STM32H753xx HAL User Manual: STM32H7xx HAL Drivers

STM32H753xx HAL User Manual
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STM32H7xx HAL Drivers

HAL Drivers User Manual

This document contains the User Manual (UM) of the STM32H753xx HAL (Hardware Abstraction Layer) drivers.

Document tabsheets description:

  • "Modules" : List the different modules.
  • "Files" : List all the files and globals.
  • "Directories" : Firmware Directory hierarchy.
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization/de-initialization functions

  • Data Structures
  • Files
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Functions
Initialization/de-initialization functions

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initialize the CRC MSP.
void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.

Function Documentation

HAL_StatusTypeDef HAL_CRC_DeInit ( CRC_HandleTypeDef * hcrc )

DeInitialize the CRC peripheral.

Parameters:
hcrc,: CRC handle
Return values:
HAL status

Definition at line 195 of file stm32h7xx_hal_crc.c.

References __HAL_CRC_DR_RESET, assert_param, HAL_CRC_MspDeInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_RESET, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRC_Init ( CRC_HandleTypeDef * hcrc )

Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.

Parameters:
hcrc,: CRC handle
Return values:
HAL status

Definition at line 118 of file stm32h7xx_hal_crc.c.

References assert_param, CRC_POLYLENGTH_32B, CRC_InitTypeDef::CRCLength, DEFAULT_CRC32_POLY, DEFAULT_CRC_INITVALUE, DEFAULT_INIT_VALUE_ENABLE, DEFAULT_POLYNOMIAL_ENABLE, CRC_InitTypeDef::DefaultInitValueUse, CRC_InitTypeDef::DefaultPolynomialUse, CRC_InitTypeDef::GeneratingPolynomial, HAL_CRC_MspInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, HAL_CRC_STATE_RESET, HAL_CRCEx_Polynomial_Set(), CRC_HandleTypeDef::Init, CRC_InitTypeDef::InitValue, CRC_HandleTypeDef::InputDataFormat, CRC_InitTypeDef::InputDataInversionMode, CRC_HandleTypeDef::Instance, IS_CRC_INPUTDATA_FORMAT, IS_CRC_INPUTDATA_INVERSION_MODE, IS_CRC_OUTPUTDATA_INVERSION_MODE, IS_DEFAULT_INIT_VALUE, IS_DEFAULT_POLYNOMIAL, CRC_HandleTypeDef::Lock, CRC_InitTypeDef::OutputDataInversionMode, and CRC_HandleTypeDef::State.

void HAL_CRC_MspDeInit ( CRC_HandleTypeDef * hcrc )

DeInitialize the CRC MSP.

Parameters:
hcrc,: CRC handle
Return values:
None

Definition at line 254 of file stm32h7xx_hal_crc.c.

Referenced by HAL_CRC_DeInit().

void HAL_CRC_MspInit ( CRC_HandleTypeDef * hcrc )

Initialize the CRC MSP.

Parameters:
hcrc,: CRC handle
Return values:
None

Definition at line 239 of file stm32h7xx_hal_crc.c.

Referenced by HAL_CRC_Init().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions

Functions

uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.

Function Documentation

uint32_t HAL_CRC_Accumulate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.

Parameters:
hcrc,: CRC handle
pBuffer,: pointer to the input data buffer, exact input data format is provided by hcrc->InputDataFormat.
BufferLength,: input data buffer length (number of bytes if pBuffer type is * uint8_t, number of half-words if pBuffer type is * uint16_t, number of words if pBuffer type is * uint32_t).
Note:
By default, the API expects a uint32_t pointer as input buffer parameter. Input buffer pointers with other types simply need to be cast in uint32_t and the API will internally adjust its input data processing based on the handle field hcrc->InputDataFormat.
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 303 of file stm32h7xx_hal_crc.c.

References CRC_Handle_16(), CRC_Handle_8(), CRC_INPUTDATA_FORMAT_BYTES, CRC_INPUTDATA_FORMAT_HALFWORDS, CRC_INPUTDATA_FORMAT_WORDS, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::InputDataFormat, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

uint32_t HAL_CRC_Calculate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.

Parameters:
hcrc,: CRC handle
pBuffer,: pointer to the input data buffer, exact input data format is provided by hcrc->InputDataFormat.
BufferLength,: input data buffer length (number of bytes if pBuffer type is * uint8_t, number of half-words if pBuffer type is * uint16_t, number of words if pBuffer type is * uint32_t).
Note:
By default, the API expects a uint32_t pointer as input buffer parameter. Input buffer pointers with other types simply need to be cast in uint32_t and the API will internally adjust its input data processing based on the handle field hcrc->InputDataFormat.
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 361 of file stm32h7xx_hal_crc.c.

References __HAL_CRC_DR_RESET, CRC_Handle_16(), CRC_Handle_8(), CRC_INPUTDATA_FORMAT_BYTES, CRC_INPUTDATA_FORMAT_HALFWORDS, CRC_INPUTDATA_FORMAT_WORDS, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::InputDataFormat, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions

Functions

HAL_CRC_StateTypeDef HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC state.

Function Documentation

HAL_CRC_StateTypeDef HAL_CRC_GetState ( CRC_HandleTypeDef * hcrc )

Return the CRC state.

Parameters:
hcrc,: CRC handle
Return values:
HAL state

Definition at line 503 of file stm32h7xx_hal_crc.c.

References CRC_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization Functions

Functions
Initialization and de-initialization Functions
HAL Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configures the SysTick to generate an interrupt each 1 millisecond, which is clocked by the HSI (at this stage, the clock is not yet configured and thus the system is running from the internal HSI at 16 MHz).
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the systick.
__weak void | HAL_MspInit (void)
Initializes the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initializes the Flash interface the NVIC allocation and initial clock
          configuration. It initializes the systick also when timeout is needed
          and the backup domain when enabled.
      (+) de-Initializes common part of the HAL
      (+) Configure The time base source to have 1ms time base with a dedicated
          Tick interrupt priority.
        (++) Systick timer is used by default as source of time base, but user
             can eventually implement his proper time base source (a general purpose
             timer for example or other time source), keeping in mind that Time base
             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
             handled in milliseconds basis.
        (++) Time base configuration function (HAL_InitTick ()) is called automatically
             at the beginning of the program after reset by HAL_Init() or at any time
             when clock is configured, by HAL_RCC_ClockConfig().
        (++) Source of time base is configured  to generate interrupts at regular
             time intervals. Care must be taken if HAL_Delay() is called from a
             peripheral ISR process, the Tick interrupt line must have higher priority
            (numerically lower) than the peripheral interrupt. Otherwise the caller
            ISR process will be blocked.
       (++) functions affecting time base configurations are declared as __weak
             to make  override possible  in case of other  implementations in user file.

Function Documentation

HAL_StatusTypeDef HAL_DeInit ( void )

This function de-Initializes common part of the HAL and stops the systick.

This function is optional.

Return values:
HAL status

Definition at line 163 of file stm32h7xx_hal.c.

References __HAL_RCC_AHB1_FORCE_RESET, __HAL_RCC_AHB1_RELEASE_RESET, __HAL_RCC_AHB2_FORCE_RESET, __HAL_RCC_AHB2_RELEASE_RESET, __HAL_RCC_AHB3_FORCE_RESET, __HAL_RCC_AHB3_RELEASE_RESET, __HAL_RCC_AHB4_FORCE_RESET, __HAL_RCC_AHB4_RELEASE_RESET, __HAL_RCC_APB1H_FORCE_RESET, __HAL_RCC_APB1H_RELEASE_RESET, __HAL_RCC_APB1L_FORCE_RESET, __HAL_RCC_APB1L_RELEASE_RESET, __HAL_RCC_APB2_FORCE_RESET, __HAL_RCC_APB2_RELEASE_RESET, __HAL_RCC_APB3_FORCE_RESET, __HAL_RCC_APB3_RELEASE_RESET, __HAL_RCC_APB4_FORCE_RESET, __HAL_RCC_APB4_RELEASE_RESET, and HAL_MspDeInit().

HAL_StatusTypeDef HAL_Init ( void )

This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configures the SysTick to generate an interrupt each 1 millisecond, which is clocked by the HSI (at this stage, the clock is not yet configured and thus the system is running from the internal HSI at 16 MHz).

Set NVIC Group Priority to 4. Calls the HAL_MspInit() callback function defined in user file "stm32h7xx_hal_msp.c" to do the global low level hardware initialization

Note:
SysTick is used as time base for the HAL_Delay() function, the application need to ensure that the SysTick time base is always set to 1 millisecond to have correct HAL operation.
Return values:
HAL status

Definition at line 142 of file stm32h7xx_hal.c.

References HAL_InitTick(), HAL_MspInit(), HAL_NVIC_SetPriorityGrouping(), NVIC_PRIORITYGROUP_4, and TICK_INT_PRIORITY.

HAL_StatusTypeDef HAL_InitTick ( uint32_t TickPriority )

This function configures the source of the time base.

The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.

Note:
This function is called automatically at the beginning of program after reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
In the default implementation, SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Care must be taken if HAL_Delay() is called from a peripheral ISR process, The the SysTick interrupt must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. The function is declared as __weak to be overwritten in case of other implementation in user file.
Parameters:
TickPriority,: Tick interrupt priority.
Return values:
HAL status

Definition at line 238 of file stm32h7xx_hal.c.

References HAL_NVIC_SetPriority(), and HAL_SYSTICK_Config().

Referenced by HAL_Init(), and HAL_RCC_ClockConfig().

void HAL_MspDeInit ( void )

DeInitializes the MSP.

Return values:
None

Definition at line 215 of file stm32h7xx_hal.c.

Referenced by HAL_DeInit().

void HAL_MspInit ( void )

Initializes the MSP.

Return values:
None

Definition at line 204 of file stm32h7xx_hal.c.

Referenced by HAL_Init().

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HAL Control functions

Functions
HAL Control functions
HAL Exported Functions

HAL Control functions. More...

Functions

__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
__weak void | HAL_Delay (__IO uint32_t Delay)
This function provides accurate delay (in milliseconds) based on variable incremented.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
void | HAL_SYSCFG_VREFBUF_VoltageScalingConfig (uint32_t VoltageScaling)
Configure the internal voltage reference buffer voltage scale.
void | HAL_SYSCFG_VREFBUF_HighImpedanceConfig (uint32_t Mode)
Configure the internal voltage reference buffer high impedance mode.
void | HAL_SYSCFG_VREFBUF_TrimmingConfig (uint32_t TrimmingValue)
Tune the Internal Voltage Reference buffer (VREFBUF).
HAL_StatusTypeDef | HAL_SYSCFG_EnableVREFBUF (void)
Enable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_DisableVREFBUF (void)
Disable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_ETHInterfaceSelect (uint32_t SYSCFG_ETHInterface)
Ethernet PHY Interface Selection either MII or RMII.
void | HAL_SYSCFG_AnalogSwitchConfig (uint32_t SYSCFG_AnalogSwitch, uint32_t SYSCFG_SwitchState)
Analog Switch control for dual analog pads.
void | HAL_SYSCFG_EnableBOOST (void)
Enables the booster to reduce the total harmonic distortion of the analog switch when the supply voltage is lower than 2.7 V.
void | HAL_SYSCFG_DisableBOOST (void)
Disables the booster.
void | HAL_SYSCFG_CM7BootAddConfig (uint32_t BootRegister, uint32_t BootAddress)
BootCM7 address 0 configuration.
void | HAL_EnableCompensationCell (void)
Enables the I/O Compensation Cell.
void | HAL_DisableCompensationCell (void)
Power-down the I/O Compensation Cell.
void | HAL_SYSCFG_EnableIOSpeedOptimize (void)
To Enable optimize the I/O speed when the product voltage is low.
void | HAL_SYSCFG_DisableIOSpeedOptimize (void)
To Disable optimize the I/O speed when the product voltage is low.
void | HAL_SYSCFG_CompensationCodeSelect (uint32_t SYSCFG_CompCode)
Code selection for the I/O Compensation cell.
void | HAL_SYSCFG_CompensationCodeConfig (uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode)
Code selection for the I/O Compensation cell.
void | HAL_EnableDBGSleepMode (void)
Enable the Debug Module during Domain1 SLEEP mode.
void | HAL_DisableDBGSleepMode (void)
Disable the Debug Module during Domain1 SLEEP mode.
void | HAL_EnableDBGStopMode (void)
Enable the Debug Module during Domain1 STOP mode.
void | HAL_DisableDBGStopMode (void)
Disable the Debug Module during Domain1 STOP mode.
void | HAL_EnableDBGStandbyMode (void)
Enable the Debug Module during Domain1 STANDBY mode.
void | HAL_DisableDBGStandbyMode (void)
Disable the Debug Module during Domain1 STANDBY mode.
void | HAL_EnableDomain3DBGStopMode (void)
Enable the Debug Module during Domain3 STOP mode.
void | HAL_DisableDomain3DBGStopMode (void)
Disable the Debug Module during Domain3 STOP mode.
void | HAL_EnableDomain3DBGStandbyMode (void)
Enable the Debug Module during Domain3 STANDBY mode.
void | HAL_DisableDomain3DBGStandbyMode (void)
Disable the Debug Module during Domain3 STANDBY mode.
void | HAL_SetFMCMemorySwappingConfig (uint32_t BankMapConfig)
Set the FMC Memory Mapping Swapping config.
uint32_t | HAL_GetFMCMemorySwappingConfig (void)
Get FMC Bank mapping mode.
void | HAL_EXTI_EdgeConfig (uint32_t EXTI_Line, uint32_t EXTI_Edge)
Configure the EXTI input event line edge.
void | HAL_EXTI_GenerateSWInterrupt (uint32_t EXTI_Line)
Generates a Software interrupt on selected EXTI line.
void | HAL_EXTI_D1_ClearFlag (uint32_t EXTI_Line)
Clears the EXTI's line pending flags for Domain D1.
void | HAL_EXTI_D1_EventInputConfig (uint32_t EXTI_Line, uint32_t EXTI_Mode, uint32_t EXTI_LineCmd)
Configure the EXTI input event line for Domain D1.
void | HAL_EXTI_D3_EventInputConfig (uint32_t EXTI_Line, uint32_t EXTI_LineCmd, uint32_t EXTI_ClearSrc)
Configure the EXTI input event line for Domain D3.

Detailed Description

HAL Control functions.

 ===============================================================================
                      ##### HAL Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Provide a tick value in millisecond
      (+) Provide a blocking delay in millisecond
      (+) Suspend the time base source interrupt
      (+) Resume the time base source interrupt
      (+) Get the HAL API driver version
      (+) Get the device identifier
      (+) Get the device revision identifier
      (+) Enable/Disable Debug module during SLEEP mode
      (+) Enable/Disable Debug module during STOP mode
      (+) Enable/Disable Debug module during STANDBY mode

Function Documentation

void HAL_Delay ( __IO uint32_t Delay )

This function provides accurate delay (in milliseconds) based on variable incremented.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals where uwTick is incremented.
ThiS function is declared as __weak to be overwritten in case of other implementations in user file.
Parameters:
Delay,: specifies the delay time length, in milliseconds.
Return values:
None

Definition at line 313 of file stm32h7xx_hal.c.

References HAL_GetTick().

Referenced by HAL_DAC_ConfigChannel(), HAL_DACEx_SelfCalibrate(), HAL_OPAMP_SelfCalibrate(), HAL_OPAMPEx_SelfCalibrateAll(), and HAL_PCDEx_BCD_VBUSDetect().

void HAL_DisableCompensationCell ( void )

Power-down the I/O Compensation Cell.

Note:
The I/O compensation cell can be used only when the device supply voltage ranges from 2.4 to 3.6 V.
Return values:
None

Definition at line 585 of file stm32h7xx_hal.c.

void HAL_DisableDBGSleepMode ( void )

Disable the Debug Module during Domain1 SLEEP mode.

Return values:
None

Definition at line 662 of file stm32h7xx_hal.c.

void HAL_DisableDBGStandbyMode ( void )

Disable the Debug Module during Domain1 STANDBY mode.

Return values:
None

Definition at line 698 of file stm32h7xx_hal.c.

void HAL_DisableDBGStopMode ( void )

Disable the Debug Module during Domain1 STOP mode.

Return values:
None

Definition at line 680 of file stm32h7xx_hal.c.

void HAL_DisableDomain3DBGStandbyMode ( void )

Disable the Debug Module during Domain3 STANDBY mode.

Return values:
None

Definition at line 734 of file stm32h7xx_hal.c.

void HAL_DisableDomain3DBGStopMode ( void )

Disable the Debug Module during Domain3 STOP mode.

Return values:
None

Definition at line 716 of file stm32h7xx_hal.c.

void HAL_EnableCompensationCell ( void )

Enables the I/O Compensation Cell.

Note:
The I/O compensation cell can be used only when the device supply voltage ranges from 2.4 to 3.6 V.
Return values:
None

Definition at line 574 of file stm32h7xx_hal.c.

void HAL_EnableDBGSleepMode ( void )

Enable the Debug Module during Domain1 SLEEP mode.

Return values:
None

Definition at line 653 of file stm32h7xx_hal.c.

void HAL_EnableDBGStandbyMode ( void )

Enable the Debug Module during Domain1 STANDBY mode.

Return values:
None

Definition at line 689 of file stm32h7xx_hal.c.

void HAL_EnableDBGStopMode ( void )

Enable the Debug Module during Domain1 STOP mode.

Return values:
None

Definition at line 671 of file stm32h7xx_hal.c.

void HAL_EnableDomain3DBGStandbyMode ( void )

Enable the Debug Module during Domain3 STANDBY mode.

Return values:
None

Definition at line 725 of file stm32h7xx_hal.c.

void HAL_EnableDomain3DBGStopMode ( void )

Enable the Debug Module during Domain3 STOP mode.

Return values:
None

Definition at line 707 of file stm32h7xx_hal.c.

void HAL_EXTI_D1_ClearFlag ( uint32_t EXTI_Line )

Clears the EXTI's line pending flags for Domain D1.

Parameters:
EXTI_Line,: Specifies the EXTI LINE, it can be one of the following values, (EXTI_LINE0....EXTI_LINE87)excluding :line45,line46 and line77 to line84 which are reserved
Return values:
None

Definition at line 815 of file stm32h7xx_hal.c.

References assert_param, and IS_EXTI_D1_LINE.

void HAL_EXTI_D1_EventInputConfig | ( | uint32_t | EXTI_Line,
 |  | uint32_t | EXTI_Mode,
 |  | uint32_t | EXTI_LineCmd
 | ) |  |

Configure the EXTI input event line for Domain D1.

Parameters:
EXTI_Line,: Specifies the EXTI LINE, it can be one of the following values, (EXTI_LINE0 to EXTI_LINE87)excluding :line45,line46 and line77 to line84 which are reserved
EXTI_Mode,: Specifies which EXTI line is used as interrupt or an event. This parameter can be one or a combination of the following values :
  • EXTI_MODE_IT : Interrupt Mode selected
  • EXTI_MODE_EVT : Event Mode selected
EXTI_LineCmd controls (Enable/Disable) the EXTI line.
Return values:
None

Definition at line 835 of file stm32h7xx_hal.c.

References assert_param, EXTI_MODE_EVT, EXTI_MODE_IT, IS_EXTI_D1_LINE, and IS_EXTI_MODE_LINE.

void HAL_EXTI_D3_EventInputConfig | ( | uint32_t | EXTI_Line,
 |  | uint32_t | EXTI_LineCmd,
 |  | uint32_t | EXTI_ClearSrc
 | ) |  |

Configure the EXTI input event line for Domain D3.

Parameters:
EXTI_Line,: Specifies the EXTI LINE, it can be one of the following values, (EXTI_LINE0 to EXTI_LINE15),(EXTI_LINE19 to EXTI_LINE21),EXTI_LINE25, EXTI_LINE34, EXTI_LINE35,EXTI_LINE41,(EXTI_LINE48 to EXTI_LINE53)
EXTI_LineCmd controls (Enable/Disable) the EXTI line.
EXTI_ClearSrc,: Specifies the clear source of D3 pending event. This parameter can be one of the following values :
  • BDMA_CH6_CLEAR : BDMA ch6 event selected as D3 domain pendclear source
  • BDMA_CH7_CLEAR : BDMA ch7 event selected as D3 domain pendclear source
  • LPTIM4_OUT_CLEAR : LPTIM4 out selected as D3 domain pendclear source
  • LPTIM5_OUT_CLEAR : LPTIM5 out selected as D3 domain pendclear source
Return values:
None

Definition at line 883 of file stm32h7xx_hal.c.

References assert_param, IS_EXTI_D3_CLEAR, and IS_EXTI_D3_LINE.

void HAL_EXTI_EdgeConfig | ( | uint32_t | EXTI_Line,
 |  | uint32_t | EXTI_Edge
 | ) |  |

Configure the EXTI input event line edge.

Note:
No edge configuration for direct lines but for configurable lines:(EXTI_LINE0..EXTI_LINE21), EXTI_LINE49,EXTI_LINE51,EXTI_LINE85 and EXTI_LINE86.
Parameters:
EXTI_Line,: Specifies the EXTI LINE, it can be one of the following values, (EXTI_LINE0....EXTI_LINE87)excluding :line45,line46 and line77 to line84 which are reserved
EXTI_Edge,: Specifies EXTI line Edge used. This parameter can be one of the following values :
  • EXTI_RISING_EDGE : Configurable line, with Rising edge trigger detection
  • EXTI_FALLING_EDGE: Configurable line, with Falling edge trigger detection
Return values:
None

Definition at line 774 of file stm32h7xx_hal.c.

References assert_param, EXTI_FALLING_EDGE, EXTI_RISING_EDGE, IS_EXTI_CONFIG_LINE, and IS_EXTI_EDGE_LINE.

void HAL_EXTI_GenerateSWInterrupt ( uint32_t EXTI_Line )

Generates a Software interrupt on selected EXTI line.

Parameters:
EXTI_Line,: Specifies the EXTI LINE, it can be one of the following values, (EXTI_LINE0..EXTI_LINE21),EXTI_LINE49,EXTI_LINE51,EXTI_LINE85 and EXTI_LINE86.
Return values:
None

Definition at line 800 of file stm32h7xx_hal.c.

References assert_param, and IS_EXTI_CONFIG_LINE.

uint32_t HAL_GetDEVID ( void )

Returns the device identifier.

Return values:
Device identifier

Definition at line 376 of file stm32h7xx_hal.c.

References IDCODE_DEVID_MASK.

uint32_t HAL_GetFMCMemorySwappingConfig ( void )

Get FMC Bank mapping mode.

Return values:
The FMC Bank mapping mode. This parameter can be FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2

Definition at line 757 of file stm32h7xx_hal.c.

uint32_t HAL_GetHalVersion ( void )

Returns the HAL revision.

Return values:
version : 0xXYZR (8bits for each decimal, R for RC)

Definition at line 358 of file stm32h7xx_hal.c.

References __STM32H7xx_HAL_VERSION.

uint32_t HAL_GetREVID ( void )

Returns the device revision identifier.

Return values:
Device revision identifier

Definition at line 367 of file stm32h7xx_hal.c.

uint32_t HAL_GetTick ( void )

Provides a tick value in millisecond.

Note:
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
tick value

Definition at line 297 of file stm32h7xx_hal.c.

References uwTick.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_Enable(), CRYP_AESCCM_Process(), CRYP_AESGCM_Process(), CRYP_WaitOnBUSYFlag(), CRYP_WaitOnIFEMFlag(), CRYP_WaitOnOFNEFlag(), FLASH_OB_WaitForLastOperation(), FLASH_WaitForLastOperation(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), HAL_CRYPEx_AESGCM_GenerateAuthTAG(), HAL_DAC_ConfigChannel(), HAL_Delay(), HAL_DFSDM_ChannelCkabStart(), HAL_DFSDM_ChannelCkabStart_IT(), HAL_DFSDM_ChannelPollForCkab(), HAL_DFSDM_ChannelPollForScd(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DMA2D_Abort(), HAL_DMA2D_CLUTLoading_Abort(), HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_PollForTransfer(), HAL_DMA2D_Suspend(), HAL_DMA_Abort(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), HAL_ETH_Init(), HAL_ETH_ReadPHYRegister(), HAL_ETH_Transmit(), HAL_ETH_WritePHYRegister(), HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_Init(), HAL_FDCAN_TT_ConfigOperation(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), HAL_I2S_Receive(), HAL_I2S_Transmit(), HAL_I2SEx_TransmitReceive(), HAL_IRDA_Receive(), HAL_IRDA_Transmit(), HAL_IWDG_Init(), HAL_JPEG_Abort(), HAL_JPEG_Decode(), HAL_JPEG_Encode(), HAL_MDMA_Abort(), HAL_MDMA_Init(), HAL_MDMA_PollForTransfer(), HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks(), HAL_MMC_WriteBlocks(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), HAL_NAND_Write_SpareArea_8b(), HAL_NOR_GetStatus(), HAL_PCDEx_BCD_VBUSDetect(), HAL_PWREx_ConfigSupply(), HAL_PWREx_ControlVoltageScaling(), HAL_PWREx_DisableBkUpReg(), HAL_PWREx_DisableUSBReg(), HAL_PWREx_EnableBkUpReg(), HAL_PWREx_EnableUSBReg(), HAL_QSPI_Abort(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_Init(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Transmit(), HAL_RCC_ClockConfig(), HAL_RCC_OscConfig(), HAL_RCCEx_CRSWaitSynchronization(), HAL_RCCEx_PeriphCLKConfig(), HAL_RNG_GenerateRandomNumber(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_PollForAlarmBEvent(), HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_SAI_Receive(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_WriteBlocks(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Transmit(), HAL_SMBUS_IsDeviceReady(), HAL_SPDIFRX_ReceiveControlFlow(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), HAL_SPI_Abort(), HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), HAL_SWPMI_Init(), HAL_SWPMI_Receive(), HAL_SWPMI_Transmit(), HAL_SYSCFG_EnableVREFBUF(), HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), HASH_WaitOnFlagUntilTimeout(), I2C_IsAcknowledgeFailed(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), I2S_WaitFlagStateUntilTimeout(), I2SEx_WaitFlagStateUntilTimeout(), IRDA_CheckIdleState(), IRDA_WaitOnFlagUntilTimeout(), MMC_ReadExtCSD(), QSPI_WaitFlagStateUntilTimeout(), RCCEx_PLL2_Config(), RCCEx_PLL3_Config(), RTC_EnterInitMode(), SD_FindSCR(), SD_HighSpeed(), SD_PowerON(), SD_SendSDStatus(), SMARTCARD_CheckIdleState(), SMARTCARD_WaitOnFlagUntilTimeout(), SMBUS_WaitOnFlagUntilTimeout(), SPDIFRX_WaitOnFlagUntilTimeout(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), SWPMI_DMATransmitCplt(), SWPMI_WaitOnFlagSetUntilTimeout(), UART_CheckIdleState(), UART_WaitOnFlagUntilTimeout(), USART_CheckIdleState(), and USART_WaitOnFlagUntilTimeout().

void HAL_IncTick ( void )

This function is called to increment a global variable "uwTick" used as application time base.

Note:
In the default implementation, this variable is incremented each 1ms in Systick ISR.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 286 of file stm32h7xx_hal.c.

References uwTick.

void HAL_ResumeTick ( void )

Resume Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_ResumeTick() is called, the the SysTick interrupt will be enabled and so Tick increment is resumed.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 348 of file stm32h7xx_hal.c.

void HAL_SetFMCMemorySwappingConfig ( uint32_t BankMapConfig )

Set the FMC Memory Mapping Swapping config.

Parameters:
BankMapConfig,: Defines the FMC Bank mapping configuration. This parameter can be FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
Return values:
HAL state

Definition at line 745 of file stm32h7xx_hal.c.

References assert_param, and IS_FMC_SWAPBMAP_MODE.

void HAL_SuspendTick ( void )

Suspend Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_SuspendTick() is called, the the SysTick interrupt will be disabled and so Tick increment is suspended.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 332 of file stm32h7xx_hal.c.

void HAL_SYSCFG_AnalogSwitchConfig | ( | uint32_t | SYSCFG_AnalogSwitch,
 |  | uint32_t | SYSCFG_SwitchState
 | ) |  |

Analog Switch control for dual analog pads.

Parameters:
SYSCFG_AnalogSwitch,: Selects the analog pad This parameter can be one or a combination of the following values:
  • SYSCFG_SWITCH_PA0 : Select PA0 analog switch
  • SYSCFG_SWITCH_PA1: Select PA1 analog switch
  • SYSCFG_SWITCH_PC2 : Select PC2 analog switch
  • SYSCFG_SWITCH_PC3: Select PC3 analog switch
SYSCFG_SwitchState,: Open or Close the analog switch between dual pads (PXn and PXn_C) This parameter can be one or a combination of the following values:
  • SYSCFG_SWITCH_PA0_OPEN
  • SYSCFG_SWITCH_PA0_CLOSE
  • SYSCFG_SWITCH_PA1_OPEN
  • SYSCFG_SWITCH_PA1_CLOSE
  • SYSCFG_SWITCH_PC2_OPEN
  • SYSCFG_SWITCH_PC2_CLOSE
  • SYSCFG_SWITCH_PC3_OPEN
  • SYSCFG_SWITCH_PC3_CLOSE
Return values:
None

Definition at line 504 of file stm32h7xx_hal.c.

References assert_param, IS_SYSCFG_ANALOG_SWITCH, and IS_SYSCFG_SWITCH_STATE.

void HAL_SYSCFG_CM7BootAddConfig | ( | uint32_t | BootRegister,
 |  | uint32_t | BootAddress
 | ) |  |

BootCM7 address 0 configuration.

Parameters:
BootRegister :Specifies the Boot Address register (Address0 or Address1) This parameter can be one of the following values:
  • SYSCFG_BOOT_ADDR0 : Select the boot address0
  • SYSCFG_BOOT_ADDR1: Select the boot address1
BootAddress :Specifies the CM7 Boot Address to be loaded in Address0 or Address1
Return values:
None

Definition at line 549 of file stm32h7xx_hal.c.

References assert_param, IS_SYSCFG_BOOT_ADDRESS, IS_SYSCFG_BOOT_REGISTER, and SYSCFG_BOOT_ADDR0.

void HAL_SYSCFG_CompensationCodeConfig | ( | uint32_t | SYSCFG_PMOSCode,
 |  | uint32_t | SYSCFG_NMOSCode
 | ) |  |

Code selection for the I/O Compensation cell.

Parameters:
SYSCFG_PMOSCode,: PMOS compensation code This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CMPCR is set
SYSCFG_NMOSCode,: NMOS compensation code This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CMPCR is set
Return values:
None

Definition at line 640 of file stm32h7xx_hal.c.

References assert_param, and IS_SYSCFG_CODE_CONFIG.

void HAL_SYSCFG_CompensationCodeSelect ( uint32_t SYSCFG_CompCode )

Code selection for the I/O Compensation cell.

Parameters:
SYSCFG_CompCode,: Selects the code to be applied for the I/O compensation cell This parameter can be one of the following values:
  • SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
  • SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
Return values:
None

Definition at line 623 of file stm32h7xx_hal.c.

References assert_param, and IS_SYSCFG_CODE_SELECT.

void HAL_SYSCFG_DisableBOOST ( void )

Disables the booster.

Note:
Activating the booster allows to guaranty the analog switch AC performance when the supply voltage is below 2.7 V: in this case, the analog switch performance is the same on the full voltage range
Return values:
None

Definition at line 534 of file stm32h7xx_hal.c.

void HAL_SYSCFG_DisableIOSpeedOptimize ( void )

To Disable optimize the I/O speed when the product voltage is low.

Note:
This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is higher than 2.5 V might be destructive.
Return values:
None

Definition at line 610 of file stm32h7xx_hal.c.

void HAL_SYSCFG_DisableVREFBUF ( void )

Disable the Internal Voltage Reference buffer (VREFBUF).

Return values:
None

Definition at line 461 of file stm32h7xx_hal.c.

void HAL_SYSCFG_EnableBOOST ( void )

Enables the booster to reduce the total harmonic distortion of the analog switch when the supply voltage is lower than 2.7 V.

Note:
Activating the booster allows to guaranty the analog switch AC performance when the supply voltage is below 2.7 V: in this case, the analog switch performance is the same on the full voltage range
Return values:
None

Definition at line 522 of file stm32h7xx_hal.c.

void HAL_SYSCFG_EnableIOSpeedOptimize ( void )

To Enable optimize the I/O speed when the product voltage is low.

Note:
This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is higher than 2.5 V might be destructive.
Return values:
None

Definition at line 598 of file stm32h7xx_hal.c.

HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF ( void )

Enable the Internal Voltage Reference buffer (VREFBUF).

Return values:
HAL_OK/HAL_TIMEOUT

Definition at line 435 of file stm32h7xx_hal.c.

References HAL_GetTick(), and VREFBUF_TIMEOUT_VALUE.

void HAL_SYSCFG_ETHInterfaceSelect ( uint32_t SYSCFG_ETHInterface )

Ethernet PHY Interface Selection either MII or RMII.

Parameters:
SYSCFG_ETHInterface,: Selects the Ethernet PHY interface This parameter can be one of the following values:
  • SYSCFG_ETH_MII : Select the Media Independent Interface
  • SYSCFG_ETH_RMII: Select the Reduced Media Independent Interface
Return values:
None

Definition at line 474 of file stm32h7xx_hal.c.

References assert_param, and IS_SYSCFG_ETHERNET_CONFIG.

Referenced by HAL_ETH_Init().

void HAL_SYSCFG_VREFBUF_HighImpedanceConfig ( uint32_t Mode )

Configure the internal voltage reference buffer high impedance mode.

Parameters:
Mode specifies the high impedance mode This parameter can be one of the following values:
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
Return values:
None

Definition at line 411 of file stm32h7xx_hal.c.

References assert_param, and IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE.

void HAL_SYSCFG_VREFBUF_TrimmingConfig ( uint32_t TrimmingValue )

Tune the Internal Voltage Reference buffer (VREFBUF).

Return values:
None

Definition at line 423 of file stm32h7xx_hal.c.

References assert_param, and IS_SYSCFG_VREFBUF_TRIMMING.

void HAL_SYSCFG_VREFBUF_VoltageScalingConfig ( uint32_t VoltageScaling )

Configure the internal voltage reference buffer voltage scale.

Parameters:
VoltageScaling specifies the output voltage to achieve This parameter can be one of the following values:
  • SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V. This requires VDDA equal to or higher than 2.4 V.
  • SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V. This requires VDDA equal to or higher than 2.8 V.
  • SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.5 V. This requires VDDA equal to or higher than 1.8 V.
  • SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.8 V. This requires VDDA equal to or higher than 2.1 V.
Return values:
None

Definition at line 395 of file stm32h7xx_hal.c.

References assert_param, and IS_SYSCFG_VREFBUF_VOLTAGE_SCALE.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: VREFBUF Voltage Scale

Defines
VREFBUF Voltage Scale
HAL Exported Constants

Defines

#define | SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT2
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT1
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT4
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT3

Define Documentation

#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT2

Voltage reference scale 0 (VREF_OUT2)

Definition at line 67 of file stm32h7xx_hal.h.

#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT1

Voltage reference scale 1 (VREF_OUT1)

Definition at line 68 of file stm32h7xx_hal.h.

#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT4

Voltage reference scale 2 (VREF_OUT4)

Definition at line 69 of file stm32h7xx_hal.h.

#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT3

Voltage reference scale 3 (VREF_OUT3)

Definition at line 70 of file stm32h7xx_hal.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: VREFBUF High Impedance

Defines
VREFBUF High Impedance
HAL Exported Constants

Defines

#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000)
#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ

Define Documentation

#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000)

VREF_plus pin is internally connected to Voltage reference buffer output

Definition at line 80 of file stm32h7xx_hal.h.

#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ

VREF_plus pin is high impedance

Definition at line 81 of file stm32h7xx_hal.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Ethernet Config

Defines
Ethernet Config
HAL Exported Constants

Defines

#define | SYSCFG_ETH_MII ((uint32_t)0x00000000)
#define | SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2

Define Documentation

#define SYSCFG_ETH_MII ((uint32_t)0x00000000)

Select the Media Independent Interface

Definition at line 92 of file stm32h7xx_hal.h.

Referenced by HAL_ETH_Init().

#define SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2

Select the Reduced Media Independent Interface

Definition at line 93 of file stm32h7xx_hal.h.

Referenced by HAL_ETH_Init().

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Analog Switch Config

Defines
Analog Switch Config
HAL Exported Constants

Defines

#define | SYSCFG_SWITCH_PA0 SYSCFG_PMCR_PA0SO
#define | SYSCFG_SWITCH_PA1 SYSCFG_PMCR_PA1SO
#define | SYSCFG_SWITCH_PC2 SYSCFG_PMCR_PC2SO
#define | SYSCFG_SWITCH_PC3 SYSCFG_PMCR_PC3SO
#define | SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCR_PA0SO
#define | SYSCFG_SWITCH_PA0_CLOSE ((uint32_t)0x00000000)
#define | SYSCFG_SWITCH_PA1_OPEN SYSCFG_PMCR_PA1SO
#define | SYSCFG_SWITCH_PA1_CLOSE ((uint32_t)0x00000000)
#define | SYSCFG_SWITCH_PC2_OPEN SYSCFG_PMCR_PC2SO
#define | SYSCFG_SWITCH_PC2_CLOSE ((uint32_t)0x00000000)
#define | SYSCFG_SWITCH_PC3_OPEN SYSCFG_PMCR_PC3SO
#define | SYSCFG_SWITCH_PC3_CLOSE ((uint32_t)0x00000000)

Define Documentation

#define SYSCFG_SWITCH_PA0 SYSCFG_PMCR_PA0SO

Select PA0 analog switch

Definition at line 104 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PA0_CLOSE ((uint32_t)0x00000000)

PA0 analog switch closed

Definition at line 112 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCR_PA0SO

PA0 analog switch opened

Definition at line 111 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PA1 SYSCFG_PMCR_PA1SO

Select PA1 analog switch

Definition at line 105 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PA1_CLOSE ((uint32_t)0x00000000)

PA1 analog switch closed

Definition at line 114 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PA1_OPEN SYSCFG_PMCR_PA1SO

PA1 analog switch opened

Definition at line 113 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PC2 SYSCFG_PMCR_PC2SO

Select PC2 analog switch

Definition at line 106 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PC2_CLOSE ((uint32_t)0x00000000)

PC2 analog switch closed

Definition at line 116 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PC2_OPEN SYSCFG_PMCR_PC2SO

PC2 analog switch opened

Definition at line 115 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PC3 SYSCFG_PMCR_PC3SO

Select PC3 analog switch

Definition at line 107 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PC3_CLOSE ((uint32_t)0x00000000)

PC3 analog switch closed

Definition at line 118 of file stm32h7xx_hal.h.

#define SYSCFG_SWITCH_PC3_OPEN SYSCFG_PMCR_PC3SO

PC3 analog switch opened

Definition at line 117 of file stm32h7xx_hal.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Boot Config

Defines
Boot Config
HAL Exported Constants

Defines

#define | SYSCFG_BOOT_ADDR0 ((uint32_t)0x00000000)
#define | SYSCFG_BOOT_ADDR1 ((uint32_t)0x00000001)

Define Documentation

#define SYSCFG_BOOT_ADDR0 ((uint32_t)0x00000000)

Select Boot address0

Definition at line 128 of file stm32h7xx_hal.h.

Referenced by HAL_SYSCFG_CM7BootAddConfig().

#define SYSCFG_BOOT_ADDR1 ((uint32_t)0x00000001)

Select Boot address1

Definition at line 129 of file stm32h7xx_hal.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IOCompenstionCell Config

Defines
IOCompenstionCell Config
HAL Exported Constants

Defines

#define | SYSCFG_CELL_CODE ((uint32_t)0x00000000)
#define | SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS

Define Documentation

#define SYSCFG_CELL_CODE ((uint32_t)0x00000000)

Select Code from the cell

Definition at line 141 of file stm32h7xx_hal.h.

#define SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS

Code from the SYSCFG compensation cell code register

Definition at line 142 of file stm32h7xx_hal.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Event Input Config

Defines
Event Input Config
HAL Exported Constants

Defines

#define | EXTI_MODE_IT ((uint32_t)0x00010000)
#define | EXTI_MODE_EVT ((uint32_t)0x00020000)
#define | EXTI_RISING_EDGE ((uint32_t)0x00100000)
#define | EXTI_FALLING_EDGE ((uint32_t)0x00200000)
#define | EXTI_LINE0 ((uint32_t)0x00)
#define | EXTI_LINE1 ((uint32_t)0x01)
#define | EXTI_LINE2 ((uint32_t)0x02)
#define | EXTI_LINE3 ((uint32_t)0x03)
#define | EXTI_LINE4 ((uint32_t)0x04)
#define | EXTI_LINE5 ((uint32_t)0x05)
#define | EXTI_LINE6 ((uint32_t)0x06)
#define | EXTI_LINE7 ((uint32_t)0x07)
#define | EXTI_LINE8 ((uint32_t)0x08)
#define | EXTI_LINE9 ((uint32_t)0x09)
#define | EXTI_LINE10 ((uint32_t)0x0A)
#define | EXTI_LINE11 ((uint32_t)0x0B)
#define | EXTI_LINE12 ((uint32_t)0x0C)
#define | EXTI_LINE13 ((uint32_t)0x0D)
#define | EXTI_LINE14 ((uint32_t)0x0E)
#define | EXTI_LINE15 ((uint32_t)0x0F)
#define | EXTI_LINE16 ((uint32_t)0x10)
#define | EXTI_LINE17 ((uint32_t)0x11)
#define | EXTI_LINE18 ((uint32_t)0x12)
#define | EXTI_LINE19 ((uint32_t)0x13)
#define | EXTI_LINE20 ((uint32_t)0x14)
#define | EXTI_LINE21 ((uint32_t)0x15)
#define | EXTI_LINE22 ((uint32_t)0x16)
#define | EXTI_LINE23 ((uint32_t)0x17)
#define | EXTI_LINE24 ((uint32_t)0x18)
#define | EXTI_LINE25 ((uint32_t)0x19)
#define | EXTI_LINE26 ((uint32_t)0x1A)
#define | EXTI_LINE27 ((uint32_t)0x1B)
#define | EXTI_LINE28 ((uint32_t)0x1C)
#define | EXTI_LINE29 ((uint32_t)0x1D)
#define | EXTI_LINE30 ((uint32_t)0x1E)
#define | EXTI_LINE31 ((uint32_t)0x1F)
#define | EXTI_LINE32 ((uint32_t)0x20)
#define | EXTI_LINE33 ((uint32_t)0x21)
#define | EXTI_LINE34 ((uint32_t)0x22)
#define | EXTI_LINE35 ((uint32_t)0x23)
#define | EXTI_LINE36 ((uint32_t)0x24)
#define | EXTI_LINE37 ((uint32_t)0x25)
#define | EXTI_LINE38 ((uint32_t)0x26)
#define | EXTI_LINE39 ((uint32_t)0x27)
#define | EXTI_LINE40 ((uint32_t)0x28)
#define | EXTI_LINE41 ((uint32_t)0x29)
#define | EXTI_LINE42 ((uint32_t)0x2A)
#define | EXTI_LINE43 ((uint32_t)0x2B)
#define | EXTI_LINE44 ((uint32_t)0x2C)
#define | EXTI_LINE47 ((uint32_t)0x2F)
#define | EXTI_LINE48 ((uint32_t)0x30)
#define | EXTI_LINE49 ((uint32_t)0x31)
#define | EXTI_LINE50 ((uint32_t)0x32)
#define | EXTI_LINE51 ((uint32_t)0x33)
#define | EXTI_LINE52 ((uint32_t)0x34)
#define | EXTI_LINE53 ((uint32_t)0x35)
#define | EXTI_LINE54 ((uint32_t)0x36)
#define | EXTI_LINE55 ((uint32_t)0x37)
#define | EXTI_LINE56 ((uint32_t)0x38)
#define | EXTI_LINE57 ((uint32_t)0x39)
#define | EXTI_LINE58 ((uint32_t)0x3A)
#define | EXTI_LINE59 ((uint32_t)0x3B)
#define | EXTI_LINE60 ((uint32_t)0x3C)
#define | EXTI_LINE61 ((uint32_t)0x3D)
#define | EXTI_LINE62 ((uint32_t)0x3E)
#define | EXTI_LINE63 ((uint32_t)0x3F)
#define | EXTI_LINE64 ((uint32_t)0x40)
#define | EXTI_LINE65 ((uint32_t)0x41)
#define | EXTI_LINE66 ((uint32_t)0x42)
#define | EXTI_LINE67 ((uint32_t)0x43)
#define | EXTI_LINE68 ((uint32_t)0x44)
#define | EXTI_LINE69 ((uint32_t)0x45)
#define | EXTI_LINE70 ((uint32_t)0x46)
#define | EXTI_LINE71 ((uint32_t)0x47)
#define | EXTI_LINE72 ((uint32_t)0x48)
#define | EXTI_LINE73 ((uint32_t)0x49)
#define | EXTI_LINE74 ((uint32_t)0x4A)
#define | EXTI_LINE75 ((uint32_t)0x4B)
#define | EXTI_LINE76 ((uint32_t)0x4C)
#define | EXTI_LINE85 ((uint32_t)0x55)
#define | EXTI_LINE86 ((uint32_t)0x56)
#define | EXTI_LINE87 ((uint32_t)0x57)

Define Documentation

#define EXTI_FALLING_EDGE ((uint32_t)0x00200000)

Definition at line 156 of file stm32h7xx_hal.h.

Referenced by HAL_EXTI_EdgeConfig().

#define EXTI_LINE0 ((uint32_t)0x00)

External interrupt LINE 0

Definition at line 159 of file stm32h7xx_hal.h.

#define EXTI_LINE1 ((uint32_t)0x01)

External interrupt LINE 1

Definition at line 160 of file stm32h7xx_hal.h.

#define EXTI_LINE10 ((uint32_t)0x0A)

External interrupt LINE 10

Definition at line 169 of file stm32h7xx_hal.h.

#define EXTI_LINE11 ((uint32_t)0x0B)

External interrupt LINE 11

Definition at line 170 of file stm32h7xx_hal.h.

#define EXTI_LINE12 ((uint32_t)0x0C)

External interrupt LINE 12

Definition at line 171 of file stm32h7xx_hal.h.

#define EXTI_LINE13 ((uint32_t)0x0D)

External interrupt LINE 13

Definition at line 172 of file stm32h7xx_hal.h.

#define EXTI_LINE14 ((uint32_t)0x0E)

External interrupt LINE 14

Definition at line 173 of file stm32h7xx_hal.h.

#define EXTI_LINE15 ((uint32_t)0x0F)

External interrupt LINE 15

Definition at line 174 of file stm32h7xx_hal.h.

#define EXTI_LINE16 ((uint32_t)0x10)

Definition at line 175 of file stm32h7xx_hal.h.

#define EXTI_LINE17 ((uint32_t)0x11)

Definition at line 176 of file stm32h7xx_hal.h.

#define EXTI_LINE18 ((uint32_t)0x12)

Definition at line 177 of file stm32h7xx_hal.h.

#define EXTI_LINE19 ((uint32_t)0x13)

Definition at line 178 of file stm32h7xx_hal.h.

#define EXTI_LINE2 ((uint32_t)0x02)

External interrupt LINE 2

Definition at line 161 of file stm32h7xx_hal.h.

#define EXTI_LINE20 ((uint32_t)0x14)

Definition at line 179 of file stm32h7xx_hal.h.

#define EXTI_LINE21 ((uint32_t)0x15)

Definition at line 180 of file stm32h7xx_hal.h.

#define EXTI_LINE22 ((uint32_t)0x16)

Definition at line 181 of file stm32h7xx_hal.h.

#define EXTI_LINE23 ((uint32_t)0x17)

Definition at line 182 of file stm32h7xx_hal.h.

#define EXTI_LINE24 ((uint32_t)0x18)

Definition at line 183 of file stm32h7xx_hal.h.

#define EXTI_LINE25 ((uint32_t)0x19)

Definition at line 184 of file stm32h7xx_hal.h.

#define EXTI_LINE26 ((uint32_t)0x1A)

Definition at line 185 of file stm32h7xx_hal.h.

#define EXTI_LINE27 ((uint32_t)0x1B)

Definition at line 186 of file stm32h7xx_hal.h.

#define EXTI_LINE28 ((uint32_t)0x1C)

Definition at line 187 of file stm32h7xx_hal.h.

#define EXTI_LINE29 ((uint32_t)0x1D)

Definition at line 188 of file stm32h7xx_hal.h.

#define EXTI_LINE3 ((uint32_t)0x03)

External interrupt LINE 3

Definition at line 162 of file stm32h7xx_hal.h.

#define EXTI_LINE30 ((uint32_t)0x1E)

Definition at line 189 of file stm32h7xx_hal.h.

#define EXTI_LINE31 ((uint32_t)0x1F)

Definition at line 190 of file stm32h7xx_hal.h.

#define EXTI_LINE32 ((uint32_t)0x20)

Definition at line 191 of file stm32h7xx_hal.h.

#define EXTI_LINE33 ((uint32_t)0x21)

Definition at line 192 of file stm32h7xx_hal.h.

#define EXTI_LINE34 ((uint32_t)0x22)

Definition at line 193 of file stm32h7xx_hal.h.

#define EXTI_LINE35 ((uint32_t)0x23)

Definition at line 194 of file stm32h7xx_hal.h.

#define EXTI_LINE36 ((uint32_t)0x24)

Definition at line 195 of file stm32h7xx_hal.h.

#define EXTI_LINE37 ((uint32_t)0x25)

Definition at line 196 of file stm32h7xx_hal.h.

#define EXTI_LINE38 ((uint32_t)0x26)

Definition at line 197 of file stm32h7xx_hal.h.

#define EXTI_LINE39 ((uint32_t)0x27)

Definition at line 198 of file stm32h7xx_hal.h.

#define EXTI_LINE4 ((uint32_t)0x04)

External interrupt LINE 4

Definition at line 163 of file stm32h7xx_hal.h.

#define EXTI_LINE40 ((uint32_t)0x28)

Definition at line 200 of file stm32h7xx_hal.h.

#define EXTI_LINE41 ((uint32_t)0x29)

Definition at line 201 of file stm32h7xx_hal.h.

#define EXTI_LINE42 ((uint32_t)0x2A)

Definition at line 202 of file stm32h7xx_hal.h.

#define EXTI_LINE43 ((uint32_t)0x2B)

Definition at line 203 of file stm32h7xx_hal.h.

#define EXTI_LINE44 ((uint32_t)0x2C)

Definition at line 204 of file stm32h7xx_hal.h.

#define EXTI_LINE47 ((uint32_t)0x2F)

Definition at line 207 of file stm32h7xx_hal.h.

#define EXTI_LINE48 ((uint32_t)0x30)

Definition at line 208 of file stm32h7xx_hal.h.

#define EXTI_LINE49 ((uint32_t)0x31)

Definition at line 209 of file stm32h7xx_hal.h.

#define EXTI_LINE5 ((uint32_t)0x05)

External interrupt LINE 5

Definition at line 164 of file stm32h7xx_hal.h.

#define EXTI_LINE50 ((uint32_t)0x32)

Definition at line 211 of file stm32h7xx_hal.h.

#define EXTI_LINE51 ((uint32_t)0x33)

Definition at line 212 of file stm32h7xx_hal.h.

#define EXTI_LINE52 ((uint32_t)0x34)

Definition at line 213 of file stm32h7xx_hal.h.

#define EXTI_LINE53 ((uint32_t)0x35)

Definition at line 214 of file stm32h7xx_hal.h.

#define EXTI_LINE54 ((uint32_t)0x36)

Definition at line 215 of file stm32h7xx_hal.h.

#define EXTI_LINE55 ((uint32_t)0x37)

Definition at line 216 of file stm32h7xx_hal.h.

#define EXTI_LINE56 ((uint32_t)0x38)

Definition at line 217 of file stm32h7xx_hal.h.

#define EXTI_LINE57 ((uint32_t)0x39)

Definition at line 218 of file stm32h7xx_hal.h.

#define EXTI_LINE58 ((uint32_t)0x3A)

Definition at line 219 of file stm32h7xx_hal.h.

#define EXTI_LINE59 ((uint32_t)0x3B)

Definition at line 220 of file stm32h7xx_hal.h.

#define EXTI_LINE6 ((uint32_t)0x06)

External interrupt LINE 6

Definition at line 165 of file stm32h7xx_hal.h.

#define EXTI_LINE60 ((uint32_t)0x3C)

Definition at line 222 of file stm32h7xx_hal.h.

#define EXTI_LINE61 ((uint32_t)0x3D)

Definition at line 223 of file stm32h7xx_hal.h.

#define EXTI_LINE62 ((uint32_t)0x3E)

Definition at line 224 of file stm32h7xx_hal.h.

#define EXTI_LINE63 ((uint32_t)0x3F)

Definition at line 225 of file stm32h7xx_hal.h.

#define EXTI_LINE64 ((uint32_t)0x40)

Definition at line 226 of file stm32h7xx_hal.h.

#define EXTI_LINE65 ((uint32_t)0x41)

Definition at line 227 of file stm32h7xx_hal.h.

#define EXTI_LINE66 ((uint32_t)0x42)

Definition at line 228 of file stm32h7xx_hal.h.

#define EXTI_LINE67 ((uint32_t)0x43)

Definition at line 229 of file stm32h7xx_hal.h.

#define EXTI_LINE68 ((uint32_t)0x44)

Definition at line 230 of file stm32h7xx_hal.h.

#define EXTI_LINE69 ((uint32_t)0x45)

Definition at line 231 of file stm32h7xx_hal.h.

#define EXTI_LINE7 ((uint32_t)0x07)

External interrupt LINE 7

Definition at line 166 of file stm32h7xx_hal.h.

#define EXTI_LINE70 ((uint32_t)0x46)

Definition at line 233 of file stm32h7xx_hal.h.

#define EXTI_LINE71 ((uint32_t)0x47)

Definition at line 234 of file stm32h7xx_hal.h.

#define EXTI_LINE72 ((uint32_t)0x48)

Definition at line 235 of file stm32h7xx_hal.h.

#define EXTI_LINE73 ((uint32_t)0x49)

Definition at line 236 of file stm32h7xx_hal.h.

#define EXTI_LINE74 ((uint32_t)0x4A)

Definition at line 237 of file stm32h7xx_hal.h.

#define EXTI_LINE75 ((uint32_t)0x4B)

Definition at line 238 of file stm32h7xx_hal.h.

#define EXTI_LINE76 ((uint32_t)0x4C)

Definition at line 239 of file stm32h7xx_hal.h.

#define EXTI_LINE8 ((uint32_t)0x08)

External interrupt LINE 8

Definition at line 167 of file stm32h7xx_hal.h.

#define EXTI_LINE85 ((uint32_t)0x55)

Definition at line 250 of file stm32h7xx_hal.h.

#define EXTI_LINE86 ((uint32_t)0x56)

Definition at line 251 of file stm32h7xx_hal.h.

#define EXTI_LINE87 ((uint32_t)0x57)

Definition at line 252 of file stm32h7xx_hal.h.

#define EXTI_LINE9 ((uint32_t)0x09)

External interrupt LINE 9

Definition at line 168 of file stm32h7xx_hal.h.

#define EXTI_MODE_EVT ((uint32_t)0x00020000)

Definition at line 154 of file stm32h7xx_hal.h.

Referenced by HAL_EXTI_D1_EventInputConfig().

#define EXTI_MODE_IT ((uint32_t)0x00010000)

Definition at line 153 of file stm32h7xx_hal.h.

Referenced by HAL_EXTI_D1_EventInputConfig().

#define EXTI_RISING_EDGE ((uint32_t)0x00100000)

Definition at line 155 of file stm32h7xx_hal.h.

Referenced by HAL_EXTI_EdgeConfig().

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SwapBankMapping Config

Defines
SwapBankMapping Config
HAL Exported Constants

Defines

#define | FMC_SWAPBMAP_DISABLE (0x00000000U)
#define | FMC_SWAPBMAP_SDRAM_SRAM FMC_BCR1_BMAP_0
#define | FMC_SWAPBMAP_SDRAMB2 FMC_BCR1_BMAP_1

Define Documentation

#define FMC_SWAPBMAP_DISABLE (0x00000000U)

Definition at line 272 of file stm32h7xx_hal.h.

#define FMC_SWAPBMAP_SDRAM_SRAM FMC_BCR1_BMAP_0

Definition at line 273 of file stm32h7xx_hal.h.

#define FMC_SWAPBMAP_SDRAMB2 FMC_BCR1_BMAP_1

Definition at line 274 of file stm32h7xx_hal.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HAL Exported Constants

Modules | Defines
HAL Exported Constants
HAL

Modules

VREFBUF Voltage Scale
VREFBUF High Impedance
Ethernet Config
Analog Switch Config
Boot Config
IOCompenstionCell Config
Event Input Config
SwapBankMapping Config

Defines

#define | BDMA_CH6_CLEAR ((uint32_t)0x00000000)
#define | BDMA_CH7_CLEAR ((uint32_t)0x00000001)
#define | LPTIM4_OUT_CLEAR ((uint32_t)0x00000002)
#define | LPTIM5_OUT_CLEAR ((uint32_t)0x00000003)

Define Documentation

#define BDMA_CH6_CLEAR ((uint32_t)0x00000000)

BDMA ch6 event selected as D3 domain pendclear source

Definition at line 260 of file stm32h7xx_hal.h.

#define BDMA_CH7_CLEAR ((uint32_t)0x00000001)

BDMA ch7 event selected as D3 domain pendclear source

Definition at line 261 of file stm32h7xx_hal.h.

#define LPTIM4_OUT_CLEAR ((uint32_t)0x00000002)

LPTIM4 out selected as D3 domain pendclear source

Definition at line 262 of file stm32h7xx_hal.h.

#define LPTIM5_OUT_CLEAR ((uint32_t)0x00000003)

LPTIM5 out selected as D3 domain pendclear source

Definition at line 263 of file stm32h7xx_hal.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HAL Exported Macros

Defines
HAL Exported Macros
HAL

Defines

#define | IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)
#define | IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)
#define | IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
#define | IS_SYSCFG_ETHERNET_CONFIG(CONFIG)
#define | IS_SYSCFG_ANALOG_SWITCH(SWITCH)
#define | IS_SYSCFG_SWITCH_STATE(STATE)
#define | IS_SYSCFG_BOOT_REGISTER(REGISTER)
#define | IS_SYSCFG_BOOT_ADDRESS(ADDRESS) ((ADDRESS) < PERIPH_BASE)
#define | IS_SYSCFG_CODE_SELECT(SELECT)
#define | IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10))
#define | IS_EXTI_EDGE_LINE(EDGE) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE))
#define | IS_EXTI_MODE_LINE(MODE) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT))
#define | IS_EXTI_CONFIG_LINE(LINE)
#define | IS_EXTI_ALL_LINE(LINE)
#define | IS_EXTI_D1_LINE(LINE)
#define | IS_EXTI_D3_LINE(LINE)
#define | IS_EXTI_D3_CLEAR(SOURCE)
#define | IS_FMC_SWAPBMAP_MODE(__MODE__)
#define | __HAL_DBGMCU_FREEZE_WWDG1() (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1))
Freeze/Unfreeze Peripherals in Debug mode.
#define | __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2))
#define | __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3))
#define | __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4))
#define | __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5))
#define | __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6))
#define | __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7))
#define | __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12))
#define | __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13))
#define | __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14))
#define | __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1))
#define | __HAL_DBGMCU_FREEZE_I2C1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1))
#define | __HAL_DBGMCU_FREEZE_I2C2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2))
#define | __HAL_DBGMCU_FREEZE_I2C3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3))
#define | __HAL_DBGMCU_FREEZE_FDCAN() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN))
#define | __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1))
#define | __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8))
#define | __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15))
#define | __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16))
#define | __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17))
#define | __HAL_DBGMCU_FREEZE_HRTIM() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM))
#define | __HAL_DBGMCU_FREEZE_I2C4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4))
#define | __HAL_DBGMCU_FREEZE_LPTIM2() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2))
#define | __HAL_DBGMCU_FREEZE_LPTIM3() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3))
#define | __HAL_DBGMCU_FREEZE_LPTIM4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4))
#define | __HAL_DBGMCU_FREEZE_LPTIM5() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5))
#define | __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC))
#define | __HAL_DBGMCU_FREEZE_IWDG1() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1))
#define | __HAL_DBGMCU_UnFreeze_WWDG1() (DBGMCU->APB3FZ1 &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1))
#define | __HAL_DBGMCU_UnFreeze_TIM2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2))
#define | __HAL_DBGMCU_UnFreeze_TIM3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3))
#define | __HAL_DBGMCU_UnFreeze_TIM4() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4))
#define | __HAL_DBGMCU_UnFreeze_TIM5() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5))
#define | __HAL_DBGMCU_UnFreeze_TIM6() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6))
#define | __HAL_DBGMCU_UnFreeze_TIM7() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7))
#define | __HAL_DBGMCU_UnFreeze_TIM12() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12))
#define | __HAL_DBGMCU_UnFreeze_TIM13() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13))
#define | __HAL_DBGMCU_UnFreeze_TIM14() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14))
#define | __HAL_DBGMCU_UnFreeze_LPTIM1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1))
#define | __HAL_DBGMCU_UnFreeze_I2C1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1))
#define | __HAL_DBGMCU_UnFreeze_I2C2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2))
#define | __HAL_DBGMCU_UnFreeze_I2C3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3))
#define | __HAL_DBGMCU_UnFreeze_FDCAN() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN))
#define | __HAL_DBGMCU_UnFreeze_TIM1() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM1))
#define | __HAL_DBGMCU_UnFreeze_TIM8() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM8))
#define | __HAL_DBGMCU_UnFreeze_TIM15() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM15))
#define | __HAL_DBGMCU_UnFreeze_TIM16() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM16))
#define | __HAL_DBGMCU_UnFreeze_TIM17() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM17))
#define | __HAL_DBGMCU_UnFreeze_HRTIM() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM))
#define | __HAL_DBGMCU_UnFreeze_I2C4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_I2C4))
#define | __HAL_DBGMCU_UnFreeze_LPTIM2() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2))
#define | __HAL_DBGMCU_UnFreeze_LPTIM3() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3))
#define | __HAL_DBGMCU_UnFreeze_LPTIM4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4))
#define | __HAL_DBGMCU_UnFreeze_LPTIM5() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5))
#define | __HAL_DBGMCU_UnFreeze_RTC() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_RTC))
#define | __HAL_DBGMCU_UnFreeze_IWDG1() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1))

Define Documentation

#define __HAL_DBGMCU_FREEZE_FDCAN ( ) (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN))

Definition at line 466 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_HRTIM ( ) (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM))

Definition at line 474 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C1 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1))

Definition at line 463 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C2 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2))

Definition at line 464 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C3 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3))

Definition at line 465 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C4 ( ) (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4))

Definition at line 476 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_IWDG1 ( ) (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1))

Definition at line 482 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_LPTIM1 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1))

Definition at line 462 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_LPTIM2 ( ) (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2))

Definition at line 477 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_LPTIM3 ( ) (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3))

Definition at line 478 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_LPTIM4 ( ) (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4))

Definition at line 479 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_LPTIM5 ( ) (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5))

Definition at line 480 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_RTC ( ) (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC))

Definition at line 481 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM1 ( ) (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1))

Definition at line 469 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM12 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12))

Definition at line 459 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM13 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13))

Definition at line 460 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM14 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14))

Definition at line 461 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM15 ( ) (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15))

Definition at line 471 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM16 ( ) (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16))

Definition at line 472 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM17 ( ) (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17))

Definition at line 473 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM2 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2))

Definition at line 453 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM3 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3))

Definition at line 454 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM4 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4))

Definition at line 455 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM5 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5))

Definition at line 456 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM6 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6))

Definition at line 457 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM7 ( ) (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7))

Definition at line 458 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM8 ( ) (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8))

Definition at line 470 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_WWDG1 ( ) (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1))

Freeze/Unfreeze Peripherals in Debug mode.

Definition at line 451 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_FDCAN ( ) (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN))

Definition at line 500 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_HRTIM ( ) (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM))

Definition at line 508 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_I2C1 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1))

Definition at line 497 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_I2C2 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2))

Definition at line 498 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_I2C3 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3))

Definition at line 499 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_I2C4 ( ) (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_I2C4))

Definition at line 510 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_IWDG1 ( ) (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1))

Definition at line 516 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_LPTIM1 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1))

Definition at line 496 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_LPTIM2 ( ) (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2))

Definition at line 511 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_LPTIM3 ( ) (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3))

Definition at line 512 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_LPTIM4 ( ) (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4))

Definition at line 513 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_LPTIM5 ( ) (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5))

Definition at line 514 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_RTC ( ) (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_RTC))

Definition at line 515 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM1 ( ) (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM1))

Definition at line 503 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM12 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12))

Definition at line 493 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM13 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13))

Definition at line 494 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM14 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14))

Definition at line 495 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM15 ( ) (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM15))

Definition at line 505 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM16 ( ) (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM16))

Definition at line 506 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM17 ( ) (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM17))

Definition at line 507 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM2 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2))

Definition at line 487 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM3 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3))

Definition at line 488 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM4 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4))

Definition at line 489 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM5 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5))

Definition at line 490 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM6 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6))

Definition at line 491 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM7 ( ) (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7))

Definition at line 492 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_TIM8 ( ) (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM8))

Definition at line 504 of file stm32h7xx_hal.h.

#define __HAL_DBGMCU_UnFreeze_WWDG1 ( ) (DBGMCU->APB3FZ1 &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1))

Definition at line 485 of file stm32h7xx_hal.h.

#define IS_EXTI_ALL_LINE ( LINE )

Definition at line 342 of file stm32h7xx_hal.h.

#define IS_EXTI_CONFIG_LINE ( LINE )
Value:
(((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)|| \
                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)   || \
                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)   || \
                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)   || \
                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)   || \
                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \
                                ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))

Definition at line 328 of file stm32h7xx_hal.h.

Referenced by HAL_EXTI_EdgeConfig(), and HAL_EXTI_GenerateSWInterrupt().

#define IS_EXTI_D1_LINE ( LINE )

Definition at line 383 of file stm32h7xx_hal.h.

Referenced by HAL_EXTI_D1_ClearFlag(), and HAL_EXTI_D1_EventInputConfig().

#define IS_EXTI_D3_CLEAR ( SOURCE )
Value:
(((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR)    || \
                                 ((SOURCE) == LPTIM4_OUT_CLEAR) || ((SOURCE) == LPTIM5_OUT_CLEAR))

Definition at line 441 of file stm32h7xx_hal.h.

Referenced by HAL_EXTI_D3_EventInputConfig().

#define IS_EXTI_D3_LINE ( LINE )
Value:
(((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \
                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
                                ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
                                ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
                                ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
                                ((LINE) == EXTI_LINE53))

Definition at line 425 of file stm32h7xx_hal.h.

Referenced by HAL_EXTI_D3_EventInputConfig().

#define IS_EXTI_EDGE_LINE ( EDGE ) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE))

Definition at line 325 of file stm32h7xx_hal.h.

Referenced by HAL_EXTI_EdgeConfig().

#define IS_EXTI_MODE_LINE ( MODE ) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT))

Definition at line 326 of file stm32h7xx_hal.h.

Referenced by HAL_EXTI_D1_EventInputConfig().

#define IS_FMC_SWAPBMAP_MODE ( __MODE__ )
Value:
(((__MODE__) == FMC_SWAPBMAP_DISABLE)    || \
                                        ((__MODE__) == FMC_SWAPBMAP_SDRAM_SRAM) || \
                                        ((__MODE__) == FMC_SWAPBMAP_SDRAMB2))

Definition at line 444 of file stm32h7xx_hal.h.

Referenced by HAL_SetFMCMemorySwappingConfig().

#define IS_SYSCFG_ANALOG_SWITCH ( SWITCH )
Value:
((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \
                                           (((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || \
                                           (((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || \
                                           (((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3))

Definition at line 301 of file stm32h7xx_hal.h.

Referenced by HAL_SYSCFG_AnalogSwitchConfig().

#define IS_SYSCFG_BOOT_ADDRESS ( ADDRESS ) ((ADDRESS) < PERIPH_BASE)

Definition at line 318 of file stm32h7xx_hal.h.

Referenced by HAL_SYSCFG_CM7BootAddConfig().

#define IS_SYSCFG_BOOT_REGISTER ( REGISTER )
Value:
(((REGISTER) == SYSCFG_BOOT_ADDR0)|| \
                                          ((REGISTER) == SYSCFG_BOOT_ADDR1))

Definition at line 315 of file stm32h7xx_hal.h.

Referenced by HAL_SYSCFG_CM7BootAddConfig().

#define IS_SYSCFG_CODE_CONFIG ( CONFIG ) ((CONFIG) < (0x10))

Definition at line 323 of file stm32h7xx_hal.h.

Referenced by HAL_SYSCFG_CompensationCodeConfig().

#define IS_SYSCFG_CODE_SELECT ( SELECT )
Value:
(((SELECT) == SYSCFG_CELL_CODE)|| \
                                        ((SELECT) == SYSCFG_REGISTER_CODE))

Definition at line 320 of file stm32h7xx_hal.h.

Referenced by HAL_SYSCFG_CompensationCodeSelect().

#define IS_SYSCFG_ETHERNET_CONFIG ( CONFIG )
Value:
(((CONFIG) == SYSCFG_ETH_MII)        || \
                                          ((CONFIG) == SYSCFG_ETH_RMII))

Definition at line 298 of file stm32h7xx_hal.h.

Referenced by HAL_SYSCFG_ETHInterfaceSelect().

#define IS_SYSCFG_SWITCH_STATE ( STATE )
Value:
((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN)    || \
                                           (((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE)   || \
                                           (((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN)     || \
                                           (((STATE) & SYSCFG_SWITCH_PA1_CLOSE) == SYSCFG_SWITCH_PA1_CLOSE)   || \
                                           (((STATE) & SYSCFG_SWITCH_PC2_OPEN) == SYSCFG_SWITCH_PC2_OPEN)     || \
                                           (((STATE) & SYSCFG_SWITCH_PC2_CLOSE) == SYSCFG_SWITCH_PC2_CLOSE)   || \
                                           (((STATE) & SYSCFG_SWITCH_PC3_OPEN) == SYSCFG_SWITCH_PC3_OPEN)     || \
                                           (((STATE) & SYSCFG_SWITCH_PC3_CLOSE) == SYSCFG_SWITCH_PC3_CLOSE))

Definition at line 306 of file stm32h7xx_hal.h.

Referenced by HAL_SYSCFG_AnalogSwitchConfig().

#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE ( __VALUE__ )
Value:
(((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
                                                      ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))

Definition at line 293 of file stm32h7xx_hal.h.

Referenced by HAL_SYSCFG_VREFBUF_HighImpedanceConfig().

#define IS_SYSCFG_VREFBUF_TRIMMING ( __VALUE__ ) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM))

Definition at line 296 of file stm32h7xx_hal.h.

Referenced by HAL_SYSCFG_VREFBUF_TrimmingConfig().

#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE ( __SCALE__ )
Value:
(((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \
                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3))

Definition at line 287 of file stm32h7xx_hal.h.

Referenced by HAL_SYSCFG_VREFBUF_VoltageScalingConfig().

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HAL

Modules | Defines | Variables
HAL
STM32H7xx_HAL_Driver

HAL module driver. More...

Modules

HAL Exported Functions
HAL Exported Constants
HAL Exported Macros

Defines

#define | __STM32H7xx_HAL_VERSION_MAIN (0x01)
STM32H7xx HAL Driver version number V1.0.0.
#define | __STM32H7xx_HAL_VERSION_SUB1 (0x00)
#define | __STM32H7xx_HAL_VERSION_SUB2 (0x00)
#define | __STM32H7xx_HAL_VERSION_RC (0x00)
#define | __STM32H7xx_HAL_VERSION
#define | IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
#define | VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms */

Variables

__IO uint32_t | uwTick

Detailed Description

HAL module driver.

Define Documentation

#define __STM32H7xx_HAL_VERSION
Value:
((__STM32H7xx_HAL_VERSION_MAIN << 24)\
                                        |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\
                                        |(__STM32H7xx_HAL_VERSION_SUB2 << 8 )\
                                        |(__STM32H7xx_HAL_VERSION_RC))

Definition at line 74 of file stm32h7xx_hal.c.

Referenced by HAL_GetHalVersion().

#define __STM32H7xx_HAL_VERSION_MAIN (0x01)

STM32H7xx HAL Driver version number V1.0.0.

[31:24] main version

Definition at line 70 of file stm32h7xx_hal.c.

#define __STM32H7xx_HAL_VERSION_RC (0x00)

[7:0] release candidate

Definition at line 73 of file stm32h7xx_hal.c.

#define __STM32H7xx_HAL_VERSION_SUB1 (0x00)

[23:16] sub1 version

Definition at line 71 of file stm32h7xx_hal.c.

#define __STM32H7xx_HAL_VERSION_SUB2 (0x00)

[15:8] sub2 version

Definition at line 72 of file stm32h7xx_hal.c.

#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)

Definition at line 79 of file stm32h7xx_hal.c.

Referenced by HAL_GetDEVID().

#define VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms */

Definition at line 80 of file stm32h7xx_hal.c.

Referenced by HAL_SYSCFG_EnableVREFBUF().

Variable Documentation

__IO uint32_t uwTick

Definition at line 84 of file stm32h7xx_hal.c.

Referenced by HAL_GetTick(), and HAL_IncTick().

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Private Constants

Defines
ADC Private Constants
ADC

Defines

#define | ADC_CFGR_FIELDS_1
#define | ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMNGT | ADC_CFGR_AUTDLY))
#define | ADC_CFGR2_FIELDS
#define | ADC_CFGR_WD_FIELDS
#define | ADC_OFR_FIELDS ((uint32_t)(ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH))
#define | ADC_ENABLE_TIMEOUT ((uint32_t) 2)
#define | ADC_DISABLE_TIMEOUT ((uint32_t) 2)
#define | ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 210688)
#define | ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 5)
#define | ADC_TEMPSENSOR_DELAY_US ((uint32_t) 120)
#define | ADC_STAB_DELAY_US ((uint32_t) 10)

Define Documentation

#define ADC_CFGR2_FIELDS
Value:
((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OSR   |\
                                       ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
                                       ADC_CFGR2_ROVSM))

Definition at line 282 of file stm32h7xx_hal_adc.c.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_FIELDS_1
Value:
((uint32_t)(ADC_CFGR_RES    |\
                                       ADC_CFGR_CONT   | ADC_CFGR_OVRMOD  |\
                                       ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
                                       ADC_CFGR_EXTEN  | ADC_CFGR_EXTSEL))

ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going

Definition at line 273 of file stm32h7xx_hal_adc.c.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMNGT | ADC_CFGR_AUTDLY))

ADC_CFGR2 fields of parameters that can be updated when no conversion (neither regular nor injected) is on-going

Definition at line 279 of file stm32h7xx_hal_adc.c.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_WD_FIELDS
Value:
((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN | \
                                        ADC_CFGR_AWD1EN | ADC_CFGR_AWD1CH))

ADC_CFGR fields of Analog Watchdog parameters that can be updated when no conversion (neither regular nor injected) is on-going

Definition at line 286 of file stm32h7xx_hal_adc.c.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 210688)

ADC conversion completion time-out value

Definition at line 311 of file stm32h7xx_hal_adc.c.

Referenced by ADC_ConversionStop().

#define ADC_DISABLE_TIMEOUT ((uint32_t) 2)

ADC disable time-out value

Definition at line 302 of file stm32h7xx_hal_adc.c.

Referenced by ADC_Disable().

#define ADC_ENABLE_TIMEOUT ((uint32_t) 2)

ADC enable time-out value

Definition at line 301 of file stm32h7xx_hal_adc.c.

Referenced by ADC_Enable().

#define ADC_OFR_FIELDS ((uint32_t)(ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH))

ADC_OFR fields of parameters that can be updated when no conversion (neither regular nor injected) is on-going

Definition at line 290 of file stm32h7xx_hal_adc.c.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_STAB_DELAY_US ((uint32_t) 10)

ADC voltage regulator startup time

Definition at line 757 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_LinearCalibration_SetValue().

#define ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 5)

Definition at line 744 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConversionStop(), HAL_ADCEx_MultiModeStop_DMA(), and HAL_ADCEx_RegularMultiModeStop_DMA().

#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 120)

Definition at line 751 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and deinitialization functions

Functions
Initialization and deinitialization functions
ADC Exported Functions

ADC Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initialize the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitialize the ADC MSP.

Detailed Description

ADC Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and deinitialization functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Initialize and configure the ADC.
      (+) Deinitialize the ADC.

Function Documentation

HAL_StatusTypeDef HAL_ADC_DeInit ( ADC_HandleTypeDef * hadc )

Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.

Note:
Keep in mind that all ADCs use the same clock: disabling the clock will reset all ADCs.
By default, HAL_ADC_DeInit() sets DEEPPWD: this saves more power by reducing the leakage currents and is particularly interesting before entering STOP 1 or STOP 2 modes.
Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 673 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, ADC12_COMMON_REGISTER, ADC3_COMMON_REGISTER, ADC_ANY_OTHER_ENABLED, ADC_CLEAR_ERRORCODE, ADC_ConversionStop(), ADC_Disable(), ADC_FLAG_AWD1, ADC_FLAG_AWD2, ADC_FLAG_AWD3, ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_EOSMP, ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_FLAG_JQOVF, ADC_FLAG_OVR, ADC_FLAG_RDY, ADC_IS_ENABLE, ADC_IT_AWD1, ADC_IT_AWD2, ADC_IT_AWD3, ADC_IT_EOC, ADC_IT_EOS, ADC_IT_EOSMP, ADC_IT_JEOC, ADC_IT_JEOS, ADC_IT_JQOVF, ADC_IT_OVR, ADC_IT_RDY, ADC_REGULAR_INJECTED_GROUP, assert_param, ADC_InjectionConfigTypeDef::ChannelCount, ADC_InjectionConfigTypeDef::ContextQueue, HAL_ADC_MspDeInit(), HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_RESET, ADC_HandleTypeDef::InjectionConfig, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Init ( ADC_HandleTypeDef * hadc )

Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".

Note:
As prerequisite, ADC clock must be configured at RCC top level depending on possible clock sources: PLL2/PLL3 clocks or AHB clock.
Possibility to update parameters on the fly: this function initializes the ADC MSP (HAL_ADC_MspInit()) only when coming from ADC state reset. Following calls to this function can be used to reconfigure some parameters of ADC_InitTypeDef structure on the fly, without modifying MSP configuration. If ADC MSP has to be modified again, HAL_ADC_DeInit() must be called before HAL_ADC_Init(). The setting of these parameters is conditioned by ADC state. For parameters constraints, see comments of structure "ADC_InitTypeDef".
This function configures the ADC within 2 scopes: scope of entire ADC and scope of regular group. For parameters details, see comments of structure "ADC_InitTypeDef".
Parameters related to common ADC registers (ADC clock mode) are set only if all ADCs are disabled. If this is not the case, these common parameters setting are bypassed without error reporting: it can be the intended behaviour in case of update of a parameter of ADC_InitTypeDef on the fly, without disabling the other ADCs.
Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 370 of file stm32h7xx_hal_adc.c.

References ADC12_COMMON_REGISTER, ADC3_COMMON_REGISTER, ADC_ANY_OTHER_ENABLED, ADC_CFGR2_FIELDS, ADC_CFGR_AUTOWAIT, ADC_CFGR_CONTINUOUS, ADC_CFGR_DISCONTINUOUS_NUM, ADC_CFGR_DMACONTREQ, ADC_CFGR_FIELDS_1, ADC_CFGR_FIELDS_2, ADC_CFGR_REG_DISCONTINUOUS, ADC_CLEAR_ERRORCODE, ADC_EXTERNALTRIGCONVEDGE_NONE, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED, ADC_IS_ENABLE, ADC_SCAN_DISABLE, ADC_SCAN_ENABLE, ADC_SOFTWARE_START, ADC_STAB_DELAY_US, ADC_STATE_CLR_SET, ADC_TRIGGEREDMODE_SINGLE_TRIGGER, assert_param, ADC_InitTypeDef::BoostMode, ADC_InitTypeDef::ClockPrescaler, ADC_InitTypeDef::ContinuousConvMode, ADC_InitTypeDef::ConversionDataManagement, ADC_InitTypeDef::DiscontinuousConvMode, ADC_InitTypeDef::EOCSelection, ADC_HandleTypeDef::ErrorCode, ADC_InitTypeDef::ExternalTrigConv, ADC_InitTypeDef::ExternalTrigConvEdge, HAL_ADC_ERROR_INTERNAL, HAL_ADC_MspInit(), HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_READY, HAL_ADC_STATE_RESET, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_CLOCKPRESCALER, IS_ADC_CONVERSIONDATAMGT, IS_ADC_EOC_SELECTION, IS_ADC_EXTTRIG, IS_ADC_EXTTRIG_EDGE, IS_ADC_OVERRUN, IS_ADC_OVERSAMPLING_RATIO, IS_ADC_REGOVERSAMPLING_MODE, IS_ADC_REGULAR_DISCONT_NUMBER, IS_ADC_REGULAR_NB_CONV, IS_ADC_RESOLUTION, IS_ADC_RIGHT_BIT_SHIFT, IS_ADC_SCAN_MODE, IS_ADC_TRIGGERED_OVERSAMPLING_MODE, ADC_InitTypeDef::LeftBitShift, ADC_HandleTypeDef::Lock, ADC_InitTypeDef::LowPowerAutoWait, ADC_InitTypeDef::NbrOfConversion, ADC_InitTypeDef::NbrOfDiscConversion, ADC_InitTypeDef::Overrun, ADC_InitTypeDef::Oversampling, ADC_InitTypeDef::OversamplingMode, ADC_OversamplingTypeDef::OversamplingStopReset, ADC_OversamplingTypeDef::Ratio, ADC_InitTypeDef::Resolution, ADC_OversamplingTypeDef::RightBitShift, ADC_InitTypeDef::ScanConvMode, ADC_HandleTypeDef::State, and ADC_OversamplingTypeDef::TriggeredMode.

void HAL_ADC_MspDeInit ( ADC_HandleTypeDef * hadc )

DeInitialize the ADC MSP.

Parameters:
hadc,: ADC handle
Note:
All ADCs use the same clock: disabling the clock will reset all ADCs.
Return values:
None

Definition at line 898 of file stm32h7xx_hal_adc.c.

Referenced by HAL_ADC_DeInit().

void HAL_ADC_MspInit ( ADC_HandleTypeDef * hadc )

Initialize the ADC MSP.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 883 of file stm32h7xx_hal_adc.c.

Referenced by HAL_ADC_Init().

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
ADC Exported Functions

ADC IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enable ADC, starts conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for ADC event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start conversion of regular group and transfer result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handle ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non-blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non-blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog 1 callback in non-blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).

Detailed Description

ADC IO operation functions.

 ===============================================================================
             ##### IO operation functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Start conversion of regular group.
      (+) Stop conversion of regular group.
      (+) Poll for conversion complete on regular group.
      (+) Poll for conversion event.
      (+) Get result of regular channel conversion.
      (+) Start conversion of regular group and enable interruptions.
      (+) Stop conversion of regular group and disable interruptions.
      (+) Handle ADC interrupt request
      (+) Start conversion of regular group and enable DMA transfer.
      (+) Stop conversion of regular group and disable ADC DMA transfer.

Function Documentation

void HAL_ADC_ConvCpltCallback ( ADC_HandleTypeDef * hadc )

Conversion complete callback in non-blocking mode.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 2173 of file stm32h7xx_hal_adc.c.

Referenced by ADC_DMAConvCplt(), and HAL_ADC_IRQHandler().

void HAL_ADC_ConvHalfCpltCallback ( ADC_HandleTypeDef * hadc )

Conversion DMA half-transfer callback in non-blocking mode.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 2188 of file stm32h7xx_hal_adc.c.

Referenced by ADC_DMAHalfConvCplt().

void HAL_ADC_ErrorCallback ( ADC_HandleTypeDef * hadc )

ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).

Note:
In case of error due to overrun when using ADC with DMA transfer (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
  • Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
  • If needed, restart a new ADC conversion using function "HAL_ADC_Start_DMA()" (this function is also clearing overrun flag)
Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 2225 of file stm32h7xx_hal_adc.c.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), and HAL_ADC_IRQHandler().

uint32_t HAL_ADC_GetValue ( ADC_HandleTypeDef * hadc )

Get ADC regular group conversion result.

Note:
Reading register DR automatically clears ADC flag EOC (ADC group regular end of unitary conversion).
This function does not clear ADC flag EOS (ADC group regular end of sequence conversion). Occurrence of flag EOS rising:
  • If sequencer is composed of 1 rank, flag EOS is equivalent to flag EOC.
  • If sequencer is composed of several ranks, during the scan sequence flag EOC only is raised, at the end of the scan sequence both flags EOC and EOS are raised. To clear this flag, either use function: in programming model IT: HAL_ADC_IRQHandler(), in programming model polling: HAL_ADC_PollForConversion() or __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
Parameters:
hadc,: ADC handle
Return values:
ADC group regular conversion data

Definition at line 1826 of file stm32h7xx_hal_adc.c.

References assert_param, and ADC_HandleTypeDef::Instance.

void HAL_ADC_IRQHandler ( ADC_HandleTypeDef * hadc )

Handle ADC interrupt request.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 1844 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_GET_FLAG, ADC12_COMMON_REGISTER, ADC3_COMMON_REGISTER, ADC_FLAG_AWD1, ADC_FLAG_AWD2, ADC_FLAG_AWD3, ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_EOSMP, ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_FLAG_JQOVF, ADC_FLAG_OVR, ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE, ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE, ADC_IS_CONVERSION_ONGOING_INJECTED, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_IS_SOFTWARE_START_INJECTED, ADC_IS_SOFTWARE_START_REGULAR, ADC_IT_AWD1, ADC_IT_AWD2, ADC_IT_AWD3, ADC_IT_EOC, ADC_IT_EOS, ADC_IT_EOSMP, ADC_IT_JEOC, ADC_IT_JEOS, ADC_IT_JQOVF, ADC_IT_OVR, ADC_MASTER_REGISTER, ADC_MODE_INDEPENDENT, ADC_OVR_DATA_PRESERVED, assert_param, ADC_InitTypeDef::EOCSelection, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ConvCpltCallback(), HAL_ADC_ERROR_INTERNAL, HAL_ADC_ERROR_JQOVF, HAL_ADC_ERROR_OVR, HAL_ADC_ErrorCallback(), HAL_ADC_LevelOutOfWindowCallback(), HAL_ADC_STATE_AWD1, HAL_ADC_STATE_AWD2, HAL_ADC_STATE_AWD3, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_JQOVF, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_ADCEx_EndOfSamplingCallback(), HAL_ADCEx_InjectedConvCpltCallback(), HAL_ADCEx_InjectedQueueOverflowCallback(), HAL_ADCEx_LevelOutOfWindow2Callback(), HAL_ADCEx_LevelOutOfWindow3Callback(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_EOC_SELECTION, ADC_InitTypeDef::Overrun, and ADC_HandleTypeDef::State.

void HAL_ADC_LevelOutOfWindowCallback ( ADC_HandleTypeDef * hadc )

Analog watchdog 1 callback in non-blocking mode.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 2203 of file stm32h7xx_hal_adc.c.

Referenced by HAL_ADC_IRQHandler().

HAL_StatusTypeDef HAL_ADC_PollForConversion | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | Timeout
 | ) |  |

Wait for regular group conversion to be completed.

Parameters:
hadc,: ADC handle
Timeout,: Timeout value in millisecond.
Note:
Depending on hadc->Init.EOCSelection, EOS or EOC is checked and cleared depending on AUTDLY bit status.
HAL_ADC_PollForConversion() returns HAL_ERROR if EOC is polled in a DMA-managed conversions configuration: indeed, EOC is immediately reset by the DMA reading the DR register when the converted data is available. Therefore, EOC is set for a too short period to be reliably polled.
Return values:
HAL status

Definition at line 1100 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, ADC12_COMMON_REGISTER, ADC_DUALMODEDATAFORMAT_32_10_BITS, ADC_DUALMODEDATAFORMAT_8_BITS, ADC_EOC_SEQ_CONV, ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE, ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE, ADC_IS_SOFTWARE_START_REGULAR, ADC_MASTER_REGISTER, assert_param, ADC_InitTypeDef::EOCSelection, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_PollForEvent | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | EventType,
 |  | uint32_t | Timeout
 | ) |  |

Poll for ADC event.

Parameters:
hadc,: ADC handle
EventType,: the ADC event type. This parameter can be one of the following values:
  • ADC_EOSMP_EVENT ADC End of Sampling event
  • ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
  • ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
  • ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
  • ADC_OVR_EVENT ADC Overrun event
  • ADC_JQOVF_EVENT ADC Injected context queue overflow event
Timeout,: Timeout value in millisecond.
Note:
The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. Indeed, the latter is reset only if hadc->Init.Overrun field is set to ADC_OVR_DATA_OVERWRITTEN. Otherwise, DR may be potentially overwritten by a new converted data as soon as OVR is cleared. To reset OVR flag once the preserved data is retrieved, the user can resort to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
Return values:
HAL status

Definition at line 1267 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, ADC_AWD2_EVENT, ADC_AWD3_EVENT, ADC_AWD_EVENT, ADC_EOSMP_EVENT, ADC_FLAG_AWD1, ADC_FLAG_AWD2, ADC_FLAG_AWD3, ADC_FLAG_EOSMP, ADC_FLAG_JQOVF, ADC_FLAG_OVR, ADC_JQOVF_EVENT, ADC_OVR_DATA_PRESERVED, assert_param, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_JQOVF, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_AWD1, HAL_ADC_STATE_AWD2, HAL_ADC_STATE_AWD3, HAL_ADC_STATE_INJ_JQOVF, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_EVENT_TYPE, ADC_InitTypeDef::Overrun, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Start ( ADC_HandleTypeDef * hadc )

Enable ADC, starts conversion of regular group.

Note:
Interruptions enabled in this function: None.
Case of multimode enabled(when multimode feature is available): if ADC is Slave, ADC is enabled but conversion is not started, if ADC is master, ADC is enabled and multimode conversion is started.
Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 943 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, ADC12_NONMULTIMODE_OR_MULTIMODEMASTER, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_MASTER_REGISTER, ADC_STATE_CLR_SET, assert_param, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Start_DMA | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

Enable ADC, start conversion of regular group and transfer result through DMA.

Note:
Interruptions enabled in this function: overrun (if applicable), DMA half transfer, DMA transfer complete. Each of these interruptions has its dedicated callback function.
Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA() is designed for single-ADC mode only. For multimode, the dedicated HAL_ADCEx_MultiModeStart_DMA() function must be used.
Parameters:
hadc,: ADC handle
pData,: Destination Buffer address.
Length,: Length of data to be transferred from ADC peripheral to memory (in bytes)
Return values:
HAL status.

Definition at line 1625 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE_IT, ADC12_NONMULTIMODE_OR_MULTIMODEMASTER, ADC_CLEAR_ERRORCODE, ADC_DMAConvCplt(), ADC_DMAError(), ADC_DMAHalfConvCplt(), ADC_Enable(), ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE, ADC_IT_OVR, ADC_STATE_CLR_SET, assert_param, ADC_HandleTypeDef::DMA_Handle, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_DMA_Start_IT(), ADC_HandleTypeDef::Instance, ADC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_ADC_Start_IT ( ADC_HandleTypeDef * hadc )

Enable ADC, start conversion of regular group with interruption.

Note:
Interruptions enabled in this function according to initialization setting : EOC (end of conversion), EOS (end of sequence), OVR overrun. Each of these interruptions has its dedicated callback function.
Case of multimode enabled(when multimode feature is available): HAL_ADC_Start_IT() must be called for ADC Slave first, then for ADC Master. For ADC Slave, ADC is enabled only (conversion is not started). For ADC Master, ADC is enabled and multimode conversion is started.
To guarantee a proper reset of all interruptions once all the needed conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure a correct stop of the IT-based conversions.
By default, HAL_ADC_Start_IT() doesn't enable the End Of Sampling interruption. If required (e.g. in case of oversampling with trigger mode), the user must 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP); before calling HAL_ADC_Start_IT().
Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 1411 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_ENABLE_IT, ADC12_NONMULTIMODE_OR_MULTIMODEMASTER, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_EOC_SEQ_CONV, ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_IT_EOC, ADC_IT_EOS, ADC_IT_JEOC, ADC_IT_JEOS, ADC_IT_OVR, ADC_MASTER_REGISTER, ADC_OVR_DATA_PRESERVED, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::EOCSelection, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, ADC_InitTypeDef::Overrun, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.

Note:
ADC peripheral disable is forcing stop of potential conversion on injected group. If injected group is under use, it should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
Parameters:
hadc,: ADC handle
Return values:
HAL status.

Definition at line 1050 of file stm32h7xx_hal_adc.c.

References ADC_ConversionStop(), ADC_Disable(), ADC_REGULAR_INJECTED_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop_DMA ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.

Note:
ADC peripheral disable is forcing stop of potential conversion on injected group. If injected group is under use, it should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
Case of multimode enabled (when multimode feature is available): HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only. For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
Parameters:
hadc,: ADC handle
Return values:
HAL status.

Definition at line 1743 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IT_OVR, ADC_REGULAR_INJECTED_GROUP, ADC_STATE_CLR_SET, assert_param, ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop_IT ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.

Parameters:
hadc,: ADC handle
Return values:
HAL status.

Definition at line 1571 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IT_EOC, ADC_IT_EOS, ADC_IT_OVR, ADC_REGULAR_INJECTED_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
ADC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configure a channel to be assigned to ADC group regular.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configure the analog watchdog.

Detailed Description

Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Configure channels on regular group
      (+) Configure the analog watchdog

Function Documentation

HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_AnalogWDGConfTypeDef * | AnalogWDGConfig
 | ) |  |

Configure the analog watchdog.

Note:
Possibility to update parameters on the fly: This function initializes the selected analog watchdog, successive calls to this function can be used to reconfigure some parameters of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting the ADC. The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_AnalogWDGConfTypeDef".
Analog watchdog thresholds can be modified while ADC conversion is on going. In this case, some constraints must be taken into account: the programmed threshold values are effective from the next ADC EOC (end of unitary conversion). Considering that registers write delay may happen due to bus activity, this might cause an uncertainty on the effective timing of the new programmed threshold values.
Parameters:
hadc,: ADC handle
AnalogWDGConfig,: Structure of ADC analog watchdog configuration
Return values:
HAL status

Definition at line 2650 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_ENABLE_IT, ADC_ANALOGWATCHDOG_1, ADC_ANALOGWATCHDOG_2, ADC_ANALOGWATCHDOG_NONE, ADC_ANALOGWATCHDOG_SINGLE_INJEC, ADC_ANALOGWATCHDOG_SINGLE_REG, ADC_ANALOGWATCHDOG_SINGLE_REGINJEC, ADC_AWD1THRESHOLD_SHIFT_RESOLUTION, ADC_AWD23THRESHOLD_SHIFT_RESOLUTION, ADC_CFGR_SET_AWD1CH, ADC_CFGR_SET_AWD23CR, ADC_CFGR_WD_FIELDS, ADC_FLAG_AWD2, ADC_FLAG_AWD3, ADC_GET_RESOLUTION, ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED, ADC_IT_AWD1, ADC_IT_AWD2, ADC_IT_AWD3, assert_param, ADC_AnalogWDGConfTypeDef::Channel, HAL_ADC_STATE_AWD1, HAL_ADC_STATE_AWD2, HAL_ADC_STATE_AWD3, HAL_ADC_STATE_ERROR_CONFIG, ADC_AnalogWDGConfTypeDef::HighThreshold, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_ANALOG_WATCHDOG_MODE, IS_ADC_ANALOG_WATCHDOG_NUMBER, IS_ADC_CHANNEL, IS_ADC_RANGE, ADC_AnalogWDGConfTypeDef::ITMode, ADC_AnalogWDGConfTypeDef::LowThreshold, ADC_InitTypeDef::Oversampling, ADC_InitTypeDef::OversamplingMode, ADC_OversamplingTypeDef::Ratio, ADC_HandleTypeDef::State, ADC_AnalogWDGConfTypeDef::WatchdogMode, and ADC_AnalogWDGConfTypeDef::WatchdogNumber.

HAL_StatusTypeDef HAL_ADC_ConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_ChannelConfTypeDef * | sConfig
 | ) |  |

Configure a channel to be assigned to ADC group regular.

Note:
In case of usage of internal measurement channels: Vbat/VrefInt/TempSensor. These internal paths can be disabled using function HAL_ADC_DeInit().
Possibility to update parameters on the fly: This function initializes channel into ADC group regular, following calls to this function can be used to reconfigure some parameters of structure "ADC_ChannelConfTypeDef" on the fly, without resetting the ADC. The setting of these parameters is conditioned to ADC state: Refer to comments of structure "ADC_ChannelConfTypeDef".
Parameters:
hadc,: ADC handle
sConfig,: Structure of ADC channel assigned to ADC group regular.
Return values:
HAL status

Definition at line 2272 of file stm32h7xx_hal_adc.c.

References ADC12_COMMON_REGISTER, ADC3_COMMON_REGISTER, ADC_ANY_OTHER_ENABLED, ADC_CHANNEL_10, ADC_CHANNEL_9, ADC_CHANNEL_TEMPSENSOR, ADC_CHANNEL_VBAT_DIV4, ADC_CHANNEL_VREFINT, ADC_DIFFERENTIAL_ENDED, ADC_DIFSEL_CHANNEL, ADC_GET_RESOLUTION, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED, ADC_IS_ENABLE, ADC_OFFSET_1, ADC_OFFSET_2, ADC_OFFSET_3, ADC_OFFSET_4, ADC_OFFSET_SHIFT_RESOLUTION, ADC_OFR_CHANNEL, ADC_OFR_FIELDS, ADC_SMPR1, ADC_SMPR2, ADC_SQR1_RK, ADC_SQR2_RK, ADC_SQR3_RK, ADC_SQR4_RK, ADC_TEMPSENSOR_DELAY_US, assert_param, ADC_ChannelConfTypeDef::Channel, HAL_ADC_STATE_ERROR_CONFIG, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC1_DIFF_CHANNEL, IS_ADC2_DIFF_CHANNEL, IS_ADC3_DIFF_CHANNEL, IS_ADC_CHANNEL, IS_ADC_OFFSET_NUMBER, IS_ADC_RANGE, IS_ADC_REGULAR_RANK, IS_ADC_SAMPLE_TIME, IS_ADC_SINGLE_DIFFERENTIAL, ADC_ChannelConfTypeDef::Offset, ADC_ChannelConfTypeDef::OffsetNumber, ADC_ChannelConfTypeDef::OffsetRightShift, ADC_ChannelConfTypeDef::OffsetSignedSaturation, ADC_InitTypeDef::Oversampling, ADC_InitTypeDef::OversamplingMode, ADC_ChannelConfTypeDef::Rank, ADC_OversamplingTypeDef::Ratio, ADC_ChannelConfTypeDef::SamplingTime, ADC_ChannelConfTypeDef::SingleDiff, and ADC_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
ADC Exported Functions

ADC Peripheral State functions. More...

Functions

uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
Return the ADC handle state.
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.

Detailed Description

ADC Peripheral State functions.

 ===============================================================================
            ##### Peripheral state and errors functions #####
 ===============================================================================
    [..] This subsection provides functions to get in run-time the status of the
    peripheral.
      (+) Check the ADC state
      (+) Check the ADC error code

Function Documentation

uint32_t HAL_ADC_GetError ( ADC_HandleTypeDef * hadc )

Return the ADC error code.

Parameters:
hadc,: ADC handle
Return values:
ADC error code (bitfield on 32 bits)

Definition at line 2886 of file stm32h7xx_hal_adc.c.

References assert_param, ADC_HandleTypeDef::ErrorCode, and ADC_HandleTypeDef::Instance.

uint32_t HAL_ADC_GetState ( ADC_HandleTypeDef * hadc )

Return the ADC handle state.

Note:
ADC state machine is managed by bitfields, ADC status must be compared with states bits. For example: " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
Parameters:
hadc,: ADC handle
Return values:
ADC handle state (bitfield on 32 bits)

Definition at line 2871 of file stm32h7xx_hal_adc.c.

References assert_param, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Private Functions

Functions
ADC Private Functions
ADC | ADC Exported Functions

Functions

HAL_StatusTypeDef | ADC_ConversionStop (ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
Stop ADC conversion.
HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_Disable (ADC_HandleTypeDef *hadc)
Disable the selected ADC.
void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Function Documentation

HAL_StatusTypeDef ADC_ConversionStop | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | ConversionGroup
 | ) |  |

Stop ADC conversion.

Parameters:
hadc,: ADC handle
ConversionGroup,: ADC group regular and/or injected. This parameter can be one of the following values:
  • ADC_REGULAR_GROUP ADC regular conversion type.
  • ADC_INJECTED_GROUP ADC injected conversion type.
  • ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
Return values:
HAL status.

Definition at line 2915 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, ADC_CONVERSION_TIME_MAX_CPU_CYCLES, ADC_FLAG_JEOS, ADC_INJECTED_GROUP, ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED, ADC_REGULAR_GROUP, ADC_REGULAR_INJECTED_GROUP, ADC_STOP_CONVERSION_TIMEOUT, assert_param, ADC_InitTypeDef::ContinuousConvMode, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_CONVERSION_GROUP, ADC_InitTypeDef::LowPowerAutoWait, and ADC_HandleTypeDef::State.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

HAL_StatusTypeDef ADC_Disable ( ADC_HandleTypeDef * hadc )

Disable the selected ADC.

Note:
Prerequisite condition to use this function: ADC conversions must be stopped.
Parameters:
hadc,: ADC handle
Return values:
HAL status.

Definition at line 3098 of file stm32h7xx_hal_adc.c.

References ADC_DISABLE, ADC_DISABLE_TIMEOUT, ADC_DISABLING_CONDITIONS, ADC_IS_ENABLE, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

void ADC_DMAConvCplt ( DMA_HandleTypeDef * hdma )

DMA transfer complete callback.

Parameters:
hdma,: pointer to DMA handle.
Return values:
None

Definition at line 3153 of file stm32h7xx_hal_adc.c.

References ADC_FLAG_EOS, ADC_IS_SOFTWARE_START_REGULAR, HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(), HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

Referenced by HAL_ADC_Start_DMA(), and HAL_ADCEx_MultiModeStart_DMA().

void ADC_DMAError ( DMA_HandleTypeDef * hdma )

DMA error callback.

Parameters:
hdma,: pointer to DMA handle.
Return values:
None

Definition at line 3232 of file stm32h7xx_hal_adc.c.

References ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ErrorCallback(), HAL_ADC_STATE_ERROR_DMA, and ADC_HandleTypeDef::State.

Referenced by HAL_ADC_Start_DMA(), and HAL_ADCEx_MultiModeStart_DMA().

void ADC_DMAHalfConvCplt ( DMA_HandleTypeDef * hdma )

DMA half transfer complete callback.

Parameters:
hdma,: pointer to DMA handle.
Return values:
None

Definition at line 3218 of file stm32h7xx_hal_adc.c.

References HAL_ADC_ConvHalfCpltCallback().

Referenced by HAL_ADC_Start_DMA(), and HAL_ADCEx_MultiModeStart_DMA().

HAL_StatusTypeDef ADC_Enable ( ADC_HandleTypeDef * hadc )

Enable the selected ADC.

Note:
Prerequisite condition to use this function: ADC must be disabled and voltage regulator must be enabled (done into HAL_ADC_Init()).
Parameters:
hadc,: ADC handle
Return values:
HAL status.

Definition at line 3035 of file stm32h7xx_hal_adc.c.

References __HAL_ADC_GET_FLAG, ADC_ENABLE, ADC_ENABLE_TIMEOUT, ADC_ENABLING_CONDITIONS, ADC_FLAG_RDY, ADC_IS_ENABLE, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), and ADC_HandleTypeDef::State.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_LinearCalibration_GetValue(), and HAL_ADCEx_MultiModeStart_DMA().

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC States

Defines
ADC States
ADC Exported Types

Defines

#define | HAL_ADC_STATE_RESET ((uint32_t)0x00000000)
HAL ADC state machine: ADC states definition (bitfields)
#define | HAL_ADC_STATE_READY ((uint32_t)0x00000001)
#define | HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002)
#define | HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004)
#define | HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010)
#define | HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020)
#define | HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040)
#define | HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100)
#define | HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200)
#define | HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400)
#define | HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800)
#define | HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000)
#define | HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000)
#define | HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000)
#define | HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000)
#define | HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000)
#define | HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000)
#define | HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000)

Define Documentation

#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000)

Out-of-window occurrence of ADC analog watchdog 1

Definition at line 276 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000)

Out-of-window occurrence of ADC analog watchdog 2

Definition at line 277 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000)

Out-of-window occurrence of ADC analog watchdog 3

Definition at line 278 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002)

ADC is busy due to an internal process (initialization, calibration)

Definition at line 254 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), and HAL_ADCEx_Calibration_Start().

#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020)

Configuration error occurrence

Definition at line 259 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_PollForConversion(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), and HAL_ADCEx_RegularMultiModeStop_DMA().

#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040)

DMA error occurrence

Definition at line 260 of file stm32h7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), and HAL_ADCEx_RegularStop_DMA().

#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010)

Internal error occurrence

Definition at line 258 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAConvCplt(), ADC_Enable(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_Stop_DMA(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_LinearCalibration_SetValue(), HAL_ADCEx_MultiModeStop_DMA(), and HAL_ADCEx_RegularMultiModeStop_DMA().

#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000)

A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))

Definition at line 270 of file stm32h7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000)

Conversion data available on group injected

Definition at line 272 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000)

Injected queue overflow occurrence

Definition at line 273 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), and HAL_ADCEx_EnableInjectedQueue().

#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000)

ADC in multimode slave state, controlled by another ADC master (when feature available)

Definition at line 281 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define HAL_ADC_STATE_READY ((uint32_t)0x00000001)

ADC peripheral ready for use

Definition at line 253 of file stm32h7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100)

A conversion on ADC group regular is ongoing or can occur (either by continuous mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))

Definition at line 263 of file stm32h7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200)

Conversion data available on group regular

Definition at line 265 of file stm32h7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800)

Not available on this STM32 serie: End Of Sampling flag raised

Definition at line 267 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400)

Overrun occurrence

Definition at line 266 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000)

HAL ADC state machine: ADC states definition (bitfields)

Note:
ADC state machine is managed by bitfields, state must be compared with bit by bit. For example: " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " ADC not yet initialized or disabled

Definition at line 252 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_Init().

#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004)

TimeOut occurrence

Definition at line 255 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), and HAL_ADCEx_InjectedPollForConversion().

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC_OversamplingTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_OversamplingTypeDef Struct Reference
ADC Exported Types

ADC Regular Conversion Oversampling structure definition. More...

#include <stm32h7xx_hal_adc.h>

Data Fields

uint32_t | Ratio
uint32_t | RightBitShift
uint32_t | TriggeredMode
uint32_t | OversamplingStopReset

Detailed Description

ADC Regular Conversion Oversampling structure definition.

Definition at line 65 of file stm32h7xx_hal_adc.h.

Field Documentation

uint32_t ADC_OversamplingTypeDef::OversamplingStopReset

Selects the regular oversampling mode. The oversampling is either temporary stopped or reset upon an injected sequence interruption. If oversampling is enabled on both regular and injected groups, this parameter is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed during injection sequence). This parameter can be a value of ADC Extended Regular Oversampling Continued or Resumed Mode

Definition at line 76 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_OversamplingTypeDef::Ratio

Configures the oversampling ratio.

Definition at line 67 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_OversamplingTypeDef::RightBitShift

Configures the division coefficient for the Oversampler. This parameter can be a value of ADC Extended Oversampling Right Shift

Definition at line 70 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_OversamplingTypeDef::TriggeredMode

Selects the regular triggered oversampling mode. This parameter can be a value of ADC Extended Triggered Regular Oversampling

Definition at line 73 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_adc.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InitTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC instance and ADC group regular. More...

#include <stm32h7xx_hal_adc.h>

Data Fields

uint32_t | ClockPrescaler
uint32_t | Resolution
uint32_t | ScanConvMode
uint32_t | EOCSelection
FunctionalState | LowPowerAutoWait
FunctionalState | ContinuousConvMode
uint32_t | NbrOfConversion
FunctionalState | DiscontinuousConvMode
uint32_t | NbrOfDiscConversion
uint32_t | ExternalTrigConv
uint32_t | ExternalTrigConvEdge
uint32_t | ConversionDataManagement
uint32_t | Overrun
uint32_t | LeftBitShift
FunctionalState | BoostMode
FunctionalState | OversamplingMode
ADC_OversamplingTypeDef Oversampling

Detailed Description

Structure definition of ADC instance and ADC group regular.

Note:
Parameters of this structure are shared within 2 scopes:
  • Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait.
  • Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled
  • For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.
  • For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).

Definition at line 101 of file stm32h7xx_hal_adc.h.

Field Documentation

FunctionalState ADC_InitTypeDef::BoostMode

Configures the Boost mode control. When selecting an analog ADC clock frequency bigger than 20MHz, it is mandatory to first enable the BOOST Mode. This parameter can be set to ENABLE or DISABLE.

Definition at line 190 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ClockPrescaler

Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from System/PLL2/PLL3 clocks) and clock prescaler.

This parameter can be a value of ADC clock source and clock prescaler. Note: The clock is common for all the ADCs. Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 16, 14, 12 or 10 bits, AHB clock frequency /3 for resolution 8 bits. Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. Note: In case of usage of the ADC dedicated PLL clock, it must be preliminarily enabled at RCC top level. Note: This parameter can be modified only if all ADCs are disabled.

Definition at line 103 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

FunctionalState ADC_InitTypeDef::ContinuousConvMode

Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, after the first ADC conversion start trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE.

Definition at line 141 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConversionStop(), HAL_ADC_Init(), and HAL_ADCEx_MultiModeStart_DMA().

uint32_t ADC_InitTypeDef::ConversionDataManagement

Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transfered to DFSDM register. Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. This parameter can be a value of ADC Conversion Data Management. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 170 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

FunctionalState ADC_InitTypeDef::DiscontinuousConvMode

Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE.

Definition at line 151 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InitTypeDef::EOCSelection

Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. This parameter can be a value of ADC sequencer end of unitary conversion or sequence conversions.

Definition at line 126 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_InjectedStart_IT().

uint32_t ADC_InitTypeDef::ExternalTrigConv

Select the external event source used to trigger ADC group regular conversion start. If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. This parameter can be a value of ADC group regular trigger source. Caution: external trigger source is common to all ADC instances.

Definition at line 161 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ExternalTrigConvEdge

Select the external event edge used to trigger ADC group regular conversion start. If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of ADC group regular trigger edge (when external trigger is selected)

Definition at line 166 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_MultiModeStart_DMA().

uint32_t ADC_InitTypeDef::LeftBitShift

Configures the left shifting applied to the final result with or without oversampling. This parameter can be a value of ADC Extended Oversampling left Shift

Definition at line 187 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

FunctionalState ADC_InitTypeDef::LowPowerAutoWait

Select the dynamic low power Auto Delay: new conversion start only when the previous conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software, using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. This parameter can be set to ENABLE or DISABLE. Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag to free the IRQ vector sequencer. Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...).

Definition at line 129 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConversionStop(), and HAL_ADC_Init().

uint32_t ADC_InitTypeDef::NbrOfConversion

Specify the number of ranks that will be converted within the regular group sequencer. To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 16. Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 145 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::NbrOfDiscConversion

Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided. If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8.

Definition at line 157 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::Overrun

Select the behavior in case of overrun: data overwritten or preserved (default). This parameter applies to ADC group regular only. This parameter can be a value of ADC overrun. Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). Note: Error reporting with respect to the conversion mode:

  • Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
  • Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register).

Definition at line 176 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), and HAL_ADC_Start_IT().

ADC_OversamplingTypeDef ADC_InitTypeDef::Oversampling

Specify the Oversampling parameters. Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled.

Definition at line 199 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

FunctionalState ADC_InitTypeDef::OversamplingMode

Specify whether the oversampling feature is enabled or disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected

Definition at line 195 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InitTypeDef::Resolution

Configure the ADC resolution. This parameter can be a value of ADC Resolution

Definition at line 115 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ScanConvMode

Configure the sequencer of ADC groups regular and injected. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer). Scan direction is upward: from rank 1 to rank 'n'. This parameter can be a value of ADC sequencer scan mode

Definition at line 118 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_adc.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC_AnalogWDGConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_AnalogWDGConfTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC analog watchdog. More...

#include <stm32h7xx_hal_adc.h>

Data Fields

uint32_t | WatchdogNumber
uint32_t | WatchdogMode
uint32_t | Channel
FunctionalState | ITMode
uint32_t | HighThreshold
uint32_t | LowThreshold

Detailed Description

Structure definition of ADC analog watchdog.

Note:
The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. ADC state can be either: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected.

Definition at line 209 of file stm32h7xx_hal_adc.h.

Field Documentation

uint32_t ADC_AnalogWDGConfTypeDef::Channel

Select which ADC channel to monitor by analog watchdog. For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). This parameter can be a value of ADC Channels.

Definition at line 222 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::HighThreshold

Configure the ADC analog watchdog High threshold value. Depending of ADC resolution selected (16, 14, 12, 10 or 8 bits), this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.

Definition at line 230 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

FunctionalState ADC_AnalogWDGConfTypeDef::ITMode

Specify whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE

Definition at line 227 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::LowThreshold

Configures the ADC analog watchdog Low threshold value. Depending of ADC resolution selected (16, 14, 12, or 8 bits), this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.

Definition at line 234 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::WatchdogMode

Configure the ADC analog watchdog mode: single/all/none channels. For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel/all channels, ADC groups regular and/or injected. For Analog Watchdog 2 and 3: There is no configuration for all channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset channels group programmed with parameter 'Channel', set any other value to program the channel(s) to be monitored. This parameter can be a value of ADC Extended Analog Watchdog Mode.

Definition at line 216 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::WatchdogNumber

Select which ADC analog watchdog is monitoring the selected channel. For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) This parameter can be a value of ADC Extended Analog Watchdog Selection.

Definition at line 211 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_adc.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Error Code

Defines
ADC Error Code
ADC Exported Constants

Defines

#define | HAL_ADC_ERROR_NONE ((uint32_t)0x00)
#define | HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01)
#define | HAL_ADC_ERROR_OVR ((uint32_t)0x02)
#define | HAL_ADC_ERROR_DMA ((uint32_t)0x04)
#define | HAL_ADC_ERROR_JQOVF ((uint32_t)0x08)

Define Documentation

#define HAL_ADC_ERROR_DMA ((uint32_t)0x04)

DMA transfer error

Definition at line 304 of file stm32h7xx_hal_adc.h.

Referenced by ADC_DMAError(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01)

ADC IP internal error (problem of clocking, enable/disable, erroneous state, ...)

Definition at line 301 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_Enable(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADCEx_LinearCalibration_SetValue().

#define HAL_ADC_ERROR_JQOVF ((uint32_t)0x08)

Injected context queue overflow error

Definition at line 305 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define HAL_ADC_ERROR_NONE ((uint32_t)0x00)

No error

Definition at line 300 of file stm32h7xx_hal_adc.h.

#define HAL_ADC_ERROR_OVR ((uint32_t)0x02)

Overrun error

Definition at line 303 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC clock source and clock prescaler

Defines
ADC clock source and clock prescaler
ADC Exported Constants

Defines

#define | ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CCR_CKMODE_0)
#define | ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CCR_CKMODE_1)
#define | ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_CKMODE)
#define | ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
#define | ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
#define | ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
#define | ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000)
#define | ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_PRESC_0)
#define | ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_PRESC_1)
#define | ADC_CLOCK_ASYNC_DIV6 ((uint32_t)(ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))
#define | ADC_CLOCK_ASYNC_DIV8 ((uint32_t)(ADC_CCR_PRESC_2))
#define | ADC_CLOCK_ASYNC_DIV10 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_0))
#define | ADC_CLOCK_ASYNC_DIV12 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1))
#define | ADC_CLOCK_ASYNC_DIV16 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))
#define | ADC_CLOCK_ASYNC_DIV32 ((uint32_t)(ADC_CCR_PRESC_3))
#define | ADC_CLOCK_ASYNC_DIV64 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_0))
#define | ADC_CLOCK_ASYNC_DIV128 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1))
#define | ADC_CLOCK_ASYNC_DIV256 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))

Define Documentation

#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000)

ADC asynchronous clock not divided

Definition at line 321 of file stm32h7xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV10 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_0))

ADC asynchronous clock divided by 10

Definition at line 326 of file stm32h7xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV12 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1))

ADC asynchronous clock divided by 12

Definition at line 327 of file stm32h7xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV128 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1))

ADC asynchronous clock divided by 128

Definition at line 331 of file stm32h7xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV16 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))

ADC asynchronous clock divided by 16

Definition at line 328 of file stm32h7xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_PRESC_0)

ADC asynchronous clock divided by 2

Definition at line 322 of file stm32h7xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV256 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))

ADC asynchronous clock divided by 256

Definition at line 332 of file stm32h7xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV32 ((uint32_t)(ADC_CCR_PRESC_3))

ADC asynchronous clock divided by 32

Definition at line 329 of file stm32h7xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_PRESC_1)

ADC asynchronous clock divided by 4

Definition at line 323 of file stm32h7xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV6 ((uint32_t)(ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))

ADC asynchronous clock divided by 6

Definition at line 324 of file stm32h7xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV64 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_0))

ADC asynchronous clock divided by 64

Definition at line 330 of file stm32h7xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV8 ((uint32_t)(ADC_CCR_PRESC_2))

ADC asynchronous clock divided by 8

Definition at line 325 of file stm32h7xx_hal_adc.h.

#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CCR_CKMODE_0)

ADC synchronous clock derived from AHB clock not divided

Definition at line 313 of file stm32h7xx_hal_adc.h.

#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CCR_CKMODE_1)

ADC synchronous clock derived from AHB clock divided by 2

Definition at line 314 of file stm32h7xx_hal_adc.h.

#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_CKMODE)

ADC synchronous clock derived from AHB clock divided by 4

Definition at line 315 of file stm32h7xx_hal_adc.h.

#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1

Obsolete naming, kept for compatibility with some other devices

Definition at line 317 of file stm32h7xx_hal_adc.h.

#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2

Obsolete naming, kept for compatibility with some other devices

Definition at line 318 of file stm32h7xx_hal_adc.h.

#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4

Obsolete naming, kept for compatibility with some other devices

Definition at line 319 of file stm32h7xx_hal_adc.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Resolution

Defines
ADC Resolution
ADC Exported Constants

Defines

#define | ADC_RESOLUTION_16B ((uint32_t)0x00000000)
#define | ADC_RESOLUTION_14B ((uint32_t)ADC_CFGR_RES_0)
#define | ADC_RESOLUTION_12B ((uint32_t)ADC_CFGR_RES_1)
#define | ADC_RESOLUTION_10B ((uint32_t)(ADC_CFGR_RES_1 | ADC_CFGR_RES_0))
#define | ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_2)

Define Documentation

#define ADC_RESOLUTION_10B ((uint32_t)(ADC_CFGR_RES_1 | ADC_CFGR_RES_0))

ADC 10-bit resolution

Definition at line 343 of file stm32h7xx_hal_adc.h.

#define ADC_RESOLUTION_12B ((uint32_t)ADC_CFGR_RES_1)

ADC 12-bit resolution

Definition at line 342 of file stm32h7xx_hal_adc.h.

#define ADC_RESOLUTION_14B ((uint32_t)ADC_CFGR_RES_0)

ADC 14-bit resolution

Definition at line 341 of file stm32h7xx_hal_adc.h.

#define ADC_RESOLUTION_16B ((uint32_t)0x00000000)

ADC 16-bit resolution

Definition at line 340 of file stm32h7xx_hal_adc.h.

#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_2)

ADC 8-bit resolution

Definition at line 344 of file stm32h7xx_hal_adc.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC sequencer scan mode

Defines
ADC sequencer scan mode
ADC Exported Constants

Defines

#define | ADC_SCAN_DISABLE ((uint32_t)0x00000000)
#define | ADC_SCAN_ENABLE ((uint32_t)0x00000001)

Define Documentation

#define ADC_SCAN_DISABLE ((uint32_t)0x00000000)

Scan mode disabled

Definition at line 352 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SCAN_ENABLE ((uint32_t)0x00000001)

Scan mode enabled

Definition at line 353 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC group regular trigger source

Defines
ADC group regular trigger source
ADC Exported Constants

Defines

#define | ADC_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
#define | ADC_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
#define | ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
#define | ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
#define | ADC_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3)
#define | ADC_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
#define | ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
#define | ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
#define | ADC_EXTERNALTRIG_T3_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_HR1_ADCTRG1 ((uint32_t) ADC_CFGR_EXTSEL_4)
#define | ADC_EXTERNALTRIG_HR1_ADCTRG3 ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_LPTIM1_OUT ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1))
#define | ADC_EXTERNALTRIG_LPTIM2_OUT ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1| ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_LPTIM3_OUT ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2))
#define | ADC_SOFTWARE_START ((uint32_t)0x00000001)

Define Documentation

#define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))

Definition at line 368 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_HR1_ADCTRG1 ((uint32_t) ADC_CFGR_EXTSEL_4)

Definition at line 378 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_HR1_ADCTRG3 ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0))

Definition at line 379 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_LPTIM1_OUT ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1))

Definition at line 380 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_LPTIM2_OUT ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1| ADC_CFGR_EXTSEL_0))

Definition at line 381 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_LPTIM3_OUT ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2))

Definition at line 382 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))

Definition at line 376 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)

Definition at line 362 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)

Definition at line 363 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)

Definition at line 364 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))

Definition at line 371 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))

Definition at line 372 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))

Definition at line 365 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))

Definition at line 373 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T3_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))

Definition at line 377 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)

Definition at line 366 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))

Definition at line 367 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))

Definition at line 374 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))

Definition at line 375 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))

Definition at line 369 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3)

Definition at line 370 of file stm32h7xx_hal_adc.h.

#define ADC_SOFTWARE_START ((uint32_t)0x00000001)

Definition at line 384 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC group regular trigger edge (when external trigger is selected)

Defines
ADC group regular trigger edge (when external trigger is selected)
ADC Exported Constants

Defines

#define | ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0)
#define | ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1)
#define | ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN)

Define Documentation

#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1)

Regular conversions hardware trigger detection on the falling edge

Definition at line 394 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)

Regular conversions hardware trigger detection disabled

Definition at line 392 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0)

Regular conversions hardware trigger detection on the rising edge

Definition at line 393 of file stm32h7xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN)

Regular conversions hardware trigger detection on both the rising and falling edges

Definition at line 395 of file stm32h7xx_hal_adc.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC sequencer end of unitary conversion or sequence conversions

Defines
ADC sequencer end of unitary conversion or sequence conversions
ADC Exported Constants

Defines

#define | ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
#define | ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)

Define Documentation

#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)

End of sequence conversions flag

Definition at line 404 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_PollForConversion(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)

End of unitary conversion flag

Definition at line 403 of file stm32h7xx_hal_adc.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC overrun

Defines
ADC overrun
ADC Exported Constants

Defines

#define | ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000)
#define | ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR_OVRMOD)

Define Documentation

#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR_OVRMOD)

Data overwritten in case of overrun

Definition at line 413 of file stm32h7xx_hal_adc.h.

#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000)

Data preserved in case of overrun

Definition at line 412 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), and HAL_ADC_Start_IT().

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC group regular sequencer rank

Defines
ADC group regular sequencer rank
ADC Exported Constants

Defines

#define | ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
#define | ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
#define | ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
#define | ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
#define | ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
#define | ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
#define | ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
#define | ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
#define | ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
#define | ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
#define | ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
#define | ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
#define | ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
#define | ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
#define | ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
#define | ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)

Define Documentation

#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)

ADC regular conversion rank 1

Definition at line 421 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)

ADC regular conversion rank 10

Definition at line 430 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)

ADC regular conversion rank 11

Definition at line 431 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)

ADC regular conversion rank 12

Definition at line 432 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)

ADC regular conversion rank 13

Definition at line 433 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)

ADC regular conversion rank 14

Definition at line 434 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)

ADC regular conversion rank 15

Definition at line 435 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)

ADC regular conversion rank 16

Definition at line 436 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)

ADC regular conversion rank 2

Definition at line 422 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)

ADC regular conversion rank 3

Definition at line 423 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)

ADC regular conversion rank 4

Definition at line 424 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)

ADC regular conversion rank 5

Definition at line 425 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)

ADC regular conversion rank 6

Definition at line 426 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)

ADC regular conversion rank 7

Definition at line 427 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)

ADC regular conversion rank 8

Definition at line 428 of file stm32h7xx_hal_adc.h.

#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)

ADC regular conversion rank 9

Definition at line 429 of file stm32h7xx_hal_adc.h.

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STM32H753xx HAL User Manual: ADC Channels

Defines
ADC Channels
ADC Exported Constants

Defines

#define | ADC_CHANNEL_0 ((uint32_t)(0x00000000))
#define | ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ10_1))
#define | ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ10_2))
#define | ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
#define | ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ10_3))
#define | ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1))
#define | ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2))
#define | ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
#define | ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ10_4))
#define | ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1))
#define | ADC_CHANNEL_19 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1| ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_17
#define | ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_18
#define | ADC_CHANNEL_VREFINT ADC_CHANNEL_19
#define | ADC_CHANNEL_DAC1CH1_ADC2 (ADC_CHANNEL_16)
#define | ADC_CHANNEL_DAC1CH2_ADC2 (ADC_CHANNEL_17)

Define Documentation

#define ADC_CHANNEL_0 ((uint32_t)(0x00000000))

Definition at line 444 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ10_0))

Definition at line 445 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1))

Definition at line 454 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))

Definition at line 455 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2))

Definition at line 456 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))

Definition at line 457 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))

Definition at line 458 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))

Definition at line 459 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ10_4))

Definition at line 460 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0))

Definition at line 461 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1))

Definition at line 462 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_19 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1| ADC_SQR3_SQ10_0))

Definition at line 463 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ10_1))

Definition at line 446 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))

Definition at line 447 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ10_2))

Definition at line 448 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))

Definition at line 449 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))

Definition at line 450 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))

Definition at line 451 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ10_3))

Definition at line 452 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0))

Definition at line 453 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_DAC1CH1_ADC2 (ADC_CHANNEL_16)

ADC internal channel connected to DAC1 channel 1, channel specific to ADC2

Definition at line 471 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_DAC1CH2_ADC2 (ADC_CHANNEL_17)

ADC internal channel connected to DAC1 channel 2, channel specific to ADC2

Definition at line 472 of file stm32h7xx_hal_adc.h.

#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_18

Definition at line 467 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_17

Definition at line 466 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_VREFINT ADC_CHANNEL_19

Definition at line 468 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Conversion Data Management

Defines
ADC Conversion Data Management
ADC Exported Constants

Defines

#define | ADC_CONVERSIONDATA_DR ((uint32_t)0x00000000)
#define | ADC_CONVERSIONDATA_DFSDM ((uint32_t)ADC_CFGR_DMNGT_1)
#define | ADC_CONVERSIONDATA_DMA_ONESHOT ((uint32_t)ADC_CFGR_DMNGT_0)
#define | ADC_CONVERSIONDATA_DMA_CIRCULAR ((uint32_t)(ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1))

Define Documentation

#define ADC_CONVERSIONDATA_DFSDM ((uint32_t)ADC_CFGR_DMNGT_1)

DFSDM mode selected

Definition at line 482 of file stm32h7xx_hal_adc.h.

#define ADC_CONVERSIONDATA_DMA_CIRCULAR ((uint32_t)(ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1))

DMA circular mode selected

Definition at line 484 of file stm32h7xx_hal_adc.h.

#define ADC_CONVERSIONDATA_DMA_ONESHOT ((uint32_t)ADC_CFGR_DMNGT_0)

DMA one shot mode selected

Definition at line 483 of file stm32h7xx_hal_adc.h.

#define ADC_CONVERSIONDATA_DR ((uint32_t)0x00000000)

Regular Conversion data stored in DR register only

Definition at line 481 of file stm32h7xx_hal_adc.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Private Macros

Defines
ADC Private Macros
ADC

Defines

#define | IS_ADC_CONVERSIONDATAMGT(DATA)
Verify the ADC data conversion setting.
#define | ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)
Test if conversion trigger of regular group is software start or external trigger.
#define | ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)
Returns resolution bits in CFGR register: RES[1:0].
#define | ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
Clear ADC error code (set it to error code: "no error")
#define | ADC_IS_ENABLE(__HANDLE__)
Verification of ADC state: enabled or disabled.
#define | ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__)
Check if no conversion on going on regular group.
#define | ADC_STATE_CLR_SET MODIFY_REG
Simultaneously clears and sets specific bits of the handle State.
#define | IS_ADC_RANGE(RESOLUTION, ADC_VALUE)
Verify that a given value is aligned with the ADC resolution range.
#define | IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
Verify the length of the scheduled regular conversions group.
#define | IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
Verify the number of scheduled regular conversions in discontinuous mode.
#define | IS_ADC_CLOCKPRESCALER(ADC_CLOCK)
Verify the ADC clock setting.
#define | IS_ADC_RESOLUTION(RESOLUTION)
Verify the ADC resolution setting.
#define | IS_ADC_RESOLUTION_8_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B))
Verify the ADC resolution setting when limited to 8 bits.
#define | IS_ADC_SCAN_MODE(SCAN_MODE)
Verify the ADC scan mode.
#define | IS_ADC_EXTTRIG_EDGE(EDGE)
Verify the ADC edge trigger setting for regular group.
#define | IS_ADC_EXTTRIG(REGTRIG)
Verify the ADC regular conversions external trigger.
#define | IS_ADC_EOC_SELECTION(EOC_SELECTION)
Verify the ADC regular conversions check for converted data availability.
#define | IS_ADC_OVERRUN(OVR)
Verify the ADC regular conversions overrun handling.
#define | IS_ADC_SAMPLE_TIME(TIME)
Verify the ADC conversions sampling time.
#define | IS_ADC_REGULAR_RANK(__CHANNEL__)
Verify the ADC regular channel setting.

Define Documentation

#define ADC_CLEAR_ERRORCODE ( __HANDLE__ ) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)

Clear ADC error code (set it to error code: "no error")

Parameters:
__HANDLE__,: ADC handle
Return values:
None

Definition at line 532 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_GET_RESOLUTION ( __HANDLE__ ) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)

Returns resolution bits in CFGR register: RES[1:0].

Returned value is among parameters in ADC Resolution.

Parameters:
__HANDLE__,: ADC handle
Return values:
Parameter of ADC Resolution set.

Definition at line 525 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_IS_CONVERSION_ONGOING_REGULAR ( __HANDLE__ )
Value:
(( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET             \
        ) ? RESET : SET)

Check if no conversion on going on regular group.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (conversion is on going) or RESET (no conversion is on going)

Definition at line 549 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), and HAL_ADCEx_RegularMultiModeStop_DMA().

#define ADC_IS_ENABLE ( __HANDLE__ )
Value:
(( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
          ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)                  \
        ) ? SET : RESET)

Verification of ADC state: enabled or disabled.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (ADC enabled) or RESET (ADC disabled)

Definition at line 539 of file stm32h7xx_hal_adc.h.

Referenced by ADC_Disable(), ADC_Enable(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_DisableVoltageRegulator(), HAL_ADCEx_EnterADCDeepPowerDownMode(), HAL_ADCEx_InjectedConfigChannel(), and HAL_ADCEx_MultiModeConfigChannel().

#define ADC_IS_SOFTWARE_START_REGULAR ( __HANDLE__ ) (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)

Test if conversion trigger of regular group is software start or external trigger.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (software start) or RESET (external trigger)

Definition at line 516 of file stm32h7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), and HAL_ADCEx_InjectedPollForConversion().

#define ADC_STATE_CLR_SET MODIFY_REG

Simultaneously clears and sets specific bits of the handle State.

Note:
: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), the first parameter is the ADC handle State, the second parameter is the bit field to clear, the third and last parameter is the bit field to set
Return values:
None

Definition at line 560 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define IS_ADC_CLOCKPRESCALER ( ADC_CLOCK )
Value:
(((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
                                          ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
                                          ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1)     || \
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2)     || \
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4)     || \
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6)     || \
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8)     || \
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10)    || \
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12)    || \
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16)    || \
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32)    || \
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64)    || \
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128)   || \
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256) )

Verify the ADC clock setting.

Parameters:
ADC_CLOCK : programmed ADC clock.
Return values:
SET (ADC_CLOCK is a valid value) or RESET (ADC_CLOCK is invalid)

Definition at line 594 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_CONVERSIONDATAMGT ( DATA )
Value:
((((DATA) == ADC_CONVERSIONDATA_DR))          || \
    (((DATA) == ADC_CONVERSIONDATA_DFSDM))       || \
    (((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \
    (((DATA) == ADC_CONVERSIONDATA_DMA_CIRCULAR)))

Verify the ADC data conversion setting.

Parameters:
DATA : programmed DATA conversion mode.
Return values:
SET (DATA is a valid value) or RESET (DATA is invalid)

Definition at line 504 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_EOC_SELECTION ( EOC_SELECTION )
Value:
(((EOC_SELECTION) == ADC_EOC_SINGLE_CONV)    || \
                                             ((EOC_SELECTION) == ADC_EOC_SEQ_CONV))

Verify the ADC regular conversions check for converted data availability.

Parameters:
EOC_SELECTION,: converted data availability check.
Return values:
SET (EOC_SELECTION is a valid value) or RESET (EOC_SELECTION is invalid)

Definition at line 679 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADC_IRQHandler().

#define IS_ADC_EXTTRIG ( REGTRIG )
Value:
(((REGTRIG) == ADC_EXTERNALTRIG_T1_CC1)        || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC2)        || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC3)        || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_T2_CC2)        || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO)       || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_T4_CC4)        || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11)      || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_T8_TRGO)       || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_T8_TRGO2)      || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO)       || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2)      || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_T2_TRGO)       || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_T4_TRGO)       || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_T6_TRGO)       || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_T15_TRGO)      || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_T3_CC4)        || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_HR1_ADCTRG1)   || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_HR1_ADCTRG3)   || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_LPTIM1_OUT)    || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_LPTIM2_OUT)    || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_LPTIM3_OUT)    || \
                                 ((REGTRIG) == ADC_SOFTWARE_START)           )

Verify the ADC regular conversions external trigger.

Parameters:
REGTRIG,: programmed ADC regular conversions external trigger.
Return values:
SET (REGTRIG is a valid value) or RESET (REGTRIG is invalid)

Definition at line 651 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_EXTTRIG_EDGE ( EDGE )
Value:
(((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )

Verify the ADC edge trigger setting for regular group.

Parameters:
EDGE,: programmed ADC edge trigger setting.
Return values:
SET (EDGE is a valid value) or RESET (EDGE is invalid)

Definition at line 641 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_MultiModeStart_DMA().

#define IS_ADC_OVERRUN ( OVR )
Value:
(((OVR) == ADC_OVR_DATA_PRESERVED)  || \
                             ((OVR) == ADC_OVR_DATA_OVERWRITTEN)  )

Verify the ADC regular conversions overrun handling.

Parameters:
OVR,: ADC regular conversions overrun handling.
Return values:
SET (OVR is a valid value) or RESET (OVR is invalid)

Definition at line 687 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_RANGE | ( | RESOLUTION,
 |  | ADC_VALUE
 | ) |
Value:
((((RESOLUTION) == ADC_RESOLUTION_16B) && ((ADC_VALUE) <= ((uint32_t)0xFFFF))) || \
    (((RESOLUTION) == ADC_RESOLUTION_14B) && ((ADC_VALUE) <= ((uint32_t)0x3FFF))) || \
    (((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
    (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
    (((RESOLUTION) == ADC_RESOLUTION_8B)  && ((ADC_VALUE) <= ((uint32_t)0x00FF))))

Verify that a given value is aligned with the ADC resolution range.

Parameters:
RESOLUTION,: ADC resolution (16, 14, 12, 10 or 8 bits).
ADC_VALUE,: value checked against the resolution.
Return values:
SET (ADC_VALUE in line with RESOLUTION) or RESET (ADC_VALUE not in line with RESOLUTION)

Definition at line 568 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_REGULAR_DISCONT_NUMBER ( NUMBER ) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))

Verify the number of scheduled regular conversions in discontinuous mode.

Parameters:
NUMBER,: number of scheduled regular conversions in discontinuous mode.
Return values:
SET (NUMBER is within the maximum number of regular conversions in discontinous mode) or RESET (NUMBER is null or too large)

Definition at line 587 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_REGULAR_NB_CONV ( LENGTH ) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))

Verify the length of the scheduled regular conversions group.

Parameters:
LENGTH,: number of programmed conversions.
Return values:
SET (LENGTH is within the maximum number of possible programmable regular conversions) or RESET (LENGTH is null or too large)

Definition at line 580 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_REGULAR_RANK ( __CHANNEL__ )
Value:
(((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_16)   )

Verify the ADC regular channel setting.

Parameters:
__CHANNEL__,: programmed ADC regular channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 709 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define IS_ADC_RESOLUTION ( RESOLUTION )
Value:
(((RESOLUTION) == ADC_RESOLUTION_16B) || \
                                       ((RESOLUTION) == ADC_RESOLUTION_14B) || \
                                       ((RESOLUTION) == ADC_RESOLUTION_12B) || \
                                       ((RESOLUTION) == ADC_RESOLUTION_10B) || \
                                       ((RESOLUTION) == ADC_RESOLUTION_8B)    )

Verify the ADC resolution setting.

Parameters:
RESOLUTION,: programmed ADC resolution.
Return values:
SET (RESOLUTION is a valid value) or RESET (RESOLUTION is invalid)

Definition at line 615 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_RESOLUTION_8_BITS ( RESOLUTION ) (((RESOLUTION) == ADC_RESOLUTION_8B))

Verify the ADC resolution setting when limited to 8 bits.

Parameters:
RESOLUTION,: programmed ADC resolution when limited to 8 bits.
Return values:
SET (RESOLUTION is a valid value) or RESET (RESOLUTION is invalid)

Definition at line 626 of file stm32h7xx_hal_adc.h.

#define IS_ADC_SAMPLE_TIME ( TIME )
Value:
(((TIME) == ADC_SAMPLETIME_1CYCLE_5)    || \
                                  ((TIME) == ADC_SAMPLETIME_2CYCLES_5)   || \
                                  ((TIME) == ADC_SAMPLETIME_8CYCLES_5)  || \
                                  ((TIME) == ADC_SAMPLETIME_16CYCLES_5)  || \
                                  ((TIME) == ADC_SAMPLETIME_32CYCLES_5)  || \
                                  ((TIME) == ADC_SAMPLETIME_64CYCLES_5)  || \
                                  ((TIME) == ADC_SAMPLETIME_387CYCLES_5) || \
                                  ((TIME) == ADC_SAMPLETIME_810CYCLES_5)   )

Verify the ADC conversions sampling time.

Parameters:
TIME,: ADC conversions sampling time.
Return values:
SET (TIME is a valid value) or RESET (TIME is invalid)

Definition at line 695 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_SCAN_MODE ( SCAN_MODE )
Value:
(((SCAN_MODE) == ADC_SCAN_DISABLE) || \
                                     ((SCAN_MODE) == ADC_SCAN_ENABLE)    )

Verify the ADC scan mode.

Parameters:
SCAN_MODE,: programmed ADC scan mode.
Return values:
SET (SCAN_MODE is valid) or RESET (SCAN_MODE is invalid)

Definition at line 633 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Exported Macros

Defines
ADC Exported Macros
ADC

Defines

#define | __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
Reset ADC handle state.
#define | __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Checks if the specified ADC interrupt source is enabled or disabled.
#define | __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Enable an ADC interrupt.
#define | __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Disable an ADC interrupt.
#define | __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
Checks whether the specified ADC flag is set or not.
#define | __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
Clear a specified ADC flag.

Define Documentation

#define __HAL_ADC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR) = (__FLAG__))

Clear a specified ADC flag.

Parameters:
__HANDLE__,: ADC handle
__FLAG__,: ADC flag to clear This parameter can be one of the following values:
  • ADC_FLAG_RDY ADC Ready (ADRDY) flag
  • ADC_FLAG_EOSMP ADC End of Sampling flag
  • ADC_FLAG_EOC ADC End of Regular Conversion flag
  • ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
  • ADC_FLAG_OVR ADC overrun flag
  • ADC_FLAG_JEOC ADC End of Injected Conversion flag
  • ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
  • ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
  • ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
  • ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
  • ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag
Note:
: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR)
Return values:
None

Definition at line 877 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConversionStop(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define __HAL_ADC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))

Disable an ADC interrupt.

Parameters:
__HANDLE__,: ADC handle
__INTERRUPT__,: ADC Interrupt to disable
  • ADC_IT_RDY ADC Ready (ADRDY) interrupt source
  • ADC_IT_EOSMP ADC End of Sampling interrupt source
  • ADC_IT_EOC ADC End of Regular Conversion interrupt source
  • ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
  • ADC_IT_OVR ADC overrun interrupt source
  • ADC_IT_JEOC ADC End of Injected Conversion interrupt source
  • ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
  • ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
  • ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
  • ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
  • ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source
Return values:
None

Definition at line 836 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define __HAL_ADC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))

Enable an ADC interrupt.

Parameters:
__HANDLE__,: ADC handle
__INTERRUPT__,: ADC Interrupt to enable This parameter can be one of the following values:
  • ADC_IT_RDY ADC Ready (ADRDY) interrupt source
  • ADC_IT_EOSMP ADC End of Sampling interrupt source
  • ADC_IT_EOC ADC End of Regular Conversion interrupt source
  • ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
  • ADC_IT_OVR ADC overrun interrupt source
  • ADC_IT_JEOC ADC End of Injected Conversion interrupt source
  • ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
  • ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
  • ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
  • ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
  • ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source
Return values:
None

Definition at line 817 of file stm32h7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define __HAL_ADC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))

Checks whether the specified ADC flag is set or not.

Parameters:
__HANDLE__,: ADC handle
__FLAG__,: ADC flag to check This parameter can be one of the following values:
  • ADC_FLAG_RDY ADC Ready (ADRDY) flag
  • ADC_FLAG_EOSMP ADC End of Sampling flag
  • ADC_FLAG_EOC ADC End of Regular Conversion flag
  • ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
  • ADC_FLAG_OVR ADC overrun flag
  • ADC_FLAG_JEOC ADC End of Injected Conversion flag
  • ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
  • ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
  • ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
  • ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
  • ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 856 of file stm32h7xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Enable(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define __HAL_ADC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(( ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)      \
     )? SET : RESET                                                            \
    )

Checks if the specified ADC interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: ADC handle
__INTERRUPT__,: ADC interrupt source to check This parameter can be one of the following values:
  • ADC_IT_RDY ADC Ready (ADRDY) interrupt source
  • ADC_IT_EOSMP ADC End of Sampling interrupt source
  • ADC_IT_EOC ADC End of Regular Conversion interrupt source
  • ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
  • ADC_IT_OVR ADC overrun interrupt source
  • ADC_IT_JEOC ADC End of Injected Conversion interrupt source
  • ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
  • ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
  • ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
  • ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
  • ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source
Return values:
State of interruption (SET or RESET)

Definition at line 794 of file stm32h7xx_hal_adc.h.

#define __HAL_ADC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)

Reset ADC handle state.

Parameters:
__HANDLE__,: ADC handle
Return values:
None

Definition at line 774 of file stm32h7xx_hal_adc.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Extended Private Constants

Defines
ADC Extended Private Constants
ADCEx

Defines

#define | ADC_JSQR_FIELDS
#define | ADC_CFGR2_INJ_FIELDS
#define | ADC_CALIBRATION_TIMEOUT ((uint32_t) 64000)

Define Documentation

#define ADC_CALIBRATION_TIMEOUT ((uint32_t) 64000)

ADC calibration time-out value

Definition at line 101 of file stm32h7xx_hal_adc_ex.c.

Referenced by HAL_ADCEx_Calibration_Start(), HAL_ADCEx_LinearCalibration_GetValue(), and HAL_ADCEx_LinearCalibration_SetValue().

#define ADC_CFGR2_INJ_FIELDS
Value:
((uint32_t)(ADC_CFGR2_JOVSE | ADC_CFGR2_OSR  |\
                                          ADC_CFGR2_OVSS ))

ADC_CFGR2 injected oversampling parameters that can be updated when no conversion is on-going (neither regular nor injected)

Definition at line 89 of file stm32h7xx_hal_adc_ex.c.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_JSQR_FIELDS
Value:
((uint32_t)(ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
                                     ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
                                     ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 ))

ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled

Definition at line 84 of file stm32h7xx_hal_adc_ex.c.

Referenced by HAL_ADCEx_InjectedConfigChannel().

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Extended Input and Output operation functions

Functions
Extended Input and Output operation functions
ADC Extended Exported Functions

Extended IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
uint32_t | HAL_ADCEx_Calibration_GetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Get the calibration factor from automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_LinearCalibration_GetValue (ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer)
Get the calibration factor from automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_Calibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set the calibration factor to overwrite automatic conversion result, ADC must be enabled and no conversion on going.
HAL_StatusTypeDef | HAL_ADCEx_LinearCalibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer)
Set the linear calibration factor.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels and disable ADC peripheral if no regular conversion is on going.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group with interruption.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion, disable ADC peripheral if no regular conversion is on going.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStart_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start MultiMode conversion and transfer regular results through DMA.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADCEx_MultiModeGetValue (ADC_HandleTypeDef *hadc)
Return the last ADC Master and Slave regular conversions results when in multimode configuration.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non-blocking mode.
__weak void | HAL_ADCEx_InjectedQueueOverflowCallback (ADC_HandleTypeDef *hadc)
Injected context queue overflow callback.
__weak void | HAL_ADCEx_LevelOutOfWindow2Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 2 callback in non-blocking mode.
__weak void | HAL_ADCEx_LevelOutOfWindow3Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 3 callback in non-blocking mode.
__weak void | HAL_ADCEx_EndOfSamplingCallback (ADC_HandleTypeDef *hadc)
End Of Sampling callback in non-blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of ADC groups regular and injected, disable interrution of end-of-conversion, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularMultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop DMA-based MultiMode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.

Detailed Description

Extended IO operation functions.

 ===============================================================================
             ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:

      (+) Perform the ADC self-calibration for single or differential ending.
      (+) Get calibration factors for single or differential ending.
      (+) Set calibration factors for single or differential ending.

      (+) Start conversion of injected group.
      (+) Stop conversion of injected group.
      (+) Poll for conversion complete on injected group.
      (+) Get result of injected channel conversion.
      (+) Start conversion of injected group and enable interruptions.
      (+) Stop conversion of injected group and disable interruptions.

      (+) When multimode feature is available, start multimode and enable DMA transfer.
      (+) Stop multimode and disable ADC DMA transfer.
      (+) Get result of multimode conversion.

Function Documentation

uint32_t HAL_ADCEx_Calibration_GetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | SingleDiff
 | ) |  |

Get the calibration factor from automatic conversion result.

Parameters:
hadc,: ADC handle.
SingleDiff,: Selection of single-ended or differential input This parameter can be one of the following values:
  • ADC_SINGLE_ENDED Channel in mode input single ended
  • ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
Return values:
HAL state

Definition at line 240 of file stm32h7xx_hal_adc_ex.c.

References ADC_CALFACT_DIFF_GET, ADC_DIFFERENTIAL_ENDED, assert_param, ADC_HandleTypeDef::Instance, and IS_ADC_SINGLE_DIFFERENTIAL.

HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | SingleDiff,
 |  | uint32_t | CalibrationFactor
 | ) |  |

Set the calibration factor to overwrite automatic conversion result, ADC must be enabled and no conversion on going.

Parameters:
hadc,: ADC handle.
SingleDiff,: Selection of single-ended or differential input. This parameter can be one of the following values:
  • ADC_SINGLE_ENDED Channel in mode input single ended
  • ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
CalibrationFactor,: Calibration factor (coded on 7 bits maximum)
Return values:
HAL state

Definition at line 304 of file stm32h7xx_hal_adc_ex.c.

References ADC_CALFACT_DIFF_SET, ADC_DIFFERENTIAL_ENDED, ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED, ADC_IS_ENABLE, assert_param, HAL_ADC_STATE_ERROR_CONFIG, ADC_HandleTypeDef::Instance, IS_ADC_CALFACT, IS_ADC_SINGLE_DIFFERENTIAL, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_Calibration_Start | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | CalibrationMode,
 |  | uint32_t | SingleDiff
 | ) |  |

Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).

Parameters:
hadc ADC handle
CalibrationMode,: Selection of Calibration Mode This parameter can be one of the following values:
  • ADC_CALIB_OFFSET: ADC calibration in offset mode
  • ADC_CALIB_OFFSET_LINEARITY: ADC calibration in Linear offset mode
SingleDiff,: Selection of single-ended or differential input This parameter can be one of the following values:
  • ADC_SINGLE_ENDED: Channel in mode input single ended
  • ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
Return values:
HAL status

Definition at line 162 of file stm32h7xx_hal_adc_ex.c.

References ADC_CALIBRATION_TIMEOUT, ADC_Disable(), ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, IS_ADC_SINGLE_DIFFERENTIAL, and ADC_HandleTypeDef::State.

void HAL_ADCEx_EndOfSamplingCallback ( ADC_HandleTypeDef * hadc )

End Of Sampling callback in non-blocking mode.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 1354 of file stm32h7xx_hal_adc_ex.c.

Referenced by HAL_ADC_IRQHandler().

void HAL_ADCEx_InjectedConvCpltCallback ( ADC_HandleTypeDef * hadc )

Injected conversion complete callback in non-blocking mode.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 1288 of file stm32h7xx_hal_adc_ex.c.

Referenced by HAL_ADC_IRQHandler().

uint32_t HAL_ADCEx_InjectedGetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | InjectedRank
 | ) |  |

Get ADC injected group conversion result.

Note:
Reading register JDRx automatically clears ADC flag JEOC (ADC group injected end of unitary conversion).
This function does not clear ADC flag JEOS (ADC group injected end of sequence conversion) Occurrence of flag JEOS rising:
  • If sequencer is composed of 1 rank, flag JEOS is equivalent to flag JEOC.
  • If sequencer is composed of several ranks, during the scan sequence flag JEOC only is raised, at the end of the scan sequence both flags JEOC and EOS are raised. Flag JEOS must not be cleared by this function because it would not be compliant with low power features (feature low power auto-wait, not available on all STM32 families). To clear this flag, either use function: in programming model IT: HAL_ADC_IRQHandler(), in programming model polling: HAL_ADCEx_InjectedPollForConversion() or __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
Parameters:
hadc,: ADC handle
InjectedRank,: the converted ADC injected rank. This parameter can be one of the following values:
  • ADC_INJECTED_RANK_1 ADC group injected rank 1
  • ADC_INJECTED_RANK_2 ADC group injected rank 2
  • ADC_INJECTED_RANK_3 ADC group injected rank 3
  • ADC_INJECTED_RANK_4 ADC group injected rank 4
Return values:
ADC group injected conversion data

Definition at line 1252 of file stm32h7xx_hal_adc_ex.c.

References ADC_INJECTED_RANK_1, ADC_INJECTED_RANK_2, ADC_INJECTED_RANK_3, ADC_INJECTED_RANK_4, assert_param, ADC_HandleTypeDef::Instance, and IS_ADC_INJECTED_RANK.

HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | Timeout
 | ) |  |

Wait for injected group conversion to be completed.

Parameters:
hadc,: ADC handle
Timeout,: Timeout value in millisecond.
Note:
Depending on hadc->Init.EOCSelection, JEOS or JEOC is checked and cleared depending on AUTDLY bit status.
Return values:
HAL status

Definition at line 620 of file stm32h7xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, ADC_EOC_SEQ_CONV, ADC_FLAG_EOC, ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE, ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE, ADC_IS_SOFTWARE_START_INJECTED, ADC_IS_SOFTWARE_START_REGULAR, ADC_MASTER_REGISTER, assert_param, ADC_InitTypeDef::EOCSelection, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

void HAL_ADCEx_InjectedQueueOverflowCallback ( ADC_HandleTypeDef * hadc )

Injected context queue overflow callback.

Note:
This callback is called if injected context queue is enabled (parameter "QueueInjectedContext" in injected channel configuration) and if a new injected context is set when queue is full (maximum 2 contexts).
Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 1308 of file stm32h7xx_hal_adc_ex.c.

Referenced by HAL_ADC_IRQHandler().

HAL_StatusTypeDef HAL_ADCEx_InjectedStart ( ADC_HandleTypeDef * hadc )

Enable ADC, start conversion of injected group.

Note:
Interruptions enabled in this function: None.
Case of multimode enabled when multimode feature is available: HAL_ADCEx_InjectedStart() API must be called for ADC slave first, then for ADC master. For ADC slave, ADC is enabled only (conversion is not started). For ADC master, ADC is enabled and multimode conversion is started.
Parameters:
hadc,: ADC handle.
Return values:
HAL status

Definition at line 436 of file stm32h7xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, ADC12_NONMULTIMODE_OR_MULTIMODEMASTER, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE, ADC_IS_CONVERSION_ONGOING_INJECTED, ADC_STATE_CLR_SET, assert_param, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_JQOVF, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT ( ADC_HandleTypeDef * hadc )

Enable ADC, start conversion of injected group with interruption.

Note:
Interruptions enabled in this function according to initialization setting : JEOC (end of conversion) or JEOS (end of sequence)
Case of multimode enabled (when multimode feature is enabled): HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first, then for ADC master. For ADC slave, ADC is enabled only (conversion is not started). For ADC master, ADC is enabled and multimode conversion is started.
Parameters:
hadc,: ADC handle.
Return values:
HAL status.

Definition at line 774 of file stm32h7xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_ENABLE_IT, ADC12_NONMULTIMODE_OR_MULTIMODEMASTER, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_EOC_SEQ_CONV, ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_FLAG_JQOVF, ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE, ADC_IS_CONVERSION_ONGOING_INJECTED, ADC_IT_JEOC, ADC_IT_JEOS, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::EOCSelection, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_JQOVF, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStop ( ADC_HandleTypeDef * hadc )

Stop conversion of injected channels and disable ADC peripheral if no regular conversion is on going.

Note:
If ADC must be disabled and if conversion is on going on regular group, function HAL_ADC_Stop must be used to stop both injected and regular groups, and disable the ADC.
If injected group mode auto-injection is enabled, function HAL_ADC_Stop must be used.
In case of multimode enabled (when multimode feature is available), HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave. For ADC master, conversion is stopped and ADC is disabled. For ADC slave, ADC is disabled only (conversion stop of ADC master has already stopped conversion of ADC slave).
Parameters:
hadc,: ADC handle.
Return values:
HAL status

Definition at line 564 of file stm32h7xx_hal_adc_ex.c.

References ADC_ConversionStop(), ADC_Disable(), ADC_INJECTED_GROUP, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT ( ADC_HandleTypeDef * hadc )

Stop conversion of injected channels, disable interruption of end-of-conversion, disable ADC peripheral if no regular conversion is on going.

Note:
If ADC must be disabled and if conversion is on going on regular group, function HAL_ADC_Stop must be used to stop both injected and regular groups, and disable the ADC.
If injected group mode auto-injection is enabled, function HAL_ADC_Stop must be used.
Case of multimode enabled (when multimode feature is available): HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first, then for ADC slave. For ADC master, conversion is stopped and ADC is disabled. For ADC slave, ADC is disabled only (conversion stop of ADC master has already stopped conversion of ADC slave).
In case of auto-injection mode, HAL_ADC_Stop() must be used.
Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 922 of file stm32h7xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_FLAG_JQOVF, ADC_INJECTED_GROUP, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_IT_JEOC, ADC_IT_JEOS, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

void HAL_ADCEx_LevelOutOfWindow2Callback ( ADC_HandleTypeDef * hadc )

Analog watchdog 2 callback in non-blocking mode.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 1323 of file stm32h7xx_hal_adc_ex.c.

Referenced by HAL_ADC_IRQHandler().

void HAL_ADCEx_LevelOutOfWindow3Callback ( ADC_HandleTypeDef * hadc )

Analog watchdog 3 callback in non-blocking mode.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 1338 of file stm32h7xx_hal_adc_ex.c.

Referenced by HAL_ADC_IRQHandler().

HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | LinearCalib_Buffer
 | ) |  |

Get the calibration factor from automatic conversion result.

Parameters:
hadc,: ADC handle
LinearCalib_Buffer,: Linear calibration factor
Return values:
HAL state

Definition at line 263 of file stm32h7xx_hal_adc_ex.c.

References ADC_CALIBRATION_TIMEOUT, ADC_Enable(), assert_param, and ADC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | LinearCalib_Buffer
 | ) |  |

Set the linear calibration factor.

Parameters:
hadc,: ADC handle
LinearCalib_Buffer,: Linear calibration factor
Return values:
HAL state

Definition at line 353 of file stm32h7xx_hal_adc_ex.c.

References ADC_CALIBRATION_TIMEOUT, ADC_STAB_DELAY_US, assert_param, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

uint32_t HAL_ADCEx_MultiModeGetValue ( ADC_HandleTypeDef * hadc )

Return the last ADC Master and Slave regular conversions results when in multimode configuration.

Parameters:
hadc,: ADC handle of ADC Master (handle of ADC Slave must not be used)
Return values:
The converted data values.

Definition at line 1209 of file stm32h7xx_hal_adc_ex.c.

References ADC12_COMMON_REGISTER, assert_param, and ADC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

Enable ADC, start MultiMode conversion and transfer regular results through DMA.

Note:
Multimode must have been previously configured using HAL_ADCEx_MultiModeConfigChannel() function. Interruptions enabled in this function: overrun, DMA half transfer, DMA transfer complete. Each of these interruptions has its dedicated callback function.
State field of Slave ADC handle is not updated in this configuration: user should not rely on it for information related to Slave regular conversions.
Parameters:
hadc,: ADC handle of ADC master (handle of ADC slave must not be used)
pData,: Destination Buffer address.
Length,: Length of data to be transferred from ADC peripheral to memory (in bytes).
Return values:
HAL status

Definition at line 987 of file stm32h7xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE_IT, ADC12_COMMON_REGISTER, ADC_CLEAR_ERRORCODE, ADC_DMAConvCplt(), ADC_DMAError(), ADC_DMAHalfConvCplt(), ADC_Enable(), ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_IT_OVR, ADC_MULTI_SLAVE, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ContinuousConvMode, ADC_HandleTypeDef::DMA_Handle, ADC_InitTypeDef::ExternalTrigConvEdge, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_DMA_Start_IT(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_EXTTRIG_EDGE, ADC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA ( ADC_HandleTypeDef * hadc )

Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.

Note:
Multimode is kept enabled after this function. MultiMode DMA bits (MDMA and DMACFG bits of common CCR register) are maintained. To disable Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can resort to HAL_ADCEx_DisableMultiMode() API.
In case of DMA configured in circular mode, function HAL_ADC_Stop_DMA() must be called after this function with handle of ADC slave, to properly disable the DMA channel.
Parameters:
hadc,: ADC handle of ADC master (handle of ADC slave must not be used)
Return values:
HAL status

Definition at line 1101 of file stm32h7xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_IT_OVR, ADC_MULTI_SLAVE, ADC_REGULAR_INJECTED_GROUP, ADC_STATE_CLR_SET, ADC_STOP_CONVERSION_TIMEOUT, assert_param, ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), HAL_GetTick(), ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA ( ADC_HandleTypeDef * hadc )

Stop DMA-based MultiMode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.

Note:
MultiMode is kept enabled after this function. MultiMode DMA bits (MDMA and DMACFG bits of common CCR register) are maintained. To disable MultiMode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can resort to HAL_ADCEx_DisableMultiMode() API.
In case of DMA configured in circular mode, function HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of ADC slave, to properly disable the DMA channel.
Parameters:
hadc,: ADC handle of ADC master (handle of ADC slave must not be used)
Return values:
HAL status

Definition at line 1575 of file stm32h7xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IS_CONVERSION_ONGOING_INJECTED, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_IT_OVR, ADC_MULTI_SLAVE, ADC_REGULAR_GROUP, ADC_STATE_CLR_SET, ADC_STOP_CONVERSION_TIMEOUT, assert_param, ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), HAL_GetTick(), ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_RegularStop ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral if no conversion is on going on injected group.

Parameters:
hadc,: ADC handle
Return values:
HAL status.

Definition at line 1371 of file stm32h7xx_hal_adc_ex.c.

References ADC_ConversionStop(), ADC_Disable(), ADC_IS_CONVERSION_ONGOING_INJECTED, ADC_REGULAR_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral if no conversion is on going on injected group.

Note:
HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only. For multimode (when multimode feature is available), HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
Parameters:
hadc,: ADC handle
Return values:
HAL status.

Definition at line 1488 of file stm32h7xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IS_CONVERSION_ONGOING_INJECTED, ADC_IT_OVR, ADC_REGULAR_GROUP, ADC_STATE_CLR_SET, assert_param, ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of ADC groups regular and injected, disable interrution of end-of-conversion, disable ADC peripheral if no conversion is on going on injected group.

Parameters:
hadc,: ADC handle
Return values:
HAL status.

Definition at line 1428 of file stm32h7xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IS_CONVERSION_ONGOING_INJECTED, ADC_IT_EOC, ADC_IT_EOS, ADC_IT_OVR, ADC_REGULAR_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Extended Peripheral Control functions

Functions
ADC Extended Peripheral Control functions
ADC Extended Exported Functions

ADC Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configure a channel to be assigned to ADC group injected.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeConfigChannel (ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
Enable ADC multimode and configure multimode parameters.
HAL_StatusTypeDef | HAL_ADCEx_EnableInjectedQueue (ADC_HandleTypeDef *hadc)
Enable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableInjectedQueue (ADC_HandleTypeDef *hadc)
Disable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableVoltageRegulator (ADC_HandleTypeDef *hadc)
Disable ADC voltage regulator.
HAL_StatusTypeDef | HAL_ADCEx_EnterADCDeepPowerDownMode (ADC_HandleTypeDef *hadc)
Enter ADC deep-power-down mode.

Detailed Description

ADC Extended Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels on injected group
      (+) Configure multimode when multimode feature is available
      (+) Enable or Disable Injected Queue
      (+) Disable ADC voltage regulator
      (+) Enter ADC deep-power-down mode

Function Documentation

HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue ( ADC_HandleTypeDef * hadc )

Disable Injected Queue.

Note:
This function sets CFGR register JQDIS bit in order to disable the Injected Queue. JQDIS can be written only when ADSTART and JDSTART are both equal to 0 to ensure that no regulart nor injected conversion is ongoing.
Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 2450 of file stm32h7xx_hal_adc_ex.c.

References ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED, and ADC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator ( ADC_HandleTypeDef * hadc )

Disable ADC voltage regulator.

Note:
Disabling voltage regulator allows to save power. This operation can be carried out only when ADC is disabled.
To enable again the voltage regulator, the user is expected to resort to HAL_ADC_Init() API.
Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 2474 of file stm32h7xx_hal_adc_ex.c.

References ADC_IS_ENABLE, and ADC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue ( ADC_HandleTypeDef * hadc )

Enable Injected Queue.

Note:
This function resets CFGR register JQDIS bit in order to enable the Injected Queue. JQDIS can be written only when ADSTART and JDSTART are both equal to 0 to ensure that no regulart nor injected conversion is ongoing.
Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 2423 of file stm32h7xx_hal_adc_ex.c.

References ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED, HAL_ADC_STATE_INJ_JQOVF, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode ( ADC_HandleTypeDef * hadc )

Enter ADC deep-power-down mode.

Note:
This mode is achieved in setting DEEPPWD bit and allows to save power in reducing leakage currents. It is particularly interesting before entering STOP1 or STOP2 modes.
Setting DEEPPWD automatically clears ADVREGEN bit and disables the ADC voltage regulator. This means that this API encompasses HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal calibration is lost.
To exit the ADC deep-power-down mode, the user is expected to resort to HAL_ADC_Init() API as well as to relaunch a calibration with HAL_ADCEx_Calibration_Start() API or to re-apply a previously saved calibration factor.
Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 2504 of file stm32h7xx_hal_adc_ex.c.

References ADC_IS_ENABLE, and ADC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_InjectionConfTypeDef * | sConfigInjected
 | ) |  |

Configure a channel to be assigned to ADC group injected.

Note:
Possibility to update parameters on the fly: This function initializes injected group, following calls to this function can be used to reconfigure some parameters of structure "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC. The setting of these parameters is conditioned to ADC state: Refer to comments of structure "ADC_InjectionConfTypeDef".
In case of usage of internal measurement channels: Vbat/VrefInt/TempSensor. These internal paths can be disabled using function HAL_ADC_DeInit().
Caution: For Injected Context Queue use, a context must be fully defined before start of injected conversion. All channels are configured consecutively for the same ADC instance. Therefore, the number of calls to HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter InjectedNbrOfConversion for each context.
  • Example 1: If 1 context is intended to be used (or if there is no use of the Injected Queue Context feature) and if the context contains 3 injected ranks (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be called once for each channel (i.e. 3 times) before starting a conversion. This function must not be called to configure a 4th injected channel: it would start a new context into context queue.
  • Example 2: If 2 contexts are intended to be used and each of them contains 3 injected ranks (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and for each context (3 channels x 2 contexts = 6 calls). Conversion can start once the 1st context is set, that is after the first three HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
Parameters:
hadc,: ADC handle
sConfigInjected,: Structure of ADC injected group and ADC channel for injected group.
Return values:
HAL status

Definition at line 1748 of file stm32h7xx_hal_adc_ex.c.

References ADC12_COMMON_REGISTER, ADC3_COMMON_REGISTER, ADC_ANY_OTHER_ENABLED, ADC_CFGR2_INJ_FIELDS, ADC_CFGR_INJECT_CONTEXT_QUEUE, ADC_CFGR_INJECT_DISCCONTINUOUS, ADC_CHANNEL_10, ADC_CHANNEL_9, ADC_CHANNEL_TEMPSENSOR, ADC_CHANNEL_VBAT_DIV4, ADC_CHANNEL_VREFINT, ADC_DIFFERENTIAL_ENDED, ADC_DIFSEL_CHANNEL, ADC_EXTERNALTRIGINJECCONV_EDGE_NONE, ADC_GET_RESOLUTION, ADC_INJECTED_RANK_1, ADC_INJECTED_SOFTWARE_START, ADC_IS_CONVERSION_ONGOING_INJECTED, ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED, ADC_IS_ENABLE, ADC_JSQR_FIELDS, ADC_JSQR_RK, ADC_OFFSET_1, ADC_OFFSET_2, ADC_OFFSET_3, ADC_OFFSET_4, ADC_OFFSET_SHIFT_RESOLUTION, ADC_OFR_CHANNEL, ADC_SCAN_DISABLE, ADC_SMPR1, ADC_SMPR2, ADC_TEMPSENSOR_DELAY_US, assert_param, ADC_InjectionConfTypeDef::AutoInjectedConv, ADC_InjectionConfigTypeDef::ChannelCount, ADC_InjectionConfigTypeDef::ContextQueue, ADC_InitTypeDef::DiscontinuousConvMode, ADC_InjectionConfTypeDef::ExternalTrigInjecConv, ADC_InjectionConfTypeDef::ExternalTrigInjecConvEdge, HAL_ADC_STATE_ERROR_CONFIG, ADC_HandleTypeDef::Init, ADC_InjectionConfTypeDef::InjecOversampling, ADC_InjectionConfTypeDef::InjecOversamplingMode, ADC_InjectionConfTypeDef::InjectedChannel, ADC_InjectionConfTypeDef::InjectedDiscontinuousConvMode, ADC_InjectionConfTypeDef::InjectedLeftBitShift, ADC_InjectionConfTypeDef::InjectedNbrOfConversion, ADC_InjectionConfTypeDef::InjectedOffset, ADC_InjectionConfTypeDef::InjectedOffsetNumber, ADC_InjectionConfTypeDef::InjectedOffsetSignedSaturation, ADC_InjectionConfTypeDef::InjectedRank, ADC_InjectionConfTypeDef::InjectedSamplingTime, ADC_InjectionConfTypeDef::InjectedSingleDiff, ADC_HandleTypeDef::InjectionConfig, ADC_HandleTypeDef::Instance, IS_ADC1_DIFF_CHANNEL, IS_ADC2_DIFF_CHANNEL, IS_ADC3_DIFF_CHANNEL, IS_ADC_CHANNEL, IS_ADC_EXTTRIGINJEC, IS_ADC_EXTTRIGINJEC_EDGE, IS_ADC_INJECTED_NB_CONV, IS_ADC_INJECTED_RANK, IS_ADC_OFFSET_NUMBER, IS_ADC_OVERSAMPLING_RATIO, IS_ADC_RANGE, IS_ADC_RIGHT_BIT_SHIFT, IS_ADC_SAMPLE_TIME, IS_ADC_SINGLE_DIFFERENTIAL, ADC_InitTypeDef::Oversampling, ADC_InitTypeDef::OversamplingMode, ADC_InjectionConfTypeDef::QueueInjectedContext, ADC_OversamplingTypeDef::Ratio, ADC_InjOversamplingTypeDef::Ratio, ADC_InjOversamplingTypeDef::RightBitShift, ADC_InitTypeDef::ScanConvMode, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_MultiModeTypeDef * | multimode
 | ) |  |

Enable ADC multimode and configure multimode parameters.

Note:
Possibility to update parameters on the fly: This function initializes multimode parameters, following calls to this function can be used to reconfigure some parameters of structure "ADC_MultiModeTypeDef" on the fly, without reseting the ADCs. The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_MultiModeTypeDef".
To move back configuration from multimode to single mode, ADC must be reset (using function HAL_ADC_Init() ).
Parameters:
hadc,: Master ADC handle
multimode : Structure of ADC multimode configuration
Return values:
HAL status

Definition at line 2315 of file stm32h7xx_hal_adc_ex.c.

References ADC12_COMMON_REGISTER, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_IS_ENABLE, ADC_MODE_INDEPENDENT, ADC_MULTI_SLAVE, assert_param, ADC_MultiModeTypeDef::DualModeData, HAL_ADC_STATE_ERROR_CONFIG, ADC_HandleTypeDef::Instance, IS_ADC_DUAL_DATA_MODE, IS_ADC_MODE, IS_ADC_SAMPLING_DELAY, ADC_MultiModeTypeDef::Mode, ADC_HandleTypeDef::State, and ADC_MultiModeTypeDef::TwoSamplingDelay.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC_InjectionConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InjectionConfigTypeDef Struct Reference
ADC Extended Exported Types

ADC group injected contexts queue configuration. More...

#include <stm32h7xx_hal_adc_ex.h>

Data Fields

uint32_t | ContextQueue
uint32_t | ChannelCount

Detailed Description

ADC group injected contexts queue configuration.

Definition at line 65 of file stm32h7xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_InjectionConfigTypeDef::ChannelCount

Number of channels in the injected sequence

Definition at line 71 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfigTypeDef::ContextQueue

Injected channel configuration context: build-up over each HAL_ADCEx_InjectedConfigChannel() call to finally initialize JSQR register at HAL_ADCEx_InjectedConfigChannel() last call

Definition at line 67 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_adc_ex.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_HandleTypeDef Struct Reference
ADC Extended Exported Types

ADC handle Structure definition. More...

#include <stm32h7xx_hal_adc_ex.h>

Data Fields

ADC_TypeDef * | Instance
ADC_InitTypeDef Init
DMA_HandleTypeDef * DMA_Handle
HAL_LockTypeDef | Lock
__IO uint32_t | State
__IO uint32_t | ErrorCode
ADC_InjectionConfigTypeDef InjectionConfig

Detailed Description

ADC handle Structure definition.

Definition at line 77 of file stm32h7xx_hal_adc_ex.h.

Field Documentation

DMA_HandleTypeDef* ADC_HandleTypeDef::DMA_Handle

Pointer DMA Handler

Definition at line 83 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Start_DMA(), HAL_ADC_Stop_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), and HAL_ADCEx_RegularStop_DMA().

__IO uint32_t ADC_HandleTypeDef::ErrorCode

ADC Error code

Definition at line 89 of file stm32h7xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAError(), ADC_Enable(), HAL_ADC_GetError(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_LinearCalibration_SetValue().

ADC_InitTypeDef ADC_HandleTypeDef::Init

ADC initialization parameters and regular conversions setting

Definition at line 81 of file stm32h7xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

ADC_InjectionConfigTypeDef ADC_HandleTypeDef::InjectionConfig

ADC injected channel configuration build-up structure

Definition at line 91 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADCEx_InjectedConfigChannel().

ADC_TypeDef* ADC_HandleTypeDef::Instance

Register base address

Definition at line 79 of file stm32h7xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAConvCplt(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetError(), HAL_ADC_GetState(), HAL_ADC_GetValue(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_GetValue(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_DisableInjectedQueue(), HAL_ADCEx_DisableVoltageRegulator(), HAL_ADCEx_EnableInjectedQueue(), HAL_ADCEx_EnterADCDeepPowerDownMode(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_LinearCalibration_GetValue(), HAL_ADCEx_LinearCalibration_SetValue(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeGetValue(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

HAL_LockTypeDef ADC_HandleTypeDef::Lock

ADC locking object

Definition at line 85 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

__IO uint32_t ADC_HandleTypeDef::State

ADC communication state (bit-map of ADC states)

Definition at line 87 of file stm32h7xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAConvCplt(), ADC_DMAError(), ADC_Enable(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetState(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_EnableInjectedQueue(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_LinearCalibration_SetValue(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_adc_ex.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC_InjOversamplingTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InjOversamplingTypeDef Struct Reference
ADC Extended Exported Types

ADC Injected Conversion Oversampling structure definition. More...

#include <stm32h7xx_hal_adc_ex.h>

Data Fields

uint32_t | Ratio
uint32_t | RightBitShift

Detailed Description

ADC Injected Conversion Oversampling structure definition.

Definition at line 97 of file stm32h7xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_InjOversamplingTypeDef::Ratio

Configures the oversampling ratio. This parameter can be a value between 0 to 1023

Definition at line 99 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjOversamplingTypeDef::RightBitShift

Configures the division coefficient for the Oversampler. This parameter can be a value of ADC Extended Oversampling Right Shift

Definition at line 102 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_adc_ex.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC_ChannelConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_ChannelConfTypeDef Struct Reference
ADC Extended Exported Types

Structure definition of ADC channel for regular group. More...

#include <stm32h7xx_hal_adc_ex.h>

Data Fields

uint32_t | Channel
uint32_t | Rank
uint32_t | SamplingTime
uint32_t | SingleDiff
uint32_t | OffsetNumber
uint32_t | Offset
FunctionalState | OffsetRightShift
FunctionalState | OffsetSignedSaturation

Detailed Description

Structure definition of ADC channel for regular group.

Note:
The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
  • For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
  • For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).

Definition at line 117 of file stm32h7xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_ChannelConfTypeDef::Channel

Specify the channel to configure into ADC regular group. This parameter can be a value of ADC Channels Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device DataSheet for channels availability.

Definition at line 119 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::Offset

Define the offset to be subtracted from the raw converted data. Offset value must be a positive number. Depending of ADC resolution selected (16, 14, 12, 10 or 8 bits), this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 154 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::OffsetNumber

Select the offset number This parameter can be a value of ADC Extended Offset Number Caution: Only one offset is allowed per channel. This parameter overwrites the last setting.

Definition at line 150 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

FunctionalState ADC_ChannelConfTypeDef::OffsetRightShift

Define the Right-shift data after Offset correction. This parameter is applied only for 16-bit or 8-bit resolution. This parameter can be set to ENABLE or DISABLE.

Definition at line 161 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

FunctionalState ADC_ChannelConfTypeDef::OffsetSignedSaturation

Specify whether the Signed saturation feature is used or not. This parameter is applied only for 16-bit or 8-bit resolution. This parameter can be set to ENABLE or DISABLE.

Definition at line 165 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::Rank

Specify the rank in the regular group sequencer. This parameter can be a value of ADC group regular sequencer rank Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted)

Definition at line 123 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::SamplingTime

Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time This parameter can be a value of ADC Sampling Times Caution: This parameter applies to a channel that can be used into regular and/or injected group. It overwrites the last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device DataSheet for timings values.

Definition at line 128 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::SingleDiff

Select single-ended or differential input. In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically. This parameter must be a value of ADC Extended Single-ended/Differential input mode Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case of another parameter update on the fly)

Definition at line 138 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_adc_ex.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC_InjectionConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InjectionConfTypeDef Struct Reference
ADC Extended Exported Types

Structure definition of ADC group injected and ADC channel affected to ADC group injected. More...

#include <stm32h7xx_hal_adc_ex.h>

Data Fields

uint32_t | InjectedChannel
uint32_t | InjectedRank
uint32_t | InjectedSamplingTime
uint32_t | InjectedSingleDiff
uint32_t | InjectedOffsetNumber
uint32_t | InjectedOffset
uint32_t | InjectedOffsetRightShift
FunctionalState | InjectedOffsetSignedSaturation
uint32_t | InjectedLeftBitShift
uint32_t | InjectedNbrOfConversion
FunctionalState | InjectedDiscontinuousConvMode
FunctionalState | AutoInjectedConv
FunctionalState | QueueInjectedContext
uint32_t | ExternalTrigInjecConv
uint32_t | ExternalTrigInjecConvEdge
FunctionalState | InjecOversamplingMode
ADC_InjOversamplingTypeDef InjecOversampling

Detailed Description

Structure definition of ADC group injected and ADC channel affected to ADC group injected.

Note:
Parameters of this structure are shared within 2 scopes:
  • Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
  • Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
  • For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
  • For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
  • For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going on ADC groups regular and injected. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).

Definition at line 186 of file stm32h7xx_hal_adc_ex.h.

Field Documentation

FunctionalState ADC_InjectionConfTypeDef::AutoInjectedConv

Enables or disables the selected ADC group injected automatic conversion after regular one This parameter can be set to ENABLE or DISABLE. Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. To maintain JAUTO always enabled, DMA must be configured in circular mode. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 253 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::ExternalTrigInjecConv

Selects the external event used to trigger the conversion start of injected group. If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. This parameter can be a value of ADC Extended External Trigger Source for Injected Group. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 273 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::ExternalTrigInjecConvEdge

Selects the external trigger edge of injected group. This parameter can be a value of ADC group injected trigger edge (when external trigger is selected). If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 279 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

ADC_InjOversamplingTypeDef ADC_InjectionConfTypeDef::InjecOversampling

Specifies the Oversampling parameters. Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared).

Definition at line 289 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

FunctionalState ADC_InjectionConfTypeDef::InjecOversamplingMode

Specifies whether the oversampling feature is enabled or disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared)

Definition at line 285 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedChannel

Specifies the channel to configure into ADC group injected. This parameter can be a value of ADC Channels Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability.

Definition at line 188 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

FunctionalState ADC_InjectionConfTypeDef::InjectedDiscontinuousConvMode

Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 243 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedLeftBitShift

Configures the left shifting applied to the final result with or without oversampling. This parameter can be a value of ADC Extended Oversampling left Shift

Definition at line 235 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedNbrOfConversion

Specifies the number of ranks that will be converted within the ADC group injected sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 237 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedOffset

Defines the offset to be subtracted from the raw converted data. Offset value must be a positive number. Depending of ADC resolution selected (16, 14, 12, 10 or 8bits), this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 223 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedOffsetNumber

Selects the offset number. This parameter can be a value of ADC Extended Offset Number. Caution: Only one offset is allowed per channel. This parameter overwrites the last setting.

Definition at line 219 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedOffsetRightShift

Defines the Right-shift data after Offset correction. This parameter is applied only for 16-bit or 8-bit resolution. This parameter must be a value of ADC Extended Oversampling Right Shift.

Definition at line 229 of file stm32h7xx_hal_adc_ex.h.

FunctionalState ADC_InjectionConfTypeDef::InjectedOffsetSignedSaturation

Specifies whether the Signed saturation feature is used or not. This parameter is applied only for 16-bit or 8-bit resolution. This parameter can be set to ENABLE or DISABLE.

Definition at line 232 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedRank

Specifies the rank in the ADC group injected sequencer. This parameter must be a value of ADC Extended Injected Channel Rank. Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted)

Definition at line 192 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedSamplingTime

Sampling time value to be set for the selected channel. Unit: ADC clock cycles. Conversion time is the addition of sampling time and processing time This parameter can be a value of ADC Sampling Times. Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values.

Definition at line 197 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedSingleDiff

Selection of single-ended or differential input. In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically. This parameter must be a value of ADC Extended Single-ended/Differential input mode. Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case of another parameter update on the fly)

Definition at line 207 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

FunctionalState ADC_InjectionConfTypeDef::QueueInjectedContext

Specifies whether the context queue feature is enabled. This parameter can be set to ENABLE or DISABLE. If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a new injected context is set when queue is full, error is triggered by interruption and through function 'HAL_ADCEx_InjectedQueueOverflowCallback'. Caution: This feature request that the sequence is fully configured before injected conversion start. Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).

Definition at line 262 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_adc_ex.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC_MultiModeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_MultiModeTypeDef Struct Reference
ADC Extended Exported Types

Structure definition of ADC MultiMode. More...

#include <stm32h7xx_hal_adc_ex.h>

Data Fields

uint32_t | Mode
uint32_t | DualModeData
uint32_t | TwoSamplingDelay

Detailed Description

Structure definition of ADC MultiMode.

Note:
The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). Both Master and Slave ADCs must be disabled.

Definition at line 301 of file stm32h7xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_MultiModeTypeDef::DualModeData

Configures the Dual ADC Mode Data Format: This parameter can be a value of ADC Extended Dual Mode Data Formatting

Definition at line 305 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

uint32_t ADC_MultiModeTypeDef::Mode

Configures the ADC to operate in independent or MultiMode. This parameter can be a value of ADC Extended multimode dual mode

Definition at line 303 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

uint32_t ADC_MultiModeTypeDef::TwoSamplingDelay

Configures the Delay between 2 sampling phases. This parameter can be a value of ADC Extended delay between 2 sampling phases Delay range depends on selected resolution: from 1 to 9 clock cycles for 16 bits, from 1 to 9 clock cycles for 14 bits from 1 to 8 clock cycles for 12 bits from 1 to 6 clock cycles for 10 bits from 1 to 6 clock cycles for 8 bits

Definition at line 307 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_adc_ex.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Extended External Trigger Source for Injected Group

Defines
ADC Extended External Trigger Source for Injected Group
ADC Extended Exported Constants

Defines

#define | ADC_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
#define | ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
#define | ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
#define | ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
#define | ADC_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
#define | ADC_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2 ((uint32_t)ADC_JSQR_JEXTSEL_4)
#define | ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4 ((uint32_t)(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_LPTIM1_OUT ((uint32_t)(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJEC_LPTIM2_OUT ((uint32_t)(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_LPTIM3_OUT ((uint32_t)(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2))
#define | ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)

Define Documentation

#define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))

Event 6 triggers injected group conversion start

Definition at line 336 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2 ((uint32_t)ADC_JSQR_JEXTSEL_4)

Event 16 triggers injected group conversion start

Definition at line 346 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4 ((uint32_t)(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0))

Event 17 triggers injected group conversion start

Definition at line 347 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_LPTIM1_OUT ((uint32_t)(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1))

Event 18 triggers injected group conversion start

Definition at line 348 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_LPTIM2_OUT ((uint32_t)(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))

Event 19 triggers injected group conversion start

Definition at line 349 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_LPTIM3_OUT ((uint32_t)(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2))

Event 20 triggers injected group conversion start

Definition at line 350 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))

Event 15 triggers injected group conversion start

Definition at line 345 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)

Event 1 triggers injected group conversion start

Definition at line 331 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)

Event 0 triggers injected group conversion start

Definition at line 330 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)

Event 8 triggers injected group conversion start

Definition at line 338 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))

Event 3 triggers injected group conversion start

Definition at line 333 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)

Event 2 triggers injected group conversion start

Definition at line 332 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))

Event 13 triggers injected group conversion start

Definition at line 343 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))

Event 11 triggers injected group conversion start

Definition at line 341 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)

Event 4 triggers injected group conversion start

Definition at line 334 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))

Event 12 triggers injected group conversion start

Definition at line 342 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))

Event 5 triggers injected group conversion start

Definition at line 335 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))

Event 14 triggers injected group conversion start

Definition at line 344 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))

Event 7 triggers injected group conversion start

Definition at line 337 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))

Event 9 triggers injected group conversion start

Definition at line 339 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))

Event 10 triggers injected group conversion start

Definition at line 340 of file stm32h7xx_hal_adc_ex.h.

#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)

Software triggers injected group conversion start

Definition at line 352 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC group injected trigger edge (when external trigger is selected)

Defines
ADC group injected trigger edge (when external trigger is selected)
ADC Extended Exported Constants

Defines

#define | ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN)

Define Documentation

#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1)

Injected conversions hardware trigger detection on the falling edge

Definition at line 362 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000)

Injected conversions hardware trigger detection disabled

Definition at line 360 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0)

Injected conversions hardware trigger detection on the rising edge

Definition at line 361 of file stm32h7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN)

Injected conversions hardware trigger detection on both the rising and falling edges

Definition at line 363 of file stm32h7xx_hal_adc_ex.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Extended Single-ended/Differential input mode

Defines
ADC Extended Single-ended/Differential input mode
ADC Extended Exported Constants

Defines

#define | ADC_SINGLE_ENDED ((uint32_t)0x00000000)
#define | ADC_DIFFERENTIAL_ENDED ((uint32_t)ADC_CR_ADCALDIF)

Define Documentation

#define ADC_DIFFERENTIAL_ENDED ((uint32_t)ADC_CR_ADCALDIF)

ADC channel set in differential mode

Definition at line 372 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), HAL_ADCEx_Calibration_GetValue(), HAL_ADCEx_Calibration_SetValue(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SINGLE_ENDED ((uint32_t)0x00000000)

ADC channel set in single-ended input mode

Definition at line 371 of file stm32h7xx_hal_adc_ex.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Extended Offset Number

Defines
ADC Extended Offset Number
ADC Extended Exported Constants

Defines

#define | ADC_OFFSET_NONE ((uint32_t)0x00)
#define | ADC_OFFSET_1 ((uint32_t)0x01)
#define | ADC_OFFSET_2 ((uint32_t)0x02)
#define | ADC_OFFSET_3 ((uint32_t)0x03)
#define | ADC_OFFSET_4 ((uint32_t)0x04)

Define Documentation

#define ADC_OFFSET_1 ((uint32_t)0x01)

Offset correction to apply to a first channel

Definition at line 381 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_OFFSET_2 ((uint32_t)0x02)

Offset correction to apply to a second channel

Definition at line 382 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_OFFSET_3 ((uint32_t)0x03)

Offset correction to apply to a third channel

Definition at line 383 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_OFFSET_4 ((uint32_t)0x04)

Offset correction to apply to a fourth channel

Definition at line 384 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_OFFSET_NONE ((uint32_t)0x00)

No offset correction

Definition at line 380 of file stm32h7xx_hal_adc_ex.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Extended Injected Channel Rank

Defines
ADC Extended Injected Channel Rank
ADC Extended Exported Constants

Defines

#define | ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
#define | ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
#define | ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
#define | ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)

Define Documentation

#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)

ADC injected conversion rank 1

Definition at line 392 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel(), and HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)

ADC injected conversion rank 2

Definition at line 393 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)

ADC injected conversion rank 3

Definition at line 394 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)

ADC injected conversion rank 4

Definition at line 395 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Extended multimode dual mode

Defines
ADC Extended multimode dual mode
ADC Extended Exported Constants

Defines

#define | ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000))
#define | ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_0))
#define | ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_1))
#define | ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0))
#define | ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0))
#define | ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1))
#define | ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0))
#define | ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0))

Define Documentation

#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0))

Alternate trigger mode only

Definition at line 410 of file stm32h7xx_hal_adc_ex.h.

#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0))

Injected simultaneous mode only

Definition at line 407 of file stm32h7xx_hal_adc_ex.h.

#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0))

Interleaved mode only

Definition at line 409 of file stm32h7xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0))

Combined Interleaved mode + injected simultaneous mode

Definition at line 406 of file stm32h7xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1))

Regular simultaneous mode only

Definition at line 408 of file stm32h7xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_1))

Combined regular simultaneous + alternate trigger mode

Definition at line 405 of file stm32h7xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_0))

Combined regular simultaneous + injected simultaneous mode

Definition at line 404 of file stm32h7xx_hal_adc_ex.h.

#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000))

Independent ADC conversions mode

Definition at line 403 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADCEx_MultiModeConfigChannel().

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Extended Dual Mode Data Formatting

Defines
ADC Extended Dual Mode Data Formatting
ADC Extended Exported Constants

Defines

#define | ADC_DUALMODEDATAFORMAT_DISABLED ((uint32_t)0x00000000)
#define | ADC_DUALMODEDATAFORMAT_32_10_BITS ((uint32_t)ADC_CCR_DAMDF_1)
#define | ADC_DUALMODEDATAFORMAT_8_BITS ((uint32_t)(ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1))

Define Documentation

#define ADC_DUALMODEDATAFORMAT_32_10_BITS ((uint32_t)ADC_CCR_DAMDF_1)

Data formatting mode for 32 down to 10-bit resolution

Definition at line 420 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForConversion().

#define ADC_DUALMODEDATAFORMAT_8_BITS ((uint32_t)(ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1))

Data formatting mode for 8-bit resolution

Definition at line 421 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForConversion().

#define ADC_DUALMODEDATAFORMAT_DISABLED ((uint32_t)0x00000000)

Dual ADC mode without data packing: ADCx_CDR and ADCx_CDR2 registers not used

Definition at line 419 of file stm32h7xx_hal_adc_ex.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Extended delay between 2 sampling phases

Defines
ADC Extended delay between 2 sampling phases
ADC Extended Exported Constants

Defines

#define | ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000))
#define | ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)(ADC_CCR_DELAY_2))
#define | ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)(ADC_CCR_DELAY_3))

Define Documentation

#define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000))

1 ADC clock cycle delay

Definition at line 429 of file stm32h7xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC_CCR_DELAY_0))

2 ADC clock cycles delay

Definition at line 430 of file stm32h7xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC_CCR_DELAY_1))

3 ADC clock cycles delay

Definition at line 431 of file stm32h7xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))

4 ADC clock cycles delay (lower for less then 10-bit resolution)

Definition at line 432 of file stm32h7xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)(ADC_CCR_DELAY_2))

5 ADC clock cycles delay (lower for less then 12-bit resolution)

Definition at line 433 of file stm32h7xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))

6 ADC clock cycles delay (lower for less then 14-bit resolution)

Definition at line 434 of file stm32h7xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))

7 ADC clock cycles delay (lower for less then 16-bit resolution)

Definition at line 435 of file stm32h7xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))

8 ADC clock cycles delay (lower for less then 16-bit resolution)

Definition at line 436 of file stm32h7xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)(ADC_CCR_DELAY_3))

9 ADC clock cycles delay (lower for less then 16-bit resolution)

Definition at line 437 of file stm32h7xx_hal_adc_ex.h.

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STM32H753xx HAL User Manual: ADC Extended Analog Watchdog Selection

Defines
ADC Extended Analog Watchdog Selection
ADC Extended Exported Constants

Defines

#define | ADC_ANALOGWATCHDOG_1 ((uint32_t)0x00000001)
#define | ADC_ANALOGWATCHDOG_2 ((uint32_t)0x00000002)
#define | ADC_ANALOGWATCHDOG_3 ((uint32_t)0x00000003)

Define Documentation

#define ADC_ANALOGWATCHDOG_1 ((uint32_t)0x00000001)

Analog watchdog 1 selection

Definition at line 445 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_2 ((uint32_t)0x00000002)

Analog watchdog 2 selection

Definition at line 446 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_3 ((uint32_t)0x00000003)

Analog watchdog 3 selection

Definition at line 447 of file stm32h7xx_hal_adc_ex.h.

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STM32H753xx HAL User Manual: ADC Extended Analog Watchdog Mode

Defines
ADC Extended Analog Watchdog Mode
ADC Extended Exported Constants

Defines

#define | ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000)
#define | ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN))
#define | ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN))
#define | ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))
#define | ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR_AWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CFGR_JAWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))

Define Documentation

#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CFGR_JAWD1EN)

Analog watchdog applied to injected group all channels

Definition at line 460 of file stm32h7xx_hal_adc_ex.h.

#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR_AWD1EN)

Analog watchdog applied to regular group all channels

Definition at line 459 of file stm32h7xx_hal_adc_ex.h.

#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))

Analog watchdog applied to regular and injected groups all channels

Definition at line 461 of file stm32h7xx_hal_adc_ex.h.

#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000)

No analog watchdog selected

Definition at line 455 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN))

Analog watchdog applied to an injected group single channel

Definition at line 457 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN))

Analog watchdog applied to a regular group single channel

Definition at line 456 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))

Analog watchdog applied to a regular and injected groups single channel

Definition at line 458 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

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STM32H753xx HAL User Manual: ADC Extended Conversion Group

Defines
ADC Extended Conversion Group
ADC Extended Exported Constants

Defines

#define | ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))
#define | ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS))
#define | ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS))

Define Documentation

#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS))

ADC injected group selection

Definition at line 470 of file stm32h7xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADCEx_InjectedStop(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))

ADC regular group selection

Definition at line 469 of file stm32h7xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS))

ADC regular and injected groups selection

Definition at line 471 of file stm32h7xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADC_DeInit(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), and HAL_ADCEx_MultiModeStop_DMA().

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STM32H753xx HAL User Manual: ADC Extended Event Type

Defines
ADC Extended Event Type
ADC Extended Exported Constants

Defines

#define | ADC_EOSMP_EVENT ((uint32_t)ADC_FLAG_EOSMP)
#define | ADC_AWD1_EVENT ((uint32_t)ADC_FLAG_AWD1)
#define | ADC_AWD2_EVENT ((uint32_t)ADC_FLAG_AWD2)
#define | ADC_AWD3_EVENT ((uint32_t)ADC_FLAG_AWD3)
#define | ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
#define | ADC_JQOVF_EVENT ((uint32_t)ADC_FLAG_JQOVF)

Define Documentation

#define ADC_AWD1_EVENT ((uint32_t)ADC_FLAG_AWD1)

ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series)

Definition at line 480 of file stm32h7xx_hal_adc_ex.h.

#define ADC_AWD2_EVENT ((uint32_t)ADC_FLAG_AWD2)

ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series)

Definition at line 481 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_AWD3_EVENT ((uint32_t)ADC_FLAG_AWD3)

ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series)

Definition at line 482 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_EOSMP_EVENT ((uint32_t)ADC_FLAG_EOSMP)

ADC End of Sampling event

Definition at line 479 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_JQOVF_EVENT ((uint32_t)ADC_FLAG_JQOVF)

ADC Injected Context Queue Overflow event

Definition at line 484 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)

ADC overrun event

Definition at line 483 of file stm32h7xx_hal_adc_ex.h.

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STM32H753xx HAL User Manual: ADC Extended Interrupts Definition

Defines
ADC Extended Interrupts Definition
ADC Extended Exported Constants

Defines

#define | ADC_IT_RDY ADC_IER_RDY
#define | ADC_IT_EOSMP ADC_IER_EOSMP
#define | ADC_IT_EOC ADC_IER_EOC
#define | ADC_IT_EOS ADC_IER_EOS
#define | ADC_IT_OVR ADC_IER_OVR
#define | ADC_IT_JEOC ADC_IER_JEOC
#define | ADC_IT_JEOS ADC_IER_JEOS
#define | ADC_IT_AWD1 ADC_IER_AWD1
#define | ADC_IT_AWD2 ADC_IER_AWD2
#define | ADC_IT_AWD3 ADC_IER_AWD3
#define | ADC_IT_JQOVF ADC_IER_JQOVF
#define | ADC_IT_AWD ADC_IT_AWD1

Define Documentation

#define ADC_IT_AWD ADC_IT_AWD1

ADC Analog watchdog 1 interrupt source: Naming for compatibility with other STM32 devices having only one analog watchdog

Definition at line 505 of file stm32h7xx_hal_adc_ex.h.

#define ADC_IT_AWD1 ADC_IER_AWD1

ADC Analog watchdog 1 interrupt source (main analog watchdog)

Definition at line 500 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_AWD2 ADC_IER_AWD2

ADC Analog watchdog 2 interrupt source (additional analog watchdog)

Definition at line 501 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_AWD3 ADC_IER_AWD3

ADC Analog watchdog 3 interrupt source (additional analog watchdog)

Definition at line 502 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_EOC ADC_IER_EOC

ADC End of Regular Conversion interrupt source

Definition at line 495 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADC_Stop_IT(), and HAL_ADCEx_RegularStop_IT().

#define ADC_IT_EOS ADC_IER_EOS

ADC End of Regular sequence of Conversions interrupt source

Definition at line 496 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADC_Stop_IT(), and HAL_ADCEx_RegularStop_IT().

#define ADC_IT_EOSMP ADC_IER_EOSMP

ADC End of Sampling interrupt source

Definition at line 494 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_JEOC ADC_IER_JEOC

ADC End of Injected Conversion interrupt source

Definition at line 498 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_IT_JEOS ADC_IER_JEOS

ADC End of Injected sequence of Conversions interrupt source

Definition at line 499 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_IT_JQOVF ADC_IER_JQOVF

ADC Injected Context Queue Overflow interrupt source

Definition at line 503 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_OVR ADC_IER_OVR

ADC overrun interrupt source

Definition at line 497 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define ADC_IT_RDY ADC_IER_RDY

ADC Ready (ADRDY) interrupt source

Definition at line 493 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit().

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STM32H753xx HAL User Manual: ADC Extended Flags Definition

Defines
ADC Extended Flags Definition
ADC Extended Exported Constants

Defines

#define | ADC_FLAG_RDY ADC_ISR_ADRD
#define | ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | ADC_FLAG_EOC ADC_ISR_EOC
#define | ADC_FLAG_EOS ADC_ISR_EOS
#define | ADC_FLAG_OVR ADC_ISR_OVR
#define | ADC_FLAG_JEOC ADC_ISR_JEOC
#define | ADC_FLAG_JEOS ADC_ISR_JEOS
#define | ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | ADC_FLAG_AWD3 ADC_ISR_AWD3
#define | ADC_FLAG_JQOVF ADC_ISR_JQOVF
#define | ADC_FLAG_AWD ADC_FLAG_AWD1
#define | ADC_FLAG_ALL
#define | ADC_FLAG_POSTCONV_ALL

Define Documentation

#define ADC_FLAG_ALL
Value:
(ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS |  \
                         ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \
                         ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF)

ADC all flags

Definition at line 527 of file stm32h7xx_hal_adc_ex.h.

#define ADC_FLAG_AWD ADC_FLAG_AWD1

ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog

Definition at line 525 of file stm32h7xx_hal_adc_ex.h.

#define ADC_FLAG_AWD1 ADC_ISR_AWD1

ADC Analog watchdog 1 flag (main analog watchdog)

Definition at line 520 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_AWD2 ADC_ISR_AWD2

ADC Analog watchdog 2 flag (additional analog watchdog)

Definition at line 521 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_AWD3 ADC_ISR_AWD3

ADC Analog watchdog 3 flag (additional analog watchdog)

Definition at line 522 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_EOC ADC_ISR_EOC

ADC End of Regular Conversion flag

Definition at line 515 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_FLAG_EOS ADC_ISR_EOS

ADC End of Regular sequence of Conversions flag

Definition at line 516 of file stm32h7xx_hal_adc_ex.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_FLAG_EOSMP ADC_ISR_EOSMP

ADC End of Sampling flag

Definition at line 514 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_JEOC ADC_ISR_JEOC

ADC End of Injected Conversion flag

Definition at line 518 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_FLAG_JEOS ADC_ISR_JEOS

ADC End of Injected sequence of Conversions flag

Definition at line 519 of file stm32h7xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_FLAG_JQOVF ADC_ISR_JQOVF

ADC Injected Context Queue Overflow flag

Definition at line 523 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_FLAG_OVR ADC_ISR_OVR

ADC overrun flag

Definition at line 517 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_FLAG_POSTCONV_ALL
Value:
(ADC_FLAG_EOC | ADC_FLAG_EOS  | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \
                               ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \
                               ADC_FLAG_JQOVF)

ADC post-conversion all flags

Definition at line 532 of file stm32h7xx_hal_adc_ex.h.

#define ADC_FLAG_RDY ADC_ISR_ADRD

ADC Ready (ADRDY) flag

Definition at line 513 of file stm32h7xx_hal_adc_ex.h.

Referenced by ADC_Enable(), and HAL_ADC_DeInit().

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STM32H753xx HAL User Manual: ADC Extended Oversampling Right Shift

Defines
ADC Extended Oversampling Right Shift
ADC Extended Exported Constants

Defines

#define | ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000)
#define | ADC_RIGHTBITSHIFT_1 ((uint32_t)ADC_CFGR2_OVSS_0)
#define | ADC_RIGHTBITSHIFT_2 ((uint32_t)ADC_CFGR2_OVSS_1)
#define | ADC_RIGHTBITSHIFT_3 ((uint32_t)(ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0))
#define | ADC_RIGHTBITSHIFT_4 ((uint32_t)ADC_CFGR2_OVSS_2)
#define | ADC_RIGHTBITSHIFT_5 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0))
#define | ADC_RIGHTBITSHIFT_6 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1))
#define | ADC_RIGHTBITSHIFT_7 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0))
#define | ADC_RIGHTBITSHIFT_8 ((uint32_t)ADC_CFGR2_OVSS_3)
#define | ADC_RIGHTBITSHIFT_9 ((uint32_t)(ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0))
#define | ADC_RIGHTBITSHIFT_10 ((uint32_t)(ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1))
#define | ADC_RIGHTBITSHIFT_11 ((uint32_t)(ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0))

Define Documentation

#define ADC_RIGHTBITSHIFT_1 ((uint32_t)ADC_CFGR2_OVSS_0)

ADC 1 bit shift for oversampling

Definition at line 544 of file stm32h7xx_hal_adc_ex.h.

#define ADC_RIGHTBITSHIFT_10 ((uint32_t)(ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1))

ADC 10 bits shift for oversampling

Definition at line 553 of file stm32h7xx_hal_adc_ex.h.

#define ADC_RIGHTBITSHIFT_11 ((uint32_t)(ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0))

ADC 11 bits shift for oversampling

Definition at line 554 of file stm32h7xx_hal_adc_ex.h.

#define ADC_RIGHTBITSHIFT_2 ((uint32_t)ADC_CFGR2_OVSS_1)

ADC 2 bits shift for oversampling

Definition at line 545 of file stm32h7xx_hal_adc_ex.h.

#define ADC_RIGHTBITSHIFT_3 ((uint32_t)(ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0))

ADC 3 bits shift for oversampling

Definition at line 546 of file stm32h7xx_hal_adc_ex.h.

#define ADC_RIGHTBITSHIFT_4 ((uint32_t)ADC_CFGR2_OVSS_2)

ADC 4 bits shift for oversampling

Definition at line 547 of file stm32h7xx_hal_adc_ex.h.

#define ADC_RIGHTBITSHIFT_5 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0))

ADC 5 bits shift for oversampling

Definition at line 548 of file stm32h7xx_hal_adc_ex.h.

#define ADC_RIGHTBITSHIFT_6 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1))

ADC 6 bits shift for oversampling

Definition at line 549 of file stm32h7xx_hal_adc_ex.h.

#define ADC_RIGHTBITSHIFT_7 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0))

ADC 7 bits shift for oversampling

Definition at line 550 of file stm32h7xx_hal_adc_ex.h.

#define ADC_RIGHTBITSHIFT_8 ((uint32_t)ADC_CFGR2_OVSS_3)

ADC 8 bits shift for oversampling

Definition at line 551 of file stm32h7xx_hal_adc_ex.h.

#define ADC_RIGHTBITSHIFT_9 ((uint32_t)(ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0))

ADC 9 bits shift for oversampling

Definition at line 552 of file stm32h7xx_hal_adc_ex.h.

#define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000)

ADC No bit shift for oversampling

Definition at line 543 of file stm32h7xx_hal_adc_ex.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Extended Oversampling left Shift

Defines
ADC Extended Oversampling left Shift
ADC Extended Exported Constants

Defines

#define | ADC_LEFTBITSHIFT_NONE ((uint32_t)0x00000000)
#define | ADC_LEFTBITSHIFT_1 ((uint32_t)ADC_CFGR2_LSHIFT_0)
#define | ADC_LEFTBITSHIFT_2 ((uint32_t)ADC_CFGR2_LSHIFT_1)
#define | ADC_LEFTBITSHIFT_3 ((uint32_t)(ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0))
#define | ADC_LEFTBITSHIFT_4 ((uint32_t)ADC_CFGR2_LSHIFT_2)
#define | ADC_LEFTBITSHIFT_5 ((uint32_t)(ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0))
#define | ADC_LEFTBITSHIFT_6 ((uint32_t)(ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1))
#define | ADC_LEFTBITSHIFT_7 ((uint32_t)(ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0))
#define | ADC_LEFTBITSHIFT_8 ((uint32_t)ADC_CFGR2_LSHIFT_3)
#define | ADC_LEFTBITSHIFT_9 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0))
#define | ADC_LEFTBITSHIFT_10 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1))
#define | ADC_LEFTBITSHIFT_11 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0))
#define | ADC_LEFTBITSHIFT_12 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2))
#define | ADC_LEFTBITSHIFT_13 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0))
#define | ADC_LEFTBITSHIFT_14 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1))
#define | ADC_LEFTBITSHIFT_15 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0))

Define Documentation

#define ADC_LEFTBITSHIFT_1 ((uint32_t)ADC_CFGR2_LSHIFT_0)

ADC 1 bit shift

Definition at line 563 of file stm32h7xx_hal_adc_ex.h.

#define ADC_LEFTBITSHIFT_10 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1))

ADC 10 bits shift

Definition at line 572 of file stm32h7xx_hal_adc_ex.h.

#define ADC_LEFTBITSHIFT_11 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0))

ADC 11 bits shift

Definition at line 573 of file stm32h7xx_hal_adc_ex.h.

#define ADC_LEFTBITSHIFT_12 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2))

ADC 12 bits shift

Definition at line 574 of file stm32h7xx_hal_adc_ex.h.

#define ADC_LEFTBITSHIFT_13 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0))

ADC 13 bits shift

Definition at line 575 of file stm32h7xx_hal_adc_ex.h.

#define ADC_LEFTBITSHIFT_14 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1))

ADC 14 bits shift

Definition at line 576 of file stm32h7xx_hal_adc_ex.h.

#define ADC_LEFTBITSHIFT_15 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0))

ADC 15 bits shift

Definition at line 577 of file stm32h7xx_hal_adc_ex.h.

#define ADC_LEFTBITSHIFT_2 ((uint32_t)ADC_CFGR2_LSHIFT_1)

ADC 2 bits shift

Definition at line 564 of file stm32h7xx_hal_adc_ex.h.

#define ADC_LEFTBITSHIFT_3 ((uint32_t)(ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0))

ADC 3 bits shift

Definition at line 565 of file stm32h7xx_hal_adc_ex.h.

#define ADC_LEFTBITSHIFT_4 ((uint32_t)ADC_CFGR2_LSHIFT_2)

ADC 4 bits shift

Definition at line 566 of file stm32h7xx_hal_adc_ex.h.

#define ADC_LEFTBITSHIFT_5 ((uint32_t)(ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0))

ADC 5 bits shift

Definition at line 567 of file stm32h7xx_hal_adc_ex.h.

#define ADC_LEFTBITSHIFT_6 ((uint32_t)(ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1))

ADC 6 bits shift

Definition at line 568 of file stm32h7xx_hal_adc_ex.h.

#define ADC_LEFTBITSHIFT_7 ((uint32_t)(ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0))

ADC 7 bits shift

Definition at line 569 of file stm32h7xx_hal_adc_ex.h.

#define ADC_LEFTBITSHIFT_8 ((uint32_t)ADC_CFGR2_LSHIFT_3)

ADC 8 bits shift

Definition at line 570 of file stm32h7xx_hal_adc_ex.h.

#define ADC_LEFTBITSHIFT_9 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0))

ADC 9 bits shift

Definition at line 571 of file stm32h7xx_hal_adc_ex.h.

#define ADC_LEFTBITSHIFT_NONE ((uint32_t)0x00000000)

ADC No bit shift

Definition at line 562 of file stm32h7xx_hal_adc_ex.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Extended Triggered Regular Oversampling

Defines
ADC Extended Triggered Regular Oversampling
ADC Extended Exported Constants

Defines

#define | ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000)
#define | ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)ADC_CFGR2_TROVS)

Define Documentation

#define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)ADC_CFGR2_TROVS)

A trigger for each oversampled conversion

Definition at line 586 of file stm32h7xx_hal_adc_ex.h.

#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000)

A single trigger for all channel oversampled conversions

Definition at line 585 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Extended Regular Oversampling Continued or Resumed Mode

Defines
ADC Extended Regular Oversampling Continued or Resumed Mode
ADC Extended Exported Constants

Defines

#define | ADC_REGOVERSAMPLING_CONTINUED_MODE ((uint32_t)0x00000000)
#define | ADC_REGOVERSAMPLING_RESUMED_MODE ((uint32_t)ADC_CFGR2_ROVSM)

Define Documentation

#define ADC_REGOVERSAMPLING_CONTINUED_MODE ((uint32_t)0x00000000)

Oversampling buffer maintained during injection sequence

Definition at line 594 of file stm32h7xx_hal_adc_ex.h.

#define ADC_REGOVERSAMPLING_RESUMED_MODE ((uint32_t)ADC_CFGR2_ROVSM)

Oversampling buffer zeroed during injection sequence

Definition at line 595 of file stm32h7xx_hal_adc_ex.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Sampling Times

Defines
ADC Sampling Times
ADC Extended Exported Constants

Defines

#define | ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000)
#define | ADC_SAMPLETIME_2CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_0)
#define | ADC_SAMPLETIME_8CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_1)
#define | ADC_SAMPLETIME_16CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0))
#define | ADC_SAMPLETIME_32CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_2)
#define | ADC_SAMPLETIME_64CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0))
#define | ADC_SAMPLETIME_387CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1))
#define | ADC_SAMPLETIME_810CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10)

Define Documentation

#define ADC_SAMPLETIME_16CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0))

Sampling time 16.5 ADC clock cycles

Definition at line 606 of file stm32h7xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000)

Sampling time 1.5 ADC clock cycle

Definition at line 603 of file stm32h7xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_2CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_0)

Sampling time 2.5 ADC clock cycles

Definition at line 604 of file stm32h7xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_32CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_2)

Sampling time 32.5 ADC clock cycles

Definition at line 607 of file stm32h7xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_387CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1))

Sampling time 387.5 ADC clock cycles

Definition at line 609 of file stm32h7xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_64CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0))

Sampling time 64.5 ADC clock cycles

Definition at line 608 of file stm32h7xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_810CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10)

Sampling time 810.5 ADC clock cycles

Definition at line 610 of file stm32h7xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_8CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_1)

Sampling time 8.5 ADC clock cycles

Definition at line 605 of file stm32h7xx_hal_adc_ex.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Extended Calibration mode offset mode or linear mode

Defines
ADC Extended Calibration mode offset mode or linear mode
ADC Extended Exported Constants

Defines

#define | ADC_CALIB_OFFSET ((uint32_t)0x00000000)
#define | ADC_CALIB_OFFSET_LINEARITY (ADC_CR_ADCALLIN)

Define Documentation

#define ADC_CALIB_OFFSET ((uint32_t)0x00000000)

Definition at line 618 of file stm32h7xx_hal_adc_ex.h.

#define ADC_CALIB_OFFSET_LINEARITY (ADC_CR_ADCALLIN)

Definition at line 619 of file stm32h7xx_hal_adc_ex.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Extended Exported Constants

Modules | Defines
ADC Extended Exported Constants
ADCEx

Modules

ADC Extended External Trigger Source for Injected Group
ADC group injected trigger edge (when external trigger is selected)
ADC Extended Single-ended/Differential input mode
ADC Extended Offset Number
ADC Extended Injected Channel Rank
ADC Extended multimode dual mode
ADC Extended Dual Mode Data Formatting
ADC Extended delay between 2 sampling phases
ADC Extended Analog Watchdog Selection
ADC Extended Analog Watchdog Mode
ADC Extended Conversion Group
ADC Extended Event Type
ADC Extended Interrupts Definition
ADC Extended Flags Definition
ADC Extended Oversampling Right Shift
ADC Extended Oversampling left Shift
ADC Extended Triggered Regular Oversampling
ADC Extended Regular Oversampling Continued or Resumed Mode
ADC Sampling Times
ADC Extended Calibration mode offset mode or linear mode

Defines

#define ADC_AWD_EVENT ADC_AWD1_EVENT

Define Documentation

#define ADC_AWD_EVENT ADC_AWD1_EVENT

ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog

Definition at line 488 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForEvent().

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ADC Extended Private Macros

Defines
ADC Extended Private Macros
ADCEx

Defines

#define | IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
Verify the length of scheduled injected conversions group.
#define | IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= ((uint32_t)0x7F))
Calibration factor length verification (7 bits maximum)
#define | IS_ADC_CHANNEL(__CHANNEL__)
Verify the ADC channel setting.
#define | IS_ADC1_DIFF_CHANNEL(__CHANNEL__)
Verify the ADC channel setting in differential mode for ADC1.
#define | IS_ADC2_DIFF_CHANNEL(__CHANNEL__)
Verify the ADC channel setting in differential mode for ADC2.
#define | IS_ADC3_DIFF_CHANNEL(__CHANNEL__)
Verify the ADC channel setting in differential mode for ADC3.
#define | ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
Test if conversion trigger of injected group is software start or external trigger.
#define | ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__)
Check if no conversion on going on regular or injected groups.
#define | ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__)
Check if no conversion on going on injected group.
#define | ADC_IS_INDEPENDENT(__HANDLE__)
Check whether or not ADC is independent.
#define | ADC_SMPR1(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << (POSITION_VAL(ADC_SMPR1_SMP1) * (__CHANNELNB__)))
Set the ADC's sample time for Channels numbers between 0 and 9.
#define | ADC_SMPR2(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << ((POSITION_VAL(ADC_SMPR2_SMP11) * ((__CHANNELNB__) - 10))))
Set the ADC's sample time for Channels numbers between 10 and 18.
#define | ADC_SQR1_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR1_SQ1) * (__RANKNB__)))
Set the selected regular Channel rank for rank between 1 and 4.
#define | ADC_SQR2_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR2_SQ6) * ((__RANKNB__) - 5)))
Set the selected regular Channel rank for rank between 5 and 9.
#define | ADC_SQR3_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR3_SQ11) * ((__RANKNB__) - 10)))
Set the selected regular Channel rank for rank between 10 and 14.
#define | ADC_SQR4_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR4_SQ16) * ((__RANKNB__) - 15)))
Set the selected regular Channel rank for rank between 15 and 16.
#define | ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << ((POSITION_VAL(ADC_JSQR_JSQ1)-3) * (__RANKNB__) +3))
Set the selected injected Channel rank.
#define | ADC_CFGR_SET_AWD1CH(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_CFGR_AWD1CH))
Set the Analog Watchdog 1 channel.
#define | ADC_CFGR_SET_AWD23CR(__CHANNEL__) (1U << (__CHANNEL__))
Configure the channel number into Analog Watchdog 2 or 3.
#define | ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((uint32_t)(__INJECT_CONTEXT_QUEUE_MODE__) << POSITION_VAL(ADC_CFGR_JQM))
Enable ADC injected context queue.
#define | ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_JDISCEN))
Enable ADC discontinuous conversion mode for injected group.
#define | ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_DISCEN))
Enable ADC discontinuous conversion mode for regular group.
#define | ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << POSITION_VAL(ADC_CFGR_DISCNUM))
Configures the number of discontinuous conversions for regular group.
#define | ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << POSITION_VAL(ADC_CFGR_AUTDLY))
Enable the ADC auto delay mode.
#define | ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_CONT))
Enable ADC continuous conversion mode.
#define | ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__))
Enable the ADC DMA continuous request.
#define | ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_OFR1_OFFSET1_CH))
Configure the channel number into offset OFRx register.
#define | ADC_DIFSEL_CHANNEL(__CHANNEL__) (1U << (__CHANNEL__))
Configure the channel number into differential mode selection register.
#define | ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D >> POSITION_VAL(ADC_CALFACT_CALFACT_D)) ) << POSITION_VAL(ADC_CALFACT_CALFACT_D))
Calibration factor in differential mode to be set into calibration register.
#define | ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> POSITION_VAL(ADC_CALFACT_CALFACT_D))
Calibration factor in differential mode to be retrieved from calibration register.
#define | ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16)
Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
#define | ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CCR_DMACFG))
Enable the ADC DMA continuous request for ADC multimode.
#define | ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
Enable the ADC peripheral.
#define | ADC_ENABLING_CONDITIONS(__HANDLE__)
Verification of hardware constraints before ADC can be enabled.
#define | ADC_DISABLE(__HANDLE__)
Disable the ADC peripheral.
#define | ADC_DISABLING_CONDITIONS(__HANDLE__)
Verification of hardware constraints before ADC can be disabled.
#define | ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 2)*2))
Shift the offset in function of the selected ADC resolution.
#define | ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 2)*2))
Shift the AWD1 threshold in function of the selected ADC resolution.
#define | ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 2)*2))
Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.
#define | ADC12_COMMON_REGISTER(__HANDLE__) (ADC12_COMMON)
Report common register to ADC1 and ADC2.
#define | ADC3_COMMON_REGISTER(__HANDLE__) (ADC3_COMMON)
Report common register to ADC1 and ADC2.
#define | ADC_MASTER_REGISTER(__HANDLE__)
Report Master Instance.
#define | ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__)
Check whether or not dual regular conversions are enabled.
#define | ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)
Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master.
#define | ADC3_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)
Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master.
#define | ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__)
Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled.
#define | ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__)
Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled.
#define | ADC_INSTANCE_IS_ENABLED(__INSTANCE__)
Verification of ADC state: enabled or disabled, directly checked on instance as input parameter.
#define | ADC_ANY_OTHER_ENABLED(__HANDLE__)
Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle.
#define | ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
Set handle instance of the ADC slave associated to the ADC master.
#define | IS_ADC_SINGLE_DIFFERENTIAL(SING_DIFF)
Verify the ADC single-ended input or differential mode setting.
#define | IS_ADC_OFFSET_NUMBER(OFFSET_NUMBER)
Verify the ADC offset management setting.
#define | IS_ADC_INJECTED_RANK(CHANNEL)
Verify the ADC injected channel setting.
#define | IS_ADC_EXTTRIGINJEC(INJTRIG)
Verify the ADC injected conversions external trigger.
#define | IS_ADC_EXTTRIGINJEC_EDGE(EDGE)
Verify the ADC edge trigger setting for injected group.
#define | IS_ADC_MODE(MODE)
Verify the ADC multimode setting.
#define | IS_ADC_DUAL_DATA_MODE(MODE)
Verify the ADC dual data mode setting.
#define | IS_ADC_SAMPLING_DELAY(DELAY)
Verify the ADC multimode delay setting.
#define | IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG)
Verify the ADC analog watchdog setting.
#define | IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG)
Verify the ADC analog watchdog mode setting.
#define | IS_ADC_CONVERSION_GROUP(CONVERSION)
Verify the ADC conversion (regular or injected or both).
#define | IS_ADC_EVENT_TYPE(EVENT)
Verify the ADC event type.
#define | IS_ADC_SCAN_MODE(SCAN_MODE)
Verify the ADC scan mode.
#define | IS_ADC_OVERSAMPLING_RATIO(RATIO) ((RATIO) < 1024)
Verify the ADC oversampling ratio.
#define | IS_ADC_RIGHT_BIT_SHIFT(SHIFT)
Verify the ADC oversampling right shift.
#define | IS_ADC_LEFT_BIT_SHIFT(SHIFT)
Verify the ADC oversampling left shift.
#define | IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE)
Verify the ADC oversampling triggered mode.
#define | IS_ADC_REGOVERSAMPLING_MODE(MODE)
Verify the ADC oversampling regular conversion resumed or continued mode.

Define Documentation

#define ADC12_COMMON_REGISTER ( __HANDLE__ ) (ADC12_COMMON)

Report common register to ADC1 and ADC2.

Parameters:
__HANDLE__,: ADC handle
Return values:
Common control register

Definition at line 1020 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeGetValue(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER ( __HANDLE__ )
Value:
( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)     \
    )?                                                                         \
     SET                                                                       \
     :                                                                         \
     ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET)                            \
  )

Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode)

Definition at line 1063 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC3_COMMON_REGISTER ( __HANDLE__ ) (ADC3_COMMON)

Report common register to ADC1 and ADC2.

Parameters:
__HANDLE__,: ADC handle
Return values:
Common control register

Definition at line 1027 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC3_NONMULTIMODE_OR_MULTIMODEMASTER ( __HANDLE__ )
Value:
( ( ((__HANDLE__)->Instance == ADC3)                                          \
    )?                                                                         \
     SET                                                                       \
     :                                                                         \
     ((ADC3_COMMON->CCR & ADC_CCR_DUAL) == RESET)                            \
  )

Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode)

Definition at line 1076 of file stm32h7xx_hal_adc_ex.h.

#define ADC_ANY_OTHER_ENABLED ( __HANDLE__ )
Value:
( ( ((__HANDLE__)->Instance == ADC1)                                         \
    )?                                                                         \
     (ADC_INSTANCE_IS_ENABLED(ADC2)) || (ADC_INSTANCE_IS_ENABLED(ADC3))  \
     :                                                                         \
     ( ( ((__HANDLE__)->Instance == ADC2)                                      \
       )?                                                                      \
         (ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC3))  \
        :                                                                      \
          ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC2))    \
     )                                                                         \

Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (at least one other ADC is enabled) or RESET (no other ADC is enabled, all other ADCs are disabled)

Definition at line 1127 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION | ( | __HANDLE__,
 |  | __THRESHOLD__
 | ) | ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 2)*2))

Shift the AWD1 threshold in function of the selected ADC resolution.

Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0. If resolution 16 bits, no shift. If resolution 14 bits, shift of 2 ranks on the left. If resolution 12 bits, shift of 4 ranks on the left. If resolution 10 bits, shift of 6 ranks on the left. If resolution 8 bits, shift of 8 ranks on the left. therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2))

Parameters:
__HANDLE__,: ADC handle
__THRESHOLD__,: Value to be shifted
Return values:
None

Definition at line 996 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION | ( | __HANDLE__,
 |  | __THRESHOLD__
 | ) | ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 2)*2))

Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.

Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0. If resolution 16 bits, no shift. If resolution 14 bits, shift of 2 ranks on the left. If resolution 12 bits, shift of 4 ranks on the left. If resolution 10 bits, shift of 6 ranks on the left. If resolution 8 bits, shift of 8 ranks on the left. therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2))

Parameters:
__HANDLE__,: ADC handle
__THRESHOLD__,: Value to be shifted
Return values:
None

Definition at line 1012 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_CALFACT_DIFF_GET ( __CALIBRATION_FACTOR__ ) ((__CALIBRATION_FACTOR__) >> POSITION_VAL(ADC_CALFACT_CALFACT_D))

Calibration factor in differential mode to be retrieved from calibration register.

Parameters:
__CALIBRATION_FACTOR__,: Calibration factor value
Return values:
None

Definition at line 911 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_Calibration_GetValue().

#define ADC_CALFACT_DIFF_SET ( __CALIBRATION_FACTOR__ ) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D >> POSITION_VAL(ADC_CALFACT_CALFACT_D)) ) << POSITION_VAL(ADC_CALFACT_CALFACT_D))

Calibration factor in differential mode to be set into calibration register.

Parameters:
__CALIBRATION_FACTOR__,: Calibration factor value
Return values:
None

Definition at line 904 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_Calibration_SetValue().

#define ADC_CCR_MULTI_DMACONTREQ ( __DMACONTREQ_MODE__ ) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CCR_DMACFG))

Enable the ADC DMA continuous request for ADC multimode.

Parameters:
__DMACONTREQ_MODE__,: DMA continuous request mode.
Return values:
None

Definition at line 925 of file stm32h7xx_hal_adc_ex.h.

#define ADC_CFGR_AUTOWAIT ( __AUTOWAIT__ ) ((__AUTOWAIT__) << POSITION_VAL(ADC_CFGR_AUTDLY))

Enable the ADC auto delay mode.

Parameters:
__AUTOWAIT__,: Auto delay bit enable or disable.
Return values:
None

Definition at line 869 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_CONTINUOUS ( __CONTINUOUS_MODE__ ) ((__CONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_CONT))

Enable ADC continuous conversion mode.

Parameters:
__CONTINUOUS_MODE__,: Continuous mode.
Return values:
None

Definition at line 876 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_DISCONTINUOUS_NUM ( __NBR_DISCONTINUOUS_CONV__ ) (((__NBR_DISCONTINUOUS_CONV__) - 1) << POSITION_VAL(ADC_CFGR_DISCNUM))

Configures the number of discontinuous conversions for regular group.

Parameters:
__NBR_DISCONTINUOUS_CONV__,: Number of discontinuous conversions.
Return values:
None

Definition at line 862 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_DMACONTREQ ( __DMACONTREQ_MODE__ ) ((__DMACONTREQ_MODE__))

Enable the ADC DMA continuous request.

Parameters:
__DMACONTREQ_MODE__,: DMA continuous request mode.
Return values:
None

Definition at line 883 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_INJECT_CONTEXT_QUEUE ( __INJECT_CONTEXT_QUEUE_MODE__ ) ((uint32_t)(__INJECT_CONTEXT_QUEUE_MODE__) << POSITION_VAL(ADC_CFGR_JQM))

Enable ADC injected context queue.

Parameters:
__INJECT_CONTEXT_QUEUE_MODE__,: Injected context queue mode.
Return values:
None

Definition at line 841 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_CFGR_INJECT_DISCCONTINUOUS ( __INJECT_DISCONTINUOUS_MODE__ ) ((__INJECT_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_JDISCEN))

Enable ADC discontinuous conversion mode for injected group.

Parameters:
__INJECT_DISCONTINUOUS_MODE__,: Injected discontinuous mode.
Return values:
None

Definition at line 848 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_CFGR_REG_DISCONTINUOUS ( __REG_DISCONTINUOUS_MODE__ ) ((__REG_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_DISCEN))

Enable ADC discontinuous conversion mode for regular group.

Parameters:
__REG_DISCONTINUOUS_MODE__,: Regular discontinuous mode.
Return values:
None

Definition at line 855 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_SET_AWD1CH ( __CHANNEL__ ) ((__CHANNEL__) << POSITION_VAL(ADC_CFGR_AWD1CH))

Set the Analog Watchdog 1 channel.

Parameters:
__CHANNEL__,: channel to be monitored by Analog Watchdog 1.
Return values:
None

Definition at line 827 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_CFGR_SET_AWD23CR ( __CHANNEL__ ) (1U << (__CHANNEL__))

Configure the channel number into Analog Watchdog 2 or 3.

Parameters:
__CHANNEL__,: ADC Channel
Return values:
None

Definition at line 834 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_DIFSEL_CHANNEL ( __CHANNEL__ ) (1U << (__CHANNEL__))

Configure the channel number into differential mode selection register.

Parameters:
__CHANNEL__,: ADC Channel
Return values:
None

Definition at line 897 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_DISABLE ( __HANDLE__ )
Value:
do{                                                                          \
         (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS;                           \
          __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
  } while(0)

Disable the ADC peripheral.

Parameters:
__HANDLE__,: ADC handle
Return values:
None

Definition at line 951 of file stm32h7xx_hal_adc_ex.h.

Referenced by ADC_Disable().

#define ADC_DISABLING_CONDITIONS ( __HANDLE__ )
Value:
(( ( ((__HANDLE__)->Instance->CR) &                                     \
            (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN   \
        ) ? SET : RESET)

Verification of hardware constraints before ADC can be disabled.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (ADC can be disabled) or RESET (ADC cannot be disabled)

Definition at line 962 of file stm32h7xx_hal_adc_ex.h.

Referenced by ADC_Disable().

#define ADC_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)

Enable the ADC peripheral.

Parameters:
__HANDLE__,: ADC handle
Return values:
None

Definition at line 932 of file stm32h7xx_hal_adc_ex.h.

Referenced by ADC_Enable().

#define ADC_ENABLING_CONDITIONS ( __HANDLE__ )
Value:
(( ( ((__HANDLE__)->Instance->CR) &                                    \
            (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART |  \
             ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN                    ) \
           ) == RESET                                                         \
        ) ? SET : RESET)

Verification of hardware constraints before ADC can be enabled.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (ADC can be enabled) or RESET (ADC cannot be enabled)

Definition at line 939 of file stm32h7xx_hal_adc_ex.h.

Referenced by ADC_Enable().

#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE ( __HANDLE__ )
Value:
( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
    )?                                                                     \
     SET                                                                   \
     :                                                                     \
     ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)    || \
       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT)  || \
       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))

Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)

Definition at line 1103 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE ( __HANDLE__ )
Value:
( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3)  \
    )?                                                                      \
     SET                                                                    \
     :                                                                      \
     ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)     || \
       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))

Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)

Definition at line 1089 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_IT(), and HAL_ADCEx_InjectedPollForConversion().

#define ADC_INSTANCE_IS_ENABLED ( __INSTANCE__ )
Value:
(( ((((__INSTANCE__)->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
          ((((__INSTANCE__)->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)                  \
        ) ? SET : RESET)

Verification of ADC state: enabled or disabled, directly checked on instance as input parameter.

Parameters:
__INSTANCE__,: ADC instance
Return values:
SET (ADC enabled) or RESET (ADC disabled)

Definition at line 1117 of file stm32h7xx_hal_adc_ex.h.

#define ADC_IS_CONVERSION_ONGOING_INJECTED ( __HANDLE__ )
Value:
(( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET            \
        ) ? RESET : SET)

Check if no conversion on going on injected group.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (conversion is on going) or RESET (no conversion is on going)

Definition at line 749 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ( __HANDLE__ )
Value:
(( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET  \
        ) ? RESET : SET)

Check if no conversion on going on regular or injected groups.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (conversion is on going) or RESET (no conversion is on going)

Definition at line 740 of file stm32h7xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_DisableInjectedQueue(), HAL_ADCEx_EnableInjectedQueue(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE ( __HANDLE__ )
Value:
( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
    )?                                                                           \
     ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT)     &&      \
       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) &&      \
       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) )         \
     :                                                                           \
     RESET                                                                       \
  )

Check whether or not dual regular conversions are enabled.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)

Definition at line 1048 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForConversion(), and HAL_ADC_Start_DMA().

#define ADC_IS_INDEPENDENT ( __HANDLE__ )
Value:
( ( ( ((__HANDLE__)->Instance) == ADC3) \
    )?                                    \
     SET                                  \
     :                                    \
     RESET                                \
  )

Check whether or not ADC is independent.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (ADC is independent) or RESET (ADC is not)

Definition at line 758 of file stm32h7xx_hal_adc_ex.h.

#define ADC_IS_SOFTWARE_START_INJECTED ( __HANDLE__ ) (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)

Test if conversion trigger of injected group is software start or external trigger.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (software start) or RESET (external trigger)

Definition at line 732 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADCEx_InjectedPollForConversion().

#define ADC_JSQR_RK | ( | __CHANNELNB__,
 |  | __RANKNB__
 | ) | ((__CHANNELNB__) << ((POSITION_VAL(ADC_JSQR_JSQ1)-3) * (__RANKNB__) +3))

Set the selected injected Channel rank.

Parameters:
__CHANNELNB__,: Channel number.
__RANKNB__,: Rank number.
Return values:
None

Definition at line 820 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_MASTER_REGISTER ( __HANDLE__ )
Value:
( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \
    )?                                                                           \
     ((__HANDLE__)->Instance)                                                    \
     :                                                                           \
     (ADC1)                                                                      \
  )

Report Master Instance.

Parameters:
__HANDLE__,: ADC handle
Note:
return same instance if ADC of input handle is independent ADC
Return values:
Master Instance

Definition at line 1035 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_IT(), and HAL_ADCEx_InjectedPollForConversion().

#define ADC_MULTI_SLAVE | ( | __HANDLE_MASTER__,
 |  | __HANDLE_SLAVE__
 | ) | ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )

Set handle instance of the ADC slave associated to the ADC master.

Parameters:
__HANDLE_MASTER__,: ADC master handle
__HANDLE_SLAVE__,: ADC slave handle
Note:
if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC (ADC3), __HANDLE_SLAVE__ instance is set to NULL
Return values:
None

Definition at line 1146 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), and HAL_ADCEx_RegularMultiModeStop_DMA().

#define ADC_OFFSET_SHIFT_RESOLUTION | ( | __HANDLE__,
 |  | __OFFSET__
 | ) | ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 2)*2))

Shift the offset in function of the selected ADC resolution.

Offset has to be left-aligned on bit 15, the LSB (right bits) are set to 0 If resolution 16 bits, no shift. If resolution 14 bits, shift of 2 ranks on the left. If resolution 12 bits, shift of 4 ranks on the left. If resolution 10 bits, shift of 6 ranks on the left. If resolution 8 bits, shift of 8 ranks on the left. therefore, shift = (16 - resolution) = 16 - (16 - (((RES[2:0]) >> 2)*2))

Parameters:
__HANDLE__,: ADC handle
__OFFSET__,: Value to be shifted
Return values:
None

Definition at line 980 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_OFR_CHANNEL ( __CHANNEL__ ) ((__CHANNEL__) << POSITION_VAL(ADC_OFR1_OFFSET1_CH))

Configure the channel number into offset OFRx register.

Parameters:
__CHANNEL__,: ADC Channel
Return values:
None

Definition at line 890 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SMPR1 | ( | __SAMPLETIME__,
 |  | __CHANNELNB__
 | ) | ((__SAMPLETIME__) << (POSITION_VAL(ADC_SMPR1_SMP1) * (__CHANNELNB__)))

Set the ADC's sample time for Channels numbers between 0 and 9.

Parameters:
__SAMPLETIME__,: Sample time parameter.
__CHANNELNB__,: Channel number.
Return values:
None

Definition at line 772 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SMPR2 | ( | __SAMPLETIME__,
 |  | __CHANNELNB__
 | ) | ((__SAMPLETIME__) << ((POSITION_VAL(ADC_SMPR2_SMP11) * ((__CHANNELNB__) - 10))))

Set the ADC's sample time for Channels numbers between 10 and 18.

Parameters:
__SAMPLETIME__,: Sample time parameter.
__CHANNELNB__,: Channel number.
Return values:
None

Definition at line 780 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SQR1_RK | ( | __CHANNELNB__,
 |  | __RANKNB__
 | ) | ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR1_SQ1) * (__RANKNB__)))

Set the selected regular Channel rank for rank between 1 and 4.

Parameters:
__CHANNELNB__,: Channel number.
__RANKNB__,: Rank number.
Return values:
None

Definition at line 788 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_SQR2_RK | ( | __CHANNELNB__,
 |  | __RANKNB__
 | ) | ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR2_SQ6) * ((__RANKNB__) - 5)))

Set the selected regular Channel rank for rank between 5 and 9.

Parameters:
__CHANNELNB__,: Channel number.
__RANKNB__,: Rank number.
Return values:
None

Definition at line 796 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_SQR3_RK | ( | __CHANNELNB__,
 |  | __RANKNB__
 | ) | ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR3_SQ11) * ((__RANKNB__) - 10)))

Set the selected regular Channel rank for rank between 10 and 14.

Parameters:
__CHANNELNB__,: Channel number.
__RANKNB__,: Rank number.
Return values:
None

Definition at line 804 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_SQR4_RK | ( | __CHANNELNB__,
 |  | __RANKNB__
 | ) | ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR4_SQ16) * ((__RANKNB__) - 15)))

Set the selected regular Channel rank for rank between 15 and 16.

Parameters:
__CHANNELNB__,: Channel number.
__RANKNB__,: Rank number.
Return values:
None

Definition at line 812 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_TRX_HIGHTHRESHOLD ( __THRESHOLD__ ) ((__THRESHOLD__) << 16)

Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.

Parameters:
__THRESHOLD__,: Threshold value
Return values:
None

Definition at line 918 of file stm32h7xx_hal_adc_ex.h.

#define IS_ADC1_DIFF_CHANNEL ( __CHANNEL__ )
Value:
(((__CHANNEL__) == ADC_CHANNEL_1)|| \
                                      ((__CHANNEL__) == ADC_CHANNEL_2)      ||\
                                      ((__CHANNEL__) == ADC_CHANNEL_3)      ||\
                                      ((__CHANNEL__) == ADC_CHANNEL_4)      ||\
                                      ((__CHANNEL__) == ADC_CHANNEL_5)      ||\
                                      ((__CHANNEL__) == ADC_CHANNEL_10)     ||\
                                      ((__CHANNEL__) == ADC_CHANNEL_11)     ||\
                                      ((__CHANNEL__) == ADC_CHANNEL_12)     ||\
                                      ((__CHANNEL__) == ADC_CHANNEL_16)     ||\
                                      ((__CHANNEL__) == ADC_CHANNEL_18)      )

Verify the ADC channel setting in differential mode for ADC1.

Parameters:
__CHANNEL__,: programmed ADC channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 684 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC2_DIFF_CHANNEL ( __CHANNEL__ )
Value:
(((__CHANNEL__) == ADC_CHANNEL_1)|| \
                                      ((__CHANNEL__) == ADC_CHANNEL_2)      || \
                                      ((__CHANNEL__) == ADC_CHANNEL_3)      || \
                                      ((__CHANNEL__) == ADC_CHANNEL_4)      || \
                                      ((__CHANNEL__) == ADC_CHANNEL_5)      || \
                                      ((__CHANNEL__) == ADC_CHANNEL_10)     || \
                                      ((__CHANNEL__) == ADC_CHANNEL_11)     || \
                                      ((__CHANNEL__) == ADC_CHANNEL_12)     || \
                                      ((__CHANNEL__) == ADC_CHANNEL_18)      )

Verify the ADC channel setting in differential mode for ADC2.

Parameters:
__CHANNEL__,: programmed ADC channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 700 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC3_DIFF_CHANNEL ( __CHANNEL__ )
Value:
(((__CHANNEL__) == ADC_CHANNEL_1) || \
                                      ((__CHANNEL__) == ADC_CHANNEL_2)      || \
                                      ((__CHANNEL__) == ADC_CHANNEL_3)      || \
                                      ((__CHANNEL__) == ADC_CHANNEL_4)      || \
                                      ((__CHANNEL__) == ADC_CHANNEL_5)      || \
                                      ((__CHANNEL__) == ADC_CHANNEL_10)     || \
                                      ((__CHANNEL__) == ADC_CHANNEL_11)     || \
                                      ((__CHANNEL__) == ADC_CHANNEL_13)     || \
                                      ((__CHANNEL__) == ADC_CHANNEL_14)     || \
                                      ((__CHANNEL__) == ADC_CHANNEL_15)       )

Verify the ADC channel setting in differential mode for ADC3.

Parameters:
__CHANNEL__,: programmed ADC channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 715 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_ANALOG_WATCHDOG_MODE ( WATCHDOG )
Value:
(((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)             || \
                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)     || \
                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  || \
                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)          || \
                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC)        || \
                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)       )

Verify the ADC analog watchdog mode setting.

Parameters:
WATCHDOG,: programmed ADC analog watchdog mode setting.
Return values:
SET (WATCHDOG is valid) or RESET (WATCHDOG is invalid)

Definition at line 1264 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define IS_ADC_ANALOG_WATCHDOG_NUMBER ( WATCHDOG )
Value:
(((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \
                                                 ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \
                                                 ((WATCHDOG) == ADC_ANALOGWATCHDOG_3)   )

Verify the ADC analog watchdog setting.

Parameters:
WATCHDOG,: programmed ADC analog watchdog setting.
Return values:
SET (WATCHDOG is valid) or RESET (WATCHDOG is invalid)

Definition at line 1255 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define IS_ADC_CALFACT ( _Calibration_Factor_ ) ((_Calibration_Factor_) <= ((uint32_t)0x7F))

Calibration factor length verification (7 bits maximum)

Parameters:
_Calibration_Factor_,: Calibration factor value
Return values:
None

Definition at line 646 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_Calibration_SetValue().

#define IS_ADC_CHANNEL ( __CHANNEL__ )
Value:
(((__CHANNEL__) == ADC_CHANNEL_0)       || \
                                 ((__CHANNEL__) == ADC_CHANNEL_1)           || \
                                 ((__CHANNEL__) == ADC_CHANNEL_2)           || \
                                 ((__CHANNEL__) == ADC_CHANNEL_3)           || \
                                 ((__CHANNEL__) == ADC_CHANNEL_4)           || \
                                 ((__CHANNEL__) == ADC_CHANNEL_5)           || \
                                 ((__CHANNEL__) == ADC_CHANNEL_6)           || \
                                 ((__CHANNEL__) == ADC_CHANNEL_7)           || \
                                 ((__CHANNEL__) == ADC_CHANNEL_8)           || \
                                 ((__CHANNEL__) == ADC_CHANNEL_9)           || \
                                 ((__CHANNEL__) == ADC_CHANNEL_10)          || \
                                 ((__CHANNEL__) == ADC_CHANNEL_11)          || \
                                 ((__CHANNEL__) == ADC_CHANNEL_12)          || \
                                 ((__CHANNEL__) == ADC_CHANNEL_13)          || \
                                 ((__CHANNEL__) == ADC_CHANNEL_14)          || \
                                 ((__CHANNEL__) == ADC_CHANNEL_15)          || \
                                 ((__CHANNEL__) == ADC_CHANNEL_16)          || \
                                 ((__CHANNEL__) == ADC_CHANNEL_17)          || \
                                 ((__CHANNEL__) == ADC_CHANNEL_18)          || \
                                 ((__CHANNEL__) == ADC_CHANNEL_19)          || \
                                 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR)  || \
                                 ((__CHANNEL__) == ADC_CHANNEL_VBAT_DIV4)   || \
                                 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2)|| \
                                 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2)|| \
                                 ((__CHANNEL__) == ADC_CHANNEL_VREFINT)       )

Verify the ADC channel setting.

Parameters:
__CHANNEL__,: programmed ADC channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 653 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_CONVERSION_GROUP ( CONVERSION )
Value:
(((CONVERSION) == ADC_REGULAR_GROUP)         || \
                                                 ((CONVERSION) == ADC_INJECTED_GROUP)        || \
                                                 ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP)  )

Verify the ADC conversion (regular or injected or both).

Parameters:
CONVERSION,: ADC conversion group.
Return values:
SET (CONVERSION is valid) or RESET (CONVERSION is invalid)

Definition at line 1276 of file stm32h7xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop().

#define IS_ADC_DUAL_DATA_MODE ( MODE )
Value:
(((MODE) == ADC_DUALMODEDATAFORMAT_DISABLED)   || \
                                     ((MODE) == ADC_DUALMODEDATAFORMAT_32_10_BITS) || \
                                     ((MODE) == ADC_DUALMODEDATAFORMAT_8_BITS)     )

Verify the ADC dual data mode setting.

Parameters:
MODE,: programmed ADC dual mode setting.
Return values:
SET (MODE is valid) or RESET (MODE is invalid)

Definition at line 1231 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

#define IS_ADC_EVENT_TYPE ( EVENT )
Value:
(((EVENT) == ADC_EOSMP_EVENT) || \
                                  ((EVENT) == ADC_AWD_EVENT)   || \
                                  ((EVENT) == ADC_AWD2_EVENT)  || \
                                  ((EVENT) == ADC_AWD3_EVENT)  || \
                                  ((EVENT) == ADC_OVR_EVENT)   || \
                                  ((EVENT) == ADC_JQOVF_EVENT)  )

Verify the ADC event type.

Parameters:
EVENT,: ADC event.
Return values:
SET (EVENT is valid) or RESET (EVENT is invalid)

Definition at line 1285 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForEvent().

#define IS_ADC_EXTTRIGINJEC ( INJTRIG )
Value:
(((INJTRIG) == ADC_EXTERNALTRIGINJEC_T1_TRGO)     || \
                                      ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T1_CC4)      || \
                                      ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T2_TRGO)     || \
                                      ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T2_CC1)      || \
                                      ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T3_CC4)      || \
                                      ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T4_TRGO)     || \
                                      ((INJTRIG) == ADC_EXTERNALTRIGINJEC_EXT_IT15)    || \
                                      ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T8_CC4)      || \
                                      ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)    || \
                                      ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T8_TRGO)     || \
                                      ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)    || \
                                      ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T3_CC3)      || \
                                      ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T3_TRGO)     || \
                                      ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T3_CC1)      || \
                                      ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T6_TRGO)     || \
                                      ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T15_TRGO)    || \
                                                                                \
                                      ((INJTRIG) == ADC_SOFTWARE_START)                   )

Verify the ADC injected conversions external trigger.

Parameters:
INJTRIG,: programmed ADC injected conversions external trigger.
Return values:
SET (INJTRIG is a valid value) or RESET (INJTRIG is invalid)

Definition at line 1183 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_EXTTRIGINJEC_EDGE ( EDGE )
Value:
(((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)         || \
                                        ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
                                        ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
                                        ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING)  )

Verify the ADC edge trigger setting for injected group.

Parameters:
EDGE,: programmed ADC edge trigger setting.
Return values:
SET (EDGE is a valid value) or RESET (EDGE is invalid)

Definition at line 1207 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_INJECTED_NB_CONV ( LENGTH ) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))

Verify the length of scheduled injected conversions group.

Parameters:
LENGTH : number of programmed conversions.
Return values:
SET (LENGTH is within the maximum number of possible programmable injected conversions) or RESET (LENGTH is null or too large)

Definition at line 639 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_INJECTED_RANK ( CHANNEL )
Value:
(((CHANNEL) == ADC_INJECTED_RANK_1) || \
                                       ((CHANNEL) == ADC_INJECTED_RANK_2) || \
                                       ((CHANNEL) == ADC_INJECTED_RANK_3) || \
                                       ((CHANNEL) == ADC_INJECTED_RANK_4)   )

Verify the ADC injected channel setting.

Parameters:
CHANNEL,: programmed ADC injected channel.
Return values:
SET (CHANNEL is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 1173 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel(), and HAL_ADCEx_InjectedGetValue().

#define IS_ADC_LEFT_BIT_SHIFT ( SHIFT )
Value:
(((SHIFT) == ADC_LEFTBITSHIFT_NONE) || \
                                                     ((SHIFT) == ADC_LEFTBITSHIFT_1   ) || \
                                                     ((SHIFT) == ADC_LEFTBITSHIFT_2   ) || \
                                                     ((SHIFT) == ADC_LEFTBITSHIFT_3   ) || \
                                                     ((SHIFT) == ADC_LEFTBITSHIFT_4   ) || \
                                                     ((SHIFT) == ADC_LEFTBITSHIFT_5   ) || \
                                                     ((SHIFT) == ADC_LEFTBITSHIFT_6   ) || \
                                                     ((SHIFT) == ADC_LEFTBITSHIFT_7   ) || \
                                                     ((SHIFT) == ADC_LEFTBITSHIFT_8   ) || \
                                                     ((SHIFT) == ADC_LEFTBITSHIFT_9   ) || \
                                                     ((SHIFT) == ADC_LEFTBITSHIFT_10   ) || \
                                                     ((SHIFT) == ADC_LEFTBITSHIFT_11   ) || \
                                                     ((SHIFT) == ADC_LEFTBITSHIFT_12   ) || \
                                                     ((SHIFT) == ADC_LEFTBITSHIFT_13   ) || \
                                                     ((SHIFT) == ADC_LEFTBITSHIFT_14   ) || \
                                                     ((SHIFT) == ADC_LEFTBITSHIFT_15   ))

Verify the ADC oversampling left shift.

Parameters:
SHIFT,: programmed ADC oversampling left shift.
Return values:
SET (SHIFT is a valid value) or RESET (SHIFT is invalid)

Definition at line 1327 of file stm32h7xx_hal_adc_ex.h.

#define IS_ADC_MODE ( MODE )
Value:
(((MODE) == ADC_MODE_INDEPENDENT)               || \
                           ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
                           ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)   || \
                           ((MODE) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
                           ((MODE) == ADC_DUALMODE_INJECSIMULT)           || \
                           ((MODE) == ADC_DUALMODE_REGSIMULT)             || \
                           ((MODE) == ADC_DUALMODE_INTERL)                || \
                           ((MODE) == ADC_DUALMODE_ALTERTRIG)               )

Verify the ADC multimode setting.

Parameters:
MODE,: programmed ADC multimode setting.
Return values:
SET (MODE is valid) or RESET (MODE is invalid)

Definition at line 1217 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

#define IS_ADC_OFFSET_NUMBER ( OFFSET_NUMBER )
Value:
(((OFFSET_NUMBER) == ADC_OFFSET_NONE) || \
                                             ((OFFSET_NUMBER) == ADC_OFFSET_1)    || \
                                             ((OFFSET_NUMBER) == ADC_OFFSET_2)    || \
                                             ((OFFSET_NUMBER) == ADC_OFFSET_3)    || \
                                             ((OFFSET_NUMBER) == ADC_OFFSET_4)      )

Verify the ADC offset management setting.

Parameters:
OFFSET_NUMBER,: ADC offset management.
Return values:
SET (OFFSET_NUMBER is valid) or RESET (OFFSET_NUMBER is invalid)

Definition at line 1162 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_OVERSAMPLING_RATIO ( RATIO ) ((RATIO) < 1024)

Verify the ADC oversampling ratio.

Parameters:
RATIO,: programmed ADC oversampling ratio.
Return values:
SET (RATIO is a valid value) or RESET (RATIO is invalid)

Definition at line 1305 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_REGOVERSAMPLING_MODE ( MODE )
Value:
(((MODE) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
                                           ((MODE) == ADC_REGOVERSAMPLING_RESUMED_MODE) )

Verify the ADC oversampling regular conversion resumed or continued mode.

Parameters:
MODE,: programmed ADC oversampling regular conversion resumed or continued mode.
Return values:
SET (MODE is valid) or RESET (MODE is invalid)

Definition at line 1357 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_RIGHT_BIT_SHIFT ( SHIFT )
Value:
(((SHIFT) == ADC_RIGHTBITSHIFT_NONE) || \
                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_1   ) || \
                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_2   ) || \
                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_3   ) || \
                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_4   ) || \
                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_5   ) || \
                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_6   ) || \
                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_7   ) || \
                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_8   ))

Verify the ADC oversampling right shift.

Parameters:
SHIFT,: programmed ADC oversampling right shift.
Return values:
SET (SHIFT is a valid value) or RESET (SHIFT is invalid)

Definition at line 1312 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_SAMPLING_DELAY ( DELAY )
Value:
(((DELAY) == ADC_TWOSAMPLINGDELAY_1CYCLE)   || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_2CYCLES)  || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_3CYCLES)  || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_4CYCLES)  || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES))

Verify the ADC multimode delay setting.

Parameters:
DELAY,: programmed ADC multimode delay setting.
Return values:
SET (DELAY is a valid value) or RESET (DELAY is invalid)

Definition at line 1240 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

#define IS_ADC_SCAN_MODE ( SCAN_MODE )
Value:
(((SCAN_MODE) == ADC_SCAN_DISABLE) || \
                                     ((SCAN_MODE) == ADC_SCAN_ENABLE)    )

Verify the ADC scan mode.

Parameters:
SCAN_MODE,: ADC scan mode.
Return values:
SET (SCAN_MODE is valid) or RESET (SCAN_MODE is invalid)

Definition at line 1297 of file stm32h7xx_hal_adc_ex.h.

#define IS_ADC_SINGLE_DIFFERENTIAL ( SING_DIFF )
Value:
(((SING_DIFF) == ADC_SINGLE_ENDED)      || \
                                               ((SING_DIFF) == ADC_DIFFERENTIAL_ENDED)  )

Verify the ADC single-ended input or differential mode setting.

Parameters:
SING_DIFF,: programmed channel setting.
Return values:
SET (SING_DIFF is valid) or RESET (SING_DIFF is invalid)

Definition at line 1154 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), HAL_ADCEx_Calibration_GetValue(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE ( MODE )
Value:
(((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
                                                  ((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )

Verify the ADC oversampling triggered mode.

Parameters:
MODE,: programmed ADC oversampling triggered mode.
Return values:
SET (MODE is valid) or RESET (MODE is invalid)

Definition at line 1349 of file stm32h7xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CEC Private Constants

CEC Private Constants
CEC
Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CEC Private Functions

CEC Private Functions
CEC
Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CEC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CEC_Init (CEC_HandleTypeDef *hcec)
Initializes the CEC mode according to the specified parameters in the CEC_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_CEC_DeInit (CEC_HandleTypeDef *hcec)
DeInitializes the CEC peripheral.
HAL_StatusTypeDef | HAL_CEC_SetDeviceAddress (CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
Initializes the Own Address of the CEC device.
__weak void | HAL_CEC_MspInit (CEC_HandleTypeDef *hcec)
CEC MSP Init.
__weak void | HAL_CEC_MspDeInit (CEC_HandleTypeDef *hcec)
CEC MSP DeInit.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the CEC
      (+) The following parameters need to be configured:
        (++) SignalFreeTime
        (++) Tolerance
        (++) BRERxStop                 (RX stopped or not upon Bit Rising Error)
        (++) BREErrorBitGen            (Error-Bit generation in case of Bit Rising Error)
        (++) LBPEErrorBitGen           (Error-Bit generation in case of Long Bit Period Error)
        (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
        (++) SignalFreeTimeOption      (SFT Timer start definition)
        (++) OwnAddress                (CEC device address)
        (++) ListenMode

Function Documentation

HAL_StatusTypeDef HAL_CEC_DeInit ( CEC_HandleTypeDef * hcec )

DeInitializes the CEC peripheral.

Parameters:
hcec,: CEC handle
Return values:
HAL status

Definition at line 217 of file stm32h7xx_hal_cec.c.

References __HAL_CEC_CLEAR_FLAG, __HAL_CEC_DISABLE, __HAL_CEC_DISABLE_IT, assert_param, CEC_FLAG_RXBR, CEC_FLAG_RXEND, CEC_FLAG_TXBR, CEC_FLAG_TXEND, CEC_IER_RX_ALL_ERR, CEC_IER_TX_ALL_ERR, CEC_ISR_ALL_ERROR, CEC_IT_RXBR, CEC_IT_RXEND, CEC_IT_TXBR, CEC_IT_TXEND, CEC_HandleTypeDef::ErrorCode, CEC_HandleTypeDef::gState, HAL_CEC_ERROR_NONE, HAL_CEC_MspDeInit(), HAL_CEC_STATE_BUSY, HAL_CEC_STATE_RESET, CEC_HandleTypeDef::Instance, and CEC_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_CEC_Init ( CEC_HandleTypeDef * hcec )

Initializes the CEC mode according to the specified parameters in the CEC_InitTypeDef and creates the associated handle.

Parameters:
hcec,: CEC handle
Return values:
HAL status

Definition at line 147 of file stm32h7xx_hal_cec.c.

References __HAL_CEC_DISABLE, __HAL_CEC_ENABLE, __HAL_CEC_ENABLE_IT, assert_param, CEC_InitTypeDef::BREErrorBitGen, CEC_InitTypeDef::BRERxStop, CEC_InitTypeDef::BroadcastMsgNoErrorBitGen, CEC_IER_RX_ALL_ERR, CEC_IER_TX_ALL_ERR, CEC_IT_RXBR, CEC_IT_RXEND, CEC_IT_TXBR, CEC_IT_TXEND, CEC_HandleTypeDef::ErrorCode, CEC_HandleTypeDef::gState, HAL_CEC_ERROR_NONE, HAL_CEC_MspInit(), HAL_CEC_STATE_BUSY, HAL_CEC_STATE_READY, HAL_CEC_STATE_RESET, CEC_HandleTypeDef::Init, CEC_HandleTypeDef::Instance, IS_CEC_BREERRORBITGEN, IS_CEC_BRERXSTOP, IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION, IS_CEC_LBPEERRORBITGEN, IS_CEC_LISTENING_MODE, IS_CEC_OWN_ADDRESS, IS_CEC_SFTOP, IS_CEC_SIGNALFREETIME, IS_CEC_TOLERANCE, CEC_InitTypeDef::LBPEErrorBitGen, CEC_InitTypeDef::ListenMode, CEC_HandleTypeDef::Lock, CEC_InitTypeDef::OwnAddress, CEC_InitTypeDef::RxBuffer, CEC_HandleTypeDef::RxState, CEC_InitTypeDef::SignalFreeTime, CEC_InitTypeDef::SignalFreeTimeOption, and CEC_InitTypeDef::Tolerance.

void HAL_CEC_MspDeInit ( CEC_HandleTypeDef * hcec )

CEC MSP DeInit.

Parameters:
hcec,: CEC handle
Return values:
None

Definition at line 332 of file stm32h7xx_hal_cec.c.

Referenced by HAL_CEC_DeInit().

void HAL_CEC_MspInit ( CEC_HandleTypeDef * hcec )

CEC MSP Init.

Parameters:
hcec,: CEC handle
Return values:
None

Definition at line 318 of file stm32h7xx_hal_cec.c.

Referenced by HAL_CEC_Init().

HAL_StatusTypeDef HAL_CEC_SetDeviceAddress | ( | CEC_HandleTypeDef * | hcec,
 |  | uint16_t | CEC_OwnAddress
 | ) |  |

Initializes the Own Address of the CEC device.

Parameters:
hcec,: CEC handle
CEC_OwnAddress,: The CEC own address.
Return values:
HAL status

Definition at line 272 of file stm32h7xx_hal_cec.c.

References __HAL_CEC_DISABLE, __HAL_CEC_ENABLE, assert_param, CEC_OWN_ADDRESS_NONE, CEC_HandleTypeDef::ErrorCode, CEC_HandleTypeDef::gState, HAL_CEC_ERROR_NONE, HAL_CEC_STATE_BUSY, HAL_CEC_STATE_READY, CEC_HandleTypeDef::Instance, IS_CEC_OWN_ADDRESS, and CEC_HandleTypeDef::RxState.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
CEC Exported Functions

CEC Transmit/Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_CEC_Transmit_IT (CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
Send data in interrupt mode.
uint32_t | HAL_CEC_GetLastReceivedFrameSize (CEC_HandleTypeDef *hcec)
Get size of the received frame.
void | HAL_CEC_ChangeRxBuffer (CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
Change Rx Buffer.
void | HAL_CEC_IRQHandler (CEC_HandleTypeDef *hcec)
This function handles CEC interrupt requests.
__weak void | HAL_CEC_TxCpltCallback (CEC_HandleTypeDef *hcec)
Tx Transfer completed callback.
__weak void | HAL_CEC_RxCpltCallback (CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
Rx Transfer completed callback.
__weak void | HAL_CEC_ErrorCallback (CEC_HandleTypeDef *hcec)
CEC error callbacks.

Detailed Description

CEC Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the CEC data transfers.

    (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
        logical addresses (4-bit long addresses, 0xF for broadcast messages destination)

    (#) The communication is performed using Interrupts.
           These API's return the HAL status.
           The end of the data processing will be indicated through the
           dedicated CEC IRQ when using Interrupt mode.
           The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or Receive process
           The HAL_CEC_ErrorCallback() user callback will be executed when a communication
           error is detected

    (#) API's with Interrupt are :
         (+) HAL_CEC_Transmit_IT()
         (+) HAL_CEC_IRQHandler()

    (#) A set of User Callbacks are provided:
         (+) HAL_CEC_TxCpltCallback()
         (+) HAL_CEC_RxCpltCallback()
         (+) HAL_CEC_ErrorCallback()

Function Documentation

void HAL_CEC_ChangeRxBuffer | ( | CEC_HandleTypeDef * | hcec,
 |  | uint8_t * | Rxbuffer
 | ) |  |

Change Rx Buffer.

Parameters:
hcec,: CEC handle
Rxbuffer,: Rx Buffer
Note:
This function can be called only inside the HAL_CEC_RxCpltCallback()
Return values:
Frame size

Definition at line 455 of file stm32h7xx_hal_cec.c.

References CEC_HandleTypeDef::Init, and CEC_InitTypeDef::RxBuffer.

void HAL_CEC_ErrorCallback ( CEC_HandleTypeDef * hcec )

CEC error callbacks.

Parameters:
hcec,: CEC handle
Return values:
None

Definition at line 596 of file stm32h7xx_hal_cec.c.

Referenced by HAL_CEC_IRQHandler().

uint32_t HAL_CEC_GetLastReceivedFrameSize ( CEC_HandleTypeDef * hcec )

Get size of the received frame.

Parameters:
hcec,: CEC handle
Return values:
Frame size

Definition at line 443 of file stm32h7xx_hal_cec.c.

References CEC_HandleTypeDef::RxXferSize.

void HAL_CEC_IRQHandler ( CEC_HandleTypeDef * hcec )

This function handles CEC interrupt requests.

Parameters:
hcec,: CEC handle
Return values:
None

Definition at line 465 of file stm32h7xx_hal_cec.c.

References __HAL_CEC_CLEAR_FLAG, __HAL_CEC_LAST_BYTE_TX_SET, CEC_FLAG_ARBLST, CEC_FLAG_LBPE, CEC_FLAG_RXBR, CEC_FLAG_RXEND, CEC_FLAG_SBPE, CEC_FLAG_TXBR, CEC_FLAG_TXEND, CEC_HandleTypeDef::ErrorCode, CEC_HandleTypeDef::gState, HAL_CEC_ERROR_ARBLST, HAL_CEC_ERROR_BRE, HAL_CEC_ERROR_NONE, HAL_CEC_ERROR_RXACKE, HAL_CEC_ERROR_RXOVR, HAL_CEC_ERROR_TXACKE, HAL_CEC_ERROR_TXERR, HAL_CEC_ERROR_TXUDR, HAL_CEC_ErrorCallback(), HAL_CEC_RxCpltCallback(), HAL_CEC_STATE_BUSY_RX, HAL_CEC_STATE_READY, HAL_CEC_TxCpltCallback(), CEC_HandleTypeDef::Init, CEC_HandleTypeDef::Instance, CEC_HandleTypeDef::pTxBuffPtr, CEC_InitTypeDef::RxBuffer, CEC_HandleTypeDef::RxState, CEC_HandleTypeDef::RxXferSize, and CEC_HandleTypeDef::TxXferCount.

void HAL_CEC_RxCpltCallback | ( | CEC_HandleTypeDef * | hcec,
 |  | uint32_t | RxFrameSize
 | ) |  |

Rx Transfer completed callback.

Parameters:
hcec,: CEC handle
RxFrameSize,: Size of frame
Return values:
None

Definition at line 581 of file stm32h7xx_hal_cec.c.

Referenced by HAL_CEC_IRQHandler().

HAL_StatusTypeDef HAL_CEC_Transmit_IT | ( | CEC_HandleTypeDef * | hcec,
 |  | uint8_t | InitiatorAddress,
 |  | uint8_t | DestinationAddress,
 |  | uint8_t * | pData,
 |  | uint32_t | Size
 | ) |  |

Send data in interrupt mode.

Parameters:
hcec,: CEC handle
InitiatorAddress,: Initiator address
DestinationAddress,: destination logical address
pData,: pointer to input byte data buffer
Size,: amount of data to be sent in bytes (without counting the header). 0 means only the header is sent (ping operation). Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
Return values:
HAL status

Definition at line 390 of file stm32h7xx_hal_cec.c.

References __HAL_CEC_FIRST_BYTE_TX_SET, __HAL_CEC_LAST_BYTE_TX_SET, assert_param, CEC_INITIATOR_LSB_POS, CEC_HandleTypeDef::ErrorCode, CEC_HandleTypeDef::gState, HAL_CEC_ERROR_NONE, HAL_CEC_STATE_BUSY_TX, HAL_CEC_STATE_READY, CEC_HandleTypeDef::Instance, IS_CEC_ADDRESS, IS_CEC_MSGSIZE, CEC_HandleTypeDef::pTxBuffPtr, and CEC_HandleTypeDef::TxXferCount.

void HAL_CEC_TxCpltCallback ( CEC_HandleTypeDef * hcec )

Tx Transfer completed callback.

Parameters:
hcec,: CEC handle
Return values:
None

Definition at line 566 of file stm32h7xx_hal_cec.c.

Referenced by HAL_CEC_IRQHandler().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control function

Functions
Peripheral Control function
CEC Exported Functions

CEC control functions. More...

Functions

HAL_CEC_StateTypeDef | HAL_CEC_GetState (CEC_HandleTypeDef *hcec)
return the CEC state
uint32_t | HAL_CEC_GetError (CEC_HandleTypeDef *hcec)
Return the CEC error code.

Detailed Description

CEC control functions.

 ===============================================================================
                      ##### Peripheral Control function #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the CEC.
     (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
     (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.

Function Documentation

uint32_t HAL_CEC_GetError ( CEC_HandleTypeDef * hcec )

Return the CEC error code.

Parameters:
hcec : pointer to a CEC_HandleTypeDef structure that contains the configuration information for the specified CEC.
Return values:
CEC Error Code

Definition at line 644 of file stm32h7xx_hal_cec.c.

References CEC_HandleTypeDef::ErrorCode.

HAL_CEC_StateTypeDef HAL_CEC_GetState ( CEC_HandleTypeDef * hcec )

return the CEC state

Parameters:
hcec,: pointer to a CEC_HandleTypeDef structure that contains the configuration information for the specified CEC module.
Return values:
HAL state

Definition at line 629 of file stm32h7xx_hal_cec.c.

References CEC_HandleTypeDef::gState, and CEC_HandleTypeDef::RxState.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CEC Exported Types

Data Structures | Enumerations
CEC Exported Types
CEC

Data Structures

struct | CEC_InitTypeDef
CEC Init Structure definition. More...
struct | CEC_HandleTypeDef
CEC handle Structure definition. More...

Enumerations

enum HAL_CEC_StateTypeDef {
HAL_CEC_STATE_RESET = 0x00U, HAL_CEC_STATE_READY = 0x20U, HAL_CEC_STATE_BUSY = 0x24U, HAL_CEC_STATE_BUSY_RX = 0x22U,
HAL_CEC_STATE_BUSY_TX = 0x21U, HAL_CEC_STATE_BUSY_RX_TX = 0x23U, HAL_CEC_STATE_ERROR = 0x60U
}
HAL CEC State structures definition. More...

Enumeration Type Documentation

enum HAL_CEC_StateTypeDef

HAL CEC State structures definition.

Note:
HAL CEC State value is a combination of 2 different substates: gState and RxState.
  • gState contains CEC state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7 (not used) x : Should be set to 0 b6 Error information 0 : No Error 1 : Error b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP initialized. HAL CEC Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (IP busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.
Enumerator:
HAL_CEC_STATE_RESET

Peripheral is not yet Initialized Value is allowed for gState and RxState

HAL_CEC_STATE_READY

Peripheral Initialized and ready for use Value is allowed for gState and RxState

HAL_CEC_STATE_BUSY

an internal process is ongoing Value is allowed for gState only

HAL_CEC_STATE_BUSY_RX

Data Reception process is ongoing Value is allowed for RxState only

HAL_CEC_STATE_BUSY_TX

Data Transmission process is ongoing Value is allowed for gState only

HAL_CEC_STATE_BUSY_RX_TX

an internal process is ongoing Value is allowed for gState only

HAL_CEC_STATE_ERROR

Error Value is allowed for gState only

Definition at line 167 of file stm32h7xx_hal_cec.h.

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STM32H753xx HAL User Manual: CEC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CEC_InitTypeDef Struct Reference
CEC Exported Types

CEC Init Structure definition. More...

#include <stm32h7xx_hal_cec.h>

Data Fields

uint32_t | SignalFreeTime
uint32_t | Tolerance
uint32_t | BRERxStop
uint32_t | BREErrorBitGen
uint32_t | LBPEErrorBitGen
uint32_t | BroadcastMsgNoErrorBitGen
uint32_t | SignalFreeTimeOption
uint32_t | ListenMode
uint16_t | OwnAddress
uint8_t * | RxBuffer

Detailed Description

CEC Init Structure definition.

Definition at line 65 of file stm32h7xx_hal_cec.h.

Field Documentation

uint32_t CEC_InitTypeDef::BREErrorBitGen

Set BREGEN bit CEC Error Bit Generation if Bit Rise Error reported : specifies whether or not an Error-Bit is generated on the CEC line upon Bit Rising Error detection.

  • CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
  • CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set.

Definition at line 81 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::BRERxStop

Set BRESTP bit CEC Reception Stop on Error : specifies whether or not a Bit Rising Error stops the reception.

  • CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
  • CEC_RX_STOP_ON_BRE: reception is stopped.

Definition at line 77 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::BroadcastMsgNoErrorBitGen

Set BRDNOGEN bit CEC Error Bit Generation on Broadcast message : allows to avoid an Error-Bit generation on the CEC line upon an error detected on a broadcast message.

It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:

  • CEC_BROADCASTERROR_ERRORBIT_GENERATION.
    • a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
    • b) LBPE detection: error-bit generation on the CEC line if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
  • CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION. no error-bit generation in case neither a) nor b) are satisfied. Additionally, there is no error-bit generation in case of Short Bit Period Error detection in a broadcast message while LSTN bit is set.

Definition at line 91 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::LBPEErrorBitGen

Set LBPEGEN bit CEC Error Bit Generation if Long Bit Period Error reported : specifies whether or not an Error-Bit is generated on the CEC line upon Long Bit Period Error detection.

  • CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
  • CEC_LBPE_ERRORBIT_GENERATION: error-bit generation.

Definition at line 86 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::ListenMode

Set LSTN bit CEC Listening mode option : specifies device listening mode. It can take two values:

  • CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its own address (OAR). Messages addressed to different destination are ignored. Broadcast messages are always received.
  • CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own address (OAR) with positive acknowledge. Messages addressed to different destination are received, but without interfering with the CEC bus: no acknowledge sent.

Definition at line 111 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint16_t CEC_InitTypeDef::OwnAddress

Own addresses configuration This parameter can be a value of CEC Own Address

Definition at line 121 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint8_t* CEC_InitTypeDef::RxBuffer

CEC Rx buffer pointer

Definition at line 124 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_ChangeRxBuffer(), HAL_CEC_Init(), and HAL_CEC_IRQHandler().

uint32_t CEC_InitTypeDef::SignalFreeTime

Set SFT field, specifies the Signal Free Time. It can be one of CEC Signal Free Time setting parameter and belongs to the set {0,...,7} where 0x0 is the default configuration else means 0.5 + (SignalFreeTime - 1) nominal data bit periods

Definition at line 67 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::SignalFreeTimeOption

Set SFTOP bit CEC Signal Free Time start option : specifies when SFT timer starts.

  • CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
  • CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception.

Definition at line 107 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::Tolerance

Set RXTOL bit, specifies the tolerance accepted on the received waveforms, it can be a value of CEC Receiver Tolerance : it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE

Definition at line 73 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_cec.h
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STM32H753xx HAL User Manual: CEC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CEC_HandleTypeDef Struct Reference
CEC Exported Types

CEC handle Structure definition. More...

#include <stm32h7xx_hal_cec.h>

Data Fields

CEC_TypeDef * | Instance
CEC_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferCount
uint16_t | RxXferSize
HAL_LockTypeDef | Lock
HAL_CEC_StateTypeDef gState
HAL_CEC_StateTypeDef RxState
uint32_t | ErrorCode

Detailed Description

CEC handle Structure definition.

Definition at line 187 of file stm32h7xx_hal_cec.h.

Field Documentation

uint32_t CEC_HandleTypeDef::ErrorCode

For errors handling purposes, copy of ISR register in case error is reported

Definition at line 208 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_GetError(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_SetDeviceAddress(), and HAL_CEC_Transmit_IT().

HAL_CEC_StateTypeDef CEC_HandleTypeDef::gState

CEC state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_CEC_StateTypeDef

Definition at line 201 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_GetState(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_SetDeviceAddress(), and HAL_CEC_Transmit_IT().

CEC_InitTypeDef CEC_HandleTypeDef::Init

CEC communication parameters

Definition at line 191 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_ChangeRxBuffer(), HAL_CEC_Init(), and HAL_CEC_IRQHandler().

CEC_TypeDef* CEC_HandleTypeDef::Instance

CEC registers base address

Definition at line 189 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_SetDeviceAddress(), and HAL_CEC_Transmit_IT().

HAL_LockTypeDef CEC_HandleTypeDef::Lock

Locking object

Definition at line 199 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint8_t* CEC_HandleTypeDef::pTxBuffPtr

Pointer to CEC Tx transfer Buffer

Definition at line 193 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Transmit_IT().

HAL_CEC_StateTypeDef CEC_HandleTypeDef::RxState

CEC state information related to Rx operations. This parameter can be a value of HAL_CEC_StateTypeDef

Definition at line 205 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_GetState(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), and HAL_CEC_SetDeviceAddress().

uint16_t CEC_HandleTypeDef::RxXferSize

CEC Rx Transfer size, 0: header received only

Definition at line 197 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_GetLastReceivedFrameSize(), and HAL_CEC_IRQHandler().

uint16_t CEC_HandleTypeDef::TxXferCount

CEC Tx Transfer Counter

Definition at line 195 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_cec.h
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STM32H753xx HAL User Manual: CEC Error Code

Defines
CEC Error Code
CEC Exported Constants

Defines

#define | HAL_CEC_ERROR_NONE (uint32_t) 0x0000U
#define | HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR
#define | HAL_CEC_ERROR_BRE CEC_ISR_BRE
#define | HAL_CEC_ERROR_SBPE CEC_ISR_SBPE
#define | HAL_CEC_ERROR_LBPE CEC_ISR_LBPE
#define | HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE
#define | HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST
#define | HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR
#define | HAL_CEC_ERROR_TXERR CEC_ISR_TXERR
#define | HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE

Define Documentation

#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST

CEC Arbitration Lost

Definition at line 229 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_BRE CEC_ISR_BRE

CEC Rx Bit Rising Error

Definition at line 225 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE

CEC Rx Long Bit period Error

Definition at line 227 of file stm32h7xx_hal_cec.h.

#define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U

no error

Definition at line 223 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_SetDeviceAddress(), and HAL_CEC_Transmit_IT().

#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE

CEC Rx Missing Acknowledge

Definition at line 228 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR

CEC Rx-Overrun

Definition at line 224 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE

CEC Rx Short Bit period Error

Definition at line 226 of file stm32h7xx_hal_cec.h.

#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE

CEC Tx Missing Acknowledge

Definition at line 232 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR

CEC Tx-Error

Definition at line 231 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR

CEC Tx-Buffer Underrun

Definition at line 230 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

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STM32H753xx HAL User Manual: CEC Signal Free Time setting parameter

Defines
CEC Signal Free Time setting parameter
CEC Exported Constants

Defines

#define | CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
#define | CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
#define | CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
#define | CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
#define | CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
#define | CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
#define | CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
#define | CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)

Define Documentation

#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)

Definition at line 241 of file stm32h7xx_hal_cec.h.

#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)

Definition at line 242 of file stm32h7xx_hal_cec.h.

#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)

Definition at line 243 of file stm32h7xx_hal_cec.h.

#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)

Definition at line 244 of file stm32h7xx_hal_cec.h.

#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)

Definition at line 245 of file stm32h7xx_hal_cec.h.

#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)

Definition at line 246 of file stm32h7xx_hal_cec.h.

#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)

Definition at line 247 of file stm32h7xx_hal_cec.h.

#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U)

Definition at line 240 of file stm32h7xx_hal_cec.h.

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STM32H753xx HAL User Manual: CEC Receiver Tolerance

Defines
CEC Receiver Tolerance
CEC Exported Constants

Defines

#define | CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
#define | CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)

Define Documentation

#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)

Definition at line 256 of file stm32h7xx_hal_cec.h.

#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)

Definition at line 255 of file stm32h7xx_hal_cec.h.

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STM32H753xx HAL User Manual: CEC Reception Stop on Error

Defines
CEC Reception Stop on Error
CEC Exported Constants

Defines

#define | CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
#define | CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)

Define Documentation

#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)

Definition at line 264 of file stm32h7xx_hal_cec.h.

#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)

Definition at line 265 of file stm32h7xx_hal_cec.h.

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STM32H753xx HAL User Manual: CEC Error Bit Generation if Bit Rise Error reported

Defines
CEC Error Bit Generation if Bit Rise Error reported
CEC Exported Constants

Defines

#define | CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define | CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)

Define Documentation

#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)

Definition at line 274 of file stm32h7xx_hal_cec.h.

#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)

Definition at line 273 of file stm32h7xx_hal_cec.h.

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STM32H753xx HAL User Manual: CEC Error Bit Generation if Long Bit Period Error reported

Defines
CEC Error Bit Generation if Long Bit Period Error reported
CEC Exported Constants

Defines

#define | CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define | CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)

Define Documentation

#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)

Definition at line 283 of file stm32h7xx_hal_cec.h.

#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)

Definition at line 282 of file stm32h7xx_hal_cec.h.

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STM32H753xx HAL User Manual: CEC Error Bit Generation on Broadcast message

Defines
CEC Error Bit Generation on Broadcast message
CEC Exported Constants

Defines

#define | CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
#define | CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)

Define Documentation

#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)

Definition at line 291 of file stm32h7xx_hal_cec.h.

#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)

Definition at line 292 of file stm32h7xx_hal_cec.h.

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STM32H753xx HAL User Manual: CEC Signal Free Time start option

Defines
CEC Signal Free Time start option
CEC Exported Constants

Defines

#define | CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
#define | CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)

Define Documentation

#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)

Definition at line 301 of file stm32h7xx_hal_cec.h.

#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)

Definition at line 300 of file stm32h7xx_hal_cec.h.

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STM32H753xx HAL User Manual: CEC Listening mode option

Defines
CEC Listening mode option
CEC Exported Constants

Defines

#define | CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
#define | CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)

Define Documentation

#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)

Definition at line 310 of file stm32h7xx_hal_cec.h.

#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)

Definition at line 309 of file stm32h7xx_hal_cec.h.

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STM32H753xx HAL User Manual: CEC Device Own Address position in CEC CFGR register

Defines
CEC Device Own Address position in CEC CFGR register
CEC Exported Constants

Defines

#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)

Define Documentation

#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)

Definition at line 318 of file stm32h7xx_hal_cec.h.

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STM32H753xx HAL User Manual: CEC Initiator logical address position in message header

Defines
CEC Initiator logical address position in message header
CEC Exported Constants

Defines

#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)

Define Documentation

#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)

Definition at line 326 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Transmit_IT().

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STM32H753xx HAL User Manual: CEC Own Address

Defines
CEC Own Address
CEC Exported Constants

Defines

#define | CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
#define | CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
#define | CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
#define | CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
#define | CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
#define | CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
#define | CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
#define | CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
#define | CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
#define | CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
#define | CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
#define | CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
#define | CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
#define | CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
#define | CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
#define | CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */

Define Documentation

#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */

Definition at line 335 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */

Definition at line 336 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */

Definition at line 345 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */

Definition at line 346 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */

Definition at line 347 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */

Definition at line 348 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */

Definition at line 349 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */

Definition at line 337 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */

Definition at line 338 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */

Definition at line 339 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */

Definition at line 340 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */

Definition at line 341 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */

Definition at line 342 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */

Definition at line 343 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */

Definition at line 344 of file stm32h7xx_hal_cec.h.

#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */

Definition at line 334 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_SetDeviceAddress().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CEC Interrupts definition

Defines
CEC Interrupts definition
CEC Exported Constants

Defines

#define | CEC_IT_TXACKE CEC_IER_TXACKEIE
#define | CEC_IT_TXERR CEC_IER_TXERRIE
#define | CEC_IT_TXUDR CEC_IER_TXUDRIE
#define | CEC_IT_TXEND CEC_IER_TXENDIE
#define | CEC_IT_TXBR CEC_IER_TXBRIE
#define | CEC_IT_ARBLST CEC_IER_ARBLSTIE
#define | CEC_IT_RXACKE CEC_IER_RXACKEIE
#define | CEC_IT_LBPE CEC_IER_LBPEIE
#define | CEC_IT_SBPE CEC_IER_SBPEIE
#define | CEC_IT_BRE CEC_IER_BREIE
#define | CEC_IT_RXOVR CEC_IER_RXOVRIE
#define | CEC_IT_RXEND CEC_IER_RXENDIE
#define | CEC_IT_RXBR CEC_IER_RXBRIE

Define Documentation

#define CEC_IT_ARBLST CEC_IER_ARBLSTIE

Definition at line 362 of file stm32h7xx_hal_cec.h.

#define CEC_IT_BRE CEC_IER_BREIE

Definition at line 366 of file stm32h7xx_hal_cec.h.

#define CEC_IT_LBPE CEC_IER_LBPEIE

Definition at line 364 of file stm32h7xx_hal_cec.h.

#define CEC_IT_RXACKE CEC_IER_RXACKEIE

Definition at line 363 of file stm32h7xx_hal_cec.h.

#define CEC_IT_RXBR CEC_IER_RXBRIE

Definition at line 369 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

#define CEC_IT_RXEND CEC_IER_RXENDIE

Definition at line 368 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

#define CEC_IT_RXOVR CEC_IER_RXOVRIE

Definition at line 367 of file stm32h7xx_hal_cec.h.

#define CEC_IT_SBPE CEC_IER_SBPEIE

Definition at line 365 of file stm32h7xx_hal_cec.h.

#define CEC_IT_TXACKE CEC_IER_TXACKEIE

Definition at line 357 of file stm32h7xx_hal_cec.h.

#define CEC_IT_TXBR CEC_IER_TXBRIE

Definition at line 361 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

#define CEC_IT_TXEND CEC_IER_TXENDIE

Definition at line 360 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

#define CEC_IT_TXERR CEC_IER_TXERRIE

Definition at line 358 of file stm32h7xx_hal_cec.h.

#define CEC_IT_TXUDR CEC_IER_TXUDRIE

Definition at line 359 of file stm32h7xx_hal_cec.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CEC Flags definition

Defines
CEC Flags definition
CEC Exported Constants

Defines

#define | CEC_FLAG_TXACKE CEC_ISR_TXACKE
#define | CEC_FLAG_TXERR CEC_ISR_TXERR
#define | CEC_FLAG_TXUDR CEC_ISR_TXUDR
#define | CEC_FLAG_TXEND CEC_ISR_TXEND
#define | CEC_FLAG_TXBR CEC_ISR_TXBR
#define | CEC_FLAG_ARBLST CEC_ISR_ARBLST
#define | CEC_FLAG_RXACKE CEC_ISR_RXACKE
#define | CEC_FLAG_LBPE CEC_ISR_LBPE
#define | CEC_FLAG_SBPE CEC_ISR_SBPE
#define | CEC_FLAG_BRE CEC_ISR_BRE
#define | CEC_FLAG_RXOVR CEC_ISR_RXOVR
#define | CEC_FLAG_RXEND CEC_ISR_RXEND
#define | CEC_FLAG_RXBR CEC_ISR_RXBR

Define Documentation

#define CEC_FLAG_ARBLST CEC_ISR_ARBLST

Definition at line 382 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define CEC_FLAG_BRE CEC_ISR_BRE

Definition at line 386 of file stm32h7xx_hal_cec.h.

#define CEC_FLAG_LBPE CEC_ISR_LBPE

Definition at line 384 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define CEC_FLAG_RXACKE CEC_ISR_RXACKE

Definition at line 383 of file stm32h7xx_hal_cec.h.

#define CEC_FLAG_RXBR CEC_ISR_RXBR

Definition at line 389 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_IRQHandler().

#define CEC_FLAG_RXEND CEC_ISR_RXEND

Definition at line 388 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_IRQHandler().

#define CEC_FLAG_RXOVR CEC_ISR_RXOVR

Definition at line 387 of file stm32h7xx_hal_cec.h.

#define CEC_FLAG_SBPE CEC_ISR_SBPE

Definition at line 385 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define CEC_FLAG_TXACKE CEC_ISR_TXACKE

Definition at line 377 of file stm32h7xx_hal_cec.h.

#define CEC_FLAG_TXBR CEC_ISR_TXBR

Definition at line 381 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_IRQHandler().

#define CEC_FLAG_TXEND CEC_ISR_TXEND

Definition at line 380 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_IRQHandler().

#define CEC_FLAG_TXERR CEC_ISR_TXERR

Definition at line 378 of file stm32h7xx_hal_cec.h.

#define CEC_FLAG_TXUDR CEC_ISR_TXUDR

Definition at line 379 of file stm32h7xx_hal_cec.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CEC all RX or TX errors flags

Defines
CEC all RX or TX errors flags
CEC Exported Constants

Defines

#define CEC_ISR_ALL_ERROR

Define Documentation

#define CEC_ISR_ALL_ERROR
Value:
((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
                                                  CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)

Definition at line 397 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CEC all RX errors interrupts enabling flag

Defines
CEC all RX errors interrupts enabling flag
CEC Exported Constants

Defines

#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)

Define Documentation

#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)

Definition at line 406 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CEC all TX errors interrupts enabling flag

Defines
CEC all TX errors interrupts enabling flag
CEC Exported Constants

Defines

#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)

Define Documentation

#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)

Definition at line 414 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CEC Exported Macros

Defines
CEC Exported Macros
CEC

Defines

#define | __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__)
Reset CEC handle gstate & RxState.
#define | __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
Checks whether or not the specified CEC interrupt flag is set.
#define | __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
Clears the interrupt or status flag when raised (write at 1)
#define | __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enables the specified CEC interrupt.
#define | __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disables the specified CEC interrupt.
#define | __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
Checks whether or not the specified CEC interrupt is enabled.
#define | __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
Enables the CEC device.
#define | __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
Disables the CEC device.
#define | __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
Set Transmission Start flag.
#define | __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
Set Transmission End flag.
#define | __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
Get Transmission Start flag.
#define | __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
Get Transmission End flag.
#define | __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
Clear OAR register.
#define | __HAL_CEC_SET_OAR(__HANDLE__, __ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
Set OAR register (without resetting previously set address in case of multi-address mode) To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand.

Define Documentation

#define __HAL_CEC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR |= (__FLAG__))

Clears the interrupt or status flag when raised (write at 1)

Parameters:
__HANDLE__,: specifies the CEC Handle.
__FLAG__,: specifies the interrupt/status flag to clear. This parameter can be one of the following values:
  • CEC_FLAG_TXACKE: Tx Missing acknowledge Error
  • CEC_FLAG_TXERR: Tx Error.
  • CEC_FLAG_TXUDR: Tx-Buffer Underrun.
  • CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
  • CEC_FLAG_TXBR: Tx-Byte Request.
  • CEC_FLAG_ARBLST: Arbitration Lost
  • CEC_FLAG_RXACKE: Rx-Missing Acknowledge
  • CEC_FLAG_LBPE: Rx Long period Error
  • CEC_FLAG_SBPE: Rx Short period Error
  • CEC_FLAG_BRE: Rx Bit Rising Error
  • CEC_FLAG_RXOVR: Rx Overrun.
  • CEC_FLAG_RXEND: End Of Reception.
  • CEC_FLAG_RXBR: Rx-Byte Received.
Return values:
none

Definition at line 476 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_IRQHandler().

#define __HAL_CEC_CLEAR_OAR ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)

Clear OAR register.

Parameters:
__HANDLE__,: specifies the CEC Handle.
Return values:
none

Definition at line 582 of file stm32h7xx_hal_cec.h.

#define __HAL_CEC_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)

Disables the CEC device.

Parameters:
__HANDLE__,: specifies the CEC Handle.
Return values:
none

Definition at line 551 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_Init(), and HAL_CEC_SetDeviceAddress().

#define __HAL_CEC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))

Disables the specified CEC interrupt.

Parameters:
__HANDLE__,: specifies the CEC Handle.
__INTERRUPT__,: specifies the CEC interrupt to disable. This parameter can be one of the following values:
  • CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
  • CEC_IT_TXERR: Tx Error IT Enable
  • CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
  • CEC_IT_TXEND: End of transmission IT Enable
  • CEC_IT_TXBR: Tx-Byte Request IT Enable
  • CEC_IT_ARBLST: Arbitration Lost IT Enable
  • CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
  • CEC_IT_LBPE: Rx Long period Error IT Enable
  • CEC_IT_SBPE: Rx Short period Error IT Enable
  • CEC_IT_BRE: Rx Bit Rising Error IT Enable
  • CEC_IT_RXOVR: Rx Overrun IT Enable
  • CEC_IT_RXEND: End Of Reception IT Enable
  • CEC_IT_RXBR: Rx-Byte Received IT Enable
Return values:
none

Definition at line 518 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit().

#define __HAL_CEC_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)

Enables the CEC device.

Parameters:
__HANDLE__,: specifies the CEC Handle.
Return values:
none

Definition at line 545 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init(), and HAL_CEC_SetDeviceAddress().

#define __HAL_CEC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enables the specified CEC interrupt.

Parameters:
__HANDLE__,: specifies the CEC Handle.
__INTERRUPT__,: specifies the CEC interrupt to enable. This parameter can be one of the following values:
  • CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
  • CEC_IT_TXERR: Tx Error IT Enable
  • CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
  • CEC_IT_TXEND: End of transmission IT Enable
  • CEC_IT_TXBR: Tx-Byte Request IT Enable
  • CEC_IT_ARBLST: Arbitration Lost IT Enable
  • CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
  • CEC_IT_LBPE: Rx Long period Error IT Enable
  • CEC_IT_SBPE: Rx Short period Error IT Enable
  • CEC_IT_BRE: Rx Bit Rising Error IT Enable
  • CEC_IT_RXOVR: Rx Overrun IT Enable
  • CEC_IT_RXEND: End Of Reception IT Enable
  • CEC_IT_RXBR: Rx-Byte Received IT Enable
Return values:
none

Definition at line 497 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define __HAL_CEC_FIRST_BYTE_TX_SET ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)

Set Transmission Start flag.

Parameters:
__HANDLE__,: specifies the CEC Handle.
Return values:
none

Definition at line 557 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Transmit_IT().

#define __HAL_CEC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR & (__FLAG__))

Checks whether or not the specified CEC interrupt flag is set.

Parameters:
__HANDLE__,: specifies the CEC Handle.
__FLAG__,: specifies the flag to check.
  • CEC_FLAG_TXACKE: Tx Missing acknowledge Error
  • CEC_FLAG_TXERR: Tx Error.
  • CEC_FLAG_TXUDR: Tx-Buffer Underrun.
  • CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
  • CEC_FLAG_TXBR: Tx-Byte Request.
  • CEC_FLAG_ARBLST: Arbitration Lost
  • CEC_FLAG_RXACKE: Rx-Missing Acknowledge
  • CEC_FLAG_LBPE: Rx Long period Error
  • CEC_FLAG_SBPE: Rx Short period Error
  • CEC_FLAG_BRE: Rx Bit Rising Error
  • CEC_FLAG_RXOVR: Rx Overrun.
  • CEC_FLAG_RXEND: End Of Reception.
  • CEC_FLAG_RXBR: Rx-Byte Received.
Return values:
ITStatus

Definition at line 455 of file stm32h7xx_hal_cec.h.

#define __HAL_CEC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER & (__INTERRUPT__))

Checks whether or not the specified CEC interrupt is enabled.

Parameters:
__HANDLE__,: specifies the CEC Handle.
__INTERRUPT__,: specifies the CEC interrupt to check. This parameter can be one of the following values:
  • CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
  • CEC_IT_TXERR: Tx Error IT Enable
  • CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
  • CEC_IT_TXEND: End of transmission IT Enable
  • CEC_IT_TXBR: Tx-Byte Request IT Enable
  • CEC_IT_ARBLST: Arbitration Lost IT Enable
  • CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
  • CEC_IT_LBPE: Rx Long period Error IT Enable
  • CEC_IT_SBPE: Rx Short period Error IT Enable
  • CEC_IT_BRE: Rx Bit Rising Error IT Enable
  • CEC_IT_RXOVR: Rx Overrun IT Enable
  • CEC_IT_RXEND: End Of Reception IT Enable
  • CEC_IT_RXBR: Rx-Byte Received IT Enable
Return values:
FlagStatus

Definition at line 539 of file stm32h7xx_hal_cec.h.

#define __HAL_CEC_GET_TRANSMISSION_END_FLAG ( __HANDLE__ ) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)

Get Transmission End flag.

Parameters:
__HANDLE__,: specifies the CEC Handle.
Return values:
FlagStatus

Definition at line 576 of file stm32h7xx_hal_cec.h.

#define __HAL_CEC_GET_TRANSMISSION_START_FLAG ( __HANDLE__ ) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)

Get Transmission Start flag.

Parameters:
__HANDLE__,: specifies the CEC Handle.
Return values:
FlagStatus

Definition at line 570 of file stm32h7xx_hal_cec.h.

#define __HAL_CEC_LAST_BYTE_TX_SET ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)

Set Transmission End flag.

Parameters:
__HANDLE__,: specifies the CEC Handle.
Return values:
none If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.

Definition at line 564 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Transmit_IT().

#define __HAL_CEC_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_CEC_STATE_RESET;     \
                                                       (__HANDLE__)->RxState = HAL_CEC_STATE_RESET;    \
                                                     } while(0)

Reset CEC handle gstate & RxState.

Parameters:
__HANDLE__,: CEC handle.
Return values:
None

Definition at line 432 of file stm32h7xx_hal_cec.h.

#define __HAL_CEC_SET_OAR | ( | __HANDLE__,
 |  | __ADDRESS__
 | ) | SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)

Set OAR register (without resetting previously set address in case of multi-address mode) To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand.

Parameters:
__HANDLE__,: specifies the CEC Handle.
__ADDRESS__,: Own Address value (CEC logical address is identified by bit position)
Return values:
none

Definition at line 590 of file stm32h7xx_hal_cec.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CEC Private Types

CEC Private Types
CEC
Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CEC Private Variables

CEC Private Variables
CEC
Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CEC Private Macros

Defines
CEC Private Macros
CEC

Defines

#define | IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
#define | IS_CEC_TOLERANCE(__RXTOL__)
#define | IS_CEC_BRERXSTOP(__BRERXSTOP__)
#define | IS_CEC_BREERRORBITGEN(__ERRORBITGEN__)
#define | IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__)
#define | IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__)
#define | IS_CEC_SFTOP(__SFTOP__)
#define | IS_CEC_LISTENING_MODE(__MODE__)
#define | IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10)
Check CEC message size.
#define | IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFF)
Check CEC device Own Address Register (OAR) setting.
#define | IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
Check CEC initiator or destination logical address setting.

Define Documentation

#define IS_CEC_ADDRESS ( __ADDRESS__ ) ((__ADDRESS__) <= 0xF)

Check CEC initiator or destination logical address setting.

Initiator and destination addresses are coded over 4 bits.

Parameters:
__ADDRESS__,: CEC initiator or logical address.
Return values:
Test result (TRUE or FALSE).

Definition at line 719 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Transmit_IT().

#define IS_CEC_BREERRORBITGEN ( __ERRORBITGEN__ )
Value:
(((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
                                                ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))

Definition at line 683 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_BRERXSTOP ( __BRERXSTOP__ )
Value:
(((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
                                           ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))

Definition at line 680 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ( __ERRORBITGEN__ )
Value:
(((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
                                                                       ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))

Definition at line 689 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_LBPEERRORBITGEN ( __ERRORBITGEN__ )
Value:
(((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
                                                 ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))

Definition at line 686 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_LISTENING_MODE ( __MODE__ )
Value:
(((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
                                             ((__MODE__) == CEC_FULL_LISTENING_MODE))

Definition at line 695 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_MSGSIZE ( __SIZE__ ) ((__SIZE__) <= 0x10)

Check CEC message size.

The message size is the payload size: without counting the header, it varies from 0 byte (ping operation, one header only, no payload) to 15 bytes (1 opcode and up to 14 operands following the header).

Parameters:
__SIZE__,: CEC message size.
Return values:
Test result (TRUE or FALSE).

Definition at line 705 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Transmit_IT().

#define IS_CEC_OWN_ADDRESS ( __ADDRESS__ ) ((__ADDRESS__) <= 0x7FFF)

Check CEC device Own Address Register (OAR) setting.

OAR address is written in a 15-bit field within CEC_CFGR register.

Parameters:
__ADDRESS__,: CEC own address.
Return values:
Test result (TRUE or FALSE).

Definition at line 712 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init(), and HAL_CEC_SetDeviceAddress().

#define IS_CEC_SFTOP ( __SFTOP__ )
Value:
(((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
                                          ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))

Definition at line 692 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_SIGNALFREETIME ( __SFT__ ) ((__SFT__) <= CEC_CFGR_SFT)

Definition at line 675 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_TOLERANCE ( __RXTOL__ )
Value:
(((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
                                            ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))

Definition at line 677 of file stm32h7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
COMP Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Init (COMP_HandleTypeDef *hcomp)
Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP peripheral.
__weak void | HAL_COMP_MspInit (COMP_HandleTypeDef *hcomp)
Initialize the COMP MSP.
__weak void | HAL_COMP_MspDeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP MSP.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions to initialize and de-initialize comparators

Function Documentation

HAL_StatusTypeDef HAL_COMP_DeInit ( COMP_HandleTypeDef * hcomp )

DeInitialize the COMP peripheral.

Note:
Deinitialization cannot be performed if the COMP configuration is locked. To unlock the configuration, perform a system reset.
Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 394 of file stm32h7xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, HAL_COMP_MspDeInit(), HAL_COMP_STATE_RESET, COMP_HandleTypeDef::Instance, and COMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_COMP_Init ( COMP_HandleTypeDef * hcomp )

Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.

Note:
If the selected comparator is locked, initialization can't be performed. To unlock the configuration, perform a system reset.
Parameters:
hcomp,: COMP handle
Return values:
HAL status

Definition at line 224 of file stm32h7xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, COMP_InitTypeDef::BlankingSrce, COMP_DELAY_VOLTAGE_SCALER_STAB_US, COMP_EXTI_EVENT, COMP_EXTI_FALLING, COMP_EXTI_IT, COMP_EXTI_RISING, COMP_GET_EXTI_LINE, COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON, HAL_COMP_MspInit(), HAL_COMP_STATE_READY, HAL_COMP_STATE_RESET, COMP_InitTypeDef::Hysteresis, COMP_HandleTypeDef::Init, COMP_HandleTypeDef::Instance, COMP_InitTypeDef::InvertingInput, IS_COMP_BLANKINGSRCE, IS_COMP_HYSTERESIS, IS_COMP_INPUT_MINUS, IS_COMP_INPUT_PLUS, IS_COMP_OUTPUTPOL, IS_COMP_POWERMODE, IS_COMP_TRIGGERMODE, IS_COMP_WINDOWMODE, COMP_HandleTypeDef::Lock, COMP_InitTypeDef::Mode, COMP_InitTypeDef::NonInvertingInput, COMP_InitTypeDef::OutputPol, COMP_HandleTypeDef::State, COMP_InitTypeDef::TriggerMode, and COMP_InitTypeDef::WindowMode.

void HAL_COMP_MspDeInit ( COMP_HandleTypeDef * hcomp )

DeInitialize the COMP MSP.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 443 of file stm32h7xx_hal_comp.c.

Referenced by HAL_COMP_DeInit().

void HAL_COMP_MspInit ( COMP_HandleTypeDef * hcomp )

Initialize the COMP MSP.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 429 of file stm32h7xx_hal_comp.c.

Referenced by HAL_COMP_Init().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Start-Stop operation functions

Functions
Start-Stop operation functions
COMP Exported Functions

Start-Stop operation functions. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Start (COMP_HandleTypeDef *hcomp)
Start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop (COMP_HandleTypeDef *hcomp)
Stop the comparator.
HAL_StatusTypeDef | HAL_COMP_Start_IT (COMP_HandleTypeDef *hcomp)
Enable the interrupt and start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop_IT (COMP_HandleTypeDef *hcomp)
Disable the interrupt and Stop the comparator.
void | HAL_COMP_IRQHandler (COMP_HandleTypeDef *hcomp)
Comparator IRQ Handler.

Detailed Description

Start-Stop operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start a Comparator instance without interrupt.
      (+) Stop a Comparator instance without interrupt.
      (+) Start a Comparator instance with interrupt generation.
      (+) Stop a Comparator instance with interrupt generation.

Function Documentation

void HAL_COMP_IRQHandler ( COMP_HandleTypeDef * hcomp )

Comparator IRQ Handler.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 636 of file stm32h7xx_hal_comp.c.

References __HAL_COMP_CLEAR_C1IFLAG, __HAL_COMP_CLEAR_C2IFLAG, __HAL_COMP_DISABLE_IT, __HAL_COMP_GET_FLAG, __HAL_COMP_GET_IT_SOURCE, COMP_EXTI_LINE_COMP1, COMP_EXTI_LINE_COMP2, COMP_FLAG_C1I, COMP_FLAG_C2I, COMP_GET_EXTI_LINE, COMP_IT_EN, HAL_COMP_STATE_READY, HAL_COMP_TriggerCallback(), COMP_HandleTypeDef::Instance, and COMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_COMP_Start ( COMP_HandleTypeDef * hcomp )

Start the comparator.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 478 of file stm32h7xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, COMP_DELAY_STARTUP_US, HAL_COMP_STATE_BUSY, HAL_COMP_STATE_READY, COMP_HandleTypeDef::Instance, and COMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_COMP_Start_IT ( COMP_HandleTypeDef * hcomp )

Enable the interrupt and start the comparator.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 565 of file stm32h7xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, COMP_DELAY_STARTUP_US, HAL_COMP_STATE_BUSY, HAL_COMP_STATE_READY, COMP_HandleTypeDef::Instance, and COMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_COMP_Stop ( COMP_HandleTypeDef * hcomp )

Stop the comparator.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 527 of file stm32h7xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, HAL_COMP_STATE_BUSY, HAL_COMP_STATE_READY, COMP_HandleTypeDef::Instance, and COMP_HandleTypeDef::State.

Referenced by HAL_COMP_Stop_IT().

HAL_StatusTypeDef HAL_COMP_Stop_IT ( COMP_HandleTypeDef * hcomp )

Disable the interrupt and Stop the comparator.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 616 of file stm32h7xx_hal_comp.c.

References COMP_GET_EXTI_LINE, HAL_COMP_Stop(), and COMP_HandleTypeDef::Instance.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
COMP Exported Functions

Management functions. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Lock (COMP_HandleTypeDef *hcomp)
Lock the selected comparator configuration.
uint32_t | HAL_COMP_GetOutputLevel (COMP_HandleTypeDef *hcomp)
Return the output level (high or low) of the selected comparator.
__weak void | HAL_COMP_TriggerCallback (COMP_HandleTypeDef *hcomp)
Comparator callback.

Detailed Description

Management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the comparators.

Function Documentation

uint32_t HAL_COMP_GetOutputLevel ( COMP_HandleTypeDef * hcomp )

Return the output level (high or low) of the selected comparator.

Note:
The output level depends on the selected polarity. If the polarity is not inverted:
  • Comparator output is low when the input plus is at a lower voltage than the input minus
  • Comparator output is high when the input plus is at a higher voltage than the input minus If the polarity is inverted:
  • Comparator output is high when the input plus is at a lower voltage than the input minus
  • Comparator output is low when the input plus is at a higher voltage than the input minus
Parameters:
hcomp COMP handle
Return values:
Returns the selected comparator output level:
  • COMP_OUTPUT_LEVEL_LOW
  • COMP_OUTPUT_LEVEL_HIGH

Definition at line 769 of file stm32h7xx_hal_comp.c.

References assert_param, and COMP_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_COMP_Lock ( COMP_HandleTypeDef * hcomp )

Lock the selected comparator configuration.

Note:
A system reset is required to unlock the comparator configuration.
Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 724 of file stm32h7xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, __HAL_COMP_LOCK, assert_param, COMP_STATE_BITFIELD_LOCK, COMP_HandleTypeDef::Instance, and COMP_HandleTypeDef::State.

void HAL_COMP_TriggerCallback ( COMP_HandleTypeDef * hcomp )

Comparator callback.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 789 of file stm32h7xx_hal_comp.c.

Referenced by HAL_COMP_IRQHandler().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
COMP Exported Functions

Peripheral State functions. More...

Functions

HAL_COMP_StateTypeDef HAL_COMP_GetState (COMP_HandleTypeDef *hcomp)
Return the COMP handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral.

Function Documentation

HAL_COMP_StateTypeDef HAL_COMP_GetState ( COMP_HandleTypeDef * hcomp )

Return the COMP handle state.

Parameters:
hcomp COMP handle
Return values:
HAL state

Definition at line 822 of file stm32h7xx_hal_comp.c.

References assert_param, HAL_COMP_STATE_RESET, COMP_HandleTypeDef::Instance, and COMP_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: COMP Exported Types

Data Structures | Defines | Enumerations
COMP Exported Types
COMP

Data Structures

struct | COMP_InitTypeDef
COMP Init structure definition. More...
struct | COMP_HandleTypeDef
COMP Handle Structure definition. More...

Defines

#define | COMP_STATE_BITFIELD_LOCK ((uint32_t)0x10)
HAL COMP state machine: HAL COMP states definition.

Enumerations

enum HAL_COMP_StateTypeDef {
HAL_COMP_STATE_RESET = 0x00, HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), HAL_COMP_STATE_READY = 0x01, HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK),
HAL_COMP_STATE_BUSY = 0x02, HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)
}

Define Documentation

#define COMP_STATE_BITFIELD_LOCK ((uint32_t)0x10)

HAL COMP state machine: HAL COMP states definition.

Definition at line 101 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Lock().

Enumeration Type Documentation

enum HAL_COMP_StateTypeDef
Enumerator:
HAL_COMP_STATE_RESET

COMP not yet initialized

HAL_COMP_STATE_RESET_LOCKED

COMP not yet initialized and configuration is locked

HAL_COMP_STATE_READY

COMP initialized and ready for use

HAL_COMP_STATE_READY_LOCKED

COMP initialized but configuration is locked

HAL_COMP_STATE_BUSY

COMP is running

HAL_COMP_STATE_BUSY_LOCKED

COMP is running and configuration is locked

Definition at line 102 of file stm32h7xx_hal_comp.h.

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STM32H753xx HAL User Manual: COMP_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
COMP_InitTypeDef Struct Reference
COMP Exported Types

COMP Init structure definition. More...

#include <stm32h7xx_hal_comp.h>

Data Fields

uint32_t | WindowMode
uint32_t | Mode
uint32_t | NonInvertingInput
uint32_t | InvertingInput
uint32_t | Hysteresis
uint32_t | OutputPol
uint32_t | BlankingSrce
uint32_t | TriggerMode

Detailed Description

COMP Init structure definition.

Definition at line 65 of file stm32h7xx_hal_comp.h.

Field Documentation

uint32_t COMP_InitTypeDef::BlankingSrce

Set comparator blanking source. This parameter can be a value of COMP Blanking Source

Definition at line 90 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::Hysteresis

Set comparator hysteresis mode of the input minus. This parameter can be a value of COMP hysteresis

Definition at line 84 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::InvertingInput

Set comparator input minus (inverting input). This parameter can be a value of COMP input minus (inverting input)

Definition at line 81 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::Mode

Set comparator operating mode to adjust power and speed. Note: For the characteritics of comparator power modes (propagation delay and power consumption), refer to device datasheet. This parameter can be a value of COMP power mode

Definition at line 73 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::NonInvertingInput

Set comparator input plus (non-inverting input). This parameter can be a value of COMP input plus (non-inverting input)

Definition at line 78 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::OutputPol

Set comparator output polarity. This parameter can be a value of COMP Output Polarity

Definition at line 87 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::TriggerMode

Set the comparator output triggering External Interrupt Line (EXTI). This parameter can be a value of COMP output to EXTI

Definition at line 93 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::WindowMode

Set window mode of a pair of comparators instances (2 consecutive instances odd and even COMP<x> and COMP<x+1>). Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode. This parameter can be a value of COMP Window Mode

Definition at line 68 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_comp.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: COMP_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
COMP_HandleTypeDef Struct Reference
COMP Exported Types

COMP Handle Structure definition. More...

#include <stm32h7xx_hal_comp.h>

Data Fields

COMP_TypeDef * | Instance
COMP_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_COMP_StateTypeDef | State

Detailed Description

COMP Handle Structure definition.

Definition at line 115 of file stm32h7xx_hal_comp.h.

Field Documentation

COMP_InitTypeDef COMP_HandleTypeDef::Init

COMP required parameters

Definition at line 118 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

COMP_TypeDef* COMP_HandleTypeDef::Instance

Register base address

Definition at line 117 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_GetOutputLevel(), HAL_COMP_GetState(), HAL_COMP_Init(), HAL_COMP_IRQHandler(), HAL_COMP_Lock(), HAL_COMP_Start(), HAL_COMP_Start_IT(), HAL_COMP_Stop(), and HAL_COMP_Stop_IT().

HAL_LockTypeDef COMP_HandleTypeDef::Lock

Locking object

Definition at line 119 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

__IO HAL_COMP_StateTypeDef COMP_HandleTypeDef::State

COMP communication state

Definition at line 120 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_GetState(), HAL_COMP_Init(), HAL_COMP_IRQHandler(), HAL_COMP_Lock(), HAL_COMP_Start(), HAL_COMP_Start_IT(), and HAL_COMP_Stop().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_comp.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: COMP Window Mode

Defines
COMP Window Mode
COMP Exported Constants

Defines

#define | COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000)
#define | COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CFGRx_WINMODE)

Define Documentation

#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CFGRx_WINMODE)

Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible).

Definition at line 136 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000)

Window mode disable: Comparators instances pair COMP1 and COMP2 are independent

Definition at line 135 of file stm32h7xx_hal_comp.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: COMP power mode

Defines
COMP power mode
COMP Exported Constants

Defines

#define | COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000)
#define | COMP_POWERMODE_MEDIUMSPEED (COMP_CFGRx_PWRMODE_0)
#define | COMP_POWERMODE_ULTRALOWPOWER (COMP_CFGRx_PWRMODE)

Define Documentation

#define COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000)

High Speed

Definition at line 148 of file stm32h7xx_hal_comp.h.

#define COMP_POWERMODE_MEDIUMSPEED (COMP_CFGRx_PWRMODE_0)

Medium Speed

Definition at line 149 of file stm32h7xx_hal_comp.h.

#define COMP_POWERMODE_ULTRALOWPOWER (COMP_CFGRx_PWRMODE)

Ultra-low power mode

Definition at line 150 of file stm32h7xx_hal_comp.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: COMP input plus (non-inverting input)

Defines
COMP input plus (non-inverting input)
COMP Exported Constants

Defines

#define | COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000)
#define | COMP_INPUT_PLUS_IO2 (COMP_CFGRx_INPSEL)

Define Documentation

#define COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000)

Comparator input plus connected to IO1 (pin PB0 for COMP1, pin PE9 for COMP2)

Definition at line 158 of file stm32h7xx_hal_comp.h.

#define COMP_INPUT_PLUS_IO2 (COMP_CFGRx_INPSEL)

Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PE11 for COMP2)

Definition at line 159 of file stm32h7xx_hal_comp.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: COMP input minus (inverting input)

Defines
COMP input minus (inverting input)
COMP Exported Constants

Defines

#define | COMP_INPUT_MINUS_1_4VREFINT ( COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)
#define | COMP_INPUT_MINUS_1_2VREFINT ( COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)
#define | COMP_INPUT_MINUS_3_4VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)
#define | COMP_INPUT_MINUS_VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN )
#define | COMP_INPUT_MINUS_DAC1_CH1 (COMP_CFGRx_INMSEL_2 )
#define | COMP_INPUT_MINUS_DAC1_CH2 (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_0)
#define | COMP_INPUT_MINUS_IO1 (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 )
#define | COMP_INPUT_MINUS_IO2 (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0)

Define Documentation

#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)

Comparator input minus connected to 1/2 VrefInt

Definition at line 168 of file stm32h7xx_hal_comp.h.

#define COMP_INPUT_MINUS_1_4VREFINT ( COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)

Comparator input minus connected to 1/4 VrefInt

Definition at line 167 of file stm32h7xx_hal_comp.h.

#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)

Comparator input minus connected to 3/4 VrefInt

Definition at line 169 of file stm32h7xx_hal_comp.h.

#define COMP_INPUT_MINUS_DAC1_CH1 (COMP_CFGRx_INMSEL_2 )

Comparator input minus connected to DAC1 channel 1 (DAC_OUT1)

Definition at line 171 of file stm32h7xx_hal_comp.h.

#define COMP_INPUT_MINUS_DAC1_CH2 (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_0)

Comparator input minus connected to DAC1 channel 2 (DAC_OUT2)

Definition at line 172 of file stm32h7xx_hal_comp.h.

#define COMP_INPUT_MINUS_IO1 (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 )

Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PE10 for COMP2)

Definition at line 173 of file stm32h7xx_hal_comp.h.

#define COMP_INPUT_MINUS_IO2 (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0)

Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PE7 for COMP2)

Definition at line 174 of file stm32h7xx_hal_comp.h.

#define COMP_INPUT_MINUS_VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN )

Comparator input minus connected to VrefInt

Definition at line 170 of file stm32h7xx_hal_comp.h.

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STM32H753xx HAL User Manual: COMP hysteresis

Defines
COMP hysteresis
COMP Exported Constants

Defines

#define | COMP_HYSTERESIS_NONE ((uint32_t)0x00000000)
#define | COMP_HYSTERESIS_LOW (COMP_CFGRx_HYST_0)
#define | COMP_HYSTERESIS_MEDIUM (COMP_CFGRx_HYST_1)
#define | COMP_HYSTERESIS_HIGH (COMP_CFGRx_HYST)

Define Documentation

#define COMP_HYSTERESIS_HIGH (COMP_CFGRx_HYST)

Hysteresis level high

Definition at line 185 of file stm32h7xx_hal_comp.h.

#define COMP_HYSTERESIS_LOW (COMP_CFGRx_HYST_0)

Hysteresis level low

Definition at line 183 of file stm32h7xx_hal_comp.h.

#define COMP_HYSTERESIS_MEDIUM (COMP_CFGRx_HYST_1)

Hysteresis level medium

Definition at line 184 of file stm32h7xx_hal_comp.h.

#define COMP_HYSTERESIS_NONE ((uint32_t)0x00000000)

No hysteresis

Definition at line 182 of file stm32h7xx_hal_comp.h.

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STM32H753xx HAL User Manual: COMP Output Polarity

Defines
COMP Output Polarity
COMP Exported Constants

Defines

#define | COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000)
#define | COMP_OUTPUTPOL_INVERTED (COMP_CFGRx_POLARITY)

Define Documentation

#define COMP_OUTPUTPOL_INVERTED (COMP_CFGRx_POLARITY)

COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus)

Definition at line 194 of file stm32h7xx_hal_comp.h.

#define COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000)

COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus)

Definition at line 193 of file stm32h7xx_hal_comp.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: COMP Blanking Source

Defines
COMP Blanking Source
COMP Exported Constants

Defines

#define | COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000)
#define | COMP_BLANKINGSRC_TIM1_OC5 (COMP_CFGRx_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM2_OC3 (COMP_CFGRx_BLANKING_1)
#define | COMP_BLANKINGSRC_TIM3_OC3 (COMP_CFGRx_BLANKING_0 |COMP_CFGRx_BLANKING_1)
#define | COMP_BLANKINGSRC_TIM3_OC4 (COMP_CFGRx_BLANKING_2)
#define | COMP_BLANKINGSRC_TIM8_OC5 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM15_OC1 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_1)

Define Documentation

#define COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000)

No blanking source

Definition at line 204 of file stm32h7xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM15_OC1 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_1)

TIM15 OC1 selected as blanking source for comparator

Definition at line 210 of file stm32h7xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM1_OC5 (COMP_CFGRx_BLANKING_0)

TIM1 OC5 selected as blanking source for comparator

Definition at line 205 of file stm32h7xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM2_OC3 (COMP_CFGRx_BLANKING_1)

TIM2 OC3 selected as blanking source for comparator

Definition at line 206 of file stm32h7xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM3_OC3 (COMP_CFGRx_BLANKING_0 |COMP_CFGRx_BLANKING_1)

TIM3 OC3 selected as blanking source for compartor

Definition at line 207 of file stm32h7xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM3_OC4 (COMP_CFGRx_BLANKING_2)

TIM3 OC4 selected as blanking source for comparator

Definition at line 208 of file stm32h7xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM8_OC5 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_0)

TIM8 OC5 selected as blanking source for comparator

Definition at line 209 of file stm32h7xx_hal_comp.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: COMP Output Level

Defines
COMP Output Level
COMP Exported Constants

Defines

#define | COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000)
#define | COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001)

Define Documentation

#define COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001)

Definition at line 231 of file stm32h7xx_hal_comp.h.

#define COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000)

Definition at line 228 of file stm32h7xx_hal_comp.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: COMP output to EXTI

Defines
COMP output to EXTI
COMP Exported Constants

Defines

#define | COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000)
#define | COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)

Define Documentation

#define COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event only (without interruption), on falling edge

Definition at line 245 of file stm32h7xx_hal_comp.h.

#define COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING)

Comparator output triggering External Interrupt Line event only (without interruption), on rising edge

Definition at line 244 of file stm32h7xx_hal_comp.h.

#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges

Definition at line 246 of file stm32h7xx_hal_comp.h.

#define COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event with interruption, on falling edge

Definition at line 242 of file stm32h7xx_hal_comp.h.

#define COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING)

Comparator output triggering External Interrupt Line event with interruption, on rising edge

Definition at line 241 of file stm32h7xx_hal_comp.h.

#define COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges

Definition at line 243 of file stm32h7xx_hal_comp.h.

#define COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000)

Comparator output triggering no External Interrupt Line

Definition at line 240 of file stm32h7xx_hal_comp.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: COMP Flag

Defines
COMP Flag
COMP Exported Constants

Defines

#define | COMP_FLAG_C1I COMP_SR_C1IF
#define | COMP_FLAG_C2I COMP_SR_C2IF
#define | COMP_FLAG_LOCK COMP_CFGRx_LOCK

Define Documentation

#define COMP_FLAG_C1I COMP_SR_C1IF

Comparator 1 Interrupt Flag

Definition at line 255 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define COMP_FLAG_C2I COMP_SR_C2IF

Comparator 2 Interrupt Flag

Definition at line 256 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define COMP_FLAG_LOCK COMP_CFGRx_LOCK

Lock flag

Definition at line 257 of file stm32h7xx_hal_comp.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: COMP Interruption Clear Flags

Defines
COMP Interruption Clear Flags
COMP Exported Constants

Defines

#define | COMP_CLEAR_C1IF COMP_ICFR_C1IF
#define | COMP_CLEAR_C2IF COMP_ICFR_C2IF

Define Documentation

#define COMP_CLEAR_C1IF COMP_ICFR_C1IF

Clear Comparator 1 Interrupt Flag

Definition at line 264 of file stm32h7xx_hal_comp.h.

#define COMP_CLEAR_C2IF COMP_ICFR_C2IF

Clear Comparator 2 Interrupt Flag

Definition at line 265 of file stm32h7xx_hal_comp.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: COMP Interrupts Definitions

Defines
COMP Interrupts Definitions
COMP Exported Constants

Defines

#define COMP_IT_EN COMP_CFGRx_ITEN

Define Documentation

#define COMP_IT_EN COMP_CFGRx_ITEN

Definition at line 272 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: COMP Handle Management

Defines
COMP Handle Management
COMP Exported Macros

Defines

#define | __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
Reset COMP handle state.
#define | __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)
Enable the specified comparator.
#define | __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)
Disable the specified comparator.
#define | __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK)
Lock the specified comparator configuration.
#define | __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK) == COMP_CFGRx_LOCK)
Check whether the specified comparator is locked.

Define Documentation

#define __HAL_COMP_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)

Disable the specified comparator.

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 309 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)

Enable the specified comparator.

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 302 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_IS_LOCKED ( __HANDLE__ ) (READ_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK) == COMP_CFGRx_LOCK)

Check whether the specified comparator is locked.

Parameters:
__HANDLE__ COMP handle
Return values:
Value 0 if COMP instance is not locked, value 1 if COMP instance is locked

Definition at line 327 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_Init(), HAL_COMP_Lock(), HAL_COMP_Start(), HAL_COMP_Start_IT(), and HAL_COMP_Stop().

#define __HAL_COMP_LOCK ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK)

Lock the specified comparator configuration.

Note:
Using this macro induce HAL COMP handle state machine being no more in line with COMP instance state. To keep HAL COMP handle state machine updated, it is recommended to use function "HAL_COMP_Lock')".
Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 320 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Lock().

#define __HAL_COMP_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)

Reset COMP handle state.

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 295 of file stm32h7xx_hal_comp.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: COMP external interrupt line management

Defines
COMP external interrupt line management
COMP Exported Macros

Defines

#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI Line in event mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI Line in event mode.
#define | __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)
Check whether the COMP1 EXTI line flag is set or not.
#define | __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)
Clear the COMP1 EXTI flag.
#define | __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1)
Generate a software interrupt on the COMP1 EXTI line.
#define | __HAL_COMP_COMP1_EXTID3_ENABLE_EVENT() SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 D3 EXTI Line in event mode.
#define | __HAL_COMP_COMP1_EXTID3_DISABLE_EVENT() CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 D3 EXTI Line in event mode.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI Line in event mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI Line in event mode.
#define | __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)
Check whether the COMP2 EXTI line flag is set or not.
#define | __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)
Clear the the COMP2 EXTI flag.
#define | __HAL_COMP_COMP2_EXTID3_ENABLE_EVENT() SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 D3 EXTI Line in event mode.
#define | __HAL_COMP_COMP2_EXTID3_DISABLE_EVENT() CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 D3 EXTI Line in event mode.
#define | __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2)
Generate a software interrupt on the COMP2 EXTI line.
#define | __HAL_COMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CFGR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified COMP interrupt source is enabled or disabled.
#define | __HAL_COMP_GET_FLAG(__FLAG__) ((COMP12->SR & (__FLAG__)) == (__FLAG__))
Checks whether the specified COMP flag is set or not.
#define | __HAL_COMP_CLEAR_FLAG(__FLAG__) (COMP12->ICFR = (__FLAG__))
Clears the specified COMP pending flag.
#define | __HAL_COMP_CLEAR_C1IFLAG() __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C1IF)
Clear the COMP C1I flag.
#define | __HAL_COMP_CLEAR_C2IFLAG() __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C2IF)
Clear the COMP C2I flag.
#define | __HAL_COMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ( ((__HANDLE__)->Instance->CFGR) |= (__INTERRUPT__) )
Enable the specified COMP interrupt.
#define | __HAL_COMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFGR) &= ~(__INTERRUPT__))
Disable the specified COMP interrupt.

Define Documentation

#define __HAL_COMP_CLEAR_C1IFLAG ( ) __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C1IF)

Clear the COMP C1I flag.

Return values:
None

Definition at line 564 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define __HAL_COMP_CLEAR_C2IFLAG ( ) __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C2IF)

Clear the COMP C2I flag.

Return values:
None

Definition at line 569 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define __HAL_COMP_CLEAR_FLAG ( __FLAG__ ) (COMP12->ICFR = (__FLAG__))

Clears the specified COMP pending flag.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be any combination of the following values:
  • COMP_CLEAR_C1IF : Clear Comparator 1 Interrupt Flag
  • COMP_CLEAR_C2IF : Clear Comparator 2 Interrupt Flag
Return values:
None

Definition at line 559 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG ( ) WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)

Clear the COMP1 EXTI flag.

Return values:
None

Definition at line 416 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI Line in event mode.

Return values:
None

Definition at line 405 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line falling edge trigger.

Return values:
None

Definition at line 360 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line in interrupt mode.

Return values:
None

Definition at line 393 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line rising edge trigger.

Return values:
None

Definition at line 348 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
                                                               __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
                                                             } while(0)

Disable the COMP1 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 377 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI Line in event mode.

Return values:
None

Definition at line 399 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line falling edge trigger.

Return values:
None

Definition at line 354 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_IT ( ) SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line in interrupt mode.

Return values:
None

Definition at line 387 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line rising edge trigger.

Return values:
None

Definition at line 341 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
                                                               __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
                                                             } while(0)

Enable the COMP1 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 367 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1)

Generate a software interrupt on the COMP1 EXTI line.

Return values:
None

Definition at line 422 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_GET_FLAG ( ) READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)

Check whether the COMP1 EXTI line flag is set or not.

Return values:
RESET or SET

Definition at line 411 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTID3_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)

Disable the COMP1 D3 EXTI Line in event mode.

Return values:
None

Definition at line 434 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTID3_ENABLE_EVENT ( ) SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)

Enable the COMP1 D3 EXTI Line in event mode.

Return values:
None

Definition at line 428 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG ( ) WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)

Clear the the COMP2 EXTI flag.

Return values:
None

Definition at line 512 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI Line in event mode.

Return values:
None

Definition at line 500 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line falling edge trigger.

Return values:
None

Definition at line 459 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line.

Return values:
None

Definition at line 488 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line rising edge trigger.

Return values:
None

Definition at line 447 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
                                                               __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
                                                             } while(0)

Disable the COMP2 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 474 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI Line in event mode.

Return values:
None

Definition at line 494 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line falling edge trigger.

Return values:
None

Definition at line 453 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_IT ( ) SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line.

Return values:
None

Definition at line 482 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line rising edge trigger.

Return values:
None

Definition at line 441 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
                                                               __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
                                                             } while(0)

Enable the COMP2 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 465 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2)

Generate a software interrupt on the COMP2 EXTI line.

Return values:
None

Definition at line 530 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_GET_FLAG ( ) READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)

Check whether the COMP2 EXTI line flag is set or not.

Return values:
RESET or SET

Definition at line 506 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTID3_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)

Disable the COMP2 D3 EXTI Line in event mode.

Return values:
None

Definition at line 524 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTID3_ENABLE_EVENT ( ) SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)

Enable the COMP2 D3 EXTI Line in event mode.

Return values:
None

Definition at line 518 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CFGR) &= ~(__INTERRUPT__))

Disable the specified COMP interrupt.

Parameters:
__HANDLE__,: specifies the COMP Handle.
__INTERRUPT__,: specifies the COMP interrupt source to enable. This parameter can be one of the following values:
  • COMP_CFGRx_ITEN : Comparator interrupt
Return values:
None

Definition at line 587 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define __HAL_COMP_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ( ((__HANDLE__)->Instance->CFGR) |= (__INTERRUPT__) )

Enable the specified COMP interrupt.

Parameters:
__HANDLE__,: specifies the COMP Handle.
__INTERRUPT__,: specifies the COMP interrupt source to enable. This parameter can be one of the following values:
  • COMP_CFGRx_ITEN : Comparator interrupt
Return values:
None

Definition at line 578 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_GET_FLAG ( __FLAG__ ) ((COMP12->SR & (__FLAG__)) == (__FLAG__))

Checks whether the specified COMP flag is set or not.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • COMP_FLAG_C1I: Comparator 1 Interrupt Flag
  • COMP_FLAG_C2I: Comparator 2 Interrupt Flag
Return values:
The new state of __FLAG__ (TRUE or FALSE)

Definition at line 550 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define __HAL_COMP_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CFGR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks if the specified COMP interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: specifies the COMP Handle. This parameter can be COMP1 where x: 1 or 2 to select the COMP peripheral.
__INTERRUPT__,: specifies the COMP interrupt source to check. This parameter can be one of the following values:
  • COMP_IT_EN: Comparator interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE)

Definition at line 541 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: COMP Exported Macros

Modules | Defines
COMP Exported Macros
COMP

Modules

COMP Handle Management
COMP external interrupt line management

Defines

#define | __HAL_COMP_ENABLE_OR(__AF__) SET_BIT(COMP12->OR, (__AF__))
Enable the specified bit in the Option register.
#define | __HAL_COMP_DISABLE_OR(__AF__) CLEAR_BIT(COMP12->OR, (__AF__))
Disable the specified bit in the Option register.

Define Documentation

#define __HAL_COMP_DISABLE_OR ( __AF__ ) CLEAR_BIT(COMP12->OR, (__AF__))

Disable the specified bit in the Option register.

Parameters:
__AF__,: specifies the Alternate Function source selection . This parameter can be one of the following values:
  • COMP_OR_AFOPA6 : Alternate Function PA6 source selection
  • COMP_OR_AFOPA8 : Alternate Function PA8 source selection
  • COMP_OR_AFOPB12 : Alternate Function PB12 source selection
  • COMP_OR_AFOPE6 : Alternate Function PE6 source selection
  • COMP_OR_AFOPE15 : Alternate Function PE15 source selection
  • COMP_OR_AFOPG2 : Alternate Function PG2 source selection
  • COMP_OR_AFOPG3 : Alternate Function PG3 source selection
  • COMP_OR_AFOPG4 : Alternate Function PG4 source selection
  • COMP_OR_AFOPI1 : Alternate Function PI1 source selection
  • COMP_OR_AFOPI4 : Alternate Function PI4 source selection
  • COMP_OR_AFOPK2 : Alternate Function PK2 source selection
Return values:
None

Definition at line 626 of file stm32h7xx_hal_comp.h.

#define __HAL_COMP_ENABLE_OR ( __AF__ ) SET_BIT(COMP12->OR, (__AF__))

Enable the specified bit in the Option register.

Parameters:
__AF__,: specifies the Alternate Function source selection . This parameter can be one of the following values:
  • COMP_OR_AFOPA6 : Alternate Function PA6 source selection
  • COMP_OR_AFOPA8 : Alternate Function PA8 source selection
  • COMP_OR_AFOPB12 : Alternate Function PB12 source selection
  • COMP_OR_AFOPE6 : Alternate Function PE6 source selection
  • COMP_OR_AFOPE15 : Alternate Function PE15 source selection
  • COMP_OR_AFOPG2 : Alternate Function PG2 source selection
  • COMP_OR_AFOPG3 : Alternate Function PG3 source selection
  • COMP_OR_AFOPG4 : Alternate Function PG4 source selection
  • COMP_OR_AFOPI1 : Alternate Function PI1 source selection
  • COMP_OR_AFOPI4 : Alternate Function PI4 source selection
  • COMP_OR_AFOPK2 : Alternate Function PK2 source selection
Return values:
None

Definition at line 608 of file stm32h7xx_hal_comp.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: COMP EXTI Lines

Defines
COMP EXTI Lines
COMP Private Constants

Defines

#define | COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM20)
#define | COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM21)
#define | COMP_EXTI_IT ((uint32_t) 0x01)
#define | COMP_EXTI_EVENT ((uint32_t) 0x02)
#define | COMP_EXTI_RISING ((uint32_t) 0x10)
#define | COMP_EXTI_FALLING ((uint32_t) 0x20)

Define Documentation

#define COMP_EXTI_EVENT ((uint32_t) 0x02)

EXTI line event only (without interruption)

Definition at line 648 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_EXTI_FALLING ((uint32_t) 0x20)

EXTI line event on falling edge

Definition at line 650 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_EXTI_IT ((uint32_t) 0x01)

EXTI line event with interruption

Definition at line 647 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM20)

EXTI line 20 connected to COMP1 output

Definition at line 639 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM21)

EXTI line 21 connected to COMP2 output

Definition at line 640 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define COMP_EXTI_RISING ((uint32_t) 0x10)

EXTI line event on rising edge

Definition at line 649 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: COMP Private Constants

Modules | Defines
COMP Private Constants
COMP

Modules

COMP EXTI Lines

Defines

#define | COMP_DELAY_STARTUP_US ((uint32_t) 80U)
#define | COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U)

Define Documentation

#define COMP_DELAY_STARTUP_US ((uint32_t) 80U)

Delay for COMP startup time

Definition at line 181 of file stm32h7xx_hal_comp.c.

Referenced by HAL_COMP_Start(), and HAL_COMP_Start_IT().

#define COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U)

Delay for COMP voltage scaler stabilization time

Definition at line 187 of file stm32h7xx_hal_comp.c.

Referenced by HAL_COMP_Init().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: COMP Private macros to get EXTI line associated with Comparators

Defines
COMP Private macros to get EXTI line associated with Comparators
COMP Private Macros

Defines

#define COMP_GET_EXTI_LINE(__INSTANCE__)
Get the specified EXTI line for a comparator instance.

Define Documentation

#define COMP_GET_EXTI_LINE ( __INSTANCE__ )
Value:
(((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
                                                      COMP_EXTI_LINE_COMP2)

Get the specified EXTI line for a comparator instance.

Parameters:
__INSTANCE__,: specifies the COMP instance.
Return values:
value of COMP EXTI Lines

Definition at line 670 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init(), HAL_COMP_IRQHandler(), and HAL_COMP_Stop_IT().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: COMP private macros to check input parameters

Defines
COMP private macros to check input parameters
COMP Private Macros

Defines

#define | IS_COMP_WINDOWMODE(__WINDOWMODE__)
#define | IS_COMP_POWERMODE(__POWERMODE__)
#define | IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_COMP_HYSTERESIS(__HYSTERESIS__)
#define | IS_COMP_OUTPUTPOL(__POL__)
#define | IS_COMP_BLANKINGSRCE(__SOURCE__)
#define | IS_COMP_TRIGGERMODE(__MODE__)
#define | IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__)

Define Documentation

#define IS_COMP_BLANKINGSRCE ( __SOURCE__ )
Value:
(((__SOURCE__) == COMP_BLANKINGSRC_NONE)            || \
                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5)  || \
                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3)  || \
                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3)  || \
                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4)  || \
                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5)  || \
                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1))

Definition at line 709 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_HYSTERESIS ( __HYSTERESIS__ )
Value:
(((__HYSTERESIS__) == COMP_HYSTERESIS_NONE)   || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW)    || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))

Definition at line 701 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_INPUT_MINUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_MINUS__
 | ) |
Value:
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)    || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)    || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2))

Definition at line 691 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_INPUT_PLUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_PLUS__
 | ) |
Value:
(((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
                                                               ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2))

Definition at line 686 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_OUTPUT_LEVEL ( __OUTPUT_LEVEL__ )
Value:
(((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW)     || \
                                                ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))

Definition at line 726 of file stm32h7xx_hal_comp.h.

#define IS_COMP_OUTPUTPOL ( __POL__ )
Value:
(((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
                                             ((__POL__) == COMP_OUTPUTPOL_INVERTED))

Definition at line 706 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_POWERMODE ( __POWERMODE__ )
Value:
(((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED)    || \
                                             ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED)  || \
                                             ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER)  )

Definition at line 681 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_TRIGGERMODE ( __MODE__ )
Value:
(((__MODE__) == COMP_TRIGGERMODE_NONE)                 || \
                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING)            || \
                                             ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \
                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \
                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \
                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \
                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))

Definition at line 718 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_WINDOWMODE ( __WINDOWMODE__ )
Value:
(((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE)                || \
                                             ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)  )

Definition at line 678 of file stm32h7xx_hal_comp.h.

Referenced by HAL_COMP_Init().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CORTEX Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Sets the priority grouping field (preemption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Sets the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiates a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initializes the System Timer and its interrupt, and starts the System Tick Timer.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]
      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
      Systick functionalities

Function Documentation

void HAL_NVIC_DisableIRQ ( IRQn_Type IRQn )

Disables a device specific interrupt in the NVIC interrupt controller.

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
Return values:
None

Definition at line 221 of file stm32h7xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_EnableIRQ ( IRQn_Type IRQn )

Enables a device specific interrupt in the NVIC interrupt controller.

Note:
To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() function should be called before.
Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
Return values:
None

Definition at line 205 of file stm32h7xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_SetPriority | ( | IRQn_Type | IRQn,
 |  | uint32_t | PreemptPriority,
 |  | uint32_t | SubPriority
 | ) |  |

Sets the priority of an interrupt.

Parameters:
IRQn,: External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
PreemptPriority,: The preemption priority for the IRQn channel. This parameter can be a value between 0 and 15 A lower priority value indicates a higher priority
SubPriority,: the subpriority level for the IRQ channel. This parameter can be a value between 0 and 15 A lower priority value indicates a higher priority.
Return values:
None

Definition at line 183 of file stm32h7xx_hal_cortex.c.

References assert_param, IS_NVIC_PREEMPTION_PRIORITY, and IS_NVIC_SUB_PRIORITY.

Referenced by HAL_InitTick().

void HAL_NVIC_SetPriorityGrouping ( uint32_t PriorityGroup )

Sets the priority grouping field (preemption priority and subpriority) using the required unlock sequence.

Parameters:
PriorityGroup,: The priority grouping bits length. This parameter can be one of the following values:
  • NVIC_PRIORITYGROUP_0: 0 bits for preemption priority 4 bits for subpriority
  • NVIC_PRIORITYGROUP_1: 1 bits for preemption priority 3 bits for subpriority
  • NVIC_PRIORITYGROUP_2: 2 bits for preemption priority 2 bits for subpriority
  • NVIC_PRIORITYGROUP_3: 3 bits for preemption priority 1 bits for subpriority
  • NVIC_PRIORITYGROUP_4: 4 bits for preemption priority 0 bits for subpriority
Note:
When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. The pending IRQ priority will be managed only by the subpriority.
Return values:
None

Definition at line 161 of file stm32h7xx_hal_cortex.c.

References assert_param, and IS_NVIC_PRIORITY_GROUP.

Referenced by HAL_Init().

void HAL_NVIC_SystemReset ( void )

Initiates a system reset request to reset the MCU.

Return values:
None

Definition at line 234 of file stm32h7xx_hal_cortex.c.

uint32_t HAL_SYSTICK_Config ( uint32_t TicksNumb )

Initializes the System Timer and its interrupt, and starts the System Tick Timer.

Counter is in free running mode to generate periodic interrupts.

Parameters:
TicksNumb,: Specifies the ticks Number of ticks between two interrupts.
Return values:
status,: - 0 Function succeeded.
  • 1 Function failed.

Definition at line 247 of file stm32h7xx_hal_cortex.c.

Referenced by HAL_InitTick().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
CORTEX Exported Functions

Cortex control functions. More...

Functions

void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initializes and configures the Region and the memory to be protected.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Gets the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Gets the priority of an interrupt.
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Sets Pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clears the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Gets active interrupt ( reads the active register in NVIC and returns the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configures the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
This function handles SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.
uint32_t | HAL_GetCurrentCPUID (void)
Returns the current CPU ID.

Detailed Description

Cortex control functions.

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
    [..]
      This subsection provides a set of functions allowing to control the CORTEX
      (NVIC, SYSTICK, MPU) functionalities.

Function Documentation

uint32_t HAL_GetCurrentCPUID ( void )

Returns the current CPU ID.

Return values:
CPU identifier

Definition at line 470 of file stm32h7xx_hal_cortex.c.

References CM7_CPUID.

Referenced by HAL_HSEM_FastTake(), HAL_HSEM_Release(), and HAL_HSEM_Take().

void HAL_MPU_ConfigRegion ( MPU_Region_InitTypeDef * MPU_Init )

Initializes and configures the Region and the memory to be protected.

Parameters:
MPU_Init,: Pointer to a MPU_Region_InitTypeDef structure that contains the initialization and configuration information.
Return values:
None

Definition at line 277 of file stm32h7xx_hal_cortex.c.

References MPU_Region_InitTypeDef::AccessPermission, assert_param, MPU_Region_InitTypeDef::BaseAddress, MPU_Region_InitTypeDef::DisableExec, MPU_Region_InitTypeDef::Enable, IS_MPU_ACCESS_BUFFERABLE, IS_MPU_ACCESS_CACHEABLE, IS_MPU_ACCESS_SHAREABLE, IS_MPU_INSTRUCTION_ACCESS, IS_MPU_REGION_ENABLE, IS_MPU_REGION_NUMBER, IS_MPU_REGION_PERMISSION_ATTRIBUTE, IS_MPU_REGION_SIZE, IS_MPU_SUB_REGION_DISABLE, IS_MPU_TEX_LEVEL, MPU_Region_InitTypeDef::IsBufferable, MPU_Region_InitTypeDef::IsCacheable, MPU_Region_InitTypeDef::IsShareable, MPU_Region_InitTypeDef::Number, MPU_Region_InitTypeDef::Size, MPU_Region_InitTypeDef::SubRegionDisable, and MPU_Region_InitTypeDef::TypeExtField.

void HAL_NVIC_ClearPendingIRQ ( IRQn_Type IRQn )

Clears the pending bit of an external interrupt.

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
Return values:
None

Definition at line 397 of file stm32h7xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

uint32_t HAL_NVIC_GetActive ( IRQn_Type IRQn )

Gets active interrupt ( reads the active register in NVIC and returns the active bit).

Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
Return values:
status,: - 0 Interrupt status is not pending.
  • 1 Interrupt status is pending.

Definition at line 414 of file stm32h7xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

uint32_t HAL_NVIC_GetPendingIRQ ( IRQn_Type IRQn )

Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
Return values:
status,: - 0 Interrupt status is not pending.
  • 1 Interrupt status is pending.

Definition at line 381 of file stm32h7xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_GetPriority | ( | IRQn_Type | IRQn,
 |  | uint32_t | PriorityGroup,
 |  | uint32_t * | pPreemptPriority,
 |  | uint32_t * | pSubPriority
 | ) |  |

Gets the priority of an interrupt.

Parameters:
IRQn,: External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
PriorityGroup,: the priority grouping bits length. This parameter can be one of the following values:
  • NVIC_PRIORITYGROUP_0: 0 bits for preemption priority 4 bits for subpriority
  • NVIC_PRIORITYGROUP_1: 1 bits for preemption priority 3 bits for subpriority
  • NVIC_PRIORITYGROUP_2: 2 bits for preemption priority 2 bits for subpriority
  • NVIC_PRIORITYGROUP_3: 3 bits for preemption priority 1 bits for subpriority
  • NVIC_PRIORITYGROUP_4: 4 bits for preemption priority 0 bits for subpriority
pPreemptPriority,: Pointer on the Preemptive priority value (starting from 0).
pSubPriority,: Pointer on the Subpriority value (starting from 0).
Return values:
None

Definition at line 348 of file stm32h7xx_hal_cortex.c.

References assert_param, and IS_NVIC_PRIORITY_GROUP.

uint32_t HAL_NVIC_GetPriorityGrouping ( void )

Gets the priority grouping field from the NVIC Interrupt Controller.

Return values:
Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)

Definition at line 321 of file stm32h7xx_hal_cortex.c.

void HAL_NVIC_SetPendingIRQ ( IRQn_Type IRQn )

Sets Pending bit of an external interrupt.

Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
Return values:
None

Definition at line 363 of file stm32h7xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_SYSTICK_Callback ( void )

SYSTICK callback.

Return values:
None

Definition at line 458 of file stm32h7xx_hal_cortex.c.

Referenced by HAL_SYSTICK_IRQHandler().

void HAL_SYSTICK_CLKSourceConfig ( uint32_t CLKSource )

Configures the SysTick clock source.

Parameters:
CLKSource,: specifies the SysTick clock source. This parameter can be one of the following values:
  • SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
  • SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
Return values:
None

Definition at line 431 of file stm32h7xx_hal_cortex.c.

References assert_param, IS_SYSTICK_CLK_SOURCE, and SYSTICK_CLKSOURCE_HCLK.

void HAL_SYSTICK_IRQHandler ( void )

This function handles SYSTICK interrupt request.

Return values:
None

Definition at line 449 of file stm32h7xx_hal_cortex.c.

References HAL_SYSTICK_Callback().

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STM32H753xx HAL User Manual: MPU_Region_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
MPU_Region_InitTypeDef Struct Reference
MPU Region Initialization Structure Definition

#include <stm32h7xx_hal_cortex.h>

Data Fields

uint8_t | Enable
uint8_t | Number
uint32_t | BaseAddress
uint8_t | Size
uint8_t | SubRegionDisable
uint8_t | TypeExtField
uint8_t | AccessPermission
uint8_t | DisableExec
uint8_t | IsShareable
uint8_t | IsCacheable
uint8_t | IsBufferable

Detailed Description

Definition at line 66 of file stm32h7xx_hal_cortex.h.

Field Documentation

uint8_t MPU_Region_InitTypeDef::AccessPermission

Specifies the region access permission type. This parameter can be a value of CORTEX MPU Region Permission Attributes

Definition at line 79 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint32_t MPU_Region_InitTypeDef::BaseAddress

Specifies the base address of the region to protect.

Definition at line 72 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::DisableExec

Specifies the instruction access status. This parameter can be a value of CORTEX MPU Instruction Access

Definition at line 81 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Enable

Specifies the status of the region. This parameter can be a value of CORTEX MPU Region Enable

Definition at line 68 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsBufferable

Specifies the bufferable status of the protected region. This parameter can be a value of CORTEX MPU Instruction Access Bufferable

Definition at line 87 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsCacheable

Specifies the cacheable status of the region protected. This parameter can be a value of CORTEX MPU Instruction Access Cacheable

Definition at line 85 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsShareable

Specifies the shareability status of the protected region. This parameter can be a value of CORTEX MPU Instruction Access Shareable

Definition at line 83 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Number

Specifies the number of the region to protect. This parameter can be a value of CORTEX MPU Region Number

Definition at line 70 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Size

Specifies the size of the region to protect. This parameter can be a value of CORTEX MPU Region Size

Definition at line 73 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::SubRegionDisable

Specifies the number of the subregion protection to disable. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 75 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::TypeExtField

Specifies the TEX field level. This parameter can be a value of MPU TEX Levels

Definition at line 77 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_cortex.h
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STM32H753xx HAL User Manual: CORTEX Preemption Priority Group

Defines
CORTEX Preemption Priority Group
CORTEX Exported Constants

Defines

#define | NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007)
#define | NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006)
#define | NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005)
#define | NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004)
#define | NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003)

Define Documentation

#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007)

0 bits for pre-emption priority 4 bits for subpriority

Definition at line 108 of file stm32h7xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006)

1 bits for pre-emption priority 3 bits for subpriority

Definition at line 110 of file stm32h7xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005)

2 bits for pre-emption priority 2 bits for subpriority

Definition at line 112 of file stm32h7xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004)

3 bits for pre-emption priority 1 bits for subpriority

Definition at line 114 of file stm32h7xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003)

4 bits for pre-emption priority 0 bits for subpriority

Definition at line 116 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_Init().

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STM32H753xx HAL User Manual: CORTEX _SysTick clock source

Defines
CORTEX _SysTick clock source
CORTEX Exported Constants

Defines

#define | SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
#define | SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)

Define Documentation

#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)

Definition at line 126 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_SYSTICK_CLKSourceConfig().

#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)

Definition at line 125 of file stm32h7xx_hal_cortex.h.

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STM32H753xx HAL User Manual: MPU HFNMI and PRIVILEGED Access control

Defines
MPU HFNMI and PRIVILEGED Access control
CORTEX Exported Constants

Defines

#define | MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
#define | MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
#define | MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
#define | MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)

Define Documentation

#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)

Definition at line 137 of file stm32h7xx_hal_cortex.h.

#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)

Definition at line 139 of file stm32h7xx_hal_cortex.h.

#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)

Definition at line 136 of file stm32h7xx_hal_cortex.h.

#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)

Definition at line 138 of file stm32h7xx_hal_cortex.h.

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STM32H753xx HAL User Manual: CORTEX MPU Region Enable

Defines
CORTEX MPU Region Enable
CORTEX Exported Constants

Defines

#define | MPU_REGION_ENABLE ((uint8_t)0x01)
#define | MPU_REGION_DISABLE ((uint8_t)0x00)

Define Documentation

#define MPU_REGION_DISABLE ((uint8_t)0x00)

Definition at line 148 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_ENABLE ((uint8_t)0x01)

Definition at line 147 of file stm32h7xx_hal_cortex.h.

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STM32H753xx HAL User Manual: CORTEX MPU Instruction Access

Defines
CORTEX MPU Instruction Access
CORTEX Exported Constants

Defines

#define | MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define | MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)

Define Documentation

#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)

Definition at line 157 of file stm32h7xx_hal_cortex.h.

#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)

Definition at line 156 of file stm32h7xx_hal_cortex.h.

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STM32H753xx HAL User Manual: CORTEX MPU Instruction Access Shareable

Defines
CORTEX MPU Instruction Access Shareable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)

Define Documentation

#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)

Definition at line 166 of file stm32h7xx_hal_cortex.h.

#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)

Definition at line 165 of file stm32h7xx_hal_cortex.h.

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STM32H753xx HAL User Manual: CORTEX MPU Instruction Access Cacheable

Defines
CORTEX MPU Instruction Access Cacheable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)

Define Documentation

#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)

Definition at line 174 of file stm32h7xx_hal_cortex.h.

#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)

Definition at line 175 of file stm32h7xx_hal_cortex.h.

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STM32H753xx HAL User Manual: CORTEX MPU Instruction Access Bufferable

Defines
CORTEX MPU Instruction Access Bufferable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)

Define Documentation

#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)

Definition at line 183 of file stm32h7xx_hal_cortex.h.

#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)

Definition at line 184 of file stm32h7xx_hal_cortex.h.

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STM32H753xx HAL User Manual: MPU TEX Levels

Defines
MPU TEX Levels
CORTEX Exported Constants

Defines

#define | MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define | MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define | MPU_TEX_LEVEL2 ((uint8_t)0x02)

Define Documentation

#define MPU_TEX_LEVEL0 ((uint8_t)0x00)

Definition at line 192 of file stm32h7xx_hal_cortex.h.

#define MPU_TEX_LEVEL1 ((uint8_t)0x01)

Definition at line 193 of file stm32h7xx_hal_cortex.h.

#define MPU_TEX_LEVEL2 ((uint8_t)0x02)

Definition at line 194 of file stm32h7xx_hal_cortex.h.

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STM32H753xx HAL User Manual: CORTEX MPU Region Size

Defines
CORTEX MPU Region Size
CORTEX Exported Constants

Defines

#define | MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define | MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define | MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define | MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define | MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define | MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define | MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define | MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define | MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define | MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define | MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define | MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define | MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define | MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define | MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define | MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define | MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define | MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define | MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define | MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define | MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define | MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define | MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define | MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define | MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define | MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define | MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define | MPU_REGION_SIZE_4GB ((uint8_t)0x1F)

Define Documentation

#define MPU_REGION_SIZE_128B ((uint8_t)0x06)

Definition at line 204 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)

Definition at line 214 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)

Definition at line 224 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)

Definition at line 211 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)

Definition at line 221 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)

Definition at line 227 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)

Definition at line 207 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)

Definition at line 217 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_256B ((uint8_t)0x07)

Definition at line 205 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)

Definition at line 215 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)

Definition at line 225 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)

Definition at line 228 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)

Definition at line 208 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)

Definition at line 218 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_32B ((uint8_t)0x04)

Definition at line 202 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)

Definition at line 212 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)

Definition at line 222 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)

Definition at line 229 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)

Definition at line 209 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)

Definition at line 219 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_512B ((uint8_t)0x08)

Definition at line 206 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)

Definition at line 216 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)

Definition at line 226 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_64B ((uint8_t)0x05)

Definition at line 203 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)

Definition at line 213 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)

Definition at line 223 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)

Definition at line 210 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)

Definition at line 220 of file stm32h7xx_hal_cortex.h.

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STM32H753xx HAL User Manual: CORTEX MPU Region Permission Attributes

Defines
CORTEX MPU Region Permission Attributes
CORTEX Exported Constants

Defines

#define | MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define | MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define | MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define | MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define | MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define | MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)

Define Documentation

#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)

Definition at line 240 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)

Definition at line 237 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_PRIV_RO ((uint8_t)0x05)

Definition at line 241 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)

Definition at line 242 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_PRIV_RW ((uint8_t)0x01)

Definition at line 238 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)

Definition at line 239 of file stm32h7xx_hal_cortex.h.

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STM32H753xx HAL User Manual: CORTEX MPU Region Number

Defines
CORTEX MPU Region Number
CORTEX Exported Constants

Defines

#define | MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define | MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define | MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define | MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define | MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define | MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define | MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define | MPU_REGION_NUMBER7 ((uint8_t)0x07)

Define Documentation

#define MPU_REGION_NUMBER0 ((uint8_t)0x00)

Definition at line 250 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER1 ((uint8_t)0x01)

Definition at line 251 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER2 ((uint8_t)0x02)

Definition at line 252 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER3 ((uint8_t)0x03)

Definition at line 253 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER4 ((uint8_t)0x04)

Definition at line 254 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER5 ((uint8_t)0x05)

Definition at line 255 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER6 ((uint8_t)0x06)

Definition at line 256 of file stm32h7xx_hal_cortex.h.

#define MPU_REGION_NUMBER7 ((uint8_t)0x07)

Definition at line 257 of file stm32h7xx_hal_cortex.h.

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STM32H753xx HAL User Manual: CORTEX Exported Macros

CORTEX Exported Macros
CORTEX
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STM32H753xx HAL User Manual: CORTEX_CPU_Identifier

Defines
CORTEX_CPU_Identifier
CORTEX

Defines

#define CM7_CPUID (uint32_t)0x00000003

Define Documentation

#define CM7_CPUID (uint32_t)0x00000003

Definition at line 282 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_GetCurrentCPUID().

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STM32H753xx HAL User Manual: CORTEX Private Macros

Defines
CORTEX Private Macros
CORTEX

Defines

#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define | IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
#define | IS_SYSTICK_CLK_SOURCE(SOURCE)
#define | IS_MPU_REGION_ENABLE(STATE)
#define | IS_MPU_INSTRUCTION_ACCESS(STATE)
#define | IS_MPU_ACCESS_SHAREABLE(STATE)
#define | IS_MPU_ACCESS_CACHEABLE(STATE)
#define | IS_MPU_ACCESS_BUFFERABLE(STATE)
#define | IS_MPU_TEX_LEVEL(TYPE)
#define | IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)
#define | IS_MPU_REGION_NUMBER(NUMBER)
#define | IS_MPU_REGION_SIZE(SIZE)
#define | IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)

Define Documentation

#define IS_MPU_ACCESS_BUFFERABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_BUFFERABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))

Definition at line 370 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_ACCESS_CACHEABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_CACHEABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))

Definition at line 367 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_ACCESS_SHAREABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_SHAREABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))

Definition at line 364 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_INSTRUCTION_ACCESS ( STATE )
Value:
(((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))

Definition at line 361 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_ENABLE ( STATE )
Value:
(((STATE) == MPU_REGION_ENABLE) || \
                                     ((STATE) == MPU_REGION_DISABLE))

Definition at line 358 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_NUMBER ( NUMBER )
Value:
(((NUMBER) == MPU_REGION_NUMBER0) || \
                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
                                         ((NUMBER) == MPU_REGION_NUMBER7))

Definition at line 384 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_PERMISSION_ATTRIBUTE ( TYPE )
Value:
(((TYPE) == MPU_REGION_NO_ACCESS)   || \
                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))

Definition at line 377 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_SIZE ( SIZE )
Value:
(((SIZE) == MPU_REGION_SIZE_32B)   || \
                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4GB))

Definition at line 393 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_SUB_REGION_DISABLE ( SUBREGION ) ((SUBREGION) < (uint16_t)0x00FF)

Definition at line 422 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_TEX_LEVEL ( TYPE )
Value:
(((TYPE) == MPU_TEX_LEVEL0)  || \
                                ((TYPE) == MPU_TEX_LEVEL1)  || \
                                ((TYPE) == MPU_TEX_LEVEL2))

Definition at line 373 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_NVIC_DEVICE_IRQ ( IRQ ) ((IRQ) >= 0x00)

Definition at line 352 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_NVIC_ClearPendingIRQ(), HAL_NVIC_DisableIRQ(), HAL_NVIC_EnableIRQ(), HAL_NVIC_GetActive(), HAL_NVIC_GetPendingIRQ(), and HAL_NVIC_SetPendingIRQ().

#define IS_NVIC_PREEMPTION_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10)

Definition at line 348 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_NVIC_SetPriority().

#define IS_NVIC_PRIORITY_GROUP ( GROUP )
Value:
(((GROUP) == NVIC_PRIORITYGROUP_0) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_4))

Definition at line 342 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_NVIC_GetPriority(), and HAL_NVIC_SetPriorityGrouping().

#define IS_NVIC_SUB_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10)

Definition at line 350 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_NVIC_SetPriority().

#define IS_SYSTICK_CLK_SOURCE ( SOURCE )
Value:
(((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))

Definition at line 354 of file stm32h7xx_hal_cortex.h.

Referenced by HAL_SYSTICK_CLKSourceConfig().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CORTEX Private Functions

Functions
CORTEX Private Functions
CORTEX

CORTEX private functions. More...

Functions

__STATIC_INLINE void | HAL_MPU_Disable (void)
Disables the MPU.
__STATIC_INLINE void | HAL_MPU_Enable (uint32_t MPU_Control)
Enables the MPU.

Detailed Description

CORTEX private functions.

Function Documentation

__STATIC_INLINE void HAL_MPU_Disable ( void )

Disables the MPU.

Return values:
None

Definition at line 440 of file stm32h7xx_hal_cortex.h.

__STATIC_INLINE void HAL_MPU_Enable ( uint32_t MPU_Control )

Enables the MPU.

Parameters:
MPU_Control,: Specifies the control mode of the MPU during hard fault, NMI, FAULTMASK and privileged access to the default memory This parameter can be one of the following values:
  • MPU_HFNMI_PRIVDEF_NONE
  • MPU_HARDFAULT_NMI
  • MPU_PRIVILEGED_DEFAULT
  • MPU_HFNMI_PRIVDEF
Return values:
None

Definition at line 460 of file stm32h7xx_hal_cortex.h.

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STM32H753xx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
CRC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initialize the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the CRC according to the specified parameters
          in the CRC_InitTypeDef and create the associated handle
      (+) DeInitialize the CRC peripheral
      (+) Initialize the CRC MSP
      (+) DeInitialize CRC MSP

Function Documentation

HAL_StatusTypeDef HAL_CRC_DeInit ( CRC_HandleTypeDef * hcrc )

DeInitialize the CRC peripheral.

Parameters:
hcrc,: CRC handle
Return values:
HAL status

Definition at line 195 of file stm32h7xx_hal_crc.c.

References __HAL_CRC_DR_RESET, assert_param, HAL_CRC_MspDeInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_RESET, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRC_Init ( CRC_HandleTypeDef * hcrc )

Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.

Parameters:
hcrc,: CRC handle
Return values:
HAL status

Definition at line 118 of file stm32h7xx_hal_crc.c.

References assert_param, CRC_POLYLENGTH_32B, CRC_InitTypeDef::CRCLength, DEFAULT_CRC32_POLY, DEFAULT_CRC_INITVALUE, DEFAULT_INIT_VALUE_ENABLE, DEFAULT_POLYNOMIAL_ENABLE, CRC_InitTypeDef::DefaultInitValueUse, CRC_InitTypeDef::DefaultPolynomialUse, CRC_InitTypeDef::GeneratingPolynomial, HAL_CRC_MspInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, HAL_CRC_STATE_RESET, HAL_CRCEx_Polynomial_Set(), CRC_HandleTypeDef::Init, CRC_InitTypeDef::InitValue, CRC_HandleTypeDef::InputDataFormat, CRC_InitTypeDef::InputDataInversionMode, CRC_HandleTypeDef::Instance, IS_CRC_INPUTDATA_FORMAT, IS_CRC_INPUTDATA_INVERSION_MODE, IS_CRC_OUTPUTDATA_INVERSION_MODE, IS_DEFAULT_INIT_VALUE, IS_DEFAULT_POLYNOMIAL, CRC_HandleTypeDef::Lock, CRC_InitTypeDef::OutputDataInversionMode, and CRC_HandleTypeDef::State.

__weak void HAL_CRC_MspDeInit ( CRC_HandleTypeDef * hcrc )

DeInitialize the CRC MSP.

Parameters:
hcrc,: CRC handle
Return values:
None

Definition at line 254 of file stm32h7xx_hal_crc.c.

Referenced by HAL_CRC_DeInit().

__weak void HAL_CRC_MspInit ( CRC_HandleTypeDef * hcrc )

Initialize the CRC MSP.

Parameters:
hcrc,: CRC handle
Return values:
None

Definition at line 239 of file stm32h7xx_hal_crc.c.

Referenced by HAL_CRC_Init().

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STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
CRC Exported Functions

Peripheral Control functions. More...

Functions

uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.
static uint32_t | CRC_Handle_8 (CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
Enter 8-bit input data to the CRC calculator.
static uint32_t | CRC_Handle_16 (CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
Enter 16-bit input data to the CRC calculator.

Detailed Description

Peripheral Control functions.

 ==============================================================================
                      ##### Peripheral Control functions #####
 ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
          using combination of the previous CRC value and the new one.

          or

      (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
          independently of the previous CRC value.

Function Documentation

static uint32_t CRC_Handle_16 | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint16_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  | [static]

Enter 16-bit input data to the CRC calculator.

Specific data handling to optimize processing time.

Parameters:
hcrc,: CRC handle
pBuffer,: pointer to the input data buffer
BufferLength,: input data buffer length
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 459 of file stm32h7xx_hal_crc.c.

References CRC_HandleTypeDef::Instance.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

static uint32_t CRC_Handle_8 | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint8_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  | [static]

Enter 8-bit input data to the CRC calculator.

Specific data handling to optimize processing time.

Parameters:
hcrc,: CRC handle
pBuffer,: pointer to the input data buffer
BufferLength,: input data buffer length
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 418 of file stm32h7xx_hal_crc.c.

References CRC_HandleTypeDef::Instance.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

uint32_t HAL_CRC_Accumulate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.

Parameters:
hcrc,: CRC handle
pBuffer,: pointer to the input data buffer, exact input data format is provided by hcrc->InputDataFormat.
BufferLength,: input data buffer length (number of bytes if pBuffer type is * uint8_t, number of half-words if pBuffer type is * uint16_t, number of words if pBuffer type is * uint32_t).
Note:
By default, the API expects a uint32_t pointer as input buffer parameter. Input buffer pointers with other types simply need to be cast in uint32_t and the API will internally adjust its input data processing based on the handle field hcrc->InputDataFormat.
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 303 of file stm32h7xx_hal_crc.c.

References CRC_Handle_16(), CRC_Handle_8(), CRC_INPUTDATA_FORMAT_BYTES, CRC_INPUTDATA_FORMAT_HALFWORDS, CRC_INPUTDATA_FORMAT_WORDS, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::InputDataFormat, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

uint32_t HAL_CRC_Calculate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.

Parameters:
hcrc,: CRC handle
pBuffer,: pointer to the input data buffer, exact input data format is provided by hcrc->InputDataFormat.
BufferLength,: input data buffer length (number of bytes if pBuffer type is * uint8_t, number of half-words if pBuffer type is * uint16_t, number of words if pBuffer type is * uint32_t).
Note:
By default, the API expects a uint32_t pointer as input buffer parameter. Input buffer pointers with other types simply need to be cast in uint32_t and the API will internally adjust its input data processing based on the handle field hcrc->InputDataFormat.
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 361 of file stm32h7xx_hal_crc.c.

References __HAL_CRC_DR_RESET, CRC_Handle_16(), CRC_Handle_8(), CRC_INPUTDATA_FORMAT_BYTES, CRC_INPUTDATA_FORMAT_HALFWORDS, CRC_INPUTDATA_FORMAT_WORDS, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::InputDataFormat, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
CRC Exported Functions

Peripheral State functions. More...

Functions

HAL_CRC_StateTypeDef HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC state.

Detailed Description

Peripheral State functions.

 ==============================================================================
                      ##### Peripheral State functions #####
 ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_CRC_StateTypeDef HAL_CRC_GetState ( CRC_HandleTypeDef * hcrc )

Return the CRC state.

Parameters:
hcrc,: CRC handle
Return values:
HAL state

Definition at line 503 of file stm32h7xx_hal_crc.c.

References CRC_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRC Exported Functions

Modules | Defines
CRC Exported Functions
CRC

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

Defines

#define | HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
#define | HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse

Define Documentation

#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse

Definition at line 306 of file stm32h7xx_hal_crc.h.

#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse

Definition at line 307 of file stm32h7xx_hal_crc.h.

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STM32H753xx HAL User Manual: CRC State Structure definition

Enumerations
CRC State Structure definition
CRC Exported Types

Enumerations

enum HAL_CRC_StateTypeDef {
HAL_CRC_STATE_RESET = 0x00U, HAL_CRC_STATE_READY = 0x01U, HAL_CRC_STATE_BUSY = 0x02U, HAL_CRC_STATE_TIMEOUT = 0x03U,
HAL_CRC_STATE_ERROR = 0x04U
}

Enumeration Type Documentation

enum HAL_CRC_StateTypeDef
Enumerator:
HAL_CRC_STATE_RESET

CRC not yet initialized or disabled

HAL_CRC_STATE_READY

CRC initialized and ready for use

HAL_CRC_STATE_BUSY

CRC internal process is ongoing

HAL_CRC_STATE_TIMEOUT

CRC timeout state

HAL_CRC_STATE_ERROR

CRC error state

Definition at line 66 of file stm32h7xx_hal_crc.h.

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STM32H753xx HAL User Manual: CRC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRC_InitTypeDef Struct Reference
CRC Init Structure definition

#include <stm32h7xx_hal_crc.h>

Data Fields

uint8_t | DefaultPolynomialUse
uint8_t | DefaultInitValueUse
uint32_t | GeneratingPolynomial
uint32_t | CRCLength
uint32_t | InitValue
uint32_t | InputDataInversionMode
uint32_t | OutputDataInversionMode

Detailed Description

Definition at line 81 of file stm32h7xx_hal_crc.h.

Field Documentation

uint32_t CRC_InitTypeDef::CRCLength

This parameter is a value of Polynomial sizes to configure the IP and indicates CRC length. Value can be either one of CRC_POLYLENGTH_32B (32-bit CRC) CRC_POLYLENGTH_16B (16-bit CRC) CRC_POLYLENGTH_8B (8-bit CRC) CRC_POLYLENGTH_7B (7-bit CRC)

Definition at line 99 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint8_t CRC_InitTypeDef::DefaultInitValueUse

This parameter is a value of Indicates whether or not default init value is used and indicates if default init value is used. If set to DEFAULT_INIT_VALUE_ENABLE, resort to default 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set

Definition at line 89 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint8_t CRC_InitTypeDef::DefaultPolynomialUse

This parameter is a value of Indicates whether or not default polynomial is used and indicates if default polynomial is used. If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. In that case, there is no need to set GeneratingPolynomial field. If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set

Definition at line 83 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::GeneratingPolynomial

Set CRC generating polynomial. 7, 8, 16 or 32-bit long value for a polynomial degree respectively equal to 7, 8, 16 or 32. This field is written in normal representation, e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65. No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE

Definition at line 94 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::InitValue

Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse is set to DEFAULT_INIT_VALUE_ENABLE

Definition at line 106 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::InputDataInversionMode

This parameter is a value of CRC Extended input data inversion modes and specifies input data inversion mode. Can be either one of the following values CRC_INPUTDATA_INVERSION_NONE no input data inversion CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2 CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458

Definition at line 109 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::OutputDataInversionMode

This parameter is a value of CRC Extended output data inversion modes and specifies output data (i.e. CRC) inversion mode. Can be either CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, or CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488

Definition at line 116 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_crc.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRC_HandleTypeDef Struct Reference
CRC Handle Structure definition

#include <stm32h7xx_hal_crc.h>

Data Fields

CRC_TypeDef * | Instance
CRC_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_CRC_StateTypeDef | State
uint32_t | InputDataFormat

Detailed Description

Definition at line 128 of file stm32h7xx_hal_crc.h.

Field Documentation

CRC_InitTypeDef CRC_HandleTypeDef::Init

CRC configuration parameters

Definition at line 132 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_HandleTypeDef::InputDataFormat

This parameter is a value of CRC input buffer format and specifies input data format. Can be either CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data) CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data) CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bits data) Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error must occur if InputBufferFormat is not one of the three values listed above

Definition at line 138 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), HAL_CRC_Calculate(), and HAL_CRC_Init().

CRC_TypeDef* CRC_HandleTypeDef::Instance

Register base address

Definition at line 130 of file stm32h7xx_hal_crc.h.

Referenced by CRC_Handle_16(), CRC_Handle_8(), HAL_CRC_Accumulate(), HAL_CRC_Calculate(), HAL_CRC_DeInit(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), HAL_CRCEx_Output_Data_Reverse(), and HAL_CRCEx_Polynomial_Set().

HAL_LockTypeDef CRC_HandleTypeDef::Lock

CRC Locking object

Definition at line 134 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

__IO HAL_CRC_StateTypeDef CRC_HandleTypeDef::State

CRC communication state

Definition at line 136 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), HAL_CRC_Calculate(), HAL_CRC_DeInit(), HAL_CRC_GetState(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), and HAL_CRCEx_Output_Data_Reverse().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_crc.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Default CRC generating polynomial

Defines
Default CRC generating polynomial
CRC exported constants

Defines

#define DEFAULT_CRC32_POLY 0x04C11DB7U

Define Documentation

#define DEFAULT_CRC32_POLY 0x04C11DB7U

Definition at line 162 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Default CRC computation initialization value

Defines
Default CRC computation initialization value
CRC exported constants

Defines

#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Define Documentation

#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Definition at line 171 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32H753xx HAL User Manual: Indicates whether or not default polynomial is used

Defines
Indicates whether or not default polynomial is used
CRC exported constants

Defines

#define | DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)

Define Documentation

#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)

Definition at line 181 of file stm32h7xx_hal_crc.h.

#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)

Definition at line 180 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32H753xx HAL User Manual: Indicates whether or not default init value is used

Defines
Indicates whether or not default init value is used
CRC exported constants

Defines

#define | DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)

Define Documentation

#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)

Definition at line 192 of file stm32h7xx_hal_crc.h.

#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)

Definition at line 191 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32H753xx HAL User Manual: Polynomial sizes to configure the IP

Defines
Polynomial sizes to configure the IP
CRC exported constants

Defines

#define | CRC_POLYLENGTH_32B ((uint32_t)0x00000000U)
#define | CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)
#define | CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)
#define | CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)

Define Documentation

#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)

Definition at line 202 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000U)

Definition at line 201 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)

Definition at line 204 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)

Definition at line 203 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

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STM32H753xx HAL User Manual: CRC polynomial possible sizes actual definitions

Defines
CRC polynomial possible sizes actual definitions
CRC exported constants

Defines

#define | HAL_CRC_LENGTH_32B 32U
#define | HAL_CRC_LENGTH_16B 16U
#define | HAL_CRC_LENGTH_8B 8U
#define | HAL_CRC_LENGTH_7B 7U

Define Documentation

#define HAL_CRC_LENGTH_16B 16U

Definition at line 213 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define HAL_CRC_LENGTH_32B 32U

Definition at line 212 of file stm32h7xx_hal_crc.h.

#define HAL_CRC_LENGTH_7B 7U

Definition at line 215 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define HAL_CRC_LENGTH_8B 8U

Definition at line 214 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

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STM32H753xx HAL User Manual: CRC input buffer format

Defines
CRC input buffer format
CRC exported constants

Defines

#define | CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000U)
#define | CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001U)
#define | CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002U)
#define | CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003U)

Define Documentation

#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001U)

Definition at line 229 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002U)

Definition at line 230 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000U)

Definition at line 228 of file stm32h7xx_hal_crc.h.

#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003U)

Definition at line 231 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRC exported macros

Defines
CRC exported macros
CRC

Defines

#define | __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
Reset CRC handle state.
#define | __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
Reset CRC Data Register.
#define | __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
Set CRC INIT non-default value.
#define | __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
Stores a 32-bit data in the Independent Data(ID) register.
#define | __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
Returns the 32-bit data stored in the Independent Data(ID) register.

Define Documentation

#define __HAL_CRC_DR_RESET ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)

Reset CRC Data Register.

Parameters:
__HANDLE__,: CRC handle
Return values:
None.

Definition at line 256 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Calculate(), and HAL_CRC_DeInit().

#define __HAL_CRC_GET_IDR ( __HANDLE__ ) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)

Returns the 32-bit data stored in the Independent Data(ID) register.

Parameters:
__HANDLE__,: CRC handle
Return values:
32-bit value of the ID register

Definition at line 279 of file stm32h7xx_hal_crc.h.

#define __HAL_CRC_INITIALCRCVALUE_CONFIG | ( | __HANDLE__,
 |  | __INIT__
 | ) | ((__HANDLE__)->Instance->INIT = (__INIT__))

Set CRC INIT non-default value.

Parameters:
__HANDLE__ | : CRC handle
__INIT__ | : 32-bit initial value
Return values:
None.

Definition at line 264 of file stm32h7xx_hal_crc.h.

#define __HAL_CRC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)

Reset CRC handle state.

Parameters:
__HANDLE__,: CRC handle.
Return values:
None

Definition at line 249 of file stm32h7xx_hal_crc.h.

#define __HAL_CRC_SET_IDR | ( | __HANDLE__,
 |  | __VALUE__
 | ) | (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))

Stores a 32-bit data in the Independent Data(ID) register.

Parameters:
__HANDLE__,: CRC handle
__VALUE__,: 32-bit value to be stored in the ID register
Return values:
None

Definition at line 272 of file stm32h7xx_hal_crc.h.

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STM32H753xx HAL User Manual: CRC Private Types

CRC Private Types
CRC
Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRC Private Defines

CRC Private Defines
CRC
Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRC Private Variables

CRC Private Variables
CRC
Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRC Private Constants

CRC Private Constants
CRC
Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRC Private Macros

Defines
CRC Private Macros
CRC

Defines

#define | IS_DEFAULT_POLYNOMIAL(__DEFAULT__)
#define | IS_DEFAULT_INIT_VALUE(__VALUE__)
#define | IS_CRC_POL_LENGTH(__LENGTH__)
#define | IS_CRC_INPUTDATA_FORMAT(__FORMAT__)

Define Documentation

#define IS_CRC_INPUTDATA_FORMAT ( __FORMAT__ )
Value:
(((__FORMAT__) == CRC_INPUTDATA_FORMAT_BYTES) || \
                                                   ((__FORMAT__) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
                                                   ((__FORMAT__) == CRC_INPUTDATA_FORMAT_WORDS))

Definition at line 381 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

#define IS_CRC_POL_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == CRC_POLYLENGTH_32B) || \
                                           ((__LENGTH__) == CRC_POLYLENGTH_16B) || \
                                           ((__LENGTH__) == CRC_POLYLENGTH_8B)  || \
                                           ((__LENGTH__) == CRC_POLYLENGTH_7B))

Definition at line 377 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define IS_DEFAULT_INIT_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == DEFAULT_INIT_VALUE_ENABLE) || \
                                           ((__VALUE__) == DEFAULT_INIT_VALUE_DISABLE))

Definition at line 375 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

#define IS_DEFAULT_POLYNOMIAL ( __DEFAULT__ )
Value:
(((__DEFAULT__) == DEFAULT_POLYNOMIAL_ENABLE) || \
                                            ((__DEFAULT__) == DEFAULT_POLYNOMIAL_DISABLE))

Definition at line 373 of file stm32h7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32H753xx HAL User Manual: CRC Private Functions Prototypes

CRC Private Functions Prototypes
CRC
Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRC Private Functions

CRC Private Functions
CRC
Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRYP Exported Functions

CRYP Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CRYP_Init (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP according to the specified parameters in the CRYP_ConfigTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_CRYP_DeInit (CRYP_HandleTypeDef *hcryp)
De-Initializes the CRYP peripheral.
HAL_StatusTypeDef | HAL_CRYP_SetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Configure the CRYP according to the specified parameters in the CRYP_ConfigTypeDef.
HAL_StatusTypeDef | HAL_CRYP_GetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Get CRYP Configuration parameters in associated handle.
__weak void | HAL_CRYP_MspInit (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP MSP.
__weak void | HAL_CRYP_MspDeInit (CRYP_HandleTypeDef *hcryp)
DeInitializes CRYP MSP.

Detailed Description

CRYP Initialization and Configuration functions.

  ========================================================================================
     ##### Initialization, de-initialization and Set and Get configuration functions #####
  ========================================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the CRYP
      (+) DeInitialize the CRYP
      (+) Initialize the CRYP MSP
      (+) DeInitialize the CRYP MSP
      (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
          Parameters which are configured in This section are :
          (++) Key size
          (++) Data Type : 32,16, 8 or 1bit
          (++) AlgoMode : for CRYP1 IP
                 ECB and CBC in DES/TDES Standard
                 ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
      (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef

Function Documentation

HAL_StatusTypeDef HAL_CRYP_DeInit ( CRYP_HandleTypeDef * hcryp )

De-Initializes the CRYP peripheral.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 412 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, CRYP_PHASE_READY, CRYP_HandleTypeDef::CrypHeaderCount, CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, HAL_CRYP_MspDeInit(), HAL_CRYP_STATE_RESET, CRYP_HandleTypeDef::Phase, and CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_GetConfig | ( | CRYP_HandleTypeDef * | hcryp,
 |  | CRYP_ConfigTypeDef * | pConf
 | ) |  |

Get CRYP Configuration parameters in associated handle.

Parameters:
pConf,: pointer to a CRYP_ConfigTypeDef structure
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 519 of file stm32h7xx_hal_cryp.c.

References CRYP_ConfigTypeDef::Algorithm, CRYP_ConfigTypeDef::B0, CRYP_ConfigTypeDef::DataType, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, CRYP_HandleTypeDef::Init, CRYP_ConfigTypeDef::KeySize, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, and CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Init ( CRYP_HandleTypeDef * hcryp )

Initializes the CRYP according to the specified parameters in the CRYP_ConfigTypeDef and creates the associated handle.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 368 of file stm32h7xx_hal_cryp.c.

References CRYP_ConfigTypeDef::Algorithm, assert_param, CRYP_PHASE_READY, CRYP_ConfigTypeDef::DataType, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_NONE, HAL_CRYP_MspInit(), HAL_CRYP_STATE_READY, HAL_CRYP_STATE_RESET, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, IS_CRYP_ALGORITHM, IS_CRYP_DATATYPE, IS_CRYP_KEYSIZE, CRYP_ConfigTypeDef::KeySize, CRYP_HandleTypeDef::Lock, CRYP_HandleTypeDef::Phase, and CRYP_HandleTypeDef::State.

void HAL_CRYP_MspDeInit ( CRYP_HandleTypeDef * hcryp )

DeInitializes CRYP MSP.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
None

Definition at line 586 of file stm32h7xx_hal_cryp.c.

Referenced by HAL_CRYP_DeInit().

void HAL_CRYP_MspInit ( CRYP_HandleTypeDef * hcryp )

Initializes the CRYP MSP.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
None

Definition at line 570 of file stm32h7xx_hal_cryp.c.

Referenced by HAL_CRYP_Init().

HAL_StatusTypeDef HAL_CRYP_SetConfig | ( | CRYP_HandleTypeDef * | hcryp,
 |  | CRYP_ConfigTypeDef * | pConf
 | ) |  |

Configure the CRYP according to the specified parameters in the CRYP_ConfigTypeDef.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure
pConf,: pointer to a CRYP_ConfigTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 452 of file stm32h7xx_hal_cryp.c.

References CRYP_ConfigTypeDef::Algorithm, assert_param, CRYP_ConfigTypeDef::B0, CRYP_PHASE_READY, CRYP_ConfigTypeDef::DataType, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NONE, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, IS_CRYP_ALGORITHM, IS_CRYP_DATATYPE, IS_CRYP_KEYSIZE, CRYP_ConfigTypeDef::KeySize, CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, and CRYP_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Encrypt Decrypt functions

Functions
Encrypt Decrypt functions
CRYP Exported Functions

CRYP processing functions. More...

Functions

HAL_StatusTypeDef | HAL_CRYP_Encrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Encryption mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Decryption mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in interrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in itnterrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in DMA mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in DMA mode.

Detailed Description

CRYP processing functions.

  ==============================================================================
                      ##### Encrypt Decrypt  functions #####
  ==============================================================================
    [..]  This section provides API allowing to Encrypt/Decrypt Data following
          Standard DES/TDES or AES, and Algorithm configured by the user:
      (+) Standard DES/TDES only supported by CRYP1 IP, below list of Algorithm supported :
           (++)  Electronic Code Book(ECB)
           (++) Cipher Block Chaining (CBC)
      (+) Standard AES  supported by CRYP1 IP , list of Algorithm supported:
           (++) Electronic Code Book(ECB)
           (++) Cipher Block Chaining (CBC)
           (++) Counter mode (CTR)
           (++) Cipher Block Chaining (CBC)
           (++) Counter mode (CTR)
           (++) Galois/counter mode (GCM)
           (++) Counter with Cipher Block Chaining-Message(CCM)
    [..]  Three processing functions are available:
      (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
      (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
      (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA

Function Documentation

HAL_StatusTypeDef HAL_CRYP_Decrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output,
 |  | uint32_t | Timeout
 | ) |  |

Decryption mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input,: Pointer to the input buffer (ciphertext )
Size,: Length of the plaintext buffer in word.
Output,: Pointer to the output buffer(plaintext)
Timeout,: Specify Timeout value
Return values:
HAL status

Definition at line 756 of file stm32h7xx_hal_cryp.c.

References CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_Decrypt(), CRYP_AES_ECB, CRYP_AES_GCM, CRYP_AESCCM_Process(), CRYP_AESGCM_Process(), CRYP_DES_CBC, CRYP_DES_ECB, CRYP_OPERATINGMODE_DECRYPT, CRYP_PHASE_PROCESS, CRYP_TDES_CBC, CRYP_TDES_ECB, CRYP_TDES_Process(), CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_FIFO_FLUSH, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output
 | ) |  |

Decryption in DMA mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input,: Pointer to the input buffer (ciphertext )
Size,: Length of the plaintext buffer in word
Output,: Pointer to the output buffer(plaintext)
Return values:
HAL status

Definition at line 1206 of file stm32h7xx_hal_cryp.c.

References CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_Decrypt_DMA(), CRYP_AES_ECB, CRYP_AES_GCM, CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process_DMA(), CRYP_DES_CBC, CRYP_DES_ECB, CRYP_OPERATINGMODE_DECRYPT, CRYP_PHASE_PROCESS, CRYP_SetDMAConfig(), CRYP_TDES_CBC, CRYP_TDES_ECB, CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_FIFO_FLUSH, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Decrypt_IT | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output
 | ) |  |

Decryption in itnterrupt mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input,: Pointer to the input buffer (ciphertext )
Size,: Length of the plaintext buffer in word.
Output,: Pointer to the output buffer(plaintext)
Return values:
HAL status

Definition at line 977 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_Decrypt_IT(), CRYP_AES_ECB, CRYP_AES_GCM, CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_DES_CBC, CRYP_DES_ECB, CRYP_IT_INI, CRYP_IT_OUTI, CRYP_OPERATINGMODE_DECRYPT, CRYP_PHASE_PROCESS, CRYP_TDES_CBC, CRYP_TDES_ECB, CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_FIFO_FLUSH, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Encrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output,
 |  | uint32_t | Timeout
 | ) |  |

Encryption mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input,: Pointer to the input buffer (plaintext)
Size,: Length of the plaintext buffer in word.
Output,: Pointer to the output buffer(ciphertext)
Timeout,: Specify Timeout value
Return values:
HAL status

Definition at line 640 of file stm32h7xx_hal_cryp.c.

References CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_AES_Encrypt(), CRYP_AES_GCM, CRYP_AESCCM_Process(), CRYP_AESGCM_Process(), CRYP_DES_CBC, CRYP_DES_ECB, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_PROCESS, CRYP_TDES_CBC, CRYP_TDES_ECB, CRYP_TDES_Process(), CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_FIFO_FLUSH, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output
 | ) |  |

Encryption in DMA mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input,: Pointer to the input buffer (plaintext)
Size,: Length of the plaintext buffer in word.
Output,: Pointer to the output buffer(ciphertext)
Return values:
HAL status

Definition at line 1085 of file stm32h7xx_hal_cryp.c.

References CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_AES_GCM, CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process_DMA(), CRYP_DES_CBC, CRYP_DES_ECB, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_PROCESS, CRYP_SetDMAConfig(), CRYP_SetKey(), CRYP_TDES_CBC, CRYP_TDES_ECB, CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_FIFO_FLUSH, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Encrypt_IT | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output
 | ) |  |

Encryption in interrupt mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input,: Pointer to the input buffer (plaintext)
Size,: Length of the plaintext buffer in word
Output,: Pointer to the output buffer(ciphertext)
Return values:
HAL status

Definition at line 872 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_AES_Encrypt_IT(), CRYP_AES_GCM, CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_DES_CBC, CRYP_DES_ECB, CRYP_IT_INI, CRYP_IT_OUTI, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_PROCESS, CRYP_TDES_CBC, CRYP_TDES_ECB, CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_FIFO_FLUSH, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRYP IRQ handler management

Functions
CRYP IRQ handler management
CRYP Exported Functions

CRYP IRQ handler. More...

Functions

void | HAL_CRYP_IRQHandler (CRYP_HandleTypeDef *hcryp)
This function handles cryptographic interrupt request.
uint32_t | HAL_CRYP_GetError (CRYP_HandleTypeDef *hcryp)
Return the CRYP error code.
HAL_CRYP_STATETypeDef | HAL_CRYP_GetState (CRYP_HandleTypeDef *hcryp)
Returns the CRYP state.
__weak void | HAL_CRYP_InCpltCallback (CRYP_HandleTypeDef *hcryp)
Input FIFO transfer completed callback.
__weak void | HAL_CRYP_OutCpltCallback (CRYP_HandleTypeDef *hcryp)
Output FIFO transfer completed callback.
__weak void | HAL_CRYP_ErrorCallback (CRYP_HandleTypeDef *hcryp)
CRYP error callback.

Detailed Description

CRYP IRQ handler.

  ==============================================================================
                ##### CRYP IRQ handler management #####
  ==============================================================================
[..]  This section provides CRYP IRQ handler and callback functions.
      (+) HAL_CRYP_IRQHandler CRYP interrupt request
      (+) HAL_CRYP_InCpltCallback input data transfer complete callback
      (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
      (+) HAL_CRYP_ErrorCallback  CRYP error callback
      (+) HAL_CRYP_GetState return the CRYP state
      (+) HAL_CRYP_GetError return the CRYP error code

Function Documentation

void HAL_CRYP_ErrorCallback ( CRYP_HandleTypeDef * hcryp )

CRYP error callback.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
None

Definition at line 1424 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AES_ProcessData(), CRYP_DMAError(), CRYP_TDES_Process(), and CRYP_Workaround().

uint32_t HAL_CRYP_GetError ( CRYP_HandleTypeDef * hcryp )

Return the CRYP error code.

Parameters:
hcryp : pointer to a CRYP_HandleTypeDef structure that contains the configuration information for the CRYP IP
Return values:
CRYP error code

Definition at line 1370 of file stm32h7xx_hal_cryp.c.

References CRYP_HandleTypeDef::ErrorCode.

HAL_CRYP_STATETypeDef HAL_CRYP_GetState ( CRYP_HandleTypeDef * hcryp )

Returns the CRYP state.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
HAL state

Definition at line 1381 of file stm32h7xx_hal_cryp.c.

References CRYP_HandleTypeDef::State.

void HAL_CRYP_InCpltCallback ( CRYP_HandleTypeDef * hcryp )

Input FIFO transfer completed callback.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
None

Definition at line 1392 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AES_IT(), CRYP_DMAInCplt(), CRYP_GCMCCM_SetPayloadPhase_IT(), and CRYP_TDES_IT().

void HAL_CRYP_IRQHandler ( CRYP_HandleTypeDef * hcryp )

This function handles cryptographic interrupt request.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
None

Definition at line 1331 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_GET_IT, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CBC, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_AES_GCM, CRYP_AES_IT(), CRYP_DES_CBC, CRYP_DES_ECB, CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_IT_INI, CRYP_IT_OUTI, CRYP_PHASE_HEADER, CRYP_TDES_CBC, CRYP_TDES_ECB, CRYP_TDES_IT(), CRYP_HandleTypeDef::Init, and CRYP_HandleTypeDef::Instance.

void HAL_CRYP_OutCpltCallback ( CRYP_HandleTypeDef * hcryp )

Output FIFO transfer completed callback.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
None

Definition at line 1408 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AES_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_IT(), and CRYP_TDES_IT().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRYP Private Functions

Functions
CRYP Private Functions
CRYP | CRYP Exported Functions

Functions

static HAL_StatusTypeDef | CRYP_TDES_Process (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption in ECB/CBC Algorithm with DES/TDES standard.
static HAL_StatusTypeDef | CRYP_TDES_IT (CRYP_HandleTypeDef *hcryp)
CRYP block input/output data handling under interruption with DES/TDES standard.
static HAL_StatusTypeDef | CRYP_AES_Encrypt (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption in ECB/CBC & CTR Algorithm with AES Standard.
static HAL_StatusTypeDef | CRYP_AES_Encrypt_IT (CRYP_HandleTypeDef *hcryp)
Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.
static HAL_StatusTypeDef | CRYP_AES_Decrypt (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Decryption in ECB/CBC & CTR mode with AES Standard.
static HAL_StatusTypeDef | CRYP_AES_Decrypt_IT (CRYP_HandleTypeDef *hcryp)
Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.
static HAL_StatusTypeDef | CRYP_AES_Decrypt_DMA (CRYP_HandleTypeDef *hcryp)
Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode.
static void | CRYP_DMAInCplt (DMA_HandleTypeDef *hdma)
DMA CRYP input data process complete callback.
static void | CRYP_DMAOutCplt (DMA_HandleTypeDef *hdma)
DMA CRYP output data process complete callback.
static void | CRYP_DMAError (DMA_HandleTypeDef *hdma)
DMA CRYP communication error callback.
static void | CRYP_SetDMAConfig (CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
Set the DMA configuration and start the DMA transfer.
static HAL_StatusTypeDef | CRYP_AES_ProcessData (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Process Data: Write Input data in polling mode and used in AES functions.
static HAL_StatusTypeDef | CRYP_AES_IT (CRYP_HandleTypeDef *hcryp)
Handle CRYP block input/output data handling under interruption.
static void | CRYP_SetKey (CRYP_HandleTypeDef *hcryp, uint32_t *Key, uint32_t KeySize)
Writes Key in Key registers.
static HAL_StatusTypeDef | CRYP_AESGCM_Process (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG.
static HAL_StatusTypeDef | CRYP_AESGCM_Process_IT (CRYP_HandleTypeDef *hcryp)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode.
static HAL_StatusTypeDef | CRYP_AESGCM_Process_DMA (CRYP_HandleTypeDef *hcryp)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA.
static HAL_StatusTypeDef | CRYP_AESCCM_Process (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
AES CCM encryption/decryption processing in polling mode.
static HAL_StatusTypeDef | CRYP_AESCCM_Process_IT (CRYP_HandleTypeDef *hcryp)
AES CCM encryption/decryption process in interrupt mode.
static HAL_StatusTypeDef | CRYP_AESCCM_Process_DMA (CRYP_HandleTypeDef *hcryp)
AES CCM encryption/decryption process in DMA mode.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetPayloadPhase_IT (CRYP_HandleTypeDef *hcryp)
Sets the payload phase in iterrupt mode.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetHeaderPhase (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Sets the header phase in polling mode.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetHeaderPhase_DMA (CRYP_HandleTypeDef *hcryp)
Sets the header phase when using DMA in process.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetHeaderPhase_IT (CRYP_HandleTypeDef *hcryp)
Sets the header phase in interrupt mode.
static void | CRYP_Workaround (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Workaround used for GCM/CCM mode.
static HAL_StatusTypeDef | CRYP_WaitOnIFEMFlag (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.
static HAL_StatusTypeDef | CRYP_WaitOnBUSYFlag (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.
static HAL_StatusTypeDef | CRYP_WaitOnOFNEFlag (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.

Function Documentation

static HAL_StatusTypeDef CRYP_AES_Decrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Decryption in ECB/CBC & CTR mode with AES Standard.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure
Timeout,: Specify Timeout value
Return values:
HAL status

Definition at line 1667 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_AES_ProcessData(), CRYP_PHASE_PROCESS, CRYP_SetKey(), CRYP_WaitOnBUSYFlag(), CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt().

static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA ( CRYP_HandleTypeDef * hcryp ) [static]

Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 1818 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_FLAG_BUSY, CRYP_PHASE_PROCESS, CRYP_SetDMAConfig(), CRYP_SetKey(), CRYP_TIMEOUT_KEYPREPARATION, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt_DMA().

static HAL_StatusTypeDef CRYP_AES_Decrypt_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 1740 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_FLAG_BUSY, CRYP_IT_INI, CRYP_IT_OUTI, CRYP_PHASE_PROCESS, CRYP_SetKey(), CRYP_TIMEOUT_KEYPREPARATION, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt_IT().

static HAL_StatusTypeDef CRYP_AES_Encrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Encryption in ECB/CBC & CTR Algorithm with AES Standard.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure
Timeout,: specify Timeout value
Return values:
HAL status

Definition at line 1580 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_ECB, CRYP_AES_ProcessData(), CRYP_PHASE_PROCESS, CRYP_SetKey(), CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Encrypt().

static HAL_StatusTypeDef CRYP_AES_Encrypt_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 1623 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_ECB, CRYP_IT_INI, CRYP_IT_OUTI, CRYP_PHASE_PROCESS, CRYP_SetKey(), HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Encrypt_IT().

static HAL_StatusTypeDef CRYP_AES_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Handle CRYP block input/output data handling under interruption.

Note:
The function is called under interruption only, once interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
HAL status

Definition at line 2062 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_DISABLE_IT, CRYP_FLAG_IFNF, CRYP_FLAG_OFNE, CRYP_IT_INI, CRYP_IT_OUTI, CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_InCpltCallback(), HAL_CRYP_OutCpltCallback(), HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Instance, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_IRQHandler().

static HAL_StatusTypeDef CRYP_AES_ProcessData | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Process Data: Write Input data in polling mode and used in AES functions.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Timeout,: Specify Timeout value
Return values:
None

Definition at line 2000 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, CRYP_FLAG_IFNF, CRYP_FLAG_OFNE, CRYP_WaitOnOFNEFlag(), CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Instance, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Encrypt(), CRYP_AESCCM_Process(), and CRYP_AESGCM_Process().

static HAL_StatusTypeDef CRYP_AESCCM_Process | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

AES CCM encryption/decryption processing in polling mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 2491 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::B0, CRYP_AES_ProcessData(), CRYP_CCM_CTR1_0, CRYP_CCM_CTR1_1, CRYP_CCM_CTR1_2, CRYP_DATATYPE_16B, CRYP_DATATYPE_1B, CRYP_DATATYPE_8B, CRYP_GCMCCM_SetHeaderPhase(), CRYP_PHASE_INIT, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, CRYP_SET_PHASE, CRYP_SetKey(), CRYP_Workaround(), CRYP_HandleTypeDef::CrypHeaderCount, CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, CRYP_ConfigTypeDef::DataType, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, HAL_GetTick(), CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pKey, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt(), and HAL_CRYP_Encrypt().

static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA ( CRYP_HandleTypeDef * hcryp ) [static]

AES CCM encryption/decryption process in DMA mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 2757 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::B0, CRYP_CCM_CTR1_0, CRYP_CCM_CTR1_1, CRYP_CCM_CTR1_2, CRYP_DATATYPE_16B, CRYP_DATATYPE_1B, CRYP_DATATYPE_8B, CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_PHASE_INIT, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, CRYP_SET_PHASE, CRYP_SetDMAConfig(), CRYP_SetKey(), CRYP_TIMEOUT_GCMCCMINITPHASE, CRYP_HandleTypeDef::CrypHeaderCount, CRYP_ConfigTypeDef::DataType, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pKey, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt_DMA(), and HAL_CRYP_Encrypt_DMA().

static HAL_StatusTypeDef CRYP_AESCCM_Process_IT ( CRYP_HandleTypeDef * hcryp ) [static]

AES CCM encryption/decryption process in interrupt mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 2667 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_ConfigTypeDef::B0, CRYP_CCM_CTR1_0, CRYP_CCM_CTR1_1, CRYP_CCM_CTR1_2, CRYP_DATATYPE_16B, CRYP_DATATYPE_1B, CRYP_DATATYPE_8B, CRYP_IT_INI, CRYP_PHASE_HEADER, CRYP_PHASE_INIT, CRYP_SET_PHASE, CRYP_SetKey(), CRYP_TIMEOUT_GCMCCMINITPHASE, CRYP_HandleTypeDef::CrypHeaderCount, CRYP_ConfigTypeDef::DataType, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, CRYP_ConfigTypeDef::pKey, and CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt_IT(), and HAL_CRYP_Encrypt_IT().

static HAL_StatusTypeDef CRYP_AESGCM_Process | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Encryption/Decryption process in AES GCM mode and prepare the authentication TAG.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 2181 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_AES_ProcessData(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_PHASE_INIT, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, CRYP_SET_PHASE, CRYP_SetKey(), CRYP_Workaround(), CRYP_HandleTypeDef::CrypHeaderCount, CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, HAL_GetTick(), CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt(), and HAL_CRYP_Encrypt().

static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA ( CRYP_HandleTypeDef * hcryp ) [static]

Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 2390 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_PHASE_INIT, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, CRYP_SET_PHASE, CRYP_SetDMAConfig(), CRYP_SetKey(), CRYP_TIMEOUT_GCMCCMINITPHASE, CRYP_HandleTypeDef::CrypHeaderCount, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt_DMA(), and HAL_CRYP_Encrypt_DMA().

static HAL_StatusTypeDef CRYP_AESGCM_Process_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 2325 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_IT_INI, CRYP_PHASE_HEADER, CRYP_PHASE_INIT, CRYP_SET_PHASE, CRYP_SetKey(), CRYP_TIMEOUT_GCMCCMINITPHASE, CRYP_HandleTypeDef::CrypHeaderCount, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_ConfigTypeDef::KeySize, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, and CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt_IT(), and HAL_CRYP_Encrypt_IT().

static void CRYP_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA CRYP communication error callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1943 of file stm32h7xx_hal_cryp.c.

References CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_DMA, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, and CRYP_HandleTypeDef::State.

Referenced by CRYP_SetDMAConfig().

static void CRYP_DMAInCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA CRYP input data process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1898 of file stm32h7xx_hal_cryp.c.

References HAL_CRYP_InCpltCallback(), and CRYP_HandleTypeDef::Instance.

Referenced by CRYP_SetDMAConfig().

static void CRYP_DMAOutCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA CRYP output data process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1915 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_GCM, HAL_CRYP_OutCpltCallback(), HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, and CRYP_HandleTypeDef::State.

Referenced by CRYP_SetDMAConfig().

static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Sets the header phase in polling mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module(Header & HeaderSize)
Timeout,: Timeout value
Return values:
state

Definition at line 3018 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_PHASE_HEADER, CRYP_SET_PHASE, CRYP_WaitOnBUSYFlag(), CRYP_WaitOnIFEMFlag(), CRYP_HandleTypeDef::CrypHeaderCount, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, and CRYP_HandleTypeDef::State.

Referenced by CRYP_AESCCM_Process(), and CRYP_AESGCM_Process().

static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA ( CRYP_HandleTypeDef * hcryp ) [static]

Sets the header phase when using DMA in process.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module(Header & HeaderSize)
Return values:
None

Definition at line 3143 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_FLAG_BUSY, CRYP_FLAG_IFEM, CRYP_PHASE_HEADER, CRYP_SET_PHASE, CRYP_TIMEOUT_GCMCCMHEADERPHASE, CRYP_HandleTypeDef::CrypHeaderCount, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, and CRYP_HandleTypeDef::State.

Referenced by CRYP_AESCCM_Process_DMA(), and CRYP_AESGCM_Process_DMA().

static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Sets the header phase in interrupt mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module(Header & HeaderSize)
Return values:
None

Definition at line 3289 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_DISABLE_IT, __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_IT_INI, CRYP_IT_OUTI, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, CRYP_SET_PHASE, CRYP_HandleTypeDef::CrypHeaderCount, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, and CRYP_HandleTypeDef::Phase.

Referenced by HAL_CRYP_IRQHandler().

static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Sets the payload phase in iterrupt mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
state

Definition at line 2886 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_DISABLE_IT, CRYP_FLAG_OFNE, CRYP_IT_INI, CRYP_IT_OUTI, CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, HAL_CRYP_InCpltCallback(), HAL_CRYP_OutCpltCallback(), HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Instance, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_IRQHandler().

static void CRYP_SetDMAConfig | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | inputaddr,
 |  | uint16_t | Size,
 |  | uint32_t | outputaddr
 | ) |  | [static]

Set the DMA configuration and start the DMA transfer.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
inputaddr,: address of the input buffer
Size,: size of the input buffer, must be a multiple of 16.
outputaddr,: address of the output buffer
Return values:
None

Definition at line 1966 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_ENABLE, CRYP_DMAError(), CRYP_DMAInCplt(), CRYP_DMAOutCplt(), HAL_DMA_Start_IT(), CRYP_HandleTypeDef::hdmain, CRYP_HandleTypeDef::hdmaout, CRYP_HandleTypeDef::Instance, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by CRYP_AES_Decrypt_DMA(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process_DMA(), HAL_CRYP_Decrypt_DMA(), and HAL_CRYP_Encrypt_DMA().

static void CRYP_SetKey | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Key,
 |  | uint32_t | KeySize
 | ) |  | [static]

Writes Key in Key registers.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Key,: Pointer to Key buffer
KeySize,: Size of Key
Return values:
None

Definition at line 2140 of file stm32h7xx_hal_cryp.c.

References CRYP_KEYSIZE_128B, CRYP_KEYSIZE_192B, CRYP_KEYSIZE_256B, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, and CRYP_ConfigTypeDef::pKey.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), and HAL_CRYP_Encrypt_DMA().

static HAL_StatusTypeDef CRYP_TDES_IT ( CRYP_HandleTypeDef * hcryp ) [static]

CRYP block input/output data handling under interruption with DES/TDES standard.

Note:
The function is called under interruption only, once interruptions have been enabled by CRYP_Decrypt_IT() and CRYP_Encrypt_IT().
Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
HAL status

Definition at line 1513 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_DISABLE_IT, __HAL_CRYP_GET_FLAG, __HAL_CRYP_GET_IT, CRYP_FLAG_INRIS, CRYP_FLAG_OUTRIS, CRYP_IT_INI, CRYP_IT_OUTI, CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_InCpltCallback(), HAL_CRYP_OutCpltCallback(), HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Instance, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_IRQHandler().

static HAL_StatusTypeDef CRYP_TDES_Process | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Encryption in ECB/CBC Algorithm with DES/TDES standard.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Timeout,: Timeout value
Return values:
HAL status

Definition at line 1449 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_FLAG_IFNF, CRYP_FLAG_OFNE, CRYP_WaitOnOFNEFlag(), CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Instance, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt(), and HAL_CRYP_Encrypt().

static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 3633 of file stm32h7xx_hal_cryp.c.

References CRYP_FLAG_BUSY, HAL_GetTick(), and CRYP_HandleTypeDef::Instance.

Referenced by CRYP_AES_Decrypt(), CRYP_GCMCCM_SetHeaderPhase(), and CRYP_Workaround().

static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 3606 of file stm32h7xx_hal_cryp.c.

References CRYP_FLAG_IFEM, HAL_GetTick(), and CRYP_HandleTypeDef::Instance.

Referenced by CRYP_GCMCCM_SetHeaderPhase().

static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 3662 of file stm32h7xx_hal_cryp.c.

References CRYP_FLAG_OFNE, HAL_GetTick(), and CRYP_HandleTypeDef::Instance.

Referenced by CRYP_AES_ProcessData(), CRYP_TDES_Process(), and CRYP_Workaround().

static void CRYP_Workaround | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Workaround used for GCM/CCM mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Timeout,: Timeout value
Return values:
None

Definition at line 3355 of file stm32h7xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::Algorithm, CRYP_ConfigTypeDef::B0, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_GCM, CRYP_FLAG_OFNE, CRYP_OPERATINGMODE_DECRYPT, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_FINAL, CRYP_PHASE_HEADER, CRYP_WaitOnBUSYFlag(), CRYP_WaitOnOFNEFlag(), CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

Referenced by CRYP_AESCCM_Process(), and CRYP_AESGCM_Process().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRYP Exported Types

Data Structures | Enumerations
CRYP Exported Types
CRYP

Data Structures

struct | CRYP_ConfigTypeDef
CRYP Init Structure definition. More...
struct | CRYP_HandleTypeDef
CRYP handle Structure definition. More...

Enumerations

enum | HAL_CRYP_STATETypeDef { HAL_CRYP_STATE_RESET = 0x00U, HAL_CRYP_STATE_READY = 0x01U, HAL_CRYP_STATE_BUSY = 0x02U }
CRYP State Structure definition. More...

Enumeration Type Documentation

enum HAL_CRYP_STATETypeDef

CRYP State Structure definition.

Enumerator:
HAL_CRYP_STATE_RESET

CRYP not yet initialized or disabled

HAL_CRYP_STATE_READY

CRYP initialized and ready for use

HAL_CRYP_STATE_BUSY

CRYP BUSY, internal processing is ongoing

Definition at line 91 of file stm32h7xx_hal_cryp.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRYP_ConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRYP_ConfigTypeDef Struct Reference
CRYP Exported Types

CRYP Init Structure definition. More...

#include <stm32h7xx_hal_cryp.h>

Data Fields

uint32_t | DataType
uint32_t | KeySize
uint32_t * | pKey
uint32_t * | pInitVect
uint32_t | Algorithm
uint32_t * | Header
uint32_t | HeaderSize
uint32_t * | B0

Detailed Description

CRYP Init Structure definition.

Definition at line 67 of file stm32h7xx_hal_cryp.h.

Field Documentation

uint32_t CRYP_ConfigTypeDef::Algorithm

DES/ TDES Algorithm ECB/CBC AES Algorithm ECB/CBC/CTR/GCM or CCM This parameter can be a value of CRYP Algorithm Mode

Definition at line 76 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_DMAOutCplt(), CRYP_Workaround(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_Init(), HAL_CRYP_IRQHandler(), and HAL_CRYP_SetConfig().

uint32_t* CRYP_ConfigTypeDef::B0

B0 is first authentication block used only in AES CCM mode

Definition at line 83 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_Workaround(), HAL_CRYP_GetConfig(), HAL_CRYP_SetConfig(), and HAL_CRYPEx_AESCCM_GenerateAuthTAG().

uint32_t CRYP_ConfigTypeDef::DataType

32-bit data, 16-bit data, 8-bit data or 1-bit string. This parameter can be a value of CRYP Data Type

Definition at line 69 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_Init(), HAL_CRYP_SetConfig(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

uint32_t* CRYP_ConfigTypeDef::Header

used only in AES GCM and CCM Algorithm for authentication, GCM : also known as Additional Authentication Data CCM : named B1 composed of the associated data length and Associated Data.

Definition at line 79 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), HAL_CRYP_GetConfig(), and HAL_CRYP_SetConfig().

uint32_t CRYP_ConfigTypeDef::HeaderSize

The size of header buffer in word

Definition at line 82 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_SetConfig(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

uint32_t CRYP_ConfigTypeDef::KeySize

Used only in AES mode : 128, 192 or 256 bit key length in CRYP1. This parameter can be a value of CRYP Key Size

Definition at line 71 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_GetConfig(), HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

uint32_t* CRYP_ConfigTypeDef::pInitVect

The initialization vector used also as initialization counter in CTR mode

Definition at line 74 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), and HAL_CRYP_SetConfig().

uint32_t* CRYP_ConfigTypeDef::pKey

The key used for encryption/decryption

Definition at line 73 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_SetKey(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), and HAL_CRYP_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_cryp.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRYP_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRYP_HandleTypeDef Struct Reference
CRYP Exported Types

CRYP handle Structure definition. More...

#include <stm32h7xx_hal_cryp.h>

Data Fields

CRYP_TypeDef * | Instance
CRYP_ConfigTypeDef Init
uint32_t * | pCrypInBuffPtr
uint32_t * | pCrypOutBuffPtr
__IO uint16_t | CrypHeaderCount
__IO uint16_t | CrypInCount
__IO uint16_t | CrypOutCount
uint16_t | Size
uint32_t | Phase
DMA_HandleTypeDef * hdmain
DMA_HandleTypeDef * hdmaout
HAL_LockTypeDef | Lock
__IO HAL_CRYP_STATETypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

CRYP handle Structure definition.

Definition at line 103 of file stm32h7xx_hal_cryp.h.

Field Documentation

__IO uint16_t CRYP_HandleTypeDef::CrypHeaderCount

Counter of header data

Definition at line 114 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), and HAL_CRYP_DeInit().

__IO uint16_t CRYP_HandleTypeDef::CrypInCount

Counter of input data

Definition at line 116 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Encrypt(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESGCM_Process(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), CRYP_TDES_Process(), CRYP_Workaround(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_DeInit(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

__IO uint16_t CRYP_HandleTypeDef::CrypOutCount

Counter of output data

Definition at line 118 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Encrypt(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESGCM_Process(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), CRYP_TDES_Process(), CRYP_Workaround(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_DeInit(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

__IO uint32_t CRYP_HandleTypeDef::ErrorCode

CRYP peripheral error code

Definition at line 132 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAError(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_TDES_IT(), CRYP_TDES_Process(), CRYP_Workaround(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_GetError(), HAL_CRYP_Init(), HAL_CRYP_SetConfig(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

DMA_HandleTypeDef* CRYP_HandleTypeDef::hdmain

CRYP In DMA handle parameters

Definition at line 124 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_SetDMAConfig().

DMA_HandleTypeDef* CRYP_HandleTypeDef::hdmaout

CRYP Out DMA handle parameters

Definition at line 126 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_SetDMAConfig().

CRYP_ConfigTypeDef CRYP_HandleTypeDef::Init

CRYP required parameters

Definition at line 108 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_SetKey(), CRYP_Workaround(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_Init(), HAL_CRYP_IRQHandler(), HAL_CRYP_SetConfig(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

CRYP_TypeDef* CRYP_HandleTypeDef::Instance

CRYP registers base address

Definition at line 106 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAInCplt(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_SetDMAConfig(), CRYP_SetKey(), CRYP_TDES_IT(), CRYP_TDES_Process(), CRYP_WaitOnBUSYFlag(), CRYP_WaitOnIFEMFlag(), CRYP_WaitOnOFNEFlag(), CRYP_Workaround(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_Init(), HAL_CRYP_IRQHandler(), HAL_CRYP_SetConfig(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

HAL_LockTypeDef CRYP_HandleTypeDef::Lock

CRYP locking object

Definition at line 128 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Init().

uint32_t* CRYP_HandleTypeDef::pCrypInBuffPtr

Pointer to CRYP processing (encryption, decryption,...) buffer

Definition at line 110 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_DMA(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), CRYP_TDES_Process(), CRYP_Workaround(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

uint32_t* CRYP_HandleTypeDef::pCrypOutBuffPtr

Pointer to CRYP processing (encryption, decryption,...) buffer

Definition at line 112 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_DMA(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), CRYP_TDES_Process(), CRYP_Workaround(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

uint32_t CRYP_HandleTypeDef::Phase

CRYP peripheral phase

Definition at line 122 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_DeInit(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_Init(), HAL_CRYP_SetConfig(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

uint16_t CRYP_HandleTypeDef::Size

length of input data in word

Definition at line 120 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), CRYP_TDES_Process(), CRYP_Workaround(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

__IO HAL_CRYP_STATETypeDef CRYP_HandleTypeDef::State

CRYP peripheral state

Definition at line 130 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAError(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), CRYP_TDES_Process(), CRYP_Workaround(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_DeInit(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_GetState(), HAL_CRYP_Init(), HAL_CRYP_SetConfig(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_cryp.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRYP Error Definition

Defines
CRYP Error Definition
CRYP Exported Constants

Defines

#define | HAL_CRYP_ERROR_NONE 0x00000000U
#define | HAL_CRYP_ERROR_WRITE 0x00000001U
#define | HAL_CRYP_ERROR_READ 0x00000002U
#define | HAL_CRYP_ERROR_DMA 0x00000004U
#define | HAL_CRYP_ERROR_BUSY 0x00000008U
#define | HAL_CRYP_ERROR_TIMEOUT 0x00000010U
#define | HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U
#define | HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U

Define Documentation

#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U

Sequence are not respected only for GCM or CCM

Definition at line 156 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define HAL_CRYP_ERROR_BUSY 0x00000008U

Busy flag error

Definition at line 153 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_TDES_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_SetConfig(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define HAL_CRYP_ERROR_DMA 0x00000004U

DMA error

Definition at line 152 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_DMAError().

#define HAL_CRYP_ERROR_NONE 0x00000000U

No error

Definition at line 149 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U

Not supported mode

Definition at line 155 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

#define HAL_CRYP_ERROR_READ 0x00000002U

Read error

Definition at line 151 of file stm32h7xx_hal_cryp.h.

#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U

Timeout error

Definition at line 154 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_TDES_Process(), CRYP_Workaround(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define HAL_CRYP_ERROR_WRITE 0x00000001U

Write error

Definition at line 150 of file stm32h7xx_hal_cryp.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRYP Algorithm Mode

Defines
CRYP Algorithm Mode
CRYP Exported Constants

Defines

#define | CRYP_DES_ECB CRYP_CR_ALGOMODE_DES_ECB
#define | CRYP_DES_CBC CRYP_CR_ALGOMODE_DES_CBC
#define | CRYP_TDES_ECB CRYP_CR_ALGOMODE_TDES_ECB
#define | CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC
#define | CRYP_AES_ECB CRYP_CR_ALGOMODE_AES_ECB
#define | CRYP_AES_CBC CRYP_CR_ALGOMODE_AES_CBC
#define | CRYP_AES_CTR CRYP_CR_ALGOMODE_AES_CTR
#define | CRYP_AES_GCM CRYP_CR_ALGOMODE_AES_GCM
#define | CRYP_AES_CCM CRYP_CR_ALGOMODE_AES_CCM

Define Documentation

#define CRYP_AES_CBC CRYP_CR_ALGOMODE_AES_CBC

Definition at line 171 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

#define CRYP_AES_CCM CRYP_CR_ALGOMODE_AES_CCM

Definition at line 174 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_Workaround(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

#define CRYP_AES_CTR CRYP_CR_ALGOMODE_AES_CTR

Definition at line 172 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_Workaround(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

#define CRYP_AES_ECB CRYP_CR_ALGOMODE_AES_ECB

Definition at line 170 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

#define CRYP_AES_GCM CRYP_CR_ALGOMODE_AES_GCM

Definition at line 173 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_DMAOutCplt(), CRYP_Workaround(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

#define CRYP_DES_CBC CRYP_CR_ALGOMODE_DES_CBC

Definition at line 167 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

#define CRYP_DES_ECB CRYP_CR_ALGOMODE_DES_ECB

Definition at line 166 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

#define CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC

Definition at line 169 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

#define CRYP_TDES_ECB CRYP_CR_ALGOMODE_TDES_ECB

Definition at line 168 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRYP Key Size

Defines
CRYP Key Size
CRYP Exported Constants

Defines

#define | CRYP_KEYSIZE_128B 0x00000000U
#define | CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
#define | CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1

Define Documentation

#define CRYP_KEYSIZE_128B 0x00000000U

Definition at line 184 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_SetKey().

#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0

Definition at line 185 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_SetKey().

#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1

Definition at line 186 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_SetKey().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRYP Data Type

Defines
CRYP Data Type
CRYP Exported Constants

Defines

#define | CRYP_DATATYPE_32B 0x00000000U
#define | CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
#define | CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
#define | CRYP_DATATYPE_1B CRYP_CR_DATATYPE

Define Documentation

#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0

Definition at line 197 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE

Definition at line 199 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define CRYP_DATATYPE_32B 0x00000000U

Definition at line 196 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1

Definition at line 198 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRYP Interrupt

Defines
CRYP Interrupt
CRYP Exported Constants

Defines

#define | CRYP_IT_INI CRYP_IMSCR_INIM
#define | CRYP_IT_OUTI CRYP_IMSCR_OUTIM

Define Documentation

#define CRYP_IT_INI CRYP_IMSCR_INIM

Input FIFO Interrupt

Definition at line 209 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

#define CRYP_IT_OUTI CRYP_IMSCR_OUTIM

Output FIFO Interrupt

Definition at line 210 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRYP Flags

Defines
CRYP Flags
CRYP Exported Constants

Defines

#define | CRYP_FLAG_IFEM CRYP_SR_IFEM
#define | CRYP_FLAG_IFNF CRYP_SR_IFNF
#define | CRYP_FLAG_OFNE CRYP_SR_OFNE
#define | CRYP_FLAG_OFFU CRYP_SR_OFFU
#define | CRYP_FLAG_BUSY CRYP_SR_BUSY
#define | CRYP_FLAG_OUTRIS 0x01000002U
#define | CRYP_FLAG_INRIS 0x01000001U

Define Documentation

#define CRYP_FLAG_BUSY CRYP_SR_BUSY

The CRYP core is currently processing a block of data or a key preparation (for AES decryption).

Definition at line 225 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_GCMCCM_SetHeaderPhase_DMA(), and CRYP_WaitOnBUSYFlag().

#define CRYP_FLAG_IFEM CRYP_SR_IFEM

Input FIFO is empty

Definition at line 221 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_GCMCCM_SetHeaderPhase_DMA(), and CRYP_WaitOnIFEMFlag().

#define CRYP_FLAG_IFNF CRYP_SR_IFNF

Input FIFO is not Full

Definition at line 222 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_AES_ProcessData(), and CRYP_TDES_Process().

#define CRYP_FLAG_INRIS 0x01000001U

Input FIFO service raw interrupt status

Definition at line 229 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_TDES_IT().

#define CRYP_FLAG_OFFU CRYP_SR_OFFU

Output FIFO is Full

Definition at line 224 of file stm32h7xx_hal_cryp.h.

#define CRYP_FLAG_OFNE CRYP_SR_OFNE

Output FIFO is not empty

Definition at line 223 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_Process(), CRYP_WaitOnOFNEFlag(), CRYP_Workaround(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define CRYP_FLAG_OUTRIS 0x01000002U

Output FIFO service raw interrupt status

Definition at line 228 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_TDES_IT().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRYP Exported Macros

Defines
CRYP Exported Macros
CRYP

Defines

#define | __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
Enable/Disable the CRYP peripheral.
#define | __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)
#define | CRYP_FLAG_MASK 0x0000001FU
Check whether the specified CRYP status flag is set or not.
#define | __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__)
#define | __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified CRYP interrupt is set or not.
#define | __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
Enable the CRYP interrupt.
#define | __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
Disable the CRYP interrupt.

Define Documentation

#define __HAL_CRYP_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)

Definition at line 252 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Encrypt(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_TDES_IT(), CRYP_TDES_Process(), CRYP_Workaround(), HAL_CRYP_DeInit(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define __HAL_CRYP_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))

Disable the CRYP interrupt.

Parameters:
__HANDLE__,: specifies the CRYP handle.
__INTERRUPT__,: CRYP Interrupt. This parameter can be one of the following values for CRYP: @ CRYP_IT_INI : Input FIFO service interrupt mask. @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
Return values:
None

Definition at line 305 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), and CRYP_TDES_IT().

#define __HAL_CRYP_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)

Enable/Disable the CRYP peripheral.

Parameters:
__HANDLE__,: specifies the CRYP handle.
Return values:
None

Definition at line 251 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_SetDMAConfig(), CRYP_TDES_Process(), CRYP_Workaround(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_IT(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define __HAL_CRYP_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))

Enable the CRYP interrupt.

Parameters:
__HANDLE__,: specifies the CRYP handle.
__INTERRUPT__,: CRYP Interrupt. This parameter can be one of the following values for CRYP: @ CRYP_IT_INI : Input FIFO service interrupt mask. @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
Return values:
None

Definition at line 293 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase_IT(), HAL_CRYP_Decrypt_IT(), and HAL_CRYP_Encrypt_IT().

#define __HAL_CRYP_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
                                                 ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))

Definition at line 269 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_TDES_IT().

#define __HAL_CRYP_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified CRYP interrupt is set or not.

Parameters:
__HANDLE__,: specifies the CRYP handle.
__INTERRUPT__,: specifies the interrupt to check. This parameter can be one of the following values for CRYP:
  • CRYP_IT_INI: Input FIFO service masked interrupt status
  • CRYP_IT_OUTI: Output FIFO service masked interrupt status
Return values:
The state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 281 of file stm32h7xx_hal_cryp.h.

Referenced by CRYP_TDES_IT(), and HAL_CRYP_IRQHandler().

#define CRYP_FLAG_MASK 0x0000001FU

Check whether the specified CRYP status flag is set or not.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be one of the following values for CRYP:
  • CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data or a key preparation (for AES decryption).
  • CRYP_FLAG_IFEM: Input FIFO is empty
  • CRYP_FLAG_IFNF: Input FIFO is not full
  • CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
  • CRYP_FLAG_OFNE: Output FIFO is not empty
  • CRYP_FLAG_OFFU: Output FIFO is full
  • CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
Return values:
The state of __FLAG__ (TRUE or FALSE).

Definition at line 267 of file stm32h7xx_hal_cryp.h.

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STM32H753xx HAL User Manual: CRYP Private macros to check input parameters

Defines
CRYP Private macros to check input parameters
CRYP Private Macros

Defines

#define | IS_CRYP_ALGORITHM(ALGORITHM)
#define | IS_CRYP_KEYSIZE(KEYSIZE)
#define | IS_CRYP_DATATYPE(DATATYPE)

Define Documentation

#define IS_CRYP_ALGORITHM ( ALGORITHM )
Value:
(((ALGORITHM) == CRYP_DES_ECB)   || \
                                   ((ALGORITHM)  == CRYP_DES_CBC)   || \
                                   ((ALGORITHM)  == CRYP_TDES_ECB)  || \
                                   ((ALGORITHM)  == CRYP_TDES_CBC)  || \
                                   ((ALGORITHM)  == CRYP_AES_ECB)   || \
                                   ((ALGORITHM)  == CRYP_AES_CBC)   || \
                                   ((ALGORITHM)  == CRYP_AES_CTR)   || \
                                   ((ALGORITHM)  == CRYP_AES_GCM)   || \
                                   ((ALGORITHM)  == CRYP_AES_CCM))

Definition at line 378 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

#define IS_CRYP_DATATYPE ( DATATYPE )
Value:
(((DATATYPE) == CRYP_DATATYPE_32B)   || \
                                   ((DATATYPE) == CRYP_DATATYPE_16B) || \
                                   ((DATATYPE) == CRYP_DATATYPE_8B) || \
                                   ((DATATYPE) == CRYP_DATATYPE_1B))

Definition at line 392 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

#define IS_CRYP_KEYSIZE ( KEYSIZE )
Value:
(((KEYSIZE) == CRYP_KEYSIZE_128B)   || \
                                 ((KEYSIZE) == CRYP_KEYSIZE_192B)   || \
                                 ((KEYSIZE) == CRYP_KEYSIZE_256B))

Definition at line 388 of file stm32h7xx_hal_cryp.h.

Referenced by HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

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STM32H753xx HAL User Manual: CRYP Private Macros

Modules | Defines
CRYP Private Macros
CRYP

Modules

CRYP Private macros to check input parameters

Defines

#define | CRYP_SET_PHASE(__HANDLE__, __PHASE__)
#define | HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)

Define Documentation

#define CRYP_SET_PHASE | ( | __HANDLE__,
 |  | __PHASE__
 | ) |
Value:
do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
                                                        (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
                                                       }while(0)

Definition at line 276 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), and CRYP_GCMCCM_SetHeaderPhase_IT().

#define HAL_CRYP_FIFO_FLUSH ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)

Definition at line 280 of file stm32h7xx_hal_cryp.c.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

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STM32H753xx HAL User Manual: CRYP Private Constants

CRYP Private Constants
CRYP
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STM32H753xx HAL User Manual: CRYP Private Defines

Defines
CRYP Private Defines
CRYP

Defines

#define | CRYP_TIMEOUT_KEYPREPARATION 82U /*The latency of key preparation operation is 82 clock cycles.*/
#define | CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
#define | CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
#define | CRYP_PHASE_READY 0x00000001U
#define | CRYP_PHASE_PROCESS 0x00000002U
#define | CRYP_PHASE_INIT 0x00000000U
#define | CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
#define | CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
#define | CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
#define | CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
#define | CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR
#define | CRYP_CCM_CTR1_0 0x07FFFFFFU
#define | CRYP_CCM_CTR1_1 0xFFFFFF00U
#define | CRYP_CCM_CTR1_2 0x00000001U

Define Documentation

#define CRYP_CCM_CTR1_0 0x07FFFFFFU

Definition at line 261 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), and CRYP_AESCCM_Process_IT().

#define CRYP_CCM_CTR1_1 0xFFFFFF00U

Definition at line 262 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), and CRYP_AESCCM_Process_IT().

#define CRYP_CCM_CTR1_2 0x00000001U

Definition at line 263 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), and CRYP_AESCCM_Process_IT().

#define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR

Decryption

Definition at line 257 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_Workaround(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), and HAL_CRYP_Decrypt_IT().

#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U

Encryption mode

Definition at line 256 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_Workaround(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH

GCM/GMAC or CCM final phase

Definition at line 255 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_Workaround().

#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0

GCM/GMAC or CCM header phase

Definition at line 253 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_Workaround(), and HAL_CRYP_IRQHandler().

#define CRYP_PHASE_INIT 0x00000000U

GCM/GMAC (or CCM) init phase

Definition at line 252 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), and CRYP_AESGCM_Process_IT().

#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1

GCM(/CCM) payload phase

Definition at line 254 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), and CRYP_GCMCCM_SetHeaderPhase_IT().

#define CRYP_PHASE_PROCESS 0x00000002U

CRYP peripheral is in processing phase

Definition at line 250 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

#define CRYP_PHASE_READY 0x00000001U

CRYP peripheral is ready for initialization.

Definition at line 249 of file stm32h7xx_hal_cryp.c.

Referenced by HAL_CRYP_DeInit(), HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/

Definition at line 247 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_GCMCCM_SetHeaderPhase_DMA().

#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/

Definition at line 246 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_DMA(), and CRYP_AESGCM_Process_IT().

#define CRYP_TIMEOUT_KEYPREPARATION 82U /*The latency of key preparation operation is 82 clock cycles.*/

Definition at line 245 of file stm32h7xx_hal_cryp.c.

Referenced by CRYP_AES_Decrypt_DMA(), and CRYP_AES_Decrypt_IT().

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STM32H753xx HAL User Manual: CRYP Private Variables

CRYP Private Variables
CRYP
Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRYP_Private_Functions_prototypes

CRYP_Private_Functions_prototypes
CRYP
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STM32H753xx HAL User Manual: CRYPEx Private Types

CRYPEx Private Types
CRYPEx
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STM32H753xx HAL User Manual: CRYPEx Private Variables

CRYPEx Private Variables
CRYPEx
Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRYPEx Private Constants

CRYPEx Private Constants
CRYPEx
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STM32H753xx HAL User Manual: CRYPEx Private Macros

CRYPEx Private Macros
CRYPEx
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STM32H753xx HAL User Manual: CRYPEx Private Functions

CRYPEx Private Functions
CRYPEx
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STM32H753xx HAL User Manual: Extended AES processing functions

Functions
Extended AES processing functions
CRYPEx Exported Functions

CRYPEx Extended processing functions. More...

Functions

HAL_StatusTypeDef | HAL_CRYPEx_AESGCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
generate the GCM authentication TAG.
HAL_StatusTypeDef | HAL_CRYPEx_AESCCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
AES CCM Authentication TAG generation.

Detailed Description

CRYPEx Extended processing functions.

  ==============================================================================
              ##### Extended AES processing functions #####
  ==============================================================================
    [..]  This section provides functions allowing to generate the authentication
          TAG in Polling mode
      (+)HAL_CRYPEx_AESGCM_GenerateAuthTAG
      (+)HAL_CRYPEx_AESCCM_GenerateAuthTAG
         they should be used after Encrypt/Decrypt operation.

Function Documentation

HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | AuthTag,
 |  | uint32_t | Timeout
 | ) |  |

AES CCM Authentication TAG generation.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
AuthTag,: Pointer to the authentication buffer
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 267 of file stm32h7xx_hal_cryp_ex.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::B0, CRYP_CCM_CTR0_0, CRYP_CCM_CTR0_3, CRYP_DATATYPE_16B, CRYP_DATATYPE_1B, CRYP_DATATYPE_8B, CRYP_FLAG_OFNE, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_FINAL, CRYPEx_PHASE_FINAL, CRYPEx_PHASE_PROCESS, CRYP_ConfigTypeDef::DataType, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, HAL_GetTick(), CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_HandleTypeDef::Phase, and CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | AuthTag,
 |  | uint32_t | Timeout
 | ) |  |

generate the GCM authentication TAG.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
AuthTag,: Pointer to the authentication buffer
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 128 of file stm32h7xx_hal_cryp_ex.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_DATATYPE_16B, CRYP_DATATYPE_1B, CRYP_DATATYPE_32B, CRYP_DATATYPE_8B, CRYP_FLAG_OFNE, CRYP_PHASE_FINAL, CRYPEx_PHASE_FINAL, CRYPEx_PHASE_PROCESS, CRYP_ConfigTypeDef::DataType, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, HAL_GetTick(), CRYP_ConfigTypeDef::HeaderSize, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_HandleTypeDef::Phase, CRYP_HandleTypeDef::Size, and CRYP_HandleTypeDef::State.

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STM32H753xx HAL User Manual: CRYPEx_Private_Defines

Defines
CRYPEx_Private_Defines
CRYPEx

Defines

#define | CRYP_PHASE_INIT 0x00000000U
#define | CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
#define | CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
#define | CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
#define | CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
#define | CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR
#define | CRYPEx_PHASE_PROCESS 0x02U
#define | CRYPEx_PHASE_FINAL 0x03U
#define | CRYP_CCM_CTR0_0 0x07FFFFFFU
#define | CRYP_CCM_CTR0_3 0xFFFFFF00U

Define Documentation

#define CRYP_CCM_CTR0_0 0x07FFFFFFU

Definition at line 83 of file stm32h7xx_hal_cryp_ex.c.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG().

#define CRYP_CCM_CTR0_3 0xFFFFFF00U

Definition at line 84 of file stm32h7xx_hal_cryp_ex.c.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG().

#define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR

Definition at line 77 of file stm32h7xx_hal_cryp_ex.c.

#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U

Definition at line 76 of file stm32h7xx_hal_cryp_ex.c.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG().

#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH

Definition at line 74 of file stm32h7xx_hal_cryp_ex.c.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0

Definition at line 72 of file stm32h7xx_hal_cryp_ex.c.

#define CRYP_PHASE_INIT 0x00000000U

Definition at line 71 of file stm32h7xx_hal_cryp_ex.c.

#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1

Definition at line 73 of file stm32h7xx_hal_cryp_ex.c.

#define CRYPEx_PHASE_FINAL 0x03U

CRYP peripheral is in final phase this is relevant only with CCM and GCM modes

Definition at line 80 of file stm32h7xx_hal_cryp_ex.c.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define CRYPEx_PHASE_PROCESS 0x02U

CRYP peripheral is in processing phase

Definition at line 79 of file stm32h7xx_hal_cryp_ex.c.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

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STM32H753xx HAL User Manual: DAC Exported Types

Data Structures | Enumerations
DAC Exported Types
DAC

Data Structures

struct | DAC_HandleTypeDef
DAC handle Structure definition. More...
struct | DAC_SampleAndHoldConfTypeDef
DAC Configuration sample and hold Channel structure definition. More...
struct | DAC_ChannelConfTypeDef
DAC Configuration regular Channel structure definition. More...

Enumerations

enum HAL_DAC_StateTypeDef {
HAL_DAC_STATE_RESET = 0x00, HAL_DAC_STATE_READY = 0x01, HAL_DAC_STATE_BUSY = 0x02, HAL_DAC_STATE_TIMEOUT = 0x03,
HAL_DAC_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_DAC_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_DAC_STATE_RESET

DAC not yet initialized or disabled

HAL_DAC_STATE_READY

DAC initialized and ready for use

HAL_DAC_STATE_BUSY

DAC internal processing is ongoing

HAL_DAC_STATE_TIMEOUT

DAC timeout state

HAL_DAC_STATE_ERROR

DAC error state

Definition at line 67 of file stm32h7xx_hal_dac.h.

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STM32H753xx HAL User Manual: DAC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DAC_HandleTypeDef Struct Reference
DAC Exported Types

DAC handle Structure definition. More...

#include <stm32h7xx_hal_dac.h>

Data Fields

DAC_TypeDef * | Instance
__IO HAL_DAC_StateTypeDef | State
HAL_LockTypeDef | Lock
DMA_HandleTypeDef * DMA_Handle1
DMA_HandleTypeDef * DMA_Handle2
__IO uint32_t | ErrorCode

Detailed Description

DAC handle Structure definition.

Definition at line 80 of file stm32h7xx_hal_dac.h.

Field Documentation

DMA_HandleTypeDef* DAC_HandleTypeDef::DMA_Handle1

Pointer DMA handler for channel 1

Definition at line 88 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

DMA_HandleTypeDef* DAC_HandleTypeDef::DMA_Handle2

Pointer DMA handler for channel 2

Definition at line 90 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

__IO uint32_t DAC_HandleTypeDef::ErrorCode

DAC Error code

Definition at line 92 of file stm32h7xx_hal_dac.h.

Referenced by DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetError(), HAL_DAC_Init(), and HAL_DAC_IRQHandler().

DAC_TypeDef* DAC_HandleTypeDef::Instance

Register base address

Definition at line 82 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetValue(), HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualGetValue(), HAL_DACEx_DualSetValue(), HAL_DACEx_GetTrimOffset(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_SelfCalibrate(), HAL_DACEx_SetUserTrimming(), and HAL_DACEx_TriangleWaveGenerate().

HAL_LockTypeDef DAC_HandleTypeDef::Lock

DAC locking object

Definition at line 86 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Init().

__IO HAL_DAC_StateTypeDef DAC_HandleTypeDef::State

DAC communication state

Definition at line 84 of file stm32h7xx_hal_dac.h.

Referenced by DAC_DMAConvCpltCh1(), DAC_DMAConvCpltCh2(), DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetState(), HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_GetTrimOffset(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_SelfCalibrate(), and HAL_DACEx_TriangleWaveGenerate().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dac.h
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STM32H753xx HAL User Manual: DAC_SampleAndHoldConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DAC_SampleAndHoldConfTypeDef Struct Reference
DAC Exported Types

DAC Configuration sample and hold Channel structure definition. More...

#include <stm32h7xx_hal_dac.h>

Data Fields

uint32_t | DAC_SampleTime
uint32_t | DAC_HoldTime
uint32_t | DAC_RefreshTime

Detailed Description

DAC Configuration sample and hold Channel structure definition.

Definition at line 99 of file stm32h7xx_hal_dac.h.

Field Documentation

uint32_t DAC_SampleAndHoldConfTypeDef::DAC_HoldTime

Specifies the hold time for the selected channel This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 1023

Definition at line 105 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_SampleAndHoldConfTypeDef::DAC_RefreshTime

Specifies the refresh time for the selected channel This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 255

Definition at line 109 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_SampleAndHoldConfTypeDef::DAC_SampleTime

Specifies the Sample time for the selected channel. This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 1023

Definition at line 101 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dac.h
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STM32H753xx HAL User Manual: DAC_ChannelConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DAC_ChannelConfTypeDef Struct Reference
DAC Exported Types

DAC Configuration regular Channel structure definition. More...

#include <stm32h7xx_hal_dac.h>

Data Fields

uint32_t | DAC_SampleAndHold
uint32_t | DAC_Trigger
uint32_t | DAC_OutputBuffer
uint32_t | DAC_ConnectOnChipPeripheral
uint32_t | DAC_UserTrimming
uint32_t | DAC_TrimmingValue
DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig

Detailed Description

DAC Configuration regular Channel structure definition.

Definition at line 118 of file stm32h7xx_hal_dac.h.

Field Documentation

uint32_t DAC_ChannelConfTypeDef::DAC_ConnectOnChipPeripheral

Specifies whether the DAC output is connected or not to on chip peripheral . This parameter can be a value of DAC ConnectOnChipPeripheral

Definition at line 129 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_OutputBuffer

Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of DAC output buffer

Definition at line 126 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_SampleAndHold

Specifies whether the DAC mode. This parameter can be a value of . Mode is Sample and hold (low power or normal)

Definition at line 120 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

DAC_SampleAndHoldConfTypeDef DAC_ChannelConfTypeDef::DAC_SampleAndHoldConfig

Sample and Hold settings

Definition at line 140 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_Trigger

Specifies the external trigger for the selected DAC channel. This parameter can be a value of DAC trigger selection

Definition at line 123 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_TrimmingValue

Specifies the offset trimming value i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. This parameter must be a number between Min_Data = 1 and Max_Data = 31

Definition at line 136 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DACEx_SelfCalibrate(), and HAL_DACEx_SetUserTrimming().

uint32_t DAC_ChannelConfTypeDef::DAC_UserTrimming

Specifies the trimming mode This parameter must be a value of DAC User Trimming DAC_UserTrimming is either factory or user trimming

Definition at line 132 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DACEx_SelfCalibrate(), and HAL_DACEx_SetUserTrimming().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dac.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DAC Error Code

Defines
DAC Error Code
DAC Exported Constants

Defines

#define | HAL_DAC_ERROR_NONE 0x00
#define | HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01
#define | HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02
#define | HAL_DAC_ERROR_DMA 0x04
#define | HAL_DAC_ERROR_TIMEOUT 0x08

Define Documentation

#define HAL_DAC_ERROR_DMA 0x04

DMA error

Definition at line 160 of file stm32h7xx_hal_dac.h.

Referenced by DAC_DMAErrorCh1(), and DAC_DMAErrorCh2().

#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01

DAC channel1 DMA underrun error

Definition at line 158 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02

DAC channel2 DMA underrun error

Definition at line 159 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define HAL_DAC_ERROR_NONE 0x00

No error

Definition at line 157 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_DeInit(), and HAL_DAC_Init().

#define HAL_DAC_ERROR_TIMEOUT 0x08

Timeout error

Definition at line 161 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

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STM32H753xx HAL User Manual: DAC trigger selection

Defines
DAC trigger selection
DAC Exported Constants

Defines

#define | DAC_TRIGGER_NONE ((uint32_t)0x00000000)
#define | DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TEN1))
#define | DAC_TRIGGER_T1_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_2 |DAC_CR_TEN1))
#define | DAC_TRIGGER_T6_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TEN1))
#define | DAC_TRIGGER_HR1_TRGO1 ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_HR1_TRGO2 ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_LP1_OUT ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_LP2_OUT ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1))
#define | DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))

Define Documentation

#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))

EXTI Line9 event selected as external conversion trigger for DAC channel

Definition at line 183 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_HR1_TRGO1 ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))

HR1 TRGO1 selected as external conversion trigger for DAC channel

Definition at line 179 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_HR1_TRGO2 ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1))

HR1 TRGO2 selected as external conversion trigger for DAC channel

Definition at line 180 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_LP1_OUT ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))

LP1 OUT TRGO selected as external conversion trigger for DAC channel

Definition at line 181 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_LP2_OUT ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1))

LP2 OUT TRGO selected as external conversion trigger for DAC channel

Definition at line 182 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_NONE ((uint32_t)0x00000000)

Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger

Definition at line 169 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TEN1))

Conversion started by software trigger for DAC channel

Definition at line 170 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TEN1))

TIM15 TRGO selected as external conversion trigger for DAC channel

Definition at line 178 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_T1_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1))

TIM1 TRGO selected as external conversion trigger for DAC channel

Definition at line 171 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1))

TIM2 TRGO selected as external conversion trigger for DAC channel

Definition at line 172 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))

TIM4 TRGO selected as external conversion trigger for DAC channel

Definition at line 173 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_2 |DAC_CR_TEN1))

TIM5 TRGO selected as external conversion trigger for DAC channel

Definition at line 174 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_T6_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))

TIM6 TRGO selected as external conversion trigger for DAC channel

Definition at line 175 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1))

TIM7 TRGO selected as external conversion trigger for DAC channel

Definition at line 176 of file stm32h7xx_hal_dac.h.

#define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))

TIM8 TRGO selected as external conversion trigger for DAC channel

Definition at line 177 of file stm32h7xx_hal_dac.h.

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STM32H753xx HAL User Manual: DAC output buffer

Defines
DAC output buffer
DAC Exported Constants

Defines

#define | DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
#define | DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_MCR_MODE1_1)

Define Documentation

#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_MCR_MODE1_1)

Definition at line 192 of file stm32h7xx_hal_dac.h.

#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)

Definition at line 191 of file stm32h7xx_hal_dac.h.

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STM32H753xx HAL User Manual: DAC ConnectOnChipPeripheral

Defines
DAC ConnectOnChipPeripheral
DAC Exported Constants

Defines

#define | DAC_CHIPCONNECT_DISABLE ((uint32_t)0x00000000)
#define | DAC_CHIPCONNECT_ENABLE ((uint32_t)DAC_MCR_MODE1_0)

Define Documentation

#define DAC_CHIPCONNECT_DISABLE ((uint32_t)0x00000000)

Definition at line 201 of file stm32h7xx_hal_dac.h.

#define DAC_CHIPCONNECT_ENABLE ((uint32_t)DAC_MCR_MODE1_0)

Definition at line 202 of file stm32h7xx_hal_dac.h.

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STM32H753xx HAL User Manual: DAC User Trimming

Defines
DAC User Trimming
DAC Exported Constants

Defines

#define | DAC_TRIMMING_FACTORY ((uint32_t)0x00000000)
#define | DAC_TRIMMING_USER ((uint32_t)0x00000001)

Define Documentation

#define DAC_TRIMMING_FACTORY ((uint32_t)0x00000000)

Factory trimming

Definition at line 212 of file stm32h7xx_hal_dac.h.

#define DAC_TRIMMING_USER ((uint32_t)0x00000001)

User trimming

Definition at line 213 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DACEx_SelfCalibrate(), and HAL_DACEx_SetUserTrimming().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: . Mode is Sample and hold (low power or normal)

Defines
. Mode is Sample and hold (low power or normal)
DAC Exported Constants

Defines

#define | DAC_SAMPLEANDHOLD_DISABLE ((uint32_t)0x00000000)
#define | DAC_SAMPLEANDHOLD_ENABLE ((uint32_t)DAC_MCR_MODE1_2)

Define Documentation

#define DAC_SAMPLEANDHOLD_DISABLE ((uint32_t)0x00000000)

Definition at line 222 of file stm32h7xx_hal_dac.h.

#define DAC_SAMPLEANDHOLD_ENABLE ((uint32_t)DAC_MCR_MODE1_2)

Definition at line 223 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DAC Channel selection

Defines
DAC Channel selection
DAC Exported Constants

Defines

#define | DAC_CHANNEL_1 ((uint32_t)0x00000000)
#define | DAC_CHANNEL_2 ((uint32_t)0x00000010)

Define Documentation

#define DAC_CHANNEL_1 ((uint32_t)0x00000000)

Definition at line 234 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_GetValue(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA(), and HAL_DACEx_SelfCalibrate().

#define DAC_CHANNEL_2 ((uint32_t)0x00000010)

Definition at line 235 of file stm32h7xx_hal_dac.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DAC data alignment

Defines
DAC data alignment
DAC Exported Constants

Defines

#define | DAC_ALIGN_12B_R ((uint32_t)0x00000000)
#define | DAC_ALIGN_12B_L ((uint32_t)0x00000004)
#define | DAC_ALIGN_8B_R ((uint32_t)0x00000008)

Define Documentation

#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)

Definition at line 245 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA().

#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)

Definition at line 244 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_SelfCalibrate().

#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)

Definition at line 246 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualSetValue().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DAC flags definition

Defines
DAC flags definition
DAC Exported Constants

Defines

#define | DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define | DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)

Define Documentation

#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)

Definition at line 254 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)

Definition at line 255 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DAC IT definition

Defines
DAC IT definition
DAC Exported Constants

Defines

#define | DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define | DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)

Define Documentation

#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)

Definition at line 264 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler(), HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)

Definition at line 265 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler(), HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DAC Exported Macros

Defines
DAC Exported Macros
DAC

Defines

#define | __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
Reset DAC handle state.
#define | __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
Enable the DAC channel.
#define | __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
Disable the DAC channel.
#define | DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
Set DHR12R1 alignment.
#define | DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
Set DHR12R2 alignment.
#define | DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
Set DHR12RD alignment.
#define | __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the DAC interrupt.
#define | __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the DAC interrupt.
#define | __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified DAC interrupt source is enabled or not.
#define | __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected DAC's flag status.
#define | __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
Clear the DAC's flag.

Define Documentation

#define __HAL_DAC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR) = (__FLAG__))

Clear the DAC's flag.

Parameters:
__HANDLE__,: specifies the DAC handle.
__FLAG__,: specifies the DAC flag to clear. This parameter can be any combination of the following values:
  • DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
  • DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
Return values:
None

Definition at line 369 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define __HAL_DAC_DISABLE | ( | __HANDLE__,
 |  | __DAC_Channel__
 | ) | ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))

Disable the DAC channel.

Parameters:
__HANDLE__,: specifies the DAC handle
__DAC_Channel__,: specifies the DAC channel.
Return values:
None

Definition at line 300 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Stop(), and HAL_DAC_Stop_DMA().

#define __HAL_DAC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))

Disable the DAC interrupt.

Parameters:
__HANDLE__,: specifies the DAC handle
__INTERRUPT__,: specifies the DAC interrupt. This parameter can be any combination of the following values:
  • DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
  • DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
Return values:
None

Definition at line 339 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Stop_DMA().

#define __HAL_DAC_ENABLE | ( | __HANDLE__,
 |  | __DAC_Channel__
 | ) | ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))

Enable the DAC channel.

Parameters:
__HANDLE__,: specifies the DAC handle.
__DAC_Channel__,: specifies the DAC channel
Return values:
None

Definition at line 292 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Start(), and HAL_DAC_Start_DMA().

#define __HAL_DAC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))

Enable the DAC interrupt.

Parameters:
__HANDLE__,: specifies the DAC handle
__INTERRUPT__,: specifies the DAC interrupt. This parameter can be any combination of the following values:
  • DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
  • DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
Return values:
None

Definition at line 329 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA().

#define __HAL_DAC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Get the selected DAC's flag status.

Parameters:
__HANDLE__,: specifies the DAC handle.
__FLAG__,: specifies the DAC flag to get. This parameter can be any combination of the following values:
  • DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
  • DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
Return values:
None

Definition at line 359 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define __HAL_DAC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified DAC interrupt source is enabled or not.

Parameters:
__HANDLE__,: DAC handle
__INTERRUPT__,: DAC interrupt source to check This parameter can be any combination of the following values:
  • DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
  • DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
Return values:
State of interruption (SET or RESET)

Definition at line 349 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define __HAL_DAC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)

Reset DAC handle state.

Parameters:
__HANDLE__,: specifies the DAC handle.
Return values:
None

Definition at line 285 of file stm32h7xx_hal_dac.h.

#define DAC_DHR12R1_ALIGNMENT ( __ALIGNMENT__ ) (((uint32_t)0x00000008) + (__ALIGNMENT__))

Set DHR12R1 alignment.

Parameters:
__ALIGNMENT__,: specifies the DAC alignment
Return values:
None

Definition at line 307 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), and HAL_DACEx_SelfCalibrate().

#define DAC_DHR12R2_ALIGNMENT ( __ALIGNMENT__ ) (((uint32_t)0x00000014) + (__ALIGNMENT__))

Set DHR12R2 alignment.

Parameters:
__ALIGNMENT__,: specifies the DAC alignment
Return values:
None

Definition at line 313 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), and HAL_DACEx_SelfCalibrate().

#define DAC_DHR12RD_ALIGNMENT ( __ALIGNMENT__ ) (((uint32_t)0x00000020) + (__ALIGNMENT__))

Set DHR12RD alignment.

Parameters:
__ALIGNMENT__,: specifies the DAC alignment
Return values:
None

Definition at line 319 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DACEx_DualSetValue().

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STM32H753xx HAL User Manual: DAC Private Macros

Defines
DAC Private Macros
DAC

Defines

#define | IS_DAC_OUTPUT_BUFFER_STATE(STATE)
#define | IS_DAC_CHANNEL(CHANNEL)
#define | IS_DAC_ALIGN(ALIGN)
#define | IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
#define | IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x0000000FF)

Define Documentation

#define IS_DAC_ALIGN ( ALIGN )
Value:
(((ALIGN) == DAC_ALIGN_12B_R) || \
                             ((ALIGN) == DAC_ALIGN_12B_L) || \
                             ((ALIGN) == DAC_ALIGN_8B_R))

Definition at line 386 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), HAL_DAC_Start_DMA(), and HAL_DACEx_DualSetValue().

#define IS_DAC_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == DAC_CHANNEL_1) || \
                                ((CHANNEL) == DAC_CHANNEL_2))

Definition at line 383 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_GetValue(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_GetTrimOffset(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_SelfCalibrate(), HAL_DACEx_SetUserTrimming(), and HAL_DACEx_TriangleWaveGenerate().

#define IS_DAC_DATA ( DATA ) ((DATA) <= 0xFFF0)

Definition at line 390 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), and HAL_DACEx_DualSetValue().

#define IS_DAC_OUTPUT_BUFFER_STATE ( STATE )
Value:
(((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))

Definition at line 380 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_REFRESHTIME ( TIME ) ((TIME) <= 0x0000000FF)

Definition at line 392 of file stm32h7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

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STM32H753xx HAL User Manual: DAC Private Functions

Functions
DAC Private Functions
DAC Private Constants

Functions

static void | DAC_DMAConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
static void | DAC_DMAErrorCh1 (DMA_HandleTypeDef *hdma)
DMA error callback.
static void | DAC_DMAHalfConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.

Function Documentation

static void DAC_DMAConvCpltCh1 ( DMA_HandleTypeDef * hdma ) [static]

DMA conversion complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1121 of file stm32h7xx_hal_dac.c.

References HAL_DAC_ConvCpltCallbackCh1(), HAL_DAC_STATE_READY, and DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

static void DAC_DMAErrorCh1 ( DMA_HandleTypeDef * hdma ) [static]

DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1149 of file stm32h7xx_hal_dac.c.

References DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_ErrorCallbackCh1(), HAL_DAC_STATE_READY, and DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

static void DAC_DMAHalfConvCpltCh1 ( DMA_HandleTypeDef * hdma ) [static]

DMA half transfer complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1136 of file stm32h7xx_hal_dac.c.

References HAL_DAC_ConvHalfCpltCallbackCh1().

Referenced by HAL_DAC_Start_DMA().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DAC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitialize the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initialize the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitialize the DAC MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the DAC.
      (+) De-initialize the DAC.

Function Documentation

HAL_StatusTypeDef HAL_DAC_DeInit ( DAC_HandleTypeDef * hdac )

Deinitialize the DAC peripheral registers to their default reset values.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 354 of file stm32h7xx_hal_dac.c.

References assert_param, DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_NONE, HAL_DAC_MspDeInit(), HAL_DAC_STATE_BUSY, HAL_DAC_STATE_RESET, DAC_HandleTypeDef::Instance, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Init ( DAC_HandleTypeDef * hdac )

Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 317 of file stm32h7xx_hal_dac.c.

References assert_param, DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_NONE, HAL_DAC_MspInit(), HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, HAL_DAC_STATE_RESET, DAC_HandleTypeDef::Instance, DAC_HandleTypeDef::Lock, and DAC_HandleTypeDef::State.

void HAL_DAC_MspDeInit ( DAC_HandleTypeDef * hdac )

DeInitialize the DAC MSP.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 405 of file stm32h7xx_hal_dac.c.

Referenced by HAL_DAC_DeInit().

void HAL_DAC_MspInit ( DAC_HandleTypeDef * hdac )

Initialize the DAC MSP.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 390 of file stm32h7xx_hal_dac.c.

Referenced by HAL_DAC_Init().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
DAC Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enable DAC and start conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disable DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enable DAC and start conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disable DAC and stop conversion of channel.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handle DAC interrupt request This function uses the interruption of DMA underrun.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.

Detailed Description

IO operation functions.

  ==============================================================================
             ##### IO operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion.
      (+) Stop conversion.
      (+) Start conversion and enable DMA transfer.
      (+) Stop conversion and disable DMA transfer.
      (+) Set the specified data holding register value for DAC channel.

Function Documentation

void HAL_DAC_ConvCpltCallbackCh1 ( DAC_HandleTypeDef * hdac )

Conversion complete callback in non-blocking mode for Channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 802 of file stm32h7xx_hal_dac.c.

Referenced by DAC_DMAConvCpltCh1().

void HAL_DAC_ConvHalfCpltCallbackCh1 ( DAC_HandleTypeDef * hdac )

Conversion half DMA transfer callback in non-blocking mode for Channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 818 of file stm32h7xx_hal_dac.c.

Referenced by DAC_DMAHalfConvCpltCh1().

void HAL_DAC_DMAUnderrunCallbackCh1 ( DAC_HandleTypeDef * hdac )

DMA underrun DAC callback for channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 850 of file stm32h7xx_hal_dac.c.

Referenced by HAL_DAC_IRQHandler().

void HAL_DAC_ErrorCallbackCh1 ( DAC_HandleTypeDef * hdac )

Error DAC callback for Channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 834 of file stm32h7xx_hal_dac.c.

Referenced by DAC_DMAErrorCh1().

void HAL_DAC_IRQHandler ( DAC_HandleTypeDef * hdac )

Handle DAC interrupt request This function uses the interruption of DMA underrun.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 708 of file stm32h7xx_hal_dac.c.

References __HAL_DAC_CLEAR_FLAG, __HAL_DAC_GET_FLAG, __HAL_DAC_GET_IT_SOURCE, DAC_FLAG_DMAUDR1, DAC_FLAG_DMAUDR2, DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, DAC_HandleTypeDef::ErrorCode, HAL_DAC_DMAUnderrunCallbackCh1(), HAL_DAC_ERROR_DMAUNDERRUNCH1, HAL_DAC_ERROR_DMAUNDERRUNCH2, HAL_DAC_STATE_ERROR, HAL_DACEx_DMAUnderrunCallbackCh2(), DAC_HandleTypeDef::Instance, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_SetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Alignment,
 |  | uint32_t | Data
 | ) |  |

Set the specified data holding register value for DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Alignment,: Specifies the data alignment. This parameter can be one of the following values:
  • DAC_ALIGN_8B_R: 8bit right data alignment selected
  • DAC_ALIGN_12B_L: 12bit left data alignment selected
  • DAC_ALIGN_12B_R: 12bit right data alignment selected
Data,: Data to be loaded in the selected data holding register.
Return values:
HAL status

Definition at line 770 of file stm32h7xx_hal_dac.c.

References assert_param, DAC_CHANNEL_1, DAC_DHR12R1_ALIGNMENT, DAC_DHR12R2_ALIGNMENT, DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, IS_DAC_CHANNEL, and IS_DAC_DATA.

HAL_StatusTypeDef HAL_DAC_Start | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Enable DAC and start conversion of channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 447 of file stm32h7xx_hal_dac.c.

References __HAL_DAC_ENABLE, assert_param, DAC_CHANNEL_1, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Start_DMA | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint32_t | Length,
 |  | uint32_t | Alignment
 | ) |  |

Enable DAC and start conversion of channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
pData,: The destination peripheral Buffer address.
Length,: The length of data to be transferred from memory to DAC peripheral
Alignment,: Specifies the data alignment for DAC channel. This parameter can be one of the following values:
  • DAC_ALIGN_8B_R: 8bit right data alignment selected
  • DAC_ALIGN_12B_L: 12bit left data alignment selected
  • DAC_ALIGN_12B_R: 12bit right data alignment selected
Return values:
HAL status

Definition at line 534 of file stm32h7xx_hal_dac.c.

References __HAL_DAC_ENABLE, __HAL_DAC_ENABLE_IT, assert_param, DAC_ALIGN_12B_L, DAC_ALIGN_12B_R, DAC_ALIGN_8B_R, DAC_CHANNEL_1, DAC_DMAConvCpltCh1(), DAC_DMAConvCpltCh2(), DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), DAC_DMAHalfConvCpltCh1(), DAC_DMAHalfConvCpltCh2(), DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, DAC_HandleTypeDef::DMA_Handle1, DAC_HandleTypeDef::DMA_Handle2, HAL_DAC_STATE_BUSY, HAL_DMA_Start_IT(), DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, IS_DAC_CHANNEL, DAC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DAC_Stop | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Disable DAC and stop conversion of channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 502 of file stm32h7xx_hal_dac.c.

References __HAL_DAC_DISABLE, assert_param, HAL_DAC_STATE_READY, IS_DAC_CHANNEL, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Stop_DMA | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Disable DAC and stop conversion of channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 654 of file stm32h7xx_hal_dac.c.

References __HAL_DAC_DISABLE, __HAL_DAC_DISABLE_IT, assert_param, DAC_CHANNEL_1, DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, DAC_HandleTypeDef::DMA_Handle1, DAC_HandleTypeDef::DMA_Handle2, HAL_DAC_STATE_ERROR, HAL_DAC_STATE_READY, HAL_DMA_Abort(), DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and DAC_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
DAC Exported Functions

Peripheral Control functions. More...

Functions

uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configure the selected DAC channel.

Detailed Description

Peripheral Control functions.

  ==============================================================================
             ##### Peripheral Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels.
      (+) Get result of conversion.

Function Documentation

HAL_StatusTypeDef HAL_DAC_ConfigChannel | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Configure the selected DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig,: DAC configuration structure.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 916 of file stm32h7xx_hal_dac.c.

References assert_param, DAC_CHANNEL_1, DAC_ChannelConfTypeDef::DAC_ConnectOnChipPeripheral, DAC_SampleAndHoldConfTypeDef::DAC_HoldTime, DAC_ChannelConfTypeDef::DAC_OutputBuffer, DAC_SampleAndHoldConfTypeDef::DAC_RefreshTime, DAC_ChannelConfTypeDef::DAC_SampleAndHold, DAC_SAMPLEANDHOLD_ENABLE, DAC_ChannelConfTypeDef::DAC_SampleAndHoldConfig, DAC_SampleAndHoldConfTypeDef::DAC_SampleTime, DAC_ChannelConfTypeDef::DAC_Trigger, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_TIMEOUT, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, HAL_DAC_STATE_TIMEOUT, HAL_Delay(), HAL_GetTick(), DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_CHIP_CONNECTION, IS_DAC_HOLDTIME, IS_DAC_OUTPUT_BUFFER_STATE, IS_DAC_REFRESHTIME, IS_DAC_SAMPLEANDHOLD, IS_DAC_SAMPLETIME, IS_DAC_TRIGGER, IS_DAC_TRIMMING, IS_DAC_TRIMMINGVALUE, DAC_HandleTypeDef::State, and TIMEOUT_DAC_CALIBCONFIG.

uint32_t HAL_DAC_GetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Return the last data output value of the selected DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
The selected DAC channel data output value.

Definition at line 890 of file stm32h7xx_hal_dac.c.

References assert_param, DAC_CHANNEL_1, DAC_HandleTypeDef::Instance, and IS_DAC_CHANNEL.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
DAC Exported Functions

Peripheral State and Errors functions. More...

Functions

HAL_DAC_StateTypeDef | HAL_DAC_GetState (DAC_HandleTypeDef *hdac)
return the DAC handle state
uint32_t | HAL_DAC_GetError (DAC_HandleTypeDef *hdac)
Return the DAC error code.

Detailed Description

Peripheral State and Errors functions.

  ==============================================================================
            ##### Peripheral State and Errors functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DAC state.
      (+) Check the DAC Errors.

Function Documentation

uint32_t HAL_DAC_GetError ( DAC_HandleTypeDef * hdac )

Return the DAC error code.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
DAC Error Code

Definition at line 1097 of file stm32h7xx_hal_dac.c.

References DAC_HandleTypeDef::ErrorCode.

HAL_DAC_StateTypeDef HAL_DAC_GetState ( DAC_HandleTypeDef * hdac )

return the DAC handle state

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL state

Definition at line 1085 of file stm32h7xx_hal_dac.c.

References DAC_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DAC Private Constants

Modules | Defines
DAC Private Constants
DAC

Modules

DAC Private Functions
DAC Exported Functions

Defines

#define TIMEOUT_DAC_CALIBCONFIG ((uint32_t)1) /* 1ms */

Define Documentation

#define TIMEOUT_DAC_CALIBCONFIG ((uint32_t)1) /* 1ms */

Definition at line 274 of file stm32h7xx_hal_dac.c.

Referenced by HAL_DAC_ConfigChannel().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
DACEx Exported Functions

Extended IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel2.
HAL_StatusTypeDef | HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Run the self calibration of one DAC channel.
HAL_StatusTypeDef | HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
Set the trimming mode and trimming value (user trimming mode applied).

Detailed Description

Extended IO operation functions.

  ==============================================================================
                 ##### Extended features functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion with triangle wave generation.
      (+) Start conversion with noise wave generation.
      (+) Start self calibration.
      (+) Set user trimming mode.
      (+) Get result of dual mode conversion.

Function Documentation

void HAL_DACEx_ConvCpltCallbackCh2 ( DAC_HandleTypeDef * hdac )

Conversion complete callback in non-blocking mode for Channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 256 of file stm32h7xx_hal_dac_ex.c.

Referenced by DAC_DMAConvCpltCh2().

void HAL_DACEx_ConvHalfCpltCallbackCh2 ( DAC_HandleTypeDef * hdac )

Conversion half DMA transfer callback in non-blocking mode for Channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 272 of file stm32h7xx_hal_dac_ex.c.

Referenced by DAC_DMAHalfConvCpltCh2().

void HAL_DACEx_DMAUnderrunCallbackCh2 ( DAC_HandleTypeDef * hdac )

DMA underrun DAC callback for channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 304 of file stm32h7xx_hal_dac_ex.c.

Referenced by HAL_DAC_IRQHandler().

HAL_StatusTypeDef HAL_DACEx_DualSetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Alignment,
 |  | uint32_t | Data1,
 |  | uint32_t | Data2
 | ) |  |

Set the specified data holding register value for dual DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Alignment,: Specifies the data alignment for dual channel DAC. This parameter can be one of the following values: DAC_ALIGN_8B_R: 8bit right data alignment selected DAC_ALIGN_12B_L: 12bit left data alignment selected DAC_ALIGN_12B_R: 12bit right data alignment selected
Data1,: Data for DAC Channel2 to be loaded in the selected data holding register.
Data2,: Data for DAC Channel1 to be loaded in the selected data holding register.
Note:
In dual mode, a unique register access is required to write in both DAC channels at the same time.
Return values:
HAL status

Definition at line 221 of file stm32h7xx_hal_dac_ex.c.

References assert_param, DAC_ALIGN_8B_R, DAC_DHR12RD_ALIGNMENT, DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, and IS_DAC_DATA.

void HAL_DACEx_ErrorCallbackCh2 ( DAC_HandleTypeDef * hdac )

Error DAC callback for Channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 288 of file stm32h7xx_hal_dac_ex.c.

Referenced by DAC_DMAErrorCh2().

HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Amplitude
 | ) |  |

Enable or disable the selected DAC channel wave generation.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Amplitude,: Unmask DAC channel LFSR for noise wave generation. This parameter can be one of the following values:
  • DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
  • DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
Return values:
HAL status

Definition at line 179 of file stm32h7xx_hal_dac_ex.c.

References assert_param, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_SelfCalibrate | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Run the self calibration of one DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig,: DAC channel configuration structure.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
Updates | DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
HAL | status
Note:
Calibration runs about 7 ms.

Definition at line 329 of file stm32h7xx_hal_dac_ex.c.

References assert_param, DAC_ALIGN_12B_R, DAC_CHANNEL_1, DAC_DHR12R1_ALIGNMENT, DAC_DHR12R2_ALIGNMENT, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, HAL_DAC_STATE_BUSY, HAL_Delay(), DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_SetUserTrimming | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel,
 |  | uint32_t | NewTrimmingValue
 | ) |  |

Set the trimming mode and trimming value (user trimming mode applied).

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig,: DAC configuration structure updated with new DAC trimming value.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
NewTrimmingValue,: DAC new trimming value
Return values:
HAL status

Definition at line 458 of file stm32h7xx_hal_dac_ex.c.

References assert_param, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and IS_DAC_NEWTRIMMINGVALUE.

HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Amplitude
 | ) |  |

Enable or disable the selected DAC channel wave generation.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Amplitude,: Select max triangle amplitude. This parameter can be one of the following values:
  • DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
  • DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
  • DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
  • DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
  • DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
  • DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
  • DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
  • DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
  • DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
  • DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
  • DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
  • DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
Return values:
HAL status

Definition at line 130 of file stm32h7xx_hal_dac_ex.c.

References assert_param, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE, and DAC_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
DACEx | DACEx Exported Functions

Extended Peripheral Control functions. More...

Functions

uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Return the last data output value of the selected DAC channel.
uint32_t | HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the DAC trimming value.

Detailed Description

Extended Peripheral Control functions.

  ==============================================================================
             ##### Peripheral Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels.
      (+) Set the specified data holding register value for DAC channel.

Function Documentation

uint32_t HAL_DACEx_DualGetValue ( DAC_HandleTypeDef * hdac )

Return the last data output value of the selected DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
The selected DAC channel data output value.

Definition at line 549 of file stm32h7xx_hal_dac_ex.c.

References DAC_HandleTypeDef::Instance.

uint32_t HAL_DACEx_GetTrimOffset | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Return the DAC trimming value.

Parameters:
hdac : DAC handle
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
Trimming value : range: 0->31

Definition at line 503 of file stm32h7xx_hal_dac_ex.c.

References assert_param, HAL_DAC_STATE_RESET, DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and DAC_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DACEx Exported Functions

Modules | Functions
DACEx Exported Functions
DACEx

Modules

IO operation functions

Extended IO operation functions.

Peripheral Control functions

Extended Peripheral Control functions.

Functions

HAL_StatusTypeDef | HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
Set the trimming mode and trimming value (user trimming mode applied).
uint32_t | HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the DAC trimming value.

Function Documentation

uint32_t HAL_DACEx_GetTrimOffset | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Return the DAC trimming value.

Parameters:
hdac : DAC handle
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
Trimming value : range: 0->31

Definition at line 503 of file stm32h7xx_hal_dac_ex.c.

References assert_param, HAL_DAC_STATE_RESET, DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_SetUserTrimming | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel,
 |  | uint32_t | NewTrimmingValue
 | ) |  |

Set the trimming mode and trimming value (user trimming mode applied).

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig,: DAC configuration structure updated with new DAC trimming value.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
NewTrimmingValue,: DAC new trimming value
Return values:
HAL status

Definition at line 458 of file stm32h7xx_hal_dac_ex.c.

References assert_param, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and IS_DAC_NEWTRIMMINGVALUE.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DACEx private functions

Functions
DACEx private functions
DACEx

Extended private functions. More...

Functions

void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

Extended private functions.

Function Documentation

void DAC_DMAConvCpltCh2 ( DMA_HandleTypeDef * hdma )

DMA conversion complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 578 of file stm32h7xx_hal_dac_ex.c.

References HAL_DAC_STATE_READY, HAL_DACEx_ConvCpltCallbackCh2(), and DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

void DAC_DMAErrorCh2 ( DMA_HandleTypeDef * hdma )

DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 606 of file stm32h7xx_hal_dac_ex.c.

References DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_STATE_READY, HAL_DACEx_ErrorCallbackCh2(), and DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

void DAC_DMAHalfConvCpltCh2 ( DMA_HandleTypeDef * hdma )

DMA half transfer complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 593 of file stm32h7xx_hal_dac_ex.c.

References HAL_DACEx_ConvHalfCpltCallbackCh2().

Referenced by HAL_DAC_Start_DMA().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DACEx lfsrunmask triangle amplitude

Defines
DACEx lfsrunmask triangle amplitude
DACEx Exported Constants

Defines

#define | DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000)
#define | DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2)
#define | DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3)
#define | DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000)
#define | DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2)
#define | DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3)
#define | DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Define Documentation

#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000)

Unmask DAC channel LFSR bit0 for noise wave generation

Definition at line 71 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)

Unmask DAC channel LFSR bit[10:0] for noise wave generation

Definition at line 81 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[11:0] for noise wave generation

Definition at line 82 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[1:0] for noise wave generation

Definition at line 72 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1)

Unmask DAC channel LFSR bit[2:0] for noise wave generation

Definition at line 73 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[3:0] for noise wave generation

Definition at line 74 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2)

Unmask DAC channel LFSR bit[4:0] for noise wave generation

Definition at line 75 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[5:0] for noise wave generation

Definition at line 76 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)

Unmask DAC channel LFSR bit[6:0] for noise wave generation

Definition at line 77 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[7:0] for noise wave generation

Definition at line 78 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3)

Unmask DAC channel LFSR bit[8:0] for noise wave generation

Definition at line 79 of file stm32h7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[9:0] for noise wave generation

Definition at line 80 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000)

Select max triangle amplitude of 1

Definition at line 83 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 1023

Definition at line 92 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)

Select max triangle amplitude of 127

Definition at line 89 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 15

Definition at line 86 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)

Select max triangle amplitude of 2047

Definition at line 93 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 255

Definition at line 90 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0)

Select max triangle amplitude of 3

Definition at line 84 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2)

Select max triangle amplitude of 31

Definition at line 87 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 4095

Definition at line 94 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3)

Select max triangle amplitude of 511

Definition at line 91 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 63

Definition at line 88 of file stm32h7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1)

Select max triangle amplitude of 7

Definition at line 85 of file stm32h7xx_hal_dac_ex.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DACEx Private Macros

Defines
DACEx Private Macros
DACEx

Defines

#define | IS_DAC_TRIGGER(TRIGGER)
#define | IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x0000003FF)
#define | IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x0000003FF)
#define | IS_DAC_SAMPLEANDHOLD(MODE)
#define | IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
#define | IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
#define | IS_DAC_CHIP_CONNECTION(CONNECT)
#define | IS_DAC_TRIMMING(TRIMMING)
#define | IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)

Define Documentation

#define IS_DAC_CHIP_CONNECTION ( CONNECT )
Value:
(((CONNECT) == DAC_CHIPCONNECT_DISABLE) || \
                                         ((CONNECT) == DAC_CHIPCONNECT_ENABLE))

Definition at line 140 of file stm32h7xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_HOLDTIME ( TIME ) ((TIME) <= 0x0000003FF)

Definition at line 130 of file stm32h7xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE ( VALUE )
Value:
(((VALUE) == DAC_LFSRUNMASK_BIT0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))

Definition at line 146 of file stm32h7xx_hal_dac_ex.h.

Referenced by HAL_DACEx_NoiseWaveGenerate(), and HAL_DACEx_TriangleWaveGenerate().

#define IS_DAC_NEWTRIMMINGVALUE ( TRIMMINGVALUE ) ((TRIMMINGVALUE) <= 0x1F)

Definition at line 138 of file stm32h7xx_hal_dac_ex.h.

Referenced by HAL_DACEx_SetUserTrimming().

#define IS_DAC_SAMPLEANDHOLD ( MODE )
Value:
(((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
                                    ((MODE) == DAC_SAMPLEANDHOLD_ENABLE))

Definition at line 132 of file stm32h7xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_SAMPLETIME ( TIME ) ((TIME) <= 0x0000003FF)

Definition at line 128 of file stm32h7xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == DAC_TRIGGER_NONE) || \
                                 ((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_HR1_TRGO1) || \
                                 ((TRIGGER) == DAC_TRIGGER_HR1_TRGO2) || \
                                 ((TRIGGER) == DAC_TRIGGER_LP1_OUT) || \
                                 ((TRIGGER) == DAC_TRIGGER_LP2_OUT) || \
                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))

Definition at line 112 of file stm32h7xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_TRIMMING ( TRIMMING )
Value:
(((TRIMMING) == DAC_TRIMMING_FACTORY) || \
                                        ((TRIMMING) == DAC_TRIMMING_USER))

Definition at line 143 of file stm32h7xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_TRIMMINGVALUE ( TRIMMINGVALUE ) ((TRIMMINGVALUE) <= 0x1F)

Definition at line 136 of file stm32h7xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and Configuration functions

Functions
Initialization and Configuration functions
DCMI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_DCMI_Init (DCMI_HandleTypeDef *hdcmi)
Initializes the DCMI according to the specified parameters in the DCMI_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DCMI_DeInit (DCMI_HandleTypeDef *hdcmi)
Deinitializes the DCMI peripheral registers to their default reset values.
__weak void | HAL_DCMI_MspInit (DCMI_HandleTypeDef *hdcmi)
Initializes the DCMI MSP.
__weak void | HAL_DCMI_MspDeInit (DCMI_HandleTypeDef *hdcmi)
DeInitializes the DCMI MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
                ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the DCMI
      (+) De-initialize the DCMI

Function Documentation

HAL_StatusTypeDef HAL_DCMI_DeInit ( DCMI_HandleTypeDef * hdcmi )

Deinitializes the DCMI peripheral registers to their default reset values.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL status

Definition at line 224 of file stm32h7xx_hal_dcmi.c.

References DCMI_HandleTypeDef::ErrorCode, HAL_DCMI_ERROR_NONE, HAL_DCMI_MspDeInit(), HAL_DCMI_STATE_RESET, and DCMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DCMI_Init ( DCMI_HandleTypeDef * hdcmi )

Initializes the DCMI according to the specified parameters in the DCMI_InitTypeDef and create the associated handle.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL status

Definition at line 151 of file stm32h7xx_hal_dcmi.c.

References __HAL_DCMI_ENABLE_IT, assert_param, DCMI_InitTypeDef::ByteSelectMode, DCMI_InitTypeDef::ByteSelectStart, DCMI_InitTypeDef::CaptureRate, DCMI_IT_ERR, DCMI_IT_LINE, DCMI_IT_OVR, DCMI_IT_VSYNC, DCMI_POSITION_ESCR_FEC, DCMI_POSITION_ESCR_LEC, DCMI_POSITION_ESCR_LSC, DCMI_SYNCHRO_EMBEDDED, DCMI_HandleTypeDef::ErrorCode, DCMI_InitTypeDef::ExtendedDataMode, DCMI_CodesInitTypeDef::FrameEndCode, DCMI_CodesInitTypeDef::FrameStartCode, HAL_DCMI_ERROR_NONE, HAL_DCMI_MspInit(), HAL_DCMI_STATE_BUSY, HAL_DCMI_STATE_READY, HAL_DCMI_STATE_RESET, DCMI_InitTypeDef::HSPolarity, DCMI_HandleTypeDef::Init, DCMI_HandleTypeDef::Instance, IS_DCMI_BYTE_SELECT_MODE, IS_DCMI_BYTE_SELECT_START, IS_DCMI_CAPTURE_RATE, IS_DCMI_EXTENDED_DATA, IS_DCMI_HSPOLARITY, IS_DCMI_LINE_SELECT_MODE, IS_DCMI_LINE_SELECT_START, IS_DCMI_MODE_JPEG, IS_DCMI_PCKPOLARITY, IS_DCMI_SYNCHRO, IS_DCMI_VSPOLARITY, DCMI_InitTypeDef::JPEGMode, DCMI_CodesInitTypeDef::LineEndCode, DCMI_InitTypeDef::LineSelectMode, DCMI_InitTypeDef::LineSelectStart, DCMI_CodesInitTypeDef::LineStartCode, DCMI_InitTypeDef::PCKPolarity, DCMI_HandleTypeDef::State, DCMI_InitTypeDef::SynchroMode, DCMI_InitTypeDef::SyncroCode, and DCMI_InitTypeDef::VSPolarity.

void HAL_DCMI_MspDeInit ( DCMI_HandleTypeDef * hdcmi )

DeInitializes the DCMI MSP.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
None

Definition at line 263 of file stm32h7xx_hal_dcmi.c.

Referenced by HAL_DCMI_DeInit().

void HAL_DCMI_MspInit ( DCMI_HandleTypeDef * hdcmi )

Initializes the DCMI MSP.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
None

Definition at line 247 of file stm32h7xx_hal_dcmi.c.

Referenced by HAL_DCMI_Init().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
DCMI Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DCMI_Start_DMA (DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
Enables DCMI DMA request and enables DCMI capture.
HAL_StatusTypeDef | HAL_DCMI_Stop (DCMI_HandleTypeDef *hdcmi)
Disable DCMI DMA request and Disable DCMI capture.
HAL_StatusTypeDef | HAL_DCMI_Suspend (DCMI_HandleTypeDef *hdcmi)
Suspend DCMI capture.
HAL_StatusTypeDef | HAL_DCMI_Resume (DCMI_HandleTypeDef *hdcmi)
Resume DCMI capture.
void | HAL_DCMI_IRQHandler (DCMI_HandleTypeDef *hdcmi)
Handles DCMI interrupt request.
__weak void | HAL_DCMI_ErrorCallback (DCMI_HandleTypeDef *hdcmi)
Error DCMI callback.
__weak void | HAL_DCMI_LineEventCallback (DCMI_HandleTypeDef *hdcmi)
Line Event callback.
__weak void | HAL_DCMI_VsyncEventCallback (DCMI_HandleTypeDef *hdcmi)
VSYNC Event callback.
__weak void | HAL_DCMI_FrameEventCallback (DCMI_HandleTypeDef *hdcmi)
Frame Event callback.

Detailed Description

IO operation functions.

 ===============================================================================
                      #####  IO operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure destination address and data length and
          Enables DCMI DMA request and enables DCMI capture
      (+) Stop the DCMI capture.
      (+) Handles DCMI interrupt request.

Function Documentation

void HAL_DCMI_ErrorCallback ( DCMI_HandleTypeDef * hdcmi )

Error DCMI callback.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
None

Definition at line 595 of file stm32h7xx_hal_dcmi.c.

Referenced by DCMI_DMAError().

void HAL_DCMI_FrameEventCallback ( DCMI_HandleTypeDef * hdcmi )

Frame Event callback.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
None

Definition at line 640 of file stm32h7xx_hal_dcmi.c.

Referenced by HAL_DCMI_IRQHandler().

void HAL_DCMI_IRQHandler ( DCMI_HandleTypeDef * hdcmi )

Handles DCMI interrupt request.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for the DCMI.
Return values:
None

Definition at line 510 of file stm32h7xx_hal_dcmi.c.

References __HAL_DCMI_CLEAR_FLAG, __HAL_DCMI_DISABLE_IT, DCMI_DMAError(), DCMI_FLAG_ERRRI, DCMI_FLAG_FRAMERI, DCMI_FLAG_LINERI, DCMI_FLAG_OVRRI, DCMI_FLAG_VSYNCRI, DCMI_IT_ERR, DCMI_IT_FRAME, DCMI_IT_LINE, DCMI_IT_OVR, DCMI_IT_VSYNC, DCMI_MODE_SNAPSHOT, DCMI_HandleTypeDef::DMA_Handle, DCMI_HandleTypeDef::ErrorCode, HAL_DCMI_ERROR_OVR, HAL_DCMI_ERROR_SYNC, HAL_DCMI_FrameEventCallback(), HAL_DCMI_LineEventCallback(), HAL_DCMI_STATE_ERROR, HAL_DCMI_VsyncEventCallback(), HAL_DMA_Abort_IT(), DCMI_HandleTypeDef::Instance, DCMI_HandleTypeDef::State, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_DCMI_LineEventCallback ( DCMI_HandleTypeDef * hdcmi )

Line Event callback.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
None

Definition at line 611 of file stm32h7xx_hal_dcmi.c.

Referenced by HAL_DCMI_IRQHandler().

HAL_StatusTypeDef HAL_DCMI_Resume ( DCMI_HandleTypeDef * hdcmi )

Resume DCMI capture.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL status

Definition at line 484 of file stm32h7xx_hal_dcmi.c.

References HAL_DCMI_STATE_BUSY, HAL_DCMI_STATE_SUSPENDED, DCMI_HandleTypeDef::Instance, and DCMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DCMI_Start_DMA | ( | DCMI_HandleTypeDef * | hdcmi,
 |  | uint32_t | DCMI_Mode,
 |  | uint32_t | pData,
 |  | uint32_t | Length
 | ) |  |

Enables DCMI DMA request and enables DCMI capture.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
DCMI_Mode,: DCMI capture mode snapshot or continuous grab.
pData,: The destination memory Buffer address (LCD Frame buffer).
Length,: The length of capture to be transferred.
Return values:
HAL status

Definition at line 302 of file stm32h7xx_hal_dcmi.c.

References __HAL_DCMI_ENABLE, assert_param, DCMI_DMAError(), DCMI_DMAXferCplt(), DCMI_HandleTypeDef::DMA_Handle, HAL_DCMI_STATE_BUSY, HAL_DMA_Start_IT(), HAL_DMAEx_MultiBufferStart_IT(), DCMI_HandleTypeDef::Instance, IS_DCMI_CAPTURE_MODE, DCMI_HandleTypeDef::pBuffPtr, DCMI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, DCMI_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferM1CpltCallback, DCMI_HandleTypeDef::XferSize, and DCMI_HandleTypeDef::XferTransferNumber.

HAL_StatusTypeDef HAL_DCMI_Stop ( DCMI_HandleTypeDef * hdcmi )

Disable DCMI DMA request and Disable DCMI capture.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL status

Definition at line 385 of file stm32h7xx_hal_dcmi.c.

References __HAL_DCMI_DISABLE, DCMI_HandleTypeDef::DMA_Handle, DCMI_HandleTypeDef::ErrorCode, HAL_DCMI_ERROR_NONE, HAL_DCMI_ERROR_TIMEOUT, HAL_DCMI_STATE_BUSY, HAL_DCMI_STATE_READY, HAL_DMA_Abort(), HAL_TIMEOUT_DCMI_STOP, DCMI_HandleTypeDef::Instance, and DCMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DCMI_Suspend ( DCMI_HandleTypeDef * hdcmi )

Suspend DCMI capture.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL status

Definition at line 438 of file stm32h7xx_hal_dcmi.c.

References DCMI_HandleTypeDef::ErrorCode, HAL_DCMI_ERROR_TIMEOUT, HAL_DCMI_STATE_BUSY, HAL_DCMI_STATE_READY, HAL_DCMI_STATE_SUSPENDED, HAL_TIMEOUT_DCMI_STOP, DCMI_HandleTypeDef::Instance, and DCMI_HandleTypeDef::State.

void HAL_DCMI_VsyncEventCallback ( DCMI_HandleTypeDef * hdcmi )

VSYNC Event callback.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
None

Definition at line 624 of file stm32h7xx_hal_dcmi.c.

Referenced by HAL_DCMI_IRQHandler().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
DCMI Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_DCMI_ConfigCrop (DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
Configure the DCMI CROP coordinate.
HAL_StatusTypeDef | HAL_DCMI_DisableCrop (DCMI_HandleTypeDef *hdcmi)
Disable the Crop feature.
HAL_StatusTypeDef | HAL_DCMI_EnableCrop (DCMI_HandleTypeDef *hdcmi)
Enable the Crop feature.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                    ##### Peripheral Control functions #####
 ===============================================================================
[..]  This section provides functions allowing to:
      (+) Configure the CROP feature.
      (+) Enable/Disable the CROP feature.

Function Documentation

HAL_StatusTypeDef HAL_DCMI_ConfigCrop | ( | DCMI_HandleTypeDef * | hdcmi,
 |  | uint32_t | X0,
 |  | uint32_t | Y0,
 |  | uint32_t | XSize,
 |  | uint32_t | YSize
 | ) |  |

Configure the DCMI CROP coordinate.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
YSize,: DCMI Line number
XSize,: DCMI Pixel per line
X0,: DCMI window X offset
Y0,: DCMI window Y offset
Return values:
HAL status

Definition at line 679 of file stm32h7xx_hal_dcmi.c.

References assert_param, DCMI_POSITION_CWSIZE_VLINE, DCMI_POSITION_CWSTRT_VST, HAL_DCMI_STATE_BUSY, HAL_DCMI_STATE_READY, DCMI_HandleTypeDef::Instance, IS_DCMI_WINDOW_COORDINATE, IS_DCMI_WINDOW_HEIGHT, and DCMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DCMI_DisableCrop ( DCMI_HandleTypeDef * hdcmi )

Disable the Crop feature.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL status

Definition at line 712 of file stm32h7xx_hal_dcmi.c.

References HAL_DCMI_STATE_BUSY, HAL_DCMI_STATE_READY, DCMI_HandleTypeDef::Instance, and DCMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DCMI_EnableCrop ( DCMI_HandleTypeDef * hdcmi )

Enable the Crop feature.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL status

Definition at line 738 of file stm32h7xx_hal_dcmi.c.

References HAL_DCMI_STATE_BUSY, HAL_DCMI_STATE_READY, DCMI_HandleTypeDef::Instance, and DCMI_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
DCMI Exported Functions

Peripheral State functions. More...

Functions

HAL_DCMI_StateTypeDef | HAL_DCMI_GetState (DCMI_HandleTypeDef *hdcmi)
Return the DCMI state.
uint32_t | HAL_DCMI_GetError (DCMI_HandleTypeDef *hdcmi)
Return the DCMI error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
               ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DCMI state.
      (+) Get the specific DCMI error flag.

Function Documentation

uint32_t HAL_DCMI_GetError ( DCMI_HandleTypeDef * hdcmi )

Return the DCMI error code.

Parameters:
hdcmi : pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
DCMI Error Code

Definition at line 795 of file stm32h7xx_hal_dcmi.c.

References DCMI_HandleTypeDef::ErrorCode.

HAL_DCMI_StateTypeDef HAL_DCMI_GetState ( DCMI_HandleTypeDef * hdcmi )

Return the DCMI state.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL state

Definition at line 784 of file stm32h7xx_hal_dcmi.c.

References DCMI_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DCMI Private Functions

Functions
DCMI Private Functions
DCMI Exported Functions | DCMI

Functions

static void | DCMI_DMAXferCplt (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
static void | DCMI_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Function Documentation

static void DCMI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 870 of file stm32h7xx_hal_dcmi.c.

References DCMI_HandleTypeDef::DMA_Handle, DCMI_HandleTypeDef::ErrorCode, __DMA_HandleTypeDef::ErrorCode, HAL_DCMI_ERROR_DMA, HAL_DCMI_ErrorCallback(), HAL_DCMI_STATE_READY, HAL_DMA_ERROR_FE, and DCMI_HandleTypeDef::State.

Referenced by HAL_DCMI_IRQHandler(), and HAL_DCMI_Start_DMA().

static void DCMI_DMAXferCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA conversion complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 813 of file stm32h7xx_hal_dcmi.c.

References __HAL_DCMI_ENABLE_IT, DCMI_IT_FRAME, DCMI_MODE_SNAPSHOT, DCMI_HandleTypeDef::DMA_Handle, HAL_DCMI_STATE_READY, HAL_DMAEx_ChangeMemory(), DCMI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, MEMORY0, MEMORY1, DCMI_HandleTypeDef::pBuffPtr, DCMI_HandleTypeDef::State, DCMI_HandleTypeDef::XferCount, DCMI_HandleTypeDef::XferSize, and DCMI_HandleTypeDef::XferTransferNumber.

Referenced by HAL_DCMI_Start_DMA().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DCMI Exported Types

Data Structures | Enumerations
DCMI Exported Types
DCMI

Data Structures

struct | DCMI_CodesInitTypeDef
DCMI Embedded Synchronisation CODE Init structure definition. More...
struct | DCMI_InitTypeDef
DCMI Init structure definition. More...
struct | DCMI_HandleTypeDef
DCMI handle Structure definition. More...

Enumerations

enum HAL_DCMI_StateTypeDef {
HAL_DCMI_STATE_RESET = 0x00U, HAL_DCMI_STATE_READY = 0x01U, HAL_DCMI_STATE_BUSY = 0x02U, HAL_DCMI_STATE_TIMEOUT = 0x03U,
HAL_DCMI_STATE_ERROR = 0x04U, HAL_DCMI_STATE_SUSPENDED = 0x05U
}
HAL DCMI State structures definition. More...

Enumeration Type Documentation

enum HAL_DCMI_StateTypeDef

HAL DCMI State structures definition.

Enumerator:
HAL_DCMI_STATE_RESET

DCMI not yet initialized or disabled

HAL_DCMI_STATE_READY

DCMI initialized and ready for use

HAL_DCMI_STATE_BUSY

DCMI internal processing is ongoing

HAL_DCMI_STATE_TIMEOUT

DCMI timeout state

HAL_DCMI_STATE_ERROR

DCMI error state

HAL_DCMI_STATE_SUSPENDED

DCMI suspend state

Definition at line 66 of file stm32h7xx_hal_dcmi.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DCMI_CodesInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DCMI_CodesInitTypeDef Struct Reference
DCMI Exported Types

DCMI Embedded Synchronisation CODE Init structure definition. More...

#include <stm32h7xx_hal_dcmi.h>

Data Fields

uint8_t | FrameStartCode
uint8_t | LineStartCode
uint8_t | LineEndCode
uint8_t | FrameEndCode

Detailed Description

DCMI Embedded Synchronisation CODE Init structure definition.

Definition at line 79 of file stm32h7xx_hal_dcmi.h.

Field Documentation

uint8_t DCMI_CodesInitTypeDef::FrameEndCode

Specifies the code of the frame end delimiter.

Definition at line 84 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint8_t DCMI_CodesInitTypeDef::FrameStartCode

Specifies the code of the frame start delimiter.

Definition at line 81 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint8_t DCMI_CodesInitTypeDef::LineEndCode

Specifies the code of the line end delimiter.

Definition at line 83 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint8_t DCMI_CodesInitTypeDef::LineStartCode

Specifies the code of the line start delimiter.

Definition at line 82 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dcmi.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DCMI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DCMI_InitTypeDef Struct Reference
DCMI Exported Types

DCMI Init structure definition. More...

#include <stm32h7xx_hal_dcmi.h>

Data Fields

uint32_t | SynchroMode
uint32_t | PCKPolarity
uint32_t | VSPolarity
uint32_t | HSPolarity
uint32_t | CaptureRate
uint32_t | ExtendedDataMode
DCMI_CodesInitTypeDef SyncroCode
uint32_t | JPEGMode
uint32_t | ByteSelectMode
uint32_t | ByteSelectStart
uint32_t | LineSelectMode
uint32_t | LineSelectStart

Detailed Description

DCMI Init structure definition.

Definition at line 90 of file stm32h7xx_hal_dcmi.h.

Field Documentation

uint32_t DCMI_InitTypeDef::ByteSelectMode

Specifies the data to be captured by the interface This parameter can be a value of DCMI Byte Select Mode

Definition at line 116 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::ByteSelectStart

Specifies if the data to be captured by the interface is even or odd This parameter can be a value of DCMI Byte Select Start

Definition at line 119 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::CaptureRate

Specifies the frequency of frame capture: All, 1/2 or 1/4. This parameter can be a value of DCMI Capture Rate

Definition at line 104 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::ExtendedDataMode

Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. This parameter can be a value of DCMI Extended Data Mode

Definition at line 107 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::HSPolarity

Specifies the Horizontal synchronization polarity: High or Low. This parameter can be a value of DCMI HSYNC Polarity

Definition at line 101 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::JPEGMode

Enable or Disable the JPEG mode. This parameter can be a value of DCMI MODE JPEG

Definition at line 113 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::LineSelectMode

Specifies the line of data to be captured by the interface This parameter can be a value of DCMI Line Select Mode

Definition at line 122 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::LineSelectStart

Specifies if the line of data to be captured by the interface is even or odd This parameter can be a value of DCMI Line Select Start

Definition at line 125 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::PCKPolarity

Specifies the Pixel clock polarity: Falling or Rising. This parameter can be a value of DCMI PIXCK Polarity

Definition at line 95 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::SynchroMode

Specifies the Synchronization Mode: Hardware or Embedded. This parameter can be a value of DCMI Synchronization Mode

Definition at line 92 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

DCMI_CodesInitTypeDef DCMI_InitTypeDef::SyncroCode

Specifies the code of the line/frame start delimiter and the line/frame end delimiter

Definition at line 110 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::VSPolarity

Specifies the Vertical synchronization polarity: High or Low. This parameter can be a value of DCMI VSYNC Polarity

Definition at line 98 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dcmi.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DCMI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DCMI_HandleTypeDef Struct Reference
DCMI Exported Types

DCMI handle Structure definition. More...

#include <stm32h7xx_hal_dcmi.h>

Data Fields

DCMI_TypeDef * | Instance
DCMI_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_DCMI_StateTypeDef | State
__IO uint32_t | XferCount
__IO uint32_t | XferSize
uint32_t | XferTransferNumber
uint32_t | pBuffPtr
DMA_HandleTypeDef * DMA_Handle
__IO uint32_t | ErrorCode

Detailed Description

DCMI handle Structure definition.

Definition at line 132 of file stm32h7xx_hal_dcmi.h.

Field Documentation

DMA_HandleTypeDef* DCMI_HandleTypeDef::DMA_Handle

Pointer to the DMA handler

Definition at line 150 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAError(), DCMI_DMAXferCplt(), HAL_DCMI_IRQHandler(), HAL_DCMI_Start_DMA(), and HAL_DCMI_Stop().

__IO uint32_t DCMI_HandleTypeDef::ErrorCode

DCMI Error code

Definition at line 152 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAError(), HAL_DCMI_DeInit(), HAL_DCMI_GetError(), HAL_DCMI_Init(), HAL_DCMI_IRQHandler(), HAL_DCMI_Stop(), and HAL_DCMI_Suspend().

DCMI_InitTypeDef DCMI_HandleTypeDef::Init

DCMI parameters

Definition at line 136 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

DCMI_TypeDef* DCMI_HandleTypeDef::Instance

DCMI Register base address

Definition at line 134 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAXferCplt(), HAL_DCMI_ConfigCrop(), HAL_DCMI_DisableCrop(), HAL_DCMI_EnableCrop(), HAL_DCMI_Init(), HAL_DCMI_IRQHandler(), HAL_DCMI_Resume(), HAL_DCMI_Start_DMA(), HAL_DCMI_Stop(), and HAL_DCMI_Suspend().

HAL_LockTypeDef DCMI_HandleTypeDef::Lock

DCMI locking object

Definition at line 138 of file stm32h7xx_hal_dcmi.h.

uint32_t DCMI_HandleTypeDef::pBuffPtr

Pointer to DMA output buffer

Definition at line 148 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAXferCplt(), and HAL_DCMI_Start_DMA().

__IO HAL_DCMI_StateTypeDef DCMI_HandleTypeDef::State

DCMI state

Definition at line 140 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAError(), DCMI_DMAXferCplt(), HAL_DCMI_ConfigCrop(), HAL_DCMI_DeInit(), HAL_DCMI_DisableCrop(), HAL_DCMI_EnableCrop(), HAL_DCMI_GetState(), HAL_DCMI_Init(), HAL_DCMI_IRQHandler(), HAL_DCMI_Resume(), HAL_DCMI_Start_DMA(), HAL_DCMI_Stop(), and HAL_DCMI_Suspend().

__IO uint32_t DCMI_HandleTypeDef::XferCount

DMA transfer counter

Definition at line 142 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAXferCplt(), and HAL_DCMI_Start_DMA().

__IO uint32_t DCMI_HandleTypeDef::XferSize

DMA transfer size

Definition at line 144 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAXferCplt(), and HAL_DCMI_Start_DMA().

uint32_t DCMI_HandleTypeDef::XferTransferNumber

DMA transfer number

Definition at line 146 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAXferCplt(), and HAL_DCMI_Start_DMA().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dcmi.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DCMI Error Code

Defines
DCMI Error Code
DCMI Exported Constants

Defines

#define | HAL_DCMI_ERROR_NONE (0x00000000U)
#define | HAL_DCMI_ERROR_OVR (0x00000001U)
#define | HAL_DCMI_ERROR_SYNC (0x00000002U)
#define | HAL_DCMI_ERROR_TIMEOUT (0x00000020U)
#define | HAL_DCMI_ERROR_DMA (0x00000040U)

Define Documentation

#define HAL_DCMI_ERROR_DMA (0x00000040U)

DMA error

Definition at line 171 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAError().

#define HAL_DCMI_ERROR_NONE (0x00000000U)

No error

Definition at line 167 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_DeInit(), HAL_DCMI_Init(), and HAL_DCMI_Stop().

#define HAL_DCMI_ERROR_OVR (0x00000001U)

Overrun error

Definition at line 168 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define HAL_DCMI_ERROR_SYNC (0x00000002U)

Synchronization error

Definition at line 169 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define HAL_DCMI_ERROR_TIMEOUT (0x00000020U)

Timeout error

Definition at line 170 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Stop(), and HAL_DCMI_Suspend().

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STM32H753xx HAL User Manual: DCMI Capture Mode

Defines
DCMI Capture Mode
DCMI Exported Constants

Defines

#define | DCMI_MODE_CONTINUOUS (0x00000000U)
#define | DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM)

Define Documentation

#define DCMI_MODE_CONTINUOUS (0x00000000U)

The received data are transferred continuously into the destination memory through the DMA

Definition at line 179 of file stm32h7xx_hal_dcmi.h.

#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM)

Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA

Definition at line 181 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAXferCplt(), and HAL_DCMI_IRQHandler().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DCMI Synchronization Mode

Defines
DCMI Synchronization Mode
DCMI Exported Constants

Defines

#define | DCMI_SYNCHRO_HARDWARE (0x00000000U)
#define | DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS)

Define Documentation

#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS)

Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow

Definition at line 192 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define DCMI_SYNCHRO_HARDWARE (0x00000000U)

Hardware synchronization data capture (frame/line start/stop) is synchronized with the HSYNC/VSYNC signals

Definition at line 190 of file stm32h7xx_hal_dcmi.h.

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STM32H753xx HAL User Manual: DCMI PIXCK Polarity

Defines
DCMI PIXCK Polarity
DCMI Exported Constants

Defines

#define | DCMI_PCKPOLARITY_FALLING (0x00000000U)
#define | DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL)

Define Documentation

#define DCMI_PCKPOLARITY_FALLING (0x00000000U)

Pixel clock active on Falling edge

Definition at line 202 of file stm32h7xx_hal_dcmi.h.

#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL)

Pixel clock active on Rising edge

Definition at line 203 of file stm32h7xx_hal_dcmi.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DCMI VSYNC Polarity

Defines
DCMI VSYNC Polarity
DCMI Exported Constants

Defines

#define | DCMI_VSPOLARITY_LOW (0x00000000U)
#define | DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL)

Define Documentation

#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL)

Vertical synchronization active High

Definition at line 213 of file stm32h7xx_hal_dcmi.h.

#define DCMI_VSPOLARITY_LOW (0x00000000U)

Vertical synchronization active Low

Definition at line 212 of file stm32h7xx_hal_dcmi.h.

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STM32H753xx HAL User Manual: DCMI HSYNC Polarity

Defines
DCMI HSYNC Polarity
DCMI Exported Constants

Defines

#define | DCMI_HSPOLARITY_LOW (0x00000000U)
#define | DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL)

Define Documentation

#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL)

Horizontal synchronization active High

Definition at line 223 of file stm32h7xx_hal_dcmi.h.

#define DCMI_HSPOLARITY_LOW (0x00000000U)

Horizontal synchronization active Low

Definition at line 222 of file stm32h7xx_hal_dcmi.h.

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STM32H753xx HAL User Manual: DCMI MODE JPEG

Defines
DCMI MODE JPEG
DCMI Exported Constants

Defines

#define | DCMI_JPEG_DISABLE (0x00000000U)
#define | DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG)

Define Documentation

#define DCMI_JPEG_DISABLE (0x00000000U)

Mode JPEG Disabled

Definition at line 232 of file stm32h7xx_hal_dcmi.h.

#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG)

Mode JPEG Enabled

Definition at line 233 of file stm32h7xx_hal_dcmi.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DCMI Capture Rate

Defines
DCMI Capture Rate
DCMI Exported Constants

Defines

#define | DCMI_CR_ALL_FRAME (0x00000000U)
#define | DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0)
#define | DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1)

Define Documentation

#define DCMI_CR_ALL_FRAME (0x00000000U)

All frames are captured

Definition at line 242 of file stm32h7xx_hal_dcmi.h.

#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0)

Every alternate frame captured

Definition at line 243 of file stm32h7xx_hal_dcmi.h.

#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1)

One frame in 4 frames captured

Definition at line 244 of file stm32h7xx_hal_dcmi.h.

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STM32H753xx HAL User Manual: DCMI Extended Data Mode

Defines
DCMI Extended Data Mode
DCMI Exported Constants

Defines

#define | DCMI_EXTEND_DATA_8B (0x00000000U)
#define | DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0)
#define | DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1)
#define | DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))

Define Documentation

#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0)

Interface captures 10-bit data on every pixel clock

Definition at line 254 of file stm32h7xx_hal_dcmi.h.

#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1)

Interface captures 12-bit data on every pixel clock

Definition at line 255 of file stm32h7xx_hal_dcmi.h.

#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))

Interface captures 14-bit data on every pixel clock

Definition at line 256 of file stm32h7xx_hal_dcmi.h.

#define DCMI_EXTEND_DATA_8B (0x00000000U)

Interface captures 8-bit data on every pixel clock

Definition at line 253 of file stm32h7xx_hal_dcmi.h.

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STM32H753xx HAL User Manual: DCMI Window Coordinate

Defines
DCMI Window Coordinate
DCMI Exported Constants

Defines

#define DCMI_WINDOW_COORDINATE (0x3FFFU)

Define Documentation

#define DCMI_WINDOW_COORDINATE (0x3FFFU)

Window coordinate

Definition at line 265 of file stm32h7xx_hal_dcmi.h.

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STM32H753xx HAL User Manual: DCMI Window Height

Defines
DCMI Window Height
DCMI Exported Constants

Defines

#define DCMI_WINDOW_HEIGHT (0x1FFFU)

Define Documentation

#define DCMI_WINDOW_HEIGHT (0x1FFFU)

Window Height

Definition at line 274 of file stm32h7xx_hal_dcmi.h.

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STM32H753xx HAL User Manual: DCMI interrupt sources

Defines
DCMI interrupt sources
DCMI Exported Constants

Defines

#define | DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE)
#define | DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE)
#define | DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE)
#define | DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE)
#define | DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE)

Define Documentation

#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE)

Synchronization error interrupt

Definition at line 285 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init(), and HAL_DCMI_IRQHandler().

#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE)

Capture complete interrupt

Definition at line 283 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAXferCplt(), and HAL_DCMI_IRQHandler().

#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE)

Line interrupt

Definition at line 287 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init(), and HAL_DCMI_IRQHandler().

#define DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE)

Overrun interrupt

Definition at line 284 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init(), and HAL_DCMI_IRQHandler().

#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE)

VSYNC interrupt

Definition at line 286 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init(), and HAL_DCMI_IRQHandler().

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STM32H753xx HAL User Manual: DCMI Flags

Defines
DCMI Flags
DCMI Exported Constants

Defines

#define | DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC)
DCMI SR register.
#define | DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC)
#define | DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE)
#define | DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS)
DCMI RIS register.
#define | DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS)
#define | DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS)
#define | DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS)
#define | DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS)
#define | DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS)
DCMI MIS register.
#define | DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS )
#define | DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS )
#define | DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS)
#define | DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS )

Define Documentation

#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS )

DCMI Synchronization error masked interrupt status

Definition at line 315 of file stm32h7xx_hal_dcmi.h.

#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS)

Synchronization error interrupt flag

Definition at line 307 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE)

FIFO not empty flag

Definition at line 301 of file stm32h7xx_hal_dcmi.h.

#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS)

DCMI MIS register.

DCMI Frame capture complete masked interrupt status

Definition at line 313 of file stm32h7xx_hal_dcmi.h.

#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS)

DCMI RIS register.

Frame capture complete interrupt flag

Definition at line 305 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC)

DCMI SR register.

HSYNC pin state (active line / synchronization between lines)

Definition at line 299 of file stm32h7xx_hal_dcmi.h.

#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS )

DCMI Line masked interrupt status

Definition at line 317 of file stm32h7xx_hal_dcmi.h.

#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS)

Line interrupt flag

Definition at line 309 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS )

DCMI Overrun masked interrupt status

Definition at line 314 of file stm32h7xx_hal_dcmi.h.

#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS)

Overrun interrupt flag

Definition at line 306 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC)

VSYNC pin state (active frame / synchronization between frames)

Definition at line 300 of file stm32h7xx_hal_dcmi.h.

#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS)

DCMI VSYNC masked interrupt status

Definition at line 316 of file stm32h7xx_hal_dcmi.h.

#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS)

VSYNC interrupt flag

Definition at line 308 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

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STM32H753xx HAL User Manual: DCMI Byte Select Mode

Defines
DCMI Byte Select Mode
DCMI Exported Constants

Defines

#define | DCMI_BSM_ALL (0x00000000U)
#define | DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0)
#define | DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1)
#define | DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1))

Define Documentation

#define DCMI_BSM_ALL (0x00000000U)

Interface captures all received data

Definition at line 325 of file stm32h7xx_hal_dcmi.h.

#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1))

Interface captures two bytes out of four

Definition at line 328 of file stm32h7xx_hal_dcmi.h.

#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1)

Interface captures one byte out of four

Definition at line 327 of file stm32h7xx_hal_dcmi.h.

#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0)

Interface captures every other byte from the received data

Definition at line 326 of file stm32h7xx_hal_dcmi.h.

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STM32H753xx HAL User Manual: DCMI Byte Select Start

Defines
DCMI Byte Select Start
DCMI Exported Constants

Defines

#define | DCMI_OEBS_ODD (0x00000000U)
#define | DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS)

Define Documentation

#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS)

Interface captures second data from the frame/line start, first one being dropped

Definition at line 338 of file stm32h7xx_hal_dcmi.h.

#define DCMI_OEBS_ODD (0x00000000U)

Interface captures first data from the frame/line start, second one being dropped

Definition at line 337 of file stm32h7xx_hal_dcmi.h.

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STM32H753xx HAL User Manual: DCMI Line Select Mode

Defines
DCMI Line Select Mode
DCMI Exported Constants

Defines

#define | DCMI_LSM_ALL (0x00000000U)
#define | DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM)

Define Documentation

#define DCMI_LSM_ALL (0x00000000U)

Interface captures all received lines

Definition at line 347 of file stm32h7xx_hal_dcmi.h.

#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM)

Interface captures one line out of two

Definition at line 348 of file stm32h7xx_hal_dcmi.h.

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STM32H753xx HAL User Manual: DCMI Line Select Start

Defines
DCMI Line Select Start
DCMI Exported Constants

Defines

#define | DCMI_OELS_ODD (0x00000000U)
#define | DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS)

Define Documentation

#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS)

Interface captures second line from the frame start, first one being dropped

Definition at line 358 of file stm32h7xx_hal_dcmi.h.

#define DCMI_OELS_ODD (0x00000000U)

Interface captures first line from the frame start, second one being dropped

Definition at line 357 of file stm32h7xx_hal_dcmi.h.

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STM32H753xx HAL User Manual: DCMI Exported Macros

Defines
DCMI Exported Macros
DCMI

Defines

#define | __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
Reset DCMI handle state.
#define | __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
Enable the DCMI.
#define | __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
Disable the DCMI.
#define | __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)
Get the DCMI pending flag.
#define | __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the DCMI pending flags.
#define | __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified DCMI interrupts.
#define | __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
Disable the specified DCMI interrupts.
#define | __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
Check whether the specified DCMI interrupt has occurred or not.

Define Documentation

#define __HAL_DCMI_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the DCMI pending flags.

Parameters:
__HANDLE__,: DCMI handle
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • DCMI_FLAG_FRAMERI: Frame capture complete flag mask
  • DCMI_FLAG_OVFRI: Overflow flag mask
  • DCMI_FLAG_ERRRI: Synchronization error flag mask
  • DCMI_FLAG_VSYNCRI: VSYNC flag mask
  • DCMI_FLAG_LINERI: Line flag mask
Return values:
None

Definition at line 430 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define __HAL_DCMI_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))

Disable the DCMI.

Parameters:
__HANDLE__,: DCMI handle
Return values:
None

Definition at line 391 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Stop().

#define __HAL_DCMI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))

Disable the specified DCMI interrupts.

Parameters:
__HANDLE__,: DCMI handle
__INTERRUPT__,: specifies the DCMI interrupt sources to be enabled. This parameter can be any combination of the following values:
  • DCMI_IT_FRAME: Frame capture complete interrupt mask
  • DCMI_IT_OVF: Overflow interrupt mask
  • DCMI_IT_ERR: Synchronization error interrupt mask
  • DCMI_IT_VSYNC: VSYNC interrupt mask
  • DCMI_IT_LINE: Line interrupt mask
Return values:
None

Definition at line 458 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define __HAL_DCMI_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)

Enable the DCMI.

Parameters:
__HANDLE__,: DCMI handle
Return values:
None

Definition at line 384 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Start_DMA().

#define __HAL_DCMI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enable the specified DCMI interrupts.

Parameters:
__HANDLE__,: DCMI handle
__INTERRUPT__,: specifies the DCMI interrupt sources to be enabled. This parameter can be any combination of the following values:
  • DCMI_IT_FRAME: Frame capture complete interrupt mask
  • DCMI_IT_OVF: Overflow interrupt mask
  • DCMI_IT_ERR: Synchronization error interrupt mask
  • DCMI_IT_VSYNC: VSYNC interrupt mask
  • DCMI_IT_LINE: Line interrupt mask
Return values:
None

Definition at line 444 of file stm32h7xx_hal_dcmi.h.

Referenced by DCMI_DMAXferCplt(), and HAL_DCMI_Init().

#define __HAL_DCMI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\
 (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))

Get the DCMI pending flag.

Parameters:
__HANDLE__,: DCMI handle
__FLAG__,: Get the specified flag. This parameter can be one of the following values (no combination allowed)
  • DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
  • DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
  • DCMI_FLAG_FNE: FIFO empty flag
  • DCMI_FLAG_FRAMERI: Frame capture complete flag mask
  • DCMI_FLAG_OVRRI: Overrun flag mask
  • DCMI_FLAG_ERRRI: Synchronization error flag mask
  • DCMI_FLAG_VSYNCRI: VSYNC flag mask
  • DCMI_FLAG_LINERI: Line flag mask
  • DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
  • DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
  • DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
  • DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
  • DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
Return values:
The state of FLAG.

Definition at line 414 of file stm32h7xx_hal_dcmi.h.

#define __HAL_DCMI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))

Check whether the specified DCMI interrupt has occurred or not.

Parameters:
__HANDLE__,: DCMI handle
__INTERRUPT__,: specifies the DCMI interrupt source to check. This parameter can be one of the following values:
  • DCMI_IT_FRAME: Frame capture complete interrupt mask
  • DCMI_IT_OVF: Overflow interrupt mask
  • DCMI_IT_ERR: Synchronization error interrupt mask
  • DCMI_IT_VSYNC: VSYNC interrupt mask
  • DCMI_IT_LINE: Line interrupt mask
Return values:
The state of INTERRUPT.

Definition at line 472 of file stm32h7xx_hal_dcmi.h.

#define __HAL_DCMI_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)

Reset DCMI handle state.

Parameters:
__HANDLE__,: specifies the DCMI handle.
Return values:
None

Definition at line 377 of file stm32h7xx_hal_dcmi.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DCMI Private Constants

Defines
DCMI Private Constants
DCMI

Defines

#define | DCMI_MIS_INDEX (0x1000)
#define | DCMI_SR_INDEX (0x2000)

Define Documentation

#define DCMI_MIS_INDEX (0x1000)

DCMI MIS register index

Definition at line 544 of file stm32h7xx_hal_dcmi.h.

#define DCMI_SR_INDEX (0x2000)

DCMI SR register index

Definition at line 545 of file stm32h7xx_hal_dcmi.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DCMI Private Macros

Defines
DCMI Private Macros
DCMI

Defines

#define | IS_DCMI_CAPTURE_MODE(MODE)
#define | IS_DCMI_SYNCHRO(MODE)
#define | IS_DCMI_PCKPOLARITY(POLARITY)
#define | IS_DCMI_VSPOLARITY(POLARITY)
#define | IS_DCMI_HSPOLARITY(POLARITY)
#define | IS_DCMI_MODE_JPEG(JPEG_MODE)
#define | IS_DCMI_CAPTURE_RATE(RATE)
#define | IS_DCMI_EXTENDED_DATA(DATA)
#define | IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
#define | IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
#define | IS_DCMI_BYTE_SELECT_MODE(MODE)
#define | IS_DCMI_BYTE_SELECT_START(POLARITY)
#define | IS_DCMI_LINE_SELECT_MODE(MODE)
#define | IS_DCMI_LINE_SELECT_START(POLARITY)

Define Documentation

#define IS_DCMI_BYTE_SELECT_MODE ( MODE )
Value:
(((MODE) == DCMI_BSM_ALL) || \
                                       ((MODE) == DCMI_BSM_OTHER) || \
                                       ((MODE) == DCMI_BSM_ALTERNATE_4) || \
                                       ((MODE) == DCMI_BSM_ALTERNATE_2))

Definition at line 584 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_BYTE_SELECT_START ( POLARITY )
Value:
(((POLARITY) == DCMI_OEBS_ODD) || \
                                            ((POLARITY) == DCMI_OEBS_EVEN))

Definition at line 589 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_CAPTURE_MODE ( MODE )
Value:
(((MODE) == DCMI_MODE_CONTINUOUS) || \
                                   ((MODE) == DCMI_MODE_SNAPSHOT))

Definition at line 553 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Start_DMA().

#define IS_DCMI_CAPTURE_RATE ( RATE )
Value:
(((RATE) == DCMI_CR_ALL_FRAME)         || \
                                    ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
                                    ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))

Definition at line 571 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_EXTENDED_DATA ( DATA )
Value:
(((DATA) == DCMI_EXTEND_DATA_8B)  || \
                                    ((DATA) == DCMI_EXTEND_DATA_10B) || \
                                    ((DATA) == DCMI_EXTEND_DATA_12B) || \
                                    ((DATA) == DCMI_EXTEND_DATA_14B))

Definition at line 575 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_HSPOLARITY ( POLARITY )
Value:
(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
                                     ((POLARITY) == DCMI_HSPOLARITY_HIGH))

Definition at line 565 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_LINE_SELECT_MODE ( MODE )
Value:
(((MODE) == DCMI_LSM_ALL) || \
                                       ((MODE) == DCMI_LSM_ALTERNATE_2))

Definition at line 592 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_LINE_SELECT_START ( POLARITY )
Value:
(((POLARITY) == DCMI_OELS_ODD) || \
                                            ((POLARITY) == DCMI_OELS_EVEN))

Definition at line 595 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_MODE_JPEG ( JPEG_MODE )
Value:
(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
                                     ((JPEG_MODE) == DCMI_JPEG_ENABLE))

Definition at line 568 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_PCKPOLARITY ( POLARITY )
Value:
(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
                                      ((POLARITY) == DCMI_PCKPOLARITY_RISING))

Definition at line 559 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_SYNCHRO ( MODE )
Value:
(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
                              ((MODE) == DCMI_SYNCHRO_EMBEDDED))

Definition at line 556 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_VSPOLARITY ( POLARITY )
Value:
(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
                                     ((POLARITY) == DCMI_VSPOLARITY_HIGH))

Definition at line 562 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_WINDOW_COORDINATE ( COORDINATE ) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)

Definition at line 580 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_ConfigCrop().

#define IS_DCMI_WINDOW_HEIGHT ( HEIGHT ) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)

Definition at line 582 of file stm32h7xx_hal_dcmi.h.

Referenced by HAL_DCMI_ConfigCrop().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DCMI

Modules | Defines
DCMI
STM32H7xx_HAL_Driver

DCMI HAL module driver. More...

Modules

DCMI Exported Functions
DCMI Exported Types
DCMI Exported Constants
DCMI Exported Macros
DCMI Private Constants
DCMI Private Macros
DCMI Private Functions

Defines

#define | HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* Set timeout to 1s */
#define | DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE)
#define | DCMI_POSITION_CWSTRT_VST (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST)
#define | DCMI_POSITION_ESCR_LSC (uint32_t)POSITION_VAL(DCMI_ESCR_LSC)
#define | DCMI_POSITION_ESCR_LEC (uint32_t)POSITION_VAL(DCMI_ESCR_LEC)
#define | DCMI_POSITION_ESCR_FEC (uint32_t)POSITION_VAL(DCMI_ESCR_FEC)

Detailed Description

DCMI HAL module driver.

Define Documentation

#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE)

Required left shift to set crop window vertical line count

Definition at line 110 of file stm32h7xx_hal_dcmi.c.

Referenced by HAL_DCMI_ConfigCrop().

#define DCMI_POSITION_CWSTRT_VST (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST)

Required left shift to set crop window vertical start line count

Definition at line 111 of file stm32h7xx_hal_dcmi.c.

Referenced by HAL_DCMI_ConfigCrop().

#define DCMI_POSITION_ESCR_FEC (uint32_t)POSITION_VAL(DCMI_ESCR_FEC)

Required left shift to set frame end delimiter

Definition at line 115 of file stm32h7xx_hal_dcmi.c.

Referenced by HAL_DCMI_Init().

#define DCMI_POSITION_ESCR_LEC (uint32_t)POSITION_VAL(DCMI_ESCR_LEC)

Required left shift to set line end delimiter

Definition at line 114 of file stm32h7xx_hal_dcmi.c.

Referenced by HAL_DCMI_Init().

#define DCMI_POSITION_ESCR_LSC (uint32_t)POSITION_VAL(DCMI_ESCR_LSC)

Required left shift to set line start delimiter

Definition at line 113 of file stm32h7xx_hal_dcmi.c.

Referenced by HAL_DCMI_Init().

#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* Set timeout to 1s */

Definition at line 108 of file stm32h7xx_hal_dcmi.c.

Referenced by HAL_DCMI_Stop(), and HAL_DCMI_Suspend().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DFSDM Private Define

Defines
DFSDM Private Define
DFSDM

Defines

#define | DFSDM_CHCFGR1_CLK_DIV_OFFSET POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV)
#define | DFSDM_CHAWSCDR_BKSCD_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_BKSCD)
#define | DFSDM_CHAWSCDR_FOSR_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR)
#define | DFSDM_CHCFGR2_OFFSET_OFFSET POSITION_VAL(DFSDM_CHCFGR2_OFFSET)
#define | DFSDM_CHCFGR2_DTRBS_OFFSET POSITION_VAL(DFSDM_CHCFGR2_DTRBS)
#define | DFSDM_FLTFCR_FOSR_OFFSET POSITION_VAL(DFSDM_FLTFCR_FOSR)
#define | DFSDM_FLTCR1_MSB_RCH_OFFSET 8
#define | DFSDM_FLTCR2_EXCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_EXCH)
#define | DFSDM_FLTCR2_AWDCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_AWDCH)
#define | DFSDM_FLTISR_CKABF_OFFSET POSITION_VAL(DFSDM_FLTISR_CKABF)
#define | DFSDM_FLTISR_SCDF_OFFSET POSITION_VAL(DFSDM_FLTISR_SCDF)
#define | DFSDM_FLTICR_CLRCKABF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRCKABF)
#define | DFSDM_FLTICR_CLRSCDF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRSCDF)
#define | DFSDM_FLTRDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTRDATAR_RDATA)
#define | DFSDM_FLTJDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTJDATAR_JDATA)
#define | DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT)
#define | DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT)
#define | DFSDM_FLTEXMAX_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMAX_EXMAX)
#define | DFSDM_FLTEXMIN_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMIN_EXMIN)
#define | DFSDM_FLTCNVTIMR_DATA_OFFSET POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT)
#define | DFSDM_FLTAWSR_HIGH_OFFSET POSITION_VAL(DFSDM_FLTAWSR_AWHTF)
#define | DFSDM_MSB_MASK 0xFFFF0000
#define | DFSDM_LSB_MASK 0x0000FFFF
#define | DFSDM_CKAB_TIMEOUT 5000
#define | DFSDM1_CHANNEL_NUMBER 8

Define Documentation

#define DFSDM1_CHANNEL_NUMBER 8

Definition at line 232 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_IRQHandler().

#define DFSDM_CHAWSCDR_BKSCD_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_BKSCD)

Definition at line 209 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelScdStart(), and HAL_DFSDM_ChannelScdStart_IT().

#define DFSDM_CHAWSCDR_FOSR_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR)

Definition at line 210 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelInit().

#define DFSDM_CHCFGR1_CLK_DIV_OFFSET POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV)

Definition at line 208 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelInit().

#define DFSDM_CHCFGR2_DTRBS_OFFSET POSITION_VAL(DFSDM_CHCFGR2_DTRBS)

Definition at line 212 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelInit().

#define DFSDM_CHCFGR2_OFFSET_OFFSET POSITION_VAL(DFSDM_CHCFGR2_OFFSET)

Definition at line 211 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelInit(), and HAL_DFSDM_ChannelModifyOffset().

#define DFSDM_CKAB_TIMEOUT 5000

Definition at line 231 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelCkabStart(), and HAL_DFSDM_ChannelCkabStart_IT().

#define DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT)

Definition at line 223 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

#define DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT)

Definition at line 224 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

#define DFSDM_FLTAWSR_HIGH_OFFSET POSITION_VAL(DFSDM_FLTAWSR_AWHTF)

Definition at line 228 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_IRQHandler().

#define DFSDM_FLTCNVTIMR_DATA_OFFSET POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT)

Definition at line 227 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterGetConvTimeValue().

#define DFSDM_FLTCR1_MSB_RCH_OFFSET 8

Definition at line 214 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterConfigRegChannel().

#define DFSDM_FLTCR2_AWDCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_AWDCH)

Definition at line 216 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

#define DFSDM_FLTCR2_EXCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_EXCH)

Definition at line 215 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterExdStart().

#define DFSDM_FLTEXMAX_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMAX_EXMAX)

Definition at line 225 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterGetExdMaxValue().

#define DFSDM_FLTEXMIN_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMIN_EXMIN)

Definition at line 226 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterGetExdMinValue().

#define DFSDM_FLTFCR_FOSR_OFFSET POSITION_VAL(DFSDM_FLTFCR_FOSR)

Definition at line 213 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterInit().

#define DFSDM_FLTICR_CLRCKABF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRCKABF)

Definition at line 219 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelCkabStart(), HAL_DFSDM_ChannelCkabStart_IT(), HAL_DFSDM_ChannelCkabStop(), HAL_DFSDM_ChannelCkabStop_IT(), HAL_DFSDM_ChannelPollForCkab(), and HAL_DFSDM_IRQHandler().

#define DFSDM_FLTICR_CLRSCDF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRSCDF)

Definition at line 220 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelPollForScd(), HAL_DFSDM_ChannelScdStop(), HAL_DFSDM_ChannelScdStop_IT(), and HAL_DFSDM_IRQHandler().

#define DFSDM_FLTISR_CKABF_OFFSET POSITION_VAL(DFSDM_FLTISR_CKABF)

Definition at line 217 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelCkabStart(), HAL_DFSDM_ChannelCkabStart_IT(), HAL_DFSDM_ChannelPollForCkab(), and HAL_DFSDM_IRQHandler().

#define DFSDM_FLTISR_SCDF_OFFSET POSITION_VAL(DFSDM_FLTISR_SCDF)

Definition at line 218 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelPollForScd(), and HAL_DFSDM_IRQHandler().

#define DFSDM_FLTJDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTJDATAR_JDATA)

Definition at line 222 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterGetInjectedValue().

#define DFSDM_FLTRDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTRDATAR_RDATA)

Definition at line 221 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterGetRegularValue().

#define DFSDM_LSB_MASK 0x0000FFFF

Definition at line 230 of file stm32h7xx_hal_dfsdm.c.

Referenced by DFSDM_GetInjChannelsNbr(), HAL_DFSDM_FilterAwdStart_IT(), HAL_DFSDM_FilterConfigInjChannel(), and HAL_DFSDM_FilterExdStart().

#define DFSDM_MSB_MASK 0xFFFF0000

Definition at line 229 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterConfigRegChannel().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DFSDM Private Variables

Variables
DFSDM Private Variables
DFSDM

Variables

__IO uint32_t | v_dfsdm1ChannelCounter = 0
DFSDM_Channel_HandleTypeDef * | a_dfsdm1ChannelHandle [DFSDM1_CHANNEL_NUMBER] = {NULL}

Variable Documentation

DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL}

Definition at line 243 of file stm32h7xx_hal_dfsdm.c.

__IO uint32_t v_dfsdm1ChannelCounter = 0

Definition at line 242 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelDeInit(), and HAL_DFSDM_ChannelInit().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DFSDM Private Functions

Functions
DFSDM Private Functions
DFSDM

Functions

static uint32_t | DFSDM_GetInjChannelsNbr (uint32_t Channels)
This function allows to get the number of injected channels.
static uint32_t | DFSDM_GetChannelFromInstance (DFSDM_Channel_TypeDef *Instance)
This function allows to get the channel number from channel instance.
static void | DFSDM_RegConvStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really start regular conversion.
static void | DFSDM_RegConvStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really stop regular conversion.
static void | DFSDM_InjConvStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really start injected conversion.
static void | DFSDM_InjConvStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really stop injected conversion.
static void | DFSDM_DMARegularHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback for regular conversion.
static void | DFSDM_DMARegularConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback for regular conversion.
static void | DFSDM_DMAInjectedHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback for injected conversion.
static void | DFSDM_DMAInjectedConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback for injected conversion.
static void | DFSDM_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Function Documentation

static void DFSDM_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA error callback.

Parameters:
hdma : DMA handle.
Return values:
None

Definition at line 2761 of file stm32h7xx_hal_dfsdm.c.

References DFSDM_FILTER_ERROR_DMA, DFSDM_Filter_HandleTypeDef::ErrorCode, and HAL_DFSDM_FilterErrorCallback().

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), and HAL_DFSDM_FilterRegularStart_DMA().

static void DFSDM_DMAInjectedConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA transfer complete callback for injected conversion.

Parameters:
hdma : DMA handle.
Return values:
None

Definition at line 2747 of file stm32h7xx_hal_dfsdm.c.

References HAL_DFSDM_FilterInjConvCpltCallback().

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), and HAL_DFSDM_FilterInjectedStart_DMA().

static void DFSDM_DMAInjectedHalfConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA half transfer complete callback for injected conversion.

Parameters:
hdma : DMA handle.
Return values:
None

Definition at line 2733 of file stm32h7xx_hal_dfsdm.c.

References HAL_DFSDM_FilterInjConvHalfCpltCallback().

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), and HAL_DFSDM_FilterInjectedStart_DMA().

static void DFSDM_DMARegularConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA transfer complete callback for regular conversion.

Parameters:
hdma : DMA handle.
Return values:
None

Definition at line 2719 of file stm32h7xx_hal_dfsdm.c.

References HAL_DFSDM_FilterRegConvCpltCallback().

Referenced by HAL_DFSDM_FilterRegularMsbStart_DMA(), and HAL_DFSDM_FilterRegularStart_DMA().

static void DFSDM_DMARegularHalfConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA half transfer complete callback for regular conversion.

Parameters:
hdma : DMA handle.
Return values:
None

Definition at line 2705 of file stm32h7xx_hal_dfsdm.c.

References HAL_DFSDM_FilterRegConvHalfCpltCallback().

Referenced by HAL_DFSDM_FilterRegularMsbStart_DMA(), and HAL_DFSDM_FilterRegularStart_DMA().

static uint32_t DFSDM_GetChannelFromInstance ( DFSDM_Channel_TypeDef * Instance ) [static]

This function allows to get the channel number from channel instance.

Parameters:
Instance : DFSDM channel instance.
Return values:
Channel number.

Definition at line 2801 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelCkabStart(), HAL_DFSDM_ChannelCkabStart_IT(), HAL_DFSDM_ChannelCkabStop(), HAL_DFSDM_ChannelCkabStop_IT(), HAL_DFSDM_ChannelDeInit(), HAL_DFSDM_ChannelInit(), HAL_DFSDM_ChannelPollForCkab(), HAL_DFSDM_ChannelPollForScd(), HAL_DFSDM_ChannelScdStop(), and HAL_DFSDM_ChannelScdStop_IT().

static uint32_t DFSDM_GetInjChannelsNbr ( uint32_t Channels ) [static]

This function allows to get the number of injected channels.

Parameters:
Channels : bitfield of injected channels.
Return values:
Number of injected channels.

Definition at line 2778 of file stm32h7xx_hal_dfsdm.c.

References DFSDM_LSB_MASK.

Referenced by HAL_DFSDM_FilterConfigInjChannel().

static void DFSDM_InjConvStart ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter ) [static]

This function allows to really start injected conversion.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 2924 of file stm32h7xx_hal_dfsdm.c.

References DFSDM_FILTER_SW_TRIGGER, DFSDM_FILTER_SYNC_TRIGGER, DFSDM_Filter_HandleTypeDef::ExtTriggerEdge, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, DFSDM_Filter_HandleTypeDef::InjectedTrigger, DFSDM_Filter_HandleTypeDef::Instance, DFSDM_Filter_HandleTypeDef::RegularTrigger, and DFSDM_Filter_HandleTypeDef::State.

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart(), HAL_DFSDM_FilterInjectedStart_DMA(), and HAL_DFSDM_FilterInjectedStart_IT().

static void DFSDM_InjConvStop ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter ) [static]

This function allows to really stop injected conversion.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 2968 of file stm32h7xx_hal_dfsdm.c.

References DFSDM_FILTER_EXT_TRIGGER, DFSDM_FILTER_SW_TRIGGER, DFSDM_FILTER_SYNC_TRIGGER, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, DFSDM_Filter_HandleTypeDef::InjConvRemaining, DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr, DFSDM_Filter_HandleTypeDef::InjectedScanMode, DFSDM_Filter_HandleTypeDef::InjectedTrigger, DFSDM_Filter_HandleTypeDef::Instance, DFSDM_Filter_HandleTypeDef::RegularTrigger, and DFSDM_Filter_HandleTypeDef::State.

Referenced by HAL_DFSDM_FilterInjectedStop(), HAL_DFSDM_FilterInjectedStop_DMA(), and HAL_DFSDM_FilterInjectedStop_IT().

static void DFSDM_RegConvStart ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter ) [static]

This function allows to really start regular conversion.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 2847 of file stm32h7xx_hal_dfsdm.c.

References DFSDM_FILTER_SW_TRIGGER, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, DFSDM_Filter_HandleTypeDef::InjConvRemaining, DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr, DFSDM_Filter_HandleTypeDef::InjectedScanMode, DFSDM_Filter_HandleTypeDef::InjectedTrigger, DFSDM_Filter_HandleTypeDef::Instance, DFSDM_Filter_HandleTypeDef::RegularTrigger, and DFSDM_Filter_HandleTypeDef::State.

Referenced by HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart(), HAL_DFSDM_FilterRegularStart_DMA(), and HAL_DFSDM_FilterRegularStart_IT().

static void DFSDM_RegConvStop ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter ) [static]

This function allows to really stop regular conversion.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 2888 of file stm32h7xx_hal_dfsdm.c.

References DFSDM_FILTER_SW_TRIGGER, DFSDM_FILTER_SYNC_TRIGGER, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, DFSDM_Filter_HandleTypeDef::InjConvRemaining, DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr, DFSDM_Filter_HandleTypeDef::InjectedScanMode, DFSDM_Filter_HandleTypeDef::InjectedTrigger, DFSDM_Filter_HandleTypeDef::Instance, DFSDM_Filter_HandleTypeDef::RegularTrigger, and DFSDM_Filter_HandleTypeDef::State.

Referenced by HAL_DFSDM_FilterRegularStop(), HAL_DFSDM_FilterRegularStop_DMA(), and HAL_DFSDM_FilterRegularStop_IT().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Channel initialization and de-initialization functions

Functions
Channel initialization and de-initialization functions
DFSDM Exported Functions

Channel initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_DFSDM_ChannelInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel according to the specified parameters in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_DFSDM_ChannelDeInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel.
__weak void | HAL_DFSDM_ChannelMspInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel MSP.
__weak void | HAL_DFSDM_ChannelMspDeInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel MSP.

Detailed Description

Channel initialization and de-initialization functions.

  ==============================================================================
        ##### Channel initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the DFSDM channel.
      (+) De-initialize the DFSDM channel.

Function Documentation

HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

De-initialize the DFSDM channel.

Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
HAL status.

Definition at line 386 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_RESET, HAL_DFSDM_ChannelMspDeInit(), DFSDM_Channel_HandleTypeDef::Instance, DFSDM_Channel_HandleTypeDef::State, and v_dfsdm1ChannelCounter.

HAL_StatusTypeDef HAL_DFSDM_ChannelInit ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

Initialize the DFSDM channel according to the specified parameters in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.

Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
HAL status.

Definition at line 292 of file stm32h7xx_hal_dfsdm.c.

References DFSDM_Channel_OutputClockTypeDef::Activation, assert_param, DFSDM_Channel_InitTypeDef::Awd, DFSDM_Channel_InputTypeDef::DataPacking, DFSDM_CHAWSCDR_FOSR_OFFSET, DFSDM_CHCFGR1_CLK_DIV_OFFSET, DFSDM_CHCFGR2_DTRBS_OFFSET, DFSDM_CHCFGR2_OFFSET_OFFSET, DFSDM_GetChannelFromInstance(), DFSDM_Channel_OutputClockTypeDef::Divider, DFSDM_Channel_AwdTypeDef::FilterOrder, HAL_DFSDM_CHANNEL_STATE_READY, HAL_DFSDM_ChannelMspInit(), DFSDM_Channel_HandleTypeDef::Init, DFSDM_Channel_InitTypeDef::Input, DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM_CHANNEL_DATA_PACKING, IS_DFSDM_CHANNEL_FILTER_ORDER, IS_DFSDM_CHANNEL_FILTER_OVS_RATIO, IS_DFSDM_CHANNEL_INPUT, IS_DFSDM_CHANNEL_INPUT_PINS, IS_DFSDM_CHANNEL_OFFSET, IS_DFSDM_CHANNEL_OUTPUT_CLOCK, IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER, IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT, IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE, IS_DFSDM_CHANNEL_SPI_CLOCK, DFSDM_Channel_InputTypeDef::Multiplexer, DFSDM_Channel_InitTypeDef::Offset, DFSDM_Channel_InitTypeDef::OutputClock, DFSDM_Channel_AwdTypeDef::Oversampling, DFSDM_Channel_InputTypeDef::Pins, DFSDM_Channel_InitTypeDef::RightBitShift, DFSDM_Channel_OutputClockTypeDef::Selection, DFSDM_Channel_InitTypeDef::SerialInterface, DFSDM_Channel_SerialInterfaceTypeDef::SpiClock, DFSDM_Channel_HandleTypeDef::State, DFSDM_Channel_SerialInterfaceTypeDef::Type, and v_dfsdm1ChannelCounter.

void HAL_DFSDM_ChannelMspDeInit ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

De-initialize the DFSDM channel MSP.

Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
None

Definition at line 447 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelDeInit().

void HAL_DFSDM_ChannelMspInit ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

Initialize the DFSDM channel MSP.

Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
None

Definition at line 432 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelInit().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Channel operation functions

Functions
Channel operation functions
DFSDM Exported Functions

Channel operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStart (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelPollForCkab (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the clock absence detection.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStop (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStart_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in interrupt mode.
__weak void | HAL_DFSDM_ChannelCkabCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Clock absence detection callback.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStop_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStart (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelPollForScd (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the short circuit detection.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStop (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStart_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in interrupt mode.
__weak void | HAL_DFSDM_ChannelScdCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Short circuit detection callback.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStop_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in interrupt mode.
int16_t | HAL_DFSDM_ChannelGetAwdValue (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get channel analog watchdog value.
HAL_StatusTypeDef | HAL_DFSDM_ChannelModifyOffset (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset)
This function allows to modify channel offset value.

Detailed Description

Channel operation functions.

  ==============================================================================
                   ##### Channel operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Manage clock absence detector feature.
      (+) Manage short circuit detector feature.
      (+) Get analog watchdog value.
      (+) Modify offset value.

Function Documentation

void HAL_DFSDM_ChannelCkabCallback ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

Clock absence detection callback.

Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
None

Definition at line 680 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_IRQHandler().

HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to start clock absence detection in polling mode.

Note:
Same mode has to be used for all channels.
If clock is not available on this channel during 5 seconds, clock absence detection will not be activated and function will return HAL_TIMEOUT error.
Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
HAL status

Definition at line 486 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_CKAB_TIMEOUT, DFSDM_FLTICR_CLRCKABF_OFFSET, DFSDM_FLTISR_CKABF_OFFSET, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, HAL_GetTick(), DFSDM_Channel_HandleTypeDef::Instance, and DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to start clock absence detection in interrupt mode.

Note:
Same mode has to be used for all channels.
If clock is not available on this channel during 5 seconds, clock absence detection will not be activated and function will return HAL_TIMEOUT error.
Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
HAL status

Definition at line 625 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_CKAB_TIMEOUT, DFSDM_FLTICR_CLRCKABF_OFFSET, DFSDM_FLTISR_CKABF_OFFSET, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, HAL_GetTick(), DFSDM_Channel_HandleTypeDef::Instance, and DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to stop clock absence detection in polling mode.

Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
HAL status

Definition at line 589 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTICR_CLRCKABF_OFFSET, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, DFSDM_Channel_HandleTypeDef::Instance, and DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to stop clock absence detection in interrupt mode.

Note:
Interrupt will be disabled for all channels
Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
HAL status

Definition at line 696 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTICR_CLRCKABF_OFFSET, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, DFSDM_Channel_HandleTypeDef::Instance, and DFSDM_Channel_HandleTypeDef::State.

int16_t HAL_DFSDM_ChannelGetAwdValue ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to get channel analog watchdog value.

Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
Channel analog watchdog value.

Definition at line 950 of file stm32h7xx_hal_dfsdm.c.

References DFSDM_Channel_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset | ( | DFSDM_Channel_HandleTypeDef * | hdfsdm_channel,
 |  | int32_t | Offset
 | ) |  |

This function allows to modify channel offset value.

Parameters:
hdfsdm_channel | : DFSDM channel handle.
Offset | : DFSDM channel offset. This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607.
Return values:
HAL status.

Definition at line 962 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_CHCFGR2_OFFSET_OFFSET, HAL_DFSDM_CHANNEL_STATE_READY, DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM_CHANNEL_OFFSET, and DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab | ( | DFSDM_Channel_HandleTypeDef * | hdfsdm_channel,
 |  | uint32_t | Timeout
 | ) |  |

This function allows to poll for the clock absence detection.

Parameters:
hdfsdm_channel | : DFSDM channel handle.
Timeout | : Timeout value in milliseconds.
Return values:
HAL status

Definition at line 539 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTICR_CLRCKABF_OFFSET, DFSDM_FLTISR_CKABF_OFFSET, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, HAL_GetTick(), DFSDM_Channel_HandleTypeDef::Instance, and DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd | ( | DFSDM_Channel_HandleTypeDef * | hdfsdm_channel,
 |  | uint32_t | Timeout
 | ) |  |

This function allows to poll for the short circuit detection.

Parameters:
hdfsdm_channel | : DFSDM channel handle.
Timeout | : Timeout value in milliseconds.
Return values:
HAL status

Definition at line 773 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTICR_CLRSCDF_OFFSET, DFSDM_FLTISR_SCDF_OFFSET, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, HAL_GetTick(), DFSDM_Channel_HandleTypeDef::Instance, and DFSDM_Channel_HandleTypeDef::State.

void HAL_DFSDM_ChannelScdCallback ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

Short circuit detection callback.

Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
None

Definition at line 899 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_IRQHandler().

HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart | ( | DFSDM_Channel_HandleTypeDef * | hdfsdm_channel,
 |  | uint32_t | Threshold,
 |  | uint32_t | BreakSignal
 | ) |  |

This function allows to start short circuit detection in polling mode.

Note:
Same mode has to be used for all channels
Parameters:
hdfsdm_channel | : DFSDM channel handle.
Threshold | : Short circuit detector threshold. This parameter must be a number between Min_Data = 0 and Max_Data = 255.
BreakSignal | : Break signals assigned to short circuit event. This parameter can be a values combination of DFSDM break signals.
Return values:
HAL status

Definition at line 736 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_CHAWSCDR_BKSCD_OFFSET, HAL_DFSDM_CHANNEL_STATE_READY, DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM_BREAK_SIGNALS, IS_DFSDM_CHANNEL_SCD_THRESHOLD, and DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT | ( | DFSDM_Channel_HandleTypeDef * | hdfsdm_channel,
 |  | uint32_t | Threshold,
 |  | uint32_t | BreakSignal
 | ) |  |

This function allows to start short circuit detection in interrupt mode.

Note:
Same mode has to be used for all channels
Parameters:
hdfsdm_channel | : DFSDM channel handle.
Threshold | : Short circuit detector threshold. This parameter must be a number between Min_Data = 0 and Max_Data = 255.
BreakSignal | : Break signals assigned to short circuit event. This parameter can be a values combination of DFSDM break signals.
Return values:
HAL status

Definition at line 860 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_CHAWSCDR_BKSCD_OFFSET, HAL_DFSDM_CHANNEL_STATE_READY, DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM_BREAK_SIGNALS, IS_DFSDM_CHANNEL_SCD_THRESHOLD, and DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to stop short circuit detection in polling mode.

Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
HAL status

Definition at line 823 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTICR_CLRSCDF_OFFSET, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, DFSDM_Channel_HandleTypeDef::Instance, and DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to stop short circuit detection in interrupt mode.

Note:
Interrupt will be disabled for all channels
Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
HAL status

Definition at line 915 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTICR_CLRSCDF_OFFSET, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, DFSDM_Channel_HandleTypeDef::Instance, and DFSDM_Channel_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Channel state function

Functions
Channel state function
DFSDM Exported Functions

Channel state function. More...

Functions

HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get the current DFSDM channel handle state.

Detailed Description

Channel state function.

  ==============================================================================
                   ##### Channel state function #####
  ==============================================================================
    [..]  This section provides function allowing to:
      (+) Get channel handle state.

Function Documentation

HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to get the current DFSDM channel handle state.

Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
DFSDM channel state.

Definition at line 1009 of file stm32h7xx_hal_dfsdm.c.

References DFSDM_Channel_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Filter initialization and de-initialization functions

Functions
Filter initialization and de-initialization functions
DFSDM Exported Functions

Filter initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_DFSDM_FilterInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initialize the DFSDM filter according to the specified parameters in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_DFSDM_FilterDeInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter.
__weak void | HAL_DFSDM_FilterMspInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initializes the DFSDM filter MSP.
__weak void | HAL_DFSDM_FilterMspDeInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter MSP.

Detailed Description

Filter initialization and de-initialization functions.

  ==============================================================================
        ##### Filter initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the DFSDM filter.
      (+) De-initialize the DFSDM filter.

Function Documentation

HAL_StatusTypeDef HAL_DFSDM_FilterDeInit ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

De-initializes the DFSDM filter.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status.

Definition at line 1149 of file stm32h7xx_hal_dfsdm.c.

References assert_param, HAL_DFSDM_FILTER_STATE_RESET, HAL_DFSDM_FilterMspDeInit(), DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterInit ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Initialize the DFSDM filter according to the specified parameters in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status.

Definition at line 1039 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_CONTINUOUS_CONV_OFF, DFSDM_FILTER_ERROR_NONE, DFSDM_FILTER_EXT_TRIGGER, DFSDM_FILTER_SYNC_TRIGGER, DFSDM_FLTFCR_FOSR_OFFSET, DFSDM_Filter_RegularParamTypeDef::DmaMode, DFSDM_Filter_InjectedParamTypeDef::DmaMode, DFSDM_Filter_HandleTypeDef::ErrorCode, DFSDM_Filter_InjectedParamTypeDef::ExtTrigger, DFSDM_Filter_InjectedParamTypeDef::ExtTriggerEdge, DFSDM_Filter_HandleTypeDef::ExtTriggerEdge, DFSDM_Filter_RegularParamTypeDef::FastMode, DFSDM_Filter_InitTypeDef::FilterParam, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FilterMspInit(), DFSDM_Filter_HandleTypeDef::Init, DFSDM_Filter_HandleTypeDef::InjConvRemaining, DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr, DFSDM_Filter_InitTypeDef::InjectedParam, DFSDM_Filter_HandleTypeDef::InjectedScanMode, DFSDM_Filter_HandleTypeDef::InjectedTrigger, DFSDM_Filter_HandleTypeDef::Instance, DFSDM_Filter_FilterParamTypeDef::IntOversampling, IS_DFSDM_FILTER_EXT_TRIG, IS_DFSDM_FILTER_EXT_TRIG_EDGE, IS_DFSDM_FILTER_INJ_TRIGGER, IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO, IS_DFSDM_FILTER_OVS_RATIO, IS_DFSDM_FILTER_REG_TRIGGER, IS_DFSDM_FILTER_SINC_ORDER, DFSDM_Filter_FilterParamTypeDef::Oversampling, DFSDM_Filter_HandleTypeDef::RegularContMode, DFSDM_Filter_InitTypeDef::RegularParam, DFSDM_Filter_HandleTypeDef::RegularTrigger, DFSDM_Filter_InjectedParamTypeDef::ScanMode, DFSDM_Filter_FilterParamTypeDef::SincOrder, DFSDM_Filter_HandleTypeDef::State, DFSDM_Filter_RegularParamTypeDef::Trigger, and DFSDM_Filter_InjectedParamTypeDef::Trigger.

void HAL_DFSDM_FilterMspDeInit ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

De-initializes the DFSDM filter MSP.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 1192 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterDeInit().

void HAL_DFSDM_FilterMspInit ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Initializes the DFSDM filter MSP.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 1177 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterInit().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Filter control functions

Functions
Filter control functions
DFSDM Exported Functions

Filter control functions. More...

Functions

HAL_StatusTypeDef | HAL_DFSDM_FilterConfigRegChannel (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t ContinuousMode)
This function allows to select channel and to enable/disable continuous mode for regular conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterConfigInjChannel (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to select channels for injected conversion.

Detailed Description

Filter control functions.

  ==============================================================================
                    ##### Filter control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Select channel and enable/disable continuous mode for regular conversion.
      (+) Select channels for injected conversion.

Function Documentation

HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t | Channel
 | ) |  |

This function allows to select channels for injected conversion.

Parameters:
hdfsdm_filter | : DFSDM filter handle.
Channel | : Channels for injected conversion. This parameter can be a values combination of DFSDM Channel Selection.
Return values:
HAL status

Definition at line 1275 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_GetInjChannelsNbr(), DFSDM_LSB_MASK, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_RESET, DFSDM_Filter_HandleTypeDef::InjConvRemaining, DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr, DFSDM_Filter_HandleTypeDef::InjectedScanMode, DFSDM_Filter_HandleTypeDef::Instance, IS_DFSDM_INJECTED_CHANNEL, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t | Channel,
 |  | uint32_t | ContinuousMode
 | ) |  |

This function allows to select channel and to enable/disable continuous mode for regular conversion.

Parameters:
hdfsdm_filter | : DFSDM filter handle.
Channel | : Channel for regular conversion. This parameter can be a value of DFSDM Channel Selection.
ContinuousMode | : Enable/disable continuous mode for regular conversion. This parameter can be a value of DFSDM Continuous Mode.
Return values:
HAL status

Definition at line 1230 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_CONTINUOUS_CONV_ON, DFSDM_FLTCR1_MSB_RCH_OFFSET, DFSDM_MSB_MASK, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_RESET, DFSDM_Filter_HandleTypeDef::Instance, IS_DFSDM_CONTINUOUS_MODE, IS_DFSDM_REGULAR_CHANNEL, DFSDM_Filter_HandleTypeDef::RegularContMode, and DFSDM_Filter_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Filter operation functions

Functions
Filter operation functions
DFSDM Exported Functions

Filter operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterPollForRegConversion (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of regular conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularMsbStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode and to get only the 16 most significant bits of conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in DMA mode.
int32_t | HAL_DFSDM_FilterGetRegularValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get regular conversion value.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterPollForInjConversion (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of injected conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedMsbStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode and to get only the 16 most significant bits of conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in DMA mode.
int32_t | HAL_DFSDM_FilterGetInjectedValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get injected conversion value.
HAL_StatusTypeDef | HAL_DFSDM_FilterAwdStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, DFSDM_Filter_AwdParamTypeDef *awdParam)
This function allows to start filter analog watchdog in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterAwdStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop filter analog watchdog in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterExdStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to start extreme detector feature.
HAL_StatusTypeDef | HAL_DFSDM_FilterExdStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop extreme detector feature.
int32_t | HAL_DFSDM_FilterGetExdMaxValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector maximum value.
int32_t | HAL_DFSDM_FilterGetExdMinValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector minimum value.
uint32_t | HAL_DFSDM_FilterGetConvTimeValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get conversion time value.
void | HAL_DFSDM_IRQHandler (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function handles the DFSDM interrupts.
__weak void | HAL_DFSDM_FilterRegConvCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Regular conversion complete callback.
__weak void | HAL_DFSDM_FilterRegConvHalfCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half regular conversion complete callback.
__weak void | HAL_DFSDM_FilterInjConvCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Injected conversion complete callback.
__weak void | HAL_DFSDM_FilterInjConvHalfCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half injected conversion complete callback.
__weak void | HAL_DFSDM_FilterAwdCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold)
Filter analog watchdog callback.
__weak void | HAL_DFSDM_FilterErrorCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Error callback.

Detailed Description

Filter operation functions.

  ==============================================================================
                    ##### Filter operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion of regular/injected channel.
      (+) Poll for the end of regular/injected conversion.
      (+) Stop conversion of regular/injected channel.
      (+) Start conversion of regular/injected channel and enable interrupt.
      (+) Call the callback functions at the end of regular/injected conversions.
      (+) Stop conversion of regular/injected channel and disable interrupt.
      (+) Start conversion of regular/injected channel and enable DMA transfer.
      (+) Stop conversion of regular/injected channel and disable DMA transfer.
      (+) Start analog watchdog and enable interrupt.
      (+) Call the callback function when analog watchdog occurs.
      (+) Stop analog watchdog and disable interrupt.
      (+) Start extreme detector.
      (+) Stop extreme detector.
      (+) Get result of regular channel conversion.
      (+) Get result of injected channel conversion.
      (+) Get extreme detector maximum and minimum values.
      (+) Get conversion time.
      (+) Handle DFSDM interrupt request.

Function Documentation

void HAL_DFSDM_FilterAwdCallback | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t | Channel,
 |  | uint32_t | Threshold
 | ) |  |

Filter analog watchdog callback.

Parameters:
hdfsdm_filter | : DFSDM filter handle.
Channel | : Corresponding channel.
Threshold | : Low or high threshold has been reached.
Return values:
None

Definition at line 2619 of file stm32h7xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_IRQHandler().

HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | DFSDM_Filter_AwdParamTypeDef * | awdParam
 | ) |  |

This function allows to start filter analog watchdog in interrupt mode.

Parameters:
hdfsdm_filter | : DFSDM filter handle.
awdParam | : DFSDM filter analog watchdog parameters.
Return values:
HAL status

Definition at line 2158 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_Filter_AwdParamTypeDef::Channel, DFSDM_Filter_AwdParamTypeDef::DataSource, DFSDM_FLTAWHTR_THRESHOLD_OFFSET, DFSDM_FLTAWLTR_THRESHOLD_OFFSET, DFSDM_FLTCR2_AWDCH_OFFSET, DFSDM_LSB_MASK, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_RESET, DFSDM_Filter_AwdParamTypeDef::HighBreakSignal, DFSDM_Filter_AwdParamTypeDef::HighThreshold, DFSDM_Filter_HandleTypeDef::Instance, IS_DFSDM_BREAK_SIGNALS, IS_DFSDM_FILTER_AWD_DATA_SOURCE, IS_DFSDM_FILTER_AWD_THRESHOLD, IS_DFSDM_INJECTED_CHANNEL, DFSDM_Filter_AwdParamTypeDef::LowBreakSignal, DFSDM_Filter_AwdParamTypeDef::LowThreshold, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop filter analog watchdog in interrupt mode.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 2207 of file stm32h7xx_hal_dfsdm.c.

References assert_param, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_RESET, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

void HAL_DFSDM_FilterErrorCallback ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Error callback.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 2637 of file stm32h7xx_hal_dfsdm.c.

Referenced by DFSDM_DMAError(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), and HAL_DFSDM_IRQHandler().

HAL_StatusTypeDef HAL_DFSDM_FilterExdStart | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t | Channel
 | ) |  |

This function allows to start extreme detector feature.

Parameters:
hdfsdm_filter | : DFSDM filter handle.
Channel | : Channels where extreme detector is enabled. This parameter can be a values combination of DFSDM Channel Selection.
Return values:
HAL status

Definition at line 2247 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTCR2_EXCH_OFFSET, DFSDM_LSB_MASK, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_RESET, DFSDM_Filter_HandleTypeDef::Instance, IS_DFSDM_INJECTED_CHANNEL, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterExdStop ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop extreme detector feature.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 2278 of file stm32h7xx_hal_dfsdm.c.

References assert_param, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_RESET, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

uint32_t HAL_DFSDM_FilterGetConvTimeValue ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to get conversion time value.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
Conversion time value
Note:
To get time in second, this value has to be divided by DFSDM clock frequency.

Definition at line 2371 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTCNVTIMR_DATA_OFFSET, and DFSDM_Filter_HandleTypeDef::Instance.

int32_t HAL_DFSDM_FilterGetExdMaxValue | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t * | Channel
 | ) |  |

This function allows to get extreme detector maximum value.

Parameters:
hdfsdm_filter | : DFSDM filter handle.
Channel | : Corresponding channel.
Return values:
Extreme detector maximum value This value is between Min_Data = -8388608 and Max_Data = 8388607.

Definition at line 2316 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTEXMAX_DATA_OFFSET, and DFSDM_Filter_HandleTypeDef::Instance.

int32_t HAL_DFSDM_FilterGetExdMinValue | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t * | Channel
 | ) |  |

This function allows to get extreme detector minimum value.

Parameters:
hdfsdm_filter | : DFSDM filter handle.
Channel | : Corresponding channel.
Return values:
Extreme detector minimum value This value is between Min_Data = -8388608 and Max_Data = 8388607.

Definition at line 2344 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTEXMIN_DATA_OFFSET, and DFSDM_Filter_HandleTypeDef::Instance.

int32_t HAL_DFSDM_FilterGetInjectedValue | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t * | Channel
 | ) |  |

This function allows to get injected conversion value.

Parameters:
hdfsdm_filter | : DFSDM filter handle.
Channel | : Corresponding channel of injected conversion.
Return values:
Injected conversion value

Definition at line 2131 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTJDATAR_DATA_OFFSET, and DFSDM_Filter_HandleTypeDef::Instance.

int32_t HAL_DFSDM_FilterGetRegularValue | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t * | Channel
 | ) |  |

This function allows to get regular conversion value.

Parameters:
hdfsdm_filter | : DFSDM filter handle.
Channel | : Corresponding channel of regular conversion.
Return values:
Regular conversion value

Definition at line 1721 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTRDATAR_DATA_OFFSET, and DFSDM_Filter_HandleTypeDef::Instance.

void HAL_DFSDM_FilterInjConvCpltCallback ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Injected conversion complete callback.

Note:
In interrupt mode, user has to read conversion value in this function using HAL_DFSDM_FilterGetInjectedValue.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 2587 of file stm32h7xx_hal_dfsdm.c.

Referenced by DFSDM_DMAInjectedConvCplt(), and HAL_DFSDM_IRQHandler().

void HAL_DFSDM_FilterInjConvHalfCpltCallback ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Half injected conversion complete callback.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 2602 of file stm32h7xx_hal_dfsdm.c.

Referenced by DFSDM_DMAInjectedHalfConvCplt().

HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | int16_t * | pData,
 |  | uint32_t | Length
 | ) |  |

This function allows to start injected conversion in DMA mode and to get only the 16 most significant bits of conversion.

Note:
This function should be called only when DFSDM filter instance is in idle state or if regular conversion is ongoing. Please note that data on buffer will contain signed 16 most significant bits of injected conversion.
Parameters:
hdfsdm_filter | : DFSDM filter handle.
pData | : The destination buffer address.
Length | : The length of data to be transferred from DFSDM filter to memory.
Return values:
HAL status

Definition at line 2023 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_DMAError(), DFSDM_DMAInjectedConvCplt(), DFSDM_DMAInjectedHalfConvCplt(), DFSDM_FILTER_SW_TRIGGER, DFSDM_InjConvStart(), DMA_CIRCULAR, DMA_NORMAL, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DMA_Start_IT(), DFSDM_Filter_HandleTypeDef::hdmaInj, __DMA_HandleTypeDef::Init, DFSDM_Filter_HandleTypeDef::InjConvRemaining, DFSDM_Filter_HandleTypeDef::InjectedTrigger, DFSDM_Filter_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, DFSDM_Filter_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to start injected conversion in polling mode.

Note:
This function should be called only when DFSDM filter instance is in idle state or if regular conversion is ongoing.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 1749 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_InjConvStart(), HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | int32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

This function allows to start injected conversion in DMA mode.

Note:
This function should be called only when DFSDM filter instance is in idle state or if regular conversion is ongoing. Please note that data on buffer will contain signed injected conversion value on 24 most significant bits and corresponding channel on 3 least significant bits.
Parameters:
hdfsdm_filter | : DFSDM filter handle.
pData | : The destination buffer address.
Length | : The length of data to be transferred from DFSDM filter to memory.
Return values:
HAL status

Definition at line 1948 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_DMAError(), DFSDM_DMAInjectedConvCplt(), DFSDM_DMAInjectedHalfConvCplt(), DFSDM_FILTER_SW_TRIGGER, DFSDM_InjConvStart(), DMA_CIRCULAR, DMA_NORMAL, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DMA_Start_IT(), DFSDM_Filter_HandleTypeDef::hdmaInj, __DMA_HandleTypeDef::Init, DFSDM_Filter_HandleTypeDef::InjConvRemaining, DFSDM_Filter_HandleTypeDef::InjectedTrigger, DFSDM_Filter_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, DFSDM_Filter_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to start injected conversion in interrupt mode.

Note:
This function should be called only when DFSDM filter instance is in idle state or if regular conversion is ongoing.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 1879 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_InjConvStart(), HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop injected conversion in polling mode.

Note:
This function should be called only if injected conversion is ongoing.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 1849 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_InjConvStop(), HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_REG_INJ, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop injected conversion in DMA mode.

Note:
This function should be called only if injected conversion is ongoing.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 2092 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_InjConvStop(), HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_REG_INJ, HAL_DMA_Abort(), DFSDM_Filter_HandleTypeDef::hdmaInj, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop injected conversion in interrupt mode.

Note:
This function should be called only if injected conversion is ongoing.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 1910 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_InjConvStop(), HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_REG_INJ, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t | Timeout
 | ) |  |

This function allows to poll for the end of injected conversion.

Note:
This function should be called only if injected conversion is ongoing.
Parameters:
hdfsdm_filter | : DFSDM filter handle.
Timeout | : Timeout value in milliseconds.
Return values:
HAL status

Definition at line 1778 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_FILTER_ERROR_INJECTED_OVERRUN, DFSDM_FILTER_SW_TRIGGER, DFSDM_Filter_HandleTypeDef::ErrorCode, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, HAL_DFSDM_FilterErrorCallback(), HAL_GetTick(), DFSDM_Filter_HandleTypeDef::InjConvRemaining, DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr, DFSDM_Filter_HandleTypeDef::InjectedScanMode, DFSDM_Filter_HandleTypeDef::InjectedTrigger, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t | Timeout
 | ) |  |

This function allows to poll for the end of regular conversion.

Note:
This function should be called only if regular conversion is ongoing.
Parameters:
hdfsdm_filter | : DFSDM filter handle.
Timeout | : Timeout value in milliseconds.
Return values:
HAL status

Definition at line 1374 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_CONTINUOUS_CONV_OFF, DFSDM_FILTER_ERROR_REGULAR_OVERRUN, DFSDM_FILTER_SW_TRIGGER, DFSDM_Filter_HandleTypeDef::ErrorCode, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, HAL_DFSDM_FilterErrorCallback(), HAL_GetTick(), DFSDM_Filter_HandleTypeDef::Instance, DFSDM_Filter_HandleTypeDef::RegularContMode, DFSDM_Filter_HandleTypeDef::RegularTrigger, and DFSDM_Filter_HandleTypeDef::State.

void HAL_DFSDM_FilterRegConvCpltCallback ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Regular conversion complete callback.

Note:
In interrupt mode, user has to read conversion value in this function using HAL_DFSDM_FilterGetRegularValue.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 2555 of file stm32h7xx_hal_dfsdm.c.

Referenced by DFSDM_DMARegularConvCplt(), and HAL_DFSDM_IRQHandler().

void HAL_DFSDM_FilterRegConvHalfCpltCallback ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Half regular conversion complete callback.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 2570 of file stm32h7xx_hal_dfsdm.c.

Referenced by DFSDM_DMARegularHalfConvCplt().

HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | int16_t * | pData,
 |  | uint32_t | Length
 | ) |  |

This function allows to start regular conversion in DMA mode and to get only the 16 most significant bits of conversion.

Note:
This function should be called only when DFSDM filter instance is in idle state or if injected conversion is ongoing. Please note that data on buffer will contain signed 16 most significant bits of regular conversion.
Parameters:
hdfsdm_filter | : DFSDM filter handle.
pData | : The destination buffer address.
Length | : The length of data to be transferred from DFSDM filter to memory.
Return values:
HAL status

Definition at line 1611 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_CONTINUOUS_CONV_OFF, DFSDM_DMAError(), DFSDM_DMARegularConvCplt(), DFSDM_DMARegularHalfConvCplt(), DFSDM_FILTER_SW_TRIGGER, DFSDM_RegConvStart(), DMA_CIRCULAR, DMA_NORMAL, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DMA_Start_IT(), DFSDM_Filter_HandleTypeDef::hdmaReg, __DMA_HandleTypeDef::Init, DFSDM_Filter_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, DFSDM_Filter_HandleTypeDef::RegularContMode, DFSDM_Filter_HandleTypeDef::RegularTrigger, DFSDM_Filter_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to start regular conversion in polling mode.

Note:
This function should be called only when DFSDM filter instance is in idle state or if injected conversion is ongoing.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 1345 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_RegConvStart(), HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | int32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

This function allows to start regular conversion in DMA mode.

Note:
This function should be called only when DFSDM filter instance is in idle state or if injected conversion is ongoing. Please note that data on buffer will contain signed regular conversion value on 24 most significant bits and corresponding channel on 3 least significant bits.
Parameters:
hdfsdm_filter | : DFSDM filter handle.
pData | : The destination buffer address.
Length | : The length of data to be transferred from DFSDM filter to memory.
Return values:
HAL status

Definition at line 1534 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_CONTINUOUS_CONV_OFF, DFSDM_DMAError(), DFSDM_DMARegularConvCplt(), DFSDM_DMARegularHalfConvCplt(), DFSDM_FILTER_SW_TRIGGER, DFSDM_RegConvStart(), DMA_CIRCULAR, DMA_NORMAL, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DMA_Start_IT(), DFSDM_Filter_HandleTypeDef::hdmaReg, __DMA_HandleTypeDef::Init, DFSDM_Filter_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, DFSDM_Filter_HandleTypeDef::RegularContMode, DFSDM_Filter_HandleTypeDef::RegularTrigger, DFSDM_Filter_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to start regular conversion in interrupt mode.

Note:
This function should be called only when DFSDM filter instance is in idle state or if injected conversion is ongoing.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 1465 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_RegConvStart(), HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop regular conversion in polling mode.

Note:
This function should be called only if regular conversion is ongoing.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 1435 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_RegConvStop(), HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop regular conversion in DMA mode.

Note:
This function should be called only if regular conversion is ongoing.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 1682 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_RegConvStop(), HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, HAL_DMA_Abort(), DFSDM_Filter_HandleTypeDef::hdmaReg, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop regular conversion in interrupt mode.

Note:
This function should be called only if regular conversion is ongoing.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 1496 of file stm32h7xx_hal_dfsdm.c.

References assert_param, DFSDM_RegConvStop(), HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

void HAL_DFSDM_IRQHandler ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function handles the DFSDM interrupts.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 2394 of file stm32h7xx_hal_dfsdm.c.

References DFSDM1_CHANNEL_NUMBER, DFSDM_AWD_HIGH_THRESHOLD, DFSDM_AWD_LOW_THRESHOLD, DFSDM_CONTINUOUS_CONV_OFF, DFSDM_FILTER_ERROR_INJECTED_OVERRUN, DFSDM_FILTER_ERROR_REGULAR_OVERRUN, DFSDM_FILTER_SW_TRIGGER, DFSDM_FLTAWSR_HIGH_OFFSET, DFSDM_FLTICR_CLRCKABF_OFFSET, DFSDM_FLTICR_CLRSCDF_OFFSET, DFSDM_FLTISR_CKABF_OFFSET, DFSDM_FLTISR_SCDF_OFFSET, DFSDM_Filter_HandleTypeDef::ErrorCode, HAL_DFSDM_ChannelCkabCallback(), HAL_DFSDM_ChannelScdCallback(), HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FilterAwdCallback(), HAL_DFSDM_FilterErrorCallback(), HAL_DFSDM_FilterInjConvCpltCallback(), HAL_DFSDM_FilterRegConvCpltCallback(), DFSDM_Filter_HandleTypeDef::InjConvRemaining, DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr, DFSDM_Filter_HandleTypeDef::InjectedScanMode, DFSDM_Filter_HandleTypeDef::InjectedTrigger, DFSDM_Filter_HandleTypeDef::Instance, DFSDM_Filter_HandleTypeDef::RegularContMode, DFSDM_Filter_HandleTypeDef::RegularTrigger, and DFSDM_Filter_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Filter state functions

Functions
Filter state functions
DFSDM Exported Functions

Filter state functions. More...

Functions

HAL_DFSDM_Filter_StateTypeDef | HAL_DFSDM_FilterGetState (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter handle state.
uint32_t | HAL_DFSDM_FilterGetError (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter error.

Detailed Description

Filter state functions.

  ==============================================================================
                     ##### Filter state functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Get the DFSDM filter state.
      (+) Get the DFSDM filter error.

Function Documentation

uint32_t HAL_DFSDM_FilterGetError ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to get the current DFSDM filter error.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
DFSDM filter error code.

Definition at line 2681 of file stm32h7xx_hal_dfsdm.c.

References DFSDM_Filter_HandleTypeDef::ErrorCode.

HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to get the current DFSDM filter handle state.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
DFSDM filter state.

Definition at line 2670 of file stm32h7xx_hal_dfsdm.c.

References DFSDM_Filter_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DFSDM Exported Types

Data Structures | Enumerations
DFSDM Exported Types
DFSDM

Data Structures

struct | DFSDM_Channel_OutputClockTypeDef
DFSDM channel output clock structure definition. More...
struct | DFSDM_Channel_InputTypeDef
DFSDM channel input structure definition. More...
struct | DFSDM_Channel_SerialInterfaceTypeDef
DFSDM channel serial interface structure definition. More...
struct | DFSDM_Channel_AwdTypeDef
DFSDM channel analog watchdog structure definition. More...
struct | DFSDM_Channel_InitTypeDef
DFSDM channel init structure definition. More...
struct | DFSDM_Channel_HandleTypeDef
DFSDM channel handle structure definition. More...
struct | DFSDM_Filter_RegularParamTypeDef
DFSDM filter regular conversion parameters structure definition. More...
struct | DFSDM_Filter_InjectedParamTypeDef
DFSDM filter injected conversion parameters structure definition. More...
struct | DFSDM_Filter_FilterParamTypeDef
DFSDM filter parameters structure definition. More...
struct | DFSDM_Filter_InitTypeDef
DFSDM filter init structure definition. More...
struct | DFSDM_Filter_HandleTypeDef
DFSDM filter handle structure definition. More...
struct | DFSDM_Filter_AwdParamTypeDef
DFSDM filter analog watchdog parameters structure definition. More...

Enumerations

enum | HAL_DFSDM_Channel_StateTypeDef { HAL_DFSDM_CHANNEL_STATE_RESET = 0x00, HAL_DFSDM_CHANNEL_STATE_READY = 0x01, HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFF }
HAL DFSDM Channel states definition. More...
enum HAL_DFSDM_Filter_StateTypeDef {
HAL_DFSDM_FILTER_STATE_RESET = 0x00, HAL_DFSDM_FILTER_STATE_READY = 0x01, HAL_DFSDM_FILTER_STATE_REG = 0x02, HAL_DFSDM_FILTER_STATE_INJ = 0x03,
HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04, HAL_DFSDM_FILTER_STATE_ERROR = 0xFF
}
HAL DFSDM Filter states definition. More...

Enumeration Type Documentation

enum HAL_DFSDM_Channel_StateTypeDef

HAL DFSDM Channel states definition.

Enumerator:
HAL_DFSDM_CHANNEL_STATE_RESET

DFSDM channel not initialized

HAL_DFSDM_CHANNEL_STATE_READY

DFSDM channel initialized and ready for use

HAL_DFSDM_CHANNEL_STATE_ERROR

DFSDM channel state error

Definition at line 65 of file stm32h7xx_hal_dfsdm.h.

enum HAL_DFSDM_Filter_StateTypeDef

HAL DFSDM Filter states definition.

Enumerator:
HAL_DFSDM_FILTER_STATE_RESET

DFSDM filter not initialized

HAL_DFSDM_FILTER_STATE_READY

DFSDM filter initialized and ready for use

HAL_DFSDM_FILTER_STATE_REG

DFSDM filter regular conversion in progress

HAL_DFSDM_FILTER_STATE_INJ

DFSDM filter injected conversion in progress

HAL_DFSDM_FILTER_STATE_REG_INJ

DFSDM filter regular and injected conversions in progress

HAL_DFSDM_FILTER_STATE_ERROR

DFSDM filter state error

Definition at line 147 of file stm32h7xx_hal_dfsdm.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DFSDM_Channel_OutputClockTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Channel_OutputClockTypeDef Struct Reference
DFSDM Exported Types

DFSDM channel output clock structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

FunctionalState | Activation
uint32_t | Selection
uint32_t | Divider

Detailed Description

DFSDM channel output clock structure definition.

Definition at line 75 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

FunctionalState DFSDM_Channel_OutputClockTypeDef::Activation

Output clock enable/disable

Definition at line 77 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

uint32_t DFSDM_Channel_OutputClockTypeDef::Divider

Output clock divider. This parameter must be a number between Min_Data = 2 and Max_Data = 256

Definition at line 80 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

uint32_t DFSDM_Channel_OutputClockTypeDef::Selection

Output clock is system clock or audio clock. This parameter can be a value of DFSDM channel output clock selection

Definition at line 78 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DFSDM_Channel_InputTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Channel_InputTypeDef Struct Reference
DFSDM Exported Types

DFSDM channel input structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

uint32_t | Multiplexer
uint32_t | DataPacking
uint32_t | Pins

Detailed Description

DFSDM channel input structure definition.

Definition at line 87 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

uint32_t DFSDM_Channel_InputTypeDef::DataPacking

Standard, interleaved or dual mode for internal register. This parameter can be a value of DFSDM channel input data packing

Definition at line 91 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

uint32_t DFSDM_Channel_InputTypeDef::Multiplexer

Input is external serial inputs ,internal register or ADC output. This parameter can be a value of DFSDM channel input multiplexer

Definition at line 89 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

uint32_t DFSDM_Channel_InputTypeDef::Pins

Input pins are taken from same or following channel. This parameter can be a value of DFSDM channel input pins

Definition at line 93 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DFSDM_Channel_SerialInterfaceTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Channel_SerialInterfaceTypeDef Struct Reference
DFSDM Exported Types

DFSDM channel serial interface structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

uint32_t | Type
uint32_t | SpiClock

Detailed Description

DFSDM channel serial interface structure definition.

Definition at line 100 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

uint32_t DFSDM_Channel_SerialInterfaceTypeDef::SpiClock

SPI clock select (external or internal with different sampling point). This parameter can be a value of DFSDM channel SPI clock selection

Definition at line 104 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

uint32_t DFSDM_Channel_SerialInterfaceTypeDef::Type

SPI or Manchester modes. This parameter can be a value of DFSDM channel serial interface type

Definition at line 102 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DFSDM_Channel_AwdTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Channel_AwdTypeDef Struct Reference
DFSDM Exported Types

DFSDM channel analog watchdog structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

uint32_t | FilterOrder
uint32_t | Oversampling

Detailed Description

DFSDM channel analog watchdog structure definition.

Definition at line 111 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

uint32_t DFSDM_Channel_AwdTypeDef::FilterOrder

Analog watchdog Sinc filter order. This parameter can be a value of DFSDM channel analog watchdog filter order

Definition at line 113 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

uint32_t DFSDM_Channel_AwdTypeDef::Oversampling

Analog watchdog filter oversampling ratio. This parameter must be a number between Min_Data = 1 and Max_Data = 32

Definition at line 115 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DFSDM_Channel_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Channel_InitTypeDef Struct Reference
DFSDM Exported Types

DFSDM channel init structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

DFSDM_Channel_OutputClockTypeDef OutputClock
DFSDM_Channel_InputTypeDef Input
DFSDM_Channel_SerialInterfaceTypeDef SerialInterface
DFSDM_Channel_AwdTypeDef Awd
int32_t | Offset
uint32_t | RightBitShift

Detailed Description

DFSDM channel init structure definition.

Definition at line 122 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

DFSDM_Channel_AwdTypeDef DFSDM_Channel_InitTypeDef::Awd

DFSDM channel analog watchdog parameters

Definition at line 127 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

DFSDM_Channel_InputTypeDef DFSDM_Channel_InitTypeDef::Input

DFSDM channel input parameters

Definition at line 125 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

int32_t DFSDM_Channel_InitTypeDef::Offset

DFSDM channel offset. This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607

Definition at line 128 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

DFSDM_Channel_OutputClockTypeDef DFSDM_Channel_InitTypeDef::OutputClock

DFSDM channel output clock parameters

Definition at line 124 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

uint32_t DFSDM_Channel_InitTypeDef::RightBitShift

DFSDM channel right bit shift. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F

Definition at line 130 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

DFSDM_Channel_SerialInterfaceTypeDef DFSDM_Channel_InitTypeDef::SerialInterface

DFSDM channel serial interface parameters

Definition at line 126 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DFSDM_Channel_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Channel_HandleTypeDef Struct Reference
DFSDM Exported Types

DFSDM channel handle structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

DFSDM_Channel_TypeDef * Instance
DFSDM_Channel_InitTypeDef Init
HAL_DFSDM_Channel_StateTypeDef State

Detailed Description

DFSDM channel handle structure definition.

Definition at line 137 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

DFSDM_Channel_InitTypeDef DFSDM_Channel_HandleTypeDef::Init

DFSDM channel init parameters

Definition at line 140 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

DFSDM_Channel_TypeDef* DFSDM_Channel_HandleTypeDef::Instance

DFSDM channel instance

Definition at line 139 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelCkabStart(), HAL_DFSDM_ChannelCkabStart_IT(), HAL_DFSDM_ChannelCkabStop(), HAL_DFSDM_ChannelCkabStop_IT(), HAL_DFSDM_ChannelDeInit(), HAL_DFSDM_ChannelGetAwdValue(), HAL_DFSDM_ChannelInit(), HAL_DFSDM_ChannelModifyOffset(), HAL_DFSDM_ChannelPollForCkab(), HAL_DFSDM_ChannelPollForScd(), HAL_DFSDM_ChannelScdStart(), HAL_DFSDM_ChannelScdStart_IT(), HAL_DFSDM_ChannelScdStop(), and HAL_DFSDM_ChannelScdStop_IT().

HAL_DFSDM_Channel_StateTypeDef DFSDM_Channel_HandleTypeDef::State

DFSDM channel state

Definition at line 141 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelCkabStart(), HAL_DFSDM_ChannelCkabStart_IT(), HAL_DFSDM_ChannelCkabStop(), HAL_DFSDM_ChannelCkabStop_IT(), HAL_DFSDM_ChannelDeInit(), HAL_DFSDM_ChannelGetState(), HAL_DFSDM_ChannelInit(), HAL_DFSDM_ChannelModifyOffset(), HAL_DFSDM_ChannelPollForCkab(), HAL_DFSDM_ChannelPollForScd(), HAL_DFSDM_ChannelScdStart(), HAL_DFSDM_ChannelScdStart_IT(), HAL_DFSDM_ChannelScdStop(), and HAL_DFSDM_ChannelScdStop_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DFSDM_Filter_RegularParamTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Filter_RegularParamTypeDef Struct Reference
DFSDM Exported Types

DFSDM filter regular conversion parameters structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

uint32_t | Trigger
FunctionalState | FastMode
FunctionalState | DmaMode

Detailed Description

DFSDM filter regular conversion parameters structure definition.

Definition at line 160 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

FunctionalState DFSDM_Filter_RegularParamTypeDef::DmaMode

Enable/disable DMA for regular conversion

Definition at line 165 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

FunctionalState DFSDM_Filter_RegularParamTypeDef::FastMode

Enable/disable fast mode for regular conversion

Definition at line 164 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

uint32_t DFSDM_Filter_RegularParamTypeDef::Trigger

Trigger used to start regular conversion: software or synchronous. This parameter can be a value of DFSDM filter conversion trigger

Definition at line 162 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DFSDM_Filter_InjectedParamTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Filter_InjectedParamTypeDef Struct Reference
DFSDM Exported Types

DFSDM filter injected conversion parameters structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

uint32_t | Trigger
FunctionalState | ScanMode
FunctionalState | DmaMode
uint32_t | ExtTrigger
uint32_t | ExtTriggerEdge

Detailed Description

DFSDM filter injected conversion parameters structure definition.

Definition at line 171 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

FunctionalState DFSDM_Filter_InjectedParamTypeDef::DmaMode

Enable/disable DMA for injected conversion

Definition at line 176 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

uint32_t DFSDM_Filter_InjectedParamTypeDef::ExtTrigger

External trigger. This parameter can be a value of DFSDM filter external trigger

Definition at line 177 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

uint32_t DFSDM_Filter_InjectedParamTypeDef::ExtTriggerEdge

External trigger edge: rising, falling or both. This parameter can be a value of DFSDM filter external trigger edge

Definition at line 179 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

FunctionalState DFSDM_Filter_InjectedParamTypeDef::ScanMode

Enable/disable scanning mode for injected conversion

Definition at line 175 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

uint32_t DFSDM_Filter_InjectedParamTypeDef::Trigger

Trigger used to start injected conversion: software, external or synchronous. This parameter can be a value of DFSDM filter conversion trigger

Definition at line 173 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DFSDM_Filter_FilterParamTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Filter_FilterParamTypeDef Struct Reference
DFSDM Exported Types

DFSDM filter parameters structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

uint32_t | SincOrder
uint32_t | Oversampling
uint32_t | IntOversampling

Detailed Description

DFSDM filter parameters structure definition.

Definition at line 186 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

uint32_t DFSDM_Filter_FilterParamTypeDef::IntOversampling

Integrator oversampling ratio. This parameter must be a number between Min_Data = 1 and Max_Data = 256

Definition at line 192 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

uint32_t DFSDM_Filter_FilterParamTypeDef::Oversampling

Filter oversampling ratio. This parameter must be a number between Min_Data = 1 and Max_Data = 1024

Definition at line 190 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

uint32_t DFSDM_Filter_FilterParamTypeDef::SincOrder

Sinc filter order. This parameter can be a value of DFSDM filter sinc order

Definition at line 188 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DFSDM_Filter_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Filter_InitTypeDef Struct Reference
DFSDM Exported Types

DFSDM filter init structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

DFSDM_Filter_RegularParamTypeDef RegularParam
DFSDM_Filter_InjectedParamTypeDef InjectedParam
DFSDM_Filter_FilterParamTypeDef FilterParam

Detailed Description

DFSDM filter init structure definition.

Definition at line 199 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

DFSDM_Filter_FilterParamTypeDef DFSDM_Filter_InitTypeDef::FilterParam

DFSDM filter parameters

Definition at line 203 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

DFSDM_Filter_InjectedParamTypeDef DFSDM_Filter_InitTypeDef::InjectedParam

DFSDM injected conversion parameters

Definition at line 202 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

DFSDM_Filter_RegularParamTypeDef DFSDM_Filter_InitTypeDef::RegularParam

DFSDM regular conversion parameters

Definition at line 201 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DFSDM_Filter_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Filter_HandleTypeDef Struct Reference
DFSDM Exported Types

DFSDM filter handle structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

DFSDM_Filter_TypeDef * | Instance
DFSDM_Filter_InitTypeDef Init
DMA_HandleTypeDef * hdmaReg
DMA_HandleTypeDef * hdmaInj
uint32_t | RegularContMode
uint32_t | RegularTrigger
uint32_t | InjectedTrigger
uint32_t | ExtTriggerEdge
FunctionalState | InjectedScanMode
uint32_t | InjectedChannelsNbr
uint32_t | InjConvRemaining
HAL_DFSDM_Filter_StateTypeDef State
uint32_t | ErrorCode

Detailed Description

DFSDM filter handle structure definition.

Definition at line 209 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

uint32_t DFSDM_Filter_HandleTypeDef::ErrorCode

DFSDM filter error code

Definition at line 223 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_DMAError(), HAL_DFSDM_FilterGetError(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), and HAL_DFSDM_IRQHandler().

uint32_t DFSDM_Filter_HandleTypeDef::ExtTriggerEdge

Rising, falling or both edges selected

Definition at line 218 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStart(), and HAL_DFSDM_FilterInit().

DMA_HandleTypeDef* DFSDM_Filter_HandleTypeDef::hdmaInj

Pointer on DMA handler for injected conversions

Definition at line 214 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), and HAL_DFSDM_FilterInjectedStop_DMA().

DMA_HandleTypeDef* DFSDM_Filter_HandleTypeDef::hdmaReg

Pointer on DMA handler for regular conversions

Definition at line 213 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), and HAL_DFSDM_FilterRegularStop_DMA().

DFSDM_Filter_InitTypeDef DFSDM_Filter_HandleTypeDef::Init

DFSDM filter init parameters

Definition at line 212 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

uint32_t DFSDM_Filter_HandleTypeDef::InjConvRemaining

Injected conversions remaining

Definition at line 221 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterConfigInjChannel(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterPollForInjConversion(), and HAL_DFSDM_IRQHandler().

uint32_t DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr

Number of channels in injected sequence

Definition at line 220 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterConfigInjChannel(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterPollForInjConversion(), and HAL_DFSDM_IRQHandler().

FunctionalState DFSDM_Filter_HandleTypeDef::InjectedScanMode

Injected scanning mode

Definition at line 219 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterConfigInjChannel(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterPollForInjConversion(), and HAL_DFSDM_IRQHandler().

uint32_t DFSDM_Filter_HandleTypeDef::InjectedTrigger

Trigger used for injected conversion

Definition at line 217 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStart(), DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterPollForInjConversion(), and HAL_DFSDM_IRQHandler().

DFSDM_Filter_TypeDef* DFSDM_Filter_HandleTypeDef::Instance

DFSDM filter instance

Definition at line 211 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStart(), DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterAwdStart_IT(), HAL_DFSDM_FilterAwdStop_IT(), HAL_DFSDM_FilterConfigInjChannel(), HAL_DFSDM_FilterConfigRegChannel(), HAL_DFSDM_FilterDeInit(), HAL_DFSDM_FilterExdStart(), HAL_DFSDM_FilterExdStop(), HAL_DFSDM_FilterGetConvTimeValue(), HAL_DFSDM_FilterGetExdMaxValue(), HAL_DFSDM_FilterGetExdMinValue(), HAL_DFSDM_FilterGetInjectedValue(), HAL_DFSDM_FilterGetRegularValue(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStop(), HAL_DFSDM_FilterInjectedStop_DMA(), HAL_DFSDM_FilterInjectedStop_IT(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStop(), HAL_DFSDM_FilterRegularStop_DMA(), HAL_DFSDM_FilterRegularStop_IT(), and HAL_DFSDM_IRQHandler().

uint32_t DFSDM_Filter_HandleTypeDef::RegularContMode

Regular conversion continuous mode

Definition at line 215 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterConfigRegChannel(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), and HAL_DFSDM_IRQHandler().

uint32_t DFSDM_Filter_HandleTypeDef::RegularTrigger

Trigger used for regular conversion

Definition at line 216 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStart(), DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), and HAL_DFSDM_IRQHandler().

HAL_DFSDM_Filter_StateTypeDef DFSDM_Filter_HandleTypeDef::State

DFSDM filter state

Definition at line 222 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStart(), DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterAwdStart_IT(), HAL_DFSDM_FilterAwdStop_IT(), HAL_DFSDM_FilterConfigInjChannel(), HAL_DFSDM_FilterConfigRegChannel(), HAL_DFSDM_FilterDeInit(), HAL_DFSDM_FilterExdStart(), HAL_DFSDM_FilterExdStop(), HAL_DFSDM_FilterGetState(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStop(), HAL_DFSDM_FilterInjectedStop_DMA(), HAL_DFSDM_FilterInjectedStop_IT(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStop(), HAL_DFSDM_FilterRegularStop_DMA(), HAL_DFSDM_FilterRegularStop_IT(), and HAL_DFSDM_IRQHandler().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DFSDM_Filter_AwdParamTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Filter_AwdParamTypeDef Struct Reference
DFSDM Exported Types

DFSDM filter analog watchdog parameters structure definition. More...

#include <stm32h7xx_hal_dfsdm.h>

Data Fields

uint32_t | DataSource
uint32_t | Channel
int32_t | HighThreshold
int32_t | LowThreshold
uint32_t | HighBreakSignal
uint32_t | LowBreakSignal

Detailed Description

DFSDM filter analog watchdog parameters structure definition.

Definition at line 229 of file stm32h7xx_hal_dfsdm.h.

Field Documentation

uint32_t DFSDM_Filter_AwdParamTypeDef::Channel

Analog watchdog channel selection. This parameter can be a values combination of DFSDM Channel Selection

Definition at line 233 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

uint32_t DFSDM_Filter_AwdParamTypeDef::DataSource

Values from digital filter or from channel watchdog filter. This parameter can be a value of DFSDM filter analog watchdog data source

Definition at line 231 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

uint32_t DFSDM_Filter_AwdParamTypeDef::HighBreakSignal

Break signal assigned to analog watchdog high threshold event. This parameter can be a values combination of DFSDM break signals

Definition at line 239 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

int32_t DFSDM_Filter_AwdParamTypeDef::HighThreshold

High threshold for the analog watchdog. This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607

Definition at line 235 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

uint32_t DFSDM_Filter_AwdParamTypeDef::LowBreakSignal

Break signal assigned to analog watchdog low threshold event. This parameter can be a values combination of DFSDM break signals

Definition at line 241 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

int32_t DFSDM_Filter_AwdParamTypeDef::LowThreshold

Low threshold for the analog watchdog. This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607

Definition at line 237 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dfsdm.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DFSDM channel output clock selection

Defines
DFSDM channel output clock selection
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000)
#define | DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC

Define Documentation

#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC

Source for ouput clock is audio clock

Definition at line 259 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000)

Source for ouput clock is system clock

Definition at line 258 of file stm32h7xx_hal_dfsdm.h.

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STM32H753xx HAL User Manual: DFSDM channel input multiplexer

Defines
DFSDM channel input multiplexer
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000)
#define | DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0
#define | DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1

Define Documentation

#define DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0

Data are taken from ADC output

Definition at line 268 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000)

Data are taken from external inputs

Definition at line 267 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1

Data are taken from internal register

Definition at line 269 of file stm32h7xx_hal_dfsdm.h.

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STM32H753xx HAL User Manual: DFSDM channel input data packing

Defines
DFSDM channel input data packing
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000)
#define | DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0
#define | DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1

Define Documentation

#define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1

Dual data packing mode

Definition at line 279 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0

Interleaved data packing mode

Definition at line 278 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000)

Standard data packing mode

Definition at line 277 of file stm32h7xx_hal_dfsdm.h.

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STM32H753xx HAL User Manual: DFSDM channel input pins

Defines
DFSDM channel input pins
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000)
#define | DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL

Define Documentation

#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL

Input from pins on following channel

Definition at line 288 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000)

Input from pins on same channel

Definition at line 287 of file stm32h7xx_hal_dfsdm.h.

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STM32H753xx HAL User Manual: DFSDM channel serial interface type

Defines
DFSDM channel serial interface type
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000)
#define | DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0
#define | DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1
#define | DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP

Define Documentation

#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP

Manchester with falling edge

Definition at line 299 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1

Manchester with rising edge

Definition at line 298 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0

SPI with falling edge

Definition at line 297 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000)

SPI with rising edge

Definition at line 296 of file stm32h7xx_hal_dfsdm.h.

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STM32H753xx HAL User Manual: DFSDM channel SPI clock selection

Defines
DFSDM channel SPI clock selection
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000)
#define | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0
#define | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1
#define | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL

Define Documentation

#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000)

External SPI clock

Definition at line 307 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0

Internal SPI clock

Definition at line 308 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1

Internal SPI clock divided by 2, falling edge

Definition at line 309 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL

Internal SPI clock divided by 2, rising edge

Definition at line 310 of file stm32h7xx_hal_dfsdm.h.

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STM32H753xx HAL User Manual: DFSDM channel analog watchdog filter order

Defines
DFSDM channel analog watchdog filter order
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000)
#define | DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0
#define | DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1
#define | DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD

Define Documentation

#define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000)

FastSinc filter type

Definition at line 318 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0

Sinc 1 filter type

Definition at line 319 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1

Sinc 2 filter type

Definition at line 320 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD

Sinc 3 filter type

Definition at line 321 of file stm32h7xx_hal_dfsdm.h.

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STM32H753xx HAL User Manual: DFSDM filter conversion trigger

Defines
DFSDM filter conversion trigger
DFSDM Exported Constants

Defines

#define | DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000)
#define | DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001)
#define | DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002)

Define Documentation

#define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002)

External trigger (only for injected conversion)

Definition at line 331 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStop(), and HAL_DFSDM_FilterInit().

#define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000)

Software trigger

Definition at line 329 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStart(), DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), and HAL_DFSDM_IRQHandler().

#define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001)

Synchronous with DFSDM0

Definition at line 330 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStart(), DFSDM_InjConvStop(), DFSDM_RegConvStop(), and HAL_DFSDM_FilterInit().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DFSDM filter external trigger

Defines
DFSDM filter external trigger
DFSDM Exported Constants

Defines

#define | DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000)
#define | DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0
#define | DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1
#define | DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2
#define | DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)
#define | DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3
#define | DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)
#define | DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3)
#define | DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)
#define | DFSDM_FILTER_EXT_TRIG_LPTIM1 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_LPTIM2 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_0)
#define | DFSDM_FILTER_EXT_TRIG_LPTIM3 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2)

Define Documentation

#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3)

For DFSDM 0, 1, 2 and 3

Definition at line 350 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)

For DFSDM 0, 1, 2 and 3

Definition at line 351 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)

Definition at line 348 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)

Definition at line 349 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_LPTIM1 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)

For DFSDM 0, 1, 2 and 3

Definition at line 352 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_LPTIM2 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_0)

For DFSDM 0, 1, 2 and 3

Definition at line 353 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_LPTIM3 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2)

For DFSDM 0, 1, 2 and 3

Definition at line 354 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)

For DFSDM 3

Definition at line 345 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000)

For DFSDM 0, 1, 2 and 3

Definition at line 339 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0

For DFSDM 0, 1, 2 and 3

Definition at line 340 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2

For DFSDM 3

Definition at line 343 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)

For DFSDM 0, 1 and 2

Definition at line 344 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)

For DFSDM 0 and 1

Definition at line 346 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3

For DFSDM 2 and 3

Definition at line 347 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1

For DFSDM 0, 1, 2 and 3

Definition at line 341 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)

For DFSDM 0, 1 and 2

Definition at line 342 of file stm32h7xx_hal_dfsdm.h.

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STM32H753xx HAL User Manual: DFSDM filter external trigger edge

Defines
DFSDM filter external trigger edge
DFSDM Exported Constants

Defines

#define | DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0
#define | DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1
#define | DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN

Define Documentation

#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN

External rising and falling edges

Definition at line 364 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1

External falling edge

Definition at line 363 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0

External rising edge

Definition at line 362 of file stm32h7xx_hal_dfsdm.h.

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STM32H753xx HAL User Manual: DFSDM filter sinc order

Defines
DFSDM filter sinc order
DFSDM Exported Constants

Defines

#define | DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000)
#define | DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0
#define | DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1
#define | DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1)
#define | DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2
#define | DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2)

Define Documentation

#define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000)

FastSinc filter type

Definition at line 372 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0

Sinc 1 filter type

Definition at line 373 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1

Sinc 2 filter type

Definition at line 374 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1)

Sinc 3 filter type

Definition at line 375 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2

Sinc 4 filter type

Definition at line 376 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2)

Sinc 5 filter type

Definition at line 377 of file stm32h7xx_hal_dfsdm.h.

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STM32H753xx HAL User Manual: DFSDM filter analog watchdog data source

Defines
DFSDM filter analog watchdog data source
DFSDM Exported Constants

Defines

#define | DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000)
#define | DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL

Define Documentation

#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL

From analog watchdog channel

Definition at line 386 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000)

From digital filter

Definition at line 385 of file stm32h7xx_hal_dfsdm.h.

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STM32H753xx HAL User Manual: DFSDM filter error code

Defines
DFSDM filter error code
DFSDM Exported Constants

Defines

#define | DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000)
#define | DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001)
#define | DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002)
#define | DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003)

Define Documentation

#define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003)

DMA error occurs

Definition at line 397 of file stm32h7xx_hal_dfsdm.h.

Referenced by DFSDM_DMAError().

#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002)

Overrun occurs during injected conversion

Definition at line 396 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterPollForInjConversion(), and HAL_DFSDM_IRQHandler().

#define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000)

No error

Definition at line 394 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001)

Overrun occurs during regular conversion

Definition at line 395 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterPollForRegConversion(), and HAL_DFSDM_IRQHandler().

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STM32H753xx HAL User Manual: DFSDM break signals

Defines
DFSDM break signals
DFSDM Exported Constants

Defines

#define | DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000)
#define | DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001)
#define | DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002)
#define | DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004)
#define | DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008)

Define Documentation

#define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001)

Break signal 0

Definition at line 406 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002)

Break signal 1

Definition at line 407 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004)

Break signal 2

Definition at line 408 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008)

Break signal 3

Definition at line 409 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000)

No break signal

Definition at line 405 of file stm32h7xx_hal_dfsdm.h.

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STM32H753xx HAL User Manual: DFSDM Channel Selection

Defines
DFSDM Channel Selection
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_0 ((uint32_t)0x00000001)
#define | DFSDM_CHANNEL_1 ((uint32_t)0x00010002)
#define | DFSDM_CHANNEL_2 ((uint32_t)0x00020004)
#define | DFSDM_CHANNEL_3 ((uint32_t)0x00030008)
#define | DFSDM_CHANNEL_4 ((uint32_t)0x00040010)
#define | DFSDM_CHANNEL_5 ((uint32_t)0x00050020)
#define | DFSDM_CHANNEL_6 ((uint32_t)0x00060040)
#define | DFSDM_CHANNEL_7 ((uint32_t)0x00070080)

Define Documentation

#define DFSDM_CHANNEL_0 ((uint32_t)0x00000001)

Definition at line 425 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_1 ((uint32_t)0x00010002)

Definition at line 426 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_2 ((uint32_t)0x00020004)

Definition at line 427 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_3 ((uint32_t)0x00030008)

Definition at line 428 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_4 ((uint32_t)0x00040010)

Definition at line 429 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_5 ((uint32_t)0x00050020)

Definition at line 430 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_6 ((uint32_t)0x00060040)

Definition at line 431 of file stm32h7xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_7 ((uint32_t)0x00070080)

Definition at line 432 of file stm32h7xx_hal_dfsdm.h.

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STM32H753xx HAL User Manual: DFSDM Continuous Mode

Defines
DFSDM Continuous Mode
DFSDM Exported Constants

Defines

#define | DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000)
#define | DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001)

Define Documentation

#define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000)

Conversion are not continuous

Definition at line 440 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), and HAL_DFSDM_IRQHandler().

#define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001)

Conversion are continuous

Definition at line 441 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterConfigRegChannel().

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STM32H753xx HAL User Manual: DFSDM analog watchdog threshold

Defines
DFSDM analog watchdog threshold
DFSDM Exported Constants

Defines

#define | DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000)
#define | DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001)

Define Documentation

#define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000)

Analog watchdog high threshold

Definition at line 449 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_IRQHandler().

#define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001)

Analog watchdog low threshold

Definition at line 450 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_IRQHandler().

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STM32H753xx HAL User Manual: DFSDM Exported Macros

Defines
DFSDM Exported Macros
DFSDM

Defines

#define | __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
Reset DFSDM channel handle state.
#define | __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
Reset DFSDM filter handle state.

Define Documentation

#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)

Reset DFSDM channel handle state.

Parameters:
__HANDLE__,: DFSDM channel handle.
Return values:
None

Definition at line 469 of file stm32h7xx_hal_dfsdm.h.

#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)

Reset DFSDM filter handle state.

Parameters:
__HANDLE__,: DFSDM filter handle.
Return values:
None

Definition at line 475 of file stm32h7xx_hal_dfsdm.h.

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STM32H753xx HAL User Manual: DFSDM Private Macros

Defines
DFSDM Private Macros
DFSDM

Defines

#define | IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK)
#define | IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))
#define | IS_DFSDM_CHANNEL_INPUT(INPUT)
#define | IS_DFSDM_CHANNEL_DATA_PACKING(MODE)
#define | IS_DFSDM_CHANNEL_INPUT_PINS(PINS)
#define | IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE)
#define | IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE)
#define | IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER)
#define | IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32))
#define | IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
#define | IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F)
#define | IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF)
#define | IS_DFSDM_FILTER_REG_TRIGGER(TRIG)
#define | IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)
#define | IS_DFSDM_FILTER_EXT_TRIG(TRIG)
#define | IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)
#define | IS_DFSDM_FILTER_SINC_ORDER(ORDER)
#define | IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024))
#define | IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256))
#define | IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA)
#define | IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
#define | IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xF)
#define | IS_DFSDM_REGULAR_CHANNEL(CHANNEL)
#define | IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FF))
#define | IS_DFSDM_CONTINUOUS_MODE(MODE)

Define Documentation

#define IS_DFSDM_BREAK_SIGNALS ( VALUE ) ((VALUE) <= 0xF)

Definition at line 685 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelScdStart(), HAL_DFSDM_ChannelScdStart_IT(), and HAL_DFSDM_FilterAwdStart_IT().

#define IS_DFSDM_CHANNEL_DATA_PACKING ( MODE )
Value:
(((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
                                                       ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
                                                       ((MODE) == DFSDM_CHANNEL_DUAL_MODE))

Definition at line 629 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_FILTER_ORDER ( ORDER )
Value:
(((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
                                                       ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
                                                       ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
                                                       ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))

Definition at line 642 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO ( RATIO ) ((1 <= (RATIO)) && ((RATIO) <= 32))

Definition at line 646 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_INPUT ( INPUT )
Value:
(((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
                                                       ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \
                                                       ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))

Definition at line 626 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_INPUT_PINS ( PINS )
Value:
(((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
                                                       ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))

Definition at line 632 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_OFFSET ( VALUE ) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))

Definition at line 647 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit(), and HAL_DFSDM_ChannelModifyOffset().

#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK ( CLOCK )
Value:
(((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
                                                       ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))

Definition at line 623 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER ( DIVIDER ) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))

Definition at line 625 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT ( VALUE ) ((VALUE) <= 0x1F)

Definition at line 648 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_SCD_THRESHOLD ( VALUE ) ((VALUE) <= 0xFF)

Definition at line 649 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelScdStart(), and HAL_DFSDM_ChannelScdStart_IT().

#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE ( MODE )
Value:
(((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
                                                       ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))

Definition at line 634 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_SPI_CLOCK ( TYPE )
Value:
(((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))

Definition at line 638 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CONTINUOUS_MODE ( MODE )
Value:
(((MODE) == DFSDM_CONTINUOUS_CONV_OFF)  || \
                                                       ((MODE) == DFSDM_CONTINUOUS_CONV_ON))

Definition at line 695 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterConfigRegChannel().

#define IS_DFSDM_FILTER_AWD_DATA_SOURCE ( DATA )
Value:
(((DATA) == DFSDM_FILTER_AWD_FILTER_DATA)  || \
                                                       ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))

Definition at line 682 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

#define IS_DFSDM_FILTER_AWD_THRESHOLD ( VALUE ) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))

Definition at line 684 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

#define IS_DFSDM_FILTER_EXT_TRIG ( TRIG )
Value:
(((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
                                                                                ((TRIG) == DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1) || \
                                                                                ((TRIG) == DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \
                                                                                ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1) || \
                                                                                ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM2) || \
                                                                                ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3))

Definition at line 655 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define IS_DFSDM_FILTER_EXT_TRIG_EDGE ( EDGE )
Value:
(((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE)  || \
                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE)  || \
                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))

Definition at line 671 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define IS_DFSDM_FILTER_INJ_TRIGGER ( TRIG )
Value:
(((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))

Definition at line 652 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO ( RATIO ) ((1 <= (RATIO)) && ((RATIO) <= 256))

Definition at line 681 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define IS_DFSDM_FILTER_OVS_RATIO ( RATIO ) ((1 <= (RATIO)) && ((RATIO) <= 1024))

Definition at line 680 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define IS_DFSDM_FILTER_REG_TRIGGER ( TRIG )
Value:
(((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))

Definition at line 650 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define IS_DFSDM_FILTER_SINC_ORDER ( ORDER )
Value:
(((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
                                                       ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
                                                       ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
                                                       ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
                                                       ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
                                                       ((ORDER) == DFSDM_FILTER_SINC5_ORDER))

Definition at line 674 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define IS_DFSDM_INJECTED_CHANNEL ( CHANNEL ) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FF))

Definition at line 694 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT(), HAL_DFSDM_FilterConfigInjChannel(), and HAL_DFSDM_FilterExdStart().

#define IS_DFSDM_REGULAR_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == DFSDM_CHANNEL_0)  || \
                                                       ((CHANNEL) == DFSDM_CHANNEL_1)  || \
                                                       ((CHANNEL) == DFSDM_CHANNEL_2)  || \
                                                       ((CHANNEL) == DFSDM_CHANNEL_3)  || \
                                                       ((CHANNEL) == DFSDM_CHANNEL_4)  || \
                                                       ((CHANNEL) == DFSDM_CHANNEL_5)  || \
                                                       ((CHANNEL) == DFSDM_CHANNEL_6)  || \
                                                       ((CHANNEL) == DFSDM_CHANNEL_7))

Definition at line 686 of file stm32h7xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterConfigRegChannel().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA Exported Types

Data Structures | Typedefs | Enumerations
DMA Exported Types
DMA

DMA Exported Types. More...

Data Structures

struct | DMA_InitTypeDef
DMA Configuration Structure definition. More...
struct | __DMA_HandleTypeDef
DMA handle Structure definition. More...

Typedefs

typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef
DMA handle Structure definition.

Enumerations

enum HAL_DMA_StateTypeDef {
HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_ERROR = 0x03U,
HAL_DMA_STATE_ABORT = 0x04U
}
HAL DMA State structures definition. More...
enum | HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01U }
HAL DMA Transfer complete level structure definition. More...
enum HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U, HAL_DMA_XFER_ABORT_CB_ID = 0x05U, HAL_DMA_XFER_ALL_CB_ID = 0x06U
}
HAL DMA Callbacks IDs structure definition. More...

Detailed Description

DMA Exported Types.

Typedef Documentation

typedef struct __DMA_HandleTypeDef DMA_HandleTypeDef

DMA handle Structure definition.

Enumeration Type Documentation

enum HAL_DMA_CallbackIDTypeDef

HAL DMA Callbacks IDs structure definition.

Enumerator:
HAL_DMA_XFER_CPLT_CB_ID

Full transfer

HAL_DMA_XFER_HALFCPLT_CB_ID

Half Transfer

HAL_DMA_XFER_M1CPLT_CB_ID

M1 Full Transfer

HAL_DMA_XFER_M1HALFCPLT_CB_ID

M1 Half Transfer

HAL_DMA_XFER_ERROR_CB_ID

Error

HAL_DMA_XFER_ABORT_CB_ID

Abort

HAL_DMA_XFER_ALL_CB_ID

All

Definition at line 141 of file stm32h7xx_hal_dma.h.

enum HAL_DMA_LevelCompleteTypeDef

HAL DMA Transfer complete level structure definition.

Enumerator:
HAL_DMA_FULL_TRANSFER

Full transfer

HAL_DMA_HALF_TRANSFER

Half Transfer

Definition at line 132 of file stm32h7xx_hal_dma.h.

enum HAL_DMA_StateTypeDef

HAL DMA State structures definition.

Enumerator:
HAL_DMA_STATE_RESET

DMA not yet initialized or disabled

HAL_DMA_STATE_READY

DMA initialized and ready for use

HAL_DMA_STATE_BUSY

DMA process is ongoing

HAL_DMA_STATE_ERROR

DMA error state

HAL_DMA_STATE_ABORT

DMA Abort state

Definition at line 120 of file stm32h7xx_hal_dma.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA_InitTypeDef Struct Reference
DMA Exported Types

DMA Configuration Structure definition. More...

#include <stm32h7xx_hal_dma.h>

Data Fields

uint32_t | Request
uint32_t | Direction
uint32_t | PeriphInc
uint32_t | MemInc
uint32_t | PeriphDataAlignment
uint32_t | MemDataAlignment
uint32_t | Mode
uint32_t | Priority
uint32_t | FIFOMode
uint32_t | FIFOThreshold
uint32_t | MemBurst
uint32_t | PeriphBurst

Detailed Description

DMA Configuration Structure definition.

Definition at line 67 of file stm32h7xx_hal_dma.h.

Field Documentation

uint32_t DMA_InitTypeDef::Direction

Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of DMA Data transfer direction

Definition at line 72 of file stm32h7xx_hal_dma.h.

Referenced by DMA_MultiBufferSetConfig(), DMA_SetConfig(), HAL_DMA_Init(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

uint32_t DMA_InitTypeDef::FIFOMode

Specifies if the FIFO mode or Direct mode will be used for the specified stream. This parameter can be a value of DMA FIFO direct mode

Note:
The Direct mode (FIFO mode disabled) cannot be used if the memory-to-memory data transfer is configured on the selected stream

Definition at line 96 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::FIFOThreshold

Specifies the FIFO threshold level. This parameter can be a value of DMA FIFO threshold level

Definition at line 101 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CheckFifoParam(), and HAL_DMA_Init().

uint32_t DMA_InitTypeDef::MemBurst

Specifies the Burst transfer configuration for the memory transfers. It specifies the amount of data to be transferred in a single non interruptible transaction. This parameter can be a value of DMA Memory burst

Note:
The burst mode is possible only if the address Increment mode is enabled.

Definition at line 104 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CheckFifoParam(), and HAL_DMA_Init().

uint32_t DMA_InitTypeDef::MemDataAlignment

Specifies the Memory data width. This parameter can be a value of DMA Memory data size

Definition at line 85 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CheckFifoParam(), HAL_DMA_Init(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

uint32_t DMA_InitTypeDef::MemInc

Specifies whether the memory address register should be incremented or not. This parameter can be a value of DMA Memory incremented mode

Definition at line 79 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Mode

Specifies the operation mode of the DMAy Streamx. This parameter can be a value of DMA mode

Note:
The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Stream

Definition at line 88 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DMA_Init(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), SAI_DMARxCplt(), SAI_DMATxCplt(), SPDIFRX_DMARxCplt(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), USART_DMAReceiveCplt(), and USART_DMATransmitCplt().

uint32_t DMA_InitTypeDef::PeriphBurst

Specifies the Burst transfer configuration for the peripheral transfers. It specifies the amount of data to be transferred in a single non interruptible transaction. This parameter can be a value of DMA Peripheral burst

Note:
The burst mode is possible only if the address Increment mode is enabled.

Definition at line 110 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::PeriphDataAlignment

Specifies the Peripheral data width. This parameter can be a value of DMA Peripheral data size

Definition at line 82 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::PeriphInc

Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of DMA Peripheral incremented mode

Definition at line 76 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Priority

Specifies the software priority for the DMAy Streamx. This parameter can be a value of DMA Priority level

Definition at line 93 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Request

Specifies the request selected for the specified stream. This parameter can be a value of DMA Request selection

Definition at line 69 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), GetTimerIdxFromDMAHandle(), and HAL_DMA_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dma.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: __DMA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__DMA_HandleTypeDef Struct Reference
DMA Exported Types

DMA handle Structure definition. More...

#include <stm32h7xx_hal_dma.h>

Data Fields

void * | Instance
DMA_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_DMA_StateTypeDef | State
void * | Parent
void(* | XferCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferHalfCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferM1CpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferM1HalfCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferErrorCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferAbortCallback )(struct __DMA_HandleTypeDef *hdma)
__IO uint32_t | ErrorCode
uint32_t | StreamBaseAddress
uint32_t | StreamIndex
DMAMUX_Channel_TypeDef * | DMAmuxChannel
DMAMUX_ChannelStatus_TypeDef * | DMAmuxChannelStatus
uint32_t | DMAmuxChannelStatusMask
DMAMUX_RequestGen_TypeDef * | DMAmuxRequestGen
DMAMUX_RequestGenStatus_TypeDef * | DMAmuxRequestGenStatus
uint32_t | DMAmuxRequestGenStatusMask

Detailed Description

DMA handle Structure definition.

Definition at line 155 of file stm32h7xx_hal_dma.h.

Field Documentation

DMAMUX_Channel_TypeDef* __DMA_HandleTypeDef::DMAmuxChannel

DMAMUX Channel Base Address

Definition at line 185 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXChannelBaseAndMask(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_Start_IT(), HAL_DMAEx_ConfigMuxSync(), HAL_DMAEx_MultiBufferStart_IT(), and HAL_DMAEx_MUX_IRQHandler().

DMAMUX_ChannelStatus_TypeDef* __DMA_HandleTypeDef::DMAmuxChannelStatus

DMAMUX Channels Status Base Address

Definition at line 187 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXChannelBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), and HAL_DMAEx_MUX_IRQHandler().

uint32_t __DMA_HandleTypeDef::DMAmuxChannelStatusMask

DMAMUX Channel Status Mask

Definition at line 189 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXChannelBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), and HAL_DMAEx_MUX_IRQHandler().

DMAMUX_RequestGen_TypeDef* __DMA_HandleTypeDef::DMAmuxRequestGen

DMAMUX request generator Base Address

Definition at line 192 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), HAL_DMA_Start_IT(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_DisableMuxRequestGenerator(), HAL_DMAEx_EnableMuxRequestGenerator(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), and HAL_DMAEx_MUX_IRQHandler().

DMAMUX_RequestGenStatus_TypeDef* __DMA_HandleTypeDef::DMAmuxRequestGenStatus

DMAMUX request generator Status Address

Definition at line 194 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), and HAL_DMAEx_MUX_IRQHandler().

uint32_t __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask

DMAMUX request generator Status mask

Definition at line 196 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), and HAL_DMAEx_MUX_IRQHandler().

__IO uint32_t __DMA_HandleTypeDef::ErrorCode

DMA Error code

Definition at line 179 of file stm32h7xx_hal_dma.h.

Referenced by DCMI_DMAError(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_GetError(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), HAL_DMAEx_MUX_IRQHandler(), HAL_SAI_DMAStop(), and SAI_DMAError().

DMA_InitTypeDef __DMA_HandleTypeDef::Init

DMA communication parameters

Definition at line 159 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_CheckFifoParam(), DMA_MultiBufferSetConfig(), DMA_SetConfig(), GetTimerIdxFromDMAHandle(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DMA_Init(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), SAI_DMARxCplt(), SAI_DMATxCplt(), SPDIFRX_DMARxCplt(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), USART_DMAReceiveCplt(), and USART_DMATransmitCplt().

void* __DMA_HandleTypeDef::Instance

Register base address

Definition at line 157 of file stm32h7xx_hal_dma.h.

Referenced by DCMI_DMAXferCplt(), DMA_CalcBaseAndBitshift(), DMA_CalcDMAMUXChannelBaseAndMask(), DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_MultiBufferSetConfig(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_Start_IT(), HAL_DMAEx_ChangeMemory(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_ConfigMuxSync(), HAL_DMAEx_DisableMuxRequestGenerator(), HAL_DMAEx_EnableMuxRequestGenerator(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), HAL_HASH_DMAFeed_ProcessSuspend(), I2S_DMARxCplt(), I2S_DMATxCplt(), I2SEx_DMATxRxCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SWPMI_DMAReceiveCplt(), and SWPMI_DMATransmitCplt().

HAL_LockTypeDef __DMA_HandleTypeDef::Lock

DMA locking object

Definition at line 161 of file stm32h7xx_hal_dma.h.

void* __DMA_HandleTypeDef::Parent

Parent object state

Definition at line 165 of file stm32h7xx_hal_dma.h.

Referenced by SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATransmitCplt(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxHalfCplt(), UART_DMATransmitCplt(), UART_DMATxAbortCallback(), UART_DMATxHalfCplt(), UART_DMATxOnlyAbortCallback(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxAbortCallback(), USART_DMARxHalfCplt(), USART_DMATransmitCplt(), USART_DMATxAbortCallback(), and USART_DMATxHalfCplt().

__IO HAL_DMA_StateTypeDef __DMA_HandleTypeDef::State

DMA transfer state

Definition at line 163 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_GetState(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_RegisterCallback(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMA_UnRegisterCallback(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_ConfigMuxSync(), HAL_DMAEx_DisableMuxRequestGenerator(), HAL_DMAEx_EnableMuxRequestGenerator(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

uint32_t __DMA_HandleTypeDef::StreamBaseAddress

DMA Stream Base Address

Definition at line 181 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcBaseAndBitshift(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

uint32_t __DMA_HandleTypeDef::StreamIndex

DMA Stream Index

Definition at line 183 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcBaseAndBitshift(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

void(* __DMA_HandleTypeDef::XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer Abort callback

Definition at line 177 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DCMI_IRQHandler(), HAL_DCMI_Start_DMA(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SAI_IRQHandler(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_SWPMI_IRQHandler(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_IRQHandler(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), I2C_DMAAbort(), I2C_ITError(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

void(* __DMA_HandleTypeDef::XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer complete callback

Definition at line 167 of file stm32h7xx_hal_dma.h.

Referenced by CRYP_SetDMAConfig(), HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DAC_Start_DMA(), HAL_DCMI_Start_DMA(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_HRTIM_BurstDMATransfer(), HAL_HRTIM_SimpleBaseStart_DMA(), HAL_HRTIM_SimpleCaptureStart_DMA(), HAL_HRTIM_SimpleOCStart_DMA(), HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_WaveformCounterStart_DMA(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_I2SEx_TransmitReceive_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Transmit_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), HASH_DMAXferCplt(), HASH_Start_DMA(), and HMAC_Start_DMA().

void(* __DMA_HandleTypeDef::XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer error callback

Definition at line 175 of file stm32h7xx_hal_dma.h.

Referenced by CRYP_SetDMAConfig(), HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DAC_Start_DMA(), HAL_DCMI_Start_DMA(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_DMAEx_MUX_IRQHandler(), HAL_HRTIM_BurstDMATransfer(), HAL_HRTIM_SimpleBaseStart_DMA(), HAL_HRTIM_SimpleCaptureStart_DMA(), HAL_HRTIM_SimpleOCStart_DMA(), HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_WaveformCounterStart_DMA(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_I2SEx_TransmitReceive_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Transmit_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), HASH_Start_DMA(), and HMAC_Start_DMA().

void(* __DMA_HandleTypeDef::XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA Half transfer complete callback

Definition at line 169 of file stm32h7xx_hal_dma.h.

Referenced by HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DAC_Start_DMA(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_Start_IT(), HAL_DMA_UnRegisterCallback(), HAL_DMAEx_MultiBufferStart_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_I2SEx_TransmitReceive_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Transmit_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

void(* __DMA_HandleTypeDef::XferM1CpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer complete Memory1 callback

Definition at line 171 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DCMI_Start_DMA(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), and HAL_DMA_UnRegisterCallback().

void(* __DMA_HandleTypeDef::XferM1HalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer Half complete Memory1 callback

Definition at line 173 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), and HAL_DMA_UnRegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dma.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA Error Code

Defines
DMA Error Code
DMA Exported Constants

DMA Error Code. More...

Defines

#define | HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_DMA_ERROR_TE ((uint32_t)0x00000001U)
#define | HAL_DMA_ERROR_FE ((uint32_t)0x00000002U)
#define | HAL_DMA_ERROR_DME ((uint32_t)0x00000004U)
#define | HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U)
#define | HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U)
#define | HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U)
#define | HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U)
#define | HAL_DMA_ERROR_SYNC ((uint32_t)0x00000200U)
#define | HAL_DMA_ERROR_REQGEN ((uint32_t)0x00000400U)

Detailed Description

DMA Error Code.

Define Documentation

#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U)

Direct Mode error

Definition at line 219 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U)

FIFO error

Definition at line 218 of file stm32h7xx_hal_dma.h.

Referenced by DCMI_DMAError(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), SAI_DMAError(), and UART_DMAError().

#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U)

Abort requested with no Xfer ongoing

Definition at line 222 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_PollForTransfer(), and HAL_SAI_DMAStop().

#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 216 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_MultiBufferStart_IT(), HAL_MMC_Erase(), HAL_MMC_Init(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_SD_Erase(), HAL_SD_Init(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), and MMC_ReadExtCSD().

#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U)

Not supported mode

Definition at line 223 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

#define HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U)

Parameter error

Definition at line 221 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define HAL_DMA_ERROR_REQGEN ((uint32_t)0x00000400U)

DMAMUX request generator overrun error

Definition at line 225 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

#define HAL_DMA_ERROR_SYNC ((uint32_t)0x00000200U)

DMAMUX sync overrun error

Definition at line 224 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U)

Transfer error

Definition at line 217 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), and SAI_DMAError().

#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U)

Timeout error

Definition at line 220 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Init(), and HAL_DMA_PollForTransfer().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA Request selection

Defines
DMA Request selection
DMA Exported Constants

DMA Request selection. More...

Defines

#define | DMA_REQUEST_MEM2MEM ((uint32_t)0x00000000)
#define | DMA_REQUEST_GENERATOR0 ((uint32_t)0x00000001)
#define | DMA_REQUEST_GENERATOR1 ((uint32_t)0x00000002)
#define | DMA_REQUEST_GENERATOR2 ((uint32_t)0x00000003)
#define | DMA_REQUEST_GENERATOR3 ((uint32_t)0x00000004)
#define | DMA_REQUEST_GENERATOR4 ((uint32_t)0x00000005)
#define | DMA_REQUEST_GENERATOR5 ((uint32_t)0x00000006)
#define | DMA_REQUEST_GENERATOR6 ((uint32_t)0x00000007)
#define | DMA_REQUEST_GENERATOR7 ((uint32_t)0x00000008)
#define | DMA_REQUEST_ADC1 ((uint32_t)0x00000009)
#define | DMA_REQUEST_ADC2 ((uint32_t)0x0000000A)
#define | DMA_REQUEST_TIM1_CH1 ((uint32_t)0x0000000B)
#define | DMA_REQUEST_TIM1_CH2 ((uint32_t)0x0000000C)
#define | DMA_REQUEST_TIM1_CH3 ((uint32_t)0x0000000D)
#define | DMA_REQUEST_TIM1_CH4 ((uint32_t)0x0000000E)
#define | DMA_REQUEST_TIM1_UP ((uint32_t)0x0000000F)
#define | DMA_REQUEST_TIM1_TRIG ((uint32_t)0x00000010)
#define | DMA_REQUEST_TIM1_COM ((uint32_t)0x00000011)
#define | DMA_REQUEST_TIM2_CH1 ((uint32_t)0x00000012)
#define | DMA_REQUEST_TIM2_CH2 ((uint32_t)0x00000013)
#define | DMA_REQUEST_TIM2_CH3 ((uint32_t)0x00000014)
#define | DMA_REQUEST_TIM2_CH4 ((uint32_t)0x00000015)
#define | DMA_REQUEST_TIM2_UP ((uint32_t)0x00000016)
#define | DMA_REQUEST_TIM3_CH1 ((uint32_t)0x00000017)
#define | DMA_REQUEST_TIM3_CH2 ((uint32_t)0x00000018)
#define | DMA_REQUEST_TIM3_CH3 ((uint32_t)0x00000019)
#define | DMA_REQUEST_TIM3_CH4 ((uint32_t)0x0000001A)
#define | DMA_REQUEST_TIM3_UP ((uint32_t)0x0000001B)
#define | DMA_REQUEST_TIM3_TRIG ((uint32_t)0x0000001C)
#define | DMA_REQUEST_TIM4_CH1 ((uint32_t)0x0000001D)
#define | DMA_REQUEST_TIM4_CH2 ((uint32_t)0x0000001E)
#define | DMA_REQUEST_TIM4_CH3 ((uint32_t)0x0000001F)
#define | DMA_REQUEST_TIM4_UP ((uint32_t)0x00000020)
#define | DMA_REQUEST_I2C1_RX ((uint32_t)0x00000021)
#define | DMA_REQUEST_I2C1_TX ((uint32_t)0x00000022)
#define | DMA_REQUEST_I2C2_RX ((uint32_t)0x00000023)
#define | DMA_REQUEST_I2C2_TX ((uint32_t)0x00000024)
#define | DMA_REQUEST_SPI1_RX ((uint32_t)0x00000025)
#define | DMA_REQUEST_SPI1_TX ((uint32_t)0x00000026)
#define | DMA_REQUEST_SPI2_RX ((uint32_t)0x00000027)
#define | DMA_REQUEST_SPI2_TX ((uint32_t)0x00000028)
#define | DMA_REQUEST_USART1_RX ((uint32_t)0x00000029)
#define | DMA_REQUEST_USART1_TX ((uint32_t)0x0000002A)
#define | DMA_REQUEST_USART2_RX ((uint32_t)0x0000002B)
#define | DMA_REQUEST_USART2_TX ((uint32_t)0x0000002C)
#define | DMA_REQUEST_USART3_RX ((uint32_t)0x0000002D)
#define | DMA_REQUEST_USART3_TX ((uint32_t)0x0000002E)
#define | DMA_REQUEST_TIM8_CH1 ((uint32_t)0x0000002F)
#define | DMA_REQUEST_TIM8_CH2 ((uint32_t)0x00000030)
#define | DMA_REQUEST_TIM8_CH3 ((uint32_t)0x00000031)
#define | DMA_REQUEST_TIM8_CH4 ((uint32_t)0x00000032)
#define | DMA_REQUEST_TIM8_UP ((uint32_t)0x00000033)
#define | DMA_REQUEST_TIM8_TRIG ((uint32_t)0x00000034)
#define | DMA_REQUEST_TIM8_COM ((uint32_t)0x00000035)
#define | DMA_REQUEST_TIM5_CH1 ((uint32_t)0x00000037)
#define | DMA_REQUEST_TIM5_CH2 ((uint32_t)0x00000038)
#define | DMA_REQUEST_TIM5_CH3 ((uint32_t)0x00000039)
#define | DMA_REQUEST_TIM5_CH4 ((uint32_t)0x0000003A)
#define | DMA_REQUEST_TIM5_UP ((uint32_t)0x0000003B)
#define | DMA_REQUEST_TIM5_TRIG ((uint32_t)0x0000003C)
#define | DMA_REQUEST_SPI3_RX ((uint32_t)0x0000003D)
#define | DMA_REQUEST_SPI3_TX ((uint32_t)0x0000003E)
#define | DMA_REQUEST_UART4_RX ((uint32_t)0x0000003F)
#define | DMA_REQUEST_UART4_TX ((uint32_t)0x00000040)
#define | DMA_REQUEST_UART5_RX ((uint32_t)0x00000041)
#define | DMA_REQUEST_UART5_TX ((uint32_t)0x00000042)
#define | DMA_REQUEST_DAC1 ((uint32_t)0x00000043)
#define | DMA_REQUEST_DAC2 ((uint32_t)0x00000044)
#define | DMA_REQUEST_TIM6_UP ((uint32_t)0x00000045)
#define | DMA_REQUEST_TIM7_UP ((uint32_t)0x00000046)
#define | DMA_REQUEST_USART6_RX ((uint32_t)0x00000047)
#define | DMA_REQUEST_USART6_TX ((uint32_t)0x00000048)
#define | DMA_REQUEST_I2C3_RX ((uint32_t)0x00000049)
#define | DMA_REQUEST_I2C3_TX ((uint32_t)0x0000004A)
#define | DMA_REQUEST_DCMI ((uint32_t)0x0000004B)
#define | DMA_REQUEST_CRYP_IN ((uint32_t)0x0000004C)
#define | DMA_REQUEST_CRYP_OUT ((uint32_t)0x0000004D)
#define | DMA_REQUEST_HASH_IN ((uint32_t)0x0000004E)
#define | DMA_REQUEST_UART7_RX ((uint32_t)0x0000004F)
#define | DMA_REQUEST_UART7_TX ((uint32_t)0x00000050)
#define | DMA_REQUEST_UART8_RX ((uint32_t)0x00000051)
#define | DMA_REQUEST_UART8_TX ((uint32_t)0x00000052)
#define | DMA_REQUEST_SPI4_RX ((uint32_t)0x00000053)
#define | DMA_REQUEST_SPI4_TX ((uint32_t)0x00000054)
#define | DMA_REQUEST_SPI5_RX ((uint32_t)0x00000055)
#define | DMA_REQUEST_SPI5_TX ((uint32_t)0x00000056)
#define | DMA_REQUEST_SAI1_A ((uint32_t)0x00000057)
#define | DMA_REQUEST_SAI1_B ((uint32_t)0x00000058)
#define | DMA_REQUEST_SAI2_A ((uint32_t)0x00000059)
#define | DMA_REQUEST_SAI2_B ((uint32_t)0x0000005A)
#define | DMA_REQUEST_SWPMI_RX ((uint32_t)0x0000005B)
#define | DMA_REQUEST_SWPMI_TX ((uint32_t)0x0000005C)
#define | DMA_REQUEST_SPDIF_RX_DT ((uint32_t)0x0000005D)
#define | DMA_REQUEST_SPDIF_RX_CS ((uint32_t)0x0000005E)
#define | DMA_REQUEST_HRTIM_MASTER ((uint32_t)0x0000005F)
#define | DMA_REQUEST_HRTIM_TIMER_A ((uint32_t)0x00000060)
#define | DMA_REQUEST_HRTIM_TIMER_B ((uint32_t)0x00000061)
#define | DMA_REQUEST_HRTIM_TIMER_C ((uint32_t)0x00000062)
#define | DMA_REQUEST_HRTIM_TIMER_D ((uint32_t)0x00000063)
#define | DMA_REQUEST_HRTIM_TIMER_E ((uint32_t)0x00000064)
#define | DMA_REQUEST_DFSDM1_FLT0 ((uint32_t)0x00000065)
#define | DMA_REQUEST_DFSDM1_FLT1 ((uint32_t)0x00000066)
#define | DMA_REQUEST_DFSDM1_FLT2 ((uint32_t)0x00000067)
#define | DMA_REQUEST_DFSDM1_FLT3 ((uint32_t)0x00000068)
#define | DMA_REQUEST_TIM15_CH1 ((uint32_t)0x00000069)
#define | DMA_REQUEST_TIM15_UP ((uint32_t)0x0000006A)
#define | DMA_REQUEST_TIM15_TRIG ((uint32_t)0x0000006B)
#define | DMA_REQUEST_TIM15_COM ((uint32_t)0x0000006C)
#define | DMA_REQUEST_TIM16_CH1 ((uint32_t)0x0000006D)
#define | DMA_REQUEST_TIM16_UP ((uint32_t)0x0000006E)
#define | DMA_REQUEST_TIM17_CH1 ((uint32_t)0x0000006F)
#define | DMA_REQUEST_TIM17_UP ((uint32_t)0x00000070)
#define | DMA_REQUEST_SAI3_A ((uint32_t)0x00000071)
#define | DMA_REQUEST_SAI3_B ((uint32_t)0x00000072)
#define | DMA_REQUEST_ADC3 ((uint32_t)0x00000073)
#define | BDMA_REQUEST_MEM2MEM ((uint32_t)0x00000000)
#define | BDMA_REQUEST_GENERATOR0 ((uint32_t)0x10000001)
#define | BDMA_REQUEST_GENERATOR1 ((uint32_t)0x10000002)
#define | BDMA_REQUEST_GENERATOR2 ((uint32_t)0x10000003)
#define | BDMA_REQUEST_GENERATOR3 ((uint32_t)0x10000004)
#define | BDMA_REQUEST_GENERATOR4 ((uint32_t)0x10000005)
#define | BDMA_REQUEST_GENERATOR5 ((uint32_t)0x10000006)
#define | BDMA_REQUEST_GENERATOR6 ((uint32_t)0x10000007)
#define | BDMA_REQUEST_GENERATOR7 ((uint32_t)0x10000008)
#define | BDMA_REQUEST_LP_UART1_RX ((uint32_t)0x10000009)
#define | BDMA_REQUEST_LP_UART1_TX ((uint32_t)0x1000000A)
#define | BDMA_REQUEST_SPI6_RX ((uint32_t)0x1000000B)
#define | BDMA_REQUEST_SPI6_TX ((uint32_t)0x1000000C)
#define | BDMA_REQUEST_I2C4_RX ((uint32_t)0x1000000D)
#define | BDMA_REQUEST_I2C4_TX ((uint32_t)0x1000000E)
#define | BDMA_REQUEST_SAI4_A ((uint32_t)0x1000000F)
#define | BDMA_REQUEST_SAI4_B ((uint32_t)0x10000010)
#define | BDMA_REQUEST_ADC3 ((uint32_t)0x10000011)

Detailed Description

DMA Request selection.

Define Documentation

#define BDMA_REQUEST_ADC3 ((uint32_t)0x10000011)

DMAMUX2 ADC3 request

Definition at line 403 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_GENERATOR0 ((uint32_t)0x10000001)

DMAMUX2 request generator 0

Definition at line 387 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define BDMA_REQUEST_GENERATOR1 ((uint32_t)0x10000002)

DMAMUX2 request generator 1

Definition at line 388 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_GENERATOR2 ((uint32_t)0x10000003)

DMAMUX2 request generator 2

Definition at line 389 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_GENERATOR3 ((uint32_t)0x10000004)

DMAMUX2 request generator 3

Definition at line 390 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_GENERATOR4 ((uint32_t)0x10000005)

DMAMUX2 request generator 4

Definition at line 391 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_GENERATOR5 ((uint32_t)0x10000006)

DMAMUX2 request generator 5

Definition at line 392 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_GENERATOR6 ((uint32_t)0x10000007)

DMAMUX2 request generator 6

Definition at line 393 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_GENERATOR7 ((uint32_t)0x10000008)

DMAMUX2 request generator 7

Definition at line 394 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define BDMA_REQUEST_I2C4_RX ((uint32_t)0x1000000D)

DMAMUX2 I2C4 RX request

Definition at line 399 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_I2C4_TX ((uint32_t)0x1000000E)

DMAMUX2 I2C4 TX request

Definition at line 400 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_LP_UART1_RX ((uint32_t)0x10000009)

DMAMUX2 LP_UART1_RX request

Definition at line 395 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_LP_UART1_TX ((uint32_t)0x1000000A)

DMAMUX2 LP_UART1_TX request

Definition at line 396 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_MEM2MEM ((uint32_t)0x00000000)

memory to memory transfer

Definition at line 386 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_SAI4_A ((uint32_t)0x1000000F)

DMAMUX2 SAI4 A request

Definition at line 401 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_SAI4_B ((uint32_t)0x10000010)

DMAMUX2 SAI4 B request

Definition at line 402 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_SPI6_RX ((uint32_t)0x1000000B)

DMAMUX2 SPI6 RX request

Definition at line 397 of file stm32h7xx_hal_dma.h.

#define BDMA_REQUEST_SPI6_TX ((uint32_t)0x1000000C)

DMAMUX2 SPI6 TX request

Definition at line 398 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_ADC1 ((uint32_t)0x00000009)

DMAMUX1 ADC1 request

Definition at line 247 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_ADC2 ((uint32_t)0x0000000A)

DMAMUX1 ADC2 request

Definition at line 248 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_ADC3 ((uint32_t)0x00000073)

DMAMUX1 ADC3 request

Definition at line 382 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_CRYP_IN ((uint32_t)0x0000004C)

DMAMUX1 CRYP IN request

Definition at line 330 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_CRYP_OUT ((uint32_t)0x0000004D)

DMAMUX1 CRYP OUT request

Definition at line 331 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_DAC1 ((uint32_t)0x00000043)

DMAMUX1 DAC1 request

Definition at line 316 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_DAC2 ((uint32_t)0x00000044)

DMAMUX1 DAC2 request

Definition at line 317 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_DCMI ((uint32_t)0x0000004B)

DMAMUX1 DCMI request

Definition at line 328 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_DFSDM1_FLT0 ((uint32_t)0x00000065)

DMAMUX1 DFSDM Filter0 request

Definition at line 363 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_DFSDM1_FLT1 ((uint32_t)0x00000066)

DMAMUX1 DFSDM Filter1 request

Definition at line 364 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_DFSDM1_FLT2 ((uint32_t)0x00000067)

DMAMUX1 DFSDM Filter2 request

Definition at line 365 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_DFSDM1_FLT3 ((uint32_t)0x00000068)

DMAMUX1 DFSDM Filter3 request

Definition at line 366 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR0 ((uint32_t)0x00000001)

DMAMUX1 request generator 0

Definition at line 238 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), and HAL_DMA_Init().

#define DMA_REQUEST_GENERATOR1 ((uint32_t)0x00000002)

DMAMUX1 request generator 1

Definition at line 239 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR2 ((uint32_t)0x00000003)

DMAMUX1 request generator 2

Definition at line 240 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR3 ((uint32_t)0x00000004)

DMAMUX1 request generator 3

Definition at line 241 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR4 ((uint32_t)0x00000005)

DMAMUX1 request generator 4

Definition at line 242 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR5 ((uint32_t)0x00000006)

DMAMUX1 request generator 5

Definition at line 243 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR6 ((uint32_t)0x00000007)

DMAMUX1 request generator 6

Definition at line 244 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR7 ((uint32_t)0x00000008)

DMAMUX1 request generator 7

Definition at line 245 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), and HAL_DMA_Init().

#define DMA_REQUEST_HASH_IN ((uint32_t)0x0000004E)

DMAMUX1 HASH IN request

Definition at line 333 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_HRTIM_MASTER ((uint32_t)0x0000005F)

DMAMUX1 HRTIM1 Master request 1

Definition at line 356 of file stm32h7xx_hal_dma.h.

Referenced by GetTimerIdxFromDMAHandle().

#define DMA_REQUEST_HRTIM_TIMER_A ((uint32_t)0x00000060)

DMAMUX1 HRTIM1 TimerA request 2

Definition at line 357 of file stm32h7xx_hal_dma.h.

Referenced by GetTimerIdxFromDMAHandle().

#define DMA_REQUEST_HRTIM_TIMER_B ((uint32_t)0x00000061)

DMAMUX1 HRTIM1 TimerB request 3

Definition at line 358 of file stm32h7xx_hal_dma.h.

Referenced by GetTimerIdxFromDMAHandle().

#define DMA_REQUEST_HRTIM_TIMER_C ((uint32_t)0x00000062)

DMAMUX1 HRTIM1 TimerC request 4

Definition at line 359 of file stm32h7xx_hal_dma.h.

Referenced by GetTimerIdxFromDMAHandle().

#define DMA_REQUEST_HRTIM_TIMER_D ((uint32_t)0x00000063)

DMAMUX1 HRTIM1 TimerD request 5

Definition at line 360 of file stm32h7xx_hal_dma.h.

Referenced by GetTimerIdxFromDMAHandle().

#define DMA_REQUEST_HRTIM_TIMER_E ((uint32_t)0x00000064)

DMAMUX1 HRTIM1 TimerE request 6

Definition at line 361 of file stm32h7xx_hal_dma.h.

Referenced by GetTimerIdxFromDMAHandle().

#define DMA_REQUEST_I2C1_RX ((uint32_t)0x00000021)

DMAMUX1 I2C1 RX request

Definition at line 276 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_I2C1_TX ((uint32_t)0x00000022)

DMAMUX1 I2C1 TX request

Definition at line 277 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_I2C2_RX ((uint32_t)0x00000023)

DMAMUX1 I2C2 RX request

Definition at line 278 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_I2C2_TX ((uint32_t)0x00000024)

DMAMUX1 I2C2 TX request

Definition at line 279 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_I2C3_RX ((uint32_t)0x00000049)

DMAMUX1 I2C3 RX request

Definition at line 325 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_I2C3_TX ((uint32_t)0x0000004A)

DMAMUX1 I2C3 TX request

Definition at line 326 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_MEM2MEM ((uint32_t)0x00000000)

memory to memory transfer

Definition at line 236 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define DMA_REQUEST_SAI1_A ((uint32_t)0x00000057)

DMAMUX1 SAI1 A request

Definition at line 345 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SAI1_B ((uint32_t)0x00000058)

DMAMUX1 SAI1 B request

Definition at line 346 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SAI2_A ((uint32_t)0x00000059)

DMAMUX1 SAI2 A request

Definition at line 347 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SAI2_B ((uint32_t)0x0000005A)

DMAMUX1 SAI2 B request

Definition at line 348 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SAI3_A ((uint32_t)0x00000071)

DMAMUX1 SAI3 A request

Definition at line 379 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SAI3_B ((uint32_t)0x00000072)

DMAMUX1 SAI3 B request

Definition at line 380 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPDIF_RX_CS ((uint32_t)0x0000005E)

DMAMUX1 SPDIF RXCS request

Definition at line 354 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPDIF_RX_DT ((uint32_t)0x0000005D)

DMAMUX1 SPDIF RXDT request

Definition at line 353 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPI1_RX ((uint32_t)0x00000025)

DMAMUX1 SPI1 RX request

Definition at line 281 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPI1_TX ((uint32_t)0x00000026)

DMAMUX1 SPI1 TX request

Definition at line 282 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPI2_RX ((uint32_t)0x00000027)

DMAMUX1 SPI2 RX request

Definition at line 283 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPI2_TX ((uint32_t)0x00000028)

DMAMUX1 SPI2 TX request

Definition at line 284 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPI3_RX ((uint32_t)0x0000003D)

DMAMUX1 SPI3 RX request

Definition at line 308 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPI3_TX ((uint32_t)0x0000003E)

DMAMUX1 SPI3 TX request

Definition at line 309 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPI4_RX ((uint32_t)0x00000053)

DMAMUX1 SPI4 RX request

Definition at line 340 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPI4_TX ((uint32_t)0x00000054)

DMAMUX1 SPI4 TX request

Definition at line 341 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPI5_RX ((uint32_t)0x00000055)

DMAMUX1 SPI5 RX request

Definition at line 342 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SPI5_TX ((uint32_t)0x00000056)

DMAMUX1 SPI5 TX request

Definition at line 343 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SWPMI_RX ((uint32_t)0x0000005B)

DMAMUX1 SWPMI RX request

Definition at line 350 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_SWPMI_TX ((uint32_t)0x0000005C)

DMAMUX1 SWPMI TX request

Definition at line 351 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM15_CH1 ((uint32_t)0x00000069)

DMAMUX1 TIM15 CH1 request

Definition at line 368 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM15_COM ((uint32_t)0x0000006C)

DMAMUX1 TIM15 COM request

Definition at line 371 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM15_TRIG ((uint32_t)0x0000006B)

DMAMUX1 TIM15 TRIG request

Definition at line 370 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM15_UP ((uint32_t)0x0000006A)

DMAMUX1 TIM15 UP request

Definition at line 369 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM16_CH1 ((uint32_t)0x0000006D)

DMAMUX1 TIM16 CH1 request

Definition at line 373 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM16_UP ((uint32_t)0x0000006E)

DMAMUX1 TIM16 UP request

Definition at line 374 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM17_CH1 ((uint32_t)0x0000006F)

DMAMUX1 TIM17 CH1 request

Definition at line 376 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM17_UP ((uint32_t)0x00000070)

DMAMUX1 TIM17 UP request

Definition at line 377 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM1_CH1 ((uint32_t)0x0000000B)

DMAMUX1 TIM1 CH1 request

Definition at line 250 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM1_CH2 ((uint32_t)0x0000000C)

DMAMUX1 TIM1 CH2 request

Definition at line 251 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM1_CH3 ((uint32_t)0x0000000D)

DMAMUX1 TIM1 CH3 request

Definition at line 252 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM1_CH4 ((uint32_t)0x0000000E)

DMAMUX1 TIM1 CH4 request

Definition at line 253 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM1_COM ((uint32_t)0x00000011)

DMAMUX1 TIM1 COM request

Definition at line 256 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM1_TRIG ((uint32_t)0x00000010)

DMAMUX1 TIM1 TRIG request

Definition at line 255 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM1_UP ((uint32_t)0x0000000F)

DMAMUX1 TIM1 UP request

Definition at line 254 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM2_CH1 ((uint32_t)0x00000012)

DMAMUX1 TIM2 CH1 request

Definition at line 258 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM2_CH2 ((uint32_t)0x00000013)

DMAMUX1 TIM2 CH2 request

Definition at line 259 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM2_CH3 ((uint32_t)0x00000014)

DMAMUX1 TIM2 CH3 request

Definition at line 260 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM2_CH4 ((uint32_t)0x00000015)

DMAMUX1 TIM2 CH4 request

Definition at line 261 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM2_UP ((uint32_t)0x00000016)

DMAMUX1 TIM2 UP request

Definition at line 262 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM3_CH1 ((uint32_t)0x00000017)

DMAMUX1 TIM3 CH1 request

Definition at line 264 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM3_CH2 ((uint32_t)0x00000018)

DMAMUX1 TIM3 CH2 request

Definition at line 265 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM3_CH3 ((uint32_t)0x00000019)

DMAMUX1 TIM3 CH3 request

Definition at line 266 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM3_CH4 ((uint32_t)0x0000001A)

DMAMUX1 TIM3 CH4 request

Definition at line 267 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM3_TRIG ((uint32_t)0x0000001C)

DMAMUX1 TIM3 TRIG request

Definition at line 269 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM3_UP ((uint32_t)0x0000001B)

DMAMUX1 TIM3 UP request

Definition at line 268 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM4_CH1 ((uint32_t)0x0000001D)

DMAMUX1 TIM4 CH1 request

Definition at line 271 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM4_CH2 ((uint32_t)0x0000001E)

DMAMUX1 TIM4 CH2 request

Definition at line 272 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM4_CH3 ((uint32_t)0x0000001F)

DMAMUX1 TIM4 CH3 request

Definition at line 273 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM4_UP ((uint32_t)0x00000020)

DMAMUX1 TIM4 UP request

Definition at line 274 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM5_CH1 ((uint32_t)0x00000037)

DMAMUX1 TIM5 CH1 request

Definition at line 301 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM5_CH2 ((uint32_t)0x00000038)

DMAMUX1 TIM5 CH2 request

Definition at line 302 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM5_CH3 ((uint32_t)0x00000039)

DMAMUX1 TIM5 CH3 request

Definition at line 303 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM5_CH4 ((uint32_t)0x0000003A)

DMAMUX1 TIM5 CH4 request

Definition at line 304 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM5_TRIG ((uint32_t)0x0000003C)

DMAMUX1 TIM5 TRIG request

Definition at line 306 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM5_UP ((uint32_t)0x0000003B)

DMAMUX1 TIM5 UP request

Definition at line 305 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM6_UP ((uint32_t)0x00000045)

DMAMUX1 TIM6 UP request

Definition at line 319 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM7_UP ((uint32_t)0x00000046)

DMAMUX1 TIM7 UP request

Definition at line 320 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM8_CH1 ((uint32_t)0x0000002F)

DMAMUX1 TIM8 CH1 request

Definition at line 293 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM8_CH2 ((uint32_t)0x00000030)

DMAMUX1 TIM8 CH2 request

Definition at line 294 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM8_CH3 ((uint32_t)0x00000031)

DMAMUX1 TIM8 CH3 request

Definition at line 295 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM8_CH4 ((uint32_t)0x00000032)

DMAMUX1 TIM8 CH4 request

Definition at line 296 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM8_COM ((uint32_t)0x00000035)

DMAMUX1 TIM8 COM request

Definition at line 299 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM8_TRIG ((uint32_t)0x00000034)

DMAMUX1 TIM8 TRIG request

Definition at line 298 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_TIM8_UP ((uint32_t)0x00000033)

DMAMUX1 TIM8 UP request

Definition at line 297 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_UART4_RX ((uint32_t)0x0000003F)

DMAMUX1 UART4 RX request

Definition at line 311 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_UART4_TX ((uint32_t)0x00000040)

DMAMUX1 UART4 TX request

Definition at line 312 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_UART5_RX ((uint32_t)0x00000041)

DMAMUX1 UART5 RX request

Definition at line 313 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_UART5_TX ((uint32_t)0x00000042)

DMAMUX1 UART5 TX request

Definition at line 314 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_UART7_RX ((uint32_t)0x0000004F)

DMAMUX1 UART7 RX request

Definition at line 335 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_UART7_TX ((uint32_t)0x00000050)

DMAMUX1 UART7 TX request

Definition at line 336 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_UART8_RX ((uint32_t)0x00000051)

DMAMUX1 UART8 RX request

Definition at line 337 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_UART8_TX ((uint32_t)0x00000052)

DMAMUX1 UART8 TX request

Definition at line 338 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_USART1_RX ((uint32_t)0x00000029)

DMAMUX1 USART1 RX request

Definition at line 286 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_USART1_TX ((uint32_t)0x0000002A)

DMAMUX1 USART1 TX request

Definition at line 287 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_USART2_RX ((uint32_t)0x0000002B)

DMAMUX1 USART2 RX request

Definition at line 288 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_USART2_TX ((uint32_t)0x0000002C)

DMAMUX1 USART2 TX request

Definition at line 289 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_USART3_RX ((uint32_t)0x0000002D)

DMAMUX1 USART3 RX request

Definition at line 290 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_USART3_TX ((uint32_t)0x0000002E)

DMAMUX1 USART3 TX request

Definition at line 291 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_USART6_RX ((uint32_t)0x00000047)

DMAMUX1 USART6 RX request

Definition at line 322 of file stm32h7xx_hal_dma.h.

#define DMA_REQUEST_USART6_TX ((uint32_t)0x00000048)

DMAMUX1 USART6 TX request

Definition at line 323 of file stm32h7xx_hal_dma.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA Data transfer direction

Defines
DMA Data transfer direction
DMA Exported Constants

DMA data transfer direction. More...

Defines

#define | DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U)
#define | DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0)
#define | DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1)

Detailed Description

DMA data transfer direction.

Define Documentation

#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1)

Memory to memory direction

Definition at line 415 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0)

Memory to peripheral direction

Definition at line 414 of file stm32h7xx_hal_dma.h.

Referenced by DMA_MultiBufferSetConfig(), and DMA_SetConfig().

#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U)

Peripheral to memory direction

Definition at line 413 of file stm32h7xx_hal_dma.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA Peripheral incremented mode

Defines
DMA Peripheral incremented mode
DMA Exported Constants

DMA peripheral incremented mode. More...

Defines

#define | DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC)
#define | DMA_PINC_DISABLE ((uint32_t)0x00000000U)

Detailed Description

DMA peripheral incremented mode.

Define Documentation

#define DMA_PINC_DISABLE ((uint32_t)0x00000000U)

Peripheral increment mode disable

Definition at line 425 of file stm32h7xx_hal_dma.h.

#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC)

Peripheral increment mode enable

Definition at line 424 of file stm32h7xx_hal_dma.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA Memory incremented mode

Defines
DMA Memory incremented mode
DMA Exported Constants

DMA memory incremented mode. More...

Defines

#define | DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC)
#define | DMA_MINC_DISABLE ((uint32_t)0x00000000U)

Detailed Description

DMA memory incremented mode.

Define Documentation

#define DMA_MINC_DISABLE ((uint32_t)0x00000000U)

Memory increment mode disable

Definition at line 435 of file stm32h7xx_hal_dma.h.

#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC)

Memory increment mode enable

Definition at line 434 of file stm32h7xx_hal_dma.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA Peripheral data size

Defines
DMA Peripheral data size
DMA Exported Constants

DMA peripheral data size. More...

Defines

#define | DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U)
#define | DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0)
#define | DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1)

Detailed Description

DMA peripheral data size.

Define Documentation

#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U)

Peripheral data alignment: Byte

Definition at line 444 of file stm32h7xx_hal_dma.h.

#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0)

Peripheral data alignment: HalfWord

Definition at line 445 of file stm32h7xx_hal_dma.h.

#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1)

Peripheral data alignment: Word

Definition at line 446 of file stm32h7xx_hal_dma.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA Memory data size

Defines
DMA Memory data size
DMA Exported Constants

DMA memory data size. More...

Defines

#define | DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U)
#define | DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0)
#define | DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1)

Detailed Description

DMA memory data size.

Define Documentation

#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U)

Memory data alignment: Byte

Definition at line 455 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CheckFifoParam().

#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0)

Memory data alignment: HalfWord

Definition at line 456 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CheckFifoParam(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1)

Memory data alignment: Word

Definition at line 457 of file stm32h7xx_hal_dma.h.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA mode

Defines
DMA mode
DMA Exported Constants

DMA mode. More...

Defines

#define | DMA_NORMAL ((uint32_t)0x00000000U)
#define | DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC)
#define | DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)

Detailed Description

DMA mode.

Define Documentation

#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC)

Circular mode

Definition at line 467 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), SAI_DMARxCplt(), SAI_DMATxCplt(), SPDIFRX_DMARxCplt(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), USART_DMAReceiveCplt(), and USART_DMATransmitCplt().

#define DMA_NORMAL ((uint32_t)0x00000000U)

Normal mode

Definition at line 466 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), and HAL_DFSDM_FilterRegularStart_DMA().

#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)

Peripheral flow control mode

Definition at line 468 of file stm32h7xx_hal_dma.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA Priority level

Defines
DMA Priority level
DMA Exported Constants

DMA priority levels. More...

Defines

#define | DMA_PRIORITY_LOW ((uint32_t)0x00000000U)
#define | DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0)
#define | DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1)
#define | DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL)

Detailed Description

DMA priority levels.

Define Documentation

#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1)

Priority level: High

Definition at line 479 of file stm32h7xx_hal_dma.h.

#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U)

Priority level: Low

Definition at line 477 of file stm32h7xx_hal_dma.h.

#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0)

Priority level: Medium

Definition at line 478 of file stm32h7xx_hal_dma.h.

#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL)

Priority level: Very High

Definition at line 480 of file stm32h7xx_hal_dma.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA FIFO direct mode

Defines
DMA FIFO direct mode
DMA Exported Constants

DMA FIFO direct mode. More...

Defines

#define | DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U)
#define | DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS)

Detailed Description

DMA FIFO direct mode.

Define Documentation

#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U)

FIFO mode disable

Definition at line 489 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS)

FIFO mode enable

Definition at line 490 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA FIFO threshold level

Defines
DMA FIFO threshold level
DMA Exported Constants

DMA FIFO level. More...

Defines

#define | DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U)
#define | DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0)
#define | DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1)
#define | DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH)

Detailed Description

DMA FIFO level.

Define Documentation

#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U)

FIFO threshold 1 quart full configuration

Definition at line 499 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CheckFifoParam().

#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1)

FIFO threshold 3 quarts full configuration

Definition at line 501 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CheckFifoParam().

#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH)

FIFO threshold full configuration

Definition at line 502 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CheckFifoParam().

#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0)

FIFO threshold half full configuration

Definition at line 500 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CheckFifoParam().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA Memory burst

Defines
DMA Memory burst
DMA Exported Constants

DMA memory burst. More...

Defines

#define | DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
#define | DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
#define | DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
#define | DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)

Detailed Description

DMA memory burst.

Define Documentation

#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)

Definition at line 514 of file stm32h7xx_hal_dma.h.

Referenced by DMA_CheckFifoParam().

#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)

Definition at line 512 of file stm32h7xx_hal_dma.h.

#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)

Definition at line 513 of file stm32h7xx_hal_dma.h.

#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)

Definition at line 511 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA Peripheral burst

Defines
DMA Peripheral burst
DMA Exported Constants

DMA peripheral burst. More...

Defines

#define | DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
#define | DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
#define | DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
#define | DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)

Detailed Description

DMA peripheral burst.

Define Documentation

#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)

Definition at line 526 of file stm32h7xx_hal_dma.h.

#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)

Definition at line 524 of file stm32h7xx_hal_dma.h.

#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)

Definition at line 525 of file stm32h7xx_hal_dma.h.

#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)

Definition at line 523 of file stm32h7xx_hal_dma.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA interrupt enable definitions

Defines
DMA interrupt enable definitions
DMA Exported Constants

DMA interrupts definition. More...

Defines

#define | DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
#define | DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
#define | DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
#define | DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
#define | DMA_IT_FE ((uint32_t)0x00000080U)

Detailed Description

DMA interrupts definition.

Define Documentation

#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)

Definition at line 538 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_IRQHandler(), HAL_DMA_Start_IT(), and HAL_DMAEx_MultiBufferStart_IT().

#define DMA_IT_FE ((uint32_t)0x00000080U)

Definition at line 539 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_IRQHandler(), HAL_DMA_Start_IT(), and HAL_DMAEx_MultiBufferStart_IT().

#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)

Definition at line 536 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_IRQHandler(), HAL_DMA_Start_IT(), and HAL_DMAEx_MultiBufferStart_IT().

#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)

Definition at line 535 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_IRQHandler(), HAL_DMA_Start_IT(), and HAL_DMAEx_MultiBufferStart_IT().

#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)

Definition at line 537 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_IRQHandler(), HAL_DMA_Start_IT(), and HAL_DMAEx_MultiBufferStart_IT().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA flag definitions

Defines
DMA flag definitions
DMA Exported Constants

DMA flag definitions. More...

Defines

#define | DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U)
#define | DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U)
#define | DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
#define | DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
#define | DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
#define | DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
#define | DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
#define | DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
#define | DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
#define | DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
#define | DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
#define | DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
#define | DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
#define | DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
#define | DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
#define | DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
#define | DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
#define | DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
#define | DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
#define | DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)

Detailed Description

DMA flag definitions.

Define Documentation

#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U)

Definition at line 549 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)

Definition at line 554 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)

Definition at line 559 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)

Definition at line 564 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U)

Definition at line 548 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)

Definition at line 553 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)

Definition at line 558 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)

Definition at line 563 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)

Definition at line 551 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)

Definition at line 556 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)

Definition at line 561 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)

Definition at line 566 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)

Definition at line 552 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)

Definition at line 557 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)

Definition at line 562 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)

Definition at line 567 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)

Definition at line 550 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)

Definition at line 555 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)

Definition at line 560 of file stm32h7xx_hal_dma.h.

#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)

Definition at line 565 of file stm32h7xx_hal_dma.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: BDMA flag definitions

Defines
BDMA flag definitions
DMA Exported Constants

BDMA flag definitions. More...

Defines

#define | BDMA_FLAG_GL0 ((uint32_t)0x00000001)
#define | BDMA_FLAG_TC0 ((uint32_t)0x00000002)
#define | BDMA_FLAG_HT0 ((uint32_t)0x00000004)
#define | BDMA_FLAG_TE0 ((uint32_t)0x00000008)
#define | BDMA_FLAG_GL1 ((uint32_t)0x00000010)
#define | BDMA_FLAG_TC1 ((uint32_t)0x00000020)
#define | BDMA_FLAG_HT1 ((uint32_t)0x00000040)
#define | BDMA_FLAG_TE1 ((uint32_t)0x00000080)
#define | BDMA_FLAG_GL2 ((uint32_t)0x00000100)
#define | BDMA_FLAG_TC2 ((uint32_t)0x00000200)
#define | BDMA_FLAG_HT2 ((uint32_t)0x00000400)
#define | BDMA_FLAG_TE2 ((uint32_t)0x00000800)
#define | BDMA_FLAG_GL3 ((uint32_t)0x00001000)
#define | BDMA_FLAG_TC3 ((uint32_t)0x00002000)
#define | BDMA_FLAG_HT3 ((uint32_t)0x00004000)
#define | BDMA_FLAG_TE3 ((uint32_t)0x00008000)
#define | BDMA_FLAG_GL4 ((uint32_t)0x00010000)
#define | BDMA_FLAG_TC4 ((uint32_t)0x00020000)
#define | BDMA_FLAG_HT4 ((uint32_t)0x00040000)
#define | BDMA_FLAG_TE4 ((uint32_t)0x00080000)
#define | BDMA_FLAG_GL5 ((uint32_t)0x00100000)
#define | BDMA_FLAG_TC5 ((uint32_t)0x00200000)
#define | BDMA_FLAG_HT5 ((uint32_t)0x00400000)
#define | BDMA_FLAG_TE5 ((uint32_t)0x00800000)
#define | BDMA_FLAG_GL6 ((uint32_t)0x01000000)
#define | BDMA_FLAG_TC6 ((uint32_t)0x02000000)
#define | BDMA_FLAG_HT6 ((uint32_t)0x04000000)
#define | BDMA_FLAG_TE6 ((uint32_t)0x08000000)
#define | BDMA_FLAG_GL7 ((uint32_t)0x10000000)
#define | BDMA_FLAG_TC7 ((uint32_t)0x20000000)
#define | BDMA_FLAG_HT7 ((uint32_t)0x40000000)
#define | BDMA_FLAG_TE7 ((uint32_t)0x80000000)

Detailed Description

BDMA flag definitions.

Define Documentation

#define BDMA_FLAG_GL0 ((uint32_t)0x00000001)

Definition at line 576 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_GL1 ((uint32_t)0x00000010)

Definition at line 580 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_GL2 ((uint32_t)0x00000100)

Definition at line 584 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_GL3 ((uint32_t)0x00001000)

Definition at line 588 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_GL4 ((uint32_t)0x00010000)

Definition at line 592 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_GL5 ((uint32_t)0x00100000)

Definition at line 596 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_GL6 ((uint32_t)0x01000000)

Definition at line 600 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_GL7 ((uint32_t)0x10000000)

Definition at line 604 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_HT0 ((uint32_t)0x00000004)

Definition at line 578 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define BDMA_FLAG_HT1 ((uint32_t)0x00000040)

Definition at line 582 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_HT2 ((uint32_t)0x00000400)

Definition at line 586 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_HT3 ((uint32_t)0x00004000)

Definition at line 590 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_HT4 ((uint32_t)0x00040000)

Definition at line 594 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_HT5 ((uint32_t)0x00400000)

Definition at line 598 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_HT6 ((uint32_t)0x04000000)

Definition at line 602 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_HT7 ((uint32_t)0x40000000)

Definition at line 606 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TC0 ((uint32_t)0x00000002)

Definition at line 577 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define BDMA_FLAG_TC1 ((uint32_t)0x00000020)

Definition at line 581 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TC2 ((uint32_t)0x00000200)

Definition at line 585 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TC3 ((uint32_t)0x00002000)

Definition at line 589 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TC4 ((uint32_t)0x00020000)

Definition at line 593 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TC5 ((uint32_t)0x00200000)

Definition at line 597 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TC6 ((uint32_t)0x02000000)

Definition at line 601 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TC7 ((uint32_t)0x20000000)

Definition at line 605 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TE0 ((uint32_t)0x00000008)

Definition at line 579 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define BDMA_FLAG_TE1 ((uint32_t)0x00000080)

Definition at line 583 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TE2 ((uint32_t)0x00000800)

Definition at line 587 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TE3 ((uint32_t)0x00008000)

Definition at line 591 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TE4 ((uint32_t)0x00080000)

Definition at line 595 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TE5 ((uint32_t)0x00800000)

Definition at line 599 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TE6 ((uint32_t)0x08000000)

Definition at line 603 of file stm32h7xx_hal_dma.h.

#define BDMA_FLAG_TE7 ((uint32_t)0x80000000)

Definition at line 607 of file stm32h7xx_hal_dma.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA Exported Macros

Defines
DMA Exported Macros
DMA

Defines

#define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Reset DMA handle state.
#define | __HAL_DMA_GET_FS(__HANDLE__) ((IS_D2_DMA_INSTANCE(__HANDLE__))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0)
Return the current DMA Stream FIFO filled level.
#define | __HAL_DMA_ENABLE(__HANDLE__)
Enable the specified DMA Stream.
#define | __HAL_DMA_DISABLE(__HANDLE__)
Disable the specified DMA Stream.
#define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream transfer complete flag.
#define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream half transfer complete flag.
#define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream transfer error flag.
#define | __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream FIFO error flag.
#define | __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream direct mode error flag.
#define | __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)
Returns the current BDMA Channel Global interrupt flag.
#define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)
Get the DMA Stream pending flags.
#define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the DMA Stream pending flags.
#define | D2_TO_D3_DMA_IT(__DMA_IT__)
#define | __HAL_DMA_D3_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (D2_TO_D3_DMA_IT(__INTERRUPT__)))
#define | __HAL_DMA_D2_ENABLE_IT(__HANDLE__, __INTERRUPT__)
#define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified DMA Stream interrupts.
#define | __HAL_DMA_D3_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(D2_TO_D3_DMA_IT(__INTERRUPT__)))
#define | __HAL_DMA_D2_DISABLE_IT(__HANDLE__, __INTERRUPT__)
#define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified DMA Stream interrupts.
#define | __HAL_DMA_D3_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (D2_TO_D3_DMA_IT(__INTERRUPT__))))
#define | __HAL_DMA_D2_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
#define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified DMA Stream interrupt is enabled or not.
#define | __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__)
Writes the number of data units to be transferred on the DMA Stream.
#define | __HAL_DMA_GET_COUNTER(__HANDLE__)
Returns the number of remaining data units in the current DMAy Streamx transfer.

Define Documentation

#define __HAL_BDMA_GET_GI_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_ISR_GIF2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_ISR_GIF3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_ISR_GIF4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_ISR_GIF5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\
  (uint32_t)0x00000000)

Returns the current BDMA Channel Global interrupt flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified transfer error flag index.

Definition at line 811 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__))  :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))

Clear the DMA Stream pending flags.

Parameters:
__HANDLE__,: DMA handle
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • DMA_FLAG_TCIFx: Transfer complete flag.
  • DMA_FLAG_HTIFx: Half transfer complete flag.
  • DMA_FLAG_TEIFx: Transfer error flag.
  • DMA_FLAG_DMEIFx: Direct mode error flag.
  • DMA_FLAG_FEIFx: FIFO error flag. Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
Return values:
None

Definition at line 854 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_D2_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__INTERRUPT__) != DMA_IT_FE)? \
(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__)))

Definition at line 897 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_D2_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__INTERRUPT__) != DMA_IT_FE)? \
(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__)))

Definition at line 875 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_D2_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__INTERRUPT__) != DMA_IT_FE)? \
                                                        (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \
                                                        (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__)))

Definition at line 919 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_D3_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(D2_TO_D3_DMA_IT(__INTERRUPT__)))

Definition at line 895 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_D3_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (D2_TO_D3_DMA_IT(__INTERRUPT__)))

Definition at line 872 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_D3_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (D2_TO_D3_DMA_IT(__INTERRUPT__))))

Definition at line 917 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_DISABLE ( __HANDLE__ )
Value:
((IS_D2_DMA_INSTANCE(__HANDLE__))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &=  ~DMA_SxCR_EN) : \
(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &=  ~BDMA_CCR_EN))

Disable the specified DMA Stream.

Parameters:
__HANDLE__,: DMA handle
Return values:
None

Definition at line 656 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_I2S_DMAStop(), and HAL_SPDIFRX_DMAStop().

#define __HAL_DMA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((IS_D2_DMA_INSTANCE(__HANDLE__))?\
                                                         (__HAL_DMA_D2_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
                                                         (__HAL_DMA_D3_DISABLE_IT((__HANDLE__), (__INTERRUPT__))))

Disable the specified DMA Stream interrupts.

Parameters:
__HANDLE__,: DMA handle
__INTERRUPT__,: specifies the DMA interrupt sources to be enabled or disabled. This parameter can be one of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask.
  • DMA_IT_HT: Half transfer complete interrupt mask.
  • DMA_IT_TE: Transfer error interrupt mask.
  • DMA_IT_FE: FIFO error interrupt mask.
  • DMA_IT_DME: Direct mode error interrupt.
Return values:
None

Definition at line 912 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_ENABLE ( __HANDLE__ )
Value:
((IS_D2_DMA_INSTANCE(__HANDLE__))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |=  DMA_SxCR_EN) : \
(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |=  BDMA_CCR_EN))

Enable the specified DMA Stream.

Parameters:
__HANDLE__,: DMA handle
Return values:
None

Definition at line 647 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

#define __HAL_DMA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((IS_D2_DMA_INSTANCE(__HANDLE__))?\
                                                        (__HAL_DMA_D2_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
                                                        (__HAL_DMA_D3_ENABLE_IT((__HANDLE__), (__INTERRUPT__))))

Enable the specified DMA Stream interrupts.

Parameters:
__HANDLE__,: DMA handle
__INTERRUPT__,: specifies the DMA interrupt sources to be enabled or disabled. This parameter can be one of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask.
  • DMA_IT_HT: Half transfer complete interrupt mask.
  • DMA_IT_TE: Transfer error interrupt mask.
  • DMA_IT_FE: FIFO error interrupt mask.
  • DMA_IT_DME: Direct mode error interrupt.
Return values:
None

Definition at line 890 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_GET_COUNTER ( __HANDLE__ )
Value:
((IS_D2_DMA_INSTANCE(__HANDLE__))?\
                                           (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) :\
                                           (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR))

Returns the number of remaining data units in the current DMAy Streamx transfer.

Parameters:
__HANDLE__,: DMA handle
Return values:
The number of remaining data units in the current DMA Stream transfer.

Definition at line 966 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_GET_DME_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\
  (uint32_t)0x00000000)

Return the current DMA Stream direct mode error flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified direct mode error flag index.

Definition at line 787 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_GET_FE_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\
  (uint32_t)0x00000000)

Return the current DMA Stream FIFO error flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified FIFO error flag index.

Definition at line 763 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__))  :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))

Get the DMA Stream pending flags.

Parameters:
__HANDLE__,: DMA handle
__FLAG__,: Get the specified flag. This parameter can be any combination of the following values:
  • DMA_FLAG_TCIFx: Transfer complete flag.
  • DMA_FLAG_HTIFx: Half transfer complete flag.
  • DMA_FLAG_TEIFx: Transfer error flag.
  • DMA_FLAG_DMEIFx: Direct mode error flag.
  • DMA_FLAG_FEIFx: FIFO error flag. Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
Return values:
The state of FLAG (SET or RESET).

Definition at line 835 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_GET_FS ( __HANDLE__ ) ((IS_D2_DMA_INSTANCE(__HANDLE__))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0)

Return the current DMA Stream FIFO filled level.

Parameters:
__HANDLE__,: DMA handle
Return values:
The FIFO filling state.
  • DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full and not empty.
  • DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
  • DMA_FIFOStatus_HalfFull: if more than 1 half-full.
  • DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
  • DMA_FIFOStatus_Empty: when FIFO is empty
  • DMA_FIFOStatus_Full: when FIFO is full

Definition at line 640 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_GET_HT_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_HT0    :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_HT1    :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_HT2    :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_HT3    :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_HT4    :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_HT5    :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6    :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7    :\
 (uint32_t)0x00000000)

Return the current DMA Stream half transfer complete flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified half transfer complete flag index.

Definition at line 699 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((IS_D2_DMA_INSTANCE(__HANDLE__))? \
                                                            (__HAL_DMA_D2_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\
                                                            (__HAL_DMA_D3_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))))

Check whether the specified DMA Stream interrupt is enabled or not.

Parameters:
__HANDLE__,: DMA handle
__INTERRUPT__,: specifies the DMA interrupt source to check. This parameter can be one of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask.
  • DMA_IT_HT: Half transfer complete interrupt mask.
  • DMA_IT_TE: Transfer error interrupt mask.
  • DMA_IT_FE: FIFO error interrupt mask.
  • DMA_IT_DME: Direct mode error interrupt.
Return values:
The state of DMA_IT.

Definition at line 935 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler().

#define __HAL_DMA_GET_TC_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TC0    :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TC1    :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TC2    :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TC3    :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TC4    :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TC5    :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6    :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7    :\
 (uint32_t)0x00000000)

Return the current DMA Stream transfer complete flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified transfer complete flag index.

Definition at line 667 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_GET_TE_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TE0    :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TE1    :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TE2    :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TE3    :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TE4    :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TE5    :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6    :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7    :\
 (uint32_t)0x00000000)

Return the current DMA Stream transfer error flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified transfer error flag index.

Definition at line 731 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)

Reset DMA handle state.

Parameters:
__HANDLE__,: specifies the DMA handle.
Return values:
None

Definition at line 626 of file stm32h7xx_hal_dma.h.

#define __HAL_DMA_SET_COUNTER | ( | __HANDLE__,
 |  | __COUNTER__
 | ) |
Value:
((IS_D2_DMA_INSTANCE(__HANDLE__))? \
                                                        (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) :\
                                                        (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__)))

Writes the number of data units to be transferred on the DMA Stream.

Parameters:
__HANDLE__,: DMA handle
__COUNTER__,: Number of data units to be transferred (from 0 to 65535) Number of data items depends only on the Peripheral data format.
Note:
If Peripheral data format is Bytes: number of data units is equal to total number of bytes to be transferred.
If Peripheral data format is Half-Word: number of data units is equal to total number of bytes to be transferred / 2.
If Peripheral data format is Word: number of data units is equal to total number of bytes to be transferred / 4.
Return values:
The number of remaining data units in the current DMAy Streamx transfer.

Definition at line 956 of file stm32h7xx_hal_dma.h.

#define D2_TO_D3_DMA_IT ( __DMA_IT__ )
Value:
((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
(((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) :\
(((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE)  :\
(((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE)  :\
((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE :\
((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE :\
((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE :\
(uint32_t)0x00000000)

Definition at line 861 of file stm32h7xx_hal_dma.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DMA Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitializes the DMA peripheral.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
             ##### Initialization and de-initialization functions  #####
 ===============================================================================
    [..]
    This section provides functions allowing to initialize the DMA Stream source
    and destination incrementation and data sizes, transfer direction,
    circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
    [..]
    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
    reference manual.
    The HAL_DMA_DeInit function allows to deinitialize the DMA stream.

Function Documentation

HAL_StatusTypeDef HAL_DMA_DeInit ( DMA_HandleTypeDef * hdma )

DeInitializes the DMA peripheral.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 440 of file stm32h7xx_hal_dma.c.

References __HAL_DMA_DISABLE, DMA_CalcBaseAndBitshift(), __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_RESET, DMA_Base_Registers::IFCR, __DMA_HandleTypeDef::Instance, IS_D2_DMA_INSTANCE, IS_D3_DMA_INSTANCE, __DMA_HandleTypeDef::State, and __DMA_HandleTypeDef::StreamIndex.

HAL_StatusTypeDef HAL_DMA_Init ( DMA_HandleTypeDef * hdma )

Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and create the associated handle.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 211 of file stm32h7xx_hal_dma.c.

References __HAL_DMA_DISABLE, assert_param, BDMA_REQUEST_GENERATOR0, BDMA_REQUEST_GENERATOR7, D2_TO_D3_DMA_DIRECTION, D2_TO_D3_DMA_MDATA_SIZE, D2_TO_D3_DMA_MEMORY_INC, D2_TO_D3_DMA_MODE, D2_TO_D3_DMA_PDATA_SIZE, D2_TO_D3_DMA_PERIPHERAL_INC, D2_TO_D3_DMA_PRIORITY, DMA_InitTypeDef::Direction, DMA_CalcBaseAndBitshift(), DMA_CalcDMAMUXChannelBaseAndMask(), DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_CheckFifoParam(), DMA_FIFOMODE_DISABLE, DMA_FIFOMODE_ENABLE, DMA_MBURST_SINGLE, DMA_MEMORY_TO_MEMORY, DMA_REQUEST_GENERATOR0, DMA_REQUEST_GENERATOR7, DMA_REQUEST_MEM2MEM, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, DMA_InitTypeDef::FIFOMode, DMA_InitTypeDef::FIFOThreshold, HAL_DMA_ERROR_NONE, HAL_DMA_ERROR_PARAM, HAL_DMA_ERROR_TIMEOUT, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_ERROR, HAL_DMA_STATE_READY, HAL_GetTick(), HAL_TIMEOUT_DMA_ABORT, DMA_Base_Registers::IFCR, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, IS_BDMA_D3_REQUEST, IS_D2_DMA_INSTANCE, IS_D3_DMA_INSTANCE, IS_DMA_D2_REQUEST, IS_DMA_DIRECTION, IS_DMA_FIFO_MODE_STATE, IS_DMA_FIFO_THRESHOLD, IS_DMA_MEMORY_BURST, IS_DMA_MEMORY_DATA_SIZE, IS_DMA_MEMORY_INC_STATE, IS_DMA_MODE, IS_DMA_PERIPHERAL_BURST, IS_DMA_PERIPHERAL_DATA_SIZE, IS_DMA_PERIPHERAL_INC_STATE, IS_DMA_PRIORITY, DMA_InitTypeDef::MemBurst, DMA_InitTypeDef::MemDataAlignment, DMA_InitTypeDef::MemInc, DMA_InitTypeDef::Mode, DMA_InitTypeDef::PeriphBurst, DMA_InitTypeDef::PeriphDataAlignment, DMA_InitTypeDef::PeriphInc, DMA_InitTypeDef::Priority, DMA_InitTypeDef::Request, __DMA_HandleTypeDef::State, and __DMA_HandleTypeDef::StreamIndex.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I/O operation functions

Functions
I/O operation functions
DMA Exported Functions

I/O operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Starts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.

Detailed Description

I/O operation functions.

 ===============================================================================
                      #####  IO operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the source, destination address and data length and Start DMA transfer
      (+) Configure the source, destination address and data length and
          Start DMA transfer with interrupt
      (+) Register and Unregister DMA callbacks
      (+) Abort DMA transfer
      (+) Poll for transfer complete
      (+) Handle DMA interrupt request

Function Documentation

HAL_StatusTypeDef HAL_DMA_Abort ( DMA_HandleTypeDef * hdma )

Aborts the DMA Transfer.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Note:
After disabling a DMA Stream, a check for wait until the DMA Stream is effectively disabled is added. If a Stream is disabled while a data transfer is ongoing, the current data will be transferred and the Stream will be effectively disabled only after the transfer of this single data is finished.
Return values:
HAL status

Definition at line 721 of file stm32h7xx_hal_dma.c.

References __HAL_DMA_DISABLE, DMA_IT_DME, DMA_IT_FE, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NO_XFER, HAL_DMA_ERROR_TIMEOUT, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_ERROR, HAL_DMA_STATE_READY, HAL_GetTick(), HAL_TIMEOUT_DMA_ABORT, DMA_Base_Registers::IFCR, __DMA_HandleTypeDef::Instance, IS_D2_DMA_INSTANCE, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::StreamBaseAddress, and __DMA_HandleTypeDef::StreamIndex.

Referenced by HAL_ADC_Stop_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop_DMA(), HAL_DAC_Stop_DMA(), HAL_DCMI_Stop(), HAL_DFSDM_FilterInjectedStop_DMA(), HAL_DFSDM_FilterRegularStop_DMA(), HAL_DMA_PollForTransfer(), HAL_HASH_DMAFeed_ProcessSuspend(), HAL_HRTIM_SimpleBaseStop_DMA(), HAL_HRTIM_SimpleCaptureStop_DMA(), HAL_HRTIM_SimpleOCStop_DMA(), HAL_HRTIM_SimplePWMStop_DMA(), HAL_HRTIM_WaveformCounterStop_DMA(), HAL_I2S_DMAStop(), HAL_IRDA_Abort(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DMAStop(), HAL_SAI_Abort(), HAL_SAI_DMAStop(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_SPI_Abort(), HAL_SPI_DMAStop(), HAL_SWPMI_DMAStop(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_UART_Abort(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DMAStop(), HAL_USART_Abort(), and HAL_USART_DMAStop().

HAL_StatusTypeDef HAL_DMA_Abort_IT ( DMA_HandleTypeDef * hdma )

Aborts the DMA Transfer in Interrupt mode.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 828 of file stm32h7xx_hal_dma.c.

References __HAL_DMA_DISABLE, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NO_XFER, HAL_DMA_STATE_ABORT, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, IS_D2_DMA_INSTANCE, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::StreamIndex, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_DCMI_IRQHandler(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_IRQHandler(), HAL_SAI_IRQHandler(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SWPMI_IRQHandler(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit_IT(), HAL_UART_IRQHandler(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), and I2C_ITError().

void HAL_DMA_IRQHandler ( DMA_HandleTypeDef * hdma )

Handles DMA interrupt request.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
None

Definition at line 1145 of file stm32h7xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_GET_IT_SOURCE, BDMA_FLAG_HT0, BDMA_FLAG_TC0, BDMA_FLAG_TE0, DMA_FLAG_DMEIF0_4, DMA_FLAG_FEIF0_4, DMA_FLAG_HTIF0_4, DMA_FLAG_TCIF0_4, DMA_FLAG_TEIF0_4, DMA_IT_DME, DMA_IT_FE, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_DME, HAL_DMA_ERROR_FE, HAL_DMA_ERROR_NONE, HAL_DMA_ERROR_TE, HAL_DMA_STATE_ABORT, HAL_DMA_STATE_ERROR, HAL_DMA_STATE_READY, DMA_Base_Registers::IFCR, __DMA_HandleTypeDef::Instance, IS_D2_DMA_INSTANCE, IS_D3_DMA_INSTANCE, DMA_Base_Registers::ISR, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::StreamBaseAddress, __DMA_HandleTypeDef::StreamIndex, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __DMA_HandleTypeDef::XferM1CpltCallback, and __DMA_HandleTypeDef::XferM1HalfCpltCallback.

HAL_StatusTypeDef HAL_DMA_PollForTransfer | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_LevelCompleteTypeDef | CompleteLevel,
 |  | uint32_t | Timeout
 | ) |  |

Polling for transfer complete.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
CompleteLevel,: Specifies the DMA level complete.
Note:
The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead. This model could be used for debug purpose.
The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
Parameters:
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 906 of file stm32h7xx_hal_dma.c.

References BDMA_FLAG_HT0, BDMA_FLAG_TC0, BDMA_FLAG_TE0, DMA_FLAG_DMEIF0_4, DMA_FLAG_FEIF0_4, DMA_FLAG_HTIF0_4, DMA_FLAG_TCIF0_4, DMA_FLAG_TEIF0_4, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_ERROR_DME, HAL_DMA_ERROR_FE, HAL_DMA_ERROR_NO_XFER, HAL_DMA_ERROR_NONE, HAL_DMA_ERROR_NOT_SUPPORTED, HAL_DMA_ERROR_REQGEN, HAL_DMA_ERROR_SYNC, HAL_DMA_ERROR_TE, HAL_DMA_ERROR_TIMEOUT, HAL_DMA_FULL_TRANSFER, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, HAL_GetTick(), __DMA_HandleTypeDef::Instance, IS_D2_DMA_INSTANCE, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::StreamBaseAddress, and __DMA_HandleTypeDef::StreamIndex.

HAL_StatusTypeDef HAL_DMA_RegisterCallback | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_CallbackIDTypeDef | CallbackID,
 |  | void(*)(DMA_HandleTypeDef *_hdma) | pCallback
 | ) |  |

Register callbacks.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
CallbackID,: User Callback identifer a DMA_HandleTypeDef structure as parameter.
pCallback,: pointer to private callbacsk function which has pointer to a DMA_HandleTypeDef structure as parameter.
Return values:
HAL status

Definition at line 1455 of file stm32h7xx_hal_dma.c.

References HAL_DMA_STATE_READY, HAL_DMA_XFER_ABORT_CB_ID, HAL_DMA_XFER_CPLT_CB_ID, HAL_DMA_XFER_ERROR_CB_ID, HAL_DMA_XFER_HALFCPLT_CB_ID, HAL_DMA_XFER_M1CPLT_CB_ID, HAL_DMA_XFER_M1HALFCPLT_CB_ID, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __DMA_HandleTypeDef::XferM1CpltCallback, and __DMA_HandleTypeDef::XferM1HalfCpltCallback.

HAL_StatusTypeDef HAL_DMA_Start | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  |

Starts the DMA Transfer.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 572 of file stm32h7xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_ENABLE, assert_param, DMA_SetConfig(), __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, IS_DMA_BUFFER_SIZE, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA_Start_IT | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  |

Start the DMA Transfer with interrupt enabled.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 625 of file stm32h7xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_ENABLE, assert_param, DMA_IT_DME, DMA_IT_FE, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, DMA_SetConfig(), __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, IS_D2_DMA_INSTANCE, IS_DMA_BUFFER_SIZE, __DMA_HandleTypeDef::State, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by CRYP_SetDMAConfig(), HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DAC_Start_DMA(), HAL_DCMI_Start_DMA(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_HRTIM_BurstDMATransfer(), HAL_HRTIM_SimpleBaseStart_DMA(), HAL_HRTIM_SimpleCaptureStart_DMA(), HAL_HRTIM_SimpleOCStart_DMA(), HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_WaveformCounterStart_DMA(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_I2SEx_TransmitReceive_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Transmit_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), HASH_DMAXferCplt(), HASH_Start_DMA(), HMAC_Start_DMA(), I2C_DMAMasterReceiveCplt(), and I2C_DMAMasterTransmitCplt().

HAL_StatusTypeDef HAL_DMA_UnRegisterCallback | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_CallbackIDTypeDef | CallbackID
 | ) |  |

UnRegister callbacks.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
CallbackID,: User Callback identifer a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
Return values:
HAL status

Definition at line 1521 of file stm32h7xx_hal_dma.c.

References HAL_DMA_STATE_READY, HAL_DMA_XFER_ABORT_CB_ID, HAL_DMA_XFER_ALL_CB_ID, HAL_DMA_XFER_CPLT_CB_ID, HAL_DMA_XFER_ERROR_CB_ID, HAL_DMA_XFER_HALFCPLT_CB_ID, HAL_DMA_XFER_M1CPLT_CB_ID, HAL_DMA_XFER_M1HALFCPLT_CB_ID, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __DMA_HandleTypeDef::XferM1CpltCallback, and __DMA_HandleTypeDef::XferM1HalfCpltCallback.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
DMA Exported Functions

Peripheral State functions. More...

Functions

HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Returns the DMA state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                    ##### State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DMA state
      (+) Get error code

Function Documentation

uint32_t HAL_DMA_GetError ( DMA_HandleTypeDef * hdma )

Return the DMA error code.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
DMA Error Code

Definition at line 1623 of file stm32h7xx_hal_dma.c.

References __DMA_HandleTypeDef::ErrorCode.

Referenced by SAI_DMAError(), and UART_DMAError().

HAL_DMA_StateTypeDef HAL_DMA_GetState ( DMA_HandleTypeDef * hdma )

Returns the DMA state.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL state

Definition at line 1612 of file stm32h7xx_hal_dma.c.

References __DMA_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA Private Constants

Defines
DMA Private Constants
DMA

DMA private defines and constants. More...

Defines

#define | HAL_TIMEOUT_DMA_ABORT (5U) /* 5 ms */
#define | BDMA_PERIPH_TO_MEMORY (0x00000000U)
#define | BDMA_MEMORY_TO_PERIPH ((uint32_t)BDMA_CCR_DIR)
#define | BDMA_MEMORY_TO_MEMORY ((uint32_t)BDMA_CCR_MEM2MEM)
#define | D2_TO_D3_DMA_DIRECTION(__D2_DMA_DIRECTION__)
#define | D2_TO_D3_DMA_PERIPHERAL_INC(__D2_PERIPHERAL_INC__) ((__D2_PERIPHERAL_INC__) >> 3U)
#define | D2_TO_D3_DMA_MEMORY_INC(__D2_MEMORY_INC__) ((__D2_MEMORY_INC__) >> 3U)
#define | D2_TO_D3_DMA_PDATA_SIZE(__D2_PDATA_SIZE__) ((__D2_PDATA_SIZE__) >> 3U)
#define | D2_TO_D3_DMA_MDATA_SIZE(__D2_MDATA_SIZE__) ((__D2_MDATA_SIZE__) >> 3U)
#define | D2_TO_D3_DMA_MODE(__D2_MODE__) (((__D2_MODE__) >> 3U) & BDMA_CCR_CIRC)
#define | D2_TO_D3_DMA_PRIORITY(__D2_PRIORITY__) ((__D2_PRIORITY__) >> 4U)

Detailed Description

DMA private defines and constants.

Define Documentation

#define BDMA_MEMORY_TO_MEMORY ((uint32_t)BDMA_CCR_MEM2MEM)

Memory to memory direction

Definition at line 145 of file stm32h7xx_hal_dma.c.

#define BDMA_MEMORY_TO_PERIPH ((uint32_t)BDMA_CCR_DIR)

Memory to peripheral direction

Definition at line 144 of file stm32h7xx_hal_dma.c.

#define BDMA_PERIPH_TO_MEMORY (0x00000000U)

Peripheral to memory direction

Definition at line 143 of file stm32h7xx_hal_dma.c.

#define D2_TO_D3_DMA_DIRECTION ( __D2_DMA_DIRECTION__ )
Value:
(((__D2_DMA_DIRECTION__)== DMA_MEMORY_TO_PERIPH)? BDMA_MEMORY_TO_PERIPH: \
                                                      ((__D2_DMA_DIRECTION__)== DMA_MEMORY_TO_MEMORY)? BDMA_MEMORY_TO_MEMORY: \
                                                       BDMA_PERIPH_TO_MEMORY)

Definition at line 147 of file stm32h7xx_hal_dma.c.

Referenced by HAL_DMA_Init().

#define D2_TO_D3_DMA_MDATA_SIZE ( __D2_MDATA_SIZE__ ) ((__D2_MDATA_SIZE__) >> 3U)

Definition at line 155 of file stm32h7xx_hal_dma.c.

Referenced by HAL_DMA_Init().

#define D2_TO_D3_DMA_MEMORY_INC ( __D2_MEMORY_INC__ ) ((__D2_MEMORY_INC__) >> 3U)

Definition at line 152 of file stm32h7xx_hal_dma.c.

Referenced by HAL_DMA_Init().

#define D2_TO_D3_DMA_MODE ( __D2_MODE__ ) (((__D2_MODE__) >> 3U) & BDMA_CCR_CIRC)

Definition at line 158 of file stm32h7xx_hal_dma.c.

Referenced by HAL_DMA_Init().

#define D2_TO_D3_DMA_PDATA_SIZE ( __D2_PDATA_SIZE__ ) ((__D2_PDATA_SIZE__) >> 3U)

Definition at line 154 of file stm32h7xx_hal_dma.c.

Referenced by HAL_DMA_Init().

#define D2_TO_D3_DMA_PERIPHERAL_INC ( __D2_PERIPHERAL_INC__ ) ((__D2_PERIPHERAL_INC__) >> 3U)

Definition at line 151 of file stm32h7xx_hal_dma.c.

Referenced by HAL_DMA_Init().

#define D2_TO_D3_DMA_PRIORITY ( __D2_PRIORITY__ ) ((__D2_PRIORITY__) >> 4U)

Definition at line 160 of file stm32h7xx_hal_dma.c.

Referenced by HAL_DMA_Init().

#define HAL_TIMEOUT_DMA_ABORT (5U) /* 5 ms */

Definition at line 140 of file stm32h7xx_hal_dma.c.

Referenced by HAL_DMA_Abort(), and HAL_DMA_Init().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA Private Macros

Defines
DMA Private Macros
DMA

DMA private macros. More...

Defines

#define | IS_DMA_D2_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3))
#define | IS_BDMA_D3_REQUEST(REQUEST)
#define | IS_D2_DMA_INSTANCE(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) >= ((uint32_t)DMA1_Stream0)) && ((uint32_t)((__HANDLE__)->Instance) <= ((uint32_t)DMA2_Stream7)))
#define | IS_D3_DMA_INSTANCE(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) >= ((uint32_t)BDMA_Channel0)) && ((uint32_t)((__HANDLE__)->Instance) <= ((uint32_t)BDMA_Channel7)))
#define | IS_DMA_DIRECTION(DIRECTION)
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MODE(MODE)
#define | IS_DMA_PRIORITY(PRIORITY)
#define | IS_DMA_FIFO_MODE_STATE(STATE)
#define | IS_DMA_FIFO_THRESHOLD(THRESHOLD)
#define | IS_DMA_MEMORY_BURST(BURST)
#define | IS_DMA_PERIPHERAL_BURST(BURST)

Detailed Description

DMA private macros.

Define Documentation

#define IS_BDMA_D3_REQUEST ( REQUEST )
Value:
(((REQUEST) == BDMA_REQUEST_MEM2MEM) || \
                                    (((REQUEST) >= BDMA_REQUEST_GENERATOR0) &&  ((REQUEST) <= BDMA_REQUEST_ADC3)))

Definition at line 1040 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_D2_DMA_INSTANCE ( __HANDLE__ ) (((uint32_t)((__HANDLE__)->Instance) >= ((uint32_t)DMA1_Stream0)) && ((uint32_t)((__HANDLE__)->Instance) <= ((uint32_t)DMA2_Stream7)))

Definition at line 1043 of file stm32h7xx_hal_dma.h.

Referenced by DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_Start_IT(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_ConfigMuxSync(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

#define IS_D3_DMA_INSTANCE ( __HANDLE__ ) (((uint32_t)((__HANDLE__)->Instance) >= ((uint32_t)BDMA_Channel0)) && ((uint32_t)((__HANDLE__)->Instance) <= ((uint32_t)BDMA_Channel7)))

Definition at line 1044 of file stm32h7xx_hal_dma.h.

Referenced by DMA_SetConfig(), HAL_DMA_DeInit(), HAL_DMA_Init(), and HAL_DMA_IRQHandler().

#define IS_DMA_BUFFER_SIZE ( SIZE ) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))

Definition at line 1051 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

#define IS_DMA_D2_REQUEST ( REQUEST ) (((REQUEST) <= DMA_REQUEST_ADC3))

Definition at line 1038 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_DIRECTION ( DIRECTION )
Value:
(((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))

Definition at line 1047 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_FIFO_MODE_STATE ( STATE )
Value:
(((STATE) == DMA_FIFOMODE_DISABLE ) || \
                                       ((STATE) == DMA_FIFOMODE_ENABLE))

Definition at line 1076 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_FIFO_THRESHOLD ( THRESHOLD )
Value:
(((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))

Definition at line 1079 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_BURST ( BURST )
Value:
(((BURST) == DMA_MBURST_SINGLE) || \
                                    ((BURST) == DMA_MBURST_INC4)   || \
                                    ((BURST) == DMA_MBURST_INC8)   || \
                                    ((BURST) == DMA_MBURST_INC16))

Definition at line 1084 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_MDATAALIGN_BYTE)     || \
                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
                                       ((SIZE) == DMA_MDATAALIGN_WORD ))

Definition at line 1063 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_INC_STATE ( STATE )
Value:
(((STATE) == DMA_MINC_ENABLE)  || \
                                        ((STATE) == DMA_MINC_DISABLE))

Definition at line 1056 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MODE ( MODE )
Value:
(((MODE) == DMA_NORMAL )  || \
                           ((MODE) == DMA_CIRCULAR) || \
                           ((MODE) == DMA_PFCTRL))

Definition at line 1067 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_BURST ( BURST )
Value:
(((BURST) == DMA_PBURST_SINGLE) || \
                                        ((BURST) == DMA_PBURST_INC4)   || \
                                        ((BURST) == DMA_PBURST_INC8)   || \
                                        ((BURST) == DMA_PBURST_INC16))

Definition at line 1089 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_PDATAALIGN_BYTE)     || \
                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
                                           ((SIZE) == DMA_PDATAALIGN_WORD))

Definition at line 1059 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_INC_STATE ( STATE )
Value:
(((STATE) == DMA_PINC_ENABLE) || \
                                            ((STATE) == DMA_PINC_DISABLE))

Definition at line 1053 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PRIORITY ( PRIORITY )
Value:
(((PRIORITY) == DMA_PRIORITY_LOW )   || \
                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))

Definition at line 1071 of file stm32h7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA Private Functions

Functions
DMA Private Functions
DMA

DMA private functions. More...

Functions

static void | DMA_SetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Sets the DMA Transfer parameter.
static uint32_t | DMA_CalcBaseAndBitshift (DMA_HandleTypeDef *hdma)
Returns the DMA Stream base address depending on stream number.
static HAL_StatusTypeDef | DMA_CheckFifoParam (DMA_HandleTypeDef *hdma)
Check compatibility between FIFO threshold level and size of the memory burst.
static void | DMA_CalcDMAMUXChannelBaseAndMask (DMA_HandleTypeDef *hdma)
Updates the DMA handle with the DMAMUX channel and status mask depending on stream number.
static void | DMA_CalcDMAMUXRequestGenBaseAndMask (DMA_HandleTypeDef *hdma)
Updates the DMA handle with the DMAMUX request generator params.

Detailed Description

DMA private functions.

Function Documentation

static uint32_t DMA_CalcBaseAndBitshift ( DMA_HandleTypeDef * hdma ) [static]

Returns the DMA Stream base address depending on stream number.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
Stream base address

Definition at line 1728 of file stm32h7xx_hal_dma.c.

References __DMA_HandleTypeDef::Instance, __DMA_HandleTypeDef::StreamBaseAddress, and __DMA_HandleTypeDef::StreamIndex.

Referenced by HAL_DMA_DeInit(), and HAL_DMA_Init().

static void DMA_CalcDMAMUXChannelBaseAndMask ( DMA_HandleTypeDef * hdma ) [static]

Updates the DMA handle with the DMAMUX channel and status mask depending on stream number.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 1850 of file stm32h7xx_hal_dma.c.

References __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, and __DMA_HandleTypeDef::Instance.

Referenced by HAL_DMA_Init().

static void DMA_CalcDMAMUXRequestGenBaseAndMask ( DMA_HandleTypeDef * hdma ) [static]

Updates the DMA handle with the DMAMUX request generator params.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 1886 of file stm32h7xx_hal_dma.c.

References DMA_REQUEST_GENERATOR0, DMA_REQUEST_GENERATOR7, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, and DMA_InitTypeDef::Request.

Referenced by HAL_DMA_Init().

static HAL_StatusTypeDef DMA_CheckFifoParam ( DMA_HandleTypeDef * hdma ) [static]

Check compatibility between FIFO threshold level and size of the memory burst.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 1756 of file stm32h7xx_hal_dma.c.

References DMA_FIFO_THRESHOLD_1QUARTERFULL, DMA_FIFO_THRESHOLD_3QUARTERSFULL, DMA_FIFO_THRESHOLD_FULL, DMA_FIFO_THRESHOLD_HALFFULL, DMA_MBURST_INC16, DMA_MDATAALIGN_BYTE, DMA_MDATAALIGN_HALFWORD, DMA_InitTypeDef::FIFOThreshold, __DMA_HandleTypeDef::Init, DMA_InitTypeDef::MemBurst, and DMA_InitTypeDef::MemDataAlignment.

Referenced by HAL_DMA_Init().

static void DMA_SetConfig | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  | [static]

Sets the DMA Transfer parameter.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 1649 of file stm32h7xx_hal_dma.c.

References DMA_InitTypeDef::Direction, DMA_MEMORY_TO_PERIPH, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, DMA_Base_Registers::IFCR, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, IS_D2_DMA_INSTANCE, IS_D3_DMA_INSTANCE, __DMA_HandleTypeDef::StreamBaseAddress, and __DMA_HandleTypeDef::StreamIndex.

Referenced by HAL_DMA_Start(), and HAL_DMA_Start_IT().

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STM32H753xx HAL User Manual: DMA_Base_Registers Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA_Base_Registers Struct Reference
DMA

Data Fields

__IO uint32_t | ISR
__IO uint32_t | Reserved0
__IO uint32_t | IFCR

Detailed Description

Definition at line 128 of file stm32h7xx_hal_dma.c.

Field Documentation

__IO uint32_t DMA_Base_Registers::IFCR

DMA interrupt flag clear register

Definition at line 132 of file stm32h7xx_hal_dma.c.

Referenced by DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_DeInit(), HAL_DMA_Init(), and HAL_DMA_IRQHandler().

__IO uint32_t DMA_Base_Registers::ISR

DMA interrupt status register

Definition at line 130 of file stm32h7xx_hal_dma.c.

Referenced by HAL_DMA_IRQHandler().

__IO uint32_t DMA_Base_Registers::Reserved0

Definition at line 131 of file stm32h7xx_hal_dma.c.

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dma.c
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STM32H753xx HAL User Manual: DMA2D Time Out

Defines
DMA2D Time Out
DMA2D Private Constants

Defines

#define | DMA2D_TIMEOUT_ABORT ((uint32_t)1000)
#define | DMA2D_TIMEOUT_SUSPEND ((uint32_t)1000)

Define Documentation

#define DMA2D_TIMEOUT_ABORT ((uint32_t)1000)

1s

Definition at line 151 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_Abort(), and HAL_DMA2D_CLUTLoading_Abort().

#define DMA2D_TIMEOUT_SUSPEND ((uint32_t)1000)

1s

Definition at line 152 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_CLUTLoading_Suspend(), and HAL_DMA2D_Suspend().

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STM32H753xx HAL User Manual: DMA2D Shifts

Defines
DMA2D Shifts
DMA2D Private Constants

Defines

#define | DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS)
#define | DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS)
#define | DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM)
#define | DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM)
#define | DMA2D_POSITION_OPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_OPFCCR_AI)
#define | DMA2D_POSITION_FGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AI)
#define | DMA2D_POSITION_BGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AI)
#define | DMA2D_POSITION_OPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_OPFCCR_RBS)
#define | DMA2D_POSITION_FGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_RBS)
#define | DMA2D_POSITION_BGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_RBS)
#define | DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT)
#define | DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM)
#define | DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM)
#define | DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA)
#define | DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA)
#define | DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL)
#define | DMA2D_POSITION_FGPFCCR_CSS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CSS)

Define Documentation

#define DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT)

Required left shift to set deadtime value

Definition at line 174 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_ConfigDeadTime().

#define DMA2D_POSITION_BGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AI)

Required left shift to set background alpha inversion

Definition at line 168 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_ConfigLayer().

#define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA)

Required left shift to set background alpha value

Definition at line 180 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_ConfigLayer().

#define DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM)

Required left shift to set background alpha mode

Definition at line 177 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_ConfigLayer().

#define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM)

Required left shift to set background CLUT color mode

Definition at line 164 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_CLUTLoad(), HAL_DMA2D_CLUTLoad_IT(), and HAL_DMA2D_ConfigCLUT().

#define DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS)

Required left shift to set background CLUT size

Definition at line 161 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_CLUTLoad(), HAL_DMA2D_CLUTLoad_IT(), and HAL_DMA2D_ConfigCLUT().

#define DMA2D_POSITION_BGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_RBS)

Required left shift to set background Red/Blue swap

Definition at line 172 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_ConfigLayer().

#define DMA2D_POSITION_FGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AI)

Required left shift to set foreground alpha inversion

Definition at line 167 of file stm32h7xx_hal_dma2d.c.

#define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA)

Required left shift to set foreground alpha value

Definition at line 179 of file stm32h7xx_hal_dma2d.c.

#define DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM)

Required left shift to set foreground alpha mode

Definition at line 176 of file stm32h7xx_hal_dma2d.c.

#define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM)

Required left shift to set foreground CLUT color mode

Definition at line 163 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_CLUTLoad(), HAL_DMA2D_CLUTLoad_IT(), and HAL_DMA2D_ConfigCLUT().

#define DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS)

Required left shift to set foreground CLUT size

Definition at line 160 of file stm32h7xx_hal_dma2d.c.

#define DMA2D_POSITION_FGPFCCR_CSS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CSS)

Required left shift to set foreground Chroma sub-sampling

Definition at line 184 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_ConfigLayer().

#define DMA2D_POSITION_FGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_RBS)

Required left shift to set foreground Red/Blue swap

Definition at line 171 of file stm32h7xx_hal_dma2d.c.

#define DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL)

Required left shift to set pixels per lines value

Definition at line 182 of file stm32h7xx_hal_dma2d.c.

Referenced by DMA2D_SetConfig().

#define DMA2D_POSITION_OPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_OPFCCR_AI)

Required left shift to set output alpha inversion

Definition at line 166 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_Init().

#define DMA2D_POSITION_OPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_OPFCCR_RBS)

Required left shift to set output Red/Blue swap

Definition at line 170 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_Init().

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STM32H753xx HAL User Manual: DMA2D Maximum Line Watermark

Defines
DMA2D Maximum Line Watermark
DMA2D Private Constants

Defines

#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW

Define Documentation

#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW

DMA2D maximum line watermark

Definition at line 523 of file stm32h7xx_hal_dma2d.h.

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STM32H753xx HAL User Manual: DMA2D Color Value

Defines
DMA2D Color Value
DMA2D Private Constants

Defines

#define DMA2D_COLOR_VALUE ((uint32_t)0x000000FFU)

Define Documentation

#define DMA2D_COLOR_VALUE ((uint32_t)0x000000FFU)

Color value mask

Definition at line 531 of file stm32h7xx_hal_dma2d.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA2D Offset

Defines
DMA2D Offset
DMA2D Private Constants

Defines

#define DMA2D_OFFSET DMA2D_FGOR_LO

Define Documentation

#define DMA2D_OFFSET DMA2D_FGOR_LO

maximum Line Offset

Definition at line 539 of file stm32h7xx_hal_dma2d.h.

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STM32H753xx HAL User Manual: DMA2D Size

Defines
DMA2D Size
DMA2D Private Constants

Defines

#define | DMA2D_PIXEL (DMA2D_NLR_PL >> 16U)
#define | DMA2D_LINE DMA2D_NLR_NL

Define Documentation

#define DMA2D_LINE DMA2D_NLR_NL

DMA2D maximum number of lines

Definition at line 548 of file stm32h7xx_hal_dma2d.h.

#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U)

DMA2D maximum number of pixels per line

Definition at line 547 of file stm32h7xx_hal_dma2d.h.

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STM32H753xx HAL User Manual: DMA2D CLUT Size

Defines
DMA2D CLUT Size
DMA2D Private Constants

Defines

#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8)

Define Documentation

#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8)

DMA2D maximum CLUT size

Definition at line 556 of file stm32h7xx_hal_dma2d.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DMA2D Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA2D_Init (DMA2D_HandleTypeDef *hdma2d)
Initialize the DMA2D according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d)
Deinitializes the DMA2D peripheral registers to their default reset values.
__weak void | HAL_DMA2D_MspInit (DMA2D_HandleTypeDef *hdma2d)
Initializes the DMA2D MSP.
__weak void | HAL_DMA2D_MspDeInit (DMA2D_HandleTypeDef *hdma2d)
DeInitializes the DMA2D MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
                ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the DMA2D
      (+) De-initialize the DMA2D

Function Documentation

HAL_StatusTypeDef HAL_DMA2D_DeInit ( DMA2D_HandleTypeDef * hdma2d )

Deinitializes the DMA2D peripheral registers to their default reset values.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
None

Definition at line 290 of file stm32h7xx_hal_dma2d.c.

References __DMA2D_HandleTypeDef::ErrorCode, HAL_DMA2D_Abort(), HAL_DMA2D_CLUTLoading_Abort(), HAL_DMA2D_ERROR_NONE, HAL_DMA2D_MspDeInit(), HAL_DMA2D_STATE_RESET, __DMA2D_HandleTypeDef::Instance, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_Init ( DMA2D_HandleTypeDef * hdma2d )

Initialize the DMA2D according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL status

Definition at line 233 of file stm32h7xx_hal_dma2d.c.

References DMA2D_InitTypeDef::AlphaInverted, assert_param, DMA2D_InitTypeDef::ColorMode, DMA2D_POSITION_OPFCCR_AI, DMA2D_POSITION_OPFCCR_RBS, __DMA2D_HandleTypeDef::ErrorCode, HAL_DMA2D_ERROR_NONE, HAL_DMA2D_MspInit(), HAL_DMA2D_STATE_BUSY, HAL_DMA2D_STATE_READY, HAL_DMA2D_STATE_RESET, __DMA2D_HandleTypeDef::Init, __DMA2D_HandleTypeDef::Instance, IS_DMA2D_CMODE, IS_DMA2D_MODE, IS_DMA2D_OFFSET, __DMA2D_HandleTypeDef::Lock, DMA2D_InitTypeDef::Mode, DMA2D_InitTypeDef::OutputOffset, DMA2D_InitTypeDef::RedBlueSwap, and __DMA2D_HandleTypeDef::State.

void HAL_DMA2D_MspDeInit ( DMA2D_HandleTypeDef * hdma2d )

DeInitializes the DMA2D MSP.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
None

Definition at line 380 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_DeInit().

void HAL_DMA2D_MspInit ( DMA2D_HandleTypeDef * hdma2d )

Initializes the DMA2D MSP.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
None

Definition at line 364 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_Init().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
DMA2D Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA2D_Start (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Start_IT (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the DMA2D Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_BlendingStart (DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the multi-source DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_BlendingStart_IT (DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the multi-source DMA2D Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_Abort (DMA2D_HandleTypeDef *hdma2d)
Abort the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Suspend (DMA2D_HandleTypeDef *hdma2d)
Suspend the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Resume (DMA2D_HandleTypeDef *hdma2d)
Resume the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_EnableCLUT (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Enable the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoad (DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Start DMA2D CLUT Loading.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoad_IT (DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Start DMA2D CLUT Loading with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoading_Abort (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Abort the DMA2D CLUT loading.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoading_Suspend (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Suspend the DMA2D CLUT loading.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoading_Resume (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Resume the DMA2D CLUT loading.
HAL_StatusTypeDef | HAL_DMA2D_PollForTransfer (DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
Polling for transfer complete or CLUT loading.
void | HAL_DMA2D_IRQHandler (DMA2D_HandleTypeDef *hdma2d)
Handle DMA2D interrupt request.
__weak void | HAL_DMA2D_LineEventCallback (DMA2D_HandleTypeDef *hdma2d)
Transfer watermark callback.
__weak void | HAL_DMA2D_CLUTLoadingCpltCallback (DMA2D_HandleTypeDef *hdma2d)
CLUT Transfer Complete callback.

Detailed Description

IO operation functions.

 ===============================================================================
                      #####  IO operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the pdata, destination address and data size then
          start the DMA2D transfer.
      (+) Configure the source for foreground and background, destination address
          and data size then start a MultiBuffer DMA2D transfer.
      (+) Configure the pdata, destination address and data size then
          start the DMA2D transfer with interrupt.
      (+) Configure the source for foreground and background, destination address
          and data size then start a MultiBuffer DMA2D transfer with interrupt.
      (+) Abort DMA2D transfer.
      (+) Suspend DMA2D transfer.
      (+) Resume DMA2D transfer.
      (+) Enable CLUT transfer.
      (+) Configure CLUT loading then start transfer in polling mode.
      (+) Configure CLUT loading then start transfer in interrupt mode.
      (+) Abort DMA2D CLUT loading.
      (+) Suspend DMA2D CLUT loading.
      (+) Resume DMA2D CLUT loading.
      (+) Poll for transfer complete.
      (+) handle DMA2D interrupt request.
      (+) Transfer watermark callback.
      (+) CLUT Transfer Complete callback.

Function Documentation

HAL_StatusTypeDef HAL_DMA2D_Abort ( DMA2D_HandleTypeDef * hdma2d )

Abort the DMA2D Transfer.

Parameters:
hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL status

Definition at line 580 of file stm32h7xx_hal_dma2d.c.

References __HAL_DMA2D_DISABLE_IT, DMA2D_IT_CE, DMA2D_IT_TC, DMA2D_IT_TE, DMA2D_TIMEOUT_ABORT, __DMA2D_HandleTypeDef::ErrorCode, HAL_DMA2D_ERROR_TIMEOUT, HAL_DMA2D_STATE_READY, HAL_DMA2D_STATE_TIMEOUT, HAL_GetTick(), __DMA2D_HandleTypeDef::Instance, and __DMA2D_HandleTypeDef::State.

Referenced by HAL_DMA2D_DeInit().

HAL_StatusTypeDef HAL_DMA2D_BlendingStart | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | SrcAddress1,
 |  | uint32_t | SrcAddress2,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Width,
 |  | uint32_t | Height
 | ) |  |

Start the multi-source DMA2D Transfer.

Parameters:
hdma2d,: Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
SrcAddress1,: The source memory Buffer address for the foreground layer.
SrcAddress2,: The source memory Buffer address for the background layer.
DstAddress,: The destination memory Buffer address.
Width,: The width of data to be transferred from source to destination (expressed in number of pixels per line).
Height,: The height of data to be transferred from source to destination (expressed in number of lines).
Return values:
HAL status

Definition at line 512 of file stm32h7xx_hal_dma2d.c.

References __HAL_DMA2D_ENABLE, assert_param, DMA2D_SetConfig(), HAL_DMA2D_STATE_BUSY, __DMA2D_HandleTypeDef::Instance, IS_DMA2D_LINE, IS_DMA2D_PIXEL, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | SrcAddress1,
 |  | uint32_t | SrcAddress2,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Width,
 |  | uint32_t | Height
 | ) |  |

Start the multi-source DMA2D Transfer with interrupt enabled.

Parameters:
hdma2d,: Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
SrcAddress1,: The source memory Buffer address for the foreground layer.
SrcAddress2,: The source memory Buffer address for the background layer.
DstAddress,: The destination memory Buffer address.
Width,: The width of data to be transferred from source to destination (expressed in number of pixels per line).
Height,: The height of data to be transferred from source to destination (expressed in number of lines).
Return values:
HAL status

Definition at line 547 of file stm32h7xx_hal_dma2d.c.

References __HAL_DMA2D_ENABLE, __HAL_DMA2D_ENABLE_IT, assert_param, DMA2D_IT_CE, DMA2D_IT_TC, DMA2D_IT_TE, DMA2D_SetConfig(), HAL_DMA2D_STATE_BUSY, __DMA2D_HandleTypeDef::Instance, IS_DMA2D_LINE, IS_DMA2D_PIXEL, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_CLUTLoad | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | DMA2D_CLUTCfgTypeDef | CLUTCfg,
 |  | uint32_t | LayerIdx
 | ) |  |

Start DMA2D CLUT Loading.

Parameters:
hdma2d,: Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
CLUTCfg,: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains the configuration information for the color look up table.
LayerIdx,: DMA2D Layer index. This parameter can be one of the following values: 0(background) / 1(foreground)
Note:
Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
Return values:
HAL status

Definition at line 745 of file stm32h7xx_hal_dma2d.c.

References assert_param, DMA2D_CLUTCfgTypeDef::CLUTColorMode, DMA2D_POSITION_BGPFCCR_CCM, DMA2D_POSITION_BGPFCCR_CS, DMA2D_POSITION_FGPFCCR_CCM, HAL_DMA2D_STATE_BUSY, __DMA2D_HandleTypeDef::Instance, IS_DMA2D_CLUT_CM, IS_DMA2D_CLUT_SIZE, IS_DMA2D_LAYER, DMA2D_CLUTCfgTypeDef::pCLUT, DMA2D_CLUTCfgTypeDef::Size, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | DMA2D_CLUTCfgTypeDef | CLUTCfg,
 |  | uint32_t | LayerIdx
 | ) |  |

Start DMA2D CLUT Loading with interrupt enabled.

Parameters:
hdma2d,: Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
CLUTCfg,: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains the configuration information for the color look up table.
LayerIdx,: DMA2D Layer index. This parameter can be one of the following values: 0(background) / 1(foreground)
Return values:
HAL status

Definition at line 799 of file stm32h7xx_hal_dma2d.c.

References __HAL_DMA2D_ENABLE_IT, assert_param, DMA2D_CLUTCfgTypeDef::CLUTColorMode, DMA2D_IT_CAE, DMA2D_IT_CE, DMA2D_IT_CTC, DMA2D_IT_TE, DMA2D_POSITION_BGPFCCR_CCM, DMA2D_POSITION_BGPFCCR_CS, DMA2D_POSITION_FGPFCCR_CCM, HAL_DMA2D_STATE_BUSY, __DMA2D_HandleTypeDef::Instance, IS_DMA2D_CLUT_CM, IS_DMA2D_CLUT_SIZE, IS_DMA2D_LAYER, DMA2D_CLUTCfgTypeDef::pCLUT, DMA2D_CLUTCfgTypeDef::Size, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | LayerIdx
 | ) |  |

Abort the DMA2D CLUT loading.

Parameters:
hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
LayerIdx,: DMA2D Layer index. This parameter can be one of the following values: 0(background) / 1(foreground)
Return values:
HAL status

Definition at line 857 of file stm32h7xx_hal_dma2d.c.

References __HAL_DMA2D_DISABLE_IT, DMA2D_IT_CAE, DMA2D_IT_CE, DMA2D_IT_CTC, DMA2D_IT_TE, DMA2D_TIMEOUT_ABORT, __DMA2D_HandleTypeDef::ErrorCode, HAL_DMA2D_ERROR_TIMEOUT, HAL_DMA2D_STATE_READY, HAL_DMA2D_STATE_TIMEOUT, HAL_GetTick(), __DMA2D_HandleTypeDef::Instance, and __DMA2D_HandleTypeDef::State.

Referenced by HAL_DMA2D_DeInit().

HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | LayerIdx
 | ) |  |

Resume the DMA2D CLUT loading.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
LayerIdx,: DMA2D Layer index. This parameter can be one of the following values: 0(background) / 1(foreground)
Return values:
HAL status

Definition at line 975 of file stm32h7xx_hal_dma2d.c.

References HAL_DMA2D_STATE_BUSY, __DMA2D_HandleTypeDef::Instance, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | LayerIdx
 | ) |  |

Suspend the DMA2D CLUT loading.

Parameters:
hdma2d,: Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
LayerIdx,: DMA2D Layer index. This parameter can be one of the following values: 0(background) / 1(foreground)
Return values:
HAL status

Definition at line 916 of file stm32h7xx_hal_dma2d.c.

References DMA2D_TIMEOUT_SUSPEND, __DMA2D_HandleTypeDef::ErrorCode, HAL_DMA2D_ERROR_TIMEOUT, HAL_DMA2D_STATE_SUSPEND, HAL_DMA2D_STATE_TIMEOUT, HAL_GetTick(), __DMA2D_HandleTypeDef::Instance, and __DMA2D_HandleTypeDef::State.

void HAL_DMA2D_CLUTLoadingCpltCallback ( DMA2D_HandleTypeDef * hdma2d )

CLUT Transfer Complete callback.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
None

Definition at line 1317 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_IRQHandler().

HAL_StatusTypeDef HAL_DMA2D_EnableCLUT | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | LayerIdx
 | ) |  |

Enable the DMA2D CLUT Transfer.

Parameters:
hdma2d,: Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
LayerIdx,: DMA2D Layer index. This parameter can be one of the following values: 0(background) / 1(foreground)
Return values:
HAL status

Definition at line 707 of file stm32h7xx_hal_dma2d.c.

References assert_param, HAL_DMA2D_STATE_BUSY, __DMA2D_HandleTypeDef::Instance, IS_DMA2D_LAYER, and __DMA2D_HandleTypeDef::State.

void HAL_DMA2D_IRQHandler ( DMA2D_HandleTypeDef * hdma2d )

Handle DMA2D interrupt request.

Parameters:
hdma2d,: Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL status

Definition at line 1140 of file stm32h7xx_hal_dma2d.c.

References __HAL_DMA2D_CLEAR_FLAG, __HAL_DMA2D_DISABLE_IT, DMA2D_FLAG_CAE, DMA2D_FLAG_CE, DMA2D_FLAG_CTC, DMA2D_FLAG_TC, DMA2D_FLAG_TE, DMA2D_FLAG_TW, DMA2D_IT_CAE, DMA2D_IT_CE, DMA2D_IT_CTC, DMA2D_IT_TC, DMA2D_IT_TE, DMA2D_IT_TW, __DMA2D_HandleTypeDef::ErrorCode, HAL_DMA2D_CLUTLoadingCpltCallback(), HAL_DMA2D_ERROR_CAE, HAL_DMA2D_ERROR_CE, HAL_DMA2D_ERROR_NONE, HAL_DMA2D_ERROR_TE, HAL_DMA2D_LineEventCallback(), HAL_DMA2D_STATE_ERROR, HAL_DMA2D_STATE_READY, __DMA2D_HandleTypeDef::Instance, __DMA2D_HandleTypeDef::State, __DMA2D_HandleTypeDef::XferCpltCallback, and __DMA2D_HandleTypeDef::XferErrorCallback.

void HAL_DMA2D_LineEventCallback ( DMA2D_HandleTypeDef * hdma2d )

Transfer watermark callback.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
None

Definition at line 1301 of file stm32h7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_IRQHandler().

HAL_StatusTypeDef HAL_DMA2D_PollForTransfer | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | Timeout
 | ) |  |

Polling for transfer complete or CLUT loading.

Parameters:
hdma2d,: Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1014 of file stm32h7xx_hal_dma2d.c.

References __HAL_DMA2D_CLEAR_FLAG, __HAL_DMA2D_GET_FLAG, DMA2D_FLAG_CAE, DMA2D_FLAG_CE, DMA2D_FLAG_CTC, DMA2D_FLAG_TC, DMA2D_FLAG_TE, __DMA2D_HandleTypeDef::ErrorCode, HAL_DMA2D_ERROR_CAE, HAL_DMA2D_ERROR_CE, HAL_DMA2D_ERROR_TE, HAL_DMA2D_ERROR_TIMEOUT, HAL_DMA2D_STATE_ERROR, HAL_DMA2D_STATE_READY, HAL_DMA2D_STATE_TIMEOUT, HAL_GetTick(), __DMA2D_HandleTypeDef::Instance, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_Resume ( DMA2D_HandleTypeDef * hdma2d )

Resume the DMA2D Transfer.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL status

Definition at line 679 of file stm32h7xx_hal_dma2d.c.

References HAL_DMA2D_STATE_BUSY, __DMA2D_HandleTypeDef::Instance, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_Start | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | pdata,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Width,
 |  | uint32_t | Height
 | ) |  |

Start the DMA2D Transfer.

Parameters:
hdma2d,: Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
pdata,: Configure the source memory Buffer address if Memory-to-Memory or Memory-to-Memory with pixel format conversion mode is selected, or configure the color value if Register-to-Memory mode is selected.
DstAddress,: The destination memory Buffer address.
Width,: The width of data to be transferred from source to destination (expressed in number of pixels per line).
Height,: The height of data to be transferred from source to destination (expressed in number of lines).
Return values:
HAL status

Definition at line 443 of file stm32h7xx_hal_dma2d.c.

References __HAL_DMA2D_ENABLE, assert_param, DMA2D_SetConfig(), HAL_DMA2D_STATE_BUSY, IS_DMA2D_LINE, IS_DMA2D_PIXEL, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_Start_IT | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | pdata,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Width,
 |  | uint32_t | Height
 | ) |  |

Start the DMA2D Transfer with interrupt enabled.

Parameters:
hdma2d,: Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
pdata,: Configure the source memory Buffer address if the Memory-to-Memory or Memory-to-Memory with pixel format conversion mode is selected, or configure the color value if Register-to-Memory mode is selected.
DstAddress,: The destination memory Buffer address.
Width,: The width of data to be transferred from source to destination (expressed in number of pixels per line).
Height,: The height of data to be transferred from source to destination (expressed in number of lines).
Return values:
HAL status

Definition at line 477 of file stm32h7xx_hal_dma2d.c.

References __HAL_DMA2D_ENABLE, __HAL_DMA2D_ENABLE_IT, assert_param, DMA2D_IT_CE, DMA2D_IT_TC, DMA2D_IT_TE, DMA2D_SetConfig(), HAL_DMA2D_STATE_BUSY, IS_DMA2D_LINE, IS_DMA2D_PIXEL, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_Suspend ( DMA2D_HandleTypeDef * hdma2d )

Suspend the DMA2D Transfer.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL status

Definition at line 629 of file stm32h7xx_hal_dma2d.c.

References DMA2D_TIMEOUT_SUSPEND, __DMA2D_HandleTypeDef::ErrorCode, HAL_DMA2D_ERROR_TIMEOUT, HAL_DMA2D_STATE_SUSPEND, HAL_DMA2D_STATE_TIMEOUT, HAL_GetTick(), __DMA2D_HandleTypeDef::Instance, and __DMA2D_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
DMA2D Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA2D_ConfigLayer (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Configure the DMA2D Layer according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA2D_ConfigCLUT (DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Configure the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_ProgramLineEvent (DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
Configure the line watermark.
HAL_StatusTypeDef | HAL_DMA2D_EnableDeadTime (DMA2D_HandleTypeDef *hdma2d)
Enable DMA2D dead time feature.
HAL_StatusTypeDef | HAL_DMA2D_DisableDeadTime (DMA2D_HandleTypeDef *hdma2d)
Disable DMA2D dead time feature.
HAL_StatusTypeDef | HAL_DMA2D_ConfigDeadTime (DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
Configure dead time.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                    ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the DMA2D foreground or background layer parameters.
      (+) Configure the DMA2D CLUT transfer.
      (+) Configure the line watermark
      (+) Configure the dead time value.
      (+) Enable or disable the dead time value functionality.

Function Documentation

HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | DMA2D_CLUTCfgTypeDef | CLUTCfg,
 |  | uint32_t | LayerIdx
 | ) |  |

Configure the DMA2D CLUT Transfer.

Parameters:
hdma2d,: Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
CLUTCfg,: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains the configuration information for the color look up table.
LayerIdx,: DMA2D Layer index. This parameter can be one of the following values: 0(background) / 1(foreground)
Return values:
HAL status

Definition at line 1458 of file stm32h7xx_hal_dma2d.c.

References assert_param, DMA2D_CLUTCfgTypeDef::CLUTColorMode, DMA2D_POSITION_BGPFCCR_CCM, DMA2D_POSITION_BGPFCCR_CS, DMA2D_POSITION_FGPFCCR_CCM, HAL_DMA2D_STATE_BUSY, HAL_DMA2D_STATE_READY, __DMA2D_HandleTypeDef::Instance, IS_DMA2D_CLUT_CM, IS_DMA2D_CLUT_SIZE, IS_DMA2D_LAYER, DMA2D_CLUTCfgTypeDef::pCLUT, DMA2D_CLUTCfgTypeDef::Size, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint8_t | DeadTime
 | ) |  |

Configure dead time.

Note:
The dead time value represents the guaranteed minimum number of cycles between two consecutive transactions on the AHB bus.
Parameters:
hdma2d,: DMA2D handle.
DeadTime,: dead time value.
Return values:
HAL status

Definition at line 1592 of file stm32h7xx_hal_dma2d.c.

References DMA2D_POSITION_AMTCR_DT, HAL_DMA2D_STATE_BUSY, HAL_DMA2D_STATE_READY, __DMA2D_HandleTypeDef::Instance, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_ConfigLayer | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | LayerIdx
 | ) |  |

Configure the DMA2D Layer according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
LayerIdx,: DMA2D Layer index. This parameter can be one of the following values: 0(background) / 1(foreground)
Return values:
HAL status

Definition at line 1360 of file stm32h7xx_hal_dma2d.c.

References DMA2D_LayerCfgTypeDef::AlphaInverted, DMA2D_LayerCfgTypeDef::AlphaMode, assert_param, DMA2D_LayerCfgTypeDef::ChromaSubSampling, DMA2D_INPUT_A4, DMA2D_INPUT_A8, DMA2D_INPUT_YCBCR, DMA2D_M2M, DMA2D_POSITION_BGPFCCR_AI, DMA2D_POSITION_BGPFCCR_ALPHA, DMA2D_POSITION_BGPFCCR_AM, DMA2D_POSITION_BGPFCCR_RBS, DMA2D_POSITION_FGPFCCR_CSS, DMA2D_R2M, HAL_DMA2D_STATE_BUSY, HAL_DMA2D_STATE_READY, __DMA2D_HandleTypeDef::Init, DMA2D_LayerCfgTypeDef::InputAlpha, DMA2D_LayerCfgTypeDef::InputColorMode, DMA2D_LayerCfgTypeDef::InputOffset, __DMA2D_HandleTypeDef::Instance, IS_DMA2D_ALPHA_MODE, IS_DMA2D_INPUT_COLOR_MODE, IS_DMA2D_LAYER, IS_DMA2D_OFFSET, __DMA2D_HandleTypeDef::LayerCfg, DMA2D_InitTypeDef::Mode, DMA2D_LayerCfgTypeDef::RedBlueSwap, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime ( DMA2D_HandleTypeDef * hdma2d )

Disable DMA2D dead time feature.

Parameters:
hdma2d,: DMA2D handle.
Return values:
HAL status

Definition at line 1566 of file stm32h7xx_hal_dma2d.c.

References HAL_DMA2D_STATE_BUSY, HAL_DMA2D_STATE_READY, __DMA2D_HandleTypeDef::Instance, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime ( DMA2D_HandleTypeDef * hdma2d )

Enable DMA2D dead time feature.

Parameters:
hdma2d,: DMA2D handle.
Return values:
HAL status

Definition at line 1543 of file stm32h7xx_hal_dma2d.c.

References HAL_DMA2D_STATE_BUSY, HAL_DMA2D_STATE_READY, __DMA2D_HandleTypeDef::Instance, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | Line
 | ) |  |

Configure the line watermark.

Parameters:
hdma2d,: Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Line,: Line Watermark configuration (maximum 16-bit long value expected).
Note:
HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
The transfer watermark interrupt is disabled once it has occurred.
Return values:
HAL status

Definition at line 1512 of file stm32h7xx_hal_dma2d.c.

References __HAL_DMA2D_ENABLE_IT, assert_param, DMA2D_IT_TW, HAL_DMA2D_STATE_BUSY, HAL_DMA2D_STATE_READY, __DMA2D_HandleTypeDef::Instance, IS_DMA2D_LINEWATERMARK, and __DMA2D_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
DMA2D Exported Functions

Peripheral State functions. More...

Functions

HAL_DMA2D_StateTypeDef | HAL_DMA2D_GetState (DMA2D_HandleTypeDef *hdma2d)
Return the DMA2D state.
uint32_t | HAL_DMA2D_GetError (DMA2D_HandleTypeDef *hdma2d)
Return the DMA2D error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                  ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) Get the DMA2D state
      (+) Get the DMA2D error code

Function Documentation

uint32_t HAL_DMA2D_GetError ( DMA2D_HandleTypeDef * hdma2d )

Return the DMA2D error code.

Parameters:
hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for DMA2D.
Return values:
DMA2D Error Code

Definition at line 1648 of file stm32h7xx_hal_dma2d.c.

References __DMA2D_HandleTypeDef::ErrorCode.

HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState ( DMA2D_HandleTypeDef * hdma2d )

Return the DMA2D state.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL state

Definition at line 1637 of file stm32h7xx_hal_dma2d.c.

References __DMA2D_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA2D Private Functions

Functions
DMA2D Private Functions
DMA2D

Functions

static void DMA2D_SetConfig (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Set the DMA2D transfer parameters.

Function Documentation

static void DMA2D_SetConfig | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | pdata,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Width,
 |  | uint32_t | Height
 | ) |  | [static]

Set the DMA2D transfer parameters.

Parameters:
hdma2d,: Pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the specified DMA2D.
pdata,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
Width,: The width of data to be transferred from source to destination.
Height,: The height of data to be transferred from source to destination.
Return values:
HAL status

Definition at line 1676 of file stm32h7xx_hal_dma2d.c.

References DMA2D_InitTypeDef::ColorMode, DMA2D_OUTPUT_ARGB1555, DMA2D_OUTPUT_ARGB8888, DMA2D_OUTPUT_RGB565, DMA2D_OUTPUT_RGB888, DMA2D_POSITION_NLR_PL, DMA2D_R2M, __DMA2D_HandleTypeDef::Init, __DMA2D_HandleTypeDef::Instance, and DMA2D_InitTypeDef::Mode.

Referenced by HAL_DMA2D_BlendingStart(), HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_Start(), and HAL_DMA2D_Start_IT().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA2D Exported Types

Data Structures | Defines | Typedefs | Enumerations
DMA2D Exported Types
DMA2D

Data Structures

struct | DMA2D_ColorTypeDef
DMA2D color Structure definition. More...
struct | DMA2D_CLUTCfgTypeDef
DMA2D CLUT Structure definition. More...
struct | DMA2D_InitTypeDef
DMA2D Init structure definition. More...
struct | DMA2D_LayerCfgTypeDef
DMA2D Layer structure definition. More...
struct | __DMA2D_HandleTypeDef
DMA2D handle Structure definition. More...

Defines

#define | MAX_DMA2D_LAYER 2U

Typedefs

typedef struct
__DMA2D_HandleTypeDef 		DMA2D_HandleTypeDef
DMA2D handle Structure definition.

Enumerations

enum HAL_DMA2D_StateTypeDef {
HAL_DMA2D_STATE_RESET = 0x00U, HAL_DMA2D_STATE_READY = 0x01U, HAL_DMA2D_STATE_BUSY = 0x02U, HAL_DMA2D_STATE_TIMEOUT = 0x03U,
HAL_DMA2D_STATE_ERROR = 0x04U, HAL_DMA2D_STATE_SUSPEND = 0x05U
}
HAL DMA2D State structures definition. More...

Define Documentation

#define MAX_DMA2D_LAYER 2U

DMA2D maximum number of layers

Definition at line 62 of file stm32h7xx_hal_dma2d.h.

Typedef Documentation

typedef struct __DMA2D_HandleTypeDef DMA2D_HandleTypeDef

DMA2D handle Structure definition.

Enumeration Type Documentation

enum HAL_DMA2D_StateTypeDef

HAL DMA2D State structures definition.

Enumerator:
HAL_DMA2D_STATE_RESET

DMA2D not yet initialized or disabled

HAL_DMA2D_STATE_READY

Peripheral Initialized and ready for use

HAL_DMA2D_STATE_BUSY

An internal process is ongoing

HAL_DMA2D_STATE_TIMEOUT

Timeout state

HAL_DMA2D_STATE_ERROR

DMA2D state error

HAL_DMA2D_STATE_SUSPEND

DMA2D process is suspended

Definition at line 152 of file stm32h7xx_hal_dma2d.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA2D_ColorTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA2D_ColorTypeDef Struct Reference
DMA2D Exported Types

DMA2D color Structure definition. More...

#include <stm32h7xx_hal_dma2d.h>

Data Fields

uint32_t | Blue
uint32_t | Green
uint32_t | Red

Detailed Description

DMA2D color Structure definition.

Definition at line 67 of file stm32h7xx_hal_dma2d.h.

Field Documentation

uint32_t DMA2D_ColorTypeDef::Blue

Configures the blue value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

Definition at line 69 of file stm32h7xx_hal_dma2d.h.

uint32_t DMA2D_ColorTypeDef::Green

Configures the green value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

Definition at line 72 of file stm32h7xx_hal_dma2d.h.

uint32_t DMA2D_ColorTypeDef::Red

Configures the red value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

Definition at line 75 of file stm32h7xx_hal_dma2d.h.

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dma2d.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA2D_CLUTCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA2D_CLUTCfgTypeDef Struct Reference
DMA2D Exported Types

DMA2D CLUT Structure definition. More...

#include <stm32h7xx_hal_dma2d.h>

Data Fields

uint32_t * | pCLUT
uint32_t | CLUTColorMode
uint32_t | Size

Detailed Description

DMA2D CLUT Structure definition.

Definition at line 82 of file stm32h7xx_hal_dma2d.h.

Field Documentation

uint32_t DMA2D_CLUTCfgTypeDef::CLUTColorMode

Configures the DMA2D CLUT color mode. This parameter can be one value of DMA2D CLUT Color Mode.

Definition at line 86 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_CLUTLoad(), HAL_DMA2D_CLUTLoad_IT(), and HAL_DMA2D_ConfigCLUT().

uint32_t* DMA2D_CLUTCfgTypeDef::pCLUT

Configures the DMA2D CLUT memory address.

Definition at line 84 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_CLUTLoad(), HAL_DMA2D_CLUTLoad_IT(), and HAL_DMA2D_ConfigCLUT().

uint32_t DMA2D_CLUTCfgTypeDef::Size

Configures the DMA2D CLUT size. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

Definition at line 89 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_CLUTLoad(), HAL_DMA2D_CLUTLoad_IT(), and HAL_DMA2D_ConfigCLUT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dma2d.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA2D_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA2D_InitTypeDef Struct Reference
DMA2D Exported Types

DMA2D Init structure definition. More...

#include <stm32h7xx_hal_dma2d.h>

Data Fields

uint32_t | Mode
uint32_t | ColorMode
uint32_t | OutputOffset
uint32_t | AlphaInverted
uint32_t | RedBlueSwap

Detailed Description

DMA2D Init structure definition.

Definition at line 96 of file stm32h7xx_hal_dma2d.h.

Field Documentation

uint32_t DMA2D_InitTypeDef::AlphaInverted

Select regular or inverted alpha value for the output pixel format converter. This parameter can be one value of DMA2D ALPHA Inversion

Definition at line 106 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_Init().

uint32_t DMA2D_InitTypeDef::ColorMode

Configures the color format of the output image. This parameter can be one value of DMA2D Output Color Mode.

Definition at line 101 of file stm32h7xx_hal_dma2d.h.

Referenced by DMA2D_SetConfig(), and HAL_DMA2D_Init().

uint32_t DMA2D_InitTypeDef::Mode

Configures the DMA2D transfer mode. This parameter can be one value of DMA2D Mode.

Definition at line 98 of file stm32h7xx_hal_dma2d.h.

Referenced by DMA2D_SetConfig(), HAL_DMA2D_ConfigLayer(), and HAL_DMA2D_Init().

uint32_t DMA2D_InitTypeDef::OutputOffset

Specifies the Offset value. This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.

Definition at line 104 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_Init().

uint32_t DMA2D_InitTypeDef::RedBlueSwap

Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) for the output pixel format converter. This parameter can be one value of DMA2D Red and Blue Swap.

Definition at line 109 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dma2d.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA2D_LayerCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA2D_LayerCfgTypeDef Struct Reference
DMA2D Exported Types

DMA2D Layer structure definition. More...

#include <stm32h7xx_hal_dma2d.h>

Data Fields

uint32_t | InputOffset
uint32_t | InputColorMode
uint32_t | AlphaMode
uint32_t | InputAlpha
uint32_t | AlphaInverted
uint32_t | RedBlueSwap
uint32_t | ChromaSubSampling

Detailed Description

DMA2D Layer structure definition.

Definition at line 119 of file stm32h7xx_hal_dma2d.h.

Field Documentation

uint32_t DMA2D_LayerCfgTypeDef::AlphaInverted

Select regular or inverted alpha value. This parameter can be one value of DMA2D ALPHA Inversion.

Definition at line 139 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

uint32_t DMA2D_LayerCfgTypeDef::AlphaMode

Configures the DMA2D foreground or background alpha mode. This parameter can be one value of DMA2D Alpha Mode.

Definition at line 127 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

uint32_t DMA2D_LayerCfgTypeDef::ChromaSubSampling

Configure the chroma sub-sampling mode for the YCbCr color mode This parameter can be one value of DMA2D Chroma Sub Sampling

Definition at line 145 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

uint32_t DMA2D_LayerCfgTypeDef::InputAlpha

Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.

Note:
In case of A8 or A4 color mode (ARGB), this parameter must be a number between Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
  • InputAlpha[24:31] is the alpha value ALPHA[0:7]
  • InputAlpha[16:23] is the red value RED[0:7]
  • InputAlpha[8:15] is the green value GREEN[0:7]
  • InputAlpha[0:7] is the blue value BLUE[0:7].

Definition at line 130 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

uint32_t DMA2D_LayerCfgTypeDef::InputColorMode

Configures the DMA2D foreground or background color mode. This parameter can be one value of DMA2D Input Color Mode.

Definition at line 124 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

uint32_t DMA2D_LayerCfgTypeDef::InputOffset

Configures the DMA2D foreground or background offset. This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.

Definition at line 121 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

uint32_t DMA2D_LayerCfgTypeDef::RedBlueSwap

Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). This parameter can be one value of DMA2D Red and Blue Swap.

Definition at line 142 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dma2d.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: __DMA2D_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__DMA2D_HandleTypeDef Struct Reference
DMA2D Exported Types

DMA2D handle Structure definition. More...

#include <stm32h7xx_hal_dma2d.h>

Data Fields

DMA2D_TypeDef * | Instance
DMA2D_InitTypeDef Init
void(* | XferCpltCallback )(struct __DMA2D_HandleTypeDef *hdma2d)
void(* | XferErrorCallback )(struct __DMA2D_HandleTypeDef *hdma2d)
DMA2D_LayerCfgTypeDef LayerCfg [MAX_DMA2D_LAYER]
HAL_LockTypeDef | Lock
__IO HAL_DMA2D_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

DMA2D handle Structure definition.

Definition at line 165 of file stm32h7xx_hal_dma2d.h.

Field Documentation

__IO uint32_t __DMA2D_HandleTypeDef::ErrorCode

DMA2D error code.

Definition at line 181 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_Abort(), HAL_DMA2D_CLUTLoading_Abort(), HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_DeInit(), HAL_DMA2D_GetError(), HAL_DMA2D_Init(), HAL_DMA2D_IRQHandler(), HAL_DMA2D_PollForTransfer(), and HAL_DMA2D_Suspend().

DMA2D_InitTypeDef __DMA2D_HandleTypeDef::Init

DMA2D communication parameters.

Definition at line 169 of file stm32h7xx_hal_dma2d.h.

Referenced by DMA2D_SetConfig(), HAL_DMA2D_ConfigLayer(), HAL_DMA2D_Init(), and HAL_ETH_GetRxDataBuffer().

DMA2D_TypeDef* __DMA2D_HandleTypeDef::Instance

DMA2D register base address.

Definition at line 167 of file stm32h7xx_hal_dma2d.h.

Referenced by DMA2D_SetConfig(), HAL_DMA2D_Abort(), HAL_DMA2D_BlendingStart(), HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_CLUTLoad(), HAL_DMA2D_CLUTLoad_IT(), HAL_DMA2D_CLUTLoading_Abort(), HAL_DMA2D_CLUTLoading_Resume(), HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_ConfigCLUT(), HAL_DMA2D_ConfigDeadTime(), HAL_DMA2D_ConfigLayer(), HAL_DMA2D_DeInit(), HAL_DMA2D_DisableDeadTime(), HAL_DMA2D_EnableCLUT(), HAL_DMA2D_EnableDeadTime(), HAL_DMA2D_Init(), HAL_DMA2D_IRQHandler(), HAL_DMA2D_PollForTransfer(), HAL_DMA2D_ProgramLineEvent(), HAL_DMA2D_Resume(), and HAL_DMA2D_Suspend().

DMA2D_LayerCfgTypeDef __DMA2D_HandleTypeDef::LayerCfg[MAX_DMA2D_LAYER]

DMA2D Layers parameters

Definition at line 175 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

HAL_LockTypeDef __DMA2D_HandleTypeDef::Lock

DMA2D lock.

Definition at line 177 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_Init().

__IO HAL_DMA2D_StateTypeDef __DMA2D_HandleTypeDef::State

DMA2D transfer state.

Definition at line 179 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_Abort(), HAL_DMA2D_BlendingStart(), HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_CLUTLoad(), HAL_DMA2D_CLUTLoad_IT(), HAL_DMA2D_CLUTLoading_Abort(), HAL_DMA2D_CLUTLoading_Resume(), HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_ConfigCLUT(), HAL_DMA2D_ConfigDeadTime(), HAL_DMA2D_ConfigLayer(), HAL_DMA2D_DeInit(), HAL_DMA2D_DisableDeadTime(), HAL_DMA2D_EnableCLUT(), HAL_DMA2D_EnableDeadTime(), HAL_DMA2D_GetState(), HAL_DMA2D_Init(), HAL_DMA2D_IRQHandler(), HAL_DMA2D_PollForTransfer(), HAL_DMA2D_ProgramLineEvent(), HAL_DMA2D_Resume(), HAL_DMA2D_Start(), HAL_DMA2D_Start_IT(), and HAL_DMA2D_Suspend().

void(* __DMA2D_HandleTypeDef::XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d)

DMA2D transfer complete callback.

Definition at line 171 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler().

void(* __DMA2D_HandleTypeDef::XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d)

DMA2D transfer error callback.

Definition at line 173 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dma2d.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA2D Error Code

Defines
DMA2D Error Code
DMA2D Exported Constants

Defines

#define | HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001U)
#define | HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002U)
#define | HAL_DMA2D_ERROR_CAE ((uint32_t)0x00000004U)
#define | HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020U)

Define Documentation

#define HAL_DMA2D_ERROR_CAE ((uint32_t)0x00000004U)

CLUT access error

Definition at line 198 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler(), and HAL_DMA2D_PollForTransfer().

#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002U)

Configuration error

Definition at line 197 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler(), and HAL_DMA2D_PollForTransfer().

#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 195 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_DeInit(), HAL_DMA2D_Init(), and HAL_DMA2D_IRQHandler().

#define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001U)

Transfer error

Definition at line 196 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler(), and HAL_DMA2D_PollForTransfer().

#define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020U)

Timeout error

Definition at line 199 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_Abort(), HAL_DMA2D_CLUTLoading_Abort(), HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_PollForTransfer(), and HAL_DMA2D_Suspend().

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STM32H753xx HAL User Manual: DMA2D Mode

Defines
DMA2D Mode
DMA2D Exported Constants

Defines

#define | DMA2D_M2M ((uint32_t)0x00000000U)
#define | DMA2D_M2M_PFC DMA2D_CR_MODE_0
#define | DMA2D_M2M_BLEND DMA2D_CR_MODE_1
#define | DMA2D_R2M DMA2D_CR_MODE

Define Documentation

#define DMA2D_M2M ((uint32_t)0x00000000U)

DMA2D memory to memory transfer mode

Definition at line 207 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1

DMA2D memory to memory with blending transfer mode

Definition at line 209 of file stm32h7xx_hal_dma2d.h.

#define DMA2D_M2M_PFC DMA2D_CR_MODE_0

DMA2D memory to memory with pixel format conversion transfer mode

Definition at line 208 of file stm32h7xx_hal_dma2d.h.

#define DMA2D_R2M DMA2D_CR_MODE

DMA2D register to memory transfer mode

Definition at line 210 of file stm32h7xx_hal_dma2d.h.

Referenced by DMA2D_SetConfig(), and HAL_DMA2D_ConfigLayer().

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STM32H753xx HAL User Manual: DMA2D Output Color Mode

Defines
DMA2D Output Color Mode
DMA2D Exported Constants

Defines

#define | DMA2D_OUTPUT_ARGB8888 ((uint32_t)0x00000000U)
#define | DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0
#define | DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1
#define | DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1)
#define | DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2

Define Documentation

#define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1)

ARGB1555 DMA2D color mode

Definition at line 221 of file stm32h7xx_hal_dma2d.h.

Referenced by DMA2D_SetConfig().

#define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2

ARGB4444 DMA2D color mode

Definition at line 222 of file stm32h7xx_hal_dma2d.h.

#define DMA2D_OUTPUT_ARGB8888 ((uint32_t)0x00000000U)

ARGB8888 DMA2D color mode

Definition at line 218 of file stm32h7xx_hal_dma2d.h.

Referenced by DMA2D_SetConfig().

#define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1

RGB565 DMA2D color mode

Definition at line 220 of file stm32h7xx_hal_dma2d.h.

Referenced by DMA2D_SetConfig().

#define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0

RGB888 DMA2D color mode

Definition at line 219 of file stm32h7xx_hal_dma2d.h.

Referenced by DMA2D_SetConfig().

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STM32H753xx HAL User Manual: DMA2D Input Color Mode

Defines
DMA2D Input Color Mode
DMA2D Exported Constants

Defines

#define | DMA2D_INPUT_ARGB8888 ((uint32_t)0x00000000U)
#define | DMA2D_INPUT_RGB888 ((uint32_t)0x00000001U)
#define | DMA2D_INPUT_RGB565 ((uint32_t)0x00000002U)
#define | DMA2D_INPUT_ARGB1555 ((uint32_t)0x00000003U)
#define | DMA2D_INPUT_ARGB4444 ((uint32_t)0x00000004U)
#define | DMA2D_INPUT_L8 ((uint32_t)0x00000005U)
#define | DMA2D_INPUT_AL44 ((uint32_t)0x00000006U)
#define | DMA2D_INPUT_AL88 ((uint32_t)0x00000007U)
#define | DMA2D_INPUT_L4 ((uint32_t)0x00000008U)
#define | DMA2D_INPUT_A8 ((uint32_t)0x00000009U)
#define | DMA2D_INPUT_A4 ((uint32_t)0x0000000AU)
#define | DMA2D_INPUT_YCBCR ((uint32_t)0x0000000BU)

Define Documentation

#define DMA2D_INPUT_A4 ((uint32_t)0x0000000AU)

A4 color mode

Definition at line 240 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

#define DMA2D_INPUT_A8 ((uint32_t)0x00000009U)

A8 color mode

Definition at line 239 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

#define DMA2D_INPUT_AL44 ((uint32_t)0x00000006U)

AL44 color mode

Definition at line 236 of file stm32h7xx_hal_dma2d.h.

#define DMA2D_INPUT_AL88 ((uint32_t)0x00000007U)

AL88 color mode

Definition at line 237 of file stm32h7xx_hal_dma2d.h.

#define DMA2D_INPUT_ARGB1555 ((uint32_t)0x00000003U)

ARGB1555 color mode

Definition at line 233 of file stm32h7xx_hal_dma2d.h.

#define DMA2D_INPUT_ARGB4444 ((uint32_t)0x00000004U)

ARGB4444 color mode

Definition at line 234 of file stm32h7xx_hal_dma2d.h.

#define DMA2D_INPUT_ARGB8888 ((uint32_t)0x00000000U)

ARGB8888 color mode

Definition at line 230 of file stm32h7xx_hal_dma2d.h.

#define DMA2D_INPUT_L4 ((uint32_t)0x00000008U)

L4 color mode

Definition at line 238 of file stm32h7xx_hal_dma2d.h.

#define DMA2D_INPUT_L8 ((uint32_t)0x00000005U)

L8 color mode

Definition at line 235 of file stm32h7xx_hal_dma2d.h.

#define DMA2D_INPUT_RGB565 ((uint32_t)0x00000002U)

RGB565 color mode

Definition at line 232 of file stm32h7xx_hal_dma2d.h.

#define DMA2D_INPUT_RGB888 ((uint32_t)0x00000001U)

RGB888 color mode

Definition at line 231 of file stm32h7xx_hal_dma2d.h.

#define DMA2D_INPUT_YCBCR ((uint32_t)0x0000000BU)

YCbCr color mode

Definition at line 241 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

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STM32H753xx HAL User Manual: DMA2D Alpha Mode

Defines
DMA2D Alpha Mode
DMA2D Exported Constants

Defines

#define | DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000U)
#define | DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001U)
#define | DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002U)

Define Documentation

#define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002U)

Replace original alpha channel value by programmed alpha value with original alpha channel value

Definition at line 251 of file stm32h7xx_hal_dma2d.h.

#define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000U)

No modification of the alpha channel value

Definition at line 249 of file stm32h7xx_hal_dma2d.h.

#define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001U)

Replace original alpha channel value by programmed alpha value

Definition at line 250 of file stm32h7xx_hal_dma2d.h.

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STM32H753xx HAL User Manual: DMA2D ALPHA Inversion

Defines
DMA2D ALPHA Inversion
DMA2D Exported Constants

Defines

#define | DMA2D_REGULAR_ALPHA ((uint32_t)0x00000000U)
#define | DMA2D_INVERTED_ALPHA ((uint32_t)0x00000001U)

Define Documentation

#define DMA2D_INVERTED_ALPHA ((uint32_t)0x00000001U)

Invert the alpha channel value

Definition at line 262 of file stm32h7xx_hal_dma2d.h.

#define DMA2D_REGULAR_ALPHA ((uint32_t)0x00000000U)

No modification of the alpha channel value

Definition at line 261 of file stm32h7xx_hal_dma2d.h.

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STM32H753xx HAL User Manual: DMA2D Red and Blue Swap

Defines
DMA2D Red and Blue Swap
DMA2D Exported Constants

Defines

#define | DMA2D_RB_REGULAR ((uint32_t)0x00000000U)
#define | DMA2D_RB_SWAP ((uint32_t)0x00000001U)

Define Documentation

#define DMA2D_RB_REGULAR ((uint32_t)0x00000000U)

Select regular mode (RGB or ARGB)

Definition at line 271 of file stm32h7xx_hal_dma2d.h.

#define DMA2D_RB_SWAP ((uint32_t)0x00000001U)

Select swap mode (BGR or ABGR)

Definition at line 272 of file stm32h7xx_hal_dma2d.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA2D Chroma Sub Sampling

Defines
DMA2D Chroma Sub Sampling
DMA2D Exported Constants

Defines

#define | DMA2D_NO_CSS ((uint32_t)0x00000000)
#define | DMA2D_CSS_422 ((uint32_t)0x00000001)
#define | DMA2D_CSS_420 ((uint32_t)0x00000002)

Define Documentation

#define DMA2D_CSS_420 ((uint32_t)0x00000002)

chroma sub-sampling 4:2:0

Definition at line 282 of file stm32h7xx_hal_dma2d.h.

#define DMA2D_CSS_422 ((uint32_t)0x00000001)

chroma sub-sampling 4:2:2

Definition at line 281 of file stm32h7xx_hal_dma2d.h.

#define DMA2D_NO_CSS ((uint32_t)0x00000000)

No chroma sub-sampling 4:4:4

Definition at line 280 of file stm32h7xx_hal_dma2d.h.

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STM32H753xx HAL User Manual: DMA2D CLUT Color Mode

Defines
DMA2D CLUT Color Mode
DMA2D Exported Constants

Defines

#define | DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000U)
#define | DMA2D_CCM_RGB888 ((uint32_t)0x00000001U)

Define Documentation

#define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000U)

ARGB8888 DMA2D CLUT color mode

Definition at line 291 of file stm32h7xx_hal_dma2d.h.

#define DMA2D_CCM_RGB888 ((uint32_t)0x00000001U)

RGB888 DMA2D CLUT color mode

Definition at line 292 of file stm32h7xx_hal_dma2d.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA2D Interrupts

Defines
DMA2D Interrupts
DMA2D Exported Constants

Defines

#define | DMA2D_IT_CE DMA2D_CR_CEIE
#define | DMA2D_IT_CTC DMA2D_CR_CTCIE
#define | DMA2D_IT_CAE DMA2D_CR_CAEIE
#define | DMA2D_IT_TW DMA2D_CR_TWIE
#define | DMA2D_IT_TC DMA2D_CR_TCIE
#define | DMA2D_IT_TE DMA2D_CR_TEIE

Define Documentation

#define DMA2D_IT_CAE DMA2D_CR_CAEIE

CLUT Access Error Interrupt

Definition at line 303 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_CLUTLoad_IT(), HAL_DMA2D_CLUTLoading_Abort(), and HAL_DMA2D_IRQHandler().

#define DMA2D_IT_CE DMA2D_CR_CEIE

Configuration Error Interrupt

Definition at line 301 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_Abort(), HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_CLUTLoad_IT(), HAL_DMA2D_CLUTLoading_Abort(), HAL_DMA2D_IRQHandler(), and HAL_DMA2D_Start_IT().

#define DMA2D_IT_CTC DMA2D_CR_CTCIE

CLUT Transfer Complete Interrupt

Definition at line 302 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_CLUTLoad_IT(), HAL_DMA2D_CLUTLoading_Abort(), and HAL_DMA2D_IRQHandler().

#define DMA2D_IT_TC DMA2D_CR_TCIE

Transfer Complete Interrupt

Definition at line 305 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_Abort(), HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_IRQHandler(), and HAL_DMA2D_Start_IT().

#define DMA2D_IT_TE DMA2D_CR_TEIE

Transfer Error Interrupt

Definition at line 306 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_Abort(), HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_CLUTLoad_IT(), HAL_DMA2D_CLUTLoading_Abort(), HAL_DMA2D_IRQHandler(), and HAL_DMA2D_Start_IT().

#define DMA2D_IT_TW DMA2D_CR_TWIE

Transfer Watermark Interrupt

Definition at line 304 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler(), and HAL_DMA2D_ProgramLineEvent().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA2D Flags

Defines
DMA2D Flags
DMA2D Exported Constants

Defines

#define | DMA2D_FLAG_CE DMA2D_ISR_CEIF
#define | DMA2D_FLAG_CTC DMA2D_ISR_CTCIF
#define | DMA2D_FLAG_CAE DMA2D_ISR_CAEIF
#define | DMA2D_FLAG_TW DMA2D_ISR_TWIF
#define | DMA2D_FLAG_TC DMA2D_ISR_TCIF
#define | DMA2D_FLAG_TE DMA2D_ISR_TEIF

Define Documentation

#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF

CLUT Access Error Interrupt Flag

Definition at line 316 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler(), and HAL_DMA2D_PollForTransfer().

#define DMA2D_FLAG_CE DMA2D_ISR_CEIF

Configuration Error Interrupt Flag

Definition at line 314 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler(), and HAL_DMA2D_PollForTransfer().

#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF

CLUT Transfer Complete Interrupt Flag

Definition at line 315 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler(), and HAL_DMA2D_PollForTransfer().

#define DMA2D_FLAG_TC DMA2D_ISR_TCIF

Transfer Complete Interrupt Flag

Definition at line 318 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler(), and HAL_DMA2D_PollForTransfer().

#define DMA2D_FLAG_TE DMA2D_ISR_TEIF

Transfer Error Interrupt Flag

Definition at line 319 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler(), and HAL_DMA2D_PollForTransfer().

#define DMA2D_FLAG_TW DMA2D_ISR_TWIF

Transfer Watermark Interrupt Flag

Definition at line 317 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA2D API Aliases

Defines
DMA2D API Aliases
DMA2D Exported Constants

Defines

#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort

Define Documentation

#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort

Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code

Definition at line 327 of file stm32h7xx_hal_dma2d.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA2D Exported Macros

Defines
DMA2D Exported Macros
DMA2D

Defines

#define | __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
Reset DMA2D handle state.
#define | __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
Enable the DMA2D.
#define | __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
Get the DMA2D pending flags.
#define | __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
Clear the DMA2D pending flags.
#define | __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the specified DMA2D interrupts.
#define | __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the specified DMA2D interrupts.
#define | __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
Check whether the specified DMA2D interrupt source is enabled or not.

Define Documentation

#define __HAL_DMA2D_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->IFCR = (__FLAG__))

Clear the DMA2D pending flags.

Parameters:
__HANDLE__,: DMA2D handle
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • DMA2D_FLAG_CE: Configuration error flag
  • DMA2D_FLAG_CTC: CLUT transfer complete flag
  • DMA2D_FLAG_CAE: CLUT access error flag
  • DMA2D_FLAG_TW: Transfer Watermark flag
  • DMA2D_FLAG_TC: Transfer complete flag
  • DMA2D_FLAG_TE: Transfer error flag
Return values:
None

Definition at line 384 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler(), and HAL_DMA2D_PollForTransfer().

#define __HAL_DMA2D_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the specified DMA2D interrupts.

Parameters:
__HANDLE__,: DMA2D handle
__INTERRUPT__,: specifies the DMA2D interrupt sources to be disabled. This parameter can be any combination of the following values:
  • DMA2D_IT_CE: Configuration error interrupt mask
  • DMA2D_IT_CTC: CLUT transfer complete interrupt mask
  • DMA2D_IT_CAE: CLUT access error interrupt mask
  • DMA2D_IT_TW: Transfer Watermark interrupt mask
  • DMA2D_IT_TC: Transfer complete interrupt mask
  • DMA2D_IT_TE: Transfer error interrupt mask
Return values:
None

Definition at line 414 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_Abort(), HAL_DMA2D_CLUTLoading_Abort(), and HAL_DMA2D_IRQHandler().

#define __HAL_DMA2D_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)

Enable the DMA2D.

Parameters:
__HANDLE__,: DMA2D handle
Return values:
None.

Definition at line 352 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_BlendingStart(), HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_Start(), and HAL_DMA2D_Start_IT().

#define __HAL_DMA2D_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the specified DMA2D interrupts.

Parameters:
__HANDLE__,: DMA2D handle
__INTERRUPT__,: specifies the DMA2D interrupt sources to be enabled. This parameter can be any combination of the following values:
  • DMA2D_IT_CE: Configuration error interrupt mask
  • DMA2D_IT_CTC: CLUT transfer complete interrupt mask
  • DMA2D_IT_CAE: CLUT access error interrupt mask
  • DMA2D_IT_TW: Transfer Watermark interrupt mask
  • DMA2D_IT_TC: Transfer complete interrupt mask
  • DMA2D_IT_TE: Transfer error interrupt mask
Return values:
None

Definition at line 399 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_CLUTLoad_IT(), HAL_DMA2D_ProgramLineEvent(), and HAL_DMA2D_Start_IT().

#define __HAL_DMA2D_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR & (__FLAG__))

Get the DMA2D pending flags.

Parameters:
__HANDLE__,: DMA2D handle
__FLAG__,: flag to check. This parameter can be any combination of the following values:
  • DMA2D_FLAG_CE: Configuration error flag
  • DMA2D_FLAG_CTC: CLUT transfer complete flag
  • DMA2D_FLAG_CAE: CLUT access error flag
  • DMA2D_FLAG_TW: Transfer Watermark flag
  • DMA2D_FLAG_TC: Transfer complete flag
  • DMA2D_FLAG_TE: Transfer error flag
Return values:
The state of FLAG.

Definition at line 369 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_PollForTransfer().

#define __HAL_DMA2D_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR & (__INTERRUPT__))

Check whether the specified DMA2D interrupt source is enabled or not.

Parameters:
__HANDLE__,: DMA2D handle
__INTERRUPT__,: specifies the DMA2D interrupt source to check. This parameter can be one of the following values:
  • DMA2D_IT_CE: Configuration error interrupt mask
  • DMA2D_IT_CTC: CLUT transfer complete interrupt mask
  • DMA2D_IT_CAE: CLUT access error interrupt mask
  • DMA2D_IT_TW: Transfer Watermark interrupt mask
  • DMA2D_IT_TC: Transfer complete interrupt mask
  • DMA2D_IT_TE: Transfer error interrupt mask
Return values:
The state of INTERRUPT source.

Definition at line 429 of file stm32h7xx_hal_dma2d.h.

#define __HAL_DMA2D_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)

Reset DMA2D handle state.

Parameters:
__HANDLE__,: specifies the DMA2D handle.
Return values:
None

Definition at line 345 of file stm32h7xx_hal_dma2d.h.

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STM32H753xx HAL User Manual: DMA2D Private Macros

Defines
DMA2D Private Macros
DMA2D

Defines

#define | IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
#define | IS_DMA2D_MODE(MODE)
#define | IS_DMA2D_CMODE(MODE_ARGB)
#define | IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
#define | IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
#define | IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
#define | IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
#define | IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM)
#define | IS_DMA2D_ALPHA_MODE(AlphaMode)
#define | IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted)
#define | IS_DMA2D_RB_SWAP(RB_Swap)
#define | IS_DMA2D_CHROMA_SUB_SAMPLING
#define | IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
#define | IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
#define | IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
#define | IS_DMA2D_IT(IT)
#define | IS_DMA2D_GET_FLAG(FLAG)

Define Documentation

#define IS_DMA2D_ALPHA_INVERTED ( Alpha_Inverted )
Value:
(((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
                                                 ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))

Definition at line 590 of file stm32h7xx_hal_dma2d.h.

#define IS_DMA2D_ALPHA_MODE ( AlphaMode )
Value:
(((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
                                               ((AlphaMode) == DMA2D_REPLACE_ALPHA)  || \
                                               ((AlphaMode) == DMA2D_COMBINE_ALPHA))

Definition at line 586 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

#define IS_DMA2D_CHROMA_SUB_SAMPLING
Value:
(CSS) (((CSS) == DMA2D_NO_CSS) || \
                                            ((CSS) == DMA2D_CSS_422) || \
                                            ((CSS) == DMA2D_CSS_420))

Definition at line 596 of file stm32h7xx_hal_dma2d.h.

#define IS_DMA2D_CLUT_CM ( CLUT_CM ) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))

Definition at line 600 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_CLUTLoad(), HAL_DMA2D_CLUTLoad_IT(), and HAL_DMA2D_ConfigCLUT().

#define IS_DMA2D_CLUT_SIZE ( CLUT_SIZE ) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)

Definition at line 601 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_CLUTLoad(), HAL_DMA2D_CLUTLoad_IT(), and HAL_DMA2D_ConfigCLUT().

#define IS_DMA2D_CMODE ( MODE_ARGB )
Value:
(((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888)   || \
                                               ((MODE_ARGB) == DMA2D_OUTPUT_RGB565)   || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
                                               ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))

Definition at line 573 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_Init().

#define IS_DMA2D_COLOR ( COLOR ) ((COLOR) <= DMA2D_COLOR_VALUE)

Definition at line 576 of file stm32h7xx_hal_dma2d.h.

#define IS_DMA2D_GET_FLAG ( FLAG )
Value:
(((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
                                               ((FLAG) == DMA2D_FLAG_TW)   || ((FLAG) == DMA2D_FLAG_TC)  || \
                                               ((FLAG) == DMA2D_FLAG_TE)   || ((FLAG) == DMA2D_FLAG_CE))

Definition at line 606 of file stm32h7xx_hal_dma2d.h.

#define IS_DMA2D_INPUT_COLOR_MODE ( INPUT_CM )
Value:
(((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888)   || \
                                               ((INPUT_CM) == DMA2D_INPUT_RGB565)   || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
                                               ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8)       || \
                                               ((INPUT_CM) == DMA2D_INPUT_AL44)     || ((INPUT_CM) == DMA2D_INPUT_AL88)     || \
                                               ((INPUT_CM) == DMA2D_INPUT_L4)       || ((INPUT_CM) == DMA2D_INPUT_A8)       || \
                                               ((INPUT_CM) == DMA2D_INPUT_A4)       || ((INPUT_CM) == DMA2D_INPUT_YCBCR))

Definition at line 580 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

#define IS_DMA2D_IT ( IT )
Value:
(((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
                                               ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
                                               ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))

Definition at line 603 of file stm32h7xx_hal_dma2d.h.

#define IS_DMA2D_LAYER ( LAYER ) ((LAYER) <= MAX_DMA2D_LAYER)

Definition at line 570 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_CLUTLoad(), HAL_DMA2D_CLUTLoad_IT(), HAL_DMA2D_ConfigCLUT(), HAL_DMA2D_ConfigLayer(), and HAL_DMA2D_EnableCLUT().

#define IS_DMA2D_LINE ( LINE ) ((LINE) <= DMA2D_LINE)

Definition at line 577 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_BlendingStart(), HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_Start(), and HAL_DMA2D_Start_IT().

#define IS_DMA2D_LINEWATERMARK ( LineWatermark ) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)

Definition at line 602 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ProgramLineEvent().

#define IS_DMA2D_MODE ( MODE )
Value:
(((MODE) == DMA2D_M2M)       || ((MODE) == DMA2D_M2M_PFC) || \
                                               ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))

Definition at line 571 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_Init().

#define IS_DMA2D_OFFSET ( OOFFSET ) ((OOFFSET) <= DMA2D_OFFSET)

Definition at line 579 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer(), and HAL_DMA2D_Init().

#define IS_DMA2D_PIXEL ( PIXEL ) ((PIXEL) <= DMA2D_PIXEL)

Definition at line 578 of file stm32h7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_BlendingStart(), HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_Start(), and HAL_DMA2D_Start_IT().

#define IS_DMA2D_RB_SWAP ( RB_Swap )
Value:
(((RB_Swap) == DMA2D_RB_REGULAR) || \
                                   ((RB_Swap) == DMA2D_RB_SWAP))

Definition at line 593 of file stm32h7xx_hal_dma2d.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA2D_Private_Functions_Prototypes

DMA2D_Private_Functions_Prototypes
DMA2D
Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMAEx Exported Types

Data Structures | Enumerations
DMAEx Exported Types
DMAEx

DMAEx Exported types. More...

Data Structures

struct | HAL_DMA_MuxSyncConfigTypeDef
HAL DMAMUX Synchronization configuration structure definition. More...
struct | HAL_DMA_MuxRequestGeneratorConfigTypeDef
HAL DMAMUX request generator parameters structure definition. More...

Enumerations

enum | HAL_DMA_MemoryTypeDef { MEMORY0 = 0x00U, MEMORY1 = 0x01U }
HAL DMA Memory definition. More...

Detailed Description

DMAEx Exported types.

Enumeration Type Documentation

enum HAL_DMA_MemoryTypeDef

HAL DMA Memory definition.

Enumerator:
MEMORY0

Memory 0

MEMORY1

Memory 1

Definition at line 66 of file stm32h7xx_hal_dma_ex.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HAL_DMA_MuxSyncConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_DMA_MuxSyncConfigTypeDef Struct Reference
DMAEx Exported Types

HAL DMAMUX Synchronization configuration structure definition. More...

#include <stm32h7xx_hal_dma_ex.h>

Data Fields

uint32_t | SyncSignalID
uint32_t | SyncPolarity
FunctionalState | SyncEnable
FunctionalState | EventEnable
uint32_t | RequestNumber

Detailed Description

HAL DMAMUX Synchronization configuration structure definition.

Definition at line 76 of file stm32h7xx_hal_dma_ex.h.

Field Documentation

FunctionalState HAL_DMA_MuxSyncConfigTypeDef::EventEnable

Specifies if an event shall be generated once the RequestNumber is reached. This parameter can take the value ENABLE or DISABLE

Definition at line 88 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

uint32_t HAL_DMA_MuxSyncConfigTypeDef::RequestNumber

Specifies the number of DMA request that will be authorized after a sync event

Definition at line 91 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

FunctionalState HAL_DMA_MuxSyncConfigTypeDef::SyncEnable

Specifies if the synchronization shall be enabled or disabled This parameter can take the value ENABLE or DISABLE

Definition at line 84 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

uint32_t HAL_DMA_MuxSyncConfigTypeDef::SyncPolarity

Specifies the polarity of the signal on which the DMA request is synchronized. This parameter can be a value of DMAEx MUX SyncPolarity selection

Definition at line 81 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

uint32_t HAL_DMA_MuxSyncConfigTypeDef::SyncSignalID

Specifies the synchronization signal gating the DMA request in periodic mode. This parameter can be a value of DMAEx MUX SyncSignalID selection

Definition at line 78 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dma_ex.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HAL_DMA_MuxRequestGeneratorConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_DMA_MuxRequestGeneratorConfigTypeDef Struct Reference
DMAEx Exported Types

HAL DMAMUX request generator parameters structure definition. More...

#include <stm32h7xx_hal_dma_ex.h>

Data Fields

uint32_t | SignalID
uint32_t | Polarity
uint32_t | RequestNumber

Detailed Description

HAL DMAMUX request generator parameters structure definition.

Definition at line 99 of file stm32h7xx_hal_dma_ex.h.

Field Documentation

uint32_t HAL_DMA_MuxRequestGeneratorConfigTypeDef::Polarity

Specifies the polarity of the signal on which the request is generated. This parameter can be a value of DMAEx MUX RequestGeneneratorPolarity selection

Definition at line 104 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

uint32_t HAL_DMA_MuxRequestGeneratorConfigTypeDef::RequestNumber

Specifies the number of DMA request that will be generated after a signal event

Definition at line 107 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

uint32_t HAL_DMA_MuxRequestGeneratorConfigTypeDef::SignalID

Specifies the ID of the signal used for DMAMUX request generator This parameter can be a value of DMAEx MUX SignalGeneratorID selection

Definition at line 101 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_dma_ex.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMAEx MUX SyncSignalID selection

Defines
DMAEx MUX SyncSignalID selection
DMA Exported Constants

DMAEx MUX SyncSignalID selection. More...

Defines

#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT ((uint32_t)0x00000000)
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT ((uint32_t)0x01000000)
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT ((uint32_t)0x02000000)
#define | HAL_DMAMUX1_SYNC_LPTIM1_OUT ((uint32_t)0x03000000)
#define | HAL_DMAMUX1_SYNC_LPTIM2_OUT ((uint32_t)0x04000000)
#define | HAL_DMAMUX1_SYNC_LPTIM3_OUT ((uint32_t)0x05000000)
#define | HAL_DMAMUX1_SYNC_EXTI0 ((uint32_t)0x06000000)
#define | HAL_DMAMUX1_SYNC_TIM12_TRGO ((uint32_t)0x07000000)
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT ((uint32_t)0x00000000)
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT ((uint32_t)0x01000000)
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT ((uint32_t)0x02000000)
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT ((uint32_t)0x03000000)
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT ((uint32_t)0x04000000)
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT ((uint32_t)0x05000000)
#define | HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP ((uint32_t)0x06000000)
#define | HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP ((uint32_t)0x07000000)
#define | HAL_DMAMUX2_SYNC_LPTIM2_OUT ((uint32_t)0x08000000)
#define | HAL_DMAMUX2_SYNC_LPTIM3_OUT ((uint32_t)0x09000000)
#define | HAL_DMAMUX2_SYNC_I2C4_WKUP ((uint32_t)0x0A000000)
#define | HAL_DMAMUX2_SYNC_SPI6_WKUP ((uint32_t)0x0B000000)
#define | HAL_DMAMUX2_SYNC_COMP1_OUT ((uint32_t)0x0C000000)
#define | HAL_DMAMUX2_SYNC_RTC_WKUP ((uint32_t)0x0D000000)
#define | HAL_DMAMUX2_SYNC_EXTI0 ((uint32_t)0x0E000000)
#define | HAL_DMAMUX2_SYNC_EXTI2 ((uint32_t)0x0F000000)

Detailed Description

DMAEx MUX SyncSignalID selection.

Define Documentation

#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT ((uint32_t)0x00000000)

D2 Domain synchronization Signal is DMAMUX1 Channel0 Event

Definition at line 126 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT ((uint32_t)0x01000000)

D2 Domain synchronization Signal is DMAMUX1 Channel1 Event

Definition at line 127 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT ((uint32_t)0x02000000)

D2 Domain synchronization Signal is DMAMUX1 Channel2 Event

Definition at line 128 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI0 ((uint32_t)0x06000000)

D2 Domain synchronization Signal is EXTI0 IT

Definition at line 132 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_LPTIM1_OUT ((uint32_t)0x03000000)

D2 Domain synchronization Signal is LPTIM1 OUT

Definition at line 129 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_LPTIM2_OUT ((uint32_t)0x04000000)

D2 Domain synchronization Signal is LPTIM2 OUT

Definition at line 130 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_LPTIM3_OUT ((uint32_t)0x05000000)

D2 Domain synchronization Signal is LPTIM3 OUT

Definition at line 131 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_TIM12_TRGO ((uint32_t)0x07000000)

D2 Domain synchronization Signal is TIM12 TRGO

Definition at line 133 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_COMP1_OUT ((uint32_t)0x0C000000)

D3 Domain synchronization Signal is Comparator 1 output

Definition at line 147 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT ((uint32_t)0x00000000)

D3 Domain synchronization Signal is DMAMUX2 Channel0 Event

Definition at line 135 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT ((uint32_t)0x01000000)

D3 Domain synchronization Signal is DMAMUX2 Channel1 Event

Definition at line 136 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT ((uint32_t)0x02000000)

D3 Domain synchronization Signal is DMAMUX2 Channel2 Event

Definition at line 137 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT ((uint32_t)0x03000000)

D3 Domain synchronization Signal is DMAMUX2 Channel3 Event

Definition at line 138 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT ((uint32_t)0x04000000)

D3 Domain synchronization Signal is DMAMUX2 Channel4 Event

Definition at line 139 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT ((uint32_t)0x05000000)

D3 Domain synchronization Signal is DMAMUX2 Channel5 Event

Definition at line 140 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_EXTI0 ((uint32_t)0x0E000000)

D3 Domain synchronization Signal is EXTI0 IT

Definition at line 149 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_EXTI2 ((uint32_t)0x0F000000)

D3 Domain synchronization Signal is EXTI2 IT

Definition at line 150 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_I2C4_WKUP ((uint32_t)0x0A000000)

D3 Domain synchronization Signal is I2C4 Wakeup

Definition at line 145 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_LPTIM2_OUT ((uint32_t)0x08000000)

D3 Domain synchronization Signal is LPTIM2 output

Definition at line 143 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_LPTIM3_OUT ((uint32_t)0x09000000)

D3 Domain synchronization Signal is LPTIM3 output

Definition at line 144 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP ((uint32_t)0x06000000)

D3 Domain synchronization Signal is LPUART1 RX Wakeup

Definition at line 141 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP ((uint32_t)0x07000000)

D3 Domain synchronization Signal is LPUART1 TX Wakeup

Definition at line 142 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_RTC_WKUP ((uint32_t)0x0D000000)

D3 Domain synchronization Signal is RTC Wakeup

Definition at line 148 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_SYNC_SPI6_WKUP ((uint32_t)0x0B000000)

D3 Domain synchronization Signal is SPI6 Wakeup

Definition at line 146 of file stm32h7xx_hal_dma_ex.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMAEx MUX SyncPolarity selection

Defines
DMAEx MUX SyncPolarity selection
DMA Exported Constants

DMAEx MUX SyncPolarity selection. More...

Defines

#define | HAL_DMAMUX_SYNC_NO_EVENT ((uint32_t)0x00000000)
#define | HAL_DMAMUX_SYNC_RISING ((uint32_t)DMAMUX_CxCR_SPOL_0)
#define | HAL_DMAMUX_SYNC_FALLING ((uint32_t)DMAMUX_CxCR_SPOL_1)
#define | HAL_DMAMUX_SYNC_RISING_FALLING ((uint32_t)DMAMUX_CxCR_SPOL)

Detailed Description

DMAEx MUX SyncPolarity selection.

Define Documentation

#define HAL_DMAMUX_SYNC_FALLING ((uint32_t)DMAMUX_CxCR_SPOL_1)

synchronize with falling edge events

Definition at line 162 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX_SYNC_NO_EVENT ((uint32_t)0x00000000)

block synchronization events

Definition at line 160 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX_SYNC_RISING ((uint32_t)DMAMUX_CxCR_SPOL_0)

synchronize with rising edge events

Definition at line 161 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX_SYNC_RISING_FALLING ((uint32_t)DMAMUX_CxCR_SPOL)

synchronize with rising and falling edge events

Definition at line 163 of file stm32h7xx_hal_dma_ex.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMAEx MUX SignalGeneratorID selection

Defines
DMAEx MUX SignalGeneratorID selection
DMA Exported Constants

DMAEx MUX SignalGeneratorID selection. More...

Defines

#define | HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT ((uint32_t)0x00000000)
#define | HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT ((uint32_t)0x00000001)
#define | HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT ((uint32_t)0x00000002)
#define | HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT ((uint32_t)0x00000003)
#define | HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT ((uint32_t)0x00000004)
#define | HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT ((uint32_t)0x00000005)
#define | HAL_DMAMUX1_REQUEST_GEN_EXTI0 ((uint32_t)0x00000006)
#define | HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO ((uint32_t)0x00000007)
#define | HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT ((uint32_t)0x00000000)
#define | HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT ((uint32_t)0x00000001)
#define | HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT ((uint32_t)0x00000002)
#define | HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT ((uint32_t)0x00000003)
#define | HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT ((uint32_t)0x00000004)
#define | HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT ((uint32_t)0x00000005)
#define | HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT ((uint32_t)0x00000006)
#define | HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP ((uint32_t)0x00000007)
#define | HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP ((uint32_t)0x00000008)
#define | HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP ((uint32_t)0x00000009)
#define | HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT ((uint32_t)0x0000000A)
#define | HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP ((uint32_t)0x0000000B)
#define | HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT ((uint32_t)0x0000000C)
#define | HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP ((uint32_t)0x0000000D)
#define | HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP ((uint32_t)0x0000000E)
#define | HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP ((uint32_t)0x0000000F)
#define | HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP ((uint32_t)0x00000010)
#define | HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT ((uint32_t)0x00000011)
#define | HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT ((uint32_t)0x00000012)
#define | HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP ((uint32_t)0x00000013)
#define | HAL_DMAMUX2_REQUEST_GEN_EXTI0 ((uint32_t)0x00000014)
#define | HAL_DMAMUX2_REQUEST_GEN_EXTI2 ((uint32_t)0x00000015)
#define | HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT ((uint32_t)0x00000016)
#define | HAL_DMAMUX2_REQUEST_GEN_SPI6_IT ((uint32_t)0x00000017)
#define | HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT ((uint32_t)0x00000018)
#define | HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT ((uint32_t)0x00000019)
#define | HAL_DMAMUX2_REQUEST_GEN_ADC3_IT ((uint32_t)0x0000001A)
#define | HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT ((uint32_t)0x0000001B)
#define | HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT ((uint32_t)0x0000001C)
#define | HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT ((uint32_t)0x0000001D)

Detailed Description

DMAEx MUX SignalGeneratorID selection.

Define Documentation

#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT ((uint32_t)0x00000000)

D2 domain Request generator Signal is DMAMUX1 Channel0 Event

Definition at line 174 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT ((uint32_t)0x00000001)

D2 domain Request generator Signal is DMAMUX1 Channel1 Event

Definition at line 175 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT ((uint32_t)0x00000002)

D2 domain Request generator Signal is DMAMUX1 Channel2 Event

Definition at line 176 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 ((uint32_t)0x00000006)

D2 domain Request generator Signal is EXTI0 IT

Definition at line 180 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT ((uint32_t)0x00000003)

D2 domain Request generator Signal is LPTIM1 OUT

Definition at line 177 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT ((uint32_t)0x00000004)

D2 domain Request generator Signal is LPTIM2 OUT

Definition at line 178 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT ((uint32_t)0x00000005)

D2 domain Request generator Signal is LPTIM3 OUT

Definition at line 179 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO ((uint32_t)0x00000007)

D2 domain Request generator Signal is TIM12 TRGO

Definition at line 181 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT ((uint32_t)0x0000001B)

D3 domain Request generator Signal is ADC3 Analog Watchdog 1 output

Definition at line 210 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT ((uint32_t)0x0000001A)

D3 domain Request generator Signal is ADC3 IT

Definition at line 209 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT ((uint32_t)0x0000001C)

D3 domain Request generator Signal is BDMA Channel 0 IT

Definition at line 211 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT ((uint32_t)0x0000001D)

D3 domain Request generator Signal is BDMA Channel 1 IT

Definition at line 212 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT ((uint32_t)0x00000011)

D3 domain Request generator Signal is Comparator 1 output

Definition at line 200 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT ((uint32_t)0x00000012)

D3 domain Request generator Signal is Comparator 2 output

Definition at line 201 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT ((uint32_t)0x00000000)

D3 domain Request generator Signal is DMAMUX2 Channel0 Event

Definition at line 183 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT ((uint32_t)0x00000001)

D3 domain Request generator Signal is DMAMUX2 Channel1 Event

Definition at line 184 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT ((uint32_t)0x00000002)

D3 domain Request generator Signal is DMAMUX2 Channel2 Event

Definition at line 185 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT ((uint32_t)0x00000003)

D3 domain Request generator Signal is DMAMUX2 Channel3 Event

Definition at line 186 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT ((uint32_t)0x00000004)

D3 domain Request generator Signal is DMAMUX2 Channel4 Event

Definition at line 187 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT ((uint32_t)0x00000005)

D3 domain Request generator Signal is DMAMUX2 Channel5 Event

Definition at line 188 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT ((uint32_t)0x00000006)

D3 domain Request generator Signal is DMAMUX2 Channel6 Event

Definition at line 189 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 ((uint32_t)0x00000014)

D3 domain Request generator Signal is EXTI0

Definition at line 203 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 ((uint32_t)0x00000015)

D3 domain Request generator Signal is EXTI2

Definition at line 204 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT ((uint32_t)0x00000016)

D3 domain Request generator Signal is I2C4 IT Event

Definition at line 205 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP ((uint32_t)0x0000000F)

D3 domain Request generator Signal is I2C4 Wakeup

Definition at line 198 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT ((uint32_t)0x0000000A)

D3 domain Request generator Signal is LPTIM2 OUT

Definition at line 193 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP ((uint32_t)0x00000009)

D3 domain Request generator Signal is LPTIM2 Wakeup

Definition at line 192 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT ((uint32_t)0x0000000C)

D3 domain Request generator Signal is LPTIM3 OUT

Definition at line 195 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP ((uint32_t)0x0000000B)

D3 domain Request generator Signal is LPTIM3 Wakeup

Definition at line 194 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP ((uint32_t)0x0000000D)

D3 domain Request generator Signal is LPTIM4 Wakeup

Definition at line 196 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP ((uint32_t)0x0000000E)

D3 domain Request generator Signal is LPTIM5 Wakeup

Definition at line 197 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT ((uint32_t)0x00000019)

D3 domain Request generator Signal is LPUART1 Rx IT

Definition at line 208 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP ((uint32_t)0x00000007)

D3 domain Request generator Signal is LPUART1 RX Wakeup

Definition at line 190 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT ((uint32_t)0x00000018)

D3 domain Request generator Signal is LPUART1 Tx IT

Definition at line 207 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP ((uint32_t)0x00000008)

D3 domain Request generator Signal is LPUART1 TX Wakeup

Definition at line 191 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP ((uint32_t)0x00000013)

D3 domain Request generator Signal is RTC Wakeup

Definition at line 202 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT ((uint32_t)0x00000017)

D3 domain Request generator Signal is SPI6 IT

Definition at line 206 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP ((uint32_t)0x00000010)

D3 domain Request generator Signal is SPI6 Wakeup

Definition at line 199 of file stm32h7xx_hal_dma_ex.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMAEx MUX RequestGeneneratorPolarity selection

Defines
DMAEx MUX RequestGeneneratorPolarity selection
DMA Exported Constants

DMAEx MUX RequestGeneneratorPolarity selection. More...

Defines

#define | HAL_DMAMUX_REQUEST_GEN_NO_EVENT ((uint32_t)0x00000000)
#define | HAL_DMAMUX_REQUEST_GEN_RISING ((uint32_t)DMAMUX_RGxCR_GPOL_0)
#define | HAL_DMAMUX_REQUEST_GEN_FALLING ((uint32_t)DMAMUX_RGxCR_GPOL_1)
#define | HAL_DMAMUX_REQUEST_GEN_RISING_FALLING ((uint32_t)DMAMUX_RGxCR_GPOL)

Detailed Description

DMAEx MUX RequestGeneneratorPolarity selection.

Define Documentation

#define HAL_DMAMUX_REQUEST_GEN_FALLING ((uint32_t)DMAMUX_RGxCR_GPOL_1)

generate request on falling edge events

Definition at line 225 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT ((uint32_t)0x00000000)

block request generator events

Definition at line 223 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX_REQUEST_GEN_RISING ((uint32_t)DMAMUX_RGxCR_GPOL_0)

generate request on rising edge events

Definition at line 224 of file stm32h7xx_hal_dma_ex.h.

#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING ((uint32_t)DMAMUX_RGxCR_GPOL)

generate request on rising and falling edge events

Definition at line 226 of file stm32h7xx_hal_dma_ex.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Extended features functions

Functions
Extended features functions
DMAEx Exported Functions

Extended features functions. More...

Functions

HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer.
HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMAEx_ChangeMemory (DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
Change the memory0 or memory1 address on the fly.
HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxSync (DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
Configure the DMAMUX synchronization parameters for a given DMA stream (instance).
HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
Configure the DMAMUX request generator block used by the given DMA stream (instance).
HAL_StatusTypeDef | HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Enable the DMAMUX request generator block used by the given DMA stream (instance).
HAL_StatusTypeDef | HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Disable the DMAMUX request generator block used by the given DMA stream (instance).
void | HAL_DMAEx_MUX_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMAMUX interrupt request.

Detailed Description

Extended features functions.

 ===============================================================================
                #####  Extended features functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the source, destination address and data length and
          Start MultiBuffer DMA transfer
      (+) Configure the source, destination address and data length and
          Start MultiBuffer DMA transfer with interrupt
      (+) Change on the fly the memory0 or memory1 address.

Function Documentation

HAL_StatusTypeDef HAL_DMAEx_ChangeMemory | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | Address,
 |  | HAL_DMA_MemoryTypeDef | memory
 | ) |  |

Change the memory0 or memory1 address on the fly.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Address,: The new address
memory,: the memory to be changed, This parameter can be one of the following values: MEMORY0 / MEMORY1
Note:
The MEMORY0 address can be changed only when the current transfer use MEMORY1 and the MEMORY1 address can be changed only when the current transfer use MEMORY0.
Return values:
HAL status

Definition at line 310 of file stm32h7xx_hal_dma_ex.c.

References __DMA_HandleTypeDef::Instance, and MEMORY0.

Referenced by DCMI_DMAXferCplt().

HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_MuxRequestGeneratorConfigTypeDef * | pRequestGeneratorConfig
 | ) |  |

Configure the DMAMUX request generator block used by the given DMA stream (instance).

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef : contains the request generator parameters.
Return values:
HAL status

Definition at line 386 of file stm32h7xx_hal_dma_ex.c.

References assert_param, __DMA_HandleTypeDef::DMAmuxRequestGen, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, IS_D2_DMA_INSTANCE, IS_D2_DMAMUX_REQUEST_GEN_SIGNAL_ID, IS_D3_DMAMUX_REQUEST_GEN_SIGNAL_ID, IS_DMAMUX_REQUEST_GEN_POLARITY, IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER, HAL_DMA_MuxRequestGeneratorConfigTypeDef::Polarity, HAL_DMA_MuxRequestGeneratorConfigTypeDef::RequestNumber, HAL_DMA_MuxRequestGeneratorConfigTypeDef::SignalID, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_MuxSyncConfigTypeDef * | pSyncConfig
 | ) |  |

Configure the DMAMUX synchronization parameters for a given DMA stream (instance).

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
Return values:
HAL status

Definition at line 333 of file stm32h7xx_hal_dma_ex.c.

References assert_param, DMAMUX_POSITION_CxCR_EGE, DMAMUX_POSITION_CxCR_SE, __DMA_HandleTypeDef::DMAmuxChannel, HAL_DMA_MuxSyncConfigTypeDef::EventEnable, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, IS_D2_DMA_INSTANCE, IS_D2_DMAMUX_SYNC_SIGNAL_ID, IS_D3_DMAMUX_SYNC_SIGNAL_ID, IS_DMAMUX_SYNC_EVENT, IS_DMAMUX_SYNC_POLARITY, IS_DMAMUX_SYNC_REQUEST_NUMBER, IS_DMAMUX_SYNC_STATE, HAL_DMA_MuxSyncConfigTypeDef::RequestNumber, __DMA_HandleTypeDef::State, HAL_DMA_MuxSyncConfigTypeDef::SyncEnable, HAL_DMA_MuxSyncConfigTypeDef::SyncPolarity, and HAL_DMA_MuxSyncConfigTypeDef::SyncSignalID.

HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator ( DMA_HandleTypeDef * hdma )

Disable the DMAMUX request generator block used by the given DMA stream (instance).

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 461 of file stm32h7xx_hal_dma_ex.c.

References assert_param, __DMA_HandleTypeDef::DMAmuxRequestGen, HAL_DMA_STATE_RESET, __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator ( DMA_HandleTypeDef * hdma )

Enable the DMAMUX request generator block used by the given DMA stream (instance).

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 433 of file stm32h7xx_hal_dma_ex.c.

References assert_param, __DMA_HandleTypeDef::DMAmuxRequestGen, HAL_DMA_STATE_RESET, __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | SecondMemAddress,
 |  | uint32_t | DataLength
 | ) |  |

Starts the multi_buffer DMA Transfer.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
SecondMemAddress,: The second memory Buffer address in case of multi buffer Transfer
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 136 of file stm32h7xx_hal_dma_ex.c.

References __HAL_DMA_ENABLE, assert_param, DMA_InitTypeDef::Direction, DMA_MEMORY_TO_MEMORY, DMA_MultiBufferSetConfig(), __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NOT_SUPPORTED, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, IS_D2_DMA_INSTANCE, IS_DMA_BUFFER_SIZE, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::StreamBaseAddress, and __DMA_HandleTypeDef::StreamIndex.

HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | SecondMemAddress,
 |  | uint32_t | DataLength
 | ) |  |

Starts the multi_buffer DMA Transfer with interrupt enabled.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
SecondMemAddress,: The second memory Buffer address in case of multi buffer Transfer
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 207 of file stm32h7xx_hal_dma_ex.c.

References __HAL_DMA_ENABLE, assert_param, DMA_InitTypeDef::Direction, DMA_IT_DME, DMA_IT_FE, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, DMA_MEMORY_TO_MEMORY, DMA_MultiBufferSetConfig(), __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_ERROR_NOT_SUPPORTED, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, IS_D2_DMA_INSTANCE, IS_DMA_BUFFER_SIZE, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::StreamBaseAddress, __DMA_HandleTypeDef::StreamIndex, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_DCMI_Start_DMA().

void HAL_DMAEx_MUX_IRQHandler ( DMA_HandleTypeDef * hdma )

Handles DMAMUX interrupt request.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
None

Definition at line 489 of file stm32h7xx_hal_dma_ex.c.

References __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_REQGEN, HAL_DMA_ERROR_SYNC, and __DMA_HandleTypeDef::XferErrorCallback.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMA Private Macros

Defines
DMA Private Macros
DMAEx

DMAEx private macros. More...

Defines

#define | IS_D2_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO)
#define | IS_D3_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2)
#define | IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32))
#define | IS_DMAMUX_SYNC_POLARITY(POLARITY)
#define | IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
#define | IS_DMAMUX_SYNC_EVENT(EVENT)
#define | IS_D2_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO)
#define | IS_D3_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT)
#define | IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32))
#define | IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY)

Detailed Description

DMAEx private macros.

Define Documentation

#define IS_D2_DMAMUX_REQUEST_GEN_SIGNAL_ID ( SIGNAL_ID ) ((SIGNAL_ID) <= HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO)

Definition at line 285 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

#define IS_D2_DMAMUX_SYNC_SIGNAL_ID ( SIGNAL_ID ) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO)

Definition at line 270 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_D3_DMAMUX_REQUEST_GEN_SIGNAL_ID ( SIGNAL_ID ) ((SIGNAL_ID) <= HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT)

Definition at line 286 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

#define IS_D3_DMAMUX_SYNC_SIGNAL_ID ( SIGNAL_ID ) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2)

Definition at line 271 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_DMAMUX_REQUEST_GEN_POLARITY ( POLARITY )
Value:
(((POLARITY) == HAL_DMAMUX_REQUEST_GEN_NO_EVENT) || \
                                                  ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_RISING)   || \
                                                  ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_FALLING)   || \
                                                  ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_RISING_FALLING))

Definition at line 290 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER ( REQUEST_NUMBER ) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32))

Definition at line 288 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

#define IS_DMAMUX_SYNC_EVENT ( EVENT )
Value:
(((EVENT) == DISABLE)   || \
                                     ((EVENT) == ENABLE))

Definition at line 282 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_DMAMUX_SYNC_POLARITY ( POLARITY )
Value:
(((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT)    || \
                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING)   || \
                                           ((POLARITY) == HAL_DMAMUX_SYNC_FALLING)  || \
                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))

Definition at line 275 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_DMAMUX_SYNC_REQUEST_NUMBER ( REQUEST_NUMBER ) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32))

Definition at line 273 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_DMAMUX_SYNC_STATE ( SYNC ) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))

Definition at line 280 of file stm32h7xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMAEx Private Functions

Functions
DMAEx Private Functions
DMAEx

DMAEx Private functions. More...

Functions

static void DMA_MultiBufferSetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Set the DMA Transfer parameter.

Detailed Description

DMAEx Private functions.

Function Documentation

static void DMA_MultiBufferSetConfig | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  | [static]

Set the DMA Transfer parameter.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 555 of file stm32h7xx_hal_dma_ex.c.

References DMA_InitTypeDef::Direction, DMA_MEMORY_TO_PERIPH, __DMA_HandleTypeDef::Init, and __DMA_HandleTypeDef::Instance.

Referenced by HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: DMAEx

Modules | Defines
DMAEx
STM32H7xx_HAL_Driver

DMA Extended HAL module driver. More...

Modules

DMAEx Exported Types

DMAEx Exported types.

DMA Exported Constants

DMAEx Exported constants.

DMAEx Exported Functions

DMAEx Exported functions.

DMA Private Macros

DMAEx private macros.

DMAEx Private Functions

DMAEx Private functions.

Defines

#define | DMAMUX_POSITION_CxCR_SE (uint32_t)POSITION_VAL(DMAMUX_CxCR_SE)
#define | DMAMUX_POSITION_CxCR_EGE (uint32_t)POSITION_VAL(DMAMUX_CxCR_EGE)

Detailed Description

DMA Extended HAL module driver.

Define Documentation

#define DMAMUX_POSITION_CxCR_EGE (uint32_t)POSITION_VAL(DMAMUX_CxCR_EGE)

Required for left shift of the DMAMUX SYNC EVENT enable/disable

Definition at line 88 of file stm32h7xx_hal_dma_ex.c.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define DMAMUX_POSITION_CxCR_SE (uint32_t)POSITION_VAL(DMAMUX_CxCR_SE)

Required for left shift of the DMAMUX SYNC enable/disable

Definition at line 87 of file stm32h7xx_hal_dma_ex.c.

Referenced by HAL_DMAEx_ConfigMuxSync().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Private Macros

Defines
ETH Private Macros
ETH

Defines

#define | INCR_TX_DESC_INDEX(inx, offset)
#define | INCR_RX_DESC_INDEX(inx, offset)

Define Documentation

#define INCR_RX_DESC_INDEX | ( | inx,
 |  | offset
 | ) |
Value:
do {\
        (inx) += (offset);\
          if ((inx) >= ETH_RX_DESC_CNT){\
            (inx) = ((inx) - ETH_RX_DESC_CNT);}\
} while (0)

Definition at line 168 of file stm32h7xx_hal_eth.c.

Referenced by HAL_ETH_BuildRxDescriptors(), HAL_ETH_GetRxDataBuffer(), HAL_ETH_GetRxDataInfo(), HAL_ETH_GetRxDataLength(), HAL_ETH_IsRxDataAvailable(), and HAL_ETH_Start_IT().

#define INCR_TX_DESC_INDEX | ( | inx,
 |  | offset
 | ) |
Value:
do {\
        (inx) += (offset);\
          if ((inx) >= ETH_TX_DESC_CNT){\
            (inx) = ((inx) - ETH_TX_DESC_CNT);}\
} while (0)

Definition at line 161 of file stm32h7xx_hal_eth.c.

Referenced by ETH_Prepare_Tx_Descriptors(), HAL_ETH_Transmit(), and HAL_ETH_Transmit_IT().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Private Functions

Functions
ETH Private Functions
ETH

Functions

static void | ETH_SetMACConfig (ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
static void | ETH_SetDMAConfig (ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)

Function Documentation

static void ETH_SetDMAConfig | ( | ETH_HandleTypeDef * | heth,
 |  | ETH_DMAConfigTypeDef * | dmaconf
 | ) |  | [static]

Definition at line 2104 of file stm32h7xx_hal_eth.c.

References ETH_DMAConfigTypeDef::AddressAlignedBeats, ETH_DMAConfigTypeDef::BurstMode, ETH_DMAConfigTypeDef::DMAArbitration, ETH_DMACCR_MASK, ETH_DMACRCR_MASK, ETH_DMACTCR_MASK, ETH_DMAMR_MASK, ETH_DMASBMR_MASK, ETH_DMAConfigTypeDef::FlushRxPacket, ETH_HandleTypeDef::Instance, ETH_DMAConfigTypeDef::MaximumSegmentSize, ETH_DMAConfigTypeDef::PBLx8Mode, ETH_DMAConfigTypeDef::RebuildINCRxBurst, ETH_DMAConfigTypeDef::RxDMABurstLength, ETH_DMAConfigTypeDef::SecondPacketOperate, ETH_DMAConfigTypeDef::TCPSegmentation, and ETH_DMAConfigTypeDef::TxDMABurstLength.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_SetDMAConfig().

static void ETH_SetMACConfig | ( | ETH_HandleTypeDef * | heth,
 |  | ETH_MACConfigTypeDef * | macconf
 | ) |  | [static]

Definition at line 2027 of file stm32h7xx_hal_eth.c.

References ETH_MACConfigTypeDef::AutomaticPadCRCStrip, ETH_MACConfigTypeDef::BackOffLimit, ETH_MACConfigTypeDef::CarrierSenseBeforeTransmit, ETH_MACConfigTypeDef::CarrierSenseDuringTransmit, ETH_MACConfigTypeDef::ChecksumOffload, ETH_MACConfigTypeDef::CRCCheckingRxPackets, ETH_MACConfigTypeDef::CRCStripTypePacket, ETH_MACConfigTypeDef::DeferralCheck, ETH_MACConfigTypeDef::DropTCPIPChecksumErrorPacket, ETH_MACConfigTypeDef::DuplexMode, ETH_MACCR_MASK, ETH_MACECR_MASK, ETH_MACRFCR_MASK, ETH_MACTFCR_MASK, ETH_MACWTR_MASK, ETH_MTLRQOMR_MASK, ETH_MTLTQOMR_MASK, ETH_MACConfigTypeDef::ExtendedInterPacketGap, ETH_MACConfigTypeDef::ExtendedInterPacketGapVal, ETH_MACConfigTypeDef::ForwardRxErrorPacket, ETH_MACConfigTypeDef::ForwardRxUndersizedGoodPacket, ETH_MACConfigTypeDef::GiantPacketSizeLimit, ETH_MACConfigTypeDef::GiantPacketSizeLimitControl, ETH_HandleTypeDef::Instance, ETH_MACConfigTypeDef::InterPacketGapVal, ETH_MACConfigTypeDef::Jabber, ETH_MACConfigTypeDef::JumboPacket, ETH_MACConfigTypeDef::LoopbackMode, ETH_MACConfigTypeDef::PauseLowThreshold, ETH_MACConfigTypeDef::PauseTime, ETH_MACConfigTypeDef::PreambleLength, ETH_MACConfigTypeDef::ProgrammableWatchdog, ETH_MACConfigTypeDef::ReceiveFlowControl, ETH_MACConfigTypeDef::ReceiveOwn, ETH_MACConfigTypeDef::ReceiveQueueMode, ETH_MACConfigTypeDef::RetryTransmission, ETH_MACConfigTypeDef::SlowProtocolDetect, ETH_MACConfigTypeDef::SourceAddrControl, ETH_MACConfigTypeDef::Speed, ETH_MACConfigTypeDef::Support2KPacket, ETH_MACConfigTypeDef::TransmitFlowControl, ETH_MACConfigTypeDef::TransmitQueueMode, ETH_MACConfigTypeDef::UnicastPausePacketDetect, ETH_MACConfigTypeDef::UnicastSlowProtocolPacketDetect, ETH_MACConfigTypeDef::Watchdog, ETH_MACConfigTypeDef::WatchdogTimeout, and ETH_MACConfigTypeDef::ZeroQuantaPause.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_SetMACConfig().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and deinitialization functions

Functions
Initialization and deinitialization functions
ETH Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_ETH_Init (ETH_HandleTypeDef *heth)
Initialize the Ethernet peripheral registers.
HAL_StatusTypeDef | HAL_ETH_DeInit (ETH_HandleTypeDef *heth)
DeInitializes the ETH peripheral.
__weak void | HAL_ETH_MspInit (ETH_HandleTypeDef *heth)
Initializes the ETH MSP.
__weak void | HAL_ETH_MspDeInit (ETH_HandleTypeDef *heth)
DeInitializes ETH MSP.
HAL_StatusTypeDef | HAL_ETH_DescAssignMemory (ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1, uint8_t *pBuffer2)
Assign memory buffers to a DMA Rx descriptor.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          deinitialize the ETH peripheral:

      (+) User must Implement HAL_ETH_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO and NVIC ).

      (+) Call the function HAL_ETH_Init() to configure the selected device with
          the selected configuration:
        (++) MAC address
        (++) Media interface (MII or RMII)
        (++) Rx DMA Descriptors Tab
        (++) Tx DMA Descriptors Tab
        (++) Length of Rx Buffers

      (+) Call the function HAL_ETH_DescAssignMemory() to assign data buffers
          for each Rx DMA Descriptor

      (+) Call the function HAL_ETH_DeInit() to restore the default configuration
          of the selected ETH peripheral.

Function Documentation

HAL_StatusTypeDef HAL_ETH_DeInit ( ETH_HandleTypeDef * heth )

DeInitializes the ETH peripheral.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
HAL status

Definition at line 336 of file stm32h7xx_hal_eth.c.

References ETH_HandleTypeDef::gState, HAL_ETH_MspDeInit(), HAL_ETH_STATE_BUSY, and HAL_ETH_STATE_RESET.

HAL_StatusTypeDef HAL_ETH_DescAssignMemory | ( | ETH_HandleTypeDef * | heth,
 |  | uint32_t | Index,
 |  | uint8_t * | pBuffer1,
 |  | uint8_t * | pBuffer2
 | ) |  |

Assign memory buffers to a DMA Rx descriptor.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Index : index of the DMA Rx descriptor this parameter can be a value from 0x0 to (ETH_RX_DESC_CNT -1)
pBuffer1,: address of buffer1
pBuffer2,: address of buffer 2 if available
Return values:
HAL status

Definition at line 391 of file stm32h7xx_hal_eth.c.

References ETH_HandleTypeDef::ErrorCode, ETH_DMARXNDESCRF_BUF1V, ETH_DMARXNDESCRF_BUF2V, ETH_DMARXNDESCRF_OWN, ETH_RX_DESC_CNT, HAL_ETH_ERROR_PARAM, ETH_RxDescListTypeDef::RxDesc, and ETH_HandleTypeDef::RxDescList.

HAL_StatusTypeDef HAL_ETH_Init ( ETH_HandleTypeDef * heth )

Initialize the Ethernet peripheral registers.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
HAL status

Definition at line 233 of file stm32h7xx_hal_eth.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, ETH_HandleTypeDef::ErrorCode, ETH_DMARxDescListInit(), ETH_DMATxDescListInit(), ETH_MAC_MDIO_ClkConfig(), ETH_MAC_US_TICK, ETH_MACDMAConfig(), ETH_SWRESET_TIMEOUT, ETH_HandleTypeDef::gState, HAL_ETH_ERROR_NONE, HAL_ETH_ERROR_PARAM, HAL_ETH_ERROR_TIMEOUT, HAL_ETH_MII_MODE, HAL_ETH_MspInit(), HAL_ETH_STATE_BUSY, HAL_ETH_STATE_ERROR, HAL_ETH_STATE_READY, HAL_ETH_STATE_RESET, HAL_GetTick(), HAL_RCC_GetHCLKFreq(), HAL_SYSCFG_ETHInterfaceSelect(), ETH_HandleTypeDef::Init, ETH_HandleTypeDef::Instance, ETH_InitTypeDef::MACAddr, ETH_InitTypeDef::MediaInterface, ETH_InitTypeDef::RxBuffLen, ETH_HandleTypeDef::RxState, SYSCFG_ETH_MII, and SYSCFG_ETH_RMII.

void HAL_ETH_MspDeInit ( ETH_HandleTypeDef * heth )

DeInitializes ETH MSP.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 372 of file stm32h7xx_hal_eth.c.

Referenced by HAL_ETH_DeInit().

void HAL_ETH_MspInit ( ETH_HandleTypeDef * heth )

Initializes the ETH MSP.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 357 of file stm32h7xx_hal_eth.c.

Referenced by HAL_ETH_Init().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
ETH Exported Functions

ETH Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_ETH_Start (ETH_HandleTypeDef *heth)
Enables Ethernet MAC and DMA reception and transmission.
HAL_StatusTypeDef | HAL_ETH_Start_IT (ETH_HandleTypeDef *heth)
Enables Ethernet MAC and DMA reception/transmission in Interrupt mode.
HAL_StatusTypeDef | HAL_ETH_Stop (ETH_HandleTypeDef *heth)
Stop Ethernet MAC and DMA reception/transmission.
HAL_StatusTypeDef | HAL_ETH_Stop_IT (ETH_HandleTypeDef *heth)
Stop Ethernet MAC and DMA reception/transmission in Interrupt mode.
HAL_StatusTypeDef | HAL_ETH_Transmit (ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout)
Sends an Ethernet Packet in polling mode.
HAL_StatusTypeDef | HAL_ETH_Transmit_IT (ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig)
Sends an Ethernet Packet in interrupt mode.
uint8_t | HAL_ETH_IsRxDataAvailable (ETH_HandleTypeDef *heth)
Checks for received Packets.
HAL_StatusTypeDef | HAL_ETH_GetRxDataBuffer (ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer)
This function gets the buffer address of last received Packet.
HAL_StatusTypeDef | HAL_ETH_GetRxDataLength (ETH_HandleTypeDef *heth, uint32_t *Length)
This function gets the length of last received Packet.
HAL_StatusTypeDef | HAL_ETH_GetRxDataInfo (ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo)
Get the Rx data info (Packet type, VLAN tag, Filters status, ...)
HAL_StatusTypeDef | HAL_ETH_BuildRxDescriptors (ETH_HandleTypeDef *heth)
This function gives back Rx Desc of the last received Packet to the DMA, so ETH DMA will be able to use these descriptors to receive next Packets.
void | HAL_ETH_IRQHandler (ETH_HandleTypeDef *heth)
This function handles ETH interrupt request.
__weak void | HAL_ETH_TxCpltCallback (ETH_HandleTypeDef *heth)
Tx Transfer completed callbacks.
__weak void | HAL_ETH_RxCpltCallback (ETH_HandleTypeDef *heth)
Rx Transfer completed callbacks.
__weak void | HAL_ETH_DMAErrorCallback (ETH_HandleTypeDef *heth)
Ethernet DMA transfer error callbacks.
__weak void | HAL_ETH_MACErrorCallback (ETH_HandleTypeDef *heth)
Ethernet MAC transfer error callbacks.
__weak void | HAL_ETH_PMTCallback (ETH_HandleTypeDef *heth)
Ethernet Power Management module IT callback.
__weak void | HAL_ETH_EEECallback (ETH_HandleTypeDef *heth)
Energy Efficient Etherent IT callback.
__weak void | HAL_ETH_WakeUpCallback (ETH_HandleTypeDef *heth)
ETH WAKEUP interrupt callback.
HAL_StatusTypeDef | HAL_ETH_ReadPHYRegister (ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue)
Read a PHY register.
HAL_StatusTypeDef | HAL_ETH_WritePHYRegister (ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue)
Writes to a PHY register.

Detailed Description

ETH Transmit and Receive functions.

  ==============================================================================
                      ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the ETH
    data transfer.

Function Documentation

HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors ( ETH_HandleTypeDef * heth )

This function gives back Rx Desc of the last received Packet to the DMA, so ETH DMA will be able to use these descriptors to receive next Packets.

It should be called after processing the received Packet.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
HAL status.

Definition at line 1110 of file stm32h7xx_hal_eth.c.

References ETH_RxDescListTypeDef::AppContextDesc, ETH_RxDescListTypeDef::AppDescNbr, ETH_DMARXNDESCRF_BUF1V, ETH_DMARXNDESCRF_BUF2V, ETH_DMARXNDESCRF_IOC, ETH_DMARXNDESCRF_OWN, ETH_RxDescListTypeDef::FirstAppDesc, INCR_RX_DESC_INDEX, ETH_HandleTypeDef::Instance, ETH_RxDescListTypeDef::ItMode, ETH_RxDescListTypeDef::RxDesc, and ETH_HandleTypeDef::RxDescList.

void HAL_ETH_DMAErrorCallback ( ETH_HandleTypeDef * heth )

Ethernet DMA transfer error callbacks.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 1318 of file stm32h7xx_hal_eth.c.

Referenced by HAL_ETH_IRQHandler().

void HAL_ETH_EEECallback ( ETH_HandleTypeDef * heth )

Energy Efficient Etherent IT callback.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 1361 of file stm32h7xx_hal_eth.c.

Referenced by HAL_ETH_IRQHandler().

HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer | ( | ETH_HandleTypeDef * | heth,
 |  | ETH_BufferTypeDef * | RxBuffer
 | ) |  |

This function gets the buffer address of last received Packet.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
RxBuffer,: Pointer to a ETH_BufferTypeDef structure
Return values:
HAL status

Definition at line 901 of file stm32h7xx_hal_eth.c.

References ETH_RxDescListTypeDef::AppDescNbr, __ETH_BufferTypeDef::buffer, ETH_DMARXNDESCWBF_PL, ETH_RxDescListTypeDef::FirstAppDesc, HAL_ETH_IsRxDataAvailable(), INCR_RX_DESC_INDEX, __DMA2D_HandleTypeDef::Init, ETH_HandleTypeDef::Init, __ETH_BufferTypeDef::len, __ETH_BufferTypeDef::next, ETH_InitTypeDef::RxBuffLen, ETH_RxDescListTypeDef::RxDesc, and ETH_HandleTypeDef::RxDescList.

HAL_StatusTypeDef HAL_ETH_GetRxDataInfo | ( | ETH_HandleTypeDef * | heth,
 |  | ETH_RxPacketInfo * | RxPacketInfo
 | ) |  |

Get the Rx data info (Packet type, VLAN tag, Filters status, ...)

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
RxPacketInfo,: parameter to hold info of received buffer
Return values:
HAL status

Definition at line 1037 of file stm32h7xx_hal_eth.c.

References ETH_RxDescListTypeDef::AppDescNbr, ETH_RxPacketInfo::Checksum, ETH_RxPacketInfo::ErrorCode, ETH_DMARXNDESCWBF_DAF, ETH_DMARXNDESCWBF_ERRORS_MASK, ETH_DMARXNDESCWBF_ES, ETH_DMARXNDESCWBF_HF, ETH_DMARXNDESCWBF_IPCB, ETH_DMARXNDESCWBF_IPCE, ETH_DMARXNDESCWBF_IPHE, ETH_DMARXNDESCWBF_IPV4, ETH_DMARXNDESCWBF_IPV6, ETH_DMARXNDESCWBF_IVT, ETH_DMARXNDESCWBF_L3FM, ETH_DMARXNDESCWBF_L3L4FM, ETH_DMARXNDESCWBF_L4FM, ETH_DMARXNDESCWBF_LT, ETH_DMARXNDESCWBF_LT_DVLAN, ETH_DMARXNDESCWBF_LT_VLAN, ETH_DMARXNDESCWBF_OVT, ETH_DMARXNDESCWBF_PT, ETH_DMARXNDESCWBF_RS0V, ETH_DMARXNDESCWBF_RS1V, ETH_DMARXNDESCWBF_RS2V, ETH_DMARXNDESCWBF_SAF, ETH_DMARXNDESCWBF_VF, ETH_RxDescListTypeDef::FirstAppDesc, HAL_ETH_IsRxDataAvailable(), ETH_RxPacketInfo::HeaderType, INCR_RX_DESC_INDEX, ETH_RxPacketInfo::InnerVlanTag, ETH_RxPacketInfo::L3FilterStatus, ETH_RxPacketInfo::L4FilterStatus, ETH_RxPacketInfo::MacFilterStatus, ETH_RxPacketInfo::PayloadType, ETH_RxDescListTypeDef::RxDesc, ETH_HandleTypeDef::RxDescList, ETH_RxPacketInfo::SegmentCnt, and ETH_RxPacketInfo::VlanTag.

HAL_StatusTypeDef HAL_ETH_GetRxDataLength | ( | ETH_HandleTypeDef * | heth,
 |  | uint32_t * | Length
 | ) |  |

This function gets the length of last received Packet.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Length,: parameter to hold Rx packet length
Return values:
HAL Status

Definition at line 1005 of file stm32h7xx_hal_eth.c.

References ETH_RxDescListTypeDef::AppDescNbr, ETH_DMARXNDESCWBF_PL, ETH_RxDescListTypeDef::FirstAppDesc, HAL_ETH_IsRxDataAvailable(), INCR_RX_DESC_INDEX, ETH_RxDescListTypeDef::RxDesc, and ETH_HandleTypeDef::RxDescList.

void HAL_ETH_IRQHandler ( ETH_HandleTypeDef * heth )

This function handles ETH interrupt request.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
HAL status

Definition at line 1173 of file stm32h7xx_hal_eth.c.

References __HAL_ETH_DMA_CLEAR_IT, __HAL_ETH_DMA_DISABLE_IT, __HAL_ETH_DMA_GET_IT, __HAL_ETH_DMA_GET_IT_SOURCE, __HAL_ETH_MAC_GET_IT, __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG, __HAL_ETH_WAKEUP_EXTI_GET_FLAG, ETH_HandleTypeDef::DMAErrorCode, ETH_HandleTypeDef::ErrorCode, ETH_MAC_LPI_IT, ETH_MAC_PMT_IT, ETH_WAKEUP_EXTI_LINE, ETH_HandleTypeDef::gState, HAL_ETH_DMAErrorCallback(), HAL_ETH_EEECallback(), HAL_ETH_ERROR_DMA, HAL_ETH_ERROR_NONE, HAL_ETH_IsRxDataAvailable(), HAL_ETH_MACErrorCallback(), HAL_ETH_PMTCallback(), HAL_ETH_RxCpltCallback(), HAL_ETH_STATE_ERROR, HAL_ETH_STATE_READY, HAL_ETH_TxCpltCallback(), HAL_ETH_WakeUpCallback(), ETH_HandleTypeDef::Instance, ETH_HandleTypeDef::MACErrorCode, ETH_HandleTypeDef::MACLPIEvent, and ETH_HandleTypeDef::MACWakeUpEvent.

uint8_t HAL_ETH_IsRxDataAvailable ( ETH_HandleTypeDef * heth )

Checks for received Packets.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
1,: A Packet is received 0: no Packet received

Definition at line 778 of file stm32h7xx_hal_eth.c.

References ETH_RxDescListTypeDef::AppContextDesc, ETH_RxDescListTypeDef::AppDescNbr, ETH_RxDescListTypeDef::CurRxDesc, ETH_DMARXNDESCRF_BUF1V, ETH_DMARXNDESCRF_BUF2V, ETH_DMARXNDESCRF_IOC, ETH_DMARXNDESCRF_OWN, ETH_DMARXNDESCWBF_CTXT, ETH_DMARXNDESCWBF_FD, ETH_DMARXNDESCWBF_LD, ETH_DMARXNDESCWBF_OWN, ETH_RX_DESC_CNT, ETH_RxDescListTypeDef::FirstAppDesc, INCR_RX_DESC_INDEX, ETH_RxDescListTypeDef::ItMode, ETH_RxDescListTypeDef::RxDesc, and ETH_HandleTypeDef::RxDescList.

Referenced by HAL_ETH_GetRxDataBuffer(), HAL_ETH_GetRxDataInfo(), HAL_ETH_GetRxDataLength(), and HAL_ETH_IRQHandler().

void HAL_ETH_MACErrorCallback ( ETH_HandleTypeDef * heth )

Ethernet MAC transfer error callbacks.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 1331 of file stm32h7xx_hal_eth.c.

Referenced by HAL_ETH_IRQHandler().

void HAL_ETH_PMTCallback ( ETH_HandleTypeDef * heth )

Ethernet Power Management module IT callback.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 1346 of file stm32h7xx_hal_eth.c.

Referenced by HAL_ETH_IRQHandler().

HAL_StatusTypeDef HAL_ETH_ReadPHYRegister | ( | ETH_HandleTypeDef * | heth,
 |  | uint32_t | PHYAddr,
 |  | uint32_t | PHYReg,
 |  | uint32_t * | pRegValue
 | ) |  |

Read a PHY register.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
PHYAddr,: PHY port address, must be a value from 0 to 31
PHYReg,: PHY register address, must be a value from 0 to 31
pRegValue,: parameter to hold read value
Return values:
HAL status

Definition at line 1394 of file stm32h7xx_hal_eth.c.

References ETH_MDIO_BUS_TIMEOUT, HAL_GetTick(), and ETH_HandleTypeDef::Instance.

void HAL_ETH_RxCpltCallback ( ETH_HandleTypeDef * heth )

Rx Transfer completed callbacks.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 1303 of file stm32h7xx_hal_eth.c.

Referenced by HAL_ETH_IRQHandler().

HAL_StatusTypeDef HAL_ETH_Start ( ETH_HandleTypeDef * heth )

Enables Ethernet MAC and DMA reception and transmission.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
HAL status

Definition at line 450 of file stm32h7xx_hal_eth.c.

References ETH_HandleTypeDef::gState, HAL_ETH_STATE_BUSY, HAL_ETH_STATE_BUSY_RX, HAL_ETH_STATE_READY, ETH_HandleTypeDef::Instance, and ETH_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_ETH_Start_IT ( ETH_HandleTypeDef * heth )

Enables Ethernet MAC and DMA reception/transmission in Interrupt mode.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
HAL status

Definition at line 491 of file stm32h7xx_hal_eth.c.

References __HAL_ETH_DMA_ENABLE_IT, ETH_DMARXNDESCRF_IOC, ETH_RX_DESC_CNT, ETH_HandleTypeDef::gState, HAL_ETH_STATE_BUSY, HAL_ETH_STATE_BUSY_RX, HAL_ETH_STATE_READY, INCR_RX_DESC_INDEX, ETH_HandleTypeDef::Instance, ETH_RxDescListTypeDef::ItMode, ETH_RxDescListTypeDef::RxDesc, ETH_HandleTypeDef::RxDescList, and ETH_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_ETH_Stop ( ETH_HandleTypeDef * heth )

Stop Ethernet MAC and DMA reception/transmission.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
HAL status

Definition at line 554 of file stm32h7xx_hal_eth.c.

References ETH_HandleTypeDef::gState, HAL_ETH_STATE_BUSY, HAL_ETH_STATE_READY, HAL_ETH_STATE_RESET, ETH_HandleTypeDef::Instance, and ETH_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_ETH_Stop_IT ( ETH_HandleTypeDef * heth )

Stop Ethernet MAC and DMA reception/transmission in Interrupt mode.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
HAL status

Definition at line 594 of file stm32h7xx_hal_eth.c.

References __HAL_ETH_DMA_DISABLE_IT, ETH_DMA_NORMAL_IT, ETH_DMA_RX_IT, ETH_DMA_TX_IT, ETH_DMARXNDESCRF_IOC, ETH_RX_DESC_CNT, ETH_HandleTypeDef::gState, HAL_ETH_STATE_BUSY, HAL_ETH_STATE_READY, HAL_ETH_STATE_RESET, ETH_HandleTypeDef::Instance, ETH_RxDescListTypeDef::ItMode, ETH_RxDescListTypeDef::RxDesc, ETH_HandleTypeDef::RxDescList, and ETH_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_ETH_Transmit | ( | ETH_HandleTypeDef * | heth,
 |  | ETH_TxPacketConfig * | pTxConfig,
 |  | uint32_t | Timeout
 | ) |  |

Sends an Ethernet Packet in polling mode.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
pTxConfig,: Hold the configuration of packet to be transmitted
Timeout,: timeout value
Return values:
HAL status

Definition at line 652 of file stm32h7xx_hal_eth.c.

References ETH_TxDescListTypeDef::CurTxDesc, ETH_HandleTypeDef::DMAErrorCode, ETH_HandleTypeDef::ErrorCode, ETH_DMATXNDESCWBF_OWN, ETH_Prepare_Tx_Descriptors(), ETH_HandleTypeDef::gState, HAL_ETH_ERROR_BUSY, HAL_ETH_ERROR_DMA, HAL_ETH_ERROR_NONE, HAL_ETH_ERROR_PARAM, HAL_ETH_ERROR_TIMEOUT, HAL_ETH_STATE_BUSY_TX, HAL_ETH_STATE_ERROR, HAL_ETH_STATE_READY, HAL_GetTick(), INCR_TX_DESC_INDEX, ETH_HandleTypeDef::Instance, ETH_TxDescListTypeDef::TxDesc, and ETH_HandleTypeDef::TxDescList.

HAL_StatusTypeDef HAL_ETH_Transmit_IT | ( | ETH_HandleTypeDef * | heth,
 |  | ETH_TxPacketConfig * | pTxConfig
 | ) |  |

Sends an Ethernet Packet in interrupt mode.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
pTxConfig,: Hold the configuration of packet to be transmitted
Return values:
HAL status

Definition at line 736 of file stm32h7xx_hal_eth.c.

References ETH_TxDescListTypeDef::CurTxDesc, ETH_HandleTypeDef::ErrorCode, ETH_Prepare_Tx_Descriptors(), ETH_HandleTypeDef::gState, HAL_ETH_ERROR_BUSY, HAL_ETH_ERROR_NONE, HAL_ETH_STATE_BUSY_TX, HAL_ETH_STATE_READY, INCR_TX_DESC_INDEX, ETH_HandleTypeDef::Instance, ETH_TxDescListTypeDef::TxDesc, and ETH_HandleTypeDef::TxDescList.

void HAL_ETH_TxCpltCallback ( ETH_HandleTypeDef * heth )

Tx Transfer completed callbacks.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 1288 of file stm32h7xx_hal_eth.c.

Referenced by HAL_ETH_IRQHandler().

void HAL_ETH_WakeUpCallback ( ETH_HandleTypeDef * heth )

ETH WAKEUP interrupt callback.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 1376 of file stm32h7xx_hal_eth.c.

Referenced by HAL_ETH_IRQHandler().

HAL_StatusTypeDef HAL_ETH_WritePHYRegister | ( | ETH_HandleTypeDef * | heth,
 |  | uint32_t | PHYAddr,
 |  | uint32_t | PHYReg,
 |  | uint32_t | RegValue
 | ) |  |

Writes to a PHY register.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
PHYAddr,: PHY port address, must be a value from 0 to 31
PHYReg,: PHY register address, must be a value from 0 to 31
RegValue,: the value to write
Return values:
HAL status

Definition at line 1449 of file stm32h7xx_hal_eth.c.

References ETH_MDIO_BUS_TIMEOUT, HAL_GetTick(), and ETH_HandleTypeDef::Instance.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
ETH Exported Functions

ETH control functions. More...

Functions

HAL_StatusTypeDef | HAL_ETH_GetMACConfig (ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
Get the configuration of the MAC and MTL subsystems.
HAL_StatusTypeDef | HAL_ETH_GetDMAConfig (ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
Get the configuration of the DMA.
HAL_StatusTypeDef | HAL_ETH_SetMACConfig (ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
Set the MAC configuration.
HAL_StatusTypeDef | HAL_ETH_SetDMAConfig (ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
Set the ETH DMA configuration.
void | HAL_ETH_SetMDIOClockRange (ETH_HandleTypeDef *heth)
Configures the Clock range of ETH MDIO interface.
HAL_StatusTypeDef | HAL_ETH_SetMACFilterConfig (ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
Set the ETH MAC (L2) Filters configuration.
HAL_StatusTypeDef | HAL_ETH_GetMACFilterConfig (ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
Get the ETH MAC (L2) Filters configuration.
HAL_StatusTypeDef | HAL_ETH_SetSourceMACAddrMatch (ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr)
Set the source MAC Address to be matched.
HAL_StatusTypeDef | HAL_ETH_SetHashTable (ETH_HandleTypeDef *heth, uint32_t *pHashTable)
Set the ETH Hash Table Value.
void | HAL_ETH_SetRxVLANIdentifier (ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier)
Set the VLAN Identifier for Rx packets.
void | HAL_ETH_EnterPowerDownMode (ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig)
Enters the Power down mode.
void | HAL_ETH_ExitPowerDownMode (ETH_HandleTypeDef *heth)
Exits from the Power down mode.
HAL_StatusTypeDef | HAL_ETH_SetWakeUpFilter (ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count)
Set the WakeUp filter.

Detailed Description

ETH control functions.

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control the ETH
    peripheral.

Function Documentation

void HAL_ETH_EnterPowerDownMode | ( | ETH_HandleTypeDef * | heth,
 |  | ETH_PowerDownConfigTypeDef * | pPowerDownConfig
 | ) |  |

Enters the Power down mode.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
pPowerDownConfig,: a pointer to ETH_PowerDownConfigTypeDef structure that contains the Power Down configration
Return values:
None.

Definition at line 1872 of file stm32h7xx_hal_eth.c.

References __HAL_ETH_MAC_ENABLE_IT, ETH_MACPCSR_MASK, ETH_PowerDownConfigTypeDef::GlobalUnicast, ETH_HandleTypeDef::Instance, ETH_PowerDownConfigTypeDef::MagicPacket, ETH_PowerDownConfigTypeDef::WakeUpForward, and ETH_PowerDownConfigTypeDef::WakeUpPacket.

void HAL_ETH_ExitPowerDownMode ( ETH_HandleTypeDef * heth )

Exits from the Power down mode.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None.

Definition at line 1894 of file stm32h7xx_hal_eth.c.

References __HAL_ETH_MAC_DISABLE_IT, and ETH_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_ETH_GetDMAConfig | ( | ETH_HandleTypeDef * | heth,
 |  | ETH_DMAConfigTypeDef * | dmaconf
 | ) |  |

Get the configuration of the DMA.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
dmaconf,: pointer to a ETH_DMAConfigTypeDef structure that will hold the configuration of the ETH DMA.
Return values:
HAL Status

Definition at line 1588 of file stm32h7xx_hal_eth.c.

References ETH_DMAConfigTypeDef::AddressAlignedBeats, ETH_DMAConfigTypeDef::BurstMode, ETH_DMAConfigTypeDef::DMAArbitration, ETH_DMAConfigTypeDef::FlushRxPacket, ETH_HandleTypeDef::Instance, ETH_DMAConfigTypeDef::MaximumSegmentSize, ETH_DMAConfigTypeDef::PBLx8Mode, ETH_DMAConfigTypeDef::RebuildINCRxBurst, ETH_DMAConfigTypeDef::RxDMABurstLength, ETH_DMAConfigTypeDef::SecondPacketOperate, ETH_DMAConfigTypeDef::TCPSegmentation, and ETH_DMAConfigTypeDef::TxDMABurstLength.

HAL_StatusTypeDef HAL_ETH_GetMACConfig | ( | ETH_HandleTypeDef * | heth,
 |  | ETH_MACConfigTypeDef * | macconf
 | ) |  |

Get the configuration of the MAC and MTL subsystems.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
macconf,: pointer to a ETH_MACConfigTypeDef structure that will hold the configuration of the MAC.
Return values:
HAL Status

Definition at line 1521 of file stm32h7xx_hal_eth.c.

References ETH_MACConfigTypeDef::AutomaticPadCRCStrip, ETH_MACConfigTypeDef::BackOffLimit, ETH_MACConfigTypeDef::CarrierSenseBeforeTransmit, ETH_MACConfigTypeDef::CarrierSenseDuringTransmit, ETH_MACConfigTypeDef::ChecksumOffload, ETH_MACConfigTypeDef::CRCCheckingRxPackets, ETH_MACConfigTypeDef::CRCStripTypePacket, ETH_MACConfigTypeDef::DeferralCheck, ETH_MACConfigTypeDef::DropTCPIPChecksumErrorPacket, ETH_MACConfigTypeDef::DuplexMode, ETH_MACConfigTypeDef::ExtendedInterPacketGap, ETH_MACConfigTypeDef::ExtendedInterPacketGapVal, ETH_MACConfigTypeDef::ForwardRxErrorPacket, ETH_MACConfigTypeDef::ForwardRxUndersizedGoodPacket, ETH_MACConfigTypeDef::GiantPacketSizeLimit, ETH_MACConfigTypeDef::GiantPacketSizeLimitControl, ETH_HandleTypeDef::Instance, ETH_MACConfigTypeDef::InterPacketGapVal, ETH_MACConfigTypeDef::Jabber, ETH_MACConfigTypeDef::JumboPacket, ETH_MACConfigTypeDef::LoopbackMode, ETH_MACConfigTypeDef::PauseLowThreshold, ETH_MACConfigTypeDef::PauseTime, ETH_MACConfigTypeDef::PreambleLength, ETH_MACConfigTypeDef::ProgrammableWatchdog, ETH_MACConfigTypeDef::ReceiveFlowControl, ETH_MACConfigTypeDef::ReceiveOwn, ETH_MACConfigTypeDef::ReceiveQueueMode, ETH_MACConfigTypeDef::RetryTransmission, ETH_MACConfigTypeDef::SlowProtocolDetect, ETH_MACConfigTypeDef::SourceAddrControl, ETH_MACConfigTypeDef::Speed, ETH_MACConfigTypeDef::Support2KPacket, ETH_MACConfigTypeDef::TransmitFlowControl, ETH_MACConfigTypeDef::TransmitQueueMode, ETH_MACConfigTypeDef::UnicastPausePacketDetect, ETH_MACConfigTypeDef::UnicastSlowProtocolPacketDetect, ETH_MACConfigTypeDef::Watchdog, ETH_MACConfigTypeDef::WatchdogTimeout, and ETH_MACConfigTypeDef::ZeroQuantaPause.

HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig | ( | ETH_HandleTypeDef * | heth,
 |  | ETH_MACFilterConfigTypeDef * | pFilterConfig
 | ) |  |

Get the ETH MAC (L2) Filters configuration.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
pFilterConfig,: pointer to a ETH_MACFilterConfigTypeDef structure that will hold the configuration of the ETH MAC filters.
Return values:
HAL status

Definition at line 1761 of file stm32h7xx_hal_eth.c.

References ETH_MACFilterConfigTypeDef::BroadcastFilter, ETH_MACFilterConfigTypeDef::ControlPacketsFilter, ETH_MACFilterConfigTypeDef::DestAddrInverseFiltering, ETH_MACFilterConfigTypeDef::HachOrPerfectFilter, ETH_MACFilterConfigTypeDef::HashMulticast, ETH_MACFilterConfigTypeDef::HashUnicast, ETH_HandleTypeDef::Instance, ETH_MACFilterConfigTypeDef::PassAllMulticast, ETH_MACFilterConfigTypeDef::PromiscuousMode, ETH_MACFilterConfigTypeDef::ReceiveAllMode, ETH_MACFilterConfigTypeDef::SrcAddrFiltering, and ETH_MACFilterConfigTypeDef::SrcAddrInverseFiltering.

HAL_StatusTypeDef HAL_ETH_SetDMAConfig | ( | ETH_HandleTypeDef * | heth,
 |  | ETH_DMAConfigTypeDef * | dmaconf
 | ) |  |

Set the ETH DMA configuration.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
dmaconf,: pointer to a ETH_DMAConfigTypeDef structure that will hold the configuration of the ETH DMA.
Return values:
HAL status

Definition at line 1649 of file stm32h7xx_hal_eth.c.

References ETH_SetDMAConfig(), HAL_ETH_STATE_READY, and ETH_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_ETH_SetHashTable | ( | ETH_HandleTypeDef * | heth,
 |  | uint32_t * | pHashTable
 | ) |  |

Set the ETH Hash Table Value.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
pHashTable,: pointer to a table of two 32 bit values, that contains the 64 bits of the hash table.
Return values:
HAL status

Definition at line 1828 of file stm32h7xx_hal_eth.c.

References ETH_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_ETH_SetMACConfig | ( | ETH_HandleTypeDef * | heth,
 |  | ETH_MACConfigTypeDef * | macconf
 | ) |  |

Set the MAC configuration.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
macconf,: pointer to a ETH_MACConfigTypeDef structure that contains the configuration of the MAC.
Return values:
HAL status

Definition at line 1622 of file stm32h7xx_hal_eth.c.

References ETH_SetMACConfig(), HAL_ETH_STATE_READY, and ETH_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig | ( | ETH_HandleTypeDef * | heth,
 |  | ETH_MACFilterConfigTypeDef * | pFilterConfig
 | ) |  |

Set the ETH MAC (L2) Filters configuration.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
pFilterConfig,: pointer to a ETH_MACFilterConfigTypeDef structure that contains the configuration of the ETH MAC filters.
Return values:
HAL status

Definition at line 1727 of file stm32h7xx_hal_eth.c.

References ETH_MACFilterConfigTypeDef::BroadcastFilter, ETH_MACFilterConfigTypeDef::ControlPacketsFilter, ETH_MACFilterConfigTypeDef::DestAddrInverseFiltering, ETH_MACPFR_MASK, ETH_MACFilterConfigTypeDef::HachOrPerfectFilter, ETH_MACFilterConfigTypeDef::HashMulticast, ETH_MACFilterConfigTypeDef::HashUnicast, ETH_HandleTypeDef::Instance, ETH_MACFilterConfigTypeDef::PassAllMulticast, ETH_MACFilterConfigTypeDef::PromiscuousMode, ETH_MACFilterConfigTypeDef::ReceiveAllMode, ETH_MACFilterConfigTypeDef::SrcAddrFiltering, and ETH_MACFilterConfigTypeDef::SrcAddrInverseFiltering.

void HAL_ETH_SetMDIOClockRange ( ETH_HandleTypeDef * heth )

Configures the Clock range of ETH MDIO interface.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 1674 of file stm32h7xx_hal_eth.c.

References HAL_RCC_GetHCLKFreq(), and ETH_HandleTypeDef::Instance.

void HAL_ETH_SetRxVLANIdentifier | ( | ETH_HandleTypeDef * | heth,
 |  | uint32_t | ComparisonBits,
 |  | uint32_t | VLANIdentifier
 | ) |  |

Set the VLAN Identifier for Rx packets.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
ComparisonBits,: 12 or 16 bit comparison mode must be a value of ETH VLAN Tag Comparison
VLANIdentifier,: VLAN Identifier value
Return values:
None

Definition at line 1850 of file stm32h7xx_hal_eth.c.

References ETH_VLANTAGCOMPARISON_16BIT, and ETH_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch | ( | ETH_HandleTypeDef * | heth,
 |  | uint32_t | AddrNbr,
 |  | uint8_t * | pMACAddr
 | ) |  |

Set the source MAC Address to be matched.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
AddrNbr,: The MAC address to configure This parameter must be a value of the following: ETH_MAC_ADDRESS1 ETH_MAC_ADDRESS2 ETH_MAC_ADDRESS3
pMACAddr,: Pointer to MAC address buffer data (6 bytes)
Return values:
HAL status

Definition at line 1795 of file stm32h7xx_hal_eth.c.

References ETH_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter | ( | ETH_HandleTypeDef * | heth,
 |  | uint32_t * | pFilter,
 |  | uint32_t | Count
 | ) |  |

Set the WakeUp filter.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
pFilter,: pointer to filter registers values
Count,: number of filter registers, must be from 1 to 8.
Return values:
None.

Definition at line 1917 of file stm32h7xx_hal_eth.c.

References ETH_HandleTypeDef::Instance.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
ETH Exported Functions

ETH State and Errors functions. More...

Functions

HAL_ETH_StateTypeDef | HAL_ETH_GetState (ETH_HandleTypeDef *heth)
Returns the ETH state.
uint32_t | HAL_ETH_GetError (ETH_HandleTypeDef *heth)
Returns the ETH error code.
uint32_t | HAL_ETH_GetDMAError (ETH_HandleTypeDef *heth)
Returns the ETH DMA error code.
uint32_t | HAL_ETH_GetMACError (ETH_HandleTypeDef *heth)
Returns the ETH MAC error code.
uint32_t | HAL_ETH_GetMACWakeUpSource (ETH_HandleTypeDef *heth)
Returns the ETH MAC WakeUp event source.

Detailed Description

ETH State and Errors functions.

  ==============================================================================
                 ##### Peripheral State and Errors functions #####
  ==============================================================================
 [..]
   This subsection provides a set of functions allowing to return the State of
   ETH communication process, return Peripheral Errors occurred during communication
   process

Function Documentation

uint32_t HAL_ETH_GetDMAError ( ETH_HandleTypeDef * heth )

Returns the ETH DMA error code.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
ETH DMA Error Code

Definition at line 1992 of file stm32h7xx_hal_eth.c.

References ETH_HandleTypeDef::DMAErrorCode.

uint32_t HAL_ETH_GetError ( ETH_HandleTypeDef * heth )

Returns the ETH error code.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
ETH Error Code

Definition at line 1981 of file stm32h7xx_hal_eth.c.

References ETH_HandleTypeDef::ErrorCode.

uint32_t HAL_ETH_GetMACError ( ETH_HandleTypeDef * heth )

Returns the ETH MAC error code.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
ETH MAC Error Code

Definition at line 2003 of file stm32h7xx_hal_eth.c.

References ETH_HandleTypeDef::MACErrorCode.

uint32_t HAL_ETH_GetMACWakeUpSource ( ETH_HandleTypeDef * heth )

Returns the ETH MAC WakeUp event source.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
ETH MAC WakeUp event source

Definition at line 2014 of file stm32h7xx_hal_eth.c.

References ETH_HandleTypeDef::MACWakeUpEvent.

HAL_ETH_StateTypeDef HAL_ETH_GetState ( ETH_HandleTypeDef * heth )

Returns the ETH state.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
HAL state

Definition at line 1966 of file stm32h7xx_hal_eth.c.

References ETH_HandleTypeDef::gState, and ETH_HandleTypeDef::RxState.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Exported Types

Data Structures | Typedefs | Enumerations
ETH Exported Types
ETH

Data Structures

struct | __ETH_BufferTypeDef
ETH Buffers List structure definition. More...
struct | ETH_TxDescListTypeDef
DMA Transmit Descriptors Wrapper structure definition. More...
struct | ETH_TxPacketConfig
Transmit Packet Configuration structure definition. More...
struct | ETH_RxDescListTypeDef
DMA Receive Descriptors Wrapper structure definition. More...
struct | ETH_RxPacketInfo
Received Packet Information structure definition. More...
struct | ETH_MACConfigTypeDef
ETH MAC Configuration Structure definition. More...
struct | ETH_DMAConfigTypeDef
ETH DMA Configuration Structure definition. More...
struct | ETH_InitTypeDef
ETH Init Structure definition. More...
struct | ETH_HandleTypeDef
ETH Handle Structure definition. More...
struct | ETH_MACFilterConfigTypeDef
ETH MAC filter structure definition. More...
struct | ETH_PowerDownConfigTypeDef
ETH Power Down structure definition. More...

Typedefs

struct {
uint32_t DESC0
uint32_t DESC1
uint32_t DESC2
uint32_t DESC3
uint32_t BackupAddr0
uint32_t BackupAddr1
} ETH_DMADescTypeDef
ETH DMA Descriptor structure definition.
typedef struct __ETH_BufferTypeDef | ETH_BufferTypeDef
ETH Buffers List structure definition.

Enumerations

enum | ETH_MediaInterfaceTypeDef { HAL_ETH_MII_MODE = 0x00, HAL_ETH_RMII_MODE = 0x01 }
HAL ETH Media Interfaces enum definition. More...
enum HAL_ETH_StateTypeDef {
HAL_ETH_STATE_RESET = 0x00, HAL_ETH_STATE_READY = 0x10, HAL_ETH_STATE_BUSY = 0x23, HAL_ETH_STATE_BUSY_TX = 0x21,
HAL_ETH_STATE_BUSY_RX = 0x22, HAL_ETH_STATE_ERROR = 0xE0
}
HAL State structures definition. More...

Typedef Documentation

typedef struct __ETH_BufferTypeDef ETH_BufferTypeDef

ETH Buffers List structure definition.

typedef { ... } ETH_DMADescTypeDef

ETH DMA Descriptor structure definition.

Enumeration Type Documentation

enum ETH_MediaInterfaceTypeDef

HAL ETH Media Interfaces enum definition.

Enumerator:
HAL_ETH_MII_MODE

Media Independent Interface

HAL_ETH_RMII_MODE

Reduced Media Independent Interface

Definition at line 378 of file stm32h7xx_hal_eth.h.

enum HAL_ETH_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_ETH_STATE_RESET

Peripheral not yet Initialized or disabled

HAL_ETH_STATE_READY

Peripheral Communication started

HAL_ETH_STATE_BUSY

an internal process is ongoing

HAL_ETH_STATE_BUSY_TX

Transmission process is ongoing

HAL_ETH_STATE_BUSY_RX

Reception process is ongoing

HAL_ETH_STATE_ERROR

Error State

Definition at line 411 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: __ETH_BufferTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__ETH_BufferTypeDef Struct Reference
ETH Exported Types

ETH Buffers List structure definition. More...

#include <stm32h7xx_hal_eth.h>

Data Fields

uint8_t * | buffer
uint32_t | len
struct __ETH_BufferTypeDef * | next

Detailed Description

ETH Buffers List structure definition.

Definition at line 94 of file stm32h7xx_hal_eth.h.

Field Documentation

uint8_t* __ETH_BufferTypeDef::buffer

Definition at line 96 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataBuffer().

uint32_t __ETH_BufferTypeDef::len

Definition at line 98 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataBuffer().

struct __ETH_BufferTypeDef* __ETH_BufferTypeDef::next

Definition at line 100 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataBuffer().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_eth.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH_TxDescListTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ETH_TxDescListTypeDef Struct Reference
ETH Exported Types

DMA Transmit Descriptors Wrapper structure definition. More...

#include <stm32h7xx_hal_eth.h>

Data Fields

uint32_t | TxDesc [ETH_TX_DESC_CNT]
uint32_t | CurTxDesc

Detailed Description

DMA Transmit Descriptors Wrapper structure definition.

Definition at line 109 of file stm32h7xx_hal_eth.h.

Field Documentation

uint32_t ETH_TxDescListTypeDef::CurTxDesc

Definition at line 113 of file stm32h7xx_hal_eth.h.

Referenced by ETH_DMATxDescListInit(), ETH_Prepare_Tx_Descriptors(), HAL_ETH_Transmit(), and HAL_ETH_Transmit_IT().

uint32_t ETH_TxDescListTypeDef::TxDesc[ETH_TX_DESC_CNT]

Definition at line 111 of file stm32h7xx_hal_eth.h.

Referenced by ETH_DMATxDescListInit(), ETH_Prepare_Tx_Descriptors(), HAL_ETH_Transmit(), and HAL_ETH_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_eth.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH_TxPacketConfig Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ETH_TxPacketConfig Struct Reference
ETH Exported Types

Transmit Packet Configuration structure definition. More...

#include <stm32h7xx_hal_eth.h>

Data Fields

uint32_t | Attributes
uint32_t | Length
ETH_BufferTypeDef * TxBuffer
uint32_t | SrcAddrCtrl
uint32_t | CRCPadCtrl
uint32_t | ChecksumCtrl
uint32_t | MaxSegmentSize
uint32_t | PayloadLen
uint32_t | TCPHeaderLen
uint32_t | VlanTag
uint32_t | VlanCtrl
uint32_t | InnerVlanTag
uint32_t | InnerVlanCtrl

Detailed Description

Transmit Packet Configuration structure definition.

Definition at line 123 of file stm32h7xx_hal_eth.h.

Field Documentation

uint32_t ETH_TxPacketConfig::Attributes

Tx packet HW features capabilities. This parameter can be a combination of ETH Tx Packet Attributes

Definition at line 125 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

uint32_t ETH_TxPacketConfig::ChecksumCtrl

Specifies the checksum insertion control. This parameter can be a value of ETH Tx Packet Checksum Control

Definition at line 138 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

uint32_t ETH_TxPacketConfig::CRCPadCtrl

Specifies the CRC and Pad insertion and replacement control. This parameter can be a value of ETH Tx Packet CRC Pad Control

Definition at line 135 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

uint32_t ETH_TxPacketConfig::InnerVlanCtrl

Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled. This parameter can be a value of ETH Tx Packet Inner VLAN Control

Definition at line 159 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

uint32_t ETH_TxPacketConfig::InnerVlanTag

Sets Inner VLAN Tag only when Inner VLAN is enabled. This parameter can be a value from 0x0 to 0x3FFFF

Definition at line 156 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

uint32_t ETH_TxPacketConfig::Length

Total packet length

Definition at line 128 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

uint32_t ETH_TxPacketConfig::MaxSegmentSize

Sets TCP maximum segment size only when TCP segmentation is enabled. This parameter can be a value from 0x0 to 0x3FFF

Definition at line 141 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

uint32_t ETH_TxPacketConfig::PayloadLen

Sets Total payload length only when TCP segmentation is enabled. This parameter can be a value from 0x0 to 0x3FFFF

Definition at line 144 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

uint32_t ETH_TxPacketConfig::SrcAddrCtrl

Specifies the source address insertion control. This parameter can be a value of ETH Tx Packet Source Addr Control

Definition at line 132 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

uint32_t ETH_TxPacketConfig::TCPHeaderLen

Sets TCP header length only when TCP segmentation is enabled. This parameter can be a value from 0x5 to 0xF

Definition at line 147 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

ETH_BufferTypeDef* ETH_TxPacketConfig::TxBuffer

Tx buffers pointers

Definition at line 130 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

uint32_t ETH_TxPacketConfig::VlanCtrl

Specifies VLAN Tag insertion control only when VLAN is enabled. This parameter can be a value of ETH Tx Packet VLAN Control

Definition at line 153 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

uint32_t ETH_TxPacketConfig::VlanTag

Sets VLAN Tag only when VLAN is enabled. This parameter can be a value from 0x0 to 0xFFFF

Definition at line 150 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_eth.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH_RxDescListTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ETH_RxDescListTypeDef Struct Reference
ETH Exported Types

DMA Receive Descriptors Wrapper structure definition. More...

#include <stm32h7xx_hal_eth.h>

Data Fields

uint32_t | RxDesc [ETH_RX_DESC_CNT]
uint32_t | CurRxDesc
uint32_t | FirstAppDesc
uint32_t | AppDescNbr
uint32_t | AppContextDesc
uint32_t | ItMode

Detailed Description

DMA Receive Descriptors Wrapper structure definition.

Definition at line 170 of file stm32h7xx_hal_eth.h.

Field Documentation

uint32_t ETH_RxDescListTypeDef::AppContextDesc

Definition at line 180 of file stm32h7xx_hal_eth.h.

Referenced by ETH_DMARxDescListInit(), HAL_ETH_BuildRxDescriptors(), and HAL_ETH_IsRxDataAvailable().

uint32_t ETH_RxDescListTypeDef::AppDescNbr

Definition at line 178 of file stm32h7xx_hal_eth.h.

Referenced by ETH_DMARxDescListInit(), HAL_ETH_BuildRxDescriptors(), HAL_ETH_GetRxDataBuffer(), HAL_ETH_GetRxDataInfo(), HAL_ETH_GetRxDataLength(), and HAL_ETH_IsRxDataAvailable().

uint32_t ETH_RxDescListTypeDef::CurRxDesc

Definition at line 174 of file stm32h7xx_hal_eth.h.

Referenced by ETH_DMARxDescListInit(), and HAL_ETH_IsRxDataAvailable().

uint32_t ETH_RxDescListTypeDef::FirstAppDesc

Definition at line 176 of file stm32h7xx_hal_eth.h.

Referenced by ETH_DMARxDescListInit(), HAL_ETH_BuildRxDescriptors(), HAL_ETH_GetRxDataBuffer(), HAL_ETH_GetRxDataInfo(), HAL_ETH_GetRxDataLength(), and HAL_ETH_IsRxDataAvailable().

uint32_t ETH_RxDescListTypeDef::ItMode

Definition at line 183 of file stm32h7xx_hal_eth.h.

Referenced by ETH_DMARxDescListInit(), HAL_ETH_BuildRxDescriptors(), HAL_ETH_IsRxDataAvailable(), HAL_ETH_Start_IT(), and HAL_ETH_Stop_IT().

uint32_t ETH_RxDescListTypeDef::RxDesc[ETH_RX_DESC_CNT]

Definition at line 172 of file stm32h7xx_hal_eth.h.

Referenced by ETH_DMARxDescListInit(), HAL_ETH_BuildRxDescriptors(), HAL_ETH_DescAssignMemory(), HAL_ETH_GetRxDataBuffer(), HAL_ETH_GetRxDataInfo(), HAL_ETH_GetRxDataLength(), HAL_ETH_IsRxDataAvailable(), HAL_ETH_Start_IT(), and HAL_ETH_Stop_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_eth.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH_RxPacketInfo Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ETH_RxPacketInfo Struct Reference
ETH Exported Types

Received Packet Information structure definition. More...

#include <stm32h7xx_hal_eth.h>

Data Fields

uint32_t | SegmentCnt
uint32_t | VlanTag
uint32_t | InnerVlanTag
uint32_t | Checksum
uint32_t | HeaderType
uint32_t | PayloadType
uint32_t | MacFilterStatus
uint32_t | L3FilterStatus
uint32_t | L4FilterStatus
uint32_t | ErrorCode

Detailed Description

Received Packet Information structure definition.

Definition at line 193 of file stm32h7xx_hal_eth.h.

Field Documentation

uint32_t ETH_RxPacketInfo::Checksum

Definition at line 201 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

uint32_t ETH_RxPacketInfo::ErrorCode

Definition at line 219 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

uint32_t ETH_RxPacketInfo::HeaderType

Definition at line 204 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

uint32_t ETH_RxPacketInfo::InnerVlanTag

Definition at line 199 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

uint32_t ETH_RxPacketInfo::L3FilterStatus

Definition at line 213 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

uint32_t ETH_RxPacketInfo::L4FilterStatus

Definition at line 216 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

uint32_t ETH_RxPacketInfo::MacFilterStatus

Definition at line 210 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

uint32_t ETH_RxPacketInfo::PayloadType

Definition at line 207 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

uint32_t ETH_RxPacketInfo::SegmentCnt

Definition at line 195 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

uint32_t ETH_RxPacketInfo::VlanTag

Definition at line 197 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_eth.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH_MACConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ETH_MACConfigTypeDef Struct Reference
ETH Exported Types

ETH MAC Configuration Structure definition. More...

#include <stm32h7xx_hal_eth.h>

Data Fields

uint32_t | SourceAddrControl
FunctionalState | ChecksumOffload
uint32_t | InterPacketGapVal
FunctionalState | GiantPacketSizeLimitControl
FunctionalState | Support2KPacket
FunctionalState | CRCStripTypePacket
FunctionalState | AutomaticPadCRCStrip
FunctionalState | Watchdog
FunctionalState | Jabber
FunctionalState | JumboPacket
uint32_t | Speed
uint32_t | DuplexMode
FunctionalState | LoopbackMode
FunctionalState | CarrierSenseBeforeTransmit
FunctionalState | ReceiveOwn
FunctionalState | CarrierSenseDuringTransmit
FunctionalState | RetryTransmission
uint32_t | BackOffLimit
FunctionalState | DeferralCheck
uint32_t | PreambleLength
FunctionalState | UnicastSlowProtocolPacketDetect
FunctionalState | SlowProtocolDetect
FunctionalState | CRCCheckingRxPackets
uint32_t | GiantPacketSizeLimit
FunctionalState | ExtendedInterPacketGap
uint32_t | ExtendedInterPacketGapVal
FunctionalState | ProgrammableWatchdog
uint32_t | WatchdogTimeout
uint32_t | PauseTime
FunctionalState | ZeroQuantaPause
uint32_t | PauseLowThreshold
FunctionalState | TransmitFlowControl
FunctionalState | UnicastPausePacketDetect
FunctionalState | ReceiveFlowControl
uint32_t | TransmitQueueMode
uint32_t | ReceiveQueueMode
FunctionalState | DropTCPIPChecksumErrorPacket
FunctionalState | ForwardRxErrorPacket
FunctionalState | ForwardRxUndersizedGoodPacket

Detailed Description

ETH MAC Configuration Structure definition.

Definition at line 230 of file stm32h7xx_hal_eth.h.

Field Documentation

FunctionalState ETH_MACConfigTypeDef::AutomaticPadCRCStrip

Enables or disables the Automatic MAC Pad/CRC Stripping.

Definition at line 246 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

uint32_t ETH_MACConfigTypeDef::BackOffLimit

Selects the BackOff limit value. This parameter can be a value of ETH Back Off Limit

Definition at line 276 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::CarrierSenseBeforeTransmit

Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode.

Definition at line 268 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::CarrierSenseDuringTransmit

Enables or disables the Carrier Sense During Transmission in the Half Duplex mode

Definition at line 272 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::ChecksumOffload

Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers

Definition at line 235 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::CRCCheckingRxPackets

Enable or disables the CRC Checking for Received Packets.

Definition at line 288 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::CRCStripTypePacket

Enables or disables the CRC stripping for Type packets.

Definition at line 244 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::DeferralCheck

Enables or disables the deferral check function in Half Duplex mode.

Definition at line 279 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::DropTCPIPChecksumErrorPacket

Enables or disables Dropping of TCPIP Checksum Error Packets.

Definition at line 326 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

uint32_t ETH_MACConfigTypeDef::DuplexMode

Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode This parameter can be a value of ETH Duplex Mode

Definition at line 263 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::ExtendedInterPacketGap

Enable or disables the extended inter packet gap.

Definition at line 294 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

uint32_t ETH_MACConfigTypeDef::ExtendedInterPacketGapVal

Sets the Extended IPG between Packet during transmission. This parameter can be a value from 0x0 to 0xFF

Definition at line 296 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::ForwardRxErrorPacket

Enables or disables forwarding Error Packets.

Definition at line 328 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::ForwardRxUndersizedGoodPacket

Enables or disables forwarding Undersized Good Packets.

Definition at line 330 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

uint32_t ETH_MACConfigTypeDef::GiantPacketSizeLimit

Specifies the packet size that the MAC will declare it as Giant, If it's size is greater than the value programmed in this field in units of bytes This parameter must be a number between Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte)

Definition at line 290 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::GiantPacketSizeLimitControl

Enables or disables the Giant Packet Size Limit Control.

Definition at line 240 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

uint32_t ETH_MACConfigTypeDef::InterPacketGapVal

Sets the minimum IPG between Packet during transmission. This parameter can be a value of ETH Inter Packet Gap

Definition at line 237 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::Jabber

Enables or disables Jabber timer on Tx path When enabled, the MAC allows no more then 2048 bytes to be sent. When disabled, the MAC can send up to 16384 bytes.

Definition at line 252 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::JumboPacket

Enables or disables receiving Jumbo Packet When enabled, the MAC allows jumbo packets of 9,018 bytes without reporting a giant packet error

Definition at line 256 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::LoopbackMode

Enables or disables the loopback mode

Definition at line 266 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

uint32_t ETH_MACConfigTypeDef::PauseLowThreshold

This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet. This parameter can be a value of ETH Pause Low Threshold

Definition at line 309 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

uint32_t ETH_MACConfigTypeDef::PauseTime

This field holds the value to be used in the Pause Time field in the transmit control packet. This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF

Definition at line 304 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

uint32_t ETH_MACConfigTypeDef::PreambleLength

Selects or not the Preamble Length for Transmit packets (Full Duplex mode). This parameter can be a value of ETH Preamble Length

Definition at line 281 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::ProgrammableWatchdog

Enable or disables the Programmable Watchdog.

Definition at line 299 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::ReceiveFlowControl

Enables or disables the MAC to decodes the received Pause packet and disables its transmitter for a specified (Pause) time

Definition at line 317 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::ReceiveOwn

Enables or disables the Receive Own in Half Duplex mode.

Definition at line 270 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

uint32_t ETH_MACConfigTypeDef::ReceiveQueueMode

Specifies the Receive Queue operating mode. This parameter can be a value of ETH Receive Mode

Definition at line 323 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::RetryTransmission

Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.

Definition at line 274 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::SlowProtocolDetect

Enable or disables the Slow Protocol Detection.

Definition at line 286 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

uint32_t ETH_MACConfigTypeDef::SourceAddrControl

Selects the Source Address Insertion or Replacement Control. This parameter can be a value of ETH Source Addr Control

Definition at line 232 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

uint32_t ETH_MACConfigTypeDef::Speed

Sets the Ethernet speed: 10/100 Mbps. This parameter can be a value of ETH Speed

Definition at line 260 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::Support2KPacket

Enables or disables the IEEE 802.3as Support for 2K length Packets

Definition at line 242 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::TransmitFlowControl

Enables or disables the MAC to transmit Pause packets in Full Duplex mode or the MAC back pressure operation in Half Duplex mode

Definition at line 312 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

uint32_t ETH_MACConfigTypeDef::TransmitQueueMode

Specifies the Transmit Queue operating mode. This parameter can be a value of ETH Transmit Mode

Definition at line 320 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::UnicastPausePacketDetect

Enables or disables the MAC to detect Pause packets with unicast address of the station

Definition at line 315 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::UnicastSlowProtocolPacketDetect

Enable or disables the Detection of Slow Protocol Packets with unicast address.

Definition at line 284 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::Watchdog

Enables or disables the Watchdog timer on Rx path When enabled, the MAC allows no more then 2048 bytes to be received. When disabled, the MAC can receive up to 16384 bytes.

Definition at line 248 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

uint32_t ETH_MACConfigTypeDef::WatchdogTimeout

This field is used as watchdog timeout for a received packet This parameter can be a value of ETH Watchdog Timeout

Definition at line 301 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

FunctionalState ETH_MACConfigTypeDef::ZeroQuantaPause

Enable or disables the automatic generation of Zero Quanta Pause Control packets.

Definition at line 307 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetMACConfig(), and HAL_ETH_GetMACConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_eth.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH_DMAConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ETH_DMAConfigTypeDef Struct Reference
ETH Exported Types

ETH DMA Configuration Structure definition. More...

#include <stm32h7xx_hal_eth.h>

Data Fields

uint32_t | DMAArbitration
FunctionalState | AddressAlignedBeats
uint32_t | BurstMode
FunctionalState | RebuildINCRxBurst
FunctionalState | PBLx8Mode
uint32_t | TxDMABurstLength
FunctionalState | SecondPacketOperate
uint32_t | RxDMABurstLength
FunctionalState | FlushRxPacket
FunctionalState | TCPSegmentation
uint32_t | MaximumSegmentSize

Detailed Description

ETH DMA Configuration Structure definition.

Definition at line 339 of file stm32h7xx_hal_eth.h.

Field Documentation

FunctionalState ETH_DMAConfigTypeDef::AddressAlignedBeats

Enables or disables the AHB Master interface address aligned burst transfers on Read and Write channels

Definition at line 344 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetDMAConfig(), and HAL_ETH_GetDMAConfig().

uint32_t ETH_DMAConfigTypeDef::BurstMode

Sets the AHB Master interface burst transfers. This parameter can be a value of ETH Burst Mode

Definition at line 347 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetDMAConfig(), and HAL_ETH_GetDMAConfig().

uint32_t ETH_DMAConfigTypeDef::DMAArbitration

Sets the arbitration scheme between DMA Tx and Rx This parameter can be a value of ETH DMA Arbitration

Definition at line 341 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetDMAConfig(), and HAL_ETH_GetDMAConfig().

FunctionalState ETH_DMAConfigTypeDef::FlushRxPacket

Enables or disables the Rx Packet Flush

Definition at line 364 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetDMAConfig(), and HAL_ETH_GetDMAConfig().

uint32_t ETH_DMAConfigTypeDef::MaximumSegmentSize

Sets the maximum segment size that should be used while segmenting the packet This parameter can be a value from 0x40 to 0x3FFF

Definition at line 368 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetDMAConfig(), and HAL_ETH_GetDMAConfig().

FunctionalState ETH_DMAConfigTypeDef::PBLx8Mode

Enables or disables the PBL multiplication by eight.

Definition at line 353 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetDMAConfig(), and HAL_ETH_GetDMAConfig().

FunctionalState ETH_DMAConfigTypeDef::RebuildINCRxBurst

Enables or disables the AHB Master to rebuild the pending beats of any initiated burst transfer with INCRx and SINGLE transfers.

Definition at line 350 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetDMAConfig(), and HAL_ETH_GetDMAConfig().

uint32_t ETH_DMAConfigTypeDef::RxDMABurstLength

Indicates the maximum number of beats to be transferred in one Rx DMA transaction. This parameter can be a value of ETH Rx DMA Burst Length

Definition at line 361 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetDMAConfig(), and HAL_ETH_GetDMAConfig().

FunctionalState ETH_DMAConfigTypeDef::SecondPacketOperate

Enables or disables the Operate on second Packet mode, which allows the DMA to process a second Packet of Transmit data even before obtaining the status for the first one.

Definition at line 358 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetDMAConfig(), and HAL_ETH_GetDMAConfig().

FunctionalState ETH_DMAConfigTypeDef::TCPSegmentation

Enables or disables the TCP Segmentation

Definition at line 366 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetDMAConfig(), and HAL_ETH_GetDMAConfig().

uint32_t ETH_DMAConfigTypeDef::TxDMABurstLength

Indicates the maximum number of beats to be transferred in one Tx DMA transaction. This parameter can be a value of ETH Tx DMA Burst Length

Definition at line 355 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), ETH_SetDMAConfig(), and HAL_ETH_GetDMAConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_eth.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ETH_InitTypeDef Struct Reference
ETH Exported Types

ETH Init Structure definition. More...

#include <stm32h7xx_hal_eth.h>

Data Fields

uint8_t * | MACAddr
ETH_MediaInterfaceTypeDef MediaInterface
ETH_DMADescTypeDef * TxDesc
ETH_DMADescTypeDef * RxDesc
uint32_t | RxBuffLen

Detailed Description

ETH Init Structure definition.

Definition at line 390 of file stm32h7xx_hal_eth.h.

Field Documentation

uint8_t* ETH_InitTypeDef::MACAddr

MAC Address of used Hardware: must be pointer on an array of 6 bytes

Definition at line 393 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_Init().

ETH_MediaInterfaceTypeDef ETH_InitTypeDef::MediaInterface

Selects the MII interface or the RMII interface.

Definition at line 395 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_Init().

uint32_t ETH_InitTypeDef::RxBuffLen

Provides the length of Rx buffers size

Definition at line 401 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataBuffer(), and HAL_ETH_Init().

ETH_DMADescTypeDef* ETH_InitTypeDef::RxDesc

Provides the address of the first DMA Rx descriptor in the list

Definition at line 399 of file stm32h7xx_hal_eth.h.

Referenced by ETH_DMARxDescListInit().

ETH_DMADescTypeDef* ETH_InitTypeDef::TxDesc

Provides the address of the first DMA Tx descriptor in the list

Definition at line 397 of file stm32h7xx_hal_eth.h.

Referenced by ETH_DMATxDescListInit().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_eth.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ETH_HandleTypeDef Struct Reference
ETH Exported Types

ETH Handle Structure definition. More...

#include <stm32h7xx_hal_eth.h>

Data Fields

ETH_TypeDef * | Instance
ETH_InitTypeDef Init
ETH_TxDescListTypeDef TxDescList
ETH_RxDescListTypeDef RxDescList
HAL_LockTypeDef | Lock
__IO HAL_ETH_StateTypeDef | gState
__IO HAL_ETH_StateTypeDef | RxState
__IO uint32_t | ErrorCode
__IO uint32_t | DMAErrorCode
__IO uint32_t | MACErrorCode
__IO uint32_t | MACWakeUpEvent
__IO uint32_t | MACLPIEvent

Detailed Description

ETH Handle Structure definition.

Definition at line 427 of file stm32h7xx_hal_eth.h.

Field Documentation

__IO uint32_t ETH_HandleTypeDef::DMAErrorCode

Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs This parameter can be a combination of ETH DMA Status Flags

Definition at line 451 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetDMAError(), HAL_ETH_IRQHandler(), and HAL_ETH_Transmit().

__IO uint32_t ETH_HandleTypeDef::ErrorCode

Holds the global Error code of the ETH HAL status machine This parameter can be a value of of ETH Error Code

Definition at line 448 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_DescAssignMemory(), HAL_ETH_GetError(), HAL_ETH_Init(), HAL_ETH_IRQHandler(), HAL_ETH_Transmit(), and HAL_ETH_Transmit_IT().

__IO HAL_ETH_StateTypeDef ETH_HandleTypeDef::gState

ETH state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_ETH_StateTypeDef

Definition at line 441 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_DeInit(), HAL_ETH_GetState(), HAL_ETH_Init(), HAL_ETH_IRQHandler(), HAL_ETH_Start(), HAL_ETH_Start_IT(), HAL_ETH_Stop(), HAL_ETH_Stop_IT(), HAL_ETH_Transmit(), and HAL_ETH_Transmit_IT().

ETH_InitTypeDef ETH_HandleTypeDef::Init

Ethernet Init Configuration

Definition at line 431 of file stm32h7xx_hal_eth.h.

Referenced by ETH_DMARxDescListInit(), ETH_DMATxDescListInit(), HAL_ETH_GetRxDataBuffer(), and HAL_ETH_Init().

ETH_TypeDef* ETH_HandleTypeDef::Instance

Register base address

Definition at line 429 of file stm32h7xx_hal_eth.h.

Referenced by ETH_DMARxDescListInit(), ETH_DMATxDescListInit(), ETH_MAC_MDIO_ClkConfig(), ETH_Prepare_Tx_Descriptors(), ETH_SetDMAConfig(), ETH_SetMACConfig(), HAL_ETH_BuildRxDescriptors(), HAL_ETH_EnterPowerDownMode(), HAL_ETH_ExitPowerDownMode(), HAL_ETH_GetDMAConfig(), HAL_ETH_GetMACConfig(), HAL_ETH_GetMACFilterConfig(), HAL_ETH_Init(), HAL_ETH_IRQHandler(), HAL_ETH_ReadPHYRegister(), HAL_ETH_SetHashTable(), HAL_ETH_SetMACFilterConfig(), HAL_ETH_SetMDIOClockRange(), HAL_ETH_SetRxVLANIdentifier(), HAL_ETH_SetSourceMACAddrMatch(), HAL_ETH_SetWakeUpFilter(), HAL_ETH_Start(), HAL_ETH_Start_IT(), HAL_ETH_Stop(), HAL_ETH_Stop_IT(), HAL_ETH_Transmit(), HAL_ETH_Transmit_IT(), HAL_ETH_WritePHYRegister(), HAL_ETHEx_DisableARPOffload(), HAL_ETHEx_DisableL3L4Filtering(), HAL_ETHEx_DisableVLANProcessing(), HAL_ETHEx_EnableARPOffload(), HAL_ETHEx_EnableL3L4Filtering(), HAL_ETHEx_EnableVLANProcessing(), HAL_ETHEx_EnterLPIMode(), HAL_ETHEx_ExitLPIMode(), HAL_ETHEx_GetL3FilterConfig(), HAL_ETHEx_GetL4FilterConfig(), HAL_ETHEx_GetRxVLANConfig(), HAL_ETHEx_GetTxVLANConfig(), HAL_ETHEx_SetARPAddressMatch(), HAL_ETHEx_SetL3FilterConfig(), HAL_ETHEx_SetL4FilterConfig(), HAL_ETHEx_SetRxVLANConfig(), HAL_ETHEx_SetTxVLANConfig(), HAL_ETHEx_SetTxVLANIdentifier(), and HAL_ETHEx_SetVLANHashTable().

HAL_LockTypeDef ETH_HandleTypeDef::Lock

Locking object

Definition at line 439 of file stm32h7xx_hal_eth.h.

__IO uint32_t ETH_HandleTypeDef::MACErrorCode

Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs This parameter can be a combination of ETH MAC Rx Tx Status

Definition at line 454 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetMACError(), and HAL_ETH_IRQHandler().

__IO uint32_t ETH_HandleTypeDef::MACLPIEvent

Holds the LPI event when the an LPI status interrupt occurs. This parameter can be a value of ETHEx LPI Event

Definition at line 460 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_IRQHandler(), and HAL_ETHEx_GetMACLPIEvent().

__IO uint32_t ETH_HandleTypeDef::MACWakeUpEvent

Holds the Wake Up event when the MAC exit the power down mode This parameter can be a value of ETH MAC Wake Up Event

Definition at line 457 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetMACWakeUpSource(), and HAL_ETH_IRQHandler().

ETH_RxDescListTypeDef ETH_HandleTypeDef::RxDescList

Rx descriptor wrapper: holds all Rx descriptors list addresses and current descriptor index

Definition at line 436 of file stm32h7xx_hal_eth.h.

Referenced by ETH_DMARxDescListInit(), HAL_ETH_BuildRxDescriptors(), HAL_ETH_DescAssignMemory(), HAL_ETH_GetRxDataBuffer(), HAL_ETH_GetRxDataInfo(), HAL_ETH_GetRxDataLength(), HAL_ETH_IsRxDataAvailable(), HAL_ETH_Start_IT(), and HAL_ETH_Stop_IT().

__IO HAL_ETH_StateTypeDef ETH_HandleTypeDef::RxState

ETH state information related to Rx operations. This parameter can be a value of HAL_ETH_StateTypeDef

Definition at line 445 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetState(), HAL_ETH_Init(), HAL_ETH_SetDMAConfig(), HAL_ETH_SetMACConfig(), HAL_ETH_Start(), HAL_ETH_Start_IT(), HAL_ETH_Stop(), and HAL_ETH_Stop_IT().

ETH_TxDescListTypeDef ETH_HandleTypeDef::TxDescList

Tx descriptor wrapper: holds all Tx descriptors list addresses and current descriptor index

Definition at line 433 of file stm32h7xx_hal_eth.h.

Referenced by ETH_DMATxDescListInit(), ETH_Prepare_Tx_Descriptors(), HAL_ETH_Transmit(), and HAL_ETH_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_eth.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH_MACFilterConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ETH_MACFilterConfigTypeDef Struct Reference
ETH Exported Types

ETH MAC filter structure definition. More...

#include <stm32h7xx_hal_eth.h>

Data Fields

FunctionalState | PromiscuousMode
FunctionalState | ReceiveAllMode
FunctionalState | HachOrPerfectFilter
FunctionalState | HashUnicast
FunctionalState | HashMulticast
FunctionalState | PassAllMulticast
FunctionalState | SrcAddrFiltering
FunctionalState | SrcAddrInverseFiltering
FunctionalState | DestAddrInverseFiltering
FunctionalState | BroadcastFilter
uint32_t | ControlPacketsFilter

Detailed Description

ETH MAC filter structure definition.

Definition at line 471 of file stm32h7xx_hal_eth.h.

Field Documentation

FunctionalState ETH_MACFilterConfigTypeDef::BroadcastFilter

Enable or Disable broadcast filter

Definition at line 490 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetMACFilterConfig(), and HAL_ETH_SetMACFilterConfig().

uint32_t ETH_MACFilterConfigTypeDef::ControlPacketsFilter

Set the control packets filter This parameter can be a value of ETH Control Packets Filter

Definition at line 492 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetMACFilterConfig(), and HAL_ETH_SetMACFilterConfig().

FunctionalState ETH_MACFilterConfigTypeDef::DestAddrInverseFiltering

Enable or Disable destination address inverse filtering

Definition at line 488 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetMACFilterConfig(), and HAL_ETH_SetMACFilterConfig().

FunctionalState ETH_MACFilterConfigTypeDef::HachOrPerfectFilter

Enable or Disable Perfect filtering in addition to Hash filtering

Definition at line 476 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetMACFilterConfig(), and HAL_ETH_SetMACFilterConfig().

FunctionalState ETH_MACFilterConfigTypeDef::HashMulticast

Enable or Disable Hash filtering on multicast packets

Definition at line 480 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetMACFilterConfig(), and HAL_ETH_SetMACFilterConfig().

FunctionalState ETH_MACFilterConfigTypeDef::HashUnicast

Enable or Disable Hash filtering on unicast packets

Definition at line 478 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetMACFilterConfig(), and HAL_ETH_SetMACFilterConfig().

FunctionalState ETH_MACFilterConfigTypeDef::PassAllMulticast

Enable or Disable passing all multicast packets

Definition at line 482 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetMACFilterConfig(), and HAL_ETH_SetMACFilterConfig().

FunctionalState ETH_MACFilterConfigTypeDef::PromiscuousMode

Enable or Disable Promiscuous Mode

Definition at line 472 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetMACFilterConfig(), and HAL_ETH_SetMACFilterConfig().

FunctionalState ETH_MACFilterConfigTypeDef::ReceiveAllMode

Enable or Disable Receive All Mode

Definition at line 474 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetMACFilterConfig(), and HAL_ETH_SetMACFilterConfig().

FunctionalState ETH_MACFilterConfigTypeDef::SrcAddrFiltering

Enable or Disable source address filtering module

Definition at line 484 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetMACFilterConfig(), and HAL_ETH_SetMACFilterConfig().

FunctionalState ETH_MACFilterConfigTypeDef::SrcAddrInverseFiltering

Enable or Disable source address inverse filtering

Definition at line 486 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetMACFilterConfig(), and HAL_ETH_SetMACFilterConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_eth.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH_PowerDownConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ETH_PowerDownConfigTypeDef Struct Reference
ETH Exported Types

ETH Power Down structure definition. More...

#include <stm32h7xx_hal_eth.h>

Data Fields

FunctionalState | WakeUpPacket
FunctionalState | MagicPacket
FunctionalState | GlobalUnicast
FunctionalState | WakeUpForward

Detailed Description

ETH Power Down structure definition.

Definition at line 502 of file stm32h7xx_hal_eth.h.

Field Documentation

FunctionalState ETH_PowerDownConfigTypeDef::GlobalUnicast

Enable or Disable Global unicast packet detection in power down mode

Definition at line 507 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_EnterPowerDownMode().

FunctionalState ETH_PowerDownConfigTypeDef::MagicPacket

Enable or Disable Magic packet detection in power down mode

Definition at line 505 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_EnterPowerDownMode().

FunctionalState ETH_PowerDownConfigTypeDef::WakeUpForward

Enable or Disable Forwarding Wake up packets

Definition at line 509 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_EnterPowerDownMode().

FunctionalState ETH_PowerDownConfigTypeDef::WakeUpPacket

Enable or Disable Wake up packet detection in power down mode

Definition at line 503 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_EnterPowerDownMode().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_eth.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH DMA Tx Descriptor Bit Definition

Defines
ETH DMA Tx Descriptor Bit Definition
ETH Exported Constants

Defines

#define | ETH_DMATXNDESCRF_B1AP ((uint32_t)0xFFFFFFFF)
Bit definition of TDES0 RF register.
#define | ETH_DMATXNDESCRF_B2AP ((uint32_t)0xFFFFFFFF)
Bit definition of TDES1 RF register.
#define | ETH_DMATXNDESCRF_IOC ((uint32_t)0x80000000)
Bit definition of TDES2 RF register.
#define | ETH_DMATXNDESCRF_TTSE ((uint32_t)0x40000000)
#define | ETH_DMATXNDESCRF_B2L ((uint32_t)0x3FFF0000)
#define | ETH_DMATXNDESCRF_VTIR ((uint32_t)0x0000C000)
#define | ETH_DMATXNDESCRF_VTIR_DISABLE ((uint32_t)0x00000000)
#define | ETH_DMATXNDESCRF_VTIR_REMOVE ((uint32_t)0x00004000)
#define | ETH_DMATXNDESCRF_VTIR_INSERT ((uint32_t)0x00008000)
#define | ETH_DMATXNDESCRF_VTIR_REPLACE ((uint32_t)0x0000C000)
#define | ETH_DMATXNDESCRF_B1L ((uint32_t)0x00003FFF)
#define | ETH_DMATXNDESCRF_HL ((uint32_t)0x000003FF)
#define | ETH_DMATXNDESCRF_OWN ((uint32_t)0x80000000)
Bit definition of TDES3 RF register.
#define | ETH_DMATXNDESCRF_CTXT ((uint32_t)0x40000000)
#define | ETH_DMATXNDESCRF_FD ((uint32_t)0x20000000)
#define | ETH_DMATXNDESCRF_LD ((uint32_t)0x10000000)
#define | ETH_DMATXNDESCRF_CPC ((uint32_t)0x0C000000)
#define | ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT ((uint32_t)0x00000000)
#define | ETH_DMATXNDESCRF_CPC_CRC_INSERT ((uint32_t)0x04000000)
#define | ETH_DMATXNDESCRF_CPC_DISABLE ((uint32_t)0x08000000)
#define | ETH_DMATXNDESCRF_CPC_CRC_REPLACE ((uint32_t)0x0C000000)
#define | ETH_DMATXNDESCRF_SAIC ((uint32_t)0x03800000)
#define | ETH_DMATXNDESCRF_SAIC_DISABLE ((uint32_t)0x00000000)
#define | ETH_DMATXNDESCRF_SAIC_INSERT ((uint32_t)0x00800000)
#define | ETH_DMATXNDESCRF_SAIC_REPLACE ((uint32_t)0x01000000)
#define | ETH_DMATXNDESCRF_THL ((uint32_t)0x00780000)
#define | ETH_DMATXNDESCRF_TSE ((uint32_t)0x00040000)
#define | ETH_DMATXNDESCRF_CIC ((uint32_t)0x00030000)
#define | ETH_DMATXNDESCRF_CIC_DISABLE ((uint32_t)0x00000000)
#define | ETH_DMATXNDESCRF_CIC_IPHDR_INSERT ((uint32_t)0x00010000)
#define | ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT ((uint32_t)0x00020000)
#define | ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC ((uint32_t)0x00030000)
#define | ETH_DMATXNDESCRF_TPL ((uint32_t)0x0003FFFF)
#define | ETH_DMATXNDESCRF_FL ((uint32_t)0x00007FFF)
#define | ETH_DMATXNDESCWBF_TTSL ((uint32_t)0xFFFFFFFF)
Bit definition of TDES0 WBF register.
#define | ETH_DMATXNDESCWBF_TTSH ((uint32_t)0xFFFFFFFF)
Bit definition of TDES1 WBF register.
#define | ETH_DMATXNDESCWBF_OWN ((uint32_t)0x80000000)
Bit definition of TDES3 WBF register.
#define | ETH_DMATXNDESCWBF_CTXT ((uint32_t)0x40000000)
#define | ETH_DMATXNDESCWBF_FD ((uint32_t)0x20000000)
#define | ETH_DMATXNDESCWBF_LD ((uint32_t)0x10000000)
#define | ETH_DMATXNDESCWBF_TTSS ((uint32_t)0x00020000)
#define | ETH_DMATXNDESCWBF_DP ((uint32_t)0x04000000)
#define | ETH_DMATXNDESCWBF_TTSE ((uint32_t)0x02000000)
#define | ETH_DMATXNDESCWBF_ES ((uint32_t)0x00008000)
#define | ETH_DMATXNDESCWBF_JT ((uint32_t)0x00004000)
#define | ETH_DMATXNDESCWBF_FF ((uint32_t)0x00002000)
#define | ETH_DMATXNDESCWBF_PCE ((uint32_t)0x00001000)
#define | ETH_DMATXNDESCWBF_LCA ((uint32_t)0x00000800)
#define | ETH_DMATXNDESCWBF_NC ((uint32_t)0x00000400)
#define | ETH_DMATXNDESCWBF_LCO ((uint32_t)0x00000200)
#define | ETH_DMATXNDESCWBF_EC ((uint32_t)0x00000100)
#define | ETH_DMATXNDESCWBF_CC ((uint32_t)0x000000F0)
#define | ETH_DMATXNDESCWBF_ED ((uint32_t)0x00000008)
#define | ETH_DMATXNDESCWBF_UF ((uint32_t)0x00000004)
#define | ETH_DMATXNDESCWBF_DB ((uint32_t)0x00000002)
#define | ETH_DMATXNDESCWBF_IHE ((uint32_t)0x00000004)
#define | ETH_DMATXCDESC_TTSL ((uint32_t)0xFFFFFFFF)
Bit definition of Tx context descriptor register 0.
#define | ETH_DMATXCDESC_TTSH ((uint32_t)0xFFFFFFFF)
Bit definition of Tx context descriptor register 1.
#define | ETH_DMATXCDESC_IVT ((uint32_t)0xFFFF0000)
Bit definition of Tx context descriptor register 2.
#define | ETH_DMATXCDESC_MSS ((uint32_t)0x00003FFF)
#define | ETH_DMATXCDESC_OWN ((uint32_t)0x80000000)
Bit definition of Tx context descriptor register 3.
#define | ETH_DMATXCDESC_CTXT ((uint32_t)0x40000000)
#define | ETH_DMATXCDESC_OSTC ((uint32_t)0x08000000)
#define | ETH_DMATXCDESC_TCMSSV ((uint32_t)0x04000000)
#define | ETH_DMATXCDESC_CDE ((uint32_t)0x00800000)
#define | ETH_DMATXCDESC_IVTIR ((uint32_t)0x000C0000)
#define | ETH_DMATXCDESC_IVTIR_DISABLE ((uint32_t)0x00000000)
#define | ETH_DMATXCDESC_IVTIR_REMOVE ((uint32_t)0x00040000)
#define | ETH_DMATXCDESC_IVTIR_INSERT ((uint32_t)0x00080000)
#define | ETH_DMATXCDESC_IVTIR_REPLACE ((uint32_t)0x000C0000)
#define | ETH_DMATXCDESC_IVLTV ((uint32_t)0x00020000)
#define | ETH_DMATXCDESC_VLTV ((uint32_t)0x00010000)
#define | ETH_DMATXCDESC_VT ((uint32_t)0x0000FFFF)

Define Documentation

#define ETH_DMATXCDESC_CDE ((uint32_t)0x00800000)

Context Descriptor Error

Definition at line 678 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXCDESC_CTXT ((uint32_t)0x40000000)

Context Type

Definition at line 675 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXCDESC_IVLTV ((uint32_t)0x00020000)

Inner VLAN Tag Valid

Definition at line 684 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXCDESC_IVT ((uint32_t)0xFFFF0000)

Bit definition of Tx context descriptor register 2.

Inner VLAN Tag

Definition at line 668 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXCDESC_IVTIR ((uint32_t)0x000C0000)

Inner VLAN Tag Insert or Replace Mask

Definition at line 679 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXCDESC_IVTIR_DISABLE ((uint32_t)0x00000000)

Do not add the inner VLAN tag.

Definition at line 680 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXCDESC_IVTIR_INSERT ((uint32_t)0x00080000)

Insert the inner VLAN tag.

Definition at line 682 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXCDESC_IVTIR_REMOVE ((uint32_t)0x00040000)

Remove the inner VLAN tag from the packets before transmission.

Definition at line 681 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXCDESC_IVTIR_REPLACE ((uint32_t)0x000C0000)

Replace the inner VLAN tag.

Definition at line 683 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXCDESC_MSS ((uint32_t)0x00003FFF)

Maximum Segment Size

Definition at line 669 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXCDESC_OSTC ((uint32_t)0x08000000)

One-Step Timestamp Correction Enable

Definition at line 676 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXCDESC_OWN ((uint32_t)0x80000000)

Bit definition of Tx context descriptor register 3.

OWN bit: descriptor is owned by DMA engine

Definition at line 674 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXCDESC_TCMSSV ((uint32_t)0x04000000)

One-Step Timestamp Correction Input or MSS Valid

Definition at line 677 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXCDESC_TTSH ((uint32_t)0xFFFFFFFF)

Bit definition of Tx context descriptor register 1.

Transmit Packet Timestamp High

Definition at line 663 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXCDESC_TTSL ((uint32_t)0xFFFFFFFF)

Bit definition of Tx context descriptor register 0.

Transmit Packet Timestamp Low

Definition at line 658 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXCDESC_VLTV ((uint32_t)0x00010000)

VLAN Tag Valid

Definition at line 685 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXCDESC_VT ((uint32_t)0x0000FFFF)

VLAN Tag

Definition at line 686 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXNDESCRF_B1AP ((uint32_t)0xFFFFFFFF)

Bit definition of TDES0 RF register.

Transmit Packet Timestamp Low

Definition at line 545 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCRF_B1L ((uint32_t)0x00003FFF)

Buffer 1 Length

Definition at line 563 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXNDESCRF_B2AP ((uint32_t)0xFFFFFFFF)

Bit definition of TDES1 RF register.

Transmit Packet Timestamp High

Definition at line 550 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCRF_B2L ((uint32_t)0x3FFF0000)

Buffer 2 Length

Definition at line 557 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXNDESCRF_CIC ((uint32_t)0x00030000)

Checksum Insertion Control: 4 cases

Definition at line 584 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXNDESCRF_CIC_DISABLE ((uint32_t)0x00000000)

Do Nothing: Checksum Engine is disabled

Definition at line 585 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT ((uint32_t)0x00010000)

Only IP header checksum calculation and insertion are enabled.

Definition at line 586 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT ((uint32_t)0x00020000)

IP header checksum and payload checksum calculation and insertion are enabled, but pseudo header checksum is not calculated in hardware

Definition at line 587 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC ((uint32_t)0x00030000)

IP Header checksum and payload checksum calculation and insertion are enabled, and pseudo header checksum is calculated in hardware.

Definition at line 589 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCRF_CPC ((uint32_t)0x0C000000)

CRC Pad Control mask

Definition at line 573 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXNDESCRF_CPC_CRC_INSERT ((uint32_t)0x04000000)

CRC Pad Control: CRC Insertion (Disable Pad Insertion)

Definition at line 575 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCRF_CPC_CRC_REPLACE ((uint32_t)0x0C000000)

CRC Pad Control: CRC Replacement

Definition at line 577 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT ((uint32_t)0x00000000)

CRC Pad Control: CRC and Pad Insertion

Definition at line 574 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCRF_CPC_DISABLE ((uint32_t)0x08000000)

CRC Pad Control: Disable CRC Insertion

Definition at line 576 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCRF_CTXT ((uint32_t)0x40000000)

Context Type

Definition at line 570 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXNDESCRF_FD ((uint32_t)0x20000000)

First Descriptor

Definition at line 571 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXNDESCRF_FL ((uint32_t)0x00007FFF)

Transmit End of Ring

Definition at line 592 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXNDESCRF_HL ((uint32_t)0x000003FF)

Header Length

Definition at line 564 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCRF_IOC ((uint32_t)0x80000000)

Bit definition of TDES2 RF register.

Interrupt on Completion

Definition at line 555 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXNDESCRF_LD ((uint32_t)0x10000000)

Last Descriptor

Definition at line 572 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXNDESCRF_OWN ((uint32_t)0x80000000)

Bit definition of TDES3 RF register.

OWN bit: descriptor is owned by DMA engine

Definition at line 569 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXNDESCRF_SAIC ((uint32_t)0x03800000)

SA Insertion Control mask

Definition at line 578 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXNDESCRF_SAIC_DISABLE ((uint32_t)0x00000000)

SA Insertion Control: Do not include the source address

Definition at line 579 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCRF_SAIC_INSERT ((uint32_t)0x00800000)

SA Insertion Control: Include or insert the source address

Definition at line 580 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCRF_SAIC_REPLACE ((uint32_t)0x01000000)

SA Insertion Control: Replace the source address

Definition at line 581 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCRF_THL ((uint32_t)0x00780000)

TCP Header Length

Definition at line 582 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXNDESCRF_TPL ((uint32_t)0x0003FFFF)

TCP Payload Length

Definition at line 591 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXNDESCRF_TSE ((uint32_t)0x00040000)

TCP segmentation enable

Definition at line 583 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXNDESCRF_TTSE ((uint32_t)0x40000000)

Transmit Timestamp Enable

Definition at line 556 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCRF_VTIR ((uint32_t)0x0000C000)

VLAN Tag Insertion or Replacement mask

Definition at line 558 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_DMATXNDESCRF_VTIR_DISABLE ((uint32_t)0x00000000)

Do not add a VLAN tag.

Definition at line 559 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCRF_VTIR_INSERT ((uint32_t)0x00008000)

Insert a VLAN tag.

Definition at line 561 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCRF_VTIR_REMOVE ((uint32_t)0x00004000)

Remove the VLAN tag from the packets before transmission.

Definition at line 560 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCRF_VTIR_REPLACE ((uint32_t)0x0000C000)

Replace the VLAN tag.

Definition at line 562 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCWBF_CC ((uint32_t)0x000000F0)

Collision Count

Definition at line 635 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCWBF_CTXT ((uint32_t)0x40000000)

Context Type

Definition at line 621 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCWBF_DB ((uint32_t)0x00000002)

Deferred Bit

Definition at line 638 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCWBF_DP ((uint32_t)0x04000000)

Disable Padding

Definition at line 625 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCWBF_EC ((uint32_t)0x00000100)

Excessive Collision: transmission aborted after 16 collisions

Definition at line 634 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCWBF_ED ((uint32_t)0x00000008)

Excessive Deferral

Definition at line 636 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCWBF_ES ((uint32_t)0x00008000)

Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT

Definition at line 627 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCWBF_FD ((uint32_t)0x20000000)

First Descriptor

Definition at line 622 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCWBF_FF ((uint32_t)0x00002000)

Packet Flushed: DMA/MTL flushed the packet due to SW flush

Definition at line 629 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCWBF_IHE ((uint32_t)0x00000004)

IP Header Error

Definition at line 639 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCWBF_JT ((uint32_t)0x00004000)

Jabber Timeout

Definition at line 628 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCWBF_LCA ((uint32_t)0x00000800)

Loss of Carrier: carrier lost during transmission

Definition at line 631 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCWBF_LCO ((uint32_t)0x00000200)

Late Collision: transmission aborted due to collision

Definition at line 633 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCWBF_LD ((uint32_t)0x10000000)

Last Descriptor

Definition at line 623 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCWBF_NC ((uint32_t)0x00000400)

No Carrier: no carrier signal from the transceiver

Definition at line 632 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCWBF_OWN ((uint32_t)0x80000000)

Bit definition of TDES3 WBF register.

OWN bit: descriptor is owned by DMA engine

Definition at line 620 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors(), and HAL_ETH_Transmit().

#define ETH_DMATXNDESCWBF_PCE ((uint32_t)0x00001000)

Payload Checksum Error

Definition at line 630 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCWBF_TTSE ((uint32_t)0x02000000)

Transmit Timestamp Enable

Definition at line 626 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCWBF_TTSH ((uint32_t)0xFFFFFFFF)

Bit definition of TDES1 WBF register.

Buffer2 Address Pointer

Definition at line 615 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCWBF_TTSL ((uint32_t)0xFFFFFFFF)

Bit definition of TDES0 WBF register.

Buffer1 Address Pointer or TSO Header Address Pointer

Definition at line 610 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCWBF_TTSS ((uint32_t)0x00020000)

Tx Timestamp Status

Definition at line 624 of file stm32h7xx_hal_eth.h.

#define ETH_DMATXNDESCWBF_UF ((uint32_t)0x00000004)

Underflow Error: late data arrival from the memory

Definition at line 637 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH DMA Rx Descriptor Bit Definition

Defines
ETH DMA Rx Descriptor Bit Definition
ETH Exported Constants

Defines

#define | ETH_DMARXNDESCRF_BUF1AP ((uint32_t)0xFFFFFFFF)
Bit definition of Rx normal descriptor register 0 read format.
#define | ETH_DMARXNDESCRF_BUF2AP ((uint32_t)0xFFFFFFFF)
Bit definition of Rx normal descriptor register 2 read format.
#define | ETH_DMARXNDESCRF_OWN ((uint32_t)0x80000000)
Bit definition of Rx normal descriptor register 3 read format.
#define | ETH_DMARXNDESCRF_IOC ((uint32_t)0x40000000)
#define | ETH_DMARXNDESCRF_BUF2V ((uint32_t)0x02000000)
#define | ETH_DMARXNDESCRF_BUF1V ((uint32_t)0x01000000)
#define | ETH_DMARXNDESCWBF_IVT ((uint32_t)0xFFFF0000)
Bit definition of Rx normal descriptor register 0 write back format.
#define | ETH_DMARXNDESCWBF_OVT ((uint32_t)0x0000FFFF)
#define | ETH_DMARXNDESCWBF_OPC ((uint32_t)0xFFFF0000)
Bit definition of Rx normal descriptor register 1 write back format.
#define | ETH_DMARXNDESCWBF_TD ((uint32_t)0x00008000)
#define | ETH_DMARXNDESCWBF_TSA ((uint32_t)0x00004000)
#define | ETH_DMARXNDESCWBF_PV ((uint32_t)0x00002000)
#define | ETH_DMARXNDESCWBF_PFT ((uint32_t)0x00001000)
#define | ETH_DMARXNDESCWBF_PMT_NO ((uint32_t)0x00000000)
#define | ETH_DMARXNDESCWBF_PMT_SYNC ((uint32_t)0x00000100)
#define | ETH_DMARXNDESCWBF_PMT_FUP ((uint32_t)0x00000200)
#define | ETH_DMARXNDESCWBF_PMT_DREQ ((uint32_t)0x00000300)
#define | ETH_DMARXNDESCWBF_PMT_DRESP ((uint32_t)0x00000400)
#define | ETH_DMARXNDESCWBF_PMT_PDREQ ((uint32_t)0x00000500)
#define | ETH_DMARXNDESCWBF_PMT_PDRESP ((uint32_t)0x00000600)
#define | ETH_DMARXNDESCWBF_PMT_PDRESPFUP ((uint32_t)0x00000700)
#define | ETH_DMARXNDESCWBF_PMT_ANNOUNCE ((uint32_t)0x00000800)
#define | ETH_DMARXNDESCWBF_PMT_MANAG ((uint32_t)0x00000900)
#define | ETH_DMARXNDESCWBF_PMT_SIGN ((uint32_t)0x00000A00)
#define | ETH_DMARXNDESCWBF_PMT_RESERVED ((uint32_t)0x00000F00)
#define | ETH_DMARXNDESCWBF_IPCE ((uint32_t)0x00000080)
#define | ETH_DMARXNDESCWBF_IPCB ((uint32_t)0x00000040)
#define | ETH_DMARXNDESCWBF_IPV6 ((uint32_t)0x00000020)
#define | ETH_DMARXNDESCWBF_IPV4 ((uint32_t)0x00000010)
#define | ETH_DMARXNDESCWBF_IPHE ((uint32_t)0x00000008)
#define | ETH_DMARXNDESCWBF_PT ((uint32_t)0x00000003)
#define | ETH_DMARXNDESCWBF_PT_UNKNOWN ((uint32_t)0x00000000)
#define | ETH_DMARXNDESCWBF_PT_UDP ((uint32_t)0x00000001)
#define | ETH_DMARXNDESCWBF_PT_TCP ((uint32_t)0x00000002)
#define | ETH_DMARXNDESCWBF_PT_ICMP ((uint32_t)0x00000003)
#define | ETH_DMARXNDESCWBF_L3L4FM ((uint32_t)0x20000000)
Bit definition of Rx normal descriptor register 2 write back format.
#define | ETH_DMARXNDESCWBF_L4FM ((uint32_t)0x10000000)
#define | ETH_DMARXNDESCWBF_L3FM ((uint32_t)0x08000000)
#define | ETH_DMARXNDESCWBF_MADRM ((uint32_t)0x07F80000)
#define | ETH_DMARXNDESCWBF_HF ((uint32_t)0x00040000)
#define | ETH_DMARXNDESCWBF_DAF ((uint32_t)0x00020000)
#define | ETH_DMARXNDESCWBF_SAF ((uint32_t)0x00010000)
#define | ETH_DMARXNDESCWBF_VF ((uint32_t)0x00008000)
#define | ETH_DMARXNDESCWBF_ARPNR ((uint32_t)0x00000400)
#define | ETH_DMARXNDESCWBF_OWN ((uint32_t)0x80000000)
Bit definition of Rx normal descriptor register 3 write back format.
#define | ETH_DMARXNDESCWBF_CTXT ((uint32_t)0x40000000)
#define | ETH_DMARXNDESCWBF_FD ((uint32_t)0x20000000)
#define | ETH_DMARXNDESCWBF_LD ((uint32_t)0x10000000)
#define | ETH_DMARXNDESCWBF_RS2V ((uint32_t)0x08000000)
#define | ETH_DMARXNDESCWBF_RS1V ((uint32_t)0x04000000)
#define | ETH_DMARXNDESCWBF_RS0V ((uint32_t)0x02000000)
#define | ETH_DMARXNDESCWBF_CE ((uint32_t)0x01000000)
#define | ETH_DMARXNDESCWBF_GP ((uint32_t)0x00800000)
#define | ETH_DMARXNDESCWBF_RWT ((uint32_t)0x00400000)
#define | ETH_DMARXNDESCWBF_OE ((uint32_t)0x00200000)
#define | ETH_DMARXNDESCWBF_RE ((uint32_t)0x00100000)
#define | ETH_DMARXNDESCWBF_DE ((uint32_t)0x00080000)
#define | ETH_DMARXNDESCWBF_LT ((uint32_t)0x00070000)
#define | ETH_DMARXNDESCWBF_LT_LP ((uint32_t)0x00000000)
#define | ETH_DMARXNDESCWBF_LT_TP ((uint32_t)0x00010000)
#define | ETH_DMARXNDESCWBF_LT_ARP ((uint32_t)0x00030000)
#define | ETH_DMARXNDESCWBF_LT_VLAN ((uint32_t)0x00040000)
#define | ETH_DMARXNDESCWBF_LT_DVLAN ((uint32_t)0x00050000)
#define | ETH_DMARXNDESCWBF_LT_MAC ((uint32_t)0x00060000)
#define | ETH_DMARXNDESCWBF_LT_OAM ((uint32_t)0x00070000)
#define | ETH_DMARXNDESCWBF_ES ((uint32_t)0x00008000)
#define | ETH_DMARXNDESCWBF_PL ((uint32_t)0x00007FFF)
#define | ETH_DMARXCDESC_RTSL ((uint32_t)0xFFFFFFFF)
Bit definition of Rx context descriptor register 0.
#define | ETH_DMARXCDESC_RTSH ((uint32_t)0xFFFFFFFF)
Bit definition of Rx context descriptor register 1.
#define | ETH_DMARXCDESC_OWN ((uint32_t)0x80000000)
Bit definition of Rx context descriptor register 3.
#define | ETH_DMARXCDESC_CTXT ((uint32_t)0x40000000)

Define Documentation

#define ETH_DMARXCDESC_CTXT ((uint32_t)0x40000000)

Receive Context Descriptor

Definition at line 846 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXCDESC_OWN ((uint32_t)0x80000000)

Bit definition of Rx context descriptor register 3.

Own Bit

Definition at line 845 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXCDESC_RTSH ((uint32_t)0xFFFFFFFF)

Bit definition of Rx context descriptor register 1.

Receive Packet Timestamp High

Definition at line 840 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXCDESC_RTSL ((uint32_t)0xFFFFFFFF)

Bit definition of Rx context descriptor register 0.

Receive Packet Timestamp Low

Definition at line 835 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCRF_BUF1AP ((uint32_t)0xFFFFFFFF)

Bit definition of Rx normal descriptor register 0 read format.

Header or Buffer 1 Address Pointer

Definition at line 713 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCRF_BUF1V ((uint32_t)0x01000000)

Buffer 1 Address Valid

Definition at line 726 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_BuildRxDescriptors(), HAL_ETH_DescAssignMemory(), and HAL_ETH_IsRxDataAvailable().

#define ETH_DMARXNDESCRF_BUF2AP ((uint32_t)0xFFFFFFFF)

Bit definition of Rx normal descriptor register 2 read format.

Buffer 2 Address Pointer

Definition at line 718 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCRF_BUF2V ((uint32_t)0x02000000)

Buffer 2 Address Valid

Definition at line 725 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_BuildRxDescriptors(), HAL_ETH_DescAssignMemory(), and HAL_ETH_IsRxDataAvailable().

#define ETH_DMARXNDESCRF_IOC ((uint32_t)0x40000000)

Interrupt Enabled on Completion

Definition at line 724 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_BuildRxDescriptors(), HAL_ETH_IsRxDataAvailable(), HAL_ETH_Start_IT(), and HAL_ETH_Stop_IT().

#define ETH_DMARXNDESCRF_OWN ((uint32_t)0x80000000)

Bit definition of Rx normal descriptor register 3 read format.

OWN bit: descriptor is owned by DMA engine

Definition at line 723 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_BuildRxDescriptors(), HAL_ETH_DescAssignMemory(), and HAL_ETH_IsRxDataAvailable().

#define ETH_DMARXNDESCWBF_ARPNR ((uint32_t)0x00000400)

ARP Reply Not Generated

Definition at line 789 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_CE ((uint32_t)0x01000000)

CRC Error

Definition at line 802 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_CTXT ((uint32_t)0x40000000)

Receive Context Descriptor

Definition at line 796 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_IsRxDataAvailable().

#define ETH_DMARXNDESCWBF_DAF ((uint32_t)0x00020000)

Destination Address Filter Fail

Definition at line 786 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMARXNDESCWBF_DE ((uint32_t)0x00080000)

Dribble Bit Error

Definition at line 807 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_ES ((uint32_t)0x00008000)

Error Summary

Definition at line 816 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMARXNDESCWBF_FD ((uint32_t)0x20000000)

First Descriptor

Definition at line 797 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_IsRxDataAvailable().

#define ETH_DMARXNDESCWBF_GP ((uint32_t)0x00800000)

Giant Packet

Definition at line 803 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_HF ((uint32_t)0x00040000)

Hash Filter Status

Definition at line 785 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMARXNDESCWBF_IPCB ((uint32_t)0x00000040)

IP Checksum Bypassed

Definition at line 768 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMARXNDESCWBF_IPCE ((uint32_t)0x00000080)

IP Payload Error

Definition at line 767 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMARXNDESCWBF_IPHE ((uint32_t)0x00000008)

IP Header Error

Definition at line 771 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMARXNDESCWBF_IPV4 ((uint32_t)0x00000010)

IPv4 header Present

Definition at line 770 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMARXNDESCWBF_IPV6 ((uint32_t)0x00000020)

IPv6 header Present

Definition at line 769 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMARXNDESCWBF_IVT ((uint32_t)0xFFFF0000)

Bit definition of Rx normal descriptor register 0 write back format.

Inner VLAN Tag

Definition at line 744 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMARXNDESCWBF_L3FM ((uint32_t)0x08000000)

Layer 3 Filter Match

Definition at line 783 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMARXNDESCWBF_L3L4FM ((uint32_t)0x20000000)

Bit definition of Rx normal descriptor register 2 write back format.

L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched

Definition at line 781 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMARXNDESCWBF_L4FM ((uint32_t)0x10000000)

Layer 4 Filter Match

Definition at line 782 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMARXNDESCWBF_LD ((uint32_t)0x10000000)

Last Descriptor

Definition at line 798 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_IsRxDataAvailable().

#define ETH_DMARXNDESCWBF_LT ((uint32_t)0x00070000)

Length/Type Field

Definition at line 808 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMARXNDESCWBF_LT_ARP ((uint32_t)0x00030000)

The packet is a ARP Request packet type

Definition at line 811 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_LT_DVLAN ((uint32_t)0x00050000)

The packet is a type packet with Double VLAN Tag

Definition at line 813 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMARXNDESCWBF_LT_LP ((uint32_t)0x00000000)

The packet is a length packet

Definition at line 809 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_LT_MAC ((uint32_t)0x00060000)

The packet is a MAC Control packet type

Definition at line 814 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_LT_OAM ((uint32_t)0x00070000)

The packet is a OAM packet type

Definition at line 815 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_LT_TP ((uint32_t)0x00010000)

The packet is a type packet

Definition at line 810 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_LT_VLAN ((uint32_t)0x00040000)

The packet is a type packet with VLAN Tag

Definition at line 812 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMARXNDESCWBF_MADRM ((uint32_t)0x07F80000)

MAC Address Match or Hash Value

Definition at line 784 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_OE ((uint32_t)0x00200000)

Overflow Error

Definition at line 805 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_OPC ((uint32_t)0xFFFF0000)

Bit definition of Rx normal descriptor register 1 write back format.

OAM Sub-Type Code, or MAC Control Packet opcode

Definition at line 750 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_OVT ((uint32_t)0x0000FFFF)

Outer VLAN Tag

Definition at line 745 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMARXNDESCWBF_OWN ((uint32_t)0x80000000)

Bit definition of Rx normal descriptor register 3 write back format.

Own Bit

Definition at line 795 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_IsRxDataAvailable().

#define ETH_DMARXNDESCWBF_PFT ((uint32_t)0x00001000)

PTP Packet Type

Definition at line 754 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_PL ((uint32_t)0x00007FFF)

Packet Length

Definition at line 817 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataBuffer(), and HAL_ETH_GetRxDataLength().

#define ETH_DMARXNDESCWBF_PMT_ANNOUNCE ((uint32_t)0x00000800)

PTP Message Type: Announce

Definition at line 763 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_PMT_DREQ ((uint32_t)0x00000300)

PTP Message Type: Delay_Req (all clock types)

Definition at line 758 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_PMT_DRESP ((uint32_t)0x00000400)

PTP Message Type: Delay_Resp (all clock types)

Definition at line 759 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_PMT_FUP ((uint32_t)0x00000200)

PTP Message Type: Follow_Up (all clock types)

Definition at line 757 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_PMT_MANAG ((uint32_t)0x00000900)

PTP Message Type: Management

Definition at line 764 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_PMT_NO ((uint32_t)0x00000000)

PTP Message Type: No PTP message received

Definition at line 755 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_PMT_PDREQ ((uint32_t)0x00000500)

PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock)

Definition at line 760 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_PMT_PDRESP ((uint32_t)0x00000600)

PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock)

Definition at line 761 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_PMT_PDRESPFUP ((uint32_t)0x00000700)

PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock)

Definition at line 762 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_PMT_RESERVED ((uint32_t)0x00000F00)

PTP Message Type: PTP packet with Reserved message type

Definition at line 766 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_PMT_SIGN ((uint32_t)0x00000A00)

PTP Message Type: Signaling

Definition at line 765 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_PMT_SYNC ((uint32_t)0x00000100)

PTP Message Type: SYNC (all clock types)

Definition at line 756 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_PT ((uint32_t)0x00000003)

Payload Type mask

Definition at line 772 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMARXNDESCWBF_PT_ICMP ((uint32_t)0x00000003)

Payload Type: ICMP

Definition at line 776 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_PT_TCP ((uint32_t)0x00000002)

Payload Type: TCP

Definition at line 775 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_PT_UDP ((uint32_t)0x00000001)

Payload Type: UDP

Definition at line 774 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_PT_UNKNOWN ((uint32_t)0x00000000)

Payload Type: Unknown type or IP/AV payload not processed

Definition at line 773 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_PV ((uint32_t)0x00002000)

PTP Version

Definition at line 753 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_RE ((uint32_t)0x00100000)

Receive Error

Definition at line 806 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_RS0V ((uint32_t)0x02000000)

Receive Status RDES0 Valid

Definition at line 801 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMARXNDESCWBF_RS1V ((uint32_t)0x04000000)

Receive Status RDES1 Valid

Definition at line 800 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMARXNDESCWBF_RS2V ((uint32_t)0x08000000)

Receive Status RDES2 Valid

Definition at line 799 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMARXNDESCWBF_RWT ((uint32_t)0x00400000)

Receive Watchdog Timeout

Definition at line 804 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_SAF ((uint32_t)0x00010000)

SA Address Filter Fail

Definition at line 787 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMARXNDESCWBF_TD ((uint32_t)0x00008000)

Timestamp Dropped

Definition at line 751 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_TSA ((uint32_t)0x00004000)

Timestamp Available

Definition at line 752 of file stm32h7xx_hal_eth.h.

#define ETH_DMARXNDESCWBF_VF ((uint32_t)0x00008000)

VLAN Filter Status

Definition at line 788 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_GetRxDataInfo().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH frame settings

Defines
ETH frame settings
ETH Exported Constants

Defines

#define | ETH_MAX_PACKET_SIZE ((uint32_t)1528)
#define | ETH_HEADER ((uint32_t)14)
#define | ETH_CRC ((uint32_t)4)
#define | ETH_VLAN_TAG ((uint32_t)4)
#define | ETH_MIN_PAYLOAD ((uint32_t)46)
#define | ETH_MAX_PAYLOAD ((uint32_t)1500)
#define | ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000)

Define Documentation

#define ETH_CRC ((uint32_t)4)

Ethernet CRC

Definition at line 857 of file stm32h7xx_hal_eth.h.

#define ETH_HEADER ((uint32_t)14)

6 byte Dest addr, 6 byte Src addr, 2 byte length/type

Definition at line 856 of file stm32h7xx_hal_eth.h.

#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000)

Jumbo frame payload size

Definition at line 861 of file stm32h7xx_hal_eth.h.

#define ETH_MAX_PACKET_SIZE ((uint32_t)1528)

ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC

Definition at line 855 of file stm32h7xx_hal_eth.h.

#define ETH_MAX_PAYLOAD ((uint32_t)1500)

Maximum Ethernet payload size

Definition at line 860 of file stm32h7xx_hal_eth.h.

#define ETH_MIN_PAYLOAD ((uint32_t)46)

Minimum Ethernet payload size

Definition at line 859 of file stm32h7xx_hal_eth.h.

#define ETH_VLAN_TAG ((uint32_t)4)

optional 802.1q VLAN Tag

Definition at line 858 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Error Code

Defines
ETH Error Code
ETH Exported Constants

Defines

#define | HAL_ETH_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_ETH_ERROR_PARAM ((uint32_t)0x00000001U)
#define | HAL_ETH_ERROR_BUSY ((uint32_t)0x00000002U)
#define | HAL_ETH_ERROR_TIMEOUT ((uint32_t)0x00000004U)
#define | HAL_ETH_ERROR_DMA ((uint32_t)0x00000008U)
#define | HAL_ETH_ERROR_MAC ((uint32_t)0x00000010U)

Define Documentation

#define HAL_ETH_ERROR_BUSY ((uint32_t)0x00000002U)

Parameter error

Definition at line 871 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors(), HAL_ETH_Transmit(), and HAL_ETH_Transmit_IT().

#define HAL_ETH_ERROR_DMA ((uint32_t)0x00000008U)

DMA transfer error

Definition at line 873 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_IRQHandler(), and HAL_ETH_Transmit().

#define HAL_ETH_ERROR_MAC ((uint32_t)0x00000010U)

MAC transfer error

Definition at line 874 of file stm32h7xx_hal_eth.h.

#define HAL_ETH_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 869 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors(), HAL_ETH_Init(), HAL_ETH_IRQHandler(), HAL_ETH_Transmit(), and HAL_ETH_Transmit_IT().

#define HAL_ETH_ERROR_PARAM ((uint32_t)0x00000001U)

Busy error

Definition at line 870 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_DescAssignMemory(), HAL_ETH_Init(), and HAL_ETH_Transmit().

#define HAL_ETH_ERROR_TIMEOUT ((uint32_t)0x00000004U)

Timeout error

Definition at line 872 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_Init(), and HAL_ETH_Transmit().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Tx Packet Attributes

Defines
ETH Tx Packet Attributes
ETH Exported Constants

Defines

#define | ETH_TX_PACKETS_FEATURES_CSUM ((uint32_t)0x00000001)
#define | ETH_TX_PACKETS_FEATURES_SAIC ((uint32_t)0x00000002)
#define | ETH_TX_PACKETS_FEATURES_VLANTAG ((uint32_t)0x00000004)
#define | ETH_TX_PACKETS_FEATURES_INNERVLANTAG ((uint32_t)0x00000008)
#define | ETH_TX_PACKETS_FEATURES_TSO ((uint32_t)0x00000010)
#define | ETH_TX_PACKETS_FEATURES_CRCPAD ((uint32_t)0x00000020)

Define Documentation

#define ETH_TX_PACKETS_FEATURES_CRCPAD ((uint32_t)0x00000020)

Definition at line 887 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_TX_PACKETS_FEATURES_CSUM ((uint32_t)0x00000001)

Definition at line 882 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_TX_PACKETS_FEATURES_INNERVLANTAG ((uint32_t)0x00000008)

Definition at line 885 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_TX_PACKETS_FEATURES_SAIC ((uint32_t)0x00000002)

Definition at line 883 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_TX_PACKETS_FEATURES_TSO ((uint32_t)0x00000010)

Definition at line 886 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

#define ETH_TX_PACKETS_FEATURES_VLANTAG ((uint32_t)0x00000004)

Definition at line 884 of file stm32h7xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Tx Packet Source Addr Control

Defines
ETH Tx Packet Source Addr Control
ETH Exported Constants

Defines

#define | ETH_SRC_ADDR_CONTROL_DISABLE ETH_DMATXNDESCRF_SAIC_DISABLE
#define | ETH_SRC_ADDR_INSERT ETH_DMATXNDESCRF_SAIC_INSERT
#define | ETH_SRC_ADDR_REPLACE ETH_DMATXNDESCRF_SAIC_REPLACE

Define Documentation

#define ETH_SRC_ADDR_CONTROL_DISABLE ETH_DMATXNDESCRF_SAIC_DISABLE

Definition at line 895 of file stm32h7xx_hal_eth.h.

#define ETH_SRC_ADDR_INSERT ETH_DMATXNDESCRF_SAIC_INSERT

Definition at line 896 of file stm32h7xx_hal_eth.h.

#define ETH_SRC_ADDR_REPLACE ETH_DMATXNDESCRF_SAIC_REPLACE

Definition at line 897 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Tx Packet CRC Pad Control

Defines
ETH Tx Packet CRC Pad Control
ETH Exported Constants

Defines

#define | ETH_CRC_PAD_DISABLE ETH_DMATXNDESCRF_CPC_DISABLE
#define | ETH_CRC_PAD_INSERT ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT
#define | ETH_CRC_INSERT ETH_DMATXNDESCRF_CPC_CRC_INSERT
#define | ETH_CRC_REPLACE ETH_DMATXNDESCRF_CPC_CRC_REPLACE

Define Documentation

#define ETH_CRC_INSERT ETH_DMATXNDESCRF_CPC_CRC_INSERT

Definition at line 907 of file stm32h7xx_hal_eth.h.

#define ETH_CRC_PAD_DISABLE ETH_DMATXNDESCRF_CPC_DISABLE

Definition at line 905 of file stm32h7xx_hal_eth.h.

#define ETH_CRC_PAD_INSERT ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT

Definition at line 906 of file stm32h7xx_hal_eth.h.

#define ETH_CRC_REPLACE ETH_DMATXNDESCRF_CPC_CRC_REPLACE

Definition at line 908 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Tx Packet Checksum Control

Defines
ETH Tx Packet Checksum Control
ETH Exported Constants

Defines

#define | ETH_CHECKSUM_DISABLE ETH_DMATXNDESCRF_CIC_DISABLE
#define | ETH_CHECKSUM_IPHDR_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_INSERT
#define | ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT
#define | ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC

Define Documentation

#define ETH_CHECKSUM_DISABLE ETH_DMATXNDESCRF_CIC_DISABLE

Definition at line 916 of file stm32h7xx_hal_eth.h.

#define ETH_CHECKSUM_IPHDR_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_INSERT

Definition at line 917 of file stm32h7xx_hal_eth.h.

#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT

Definition at line 918 of file stm32h7xx_hal_eth.h.

#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC

Definition at line 919 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Tx Packet VLAN Control

Defines
ETH Tx Packet VLAN Control
ETH Exported Constants

Defines

#define | ETH_VLAN_DISABLE ETH_DMATXNDESCRF_VTIR_DISABLE
#define | ETH_VLAN_REMOVE ETH_DMATXNDESCRF_VTIR_REMOVE
#define | ETH_VLAN_INSERT ETH_DMATXNDESCRF_VTIR_INSERT
#define | ETH_VLAN_REPLACE ETH_DMATXNDESCRF_VTIR_REPLACE

Define Documentation

#define ETH_VLAN_DISABLE ETH_DMATXNDESCRF_VTIR_DISABLE

Definition at line 927 of file stm32h7xx_hal_eth.h.

#define ETH_VLAN_INSERT ETH_DMATXNDESCRF_VTIR_INSERT

Definition at line 929 of file stm32h7xx_hal_eth.h.

#define ETH_VLAN_REMOVE ETH_DMATXNDESCRF_VTIR_REMOVE

Definition at line 928 of file stm32h7xx_hal_eth.h.

#define ETH_VLAN_REPLACE ETH_DMATXNDESCRF_VTIR_REPLACE

Definition at line 930 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Tx Packet Inner VLAN Control

Defines
ETH Tx Packet Inner VLAN Control
ETH Exported Constants

Defines

#define | ETH_INNER_VLAN_DISABLE ETH_DMATXCDESC_IVTIR_DISABLE
#define | ETH_INNER_VLAN_REMOVE ETH_DMATXCDESC_IVTIR_REMOVE
#define | ETH_INNER_VLAN_INSERT ETH_DMATXCDESC_IVTIR_INSERT
#define | ETH_INNER_VLAN_REPLACE ETH_DMATXCDESC_IVTIR_REPLACE

Define Documentation

#define ETH_INNER_VLAN_DISABLE ETH_DMATXCDESC_IVTIR_DISABLE

Definition at line 938 of file stm32h7xx_hal_eth.h.

#define ETH_INNER_VLAN_INSERT ETH_DMATXCDESC_IVTIR_INSERT

Definition at line 940 of file stm32h7xx_hal_eth.h.

#define ETH_INNER_VLAN_REMOVE ETH_DMATXCDESC_IVTIR_REMOVE

Definition at line 939 of file stm32h7xx_hal_eth.h.

#define ETH_INNER_VLAN_REPLACE ETH_DMATXCDESC_IVTIR_REPLACE

Definition at line 941 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Rx Checksum Status

Defines
ETH Rx Checksum Status
ETH Exported Constants

Defines

#define | ETH_CHECKSUM_BYPASSED ETH_DMARXNDESCWBF_IPCB
#define | ETH_CHECKSUM_IP_HEADER_ERROR ETH_DMARXNDESCWBF_IPHE
#define | ETH_CHECKSUM_IP_PAYLOAD_ERROR ETH_DMARXNDESCWBF_IPCE

Define Documentation

#define ETH_CHECKSUM_BYPASSED ETH_DMARXNDESCWBF_IPCB

Definition at line 949 of file stm32h7xx_hal_eth.h.

#define ETH_CHECKSUM_IP_HEADER_ERROR ETH_DMARXNDESCWBF_IPHE

Definition at line 950 of file stm32h7xx_hal_eth.h.

#define ETH_CHECKSUM_IP_PAYLOAD_ERROR ETH_DMARXNDESCWBF_IPCE

Definition at line 951 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Rx IP Header Type

Defines
ETH Rx IP Header Type
ETH Exported Constants

Defines

#define | ETH_IP_HEADER_IPV4 ETH_DMARXNDESCWBF_IPV4
#define | ETH_IP_HEADER_IPV6 ETH_DMARXNDESCWBF_IPV6

Define Documentation

#define ETH_IP_HEADER_IPV4 ETH_DMARXNDESCWBF_IPV4

Definition at line 959 of file stm32h7xx_hal_eth.h.

#define ETH_IP_HEADER_IPV6 ETH_DMARXNDESCWBF_IPV6

Definition at line 960 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Rx Payload Type

Defines
ETH Rx Payload Type
ETH Exported Constants

Defines

#define | ETH_IP_PAYLOAD_UNKNOWN ETH_DMARXNDESCWBF_PT_UNKNOWN
#define | ETH_IP_PAYLOAD_UDP ETH_DMARXNDESCWBF_PT_UDP
#define | ETH_IP_PAYLOAD_TCP ETH_DMARXNDESCWBF_PT_TCP
#define | ETH_IP_PAYLOAD_ICMPN ETH_DMARXNDESCWBF_PT_ICMP

Define Documentation

#define ETH_IP_PAYLOAD_ICMPN ETH_DMARXNDESCWBF_PT_ICMP

Definition at line 971 of file stm32h7xx_hal_eth.h.

#define ETH_IP_PAYLOAD_TCP ETH_DMARXNDESCWBF_PT_TCP

Definition at line 970 of file stm32h7xx_hal_eth.h.

#define ETH_IP_PAYLOAD_UDP ETH_DMARXNDESCWBF_PT_UDP

Definition at line 969 of file stm32h7xx_hal_eth.h.

#define ETH_IP_PAYLOAD_UNKNOWN ETH_DMARXNDESCWBF_PT_UNKNOWN

Definition at line 968 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Rx MAC Filter Status

Defines
ETH Rx MAC Filter Status
ETH Exported Constants

Defines

#define | ETH_HASH_FILTER_PASS ETH_DMARXNDESCWBF_HF
#define | ETH_VLAN_FILTER_PASS ETH_DMARXNDESCWBF_VF
#define | ETH_DEST_ADDRESS_FAIL ETH_DMARXNDESCWBF_DAF
#define | ETH_SOURCE_ADDRESS_FAIL ETH_DMARXNDESCWBF_SAF

Define Documentation

#define ETH_DEST_ADDRESS_FAIL ETH_DMARXNDESCWBF_DAF

Definition at line 981 of file stm32h7xx_hal_eth.h.

#define ETH_HASH_FILTER_PASS ETH_DMARXNDESCWBF_HF

Definition at line 979 of file stm32h7xx_hal_eth.h.

#define ETH_SOURCE_ADDRESS_FAIL ETH_DMARXNDESCWBF_SAF

Definition at line 982 of file stm32h7xx_hal_eth.h.

#define ETH_VLAN_FILTER_PASS ETH_DMARXNDESCWBF_VF

Definition at line 980 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Rx L3 Filter Status

Defines
ETH Rx L3 Filter Status
ETH Exported Constants

Defines

#define | ETH_L3_FILTER0_MATCH ETH_DMARXNDESCWBF_L3FM
#define | ETH_L3_FILTER1_MATCH (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM)

Define Documentation

#define ETH_L3_FILTER0_MATCH ETH_DMARXNDESCWBF_L3FM

Definition at line 990 of file stm32h7xx_hal_eth.h.

#define ETH_L3_FILTER1_MATCH (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM)

Definition at line 991 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Rx L4 Filter Status

Defines
ETH Rx L4 Filter Status
ETH Exported Constants

Defines

#define | ETH_L4_FILTER0_MATCH ETH_DMARXNDESCWBF_L4FM
#define | ETH_L4_FILTER1_MATCH (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM)

Define Documentation

#define ETH_L4_FILTER0_MATCH ETH_DMARXNDESCWBF_L4FM

Definition at line 999 of file stm32h7xx_hal_eth.h.

#define ETH_L4_FILTER1_MATCH (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM)

Definition at line 1000 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Rx Error Code

Defines
ETH Rx Error Code
ETH Exported Constants

Defines

#define | ETH_DRIBBLE_BIT_ERROR ETH_DMARXNDESCWBF_DE
#define | ETH_RECEIVE_ERROR ETH_DMARXNDESCWBF_RE
#define | ETH_RECEIVE_OVERFLOW ETH_DMARXNDESCWBF_OE
#define | ETH_WATCHDOG_TIMEOUT ETH_DMARXNDESCWBF_RWT
#define | ETH_GIANT_PACKET ETH_DMARXNDESCWBF_GP
#define | ETH_CRC_ERROR ETH_DMARXNDESCWBF_CE

Define Documentation

#define ETH_CRC_ERROR ETH_DMARXNDESCWBF_CE

Definition at line 1013 of file stm32h7xx_hal_eth.h.

#define ETH_DRIBBLE_BIT_ERROR ETH_DMARXNDESCWBF_DE

Definition at line 1008 of file stm32h7xx_hal_eth.h.

#define ETH_GIANT_PACKET ETH_DMARXNDESCWBF_GP

Definition at line 1012 of file stm32h7xx_hal_eth.h.

#define ETH_RECEIVE_ERROR ETH_DMARXNDESCWBF_RE

Definition at line 1009 of file stm32h7xx_hal_eth.h.

#define ETH_RECEIVE_OVERFLOW ETH_DMARXNDESCWBF_OE

Definition at line 1010 of file stm32h7xx_hal_eth.h.

#define ETH_WATCHDOG_TIMEOUT ETH_DMARXNDESCWBF_RWT

Definition at line 1011 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH DMA Arbitration

Defines
ETH DMA Arbitration
ETH Exported Constants

Defines

#define | ETH_DMAARBITRATION_RX ETH_DMAMR_DA
#define | ETH_DMAARBITRATION_RX1_TX1 ((uint32_t)0x00000000)
#define | ETH_DMAARBITRATION_RX2_TX1 ETH_DMAMR_PR_2_1
#define | ETH_DMAARBITRATION_RX3_TX1 ETH_DMAMR_PR_3_1
#define | ETH_DMAARBITRATION_RX4_TX1 ETH_DMAMR_PR_4_1
#define | ETH_DMAARBITRATION_RX5_TX1 ETH_DMAMR_PR_5_1
#define | ETH_DMAARBITRATION_RX6_TX1 ETH_DMAMR_PR_6_1
#define | ETH_DMAARBITRATION_RX7_TX1 ETH_DMAMR_PR_7_1
#define | ETH_DMAARBITRATION_RX8_TX1 ETH_DMAMR_PR_8_1
#define | ETH_DMAARBITRATION_TX (ETH_DMAMR_TXPR | ETH_DMAMR_DA)
#define | ETH_DMAARBITRATION_TX1_RX1 ((uint32_t)0x00000000)
#define | ETH_DMAARBITRATION_TX2_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)
#define | ETH_DMAARBITRATION_TX3_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1)
#define | ETH_DMAARBITRATION_TX4_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1)
#define | ETH_DMAARBITRATION_TX5_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1)
#define | ETH_DMAARBITRATION_TX6_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1)
#define | ETH_DMAARBITRATION_TX7_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1)
#define | ETH_DMAARBITRATION_TX8_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1)

Define Documentation

#define ETH_DMAARBITRATION_RX ETH_DMAMR_DA

Definition at line 1021 of file stm32h7xx_hal_eth.h.

#define ETH_DMAARBITRATION_RX1_TX1 ((uint32_t)0x00000000)

Definition at line 1022 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_DMAARBITRATION_RX2_TX1 ETH_DMAMR_PR_2_1

Definition at line 1023 of file stm32h7xx_hal_eth.h.

#define ETH_DMAARBITRATION_RX3_TX1 ETH_DMAMR_PR_3_1

Definition at line 1024 of file stm32h7xx_hal_eth.h.

#define ETH_DMAARBITRATION_RX4_TX1 ETH_DMAMR_PR_4_1

Definition at line 1025 of file stm32h7xx_hal_eth.h.

#define ETH_DMAARBITRATION_RX5_TX1 ETH_DMAMR_PR_5_1

Definition at line 1026 of file stm32h7xx_hal_eth.h.

#define ETH_DMAARBITRATION_RX6_TX1 ETH_DMAMR_PR_6_1

Definition at line 1027 of file stm32h7xx_hal_eth.h.

#define ETH_DMAARBITRATION_RX7_TX1 ETH_DMAMR_PR_7_1

Definition at line 1028 of file stm32h7xx_hal_eth.h.

#define ETH_DMAARBITRATION_RX8_TX1 ETH_DMAMR_PR_8_1

Definition at line 1029 of file stm32h7xx_hal_eth.h.

#define ETH_DMAARBITRATION_TX (ETH_DMAMR_TXPR | ETH_DMAMR_DA)

Definition at line 1030 of file stm32h7xx_hal_eth.h.

#define ETH_DMAARBITRATION_TX1_RX1 ((uint32_t)0x00000000)

Definition at line 1031 of file stm32h7xx_hal_eth.h.

#define ETH_DMAARBITRATION_TX2_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)

Definition at line 1032 of file stm32h7xx_hal_eth.h.

#define ETH_DMAARBITRATION_TX3_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1)

Definition at line 1033 of file stm32h7xx_hal_eth.h.

#define ETH_DMAARBITRATION_TX4_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1)

Definition at line 1034 of file stm32h7xx_hal_eth.h.

#define ETH_DMAARBITRATION_TX5_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1)

Definition at line 1035 of file stm32h7xx_hal_eth.h.

#define ETH_DMAARBITRATION_TX6_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1)

Definition at line 1036 of file stm32h7xx_hal_eth.h.

#define ETH_DMAARBITRATION_TX7_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1)

Definition at line 1037 of file stm32h7xx_hal_eth.h.

#define ETH_DMAARBITRATION_TX8_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1)

Definition at line 1038 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Burst Mode

Defines
ETH Burst Mode
ETH Exported Constants

Defines

#define | ETH_BURSTLENGTH_FIXED ETH_DMASBMR_FB
#define | ETH_BURSTLENGTH_MIXED ETH_DMASBMR_MB
#define | ETH_BURSTLENGTH_UNSPECIFIED ((uint32_t)0x00000000)

Define Documentation

#define ETH_BURSTLENGTH_FIXED ETH_DMASBMR_FB

Definition at line 1046 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_BURSTLENGTH_MIXED ETH_DMASBMR_MB

Definition at line 1047 of file stm32h7xx_hal_eth.h.

#define ETH_BURSTLENGTH_UNSPECIFIED ((uint32_t)0x00000000)

Definition at line 1048 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Tx DMA Burst Length

Defines
ETH Tx DMA Burst Length
ETH Exported Constants

Defines

#define | ETH_TXDMABURSTLENGTH_1BEAT ETH_DMACTCR_TPBL_1PBL
#define | ETH_TXDMABURSTLENGTH_2BEAT ETH_DMACTCR_TPBL_2PBL
#define | ETH_TXDMABURSTLENGTH_4BEAT ETH_DMACTCR_TPBL_4PBL
#define | ETH_TXDMABURSTLENGTH_8BEAT ETH_DMACTCR_TPBL_8PBL
#define | ETH_TXDMABURSTLENGTH_16BEAT ETH_DMACTCR_TPBL_16PBL
#define | ETH_TXDMABURSTLENGTH_32BEAT ETH_DMACTCR_TPBL_32PBL

Define Documentation

#define ETH_TXDMABURSTLENGTH_16BEAT ETH_DMACTCR_TPBL_16PBL

Definition at line 1060 of file stm32h7xx_hal_eth.h.

#define ETH_TXDMABURSTLENGTH_1BEAT ETH_DMACTCR_TPBL_1PBL

Definition at line 1056 of file stm32h7xx_hal_eth.h.

#define ETH_TXDMABURSTLENGTH_2BEAT ETH_DMACTCR_TPBL_2PBL

Definition at line 1057 of file stm32h7xx_hal_eth.h.

#define ETH_TXDMABURSTLENGTH_32BEAT ETH_DMACTCR_TPBL_32PBL

Definition at line 1061 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_TXDMABURSTLENGTH_4BEAT ETH_DMACTCR_TPBL_4PBL

Definition at line 1058 of file stm32h7xx_hal_eth.h.

#define ETH_TXDMABURSTLENGTH_8BEAT ETH_DMACTCR_TPBL_8PBL

Definition at line 1059 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Rx DMA Burst Length

Defines
ETH Rx DMA Burst Length
ETH Exported Constants

Defines

#define | ETH_RXDMABURSTLENGTH_1BEAT ETH_DMACRCR_RPBL_1PBL
#define | ETH_RXDMABURSTLENGTH_2BEAT ETH_DMACRCR_RPBL_2PBL
#define | ETH_RXDMABURSTLENGTH_4BEAT ETH_DMACRCR_RPBL_4PBL
#define | ETH_RXDMABURSTLENGTH_8BEAT ETH_DMACRCR_RPBL_8PBL
#define | ETH_RXDMABURSTLENGTH_16BEAT ETH_DMACRCR_RPBL_16PBL
#define | ETH_RXDMABURSTLENGTH_32BEAT ETH_DMACRCR_RPBL_32PBL

Define Documentation

#define ETH_RXDMABURSTLENGTH_16BEAT ETH_DMACRCR_RPBL_16PBL

Definition at line 1073 of file stm32h7xx_hal_eth.h.

#define ETH_RXDMABURSTLENGTH_1BEAT ETH_DMACRCR_RPBL_1PBL

Definition at line 1069 of file stm32h7xx_hal_eth.h.

#define ETH_RXDMABURSTLENGTH_2BEAT ETH_DMACRCR_RPBL_2PBL

Definition at line 1070 of file stm32h7xx_hal_eth.h.

#define ETH_RXDMABURSTLENGTH_32BEAT ETH_DMACRCR_RPBL_32PBL

Definition at line 1074 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_RXDMABURSTLENGTH_4BEAT ETH_DMACRCR_RPBL_4PBL

Definition at line 1071 of file stm32h7xx_hal_eth.h.

#define ETH_RXDMABURSTLENGTH_8BEAT ETH_DMACRCR_RPBL_8PBL

Definition at line 1072 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH DMA Interrupts

Defines
ETH DMA Interrupts
ETH Exported Constants

Defines

#define | ETH_DMA_NORMAL_IT ETH_DMACIER_NIE
#define | ETH_DMA_ABNORMAL_IT ETH_DMACIER_AIE
#define | ETH_DMA_CONTEXT_DESC_ERROR_IT ETH_DMACIER_CDEE
#define | ETH_DMA_FATAL_BUS_ERROR_IT ETH_DMACIER_FBEE
#define | ETH_DMA_EARLY_RX_IT ETH_DMACIER_ERIE
#define | ETH_DMA_EARLY_TX_IT ETH_DMACIER_ETIE
#define | ETH_DMA_RX_WATCHDOG_TIMEOUT_IT ETH_DMACIER_RWTE
#define | ETH_DMA_RX_PROCESS_STOPPED_IT ETH_DMACIER_RSE
#define | ETH_DMA_RX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_RBUE
#define | ETH_DMA_RX_IT ETH_DMACIER_RIE
#define | ETH_DMA_TX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_TBUE
#define | ETH_DMA_TX_PROCESS_STOPPED_IT ETH_DMACIER_TXSE
#define | ETH_DMA_TX_IT ETH_DMACIER_TIE

Define Documentation

#define ETH_DMA_ABNORMAL_IT ETH_DMACIER_AIE

Definition at line 1083 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_CONTEXT_DESC_ERROR_IT ETH_DMACIER_CDEE

Definition at line 1084 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_EARLY_RX_IT ETH_DMACIER_ERIE

Definition at line 1086 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_EARLY_TX_IT ETH_DMACIER_ETIE

Definition at line 1087 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_FATAL_BUS_ERROR_IT ETH_DMACIER_FBEE

Definition at line 1085 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_NORMAL_IT ETH_DMACIER_NIE

Definition at line 1082 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_Stop_IT().

#define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_RBUE

Definition at line 1090 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_RX_IT ETH_DMACIER_RIE

Definition at line 1091 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_Stop_IT().

#define ETH_DMA_RX_PROCESS_STOPPED_IT ETH_DMACIER_RSE

Definition at line 1089 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT ETH_DMACIER_RWTE

Definition at line 1088 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_TBUE

Definition at line 1092 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_TX_IT ETH_DMACIER_TIE

Definition at line 1094 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_Stop_IT().

#define ETH_DMA_TX_PROCESS_STOPPED_IT ETH_DMACIER_TXSE

Definition at line 1093 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH DMA Status Flags

Defines
ETH DMA Status Flags
ETH Exported Constants

Defines

#define | ETH_DMA_RX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
#define | ETH_DMA_RX_DESC_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0)
#define | ETH_DMA_RX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1)
#define | ETH_DMA_RX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0)
#define | ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_REB_BIT_2
#define | ETH_DMA_TX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
#define | ETH_DMA_TX_DESC_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0)
#define | ETH_DMA_TX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1)
#define | ETH_DMA_TX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0)
#define | ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_TEB_BIT_2
#define | ETH_DMA_CONTEXT_DESC_ERROR_FLAG ETH_DMACSR_CDE
#define | ETH_DMA_FATAL_BUS_ERROR_FLAG ETH_DMACSR_FBE
#define | ETH_DMA_EARLY_TX_IT_FLAG ETH_DMACSR_ERI
#define | ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG ETH_DMACSR_RWT
#define | ETH_DMA_RX_PROCESS_STOPPED_FLAG ETH_DMACSR_RPS
#define | ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG ETH_DMACSR_RBU
#define | ETH_DMA_TX_PROCESS_STOPPED_FLAG ETH_DMACSR_TPS

Define Documentation

#define ETH_DMA_CONTEXT_DESC_ERROR_FLAG ETH_DMACSR_CDE

Definition at line 1112 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_EARLY_TX_IT_FLAG ETH_DMACSR_ERI

Definition at line 1114 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_FATAL_BUS_ERROR_FLAG ETH_DMACSR_FBE

Definition at line 1113 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0)

Definition at line 1105 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG ETH_DMACSR_RBU

Definition at line 1117 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_REB_BIT_2

Definition at line 1106 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_RX_DESC_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0)

Definition at line 1103 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1)

Definition at line 1104 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_RX_NO_ERROR_FLAG ((uint32_t)0x00000000U)

Definition at line 1102 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_RX_PROCESS_STOPPED_FLAG ETH_DMACSR_RPS

Definition at line 1116 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG ETH_DMACSR_RWT

Definition at line 1115 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0)

Definition at line 1110 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_TEB_BIT_2

Definition at line 1111 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_TX_DESC_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0)

Definition at line 1108 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1)

Definition at line 1109 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_TX_NO_ERROR_FLAG ((uint32_t)0x00000000U)

Definition at line 1107 of file stm32h7xx_hal_eth.h.

#define ETH_DMA_TX_PROCESS_STOPPED_FLAG ETH_DMACSR_TPS

Definition at line 1118 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Transmit Mode

Defines
ETH Transmit Mode
ETH Exported Constants

Defines

#define | ETH_TRANSMITSTOREFORWARD ETH_MTLTQOMR_TSF
#define | ETH_TRANSMITTHRESHOLD_32 ETH_MTLTQOMR_TTC_32BITS
#define | ETH_TRANSMITTHRESHOLD_64 ETH_MTLTQOMR_TTC_64BITS
#define | ETH_TRANSMITTHRESHOLD_96 ETH_MTLTQOMR_TTC_96BITS
#define | ETH_TRANSMITTHRESHOLD_128 ETH_MTLTQOMR_TTC_128BITS
#define | ETH_TRANSMITTHRESHOLD_192 ETH_MTLTQOMR_TTC_192BITS
#define | ETH_TRANSMITTHRESHOLD_256 ETH_MTLTQOMR_TTC_256BITS
#define | ETH_TRANSMITTHRESHOLD_384 ETH_MTLTQOMR_TTC_384BITS
#define | ETH_TRANSMITTHRESHOLD_512 ETH_MTLTQOMR_TTC_512BITS

Define Documentation

#define ETH_TRANSMITSTOREFORWARD ETH_MTLTQOMR_TSF

Definition at line 1126 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_TRANSMITTHRESHOLD_128 ETH_MTLTQOMR_TTC_128BITS

Definition at line 1130 of file stm32h7xx_hal_eth.h.

#define ETH_TRANSMITTHRESHOLD_192 ETH_MTLTQOMR_TTC_192BITS

Definition at line 1131 of file stm32h7xx_hal_eth.h.

#define ETH_TRANSMITTHRESHOLD_256 ETH_MTLTQOMR_TTC_256BITS

Definition at line 1132 of file stm32h7xx_hal_eth.h.

#define ETH_TRANSMITTHRESHOLD_32 ETH_MTLTQOMR_TTC_32BITS

Definition at line 1127 of file stm32h7xx_hal_eth.h.

#define ETH_TRANSMITTHRESHOLD_384 ETH_MTLTQOMR_TTC_384BITS

Definition at line 1133 of file stm32h7xx_hal_eth.h.

#define ETH_TRANSMITTHRESHOLD_512 ETH_MTLTQOMR_TTC_512BITS

Definition at line 1134 of file stm32h7xx_hal_eth.h.

#define ETH_TRANSMITTHRESHOLD_64 ETH_MTLTQOMR_TTC_64BITS

Definition at line 1128 of file stm32h7xx_hal_eth.h.

#define ETH_TRANSMITTHRESHOLD_96 ETH_MTLTQOMR_TTC_96BITS

Definition at line 1129 of file stm32h7xx_hal_eth.h.

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STM32H753xx HAL User Manual: ETH Receive Mode

Defines
ETH Receive Mode
ETH Exported Constants

Defines

#define | ETH_RECEIVESTOREFORWARD ETH_MTLRQOMR_RSF
#define | ETH_RECEIVETHRESHOLD8_64 ETH_MTLRQOMR_RTC_64BITS
#define | ETH_RECEIVETHRESHOLD8_32 ETH_MTLRQOMR_RTC_32BITS
#define | ETH_RECEIVETHRESHOLD8_96 ETH_MTLRQOMR_RTC_96BITS
#define | ETH_RECEIVETHRESHOLD8_128 ETH_MTLRQOMR_RTC_128BITS

Define Documentation

#define ETH_RECEIVESTOREFORWARD ETH_MTLRQOMR_RSF

Definition at line 1142 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_RECEIVETHRESHOLD8_128 ETH_MTLRQOMR_RTC_128BITS

Definition at line 1146 of file stm32h7xx_hal_eth.h.

#define ETH_RECEIVETHRESHOLD8_32 ETH_MTLRQOMR_RTC_32BITS

Definition at line 1144 of file stm32h7xx_hal_eth.h.

#define ETH_RECEIVETHRESHOLD8_64 ETH_MTLRQOMR_RTC_64BITS

Definition at line 1143 of file stm32h7xx_hal_eth.h.

#define ETH_RECEIVETHRESHOLD8_96 ETH_MTLRQOMR_RTC_96BITS

Definition at line 1145 of file stm32h7xx_hal_eth.h.

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STM32H753xx HAL User Manual: ETH Pause Low Threshold

Defines
ETH Pause Low Threshold
ETH Exported Constants

Defines

#define | ETH_PAUSELOWTHRESHOLD_MINUS_4 ETH_MACTFCR_PLT_MINUS4
#define | ETH_PAUSELOWTHRESHOLD_MINUS_28 ETH_MACTFCR_PLT_MINUS28
#define | ETH_PAUSELOWTHRESHOLD_MINUS_36 ETH_MACTFCR_PLT_MINUS36
#define | ETH_PAUSELOWTHRESHOLD_MINUS_144 ETH_MACTFCR_PLT_MINUS144
#define | ETH_PAUSELOWTHRESHOLD_MINUS_256 ETH_MACTFCR_PLT_MINUS256
#define | ETH_PAUSELOWTHRESHOLD_MINUS_512 ETH_MACTFCR_PLT_MINUS512

Define Documentation

#define ETH_PAUSELOWTHRESHOLD_MINUS_144 ETH_MACTFCR_PLT_MINUS144

Definition at line 1157 of file stm32h7xx_hal_eth.h.

#define ETH_PAUSELOWTHRESHOLD_MINUS_256 ETH_MACTFCR_PLT_MINUS256

Definition at line 1158 of file stm32h7xx_hal_eth.h.

#define ETH_PAUSELOWTHRESHOLD_MINUS_28 ETH_MACTFCR_PLT_MINUS28

Definition at line 1155 of file stm32h7xx_hal_eth.h.

#define ETH_PAUSELOWTHRESHOLD_MINUS_36 ETH_MACTFCR_PLT_MINUS36

Definition at line 1156 of file stm32h7xx_hal_eth.h.

#define ETH_PAUSELOWTHRESHOLD_MINUS_4 ETH_MACTFCR_PLT_MINUS4

Definition at line 1154 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_PAUSELOWTHRESHOLD_MINUS_512 ETH_MACTFCR_PLT_MINUS512

Definition at line 1159 of file stm32h7xx_hal_eth.h.

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STM32H753xx HAL User Manual: ETH Watchdog Timeout

Defines
ETH Watchdog Timeout
ETH Exported Constants

Defines

#define | ETH_WATCHDOGTIMEOUT_2KB ETH_MACWTR_WTO_2KB
#define | ETH_WATCHDOGTIMEOUT_3KB ETH_MACWTR_WTO_3KB
#define | ETH_WATCHDOGTIMEOUT_4KB ETH_MACWTR_WTO_4KB
#define | ETH_WATCHDOGTIMEOUT_5KB ETH_MACWTR_WTO_5KB
#define | ETH_WATCHDOGTIMEOUT_6KB ETH_MACWTR_WTO_6KB
#define | ETH_WATCHDOGTIMEOUT_7KB ETH_MACWTR_WTO_7KB
#define | ETH_WATCHDOGTIMEOUT_8KB ETH_MACWTR_WTO_8KB
#define | ETH_WATCHDOGTIMEOUT_9KB ETH_MACWTR_WTO_9KB
#define | ETH_WATCHDOGTIMEOUT_10KB ETH_MACWTR_WTO_10KB
#define | ETH_WATCHDOGTIMEOUT_11KB ETH_MACWTR_WTO_12KB
#define | ETH_WATCHDOGTIMEOUT_12KB ETH_MACWTR_WTO_12KB
#define | ETH_WATCHDOGTIMEOUT_13KB ETH_MACWTR_WTO_13KB
#define | ETH_WATCHDOGTIMEOUT_14KB ETH_MACWTR_WTO_14KB
#define | ETH_WATCHDOGTIMEOUT_15KB ETH_MACWTR_WTO_15KB
#define | ETH_WATCHDOGTIMEOUT_16KB ETH_MACWTR_WTO_16KB

Define Documentation

#define ETH_WATCHDOGTIMEOUT_10KB ETH_MACWTR_WTO_10KB

Definition at line 1175 of file stm32h7xx_hal_eth.h.

#define ETH_WATCHDOGTIMEOUT_11KB ETH_MACWTR_WTO_12KB

Definition at line 1176 of file stm32h7xx_hal_eth.h.

#define ETH_WATCHDOGTIMEOUT_12KB ETH_MACWTR_WTO_12KB

Definition at line 1177 of file stm32h7xx_hal_eth.h.

#define ETH_WATCHDOGTIMEOUT_13KB ETH_MACWTR_WTO_13KB

Definition at line 1178 of file stm32h7xx_hal_eth.h.

#define ETH_WATCHDOGTIMEOUT_14KB ETH_MACWTR_WTO_14KB

Definition at line 1179 of file stm32h7xx_hal_eth.h.

#define ETH_WATCHDOGTIMEOUT_15KB ETH_MACWTR_WTO_15KB

Definition at line 1180 of file stm32h7xx_hal_eth.h.

#define ETH_WATCHDOGTIMEOUT_16KB ETH_MACWTR_WTO_16KB

Definition at line 1181 of file stm32h7xx_hal_eth.h.

#define ETH_WATCHDOGTIMEOUT_2KB ETH_MACWTR_WTO_2KB

Definition at line 1167 of file stm32h7xx_hal_eth.h.

#define ETH_WATCHDOGTIMEOUT_3KB ETH_MACWTR_WTO_3KB

Definition at line 1168 of file stm32h7xx_hal_eth.h.

#define ETH_WATCHDOGTIMEOUT_4KB ETH_MACWTR_WTO_4KB

Definition at line 1169 of file stm32h7xx_hal_eth.h.

#define ETH_WATCHDOGTIMEOUT_5KB ETH_MACWTR_WTO_5KB

Definition at line 1170 of file stm32h7xx_hal_eth.h.

#define ETH_WATCHDOGTIMEOUT_6KB ETH_MACWTR_WTO_6KB

Definition at line 1171 of file stm32h7xx_hal_eth.h.

#define ETH_WATCHDOGTIMEOUT_7KB ETH_MACWTR_WTO_7KB

Definition at line 1172 of file stm32h7xx_hal_eth.h.

#define ETH_WATCHDOGTIMEOUT_8KB ETH_MACWTR_WTO_8KB

Definition at line 1173 of file stm32h7xx_hal_eth.h.

#define ETH_WATCHDOGTIMEOUT_9KB ETH_MACWTR_WTO_9KB

Definition at line 1174 of file stm32h7xx_hal_eth.h.

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STM32H753xx HAL User Manual: ETH Inter Packet Gap

Defines
ETH Inter Packet Gap
ETH Exported Constants

Defines

#define | ETH_INTERPACKETGAP_96BIT ETH_MACCR_IPG_96BIT
#define | ETH_INTERPACKETGAP_88BIT ETH_MACCR_IPG_88BIT
#define | ETH_INTERPACKETGAP_80BIT ETH_MACCR_IPG_80BIT
#define | ETH_INTERPACKETGAP_72BIT ETH_MACCR_IPG_72BIT
#define | ETH_INTERPACKETGAP_64BIT ETH_MACCR_IPG_64BIT
#define | ETH_INTERPACKETGAP_56BIT ETH_MACCR_IPG_56BIT
#define | ETH_INTERPACKETGAP_48BIT ETH_MACCR_IPG_48BIT
#define | ETH_INTERPACKETGAP_40BIT ETH_MACCR_IPG_40BIT

Define Documentation

#define ETH_INTERPACKETGAP_40BIT ETH_MACCR_IPG_40BIT

Definition at line 1196 of file stm32h7xx_hal_eth.h.

#define ETH_INTERPACKETGAP_48BIT ETH_MACCR_IPG_48BIT

Definition at line 1195 of file stm32h7xx_hal_eth.h.

#define ETH_INTERPACKETGAP_56BIT ETH_MACCR_IPG_56BIT

Definition at line 1194 of file stm32h7xx_hal_eth.h.

#define ETH_INTERPACKETGAP_64BIT ETH_MACCR_IPG_64BIT

Definition at line 1193 of file stm32h7xx_hal_eth.h.

#define ETH_INTERPACKETGAP_72BIT ETH_MACCR_IPG_72BIT

Definition at line 1192 of file stm32h7xx_hal_eth.h.

#define ETH_INTERPACKETGAP_80BIT ETH_MACCR_IPG_80BIT

Definition at line 1191 of file stm32h7xx_hal_eth.h.

#define ETH_INTERPACKETGAP_88BIT ETH_MACCR_IPG_88BIT

Definition at line 1190 of file stm32h7xx_hal_eth.h.

#define ETH_INTERPACKETGAP_96BIT ETH_MACCR_IPG_96BIT

Definition at line 1189 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

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STM32H753xx HAL User Manual: ETH Speed

Defines
ETH Speed
ETH Exported Constants

Defines

#define | ETH_SPEED_10M ((uint32_t)0x00000000)
#define | ETH_SPEED_100M ETH_MACCR_FES

Define Documentation

#define ETH_SPEED_100M ETH_MACCR_FES

Definition at line 1205 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_SPEED_10M ((uint32_t)0x00000000)

Definition at line 1204 of file stm32h7xx_hal_eth.h.

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STM32H753xx HAL User Manual: ETH Duplex Mode

Defines
ETH Duplex Mode
ETH Exported Constants

Defines

#define | ETH_FULLDUPLEX_MODE ETH_MACCR_DM
#define | ETH_HALFDUPLEX_MODE ((uint32_t)0x00000000)

Define Documentation

#define ETH_FULLDUPLEX_MODE ETH_MACCR_DM

Definition at line 1213 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_HALFDUPLEX_MODE ((uint32_t)0x00000000)

Definition at line 1214 of file stm32h7xx_hal_eth.h.

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STM32H753xx HAL User Manual: ETH Back Off Limit

Defines
ETH Back Off Limit
ETH Exported Constants

Defines

#define | ETH_BACKOFFLIMIT_10 ETH_MACCR_BL_10
#define | ETH_BACKOFFLIMIT_8 ETH_MACCR_BL_8
#define | ETH_BACKOFFLIMIT_4 ETH_MACCR_BL_4
#define | ETH_BACKOFFLIMIT_1 ETH_MACCR_BL_1

Define Documentation

#define ETH_BACKOFFLIMIT_1 ETH_MACCR_BL_1

Definition at line 1225 of file stm32h7xx_hal_eth.h.

#define ETH_BACKOFFLIMIT_10 ETH_MACCR_BL_10

Definition at line 1222 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_BACKOFFLIMIT_4 ETH_MACCR_BL_4

Definition at line 1224 of file stm32h7xx_hal_eth.h.

#define ETH_BACKOFFLIMIT_8 ETH_MACCR_BL_8

Definition at line 1223 of file stm32h7xx_hal_eth.h.

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STM32H753xx HAL User Manual: ETH Preamble Length

Defines
ETH Preamble Length
ETH Exported Constants

Defines

#define | ETH_PREAMBLELENGTH_7 ETH_MACCR_PRELEN_7
#define | ETH_PREAMBLELENGTH_5 ETH_MACCR_PRELEN_5
#define | ETH_PREAMBLELENGTH_3 ETH_MACCR_PRELEN_3

Define Documentation

#define ETH_PREAMBLELENGTH_3 ETH_MACCR_PRELEN_3

Definition at line 1235 of file stm32h7xx_hal_eth.h.

#define ETH_PREAMBLELENGTH_5 ETH_MACCR_PRELEN_5

Definition at line 1234 of file stm32h7xx_hal_eth.h.

#define ETH_PREAMBLELENGTH_7 ETH_MACCR_PRELEN_7

Definition at line 1233 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

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STM32H753xx HAL User Manual: ETH Source Addr Control

Defines
ETH Source Addr Control
ETH Exported Constants

Defines

#define | ETH_SOURCEADDRESS_DISABLE ((uint32_t)0x00000000)
#define | ETH_SOURCEADDRESS_INSERT_ADDR0 ETH_MACCR_SARC_INSADDR0
#define | ETH_SOURCEADDRESS_INSERT_ADDR1 ETH_MACCR_SARC_INSADDR1
#define | ETH_SOURCEADDRESS_REPLACE_ADDR0 ETH_MACCR_SARC_REPADDR0
#define | ETH_SOURCEADDRESS_REPLACE_ADDR1 ETH_MACCR_SARC_REPADDR1

Define Documentation

#define ETH_SOURCEADDRESS_DISABLE ((uint32_t)0x00000000)

Definition at line 1243 of file stm32h7xx_hal_eth.h.

#define ETH_SOURCEADDRESS_INSERT_ADDR0 ETH_MACCR_SARC_INSADDR0

Definition at line 1244 of file stm32h7xx_hal_eth.h.

#define ETH_SOURCEADDRESS_INSERT_ADDR1 ETH_MACCR_SARC_INSADDR1

Definition at line 1245 of file stm32h7xx_hal_eth.h.

#define ETH_SOURCEADDRESS_REPLACE_ADDR0 ETH_MACCR_SARC_REPADDR0

Definition at line 1246 of file stm32h7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_SOURCEADDRESS_REPLACE_ADDR1 ETH_MACCR_SARC_REPADDR1

Definition at line 1247 of file stm32h7xx_hal_eth.h.

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STM32H753xx HAL User Manual: ETH Control Packets Filter

Defines
ETH Control Packets Filter
ETH Exported Constants

Defines

#define | ETH_CTRLPACKETS_BLOCK_ALL ETH_MACPFR_PCF_BLOCKALL
#define | ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA
#define | ETH_CTRLPACKETS_FORWARD_ALL ETH_MACPFR_PCF_FORWARDALL
#define | ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER

Define Documentation

#define ETH_CTRLPACKETS_BLOCK_ALL ETH_MACPFR_PCF_BLOCKALL

Definition at line 1255 of file stm32h7xx_hal_eth.h.

#define ETH_CTRLPACKETS_FORWARD_ALL ETH_MACPFR_PCF_FORWARDALL

Definition at line 1257 of file stm32h7xx_hal_eth.h.

#define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA

Definition at line 1256 of file stm32h7xx_hal_eth.h.

#define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER

Definition at line 1258 of file stm32h7xx_hal_eth.h.

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STM32H753xx HAL User Manual: ETH VLAN Tag Comparison

Defines
ETH VLAN Tag Comparison
ETH Exported Constants

Defines

#define | ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U)
#define | ETH_VLANTAGCOMPARISON_12BIT ETH_MACVTR_ETV

Define Documentation

#define ETH_VLANTAGCOMPARISON_12BIT ETH_MACVTR_ETV

Definition at line 1267 of file stm32h7xx_hal_eth.h.

#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U)

Definition at line 1266 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_SetRxVLANIdentifier().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH MAC addresses

Defines
ETH MAC addresses
ETH Exported Constants

Defines

#define | ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U)
#define | ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U)
#define | ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U)
#define | ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U)

Define Documentation

#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U)

Definition at line 1275 of file stm32h7xx_hal_eth.h.

#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U)

Definition at line 1276 of file stm32h7xx_hal_eth.h.

#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U)

Definition at line 1277 of file stm32h7xx_hal_eth.h.

#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U)

Definition at line 1278 of file stm32h7xx_hal_eth.h.

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STM32H753xx HAL User Manual: ETH MAC Interrupts

Defines
ETH MAC Interrupts
ETH Exported Constants

Defines

#define | ETH_MAC_RX_STATUS_IT ETH_MACIER_RXSTSIE
#define | ETH_MAC_TX_STATUS_IT ETH_MACIER_TXSTSIE
#define | ETH_MAC_TIMESTAMP_IT ETH_MACIER_TSIE
#define | ETH_MAC_LPI_IT ETH_MACIER_LPIIE
#define | ETH_MAC_PMT_IT ETH_MACIER_PMTIE
#define | ETH_MAC_PHY_IT ETH_MACIER_PHYIE

Define Documentation

#define ETH_MAC_LPI_IT ETH_MACIER_LPIIE

Definition at line 1289 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_IRQHandler().

#define ETH_MAC_PHY_IT ETH_MACIER_PHYIE

Definition at line 1291 of file stm32h7xx_hal_eth.h.

#define ETH_MAC_PMT_IT ETH_MACIER_PMTIE

Definition at line 1290 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_IRQHandler().

#define ETH_MAC_RX_STATUS_IT ETH_MACIER_RXSTSIE

Definition at line 1286 of file stm32h7xx_hal_eth.h.

#define ETH_MAC_TIMESTAMP_IT ETH_MACIER_TSIE

Definition at line 1288 of file stm32h7xx_hal_eth.h.

#define ETH_MAC_TX_STATUS_IT ETH_MACIER_TXSTSIE

Definition at line 1287 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH MAC Wake Up Event

Defines
ETH MAC Wake Up Event
ETH Exported Constants

Defines

#define | ETH_WAKEUP_PACKET_RECIEVED ETH_MACPCSR_RWKPRCVD
#define | ETH_MAGIC_PACKET_RECIEVED ETH_MACPCSR_MGKPRCVD

Define Documentation

#define ETH_MAGIC_PACKET_RECIEVED ETH_MACPCSR_MGKPRCVD

Definition at line 1300 of file stm32h7xx_hal_eth.h.

#define ETH_WAKEUP_PACKET_RECIEVED ETH_MACPCSR_RWKPRCVD

Definition at line 1299 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH MAC Rx Tx Status

Defines
ETH MAC Rx Tx Status
ETH Exported Constants

Defines

#define | ETH_RECEIVE_WATCHDOG_TIMEOUT ETH_MACRXTXSR_RWT
#define | ETH_EXECESSIVE_COLLISIONS ETH_MACRXTXSR_EXCOL
#define | ETH_LATE_COLLISIONS ETH_MACRXTXSR_LCOL
#define | ETH_EXECESSIVE_DEFERRAL ETH_MACRXTXSR_EXDEF
#define | ETH_LOSS_OF_CARRIER ETH_MACRXTXSR_LCARR
#define | ETH_NO_CARRIER ETH_MACRXTXSR_NCARR
#define | ETH_TRANSMIT_JABBR_TIMEOUT ETH_MACRXTXSR_TJT

Define Documentation

#define ETH_EXECESSIVE_COLLISIONS ETH_MACRXTXSR_EXCOL

Definition at line 1309 of file stm32h7xx_hal_eth.h.

#define ETH_EXECESSIVE_DEFERRAL ETH_MACRXTXSR_EXDEF

Definition at line 1311 of file stm32h7xx_hal_eth.h.

#define ETH_LATE_COLLISIONS ETH_MACRXTXSR_LCOL

Definition at line 1310 of file stm32h7xx_hal_eth.h.

#define ETH_LOSS_OF_CARRIER ETH_MACRXTXSR_LCARR

Definition at line 1312 of file stm32h7xx_hal_eth.h.

#define ETH_NO_CARRIER ETH_MACRXTXSR_NCARR

Definition at line 1313 of file stm32h7xx_hal_eth.h.

#define ETH_RECEIVE_WATCHDOG_TIMEOUT ETH_MACRXTXSR_RWT

Definition at line 1308 of file stm32h7xx_hal_eth.h.

#define ETH_TRANSMIT_JABBR_TIMEOUT ETH_MACRXTXSR_TJT

Definition at line 1314 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Exported Macros

Defines
ETH Exported Macros
ETH

Defines

#define | __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
Reset ETH handle state.
#define | __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__))
Enables the specified ETHERNET DMA interrupts.
#define | __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))
Disables the specified ETHERNET DMA interrupts.
#define | __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACIER & (__INTERRUPT__)) == (__INTERRUPT__))
Gets the ETHERNET DMA IT source enabled or disabled.
#define | __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACSR & (__INTERRUPT__)) == (__INTERRUPT__))
Gets the ETHERNET DMA IT pending bit.
#define | __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))
Clears the ETHERNET DMA IT pending bit.
#define | __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))
Checks whether the specified ETHERNET DMA flag is set or not.
#define | __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))
Clears the specified ETHERNET DMA flag.
#define | __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))
Enables the specified ETHERNET MAC interrupts.
#define | __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))
Disables the specified ETHERNET MAC interrupts.
#define | __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__))
Checks whether the specified ETHERNET MAC flag is set or not.
#define | ETH_WAKEUP_EXTI_LINE ((uint32_t)0x00400000) /* !< 86 - 64 = 22 */
#define | __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI_D1->IMR3 |= (__EXTI_LINE__))
Enable the ETH WAKEUP Exti Line.
#define | __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 & (__EXTI_LINE__))
checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
#define | __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__))
Clear the ETH WAKEUP Exti flag.
#define | __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__)
enable rising edge interrupt on selected EXTI line.
#define | __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__)
enable falling edge interrupt on selected EXTI line.
#define | __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__)
enable falling edge interrupt on selected EXTI line.
#define | __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__))
Generates a Software interrupt on selected EXTI line.

Define Documentation

#define __HAL_ETH_DMA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))

Clears the specified ETHERNET DMA flag.

Parameters:
__HANDLE__,: ETH Handle
__FLAG__,: specifies the flag to check. ETH DMA Status Flags
Return values:
The state of ETH DMA FLAG (SET or RESET).

Definition at line 1390 of file stm32h7xx_hal_eth.h.

#define __HAL_ETH_DMA_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))

Clears the ETHERNET DMA IT pending bit.

Parameters:
__HANDLE__ : ETH Handle
__INTERRUPT__,: specifies the interrupt pending bit to clear. ETH DMA Interrupts
Return values:
None

Definition at line 1374 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_IRQHandler().

#define __HAL_ETH_DMA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))

Disables the specified ETHERNET DMA interrupts.

Parameters:
__HANDLE__ : ETH Handle
__INTERRUPT__,: specifies the ETHERNET DMA interrupt sources to be disabled. ETH DMA Interrupts
Return values:
None

Definition at line 1350 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_IRQHandler(), and HAL_ETH_Stop_IT().

#define __HAL_ETH_DMA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__))

Enables the specified ETHERNET DMA interrupts.

Parameters:
__HANDLE__ : ETH Handle
__INTERRUPT__,: specifies the ETHERNET DMA interrupt sources to be enabled ETH DMA Interrupts
Return values:
None

Definition at line 1341 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_Start_IT().

#define __HAL_ETH_DMA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))

Checks whether the specified ETHERNET DMA flag is set or not.

Parameters:
__HANDLE__,: ETH Handle
__FLAG__,: specifies the flag to check. ETH DMA Status Flags
Return values:
The state of ETH DMA FLAG (SET or RESET).

Definition at line 1382 of file stm32h7xx_hal_eth.h.

#define __HAL_ETH_DMA_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->DMACSR & (__INTERRUPT__)) == (__INTERRUPT__))

Gets the ETHERNET DMA IT pending bit.

Parameters:
__HANDLE__ : ETH Handle
__INTERRUPT__,: specifies the interrupt source to get . ETH DMA Interrupts
Return values:
The state of ETH DMA IT (SET or RESET)

Definition at line 1366 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_IRQHandler().

#define __HAL_ETH_DMA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->DMACIER & (__INTERRUPT__)) == (__INTERRUPT__))

Gets the ETHERNET DMA IT source enabled or disabled.

Parameters:
__HANDLE__ : ETH Handle
__INTERRUPT__,: specifies the interrupt source to get . ETH DMA Interrupts
Return values:
The ETH DMA IT Source enabled or disabled

Definition at line 1358 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_IRQHandler().

#define __HAL_ETH_MAC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))

Disables the specified ETHERNET MAC interrupts.

Parameters:
__HANDLE__ : ETH Handle
__INTERRUPT__,: specifies the ETHERNET MAC interrupt sources to be enabled ETH MAC Interrupts
Return values:
None

Definition at line 1408 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_ExitPowerDownMode(), and HAL_ETHEx_ExitLPIMode().

#define __HAL_ETH_MAC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))

Enables the specified ETHERNET MAC interrupts.

Parameters:
__HANDLE__ : ETH Handle
__INTERRUPT__,: specifies the ETHERNET MAC interrupt sources to be enabled ETH MAC Interrupts
Return values:
None

Definition at line 1399 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_EnterPowerDownMode(), and HAL_ETHEx_EnterLPIMode().

#define __HAL_ETH_MAC_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__))

Checks whether the specified ETHERNET MAC flag is set or not.

Parameters:
__HANDLE__,: ETH Handle
__INTERRUPT__,: specifies the flag to check. ETH MAC Interrupts
Return values:
The state of ETH MAC IT (SET or RESET). External interrupt line 86 Connected to the ETH wakeup EXTI Line

Definition at line 1416 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_IRQHandler().

#define __HAL_ETH_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)

Reset ETH handle state.

Parameters:
__HANDLE__,: specifies the ETH handle.
Return values:
None

Definition at line 1332 of file stm32h7xx_hal_eth.h.

#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG ( __EXTI_LINE__ ) (EXTI_D1->PR3 = (__EXTI_LINE__))

Clear the ETH WAKEUP Exti flag.

Parameters:
__EXTI_LINE__,: specifies the ETH WAKEUP Exti sources to be cleared.
  • ETH_WAKEUP_EXTI_LINE
Return values:
None.

Definition at line 1445 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_IRQHandler().

#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE ( __EXTI_LINE__ )
Value:
(EXTI->RTSR3 &= ~(__EXTI_LINE__));\
                                                                 (EXTI->FTSR3 |= (__EXTI_LINE__))

enable falling edge interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__,: specifies the ETH WAKEUP EXTI sources to be disabled.
  • ETH_WAKEUP_EXTI_LINE
Return values:
None

Definition at line 1463 of file stm32h7xx_hal_eth.h.

#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT ( __EXTI_LINE__ ) (EXTI_D1->IMR3 |= (__EXTI_LINE__))

Enable the ETH WAKEUP Exti Line.

Parameters:
__EXTI_LINE__,: specifies the ETH WAKEUP Exti sources to be enabled.
  • ETH_WAKEUP_EXTI_LINE
Return values:
None.

Definition at line 1429 of file stm32h7xx_hal_eth.h.

#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE ( __EXTI_LINE__ )
Value:
(EXTI->FTSR3 &= ~(__EXTI_LINE__)); \
                                                                (EXTI->RTSR3 |= (__EXTI_LINE__))

enable rising edge interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__,: specifies the ETH WAKEUP EXTI sources to be disabled.
  • ETH_WAKEUP_EXTI_LINE
Return values:
None

Definition at line 1454 of file stm32h7xx_hal_eth.h.

#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE ( __EXTI_LINE__ )
Value:
(EXTI->RTSR3 |= (__EXTI_LINE__));\
                                                                        (EXTI->FTSR3 |= (__EXTI_LINE__))

enable falling edge interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__,: specifies the ETH WAKEUP EXTI sources to be disabled.
  • ETH_WAKEUP_EXTI_LINE
Return values:
None

Definition at line 1472 of file stm32h7xx_hal_eth.h.

#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT ( __EXTI_LINE__ ) (EXTI->SWIER3 |= (__EXTI_LINE__))

Generates a Software interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__,: specifies the ETH WAKEUP EXTI sources to be disabled.
  • ETH_WAKEUP_EXTI_LINE
Return values:
None

Definition at line 1481 of file stm32h7xx_hal_eth.h.

#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG ( __EXTI_LINE__ ) (EXTI_D1->PR3 & (__EXTI_LINE__))

checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.

Parameters:
__EXTI_LINE__,: specifies the ETH WAKEUP Exti sources to be cleared.
  • ETH_WAKEUP_EXTI_LINE
Return values:
EXTI ETH WAKEUP Line Status.

Definition at line 1437 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_IRQHandler().

#define ETH_WAKEUP_EXTI_LINE ((uint32_t)0x00400000) /* !< 86 - 64 = 22 */

Definition at line 1421 of file stm32h7xx_hal_eth.h.

Referenced by HAL_ETH_IRQHandler().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH Private Constants

Defines
ETH Private Constants
ETH

Defines

#define | ETH_MACCR_MASK ((uint32_t)0xFFFB7F7CU)
#define | ETH_MACECR_MASK ((uint32_t)0x3F077FFFU)
#define | ETH_MACPFR_MASK ((uint32_t)0x800007FFF)
#define | ETH_MACWTR_MASK ((uint32_t)0x0000010FU)
#define | ETH_MACTFCR_MASK ((uint32_t)0xFFFF00F2U)
#define | ETH_MACRFCR_MASK ((uint32_t)0x00000003U)
#define | ETH_MTLTQOMR_MASK ((uint32_t)0x00000072U)
#define | ETH_MTLRQOMR_MASK ((uint32_t)0x0000007BU)
#define | ETH_DMAMR_MASK ((uint32_t)0x00007802U)
#define | ETH_DMASBMR_MASK ((uint32_t)0x0000D001U)
#define | ETH_DMACCR_MASK ((uint32_t)0x00013FFFU)
#define | ETH_DMACTCR_MASK ((uint32_t)0x003F1010U)
#define | ETH_DMACRCR_MASK ((uint32_t)0x803F0000U)
#define | ETH_MACPCSR_MASK
#define | ETH_SWRESET_TIMEOUT ((uint32_t)500U)
#define | ETH_MDIO_BUS_TIMEOUT ((uint32_t)1000U)
#define | ETH_DMARXNDESCWBF_ERRORS_MASK
#define | ETH_MAC_US_TICK ((uint32_t)1000000U)

Define Documentation

#define ETH_DMACCR_MASK ((uint32_t)0x00013FFFU)

Definition at line 136 of file stm32h7xx_hal_eth.c.

Referenced by ETH_SetDMAConfig().

#define ETH_DMACRCR_MASK ((uint32_t)0x803F0000U)

Definition at line 138 of file stm32h7xx_hal_eth.c.

Referenced by ETH_SetDMAConfig().

#define ETH_DMACTCR_MASK ((uint32_t)0x003F1010U)

Definition at line 137 of file stm32h7xx_hal_eth.c.

Referenced by ETH_SetDMAConfig().

#define ETH_DMAMR_MASK ((uint32_t)0x00007802U)

Definition at line 134 of file stm32h7xx_hal_eth.c.

Referenced by ETH_SetDMAConfig().

#define ETH_DMARXNDESCWBF_ERRORS_MASK
Value:
((uint32_t)(ETH_DMARXNDESCWBF_DE | ETH_DMARXNDESCWBF_RE | \
                                                  ETH_DMARXNDESCWBF_OE | ETH_DMARXNDESCWBF_RWT |\
                                                  ETH_DMARXNDESCWBF_GP | ETH_DMARXNDESCWBF_CE))

Definition at line 147 of file stm32h7xx_hal_eth.c.

Referenced by HAL_ETH_GetRxDataInfo().

#define ETH_DMASBMR_MASK ((uint32_t)0x0000D001U)

Definition at line 135 of file stm32h7xx_hal_eth.c.

Referenced by ETH_SetDMAConfig().

#define ETH_MAC_US_TICK ((uint32_t)1000000U)

Definition at line 151 of file stm32h7xx_hal_eth.c.

Referenced by HAL_ETH_Init().

#define ETH_MACCR_MASK ((uint32_t)0xFFFB7F7CU)

Definition at line 125 of file stm32h7xx_hal_eth.c.

Referenced by ETH_SetMACConfig().

#define ETH_MACECR_MASK ((uint32_t)0x3F077FFFU)

Definition at line 126 of file stm32h7xx_hal_eth.c.

Referenced by ETH_SetMACConfig().

#define ETH_MACPCSR_MASK
Value:
(ETH_MACPCSR_PWRDWN | ETH_MACPCSR_RWKPKTEN | \
                              ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | \
                              ETH_MACPCSR_RWKPFE)

Definition at line 139 of file stm32h7xx_hal_eth.c.

Referenced by HAL_ETH_EnterPowerDownMode().

#define ETH_MACPFR_MASK ((uint32_t)0x800007FFF)

Definition at line 127 of file stm32h7xx_hal_eth.c.

Referenced by HAL_ETH_SetMACFilterConfig().

#define ETH_MACRFCR_MASK ((uint32_t)0x00000003U)

Definition at line 130 of file stm32h7xx_hal_eth.c.

Referenced by ETH_SetMACConfig().

#define ETH_MACTFCR_MASK ((uint32_t)0xFFFF00F2U)

Definition at line 129 of file stm32h7xx_hal_eth.c.

Referenced by ETH_SetMACConfig().

#define ETH_MACWTR_MASK ((uint32_t)0x0000010FU)

Definition at line 128 of file stm32h7xx_hal_eth.c.

Referenced by ETH_SetMACConfig().

#define ETH_MDIO_BUS_TIMEOUT ((uint32_t)1000U)

Definition at line 145 of file stm32h7xx_hal_eth.c.

Referenced by HAL_ETH_ReadPHYRegister(), and HAL_ETH_WritePHYRegister().

#define ETH_MTLRQOMR_MASK ((uint32_t)0x0000007BU)

Definition at line 132 of file stm32h7xx_hal_eth.c.

Referenced by ETH_SetMACConfig().

#define ETH_MTLTQOMR_MASK ((uint32_t)0x00000072U)

Definition at line 131 of file stm32h7xx_hal_eth.c.

Referenced by ETH_SetMACConfig().

#define ETH_SWRESET_TIMEOUT ((uint32_t)500U)

Definition at line 144 of file stm32h7xx_hal_eth.c.

Referenced by HAL_ETH_Init().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH

Modules | Defines | Functions
ETH
STM32H7xx_HAL_Driver

ETH HAL module driver. More...

Modules

ETH Private Macros
ETH Private Functions
ETH Exported Functions
ETH Exported Types
ETH Exported Constants
ETH Exported Macros
ETH Private Constants

Defines

#define | ETH_TX_DESC_CNT 4
#define | ETH_RX_DESC_CNT 4

Functions

static void | ETH_MACDMAConfig (ETH_HandleTypeDef *heth)
Configures Ethernet MAC and DMA with default parameters.
static void | ETH_MAC_MDIO_ClkConfig (ETH_HandleTypeDef *heth)
Configures the Clock range of SMI interface.
static void | ETH_DMATxDescListInit (ETH_HandleTypeDef *heth)
Initializes the DMA Tx descriptors.
static void | ETH_DMARxDescListInit (ETH_HandleTypeDef *heth)
Initializes the DMA Rx descriptors in chain mode.
static uint32_t | ETH_Prepare_Tx_Descriptors (ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode)
Prepare Tx DMA descriptor before transmission.

Detailed Description

ETH HAL module driver.

Define Documentation

#define ETH_RX_DESC_CNT 4

Definition at line 63 of file stm32h7xx_hal_eth.h.

#define ETH_TX_DESC_CNT 4

Definition at line 59 of file stm32h7xx_hal_eth.h.

Function Documentation

static void ETH_DMARxDescListInit ( ETH_HandleTypeDef * heth ) [static]

Initializes the DMA Rx descriptors in chain mode.

called by HAL_ETH_Init() API.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 2308 of file stm32h7xx_hal_eth.c.

References ETH_RxDescListTypeDef::AppContextDesc, ETH_RxDescListTypeDef::AppDescNbr, ETH_RxDescListTypeDef::CurRxDesc, ETH_RX_DESC_CNT, ETH_RxDescListTypeDef::FirstAppDesc, ETH_HandleTypeDef::Init, ETH_HandleTypeDef::Instance, ETH_RxDescListTypeDef::ItMode, ETH_RxDescListTypeDef::RxDesc, ETH_InitTypeDef::RxDesc, and ETH_HandleTypeDef::RxDescList.

Referenced by HAL_ETH_Init().

static void ETH_DMATxDescListInit ( ETH_HandleTypeDef * heth ) [static]

Initializes the DMA Tx descriptors.

called by HAL_ETH_Init() API.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 2271 of file stm32h7xx_hal_eth.c.

References ETH_TxDescListTypeDef::CurTxDesc, ETH_TX_DESC_CNT, ETH_HandleTypeDef::Init, ETH_HandleTypeDef::Instance, ETH_TxDescListTypeDef::TxDesc, ETH_InitTypeDef::TxDesc, and ETH_HandleTypeDef::TxDescList.

Referenced by HAL_ETH_Init().

static void ETH_MAC_MDIO_ClkConfig ( ETH_HandleTypeDef * heth ) [static]

Configures the Clock range of SMI interface.

called by HAL_ETH_Init() API.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 2219 of file stm32h7xx_hal_eth.c.

References HAL_RCC_GetHCLKFreq(), and ETH_HandleTypeDef::Instance.

Referenced by HAL_ETH_Init().

static void ETH_MACDMAConfig ( ETH_HandleTypeDef * heth ) [static]

Configures Ethernet MAC and DMA with default parameters.

called by HAL_ETH_Init() API.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
HAL status

Definition at line 2146 of file stm32h7xx_hal_eth.c.

References ETH_DMAConfigTypeDef::AddressAlignedBeats, ETH_MACConfigTypeDef::AutomaticPadCRCStrip, ETH_MACConfigTypeDef::BackOffLimit, ETH_DMAConfigTypeDef::BurstMode, ETH_MACConfigTypeDef::CarrierSenseBeforeTransmit, ETH_MACConfigTypeDef::CarrierSenseDuringTransmit, ETH_MACConfigTypeDef::ChecksumOffload, ETH_MACConfigTypeDef::CRCCheckingRxPackets, ETH_MACConfigTypeDef::CRCStripTypePacket, ETH_MACConfigTypeDef::DeferralCheck, ETH_DMAConfigTypeDef::DMAArbitration, ETH_MACConfigTypeDef::DropTCPIPChecksumErrorPacket, ETH_MACConfigTypeDef::DuplexMode, ETH_BACKOFFLIMIT_10, ETH_BURSTLENGTH_FIXED, ETH_DMAARBITRATION_RX1_TX1, ETH_FULLDUPLEX_MODE, ETH_INTERPACKETGAP_96BIT, ETH_PAUSELOWTHRESHOLD_MINUS_4, ETH_PREAMBLELENGTH_7, ETH_RECEIVESTOREFORWARD, ETH_RXDMABURSTLENGTH_32BEAT, ETH_SetDMAConfig(), ETH_SetMACConfig(), ETH_SOURCEADDRESS_REPLACE_ADDR0, ETH_SPEED_100M, ETH_TRANSMITSTOREFORWARD, ETH_TXDMABURSTLENGTH_32BEAT, ETH_MACConfigTypeDef::ExtendedInterPacketGap, ETH_MACConfigTypeDef::ExtendedInterPacketGapVal, ETH_DMAConfigTypeDef::FlushRxPacket, ETH_MACConfigTypeDef::ForwardRxErrorPacket, ETH_MACConfigTypeDef::ForwardRxUndersizedGoodPacket, ETH_MACConfigTypeDef::GiantPacketSizeLimit, ETH_MACConfigTypeDef::GiantPacketSizeLimitControl, ETH_MACConfigTypeDef::InterPacketGapVal, ETH_MACConfigTypeDef::Jabber, ETH_MACConfigTypeDef::JumboPacket, ETH_MACConfigTypeDef::LoopbackMode, ETH_DMAConfigTypeDef::MaximumSegmentSize, ETH_MACConfigTypeDef::PauseLowThreshold, ETH_MACConfigTypeDef::PauseTime, ETH_DMAConfigTypeDef::PBLx8Mode, ETH_MACConfigTypeDef::PreambleLength, ETH_MACConfigTypeDef::ProgrammableWatchdog, ETH_DMAConfigTypeDef::RebuildINCRxBurst, ETH_MACConfigTypeDef::ReceiveFlowControl, ETH_MACConfigTypeDef::ReceiveOwn, ETH_MACConfigTypeDef::ReceiveQueueMode, ETH_MACConfigTypeDef::RetryTransmission, ETH_DMAConfigTypeDef::RxDMABurstLength, ETH_DMAConfigTypeDef::SecondPacketOperate, ETH_MACConfigTypeDef::SlowProtocolDetect, ETH_MACConfigTypeDef::SourceAddrControl, ETH_MACConfigTypeDef::Speed, ETH_MACConfigTypeDef::Support2KPacket, ETH_DMAConfigTypeDef::TCPSegmentation, ETH_MACConfigTypeDef::TransmitFlowControl, ETH_MACConfigTypeDef::TransmitQueueMode, ETH_DMAConfigTypeDef::TxDMABurstLength, ETH_MACConfigTypeDef::UnicastPausePacketDetect, ETH_MACConfigTypeDef::UnicastSlowProtocolPacketDetect, ETH_MACConfigTypeDef::Watchdog, ETH_MACConfigTypeDef::WatchdogTimeout, and ETH_MACConfigTypeDef::ZeroQuantaPause.

Referenced by HAL_ETH_Init().

static uint32_t ETH_Prepare_Tx_Descriptors | ( | ETH_HandleTypeDef * | heth,
 |  | ETH_TxPacketConfig * | pTxConfig,
 |  | uint32_t | ItMode
 | ) |  | [static]

Prepare Tx DMA descriptor before transmission.

called by HAL_ETH_Transmit_IT and HAL_ETH_Transmit_IT() API.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
pTxConfig,: Tx packet configuration
ItMode,: Enable or disable Tx EOT interrept
Return values:
None

Definition at line 2353 of file stm32h7xx_hal_eth.c.

References ETH_TxPacketConfig::Attributes, ETH_TxPacketConfig::ChecksumCtrl, ETH_TxPacketConfig::CRCPadCtrl, ETH_TxDescListTypeDef::CurTxDesc, ETH_DMATXCDESC_CTXT, ETH_DMATXCDESC_IVLTV, ETH_DMATXCDESC_IVT, ETH_DMATXCDESC_IVTIR, ETH_DMATXCDESC_MSS, ETH_DMATXCDESC_OWN, ETH_DMATXCDESC_TCMSSV, ETH_DMATXCDESC_VLTV, ETH_DMATXCDESC_VT, ETH_DMATXNDESCRF_B1L, ETH_DMATXNDESCRF_B2L, ETH_DMATXNDESCRF_CIC, ETH_DMATXNDESCRF_CPC, ETH_DMATXNDESCRF_CTXT, ETH_DMATXNDESCRF_FD, ETH_DMATXNDESCRF_FL, ETH_DMATXNDESCRF_IOC, ETH_DMATXNDESCRF_LD, ETH_DMATXNDESCRF_OWN, ETH_DMATXNDESCRF_SAIC, ETH_DMATXNDESCRF_THL, ETH_DMATXNDESCRF_TPL, ETH_DMATXNDESCRF_TSE, ETH_DMATXNDESCRF_VTIR, ETH_DMATXNDESCWBF_OWN, ETH_TX_PACKETS_FEATURES_CRCPAD, ETH_TX_PACKETS_FEATURES_CSUM, ETH_TX_PACKETS_FEATURES_INNERVLANTAG, ETH_TX_PACKETS_FEATURES_SAIC, ETH_TX_PACKETS_FEATURES_TSO, ETH_TX_PACKETS_FEATURES_VLANTAG, HAL_ETH_ERROR_BUSY, HAL_ETH_ERROR_NONE, INCR_TX_DESC_INDEX, ETH_TxPacketConfig::InnerVlanCtrl, ETH_TxPacketConfig::InnerVlanTag, ETH_HandleTypeDef::Instance, ETH_TxPacketConfig::Length, ETH_TxPacketConfig::MaxSegmentSize, ETH_TxPacketConfig::PayloadLen, ETH_TxPacketConfig::SrcAddrCtrl, ETH_TxPacketConfig::TCPHeaderLen, ETH_TxPacketConfig::TxBuffer, ETH_TxDescListTypeDef::TxDesc, ETH_HandleTypeDef::TxDescList, ETH_TxPacketConfig::VlanCtrl, and ETH_TxPacketConfig::VlanTag.

Referenced by HAL_ETH_Transmit(), and HAL_ETH_Transmit_IT().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETHEx Private Constants

Defines
ETHEx Private Constants
ETHEx

Defines

#define | ETH_MACL4CR_MASK
#define | ETH_MACL3CR_MASK
#define | ETH_MACRXVLAN_MASK
#define | ETH_MACTXVLAN_MASK

Define Documentation

#define ETH_MACL3CR_MASK
Value:
(ETH_MACL3L4CR_L3PEN | ETH_MACL3L4CR_L3SAM | \
                              ETH_MACL3L4CR_L3SAIM | ETH_MACL3L4CR_L3DAM | \
                              ETH_MACL3L4CR_L3DAIM | ETH_MACL3L4CR_L3HSBM | \
                              ETH_MACL3L4CR_L3HDBM)

Definition at line 62 of file stm32h7xx_hal_eth_ex.c.

Referenced by HAL_ETHEx_SetL3FilterConfig().

#define ETH_MACL4CR_MASK
Value:
(ETH_MACL3L4CR_L4PEN | ETH_MACL3L4CR_L4SPM | \
                              ETH_MACL3L4CR_L4SPIM | ETH_MACL3L4CR_L4DPM | \
                              ETH_MACL3L4CR_L4DPIM)

Definition at line 58 of file stm32h7xx_hal_eth_ex.c.

Referenced by HAL_ETHEx_SetL4FilterConfig().

#define ETH_MACRXVLAN_MASK
Value:
(ETH_MACVTR_EIVLRXS | ETH_MACVTR_EIVLS | \
                            ETH_MACVTR_ERIVLT | ETH_MACVTR_EDVLP | \
                            ETH_MACVTR_VTHM | ETH_MACVTR_EVLRXS | \
                            ETH_MACVTR_EVLS | ETH_MACVTR_DOVLTC | \
                            ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL | \
                            ETH_MACVTR_VTIM | ETH_MACVTR_ETV)

Definition at line 67 of file stm32h7xx_hal_eth_ex.c.

Referenced by HAL_ETHEx_SetRxVLANConfig().

#define ETH_MACTXVLAN_MASK
Value:
(ETH_MACVIR_VLTI | ETH_MACVIR_CSVL | \
                            ETH_MACVIR_VLP | ETH_MACVIR_VLC)

Definition at line 74 of file stm32h7xx_hal_eth_ex.c.

Referenced by HAL_ETHEx_SetTxVLANConfig().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Extended features functions

Functions
Extended features functions
ETH Extended Exported Functions

Extended features functions. More...

Functions

void | HAL_ETHEx_EnableARPOffload (ETH_HandleTypeDef *heth)
Enables ARP Offload.
void | HAL_ETHEx_DisableARPOffload (ETH_HandleTypeDef *heth)
Disables ARP Offload.
void | HAL_ETHEx_SetARPAddressMatch (ETH_HandleTypeDef *heth, uint32_t IpAddress)
Set the ARP Match IP address.
HAL_StatusTypeDef | HAL_ETHEx_SetL4FilterConfig (ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig)
Configures the L4 Filter, this function allow to: set the layer 4 protocol to be matched (TCP or UDP) enable/disable L4 source/destination port perfect/inverse match.
HAL_StatusTypeDef | HAL_ETHEx_GetL4FilterConfig (ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig)
Configures the L4 Filter, this function allow to: set the layer 4 protocol to be matched (TCP or UDP) enable/disable L4 source/destination port perfect/inverse match.
HAL_StatusTypeDef | HAL_ETHEx_SetL3FilterConfig (ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
Configures the L3 Filter, this function allow to: set the layer 3 protocol to be matched (IPv4 or IPv6) enable/disable L3 source/destination port perfect/inverse match.
HAL_StatusTypeDef | HAL_ETHEx_GetL3FilterConfig (ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
Configures the L3 Filter, this function allow to: set the layer 3 protocol to be matched (IPv4 or IPv6) enable/disable L3 source/destination port perfect/inverse match.
void | HAL_ETHEx_EnableL3L4Filtering (ETH_HandleTypeDef *heth)
Enables L3 and L4 filtering process.
void | HAL_ETHEx_DisableL3L4Filtering (ETH_HandleTypeDef *heth)
Disables L3 and L4 filtering process.
HAL_StatusTypeDef | HAL_ETHEx_GetRxVLANConfig (ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
Get the VLAN Configuration for Receive Packets.
HAL_StatusTypeDef | HAL_ETHEx_SetRxVLANConfig (ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
Set the VLAN Configuration for Receive Packets.
void | HAL_ETHEx_SetVLANHashTable (ETH_HandleTypeDef *heth, uint32_t VLANHashTable)
Set the VLAN Hash Table.
HAL_StatusTypeDef | HAL_ETHEx_GetTxVLANConfig (ETH_HandleTypeDef *heth, uint32_t VLANTag, ETH_TxVLANConfigTypeDef *pVlanConfig)
Get the VLAN Configuration for Transmit Packets.
HAL_StatusTypeDef | HAL_ETHEx_SetTxVLANConfig (ETH_HandleTypeDef *heth, uint32_t VLANTag, ETH_TxVLANConfigTypeDef *pVlanConfig)
Set the VLAN Configuration for Transmit Packets.
void | HAL_ETHEx_SetTxVLANIdentifier (ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier)
Set the VLAN Tag Identifier for Transmit Packets.
void | HAL_ETHEx_EnableVLANProcessing (ETH_HandleTypeDef *heth)
Enables the VLAN Tag Filtering process.
void | HAL_ETHEx_DisableVLANProcessing (ETH_HandleTypeDef *heth)
Disables the VLAN Tag Filtering process.
void | HAL_ETHEx_EnterLPIMode (ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop)
Enters the Low Power Idle (LPI) mode.
void | HAL_ETHEx_ExitLPIMode (ETH_HandleTypeDef *heth)
Exits the Low Power Idle (LPI) mode.
uint32_t | HAL_ETHEx_GetMACLPIEvent (ETH_HandleTypeDef *heth)
Returns the ETH MAC LPI event.

Detailed Description

Extended features functions.

 ===============================================================================
                      ##### Extended features functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Configure ARP offload module
      (+) Configure L3 and L4 filters
      (+) Configure Extended VLAN features
      (+) Configure Energy Efficient Ethernet module

Function Documentation

void HAL_ETHEx_DisableARPOffload ( ETH_HandleTypeDef * heth )

Disables ARP Offload.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 121 of file stm32h7xx_hal_eth_ex.c.

References ETH_HandleTypeDef::Instance.

void HAL_ETHEx_DisableL3L4Filtering ( ETH_HandleTypeDef * heth )

Disables L3 and L4 filtering process.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None.

Definition at line 342 of file stm32h7xx_hal_eth_ex.c.

References ETH_HandleTypeDef::Instance.

void HAL_ETHEx_DisableVLANProcessing ( ETH_HandleTypeDef * heth )

Disables the VLAN Tag Filtering process.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None.

Definition at line 538 of file stm32h7xx_hal_eth_ex.c.

References ETH_HandleTypeDef::Instance.

void HAL_ETHEx_EnableARPOffload ( ETH_HandleTypeDef * heth )

Enables ARP Offload.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 110 of file stm32h7xx_hal_eth_ex.c.

References ETH_HandleTypeDef::Instance.

void HAL_ETHEx_EnableL3L4Filtering ( ETH_HandleTypeDef * heth )

Enables L3 and L4 filtering process.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None.

Definition at line 330 of file stm32h7xx_hal_eth_ex.c.

References ETH_HandleTypeDef::Instance.

void HAL_ETHEx_EnableVLANProcessing ( ETH_HandleTypeDef * heth )

Enables the VLAN Tag Filtering process.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None.

Definition at line 526 of file stm32h7xx_hal_eth_ex.c.

References ETH_HandleTypeDef::Instance.

void HAL_ETHEx_EnterLPIMode | ( | ETH_HandleTypeDef * | heth,
 |  | FunctionalState | TxAutomate,
 |  | FunctionalState | TxClockStop
 | ) |  |

Enters the Low Power Idle (LPI) mode.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
TxAutomate,: Enable/Disbale automate enter/exit LPI mode.
TxClockStop,: Enable/Disbale Tx clock stop in LPI mode.
Return values:
None

Definition at line 552 of file stm32h7xx_hal_eth_ex.c.

References __HAL_ETH_MAC_ENABLE_IT, and ETH_HandleTypeDef::Instance.

void HAL_ETHEx_ExitLPIMode ( ETH_HandleTypeDef * heth )

Exits the Low Power Idle (LPI) mode.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 573 of file stm32h7xx_hal_eth_ex.c.

References __HAL_ETH_MAC_DISABLE_IT, and ETH_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig | ( | ETH_HandleTypeDef * | heth,
 |  | uint32_t | Filter,
 |  | ETH_L3FilterConfigTypeDef * | pL3FilterConfig
 | ) |  |

Configures the L3 Filter, this function allow to: set the layer 3 protocol to be matched (IPv4 or IPv6) enable/disable L3 source/destination port perfect/inverse match.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Filter,: L3 filter to configured, this parameter must be one of the following ETH_L3_FILTER_0 ETH_L3_FILTER_1
pL3FilterConfig,: pointer to a ETH_L3FilterConfigTypeDef structure that will contain the L3 filter configuration.
Return values:
HAL status

Definition at line 293 of file stm32h7xx_hal_eth_ex.c.

References ETH_L3FilterConfigTypeDef::DestAddrFilterMatch, ETH_L3FilterConfigTypeDef::DestAddrHigherBitsMatch, ETH_HandleTypeDef::Instance, ETH_L3FilterConfigTypeDef::Ip4DestAddr, ETH_L3FilterConfigTypeDef::Ip4SrcAddr, ETH_L3FilterConfigTypeDef::Ip6Addr, ETH_L3FilterConfigTypeDef::Protocol, ETH_L3FilterConfigTypeDef::SrcAddrFilterMatch, and ETH_L3FilterConfigTypeDef::SrcAddrHigherBitsMatch.

HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig | ( | ETH_HandleTypeDef * | heth,
 |  | uint32_t | Filter,
 |  | ETH_L4FilterConfigTypeDef * | pL4FilterConfig
 | ) |  |

Configures the L4 Filter, this function allow to: set the layer 4 protocol to be matched (TCP or UDP) enable/disable L4 source/destination port perfect/inverse match.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Filter,: L4 filter to configured, this parameter must be one of the following ETH_L4_FILTER_0 ETH_L4_FILTER_1
pL4FilterConfig,: pointer to a ETH_L4FilterConfigTypeDef structure that contains L4 filter configuration.
Return values:
HAL status

Definition at line 198 of file stm32h7xx_hal_eth_ex.c.

References ETH_L4FilterConfigTypeDef::DestinationPort, ETH_L4FilterConfigTypeDef::DestPortFilterMatch, ETH_HandleTypeDef::Instance, ETH_L4FilterConfigTypeDef::Protocol, ETH_L4FilterConfigTypeDef::SourcePort, and ETH_L4FilterConfigTypeDef::SrcPortFilterMatch.

uint32_t HAL_ETHEx_GetMACLPIEvent ( ETH_HandleTypeDef * heth )

Returns the ETH MAC LPI event.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
ETH MAC WakeUp event

Definition at line 589 of file stm32h7xx_hal_eth_ex.c.

References ETH_HandleTypeDef::MACLPIEvent.

HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig | ( | ETH_HandleTypeDef * | heth,
 |  | ETH_RxVLANConfigTypeDef * | pVlanConfig
 | ) |  |

Get the VLAN Configuration for Receive Packets.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
pVlanConfig,: pointer to a ETH_RxVLANConfigTypeDef structure that will contain the VLAN filter configuration.
Return values:
HAL status

Definition at line 356 of file stm32h7xx_hal_eth_ex.c.

References ETH_RxVLANConfigTypeDef::DoubleVLANProcessing, ETH_RxVLANConfigTypeDef::InnerVLANTag, ETH_RxVLANConfigTypeDef::InnerVLANTagInStatus, ETH_HandleTypeDef::Instance, ETH_RxVLANConfigTypeDef::StripInnerVLANTag, ETH_RxVLANConfigTypeDef::StripVLANTag, ETH_RxVLANConfigTypeDef::VLANTagHashTableMatch, ETH_RxVLANConfigTypeDef::VLANTagInStatus, ETH_RxVLANConfigTypeDef::VLANTagInverceMatch, and ETH_RxVLANConfigTypeDef::VLANTypeCheck.

HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig | ( | ETH_HandleTypeDef * | heth,
 |  | uint32_t | VLANTag,
 |  | ETH_TxVLANConfigTypeDef * | pVlanConfig
 | ) |  |

Get the VLAN Configuration for Transmit Packets.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
VLANTag,: Selects the vlan tag, this parameter must be one of the following ETH_OUTER_TX_VLANTAG ETH_INNER_TX_VLANTAG
pVlanConfig,: pointer to a ETH_TxVLANConfigTypeDef structure that will contain the Tx VLAN filter configuration.
Return values:
HAL Status.

Definition at line 432 of file stm32h7xx_hal_eth_ex.c.

References ETH_INNER_TX_VLANTAG, ETH_HandleTypeDef::Instance, ETH_TxVLANConfigTypeDef::SourceTxDesc, ETH_TxVLANConfigTypeDef::SVLANType, and ETH_TxVLANConfigTypeDef::VLANTagControl.

void HAL_ETHEx_SetARPAddressMatch | ( | ETH_HandleTypeDef * | heth,
 |  | uint32_t | IpAddress
 | ) |  |

Set the ARP Match IP address.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
IpAddress,: IP Address to be matched for incoming ARP requests
Return values:
None

Definition at line 133 of file stm32h7xx_hal_eth_ex.c.

References ETH_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig | ( | ETH_HandleTypeDef * | heth,
 |  | uint32_t | Filter,
 |  | ETH_L3FilterConfigTypeDef * | pL3FilterConfig
 | ) |  |

Configures the L3 Filter, this function allow to: set the layer 3 protocol to be matched (IPv4 or IPv6) enable/disable L3 source/destination port perfect/inverse match.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Filter,: L3 filter to configured, this parameter must be one of the following ETH_L3_FILTER_0 ETH_L3_FILTER_1
pL3FilterConfig,: pointer to a ETH_L3FilterConfigTypeDef structure that contains L3 filter configuration.
Return values:
HAL status

Definition at line 235 of file stm32h7xx_hal_eth_ex.c.

References ETH_L3FilterConfigTypeDef::DestAddrFilterMatch, ETH_L3FilterConfigTypeDef::DestAddrHigherBitsMatch, ETH_MACL3CR_MASK, ETH_HandleTypeDef::Instance, ETH_L3FilterConfigTypeDef::Ip4DestAddr, ETH_L3FilterConfigTypeDef::Ip4SrcAddr, ETH_L3FilterConfigTypeDef::Ip6Addr, ETH_L3FilterConfigTypeDef::Protocol, ETH_L3FilterConfigTypeDef::SrcAddrFilterMatch, and ETH_L3FilterConfigTypeDef::SrcAddrHigherBitsMatch.

HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig | ( | ETH_HandleTypeDef * | heth,
 |  | uint32_t | Filter,
 |  | ETH_L4FilterConfigTypeDef * | pL4FilterConfig
 | ) |  |

Configures the L4 Filter, this function allow to: set the layer 4 protocol to be matched (TCP or UDP) enable/disable L4 source/destination port perfect/inverse match.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Filter,: L4 filter to configured, this parameter must be one of the following ETH_L4_FILTER_0 ETH_L4_FILTER_1
pL4FilterConfig,: pointer to a ETH_L4FilterConfigTypeDef structure that contains L4 filter configuration.
Return values:
HAL status

Definition at line 151 of file stm32h7xx_hal_eth_ex.c.

References ETH_L4FilterConfigTypeDef::DestinationPort, ETH_L4FilterConfigTypeDef::DestPortFilterMatch, ETH_MACL4CR_MASK, ETH_HandleTypeDef::Instance, ETH_L4FilterConfigTypeDef::Protocol, ETH_L4FilterConfigTypeDef::SourcePort, and ETH_L4FilterConfigTypeDef::SrcPortFilterMatch.

HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig | ( | ETH_HandleTypeDef * | heth,
 |  | ETH_RxVLANConfigTypeDef * | pVlanConfig
 | ) |  |

Set the VLAN Configuration for Receive Packets.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
pVlanConfig,: pointer to a ETH_RxVLANConfigTypeDef structure that contains VLAN filter configuration.
Return values:
HAL status

Definition at line 384 of file stm32h7xx_hal_eth_ex.c.

References ETH_RxVLANConfigTypeDef::DoubleVLANProcessing, ETH_MACRXVLAN_MASK, ETH_RxVLANConfigTypeDef::InnerVLANTag, ETH_RxVLANConfigTypeDef::InnerVLANTagInStatus, ETH_HandleTypeDef::Instance, ETH_RxVLANConfigTypeDef::StripInnerVLANTag, ETH_RxVLANConfigTypeDef::StripVLANTag, ETH_RxVLANConfigTypeDef::VLANTagHashTableMatch, ETH_RxVLANConfigTypeDef::VLANTagInStatus, ETH_RxVLANConfigTypeDef::VLANTagInverceMatch, and ETH_RxVLANConfigTypeDef::VLANTypeCheck.

HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig | ( | ETH_HandleTypeDef * | heth,
 |  | uint32_t | VLANTag,
 |  | ETH_TxVLANConfigTypeDef * | pVlanConfig
 | ) |  |

Set the VLAN Configuration for Transmit Packets.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
VLANTag,: Selects the vlan tag, this parameter must be one of the following ETH_OUTER_TX_VLANTAG ETH_INNER_TX_VLANTAG
pVlanConfig,: pointer to a ETH_TxVLANConfigTypeDef structure that contains Tx VLAN filter configuration.
Return values:
HAL Status

Definition at line 469 of file stm32h7xx_hal_eth_ex.c.

References ETH_INNER_TX_VLANTAG, ETH_MACTXVLAN_MASK, ETH_HandleTypeDef::Instance, ETH_TxVLANConfigTypeDef::SourceTxDesc, ETH_TxVLANConfigTypeDef::SVLANType, and ETH_TxVLANConfigTypeDef::VLANTagControl.

void HAL_ETHEx_SetTxVLANIdentifier | ( | ETH_HandleTypeDef * | heth,
 |  | uint32_t | VLANTag,
 |  | uint32_t | VLANIdentifier
 | ) |  |

Set the VLAN Tag Identifier for Transmit Packets.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
VLANTag,: Selects the vlan tag, this parameter must be one of the following ETH_OUTER_TX_VLANTAG ETH_INNER_TX_VLANTAG
VLANIdentifier,: VLAN Identifier 16 bit value
Return values:
None

Definition at line 504 of file stm32h7xx_hal_eth_ex.c.

References ETH_INNER_TX_VLANTAG, and ETH_HandleTypeDef::Instance.

void HAL_ETHEx_SetVLANHashTable | ( | ETH_HandleTypeDef * | heth,
 |  | uint32_t | VLANHashTable
 | ) |  |

Set the VLAN Hash Table.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
VLANHashTable,: VLAN hash table 16 bit value
Return values:
None

Definition at line 416 of file stm32h7xx_hal_eth_ex.c.

References ETH_HandleTypeDef::Instance.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH_RxVLANConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ETH_RxVLANConfigTypeDef Struct Reference
ETHEx Exported Types

ETH RX VLAN structure definition. More...

#include <stm32h7xx_hal_eth_ex.h>

Data Fields

FunctionalState | InnerVLANTagInStatus
uint32_t | StripInnerVLANTag
FunctionalState | InnerVLANTag
FunctionalState | DoubleVLANProcessing
FunctionalState | VLANTagHashTableMatch
FunctionalState | VLANTagInStatus
uint32_t | StripVLANTag
uint32_t | VLANTypeCheck
FunctionalState | VLANTagInverceMatch

Detailed Description

ETH RX VLAN structure definition.

Definition at line 65 of file stm32h7xx_hal_eth_ex.h.

Field Documentation

FunctionalState ETH_RxVLANConfigTypeDef::DoubleVLANProcessing

Enable or Disable double VLAN processing

Definition at line 73 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetRxVLANConfig(), and HAL_ETHEx_SetRxVLANConfig().

FunctionalState ETH_RxVLANConfigTypeDef::InnerVLANTag

Enables or disables Inner VLAN Tag

Definition at line 71 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetRxVLANConfig(), and HAL_ETHEx_SetRxVLANConfig().

FunctionalState ETH_RxVLANConfigTypeDef::InnerVLANTagInStatus

Enables or disables Inner VLAN Tag in Rx Status

Definition at line 66 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetRxVLANConfig(), and HAL_ETHEx_SetRxVLANConfig().

uint32_t ETH_RxVLANConfigTypeDef::StripInnerVLANTag

Sets the Inner VLAN Tag Stripping on Receive This parameter can be a value of ETHEx Rx Inner VLAN Tag Stripping

Definition at line 68 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetRxVLANConfig(), and HAL_ETHEx_SetRxVLANConfig().

uint32_t ETH_RxVLANConfigTypeDef::StripVLANTag

Set the VLAN Tag Stripping on Receive This parameter can be a value of ETHEx Rx VLAN Tag Stripping

Definition at line 79 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetRxVLANConfig(), and HAL_ETHEx_SetRxVLANConfig().

FunctionalState ETH_RxVLANConfigTypeDef::VLANTagHashTableMatch

Enable or Disable VLAN Tag Hash Table Match

Definition at line 75 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetRxVLANConfig(), and HAL_ETHEx_SetRxVLANConfig().

FunctionalState ETH_RxVLANConfigTypeDef::VLANTagInStatus

Enable or Disable VLAN Tag in Rx status

Definition at line 77 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetRxVLANConfig(), and HAL_ETHEx_SetRxVLANConfig().

FunctionalState ETH_RxVLANConfigTypeDef::VLANTagInverceMatch

Enable or disable VLAN Tag Inverse Match

Definition at line 85 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetRxVLANConfig(), and HAL_ETHEx_SetRxVLANConfig().

uint32_t ETH_RxVLANConfigTypeDef::VLANTypeCheck

Enable or Disable VLAN Type Check This parameter can be a value of ETHEx VLAN Type Check

Definition at line 82 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetRxVLANConfig(), and HAL_ETHEx_SetRxVLANConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_eth_ex.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH_TxVLANConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ETH_TxVLANConfigTypeDef Struct Reference
ETHEx Exported Types

ETH TX VLAN structure definition. More...

#include <stm32h7xx_hal_eth_ex.h>

Data Fields

FunctionalState | SourceTxDesc
FunctionalState | SVLANType
uint32_t | VLANTagControl

Detailed Description

ETH TX VLAN structure definition.

Definition at line 94 of file stm32h7xx_hal_eth_ex.h.

Field Documentation

FunctionalState ETH_TxVLANConfigTypeDef::SourceTxDesc

Enable or Disable VLAN tag source from DMA tx descriptors

Definition at line 95 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetTxVLANConfig(), and HAL_ETHEx_SetTxVLANConfig().

FunctionalState ETH_TxVLANConfigTypeDef::SVLANType

Enable or Disable insertion of SVLAN type

Definition at line 97 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetTxVLANConfig(), and HAL_ETHEx_SetTxVLANConfig().

uint32_t ETH_TxVLANConfigTypeDef::VLANTagControl

Sets the VLAN tag control in tx packets This parameter can be a value of ETHEx_VLAN_Tag_Control

Definition at line 99 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetTxVLANConfig(), and HAL_ETHEx_SetTxVLANConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_eth_ex.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH_L3FilterConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ETH_L3FilterConfigTypeDef Struct Reference
ETHEx Exported Types

ETH L3 filter structure definition. More...

#include <stm32h7xx_hal_eth_ex.h>

Data Fields

uint32_t | Protocol
uint32_t | SrcAddrFilterMatch
uint32_t | DestAddrFilterMatch
uint32_t | SrcAddrHigherBitsMatch
uint32_t | DestAddrHigherBitsMatch
uint32_t | Ip4SrcAddr
uint32_t | Ip4DestAddr
uint32_t | Ip6Addr [4]

Detailed Description

ETH L3 filter structure definition.

Definition at line 109 of file stm32h7xx_hal_eth_ex.h.

Field Documentation

uint32_t ETH_L3FilterConfigTypeDef::DestAddrFilterMatch

Sets the L3 filter destination address match This parameter can be a value of ETHEx L3 Destination Match

Definition at line 116 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetL3FilterConfig(), and HAL_ETHEx_SetL3FilterConfig().

uint32_t ETH_L3FilterConfigTypeDef::DestAddrHigherBitsMatch

Sets the L3 filter destination address higher bits match This parameter can be a value from 0 to 31

Definition at line 122 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetL3FilterConfig(), and HAL_ETHEx_SetL3FilterConfig().

uint32_t ETH_L3FilterConfigTypeDef::Ip4DestAddr

Sets the L3 filter IPv4 destination address if IPv4 protocol is used This parameter can be a value from 0 to 0xFFFFFFFF

Definition at line 128 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetL3FilterConfig(), and HAL_ETHEx_SetL3FilterConfig().

uint32_t ETH_L3FilterConfigTypeDef::Ip4SrcAddr

Sets the L3 filter IPv4 source address if IPv4 protocol is used This parameter can be a value from 0x0 to 0xFFFFFFFF

Definition at line 125 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetL3FilterConfig(), and HAL_ETHEx_SetL3FilterConfig().

uint32_t ETH_L3FilterConfigTypeDef::Ip6Addr[4]

Sets the L3 filter IPv6 address if IPv6 protocol is used This parameter must be a table of 4 words (4* 32 bits)

Definition at line 131 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetL3FilterConfig(), and HAL_ETHEx_SetL3FilterConfig().

uint32_t ETH_L3FilterConfigTypeDef::Protocol

Sets the L3 filter protocol to IPv4 or IPv6 This parameter can be a value of ETHEx L3 Protocol

Definition at line 110 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetL3FilterConfig(), and HAL_ETHEx_SetL3FilterConfig().

uint32_t ETH_L3FilterConfigTypeDef::SrcAddrFilterMatch

Sets the L3 filter source address match This parameter can be a value of ETHEx L3 Source Match

Definition at line 113 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetL3FilterConfig(), and HAL_ETHEx_SetL3FilterConfig().

uint32_t ETH_L3FilterConfigTypeDef::SrcAddrHigherBitsMatch

Sets the L3 filter source address higher bits match This parameter can be a value from 0 to 31

Definition at line 119 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetL3FilterConfig(), and HAL_ETHEx_SetL3FilterConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_eth_ex.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETH_L4FilterConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ETH_L4FilterConfigTypeDef Struct Reference
ETHEx Exported Types

ETH L4 filter structure definition. More...

#include <stm32h7xx_hal_eth_ex.h>

Data Fields

uint32_t | Protocol
uint32_t | SrcPortFilterMatch
uint32_t | DestPortFilterMatch
uint32_t | SourcePort
uint32_t | DestinationPort

Detailed Description

ETH L4 filter structure definition.

Definition at line 141 of file stm32h7xx_hal_eth_ex.h.

Field Documentation

uint32_t ETH_L4FilterConfigTypeDef::DestinationPort

Sets the L4 filter destination port This parameter must be a value from 0x0 to 0xFFFF

Definition at line 154 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetL4FilterConfig(), and HAL_ETHEx_SetL4FilterConfig().

uint32_t ETH_L4FilterConfigTypeDef::DestPortFilterMatch

Sets the L4 filter destination port match This parameter can be a value of ETHEx L4 Destination Match

Definition at line 148 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetL4FilterConfig(), and HAL_ETHEx_SetL4FilterConfig().

uint32_t ETH_L4FilterConfigTypeDef::Protocol

Sets the L4 filter protocol to TCP or UDP This parameter can be a value of ETHEx L4 Protocol

Definition at line 142 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetL4FilterConfig(), and HAL_ETHEx_SetL4FilterConfig().

uint32_t ETH_L4FilterConfigTypeDef::SourcePort

Sets the L4 filter source port This parameter must be a value from 0x0 to 0xFFFF

Definition at line 151 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetL4FilterConfig(), and HAL_ETHEx_SetL4FilterConfig().

uint32_t ETH_L4FilterConfigTypeDef::SrcPortFilterMatch

Sets the L4 filter source port match This parameter can be a value of ETHEx L4 Source Match

Definition at line 145 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetL4FilterConfig(), and HAL_ETHEx_SetL4FilterConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_eth_ex.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: ETHEx LPI Event

Defines
ETHEx LPI Event
ETHEx Exported Constants

Defines

#define | ETH_TX_LPI_ENTRY ETH_MACLCSR_TLPIEN
#define | ETH_TX_LPI_EXIT ETH_MACLCSR_TLPIEX
#define | ETH_RX_LPI_ENTRY ETH_MACLCSR_RLPIEN
#define | ETH_RX_LPI_EXIT ETH_MACLCSR_RLPIEX

Define Documentation

#define ETH_RX_LPI_ENTRY ETH_MACLCSR_RLPIEN

Definition at line 175 of file stm32h7xx_hal_eth_ex.h.

#define ETH_RX_LPI_EXIT ETH_MACLCSR_RLPIEX

Definition at line 176 of file stm32h7xx_hal_eth_ex.h.

#define ETH_TX_LPI_ENTRY ETH_MACLCSR_TLPIEN

Definition at line 173 of file stm32h7xx_hal_eth_ex.h.

#define ETH_TX_LPI_EXIT ETH_MACLCSR_TLPIEX

Definition at line 174 of file stm32h7xx_hal_eth_ex.h.

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STM32H753xx HAL User Manual: ETHEx L3 Filter

Defines
ETHEx L3 Filter
ETHEx Exported Constants

Defines

#define | ETH_L3_FILTER_0 ((uint32_t)0x00000000)
#define | ETH_L3_FILTER_1 ((uint32_t)0x0000000C)

Define Documentation

#define ETH_L3_FILTER_0 ((uint32_t)0x00000000)

Definition at line 184 of file stm32h7xx_hal_eth_ex.h.

#define ETH_L3_FILTER_1 ((uint32_t)0x0000000C)

Definition at line 185 of file stm32h7xx_hal_eth_ex.h.

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STM32H753xx HAL User Manual: ETHEx L4 Filter

Defines
ETHEx L4 Filter
ETHEx Exported Constants

Defines

#define | ETH_L4_FILTER_0 ((uint32_t)0x00000000)
#define | ETH_L4_FILTER_1 ((uint32_t)0x0000000C)

Define Documentation

#define ETH_L4_FILTER_0 ((uint32_t)0x00000000)

Definition at line 193 of file stm32h7xx_hal_eth_ex.h.

#define ETH_L4_FILTER_1 ((uint32_t)0x0000000C)

Definition at line 194 of file stm32h7xx_hal_eth_ex.h.

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STM32H753xx HAL User Manual: ETHEx L3 Protocol

Defines
ETHEx L3 Protocol
ETHEx Exported Constants

Defines

#define | ETH_L3_IPV6_MATCH ETH_MACL3L4CR_L3PEN
#define | ETH_L3_IPV4_MATCH ((uint32_t)0x00000000)

Define Documentation

#define ETH_L3_IPV4_MATCH ((uint32_t)0x00000000)

Definition at line 203 of file stm32h7xx_hal_eth_ex.h.

#define ETH_L3_IPV6_MATCH ETH_MACL3L4CR_L3PEN

Definition at line 202 of file stm32h7xx_hal_eth_ex.h.

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STM32H753xx HAL User Manual: ETHEx L3 Source Match

Defines
ETHEx L3 Source Match
ETHEx Exported Constants

Defines

#define | ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3SAM
#define | ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM)
#define | ETH_L3_SRC_ADDR_MATCH_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM)

Definition at line 212 of file stm32h7xx_hal_eth_ex.h.

#define ETH_L3_SRC_ADDR_MATCH_DISABLE ((uint32_t)0x00000000)

Definition at line 213 of file stm32h7xx_hal_eth_ex.h.

#define ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3SAM

Definition at line 211 of file stm32h7xx_hal_eth_ex.h.

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STM32H753xx HAL User Manual: ETHEx L3 Destination Match

Defines
ETHEx L3 Destination Match
ETHEx Exported Constants

Defines

#define | ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3DAM
#define | ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM)
#define | ETH_L3_DEST_ADDR_MATCH_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM)

Definition at line 222 of file stm32h7xx_hal_eth_ex.h.

#define ETH_L3_DEST_ADDR_MATCH_DISABLE ((uint32_t)0x00000000)

Definition at line 223 of file stm32h7xx_hal_eth_ex.h.

#define ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3DAM

Definition at line 221 of file stm32h7xx_hal_eth_ex.h.

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STM32H753xx HAL User Manual: ETHEx L4 Protocol

Defines
ETHEx L4 Protocol
ETHEx Exported Constants

Defines

#define | ETH_L4_UDP_MATCH ETH_MACL3L4CR_L4PEN
#define | ETH_L4_TCP_MATCH ((uint32_t)0x00000000)

Define Documentation

#define ETH_L4_TCP_MATCH ((uint32_t)0x00000000)

Definition at line 232 of file stm32h7xx_hal_eth_ex.h.

#define ETH_L4_UDP_MATCH ETH_MACL3L4CR_L4PEN

Definition at line 231 of file stm32h7xx_hal_eth_ex.h.

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STM32H753xx HAL User Manual: ETHEx L4 Source Match

Defines
ETHEx L4 Source Match
ETHEx Exported Constants

Defines

#define | ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4SPM
#define | ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM)
#define | ETH_L4_SRC_PORT_MATCH_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM)

Definition at line 241 of file stm32h7xx_hal_eth_ex.h.

#define ETH_L4_SRC_PORT_MATCH_DISABLE ((uint32_t)0x00000000)

Definition at line 242 of file stm32h7xx_hal_eth_ex.h.

#define ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4SPM

Definition at line 240 of file stm32h7xx_hal_eth_ex.h.

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STM32H753xx HAL User Manual: ETHEx L4 Destination Match

Defines
ETHEx L4 Destination Match
ETHEx Exported Constants

Defines

#define | ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4DPM
#define | ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)
#define | ETH_L4_DEST_PORT_MATCH_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)

Definition at line 251 of file stm32h7xx_hal_eth_ex.h.

#define ETH_L4_DEST_PORT_MATCH_DISABLE ((uint32_t)0x00000000)

Definition at line 252 of file stm32h7xx_hal_eth_ex.h.

#define ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4DPM

Definition at line 250 of file stm32h7xx_hal_eth_ex.h.

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STM32H753xx HAL User Manual: ETHEx Rx Inner VLAN Tag Stripping

Defines
ETHEx Rx Inner VLAN Tag Stripping
ETHEx Exported Constants

Defines

#define | ETH_INNERVLANTAGRXSTRIPPING_NONE ETH_MACVTR_EIVLS_DONOTSTRIP
#define | ETH_INNERVLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EIVLS_STRIPIFPASS
#define | ETH_INNERVLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS
#define | ETH_INNERVLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EIVLS_ALWAYSSTRIP

Define Documentation

#define ETH_INNERVLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EIVLS_ALWAYSSTRIP

Definition at line 263 of file stm32h7xx_hal_eth_ex.h.

#define ETH_INNERVLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS

Definition at line 262 of file stm32h7xx_hal_eth_ex.h.

#define ETH_INNERVLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EIVLS_STRIPIFPASS

Definition at line 261 of file stm32h7xx_hal_eth_ex.h.

#define ETH_INNERVLANTAGRXSTRIPPING_NONE ETH_MACVTR_EIVLS_DONOTSTRIP

Definition at line 260 of file stm32h7xx_hal_eth_ex.h.

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STM32H753xx HAL User Manual: ETHEx Rx VLAN Tag Stripping

Defines
ETHEx Rx VLAN Tag Stripping
ETHEx Exported Constants

Defines

#define | ETH_VLANTAGRXSTRIPPING_NONE ETH_MACVTR_EVLS_DONOTSTRIP
#define | ETH_VLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EVLS_STRIPIFPASS
#define | ETH_VLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS
#define | ETH_VLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EVLS_ALWAYSSTRIP

Define Documentation

#define ETH_VLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EVLS_ALWAYSSTRIP

Definition at line 274 of file stm32h7xx_hal_eth_ex.h.

#define ETH_VLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS

Definition at line 273 of file stm32h7xx_hal_eth_ex.h.

#define ETH_VLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EVLS_STRIPIFPASS

Definition at line 272 of file stm32h7xx_hal_eth_ex.h.

#define ETH_VLANTAGRXSTRIPPING_NONE ETH_MACVTR_EVLS_DONOTSTRIP

Definition at line 271 of file stm32h7xx_hal_eth_ex.h.

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STM32H753xx HAL User Manual: ETHEx VLAN Type Check

Defines
ETHEx VLAN Type Check
ETHEx Exported Constants

Defines

#define | ETH_VLANTYPECHECK_DISABLE ETH_MACVTR_DOVLTC
#define | ETH_VLANTYPECHECK_SVLAN (ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL)
#define | ETH_VLANTYPECHECK_CVLAN ((uint32_t)0x00000000)

Define Documentation

#define ETH_VLANTYPECHECK_CVLAN ((uint32_t)0x00000000)

Definition at line 284 of file stm32h7xx_hal_eth_ex.h.

#define ETH_VLANTYPECHECK_DISABLE ETH_MACVTR_DOVLTC

Definition at line 282 of file stm32h7xx_hal_eth_ex.h.

#define ETH_VLANTYPECHECK_SVLAN (ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL)

Definition at line 283 of file stm32h7xx_hal_eth_ex.h.

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STM32H753xx HAL User Manual: ETHEx_VLAN_Tag_Control

Defines
ETHEx_VLAN_Tag_Control
ETHEx Exported Constants

Defines

#define | ETH_VLANTAGCONTROL_NONE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_NOVLANTAG)
#define | ETH_VLANTAGCONTROL_DELETE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGDELETE)
#define | ETH_VLANTAGCONTROL_INSERT (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGINSERT)
#define | ETH_VLANTAGCONTROL_REPLACE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGREPLACE)

Define Documentation

#define ETH_VLANTAGCONTROL_DELETE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGDELETE)

Definition at line 293 of file stm32h7xx_hal_eth_ex.h.

#define ETH_VLANTAGCONTROL_INSERT (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGINSERT)

Definition at line 294 of file stm32h7xx_hal_eth_ex.h.

#define ETH_VLANTAGCONTROL_NONE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_NOVLANTAG)

Definition at line 292 of file stm32h7xx_hal_eth_ex.h.

#define ETH_VLANTAGCONTROL_REPLACE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGREPLACE)

Definition at line 295 of file stm32h7xx_hal_eth_ex.h.

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STM32H753xx HAL User Manual: ETHEx Tx VLAN Tag

Defines
ETHEx Tx VLAN Tag
ETHEx Exported Constants

Defines

#define | ETH_INNER_TX_VLANTAG ((uint32_t)0x00000001U)
#define | ETH_OUTER_TX_VLANTAG ((uint32_t)0x00000000U)

Define Documentation

#define ETH_INNER_TX_VLANTAG ((uint32_t)0x00000001U)

Definition at line 303 of file stm32h7xx_hal_eth_ex.h.

Referenced by HAL_ETHEx_GetTxVLANConfig(), HAL_ETHEx_SetTxVLANConfig(), and HAL_ETHEx_SetTxVLANIdentifier().

#define ETH_OUTER_TX_VLANTAG ((uint32_t)0x00000000U)

Definition at line 304 of file stm32h7xx_hal_eth_ex.h.

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STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
FDCAN Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_Init (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN peripheral according to the specified parameters in the FDCAN_InitTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_DeInit (FDCAN_HandleTypeDef *hfdcan)
Deinitializes the FDCAN peripheral registers to their default reset values.
__weak void | HAL_FDCAN_MspInit (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN MSP.
__weak void | HAL_FDCAN_MspDeInit (FDCAN_HandleTypeDef *hfdcan)
DeInitializes the FDCAN MSP.
HAL_StatusTypeDef | HAL_FDCAN_EnterPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Enter FDCAN peripheral in sleep mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Exit power down mode.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the FDCAN.
      (+) De-initialize the FDCAN.
      (+) Enter FDCAN peripheral in power down mode.
      (+) Exit power down mode.

Function Documentation

HAL_StatusTypeDef HAL_FDCAN_DeInit ( FDCAN_HandleTypeDef * hfdcan )

Deinitializes the FDCAN peripheral registers to their default reset values.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 471 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NONE, HAL_FDCAN_MspDeInit(), HAL_FDCAN_STATE_RESET, HAL_FDCAN_Stop(), FDCAN_HandleTypeDef::Instance, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode ( FDCAN_HandleTypeDef * hfdcan )

Enter FDCAN peripheral in sleep mode.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 534 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_ERROR, HAL_GetTick(), FDCAN_HandleTypeDef::Instance, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode ( FDCAN_HandleTypeDef * hfdcan )

Exit power down mode.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 569 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_ERROR, HAL_GetTick(), FDCAN_HandleTypeDef::Instance, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_Init ( FDCAN_HandleTypeDef * hfdcan )

Initializes the FDCAN peripheral according to the specified parameters in the FDCAN_InitTypeDef structure.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 214 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_InitTypeDef::AutoRetransmission, CvtEltSize, FDCAN_InitTypeDef::DataPrescaler, FDCAN_InitTypeDef::DataSyncJumpWidth, FDCAN_InitTypeDef::DataTimeSeg1, FDCAN_InitTypeDef::DataTimeSeg2, FDCAN_HandleTypeDef::ErrorCode, FDCAN_InitTypeDef::ExtFiltersNbr, FDCAN_CalcultateRamBlockAddresses(), FDCAN_FRAME_FD_BRS, FDCAN_MODE_BUS_MONITORING, FDCAN_MODE_EXTERNAL_LOOPBACK, FDCAN_MODE_NORMAL, FDCAN_MODE_RESTRICTED_OPERATION, FDCAN_TIMEOUT_VALUE, FDCAN_InitTypeDef::FrameFormat, HAL_FDCAN_ERROR_NONE, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_MspInit(), HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, HAL_FDCAN_STATE_RESET, HAL_GetTick(), FDCAN_HandleTypeDef::Init, FDCAN_HandleTypeDef::Instance, IS_FDCAN_DATA_PRESCALER, IS_FDCAN_DATA_SIZE, IS_FDCAN_DATA_SJW, IS_FDCAN_DATA_TSEG1, IS_FDCAN_DATA_TSEG2, IS_FDCAN_FRAME_FORMAT, IS_FDCAN_MAX_VALUE, IS_FDCAN_MODE, IS_FDCAN_NOMINAL_PRESCALER, IS_FDCAN_NOMINAL_SJW, IS_FDCAN_NOMINAL_TSEG1, IS_FDCAN_NOMINAL_TSEG2, IS_FDCAN_TX_FIFO_QUEUE_MODE, FDCAN_HandleTypeDef::Lock, FDCAN_InitTypeDef::Mode, FDCAN_InitTypeDef::NominalPrescaler, FDCAN_InitTypeDef::NominalSyncJumpWidth, FDCAN_InitTypeDef::NominalTimeSeg1, FDCAN_InitTypeDef::NominalTimeSeg2, FDCAN_InitTypeDef::ProtocolException, FDCAN_InitTypeDef::RxBufferSize, FDCAN_InitTypeDef::RxBuffersNbr, FDCAN_InitTypeDef::RxFifo0ElmtSize, FDCAN_InitTypeDef::RxFifo0ElmtsNbr, FDCAN_InitTypeDef::RxFifo1ElmtSize, FDCAN_InitTypeDef::RxFifo1ElmtsNbr, FDCAN_HandleTypeDef::State, FDCAN_InitTypeDef::StdFiltersNbr, FDCAN_InitTypeDef::TransmitPause, FDCAN_HandleTypeDef::ttcan, FDCAN_InitTypeDef::TxBuffersNbr, FDCAN_InitTypeDef::TxElmtSize, FDCAN_InitTypeDef::TxEventsNbr, FDCAN_InitTypeDef::TxFifoQueueElmtsNbr, and FDCAN_InitTypeDef::TxFifoQueueMode.

void HAL_FDCAN_MspDeInit ( FDCAN_HandleTypeDef * hfdcan )

DeInitializes the FDCAN MSP.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 519 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_DeInit().

void HAL_FDCAN_MspInit ( FDCAN_HandleTypeDef * hfdcan )

Initializes the FDCAN MSP.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 504 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init().

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STM32H753xx HAL User Manual: Configuration functions

Functions
Configuration functions
FDCAN Exported Functions

FDCAN Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_ConfigClockCalibration (FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig)
Configure the FDCAN clock calibration unit according to the specified parameters in the FDCAN_ClkCalUnitTypeDef structure.
uint32_t | HAL_FDCAN_GetClockCalibrationState (FDCAN_HandleTypeDef *hfdcan)
Get the clock calibration state.
HAL_StatusTypeDef | HAL_FDCAN_ResetClockCalibrationState (FDCAN_HandleTypeDef *hfdcan)
Reset the clock calibration state.
uint32_t | HAL_FDCAN_GetClockCalibrationCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t Counter)
Get the clock calibration counter value.
HAL_StatusTypeDef | HAL_FDCAN_ConfigFilter (FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
Configure the FDCAN reception filter according to the specified parameters in the FDCAN_FilterTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_ConfigGlobalFilter (FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt)
Configure the FDCAN global filter.
HAL_StatusTypeDef | HAL_FDCAN_ConfigExtendedIdMask (FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
Configure the extended ID mask.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRxFifoOverwrite (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
Configure the Rx FIFO operation mode.
HAL_StatusTypeDef | HAL_FDCAN_ConfigFifoWatermark (FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark)
Configure the FIFO watermark.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRamWatchdog (FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
Configure the RAM watchdog.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
Configure the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
Enable the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timestamp counter.
uint16_t | HAL_FDCAN_GetTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Get the timestamp counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timestamp counter to zero.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimeoutCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
Configure the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Enable the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timeout counter.
uint16_t | HAL_FDCAN_GetTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Get the timeout counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timeout counter to its start value.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
Configure the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_EnableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Enable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_DisableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Disable the transmitter delay compensation.

Detailed Description

FDCAN Configuration functions.

  ==============================================================================
              ##### Configuration functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) HAL_FDCAN_ConfigClockCalibration        : Configure the FDCAN clock calibration unit
        (+) HAL_FDCAN_GetClockCalibrationState      : Get the clock calibration state
        (+) HAL_FDCAN_ResetClockCalibrationState    : Reset the clock calibration state
        (+) HAL_FDCAN_GetClockCalibrationCounter    : Get the clock calibration counters values
      (+) HAL_FDCAN_ConfigFilter                  : Configure the FDCAN reception filters
      (+) HAL_FDCAN_ConfigGlobalFilter            : Configure the FDCAN global filter
      (+) HAL_FDCAN_ConfigExtendedIdMask          : Configure the extended ID mask
      (+) HAL_FDCAN_ConfigRxFifoOverwrite         : Configure the Rx FIFO operation mode
      (+) HAL_FDCAN_ConfigFifoWatermark           : Configure the FIFO watermark
      (+) HAL_FDCAN_ConfigRamWatchdog             : Configure the RAM watchdog
      (+) HAL_FDCAN_ConfigTimestampCounter        : Configure the timestamp counter
        (+) HAL_FDCAN_EnableTimestampCounter        : Enable the timestamp counter
        (+) HAL_FDCAN_DisableTimestampCounter       : Disable the timestamp counter
        (+) HAL_FDCAN_GetTimestampCounter           : Get the timestamp counter value
        (+) HAL_FDCAN_ResetTimestampCounter         : Reset the timestamp counter to zero
      (+) HAL_FDCAN_ConfigTimeoutCounter          : Configure the timeout counter
        (+) HAL_FDCAN_EnableTimeoutCounter          : Enable the timeout counter
        (+) HAL_FDCAN_DisableTimeoutCounter         : Disable the timeout counter
        (+) HAL_FDCAN_GetTimeoutCounter             : Get the timeout counter value
        (+) HAL_FDCAN_ResetTimeoutCounter           : Reset the timeout counter to its start value
      (+) HAL_FDCAN_ConfigTxDelayCompensation     : Configure the transmitter delay compensation
        (+) HAL_FDCAN_EnableTxDelayCompensation     : Enable the transmitter delay compensation
        (+) HAL_FDCAN_DisableTxDelayCompensation    : Disable the transmitter delay compensation

Function Documentation

HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_ClkCalUnitTypeDef * | sCcuConfig
 | ) |  |

Configure the FDCAN clock calibration unit according to the specified parameters in the FDCAN_ClkCalUnitTypeDef structure.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
sCcuConfig,: pointer to an FDCAN_ClkCalUnitTypeDef structure that contains the clock calibration information
Return values:
HAL status

Definition at line 650 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_ClkCalUnitTypeDef::CalFieldLength, FDCAN_ClkCalUnitTypeDef::ClockCalibration, FDCAN_ClkCalUnitTypeDef::ClockDivider, FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, IS_FDCAN_CALIBRATION_FIELD_LENGTH, IS_FDCAN_CKDIV, IS_FDCAN_MAX_VALUE, IS_FDCAN_MIN_VALUE, FDCAN_ClkCalUnitTypeDef::MinOscClkPeriods, FDCAN_HandleTypeDef::State, FDCAN_ClkCalUnitTypeDef::TimeQuantaPerBitTime, and FDCAN_ClkCalUnitTypeDef::WatchdogStartValue.

HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | Mask
 | ) |  |

Configure the extended ID mask.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Mask,: Extended ID Mask. This parameter must be a number between 0 and 0x1FFFFFFF
Return values:
HAL status

Definition at line 918 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | FIFO,
 |  | uint32_t | Watermark
 | ) |  |

Configure the FIFO watermark.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
FIFO,: select the FIFO to be configured. This parameter can be a value of
  • FDCAN_FIFO_watermark.
Watermark,: level for FIFO watermark interrupt. This parameter must be a number between:
  • 0 and 32, if FIFO is FDCAN_CFG_TX_EVENT_FIFO
  • 0 and 64, if FIFO is FDCAN_CFG_RX_FIFO0 or FDCAN_CFG_RX_FIFO1
Return values:
HAL status

Definition at line 995 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_CFG_RX_FIFO0, FDCAN_CFG_TX_EVENT_FIFO, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, IS_FDCAN_FIFO_WATERMARK, IS_FDCAN_MAX_VALUE, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigFilter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_FilterTypeDef * | sFilterConfig
 | ) |  |

Configure the FDCAN reception filter according to the specified parameters in the FDCAN_FilterTypeDef structure.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
sFilterConfig,: pointer to an FDCAN_FilterTypeDef structure that contains the filter configuration information
Return values:
HAL status

Definition at line 771 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_MsgRamAddressTypeDef::ExtendedFilterSA, FDCAN_InitTypeDef::ExtFiltersNbr, FDCAN_FILTER_TO_RXBUFFER, FDCAN_STANDARD_ID, FDCAN_FilterTypeDef::FilterConfig, FDCAN_FilterTypeDef::FilterID1, FDCAN_FilterTypeDef::FilterID2, FDCAN_FilterTypeDef::FilterIndex, FDCAN_FilterTypeDef::FilterType, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, FDCAN_FilterTypeDef::IdType, FDCAN_HandleTypeDef::Init, IS_FDCAN_EXT_FILTER_TYPE, IS_FDCAN_FILTER_CFG, IS_FDCAN_ID_TYPE, IS_FDCAN_MAX_VALUE, IS_FDCAN_STD_FILTER_TYPE, FDCAN_FilterTypeDef::IsCalibrationMsg, FDCAN_HandleTypeDef::msgRam, FDCAN_FilterTypeDef::RxBufferIndex, FDCAN_MsgRamAddressTypeDef::StandardFilterSA, FDCAN_HandleTypeDef::State, and FDCAN_InitTypeDef::StdFiltersNbr.

HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | NonMatchingStd,
 |  | uint32_t | NonMatchingExt,
 |  | uint32_t | RejectRemoteStd,
 |  | uint32_t | RejectRemoteExt
 | ) |  |

Configure the FDCAN global filter.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
NonMatchingStd,: Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. This parameter can be a value of
  • FDCAN_Non_Matching_Frames.
NonMatchingExt,: Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. This parameter can be a value of
  • FDCAN_Non_Matching_Frames.
RejectRemoteStd,: Enable or disable the remote standard frames rejection. This parameter can be set to ENABLE or DISABLE.
RejectRemoteExt,: Enable or disable the remote extended frames rejection. This parameter can be set to ENABLE or DISABLE.
Return values:
HAL status

Definition at line 881 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, IS_FDCAN_NON_MATCHING, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | CounterStartValue
 | ) |  |

Configure the RAM watchdog.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
CounterStartValue,: Start value of the Message RAM Watchdog Counter, This parameter must be a number between 0x00 and 0xFF, with the reset value of 0x00 the counter is disabled.
Return values:
HAL status

Definition at line 1045 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxFifo,
 |  | uint32_t | OperationMode
 | ) |  |

Configure the Rx FIFO operation mode.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxFifo,: Rx FIFO. This parameter can be one of the following values:
  • FDCAN_RX_FIFO0: Rx FIFO 0
  • FDCAN_RX_FIFO1: Rx FIFO 1
OperationMode,: operation mode. This parameter can be a value of
  • FDCAN_Rx_FIFO_operation_mode.
Return values:
HAL status

Definition at line 952 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_RX_FIFO0, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, IS_FDCAN_RX_FIFO, IS_FDCAN_RX_FIFO_MODE, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TimeoutOperation,
 |  | uint32_t | TimeoutPeriod
 | ) |  |

Configure the timeout counter.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TimeoutOperation,: Timeout counter operation. This parameter can be a value of
  • FDCAN_Timeout_Operation.
TimeoutPeriod,: Start value of the timeout down-counter. This parameter must be a number between 0x0000 and 0xFFFF
Return values:
HAL status

Definition at line 1200 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, IS_FDCAN_TIMEOUT, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TimestampPrescaler
 | ) |  |

Configure the timestamp counter.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TimestampPrescaler,: Timestamp Counter Prescaler. This parameter can be a value of
  • FDCAN_Timestamp_Prescaler.
Return values:
HAL status

Definition at line 1075 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, IS_FDCAN_TIMESTAMP_PRESCALER, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TdcOffset,
 |  | uint32_t | TdcFilter
 | ) |  |

Configure the transmitter delay compensation.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TdcOffset,: Transmitter Delay Compensation Offset. This parameter must be a number between 0x00 and 0xFF.
TdcFilter,: Transmitter Delay Compensation Filter Window Length. This parameter must be a number between 0x00 and 0xFF.
Return values:
HAL status

Definition at line 1320 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter ( FDCAN_HandleTypeDef * hfdcan )

Disable the timeout counter.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1254 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter ( FDCAN_HandleTypeDef * hfdcan )

Disable the timestamp counter.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1133 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation ( FDCAN_HandleTypeDef * hfdcan )

Disable the transmitter delay compensation.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1374 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter ( FDCAN_HandleTypeDef * hfdcan )

Enable the timeout counter.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1229 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TimestampOperation
 | ) |  |

Enable the timestamp counter.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TimestampOperation,: Timestamp counter operation. This parameter can be a value of
  • FDCAN_Timestamp.
Return values:
HAL status

Definition at line 1105 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, IS_FDCAN_TIMESTAMP, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation ( FDCAN_HandleTypeDef * hfdcan )

Enable the transmitter delay compensation.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1349 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, and FDCAN_HandleTypeDef::State.

uint32_t HAL_FDCAN_GetClockCalibrationCounter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | Counter
 | ) |  |

Get the clock calibration counter value.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Counter,: clock calibration counter. This parameter can be a value of
  • FDCAN_calibration_counter.
Return values:
Value,: clock calibration counter value

Definition at line 746 of file stm32h7xx_hal_fdcan.c.

References FDCAN_CALIB_CLOCK_PERIOD_COUNTER, and FDCAN_CALIB_TIME_QUANTA_COUNTER.

uint32_t HAL_FDCAN_GetClockCalibrationState ( FDCAN_HandleTypeDef * hfdcan )

Get the clock calibration state.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
State,: clock calibration state (can be a value of
  • FDCAN_calibration_state)

Definition at line 718 of file stm32h7xx_hal_fdcan.c.

uint16_t HAL_FDCAN_GetTimeoutCounter ( FDCAN_HandleTypeDef * hfdcan )

Get the timeout counter value.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
Value,: Timeout counter value

Definition at line 1279 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HandleTypeDef::Instance.

uint16_t HAL_FDCAN_GetTimestampCounter ( FDCAN_HandleTypeDef * hfdcan )

Get the timestamp counter value.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
Value,: Timestamp counter value

Definition at line 1158 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState ( FDCAN_HandleTypeDef * hfdcan )

Reset the clock calibration state.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 729 of file stm32h7xx_hal_fdcan.c.

HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter ( FDCAN_HandleTypeDef * hfdcan )

Reset the timeout counter to its start value.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1290 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_CONTINUOUS, HAL_FDCAN_ERROR_NOT_SUPPORTED, and FDCAN_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter ( FDCAN_HandleTypeDef * hfdcan )

Reset the timestamp counter to zero.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1169 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMESTAMP_EXTERNAL, HAL_FDCAN_ERROR_NOT_SUPPORTED, and FDCAN_HandleTypeDef::Instance.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Control functions

Functions
Control functions
FDCAN Exported Functions

Control functions. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_Start (FDCAN_HandleTypeDef *hfdcan)
Start the FDCAN module.
HAL_StatusTypeDef | HAL_FDCAN_Stop (FDCAN_HandleTypeDef *hfdcan)
Stop the FDCAN module and enable access to configuration registers.
HAL_StatusTypeDef | HAL_FDCAN_AddMessageToTxFifoQ (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData)
Add a message to the Tx FIFO/Queue and activate the corresponding transmission request.
HAL_StatusTypeDef | HAL_FDCAN_AddMessageToTxBuffer (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
Add a message to a dedicated Tx buffer.
HAL_StatusTypeDef | HAL_FDCAN_EnableTxBufferRequest (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
Enable transmission request.
HAL_StatusTypeDef | HAL_FDCAN_AbortTxRequest (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
Abort transmission request.
HAL_StatusTypeDef | HAL_FDCAN_GetRxMessage (FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetTxEvent (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetHighPriorityMessageStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
Get high priority message status.
HAL_StatusTypeDef | HAL_FDCAN_GetProtocolStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
Get protocol status.
HAL_StatusTypeDef | HAL_FDCAN_GetErrorCounters (FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
Get error counter values.
uint32_t | HAL_FDCAN_IsRxBufferMessageAvailable (FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex)
Check if a new message is received in the selected Rx buffer.
uint32_t | HAL_FDCAN_IsTxBufferMessagePending (FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
Check if a transmission request is pending on the selected Tx buffer.
uint32_t | HAL_FDCAN_GetRxFifoFillLevel (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
Return Rx FIFO fill level.
uint32_t | HAL_FDCAN_GetTxFifoFreeLevel (FDCAN_HandleTypeDef *hfdcan)
Return Tx FIFO free level: number of consecutive free Tx FIFO elements starting from Tx FIFO GetIndex.
uint32_t | HAL_FDCAN_IsRestrictedOperationMode (FDCAN_HandleTypeDef *hfdcan)
Check if the FDCAN peripheral entered Restricted Operation Mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitRestrictedOperationMode (FDCAN_HandleTypeDef *hfdcan)
Exit Restricted Operation Mode.

Detailed Description

Control functions.

  ==============================================================================
                          ##### Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) HAL_FDCAN_Start                        : Start the FDCAN module
      (+) HAL_FDCAN_Stop                         : Stop the FDCAN module and enable access to configuration registers
      (+) HAL_FDCAN_AddMessageToTxFifoQ          : Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
      (+) HAL_FDCAN_AddMessageToTxBuffer         : Add a message to a dedicated Tx buffer
      (+) HAL_FDCAN_EnableTxBufferRequest        : Enable transmission request
      (+) HAL_FDCAN_AbortTxRequest               : Abort transmission request
      (+) HAL_FDCAN_GetRxMessage                 : Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM
      (+) HAL_FDCAN_GetTxEvent                   : Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM
      (+) HAL_FDCAN_GetHighPriorityMessageStatus : Get high priority message status
      (+) HAL_FDCAN_GetProtocolStatus            : Get protocol status
      (+) HAL_FDCAN_GetErrorCounters             : Get error counter values
      (+) HAL_FDCAN_IsRxBufferMessageAvailable   : Check if a new message is received in the selected Rx buffer
      (+) HAL_FDCAN_IsTxBufferMessagePending     : Check if a transmission request is pending on the selected Tx buffer
      (+) HAL_FDCAN_GetRxFifoFillLevel           : Return Rx FIFO fill level
      (+) HAL_FDCAN_GetTxFifoFreeLevel           : Return Tx FIFO free level
      (+) HAL_FDCAN_IsRestrictedOperationMode    : Check if the FDCAN peripheral entered Restricted Operation Mode
      (+) HAL_FDCAN_ExitRestrictedOperationMode  : Exit Restricted Operation Mode

Function Documentation

HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | BufferIndex
 | ) |  |

Abort transmission request.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
BufferIndex,: buffer index. This parameter can be any combination of
  • FDCAN_Tx_location.
Return values:
HAL status

Definition at line 1683 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_STARTED, HAL_FDCAN_STATE_BUSY, FDCAN_HandleTypeDef::Instance, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_TxHeaderTypeDef * | pTxHeader,
 |  | uint8_t * | pTxData,
 |  | uint32_t | BufferIndex
 | ) |  |

Add a message to a dedicated Tx buffer.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
pTxHeader,: pointer to a FDCAN_TxHeaderTypeDef structure.
pTxData,: pointer to a buffer containing the payload of the Tx frame.
BufferIndex,: index of the buffer to be configured. This parameter can be a value of
  • FDCAN_Tx_location.
Return values:
HAL status

Definition at line 1590 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_TxHeaderTypeDef::BitRateSwitch, FDCAN_TxHeaderTypeDef::DataLength, FDCAN_HandleTypeDef::ErrorCode, FDCAN_TxHeaderTypeDef::ErrorStateIndicator, FDCAN_CopyMessageToRAM(), FDCAN_STANDARD_ID, FDCAN_TxHeaderTypeDef::FDFormat, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_PARAM, HAL_FDCAN_ERROR_PENDING, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, FDCAN_TxHeaderTypeDef::Identifier, FDCAN_TxHeaderTypeDef::IdType, FDCAN_HandleTypeDef::Instance, IS_FDCAN_BRS, IS_FDCAN_DLC, IS_FDCAN_EFC, IS_FDCAN_ESI, IS_FDCAN_FDF, IS_FDCAN_FRAME_TYPE, IS_FDCAN_ID_TYPE, IS_FDCAN_MAX_VALUE, IS_FDCAN_TX_LOCATION, FDCAN_TxHeaderTypeDef::MessageMarker, FDCAN_HandleTypeDef::State, FDCAN_TxHeaderTypeDef::TxEventFifoControl, and FDCAN_TxHeaderTypeDef::TxFrameType.

HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_TxHeaderTypeDef * | pTxHeader,
 |  | uint8_t * | pTxData
 | ) |  |

Add a message to the Tx FIFO/Queue and activate the corresponding transmission request.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
pTxHeader,: pointer to a FDCAN_TxHeaderTypeDef structure.
pTxData,: pointer to a buffer containing the payload of the Tx frame.
Return values:
HAL status

Definition at line 1515 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_TxHeaderTypeDef::BitRateSwitch, FDCAN_TxHeaderTypeDef::DataLength, FDCAN_HandleTypeDef::ErrorCode, FDCAN_TxHeaderTypeDef::ErrorStateIndicator, FDCAN_CopyMessageToRAM(), FDCAN_STANDARD_ID, FDCAN_TxHeaderTypeDef::FDFormat, HAL_FDCAN_ERROR_NOT_STARTED, HAL_FDCAN_ERROR_PARAM, HAL_FDCAN_STATE_BUSY, FDCAN_TxHeaderTypeDef::Identifier, FDCAN_TxHeaderTypeDef::IdType, FDCAN_HandleTypeDef::Instance, IS_FDCAN_BRS, IS_FDCAN_DLC, IS_FDCAN_EFC, IS_FDCAN_ESI, IS_FDCAN_FDF, IS_FDCAN_FRAME_TYPE, IS_FDCAN_ID_TYPE, IS_FDCAN_MAX_VALUE, FDCAN_TxHeaderTypeDef::MessageMarker, FDCAN_HandleTypeDef::State, FDCAN_TxHeaderTypeDef::TxEventFifoControl, and FDCAN_TxHeaderTypeDef::TxFrameType.

HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | BufferIndex
 | ) |  |

Enable transmission request.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
BufferIndex,: buffer index. This parameter can be any combination of
  • FDCAN_Tx_location.
Return values:
HAL status

Definition at line 1656 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_STARTED, HAL_FDCAN_STATE_BUSY, FDCAN_HandleTypeDef::Instance, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode ( FDCAN_HandleTypeDef * hfdcan )

Exit Restricted Operation Mode.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2162 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_ErrorCountersTypeDef * | ErrorCounters
 | ) |  |

Get error counter values.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ErrorCounters,: pointer to an FDCAN_ErrorCountersTypeDef structure.
Return values:
HAL status

Definition at line 2016 of file stm32h7xx_hal_fdcan.c.

References FDCAN_ErrorCountersTypeDef::ErrorLogging, FDCAN_HandleTypeDef::Instance, FDCAN_ErrorCountersTypeDef::RxErrorCnt, FDCAN_ErrorCountersTypeDef::RxErrorPassive, and FDCAN_ErrorCountersTypeDef::TxErrorCnt.

HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_HpMsgStatusTypeDef * | HpMsgStatus
 | ) |  |

Get high priority message status.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
HpMsgStatus,: pointer to an FDCAN_HpMsgStatusTypeDef structure.
Return values:
HAL status

Definition at line 1967 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HpMsgStatusTypeDef::FilterIndex, FDCAN_HpMsgStatusTypeDef::FilterList, FDCAN_HandleTypeDef::Instance, FDCAN_HpMsgStatusTypeDef::MessageIndex, and FDCAN_HpMsgStatusTypeDef::MessageStorage.

HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_ProtocolStatusTypeDef * | ProtocolStatus
 | ) |  |

Get protocol status.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ProtocolStatus,: pointer to an FDCAN_ProtocolStatusTypeDef structure.
Return values:
HAL status

Definition at line 1985 of file stm32h7xx_hal_fdcan.c.

References FDCAN_ProtocolStatusTypeDef::Activity, FDCAN_ProtocolStatusTypeDef::BusOff, FDCAN_ProtocolStatusTypeDef::DataLastErrorCode, FDCAN_ProtocolStatusTypeDef::ErrorPassive, FDCAN_HandleTypeDef::Instance, FDCAN_ProtocolStatusTypeDef::LastErrorCode, FDCAN_ProtocolStatusTypeDef::ProtocolException, FDCAN_ProtocolStatusTypeDef::RxBRSflag, FDCAN_ProtocolStatusTypeDef::RxESIflag, FDCAN_ProtocolStatusTypeDef::RxFDFflag, FDCAN_ProtocolStatusTypeDef::TDCvalue, and FDCAN_ProtocolStatusTypeDef::Warning.

uint32_t HAL_FDCAN_GetRxFifoFillLevel | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxFifo
 | ) |  |

Return Rx FIFO fill level.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxFifo,: Rx FIFO. This parameter can be one of the following values:
  • FDCAN_RX_FIFO0: Rx FIFO 0
  • FDCAN_RX_FIFO1: Rx FIFO 1
Return values:
Level,: Rx FIFO fill level.

Definition at line 2101 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_RX_FIFO0, FDCAN_HandleTypeDef::Instance, and IS_FDCAN_RX_FIFO.

HAL_StatusTypeDef HAL_FDCAN_GetRxMessage | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxLocation,
 |  | FDCAN_RxHeaderTypeDef * | pRxHeader,
 |  | uint8_t * | pRxData
 | ) |  |

Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxLocation,: Location of the received message to be read. This parameter can be a value of
  • FDCAN_Rx_location.
pRxHeader,: pointer to a FDCAN_RxHeaderTypeDef structure.
pRxData,: pointer to a buffer where the payload of the Rx frame will be stored.
Return values:
HAL status

Definition at line 1712 of file stm32h7xx_hal_fdcan.c.

References FDCAN_RxHeaderTypeDef::BitRateSwitch, FDCAN_RxHeaderTypeDef::DataLength, DLCtoBytes, FDCAN_HandleTypeDef::ErrorCode, FDCAN_RxHeaderTypeDef::ErrorStateIndicator, FDCAN_ELEMENT_MASK_ANMF, FDCAN_ELEMENT_MASK_BRS, FDCAN_ELEMENT_MASK_DLC, FDCAN_ELEMENT_MASK_ESI, FDCAN_ELEMENT_MASK_EXTID, FDCAN_ELEMENT_MASK_FDF, FDCAN_ELEMENT_MASK_FIDX, FDCAN_ELEMENT_MASK_RTR, FDCAN_ELEMENT_MASK_STDID, FDCAN_ELEMENT_MASK_TS, FDCAN_ELEMENT_MASK_XTD, FDCAN_RX_BUFFER32, FDCAN_RX_FIFO0, FDCAN_RX_FIFO1, FDCAN_STANDARD_ID, FDCAN_RxHeaderTypeDef::FDFormat, FDCAN_RxHeaderTypeDef::FilterIndex, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_PARAM, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, FDCAN_RxHeaderTypeDef::Identifier, FDCAN_RxHeaderTypeDef::IdType, FDCAN_HandleTypeDef::Init, FDCAN_HandleTypeDef::Instance, FDCAN_RxHeaderTypeDef::IsFilterMatchingFrame, FDCAN_HandleTypeDef::msgRam, FDCAN_MsgRamAddressTypeDef::RxBufferSA, FDCAN_InitTypeDef::RxBufferSize, FDCAN_InitTypeDef::RxBuffersNbr, FDCAN_InitTypeDef::RxFifo0ElmtSize, FDCAN_MsgRamAddressTypeDef::RxFIFO0SA, FDCAN_InitTypeDef::RxFifo1ElmtSize, FDCAN_MsgRamAddressTypeDef::RxFIFO1SA, FDCAN_RxHeaderTypeDef::RxFrameType, FDCAN_RxHeaderTypeDef::RxTimestamp, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_GetTxEvent | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_TxEventFifoTypeDef * | pTxEvent
 | ) |  |

Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
pTxEvent,: pointer to a FDCAN_TxEventFifoTypeDef structure.
Return values:
HAL status

Definition at line 1876 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_TxEventFifoTypeDef::BitRateSwitch, FDCAN_TxEventFifoTypeDef::DataLength, FDCAN_HandleTypeDef::ErrorCode, FDCAN_TxEventFifoTypeDef::ErrorStateIndicator, FDCAN_TxEventFifoTypeDef::EventType, FDCAN_ELEMENT_MASK_BRS, FDCAN_ELEMENT_MASK_DLC, FDCAN_ELEMENT_MASK_ESI, FDCAN_ELEMENT_MASK_ET, FDCAN_ELEMENT_MASK_EXTID, FDCAN_ELEMENT_MASK_FDF, FDCAN_ELEMENT_MASK_MM, FDCAN_ELEMENT_MASK_RTR, FDCAN_ELEMENT_MASK_STDID, FDCAN_ELEMENT_MASK_TS, FDCAN_ELEMENT_MASK_XTD, FDCAN_STANDARD_ID, FDCAN_TxEventFifoTypeDef::FDFormat, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_PARAM, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, FDCAN_TxEventFifoTypeDef::Identifier, FDCAN_TxEventFifoTypeDef::IdType, FDCAN_HandleTypeDef::Init, FDCAN_HandleTypeDef::Instance, IS_FDCAN_MIN_VALUE, FDCAN_TxEventFifoTypeDef::MessageMarker, FDCAN_HandleTypeDef::msgRam, FDCAN_HandleTypeDef::State, FDCAN_MsgRamAddressTypeDef::TxEventFIFOSA, FDCAN_InitTypeDef::TxEventsNbr, FDCAN_TxEventFifoTypeDef::TxFrameType, and FDCAN_TxEventFifoTypeDef::TxTimestamp.

uint32_t HAL_FDCAN_GetTxFifoFreeLevel ( FDCAN_HandleTypeDef * hfdcan )

Return Tx FIFO free level: number of consecutive free Tx FIFO elements starting from Tx FIFO GetIndex.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
Level,: Tx FIFO free level.

Definition at line 2128 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HandleTypeDef::Instance.

uint32_t HAL_FDCAN_IsRestrictedOperationMode ( FDCAN_HandleTypeDef * hfdcan )

Check if the FDCAN peripheral entered Restricted Operation Mode.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
Status,:
  • 0 : Normal FDCAN operation.
  • 1 : Restricted Operation Mode active.

Definition at line 2146 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HandleTypeDef::Instance.

uint32_t HAL_FDCAN_IsRxBufferMessageAvailable | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxBufferIndex
 | ) |  |

Check if a new message is received in the selected Rx buffer.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxBufferIndex,: Rx buffer index. This parameter must be a number between 0 and 63.
Return values:
Status,:
  • 0 : No new message on RxBufferIndex.
  • 1 : New message received on RxBufferIndex.

Definition at line 2043 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::Instance, and IS_FDCAN_MAX_VALUE.

uint32_t HAL_FDCAN_IsTxBufferMessagePending | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TxBufferIndex
 | ) |  |

Check if a transmission request is pending on the selected Tx buffer.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TxBufferIndex,: Tx buffer index. This parameter can be a value of
  • FDCAN_Tx_location.
Return values:
Status,:
  • 0 : No pending transmission request on RxBufferIndex.
  • 1 : Pending transmission request on RxBufferIndex.

Definition at line 2078 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::Instance, and IS_FDCAN_TX_LOCATION.

HAL_StatusTypeDef HAL_FDCAN_Start ( FDCAN_HandleTypeDef * hfdcan )

Start the FDCAN module.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1433 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NONE, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_Stop ( FDCAN_HandleTypeDef * hfdcan )

Stop the FDCAN module and enable access to configuration registers.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1464 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_NOT_STARTED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, and FDCAN_HandleTypeDef::State.

Referenced by HAL_FDCAN_DeInit().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TT Configuration and control functions

Functions
TT Configuration and control functions
FDCAN Exported Functions

TT Configuration and control functions. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigOperation (FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams)
Initialize TT operation parameters.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigReferenceMessage (FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload)
Configure the reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigTrigger (FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig)
Configure the FDCAN trigger according to the specified parameters in the FDCAN_TriggerTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_TT_SetGlobalTime (FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset)
Schedule global time adjustment for the next reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_SetClockSynchronization (FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator)
Schedule TUR numerator update for the next reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigStopWatch (FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity)
Configure stop watch source and polarity.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigRegisterTimeMark (FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle)
Configure register time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableRegisterTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Enable register time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableRegisterTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Disable register time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableTriggerTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Enable trigger time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableTriggerTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Disable trigger time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableHardwareGapControl (FDCAN_HandleTypeDef *hfdcan)
Enable gap control by input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableHardwareGapControl (FDCAN_HandleTypeDef *hfdcan)
Disable gap control by input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableTimeMarkGapControl (FDCAN_HandleTypeDef *hfdcan)
Enable gap control (finish only) by register time mark interrupt.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableTimeMarkGapControl (FDCAN_HandleTypeDef *hfdcan)
Disable gap control by register time mark interrupt.
HAL_StatusTypeDef | HAL_FDCAN_TT_SetNextIsGap (FDCAN_HandleTypeDef *hfdcan)
Transmit next reference message with Next_is_Gap = "1".
HAL_StatusTypeDef | HAL_FDCAN_TT_SetEndOfGap (FDCAN_HandleTypeDef *hfdcan)
Finish a Gap by requesting start of reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigExternalSyncPhase (FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase)
Configure target phase used for external synchronization by event trigger input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableExternalSynchronization (FDCAN_HandleTypeDef *hfdcan)
Synchronize the phase of the FDCAN schedule to an external schedule using event trigger input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableExternalSynchronization (FDCAN_HandleTypeDef *hfdcan)
Disable external schedule synchronization.
HAL_StatusTypeDef | HAL_FDCAN_TT_GetOperationStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus)
Get TT operation status.

Detailed Description

TT Configuration and control functions.

  ==============================================================================
              ##### TT Configuration and control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) HAL_FDCAN_TT_ConfigOperation                  : Initialize TT operation parameters
      (+) HAL_FDCAN_TT_ConfigReferenceMessage           : Configure the reference message
      (+) HAL_FDCAN_TT_ConfigTrigger                    : Configure the FDCAN trigger
      (+) HAL_FDCAN_TT_SetGlobalTime                    : Schedule global time adjustment
      (+) HAL_FDCAN_TT_SetClockSynchronization          : Schedule TUR numerator update
      (+) HAL_FDCAN_TT_ConfigStopWatch                  : Configure stop watch source and polarity
      (+) HAL_FDCAN_TT_ConfigRegisterTimeMark           : Configure register time mark pulse generation
        (+) HAL_FDCAN_TT_EnableRegisterTimeMarkPulse      : Enable register time mark pulse generation
        (+) HAL_FDCAN_TT_DisableRegisterTimeMarkPulse     : Disable register time mark pulse generation
      (+) HAL_FDCAN_TT_EnableTriggerTimeMarkPulse       : Enable trigger time mark pulse generation
      (+) HAL_FDCAN_TT_DisableTriggerTimeMarkPulse      : Disable trigger time mark pulse generation
      (+) HAL_FDCAN_TT_EnableHardwareGapControl         : Enable gap control by input pin fdcan1_evt
      (+) HAL_FDCAN_TT_DisableHardwareGapControl        : Disable gap control by input pin fdcan1_evt
      (+) HAL_FDCAN_TT_EnableTimeMarkGapControl         : Enable gap control (finish only) by register time mark interrupt
      (+) HAL_FDCAN_TT_DisableTimeMarkGapControl        : Disable gap control by register time mark interrupt
      (+) HAL_FDCAN_TT_SetNextIsGap                     : Transmit next reference message with Next_is_Gap = "1"
      (+) HAL_FDCAN_TT_SetEndOfGap                      : Finish a Gap by requesting start of reference message
      (+) HAL_FDCAN_TT_ConfigExternalSyncPhase          : Configure target phase used for external synchronization
        (+) HAL_FDCAN_TT_EnableExternalSynchronization    : Synchronize the phase of the FDCAN schedule to an external schedule
        (+) HAL_FDCAN_TT_DisableExternalSynchronization   : Disable external schedule synchronization
      (+) HAL_FDCAN_TT_GetOperationStatus               : Get TT operation status

Function Documentation

HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TargetPhase
 | ) |  |

Configure target phase used for external synchronization by event trigger input pin fdcan1_evt.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TargetPhase,: defines target value of cycle time when a rising edge of fdcan1_evt is expected. This parameter must be a number between 0 and 0xFFFF.
Return values:
HAL status

Definition at line 3442 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_PENDING, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, FDCAN_HandleTypeDef::State, and FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_TT_ConfigTypeDef * | pTTParams
 | ) |  |

Initialize TT operation parameters.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
pTTParams,: pointer to a FDCAN_TT_ConfigTypeDef structure.
Return values:
HAL status

Definition at line 2226 of file stm32h7xx_hal_fdcan.c.

References FDCAN_TT_ConfigTypeDef::AppWdgLimit, assert_param, FDCAN_TT_ConfigTypeDef::BasicCyclesNbr, FDCAN_TT_ConfigTypeDef::ClockCalibration, FDCAN_TT_ConfigTypeDef::CycleStartSync, FDCAN_MsgRamAddressTypeDef::EndAddress, FDCAN_HandleTypeDef::ErrorCode, FDCAN_TT_ConfigTypeDef::EventTrigSel, FDCAN_TT_ConfigTypeDef::EvtTrigPolarity, FDCAN_TT_ConfigTypeDef::ExpTxTrigNbr, FDCAN_TT_ConfigTypeDef::ExternalClkSync, FDCAN_TIMEOUT_VALUE, FDCAN_TT_COMMUNICATION_LEVEL0, FDCAN_TT_COMMUNICATION_LEVEL1, FDCAN_TT_POTENTIAL_MASTER, FDCAN_TT_ConfigTypeDef::GapEnable, FDCAN_TT_ConfigTypeDef::GlobalTimeFilter, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_ERROR_PARAM, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, HAL_GetTick(), FDCAN_TT_ConfigTypeDef::InitRefTrigOffset, FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, IS_FDCAN_TT_AUTO_CLK_CALIBRATION, IS_FDCAN_TT_BASIC_CYCLES_NUMBER, IS_FDCAN_TT_CYCLE_START_SYNC, IS_FDCAN_TT_EVENT_TRIGGER, IS_FDCAN_TT_EVENT_TRIGGER_POLARITY, IS_FDCAN_TT_EXTERNAL_CLK_SYNC, IS_FDCAN_TT_GLOBAL_TIME_FILTERING, IS_FDCAN_TT_OPERATION, IS_FDCAN_TT_STOP_WATCH_TRIGGER, IS_FDCAN_TT_TIME_MASTER, IS_FDCAN_TT_TUR_DENOMINATOR, IS_FDCAN_TT_TUR_LEVEL_0_2, IS_FDCAN_TT_TUR_LEVEL_1, IS_FDCAN_TT_TUR_NUMERATOR, IS_FDCAN_TT_TX_ENABLE_WINDOW, FDCAN_HandleTypeDef::msgRam, FDCAN_TT_ConfigTypeDef::OperationMode, FDCAN_HandleTypeDef::State, FDCAN_TT_ConfigTypeDef::StopWatchTrigSel, FDCAN_TT_ConfigTypeDef::SyncDevLimit, FDCAN_TT_ConfigTypeDef::TimeMaster, FDCAN_TT_ConfigTypeDef::TriggerMemoryNbr, FDCAN_HandleTypeDef::ttcan, FDCAN_MsgRamAddressTypeDef::TTMemorySA, FDCAN_TT_ConfigTypeDef::TURDenominator, FDCAN_TT_ConfigTypeDef::TURNumerator, and FDCAN_TT_ConfigTypeDef::TxEnableWindow.

HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | IdType,
 |  | uint32_t | Identifier,
 |  | uint32_t | Payload
 | ) |  |

Configure the reference message.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
IdType,: Identifier Type. This parameter can be a value of
  • FDCAN_id_type.
Identifier,: Reference Identifier. This parameter must be a number between:
  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID
Payload,: Enable or disable the additional payload. This parameter can be a value of
  • FDCAN_TT_Reference_Message_Payload. This parameter is ignored in case of time slaves. If this parameter is set to FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD, the following elements are taken from Tx Buffer 0:
    • MessageMarker
    • TxEventFifoControl
    • DataLength
    • Data Bytes (payload):
      • bytes 2-8, for Level 1
      • bytes 5-8, for Level 0 and Level 2
Return values:
HAL status

Definition at line 2403 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_EXTENDED_ID, FDCAN_STANDARD_ID, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, IS_FDCAN_ID_TYPE, IS_FDCAN_MAX_VALUE, IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD, FDCAN_HandleTypeDef::State, and FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TimeMarkSource,
 |  | uint32_t | TimeMarkValue,
 |  | uint32_t | RepeatFactor,
 |  | uint32_t | StartCycle
 | ) |  |

Configure register time mark pulse generation.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TimeMarkSource,: time mark source. This parameter can be a value of
  • FDCAN_TT_time_mark_source.
TimeMarkValue,: time mark value (reference). This parameter must be a number between 0 and 0xFFFF.
RepeatFactor,: repeat factor of the cycle for which the time mark is valid. This parameter can be a value of
  • FDCAN_TT_Repeat_Factor.
StartCycle,: index of the first cycle in which the time mark becomes valid. This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE. This parameter must be a number between 0 and RepeatFactor.
Return values:
HAL status

Definition at line 2759 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, FDCAN_TT_REG_TIMEMARK_DIABLED, FDCAN_TT_REPEAT_EVERY_CYCLE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE, IS_FDCAN_TT_REPEAT_FACTOR, FDCAN_HandleTypeDef::State, and FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | Source,
 |  | uint32_t | Polarity
 | ) |  |

Configure stop watch source and polarity.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Source,: stop watch source. This parameter can be a value of
  • FDCAN_TT_stop_watch_source.
Polarity,: stop watch polarity. This parameter can be a value of
  • FDCAN_TT_stop_watch_polarity.
Return values:
HAL status

Definition at line 2702 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, IS_FDCAN_TT_STOP_WATCH_POLARITY, IS_FDCAN_TT_STOP_WATCH_SOURCE, FDCAN_HandleTypeDef::State, and FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_TriggerTypeDef * | sTriggerConfig
 | ) |  |

Configure the FDCAN trigger according to the specified parameters in the FDCAN_TriggerTypeDef structure.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
sTriggerConfig,: pointer to an FDCAN_TriggerTypeDef structure that contains the trigger configuration information
Return values:
HAL status

Definition at line 2451 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_STANDARD_ID, FDCAN_TT_REPEAT_EVERY_CYCLE, FDCAN_TT_RX_TRIGGER, FDCAN_TT_TX_TRIGGER_ARBITRATION, FDCAN_TT_TX_TRIGGER_CONTINUOUS, FDCAN_TT_TX_TRIGGER_MERGED, FDCAN_TT_TX_TRIGGER_SINGLE, FDCAN_TriggerTypeDef::FilterIndex, FDCAN_TriggerTypeDef::FilterType, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, IS_FDCAN_ID_TYPE, IS_FDCAN_MAX_VALUE, IS_FDCAN_TT_REPEAT_FACTOR, IS_FDCAN_TT_TM_EVENT_EXTERNAL, IS_FDCAN_TT_TM_EVENT_INTERNAL, IS_FDCAN_TT_TRIGGER_TYPE, IS_FDCAN_TX_LOCATION, FDCAN_HandleTypeDef::msgRam, FDCAN_TriggerTypeDef::RepeatFactor, FDCAN_TriggerTypeDef::StartCycle, FDCAN_HandleTypeDef::State, FDCAN_TriggerTypeDef::TimeMark, FDCAN_TriggerTypeDef::TmEventExt, FDCAN_TriggerTypeDef::TmEventInt, FDCAN_TriggerTypeDef::TriggerIndex, FDCAN_TriggerTypeDef::TriggerType, FDCAN_MsgRamAddressTypeDef::TTMemorySA, and FDCAN_TriggerTypeDef::TxBufferIndex.

HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization ( FDCAN_HandleTypeDef * hfdcan )

Disable external schedule synchronization.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 3527 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, FDCAN_HandleTypeDef::State, and FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl ( FDCAN_HandleTypeDef * hfdcan )

Disable gap control by input pin fdcan1_evt.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 3133 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, FDCAN_TT_COMMUNICATION_LEVEL0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_NOT_SUPPORTED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, FDCAN_HandleTypeDef::State, and FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse ( FDCAN_HandleTypeDef * hfdcan )

Disable register time mark pulse generation.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2916 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, FDCAN_HandleTypeDef::State, and FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl ( FDCAN_HandleTypeDef * hfdcan )

Disable gap control by register time mark interrupt.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 3249 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, FDCAN_TT_COMMUNICATION_LEVEL0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_NOT_SUPPORTED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, FDCAN_HandleTypeDef::State, and FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse ( FDCAN_HandleTypeDef * hfdcan )

Disable trigger time mark pulse generation.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 3019 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, FDCAN_TT_COMMUNICATION_LEVEL0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_NOT_SUPPORTED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, FDCAN_HandleTypeDef::State, and FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization ( FDCAN_HandleTypeDef * hfdcan )

Synchronize the phase of the FDCAN schedule to an external schedule using event trigger input pin fdcan1_evt.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 3481 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, FDCAN_HandleTypeDef::State, and FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl ( FDCAN_HandleTypeDef * hfdcan )

Enable gap control by input pin fdcan1_evt.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 3076 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, FDCAN_TT_COMMUNICATION_LEVEL0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_NOT_SUPPORTED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, FDCAN_HandleTypeDef::State, and FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse ( FDCAN_HandleTypeDef * hfdcan )

Enable register time mark pulse generation.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2870 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, FDCAN_HandleTypeDef::State, and FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl ( FDCAN_HandleTypeDef * hfdcan )

Enable gap control (finish only) by register time mark interrupt.

The next register time mark interrupt (TTIR.RTMI = "1") will finish the Gap and start the reference message.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 3192 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, FDCAN_TT_COMMUNICATION_LEVEL0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_NOT_SUPPORTED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, FDCAN_HandleTypeDef::State, and FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse ( FDCAN_HandleTypeDef * hfdcan )

Enable trigger time mark pulse generation.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2962 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, FDCAN_TT_COMMUNICATION_LEVEL0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_NOT_SUPPORTED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, FDCAN_HandleTypeDef::State, and FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_TTOperationStatusTypeDef * | TTOpStatus
 | ) |  |

Get TT operation status.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TTOpStatus,: pointer to an FDCAN_TTOperationStatusTypeDef structure.
Return values:
HAL status

Definition at line 3574 of file stm32h7xx_hal_fdcan.c.

References FDCAN_TTOperationStatusTypeDef::AppWdgEvt, assert_param, FDCAN_TTOperationStatusTypeDef::ClockQuality, FDCAN_TTOperationStatusTypeDef::ECSPending, FDCAN_TTOperationStatusTypeDef::ErrorLevel, FDCAN_TTOperationStatusTypeDef::GapFinished, FDCAN_TTOperationStatusTypeDef::GapStarted, FDCAN_TTOperationStatusTypeDef::GTimeDiscPending, FDCAN_TTOperationStatusTypeDef::GTimeQuality, FDCAN_HandleTypeDef::Instance, FDCAN_TTOperationStatusTypeDef::MasterPriority, FDCAN_TTOperationStatusTypeDef::MasterState, FDCAN_TTOperationStatusTypeDef::PhaseLock, FDCAN_TTOperationStatusTypeDef::RefTrigOffset, FDCAN_TTOperationStatusTypeDef::SyncState, FDCAN_HandleTypeDef::ttcan, and FDCAN_TTOperationStatusTypeDef::WaitForEvt.

HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | NewTURNumerator
 | ) |  |

Schedule TUR numerator update for the next reference message.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
NewTURNumerator,: new value of the TUR numerator. This parameter must be a number between 0x10000 and 0x1FFFF.
Return values:
HAL status

Definition at line 2630 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_NOT_SUPPORTED, HAL_FDCAN_ERROR_PENDING, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, IS_FDCAN_TT_TUR_NUMERATOR, FDCAN_HandleTypeDef::State, and FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap ( FDCAN_HandleTypeDef * hfdcan )

Finish a Gap by requesting start of reference message.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 3372 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, FDCAN_TT_COMMUNICATION_LEVEL0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_NOT_SUPPORTED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, FDCAN_HandleTypeDef::State, and FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TimePreset
 | ) |  |

Schedule global time adjustment for the next reference message.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TimePreset,: time preset value. This parameter must be a number between:
  • 0x0000 and 0x7FFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark + TimePreset or:
  • 0x8001 and 0xFFFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark - (0x10000 - TimePreset)
Return values:
HAL status

Definition at line 2560 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_NOT_SUPPORTED, HAL_FDCAN_ERROR_PENDING, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, IS_FDCAN_TT_TIME_PRESET, FDCAN_HandleTypeDef::State, and FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap ( FDCAN_HandleTypeDef * hfdcan )

Transmit next reference message with Next_is_Gap = "1".

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 3306 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, FDCAN_TT_COMMUNICATION_LEVEL0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_ERROR_NOT_SUPPORTED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, FDCAN_HandleTypeDef::State, and FDCAN_HandleTypeDef::ttcan.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Interrupts management

Functions
Interrupts management
FDCAN Exported Functions

Interrupts management. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_ConfigInterruptLines (FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
Assign interrupts to either Interrupt line 0 or 1.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigInterruptLines (FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine)
Assign TT interrupts to either Interrupt line 0 or 1.
HAL_StatusTypeDef | HAL_FDCAN_ActivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
Enable interrupts.
HAL_StatusTypeDef | HAL_FDCAN_DeactivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
Disable interrupts.
HAL_StatusTypeDef | HAL_FDCAN_TT_ActivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs)
Enable TT interrupts.
HAL_StatusTypeDef | HAL_FDCAN_TT_DeactivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs)
Disable TT interrupts.
void | HAL_FDCAN_IRQHandler (FDCAN_HandleTypeDef *hfdcan)
Handles FDCAN interrupt request.

Detailed Description

Interrupts management.

  ==============================================================================
                       ##### Interrupts management #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) HAL_FDCAN_ConfigInterruptLines      : Assign interrupts to either Interrupt line 0 or 1
      (+) HAL_FDCAN_TT_ConfigInterruptLines   : Assign TT interrupts to either Interrupt line 0 or 1
      (+) HAL_FDCAN_ActivateNotification      : Enable interrupts
      (+) HAL_FDCAN_DeactivateNotification    : Disable interrupts
      (+) HAL_FDCAN_TT_ActivateNotification   : Enable TT interrupts
      (+) HAL_FDCAN_TT_DeactivateNotification : Disable TT interrupts
      (+) HAL_FDCAN_IRQHandler                : Handles FDCAN interrupt request

Function Documentation

HAL_StatusTypeDef HAL_FDCAN_ActivateNotification | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | ActiveITs,
 |  | uint32_t | BufferIndexes
 | ) |  |

Enable interrupts.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ActiveITs,: indicates which interrupts will be enabled. This parameter can be any combination of
  • FDCAN_Interrupts.
BufferIndexes,: Tx Buffer Indexes. This parameter can be any combination of
  • FDCAN_Tx_location. This parameter is ignored if ActiveITs does not include one of the following:
    • FDCAN_IT_TX_COMPLETE
    • FDCAN_IT_TX_ABORT_COMPLETE
Return values:
HAL status

Definition at line 3722 of file stm32h7xx_hal_fdcan.c.

References __HAL_FDCAN_ENABLE_IT, assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_INTERRUPT_LINE0, FDCAN_INTERRUPT_LINE1, FDCAN_IT_TX_ABORT_COMPLETE, FDCAN_IT_TX_COMPLETE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, IS_FDCAN_IT, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | ITList,
 |  | uint32_t | InterruptLine
 | ) |  |

Assign interrupts to either Interrupt line 0 or 1.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ITList,: indicates which interrupts will be assigned to the selected interrupt line. This parameter can be any combination of
  • FDCAN_Interrupts.
InterruptLine,: Interrupt line. This parameter can be a value of
  • FDCAN_Interrupt_Line.
Return values:
HAL status

Definition at line 3638 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_INTERRUPT_LINE0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, IS_FDCAN_IT, IS_FDCAN_IT_LINE, and FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | InactiveITs
 | ) |  |

Disable interrupts.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
InactiveITs,: indicates which interrupts will be disabled. This parameter can be any combination of
  • FDCAN_Interrupts.
Return values:
HAL status

Definition at line 3783 of file stm32h7xx_hal_fdcan.c.

References __HAL_FDCAN_DISABLE_IT, assert_param, FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, IS_FDCAN_IT, and FDCAN_HandleTypeDef::State.

void HAL_FDCAN_IRQHandler ( FDCAN_HandleTypeDef * hfdcan )

Handles FDCAN interrupt request.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 3888 of file stm32h7xx_hal_fdcan.c.

References __HAL_FDCAN_CLEAR_FLAG, __HAL_FDCAN_DISABLE_IT, __HAL_FDCAN_GET_FLAG, __HAL_FDCAN_GET_IT_SOURCE, __HAL_FDCAN_TT_CLEAR_FLAG, __HAL_FDCAN_TT_DISABLE_IT, __HAL_FDCAN_TT_GET_FLAG, __HAL_FDCAN_TT_GET_IT_SOURCE, FDCAN_HandleTypeDef::ErrorCode, FDCAN_ERROR_MASK, FDCAN_FLAG_RAM_ACCESS_FAILURE, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG, FDCAN_FLAG_TIMEOUT_OCCURRED, FDCAN_FLAG_TIMESTAMP_WRAPAROUND, FDCAN_FLAG_TX_ABORT_COMPLETE, FDCAN_FLAG_TX_COMPLETE, FDCAN_FLAG_TX_FIFO_EMPTY, FDCAN_IT_RAM_ACCESS_FAILURE, FDCAN_IT_RX_BUFFER_NEW_MESSAGE, FDCAN_IT_RX_HIGH_PRIORITY_MSG, FDCAN_IT_TIMEOUT_OCCURRED, FDCAN_IT_TIMESTAMP_WRAPAROUND, FDCAN_IT_TX_ABORT_COMPLETE, FDCAN_IT_TX_COMPLETE, FDCAN_IT_TX_FIFO_EMPTY, FDCAN_RX_FIFO0_MASK, FDCAN_RX_FIFO1_MASK, FDCAN_TT_DISTURBING_ERROR_MASK, FDCAN_TT_FATAL_ERROR_MASK, FDCAN_TT_FLAG_STOP_WATCH, FDCAN_TT_GLOBAL_TIME_MASK, FDCAN_TT_IT_STOP_WATCH, FDCAN_TT_SCHEDULE_SYNC_MASK, FDCAN_TT_TIME_MARK_MASK, FDCAN_TX_EVENT_FIFO_MASK, HAL_FDCAN_ClockCalibrationCallback(), HAL_FDCAN_ERROR_NONE, HAL_FDCAN_ERROR_RAM_ACCESS, HAL_FDCAN_ErrorCallback(), HAL_FDCAN_HighPriorityMessageCallback(), HAL_FDCAN_RxBufferNewMessageCallback(), HAL_FDCAN_RxFifo0Callback(), HAL_FDCAN_RxFifo1Callback(), HAL_FDCAN_TimeoutOccurredCallback(), HAL_FDCAN_TimestampWraparoundCallback(), HAL_FDCAN_TT_GlobalTimeCallback(), HAL_FDCAN_TT_ScheduleSyncCallback(), HAL_FDCAN_TT_StopWatchCallback(), HAL_FDCAN_TT_TimeMarkCallback(), HAL_FDCAN_TxBufferAbortCallback(), HAL_FDCAN_TxBufferCompleteCallback(), HAL_FDCAN_TxEventFifoCallback(), HAL_FDCAN_TxFifoEmptyCallback(), FDCAN_HandleTypeDef::Instance, and FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | ActiveTTITs
 | ) |  |

Enable TT interrupts.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ActiveTTITs,: indicates which TT interrupts will be enabled. This parameter can be any combination of
  • FDCAN_TTInterrupts.
Return values:
HAL status

Definition at line 3813 of file stm32h7xx_hal_fdcan.c.

References __HAL_FDCAN_TT_ENABLE_IT, assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_INTERRUPT_LINE0, FDCAN_INTERRUPT_LINE1, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, IS_FDCAN_TT_IT, FDCAN_HandleTypeDef::State, and FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TTITList,
 |  | uint32_t | InterruptLine
 | ) |  |

Assign TT interrupts to either Interrupt line 0 or 1.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TTITList,: indicates which interrupts will be assigned to the selected interrupt line. This parameter can be any combination of
  • FDCAN_TTInterrupts.
InterruptLine,: Interrupt line. This parameter can be a value of
  • FDCAN_Interrupt_Line.
Return values:
HAL status

Definition at line 3678 of file stm32h7xx_hal_fdcan.c.

References assert_param, FDCAN_HandleTypeDef::ErrorCode, FDCAN_INTERRUPT_LINE0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, FDCAN_HandleTypeDef::Instance, IS_FDCAN_IT_LINE, IS_FDCAN_TT_IT, FDCAN_HandleTypeDef::State, and FDCAN_HandleTypeDef::ttcan.

HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | InactiveTTITs
 | ) |  |

Disable TT interrupts.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
InactiveTTITs,: indicates which TT interrupts will be disabled. This parameter can be any combination of
  • FDCAN_TTInterrupts.
Return values:
HAL status

Definition at line 3860 of file stm32h7xx_hal_fdcan.c.

References __HAL_FDCAN_TT_DISABLE_IT, assert_param, FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, IS_FDCAN_TT_IT, and FDCAN_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Callback functions

Functions
Callback functions
FDCAN Exported Functions

FDCAN Callback functions. More...

Functions

__weak void | HAL_FDCAN_ClockCalibrationCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)
Clock Calibration callback.
__weak void | HAL_FDCAN_TxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
Tx Event callback.
__weak void | HAL_FDCAN_RxFifo0Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
Rx FIFO 0 callback.
__weak void | HAL_FDCAN_RxFifo1Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
Rx FIFO 1 callback.
__weak void | HAL_FDCAN_TxFifoEmptyCallback (FDCAN_HandleTypeDef *hfdcan)
Tx FIFO Empty callback.
__weak void | HAL_FDCAN_TxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Complete callback.
__weak void | HAL_FDCAN_TxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Cancellation callback.
__weak void | HAL_FDCAN_RxBufferNewMessageCallback (FDCAN_HandleTypeDef *hfdcan)
Rx Buffer New Message callback.
__weak void | HAL_FDCAN_TimestampWraparoundCallback (FDCAN_HandleTypeDef *hfdcan)
Timestamp Wraparound callback.
__weak void | HAL_FDCAN_TimeoutOccurredCallback (FDCAN_HandleTypeDef *hfdcan)
Timeout Occurred callback.
__weak void | HAL_FDCAN_HighPriorityMessageCallback (FDCAN_HandleTypeDef *hfdcan)
High Priority Message callback.
__weak void | HAL_FDCAN_ErrorCallback (FDCAN_HandleTypeDef *hfdcan)
Error callback.
__weak void | HAL_FDCAN_TT_ScheduleSyncCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)
TT Schedule Synchronization callback.
__weak void | HAL_FDCAN_TT_TimeMarkCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)
TT Time Mark callback.
__weak void | HAL_FDCAN_TT_StopWatchCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)
TT Stop Watch callback.
__weak void | HAL_FDCAN_TT_GlobalTimeCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)
TT Global Time callback.

Detailed Description

FDCAN Callback functions.

  ==============================================================================
                          ##### Callback functions #####
  ==============================================================================
    [..]
    This subsection provides the following callback functions:
      (+) HAL_FDCAN_ClockCalibrationCallback
      (+) HAL_FDCAN_TxEventFifoCallback
      (+) HAL_FDCAN_RxFifo0Callback
      (+) HAL_FDCAN_RxFifo1Callback
      (+) HAL_FDCAN_TxFifoEmptyCallback
      (+) HAL_FDCAN_TxBufferCompleteCallback
      (+) HAL_FDCAN_TxBufferAbortCallback
      (+) HAL_FDCAN_RxBufferNewMessageCallback
      (+) HAL_FDCAN_HighPriorityMessageCallback
      (+) HAL_FDCAN_TimestampWraparoundCallback
      (+) HAL_FDCAN_TimeoutOccurredCallback
      (+) HAL_FDCAN_ErrorCallback
      (+) HAL_FDCAN_TTSchedSyncCallback
      (+) HAL_FDCAN_TTTimeMarkCallback
      (+) HAL_FDCAN_TTStopWatchCallback
      (+) HAL_FDCAN_TTGlobalTimeCallback

Function Documentation

void HAL_FDCAN_ClockCalibrationCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | ClkCalibrationITs
 | ) |  |

Clock Calibration callback.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ClkCalibrationITs,: indicates which Clock Calibration interrupts are signalled. This parameter can be any combination of
  • FDCAN_Clock_Calibration_Interrupts.
Return values:
None

Definition at line 4272 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

void HAL_FDCAN_ErrorCallback ( FDCAN_HandleTypeDef * hfdcan )

Error callback.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 4464 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

void HAL_FDCAN_HighPriorityMessageCallback ( FDCAN_HandleTypeDef * hfdcan )

High Priority Message callback.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 4448 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

void HAL_FDCAN_RxBufferNewMessageCallback ( FDCAN_HandleTypeDef * hfdcan )

Rx Buffer New Message callback.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 4400 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

void HAL_FDCAN_RxFifo0Callback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxFifo0ITs
 | ) |  |

Rx FIFO 0 callback.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxFifo0ITs,: indicates which Rx FIFO 0 interrupts are signalled. This parameter can be any combination of
  • FDCAN_Rx_Fifo0_Interrupts.
Return values:
None

Definition at line 4310 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

void HAL_FDCAN_RxFifo1Callback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxFifo1ITs
 | ) |  |

Rx FIFO 1 callback.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxFifo1ITs,: indicates which Rx FIFO 1 interrupts are signalled. This parameter can be any combination of
  • FDCAN_Rx_Fifo1_Interrupts.
Return values:
None

Definition at line 4329 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

void HAL_FDCAN_TimeoutOccurredCallback ( FDCAN_HandleTypeDef * hfdcan )

Timeout Occurred callback.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 4432 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

void HAL_FDCAN_TimestampWraparoundCallback ( FDCAN_HandleTypeDef * hfdcan )

Timestamp Wraparound callback.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 4416 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

void HAL_FDCAN_TT_GlobalTimeCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TTGlobTimeITs
 | ) |  |

TT Global Time callback.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TTGlobTimeITs,: indicates which TT Global Time interrupts are signalled. This parameter can be any combination of
  • FDCAN_TTGlobalTime_Interrupts.
Return values:
None

Definition at line 4543 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

void HAL_FDCAN_TT_ScheduleSyncCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TTSchedSyncITs
 | ) |  |

TT Schedule Synchronization callback.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TTSchedSyncITs,: indicates which TT Schedule Synchronization interrupts are signalled. This parameter can be any combination of
  • FDCAN_TTScheduleSynchronization_Interrupts.
Return values:
None

Definition at line 4482 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

void HAL_FDCAN_TT_StopWatchCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | SWTime,
 |  | uint32_t | SWCycleCount
 | ) |  |

TT Stop Watch callback.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
SWTime,: Time Value captured at the Stop Watch Trigger pin (fdcan1_swt) falling/rising edge (as configured via HAL_FDCAN_TTConfigStopWatch). This parameter is a number between 0 and 0xFFFF.
SWCycleCount,: Cycle count value captured together with SWTime. This parameter is a number between 0 and 0x3F.
Return values:
None

Definition at line 4523 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

void HAL_FDCAN_TT_TimeMarkCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TTTimeMarkITs
 | ) |  |

TT Time Mark callback.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TTTimeMarkITs,: indicates which TT Schedule Synchronization interrupts are signalled. This parameter can be any combination of
  • FDCAN_TTTimeMark_Interrupts.
Return values:
None

Definition at line 4501 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

void HAL_FDCAN_TxBufferAbortCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | BufferIndexes
 | ) |  |

Transmission Cancellation callback.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
BufferIndexes,: Indexes of the aborted buffers. This parameter can be any combination of
  • FDCAN_Tx_location.
Return values:
None

Definition at line 4383 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

void HAL_FDCAN_TxBufferCompleteCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | BufferIndexes
 | ) |  |

Transmission Complete callback.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
BufferIndexes,: Indexes of the transmitted buffers. This parameter can be any combination of
  • FDCAN_Tx_location.
Return values:
None

Definition at line 4364 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

void HAL_FDCAN_TxEventFifoCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TxEventFifoITs
 | ) |  |

Tx Event callback.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TxEventFifoITs,: indicates which Tx Event FIFO interrupts are signalled. This parameter can be any combination of
  • FDCAN_Tx_Event_Fifo_Interrupts.
Return values:
None

Definition at line 4291 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

void HAL_FDCAN_TxFifoEmptyCallback ( FDCAN_HandleTypeDef * hfdcan )

Tx FIFO Empty callback.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 4346 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
FDCAN Exported Functions

FDCAN Peripheral State functions. More...

Functions

HAL_FDCAN_StateTypeDef | HAL_FDCAN_GetState (FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN state.
uint32_t | HAL_FDCAN_GetError (FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN error code.

Detailed Description

FDCAN Peripheral State functions.

  ==============================================================================
                      ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) HAL_FDCAN_GetState()  : Return the FDCAN state.
      (+) HAL_FDCAN_GetError()  : Return the FDCAN error code if any.

Function Documentation

uint32_t HAL_FDCAN_GetError ( FDCAN_HandleTypeDef * hfdcan )

Return the FDCAN error code.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
FDCAN Error Code

Definition at line 4591 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HandleTypeDef::ErrorCode.

HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState ( FDCAN_HandleTypeDef * hfdcan )

Return the FDCAN state.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL state

Definition at line 4579 of file stm32h7xx_hal_fdcan.c.

References FDCAN_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Exported Types

Data Structures | Enumerations
FDCAN Exported Types
FDCAN

Data Structures

struct | FDCAN_InitTypeDef
FDCAN Init structure definition. More...
struct | FDCAN_ClkCalUnitTypeDef
FDCAN clock calibration unit structure definition. More...
struct | FDCAN_FilterTypeDef
FDCAN filter structure definition. More...
struct | FDCAN_TxHeaderTypeDef
FDCAN Tx header structure definition. More...
struct | FDCAN_RxHeaderTypeDef
FDCAN Rx header structure definition. More...
struct | FDCAN_TxEventFifoTypeDef
FDCAN Tx event FIFO structure definition. More...
struct | FDCAN_HpMsgStatusTypeDef
FDCAN High Priority Message Status structure definition. More...
struct | FDCAN_ProtocolStatusTypeDef
FDCAN Protocol Status structure definition. More...
struct | FDCAN_ErrorCountersTypeDef
FDCAN Error Counters structure definition. More...
struct | FDCAN_TT_ConfigTypeDef
FDCAN TT Init structure definition. More...
struct | FDCAN_TriggerTypeDef
FDCAN Trigger structure definition. More...
struct | FDCAN_TTOperationStatusTypeDef
FDCAN TT Operation Status structure definition. More...
struct | FDCAN_MsgRamAddressTypeDef
FDCAN Message RAM blocks. More...
struct | FDCAN_HandleTypeDef
FDCAN handle structure definition. More...

Enumerations

enum | HAL_FDCAN_StateTypeDef { HAL_FDCAN_STATE_RESET = 0x00U, HAL_FDCAN_STATE_READY = 0x01U, HAL_FDCAN_STATE_BUSY = 0x02U, HAL_FDCAN_STATE_ERROR = 0x03U }
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_FDCAN_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_FDCAN_STATE_RESET

FDCAN not yet initialized or disabled

HAL_FDCAN_STATE_READY

FDCAN initialized and ready for use

HAL_FDCAN_STATE_BUSY

FDCAN process is ongoing

HAL_FDCAN_STATE_ERROR

FDCAN error state

Definition at line 65 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_InitTypeDef Struct Reference
FDCAN Exported Types

FDCAN Init structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | FrameFormat
uint32_t | Mode
FunctionalState | AutoRetransmission
FunctionalState | TransmitPause
FunctionalState | ProtocolException
uint32_t | NominalPrescaler
uint32_t | NominalSyncJumpWidth
uint32_t | NominalTimeSeg1
uint32_t | NominalTimeSeg2
uint32_t | DataPrescaler
uint32_t | DataSyncJumpWidth
uint32_t | DataTimeSeg1
uint32_t | DataTimeSeg2
uint32_t | MessageRAMOffset
uint32_t | StdFiltersNbr
uint32_t | ExtFiltersNbr
uint32_t | RxFifo0ElmtsNbr
uint32_t | RxFifo0ElmtSize
uint32_t | RxFifo1ElmtsNbr
uint32_t | RxFifo1ElmtSize
uint32_t | RxBuffersNbr
uint32_t | RxBufferSize
uint32_t | TxEventsNbr
uint32_t | TxBuffersNbr
uint32_t | TxFifoQueueElmtsNbr
uint32_t | TxFifoQueueMode
uint32_t | TxElmtSize

Detailed Description

FDCAN Init structure definition.

Definition at line 76 of file stm32h7xx_hal_fdcan.h.

Field Documentation

FunctionalState FDCAN_InitTypeDef::AutoRetransmission

Enable or disable the automatic retransmission mode. This parameter can be set to ENABLE or DISABLE

Definition at line 84 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::DataPrescaler

Specifies the value by which the oscillator frequency is divided for generating the data bit time quanta. This parameter must be a number between 1 and 32

Definition at line 108 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::DataSyncJumpWidth

Specifies the maximum number of time quanta the FDCAN hardware is allowed to lengthen or shorten a data bit to perform resynchronization. This parameter must be a number between 1 and 16

Definition at line 112 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::DataTimeSeg1

Specifies the number of time quanta in Data Bit Segment 1. This parameter must be a number between 1 and 32

Definition at line 117 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::DataTimeSeg2

Specifies the number of time quanta in Data Bit Segment 2. This parameter must be a number between 1 and 16

Definition at line 120 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::ExtFiltersNbr

Specifies the number of extended Message ID filters. This parameter must be a number between 0 and 64

Definition at line 129 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_ConfigFilter(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::FrameFormat

Specifies the FDCAN frame format. This parameter can be a value of FDCAN Frame Format

Definition at line 78 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::MessageRAMOffset

Specifies the message RAM start address. This parameter must be a number between 0 and 2560

Definition at line 123 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses().

uint32_t FDCAN_InitTypeDef::Mode

Specifies the FDCAN mode. This parameter can be a value of FDCAN Operating Mode

Definition at line 81 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::NominalPrescaler

Specifies the value by which the oscillator frequency is divided for generating the nominal bit time quanta. This parameter must be a number between 1 and 512

Definition at line 93 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::NominalSyncJumpWidth

Specifies the maximum number of time quanta the FDCAN hardware is allowed to lengthen or shorten a bit to perform resynchronization. This parameter must be a number between 1 and 128

Definition at line 97 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::NominalTimeSeg1

Specifies the number of time quanta in Bit Segment 1. This parameter must be a number between 2 and 256

Definition at line 102 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::NominalTimeSeg2

Specifies the number of time quanta in Bit Segment 2. This parameter must be a number between 2 and 128

Definition at line 105 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

FunctionalState FDCAN_InitTypeDef::ProtocolException

Enable or disable the Protocol Exception Handling. This parameter can be set to ENABLE or DISABLE

Definition at line 90 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::RxBufferSize

Specifies the Data Field Size in an Rx Buffer element. This parameter can be a value of FDCAN Data Field Size

Definition at line 147 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::RxBuffersNbr

Specifies the number of Dedicated Rx Buffer elements. This parameter must be a number between 0 and 64

Definition at line 144 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::RxFifo0ElmtSize

Specifies the Data Field Size in an Rx FIFO 0 element. This parameter can be a value of FDCAN Data Field Size

Definition at line 135 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::RxFifo0ElmtsNbr

Specifies the number of Rx FIFO0 Elements. This parameter must be a number between 0 and 64

Definition at line 132 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::RxFifo1ElmtSize

Specifies the Data Field Size in an Rx FIFO 1 element. This parameter can be a value of FDCAN Data Field Size

Definition at line 141 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::RxFifo1ElmtsNbr

Specifies the number of Rx FIFO 1 Elements. This parameter must be a number between 0 and 64

Definition at line 138 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::StdFiltersNbr

Specifies the number of standard Message ID filters. This parameter must be a number between 0 and 128

Definition at line 126 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_ConfigFilter(), and HAL_FDCAN_Init().

FunctionalState FDCAN_InitTypeDef::TransmitPause

Enable or disable the Transmit Pause feature. This parameter can be set to ENABLE or DISABLE

Definition at line 87 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::TxBuffersNbr

Specifies the number of Dedicated Tx Buffers. This parameter must be a number between 0 and 32

Definition at line 153 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::TxElmtSize

Specifies the Data Field Size in a Tx Element. This parameter can be a value of FDCAN Data Field Size

Definition at line 162 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), FDCAN_CopyMessageToRAM(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::TxEventsNbr

Specifies the number of Tx Event FIFO elements. This parameter must be a number between 0 and 32

Definition at line 150 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_GetTxEvent(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::TxFifoQueueElmtsNbr

Specifies the number of Tx Buffers used for Tx FIFO/Queue. This parameter must be a number between 0 and 32

Definition at line 156 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::TxFifoQueueMode

Tx FIFO/Queue Mode selection. This parameter can be a value of FDCAN Tx FIFO/Queue Mode

Definition at line 159 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN_ClkCalUnitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_ClkCalUnitTypeDef Struct Reference
FDCAN Exported Types

FDCAN clock calibration unit structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | ClockCalibration
uint32_t | ClockDivider
uint32_t | MinOscClkPeriods
uint32_t | CalFieldLength
uint32_t | TimeQuantaPerBitTime
uint32_t | WatchdogStartValue

Detailed Description

FDCAN clock calibration unit structure definition.

Definition at line 170 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_ClkCalUnitTypeDef::CalFieldLength

Specifies the calibration field length. This parameter can be a value of FDCAN Calibration Field Length

Definition at line 183 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration().

uint32_t FDCAN_ClkCalUnitTypeDef::ClockCalibration

Enable or disable the clock calibration. This parameter can be set to ENABLE or DISABLE

Definition at line 172 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration().

uint32_t FDCAN_ClkCalUnitTypeDef::ClockDivider

Specifies the FDCAN kernel clock divider when the clock calibration is bypassed. This parameter can be a value of FDCAN Clock Divider

Definition at line 175 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration().

uint32_t FDCAN_ClkCalUnitTypeDef::MinOscClkPeriods

Configures the minimum number of periods in two CAN bit times. The actual configured number of periods is MinOscClkPeriods x 32. This parameter must be a number between 0x00 and 0xFF

Definition at line 179 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration().

uint32_t FDCAN_ClkCalUnitTypeDef::TimeQuantaPerBitTime

Configures the number of time quanta per bit time. This parameter must be a number between 4 and 25

Definition at line 186 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration().

uint32_t FDCAN_ClkCalUnitTypeDef::WatchdogStartValue

Start value of the Calibration Watchdog Counter. If set to zero the counter is disabled. This parameter must be a number between 0x0000 and 0xFFFF

Definition at line 189 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN_FilterTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_FilterTypeDef Struct Reference
FDCAN Exported Types

FDCAN filter structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | IdType
uint32_t | FilterIndex
uint32_t | FilterType
uint32_t | FilterConfig
uint32_t | FilterID1
uint32_t | FilterID2
uint32_t | RxBufferIndex
uint32_t | IsCalibrationMsg

Detailed Description

FDCAN filter structure definition.

Definition at line 198 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_FilterTypeDef::FilterConfig

Specifies the filter configuration. This parameter can be a value of FDCAN Filter Configuration

Definition at line 215 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::FilterID1

Specifies the filter identification 1. This parameter must be a number between:

  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID

Definition at line 218 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::FilterID2

Specifies the filter identification 2. This parameter is ignored if FilterConfig is set to FDCAN_FILTER_TO_RXBUFFER. This parameter must be a number between:

  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID

Definition at line 223 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::FilterIndex

Specifies the filter which will be initialized. This parameter must be a number between:

  • 0 and 127, if IdType is FDCAN_STANDARD_ID
  • 0 and 63, if IdType is FDCAN_EXTENDED_ID

Definition at line 203 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::FilterType

Specifies the filter type. This parameter can be a value of FDCAN Filter Type. The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted only when IdType is FDCAN_EXTENDED_ID. This parameter is ignored if FilterConfig is set to FDCAN_FILTER_TO_RXBUFFER

Definition at line 208 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::IdType

Specifies the identifier type. This parameter can be a value of FDCAN ID Type

Definition at line 200 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::IsCalibrationMsg

Specifies whether the filter is configured for calibration messages. This parameter is ignored if FilterConfig is different from FDCAN_FILTER_TO_RXBUFFER. This parameter can be:

  • 0 : ordinary message
  • 1 : calibration message

Definition at line 236 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::RxBufferIndex

Contains the index of the Rx buffer in which the matching message will be stored. This parameter must be a number between 0 and 63. This parameter is ignored if FilterConfig is different from FDCAN_FILTER_TO_RXBUFFER

Definition at line 230 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN_TxHeaderTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_TxHeaderTypeDef Struct Reference
FDCAN Exported Types

FDCAN Tx header structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | Identifier
uint32_t | IdType
uint32_t | TxFrameType
uint32_t | DataLength
uint32_t | ErrorStateIndicator
uint32_t | BitRateSwitch
uint32_t | FDFormat
uint32_t | TxEventFifoControl
uint32_t | MessageMarker

Detailed Description

FDCAN Tx header structure definition.

Definition at line 249 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_TxHeaderTypeDef::BitRateSwitch

Specifies whether the Tx frame will be transmitted with or without bit rate switching. This parameter can be a value of FDCAN Bit Rate Switching

Definition at line 269 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::DataLength

Specifies the length of the frame that will be transmitted. This parameter can be a value of FDCAN Data Length Code

Definition at line 263 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::ErrorStateIndicator

Specifies the error state indicator. This parameter can be a value of FDCAN Error State Indicator

Definition at line 266 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::FDFormat

Specifies whether the Tx frame will be transmitted in classic or FD format. This parameter can be a value of FDCAN format

Definition at line 273 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::Identifier

Specifies the identifier. This parameter must be a number between:

  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID

Definition at line 251 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::IdType

Specifies the identifier type for the message that will be transmitted. This parameter can be a value of FDCAN ID Type

Definition at line 256 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::MessageMarker

Specifies the message marker to be copied into Tx Event FIFO element for identification of Tx message status. This parameter must be a number between 0 and 0xFF

Definition at line 280 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::TxEventFifoControl

Specifies the event FIFO control. This parameter can be a value of FDCAN Event FIFO control

Definition at line 277 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::TxFrameType

Specifies the frame type of the message that will be transmitted. This parameter can be a value of FDCAN Frame Type

Definition at line 260 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN_RxHeaderTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_RxHeaderTypeDef Struct Reference
FDCAN Exported Types

FDCAN Rx header structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | Identifier
uint32_t | IdType
uint32_t | RxFrameType
uint32_t | DataLength
uint32_t | ErrorStateIndicator
uint32_t | BitRateSwitch
uint32_t | FDFormat
uint32_t | RxTimestamp
uint32_t | FilterIndex
uint32_t | IsFilterMatchingFrame

Detailed Description

FDCAN Rx header structure definition.

Definition at line 289 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_RxHeaderTypeDef::BitRateSwitch

Specifies whether the Rx frame is received with or without bit rate switching. This parameter can be a value of FDCAN Bit Rate Switching

Definition at line 308 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::DataLength

Specifies the received frame length. This parameter can be a value of FDCAN Data Length Code

Definition at line 302 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::ErrorStateIndicator

Specifies the error state indicator. This parameter can be a value of FDCAN Error State Indicator

Definition at line 305 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::FDFormat

Specifies whether the Rx frame is received in classic or FD format. This parameter can be a value of FDCAN format

Definition at line 312 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::FilterIndex

Specifies the index of matching Rx acceptance filter element. This parameter must be a number between:

  • 0 and 127, if IdType is FDCAN_STANDARD_ID
  • 0 and 63, if IdType is FDCAN_EXTENDED_ID

Definition at line 320 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::Identifier

Specifies the identifier. This parameter must be a number between:

  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID

Definition at line 291 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::IdType

Specifies the identifier type of the received message. This parameter can be a value of FDCAN ID Type

Definition at line 296 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::IsFilterMatchingFrame

Specifies whether the accepted frame did not match any Rx filter. Acceptance of non-matching frames may be enabled via HAL_FDCAN_ConfigGlobalFilter(). This parameter can be 0 or 1

Definition at line 325 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::RxFrameType

Specifies the the received message frame type. This parameter can be a value of FDCAN Frame Type

Definition at line 299 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::RxTimestamp

Specifies the timestamp counter value captured on start of frame reception. This parameter must be a number between 0 and 0xFFFF

Definition at line 316 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN_TxEventFifoTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_TxEventFifoTypeDef Struct Reference
FDCAN Exported Types

FDCAN Tx event FIFO structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | Identifier
uint32_t | IdType
uint32_t | TxFrameType
uint32_t | DataLength
uint32_t | ErrorStateIndicator
uint32_t | BitRateSwitch
uint32_t | FDFormat
uint32_t | TxTimestamp
uint32_t | MessageMarker
uint32_t | EventType

Detailed Description

FDCAN Tx event FIFO structure definition.

Definition at line 335 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_TxEventFifoTypeDef::BitRateSwitch

Specifies whether the Tx frame is transmitted with or without bit rate switching. This parameter can be a value of FDCAN Bit Rate Switching

Definition at line 354 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::DataLength

Specifies the length of the transmitted frame. This parameter can be a value of FDCAN Data Length Code

Definition at line 348 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::ErrorStateIndicator

Specifies the error state indicator. This parameter can be a value of FDCAN Error State Indicator

Definition at line 351 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::EventType

Specifies the event type. This parameter can be a value of FDCAN Event Type

Definition at line 370 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::FDFormat

Specifies whether the Tx frame is transmitted in classic or FD format. This parameter can be a value of FDCAN format

Definition at line 358 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::Identifier

Specifies the identifier. This parameter must be a number between:

  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID

Definition at line 337 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::IdType

Specifies the identifier type for the transmitted message. This parameter can be a value of FDCAN ID Type

Definition at line 342 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::MessageMarker

Specifies the message marker copied into Tx Event FIFO element for identification of Tx message status. This parameter must be a number between 0 and 0xFF

Definition at line 366 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::TxFrameType

Specifies the frame type of the transmitted message. This parameter can be a value of FDCAN Frame Type

Definition at line 345 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::TxTimestamp

Specifies the timestamp counter value captured on start of frame transmission. This parameter must be a number between 0 and 0xFFFF

Definition at line 362 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN_HpMsgStatusTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_HpMsgStatusTypeDef Struct Reference
FDCAN Exported Types

FDCAN High Priority Message Status structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | FilterList
uint32_t | FilterIndex
uint32_t | MessageStorage
uint32_t | MessageIndex

Detailed Description

FDCAN High Priority Message Status structure definition.

Definition at line 378 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_HpMsgStatusTypeDef::FilterIndex

Specifies the index of matching filter element. This parameter can be a number between:

  • 0 and 127, if FilterList is 0 (Standard)
  • 0 and 63, if FilterList is 1 (Extended)

Definition at line 385 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetHighPriorityMessageStatus().

uint32_t FDCAN_HpMsgStatusTypeDef::FilterList

Specifies the filter list of the matching filter element. This parameter can be:

  • 0 : Standard Filter List
  • 1 : Extended Filter List

Definition at line 380 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetHighPriorityMessageStatus().

uint32_t FDCAN_HpMsgStatusTypeDef::MessageIndex

Specifies the Index of Rx FIFO element to which the message was stored. This parameter is valid only when MessageStorage is: FDCAN_HP_STORAGE_RXFIFO0 or FDCAN_HP_STORAGE_RXFIFO1

Definition at line 393 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetHighPriorityMessageStatus().

uint32_t FDCAN_HpMsgStatusTypeDef::MessageStorage

Specifies the HP Message Storage. This parameter can be a value of FDCAN High Priority Message Storage

Definition at line 390 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetHighPriorityMessageStatus().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN_ProtocolStatusTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_ProtocolStatusTypeDef Struct Reference
FDCAN Exported Types

FDCAN Protocol Status structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | LastErrorCode
uint32_t | DataLastErrorCode
uint32_t | Activity
uint32_t | ErrorPassive
uint32_t | Warning
uint32_t | BusOff
uint32_t | RxESIflag
uint32_t | RxBRSflag
uint32_t | RxFDFflag
uint32_t | ProtocolException
uint32_t | TDCvalue

Detailed Description

FDCAN Protocol Status structure definition.

Definition at line 405 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_ProtocolStatusTypeDef::Activity

Specifies the FDCAN module communication state. This parameter can be a value of FDCAN communication state

Definition at line 414 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::BusOff

Specifies the FDCAN module Bus_Off status. This parameter can be:

  • 0 : The FDCAN is not in Bus_Off state
  • 1 : The FDCAN is in Bus_Off state

Definition at line 427 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::DataLastErrorCode

Specifies the type of the last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. This parameter can be a value of FDCAN protocol error code

Definition at line 410 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::ErrorPassive

Specifies the FDCAN module error status. This parameter can be:

  • 0 : The FDCAN is in Error_Active state
  • 1 : The FDCAN is in Error_Passive state

Definition at line 417 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::LastErrorCode

Specifies the type of the last error that occurred on the FDCAN bus. This parameter can be a value of FDCAN protocol error code

Definition at line 407 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::ProtocolException

Specifies the FDCAN module Protocol Exception status. This parameter can be:

  • 0 : No protocol exception event occurred since last read access
  • 1 : Protocol exception event occurred

Definition at line 447 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::RxBRSflag

Specifies BRS flag of last received CAN FD message. This parameter can be:

  • 0 : Last received CAN FD message did not have its BRS flag set
  • 1 : Last received CAN FD message had its BRS flag set

Definition at line 437 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::RxESIflag

Specifies ESI flag of last received CAN FD message. This parameter can be:

  • 0 : Last received CAN FD message did not have its ESI flag set
  • 1 : Last received CAN FD message had its ESI flag set

Definition at line 432 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::RxFDFflag

Specifies FDF flag of last received CAN FD message. This parameter can be:

  • 0 : Last received CAN FD message did not have its FDF flag set
  • 1 : Last received CAN FD message had its FDF flag set

Definition at line 442 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::TDCvalue

Specifies the Transmitter Delay Compensation Value. This parameter can be a number between 0 and 127

Definition at line 452 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::Warning

Specifies the FDCAN module warning status. This parameter can be:

  • 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96
  • 1 : at least one of error counters has reached the Error_Warning limit of 96

Definition at line 422 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN_ErrorCountersTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_ErrorCountersTypeDef Struct Reference
FDCAN Exported Types

FDCAN Error Counters structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | TxErrorCnt
uint32_t | RxErrorCnt
uint32_t | RxErrorPassive
uint32_t | ErrorLogging

Detailed Description

FDCAN Error Counters structure definition.

Definition at line 460 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_ErrorCountersTypeDef::ErrorLogging

Specifies the Transmit/Receive error logging counter value. This parameter can be a number between 0 and 127. This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt or the RxErrorCnt to be incremented. The counter stops at 127; the next increment of TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW

Definition at line 473 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetErrorCounters().

uint32_t FDCAN_ErrorCountersTypeDef::RxErrorCnt

Specifies the Receive Error Counter Value. This parameter can be a number between 0 and 127

Definition at line 465 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetErrorCounters().

uint32_t FDCAN_ErrorCountersTypeDef::RxErrorPassive

Specifies the Receive Error Passive status. This parameter can be:

  • 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
  • 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128

Definition at line 468 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetErrorCounters().

uint32_t FDCAN_ErrorCountersTypeDef::TxErrorCnt

Specifies the Transmit Error Counter Value. This parameter can be a number between 0 and 255

Definition at line 462 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetErrorCounters().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN_TT_ConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_TT_ConfigTypeDef Struct Reference
FDCAN Exported Types

FDCAN TT Init structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | OperationMode
uint32_t | GapEnable
uint32_t | TimeMaster
uint32_t | SyncDevLimit
uint32_t | InitRefTrigOffset
uint32_t | ExternalClkSync
uint32_t | AppWdgLimit
uint32_t | GlobalTimeFilter
uint32_t | ClockCalibration
uint32_t | EvtTrigPolarity
uint32_t | BasicCyclesNbr
uint32_t | CycleStartSync
uint32_t | TxEnableWindow
uint32_t | ExpTxTrigNbr
uint32_t | TURNumerator
uint32_t | TURDenominator
uint32_t | TriggerMemoryNbr
uint32_t | StopWatchTrigSel
uint32_t | EventTrigSel

Detailed Description

FDCAN TT Init structure definition.

Definition at line 484 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_TT_ConfigTypeDef::AppWdgLimit

Specifies the Application Watchdog Limit : maximum time after which the application has to serve the application watchdog. The application watchdog is incremented once each 256 NTUs. The application watchdog can be disabled by setting AppWdgLimit to 0. This parameter must be a number between 0 and 255. This parameter is ignored if OperationMode is set to FDCAN_TT_COMMUNICATION_LEVEL0

Definition at line 510 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::BasicCyclesNbr

Specifies the nubmer of basic cycles in the system matrix. This parameter can be a value of FDCAN TT Basic Cycle Number

Definition at line 533 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::ClockCalibration

Enable or disable Automatic Clock Calibration. This parameter can be a value of FDCAN TT Automatic Clock Calibration. This parameter is ignored if OperationMode is set to FDCAN_TT_COMMUNICATION_LEVEL1

Definition at line 523 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::CycleStartSync

Enable or disable synchronization pulse output at pin fdcan1_soc. This parameter can be a value of FDCAN TT Cycle Start Sync

Definition at line 536 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::EventTrigSel

Specifies the input to be used as event trigger. This parameter can be a value of FDCAN TT Event Trigger Selection

Definition at line 560 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::EvtTrigPolarity

Specifies the Event Trigger Polarity. This parameter can be a value of FDCAN TT Event Trigger Polarity. This parameter is ignored if OperationMode is set to FDCAN_TT_COMMUNICATION_LEVEL0

Definition at line 528 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::ExpTxTrigNbr

Specifies the number of expected Tx_Triggers in the system matrix. This is the sum of Tx_Triggers for exclusive, single arbitrating and merged arbitrating windows. This parameter must be a number between 0 and 4095

Definition at line 542 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::ExternalClkSync

Enable or disable External Clock Synchronization. This parameter can be a value of FDCAN TT External Clock Synchronization. This parameter is ignored if OperationMode is set to FDCAN_TT_COMMUNICATION_LEVEL1

Definition at line 505 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::GapEnable

Specifies the FDCAN TT Operation. This parameter can be a value of FDCAN TT Operation. This parameter is ignored if OperationMode is set to FDCAN_TT_COMMUNICATION_LEVEL0

Definition at line 489 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::GlobalTimeFilter

Enable or disable Global Time Filtering. This parameter can be a value of FDCAN TT Global Time Filtering. This parameter is ignored if OperationMode is set to FDCAN_TT_COMMUNICATION_LEVEL1

Definition at line 518 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::InitRefTrigOffset

Specifies the Initial Reference Trigger Offset. This parameter must be a number between 0 and 127

Definition at line 502 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::OperationMode

Specifies the FDCAN Operation Mode. This parameter can be a value of FDCAN Operation Mode

Definition at line 486 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::StopWatchTrigSel

Specifies the input to be used as stop watch trigger. This parameter can be a value of FDCAN TT Stop Watch Trigger Selection

Definition at line 557 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::SyncDevLimit

Specifies the Synchronization Deviation Limit SDL of the TUR numerator : TUR = (Numerator ± SDL) / Denominator. With : SDL = 2^(SyncDevLimit+5). This parameter must be a number between 0 and 7

Definition at line 497 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::TimeMaster

Specifies whether the instance is a slave or a potential master. This parameter can be a value of FDCAN TT Time Master

Definition at line 494 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::TriggerMemoryNbr

Specifies the number of trigger memory elements. This parameter must be a number between 0 and 64

Definition at line 554 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::TURDenominator

Specifies the TUR (Time Unit Ratio) denominator. This parameter must be a number between 0x0001 and 0x3FFF

Definition at line 551 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::TURNumerator

Specifies the TUR (Time Unit Ratio) numerator. It is adviced to set this parameter to the largest applicable value. This parameter must be a number between 0x10000 and 0x1FFFF

Definition at line 547 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_TT_ConfigTypeDef::TxEnableWindow

Specifies the length of Tx enable window in NTUs. This parameter must be a number between 1 and 16

Definition at line 539 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN_TriggerTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_TriggerTypeDef Struct Reference
FDCAN Exported Types

FDCAN Trigger structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | TriggerIndex
uint32_t | TimeMark
uint32_t | RepeatFactor
uint32_t | StartCycle
uint32_t | TmEventInt
uint32_t | TmEventExt
uint32_t | TriggerType
uint32_t | FilterType
uint32_t | TxBufferIndex
uint32_t | FilterIndex

Detailed Description

FDCAN Trigger structure definition.

Definition at line 568 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_TriggerTypeDef::FilterIndex

Specifies the filter for which the trigger is valid. This parameter is taken in consideration only if the trigger is configured for reception. This parameter must be a number between:

  • 0 and 127, if FilterType is FDCAN_STANDARD_ID
  • 0 and 63, if FilterType is FDCAN_EXTENDED_ID

Definition at line 604 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

uint32_t FDCAN_TriggerTypeDef::FilterType

Specifies the filter identifier type. This parameter can be a value of FDCAN ID Type

Definition at line 596 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

uint32_t FDCAN_TriggerTypeDef::RepeatFactor

Specifies the trigger repeat factor. This parameter can be a value of FDCAN TT repeat factor

Definition at line 576 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

uint32_t FDCAN_TriggerTypeDef::StartCycle

Specifies the index of the first cycle in which the trigger becomes active. This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE. This parameter must be a number between 0 and RepeatFactor

Definition at line 579 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

uint32_t FDCAN_TriggerTypeDef::TimeMark

Specifies the cycle time for which the trigger becomes active. This parameter must be a number between 0 and 0xFFFF

Definition at line 573 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

uint32_t FDCAN_TriggerTypeDef::TmEventExt

Enable or disable the external time mark event. If enabled, and if TTOCN.TTIE is set, a pulse is generated at fdcan1_tmp when trigger memory element becomes active. This parameter can be a value of FDCAN TT time mark event external

Definition at line 588 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

uint32_t FDCAN_TriggerTypeDef::TmEventInt

Enable or disable the internal time mark event. If enabled, FDCAN_TT_FLAG_TRIG_TIME_MARK flag is set when trigger memory element becomes active. This parameter can be a value of FDCAN TT time mark event internal

Definition at line 583 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

uint32_t FDCAN_TriggerTypeDef::TriggerIndex

Specifies the trigger which will be configured. This parameter must be a number between 0 and 63

Definition at line 570 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

uint32_t FDCAN_TriggerTypeDef::TriggerType

Specifies the trigger type. This parameter can be a value of FDCAN TT trigger type

Definition at line 593 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

uint32_t FDCAN_TriggerTypeDef::TxBufferIndex

Specifies the index of the Tx buffer for which the trigger is valid. This parameter can be a value of FDCAN Tx Location. This parameter is taken in consideration only if the trigger is configured for transmission.

Definition at line 599 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN_TTOperationStatusTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_TTOperationStatusTypeDef Struct Reference
FDCAN Exported Types

FDCAN TT Operation Status structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | ErrorLevel
uint32_t | MasterState
uint32_t | SyncState
uint32_t | GTimeQuality
uint32_t | ClockQuality
uint32_t | RefTrigOffset
uint32_t | GTimeDiscPending
uint32_t | GapFinished
uint32_t | MasterPriority
uint32_t | GapStarted
uint32_t | WaitForEvt
uint32_t | AppWdgEvt
uint32_t | ECSPending
uint32_t | PhaseLock

Detailed Description

FDCAN TT Operation Status structure definition.

Definition at line 616 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_TTOperationStatusTypeDef::AppWdgEvt

Specifies the Application Watchdog State. This parameter can be:

  • 0 : Application Watchdog served in time
  • 1 : Failed to serve Application Watchdog in time

Definition at line 665 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::ClockQuality

Specifies the Quality of Clock Speed. This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1. This parameter can be:

  • 0 : Local clock speed not synchronized to Time Master clock speed
  • 1 : Synchronization Deviation ≤ SDL

Definition at line 633 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::ECSPending

Specifies the External Clock Synchronization State. This parameter can be:

  • 0 : No external clock synchronization pending
  • 1 : Node waits for external clock synchronization to take effect

Definition at line 670 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::ErrorLevel

Specifies the type of the TT operation error level. This parameter can be a value of FDCAN TT Error Level

Definition at line 618 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::GapFinished

Specifies whether a Gap is finished. This parameter can be:

  • 0 : Reset at the end of each reference message
  • 1 : Gap finished

Definition at line 647 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::GapStarted

Specifies whether a Gap is started. This parameter can be:

  • 0 : No Gap in schedule
  • 1 : Gap time after Basic Cycle has started

Definition at line 655 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::GTimeDiscPending

Specifies the Global Time Discontinuity State. This parameter can be:

  • 0 : No global time preset pending
  • 1 : Node waits for the global time preset to take effect

Definition at line 642 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::GTimeQuality

Specifies the Quality of Global Time Phase. This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0. This parameter can be:

  • 0 : Global time not valid
  • 1 : Global time in phase with Time Master

Definition at line 627 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::MasterPriority

Specifies the Priority of actual Time Master. This parameter can be a number between 0 and 0x7

Definition at line 652 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::MasterState

Specifies the type of the TT master state. This parameter can be a value of FDCAN TT Master State

Definition at line 621 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::PhaseLock

Specifies the Phase Lock State. This parameter can be:

  • 0 : Phase outside range
  • 1 : Phase inside range

Definition at line 675 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::RefTrigOffset

Specifies the Actual Reference Trigger Offset Value. This parameter can be a number between 0 and 0xFF

Definition at line 639 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::SyncState

Specifies the type of the TT synchronization state. This parameter can be a value of FDCAN TT Synchronization State

Definition at line 624 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

uint32_t FDCAN_TTOperationStatusTypeDef::WaitForEvt

Specifies whether a Gap is annouced. This parameter can be:

  • 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0
  • 1 : Reference message with Next_is_Gap = 1 received

Definition at line 660 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_GetOperationStatus().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN_MsgRamAddressTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_MsgRamAddressTypeDef Struct Reference
FDCAN Exported Types

FDCAN Message RAM blocks. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

uint32_t | StandardFilterSA
uint32_t | ExtendedFilterSA
uint32_t | RxFIFO0SA
uint32_t | RxFIFO1SA
uint32_t | RxBufferSA
uint32_t | TxEventFIFOSA
uint32_t | TxBufferSA
uint32_t | TxFIFOQSA
uint32_t | TTMemorySA
uint32_t | EndAddress

Detailed Description

FDCAN Message RAM blocks.

Definition at line 685 of file stm32h7xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_MsgRamAddressTypeDef::EndAddress

Specifies the End Address of the allocated RAM. This parameter must be a 32-bit word address

Definition at line 714 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_TT_ConfigOperation().

uint32_t FDCAN_MsgRamAddressTypeDef::ExtendedFilterSA

Specifies the Extended Filter List Start Address. This parameter must be a 32-bit word address

Definition at line 690 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_MsgRamAddressTypeDef::RxBufferSA

Specifies the Rx Buffer Start Address. This parameter must be a 32-bit word address

Definition at line 699 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_MsgRamAddressTypeDef::RxFIFO0SA

Specifies the Rx FIFO 0 Start Address. This parameter must be a 32-bit word address

Definition at line 693 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_MsgRamAddressTypeDef::RxFIFO1SA

Specifies the Rx FIFO 1 Start Address. This parameter must be a 32-bit word address

Definition at line 696 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_MsgRamAddressTypeDef::StandardFilterSA

Specifies the Standard Filter List Start Address. This parameter must be a 32-bit word address

Definition at line 687 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_MsgRamAddressTypeDef::TTMemorySA

Specifies the Trigger Memory Start Address. This parameter must be a 32-bit word address

Definition at line 711 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation(), and HAL_FDCAN_TT_ConfigTrigger().

uint32_t FDCAN_MsgRamAddressTypeDef::TxBufferSA

Specifies the Tx Buffers Start Address. This parameter must be a 32-bit word address

Definition at line 705 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and FDCAN_CopyMessageToRAM().

uint32_t FDCAN_MsgRamAddressTypeDef::TxEventFIFOSA

Specifies the Tx Event FIFO Start Address. This parameter must be a 32-bit word address

Definition at line 702 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_MsgRamAddressTypeDef::TxFIFOQSA

Specifies the Tx FIFO/Queue Start Address. This parameter must be a 32-bit word address

Definition at line 708 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_HandleTypeDef Struct Reference
FDCAN Exported Types

FDCAN handle structure definition. More...

#include <stm32h7xx_hal_fdcan.h>

Data Fields

FDCAN_GlobalTypeDef * | Instance
TTCAN_TypeDef * | ttcan
FDCAN_InitTypeDef Init
FDCAN_MsgRamAddressTypeDef msgRam
__IO HAL_FDCAN_StateTypeDef | State
HAL_LockTypeDef | Lock
__IO uint32_t | ErrorCode

Detailed Description

FDCAN handle structure definition.

Definition at line 722 of file stm32h7xx_hal_fdcan.h.

Field Documentation

__IO uint32_t FDCAN_HandleTypeDef::ErrorCode

FDCAN Error code

Definition at line 736 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_AbortTxRequest(), HAL_FDCAN_ActivateNotification(), HAL_FDCAN_AddMessageToTxBuffer(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigClockCalibration(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigFifoWatermark(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_ConfigGlobalFilter(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTimestampCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_DeactivateNotification(), HAL_FDCAN_DeInit(), HAL_FDCAN_DisableTimeoutCounter(), HAL_FDCAN_DisableTimestampCounter(), HAL_FDCAN_DisableTxDelayCompensation(), HAL_FDCAN_EnableTimeoutCounter(), HAL_FDCAN_EnableTimestampCounter(), HAL_FDCAN_EnableTxBufferRequest(), HAL_FDCAN_EnableTxDelayCompensation(), HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_ExitRestrictedOperationMode(), HAL_FDCAN_GetError(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetTxEvent(), HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_ResetTimeoutCounter(), HAL_FDCAN_ResetTimestampCounter(), HAL_FDCAN_Start(), HAL_FDCAN_Stop(), HAL_FDCAN_TT_ActivateNotification(), HAL_FDCAN_TT_ConfigExternalSyncPhase(), HAL_FDCAN_TT_ConfigInterruptLines(), HAL_FDCAN_TT_ConfigOperation(), HAL_FDCAN_TT_ConfigReferenceMessage(), HAL_FDCAN_TT_ConfigRegisterTimeMark(), HAL_FDCAN_TT_ConfigStopWatch(), HAL_FDCAN_TT_ConfigTrigger(), HAL_FDCAN_TT_DeactivateNotification(), HAL_FDCAN_TT_DisableExternalSynchronization(), HAL_FDCAN_TT_DisableHardwareGapControl(), HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(), HAL_FDCAN_TT_DisableTimeMarkGapControl(), HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(), HAL_FDCAN_TT_EnableExternalSynchronization(), HAL_FDCAN_TT_EnableHardwareGapControl(), HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(), HAL_FDCAN_TT_EnableTimeMarkGapControl(), HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(), HAL_FDCAN_TT_SetClockSynchronization(), HAL_FDCAN_TT_SetEndOfGap(), HAL_FDCAN_TT_SetGlobalTime(), and HAL_FDCAN_TT_SetNextIsGap().

FDCAN_InitTypeDef FDCAN_HandleTypeDef::Init

FDCAN required parameters

Definition at line 728 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), FDCAN_CopyMessageToRAM(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetTxEvent(), and HAL_FDCAN_Init().

FDCAN_GlobalTypeDef* FDCAN_HandleTypeDef::Instance

Register base address

Definition at line 724 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_AbortTxRequest(), HAL_FDCAN_ActivateNotification(), HAL_FDCAN_AddMessageToTxBuffer(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigClockCalibration(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigFifoWatermark(), HAL_FDCAN_ConfigGlobalFilter(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTimestampCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_DeInit(), HAL_FDCAN_DisableTimeoutCounter(), HAL_FDCAN_DisableTimestampCounter(), HAL_FDCAN_DisableTxDelayCompensation(), HAL_FDCAN_EnableTimeoutCounter(), HAL_FDCAN_EnableTimestampCounter(), HAL_FDCAN_EnableTxBufferRequest(), HAL_FDCAN_EnableTxDelayCompensation(), HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_ExitRestrictedOperationMode(), HAL_FDCAN_GetErrorCounters(), HAL_FDCAN_GetHighPriorityMessageStatus(), HAL_FDCAN_GetProtocolStatus(), HAL_FDCAN_GetRxFifoFillLevel(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetTimeoutCounter(), HAL_FDCAN_GetTimestampCounter(), HAL_FDCAN_GetTxEvent(), HAL_FDCAN_GetTxFifoFreeLevel(), HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_IsRestrictedOperationMode(), HAL_FDCAN_IsRxBufferMessageAvailable(), HAL_FDCAN_IsTxBufferMessagePending(), HAL_FDCAN_ResetTimeoutCounter(), HAL_FDCAN_ResetTimestampCounter(), HAL_FDCAN_Start(), HAL_FDCAN_Stop(), HAL_FDCAN_TT_ActivateNotification(), HAL_FDCAN_TT_ConfigExternalSyncPhase(), HAL_FDCAN_TT_ConfigInterruptLines(), HAL_FDCAN_TT_ConfigOperation(), HAL_FDCAN_TT_ConfigReferenceMessage(), HAL_FDCAN_TT_ConfigRegisterTimeMark(), HAL_FDCAN_TT_ConfigStopWatch(), HAL_FDCAN_TT_ConfigTrigger(), HAL_FDCAN_TT_DisableExternalSynchronization(), HAL_FDCAN_TT_DisableHardwareGapControl(), HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(), HAL_FDCAN_TT_DisableTimeMarkGapControl(), HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(), HAL_FDCAN_TT_EnableExternalSynchronization(), HAL_FDCAN_TT_EnableHardwareGapControl(), HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(), HAL_FDCAN_TT_EnableTimeMarkGapControl(), HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(), HAL_FDCAN_TT_GetOperationStatus(), HAL_FDCAN_TT_SetClockSynchronization(), HAL_FDCAN_TT_SetEndOfGap(), HAL_FDCAN_TT_SetGlobalTime(), and HAL_FDCAN_TT_SetNextIsGap().

HAL_LockTypeDef FDCAN_HandleTypeDef::Lock

FDCAN locking object

Definition at line 734 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

FDCAN_MsgRamAddressTypeDef FDCAN_HandleTypeDef::msgRam

FDCAN Message RAM blocks

Definition at line 730 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), FDCAN_CopyMessageToRAM(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetTxEvent(), HAL_FDCAN_TT_ConfigOperation(), and HAL_FDCAN_TT_ConfigTrigger().

__IO HAL_FDCAN_StateTypeDef FDCAN_HandleTypeDef::State

FDCAN communication state

Definition at line 732 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AbortTxRequest(), HAL_FDCAN_ActivateNotification(), HAL_FDCAN_AddMessageToTxBuffer(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigClockCalibration(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigFifoWatermark(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_ConfigGlobalFilter(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTimestampCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_DeactivateNotification(), HAL_FDCAN_DeInit(), HAL_FDCAN_DisableTimeoutCounter(), HAL_FDCAN_DisableTimestampCounter(), HAL_FDCAN_DisableTxDelayCompensation(), HAL_FDCAN_EnableTimeoutCounter(), HAL_FDCAN_EnableTimestampCounter(), HAL_FDCAN_EnableTxBufferRequest(), HAL_FDCAN_EnableTxDelayCompensation(), HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_ExitRestrictedOperationMode(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetState(), HAL_FDCAN_GetTxEvent(), HAL_FDCAN_Init(), HAL_FDCAN_Start(), HAL_FDCAN_Stop(), HAL_FDCAN_TT_ActivateNotification(), HAL_FDCAN_TT_ConfigExternalSyncPhase(), HAL_FDCAN_TT_ConfigInterruptLines(), HAL_FDCAN_TT_ConfigOperation(), HAL_FDCAN_TT_ConfigReferenceMessage(), HAL_FDCAN_TT_ConfigRegisterTimeMark(), HAL_FDCAN_TT_ConfigStopWatch(), HAL_FDCAN_TT_ConfigTrigger(), HAL_FDCAN_TT_DeactivateNotification(), HAL_FDCAN_TT_DisableExternalSynchronization(), HAL_FDCAN_TT_DisableHardwareGapControl(), HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(), HAL_FDCAN_TT_DisableTimeMarkGapControl(), HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(), HAL_FDCAN_TT_EnableExternalSynchronization(), HAL_FDCAN_TT_EnableHardwareGapControl(), HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(), HAL_FDCAN_TT_EnableTimeMarkGapControl(), HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(), HAL_FDCAN_TT_SetClockSynchronization(), HAL_FDCAN_TT_SetEndOfGap(), HAL_FDCAN_TT_SetGlobalTime(), and HAL_FDCAN_TT_SetNextIsGap().

TTCAN_TypeDef* FDCAN_HandleTypeDef::ttcan

TT register base address

Definition at line 726 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_TT_ActivateNotification(), HAL_FDCAN_TT_ConfigExternalSyncPhase(), HAL_FDCAN_TT_ConfigInterruptLines(), HAL_FDCAN_TT_ConfigOperation(), HAL_FDCAN_TT_ConfigReferenceMessage(), HAL_FDCAN_TT_ConfigRegisterTimeMark(), HAL_FDCAN_TT_ConfigStopWatch(), HAL_FDCAN_TT_DisableExternalSynchronization(), HAL_FDCAN_TT_DisableHardwareGapControl(), HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(), HAL_FDCAN_TT_DisableTimeMarkGapControl(), HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(), HAL_FDCAN_TT_EnableExternalSynchronization(), HAL_FDCAN_TT_EnableHardwareGapControl(), HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(), HAL_FDCAN_TT_EnableTimeMarkGapControl(), HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(), HAL_FDCAN_TT_GetOperationStatus(), HAL_FDCAN_TT_SetClockSynchronization(), HAL_FDCAN_TT_SetEndOfGap(), HAL_FDCAN_TT_SetGlobalTime(), and HAL_FDCAN_TT_SetNextIsGap().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_fdcan.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HAL FDCAN Error Code

Defines
HAL FDCAN Error Code
FDCAN Exported Constants

Defines

#define | HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U)
#define | HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U)
#define | HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U)
#define | HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U)
#define | HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U)
#define | HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U)
#define | HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U)
#define | HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U)
#define | HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO
#define | HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI
#define | HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA
#define | HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED
#define | HAL_FDCAN_ERROR_RESEVED_AREA FDCAN_IR_ARA
#define | HAL_FDCAN_ERROR_TT_GLOBAL_TIME FDCAN_TTIR_GTE
#define | HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU
#define | HAL_FDCAN_ERROR_TT_TX_OVERFLOW FDCAN_TTIR_TXO
#define | HAL_FDCAN_ERROR_TT_SCHEDULE1 FDCAN_TTIR_SE1
#define | HAL_FDCAN_ERROR_TT_SCHEDULE2 FDCAN_TTIR_SE2
#define | HAL_FDCAN_ERROR_TT_NO_INIT_REF FDCAN_TTIR_IWT
#define | HAL_FDCAN_ERROR_TT_NO_REF FDCAN_TTIR_WT
#define | HAL_FDCAN_ERROR_TT_APPL_WDG FDCAN_TTIR_AW
#define | HAL_FDCAN_ERROR_TT_CONFIG FDCAN_TTIR_CER

Define Documentation

#define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO

Overflow of CAN Error Logging Counter

Definition at line 762 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 753 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_DeInit(), HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_Start().

#define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U)

Peripheral not initialized

Definition at line 755 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), HAL_FDCAN_AddMessageToTxBuffer(), HAL_FDCAN_ConfigClockCalibration(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_DeactivateNotification(), HAL_FDCAN_ExitRestrictedOperationMode(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetTxEvent(), HAL_FDCAN_TT_ActivateNotification(), HAL_FDCAN_TT_ConfigExternalSyncPhase(), HAL_FDCAN_TT_ConfigInterruptLines(), HAL_FDCAN_TT_ConfigRegisterTimeMark(), HAL_FDCAN_TT_ConfigStopWatch(), HAL_FDCAN_TT_DeactivateNotification(), HAL_FDCAN_TT_DisableExternalSynchronization(), HAL_FDCAN_TT_DisableHardwareGapControl(), HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(), HAL_FDCAN_TT_DisableTimeMarkGapControl(), HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(), HAL_FDCAN_TT_EnableExternalSynchronization(), HAL_FDCAN_TT_EnableHardwareGapControl(), HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(), HAL_FDCAN_TT_EnableTimeMarkGapControl(), HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(), HAL_FDCAN_TT_SetClockSynchronization(), HAL_FDCAN_TT_SetEndOfGap(), HAL_FDCAN_TT_SetGlobalTime(), and HAL_FDCAN_TT_SetNextIsGap().

#define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U)

Peripheral not ready

Definition at line 756 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigFifoWatermark(), HAL_FDCAN_ConfigGlobalFilter(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTimestampCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_DisableTimeoutCounter(), HAL_FDCAN_DisableTimestampCounter(), HAL_FDCAN_DisableTxDelayCompensation(), HAL_FDCAN_EnableTimeoutCounter(), HAL_FDCAN_EnableTimestampCounter(), HAL_FDCAN_EnableTxDelayCompensation(), HAL_FDCAN_Start(), HAL_FDCAN_TT_ConfigOperation(), HAL_FDCAN_TT_ConfigReferenceMessage(), and HAL_FDCAN_TT_ConfigTrigger().

#define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U)

Peripheral not started

Definition at line 757 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AbortTxRequest(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_EnableTxBufferRequest(), and HAL_FDCAN_Stop().

#define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U)

Mode not supported

Definition at line 758 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ResetTimeoutCounter(), HAL_FDCAN_ResetTimestampCounter(), HAL_FDCAN_TT_DisableHardwareGapControl(), HAL_FDCAN_TT_DisableTimeMarkGapControl(), HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(), HAL_FDCAN_TT_EnableHardwareGapControl(), HAL_FDCAN_TT_EnableTimeMarkGapControl(), HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(), HAL_FDCAN_TT_SetClockSynchronization(), HAL_FDCAN_TT_SetEndOfGap(), HAL_FDCAN_TT_SetGlobalTime(), and HAL_FDCAN_TT_SetNextIsGap().

#define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U)

Parameter error

Definition at line 759 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_AddMessageToTxBuffer(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetTxEvent(), and HAL_FDCAN_TT_ConfigOperation().

#define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U)

Pending operation

Definition at line 760 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), HAL_FDCAN_TT_ConfigExternalSyncPhase(), HAL_FDCAN_TT_SetClockSynchronization(), and HAL_FDCAN_TT_SetGlobalTime().

#define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA

Protocol Error in Arbitration Phase (Nominal Bit Time is used)

Definition at line 764 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED

Protocol Error in Data Phase (Data Bit Time is used)

Definition at line 765 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U)

Message RAM Access Failure

Definition at line 761 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI

Message RAM Watchdog event occurred

Definition at line 763 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_RESEVED_AREA FDCAN_IR_ARA

Access to Reserved Address

Definition at line 766 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U)

Timeout error

Definition at line 754 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_Init(), HAL_FDCAN_Stop(), HAL_FDCAN_TT_ConfigOperation(), HAL_FDCAN_TT_ConfigRegisterTimeMark(), HAL_FDCAN_TT_ConfigStopWatch(), HAL_FDCAN_TT_DisableExternalSynchronization(), HAL_FDCAN_TT_DisableHardwareGapControl(), HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(), HAL_FDCAN_TT_DisableTimeMarkGapControl(), HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(), HAL_FDCAN_TT_EnableExternalSynchronization(), HAL_FDCAN_TT_EnableHardwareGapControl(), HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(), HAL_FDCAN_TT_EnableTimeMarkGapControl(), HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(), HAL_FDCAN_TT_SetClockSynchronization(), HAL_FDCAN_TT_SetEndOfGap(), HAL_FDCAN_TT_SetGlobalTime(), and HAL_FDCAN_TT_SetNextIsGap().

#define HAL_FDCAN_ERROR_TT_APPL_WDG FDCAN_TTIR_AW

Application watchdog not served in time

Definition at line 774 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_TT_CONFIG FDCAN_TTIR_CER

Error found in trigger list

Definition at line 775 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_TT_GLOBAL_TIME FDCAN_TTIR_GTE

Global Time Error : Synchronization deviation exceeded limit

Definition at line 767 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_TT_NO_INIT_REF FDCAN_TTIR_IWT

No system startup due to missing reference message

Definition at line 772 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_TT_NO_REF FDCAN_TTIR_WT

Missing reference message

Definition at line 773 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_TT_SCHEDULE1 FDCAN_TTIR_SE1

Scheduling error 1

Definition at line 770 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_TT_SCHEDULE2 FDCAN_TTIR_SE2

Scheduling error 2

Definition at line 771 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_TT_TX_OVERFLOW FDCAN_TTIR_TXO

Tx Count Overflow : More Tx trigger than expected in one matrix cycle

Definition at line 769 of file stm32h7xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU

Tx Count Underflow : Less Tx trigger than expected in one matrix cycle

Definition at line 768 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Frame Format

Defines
FDCAN Frame Format
FDCAN Exported Constants

Defines

#define | FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U)
#define | FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)
#define | FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE))

Define Documentation

#define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U)

Classic mode

Definition at line 783 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE))

FD mode with BitRate Switshing

Definition at line 785 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)

FD mode without BitRate Switshing

Definition at line 784 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Operating Mode

Defines
FDCAN Operating Mode
FDCAN Exported Constants

Defines

#define | FDCAN_MODE_NORMAL ((uint32_t)0x00000000U)
#define | FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U)
#define | FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U)
#define | FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U)
#define | FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U)

Define Documentation

#define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U)

Bus Monitoring mode

Definition at line 795 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U)

External LoopBack mode

Definition at line 797 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U)

Internal LoopBack mode

Definition at line 796 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U)

Normal mode

Definition at line 793 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U)

Restricted Operation mode

Definition at line 794 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Clock Divider

Defines
FDCAN Clock Divider
FDCAN Exported Constants

Defines

#define | FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U)
#define | FDCAN_CLOCK_DIV2 ((uint32_t)0x00010000U)
#define | FDCAN_CLOCK_DIV4 ((uint32_t)0x00020000U)
#define | FDCAN_CLOCK_DIV6 ((uint32_t)0x00030000U)
#define | FDCAN_CLOCK_DIV8 ((uint32_t)0x00040000U)
#define | FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U)
#define | FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U)
#define | FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U)
#define | FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U)
#define | FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U)
#define | FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U)
#define | FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U)
#define | FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U)
#define | FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U)
#define | FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U)
#define | FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U)

Define Documentation

#define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U)

Divide kernel clock by 1

Definition at line 805 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U)

Divide kernel clock by 10

Definition at line 810 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U)

Divide kernel clock by 12

Definition at line 811 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U)

Divide kernel clock by 14

Definition at line 812 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U)

Divide kernel clock by 16

Definition at line 813 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U)

Divide kernel clock by 18

Definition at line 814 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV2 ((uint32_t)0x00010000U)

Divide kernel clock by 2

Definition at line 806 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U)

Divide kernel clock by 20

Definition at line 815 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U)

Divide kernel clock by 22

Definition at line 816 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U)

Divide kernel clock by 24

Definition at line 817 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U)

Divide kernel clock by 26

Definition at line 818 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U)

Divide kernel clock by 28

Definition at line 819 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U)

Divide kernel clock by 30

Definition at line 820 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV4 ((uint32_t)0x00020000U)

Divide kernel clock by 4

Definition at line 807 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV6 ((uint32_t)0x00030000U)

Divide kernel clock by 6

Definition at line 808 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV8 ((uint32_t)0x00040000U)

Divide kernel clock by 8

Definition at line 809 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Calibration Field Length

Defines
FDCAN Calibration Field Length
FDCAN Exported Constants

Defines

#define | FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U)
#define | FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL)

Define Documentation

#define FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U)

Calibration field length is 32 bits

Definition at line 828 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL)

Calibration field length is 64 bits

Definition at line 829 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Calibration State

Defines
FDCAN Calibration State
FDCAN Exported Constants

Defines

#define | FDCAN_CLOCK_NOT_CALIBRATED ((uint32_t)0x00000000U)
#define | FDCAN_CLOCK_BASIC_CALIBRATED ((uint32_t)0x40000000U)
#define | FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U)

Define Documentation

#define FDCAN_CLOCK_BASIC_CALIBRATED ((uint32_t)0x40000000U)

Clock basic calibrated

Definition at line 838 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_NOT_CALIBRATED ((uint32_t)0x00000000U)

Clock not calibrated

Definition at line 837 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U)

Clock precision calibrated

Definition at line 839 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Calibration Counter

Defines
FDCAN Calibration Counter
FDCAN Exported Constants

Defines

#define | FDCAN_CALIB_TIME_QUANTA_COUNTER ((uint32_t)0x00000000U)
#define | FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U)
#define | FDCAN_CALIB_WATCHDOG_COUNTER ((uint32_t)0x00000002U)

Define Documentation

#define FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U)

Oscillator Clock Period Counter

Definition at line 848 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetClockCalibrationCounter().

#define FDCAN_CALIB_TIME_QUANTA_COUNTER ((uint32_t)0x00000000U)

Time Quanta Counter

Definition at line 847 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetClockCalibrationCounter().

#define FDCAN_CALIB_WATCHDOG_COUNTER ((uint32_t)0x00000002U)

Calibration Watchdog Counter

Definition at line 849 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Data Field Size

Defines
FDCAN Data Field Size
FDCAN Exported Constants

Defines

#define | FDCAN_DATA_BYTES_8 ((uint32_t)0x00000004U)
#define | FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U)
#define | FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U)
#define | FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U)
#define | FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U)
#define | FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU)
#define | FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU)
#define | FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U)

Define Documentation

#define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U)

12 bytes data field

Definition at line 858 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U)

16 bytes data field

Definition at line 859 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U)

20 bytes data field

Definition at line 860 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U)

24 bytes data field

Definition at line 861 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU)

32 bytes data field

Definition at line 862 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU)

48 bytes data field

Definition at line 863 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U)

64 bytes data field

Definition at line 864 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DATA_BYTES_8 ((uint32_t)0x00000004U)

8 bytes data field

Definition at line 857 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN Tx FIFO/Queue Mode

Defines
FDCAN Tx FIFO/Queue Mode
FDCAN Exported Constants

Defines

#define | FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U)
#define | FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM)

Define Documentation

#define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U)

FIFO mode

Definition at line 872 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM)

Queue mode

Definition at line 873 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN ID Type

Defines
FDCAN ID Type
FDCAN Exported Constants

Defines

#define | FDCAN_STANDARD_ID ((uint32_t)0x00000000U)
#define | FDCAN_EXTENDED_ID ((uint32_t)0x40000000U)

Define Documentation

#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U)

Extended ID element

Definition at line 882 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_TT_ConfigReferenceMessage().

#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U)

Standard ID element

Definition at line 881 of file stm32h7xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxBuffer(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetTxEvent(), HAL_FDCAN_TT_ConfigReferenceMessage(), and HAL_FDCAN_TT_ConfigTrigger().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Frame Type

Defines
FDCAN Frame Type
FDCAN Exported Constants

Defines

#define | FDCAN_DATA_FRAME ((uint32_t)0x00000000U)
#define | FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)

Define Documentation

#define FDCAN_DATA_FRAME ((uint32_t)0x00000000U)

Data frame

Definition at line 890 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)

Remote frame

Definition at line 891 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Data Length Code

Defines
FDCAN Data Length Code
FDCAN Exported Constants

Defines

#define | FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U)
#define | FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U)
#define | FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U)
#define | FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U)
#define | FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U)
#define | FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U)
#define | FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U)
#define | FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U)
#define | FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U)
#define | FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U)
#define | FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U)
#define | FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U)
#define | FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U)
#define | FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U)
#define | FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U)
#define | FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U)

Define Documentation

#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U)

0 bytes data field

Definition at line 899 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U)

1 bytes data field

Definition at line 900 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U)

12 bytes data field

Definition at line 908 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U)

16 bytes data field

Definition at line 909 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U)

2 bytes data field

Definition at line 901 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U)

20 bytes data field

Definition at line 910 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U)

24 bytes data field

Definition at line 911 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U)

3 bytes data field

Definition at line 902 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U)

32 bytes data field

Definition at line 912 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U)

4 bytes data field

Definition at line 903 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U)

48 bytes data field

Definition at line 913 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U)

5 bytes data field

Definition at line 904 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U)

6 bytes data field

Definition at line 905 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U)

64 bytes data field

Definition at line 914 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U)

7 bytes data field

Definition at line 906 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U)

8 bytes data field

Definition at line 907 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Error State Indicator

Defines
FDCAN Error State Indicator
FDCAN Exported Constants

Defines

#define | FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U)
#define | FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U)

Define Documentation

#define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U)

Transmitting node is error active

Definition at line 922 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U)

Transmitting node is error passive

Definition at line 923 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Bit Rate Switching

Defines
FDCAN Bit Rate Switching
FDCAN Exported Constants

Defines

#define | FDCAN_BRS_OFF ((uint32_t)0x00000000U)
#define | FDCAN_BRS_ON ((uint32_t)0x00100000U)

Define Documentation

#define FDCAN_BRS_OFF ((uint32_t)0x00000000U)

FDCAN frames transmitted/received without bit rate switching

Definition at line 931 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_BRS_ON ((uint32_t)0x00100000U)

FDCAN frames transmitted/received with bit rate switching

Definition at line 932 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN format

Defines
FDCAN format
FDCAN Exported Constants

Defines

#define | FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U)
#define | FDCAN_FD_CAN ((uint32_t)0x00200000U)

Define Documentation

#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U)

Frame transmitted/received in Classic CAN format

Definition at line 940 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FD_CAN ((uint32_t)0x00200000U)

Frame transmitted/received in FDCAN format

Definition at line 941 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Event FIFO control

Defines
FDCAN Event FIFO control
FDCAN Exported Constants

Defines

#define | FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U)
#define | FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U)

Define Documentation

#define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U)

Do not store Tx events

Definition at line 949 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U)

Store Tx events

Definition at line 950 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Filter Type

Defines
FDCAN Filter Type
FDCAN Exported Constants

Defines

#define | FDCAN_FILTER_RANGE ((uint32_t)0x00000000U)
#define | FDCAN_FILTER_DUAL ((uint32_t)0x00000001U)
#define | FDCAN_FILTER_MASK ((uint32_t)0x00000002U)
#define | FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U)

Define Documentation

#define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U)

Dual ID filter for FilterID1 or FilterID2

Definition at line 959 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FILTER_MASK ((uint32_t)0x00000002U)

Classic filter: FilterID1 = filter, FilterID2 = mask

Definition at line 960 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U)

Range filter from FilterID1 to FilterID2

Definition at line 958 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U)

Range filter from FilterID1 to FilterID2, EIDM mask not applied

Definition at line 961 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Filter Configuration

Defines
FDCAN Filter Configuration
FDCAN Exported Constants

Defines

#define | FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U)
#define | FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U)
#define | FDCAN_FILTER_REJECT ((uint32_t)0x00000003U)
#define | FDCAN_FILTER_HP ((uint32_t)0x00000004U)
#define | FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U)
#define | FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U)
#define | FDCAN_FILTER_TO_RXBUFFER ((uint32_t)0x00000007U)

Define Documentation

#define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U)

Disable filter element

Definition at line 969 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FILTER_HP ((uint32_t)0x00000004U)

Set high priority if filter matches

Definition at line 973 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U)

Reject ID if filter matches

Definition at line 972 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FILTER_TO_RXBUFFER ((uint32_t)0x00000007U)

Store into Rx Buffer, configuration of FilterType ignored

Definition at line 976 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

#define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U)

Store in Rx FIFO 0 if filter matches

Definition at line 970 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U)

Set high priority and store in FIFO 0 if filter matches

Definition at line 974 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U)

Store in Rx FIFO 1 if filter matches

Definition at line 971 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U)

Set high priority and store in FIFO 1 if filter matches

Definition at line 975 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Tx Location

Defines
FDCAN Tx Location
FDCAN Exported Constants

Defines

#define | FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U)
#define | FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U)
#define | FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U)
#define | FDCAN_TX_BUFFER3 ((uint32_t)0x00000008U)
#define | FDCAN_TX_BUFFER4 ((uint32_t)0x00000010U)
#define | FDCAN_TX_BUFFER5 ((uint32_t)0x00000020U)
#define | FDCAN_TX_BUFFER6 ((uint32_t)0x00000040U)
#define | FDCAN_TX_BUFFER7 ((uint32_t)0x00000080U)
#define | FDCAN_TX_BUFFER8 ((uint32_t)0x00000100U)
#define | FDCAN_TX_BUFFER9 ((uint32_t)0x00000200U)
#define | FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U)
#define | FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U)
#define | FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U)
#define | FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U)
#define | FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U)
#define | FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U)
#define | FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U)
#define | FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U)
#define | FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U)
#define | FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U)
#define | FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U)
#define | FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U)
#define | FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U)
#define | FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U)
#define | FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U)
#define | FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U)
#define | FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U)
#define | FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U)
#define | FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U)
#define | FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U)
#define | FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U)
#define | FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U)

Define Documentation

#define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U)

Add message to Tx Buffer 0

Definition at line 984 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U)

Add message to Tx Buffer 1

Definition at line 985 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U)

Add message to Tx Buffer 10

Definition at line 994 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U)

Add message to Tx Buffer 11

Definition at line 995 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U)

Add message to Tx Buffer 12

Definition at line 996 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U)

Add message to Tx Buffer 13

Definition at line 997 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U)

Add message to Tx Buffer 14

Definition at line 998 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U)

Add message to Tx Buffer 15

Definition at line 999 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U)

Add message to Tx Buffer 16

Definition at line 1000 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U)

Add message to Tx Buffer 17

Definition at line 1001 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U)

Add message to Tx Buffer 18

Definition at line 1002 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U)

Add message to Tx Buffer 19

Definition at line 1003 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U)

Add message to Tx Buffer 2

Definition at line 986 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U)

Add message to Tx Buffer 20

Definition at line 1004 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U)

Add message to Tx Buffer 21

Definition at line 1005 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U)

Add message to Tx Buffer 22

Definition at line 1006 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U)

Add message to Tx Buffer 23

Definition at line 1007 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U)

Add message to Tx Buffer 24

Definition at line 1008 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U)

Add message to Tx Buffer 25

Definition at line 1009 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U)

Add message to Tx Buffer 26

Definition at line 1010 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U)

Add message to Tx Buffer 27

Definition at line 1011 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U)

Add message to Tx Buffer 28

Definition at line 1012 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U)

Add message to Tx Buffer 29

Definition at line 1013 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER3 ((uint32_t)0x00000008U)

Add message to Tx Buffer 3

Definition at line 987 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U)

Add message to Tx Buffer 30

Definition at line 1014 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U)

Add message to Tx Buffer 31

Definition at line 1015 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER4 ((uint32_t)0x00000010U)

Add message to Tx Buffer 4

Definition at line 988 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER5 ((uint32_t)0x00000020U)

Add message to Tx Buffer 5

Definition at line 989 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER6 ((uint32_t)0x00000040U)

Add message to Tx Buffer 6

Definition at line 990 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER7 ((uint32_t)0x00000080U)

Add message to Tx Buffer 7

Definition at line 991 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER8 ((uint32_t)0x00000100U)

Add message to Tx Buffer 8

Definition at line 992 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER9 ((uint32_t)0x00000200U)

Add message to Tx Buffer 9

Definition at line 993 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Rx Location

Defines
FDCAN Rx Location
FDCAN Exported Constants

Defines

#define | FDCAN_RX_FIFO0 ((uint32_t)0x00000040U)
#define | FDCAN_RX_FIFO1 ((uint32_t)0x00000041U)
#define | FDCAN_RX_BUFFER0 ((uint32_t)0x00000000U)
#define | FDCAN_RX_BUFFER1 ((uint32_t)0x00000001U)
#define | FDCAN_RX_BUFFER2 ((uint32_t)0x00000002U)
#define | FDCAN_RX_BUFFER3 ((uint32_t)0x00000003U)
#define | FDCAN_RX_BUFFER4 ((uint32_t)0x00000004U)
#define | FDCAN_RX_BUFFER5 ((uint32_t)0x00000005U)
#define | FDCAN_RX_BUFFER6 ((uint32_t)0x00000006U)
#define | FDCAN_RX_BUFFER7 ((uint32_t)0x00000007U)
#define | FDCAN_RX_BUFFER8 ((uint32_t)0x00000008U)
#define | FDCAN_RX_BUFFER9 ((uint32_t)0x00000009U)
#define | FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU)
#define | FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU)
#define | FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU)
#define | FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU)
#define | FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU)
#define | FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU)
#define | FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U)
#define | FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U)
#define | FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U)
#define | FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U)
#define | FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U)
#define | FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U)
#define | FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U)
#define | FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U)
#define | FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U)
#define | FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U)
#define | FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU)
#define | FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU)
#define | FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU)
#define | FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU)
#define | FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU)
#define | FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU)
#define | FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U)
#define | FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U)
#define | FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U)
#define | FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U)
#define | FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U)
#define | FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U)
#define | FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U)
#define | FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U)
#define | FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U)
#define | FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U)
#define | FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU)
#define | FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU)
#define | FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU)
#define | FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU)
#define | FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU)
#define | FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU)
#define | FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U)
#define | FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U)
#define | FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U)
#define | FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U)
#define | FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U)
#define | FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U)
#define | FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U)
#define | FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U)
#define | FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U)
#define | FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U)
#define | FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU)
#define | FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU)
#define | FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU)
#define | FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU)
#define | FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU)
#define | FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU)

Define Documentation

#define FDCAN_RX_BUFFER0 ((uint32_t)0x00000000U)

Get received message from Rx Buffer 0

Definition at line 1025 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER1 ((uint32_t)0x00000001U)

Get received message from Rx Buffer 1

Definition at line 1026 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU)

Get received message from Rx Buffer 10

Definition at line 1035 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU)

Get received message from Rx Buffer 11

Definition at line 1036 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU)

Get received message from Rx Buffer 12

Definition at line 1037 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU)

Get received message from Rx Buffer 13

Definition at line 1038 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU)

Get received message from Rx Buffer 14

Definition at line 1039 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU)

Get received message from Rx Buffer 15

Definition at line 1040 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U)

Get received message from Rx Buffer 16

Definition at line 1041 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U)

Get received message from Rx Buffer 17

Definition at line 1042 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U)

Get received message from Rx Buffer 18

Definition at line 1043 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U)

Get received message from Rx Buffer 19

Definition at line 1044 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER2 ((uint32_t)0x00000002U)

Get received message from Rx Buffer 2

Definition at line 1027 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U)

Get received message from Rx Buffer 20

Definition at line 1045 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U)

Get received message from Rx Buffer 21

Definition at line 1046 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U)

Get received message from Rx Buffer 22

Definition at line 1047 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U)

Get received message from Rx Buffer 23

Definition at line 1048 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U)

Get received message from Rx Buffer 24

Definition at line 1049 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U)

Get received message from Rx Buffer 25

Definition at line 1050 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU)

Get received message from Rx Buffer 26

Definition at line 1051 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU)

Get received message from Rx Buffer 27

Definition at line 1052 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU)

Get received message from Rx Buffer 28

Definition at line 1053 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU)

Get received message from Rx Buffer 29

Definition at line 1054 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER3 ((uint32_t)0x00000003U)

Get received message from Rx Buffer 3

Definition at line 1028 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU)

Get received message from Rx Buffer 30

Definition at line 1055 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU)

Get received message from Rx Buffer 31

Definition at line 1056 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U)

Get received message from Rx Buffer 32

Definition at line 1057 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

#define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U)

Get received message from Rx Buffer 33

Definition at line 1058 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U)

Get received message from Rx Buffer 34

Definition at line 1059 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U)

Get received message from Rx Buffer 35

Definition at line 1060 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U)

Get received message from Rx Buffer 36

Definition at line 1061 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U)

Get received message from Rx Buffer 37

Definition at line 1062 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U)

Get received message from Rx Buffer 38

Definition at line 1063 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U)

Get received message from Rx Buffer 39

Definition at line 1064 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER4 ((uint32_t)0x00000004U)

Get received message from Rx Buffer 4

Definition at line 1029 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U)

Get received message from Rx Buffer 40

Definition at line 1065 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U)

Get received message from Rx Buffer 41

Definition at line 1066 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU)

Get received message from Rx Buffer 42

Definition at line 1067 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU)

Get received message from Rx Buffer 43

Definition at line 1068 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU)

Get received message from Rx Buffer 44

Definition at line 1069 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU)

Get received message from Rx Buffer 45

Definition at line 1070 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU)

Get received message from Rx Buffer 46

Definition at line 1071 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU)

Get received message from Rx Buffer 47

Definition at line 1072 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U)

Get received message from Rx Buffer 48

Definition at line 1073 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U)

Get received message from Rx Buffer 49

Definition at line 1074 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER5 ((uint32_t)0x00000005U)

Get received message from Rx Buffer 5

Definition at line 1030 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U)

Get received message from Rx Buffer 50

Definition at line 1075 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U)

Get received message from Rx Buffer 51

Definition at line 1076 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U)

Get received message from Rx Buffer 52

Definition at line 1077 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U)

Get received message from Rx Buffer 53

Definition at line 1078 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U)

Get received message from Rx Buffer 54

Definition at line 1079 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U)

Get received message from Rx Buffer 55

Definition at line 1080 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U)

Get received message from Rx Buffer 56

Definition at line 1081 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U)

Get received message from Rx Buffer 57

Definition at line 1082 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU)

Get received message from Rx Buffer 58

Definition at line 1083 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU)

Get received message from Rx Buffer 59

Definition at line 1084 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER6 ((uint32_t)0x00000006U)

Get received message from Rx Buffer 6

Definition at line 1031 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU)

Get received message from Rx Buffer 60

Definition at line 1085 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU)

Get received message from Rx Buffer 61

Definition at line 1086 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU)

Get received message from Rx Buffer 62

Definition at line 1087 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU)

Get received message from Rx Buffer 63

Definition at line 1088 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER7 ((uint32_t)0x00000007U)

Get received message from Rx Buffer 7

Definition at line 1032 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER8 ((uint32_t)0x00000008U)

Get received message from Rx Buffer 8

Definition at line 1033 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_BUFFER9 ((uint32_t)0x00000009U)

Get received message from Rx Buffer 9

Definition at line 1034 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U)

Get received message from Rx FIFO 0

Definition at line 1023 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_GetRxFifoFillLevel(), and HAL_FDCAN_GetRxMessage().

#define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U)

Get received message from Rx FIFO 1

Definition at line 1024 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Event Type

Defines
FDCAN Event Type
FDCAN Exported Constants

Defines

#define | FDCAN_TX_EVENT ((uint32_t)0x00400000U)
#define | FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U)

Define Documentation

#define FDCAN_TX_EVENT ((uint32_t)0x00400000U)

Tx event

Definition at line 1096 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U)

Transmission in spite of cancellation

Definition at line 1097 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN High Priority Message Storage

Defines
FDCAN High Priority Message Storage
FDCAN Exported Constants

Defines

#define | FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U)
#define | FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U)
#define | FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U)
#define | FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U)

Define Documentation

#define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U)

FIFO message lost

Definition at line 1106 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U)

No FIFO selected

Definition at line 1105 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U)

Message stored in FIFO 0

Definition at line 1107 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U)

Message stored in FIFO 1

Definition at line 1108 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN protocol error code

Defines
FDCAN protocol error code
FDCAN Exported Constants

Defines

#define | FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U)
#define | FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U)
#define | FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U)
#define | FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U)
#define | FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U)
#define | FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U)
#define | FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U)
#define | FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U)

Define Documentation

#define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U)

Acknowledge error

Definition at line 1119 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U)

Bit 0 (dominant) error

Definition at line 1121 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U)

Bit 1 (recessive) error

Definition at line 1120 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U)

CRC check sum error

Definition at line 1122 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U)

Form error

Definition at line 1118 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U)

No change since last read

Definition at line 1123 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U)

No error occurred

Definition at line 1116 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U)

Stuff error

Definition at line 1117 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN communication state

Defines
FDCAN communication state
FDCAN Exported Constants

Defines

#define | FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U)
#define | FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U)
#define | FDCAN_COM_STATE_RX ((uint32_t)0x00000016U)
#define | FDCAN_COM_STATE_TX ((uint32_t)0x00000024U)

Define Documentation

#define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U)

Node is neither receiver nor transmitter

Definition at line 1132 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_COM_STATE_RX ((uint32_t)0x00000016U)

Node is operating as receiver

Definition at line 1133 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U)

Node is synchronizing on CAN communication

Definition at line 1131 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_COM_STATE_TX ((uint32_t)0x00000024U)

Node is operating as transmitter

Definition at line 1134 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN FIFO watermark

Defines
FDCAN FIFO watermark
FDCAN Exported Constants

Defines

#define | FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U)
#define | FDCAN_CFG_RX_FIFO0 ((uint32_t)0x00000001U)
#define | FDCAN_CFG_RX_FIFO1 ((uint32_t)0x00000002U)

Define Documentation

#define FDCAN_CFG_RX_FIFO0 ((uint32_t)0x00000001U)

Rx FIFO0

Definition at line 1143 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFifoWatermark().

#define FDCAN_CFG_RX_FIFO1 ((uint32_t)0x00000002U)

Rx FIFO1

Definition at line 1144 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U)

Tx event FIFO

Definition at line 1142 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFifoWatermark().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN FIFO operation mode

Defines
FDCAN FIFO operation mode
FDCAN Exported Constants

Defines

#define | FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U)
#define | FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U)

Define Documentation

#define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U)

Rx FIFO blocking mode

Definition at line 1152 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U)

Rx FIFO overwrite mode

Definition at line 1153 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN non-matching frames

Defines
FDCAN non-matching frames
FDCAN Exported Constants

Defines

#define | FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U)
#define | FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U)
#define | FDCAN_REJECT ((uint32_t)0x00000002U)

Define Documentation

#define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U)

Accept in Rx FIFO 0

Definition at line 1161 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U)

Accept in Rx FIFO 1

Definition at line 1162 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_REJECT ((uint32_t)0x00000002U)

Reject

Definition at line 1163 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN interrupt line

Defines
FDCAN interrupt line
FDCAN Exported Constants

Defines

#define | FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U)
#define | FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U)

Define Documentation

#define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U)

Interrupt Line 0

Definition at line 1171 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_TT_ActivateNotification(), and HAL_FDCAN_TT_ConfigInterruptLines().

#define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U)

Interrupt Line 1

Definition at line 1172 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_TT_ActivateNotification().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN timestamp

Defines
FDCAN timestamp
FDCAN Exported Constants

Defines

#define | FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U)
#define | FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U)

Define Documentation

#define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U)

External timestamp counter value used

Definition at line 1181 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ResetTimestampCounter().

#define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U)

Timestamp counter value incremented according to TCP

Definition at line 1180 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN timestamp prescaler

Defines
FDCAN timestamp prescaler
FDCAN Exported Constants

Defines

#define | FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U)
#define | FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U)
#define | FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U)
#define | FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U)
#define | FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U)
#define | FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U)
#define | FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U)
#define | FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U)
#define | FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U)
#define | FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U)
#define | FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U)
#define | FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U)
#define | FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U)
#define | FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U)
#define | FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U)
#define | FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U)

Define Documentation

#define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U)

Timestamp counter time unit in equal to CAN bit time

Definition at line 1189 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U)

Timestamp counter time unit in equal to CAN bit time multipled by 10

Definition at line 1198 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U)

Timestamp counter time unit in equal to CAN bit time multipled by 11

Definition at line 1199 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U)

Timestamp counter time unit in equal to CAN bit time multipled by 12

Definition at line 1200 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U)

Timestamp counter time unit in equal to CAN bit time multipled by 13

Definition at line 1201 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U)

Timestamp counter time unit in equal to CAN bit time multipled by 14

Definition at line 1202 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U)

Timestamp counter time unit in equal to CAN bit time multipled by 15

Definition at line 1203 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U)

Timestamp counter time unit in equal to CAN bit time multipled by 16

Definition at line 1204 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U)

Timestamp counter time unit in equal to CAN bit time multipled by 2

Definition at line 1190 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U)

Timestamp counter time unit in equal to CAN bit time multipled by 3

Definition at line 1191 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U)

Timestamp counter time unit in equal to CAN bit time multipled by 4

Definition at line 1192 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U)

Timestamp counter time unit in equal to CAN bit time multipled by 5

Definition at line 1193 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U)

Timestamp counter time unit in equal to CAN bit time multipled by 6

Definition at line 1194 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U)

Timestamp counter time unit in equal to CAN bit time multipled by 7

Definition at line 1195 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U)

Timestamp counter time unit in equal to CAN bit time multipled by 8

Definition at line 1196 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U)

Timestamp counter time unit in equal to CAN bit time multipled by 9

Definition at line 1197 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN timeout operation

Defines
FDCAN timeout operation
FDCAN Exported Constants

Defines

#define | FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U)
#define | FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U)
#define | FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U)
#define | FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U)

Define Documentation

#define FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U)

Timeout continuous operation

Definition at line 1212 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ResetTimeoutCounter().

#define FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U)

Timeout controlled by Rx FIFO 0

Definition at line 1214 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U)

Timeout controlled by Rx FIFO 1

Definition at line 1215 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U)

Timeout controlled by Tx Event FIFO

Definition at line 1213 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN TT reference message payload

Defines
FDCAN TT reference message payload
FDCAN Exported Constants

Defines

#define | FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ((uint32_t)0x00000000U)
#define | FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS)

Define Documentation

#define FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS)

Additional payload is taken from Tx Buffer 0

Definition at line 1224 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ((uint32_t)0x00000000U)

Reference message has no additional payload

Definition at line 1223 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN TT repeat factor

Defines
FDCAN TT repeat factor
FDCAN Exported Constants

Defines

#define | FDCAN_TT_REPEAT_EVERY_CYCLE ((uint32_t)0x00000000U)
#define | FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ((uint32_t)0x00000002U)
#define | FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ((uint32_t)0x00000004U)
#define | FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ((uint32_t)0x00000008U)
#define | FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U)
#define | FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U)
#define | FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U)

Define Documentation

#define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U)

Trigger valid every 16th cycle

Definition at line 1236 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ((uint32_t)0x00000002U)

Trigger valid every 2dn cycle

Definition at line 1233 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U)

Trigger valid every 32nd cycle

Definition at line 1237 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ((uint32_t)0x00000004U)

Trigger valid every 4th cycle

Definition at line 1234 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U)

Trigger valid every 64th cycle

Definition at line 1238 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ((uint32_t)0x00000008U)

Trigger valid every 8th cycle

Definition at line 1235 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_REPEAT_EVERY_CYCLE ((uint32_t)0x00000000U)

Trigger valid for all cycles

Definition at line 1232 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigRegisterTimeMark(), and HAL_FDCAN_TT_ConfigTrigger().

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STM32H753xx HAL User Manual: FDCAN TT trigger type

Defines
FDCAN TT trigger type
FDCAN Exported Constants

Defines

#define | FDCAN_TT_TX_REF_TRIGGER ((uint32_t)0x00000000U)
#define | FDCAN_TT_TX_REF_TRIGGER_GAP ((uint32_t)0x00000001U)
#define | FDCAN_TT_TX_TRIGGER_SINGLE ((uint32_t)0x00000002U)
#define | FDCAN_TT_TX_TRIGGER_CONTINUOUS ((uint32_t)0x00000003U)
#define | FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U)
#define | FDCAN_TT_TX_TRIGGER_MERGED ((uint32_t)0x00000005U)
#define | FDCAN_TT_WATCH_TRIGGER ((uint32_t)0x00000006U)
#define | FDCAN_TT_WATCH_TRIGGER_GAP ((uint32_t)0x00000007U)
#define | FDCAN_TT_RX_TRIGGER ((uint32_t)0x00000008U)
#define | FDCAN_TT_TIME_BASE_TRIGGER ((uint32_t)0x00000009U)
#define | FDCAN_TT_END_OF_LIST ((uint32_t)0x0000000AU)

Define Documentation

#define FDCAN_TT_END_OF_LIST ((uint32_t)0x0000000AU)

Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP

Definition at line 1256 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_RX_TRIGGER ((uint32_t)0x00000008U)

Check for the reception of periodic messages in exclusive time windows

Definition at line 1254 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

#define FDCAN_TT_TIME_BASE_TRIGGER ((uint32_t)0x00000009U)

Generate internal/external events depending on TmEventInt/TmEventExt configuration

Definition at line 1255 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_TX_REF_TRIGGER ((uint32_t)0x00000000U)

Transmit reference message in strictly time-triggered operation

Definition at line 1246 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_TX_REF_TRIGGER_GAP ((uint32_t)0x00000001U)

Transmit reference message in external event-synchronized time-triggered operation

Definition at line 1247 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U)

Start a transmission in an arbitration time window

Definition at line 1250 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

#define FDCAN_TT_TX_TRIGGER_CONTINUOUS ((uint32_t)0x00000003U)

Start a continuous transmission in an exclusive time window

Definition at line 1249 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

#define FDCAN_TT_TX_TRIGGER_MERGED ((uint32_t)0x00000005U)

Start a merged arbitration window

Definition at line 1251 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

#define FDCAN_TT_TX_TRIGGER_SINGLE ((uint32_t)0x00000002U)

Start a single transmission in an exclusive time window

Definition at line 1248 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

#define FDCAN_TT_WATCH_TRIGGER ((uint32_t)0x00000006U)

Check for missing reference messages in strictly time-triggered operation

Definition at line 1252 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_WATCH_TRIGGER_GAP ((uint32_t)0x00000007U)

Check for missing reference messages in external event-synchronized time-triggered operation

Definition at line 1253 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN TT time mark event internal

Defines
FDCAN TT time mark event internal
FDCAN Exported Constants

Defines

#define | FDCAN_TT_TM_NO_INTERNAL_EVENT ((uint32_t)0x00000000U)
#define | FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U)

Define Documentation

#define FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U)

Internal event is generated when trigger becomes active

Definition at line 1265 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_TM_NO_INTERNAL_EVENT ((uint32_t)0x00000000U)

No action

Definition at line 1264 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN TT time mark event external

Defines
FDCAN TT time mark event external
FDCAN Exported Constants

Defines

#define | FDCAN_TT_TM_NO_EXTERNAL_EVENT ((uint32_t)0x00000000U)
#define | FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U)

Define Documentation

#define FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U)

External event (pulse) is generated when trigger becomes active

Definition at line 1274 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_TM_NO_EXTERNAL_EVENT ((uint32_t)0x00000000U)

No action

Definition at line 1273 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN Operation Mode

Defines
FDCAN Operation Mode
FDCAN Exported Constants

Defines

#define | FDCAN_TT_COMMUNICATION_LEVEL1 ((uint32_t)0x00000001U)
#define | FDCAN_TT_COMMUNICATION_LEVEL2 ((uint32_t)0x00000002U)
#define | FDCAN_TT_COMMUNICATION_LEVEL0 ((uint32_t)0x00000003U)

Define Documentation

#define FDCAN_TT_COMMUNICATION_LEVEL0 ((uint32_t)0x00000003U)

Time triggered communication, level 0

Definition at line 1284 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation(), HAL_FDCAN_TT_DisableHardwareGapControl(), HAL_FDCAN_TT_DisableTimeMarkGapControl(), HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(), HAL_FDCAN_TT_EnableHardwareGapControl(), HAL_FDCAN_TT_EnableTimeMarkGapControl(), HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(), HAL_FDCAN_TT_SetEndOfGap(), and HAL_FDCAN_TT_SetNextIsGap().

#define FDCAN_TT_COMMUNICATION_LEVEL1 ((uint32_t)0x00000001U)

Time triggered communication, level 1

Definition at line 1282 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define FDCAN_TT_COMMUNICATION_LEVEL2 ((uint32_t)0x00000002U)

Time triggered communication, level 2

Definition at line 1283 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN TT Operation

Defines
FDCAN TT Operation
FDCAN Exported Constants

Defines

#define | FDCAN_STRICTLY_TT_OPERATION ((uint32_t)0x00000000U)
#define | FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN)

Define Documentation

#define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN)

External event-synchronized time-triggered operation

Definition at line 1293 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_STRICTLY_TT_OPERATION ((uint32_t)0x00000000U)

Strictly time-triggered operation

Definition at line 1292 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN TT Time Master

Defines
FDCAN TT Time Master
FDCAN Exported Constants

Defines

#define | FDCAN_TT_SLAVE ((uint32_t)0x00000000U)
#define | FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM)

Define Documentation

#define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM)

Potential time master

Definition at line 1302 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define FDCAN_TT_SLAVE ((uint32_t)0x00000000U)

Time slave

Definition at line 1301 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN TT External Clock Synchronization

Defines
FDCAN TT External Clock Synchronization
FDCAN Exported Constants

Defines

#define | FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_TT_EXT_CLK_SYNC_ENABLE ((uint32_t)FDCAN_TTOCF_EECS)

Define Documentation

#define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U)

External clock synchronization in Level 0,2 disabled

Definition at line 1310 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_EXT_CLK_SYNC_ENABLE ((uint32_t)FDCAN_TTOCF_EECS)

External clock synchronization in Level 0,2 enabled

Definition at line 1311 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN TT Global Time Filtering

Defines
FDCAN TT Global Time Filtering
FDCAN Exported Constants

Defines

#define | FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_TT_GLOB_TIME_FILT_ENABLE ((uint32_t)FDCAN_TTOCF_EGTF)

Define Documentation

#define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U)

Global time filtering in Level 0,2 disabled

Definition at line 1319 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_GLOB_TIME_FILT_ENABLE ((uint32_t)FDCAN_TTOCF_EGTF)

Global time filtering in Level 0,2 enabled

Definition at line 1320 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN TT Automatic Clock Calibration

Defines
FDCAN TT Automatic Clock Calibration
FDCAN Exported Constants

Defines

#define | FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_TT_AUTO_CLK_CALIB_ENABLE ((uint32_t)FDCAN_TTOCF_ECC)

Define Documentation

#define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U)

Automatic clock calibration in Level 0,2 disabled

Definition at line 1328 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_AUTO_CLK_CALIB_ENABLE ((uint32_t)FDCAN_TTOCF_ECC)

Automatic clock calibration in Level 0,2 enabled

Definition at line 1329 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN TT Event Trigger Polarity

Defines
FDCAN TT Event Trigger Polarity
FDCAN Exported Constants

Defines

#define | FDCAN_TT_EVT_TRIG_POL_RISING ((uint32_t)0x00000000U)
#define | FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP)

Define Documentation

#define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP)

Falling edge trigger

Definition at line 1338 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_EVT_TRIG_POL_RISING ((uint32_t)0x00000000U)

Rising edge trigger

Definition at line 1337 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN TT Basic Cycle Number

Defines
FDCAN TT Basic Cycle Number
FDCAN Exported Constants

Defines

#define | FDCAN_TT_CYCLES_PER_MATRIX_1 ((uint32_t)0x00000000U)
#define | FDCAN_TT_CYCLES_PER_MATRIX_2 ((uint32_t)0x00000001U)
#define | FDCAN_TT_CYCLES_PER_MATRIX_4 ((uint32_t)0x00000003U)
#define | FDCAN_TT_CYCLES_PER_MATRIX_8 ((uint32_t)0x00000007U)
#define | FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU)
#define | FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU)
#define | FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU)

Define Documentation

#define FDCAN_TT_CYCLES_PER_MATRIX_1 ((uint32_t)0x00000000U)

1 Basic Cycle per Matrix

Definition at line 1346 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU)

16 Basic Cycles per Matrix

Definition at line 1350 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_CYCLES_PER_MATRIX_2 ((uint32_t)0x00000001U)

2 Basic Cycles per Matrix

Definition at line 1347 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU)

32 Basic Cycles per Matrix

Definition at line 1351 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_CYCLES_PER_MATRIX_4 ((uint32_t)0x00000003U)

4 Basic Cycles per Matrix

Definition at line 1348 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU)

64 Basic Cycles per Matrix

Definition at line 1352 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_CYCLES_PER_MATRIX_8 ((uint32_t)0x00000007U)

8 Basic Cycles per Matrix

Definition at line 1349 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN TT Cycle Start Sync

Defines
FDCAN TT Cycle Start Sync
FDCAN Exported Constants

Defines

#define | FDCAN_TT_NO_SYNC_PULSE ((uint32_t)0x00000000U)
#define | FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U)
#define | FDCAN_TT_SYNC_MATRIX_START ((uint32_t)0x00000080U)

Define Documentation

#define FDCAN_TT_NO_SYNC_PULSE ((uint32_t)0x00000000U)

No sync pulse

Definition at line 1360 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U)

Sync pulse at start of basic cycle

Definition at line 1361 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_SYNC_MATRIX_START ((uint32_t)0x00000080U)

Sync pulse at start of matrix

Definition at line 1362 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN TT Stop Watch Trigger Selection

Defines
FDCAN TT Stop Watch Trigger Selection
FDCAN Exported Constants

Defines

#define | FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U)
#define | FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U)
#define | FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U)
#define | FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U)

Define Documentation

#define FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U)

TIM2 selected as stop watch trigger

Definition at line 1370 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U)

TIM3 selected as stop watch trigger

Definition at line 1371 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U)

ETH selected as stop watch trigger

Definition at line 1372 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U)

HRTIM selected as stop watch trigger

Definition at line 1373 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN TT Event Trigger Selection

Defines
FDCAN TT Event Trigger Selection
FDCAN Exported Constants

Defines

#define | FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U)
#define | FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U)
#define | FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U)
#define | FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U)

Define Documentation

#define FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U)

TIM2 selected as event trigger

Definition at line 1381 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U)

TIM3 selected as event trigger

Definition at line 1382 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U)

ETH selected as event trigger

Definition at line 1383 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U)

HRTIM selected as event trigger

Definition at line 1384 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN TT Stop Watch Source

Defines
FDCAN TT Stop Watch Source
FDCAN Exported Constants

Defines

#define | FDCAN_TT_STOP_WATCH_DISABLED ((uint32_t)0x00000000U)
#define | FDCAN_TT_STOP_WATCH_CYCLE_TIME ((uint32_t)0x00000008U)
#define | FDCAN_TT_STOP_WATCH_LOCAL_TIME ((uint32_t)0x00000010U)
#define | FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U)

Define Documentation

#define FDCAN_TT_STOP_WATCH_CYCLE_TIME ((uint32_t)0x00000008U)

Actual value of cycle time is copied to Capture Time register (TTCPT.SWV)

Definition at line 1393 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_STOP_WATCH_DISABLED ((uint32_t)0x00000000U)

Stop Watch disabled

Definition at line 1392 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U)

Actual value of global time is copied to Capture Time register (TTCPT.SWV)

Definition at line 1395 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_STOP_WATCH_LOCAL_TIME ((uint32_t)0x00000010U)

Actual value of local time is copied to Capture Time register (TTCPT.SWV)

Definition at line 1394 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN TT Stop Watch Polarity

Defines
FDCAN TT Stop Watch Polarity
FDCAN Exported Constants

Defines

#define | FDCAN_TT_STOP_WATCH_RISING ((uint32_t)0x00000000U)
#define | FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U)

Define Documentation

#define FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U)

Selected stop watch source is captured at falling edge of fdcan1_swt

Definition at line 1404 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_STOP_WATCH_RISING ((uint32_t)0x00000000U)

Selected stop watch source is captured at rising edge of fdcan1_swt

Definition at line 1403 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN TT Time Mark Source

Defines
FDCAN TT Time Mark Source
FDCAN Exported Constants

Defines

#define | FDCAN_TT_REG_TIMEMARK_DIABLED ((uint32_t)0x00000000U)
#define | FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U)
#define | FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U)
#define | FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U)

Define Documentation

#define FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U)

Register Time Mark Interrupt if Time Mark = cycle time

Definition at line 1413 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_REG_TIMEMARK_DIABLED ((uint32_t)0x00000000U)

No Register Time Mark Interrupt generated

Definition at line 1412 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigRegisterTimeMark().

#define FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U)

Register Time Mark Interrupt if Time Mark = global time

Definition at line 1415 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U)

Register Time Mark Interrupt if Time Mark = local time

Definition at line 1414 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN TT Error Level

Defines
FDCAN TT Error Level
FDCAN Exported Constants

Defines

#define | FDCAN_TT_NO_ERROR ((uint32_t)0x00000000U)
#define | FDCAN_TT_WARNING ((uint32_t)0x00000001U)
#define | FDCAN_TT_ERROR ((uint32_t)0x00000002U)
#define | FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U)

Define Documentation

#define FDCAN_TT_ERROR ((uint32_t)0x00000002U)

Severity 2 - Error

Definition at line 1425 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_NO_ERROR ((uint32_t)0x00000000U)

Severity 0 - No Error

Definition at line 1423 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U)

Severity 3 - Severe Error

Definition at line 1426 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_WARNING ((uint32_t)0x00000001U)

Severity 1 - Warning

Definition at line 1424 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN TT Master State

Defines
FDCAN TT Master State
FDCAN Exported Constants

Defines

#define | FDCAN_TT_MASTER_OFF ((uint32_t)0x00000000U)
#define | FDCAN_TT_TIME_SLAVE ((uint32_t)0x00000004U)
#define | FDCAN_TT_BACKUP_TIME_MASTER ((uint32_t)0x00000008U)
#define | FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU)

Define Documentation

#define FDCAN_TT_BACKUP_TIME_MASTER ((uint32_t)0x00000008U)

Operating as Backup Time Master

Definition at line 1436 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU)

Operating as current Time Master

Definition at line 1437 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_MASTER_OFF ((uint32_t)0x00000000U)

Master_Off, no master properties relevant

Definition at line 1434 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_TIME_SLAVE ((uint32_t)0x00000004U)

Operating as Time Slave

Definition at line 1435 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN TT Synchronization State

Defines
FDCAN TT Synchronization State
FDCAN Exported Constants

Defines

#define | FDCAN_TT_OUT_OF_SYNC ((uint32_t)0x00000000U)
#define | FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U)
#define | FDCAN_TT_IN_GAP ((uint32_t)0x00000020U)
#define | FDCAN_TT_IN_SCHEDULE ((uint32_t)0x00000030U)

Define Documentation

#define FDCAN_TT_IN_GAP ((uint32_t)0x00000020U)

Schedule suspended by Gap

Definition at line 1447 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IN_SCHEDULE ((uint32_t)0x00000030U)

Synchronized to schedule

Definition at line 1448 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_OUT_OF_SYNC ((uint32_t)0x00000000U)

Out of Synchronization

Definition at line 1445 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U)

Synchronizing to communication

Definition at line 1446 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: Interrupt masks

Defines
Interrupt masks
FDCAN Exported Constants

Defines

#define | FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU)
#define | CCU_IR_MASK ((uint32_t)0xC0000000U)

Define Documentation

#define CCU_IR_MASK ((uint32_t)0xC0000000U)

CCU interrupts mask

Definition at line 1457 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU)

FDCAN interrupts mask

Definition at line 1456 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN Flags

Defines
FDCAN Flags
FDCAN Exported Constants

Defines

#define | FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC
#define | FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF
#define | FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE
#define | FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM
#define | FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE FDCAN_IR_DRX
#define | FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL
#define | FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF
#define | FDCAN_FLAG_TX_EVT_FIFO_WATERMARK FDCAN_IR_TEFW
#define | FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN
#define | FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L
#define | FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F
#define | FDCAN_FLAG_RX_FIFO0_WATERMARK FDCAN_IR_RF0W
#define | FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N
#define | FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L
#define | FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F
#define | FDCAN_FLAG_RX_FIFO1_WATERMARK FDCAN_IR_RF1W
#define | FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N
#define | FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF
#define | FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO
#define | FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP
#define | FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW
#define | FDCAN_FLAG_BUS_OFF FDCAN_IR_BO
#define | FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI
#define | FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA
#define | FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED
#define | FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA
#define | FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW
#define | FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO
#define | FDCAN_FLAG_CALIB_STATE_CHANGED (FDCANCCU_IR_CSC << 30)
#define | FDCAN_FLAG_CALIB_WATCHDOG_EVENT (FDCANCCU_IR_CWE << 30)

Define Documentation

#define FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA

Protocol error in arbitration phase detected

Definition at line 1488 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_BUS_OFF FDCAN_IR_BO

Bus_Off status changed

Definition at line 1486 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_CALIB_STATE_CHANGED (FDCANCCU_IR_CSC << 30)

Clock calibration state changed

Definition at line 1493 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_CALIB_WATCHDOG_EVENT (FDCANCCU_IR_CWE << 30)

Clock calibration watchdog event occurred

Definition at line 1494 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED

Protocol error in data phase detected

Definition at line 1489 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO

Overflow of FDCAN Error Logging Counter occurred

Definition at line 1483 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP

Error_Passive status changed

Definition at line 1484 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW

Error_Warning status changed

Definition at line 1485 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF

Message RAM access failure occurred

Definition at line 1482 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI

Message RAM Watchdog event due to missing READY

Definition at line 1487 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA

Access to reserved address occurred

Definition at line 1490 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE FDCAN_IR_DRX

At least one received message stored into a Rx Buffer

Definition at line 1469 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F

Rx FIFO 0 full

Definition at line 1475 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L

Rx FIFO 0 message lost

Definition at line 1474 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N

New message written to Rx FIFO 0

Definition at line 1477 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO0_WATERMARK FDCAN_IR_RF0W

Rx FIFO 0 fill level reached watermark

Definition at line 1476 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F

Rx FIFO 1 full

Definition at line 1479 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L

Rx FIFO 1 message lost

Definition at line 1478 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N

New message written to Rx FIFO 1

Definition at line 1481 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO1_WATERMARK FDCAN_IR_RF1W

Rx FIFO 1 fill level reached watermark

Definition at line 1480 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM

High priority message received

Definition at line 1468 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO

Timeout reached

Definition at line 1492 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW

Timestamp counter wrapped around

Definition at line 1491 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF

Transmission Cancellation Finished

Definition at line 1466 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC

Transmission Completed

Definition at line 1465 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL

Tx Event FIFO element lost

Definition at line 1470 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF

Tx Event FIFO full

Definition at line 1471 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN

Tx Handler wrote Tx Event FIFO element

Definition at line 1473 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK FDCAN_IR_TEFW

Tx Event FIFO fill level reached watermark

Definition at line 1472 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE

Tx FIFO Empty

Definition at line 1467 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

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STM32H753xx HAL User Manual: FDCAN Tx Interrupts

Defines
FDCAN Tx Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE
#define | FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE
#define | FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE

Define Documentation

#define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE

Transmission Cancellation Finished

Definition at line 1507 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_IRQHandler().

#define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE

Transmission Completed

Definition at line 1506 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_IRQHandler().

#define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE

Tx FIFO Empty

Definition at line 1508 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

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STM32H753xx HAL User Manual: FDCAN Rx Interrupts

Defines
FDCAN Rx Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME
#define | FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE

Define Documentation

#define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE

At least one received message stored into a Rx Buffer

Definition at line 1517 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME

High priority message received

Definition at line 1516 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Counter Interrupts

Defines
FDCAN Counter Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE
#define | FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE

Define Documentation

#define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE

Timeout reached

Definition at line 1526 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE

Timestamp counter wrapped around

Definition at line 1525 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

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STM32H753xx HAL User Manual: Clock Calibration Interrupts

Defines
Clock Calibration Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_CALIB_STATE_CHANGED (FDCANCCU_IE_CSCE << 30)
#define | FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30)

Define Documentation

#define FDCAN_IT_CALIB_STATE_CHANGED (FDCANCCU_IE_CSCE << 30)

Clock calibration state changed

Definition at line 1534 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30)

Clock calibration watchdog event occurred

Definition at line 1535 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN Tx Event FIFO Interrupts

Defines
FDCAN Tx Event FIFO Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE
#define | FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE
#define | FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE
#define | FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE

Define Documentation

#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE

Tx Event FIFO element lost

Definition at line 1543 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE

Tx Event FIFO full

Definition at line 1544 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE

Tx Handler wrote Tx Event FIFO element

Definition at line 1546 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE

Tx Event FIFO fill level reached watermark

Definition at line 1545 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN Rx FIFO 0 Interrupts

Defines
FDCAN Rx FIFO 0 Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE
#define | FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE
#define | FDCAN_IT_RX_FIFO0_WATERMARK FDCAN_IE_RF0WE
#define | FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE

Define Documentation

#define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE

Rx FIFO 0 full

Definition at line 1555 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE

Rx FIFO 0 message lost

Definition at line 1554 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE

New message written to Rx FIFO 0

Definition at line 1557 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_RX_FIFO0_WATERMARK FDCAN_IE_RF0WE

Rx FIFO 0 fill level reached watermark

Definition at line 1556 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN Rx FIFO 1 Interrupts

Defines
FDCAN Rx FIFO 1 Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE
#define | FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE
#define | FDCAN_IT_RX_FIFO1_WATERMARK FDCAN_IE_RF1WE
#define | FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE

Define Documentation

#define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE

Rx FIFO 1 full

Definition at line 1566 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE

Rx FIFO 1 message lost

Definition at line 1565 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE

New message written to Rx FIFO 1

Definition at line 1568 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_RX_FIFO1_WATERMARK FDCAN_IE_RF1WE

Rx FIFO 1 fill level reached watermark

Definition at line 1567 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN Error Interrupts

Defines
FDCAN Error Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE
#define | FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE
#define | FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE
#define | FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE
#define | FDCAN_IT_BUS_OFF FDCAN_IE_BOE
#define | FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE
#define | FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE
#define | FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE
#define | FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE

Define Documentation

#define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE

Protocol error in arbitration phase detected

Definition at line 1582 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_BUS_OFF FDCAN_IE_BOE

Bus_Off status changed

Definition at line 1580 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE

Protocol error in data phase detected

Definition at line 1583 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE

Overflow of FDCAN Error Logging Counter occurred

Definition at line 1577 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE

Error_Passive status changed

Definition at line 1578 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE

Error_Warning status changed

Definition at line 1579 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE

Message RAM access failure occurred

Definition at line 1576 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE

Message RAM Watchdog event due to missing READY

Definition at line 1581 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE

Access to reserved address occurred

Definition at line 1584 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN TT Flags

Defines
FDCAN TT Flags
FDCAN Exported Constants

Defines

#define | FDCAN_TT_FLAG_BASIC_CYCLE_START FDCAN_TTIR_SBC
#define | FDCAN_TT_FLAG_MATRIX_CYCLE_START FDCAN_TTIR_SMC
#define | FDCAN_TT_FLAG_SYNC_MODE_CHANGE FDCAN_TTIR_CSM
#define | FDCAN_TT_FLAG_START_OF_GAP FDCAN_TTIR_SOG
#define | FDCAN_TT_FLAG_REG_TIME_MARK FDCAN_TTIR_RTMI
#define | FDCAN_TT_FLAG_TRIG_TIME_MARK FDCAN_TTIR_TTMI
#define | FDCAN_TT_FLAG_STOP_WATCH FDCAN_TTIR_SWE
#define | FDCAN_TT_FLAG_GLOBAL_TIME_WRAP FDCAN_TTIR_GTW
#define | FDCAN_TT_FLAG_GLOBAL_TIME_DISC FDCAN_TTIR_GTD
#define | FDCAN_TT_FLAG_GLOBAL_TIME_ERROR FDCAN_TTIR_GTE
#define | FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW FDCAN_TTIR_TXU
#define | FDCAN_TT_FLAG_TX_COUNT_OVERFLOW FDCAN_TTIR_TXO
#define | FDCAN_TT_FLAG_SCHEDULING_ERROR_1 FDCAN_TTIR_SE1
#define | FDCAN_TT_FLAG_SCHEDULING_ERROR_2 FDCAN_TTIR_SE2
#define | FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE FDCAN_TTIR_ELC
#define | FDCAN_TT_FLAG_INIT_WATCH_TRIGGER FDCAN_TTIR_IWT
#define | FDCAN_TT_FLAG_WATCH_TRIGGER FDCAN_TTIR_WT
#define | FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW
#define | FDCAN_TT_FLAG_CONFIG_ERROR FDCAN_TTIR_CER

Define Documentation

#define FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW

Application Watchdog

Definition at line 1613 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_BASIC_CYCLE_START FDCAN_TTIR_SBC

Start of Basic Cycle

Definition at line 1596 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_CONFIG_ERROR FDCAN_TTIR_CER

Configuration Error

Definition at line 1614 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE FDCAN_TTIR_ELC

Error Level Changed

Definition at line 1610 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_GLOBAL_TIME_DISC FDCAN_TTIR_GTD

Global Time Discontinuity

Definition at line 1604 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR FDCAN_TTIR_GTE

Global Time Error

Definition at line 1605 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP FDCAN_TTIR_GTW

Global Time Wrap

Definition at line 1603 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER FDCAN_TTIR_IWT

Initialization Watch Trigger

Definition at line 1611 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_MATRIX_CYCLE_START FDCAN_TTIR_SMC

Start of Matrix Cycle

Definition at line 1597 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_REG_TIME_MARK FDCAN_TTIR_RTMI

Register Time Mark Interrupt

Definition at line 1600 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_SCHEDULING_ERROR_1 FDCAN_TTIR_SE1

Scheduling Error 1

Definition at line 1608 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_SCHEDULING_ERROR_2 FDCAN_TTIR_SE2

Scheduling Error 2

Definition at line 1609 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_START_OF_GAP FDCAN_TTIR_SOG

Start of Gap

Definition at line 1599 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_STOP_WATCH FDCAN_TTIR_SWE

Stop Watch Event

Definition at line 1602 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_TT_FLAG_SYNC_MODE_CHANGE FDCAN_TTIR_CSM

Change of Synchronization Mode

Definition at line 1598 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_TRIG_TIME_MARK FDCAN_TTIR_TTMI

Trigger Time Mark Event Internal

Definition at line 1601 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW FDCAN_TTIR_TXO

Tx Count Overflow

Definition at line 1607 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW FDCAN_TTIR_TXU

Tx Count Underflow

Definition at line 1606 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_FLAG_WATCH_TRIGGER FDCAN_TTIR_WT

Watch Trigger

Definition at line 1612 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN TT Schedule Synchronization Interrupts

Defines
FDCAN TT Schedule Synchronization Interrupts
FDCAN TT Interrupts

Defines

#define | FDCAN_TT_IT_BASIC_CYCLE_START FDCAN_TTIE_SBCE
#define | FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE
#define | FDCAN_TT_IT_SYNC_MODE_CHANGE FDCAN_TTIE_CSME
#define | FDCAN_TT_IT_START_OF_GAP FDCAN_TTIE_SOGE

Define Documentation

#define FDCAN_TT_IT_BASIC_CYCLE_START FDCAN_TTIE_SBCE

Start of Basic Cycle

Definition at line 1626 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE

Start of Matrix Cycle

Definition at line 1627 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_START_OF_GAP FDCAN_TTIE_SOGE

Start of Gap

Definition at line 1629 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_SYNC_MODE_CHANGE FDCAN_TTIE_CSME

Change of Synchronization Mode

Definition at line 1628 of file stm32h7xx_hal_fdcan.h.

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STM32H753xx HAL User Manual: FDCAN TT Time Mark Interrupts

Defines
FDCAN TT Time Mark Interrupts
FDCAN TT Interrupts

Defines

#define | FDCAN_TT_IT_REG_TIME_MARK FDCAN_TTIE_RTMIE
#define | FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE

Define Documentation

#define FDCAN_TT_IT_REG_TIME_MARK FDCAN_TTIE_RTMIE

Register Time Mark Interrupt

Definition at line 1637 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE

Trigger Time Mark Event Internal

Definition at line 1638 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN TT Stop Watch Interrupt

Defines
FDCAN TT Stop Watch Interrupt
FDCAN TT Interrupts

Defines

#define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE

Define Documentation

#define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE

Stop Watch Event

Definition at line 1646 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN TT Global Time Interrupts

Defines
FDCAN TT Global Time Interrupts
FDCAN TT Interrupts

Defines

#define | FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE
#define | FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE

Define Documentation

#define FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE

Global Time Discontinuity

Definition at line 1655 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE

Global Time Wrap

Definition at line 1654 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN TT Disturbing Error Interrupts

Defines
FDCAN TT Disturbing Error Interrupts
FDCAN TT Interrupts

Defines

#define | FDCAN_TT_IT_GLOBAL_TIME_ERROR FDCAN_TTIE_GTEE
#define | FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE
#define | FDCAN_TT_IT_TX_COUNT_OVERFLOW FDCAN_TTIE_TXOE
#define | FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E
#define | FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E
#define | FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE

Define Documentation

#define FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE

Error Level Changed

Definition at line 1668 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_GLOBAL_TIME_ERROR FDCAN_TTIE_GTEE

Global Time Error

Definition at line 1663 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E

Scheduling Error 1

Definition at line 1666 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E

Scheduling Error 2

Definition at line 1667 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_TX_COUNT_OVERFLOW FDCAN_TTIE_TXOE

Tx Count Overflow

Definition at line 1665 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE

Tx Count Underflow

Definition at line 1664 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN TT Fatal Error Interrupts

Defines
FDCAN TT Fatal Error Interrupts
FDCAN TT Interrupts

Defines

#define | FDCAN_TT_IT_INIT_WATCH_TRIGGER FDCAN_TTIE_IWTE
#define | FDCAN_TT_IT_WATCH_TRIGGER FDCAN_TTIE_WTE
#define | FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE
#define | FDCAN_TT_IT_CONFIG_ERROR FDCAN_TTIE_CERE

Define Documentation

#define FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE

Application Watchdog

Definition at line 1678 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_CONFIG_ERROR FDCAN_TTIE_CERE

Configuration Error

Definition at line 1679 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_INIT_WATCH_TRIGGER FDCAN_TTIE_IWTE

Initialization Watch Trigger

Definition at line 1676 of file stm32h7xx_hal_fdcan.h.

#define FDCAN_TT_IT_WATCH_TRIGGER FDCAN_TTIE_WTE

Watch Trigger

Definition at line 1677 of file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Exported Macros

Defines
FDCAN Exported Macros
FDCAN

Defines

#define | __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
Reset FDCAN handle state.
#define | __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified FDCAN interrupts.
#define | __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified FDCAN interrupts.
#define | __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
Check whether the specified FDCAN interrupt is set or not.
#define | __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__)
Clear the specified FDCAN interrupts.
#define | __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
Check whether the specified FDCAN flag is set or not.
#define | __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the specified FDCAN flags.
#define | __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__)))
Check if the specified FDCAN interrupt source is enabled or disabled.
#define | __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__))
Enable the specified FDCAN TT interrupts.
#define | __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__))
Disable the specified FDCAN TT interrupts.
#define | __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__))
Check whether the specified FDCAN TT interrupt is set or not.
#define | __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__))
Clear the specified FDCAN TT interrupts.
#define | __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__))
Check whether the specified FDCAN TT flag is set or not.
#define | __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__))
Clear the specified FDCAN TT flags.
#define | __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__))
Check if the specified FDCAN TT interrupt source is enabled or disabled.

Define Documentation

#define __HAL_FDCAN_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
do{                                                              \
    ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \
    FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30);          \
  }while(0)

Clear the specified FDCAN flags.

Parameters:
__HANDLE__,: FDCAN handle.
__FLAG__,: specifies the flags to clear. This parameter can be any combination of
  • FDCAN_flags
Return values:
None

Definition at line 1768 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define __HAL_FDCAN_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
do{                                                              \
    ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \
    FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
  }while(0)

Clear the specified FDCAN interrupts.

Parameters:
__HANDLE__,: FDCAN handle.
__INTERRUPT__,: specifies the interrupts to clear. This parameter can be any combination of
  • FDCAN_Interrupts
Return values:
None

Definition at line 1746 of file stm32h7xx_hal_fdcan.h.

#define __HAL_FDCAN_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
do{                                                                   \
    ((__HANDLE__)->Instance->IE) &= ~((__INTERRUPT__) & FDCAN_IR_MASK); \
    FDCAN_CCU->IE &= ~(((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
  }while(0)

Disable the specified FDCAN interrupts.

Parameters:
__HANDLE__,: FDCAN handle.
__INTERRUPT__,: FDCAN interrupt. This parameter can be any combination of
  • FDCAN_Interrupts
Return values:
None

Definition at line 1724 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_DeactivateNotification(), and HAL_FDCAN_IRQHandler().

#define __HAL_FDCAN_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
do{                                                                \
    (__HANDLE__)->Instance->IE |= ((__INTERRUPT__) & FDCAN_IR_MASK); \
    FDCAN_CCU->IE |= (((__INTERRUPT__) & CCU_IR_MASK) >> 30);        \
  }while(0)

Enable the specified FDCAN interrupts.

Parameters:
__HANDLE__,: FDCAN handle.
__INTERRUPT__,: FDCAN interrupt. This parameter can be any combination of
  • FDCAN_Interrupts
Return values:
None

Definition at line 1710 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification().

#define __HAL_FDCAN_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))

Check whether the specified FDCAN flag is set or not.

Parameters:
__HANDLE__,: FDCAN handle.
__FLAG__,: FDCAN flag. This parameter can be one of
  • FDCAN_flags
Return values:
None

Definition at line 1759 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define __HAL_FDCAN_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))

Check whether the specified FDCAN interrupt is set or not.

Parameters:
__HANDLE__,: FDCAN handle.
__INTERRUPT__,: FDCAN interrupt. This parameter can be one of
  • FDCAN_Interrupts
Return values:
None

Definition at line 1737 of file stm32h7xx_hal_fdcan.h.

#define __HAL_FDCAN_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__)))

Check if the specified FDCAN interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: FDCAN handle.
__INTERRUPT__,: specifies the FDCAN interrupt source to check. This parameter can be a value of
  • FDCAN_Interrupts
Return values:
None

Definition at line 1780 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define __HAL_FDCAN_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)

Reset FDCAN handle state.

Parameters:
__HANDLE__,: FDCAN handle.
Return values:
None

Definition at line 1701 of file stm32h7xx_hal_fdcan.h.

#define __HAL_FDCAN_TT_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->ttcan->TTIR) = (__FLAG__))

Clear the specified FDCAN TT flags.

Parameters:
__HANDLE__,: FDCAN handle.
__FLAG__,: specifies the TT flags to clear. This parameter can be any combination of
  • FDCAN_TTflags
Return values:
None

Definition at line 1834 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define __HAL_FDCAN_TT_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__))

Clear the specified FDCAN TT interrupts.

Parameters:
__HANDLE__,: FDCAN handle.
__INTERRUPT__,: specifies the TT interrupts to clear. This parameter can be any combination of
  • FDCAN_TTInterrupts
Return values:
None

Definition at line 1816 of file stm32h7xx_hal_fdcan.h.

#define __HAL_FDCAN_TT_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__))

Disable the specified FDCAN TT interrupts.

Parameters:
__HANDLE__,: FDCAN handle.
__INTERRUPT__,: FDCAN TT interrupt. This parameter can be any combination of
  • FDCAN_TTInterrupts
Return values:
None

Definition at line 1798 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler(), and HAL_FDCAN_TT_DeactivateNotification().

#define __HAL_FDCAN_TT_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__))

Enable the specified FDCAN TT interrupts.

Parameters:
__HANDLE__,: FDCAN handle.
__INTERRUPT__,: FDCAN TT interrupt. This parameter can be any combination of
  • FDCAN_TTInterrupts
Return values:
None

Definition at line 1789 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ActivateNotification().

#define __HAL_FDCAN_TT_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->ttcan->TTIR) & (__FLAG__))

Check whether the specified FDCAN TT flag is set or not.

Parameters:
__HANDLE__,: FDCAN handle.
__FLAG__,: FDCAN TT flag. This parameter can be one of
  • FDCAN_TTflags
Return values:
None

Definition at line 1825 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define __HAL_FDCAN_TT_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__))

Check whether the specified FDCAN TT interrupt is set or not.

Parameters:
__HANDLE__,: FDCAN handle.
__INTERRUPT__,: FDCAN TT interrupt. This parameter can be one of
  • FDCAN_TTInterrupts
Return values:
None

Definition at line 1807 of file stm32h7xx_hal_fdcan.h.

#define __HAL_FDCAN_TT_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__))

Check if the specified FDCAN TT interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: FDCAN handle.
__INTERRUPT__,: specifies the FDCAN TT interrupt source to check. This parameter can be a value of
  • FDCAN_TTInterrupts
Return values:
None

Definition at line 1842 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Private Types

FDCAN Private Types
FDCAN
Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Private Variables

FDCAN Private Variables
FDCAN
Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Private Constants

Defines
FDCAN Private Constants
FDCAN

Defines

#define | FDCAN_TIMEOUT_VALUE 10
#define | FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFW | FDCAN_IR_TEFN)
#define | FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0W | FDCAN_IR_RF0N)
#define | FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1W | FDCAN_IR_RF1N)
#define | FDCAN_ERROR_MASK
#define | FDCAN_TT_SCHEDULE_SYNC_MASK (FDCAN_TTIR_SBC | FDCAN_TTIR_SMC | FDCAN_TTIR_CSM | FDCAN_TTIR_SOG)
#define | FDCAN_TT_TIME_MARK_MASK (FDCAN_TTIR_RTMI | FDCAN_TTIR_TTMI)
#define | FDCAN_TT_GLOBAL_TIME_MASK (FDCAN_TTIR_GTW | FDCAN_TTIR_GTD)
#define | FDCAN_TT_DISTURBING_ERROR_MASK
#define | FDCAN_TT_FATAL_ERROR_MASK (FDCAN_TTIR_IWT | FDCAN_TTIR_WT | FDCAN_TTIR_AW | FDCAN_TTIR_CER)
#define | FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */
#define | FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */
#define | FDCAN_ELEMENT_MASK_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */
#define | FDCAN_ELEMENT_MASK_XTD ((uint32_t)0x40000000U) /* Extended Identifier */
#define | FDCAN_ELEMENT_MASK_ESI ((uint32_t)0x80000000U) /* Error State Indicator */
#define | FDCAN_ELEMENT_MASK_TS ((uint32_t)0x0000FFFFU) /* Timestamp */
#define | FDCAN_ELEMENT_MASK_DLC ((uint32_t)0x000F0000U) /* Data Length Code */
#define | FDCAN_ELEMENT_MASK_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */
#define | FDCAN_ELEMENT_MASK_FDF ((uint32_t)0x00200000U) /* FD Format */
#define | FDCAN_ELEMENT_MASK_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */
#define | FDCAN_ELEMENT_MASK_MM ((uint32_t)0xFF000000U) /* Message Marker */
#define | FDCAN_ELEMENT_MASK_FIDX ((uint32_t)0x7F000000U) /* Filter Index */
#define | FDCAN_ELEMENT_MASK_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
#define | FDCAN_ELEMENT_MASK_ET ((uint32_t)0x00C00000U) /* Event type */

Define Documentation

#define FDCAN_ELEMENT_MASK_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */

Definition at line 163 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage().

#define FDCAN_ELEMENT_MASK_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */

Definition at line 158 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_DLC ((uint32_t)0x000F0000U) /* Data Length Code */

Definition at line 157 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */

Definition at line 160 of file stm32h7xx_hal_fdcan.c.

#define FDCAN_ELEMENT_MASK_ESI ((uint32_t)0x80000000U) /* Error State Indicator */

Definition at line 155 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_ET ((uint32_t)0x00C00000U) /* Event type */

Definition at line 164 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */

Definition at line 152 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_FDF ((uint32_t)0x00200000U) /* FD Format */

Definition at line 159 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_FIDX ((uint32_t)0x7F000000U) /* Filter Index */

Definition at line 162 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage().

#define FDCAN_ELEMENT_MASK_MM ((uint32_t)0xFF000000U) /* Message Marker */

Definition at line 161 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */

Definition at line 153 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */

Definition at line 151 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_TS ((uint32_t)0x0000FFFFU) /* Timestamp */

Definition at line 156 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_XTD ((uint32_t)0x40000000U) /* Extended Identifier */

Definition at line 154 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ERROR_MASK
Value:
(FDCAN_IR_ELO | FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO | \
                          FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)

Definition at line 142 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0W | FDCAN_IR_RF0N)

Definition at line 140 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1W | FDCAN_IR_RF1N)

Definition at line 141 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_TIMEOUT_VALUE 10

Definition at line 137 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_Init(), HAL_FDCAN_Stop(), HAL_FDCAN_TT_ConfigOperation(), HAL_FDCAN_TT_ConfigRegisterTimeMark(), HAL_FDCAN_TT_ConfigStopWatch(), HAL_FDCAN_TT_DisableExternalSynchronization(), HAL_FDCAN_TT_DisableHardwareGapControl(), HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(), HAL_FDCAN_TT_DisableTimeMarkGapControl(), HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(), HAL_FDCAN_TT_EnableExternalSynchronization(), HAL_FDCAN_TT_EnableHardwareGapControl(), HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(), HAL_FDCAN_TT_EnableTimeMarkGapControl(), HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(), HAL_FDCAN_TT_SetClockSynchronization(), HAL_FDCAN_TT_SetEndOfGap(), HAL_FDCAN_TT_SetGlobalTime(), and HAL_FDCAN_TT_SetNextIsGap().

#define FDCAN_TT_DISTURBING_ERROR_MASK
Value:
(FDCAN_TTIR_GTE | FDCAN_TTIR_TXU | FDCAN_TTIR_TXO | \
                                        FDCAN_TTIR_SE1 | FDCAN_TTIR_SE2 | FDCAN_TTIR_ELC)

Definition at line 147 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_TT_FATAL_ERROR_MASK (FDCAN_TTIR_IWT | FDCAN_TTIR_WT | FDCAN_TTIR_AW | FDCAN_TTIR_CER)

Definition at line 149 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_TT_GLOBAL_TIME_MASK (FDCAN_TTIR_GTW | FDCAN_TTIR_GTD)

Definition at line 146 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_TT_SCHEDULE_SYNC_MASK (FDCAN_TTIR_SBC | FDCAN_TTIR_SMC | FDCAN_TTIR_CSM | FDCAN_TTIR_SOG)

Definition at line 144 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_TT_TIME_MARK_MASK (FDCAN_TTIR_RTMI | FDCAN_TTIR_TTMI)

Definition at line 145 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFW | FDCAN_IR_TEFN)

Definition at line 139 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Private Macros

Defines
FDCAN Private Macros
FDCAN

Defines

#define | IS_FDCAN_FRAME_FORMAT(FORMAT)
#define | IS_FDCAN_MODE(MODE)
#define | IS_FDCAN_CKDIV(CKDIV)
#define | IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 512))
#define | IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1) && ((SJW) <= 128))
#define | IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 2) && ((TSEG1) <= 256))
#define | IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 2) && ((TSEG2) <= 128))
#define | IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 32))
#define | IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1) && ((SJW) <= 16))
#define | IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1) && ((TSEG1) <= 32))
#define | IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1) && ((TSEG2) <= 16))
#define | IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX))
#define | IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN))
#define | IS_FDCAN_DATA_SIZE(SIZE)
#define | IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE)
#define | IS_FDCAN_ID_TYPE(ID_TYPE)
#define | IS_FDCAN_FILTER_CFG(CONFIG)
#define | IS_FDCAN_TX_LOCATION(LOCATION)
#define | IS_FDCAN_RX_FIFO(FIFO)
#define | IS_FDCAN_RX_FIFO_MODE(MODE)
#define | IS_FDCAN_STD_FILTER_TYPE(TYPE)
#define | IS_FDCAN_EXT_FILTER_TYPE(TYPE)
#define | IS_FDCAN_FRAME_TYPE(TYPE)
#define | IS_FDCAN_DLC(DLC)
#define | IS_FDCAN_ESI(ESI)
#define | IS_FDCAN_BRS(BRS)
#define | IS_FDCAN_FDF(FDF)
#define | IS_FDCAN_EFC(EFC)
#define | IS_FDCAN_IT(IT) (((IT) & 0xC0300000U) == RESET)
#define | IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == RESET)
#define | IS_FDCAN_FIFO_WATERMARK(FIFO)
#define | IS_FDCAN_NON_MATCHING(DESTINATION)
#define | IS_FDCAN_IT_LINE(IT_LINE)
#define | IS_FDCAN_TIMESTAMP(OPERATION)
#define | IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER)
#define | IS_FDCAN_TIMEOUT(OPERATION)
#define | IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH)
#define | IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD)
#define | IS_FDCAN_TT_REPEAT_FACTOR(FACTOR)
#define | IS_FDCAN_TT_TRIGGER_TYPE(TYPE)
#define | IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT)
#define | IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT)
#define | IS_FDCAN_OPERATION_MODE(MODE)
#define | IS_FDCAN_TT_OPERATION(OPERATION)
#define | IS_FDCAN_TT_TIME_MASTER(FUNCTION)
#define | IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC)
#define | IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING)
#define | IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION)
#define | IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY)
#define | IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER)
#define | IS_FDCAN_TT_CYCLE_START_SYNC(SYNC)
#define | IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1) && ((NTU) <= 16))
#define | IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000) && ((NUMERATOR) <= 0x1FFFF))
#define | IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001) && ((DENOMINATOR) <= 0x3FFF))
#define | IS_FDCAN_TT_TUR_LEVEL_1(NC, DC) ((NC) >= (4 * (DC)))
#define | IS_FDCAN_TT_TUR_LEVEL_0_2(NC, DC) ((NC) >= (8 * (DC)))
#define | IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER)
#define | IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER)
#define | IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFF) && ((TIME) != 0x8000))
#define | IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE)
#define | IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY)
#define | IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE)

Define Documentation

#define IS_FDCAN_BRS ( BRS )
Value:
(((BRS) == FDCAN_BRS_OFF) || \
                           ((BRS) == FDCAN_BRS_ON ))

Definition at line 2137 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_CALIBRATION_FIELD_LENGTH ( LENGTH )
Value:
(((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_32) || \
                                                   ((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_64))

Definition at line 2175 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration().

#define IS_FDCAN_CKDIV ( CKDIV )
Value:
(((CKDIV) == FDCAN_CLOCK_DIV1 ) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV10) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV12) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV14) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV16) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV18) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV20) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV22) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV24) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV26) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV28) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV30))

Definition at line 2044 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration().

#define IS_FDCAN_DATA_PRESCALER ( PRESCALER ) (((PRESCALER) >= 1) && ((PRESCALER) <= 32))

Definition at line 2064 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_DATA_SIZE ( SIZE )
Value:
(((SIZE) == FDCAN_DATA_BYTES_8 ) || \
                                  ((SIZE) == FDCAN_DATA_BYTES_12) || \
                                  ((SIZE) == FDCAN_DATA_BYTES_16) || \
                                  ((SIZE) == FDCAN_DATA_BYTES_20) || \
                                  ((SIZE) == FDCAN_DATA_BYTES_24) || \
                                  ((SIZE) == FDCAN_DATA_BYTES_32) || \
                                  ((SIZE) == FDCAN_DATA_BYTES_48) || \
                                  ((SIZE) == FDCAN_DATA_BYTES_64))

Definition at line 2070 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_DATA_SJW ( SJW ) (((SJW) >= 1) && ((SJW) <= 16))

Definition at line 2065 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_DATA_TSEG1 ( TSEG1 ) (((TSEG1) >= 1) && ((TSEG1) <= 32))

Definition at line 2066 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_DATA_TSEG2 ( TSEG2 ) (((TSEG2) >= 1) && ((TSEG2) <= 16))

Definition at line 2067 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_DLC ( DLC )
Value:
(((DLC) == FDCAN_DLC_BYTES_0 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_1 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_2 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_3 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_4 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_5 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_6 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_7 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_8 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_12) || \
                           ((DLC) == FDCAN_DLC_BYTES_16) || \
                           ((DLC) == FDCAN_DLC_BYTES_20) || \
                           ((DLC) == FDCAN_DLC_BYTES_24) || \
                           ((DLC) == FDCAN_DLC_BYTES_32) || \
                           ((DLC) == FDCAN_DLC_BYTES_48) || \
                           ((DLC) == FDCAN_DLC_BYTES_64))

Definition at line 2119 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_EFC ( EFC )
Value:
(((EFC) == FDCAN_NO_TX_EVENTS   ) || \
                           ((EFC) == FDCAN_STORE_TX_EVENTS))

Definition at line 2141 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_ESI ( ESI )
Value:
(((ESI) == FDCAN_ESI_ACTIVE ) || \
                           ((ESI) == FDCAN_ESI_PASSIVE))

Definition at line 2135 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_EXT_FILTER_TYPE ( TYPE )
Value:
(((TYPE) == FDCAN_FILTER_RANGE        ) || \
                                        ((TYPE) == FDCAN_FILTER_DUAL         ) || \
                                        ((TYPE) == FDCAN_FILTER_MASK         ) || \
                                        ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))

Definition at line 2113 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

#define IS_FDCAN_FDF ( FDF )
Value:
(((FDF) == FDCAN_CLASSIC_CAN) || \
                           ((FDF) == FDCAN_FD_CAN     ))

Definition at line 2139 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_FIFO_WATERMARK ( FIFO )
Value:
(((FIFO) == FDCAN_CFG_TX_EVENT_FIFO) || \
                                       ((FIFO) == FDCAN_CFG_RX_FIFO0     ) || \
                                       ((FIFO) == FDCAN_CFG_RX_FIFO1     ))

Definition at line 2145 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFifoWatermark().

#define IS_FDCAN_FILTER_CFG ( CONFIG )
Value:
(((CONFIG) == FDCAN_FILTER_DISABLE      ) || \
                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0   ) || \
                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1   ) || \
                                     ((CONFIG) == FDCAN_FILTER_REJECT       ) || \
                                     ((CONFIG) == FDCAN_FILTER_HP           ) || \
                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP) || \
                                     ((CONFIG) == FDCAN_FILTER_TO_RXBUFFER  ))

Definition at line 2082 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

#define IS_FDCAN_FRAME_FORMAT ( FORMAT )
Value:
(((FORMAT) == FDCAN_FRAME_CLASSIC  ) || \
                                       ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
                                       ((FORMAT) == FDCAN_FRAME_FD_BRS   ))

Definition at line 2036 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_FRAME_TYPE ( TYPE )
Value:
(((TYPE) == FDCAN_DATA_FRAME  ) || \
                                   ((TYPE) == FDCAN_REMOTE_FRAME))

Definition at line 2117 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_ID_TYPE ( ID_TYPE )
Value:
(((ID_TYPE) == FDCAN_STANDARD_ID) || \
                                   ((ID_TYPE) == FDCAN_EXTENDED_ID))

Definition at line 2080 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_TT_ConfigReferenceMessage(), and HAL_FDCAN_TT_ConfigTrigger().

#define IS_FDCAN_IT ( IT ) (((IT) & 0xC0300000U) == RESET)

Definition at line 2143 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), HAL_FDCAN_ConfigInterruptLines(), and HAL_FDCAN_DeactivateNotification().

#define IS_FDCAN_IT_LINE ( IT_LINE )
Value:
(((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \
                                   ((IT_LINE) == FDCAN_INTERRUPT_LINE1))

Definition at line 2151 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigInterruptLines(), and HAL_FDCAN_TT_ConfigInterruptLines().

#define IS_FDCAN_MAX_VALUE | ( | VALUE,
 |  | MAX
 | ) | ((VALUE) <= (MAX))

Definition at line 2068 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigClockCalibration(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigFifoWatermark(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_Init(), HAL_FDCAN_IsRxBufferMessageAvailable(), HAL_FDCAN_TT_ConfigExternalSyncPhase(), HAL_FDCAN_TT_ConfigOperation(), HAL_FDCAN_TT_ConfigReferenceMessage(), HAL_FDCAN_TT_ConfigRegisterTimeMark(), and HAL_FDCAN_TT_ConfigTrigger().

#define IS_FDCAN_MIN_VALUE | ( | VALUE,
 |  | MIN
 | ) | ((VALUE) >= (MIN))

Definition at line 2069 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigClockCalibration(), and HAL_FDCAN_GetTxEvent().

#define IS_FDCAN_MODE ( MODE )
Value:
(((MODE) == FDCAN_MODE_NORMAL              ) || \
                             ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
                             ((MODE) == FDCAN_MODE_BUS_MONITORING      ) || \
                             ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK   ) || \
                             ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK   ))

Definition at line 2039 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_NOMINAL_PRESCALER ( PRESCALER ) (((PRESCALER) >= 1) && ((PRESCALER) <= 512))

Definition at line 2060 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_NOMINAL_SJW ( SJW ) (((SJW) >= 1) && ((SJW) <= 128))

Definition at line 2061 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_NOMINAL_TSEG1 ( TSEG1 ) (((TSEG1) >= 2) && ((TSEG1) <= 256))

Definition at line 2062 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_NOMINAL_TSEG2 ( TSEG2 ) (((TSEG2) >= 2) && ((TSEG2) <= 128))

Definition at line 2063 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_NON_MATCHING ( DESTINATION )
Value:
(((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
                                            ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
                                            ((DESTINATION) == FDCAN_REJECT            ))

Definition at line 2148 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigGlobalFilter().

#define IS_FDCAN_OPERATION_MODE ( MODE )
Value:
(((MODE) == FDCAN_TT_COMMUNICATION_LEVEL1 ) || \
                                       ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL2 ) || \
                                       ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL0 ))

Definition at line 2201 of file stm32h7xx_hal_fdcan.h.

#define IS_FDCAN_RX_FIFO ( FIFO )
Value:
(((FIFO) == FDCAN_RX_FIFO0) || \
                                ((FIFO) == FDCAN_RX_FIFO1))

Definition at line 2106 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigRxFifoOverwrite(), and HAL_FDCAN_GetRxFifoFillLevel().

#define IS_FDCAN_RX_FIFO_MODE ( MODE )
Value:
(((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \
                                     ((MODE) == FDCAN_RX_FIFO_OVERWRITE))

Definition at line 2108 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigRxFifoOverwrite().

#define IS_FDCAN_STD_FILTER_TYPE ( TYPE )
Value:
(((TYPE) == FDCAN_FILTER_RANGE) || \
                                        ((TYPE) == FDCAN_FILTER_DUAL ) || \
                                        ((TYPE) == FDCAN_FILTER_MASK ))

Definition at line 2110 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

#define IS_FDCAN_TIMEOUT ( OPERATION )
Value:
(((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS   ) || \
                                     ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0     ) || \
                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1     ))

Definition at line 2171 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigTimeoutCounter().

#define IS_FDCAN_TIMESTAMP ( OPERATION )
Value:
(((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
                                       ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))

Definition at line 2153 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_EnableTimestampCounter().

#define IS_FDCAN_TIMESTAMP_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))

Definition at line 2155 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigTimestampCounter().

#define IS_FDCAN_TT_AUTO_CLK_CALIBRATION ( CALIBRATION )
Value:
(((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_DISABLE) || \
                                                       ((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_ENABLE ))

Definition at line 2212 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_BASIC_CYCLES_NUMBER ( NUMBER )
Value:
(((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_1 ) || \
                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_2 ) || \
                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_4 ) || \
                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_8 ) || \
                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_16) || \
                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_32) || \
                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_64))

Definition at line 2216 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_CYCLE_START_SYNC ( SYNC )
Value:
(((SYNC) == FDCAN_TT_NO_SYNC_PULSE         ) || \
                                            ((SYNC) == FDCAN_TT_SYNC_BASIC_CYCLE_START) || \
                                            ((SYNC) == FDCAN_TT_SYNC_MATRIX_START     ))

Definition at line 2223 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_EVENT_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_0) || \
                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_1) || \
                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_2) || \
                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_3))

Definition at line 2235 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_EVENT_TRIGGER_POLARITY ( POLARITY )
Value:
(((POLARITY) == FDCAN_TT_EVT_TRIG_POL_RISING ) || \
                                                      ((POLARITY) == FDCAN_TT_EVT_TRIG_POL_FALLING))

Definition at line 2214 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_EXTERNAL_CLK_SYNC ( SYNC )
Value:
(((SYNC) == FDCAN_TT_EXT_CLK_SYNC_DISABLE) || \
                                             ((SYNC) == FDCAN_TT_EXT_CLK_SYNC_ENABLE ))

Definition at line 2208 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_GLOBAL_TIME_FILTERING ( FILTERING )
Value:
(((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_DISABLE) || \
                                                      ((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_ENABLE ))

Definition at line 2210 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_IT ( IT ) (((IT) & 0xFFF80000U) == RESET)

Definition at line 2144 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ActivateNotification(), HAL_FDCAN_TT_ConfigInterruptLines(), and HAL_FDCAN_TT_DeactivateNotification().

#define IS_FDCAN_TT_OPERATION ( OPERATION )
Value:
(((OPERATION) == FDCAN_STRICTLY_TT_OPERATION      ) || \
                                          ((OPERATION) == FDCAN_EXT_EVT_SYNC_TT_OPERATION))

Definition at line 2204 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD ( PAYLOAD )
Value:
(((PAYLOAD) == FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ) || \
                                                        ((PAYLOAD) == FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD))

Definition at line 2177 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigReferenceMessage().

#define IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE ( SOURCE )
Value:
(((SOURCE) == FDCAN_TT_REG_TIMEMARK_DIABLED ) || \
                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \
                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \
                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME))

Definition at line 2246 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigRegisterTimeMark().

#define IS_FDCAN_TT_REPEAT_FACTOR ( FACTOR )
Value:
(((FACTOR) == FDCAN_TT_REPEAT_EVERY_CYCLE     ) || \
                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ) || \
                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ) || \
                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ) || \
                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_16TH_CYCLE) || \
                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_32ND_CYCLE) || \
                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_64TH_CYCLE))

Definition at line 2179 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigRegisterTimeMark(), and HAL_FDCAN_TT_ConfigTrigger().

#define IS_FDCAN_TT_STOP_WATCH_POLARITY ( POLARITY )
Value:
(((POLARITY) == FDCAN_TT_STOP_WATCH_DISABLED   ) || \
                                                   ((POLARITY) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME))

Definition at line 2244 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigStopWatch().

#define IS_FDCAN_TT_STOP_WATCH_SOURCE ( SOURCE )
Value:
(((SOURCE) == FDCAN_TT_STOP_WATCH_DISABLED   ) || \
                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_CYCLE_TIME ) || \
                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_LOCAL_TIME ) || \
                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME))

Definition at line 2240 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigStopWatch().

#define IS_FDCAN_TT_STOP_WATCH_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_0) || \
                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_1) || \
                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_2) || \
                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_3))

Definition at line 2231 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_TIME_MASTER ( FUNCTION )
Value:
(((FUNCTION) == FDCAN_TT_SLAVE           ) || \
                                           ((FUNCTION) == FDCAN_TT_POTENTIAL_MASTER))

Definition at line 2206 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_TIME_PRESET ( TIME ) (((TIME) <= 0xFFFF) && ((TIME) != 0x8000))

Definition at line 2239 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_SetGlobalTime().

#define IS_FDCAN_TT_TM_EVENT_EXTERNAL ( EVENT )
Value:
(((EVENT) == FDCAN_TT_TM_NO_EXTERNAL_EVENT ) || \
                                              ((EVENT) == FDCAN_TT_TM_GEN_EXTERNAL_EVENT))

Definition at line 2199 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

#define IS_FDCAN_TT_TM_EVENT_INTERNAL ( EVENT )
Value:
(((EVENT) == FDCAN_TT_TM_NO_INTERNAL_EVENT ) || \
                                              ((EVENT) == FDCAN_TT_TM_GEN_INTERNAL_EVENT))

Definition at line 2197 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

#define IS_FDCAN_TT_TRIGGER_TYPE ( TYPE )
Value:
(((TYPE) == FDCAN_TT_TX_REF_TRIGGER        ) || \
                                        ((TYPE) == FDCAN_TT_TX_REF_TRIGGER_GAP    ) || \
                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE     ) || \
                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) || \
                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_ARBITRATION) || \
                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED     ) || \
                                        ((TYPE) == FDCAN_TT_WATCH_TRIGGER         ) || \
                                        ((TYPE) == FDCAN_TT_WATCH_TRIGGER_GAP     ) || \
                                        ((TYPE) == FDCAN_TT_RX_TRIGGER            ) || \
                                        ((TYPE) == FDCAN_TT_TIME_BASE_TRIGGER     ) || \
                                        ((TYPE) == FDCAN_TT_END_OF_LIST           ))

Definition at line 2186 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigTrigger().

#define IS_FDCAN_TT_TUR_DENOMINATOR ( DENOMINATOR ) (((DENOMINATOR) >= 0x0001) && ((DENOMINATOR) <= 0x3FFF))

Definition at line 2228 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_TUR_LEVEL_0_2 | ( | NC,
 |  | DC
 | ) | ((NC) >= (8 * (DC)))

Definition at line 2230 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_TUR_LEVEL_1 | ( | NC,
 |  | DC
 | ) | ((NC) >= (4 * (DC)))

Definition at line 2229 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TT_TUR_NUMERATOR ( NUMERATOR ) (((NUMERATOR) >= 0x10000) && ((NUMERATOR) <= 0x1FFFF))

Definition at line 2227 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation(), and HAL_FDCAN_TT_SetClockSynchronization().

#define IS_FDCAN_TT_TX_ENABLE_WINDOW ( NTU ) (((NTU) >= 1) && ((NTU) <= 16))

Definition at line 2226 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_TT_ConfigOperation().

#define IS_FDCAN_TX_FIFO_QUEUE_MODE ( MODE )
Value:
(((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
                                           ((MODE) == FDCAN_TX_QUEUE_OPERATION))

Definition at line 2078 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_TX_LOCATION ( LOCATION )
Value:
(((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER2 ) || ((LOCATION) == FDCAN_TX_BUFFER3 ) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER4 ) || ((LOCATION) == FDCAN_TX_BUFFER5 ) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER6 ) || ((LOCATION) == FDCAN_TX_BUFFER7 ) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER8 ) || ((LOCATION) == FDCAN_TX_BUFFER9 ) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER10) || ((LOCATION) == FDCAN_TX_BUFFER11) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER12) || ((LOCATION) == FDCAN_TX_BUFFER13) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER14) || ((LOCATION) == FDCAN_TX_BUFFER15) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER16) || ((LOCATION) == FDCAN_TX_BUFFER17) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER18) || ((LOCATION) == FDCAN_TX_BUFFER19) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER20) || ((LOCATION) == FDCAN_TX_BUFFER21) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER22) || ((LOCATION) == FDCAN_TX_BUFFER23) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER24) || ((LOCATION) == FDCAN_TX_BUFFER25) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER26) || ((LOCATION) == FDCAN_TX_BUFFER27) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER28) || ((LOCATION) == FDCAN_TX_BUFFER29) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER30) || ((LOCATION) == FDCAN_TX_BUFFER31))

Definition at line 2090 of file stm32h7xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), HAL_FDCAN_IsTxBufferMessagePending(), and HAL_FDCAN_TT_ConfigTrigger().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Private Functions Prototypes

FDCAN Private Functions Prototypes
FDCAN
Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN Private Functions

Functions
FDCAN Private Functions
FDCAN

Functions

static HAL_StatusTypeDef | FDCAN_CalcultateRamBlockAddresses (FDCAN_HandleTypeDef *hfdcan)
Calculate each RAM block start address and size.
static HAL_StatusTypeDef | FDCAN_CopyMessageToRAM (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
Copy Tx message to the message RAM.

Function Documentation

static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses ( FDCAN_HandleTypeDef * hfdcan ) [static]

Calculate each RAM block start address and size.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 4615 of file stm32h7xx_hal_fdcan.c.

References FDCAN_MsgRamAddressTypeDef::EndAddress, FDCAN_HandleTypeDef::ErrorCode, FDCAN_MsgRamAddressTypeDef::ExtendedFilterSA, FDCAN_InitTypeDef::ExtFiltersNbr, HAL_FDCAN_ERROR_PARAM, FDCAN_HandleTypeDef::Init, FDCAN_HandleTypeDef::Instance, FDCAN_InitTypeDef::MessageRAMOffset, FDCAN_HandleTypeDef::msgRam, FDCAN_MsgRamAddressTypeDef::RxBufferSA, FDCAN_InitTypeDef::RxBufferSize, FDCAN_InitTypeDef::RxBuffersNbr, FDCAN_InitTypeDef::RxFifo0ElmtSize, FDCAN_InitTypeDef::RxFifo0ElmtsNbr, FDCAN_MsgRamAddressTypeDef::RxFIFO0SA, FDCAN_InitTypeDef::RxFifo1ElmtSize, FDCAN_InitTypeDef::RxFifo1ElmtsNbr, FDCAN_MsgRamAddressTypeDef::RxFIFO1SA, FDCAN_MsgRamAddressTypeDef::StandardFilterSA, FDCAN_InitTypeDef::StdFiltersNbr, FDCAN_MsgRamAddressTypeDef::TxBufferSA, FDCAN_InitTypeDef::TxBuffersNbr, FDCAN_InitTypeDef::TxElmtSize, FDCAN_MsgRamAddressTypeDef::TxEventFIFOSA, FDCAN_InitTypeDef::TxEventsNbr, FDCAN_MsgRamAddressTypeDef::TxFIFOQSA, and FDCAN_InitTypeDef::TxFifoQueueElmtsNbr.

Referenced by HAL_FDCAN_Init().

static HAL_StatusTypeDef FDCAN_CopyMessageToRAM | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_TxHeaderTypeDef * | pTxHeader,
 |  | uint8_t * | pTxData,
 |  | uint32_t | BufferIndex
 | ) |  | [static]

Copy Tx message to the message RAM.

Parameters:
hfdcan,: pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
pTxHeader,: pointer to a FDCAN_TxHeaderTypeDef structure.
pTxData,: pointer to a buffer containing the payload of the Tx frame.
BufferIndex,: index of the buffer to be configured.
Return values:
HAL status

Definition at line 4713 of file stm32h7xx_hal_fdcan.c.

References FDCAN_TxHeaderTypeDef::BitRateSwitch, FDCAN_TxHeaderTypeDef::DataLength, DLCtoBytes, FDCAN_TxHeaderTypeDef::ErrorStateIndicator, FDCAN_EXTENDED_ID, FDCAN_STANDARD_ID, FDCAN_TxHeaderTypeDef::FDFormat, FDCAN_TxHeaderTypeDef::Identifier, FDCAN_TxHeaderTypeDef::IdType, FDCAN_HandleTypeDef::Init, FDCAN_TxHeaderTypeDef::MessageMarker, FDCAN_HandleTypeDef::msgRam, FDCAN_MsgRamAddressTypeDef::TxBufferSA, FDCAN_InitTypeDef::TxElmtSize, FDCAN_TxHeaderTypeDef::TxEventFifoControl, and FDCAN_TxHeaderTypeDef::TxFrameType.

Referenced by HAL_FDCAN_AddMessageToTxBuffer(), and HAL_FDCAN_AddMessageToTxFifoQ().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FDCAN

Modules | Variables
FDCAN
STM32H7xx_HAL_Driver

FDCAN HAL module driver. More...

Modules

FDCAN Exported Functions
FDCAN Exported Types
FDCAN Exported Constants
FDCAN Exported Macros
FDCAN Private Types
FDCAN Private Variables
FDCAN Private Constants
FDCAN Private Macros
FDCAN Private Functions Prototypes
FDCAN Private Functions

Variables

static const uint8_t | DLCtoBytes [] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}
static const uint8_t | CvtEltSize [] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7}

Detailed Description

FDCAN HAL module driver.

Variable Documentation

const uint8_t CvtEltSize[] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7} [static]

Definition at line 173 of file stm32h7xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init().

const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64} [static]

Definition at line 172 of file stm32h7xx_hal_fdcan.c.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_GetRxMessage().

Generated on Fri Apr 28 2017 15:42:45 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Programming operation functions

Functions
Programming operation functions
FLASH Private functions

Programming operation functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t FlashAddress, uint64_t DataAddress)
Program flash word of 256 bits at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t FlashAddress, uint64_t DataAddress)
Program flash words of 256 bits at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
This function handles FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.

Detailed Description

Programming operation functions.

 ===============================================================================
                  ##### Programming operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the FLASH
    program operations.

Function Documentation

__weak void HAL_FLASH_EndOfOperationCallback ( uint32_t ReturnValue )

FLASH end of operation interrupt callback.

Parameters:
ReturnValue The value saved in this parameter depends on the ongoing procedure Mass Erase Bank number which has been requested to erase Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that all the selected sectors have been erased) Program Address which was selected for data program
Return values:
None

Definition at line 550 of file stm32h7xx_hal_flash.c.

Referenced by HAL_FLASH_IRQHandler().

void HAL_FLASH_IRQHandler ( void )

This function handles FLASH interrupt request.

Return values:
None

Definition at line 330 of file stm32h7xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG_BANK1, __HAL_FLASH_CLEAR_FLAG_BANK2, __HAL_FLASH_DISABLE_IT_BANK1, __HAL_FLASH_DISABLE_IT_BANK2, __HAL_FLASH_GET_FLAG_BANK1, __HAL_FLASH_GET_FLAG_BANK2, FLASH_ProcessTypeDef::Address, FLASH_BANK_1, FLASH_BANK_2, FLASH_Erase_Sector(), FLASH_FLAG_ALL_ERRORS_BANK1, FLASH_FLAG_ALL_ERRORS_BANK2, FLASH_FLAG_EOP_BANK1, FLASH_FLAG_EOP_BANK2, FLASH_FLAG_INCERR_BANK1, FLASH_FLAG_INCERR_BANK2, FLASH_FLAG_OPERR_BANK1, FLASH_FLAG_OPERR_BANK2, FLASH_FLAG_PGSERR_BANK1, FLASH_FLAG_PGSERR_BANK2, FLASH_FLAG_STRBER_BANK1R, FLASH_FLAG_STRBER_BANK2R, FLASH_FLAG_WRPERR_BANK1, FLASH_FLAG_WRPERR_BANK2, FLASH_IT_EOP_BANK1, FLASH_IT_EOP_BANK2, FLASH_IT_INCERR_BANK1, FLASH_IT_INCERR_BANK2, FLASH_IT_OPERR_BANK1, FLASH_IT_OPERR_BANK2, FLASH_IT_PGSERR_BANK1, FLASH_IT_PGSERR_BANK2, FLASH_IT_STRBERR_BANK1, FLASH_IT_STRBERR_BANK2, FLASH_IT_WRPERR_BANK1, FLASH_IT_WRPERR_BANK2, FLASH_PROC_ALLBANK_MASSERASE, FLASH_PROC_MASSERASE_BANK1, FLASH_PROC_MASSERASE_BANK2, FLASH_PROC_NONE, FLASH_PROC_PROGRAM_BANK1, FLASH_PROC_PROGRAM_BANK2, FLASH_PROC_SECTERASE_BANK1, FLASH_PROC_SECTERASE_BANK2, FLASH_SetErrorCode(), HAL_FLASH_EndOfOperationCallback(), HAL_FLASH_OperationErrorCallback(), FLASH_ProcessTypeDef::NbSectorsToErase, FLASH_ProcessTypeDef::ProcedureOnGoing, FLASH_ProcessTypeDef::Sector, and FLASH_ProcessTypeDef::VoltageForErase.

__weak void HAL_FLASH_OperationErrorCallback ( uint32_t ReturnValue )

FLASH operation error interrupt callback.

Parameters:
ReturnValue The value saved in this parameter depends on the ongoing procedure Mass Erase: Bank number which has been requested to erase Sectors Erase: Sector number which returned an error Program: Address which was selected for data program
Return values:
None

Definition at line 565 of file stm32h7xx_hal_flash.c.

Referenced by HAL_FLASH_IRQHandler().

HAL_StatusTypeDef HAL_FLASH_Program | ( | uint32_t | TypeProgram,
 |  | uint32_t | FlashAddress,
 |  | uint64_t | DataAddress
 | ) |  |

Program flash word of 256 bits at a specified address.

Parameters:
TypeProgram | Indicate the way to program at a specified address. This parameter can be a value of FLASH Type Program
FlashAddress | specifies the address to be programmed.
DataAddress | specifies the address of data (256 bits) to be programmed
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 165 of file stm32h7xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG_BANK1, __HAL_FLASH_CLEAR_FLAG_BANK2, __HAL_FLASH_GET_FLAG_BANK1, __HAL_FLASH_GET_FLAG_BANK2, assert_param, FLASH_BANK_1, FLASH_BANK_2, FLASH_FLAG_ALL_ERRORS_BANK1, FLASH_FLAG_ALL_ERRORS_BANK2, FLASH_FLAG_EOP_BANK1, FLASH_FLAG_EOP_BANK2, FLASH_FLAG_QW_BANK1, FLASH_FLAG_QW_BANK2, FLASH_FLAG_WBNE_BANK1, FLASH_FLAG_WBNE_BANK2, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_FLASH_PROGRAM_ADDRESS, IS_FLASH_PROGRAM_ADDRESS_BANK1, and IS_FLASH_TYPEPROGRAM.

HAL_StatusTypeDef HAL_FLASH_Program_IT | ( | uint32_t | TypeProgram,
 |  | uint32_t | FlashAddress,
 |  | uint64_t | DataAddress
 | ) |  |

Program flash words of 256 bits at a specified address with interrupt enabled.

Parameters:
TypeProgram | Indicate the way to program at a specified address. This parameter can be a value of FLASH Type Program
FlashAddress | specifies the address to be programmed.
DataAddress | specifies the address of data (256 bits) to be programmed
Return values:
HAL Status

Definition at line 263 of file stm32h7xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG_BANK1, __HAL_FLASH_CLEAR_FLAG_BANK2, __HAL_FLASH_ENABLE_IT_BANK1, __HAL_FLASH_ENABLE_IT_BANK2, FLASH_ProcessTypeDef::Address, assert_param, FLASH_BANK_1, FLASH_BANK_2, FLASH_FLAG_ALL_ERRORS_BANK1, FLASH_FLAG_ALL_ERRORS_BANK2, FLASH_FLAG_EOP_BANK1, FLASH_FLAG_EOP_BANK2, FLASH_IT_EOP_BANK1, FLASH_IT_EOP_BANK2, FLASH_IT_INCERR_BANK1, FLASH_IT_INCERR_BANK2, FLASH_IT_OPERR_BANK1, FLASH_IT_OPERR_BANK2, FLASH_IT_PGSERR_BANK1, FLASH_IT_PGSERR_BANK2, FLASH_IT_STRBERR_BANK1, FLASH_IT_STRBERR_BANK2, FLASH_IT_WRPERR_BANK1, FLASH_IT_WRPERR_BANK2, FLASH_PROC_PROGRAM_BANK1, FLASH_PROC_PROGRAM_BANK2, IS_FLASH_PROGRAM_ADDRESS, IS_FLASH_PROGRAM_ADDRESS_BANK1, IS_FLASH_TYPEPROGRAM, and FLASH_ProcessTypeDef::ProcedureOnGoing.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
FLASH Private functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control registers access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Locks the FLASH control registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.

Detailed Description

management functions

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the FLASH
    memory operations.

Function Documentation

HAL_StatusTypeDef HAL_FLASH_Lock ( void )

Locks the FLASH control registers access.

Return values:
HAL Status

Definition at line 619 of file stm32h7xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Launch ( void )

Launch the option byte loading.

Return values:
HAL Status

Definition at line 666 of file stm32h7xx_hal_flash.c.

References FLASH_OB_WaitForLastOperation(), and FLASH_TIMEOUT_VALUE.

HAL_StatusTypeDef HAL_FLASH_OB_Lock ( void )

Lock the FLASH Option Control Registers access.

Return values:
HAL Status

Definition at line 654 of file stm32h7xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Unlock ( void )

Unlock the FLASH Option Control Registers access.

Return values:
HAL Status

Definition at line 634 of file stm32h7xx_hal_flash.c.

References FLASH_OPT_KEY1, and FLASH_OPT_KEY2.

HAL_StatusTypeDef HAL_FLASH_Unlock ( void )

Unlock the FLASH control registers access.

Return values:
HAL Status

Definition at line 595 of file stm32h7xx_hal_flash.c.

References FLASH_KEY1, and FLASH_KEY2.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
FLASH Private functions

Peripheral Errors functions. More...

Functions

uint32_t HAL_FLASH_GetError (void)
Get the specific FLASH error flag.

Detailed Description

Peripheral Errors functions.

 ===============================================================================
                ##### Peripheral Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time Errors of the FLASH peripheral.

Function Documentation

uint32_t HAL_FLASH_GetError ( void )

Get the specific FLASH error flag.

Return values:
HAL_FLASH_ERRORCode The returned value can be:
  • HAL_FLASH_ERROR_NONE: No error set
  • HAL_FLASH_ERROR_WRP_BANK1: Write Protection Error on Bank 1
  • HAL_FLASH_ERROR_PGS_BANK1 : Program Sequence Error on Bank 1
  • HAL_FLASH_ERROR_STRB_BANK1 : Strobe Error on Bank 1
  • HAL_FLASH_ERROR_INC_BANK1 : Inconsistency Error on Bank 1
  • HAL_FLASH_ERROR_OPE_BANK1 : Operation Error on Bank 1
  • HAL_FLASH_ERROR_RDP_BANK1 : Read Protection Error on Bank 1
  • HAL_FLASH_ERROR_RDS_BANK1 : Read Secured Error on Bank 1
  • HAL_FLASH_ERROR_SNECC_BANK1: SNECC Error on Bank 1
  • HAL_FLASH_ERROR_DBECC_BANK1: Double Detection ECC on Bank 1
  • HAL_FLASH_ERROR_WRP_BANK2 : Write Protection Error on Bank 2
  • HAL_FLASH_ERROR_PGS_BANK2 : Program Sequence Error on Bank 2
  • HAL_FLASH_ERROR_STRB_BANK2 : Strobe Error on Bank 2
  • HAL_FLASH_ERROR_INC_BANK2 : Inconsistency Error on Bank 2
  • HAL_FLASH_ERROR_OPE_BANK2 : Operation Error on Bank 2
  • HAL_FLASH_ERROR_RDP_BANK2 : Read Protection Error on Bank 2
  • HAL_FLASH_ERROR_RDS_BANK2 : Read Secured Error on Bank 2
  • HAL_FLASH_ERROR_SNECC_BANK2: SNECC Error on Bank 2
  • HAL_FLASH_ERROR_DBECC_BANK2: Double Detection ECC on Bank 2

Definition at line 723 of file stm32h7xx_hal_flash.c.

References FLASH_ProcessTypeDef::ErrorCode.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH Exported Types

Data Structures | Enumerations
FLASH Exported Types
FLASH

Data Structures

struct FLASH_ProcessTypeDef
FLASH handle Structure definition. More...

Enumerations

enum FLASH_ProcedureTypeDef {
FLASH_PROC_NONE = 0U, FLASH_PROC_SECTERASE_BANK1, FLASH_PROC_MASSERASE_BANK1, FLASH_PROC_PROGRAM_BANK1,
FLASH_PROC_SECTERASE_BANK2, FLASH_PROC_MASSERASE_BANK2, FLASH_PROC_PROGRAM_BANK2, FLASH_PROC_ALLBANK_MASSERASE
}
FLASH Procedure structure definition. More...

Enumeration Type Documentation

enum FLASH_ProcedureTypeDef

FLASH Procedure structure definition.

Enumerator:
FLASH_PROC_NONE
FLASH_PROC_SECTERASE_BANK1
FLASH_PROC_MASSERASE_BANK1
FLASH_PROC_PROGRAM_BANK1
FLASH_PROC_SECTERASE_BANK2
FLASH_PROC_MASSERASE_BANK2
FLASH_PROC_PROGRAM_BANK2
FLASH_PROC_ALLBANK_MASSERASE

Definition at line 65 of file stm32h7xx_hal_flash.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH_ProcessTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_ProcessTypeDef Struct Reference
FLASH Exported Types

FLASH handle Structure definition. More...

#include <stm32h7xx_hal_flash.h>

Data Fields

__IO FLASH_ProcedureTypeDef | ProcedureOnGoing
__IO uint32_t | NbSectorsToErase
__IO uint8_t | VoltageForErase
__IO uint32_t | Sector
__IO uint32_t | Address
HAL_LockTypeDef | Lock
__IO uint32_t | ErrorCode

Detailed Description

FLASH handle Structure definition.

Definition at line 81 of file stm32h7xx_hal_flash.h.

Field Documentation

__IO uint32_t FLASH_ProcessTypeDef::Address

Internal variable to save address selected for program

Definition at line 91 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASH_Program_IT().

__IO uint32_t FLASH_ProcessTypeDef::ErrorCode

FLASH error code

Definition at line 95 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_OB_WaitForLastOperation(), FLASH_SetErrorCode(), HAL_FLASH_GetError(), and HAL_FLASHEx_OBProgram().

HAL_LockTypeDef FLASH_ProcessTypeDef::Lock

FLASH locking object

Definition at line 93 of file stm32h7xx_hal_flash.h.

__IO uint32_t FLASH_ProcessTypeDef::NbSectorsToErase

Internal variable to save the remaining sectors to erase in IT context

Definition at line 85 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

__IO FLASH_ProcedureTypeDef FLASH_ProcessTypeDef::ProcedureOnGoing

Internal variable to indicate which procedure is ongoing or not in IT context

Definition at line 83 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

__IO uint32_t FLASH_ProcessTypeDef::Sector

Internal variable to define the current sector which is erasing

Definition at line 89 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

__IO uint8_t FLASH_ProcessTypeDef::VoltageForErase

Internal variable to provide voltage range selected by user in IT context

Definition at line 87 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_flash.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH Error Code

Defines
FLASH Error Code
FLASH Exported Constants

FLASH Error Code. More...

Defines

#define | HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_FLASH_ERROR_WRP ((uint32_t)0x00000001U)
#define | HAL_FLASH_ERROR_PGS ((uint32_t)0x00000002U)
#define | HAL_FLASH_ERROR_STRB ((uint32_t)0x00000004U)
#define | HAL_FLASH_ERROR_INC ((uint32_t)0x00000008U)
#define | HAL_FLASH_ERROR_OPE ((uint32_t)0x00000010U)
#define | HAL_FLASH_ERROR_RDP ((uint32_t)0x00000020U)
#define | HAL_FLASH_ERROR_RDS ((uint32_t)0x00000040U)
#define | HAL_FLASH_ERROR_SNECC ((uint32_t)0x00000080U)
#define | HAL_FLASH_ERROR_DBECC ((uint32_t)0x00000100U)
#define | HAL_FLASH_ERROR_WRP_BANK1 ((uint32_t)0x00000001U)
#define | HAL_FLASH_ERROR_PGS_BANK1 ((uint32_t)0x00000002U)
#define | HAL_FLASH_ERROR_STRB_BANK1 ((uint32_t)0x00000004U)
#define | HAL_FLASH_ERROR_INC_BANK1 ((uint32_t)0x00000008U)
#define | HAL_FLASH_ERROR_OPE_BANK1 ((uint32_t)0x00000010U)
#define | HAL_FLASH_ERROR_RDP_BANK1 ((uint32_t)0x00000020U)
#define | HAL_FLASH_ERROR_RDS_BANK1 ((uint32_t)0x00000040U)
#define | HAL_FLASH_ERROR_SNECC_BANK1 ((uint32_t)0x00000080U)
#define | HAL_FLASH_ERROR_DBECC_BANK1 ((uint32_t)0x00000100U)
#define | HAL_FLASH_ERROR_WRP_BANK2 ((uint32_t)0x00001000U)
#define | HAL_FLASH_ERROR_PGS_BANK2 ((uint32_t)0x00002000U)
#define | HAL_FLASH_ERROR_STRB_BANK2 ((uint32_t)0x00004000U)
#define | HAL_FLASH_ERROR_INC_BANK2 ((uint32_t)0x00008000U)
#define | HAL_FLASH_ERROR_OPE_BANK2 ((uint32_t)0x00010000U)
#define | HAL_FLASH_ERROR_RDP_BANK2 ((uint32_t)0x00020000U)
#define | HAL_FLASH_ERROR_RDS_BANK2 ((uint32_t)0x00040000U)
#define | HAL_FLASH_ERROR_SNECC_BANK2 ((uint32_t)0x00080000U)
#define | HAL_FLASH_ERROR_DBECC_BANK2 ((uint32_t)0x00100000U)
#define | HAL_FLASH_ERROR_OB_CHANGE ((uint32_t)0x01000000U)

Detailed Description

FLASH Error Code.

Define Documentation

#define HAL_FLASH_ERROR_DBECC ((uint32_t)0x00000100U)

Double Detection ECC

Definition at line 123 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_DBECC_BANK1 ((uint32_t)0x00000100U)

Double Detection ECC on Bank 1

Definition at line 133 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_DBECC_BANK2 ((uint32_t)0x00100000U)

Double Detection ECC on Bank 2

Definition at line 143 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_INC ((uint32_t)0x00000008U)

Inconsistency Error

Definition at line 118 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_INC_BANK1 ((uint32_t)0x00000008U)

Inconsistency Error on Bank 1

Definition at line 128 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_INC_BANK2 ((uint32_t)0x00008000U)

Inconsistency Error on Bank 2

Definition at line 138 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 113 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), and HAL_FLASHEx_OBProgram().

#define HAL_FLASH_ERROR_OB_CHANGE ((uint32_t)0x01000000U)

Option Byte Change Error

Definition at line 145 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_OB_WaitForLastOperation().

#define HAL_FLASH_ERROR_OPE ((uint32_t)0x00000010U)

Operation Error

Definition at line 119 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_OPE_BANK1 ((uint32_t)0x00000010U)

Operation Error on Bank 1

Definition at line 129 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_OPE_BANK2 ((uint32_t)0x00010000U)

Operation Error on Bank 2

Definition at line 139 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_PGS ((uint32_t)0x00000002U)

Program Sequence Error

Definition at line 116 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_PGS_BANK1 ((uint32_t)0x00000002U)

Program Sequence Error on Bank 1

Definition at line 126 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_PGS_BANK2 ((uint32_t)0x00002000U)

Program Sequence Error on Bank 2

Definition at line 136 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_RDP ((uint32_t)0x00000020U)

Read Protection Error

Definition at line 120 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_RDP_BANK1 ((uint32_t)0x00000020U)

Read Protection Error on Bank 1

Definition at line 130 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_RDP_BANK2 ((uint32_t)0x00020000U)

Read Protection Error on Bank 2

Definition at line 140 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_RDS ((uint32_t)0x00000040U)

Read Secured Error

Definition at line 121 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_RDS_BANK1 ((uint32_t)0x00000040U)

Read Secured Error on Bank 1

Definition at line 131 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_RDS_BANK2 ((uint32_t)0x00040000U)

Read Secured Error on Bank 2

Definition at line 141 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_SNECC ((uint32_t)0x00000080U)

Single Detection ECC

Definition at line 122 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_SNECC_BANK1 ((uint32_t)0x00000080U)

Single Detection ECC on Bank 1

Definition at line 132 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_SNECC_BANK2 ((uint32_t)0x00080000U)

Single Detection ECC on Bank 2

Definition at line 142 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_STRB ((uint32_t)0x00000004U)

Strobe Error

Definition at line 117 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_STRB_BANK1 ((uint32_t)0x00000004U)

Strobe Error on Bank 1

Definition at line 127 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_STRB_BANK2 ((uint32_t)0x00004000U)

Strobe Error on Bank 2

Definition at line 137 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000001U)

Write Protection Error

Definition at line 115 of file stm32h7xx_hal_flash.h.

#define HAL_FLASH_ERROR_WRP_BANK1 ((uint32_t)0x00000001U)

Write Protection Error on Bank 1

Definition at line 125 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_WRP_BANK2 ((uint32_t)0x00001000U)

Write Protection Error on Bank 2

Definition at line 135 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH Type Program

Defines
FLASH Type Program
FLASH Exported Constants

Defines

#define FLASH_TYPEPROGRAM_FLASHWORD ((uint32_t)0x03U)

Define Documentation

#define FLASH_TYPEPROGRAM_FLASHWORD ((uint32_t)0x03U)

Program a flash word (256-bit) at a specified address

Definition at line 154 of file stm32h7xx_hal_flash.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH Flag definition

Defines
FLASH Flag definition
FLASH Exported Constants

Flag definition. More...

Defines

#define | FLASH_FLAG_BSY FLASH_SR_BSY
#define | FLASH_FLAG_WDW FLASH_SR_WDW
#define | FLASH_FLAG_QW FLASH_SR_QW
#define | FLASH_FLAG_CRC_BUSY FLASH_SR_CRC_BUSY
#define | FLASH_FLAG_EOP FLASH_SR_EOP
#define | FLASH_FLAG_WRPERR FLASH_SR_WRPERR
#define | FLASH_FLAG_PGSERR FLASH_SR_PGSERR
#define | FLASH_FLAG_STRBERR FLASH_SR_STRBERR
#define | FLASH_FLAG_INCERR FLASH_SR_INCERR
#define | FLASH_FLAG_OPERR FLASH_SR_OPERR
#define | FLASH_FLAG_RDPERR FLASH_SR_RDPERR
#define | FLASH_FLAG_RDSERR FLASH_SR_RDSERR
#define | FLASH_FLAG_SNECCERR FLASH_SR_SNECCERR
#define | FLASH_FLAG_DBECCERR FLASH_SR_DBECCERR
#define | FLASH_FLAG_CRCEND FLASH_SR_CRCEND
#define | FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY
#define | FLASH_FLAG_WBNE_BANK1 FLASH_SR_WBNE
#define | FLASH_FLAG_QW_BANK1 FLASH_SR_QW
#define | FLASH_FLAG_CRC_BUSY_BANK1 FLASH_SR_CRC_BUSY
#define | FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP
#define | FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPERR
#define | FLASH_FLAG_PGSERR_BANK1 FLASH_SR_PGSERR
#define | FLASH_FLAG_STRBER_BANK1R FLASH_SR_STRBERR
#define | FLASH_FLAG_INCERR_BANK1 FLASH_SR_INCERR
#define | FLASH_FLAG_OPERR_BANK1 FLASH_SR_OPERR
#define | FLASH_FLAG_RDPERR_BANK1 FLASH_SR_RDPERR
#define | FLASH_FLAG_RDSERR_BANK1 FLASH_SR_RDSERR
#define | FLASH_FLAG_SNECCE_BANK1RR FLASH_SR_SNECCERR
#define | FLASH_FLAG_DBECCE_BANK1RR FLASH_SR_DBECCERR
#define | FLASH_FLAG_CRCEND_BANK1 FLASH_SR_CRCEND
#define | FLASH_FLAG_ALL_ERRORS_BANK1
#define | FLASH_FLAG_ALL_BANK1
#define | FLASH_FLAG_BSY_BANK2 (FLASH_SR_BSY | 0x80000000U)
#define | FLASH_FLAG_WBNE_BANK2 (FLASH_SR_WBNE | 0x80000000U)
#define | FLASH_FLAG_QW_BANK2 (FLASH_SR_QW | 0x80000000U)
#define | FLASH_FLAG_CRC_BUSY_BANK2 (FLASH_SR_CRC_BUSY | 0x80000000U)
#define | FLASH_FLAG_EOP_BANK2 (FLASH_SR_EOP | 0x80000000U)
#define | FLASH_FLAG_WRPERR_BANK2 (FLASH_SR_WRPERR | 0x80000000U)
#define | FLASH_FLAG_PGSERR_BANK2 (FLASH_SR_PGSERR | 0x80000000U)
#define | FLASH_FLAG_STRBER_BANK2R (FLASH_SR_STRBERR | 0x80000000U)
#define | FLASH_FLAG_INCERR_BANK2 (FLASH_SR_INCERR | 0x80000000U)
#define | FLASH_FLAG_OPERR_BANK2 (FLASH_SR_OPERR | 0x80000000U)
#define | FLASH_FLAG_RDPERR_BANK2 (FLASH_SR_RDPERR | 0x80000000U)
#define | FLASH_FLAG_RDSERR_BANK2 (FLASH_SR_RDSERR | 0x80000000U)
#define | FLASH_FLAG_SNECCE_BANK2RR (FLASH_SR_SNECCERR | 0x80000000U)
#define | FLASH_FLAG_DBECCE_BANK2RR (FLASH_SR_DBECCERR | 0x80000000U)
#define | FLASH_FLAG_CRCEND_BANK2 (FLASH_SR_CRCEND | 0x80000000U)
#define | FLASH_FLAG_ALL_ERRORS_BANK2
#define | FLASH_FLAG_ALL_BANK2

Detailed Description

Flag definition.

Define Documentation

#define FLASH_FLAG_ALL_BANK1
Value:
(FLASH_FLAG_BSY_BANK1      | FLASH_FLAG_WBNE_BANK1      | \
                                           FLASH_FLAG_QW_BANK1       | FLASH_FLAG_CRC_BUSY_BANK1 | \
                                           FLASH_FLAG_EOP_BANK1      | FLASH_FLAG_CRCEND_BANK1   | \
                                           FLASH_FLAG_ALL_ERRORS_BANK1)

Definition at line 205 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_ALL_BANK2
Value:
(FLASH_FLAG_BSY_BANK2      | FLASH_FLAG_WBNE_BANK2      | \
                                           FLASH_FLAG_QW_BANK2       | FLASH_FLAG_CRC_BUSY_BANK2 | \
                                           FLASH_FLAG_EOP_BANK2      | FLASH_FLAG_CRCEND_BANK2   | \
                                           FLASH_FLAG_ALL_ERRORS_BANK2)

Definition at line 233 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_ALL_ERRORS_BANK1
Value:
(FLASH_FLAG_WRPERR_BANK1  | FLASH_FLAG_PGSERR_BANK1   | \
                                           FLASH_FLAG_STRBER_BANK1R | FLASH_FLAG_INCERR_BANK1   | \
                                           FLASH_FLAG_OPERR_BANK1   | FLASH_FLAG_RDPERR_BANK1   | \
                                           FLASH_FLAG_RDSERR_BANK1  | FLASH_FLAG_SNECCE_BANK1RR | \
                                           FLASH_FLAG_DBECCE_BANK1RR)

Definition at line 199 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), HAL_FLASH_IRQHandler(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_FLAG_ALL_ERRORS_BANK2
Value:
(FLASH_FLAG_WRPERR_BANK2  | FLASH_FLAG_PGSERR_BANK2   | \
                                           FLASH_FLAG_STRBER_BANK2R | FLASH_FLAG_INCERR_BANK2   | \
                                           FLASH_FLAG_OPERR_BANK2   | FLASH_FLAG_RDPERR_BANK2   | \
                                           FLASH_FLAG_RDSERR_BANK2  | FLASH_FLAG_SNECCE_BANK2RR | \
                                           FLASH_FLAG_DBECCE_BANK2RR)

Definition at line 227 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), HAL_FLASH_IRQHandler(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_FLAG_BSY FLASH_SR_BSY

FLASH Busy flag

Definition at line 165 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY

FLASH Bank 1 Busy flag

Definition at line 182 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation().

#define FLASH_FLAG_BSY_BANK2 (FLASH_SR_BSY | 0x80000000U)

FLASH Bank 2 Busy flag

Definition at line 210 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation().

#define FLASH_FLAG_CRC_BUSY FLASH_SR_CRC_BUSY

CRC module is working on flag

Definition at line 168 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_CRC_BUSY_BANK1 FLASH_SR_CRC_BUSY

CRC module is working on Bank 1 flag

Definition at line 185 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_CRC_BUSY_BANK2 (FLASH_SR_CRC_BUSY | 0x80000000U)

CRC module is working on Bank 2 flag

Definition at line 213 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_CRCEND FLASH_SR_CRCEND

CRC module completes on bank flag

Definition at line 179 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_CRCEND_BANK1 FLASH_SR_CRCEND

CRC module completes on bank Bank 1 flag

Definition at line 196 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_CRCEND_BANK2 (FLASH_SR_CRCEND | 0x80000000U)

CRC module completes on bank Bank 2 flag

Definition at line 224 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_DBECCE_BANK1RR FLASH_SR_DBECCERR

Double Detection ECC Error on Bank 1 flag

Definition at line 195 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define FLASH_FLAG_DBECCE_BANK2RR (FLASH_SR_DBECCERR | 0x80000000U)

Double Detection ECC Error on Bank 2 flag

Definition at line 223 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define FLASH_FLAG_DBECCERR FLASH_SR_DBECCERR

Double Detection ECC Error on flag

Definition at line 178 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_EOP FLASH_SR_EOP

End Of Program on flag

Definition at line 169 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP

End Of Program on Bank 1 flag

Definition at line 186 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_FLAG_EOP_BANK2 (FLASH_SR_EOP | 0x80000000U)

End Of Program on Bank 2 flag

Definition at line 214 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_FLAG_INCERR FLASH_SR_INCERR

Inconsistency Error on flag

Definition at line 173 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_INCERR_BANK1 FLASH_SR_INCERR

Inconsistency Error on Bank 1 flag

Definition at line 190 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_INCERR_BANK2 (FLASH_SR_INCERR | 0x80000000U)

Inconsistency Error on Bank 2 flag

Definition at line 218 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_OPERR FLASH_SR_OPERR

Operation Error on flag

Definition at line 174 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_OPERR_BANK1 FLASH_SR_OPERR

Operation Error on Bank 1 flag

Definition at line 191 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_OPERR_BANK2 (FLASH_SR_OPERR | 0x80000000U)

Operation Error on Bank 2 flag

Definition at line 219 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR

Program Sequence Error on flag

Definition at line 171 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_PGSERR_BANK1 FLASH_SR_PGSERR

Program Sequence Error on Bank 1 flag

Definition at line 188 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_PGSERR_BANK2 (FLASH_SR_PGSERR | 0x80000000U)

Program Sequence Error on Bank 2 flag

Definition at line 216 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_QW FLASH_SR_QW

Write Waiting in Operation Queue on flag

Definition at line 167 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_QW_BANK1 FLASH_SR_QW

Write Waiting in Operation Queue on Bank 1 flag

Definition at line 184 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_Program().

#define FLASH_FLAG_QW_BANK2 (FLASH_SR_QW | 0x80000000U)

Write Waiting in Operation Queue on Bank 2 flag

Definition at line 212 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_Program().

#define FLASH_FLAG_RDPERR FLASH_SR_RDPERR

Read Protection Error on flag

Definition at line 175 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_RDPERR_BANK1 FLASH_SR_RDPERR

Read Protection Error on Bank 1 flag

Definition at line 192 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define FLASH_FLAG_RDPERR_BANK2 (FLASH_SR_RDPERR | 0x80000000U)

Read Protection Error on Bank 2 flag

Definition at line 220 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define FLASH_FLAG_RDSERR FLASH_SR_RDSERR

Read Secured Error on flag

Definition at line 176 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_RDSERR_BANK1 FLASH_SR_RDSERR

Read Secured Error on Bank 1 flag

Definition at line 193 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define FLASH_FLAG_RDSERR_BANK2 (FLASH_SR_RDSERR | 0x80000000U)

Read Secured Error on Bank 2 flag

Definition at line 221 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define FLASH_FLAG_SNECCE_BANK1RR FLASH_SR_SNECCERR

Single ECC Error Correction on Bank 1 flag

Definition at line 194 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define FLASH_FLAG_SNECCE_BANK2RR (FLASH_SR_SNECCERR | 0x80000000U)

Single ECC Error Correction on Bank 2 flag

Definition at line 222 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define FLASH_FLAG_SNECCERR FLASH_SR_SNECCERR

Single ECC Error Correction on flag

Definition at line 177 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_STRBER_BANK1R FLASH_SR_STRBERR

strobe Error on Bank 1 flag

Definition at line 189 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_STRBER_BANK2R (FLASH_SR_STRBERR | 0x80000000U)

Strobe Error on Bank 2 flag

Definition at line 217 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_STRBERR FLASH_SR_STRBERR

strobe Error on flag

Definition at line 172 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_WBNE_BANK1 FLASH_SR_WBNE

Waiting for Data to Write on Bank 1 flag

Definition at line 183 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_Program().

#define FLASH_FLAG_WBNE_BANK2 (FLASH_SR_WBNE | 0x80000000U)

Waiting for Data to Write on Bank 2 flag

Definition at line 211 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_Program().

#define FLASH_FLAG_WDW FLASH_SR_WDW

Waiting for Data to Write on flag

Definition at line 166 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR

Write Protection Error on flag

Definition at line 170 of file stm32h7xx_hal_flash.h.

#define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPERR

Write Protection Error on Bank 1 flag

Definition at line 187 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR_WRPERR | 0x80000000U)

Write Protection Error on Bank 2 flag

Definition at line 215 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), and HAL_FLASH_IRQHandler().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH Interrupt definition

Defines
FLASH Interrupt definition
FLASH Exported Constants

FLASH Interrupt definition. More...

Defines

#define | FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE
#define | FLASH_IT_WRPERR_BANK1 FLASH_CR_WRPERRIE
#define | FLASH_IT_PGSERR_BANK1 FLASH_CR_PGSERRIE
#define | FLASH_IT_STRBERR_BANK1 FLASH_CR_STRBERRIE
#define | FLASH_IT_INCERR_BANK1 FLASH_CR_INCERRIE
#define | FLASH_IT_OPERR_BANK1 FLASH_CR_OPERRIE
#define | FLASH_IT_RDPERR_BANK1 FLASH_CR_RDPERRIE
#define | FLASH_IT_RDSERR_BANK1 FLASH_CR_RDSERRIE
#define | FLASH_IT_SNECCERR_BANK1 FLASH_CR_SNECCERRIE
#define | FLASH_IT_DBECCERR_BANK1 FLASH_CR_DBECCERRIE
#define | FLASH_IT_CRCEND_BANK1 FLASH_CR_CRCENDIE
#define | FLASH_IT_ALL_BANK1
#define | FLASH_IT_EOP_BANK2 (FLASH_CR_EOPIE | 0x80000000U)
#define | FLASH_IT_WRPERR_BANK2 (FLASH_CR_WRPERRIE | 0x80000000U)
#define | FLASH_IT_PGSERR_BANK2 (FLASH_CR_PGSERRIE | 0x80000000U)
#define | FLASH_IT_STRBERR_BANK2 (FLASH_CR_STRBERRIE | 0x80000000U)
#define | FLASH_IT_INCERR_BANK2 (FLASH_CR_INCERRIE | 0x80000000U)
#define | FLASH_IT_OPERR_BANK2 (FLASH_CR_OPERRIE | 0x80000000U)
#define | FLASH_IT_RDPERR_BANK2 (FLASH_CR_RDPERRIE | 0x80000000U)
#define | FLASH_IT_RDSERR_BANK2 (FLASH_CR_RDSERRIE | 0x80000000U)
#define | FLASH_IT_SNECCERR_BANK2 (FLASH_CR_SNECCERRIE | 0x80000000U)
#define | FLASH_IT_DBECCERR_BANK2 (FLASH_CR_DBECCERRIE | 0x80000000U)
#define | FLASH_IT_CRCEND_BANK2 (FLASH_CR_CRCENDIE | 0x80000000U)
#define | FLASH_IT_ALL_BANK2

Detailed Description

FLASH Interrupt definition.

Define Documentation

#define FLASH_IT_ALL_BANK1
Value:
(FLASH_IT_EOP_BANK1       | FLASH_IT_WRPERR_BANK1    | \
                                            FLASH_IT_PGSERR_BANK1    | FLASH_IT_STRBERR_BANK1   | \
                                            FLASH_IT_INCERR_BANK1    | FLASH_IT_OPERR_BANK1     | \
                                            FLASH_IT_RDPERR_BANK1    | FLASH_IT_RDSERR_BANK1    | \
                                            FLASH_CR_SNECCERRIE | FLASH_CR_DBECCERRIE | \
                                            FLASH_CR_CRCENDIE )

Definition at line 261 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_ALL_BANK2
Value:
(FLASH_IT_EOP_BANK2       | FLASH_IT_WRPERR_BANK1    | \
                                            FLASH_IT_PGSERR_BANK2    | FLASH_IT_STRBERR_BANK1   | \
                                            FLASH_IT_INCERR_BANK2    | FLASH_IT_OPERR_BANK1     | \
                                            FLASH_IT_RDPERR_BANK2    | FLASH_IT_RDSERR_BANK1    | \
                                            FLASH_CR_SNECCERRIE | FLASH_CR_DBECCERRIE | \
                                            FLASH_CR_CRCENDIE )

Definition at line 281 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_CRCEND_BANK1 FLASH_CR_CRCENDIE

CRC End on Bank 1 Interrupt source

Definition at line 259 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_CRCEND_BANK2 (FLASH_CR_CRCENDIE | 0x80000000U)

CRC End on Bank 2 Interrupt source

Definition at line 278 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_DBECCERR_BANK1 FLASH_CR_DBECCERRIE

Double Detection ECC Error on Bank 1 Interrupt source

Definition at line 258 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_DBECCERR_BANK2 (FLASH_CR_DBECCERRIE | 0x80000000U)

Double Detection ECC Error on Bank 2 Interrupt source

Definition at line 277 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE

End of FLASH Bank 1 Operation Interrupt source

Definition at line 249 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_EOP_BANK2 (FLASH_CR_EOPIE | 0x80000000U)

End of FLASH Bank 2 Operation Interrupt source

Definition at line 268 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_INCERR_BANK1 FLASH_CR_INCERRIE

Inconsistency Error on Bank 1 Interrupt source

Definition at line 253 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_INCERR_BANK2 (FLASH_CR_INCERRIE | 0x80000000U)

Inconsistency Error on Bank 2 Interrupt source

Definition at line 272 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_OPERR_BANK1 FLASH_CR_OPERRIE

Operation Error on Bank 1 Interrupt source

Definition at line 254 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_OPERR_BANK2 (FLASH_CR_OPERRIE | 0x80000000U)

Operation Error on Bank 2 Interrupt source

Definition at line 273 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_PGSERR_BANK1 FLASH_CR_PGSERRIE

Program Sequence Error on Bank 1 Interrupt source

Definition at line 251 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_PGSERR_BANK2 (FLASH_CR_PGSERRIE | 0x80000000U)

Program Sequence Error on Bank 2 Interrupt source

Definition at line 270 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_RDPERR_BANK1 FLASH_CR_RDPERRIE

Read protection Error on Bank 1 Interrupt source

Definition at line 255 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_RDPERR_BANK2 (FLASH_CR_RDPERRIE | 0x80000000U)

Read protection Error on Bank 2 Interrupt source

Definition at line 274 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_RDSERR_BANK1 FLASH_CR_RDSERRIE

Read Secured Error on Bank 1 Interrupt source

Definition at line 256 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_RDSERR_BANK2 (FLASH_CR_RDSERRIE | 0x80000000U)

Read Secured Error on Bank 2 Interrupt source

Definition at line 275 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_SNECCERR_BANK1 FLASH_CR_SNECCERRIE

Single ECC Error Correction on Bank 1 Interrupt source

Definition at line 257 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_SNECCERR_BANK2 (FLASH_CR_SNECCERRIE | 0x80000000U)

Single ECC Error Correction on Bank 2 Interrupt source

Definition at line 276 of file stm32h7xx_hal_flash.h.

#define FLASH_IT_STRBERR_BANK1 FLASH_CR_STRBERRIE

Strobe Error on Bank 1 Interrupt source

Definition at line 252 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_STRBERR_BANK2 (FLASH_CR_STRBERRIE | 0x80000000U)

Strobe Error on Bank 2 Interrupt source

Definition at line 271 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_WRPERR_BANK1 FLASH_CR_WRPERRIE

Write Protection Error on Bank 1 Interrupt source

Definition at line 250 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_WRPERR_BANK2 (FLASH_CR_WRPERRIE | 0x80000000U)

Write Protection Error on Bank 2 Interrupt source

Definition at line 269 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH Program Parallelism

Defines
FLASH Program Parallelism
FLASH Exported Constants

Defines

#define | FLASH_PSIZE_BYTE ((uint32_t)0x00000000U)
#define | FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0)
#define | FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1)
#define | FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE)
#define | CR_PSIZE_MASK ((uint32_t)0xFFFFFFCFU)

Define Documentation

#define CR_PSIZE_MASK ((uint32_t)0xFFFFFFCFU)

Definition at line 298 of file stm32h7xx_hal_flash.h.

#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U)

Definition at line 294 of file stm32h7xx_hal_flash.h.

#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE)

Definition at line 297 of file stm32h7xx_hal_flash.h.

#define FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0)

Definition at line 295 of file stm32h7xx_hal_flash.h.

#define FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1)

Definition at line 296 of file stm32h7xx_hal_flash.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH Keys

Defines
FLASH Keys
FLASH Exported Constants

Defines

#define | FLASH_KEY1 ((uint32_t)0x45670123U)
#define | FLASH_KEY2 ((uint32_t)0xCDEF89ABU)
#define | FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU)
#define | FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU)

Define Documentation

#define FLASH_KEY1 ((uint32_t)0x45670123U)

Definition at line 307 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_Unlock(), HAL_FLASHEx_Unlock_Bank1(), and HAL_FLASHEx_Unlock_Bank2().

#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU)

Definition at line 308 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_Unlock(), HAL_FLASHEx_Unlock_Bank1(), and HAL_FLASHEx_Unlock_Bank2().

#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU)

Definition at line 309 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_OB_Unlock().

#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU)

Definition at line 310 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_OB_Unlock().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH Sectors

Defines
FLASH Sectors
FLASH Exported Constants

Defines

#define | FLASH_SECTOR_0 ((uint32_t)0U)
#define | FLASH_SECTOR_1 ((uint32_t)1U)
#define | FLASH_SECTOR_2 ((uint32_t)2U)
#define | FLASH_SECTOR_3 ((uint32_t)3U)
#define | FLASH_SECTOR_4 ((uint32_t)4U)
#define | FLASH_SECTOR_5 ((uint32_t)5U)
#define | FLASH_SECTOR_6 ((uint32_t)6U)
#define | FLASH_SECTOR_7 ((uint32_t)7U)

Define Documentation

#define FLASH_SECTOR_0 ((uint32_t)0U)

Sector Number 0

Definition at line 318 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_1 ((uint32_t)1U)

Sector Number 1

Definition at line 319 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_2 ((uint32_t)2U)

Sector Number 2

Definition at line 320 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_3 ((uint32_t)3U)

Sector Number 3

Definition at line 321 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_4 ((uint32_t)4U)

Sector Number 4

Definition at line 322 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_5 ((uint32_t)5U)

Sector Number 5

Definition at line 323 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_6 ((uint32_t)6U)

Sector Number 6

Definition at line 324 of file stm32h7xx_hal_flash.h.

#define FLASH_SECTOR_7 ((uint32_t)7U)

Sector Number 7

Definition at line 325 of file stm32h7xx_hal_flash.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH Exported Macros

Defines
FLASH Exported Macros
FLASH | FLASHEx

Defines

#define | __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
Set the FLASH Latency.
#define | __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
Get the FLASH Latency.
#define | __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 |= (__INTERRUPT__))
Enable the specified FLASH interrupt.
#define | __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFF))
#define | __HAL_FLASH_ENABLE_IT(__INTERRUPT__)
#define | __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 &= ~(uint32_t)(__INTERRUPT__))
Disable the specified FLASH interrupt.
#define | __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFF))
#define | __HAL_FLASH_DISABLE_IT(__INTERRUPT__)
#define | __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) (READ_BIT(FLASH->SR1, (__FLAG__)) == (__FLAG__))
Checks whether the specified FLASH flag is set or not.
#define | __HAL_FLASH_GET_FLAG_BANK2(__FLAG__) (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFF)) == (((__FLAG__) & 0x7FFFFFFF)))
#define | __HAL_FLASH_GET_FLAG(__FLAG__)
#define | __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) WRITE_REG(FLASH->CCR1, (__FLAG__))
Clear the specified FLASH flag.
#define | __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__) WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFF))
#define | __HAL_FLASH_CLEAR_FLAG(__FLAG__)
#define | __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14)
Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)

Define Documentation

#define __HAL_FLASH_CALC_BOOT_BASE_ADR ( __ADDRESS__ ) ((__ADDRESS__) >> 14)

Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)

Note:
Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].
Parameters:
__ADDRESS__,: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)
Return values:
The FLASH Boot Base Adress

Definition at line 461 of file stm32h7xx_hal_flash_ex.h.

#define __HAL_FLASH_CLEAR_FLAG ( __FLAG__ )
Value:
(IS_FLASH_FLAG_BANK1(__FLAG__) ?  __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) : \
                                                   __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__))

Definition at line 516 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation().

#define __HAL_FLASH_CLEAR_FLAG_BANK1 ( __FLAG__ ) WRITE_REG(FLASH->CCR1, (__FLAG__))

Clear the specified FLASH flag.

Parameters:
__FLAG__,: specifies the FLASH flags to clear. This parameter can be any combination of the following values:
  • FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag
  • FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag
  • FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag
  • FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag
  • FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag
  • FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag
  • FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag
  • FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag
  • FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag
  • FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag
  • FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag
In case of Bank 2 This parameter can be any combination of the following values :
  • FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag
  • FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag
  • FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag
  • FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag
  • FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag
  • FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag
  • FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag
  • FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag
  • FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag
  • FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag
  • FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag
Return values:
none

Definition at line 512 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define __HAL_FLASH_CLEAR_FLAG_BANK2 ( __FLAG__ ) WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFF))

Definition at line 514 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define __HAL_FLASH_DISABLE_IT ( __INTERRUPT__ )
Value:
(IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
                                                __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) : \
                                                __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__))

Definition at line 430 of file stm32h7xx_hal_flash.h.

#define __HAL_FLASH_DISABLE_IT_BANK1 ( __INTERRUPT__ ) (FLASH->CR1 &= ~(uint32_t)(__INTERRUPT__))

Disable the specified FLASH interrupt.

Parameters:
__INTERRUPT__ : FLASH interrupt In case of Bank 1 This parameter can be any combination of the following values:
  • FLASH_IT_EOP_BANK1 : End of FLASH Bank 1 Operation Interrupt source
  • FLASH_IT_WRPERR_BANK1 : Write Protection Error on Bank 1 Interrupt source
  • FLASH_IT_PGSERR_BANK1 : Program Sequence Error on Bank 1 Interrupt source
  • FLASH_IT_STRBERR_BANK1 : Strobe Error on Bank 1 Interrupt source
  • FLASH_IT_INCERR_BANK1 : Inconsistency Error on Bank 1 Interrupt source
  • FLASH_IT_OPERR_BANK1 : Operation Error on Bank 1 Interrupt source
  • FLASH_IT_RDPERR_BANK1 : Read protection Error on Bank 1 Interrupt source
  • FLASH_IT_RDSERR_BANK1 : Read secure Error on Bank 1 Interrupt source
  • FLASH_IT_SNECCERR_BANK1 : Single ECC Error Correction on Bank 1 Interrupt source
  • FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source
  • FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source
In case of Bank 2 This parameter can be any combination of the following values: *
  • FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source
  • FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source
  • FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source
  • FLASH_IT_STRBERR_BANK2 : Strobe Error on Bank 2 Interrupt source
  • FLASH_IT_INCERR_BANK2 : Inconsistency Error on Bank 2 Interrupt source
  • FLASH_IT_OPERR_BANK2 : Operation Error on Bank 2 Interrupt source
  • FLASH_IT_RDPERR_BANK2 : Read protection Error on Bank 2 Interrupt source
  • FLASH_IT_RDSERR_BANK2 : Read secure Error on Bank 2 Interrupt source
  • FLASH_IT_SNECCERR_BANK2 : Single ECC Error Correction on Bank 2 Interrupt source
  • FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source
  • FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source
Return values:
none

Definition at line 426 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

#define __HAL_FLASH_DISABLE_IT_BANK2 ( __INTERRUPT__ ) (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFF))

Definition at line 428 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

#define __HAL_FLASH_ENABLE_IT ( __INTERRUPT__ )
Value:
(IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
                                                 __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) : \
                                                 __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__))

Definition at line 389 of file stm32h7xx_hal_flash.h.

#define __HAL_FLASH_ENABLE_IT_BANK1 ( __INTERRUPT__ ) (FLASH->CR1 |= (__INTERRUPT__))

Enable the specified FLASH interrupt.

Parameters:
__INTERRUPT__ : FLASH interrupt In case of Bank 1 This parameter can be any combination of the following values:
  • FLASH_IT_EOP_BANK1 : End of FLASH Bank 1 Operation Interrupt source
  • FLASH_IT_WRPERR_BANK1 : Write Protection Error on Bank 1 Interrupt source
  • FLASH_IT_PGSERR_BANK1 : Program Sequence Error on Bank 1 Interrupt source
  • FLASH_IT_STRBERR_BANK1 : Strobe Error on Bank 1 Interrupt source
  • FLASH_IT_INCERR_BANK1 : Inconsistency Error on Bank 1 Interrupt source
  • FLASH_IT_OPERR_BANK1 : Operation Error on Bank 1 Interrupt source
  • FLASH_IT_RDPERR_BANK1 : Read protection Error on Bank 1 Interrupt source
  • FLASH_IT_RDSERR_BANK1 : Read secure Error on Bank 1 Interrupt source
  • FLASH_IT_SNECCERR_BANK1 : Single ECC Error Correction on Bank 1 Interrupt source
  • FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source
  • FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source
In case of Bank 2 This parameter can be any combination of the following values: *
  • FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source
  • FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source
  • FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source
  • FLASH_IT_STRBERR_BANK2 : Strobe Error on Bank 2 Interrupt source
  • FLASH_IT_INCERR_BANK2 : Inconsistency Error on Bank 2 Interrupt source
  • FLASH_IT_OPERR_BANK2 : Operation Error on Bank 2 Interrupt source
  • FLASH_IT_RDPERR_BANK2 : Read protection Error on Bank 2 Interrupt source
  • FLASH_IT_RDSERR_BANK2 : Read secure Error on Bank 2 Interrupt source
  • FLASH_IT_SNECCERR_BANK2 : Single ECC Error Correction on Bank 2 Interrupt source
  • FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source
  • FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source
Return values:
none

Definition at line 385 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define __HAL_FLASH_ENABLE_IT_BANK2 ( __INTERRUPT__ ) (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFF))

Definition at line 387 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define __HAL_FLASH_GET_FLAG ( __FLAG__ )
Value:
(IS_FLASH_FLAG_BANK1(__FLAG__) ?  __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) : \
                                                 __HAL_FLASH_GET_FLAG_BANK2(__FLAG__))

Definition at line 477 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation().

#define __HAL_FLASH_GET_FLAG_BANK1 ( __FLAG__ ) (READ_BIT(FLASH->SR1, (__FLAG__)) == (__FLAG__))

Checks whether the specified FLASH flag is set or not.

Parameters:
__FLAG__,: specifies the FLASH flag to check. In case of Bank 1 This parameter can be any combination of the following values :
  • FLASH_FLAG_BSY_BANK1 : FLASH Bank 1 Busy flag
  • FLASH_FLAG_WBNE_BANK1 : Waiting for Data to Write on Bank 1 flag
  • FLASH_FLAG_QW_BANK1 : Write Waiting in Operation Queue on Bank 1 flag
  • FLASH_FLAG_CRC_BUSY_BANK1 : CRC module is working on Bank 1 flag
  • FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag
  • FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag
  • FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag
  • FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag
  • FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag
  • FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag
  • FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag
  • FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag
  • FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag
  • FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag
  • FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag
In case of Bank 2 This parameter can be any combination of the following values :
  • FLASH_FLAG_BSY_BANK2 : FLASH Bank 2 Busy flag
  • FLASH_FLAG_WBNE_BANK2 : Waiting for Data to Write on Bank 2 flag
  • FLASH_FLAG_QW_BANK2 : Write Waiting in Operation Queue on Bank 2 flag
  • FLASH_FLAG_CRC_BUSY_BANK2 : CRC module is working on Bank 2 flag
  • FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag
  • FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag
  • FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag
  • FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag
  • FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag
  • FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag
  • FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag
  • FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag
  • FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag
  • FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag
  • FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag
Return values:
The new state of FLASH_FLAG (SET or RESET).

Definition at line 473 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), HAL_FLASH_IRQHandler(), and HAL_FLASH_Program().

#define __HAL_FLASH_GET_FLAG_BANK2 ( __FLAG__ ) (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFF)) == (((__FLAG__) & 0x7FFFFFFF)))

Definition at line 475 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), HAL_FLASH_IRQHandler(), and HAL_FLASH_Program().

#define __HAL_FLASH_GET_LATENCY ( ) (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))

Get the FLASH Latency.

Return values:
FLASH Latency The value of this parameter depend on device used within the same series

Definition at line 352 of file stm32h7xx_hal_flash.h.

#define __HAL_FLASH_SET_LATENCY ( __LATENCY__ ) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))

Set the FLASH Latency.

Parameters:
__LATENCY__,: FLASH Latency The value of this parameter depend on device used within the same series
Return values:
none

Definition at line 344 of file stm32h7xx_hal_flash.h.

Referenced by HAL_RCC_ClockConfig().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH Private Variables

FLASH Private Variables
FLASH
Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH Private Constants

Defines
FLASH Private Constants
FLASH

Defines

#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */

Define Documentation

#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */

Definition at line 126 of file stm32h7xx_hal_flash.c.

Referenced by HAL_FLASH_OB_Launch(), and HAL_FLASH_Program().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH Definitions

Defines
FLASH Definitions
FLASH Private Macros

Defines

#define IS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD)

Define Documentation

#define IS_FLASH_TYPEPROGRAM ( VALUE ) ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD)

Definition at line 600 of file stm32h7xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH BANK IT Definitions

Defines
FLASH BANK IT Definitions
FLASH Private Macros

Defines

#define | IS_FLASH_IT_BANK1(IT) (((IT) & FLASH_IT_ALL_BANK1) == (IT))
#define | IS_FLASH_IT_BANK2(IT) (((IT) & FLASH_IT_ALL_BANK2) == (IT))

Define Documentation

#define IS_FLASH_IT_BANK1 ( IT ) (((IT) & FLASH_IT_ALL_BANK1) == (IT))

Definition at line 608 of file stm32h7xx_hal_flash.h.

#define IS_FLASH_IT_BANK2 ( IT ) (((IT) & FLASH_IT_ALL_BANK2) == (IT))

Definition at line 610 of file stm32h7xx_hal_flash.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH Address

Defines
FLASH Address
FLASH Private Macros

Defines

#define | IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < (FLASH_BANK1_BASE + FLASH_BANK_SIZE) ))
#define | IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) < (FLASH_BANK2_BASE + FLASH_BANK_SIZE) ))
#define | IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS))
#define | IS_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= (0x3FFF0000U))
#define | IS_FLASH_BANK(BANK)
#define | IS_FLASH_BANK_EXCLUSIVE(BANK)

Define Documentation

#define IS_BOOT_ADDRESS ( ADDRESS ) ((ADDRESS) <= (0x3FFF0000U))

Definition at line 628 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_OB_BootAddConfig().

#define IS_FLASH_BANK ( BANK )
Value:
(((BANK) == FLASH_BANK_1)  || \
                                            ((BANK) == FLASH_BANK_2)  || \
                                            ((BANK) == FLASH_BANK_BOTH))

Definition at line 630 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_MassErase(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_PCROPConfig(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

#define IS_FLASH_BANK_EXCLUSIVE ( BANK )
Value:
(((BANK) == FLASH_BANK_1)  || \
                                            ((BANK) == FLASH_BANK_2))

Definition at line 634 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_Erase_Sector(), FLASH_OB_GetPCROP(), FLASH_OB_GetSecureArea(), FLASH_OB_GetWRP(), FLASH_OB_SecureAreaConfig(), FLASH_WaitForLastOperation(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBGetConfig().

#define IS_FLASH_PROGRAM_ADDRESS ( ADDRESS ) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS))

Definition at line 626 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_OB_PCROPConfig(), HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define IS_FLASH_PROGRAM_ADDRESS_BANK1 ( ADDRESS ) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < (FLASH_BANK1_BASE + FLASH_BANK_SIZE) ))

Definition at line 624 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_OB_PCROPConfig(), FLASH_OB_SecureAreaConfig(), HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define IS_FLASH_PROGRAM_ADDRESS_BANK2 ( ADDRESS ) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) < (FLASH_BANK2_BASE + FLASH_BANK_SIZE) ))

Definition at line 625 of file stm32h7xx_hal_flash.h.

Referenced by FLASH_OB_PCROPConfig(), and FLASH_OB_SecureAreaConfig().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH Private Macros

Modules | Defines
FLASH Private Macros
FLASH

Modules

FLASH Definitions
FLASH BANK IT Definitions
FLASH Address

Defines

#define | IS_FLASH_FLAG_BANK1(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))
#define | IS_FLASH_FLAG_BANK2(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))

Define Documentation

#define IS_FLASH_FLAG_BANK1 ( FLAG ) (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))

Definition at line 616 of file stm32h7xx_hal_flash.h.

#define IS_FLASH_FLAG_BANK2 ( FLAG ) (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))

Definition at line 618 of file stm32h7xx_hal_flash.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH_Exported_Functions_Group1

Functions
FLASH_Exported_Functions_Group1
FLASH_Exported_Functions

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t DataAddress)
Program flash word of 256 bits at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t DataAddress)
Program flash words of 256 bits at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
This function handles FLASH interrupt request.
void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.

Function Documentation

void HAL_FLASH_EndOfOperationCallback ( uint32_t ReturnValue )

FLASH end of operation interrupt callback.

Parameters:
ReturnValue The value saved in this parameter depends on the ongoing procedure Mass Erase Bank number which has been requested to erase Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that all the selected sectors have been erased) Program Address which was selected for data program
Return values:
None

Definition at line 550 of file stm32h7xx_hal_flash.c.

Referenced by HAL_FLASH_IRQHandler().

void HAL_FLASH_IRQHandler ( void )

This function handles FLASH interrupt request.

Return values:
None

Definition at line 330 of file stm32h7xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG_BANK1, __HAL_FLASH_CLEAR_FLAG_BANK2, __HAL_FLASH_DISABLE_IT_BANK1, __HAL_FLASH_DISABLE_IT_BANK2, __HAL_FLASH_GET_FLAG_BANK1, __HAL_FLASH_GET_FLAG_BANK2, FLASH_ProcessTypeDef::Address, FLASH_BANK_1, FLASH_BANK_2, FLASH_Erase_Sector(), FLASH_FLAG_ALL_ERRORS_BANK1, FLASH_FLAG_ALL_ERRORS_BANK2, FLASH_FLAG_EOP_BANK1, FLASH_FLAG_EOP_BANK2, FLASH_FLAG_INCERR_BANK1, FLASH_FLAG_INCERR_BANK2, FLASH_FLAG_OPERR_BANK1, FLASH_FLAG_OPERR_BANK2, FLASH_FLAG_PGSERR_BANK1, FLASH_FLAG_PGSERR_BANK2, FLASH_FLAG_STRBER_BANK1R, FLASH_FLAG_STRBER_BANK2R, FLASH_FLAG_WRPERR_BANK1, FLASH_FLAG_WRPERR_BANK2, FLASH_IT_EOP_BANK1, FLASH_IT_EOP_BANK2, FLASH_IT_INCERR_BANK1, FLASH_IT_INCERR_BANK2, FLASH_IT_OPERR_BANK1, FLASH_IT_OPERR_BANK2, FLASH_IT_PGSERR_BANK1, FLASH_IT_PGSERR_BANK2, FLASH_IT_STRBERR_BANK1, FLASH_IT_STRBERR_BANK2, FLASH_IT_WRPERR_BANK1, FLASH_IT_WRPERR_BANK2, FLASH_PROC_ALLBANK_MASSERASE, FLASH_PROC_MASSERASE_BANK1, FLASH_PROC_MASSERASE_BANK2, FLASH_PROC_NONE, FLASH_PROC_PROGRAM_BANK1, FLASH_PROC_PROGRAM_BANK2, FLASH_PROC_SECTERASE_BANK1, FLASH_PROC_SECTERASE_BANK2, FLASH_SetErrorCode(), HAL_FLASH_EndOfOperationCallback(), HAL_FLASH_OperationErrorCallback(), FLASH_ProcessTypeDef::NbSectorsToErase, FLASH_ProcessTypeDef::ProcedureOnGoing, FLASH_ProcessTypeDef::Sector, and FLASH_ProcessTypeDef::VoltageForErase.

void HAL_FLASH_OperationErrorCallback ( uint32_t ReturnValue )

FLASH operation error interrupt callback.

Parameters:
ReturnValue The value saved in this parameter depends on the ongoing procedure Mass Erase: Bank number which has been requested to erase Sectors Erase: Sector number which returned an error Program: Address which was selected for data program
Return values:
None

Definition at line 565 of file stm32h7xx_hal_flash.c.

Referenced by HAL_FLASH_IRQHandler().

HAL_StatusTypeDef HAL_FLASH_Program | ( | uint32_t | TypeProgram,
 |  | uint32_t | FlashAddress,
 |  | uint64_t | DataAddress
 | ) |  |

Program flash word of 256 bits at a specified address.

Parameters:
TypeProgram | Indicate the way to program at a specified address. This parameter can be a value of FLASH Type Program
FlashAddress | specifies the address to be programmed.
DataAddress | specifies the address of data (256 bits) to be programmed
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 165 of file stm32h7xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG_BANK1, __HAL_FLASH_CLEAR_FLAG_BANK2, __HAL_FLASH_GET_FLAG_BANK1, __HAL_FLASH_GET_FLAG_BANK2, assert_param, FLASH_BANK_1, FLASH_BANK_2, FLASH_FLAG_ALL_ERRORS_BANK1, FLASH_FLAG_ALL_ERRORS_BANK2, FLASH_FLAG_EOP_BANK1, FLASH_FLAG_EOP_BANK2, FLASH_FLAG_QW_BANK1, FLASH_FLAG_QW_BANK2, FLASH_FLAG_WBNE_BANK1, FLASH_FLAG_WBNE_BANK2, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_FLASH_PROGRAM_ADDRESS, IS_FLASH_PROGRAM_ADDRESS_BANK1, and IS_FLASH_TYPEPROGRAM.

HAL_StatusTypeDef HAL_FLASH_Program_IT | ( | uint32_t | TypeProgram,
 |  | uint32_t | FlashAddress,
 |  | uint64_t | DataAddress
 | ) |  |

Program flash words of 256 bits at a specified address with interrupt enabled.

Parameters:
TypeProgram | Indicate the way to program at a specified address. This parameter can be a value of FLASH Type Program
FlashAddress | specifies the address to be programmed.
DataAddress | specifies the address of data (256 bits) to be programmed
Return values:
HAL Status

Definition at line 263 of file stm32h7xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG_BANK1, __HAL_FLASH_CLEAR_FLAG_BANK2, __HAL_FLASH_ENABLE_IT_BANK1, __HAL_FLASH_ENABLE_IT_BANK2, FLASH_ProcessTypeDef::Address, assert_param, FLASH_BANK_1, FLASH_BANK_2, FLASH_FLAG_ALL_ERRORS_BANK1, FLASH_FLAG_ALL_ERRORS_BANK2, FLASH_FLAG_EOP_BANK1, FLASH_FLAG_EOP_BANK2, FLASH_IT_EOP_BANK1, FLASH_IT_EOP_BANK2, FLASH_IT_INCERR_BANK1, FLASH_IT_INCERR_BANK2, FLASH_IT_OPERR_BANK1, FLASH_IT_OPERR_BANK2, FLASH_IT_PGSERR_BANK1, FLASH_IT_PGSERR_BANK2, FLASH_IT_STRBERR_BANK1, FLASH_IT_STRBERR_BANK2, FLASH_IT_WRPERR_BANK1, FLASH_IT_WRPERR_BANK2, FLASH_PROC_PROGRAM_BANK1, FLASH_PROC_PROGRAM_BANK2, IS_FLASH_PROGRAM_ADDRESS, IS_FLASH_PROGRAM_ADDRESS_BANK1, IS_FLASH_TYPEPROGRAM, and FLASH_ProcessTypeDef::ProcedureOnGoing.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH_Exported_Functions_Group2

Functions
FLASH_Exported_Functions_Group2
FLASH_Exported_Functions

Functions

HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control registers access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Locks the FLASH control registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.

Function Documentation

HAL_StatusTypeDef HAL_FLASH_Lock ( void )

Locks the FLASH control registers access.

Return values:
HAL Status

Definition at line 619 of file stm32h7xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Launch ( void )

Launch the option byte loading.

Return values:
HAL Status

Definition at line 666 of file stm32h7xx_hal_flash.c.

References FLASH_OB_WaitForLastOperation(), and FLASH_TIMEOUT_VALUE.

HAL_StatusTypeDef HAL_FLASH_OB_Lock ( void )

Lock the FLASH Option Control Registers access.

Return values:
HAL Status

Definition at line 654 of file stm32h7xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Unlock ( void )

Unlock the FLASH Option Control Registers access.

Return values:
HAL Status

Definition at line 634 of file stm32h7xx_hal_flash.c.

References FLASH_OPT_KEY1, and FLASH_OPT_KEY2.

HAL_StatusTypeDef HAL_FLASH_Unlock ( void )

Unlock the FLASH control registers access.

Return values:
HAL Status

Definition at line 595 of file stm32h7xx_hal_flash.c.

References FLASH_KEY1, and FLASH_KEY2.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH_Exported_Functions_Group3

Functions
FLASH_Exported_Functions_Group3
FLASH_Exported_Functions

Functions

uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout, uint32_t Bank)
Wait for a FLASH operation to complete.
HAL_StatusTypeDef | FLASH_OB_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH Option Bytes change operation to complete.

Function Documentation

HAL_StatusTypeDef FLASH_OB_WaitForLastOperation ( uint32_t Timeout )

Wait for a FLASH Option Bytes change operation to complete.

Parameters:
Timeout maximum flash operation timeout
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 820 of file stm32h7xx_hal_flash.c.

References FLASH_ProcessTypeDef::ErrorCode, HAL_FLASH_ERROR_OB_CHANGE, and HAL_GetTick().

Referenced by FLASH_OB_UserConfig(), and HAL_FLASH_OB_Launch().

HAL_StatusTypeDef FLASH_WaitForLastOperation | ( | uint32_t | Timeout,
 |  | uint32_t | Bank
 | ) |  |

Wait for a FLASH operation to complete.

Parameters:
Timeout | maximum flash operation timeout
Bank | flash FLASH_BANK_1 or FLASH_BANK_2
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 742 of file stm32h7xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_GET_FLAG, assert_param, FLASH_BANK_1, FLASH_BANK_2, FLASH_FLAG_ALL_ERRORS_BANK1, FLASH_FLAG_ALL_ERRORS_BANK2, FLASH_FLAG_BSY_BANK1, FLASH_FLAG_BSY_BANK2, FLASH_FLAG_QW_BANK1, FLASH_FLAG_QW_BANK2, FLASH_FLAG_WBNE_BANK1, FLASH_FLAG_WBNE_BANK2, FLASH_SetErrorCode(), HAL_GetTick(), and IS_FLASH_BANK_EXCLUSIVE.

Referenced by FLASH_OB_BootAddConfig(), FLASH_OB_BOR_LevelConfig(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_PCROPConfig(), FLASH_OB_RDPConfig(), FLASH_OB_SecureAreaConfig(), HAL_FLASH_Program(), and HAL_FLASHEx_Erase().

uint32_t HAL_FLASH_GetError ( void )

Get the specific FLASH error flag.

Return values:
HAL_FLASH_ERRORCode The returned value can be:
  • HAL_FLASH_ERROR_NONE: No error set
  • HAL_FLASH_ERROR_WRP_BANK1: Write Protection Error on Bank 1
  • HAL_FLASH_ERROR_PGS_BANK1 : Program Sequence Error on Bank 1
  • HAL_FLASH_ERROR_STRB_BANK1 : Strobe Error on Bank 1
  • HAL_FLASH_ERROR_INC_BANK1 : Inconsistency Error on Bank 1
  • HAL_FLASH_ERROR_OPE_BANK1 : Operation Error on Bank 1
  • HAL_FLASH_ERROR_RDP_BANK1 : Read Protection Error on Bank 1
  • HAL_FLASH_ERROR_RDS_BANK1 : Read Secured Error on Bank 1
  • HAL_FLASH_ERROR_SNECC_BANK1: SNECC Error on Bank 1
  • HAL_FLASH_ERROR_DBECC_BANK1: Double Detection ECC on Bank 1
  • HAL_FLASH_ERROR_WRP_BANK2 : Write Protection Error on Bank 2
  • HAL_FLASH_ERROR_PGS_BANK2 : Program Sequence Error on Bank 2
  • HAL_FLASH_ERROR_STRB_BANK2 : Strobe Error on Bank 2
  • HAL_FLASH_ERROR_INC_BANK2 : Inconsistency Error on Bank 2
  • HAL_FLASH_ERROR_OPE_BANK2 : Operation Error on Bank 2
  • HAL_FLASH_ERROR_RDP_BANK2 : Read Protection Error on Bank 2
  • HAL_FLASH_ERROR_RDS_BANK2 : Read Secured Error on Bank 2
  • HAL_FLASH_ERROR_SNECC_BANK2: SNECC Error on Bank 2
  • HAL_FLASH_ERROR_DBECC_BANK2: Double Detection ECC on Bank 2

Definition at line 723 of file stm32h7xx_hal_flash.c.

References FLASH_ProcessTypeDef::ErrorCode.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH

Modules | Functions | Variables
FLASH
STM32H7xx_HAL_Driver

FLASH HAL module driver. More...

Modules

FLASH Private functions
FLASH Exported Types
FLASH Exported Constants
FLASH Exported Macros
FLASH Private Variables
FLASH Private Constants
FLASH Private Macros
FLASH_Exported_Functions

Functions

static void | FLASH_SetErrorCode (uint32_t Bank)
Set the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout, uint32_t Bank)
Wait for a FLASH operation to complete.
HAL_StatusTypeDef | FLASH_OB_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH Option Bytes change operation to complete.

Variables

FLASH_ProcessTypeDef pFlash

Detailed Description

FLASH HAL module driver.

Function Documentation

HAL_StatusTypeDef FLASH_OB_WaitForLastOperation ( uint32_t Timeout )

Wait for a FLASH Option Bytes change operation to complete.

Parameters:
Timeout maximum flash operation timeout
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 820 of file stm32h7xx_hal_flash.c.

References FLASH_ProcessTypeDef::ErrorCode, HAL_FLASH_ERROR_OB_CHANGE, and HAL_GetTick().

Referenced by FLASH_OB_UserConfig(), and HAL_FLASH_OB_Launch().

static void FLASH_SetErrorCode ( uint32_t Bank ) [static]

Set the specific FLASH error flag.

Return values:
None

Definition at line 854 of file stm32h7xx_hal_flash.c.

References __HAL_FLASH_GET_FLAG_BANK1, __HAL_FLASH_GET_FLAG_BANK2, FLASH_ProcessTypeDef::ErrorCode, FLASH_BANK_1, FLASH_BANK_2, FLASH_FLAG_DBECCE_BANK1RR, FLASH_FLAG_DBECCE_BANK2RR, FLASH_FLAG_INCERR_BANK1, FLASH_FLAG_INCERR_BANK2, FLASH_FLAG_OPERR_BANK1, FLASH_FLAG_OPERR_BANK2, FLASH_FLAG_PGSERR_BANK1, FLASH_FLAG_PGSERR_BANK2, FLASH_FLAG_RDPERR_BANK1, FLASH_FLAG_RDPERR_BANK2, FLASH_FLAG_RDSERR_BANK1, FLASH_FLAG_RDSERR_BANK2, FLASH_FLAG_SNECCE_BANK1RR, FLASH_FLAG_SNECCE_BANK2RR, FLASH_FLAG_STRBER_BANK1R, FLASH_FLAG_STRBER_BANK2R, FLASH_FLAG_WRPERR_BANK1, FLASH_FLAG_WRPERR_BANK2, HAL_FLASH_ERROR_DBECC_BANK1, HAL_FLASH_ERROR_DBECC_BANK2, HAL_FLASH_ERROR_INC_BANK1, HAL_FLASH_ERROR_INC_BANK2, HAL_FLASH_ERROR_NONE, HAL_FLASH_ERROR_OPE_BANK1, HAL_FLASH_ERROR_OPE_BANK2, HAL_FLASH_ERROR_PGS_BANK1, HAL_FLASH_ERROR_PGS_BANK2, HAL_FLASH_ERROR_RDP_BANK1, HAL_FLASH_ERROR_RDP_BANK2, HAL_FLASH_ERROR_RDS_BANK1, HAL_FLASH_ERROR_RDS_BANK2, HAL_FLASH_ERROR_SNECC_BANK1, HAL_FLASH_ERROR_SNECC_BANK2, HAL_FLASH_ERROR_STRB_BANK1, HAL_FLASH_ERROR_STRB_BANK2, HAL_FLASH_ERROR_WRP_BANK1, and HAL_FLASH_ERROR_WRP_BANK2.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

HAL_StatusTypeDef FLASH_WaitForLastOperation | ( | uint32_t | Timeout,
 |  | uint32_t | Bank
 | ) |  |

Wait for a FLASH operation to complete.

Parameters:
Timeout | maximum flash operation timeout
Bank | flash FLASH_BANK_1 or FLASH_BANK_2
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 742 of file stm32h7xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_GET_FLAG, assert_param, FLASH_BANK_1, FLASH_BANK_2, FLASH_FLAG_ALL_ERRORS_BANK1, FLASH_FLAG_ALL_ERRORS_BANK2, FLASH_FLAG_BSY_BANK1, FLASH_FLAG_BSY_BANK2, FLASH_FLAG_QW_BANK1, FLASH_FLAG_QW_BANK2, FLASH_FLAG_WBNE_BANK1, FLASH_FLAG_WBNE_BANK2, FLASH_SetErrorCode(), HAL_GetTick(), and IS_FLASH_BANK_EXCLUSIVE.

Referenced by FLASH_OB_BootAddConfig(), FLASH_OB_BOR_LevelConfig(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_PCROPConfig(), FLASH_OB_RDPConfig(), FLASH_OB_SecureAreaConfig(), HAL_FLASH_Program(), and HAL_FLASHEx_Erase().

Variable Documentation

FLASH_ProcessTypeDef pFlash

Definition at line 132 of file stm32h7xx_hal_flash.c.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Extended IO operation functions

Functions
Extended IO operation functions
Extended FLASH Private functions

Extended IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
Perform a mass erase or erase the specified FLASH memory sectors.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option byte configuration.
HAL_StatusTypeDef | HAL_FLASHEx_Unlock_Bank1 (void)
Unlock the FLASH Bank1 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_Lock_Bank1 (void)
Locks the FLASH Bank1 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_Unlock_Bank2 (void)
Unlock the FLASH Bank2 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_Lock_Bank2 (void)
Locks the FLASH Bank2 control registers access.
static void | FLASH_MassErase (uint32_t VoltageRange, uint32_t Banks)
Full erase of FLASH memory sectors.
void | FLASH_Erase_Sector (uint32_t Sector, uint32_t Banks, uint32_t VoltageRange)
Erase the specified FLASH memory sector.
static HAL_StatusTypeDef | FLASH_OB_EnableWRP (uint32_t WRPSector, uint32_t Banks)
Enable the write protection of the desired bank1 or bank 2 sectors.
static HAL_StatusTypeDef | FLASH_OB_DisableWRP (uint32_t WRPSector, uint32_t Banks)
Disable the write protection of the desired bank1 or bank 2 sectors.
static void | FLASH_OB_GetWRP (uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank)
Get the write protection of the given bank1 or bank 2 sectors.
static HAL_StatusTypeDef | FLASH_OB_RDPConfig (uint32_t RDPLevel)
Set the read protection level.
static uint32_t | FLASH_OB_GetRDP (void)
Get the read protection level.
static HAL_StatusTypeDef | FLASH_OB_UserConfig (uint32_t UserType, uint32_t UserConfig)
Program the FLASH User Option Byte.
static uint32_t | FLASH_OB_GetUser (void)
Return the FLASH User Option Byte value.
static HAL_StatusTypeDef | FLASH_OB_PCROPConfig (uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks)
Configure the Proprietary code readout protection of the desired addresses.
static void | FLASH_OB_GetPCROP (uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr, uint32_t Bank)
Get the Proprietary code readout protection configuration on a given Bank.
static HAL_StatusTypeDef | FLASH_OB_BOR_LevelConfig (uint8_t Level)
Set the BOR Level.
static uint32_t | FLASH_OB_GetBOR (void)
Get the BOR Level.
static HAL_StatusTypeDef | FLASH_OB_BootAddConfig (uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1)
Set Boot address.
static void | FLASH_OB_GetBootAdd (uint32_t *BootAddress0, uint32_t *BootAddress1)
Get Boot address.
static HAL_StatusTypeDef | FLASH_OB_SecureAreaConfig (uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks)
Set secure area configuration.
static void | FLASH_OB_GetSecureArea (uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank)
Set secure area configuration.

Detailed Description

Extended IO operation functions.

 ===============================================================================
                ##### Extended programming operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the Extension FLASH
    programming operations Operations.

Function Documentation

void FLASH_Erase_Sector | ( | uint32_t | Sector,
 |  | uint32_t | Banks,
 |  | uint32_t | VoltageRange
 | ) |  |

Erase the specified FLASH memory sector.

Parameters:
Sector FLASH sector to erase
Banks Banks to be erased This parameter can be one of the following values:
  • FLASH_BANK_1: Bank1 to be erased
  • FLASH_BANK_2: Bank2 to be erased
  • FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
VoltageRange The device program/erase parallelism. This parameter can be one of the following values:
  • FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits
  • FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits
  • FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits
  • FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 62 bits
Return values:
None

Definition at line 623 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, IS_FLASH_BANK_EXCLUSIVE, IS_FLASH_SECTOR, and IS_VOLTAGERANGE.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

static void FLASH_MassErase | ( | uint32_t | VoltageRange,
 |  | uint32_t | Banks
 | ) |  | [static]

Full erase of FLASH memory sectors.

Parameters:
VoltageRange The device program/erase parallelism. This parameter can be one of the following values:
  • FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits
  • FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits
  • FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits
  • FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits
Banks Banks to be erased This parameter can be one of the following values:
  • FLASH_BANK_1: Bank1 to be erased
  • FLASH_BANK_2: Bank2 to be erased
  • FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
Return values:
HAL Status

Definition at line 579 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, IS_FLASH_BANK, and IS_VOLTAGERANGE.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

static HAL_StatusTypeDef FLASH_OB_BootAddConfig | ( | uint32_t | BootOption,
 |  | uint32_t | BootAddress0,
 |  | uint32_t | BootAddress1
 | ) |  | [static]

Set Boot address.

Parameters:
BootOption | Boot address option byte to be programmed, This parameter must be a value of FLASHEx OB BOOT OPTION (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH)
BootAddress0 | Specifies the Boot Address 0
BootAddress1 | Specifies the Boot Address 1
Return values:
HAL Status

Definition at line 1185 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_BOOT_ADDRESS, IS_OB_BOOT_ADD_OPTION, OB_BOOT_ADD0, and OB_BOOT_ADD1.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig ( uint8_t Level ) [static]

Set the BOR Level.

Parameters:
Level specifies the Option Bytes BOR Reset Level. This parameter can be one of the following values:
  • OB_BOR_LEVEL1: Supply voltage ranges from 1.69V - 1.8V
  • OB_BOR_LEVEL2: Supply voltage ranges from 1.94V - 2.1V
  • OB_BOR_LEVEL3: Supply voltage ranges from 2.30V - 2.49V
Return values:
HAL Status

Definition at line 1139 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), and IS_OB_BOR_LEVEL.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_DisableWRP | ( | uint32_t | WRPSector,
 |  | uint32_t | Banks
 | ) |  | [static]

Disable the write protection of the desired bank1 or bank 2 sectors.

Parameters:
WRPSector specifies the sector(s) to disable write protection. This parameter can be one of the following values:
  • WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
Banks the specific bank to apply WRP sectors This parameter can be one of the following values:
  • FLASH_BANK_1: WRP disable on specified bank1 sectors
  • FLASH_BANK_2: WRP disable on specified bank2 sectors
  • FLASH_BANK_BOTH: WRP disable bank1 and bank2 specified sectors
Return values:
HAL FLASH State

Definition at line 726 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_FLASH_BANK, and IS_OB_WRP_SECTOR.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_EnableWRP | ( | uint32_t | WRPSector,
 |  | uint32_t | Banks
 | ) |  | [static]

Enable the write protection of the desired bank1 or bank 2 sectors.

Parameters:
WRPSector specifies the sector(s) to be write protected. This parameter can be one of the following values:
  • WRPSector: A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_0 or OB_WRP_SECTOR_All
Banks the specific bank to apply WRP sectors This parameter can be one of the following values:
  • FLASH_BANK_1: WRP enable on specified bank1 sectors
  • FLASH_BANK_2: WRP enable on specified bank2 sectors
  • FLASH_BANK_BOTH: WRP enable bank1 and bank2 specified sectors
Return values:
HAL FLASH State

Definition at line 664 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_FLASH_BANK, and IS_OB_WRP_SECTOR.

Referenced by HAL_FLASHEx_OBProgram().

static void FLASH_OB_GetBootAdd | ( | uint32_t * | BootAddress0,
 |  | uint32_t * | BootAddress1
 | ) |  | [static]

Get Boot address.

Parameters:
BootAddress0 | Specifies the Boot Address 0.
BootAddress1 | Specifies the Boot Address 1.
Return values:
HAL Status

Definition at line 1230 of file stm32h7xx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint32_t FLASH_OB_GetBOR ( void ) [static]

Get the BOR Level.

Return values:
The Option Bytes BOR Reset Level. This parameter can be one of the following values:
  • OB_BOR_LEVEL1: Supply voltage ranges from 1.69V - 1.8V
  • OB_BOR_LEVEL2: Supply voltage ranges from 1.94V - 2.1V
  • OB_BOR_LEVEL3: Supply voltage ranges from 2.30V - 2.49V

Definition at line 1170 of file stm32h7xx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_OBGetConfig().

static void FLASH_OB_GetPCROP | ( | uint32_t * | PCROPConfig,
 |  | uint32_t * | PCROPStartAddr,
 |  | uint32_t * | PCROPEndAddr,
 |  | uint32_t | Bank
 | ) |  | [static]

Get the Proprietary code readout protection configuration on a given Bank.

Parameters:
PCROPConfig | gives if the PCROP area for the given Bank shall be erased or not when RDP level decreased from Level 1 to Level 0 or during a mass erase.
PCROPStartAddr | gives the start address of the Proprietary code readout protection of the bank
PCROPEndAddr | gives the end address of the Proprietary code readout protection of the bank
Bank the specific bank to apply PCROP sectors This parameter can be exclusively one of the following values:
  • FLASH_BANK_1: PCROP on specified bank1 area
  • FLASH_BANK_2: PCROP on specified bank2 area
  • FLASH_BANK_BOTH: is not allowed here
Return values:
HAL Status

Definition at line 1102 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, FLASH_BANK_BOTH, and IS_FLASH_BANK_EXCLUSIVE.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint32_t FLASH_OB_GetRDP ( void ) [static]

Get the read protection level.

Return values:
RDPLevel specifies the read protection level. This parameter can be one of the following values:
  • OB_RDP_LEVEL_0: No protection
  • OB_RDP_LEVEL_1: Read protection of the memory
  • OB_RDP_LEVEL_2: Full chip protection

Definition at line 866 of file stm32h7xx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_OBGetConfig().

static void FLASH_OB_GetSecureArea | ( | uint32_t * | SecureAreaConfig,
 |  | uint32_t * | SecureAreaStartAddr,
 |  | uint32_t * | SecureAreaEndAddr,
 |  | uint32_t | Bank
 | ) |  | [static]

Set secure area configuration.

Parameters:
SecureAreaConfig | specify if the secure area will be deleted or not during next mass-erase,
SecureAreaStartAddr | Specifies the secure area start address
SecureAreaEndAddr | Specifies the secure area end address
Bank | Specifies the Bank
Return values:
HAL Status

Definition at line 1315 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, FLASH_BANK_BOTH, and IS_FLASH_BANK_EXCLUSIVE.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint32_t FLASH_OB_GetUser ( void ) [static]

Return the FLASH User Option Byte value.

Return values:
The FLASH User Option Bytes values IWDG_SW(Bit4), WWDG_SW(Bit 5), nRST_STOP(Bit 6), nRST_STDY(Bit 7), FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]), ePcROP_EN(Bit 21), SWAP_BANK_OPT(Bit 31) .

Definition at line 995 of file stm32h7xx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_OBGetConfig().

static void FLASH_OB_GetWRP | ( | uint32_t * | WRPState,
 |  | uint32_t * | WRPSector,
 |  | uint32_t | Bank
 | ) |  | [static]

Get the write protection of the given bank1 or bank 2 sectors.

Parameters:
WRPState gives the write protection state on the given bank . This parameter can be one of the following values:
  • WRPState: OB_WRPSTATE_DISABLE or OB_WRPSTATE_ENABLE
WRPSector gives the write protected sector(s) on the given bank . This parameter can be one of the following values:
  • WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
Bank the specific bank to apply WRP sectors This parameter can be exclusively one of the following values:
  • FLASH_BANK_1: Get bank1 WRP sectors
  • FLASH_BANK_2: Get bank2 WRP sectors
  • FLASH_BANK_BOTH: note allowed in this functions
Return values:
HAL FLASH State

Definition at line 789 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, FLASH_BANK_BOTH, IS_FLASH_BANK_EXCLUSIVE, OB_WRPSTATE_DISABLE, and OB_WRPSTATE_ENABLE.

Referenced by HAL_FLASHEx_OBGetConfig().

static HAL_StatusTypeDef FLASH_OB_PCROPConfig | ( | uint32_t | PCROPConfig,
 |  | uint32_t | PCROPStartAddr,
 |  | uint32_t | PCROPEndAddr,
 |  | uint32_t | Banks
 | ) |  | [static]

Configure the Proprietary code readout protection of the desired addresses.

Note:
To configure the PCROP options, the option lock bit OPTLOCK must be cleared with the call of the HAL_FLASH_OB_Unlock() function.
To validate the PCROP options, the option bytes must be reloaded through the call of the HAL_FLASH_OB_Launch() function.
Parameters:
PCROPConfig specifies if the PCROP area for the given Bank shall be erased or not when RDP level decreased from Level 1 to Level 0. This parameter must be a value of
  • FLASH_OB_PCROP_RDP enumeration
PCROPStartAddr | specifies the start address of the Proprietary code readout protection This parameter can be an address between begin and end of the bank
PCROPEndAddr | specifies the end address of the Proprietary code readout protection This parameter can be an address between PCROPStartAddr and end of the bank
Banks the specific bank to apply PCROP sectors This parameter can be one of the following values:
  • FLASH_BANK_1: PCROP on specified bank1 area
  • FLASH_BANK_2: PCROP on specified bank2 area
  • FLASH_BANK_BOTH: PCROP on specified bank1 and bank2 area (same config will be applied on both banks)
Return values:
HAL Status

Definition at line 1029 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_FLASH_BANK, IS_FLASH_PROGRAM_ADDRESS, IS_FLASH_PROGRAM_ADDRESS_BANK1, IS_FLASH_PROGRAM_ADDRESS_BANK2, and IS_OB_PCROP_RDP.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_RDPConfig ( uint32_t RDPLevel ) [static]

Set the read protection level.

Note:
To configure the RDP level, the option lock bit OPTLOCK must be cleared with the call of the HAL_FLASH_OB_Unlock() function.
To validate the RDP level, the option bytes must be reloaded through the call of the HAL_FLASH_OB_Launch() function.
!!! Warning : When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 !!!
Parameters:
RDPLevel specifies the read protection level. This parameter can be one of the following values:
  • OB_RDP_LEVEL_0: No protection
  • OB_RDP_LEVEL_1: Read protection of the memory
  • OB_RDP_LEVEL_2: Full chip protection
Return values:
HAL status

Definition at line 834 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), and IS_OB_RDP_LEVEL.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_SecureAreaConfig | ( | uint32_t | SecureAreaConfig,
 |  | uint32_t | SecureAreaStartAddr,
 |  | uint32_t | SecureAreaEndAddr,
 |  | uint32_t | Banks
 | ) |  | [static]

Set secure area configuration.

Parameters:
SecureAreaConfig | specify if the secure area will be deleted or not during next mass-erase,
SecureAreaStartAddr | Specifies the secure area start address
SecureAreaEndAddr | Specifies the secure area end address
Banks | Specifies the Bank
Return values:
HAL Status

Definition at line 1251 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_FLASH_BANK_EXCLUSIVE, IS_FLASH_PROGRAM_ADDRESS_BANK1, IS_FLASH_PROGRAM_ADDRESS_BANK2, and IS_OB_SECURE_RDP.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_UserConfig | ( | uint32_t | UserType,
 |  | uint32_t | UserConfig
 | ) |  | [static]

Program the FLASH User Option Byte.

Note:
To configure the user option bytes, the option lock bit OPTLOCK must be cleared with the call of the HAL_FLASH_OB_Unlock() function.
To validate the user option bytes, the option bytes must be reloaded through the call of the HAL_FLASH_OB_Launch() function.
Parameters:
UserType The FLASH User Option Bytes to be modified : a combination of
  • FLASH_OB_USER_Type
UserConfig The FLASH User Option Bytes values: IWDG_SW(Bit4), WWDG_SW(Bit 5), nRST_STOP(Bit 6), nRST_STDY(Bit 7), FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]), ePcROP_EN(Bit 21), SWAP_BANK_OPT(Bit 31) .
Return values:
HAL status

Definition at line 890 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_OB_WaitForLastOperation(), FLASH_TIMEOUT_VALUE, IS_OB_IWDG1_SOURCE, IS_OB_STDBY_D1_RESET, IS_OB_STOP_D1_RESET, IS_OB_USER_IOHSLV, IS_OB_USER_IWDG_STDBY, IS_OB_USER_IWDG_STOP, IS_OB_USER_SECURITY, IS_OB_USER_SWAP_BANK, IS_OB_USER_TYPE, OB_USER_IOHSLV, OB_USER_IWDG1_SW, OB_USER_IWDG_STDBY, OB_USER_IWDG_STOP, OB_USER_NRST_STDBY_D1, OB_USER_NRST_STOP_D1, OB_USER_SECURITY, and OB_USER_SWAP_BANK.

Referenced by HAL_FLASHEx_OBProgram().

HAL_StatusTypeDef HAL_FLASHEx_Erase | ( | FLASH_EraseInitTypeDef * | pEraseInit,
 |  | uint32_t * | SectorError
 | ) |  |

Perform a mass erase or erase the specified FLASH memory sectors.

Parameters:
[in] | pEraseInit | pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
[out] | SectorError | pointer to variable that contains the configuration information on faulty sector in case of error (0xFFFFFFFF means that all the sectors have been correctly erased)
Return values:
HAL Status

Definition at line 158 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_EraseInitTypeDef::Banks, FLASH_BANK_1, FLASH_BANK_2, FLASH_Erase_Sector(), FLASH_MassErase(), FLASH_TIMEOUT_VALUE, FLASH_TYPEERASE_MASSERASE, FLASH_WaitForLastOperation(), IS_FLASH_BANK, IS_FLASH_BANK_EXCLUSIVE, IS_FLASH_NBSECTORS, IS_FLASH_TYPEERASE, IS_VOLTAGERANGE, FLASH_EraseInitTypeDef::NbSectors, FLASH_EraseInitTypeDef::Sector, FLASH_EraseInitTypeDef::TypeErase, and FLASH_EraseInitTypeDef::VoltageRange.

HAL_StatusTypeDef HAL_FLASHEx_Erase_IT ( FLASH_EraseInitTypeDef * pEraseInit )

Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled.

Parameters:
pEraseInit pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
Return values:
HAL Status

Definition at line 258 of file stm32h7xx_hal_flash_ex.c.

References __HAL_FLASH_CLEAR_FLAG_BANK1, __HAL_FLASH_CLEAR_FLAG_BANK2, __HAL_FLASH_ENABLE_IT_BANK1, __HAL_FLASH_ENABLE_IT_BANK2, assert_param, FLASH_EraseInitTypeDef::Banks, FLASH_BANK_1, FLASH_BANK_2, FLASH_Erase_Sector(), FLASH_FLAG_ALL_ERRORS_BANK1, FLASH_FLAG_ALL_ERRORS_BANK2, FLASH_FLAG_EOP_BANK1, FLASH_FLAG_EOP_BANK2, FLASH_IT_EOP_BANK1, FLASH_IT_EOP_BANK2, FLASH_IT_INCERR_BANK1, FLASH_IT_INCERR_BANK2, FLASH_IT_OPERR_BANK1, FLASH_IT_OPERR_BANK2, FLASH_IT_PGSERR_BANK1, FLASH_IT_PGSERR_BANK2, FLASH_IT_STRBERR_BANK1, FLASH_IT_STRBERR_BANK2, FLASH_IT_WRPERR_BANK1, FLASH_IT_WRPERR_BANK2, FLASH_MassErase(), FLASH_PROC_ALLBANK_MASSERASE, FLASH_PROC_MASSERASE_BANK1, FLASH_PROC_MASSERASE_BANK2, FLASH_PROC_SECTERASE_BANK1, FLASH_PROC_SECTERASE_BANK2, FLASH_TYPEERASE_MASSERASE, IS_FLASH_BANK, IS_FLASH_BANK_EXCLUSIVE, IS_FLASH_NBSECTORS, IS_FLASH_TYPEERASE, IS_VOLTAGERANGE, FLASH_EraseInitTypeDef::NbSectors, FLASH_ProcessTypeDef::NbSectorsToErase, FLASH_ProcessTypeDef::ProcedureOnGoing, FLASH_EraseInitTypeDef::Sector, FLASH_ProcessTypeDef::Sector, FLASH_EraseInitTypeDef::TypeErase, FLASH_ProcessTypeDef::VoltageForErase, and FLASH_EraseInitTypeDef::VoltageRange.

HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1 ( void )

Locks the FLASH Bank1 control registers access.

Return values:
HAL Status

Definition at line 524 of file stm32h7xx_hal_flash_ex.c.

HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2 ( void )

Locks the FLASH Bank2 control registers access.

Return values:
HAL Status

Definition at line 555 of file stm32h7xx_hal_flash_ex.c.

void HAL_FLASHEx_OBGetConfig ( FLASH_OBProgramInitTypeDef * pOBInit )

Get the Option byte configuration.

Note:
The parameter Banks of the pOBInit structure must be exclusively FLASH_BANK_1 or FLASH_BANK_2 as this parameter is use to get the given Bank WRP, PCROP and secured area.
Parameters:
pOBInit pointer to an FLASH_OBInitStruct structure that contains the configuration information for the programming.
Return values:
None

Definition at line 470 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_OBProgramInitTypeDef::Banks, FLASH_OBProgramInitTypeDef::BootAddr0, FLASH_OBProgramInitTypeDef::BootAddr1, FLASH_OBProgramInitTypeDef::BORLevel, FLASH_OB_GetBootAdd(), FLASH_OB_GetBOR(), FLASH_OB_GetPCROP(), FLASH_OB_GetRDP(), FLASH_OB_GetSecureArea(), FLASH_OB_GetUser(), FLASH_OB_GetWRP(), IS_FLASH_BANK_EXCLUSIVE, OPTIONBYTE_BOOTADD, OPTIONBYTE_PCROP, OPTIONBYTE_RDP, OPTIONBYTE_WRP, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::PCROPConfig, FLASH_OBProgramInitTypeDef::PCROPEndAddr, FLASH_OBProgramInitTypeDef::PCROPStartAddr, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::SecureAreaConfig, FLASH_OBProgramInitTypeDef::SecureAreaEndAddr, FLASH_OBProgramInitTypeDef::SecureAreaStartAddr, FLASH_OBProgramInitTypeDef::USERConfig, FLASH_OBProgramInitTypeDef::WRPSector, and FLASH_OBProgramInitTypeDef::WRPState.

HAL_StatusTypeDef HAL_FLASHEx_OBProgram ( FLASH_OBProgramInitTypeDef * pOBInit )

Program option bytes.

Parameters:
pOBInit pointer to an FLASH_OBInitStruct structure that contains the configuration information for the programming.
Return values:
HAL Status

Definition at line 342 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_OBProgramInitTypeDef::Banks, FLASH_OBProgramInitTypeDef::BootAddr0, FLASH_OBProgramInitTypeDef::BootAddr1, FLASH_OBProgramInitTypeDef::BootConfig, FLASH_OBProgramInitTypeDef::BORLevel, FLASH_ProcessTypeDef::ErrorCode, FLASH_OB_BootAddConfig(), FLASH_OB_BOR_LevelConfig(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_PCROPConfig(), FLASH_OB_RDPConfig(), FLASH_OB_SecureAreaConfig(), FLASH_OB_UserConfig(), HAL_FLASH_ERROR_NONE, IS_FLASH_BANK, IS_OPTIONBYTE, IS_WRPSTATE, OB_WRPSTATE_ENABLE, OPTIONBYTE_BOOTADD, OPTIONBYTE_BOR, OPTIONBYTE_PCROP, OPTIONBYTE_RDP, OPTIONBYTE_SECURE_AREA, OPTIONBYTE_USER, OPTIONBYTE_WRP, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::PCROPConfig, FLASH_OBProgramInitTypeDef::PCROPEndAddr, FLASH_OBProgramInitTypeDef::PCROPStartAddr, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::SecureAreaConfig, FLASH_OBProgramInitTypeDef::SecureAreaEndAddr, FLASH_OBProgramInitTypeDef::SecureAreaStartAddr, FLASH_OBProgramInitTypeDef::USERConfig, FLASH_OBProgramInitTypeDef::USERType, FLASH_OBProgramInitTypeDef::WRPSector, and FLASH_OBProgramInitTypeDef::WRPState.

HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1 ( void )

Unlock the FLASH Bank1 control registers access.

Return values:
HAL Status

Definition at line 504 of file stm32h7xx_hal_flash_ex.c.

References FLASH_KEY1, and FLASH_KEY2.

HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2 ( void )

Unlock the FLASH Bank2 control registers access.

Return values:
HAL Status

Definition at line 535 of file stm32h7xx_hal_flash_ex.c.

References FLASH_KEY1, and FLASH_KEY2.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Extended FLASH Private functions

Modules | Functions
Extended FLASH Private functions
FLASHEx

Modules

Extended IO operation functions

Extended IO operation functions.

Functions

void FLASH_Erase_Sector (uint32_t Sector, uint32_t Bank, uint32_t VoltageRange)
Erase the specified FLASH memory sector.

Function Documentation

void FLASH_Erase_Sector | ( | uint32_t | Sector,
 |  | uint32_t | Banks,
 |  | uint32_t | VoltageRange
 | ) |  |

Erase the specified FLASH memory sector.

Parameters:
Sector FLASH sector to erase
Banks Banks to be erased This parameter can be one of the following values:
  • FLASH_BANK_1: Bank1 to be erased
  • FLASH_BANK_2: Bank2 to be erased
  • FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
VoltageRange The device program/erase parallelism. This parameter can be one of the following values:
  • FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits
  • FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits
  • FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits
  • FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 62 bits
Return values:
None

Definition at line 623 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, IS_FLASH_BANK_EXCLUSIVE, IS_FLASH_SECTOR, and IS_VOLTAGERANGE.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH_EraseInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_EraseInitTypeDef Struct Reference
FLASH Exported Types

FLASH Erase structure definition. More...

#include <stm32h7xx_hal_flash_ex.h>

Data Fields

uint32_t | TypeErase
uint32_t | Banks
uint32_t | Sector
uint32_t | NbSectors
uint32_t | VoltageRange

Detailed Description

FLASH Erase structure definition.

Definition at line 65 of file stm32h7xx_hal_flash_ex.h.

Field Documentation

uint32_t FLASH_EraseInitTypeDef::Banks

Select banks to erase when Mass erase is enabled. This parameter must be a value of FLASH Banks

Definition at line 70 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::NbSectors

Number of sectors to be erased. This parameter must be a value between 1 and (max number of sectors - value of Initial sector)

Definition at line 76 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::Sector

Initial FLASH sector to erase when Mass erase is disabled This parameter must be a value of FLASH Sectors

Definition at line 73 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::TypeErase

Mass erase or sector Erase. This parameter can be a value of FLASH Type Erase

Definition at line 67 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::VoltageRange

The device voltage range which defines the erase parallelism This parameter must be a value of FLASH Voltage Range

Definition at line 79 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_flash_ex.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASH_OBProgramInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_OBProgramInitTypeDef Struct Reference
FLASH Exported Types

FLASH Option Bytes Program structure definition. More...

#include <stm32h7xx_hal_flash_ex.h>

Data Fields

uint32_t | OptionType
uint32_t | WRPState
uint32_t | WRPSector
uint32_t | RDPLevel
uint32_t | BORLevel
uint32_t | USERType
uint32_t | USERConfig
uint32_t | Banks
uint32_t | PCROPConfig
uint32_t | PCROPStartAddr
uint32_t | PCROPEndAddr
uint32_t | BootConfig
uint32_t | BootAddr0
uint32_t | BootAddr1
uint32_t | SecureAreaConfig
uint32_t | SecureAreaStartAddr
uint32_t | SecureAreaEndAddr

Detailed Description

FLASH Option Bytes Program structure definition.

Definition at line 88 of file stm32h7xx_hal_flash_ex.h.

Field Documentation

uint32_t FLASH_OBProgramInitTypeDef::Banks

Select banks for WRP , PCROP and secure area config . This parameter must be a value of FLASH Banks

Definition at line 110 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::BootAddr0

Boot Address 0. This parameter must be a value between begin and end of a bank

Definition at line 125 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::BootAddr1

Boot Address 1. This parameter must be a value between begin and end of a bank

Definition at line 128 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::BootConfig

Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1 or both. This parameter must be a value of FLASHEx OB BOOT OPTION enumeration

Definition at line 122 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::BORLevel

Set the BOR Level. This parameter can be a value of FLASH BOR Reset Level

Definition at line 102 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::OptionType

Option byte to be configured. This parameter can be a value of FLASH Option Type

Definition at line 90 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROPConfig

specifies if the PCROP area shall be erased or not when RDP level decreased from Level 1 to Level 0 or during a mass erase. This parameter must be a value of FLASHEx OB PCROP RDP enumeration

Definition at line 112 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROPEndAddr

PCROP End address (used for OPTIONBYTE_PCROP). This parameter must be a value between PCROP Start address and end of a bank

Definition at line 119 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROPStartAddr

PCROP Start address (used for OPTIONBYTE_PCROP). This parameter must be a value between begin and end of a bank

Definition at line 116 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::RDPLevel

Set the read protection level. This parameter can be a value of FLASH Option Bytes Read Protection

Definition at line 99 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::SecureAreaConfig

specifies if the bank secured area shall be erased or not when RDP level decreased from Level 1 to Level 0 or during a mass erase. This parameter must be a value of FLASHEx OB SECURE RDP enumeration

Definition at line 131 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::SecureAreaEndAddr

Bank Secure area End address . This parameter must be a value between Start address and end of a bank1

Definition at line 138 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::SecureAreaStartAddr

Bank Secure area Start address. This parameter must be a value between begin and end of bank1

Definition at line 135 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::USERConfig

Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY / IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY.

Definition at line 108 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::USERType

User option byte(s) to be configured (used for OPTIONBYTE_USER). This parameter can be a combination of FLASHEx OB USER Type

Definition at line 105 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPSector

Specifies the sector(s) to be write protected. The value of this parameter depend on device used within the same series

Definition at line 96 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPState

Write protection activation or deactivation. This parameter can be a value of FLASH WRP State

Definition at line 93 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_flash_ex.h
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STM32H753xx HAL User Manual: FLASH Type Erase

Defines
FLASH Type Erase
FLASH Exported Constants

Defines

#define | FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U)
#define | FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U)

Define Documentation

#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U)

Flash Mass erase activation

Definition at line 156 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U)

Sectors erase only

Definition at line 155 of file stm32h7xx_hal_flash_ex.h.

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STM32H753xx HAL User Manual: FLASH Voltage Range

Defines
FLASH Voltage Range
FLASH Exported Constants

Defines

#define | FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U)
#define | FLASH_VOLTAGE_RANGE_2 ((uint32_t)FLASH_CR_PSIZE_0)
#define | FLASH_VOLTAGE_RANGE_3 ((uint32_t)FLASH_CR_PSIZE_1)
#define | FLASH_VOLTAGE_RANGE_4 ((uint32_t)FLASH_CR_PSIZE)

Define Documentation

#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U)

Flash program/erase by 8 bits

Definition at line 164 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)FLASH_CR_PSIZE_0)

Flash program/erase by 16 bits

Definition at line 165 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)FLASH_CR_PSIZE_1)

Flash program/erase by 32 bits

Definition at line 166 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)FLASH_CR_PSIZE)

Flash program/erase by 64 bits

Definition at line 167 of file stm32h7xx_hal_flash_ex.h.

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STM32H753xx HAL User Manual: FLASH WRP State

Defines
FLASH WRP State
FLASH Exported Constants

Defines

#define | OB_WRPSTATE_DISABLE ((uint32_t)0x00U)
#define | OB_WRPSTATE_ENABLE ((uint32_t)0x01U)

Define Documentation

#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U)

Disable the write protection of the desired bank 1 sectors

Definition at line 176 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_GetWRP().

#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U)

Enable the write protection of the desired bank 1 sectors

Definition at line 177 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_GetWRP(), and HAL_FLASHEx_OBProgram().

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STM32H753xx HAL User Manual: FLASH Option Type

Defines
FLASH Option Type
FLASH Exported Constants

Defines

#define | OPTIONBYTE_WRP ((uint32_t)0x01U)
#define | OPTIONBYTE_RDP ((uint32_t)0x02U)
#define | OPTIONBYTE_USER ((uint32_t)0x04U)
#define | OPTIONBYTE_PCROP ((uint32_t)0x08U)
#define | OPTIONBYTE_BOR ((uint32_t)0x10U)
#define | OPTIONBYTE_SECURE_AREA ((uint32_t)0x20U)
#define | OPTIONBYTE_BOOTADD ((uint32_t)0x40U)

Define Documentation

#define OPTIONBYTE_BOOTADD ((uint32_t)0x40U)

BOOT ADD option byte configuration

Definition at line 191 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_BOR ((uint32_t)0x10U)

BOR option byte configuration

Definition at line 189 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_PCROP ((uint32_t)0x08U)

PCROP option byte configuration

Definition at line 188 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_RDP ((uint32_t)0x02U)

RDP option byte configuration

Definition at line 186 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_SECURE_AREA ((uint32_t)0x20U)

secure area option byte configuration

Definition at line 190 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_USER ((uint32_t)0x04U)

USER option byte configuration

Definition at line 187 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_WRP ((uint32_t)0x01U)

WRP option byte configuration

Definition at line 185 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

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STM32H753xx HAL User Manual: FLASH Option Bytes Read Protection

Defines
FLASH Option Bytes Read Protection
FLASH Exported Constants

Defines

#define | OB_RDP_LEVEL_0 ((uint32_t)0xAA00U)
#define | OB_RDP_LEVEL_1 ((uint32_t)0x5500U)
#define | OB_RDP_LEVEL_2 ((uint32_t)0xCC00U)

Define Documentation

#define OB_RDP_LEVEL_0 ((uint32_t)0xAA00U)

Definition at line 199 of file stm32h7xx_hal_flash_ex.h.

#define OB_RDP_LEVEL_1 ((uint32_t)0x5500U)

Definition at line 200 of file stm32h7xx_hal_flash_ex.h.

#define OB_RDP_LEVEL_2 ((uint32_t)0xCC00U)

Warning: When enabling read protection level 2 it s no more possible to go back to level 1 or 0

Definition at line 201 of file stm32h7xx_hal_flash_ex.h.

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STM32H753xx HAL User Manual: FLASH Option Bytes WWatchdog

Defines
FLASH Option Bytes WWatchdog
FLASH Exported Constants

Defines

#define | OB_WWDG_SW ((uint32_t)0x10U)
#define | OB_WWDG_HW ((uint32_t)0x00U)

Define Documentation

#define OB_WWDG_HW ((uint32_t)0x00U)

Hardware WWDG selected

Definition at line 211 of file stm32h7xx_hal_flash_ex.h.

#define OB_WWDG_SW ((uint32_t)0x10U)

Software WWDG selected

Definition at line 210 of file stm32h7xx_hal_flash_ex.h.

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STM32H753xx HAL User Manual: FLASH Option Bytes IWatchdog

Defines
FLASH Option Bytes IWatchdog
FLASH Exported Constants

Defines

#define | OB_IWDG_SW ((uint32_t)0x20U)
#define | OB_IWDG_HW ((uint32_t)0x00U)

Define Documentation

#define OB_IWDG_HW ((uint32_t)0x00U)

Hardware IWDG selected

Definition at line 221 of file stm32h7xx_hal_flash_ex.h.

#define OB_IWDG_SW ((uint32_t)0x20U)

Software IWDG selected

Definition at line 220 of file stm32h7xx_hal_flash_ex.h.

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STM32H753xx HAL User Manual: FLASH Option Bytes nRST_STOP

Defines
FLASH Option Bytes nRST_STOP
FLASH Exported Constants

Defines

#define | OB_STOP_NO_RST ((uint32_t)0x40U)
#define | OB_STOP_RST ((uint32_t)0x00U)

Define Documentation

#define OB_STOP_NO_RST ((uint32_t)0x40U)

No reset generated when entering in STOP

Definition at line 229 of file stm32h7xx_hal_flash_ex.h.

#define OB_STOP_RST ((uint32_t)0x00U)

Reset generated when entering in STOP

Definition at line 230 of file stm32h7xx_hal_flash_ex.h.

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STM32H753xx HAL User Manual: FLASH Option Bytes nRST_STDBY

Defines
FLASH Option Bytes nRST_STDBY
FLASH Exported Constants

Defines

#define | OB_STDBY_NO_RST ((uint32_t)0x80U)
#define | OB_STDBY_RST ((uint32_t)0x00U)

Define Documentation

#define OB_STDBY_NO_RST ((uint32_t)0x80U)

No reset generated when entering in STANDBY

Definition at line 238 of file stm32h7xx_hal_flash_ex.h.

#define OB_STDBY_RST ((uint32_t)0x00U)

Reset generated when entering in STANDBY

Definition at line 239 of file stm32h7xx_hal_flash_ex.h.

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STM32H753xx HAL User Manual: FLASH IWDG Counter Freeze in STOP

Defines
FLASH IWDG Counter Freeze in STOP
FLASH Exported Constants

Defines

#define | OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000U)
#define | OB_IWDG_STOP_ACTIVE ((uint32_t)FLASH_OPTSR_FZ_IWDG_STOP)

Define Documentation

#define OB_IWDG_STOP_ACTIVE ((uint32_t)FLASH_OPTSR_FZ_IWDG_STOP)

IWDG counter active in STOP mode

Definition at line 248 of file stm32h7xx_hal_flash_ex.h.

#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000U)

Freeze IWDG counter in STOP mode

Definition at line 247 of file stm32h7xx_hal_flash_ex.h.

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STM32H753xx HAL User Manual: FLASH IWDG Counter Freeze in STANDBY

Defines
FLASH IWDG Counter Freeze in STANDBY
FLASH Exported Constants

Defines

#define | OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000U)
#define | OB_IWDG_STDBY_ACTIVE ((uint32_t)FLASH_OPTSR_FZ_IWDG_SDBY)

Define Documentation

#define OB_IWDG_STDBY_ACTIVE ((uint32_t)FLASH_OPTSR_FZ_IWDG_SDBY)

IWDG counter active in STANDBY mode

Definition at line 257 of file stm32h7xx_hal_flash_ex.h.

#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000U)

Freeze IWDG counter in STANDBY mode

Definition at line 256 of file stm32h7xx_hal_flash_ex.h.

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STM32H753xx HAL User Manual: FLASH BOR Reset Level

Defines
FLASH BOR Reset Level
FLASH Exported Constants

Defines

#define | OB_BOR_LEVEL3 ((uint32_t)0x00U)
#define | OB_BOR_LEVEL2 ((uint32_t)0x04U)
#define | OB_BOR_LEVEL1 ((uint32_t)0x08U)
#define | OB_BOR_OFF ((uint32_t)0x0CU)

Define Documentation

#define OB_BOR_LEVEL1 ((uint32_t)0x08U)

Supply voltage ranges from 2.10 to 2.40 V

Definition at line 267 of file stm32h7xx_hal_flash_ex.h.

#define OB_BOR_LEVEL2 ((uint32_t)0x04U)

Supply voltage ranges from 2.40 to 2.70 V

Definition at line 266 of file stm32h7xx_hal_flash_ex.h.

#define OB_BOR_LEVEL3 ((uint32_t)0x00U)

Supply voltage ranges from 2.70 to 3.60 V

Definition at line 265 of file stm32h7xx_hal_flash_ex.h.

#define OB_BOR_OFF ((uint32_t)0x0CU)

Supply voltage ranges from 1.62 to 2.10 V

Definition at line 268 of file stm32h7xx_hal_flash_ex.h.

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STM32H753xx HAL User Manual: FLASH Boot Address

Defines
FLASH Boot Address
FLASH Exported Constants

Defines

#define | OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000U)
#define | OB_BOOTADDR_SYSTEM ((uint32_t)0x0040U)
#define | OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080U)
#define | OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U)
#define | OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U)
#define | OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U)
#define | OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U)

Define Documentation

#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U)

Boot from Flash on AXIM interface (0x08000000)

Definition at line 281 of file stm32h7xx_hal_flash_ex.h.

#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U)

Boot from DTCM RAM (0x20000000)

Definition at line 282 of file stm32h7xx_hal_flash_ex.h.

#define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080U)

Boot from Flash on ITCM interface (0x00200000)

Definition at line 280 of file stm32h7xx_hal_flash_ex.h.

#define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000U)

Boot from ITCM RAM (0x00000000)

Definition at line 278 of file stm32h7xx_hal_flash_ex.h.

#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U)

Boot from SRAM1 (0x20010000)

Definition at line 283 of file stm32h7xx_hal_flash_ex.h.

#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U)

Boot from SRAM2 (0x2004C000)

Definition at line 284 of file stm32h7xx_hal_flash_ex.h.

#define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040U)

Boot from System memory bootloader (0x00100000)

Definition at line 279 of file stm32h7xx_hal_flash_ex.h.

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STM32H753xx HAL User Manual: FLASH Latency

Defines
FLASH Latency
FLASH Exported Constants

Defines

#define | FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
#define | FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
#define | FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
#define | FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
#define | FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS

Define Documentation

#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS

FLASH Zero Latency cycle

Definition at line 292 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS

FLASH One Latency cycle

Definition at line 293 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS

FLASH Two Latency cycles

Definition at line 294 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS

FLASH Three Latency cycles

Definition at line 295 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS

FLASH Four Latency cycles

Definition at line 296 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS

FLASH Five Latency cycles

Definition at line 297 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS

FLASH Six Latency cycles

Definition at line 298 of file stm32h7xx_hal_flash_ex.h.

#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS

FLASH Seven Latency cycles

Definition at line 299 of file stm32h7xx_hal_flash_ex.h.

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STM32H753xx HAL User Manual: FLASH Banks

Defines
FLASH Banks
FLASH Exported Constants

Defines

#define | FLASH_BANK_1 ((uint32_t)0x01U)
#define | FLASH_BANK_2 ((uint32_t)0x02U)
#define | FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2))

Define Documentation

#define FLASH_BANK_1 ((uint32_t)0x01U)

Bank 1

Definition at line 308 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_Erase_Sector(), FLASH_MassErase(), FLASH_OB_BootAddConfig(), FLASH_OB_BOR_LevelConfig(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_GetPCROP(), FLASH_OB_GetSecureArea(), FLASH_OB_GetWRP(), FLASH_OB_PCROPConfig(), FLASH_OB_RDPConfig(), FLASH_OB_SecureAreaConfig(), FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), HAL_FLASH_IRQHandler(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define FLASH_BANK_2 ((uint32_t)0x02U)

Bank 2

Definition at line 309 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_Erase_Sector(), FLASH_MassErase(), FLASH_OB_BootAddConfig(), FLASH_OB_BOR_LevelConfig(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_GetPCROP(), FLASH_OB_GetSecureArea(), FLASH_OB_GetWRP(), FLASH_OB_PCROPConfig(), FLASH_OB_RDPConfig(), FLASH_OB_SecureAreaConfig(), FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), HAL_FLASH_IRQHandler(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2))

Bank1 and Bank2

Definition at line 310 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_GetPCROP(), FLASH_OB_GetSecureArea(), and FLASH_OB_GetWRP().

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STM32H753xx HAL User Manual: FLASHEx OB PCROP RDP

Defines
FLASHEx OB PCROP RDP
FLASH Exported Constants

Defines

#define | OB_PCROP_RDP_NOT_ERASE ((uint32_t)0x00000000U)
#define | OB_PCROP_RDP_ERASE ((uint32_t)FLASH_PRAR_DMEP)

Define Documentation

#define OB_PCROP_RDP_ERASE ((uint32_t)FLASH_PRAR_DMEP)

PCROP area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase)

Definition at line 321 of file stm32h7xx_hal_flash_ex.h.

#define OB_PCROP_RDP_NOT_ERASE ((uint32_t)0x00000000U)

PCROP area is not erased when the RDP level is decreased from Level 1 to Level 0 or during a mass erase

Definition at line 319 of file stm32h7xx_hal_flash_ex.h.

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STM32H753xx HAL User Manual: FLASH Option Bytes Write Protection

Defines
FLASH Option Bytes Write Protection
FLASH Exported Constants

Defines

#define | OB_WRP_SECTOR_0 ((uint32_t)0x00000001U)
#define | OB_WRP_SECTOR_1 ((uint32_t)0x00000002U)
#define | OB_WRP_SECTOR_2 ((uint32_t)0x00000004U)
#define | OB_WRP_SECTOR_3 ((uint32_t)0x00000008U)
#define | OB_WRP_SECTOR_4 ((uint32_t)0x00000010U)
#define | OB_WRP_SECTOR_5 ((uint32_t)0x00000020U)
#define | OB_WRP_SECTOR_6 ((uint32_t)0x00000040U)
#define | OB_WRP_SECTOR_7 ((uint32_t)0x00000080U)
#define | OB_WRP_SECTOR_All ((uint32_t)0x000000FFU)

Define Documentation

#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001U)

Write protection of Sector0

Definition at line 333 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002U)

Write protection of Sector1

Definition at line 334 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004U)

Write protection of Sector2

Definition at line 335 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_3 ((uint32_t)0x00000008U)

Write protection of Sector3

Definition at line 336 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_4 ((uint32_t)0x00000010U)

Write protection of Sector4

Definition at line 337 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_5 ((uint32_t)0x00000020U)

Write protection of Sector5

Definition at line 338 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_6 ((uint32_t)0x00000040U)

Write protection of Sector6

Definition at line 339 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_7 ((uint32_t)0x00000080U)

Write protection of Sector7

Definition at line 340 of file stm32h7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_All ((uint32_t)0x000000FFU)

Write protection of all Sectors

Definition at line 341 of file stm32h7xx_hal_flash_ex.h.

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STM32H753xx HAL User Manual: FLASHEx OB SECURITY

Defines
FLASHEx OB SECURITY
FLASH Exported Constants

Defines

#define | OB_SECURITY_DISABLE ((uint32_t)0x00000U)
#define | OB_SECURITY_ENABLE ((uint32_t)FLASH_OPTSR_SECURITY)

Define Documentation

#define OB_SECURITY_DISABLE ((uint32_t)0x00000U)

security enabled

Definition at line 350 of file stm32h7xx_hal_flash_ex.h.

#define OB_SECURITY_ENABLE ((uint32_t)FLASH_OPTSR_SECURITY)

security disabled

Definition at line 351 of file stm32h7xx_hal_flash_ex.h.

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STM32H753xx HAL User Manual: FLASHEx OB IWDG1 SW

Defines
FLASHEx OB IWDG1 SW
FLASHEx

Defines

#define | OB_IWDG1_HW ((uint32_t)FLASH_OPTSR_IWDG1_SW)
#define | OB_IWDG1_SW ((uint32_t)0x00000U)

Define Documentation

#define OB_IWDG1_HW ((uint32_t)FLASH_OPTSR_IWDG1_SW)

Hardware independent watchdog 1

Definition at line 364 of file stm32h7xx_hal_flash_ex.h.

#define OB_IWDG1_SW ((uint32_t)0x00000U)

Software independent watchdog 1

Definition at line 365 of file stm32h7xx_hal_flash_ex.h.

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STM32H753xx HAL User Manual: FLASHEx OB NRST STOP D1

Defines
FLASHEx OB NRST STOP D1
FLASHEx

Defines

#define | OB_STOP_RST_D1 ((uint32_t)0x0000U)
#define | OB_STOP_NO_RST_D1 ((uint32_t)FLASH_OPTSR_NRST_STOP_D1)

Define Documentation

#define OB_STOP_NO_RST_D1 ((uint32_t)FLASH_OPTSR_NRST_STOP_D1)

No reset generated when entering the D1 to stop mode

Definition at line 373 of file stm32h7xx_hal_flash_ex.h.

#define OB_STOP_RST_D1 ((uint32_t)0x0000U)

Reset generated when entering the D1 to stop mode

Definition at line 372 of file stm32h7xx_hal_flash_ex.h.

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STM32H753xx HAL User Manual: FLASHEx OB NRST STDBY D1

Defines
FLASHEx OB NRST STDBY D1
FLASHEx

Defines

#define | OB_STDBY_RST_D1 ((uint32_t)0x0000U)
#define | OB_STDBY_NO_RST_D1 ((uint32_t)FLASH_OPTSR_NRST_STBY_D1)

Define Documentation

#define OB_STDBY_NO_RST_D1 ((uint32_t)FLASH_OPTSR_NRST_STBY_D1)

No reset generated when entering the D1 to standby mode

Definition at line 383 of file stm32h7xx_hal_flash_ex.h.

#define OB_STDBY_RST_D1 ((uint32_t)0x0000U)

Reset generated when entering the D1 to standby mode

Definition at line 382 of file stm32h7xx_hal_flash_ex.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASHEx OB SWAP BANK

Defines
FLASHEx OB SWAP BANK
FLASHEx

Defines

#define | OB_SWAP_BANK_DISABLE ((uint32_t)0x00000U)
#define | OB_SWAP_BANK_ENABLE ((uint32_t)FLASH_OPTSR_SWAP_BANK_OPT)

Define Documentation

#define OB_SWAP_BANK_DISABLE ((uint32_t)0x00000U)

Bank swap disabled

Definition at line 392 of file stm32h7xx_hal_flash_ex.h.

#define OB_SWAP_BANK_ENABLE ((uint32_t)FLASH_OPTSR_SWAP_BANK_OPT)

Bank swap enabled

Definition at line 393 of file stm32h7xx_hal_flash_ex.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASHEx OB IOHSLV

Defines
FLASHEx OB IOHSLV
FLASHEx

Defines

#define | OB_IOHSLV_DISABLE ((uint32_t)0x00000000U)
#define | OB_IOHSLV_ENABLE ((uint32_t)FLASH_OPTSR_IO_HSLV)

Define Documentation

#define OB_IOHSLV_DISABLE ((uint32_t)0x00000000U)

IOHSLV disabled

Definition at line 402 of file stm32h7xx_hal_flash_ex.h.

#define OB_IOHSLV_ENABLE ((uint32_t)FLASH_OPTSR_IO_HSLV)

IOHSLV enabled

Definition at line 403 of file stm32h7xx_hal_flash_ex.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASHEx OB BOOT OPTION

Defines
FLASHEx OB BOOT OPTION
FLASHEx

Defines

#define | OB_BOOT_ADD0 ((uint32_t)0x01U)
#define | OB_BOOT_ADD1 ((uint32_t)0x02U)
#define | OB_BOOT_ADD_BOTH ((uint32_t)0x03U)

Define Documentation

#define OB_BOOT_ADD0 ((uint32_t)0x01U)

Select Boot Address 0

Definition at line 413 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_BootAddConfig().

#define OB_BOOT_ADD1 ((uint32_t)0x02U)

Select Boot Address 1

Definition at line 414 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_BootAddConfig().

#define OB_BOOT_ADD_BOTH ((uint32_t)0x03U)

Select Boot Address 0 and 1

Definition at line 415 of file stm32h7xx_hal_flash_ex.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASHEx OB USER Type

Defines
FLASHEx OB USER Type
FLASHEx

Defines

#define | OB_USER_NRST_STOP_D1 ((uint32_t)0x0001U)
#define | OB_USER_NRST_STDBY_D1 ((uint32_t)0x0002U)
#define | OB_USER_IWDG_STOP ((uint32_t)0x0004U)
#define | OB_USER_IWDG_STDBY ((uint32_t)0x0008U)
#define | OB_USER_ST_RAM_SIZE ((uint32_t)0x0010U)
#define | OB_USER_SECURITY ((uint32_t)0x0020U)
#define | OB_USER_SWAP_BANK ((uint32_t)0x0100U)
#define | OB_USER_IOHSLV ((uint32_t)0x0200U)
#define | OB_USER_IWDG1_SW ((uint32_t)0x0400U)

Define Documentation

#define OB_USER_IOHSLV ((uint32_t)0x0200U)

IO HSLV selection

Definition at line 432 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_IWDG1_SW ((uint32_t)0x0400U)

Independent watchdog selection

Definition at line 433 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_IWDG_STDBY ((uint32_t)0x0008U)

Independent watchdog counter freeze in standby mode

Definition at line 428 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_IWDG_STOP ((uint32_t)0x0004U)

Independent watchdog counter freeze in stop mode

Definition at line 427 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_NRST_STDBY_D1 ((uint32_t)0x0002U)

Reset when entering standby mode selection

Definition at line 426 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_NRST_STOP_D1 ((uint32_t)0x0001U)

Reset when entering Stop mode selection

Definition at line 425 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_SECURITY ((uint32_t)0x0020U)

security selection

Definition at line 430 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_ST_RAM_SIZE ((uint32_t)0x0010U)

dedicated DTCM Ram size selection

Definition at line 429 of file stm32h7xx_hal_flash_ex.h.

#define OB_USER_SWAP_BANK ((uint32_t)0x0100U)

Bank swap selection

Definition at line 431 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASHEx OB SECURE RDP

Defines
FLASHEx OB SECURE RDP
FLASHEx

Defines

#define | OB_SECURE_RDP_NOT_ERASE ((uint32_t)0x00000000U)
#define | OB_SECURE_RDP_ERASE ((uint32_t)FLASH_SCAR_DMES)

Define Documentation

#define OB_SECURE_RDP_ERASE ((uint32_t)FLASH_SCAR_DMES)

Secure area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase)

Definition at line 444 of file stm32h7xx_hal_flash_ex.h.

#define OB_SECURE_RDP_NOT_ERASE ((uint32_t)0x00000000U)

Secure area is not erased when the RDP level is decreased from Level 1 to Level 0 or during a mass erase

Definition at line 442 of file stm32h7xx_hal_flash_ex.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASHEx Private macros to check input parameters

Defines
FLASHEx Private macros to check input parameters
FLASHEx Private Macros

Defines

#define | IS_FLASH_TYPEERASE(VALUE)
#define | IS_VOLTAGERANGE(RANGE)
#define | IS_WRPSTATE(VALUE)
#define | IS_OPTIONBYTE(VALUE)
#define | IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U)
#define | IS_OB_RDP_LEVEL(LEVEL)
#define | IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
#define | IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define | IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
#define | IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
#define | IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
#define | IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
#define | IS_OB_BOR_LEVEL(LEVEL)
#define | IS_FLASH_LATENCY(LATENCY)
#define | IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
#define | IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
#define | IS_FLASH_SECTOR(SECTOR)
#define | IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xFFFFFF00) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#define | IS_FLASH_BANK(BANK)
#define | IS_OB_PCROP_RDP(CONFIG)
#define | IS_OB_SECURE_RDP(CONFIG)
#define | IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))
#define | IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
#define | IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
#define | IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
#define | IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
#define | IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))
#define | IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))
#define | IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE)) /*User can only move the security bit from 0 to 1*/
#define | IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x400U) && ((TYPE) != 0))
#define | IS_OB_BOOT_ADD_OPTION(VALUE)

Define Documentation

#define IS_FLASH_ADDRESS ( ADDRESS ) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))

Definition at line 550 of file stm32h7xx_hal_flash_ex.h.

#define IS_FLASH_BANK ( BANK )
Value:
(((BANK) == FLASH_BANK_1)  || \
                                    ((BANK) == FLASH_BANK_2)  || \
                                    ((BANK) == FLASH_BANK_BOTH))

Definition at line 561 of file stm32h7xx_hal_flash_ex.h.

#define IS_FLASH_LATENCY ( LATENCY )
Value:
(((LATENCY) == FLASH_LATENCY_0)  || \
                                   ((LATENCY) == FLASH_LATENCY_1)  || \
                                   ((LATENCY) == FLASH_LATENCY_2)  || \
                                   ((LATENCY) == FLASH_LATENCY_3)  || \
                                   ((LATENCY) == FLASH_LATENCY_4)  || \
                                   ((LATENCY) == FLASH_LATENCY_5)  || \
                                   ((LATENCY) == FLASH_LATENCY_6)  || \
                                   ((LATENCY) == FLASH_LATENCY_7))

Definition at line 541 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_FLASH_NBSECTORS ( NBSECTORS ) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))

Definition at line 552 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define IS_FLASH_SECTOR ( SECTOR )
Value:
(((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7))

Definition at line 554 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_Erase_Sector().

#define IS_FLASH_TYPEERASE ( VALUE )
Value:
(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
                                      ((VALUE) == FLASH_TYPEERASE_MASSERASE))

Definition at line 504 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define IS_OB_BOOT_ADD_OPTION ( VALUE )
Value:
(((VALUE) == OB_BOOT_ADD0) || \
                                           ((VALUE) == OB_BOOT_ADD1)  || \
                                           ((VALUE) == OB_BOOT_ADD_BOTH))

Definition at line 587 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_BootAddConfig().

#define IS_OB_BOOT_ADDRESS ( ADDRESS ) ((ADDRESS) <= 0x8013U)

Definition at line 519 of file stm32h7xx_hal_flash_ex.h.

#define IS_OB_BOR_LEVEL ( LEVEL )
Value:
(((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
                                ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))

Definition at line 538 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_BOR_LevelConfig().

#define IS_OB_IWDG1_SOURCE ( SOURCE ) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))

Definition at line 575 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_IWDG_SOURCE ( SOURCE ) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))

Definition at line 528 of file stm32h7xx_hal_flash_ex.h.

#define IS_OB_IWDG_STDBY_FREEZE ( FREEZE ) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))

Definition at line 536 of file stm32h7xx_hal_flash_ex.h.

#define IS_OB_IWDG_STOP_FREEZE ( FREEZE ) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))

Definition at line 534 of file stm32h7xx_hal_flash_ex.h.

#define IS_OB_PCROP_RDP ( CONFIG )
Value:
(((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
                                             ((CONFIG) == OB_PCROP_RDP_ERASE))

Definition at line 565 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_PCROPConfig().

#define IS_OB_RDP_LEVEL ( LEVEL )
Value:
(((LEVEL) == OB_RDP_LEVEL_0)   ||\
                                            ((LEVEL) == OB_RDP_LEVEL_1) ||\
                                            ((LEVEL) == OB_RDP_LEVEL_2))

Definition at line 522 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_RDPConfig().

#define IS_OB_SECURE_RDP ( CONFIG )
Value:
(((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \
                                             ((CONFIG) == OB_SECURE_RDP_ERASE))

Definition at line 568 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_SecureAreaConfig().

#define IS_OB_STDBY_D1_RESET ( VALUE ) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))

Definition at line 578 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_STDBY_SOURCE ( SOURCE ) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))

Definition at line 532 of file stm32h7xx_hal_flash_ex.h.

#define IS_OB_STOP_D1_RESET ( VALUE ) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))

Definition at line 576 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_STOP_SOURCE ( SOURCE ) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))

Definition at line 530 of file stm32h7xx_hal_flash_ex.h.

#define IS_OB_USER_IOHSLV ( VALUE ) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))

Definition at line 573 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_IWDG_STDBY ( VALUE ) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))

Definition at line 582 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_IWDG_STOP ( VALUE ) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))

Definition at line 580 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_SECURITY ( VALUE ) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE)) /*User can only move the security bit from 0 to 1*/

Definition at line 584 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_SWAP_BANK ( VALUE ) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))

Definition at line 571 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_TYPE ( TYPE ) (((TYPE) <= (uint32_t)0x400U) && ((TYPE) != 0))

Definition at line 585 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_WRP_SECTOR ( SECTOR ) ((((SECTOR) & (uint32_t)0xFFFFFF00) == 0x00000000U) && ((SECTOR) != 0x00000000U))

Definition at line 559 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_OB_DisableWRP(), and FLASH_OB_EnableWRP().

#define IS_OB_WWDG_SOURCE ( SOURCE ) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))

Definition at line 526 of file stm32h7xx_hal_flash_ex.h.

#define IS_OPTIONBYTE ( VALUE )
Value:
((VALUE) <= (OB_USER_IWDG1_SW | OB_USER_NRST_STDBY_D1 | OB_USER_NRST_STOP_D1  |\
                                             OB_USER_IWDG_STOP| OB_USER_IWDG_STDBY    | OB_USER_SWAP_BANK     |\
                                             OB_USER_ST_RAM_SIZE   | OB_USER_SECURITY))

Definition at line 514 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

#define IS_VOLTAGERANGE ( RANGE )
Value:
(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
                                   ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
                                   ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
                                   ((RANGE) == FLASH_VOLTAGE_RANGE_4))

Definition at line 507 of file stm32h7xx_hal_flash_ex.h.

Referenced by FLASH_Erase_Sector(), FLASH_MassErase(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define IS_WRPSTATE ( VALUE )
Value:
(((VALUE) == OB_WRPSTATE_DISABLE) || \
                               ((VALUE) == OB_WRPSTATE_ENABLE))

Definition at line 512 of file stm32h7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASHEx_Private_Constants

Defines
FLASHEx_Private_Constants
FLASHEx

Defines

#define FLASH_TIMEOUT_VALUE 50000U/* 50 s */

Define Documentation

#define FLASH_TIMEOUT_VALUE 50000U/* 50 s */

Definition at line 99 of file stm32h7xx_hal_flash_ex.c.

Referenced by FLASH_OB_BootAddConfig(), FLASH_OB_BOR_LevelConfig(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_PCROPConfig(), FLASH_OB_RDPConfig(), FLASH_OB_SecureAreaConfig(), FLASH_OB_UserConfig(), and HAL_FLASHEx_Erase().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASHEx_Exported_Functions_Group1

Functions
FLASHEx_Exported_Functions_Group1
FLASHEx_Exported_Functions

Functions

HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
Perform a mass erase or erase the specified FLASH memory sectors.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option byte configuration.
HAL_StatusTypeDef | HAL_FLASHEx_Unlock_Bank1 (void)
Unlock the FLASH Bank1 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_Lock_Bank1 (void)
Locks the FLASH Bank1 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_Unlock_Bank2 (void)
Unlock the FLASH Bank2 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_Lock_Bank2 (void)
Locks the FLASH Bank2 control registers access.

Function Documentation

HAL_StatusTypeDef HAL_FLASHEx_Erase | ( | FLASH_EraseInitTypeDef * | pEraseInit,
 |  | uint32_t * | SectorError
 | ) |  |

Perform a mass erase or erase the specified FLASH memory sectors.

Parameters:
[in] | pEraseInit | pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
[out] | SectorError | pointer to variable that contains the configuration information on faulty sector in case of error (0xFFFFFFFF means that all the sectors have been correctly erased)
Return values:
HAL Status

Definition at line 158 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_EraseInitTypeDef::Banks, FLASH_BANK_1, FLASH_BANK_2, FLASH_Erase_Sector(), FLASH_MassErase(), FLASH_TIMEOUT_VALUE, FLASH_TYPEERASE_MASSERASE, FLASH_WaitForLastOperation(), IS_FLASH_BANK, IS_FLASH_BANK_EXCLUSIVE, IS_FLASH_NBSECTORS, IS_FLASH_TYPEERASE, IS_VOLTAGERANGE, FLASH_EraseInitTypeDef::NbSectors, FLASH_EraseInitTypeDef::Sector, FLASH_EraseInitTypeDef::TypeErase, and FLASH_EraseInitTypeDef::VoltageRange.

HAL_StatusTypeDef HAL_FLASHEx_Erase_IT ( FLASH_EraseInitTypeDef * pEraseInit )

Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled.

Parameters:
pEraseInit pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
Return values:
HAL Status

Definition at line 258 of file stm32h7xx_hal_flash_ex.c.

References __HAL_FLASH_CLEAR_FLAG_BANK1, __HAL_FLASH_CLEAR_FLAG_BANK2, __HAL_FLASH_ENABLE_IT_BANK1, __HAL_FLASH_ENABLE_IT_BANK2, assert_param, FLASH_EraseInitTypeDef::Banks, FLASH_BANK_1, FLASH_BANK_2, FLASH_Erase_Sector(), FLASH_FLAG_ALL_ERRORS_BANK1, FLASH_FLAG_ALL_ERRORS_BANK2, FLASH_FLAG_EOP_BANK1, FLASH_FLAG_EOP_BANK2, FLASH_IT_EOP_BANK1, FLASH_IT_EOP_BANK2, FLASH_IT_INCERR_BANK1, FLASH_IT_INCERR_BANK2, FLASH_IT_OPERR_BANK1, FLASH_IT_OPERR_BANK2, FLASH_IT_PGSERR_BANK1, FLASH_IT_PGSERR_BANK2, FLASH_IT_STRBERR_BANK1, FLASH_IT_STRBERR_BANK2, FLASH_IT_WRPERR_BANK1, FLASH_IT_WRPERR_BANK2, FLASH_MassErase(), FLASH_PROC_ALLBANK_MASSERASE, FLASH_PROC_MASSERASE_BANK1, FLASH_PROC_MASSERASE_BANK2, FLASH_PROC_SECTERASE_BANK1, FLASH_PROC_SECTERASE_BANK2, FLASH_TYPEERASE_MASSERASE, IS_FLASH_BANK, IS_FLASH_BANK_EXCLUSIVE, IS_FLASH_NBSECTORS, IS_FLASH_TYPEERASE, IS_VOLTAGERANGE, FLASH_EraseInitTypeDef::NbSectors, FLASH_ProcessTypeDef::NbSectorsToErase, FLASH_ProcessTypeDef::ProcedureOnGoing, FLASH_EraseInitTypeDef::Sector, FLASH_ProcessTypeDef::Sector, FLASH_EraseInitTypeDef::TypeErase, FLASH_ProcessTypeDef::VoltageForErase, and FLASH_EraseInitTypeDef::VoltageRange.

HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1 ( void )

Locks the FLASH Bank1 control registers access.

Return values:
HAL Status

Definition at line 524 of file stm32h7xx_hal_flash_ex.c.

HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2 ( void )

Locks the FLASH Bank2 control registers access.

Return values:
HAL Status

Definition at line 555 of file stm32h7xx_hal_flash_ex.c.

void HAL_FLASHEx_OBGetConfig ( FLASH_OBProgramInitTypeDef * pOBInit )

Get the Option byte configuration.

Note:
The parameter Banks of the pOBInit structure must be exclusively FLASH_BANK_1 or FLASH_BANK_2 as this parameter is use to get the given Bank WRP, PCROP and secured area.
Parameters:
pOBInit pointer to an FLASH_OBInitStruct structure that contains the configuration information for the programming.
Return values:
None

Definition at line 470 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_OBProgramInitTypeDef::Banks, FLASH_OBProgramInitTypeDef::BootAddr0, FLASH_OBProgramInitTypeDef::BootAddr1, FLASH_OBProgramInitTypeDef::BORLevel, FLASH_OB_GetBootAdd(), FLASH_OB_GetBOR(), FLASH_OB_GetPCROP(), FLASH_OB_GetRDP(), FLASH_OB_GetSecureArea(), FLASH_OB_GetUser(), FLASH_OB_GetWRP(), IS_FLASH_BANK_EXCLUSIVE, OPTIONBYTE_BOOTADD, OPTIONBYTE_PCROP, OPTIONBYTE_RDP, OPTIONBYTE_WRP, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::PCROPConfig, FLASH_OBProgramInitTypeDef::PCROPEndAddr, FLASH_OBProgramInitTypeDef::PCROPStartAddr, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::SecureAreaConfig, FLASH_OBProgramInitTypeDef::SecureAreaEndAddr, FLASH_OBProgramInitTypeDef::SecureAreaStartAddr, FLASH_OBProgramInitTypeDef::USERConfig, FLASH_OBProgramInitTypeDef::WRPSector, and FLASH_OBProgramInitTypeDef::WRPState.

HAL_StatusTypeDef HAL_FLASHEx_OBProgram ( FLASH_OBProgramInitTypeDef * pOBInit )

Program option bytes.

Parameters:
pOBInit pointer to an FLASH_OBInitStruct structure that contains the configuration information for the programming.
Return values:
HAL Status

Definition at line 342 of file stm32h7xx_hal_flash_ex.c.

References assert_param, FLASH_OBProgramInitTypeDef::Banks, FLASH_OBProgramInitTypeDef::BootAddr0, FLASH_OBProgramInitTypeDef::BootAddr1, FLASH_OBProgramInitTypeDef::BootConfig, FLASH_OBProgramInitTypeDef::BORLevel, FLASH_ProcessTypeDef::ErrorCode, FLASH_OB_BootAddConfig(), FLASH_OB_BOR_LevelConfig(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_PCROPConfig(), FLASH_OB_RDPConfig(), FLASH_OB_SecureAreaConfig(), FLASH_OB_UserConfig(), HAL_FLASH_ERROR_NONE, IS_FLASH_BANK, IS_OPTIONBYTE, IS_WRPSTATE, OB_WRPSTATE_ENABLE, OPTIONBYTE_BOOTADD, OPTIONBYTE_BOR, OPTIONBYTE_PCROP, OPTIONBYTE_RDP, OPTIONBYTE_SECURE_AREA, OPTIONBYTE_USER, OPTIONBYTE_WRP, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::PCROPConfig, FLASH_OBProgramInitTypeDef::PCROPEndAddr, FLASH_OBProgramInitTypeDef::PCROPStartAddr, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::SecureAreaConfig, FLASH_OBProgramInitTypeDef::SecureAreaEndAddr, FLASH_OBProgramInitTypeDef::SecureAreaStartAddr, FLASH_OBProgramInitTypeDef::USERConfig, FLASH_OBProgramInitTypeDef::USERType, FLASH_OBProgramInitTypeDef::WRPSector, and FLASH_OBProgramInitTypeDef::WRPState.

HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1 ( void )

Unlock the FLASH Bank1 control registers access.

Return values:
HAL Status

Definition at line 504 of file stm32h7xx_hal_flash_ex.c.

References FLASH_KEY1, and FLASH_KEY2.

HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2 ( void )

Unlock the FLASH Bank2 control registers access.

Return values:
HAL Status

Definition at line 535 of file stm32h7xx_hal_flash_ex.c.

References FLASH_KEY1, and FLASH_KEY2.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: FLASHEx

Modules | Variables
FLASHEx
STM32H7xx_HAL_Driver

FLASH HAL Extension module driver. More...

Modules

Extended FLASH Private functions
FLASH Exported Types
FLASH Exported Constants
FLASHEx OB IWDG1 SW
FLASHEx OB NRST STOP D1
FLASHEx OB NRST STDBY D1
FLASHEx OB SWAP BANK
FLASHEx OB IOHSLV
FLASHEx OB BOOT OPTION
FLASHEx OB USER Type
FLASHEx OB SECURE RDP
FLASH Exported Macros
FLASHEx Private Macros
FLASHEx_Private_Constants
FLASHEx_Exported_Functions

Variables

FLASH_ProcessTypeDef pFlash

Detailed Description

FLASH HAL Extension module driver.

Variable Documentation

FLASH_ProcessTypeDef pFlash

Definition at line 132 of file stm32h7xx_hal_flash.c.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
GPIO Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initializes the GPIOx peripheral registers to their default reset values.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
  [..]
    This section provides functions allowing to initialize and de-initialize the GPIOs
    to be ready for use.

Function Documentation

void HAL_GPIO_DeInit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | GPIO_Pin
 | ) |  |

De-initializes the GPIOx peripheral registers to their default reset values.

Parameters:
GPIOx,: where x can be (A..K) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to be written. This parameter can be one of GPIO_PIN_x where x can be (0..15).
Return values:
None

Definition at line 316 of file stm32h7xx_hal_gpio.c.

References assert_param, GPIO_GET_INDEX, and GPIO_NUMBER.

void HAL_GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_InitTypeDef * | GPIO_Init
 | ) |  |

Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.

Parameters:
GPIOx,: where x can be (A..K) to select the GPIO peripheral.
GPIO_Init,: pointer to a GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
Return values:
None

Definition at line 188 of file stm32h7xx_hal_gpio.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, GPIO_InitTypeDef::Alternate, assert_param, EXTI_MODE, FALLING_EDGE, GPIO_GET_INDEX, GPIO_MODE, GPIO_MODE_AF_OD, GPIO_MODE_AF_PP, GPIO_MODE_EVT, GPIO_MODE_IT, GPIO_MODE_OUTPUT_OD, GPIO_MODE_OUTPUT_PP, GPIO_NUMBER, GPIO_OUTPUT_TYPE, IS_GPIO_AF, IS_GPIO_MODE, IS_GPIO_PIN, IS_GPIO_PULL, IS_GPIO_SPEED, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, RISING_EDGE, and GPIO_InitTypeDef::Speed.

Referenced by HAL_RCC_MCOConfig().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
GPIO Exported Functions

GPIO Read, Write, Toggle, Lock and EXTI management functions. More...

Functions

GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Sets or clears the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggles the specified GPIO pins.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
Handle EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.

Detailed Description

GPIO Read, Write, Toggle, Lock and EXTI management functions.

 ===============================================================================
                       ##### IO operation functions #####
 ===============================================================================

Function Documentation

void HAL_GPIO_EXTI_Callback ( uint16_t GPIO_Pin )

EXTI line detection callback.

Parameters:
GPIO_Pin,: Specifies the port pin connected to corresponding EXTI line.
Return values:
None

Definition at line 522 of file stm32h7xx_hal_gpio.c.

Referenced by HAL_GPIO_EXTI_IRQHandler().

void HAL_GPIO_EXTI_IRQHandler ( uint16_t GPIO_Pin )

Handle EXTI interrupt request.

Parameters:
GPIO_Pin,: Specifies the port pin connected to corresponding EXTI line.
Return values:
None

Definition at line 505 of file stm32h7xx_hal_gpio.c.

References __HAL_GPIO_EXTI_CLEAR_IT, __HAL_GPIO_EXTI_GET_IT, and HAL_GPIO_EXTI_Callback().

HAL_StatusTypeDef HAL_GPIO_LockPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Locks GPIO Pins configuration registers.

Note:
The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
The configuration of the locked GPIO pins can no longer be modified until the next reset.
Parameters:
GPIOx,: where x can be (A..K) to select the GPIO peripheral for STM32H7 family
GPIO_Pin,: specifies the port bit to be locked. This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
Return values:
None

Definition at line 471 of file stm32h7xx_hal_gpio.c.

References assert_param, and IS_GPIO_PIN.

GPIO_PinState HAL_GPIO_ReadPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Reads the specified input port pin.

Parameters:
GPIOx,: where x can be (A..K) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to read. This parameter can be GPIO_PIN_x where x can be (0..15).
Return values:
The input port pin value.

Definition at line 396 of file stm32h7xx_hal_gpio.c.

References assert_param, GPIO_PIN_RESET, GPIO_PIN_SET, and IS_GPIO_PIN.

void HAL_GPIO_TogglePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Toggles the specified GPIO pins.

Parameters:
GPIOx,: Where x can be (A..K) to select the GPIO peripheral.
GPIO_Pin,: Specifies the pins to be toggled.
Return values:
None

Definition at line 452 of file stm32h7xx_hal_gpio.c.

References assert_param, and IS_GPIO_PIN.

void HAL_GPIO_WritePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin,
 |  | GPIO_PinState | PinState
 | ) |  |

Sets or clears the selected data port bit.

Note:
This function uses GPIOx_BSRR register to allow atomic read/modify accesses. In this way, there is no risk of an IRQ occurring between the read and the modify access.
Parameters:
GPIOx,: where x can be (A..K) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to be written. This parameter can be one of GPIO_PIN_x where x can be (0..15).
PinState,: specifies the value to be written to the selected bit. This parameter can be one of the GPIO_PinState enum values:
  • GPIO_PIN_RESET: to clear the port pin
  • GPIO_PIN_SET: to set the port pin
Return values:
None

Definition at line 430 of file stm32h7xx_hal_gpio.c.

References assert_param, GPIO_PIN_RESET, IS_GPIO_PIN, and IS_GPIO_PIN_ACTION.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: GPIO Exported Types

Data Structures | Enumerations
GPIO Exported Types
GPIO

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Enumerations

enum | GPIO_PinState { GPIO_PIN_RESET = 0, GPIO_PIN_SET }
GPIO Bit SET and Bit RESET enumeration. More...

Enumeration Type Documentation

enum GPIO_PinState

GPIO Bit SET and Bit RESET enumeration.

Enumerator:
GPIO_PIN_RESET
GPIO_PIN_SET

Definition at line 86 of file stm32h7xx_hal_gpio.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: GPIO_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
GPIO_InitTypeDef Struct Reference
GPIO Exported Types

GPIO Init structure definition. More...

#include <stm32h7xx_hal_gpio.h>

Data Fields

uint32_t | Pin
uint32_t | Mode
uint32_t | Pull
uint32_t | Speed
uint32_t | Alternate

Detailed Description

GPIO Init structure definition.

Definition at line 65 of file stm32h7xx_hal_gpio.h.

Field Documentation

uint32_t GPIO_InitTypeDef::Alternate

Peripheral to be connected to the selected pins. This parameter can be a value of GPIO Alternate Function Selection

Definition at line 79 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Mode

Specifies the operating mode for the selected pins. This parameter can be a value of GPIO mode define

Definition at line 70 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Pin

Specifies the GPIO pins to be configured. This parameter can be any value of GPIO pins define

Definition at line 67 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Pull

Specifies the Pull-up or Pull-Down activation for the selected pins. This parameter can be a value of GPIO pull define

Definition at line 73 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Speed

Specifies the speed for the selected pins. This parameter can be a value of GPIO speed define

Definition at line 76 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_gpio.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: GPIO pins define

Defines
GPIO pins define
GPIO Exported Constants

Defines

#define | GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
#define | GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
#define | GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
#define | GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
#define | GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
#define | GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
#define | GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
#define | GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
#define | GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
#define | GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
#define | GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
#define | GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
#define | GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
#define | GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
#define | GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
#define | GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
#define | GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
#define | GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */

Define Documentation

#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */

Definition at line 104 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */

Definition at line 105 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */

Definition at line 114 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */

Definition at line 115 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */

Definition at line 116 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */

Definition at line 117 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */

Definition at line 118 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */

Definition at line 119 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */

Definition at line 106 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */

Definition at line 107 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */

Definition at line 108 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */

Definition at line 109 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */

Definition at line 110 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */

Definition at line 111 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */

Definition at line 112 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */

Definition at line 113 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */

Definition at line 120 of file stm32h7xx_hal_gpio.h.

#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */

Definition at line 122 of file stm32h7xx_hal_gpio.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: GPIO mode define

Defines
GPIO mode define
GPIO Exported Constants

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ. More...

Defines

#define | GPIO_MODE_INPUT ((uint32_t)0x00000000U)
#define | GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U)
#define | GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U)
#define | GPIO_MODE_AF_PP ((uint32_t)0x00000002U)
#define | GPIO_MODE_AF_OD ((uint32_t)0x00000012U)
#define | GPIO_MODE_ANALOG ((uint32_t)0x00000003U)
#define | GPIO_MODE_IT_RISING ((uint32_t)0x11110000U)
#define | GPIO_MODE_IT_FALLING ((uint32_t)0x11210000U)
#define | GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x11310000U)
#define | GPIO_MODE_EVT_RISING ((uint32_t)0x11120000U)
#define | GPIO_MODE_EVT_FALLING ((uint32_t)0x11220000U)
#define | GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x11320000U)

Detailed Description

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ.

  • X : GPIO mode or EXTI Mode
  • y : External IT or Event trigger detection
  • z : IO configuration on External IT or Event
  • Y : Output type (Push Pull or Open Drain)
  • Z : IO Direction mode (Input, Output, Alternate or Analog)

Define Documentation

#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U)

Alternate Function Open Drain Mode

Definition at line 141 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U)

Alternate Function Push Pull Mode

Definition at line 140 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U)

Analog Mode

Definition at line 143 of file stm32h7xx_hal_gpio.h.

#define GPIO_MODE_EVT_FALLING ((uint32_t)0x11220000U)

External Event Mode with Falling edge trigger detection

Definition at line 150 of file stm32h7xx_hal_gpio.h.

#define GPIO_MODE_EVT_RISING ((uint32_t)0x11120000U)

External Event Mode with Rising edge trigger detection

Definition at line 149 of file stm32h7xx_hal_gpio.h.

#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x11320000U)

External Event Mode with Rising/Falling edge trigger detection

Definition at line 151 of file stm32h7xx_hal_gpio.h.

#define GPIO_MODE_INPUT ((uint32_t)0x00000000U)

Input Floating Mode

Definition at line 137 of file stm32h7xx_hal_gpio.h.

#define GPIO_MODE_IT_FALLING ((uint32_t)0x11210000U)

External Interrupt Mode with Falling edge trigger detection

Definition at line 146 of file stm32h7xx_hal_gpio.h.

#define GPIO_MODE_IT_RISING ((uint32_t)0x11110000U)

External Interrupt Mode with Rising edge trigger detection

Definition at line 145 of file stm32h7xx_hal_gpio.h.

#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x11310000U)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 147 of file stm32h7xx_hal_gpio.h.

#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U)

Output Open Drain Mode

Definition at line 139 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U)

Output Push Pull Mode

Definition at line 138 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: GPIO speed define

Defines
GPIO speed define
GPIO Exported Constants

GPIO Output Maximum frequency. More...

Defines

#define | GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U)
#define | GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U)
#define | GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U)
#define | GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U)

Detailed Description

GPIO Output Maximum frequency.

Define Documentation

#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U)

Fast speed

Definition at line 163 of file stm32h7xx_hal_gpio.h.

#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U)

Low speed

Definition at line 161 of file stm32h7xx_hal_gpio.h.

#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U)

Medium speed

Definition at line 162 of file stm32h7xx_hal_gpio.h.

#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U)

High speed

Definition at line 164 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_RCC_MCOConfig().

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STM32H753xx HAL User Manual: GPIO pull define

Defines
GPIO pull define
GPIO Exported Constants

GPIO Pull-Up or Pull-Down Activation. More...

Defines

#define | GPIO_NOPULL ((uint32_t)0x00000000U)
#define | GPIO_PULLUP ((uint32_t)0x00000001U)
#define | GPIO_PULLDOWN ((uint32_t)0x00000002U)

Detailed Description

GPIO Pull-Up or Pull-Down Activation.

Define Documentation

#define GPIO_NOPULL ((uint32_t)0x00000000U)

No Pull-up or Pull-down activation

Definition at line 173 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_RCC_MCOConfig().

#define GPIO_PULLDOWN ((uint32_t)0x00000002U)

Pull-down activation

Definition at line 175 of file stm32h7xx_hal_gpio.h.

#define GPIO_PULLUP ((uint32_t)0x00000001U)

Pull-up activation

Definition at line 174 of file stm32h7xx_hal_gpio.h.

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STM32H753xx HAL User Manual: GPIO Exported Macros

Defines
GPIO Exported Macros
GPIO

Defines

#define | __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__))
Checks whether the specified EXTI line flag is set or not.
#define | __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__))
Clears the EXTI's line pending flags.
#define | __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__))
Checks whether the specified EXTI line is asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__))
Clears the EXTI's line pending bits.
#define | __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
Generates a Software interrupt on selected EXTI line.

Define Documentation

#define __HAL_GPIO_EXTI_CLEAR_FLAG ( __EXTI_LINE__ ) (EXTI_D1->PR1 = (__EXTI_LINE__))

Clears the EXTI's line pending flags.

Parameters:
__EXTI_LINE__,: specifies the EXTI lines flags to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 203 of file stm32h7xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_CLEAR_IT ( __EXTI_LINE__ ) (EXTI_D1->PR1 = (__EXTI_LINE__))

Clears the EXTI's line pending bits.

Parameters:
__EXTI_LINE__,: specifies the EXTI lines to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 219 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

#define __HAL_GPIO_EXTI_GENERATE_SWIT ( __EXTI_LINE__ ) (EXTI->SWIER1 |= (__EXTI_LINE__))

Generates a Software interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__,: specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
None

Definition at line 227 of file stm32h7xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_GET_FLAG ( __EXTI_LINE__ ) (EXTI_D1->PR1 & (__EXTI_LINE__))

Checks whether the specified EXTI line flag is set or not.

Parameters:
__EXTI_LINE__,: specifies the EXTI line flag to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 195 of file stm32h7xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_GET_IT ( __EXTI_LINE__ ) (EXTI_D1->PR1 & (__EXTI_LINE__))

Checks whether the specified EXTI line is asserted or not.

Parameters:
__EXTI_LINE__,: specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 211 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: GPIO Private Constants

Defines
GPIO Private Constants
GPIO

Defines

#define | GPIO_MODE ((uint32_t)0x00000003)
#define | ANALOG_MODE ((uint32_t)0x00000008)
#define | EXTI_MODE ((uint32_t)0x10000000)
#define | GPIO_MODE_IT ((uint32_t)0x00010000)
#define | GPIO_MODE_EVT ((uint32_t)0x00020000)
#define | RISING_EDGE ((uint32_t)0x00100000)
#define | FALLING_EDGE ((uint32_t)0x00200000)
#define | GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
#define | GPIO_NUMBER ((uint32_t)16)

Define Documentation

#define ANALOG_MODE ((uint32_t)0x00000008)

Definition at line 145 of file stm32h7xx_hal_gpio.c.

#define EXTI_MODE ((uint32_t)0x10000000)

Definition at line 146 of file stm32h7xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define FALLING_EDGE ((uint32_t)0x00200000)

Definition at line 150 of file stm32h7xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE ((uint32_t)0x00000003)

Definition at line 144 of file stm32h7xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_EVT ((uint32_t)0x00020000)

Definition at line 148 of file stm32h7xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_IT ((uint32_t)0x00010000)

Definition at line 147 of file stm32h7xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_NUMBER ((uint32_t)16)

Definition at line 153 of file stm32h7xx_hal_gpio.c.

Referenced by HAL_GPIO_DeInit(), and HAL_GPIO_Init().

#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)

Definition at line 151 of file stm32h7xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define RISING_EDGE ((uint32_t)0x00100000)

Definition at line 149 of file stm32h7xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

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STM32H753xx HAL User Manual: GPIO Private Macros

Defines
GPIO Private Macros
GPIO

Defines

#define | IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define | IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK ) != (uint32_t)0x00))
#define | IS_GPIO_MODE(MODE)
#define | IS_GPIO_SPEED(SPEED)
#define | IS_GPIO_PULL(PULL)

Define Documentation

#define IS_GPIO_MODE ( MODE )
Value:
(((MODE) == GPIO_MODE_INPUT)              ||\
                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
                            ((MODE) == GPIO_MODE_AF_PP)              ||\
                            ((MODE) == GPIO_MODE_AF_OD)              ||\
                            ((MODE) == GPIO_MODE_IT_RISING)          ||\
                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\
                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\
                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
                            ((MODE) == GPIO_MODE_ANALOG))

Definition at line 285 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define IS_GPIO_PIN ( __PIN__ ) ((((__PIN__) & GPIO_PIN_MASK ) != (uint32_t)0x00))

Definition at line 284 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), HAL_GPIO_LockPin(), HAL_GPIO_ReadPin(), HAL_GPIO_TogglePin(), and HAL_GPIO_WritePin().

#define IS_GPIO_PIN_ACTION ( ACTION ) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))

Definition at line 283 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_WritePin().

#define IS_GPIO_PULL ( PULL )
Value:
(((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
                            ((PULL) == GPIO_PULLDOWN))

Definition at line 300 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define IS_GPIO_SPEED ( SPEED )
Value:
(((SPEED) == GPIO_SPEED_FREQ_LOW)  || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
                              ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))

Definition at line 297 of file stm32h7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

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STM32H753xx HAL User Manual: GPIO Private Functions

GPIO Private Functions
GPIO
Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH Digest Calculation Status

Defines
HASH Digest Calculation Status
HASH Private Constants

Defines

#define | HASH_DIGEST_CALCULATION_NOT_STARTED ((uint32_t)0x00000000)
#define | HASH_DIGEST_CALCULATION_STARTED ((uint32_t)0x00000001)

Define Documentation

#define HASH_DIGEST_CALCULATION_NOT_STARTED ((uint32_t)0x00000000)

DCAL not set after input data written in DIN register

Definition at line 163 of file stm32h7xx_hal_hash.c.

Referenced by HASH_Write_Block_Data().

#define HASH_DIGEST_CALCULATION_STARTED ((uint32_t)0x00000001)

DCAL set after input data written in DIN register

Definition at line 164 of file stm32h7xx_hal_hash.c.

Referenced by HASH_IT(), and HASH_Write_Block_Data().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH Number of Context Swap Registers

Defines
HASH Number of Context Swap Registers
HASH Private Constants

Defines

#define HASH_NUMBER_OF_CSR_REGISTERS 54

Define Documentation

#define HASH_NUMBER_OF_CSR_REGISTERS 54

Number of Context Swap Registers

Definition at line 172 of file stm32h7xx_hal_hash.c.

Referenced by HAL_HASH_ContextRestoring(), and HAL_HASH_ContextSaving().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH TimeOut Value

Defines
HASH TimeOut Value
HASH Private Constants

Defines

#define HASH_TIMEOUTVALUE 1000

Define Documentation

#define HASH_TIMEOUTVALUE 1000

Time-out value

Definition at line 180 of file stm32h7xx_hal_hash.c.

Referenced by HAL_HASH_DMAFeed_ProcessSuspend(), and HASH_IT().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH Private Functions

Functions
HASH Private Functions
HASH

Functions

static void | HASH_DMAXferCplt (DMA_HandleTypeDef *hdma)
DMA HASH Input Data transfer completion callback.
static void | HASH_DMAError (DMA_HandleTypeDef *hdma)
DMA HASH communication error callback.
static void | HASH_GetDigest (uint8_t *pMsgDigest, uint8_t Size)
Retrieve the message digest.
static HAL_StatusTypeDef | HASH_WaitOnFlagUntilTimeout (HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
Handle HASH processing Timeout.
static HAL_StatusTypeDef | HASH_WriteData (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Feed the input buffer to the HASH IP.
static HAL_StatusTypeDef | HASH_IT (HASH_HandleTypeDef *hhash)
HASH processing in interruption mode.
static uint32_t | HASH_Write_Block_Data (HASH_HandleTypeDef *hhash)
Write a block of data in HASH IP in interruption mode.
static HAL_StatusTypeDef | HMAC_Processing (HASH_HandleTypeDef *hhash, uint32_t Timeout)
HMAC processing in polling mode.
HAL_StatusTypeDef | HASH_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
Initialize the HASH peripheral, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HASH_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
If not already done, initialize the HASH peripheral then processes pInBuffer.
HAL_StatusTypeDef | HASH_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm)
Initialize the HASH peripheral, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HASH_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
Initialize the HASH peripheral then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HASH_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest.
HAL_StatusTypeDef | HMAC_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
Initialize the HASH peripheral in HMAC mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HMAC_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm)
Initialize the HASH peripheral in HMAC mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HMAC_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
Initialize the HASH peripheral in HMAC mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.

Function Documentation

HAL_StatusTypeDef HASH_Accumulate | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint32_t | Algorithm
 | ) |  |

If not already done, initialize the HASH peripheral then processes pInBuffer.

Note:
Field hhash->Phase of HASH handle is tested to check whether or not the IP has already been initialized.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes, must be a multiple of 4.
Algorithm,: HASH algorithm.
Return values:
HAL status

Definition at line 2003 of file stm32h7xx_hal_hash.c.

References assert_param, HAL_HASH_PHASE_PROCESS, HAL_HASH_PHASE_READY, HAL_HASH_STATE_BUSY, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HASH_WriteData(), HASH_HandleTypeDef::HashInCount, IS_HASH_POLLING_MULTIBUFFER_SIZE, HASH_HandleTypeDef::Phase, HASH_HandleTypeDef::pHashInBuffPtr, HASH_HandleTypeDef::State, and HASH_HandleTypeDef::Status.

Referenced by HAL_HASH_MD5_Accumulate(), HAL_HASH_SHA1_Accumulate(), HAL_HASHEx_SHA224_Accumulate(), and HAL_HASHEx_SHA256_Accumulate().

static void HASH_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA HASH communication error callback.

Parameters:
hdma,: DMA handle.
Note:
HASH_DMAError() callback invokes HAL_HASH_ErrorCallback() that can contain user code to manage the error.
Return values:
None

Definition at line 1272 of file stm32h7xx_hal_hash.c.

References HAL_HASH_ErrorCallback(), HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HASH_HandleTypeDef::State, and HASH_HandleTypeDef::Status.

Referenced by HASH_Start_DMA(), and HMAC_Start_DMA().

static void HASH_DMAXferCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA HASH Input Data transfer completion callback.

Parameters:
hdma,: DMA handle.
Note:
In case of HMAC processing, HASH_DMAXferCplt() initiates the next DMA transfer for the following HMAC step.
Return values:
None

Definition at line 1161 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_SET_MDMAT, __HAL_HASH_SET_NBVALIDBITS, HASH_HandleTypeDef::DigestCalculationDisable, HAL_DMA_Start_IT(), HAL_HASH_InCpltCallback(), HAL_HASH_PHASE_HMAC_STEP_1, HAL_HASH_PHASE_HMAC_STEP_2, HAL_HASH_PHASE_HMAC_STEP_3, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HASH_HandleTypeDef::HashBuffSize, HASH_HandleTypeDef::HashInCount, HASH_HandleTypeDef::hdmain, HASH_HandleTypeDef::Init, HASH_InitTypeDef::KeySize, HASH_HandleTypeDef::Phase, HASH_HandleTypeDef::pHashInBuffPtr, HASH_HandleTypeDef::pHashMsgBuffPtr, HASH_InitTypeDef::pKey, HASH_HandleTypeDef::State, and __DMA_HandleTypeDef::XferCpltCallback.

Referenced by HASH_Start_DMA(), and HMAC_Start_DMA().

HAL_StatusTypeDef HASH_Finish | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Return the computed digest.

Note:
The API waits for DCIS to be set then reads the computed digest.
Parameters:
hhash,: HASH handle.
pOutBuffer,: pointer to the computed digest.
Timeout,: Timeout value.
Return values:
HAL status

Definition at line 2281 of file stm32h7xx_hal_hash.c.

References HAL_HASH_STATE_BUSY, HAL_HASH_STATE_READY, HASH_DIGEST_LENGTH, HASH_FLAG_DCIS, HASH_GetDigest(), HASH_WaitOnFlagUntilTimeout(), and HASH_HandleTypeDef::State.

Referenced by HAL_HASH_MD5_Finish(), HAL_HASH_SHA1_Finish(), HAL_HASHEx_SHA224_Finish(), and HAL_HASHEx_SHA256_Finish().

static void HASH_GetDigest | ( | uint8_t * | pMsgDigest,
 |  | uint8_t | Size
 | ) |  | [static]

Retrieve the message digest.

Parameters:
pMsgDigest,: pointer to the computed digest.
Size,: message digest size in bytes.
Return values:
None

Definition at line 1365 of file stm32h7xx_hal_hash.c.

Referenced by HASH_Finish(), HASH_IT(), HASH_Start(), and HMAC_Processing().

static HAL_StatusTypeDef HASH_IT ( HASH_HandleTypeDef * hhash ) [static]

HASH processing in interruption mode.

Parameters:
hhash,: HASH handle.
Note:
HASH_IT() regularly reads hhash->SuspendRequest to check whether or not the HASH processing must be suspended. If this is the case, the processing is suspended when possible and the IP feeding point reached at suspension time is stored in the handle for resumption later on.
Return values:
HAL status

Definition at line 1501 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_DISABLE_IT, __HAL_HASH_ENABLE_IT, __HAL_HASH_GET_FLAG, __HAL_HASH_SET_NBVALIDBITS, HAL_HASH_DgstCpltCallback(), HAL_HASH_InCpltCallback(), HAL_HASH_PHASE_HMAC_STEP_1, HAL_HASH_PHASE_HMAC_STEP_2, HAL_HASH_PHASE_HMAC_STEP_3, HAL_HASH_STATE_BUSY, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HAL_HASH_SUSPEND, HAL_HASH_SUSPEND_NONE, HASH_DIGEST_CALCULATION_STARTED, HASH_DIGEST_LENGTH, HASH_FLAG_BUSY, HASH_FLAG_DCIS, HASH_FLAG_DINIS, HASH_GetDigest(), HASH_IT_DCI, HASH_IT_DINI, HASH_TIMEOUTVALUE, HASH_WaitOnFlagUntilTimeout(), HASH_Write_Block_Data(), HASH_HandleTypeDef::HashBuffSize, HASH_HandleTypeDef::HashInCount, HASH_HandleTypeDef::HashITCounter, HASH_HandleTypeDef::Init, HASH_InitTypeDef::KeySize, HASH_HandleTypeDef::Phase, HASH_HandleTypeDef::pHashInBuffPtr, HASH_HandleTypeDef::pHashMsgBuffPtr, HASH_HandleTypeDef::pHashOutBuffPtr, HASH_InitTypeDef::pKey, HASH_HandleTypeDef::State, and HASH_HandleTypeDef::SuspendRequest.

Referenced by HAL_HASH_IRQHandler().

HAL_StatusTypeDef HASH_Start | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout,
 |  | uint32_t | Algorithm
 | ) |  |

Initialize the HASH peripheral, next process pInBuffer then read the computed digest.

Note:
Digest is available in pOutBuffer.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest.
Timeout,: Timeout value.
Algorithm,: HASH algorithm.
Return values:
HAL status

Definition at line 1873 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_SET_NBVALIDBITS, __HAL_HASH_START_DIGEST, HAL_HASH_PHASE_PROCESS, HAL_HASH_PHASE_READY, HAL_HASH_STATE_BUSY, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HASH_DIGEST_LENGTH, HASH_FLAG_DCIS, HASH_GetDigest(), HASH_WaitOnFlagUntilTimeout(), HASH_WriteData(), HASH_HandleTypeDef::HashInCount, HASH_HandleTypeDef::Phase, HASH_HandleTypeDef::pHashInBuffPtr, HASH_HandleTypeDef::State, and HASH_HandleTypeDef::Status.

Referenced by HAL_HASH_MD5_Start(), HAL_HASH_SHA1_Start(), HAL_HASHEx_SHA224_Start(), and HAL_HASHEx_SHA256_Start().

HAL_StatusTypeDef HASH_Start_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint32_t | Algorithm
 | ) |  |

Initialize the HASH peripheral then initiate a DMA transfer to feed the input buffer to the IP.

Note:
If MDMAT bit is set before calling this function (multi-buffer HASH processing case), the input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted. For the processing of the last buffer of the thread, MDMAT bit must be reset and the buffer length (in bytes) doesn't have to be a multiple of 4.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
Algorithm,: HASH algorithm.
Return values:
HAL status

Definition at line 2179 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_SET_NBVALIDBITS, assert_param, HAL_DMA_Start_IT(), HAL_HASH_PHASE_PROCESS, HAL_HASH_PHASE_READY, HAL_HASH_STATE_BUSY, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HASH_DMAError(), HASH_DMAXferCplt(), HASH_HandleTypeDef::HashInCount, HASH_HandleTypeDef::hdmain, IS_HASH_DMA_MULTIBUFFER_SIZE, IS_HASH_PROCESSING, HASH_HandleTypeDef::Phase, HASH_HandleTypeDef::pHashInBuffPtr, HASH_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by HAL_HASH_MD5_Start_DMA(), HAL_HASH_SHA1_Start_DMA(), HAL_HASHEx_SHA224_Start_DMA(), and HAL_HASHEx_SHA256_Start_DMA().

HAL_StatusTypeDef HASH_Start_IT | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Algorithm
 | ) |  |

Initialize the HASH peripheral, next process pInBuffer then read the computed digest in interruption mode.

Note:
Digest is available in pOutBuffer.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest.
Algorithm,: HASH algorithm.
Return values:
HAL status

Definition at line 2100 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_ENABLE_IT, __HAL_HASH_SET_NBVALIDBITS, HAL_HASH_PHASE_PROCESS, HAL_HASH_PHASE_READY, HAL_HASH_STATE_BUSY, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HASH_IT_DCI, HASH_IT_DINI, HASH_HandleTypeDef::HashInCount, HASH_HandleTypeDef::HashITCounter, HASH_HandleTypeDef::Phase, HASH_HandleTypeDef::pHashInBuffPtr, HASH_HandleTypeDef::pHashOutBuffPtr, and HASH_HandleTypeDef::State.

Referenced by HAL_HASH_MD5_Start_IT(), HAL_HASH_SHA1_Start_IT(), HAL_HASHEx_SHA224_Start_IT(), and HAL_HASHEx_SHA256_Start_IT().

static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout | ( | HASH_HandleTypeDef * | hhash,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle HASH processing Timeout.

Parameters:
hhash,: HASH handle.
Flag,: specifies the HASH flag to check.
Status,: the Flag status (SET or RESET).
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 1439 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_GET_FLAG, HAL_GetTick(), HAL_HASH_STATE_READY, HASH_HandleTypeDef::State, and HASH_HandleTypeDef::Status.

Referenced by HAL_HASH_DMAFeed_ProcessSuspend(), HASH_Finish(), HASH_IT(), HASH_Start(), and HMAC_Processing().

static uint32_t HASH_Write_Block_Data ( HASH_HandleTypeDef * hhash ) [static]

Write a block of data in HASH IP in interruption mode.

Parameters:
hhash,: HASH handle.
Note:
HASH_Write_Block_Data() is called under interruption by HASH_IT().
Return values:
HAL status

Definition at line 1626 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_DISABLE_IT, __HAL_HASH_START_DIGEST, HASH_DIGEST_CALCULATION_NOT_STARTED, HASH_DIGEST_CALCULATION_STARTED, HASH_IT_DINI, HASH_HandleTypeDef::HashInCount, HASH_HandleTypeDef::HashITCounter, and HASH_HandleTypeDef::pHashInBuffPtr.

Referenced by HASH_IT().

static HAL_StatusTypeDef HASH_WriteData | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  | [static]

Feed the input buffer to the HASH IP.

Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to input buffer.
Size,: the size of input buffer in bytes.
Note:
HASH_WriteData() regularly reads hhash->SuspendRequest to check whether or not the HASH processing must be suspended. If this is the case, the processing is suspended when possible and the IP feeding point reached at suspension time is stored in the handle for resumption later on.
Return values:
HAL status

Definition at line 1301 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_GET_FLAG, HAL_HASH_PHASE_HMAC_STEP_1, HAL_HASH_PHASE_HMAC_STEP_2, HAL_HASH_PHASE_HMAC_STEP_3, HAL_HASH_PHASE_PROCESS, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HAL_HASH_SUSPEND, HAL_HASH_SUSPEND_NONE, HASH_FLAG_DINIS, HASH_HandleTypeDef::HashInCount, HASH_HandleTypeDef::HashKeyCount, HASH_HandleTypeDef::Phase, HASH_HandleTypeDef::pHashInBuffPtr, HASH_HandleTypeDef::pHashKeyBuffPtr, HASH_HandleTypeDef::State, and HASH_HandleTypeDef::SuspendRequest.

Referenced by HASH_Accumulate(), HASH_Start(), and HMAC_Processing().

static HAL_StatusTypeDef HMAC_Processing | ( | HASH_HandleTypeDef * | hhash,
 |  | uint32_t | Timeout
 | ) |  | [static]

HMAC processing in polling mode.

Parameters:
hhash,: HASH handle.
Timeout,: Timeout value.
Return values:
HAL status

Definition at line 1712 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_SET_NBVALIDBITS, __HAL_HASH_START_DIGEST, HAL_HASH_PHASE_HMAC_STEP_1, HAL_HASH_PHASE_HMAC_STEP_2, HAL_HASH_PHASE_HMAC_STEP_3, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HASH_DIGEST_LENGTH, HASH_FLAG_BUSY, HASH_FLAG_DCIS, HASH_GetDigest(), HASH_WaitOnFlagUntilTimeout(), HASH_WriteData(), HASH_HandleTypeDef::HashBuffSize, HASH_HandleTypeDef::HashInCount, HASH_HandleTypeDef::HashKeyCount, HASH_HandleTypeDef::Init, HASH_InitTypeDef::KeySize, HASH_HandleTypeDef::Phase, HASH_HandleTypeDef::pHashInBuffPtr, HASH_HandleTypeDef::pHashKeyBuffPtr, HASH_HandleTypeDef::pHashOutBuffPtr, HASH_InitTypeDef::pKey, HASH_HandleTypeDef::State, and HASH_HandleTypeDef::Status.

Referenced by HMAC_Start().

HAL_StatusTypeDef HMAC_Start | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout,
 |  | uint32_t | Algorithm
 | ) |  |

Initialize the HASH peripheral in HMAC mode, next process pInBuffer then read the computed digest.

Note:
Digest is available in pOutBuffer.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest.
Timeout,: Timeout value.
Algorithm,: HASH algorithm.
Return values:
HAL status

Definition at line 2339 of file stm32h7xx_hal_hash.c.

References HAL_HASH_PHASE_HMAC_STEP_1, HAL_HASH_PHASE_READY, HAL_HASH_STATE_BUSY, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HASH_ALGOMODE_HMAC, HASH_HMAC_KEYTYPE_LONGKEY, HASH_HandleTypeDef::HashBuffSize, HASH_HandleTypeDef::HashInCount, HASH_HandleTypeDef::HashKeyCount, HMAC_Processing(), HASH_HandleTypeDef::Init, HASH_InitTypeDef::KeySize, HASH_HandleTypeDef::Phase, HASH_HandleTypeDef::pHashInBuffPtr, HASH_HandleTypeDef::pHashKeyBuffPtr, HASH_HandleTypeDef::pHashOutBuffPtr, HASH_InitTypeDef::pKey, and HASH_HandleTypeDef::State.

Referenced by HAL_HMAC_MD5_Start(), HAL_HMAC_SHA1_Start(), HAL_HMACEx_SHA224_Start(), and HAL_HMACEx_SHA256_Start().

HAL_StatusTypeDef HMAC_Start_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint32_t | Algorithm
 | ) |  |

Initialize the HASH peripheral in HMAC mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.

Note:
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
In case of multi-buffer HMAC processing, the input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted. Only the length of the last buffer of the thread doesn't have to be a multiple of 4.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
Algorithm,: HASH algorithm.
Return values:
HAL status

Definition at line 2513 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_RESET_MDMAT, __HAL_HASH_SET_NBVALIDBITS, assert_param, HASH_HandleTypeDef::DigestCalculationDisable, HAL_DMA_Start_IT(), HAL_HASH_PHASE_HMAC_STEP_1, HAL_HASH_PHASE_HMAC_STEP_2, HAL_HASH_PHASE_READY, HAL_HASH_STATE_BUSY, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HASH_ALGOMODE_HMAC, HASH_DMAError(), HASH_DMAXferCplt(), HASH_HMAC_KEYTYPE_LONGKEY, HASH_HandleTypeDef::HashBuffSize, HASH_HandleTypeDef::HashInCount, HASH_HandleTypeDef::hdmain, HASH_HandleTypeDef::Init, IS_HMAC_DMA_MULTIBUFFER_SIZE, IS_HMAC_PROCESSING, HASH_InitTypeDef::KeySize, HASH_HandleTypeDef::Phase, HASH_HandleTypeDef::pHashInBuffPtr, HASH_HandleTypeDef::pHashKeyBuffPtr, HASH_HandleTypeDef::pHashMsgBuffPtr, HASH_InitTypeDef::pKey, HASH_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by HAL_HMAC_MD5_Start_DMA(), HAL_HMAC_SHA1_Start_DMA(), HAL_HMACEx_MD5_Step1_2_DMA(), HAL_HMACEx_MD5_Step2_3_DMA(), HAL_HMACEx_MD5_Step2_DMA(), HAL_HMACEx_SHA1_Step1_2_DMA(), HAL_HMACEx_SHA1_Step2_3_DMA(), HAL_HMACEx_SHA1_Step2_DMA(), HAL_HMACEx_SHA224_Start_DMA(), HAL_HMACEx_SHA224_Step1_2_DMA(), HAL_HMACEx_SHA224_Step2_3_DMA(), HAL_HMACEx_SHA224_Step2_DMA(), HAL_HMACEx_SHA256_Start_DMA(), HAL_HMACEx_SHA256_Step1_2_DMA(), HAL_HMACEx_SHA256_Step2_3_DMA(), and HAL_HMACEx_SHA256_Step2_DMA().

HAL_StatusTypeDef HMAC_Start_IT | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Algorithm
 | ) |  |

Initialize the HASH peripheral in HMAC mode, next process pInBuffer then read the computed digest in interruption mode.

Note:
Digest is available in pOutBuffer.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest.
Algorithm,: HASH algorithm.
Return values:
HAL status

Definition at line 2408 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_ENABLE_IT, __HAL_HASH_SET_NBVALIDBITS, HAL_HASH_PHASE_HMAC_STEP_1, HAL_HASH_PHASE_HMAC_STEP_2, HAL_HASH_PHASE_HMAC_STEP_3, HAL_HASH_PHASE_READY, HAL_HASH_STATE_BUSY, HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HASH_ALGOMODE_HMAC, HASH_HMAC_KEYTYPE_LONGKEY, HASH_IT_DCI, HASH_IT_DINI, HASH_HandleTypeDef::HashBuffSize, HASH_HandleTypeDef::HashInCount, HASH_HandleTypeDef::HashITCounter, HASH_HandleTypeDef::Init, HASH_InitTypeDef::KeySize, HASH_HandleTypeDef::Phase, HASH_HandleTypeDef::pHashInBuffPtr, HASH_HandleTypeDef::pHashKeyBuffPtr, HASH_HandleTypeDef::pHashMsgBuffPtr, HASH_HandleTypeDef::pHashOutBuffPtr, HASH_InitTypeDef::pKey, and HASH_HandleTypeDef::State.

Referenced by HAL_HMAC_MD5_Start_IT(), HAL_HMAC_SHA1_Start_IT(), HAL_HMACEx_SHA224_Start_IT(), and HAL_HMACEx_SHA256_Start_IT().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
HASH Exported Functions

HASH Initialization, configuration and call-back functions. More...

Functions

HAL_StatusTypeDef | HAL_HASH_Init (HASH_HandleTypeDef *hhash)
Initialize the HASH according to the specified parameters in the HASH_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_HASH_DeInit (HASH_HandleTypeDef *hhash)
DeInitialize the HASH peripheral.
__weak void | HAL_HASH_MspInit (HASH_HandleTypeDef *hhash)
Initialize the HASH MSP.
__weak void | HAL_HASH_MspDeInit (HASH_HandleTypeDef *hhash)
DeInitialize the HASH MSP.
__weak void | HAL_HASH_InCpltCallback (HASH_HandleTypeDef *hhash)
Input data transfer complete call back.
__weak void | HAL_HASH_DgstCpltCallback (HASH_HandleTypeDef *hhash)
Digest computation complete call back.
__weak void | HAL_HASH_ErrorCallback (HASH_HandleTypeDef *hhash)
Error callback.

Detailed Description

HASH Initialization, configuration and call-back functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the HASH according to the specified parameters
          in the HASH_InitTypeDef and create the associated handle
      (+) DeInitialize the HASH peripheral
      (+) Initialize the HASH MCU Specific Package (MSP)
      (+) DeInitialize the HASH MSP

    [..]  This section provides as well call back functions definitions for user
          code to manage:
      (+) Input data transfer to IP completion
      (+) Calculated digest retrieval completion
      (+) Error management

Function Documentation

HAL_StatusTypeDef HAL_HASH_DeInit ( HASH_HandleTypeDef * hhash )

DeInitialize the HASH peripheral.

Parameters:
hhash,: HASH handle.
Return values:
HAL status

Definition at line 299 of file stm32h7xx_hal_hash.c.

References HASH_HandleTypeDef::DigestCalculationDisable, HAL_HASH_MspDeInit(), HAL_HASH_PHASE_READY, HAL_HASH_STATE_BUSY, HAL_HASH_STATE_RESET, HASH_HandleTypeDef::HashBuffSize, HASH_HandleTypeDef::HashInCount, HASH_HandleTypeDef::HashITCounter, HASH_HandleTypeDef::Phase, HASH_HandleTypeDef::State, and HASH_HandleTypeDef::Status.

void HAL_HASH_DgstCpltCallback ( HASH_HandleTypeDef * hhash )

Digest computation complete call back.

Note:
HAL_HASH_DgstCpltCallback() is used under interruption, is not relevant with DMA.
Parameters:
hhash,: HASH handle.
Return values:
None

Definition at line 391 of file stm32h7xx_hal_hash.c.

Referenced by HASH_IT().

void HAL_HASH_ErrorCallback ( HASH_HandleTypeDef * hhash )

Error callback.

Note:
Code user can resort to hhash->Status (HAL_ERROR, HAL_TIMEOUT,...) to retrieve the error type.
Parameters:
hhash,: HASH handle.
Return values:
None

Definition at line 408 of file stm32h7xx_hal_hash.c.

Referenced by HAL_HASH_IRQHandler(), and HASH_DMAError().

void HAL_HASH_InCpltCallback ( HASH_HandleTypeDef * hhash )

Input data transfer complete call back.

Note:
HAL_HASH_InCpltCallback() is called when the complete input message has been fed to the IP. This API is invoked only when input data are entered under interruption or thru DMA.
In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set), HAL_HASH_InCpltCallback() is called at the end of each buffer feeding to the IP.
Parameters:
hhash,: HASH handle.
Return values:
None

Definition at line 374 of file stm32h7xx_hal_hash.c.

Referenced by HASH_DMAXferCplt(), and HASH_IT().

HAL_StatusTypeDef HAL_HASH_Init ( HASH_HandleTypeDef * hhash )

Initialize the HASH according to the specified parameters in the HASH_HandleTypeDef and create the associated handle.

Note:
Only MDMAT and DATATYPE bits of HASH IP are set by HAL_HASH_Init(), other configuration bits are set by HASH or HMAC processing APIs.
MDMAT bit is systematically reset by HAL_HASH_Init(). To set it for multi-buffer HASH processing, user needs to resort to __HAL_HASH_SET_MDMAT() macro. For HMAC multi-buffer processing, the relevant APIs manage themselves the MDMAT bit.
Parameters:
hhash,: HASH handle
Return values:
HAL status

Definition at line 249 of file stm32h7xx_hal_hash.c.

References assert_param, HASH_InitTypeDef::DataType, HASH_HandleTypeDef::DigestCalculationDisable, HAL_HASH_MspInit(), HAL_HASH_PHASE_READY, HAL_HASH_STATE_BUSY, HAL_HASH_STATE_READY, HAL_HASH_STATE_RESET, HASH_HandleTypeDef::HashBuffSize, HASH_HandleTypeDef::HashInCount, HASH_HandleTypeDef::HashITCounter, HASH_HandleTypeDef::Init, IS_HASH_DATATYPE, HASH_HandleTypeDef::Lock, HASH_HandleTypeDef::Phase, HASH_HandleTypeDef::State, and HASH_HandleTypeDef::Status.

void HAL_HASH_MspDeInit ( HASH_HandleTypeDef * hhash )

DeInitialize the HASH MSP.

Parameters:
hhash,: HASH handle.
Return values:
None

Definition at line 353 of file stm32h7xx_hal_hash.c.

Referenced by HAL_HASH_DeInit().

void HAL_HASH_MspInit ( HASH_HandleTypeDef * hhash )

Initialize the HASH MSP.

Parameters:
hhash,: HASH handle.
Return values:
None

Definition at line 338 of file stm32h7xx_hal_hash.c.

Referenced by HAL_HASH_Init().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH processing functions in polling mode

Functions
HASH processing functions in polling mode
HASH Exported Functions

HASH processing functions using polling mode. More...

Functions

HAL_StatusTypeDef | HAL_HASH_MD5_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in MD5 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASH_MD5_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in MD5 mode then processes pInBuffer.
HAL_StatusTypeDef | HAL_HASH_SHA1_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASH_SHA1_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in SHA1 mode then processes pInBuffer.

Detailed Description

HASH processing functions using polling mode.

 ===============================================================================
                 ##### Polling mode HASH processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in polling mode
          the hash value using one of the following algorithms:
      (+) MD5
         (++) HAL_HASH_MD5_Start()
         (++) HAL_HASH_MD5_Accumulate()
      (+) SHA1
         (++) HAL_HASH_SHA1_Start()
         (++) HAL_HASH_SHA1_Accumulate()

    [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().

    [..]  In case of multi-buffer HASH processing (a single digest is computed while
          several buffers are fed to the IP), the user can resort to successive calls
          to HAL_HASH_xxx_Accumulate() and wrap-up the digest computation by a call
          to HAL_HASH_xxx_Start().

Function Documentation

HAL_StatusTypeDef HAL_HASH_MD5_Accumulate | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

If not already done, initialize the HASH peripheral in MD5 mode then processes pInBuffer.

Note:
Consecutive calls to HAL_HASH_MD5_Accumulate() can be used to feed several input buffers back-to-back to the IP that will yield a single HASH signature once all buffers have been entered. Wrap-up of input buffers feeding and retrieval of digest is done by a call to HAL_HASH_MD5_Start().
Field hhash->Phase of HASH handle is tested to check whether or not the IP has already been initialized.
Digest is not retrieved by this API, user must resort to HAL_HASH_MD5_Start() to read it, feeding at the same time the last input buffer to the IP.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted. Only HAL_HASH_MD5_Start() is able to manage the ending buffer with a length in bytes not a multiple of 4.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes, must be a multiple of 4.
Return values:
HAL status

Definition at line 486 of file stm32h7xx_hal_hash.c.

References HASH_Accumulate(), and HASH_ALGOSELECTION_MD5.

HAL_StatusTypeDef HAL_HASH_MD5_Start | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Initialize the HASH peripheral in MD5 mode, next process pInBuffer then read the computed digest.

Note:
Digest is available in pOutBuffer.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 16 bytes.
Timeout,: Timeout value
Return values:
HAL status

Definition at line 461 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_MD5, and HASH_Start().

HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

If not already done, initialize the HASH peripheral in SHA1 mode then processes pInBuffer.

Note:
Consecutive calls to HAL_HASH_SHA1_Accumulate() can be used to feed several input buffers back-to-back to the IP that will yield a single HASH signature once all buffers have been entered. Wrap-up of input buffers feeding and retrieval of digest is done by a call to HAL_HASH_SHA1_Start().
Field hhash->Phase of HASH handle is tested to check whether or not the IP has already been initialized.
Digest is not retrieved by this API, user must resort to HAL_HASH_SHA1_Start() to read it, feeding at the same time the last input buffer to the IP.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted. Only HAL_HASH_SHA1_Start() is able to manage the ending buffer with a length in bytes not a multiple of 4.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes, must be a multiple of 4.
Return values:
HAL status

Definition at line 527 of file stm32h7xx_hal_hash.c.

References HASH_Accumulate(), and HASH_ALGOSELECTION_SHA1.

HAL_StatusTypeDef HAL_HASH_SHA1_Start | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then read the computed digest.

Note:
Digest is available in pOutBuffer.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 20 bytes.
Timeout,: Timeout value
Return values:
HAL status

Definition at line 502 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_SHA1, and HASH_Start().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH processing functions in interrupt mode

Functions
HASH processing functions in interrupt mode
HASH Exported Functions

HASH processing functions using interrupt mode. More...

Functions

HAL_StatusTypeDef | HAL_HASH_MD5_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in MD5 mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HAL_HASH_SHA1_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then read the computed digest in interruption mode.
void | HAL_HASH_IRQHandler (HASH_HandleTypeDef *hhash)
Handle HASH interrupt request.

Detailed Description

HASH processing functions using interrupt mode.

 ===============================================================================
                 ##### Interruption mode HASH processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in interrupt mode
          the hash value using one of the following algorithms:
      (+) MD5
         (++) HAL_HASH_MD5_Start_IT()
      (+) SHA1
         (++) HAL_HASH_SHA1_Start_IT()

    [..]  API HAL_HASH_IRQHandler() manages each HASH interruption.

    [..] Note that HAL_HASH_IRQHandler() manages as well HASH IP interruptions when in
         HMAC processing mode.

Function Documentation

void HAL_HASH_IRQHandler ( HASH_HandleTypeDef * hhash )

Handle HASH interrupt request.

Parameters:
hhash,: HASH handle.
Note:
HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well.
In case of error reported during the HASH interruption processing, HAL_HASH_ErrorCallback() API is called so that user code can manage the error. The error type is available in hhash->Status field.
Return values:
None

Definition at line 601 of file stm32h7xx_hal_hash.c.

References HAL_HASH_ErrorCallback(), HASH_IT(), and HASH_HandleTypeDef::Status.

HAL_StatusTypeDef HAL_HASH_MD5_Start_IT | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer
 | ) |  |

Initialize the HASH peripheral in MD5 mode, next process pInBuffer then read the computed digest in interruption mode.

Note:
Digest is available in pOutBuffer.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 16 bytes.
Return values:
HAL status

Definition at line 571 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_MD5, and HASH_Start_IT().

HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer
 | ) |  |

Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then read the computed digest in interruption mode.

Note:
Digest is available in pOutBuffer.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 20 bytes.
Return values:
HAL status

Definition at line 587 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_SHA1, and HASH_Start_IT().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH processing functions in DMA mode

Functions
HASH processing functions in DMA mode
HASH Exported Functions

HASH processing functions using DMA mode. More...

Functions

HAL_StatusTypeDef | HAL_HASH_MD5_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASH_MD5_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in MD5 mode.
HAL_StatusTypeDef | HAL_HASH_SHA1_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASH_SHA1_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in SHA1 mode.

Detailed Description

HASH processing functions using DMA mode.

 ===============================================================================
                    ##### DMA mode HASH processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in DMA mode
          the hash value using one of the following algorithms:
      (+) MD5
         (++) HAL_HASH_MD5_Start_DMA()
         (++) HAL_HASH_MD5_Finish()
      (+) SHA1
         (++) HAL_HASH_SHA1_Start_DMA()
         (++) HAL_HASH_SHA1_Finish()

    [..]  When resorting to DMA mode to enter the data in the IP, user must resort
          to  HAL_HASH_xxx_Start_DMA() then read the resulting digest with
          HAL_HASH_xxx_Finish().

    [..]  In case of multi-buffer HASH processing, MDMAT bit must first be set before
          the successive calls to HAL_HASH_xxx_Start_DMA(). Then, MDMAT bit needs to be
          reset before the last call to HAL_HASH_xxx_Start_DMA(). Digest is finally
          retrieved thanks to HAL_HASH_xxx_Finish().

Function Documentation

HAL_StatusTypeDef HAL_HASH_MD5_Finish | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Return the computed digest in MD5 mode.

Note:
The API waits for DCIS to be set then reads the computed digest.
HAL_HASH_MD5_Finish() can be used as well to retrieve the digest in HMAC MD5 mode.
Parameters:
hhash,: HASH handle.
pOutBuffer,: pointer to the computed digest. Digest size is 16 bytes.
Timeout,: Timeout value.
Return values:
HAL status

Definition at line 671 of file stm32h7xx_hal_hash.c.

References HASH_Finish().

HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer to feed the input buffer to the IP.

Note:
Once the DMA transfer is finished, HAL_HASH_MD5_Finish() API must be called to retrieve the computed digest.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 656 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_MD5, and HASH_Start_DMA().

HAL_StatusTypeDef HAL_HASH_SHA1_Finish | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Return the computed digest in SHA1 mode.

Note:
The API waits for DCIS to be set then reads the computed digest.
HAL_HASH_SHA1_Finish() can be used as well to retrieve the digest in HMAC SHA1 mode.
Parameters:
hhash,: HASH handle.
pOutBuffer,: pointer to the computed digest. Digest size is 20 bytes.
Timeout,: Timeout value.
Return values:
HAL status

Definition at line 702 of file stm32h7xx_hal_hash.c.

References HASH_Finish().

HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer to feed the input buffer to the IP.

Note:
Once the DMA transfer is finished, HAL_HASH_SHA1_Finish() API must be called to retrieve the computed digest.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 686 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_SHA1, and HASH_Start_DMA().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HMAC processing functions in polling mode

Functions
HMAC processing functions in polling mode
HASH Exported Functions

HMAC processing functions using polling mode. More...

Functions

HAL_StatusTypeDef | HAL_HMAC_MD5_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HMAC_SHA1_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then read the computed digest.

Detailed Description

HMAC processing functions using polling mode.

 ===============================================================================
                 ##### Polling mode HMAC processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in polling mode
          the HMAC value using one of the following algorithms:
      (+) MD5
         (++) HAL_HMAC_MD5_Start()
      (+) SHA1
         (++) HAL_HMAC_SHA1_Start()

Function Documentation

HAL_StatusTypeDef HAL_HMAC_MD5_Start | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then read the computed digest.

Note:
Digest is available in pOutBuffer.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 16 bytes.
Timeout,: Timeout value.
Return values:
HAL status

Definition at line 743 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_MD5, and HMAC_Start().

HAL_StatusTypeDef HAL_HMAC_SHA1_Start | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then read the computed digest.

Note:
Digest is available in pOutBuffer.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 20 bytes.
Timeout,: Timeout value.
Return values:
HAL status

Definition at line 761 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_SHA1, and HMAC_Start().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HMAC processing functions in interrupt mode

Functions
HMAC processing functions in interrupt mode
HASH Exported Functions

HMAC processing functions using interrupt mode. More...

Functions

HAL_StatusTypeDef | HAL_HMAC_MD5_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then read the computed digest in interrupt mode.
HAL_StatusTypeDef | HAL_HMAC_SHA1_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then read the computed digest in interrupt mode.

Detailed Description

HMAC processing functions using interrupt mode.

 ===============================================================================
                 ##### Interrupt mode HMAC processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in interrupt mode
          the HMAC value using one of the following algorithms:
      (+) MD5
         (++) HAL_HMAC_MD5_Start_IT()
      (+) SHA1
         (++) HAL_HMAC_SHA1_Start_IT()

Function Documentation

HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer
 | ) |  |

Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then read the computed digest in interrupt mode.

Note:
Digest is available in pOutBuffer.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 16 bytes.
Return values:
HAL status

Definition at line 802 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_MD5, and HMAC_Start_IT().

HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer
 | ) |  |

Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then read the computed digest in interrupt mode.

Note:
Digest is available in pOutBuffer.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 20 bytes.
Return values:
HAL status

Definition at line 819 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_SHA1, and HMAC_Start_IT().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HMAC processing functions in DMA mode

Functions
HMAC processing functions in DMA mode
HASH Exported Functions

HMAC processing functions using DMA modes. More...

Functions

HAL_StatusTypeDef | HAL_HMAC_MD5_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC MD5 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.
HAL_StatusTypeDef | HAL_HMAC_SHA1_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.

Detailed Description

HMAC processing functions using DMA modes.

 ===============================================================================
                 ##### DMA mode HMAC processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in DMA mode
          the HMAC value using one of the following algorithms:
      (+) MD5
         (++) HAL_HMAC_MD5_Start_DMA()
      (+) SHA1
         (++) HAL_HMAC_SHA1_Start_DMA()

    [..]  When resorting to DMA mode to enter the data in the IP for HMAC processing,
          user must resort to  HAL_HMAC_xxx_Start_DMA() then read the resulting digest
          with HAL_HASH_xxx_Finish().

Function Documentation

HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

Initialize the HASH peripheral in HMAC MD5 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.

Note:
Once the DMA transfers are finished (indicated by hhash->State set back to HAL_HASH_STATE_READY), HAL_HASH_MD5_Finish() API must be called to retrieve the computed digest.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
If MDMAT bit is set before calling this function (multi-buffer HASH processing case), the input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted. For the processing of the last buffer of the thread, MDMAT bit must be reset and the buffer length (in bytes) doesn't have to be a multiple of 4.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 872 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_MD5, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.

Note:
Once the DMA transfers are finished (indicated by hhash->State set back to HAL_HASH_STATE_READY), HAL_HASH_SHA1_Finish() API must be called to retrieve the computed digest.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
If MDMAT bit is set before calling this function (multi-buffer HASH processing case), the input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted. For the processing of the last buffer of the thread, MDMAT bit must be reset and the buffer length (in bytes) doesn't have to be a multiple of 4.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 897 of file stm32h7xx_hal_hash.c.

References HASH_ALGOSELECTION_SHA1, and HMAC_Start_DMA().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral states functions

Functions
Peripheral states functions
HASH Exported Functions

Peripheral State functions. More...

Functions

HAL_HASH_StateTypeDef | HAL_HASH_GetState (HASH_HandleTypeDef *hhash)
Return the HASH handle state.
HAL_StatusTypeDef | HAL_HASH_GetStatus (HASH_HandleTypeDef *hhash)
Return the HASH HAL status.
void | HAL_HASH_ContextSaving (HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
Save the HASH context in case of processing suspension.
void | HAL_HASH_ContextRestoring (HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
Restore the HASH context in case of processing resumption.
void | HAL_HASH_SwFeed_ProcessSuspend (HASH_HandleTypeDef *hhash)
Initiate HASH processing suspension when in polling or interruption mode.
HAL_StatusTypeDef | HAL_HASH_DMAFeed_ProcessSuspend (HASH_HandleTypeDef *hhash)
Suspend the HASH processing when in DMA mode.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State methods #####
 ===============================================================================
    [..]
    This section permits to get in run-time the state and the peripheral handle
    status of the peripheral:
      (+) HAL_HASH_GetState()
      (+) HAL_HASH_GetStatus()

    [..]
    Additionally, this subsection provides functions allowing to save and restore
    the HASH or HMAC processing context in case of calculation suspension:
      (+) HAL_HASH_ContextSaving()
      (+) HAL_HASH_ContextRestoring()

    [..]
    This subsection provides functions allowing to suspend the HASH processing
      (+) when input are fed to the IP by software
          (++) HAL_HASH_SwFeed_ProcessSuspend()
      (+) when input are fed to the IP by DMA
          (++) HAL_HASH_DMAFeed_ProcessSuspend()

Function Documentation

void HAL_HASH_ContextRestoring | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pMemBuffer
 | ) |  |

Restore the HASH context in case of processing resumption.

Parameters:
hhash,: HASH handle.
pMemBuffer,: pointer to the memory buffer where the HASH context is stored.
Note:
The IMR, STR, CR then all the CSR registers are restored in that order. Only the r/w bits are restored.
By default, all the context swap registers (HASH_NUMBER_OF_CSR_REGISTERS of those) are restored (all of them have been saved by default beforehand).
Return values:
None

Definition at line 1015 of file stm32h7xx_hal_hash.c.

References __HAL_HASH_INIT, and HASH_NUMBER_OF_CSR_REGISTERS.

void HAL_HASH_ContextSaving | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pMemBuffer
 | ) |  |

Save the HASH context in case of processing suspension.

Parameters:
hhash,: HASH handle.
pMemBuffer,: pointer to the memory buffer where the HASH context is saved.
Note:
The IMR, STR, CR then all the CSR registers are saved in that order. Only the r/w bits are read to be restored later on.
By default, all the context swap registers (there are HASH_NUMBER_OF_CSR_REGISTERS of those) are saved.
pMemBuffer points to a buffer allocated by the user. The buffer size must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long.
Return values:
None

Definition at line 975 of file stm32h7xx_hal_hash.c.

References HASH_IT_DCI, HASH_IT_DINI, and HASH_NUMBER_OF_CSR_REGISTERS.

HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend ( HASH_HandleTypeDef * hhash )

Suspend the HASH processing when in DMA mode.

Parameters:
hhash,: HASH handle.
Note:
When suspension attempt occurs at the very end of a DMA transfer and all the data have already been entered in the IP, hhash->State is set to HAL_HASH_STATE_READY and the API returns HAL_ERROR. It is recommended to wrap-up the processing in reading the digest as usual.
Return values:
HAL status

Definition at line 1073 of file stm32h7xx_hal_hash.c.

References HAL_DMA_Abort(), HAL_HASH_STATE_READY, HAL_HASH_STATE_SUSPENDED, HASH_FLAG_BUSY, HASH_FLAG_DMAS, HASH_TIMEOUTVALUE, HASH_WaitOnFlagUntilTimeout(), HASH_HandleTypeDef::HashInCount, HASH_HandleTypeDef::hdmain, __DMA_HandleTypeDef::Instance, HASH_HandleTypeDef::pHashInBuffPtr, and HASH_HandleTypeDef::State.

HAL_HASH_StateTypeDef HAL_HASH_GetState ( HASH_HandleTypeDef * hhash )

Return the HASH handle state.

Note:
The API yields the current state of the handle (BUSY, READY,...).
Parameters:
hhash,: HASH handle.
Return values:
HAL HASH state

Definition at line 944 of file stm32h7xx_hal_hash.c.

References HASH_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HASH_GetStatus ( HASH_HandleTypeDef * hhash )

Return the HASH HAL status.

Note:
The API yields the HAL status of the handle: it is the result of the latest HASH processing and allows to report any issue (e.g. HAL_TIMEOUT).
Parameters:
hhash,: HASH handle.
Return values:
HAL status

Definition at line 957 of file stm32h7xx_hal_hash.c.

References HASH_HandleTypeDef::Status.

void HAL_HASH_SwFeed_ProcessSuspend ( HASH_HandleTypeDef * hhash )

Initiate HASH processing suspension when in polling or interruption mode.

Parameters:
hhash,: HASH handle.
Note:
Set the handle field SuspendRequest to the appropriate value so that the on-going HASH processing is suspended as soon as the required conditions are met. Note that the actual suspension is carried out by the functions HASH_WriteData() in polling mode and HASH_IT() in interruption mode.
Return values:
None

Definition at line 1058 of file stm32h7xx_hal_hash.c.

References HAL_HASH_SUSPEND, and HASH_HandleTypeDef::SuspendRequest.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH Exported Types

Data Structures | Enumerations
HASH Exported Types
HASH

Data Structures

struct | HASH_InitTypeDef
HASH Configuration Structure definition. More...
struct | HASH_HandleTypeDef
HASH Handle Structure definition. More...

Enumerations

enum HAL_HASH_StateTypeDef {
HAL_HASH_STATE_RESET = 0x00, HAL_HASH_STATE_READY = 0x01, HAL_HASH_STATE_BUSY = 0x02, HAL_HASH_STATE_TIMEOUT = 0x06,
HAL_HASH_STATE_ERROR = 0x07, HAL_HASH_STATE_SUSPENDED = 0x08
}
HAL State structures definition. More...
enum HAL_HASH_PhaseTypeDef {
HAL_HASH_PHASE_READY = 0x01, HAL_HASH_PHASE_PROCESS = 0x02, HAL_HASH_PHASE_HMAC_STEP_1 = 0x03, HAL_HASH_PHASE_HMAC_STEP_2 = 0x04,
HAL_HASH_PHASE_HMAC_STEP_3 = 0x05
}
HAL phase structures definition. More...
enum | HAL_HASH_SuspendTypeDef { HAL_HASH_SUSPEND_NONE = 0x00, HAL_HASH_SUSPEND = 0x01 }
HAL HASH mode suspend definitions. More...

Enumeration Type Documentation

enum HAL_HASH_PhaseTypeDef

HAL phase structures definition.

Enumerator:
HAL_HASH_PHASE_READY

HASH peripheral is ready to start

HAL_HASH_PHASE_PROCESS

HASH peripheral is in HASH processing phase

HAL_HASH_PHASE_HMAC_STEP_1

HASH peripheral is in HMAC step 1 processing phase (step 1 consists in entering the inner hash function key)

HAL_HASH_PHASE_HMAC_STEP_2

HASH peripheral is in HMAC step 2 processing phase (step 2 consists in entering the message text)

HAL_HASH_PHASE_HMAC_STEP_3

HASH peripheral is in HMAC step 3 processing phase (step 3 consists in entering the outer hash function key)

Definition at line 94 of file stm32h7xx_hal_hash.h.

enum HAL_HASH_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_HASH_STATE_RESET

Peripheral is not initialized

HAL_HASH_STATE_READY

Peripheral Initialized and ready for use

HAL_HASH_STATE_BUSY

Processing (hashing) is ongoing

HAL_HASH_STATE_TIMEOUT

Timeout state

HAL_HASH_STATE_ERROR

Error state

HAL_HASH_STATE_SUSPENDED

Suspended state

Definition at line 81 of file stm32h7xx_hal_hash.h.

enum HAL_HASH_SuspendTypeDef

HAL HASH mode suspend definitions.

Enumerator:
HAL_HASH_SUSPEND_NONE

HASH peripheral suspension not requested

HAL_HASH_SUSPEND

HASH peripheral suspension is requested

Definition at line 109 of file stm32h7xx_hal_hash.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HASH_InitTypeDef Struct Reference
HASH Exported Types

HASH Configuration Structure definition. More...

#include <stm32h7xx_hal_hash.h>

Data Fields

uint32_t | DataType
uint32_t | KeySize
uint8_t * | pKey

Detailed Description

HASH Configuration Structure definition.

Definition at line 67 of file stm32h7xx_hal_hash.h.

Field Documentation

uint32_t HASH_InitTypeDef::DataType

32-bit data, 16-bit data, 8-bit data or 1-bit data. This parameter can be a value of HASH input data type.

Definition at line 69 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_Init().

uint32_t HASH_InitTypeDef::KeySize

The key size is used only in HMAC operation.

Definition at line 72 of file stm32h7xx_hal_hash.h.

Referenced by HASH_DMAXferCplt(), HASH_IT(), HMAC_Processing(), HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

uint8_t* HASH_InitTypeDef::pKey

The key is used only in HMAC operation.

Definition at line 74 of file stm32h7xx_hal_hash.h.

Referenced by HASH_DMAXferCplt(), HASH_IT(), HMAC_Processing(), HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hash.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HASH_HandleTypeDef Struct Reference
HASH Exported Types

HASH Handle Structure definition. More...

#include <stm32h7xx_hal_hash.h>

Data Fields

HASH_InitTypeDef Init
uint8_t * | pHashInBuffPtr
uint8_t * | pHashOutBuffPtr
uint8_t * | pHashKeyBuffPtr
uint8_t * | pHashMsgBuffPtr
uint32_t | HashBuffSize
__IO uint32_t | HashInCount
__IO uint32_t | HashITCounter
__IO uint32_t | HashKeyCount
HAL_StatusTypeDef | Status
HAL_HASH_PhaseTypeDef Phase
DMA_HandleTypeDef * hdmain
HAL_LockTypeDef | Lock
__IO HAL_HASH_StateTypeDef | State
HAL_HASH_SuspendTypeDef SuspendRequest
FlagStatus | DigestCalculationDisable

Detailed Description

HASH Handle Structure definition.

Definition at line 119 of file stm32h7xx_hal_hash.h.

Field Documentation

FlagStatus HASH_HandleTypeDef::DigestCalculationDisable

Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation

Definition at line 151 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DeInit(), HAL_HASH_Init(), HAL_HMACEx_MD5_Step1_2_DMA(), HAL_HMACEx_MD5_Step2_3_DMA(), HAL_HMACEx_MD5_Step2_DMA(), HAL_HMACEx_SHA1_Step1_2_DMA(), HAL_HMACEx_SHA1_Step2_3_DMA(), HAL_HMACEx_SHA1_Step2_DMA(), HAL_HMACEx_SHA224_Step1_2_DMA(), HAL_HMACEx_SHA224_Step2_3_DMA(), HAL_HMACEx_SHA224_Step2_DMA(), HAL_HMACEx_SHA256_Step1_2_DMA(), HAL_HMACEx_SHA256_Step2_3_DMA(), HAL_HMACEx_SHA256_Step2_DMA(), HASH_DMAXferCplt(), and HMAC_Start_DMA().

uint32_t HASH_HandleTypeDef::HashBuffSize

Size of buffer to be processed

Definition at line 131 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DeInit(), HAL_HASH_Init(), HASH_DMAXferCplt(), HASH_IT(), HMAC_Processing(), HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

__IO uint32_t HASH_HandleTypeDef::HashInCount

Counter of inputted data

Definition at line 133 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DeInit(), HAL_HASH_DMAFeed_ProcessSuspend(), HAL_HASH_Init(), HASH_Accumulate(), HASH_DMAXferCplt(), HASH_IT(), HASH_Start(), HASH_Start_DMA(), HASH_Start_IT(), HASH_Write_Block_Data(), HASH_WriteData(), HMAC_Processing(), HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

__IO uint32_t HASH_HandleTypeDef::HashITCounter

Counter of issued interrupts

Definition at line 135 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DeInit(), HAL_HASH_Init(), HASH_IT(), HASH_Start_IT(), HASH_Write_Block_Data(), and HMAC_Start_IT().

__IO uint32_t HASH_HandleTypeDef::HashKeyCount

Counter for Key inputted data (HMAC only)

Definition at line 137 of file stm32h7xx_hal_hash.h.

Referenced by HASH_WriteData(), HMAC_Processing(), and HMAC_Start().

DMA_HandleTypeDef* HASH_HandleTypeDef::hdmain

HASH In DMA Handle parameters

Definition at line 143 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DMAFeed_ProcessSuspend(), HASH_DMAXferCplt(), HASH_Start_DMA(), and HMAC_Start_DMA().

HASH_InitTypeDef HASH_HandleTypeDef::Init

HASH required parameters

Definition at line 121 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_Init(), HASH_DMAXferCplt(), HASH_IT(), HMAC_Processing(), HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

HAL_LockTypeDef HASH_HandleTypeDef::Lock

Locking object

Definition at line 145 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_Init().

HAL_HASH_PhaseTypeDef HASH_HandleTypeDef::Phase

HASH peripheral phase

Definition at line 141 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DeInit(), HAL_HASH_Init(), HASH_Accumulate(), HASH_DMAXferCplt(), HASH_IT(), HASH_Start(), HASH_Start_DMA(), HASH_Start_IT(), HASH_WriteData(), HMAC_Processing(), HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

uint8_t* HASH_HandleTypeDef::pHashInBuffPtr

Pointer to input buffer

Definition at line 123 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DMAFeed_ProcessSuspend(), HASH_Accumulate(), HASH_DMAXferCplt(), HASH_IT(), HASH_Start(), HASH_Start_DMA(), HASH_Start_IT(), HASH_Write_Block_Data(), HASH_WriteData(), HMAC_Processing(), HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

uint8_t* HASH_HandleTypeDef::pHashKeyBuffPtr

Pointer to key buffer (HMAC only)

Definition at line 127 of file stm32h7xx_hal_hash.h.

Referenced by HASH_WriteData(), HMAC_Processing(), HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

uint8_t* HASH_HandleTypeDef::pHashMsgBuffPtr

Pointer to message buffer (HMAC only)

Definition at line 129 of file stm32h7xx_hal_hash.h.

Referenced by HASH_DMAXferCplt(), HASH_IT(), HMAC_Start_DMA(), and HMAC_Start_IT().

uint8_t* HASH_HandleTypeDef::pHashOutBuffPtr

Pointer to output buffer (digest)

Definition at line 125 of file stm32h7xx_hal_hash.h.

Referenced by HASH_IT(), HASH_Start_IT(), HMAC_Processing(), HMAC_Start(), and HMAC_Start_IT().

__IO HAL_HASH_StateTypeDef HASH_HandleTypeDef::State

HASH peripheral state

Definition at line 147 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DeInit(), HAL_HASH_DMAFeed_ProcessSuspend(), HAL_HASH_GetState(), HAL_HASH_Init(), HASH_Accumulate(), HASH_DMAError(), HASH_DMAXferCplt(), HASH_Finish(), HASH_IT(), HASH_Start(), HASH_Start_DMA(), HASH_Start_IT(), HASH_WaitOnFlagUntilTimeout(), HASH_WriteData(), HMAC_Processing(), HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

HAL_StatusTypeDef HASH_HandleTypeDef::Status

HASH peripheral status

Definition at line 139 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DeInit(), HAL_HASH_GetStatus(), HAL_HASH_Init(), HAL_HASH_IRQHandler(), HASH_Accumulate(), HASH_DMAError(), HASH_Start(), HASH_WaitOnFlagUntilTimeout(), and HMAC_Processing().

HAL_HASH_SuspendTypeDef HASH_HandleTypeDef::SuspendRequest

HASH peripheral suspension request flag

Definition at line 149 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_SwFeed_ProcessSuspend(), HASH_IT(), and HASH_WriteData().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hash.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH algorithm selection

Defines
HASH algorithm selection
HASH Exported Constants

Defines

#define | HASH_ALGOSELECTION_SHA1 ((uint32_t)0x0000)
#define | HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1
#define | HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO
#define | HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0

Define Documentation

#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0

HASH function is MD5

Definition at line 171 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_MD5_Accumulate(), HAL_HASH_MD5_Start(), HAL_HASH_MD5_Start_DMA(), HAL_HASH_MD5_Start_IT(), HAL_HMAC_MD5_Start(), HAL_HMAC_MD5_Start_DMA(), HAL_HMAC_MD5_Start_IT(), HAL_HMACEx_MD5_Step1_2_DMA(), HAL_HMACEx_MD5_Step2_3_DMA(), and HAL_HMACEx_MD5_Step2_DMA().

#define HASH_ALGOSELECTION_SHA1 ((uint32_t)0x0000)

HASH function is SHA1

Definition at line 168 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_SHA1_Accumulate(), HAL_HASH_SHA1_Start(), HAL_HASH_SHA1_Start_DMA(), HAL_HASH_SHA1_Start_IT(), HAL_HMAC_SHA1_Start(), HAL_HMAC_SHA1_Start_DMA(), HAL_HMAC_SHA1_Start_IT(), HAL_HMACEx_SHA1_Step1_2_DMA(), HAL_HMACEx_SHA1_Step2_3_DMA(), and HAL_HMACEx_SHA1_Step2_DMA().

#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1

HASH function is SHA224

Definition at line 169 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASHEx_SHA224_Accumulate(), HAL_HASHEx_SHA224_Start(), HAL_HASHEx_SHA224_Start_DMA(), HAL_HASHEx_SHA224_Start_IT(), HAL_HMACEx_SHA224_Start(), HAL_HMACEx_SHA224_Start_DMA(), HAL_HMACEx_SHA224_Start_IT(), HAL_HMACEx_SHA224_Step1_2_DMA(), HAL_HMACEx_SHA224_Step2_3_DMA(), and HAL_HMACEx_SHA224_Step2_DMA().

#define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO

HASH function is SHA256

Definition at line 170 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASHEx_SHA256_Accumulate(), HAL_HASHEx_SHA256_Start(), HAL_HASHEx_SHA256_Start_DMA(), HAL_HASHEx_SHA256_Start_IT(), HAL_HMACEx_SHA256_Start(), HAL_HMACEx_SHA256_Start_DMA(), HAL_HMACEx_SHA256_Start_IT(), HAL_HMACEx_SHA256_Step1_2_DMA(), HAL_HMACEx_SHA256_Step2_3_DMA(), and HAL_HMACEx_SHA256_Step2_DMA().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH algorithm mode

Defines
HASH algorithm mode
HASH Exported Constants

Defines

#define | HASH_ALGOMODE_HASH ((uint32_t)0x00000000)
#define | HASH_ALGOMODE_HMAC HASH_CR_MODE

Define Documentation

#define HASH_ALGOMODE_HASH ((uint32_t)0x00000000)

Algorithm is HASH

Definition at line 179 of file stm32h7xx_hal_hash.h.

#define HASH_ALGOMODE_HMAC HASH_CR_MODE

Algorithm is HMAC

Definition at line 180 of file stm32h7xx_hal_hash.h.

Referenced by HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH input data type

Defines
HASH input data type
HASH Exported Constants

Defines

#define | HASH_DATATYPE_32B ((uint32_t)0x0000)
#define | HASH_DATATYPE_16B HASH_CR_DATATYPE_0
#define | HASH_DATATYPE_8B HASH_CR_DATATYPE_1
#define | HASH_DATATYPE_1B HASH_CR_DATATYPE

Define Documentation

#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0

16-bit data. Each half word is swapped

Definition at line 189 of file stm32h7xx_hal_hash.h.

#define HASH_DATATYPE_1B HASH_CR_DATATYPE

1-bit data. In the word all bits are swapped

Definition at line 191 of file stm32h7xx_hal_hash.h.

#define HASH_DATATYPE_32B ((uint32_t)0x0000)

32-bit data. No swapping

Definition at line 188 of file stm32h7xx_hal_hash.h.

#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1

8-bit data. All bytes are swapped

Definition at line 190 of file stm32h7xx_hal_hash.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HMAC key length type

Defines
HMAC key length type
HASH Exported Constants

Defines

#define | HASH_HMAC_KEYTYPE_SHORTKEY ((uint32_t)0x00000000)
#define | HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY

Define Documentation

#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY

HMAC Key size is > 64 bytes

Definition at line 200 of file stm32h7xx_hal_hash.h.

Referenced by HMAC_Start(), HMAC_Start_DMA(), and HMAC_Start_IT().

#define HASH_HMAC_KEYTYPE_SHORTKEY ((uint32_t)0x00000000)

HMAC Key size is <= 64 bytes

Definition at line 199 of file stm32h7xx_hal_hash.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH flags definitions

Defines
HASH flags definitions
HASH Exported Constants

Defines

#define | HASH_FLAG_DINIS HASH_SR_DINIS
#define | HASH_FLAG_DCIS HASH_SR_DCIS
#define | HASH_FLAG_DMAS HASH_SR_DMAS
#define | HASH_FLAG_BUSY HASH_SR_BUSY
#define | HASH_FLAG_DINNE HASH_CR_DINNE

Define Documentation

#define HASH_FLAG_BUSY HASH_SR_BUSY

The hash core is Busy, processing a block of data

Definition at line 211 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DMAFeed_ProcessSuspend(), HASH_IT(), and HMAC_Processing().

#define HASH_FLAG_DCIS HASH_SR_DCIS

Digest calculation complete

Definition at line 209 of file stm32h7xx_hal_hash.h.

Referenced by HASH_Finish(), HASH_IT(), HASH_Start(), and HMAC_Processing().

#define HASH_FLAG_DINIS HASH_SR_DINIS

16 locations are free in the DIN : a new block can be entered in the IP

Definition at line 208 of file stm32h7xx_hal_hash.h.

Referenced by HASH_IT(), and HASH_WriteData().

#define HASH_FLAG_DINNE HASH_CR_DINNE

DIN not empty : the input buffer contains at least one word of data

Definition at line 212 of file stm32h7xx_hal_hash.h.

#define HASH_FLAG_DMAS HASH_SR_DMAS

DMA interface is enabled (DMAE=1) or a transfer is ongoing

Definition at line 210 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_DMAFeed_ProcessSuspend().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH interrupts definitions

Defines
HASH interrupts definitions
HASH Exported Constants

Defines

#define | HASH_IT_DINI HASH_IMR_DINIE
#define | HASH_IT_DCI HASH_IMR_DCIE

Define Documentation

#define HASH_IT_DCI HASH_IMR_DCIE

Digest calculation complete

Definition at line 222 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_ContextSaving(), HASH_IT(), HASH_Start_IT(), and HMAC_Start_IT().

#define HASH_IT_DINI HASH_IMR_DINIE

A new block can be entered into the input buffer (DIN)

Definition at line 221 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_ContextSaving(), HASH_IT(), HASH_Start_IT(), HASH_Write_Block_Data(), and HMAC_Start_IT().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH API alias

Defines
HASH API alias
HASH Exported Constants

Defines

#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler

Define Documentation

#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler

HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code

Definition at line 231 of file stm32h7xx_hal_hash.h.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH Exported Macros

Defines
HASH Exported Macros
HASH

Defines

#define | __HAL_HASH_GET_FLAG(__FLAG__)
Check whether or not the specified HASH flag is set.
#define | __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__))
Clear the specified HASH flag.
#define | __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__))
Enable the specified HASH interrupt.
#define | __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
Disable the specified HASH interrupt.
#define | __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
Reset HASH handle state.
#define | __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
Reset HASH handle status.
#define | __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT)
Enable the multi-buffer DMA transfer mode.
#define | __HAL_HASH_RESET_MDMAT() CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)
Disable the multi-buffer DMA transfer mode.
#define | __HAL_HASH_START_DIGEST() SET_BIT(HASH->STR, HASH_STR_DCAL)
Start the digest computation.
#define | __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * ((__SIZE__) % 4))
Set the number of valid bits in the last word written in data register DIN.
#define | __HAL_HASH_INIT() SET_BIT(HASH->CR, HASH_CR_INIT)
Reset the HASH core.

Define Documentation

#define __HAL_HASH_CLEAR_FLAG ( __FLAG__ ) CLEAR_BIT(HASH->SR, (__FLAG__))

Clear the specified HASH flag.

Parameters:
__FLAG__,: specifies the flag to clear. This parameter can be one of the following values:
  • HASH_FLAG_DINIS A new block can be entered into the input buffer.
  • HASH_FLAG_DCIS Digest calculation complete
Return values:
None

Definition at line 269 of file stm32h7xx_hal_hash.h.

#define __HAL_HASH_DISABLE_IT ( __INTERRUPT__ ) CLEAR_BIT(HASH->IMR, (__INTERRUPT__))

Disable the specified HASH interrupt.

Parameters:
__INTERRUPT__,: specifies the HASH interrupt source to disable. This parameter can be one of the following values:
  • HASH_IT_DINI A new block can be entered into the input buffer (DIN)
  • HASH_IT_DCI Digest calculation complete
Return values:
None

Definition at line 288 of file stm32h7xx_hal_hash.h.

Referenced by HASH_IT(), and HASH_Write_Block_Data().

#define __HAL_HASH_ENABLE_IT ( __INTERRUPT__ ) SET_BIT(HASH->IMR, (__INTERRUPT__))

Enable the specified HASH interrupt.

Parameters:
__INTERRUPT__,: specifies the HASH interrupt source to enable. This parameter can be one of the following values:
  • HASH_IT_DINI A new block can be entered into the input buffer (DIN)
  • HASH_IT_DCI Digest calculation complete
Return values:
None

Definition at line 279 of file stm32h7xx_hal_hash.h.

Referenced by HASH_IT(), HASH_Start_IT(), and HMAC_Start_IT().

#define __HAL_HASH_GET_FLAG ( __FLAG__ )
Value:
(((__FLAG__) > 8U)  ?                    \
                                       ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
                                       ((HASH->SR & (__FLAG__)) == (__FLAG__)) )

Check whether or not the specified HASH flag is set.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • HASH_FLAG_DINIS A new block can be entered into the input buffer.
  • HASH_FLAG_DCIS Digest calculation complete.
  • HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
  • HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
  • HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 257 of file stm32h7xx_hal_hash.h.

Referenced by HASH_IT(), HASH_WaitOnFlagUntilTimeout(), and HASH_WriteData().

#define __HAL_HASH_INIT ( ) SET_BIT(HASH->CR, HASH_CR_INIT)

Reset the HASH core.

Return values:
None

Definition at line 334 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_ContextRestoring().

#define __HAL_HASH_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)

Reset HASH handle state.

Parameters:
__HANDLE__,: HASH handle.
Return values:
None

Definition at line 294 of file stm32h7xx_hal_hash.h.

#define __HAL_HASH_RESET_HANDLE_STATUS ( __HANDLE__ ) ((__HANDLE__)->Status = HAL_OK)

Reset HASH handle status.

Parameters:
__HANDLE__,: HASH handle.
Return values:
None

Definition at line 300 of file stm32h7xx_hal_hash.h.

#define __HAL_HASH_RESET_MDMAT ( ) CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)

Disable the multi-buffer DMA transfer mode.

Return values:
None

Definition at line 313 of file stm32h7xx_hal_hash.h.

Referenced by HMAC_Start_DMA().

#define __HAL_HASH_SET_MDMAT ( ) SET_BIT(HASH->CR, HASH_CR_MDMAT)

Enable the multi-buffer DMA transfer mode.

Note:
This bit is set when hashing large files when multiple DMA transfers are needed.
Return values:
None

Definition at line 307 of file stm32h7xx_hal_hash.h.

Referenced by HASH_DMAXferCplt().

#define __HAL_HASH_SET_NBVALIDBITS ( __SIZE__ ) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * ((__SIZE__) % 4))

Set the number of valid bits in the last word written in data register DIN.

Parameters:
__SIZE__,: size in bytes of last data written in Data register.
Return values:
None

Definition at line 328 of file stm32h7xx_hal_hash.h.

Referenced by HASH_DMAXferCplt(), HASH_IT(), HASH_Start(), HASH_Start_DMA(), HASH_Start_IT(), HMAC_Processing(), HMAC_Start_DMA(), and HMAC_Start_IT().

#define __HAL_HASH_START_DIGEST ( ) SET_BIT(HASH->STR, HASH_STR_DCAL)

Start the digest computation.

Return values:
None

Definition at line 321 of file stm32h7xx_hal_hash.h.

Referenced by HASH_Start(), HASH_Write_Block_Data(), and HMAC_Processing().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH Private Macros

Defines
HASH Private Macros
HASH

Defines

#define | HASH_DIGEST_LENGTH()
Return digest length in bytes.
#define | HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8)
Return number of words already pushed in the FIFO.
#define | IS_HASH_DATATYPE(__DATATYPE__)
Ensure that HASH input data type is valid.
#define | IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4) == 0)
Ensure that input data buffer size is valid for multi-buffer HASH processing in polling mode.
#define | IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == RESET) || (((__SIZE__) % 4) == 0))
Ensure that input data buffer size is valid for multi-buffer HASH processing in DMA mode.
#define | IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__, __SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4) == 0))
Ensure that input data buffer size is valid for multi-buffer HMAC processing in DMA mode.
#define | IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
Ensure that handle phase is set to HASH processing.
#define | IS_HMAC_PROCESSING(__HANDLE__)
Ensure that handle phase is set to HMAC processing.

Define Documentation

#define HASH_DIGEST_LENGTH ( )
Value:
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1)   ?  20 : \
                             ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ?  28 : \
                             ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ?  32 : 16 ) ) )

Return digest length in bytes.

Return values:
Digest length

Definition at line 350 of file stm32h7xx_hal_hash.h.

Referenced by HASH_Finish(), HASH_IT(), HASH_Start(), and HMAC_Processing().

#define HASH_NBW_PUSHED ( ) ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8)

Return number of words already pushed in the FIFO.

Return values:
Number of words already pushed in the FIFO

Definition at line 358 of file stm32h7xx_hal_hash.h.

#define IS_HASH_DATATYPE ( __DATATYPE__ )
Value:
(((__DATATYPE__) == HASH_DATATYPE_32B)|| \
                                        ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
                                        ((__DATATYPE__) == HASH_DATATYPE_8B) || \
                                        ((__DATATYPE__) == HASH_DATATYPE_1B))

Ensure that HASH input data type is valid.

Parameters:
__DATATYPE__,: HASH input data type.
Return values:
SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)

Definition at line 365 of file stm32h7xx_hal_hash.h.

Referenced by HAL_HASH_Init().

#define IS_HASH_DMA_MULTIBUFFER_SIZE ( __SIZE__ ) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == RESET) || (((__SIZE__) % 4) == 0))

Ensure that input data buffer size is valid for multi-buffer HASH processing in DMA mode.

Note:
This check is valid only for multi-buffer HASH processing in DMA mode.
Parameters:
__SIZE__,: input data buffer size.
Return values:
SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)

Definition at line 388 of file stm32h7xx_hal_hash.h.

Referenced by HASH_Start_DMA().

#define IS_HASH_POLLING_MULTIBUFFER_SIZE ( __SIZE__ ) (((__SIZE__) % 4) == 0)

Ensure that input data buffer size is valid for multi-buffer HASH processing in polling mode.

Note:
This check is valid only for multi-buffer HASH processing in polling mode.
Parameters:
__SIZE__,: input data buffer size.
Return values:
SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)

Definition at line 379 of file stm32h7xx_hal_hash.h.

Referenced by HASH_Accumulate().

#define IS_HASH_PROCESSING ( __HANDLE__ ) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)

Ensure that handle phase is set to HASH processing.

Parameters:
__HANDLE__,: HASH handle.
Return values:
SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)

Definition at line 405 of file stm32h7xx_hal_hash.h.

Referenced by HASH_Start_DMA().

#define IS_HMAC_DMA_MULTIBUFFER_SIZE | ( | __HANDLE__,
 |  | __SIZE__
 | ) | ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4) == 0))

Ensure that input data buffer size is valid for multi-buffer HMAC processing in DMA mode.

Note:
This check is valid only for multi-buffer HMAC processing in DMA mode.
Parameters:
__HANDLE__,: HASH handle.
__SIZE__,: input data buffer size.
Return values:
SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)

Definition at line 398 of file stm32h7xx_hal_hash.h.

Referenced by HMAC_Start_DMA().

#define IS_HMAC_PROCESSING ( __HANDLE__ )
Value:
(((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
                                         ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \
                                         ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3))

Ensure that handle phase is set to HMAC processing.

Parameters:
__HANDLE__,: HASH handle.
Return values:
SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)

Definition at line 412 of file stm32h7xx_hal_hash.h.

Referenced by HMAC_Start_DMA().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH extended processing functions in polling mode

Functions
HASH extended processing functions in polling mode
HASH Extended Exported Functions

HASH extended processing functions using polling mode. More...

Functions

HAL_StatusTypeDef | HAL_HASHEx_SHA224_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASHEx_SHA224_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in SHA224 mode then processes pInBuffer.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in SHA256 mode then processes pInBuffer.

Detailed Description

HASH extended processing functions using polling mode.

 ===============================================================================
               ##### Polling mode HASH extended processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in polling mode
          the hash value using one of the following algorithms:
      (+) SHA224
         (++) HAL_HASHEx_SHA224_Start()
         (++) HAL_HASHEx_SHA224_Accumulate()
      (+) SHA256
         (++) HAL_HASHEx_SHA256_Start()
         (++) HAL_HASHEx_SHA256_Accumulate()

    [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().

    [..]  In case of multi-buffer HASH processing (a single digest is computed while
          several buffers are fed to the IP), the user can resort to successive calls
          to HAL_HASHEx_xxx_Accumulate() and wrap-up the digest computation by a call
          to HAL_HASHEx_xxx_Start().

Function Documentation

HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

If not already done, initialize the HASH peripheral in SHA224 mode then processes pInBuffer.

Note:
Consecutive calls to HAL_HASHEx_SHA224_Accumulate() can be used to feed several input buffers back-to-back to the IP that will yield a single HASH signature once all buffers have been entered. Wrap-up of input buffers feeding and retrieval of digest is done by a call to HAL_HASHEx_SHA224_Start().
Field hhash->Phase of HASH handle is tested to check whether or not the IP has already been initialized.
Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Start() to read it, feeding at the same time the last input buffer to the IP.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Start() is able to manage the ending buffer with a length in bytes not a multiple of 4.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes, must be a multiple of 4.
Return values:
HAL status

Definition at line 186 of file stm32h7xx_hal_hash_ex.c.

References HASH_Accumulate(), and HASH_ALGOSELECTION_SHA224.

HAL_StatusTypeDef HAL_HASHEx_SHA224_Start | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then read the computed digest.

Note:
Digest is available in pOutBuffer.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 28 bytes.
Timeout,: Timeout value
Return values:
HAL status

Definition at line 161 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA224, and HASH_Start().

HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

If not already done, initialize the HASH peripheral in SHA256 mode then processes pInBuffer.

Note:
Consecutive calls to HAL_HASHEx_SHA256_Accumulate() can be used to feed several input buffers back-to-back to the IP that will yield a single HASH signature once all buffers have been entered. Wrap-up of input buffers feeding and retrieval of digest is done by a call to HAL_HASHEx_SHA256_Start().
Field hhash->Phase of HASH handle is tested to check whether or not the IP has already been initialized.
Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Start() to read it, feeding at the same time the last input buffer to the IP.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Start() is able to manage the ending buffer with a length in bytes not a multiple of 4.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes, must be a multiple of 4.
Return values:
HAL status

Definition at line 227 of file stm32h7xx_hal_hash_ex.c.

References HASH_Accumulate(), and HASH_ALGOSELECTION_SHA256.

HAL_StatusTypeDef HAL_HASHEx_SHA256_Start | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then read the computed digest.

Note:
Digest is available in pOutBuffer.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 32 bytes.
Timeout,: Timeout value
Return values:
HAL status

Definition at line 202 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA256, and HASH_Start().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH extended processing functions in interrupt mode

Functions
HASH extended processing functions in interrupt mode
HASH Extended Exported Functions

HASH extended processing functions using interrupt mode. More...

Functions

HAL_StatusTypeDef | HAL_HASHEx_SHA224_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then read the computed digest in interruption mode.

Detailed Description

HASH extended processing functions using interrupt mode.

 ===============================================================================
          ##### Interruption mode HASH extended processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in interrupt mode
          the hash value using one of the following algorithms:
      (+) SHA224
         (++) HAL_HASHEx_SHA224_Start_IT()
      (+) SHA256
         (++) HAL_HASHEx_SHA256_Start_IT()

Function Documentation

HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer
 | ) |  |

Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then read the computed digest in interruption mode.

Note:
Digest is available in pOutBuffer.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 28 bytes.
Return values:
HAL status

Definition at line 266 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA224, and HASH_Start_IT().

HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer
 | ) |  |

Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then read the computed digest in interruption mode.

Note:
Digest is available in pOutBuffer.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 32 bytes.
Return values:
HAL status

Definition at line 281 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA256, and HASH_Start_IT().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH extended processing functions in DMA mode

Functions
HASH extended processing functions in DMA mode
HASH Extended Exported Functions

HASH extended processing functions using DMA mode. More...

Functions

HAL_StatusTypeDef | HAL_HASHEx_SHA224_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASHEx_SHA224_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in SHA224 mode.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in SHA256 mode.

Detailed Description

HASH extended processing functions using DMA mode.

 ===============================================================================
                ##### DMA mode HASH extended  processing functionss #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in DMA mode
          the hash value using one of the following algorithms:
      (+) SHA224
         (++) HAL_HASHEx_SHA224_Start_DMA()
         (++) HAL_HASHEx_SHA224_Finish()
      (+) SHA256
         (++) HAL_HASHEx_SHA256_Start_DMA()
         (++) HAL_HASHEx_SHA256_Finish()

    [..]  When resorting to DMA mode to enter the data in the IP, user must resort
          to  HAL_HASHEx_xxx_Start_DMA() then read the resulting digest with
          HAL_HASHEx_xxx_Finish().

    [..]  In case of multi-buffer HASH processing, MDMAT bit must first be set before
          the successive calls to HAL_HASHEx_xxx_Start_DMA(). Then, MDMAT bit needs to be
          reset before the last call to HAL_HASHEx_xxx_Start_DMA(). Digest is finally
          retrieved thanks to HAL_HASHEx_xxx_Finish().

Function Documentation

HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Return the computed digest in SHA224 mode.

Note:
The API waits for DCIS to be set then reads the computed digest.
HAL_HASHEx_SHA224_Finish() can be used as well to retrieve the digest in HMAC SHA224 mode.
Parameters:
hhash,: HASH handle.
pOutBuffer,: pointer to the computed digest. Digest size is 28 bytes.
Timeout,: Timeout value.
Return values:
HAL status

Definition at line 347 of file stm32h7xx_hal_hash_ex.c.

References HASH_Finish().

HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer to feed the input buffer to the IP.

Note:
Once the DMA transfer is finished, HAL_HASHEx_SHA224_Finish() API must be called to retrieve the computed digest.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 332 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA224, and HASH_Start_DMA().

HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Return the computed digest in SHA256 mode.

Note:
The API waits for DCIS to be set then reads the computed digest.
HAL_HASHEx_SHA256_Finish() can be used as well to retrieve the digest in HMAC SHA256 mode.
Parameters:
hhash,: HASH handle.
pOutBuffer,: pointer to the computed digest. Digest size is 32 bytes.
Timeout,: Timeout value.
Return values:
HAL status

Definition at line 377 of file stm32h7xx_hal_hash_ex.c.

References HASH_Finish().

HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer to feed the input buffer to the IP.

Note:
Once the DMA transfer is finished, HAL_HASHEx_SHA256_Finish() API must be called to retrieve the computed digest.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 362 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA256, and HASH_Start_DMA().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HMAC extended processing functions in polling mode

Functions
HMAC extended processing functions in polling mode
HASH Extended Exported Functions

HMAC extended processing functions using polling mode. More...

Functions

HAL_StatusTypeDef | HAL_HMACEx_SHA224_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then read the computed digest.

Detailed Description

HMAC extended processing functions using polling mode.

 ===============================================================================
             ##### Polling mode HMAC extended processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in polling mode
          the HMAC value using one of the following algorithms:
      (+) SHA224
         (++) HAL_HMACEx_SHA224_Start()
      (+) SHA256
         (++) HAL_HMACEx_SHA256_Start()

Function Documentation

HAL_StatusTypeDef HAL_HMACEx_SHA224_Start | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then read the computed digest.

Note:
Digest is available in pOutBuffer.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 28 bytes.
Timeout,: Timeout value.
Return values:
HAL status

Definition at line 419 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA224, and HMAC_Start().

HAL_StatusTypeDef HAL_HMACEx_SHA256_Start | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer,
 |  | uint32_t | Timeout
 | ) |  |

Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then read the computed digest.

Note:
Digest is available in pOutBuffer.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 32 bytes.
Timeout,: Timeout value.
Return values:
HAL status

Definition at line 437 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA256, and HMAC_Start().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HMAC extended processing functions in interrupt mode

Functions
HMAC extended processing functions in interrupt mode
HASH Extended Exported Functions

HMAC extended processing functions using interruption mode. More...

Functions

HAL_StatusTypeDef | HAL_HMACEx_SHA224_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then read the computed digest in interrupt mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then read the computed digest in interrupt mode.

Detailed Description

HMAC extended processing functions using interruption mode.

 ===============================================================================
             ##### Interrupt mode HMAC extended processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in interrupt mode
          the HMAC value using one of the following algorithms:
      (+) SHA224
         (++) HAL_HMACEx_SHA224_Start_IT()
      (+) SHA256
         (++) HAL_HMACEx_SHA256_Start_IT()

Function Documentation

HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer
 | ) |  |

Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then read the computed digest in interrupt mode.

Note:
Digest is available in pOutBuffer.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 28 bytes.
Return values:
HAL status

Definition at line 479 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA224, and HMAC_Start_IT().

HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size,
 |  | uint8_t * | pOutBuffer
 | ) |  |

Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then read the computed digest in interrupt mode.

Note:
Digest is available in pOutBuffer.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
pOutBuffer,: pointer to the computed digest. Digest size is 32 bytes.
Return values:
HAL status

Definition at line 496 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA256, and HMAC_Start_IT().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HMAC extended processing functions in DMA mode

Functions
HMAC extended processing functions in DMA mode
HASH Extended Exported Functions

HMAC extended processing functions using DMA mode. More...

Functions

HAL_StatusTypeDef | HAL_HMACEx_SHA224_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.

Detailed Description

HMAC extended processing functions using DMA mode.

 ===============================================================================
              ##### DMA mode HMAC extended processing functions #####
 ===============================================================================
    [..]  This section provides functions allowing to calculate in DMA mode
          the HMAC value using one of the following algorithms:
      (+) SHA224
         (++) HAL_HMACEx_SHA224_Start_DMA()
      (+) SHA256
         (++) HAL_HMACEx_SHA256_Start_DMA()

    [..]  When resorting to DMA mode to enter the data in the IP for HMAC processing,
          user must resort to  HAL_HMACEx_xxx_Start_DMA() then read the resulting digest
          with HAL_HASHEx_xxx_Finish().

Function Documentation

HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.

Note:
Once the DMA transfers are finished (indicated by hhash->State set back to HAL_HASH_STATE_READY), HAL_HASHEx_SHA224_Finish() API must be called to retrieve the computed digest.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
If MDMAT bit is set before calling this function (multi-buffer HASH processing case), the input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted. For the processing of the last buffer of the thread, MDMAT bit must be reset and the buffer length (in bytes) doesn't have to be a multiple of 4.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 553 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA224, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.

Note:
Once the DMA transfers are finished (indicated by hhash->State set back to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve the computed digest.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
If MDMAT bit is set before calling this function (multi-buffer HASH processing case), the input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted. For the processing of the last buffer of the thread, MDMAT bit must be reset and the buffer length (in bytes) doesn't have to be a multiple of 4.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (buffer to be hashed).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 577 of file stm32h7xx_hal_hash_ex.c.

References HASH_ALGOSELECTION_SHA256, and HMAC_Start_DMA().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Multi-buffer HMAC extended processing functions in DMA mode

Functions
Multi-buffer HMAC extended processing functions in DMA mode
HASH Extended Exported Functions

HMAC extended processing functions in multi-buffer DMA mode. More...

Functions

HAL_StatusTypeDef | HAL_HMACEx_MD5_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_MD5_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
MD5 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_MD5_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA1_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA1_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA1 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA1_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA224 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA256 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.

Detailed Description

HMAC extended processing functions in multi-buffer DMA mode.

 ===============================================================================
      ##### Multi-buffer DMA mode HMAC extended processing functions #####
 ===============================================================================
    [..]  This section provides functions to manage HMAC multi-buffer
          DMA-based processing for MD5, SHA1, SHA224 and SHA256 algorithms.
      (+) MD5
         (++) HAL_HMACEx_MD5_Step1_2_DMA()
         (++) HAL_HMACEx_MD5_Step2_DMA()
         (++) HAL_HMACEx_MD5_Step2_3_DMA()
      (+) SHA1
         (++) HAL_HMACEx_SHA1_Step1_2_DMA()
         (++) HAL_HMACEx_SHA1_Step2_DMA()
         (++) HAL_HMACEx_SHA1_Step2_3_DMA()
      (+) SHA256
         (++) HAL_HMACEx_SHA224_Step1_2_DMA()
         (++) HAL_HMACEx_SHA224_Step2_DMA()
         (++) HAL_HMACEx_SHA224_Step2_3_DMA()
      (+) SHA256
         (++) HAL_HMACEx_SHA256_Step1_2_DMA()
         (++) HAL_HMACEx_SHA256_Step2_DMA()
         (++) HAL_HMACEx_SHA256_Step2_3_DMA()

    [..]  User must first start-up the multi-buffer DMA-based HMAC computation in
          calling HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
          intiates step 2 with the first input buffer.

    [..]  The following buffers are next fed to the IP with a call to the API
          HAL_HMACEx_xxx_Step2_DMA(). There may be several consecutive calls
          to this API.

    [..]  Multi-buffer DMA-based HMAC computation is wrapped up by a call to
          HAL_HMACEx_xxx_Step2_3_DMA(). This finishes step 2 in feeding the last input
          buffer to the IP then carries out step 3.

    [..]  Digest is retrieved by a call to HAL_HASH_xxx_Finish() for MD-5 or
          SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 or SHA-256.

    [..]  If only two buffers need to be consecutively processed, a call to
          HAL_HMACEx_xxx_Step1_2_DMA() followed by a call to HAL_HMACEx_xxx_Step2_3_DMA()
          is sufficient.

Function Documentation

HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.

Note:
Step 1 consists in writing the inner hash function key in the IP, step 2 consists in writing the message text.
The API carries out the HMAC step 1 then starts step 2 with the first buffer entered to the IP. DCAL bit is not automatically set after the message buffer feeding, allowing other messages DMA transfers to occur.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 652 of file stm32h7xx_hal_hash_ex.c.

References HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_MD5, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.

Note:
Step 2 consists in writing the message text in the IP, step 3 consists in writing the outer hash function key.
The API wraps up the HMAC step 2 in processing the buffer entered as input parameter (the input buffer must be the last one of the multi-buffer thread) then carries out HMAC step 3.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Once the DMA transfers are finished (indicated by hhash->State set back to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve the computed digest.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 699 of file stm32h7xx_hal_hash_ex.c.

References HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_MD5, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

MD5 HMAC step 2 in multi-buffer DMA mode.

Note:
Step 2 consists in writing the message text in the IP.
The API carries on the HMAC step 2, applied to the buffer entered as input parameter. DCAL bit is not automatically set after the message buffer feeding, allowing other messages DMA transfers to occur.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 673 of file stm32h7xx_hal_hash_ex.c.

References HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_MD5, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.

Note:
Step 1 consists in writing the inner hash function key in the IP, step 2 consists in writing the message text.
The API carries out the HMAC step 1 then starts step 2 with the first buffer entered to the IP. DCAL bit is not automatically set after the message buffer feeding, allowing other messages DMA transfers to occur.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 722 of file stm32h7xx_hal_hash_ex.c.

References HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_SHA1, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.

Note:
Step 2 consists in writing the message text in the IP, step 3 consists in writing the outer hash function key.
The API wraps up the HMAC step 2 in processing the buffer entered as input parameter (the input buffer must be the last one of the multi-buffer thread) then carries out HMAC step 3.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Once the DMA transfers are finished (indicated by hhash->State set back to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve the computed digest.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 769 of file stm32h7xx_hal_hash_ex.c.

References HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_SHA1, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

SHA1 HMAC step 2 in multi-buffer DMA mode.

Note:
Step 2 consists in writing the message text in the IP.
The API carries on the HMAC step 2, applied to the buffer entered as input parameter. DCAL bit is not automatically set after the message buffer feeding, allowing other messages DMA transfers to occur.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 743 of file stm32h7xx_hal_hash_ex.c.

References HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_SHA1, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.

Note:
Step 1 consists in writing the inner hash function key in the IP, step 2 consists in writing the message text.
The API carries out the HMAC step 1 then starts step 2 with the first buffer entered to the IP. DCAL bit is not automatically set after the message buffer feeding, allowing other messages DMA transfers to occur.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 791 of file stm32h7xx_hal_hash_ex.c.

References HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_SHA224, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.

Note:
Step 2 consists in writing the message text in the IP, step 3 consists in writing the outer hash function key.
The API wraps up the HMAC step 2 in processing the buffer entered as input parameter (the input buffer must be the last one of the multi-buffer thread) then carries out HMAC step 3.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Once the DMA transfers are finished (indicated by hhash->State set back to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve the computed digest.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 838 of file stm32h7xx_hal_hash_ex.c.

References HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_SHA224, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

SHA224 HMAC step 2 in multi-buffer DMA mode.

Note:
Step 2 consists in writing the message text in the IP.
The API carries on the HMAC step 2, applied to the buffer entered as input parameter. DCAL bit is not automatically set after the message buffer feeding, allowing other messages DMA transfers to occur.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 812 of file stm32h7xx_hal_hash_ex.c.

References HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_SHA224, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.

Note:
Step 1 consists in writing the inner hash function key in the IP, step 2 consists in writing the message text.
The API carries out the HMAC step 1 then starts step 2 with the first buffer entered to the IP. DCAL bit is not automatically set after the message buffer feeding, allowing other messages DMA transfers to occur.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 860 of file stm32h7xx_hal_hash_ex.c.

References HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_SHA256, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.

Note:
Step 2 consists in writing the message text in the IP, step 3 consists in writing the outer hash function key.
The API wraps up the HMAC step 2 in processing the buffer entered as input parameter (the input buffer must be the last one of the multi-buffer thread) then carries out HMAC step 3.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
Once the DMA transfers are finished (indicated by hhash->State set back to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve the computed digest.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 907 of file stm32h7xx_hal_hash_ex.c.

References HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_SHA256, and HMAC_Start_DMA().

HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA | ( | HASH_HandleTypeDef * | hhash,
 |  | uint8_t * | pInBuffer,
 |  | uint32_t | Size
 | ) |  |

SHA256 HMAC step 2 in multi-buffer DMA mode.

Note:
Step 2 consists in writing the message text in the IP.
The API carries on the HMAC step 2, applied to the buffer entered as input parameter. DCAL bit is not automatically set after the message buffer feeding, allowing other messages DMA transfers to occur.
Same key is used for the inner and the outer hash functions; pointer to key and key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
The input buffer size (in bytes) must be a multiple of 4 otherwise, the HASH digest computation is corrupted.
Parameters:
hhash,: HASH handle.
pInBuffer,: pointer to the input buffer (message buffer).
Size,: length of the input buffer in bytes.
Return values:
HAL status

Definition at line 881 of file stm32h7xx_hal_hash_ex.c.

References HASH_HandleTypeDef::DigestCalculationDisable, HASH_ALGOSELECTION_SHA256, and HMAC_Start_DMA().

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Private Define

Defines
HRTIM Private Define
HRTIM

Defines

#define | HRTIM_FLTR_FLTxEN
#define | HRTIM_TIMCR_TIMUPDATETRIGGER

Define Documentation

#define HRTIM_FLTR_FLTxEN
Value:
(HRTIM_FLTR_FLT1EN |\
                           HRTIM_FLTR_FLT2EN |\
                           HRTIM_FLTR_FLT3EN |\
                           HRTIM_FLTR_FLT4EN | \
                           HRTIM_FLTR_FLT5EN)

Definition at line 321 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_TimingUnitWaveform_Config().

#define HRTIM_TIMCR_TIMUPDATETRIGGER
Value:
(HRTIM_TIMUPDATETRIGGER_MASTER  |\
                                      HRTIM_TIMUPDATETRIGGER_TIMER_A |\
                                      HRTIM_TIMUPDATETRIGGER_TIMER_B |\
                                      HRTIM_TIMUPDATETRIGGER_TIMER_C |\
                                      HRTIM_TIMUPDATETRIGGER_TIMER_D |\
                                      HRTIM_TIMUPDATETRIGGER_TIMER_E)

Definition at line 327 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_TimingUnitWaveform_Config().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Private Variables

Variables
HRTIM Private Variables
HRTIM

Variables

static uint32_t TimerIdxToTimerId []

Variable Documentation

uint32_t TimerIdxToTimerId[] [static]
Initial value:

{
  HRTIM_TIMERID_TIMER_A,
  HRTIM_TIMERID_TIMER_B,
  HRTIM_TIMERID_TIMER_C,
  HRTIM_TIMERID_TIMER_D,
  HRTIM_TIMERID_TIMER_E,
  HRTIM_TIMERID_MASTER,
}

Definition at line 342 of file stm32h7xx_hal_hrtim.c.

Referenced by HAL_HRTIM_SimpleBaseStart(), HAL_HRTIM_SimpleBaseStart_DMA(), HAL_HRTIM_SimpleBaseStart_IT(), HAL_HRTIM_SimpleBaseStop(), HAL_HRTIM_SimpleBaseStop_DMA(), HAL_HRTIM_SimpleBaseStop_IT(), HAL_HRTIM_SimpleCaptureStart(), HAL_HRTIM_SimpleCaptureStart_DMA(), HAL_HRTIM_SimpleCaptureStart_IT(), HAL_HRTIM_SimpleCaptureStop(), HAL_HRTIM_SimpleCaptureStop_DMA(), HAL_HRTIM_SimpleCaptureStop_IT(), HAL_HRTIM_SimpleOCStart(), HAL_HRTIM_SimpleOCStart_DMA(), HAL_HRTIM_SimpleOCStart_IT(), HAL_HRTIM_SimpleOCStop(), HAL_HRTIM_SimpleOCStop_DMA(), HAL_HRTIM_SimpleOCStop_IT(), HAL_HRTIM_SimpleOnePulseStart(), HAL_HRTIM_SimpleOnePulseStart_IT(), HAL_HRTIM_SimpleOnePulseStop(), HAL_HRTIM_SimpleOnePulseStop_IT(), HAL_HRTIM_SimplePWMStart(), HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_SimplePWMStart_IT(), HAL_HRTIM_SimplePWMStop(), HAL_HRTIM_SimplePWMStop_DMA(), HAL_HRTIM_SimplePWMStop_IT(), HAL_HRTIM_WaveformCounterStart_DMA(), HAL_HRTIM_WaveformCounterStart_IT(), HAL_HRTIM_WaveformCounterStop_DMA(), and HAL_HRTIM_WaveformCounterStop_IT().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Private Functions

Functions
HRTIM Private Functions
HRTIM

Functions

static void | HRTIM_MasterBase_Config (HRTIM_HandleTypeDef *hhrtim, HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg)
Configures the master timer time base.
static void | HRTIM_TimingUnitBase_Config (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg)
Configures timing unit (timer A to timer E) time base.
static void | HRTIM_MasterWaveform_Config (HRTIM_HandleTypeDef *hhrtim, HRTIM_TimerCfgTypeDef *pTimerCfg)
Configures the master timer in waveform mode.
static void | HRTIM_TimingUnitWaveform_Config (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, HRTIM_TimerCfgTypeDef *pTimerCfg)
Configures timing unit (timer A to timer E) in waveform mode.
static void | HRTIM_CompareUnitConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CompareUnit, HRTIM_CompareCfgTypeDef *pCompareCfg)
Configures a compare unit.
static void | HRTIM_CaptureUnitConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, uint32_t Event)
Configures a capture unit.
static void | HRTIM_OutputConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, HRTIM_OutputCfgTypeDef *pOutputCfg)
Configures the output of a timing unit.
static void | HRTIM_EventConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t Event, HRTIM_EventCfgTypeDef *pEventCfg)
Configures an external event channel.
static void | HRTIM_TIM_ResetConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event)
Configures the timer counter reset.
static uint32_t | HRTIM_GetITFromOCMode (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel)
Returns the interrupt to enable or disable according to the OC mode.
static uint32_t | HRTIM_GetDMAFromOCMode (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel)
Returns the DMA request to enable or disable according to the OC mode.
static DMA_HandleTypeDef * | HRTIM_GetDMAHandleFromTimerIdx (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
static uint32_t | GetTimerIdxFromDMAHandle (DMA_HandleTypeDef *hdma)
static void | HRTIM_ForceRegistersUpdate (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Forces an immediate transfer from the preload to the active registers.
static void | HRTIM_HRTIM_ISR (HRTIM_HandleTypeDef *hhrtim)
HRTIM interrupts service routine.
static void | HRTIM_Master_ISR (HRTIM_HandleTypeDef *hhrtim)
Master timer interrupts service routine.
static void | HRTIM_Timer_ISR (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Timer interrupts service routine.
static void | HRTIM_DMAMasterCplt (DMA_HandleTypeDef *hdma)
DMA callback invoked upon master timer related DMA request completion.
static void | HRTIM_DMATimerxCplt (DMA_HandleTypeDef *hdma)
DMA callback invoked upon timer A..E related DMA request completion.
static void | HRTIM_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
static void | HRTIM_BurstDMACplt (DMA_HandleTypeDef *hdma)
DMA callback invoked upon burst DMA transfer completion.

Function Documentation

static uint32_t GetTimerIdxFromDMAHandle ( DMA_HandleTypeDef * hdma ) [static]

Definition at line 7242 of file stm32h7xx_hal_hrtim.c.

References DMA_REQUEST_HRTIM_MASTER, DMA_REQUEST_HRTIM_TIMER_A, DMA_REQUEST_HRTIM_TIMER_B, DMA_REQUEST_HRTIM_TIMER_C, DMA_REQUEST_HRTIM_TIMER_D, DMA_REQUEST_HRTIM_TIMER_E, HRTIM_TIMERINDEX_MASTER, HRTIM_TIMERINDEX_TIMER_A, HRTIM_TIMERINDEX_TIMER_B, HRTIM_TIMERINDEX_TIMER_C, HRTIM_TIMERINDEX_TIMER_D, HRTIM_TIMERINDEX_TIMER_E, __DMA_HandleTypeDef::Init, and DMA_InitTypeDef::Request.

Referenced by HRTIM_BurstDMACplt(), and HRTIM_DMATimerxCplt().

static void HRTIM_BurstDMACplt ( DMA_HandleTypeDef * hdma ) [static]

DMA callback invoked upon burst DMA transfer completion.

Parameters:
hdma,: pointer to DMA handle.
Return values:
None

Definition at line 7815 of file stm32h7xx_hal_hrtim.c.

References GetTimerIdxFromDMAHandle(), and HAL_HRTIM_BurstDMATransferCallback().

Referenced by HAL_HRTIM_BurstDMATransfer().

static void HRTIM_CaptureUnitConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | CaptureUnit,
 |  | uint32_t | Event
 | ) |  | [static]

Configures a capture unit.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index
CaptureUnit,: Capture unit identifier
Event,: Event reference
Return values:
None

Definition at line 6622 of file stm32h7xx_hal_hrtim.c.

References HRTIM_TimerParamTypeDef::CaptureTrigger1, HRTIM_TimerParamTypeDef::CaptureTrigger2, HRTIM_CAPTURETRIGGER_EEV_1, HRTIM_CAPTURETRIGGER_EEV_10, HRTIM_CAPTURETRIGGER_EEV_2, HRTIM_CAPTURETRIGGER_EEV_3, HRTIM_CAPTURETRIGGER_EEV_4, HRTIM_CAPTURETRIGGER_EEV_5, HRTIM_CAPTURETRIGGER_EEV_6, HRTIM_CAPTURETRIGGER_EEV_7, HRTIM_CAPTURETRIGGER_EEV_8, HRTIM_CAPTURETRIGGER_EEV_9, HRTIM_CAPTUREUNIT_1, HRTIM_CAPTUREUNIT_2, HRTIM_EVENT_1, HRTIM_EVENT_10, HRTIM_EVENT_2, HRTIM_EVENT_3, HRTIM_EVENT_4, HRTIM_EVENT_5, HRTIM_EVENT_6, HRTIM_EVENT_7, HRTIM_EVENT_8, HRTIM_EVENT_9, and __HRTIM_HandleTypeDef::TimerParam.

Referenced by HAL_HRTIM_SimpleCaptureChannelConfig().

static void HRTIM_CompareUnitConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | CompareUnit,
 |  | HRTIM_CompareCfgTypeDef * | pCompareCfg
 | ) |  | [static]

Configures a compare unit.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index
CompareUnit,: Compare unit identifier
pCompareCfg,: pointer to the compare unit configuration data structure
Return values:
None

Definition at line 6553 of file stm32h7xx_hal_hrtim.c.

References HRTIM_CompareCfgTypeDef::CompareValue, HRTIM_COMPAREUNIT_1, HRTIM_COMPAREUNIT_2, HRTIM_COMPAREUNIT_3, HRTIM_COMPAREUNIT_4, HRTIM_TIMERINDEX_MASTER, and __HRTIM_HandleTypeDef::Instance.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), and HAL_HRTIM_SimplePWMChannelConfig().

static void HRTIM_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA error callback.

Parameters:
hdma,: pointer to DMA handle.
Return values:
None

Definition at line 7803 of file stm32h7xx_hal_hrtim.c.

References HAL_HRTIM_ErrorCallback().

Referenced by HAL_HRTIM_BurstDMATransfer(), HAL_HRTIM_SimpleBaseStart_DMA(), HAL_HRTIM_SimpleCaptureStart_DMA(), HAL_HRTIM_SimpleOCStart_DMA(), HAL_HRTIM_SimplePWMStart_DMA(), and HAL_HRTIM_WaveformCounterStart_DMA().

static void HRTIM_DMAMasterCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA callback invoked upon master timer related DMA request completion.

Parameters:
hdma,: pointer to DMA handle.
Return values:
None

Definition at line 7693 of file stm32h7xx_hal_hrtim.c.

References HAL_HRTIM_Compare1EventCallback(), HAL_HRTIM_Compare2EventCallback(), HAL_HRTIM_Compare3EventCallback(), HAL_HRTIM_Compare4EventCallback(), HAL_HRTIM_RegistersUpdateCallback(), HAL_HRTIM_RepetitionEventCallback(), HAL_HRTIM_SynchronizationEventCallback(), HRTIM_MASTER_DMA_MCMP1, HRTIM_MASTER_DMA_MCMP2, HRTIM_MASTER_DMA_MCMP3, HRTIM_MASTER_DMA_MCMP4, HRTIM_MASTER_DMA_MREP, HRTIM_MASTER_DMA_MUPD, HRTIM_MASTER_DMA_SYNC, HRTIM_TIMERINDEX_MASTER, and __HRTIM_HandleTypeDef::Instance.

Referenced by HAL_HRTIM_SimpleBaseStart_DMA(), and HAL_HRTIM_WaveformCounterStart_DMA().

static void HRTIM_DMATimerxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA callback invoked upon timer A..E related DMA request completion.

Parameters:
hdma,: pointer to DMA handle.
Return values:
None

Definition at line 7732 of file stm32h7xx_hal_hrtim.c.

References GetTimerIdxFromDMAHandle(), HAL_HRTIM_Capture1EventCallback(), HAL_HRTIM_Capture2EventCallback(), HAL_HRTIM_Compare1EventCallback(), HAL_HRTIM_Compare2EventCallback(), HAL_HRTIM_Compare3EventCallback(), HAL_HRTIM_Compare4EventCallback(), HAL_HRTIM_CounterResetCallback(), HAL_HRTIM_DelayedProtectionCallback(), HAL_HRTIM_Output1ResetCallback(), HAL_HRTIM_Output1SetCallback(), HAL_HRTIM_Output2ResetCallback(), HAL_HRTIM_Output2SetCallback(), HAL_HRTIM_RegistersUpdateCallback(), HAL_HRTIM_RepetitionEventCallback(), HRTIM_TIM_DMA_CMP1, HRTIM_TIM_DMA_CMP2, HRTIM_TIM_DMA_CMP3, HRTIM_TIM_DMA_CMP4, HRTIM_TIM_DMA_CPT1, HRTIM_TIM_DMA_CPT2, HRTIM_TIM_DMA_DLYPRT, HRTIM_TIM_DMA_REP, HRTIM_TIM_DMA_RST, HRTIM_TIM_DMA_RST1, HRTIM_TIM_DMA_RST2, HRTIM_TIM_DMA_SET1, HRTIM_TIM_DMA_SET2, HRTIM_TIM_DMA_UPD, and __HRTIM_HandleTypeDef::Instance.

Referenced by HAL_HRTIM_SimpleBaseStart_DMA(), HAL_HRTIM_SimpleCaptureStart_DMA(), HAL_HRTIM_SimpleOCStart_DMA(), HAL_HRTIM_SimplePWMStart_DMA(), and HAL_HRTIM_WaveformCounterStart_DMA().

static void HRTIM_EventConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | Event,
 |  | HRTIM_EventCfgTypeDef * | pEventCfg
 | ) |  | [static]

Configures an external event channel.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Event,: Event channel identifier
pEventCfg,: pointer to the event channel configuration data structure
Return values:
None

Definition at line 6796 of file stm32h7xx_hal_hrtim.c.

References HRTIM_EventCfgTypeDef::FastMode, HRTIM_EventCfgTypeDef::Filter, HRTIM_EVENT_1, HRTIM_EVENT_10, HRTIM_EVENT_2, HRTIM_EVENT_3, HRTIM_EVENT_4, HRTIM_EVENT_5, HRTIM_EVENT_6, HRTIM_EVENT_7, HRTIM_EVENT_8, HRTIM_EVENT_9, __HRTIM_HandleTypeDef::Instance, HRTIM_EventCfgTypeDef::Polarity, HRTIM_EventCfgTypeDef::Sensitivity, and HRTIM_EventCfgTypeDef::Source.

Referenced by HAL_HRTIM_EventConfig(), HAL_HRTIM_SimpleCaptureChannelConfig(), and HAL_HRTIM_SimpleOnePulseChannelConfig().

static void HRTIM_ForceRegistersUpdate | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  | [static]

Forces an immediate transfer from the preload to the active registers.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index
Return values:
None

Definition at line 7281 of file stm32h7xx_hal_hrtim.c.

References HRTIM_TIMERINDEX_MASTER, HRTIM_TIMERINDEX_TIMER_A, HRTIM_TIMERINDEX_TIMER_B, HRTIM_TIMERINDEX_TIMER_C, HRTIM_TIMERINDEX_TIMER_D, HRTIM_TIMERINDEX_TIMER_E, and __HRTIM_HandleTypeDef::Instance.

Referenced by HAL_HRTIM_WaveformTimerConfig().

static uint32_t HRTIM_GetDMAFromOCMode | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | OCChannel
 | ) |  | [static]

Returns the DMA request to enable or disable according to the OC mode.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index
OCChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
Return values:
DMA request to enable or disable

Definition at line 7125 of file stm32h7xx_hal_hrtim.c.

References HRTIM_OUTPUT_TA1, HRTIM_OUTPUT_TA2, HRTIM_OUTPUT_TB1, HRTIM_OUTPUT_TB2, HRTIM_OUTPUT_TC1, HRTIM_OUTPUT_TC2, HRTIM_OUTPUT_TD1, HRTIM_OUTPUT_TD2, HRTIM_OUTPUT_TE1, HRTIM_OUTPUT_TE2, HRTIM_OUTPUTSET_TIMCMP1, HRTIM_OUTPUTSET_TIMCMP2, HRTIM_TIM_DMA_CMP1, HRTIM_TIM_DMA_CMP2, HRTIM_TIM_DMA_RST1, HRTIM_TIM_DMA_RST2, HRTIM_TIM_DMA_SET1, HRTIM_TIM_DMA_SET2, and __HRTIM_HandleTypeDef::Instance.

Referenced by HAL_HRTIM_SimpleOCStart_DMA(), and HAL_HRTIM_SimpleOCStop_DMA().

static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  | [static]

Definition at line 7200 of file stm32h7xx_hal_hrtim.c.

References __HRTIM_HandleTypeDef::hdmaMaster, __HRTIM_HandleTypeDef::hdmaTimerA, __HRTIM_HandleTypeDef::hdmaTimerB, __HRTIM_HandleTypeDef::hdmaTimerC, __HRTIM_HandleTypeDef::hdmaTimerD, __HRTIM_HandleTypeDef::hdmaTimerE, HRTIM_TIMERINDEX_MASTER, HRTIM_TIMERINDEX_TIMER_A, HRTIM_TIMERINDEX_TIMER_B, HRTIM_TIMERINDEX_TIMER_C, HRTIM_TIMERINDEX_TIMER_D, and HRTIM_TIMERINDEX_TIMER_E.

Referenced by HAL_HRTIM_BurstDMATransfer(), HAL_HRTIM_SimpleBaseStart_DMA(), HAL_HRTIM_SimpleBaseStop_DMA(), HAL_HRTIM_SimpleCaptureStart_DMA(), HAL_HRTIM_SimpleCaptureStop_DMA(), HAL_HRTIM_SimpleOCStart_DMA(), HAL_HRTIM_SimpleOCStop_DMA(), HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_SimplePWMStop_DMA(), HAL_HRTIM_WaveformCounterStart_DMA(), and HAL_HRTIM_WaveformCounterStop_DMA().

static uint32_t HRTIM_GetITFromOCMode | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | OCChannel
 | ) |  | [static]

Returns the interrupt to enable or disable according to the OC mode.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index
OCChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
Return values:
Interrupt to enable or disable

Definition at line 7031 of file stm32h7xx_hal_hrtim.c.

References HRTIM_OUTPUT_TA1, HRTIM_OUTPUT_TA2, HRTIM_OUTPUT_TB1, HRTIM_OUTPUT_TB2, HRTIM_OUTPUT_TC1, HRTIM_OUTPUT_TC2, HRTIM_OUTPUT_TD1, HRTIM_OUTPUT_TD2, HRTIM_OUTPUT_TE1, HRTIM_OUTPUT_TE2, HRTIM_OUTPUTSET_TIMCMP1, HRTIM_OUTPUTSET_TIMCMP2, HRTIM_TIM_IT_CMP1, HRTIM_TIM_IT_CMP2, HRTIM_TIM_IT_RST1, HRTIM_TIM_IT_RST2, HRTIM_TIM_IT_SET1, HRTIM_TIM_IT_SET2, and __HRTIM_HandleTypeDef::Instance.

Referenced by HAL_HRTIM_SimpleOCStart_IT(), and HAL_HRTIM_SimpleOCStop_IT().

static void HRTIM_HRTIM_ISR ( HRTIM_HandleTypeDef * hhrtim ) [static]

HRTIM interrupts service routine.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Return values:
None

Definition at line 7325 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_CLEAR_IT, __HAL_HRTIM_GET_FLAG, __HAL_HRTIM_GET_ITSTATUS, HAL_HRTIM_Fault1Callback(), HAL_HRTIM_Fault2Callback(), HAL_HRTIM_Fault3Callback(), HAL_HRTIM_Fault4Callback(), HAL_HRTIM_Fault5Callback(), HAL_HRTIM_SystemFaultCallback(), HRTIM_FLAG_FLT1, HRTIM_FLAG_FLT2, HRTIM_FLAG_FLT3, HRTIM_FLAG_FLT4, HRTIM_FLAG_FLT5, HRTIM_FLAG_SYSFLT, HRTIM_IT_FLT1, HRTIM_IT_FLT2, HRTIM_IT_FLT3, HRTIM_IT_FLT4, HRTIM_IT_FLT5, and HRTIM_IT_SYSFLT.

Referenced by HAL_HRTIM_IRQHandler().

static void HRTIM_Master_ISR ( HRTIM_HandleTypeDef * hhrtim ) [static]

Master timer interrupts service routine.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Return values:
None

Definition at line 7405 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_CLEAR_IT, __HAL_HRTIM_GET_FLAG, __HAL_HRTIM_GET_ITSTATUS, __HAL_HRTIM_MASTER_CLEAR_IT, __HAL_HRTIM_MASTER_GET_FLAG, __HAL_HRTIM_MASTER_GET_ITSTATUS, HAL_HRTIM_BurstModePeriodCallback(), HAL_HRTIM_Compare1EventCallback(), HAL_HRTIM_Compare2EventCallback(), HAL_HRTIM_Compare3EventCallback(), HAL_HRTIM_Compare4EventCallback(), HAL_HRTIM_RegistersUpdateCallback(), HAL_HRTIM_RepetitionEventCallback(), HAL_HRTIM_SynchronizationEventCallback(), HRTIM_FLAG_BMPER, HRTIM_IT_BMPER, HRTIM_MASTER_FLAG_MCMP1, HRTIM_MASTER_FLAG_MCMP2, HRTIM_MASTER_FLAG_MCMP3, HRTIM_MASTER_FLAG_MCMP4, HRTIM_MASTER_FLAG_MREP, HRTIM_MASTER_FLAG_MUPD, HRTIM_MASTER_FLAG_SYNC, HRTIM_MASTER_IT_MCMP1, HRTIM_MASTER_IT_MCMP2, HRTIM_MASTER_IT_MCMP3, HRTIM_MASTER_IT_MCMP4, HRTIM_MASTER_IT_MREP, HRTIM_MASTER_IT_MUPD, HRTIM_MASTER_IT_SYNC, and HRTIM_TIMERINDEX_MASTER.

Referenced by HAL_HRTIM_IRQHandler().

static void HRTIM_MasterBase_Config | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | HRTIM_TimeBaseCfgTypeDef * | pTimeBaseCfg
 | ) |  | [static]

Configures the master timer time base.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
pTimeBaseCfg,: pointer to the time base configuration structure
Return values:
None

Definition at line 6295 of file stm32h7xx_hal_hrtim.c.

References __HRTIM_HandleTypeDef::Instance, HRTIM_TimeBaseCfgTypeDef::Mode, HRTIM_TimeBaseCfgTypeDef::Period, HRTIM_TimeBaseCfgTypeDef::PrescalerRatio, and HRTIM_TimeBaseCfgTypeDef::RepetitionCounter.

Referenced by HAL_HRTIM_TimeBaseConfig().

static void HRTIM_MasterWaveform_Config | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | HRTIM_TimerCfgTypeDef * | pTimerCfg
 | ) |  | [static]

Configures the master timer in waveform mode.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
pTimerCfg,: pointer to the timer configuration data structure
Return values:
None

Definition at line 6353 of file stm32h7xx_hal_hrtim.c.

References HRTIM_TimerCfgTypeDef::BurstMode, HRTIM_TimerCfgTypeDef::DACSynchro, HRTIM_TimerCfgTypeDef::HalfModeEnable, __HRTIM_HandleTypeDef::Instance, HRTIM_TimerCfgTypeDef::PreloadEnable, HRTIM_TimerCfgTypeDef::RepetitionUpdate, HRTIM_TimerCfgTypeDef::ResetOnSync, HRTIM_TimerCfgTypeDef::StartOnSync, and HRTIM_TimerCfgTypeDef::UpdateGating.

Referenced by HAL_HRTIM_WaveformTimerConfig().

static void HRTIM_OutputConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | Output,
 |  | HRTIM_OutputCfgTypeDef * | pOutputCfg
 | ) |  | [static]

Configures the output of a timing unit.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index
Output,: timing unit output identifier
pOutputCfg,: pointer to the output configuration data structure
Return values:
None

Definition at line 6706 of file stm32h7xx_hal_hrtim.c.

References HRTIM_OutputCfgTypeDef::BurstModeEntryDelayed, HRTIM_OutputCfgTypeDef::ChopperModeEnable, HRTIM_OutputCfgTypeDef::FaultLevel, HRTIM_OUTPUT_TA1, HRTIM_OUTPUT_TA2, HRTIM_OUTPUT_TB1, HRTIM_OUTPUT_TB2, HRTIM_OUTPUT_TC1, HRTIM_OUTPUT_TC2, HRTIM_OUTPUT_TD1, HRTIM_OUTPUT_TD2, HRTIM_OUTPUT_TE1, HRTIM_OUTPUT_TE2, HRTIM_OUTPUTIDLELEVEL_ACTIVE, HRTIM_OutputCfgTypeDef::IdleLevel, HRTIM_OutputCfgTypeDef::IdleMode, __HRTIM_HandleTypeDef::Instance, HRTIM_OutputCfgTypeDef::Polarity, HRTIM_OutputCfgTypeDef::ResetSource, and HRTIM_OutputCfgTypeDef::SetSource.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimplePWMChannelConfig(), and HAL_HRTIM_WaveformOutputConfig().

static void HRTIM_TIM_ResetConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | Event
 | ) |  | [static]

Configures the timer counter reset.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index
Event,: Event channel identifier
Return values:
None

Definition at line 6953 of file stm32h7xx_hal_hrtim.c.

References HRTIM_EVENT_1, HRTIM_EVENT_10, HRTIM_EVENT_2, HRTIM_EVENT_3, HRTIM_EVENT_4, HRTIM_EVENT_5, HRTIM_EVENT_6, HRTIM_EVENT_7, HRTIM_EVENT_8, HRTIM_EVENT_9, HRTIM_TIMRESETTRIGGER_EEV_1, HRTIM_TIMRESETTRIGGER_EEV_10, HRTIM_TIMRESETTRIGGER_EEV_2, HRTIM_TIMRESETTRIGGER_EEV_3, HRTIM_TIMRESETTRIGGER_EEV_4, HRTIM_TIMRESETTRIGGER_EEV_5, HRTIM_TIMRESETTRIGGER_EEV_6, HRTIM_TIMRESETTRIGGER_EEV_7, HRTIM_TIMRESETTRIGGER_EEV_8, HRTIM_TIMRESETTRIGGER_EEV_9, and __HRTIM_HandleTypeDef::Instance.

Referenced by HAL_HRTIM_SimpleOnePulseChannelConfig().

static void HRTIM_Timer_ISR | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  | [static]

Timer interrupts service routine.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
None

Definition at line 7516 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_TIMER_CLEAR_IT, __HAL_HRTIM_TIMER_GET_FLAG, __HAL_HRTIM_TIMER_GET_ITSTATUS, HAL_HRTIM_Capture1EventCallback(), HAL_HRTIM_Capture2EventCallback(), HAL_HRTIM_Compare1EventCallback(), HAL_HRTIM_Compare2EventCallback(), HAL_HRTIM_Compare3EventCallback(), HAL_HRTIM_Compare4EventCallback(), HAL_HRTIM_CounterResetCallback(), HAL_HRTIM_DelayedProtectionCallback(), HAL_HRTIM_Output1ResetCallback(), HAL_HRTIM_Output1SetCallback(), HAL_HRTIM_Output2ResetCallback(), HAL_HRTIM_Output2SetCallback(), HAL_HRTIM_RegistersUpdateCallback(), HAL_HRTIM_RepetitionEventCallback(), HRTIM_TIM_FLAG_CMP1, HRTIM_TIM_FLAG_CMP2, HRTIM_TIM_FLAG_CMP3, HRTIM_TIM_FLAG_CMP4, HRTIM_TIM_FLAG_CPT1, HRTIM_TIM_FLAG_CPT2, HRTIM_TIM_FLAG_DLYPRT, HRTIM_TIM_FLAG_REP, HRTIM_TIM_FLAG_RST, HRTIM_TIM_FLAG_RST1, HRTIM_TIM_FLAG_RST2, HRTIM_TIM_FLAG_SET1, HRTIM_TIM_FLAG_SET2, HRTIM_TIM_FLAG_UPD, HRTIM_TIM_IT_CMP1, HRTIM_TIM_IT_CMP2, HRTIM_TIM_IT_CMP3, HRTIM_TIM_IT_CMP4, HRTIM_TIM_IT_CPT1, HRTIM_TIM_IT_CPT2, HRTIM_TIM_IT_DLYPRT, HRTIM_TIM_IT_REP, HRTIM_TIM_IT_RST, HRTIM_TIM_IT_RST1, HRTIM_TIM_IT_RST2, HRTIM_TIM_IT_SET1, HRTIM_TIM_IT_SET2, and HRTIM_TIM_IT_UPD.

Referenced by HAL_HRTIM_IRQHandler().

static void HRTIM_TimingUnitBase_Config | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | HRTIM_TimeBaseCfgTypeDef * | pTimeBaseCfg
 | ) |  | [static]

Configures timing unit (timer A to timer E) time base.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index
pTimeBaseCfg,: pointer to the time base configuration structure
Return values:
None

Definition at line 6324 of file stm32h7xx_hal_hrtim.c.

References __HRTIM_HandleTypeDef::Instance, HRTIM_TimeBaseCfgTypeDef::Mode, HRTIM_TimeBaseCfgTypeDef::Period, HRTIM_TimeBaseCfgTypeDef::PrescalerRatio, and HRTIM_TimeBaseCfgTypeDef::RepetitionCounter.

Referenced by HAL_HRTIM_TimeBaseConfig().

static void HRTIM_TimingUnitWaveform_Config | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | HRTIM_TimerCfgTypeDef * | pTimerCfg
 | ) |  | [static]

Configures timing unit (timer A to timer E) in waveform mode.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index
pTimerCfg,: pointer to the timer configuration data structure
Return values:
None

Definition at line 6407 of file stm32h7xx_hal_hrtim.c.

References HRTIM_TimerCfgTypeDef::BurstMode, HRTIM_TimerCfgTypeDef::DACSynchro, HRTIM_TimerCfgTypeDef::DeadTimeInsertion, HRTIM_TimerCfgTypeDef::DelayedProtectionMode, HRTIM_TimerCfgTypeDef::FaultEnable, HRTIM_TimerCfgTypeDef::FaultLock, HRTIM_TimerCfgTypeDef::HalfModeEnable, HRTIM_FLTR_FLTxEN, HRTIM_TIMCR_TIMUPDATETRIGGER, HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6, HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7, HRTIM_TIMERINDEX_TIMER_A, HRTIM_TIMERINDEX_TIMER_B, HRTIM_TIMERINDEX_TIMER_C, HRTIM_TIMERINDEX_TIMER_D, HRTIM_TIMERINDEX_TIMER_E, HRTIM_TIMPUSHPULLMODE_DISABLED, HRTIM_TIMPUSHPULLMODE_ENABLED, HRTIM_UPDATEONREPETITION_ENABLED, __HRTIM_HandleTypeDef::Instance, HRTIM_TimerCfgTypeDef::PreloadEnable, HRTIM_TimerCfgTypeDef::PushPull, HRTIM_TimerCfgTypeDef::RepetitionUpdate, HRTIM_TimerCfgTypeDef::ResetOnSync, HRTIM_TimerCfgTypeDef::ResetTrigger, HRTIM_TimerCfgTypeDef::ResetUpdate, HRTIM_TimerCfgTypeDef::StartOnSync, HRTIM_TimerCfgTypeDef::UpdateGating, and HRTIM_TimerCfgTypeDef::UpdateTrigger.

Referenced by HAL_HRTIM_WaveformTimerConfig().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
HRTIM Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_HRTIM_Init (HRTIM_HandleTypeDef *hhrtim)
Initializes a HRTIM instance.
HAL_StatusTypeDef | HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim)
De-initializes a HRTIM instance.
__weak void | HAL_HRTIM_MspInit (HRTIM_HandleTypeDef *hhrtim)
MSP initialization for a HRTIM instance.
__weak void | HAL_HRTIM_MspDeInit (HRTIM_HandleTypeDef *hhrtim)
MSP initialization for a for a HRTIM instance.
HAL_StatusTypeDef | HAL_HRTIM_TimeBaseConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg)
Configures the time base unit of a timer.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and Time Base Configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize a HRTIM instance
      (+) De-initialize a HRTIM instance
      (+) Initialize the HRTIM MSP
      (+) De-initialize the HRTIM MSP
      (+) Configure the time base unit of a HRTIM timer

Function Documentation

HAL_StatusTypeDef HAL_HRTIM_DeInit ( HRTIM_HandleTypeDef * hhrtim )

De-initializes a HRTIM instance.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Return values:
HAL status

Definition at line 560 of file stm32h7xx_hal_hrtim.c.

References assert_param, HAL_HRTIM_MspDeInit(), HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::Instance, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_Init ( HRTIM_HandleTypeDef * hhrtim )

Initializes a HRTIM instance.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Return values:
HAL status

Definition at line 458 of file stm32h7xx_hal_hrtim.c.

References __HAL_RCC_HRTIM1_CLK_ENABLE, assert_param, HRTIM_TimerParamTypeDef::CaptureTrigger1, HRTIM_TimerParamTypeDef::CaptureTrigger2, HRTIM_TimerParamTypeDef::DMARequests, HRTIM_TimerParamTypeDef::DMASize, HRTIM_TimerParamTypeDef::DMASrcAddress, HAL_HRTIM_MspInit(), HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::hdmaMaster, __HRTIM_HandleTypeDef::hdmaTimerA, __HRTIM_HandleTypeDef::hdmaTimerB, __HRTIM_HandleTypeDef::hdmaTimerC, __HRTIM_HandleTypeDef::hdmaTimerD, __HRTIM_HandleTypeDef::hdmaTimerE, HRTIM_CAPTURETRIGGER_NONE, HRTIM_IT_NONE, HRTIM_SYNCOPTION_MASTER, HRTIM_SYNCOPTION_SLAVE, HRTIM_TIMERINDEX_MASTER, HRTIM_TIMERINDEX_TIMER_A, HRTIM_InitTypeDef::HRTIMInterruptResquests, __HRTIM_HandleTypeDef::Init, __HRTIM_HandleTypeDef::Instance, HRTIM_TimerParamTypeDef::InterruptRequests, IS_HRTIM_IT, IS_HRTIM_SYNCINPUTSOURCE, IS_HRTIM_SYNCOUTPUTPOLARITY, IS_HRTIM_SYNCOUTPUTSOURCE, __HRTIM_HandleTypeDef::State, HRTIM_InitTypeDef::SyncInputSource, HRTIM_InitTypeDef::SyncOptions, HRTIM_InitTypeDef::SyncOutputPolarity, HRTIM_InitTypeDef::SyncOutputSource, and __HRTIM_HandleTypeDef::TimerParam.

void HAL_HRTIM_MspDeInit ( HRTIM_HandleTypeDef * hhrtim )

MSP initialization for a for a HRTIM instance.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Return values:
None

Definition at line 601 of file stm32h7xx_hal_hrtim.c.

Referenced by HAL_HRTIM_DeInit().

void HAL_HRTIM_MspInit ( HRTIM_HandleTypeDef * hhrtim )

MSP initialization for a HRTIM instance.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Return values:
None

Definition at line 587 of file stm32h7xx_hal_hrtim.c.

Referenced by HAL_HRTIM_Init().

HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | HRTIM_TimeBaseCfgTypeDef * | pTimeBaseCfg
 | ) |  |

Configures the time base unit of a timer.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_MASTER for master timer
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
pTimeBaseCfg,: pointer to the time base configuration structure
Note:
This function must be called prior starting the timer
The time-base unit initialization parameters specify: The timer counter operating mode (continuous, one shot), The timer clock prescaler, The timer period, The timer repetition counter.
Return values:
HAL status

Definition at line 631 of file stm32h7xx_hal_hrtim.c.

References assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_MasterBase_Config(), HRTIM_TIMERINDEX_MASTER, HRTIM_TimingUnitBase_Config(), IS_HRTIM_MODE, IS_HRTIM_PRESCALERRATIO, IS_HRTIM_TIMERINDEX, HRTIM_TimeBaseCfgTypeDef::Mode, HRTIM_TimeBaseCfgTypeDef::PrescalerRatio, and __HRTIM_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Simple time base mode functions

Functions
Simple time base mode functions
HRTIM Exported Functions

Simple time base mode functions. More...

Functions

HAL_StatusTypeDef | HAL_HRTIM_SimpleBaseStart (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Starts the counter of a timer operating in basic time base mode.
HAL_StatusTypeDef | HAL_HRTIM_SimpleBaseStop (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Stops the counter of a timer operating in basic time base mode.
HAL_StatusTypeDef | HAL_HRTIM_SimpleBaseStart_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Starts the counter of a timer operating in simple time base mode (Timer repetition interrupt is enabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleBaseStop_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Stops the counter of a timer operating in simple time base mode (Timer repetition interrupt is disabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleBaseStart_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t SrcAddr, uint32_t DestAddr, uint32_t Length)
Starts the counter of a timer operating in simple time base mode (Timer repetition DMA request is enabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleBaseStop_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Stops the counter of a timer operating in simple time base mode (Timer repetition DMA request is disabled).

Detailed Description

Simple time base mode functions.

 ===============================================================================
              ##### Simple time base mode functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start simple time base
      (+) Stop simple time base
      (+) Start simple time base and enable interrupt
      (+) Stop simple time base and disable interrupt
      (+) Start simple time base and enable DMA transfer
      (+) Stop simple time base and disable DMA transfer
      -@-  When a HRTIM timer operates in simple time base mode, the timer
       counter counts from 0 to the period value.

Function Documentation

HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Starts the counter of a timer operating in basic time base mode.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_MASTER for master timer
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
HAL status

Definition at line 703 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_ENABLE, assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, IS_HRTIM_TIMERINDEX, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | SrcAddr,
 |  | uint32_t | DestAddr,
 |  | uint32_t | Length
 | ) |  |

Starts the counter of a timer operating in simple time base mode (Timer repetition DMA request is enabled).

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_MASTER for master timer
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
SrcAddr,: DMA transfer source address
DestAddr,: DMA transfer destination address
Length,: The length of data items (data size) to be transferred from source to destination

Definition at line 869 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_ENABLE, __HAL_HRTIM_MASTER_ENABLE_DMA, __HAL_HRTIM_TIMER_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_DMAError(), HRTIM_DMAMasterCplt(), HRTIM_DMATimerxCplt(), HRTIM_GetDMAHandleFromTimerIdx(), HRTIM_MASTER_DMA_MREP, HRTIM_TIM_DMA_REP, HRTIM_TIMERINDEX_MASTER, IS_HRTIM_TIMERINDEX, __HRTIM_HandleTypeDef::State, TimerIdxToTimerId, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Starts the counter of a timer operating in simple time base mode (Timer repetition interrupt is enabled).

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_MASTER for master timer
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
HAL status

Definition at line 774 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_ENABLE, __HAL_HRTIM_MASTER_ENABLE_IT, __HAL_HRTIM_TIMER_ENABLE_IT, assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_MASTER_IT_MREP, HRTIM_TIM_IT_REP, HRTIM_TIMERINDEX_MASTER, IS_HRTIM_TIMERINDEX, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Stops the counter of a timer operating in basic time base mode.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_MASTER for master timer
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
HAL status

Definition at line 738 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_DISABLE, assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, IS_HRTIM_TIMERINDEX, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Stops the counter of a timer operating in simple time base mode (Timer repetition DMA request is disabled).

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_MASTER for master timer
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
HAL status

Definition at line 953 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_DISABLE, __HAL_HRTIM_MASTER_DISABLE_DMA, __HAL_HRTIM_TIMER_DISABLE_DMA, assert_param, HAL_DMA_Abort(), HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::hdmaMaster, HRTIM_GetDMAHandleFromTimerIdx(), HRTIM_MASTER_DMA_MREP, HRTIM_TIM_DMA_REP, HRTIM_TIMERINDEX_MASTER, IS_HRTIM_TIMERINDEX, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Stops the counter of a timer operating in simple time base mode (Timer repetition interrupt is disabled).

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_MASTER for master timer
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
HAL status

Definition at line 820 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_DISABLE, __HAL_HRTIM_MASTER_DISABLE_IT, __HAL_HRTIM_TIMER_DISABLE_IT, assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_MASTER_IT_MREP, HRTIM_TIM_IT_REP, HRTIM_TIMERINDEX_MASTER, IS_HRTIM_TIMERINDEX, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Simple output compare mode functions

Functions
Simple output compare mode functions
HRTIM Exported Functions

Simple output compare functions. More...

Functions

HAL_StatusTypeDef | HAL_HRTIM_SimpleOCChannelConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel, HRTIM_SimpleOCChannelCfgTypeDef *pSimpleOCChannelCfg)
Configures an output in simple output compare mode.
HAL_StatusTypeDef | HAL_HRTIM_SimpleOCStart (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel)
Starts the output compare signal generation on the designed timer output.
HAL_StatusTypeDef | HAL_HRTIM_SimpleOCStop (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel)
Stops the output compare signal generation on the designed timer output.
HAL_StatusTypeDef | HAL_HRTIM_SimpleOCStart_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel)
Starts the output compare signal generation on the designed timer output (Interrupt is enabled (see note note below)).
HAL_StatusTypeDef | HAL_HRTIM_SimpleOCStop_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel)
Stops the output compare signal generation on the designed timer output (Interrupt is disabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleOCStart_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel, uint32_t SrcAddr, uint32_t DestAddr, uint32_t Length)
Starts the output compare signal generation on the designed timer output (DMA request is enabled (see note below)).
HAL_StatusTypeDef | HAL_HRTIM_SimpleOCStop_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel)
Stops the output compare signal generation on the designed timer output (DMA request is disabled).

Detailed Description

Simple output compare functions.

 ===============================================================================
              ##### Simple output compare functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure simple output channel
      (+) Start simple output compare
      (+) Stop simple output compare
      (+) Start simple output compare and enable interrupt
      (+) Stop simple output compare and disable interrupt
      (+) Start simple output compare and enable DMA transfer
      (+) Stop simple output compare and disable DMA transfer
       -@- When a HRTIM timer operates in simple output compare mode
           the output level is set to a programmable value when a match
           is found between the compare register and the counter.
           Compare unit 1 is automatically associated to output 1
           Compare unit 2 is automatically associated to output 2

Function Documentation

HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | OCChannel,
 |  | HRTIM_SimpleOCChannelCfgTypeDef * | pSimpleOCChannelCfg
 | ) |  |

Configures an output in simple output compare mode.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
OCChannel,: Timer output
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
pSimpleOCChannelCfg,: pointer to the simple output compare output configuration structure
Note:
When the timer operates in simple output compare mode: Output 1 is implicitly controlled by the compare unit 1 Output 2 is implicitly controlled by the compare unit 2 Output Set/Reset crossbar is set according to the selected output compare mode: Toggle: SETxyR = RSTxyR = CMPy Active: SETxyR = CMPy, RSTxyR = 0 Inactive: SETxy =0, RSTxy = CMPy
Return values:
HAL status

Definition at line 1055 of file stm32h7xx_hal_hrtim.c.

References assert_param, HRTIM_CompareCfgTypeDef::AutoDelayedMode, HRTIM_CompareCfgTypeDef::AutoDelayedTimeout, HRTIM_OutputCfgTypeDef::BurstModeEntryDelayed, HRTIM_OutputCfgTypeDef::ChopperModeEnable, HRTIM_CompareCfgTypeDef::CompareValue, HRTIM_OutputCfgTypeDef::FaultLevel, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_AUTODELAYEDMODE_REGULAR, HRTIM_BASICOCMODE_ACTIVE, HRTIM_BASICOCMODE_INACTIVE, HRTIM_BASICOCMODE_TOGGLE, HRTIM_COMPAREUNIT_1, HRTIM_COMPAREUNIT_2, HRTIM_CompareUnitConfig(), HRTIM_OUTPUT_TA1, HRTIM_OUTPUT_TA2, HRTIM_OUTPUT_TB1, HRTIM_OUTPUT_TB2, HRTIM_OUTPUT_TC1, HRTIM_OUTPUT_TC2, HRTIM_OUTPUT_TD1, HRTIM_OUTPUT_TD2, HRTIM_OUTPUT_TE1, HRTIM_OUTPUT_TE2, HRTIM_OUTPUTBURSTMODEENTRY_REGULAR, HRTIM_OUTPUTCHOPPERMODE_DISABLED, HRTIM_OutputConfig(), HRTIM_OUTPUTFAULTLEVEL_NONE, HRTIM_OUTPUTIDLEMODE_NONE, HRTIM_OUTPUTRESET_NONE, HRTIM_OUTPUTRESET_TIMCMP1, HRTIM_OUTPUTRESET_TIMCMP2, HRTIM_OUTPUTSET_NONE, HRTIM_OUTPUTSET_TIMCMP1, HRTIM_OUTPUTSET_TIMCMP2, HRTIM_SimpleOCChannelCfgTypeDef::IdleLevel, HRTIM_OutputCfgTypeDef::IdleLevel, HRTIM_OutputCfgTypeDef::IdleMode, IS_HRTIM_BASICOCMODE, IS_HRTIM_OUTPUTIDLELEVEL, IS_HRTIM_OUTPUTPOLARITY, IS_HRTIM_TIMER_OUTPUT, HRTIM_SimpleOCChannelCfgTypeDef::Mode, HRTIM_SimpleOCChannelCfgTypeDef::Polarity, HRTIM_OutputCfgTypeDef::Polarity, HRTIM_SimpleOCChannelCfgTypeDef::Pulse, HRTIM_OutputCfgTypeDef::ResetSource, HRTIM_OutputCfgTypeDef::SetSource, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | OCChannel
 | ) |  |

Starts the output compare signal generation on the designed timer output.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
OCChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
Return values:
HAL status

Definition at line 1196 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_ENABLE, assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMER_OUTPUT, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | OCChannel,
 |  | uint32_t | SrcAddr,
 |  | uint32_t | DestAddr,
 |  | uint32_t | Length
 | ) |  |

Starts the output compare signal generation on the designed timer output (DMA request is enabled (see note below)).

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
OCChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
SrcAddr,: DMA transfer source address
DestAddr,: DMA transfer destination address
Length,: The length of data items (data size) to be transferred from source to destination
Note:
DMA request enabling depends on the chosen output compare mode Output toggle: compare match DMA request is enabled Output set active: output set DMA request is enabled Output set inactive: output reset DMA request is enabled
Return values:
HAL status

Definition at line 1427 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_ENABLE, __HAL_HRTIM_TIMER_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_DMAError(), HRTIM_DMATimerxCplt(), HRTIM_GetDMAFromOCMode(), HRTIM_GetDMAHandleFromTimerIdx(), __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMER_OUTPUT, __HRTIM_HandleTypeDef::State, TimerIdxToTimerId, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | OCChannel
 | ) |  |

Starts the output compare signal generation on the designed timer output (Interrupt is enabled (see note note below)).

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
OCChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
Note:
Interrupt enabling depends on the chosen output compare mode Output toggle: compare match interrupt is enabled Output set active: output set interrupt is enabled Output set inactive: output reset interrupt is enabled
Return values:
HAL status

Definition at line 1301 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_ENABLE, __HAL_HRTIM_TIMER_ENABLE_IT, assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_GetITFromOCMode(), __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMER_OUTPUT, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | OCChannel
 | ) |  |

Stops the output compare signal generation on the designed timer output.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
OCChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
Return values:
HAL status

Definition at line 1246 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_DISABLE, assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMER_OUTPUT, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | OCChannel
 | ) |  |

Stops the output compare signal generation on the designed timer output (DMA request is disabled).

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
OCChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
Return values:
HAL status

Definition at line 1516 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_DISABLE, __HAL_HRTIM_TIMER_DISABLE_DMA, assert_param, HAL_DMA_Abort(), HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_GetDMAFromOCMode(), HRTIM_GetDMAHandleFromTimerIdx(), __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMER_OUTPUT, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | OCChannel
 | ) |  |

Stops the output compare signal generation on the designed timer output (Interrupt is disabled).

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
OCChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
Return values:
HAL status

Definition at line 1360 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_DISABLE, __HAL_HRTIM_TIMER_DISABLE_IT, assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_GetITFromOCMode(), __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMER_OUTPUT, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Simple PWM output mode functions

Functions
Simple PWM output mode functions
HRTIM Exported Functions

Simple PWM output functions. More...

Functions

HAL_StatusTypeDef | HAL_HRTIM_SimplePWMChannelConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel, HRTIM_SimplePWMChannelCfgTypeDef *pSimplePWMChannelCfg)
Configures an output in simple PWM mode.
HAL_StatusTypeDef | HAL_HRTIM_SimplePWMStart (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel)
Starts the PWM output signal generation on the designed timer output.
HAL_StatusTypeDef | HAL_HRTIM_SimplePWMStop (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel)
Stops the PWM output signal generation on the designed timer output.
HAL_StatusTypeDef | HAL_HRTIM_SimplePWMStart_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel)
Starts the PWM output signal generation on the designed timer output (The compare interrupt is enabled).
HAL_StatusTypeDef | HAL_HRTIM_SimplePWMStop_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel)
Stops the PWM output signal generation on the designed timer output (The compare interrupt is disabled).
HAL_StatusTypeDef | HAL_HRTIM_SimplePWMStart_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel, uint32_t SrcAddr, uint32_t DestAddr, uint32_t Length)
Starts the PWM output signal generation on the designed timer output (The compare DMA request is enabled).
HAL_StatusTypeDef | HAL_HRTIM_SimplePWMStop_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel)
Stops the PWM output signal generation on the designed timer output (The compare DMA request is disabled).

Detailed Description

Simple PWM output functions.

 ===============================================================================
              ##### Simple PWM output functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure simple PWM output channel
      (+) Start simple PWM output
      (+) Stop simple PWM output
      (+) Start simple PWM output and enable interrupt
      (+) Stop simple PWM output and disable interrupt
      (+) Start simple PWM output and enable DMA transfer
      (+) Stop simple PWM output and disable DMA transfer
      -@- When a HRTIM timer operates in simple PWM output mode
          the output level is set to a programmable value when a match is
          found between the compare register and the counter and reset when
          the timer period is reached. Duty cycle is determined by the
          comparison value.
          Compare unit 1 is automatically associated to output 1
          Compare unit 2 is automatically associated to output 2

Function Documentation

HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | PWMChannel,
 |  | HRTIM_SimplePWMChannelCfgTypeDef * | pSimplePWMChannelCfg
 | ) |  |

Configures an output in simple PWM mode.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
PWMChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
pSimplePWMChannelCfg,: pointer to the simple PWM output configuration structure
Note:
When the timer operates in simple PWM output mode: Output 1 is implicitly controlled by the compare unit 1 Output 2 is implicitly controlled by the compare unit 2 Output Set/Reset crossbar is set as follows: Output 1: SETx1R = CMP1, RSTx1R = PER Output 2: SETx2R = CMP2, RST2R = PER
When Simple PWM mode is used the registers preload mechanism is enabled (otherwise the behavior is not guaranteed).
Return values:
HAL status

Definition at line 1621 of file stm32h7xx_hal_hrtim.c.

References assert_param, HRTIM_CompareCfgTypeDef::AutoDelayedMode, HRTIM_CompareCfgTypeDef::AutoDelayedTimeout, HRTIM_OutputCfgTypeDef::BurstModeEntryDelayed, HRTIM_OutputCfgTypeDef::ChopperModeEnable, HRTIM_CompareCfgTypeDef::CompareValue, HRTIM_OutputCfgTypeDef::FaultLevel, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_AUTODELAYEDMODE_REGULAR, HRTIM_COMPAREUNIT_1, HRTIM_COMPAREUNIT_2, HRTIM_CompareUnitConfig(), HRTIM_OUTPUT_TA1, HRTIM_OUTPUT_TA2, HRTIM_OUTPUT_TB1, HRTIM_OUTPUT_TB2, HRTIM_OUTPUT_TC1, HRTIM_OUTPUT_TC2, HRTIM_OUTPUT_TD1, HRTIM_OUTPUT_TD2, HRTIM_OUTPUT_TE1, HRTIM_OUTPUT_TE2, HRTIM_OUTPUTBURSTMODEENTRY_REGULAR, HRTIM_OUTPUTCHOPPERMODE_DISABLED, HRTIM_OutputConfig(), HRTIM_OUTPUTFAULTLEVEL_NONE, HRTIM_OUTPUTIDLEMODE_NONE, HRTIM_OUTPUTSET_TIMCMP1, HRTIM_OUTPUTSET_TIMCMP2, HRTIM_OUTPUTSET_TIMPER, HRTIM_SimplePWMChannelCfgTypeDef::IdleLevel, HRTIM_OutputCfgTypeDef::IdleLevel, HRTIM_OutputCfgTypeDef::IdleMode, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_OUTPUTIDLELEVEL, IS_HRTIM_OUTPUTPOLARITY, IS_HRTIM_TIMER_OUTPUT, HRTIM_SimplePWMChannelCfgTypeDef::Polarity, HRTIM_OutputCfgTypeDef::Polarity, HRTIM_SimplePWMChannelCfgTypeDef::Pulse, HRTIM_OutputCfgTypeDef::ResetSource, HRTIM_OutputCfgTypeDef::SetSource, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | PWMChannel
 | ) |  |

Starts the PWM output signal generation on the designed timer output.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
PWMChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
Return values:
HAL status

Definition at line 1735 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_ENABLE, assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMER_OUTPUT, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | PWMChannel,
 |  | uint32_t | SrcAddr,
 |  | uint32_t | DestAddr,
 |  | uint32_t | Length
 | ) |  |

Starts the PWM output signal generation on the designed timer output (The compare DMA request is enabled).

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
PWMChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
SrcAddr,: DMA transfer source address
DestAddr,: DMA transfer destination address
Length,: The length of data items (data size) to be transferred from source to destination
Return values:
HAL status

Definition at line 1988 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_ENABLE, __HAL_HRTIM_TIMER_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_DMAError(), HRTIM_DMATimerxCplt(), HRTIM_GetDMAHandleFromTimerIdx(), HRTIM_OUTPUT_TA1, HRTIM_OUTPUT_TA2, HRTIM_OUTPUT_TB1, HRTIM_OUTPUT_TB2, HRTIM_OUTPUT_TC1, HRTIM_OUTPUT_TC2, HRTIM_OUTPUT_TD1, HRTIM_OUTPUT_TD2, HRTIM_OUTPUT_TE1, HRTIM_OUTPUT_TE2, HRTIM_TIM_DMA_CMP1, HRTIM_TIM_DMA_CMP2, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMER_OUTPUT, __HRTIM_HandleTypeDef::State, TimerIdxToTimerId, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | PWMChannel
 | ) |  |

Starts the PWM output signal generation on the designed timer output (The compare interrupt is enabled).

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
PWMChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
Return values:
HAL status

Definition at line 1836 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_ENABLE, __HAL_HRTIM_TIMER_ENABLE_IT, assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_OUTPUT_TA1, HRTIM_OUTPUT_TA2, HRTIM_OUTPUT_TB1, HRTIM_OUTPUT_TB2, HRTIM_OUTPUT_TC1, HRTIM_OUTPUT_TC2, HRTIM_OUTPUT_TD1, HRTIM_OUTPUT_TD2, HRTIM_OUTPUT_TE1, HRTIM_OUTPUT_TE2, HRTIM_TIM_IT_CMP1, HRTIM_TIM_IT_CMP2, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMER_OUTPUT, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | PWMChannel
 | ) |  |

Stops the PWM output signal generation on the designed timer output.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
PWMChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
Return values:
HAL status

Definition at line 1785 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_DISABLE, assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMER_OUTPUT, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | PWMChannel
 | ) |  |

Stops the PWM output signal generation on the designed timer output (The compare DMA request is disabled).

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
PWMChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
Return values:
HAL status

Definition at line 2093 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_DISABLE, __HAL_HRTIM_TIMER_DISABLE_DMA, assert_param, HAL_DMA_Abort(), HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_GetDMAHandleFromTimerIdx(), HRTIM_OUTPUT_TA1, HRTIM_OUTPUT_TA2, HRTIM_OUTPUT_TB1, HRTIM_OUTPUT_TB2, HRTIM_OUTPUT_TC1, HRTIM_OUTPUT_TC2, HRTIM_OUTPUT_TD1, HRTIM_OUTPUT_TD2, HRTIM_OUTPUT_TE1, HRTIM_OUTPUT_TE2, HRTIM_TIM_DMA_CMP1, HRTIM_TIM_DMA_CMP2, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMER_OUTPUT, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | PWMChannel
 | ) |  |

Stops the PWM output signal generation on the designed timer output (The compare interrupt is disabled).

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
PWMChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
Return values:
HAL status

Definition at line 1910 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_DISABLE, __HAL_HRTIM_TIMER_DISABLE_IT, assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_OUTPUT_TA1, HRTIM_OUTPUT_TA2, HRTIM_OUTPUT_TB1, HRTIM_OUTPUT_TB2, HRTIM_OUTPUT_TC1, HRTIM_OUTPUT_TC2, HRTIM_OUTPUT_TD1, HRTIM_OUTPUT_TD2, HRTIM_OUTPUT_TE1, HRTIM_OUTPUT_TE2, HRTIM_TIM_IT_CMP1, HRTIM_TIM_IT_CMP2, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMER_OUTPUT, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Simple input capture functions

Functions
Simple input capture functions
HRTIM Exported Functions

Simple input capture functions. More...

Functions

HAL_StatusTypeDef | HAL_HRTIM_SimpleCaptureChannelConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel, HRTIM_SimpleCaptureChannelCfgTypeDef *pSimpleCaptureChannelCfg)
Configures a simple capture.
HAL_StatusTypeDef | HAL_HRTIM_SimpleCaptureStart (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel)
Enables a simple capture on the designed capture unit.
HAL_StatusTypeDef | HAL_HRTIM_SimpleCaptureStop (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel)
Disables a simple capture on the designed capture unit.
HAL_StatusTypeDef | HAL_HRTIM_SimpleCaptureStart_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel)
Enables a basic capture on the designed capture unit (Capture interrupt is enabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleCaptureStop_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel)
Disables a basic capture on the designed capture unit (Capture interrupt is disabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleCaptureStart_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel, uint32_t SrcAddr, uint32_t DestAddr, uint32_t Length)
Enables a basic capture on the designed capture unit (Capture DMA request is enabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleCaptureStop_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel)
Disables a basic capture on the designed capture unit (Capture DMA request is disabled).

Detailed Description

Simple input capture functions.

 ===============================================================================
              ##### Simple input capture functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure simple input capture channel
      (+) Start simple input capture
      (+) Stop simple input capture
      (+) Start simple input capture and enable interrupt
      (+) Stop simple input capture and disable interrupt
      (+) Start simple input capture and enable DMA transfer
      (+) Stop simple input capture and disable DMA transfer
      -@- When a HRTIM timer operates in simple input capture mode
          the Capture Register (HRTIM_CPT1/2xR) is used to latch the
         value of the timer counter counter after a transition detected
         on a given external event input.

Function Documentation

HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | CaptureChannel,
 |  | HRTIM_SimpleCaptureChannelCfgTypeDef * | pSimpleCaptureChannelCfg
 | ) |  |

Configures a simple capture.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
CaptureChannel,: Capture unit This parameter can be one of the following values:
  • HRTIM_CAPTUREUNIT_1: Capture unit 1
  • HRTIM_CAPTUREUNIT_2: Capture unit 2
pSimpleCaptureChannelCfg,: pointer to the simple capture configuration structure
Note:
When the timer operates in simple capture mode the capture is trigerred by the designated external event and GPIO input is implicitly used as event source. The cature can be triggered by a rising edge, a falling edge or both edges on event channel.
Return values:
HAL status

Definition at line 2199 of file stm32h7xx_hal_hrtim.c.

References assert_param, HRTIM_SimpleCaptureChannelCfgTypeDef::Event, HRTIM_SimpleCaptureChannelCfgTypeDef::EventFilter, HRTIM_SimpleCaptureChannelCfgTypeDef::EventPolarity, HRTIM_SimpleCaptureChannelCfgTypeDef::EventSensitivity, HRTIM_EventCfgTypeDef::FastMode, HRTIM_EventCfgTypeDef::Filter, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_CaptureUnitConfig(), HRTIM_EventConfig(), HRTIM_EVENTFASTMODE_DISABLE, HRTIM_EVENTSRC_1, IS_HRTIM_CAPTUREUNIT, IS_HRTIM_EVENT, IS_HRTIM_EVENTFILTER, IS_HRTIM_EVENTPOLARITY, IS_HRTIM_EVENTSENSITIVITY, IS_HRTIM_TIMING_UNIT, HRTIM_EventCfgTypeDef::Polarity, HRTIM_EventCfgTypeDef::Sensitivity, HRTIM_EventCfgTypeDef::Source, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | CaptureChannel
 | ) |  |

Enables a simple capture on the designed capture unit.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
CaptureChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_CAPTUREUNIT_1: Capture unit 1
  • HRTIM_CAPTUREUNIT_2: Capture unit 2
Return values:
HAL status
Note:
The external event triggering the capture is available for all timing units. It can be used directly and is active as soon as the timing unit counter is enabled.

Definition at line 2270 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_ENABLE, assert_param, HRTIM_TimerParamTypeDef::CaptureTrigger1, HRTIM_TimerParamTypeDef::CaptureTrigger2, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_CAPTUREUNIT_1, HRTIM_CAPTUREUNIT_2, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_CAPTUREUNIT, IS_HRTIM_TIMING_UNIT, __HRTIM_HandleTypeDef::State, TimerIdxToTimerId, and __HRTIM_HandleTypeDef::TimerParam.

HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | CaptureChannel,
 |  | uint32_t | SrcAddr,
 |  | uint32_t | DestAddr,
 |  | uint32_t | Length
 | ) |  |

Enables a basic capture on the designed capture unit (Capture DMA request is enabled).

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
CaptureChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_CAPTUREUNIT_1: Capture unit 1
  • HRTIM_CAPTUREUNIT_2: Capture unit 2
SrcAddr,: DMA transfer source address
DestAddr,: DMA transfer destination address
Length,: The length of data items (data size) to be transferred from source to destination
Return values:
HAL status

Definition at line 2517 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_ENABLE, __HAL_HRTIM_TIMER_ENABLE_DMA, assert_param, HRTIM_TimerParamTypeDef::CaptureTrigger1, HRTIM_TimerParamTypeDef::CaptureTrigger2, HAL_DMA_Start_IT(), HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_CAPTUREUNIT_1, HRTIM_CAPTUREUNIT_2, HRTIM_DMAError(), HRTIM_DMATimerxCplt(), HRTIM_GetDMAHandleFromTimerIdx(), HRTIM_TIM_DMA_CPT1, HRTIM_TIM_DMA_CPT2, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_CAPTUREUNIT, IS_HRTIM_TIMING_UNIT, __HRTIM_HandleTypeDef::State, TimerIdxToTimerId, __HRTIM_HandleTypeDef::TimerParam, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | CaptureChannel
 | ) |  |

Enables a basic capture on the designed capture unit (Capture interrupt is enabled).

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
CaptureChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_CAPTUREUNIT_1: Capture unit 1
  • HRTIM_CAPTUREUNIT_2: Capture unit 2
Return values:
HAL status

Definition at line 2385 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_ENABLE, __HAL_HRTIM_TIMER_ENABLE_IT, assert_param, HRTIM_TimerParamTypeDef::CaptureTrigger1, HRTIM_TimerParamTypeDef::CaptureTrigger2, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_CAPTUREUNIT_1, HRTIM_CAPTUREUNIT_2, HRTIM_TIM_IT_CPT1, HRTIM_TIM_IT_CPT2, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_CAPTUREUNIT, IS_HRTIM_TIMING_UNIT, __HRTIM_HandleTypeDef::State, TimerIdxToTimerId, and __HRTIM_HandleTypeDef::TimerParam.

HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | CaptureChannel
 | ) |  |

Disables a simple capture on the designed capture unit.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
CaptureChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_CAPTUREUNIT_1: Capture unit 1
  • HRTIM_CAPTUREUNIT_2: Capture unit 2
Return values:
HAL status

Definition at line 2325 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_DISABLE, assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_CAPTURETRIGGER_NONE, HRTIM_CAPTUREUNIT_1, HRTIM_CAPTUREUNIT_2, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_CAPTUREUNIT, IS_HRTIM_TIMING_UNIT, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | CaptureChannel
 | ) |  |

Disables a basic capture on the designed capture unit (Capture DMA request is disabled).

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
CaptureChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_CAPTUREUNIT_1: Capture unit 1
  • HRTIM_CAPTUREUNIT_2: Capture unit 2
Return values:
HAL status

Definition at line 2596 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_DISABLE, __HAL_HRTIM_TIMER_DISABLE_DMA, assert_param, HAL_DMA_Abort(), HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_CAPTURETRIGGER_NONE, HRTIM_CAPTUREUNIT_1, HRTIM_CAPTUREUNIT_2, HRTIM_GetDMAHandleFromTimerIdx(), HRTIM_TIM_DMA_CPT1, HRTIM_TIM_DMA_CPT2, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_CAPTUREUNIT, IS_HRTIM_TIMING_UNIT, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | CaptureChannel
 | ) |  |

Disables a basic capture on the designed capture unit (Capture interrupt is disabled).

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
CaptureChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_CAPTUREUNIT_1: Capture unit 1
  • HRTIM_CAPTUREUNIT_2: Capture unit 2
Return values:
HAL status

Definition at line 2447 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_DISABLE, __HAL_HRTIM_TIMER_DISABLE_IT, assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_CAPTURETRIGGER_NONE, HRTIM_CAPTUREUNIT_1, HRTIM_CAPTUREUNIT_2, HRTIM_TIM_IT_CPT1, HRTIM_TIM_IT_CPT2, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_CAPTUREUNIT, IS_HRTIM_TIMING_UNIT, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Simple one pulse functions

Functions
Simple one pulse functions
HRTIM Exported Functions

Simple one pulse functions. More...

Functions

HAL_StatusTypeDef | HAL_HRTIM_SimpleOnePulseChannelConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel, HRTIM_SimpleOnePulseChannelCfgTypeDef *pSimpleOnePulseChannelCfg)
Configures an output simple one pulse mode.
HAL_StatusTypeDef | HAL_HRTIM_SimpleOnePulseStart (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel)
Enables the simple one pulse signal generation on the designed output.
HAL_StatusTypeDef | HAL_HRTIM_SimpleOnePulseStop (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel)
Disables the simple one pulse signal generation on the designed output.
HAL_StatusTypeDef | HAL_HRTIM_SimpleOnePulseStart_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel)
Enables the simple one pulse signal generation on the designed output (The compare interrupt is enabled (pulse start)).
HAL_StatusTypeDef | HAL_HRTIM_SimpleOnePulseStop_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel)
Disables the simple one pulse signal generation on the designed output (The compare interrupt is disabled).

Detailed Description

Simple one pulse functions.

 ===============================================================================
              ##### Simple one pulse functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure one pulse channel
      (+) Start one pulse generation
      (+) Stop one pulse generation
      (+) Start one pulse generation and enable interrupt
      (+) Stop one pulse generation and disable interrupt
      -@- When a HRTIM timer operates in simple one pulse mode
          the timer counter is started in response to transition detected
          on a given external event input to generate a pulse with a
          programmable length after a programmable delay.

Function Documentation

HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | OnePulseChannel,
 |  | HRTIM_SimpleOnePulseChannelCfgTypeDef * | pSimpleOnePulseChannelCfg
 | ) |  |

Configures an output simple one pulse mode.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
OnePulseChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
pSimpleOnePulseChannelCfg,: pointer to the basic one pulse output configuration structure
Note:
When the timer operates in basic one pulse mode: the timer counter is implicitely started by the reset event, the reset of the timer counter is triggered by the designated external event GPIO input is implicitly used as event source, Output 1 is implicitly controlled by the compare unit 1, Output 2 is implicitly controlled by the compare unit 2. Output Set/Reset crossbar is set as follows: Output 1: SETx1R = CMP1, RSTx1R = PER Output 2: SETx2R = CMP2, RST2R = PER
Return values:
HAL status
Note:
If HAL_HRTIM_SimpleOnePulseChannelConfig is called for both timer outputs, the reset event related configuration data provided in the second call will override the reset event related configuration data provided in the first call.

Definition at line 2718 of file stm32h7xx_hal_hrtim.c.

References assert_param, HRTIM_CompareCfgTypeDef::AutoDelayedMode, HRTIM_CompareCfgTypeDef::AutoDelayedTimeout, HRTIM_OutputCfgTypeDef::BurstModeEntryDelayed, HRTIM_OutputCfgTypeDef::ChopperModeEnable, HRTIM_CompareCfgTypeDef::CompareValue, HRTIM_SimpleOnePulseChannelCfgTypeDef::Event, HRTIM_SimpleOnePulseChannelCfgTypeDef::EventFilter, HRTIM_SimpleOnePulseChannelCfgTypeDef::EventPolarity, HRTIM_SimpleOnePulseChannelCfgTypeDef::EventSensitivity, HRTIM_EventCfgTypeDef::FastMode, HRTIM_OutputCfgTypeDef::FaultLevel, HRTIM_EventCfgTypeDef::Filter, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_AUTODELAYEDMODE_REGULAR, HRTIM_COMPAREUNIT_1, HRTIM_COMPAREUNIT_2, HRTIM_CompareUnitConfig(), HRTIM_EventConfig(), HRTIM_EVENTFASTMODE_DISABLE, HRTIM_EVENTSRC_1, HRTIM_OUTPUT_TA1, HRTIM_OUTPUT_TA2, HRTIM_OUTPUT_TB1, HRTIM_OUTPUT_TB2, HRTIM_OUTPUT_TC1, HRTIM_OUTPUT_TC2, HRTIM_OUTPUT_TD1, HRTIM_OUTPUT_TD2, HRTIM_OUTPUT_TE1, HRTIM_OUTPUT_TE2, HRTIM_OUTPUTBURSTMODEENTRY_REGULAR, HRTIM_OUTPUTCHOPPERMODE_DISABLED, HRTIM_OutputConfig(), HRTIM_OUTPUTFAULTLEVEL_NONE, HRTIM_OUTPUTIDLEMODE_NONE, HRTIM_OUTPUTSET_TIMCMP1, HRTIM_OUTPUTSET_TIMCMP2, HRTIM_OUTPUTSET_TIMPER, HRTIM_TIM_ResetConfig(), HRTIM_OutputCfgTypeDef::IdleLevel, HRTIM_OutputCfgTypeDef::IdleMode, IS_HRTIM_EVENT, IS_HRTIM_EVENTFILTER, IS_HRTIM_EVENTPOLARITY, IS_HRTIM_EVENTSENSITIVITY, IS_HRTIM_OUTPUTIDLELEVEL, IS_HRTIM_OUTPUTPOLARITY, IS_HRTIM_TIMER_OUTPUT, HRTIM_SimpleOnePulseChannelCfgTypeDef::OutputIdleLevel, HRTIM_SimpleOnePulseChannelCfgTypeDef::OutputPolarity, HRTIM_OutputCfgTypeDef::Polarity, HRTIM_EventCfgTypeDef::Polarity, HRTIM_SimpleOnePulseChannelCfgTypeDef::Pulse, HRTIM_OutputCfgTypeDef::ResetSource, HRTIM_EventCfgTypeDef::Sensitivity, HRTIM_OutputCfgTypeDef::SetSource, HRTIM_EventCfgTypeDef::Source, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | OnePulseChannel
 | ) |  |

Enables the simple one pulse signal generation on the designed output.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
OnePulseChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
Return values:
HAL status

Definition at line 2852 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_ENABLE, assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMER_OUTPUT, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | OnePulseChannel
 | ) |  |

Enables the simple one pulse signal generation on the designed output (The compare interrupt is enabled (pulse start)).

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
OnePulseChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
Return values:
HAL status

Definition at line 2953 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_ENABLE, __HAL_HRTIM_TIMER_ENABLE_IT, assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_OUTPUT_TA1, HRTIM_OUTPUT_TA2, HRTIM_OUTPUT_TB1, HRTIM_OUTPUT_TB2, HRTIM_OUTPUT_TC1, HRTIM_OUTPUT_TC2, HRTIM_OUTPUT_TD1, HRTIM_OUTPUT_TD2, HRTIM_OUTPUT_TE1, HRTIM_OUTPUT_TE2, HRTIM_TIM_IT_CMP1, HRTIM_TIM_IT_CMP2, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMER_OUTPUT, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | OnePulseChannel
 | ) |  |

Disables the simple one pulse signal generation on the designed output.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
OnePulseChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
Return values:
HAL status

Definition at line 2902 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_DISABLE, assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMER_OUTPUT, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | OnePulseChannel
 | ) |  |

Disables the simple one pulse signal generation on the designed output (The compare interrupt is disabled).

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
OnePulseChannel,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
Return values:
HAL status

Definition at line 3027 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_DISABLE, __HAL_HRTIM_TIMER_DISABLE_IT, assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_OUTPUT_TA1, HRTIM_OUTPUT_TA2, HRTIM_OUTPUT_TB1, HRTIM_OUTPUT_TB2, HRTIM_OUTPUT_TC1, HRTIM_OUTPUT_TC2, HRTIM_OUTPUT_TD1, HRTIM_OUTPUT_TD2, HRTIM_OUTPUT_TE1, HRTIM_OUTPUT_TE2, HRTIM_TIM_IT_CMP1, HRTIM_TIM_IT_CMP2, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMER_OUTPUT, __HRTIM_HandleTypeDef::State, and TimerIdxToTimerId.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Configuration functions

Functions
Configuration functions
HRTIM Exported Functions

HRTIM configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_HRTIM_BurstModeConfig (HRTIM_HandleTypeDef *hhrtim, HRTIM_BurstModeCfgTypeDef *pBurstModeCfg)
Configures the burst mode feature of the HRTIM.
HAL_StatusTypeDef | HAL_HRTIM_EventConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t Event, HRTIM_EventCfgTypeDef *pEventCfg)
Configures the conditioning of an external event.
HAL_StatusTypeDef | HAL_HRTIM_EventPrescalerConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler)
Configures the external event conditioning block prescaler.
HAL_StatusTypeDef | HAL_HRTIM_FaultConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t Fault, HRTIM_FaultCfgTypeDef *pFaultCfg)
Configures the conditioning of fault input.
HAL_StatusTypeDef | HAL_HRTIM_FaultPrescalerConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler)
Configures the fault conditioning block prescaler.
void | HAL_HRTIM_FaultModeCtl (HRTIM_HandleTypeDef *hhrtim, uint32_t Faults, uint32_t Enable)
Enables or disables the HRTIMx Fault mode.
HAL_StatusTypeDef | HAL_HRTIM_ADCTriggerConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t ADCTrigger, HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg)
Configures both the ADC trigger register update source and the ADC trigger source.

Detailed Description

HRTIM configuration functions.

 ===============================================================================
              ##### HRTIM configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to configure the HRTIM
      resources shared by all the HRTIM timers operating in waveform mode:
      (+) Configure the burst mode controller
      (+) Configure an external event conditionning
      (+) Configure the external events sampling clock
      (+) Configure a fault conditionning
      (+) Enable or disable fault inputs
      (+) Configure the faults sampling clock
      (+) Configure an ADC trigger

Function Documentation

HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | ADCTrigger,
 |  | HRTIM_ADCTriggerCfgTypeDef * | pADCTriggerCfg
 | ) |  |

Configures both the ADC trigger register update source and the ADC trigger source.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
ADCTrigger,: ADC trigger to configure This parameter can be one of the following values:
  • HRTIM_ADCTRIGGER_1: ADC trigger 1
  • HRTIM_ADCTRIGGER_2: ADC trigger 2
  • HRTIM_ADCTRIGGER_3: ADC trigger 3
  • HRTIM_ADCTRIGGER_4: ADC trigger 4
pADCTriggerCfg,: pointer to the ADC trigger configuration structure
Return values:
HAL status
Note:
This function must be called before starting the timer

Definition at line 3495 of file stm32h7xx_hal_hrtim.c.

References assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_ADCTRIGGER_1, HRTIM_ADCTRIGGER_2, HRTIM_ADCTRIGGER_3, HRTIM_ADCTRIGGER_4, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_ADCTRIGGER, IS_HRTIM_ADCTRIGGERUPDATE, __HRTIM_HandleTypeDef::State, HRTIM_ADCTriggerCfgTypeDef::Trigger, and HRTIM_ADCTriggerCfgTypeDef::UpdateSource.

HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | HRTIM_BurstModeCfgTypeDef * | pBurstModeCfg
 | ) |  |

Configures the burst mode feature of the HRTIM.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
pBurstModeCfg,: pointer to the burst mode configuration structure
Return values:
HAL status
Note:
This function must be called before starting the burst mode controller

Definition at line 3109 of file stm32h7xx_hal_hrtim.c.

References assert_param, HRTIM_BurstModeCfgTypeDef::ClockSource, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_BurstModeCfgTypeDef::IdleDuration, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_BURSTMODE, IS_HRTIM_BURSTMODECLOCKSOURCE, IS_HRTIM_BURSTMODEPRELOAD, IS_HRTIM_BURSTMODETRIGGER, IS_HRTIM_HRTIM_BURSTMODEPRESCALER, HRTIM_BurstModeCfgTypeDef::Mode, HRTIM_BurstModeCfgTypeDef::Period, HRTIM_BurstModeCfgTypeDef::PreloadEnable, HRTIM_BurstModeCfgTypeDef::Prescaler, __HRTIM_HandleTypeDef::State, and HRTIM_BurstModeCfgTypeDef::Trigger.

HAL_StatusTypeDef HAL_HRTIM_EventConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | Event,
 |  | HRTIM_EventCfgTypeDef * | pEventCfg
 | ) |  |

Configures the conditioning of an external event.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Event,: external event to configure This parameter can be one of the following values:
  • HRTIM_EVENT_1: External event 1
  • HRTIM_EVENT_2: External event 2
  • HRTIM_EVENT_3: External event 3
  • HRTIM_EVENT_4: External event 4
  • HRTIM_EVENT_5: External event 5
  • HRTIM_EVENT_6: External event 6
  • HRTIM_EVENT_7: External event 7
  • HRTIM_EVENT_8: External event 8
  • HRTIM_EVENT_9: External event 9
  • HRTIM_EVENT_10: External event 10
pEventCfg,: pointer to the event conditioning configuration structure
Note:
This function must be called before starting the timer
Return values:
HAL status

Definition at line 3188 of file stm32h7xx_hal_hrtim.c.

References assert_param, HRTIM_EventCfgTypeDef::FastMode, HRTIM_EventCfgTypeDef::Filter, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_EventConfig(), IS_HRTIM_EVENTFASTMODE, IS_HRTIM_EVENTFILTER, IS_HRTIM_EVENTPOLARITY, IS_HRTIM_EVENTSENSITIVITY, IS_HRTIM_EVENTSRC, HRTIM_EventCfgTypeDef::Polarity, HRTIM_EventCfgTypeDef::Sensitivity, HRTIM_EventCfgTypeDef::Source, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | Prescaler
 | ) |  |

Configures the external event conditioning block prescaler.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Prescaler,: Prescaler value This parameter can be one of the following values:
  • HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIM
  • HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIM / 2
  • HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIM / 4
  • HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIM / 8
Note:
This function must be called before starting the timer
Return values:
HAL status

Definition at line 3232 of file stm32h7xx_hal_hrtim.c.

References assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_EVENTPRESCALER, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_FaultConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | Fault,
 |  | HRTIM_FaultCfgTypeDef * | pFaultCfg
 | ) |  |

Configures the conditioning of fault input.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Fault,: fault input to configure This parameter can be one of the following values:
  • HRTIM_FAULT_1: Fault input 1
  • HRTIM_FAULT_2: Fault input 2
  • HRTIM_FAULT_3: Fault input 3
  • HRTIM_FAULT_4: Fault input 4
  • HRTIM_FAULT_5: Fault input 5
pFaultCfg,: pointer to the fault conditioning configuration structure
Note:
This function must be called before starting the timer and before enabling faults inputs
Return values:
HAL status

Definition at line 3281 of file stm32h7xx_hal_hrtim.c.

References assert_param, HRTIM_FaultCfgTypeDef::Filter, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_FAULT_1, HRTIM_FAULT_2, HRTIM_FAULT_3, HRTIM_FAULT_4, HRTIM_FAULT_5, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_FAULT, IS_HRTIM_FAULTFILTER, IS_HRTIM_FAULTLOCK, IS_HRTIM_FAULTPOLARITY, IS_HRTIM_FAULTSOURCE, HRTIM_FaultCfgTypeDef::Lock, HRTIM_FaultCfgTypeDef::Polarity, HRTIM_FaultCfgTypeDef::Source, and __HRTIM_HandleTypeDef::State.

void HAL_HRTIM_FaultModeCtl | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | Faults,
 |  | uint32_t | Enable
 | ) |  |

Enables or disables the HRTIMx Fault mode.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Faults,: fault input(s) to enable or disable This parameter can be any combination of the following values:
  • HRTIM_FAULT_1: Fault input 1
  • HRTIM_FAULT_2: Fault input 2
  • HRTIM_FAULT_3: Fault input 3
  • HRTIM_FAULT_4: Fault input 4
  • HRTIM_FAULT_5: Fault input 5
Enable,: Fault(s) enabling This parameter can be one of the following values:
  • HRTIM_FAULTMODECTL_ENABLED: Fault(s) enabled
  • HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled
Return values:
None

Definition at line 3435 of file stm32h7xx_hal_hrtim.c.

References assert_param, HRTIM_FAULT_1, HRTIM_FAULT_2, HRTIM_FAULT_3, HRTIM_FAULT_4, HRTIM_FAULT_5, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_FAULT, and IS_HRTIM_FAULTMODECTL.

HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | Prescaler
 | ) |  |

Configures the fault conditioning block prescaler.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Prescaler,: Prescaler value This parameter can be one of the following values:
  • HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIM
  • HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIM / 2
  • HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIM / 4
  • HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIM / 8
Return values:
HAL status
Note:
This function must be called before starting the timer and before enabling faults inputs

Definition at line 3385 of file stm32h7xx_hal_hrtim.c.

References assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_FAULTPRESCALER, and __HRTIM_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Timer waveform configuration and functions

Functions
Timer waveform configuration and functions
HRTIM Exported Functions

HRTIM timer configuration and control functions. More...

Functions

HAL_StatusTypeDef | HAL_HRTIM_WaveformTimerConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, HRTIM_TimerCfgTypeDef *pTimerCfg)
Configures the general behavior of a timer operating in waveform mode.
HAL_StatusTypeDef | HAL_HRTIM_TimerEventFilteringConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event, HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg)
Configures the event filtering capabilities of a timer (blanking, windowing)
HAL_StatusTypeDef | HAL_HRTIM_DeadTimeConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg)
Configures the deadtime insertion feature for a timer.
HAL_StatusTypeDef | HAL_HRTIM_ChopperModeConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg)
Configures the chopper mode feature for a timer.
HAL_StatusTypeDef | HAL_HRTIM_BurstDMAConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t RegistersToUpdate)
Configures the burst DMA controller for a timer.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCompareConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CompareUnit, HRTIM_CompareCfgTypeDef *pCompareCfg)
Configures the compare unit of a timer operating in waveform mode.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCaptureConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, HRTIM_CaptureCfgTypeDef *pCaptureCfg)
Configures the capture unit of a timer operating in waveform mode.
HAL_StatusTypeDef | HAL_HRTIM_WaveformOutputConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, HRTIM_OutputCfgTypeDef *pOutputCfg)
Configures the output of a timer operating in waveform mode.
HAL_StatusTypeDef | HAL_HRTIM_WaveformSetOutputLevel (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, uint32_t OutputLevel)
Forces the timer output to its active or inactive state.
HAL_StatusTypeDef | HAL_HRTIM_WaveformOutputStart (HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStart)
Enables the generation of the waveform signal on the designated output(s) Outputs can be combined (ORed) to allow for simultaneous output enabling.
HAL_StatusTypeDef | HAL_HRTIM_WaveformOutputStop (HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStop)
Disables the generation of the waveform signal on the designated output(s) Outputs can be combined (ORed) to allow for simultaneous output disabling.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCounterStart (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Starts the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter start.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCounterStop (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Stops the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter stop.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCounterStart_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Starts the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter start.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCounterStop_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Stops the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter stop.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCounterStart_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Starts the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter start.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCounterStop_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Stops the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter stop.
HAL_StatusTypeDef | HAL_HRTIM_BurstModeCtl (HRTIM_HandleTypeDef *hhrtim, uint32_t Enable)
Enables or disables the HRTIM burst mode controller.
HAL_StatusTypeDef | HAL_HRTIM_BurstModeSoftwareTrigger (HRTIM_HandleTypeDef *hhrtim)
Triggers the burst mode operation.
HAL_StatusTypeDef | HAL_HRTIM_SoftwareCapture (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit)
Triggers a software capture on the designed capture unit.
HAL_StatusTypeDef | HAL_HRTIM_SoftwareUpdate (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Triggers the update of the registers of one or several timers.
HAL_StatusTypeDef | HAL_HRTIM_SoftwareReset (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Triggers the reset of one or several timers.
HAL_StatusTypeDef | HAL_HRTIM_BurstDMATransfer (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t BurstBufferAddress, uint32_t BurstBufferLength)
Starts a burst DMA operation to update HRTIM control registers content.
HAL_StatusTypeDef | HAL_HRTIM_UpdateEnable (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Enables the transfer from preload to active registers for one or several timing units (including master timer).
HAL_StatusTypeDef | HAL_HRTIM_UpdateDisable (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Disables the transfer from preload to active registers for one or several timing units (including master timer).

Detailed Description

HRTIM timer configuration and control functions.

 ===============================================================================
              ##### HRTIM timer configuration and control functions #####
 ===============================================================================
    [..]  This section provides functions used to configure and control a
        HRTIM timer operating in waveform mode:
      (+) Configure HRTIM timer general behavior
      (+) Configure HRTIM timer event filtering
      (+) Configure HRTIM timer deadtime insertion
      (+) Configure HRTIM timer chopper mode
      (+) Configure HRTIM timer burst DMA
      (+) Configure HRTIM timer compare unit
      (+) Configure HRTIM timer capture unit
      (+) Configure HRTIM timer output
      (+) Set HRTIM timer output level
      (+) Enable HRTIM timer output
      (+) Disable HRTIM timer output
      (+) Start HRTIM timer
      (+) Stop HRTIM timer
      (+) Start HRTIM timer and enable interrupt
      (+) Stop HRTIM timer and disable interrupt
      (+) Start HRTIM timer and enable DMA transfer
      (+) Stop HRTIM timer and disable DMA transfer
      (+) Enable or disable the burst mode controller
      (+) Start the burst mode controller (by software)
      (+) Trigger a Capture (by software)
      (+) Update the HRTIM timer preloadable registers (by software)
      (+) Reset the HRTIM timer counter (by software)
      (+) Start a burst DMA transfer
      (+) Enable timer register update
      (+) Disable timer register update

Function Documentation

HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | RegistersToUpdate
 | ) |  |

Configures the burst DMA controller for a timer.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_MASTER for master timer
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
RegistersToUpdate,: registers to be written by DMA This parameter can be any combination of the following values:
  • HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
  • HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
  • HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
  • HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
  • HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
  • HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
  • HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
  • HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
  • HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
  • HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
  • HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
  • HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
  • HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
  • HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
  • HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
  • HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
  • HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
  • HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
  • HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
  • HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
  • HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
Return values:
HAL status
Note:
This function must be called before starting the timer

Definition at line 4016 of file stm32h7xx_hal_hrtim.c.

References assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_TIMERINDEX_MASTER, HRTIM_TIMERINDEX_TIMER_A, HRTIM_TIMERINDEX_TIMER_B, HRTIM_TIMERINDEX_TIMER_C, HRTIM_TIMERINDEX_TIMER_D, HRTIM_TIMERINDEX_TIMER_E, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMER_BURSTDMA, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | BurstBufferAddress,
 |  | uint32_t | BurstBufferLength
 | ) |  |

Starts a burst DMA operation to update HRTIM control registers content.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_MASTER for master timer
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
BurstBufferAddress,: address of the buffer the HRTIM control registers content will be updated from.
BurstBufferLength,: size (in WORDS) of the burst buffer.
Return values:
HAL status
Note:
The TimerIdx parameter determines the dma channel to be used by the DMA burst controller (see below) HRTIM_TIMERINDEX_MASTER: DMA channel 2 is used by the DMA burst controller HRTIM_TIMERINDEX_TIMER_A: DMA channel 3 is used by the DMA burst controller HRTIM_TIMERINDEX_TIMER_B: DMA channel 4 is used by the DMA burst controller HRTIM_TIMERINDEX_TIMER_C: DMA channel 5 is used by the DMA burst controller HRTIM_TIMERINDEX_TIMER_D: DMA channel 6 is used by the DMA burst controller HRTIM_TIMERINDEX_TIMER_E: DMA channel 7 is used by the DMA burst controller

Definition at line 5141 of file stm32h7xx_hal_hrtim.c.

References assert_param, HAL_DMA_Start_IT(), HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_BurstDMACplt(), HRTIM_DMAError(), HRTIM_GetDMAHandleFromTimerIdx(), __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMERINDEX, __HRTIM_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | Enable
 | ) |  |

Enables or disables the HRTIM burst mode controller.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Enable,: Burst mode controller enabling This parameter can be one of the following values:
  • HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
  • HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
Return values:
HAL status
Note:
This function must be called after starting the timer(s)

Definition at line 4912 of file stm32h7xx_hal_hrtim.c.

References assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_BURSTMODECTL, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger ( HRTIM_HandleTypeDef * hhrtim )

Triggers the burst mode operation.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Return values:
HAL status

Definition at line 4951 of file stm32h7xx_hal_hrtim.c.

References HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::Instance, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | HRTIM_ChopperModeCfgTypeDef * | pChopperModeCfg
 | ) |  |

Configures the chopper mode feature for a timer.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
pChopperModeCfg,: pointer to the chopper mode configuration structure
Return values:
HAL status
Note:
This function must be called before configuring the timer output(s)

Definition at line 3936 of file stm32h7xx_hal_hrtim.c.

References assert_param, HRTIM_ChopperModeCfgTypeDef::CarrierFreq, HRTIM_ChopperModeCfgTypeDef::DutyCycle, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_CHOPPER_DUTYCYCLE, IS_HRTIM_CHOPPER_PRESCALERRATIO, IS_HRTIM_CHOPPER_PULSEWIDTH, IS_HRTIM_TIMING_UNIT, HRTIM_ChopperModeCfgTypeDef::StartPulse, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | HRTIM_DeadTimeCfgTypeDef * | pDeadTimeCfg
 | ) |  |

Configures the deadtime insertion feature for a timer.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
pDeadTimeCfg,: pointer to the deadtime insertion configuration structure
Return values:
HAL status
Note:
This function must be called before starting the timer

Definition at line 3867 of file stm32h7xx_hal_hrtim.c.

References assert_param, HRTIM_DeadTimeCfgTypeDef::FallingLock, HRTIM_DeadTimeCfgTypeDef::FallingSign, HRTIM_DeadTimeCfgTypeDef::FallingSignLock, HRTIM_DeadTimeCfgTypeDef::FallingValue, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMDEADTIME_FALLINGLOCK, IS_HRTIM_TIMDEADTIME_FALLINGSIGN, IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK, IS_HRTIM_TIMDEADTIME_PRESCALERRATIO, IS_HRTIM_TIMDEADTIME_RISINGLOCK, IS_HRTIM_TIMDEADTIME_RISINGSIGN, IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK, IS_HRTIM_TIMING_UNIT, HRTIM_DeadTimeCfgTypeDef::Prescaler, HRTIM_DeadTimeCfgTypeDef::RisingLock, HRTIM_DeadTimeCfgTypeDef::RisingSign, HRTIM_DeadTimeCfgTypeDef::RisingSignLock, HRTIM_DeadTimeCfgTypeDef::RisingValue, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | CaptureUnit
 | ) |  |

Triggers a software capture on the designed capture unit.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
CaptureUnit,: Capture unit to trig This parameter can be one of the following values:
  • HRTIM_CAPTUREUNIT_1: Capture unit 1
  • HRTIM_CAPTUREUNIT_2: Capture unit 2
Return values:
HAL status
Note:
The 'software capture' bit in the capure configuration register is automatically reset by hardware

Definition at line 4992 of file stm32h7xx_hal_hrtim.c.

References assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_CAPTUREUNIT_1, HRTIM_CAPTUREUNIT_2, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_CAPTUREUNIT, IS_HRTIM_TIMING_UNIT, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_SoftwareReset | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | Timers
 | ) |  |

Triggers the reset of one or several timers.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Timers,: timers concerned with the software counter reset This parameter can be any combination of the following values:
  • HRTIM_TIMERRESET_MASTER
  • HRTIM_TIMERRESET_TIMER_A
  • HRTIM_TIMERRESET_TIMER_B
  • HRTIM_TIMERRESET_TIMER_C
  • HRTIM_TIMERRESET_TIMER_D
  • HRTIM_TIMERRESET_TIMER_E
Return values:
HAL status
Note:
The 'software reset' bits in the HRTIM conrol register 2 are automatically reset by hardware

Definition at line 5090 of file stm32h7xx_hal_hrtim.c.

References assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMERRESET, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | Timers
 | ) |  |

Triggers the update of the registers of one or several timers.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Timers,: timers concerned with the software register update This parameter can be any combination of the following values:
  • HRTIM_TIMERUPDATE_MASTER
  • HRTIM_TIMERUPDATE_A
  • HRTIM_TIMERUPDATE_B
  • HRTIM_TIMERUPDATE_C
  • HRTIM_TIMERUPDATE_D
  • HRTIM_TIMERUPDATE_E
Return values:
HAL status
Note:
The 'software update' bits in the HRTIM conrol register 2 register are automatically reset by hardware

Definition at line 5048 of file stm32h7xx_hal_hrtim.c.

References assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMERUPDATE, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | Event,
 |  | HRTIM_TimerEventFilteringCfgTypeDef * | pTimerEventFilteringCfg
 | ) |  |

Configures the event filtering capabilities of a timer (blanking, windowing)

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Event,: external event for which timer event filtering must be configured This parameter can be one of the following values:
  • HRTIM_EVENT_NONE: Reset timer event filtering configuration
  • HRTIM_EVENT_1: External event 1
  • HRTIM_EVENT_2: External event 2
  • HRTIM_EVENT_3: External event 3
  • HRTIM_EVENT_4: External event 4
  • HRTIM_EVENT_5: External event 5
  • HRTIM_EVENT_6: External event 6
  • HRTIM_EVENT_7: External event 7
  • HRTIM_EVENT_8: External event 8
  • HRTIM_EVENT_9: External event 9
  • HRTIM_EVENT_10: External event 10
pTimerEventFilteringCfg,: pointer to the timer event filtering configuration structure
Note:
This function must be called before starting the timer
Return values:
HAL status

Definition at line 3731 of file stm32h7xx_hal_hrtim.c.

References assert_param, HRTIM_TimerEventFilteringCfgTypeDef::Filter, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_EVENT_1, HRTIM_EVENT_10, HRTIM_EVENT_2, HRTIM_EVENT_3, HRTIM_EVENT_4, HRTIM_EVENT_5, HRTIM_EVENT_6, HRTIM_EVENT_7, HRTIM_EVENT_8, HRTIM_EVENT_9, HRTIM_EVENT_NONE, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_EVENT, IS_HRTIM_TIMEVENTFILTER, IS_HRTIM_TIMEVENTLATCH, IS_HRTIM_TIMING_UNIT, HRTIM_TimerEventFilteringCfgTypeDef::Latch, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_UpdateDisable | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | Timers
 | ) |  |

Disables the transfer from preload to active registers for one or several timing units (including master timer).

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Timers,: Timer(s) concerned by the register preload disabling command This parameter can be any combination of the following values:
  • HRTIM_TIMERUPDATE_MASTER
  • HRTIM_TIMERUPDATE_A
  • HRTIM_TIMERUPDATE_B
  • HRTIM_TIMERUPDATE_C
  • HRTIM_TIMERUPDATE_D
  • HRTIM_TIMERUPDATE_E
Return values:
HAL status

Definition at line 5243 of file stm32h7xx_hal_hrtim.c.

References assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMERUPDATE, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_UpdateEnable | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | Timers
 | ) |  |

Enables the transfer from preload to active registers for one or several timing units (including master timer).

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Timers,: Timer(s) concerned by the register preload enabling command This parameter can be any combination of the following values:
  • HRTIM_TIMERUPDATE_MASTER
  • HRTIM_TIMERUPDATE_A
  • HRTIM_TIMERUPDATE_B
  • HRTIM_TIMERUPDATE_C
  • HRTIM_TIMERUPDATE_D
  • HRTIM_TIMERUPDATE_E
Return values:
HAL status

Definition at line 5207 of file stm32h7xx_hal_hrtim.c.

References assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMERUPDATE, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | CaptureUnit,
 |  | HRTIM_CaptureCfgTypeDef * | pCaptureCfg
 | ) |  |

Configures the capture unit of a timer operating in waveform mode.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
CaptureUnit,: Capture unit to configure This parameter can be one of the following values:
  • HRTIM_CAPTUREUNIT_1: Capture unit 1
  • HRTIM_CAPTUREUNIT_2: Capture unit 2
pCaptureCfg,: pointer to the compare unit configuration structure
Return values:
HAL status
Note:
This function must be called before starting the timer

Definition at line 4248 of file stm32h7xx_hal_hrtim.c.

References assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_CAPTUREUNIT_1, HRTIM_CAPTUREUNIT_2, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMER_CAPTURETRIGGER, __HRTIM_HandleTypeDef::State, and HRTIM_CaptureCfgTypeDef::Trigger.

HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | CompareUnit,
 |  | HRTIM_CompareCfgTypeDef * | pCompareCfg
 | ) |  |

Configures the compare unit of a timer operating in waveform mode.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_MASTER for master timer
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
CompareUnit,: Compare unit to configure This parameter can be one of the following values:
  • HRTIM_COMPAREUNIT_1: Compare unit 1
  • HRTIM_COMPAREUNIT_2: Compare unit 2
  • HRTIM_COMPAREUNIT_3: Compare unit 3
  • HRTIM_COMPAREUNIT_4: Compare unit 4
pCompareCfg,: pointer to the compare unit configuration structure
Note:
When auto delayed mode is required for compare unit 2 or compare unit 4, application has to configure separately the capture unit. Capture unit to configure in that case depends on the compare unit auto delayed mode is applied to (see below): Auto delayed on output compare 2: capture unit 1 must be configured Auto delayed on output compare 4: capture unit 2 must be configured
Return values:
HAL status
Note:
This function must be called before starting the timer

Definition at line 4103 of file stm32h7xx_hal_hrtim.c.

References assert_param, HRTIM_CompareCfgTypeDef::AutoDelayedMode, HRTIM_CompareCfgTypeDef::AutoDelayedTimeout, HRTIM_CompareCfgTypeDef::CompareValue, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1, HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3, HRTIM_AUTODELAYEDMODE_REGULAR, HRTIM_COMPAREUNIT_1, HRTIM_COMPAREUNIT_2, HRTIM_COMPAREUNIT_3, HRTIM_COMPAREUNIT_4, HRTIM_TIMERINDEX_MASTER, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE, IS_HRTIM_TIMERINDEX, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | Timers
 | ) |  |

Starts the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter start.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Timers,: Timer counter(s) to start This parameter can be any combination of the following values:
  • HRTIM_TIMERID_MASTER
  • HRTIM_TIMERID_TIMER_A
  • HRTIM_TIMERID_TIMER_B
  • HRTIM_TIMERID_TIMER_C
  • HRTIM_TIMERID_TIMER_D
  • HRTIM_TIMERID_TIMER_E
Return values:
HAL status

Definition at line 4546 of file stm32h7xx_hal_hrtim.c.

References assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMERID, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | Timers
 | ) |  |

Starts the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter start.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Timers,: Timer counter(s) to start This parameter can be any combination of the following values: HRTIM_TIMER_MASTER
  • HRTIM_TIMER_A
  • HRTIM_TIMER_B
  • HRTIM_TIMER_C
  • HRTIM_TIMER_D
  • HRTIM_TIMER_E
Return values:
HAL status
Note:
This function enables the dma request(s) mentionned in the timer configuration data structure for every timers to start.
The source memory address, the destination memory address and the size of each DMA transfer are specified at timer configuration time (see HAL_HRTIM_WaveformTimerConfig)

Definition at line 4757 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_ENABLE, __HAL_HRTIM_MASTER_ENABLE_DMA, __HAL_HRTIM_TIMER_ENABLE_DMA, assert_param, HRTIM_TimerParamTypeDef::DMADstAddress, HRTIM_TimerParamTypeDef::DMARequests, HRTIM_TimerParamTypeDef::DMASize, HRTIM_TimerParamTypeDef::DMASrcAddress, HAL_DMA_Start_IT(), HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::hdmaMaster, HRTIM_DMAError(), HRTIM_DMAMasterCplt(), HRTIM_DMATimerxCplt(), HRTIM_GetDMAHandleFromTimerIdx(), HRTIM_TIMERID_MASTER, HRTIM_TIMERINDEX_MASTER, HRTIM_TIMERINDEX_TIMER_A, IS_HRTIM_TIMERID, __HRTIM_HandleTypeDef::State, TimerIdxToTimerId, __HRTIM_HandleTypeDef::TimerParam, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | Timers
 | ) |  |

Starts the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter start.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Timers,: Timer counter(s) to start This parameter can be any combination of the following values:
  • HRTIM_TIMERID_MASTER
  • HRTIM_TIMERID_A
  • HRTIM_TIMERID_B
  • HRTIM_TIMERID_C
  • HRTIM_TIMERID_D
  • HRTIM_TIMERID_E
Note:
HRTIM interrupts (e.g. faults interrupts) and interrupts related to the timers to start are enabled within this function. Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig function.
Return values:
HAL status

Definition at line 4623 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_ENABLE_IT, __HAL_HRTIM_MASTER_ENABLE_IT, __HAL_HRTIM_TIMER_ENABLE_IT, assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_TIMERID_MASTER, HRTIM_TIMERINDEX_MASTER, HRTIM_TIMERINDEX_TIMER_A, HRTIM_InitTypeDef::HRTIMInterruptResquests, __HRTIM_HandleTypeDef::Init, __HRTIM_HandleTypeDef::Instance, HRTIM_TimerParamTypeDef::InterruptRequests, IS_HRTIM_TIMERID, __HRTIM_HandleTypeDef::State, TimerIdxToTimerId, and __HRTIM_HandleTypeDef::TimerParam.

HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | Timers
 | ) |  |

Stops the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter stop.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Timers,: Timer counter(s) to stop This parameter can be any combination of the following values:
  • HRTIM_TIMER_MASTER
  • HRTIM_TIMER_A
  • HRTIM_TIMER_B
  • HRTIM_TIMER_C
  • HRTIM_TIMER_D
  • HRTIM_TIMER_E
Return values:
HAL status
Note:
The counter of a timer is stopped only if all timer outputs are disabled

Definition at line 4583 of file stm32h7xx_hal_hrtim.c.

References assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_TIMERID, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | Timers
 | ) |  |

Stops the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter stop.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Timers,: Timer counter(s) to stop This parameter can be any combination of the following values:
  • HRTIM_TIMER_MASTER
  • HRTIM_TIMER_A
  • HRTIM_TIMER_B
  • HRTIM_TIMER_C
  • HRTIM_TIMER_D
  • HRTIM_TIMER_E
Return values:
HAL status
Note:
The counter of a timer is stopped only if all timer outputs are disabled
All enabled timer related DMA requests are disabled.

Definition at line 4852 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_DISABLE, __HAL_HRTIM_MASTER_DISABLE_DMA, __HAL_HRTIM_TIMER_DISABLE_DMA, assert_param, HRTIM_TimerParamTypeDef::DMARequests, HAL_DMA_Abort(), HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::hdmaMaster, HRTIM_GetDMAHandleFromTimerIdx(), HRTIM_TIMERID_MASTER, HRTIM_TIMERINDEX_MASTER, HRTIM_TIMERINDEX_TIMER_A, IS_HRTIM_TIMERID, __HRTIM_HandleTypeDef::State, TimerIdxToTimerId, and __HRTIM_HandleTypeDef::TimerParam.

HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | Timers
 | ) |  |

Stops the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter stop.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Timers,: Timer counter(s) to stop This parameter can be any combination of the following values:
  • HRTIM_TIMER_MASTER
  • HRTIM_TIMER_A
  • HRTIM_TIMER_B
  • HRTIM_TIMER_C
  • HRTIM_TIMER_D
  • HRTIM_TIMER_E
Return values:
HAL status
Note:
The counter of a timer is stopped only if all timer outputs are disabled
All enabled timer related interrupts are disabled.

Definition at line 4685 of file stm32h7xx_hal_hrtim.c.

References __HAL_HRTIM_DISABLE_IT, __HAL_HRTIM_MASTER_DISABLE_IT, __HAL_HRTIM_TIMER_DISABLE_IT, assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_TIMERID_MASTER, HRTIM_TIMERINDEX_MASTER, HRTIM_TIMERINDEX_TIMER_A, HRTIM_InitTypeDef::HRTIMInterruptResquests, __HRTIM_HandleTypeDef::Init, __HRTIM_HandleTypeDef::Instance, HRTIM_TimerParamTypeDef::InterruptRequests, IS_HRTIM_TIMERID, __HRTIM_HandleTypeDef::State, TimerIdxToTimerId, and __HRTIM_HandleTypeDef::TimerParam.

HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | Output,
 |  | HRTIM_OutputCfgTypeDef * | pOutputCfg
 | ) |  |

Configures the output of a timer operating in waveform mode.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Output,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
pOutputCfg,: pointer to the timer output configuration structure
Return values:
HAL status
Note:
This function must be called before configuring the timer and after configuring the deadtime insertion feature (if required).

Definition at line 4316 of file stm32h7xx_hal_hrtim.c.

References assert_param, HRTIM_OutputCfgTypeDef::BurstModeEntryDelayed, HRTIM_OutputCfgTypeDef::ChopperModeEnable, HRTIM_OutputCfgTypeDef::FaultLevel, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_OutputConfig(), HRTIM_OutputCfgTypeDef::IdleLevel, HRTIM_OutputCfgTypeDef::IdleMode, IS_HRTIM_OUTPUTBURSTMODEENTRY, IS_HRTIM_OUTPUTCHOPPERMODE, IS_HRTIM_OUTPUTFAULTLEVEL, IS_HRTIM_OUTPUTIDLELEVEL, IS_HRTIM_OUTPUTIDLEMODE, IS_HRTIM_OUTPUTPOLARITY, IS_HRTIM_TIMER_OUTPUT, HRTIM_OutputCfgTypeDef::Polarity, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | OutputsToStart
 | ) |  |

Enables the generation of the waveform signal on the designated output(s) Outputs can be combined (ORed) to allow for simultaneous output enabling.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
OutputsToStart,: Timer output(s) to enable This parameter can be any combination of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
Return values:
HAL status

Definition at line 4470 of file stm32h7xx_hal_hrtim.c.

References assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_OUTPUT, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | OutputsToStop
 | ) |  |

Disables the generation of the waveform signal on the designated output(s) Outputs can be combined (ORed) to allow for simultaneous output disabling.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
OutputsToStop,: Timer output(s) to disable This parameter can be any combination of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
Return values:
HAL status

Definition at line 4510 of file stm32h7xx_hal_hrtim.c.

References assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_OUTPUT, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | Output,
 |  | uint32_t | OutputLevel
 | ) |  |

Forces the timer output to its active or inactive state.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Output,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
OutputLevel,: indicates whether the output is forced to its active or inactive level This parameter can be one of the following values:
  • HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active level
  • HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive level
Return values:
HAL status
Note:
The 'software set/reset trigger' bit in the output set/reset registers is automatically reset by hardware

Definition at line 4384 of file stm32h7xx_hal_hrtim.c.

References assert_param, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_OUTPUT_TA1, HRTIM_OUTPUT_TA2, HRTIM_OUTPUT_TB1, HRTIM_OUTPUT_TB2, HRTIM_OUTPUT_TC1, HRTIM_OUTPUT_TC2, HRTIM_OUTPUT_TD1, HRTIM_OUTPUT_TD2, HRTIM_OUTPUT_TE1, HRTIM_OUTPUT_TE2, HRTIM_OUTPUTLEVEL_ACTIVE, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_OUTPUTLEVEL, IS_HRTIM_TIMER_OUTPUT, and __HRTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | HRTIM_TimerCfgTypeDef * | pTimerCfg
 | ) |  |

Configures the general behavior of a timer operating in waveform mode.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_MASTER for master timer
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
pTimerCfg,: pointer to the timer configuration structure
Note:
When the timer operates in waveform mode, all the features supported by the HRTIM are available without any limitation.
Return values:
HAL status
Note:
This function must be called before starting the timer

Definition at line 3629 of file stm32h7xx_hal_hrtim.c.

References assert_param, HRTIM_TimerCfgTypeDef::BurstMode, HRTIM_TimerCfgTypeDef::DACSynchro, HRTIM_TimerCfgTypeDef::DeadTimeInsertion, HRTIM_TimerCfgTypeDef::DelayedProtectionMode, HRTIM_TimerParamTypeDef::DMADstAddress, HRTIM_TimerCfgTypeDef::DMADstAddress, HRTIM_TimerParamTypeDef::DMARequests, HRTIM_TimerCfgTypeDef::DMARequests, HRTIM_TimerParamTypeDef::DMASize, HRTIM_TimerCfgTypeDef::DMASize, HRTIM_TimerParamTypeDef::DMASrcAddress, HRTIM_TimerCfgTypeDef::DMASrcAddress, HRTIM_TimerCfgTypeDef::FaultEnable, HRTIM_TimerCfgTypeDef::FaultLock, HAL_HRTIM_STATE_BUSY, HAL_HRTIM_STATE_READY, HRTIM_TimerCfgTypeDef::HalfModeEnable, HRTIM_ForceRegistersUpdate(), HRTIM_MasterWaveform_Config(), HRTIM_TIMERINDEX_MASTER, HRTIM_TimingUnitWaveform_Config(), HRTIM_TimerParamTypeDef::InterruptRequests, HRTIM_TimerCfgTypeDef::InterruptRequests, IS_HHRTIM_DACSYNC, IS_HRTIM_HALFMODE, IS_HRTIM_MASTER_DMA, IS_HRTIM_MASTER_IT, IS_HRTIM_PRELOAD, IS_HRTIM_SYNCRESET, IS_HRTIM_SYNCSTART, IS_HRTIM_TIM_DMA, IS_HRTIM_TIM_IT, IS_HRTIM_TIMDEADTIMEINSERTION, IS_HRTIM_TIMDELAYEDPROTECTION, IS_HRTIM_TIMERBURSTMODE, IS_HRTIM_TIMERINDEX, IS_HRTIM_TIMFAULTENABLE, IS_HRTIM_TIMFAULTLOCK, IS_HRTIM_TIMPUSHPULLMODE, IS_HRTIM_TIMRESETTRIGGER, IS_HRTIM_TIMUPDATEONRESET, IS_HRTIM_TIMUPDATETRIGGER, IS_HRTIM_UPDATEGATING_MASTER, IS_HRTIM_UPDATEGATING_TIM, IS_HRTIM_UPDATEONREPETITION, HRTIM_TimerCfgTypeDef::PreloadEnable, HRTIM_TimerCfgTypeDef::PushPull, HRTIM_TimerCfgTypeDef::RepetitionUpdate, HRTIM_TimerCfgTypeDef::ResetOnSync, HRTIM_TimerCfgTypeDef::ResetTrigger, HRTIM_TimerCfgTypeDef::ResetUpdate, HRTIM_TimerCfgTypeDef::StartOnSync, __HRTIM_HandleTypeDef::State, __HRTIM_HandleTypeDef::TimerParam, HRTIM_TimerCfgTypeDef::UpdateGating, and HRTIM_TimerCfgTypeDef::UpdateTrigger.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral state functions

Functions
Peripheral state functions
HRTIM Exported Functions

Peripheral State functions. More...

Functions

HAL_HRTIM_StateTypeDef | HAL_HRTIM_GetState (HRTIM_HandleTypeDef *hhrtim)
return the HRTIM HAL state
uint32_t | HAL_HRTIM_GetCapturedValue (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit)
Returns actual value of the capture register of the designated capture unit.
uint32_t | HAL_HRTIM_WaveformGetOutputLevel (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output)
Returns actual level (active or inactive) of the designated output.
uint32_t | HAL_HRTIM_WaveformGetOutputState (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output)
Returns actual state (RUN, IDLE, FAULT) of the designated output.
uint32_t | HAL_HRTIM_GetDelayedProtectionStatus (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output)
Returns the level (active or inactive) of the designated output when the delayed protection was triggered.
uint32_t | HAL_HRTIM_GetBurstStatus (HRTIM_HandleTypeDef *hhrtim)
Returns the actual status (active or inactive) of the burst mode controller.
uint32_t | HAL_HRTIM_GetCurrentPushPullStatus (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Indicates on which output the signal is currently active (when the push pull mode is enabled).
uint32_t | HAL_HRTIM_GetIdlePushPullStatus (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Indicates on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered.

Detailed Description

Peripheral State functions.

 ===============================================================================
              ##### Peripheral State functions #####
 ===============================================================================
    [..]  This section provides functions used to get HRTIM or HRTIM timer
          specific information:
      (+) Get HRTIM HAL state
      (+) Get captured value
      (+) Get HRTIM timer output level
      (+) Get HRTIM timer output state
      (+) Get delayed protection status
      (+) Get burst status
      (+) Get current push-pull status
      (+) Get idle push-pull status

Function Documentation

uint32_t HAL_HRTIM_GetBurstStatus ( HRTIM_HandleTypeDef * hhrtim )

Returns the actual status (active or inactive) of the burst mode controller.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Return values:
Burst mode controller status

Definition at line 5615 of file stm32h7xx_hal_hrtim.c.

References __HRTIM_HandleTypeDef::Instance.

uint32_t HAL_HRTIM_GetCapturedValue | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | CaptureUnit
 | ) |  |

Returns actual value of the capture register of the designated capture unit.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
CaptureUnit,: Capture unit to trig This parameter can be one of the following values:
  • HRTIM_CAPTUREUNIT_1: Capture unit 1
  • HRTIM_CAPTUREUNIT_2: Capture unit 2
Return values:
Captured value

Definition at line 5318 of file stm32h7xx_hal_hrtim.c.

References assert_param, HRTIM_CAPTUREUNIT_1, HRTIM_CAPTUREUNIT_2, __HRTIM_HandleTypeDef::Instance, IS_HRTIM_CAPTUREUNIT, and IS_HRTIM_TIMING_UNIT.

uint32_t HAL_HRTIM_GetCurrentPushPullStatus | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Indicates on which output the signal is currently active (when the push pull mode is enabled).

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
Burst mode controller status

Definition at line 5638 of file stm32h7xx_hal_hrtim.c.

References assert_param, __HRTIM_HandleTypeDef::Instance, and IS_HRTIM_TIMING_UNIT.

uint32_t HAL_HRTIM_GetDelayedProtectionStatus | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | Output
 | ) |  |

Returns the level (active or inactive) of the designated output when the delayed protection was triggered.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Output,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TD1: Timer E - Output 1
  • HRTIM_OUTPUT_TD2: Timer E - Output 2
Return values:
Delayed protection status

Definition at line 5557 of file stm32h7xx_hal_hrtim.c.

References assert_param, HRTIM_OUTPUT_TA1, HRTIM_OUTPUT_TA2, HRTIM_OUTPUT_TB1, HRTIM_OUTPUT_TB2, HRTIM_OUTPUT_TC1, HRTIM_OUTPUT_TC2, HRTIM_OUTPUT_TD1, HRTIM_OUTPUT_TD2, HRTIM_OUTPUT_TE1, HRTIM_OUTPUT_TE2, HRTIM_OUTPUTLEVEL_ACTIVE, HRTIM_OUTPUTLEVEL_INACTIVE, __HRTIM_HandleTypeDef::Instance, and IS_HRTIM_TIMER_OUTPUT.

uint32_t HAL_HRTIM_GetIdlePushPullStatus | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Indicates on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
Idle Push Pull Status

Definition at line 5666 of file stm32h7xx_hal_hrtim.c.

References assert_param, __HRTIM_HandleTypeDef::Instance, and IS_HRTIM_TIMING_UNIT.

HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState ( HRTIM_HandleTypeDef * hhrtim )

return the HRTIM HAL state

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Return values:
HAL state

Definition at line 5296 of file stm32h7xx_hal_hrtim.c.

References __HRTIM_HandleTypeDef::State.

uint32_t HAL_HRTIM_WaveformGetOutputLevel | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | Output
 | ) |  |

Returns actual level (active or inactive) of the designated output.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Output,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
Return values:
Output level
Note:
Returned output level is taken before the output stage (chopper, polarity).

Definition at line 5372 of file stm32h7xx_hal_hrtim.c.

References assert_param, HRTIM_OUTPUT_TA1, HRTIM_OUTPUT_TA2, HRTIM_OUTPUT_TB1, HRTIM_OUTPUT_TB2, HRTIM_OUTPUT_TC1, HRTIM_OUTPUT_TC2, HRTIM_OUTPUT_TD1, HRTIM_OUTPUT_TD2, HRTIM_OUTPUT_TE1, HRTIM_OUTPUT_TE2, HRTIM_OUTPUTLEVEL_ACTIVE, HRTIM_OUTPUTLEVEL_INACTIVE, __HRTIM_HandleTypeDef::Instance, and IS_HRTIM_TIMER_OUTPUT.

uint32_t HAL_HRTIM_WaveformGetOutputState | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx,
 |  | uint32_t | Output
 | ) |  |

Returns actual state (RUN, IDLE, FAULT) of the designated output.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Output,: Timer output This parameter can be one of the following values:
  • HRTIM_OUTPUT_TA1: Timer A - Output 1
  • HRTIM_OUTPUT_TA2: Timer A - Output 2
  • HRTIM_OUTPUT_TB1: Timer B - Output 1
  • HRTIM_OUTPUT_TB2: Timer B - Output 2
  • HRTIM_OUTPUT_TC1: Timer C - Output 1
  • HRTIM_OUTPUT_TC2: Timer C - Output 2
  • HRTIM_OUTPUT_TD1: Timer D - Output 1
  • HRTIM_OUTPUT_TD2: Timer D - Output 2
  • HRTIM_OUTPUT_TE1: Timer E - Output 1
  • HRTIM_OUTPUT_TE2: Timer E - Output 2
Return values:
Output state

Definition at line 5445 of file stm32h7xx_hal_hrtim.c.

References assert_param, HRTIM_OUTPUT_TA1, HRTIM_OUTPUT_TA2, HRTIM_OUTPUT_TB1, HRTIM_OUTPUT_TB2, HRTIM_OUTPUT_TC1, HRTIM_OUTPUT_TC2, HRTIM_OUTPUT_TD1, HRTIM_OUTPUT_TD2, HRTIM_OUTPUT_TE1, HRTIM_OUTPUT_TE2, HRTIM_OUTPUTSTATE_FAULT, HRTIM_OUTPUTSTATE_IDLE, HRTIM_OUTPUTSTATE_RUN, __HRTIM_HandleTypeDef::Instance, and IS_HRTIM_TIMER_OUTPUT.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Interrupts handling

Functions
Interrupts handling
HRTIM Exported Functions

Functions called when HRTIM generates an interrupt 7 interrupts can be generated by the master timer: More...

Functions

void | HAL_HRTIM_IRQHandler (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
This function handles HRTIM interrupt request.
__weak void | HAL_HRTIM_Fault1Callback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a fault 1 interrupt occured.
__weak void | HAL_HRTIM_Fault2Callback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a fault 2 interrupt occured.
__weak void | HAL_HRTIM_Fault3Callback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a fault 3 interrupt occured.
__weak void | HAL_HRTIM_Fault4Callback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a fault 4 interrupt occured.
__weak void | HAL_HRTIM_Fault5Callback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a fault 5 interrupt occured.
__weak void | HAL_HRTIM_SystemFaultCallback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a system fault interrupt occured.
__weak void | HAL_HRTIM_BurstModePeriodCallback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when the end of the burst mode period is reached.
__weak void | HAL_HRTIM_SynchronizationEventCallback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a synchronization input event is received.
__weak void | HAL_HRTIM_RegistersUpdateCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when timer registers are updated.
__weak void | HAL_HRTIM_RepetitionEventCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when timer repetition period has elapsed.
__weak void | HAL_HRTIM_Compare1EventCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer counter matches the value programmed in the compare 1 register.
__weak void | HAL_HRTIM_Compare2EventCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer counter matches the value programmed in the compare 2 register.
__weak void | HAL_HRTIM_Compare3EventCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer counter matches the value programmed in the compare 3 register.
__weak void | HAL_HRTIM_Compare4EventCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer counter matches the value programmed in the compare 4 register.
__weak void | HAL_HRTIM_Capture1EventCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer x capture 1 event occurs.
__weak void | HAL_HRTIM_Capture2EventCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer x capture 2 event occurs.
__weak void | HAL_HRTIM_DelayedProtectionCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the delayed idle or balanced idle mode is entered.
__weak void | HAL_HRTIM_CounterResetCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer x counter reset/roll-over event occurs.
__weak void | HAL_HRTIM_Output1SetCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer x output 1 is set.
__weak void | HAL_HRTIM_Output1ResetCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer x output 1 is reset.
__weak void | HAL_HRTIM_Output2SetCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer x output 2 is set.
__weak void | HAL_HRTIM_Output2ResetCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer x output 2 is reset.
__weak void | HAL_HRTIM_BurstDMATransferCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when a DMA burst transfer is completed.
__weak void | HAL_HRTIM_ErrorCallback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a DMA error occurs.

Detailed Description

Functions called when HRTIM generates an interrupt 7 interrupts can be generated by the master timer:

  • Master timer registers update
  • Synchronization event received
  • Master timer repetition event
  • Master Compare 1 to 4 event 14 interrupts can be generated by each timing unit:
  • Delayed protection triggered
  • Counter reset or roll-over event
  • Output 1 and output 2 reset (transition active to inactive)
  • Output 1 and output 2 set (transition inactive to active)
  • Capture 1 and 2 events
  • Timing unit registers update
  • Repetition event
  • Compare 1 to 4 event 8 global interrupts are generated for the whole HRTIM:
  • System fault and Fault 1 to 5 (regardless of the timing unit attribution)
  • Burst mode period completed
 ===============================================================================
                      ##### HRTIM interrupts handling #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the HRTIM
    interrupts:
      (+)  HRTIM interrupt handler
      (+)  Callback function called when Fault1 interrupt occurs
      (+)  Callback function called when Fault2 interrupt occurs
      (+)  Callback function called when Fault3 interrupt occurs
      (+)  Callback function called when Fault4 interrupt occurs
      (+)  Callback function called when Fault5 interrupt occurs
      (+)  Callback function called when system Fault interrupt occurs
      (+)  Callback function called when burst mode period interrupt occurs
      (+)  Callback function called when synchronization input interrupt occurs
      (+)  Callback function called when a timer register update interrupt occurs
      (+)  Callback function called when a timer repetition interrupt occurs
      (+)  Callback function called when a compare 1 match interrupt occurs
      (+)  Callback function called when a compare 2 match interrupt occurs
      (+)  Callback function called when a compare 3 match interrupt occurs
      (+)  Callback function called when a compare 4 match interrupt occurs
      (+)  Callback function called when a capture 1 interrupt occurs
      (+)  Callback function called when a capture 2 interrupt occurs
      (+)  Callback function called when a delayed protection interrupt occurs
      (+)  Callback function called when a timer counter reset interrupt occurs
      (+)  Callback function called when a timer output 1 set interrupt occurs
      (+)  Callback function called when a timer output 1 reset interrupt occurs
      (+)  Callback function called when a timer output 2 set interrupt occurs
      (+)  Callback function called when a timer output 2 reset interrupt occurs
      (+)  Callback function called when a timer output 2 reset interrupt occurs
      (+)  Callback function called upon completion of a burst DMA transfer

Function Documentation

void HAL_HRTIM_BurstDMATransferCallback | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Callback function invoked when a DMA burst transfer is completed.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_MASTER for master timer
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
None

Definition at line 6250 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_BurstDMACplt().

void HAL_HRTIM_BurstModePeriodCallback ( HRTIM_HandleTypeDef * hhrtim )

Callback function invoked when the end of the burst mode period is reached.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Return values:
None

Definition at line 5864 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_Master_ISR().

void HAL_HRTIM_Capture1EventCallback | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Callback function invoked when the timer x capture 1 event occurs.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
None

Definition at line 6055 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_DMATimerxCplt(), and HRTIM_Timer_ISR().

void HAL_HRTIM_Capture2EventCallback | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Callback function invoked when the timer x capture 2 event occurs.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
None

Definition at line 6079 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_DMATimerxCplt(), and HRTIM_Timer_ISR().

void HAL_HRTIM_Compare1EventCallback | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Callback function invoked when the timer counter matches the value programmed in the compare 1 register.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_MASTER for master timer
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
None

Definition at line 5953 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_DMAMasterCplt(), HRTIM_DMATimerxCplt(), HRTIM_Master_ISR(), and HRTIM_Timer_ISR().

void HAL_HRTIM_Compare2EventCallback | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Callback function invoked when the timer counter matches the value programmed in the compare 2 register.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Return values:
None
Parameters:
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_MASTER for master timer
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E

Definition at line 5979 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_DMAMasterCplt(), HRTIM_DMATimerxCplt(), HRTIM_Master_ISR(), and HRTIM_Timer_ISR().

void HAL_HRTIM_Compare3EventCallback | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Callback function invoked when the timer counter matches the value programmed in the compare 3 register.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_MASTER for master timer
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
None

Definition at line 6005 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_DMAMasterCplt(), HRTIM_DMATimerxCplt(), HRTIM_Master_ISR(), and HRTIM_Timer_ISR().

void HAL_HRTIM_Compare4EventCallback | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Callback function invoked when the timer counter matches the value programmed in the compare 4 register.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_MASTER for master timer
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
None

Definition at line 6031 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_DMAMasterCplt(), HRTIM_DMATimerxCplt(), HRTIM_Master_ISR(), and HRTIM_Timer_ISR().

void HAL_HRTIM_CounterResetCallback | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Callback function invoked when the timer x counter reset/roll-over event occurs.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
None

Definition at line 6129 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_DMATimerxCplt(), and HRTIM_Timer_ISR().

void HAL_HRTIM_DelayedProtectionCallback | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Callback function invoked when the delayed idle or balanced idle mode is entered.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
None

Definition at line 6104 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_DMATimerxCplt(), and HRTIM_Timer_ISR().

void HAL_HRTIM_ErrorCallback ( HRTIM_HandleTypeDef * hhrtim )

Callback function invoked when a DMA error occurs.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Return values:
None

Definition at line 6267 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_DMAError().

void HAL_HRTIM_Fault1Callback ( HRTIM_HandleTypeDef * hhrtim )

Callback function invoked when a fault 1 interrupt occured.

Parameters:
hhrtim,: pointer to HAL HRTIM handle *
Return values:
None
None

Definition at line 5774 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_HRTIM_ISR().

void HAL_HRTIM_Fault2Callback ( HRTIM_HandleTypeDef * hhrtim )

Callback function invoked when a fault 2 interrupt occured.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Return values:
None

Definition at line 5789 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_HRTIM_ISR().

void HAL_HRTIM_Fault3Callback ( HRTIM_HandleTypeDef * hhrtim )

Callback function invoked when a fault 3 interrupt occured.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Return values:
None

Definition at line 5804 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_HRTIM_ISR().

void HAL_HRTIM_Fault4Callback ( HRTIM_HandleTypeDef * hhrtim )

Callback function invoked when a fault 4 interrupt occured.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Return values:
None

Definition at line 5819 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_HRTIM_ISR().

void HAL_HRTIM_Fault5Callback ( HRTIM_HandleTypeDef * hhrtim )

Callback function invoked when a fault 5 interrupt occured.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Return values:
None

Definition at line 5834 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_HRTIM_ISR().

void HAL_HRTIM_IRQHandler | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

This function handles HRTIM interrupt request.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be any value of HRTIM Timer Index
Return values:
None

Definition at line 5748 of file stm32h7xx_hal_hrtim.c.

References HRTIM_HRTIM_ISR(), HRTIM_Master_ISR(), HRTIM_Timer_ISR(), HRTIM_TIMERINDEX_COMMON, and HRTIM_TIMERINDEX_MASTER.

void HAL_HRTIM_Output1ResetCallback | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Callback function invoked when the timer x output 1 is reset.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
None

Definition at line 6177 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_DMATimerxCplt(), and HRTIM_Timer_ISR().

void HAL_HRTIM_Output1SetCallback | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Callback function invoked when the timer x output 1 is set.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
None

Definition at line 6153 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_DMATimerxCplt(), and HRTIM_Timer_ISR().

void HAL_HRTIM_Output2ResetCallback | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Callback function invoked when the timer x output 2 is reset.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
None

Definition at line 6225 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_DMATimerxCplt(), and HRTIM_Timer_ISR().

void HAL_HRTIM_Output2SetCallback | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Callback function invoked when the timer x output 2 is set.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
None

Definition at line 6201 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_DMATimerxCplt(), and HRTIM_Timer_ISR().

void HAL_HRTIM_RegistersUpdateCallback | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Callback function invoked when timer registers are updated.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_MASTER for master timer
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
None

Definition at line 5902 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_DMAMasterCplt(), HRTIM_DMATimerxCplt(), HRTIM_Master_ISR(), and HRTIM_Timer_ISR().

void HAL_HRTIM_RepetitionEventCallback | ( | HRTIM_HandleTypeDef * | hhrtim,
 |  | uint32_t | TimerIdx
 | ) |  |

Callback function invoked when timer repetition period has elapsed.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
TimerIdx,: Timer index This parameter can be one of the following values:
  • HRTIM_TIMERINDEX_MASTER for master timer
  • HRTIM_TIMERINDEX_TIMER_A for timer A
  • HRTIM_TIMERINDEX_TIMER_B for timer B
  • HRTIM_TIMERINDEX_TIMER_C for timer C
  • HRTIM_TIMERINDEX_TIMER_D for timer D
  • HRTIM_TIMERINDEX_TIMER_E for timer E
Return values:
None

Definition at line 5927 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_DMAMasterCplt(), HRTIM_DMATimerxCplt(), HRTIM_Master_ISR(), and HRTIM_Timer_ISR().

void HAL_HRTIM_SynchronizationEventCallback ( HRTIM_HandleTypeDef * hhrtim )

Callback function invoked when a synchronization input event is received.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Return values:
None

Definition at line 5879 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_DMAMasterCplt(), and HRTIM_Master_ISR().

void HAL_HRTIM_SystemFaultCallback ( HRTIM_HandleTypeDef * hhrtim )

Callback function invoked when a system fault interrupt occured.

Parameters:
hhrtim,: pointer to HAL HRTIM handle
Return values:
None

Definition at line 5849 of file stm32h7xx_hal_hrtim.c.

Referenced by HRTIM_HRTIM_ISR().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Exported Types

Data Structures | Typedefs | Enumerations
HRTIM Exported Types
HRTIM

Data Structures

struct | HRTIM_InitTypeDef
HRTIM Configuration Structure definition - Time base related parameters. More...
struct | HRTIM_TimerParamTypeDef
HRTIM Timer Structure definition. More...
struct | __HRTIM_HandleTypeDef
HRTIM Handle Structure definition. More...
struct | HRTIM_TimeBaseCfgTypeDef
Simple output compare mode configuration definition. More...
struct | HRTIM_SimpleOCChannelCfgTypeDef
Simple output compare mode configuration definition. More...
struct | HRTIM_SimplePWMChannelCfgTypeDef
Simple PWM output mode configuration definition. More...
struct | HRTIM_SimpleCaptureChannelCfgTypeDef
Simple capture mode configuration definition. More...
struct | HRTIM_SimpleOnePulseChannelCfgTypeDef
Simple One Pulse mode configuration definition. More...
struct | HRTIM_TimerCfgTypeDef
Timer configuration definition. More...
struct | HRTIM_CompareCfgTypeDef
Compare unit configuration definition. More...
struct | HRTIM_CaptureCfgTypeDef
Capture unit configuration definition. More...
struct | HRTIM_OutputCfgTypeDef
Output configuration definition. More...
struct | HRTIM_TimerEventFilteringCfgTypeDef
External event filtering in timing units configuration definition. More...
struct | HRTIM_DeadTimeCfgTypeDef
Dead time feature configuration definition. More...
struct | HRTIM_ChopperModeCfgTypeDef
Chopper mode configuration definition. More...
struct | HRTIM_EventCfgTypeDef
External event channel configuration definition. More...
struct | HRTIM_FaultCfgTypeDef
Fault channel configuration definition. More...
struct | HRTIM_BurstModeCfgTypeDef
Burst mode configuration definition. More...
struct | HRTIM_ADCTriggerCfgTypeDef
ADC trigger configuration definition. More...

Typedefs

typedef struct
__HRTIM_HandleTypeDef 		HRTIM_HandleTypeDef
HRTIM Handle Structure definition.

Enumerations

enum | HAL_HRTIM_StateTypeDef { HAL_HRTIM_STATE_READY = 0x01U, HAL_HRTIM_STATE_BUSY = 0x02U, HAL_HRTIM_STATE_TIMEOUT = 0x06U, HAL_HRTIM_STATE_ERROR = 0x07U }
HAL State structures definition. More...

Typedef Documentation

typedef struct __HRTIM_HandleTypeDef HRTIM_HandleTypeDef

HRTIM Handle Structure definition.

Enumeration Type Documentation

enum HAL_HRTIM_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_HRTIM_STATE_READY

Peripheral Initialized and ready for use

HAL_HRTIM_STATE_BUSY

an internal process is ongoing

HAL_HRTIM_STATE_TIMEOUT

Timeout state

HAL_HRTIM_STATE_ERROR

Error state

Definition at line 96 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HRTIM_InitTypeDef Struct Reference
HRTIM Exported Types

HRTIM Configuration Structure definition - Time base related parameters. More...

#include <stm32h7xx_hal_hrtim.h>

Data Fields

uint32_t | HRTIMInterruptResquests
uint32_t | SyncOptions
uint32_t | SyncInputSource
uint32_t | SyncOutputSource
uint32_t | SyncOutputPolarity

Detailed Description

HRTIM Configuration Structure definition - Time base related parameters.

Definition at line 79 of file stm32h7xx_hal_hrtim.h.

Field Documentation

uint32_t HRTIM_InitTypeDef::HRTIMInterruptResquests

Specifies which interrupts requests must enabled for the HRTIM instance This parameter can be any combination of HRTIM Common Interrupt Enable

Definition at line 81 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init(), HAL_HRTIM_WaveformCounterStart_IT(), and HAL_HRTIM_WaveformCounterStop_IT().

uint32_t HRTIM_InitTypeDef::SyncInputSource

Specifies the external synchronization input source This parameter can be a value of HRTIM Synchronization Input Source

Definition at line 85 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init().

uint32_t HRTIM_InitTypeDef::SyncOptions

Specifies how the HRTIM instance handles the external synchronization signals This parameter can be a combination of HRTIM Synchronization Options

Definition at line 83 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init().

uint32_t HRTIM_InitTypeDef::SyncOutputPolarity

Specifies the conditionning of the event to be sent on the external synchronization outputs This parameter can be a value of HRTIM Synchronization Output Polarity

Definition at line 89 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init().

uint32_t HRTIM_InitTypeDef::SyncOutputSource

Specifies the source and event to be sent on the external synchronization outputs This parameter can be a value of HRTIM Synchronization Output Source

Definition at line 87 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hrtim.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM_TimerParamTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HRTIM_TimerParamTypeDef Struct Reference
HRTIM Exported Types

HRTIM Timer Structure definition. More...

#include <stm32h7xx_hal_hrtim.h>

Data Fields

uint32_t | CaptureTrigger1
uint32_t | CaptureTrigger2
uint32_t | InterruptRequests
uint32_t | DMARequests
uint32_t | DMASrcAddress
uint32_t | DMADstAddress
uint32_t | DMASize

Detailed Description

HRTIM Timer Structure definition.

Definition at line 107 of file stm32h7xx_hal_hrtim.h.

Field Documentation

uint32_t HRTIM_TimerParamTypeDef::CaptureTrigger1

Event(s) triggering capture unit 1. When the timer operates in Simple mode, this parameter can be a value of HRTIM External Event Channels. When the timer operates in Waveform mode, this parameter can be a combination of HRTIM Capture Unit Trigger.

Definition at line 109 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init(), HAL_HRTIM_SimpleCaptureStart(), HAL_HRTIM_SimpleCaptureStart_DMA(), HAL_HRTIM_SimpleCaptureStart_IT(), and HRTIM_CaptureUnitConfig().

uint32_t HRTIM_TimerParamTypeDef::CaptureTrigger2

Event(s) triggering capture unit 2. When the timer operates in Simple mode, this parameter can be a value of HRTIM External Event Channels. When the timer operates in Waveform mode, this parameter can be a combination of HRTIM Capture Unit Trigger.

Definition at line 112 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init(), HAL_HRTIM_SimpleCaptureStart(), HAL_HRTIM_SimpleCaptureStart_DMA(), HAL_HRTIM_SimpleCaptureStart_IT(), and HRTIM_CaptureUnitConfig().

uint32_t HRTIM_TimerParamTypeDef::DMADstAddress

Address of the destination address of the DMA transfer.

Definition at line 118 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformCounterStart_DMA(), and HAL_HRTIM_WaveformTimerConfig().

uint32_t HRTIM_TimerParamTypeDef::DMARequests

DMA requests enabled for the timer.

Definition at line 116 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init(), HAL_HRTIM_WaveformCounterStart_DMA(), HAL_HRTIM_WaveformCounterStop_DMA(), and HAL_HRTIM_WaveformTimerConfig().

uint32_t HRTIM_TimerParamTypeDef::DMASize

Size of the DMA transfer

Definition at line 119 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init(), HAL_HRTIM_WaveformCounterStart_DMA(), and HAL_HRTIM_WaveformTimerConfig().

uint32_t HRTIM_TimerParamTypeDef::DMASrcAddress

Address of the source address of the DMA transfer.

Definition at line 117 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init(), HAL_HRTIM_WaveformCounterStart_DMA(), and HAL_HRTIM_WaveformTimerConfig().

uint32_t HRTIM_TimerParamTypeDef::InterruptRequests

Interrupts requests enabled for the timer.

Definition at line 115 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init(), HAL_HRTIM_WaveformCounterStart_IT(), HAL_HRTIM_WaveformCounterStop_IT(), and HAL_HRTIM_WaveformTimerConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hrtim.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: __HRTIM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__HRTIM_HandleTypeDef Struct Reference
HRTIM Exported Types

HRTIM Handle Structure definition. More...

#include <stm32h7xx_hal_hrtim.h>

Data Fields

HRTIM_TypeDef * | Instance
HRTIM_InitTypeDef Init
HRTIM_TimerParamTypeDef TimerParam [MAX_HRTIM_TIMER]
HAL_LockTypeDef | Lock
__IO HAL_HRTIM_StateTypeDef | State
DMA_HandleTypeDef * hdmaMaster
DMA_HandleTypeDef * hdmaTimerA
DMA_HandleTypeDef * hdmaTimerB
DMA_HandleTypeDef * hdmaTimerC
DMA_HandleTypeDef * hdmaTimerD
DMA_HandleTypeDef * hdmaTimerE

Detailed Description

HRTIM Handle Structure definition.

Definition at line 125 of file stm32h7xx_hal_hrtim.h.

Field Documentation

DMA_HandleTypeDef* __HRTIM_HandleTypeDef::hdmaMaster

Master timer DMA handle parameters

Definition at line 137 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init(), HAL_HRTIM_SimpleBaseStop_DMA(), HAL_HRTIM_WaveformCounterStart_DMA(), HAL_HRTIM_WaveformCounterStop_DMA(), and HRTIM_GetDMAHandleFromTimerIdx().

DMA_HandleTypeDef* __HRTIM_HandleTypeDef::hdmaTimerA

Timer A DMA handle parameters

Definition at line 138 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init(), and HRTIM_GetDMAHandleFromTimerIdx().

DMA_HandleTypeDef* __HRTIM_HandleTypeDef::hdmaTimerB

Timer B DMA handle parameters

Definition at line 139 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init(), and HRTIM_GetDMAHandleFromTimerIdx().

DMA_HandleTypeDef* __HRTIM_HandleTypeDef::hdmaTimerC

Timer C DMA handle parameters

Definition at line 140 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init(), and HRTIM_GetDMAHandleFromTimerIdx().

DMA_HandleTypeDef* __HRTIM_HandleTypeDef::hdmaTimerD

Timer D DMA handle parameters

Definition at line 141 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init(), and HRTIM_GetDMAHandleFromTimerIdx().

DMA_HandleTypeDef* __HRTIM_HandleTypeDef::hdmaTimerE

Timer E DMA handle parameters

Definition at line 142 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init(), and HRTIM_GetDMAHandleFromTimerIdx().

HRTIM_InitTypeDef __HRTIM_HandleTypeDef::Init

HRTIM required parameters

Definition at line 129 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init(), HAL_HRTIM_WaveformCounterStart_IT(), and HAL_HRTIM_WaveformCounterStop_IT().

HRTIM_TypeDef* __HRTIM_HandleTypeDef::Instance

Register base address

Definition at line 127 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_ADCTriggerConfig(), HAL_HRTIM_BurstDMAConfig(), HAL_HRTIM_BurstDMATransfer(), HAL_HRTIM_BurstModeConfig(), HAL_HRTIM_BurstModeCtl(), HAL_HRTIM_BurstModeSoftwareTrigger(), HAL_HRTIM_ChopperModeConfig(), HAL_HRTIM_DeadTimeConfig(), HAL_HRTIM_DeInit(), HAL_HRTIM_EventPrescalerConfig(), HAL_HRTIM_FaultConfig(), HAL_HRTIM_FaultModeCtl(), HAL_HRTIM_FaultPrescalerConfig(), HAL_HRTIM_GetBurstStatus(), HAL_HRTIM_GetCapturedValue(), HAL_HRTIM_GetCurrentPushPullStatus(), HAL_HRTIM_GetDelayedProtectionStatus(), HAL_HRTIM_GetIdlePushPullStatus(), HAL_HRTIM_Init(), HAL_HRTIM_SimpleCaptureStart(), HAL_HRTIM_SimpleCaptureStart_DMA(), HAL_HRTIM_SimpleCaptureStart_IT(), HAL_HRTIM_SimpleCaptureStop(), HAL_HRTIM_SimpleCaptureStop_DMA(), HAL_HRTIM_SimpleCaptureStop_IT(), HAL_HRTIM_SimpleOCStart(), HAL_HRTIM_SimpleOCStart_DMA(), HAL_HRTIM_SimpleOCStart_IT(), HAL_HRTIM_SimpleOCStop(), HAL_HRTIM_SimpleOCStop_DMA(), HAL_HRTIM_SimpleOCStop_IT(), HAL_HRTIM_SimpleOnePulseStart(), HAL_HRTIM_SimpleOnePulseStart_IT(), HAL_HRTIM_SimpleOnePulseStop(), HAL_HRTIM_SimpleOnePulseStop_IT(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_SimplePWMStart(), HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_SimplePWMStart_IT(), HAL_HRTIM_SimplePWMStop(), HAL_HRTIM_SimplePWMStop_DMA(), HAL_HRTIM_SimplePWMStop_IT(), HAL_HRTIM_SoftwareCapture(), HAL_HRTIM_SoftwareReset(), HAL_HRTIM_SoftwareUpdate(), HAL_HRTIM_TimerEventFilteringConfig(), HAL_HRTIM_UpdateDisable(), HAL_HRTIM_UpdateEnable(), HAL_HRTIM_WaveformCaptureConfig(), HAL_HRTIM_WaveformCompareConfig(), HAL_HRTIM_WaveformCounterStart(), HAL_HRTIM_WaveformCounterStart_IT(), HAL_HRTIM_WaveformCounterStop(), HAL_HRTIM_WaveformCounterStop_IT(), HAL_HRTIM_WaveformGetOutputLevel(), HAL_HRTIM_WaveformGetOutputState(), HAL_HRTIM_WaveformOutputStart(), HAL_HRTIM_WaveformOutputStop(), HAL_HRTIM_WaveformSetOutputLevel(), HRTIM_CompareUnitConfig(), HRTIM_DMAMasterCplt(), HRTIM_DMATimerxCplt(), HRTIM_EventConfig(), HRTIM_ForceRegistersUpdate(), HRTIM_GetDMAFromOCMode(), HRTIM_GetITFromOCMode(), HRTIM_MasterBase_Config(), HRTIM_MasterWaveform_Config(), HRTIM_OutputConfig(), HRTIM_TIM_ResetConfig(), HRTIM_TimingUnitBase_Config(), and HRTIM_TimingUnitWaveform_Config().

HAL_LockTypeDef __HRTIM_HandleTypeDef::Lock

Locking object

Definition at line 133 of file stm32h7xx_hal_hrtim.h.

__IO HAL_HRTIM_StateTypeDef __HRTIM_HandleTypeDef::State

HRTIM communication state

Definition at line 135 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_ADCTriggerConfig(), HAL_HRTIM_BurstDMAConfig(), HAL_HRTIM_BurstDMATransfer(), HAL_HRTIM_BurstModeConfig(), HAL_HRTIM_BurstModeCtl(), HAL_HRTIM_BurstModeSoftwareTrigger(), HAL_HRTIM_ChopperModeConfig(), HAL_HRTIM_DeadTimeConfig(), HAL_HRTIM_DeInit(), HAL_HRTIM_EventConfig(), HAL_HRTIM_EventPrescalerConfig(), HAL_HRTIM_FaultConfig(), HAL_HRTIM_FaultPrescalerConfig(), HAL_HRTIM_GetState(), HAL_HRTIM_Init(), HAL_HRTIM_SimpleBaseStart(), HAL_HRTIM_SimpleBaseStart_DMA(), HAL_HRTIM_SimpleBaseStart_IT(), HAL_HRTIM_SimpleBaseStop(), HAL_HRTIM_SimpleBaseStop_DMA(), HAL_HRTIM_SimpleBaseStop_IT(), HAL_HRTIM_SimpleCaptureChannelConfig(), HAL_HRTIM_SimpleCaptureStart(), HAL_HRTIM_SimpleCaptureStart_DMA(), HAL_HRTIM_SimpleCaptureStart_IT(), HAL_HRTIM_SimpleCaptureStop(), HAL_HRTIM_SimpleCaptureStop_DMA(), HAL_HRTIM_SimpleCaptureStop_IT(), HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOCStart(), HAL_HRTIM_SimpleOCStart_DMA(), HAL_HRTIM_SimpleOCStart_IT(), HAL_HRTIM_SimpleOCStop(), HAL_HRTIM_SimpleOCStop_DMA(), HAL_HRTIM_SimpleOCStop_IT(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimpleOnePulseStart(), HAL_HRTIM_SimpleOnePulseStart_IT(), HAL_HRTIM_SimpleOnePulseStop(), HAL_HRTIM_SimpleOnePulseStop_IT(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_SimplePWMStart(), HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_SimplePWMStart_IT(), HAL_HRTIM_SimplePWMStop(), HAL_HRTIM_SimplePWMStop_DMA(), HAL_HRTIM_SimplePWMStop_IT(), HAL_HRTIM_SoftwareCapture(), HAL_HRTIM_SoftwareReset(), HAL_HRTIM_SoftwareUpdate(), HAL_HRTIM_TimeBaseConfig(), HAL_HRTIM_TimerEventFilteringConfig(), HAL_HRTIM_UpdateDisable(), HAL_HRTIM_UpdateEnable(), HAL_HRTIM_WaveformCaptureConfig(), HAL_HRTIM_WaveformCompareConfig(), HAL_HRTIM_WaveformCounterStart(), HAL_HRTIM_WaveformCounterStart_DMA(), HAL_HRTIM_WaveformCounterStart_IT(), HAL_HRTIM_WaveformCounterStop(), HAL_HRTIM_WaveformCounterStop_DMA(), HAL_HRTIM_WaveformCounterStop_IT(), HAL_HRTIM_WaveformOutputConfig(), HAL_HRTIM_WaveformOutputStart(), HAL_HRTIM_WaveformOutputStop(), HAL_HRTIM_WaveformSetOutputLevel(), and HAL_HRTIM_WaveformTimerConfig().

HRTIM_TimerParamTypeDef __HRTIM_HandleTypeDef::TimerParam[MAX_HRTIM_TIMER]

HRTIM timers - including the master - parameters

Definition at line 131 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init(), HAL_HRTIM_SimpleCaptureStart(), HAL_HRTIM_SimpleCaptureStart_DMA(), HAL_HRTIM_SimpleCaptureStart_IT(), HAL_HRTIM_WaveformCounterStart_DMA(), HAL_HRTIM_WaveformCounterStart_IT(), HAL_HRTIM_WaveformCounterStop_DMA(), HAL_HRTIM_WaveformCounterStop_IT(), HAL_HRTIM_WaveformTimerConfig(), and HRTIM_CaptureUnitConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hrtim.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM_TimeBaseCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HRTIM_TimeBaseCfgTypeDef Struct Reference
HRTIM Exported Types

Simple output compare mode configuration definition. More...

#include <stm32h7xx_hal_hrtim.h>

Data Fields

uint32_t | Period
uint32_t | RepetitionCounter
uint32_t | PrescalerRatio
uint32_t | Mode

Detailed Description

Simple output compare mode configuration definition.

Definition at line 148 of file stm32h7xx_hal_hrtim.h.

Field Documentation

uint32_t HRTIM_TimeBaseCfgTypeDef::Mode

Specifies the counter operating mode This parameter can be any value of HRTIM Mode

Definition at line 156 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_TimeBaseConfig(), HRTIM_MasterBase_Config(), and HRTIM_TimingUnitBase_Config().

uint32_t HRTIM_TimeBaseCfgTypeDef::Period

Specifies the timer period The period value must be above 3 periods of the fHRTIM clock. Maximum value is = 0xFFDF

Definition at line 149 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_MasterBase_Config(), and HRTIM_TimingUnitBase_Config().

uint32_t HRTIM_TimeBaseCfgTypeDef::PrescalerRatio

Specifies the timer clock prescaler ratio. This parameter can be any value of HRTIM Prescaler Ratio

Definition at line 154 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_TimeBaseConfig(), HRTIM_MasterBase_Config(), and HRTIM_TimingUnitBase_Config().

uint32_t HRTIM_TimeBaseCfgTypeDef::RepetitionCounter

Specifies the timer repetition period This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

Definition at line 152 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_MasterBase_Config(), and HRTIM_TimingUnitBase_Config().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hrtim.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM_SimpleOCChannelCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HRTIM_SimpleOCChannelCfgTypeDef Struct Reference
HRTIM Exported Types

Simple output compare mode configuration definition. More...

#include <stm32h7xx_hal_hrtim.h>

Data Fields

uint32_t | Mode
uint32_t | Pulse
uint32_t | Polarity
uint32_t | IdleLevel

Detailed Description

Simple output compare mode configuration definition.

Definition at line 163 of file stm32h7xx_hal_hrtim.h.

Field Documentation

uint32_t HRTIM_SimpleOCChannelCfgTypeDef::IdleLevel

Specifies whether the output level is active or inactive when in IDLE state This parameter can be any value of HRTIM Output IDLE Level

Definition at line 170 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig().

uint32_t HRTIM_SimpleOCChannelCfgTypeDef::Mode

Specifies the output compare mode (toggle, active, inactive) This parameter can be any value of of HRTIM Simple OC Mode

Definition at line 164 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig().

uint32_t HRTIM_SimpleOCChannelCfgTypeDef::Polarity

Specifies the output polarity This parameter can be any value of HRTIM Output Polarity

Definition at line 168 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig().

uint32_t HRTIM_SimpleOCChannelCfgTypeDef::Pulse

Specifies the compare value to be loaded into the Compare Register. The compare value must be above or equal to 3 periods of the fHRTIM clock

Definition at line 166 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hrtim.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM_SimplePWMChannelCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HRTIM_SimplePWMChannelCfgTypeDef Struct Reference
HRTIM Exported Types

Simple PWM output mode configuration definition. More...

#include <stm32h7xx_hal_hrtim.h>

Data Fields

uint32_t | Pulse
uint32_t | Polarity
uint32_t | IdleLevel

Detailed Description

Simple PWM output mode configuration definition.

Definition at line 177 of file stm32h7xx_hal_hrtim.h.

Field Documentation

uint32_t HRTIM_SimplePWMChannelCfgTypeDef::IdleLevel

Specifies whether the output level is active or inactive when in IDLE state This parameter can be any value of HRTIM Output IDLE Level

Definition at line 182 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimplePWMChannelConfig().

uint32_t HRTIM_SimplePWMChannelCfgTypeDef::Polarity

Specifies the output polarity This parameter can be any value of HRTIM Output Polarity

Definition at line 180 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimplePWMChannelConfig().

uint32_t HRTIM_SimplePWMChannelCfgTypeDef::Pulse

Specifies the compare value to be loaded into the Compare Register. The compare value must be above or equal to 3 periods of the fHRTIM clock

Definition at line 178 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimplePWMChannelConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hrtim.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM_SimpleCaptureChannelCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HRTIM_SimpleCaptureChannelCfgTypeDef Struct Reference
HRTIM Exported Types

Simple capture mode configuration definition. More...

#include <stm32h7xx_hal_hrtim.h>

Data Fields

uint32_t | Event
uint32_t | EventPolarity
uint32_t | EventSensitivity
uint32_t | EventFilter

Detailed Description

Simple capture mode configuration definition.

Definition at line 189 of file stm32h7xx_hal_hrtim.h.

Field Documentation

uint32_t HRTIM_SimpleCaptureChannelCfgTypeDef::Event

Specifies the external event triggering the capture This parameter can be any 'EEVx' value of HRTIM External Event Channels

Definition at line 190 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleCaptureChannelConfig().

uint32_t HRTIM_SimpleCaptureChannelCfgTypeDef::EventFilter

Defines the frequency used to sample the External Event and the length of the digital filter This parameter can be a value of HRTIM External Event Filter

Definition at line 196 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleCaptureChannelConfig().

uint32_t HRTIM_SimpleCaptureChannelCfgTypeDef::EventPolarity

Specifies the polarity of the external event (in case of level sensitivity) This parameter can be a value of HRTIM External Event Polarity

Definition at line 192 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleCaptureChannelConfig().

uint32_t HRTIM_SimpleCaptureChannelCfgTypeDef::EventSensitivity

Specifies the sensitivity of the external event This parameter can be a value of HRTIM External Event Sensitivity

Definition at line 194 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleCaptureChannelConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hrtim.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM_SimpleOnePulseChannelCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HRTIM_SimpleOnePulseChannelCfgTypeDef Struct Reference
HRTIM Exported Types

Simple One Pulse mode configuration definition. More...

#include <stm32h7xx_hal_hrtim.h>

Data Fields

uint32_t | Pulse
uint32_t | OutputPolarity
uint32_t | OutputIdleLevel
uint32_t | Event
uint32_t | EventPolarity
uint32_t | EventSensitivity
uint32_t | EventFilter

Detailed Description

Simple One Pulse mode configuration definition.

Definition at line 203 of file stm32h7xx_hal_hrtim.h.

Field Documentation

uint32_t HRTIM_SimpleOnePulseChannelCfgTypeDef::Event

Specifies the external event triggering the pulse generation This parameter can be any 'EEVx' value of HRTIM External Event Channels

Definition at line 210 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOnePulseChannelConfig().

uint32_t HRTIM_SimpleOnePulseChannelCfgTypeDef::EventFilter

Defines the frequency used to sample the External Event and the length of the digital filter This parameter can be a value of HRTIM External Event Filter

Definition at line 216 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOnePulseChannelConfig().

uint32_t HRTIM_SimpleOnePulseChannelCfgTypeDef::EventPolarity

Specifies the polarity of the external event (in case of level sensitivity) This parameter can be a value of HRTIM External Event Polarity

Definition at line 212 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOnePulseChannelConfig().

uint32_t HRTIM_SimpleOnePulseChannelCfgTypeDef::EventSensitivity

Specifies the sensitivity of the external event This parameter can be a value of HRTIM External Event Sensitivity

Definition at line 214 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOnePulseChannelConfig().

uint32_t HRTIM_SimpleOnePulseChannelCfgTypeDef::OutputIdleLevel

Specifies whether the output level is active or inactive when in IDLE state This parameter can be any value of HRTIM Output IDLE Level

Definition at line 208 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOnePulseChannelConfig().

uint32_t HRTIM_SimpleOnePulseChannelCfgTypeDef::OutputPolarity

Specifies the output polarity This parameter can be any value of HRTIM Output Polarity

Definition at line 206 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOnePulseChannelConfig().

uint32_t HRTIM_SimpleOnePulseChannelCfgTypeDef::Pulse

Specifies the compare value to be loaded into the Compare Register. The compare value must be above or equal to 3 periods of the fHRTIM clock

Definition at line 204 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOnePulseChannelConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hrtim.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM_TimerCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HRTIM_TimerCfgTypeDef Struct Reference
HRTIM Exported Types

Timer configuration definition. More...

#include <stm32h7xx_hal_hrtim.h>

Data Fields

uint32_t | InterruptRequests
uint32_t | DMARequests
uint32_t | DMASrcAddress
uint32_t | DMADstAddress
uint32_t | DMASize
uint32_t | HalfModeEnable
uint32_t | StartOnSync
uint32_t | ResetOnSync
uint32_t | DACSynchro
uint32_t | PreloadEnable
uint32_t | UpdateGating
uint32_t | BurstMode
uint32_t | RepetitionUpdate
uint32_t | PushPull
uint32_t | FaultEnable
uint32_t | FaultLock
uint32_t | DeadTimeInsertion
uint32_t | DelayedProtectionMode
uint32_t | UpdateTrigger
uint32_t | ResetTrigger
uint32_t | ResetUpdate

Detailed Description

Timer configuration definition.

Definition at line 223 of file stm32h7xx_hal_hrtim.h.

Field Documentation

uint32_t HRTIM_TimerCfgTypeDef::BurstMode

Relevant for all HRTIM timers, including the master Specifies how the timer behaves during a burst mode operation This parameter can be any value of HRTIM Timer Burst Mode

Definition at line 257 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig(), HRTIM_MasterWaveform_Config(), and HRTIM_TimingUnitWaveform_Config().

uint32_t HRTIM_TimerCfgTypeDef::DACSynchro

Relevant for all HRTIM timers, including the master Indicates whether or not the a DAC synchronization event is generated This parameter can be any value of HRTIM DAC Synchronization

Definition at line 247 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig(), HRTIM_MasterWaveform_Config(), and HRTIM_TimingUnitWaveform_Config().

uint32_t HRTIM_TimerCfgTypeDef::DeadTimeInsertion

Relevant for Timer A to Timer E Specifies whether or not deadtime insertion is enabled for the timer This parameter can be a value of HRTIM Timer Deadtime Insertion

Definition at line 272 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig(), and HRTIM_TimingUnitWaveform_Config().

uint32_t HRTIM_TimerCfgTypeDef::DelayedProtectionMode

Relevant for Timer A to Timer E Specifies the delayed protection mode This parameter can be a value of HRTIM Timer Delayed Protection Mode

Definition at line 275 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig(), and HRTIM_TimingUnitWaveform_Config().

uint32_t HRTIM_TimerCfgTypeDef::DMADstAddress

Relevant for all HRTIM timers, including the master Specifies the address of the destination address of the DMA transfer

Definition at line 234 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

uint32_t HRTIM_TimerCfgTypeDef::DMARequests

Relevant for all HRTIM timers, including the master Specifies which DMA requests must be enabled for the timer This parameter can be any combination of HRTIM Master DMA Request Enable or HRTIM_Timing_Unit_DMA_Request_Enable

Definition at line 228 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

uint32_t HRTIM_TimerCfgTypeDef::DMASize

Relevant for all HRTIM timers, including the master Specifies the size of the DMA transfer

Definition at line 236 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

uint32_t HRTIM_TimerCfgTypeDef::DMASrcAddress

Relevant for all HRTIM timers, including the master Specifies the address of the source address of the DMA transfer

Definition at line 232 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

uint32_t HRTIM_TimerCfgTypeDef::FaultEnable

Relevant for Timer A to Timer E Specifies which fault channels are enabled for the timer This parameter can be a combination of HRTIM Timer Fault Enabling

Definition at line 266 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig(), and HRTIM_TimingUnitWaveform_Config().

uint32_t HRTIM_TimerCfgTypeDef::FaultLock

Relevant for Timer A to Timer E Specifies whether or not fault enabling status is write protected This parameter can be a value of HRTIM Timer Fault Lock

Definition at line 269 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig(), and HRTIM_TimingUnitWaveform_Config().

uint32_t HRTIM_TimerCfgTypeDef::HalfModeEnable

Relevant for all HRTIM timers, including the master Specifies whether or not hald mode is enabled This parameter can be any value of HRTIM Half Mode Enable

Definition at line 238 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig(), HRTIM_MasterWaveform_Config(), and HRTIM_TimingUnitWaveform_Config().

uint32_t HRTIM_TimerCfgTypeDef::InterruptRequests

Relevant for all HRTIM timers, including the master Specifies which interrupts requests must enabled for the timer This parameter can be any combination of HRTIM Master Interrupt Enable or HRTIM_Timing_Unit_Interrupt_Enable

Definition at line 224 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

uint32_t HRTIM_TimerCfgTypeDef::PreloadEnable

Relevant for all HRTIM timers, including the master Specifies whether or not register preload is enabled This parameter can be any value of HRTIM Register Preload Enable

Definition at line 250 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig(), HRTIM_MasterWaveform_Config(), and HRTIM_TimingUnitWaveform_Config().

uint32_t HRTIM_TimerCfgTypeDef::PushPull

Relevant for Timer A to Timer E Specifies whether or not the push-pull mode is enabled This parameter can be any value of HRTIM Timer Push Pull Mode

Definition at line 263 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig(), and HRTIM_TimingUnitWaveform_Config().

uint32_t HRTIM_TimerCfgTypeDef::RepetitionUpdate

Relevant for all HRTIM timers, including the master Specifies whether or not registers update is triggered by the repetition event This parameter can be any valuen of HRTIM Timer Repetition Update

Definition at line 260 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig(), HRTIM_MasterWaveform_Config(), and HRTIM_TimingUnitWaveform_Config().

uint32_t HRTIM_TimerCfgTypeDef::ResetOnSync

Relevant for all HRTIM timers, including the master Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled) This parameter can be any value of HRTIM Reset On Sync Input Event

Definition at line 244 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig(), HRTIM_MasterWaveform_Config(), and HRTIM_TimingUnitWaveform_Config().

uint32_t HRTIM_TimerCfgTypeDef::ResetTrigger

Relevant for Timer A to Timer E Specifies source(s) triggering the timer counter reset This parameter can be a combination of HRTIM Timer Reset Trigger

Definition at line 281 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig(), and HRTIM_TimingUnitWaveform_Config().

uint32_t HRTIM_TimerCfgTypeDef::ResetUpdate

Relevant for Timer A to Timer E Specifies whether or not registers update is triggered when the timer counter is reset This parameter can be a value of HRTIM Timer Reset Update

Definition at line 284 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig(), and HRTIM_TimingUnitWaveform_Config().

uint32_t HRTIM_TimerCfgTypeDef::StartOnSync

Relevant for all HRTIM timers, including the master Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled) This parameter can be any value of HRTIM Start On Sync Input Event

Definition at line 241 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig(), HRTIM_MasterWaveform_Config(), and HRTIM_TimingUnitWaveform_Config().

uint32_t HRTIM_TimerCfgTypeDef::UpdateGating

Relevant for all HRTIM timers, including the master Specifies how the update occurs with respect to a burst DMA transaction or update enable inputs (Slave timers only) This parameter can be any value of HRTIM Update Gating

Definition at line 253 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig(), HRTIM_MasterWaveform_Config(), and HRTIM_TimingUnitWaveform_Config().

uint32_t HRTIM_TimerCfgTypeDef::UpdateTrigger

Relevant for Timer A to Timer E Specifies source(s) triggering the timer registers update This parameter can be a combination of HRTIM Timer Update Trigger

Definition at line 278 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig(), and HRTIM_TimingUnitWaveform_Config().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hrtim.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM_CompareCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HRTIM_CompareCfgTypeDef Struct Reference
HRTIM Exported Types

Compare unit configuration definition. More...

#include <stm32h7xx_hal_hrtim.h>

Data Fields

uint32_t | CompareValue
uint32_t | AutoDelayedMode
uint32_t | AutoDelayedTimeout

Detailed Description

Compare unit configuration definition.

Definition at line 292 of file stm32h7xx_hal_hrtim.h.

Field Documentation

uint32_t HRTIM_CompareCfgTypeDef::AutoDelayedMode

Specifies the auto delayed mode for compare unit 2 or 4 This parameter can be a value of HRTIM Compare Unit Auto Delayed Mode

Definition at line 296 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimplePWMChannelConfig(), and HAL_HRTIM_WaveformCompareConfig().

uint32_t HRTIM_CompareCfgTypeDef::AutoDelayedTimeout

Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected CompareValue + AutoDelayedTimeout must be less than 0xFFFF

Definition at line 298 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimplePWMChannelConfig(), and HAL_HRTIM_WaveformCompareConfig().

uint32_t HRTIM_CompareCfgTypeDef::CompareValue

Specifies the compare value of the timer compare unit the minimum value must be greater than or equal to 3 periods of the fHRTIM clock the maximum value must be less than or equal to 0xFFFF - 1 periods of the fHRTIM clock

Definition at line 293 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_WaveformCompareConfig(), and HRTIM_CompareUnitConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hrtim.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM_CaptureCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HRTIM_CaptureCfgTypeDef Struct Reference
HRTIM Exported Types

Capture unit configuration definition. More...

#include <stm32h7xx_hal_hrtim.h>

Data Fields

uint32_t Trigger

Detailed Description

Capture unit configuration definition.

Definition at line 305 of file stm32h7xx_hal_hrtim.h.

Field Documentation

uint32_t HRTIM_CaptureCfgTypeDef::Trigger

Specifies source(s) triggering the capture This parameter can be a combination of HRTIM Capture Unit Trigger

Definition at line 306 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformCaptureConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hrtim.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM_OutputCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HRTIM_OutputCfgTypeDef Struct Reference
HRTIM Exported Types

Output configuration definition. More...

#include <stm32h7xx_hal_hrtim.h>

Data Fields

uint32_t | Polarity
uint32_t | SetSource
uint32_t | ResetSource
uint32_t | IdleMode
uint32_t | IdleLevel
uint32_t | FaultLevel
uint32_t | ChopperModeEnable
uint32_t | BurstModeEntryDelayed

Detailed Description

Output configuration definition.

Definition at line 313 of file stm32h7xx_hal_hrtim.h.

Field Documentation

uint32_t HRTIM_OutputCfgTypeDef::BurstModeEntryDelayed

Definition at line 328 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_WaveformOutputConfig(), and HRTIM_OutputConfig().

uint32_t HRTIM_OutputCfgTypeDef::ChopperModeEnable

Indicates whether or not the chopper mode is enabled. This parameter can be any value of HRTIM Output Chopper Mode Enable

Definition at line 326 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_WaveformOutputConfig(), and HRTIM_OutputConfig().

uint32_t HRTIM_OutputCfgTypeDef::FaultLevel

Specifies whether the output level is active or inactive when in FAULT state. This parameter can be any value of HRTIM Output FAULT Level

Definition at line 324 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_WaveformOutputConfig(), and HRTIM_OutputConfig().

uint32_t HRTIM_OutputCfgTypeDef::IdleLevel

Specifies whether the output level is active or inactive when in IDLE state. This parameter can be any value of HRTIM Output IDLE Level

Definition at line 322 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_WaveformOutputConfig(), and HRTIM_OutputConfig().

uint32_t HRTIM_OutputCfgTypeDef::IdleMode

Specifies whether or not the output is affected by a burst mode operation. This parameter can be any value of HRTIM Output Idle Mode

Definition at line 320 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_WaveformOutputConfig(), and HRTIM_OutputConfig().

uint32_t HRTIM_OutputCfgTypeDef::Polarity

Specifies the output polarity. This parameter can be any value of HRTIM Output Polarity

Definition at line 314 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_WaveformOutputConfig(), and HRTIM_OutputConfig().

uint32_t HRTIM_OutputCfgTypeDef::ResetSource

Specifies the event(s) transitioning the output from its active level to its inactive level. This parameter can be a combination of HRTIM Output Reset Source

Definition at line 318 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimplePWMChannelConfig(), and HRTIM_OutputConfig().

uint32_t HRTIM_OutputCfgTypeDef::SetSource

Specifies the event(s) transitioning the output from its inactive level to its active level. This parameter can be a combination of HRTIM Output Set Source

Definition at line 316 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimplePWMChannelConfig(), and HRTIM_OutputConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hrtim.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM_TimerEventFilteringCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HRTIM_TimerEventFilteringCfgTypeDef Struct Reference
HRTIM Exported Types

External event filtering in timing units configuration definition. More...

#include <stm32h7xx_hal_hrtim.h>

Data Fields

uint32_t | Filter
uint32_t | Latch

Detailed Description

External event filtering in timing units configuration definition.

Definition at line 335 of file stm32h7xx_hal_hrtim.h.

Field Documentation

uint32_t HRTIM_TimerEventFilteringCfgTypeDef::Filter

Specifies the type of event filtering within the timing unit This parameter can be a value of HRTIM Timer External Event Filter

Definition at line 336 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_TimerEventFilteringConfig().

uint32_t HRTIM_TimerEventFilteringCfgTypeDef::Latch

Specifies whether or not the signal is latched This parameter can be a value of HRTIM Timer External Event Latch

Definition at line 338 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_TimerEventFilteringConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hrtim.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM_DeadTimeCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HRTIM_DeadTimeCfgTypeDef Struct Reference
HRTIM Exported Types

Dead time feature configuration definition. More...

#include <stm32h7xx_hal_hrtim.h>

Data Fields

uint32_t | Prescaler
uint32_t | RisingValue
uint32_t | RisingSign
uint32_t | RisingLock
uint32_t | RisingSignLock
uint32_t | FallingValue
uint32_t | FallingSign
uint32_t | FallingLock
uint32_t | FallingSignLock

Detailed Description

Dead time feature configuration definition.

Definition at line 345 of file stm32h7xx_hal_hrtim.h.

Field Documentation

uint32_t HRTIM_DeadTimeCfgTypeDef::FallingLock

Specifies whether or not deadtime falling settings (value and sign) are write protected This parameter can be a value of HRTIM Deadtime Falling Lock

Definition at line 360 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_DeadTimeConfig().

uint32_t HRTIM_DeadTimeCfgTypeDef::FallingSign

Specifies whether the deadtime is positive or negative on falling edge This parameter can be a value of HRTIM Deadtime Falling Sign

Definition at line 358 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_DeadTimeConfig().

uint32_t HRTIM_DeadTimeCfgTypeDef::FallingSignLock

Specifies whether or not deadtime falling sign is write protected This parameter can be a value of HRTIM Deadtime Falling Sign Lock

Definition at line 362 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_DeadTimeConfig().

uint32_t HRTIM_DeadTimeCfgTypeDef::FallingValue

Specifies the Deadtime following a falling edge This parameter can be a number between 0x0 and 0x1FF

Definition at line 356 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_DeadTimeConfig().

uint32_t HRTIM_DeadTimeCfgTypeDef::Prescaler

Specifies the Deadtime Prescaler This parameter can be a value of HRTIM Deadtime Prescaler Ratio

Definition at line 346 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_DeadTimeConfig().

uint32_t HRTIM_DeadTimeCfgTypeDef::RisingLock

Specifies whether or not deadtime rising settings (value and sign) are write protected This parameter can be a value of HRTIM Deadtime Rising Lock

Definition at line 352 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_DeadTimeConfig().

uint32_t HRTIM_DeadTimeCfgTypeDef::RisingSign

Specifies whether the deadtime is positive or negative on rising edge This parameter can be a value of HRTIM Deadtime Rising Sign

Definition at line 350 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_DeadTimeConfig().

uint32_t HRTIM_DeadTimeCfgTypeDef::RisingSignLock

Specifies whether or not deadtime rising sign is write protected This parameter can be a value of HRTIM Deadtime Rising Sign Lock

Definition at line 354 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_DeadTimeConfig().

uint32_t HRTIM_DeadTimeCfgTypeDef::RisingValue

Specifies the Deadtime following a rising edge This parameter can be a number between 0x0 and 0x1FF

Definition at line 348 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_DeadTimeConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hrtim.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM_ChopperModeCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HRTIM_ChopperModeCfgTypeDef Struct Reference
HRTIM Exported Types

Chopper mode configuration definition. More...

#include <stm32h7xx_hal_hrtim.h>

Data Fields

uint32_t | CarrierFreq
uint32_t | DutyCycle
uint32_t | StartPulse

Detailed Description

Chopper mode configuration definition.

Definition at line 369 of file stm32h7xx_hal_hrtim.h.

Field Documentation

uint32_t HRTIM_ChopperModeCfgTypeDef::CarrierFreq

Specifies the Timer carrier frequency value. This parameter can be a value of HRTIM Chopper Frequency

Definition at line 370 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_ChopperModeConfig().

uint32_t HRTIM_ChopperModeCfgTypeDef::DutyCycle

Specifies the Timer chopper duty cycle value. This parameter can be a value of HRTIM Chopper Duty Cycle

Definition at line 372 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_ChopperModeConfig().

uint32_t HRTIM_ChopperModeCfgTypeDef::StartPulse

Specifies the Timer pulse width value. This parameter can be a value of HRTIM Chopper Start Pulse Width

Definition at line 374 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_ChopperModeConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hrtim.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM_EventCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HRTIM_EventCfgTypeDef Struct Reference
HRTIM Exported Types

External event channel configuration definition. More...

#include <stm32h7xx_hal_hrtim.h>

Data Fields

uint32_t | Source
uint32_t | Polarity
uint32_t | Sensitivity
uint32_t | Filter
uint32_t | FastMode

Detailed Description

External event channel configuration definition.

Definition at line 381 of file stm32h7xx_hal_hrtim.h.

Field Documentation

uint32_t HRTIM_EventCfgTypeDef::FastMode

Indicates whether or not low latency mode is enabled for the external event This parameter can be a value of HRTIM External Event Fast Mode

Definition at line 390 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_EventConfig(), HAL_HRTIM_SimpleCaptureChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), and HRTIM_EventConfig().

uint32_t HRTIM_EventCfgTypeDef::Filter

Defines the frequency used to sample the External Event and the length of the digital filter This parameter can be a value of HRTIM External Event Filter

Definition at line 388 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_EventConfig(), HAL_HRTIM_SimpleCaptureChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), and HRTIM_EventConfig().

uint32_t HRTIM_EventCfgTypeDef::Polarity

Specifies the polarity of the external event (in case of level sensitivity) This parameter can be a value of HRTIM External Event Polarity

Definition at line 384 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_EventConfig(), HAL_HRTIM_SimpleCaptureChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), and HRTIM_EventConfig().

uint32_t HRTIM_EventCfgTypeDef::Sensitivity

Specifies the sensitivity of the external event This parameter can be a value of HRTIM External Event Sensitivity

Definition at line 386 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_EventConfig(), HAL_HRTIM_SimpleCaptureChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), and HRTIM_EventConfig().

uint32_t HRTIM_EventCfgTypeDef::Source

Identifies the source of the external event This parameter can be a value of HRTIM External Event Sources

Definition at line 382 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_EventConfig(), HAL_HRTIM_SimpleCaptureChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), and HRTIM_EventConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hrtim.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM_FaultCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HRTIM_FaultCfgTypeDef Struct Reference
HRTIM Exported Types

Fault channel configuration definition. More...

#include <stm32h7xx_hal_hrtim.h>

Data Fields

uint32_t | Source
uint32_t | Polarity
uint32_t | Filter
uint32_t | Lock

Detailed Description

Fault channel configuration definition.

Definition at line 397 of file stm32h7xx_hal_hrtim.h.

Field Documentation

uint32_t HRTIM_FaultCfgTypeDef::Filter

Defines the frequency used to sample the Fault input and the length of the digital filter This parameter can be a value of HRTIM Fault Filter

Definition at line 402 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_FaultConfig().

uint32_t HRTIM_FaultCfgTypeDef::Lock

Indicates whether or not fault programming bits are write protected This parameter can be a value of HRTIM Fault Lock

Definition at line 404 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_FaultConfig().

uint32_t HRTIM_FaultCfgTypeDef::Polarity

Specifies the polarity of the fault event This parameter can be a value of HRTIM Fault Polarity

Definition at line 400 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_FaultConfig().

uint32_t HRTIM_FaultCfgTypeDef::Source

Identifies the source of the fault This parameter can be a value of HRTIM Fault Sources

Definition at line 398 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_FaultConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hrtim.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM_BurstModeCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HRTIM_BurstModeCfgTypeDef Struct Reference
HRTIM Exported Types

Burst mode configuration definition. More...

#include <stm32h7xx_hal_hrtim.h>

Data Fields

uint32_t | Mode
uint32_t | ClockSource
uint32_t | Prescaler
uint32_t | PreloadEnable
uint32_t | Trigger
uint32_t | IdleDuration
uint32_t | Period

Detailed Description

Burst mode configuration definition.

Definition at line 411 of file stm32h7xx_hal_hrtim.h.

Field Documentation

uint32_t HRTIM_BurstModeCfgTypeDef::ClockSource

Specifies the burst mode clock source This parameter can be a value of HRTIM Burst Mode Clock Source

Definition at line 414 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_BurstModeConfig().

uint32_t HRTIM_BurstModeCfgTypeDef::IdleDuration

Specifies number of periods during which the selected timers are in idle state This parameter can be a number between 0x0 and 0xFFFF

Definition at line 422 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_BurstModeConfig().

uint32_t HRTIM_BurstModeCfgTypeDef::Mode

Specifies the burst mode operating mode This parameter can be a value of HRTIM Burst Mode Operating Mode

Definition at line 412 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_BurstModeConfig().

uint32_t HRTIM_BurstModeCfgTypeDef::Period

Specifies burst mode repetition period This parameter can be a number between 0x1 and 0xFFFF

Definition at line 424 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_BurstModeConfig().

uint32_t HRTIM_BurstModeCfgTypeDef::PreloadEnable

Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER) This parameter can be a combination of HRTIM Burst Mode Register Preload Enable

Definition at line 418 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_BurstModeConfig().

uint32_t HRTIM_BurstModeCfgTypeDef::Prescaler

Specifies the burst mode prescaler This parameter can be a value of HRTIM Burst Mode Prescaler

Definition at line 416 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_BurstModeConfig().

uint32_t HRTIM_BurstModeCfgTypeDef::Trigger

Specifies the event(s) trigering the burst operation This parameter can be a combination of HRTIM Burst Mode Trigger

Definition at line 420 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_BurstModeConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hrtim.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM_ADCTriggerCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HRTIM_ADCTriggerCfgTypeDef Struct Reference
HRTIM Exported Types

ADC trigger configuration definition. More...

#include <stm32h7xx_hal_hrtim.h>

Data Fields

uint32_t | UpdateSource
uint32_t | Trigger

Detailed Description

ADC trigger configuration definition.

Definition at line 431 of file stm32h7xx_hal_hrtim.h.

Field Documentation

uint32_t HRTIM_ADCTriggerCfgTypeDef::Trigger

Specifies the event(s) triggering the ADC conversion This parameter can be a value of HRTIM ADC Trigger Event

Definition at line 434 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_ADCTriggerConfig().

uint32_t HRTIM_ADCTriggerCfgTypeDef::UpdateSource

Specifies the ADC trigger update source This parameter can be a combination of HRTIM ADC Trigger Update Source

Definition at line 432 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_ADCTriggerConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hrtim.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Max Timer

Defines
HRTIM Max Timer
HRTIM Exported Constants

Defines

#define MAX_HRTIM_TIMER 6U

Define Documentation

#define MAX_HRTIM_TIMER 6U

Definition at line 64 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Timer Index

Defines
HRTIM Timer Index
HRTIM Exported Constants

Constants defining the timer indexes. More...

Defines

#define | HRTIM_TIMERINDEX_TIMER_A (uint32_t)0x0U
#define | HRTIM_TIMERINDEX_TIMER_B (uint32_t)0x1U
#define | HRTIM_TIMERINDEX_TIMER_C (uint32_t)0x2U
#define | HRTIM_TIMERINDEX_TIMER_D (uint32_t)0x3U
#define | HRTIM_TIMERINDEX_TIMER_E (uint32_t)0x4U
#define | HRTIM_TIMERINDEX_MASTER (uint32_t)0x5U
#define | HRTIM_TIMERINDEX_COMMON (uint32_t)0xFFU

Detailed Description

Constants defining the timer indexes.

Define Documentation

#define HRTIM_TIMERINDEX_COMMON (uint32_t)0xFFU

Index used to access HRTIM common registers

Definition at line 457 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_IRQHandler().

#define HRTIM_TIMERINDEX_MASTER (uint32_t)0x5U

Index used to access master registers

Definition at line 456 of file stm32h7xx_hal_hrtim.h.

Referenced by GetTimerIdxFromDMAHandle(), HAL_HRTIM_BurstDMAConfig(), HAL_HRTIM_Init(), HAL_HRTIM_IRQHandler(), HAL_HRTIM_SimpleBaseStart_DMA(), HAL_HRTIM_SimpleBaseStart_IT(), HAL_HRTIM_SimpleBaseStop_DMA(), HAL_HRTIM_SimpleBaseStop_IT(), HAL_HRTIM_TimeBaseConfig(), HAL_HRTIM_WaveformCompareConfig(), HAL_HRTIM_WaveformCounterStart_DMA(), HAL_HRTIM_WaveformCounterStart_IT(), HAL_HRTIM_WaveformCounterStop_DMA(), HAL_HRTIM_WaveformCounterStop_IT(), HAL_HRTIM_WaveformTimerConfig(), HRTIM_CompareUnitConfig(), HRTIM_DMAMasterCplt(), HRTIM_ForceRegistersUpdate(), HRTIM_GetDMAHandleFromTimerIdx(), and HRTIM_Master_ISR().

#define HRTIM_TIMERINDEX_TIMER_A (uint32_t)0x0U

Index used to access timer A registers

Definition at line 451 of file stm32h7xx_hal_hrtim.h.

Referenced by GetTimerIdxFromDMAHandle(), HAL_HRTIM_BurstDMAConfig(), HAL_HRTIM_Init(), HAL_HRTIM_WaveformCounterStart_DMA(), HAL_HRTIM_WaveformCounterStart_IT(), HAL_HRTIM_WaveformCounterStop_DMA(), HAL_HRTIM_WaveformCounterStop_IT(), HRTIM_ForceRegistersUpdate(), HRTIM_GetDMAHandleFromTimerIdx(), and HRTIM_TimingUnitWaveform_Config().

#define HRTIM_TIMERINDEX_TIMER_B (uint32_t)0x1U

Index used to access timer B registers

Definition at line 452 of file stm32h7xx_hal_hrtim.h.

Referenced by GetTimerIdxFromDMAHandle(), HAL_HRTIM_BurstDMAConfig(), HRTIM_ForceRegistersUpdate(), HRTIM_GetDMAHandleFromTimerIdx(), and HRTIM_TimingUnitWaveform_Config().

#define HRTIM_TIMERINDEX_TIMER_C (uint32_t)0x2U

Index used to access timer C registers

Definition at line 453 of file stm32h7xx_hal_hrtim.h.

Referenced by GetTimerIdxFromDMAHandle(), HAL_HRTIM_BurstDMAConfig(), HRTIM_ForceRegistersUpdate(), HRTIM_GetDMAHandleFromTimerIdx(), and HRTIM_TimingUnitWaveform_Config().

#define HRTIM_TIMERINDEX_TIMER_D (uint32_t)0x3U

Index used to access timer D registers

Definition at line 454 of file stm32h7xx_hal_hrtim.h.

Referenced by GetTimerIdxFromDMAHandle(), HAL_HRTIM_BurstDMAConfig(), HRTIM_ForceRegistersUpdate(), HRTIM_GetDMAHandleFromTimerIdx(), and HRTIM_TimingUnitWaveform_Config().

#define HRTIM_TIMERINDEX_TIMER_E (uint32_t)0x4U

Index used to access timer E registers

Definition at line 455 of file stm32h7xx_hal_hrtim.h.

Referenced by GetTimerIdxFromDMAHandle(), HAL_HRTIM_BurstDMAConfig(), HRTIM_ForceRegistersUpdate(), HRTIM_GetDMAHandleFromTimerIdx(), and HRTIM_TimingUnitWaveform_Config().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Timer identifier

Defines
HRTIM Timer identifier
HRTIM Exported Constants

Constants defining timer identifiers. More...

Defines

#define | HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN)
#define | HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN)
#define | HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN)
#define | HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN)
#define | HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN)
#define | HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN)
#define | IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U)

Detailed Description

Constants defining timer identifiers.

Define Documentation

#define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN)

Master identifier

Definition at line 467 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformCounterStart_DMA(), HAL_HRTIM_WaveformCounterStart_IT(), HAL_HRTIM_WaveformCounterStop_DMA(), and HAL_HRTIM_WaveformCounterStop_IT().

#define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN)

Timer A identifier

Definition at line 468 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN)

Timer B identifier

Definition at line 469 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN)

Timer C identifier

Definition at line 470 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN)

Timer D identifier

Definition at line 471 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN)

Timer E identifier

Definition at line 472 of file stm32h7xx_hal_hrtim.h.

#define IS_HRTIM_TIMERID ( TIMERID ) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U)

Definition at line 474 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformCounterStart(), HAL_HRTIM_WaveformCounterStart_DMA(), HAL_HRTIM_WaveformCounterStart_IT(), HAL_HRTIM_WaveformCounterStop(), HAL_HRTIM_WaveformCounterStop_DMA(), and HAL_HRTIM_WaveformCounterStop_IT().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Compare Unit

Defines
HRTIM Compare Unit
HRTIM Exported Constants

Constants defining compare unit identifiers. More...

Defines

#define | HRTIM_COMPAREUNIT_1 (uint32_t)0x00000001U
#define | HRTIM_COMPAREUNIT_2 (uint32_t)0x00000002U
#define | HRTIM_COMPAREUNIT_3 (uint32_t)0x00000004U
#define | HRTIM_COMPAREUNIT_4 (uint32_t)0x00000008U

Detailed Description

Constants defining compare unit identifiers.

Define Documentation

#define HRTIM_COMPAREUNIT_1 (uint32_t)0x00000001U

Compare unit 1 identifier.

Definition at line 484 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_WaveformCompareConfig(), and HRTIM_CompareUnitConfig().

#define HRTIM_COMPAREUNIT_2 (uint32_t)0x00000002U

Compare unit 2 identifier.

Definition at line 485 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_WaveformCompareConfig(), and HRTIM_CompareUnitConfig().

#define HRTIM_COMPAREUNIT_3 (uint32_t)0x00000004U

Compare unit 3 identifier.

Definition at line 486 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformCompareConfig(), and HRTIM_CompareUnitConfig().

#define HRTIM_COMPAREUNIT_4 (uint32_t)0x00000008U

Compare unit 4 identifier.

Definition at line 487 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformCompareConfig(), and HRTIM_CompareUnitConfig().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Capture Unit

Defines
HRTIM Capture Unit
HRTIM Exported Constants

Constants defining capture unit identifiers. More...

Defines

#define | HRTIM_CAPTUREUNIT_1 (uint32_t)0x00000001U
#define | HRTIM_CAPTUREUNIT_2 (uint32_t)0x00000002U

Detailed Description

Constants defining capture unit identifiers.

Define Documentation

#define HRTIM_CAPTUREUNIT_1 (uint32_t)0x00000001U

Capture unit 1 identifier.

Definition at line 497 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_GetCapturedValue(), HAL_HRTIM_SimpleCaptureStart(), HAL_HRTIM_SimpleCaptureStart_DMA(), HAL_HRTIM_SimpleCaptureStart_IT(), HAL_HRTIM_SimpleCaptureStop(), HAL_HRTIM_SimpleCaptureStop_DMA(), HAL_HRTIM_SimpleCaptureStop_IT(), HAL_HRTIM_SoftwareCapture(), HAL_HRTIM_WaveformCaptureConfig(), and HRTIM_CaptureUnitConfig().

#define HRTIM_CAPTUREUNIT_2 (uint32_t)0x00000002U

Capture unit 2 identifier.

Definition at line 498 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_GetCapturedValue(), HAL_HRTIM_SimpleCaptureStart(), HAL_HRTIM_SimpleCaptureStart_DMA(), HAL_HRTIM_SimpleCaptureStart_IT(), HAL_HRTIM_SimpleCaptureStop(), HAL_HRTIM_SimpleCaptureStop_DMA(), HAL_HRTIM_SimpleCaptureStop_IT(), HAL_HRTIM_SoftwareCapture(), HAL_HRTIM_WaveformCaptureConfig(), and HRTIM_CaptureUnitConfig().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Timer Output

Defines
HRTIM Timer Output
HRTIM Exported Constants

Constants defining timer output identifiers. More...

Defines

#define | HRTIM_OUTPUT_TA1 (uint32_t)0x00000001U
#define | HRTIM_OUTPUT_TA2 (uint32_t)0x00000002U
#define | HRTIM_OUTPUT_TB1 (uint32_t)0x00000004U
#define | HRTIM_OUTPUT_TB2 (uint32_t)0x00000008U
#define | HRTIM_OUTPUT_TC1 (uint32_t)0x00000010U
#define | HRTIM_OUTPUT_TC2 (uint32_t)0x00000020U
#define | HRTIM_OUTPUT_TD1 (uint32_t)0x00000040U
#define | HRTIM_OUTPUT_TD2 (uint32_t)0x00000080U
#define | HRTIM_OUTPUT_TE1 (uint32_t)0x00000100U
#define | HRTIM_OUTPUT_TE2 (uint32_t)0x00000200U

Detailed Description

Constants defining timer output identifiers.

Define Documentation

#define HRTIM_OUTPUT_TA1 (uint32_t)0x00000001U

Timer A - Ouput 1 identifier.

Definition at line 508 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_GetDelayedProtectionStatus(), HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimpleOnePulseStart_IT(), HAL_HRTIM_SimpleOnePulseStop_IT(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_SimplePWMStart_IT(), HAL_HRTIM_SimplePWMStop_DMA(), HAL_HRTIM_SimplePWMStop_IT(), HAL_HRTIM_WaveformGetOutputLevel(), HAL_HRTIM_WaveformGetOutputState(), HAL_HRTIM_WaveformSetOutputLevel(), HRTIM_GetDMAFromOCMode(), HRTIM_GetITFromOCMode(), and HRTIM_OutputConfig().

#define HRTIM_OUTPUT_TA2 (uint32_t)0x00000002U

Timer A - Ouput 2 identifier.

Definition at line 509 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_GetDelayedProtectionStatus(), HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimpleOnePulseStart_IT(), HAL_HRTIM_SimpleOnePulseStop_IT(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_SimplePWMStart_IT(), HAL_HRTIM_SimplePWMStop_DMA(), HAL_HRTIM_SimplePWMStop_IT(), HAL_HRTIM_WaveformGetOutputLevel(), HAL_HRTIM_WaveformGetOutputState(), HAL_HRTIM_WaveformSetOutputLevel(), HRTIM_GetDMAFromOCMode(), HRTIM_GetITFromOCMode(), and HRTIM_OutputConfig().

#define HRTIM_OUTPUT_TB1 (uint32_t)0x00000004U

Timer B - Ouput 1 identifier.

Definition at line 510 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_GetDelayedProtectionStatus(), HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimpleOnePulseStart_IT(), HAL_HRTIM_SimpleOnePulseStop_IT(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_SimplePWMStart_IT(), HAL_HRTIM_SimplePWMStop_DMA(), HAL_HRTIM_SimplePWMStop_IT(), HAL_HRTIM_WaveformGetOutputLevel(), HAL_HRTIM_WaveformGetOutputState(), HAL_HRTIM_WaveformSetOutputLevel(), HRTIM_GetDMAFromOCMode(), HRTIM_GetITFromOCMode(), and HRTIM_OutputConfig().

#define HRTIM_OUTPUT_TB2 (uint32_t)0x00000008U

Timer B - Ouput 2 identifier.

Definition at line 511 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_GetDelayedProtectionStatus(), HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimpleOnePulseStart_IT(), HAL_HRTIM_SimpleOnePulseStop_IT(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_SimplePWMStart_IT(), HAL_HRTIM_SimplePWMStop_DMA(), HAL_HRTIM_SimplePWMStop_IT(), HAL_HRTIM_WaveformGetOutputLevel(), HAL_HRTIM_WaveformGetOutputState(), HAL_HRTIM_WaveformSetOutputLevel(), HRTIM_GetDMAFromOCMode(), HRTIM_GetITFromOCMode(), and HRTIM_OutputConfig().

#define HRTIM_OUTPUT_TC1 (uint32_t)0x00000010U

Timer C - Ouput 1 identifier.

Definition at line 512 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_GetDelayedProtectionStatus(), HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimpleOnePulseStart_IT(), HAL_HRTIM_SimpleOnePulseStop_IT(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_SimplePWMStart_IT(), HAL_HRTIM_SimplePWMStop_DMA(), HAL_HRTIM_SimplePWMStop_IT(), HAL_HRTIM_WaveformGetOutputLevel(), HAL_HRTIM_WaveformGetOutputState(), HAL_HRTIM_WaveformSetOutputLevel(), HRTIM_GetDMAFromOCMode(), HRTIM_GetITFromOCMode(), and HRTIM_OutputConfig().

#define HRTIM_OUTPUT_TC2 (uint32_t)0x00000020U

Timer C - Ouput 2 identifier.

Definition at line 513 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_GetDelayedProtectionStatus(), HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimpleOnePulseStart_IT(), HAL_HRTIM_SimpleOnePulseStop_IT(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_SimplePWMStart_IT(), HAL_HRTIM_SimplePWMStop_DMA(), HAL_HRTIM_SimplePWMStop_IT(), HAL_HRTIM_WaveformGetOutputLevel(), HAL_HRTIM_WaveformGetOutputState(), HAL_HRTIM_WaveformSetOutputLevel(), HRTIM_GetDMAFromOCMode(), HRTIM_GetITFromOCMode(), and HRTIM_OutputConfig().

#define HRTIM_OUTPUT_TD1 (uint32_t)0x00000040U

Timer D - Ouput 1 identifier.

Definition at line 514 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_GetDelayedProtectionStatus(), HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimpleOnePulseStart_IT(), HAL_HRTIM_SimpleOnePulseStop_IT(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_SimplePWMStart_IT(), HAL_HRTIM_SimplePWMStop_DMA(), HAL_HRTIM_SimplePWMStop_IT(), HAL_HRTIM_WaveformGetOutputLevel(), HAL_HRTIM_WaveformGetOutputState(), HAL_HRTIM_WaveformSetOutputLevel(), HRTIM_GetDMAFromOCMode(), HRTIM_GetITFromOCMode(), and HRTIM_OutputConfig().

#define HRTIM_OUTPUT_TD2 (uint32_t)0x00000080U

Timer D - Ouput 2 identifier.

Definition at line 515 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_GetDelayedProtectionStatus(), HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimpleOnePulseStart_IT(), HAL_HRTIM_SimpleOnePulseStop_IT(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_SimplePWMStart_IT(), HAL_HRTIM_SimplePWMStop_DMA(), HAL_HRTIM_SimplePWMStop_IT(), HAL_HRTIM_WaveformGetOutputLevel(), HAL_HRTIM_WaveformGetOutputState(), HAL_HRTIM_WaveformSetOutputLevel(), HRTIM_GetDMAFromOCMode(), HRTIM_GetITFromOCMode(), and HRTIM_OutputConfig().

#define HRTIM_OUTPUT_TE1 (uint32_t)0x00000100U

Timer E - Ouput 1 identifier.

Definition at line 516 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_GetDelayedProtectionStatus(), HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimpleOnePulseStart_IT(), HAL_HRTIM_SimpleOnePulseStop_IT(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_SimplePWMStart_IT(), HAL_HRTIM_SimplePWMStop_DMA(), HAL_HRTIM_SimplePWMStop_IT(), HAL_HRTIM_WaveformGetOutputLevel(), HAL_HRTIM_WaveformGetOutputState(), HAL_HRTIM_WaveformSetOutputLevel(), HRTIM_GetDMAFromOCMode(), HRTIM_GetITFromOCMode(), and HRTIM_OutputConfig().

#define HRTIM_OUTPUT_TE2 (uint32_t)0x00000200U

Timer E - Ouput 2 identifier.

Definition at line 517 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_GetDelayedProtectionStatus(), HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimpleOnePulseStart_IT(), HAL_HRTIM_SimpleOnePulseStop_IT(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_SimplePWMStart_IT(), HAL_HRTIM_SimplePWMStop_DMA(), HAL_HRTIM_SimplePWMStop_IT(), HAL_HRTIM_WaveformGetOutputLevel(), HAL_HRTIM_WaveformGetOutputState(), HAL_HRTIM_WaveformSetOutputLevel(), HRTIM_GetDMAFromOCMode(), HRTIM_GetITFromOCMode(), and HRTIM_OutputConfig().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM ADC Trigger

Defines
HRTIM ADC Trigger
HRTIM Exported Constants

Constants defining ADC triggers identifiers. More...

Defines

#define | HRTIM_ADCTRIGGER_1 (uint32_t)0x00000001U
#define | HRTIM_ADCTRIGGER_2 (uint32_t)0x00000002U
#define | HRTIM_ADCTRIGGER_3 (uint32_t)0x00000004U
#define | HRTIM_ADCTRIGGER_4 (uint32_t)0x00000008U

Detailed Description

Constants defining ADC triggers identifiers.

Define Documentation

#define HRTIM_ADCTRIGGER_1 (uint32_t)0x00000001U

ADC trigger 1 identifier.

Definition at line 527 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_ADCTriggerConfig().

#define HRTIM_ADCTRIGGER_2 (uint32_t)0x00000002U

ADC trigger 2 identifier.

Definition at line 528 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_ADCTriggerConfig().

#define HRTIM_ADCTRIGGER_3 (uint32_t)0x00000004U

ADC trigger 3 identifier.

Definition at line 529 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_ADCTriggerConfig().

#define HRTIM_ADCTRIGGER_4 (uint32_t)0x00000008U

ADC trigger 4 identifier.

Definition at line 530 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_ADCTriggerConfig().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM External Event Channels

Defines
HRTIM External Event Channels
HRTIM Exported Constants

Constants defining external event channel identifiers. More...

Defines

#define | HRTIM_EVENT_NONE ((uint32_t)0x00000000U)
#define | HRTIM_EVENT_1 ((uint32_t)0x00000001U)
#define | HRTIM_EVENT_2 ((uint32_t)0x00000002U)
#define | HRTIM_EVENT_3 ((uint32_t)0x00000004U)
#define | HRTIM_EVENT_4 ((uint32_t)0x00000008U)
#define | HRTIM_EVENT_5 ((uint32_t)0x00000010U)
#define | HRTIM_EVENT_6 ((uint32_t)0x00000020U)
#define | HRTIM_EVENT_7 ((uint32_t)0x00000040U)
#define | HRTIM_EVENT_8 ((uint32_t)0x00000080U)
#define | HRTIM_EVENT_9 ((uint32_t)0x00000100U)
#define | HRTIM_EVENT_10 ((uint32_t)0x00000200U)

Detailed Description

Constants defining external event channel identifiers.

Define Documentation

#define HRTIM_EVENT_1 ((uint32_t)0x00000001U)

External event channel 1 identifier.

Definition at line 541 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_TimerEventFilteringConfig(), HRTIM_CaptureUnitConfig(), HRTIM_EventConfig(), and HRTIM_TIM_ResetConfig().

#define HRTIM_EVENT_10 ((uint32_t)0x00000200U)

External event channel 10 identifier.

Definition at line 550 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_TimerEventFilteringConfig(), HRTIM_CaptureUnitConfig(), HRTIM_EventConfig(), and HRTIM_TIM_ResetConfig().

#define HRTIM_EVENT_2 ((uint32_t)0x00000002U)

External event channel 2 identifier.

Definition at line 542 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_TimerEventFilteringConfig(), HRTIM_CaptureUnitConfig(), HRTIM_EventConfig(), and HRTIM_TIM_ResetConfig().

#define HRTIM_EVENT_3 ((uint32_t)0x00000004U)

External event channel 3 identifier.

Definition at line 543 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_TimerEventFilteringConfig(), HRTIM_CaptureUnitConfig(), HRTIM_EventConfig(), and HRTIM_TIM_ResetConfig().

#define HRTIM_EVENT_4 ((uint32_t)0x00000008U)

External event channel 4 identifier.

Definition at line 544 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_TimerEventFilteringConfig(), HRTIM_CaptureUnitConfig(), HRTIM_EventConfig(), and HRTIM_TIM_ResetConfig().

#define HRTIM_EVENT_5 ((uint32_t)0x00000010U)

External event channel 5 identifier.

Definition at line 545 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_TimerEventFilteringConfig(), HRTIM_CaptureUnitConfig(), HRTIM_EventConfig(), and HRTIM_TIM_ResetConfig().

#define HRTIM_EVENT_6 ((uint32_t)0x00000020U)

External event channel 6 identifier.

Definition at line 546 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_TimerEventFilteringConfig(), HRTIM_CaptureUnitConfig(), HRTIM_EventConfig(), and HRTIM_TIM_ResetConfig().

#define HRTIM_EVENT_7 ((uint32_t)0x00000040U)

External event channel 7 identifier.

Definition at line 547 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_TimerEventFilteringConfig(), HRTIM_CaptureUnitConfig(), HRTIM_EventConfig(), and HRTIM_TIM_ResetConfig().

#define HRTIM_EVENT_8 ((uint32_t)0x00000080U)

External event channel 8 identifier.

Definition at line 548 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_TimerEventFilteringConfig(), HRTIM_CaptureUnitConfig(), HRTIM_EventConfig(), and HRTIM_TIM_ResetConfig().

#define HRTIM_EVENT_9 ((uint32_t)0x00000100U)

External event channel 9 identifier.

Definition at line 549 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_TimerEventFilteringConfig(), HRTIM_CaptureUnitConfig(), HRTIM_EventConfig(), and HRTIM_TIM_ResetConfig().

#define HRTIM_EVENT_NONE ((uint32_t)0x00000000U)

Undefined event channel.

Definition at line 540 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_TimerEventFilteringConfig().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Fault Channel

Defines
HRTIM Fault Channel
HRTIM Exported Constants

Constants defining fault channel identifiers. More...

Defines

#define | HRTIM_FAULT_1 ((uint32_t)0x01U)
#define | HRTIM_FAULT_2 ((uint32_t)0x02U)
#define | HRTIM_FAULT_3 ((uint32_t)0x04U)
#define | HRTIM_FAULT_4 ((uint32_t)0x08U)
#define | HRTIM_FAULT_5 ((uint32_t)0x10U)

Detailed Description

Constants defining fault channel identifiers.

Define Documentation

#define HRTIM_FAULT_1 ((uint32_t)0x01U)

Fault channel 1 identifier.

Definition at line 560 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_FaultConfig(), and HAL_HRTIM_FaultModeCtl().

#define HRTIM_FAULT_2 ((uint32_t)0x02U)

Fault channel 2 identifier.

Definition at line 561 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_FaultConfig(), and HAL_HRTIM_FaultModeCtl().

#define HRTIM_FAULT_3 ((uint32_t)0x04U)

Fault channel 3 identifier.

Definition at line 562 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_FaultConfig(), and HAL_HRTIM_FaultModeCtl().

#define HRTIM_FAULT_4 ((uint32_t)0x08U)

Fault channel 4 identifier.

Definition at line 563 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_FaultConfig(), and HAL_HRTIM_FaultModeCtl().

#define HRTIM_FAULT_5 ((uint32_t)0x10U)

Fault channel 5 identifier.

Definition at line 564 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_FaultConfig(), and HAL_HRTIM_FaultModeCtl().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Prescaler Ratio

Defines
HRTIM Prescaler Ratio
HRTIM Exported Constants

Constants defining timer high-resolution clock prescaler ratio. More...

Defines

#define | HRTIM_PRESCALERRATIO_MUL32 ((uint32_t)0x00000000U)
#define | HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001U)
#define | HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002U)
#define | HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003U)
#define | HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004U)
#define | HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005U)
#define | HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006U)
#define | HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007U)

Detailed Description

Constants defining timer high-resolution clock prescaler ratio.

Define Documentation

#define HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005U)

fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz).

Definition at line 580 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006U)

fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz).

Definition at line 581 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007U)

fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz).

Definition at line 582 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001U)

fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz).

Definition at line 576 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004U)

fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz).

Definition at line 579 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_PRESCALERRATIO_MUL32 ((uint32_t)0x00000000U)

fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz).

Definition at line 575 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003U)

fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz).

Definition at line 578 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002U)

fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz).

Definition at line 577 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Mode

Defines
HRTIM Mode
HRTIM Exported Constants

Constants defining timer counter operating mode. More...

Defines

#define | HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008U)
#define | HRTIM_MODE_SINGLESHOT ((uint32_t)0x00000000U)
#define | HRTIM_MODE_SINGLESHOT_RETRIGGERABLE ((uint32_t)0x00000010U)

Detailed Description

Constants defining timer counter operating mode.

Define Documentation

#define HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008U)

The timer operates in continuous (free-running) mode.

Definition at line 592 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_MODE_SINGLESHOT ((uint32_t)0x00000000U)

The timer operates in non retriggerable single-shot mode.

Definition at line 593 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE ((uint32_t)0x00000010U)

The timer operates in retriggerable single-shot mode.

Definition at line 594 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Half Mode Enable

Defines
HRTIM Half Mode Enable
HRTIM Exported Constants

Constants defining half mode enabling status. More...

Defines

#define | HRTIM_HALFMODE_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_HALFMODE_ENABLED ((uint32_t)0x00000020U)

Detailed Description

Constants defining half mode enabling status.

Define Documentation

#define HRTIM_HALFMODE_DISABLED ((uint32_t)0x00000000U)

Half mode is disabled.

Definition at line 604 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_HALFMODE_ENABLED ((uint32_t)0x00000020U)

Half mode is enabled.

Definition at line 605 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Start On Sync Input Event

Defines
HRTIM Start On Sync Input Event
HRTIM Exported Constants

Constants defining the timer behavior following the synchronization event. More...

Defines

#define | HRTIM_SYNCSTART_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM)

Detailed Description

Constants defining the timer behavior following the synchronization event.

Define Documentation

#define HRTIM_SYNCSTART_DISABLED ((uint32_t)0x00000000U)

Synchronization input event has effect on the timer.

Definition at line 615 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM)

Synchronization input event starts the timer.

Definition at line 616 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Reset On Sync Input Event

Defines
HRTIM Reset On Sync Input Event
HRTIM Exported Constants

Constants defining the timer behavior following the synchronization event. More...

Defines

#define | HRTIM_SYNCRESET_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM)

Detailed Description

Constants defining the timer behavior following the synchronization event.

Define Documentation

#define HRTIM_SYNCRESET_DISABLED ((uint32_t)0x00000000U)

Synchronization input event has effect on the timer.

Definition at line 626 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM)

Synchronization input event resets the timer.

Definition at line 627 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM DAC Synchronization

Defines
HRTIM DAC Synchronization
HRTIM Exported Constants

Constants defining on which output the DAC synchronization event is sent. More...

Defines

#define | HRTIM_DACSYNC_NONE ((uint32_t)0x00000000U)
#define | HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0)
#define | HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1)
#define | HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0)

Detailed Description

Constants defining on which output the DAC synchronization event is sent.

Define Documentation

#define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0)

DAC synchronization event generated on DACTrigOut1 output upon timer update.

Definition at line 638 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1)

DAC synchronization event generated on DACTrigOut2 output upon timer update.

Definition at line 639 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0)

DAC update generated on DACTrigOut3 output upon timer update.

Definition at line 640 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_DACSYNC_NONE ((uint32_t)0x00000000U)

No DAC synchronization event generated.

Definition at line 637 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Register Preload Enable

Defines
HRTIM Register Preload Enable
HRTIM Exported Constants

Constants defining whether a write access into a preloadable register is done into the active or the preload register. More...

Defines

#define | HRTIM_PRELOAD_DISABLED 0x00000000U
#define | HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN)

Detailed Description

Constants defining whether a write access into a preloadable register is done into the active or the preload register.

Define Documentation

#define HRTIM_PRELOAD_DISABLED 0x00000000U

Preload disabled: the write access is directly done into the active register.

Definition at line 651 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN)

Preload enabled: the write access is done into the preload register.

Definition at line 652 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Update Gating

Defines
HRTIM Update Gating
HRTIM Exported Constants

Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3. More...

Defines

#define | HRTIM_UPDATEGATING_INDEPENDENT ((uint32_t)0x00000000U)
#define | HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0)
#define | HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1)
#define | HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)
#define | HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2)
#define | HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0)
#define | HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1)
#define | HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)
#define | HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3)

Detailed Description

Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3.

Define Documentation

#define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0)

Update done when the DMA burst transfer is completed.

Definition at line 664 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1)

Update done on timer roll-over following a DMA burst transfer completion.

Definition at line 665 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_UPDATEGATING_INDEPENDENT ((uint32_t)0x00000000U)

Update done independently from the DMA burst transfer completion.

Definition at line 663 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)

Slave timer only - Update done on a rising edge of HRTIM update enable input 1.

Definition at line 666 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1)

Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1.

Definition at line 669 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2)

Slave timer only - Update done on a rising edge of HRTIM update enable input 2.

Definition at line 667 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)

Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2.

Definition at line 670 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0)

Slave timer only - Update done on a rising edge of HRTIM update enable input 3.

Definition at line 668 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3)

Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3.

Definition at line 671 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Timer Burst Mode

Defines
HRTIM Timer Burst Mode
HRTIM Exported Constants

Constants defining how the timer behaves during a burst mode operation. More...

Defines

#define | HRTIM_TIMERBURSTMODE_MAINTAINCLOCK ((uint32_t)0x000000U)
#define | HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM)

Detailed Description

Constants defining how the timer behaves during a burst mode operation.

Define Documentation

#define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK ((uint32_t)0x000000U)

Timer counter clock is maintained and the timer operates normally.

Definition at line 682 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM)

Timer counter clock is stopped and the counter is reset.

Definition at line 683 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Timer Repetition Update

Defines
HRTIM Timer Repetition Update
HRTIM Exported Constants

Constants defining whether registers are updated when the timer repetition period is completed (either due to roll-over or reset events) More...

Defines

#define | HRTIM_UPDATEONREPETITION_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU)

Detailed Description

Constants defining whether registers are updated when the timer repetition period is completed (either due to roll-over or reset events)

Define Documentation

#define HRTIM_UPDATEONREPETITION_DISABLED ((uint32_t)0x00000000U)

Update on repetition disabled.

Definition at line 695 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU)

Update on repetition enabled.

Definition at line 696 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_TimingUnitWaveform_Config().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Timer Push Pull Mode

Defines
HRTIM Timer Push Pull Mode
HRTIM Exported Constants

Constants defining whether or not the puhs-pull mode is enabled for a timer. More...

Defines

#define | HRTIM_TIMPUSHPULLMODE_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_TIMPUSHPULLMODE_ENABLED ((uint32_t)HRTIM_TIMCR_PSHPLL)

Detailed Description

Constants defining whether or not the puhs-pull mode is enabled for a timer.

Define Documentation

#define HRTIM_TIMPUSHPULLMODE_DISABLED ((uint32_t)0x00000000U)

Push-Pull mode disabled.

Definition at line 708 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_TimingUnitWaveform_Config().

#define HRTIM_TIMPUSHPULLMODE_ENABLED ((uint32_t)HRTIM_TIMCR_PSHPLL)

Push-Pull mode enabled.

Definition at line 709 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_TimingUnitWaveform_Config().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Timer Fault Enabling

Defines
HRTIM Timer Fault Enabling
HRTIM Exported Constants

Constants defining whether a faut channel is enabled for a timer. More...

Defines

#define | HRTIM_TIMFAULTENABLE_NONE ((uint32_t)0x00000000U)
#define | HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN)
#define | HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN)
#define | HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN)
#define | HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN)
#define | HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN)

Detailed Description

Constants defining whether a faut channel is enabled for a timer.

Define Documentation

#define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN)

Fault 1 enabled.

Definition at line 720 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN)

Fault 2 enabled.

Definition at line 721 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN)

Fault 3 enabled.

Definition at line 722 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN)

Fault 4 enabled.

Definition at line 723 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN)

Fault 5 enabled.

Definition at line 724 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMFAULTENABLE_NONE ((uint32_t)0x00000000U)

No fault enabled.

Definition at line 719 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Timer Fault Lock

Defines
HRTIM Timer Fault Lock
HRTIM Exported Constants

Constants defining whether or not fault enabling bits are write protected for a timer. More...

Defines

#define | HRTIM_TIMFAULTLOCK_READWRITE ((uint32_t)0x00000000U)
#define | HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTLCK)

Detailed Description

Constants defining whether or not fault enabling bits are write protected for a timer.

Define Documentation

#define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTLCK)

Timer fault enabling bits are read only.

Definition at line 736 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMFAULTLOCK_READWRITE ((uint32_t)0x00000000U)

Timer fault enabling bits are read/write.

Definition at line 735 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Timer Deadtime Insertion

Defines
HRTIM Timer Deadtime Insertion
HRTIM Exported Constants

Constants defining whether or not fault the dead time insertion feature is enabled for a timer. More...

Defines

#define | HRTIM_TIMDEADTIMEINSERTION_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN

Detailed Description

Constants defining whether or not fault the dead time insertion feature is enabled for a timer.

Define Documentation

#define HRTIM_TIMDEADTIMEINSERTION_DISABLED ((uint32_t)0x00000000U)

Output 1 and output 2 signals are independent.

Definition at line 747 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN

Deadtime is inserted between output 1 and output 2.

Definition at line 748 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Timer Delayed Protection Mode

Defines
HRTIM Timer Delayed Protection Mode
HRTIM Exported Constants

Constants defining all possible delayed protection modes for a timer. More...

Defines

#define | HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 (HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)

Detailed Description

Constants defining all possible delayed protection modes for a timer.

Also definethe source and outputs on which the delayed protection schemes are applied

Define Documentation

#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)

Timers A, B, C: Balanced Idle on external Event 6.

Definition at line 764 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_TimingUnitWaveform_Config().

#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)

Timers A, B, C: Balanced Idle on external Event 7.

Definition at line 768 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_TimingUnitWaveform_Config().

#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)

Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6.

Definition at line 763 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)

Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7.

Definition at line 767 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)

Timers A, B, C: Output 1 delayed Idle on external Event 7.

Definition at line 765 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 (HRTIM_OUTR_DLYPRTEN)

Timers A, B, C: Output 1 delayed Idle on external Event 6.

Definition at line 761 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)

Timers A, B, C: Output 2 delayed Idle on external Event 7.

Definition at line 766 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)

Timers A, B, C: Output 2 delayed Idle on external Event 6.

Definition at line 762 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000U)

No action.

Definition at line 760 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)

Timers D, E: Balanced Idle on external Event 6.

Definition at line 774 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)

Timers D, E: Balanced Idle on external Event 7.

Definition at line 778 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)

Timers D, E: Output 1 and output 2 delayed Idle on external Event 6.

Definition at line 773 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)

Timers D, E: Output 1 and output2 delayed Idle on external Event 7.

Definition at line 777 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)

Timers D, E: Output 1 delayed Idle on external Event 7.

Definition at line 775 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN)

Timers D, E: Output 1 delayed Idle on external Event 6.

Definition at line 771 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)

Timers D, E: Output 2 delayed Idle on external Event 7.

Definition at line 776 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)

Timers D, E: Output 2 delayed Idle on external Event 6.

Definition at line 772 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000U)

No action.

Definition at line 770 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Timer Update Trigger

Defines
HRTIM Timer Update Trigger
HRTIM Exported Constants

Constants defining whether the registers update is done synchronously with any other timer or master update. More...

Defines

#define | HRTIM_TIMUPDATETRIGGER_NONE ((uint32_t)0x00000000U)
#define | HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU)
#define | HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU)
#define | HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU)
#define | HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU)
#define | HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU)
#define | HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU)

Detailed Description

Constants defining whether the registers update is done synchronously with any other timer or master update.

Define Documentation

#define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU)

Register update is triggered by the master timer update.

Definition at line 790 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMUPDATETRIGGER_NONE ((uint32_t)0x00000000U)

Register update is disabled.

Definition at line 789 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU)

Register update is triggered by the timer A update.

Definition at line 791 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU)

Register update is triggered by the timer B update.

Definition at line 792 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU)

Register update is triggered by the timer C update.

Definition at line 793 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU)

Register update is triggered by the timer D update.

Definition at line 794 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU)

Register update is triggered by the timer E update.

Definition at line 795 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Timer Reset Trigger

Defines
HRTIM Timer Reset Trigger
HRTIM Exported Constants

Constants defining the events that can be selected to trigger the reset of the timer counter. More...

Defines

#define | HRTIM_TIMRESETTRIGGER_NONE ((uint32_t)0x00000000U)
#define | HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE)
#define | HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2)
#define | HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4)
#define | HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER)
#define | HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1)
#define | HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2)
#define | HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3)
#define | HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4)
#define | HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1)
#define | HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2)
#define | HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3)
#define | HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4)
#define | HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5)
#define | HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6)
#define | HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7)
#define | HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8)
#define | HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9)
#define | HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10)
#define | HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1)
#define | HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2)
#define | HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4)
#define | HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1)
#define | HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2)
#define | HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4)
#define | HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1)
#define | HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2)
#define | HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4)
#define | HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1)
#define | HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2)
#define | HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4)

Detailed Description

Constants defining the events that can be selected to trigger the reset of the timer counter.

Define Documentation

#define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2)

The timer counter is reset upon Timer Compare 2 event.

Definition at line 808 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4)

The timer counter is reset upon Timer Compare 4 event.

Definition at line 809 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1)

The timer counter is reset upon external event 1.

Definition at line 815 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_TIM_ResetConfig().

#define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10)

The timer counter is reset upon external event 10.

Definition at line 824 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_TIM_ResetConfig().

#define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2)

The timer counter is reset upon external event 2.

Definition at line 816 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_TIM_ResetConfig().

#define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3)

The timer counter is reset upon external event 3.

Definition at line 817 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_TIM_ResetConfig().

#define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4)

The timer counter is reset upon external event 4.

Definition at line 818 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_TIM_ResetConfig().

#define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5)

The timer counter is reset upon external event 5.

Definition at line 819 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_TIM_ResetConfig().

#define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6)

The timer counter is reset upon external event 6.

Definition at line 820 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_TIM_ResetConfig().

#define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7)

The timer counter is reset upon external event 7.

Definition at line 821 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_TIM_ResetConfig().

#define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8)

The timer counter is reset upon external event 8.

Definition at line 822 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_TIM_ResetConfig().

#define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9)

The timer counter is reset upon external event 9.

Definition at line 823 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_TIM_ResetConfig().

#define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1)

The timer counter is reset upon master timer Compare 1 event.

Definition at line 811 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2)

The timer counter is reset upon master timer Compare 2 event.

Definition at line 812 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3)

The timer counter is reset upon master timer Compare 3 event.

Definition at line 813 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4)

The timer counter is reset upon master timer Compare 4 event.

Definition at line 814 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER)

The timercounter is reset upon master timer period event.

Definition at line 810 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMRESETTRIGGER_NONE ((uint32_t)0x00000000U)

No counter reset trigger.

Definition at line 806 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1)

The timer counter is reset upon other timer Compare 1 event.

Definition at line 825 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2)

The timer counter is reset upon other timer Compare 2 event.

Definition at line 826 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4)

The timer counter is reset upon other timer Compare 4 event.

Definition at line 827 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1)

The timer counter is reset upon other timer Compare 1 event.

Definition at line 828 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2)

The timer counter is reset upon other timer Compare 2 event.

Definition at line 829 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4)

The timer counter is reset upon other timer Compare 4 event.

Definition at line 830 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1)

The timer counter is reset upon other timer Compare 1 event.

Definition at line 831 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2)

The timer counter is reset upon other timer Compare 2 event.

Definition at line 832 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4)

The timer counter is reset upon other timer Compare 4 event.

Definition at line 833 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1)

The timer counter is reset upon other timer Compare 1 event.

Definition at line 834 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2)

The timer counter is reset upon other timer Compare 2 event.

Definition at line 835 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4)

The timer counter is reset upon other timer Compare 4 event.

Definition at line 836 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE)

The timer counter is reset upon update event.

Definition at line 807 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Timer Reset Update

Defines
HRTIM Timer Reset Update
HRTIM Exported Constants

Constants defining whether the register are updated upon Timerx counter reset or roll-over to 0 after reaching the period value in continuous mode. More...

Defines

#define | HRTIM_TIMUPDATEONRESET_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU)

Detailed Description

Constants defining whether the register are updated upon Timerx counter reset or roll-over to 0 after reaching the period value in continuous mode.

Define Documentation

#define HRTIM_TIMUPDATEONRESET_DISABLED ((uint32_t)0x00000000U)

Update by timer x reset / roll-over disabled.

Definition at line 848 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU)

Update by timer x reset / roll-over enabled.

Definition at line 849 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Compare Unit Auto Delayed Mode

Defines
HRTIM Compare Unit Auto Delayed Mode
HRTIM Exported Constants

Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare), or in auto-delayed mode. More...

Defines

#define | HRTIM_AUTODELAYEDMODE_REGULAR ((uint32_t)0x00000000U)
#define | HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0)
#define | HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1)
#define | HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0)

Detailed Description

Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare), or in auto-delayed mode.

Define Documentation

#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0)

Compare event generated only if a capture has occurred.

Definition at line 862 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1)

Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing).

Definition at line 863 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformCompareConfig().

#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0)

Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing).

Definition at line 864 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformCompareConfig().

#define HRTIM_AUTODELAYEDMODE_REGULAR ((uint32_t)0x00000000U)

standard compare mode.

Definition at line 861 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimplePWMChannelConfig(), and HAL_HRTIM_WaveformCompareConfig().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Simple OC Mode

Defines
HRTIM Simple OC Mode
HRTIM Exported Constants

Constants defining the behavior of the output signal when the timer operates in basic output compare mode. More...

Defines

#define | HRTIM_BASICOCMODE_TOGGLE (0x00000001U)
#define | HRTIM_BASICOCMODE_INACTIVE (0x00000002U)
#define | HRTIM_BASICOCMODE_ACTIVE (0x00000003U)

Detailed Description

Constants defining the behavior of the output signal when the timer operates in basic output compare mode.

Define Documentation

#define HRTIM_BASICOCMODE_ACTIVE (0x00000003U)

Output forced to inactive level when the timer counter reaches the compare value.

Definition at line 877 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig().

#define HRTIM_BASICOCMODE_INACTIVE (0x00000002U)

Output forced to active level when the timer counter reaches the compare value.

Definition at line 876 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig().

#define HRTIM_BASICOCMODE_TOGGLE (0x00000001U)

Output toggles when the timer counter reaches the compare value.

Definition at line 875 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Output Polarity

Defines
HRTIM Output Polarity
HRTIM Exported Constants

Constants defining the polarity of a timer output. More...

Defines

#define | HRTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U)
#define | HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1)

Detailed Description

Constants defining the polarity of a timer output.

Define Documentation

#define HRTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U)

Output is acitve HIGH.

Definition at line 887 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1)

Output is active LOW.

Definition at line 888 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Output Set Source

Defines
HRTIM Output Set Source
HRTIM Exported Constants

Constants defining the events that can be selected to configure the set crossbar of a timer output. More...

Defines

#define | HRTIM_OUTPUTSET_NONE ((uint32_t)0x00000000U)
#define | HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC)
#define | HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER)
#define | HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1)
#define | HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2)
#define | HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3)
#define | HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4)
#define | HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER)
#define | HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1)
#define | HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2)
#define | HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3)
#define | HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4)
#define | HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
#define | HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
#define | HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
#define | HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
#define | HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
#define | HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
#define | HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
#define | HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
#define | HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
#define | HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1)
#define | HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2)
#define | HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3)
#define | HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4)
#define | HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5)
#define | HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6)
#define | HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7)
#define | HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8)
#define | HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9)
#define | HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10)
#define | HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE)

Detailed Description

Constants defining the events that can be selected to configure the set crossbar of a timer output.

Define Documentation

#define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1)

External event 1 forces the output to its active state.

Definition at line 920 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10)

External event 10 forces the output to its active state.

Definition at line 929 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2)

External event 2 forces the output to its active state.

Definition at line 921 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3)

External event 3 forces the output to its active state.

Definition at line 922 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4)

External event 4 forces the output to its active state.

Definition at line 923 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5)

External event 5 forces the output to its active state.

Definition at line 924 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6)

External event 6 forces the output to its active state.

Definition at line 925 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7)

External event 7 forces the output to its active state.

Definition at line 926 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8)

External event 8 forces the output to its active state.

Definition at line 927 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9)

External event 9 forces the output to its active state.

Definition at line 928 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1)

Master Timer compare 1 event forces the output to its active state.

Definition at line 907 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2)

Master Timer compare 2 event forces the output to its active state.

Definition at line 908 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3)

Master Timer compare 3 event forces the output to its active state.

Definition at line 909 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4)

Master Timer compare 4 event forces the output to its active state.

Definition at line 910 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER)

The master timer period event forces the output to its active state.

Definition at line 906 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_NONE ((uint32_t)0x00000000U)

Reset the output set crossbar.

Definition at line 899 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig().

#define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC)

Timer reset event coming solely from software or SYNC input forces the output to its active state.

Definition at line 900 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1)

Timer compare 1 event forces the output to its active state.

Definition at line 902 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimplePWMChannelConfig(), HRTIM_GetDMAFromOCMode(), and HRTIM_GetITFromOCMode().

#define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2)

Timer compare 2 event forces the output to its active state.

Definition at line 903 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimplePWMChannelConfig(), HRTIM_GetDMAFromOCMode(), and HRTIM_GetITFromOCMode().

#define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3)

Timer compare 3 event forces the output to its active state.

Definition at line 904 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4)

Timer compare 4 event forces the output to its active state.

Definition at line 905 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)

Timer event 1 forces the output to its active state.

Definition at line 911 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)

Timer event 2 forces the output to its active state.

Definition at line 912 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)

Timer event 3 forces the output to its active state.

Definition at line 913 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)

Timer event 4 forces the output to its active state.

Definition at line 914 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)

Timer event 5 forces the output to its active state.

Definition at line 915 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)

Timer event 6 forces the output to its active state.

Definition at line 916 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)

Timer event 7 forces the output to its active state.

Definition at line 917 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)

Timer event 8 forces the output to its active state.

Definition at line 918 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)

Timer event 9 forces the output to its active state.

Definition at line 919 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER)

Timer period event forces the output to its active state.

Definition at line 901 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOnePulseChannelConfig(), and HAL_HRTIM_SimplePWMChannelConfig().

#define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE)

Timer register update event forces the output to its active state.

Definition at line 930 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Output Reset Source

Defines
HRTIM Output Reset Source
HRTIM Exported Constants

Constants defining the events that can be selected to configure the set crossbar of a timer output. More...

Defines

#define | HRTIM_OUTPUTRESET_NONE ((uint32_t)0x00000000U)
#define | HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC)
#define | HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER)
#define | HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1)
#define | HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2)
#define | HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3)
#define | HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4)
#define | HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER)
#define | HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1)
#define | HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2)
#define | HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3)
#define | HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4)
#define | HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
#define | HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
#define | HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
#define | HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
#define | HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
#define | HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
#define | HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
#define | HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
#define | HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
#define | HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1)
#define | HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2)
#define | HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3)
#define | HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4)
#define | HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5)
#define | HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6)
#define | HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7)
#define | HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8)
#define | HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9)
#define | HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10)
#define | HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE)

Detailed Description

Constants defining the events that can be selected to configure the set crossbar of a timer output.

Define Documentation

#define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1)

External event 1 forces the output to its inactive state.

Definition at line 962 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10)

External event 10 forces the output to its inactive state.

Definition at line 971 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2)

External event 2 forces the output to its inactive state.

Definition at line 963 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3)

External event 3 forces the output to its inactive state.

Definition at line 964 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4)

External event 4 forces the output to its inactive state.

Definition at line 965 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5)

External event 5 forces the output to its inactive state.

Definition at line 966 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6)

External event 6 forces the output to its inactive state.

Definition at line 967 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7)

External event 7 forces the output to its inactive state.

Definition at line 968 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8)

External event 8 forces the output to its inactive state.

Definition at line 969 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9)

External event 9 forces the output to its inactive state.

Definition at line 970 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1)

Master Timer compare 1 event forces the output to its inactive state.

Definition at line 949 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2)

Master Timer compare 2 event forces the output to its inactive state.

Definition at line 950 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3)

Master Timer compare 3 event forces the output to its inactive state.

Definition at line 951 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4)

Master Timer compare 4 event forces the output to its inactive state.

Definition at line 952 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER)

The master timer period event forces the output to its inactive state.

Definition at line 948 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_NONE ((uint32_t)0x00000000U)

Reset the output reset crossbar.

Definition at line 941 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig().

#define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC)

Timer reset event coming solely from software or SYNC input forces the output to its inactive state.

Definition at line 942 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1)

Timer compare 1 event forces the output to its inactive state.

Definition at line 944 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig().

#define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2)

Timer compare 2 event forces the output to its inactive state.

Definition at line 945 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig().

#define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3)

Timer compare 3 event forces the output to its inactive state.

Definition at line 946 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4)

Timer compare 4 event forces the output to its inactive state.

Definition at line 947 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)

Timer event 1 forces the output to its inactive state.

Definition at line 953 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)

Timer event 2 forces the output to its inactive state.

Definition at line 954 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)

Timer event 3 forces the output to its inactive state.

Definition at line 955 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)

Timer event 4 forces the output to its inactive state.

Definition at line 956 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)

Timer event 5 forces the output to its inactive state.

Definition at line 957 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)

Timer event 6 forces the output to its inactive state.

Definition at line 958 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)

Timer event 7 forces the output to its inactive state.

Definition at line 959 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)

Timer event 8 forces the output to its inactive state.

Definition at line 960 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)

Timer event 9 forces the output to its inactive state.

Definition at line 961 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER)

Timer period event forces the output to its inactive state.

Definition at line 943 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE)

Timer register update event forces the output to its inactive state.

Definition at line 972 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Output Idle Mode

Defines
HRTIM Output Idle Mode
HRTIM Exported Constants

Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered. More...

Defines

#define | HRTIM_OUTPUTIDLEMODE_NONE ((uint32_t)0x00000000U)
#define | HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1)

Detailed Description

Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered.

Define Documentation

#define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1)

The output is in idle state when requested by the burst mode controller.

Definition at line 984 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTIDLEMODE_NONE ((uint32_t)0x00000000U)

The output is not affected by the burst mode operation.

Definition at line 983 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), and HAL_HRTIM_SimplePWMChannelConfig().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Output IDLE Level

Defines
HRTIM Output IDLE Level
HRTIM Exported Constants

Constants defining the output level when output is in IDLE state. More...

Defines

#define | HRTIM_OUTPUTIDLELEVEL_INACTIVE ((uint32_t)0x00000000U)
#define | HRTIM_OUTPUTIDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1)

Detailed Description

Constants defining the output level when output is in IDLE state.

Define Documentation

#define HRTIM_OUTPUTIDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1)

Output at active level when in IDLE state.

Definition at line 995 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_OutputConfig().

#define HRTIM_OUTPUTIDLELEVEL_INACTIVE ((uint32_t)0x00000000U)

Output at inactive level when in IDLE state.

Definition at line 994 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Output FAULT Level

Defines
HRTIM Output FAULT Level
HRTIM Exported Constants

Constants defining the output level when output is in FAULT state. More...

Defines

#define | HRTIM_OUTPUTFAULTLEVEL_NONE ((uint32_t)0x00000000U)
#define | HRTIM_OUTPUTFAULTLEVEL_ACTIVE (HRTIM_OUTR_FAULT1_0)
#define | HRTIM_OUTPUTFAULTLEVEL_INACTIVE (HRTIM_OUTR_FAULT1_1)
#define | HRTIM_OUTPUTFAULTLEVEL_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0)

Detailed Description

Constants defining the output level when output is in FAULT state.

Define Documentation

#define HRTIM_OUTPUTFAULTLEVEL_ACTIVE (HRTIM_OUTR_FAULT1_0)

Output at active level when in FAULT state.

Definition at line 1006 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTFAULTLEVEL_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0)

Output is tri-stated when in FAULT state.

Definition at line 1008 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTFAULTLEVEL_INACTIVE (HRTIM_OUTR_FAULT1_1)

Output at inactive level when in FAULT state.

Definition at line 1007 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTFAULTLEVEL_NONE ((uint32_t)0x00000000U)

The output is not affected by the fault input.

Definition at line 1005 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), and HAL_HRTIM_SimplePWMChannelConfig().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Output Chopper Mode Enable

Defines
HRTIM Output Chopper Mode Enable
HRTIM Exported Constants

Constants defining whether or not chopper mode is enabled for a timer output. More...

Defines

#define | HRTIM_OUTPUTCHOPPERMODE_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1)

Detailed Description

Constants defining whether or not chopper mode is enabled for a timer output.

Define Documentation

#define HRTIM_OUTPUTCHOPPERMODE_DISABLED ((uint32_t)0x00000000U)

Output signal is not altered.

Definition at line 1019 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), and HAL_HRTIM_SimplePWMChannelConfig().

#define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1)

Output signal is chopped by a carrier signal.

Definition at line 1020 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Output Burst Mode Entry Delayed

Defines
HRTIM Output Burst Mode Entry Delayed
HRTIM Exported Constants

Constants defining the idle mode entry is delayed by forcing a deadtime insertion before switching the outputs to their idle state. More...

Defines

#define | HRTIM_OUTPUTBURSTMODEENTRY_REGULAR ((uint32_t)0x00000000U)
#define | HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1)

Detailed Description

Constants defining the idle mode entry is delayed by forcing a deadtime insertion before switching the outputs to their idle state.

Define Documentation

#define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1)

Deadtime is inserted on output before entering the idle mode.

Definition at line 1032 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR ((uint32_t)0x00000000U)

The programmed Idle state is applied immediately to the Output.

Definition at line 1031 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), and HAL_HRTIM_SimplePWMChannelConfig().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Capture Unit Trigger

Defines
HRTIM Capture Unit Trigger
HRTIM Exported Constants

Constants defining the events that can be selected to trigger the capture of the timing unit counter. More...

Defines

#define | HRTIM_CAPTURETRIGGER_NONE ((uint32_t)0x00000000U)
#define | HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT)
#define | HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT)
#define | HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT)
#define | HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT)
#define | HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT)
#define | HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT)
#define | HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT)
#define | HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT)
#define | HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT)
#define | HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT)
#define | HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT)
#define | HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET)
#define | HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST)
#define | HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TIMACMP1)
#define | HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TIMACMP2)
#define | HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET)
#define | HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST)
#define | HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TIMBCMP1)
#define | HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TIMBCMP2)
#define | HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET)
#define | HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST)
#define | HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TIMCCMP1)
#define | HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TIMCCMP2)
#define | HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET)
#define | HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST)
#define | HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TIMDCMP1)
#define | HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TIMDCMP2)
#define | HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET)
#define | HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST)
#define | HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TIMECMP1)
#define | HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TIMECMP2)

Detailed Description

Constants defining the events that can be selected to trigger the capture of the timing unit counter.

Define Documentation

#define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT)

The External event 1 triggers the Capture.

Definition at line 1045 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_CaptureUnitConfig().

#define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT)

The External event 10 triggers the Capture.

Definition at line 1054 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_CaptureUnitConfig().

#define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT)

The External event 2 triggers the Capture.

Definition at line 1046 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_CaptureUnitConfig().

#define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT)

The External event 3 triggers the Capture.

Definition at line 1047 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_CaptureUnitConfig().

#define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT)

The External event 4 triggers the Capture.

Definition at line 1048 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_CaptureUnitConfig().

#define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT)

The External event 5 triggers the Capture.

Definition at line 1049 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_CaptureUnitConfig().

#define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT)

The External event 6 triggers the Capture.

Definition at line 1050 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_CaptureUnitConfig().

#define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT)

The External event 7 triggers the Capture.

Definition at line 1051 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_CaptureUnitConfig().

#define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT)

The External event 8 triggers the Capture.

Definition at line 1052 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_CaptureUnitConfig().

#define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT)

The External event 9 triggers the Capture.

Definition at line 1053 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_CaptureUnitConfig().

#define HRTIM_CAPTURETRIGGER_NONE ((uint32_t)0x00000000U)

Capture trigger is disabled.

Definition at line 1043 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init(), HAL_HRTIM_SimpleCaptureStop(), HAL_HRTIM_SimpleCaptureStop_DMA(), and HAL_HRTIM_SimpleCaptureStop_IT().

#define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST)

Capture is triggered by TA1 output active to inactive transition.

Definition at line 1056 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET)

Capture is triggered by TA1 output inactive to active transition.

Definition at line 1055 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST)

Capture is triggered by TB1 output active to inactive transition.

Definition at line 1060 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET)

Capture is triggered by TB1 output inactive to active transition.

Definition at line 1059 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST)

Capture is triggered by TC1 output active to inactive transition.

Definition at line 1064 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET)

Capture is triggered by TC1 output inactive to active transition.

Definition at line 1063 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST)

Capture is triggered by TD1 output active to inactive transition.

Definition at line 1068 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET)

Capture is triggered by TD1 output inactive to active transition.

Definition at line 1067 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST)

Capture is triggered by TE1 output active to inactive transition.

Definition at line 1072 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET)

Capture is triggered by TE1 output inactive to active transition.

Definition at line 1071 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TIMACMP1)

Timer A Compare 1 triggers Capture.

Definition at line 1057 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TIMACMP2)

Timer A Compare 2 triggers Capture.

Definition at line 1058 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TIMBCMP1)

Timer B Compare 1 triggers Capture.

Definition at line 1061 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TIMBCMP2)

Timer B Compare 2 triggers Capture.

Definition at line 1062 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TIMCCMP1)

Timer C Compare 1 triggers Capture.

Definition at line 1065 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TIMCCMP2)

Timer C Compare 2 triggers Capture.

Definition at line 1066 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TIMDCMP1)

Timer D Compare 1 triggers Capture.

Definition at line 1069 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TIMDCMP2)

Timer D Compare 2 triggers Capture.

Definition at line 1070 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TIMECMP1)

Timer E Compare 1 triggers Capture.

Definition at line 1073 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TIMECMP2)

Timer E Compare 2 triggers Capture.

Definition at line 1074 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT)

The update event triggers the Capture.

Definition at line 1044 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Timer External Event Filter

Defines
HRTIM Timer External Event Filter
HRTIM Exported Constants

Constants defining the event filtering apploed to external events by a timer. More...

Defines

#define | HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
#define | HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
#define | HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
#define | HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define | HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
#define | HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define | HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define | HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)

Detailed Description

Constants defining the event filtering apploed to external events by a timer.

Define Documentation

#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)

Blanking from counter reset/roll-over to Compare 1

Definition at line 1086 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)

Blanking from counter reset/roll-over to Compare 2

Definition at line 1087 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

Blanking from counter reset/roll-over to Compare 3

Definition at line 1088 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)

Blanking from counter reset/roll-over to Compare 4

Definition at line 1089 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)

Blanking from another timing unit: TIMFLTR1 source

Definition at line 1090 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)

Blanking from another timing unit: TIMFLTR2 source

Definition at line 1091 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

Blanking from another timing unit: TIMFLTR3 source

Definition at line 1092 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)

Blanking from another timing unit: TIMFLTR4 source

Definition at line 1093 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)

Blanking from another timing unit: TIMFLTR5 source

Definition at line 1094 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)

Blanking from another timing unit: TIMFLTR6 source

Definition at line 1095 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

Blanking from another timing unit: TIMFLTR7 source

Definition at line 1096 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)

Blanking from another timing unit: TIMFLTR8 source

Definition at line 1097 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)

Definition at line 1085 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)

Windowing from counter reset/roll-over to Compare 2

Definition at line 1098 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)

Windowing from counter reset/roll-over to Compare 3

Definition at line 1099 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)

Windowing from another timing unit: TIMWIN source

Definition at line 1100 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Timer External Event Latch

Defines
HRTIM Timer External Event Latch
HRTIM Exported Constants

Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends. More...

Defines

#define | HRTIM_TIMEVENTLATCH_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH

Detailed Description

Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends.

Define Documentation

#define HRTIM_TIMEVENTLATCH_DISABLED ((uint32_t)0x00000000U)

Event is ignored if it happens during a blank, or passed through during a window.

Definition at line 1112 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH

Event is latched and delayed till the end of the blanking or windowing period.

Definition at line 1113 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Deadtime Prescaler Ratio

Defines
HRTIM Deadtime Prescaler Ratio
HRTIM Exported Constants

Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG) More...

Defines

#define | HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 ((uint32_t)0x00000000U)
#define | HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0)
#define | HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1)
#define | HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)
#define | HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2)
#define | HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0)
#define | HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1)
#define | HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)

Detailed Description

Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG)

Define Documentation

#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)

fDTG = fHRTIM.

Definition at line 1127 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)

fDTG = fHRTIM / 16.

Definition at line 1131 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2)

fDTG = fHRTIM / 2.

Definition at line 1128 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0)

fDTG = fHRTIM / 4.

Definition at line 1129 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1)

fDTG = fHRTIM / 8.

Definition at line 1130 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1)

fDTG = fHRTIM * 2.

Definition at line 1126 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0)

fDTG = fHRTIM * 4.

Definition at line 1125 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 ((uint32_t)0x00000000U)

fDTG = fHRTIM * 8.

Definition at line 1124 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Deadtime Rising Sign

Defines
HRTIM Deadtime Rising Sign
HRTIM Exported Constants

Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge. More...

Defines

#define | HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE ((uint32_t)0x00000000U)
#define | HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR)

Detailed Description

Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge.

Define Documentation

#define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR)

Negative deadtime on rising edge.

Definition at line 1143 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE ((uint32_t)0x00000000U)

Positive deadtime on rising edge.

Definition at line 1142 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Deadtime Rising Lock

Defines
HRTIM Deadtime Rising Lock
HRTIM Exported Constants

Constants defining whether or not the deadtime (rising sign and value) is write protected. More...

Defines

#define | HRTIM_TIMDEADTIME_RISINGLOCK_WRITE ((uint32_t)0x00000000U)
#define | HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK)

Detailed Description

Constants defining whether or not the deadtime (rising sign and value) is write protected.

Define Documentation

#define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK)

Deadtime rising value and sign is read-only.

Definition at line 1155 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE ((uint32_t)0x00000000U)

Deadtime rising value and sign is writeable.

Definition at line 1154 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Deadtime Rising Sign Lock

Defines
HRTIM Deadtime Rising Sign Lock
HRTIM Exported Constants

Constants defining whether or not the deadtime rising sign is write protected. More...

Defines

#define | HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE ((uint32_t)0x00000000U)
#define | HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK)

Detailed Description

Constants defining whether or not the deadtime rising sign is write protected.

Define Documentation

#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK)

Deadtime rising sign is read-only.

Definition at line 1167 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE ((uint32_t)0x00000000U)

Deadtime rising sign is writable.

Definition at line 1166 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Deadtime Falling Sign

Defines
HRTIM Deadtime Falling Sign
HRTIM Exported Constants

Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge. More...

Defines

#define | HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE ((uint32_t)0x00000000U)
#define | HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF)

Detailed Description

Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge.

Define Documentation

#define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF)

Negative deadtime on falling edge.

Definition at line 1179 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE ((uint32_t)0x00000000U)

Positive deadtime on falling edge.

Definition at line 1178 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Deadtime Falling Lock

Defines
HRTIM Deadtime Falling Lock
HRTIM Exported Constants

Constants defining whether or not the deadtime (falling sign and value) is write protected. More...

Defines

#define | HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE ((uint32_t)0x00000000U)
#define | HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK)

Detailed Description

Constants defining whether or not the deadtime (falling sign and value) is write protected.

Define Documentation

#define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK)

Deadtime falling value and sign is read-only.

Definition at line 1191 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE ((uint32_t)0x00000000U)

Deadtime falling value and sign is writeable.

Definition at line 1190 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Deadtime Falling Sign Lock

Defines
HRTIM Deadtime Falling Sign Lock
HRTIM Exported Constants

Constants defining whether or not the deadtime falling sign is write protected. More...

Defines

#define | HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE ((uint32_t)0x00000000U)
#define | HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK)

Detailed Description

Constants defining whether or not the deadtime falling sign is write protected.

Define Documentation

#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK)

Deadtime falling sign is read-only.

Definition at line 1203 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE ((uint32_t)0x00000000U)

Deadtime falling sign is writeable.

Definition at line 1202 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Chopper Frequency

Defines
HRTIM Chopper Frequency
HRTIM Exported Constants

Constants defining the frequency of the generated high frequency carrier. More...

Defines

#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV16 ((uint32_t)0x000000U)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV32 (HRTIM_CHPR_CARFRQ_0)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV48 (HRTIM_CHPR_CARFRQ_1)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV80 (HRTIM_CHPR_CARFRQ_2)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)

Detailed Description

Constants defining the frequency of the generated high frequency carrier.

Define Documentation

#define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)

fCHPFRQ = fHRTIM / 112.

Definition at line 1219 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)

fCHPFRQ = fHRTIM / 128.

Definition at line 1220 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3)

fCHPFRQ = fHRTIM / 144.

Definition at line 1221 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PRESCALERRATIO_DIV16 ((uint32_t)0x000000U)

fCHPFRQ = fHRTIM / 16.

Definition at line 1213 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0)

fCHPFRQ = fHRTIM / 160.

Definition at line 1222 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1)

fCHPFRQ = fHRTIM / 176.

Definition at line 1223 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)

fCHPFRQ = fHRTIM / 192.

Definition at line 1224 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2)

fCHPFRQ = fHRTIM / 208.

Definition at line 1225 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)

fCHPFRQ = fHRTIM / 224.

Definition at line 1226 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)

fCHPFRQ = fHRTIM / 240.

Definition at line 1227 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)

fCHPFRQ = fHRTIM / 256.

Definition at line 1228 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PRESCALERRATIO_DIV32 (HRTIM_CHPR_CARFRQ_0)

fCHPFRQ = fHRTIM / 32.

Definition at line 1214 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PRESCALERRATIO_DIV48 (HRTIM_CHPR_CARFRQ_1)

fCHPFRQ = fHRTIM / 48.

Definition at line 1215 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PRESCALERRATIO_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)

fCHPFRQ = fHRTIM / 64.

Definition at line 1216 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PRESCALERRATIO_DIV80 (HRTIM_CHPR_CARFRQ_2)

fCHPFRQ = fHRTIM / 80.

Definition at line 1217 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PRESCALERRATIO_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)

fCHPFRQ = fHRTIM / 96.

Definition at line 1218 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Chopper Duty Cycle

Defines
HRTIM Chopper Duty Cycle
HRTIM Exported Constants

Constants defining the duty cycle of the generated high frequency carrier Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8) More...

Defines

#define | HRTIM_CHOPPER_DUTYCYCLE_0 ((uint32_t)0x000000U)
#define | HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0)
#define | HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1)
#define | HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0)
#define | HRTIM_CHOPPER_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2)
#define | HRTIM_CHOPPER_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0)
#define | HRTIM_CHOPPER_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1)
#define | HRTIM_CHOPPER_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0)

Detailed Description

Constants defining the duty cycle of the generated high frequency carrier Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)

Define Documentation

#define HRTIM_CHOPPER_DUTYCYCLE_0 ((uint32_t)0x000000U)

Only 1st pulse is present.

Definition at line 1239 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0)

Duty cycle of the carrier signal is 12.5 %.

Definition at line 1240 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1)

Duty cycle of the carrier signal is 25 %.

Definition at line 1241 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0)

Duty cycle of the carrier signal is 37.5 %.

Definition at line 1242 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2)

Duty cycle of the carrier signal is 50 %.

Definition at line 1243 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0)

Duty cycle of the carrier signal is 62.5 %.

Definition at line 1244 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1)

Duty cycle of the carrier signal is 75 %.

Definition at line 1245 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0)

Duty cycle of the carrier signal is 87.5 %.

Definition at line 1246 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Chopper Start Pulse Width

Defines
HRTIM Chopper Start Pulse Width
HRTIM Exported Constants

Constants defining the pulse width of the first pulse of the generated high frequency carrier. More...

Defines

#define | HRTIM_CHOPPER_PULSEWIDTH_16 ((uint32_t)0x000000U)
#define | HRTIM_CHOPPER_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0)
#define | HRTIM_CHOPPER_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1)
#define | HRTIM_CHOPPER_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)
#define | HRTIM_CHOPPER_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2)
#define | HRTIM_CHOPPER_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)
#define | HRTIM_CHOPPER_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)
#define | HRTIM_CHOPPER_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)
#define | HRTIM_CHOPPER_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3)
#define | HRTIM_CHOPPER_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0)
#define | HRTIM_CHOPPER_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1)
#define | HRTIM_CHOPPER_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)
#define | HRTIM_CHOPPER_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2)
#define | HRTIM_CHOPPER_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)
#define | HRTIM_CHOPPER_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)
#define | HRTIM_CHOPPER_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)

Detailed Description

Constants defining the pulse width of the first pulse of the generated high frequency carrier.

Define Documentation

#define HRTIM_CHOPPER_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)

tSTPW = tHRTIM x 112.

Definition at line 1263 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)

tSTPW = tHRTIM x 128.

Definition at line 1264 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3)

tSTPW = tHRTIM x 144.

Definition at line 1265 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PULSEWIDTH_16 ((uint32_t)0x000000U)

tSTPW = tHRTIM x 16.

Definition at line 1257 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0)

tSTPW = tHRTIM x 160.

Definition at line 1266 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1)

tSTPW = tHRTIM x 176.

Definition at line 1267 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)

tSTPW = tHRTIM x 192.

Definition at line 1268 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2)

tSTPW = tHRTIM x 208.

Definition at line 1269 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)

tSTPW = tHRTIM x 224.

Definition at line 1270 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)

tSTPW = tHRTIM x 240.

Definition at line 1271 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)

tSTPW = tHRTIM x 256.

Definition at line 1272 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0)

tSTPW = tHRTIM x 32.

Definition at line 1258 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1)

tSTPW = tHRTIM x 48.

Definition at line 1259 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)

tSTPW = tHRTIM x 64.

Definition at line 1260 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2)

tSTPW = tHRTIM x 80.

Definition at line 1261 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_CHOPPER_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)

tSTPW = tHRTIM x 96.

Definition at line 1262 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Synchronization Options

Defines
HRTIM Synchronization Options
HRTIM Exported Constants

Constants defining the options for synchronizing multiple HRTIM instances, as a master unit (generating a synchronization signal) or as a slave (waiting for a trigger to be synchronized) More...

Defines

#define | HRTIM_SYNCOPTION_NONE ((uint32_t)0x00000000U)
#define | HRTIM_SYNCOPTION_MASTER ((uint32_t)0x00000001U)
#define | HRTIM_SYNCOPTION_SLAVE ((uint32_t)0x00000002U)

Detailed Description

Constants defining the options for synchronizing multiple HRTIM instances, as a master unit (generating a synchronization signal) or as a slave (waiting for a trigger to be synchronized)

Define Documentation

#define HRTIM_SYNCOPTION_MASTER ((uint32_t)0x00000001U)

HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT).

Definition at line 1285 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init().

#define HRTIM_SYNCOPTION_NONE ((uint32_t)0x00000000U)

HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT).

Definition at line 1284 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_SYNCOPTION_SLAVE ((uint32_t)0x00000002U)

HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN).

Definition at line 1286 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Synchronization Input Source

Defines
HRTIM Synchronization Input Source
HRTIM Exported Constants

Constants defining defining the synchronization input source. More...

Defines

#define | HRTIM_SYNCINPUTSOURCE_NONE ((uint32_t)0x00000000U)
#define | HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1
#define | HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0)

Detailed Description

Constants defining defining the synchronization input source.

Define Documentation

#define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0)

A positive pulse on SYNCIN input triggers the HRTIM.

Definition at line 1297 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1

The HRTIM is synchronized with the on-chip timer.

Definition at line 1296 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_SYNCINPUTSOURCE_NONE ((uint32_t)0x00000000U)

disabled. HRTIM is not synchronized and runs in standalone mode.

Definition at line 1295 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Synchronization Output Source

Defines
HRTIM Synchronization Output Source
HRTIM Exported Constants

Constants defining the source and event to be sent on the synchronization outputs. More...

Defines

#define | HRTIM_SYNCOUTPUTSOURCE_MASTER_START ((uint32_t)0x00000000U)
#define | HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0)
#define | HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1)
#define | HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0)

Detailed Description

Constants defining the source and event to be sent on the synchronization outputs.

Define Documentation

#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0)

A pulse is sent on the SYNCOUT output upon master timer compare 1 event.

Definition at line 1309 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START ((uint32_t)0x00000000U)

A pulse is sent on the SYNCOUT output upon master timer start event.

Definition at line 1308 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0)

A pulse is sent on the SYNCOUT output upon timer A compare 1 event.

Definition at line 1311 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1)

A pulse is sent on the SYNCOUT output upon timer A start or reset events.

Definition at line 1310 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Synchronization Output Polarity

Defines
HRTIM Synchronization Output Polarity
HRTIM Exported Constants

Constants defining the routing and conditioning of the synchronization output event. More...

Defines

#define | HRTIM_SYNCOUTPUTPOLARITY_NONE ((uint32_t)0x00000000U)
#define | HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_1)
#define | HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0)

Detailed Description

Constants defining the routing and conditioning of the synchronization output event.

Define Documentation

#define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0)

SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization.

Definition at line 1323 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_SYNCOUTPUTPOLARITY_NONE ((uint32_t)0x00000000U)

Synchronization output event is disabled.

Definition at line 1321 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_1)

SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization.

Definition at line 1322 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM External Event Sources

Defines
HRTIM External Event Sources
HRTIM Exported Constants

Constants defining available sources associated to external events. More...

Defines

#define | HRTIM_EVENTSRC_1 ((uint32_t)0x00000000U)
#define | HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
#define | HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
#define | HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)

Detailed Description

Constants defining available sources associated to external events.

Define Documentation

#define HRTIM_EVENTSRC_1 ((uint32_t)0x00000000U)

External event source 1.

Definition at line 1333 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleCaptureChannelConfig(), and HAL_HRTIM_SimpleOnePulseChannelConfig().

#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)

External event source 2.

Definition at line 1334 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)

External event source 3.

Definition at line 1335 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)

External event source 4.

Definition at line 1336 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM External Event Polarity

Defines
HRTIM External Event Polarity
HRTIM Exported Constants

Constants defining the polarity of an external event. More...

Defines

#define | HRTIM_EVENTPOLARITY_HIGH ((uint32_t)0x00000000U)
#define | HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL)

Detailed Description

Constants defining the polarity of an external event.

Define Documentation

#define HRTIM_EVENTPOLARITY_HIGH ((uint32_t)0x00000000U)

External event is active high.

Definition at line 1346 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL)

External event is active low.

Definition at line 1347 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM External Event Sensitivity

Defines
HRTIM External Event Sensitivity
HRTIM Exported Constants

Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event. More...

Defines

#define | HRTIM_EVENTSENSITIVITY_LEVEL ((uint32_t)0x00000000U)
#define | HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0)
#define | HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1)
#define | HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0)

Detailed Description

Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event.

Define Documentation

#define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0)

External event is active on Rising and Falling edges.

Definition at line 1361 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1)

External event is active on Falling edge.

Definition at line 1360 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTSENSITIVITY_LEVEL ((uint32_t)0x00000000U)

External event is active on level.

Definition at line 1358 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0)

External event is active on Rising edge.

Definition at line 1359 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM External Event Fast Mode

Defines
HRTIM External Event Fast Mode
HRTIM Exported Constants

Constants defining whether or not an external event is programmed in fast mode. More...

Defines

#define | HRTIM_EVENTFASTMODE_DISABLE ((uint32_t)0x00000000U)
#define | HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST)

Detailed Description

Constants defining whether or not an external event is programmed in fast mode.

Define Documentation

#define HRTIM_EVENTFASTMODE_DISABLE ((uint32_t)0x00000000U)

External Event is acting asynchronously on outputs (low latency mode).

Definition at line 1372 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleCaptureChannelConfig(), and HAL_HRTIM_SimpleOnePulseChannelConfig().

#define HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST)

External Event is re-synchronized by the HRTIM logic before acting on outputs.

Definition at line 1373 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM External Event Filter

Defines
HRTIM External Event Filter
HRTIM Exported Constants

Constants defining the frequency used to sample an external event 6 input and the length (N) of the digital filter applied. More...

Defines

#define | HRTIM_EVENTFILTER_NONE ((uint32_t)0x00000000U)
#define | HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0)
#define | HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1)
#define | HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)
#define | HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2)
#define | HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0)
#define | HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1)
#define | HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)
#define | HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3)
#define | HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0)
#define | HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1)
#define | HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)
#define | HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2)
#define | HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0)
#define | HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1)
#define | HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)

Detailed Description

Constants defining the frequency used to sample an external event 6 input and the length (N) of the digital filter applied.

Define Documentation

#define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0)

fSAMPLING= fHRTIM, N=2.

Definition at line 1385 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1)

fSAMPLING= fEEVS/16, N=5.

Definition at line 1394 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)

fSAMPLING= fEEVS/16, N=6.

Definition at line 1395 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2)

fSAMPLING= fEEVS/16, N=8.

Definition at line 1396 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0)

fSAMPLING= fEEVS/32, N=5.

Definition at line 1397 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1)

fSAMPLING= fEEVS/32, N=6.

Definition at line 1398 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)

fSAMPLING= fEEVS/32, N=8.

Definition at line 1399 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1)

fSAMPLING= fHRTIM, N=4.

Definition at line 1386 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)

fSAMPLING= fHRTIM, N=8.

Definition at line 1387 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2)

fSAMPLING= fEEVS/2, N=6.

Definition at line 1388 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0)

fSAMPLING= fEEVS/2, N=8.

Definition at line 1389 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1)

fSAMPLING= fEEVS/4, N=6.

Definition at line 1390 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)

fSAMPLING= fEEVS/4, N=8.

Definition at line 1391 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3)

fSAMPLING= fEEVS/8, N=6.

Definition at line 1392 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0)

fSAMPLING= fEEVS/8, N=8.

Definition at line 1393 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTFILTER_NONE ((uint32_t)0x00000000U)

Filter disabled.

Definition at line 1384 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM External Event Prescaler

Defines
HRTIM External Event Prescaler
HRTIM Exported Constants

Constants defining division ratio between the timer clock frequency fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters. More...

Defines

#define | HRTIM_EVENTPRESCALER_DIV1 ((uint32_t)0x00000000U)
#define | HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0)
#define | HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1)
#define | HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0)

Detailed Description

Constants defining division ratio between the timer clock frequency fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters.

Define Documentation

#define HRTIM_EVENTPRESCALER_DIV1 ((uint32_t)0x00000000U)

fEEVS=fHRTIM.

Definition at line 1411 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0)

fEEVS=fHRTIM / 2.

Definition at line 1412 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1)

fEEVS=fHRTIM / 4.

Definition at line 1413 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0)

fEEVS=fHRTIM / 8.

Definition at line 1414 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Fault Sources

Defines
HRTIM Fault Sources
HRTIM Exported Constants

Constants defining whether a faults is be triggered by any external or internal fault source. More...

Defines

#define | HRTIM_FAULTSOURCE_DIGITALINPUT ((uint32_t)0x00000000U)
#define | HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC)

Detailed Description

Constants defining whether a faults is be triggered by any external or internal fault source.

Define Documentation

#define HRTIM_FAULTSOURCE_DIGITALINPUT ((uint32_t)0x00000000U)

Fault input is FLT input pin.

Definition at line 1425 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC)

Fault input is FLT_Int signal (e.g. internal comparator).

Definition at line 1426 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Fault Polarity

Defines
HRTIM Fault Polarity
HRTIM Exported Constants

Constants defining the polarity of a fault event. More...

Defines

#define | HRTIM_FAULTPOLARITY_LOW ((uint32_t)0x00000000U)
#define | HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P)

Detailed Description

Constants defining the polarity of a fault event.

Define Documentation

#define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P)

Fault input is active high.

Definition at line 1437 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTPOLARITY_LOW ((uint32_t)0x00000000U)

Fault input is active low.

Definition at line 1436 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Fault Filter

Defines
HRTIM Fault Filter
HRTIM Exported Constants

@ brief Constants defining the frequency used to sample the fault input and the length (N) of the digital filter applied More...

Defines

#define | HRTIM_FAULTFILTER_NONE ((uint32_t)0x00000000U)
#define | HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0)
#define | HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1)
#define | HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)
#define | HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2)
#define | HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)
#define | HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)
#define | HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)
#define | HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3)
#define | HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0)
#define | HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1)
#define | HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)
#define | HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2)
#define | HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)
#define | HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)
#define | HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)

Detailed Description

@ brief Constants defining the frequency used to sample the fault input and the length (N) of the digital filter applied

Define Documentation

#define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0)

fSAMPLING= fHRTIM, N=2.

Definition at line 1449 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1)

fSAMPLING= fFLTS/16, N=5.

Definition at line 1458 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)

fSAMPLING= fFLTS/16, N=6.

Definition at line 1459 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2)

fSAMPLING= fFLTS/16, N=8.

Definition at line 1460 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)

fSAMPLING= fFLTS/32, N=5.

Definition at line 1461 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)

fSAMPLING= fFLTS/32, N=6.

Definition at line 1462 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)

fSAMPLING= fFLTS/32, N=8.

Definition at line 1463 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1)

fSAMPLING= fHRTIM, N=4.

Definition at line 1450 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)

fSAMPLING= fHRTIM, N=8.

Definition at line 1451 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2)

fSAMPLING= fFLTS/2, N=6.

Definition at line 1452 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)

fSAMPLING= fFLTS/2, N=8.

Definition at line 1453 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)

fSAMPLING= fFLTS/4, N=6.

Definition at line 1454 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)

fSAMPLING= fFLTS/4, N=8.

Definition at line 1455 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3)

fSAMPLING= fFLTS/8, N=6.

Definition at line 1456 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0)

fSAMPLING= fFLTS/8, N=8.

Definition at line 1457 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTFILTER_NONE ((uint32_t)0x00000000U)

Filter disabled.

Definition at line 1448 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Fault Lock

Defines
HRTIM Fault Lock
HRTIM Exported Constants

Constants defining whether or not the fault programming bits are write protected. More...

Defines

#define | HRTIM_FAULTLOCK_READWRITE ((uint32_t)0x00000000U)
#define | HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK)

Detailed Description

Constants defining whether or not the fault programming bits are write protected.

Define Documentation

#define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK)

Fault settings bits are read only.

Definition at line 1475 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTLOCK_READWRITE ((uint32_t)0x00000000U)

Fault settings bits are read/write.

Definition at line 1474 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM External Fault Prescaler

Defines
HRTIM External Fault Prescaler
HRTIM Exported Constants

Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used by the digital filters. More...

Defines

#define | HRTIM_FAULTPRESCALER_DIV1 ((uint32_t)0x00000000U)
#define | HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0)
#define | HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1)
#define | HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0)

Detailed Description

Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used by the digital filters.

Define Documentation

#define HRTIM_FAULTPRESCALER_DIV1 ((uint32_t)0x00000000U)

fFLTS=fHRTIM.

Definition at line 1487 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0)

fFLTS=fHRTIM / 2.

Definition at line 1488 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1)

fFLTS=fHRTIM / 4.

Definition at line 1489 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0)

fFLTS=fHRTIM / 8.

Definition at line 1490 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Burst Mode Operating Mode

Defines
HRTIM Burst Mode Operating Mode
HRTIM Exported Constants

Constants defining if the burst mode is entered once or if it is continuously operating. More...

Defines

#define | HRTIM_BURSTMODE_SINGLESHOT ((uint32_t)0x00000000U)
#define | HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM)

Detailed Description

Constants defining if the burst mode is entered once or if it is continuously operating.

Define Documentation

#define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM)

Burst mode operates in continuous mode.

Definition at line 1502 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODE_SINGLESHOT ((uint32_t)0x00000000U)

Burst mode operates in single shot mode.

Definition at line 1501 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Burst Mode Clock Source

Defines
HRTIM Burst Mode Clock Source
HRTIM Exported Constants

Constants defining the clock source for the burst mode counter. More...

Defines

#define | HRTIM_BURSTMODECLOCKSOURCE_MASTER ((uint32_t)0x00000000U)
#define | HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0)
#define | HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1)
#define | HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)
#define | HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2)
#define | HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0)
#define | HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1)
#define | HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)
#define | HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO (HRTIM_BMCR_BMCLK_3)
#define | HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1)

Detailed Description

Constants defining the clock source for the burst mode counter.

Define Documentation

#define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1)

Prescaled fHRTIM clock is used as clock source for the burst mode counter.

Definition at line 1521 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODECLOCKSOURCE_MASTER ((uint32_t)0x00000000U)

Master timer counter reset/roll-over is used as clock source for the burst mode counter.

Definition at line 1512 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1)

On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock.

Definition at line 1518 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)

On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock.

Definition at line 1519 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO (HRTIM_BMCR_BMCLK_3)

On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock.

Definition at line 1520 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0)

Timer A counter reset/roll-over is used as clock source for the burst mode counter.

Definition at line 1513 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1)

Timer B counter reset/roll-over is used as clock source for the burst mode counter.

Definition at line 1514 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)

Timer C counter reset/roll-over is used as clock source for the burst mode counter.

Definition at line 1515 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2)

Timer D counter reset/roll-over is used as clock source for the burst mode counter.

Definition at line 1516 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0)

Timer E counter reset/roll-over is used as clock source for the burst mode counter.

Definition at line 1517 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Burst Mode Prescaler

Defines
HRTIM Burst Mode Prescaler
HRTIM Exported Constants

Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller. More...

Defines

#define | HRTIM_BURSTMODEPRESCALER_DIV1 ((uint32_t)0x00000000U)
#define | HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0)
#define | HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1)
#define | HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)
#define | HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2)
#define | HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)
#define | HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)
#define | HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)
#define | HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3)
#define | HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0)
#define | HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1)
#define | HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)
#define | HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2)
#define | HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)
#define | HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)
#define | HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)

Detailed Description

Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller.

Define Documentation

#define HRTIM_BURSTMODEPRESCALER_DIV1 ((uint32_t)0x00000000U)

fBRST = fHRTIM.

Definition at line 1532 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1)

fBRST = fHRTIM/1024.

Definition at line 1542 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)

fBRST = fHRTIM/128.

Definition at line 1539 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2)

fBRST = fHRTIM/16.

Definition at line 1536 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)

fBRST = fHRTIM/16384.

Definition at line 1546 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0)

fBRST = fHRTIM/2.

Definition at line 1533 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)

fBRST = fHRTIM/2048.

Definition at line 1543 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3)

fBRST = fHRTIM/256.

Definition at line 1540 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)

fBRST = fHRTIM/32.

Definition at line 1537 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)

fBRST = fHRTIM/32768.

Definition at line 1547 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1)

fBRST = fHRTIM/4.

Definition at line 1534 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2)

fBRST = fHRTIM/4096.

Definition at line 1544 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0)

fBRST = fHRTIM/512.

Definition at line 1541 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)

fBRST = fHRTIM/64.

Definition at line 1538 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)

fBRST = fHRTIM/8.

Definition at line 1535 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)

fBRST = fHRTIM/8192.

Definition at line 1545 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Burst Mode Register Preload Enable

Defines
HRTIM Burst Mode Register Preload Enable
HRTIM Exported Constants

Constants defining whether or not burst mode registers preload mechanism is enabled, i.e. More...

Defines

#define | HRIM_BURSTMODEPRELOAD_DISABLED ((uint32_t)0x00000000U)
#define | HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN)

Detailed Description

Constants defining whether or not burst mode registers preload mechanism is enabled, i.e.

a write access into a preloadable register (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register

Define Documentation

#define HRIM_BURSTMODEPRELOAD_DISABLED ((uint32_t)0x00000000U)

Preload disabled: the write access is directly done into active registers.

Definition at line 1559 of file stm32h7xx_hal_hrtim.h.

#define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN)

Preload enabled: the write access is done into preload registers.

Definition at line 1560 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Burst Mode Trigger

Defines
HRTIM Burst Mode Trigger
HRTIM Exported Constants

Constants defining the events that can be used tor trig the burst mode operation. More...

Defines

#define | HRTIM_BURSTMODETRIGGER_NONE ((uint32_t)0x00000000U)
#define | HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST)
#define | HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP)
#define | HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1)
#define | HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2)
#define | HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3)
#define | HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4)
#define | HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST)
#define | HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP)
#define | HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1)
#define | HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2)
#define | HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST)
#define | HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP)
#define | HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1)
#define | HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2)
#define | HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST)
#define | HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP)
#define | HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1)
#define | HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2)
#define | HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST)
#define | HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP)
#define | HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1)
#define | HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2)
#define | HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST)
#define | HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP)
#define | HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1)
#define | HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2)
#define | HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7)
#define | HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8)
#define | HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7)
#define | HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8)
#define | HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV)

Detailed Description

Constants defining the events that can be used tor trig the burst mode operation.

Define Documentation

#define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7)

External Event 7 (timer A filters applied).

Definition at line 1600 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8)

External Event 8 (timer D filters applied).

Definition at line 1601 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV)

On-chip Event

Definition at line 1602 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1)

Master compare 1.

Definition at line 1574 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2)

Master compare 2.

Definition at line 1575 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3)

Master compare 3.

Definition at line 1576 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4)

Master compare 4.

Definition at line 1577 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP)

Master repetition.

Definition at line 1573 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST)

Master reset.

Definition at line 1572 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_NONE ((uint32_t)0x00000000U)

No trigger.

Definition at line 1571 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1)

Timer A compare 1.

Definition at line 1580 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2)

Timer A compare 2.

Definition at line 1581 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7)

Timer A period following External Event 7.

Definition at line 1598 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP)

Timer A repetition.

Definition at line 1579 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST)

Timer A reset.

Definition at line 1578 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1)

Timer B compare 1.

Definition at line 1584 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2)

Timer B compare 2.

Definition at line 1585 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP)

Timer B repetition.

Definition at line 1583 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST)

Timer B reset.

Definition at line 1582 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1)

Timer C compare 1.

Definition at line 1588 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2)

Timer C compare 2.

Definition at line 1589 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP)

Timer C repetition.

Definition at line 1587 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST)

Timer C reset.

Definition at line 1586 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1)

Timer D compare 1.

Definition at line 1592 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2)

Timer D compare 2.

Definition at line 1593 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8)

Timer D period following External Event 8.

Definition at line 1599 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP)

Timer D repetition.

Definition at line 1591 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST)

Timer D reset.

Definition at line 1590 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1)

Timer E compare 1.

Definition at line 1596 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2)

Timer E compare 2.

Definition at line 1597 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP)

Timer E repetition.

Definition at line 1595 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST)

Timer E reset.

Definition at line 1594 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM ADC Trigger Update Source

Defines
HRTIM ADC Trigger Update Source
HRTIM Exported Constants

constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register). More...

Defines

#define | HRTIM_ADCTRIGGERUPDATE_MASTER ((uint32_t)0x00000000U)
#define | HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0)
#define | HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1)
#define | HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0)
#define | HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2)
#define | HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0)

Detailed Description

constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register).

Define Documentation

#define HRTIM_ADCTRIGGERUPDATE_MASTER ((uint32_t)0x00000000U)

Master timer.

Definition at line 1613 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0)

Timer A.

Definition at line 1614 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1)

Timer B.

Definition at line 1615 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0)

Timer C.

Definition at line 1616 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2)

Timer D.

Definition at line 1617 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0)

Timer E.

Definition at line 1618 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM ADC Trigger Event

Defines
HRTIM ADC Trigger Event
HRTIM Exported Constants

constants defining the events triggering ADC conversion. More...

Defines

#define | HRTIM_ADCTRIGGEREVENT13_NONE ((uint32_t)0x00000000U)
#define | HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1)
#define | HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2)
#define | HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3)
#define | HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4)
#define | HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER)
#define | HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1)
#define | HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2)
#define | HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3)
#define | HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4)
#define | HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER)
#define | HRTIM_ADCTRIGGEREVENT24_NONE ((uint32_t)0x00000000U)
#define | HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1)
#define | HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2)
#define | HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3)
#define | HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4)
#define | HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER)
#define | HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6)
#define | HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7)
#define | HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8)
#define | HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9)
#define | HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST)

Detailed Description

constants defining the events triggering ADC conversion.

HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3 HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4

Define Documentation

#define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1)

ADC Trigger on external event 1.

Definition at line 1636 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2)

ADC Trigger on external event 2.

Definition at line 1637 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3)

ADC Trigger on external event 3.

Definition at line 1638 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4)

ADC Trigger on external event 4.

Definition at line 1639 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5)

ADC Trigger on external event 5.

Definition at line 1640 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1)

ADC Trigger on master compare 1.

Definition at line 1631 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2)

ADC Trigger on master compare 2.

Definition at line 1632 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3)

ADC Trigger on master compare 3.

Definition at line 1633 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4)

ADC Trigger on master compare 4.

Definition at line 1634 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER)

ADC Trigger on master period.

Definition at line 1635 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_NONE ((uint32_t)0x00000000U)

No ADC trigger event.

Definition at line 1630 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2)

ADC Trigger on Timer A compare 2.

Definition at line 1641 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3)

ADC Trigger on Timer A compare 3.

Definition at line 1642 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4)

ADC Trigger on Timer A compare 4.

Definition at line 1643 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER)

ADC Trigger on Timer A period.

Definition at line 1644 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST)

ADC Trigger on Timer A reset.

Definition at line 1645 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2)

ADC Trigger on Timer B compare 2.

Definition at line 1646 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3)

ADC Trigger on Timer B compare 3.

Definition at line 1647 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4)

ADC Trigger on Timer B compare 4.

Definition at line 1648 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER)

ADC Trigger on Timer B period.

Definition at line 1649 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST)

ADC Trigger on Timer B reset.

Definition at line 1650 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2)

ADC Trigger on Timer C compare 2.

Definition at line 1651 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3)

ADC Trigger on Timer C compare 3.

Definition at line 1652 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4)

ADC Trigger on Timer C compare 4.

Definition at line 1653 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER)

ADC Trigger on Timer C period.

Definition at line 1654 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2)

ADC Trigger on Timer D compare 2.

Definition at line 1655 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3)

ADC Trigger on Timer D compare 3.

Definition at line 1656 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4)

ADC Trigger on Timer D compare 4.

Definition at line 1657 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER)

ADC Trigger on Timer D period.

Definition at line 1658 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2)

ADC Trigger on Timer E compare 2.

Definition at line 1659 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3)

ADC Trigger on Timer E compare 3.

Definition at line 1660 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4)

ADC Trigger on Timer E compare 4.

Definition at line 1661 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER)

ADC Trigger on Timer E period.

Definition at line 1662 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10)

ADC Trigger on external event 10.

Definition at line 1674 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6)

ADC Trigger on external event 6.

Definition at line 1670 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7)

ADC Trigger on external event 7.

Definition at line 1671 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8)

ADC Trigger on external event 8.

Definition at line 1672 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9)

ADC Trigger on external event 9.

Definition at line 1673 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1)

ADC Trigger on master compare 1.

Definition at line 1665 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2)

ADC Trigger on master compare 2.

Definition at line 1666 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3)

ADC Trigger on master compare 3.

Definition at line 1667 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4)

ADC Trigger on master compare 4.

Definition at line 1668 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER)

ADC Trigger on master period.

Definition at line 1669 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_NONE ((uint32_t)0x00000000U)

No ADC trigger event.

Definition at line 1664 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2)

ADC Trigger on Timer A compare 2.

Definition at line 1675 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3)

ADC Trigger on Timer A compare 3.

Definition at line 1676 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4)

ADC Trigger on Timer A compare 4.

Definition at line 1677 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER)

ADC Trigger on Timer A period.

Definition at line 1678 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2)

ADC Trigger on Timer B compare 2.

Definition at line 1679 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3)

ADC Trigger on Timer B compare 3.

Definition at line 1680 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4)

ADC Trigger on Timer B compare 4.

Definition at line 1681 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER)

ADC Trigger on Timer B period.

Definition at line 1682 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2)

ADC Trigger on Timer C compare 2.

Definition at line 1683 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3)

ADC Trigger on Timer C compare 3.

Definition at line 1684 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4)

ADC Trigger on Timer C compare 4.

Definition at line 1685 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER)

ADC Trigger on Timer C period.

Definition at line 1686 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST)

ADC Trigger on Timer C reset.

Definition at line 1687 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2)

ADC Trigger on Timer D compare 2.

Definition at line 1688 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3)

ADC Trigger on Timer D compare 3.

Definition at line 1689 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4)

ADC Trigger on Timer D compare 4.

Definition at line 1690 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER)

ADC Trigger on Timer D period.

Definition at line 1691 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST)

ADC Trigger on Timer D reset.

Definition at line 1692 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2)

ADC Trigger on Timer E compare 2 .

Definition at line 1693 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3)

ADC Trigger on Timer E compare 3.

Definition at line 1694 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4)

ADC Trigger on Timer E compare 4.

Definition at line 1695 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST)

ADC Trigger on Timer E reset.

Definition at line 1696 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Burst DMA Registers Update

Defines
HRTIM Burst DMA Registers Update
HRTIM Exported Constants

Constants defining the registers that can be written during a burst DMA operation. More...

Defines

#define | HRTIM_BURSTDMA_NONE ((uint32_t)0x00000000U)
#define | HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR)
#define | HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR)
#define | HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER)
#define | HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT)
#define | HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER)
#define | HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP)
#define | HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1)
#define | HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2)
#define | HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3)
#define | HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4)
#define | HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR)
#define | HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R)
#define | HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R)
#define | HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R)
#define | HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R)
#define | HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1)
#define | HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2)
#define | HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR)
#define | HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR)
#define | HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR)
#define | HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR)

Detailed Description

Constants defining the registers that can be written during a burst DMA operation.

Define Documentation

#define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR)

CHPxR register is updated by Burst DMA accesses.

Definition at line 1727 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1)

MCMP1R or CMP1xR register is updated by Burst DMA accesses.

Definition at line 1715 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2)

MCMP2R or CMP2xR register is updated by Burst DMA accesses.

Definition at line 1716 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3)

MCMP3R or CMP3xR register is updated by Burst DMA accesses.

Definition at line 1717 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4)

MCMP4R or CMP4xR register is updated by Burst DMA accesses.

Definition at line 1718 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT)

MCNTR or CNTxCR register is updated by Burst DMA accesses.

Definition at line 1712 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR)

MCR or TIMxCR register is updated by Burst DMA accesses.

Definition at line 1709 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER)

MDIER or TIMxDIER register is updated by Burst DMA accesses.

Definition at line 1711 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR)

TDxR register is updated by Burst DMA accesses.

Definition at line 1719 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1)

EEFxR1 register is updated by Burst DMA accesses.

Definition at line 1724 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2)

EEFxR2 register is updated by Burst DMA accesses.

Definition at line 1725 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR)

FLTxR register is updated by Burst DMA accesses.

Definition at line 1729 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR)

MICR or TIMxICR register is updated by Burst DMA accesses.

Definition at line 1710 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTDMA_NONE ((uint32_t)0x00000000U)

No register is updated by Burst DMA accesses.

Definition at line 1708 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR)

OUTxR register is updated by Burst DMA accesses.

Definition at line 1728 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER)

MPER or PERxR register is updated by Burst DMA accesses.

Definition at line 1713 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP)

MREPR or REPxR register is updated by Burst DMA accesses.

Definition at line 1714 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R)

RST1R register is updated by Burst DMA accesses.

Definition at line 1721 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R)

RST1R register is updated by Burst DMA accesses.

Definition at line 1723 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR)

RSTxR register is updated by Burst DMA accesses.

Definition at line 1726 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R)

SET1R register is updated by Burst DMA accesses.

Definition at line 1720 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R)

SET2R register is updated by Burst DMA accesses.

Definition at line 1722 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Burst Mode Control

Defines
HRTIM Burst Mode Control
HRTIM Exported Constants

Constants used to enable or disable the burst mode controller. More...

Defines

#define | HRTIM_BURSTMODECTL_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME)

Detailed Description

Constants used to enable or disable the burst mode controller.

Define Documentation

#define HRTIM_BURSTMODECTL_DISABLED ((uint32_t)0x00000000U)

Burst mode disabled.

Definition at line 1739 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME)

Burst mode enabled.

Definition at line 1740 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Fault Mode Control

Defines
HRTIM Fault Mode Control
HRTIM Exported Constants

Constants used to enable or disable a fault channel. More...

Defines

#define | HRTIM_FAULTMODECTL_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_FAULTMODECTL_ENABLED ((uint32_t)0x00000001U)

Detailed Description

Constants used to enable or disable a fault channel.

Define Documentation

#define HRTIM_FAULTMODECTL_DISABLED ((uint32_t)0x00000000U)

Fault channel is disabled.

Definition at line 1750 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_FAULTMODECTL_ENABLED ((uint32_t)0x00000001U)

Fault channel is enabled.

Definition at line 1751 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Software Timer Update

Defines
HRTIM Software Timer Update
HRTIM Exported Constants

Constants used to force timer registers update. More...

Defines

#define | HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU)
#define | HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU)
#define | HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU)
#define | HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU)
#define | HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU)
#define | HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU)

Detailed Description

Constants used to force timer registers update.

Define Documentation

#define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU)

Forces an immediate transfer from the preload to the active register in the timer A.

Definition at line 1762 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU)

Forces an immediate transfer from the preload to the active register in the timer B.

Definition at line 1763 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU)

Forces an immediate transfer from the preload to the active register in the timer C.

Definition at line 1764 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU)

Forces an immediate transfer from the preload to the active register in the timer D.

Definition at line 1765 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU)

Forces an immediate transfer from the preload to the active register in the timer E.

Definition at line 1766 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU)

Forces an immediate transfer from the preload to the active register in the master timer.

Definition at line 1761 of file stm32h7xx_hal_hrtim.h.

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STM32H753xx HAL User Manual: HRTIM Software Timer Reset

Defines
HRTIM Software Timer Reset
HRTIM Exported Constants

Constants used to force timer counter reset. More...

Defines

#define | HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST)
#define | HRTIM_TIMERRESET_TIMER_A (HRTIM_CR2_TARST)
#define | HRTIM_TIMERRESET_TIMER_B (HRTIM_CR2_TBRST)
#define | HRTIM_TIMERRESET_TIMER_C (HRTIM_CR2_TCRST)
#define | HRTIM_TIMERRESET_TIMER_D (HRTIM_CR2_TDRST)
#define | HRTIM_TIMERRESET_TIMER_E (HRTIM_CR2_TERST)

Detailed Description

Constants used to force timer counter reset.

Define Documentation

#define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST)

Resets the master timer counter.

Definition at line 1776 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMERRESET_TIMER_A (HRTIM_CR2_TARST)

Resets the timer A counter.

Definition at line 1777 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMERRESET_TIMER_B (HRTIM_CR2_TBRST)

Resets the timer B counter.

Definition at line 1778 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMERRESET_TIMER_C (HRTIM_CR2_TCRST)

Resets the timer C counter.

Definition at line 1779 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMERRESET_TIMER_D (HRTIM_CR2_TDRST)

Resets the timer D counter.

Definition at line 1780 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIMERRESET_TIMER_E (HRTIM_CR2_TERST)

Resets the timer E counter.

Definition at line 1781 of file stm32h7xx_hal_hrtim.h.

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STM32H753xx HAL User Manual: HRTIM Output Level

Defines
HRTIM Output Level
HRTIM Exported Constants

Constants defining the level of a timer output. More...

Defines

#define | HRTIM_OUTPUTLEVEL_ACTIVE ((uint32_t)0x00000001U)
#define | HRTIM_OUTPUTLEVEL_INACTIVE ((uint32_t)0x00000002U)

Detailed Description

Constants defining the level of a timer output.

Define Documentation

#define HRTIM_OUTPUTLEVEL_ACTIVE ((uint32_t)0x00000001U)

Forces the output to its active state.

Definition at line 1791 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_GetDelayedProtectionStatus(), HAL_HRTIM_WaveformGetOutputLevel(), and HAL_HRTIM_WaveformSetOutputLevel().

#define HRTIM_OUTPUTLEVEL_INACTIVE ((uint32_t)0x00000002U)

Forces the output to its inactive state.

Definition at line 1792 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_GetDelayedProtectionStatus(), and HAL_HRTIM_WaveformGetOutputLevel().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Output State

Defines
HRTIM Output State
HRTIM Exported Constants

Constants defining the state of a timer output. More...

Defines

#define | HRTIM_OUTPUTSTATE_IDLE ((uint32_t)0x00000001U)
#define | HRTIM_OUTPUTSTATE_RUN ((uint32_t)0x00000002U)
#define | HRTIM_OUTPUTSTATE_FAULT ((uint32_t)0x00000003U)

Detailed Description

Constants defining the state of a timer output.

Define Documentation

#define HRTIM_OUTPUTSTATE_FAULT ((uint32_t)0x00000003U)

Safety state, entered in case of a shut-down request on FAULTx inputs.

Definition at line 1806 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformGetOutputState().

#define HRTIM_OUTPUTSTATE_IDLE ((uint32_t)0x00000001U)

Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit.

Definition at line 1802 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformGetOutputState().

#define HRTIM_OUTPUTSTATE_RUN ((uint32_t)0x00000002U)

Default operating state (e.g. after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation.

Definition at line 1804 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformGetOutputState().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Burst Mode Status

Defines
HRTIM Burst Mode Status
HRTIM Exported Constants

Constants defining the operating state of the burst mode controller. More...

Defines

#define | HRTIM_BURSTMODESTATUS_NORMAL ((uint32_t) 0x00000000U)
#define | HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT)

Detailed Description

Constants defining the operating state of the burst mode controller.

Define Documentation

#define HRTIM_BURSTMODESTATUS_NORMAL ((uint32_t) 0x00000000U)

Normal operation.

Definition at line 1816 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT)

Burst operation on-going.

Definition at line 1817 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Current Push Pull Status

Defines
HRTIM Current Push Pull Status
HRTIM Exported Constants

Constants defining on which output the signal is currently applied in push-pull mode. More...

Defines

#define | HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 ((uint32_t) 0x00000000U)
#define | HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT)

Detailed Description

Constants defining on which output the signal is currently applied in push-pull mode.

Define Documentation

#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 ((uint32_t) 0x00000000U)

Signal applied on output 1 and output 2 forced inactive.

Definition at line 1827 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT)

Signal applied on output 2 and output 1 forced inactive.

Definition at line 1828 of file stm32h7xx_hal_hrtim.h.

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STM32H753xx HAL User Manual: HRTIM Idle Push Pull Status

Defines
HRTIM Idle Push Pull Status
HRTIM Exported Constants

Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered. More...

Defines

#define | HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 ((uint32_t) 0x00000000U)
#define | HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT)

Detailed Description

Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered.

Define Documentation

#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 ((uint32_t) 0x00000000U)

Protection occurred when the output 1 was active and output 2 forced inactive.

Definition at line 1839 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT)

Protection occurred when the output 2 was active and output 1 forced inactive.

Definition at line 1840 of file stm32h7xx_hal_hrtim.h.

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STM32H753xx HAL User Manual: HRTIM Common Interrupt Enable

Defines
HRTIM Common Interrupt Enable
HRTIM Exported Constants

Defines

#define | HRTIM_IT_NONE ((uint32_t)0x00000000U)
#define | HRTIM_IT_FLT1 HRTIM_IER_FLT1
#define | HRTIM_IT_FLT2 HRTIM_IER_FLT2
#define | HRTIM_IT_FLT3 HRTIM_IER_FLT3
#define | HRTIM_IT_FLT4 HRTIM_IER_FLT4
#define | HRTIM_IT_FLT5 HRTIM_IER_FLT5
#define | HRTIM_IT_SYSFLT HRTIM_IER_SYSFLT
#define | HRTIM_IT_BMPER HRTIM_IER_BMPER

Define Documentation

#define HRTIM_IT_BMPER HRTIM_IER_BMPER

Burst mode period interrupt enable.

Definition at line 1855 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Master_ISR().

#define HRTIM_IT_FLT1 HRTIM_IER_FLT1

Fault 1 interrupt enable.

Definition at line 1849 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_HRTIM_ISR().

#define HRTIM_IT_FLT2 HRTIM_IER_FLT2

Fault 2 interrupt enable.

Definition at line 1850 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_HRTIM_ISR().

#define HRTIM_IT_FLT3 HRTIM_IER_FLT3

Fault 3 interrupt enable.

Definition at line 1851 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_HRTIM_ISR().

#define HRTIM_IT_FLT4 HRTIM_IER_FLT4

Fault 4 interrupt enable.

Definition at line 1852 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_HRTIM_ISR().

#define HRTIM_IT_FLT5 HRTIM_IER_FLT5

Fault 5 interrupt enable.

Definition at line 1853 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_HRTIM_ISR().

#define HRTIM_IT_NONE ((uint32_t)0x00000000U)

No interrupt enabled.

Definition at line 1848 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init().

#define HRTIM_IT_SYSFLT HRTIM_IER_SYSFLT

System Fault interrupt enable.

Definition at line 1854 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_HRTIM_ISR().

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STM32H753xx HAL User Manual: HRTIM Master Interrupt Enable

Defines
HRTIM Master Interrupt Enable
HRTIM Exported Constants

Defines

#define | HRTIM_MASTER_IT_NONE ((uint32_t)0x00000000U)
#define | HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE
#define | HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE
#define | HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE
#define | HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE
#define | HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE
#define | HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE
#define | HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE

Define Documentation

#define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE

Master compare 1 interrupt enable.

Definition at line 1865 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Master_ISR().

#define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE

Master compare 2 interrupt enable.

Definition at line 1866 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Master_ISR().

#define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE

Master compare 3 interrupt enable.

Definition at line 1867 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Master_ISR().

#define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE

Master compare 4 interrupt enable.

Definition at line 1868 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Master_ISR().

#define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE

Master Repetition interrupt enable.

Definition at line 1869 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleBaseStart_IT(), HAL_HRTIM_SimpleBaseStop_IT(), and HRTIM_Master_ISR().

#define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE

Master update interrupt enable.

Definition at line 1871 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Master_ISR().

#define HRTIM_MASTER_IT_NONE ((uint32_t)0x00000000U)

No interrupt enabled.

Definition at line 1864 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE

Synchronization input interrupt enable.

Definition at line 1870 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Master_ISR().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Timing Unit Interrupt Enable

Defines
HRTIM Timing Unit Interrupt Enable
HRTIM Exported Constants

Defines

#define | HRTIM_TIM_IT_NONE ((uint32_t)0x00000000U)
#define | HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE
#define | HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE
#define | HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE
#define | HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE
#define | HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE
#define | HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE
#define | HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE
#define | HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE
#define | HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE
#define | HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE
#define | HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE
#define | HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE
#define | HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE
#define | HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE

Define Documentation

#define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE

Timer compare 1 interrupt enable.

Definition at line 1881 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOnePulseStart_IT(), HAL_HRTIM_SimpleOnePulseStop_IT(), HAL_HRTIM_SimplePWMStart_IT(), HAL_HRTIM_SimplePWMStop_IT(), HRTIM_GetITFromOCMode(), and HRTIM_Timer_ISR().

#define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE

Timer compare 2 interrupt enable.

Definition at line 1882 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOnePulseStart_IT(), HAL_HRTIM_SimpleOnePulseStop_IT(), HAL_HRTIM_SimplePWMStart_IT(), HAL_HRTIM_SimplePWMStop_IT(), HRTIM_GetITFromOCMode(), and HRTIM_Timer_ISR().

#define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE

Timer compare 3 interrupt enable.

Definition at line 1883 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

#define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE

Timer compare 4 interrupt enable.

Definition at line 1884 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

#define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE

Timer capture 1 interrupt enable.

Definition at line 1887 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleCaptureStart_IT(), HAL_HRTIM_SimpleCaptureStop_IT(), and HRTIM_Timer_ISR().

#define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE

Timer capture 2 interrupt enable.

Definition at line 1888 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleCaptureStart_IT(), HAL_HRTIM_SimpleCaptureStop_IT(), and HRTIM_Timer_ISR().

#define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE

Timer delay protection interrupt enable.

Definition at line 1894 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

#define HRTIM_TIM_IT_NONE ((uint32_t)0x00000000U)

No interrupt enabled.

Definition at line 1880 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE

Timer repetition interrupt enable.

Definition at line 1885 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleBaseStart_IT(), HAL_HRTIM_SimpleBaseStop_IT(), and HRTIM_Timer_ISR().

#define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE

Timer reset interrupt enable.

Definition at line 1893 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

#define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE

Timer output 1 reset interrupt enable.

Definition at line 1890 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_GetITFromOCMode(), and HRTIM_Timer_ISR().

#define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE

Timer output 2 reset interrupt enable.

Definition at line 1892 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_GetITFromOCMode(), and HRTIM_Timer_ISR().

#define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE

Timer output 1 set interrupt enable.

Definition at line 1889 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_GetITFromOCMode(), and HRTIM_Timer_ISR().

#define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE

Timer output 2 set interrupt enable.

Definition at line 1891 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_GetITFromOCMode(), and HRTIM_Timer_ISR().

#define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE

Timer update interrupt enable.

Definition at line 1886 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Common Interrupt Flag

Defines
HRTIM Common Interrupt Flag
HRTIM Exported Constants

Defines

#define | HRTIM_FLAG_FLT1 HRTIM_ISR_FLT1
#define | HRTIM_FLAG_FLT2 HRTIM_ISR_FLT2
#define | HRTIM_FLAG_FLT3 HRTIM_ISR_FLT3
#define | HRTIM_FLAG_FLT4 HRTIM_ISR_FLT4
#define | HRTIM_FLAG_FLT5 HRTIM_ISR_FLT5
#define | HRTIM_FLAG_SYSFLT HRTIM_ISR_SYSFLT
#define | HRTIM_FLAG_BMPER HRTIM_ISR_BMPER

Define Documentation

#define HRTIM_FLAG_BMPER HRTIM_ISR_BMPER

Burst mode period interrupt flag.

Definition at line 1909 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Master_ISR().

#define HRTIM_FLAG_FLT1 HRTIM_ISR_FLT1

Fault 1 interrupt flag.

Definition at line 1903 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_HRTIM_ISR().

#define HRTIM_FLAG_FLT2 HRTIM_ISR_FLT2

Fault 2 interrupt flag.

Definition at line 1904 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_HRTIM_ISR().

#define HRTIM_FLAG_FLT3 HRTIM_ISR_FLT3

Fault 3 interrupt flag.

Definition at line 1905 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_HRTIM_ISR().

#define HRTIM_FLAG_FLT4 HRTIM_ISR_FLT4

Fault 4 interrupt flag.

Definition at line 1906 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_HRTIM_ISR().

#define HRTIM_FLAG_FLT5 HRTIM_ISR_FLT5

Fault 5 interrupt flag.

Definition at line 1907 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_HRTIM_ISR().

#define HRTIM_FLAG_SYSFLT HRTIM_ISR_SYSFLT

System Fault interrupt flag.

Definition at line 1908 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_HRTIM_ISR().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Master Interrupt Flag

Defines
HRTIM Master Interrupt Flag
HRTIM Exported Constants

Defines

#define | HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1
#define | HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2
#define | HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3
#define | HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4
#define | HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP
#define | HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC
#define | HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD

Define Documentation

#define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1

Master compare 1 interrupt flag.

Definition at line 1918 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Master_ISR().

#define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2

Master compare 2 interrupt flag.

Definition at line 1919 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Master_ISR().

#define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3

Master compare 3 interrupt flag.

Definition at line 1920 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Master_ISR().

#define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4

Master compare 4 interrupt flag.

Definition at line 1921 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Master_ISR().

#define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP

Master Repetition interrupt flag.

Definition at line 1922 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Master_ISR().

#define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD

Master update interrupt flag.

Definition at line 1924 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Master_ISR().

#define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC

Synchronization input interrupt flag.

Definition at line 1923 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Master_ISR().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Timing Unit Interrupt Flag

Defines
HRTIM Timing Unit Interrupt Flag
HRTIM Exported Constants

Defines

#define | HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1
#define | HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2
#define | HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3
#define | HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4
#define | HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP
#define | HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD
#define | HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1
#define | HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2
#define | HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1
#define | HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1
#define | HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2
#define | HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2
#define | HRTIM_TIM_FLAG_RST HRTIM_TIMISR_RST
#define | HRTIM_TIM_FLAG_DLYPRT HRTIM_TIMISR_DLYPRT

Define Documentation

#define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1

Timer compare 1 interrupt flag.

Definition at line 1933 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

#define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2

Timer compare 2 interrupt flag.

Definition at line 1934 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

#define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3

Timer compare 3 interrupt flag.

Definition at line 1935 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

#define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4

Timer compare 4 interrupt flag.

Definition at line 1936 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

#define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1

Timer capture 1 interrupt flag.

Definition at line 1939 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

#define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2

Timer capture 2 interrupt flag.

Definition at line 1940 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

#define HRTIM_TIM_FLAG_DLYPRT HRTIM_TIMISR_DLYPRT

Timer delay protection interrupt flag.

Definition at line 1946 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

#define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP

Timer repetition interrupt flag.

Definition at line 1937 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

#define HRTIM_TIM_FLAG_RST HRTIM_TIMISR_RST

Timer reset interrupt flag.

Definition at line 1945 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

#define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1

Timer output 1 reset interrupt flag.

Definition at line 1942 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

#define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2

Timer output 2 reset interrupt flag.

Definition at line 1944 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

#define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1

Timer output 1 set interrupt flag.

Definition at line 1941 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

#define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2

Timer output 2 set interrupt flag.

Definition at line 1943 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

#define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD

Timer update interrupt flag.

Definition at line 1938 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Master DMA Request Enable

Defines
HRTIM Master DMA Request Enable
HRTIM Exported Constants

Defines

#define | HRTIM_MASTER_DMA_NONE ((uint32_t)0x00000000U)
#define | HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE
#define | HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE
#define | HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE
#define | HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE
#define | HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE
#define | HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE
#define | HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE

Define Documentation

#define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE

Master compare 1 DMA request enable.

Definition at line 1956 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_DMAMasterCplt().

#define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE

Master compare 2 DMA request enable.

Definition at line 1957 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_DMAMasterCplt().

#define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE

Master compare 3 DMA request enable.

Definition at line 1958 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_DMAMasterCplt().

#define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE

Master compare 4 DMA request enable.

Definition at line 1959 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_DMAMasterCplt().

#define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE

Master Repetition DMA request enable.

Definition at line 1960 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleBaseStart_DMA(), HAL_HRTIM_SimpleBaseStop_DMA(), and HRTIM_DMAMasterCplt().

#define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE

Master update DMA request enable.

Definition at line 1962 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_DMAMasterCplt().

#define HRTIM_MASTER_DMA_NONE ((uint32_t)0x00000000U)

No DMA request enable.

Definition at line 1955 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE

Synchronization input DMA request enable.

Definition at line 1961 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_DMAMasterCplt().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Timing Unit DMA Request Enable

Defines
HRTIM Timing Unit DMA Request Enable
HRTIM Exported Constants

Defines

#define | HRTIM_TIM_DMA_NONE ((uint32_t)0x00000000U)
#define | HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE
#define | HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE
#define | HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE
#define | HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE
#define | HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE
#define | HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE
#define | HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE
#define | HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE
#define | HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE
#define | HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE
#define | HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE
#define | HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE
#define | HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE
#define | HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE

Define Documentation

#define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE

Timer compare 1 DMA request enable.

Definition at line 1972 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_SimplePWMStop_DMA(), HRTIM_DMATimerxCplt(), and HRTIM_GetDMAFromOCMode().

#define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE

Timer compare 2 DMA request enable.

Definition at line 1973 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_SimplePWMStop_DMA(), HRTIM_DMATimerxCplt(), and HRTIM_GetDMAFromOCMode().

#define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE

Timer compare 3 DMA request enable.

Definition at line 1974 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_DMATimerxCplt().

#define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE

Timer compare 4 DMA request enable.

Definition at line 1975 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_DMATimerxCplt().

#define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE

Timer capture 1 DMA request enable.

Definition at line 1978 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleCaptureStart_DMA(), HAL_HRTIM_SimpleCaptureStop_DMA(), and HRTIM_DMATimerxCplt().

#define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE

Timer capture 2 DMA request enable.

Definition at line 1979 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleCaptureStart_DMA(), HAL_HRTIM_SimpleCaptureStop_DMA(), and HRTIM_DMATimerxCplt().

#define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE

Timer delay protection DMA request enable.

Definition at line 1985 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_DMATimerxCplt().

#define HRTIM_TIM_DMA_NONE ((uint32_t)0x00000000U)

No DMA request enable.

Definition at line 1971 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE

Timer repetition DMA request enable.

Definition at line 1976 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleBaseStart_DMA(), HAL_HRTIM_SimpleBaseStop_DMA(), and HRTIM_DMATimerxCplt().

#define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE

Timer reset DMA request enable.

Definition at line 1984 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_DMATimerxCplt().

#define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE

Timer output 1 reset DMA request enable.

Definition at line 1981 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_DMATimerxCplt(), and HRTIM_GetDMAFromOCMode().

#define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE

Timer output 2 reset DMA request enable.

Definition at line 1983 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_DMATimerxCplt(), and HRTIM_GetDMAFromOCMode().

#define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE

Timer output 1 set DMA request enable.

Definition at line 1980 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_DMATimerxCplt(), and HRTIM_GetDMAFromOCMode().

#define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE

Timer output 2 set DMA request enable.

Definition at line 1982 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_DMATimerxCplt(), and HRTIM_GetDMAFromOCMode().

#define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE

Timer update DMA request enable.

Definition at line 1977 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_DMATimerxCplt().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Exported Macros

Defines
HRTIM Exported Macros
HRTIM

Defines

#define | __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)
Reset HRTIM handle state.
#define | __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__))
Enables or disables the timer counter(s)
#define | HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
#define | HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
#define | HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
#define | HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
#define | HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
#define | __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)
#define | __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
Enables or disables the specified HRTIM common interrupts.
#define | __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
Enables or disables the specified HRTIM common interrupts.
#define | __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
#define | __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
#define | __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__))
Enables or disables the specified HRTIM Master timer interrupts.
#define | __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))
#define | __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__))
Enables or disables the specified HRTIM Timerx interrupts.
#define | __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))
#define | __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified HRTIM common interrupt source is enabled or disabled.
#define | __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified HRTIM Master interrupt source is enabled or disabled.
#define | __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified HRTIM Timerx interrupt source is enabled or disabled.
#define | __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))
Clears the specified HRTIM common pending flag.
#define | __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__))
Clears the specified HRTIM Master pending flag.
#define | __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__))
Clears the specified HRTIM Timerx pending flag.
#define | __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))
Enables or disables the specified HRTIM Master timer DMA requets.
#define | __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
#define | __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__))
Enables or disables the specified HRTIM Timerx DMA requests.
#define | __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))
#define | __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__))
#define | __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))
#define | __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__))
#define | __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))
#define | __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__,__TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__))
#define | __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__,__TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))
#define | __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__)
Sets the HRTIM timer Counter Register value on runtime.
#define | __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__)
Gets the HRTIM timer Counter Register value on runtime.
#define | __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__)
Sets the HRTIM timer Period value on runtime.
#define | __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__)
Gets the HRTIM timer Period Register value on runtime.
#define | __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__)
Sets the HRTIM timer clock prescaler value on runtime.
#define | __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__)
Gets the HRTIM timer clock prescaler value on runtime.
#define | __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__)
Sets the HRTIM timer Compare Register value on runtime.
#define | __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__)
Gets the HRTIM timer Compare Register value on runtime.

Define Documentation

#define __HAL_HRTIM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))

Definition at line 3049 of file stm32h7xx_hal_hrtim.h.

#define __HAL_HRTIM_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))

Clears the specified HRTIM common pending flag.

Parameters:
__HANDLE__,: specifies the HRTIM Handle.
__INTERRUPT__,: specifies the interrupt pending bit to clear. This parameter can be one of the following values:
  • HRTIM_IT_FLT1: Fault 1 interrupt clear flag
  • HRTIM_IT_FLT2: Fault 2 interrupt clear flag
  • HRTIM_IT_FLT3: Fault 3 clear flag
  • HRTIM_IT_FLT4: Fault 4 clear flag
  • HRTIM_IT_FLT5: Fault 5 clear flag
  • HRTIM_IT_SYSFLT: System Fault interrupt clear flag
  • HRTIM_IT_BMPER: Burst mode period interrupt clear flag
Return values:
None

Definition at line 2951 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_HRTIM_ISR(), and HRTIM_Master_ISR().

#define __HAL_HRTIM_DISABLE | ( | __HANDLE__,
 |  | __TIMERS__
 | ) |

Definition at line 2779 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleBaseStop(), HAL_HRTIM_SimpleBaseStop_DMA(), HAL_HRTIM_SimpleBaseStop_IT(), HAL_HRTIM_SimpleCaptureStop(), HAL_HRTIM_SimpleCaptureStop_DMA(), HAL_HRTIM_SimpleCaptureStop_IT(), HAL_HRTIM_SimpleOCStop(), HAL_HRTIM_SimpleOCStop_DMA(), HAL_HRTIM_SimpleOCStop_IT(), HAL_HRTIM_SimpleOnePulseStop(), HAL_HRTIM_SimpleOnePulseStop_IT(), HAL_HRTIM_SimplePWMStop(), HAL_HRTIM_SimplePWMStop_DMA(), HAL_HRTIM_SimplePWMStop_IT(), and HAL_HRTIM_WaveformCounterStop_DMA().

#define __HAL_HRTIM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))

Definition at line 3006 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformCounterStop_IT().

#define __HAL_HRTIM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))

Definition at line 3006 of file stm32h7xx_hal_hrtim.h.

#define __HAL_HRTIM_ENABLE | ( | __HANDLE__,
 |  | __TIMERS__
 | ) | ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__))

Enables or disables the timer counter(s)

Parameters:
__HANDLE__,: specifies the HRTIM Handle.
__TIMERS__,: timersto enable/disable This parameter can be any combinations of the following values:
  • HRTIM_TIMERID_MASTER: Master timer identifier
  • HRTIM_TIMERID_TIMER_A: Timer A identifier
  • HRTIM_TIMERID_TIMER_B: Timer B identifier
  • HRTIM_TIMERID_TIMER_C: Timer C identifier
  • HRTIM_TIMERID_TIMER_D: Timer D identifier
  • HRTIM_TIMERID_TIMER_E: Timer E identifier
Return values:
None

Definition at line 2770 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleBaseStart(), HAL_HRTIM_SimpleBaseStart_DMA(), HAL_HRTIM_SimpleBaseStart_IT(), HAL_HRTIM_SimpleCaptureStart(), HAL_HRTIM_SimpleCaptureStart_DMA(), HAL_HRTIM_SimpleCaptureStart_IT(), HAL_HRTIM_SimpleOCStart(), HAL_HRTIM_SimpleOCStart_DMA(), HAL_HRTIM_SimpleOCStart_IT(), HAL_HRTIM_SimpleOnePulseStart(), HAL_HRTIM_SimpleOnePulseStart_IT(), HAL_HRTIM_SimplePWMStart(), HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_SimplePWMStart_IT(), and HAL_HRTIM_WaveformCounterStart_DMA().

#define __HAL_HRTIM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))

Enables or disables the specified HRTIM common interrupts.

Parameters:
__HANDLE__,: specifies the HRTIM Handle.
__INTERRUPT__,: specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • HRTIM_IT_FLT1: Fault 1 interrupt enable
  • HRTIM_IT_FLT2: Fault 2 interrupt enable
  • HRTIM_IT_FLT3: Fault 3 interrupt enable
  • HRTIM_IT_FLT4: Fault 4 interrupt enable
  • HRTIM_IT_FLT5: Fault 5 interrupt enable
  • HRTIM_IT_SYSFLT: System Fault interrupt enable
  • HRTIM_IT_BMPER: Burst mode period interrupt enable
Return values:
None

Definition at line 3005 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformCounterStart_IT().

#define __HAL_HRTIM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))

Enables or disables the specified HRTIM common interrupts.

Parameters:
__HANDLE__,: specifies the HRTIM Handle.
__INTERRUPT__,: specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • HRTIM_IT_FLT1: Fault 1 interrupt enable
  • HRTIM_IT_FLT2: Fault 2 interrupt enable
  • HRTIM_IT_FLT3: Fault 3 interrupt enable
  • HRTIM_IT_FLT4: Fault 4 interrupt enable
  • HRTIM_IT_FLT5: Fault 5 interrupt enable
  • HRTIM_IT_SYSFLT: System Fault interrupt enable
  • HRTIM_IT_BMPER: Burst mode period interrupt enable
Return values:
None

Definition at line 3005 of file stm32h7xx_hal_hrtim.h.

#define __HAL_HRTIM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__))

Definition at line 3048 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_HRTIM_ISR(), and HRTIM_Master_ISR().

#define __HAL_HRTIM_GET_ITSTATUS | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks if the specified HRTIM common interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: specifies the HRTIM Handle.
__INTERRUPT__,: specifies the interrupt source to check. This parameter can be one of the following values:
  • HRTIM_IT_FLT1: Fault 1 interrupt enable
  • HRTIM_IT_FLT2: Fault 2 interrupt enable
  • HRTIM_IT_FLT3: Fault 3 enable
  • HRTIM_IT_FLT4: Fault 4 enable
  • HRTIM_IT_FLT5: Fault 5 enable
  • HRTIM_IT_SYSFLT: System Fault interrupt enable
  • HRTIM_IT_BMPER: Burst mode period interrupt enable
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 2891 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_HRTIM_ISR(), and HRTIM_Master_ISR().

#define __HAL_HRTIM_GETCLOCKPRESCALER | ( | __HANDLE__,
 |  | __TIMER__
 | ) |
Value:
(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\
   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR  & HRTIM_TIMCR_CK_PSC))

Gets the HRTIM timer clock prescaler value on runtime.

Parameters:
__HANDLE__,: HRTIM Handle.
__TIMER__,: HRTIM timer This parameter can be one of the following values:
  • 0x5 for master timer
  • 0x0 to 0x4 for timers A to E
Return values:
timer clock prescaler value

Definition at line 3137 of file stm32h7xx_hal_hrtim.h.

#define __HAL_HRTIM_GETCOMPARE | ( | __HANDLE__,
 |  | __TIMER__,
 |  | __COMPAREUNIT__
 | ) |
Value:
(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
        (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\
         ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\
         ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\
         ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \
         : \
        (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\
         ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\
         ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\
         ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR)))

Gets the HRTIM timer Compare Register value on runtime.

Parameters:
__HANDLE__,: HRTIM Handle.
__TIMER__,: HRTIM timer This parameter can be one of the following values:
  • 0x0 to 0x4 for timers A to E
__COMPAREUNIT__,: timer compare unit This parameter can be one of the following values:
  • HRTIM_COMPAREUNIT_1: Compare unit 1
  • HRTIM_COMPAREUNIT_2: Compare unit 2
  • HRTIM_COMPAREUNIT_3: Compare unit 3
  • HRTIM_COMPAREUNIT_4: Compare unit 4
Return values:
Compare value

Definition at line 3180 of file stm32h7xx_hal_hrtim.h.

#define __HAL_HRTIM_GETCOUNTER | ( | __HANDLE__,
 |  | __TIMER__
 | ) |
Value:
(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\
   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR))

Gets the HRTIM timer Counter Register value on runtime.

Parameters:
__HANDLE__,: HRTIM Handle.
__TIMER__,: HRTIM timer This parameter can be one of the following values:
  • 0x5 for master timer
  • 0x0 to 0x4 for timers A to E
Return values:
HRTIM timer Counter Register value

Definition at line 3078 of file stm32h7xx_hal_hrtim.h.

#define __HAL_HRTIM_GETPERIOD | ( | __HANDLE__,
 |  | __TIMER__
 | ) |
Value:
(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\
   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR))

Gets the HRTIM timer Period Register value on runtime.

Parameters:
__HANDLE__,: HRTIM Handle.
__TIMER__,: HRTIM timer This parameter can be one of the following values:
  • 0x5 for master timer
  • 0x0 to 0x4 for timers A to E
Return values:
timer Period Register

Definition at line 3103 of file stm32h7xx_hal_hrtim.h.

#define __HAL_HRTIM_MASTER_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))

Definition at line 3052 of file stm32h7xx_hal_hrtim.h.

#define __HAL_HRTIM_MASTER_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__))

Clears the specified HRTIM Master pending flag.

Parameters:
__HANDLE__,: specifies the HRTIM Handle.
__INTERRUPT__,: specifies the interrupt pending bit to clear. This parameter can be one of the following values:
  • HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag
  • HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag
  • HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag
  • HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag
  • HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag
  • HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag
  • HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag
Return values:
None

Definition at line 2966 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Master_ISR().

#define __HAL_HRTIM_MASTER_DISABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))

Definition at line 3022 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleBaseStop_DMA(), and HAL_HRTIM_WaveformCounterStop_DMA().

#define __HAL_HRTIM_MASTER_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))

Definition at line 2852 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleBaseStop_IT(), and HAL_HRTIM_WaveformCounterStop_IT().

#define __HAL_HRTIM_MASTER_ENABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))

Enables or disables the specified HRTIM Master timer DMA requets.

Parameters:
__HANDLE__,: specifies the HRTIM Handle.
__DMA__,: specifies the DMA request to enable or disable. This parameter can be one of the following values:
  • HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA resquest enable
  • HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA resquest enable
  • HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA resquest enable
  • HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA resquest enable
  • HRTIM_MASTER_DMA_MREP: Master Repetition DMA resquest enable
  • HRTIM_MASTER_DMA_SYNC: Synchronization input DMA resquest enable
  • HRTIM_MASTER_DMA_MUPD: Master update DMA resquest enable
Return values:
None

Definition at line 3021 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleBaseStart_DMA(), and HAL_HRTIM_WaveformCounterStart_DMA().

#define __HAL_HRTIM_MASTER_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__))

Enables or disables the specified HRTIM Master timer interrupts.

Parameters:
__HANDLE__,: specifies the HRTIM Handle.
__INTERRUPT__,: specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
  • HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
  • HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
  • HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
  • HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
  • HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
  • HRTIM_MASTER_IT_MUPD: Master update interrupt enable
Return values:
None

Definition at line 2851 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleBaseStart_IT(), and HAL_HRTIM_WaveformCounterStart_IT().

#define __HAL_HRTIM_MASTER_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__))

Definition at line 3051 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Master_ISR().

#define __HAL_HRTIM_MASTER_GET_ITSTATUS | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks if the specified HRTIM Master interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: specifies the HRTIM Handle.
__INTERRUPT__,: specifies the interrupt source to check. This parameter can be one of the following values:
  • HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
  • HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
  • HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
  • HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
  • HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
  • HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
  • HRTIM_MASTER_IT_MUPD: Master update interrupt enable
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 2906 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Master_ISR().

#define __HAL_HRTIM_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)

Reset HRTIM handle state.

Parameters:
__HANDLE__,: HRTIM handle.
Return values:
None

Definition at line 2756 of file stm32h7xx_hal_hrtim.h.

#define __HAL_HRTIM_SETCLOCKPRESCALER | ( | __HANDLE__,
 |  | __TIMER__,
 |  | __PRESCALER__
 | ) |
Value:
(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__PRESCALER__)) :\
   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR |= (__PRESCALER__)))

Sets the HRTIM timer clock prescaler value on runtime.

Parameters:
__HANDLE__,: HRTIM Handle.
__TIMER__,: HRTIM timer This parameter can be one of the following values:
  • 0x5 for master timer
  • 0x0 to 0x4 for timers A to E
__PRESCALER__,: specifies the clock prescaler new value. This parameter can be one of the following values:
  • HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
  • HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
  • HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
  • HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
  • HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
  • HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
  • HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
  • HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)
Return values:
None

Definition at line 3125 of file stm32h7xx_hal_hrtim.h.

#define __HAL_HRTIM_SETCOMPARE | ( | __HANDLE__,
 |  | __TIMER__,
 |  | __COMPAREUNIT__,
 |  | __COMPARE__
 | ) |
Value:
(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
        (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\
         ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\
         ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\
         ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \
         : \
        (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\
         ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\
         ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\
         ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__))))

Sets the HRTIM timer Compare Register value on runtime.

Parameters:
__HANDLE__,: HRTIM Handle.
__TIMER__,: HRTIM timer This parameter can be one of the following values:
  • 0x0 to 0x4 for timers A to E
__COMPAREUNIT__,: timer compare unit This parameter can be one of the following values:
  • HRTIM_COMPAREUNIT_1: Compare unit 1
  • HRTIM_COMPAREUNIT_2: Compare unit 2
  • HRTIM_COMPAREUNIT_3: Compare unit 3
  • HRTIM_COMPAREUNIT_4: Compare unit 4
__COMPARE__,: specifies the Compare new value.
Return values:
None

Definition at line 3155 of file stm32h7xx_hal_hrtim.h.

#define __HAL_HRTIM_SETCOUNTER | ( | __HANDLE__,
 |  | __TIMER__,
 |  | __COUNTER__
 | ) |
Value:
(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\
   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__)))

Sets the HRTIM timer Counter Register value on runtime.

Parameters:
__HANDLE__,: HRTIM Handle.
__TIMER__,: HRTIM timer This parameter can be one of the following values:
  • 0x5 for master timer
  • 0x0 to 0x4 for timers A to E
__COUNTER__,: specifies the Counter Register new value.
Return values:
None

Definition at line 3066 of file stm32h7xx_hal_hrtim.h.

#define __HAL_HRTIM_SETPERIOD | ( | __HANDLE__,
 |  | __TIMER__,
 |  | __PERIOD__
 | ) |
Value:
(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\
   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__)))

Sets the HRTIM timer Period value on runtime.

Parameters:
__HANDLE__,: HRTIM Handle.
__TIMER__,: HRTIM timer This parameter can be one of the following values:
  • 0x5 for master timer
  • 0x0 to 0x4 for timers A to E
__PERIOD__,: specifies the Period Register new value.
Return values:
None

Definition at line 3091 of file stm32h7xx_hal_hrtim.h.

#define __HAL_HRTIM_TIMER_CLEAR_FLAG | ( | __HANDLE__,
 |  | __TIMER__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))

Definition at line 3055 of file stm32h7xx_hal_hrtim.h.

#define __HAL_HRTIM_TIMER_CLEAR_IT | ( | __HANDLE__,
 |  | __TIMER__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__))

Clears the specified HRTIM Timerx pending flag.

Parameters:
__HANDLE__,: specifies the HRTIM Handle.
__TIMER__,: specified the timing unit (Timer A to E)
__INTERRUPT__,: specifies the interrupt pending bit to clear. This parameter can be one of the following values:
  • HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag
  • HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag
  • HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag
  • HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag
  • HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag
  • HRTIM_TIM_IT_UPD: Timer update interrupt clear flag
  • HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag
  • HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag
  • HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag
  • HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag
  • HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag
  • HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag
  • HRTIM_TIM_IT_RST: Timer reset interrupt clear flag
  • HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag
Return values:
None

Definition at line 2989 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

#define __HAL_HRTIM_TIMER_DISABLE_DMA | ( | __HANDLE__,
 |  | __TIMER__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))

Definition at line 3046 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleBaseStop_DMA(), HAL_HRTIM_SimpleCaptureStop_DMA(), HAL_HRTIM_SimpleOCStop_DMA(), HAL_HRTIM_SimplePWMStop_DMA(), and HAL_HRTIM_WaveformCounterStop_DMA().

#define __HAL_HRTIM_TIMER_DISABLE_IT | ( | __HANDLE__,
 |  | __TIMER__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))

Definition at line 2876 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleBaseStop_IT(), HAL_HRTIM_SimpleCaptureStop_IT(), HAL_HRTIM_SimpleOCStop_IT(), HAL_HRTIM_SimpleOnePulseStop_IT(), HAL_HRTIM_SimplePWMStop_IT(), and HAL_HRTIM_WaveformCounterStop_IT().

#define __HAL_HRTIM_TIMER_ENABLE_DMA | ( | __HANDLE__,
 |  | __TIMER__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__))

Enables or disables the specified HRTIM Timerx DMA requests.

Parameters:
__HANDLE__,: specifies the HRTIM Handle.
__TIMER__,: specified the timing unit (Timer A to E)
__DMA__,: specifies the DMA request to enable or disable. This parameter can be one of the following values:
  • HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA resquest enable
  • HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA resquest enable
  • HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA resquest enable
  • HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA resquest enable
  • HRTIM_TIM_DMA_REP: Timer repetition DMA resquest enable
  • HRTIM_TIM_DMA_UPD: Timer update DMA resquest enable
  • HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA resquest enable
  • HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA resquest enable
  • HRTIM_TIM_DMA_SET1: Timer output 1 set DMA resquest enable
  • HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA resquest enable
  • HRTIM_TIM_DMA_SET2: Timer output 2 set DMA resquest enable
  • HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA resquest enable
  • HRTIM_TIM_DMA_RST: Timer reset DMA resquest enable
  • HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA resquest enable
Return values:
None

Definition at line 3045 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleBaseStart_DMA(), HAL_HRTIM_SimpleCaptureStart_DMA(), HAL_HRTIM_SimpleOCStart_DMA(), HAL_HRTIM_SimplePWMStart_DMA(), and HAL_HRTIM_WaveformCounterStart_DMA().

#define __HAL_HRTIM_TIMER_ENABLE_IT | ( | __HANDLE__,
 |  | __TIMER__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__))

Enables or disables the specified HRTIM Timerx interrupts.

Parameters:
__HANDLE__,: specifies the HRTIM Handle.
__TIMER__,: specified the timing unit (Timer A to E)
__INTERRUPT__,: specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
  • HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
  • HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
  • HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
  • HRTIM_TIM_IT_REP: Timer repetition interrupt enable
  • HRTIM_TIM_IT_UPD: Timer update interrupt enable
  • HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
  • HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
  • HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
  • HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
  • HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
  • HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
  • HRTIM_TIM_IT_RST: Timer reset interrupt enable
  • HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
Return values:
None

Definition at line 2875 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleBaseStart_IT(), HAL_HRTIM_SimpleCaptureStart_IT(), HAL_HRTIM_SimpleOCStart_IT(), HAL_HRTIM_SimpleOnePulseStart_IT(), HAL_HRTIM_SimplePWMStart_IT(), and HAL_HRTIM_WaveformCounterStart_IT().

#define __HAL_HRTIM_TIMER_GET_FLAG | ( | __HANDLE__,
 |  | __TIMER__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__))

Definition at line 3054 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

#define __HAL_HRTIM_TIMER_GET_ITSTATUS | ( | __HANDLE__,
 |  | __TIMER__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks if the specified HRTIM Timerx interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: specifies the HRTIM Handle.
__TIMER__,: specified the timing unit (Timer A to E)
__INTERRUPT__,: specifies the interrupt source to check. This parameter can be one of the following values:
  • HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
  • HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
  • HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
  • HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
  • HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
  • HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
  • HRTIM_MASTER_IT_MUPD: Master update interrupt enable
  • HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
  • HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
  • HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
  • HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
  • HRTIM_TIM_IT_REP: Timer repetition interrupt enable
  • HRTIM_TIM_IT_UPD: Timer update interrupt enable
  • HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
  • HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
  • HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
  • HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
  • HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
  • HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
  • HRTIM_TIM_IT_RST: Timer reset interrupt enable
  • HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 2936 of file stm32h7xx_hal_hrtim.h.

Referenced by HRTIM_Timer_ISR().

#define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)

Definition at line 2774 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)

Definition at line 2775 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)

Definition at line 2776 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)

Definition at line 2777 of file stm32h7xx_hal_hrtim.h.

#define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)

Definition at line 2778 of file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HRTIM Private Macros

Defines
HRTIM Private Macros
HRTIM

Defines

#define | IS_HRTIM_TIMERINDEX(TIMERINDEX)
#define | IS_HRTIM_TIMING_UNIT(TIMERINDEX)
#define | IS_HRTIM_COMPAREUNIT(COMPAREUNIT)
#define | IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)
#define | IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U)
#define | IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)
#define | IS_HRTIM_ADCTRIGGER(ADCTRIGGER)
#define | IS_HRTIM_EVENT(EVENT)
#define | IS_HRTIM_FAULT(FAULT)
#define | IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)
#define | IS_HRTIM_MODE(MODE)
#define | IS_HRTIM_MODE_ONEPULSE(MODE)
#define | IS_HRTIM_HALFMODE(HALFMODE)
#define | IS_HRTIM_SYNCSTART(SYNCSTART)
#define | IS_HRTIM_SYNCRESET(SYNCRESET)
#define | IS_HHRTIM_DACSYNC(DACSYNC)
#define | IS_HRTIM_PRELOAD(PRELOAD)
#define | IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)
#define | IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)
#define | IS_HRTIM_TIMERBURSTMODE(TIMERBURSTMODE)
#define | IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION)
#define | IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)
#define | IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U)
#define | IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)
#define | IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)
#define | IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)
#define | IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U)
#define | IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U)
#define | IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001U) == 0x00000000U)
#define | IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET)
#define | IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)
#define | IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE)
#define | IS_HRTIM_BASICOCMODE(BASICOCMODE)
#define | IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)
#define | IS_HRTIM_OUTPUTSET(OUTPUTSET)
#define | IS_HRTIM_OUTPUTRESET(OUTPUTRESET)
#define | IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)
#define | IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)
#define | IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)
#define | IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)
#define | IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)
#define | IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER)
#define | IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)
#define | IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)
#define | IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)
#define | IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)
#define | IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)
#define | IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)
#define | IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)
#define | IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)
#define | IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)
#define | IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)
#define | IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)
#define | IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)
#define | IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)
#define | IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)
#define | IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)
#define | IS_HRTIM_EVENTSRC(EVENTSRC)
#define | IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)
#define | IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)
#define | IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)
#define | IS_HRTIM_EVENTFILTER(EVENT, FILTER)
#define | IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)
#define | IS_HRTIM_FAULTSOURCE(FAULTSOURCE)
#define | IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)
#define | IS_HRTIM_FAULTFILTER(FAULTFILTER)
#define | IS_HRTIM_FAULTLOCK(FAULTLOCK)
#define | IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)
#define | IS_HRTIM_BURSTMODE(BURSTMODE)
#define | IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)
#define | IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)
#define | IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)
#define | IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)
#define | IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)
#define | IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA)
#define | IS_HRTIM_BURSTMODECTL(BURSTMODECTL)
#define | IS_HRTIM_FAULTMODECTL(FAULTMODECTL)
#define | IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U)
#define | IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FFU) == 0x00000000U)
#define | IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)
#define | IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0U) == 0x00000000U)
#define | IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U)
#define | IS_HRTIM_TIM_IT(IS_HRTIM_TIM_IT) (((IS_HRTIM_TIM_IT) & 0xFFFF8020U) == 0x00000000U)
#define | IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U)
#define | IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U)

Define Documentation

#define IS_HHRTIM_DACSYNC ( DACSYNC )
Value:
(((DACSYNC) == HRTIM_DACSYNC_NONE)          ||  \
                 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1)  ||  \
                 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2)  ||  \
                 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))

Definition at line 2102 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

#define IS_HRTIM_ADCTRIGGER ( ADCTRIGGER )
Value:
(((ADCTRIGGER) == HRTIM_ADCTRIGGER_1)   || \
     ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2)   || \
     ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3)   || \
     ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))

Definition at line 2046 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_ADCTriggerConfig().

#define IS_HRTIM_ADCTRIGGERUPDATE ( ADCTRIGGERUPDATE )
Value:
(((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER)   || \
              ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A)  || \
              ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B)  || \
              ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C)  || \
              ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D)  || \
              ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E))

Definition at line 2697 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_ADCTriggerConfig().

#define IS_HRTIM_AUTODELAYEDMODE ( AUTODELAYEDMODE )
Value:
(((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                  || \
               ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)    || \
               ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)  || \
               ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))

Definition at line 2176 of file stm32h7xx_hal_hrtim.h.

#define IS_HRTIM_BASICOCMODE ( BASICOCMODE )
Value:
(((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE)   || \
               ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \
               ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))

Definition at line 2196 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig().

#define IS_HRTIM_BURSTMODE ( BURSTMODE )
Value:
(((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT)  || \
               ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))

Definition at line 2625 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_BurstModeConfig().

#define IS_HRTIM_BURSTMODECLOCKSOURCE ( BURSTMODECLOCKSOURCE )
Value:
(((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER)      || \
               ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A)     || \
               ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B)     || \
               ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C)     || \
               ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D)     || \
               ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E)     || \
               ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC)    || \
               ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC)    || \
               ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO)   || \
               ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))

Definition at line 2629 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_BurstModeConfig().

#define IS_HRTIM_BURSTMODECTL ( BURSTMODECTL )
Value:
(((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED)  || \
     ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))

Definition at line 2718 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_BurstModeCtl().

#define IS_HRTIM_BURSTMODEPRELOAD ( BURSTMODEPRELOAD )
Value:
(((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED)  || \
               ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))

Definition at line 2659 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_BurstModeConfig().

#define IS_HRTIM_BURSTMODETRIGGER ( BURSTMODETRIGGER )

Definition at line 2663 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_BurstModeConfig().

#define IS_HRTIM_CAPTUREUNIT ( CAPTUREUNIT )
Value:
(((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1)   || \
     ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))

Definition at line 2019 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_GetCapturedValue(), HAL_HRTIM_SimpleCaptureChannelConfig(), HAL_HRTIM_SimpleCaptureStart(), HAL_HRTIM_SimpleCaptureStart_DMA(), HAL_HRTIM_SimpleCaptureStart_IT(), HAL_HRTIM_SimpleCaptureStop(), HAL_HRTIM_SimpleCaptureStop_DMA(), HAL_HRTIM_SimpleCaptureStop_IT(), and HAL_HRTIM_SoftwareCapture().

#define IS_HRTIM_CHOPPER_DUTYCYCLE ( DUTYCYCLE )
Value:
(((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0)    || \
                         ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125)  || \
                         ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250)  || \
                         ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375)  || \
                         ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500)  || \
                         ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625)  || \
                         ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750)  || \
                         ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875))

Definition at line 2474 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_ChopperModeConfig().

#define IS_HRTIM_CHOPPER_PRESCALERRATIO ( PRESCALERRATIO )
Value:
(((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16)    || \
                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32)    || \
                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48)    || \
                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64)    || \
                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80)    || \
                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96)    || \
                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112)   || \
                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128)   || \
                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144)   || \
                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160)   || \
                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176)   || \
                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192)   || \
                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208)   || \
                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224)   || \
                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240)   || \
                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256))

Definition at line 2456 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_ChopperModeConfig().

#define IS_HRTIM_CHOPPER_PULSEWIDTH ( PULSEWIDTH )
Value:
(((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16)   || \
                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32)   || \
                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48)   || \
                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64)   || \
                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80)   || \
                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96)   || \
                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112)  || \
                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128)  || \
                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144)  || \
                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160)  || \
                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176)  || \
                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192)  || \
                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208)  || \
                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224)  || \
                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240)  || \
                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256))

Definition at line 2484 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_ChopperModeConfig().

#define IS_HRTIM_COMPAREUNIT ( COMPAREUNIT )
Value:
(((COMPAREUNIT) == HRTIM_COMPAREUNIT_1)  || \
     ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2)  || \
     ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3)  || \
     ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))

Definition at line 2013 of file stm32h7xx_hal_hrtim.h.

#define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE | ( | COMPAREUNIT,
 |  | AUTODELAYEDMODE
 | ) |
Value:
((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) &&                                 \
     (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                 ||  \
      ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)   ||  \
      ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) ||  \
      ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))   \
    ||                                                                         \
    (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) &&                                 \
     (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                 ||  \
      ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)   ||  \
      ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) ||  \
      ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))

Definition at line 2183 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformCompareConfig().

#define IS_HRTIM_EVENT ( EVENT )
Value:
(((EVENT) == HRTIM_EVENT_1)   || \
       ((EVENT) == HRTIM_EVENT_2)   || \
       ((EVENT) == HRTIM_EVENT_3)   || \
       ((EVENT) == HRTIM_EVENT_4)   || \
       ((EVENT) == HRTIM_EVENT_5)   || \
       ((EVENT) == HRTIM_EVENT_6)   || \
       ((EVENT) == HRTIM_EVENT_7)   || \
       ((EVENT) == HRTIM_EVENT_8)   || \
       ((EVENT) == HRTIM_EVENT_9)   || \
       ((EVENT) == HRTIM_EVENT_10))

Definition at line 2052 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleCaptureChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), and HAL_HRTIM_TimerEventFilteringConfig().

#define IS_HRTIM_EVENTFASTMODE | ( | EVENT,
 |  | FASTMODE
 | ) |
Value:
(((((EVENT) == HRTIM_EVENT_1) ||                 \
       ((EVENT) == HRTIM_EVENT_2) ||                 \
       ((EVENT) == HRTIM_EVENT_3) ||                 \
       ((EVENT) == HRTIM_EVENT_4) ||                 \
       ((EVENT) == HRTIM_EVENT_5)) &&                \
      (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \
       ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \
    ||                                               \
    (((EVENT) == HRTIM_EVENT_6) ||                   \
     ((EVENT) == HRTIM_EVENT_7) ||                   \
     ((EVENT) == HRTIM_EVENT_8) ||                   \
     ((EVENT) == HRTIM_EVENT_9) ||                   \
     ((EVENT) == HRTIM_EVENT_10)))

Definition at line 2539 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_EventConfig().

#define IS_HRTIM_EVENTFILTER | ( | EVENT,
 |  | FILTER
 | ) |
Value:
((((EVENT) == HRTIM_EVENT_1) ||            \
        ((EVENT) == HRTIM_EVENT_2) ||            \
        ((EVENT) == HRTIM_EVENT_3) ||            \
        ((EVENT) == HRTIM_EVENT_4) ||            \
        ((EVENT) == HRTIM_EVENT_5))              \
       ||                                        \
      ((((EVENT) == HRTIM_EVENT_6) ||            \
        ((EVENT) == HRTIM_EVENT_7) ||            \
        ((EVENT) == HRTIM_EVENT_8) ||            \
        ((EVENT) == HRTIM_EVENT_9) ||            \
        ((EVENT) == HRTIM_EVENT_10)) &&          \
        (((FILTER) == HRTIM_EVENTFILTER_NONE) || \
        ((FILTER) == HRTIM_EVENTFILTER_1)     || \
        ((FILTER) == HRTIM_EVENTFILTER_2)     || \
        ((FILTER) == HRTIM_EVENTFILTER_3)     || \
        ((FILTER) == HRTIM_EVENTFILTER_4)     || \
        ((FILTER) == HRTIM_EVENTFILTER_5)     || \
        ((FILTER) == HRTIM_EVENTFILTER_6)     || \
        ((FILTER) == HRTIM_EVENTFILTER_7)     || \
        ((FILTER) == HRTIM_EVENTFILTER_8)     || \
        ((FILTER) == HRTIM_EVENTFILTER_9)     || \
        ((FILTER) == HRTIM_EVENTFILTER_10)    || \
        ((FILTER) == HRTIM_EVENTFILTER_11)    || \
        ((FILTER) == HRTIM_EVENTFILTER_12)    || \
        ((FILTER) == HRTIM_EVENTFILTER_13)    || \
        ((FILTER) == HRTIM_EVENTFILTER_14)    || \
        ((FILTER) == HRTIM_EVENTFILTER_15))))

Definition at line 2554 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_EventConfig(), HAL_HRTIM_SimpleCaptureChannelConfig(), and HAL_HRTIM_SimpleOnePulseChannelConfig().

#define IS_HRTIM_EVENTPOLARITY | ( | EVENTSENSITIVITY,
 |  | EVENTPOLARITY
 | ) |
Value:
((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL)  &&      \
       (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH)  ||           \
        ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW)))              \
      ||                                                            \
      (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
       ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \
       ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)))

Definition at line 2524 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_EventConfig(), HAL_HRTIM_SimpleCaptureChannelConfig(), and HAL_HRTIM_SimpleOnePulseChannelConfig().

#define IS_HRTIM_EVENTPRESCALER ( EVENTPRESCALER )
Value:
(((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1)  || \
              ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2)   || \
              ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4)   || \
              ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))

Definition at line 2583 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_EventPrescalerConfig().

#define IS_HRTIM_EVENTSENSITIVITY ( EVENTSENSITIVITY )
Value:
(((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL)       || \
                     ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE)  || \
                     ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \
                     ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))

Definition at line 2533 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_EventConfig(), HAL_HRTIM_SimpleCaptureChannelConfig(), and HAL_HRTIM_SimpleOnePulseChannelConfig().

#define IS_HRTIM_EVENTSRC ( EVENTSRC )
Value:
(((EVENTSRC) == HRTIM_EVENTSRC_1)   || \
                 ((EVENTSRC) == HRTIM_EVENTSRC_2)   || \
                 ((EVENTSRC) == HRTIM_EVENTSRC_3)   || \
                 ((EVENTSRC) == HRTIM_EVENTSRC_4))

Definition at line 2518 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_EventConfig().

#define IS_HRTIM_FAULT ( FAULT )
Value:
(((FAULT) == HRTIM_FAULT_1)   || \
       ((FAULT) == HRTIM_FAULT_2)   || \
       ((FAULT) == HRTIM_FAULT_3)   || \
       ((FAULT) == HRTIM_FAULT_4)   || \
       ((FAULT) == HRTIM_FAULT_5))

Definition at line 2064 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_FaultConfig(), and HAL_HRTIM_FaultModeCtl().

#define IS_HRTIM_FAULTFILTER ( FAULTFILTER )
Value:
(((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \
                 ((FAULTFILTER) == HRTIM_FAULTFILTER_1)    || \
                 ((FAULTFILTER) == HRTIM_FAULTFILTER_2)    || \
                 ((FAULTFILTER) == HRTIM_FAULTFILTER_3)    || \
                 ((FAULTFILTER) == HRTIM_FAULTFILTER_4)    || \
                 ((FAULTFILTER) == HRTIM_FAULTFILTER_5)    || \
                 ((FAULTFILTER) == HRTIM_FAULTFILTER_6)    || \
                 ((FAULTFILTER) == HRTIM_FAULTFILTER_7)    || \
                 ((FAULTFILTER) == HRTIM_FAULTFILTER_8)    || \
                 ((FAULTFILTER) == HRTIM_FAULTFILTER_9)    || \
                 ((FAULTFILTER) == HRTIM_FAULTFILTER_10)   || \
                 ((FAULTFILTER) == HRTIM_FAULTFILTER_11)   || \
                 ((FAULTFILTER) == HRTIM_FAULTFILTER_12)   || \
                 ((FAULTFILTER) == HRTIM_FAULTFILTER_13)   || \
                 ((FAULTFILTER) == HRTIM_FAULTFILTER_14)   || \
                 ((FAULTFILTER) == HRTIM_FAULTFILTER_15))

Definition at line 2597 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_FaultConfig().

#define IS_HRTIM_FAULTLOCK ( FAULTLOCK )
Value:
(((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \
               ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))

Definition at line 2615 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_FaultConfig().

#define IS_HRTIM_FAULTMODECTL ( FAULTMODECTL )
Value:
(((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED)  || \
     ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED))

Definition at line 2722 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_FaultModeCtl().

#define IS_HRTIM_FAULTPOLARITY ( HRTIM_FAULTPOLARITY )
Value:
(((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \
               ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))

Definition at line 2593 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_FaultConfig().

#define IS_HRTIM_FAULTPRESCALER ( FAULTPRESCALER )
Value:
(((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1)  || \
              ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2)   || \
              ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4)   || \
              ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))

Definition at line 2619 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_FaultPrescalerConfig().

#define IS_HRTIM_FAULTSOURCE ( FAULTSOURCE )
Value:
(((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \
               ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL))

Definition at line 2589 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_FaultConfig().

#define IS_HRTIM_HALFMODE ( HALFMODE )
Value:
(((HALFMODE) == HRTIM_HALFMODE_DISABLED)  ||  \
             ((HALFMODE) == HRTIM_HALFMODE_ENABLED))

Definition at line 2090 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

#define IS_HRTIM_HRTIM_BURSTMODEPRESCALER ( BURSTMODEPRESCALER )
Value:
(((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1)     || \
               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2)     || \
               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4)     || \
               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8)     || \
               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16)    || \
               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32)    || \
               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64)    || \
               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128)   || \
               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256)   || \
               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512)   || \
               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024)  || \
               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048)  || \
               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096)  || \
               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192)  || \
               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \
               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))

Definition at line 2641 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_BurstModeConfig().

#define IS_HRTIM_IT ( IT ) (((IT) & 0xFFFCFFC0U) == 0x00000000U)

Definition at line 2734 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init().

#define IS_HRTIM_MASTER_DMA ( MASTER_DMA ) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U)

Definition at line 2740 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

#define IS_HRTIM_MASTER_IT ( MASTER_IT ) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U)

Definition at line 2736 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

#define IS_HRTIM_MODE ( MODE )
Value:
(((MODE) == HRTIM_MODE_CONTINUOUS)  ||  \
           ((MODE) == HRTIM_MODE_SINGLESHOT) || \
           ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))

Definition at line 2081 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_TimeBaseConfig().

#define IS_HRTIM_MODE_ONEPULSE ( MODE )
Value:
(((MODE) == HRTIM_MODE_SINGLESHOT) || \
           ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))

Definition at line 2086 of file stm32h7xx_hal_hrtim.h.

#define IS_HRTIM_OUTPUT ( OUTPUT ) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U)

Definition at line 2023 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformOutputStart(), and HAL_HRTIM_WaveformOutputStop().

#define IS_HRTIM_OUTPUTBURSTMODEENTRY ( OUTPUTBURSTMODEENTRY )
Value:
(((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR)  || \
               ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))

Definition at line 2292 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformOutputConfig().

#define IS_HRTIM_OUTPUTCHOPPERMODE ( OUTPUTCHOPPERMODE )
Value:
(((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED)  || \
               ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))

Definition at line 2288 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformOutputConfig().

#define IS_HRTIM_OUTPUTFAULTLEVEL ( OUTPUTFAULTLEVEL )
Value:
(((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE)     || \
               ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE)   || \
               ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \
               ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ))

Definition at line 2282 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformOutputConfig().

#define IS_HRTIM_OUTPUTIDLELEVEL ( OUTPUTIDLELEVEL )
Value:
(((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \
               ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE))

Definition at line 2278 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimplePWMChannelConfig(), and HAL_HRTIM_WaveformOutputConfig().

#define IS_HRTIM_OUTPUTIDLEMODE ( OUTPUTIDLEMODE )
Value:
(((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \
               ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))

Definition at line 2274 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformOutputConfig().

#define IS_HRTIM_OUTPUTLEVEL ( OUTPUTLEVEL )
Value:
(((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE)  || \
     ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))

Definition at line 2730 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformSetOutputLevel().

#define IS_HRTIM_OUTPUTPOLARITY ( OUTPUTPOLARITY )
Value:
(((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \
               ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))

Definition at line 2202 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimplePWMChannelConfig(), and HAL_HRTIM_WaveformOutputConfig().

#define IS_HRTIM_OUTPUTRESET ( OUTPUTRESET )

Definition at line 2240 of file stm32h7xx_hal_hrtim.h.

#define IS_HRTIM_OUTPUTSET ( OUTPUTSET )

Definition at line 2206 of file stm32h7xx_hal_hrtim.h.

#define IS_HRTIM_PRELOAD ( PRELOAD )
Value:
(((PRELOAD) == HRTIM_PRELOAD_DISABLED)  ||  \
                 ((PRELOAD) == HRTIM_PRELOAD_ENABLED))

Definition at line 2108 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

#define IS_HRTIM_PRESCALERRATIO ( PRESCALERRATIO )
Value:
(((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
         ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
         ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8)  || \
         ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4)  || \
         ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2)  || \
         ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1)  || \
         ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2)  || \
         ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))

Definition at line 2071 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_TimeBaseConfig().

#define IS_HRTIM_SYNCINPUTSOURCE ( SYNCINPUTSOURCE )
Value:
(((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE)             || \
               ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT)    || \
               ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))

Definition at line 2502 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init().

#define IS_HRTIM_SYNCOUTPUTPOLARITY ( SYNCOUTPUTPOLARITY )
Value:
(((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE)  || \
               ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE)  || \
               ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))

Definition at line 2513 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init().

#define IS_HRTIM_SYNCOUTPUTSOURCE ( SYNCOUTPUTSOURCE )
Value:
(((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START)  || \
               ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1)   || \
               ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START)    || \
               ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))

Definition at line 2507 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_Init().

#define IS_HRTIM_SYNCRESET ( SYNCRESET )
Value:
(((SYNCRESET) == HRTIM_SYNCRESET_DISABLED)  ||  \
                 ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))

Definition at line 2098 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

#define IS_HRTIM_SYNCSTART ( SYNCSTART )
Value:
(((SYNCSTART) == HRTIM_SYNCSTART_DISABLED)  ||  \
               ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))

Definition at line 2094 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

#define IS_HRTIM_TIM_DMA ( TIM_DMA ) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U)

Definition at line 2742 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

#define IS_HRTIM_TIM_IT ( IS_HRTIM_TIM_IT ) (((IS_HRTIM_TIM_IT) & 0xFFFF8020U) == 0x00000000U)

Definition at line 2738 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

#define IS_HRTIM_TIMDEADTIME_FALLINGLOCK ( FALLINGLOCK )
Value:
(((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE)    || \
                           ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))

Definition at line 2448 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_DeadTimeConfig().

#define IS_HRTIM_TIMDEADTIME_FALLINGSIGN ( FALLINGSIGN )
Value:
(((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE)    || \
                       ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))

Definition at line 2444 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_DeadTimeConfig().

#define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK ( FALLINGSIGNLOCK )
Value:
(((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE)    || \
                         ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))

Definition at line 2452 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_DeadTimeConfig().

#define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO ( PRESCALERRATIO )
Value:
(((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \
                 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \
                 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \
                 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \
                 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \
                 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \
                 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \
                 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16))

Definition at line 2422 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_DeadTimeConfig().

#define IS_HRTIM_TIMDEADTIME_RISINGLOCK ( RISINGLOCK )
Value:
(((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE)    || \
                     ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))

Definition at line 2436 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_DeadTimeConfig().

#define IS_HRTIM_TIMDEADTIME_RISINGSIGN ( RISINGSIGN )
Value:
(((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE)    || \
                 ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))

Definition at line 2432 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_DeadTimeConfig().

#define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK ( RISINGSIGNLOCK )
Value:
(((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE)    || \
                   ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))

Definition at line 2440 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_DeadTimeConfig().

#define IS_HRTIM_TIMDEADTIMEINSERTION | ( | TIMPUSHPULLMODE,
 |  | TIMDEADTIMEINSERTION
 | ) |
Value:
((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) &&               \
        ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \
          ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED))))  \
      ||                                                                     \
        (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) &&             \
         ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED)))

Definition at line 2146 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

#define IS_HRTIM_TIMDELAYEDPROTECTION | ( | TIMPUSHPULLMODE,
 |  | TIMDELAYEDPROTECTION
 | ) |
Value:
((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED)          || \
            ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6)  || \
            ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6)  || \
            ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6)  || \
            ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \
            ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \
            ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7))    \
            ||                                                                           \
            (((TIMPUSHPULLMODE) ==  HRTIM_TIMPUSHPULLMODE_ENABLED) &&                    \
             (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)     || \
              ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))))

Definition at line 2154 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

#define IS_HRTIM_TIMER_BURSTDMA | ( | TIMER,
 |  | BURSTDMA
 | ) |
Value:
((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000U) == 0x00000000U)) \
    ||                                                                                 \
    (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
    ||                                                                                 \
    (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
    ||                                                                                 \
    (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
    ||                                                                                 \
    (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
    ||                                                                                 \
    (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)))

Definition at line 2705 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_BurstDMAConfig().

#define IS_HRTIM_TIMER_CAPTURETRIGGER | ( | TIMER,
 |  | CAPTURETRIGGER
 | ) |

Definition at line 2296 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformCaptureConfig().

#define IS_HRTIM_TIMER_OUTPUT | ( | TIMER,
 |  | OUTPUT
 | ) |
Value:
((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) &&   \
     (((OUTPUT) == HRTIM_OUTPUT_TA1) ||          \
      ((OUTPUT) == HRTIM_OUTPUT_TA2)))           \
    ||                                           \
    (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) &&    \
     (((OUTPUT) == HRTIM_OUTPUT_TB1) ||          \
      ((OUTPUT) == HRTIM_OUTPUT_TB2)))           \
    ||                                           \
    (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) &&    \
     (((OUTPUT) == HRTIM_OUTPUT_TC1) ||          \
      ((OUTPUT) == HRTIM_OUTPUT_TC2)))           \
    ||                                           \
    (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) &&    \
     (((OUTPUT) == HRTIM_OUTPUT_TD1) ||          \
      ((OUTPUT) == HRTIM_OUTPUT_TD2)))           \
    ||                                           \
    (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) &&    \
     (((OUTPUT) == HRTIM_OUTPUT_TE1) ||          \
      ((OUTPUT) == HRTIM_OUTPUT_TE2))))

Definition at line 2025 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_GetDelayedProtectionStatus(), HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOCStart(), HAL_HRTIM_SimpleOCStart_DMA(), HAL_HRTIM_SimpleOCStart_IT(), HAL_HRTIM_SimpleOCStop(), HAL_HRTIM_SimpleOCStop_DMA(), HAL_HRTIM_SimpleOCStop_IT(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimpleOnePulseStart(), HAL_HRTIM_SimpleOnePulseStart_IT(), HAL_HRTIM_SimpleOnePulseStop(), HAL_HRTIM_SimpleOnePulseStop_IT(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_SimplePWMStart(), HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_SimplePWMStart_IT(), HAL_HRTIM_SimplePWMStop(), HAL_HRTIM_SimplePWMStop_DMA(), HAL_HRTIM_SimplePWMStop_IT(), HAL_HRTIM_WaveformGetOutputLevel(), HAL_HRTIM_WaveformGetOutputState(), HAL_HRTIM_WaveformOutputConfig(), and HAL_HRTIM_WaveformSetOutputLevel().

#define IS_HRTIM_TIMERBURSTMODE ( TIMERBURSTMODE )
Value:
(((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK)  || \
                 ((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))

Definition at line 2128 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

#define IS_HRTIM_TIMERINDEX ( TIMERINDEX )
Value:
(((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER)   || \
     ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A)  || \
     ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B)  || \
     ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C)  || \
     ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D)  || \
     ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))

Definition at line 1999 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_BurstDMATransfer(), HAL_HRTIM_SimpleBaseStart(), HAL_HRTIM_SimpleBaseStart_DMA(), HAL_HRTIM_SimpleBaseStart_IT(), HAL_HRTIM_SimpleBaseStop(), HAL_HRTIM_SimpleBaseStop_DMA(), HAL_HRTIM_SimpleBaseStop_IT(), HAL_HRTIM_TimeBaseConfig(), HAL_HRTIM_WaveformCompareConfig(), and HAL_HRTIM_WaveformTimerConfig().

#define IS_HRTIM_TIMERRESET ( TIMERRESET ) (((TIMERRESET) & 0xFFFFC0FFU) == 0x00000000U)

Definition at line 2728 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SoftwareReset().

#define IS_HRTIM_TIMERUPDATE ( TIMERUPDATE ) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U)

Definition at line 2726 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_SoftwareUpdate(), HAL_HRTIM_UpdateDisable(), and HAL_HRTIM_UpdateEnable().

#define IS_HRTIM_TIMEVENTFILTER ( TIMEVENTFILTER )
Value:
(((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE)           || \
                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1)   || \
                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2)   || \
                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3)   || \
                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4)   || \
                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1)  || \
                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2)  || \
                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3)  || \
                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4)  || \
                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5)  || \
                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6)  || \
                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7)  || \
                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8)  || \
                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2)  || \
                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3)  || \
                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM))

Definition at line 2400 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_TimerEventFilteringConfig().

#define IS_HRTIM_TIMEVENTLATCH ( TIMEVENTLATCH )
Value:
(((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \
               ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))

Definition at line 2418 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_TimerEventFilteringConfig().

#define IS_HRTIM_TIMFAULTENABLE ( TIMFAULTENABLE ) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U)

Definition at line 2140 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

#define IS_HRTIM_TIMFAULTLOCK ( TIMFAULTLOCK )
Value:
(((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \
       ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))

Definition at line 2142 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

#define IS_HRTIM_TIMING_UNIT ( TIMERINDEX )
Value:
(((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A)  || \
      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B)  || \
      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C)  || \
      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D)  || \
      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))

Definition at line 2007 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_ChopperModeConfig(), HAL_HRTIM_DeadTimeConfig(), HAL_HRTIM_GetCapturedValue(), HAL_HRTIM_GetCurrentPushPullStatus(), HAL_HRTIM_GetIdlePushPullStatus(), HAL_HRTIM_SimpleCaptureChannelConfig(), HAL_HRTIM_SimpleCaptureStart(), HAL_HRTIM_SimpleCaptureStart_DMA(), HAL_HRTIM_SimpleCaptureStart_IT(), HAL_HRTIM_SimpleCaptureStop(), HAL_HRTIM_SimpleCaptureStop_DMA(), HAL_HRTIM_SimpleCaptureStop_IT(), HAL_HRTIM_SoftwareCapture(), and HAL_HRTIM_TimerEventFilteringConfig().

#define IS_HRTIM_TIMPUSHPULLMODE ( TIMPUSHPULLMODE )
Value:
(((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \
                   ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))

Definition at line 2136 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

#define IS_HRTIM_TIMRESETTRIGGER ( TIMRESETTRIGGER ) (((TIMRESETTRIGGER) & 0x800000001U) == 0x00000000U)

Definition at line 2170 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

#define IS_HRTIM_TIMUPDATEONRESET ( TIMUPDATEONRESET )
Value:
(((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \
               ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))

Definition at line 2172 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

#define IS_HRTIM_TIMUPDATETRIGGER ( TIMUPDATETRIGGER ) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U)

Definition at line 2168 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

#define IS_HRTIM_TIMUPDATETRIGGER ( TIMUPDATETRIGGER ) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U)

Definition at line 2168 of file stm32h7xx_hal_hrtim.h.

#define IS_HRTIM_UPDATEGATING_MASTER ( UPDATEGATING )
Value:
(((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT)      ||  \
                 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST)         ||  \
                 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))

Definition at line 2112 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

#define IS_HRTIM_UPDATEGATING_TIM ( UPDATEGATING )
Value:
(((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT)      ||  \
                 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST)         ||  \
                 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)  ||  \
                 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1)           ||  \
                 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2)           ||  \
                 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3)           ||  \
                 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE)    ||  \
                 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE)    ||  \
                 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))

Definition at line 2117 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

#define IS_HRTIM_UPDATEONREPETITION ( UPDATEONREPETITION )
Value:
(((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED)  || \
                 ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))

Definition at line 2132 of file stm32h7xx_hal_hrtim.h.

Referenced by HAL_HRTIM_WaveformTimerConfig().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Take and Release functions

Functions
Take and Release functions
HSEM Exported Functions

HSEM Take and Release functions. More...

Functions

HAL_StatusTypeDef | HAL_HSEM_Take (uint32_t SemID, uint32_t ProcessID)
Take a semaphore in 2 Step mode.
HAL_StatusTypeDef | HAL_HSEM_FastTake (uint32_t SemID)
Fast Take a semaphore with 1 Step mode.
uint32_t | HAL_HSEM_IsSemTaken (uint32_t SemID)
Check semaphore state Taken or not.
void | HAL_HSEM_Release (uint32_t SemID, uint32_t ProcessID)
Release a semaphore.
void | HAL_HSEM_ReleaseAll (uint32_t Key, uint32_t MasterID)
Release All semaphore used by a given Master .

Detailed Description

HSEM Take and Release functions.

 ==============================================================================
              ##### HSEM Take and Release functions #####
 ==============================================================================
[..] This section provides functions allowing to:
      (+) Take a semaphore with 2 Step method
      (+) Fast Take a semaphore with 1 Step method
      (+) Check semaphore state Taken or not
      (+) Release a semaphore
      (+) Release all semaphore at once

Function Documentation

HAL_StatusTypeDef HAL_HSEM_FastTake ( uint32_t SemID )

Fast Take a semaphore with 1 Step mode.

Parameters:
SemID,: semaphore ID from 0 to 31
Return values:
HAL status

Definition at line 181 of file stm32h7xx_hal_hsem.c.

References assert_param, HAL_GetCurrentCPUID(), and IS_HSEM_SEMID.

uint32_t HAL_HSEM_IsSemTaken ( uint32_t SemID )

Check semaphore state Taken or not.

Parameters:
SemID,: semaphore ID
Return values:
HAL HSEM state

Definition at line 202 of file stm32h7xx_hal_hsem.c.

void HAL_HSEM_Release | ( | uint32_t | SemID,
 |  | uint32_t | ProcessID
 | ) |  |

Release a semaphore.

Parameters:
SemID,: semaphore ID from 0 to 31
ProcessID,: Process ID from 0 to 255
Return values:
None

Definition at line 214 of file stm32h7xx_hal_hsem.c.

References assert_param, HAL_GetCurrentCPUID(), IS_HSEM_PROCESSID, and IS_HSEM_SEMID.

void HAL_HSEM_ReleaseAll | ( | uint32_t | Key,
 |  | uint32_t | MasterID
 | ) |  |

Release All semaphore used by a given Master .

Parameters:
Key,: Semaphore Key , value from 0 to 0xFFFF
MasterID,: MasterID of the CPU that is using semaphores to be Released
Return values:
None

Definition at line 231 of file stm32h7xx_hal_hsem.c.

References assert_param, IS_HSEM_KEY, and IS_HSEM_MASTERID.

HAL_StatusTypeDef HAL_HSEM_Take | ( | uint32_t | SemID,
 |  | uint32_t | ProcessID
 | ) |  |

Take a semaphore in 2 Step mode.

Parameters:
SemID,: semaphore ID from 0 to 31
ProcessID,: Process ID from 0 to 255
Return values:
HAL status

Definition at line 156 of file stm32h7xx_hal_hsem.c.

References assert_param, HAL_GetCurrentCPUID(), IS_HSEM_PROCESSID, and IS_HSEM_SEMID.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HSEM Set and Get Key functions

Functions
HSEM Set and Get Key functions
HSEM Exported Functions

HSEM Set and Get Key functions. More...

Functions

void | HAL_HSEM_SetClearKey (uint32_t Key)
Set semaphore Key .
uint32_t | HAL_HSEM_GetClearKey (void)
Get semaphore Key .

Detailed Description

HSEM Set and Get Key functions.

  ==============================================================================
              ##### HSEM Set and Get Key functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Set semaphore Key
      (+) Get semaphore Key

Function Documentation

uint32_t HAL_HSEM_GetClearKey ( void )

Get semaphore Key .

Return values:
Semaphore Key , value from 0 to 0xFFFF

Definition at line 275 of file stm32h7xx_hal_hsem.c.

void HAL_HSEM_SetClearKey ( uint32_t Key )

Set semaphore Key .

Parameters:
Key,: Semaphore Key , value from 0 to 0xFFFF
Return values:
None

Definition at line 263 of file stm32h7xx_hal_hsem.c.

References assert_param, and IS_HSEM_KEY.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HSEM IRQ handler management

Functions
HSEM IRQ handler management
HSEM Exported Functions

HSEM Notification functions. More...

Functions

void | HAL_HSEM_ActivateNotification (uint32_t SemMask)
Activate Semaphore release Notification for a given Semaphores Mask .
void | HAL_HSEM_DeactivateNotification (uint32_t SemMask)
Deactivate Semaphore release Notification for a given Semaphores Mask .
void | HAL_HSEM_IRQHandler (void)
This function handles HSEM interrupt request.
__weak void | HAL_HSEM_FreeCallback (uint32_t SemMask)
Semaphore Released Callback.

Detailed Description

HSEM Notification functions.

  ==============================================================================
      ##### HSEM IRQ handler management and Notification functions #####
  ==============================================================================
[..]  This section provides HSEM IRQ handler and Notification function.

Function Documentation

void HAL_HSEM_ActivateNotification ( uint32_t SemMask )

Activate Semaphore release Notification for a given Semaphores Mask .

Parameters:
SemMask,: Mask of Released semaphores
Return values:
Semaphore Key

Definition at line 302 of file stm32h7xx_hal_hsem.c.

void HAL_HSEM_DeactivateNotification ( uint32_t SemMask )

Deactivate Semaphore release Notification for a given Semaphores Mask .

Parameters:
SemMask,: Mask of Released semaphores
Return values:
Semaphore Key

Definition at line 313 of file stm32h7xx_hal_hsem.c.

void HAL_HSEM_FreeCallback ( uint32_t SemMask )

Semaphore Released Callback.

Parameters:
SemMask,: Mask of Released semaphores
Return values:
None

Definition at line 347 of file stm32h7xx_hal_hsem.c.

Referenced by HAL_HSEM_IRQHandler().

void HAL_HSEM_IRQHandler ( void )

This function handles HSEM interrupt request.

Return values:
None

Definition at line 324 of file stm32h7xx_hal_hsem.c.

References HAL_HSEM_FreeCallback().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HSEM Exported Types

HSEM Exported Types
HSEM
Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HSEM Exported Constants

HSEM Exported Constants
HSEM
Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HSEM Exported Macros

Defines
HSEM Exported Macros
HSEM

Defines

#define | __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))
SemID to mask helper Macro.
#define | __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER0 |= (__SEM_MASK__))
Enables the specified HSEM interrupts.
#define | __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER0 &= ~(__SEM_MASK__))
Disables the specified HSEM interrupts.
#define | __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR0)
Checks whether interrupt has occurred or not for semaphores specified by a mask.
#define | __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR0)
Get the semaphores release status flags.
#define | __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR0 |= (__SEM_MASK__))
Clears the HSEM Interrupt flags.

Define Documentation

#define __HAL_HSEM_CLEAR_FLAG ( __SEM_MASK__ ) (HSEM->ICR0 |= (__SEM_MASK__))

Clears the HSEM Interrupt flags.

Parameters:
__SEM_MASK__,: semaphores Mask
Return values:
None.

Definition at line 124 of file stm32h7xx_hal_hsem.h.

#define __HAL_HSEM_DISABLE_IT ( __SEM_MASK__ ) (HSEM->IER0 &= ~(__SEM_MASK__))

Disables the specified HSEM interrupts.

Parameters:
__SEM_MASK__,: semaphores Mask
Return values:
None.

Definition at line 103 of file stm32h7xx_hal_hsem.h.

#define __HAL_HSEM_ENABLE_IT ( __SEM_MASK__ ) (HSEM->IER0 |= (__SEM_MASK__))

Enables the specified HSEM interrupts.

Parameters:
__SEM_MASK__,: semaphores Mask
Return values:
None.

Definition at line 97 of file stm32h7xx_hal_hsem.h.

#define __HAL_HSEM_GET_FLAG ( __SEM_MASK__ ) ((__SEM_MASK__) & HSEM->ISR0)

Get the semaphores release status flags.

Parameters:
__SEM_MASK__,: semaphores Mask
Return values:
semaphores Mask : Semaphores where Release flags rise.

Definition at line 117 of file stm32h7xx_hal_hsem.h.

#define __HAL_HSEM_GET_IT ( __SEM_MASK__ ) ((__SEM_MASK__) & HSEM->MISR0)

Checks whether interrupt has occurred or not for semaphores specified by a mask.

Parameters:
__SEM_MASK__,: semaphores Mask
Return values:
semaphores Mask : Semaphores where an interrupt occurred.

Definition at line 110 of file stm32h7xx_hal_hsem.h.

#define __HAL_HSEM_SEMID_TO_MASK ( __SEMID__ ) (1 << (__SEMID__))

SemID to mask helper Macro.

Parameters:
__SEMID__,: semaphore ID from 0 to 31
Return values:
Semaphore Mask.

Definition at line 89 of file stm32h7xx_hal_hsem.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HSEM Private Types

HSEM Private Types
HSEM
Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HSEM Private Variables

HSEM Private Variables
HSEM
Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HSEM Private Constants

HSEM Private Constants
HSEM
Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HSEM Private Macros

Defines
HSEM Private Macros
HSEM

Defines

#define | IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )
#define | IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )
#define | IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
#define | IS_HSEM_MASTERID(__MASTERID__) (((__MASTERID__) == HSEM_CM7_MASTERID))

Define Documentation

#define IS_HSEM_KEY ( __KEY__ ) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )

Definition at line 228 of file stm32h7xx_hal_hsem.h.

Referenced by HAL_HSEM_ReleaseAll(), and HAL_HSEM_SetClearKey().

#define IS_HSEM_MASTERID ( __MASTERID__ ) (((__MASTERID__) == HSEM_CM7_MASTERID))

Definition at line 230 of file stm32h7xx_hal_hsem.h.

Referenced by HAL_HSEM_ReleaseAll().

#define IS_HSEM_PROCESSID ( __PROCESSID__ ) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )

Definition at line 226 of file stm32h7xx_hal_hsem.h.

Referenced by HAL_HSEM_Release(), and HAL_HSEM_Take().

#define IS_HSEM_SEMID ( __SEMID__ ) ((__SEMID__) <= HSEM_SEMID_MAX )

Definition at line 224 of file stm32h7xx_hal_hsem.h.

Referenced by HAL_HSEM_FastTake(), HAL_HSEM_Release(), and HAL_HSEM_Take().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2C Private Define

Defines
I2C Private Define
I2C

Defines

#define | TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFFU)
#define | I2C_TIMEOUT_ADDR ((uint32_t)10000U)
#define | I2C_TIMEOUT_BUSY ((uint32_t)25U)
#define | I2C_TIMEOUT_DIR ((uint32_t)25U)
#define | I2C_TIMEOUT_RXNE ((uint32_t)25U)
#define | I2C_TIMEOUT_STOPF ((uint32_t)25U)
#define | I2C_TIMEOUT_TC ((uint32_t)25U)
#define | I2C_TIMEOUT_TCR ((uint32_t)25U)
#define | I2C_TIMEOUT_TXIS ((uint32_t)25U)
#define | I2C_TIMEOUT_FLAG ((uint32_t)25U)
#define | MAX_NBYTE_SIZE 255U
#define | SlaveAddr_SHIFT 7U
#define | SlaveAddr_MSK 0x06U
#define | I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~HAL_I2C_STATE_READY)))
#define | I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
#define | I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))
#define | I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))
#define | I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))
#define | I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))
#define | I2C_XFER_TX_IT ((uint32_t)0x00000001U)
#define | I2C_XFER_RX_IT ((uint32_t)0x00000002U)
#define | I2C_XFER_LISTEN_IT ((uint32_t)0x00000004U)
#define | I2C_XFER_ERROR_IT ((uint32_t)0x00000011U)
#define | I2C_XFER_CPLT_IT ((uint32_t)0x00000012U)
#define | I2C_XFER_RELOAD_IT ((uint32_t)0x00000012U)

Define Documentation

#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))

Master Busy RX, combinaison of State LSB and Mode enum

Definition at line 282 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Sequential_Receive_IT(), and I2C_ITMasterSequentialCplt().

#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))

Master Busy TX, combinaison of State LSB and Mode enum

Definition at line 281 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Sequential_Transmit_IT(), and I2C_ITMasterSequentialCplt().

#define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))

Memory Busy RX, combinaison of State LSB and Mode enum

Definition at line 286 of file stm32h7xx_hal_i2c.c.

#define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))

Memory Busy TX, combinaison of State LSB and Mode enum

Definition at line 285 of file stm32h7xx_hal_i2c.c.

#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~HAL_I2C_STATE_READY)))

Mask State define, keep only RX and TX bits

Definition at line 279 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_DisableListen_IT().

#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))

Default Value

Definition at line 280 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_DeInit(), HAL_I2C_Init(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), and I2C_ITSlaveCplt().

#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))

Slave Busy RX, combinaison of State LSB and Mode enum

Definition at line 284 of file stm32h7xx_hal_i2c.c.

Referenced by I2C_ITSlaveSequentialCplt().

#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))

Slave Busy TX, combinaison of State LSB and Mode enum

Definition at line 283 of file stm32h7xx_hal_i2c.c.

Referenced by I2C_ITSlaveSequentialCplt().

#define I2C_TIMEOUT_ADDR ((uint32_t)10000U)

10 s

Definition at line 264 of file stm32h7xx_hal_i2c.c.

#define I2C_TIMEOUT_BUSY ((uint32_t)25U)

25 ms

Definition at line 265 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), and HAL_I2C_Mem_Write().

#define I2C_TIMEOUT_DIR ((uint32_t)25U)

25 ms

Definition at line 266 of file stm32h7xx_hal_i2c.c.

#define I2C_TIMEOUT_FLAG ((uint32_t)25U)

25 ms

Definition at line 272 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

#define I2C_TIMEOUT_RXNE ((uint32_t)25U)

25 ms

Definition at line 267 of file stm32h7xx_hal_i2c.c.

#define I2C_TIMEOUT_STOPF ((uint32_t)25U)

25 ms

Definition at line 268 of file stm32h7xx_hal_i2c.c.

#define I2C_TIMEOUT_TC ((uint32_t)25U)

25 ms

Definition at line 269 of file stm32h7xx_hal_i2c.c.

#define I2C_TIMEOUT_TCR ((uint32_t)25U)

25 ms

Definition at line 270 of file stm32h7xx_hal_i2c.c.

#define I2C_TIMEOUT_TXIS ((uint32_t)25U)

25 ms

Definition at line 271 of file stm32h7xx_hal_i2c.c.

#define I2C_XFER_CPLT_IT ((uint32_t)0x00000012U)

Definition at line 295 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), I2C_Disable_IRQ(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), and I2C_Master_ISR_DMA().

#define I2C_XFER_ERROR_IT ((uint32_t)0x00000011U)

Definition at line 294 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), I2C_Disable_IRQ(), and I2C_Enable_IRQ().

#define I2C_XFER_LISTEN_IT ((uint32_t)0x00000004U)

Definition at line 292 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), and I2C_ITSlaveCplt().

#define I2C_XFER_RELOAD_IT ((uint32_t)0x00000012U)

Definition at line 296 of file stm32h7xx_hal_i2c.c.

Referenced by I2C_Disable_IRQ(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), and I2C_Enable_IRQ().

#define I2C_XFER_RX_IT ((uint32_t)0x00000002U)

Definition at line 291 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSequentialCplt().

#define I2C_XFER_TX_IT ((uint32_t)0x00000001U)

Definition at line 290 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSequentialCplt().

#define MAX_NBYTE_SIZE 255U

Definition at line 274 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define SlaveAddr_MSK 0x06U

Definition at line 276 of file stm32h7xx_hal_i2c.c.

Referenced by I2C_ITAddrCplt().

#define SlaveAddr_SHIFT 7U

Definition at line 275 of file stm32h7xx_hal_i2c.c.

Referenced by I2C_ITAddrCplt().

#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFFU)

I2C TIMING clear register Mask

Definition at line 263 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Init().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2C Private Functions

Functions
I2C Private Functions
I2C

Functions

static void | I2C_DMAMasterTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C master transmit process complete callback.
static void | I2C_DMAMasterReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C master receive process complete callback.
static void | I2C_DMASlaveTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave transmit process complete callback.
static void | I2C_DMASlaveReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave receive process complete callback.
static void | I2C_DMAError (DMA_HandleTypeDef *hdma)
DMA I2C communication error callback.
static void | I2C_DMAAbort (DMA_HandleTypeDef *hdma)
DMA I2C communication abort callback (To be called at end of DMA Abort procedure).
static void | I2C_ITAddrCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Address complete process callback.
static void | I2C_ITMasterSequentialCplt (I2C_HandleTypeDef *hi2c)
I2C Master sequential complete process.
static void | I2C_ITSlaveSequentialCplt (I2C_HandleTypeDef *hi2c)
I2C Slave sequential complete process.
static void | I2C_ITMasterCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Master complete process.
static void | I2C_ITSlaveCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Slave complete process.
static void | I2C_ITListenCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Listen complete process.
static void | I2C_ITError (I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
I2C interrupts error process.
static HAL_StatusTypeDef | I2C_RequestMemoryWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | I2C_RequestMemoryRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for read request.
static HAL_StatusTypeDef | I2C_Master_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Slave_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Master_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
static HAL_StatusTypeDef | I2C_Slave_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
static HAL_StatusTypeDef | I2C_WaitOnFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout.
static HAL_StatusTypeDef | I2C_WaitOnTXISFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of TXIS flag.
static HAL_StatusTypeDef | I2C_WaitOnRXNEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | I2C_WaitOnSTOPFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | I2C_IsAcknowledgeFailed (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles Acknowledge failed detection during an I2C Communication.
static HAL_StatusTypeDef | I2C_Enable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static HAL_StatusTypeDef | I2C_Disable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static void | I2C_Flush_TXDR (I2C_HandleTypeDef *hi2c)
I2C Tx data register flush process.
static void | I2C_TransferConfig (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).

Function Documentation

static HAL_StatusTypeDef I2C_Disable_IRQ | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the disabling of Interrupts.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
InterruptRequest,: Value of I2C Interrupt configuration definition.
Return values:
HAL status

Definition at line 4777 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, HAL_I2C_STATE_LISTEN, I2C_IT_ADDRI, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_XFER_CPLT_IT, I2C_XFER_ERROR_IT, I2C_XFER_LISTEN_IT, I2C_XFER_RELOAD_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSequentialCplt().

static void I2C_DMAAbort ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C communication abort callback (To be called at end of DMA Abort procedure).

Parameters:
hdma,: DMA handle.
Return values:
None

Definition at line 4420 of file stm32h7xx_hal_i2c.c.

References HAL_I2C_AbortCpltCallback(), HAL_I2C_ErrorCallback(), HAL_I2C_STATE_ABORT, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::State, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by I2C_ITError().

static void I2C_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C communication error callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 4403 of file stm32h7xx_hal_i2c.c.

References HAL_I2C_ERROR_DMA, I2C_ITError(), and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), and HAL_I2C_Slave_Transmit_DMA().

static void I2C_DMAMasterReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C master receive process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 4346 of file stm32h7xx_hal_i2c.c.

References HAL_DMA_Start_IT(), __I2C_HandleTypeDef::hdmarx, I2C_Enable_IRQ(), I2C_XFER_CPLT_IT, I2C_XFER_RELOAD_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA(), and HAL_I2C_Mem_Read_DMA().

static void I2C_DMAMasterTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C master transmit process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 4289 of file stm32h7xx_hal_i2c.c.

References HAL_DMA_Start_IT(), __I2C_HandleTypeDef::hdmatx, I2C_Enable_IRQ(), I2C_XFER_CPLT_IT, I2C_XFER_RELOAD_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Transmit_DMA(), and HAL_I2C_Mem_Write_DMA().

static void I2C_DMASlaveReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C slave receive process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 4388 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Slave_Receive_DMA().

static void I2C_DMASlaveTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C slave transmit process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 4331 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Slave_Transmit_DMA().

static HAL_StatusTypeDef I2C_Enable_IRQ | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the enabling of Interrupts.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
InterruptRequest,: Value of I2C Interrupt configuration definition.
Return values:
HAL status

Definition at line 4704 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_ENABLE_IT, I2C_IT_ADDRI, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_Master_ISR_DMA(), I2C_Slave_ISR_DMA(), I2C_XFER_CPLT_IT, I2C_XFER_ERROR_IT, I2C_XFER_LISTEN_IT, I2C_XFER_RELOAD_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, and __I2C_HandleTypeDef::XferISR.

Referenced by HAL_I2C_EnableListen_IT(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), and I2C_Master_ISR_DMA().

static void I2C_Flush_TXDR ( I2C_HandleTypeDef * hi2c ) [static]

I2C Tx data register flush process.

Parameters:
hi2c,: I2C handle.
Return values:
None

Definition at line 4268 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_FLAG_TXE, I2C_FLAG_TXIS, and __I2C_HandleTypeDef::Instance.

Referenced by I2C_IsAcknowledgeFailed(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

static HAL_StatusTypeDef I2C_IsAcknowledgeFailed | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles Acknowledge failed detection during an I2C Communication.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout,: Timeout duration
Tickstart,: Tick start value
Return values:
HAL status

Definition at line 4608 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_RESET_CR2, __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

static void I2C_ITAddrCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Address complete process callback.

Parameters:
hi2c,: I2C handle.
ITFlags,: Interrupt flags to handle.
Return values:
None

Definition at line 3752 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, I2C_InitTypeDef::AddressingMode, __I2C_HandleTypeDef::AddrEventCount, HAL_I2C_AddrCallback(), HAL_I2C_STATE_LISTEN, I2C_ADDRESSINGMODE_10BIT, I2C_Disable_IRQ(), I2C_FLAG_ADDR, I2C_GET_ADDR_MATCH, I2C_GET_DIR, I2C_GET_OWN_ADDRESS1, I2C_GET_OWN_ADDRESS2, I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Init, SlaveAddr_MSK, SlaveAddr_SHIFT, and __I2C_HandleTypeDef::State.

Referenced by I2C_Slave_ISR_IT().

static void I2C_ITError | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ErrorCode
 | ) |  | [static]

I2C interrupts error process.

Parameters:
hi2c,: I2C handle.
ErrorCode,: Error code to handle.
Return values:
None

Definition at line 4166 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_I2C_AbortCpltCallback(), HAL_I2C_ErrorCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_ABORT, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_IT(), I2C_STATE_NONE, I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_DMAError(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

static void I2C_ITListenCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Listen complete process.

Parameters:
hi2c,: I2C handle.
ITFlags,: Interrupt flags to handle.
Return values:
None

Definition at line 4122 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ListenCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_NO_OPTION_FRAME, I2C_STATE_NONE, I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by I2C_ITSlaveCplt(), and I2C_Slave_ISR_IT().

static void I2C_ITMasterCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Master complete process.

Parameters:
hi2c,: I2C handle.
ITFlags,: Interrupt flags to handle.
Return values:
None

Definition at line 3924 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MemRxCpltCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_ABORT, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_ITError(), I2C_NO_OPTION_FRAME, I2C_RESET_CR2, I2C_STATE_NONE, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferOptions.

Referenced by I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

static void I2C_ITMasterSequentialCplt ( I2C_HandleTypeDef * hi2c ) [static]

I2C Master sequential complete process.

Parameters:
hi2c,: I2C handle.
Return values:
None

Definition at line 3835 of file stm32h7xx_hal_i2c.c.

References HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_STATE_MASTER_BUSY_RX, I2C_STATE_MASTER_BUSY_TX, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferISR.

Referenced by I2C_Master_ISR_IT().

static void I2C_ITSlaveCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Slave complete process.

Parameters:
hi2c,: I2C handle.
ITFlags,: Interrupt flags to handle.
Return values:
None

Definition at line 4016 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ListenCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_FLAG_ADDR, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_GET_DMA_REMAIN_DATA, I2C_ITError(), I2C_ITListenCplt(), I2C_NO_OPTION_FRAME, I2C_RESET_CR2, I2C_STATE_NONE, I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static void I2C_ITSlaveSequentialCplt ( I2C_HandleTypeDef * hi2c ) [static]

I2C Slave sequential complete process.

Parameters:
hi2c,: I2C handle.
Return values:
None

Definition at line 3880 of file stm32h7xx_hal_i2c.c.

References HAL_I2C_MODE_NONE, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_Disable_IRQ(), I2C_STATE_SLAVE_BUSY_RX, I2C_STATE_SLAVE_BUSY_TX, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, and __I2C_HandleTypeDef::State.

Referenced by I2C_Slave_ISR_IT().

static HAL_StatusTypeDef I2C_Master_ISR_DMA | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags,: Interrupt flags to handle.
ITSources,: Interrupt sources enabled.
Return values:
HAL status

Definition at line 3482 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_DISABLE_IT, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_SIZE, HAL_I2C_STATE_BUSY_RX, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_Flush_TXDR(), I2C_IT_NACKI, I2C_IT_STOPI, I2C_IT_TCI, I2C_ITError(), I2C_ITMasterCplt(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_CPLT_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), and I2C_Enable_IRQ().

static HAL_StatusTypeDef I2C_Master_ISR_IT | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags,: Interrupt flags to handle.
ITSources,: Interrupt sources enabled.
Return values:
HAL status

Definition at line 3248 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_SIZE, I2C_AUTOEND_MODE, I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TC, I2C_FLAG_TCR, I2C_FLAG_TXIS, I2C_Flush_TXDR(), I2C_GET_STOP_MODE, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_ITError(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), I2C_NO_OPTION_FRAME, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_TransferConfig(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_IT(), and HAL_I2C_Mem_Write_IT().

static HAL_StatusTypeDef I2C_RequestMemoryRead | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Master sends target device address followed by internal memory address for read request.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
MemAddress,: Internal memory address
MemAddSize,: Size of internal memory address
Timeout,: Timeout duration
Tickstart Tick start value
Return values:
HAL status

Definition at line 3691 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, I2C_FLAG_TC, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_MEMADD_SIZE_8BIT, I2C_SOFTEND_MODE, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), and HAL_I2C_Mem_Read_IT().

static HAL_StatusTypeDef I2C_RequestMemoryWrite | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Master sends target device address followed by internal memory address for write request.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
MemAddress,: Internal memory address
MemAddSize,: Size of internal memory address
Timeout,: Timeout duration
Tickstart Tick start value
Return values:
HAL status

Definition at line 3625 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, I2C_FLAG_TCR, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_MEMADD_SIZE_8BIT, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

static HAL_StatusTypeDef I2C_Slave_ISR_DMA | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags,: Interrupt flags to handle.
ITSources,: Interrupt sources enabled.
Return values:
HAL status

Definition at line 3571 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_GET_DMA_REMAIN_DATA, I2C_IT_ADDRI, I2C_IT_NACKI, I2C_IT_STOPI, and I2C_ITSlaveCplt().

Referenced by HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), and I2C_Enable_IRQ().

static HAL_StatusTypeDef I2C_Slave_ISR_IT | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags,: Interrupt flags to handle.
ITSources,: Interrupt sources enabled.
Return values:
HAL status

Definition at line 3369 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TXIS, I2C_Flush_TXDR(), I2C_IT_ADDRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TXI, I2C_ITAddrCplt(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSequentialCplt(), I2C_LAST_FRAME, I2C_NEXT_FRAME, I2C_NO_OPTION_FRAME, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_EnableListen_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_IT(), and I2C_ITError().

static void I2C_TransferConfig | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t | Size,
 |  | uint32_t | Mode,
 |  | uint32_t | Request
 | ) |  | [static]

Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).

Parameters:
hi2c,: I2C handle.
DevAddress,: Specifies the slave address to be programmed.
Size,: Specifies the number of bytes to be programmed. This parameter must be a value between 0 and 255.
Mode,: New state of the I2C START condition generation. This parameter can be one of the following values:
  • I2C_RELOAD_MODE: Enable Reload mode .
  • I2C_AUTOEND_MODE: Enable Automatic end mode.
  • I2C_SOFTEND_MODE: Enable Software end mode.
Request,: New state of the I2C START condition generation. This parameter can be one of the following values:
  • I2C_NO_STARTSTOP: Don't Generate stop and start condition.
  • I2C_GENERATE_STOP: Generate stop condition (Size should be set to 0).
  • I2C_GENERATE_START_READ: Generate Restart for read request.
  • I2C_GENERATE_START_WRITE: Generate Restart for write request.
Return values:
None

Definition at line 4674 of file stm32h7xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::Instance, IS_TRANSFER_MODE, and IS_TRANSFER_REQUEST.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Flag,: Specifies the I2C flag to check.
Status,: The new Flag status (SET or RESET).
Timeout,: Timeout duration
Tickstart,: Tick start value
Return values:
HAL status

Definition at line 4456 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, HAL_GetTick(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of RXNE flag.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout,: Timeout duration
Tickstart,: Tick start value
Return values:
HAL status

Definition at line 4556 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_IsAcknowledgeFailed(), I2C_RESET_CR2, __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Receive(), and HAL_I2C_Slave_Receive().

static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of STOP flag.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout,: Timeout duration
Tickstart,: Tick start value
Return values:
HAL status

Definition at line 4522 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_STOPF, I2C_IsAcknowledgeFailed(), __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), and HAL_I2C_Slave_Transmit().

static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of TXIS flag.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout,: Timeout duration
Tickstart,: Tick start value
Return values:
HAL status

Definition at line 4485 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_TXIS, I2C_IsAcknowledgeFailed(), __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Transmit(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2C Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          deinitialize the I2Cx peripheral:

      (+) User must Implement HAL_I2C_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_I2C_Init() to configure the selected device with
          the selected configuration:
        (++) Clock Timing
        (++) Own Address 1
        (++) Addressing mode (Master, Slave)
        (++) Dual Addressing mode
        (++) Own Address 2
        (++) Own Address 2 Mask
        (++) General call mode
        (++) Nostretch mode

      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
          of the selected I2Cx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_I2C_DeInit ( I2C_HandleTypeDef * hi2c )

DeInitialize the I2C peripheral.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 494 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_DISABLE, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MspDeInit(), HAL_I2C_STATE_BUSY, HAL_I2C_STATE_RESET, I2C_STATE_NONE, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Init ( I2C_HandleTypeDef * hi2c )

Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 407 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, I2C_InitTypeDef::AddressingMode, assert_param, I2C_InitTypeDef::DualAddressMode, __I2C_HandleTypeDef::ErrorCode, I2C_InitTypeDef::GeneralCallMode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MspInit(), HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, HAL_I2C_STATE_RESET, I2C_ADDRESSINGMODE_10BIT, I2C_ADDRESSINGMODE_7BIT, I2C_DUALADDRESS_ENABLE, I2C_STATE_NONE, __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, IS_I2C_ADDRESSING_MODE, IS_I2C_DUAL_ADDRESS, IS_I2C_GENERAL_CALL, IS_I2C_NO_STRETCH, IS_I2C_OWN_ADDRESS1, IS_I2C_OWN_ADDRESS2, IS_I2C_OWN_ADDRESS2_MASK, __I2C_HandleTypeDef::Lock, __I2C_HandleTypeDef::Mode, I2C_InitTypeDef::NoStretchMode, I2C_InitTypeDef::OwnAddress1, I2C_InitTypeDef::OwnAddress2, I2C_InitTypeDef::OwnAddress2Masks, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, I2C_InitTypeDef::Timing, and TIMING_CLEAR_MASK.

void HAL_I2C_MspDeInit ( I2C_HandleTypeDef * hi2c )

DeInitialize the I2C MSP.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 546 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_DeInit().

void HAL_I2C_MspInit ( I2C_HandleTypeDef * hi2c )

Initialize the I2C MSP.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 530 of file stm32h7xx_hal_i2c.c.

Referenced by HAL_I2C_Init().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
I2C Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master/host I2C process communication with Interrupt.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the I2C data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_I2C_Master_Transmit()
        (++) HAL_I2C_Master_Receive()
        (++) HAL_I2C_Slave_Transmit()
        (++) HAL_I2C_Slave_Receive()
        (++) HAL_I2C_Mem_Write()
        (++) HAL_I2C_Mem_Read()
        (++) HAL_I2C_IsDeviceReady()

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_I2C_Master_Transmit_IT()
        (++) HAL_I2C_Master_Receive_IT()
        (++) HAL_I2C_Slave_Transmit_IT()
        (++) HAL_I2C_Slave_Receive_IT()
        (++) HAL_I2C_Mem_Write_IT()
        (++) HAL_I2C_Mem_Read_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_I2C_Master_Transmit_DMA()
        (++) HAL_I2C_Master_Receive_DMA()
        (++) HAL_I2C_Slave_Transmit_DMA()
        (++) HAL_I2C_Slave_Receive_DMA()
        (++) HAL_I2C_Mem_Write_DMA()
        (++) HAL_I2C_Mem_Read_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_I2C_MemTxCpltCallback()
        (++) HAL_I2C_MemRxCpltCallback()
        (++) HAL_I2C_MasterTxCpltCallback()
        (++) HAL_I2C_MasterRxCpltCallback()
        (++) HAL_I2C_SlaveTxCpltCallback()
        (++) HAL_I2C_SlaveRxCpltCallback()
        (++) HAL_I2C_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_I2C_DisableListen_IT ( I2C_HandleTypeDef * hi2c )

Disable the Address listen mode with Interrupt.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C
Return values:
HAL status

Definition at line 2872 of file stm32h7xx_hal_i2c.c.

References HAL_I2C_MODE_NONE, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_STATE_MSK, I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_EnableListen_IT ( I2C_HandleTypeDef * hi2c )

Enable the Address listen mode with Interrupt.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 2848 of file stm32h7xx_hal_i2c.c.

References HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_IsDeviceReady | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Checks if target device is ready for communication.

Note:
This function is used with Memory devices
Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
Trials,: Number of trials
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 2443 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_InitTypeDef::AddressingMode, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, HAL_I2C_STATE_TIMEOUT, I2C_FLAG_AF, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_GENERATE_START, I2C_WaitOnFlagUntilTimeout(), __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Master_Abort_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master/host I2C process communication with Interrupt.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
Return values:
HAL status

Definition at line 2904 of file stm32h7xx_hal_i2c.c.

References HAL_I2C_MODE_MASTER, HAL_I2C_STATE_ABORT, I2C_AUTOEND_MODE, I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_GENERATE_STOP, I2C_TransferConfig(), I2C_XFER_CPLT_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Master_Receive | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receives in master mode an amount of data in blocking mode.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 752 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_READ, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 1487 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 1214 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_RX_IT, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
XferOptions,: Options of Transfer, value of
  • I2C_XferOptions_definition
Return values:
HAL status

Definition at line 2633 of file stm32h7xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_GENERATE_START_READ, I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_MASTER_BUSY_RX, I2C_TransferConfig(), I2C_XFER_RX_IT, IS_I2C_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
XferOptions,: Options of Transfer, value of
  • I2C_XferOptions_definition
Return values:
HAL status

Definition at line 2561 of file stm32h7xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_GENERATE_START_WRITE, I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_MASTER_BUSY_TX, I2C_TransferConfig(), I2C_XFER_TX_IT, IS_I2C_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in master mode an amount of data in blocking mode.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 629 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_WRITE, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 1380 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 1146 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_TX_IT, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Read an amount of data in blocking mode from a specific memory address.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
MemAddress,: Internal memory address
MemAddSize,: Size of internal memory address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1878 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_READ, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryRead(), I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Reads an amount of data in non-blocking mode with DMA from a specific memory address.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
MemAddress,: Internal memory address
MemAddSize,: Size of internal memory address
pData,: Pointer to data buffer
Size,: Amount of data to be read
Return values:
HAL status

Definition at line 2330 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_DMA(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_RequestMemoryRead(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), I2C_XFER_ERROR_IT, __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Read an amount of data in non-blocking mode with Interrupt from a specific memory address.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
MemAddress,: Internal memory address
MemAddSize,: Size of internal memory address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 2118 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_RequestMemoryRead(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), I2C_XFER_RX_IT, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Write an amount of data in blocking mode to a specific memory address.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
MemAddress,: Internal memory address
MemAddSize,: Size of internal memory address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1727 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryWrite(), I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in non-blocking mode with DMA to a specific memory address.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
MemAddress,: Internal memory address
MemAddSize,: Size of internal memory address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 2215 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_Master_ISR_DMA(), I2C_NO_OPTION_FRAME, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryWrite(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), I2C_XFER_ERROR_IT, __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in non-blocking mode with Interrupt to a specific memory address.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
MemAddress,: Internal memory address
MemAddSize,: Size of internal memory address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 2020 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryWrite(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), I2C_XFER_TX_IT, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Receive | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive in slave mode an amount of data in blocking mode.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1015 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_FLAG_ADDR, I2C_FLAG_BUSY, I2C_FLAG_DIR, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 1658 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_DMAError(), I2C_DMASlaveReceiveCplt(), I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 1330 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
XferOptions,: Options of Transfer, value of
  • I2C_XferOptions_definition
Return values:
HAL status

Definition at line 2778 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_DIRECTION_TRANSMIT, I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
XferOptions,: Options of Transfer, value of
  • I2C_XferOptions_definition
Return values:
HAL status

Definition at line 2704 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_DIRECTION_RECEIVE, I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in slave mode an amount of data in blocking mode.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 875 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, I2C_InitTypeDef::AddressingMode, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_ADDRESSINGMODE_10BIT, I2C_FLAG_ADDR, I2C_FLAG_BUSY, I2C_FLAG_DIR, I2C_FLAG_STOPF, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 1592 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_DMAError(), I2C_DMASlaveTransmitCplt(), I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 1281 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRQ Handler and Callbacks

Functions
IRQ Handler and Callbacks
I2C Exported Functions

Functions

void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.

Function Documentation

void HAL_I2C_AbortCpltCallback ( I2C_HandleTypeDef * hi2c )

I2C abort callback.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3165 of file stm32h7xx_hal_i2c.c.

Referenced by I2C_DMAAbort(), and I2C_ITError().

void HAL_I2C_AddrCallback | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t | TransferDirection,
 |  | uint16_t | AddrMatchCode
 | ) |  |

Slave Address Match callback.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
TransferDirection,: Master request Transfer Direction (Write/Read), value of
  • I2C_XferOptions_definition
AddrMatchCode,: Address Match Code
Return values:
None

Definition at line 3083 of file stm32h7xx_hal_i2c.c.

Referenced by I2C_ITAddrCplt().

void HAL_I2C_ER_IRQHandler ( I2C_HandleTypeDef * hi2c )

This function handles I2C error interrupt request.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 2973 of file stm32h7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_ARLO, HAL_I2C_ERROR_BERR, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_OVR, I2C_FLAG_ARLO, I2C_FLAG_BERR, I2C_FLAG_OVR, I2C_IT_ERRI, I2C_ITError(), and __I2C_HandleTypeDef::Instance.

void HAL_I2C_ErrorCallback ( I2C_HandleTypeDef * hi2c )

I2C error callback.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3149 of file stm32h7xx_hal_i2c.c.

Referenced by I2C_DMAAbort(), and I2C_ITError().

void HAL_I2C_EV_IRQHandler ( I2C_HandleTypeDef * hi2c )

This function handles I2C event interrupt request.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 2954 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::XferISR.

void HAL_I2C_ListenCpltCallback ( I2C_HandleTypeDef * hi2c )

Listen Complete callback.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3101 of file stm32h7xx_hal_i2c.c.

Referenced by I2C_ITListenCplt(), and I2C_ITSlaveCplt().

void HAL_I2C_MasterRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Master Rx Transfer completed callback.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3034 of file stm32h7xx_hal_i2c.c.

Referenced by I2C_ITMasterCplt(), and I2C_ITMasterSequentialCplt().

void HAL_I2C_MasterTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Master Tx Transfer completed callback.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3018 of file stm32h7xx_hal_i2c.c.

Referenced by I2C_ITMasterCplt(), and I2C_ITMasterSequentialCplt().

void HAL_I2C_MemRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Memory Rx Transfer completed callback.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3133 of file stm32h7xx_hal_i2c.c.

Referenced by I2C_ITMasterCplt().

void HAL_I2C_MemTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Memory Tx Transfer completed callback.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3117 of file stm32h7xx_hal_i2c.c.

Referenced by I2C_ITMasterCplt().

void HAL_I2C_SlaveRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Slave Rx Transfer completed callback.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3065 of file stm32h7xx_hal_i2c.c.

Referenced by I2C_ITSlaveCplt(), and I2C_ITSlaveSequentialCplt().

void HAL_I2C_SlaveTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Slave Tx Transfer completed callback.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3049 of file stm32h7xx_hal_i2c.c.

Referenced by I2C_ITSlaveCplt(), and I2C_ITSlaveSequentialCplt().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State, Mode and Error functions

Functions
Peripheral State, Mode and Error functions
I2C Exported Functions

Peripheral State, Mode and Error functions. More...

Functions

HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

Peripheral State, Mode and Error functions.

 ===============================================================================
            ##### Peripheral State, Mode and Error functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_I2C_GetError ( I2C_HandleTypeDef * hi2c )

Return the I2C error code.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
I2C Error Code

Definition at line 3223 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode.

HAL_I2C_ModeTypeDef HAL_I2C_GetMode ( I2C_HandleTypeDef * hi2c )

Returns the I2C Master, Slave, Memory or no mode.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL mode

Definition at line 3212 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::Mode.

HAL_I2C_StateTypeDef HAL_I2C_GetState ( I2C_HandleTypeDef * hi2c )

Return the I2C handle state.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL state

Definition at line 3200 of file stm32h7xx_hal_i2c.c.

References __I2C_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2C_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2C_InitTypeDef Struct Reference
I2C Configuration Structure definition

#include <stm32h7xx_hal_i2c.h>

Data Fields

uint32_t | Timing
uint32_t | OwnAddress1
uint32_t | AddressingMode
uint32_t | DualAddressMode
uint32_t | OwnAddress2
uint32_t | OwnAddress2Masks
uint32_t | GeneralCallMode
uint32_t | NoStretchMode

Detailed Description

Definition at line 66 of file stm32h7xx_hal_i2c.h.

Field Documentation

uint32_t I2C_InitTypeDef::AddressingMode

Specifies if 7-bit or 10-bit addressing mode is selected. This parameter can be a value of I2C Addressing Mode

Definition at line 75 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), and I2C_ITAddrCplt().

uint32_t I2C_InitTypeDef::DualAddressMode

Specifies if dual addressing mode is selected. This parameter can be a value of I2C Dual Addressing Mode

Definition at line 78 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::GeneralCallMode

Specifies if general call mode is selected. This parameter can be a value of I2C General Call Addressing Mode

Definition at line 87 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::NoStretchMode

Specifies if nostretch mode is selected. This parameter can be a value of I2C No-Stretch Mode

Definition at line 90 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress1

Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.

Definition at line 72 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress2

Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address.

Definition at line 81 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress2Masks

Specifies the acknowledge mask address second device own address if dual addressing mode is selected This parameter can be a value of I2C Own Address2 Masks

Definition at line 84 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::Timing

Specifies the I2C_TIMINGR_register value. This parameter calculated by referring to I2C initialization section in Reference manual

Definition at line 68 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_i2c.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HAL state structure definition

Enumerations
HAL state structure definition
I2C Exported Types

HAL State structure definition. More...

Enumerations

enum HAL_I2C_StateTypeDef {
HAL_I2C_STATE_RESET = 0x00U, HAL_I2C_STATE_READY = 0x20U, HAL_I2C_STATE_BUSY = 0x24U, HAL_I2C_STATE_BUSY_TX = 0x21U,
HAL_I2C_STATE_BUSY_RX = 0x22U, HAL_I2C_STATE_LISTEN = 0x28U, HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU,
HAL_I2C_STATE_ABORT = 0x60U, HAL_I2C_STATE_TIMEOUT = 0xA0U, HAL_I2C_STATE_ERROR = 0xE0U
}

Detailed Description

HAL State structure definition.

Enumeration Type Documentation

enum HAL_I2C_StateTypeDef
Enumerator:
HAL_I2C_STATE_RESET

Peripheral is not yet Initialized

HAL_I2C_STATE_READY

Peripheral Initialized and ready for use

HAL_I2C_STATE_BUSY

An internal process is ongoing

HAL_I2C_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_I2C_STATE_BUSY_RX

Data Reception process is ongoing

HAL_I2C_STATE_LISTEN

Address Listen Mode is ongoing

HAL_I2C_STATE_BUSY_TX_LISTEN

Address Listen Mode and Data Transmission process is ongoing

HAL_I2C_STATE_BUSY_RX_LISTEN

Address Listen Mode and Data Reception process is ongoing

HAL_I2C_STATE_ABORT

Abort user request ongoing

HAL_I2C_STATE_TIMEOUT

Timeout state

HAL_I2C_STATE_ERROR

Error

Definition at line 104 of file stm32h7xx_hal_i2c.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HAL mode structure definition

Enumerations
HAL mode structure definition
I2C Exported Types

HAL Mode structure definition. More...

Enumerations

enum HAL_I2C_ModeTypeDef { HAL_I2C_MODE_NONE = 0x00U, HAL_I2C_MODE_MASTER = 0x10U, HAL_I2C_MODE_SLAVE = 0x20U, HAL_I2C_MODE_MEM = 0x40U }

Detailed Description

HAL Mode structure definition.

Enumeration Type Documentation

enum HAL_I2C_ModeTypeDef
Enumerator:
HAL_I2C_MODE_NONE

No I2C communication on going

HAL_I2C_MODE_MASTER

I2C communication is in Master Mode

HAL_I2C_MODE_SLAVE

I2C communication is in Slave Mode

HAL_I2C_MODE_MEM

I2C communication is in Memory Mode

Definition at line 130 of file stm32h7xx_hal_i2c.h.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2C Error Code definition

Defines
I2C Error Code definition
I2C Exported Types

I2C Error Code definition. More...

Defines

#define | HAL_I2C_ERROR_NONE (0x00000000U)
#define | HAL_I2C_ERROR_BERR (0x00000001U)
#define | HAL_I2C_ERROR_ARLO (0x00000002U)
#define | HAL_I2C_ERROR_AF (0x00000004U)
#define | HAL_I2C_ERROR_OVR (0x00000008U)
#define | HAL_I2C_ERROR_DMA (0x00000010U)
#define | HAL_I2C_ERROR_TIMEOUT (0x00000020U)
#define | HAL_I2C_ERROR_SIZE (0x00000040U)

Detailed Description

I2C Error Code definition.

Define Documentation

#define HAL_I2C_ERROR_AF (0x00000004U)

ACKF error

Definition at line 150 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_IsAcknowledgeFailed(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define HAL_I2C_ERROR_ARLO (0x00000002U)

ARLO error

Definition at line 149 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_BERR (0x00000001U)

BERR error

Definition at line 148 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 152 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_DMAError().

#define HAL_I2C_ERROR_NONE (0x00000000U)

No error

Definition at line 147 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define HAL_I2C_ERROR_OVR (0x00000008U)

OVR error

Definition at line 151 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_SIZE (0x00000040U)

Size Management error

Definition at line 154 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define HAL_I2C_ERROR_TIMEOUT (0x00000020U)

Timeout error

Definition at line 153 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Receive(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2C handle Structure definition

Data Structures | Typedefs
I2C handle Structure definition
I2C Exported Types

I2C handle Structure definition. More...

Data Structures

struct | __I2C_HandleTypeDef

Typedefs

typedef struct __I2C_HandleTypeDef | I2C_HandleTypeDef

Detailed Description

I2C handle Structure definition.

Typedef Documentation

typedef struct __I2C_HandleTypeDef I2C_HandleTypeDef
Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: __I2C_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__I2C_HandleTypeDef Struct Reference
I2C handle Structure definition

#include <stm32h7xx_hal_i2c.h>

Data Fields

I2C_TypeDef * | Instance
I2C_InitTypeDef Init
uint8_t * | pBuffPtr
uint16_t | XferSize
__IO uint16_t | XferCount
__IO uint32_t | XferOptions
__IO uint32_t | PreviousState
HAL_StatusTypeDef(* | XferISR )(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_I2C_StateTypeDef | State
__IO HAL_I2C_ModeTypeDef | Mode
__IO uint32_t | ErrorCode
__IO uint32_t | AddrEventCount

Detailed Description

Definition at line 163 of file stm32h7xx_hal_i2c.h.

Field Documentation

__IO uint32_t __I2C_HandleTypeDef::AddrEventCount

I2C Address Event counter

Definition at line 194 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

__IO uint32_t __I2C_HandleTypeDef::ErrorCode

I2C Error code

Definition at line 192 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_GetError(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_IsAcknowledgeFailed(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

DMA_HandleTypeDef* __I2C_HandleTypeDef::hdmarx

I2C Rx DMA handle parameters

Definition at line 184 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Slave_Receive_DMA(), I2C_DMAAbort(), I2C_DMAMasterReceiveCplt(), and I2C_ITError().

DMA_HandleTypeDef* __I2C_HandleTypeDef::hdmatx

I2C Tx DMA handle parameters

Definition at line 182 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Transmit_DMA(), I2C_DMAAbort(), I2C_DMAMasterTransmitCplt(), and I2C_ITError().

I2C_InitTypeDef __I2C_HandleTypeDef::Init

I2C communication parameters

Definition at line 167 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), and I2C_ITAddrCplt().

I2C_TypeDef* __I2C_HandleTypeDef::Instance

I2C registers base address

Definition at line 165 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_EV_IRQHandler(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), HAL_I2CEx_EnableWakeUp(), I2C_DMAAbort(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_Flush_TXDR(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_Slave_ISR_IT(), and I2C_TransferConfig().

HAL_LockTypeDef __I2C_HandleTypeDef::Lock

I2C locking object

Definition at line 186 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

__IO HAL_I2C_ModeTypeDef __I2C_HandleTypeDef::Mode

I2C communication mode

Definition at line 190 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_GetMode(), HAL_I2C_Init(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_IsAcknowledgeFailed(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSequentialCplt(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

uint8_t* __I2C_HandleTypeDef::pBuffPtr

Pointer to I2C transfer buffer

Definition at line 169 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

__IO uint32_t __I2C_HandleTypeDef::PreviousState

I2C communication Previous state

Definition at line 178 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_Init(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSequentialCplt().

__IO HAL_I2C_StateTypeDef __I2C_HandleTypeDef::State

I2C communication state

Definition at line 188 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_GetState(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), HAL_I2CEx_EnableWakeUp(), I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_IsAcknowledgeFailed(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSequentialCplt(), I2C_Master_ISR_DMA(), I2C_Slave_ISR_IT(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

__IO uint16_t __I2C_HandleTypeDef::XferCount

I2C transfer counter

Definition at line 173 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

HAL_StatusTypeDef(* __I2C_HandleTypeDef::XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)

I2C transfer IRQ handler function pointer

Definition at line 180 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_EV_IRQHandler(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), and I2C_ITSlaveCplt().

__IO uint32_t __I2C_HandleTypeDef::XferOptions

I2C sequantial transfer options, this parameter can be a value of I2C Sequential Transfer Options

Definition at line 175 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

uint16_t __I2C_HandleTypeDef::XferSize

I2C transfer size

Definition at line 171 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_i2c.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2C Sequential Transfer Options

Defines
I2C Sequential Transfer Options
I2C Exported Constants

Defines

#define | I2C_NO_OPTION_FRAME (0xFFFF0000U)
#define | I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)

Define Documentation

#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)

Definition at line 216 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Slave_ISR_IT().

#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))

Definition at line 214 of file stm32h7xx_hal_i2c.h.

#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)

Definition at line 213 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Slave_ISR_IT().

#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)

Definition at line 217 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Slave_ISR_IT().

#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))

Definition at line 215 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Slave_ISR_IT().

#define I2C_NO_OPTION_FRAME (0xFFFF0000U)

Definition at line 212 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

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STM32H753xx HAL User Manual: I2C Addressing Mode

Defines
I2C Addressing Mode
I2C Exported Constants

Defines

#define | I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define | I2C_ADDRESSINGMODE_10BIT (0x00000002U)

Define Documentation

#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)

Definition at line 226 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_Slave_Transmit(), and I2C_ITAddrCplt().

#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)

Definition at line 225 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2C Dual Addressing Mode

Defines
I2C Dual Addressing Mode
I2C Exported Constants

Defines

#define | I2C_DUALADDRESS_DISABLE (0x00000000U)
#define | I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Define Documentation

#define I2C_DUALADDRESS_DISABLE (0x00000000U)

Definition at line 234 of file stm32h7xx_hal_i2c.h.

#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Definition at line 235 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2C Own Address2 Masks

Defines
I2C Own Address2 Masks
I2C Exported Constants

Defines

#define | I2C_OA2_NOMASK ((uint8_t)0x00U)
#define | I2C_OA2_MASK01 ((uint8_t)0x01U)
#define | I2C_OA2_MASK02 ((uint8_t)0x02U)
#define | I2C_OA2_MASK03 ((uint8_t)0x03U)
#define | I2C_OA2_MASK04 ((uint8_t)0x04U)
#define | I2C_OA2_MASK05 ((uint8_t)0x05U)
#define | I2C_OA2_MASK06 ((uint8_t)0x06U)
#define | I2C_OA2_MASK07 ((uint8_t)0x07U)

Define Documentation

#define I2C_OA2_MASK01 ((uint8_t)0x01U)

Definition at line 244 of file stm32h7xx_hal_i2c.h.

#define I2C_OA2_MASK02 ((uint8_t)0x02U)

Definition at line 245 of file stm32h7xx_hal_i2c.h.

#define I2C_OA2_MASK03 ((uint8_t)0x03U)

Definition at line 246 of file stm32h7xx_hal_i2c.h.

#define I2C_OA2_MASK04 ((uint8_t)0x04U)

Definition at line 247 of file stm32h7xx_hal_i2c.h.

#define I2C_OA2_MASK05 ((uint8_t)0x05U)

Definition at line 248 of file stm32h7xx_hal_i2c.h.

#define I2C_OA2_MASK06 ((uint8_t)0x06U)

Definition at line 249 of file stm32h7xx_hal_i2c.h.

#define I2C_OA2_MASK07 ((uint8_t)0x07U)

Definition at line 250 of file stm32h7xx_hal_i2c.h.

#define I2C_OA2_NOMASK ((uint8_t)0x00U)

Definition at line 243 of file stm32h7xx_hal_i2c.h.

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STM32H753xx HAL User Manual: I2C General Call Addressing Mode

Defines
I2C General Call Addressing Mode
I2C Exported Constants

Defines

#define | I2C_GENERALCALL_DISABLE (0x00000000U)
#define | I2C_GENERALCALL_ENABLE I2C_CR1_GCEN

Define Documentation

#define I2C_GENERALCALL_DISABLE (0x00000000U)

Definition at line 258 of file stm32h7xx_hal_i2c.h.

#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN

Definition at line 259 of file stm32h7xx_hal_i2c.h.

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STM32H753xx HAL User Manual: I2C No-Stretch Mode

Defines
I2C No-Stretch Mode
I2C Exported Constants

Defines

#define | I2C_NOSTRETCH_DISABLE (0x00000000U)
#define | I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Define Documentation

#define I2C_NOSTRETCH_DISABLE (0x00000000U)

Definition at line 267 of file stm32h7xx_hal_i2c.h.

#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Definition at line 268 of file stm32h7xx_hal_i2c.h.

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STM32H753xx HAL User Manual: I2C Memory Address Size

Defines
I2C Memory Address Size
I2C Exported Constants

Defines

#define | I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define | I2C_MEMADD_SIZE_16BIT (0x00000002U)

Define Documentation

#define I2C_MEMADD_SIZE_16BIT (0x00000002U)

Definition at line 277 of file stm32h7xx_hal_i2c.h.

#define I2C_MEMADD_SIZE_8BIT (0x00000001U)

Definition at line 276 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2C Transfer Direction

Defines
I2C Transfer Direction
I2C Exported Constants

Defines

#define | I2C_DIRECTION_TRANSMIT (0x00000000U)
#define | I2C_DIRECTION_RECEIVE (0x00000001U)

Define Documentation

#define I2C_DIRECTION_RECEIVE (0x00000001U)

Definition at line 286 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Sequential_Transmit_IT().

#define I2C_DIRECTION_TRANSMIT (0x00000000U)

Definition at line 285 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Sequential_Receive_IT().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2C Reload End Mode

Defines
I2C Reload End Mode
I2C Exported Constants

Defines

#define | I2C_RELOAD_MODE I2C_CR2_RELOAD
#define | I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define | I2C_SOFTEND_MODE (0x00000000U)

Define Documentation

#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND

Definition at line 295 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define I2C_RELOAD_MODE I2C_CR2_RELOAD

Definition at line 294 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_RequestMemoryWrite().

#define I2C_SOFTEND_MODE (0x00000000U)

Definition at line 296 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead().

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STM32H753xx HAL User Manual: I2C Start or Stop Mode

Defines
I2C Start or Stop Mode
I2C Exported Constants

Defines

#define | I2C_NO_STARTSTOP (0x00000000U)
#define | I2C_GENERATE_STOP I2C_CR2_STOP
#define | I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | I2C_GENERATE_START_WRITE I2C_CR2_START

Define Documentation

#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)

Definition at line 306 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), and HAL_I2C_Mem_Read_IT().

#define I2C_GENERATE_START_WRITE I2C_CR2_START

Definition at line 307 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_GENERATE_STOP I2C_CR2_STOP

Definition at line 305 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Abort_IT().

#define I2C_NO_STARTSTOP (0x00000000U)

Definition at line 304 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

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STM32H753xx HAL User Manual: I2C Interrupt configuration definition

Defines
I2C Interrupt configuration definition
I2C Exported Constants

I2C Interrupt definition Elements values convention: 0xXXXXXXXX. More...

Defines

#define | I2C_IT_ERRI I2C_CR1_ERRIE
#define | I2C_IT_TCI I2C_CR1_TCIE
#define | I2C_IT_STOPI I2C_CR1_STOPIE
#define | I2C_IT_NACKI I2C_CR1_NACKIE
#define | I2C_IT_ADDRI I2C_CR1_ADDRIE
#define | I2C_IT_RXI I2C_CR1_RXIE
#define | I2C_IT_TXI I2C_CR1_TXIE

Detailed Description

I2C Interrupt definition Elements values convention: 0xXXXXXXXX.

  • XXXXXXXX : Interrupt control mask

Define Documentation

#define I2C_IT_ADDRI I2C_CR1_ADDRIE

Definition at line 322 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_IT_ERRI I2C_CR1_ERRIE

Definition at line 318 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_Disable_IRQ(), and I2C_Enable_IRQ().

#define I2C_IT_NACKI I2C_CR1_NACKIE

Definition at line 321 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_IT_RXI I2C_CR1_RXIE

Definition at line 323 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

#define I2C_IT_STOPI I2C_CR1_STOPIE

Definition at line 320 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_IT_TCI I2C_CR1_TCIE

Definition at line 319 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define I2C_IT_TXI I2C_CR1_TXIE

Definition at line 324 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

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STM32H753xx HAL User Manual: I2C Flag definition

Defines
I2C Flag definition
I2C Exported Constants

Defines

#define | I2C_FLAG_TXE I2C_ISR_TXE
#define | I2C_FLAG_TXIS I2C_ISR_TXIS
#define | I2C_FLAG_RXNE I2C_ISR_RXNE
#define | I2C_FLAG_ADDR I2C_ISR_ADDR
#define | I2C_FLAG_AF I2C_ISR_NACKF
#define | I2C_FLAG_STOPF I2C_ISR_STOPF
#define | I2C_FLAG_TC I2C_ISR_TC
#define | I2C_FLAG_TCR I2C_ISR_TCR
#define | I2C_FLAG_BERR I2C_ISR_BERR
#define | I2C_FLAG_ARLO I2C_ISR_ARLO
#define | I2C_FLAG_OVR I2C_ISR_OVR
#define | I2C_FLAG_PECERR I2C_ISR_PECERR
#define | I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | I2C_FLAG_ALERT I2C_ISR_ALERT
#define | I2C_FLAG_BUSY I2C_ISR_BUSY
#define | I2C_FLAG_DIR I2C_ISR_DIR

Define Documentation

#define I2C_FLAG_ADDR I2C_ISR_ADDR

Definition at line 335 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), I2C_ITAddrCplt(), I2C_ITSlaveCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_FLAG_AF I2C_ISR_NACKF

Definition at line 336 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), I2C_IsAcknowledgeFailed(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_FLAG_ALERT I2C_ISR_ALERT

Definition at line 345 of file stm32h7xx_hal_i2c.h.

#define I2C_FLAG_ARLO I2C_ISR_ARLO

Definition at line 341 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_BERR I2C_ISR_BERR

Definition at line 340 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_BUSY I2C_ISR_BUSY

Definition at line 346 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), and HAL_I2C_Slave_Transmit().

#define I2C_FLAG_DIR I2C_ISR_DIR

Definition at line 347 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Receive(), and HAL_I2C_Slave_Transmit().

#define I2C_FLAG_OVR I2C_ISR_OVR

Definition at line 342 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_PECERR I2C_ISR_PECERR

Definition at line 343 of file stm32h7xx_hal_i2c.h.

#define I2C_FLAG_RXNE I2C_ISR_RXNE

Definition at line 334 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Slave_Receive(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_IT(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define I2C_FLAG_STOPF I2C_ISR_STOPF

Definition at line 337 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_IsAcknowledgeFailed(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), I2C_WaitOnRXNEFlagUntilTimeout(), and I2C_WaitOnSTOPFlagUntilTimeout().

#define I2C_FLAG_TC I2C_ISR_TC

Definition at line 338 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Master_ISR_IT(), and I2C_RequestMemoryRead().

#define I2C_FLAG_TCR I2C_ISR_TCR

Definition at line 339 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_RequestMemoryWrite().

#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT

Definition at line 344 of file stm32h7xx_hal_i2c.h.

#define I2C_FLAG_TXE I2C_ISR_TXE

Definition at line 332 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Flush_TXDR().

#define I2C_FLAG_TXIS I2C_ISR_TXIS

Definition at line 333 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Flush_TXDR(), I2C_Master_ISR_IT(), I2C_Slave_ISR_IT(), and I2C_WaitOnTXISFlagUntilTimeout().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2C Exported Macros

Defines
I2C Exported Macros
I2C

Defines

#define | __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
Reset I2C handle state.
#define | __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified I2C interrupt.
#define | __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified I2C interrupt.
#define | __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified I2C interrupt source is enabled or not.
#define | __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
Check whether the specified I2C flag is set or not.
#define | __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified I2C peripheral.
#define | __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified I2C peripheral.
#define | __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge I2C peripheral in Slave mode.

Define Documentation

#define __HAL_I2C_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
                                                                                : ((__HANDLE__)->Instance->ICR = (__FLAG__)))

Clear the I2C pending flags which are cleared by writing 1 in a specific bit.

Parameters:
__HANDLE__ specifies the I2C Handle.
__FLAG__ specifies the flag to clear. This parameter can be any combination of the following values:
  • I2C_FLAG_TXE Transmit data register empty
  • I2C_FLAG_ADDR Address matched (slave mode)
  • I2C_FLAG_AF Acknowledge failure received flag
  • I2C_FLAG_STOPF STOP detection flag
  • I2C_FLAG_BERR Bus error
  • I2C_FLAG_ARLO Arbitration lost
  • I2C_FLAG_OVR Overrun/Underrun
  • I2C_FLAG_PECERR PEC error in reception
  • I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
  • I2C_FLAG_ALERT SMBus alert
Return values:
None

Definition at line 458 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), I2C_Flush_TXDR(), I2C_IsAcknowledgeFailed(), I2C_ITAddrCplt(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define __HAL_I2C_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Disable the specified I2C peripheral.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 471 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_Init(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), and HAL_I2CEx_EnableWakeUp().

#define __HAL_I2C_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))

Disable the specified I2C interrupt.

Parameters:
__HANDLE__ specifies the I2C Handle.
__INTERRUPT__ specifies the interrupt source to disable. This parameter can be one of the following values:
  • I2C_IT_ERRI Errors interrupt enable
  • I2C_IT_TCI Transfer complete interrupt enable
  • I2C_IT_STOPI STOP detection interrupt enable
  • I2C_IT_NACKI NACK received interrupt enable
  • I2C_IT_ADDRI Address match interrupt enable
  • I2C_IT_RXI RX interrupt enable
  • I2C_IT_TXI TX interrupt enable
Return values:
None

Definition at line 398 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), and I2C_Master_ISR_DMA().

#define __HAL_I2C_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Enable the specified I2C peripheral.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 465 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), and HAL_I2CEx_EnableWakeUp().

#define __HAL_I2C_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))

Enable the specified I2C interrupt.

Parameters:
__HANDLE__ specifies the I2C Handle.
__INTERRUPT__ specifies the interrupt source to enable. This parameter can be one of the following values:
  • I2C_IT_ERRI Errors interrupt enable
  • I2C_IT_TCI Transfer complete interrupt enable
  • I2C_IT_STOPI STOP detection interrupt enable
  • I2C_IT_NACKI NACK received interrupt enable
  • I2C_IT_ADDRI Address match interrupt enable
  • I2C_IT_RXI RX interrupt enable
  • I2C_IT_TXI TX interrupt enable
Return values:
None

Definition at line 382 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Enable_IRQ().

#define __HAL_I2C_GENERATE_NACK ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))

Generate a Non-Acknowledge I2C peripheral in Slave mode.

Parameters:
__HANDLE__,: specifies the I2C Handle.
Return values:
None

Definition at line 477 of file stm32h7xx_hal_i2c.h.

#define __HAL_I2C_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)

Check whether the specified I2C flag is set or not.

Parameters:
__HANDLE__ specifies the I2C Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • I2C_FLAG_TXE Transmit data register empty
  • I2C_FLAG_TXIS Transmit interrupt status
  • I2C_FLAG_RXNE Receive data register not empty
  • I2C_FLAG_ADDR Address matched (slave mode)
  • I2C_FLAG_AF Acknowledge failure received flag
  • I2C_FLAG_STOPF STOP detection flag
  • I2C_FLAG_TC Transfer complete (master mode)
  • I2C_FLAG_TCR Transfer complete reload
  • I2C_FLAG_BERR Bus error
  • I2C_FLAG_ARLO Arbitration lost
  • I2C_FLAG_OVR Overrun/Underrun
  • I2C_FLAG_PECERR PEC error in reception
  • I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
  • I2C_FLAG_ALERT SMBus alert
  • I2C_FLAG_BUSY Bus busy
  • I2C_FLAG_DIR Transfer direction (slave mode)
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 439 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), I2C_Flush_TXDR(), I2C_IsAcknowledgeFailed(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

#define __HAL_I2C_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified I2C interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the I2C Handle.
__INTERRUPT__ specifies the I2C interrupt source to check. This parameter can be one of the following values:
  • I2C_IT_ERRI Errors interrupt enable
  • I2C_IT_TCI Transfer complete interrupt enable
  • I2C_IT_STOPI STOP detection interrupt enable
  • I2C_IT_NACKI NACK received interrupt enable
  • I2C_IT_ADDRI Address match interrupt enable
  • I2C_IT_RXI RX interrupt enable
  • I2C_IT_TXI TX interrupt enable
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 414 of file stm32h7xx_hal_i2c.h.

#define __HAL_I2C_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)

Reset I2C handle state.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 366 of file stm32h7xx_hal_i2c.h.

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STM32H753xx HAL User Manual: I2C Private Constants

I2C Private Constants
I2C
Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2C Private Macros

Defines
I2C Private Macros
I2C

Defines

#define | IS_I2C_ADDRESSING_MODE(MODE)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_OWN_ADDRESS2_MASK(MASK)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_MEMADD_SIZE(SIZE)
#define | IS_TRANSFER_MODE(MODE)
#define | IS_TRANSFER_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
#define | I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define | I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
#define | I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define | I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | I2C_GENERATE_START(__ADDMODE__, __ADDRESS__)

Define Documentation

#define I2C_GENERATE_START | ( | __ADDMODE__,
 |  | __ADDRESS__
 | ) |
Value:
(((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
                                                          (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))

Definition at line 645 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady().

#define I2C_GET_ADDR_MATCH ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)

Definition at line 633 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

#define I2C_GET_DIR ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)

Definition at line 634 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), and I2C_ITAddrCplt().

#define I2C_GET_OWN_ADDRESS1 ( __HANDLE__ ) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)

Definition at line 636 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

#define I2C_GET_OWN_ADDRESS2 ( __HANDLE__ ) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)

Definition at line 637 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

#define I2C_GET_STOP_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)

Definition at line 635 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_Master_ISR_IT().

#define I2C_MEM_ADD_LSB ( __ADDRESS__ ) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))

Definition at line 643 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_MEM_ADD_MSB ( __ADDRESS__ ) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))

Definition at line 642 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_RESET_CR2 ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))

Definition at line 631 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), I2C_IsAcknowledgeFailed(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define IS_I2C_ADDRESSING_MODE ( MODE )
Value:
(((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))

Definition at line 592 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_DUAL_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))

Definition at line 595 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_GENERAL_CALL ( CALL )
Value:
(((CALL) == I2C_GENERALCALL_DISABLE) || \
                                         ((CALL) == I2C_GENERALCALL_ENABLE))

Definition at line 607 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_MEMADD_SIZE ( SIZE )
Value:
(((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))

Definition at line 613 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

#define IS_I2C_NO_STRETCH ( STRETCH )
Value:
(((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))

Definition at line 610 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS1 ( ADDRESS1 ) ((ADDRESS1) <= 0x000003FFU)

Definition at line 639 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS2 ( ADDRESS2 ) ((ADDRESS2) <= (uint16_t)0x00FFU)

Definition at line 640 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS2_MASK ( MASK )
Value:
(((MASK) == I2C_OA2_NOMASK)  || \
                                         ((MASK) == I2C_OA2_MASK01) || \
                                         ((MASK) == I2C_OA2_MASK02) || \
                                         ((MASK) == I2C_OA2_MASK03) || \
                                         ((MASK) == I2C_OA2_MASK04) || \
                                         ((MASK) == I2C_OA2_MASK05) || \
                                         ((MASK) == I2C_OA2_MASK06) || \
                                         ((MASK) == I2C_OA2_MASK07))

Definition at line 598 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_TRANSFER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == I2C_FIRST_FRAME)          || \
                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \
                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
                                                   ((REQUEST) == I2C_LAST_FRAME))

Definition at line 625 of file stm32h7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), and HAL_I2C_Slave_Sequential_Transmit_IT().

#define IS_TRANSFER_MODE ( MODE )
Value:
(((MODE) == I2C_RELOAD_MODE)   || \
                                         ((MODE) == I2C_AUTOEND_MODE) || \
                                         ((MODE) == I2C_SOFTEND_MODE))

Definition at line 616 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_TransferConfig().

#define IS_TRANSFER_REQUEST ( REQUEST )
Value:
(((REQUEST) == I2C_GENERATE_STOP)        || \
                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \
                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \
                                         ((REQUEST) == I2C_NO_STARTSTOP))

Definition at line 620 of file stm32h7xx_hal_i2c.h.

Referenced by I2C_TransferConfig().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2C

Modules | Defines
I2C
STM32H7xx_HAL_Driver

I2C HAL module driver. More...

Modules

I2C Private Define
I2C Private Functions
I2C Exported Functions
I2C Exported Types
I2C Exported Constants
I2C Exported Macros
I2C Private Constants
I2C Private Macros

Defines

#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__)

Detailed Description

I2C HAL module driver.

Define Documentation

#define I2C_GET_DMA_REMAIN_DATA ( __HANDLE__ )
Value:
(((__HANDLE__)->Instance == I2C4)?                                                  \
                                             ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ?                                \
                                              ((uint32_t)(((BDMA_Channel_TypeDef *)(__HANDLE__)->hdmatx->Instance)->CNDTR)) :  \
                                              ((uint32_t)(((BDMA_Channel_TypeDef *)(__HANDLE__)->hdmarx->Instance)->CNDTR))) : \
                                             ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ?                                \
                                              ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmatx->Instance)->NDTR)) :   \
                                              ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmarx->Instance)->NDTR))))

Definition at line 302 of file stm32h7xx_hal_i2c.c.

Referenced by I2C_ITSlaveCplt(), and I2C_Slave_ISR_DMA().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2C Extended Private Constants

I2C Extended Private Constants
Extended features functions
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STM32H753xx HAL User Manual: I2C Extended Private Macros

Defines
I2C Extended Private Macros
Extended features functions

Defines

#define | IS_I2C_ANALOG_FILTER(FILTER)
#define | IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_I2C_FASTMODEPLUS(__CONFIG__)

Define Documentation

#define IS_I2C_ANALOG_FILTER ( FILTER )
Value:
(((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))

Definition at line 126 of file stm32h7xx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_ConfigAnalogFilter().

#define IS_I2C_DIGITAL_FILTER ( FILTER ) ((FILTER) <= 0x0000000FU)

Definition at line 129 of file stm32h7xx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_ConfigDigitalFilter().

#define IS_I2C_FASTMODEPLUS ( __CONFIG__ )
Value:
((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \
                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))

Definition at line 132 of file stm32h7xx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_DisableFastModePlus(), and HAL_I2CEx_EnableFastModePlus().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2C Extended Private Functions

I2C Extended Private Functions
Extended features functions
Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Extended features functions

Modules | Functions
Extended features functions
I2C Extended Exported Functions

Extended features functions. More...

Modules

I2C Extended Private Constants
I2C Extended Private Macros
I2C Extended Private Functions

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configure I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configure I2C Digital noise filter.
HAL_StatusTypeDef | HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
Enable I2C wakeup from stop mode.
HAL_StatusTypeDef | HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
Disable I2C wakeup from stop mode.
void | HAL_I2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
void | HAL_I2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.

Detailed Description

Extended features functions.

 ===============================================================================
                      ##### Extended features functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Configure Noise Filters
      (+) Configure Wake Up Feature
      (+) Configure Fast Mode Plus

Function Documentation

HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | AnalogFilter
 | ) |  |

Configure I2C Analog noise filter.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
AnalogFilter,: New state of the Analog filter.
Return values:
HAL status

Definition at line 115 of file stm32h7xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, IS_I2C_ANALOG_FILTER, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure I2C Digital noise filter.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
DigitalFilter,: Coefficient of digital noise filter between 0x00 and 0x0F.
Return values:
HAL status

Definition at line 159 of file stm32h7xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, IS_I2C_DIGITAL_FILTER, and __I2C_HandleTypeDef::State.

void HAL_I2CEx_DisableFastModePlus ( uint32_t ConfigFastModePlus )

Disable the I2C fast mode plus driving capability.

Parameters:
ConfigFastModePlus,: Selects the pin. This parameter can be one of the I2C Extended Fast Mode Plus values
Return values:
None

Definition at line 306 of file stm32h7xx_hal_i2c_ex.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, and IS_I2C_FASTMODEPLUS.

HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp ( I2C_HandleTypeDef * hi2c )

Disable I2C wakeup from stop mode.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
Return values:
HAL status

Definition at line 249 of file stm32h7xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::State.

void HAL_I2CEx_EnableFastModePlus ( uint32_t ConfigFastModePlus )

Enable the I2C fast mode plus driving capability.

Parameters:
ConfigFastModePlus,: Selects the pin. This parameter can be one of the I2C Extended Fast Mode Plus values
Return values:
None

Definition at line 288 of file stm32h7xx_hal_i2c_ex.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, and IS_I2C_FASTMODEPLUS.

HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp ( I2C_HandleTypeDef * hi2c )

Enable I2C wakeup from stop mode.

Parameters:
hi2c,: Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
Return values:
HAL status

Definition at line 210 of file stm32h7xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2C Extended Analog Filter

Defines
I2C Extended Analog Filter
I2C Extended Exported Constants

Defines

#define | I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U)
#define | I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Define Documentation

#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Definition at line 68 of file stm32h7xx_hal_i2c_ex.h.

#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U)

Definition at line 67 of file stm32h7xx_hal_i2c_ex.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2C Extended Fast Mode Plus

Defines
I2C Extended Fast Mode Plus
I2C Extended Exported Constants

Defines

#define | I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP
#define | I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP
#define | I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP
#define | I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP
#define | I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP
#define | I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP
#define | I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP
#define | I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP

Define Documentation

#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP

Definition at line 81 of file stm32h7xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP

Definition at line 82 of file stm32h7xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP

Definition at line 83 of file stm32h7xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP

Definition at line 84 of file stm32h7xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP

Definition at line 76 of file stm32h7xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP

Definition at line 77 of file stm32h7xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP

Definition at line 78 of file stm32h7xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP

Definition at line 79 of file stm32h7xx_hal_i2c_ex.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2S Extended Private Typedef

Enumerations
I2S Extended Private Typedef
I2SEx

Enumerations

enum I2S_UseTypeDef { I2S_USE_I2S = 0x00U, I2S_USE_I2SEXT = 0x01U }

Enumeration Type Documentation

enum I2S_UseTypeDef
Enumerator:
I2S_USE_I2S

I2Sx should be used

I2S_USE_I2SEXT

I2Sx_ext should be used

Definition at line 107 of file stm32h7xx_hal_i2s_ex.c.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2S Extended Private Functions

Functions
I2S Extended Private Functions
I2SEx

Functions

static void | I2SEx_DMATxRxCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit receive process complete callback.
static void | I2SEx_DMATxRxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit receive process half complete callback.
static void | I2SEx_TxRxDMAError (DMA_HandleTypeDef *hdma)
DMA I2S communication error callback.
static void | I2SEx_2linesTxISR_16BIT (struct __I2S_HandleTypeDef *hi2s)
Tx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | I2SEx_2linesTxISR_32BIT (struct __I2S_HandleTypeDef *hi2s)
Tx 32-bit handler for Transmit and Receive in Interrupt mode.
static void | I2SEx_2linesRxISR_16BIT (struct __I2S_HandleTypeDef *hi2s)
Rx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | I2SEx_2linesRxISR_32BIT (struct __I2S_HandleTypeDef *hi2s)
Rx 32-bit handler for Transmit and Receive in Interrupt mode.
static void | I2SEx_CloseRxTx_ISR (I2S_HandleTypeDef *hi2s)
Handle the end of the RXTX transaction.
static HAL_StatusTypeDef | I2SEx_WaitFlagStateUntilTimeout (I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
This function handles I2S Communication Timeout.

Function Documentation

static void I2SEx_2linesRxISR_16BIT ( struct __I2S_HandleTypeDef * hi2s ) [static]

Rx 16-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module.
Return values:
None

Definition at line 730 of file stm32h7xx_hal_i2s_ex.c.

References __HAL_I2S_DISABLE_IT, I2S_IT_RXNE, I2SEx_CloseRxTx_ISR(), __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::RxXferCount, and __I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2SEx_TransmitReceive_IT().

static void I2SEx_2linesRxISR_32BIT ( struct __I2S_HandleTypeDef * hi2s ) [static]

Rx 32-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module.
Return values:
None

Definition at line 755 of file stm32h7xx_hal_i2s_ex.c.

References __HAL_I2S_DISABLE_IT, I2S_IT_RXNE, I2SEx_CloseRxTx_ISR(), __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::RxXferCount, and __I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2SEx_TransmitReceive_IT().

static void I2SEx_2linesTxISR_16BIT ( struct __I2S_HandleTypeDef * hi2s ) [static]

Tx 16-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module.
Return values:
None

Definition at line 780 of file stm32h7xx_hal_i2s_ex.c.

References __HAL_I2S_DISABLE_IT, I2S_IT_TXE, I2SEx_CloseRxTx_ISR(), __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::RxXferCount, and __I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2SEx_TransmitReceive_IT().

static void I2SEx_2linesTxISR_32BIT ( struct __I2S_HandleTypeDef * hi2s ) [static]

Tx 32-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module.
Return values:
None

Definition at line 806 of file stm32h7xx_hal_i2s_ex.c.

References __HAL_I2S_DISABLE_IT, I2S_IT_TXE, I2SEx_CloseRxTx_ISR(), __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::RxXferCount, and __I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2SEx_TransmitReceive_IT().

static void I2SEx_CloseRxTx_ISR ( I2S_HandleTypeDef * hi2s ) [static]

Handle the end of the RXTX transaction.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module.
Return values:
None

Definition at line 832 of file stm32h7xx_hal_i2s_ex.c.

References __HAL_I2S_DISABLE_IT, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_ErrorCallback(), HAL_I2S_RxCpltCallback(), HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, HAL_I2SEx_TxRxCpltCallback(), I2S_IT_ERR, I2S_IT_RXNE, I2S_IT_TXE, and __I2S_HandleTypeDef::State.

Referenced by I2SEx_2linesRxISR_16BIT(), I2SEx_2linesRxISR_32BIT(), I2SEx_2linesTxISR_16BIT(), and I2SEx_2linesTxISR_32BIT().

static void I2SEx_DMATxRxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S transmit receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 636 of file stm32h7xx_hal_i2s_ex.c.

References __HAL_I2S_DISABLE, __HAL_I2S_ENABLE, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_READY, HAL_I2SEx_TxRxCpltCallback(), __I2S_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::State, and __I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2SEx_TransmitReceive_DMA().

static void I2SEx_DMATxRxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S transmit receive process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 679 of file stm32h7xx_hal_i2s_ex.c.

References HAL_I2SEx_TxRxHalfCpltCallback().

Referenced by HAL_I2SEx_TransmitReceive_DMA().

static void I2SEx_TxRxDMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S communication error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 692 of file stm32h7xx_hal_i2s_ex.c.

References __HAL_I2S_DISABLE, __HAL_I2S_ENABLE, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_DMA, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_READY, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::State, and __I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2SEx_TransmitReceive_DMA().

static HAL_StatusTypeDef I2SEx_WaitFlagStateUntilTimeout | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint32_t | Flag,
 |  | uint32_t | State,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles I2S Communication Timeout.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Flag,: Flag checked
State,: Value of the flag expected
Timeout,: Duration of the timeout
Return values:
HAL status

Definition at line 866 of file stm32h7xx_hal_i2s_ex.c.

References __HAL_I2S_GET_FLAG, HAL_GetTick(), HAL_I2S_STATE_READY, and __I2S_HandleTypeDef::State.

Referenced by HAL_I2SEx_TransmitReceive().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2S Extended IO operation functions

Functions
I2S Extended IO operation functions
I2S Extended Exported Functions

I2SEx IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_I2SEx_TransmitReceive (I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2SEx_TransmitReceive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2SEx_TransmitReceive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
__weak void | HAL_I2SEx_TxRxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx/Rx Transfer half completed callbacks.
__weak void | HAL_I2SEx_TxRxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx/Rx Transfer completed callbacks.

Detailed Description

I2SEx IO operation functions.

 ===============================================================================
                       ##### IO operation functions#####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the I2S data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_I2SEx_TransmitReceive()

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_I2SEx_TransmitReceive_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_I2SEx_TransmitReceive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_I2SEx_TxRxCpltCallback()
        (++) HAL_I2SEx_TxRxErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_I2SEx_TransmitReceive | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pTxData,
 |  | uint16_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit and Receive an amount of data in blocking mode.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pTxData,: a 16-bit pointer to the Transmit data buffer
pRxData,: a 16-bit pointer to the Receive data buffer
Size,: number of frames to be sent
Timeout,: Timeout duration
Note:
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
Return values:
HAL status

Definition at line 196 of file stm32h7xx_hal_i2s_ex.c.

References __HAL_I2S_ENABLE, __HAL_I2S_GET_FLAG, assert_param, __I2S_HandleTypeDef::ErrorCode, I2S_InitTypeDef::FifoThreshold, HAL_GetTick(), HAL_I2S_ERROR_NONE, HAL_I2S_ERROR_TIMEOUT, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_BUSY_TX_RX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_FLAG_RXNE, I2S_FLAG_RXWNE, I2S_FLAG_TXE, I2SEx_WaitFlagStateUntilTimeout(), __I2S_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, IS_I2S_FD_MODE, IS_I2S_MASTER, I2S_InitTypeDef::Mode, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::RxXferSize, SPI_FIFO_THRESHOLD_01DATA, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxXferCount, and __I2S_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pTxData,
 |  | uint16_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in non-blocking mode with DMA.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pTxData,: a 16-bit pointer to the Transmit data buffer.
pRxData,: a 16-bit pointer to the Receive data buffer.
Size,: number of frames to be sent.
Note:
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 470 of file stm32h7xx_hal_i2s_ex.c.

References __HAL_I2S_DISABLE, __HAL_I2S_ENABLE, assert_param, __I2S_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_TX_RX, HAL_I2S_STATE_READY, __I2S_HandleTypeDef::hdmarx, __I2S_HandleTypeDef::hdmatx, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2SEx_DMATxRxCplt(), I2SEx_DMATxRxHalfCplt(), I2SEx_TxRxDMAError(), __I2S_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, IS_I2S_FD_MODE, I2S_InitTypeDef::Mode, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::RxXferSize, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxXferCount, __I2S_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pTxData,
 |  | uint16_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pTxData,: a 16-bit pointer to the Transmit data buffer.
pRxData,: a 16-bit pointer to the Receive data buffer.
Size,: number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
Return values:
HAL status

Definition at line 393 of file stm32h7xx_hal_i2s_ex.c.

References __HAL_I2S_ENABLE, __HAL_I2S_ENABLE_IT, assert_param, I2S_InitTypeDef::DataFormat, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_16B, I2S_IT_ERR, I2S_IT_RXNE, I2S_IT_TXE, I2SEx_2linesRxISR_16BIT(), I2SEx_2linesRxISR_32BIT(), I2SEx_2linesTxISR_16BIT(), I2SEx_2linesTxISR_32BIT(), __I2S_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, IS_I2S_FD_MODE, IS_I2S_MASTER, I2S_InitTypeDef::Mode, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::RxISR, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::RxXferSize, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxISR, __I2S_HandleTypeDef::TxXferCount, and __I2S_HandleTypeDef::TxXferSize.

void HAL_I2SEx_TxRxCpltCallback ( I2S_HandleTypeDef * hi2s )

Tx/Rx Transfer completed callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 608 of file stm32h7xx_hal_i2s_ex.c.

Referenced by I2SEx_CloseRxTx_ISR(), and I2SEx_DMATxRxCplt().

void HAL_I2SEx_TxRxHalfCpltCallback ( I2S_HandleTypeDef * hi2s )

Tx/Rx Transfer half completed callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 592 of file stm32h7xx_hal_i2s_ex.c.

Referenced by I2SEx_DMATxRxHalfCplt().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDA Private Constants

Defines
IRDA Private Constants
IRDA

Defines

#define | IRDA_TEACK_REACK_TIMEOUT 1000
#define | IRDA_CR1_FIELDS

Define Documentation

#define IRDA_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE \
                                   | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))

UART or USART CR1 fields of parameters set by IRDA_SetConfig API

Definition at line 161 of file stm32h7xx_hal_irda.c.

Referenced by IRDA_SetConfig().

#define IRDA_TEACK_REACK_TIMEOUT 1000

IRDA TX or RX enable acknowledge time-out value

Definition at line 160 of file stm32h7xx_hal_irda.c.

Referenced by IRDA_CheckIdleState().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
IRDA Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
Initialize the IRDA MSP.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the USARTx
  in asynchronous IRDA mode.
  (+) For the asynchronous mode only these parameters can be configured:
      (++) Baud Rate
      (++) Word Length
      (++) Parity: If the parity is enabled, then the MSB bit of the data written
           in the data register is transmitted but is changed by the parity bit.
      (++) Power mode
      (++) Prescaler setting
      (++) Receiver/transmitter modes

  [..]
  The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
  (details for the procedures are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible IRDA frame formats are listed in the following table.

Table 1. IRDA frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | IRDA frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_IRDA_DeInit ( IRDA_HandleTypeDef * hirda )

DeInitialize the IRDA peripheral.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 310 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_DISABLE, assert_param, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_NONE, HAL_IRDA_MspDeInit(), HAL_IRDA_STATE_BUSY, HAL_IRDA_STATE_RESET, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_Init ( IRDA_HandleTypeDef * hirda )

Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 257 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_DISABLE, __HAL_IRDA_ENABLE, assert_param, IRDA_HandleTypeDef::gState, HAL_IRDA_MspInit(), HAL_IRDA_STATE_BUSY, HAL_IRDA_STATE_RESET, IRDA_HandleTypeDef::Instance, IRDA_CheckIdleState(), IRDA_SetConfig(), and IRDA_HandleTypeDef::Lock.

void HAL_IRDA_MspDeInit ( IRDA_HandleTypeDef * hirda )

DeInitialize the IRDA MSP.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 360 of file stm32h7xx_hal_irda.c.

Referenced by HAL_IRDA_DeInit().

void HAL_IRDA_MspInit ( IRDA_HandleTypeDef * hirda )

Initialize the IRDA MSP.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 344 of file stm32h7xx_hal_irda.c.

Referenced by HAL_IRDA_Init().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
IRDA Exported Functions

IRDA Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_Abort (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_Abort_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
Handle IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer completed callback.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callback.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer completed callback.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callback.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callback.
__weak void | HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Receive Complete callback.

Detailed Description

IRDA Transmit and Receive functions.

  ==============================================================================
                         ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the IRDA data transfers.

  [..]
    IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
    is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
    While receiving data, transmission should be avoided as the data to be transmitted
    could be corrupted.

    (#) There are two modes of transfer:
        (++) Blocking mode: the communication is performed in polling mode.
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (++) Non-Blocking mode: the communication is performed using Interrupts
             or DMA, these API's return the HAL status.
             The end of the data processing will be indicated through the
             dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
             The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
             will be executed respectively at the end of the Transmit or Receive process
             The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected

    (#) Blocking mode APIs are :
        (++) HAL_IRDA_Transmit()
        (++) HAL_IRDA_Receive()

    (#) Non Blocking mode APIs with Interrupt are :
        (++) HAL_IRDA_Transmit_IT()
        (++) HAL_IRDA_Receive_IT()
        (++) HAL_IRDA_IRQHandler()

    (#) Non Blocking mode functions with DMA are :
        (++) HAL_IRDA_Transmit_DMA()
        (++) HAL_IRDA_Receive_DMA()
        (++) HAL_IRDA_DMAPause()
        (++) HAL_IRDA_DMAResume()
        (++) HAL_IRDA_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
        (++) HAL_IRDA_TxHalfCpltCallback()
        (++) HAL_IRDA_TxCpltCallback()
        (++) HAL_IRDA_RxHalfCpltCallback()
        (++) HAL_IRDA_RxCpltCallback()
        (++) HAL_IRDA_ErrorCallback()

    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (+) HAL_IRDA_Abort()
        (+) HAL_IRDA_AbortTransmit()
        (+) HAL_IRDA_AbortReceive()
        (+) HAL_IRDA_Abort_IT()
        (+) HAL_IRDA_AbortTransmit_IT()
        (+) HAL_IRDA_AbortReceive_IT()

    (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
        (+) HAL_IRDA_AbortCpltCallback()
        (+) HAL_IRDA_AbortTransmitCpltCallback()
        (+) HAL_IRDA_AbortReceiveCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
           and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
           If user wants to abort it, Abort services should be called by user.
       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
           Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.

Function Documentation

HAL_StatusTypeDef HAL_IRDA_Abort ( IRDA_HandleTypeDef * hirda )

Abort ongoing transfers (blocking mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 959 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_Abort_IT ( IRDA_HandleTypeDef * hirda )

Abort ongoing transfers (Interrupt mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1119 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_IRDA_AbortCpltCallback(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_IRDA_AbortCpltCallback ( IRDA_HandleTypeDef * hirda )

IRDA Abort Complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1597 of file stm32h7xx_hal_irda.c.

Referenced by HAL_IRDA_Abort_IT(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

HAL_StatusTypeDef HAL_IRDA_AbortReceive ( IRDA_HandleTypeDef * hirda )

Abort ongoing Receive transfer (blocking mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1070 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, HAL_DMA_Abort(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT ( IRDA_HandleTypeDef * hirda )

Abort ongoing Receive transfer (Interrupt mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1311 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, HAL_DMA_Abort_IT(), HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_DMARxOnlyAbortCallback(), IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_IRDA_AbortReceiveCpltCallback ( IRDA_HandleTypeDef * hirda )

IRDA Abort Receive Complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1629 of file stm32h7xx_hal_irda.c.

Referenced by HAL_IRDA_AbortReceive_IT(), and IRDA_DMARxOnlyAbortCallback().

HAL_StatusTypeDef HAL_IRDA_AbortTransmit ( IRDA_HandleTypeDef * hirda )

Abort ongoing Transmit transfer (blocking mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1027 of file stm32h7xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT ( IRDA_HandleTypeDef * hirda )

Abort ongoing Transmit transfer (Interrupt mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1245 of file stm32h7xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, IRDA_DMATxOnlyAbortCallback(), IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_IRDA_AbortTransmitCpltCallback ( IRDA_HandleTypeDef * hirda )

IRDA Abort Complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1613 of file stm32h7xx_hal_irda.c.

Referenced by HAL_IRDA_AbortTransmit_IT(), and IRDA_DMATxOnlyAbortCallback().

HAL_StatusTypeDef HAL_IRDA_DMAPause ( IRDA_HandleTypeDef * hirda )

Pause the DMA Transfer.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 835 of file stm32h7xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_DMAResume ( IRDA_HandleTypeDef * hirda )

Resume the DMA Transfer.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 869 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_OREFLAG, IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_DMAStop ( IRDA_HandleTypeDef * hirda )

Stop the DMA Transfer.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 904 of file stm32h7xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, IRDA_EndRxTransfer(), IRDA_EndTxTransfer(), and IRDA_HandleTypeDef::RxState.

void HAL_IRDA_ErrorCallback ( IRDA_HandleTypeDef * hirda )

IRDA error callback.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1581 of file stm32h7xx_hal_irda.c.

Referenced by HAL_IRDA_IRQHandler(), IRDA_DMAAbortOnError(), and IRDA_DMAError().

void HAL_IRDA_IRQHandler ( IRDA_HandleTypeDef * hirda )

Handle IRDA interrupt request.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1375 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_IT, IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_IRDA_ERROR_FE, HAL_IRDA_ERROR_NE, HAL_IRDA_ERROR_NONE, HAL_IRDA_ERROR_ORE, HAL_IRDA_ERROR_PE, HAL_IRDA_ErrorCallback(), IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_DMAAbortOnError(), IRDA_EndRxTransfer(), IRDA_EndTransmit_IT(), IRDA_Receive_IT(), IRDA_Transmit_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_Receive | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer.
Size,: Amount of data to be received.
Timeout,: Specify timeout value.
Return values:
HAL status

Definition at line 537 of file stm32h7xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_FLAG_RXNE, IRDA_MASK_COMPUTATION, IRDA_PARITY_NONE, IRDA_WaitOnFlagUntilTimeout(), IRDA_WORDLENGTH_9B, IRDA_HandleTypeDef::Mask, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, IRDA_HandleTypeDef::RxXferSize, and IRDA_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_IRDA_Receive_DMA | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer.
Size,: Amount of data to be received.
Note:
When the IRDA parity is enabled (PCE = 1) the received data contains the parity bit (MSB position).
Return values:
HAL status

Definition at line 772 of file stm32h7xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::Instance, IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMAReceiveHalfCplt(), IRDA_HandleTypeDef::pRxBuffPtr, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_Receive_IT | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer.
Size,: Amount of data to be received.
Return values:
HAL status

Definition at line 658 of file stm32h7xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Instance, IRDA_MASK_COMPUTATION, IRDA_HandleTypeDef::pRxBuffPtr, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, and IRDA_HandleTypeDef::RxXferSize.

void HAL_IRDA_RxCpltCallback ( IRDA_HandleTypeDef * hirda )

Rx Transfer completed callback.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1549 of file stm32h7xx_hal_irda.c.

Referenced by IRDA_DMAReceiveCplt(), and IRDA_Receive_IT().

void HAL_IRDA_RxHalfCpltCallback ( IRDA_HandleTypeDef * hirda )

Rx Half Transfer complete callback.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1565 of file stm32h7xx_hal_irda.c.

Referenced by IRDA_DMAReceiveHalfCplt().

HAL_StatusTypeDef HAL_IRDA_Transmit | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer.
Size,: Amount of data to be sent.
Timeout,: Specify timeout value.
Return values:
HAL status

Definition at line 464 of file stm32h7xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_FLAG_TC, IRDA_FLAG_TXE, IRDA_PARITY_NONE, IRDA_WaitOnFlagUntilTimeout(), IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::TxXferCount, IRDA_HandleTypeDef::TxXferSize, and IRDA_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_IRDA_Transmit_DMA | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: pointer to data buffer.
Size,: amount of data to be sent.
Return values:
HAL status

Definition at line 708 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, IRDA_CLEAR_TCF, IRDA_DMAError(), IRDA_DMATransmitCplt(), IRDA_DMATransmitHalfCplt(), IRDA_HandleTypeDef::pTxBuffPtr, IRDA_HandleTypeDef::TxXferCount, IRDA_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_Transmit_IT | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer.
Size,: Amount of data to be sent.
Return values:
HAL status

Definition at line 612 of file stm32h7xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Instance, IRDA_HandleTypeDef::pTxBuffPtr, IRDA_HandleTypeDef::TxXferCount, and IRDA_HandleTypeDef::TxXferSize.

void HAL_IRDA_TxCpltCallback ( IRDA_HandleTypeDef * hirda )

Tx Transfer completed callback.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1517 of file stm32h7xx_hal_irda.c.

Referenced by IRDA_DMATransmitCplt(), and IRDA_EndTransmit_IT().

void HAL_IRDA_TxHalfCpltCallback ( IRDA_HandleTypeDef * hirda )

Tx Half Transfer completed callback.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 1533 of file stm32h7xx_hal_irda.c.

Referenced by IRDA_DMATransmitHalfCplt().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
IRDA Exported Functions

IRDA State and Errors functions. More...

Functions

HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Return the IRDA handle state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IRDA handle error code.

Detailed Description

IRDA State and Errors functions.

  ==============================================================================
                  ##### Peripheral State and Error functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to return the State of IrDA
    communication process and also return Peripheral Errors occurred during communication process
     (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
         of the IRDA peripheral handle.
     (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
         communication.

Function Documentation

uint32_t HAL_IRDA_GetError ( IRDA_HandleTypeDef * hirda )

Return the IRDA handle error code.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
IRDA Error Code

Definition at line 1684 of file stm32h7xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode.

HAL_IRDA_StateTypeDef HAL_IRDA_GetState ( IRDA_HandleTypeDef * hirda )

Return the IRDA handle state.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL state

Definition at line 1668 of file stm32h7xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, and IRDA_HandleTypeDef::RxState.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDA Private Functions

Functions
IRDA Private Functions
IRDA

Functions

static HAL_StatusTypeDef | IRDA_SetConfig (IRDA_HandleTypeDef *hirda)
Configure the IRDA peripheral.
static HAL_StatusTypeDef | IRDA_CheckIdleState (IRDA_HandleTypeDef *hirda)
Check the IRDA Idle State.
static HAL_StatusTypeDef | IRDA_WaitOnFlagUntilTimeout (IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle IRDA Communication Timeout.
static void | IRDA_EndTxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
static void | IRDA_EndRxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).
static void | IRDA_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process complete callback.
static void | IRDA_DMATransmitHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process complete callback.
static void | IRDA_DMAReceiveHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAError (DMA_HandleTypeDef *hdma)
DMA IRDA communication error callback.
static void | IRDA_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA IRDA communication abort callback (To be called at end of DMA Abort procedure).
static void | IRDA_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | IRDA_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | IRDA_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | IRDA_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static HAL_StatusTypeDef | IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda)
Send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | IRDA_EndTransmit_IT (IRDA_HandleTypeDef *hirda)
Wrap up transmission in non-blocking mode.
static HAL_StatusTypeDef | IRDA_Receive_IT (IRDA_HandleTypeDef *hirda)
Receive an amount of data in non-blocking mode.

Function Documentation

static HAL_StatusTypeDef IRDA_CheckIdleState ( IRDA_HandleTypeDef * hirda ) [static]

Check the IRDA Idle State.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 1780 of file stm32h7xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Instance, IRDA_TEACK_REACK_TIMEOUT, IRDA_WaitOnFlagUntilTimeout(), and IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_Init().

static void IRDA_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA communication abort callback (To be called at end of DMA Abort procedure).

Parameters:
hdma,: DMA handle.
Return values:
None

Definition at line 2008 of file stm32h7xx_hal_irda.c.

References HAL_IRDA_ErrorCallback(), IRDA_HandleTypeDef::RxXferCount, and IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_IRQHandler().

static void IRDA_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA communication error callback.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1976 of file stm32h7xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_DMA, HAL_IRDA_ErrorCallback(), HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, IRDA_HandleTypeDef::Instance, IRDA_EndRxTransfer(), IRDA_EndTxTransfer(), IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, and IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_Receive_DMA(), and HAL_IRDA_Transmit_DMA().

static void IRDA_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process complete callback.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1933 of file stm32h7xx_hal_irda.c.

References DMA_CIRCULAR, HAL_IRDA_RxCpltCallback(), HAL_IRDA_STATE_READY, __DMA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, IRDA_HandleTypeDef::RxState, and IRDA_HandleTypeDef::RxXferCount.

Referenced by HAL_IRDA_Receive_DMA().

static void IRDA_DMAReceiveHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process half complete callback.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1963 of file stm32h7xx_hal_irda.c.

References HAL_IRDA_RxHalfCpltCallback().

Referenced by HAL_IRDA_Receive_DMA().

static void IRDA_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2067 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::hdmatx, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_IRDA_Abort_IT().

static void IRDA_DMARxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Rx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2130 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_STATE_READY, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_HandleTypeDef::RxState, and IRDA_HandleTypeDef::RxXferCount.

Referenced by HAL_IRDA_AbortReceive_IT().

static void IRDA_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA transmit process complete callback.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1891 of file stm32h7xx_hal_irda.c.

References DMA_CIRCULAR, HAL_IRDA_TxCpltCallback(), __DMA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, and IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_Transmit_DMA().

static void IRDA_DMATransmitHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process half complete callback.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1920 of file stm32h7xx_hal_irda.c.

References HAL_IRDA_TxHalfCpltCallback().

Referenced by HAL_IRDA_Transmit_DMA().

static void IRDA_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2025 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::hdmatx, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_IRDA_Abort_IT().

static void IRDA_DMATxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Tx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2109 of file stm32h7xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_STATE_READY, and IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_AbortTransmit_IT().

static void IRDA_EndRxTransfer ( IRDA_HandleTypeDef * hirda ) [static]

End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).

Parameters:
hirda,: IRDA handle.
Return values:
None

Definition at line 1875 of file stm32h7xx_hal_irda.c.

References HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_DMAStop(), HAL_IRDA_IRQHandler(), and IRDA_DMAError().

static HAL_StatusTypeDef IRDA_EndTransmit_IT ( IRDA_HandleTypeDef * hirda ) [static]

Wrap up transmission in non-blocking mode.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 2200 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_DISABLE_IT, IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_READY, HAL_IRDA_TxCpltCallback(), IRDA_HandleTypeDef::Instance, and IRDA_IT_ERR.

Referenced by HAL_IRDA_IRQHandler().

static void IRDA_EndTxTransfer ( IRDA_HandleTypeDef * hirda ) [static]

End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).

Parameters:
hirda,: IRDA handle.
Return values:
None

Definition at line 1861 of file stm32h7xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_READY, and IRDA_HandleTypeDef::Instance.

Referenced by HAL_IRDA_DMAStop(), and IRDA_DMAError().

static HAL_StatusTypeDef IRDA_Receive_IT ( IRDA_HandleTypeDef * hirda ) [static]

Receive an amount of data in non-blocking mode.

Function is called under interruption only, once interruptions have been enabled by HAL_IRDA_Receive_IT().

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 2225 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_SEND_REQ, HAL_IRDA_RxCpltCallback(), HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_PARITY_NONE, IRDA_RXDATA_FLUSH_REQUEST, IRDA_WORDLENGTH_9B, IRDA_HandleTypeDef::Mask, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::pRxBuffPtr, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_IRQHandler().

static HAL_StatusTypeDef IRDA_SetConfig ( IRDA_HandleTypeDef * hirda ) [static]

Configure the IRDA peripheral.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1707 of file stm32h7xx_hal_irda.c.

References assert_param, IRDA_InitTypeDef::BaudRate, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPLL2ClockFreq(), HAL_RCCEx_GetPLL3ClockFreq(), HSI_VALUE, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_CLOCKSOURCE_CSI, IRDA_CLOCKSOURCE_D2PCLK1, IRDA_CLOCKSOURCE_D2PCLK2, IRDA_CLOCKSOURCE_HSI, IRDA_CLOCKSOURCE_LSE, IRDA_CLOCKSOURCE_PLL2Q, IRDA_CLOCKSOURCE_PLL3Q, IRDA_CLOCKSOURCE_UNDEFINED, IRDA_CR1_FIELDS, IRDA_GETCLOCKSOURCE, IS_IRDA_BAUDRATE, IS_IRDA_PARITY, IS_IRDA_POWERMODE, IS_IRDA_PRESCALER, IS_IRDA_TX_RX_MODE, IS_IRDA_WORD_LENGTH, LSE_VALUE, IRDA_InitTypeDef::Mode, IRDA_InitTypeDef::Parity, PLL2_ClocksTypeDef::PLL2_Q_Frequency, PLL3_ClocksTypeDef::PLL3_Q_Frequency, IRDA_InitTypeDef::PowerMode, IRDA_InitTypeDef::Prescaler, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_Init().

static HAL_StatusTypeDef IRDA_Transmit_IT ( IRDA_HandleTypeDef * hirda ) [static]

Send an amount of data in non-blocking mode.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_IRDA_Transmit_IT().
Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 2154 of file stm32h7xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_TX, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_PARITY_NONE, IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::pTxBuffPtr, IRDA_HandleTypeDef::TxXferCount, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_IRQHandler().

static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle IRDA Communication Timeout.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Flag,: specifies the IRDA flag to check.
Status,: the new flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status.
Tickstart,: tick start value.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 1830 of file stm32h7xx_hal_irda.c.

References __HAL_IRDA_GET_FLAG, IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), and IRDA_CheckIdleState().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDA Exported Types

Data Structures | Enumerations
IRDA Exported Types
IRDA

Data Structures

struct | IRDA_InitTypeDef
IRDA Init Structure definition. More...
struct | IRDA_HandleTypeDef
IRDA handle Structure definition. More...

Enumerations

enum HAL_IRDA_StateTypeDef {
HAL_IRDA_STATE_RESET = 0x00U, HAL_IRDA_STATE_READY = 0x20U, HAL_IRDA_STATE_BUSY = 0x24U, HAL_IRDA_STATE_BUSY_TX = 0x21U,
HAL_IRDA_STATE_BUSY_RX = 0x22U, HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, HAL_IRDA_STATE_TIMEOUT = 0xA0U, HAL_IRDA_STATE_ERROR = 0xE0U
}
HAL IRDA State structures definition. More...
enum HAL_IRDA_ErrorTypeDef {
HAL_IRDA_ERROR_NONE = 0x00, HAL_IRDA_ERROR_PE = 0x01, HAL_IRDA_ERROR_NE = 0x02, HAL_IRDA_ERROR_FE = 0x04,
HAL_IRDA_ERROR_ORE = 0x08, HAL_IRDA_ERROR_DMA = 0x10, HAL_IRDA_ERROR_BUSY = 0x20
}
HAL IRDA Error Code structure definition. More...
enum IRDA_ClockSourceTypeDef {
IRDA_CLOCKSOURCE_D2PCLK1 = 0x00, IRDA_CLOCKSOURCE_D2PCLK2 = 0x01, IRDA_CLOCKSOURCE_D3PCLK1 = 0x02, IRDA_CLOCKSOURCE_PLL2Q = 0x04,
IRDA_CLOCKSOURCE_HSI = 0x08, IRDA_CLOCKSOURCE_CSI = 0x10, IRDA_CLOCKSOURCE_LSE = 0x20, IRDA_CLOCKSOURCE_PLL3Q = 0x40,
IRDA_CLOCKSOURCE_UNDEFINED = 0x80
}
IRDA clock sources definition. More...
enum IRDA_ControlTypeDef {
IRDA_BAUDRATE = 0x00, IRDA_PARITY = 0x01, IRDA_WORDLENGTH = 0x02, IRDA_MODE = 0x03,
IRDA_PRESCALER = 0x04, IRDA_POWERMODE = 0x05
}
IRDA Configuration enumeration values definition. More...

Enumeration Type Documentation

enum HAL_IRDA_ErrorTypeDef

HAL IRDA Error Code structure definition.

Enumerator:
HAL_IRDA_ERROR_NONE

No error

HAL_IRDA_ERROR_PE

Parity error

HAL_IRDA_ERROR_NE

Noise error

HAL_IRDA_ERROR_FE

frame error

HAL_IRDA_ERROR_ORE

Overrun error

HAL_IRDA_ERROR_DMA

DMA transfer error

HAL_IRDA_ERROR_BUSY

Busy Error

Definition at line 155 of file stm32h7xx_hal_irda.h.

enum HAL_IRDA_StateTypeDef

HAL IRDA State structures definition.

Note:
HAL IRDA State value is a combination of 2 different substates: gState and RxState.
  • gState contains IRDA state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized. HAL IRDA Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (IP busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.
Enumerator:
HAL_IRDA_STATE_RESET

Peripheral is not initialized Value is allowed for gState and RxState

HAL_IRDA_STATE_READY

Peripheral Initialized and ready for use Value is allowed for gState and RxState

HAL_IRDA_STATE_BUSY

an internal process is ongoing Value is allowed for gState only

HAL_IRDA_STATE_BUSY_TX

Data Transmission process is ongoing Value is allowed for gState only

HAL_IRDA_STATE_BUSY_RX

Data Reception process is ongoing Value is allowed for RxState only

HAL_IRDA_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

HAL_IRDA_STATE_TIMEOUT

Timeout state Value is allowed for gState only

HAL_IRDA_STATE_ERROR

Error Value is allowed for gState only

Definition at line 131 of file stm32h7xx_hal_irda.h.

enum IRDA_ClockSourceTypeDef

IRDA clock sources definition.

Enumerator:
IRDA_CLOCKSOURCE_D2PCLK1

Domain2 PCLK1 clock source

IRDA_CLOCKSOURCE_D2PCLK2

Domain2 PCLK2 clock source

IRDA_CLOCKSOURCE_D3PCLK1

Domain3 PCLK1 clock source

IRDA_CLOCKSOURCE_PLL2Q

PLL2Q clock source

IRDA_CLOCKSOURCE_HSI

HSI clock source

IRDA_CLOCKSOURCE_CSI

CSI clock source

IRDA_CLOCKSOURCE_LSE

LSE clock source

IRDA_CLOCKSOURCE_PLL3Q

PCLK2 clock source

IRDA_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 169 of file stm32h7xx_hal_irda.h.

enum IRDA_ControlTypeDef

IRDA Configuration enumeration values definition.

Enumerator:
IRDA_BAUDRATE

IRDA Baud rate

IRDA_PARITY

IRDA frame parity

IRDA_WORDLENGTH

IRDA frame length

IRDA_MODE

IRDA communication mode

IRDA_PRESCALER

IRDA prescaling

IRDA_POWERMODE

IRDA power mode

Definition at line 225 of file stm32h7xx_hal_irda.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IRDA_InitTypeDef Struct Reference
IRDA Exported Types

IRDA Init Structure definition. More...

#include <stm32h7xx_hal_irda.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | Parity
uint32_t | Mode
uint8_t | Prescaler
uint16_t | PowerMode

Detailed Description

IRDA Init Structure definition.

Definition at line 65 of file stm32h7xx_hal_irda.h.

Field Documentation

uint32_t IRDA_InitTypeDef::BaudRate

This member configures the IRDA communication baud rate. The baud rate register is computed using the following formula: Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate)))

Definition at line 67 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of IRDA Transfer Mode

Definition at line 81 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of IRDA Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 74 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

uint16_t IRDA_InitTypeDef::PowerMode

Specifies the IRDA power mode. This parameter can be a value of IRDA Low Power

Definition at line 88 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint8_t IRDA_InitTypeDef::Prescaler

Specifies the Prescaler value for dividing the UART/USART source clock to achieve low-power frequency.

Note:
Prescaler value 0 is forbidden

Definition at line 84 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of IRDA Word Length

Definition at line 71 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_irda.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IRDA_HandleTypeDef Struct Reference
IRDA Exported Types

IRDA handle Structure definition. More...

#include <stm32h7xx_hal_irda.h>

Data Fields

USART_TypeDef * | Instance
IRDA_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | Mask
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_IRDA_StateTypeDef | gState
__IO HAL_IRDA_StateTypeDef | RxState
uint32_t | ErrorCode

Detailed Description

IRDA handle Structure definition.

Definition at line 185 of file stm32h7xx_hal_irda.h.

Field Documentation

uint32_t IRDA_HandleTypeDef::ErrorCode

IRDA Error code

Definition at line 218 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_DeInit(), HAL_IRDA_GetError(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

__IO HAL_IRDA_StateTypeDef IRDA_HandleTypeDef::gState

IRDA state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_IRDA_StateTypeDef

Definition at line 211 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_GetState(), HAL_IRDA_Init(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), IRDA_EndTransmit_IT(), IRDA_EndTxTransfer(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* IRDA_HandleTypeDef::hdmarx

IRDA Rx DMA Handle parameters

Definition at line 207 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_DMAStop(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_DMA(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

DMA_HandleTypeDef* IRDA_HandleTypeDef::hdmatx

IRDA Tx DMA Handle parameters

Definition at line 205 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_DMAStop(), HAL_IRDA_Transmit_DMA(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

IRDA_InitTypeDef IRDA_HandleTypeDef::Init

IRDA communication parameters

Definition at line 189 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

USART_TypeDef* IRDA_HandleTypeDef::Instance

IRDA registers base address

Definition at line 187 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_Init(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), IRDA_EndRxTransfer(), IRDA_EndTransmit_IT(), IRDA_EndTxTransfer(), IRDA_Receive_IT(), IRDA_SetConfig(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

HAL_LockTypeDef IRDA_HandleTypeDef::Lock

Locking object

Definition at line 209 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

uint16_t IRDA_HandleTypeDef::Mask

IRDA RX RDR register mask

Definition at line 203 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), and IRDA_Receive_IT().

uint8_t* IRDA_HandleTypeDef::pRxBuffPtr

Pointer to IRDA Rx transfer Buffer

Definition at line 197 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), and IRDA_Receive_IT().

uint8_t* IRDA_HandleTypeDef::pTxBuffPtr

Pointer to IRDA Tx transfer Buffer

Definition at line 191 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), and IRDA_Transmit_IT().

__IO HAL_IRDA_StateTypeDef IRDA_HandleTypeDef::RxState

IRDA state information related to Rx operations. This parameter can be a value of HAL_IRDA_StateTypeDef

Definition at line 215 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_GetState(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), IRDA_DMATxAbortCallback(), IRDA_EndRxTransfer(), IRDA_Receive_IT(), and IRDA_WaitOnFlagUntilTimeout().

__IO uint16_t IRDA_HandleTypeDef::RxXferCount

IRDA Rx Transfer Counter

Definition at line 201 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_Receive(), HAL_IRDA_Receive_IT(), IRDA_DMAAbortOnError(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), IRDA_DMATxAbortCallback(), and IRDA_Receive_IT().

uint16_t IRDA_HandleTypeDef::RxXferSize

IRDA Rx Transfer size

Definition at line 199 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), and HAL_IRDA_Receive_IT().

__IO uint16_t IRDA_HandleTypeDef::TxXferCount

IRDA Tx Transfer Counter

Definition at line 195 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_DMAAbortOnError(), IRDA_DMAError(), IRDA_DMARxAbortCallback(), IRDA_DMATransmitCplt(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), and IRDA_Transmit_IT().

uint16_t IRDA_HandleTypeDef::TxXferSize

IRDA Tx Transfer size

Definition at line 193 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), and HAL_IRDA_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_irda.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDA Word Length

Defines
IRDA Word Length
IRDA Exported Constants

Defines

#define | IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define | IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
#define | IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

Define Documentation

#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)

7-bit long frame

Definition at line 247 of file stm32h7xx_hal_irda.h.

#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)

8-bit long frame

Definition at line 248 of file stm32h7xx_hal_irda.h.

#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

9-bit long frame

Definition at line 249 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), and IRDA_Transmit_IT().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDA Parity

Defines
IRDA Parity
IRDA Exported Constants

Defines

#define | IRDA_PARITY_NONE ((uint32_t)0x00000000)
#define | IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

Even parity

Definition at line 258 of file stm32h7xx_hal_irda.h.

#define IRDA_PARITY_NONE ((uint32_t)0x00000000)

No parity

Definition at line 257 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), and IRDA_Transmit_IT().

#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Odd parity

Definition at line 259 of file stm32h7xx_hal_irda.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDA Transfer Mode

Defines
IRDA Transfer Mode
IRDA Exported Constants

Defines

#define | IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
#define | IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
#define | IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)

RX mode

Definition at line 267 of file stm32h7xx_hal_irda.h.

#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)

TX mode

Definition at line 268 of file stm32h7xx_hal_irda.h.

#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

RX and TX mode

Definition at line 269 of file stm32h7xx_hal_irda.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDA Low Power

Defines
IRDA Low Power
IRDA Exported Constants

Defines

#define | IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000)
#define | IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)

Define Documentation

#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)

IRDA low power mode

Definition at line 278 of file stm32h7xx_hal_irda.h.

#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000)

IRDA normal power mode

Definition at line 277 of file stm32h7xx_hal_irda.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDA State

Defines
IRDA State
IRDA Exported Constants

Defines

#define | IRDA_STATE_DISABLE ((uint32_t)0x00000000)
#define | IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE)

Define Documentation

#define IRDA_STATE_DISABLE ((uint32_t)0x00000000)

IRDA disabled

Definition at line 286 of file stm32h7xx_hal_irda.h.

#define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE)

IRDA enabled

Definition at line 287 of file stm32h7xx_hal_irda.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDA Mode

Defines
IRDA Mode
IRDA Exported Constants

Defines

#define | IRDA_MODE_DISABLE ((uint32_t)0x00000000)
#define | IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN)

Define Documentation

#define IRDA_MODE_DISABLE ((uint32_t)0x00000000)

Associated UART disabled in IRDA mode

Definition at line 295 of file stm32h7xx_hal_irda.h.

#define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN)

Associated UART enabled in IRDA mode

Definition at line 296 of file stm32h7xx_hal_irda.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDA One Bit Sampling

Defines
IRDA One Bit Sampling
IRDA Exported Constants

Defines

#define | IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)
#define | IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

Define Documentation

#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)

One-bit sampling disabled

Definition at line 304 of file stm32h7xx_hal_irda.h.

#define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

One-bit sampling enabled

Definition at line 305 of file stm32h7xx_hal_irda.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDA DMA Tx

Defines
IRDA DMA Tx
IRDA Exported Constants

Defines

#define | IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000)
#define | IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)

Define Documentation

#define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000)

IRDA DMA TX disabled

Definition at line 313 of file stm32h7xx_hal_irda.h.

#define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)

IRDA DMA TX enabled

Definition at line 314 of file stm32h7xx_hal_irda.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDA DMA Rx

Defines
IRDA DMA Rx
IRDA Exported Constants

Defines

#define | IRDA_DMA_RX_DISABLE ((uint32_t)0x00000000)
#define | IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)

Define Documentation

#define IRDA_DMA_RX_DISABLE ((uint32_t)0x00000000)

IRDA DMA RX disabled

Definition at line 322 of file stm32h7xx_hal_irda.h.

#define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)

IRDA DMA RX enabled

Definition at line 323 of file stm32h7xx_hal_irda.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDA Request Parameters

Defines
IRDA Request Parameters
IRDA Exported Constants

Defines

#define | IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ)
#define | IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ)
#define | IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ)

Define Documentation

#define IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ)

Auto-Baud Rate Request

Definition at line 331 of file stm32h7xx_hal_irda.h.

#define IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ)

Receive Data flush Request

Definition at line 332 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_Receive_IT().

#define IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ)

Transmit data flush Request

Definition at line 333 of file stm32h7xx_hal_irda.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDA Flags

Defines
IRDA Flags
IRDA Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | IRDA_FLAG_REACK ((uint32_t)0x00400000)
#define | IRDA_FLAG_TEACK ((uint32_t)0x00200000)
#define | IRDA_FLAG_BUSY ((uint32_t)0x00010000)
#define | IRDA_FLAG_ABRF ((uint32_t)0x00008000)
#define | IRDA_FLAG_ABRE ((uint32_t)0x00004000)
#define | IRDA_FLAG_TXE ((uint32_t)0x00000080)
#define | IRDA_FLAG_TC ((uint32_t)0x00000040)
#define | IRDA_FLAG_RXNE ((uint32_t)0x00000020)
#define | IRDA_FLAG_ORE ((uint32_t)0x00000008)
#define | IRDA_FLAG_NE ((uint32_t)0x00000004)
#define | IRDA_FLAG_FE ((uint32_t)0x00000002)
#define | IRDA_FLAG_PE ((uint32_t)0x00000001)

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define IRDA_FLAG_ABRE ((uint32_t)0x00004000)

IRDA Auto baud rate error

Definition at line 347 of file stm32h7xx_hal_irda.h.

#define IRDA_FLAG_ABRF ((uint32_t)0x00008000)

IRDA Auto baud rate flag

Definition at line 346 of file stm32h7xx_hal_irda.h.

#define IRDA_FLAG_BUSY ((uint32_t)0x00010000)

IRDA Busy flag

Definition at line 345 of file stm32h7xx_hal_irda.h.

#define IRDA_FLAG_FE ((uint32_t)0x00000002)

IRDA Framing error

Definition at line 353 of file stm32h7xx_hal_irda.h.

#define IRDA_FLAG_NE ((uint32_t)0x00000004)

IRDA Noise error

Definition at line 352 of file stm32h7xx_hal_irda.h.

#define IRDA_FLAG_ORE ((uint32_t)0x00000008)

IRDA Overrun error

Definition at line 351 of file stm32h7xx_hal_irda.h.

#define IRDA_FLAG_PE ((uint32_t)0x00000001)

IRDA Parity error

Definition at line 354 of file stm32h7xx_hal_irda.h.

#define IRDA_FLAG_REACK ((uint32_t)0x00400000)

IRDA Receive enable acknowledge flag

Definition at line 343 of file stm32h7xx_hal_irda.h.

#define IRDA_FLAG_RXNE ((uint32_t)0x00000020)

IRDA Read data register not empty

Definition at line 350 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive().

#define IRDA_FLAG_TC ((uint32_t)0x00000040)

IRDA Transmission complete

Definition at line 349 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit().

#define IRDA_FLAG_TEACK ((uint32_t)0x00200000)

IRDA Transmit enable acknowledge flag

Definition at line 344 of file stm32h7xx_hal_irda.h.

#define IRDA_FLAG_TXE ((uint32_t)0x00000080)

IRDA Transmit data register empty

Definition at line 348 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDA Interrupts Definition

Defines
IRDA Interrupts Definition
IRDA Exported Constants

Elements values convention: 0000ZZZZ0XXYYYYYb. More...

Defines

#define | IRDA_IT_PE ((uint16_t)0x0028)
#define | IRDA_IT_TXE ((uint16_t)0x0727)
#define | IRDA_IT_TC ((uint16_t)0x0626)
#define | IRDA_IT_RXNE ((uint16_t)0x0525)
#define | IRDA_IT_IDLE ((uint16_t)0x0424)
#define | IRDA_IT_ERR ((uint16_t)0x0060)
#define | IRDA_IT_ORE ((uint16_t)0x0300)
#define | IRDA_IT_NE ((uint16_t)0x0200)
#define | IRDA_IT_FE ((uint16_t)0x0100)

Detailed Description

Elements values convention: 0000ZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define IRDA_IT_ERR ((uint16_t)0x0060)

IRDA Error interruption

Definition at line 374 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_EndTransmit_IT().

#define IRDA_IT_FE ((uint16_t)0x0100)

IRDA Frame error interruption

Definition at line 377 of file stm32h7xx_hal_irda.h.

#define IRDA_IT_IDLE ((uint16_t)0x0424)

IRDA Idle interruption

Definition at line 373 of file stm32h7xx_hal_irda.h.

#define IRDA_IT_NE ((uint16_t)0x0200)

IRDA Noise error interruption

Definition at line 376 of file stm32h7xx_hal_irda.h.

#define IRDA_IT_ORE ((uint16_t)0x0300)

IRDA Overrun error interruption

Definition at line 375 of file stm32h7xx_hal_irda.h.

#define IRDA_IT_PE ((uint16_t)0x0028)

IRDA Parity error interruption

Definition at line 369 of file stm32h7xx_hal_irda.h.

#define IRDA_IT_RXNE ((uint16_t)0x0525)

IRDA Read data register not empty interruption

Definition at line 372 of file stm32h7xx_hal_irda.h.

#define IRDA_IT_TC ((uint16_t)0x0626)

IRDA Transmission complete interruption

Definition at line 371 of file stm32h7xx_hal_irda.h.

#define IRDA_IT_TXE ((uint16_t)0x0727)

IRDA Transmit data register empty interruption

Definition at line 370 of file stm32h7xx_hal_irda.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDA Interruption Clear Flags

Defines
IRDA Interruption Clear Flags
IRDA Exported Constants

Defines

#define | IRDA_CLEAR_PEF USART_ICR_PECF
#define | IRDA_CLEAR_FEF USART_ICR_FECF
#define | IRDA_CLEAR_NEF USART_ICR_NCF
#define | IRDA_CLEAR_OREF USART_ICR_ORECF
#define | IRDA_CLEAR_IDLEF USART_ICR_IDLECF
#define | IRDA_CLEAR_TCF USART_ICR_TCCF

Define Documentation

#define IRDA_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 386 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 389 of file stm32h7xx_hal_irda.h.

#define IRDA_CLEAR_NEF USART_ICR_NCF

Noise detected Clear Flag

Definition at line 387 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_OREF USART_ICR_ORECF

OverRun Error Clear Flag

Definition at line 388 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 385 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 390 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit_DMA().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDA interruptions flags mask

Defines
IRDA interruptions flags mask
IRDA Exported Constants

Defines

#define IRDA_IT_MASK ((uint16_t)0x001F)

Define Documentation

#define IRDA_IT_MASK ((uint16_t)0x001F)

IRDA Interruptions flags mask

Definition at line 398 of file stm32h7xx_hal_irda.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDA Exported Macros

Defines
IRDA Exported Macros
IRDA

Defines

#define | __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)
Reset IRDA handle state.
#define | __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)
Flush the IRDA DR register.
#define | __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified IRDA pending flag.
#define | __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
Clear the IRDA PE pending flag.
#define | __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
Clear the IRDA FE pending flag.
#define | __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
Clear the IRDA NE pending flag.
#define | __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
Clear the IRDA ORE pending flag.
#define | __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
Clear the IRDA IDLE pending flag.
#define | __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified IRDA flag is set or not.
#define | __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified IRDA interrupt.
#define | __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified IRDA interrupt.
#define | __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08)))
Check whether the specified IRDA interrupt has occurred or not.
#define | __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified IRDA interrupt source is enabled or not.
#define | __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
#define | __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific IRDA request flag.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the IRDA one bit sample method.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the IRDA one bit sample method.
#define | __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART/USART associated to IRDA Handle.
#define | __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART/USART associated to IRDA Handle.

Define Documentation

#define __HAL_IRDA_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)

Clear the IRDA FE pending flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 457 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified IRDA pending flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
__FLAG__,: specifies the flag to check. This parameter can be any combination of the following values:
  • IRDA_CLEAR_PEF
  • IRDA_CLEAR_FEF
  • IRDA_CLEAR_NEF
  • IRDA_CLEAR_OREF
  • IRDA_CLEAR_TCF
  • IRDA_CLEAR_IDLEF
Return values:
None

Definition at line 444 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_Transmit_DMA(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define __HAL_IRDA_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)

Clear the IRDA IDLE pending flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 475 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified IRDA ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
__IT_CLEAR__,: specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt This parameter can be one of the following values:
  • IRDA_CLEAR_PEF Parity Error Clear Flag
  • IRDA_CLEAR_FEF Framing Error Clear Flag
  • IRDA_CLEAR_NEF Noise detected Clear Flag
  • IRDA_CLEAR_OREF OverRun Error Clear Flag
  • IRDA_CLEAR_TCF Transmission Complete Clear Flag
Return values:
None

Definition at line 575 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define __HAL_IRDA_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)

Clear the IRDA NE pending flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 463 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)

Clear the IRDA ORE pending flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 469 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_DMAResume().

#define __HAL_IRDA_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)

Clear the IRDA PE pending flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 450 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable UART/USART associated to IRDA Handle.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 612 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), and HAL_IRDA_Init().

#define __HAL_IRDA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))

Disable the specified IRDA interrupt.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
__INTERRUPT__,: specifies the IRDA interrupt source to disable. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_PE Parity Error interrupt
  • IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 526 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_EndTransmit_IT().

#define __HAL_IRDA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable UART/USART associated to IRDA Handle.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 606 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

#define __HAL_IRDA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))

Enable the specified IRDA interrupt.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
__INTERRUPT__,: specifies the IRDA interrupt source to enable. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_PE Parity Error interrupt
  • IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 510 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                                                                    \
         SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
         SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
      } while(0)

Flush the IRDA DR register.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 426 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified IRDA flag is set or not.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • IRDA_FLAG_REACK Receive enable acknowledge flag
  • IRDA_FLAG_TEACK Transmit enable acknowledge flag
  • IRDA_FLAG_BUSY Busy flag
  • IRDA_FLAG_ABRF Auto Baud rate detection flag
  • IRDA_FLAG_ABRE Auto Baud rate detection error flag
  • IRDA_FLAG_TXE Transmit data register empty flag
  • IRDA_FLAG_TC Transmission Complete flag
  • IRDA_FLAG_RXNE Receive data register not empty flag
  • IRDA_FLAG_ORE OverRun Error flag
  • IRDA_FLAG_NE Noise Error flag
  • IRDA_FLAG_FE Framing Error flag
  • IRDA_FLAG_PE Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 495 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_WaitOnFlagUntilTimeout().

#define __HAL_IRDA_GET_IT | ( | __HANDLE__,
 |  | __IT__
 | ) | ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08)))

Check whether the specified IRDA interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
__IT__,: specifies the IRDA interrupt source to check. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_ORE OverRun Error interrupt
  • IRDA_IT_NE Noise Error interrupt
  • IRDA_IT_FE Framing Error interrupt
  • IRDA_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 545 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))

Check whether the specified IRDA interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
__IT__,: specifies the IRDA interrupt source to check. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_ERR Framing, overrun or noise error interrupt
  • IRDA_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 559 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

Disable the IRDA one bit sample method.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 600 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the IRDA one bit sample method.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 594 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
                                                     } while(0)

Reset IRDA handle state.

Parameters:
__HANDLE__,: IRDA handle.
Return values:
None

Definition at line 417 of file stm32h7xx_hal_irda.h.

#define __HAL_IRDA_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific IRDA request flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
__REQ__,: specifies the request flag to set This parameter can be one of the following values:
  • IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
  • IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
  • IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 588 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_Receive_IT().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDA Private Macros

Defines
IRDA Private Macros
IRDA

Defines

#define | IRDA_MASK_COMPUTATION(__HANDLE__)
Compute the mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
Ensure that IRDA Baud rate is less or equal to maximum value.
#define | IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
Ensure that IRDA prescaler value is strictly larger than 0.
#define | IS_IRDA_WORD_LENGTH(__LENGTH__)
Ensure that IRDA frame length is valid.
#define | IS_IRDA_PARITY(__PARITY__)
Ensure that IRDA frame parity is valid.
#define | IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
Ensure that IRDA communication mode is valid.
#define | IS_IRDA_POWERMODE(__MODE__)
Ensure that IRDA power mode is valid.
#define | IS_IRDA_STATE(__STATE__)
Ensure that IRDA state is valid.
#define | IS_IRDA_MODE(__MODE__)
Ensure that IRDA associated UART/USART mode is valid.
#define | IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that IRDA sampling rate is valid.
#define | IS_IRDA_DMA_TX(__DMATX__)
Ensure that IRDA DMA TX mode is valid.
#define | IS_IRDA_DMA_RX(__DMARX__)
Ensure that IRDA DMA RX mode is valid.
#define | IS_IRDA_REQUEST_PARAMETER(__PARAM__)
Ensure that IRDA request is valid.

Define Documentation

#define IRDA_MASK_COMPUTATION ( __HANDLE__ )

Compute the mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None,the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.

Definition at line 628 of file stm32h7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), and HAL_IRDA_Receive_IT().

#define IS_IRDA_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 115201)

Ensure that IRDA Baud rate is less or equal to maximum value.

Parameters:
__BAUDRATE__,: specifies the IRDA Baudrate set by the user.
Return values:
True or False

Definition at line 669 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_DMA_RX ( __DMARX__ )
Value:
(((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
                                   ((__DMARX__) == IRDA_DMA_RX_ENABLE))

Ensure that IRDA DMA RX mode is valid.

Parameters:
__DMARX__,: IRDA DMA RX mode.
Return values:
SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)

Definition at line 747 of file stm32h7xx_hal_irda.h.

#define IS_IRDA_DMA_TX ( __DMATX__ )
Value:
(((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
                                       ((__DMATX__) == IRDA_DMA_TX_ENABLE))

Ensure that IRDA DMA TX mode is valid.

Parameters:
__DMATX__,: IRDA DMA TX mode.
Return values:
SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)

Definition at line 739 of file stm32h7xx_hal_irda.h.

#define IS_IRDA_MODE ( __MODE__ )
Value:
(((__MODE__) == IRDA_MODE_DISABLE) || \
                                 ((__MODE__) == IRDA_MODE_ENABLE))

Ensure that IRDA associated UART/USART mode is valid.

Parameters:
__MODE__,: IRDA associated UART/USART mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 723 of file stm32h7xx_hal_irda.h.

#define IS_IRDA_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
                                                 ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))

Ensure that IRDA sampling rate is valid.

Parameters:
__ONEBIT__,: IRDA sampling rate.
Return values:
SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

Definition at line 731 of file stm32h7xx_hal_irda.h.

#define IS_IRDA_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == IRDA_PARITY_NONE) || \
                                    ((__PARITY__) == IRDA_PARITY_EVEN) || \
                                    ((__PARITY__) == IRDA_PARITY_ODD))

Ensure that IRDA frame parity is valid.

Parameters:
__PARITY__,: IRDA frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 691 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_POWERMODE ( __MODE__ )
Value:
(((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
                                     ((__MODE__) == IRDA_POWERMODE_NORMAL))

Ensure that IRDA power mode is valid.

Parameters:
__MODE__,: IRDA power mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 707 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_PRESCALER ( __PRESCALER__ ) ((__PRESCALER__) > 0)

Ensure that IRDA prescaler value is strictly larger than 0.

Parameters:
__PRESCALER__,: specifies the IRDA prescaler value set by the user.
Return values:
True or False

Definition at line 675 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
                                              ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
                                              ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))

Ensure that IRDA request is valid.

Parameters:
__PARAM__,: IRDA request.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 755 of file stm32h7xx_hal_irda.h.

#define IS_IRDA_STATE ( __STATE__ )
Value:
(((__STATE__) == IRDA_STATE_DISABLE) || \
                                  ((__STATE__) == IRDA_STATE_ENABLE))

Ensure that IRDA state is valid.

Parameters:
__STATE__,: IRDA state mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 715 of file stm32h7xx_hal_irda.h.

#define IS_IRDA_TX_RX_MODE ( __MODE__ ) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))

Ensure that IRDA communication mode is valid.

Parameters:
__MODE__,: IRDA communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 700 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
                                         ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
                                         ((__LENGTH__) == IRDA_WORDLENGTH_9B))

Ensure that IRDA frame length is valid.

Parameters:
__LENGTH__,: IRDA frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 682 of file stm32h7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
JPEG Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_JPEG_Init (JPEG_HandleTypeDef *hjpeg)
Initializes the JPEG according to the specified parameters in the JPEG_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_JPEG_DeInit (JPEG_HandleTypeDef *hjpeg)
DeInitializes the JPEG peripheral.
__weak void | HAL_JPEG_MspInit (JPEG_HandleTypeDef *hjpeg)
Initializes the JPEG MSP.
__weak void | HAL_JPEG_MspDeInit (JPEG_HandleTypeDef *hjpeg)
DeInitializes JPEG MSP.

Detailed Description

Initialization and de-initialization functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the JPEG peripheral and creates the associated handle
      (+) DeInitialize the JPEG peripheral

Function Documentation

HAL_StatusTypeDef HAL_JPEG_DeInit ( JPEG_HandleTypeDef * hjpeg )

DeInitializes the JPEG peripheral.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
HAL status

Definition at line 542 of file stm32h7xx_hal_jpeg.c.

References JPEG_HandleTypeDef::Context, JPEG_HandleTypeDef::ErrorCode, HAL_JPEG_ERROR_NONE, HAL_JPEG_MspDeInit(), HAL_JPEG_STATE_BUSY, HAL_JPEG_STATE_RESET, JPEG_HandleTypeDef::JpegInCount, JPEG_HandleTypeDef::JpegOutCount, and JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_Init ( JPEG_HandleTypeDef * hjpeg )

Initializes the JPEG according to the specified parameters in the JPEG_InitTypeDef and creates the associated handle.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
HAL status

Definition at line 459 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_CLEAR_FLAG, __HAL_JPEG_DISABLE_IT, __HAL_JPEG_ENABLE, JPEG_HandleTypeDef::Context, JPEG_HandleTypeDef::ErrorCode, HAL_JPEG_ERROR_HUFF_TABLE, HAL_JPEG_ERROR_NONE, HAL_JPEG_MspInit(), HAL_JPEG_STATE_BUSY, HAL_JPEG_STATE_READY, HAL_JPEG_STATE_RESET, JPEG_HandleTypeDef::Instance, JPEG_CHROM_QuantTable, JPEG_FLAG_ALL, JPEG_INTERRUPT_MASK, JPEG_LUM_QuantTable, JPEG_Set_HuffEnc_Mem(), JPEG_HandleTypeDef::JpegInCount, JPEG_HandleTypeDef::JpegOutCount, JPEG_HandleTypeDef::Lock, JPEG_HandleTypeDef::QuantTable0, JPEG_HandleTypeDef::QuantTable1, JPEG_HandleTypeDef::QuantTable2, JPEG_HandleTypeDef::QuantTable3, and JPEG_HandleTypeDef::State.

void HAL_JPEG_MspDeInit ( JPEG_HandleTypeDef * hjpeg )

DeInitializes JPEG MSP.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 598 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_DeInit().

void HAL_JPEG_MspInit ( JPEG_HandleTypeDef * hjpeg )

Initializes the JPEG MSP.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 582 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Init().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Configuration functions

Functions
Configuration functions
JPEG Exported Functions

JPEG Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_JPEG_ConfigEncoding (JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf)
Set the JPEG encoding configuration.
HAL_StatusTypeDef | HAL_JPEG_GetInfo (JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
Extract the image configuration from the JPEG header during the decoding.
HAL_StatusTypeDef | HAL_JPEG_EnableHeaderParsing (JPEG_HandleTypeDef *hjpeg)
Enable JPEG Header parsing for decoding.
HAL_StatusTypeDef | HAL_JPEG_DisableHeaderParsing (JPEG_HandleTypeDef *hjpeg)
Disable JPEG Header parsing for decoding.
HAL_StatusTypeDef | HAL_JPEG_SetUserQuantTables (JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, uint8_t *QTable2, uint8_t *QTable3)
Modify the default Quantization tables used for JPEG encoding.

Detailed Description

JPEG Configuration functions.

  ==============================================================================
              ##### Configuration functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) HAL_JPEG_ConfigEncoding() : JPEG encoding configuration
      (+) HAL_JPEG_GetInfo() :  Extract the image configuration from the JPEG header during the decoding
      (+) HAL_JPEG_EnableHeaderParsing() :  Enable JPEG Header parsing for decoding
      (+) HAL_JPEG_DisableHeaderParsing() : Disable JPEG Header parsing for decoding
      (+) HAL_JPEG_SetUserQuantTables : Modify the default Quantization tables used for JPEG encoding.

Function Documentation

HAL_StatusTypeDef HAL_JPEG_ConfigEncoding | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | JPEG_ConfTypeDef * | pConf
 | ) |  |

Set the JPEG encoding configuration.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
pConf,: pointer to a JPEG_ConfTypeDef structure that contains the encoding configuration
Return values:
HAL status

Definition at line 638 of file stm32h7xx_hal_jpeg.c.

References assert_param, JPEG_ConfTypeDef::ChromaSubsampling, JPEG_ConfTypeDef::ColorSpace, JPEG_HandleTypeDef::Conf, JPEG_HandleTypeDef::Context, JPEG_HandleTypeDef::ErrorCode, HAL_JPEG_ERROR_QUANT_TABLE, HAL_JPEG_STATE_BUSY, HAL_JPEG_STATE_READY, JPEG_ConfTypeDef::ImageHeight, JPEG_ConfTypeDef::ImageQuality, JPEG_ConfTypeDef::ImageWidth, JPEG_HandleTypeDef::Instance, IS_JPEG_CHROMASUBSAMPLING, IS_JPEG_COLORSPACE, IS_JPEG_IMAGE_QUALITY, JPEG_420_SUBSAMPLING, JPEG_422_SUBSAMPLING, JPEG_444_SUBSAMPLING, JPEG_CONTEXT_CONF_ENCODING, JPEG_CONTEXT_CUSTOM_TABLES, JPEG_GRAYSCALE_COLORSPACE, JPEG_Set_Quantization_Mem(), JPEG_SetColorCMYK(), JPEG_SetColorGrayScale(), JPEG_SetColorYCBCR(), JPEG_YCBCR_COLORSPACE, JPEG_HandleTypeDef::QuantTable0, JPEG_HandleTypeDef::QuantTable1, JPEG_HandleTypeDef::QuantTable2, JPEG_HandleTypeDef::QuantTable3, and JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing ( JPEG_HandleTypeDef * hjpeg )

Disable JPEG Header parsing for decoding.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for the JPEG.
Return values:
HAL status

Definition at line 923 of file stm32h7xx_hal_jpeg.c.

References HAL_JPEG_STATE_BUSY, HAL_JPEG_STATE_READY, JPEG_HandleTypeDef::Instance, and JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing ( JPEG_HandleTypeDef * hjpeg )

Enable JPEG Header parsing for decoding.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for the JPEG.
Return values:
HAL status

Definition at line 887 of file stm32h7xx_hal_jpeg.c.

References HAL_JPEG_STATE_BUSY, HAL_JPEG_STATE_READY, JPEG_HandleTypeDef::Instance, and JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_GetInfo | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | JPEG_ConfTypeDef * | pInfo
 | ) |  |

Extract the image configuration from the JPEG header during the decoding.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
pInfo,: pointer to a JPEG_ConfTypeDef structure that contains The JPEG decoded header informations
Return values:
HAL status

Definition at line 820 of file stm32h7xx_hal_jpeg.c.

References JPEG_ConfTypeDef::ChromaSubsampling, JPEG_ConfTypeDef::ColorSpace, JPEG_ConfTypeDef::ImageHeight, JPEG_ConfTypeDef::ImageQuality, JPEG_ConfTypeDef::ImageWidth, JPEG_HandleTypeDef::Instance, JPEG_420_SUBSAMPLING, JPEG_422_SUBSAMPLING, JPEG_444_SUBSAMPLING, JPEG_CMYK_COLORSPACE, JPEG_GetQuality(), JPEG_GRAYSCALE_COLORSPACE, and JPEG_YCBCR_COLORSPACE.

Referenced by JPEG_DMA_ContinueProcess(), and JPEG_Process().

HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | QTable0,
 |  | uint8_t * | QTable1,
 |  | uint8_t * | QTable2,
 |  | uint8_t * | QTable3
 | ) |  |

Modify the default Quantization tables used for JPEG encoding.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
QTable0 | : pointer to uint8_t , define the user quantification table for color component 1. If NULL assume no need to update the table and no error return
QTable1 | : pointer to uint8_t , define the user quantification table for color component 2. If NULL assume no need to update the table and no error return.
QTable2 | : pointer to uint8_t , define the user quantification table for color component 3, If NULL assume no need to update the table and no error return.
QTable3 | : pointer to uint8_t , define the user quantification table for color component 4. If NULL assume no need to update the table and no error return.
Return values:
HAL status

Definition at line 970 of file stm32h7xx_hal_jpeg.c.

References JPEG_HandleTypeDef::Context, HAL_JPEG_STATE_BUSY, HAL_JPEG_STATE_READY, JPEG_CONTEXT_CUSTOM_TABLES, JPEG_HandleTypeDef::QuantTable0, JPEG_HandleTypeDef::QuantTable1, JPEG_HandleTypeDef::QuantTable2, JPEG_HandleTypeDef::QuantTable3, and JPEG_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: encoding/decoding processing functions

Functions
encoding/decoding processing functions
JPEG Exported Functions

processing functions. More...

Functions

HAL_StatusTypeDef | HAL_JPEG_Encode (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout)
Starts JPEG encoding with polling processing.
HAL_StatusTypeDef | HAL_JPEG_Decode (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, uint8_t *pDataOutMCU, uint32_t OutDataLength, uint32_t Timeout)
Starts JPEG decoding with polling processing.
HAL_StatusTypeDef | HAL_JPEG_Encode_IT (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)
Starts JPEG encoding with interrupt processing.
HAL_StatusTypeDef | HAL_JPEG_Decode_IT (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, uint8_t *pDataOutMCU, uint32_t OutDataLength)
Starts JPEG decoding with interrupt processing.
HAL_StatusTypeDef | HAL_JPEG_Encode_DMA (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)
Starts JPEG encoding with DMA processing.
HAL_StatusTypeDef | HAL_JPEG_Decode_DMA (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, uint8_t *pDataOutMCU, uint32_t OutDataLength)
Starts JPEG decoding with DMA processing.
HAL_StatusTypeDef | HAL_JPEG_Pause (JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)
Pause the JPEG Input/Output processing.
HAL_StatusTypeDef | HAL_JPEG_Resume (JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)
Resume the JPEG Input/Output processing.
void | HAL_JPEG_ConfigInputBuffer (JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength)
Config Encoding/Decoding Input Buffer.
void | HAL_JPEG_ConfigOutputBuffer (JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength)
Config Encoding/Decoding Output Buffer.
HAL_StatusTypeDef | HAL_JPEG_Abort (JPEG_HandleTypeDef *hjpeg)
Aborts the JPEG Encoding/Decoding.

Detailed Description

processing functions.

  ==============================================================================
                      ##### JPEG processing functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) HAL_JPEG_Encode()     : JPEG encoding with polling process
      (+) HAL_JPEG_Decode()     : JPEG decoding with polling process
      (+) HAL_JPEG_Encode_IT()  : JPEG encoding with interrupt process
      (+) HAL_JPEG_Decode_IT()  : JPEG decoding with interrupt process
      (+) HAL_JPEG_Encode_DMA() : JPEG encoding with DMA process
      (+) HAL_JPEG_Decode_DMA() : JPEG decoding with DMA process
      (+) HAL_JPEG_Pause()      :   Pause the Input/Output processing
      (+) HAL_JPEG_Resume()     :  Resume the JPEG Input/Output processing
      (+) HAL_JPEG_ConfigInputBuffer()  : Config Encoding/Decoding Input Buffer
      (+) HAL_JPEG_ConfigOutputBuffer() : Config Encoding/Decoding Output Buffer
      (+) HAL_JPEG_Abort()              : Aborts the JPEG Encoding/Decoding

Function Documentation

HAL_StatusTypeDef HAL_JPEG_Abort ( JPEG_HandleTypeDef * hjpeg )

Aborts the JPEG Encoding/Decoding.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
HAL status

Definition at line 1673 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_CLEAR_FLAG, __HAL_JPEG_DISABLE_IT, __HAL_JPEG_GET_FLAG, JPEG_HandleTypeDef::Context, JPEG_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_JPEG_ERROR_TIMEOUT, HAL_JPEG_STATE_READY, HAL_JPEG_STATE_TIMEOUT, HAL_MDMA_Abort(), JPEG_HandleTypeDef::hdmain, JPEG_HandleTypeDef::hdmaout, JPEG_HandleTypeDef::Instance, JPEG_CONTEXT_DMA, JPEG_CONTEXT_ENDING_DMA, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_OPERATION_MASK, JPEG_CONTEXT_PAUSE_INPUT, JPEG_CONTEXT_PAUSE_OUTPUT, JPEG_FLAG_ALL, JPEG_FLAG_COF, JPEG_INTERRUPT_MASK, JPEG_TIMEOUT_VALUE, JPEG_HandleTypeDef::JpegInCount, JPEG_HandleTypeDef::JpegOutCount, and JPEG_HandleTypeDef::State.

void HAL_JPEG_ConfigInputBuffer | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | pNewInputBuffer,
 |  | uint32_t | InDataLength
 | ) |  |

Config Encoding/Decoding Input Buffer.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module.
pNewInputBuffer,: Pointer to the new input data buffer
InDataLength,: Size in bytes of the new Input data buffer
Return values:
HAL status

Definition at line 1647 of file stm32h7xx_hal_jpeg.c.

References JPEG_HandleTypeDef::InDataLength, and JPEG_HandleTypeDef::pJpegInBuffPtr.

void HAL_JPEG_ConfigOutputBuffer | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | pNewOutputBuffer,
 |  | uint32_t | OutDataLength
 | ) |  |

Config Encoding/Decoding Output Buffer.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module.
pNewOutputBuffer,: Pointer to the new output data buffer
OutDataLength,: Size in bytes of the new Output data buffer
Return values:
HAL status

Definition at line 1661 of file stm32h7xx_hal_jpeg.c.

References JPEG_HandleTypeDef::OutDataLength, and JPEG_HandleTypeDef::pJpegOutBuffPtr.

HAL_StatusTypeDef HAL_JPEG_Decode | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | pDataIn,
 |  | uint32_t | InDataLength,
 |  | uint8_t * | pDataOutMCU,
 |  | uint32_t | OutDataLength,
 |  | uint32_t | Timeout
 | ) |  |

Starts JPEG decoding with polling processing.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
pDataIn,: Pointer to the input data buffer
InDataLength,: size in bytes Input buffer
pDataOutMCU,: Pointer to the Output data buffer
OutDataLength,: size in bytes of the Output buffer
Timeout,: Specify Timeout value
Return values:
HAL status

Definition at line 1149 of file stm32h7xx_hal_jpeg.c.

References assert_param, JPEG_HandleTypeDef::Context, JPEG_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_JPEG_ERROR_TIMEOUT, HAL_JPEG_STATE_BUSY_DECODING, HAL_JPEG_STATE_READY, JPEG_HandleTypeDef::InDataLength, JPEG_CONTEXT_DECODE, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_OPERATION_MASK, JPEG_CONTEXT_POLLING, JPEG_Init_Process(), JPEG_Process(), JPEG_PROCESS_ONGOING, JPEG_HandleTypeDef::JpegInCount, JPEG_HandleTypeDef::JpegOutCount, JPEG_HandleTypeDef::OutDataLength, JPEG_HandleTypeDef::pJpegInBuffPtr, JPEG_HandleTypeDef::pJpegOutBuffPtr, and JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_Decode_DMA | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | pDataIn,
 |  | uint32_t | InDataLength,
 |  | uint8_t * | pDataOutMCU,
 |  | uint32_t | OutDataLength
 | ) |  |

Starts JPEG decoding with DMA processing.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
pDataIn,: Pointer to the input data buffer
InDataLength,: size in bytes Input buffer
pDataOutMCU,: Pointer to the Output data buffer
OutDataLength,: size in bytes of the Output buffer
Return values:
HAL status

Definition at line 1453 of file stm32h7xx_hal_jpeg.c.

References assert_param, JPEG_HandleTypeDef::Context, HAL_JPEG_STATE_BUSY_DECODING, HAL_JPEG_STATE_READY, JPEG_HandleTypeDef::InDataLength, JPEG_CONTEXT_DECODE, JPEG_CONTEXT_DMA, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_OPERATION_MASK, JPEG_DMA_StartProcess(), JPEG_Init_Process(), JPEG_HandleTypeDef::JpegInCount, JPEG_HandleTypeDef::JpegOutCount, JPEG_HandleTypeDef::OutDataLength, JPEG_HandleTypeDef::pJpegInBuffPtr, JPEG_HandleTypeDef::pJpegOutBuffPtr, and JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_Decode_IT | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | pDataIn,
 |  | uint32_t | InDataLength,
 |  | uint8_t * | pDataOutMCU,
 |  | uint32_t | OutDataLength
 | ) |  |

Starts JPEG decoding with interrupt processing.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
pDataIn,: Pointer to the input data buffer
InDataLength,: size in bytes Input buffer
pDataOutMCU,: Pointer to the Output data buffer
OutDataLength,: size in bytes of the Output buffer
Return values:
HAL status

Definition at line 1318 of file stm32h7xx_hal_jpeg.c.

References assert_param, JPEG_HandleTypeDef::Context, HAL_JPEG_STATE_BUSY_DECODING, HAL_JPEG_STATE_READY, JPEG_HandleTypeDef::InDataLength, JPEG_CONTEXT_DECODE, JPEG_CONTEXT_IT, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_OPERATION_MASK, JPEG_Init_Process(), JPEG_HandleTypeDef::JpegInCount, JPEG_HandleTypeDef::JpegOutCount, JPEG_HandleTypeDef::OutDataLength, JPEG_HandleTypeDef::pJpegInBuffPtr, JPEG_HandleTypeDef::pJpegOutBuffPtr, and JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_Encode | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | pDataInMCU,
 |  | uint32_t | InDataLength,
 |  | uint8_t * | pDataOut,
 |  | uint32_t | OutDataLength,
 |  | uint32_t | Timeout
 | ) |  |

Starts JPEG encoding with polling processing.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
pDataInMCU,: Pointer to the Input buffer
InDataLength,: size in bytes Input buffer
pDataOut,: Pointer to the jpeg output data buffer
OutDataLength,: size in bytes of the Output buffer
Timeout,: Specify Timeout value
Return values:
HAL status

Definition at line 1044 of file stm32h7xx_hal_jpeg.c.

References assert_param, JPEG_HandleTypeDef::Context, JPEG_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_JPEG_ERROR_TIMEOUT, HAL_JPEG_STATE_BUSY_ENCODING, HAL_JPEG_STATE_READY, JPEG_HandleTypeDef::InDataLength, JPEG_CONTEXT_CONF_ENCODING, JPEG_CONTEXT_ENCODE, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_OPERATION_MASK, JPEG_CONTEXT_POLLING, JPEG_Init_Process(), JPEG_Process(), JPEG_PROCESS_ONGOING, JPEG_HandleTypeDef::JpegInCount, JPEG_HandleTypeDef::JpegOutCount, JPEG_HandleTypeDef::OutDataLength, JPEG_HandleTypeDef::pJpegInBuffPtr, JPEG_HandleTypeDef::pJpegOutBuffPtr, and JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_Encode_DMA | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | pDataInMCU,
 |  | uint32_t | InDataLength,
 |  | uint8_t * | pDataOut,
 |  | uint32_t | OutDataLength
 | ) |  |

Starts JPEG encoding with DMA processing.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
pDataInMCU,: Pointer to the Input buffer
InDataLength,: size in bytes Input buffer
pDataOut,: Pointer to the jpeg output data buffer
OutDataLength,: size in bytes of the Output buffer
Return values:
HAL status

Definition at line 1381 of file stm32h7xx_hal_jpeg.c.

References assert_param, JPEG_HandleTypeDef::Context, HAL_JPEG_STATE_BUSY_ENCODING, HAL_JPEG_STATE_READY, JPEG_HandleTypeDef::InDataLength, JPEG_CONTEXT_CONF_ENCODING, JPEG_CONTEXT_DMA, JPEG_CONTEXT_ENCODE, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_OPERATION_MASK, JPEG_DMA_StartProcess(), JPEG_Init_Process(), JPEG_HandleTypeDef::JpegInCount, JPEG_HandleTypeDef::JpegOutCount, JPEG_HandleTypeDef::OutDataLength, JPEG_HandleTypeDef::pJpegInBuffPtr, JPEG_HandleTypeDef::pJpegOutBuffPtr, and JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_Encode_IT | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | pDataInMCU,
 |  | uint32_t | InDataLength,
 |  | uint8_t * | pDataOut,
 |  | uint32_t | OutDataLength
 | ) |  |

Starts JPEG encoding with interrupt processing.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
pDataInMCU,: Pointer to the Input buffer
InDataLength,: size in bytes Input buffer
pDataOut,: Pointer to the jpeg output data buffer
OutDataLength,: size in bytes of the Output buffer
Return values:
HAL status

Definition at line 1245 of file stm32h7xx_hal_jpeg.c.

References assert_param, JPEG_HandleTypeDef::Context, HAL_JPEG_STATE_BUSY_ENCODING, HAL_JPEG_STATE_READY, JPEG_HandleTypeDef::InDataLength, JPEG_CONTEXT_CONF_ENCODING, JPEG_CONTEXT_ENCODE, JPEG_CONTEXT_IT, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_OPERATION_MASK, JPEG_Init_Process(), JPEG_HandleTypeDef::JpegInCount, JPEG_HandleTypeDef::JpegOutCount, JPEG_HandleTypeDef::OutDataLength, JPEG_HandleTypeDef::pJpegInBuffPtr, JPEG_HandleTypeDef::pJpegOutBuffPtr, and JPEG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_JPEG_Pause | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint32_t | XferSelection
 | ) |  |

Pause the JPEG Input/Output processing.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
XferSelection,: This parameter can be one of the following values : JPEG_PAUSE_RESUME_INPUT : Pause Input processing JPEG_PAUSE_RESUME_OUTPUT: Pause Output processing JPEG_PAUSE_RESUME_INPUT_OUTPUT: Pause Input and Output processing
Return values:
HAL status

Definition at line 1515 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_DISABLE_IT, assert_param, JPEG_HandleTypeDef::Context, IS_JPEG_PAUSE_RESUME_STATE, JPEG_CONTEXT_DMA, JPEG_CONTEXT_IT, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_PAUSE_INPUT, JPEG_CONTEXT_PAUSE_OUTPUT, JPEG_IT_EOC, JPEG_IT_IFNF, JPEG_IT_IFT, JPEG_IT_OFNE, JPEG_IT_OFT, JPEG_PAUSE_RESUME_INPUT, and JPEG_PAUSE_RESUME_OUTPUT.

Referenced by JPEG_ReadInputData().

HAL_StatusTypeDef HAL_JPEG_Resume | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint32_t | XferSelection
 | ) |  |

Resume the JPEG Input/Output processing.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
XferSelection,: This parameter can be one of the following values : JPEG_PAUSE_RESUME_INPUT : Resume Input processing JPEG_PAUSE_RESUME_OUTPUT: Resume Output processing JPEG_PAUSE_RESUME_INPUT_OUTPUT: Resume Input and Output processing
Return values:
HAL status

Definition at line 1563 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_ENABLE_IT, assert_param, MDMA_InitTypeDef::BufferTransferLength, JPEG_HandleTypeDef::Context, HAL_MDMA_Start_IT(), JPEG_HandleTypeDef::hdmain, JPEG_HandleTypeDef::hdmaout, JPEG_HandleTypeDef::InDataLength, __MDMA_HandleTypeDef::Init, JPEG_HandleTypeDef::Instance, IS_JPEG_PAUSE_RESUME_STATE, JPEG_CONTEXT_DMA, JPEG_CONTEXT_ENDING_DMA, JPEG_CONTEXT_IT, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_PAUSE_INPUT, JPEG_CONTEXT_PAUSE_OUTPUT, JPEG_DMA_PollResidualData(), JPEG_IT_EOC, JPEG_IT_IFNF, JPEG_IT_IFT, JPEG_IT_OFNE, JPEG_IT_OFT, JPEG_PAUSE_RESUME_INPUT, JPEG_PAUSE_RESUME_OUTPUT, JPEG_HandleTypeDef::OutDataLength, JPEG_HandleTypeDef::pJpegInBuffPtr, and JPEG_HandleTypeDef::pJpegOutBuffPtr.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: JPEG Decode/Encode callback functions

Functions
JPEG Decode/Encode callback functions
JPEG Exported Functions

JPEG process callback functions. More...

Functions

__weak void | HAL_JPEG_InfoReadyCallback (JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
Decoding JPEG Info ready callback.
__weak void | HAL_JPEG_EncodeCpltCallback (JPEG_HandleTypeDef *hjpeg)
Encoding complete callback.
__weak void | HAL_JPEG_DecodeCpltCallback (JPEG_HandleTypeDef *hjpeg)
Decoding complete callback.
__weak void | HAL_JPEG_ErrorCallback (JPEG_HandleTypeDef *hjpeg)
JPEG error callback.
__weak void | HAL_JPEG_GetDataCallback (JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData)
Get New Data chunk callback.
__weak void | HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength)
Decoded/Encoded Data ready callback.

Detailed Description

JPEG process callback functions.

  ==============================================================================
              #####  JPEG Decode and Encode callback functions  #####
  ==============================================================================
    [..]  This section provides callback functions:
      (+) HAL_JPEG_InfoReadyCallback()  : Decoding JPEG Info ready callback
      (+) HAL_JPEG_EncodeCpltCallback() : Encoding complete callback.
      (+) HAL_JPEG_DecodeCpltCallback() : Decoding complete callback.
      (+) HAL_JPEG_ErrorCallback()      : JPEG error callback.
      (+) HAL_JPEG_GetDataCallback()    : Get New Data chunk callback.
      (+) HAL_JPEG_DataReadyCallback()  : Decoded/Encoded Data ready  callback.

Function Documentation

void HAL_JPEG_DataReadyCallback | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | pDataOut,
 |  | uint32_t | OutDataLength
 | ) |  |

Decoded/Encoded Data ready callback.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
pDataOut,: pointer to the output data buffer
OutDataLength,: number in bytes of data available in the specified output buffer
Return values:
None

Definition at line 1858 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_MDMAOutCpltCallback(), JPEG_Process(), and JPEG_StoreOutputData().

void HAL_JPEG_DecodeCpltCallback ( JPEG_HandleTypeDef * hjpeg )

Decoding complete callback.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 1806 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), and JPEG_Process().

void HAL_JPEG_EncodeCpltCallback ( JPEG_HandleTypeDef * hjpeg )

Encoding complete callback.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 1790 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), and JPEG_Process().

void HAL_JPEG_ErrorCallback ( JPEG_HandleTypeDef * hjpeg )

JPEG error callback.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 1822 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_MDMAErrorCallback().

void HAL_JPEG_GetDataCallback | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint32_t | NbDecodedData
 | ) |  |

Get New Data chunk callback.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
NbDecodedData,: Number of consummed data in the previous chunk in bytes
Return values:
None

Definition at line 1839 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_MDMAInCpltCallback(), and JPEG_ReadInputData().

void HAL_JPEG_InfoReadyCallback | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | JPEG_ConfTypeDef * | pInfo
 | ) |  |

Decoding JPEG Info ready callback.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
pInfo,: pointer to a JPEG_ConfTypeDef structure that contains The JPEG decoded header informations
Return values:
None

Definition at line 1773 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_DMA_ContinueProcess(), and JPEG_Process().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: JPEG IRQ handler management

Functions
JPEG IRQ handler management
JPEG Exported Functions

JPEG IRQ handler. More...

Functions

void HAL_JPEG_IRQHandler (JPEG_HandleTypeDef *hjpeg)
This function handles JPEG interrupt request.

Detailed Description

JPEG IRQ handler.

  ==============================================================================
                ##### JPEG IRQ handler management #####
  ==============================================================================
    [..]  This section provides JPEG IRQ handler function.
      (+) HAL_JPEG_IRQHandler()  : handles JPEG interrupt request

Function Documentation

void HAL_JPEG_IRQHandler ( JPEG_HandleTypeDef * hjpeg )

This function handles JPEG interrupt request.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 1895 of file stm32h7xx_hal_jpeg.c.

References JPEG_HandleTypeDef::Context, HAL_JPEG_STATE_BUSY_DECODING, HAL_JPEG_STATE_BUSY_ENCODING, JPEG_CONTEXT_DMA, JPEG_CONTEXT_IT, JPEG_CONTEXT_METHOD_MASK, JPEG_DMA_ContinueProcess(), JPEG_Process(), and JPEG_HandleTypeDef::State.

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STM32H753xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
JPEG Exported Functions

Peripheral State functions. More...

Functions

HAL_JPEG_STATETypeDef | HAL_JPEG_GetState (JPEG_HandleTypeDef *hjpeg)
Returns the JPEG state.
uint32_t | HAL_JPEG_GetError (JPEG_HandleTypeDef *hjpeg)
Return the JPEG error code.

Detailed Description

Peripheral State functions.

  ==============================================================================
                    ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]  This section provides JPEG State and Errors function.
      (+) HAL_JPEG_GetState()  : permits to get in run-time the JPEG state.
      (+) HAL_JPEG_GetError()  : Returns the JPEG error code if any.

Function Documentation

uint32_t HAL_JPEG_GetError ( JPEG_HandleTypeDef * hjpeg )

Return the JPEG error code.

Parameters:
hjpeg : pointer to a JPEG_HandleTypeDef structure that contains the configuration information for the specified JPEG.
Return values:
JPEG Error Code

Definition at line 1956 of file stm32h7xx_hal_jpeg.c.

References JPEG_HandleTypeDef::ErrorCode.

HAL_JPEG_STATETypeDef HAL_JPEG_GetState ( JPEG_HandleTypeDef * hjpeg )

Returns the JPEG state.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
JPEG state

Definition at line 1945 of file stm32h7xx_hal_jpeg.c.

References JPEG_HandleTypeDef::State.

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STM32H753xx HAL User Manual: JPEG_ConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
JPEG_ConfTypeDef Struct Reference
JPEG Configuration for encoding Structure definition

#include <stm32h7xx_hal_jpeg.h>

Data Fields

uint8_t | ColorSpace
uint8_t | ChromaSubsampling
uint32_t | ImageHeight
uint32_t | ImageWidth
uint8_t | ImageQuality

Detailed Description

Definition at line 67 of file stm32h7xx_hal_jpeg.h.

Field Documentation

uint8_t JPEG_ConfTypeDef::ChromaSubsampling

Chroma Subsampling in case of YCBCR or CMYK color space, 0-> 4:4:4 , 1-> 4:2:2, 2 -> 4:1:1, 3 -> 4:2:0 This parameter can be a value of JPEG Chrominance Sampling

Definition at line 72 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), HAL_JPEG_GetInfo(), JPEG_SetColorCMYK(), and JPEG_SetColorYCBCR().

uint8_t JPEG_ConfTypeDef::ColorSpace

Image Color space : gray-scale, YCBCR, RGB or CMYK This parameter can be a value of JPEG ColorSpace

Definition at line 69 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), and HAL_JPEG_GetInfo().

uint32_t JPEG_ConfTypeDef::ImageHeight

Image height : number of lines

Definition at line 75 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), and HAL_JPEG_GetInfo().

uint8_t JPEG_ConfTypeDef::ImageQuality

Quality of the JPEG encoding : from 1 to 100

Definition at line 79 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), HAL_JPEG_GetInfo(), JPEG_DMA_ContinueProcess(), JPEG_Process(), and JPEG_Set_Quantization_Mem().

uint32_t JPEG_ConfTypeDef::ImageWidth

Image width : number of pixels per line

Definition at line 77 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), and HAL_JPEG_GetInfo().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_jpeg.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HAL JPEG state structure definition

Enumerations
HAL JPEG state structure definition
JPEG Exported Types

HAL JPEG State structure definition. More...

Enumerations

enum HAL_JPEG_STATETypeDef {
HAL_JPEG_STATE_RESET = 0x00U, HAL_JPEG_STATE_READY = 0x01U, HAL_JPEG_STATE_BUSY = 0x02U, HAL_JPEG_STATE_BUSY_ENCODING = 0x03U,
HAL_JPEG_STATE_BUSY_DECODING = 0x04U, HAL_JPEG_STATE_TIMEOUT = 0x05U, HAL_JPEG_STATE_ERROR = 0x06U
}

Detailed Description

HAL JPEG State structure definition.

Enumeration Type Documentation

enum HAL_JPEG_STATETypeDef
Enumerator:
HAL_JPEG_STATE_RESET

JPEG not yet initialized or disabled

HAL_JPEG_STATE_READY

JPEG initialized and ready for use

HAL_JPEG_STATE_BUSY

JPEG internal processing is ongoing

HAL_JPEG_STATE_BUSY_ENCODING

JPEG encoding processing is ongoing

HAL_JPEG_STATE_BUSY_DECODING

JPEG decoding processing is ongoing

HAL_JPEG_STATE_TIMEOUT

JPEG timeout state

HAL_JPEG_STATE_ERROR

JPEG error state

Definition at line 90 of file stm32h7xx_hal_jpeg.h.

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STM32H753xx HAL User Manual: JPEG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
JPEG_HandleTypeDef Struct Reference
JPEG handle Structure definition

#include <stm32h7xx_hal_jpeg.h>

Data Fields

JPEG_TypeDef * | Instance
JPEG_ConfTypeDef Conf
uint8_t * | pJpegInBuffPtr
uint8_t * | pJpegOutBuffPtr
__IO uint32_t | JpegInCount
__IO uint32_t | JpegOutCount
uint32_t | InDataLength
uint32_t | OutDataLength
MDMA_HandleTypeDef * hdmain
MDMA_HandleTypeDef * hdmaout
uint8_t | CustomQuanTable
uint8_t * | QuantTable0
uint8_t * | QuantTable1
uint8_t * | QuantTable2
uint8_t * | QuantTable3
HAL_LockTypeDef | Lock
__IO HAL_JPEG_STATETypeDef | State
__IO uint32_t | ErrorCode
__IO uint32_t | Context

Detailed Description

Definition at line 110 of file stm32h7xx_hal_jpeg.h.

Field Documentation

JPEG_ConfTypeDef JPEG_HandleTypeDef::Conf

Current JPEG encoding/decoding parameters

Definition at line 114 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), JPEG_DMA_ContinueProcess(), JPEG_Process(), JPEG_Set_Quantization_Mem(), JPEG_SetColorCMYK(), and JPEG_SetColorYCBCR().

__IO uint32_t JPEG_HandleTypeDef::Context

JPEG Internal context

Definition at line 148 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_ConfigEncoding(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_DeInit(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), HAL_JPEG_Init(), HAL_JPEG_IRQHandler(), HAL_JPEG_Pause(), HAL_JPEG_Resume(), HAL_JPEG_SetUserQuantTables(), JPEG_DMA_ContinueProcess(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_Init_Process(), JPEG_MDMAInCpltCallback(), JPEG_MDMAOutAbortCallback(), JPEG_MDMAOutCpltCallback(), JPEG_Process(), and JPEG_ReadInputData().

uint8_t JPEG_HandleTypeDef::CustomQuanTable

If set to 1 specify that user customized quantization tables are used

Definition at line 132 of file stm32h7xx_hal_jpeg.h.

__IO uint32_t JPEG_HandleTypeDef::ErrorCode

JPEG Error code

Definition at line 146 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_ConfigEncoding(), HAL_JPEG_Decode(), HAL_JPEG_DeInit(), HAL_JPEG_Encode(), HAL_JPEG_GetError(), HAL_JPEG_Init(), and JPEG_MDMAErrorCallback().

MDMA_HandleTypeDef* JPEG_HandleTypeDef::hdmain

JPEG In MDMA handle parameters

Definition at line 128 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Resume(), JPEG_DMA_ContinueProcess(), JPEG_DMA_StartProcess(), and JPEG_MDMAInCpltCallback().

MDMA_HandleTypeDef* JPEG_HandleTypeDef::hdmaout

JPEG Out MDMA handle parameters

Definition at line 130 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Resume(), JPEG_DMA_ContinueProcess(), JPEG_DMA_EndProcess(), JPEG_DMA_StartProcess(), and JPEG_MDMAOutCpltCallback().

uint32_t JPEG_HandleTypeDef::InDataLength

Input Buffer Length in Bytes

Definition at line 124 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigInputBuffer(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), HAL_JPEG_Resume(), JPEG_DMA_StartProcess(), JPEG_MDMAInCpltCallback(), and JPEG_ReadInputData().

JPEG_TypeDef* JPEG_HandleTypeDef::Instance

JPEG peripheral register base address

Definition at line 112 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_ConfigEncoding(), HAL_JPEG_DisableHeaderParsing(), HAL_JPEG_EnableHeaderParsing(), HAL_JPEG_GetInfo(), HAL_JPEG_Init(), HAL_JPEG_Resume(), JPEG_DMA_ContinueProcess(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_DMA_StartProcess(), JPEG_GetQuality(), JPEG_Init_Process(), JPEG_MDMAErrorCallback(), JPEG_MDMAInCpltCallback(), JPEG_MDMAOutCpltCallback(), JPEG_Process(), JPEG_ReadInputData(), JPEG_Set_Huff_DHTMem(), JPEG_Set_HuffAC_Mem(), JPEG_Set_HuffDC_Mem(), JPEG_Set_HuffEnc_Mem(), JPEG_Set_Quantization_Mem(), JPEG_SetColorCMYK(), JPEG_SetColorGrayScale(), JPEG_SetColorYCBCR(), and JPEG_StoreOutputData().

__IO uint32_t JPEG_HandleTypeDef::JpegInCount

Internal Counter of input data

Definition at line 120 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_DeInit(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), HAL_JPEG_Init(), JPEG_MDMAInCpltCallback(), and JPEG_ReadInputData().

__IO uint32_t JPEG_HandleTypeDef::JpegOutCount

Internal Counter of output data

Definition at line 122 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_DeInit(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), HAL_JPEG_Init(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_MDMAOutCpltCallback(), JPEG_Process(), and JPEG_StoreOutputData().

HAL_LockTypeDef JPEG_HandleTypeDef::Lock

JPEG locking object

Definition at line 142 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Init().

uint32_t JPEG_HandleTypeDef::OutDataLength

Output Buffer Length in Bytes

Definition at line 126 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigOutputBuffer(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), HAL_JPEG_Resume(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_DMA_StartProcess(), JPEG_MDMAOutCpltCallback(), and JPEG_StoreOutputData().

uint8_t* JPEG_HandleTypeDef::pJpegInBuffPtr

Pointer to JPEG processing (encoding, decoding,...) input buffer

Definition at line 116 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigInputBuffer(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), HAL_JPEG_Resume(), JPEG_DMA_StartProcess(), JPEG_MDMAInCpltCallback(), and JPEG_ReadInputData().

uint8_t* JPEG_HandleTypeDef::pJpegOutBuffPtr

Pointer to JPEG processing (encoding, decoding,...) output buffer

Definition at line 118 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigOutputBuffer(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), HAL_JPEG_Resume(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_DMA_StartProcess(), JPEG_MDMAOutCpltCallback(), JPEG_Process(), and JPEG_StoreOutputData().

uint8_t* JPEG_HandleTypeDef::QuantTable0

Basic Quantization Table for component 0

Definition at line 134 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), HAL_JPEG_Init(), and HAL_JPEG_SetUserQuantTables().

uint8_t* JPEG_HandleTypeDef::QuantTable1

Basic Quantization Table for component 1

Definition at line 136 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), HAL_JPEG_Init(), and HAL_JPEG_SetUserQuantTables().

uint8_t* JPEG_HandleTypeDef::QuantTable2

Basic Quantization Table for component 2

Definition at line 138 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), HAL_JPEG_Init(), and HAL_JPEG_SetUserQuantTables().

uint8_t* JPEG_HandleTypeDef::QuantTable3

Basic Quantization Table for component 3

Definition at line 140 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), HAL_JPEG_Init(), and HAL_JPEG_SetUserQuantTables().

__IO HAL_JPEG_STATETypeDef JPEG_HandleTypeDef::State

JPEG peripheral state

Definition at line 144 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_ConfigEncoding(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_DeInit(), HAL_JPEG_DisableHeaderParsing(), HAL_JPEG_EnableHeaderParsing(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), HAL_JPEG_GetState(), HAL_JPEG_Init(), HAL_JPEG_IRQHandler(), HAL_JPEG_SetUserQuantTables(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_MDMAErrorCallback(), and JPEG_Process().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_jpeg.h
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STM32H753xx HAL User Manual: JPEG Error Code definition

Defines
JPEG Error Code definition
JPEG Exported Constants

JPEG Error Code definition. More...

Defines

#define | HAL_JPEG_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_JPEG_ERROR_HUFF_TABLE ((uint32_t)0x00000001U)
#define | HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U)
#define | HAL_JPEG_ERROR_DMA ((uint32_t)0x00000004U)
#define | HAL_JPEG_ERROR_TIMEOUT ((uint32_t)0x00000008U)

Detailed Description

JPEG Error Code definition.

Define Documentation

#define HAL_JPEG_ERROR_DMA ((uint32_t)0x00000004U)

DMA transfer error

Definition at line 174 of file stm32h7xx_hal_jpeg.h.

Referenced by JPEG_MDMAErrorCallback().

#define HAL_JPEG_ERROR_HUFF_TABLE ((uint32_t)0x00000001U)

HUffman Table programming error

Definition at line 172 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Init().

#define HAL_JPEG_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 171 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_DeInit(), and HAL_JPEG_Init().

#define HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U)

Quantization Table programming error

Definition at line 173 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding().

#define HAL_JPEG_ERROR_TIMEOUT ((uint32_t)0x00000008U)

Timeout error

Definition at line 175 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Decode(), and HAL_JPEG_Encode().

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STM32H753xx HAL User Manual: JPEG Quantization Table Size

Defines
JPEG Quantization Table Size
JPEG Exported Constants

JPEG Quantization Table Size. More...

Defines

#define JPEG_QUANT_TABLE_SIZE ((uint32_t)64U)

Detailed Description

JPEG Quantization Table Size.

Define Documentation

#define JPEG_QUANT_TABLE_SIZE ((uint32_t)64U)

JPEG Quantization Table Size in bytes

Definition at line 185 of file stm32h7xx_hal_jpeg.h.

Referenced by JPEG_GetQuality(), and JPEG_Set_Quantization_Mem().

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STM32H753xx HAL User Manual: JPEG ColorSpace

Defines
JPEG ColorSpace
JPEG Exported Constants

JPEG Color Space. More...

Defines

#define | JPEG_GRAYSCALE_COLORSPACE ((uint32_t)0x00000000U)
#define | JPEG_YCBCR_COLORSPACE JPEG_CONFR1_COLORSPACE_0
#define | JPEG_CMYK_COLORSPACE JPEG_CONFR1_COLORSPACE

Detailed Description

JPEG Color Space.

Define Documentation

#define JPEG_CMYK_COLORSPACE JPEG_CONFR1_COLORSPACE

Definition at line 197 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_GetInfo().

#define JPEG_GRAYSCALE_COLORSPACE ((uint32_t)0x00000000U)

Definition at line 195 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), and HAL_JPEG_GetInfo().

#define JPEG_YCBCR_COLORSPACE JPEG_CONFR1_COLORSPACE_0

Definition at line 196 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), and HAL_JPEG_GetInfo().

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STM32H753xx HAL User Manual: JPEG Chrominance Sampling

Defines
JPEG Chrominance Sampling
JPEG Exported Constants

JPEG Chrominance Sampling. More...

Defines

#define | JPEG_444_SUBSAMPLING ((uint32_t)0x00000000U)
#define | JPEG_420_SUBSAMPLING ((uint32_t)0x00000001U)
#define | JPEG_422_SUBSAMPLING ((uint32_t)0x00000002U)

Detailed Description

JPEG Chrominance Sampling.

Define Documentation

#define JPEG_420_SUBSAMPLING ((uint32_t)0x00000001U)

Chroma Subsampling 4:2:0

Definition at line 210 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), HAL_JPEG_GetInfo(), JPEG_SetColorCMYK(), and JPEG_SetColorYCBCR().

#define JPEG_422_SUBSAMPLING ((uint32_t)0x00000002U)

Chroma Subsampling 4:2:2

Definition at line 211 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), HAL_JPEG_GetInfo(), JPEG_SetColorCMYK(), and JPEG_SetColorYCBCR().

#define JPEG_444_SUBSAMPLING ((uint32_t)0x00000000U)

Chroma Subsampling 4:4:4

Definition at line 209 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding(), and HAL_JPEG_GetInfo().

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STM32H753xx HAL User Manual: JPEG Image Quality

Defines
JPEG Image Quality
JPEG Exported Constants

JPEG Min and Max Image Quality. More...

Defines

#define | JPEG_IMAGE_QUALITY_MIN ((uint32_t)1U)
#define | JPEG_IMAGE_QUALITY_MAX ((uint32_t)100U)

Detailed Description

JPEG Min and Max Image Quality.

Define Documentation

#define JPEG_IMAGE_QUALITY_MAX ((uint32_t)100U)

Maximum JPEG quality

Definition at line 222 of file stm32h7xx_hal_jpeg.h.

#define JPEG_IMAGE_QUALITY_MIN ((uint32_t)1U)

Minimum JPEG quality

Definition at line 221 of file stm32h7xx_hal_jpeg.h.

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STM32H753xx HAL User Manual: JPEG Interrupt configuration definition

Defines
JPEG Interrupt configuration definition
JPEG Exported Constants

JPEG Interrupt definition. More...

Defines

#define | JPEG_IT_IFT ((uint32_t)JPEG_CR_IFTIE)
#define | JPEG_IT_IFNF ((uint32_t)JPEG_CR_IFNFIE)
#define | JPEG_IT_OFT ((uint32_t)JPEG_CR_OFTIE)
#define | JPEG_IT_OFNE ((uint32_t)JPEG_CR_OFTIE)
#define | JPEG_IT_EOC ((uint32_t)JPEG_CR_EOCIE)
#define | JPEG_IT_HPD ((uint32_t)JPEG_CR_HPDIE)

Detailed Description

JPEG Interrupt definition.

Define Documentation

#define JPEG_IT_EOC ((uint32_t)JPEG_CR_EOCIE)

End of Conversion Interrupt

Definition at line 236 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Pause(), HAL_JPEG_Resume(), JPEG_Init_Process(), JPEG_MDMAInCpltCallback(), and JPEG_MDMAOutCpltCallback().

#define JPEG_IT_HPD ((uint32_t)JPEG_CR_HPDIE)

Header Parsing Done Interrupt

Definition at line 237 of file stm32h7xx_hal_jpeg.h.

Referenced by JPEG_DMA_ContinueProcess(), JPEG_Init_Process(), JPEG_MDMAInCpltCallback(), JPEG_MDMAOutCpltCallback(), and JPEG_Process().

#define JPEG_IT_IFNF ((uint32_t)JPEG_CR_IFNFIE)

Input FIFO Not Full Interrupt

Definition at line 233 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Pause(), HAL_JPEG_Resume(), and JPEG_Init_Process().

#define JPEG_IT_IFT ((uint32_t)JPEG_CR_IFTIE)

Input FIFO Threshold Interrupt

Definition at line 232 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Pause(), HAL_JPEG_Resume(), and JPEG_Init_Process().

#define JPEG_IT_OFNE ((uint32_t)JPEG_CR_OFTIE)

Output FIFO Not Empty Interrupt

Definition at line 235 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Pause(), HAL_JPEG_Resume(), and JPEG_Init_Process().

#define JPEG_IT_OFT ((uint32_t)JPEG_CR_OFTIE)

Output FIFO Threshold Interrupt

Definition at line 234 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Pause(), HAL_JPEG_Resume(), and JPEG_Init_Process().

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STM32H753xx HAL User Manual: JPEG Flag definition

Defines
JPEG Flag definition
JPEG Exported Constants

JPEG Flags definition. More...

Defines

#define | JPEG_FLAG_IFTF ((uint32_t)JPEG_SR_IFTF)
#define | JPEG_FLAG_IFNFF ((uint32_t)JPEG_SR_IFNFF)
#define | JPEG_FLAG_OFTF ((uint32_t)JPEG_SR_OFTF)
#define | JPEG_FLAG_OFNEF ((uint32_t)JPEG_SR_OFNEF)
#define | JPEG_FLAG_EOCF ((uint32_t)JPEG_SR_EOCF)
#define | JPEG_FLAG_HPDF ((uint32_t)JPEG_SR_HPDF)
#define | JPEG_FLAG_COF ((uint32_t)JPEG_SR_COF)
#define | JPEG_FLAG_ALL ((uint32_t)0x000000FEU)

Detailed Description

JPEG Flags definition.

Define Documentation

#define JPEG_FLAG_ALL ((uint32_t)0x000000FEU)

JPEG Codec All previous flag

Definition at line 254 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Init(), JPEG_DMA_ContinueProcess(), JPEG_Init_Process(), and JPEG_Process().

#define JPEG_FLAG_COF ((uint32_t)JPEG_SR_COF)

JPEG Codec operation on going flag

Definition at line 252 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort().

#define JPEG_FLAG_EOCF ((uint32_t)JPEG_SR_EOCF)

JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO

Definition at line 250 of file stm32h7xx_hal_jpeg.h.

Referenced by JPEG_DMA_ContinueProcess(), JPEG_MDMAOutCpltCallback(), and JPEG_Process().

#define JPEG_FLAG_HPDF ((uint32_t)JPEG_SR_HPDF)

JPEG Codec has finished the parsing of the headers and the internal registers have been updated

Definition at line 251 of file stm32h7xx_hal_jpeg.h.

Referenced by JPEG_DMA_ContinueProcess(), and JPEG_Process().

#define JPEG_FLAG_IFNFF ((uint32_t)JPEG_SR_IFNFF)

Input FIFO Not Full Flag, a data can be written

Definition at line 247 of file stm32h7xx_hal_jpeg.h.

Referenced by JPEG_Process().

#define JPEG_FLAG_IFTF ((uint32_t)JPEG_SR_IFTF)

Input FIFO is not full and is bellow its threshold flag

Definition at line 246 of file stm32h7xx_hal_jpeg.h.

Referenced by JPEG_Process().

#define JPEG_FLAG_OFNEF ((uint32_t)JPEG_SR_OFNEF)

Output FIFO is not empty, a data is available

Definition at line 249 of file stm32h7xx_hal_jpeg.h.

Referenced by JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), and JPEG_Process().

#define JPEG_FLAG_OFTF ((uint32_t)JPEG_SR_OFTF)

Output FIFO is not empty and has reach its threshold

Definition at line 248 of file stm32h7xx_hal_jpeg.h.

Referenced by JPEG_Process().

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STM32H753xx HAL User Manual: JPEG Process Pause Resume definition

Defines
JPEG Process Pause Resume definition
JPEG Exported Constants

JPEG process pause, resume definition. More...

Defines

#define | JPEG_PAUSE_RESUME_INPUT ((uint32_t)0x00000001U)
#define | JPEG_PAUSE_RESUME_OUTPUT ((uint32_t)0x00000002U)
#define | JPEG_PAUSE_RESUME_INPUT_OUTPUT ((uint32_t)0x00000003U)

Detailed Description

JPEG process pause, resume definition.

Define Documentation

#define JPEG_PAUSE_RESUME_INPUT ((uint32_t)0x00000001U)

Pause/Resume Input FIFO Xfer

Definition at line 263 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Pause(), HAL_JPEG_Resume(), and JPEG_ReadInputData().

#define JPEG_PAUSE_RESUME_INPUT_OUTPUT ((uint32_t)0x00000003U)

Pause/Resume Input and Output FIFO Xfer

Definition at line 265 of file stm32h7xx_hal_jpeg.h.

#define JPEG_PAUSE_RESUME_OUTPUT ((uint32_t)0x00000002U)

Pause/Resume Output FIFO Xfer

Definition at line 264 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Pause(), and HAL_JPEG_Resume().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: JPEG Exported Macros

Defines
JPEG Exported Macros
JPEG

Defines

#define | __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_JPEG_STATE_RESET)
Reset JPEG handle state.
#define | __HAL_JPEG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= JPEG_CR_JCEN)
Enable the JPEG peripheral.
#define | __HAL_JPEG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~JPEG_CR_JCEN)
Disable the JPEG peripheral.
#define | __HAL_JPEG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)))
Check the specified JPEG status flag.
#define | __HAL_JPEG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->CFR |= ((__FLAG__) & (JPEG_FLAG_EOCF | JPEG_FLAG_HPDF))))
Clear the specified JPEG status flag.
#define | __HAL_JPEG_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) )
Enable Interrupt.
#define | __HAL_JPEG_DISABLE_IT(__HANDLE__, __INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0)
Disable Interrupt.
#define | __HAL_JPEG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
Get Interrupt state.

Define Documentation

#define __HAL_JPEG_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->CFR |= ((__FLAG__) & (JPEG_FLAG_EOCF | JPEG_FLAG_HPDF))))

Clear the specified JPEG status flag.

Parameters:
__HANDLE__,: specifies the JPEG handle.
__FLAG__ : specifies the flag to clear This parameter can be one of the following values:
  • JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO
  • JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers
Return values:
: None

Definition at line 332 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Init(), JPEG_DMA_ContinueProcess(), JPEG_Init_Process(), and JPEG_Process().

#define __HAL_JPEG_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~JPEG_CR_JCEN)

Disable the JPEG peripheral.

Parameters:
__HANDLE__,: specifies the JPEG handle.
Return values:
None

Definition at line 298 of file stm32h7xx_hal_jpeg.h.

#define __HAL_JPEG_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0)

Disable Interrupt.

Parameters:
__HANDLE__,: specifies the JPEG handle.
__INTERRUPT__ : specifies the interrupt to disable This parameter can be one of the following values:
  • JPEG_IT_IFT : Input FIFO Threshold Interrupt
  • JPEG_IT_IFNF : Input FIFO Not Full Interrupt
  • JPEG_IT_OFT : Output FIFO Threshold Interrupt
  • JPEG_IT_OFNE : Output FIFO Not empty Interrupt
  • JPEG_IT_EOC : End of Conversion Interrupt
  • JPEG_IT_HPD : Header Parsing Done Interrupt
Note:
: To disable an IT we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits located in the same IT enable register (CR register).
Return values:
: No retrun

Definition at line 367 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Init(), HAL_JPEG_Pause(), JPEG_DMA_ContinueProcess(), JPEG_Init_Process(), JPEG_MDMAErrorCallback(), JPEG_MDMAInCpltCallback(), JPEG_MDMAOutCpltCallback(), and JPEG_Process().

#define __HAL_JPEG_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= JPEG_CR_JCEN)

Enable the JPEG peripheral.

Parameters:
__HANDLE__,: specifies the JPEG handle.
Return values:
None

Definition at line 291 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Init().

#define __HAL_JPEG_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) )

Enable Interrupt.

Parameters:
__HANDLE__,: specifies the JPEG handle.
__INTERRUPT__ : specifies the interrupt to enable This parameter can be one of the following values:
  • JPEG_IT_IFT : Input FIFO Threshold Interrupt
  • JPEG_IT_IFNF : Input FIFO Not Full Interrupt
  • JPEG_IT_OFT : Output FIFO Threshold Interrupt
  • JPEG_IT_OFNE : Output FIFO Not empty Interrupt
  • JPEG_IT_EOC : End of Conversion Interrupt
  • JPEG_IT_HPD : Header Parsing Done Interrupt
Return values:
: No retrun

Definition at line 349 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Resume(), JPEG_Init_Process(), JPEG_MDMAInCpltCallback(), and JPEG_MDMAOutCpltCallback().

#define __HAL_JPEG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)))

Check the specified JPEG status flag.

Parameters:
__HANDLE__,: specifies the JPEG handle.
__FLAG__ : specifies the flag to check This parameter can be one of the following values:
  • JPEG_FLAG_IFTF : The input FIFO is not full and is bellow its threshold flag
  • JPEG_FLAG_IFNFF : The input FIFO Not Full Flag, a data can be written
  • JPEG_FLAG_OFTF : The output FIFO is not empty and has reach its threshold
  • JPEG_FLAG_OFNEF : The output FIFO is not empty, a data is available
  • JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO
  • JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers and the internal registers have been updated
  • JPEG_FLAG_COF : JPEG Codec operation on going flag
Return values:
: __HAL_JPEG_GET_FLAG : returns The new state of __FLAG__ (TRUE or FALSE)

Definition at line 319 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Abort(), JPEG_DMA_ContinueProcess(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_MDMAOutCpltCallback(), and JPEG_Process().

#define __HAL_JPEG_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR & (__INTERRUPT__))

Get Interrupt state.

Parameters:
__HANDLE__,: specifies the JPEG handle.
__INTERRUPT__ : specifies the interrupt to check This parameter can be one of the following values:
  • JPEG_IT_IFT : Input FIFO Threshold Interrupt
  • JPEG_IT_IFNF : Input FIFO Not Full Interrupt
  • JPEG_IT_OFT : Output FIFO Threshold Interrupt
  • JPEG_IT_OFNE : Output FIFO Not empty Interrupt
  • JPEG_IT_EOC : End of Conversion Interrupt
  • JPEG_IT_HPD : Header Parsing Done Interrupt
Return values:
: returns The new state of __INTERRUPT__ (Enabled or disabled)

Definition at line 384 of file stm32h7xx_hal_jpeg.h.

#define __HAL_JPEG_RESET_HANDLE_STATE ( __HANDLE__ ) ( (__HANDLE__)->State = HAL_JPEG_STATE_RESET)

Reset JPEG handle state.

Parameters:
__HANDLE__,: specifies the JPEG handle.
Return values:
None

Definition at line 283 of file stm32h7xx_hal_jpeg.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: JPEG_ACHuffTableTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
JPEG_ACHuffTableTypeDef Struct Reference
JPEG Private Types

Data Fields

uint8_t | Bits [16]
uint8_t | HuffVal [162]

Detailed Description

Definition at line 242 of file stm32h7xx_hal_jpeg.c.

Field Documentation

uint8_t JPEG_ACHuffTableTypeDef::Bits[16]

bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C

Definition at line 245 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_ACHuff_BitsVals_To_SizeCodes(), and JPEG_Set_Huff_DHTMem().

uint8_t JPEG_ACHuffTableTypeDef::HuffVal[162]

The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C

Definition at line 247 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_ACHuff_BitsVals_To_SizeCodes(), and JPEG_Set_Huff_DHTMem().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_jpeg.c
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: JPEG_DCHuffTableTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
JPEG_DCHuffTableTypeDef Struct Reference
JPEG Private Types

Data Fields

uint8_t | Bits [16]
uint8_t | HuffVal [12]

Detailed Description

Definition at line 252 of file stm32h7xx_hal_jpeg.c.

Field Documentation

uint8_t JPEG_DCHuffTableTypeDef::Bits[16]

bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C

Definition at line 255 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_DCHuff_BitsVals_To_SizeCodes(), and JPEG_Set_Huff_DHTMem().

uint8_t JPEG_DCHuffTableTypeDef::HuffVal[12]

The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C

Definition at line 257 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_DCHuff_BitsVals_To_SizeCodes(), and JPEG_Set_Huff_DHTMem().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_jpeg.c
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: JPEG_AC_HuffCodeTableTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
JPEG_AC_HuffCodeTableTypeDef Struct Reference
JPEG Private Types

Data Fields

uint8_t | CodeLength [JPEG_AC_HUFF_TABLE_SIZE]
uint32_t | HuffmanCode [JPEG_AC_HUFF_TABLE_SIZE]

Detailed Description

Definition at line 262 of file stm32h7xx_hal_jpeg.c.

Field Documentation

uint8_t JPEG_AC_HuffCodeTableTypeDef::CodeLength[JPEG_AC_HUFF_TABLE_SIZE]

Code length

Definition at line 264 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_ACHuff_BitsVals_To_SizeCodes(), and JPEG_Set_HuffAC_Mem().

uint32_t JPEG_AC_HuffCodeTableTypeDef::HuffmanCode[JPEG_AC_HUFF_TABLE_SIZE]

HuffmanCode

Definition at line 266 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_ACHuff_BitsVals_To_SizeCodes(), and JPEG_Set_HuffAC_Mem().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_jpeg.c
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: JPEG_DC_HuffCodeTableTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
JPEG_DC_HuffCodeTableTypeDef Struct Reference
JPEG Private Types

Data Fields

uint8_t | CodeLength [JPEG_DC_HUFF_TABLE_SIZE]
uint32_t | HuffmanCode [JPEG_DC_HUFF_TABLE_SIZE]

Detailed Description

Definition at line 270 of file stm32h7xx_hal_jpeg.c.

Field Documentation

uint8_t JPEG_DC_HuffCodeTableTypeDef::CodeLength[JPEG_DC_HUFF_TABLE_SIZE]

Code length

Definition at line 272 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_DCHuff_BitsVals_To_SizeCodes(), and JPEG_Set_HuffDC_Mem().

uint32_t JPEG_DC_HuffCodeTableTypeDef::HuffmanCode[JPEG_DC_HUFF_TABLE_SIZE]

HuffmanCode

Definition at line 274 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_DCHuff_BitsVals_To_SizeCodes(), and JPEG_Set_HuffDC_Mem().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_jpeg.c
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: JPEG Private Defines

JPEG Private Defines
JPEG
Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: JPEG Private Variables

Variables
JPEG Private Variables
JPEG

Variables

static const
JPEG_DCHuffTableTypeDef 		JPEG_DCLUM_HuffTable
static const
JPEG_DCHuffTableTypeDef 		JPEG_DCCHROM_HuffTable
static const
JPEG_ACHuffTableTypeDef 		JPEG_ACLUM_HuffTable
static const
JPEG_ACHuffTableTypeDef 		JPEG_ACCHROM_HuffTable
static const uint8_t | JPEG_LUM_QuantTable [JPEG_QUANT_TABLE_SIZE]
static const uint8_t | JPEG_CHROM_QuantTable [JPEG_QUANT_TABLE_SIZE]
static const uint8_t | JPEG_ZIGZAG_ORDER [JPEG_QUANT_TABLE_SIZE]

Variable Documentation

const JPEG_ACHuffTableTypeDef JPEG_ACCHROM_HuffTable [static]
Initial value:
{
  { 0, 2, 1, 2, 4, 4, 3, 4, 7, 5, 4, 4, 0, 1, 2, 0x77 },

  {   0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21,
      0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71,
      0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91,
      0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33, 0x52, 0xf0,
      0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24, 0x34,
      0xe1, 0x25, 0xf1, 0x17, 0x18, 0x19, 0x1a, 0x26,
      0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37, 0x38,
      0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48,
      0x49, 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,
      0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
      0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
      0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
      0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96,
      0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5,
      0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4,
      0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3,
      0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2,
      0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda,
      0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9,
      0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
      0xf9, 0xfa }
}

Definition at line 329 of file stm32h7xx_hal_jpeg.c.

const JPEG_ACHuffTableTypeDef JPEG_ACLUM_HuffTable [static]
Initial value:
{
  { 0, 2, 1, 3, 3, 2, 4, 3, 5, 5, 4, 4, 0, 0, 1, 0x7d },

  {   0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12,
      0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07,
      0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08,
      0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0,
      0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16,
      0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28,
      0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
      0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,
      0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59,
      0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69,
      0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79,
      0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89,
      0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98,
      0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
      0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6,
      0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5,
      0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4,
      0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2,
      0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea,
      0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
      0xf9, 0xfa }
}

Definition at line 302 of file stm32h7xx_hal_jpeg.c.

const uint8_t JPEG_CHROM_QuantTable[JPEG_QUANT_TABLE_SIZE] [static]
Initial value:

{
  17,  18,  24,  47,  99,  99,  99,  99,
  18,  21,  26,  66,  99,  99,  99,  99,
  24,  26,  56,  99,  99,  99,  99,  99,
  47,  66,  99,  99,  99,  99,  99,  99,
  99,  99,  99,  99,  99,  99,  99,  99,
  99,  99,  99,  99,  99,  99,  99,  99,
  99,  99,  99,  99,  99,  99,  99,  99,
  99,  99,  99,  99,  99,  99,  99,  99
}

Definition at line 371 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Init().

const JPEG_DCHuffTableTypeDef JPEG_DCCHROM_HuffTable [static]
Initial value:
{
  { 0, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },

  { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb }
}

Definition at line 295 of file stm32h7xx_hal_jpeg.c.

const JPEG_DCHuffTableTypeDef JPEG_DCLUM_HuffTable [static]
Initial value:
{
  { 0, 1, 5, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },

  { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb }

}

Definition at line 287 of file stm32h7xx_hal_jpeg.c.

const uint8_t JPEG_LUM_QuantTable[JPEG_QUANT_TABLE_SIZE] [static]
Initial value:

{
  16,  11,  10,  16,  24,  40,  51,  61,
  12,  12,  14,  19,  26,  58,  60,  55,
  14,  13,  16,  24,  40,  57,  69,  56,
  14,  17,  22,  29,  51,  87,  80,  62,
  18,  22,  37,  56,  68, 109, 103,  77,
  24,  35,  55,  64,  81, 104, 113,  92,
  49,  64,  78,  87, 103, 121, 120, 101,
  72,  92,  95,  98, 112, 100, 103,  99
}

Definition at line 360 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Init(), and JPEG_GetQuality().

const uint8_t JPEG_ZIGZAG_ORDER[JPEG_QUANT_TABLE_SIZE] [static]
Initial value:
{
   0,   1,   8,  16,   9,   2,   3,  10,
  17,  24,  32,  25,  18,  11,   4,   5,
  12,  19,  26,  33,  40,  48,  41,  34,
  27,  20,  13,   6,   7,  14,  21,  28,
  35,  42,  49,  56,  57,  50,  43,  36,
  29,  22,  15,  23,  30,  37,  44,  51,
  58,  59,  52,  45,  38,  31,  39,  46,
  53,  60,  61,  54,  47,  55,  62,  63
}

Definition at line 383 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_GetQuality(), and JPEG_Set_Quantization_Mem().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: JPEG Private Constants

Defines
JPEG Private Constants
JPEG

Defines

#define | JPEG_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */
#define | JPEG_AC_HUFF_TABLE_SIZE ((uint32_t)162U) /* Huffman AC table size : 162 codes*/
#define | JPEG_DC_HUFF_TABLE_SIZE ((uint32_t)12U) /* Huffman AC table size : 12 codes*/
#define | JPEG_FIFO_SIZE ((uint32_t)16U) /* JPEG Input/Output HW FIFO size in words*/
#define | JPEG_FIFO_TH_SIZE ((uint32_t)8U) /* JPEG Input/Output HW FIFO Threshold in words*/
#define | JPEG_INTERRUPT_MASK ((uint32_t)0x0000007EU) /* JPEG Interrupt Mask*/
#define | JPEG_CONTEXT_ENCODE ((uint32_t)0x00000001U) /* JPEG context : operation is encoding*/
#define | JPEG_CONTEXT_DECODE ((uint32_t)0x00000002U) /* JPEG context : operation is decoding*/
#define | JPEG_CONTEXT_OPERATION_MASK ((uint32_t)0x00000003U) /* JPEG context : operation Mask */
#define | JPEG_CONTEXT_POLLING ((uint32_t)0x00000004U) /* JPEG context : Transfer use Polling */
#define | JPEG_CONTEXT_IT ((uint32_t)0x00000008U) /* JPEG context : Transfer use Interrupt */
#define | JPEG_CONTEXT_DMA ((uint32_t)0x0000000CU) /* JPEG context : Transfer use DMA */
#define | JPEG_CONTEXT_METHOD_MASK ((uint32_t)0x0000000CU) /* JPEG context : Transfer Mask */
#define | JPEG_CONTEXT_CONF_ENCODING ((uint32_t)0x00000100U) /* JPEG context : encoding config done */
#define | JPEG_CONTEXT_PAUSE_INPUT ((uint32_t)0x00001000U) /* JPEG context : Pause Input */
#define | JPEG_CONTEXT_PAUSE_OUTPUT ((uint32_t)0x00002000U) /* JPEG context : Pause Output */
#define | JPEG_CONTEXT_CUSTOM_TABLES ((uint32_t)0x00004000U) /* JPEG context : Use custom quantization tables */
#define | JPEG_CONTEXT_ENDING_DMA ((uint32_t)0x00008000U) /* JPEG context : ending with DMA in progress */
#define | JPEG_PROCESS_ONGOING ((uint32_t)0x00000000U) /* Process is on going */
#define | JPEG_PROCESS_DONE ((uint32_t)0x00000001U) /* Process is done (ends) */

Define Documentation

#define JPEG_AC_HUFF_TABLE_SIZE ((uint32_t)162U) /* Huffman AC table size : 162 codes*/

Definition at line 200 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_ACHuff_BitsVals_To_SizeCodes(), and JPEG_Set_HuffAC_Mem().

#define JPEG_CONTEXT_CONF_ENCODING ((uint32_t)0x00000100U) /* JPEG context : encoding config done */

Definition at line 218 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_ConfigEncoding(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), and JPEG_Process().

#define JPEG_CONTEXT_CUSTOM_TABLES ((uint32_t)0x00004000U) /* JPEG context : Use custom quantization tables */

Definition at line 223 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_ConfigEncoding(), HAL_JPEG_SetUserQuantTables(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), and JPEG_Process().

#define JPEG_CONTEXT_DECODE ((uint32_t)0x00000002U) /* JPEG context : operation is decoding*/

Definition at line 209 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), JPEG_DMA_ContinueProcess(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_Init_Process(), and JPEG_Process().

#define JPEG_CONTEXT_DMA ((uint32_t)0x0000000CU) /* JPEG context : Transfer use DMA */

Definition at line 214 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Encode_DMA(), HAL_JPEG_IRQHandler(), HAL_JPEG_Pause(), HAL_JPEG_Resume(), JPEG_Init_Process(), JPEG_MDMAInCpltCallback(), and JPEG_MDMAOutCpltCallback().

#define JPEG_CONTEXT_ENCODE ((uint32_t)0x00000001U) /* JPEG context : operation is encoding*/

Definition at line 208 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_Init_Process(), and JPEG_Process().

#define JPEG_CONTEXT_ENDING_DMA ((uint32_t)0x00008000U) /* JPEG context : ending with DMA in progress */

Definition at line 225 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Resume(), JPEG_DMA_ContinueProcess(), JPEG_MDMAInCpltCallback(), JPEG_MDMAOutAbortCallback(), and JPEG_MDMAOutCpltCallback().

#define JPEG_CONTEXT_IT ((uint32_t)0x00000008U) /* JPEG context : Transfer use Interrupt */

Definition at line 213 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Decode_IT(), HAL_JPEG_Encode_IT(), HAL_JPEG_IRQHandler(), HAL_JPEG_Pause(), HAL_JPEG_Resume(), JPEG_Init_Process(), and JPEG_Process().

#define JPEG_CONTEXT_METHOD_MASK ((uint32_t)0x0000000CU) /* JPEG context : Transfer Mask */

Definition at line 215 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), HAL_JPEG_IRQHandler(), HAL_JPEG_Pause(), HAL_JPEG_Resume(), JPEG_Init_Process(), JPEG_MDMAInCpltCallback(), JPEG_MDMAOutCpltCallback(), and JPEG_Process().

#define JPEG_CONTEXT_OPERATION_MASK ((uint32_t)0x00000003U) /* JPEG context : operation Mask */

Definition at line 210 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), JPEG_DMA_ContinueProcess(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_Init_Process(), and JPEG_Process().

#define JPEG_CONTEXT_PAUSE_INPUT ((uint32_t)0x00001000U) /* JPEG context : Pause Input */

Definition at line 220 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Pause(), HAL_JPEG_Resume(), JPEG_Init_Process(), JPEG_MDMAInCpltCallback(), JPEG_Process(), and JPEG_ReadInputData().

#define JPEG_CONTEXT_PAUSE_OUTPUT ((uint32_t)0x00002000U) /* JPEG context : Pause Output */

Definition at line 221 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Pause(), HAL_JPEG_Resume(), JPEG_DMA_EndProcess(), JPEG_DMA_PollResidualData(), JPEG_Init_Process(), JPEG_MDMAOutCpltCallback(), and JPEG_Process().

#define JPEG_CONTEXT_POLLING ((uint32_t)0x00000004U) /* JPEG context : Transfer use Polling */

Definition at line 212 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Decode(), and HAL_JPEG_Encode().

#define JPEG_DC_HUFF_TABLE_SIZE ((uint32_t)12U) /* Huffman AC table size : 12 codes*/

Definition at line 201 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_DCHuff_BitsVals_To_SizeCodes(), and JPEG_Set_HuffDC_Mem().

#define JPEG_FIFO_SIZE ((uint32_t)16U) /* JPEG Input/Output HW FIFO size in words*/

Definition at line 203 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_DMA_PollResidualData().

#define JPEG_FIFO_TH_SIZE ((uint32_t)8U) /* JPEG Input/Output HW FIFO Threshold in words*/

Definition at line 204 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_Process().

#define JPEG_INTERRUPT_MASK ((uint32_t)0x0000007EU) /* JPEG Interrupt Mask*/

Definition at line 206 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Abort(), HAL_JPEG_Init(), JPEG_DMA_ContinueProcess(), JPEG_Init_Process(), JPEG_MDMAErrorCallback(), JPEG_MDMAInCpltCallback(), JPEG_MDMAOutCpltCallback(), and JPEG_Process().

#define JPEG_PROCESS_DONE ((uint32_t)0x00000001U) /* Process is done (ends) */

Definition at line 228 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_DMA_EndProcess(), and JPEG_Process().

#define JPEG_PROCESS_ONGOING ((uint32_t)0x00000000U) /* Process is on going */

Definition at line 227 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Decode(), HAL_JPEG_Encode(), JPEG_DMA_ContinueProcess(), JPEG_DMA_EndProcess(), and JPEG_Process().

#define JPEG_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */

Definition at line 199 of file stm32h7xx_hal_jpeg.c.

Referenced by HAL_JPEG_Abort().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: JPEG Private Macros

Defines
JPEG Private Macros
JPEG

Defines

#define | IS_JPEG_CHROMASUBSAMPLING(SUBSAMPLING)
#define | IS_JPEG_IMAGE_QUALITY(NUMBER) (((NUMBER) >= JPEG_IMAGE_QUALITY_MIN) && ((NUMBER) <= JPEG_IMAGE_QUALITY_MAX))
#define | IS_JPEG_COLORSPACE(COLORSPACE)
#define | IS_JPEG_PAUSE_RESUME_STATE(VALUE)

Define Documentation

#define IS_JPEG_CHROMASUBSAMPLING ( SUBSAMPLING )
Value:
(((SUBSAMPLING) == JPEG_444_SUBSAMPLING) || \
                                                ((SUBSAMPLING) == JPEG_420_SUBSAMPLING) || \
                                                ((SUBSAMPLING) == JPEG_422_SUBSAMPLING))

Definition at line 523 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding().

#define IS_JPEG_COLORSPACE ( COLORSPACE )
Value:
(((COLORSPACE) == JPEG_GRAYSCALE_COLORSPACE) || \
                                        ((COLORSPACE) == JPEG_YCBCR_COLORSPACE)     || \
                                        ((COLORSPACE) == JPEG_CMYK_COLORSPACE))

Definition at line 529 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding().

#define IS_JPEG_IMAGE_QUALITY ( NUMBER ) (((NUMBER) >= JPEG_IMAGE_QUALITY_MIN) && ((NUMBER) <= JPEG_IMAGE_QUALITY_MAX))

Definition at line 527 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_ConfigEncoding().

#define IS_JPEG_PAUSE_RESUME_STATE ( VALUE )
Value:
(((VALUE) == JPEG_PAUSE_RESUME_INPUT) || \
                                           ((VALUE) == JPEG_PAUSE_RESUME_OUTPUT)|| \
                                           ((VALUE) == JPEG_PAUSE_RESUME_INPUT_OUTPUT))

Definition at line 533 of file stm32h7xx_hal_jpeg.h.

Referenced by HAL_JPEG_Pause(), and HAL_JPEG_Resume().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: JPEG Private Functions Prototypes

JPEG Private Functions Prototypes
JPEG
Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: JPEG Private Functions

Functions
JPEG Private Functions
JPEG | MDMA

Functions

static HAL_StatusTypeDef | JPEG_Bits_To_SizeCodes (uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK)
Generates Huffman sizes/Codes Table from Bits/vals Table.
static HAL_StatusTypeDef | JPEG_ACHuff_BitsVals_To_SizeCodes (JPEG_ACHuffTableTypeDef *AC_BitsValsTable, JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable)
Transform a Bits/Vals AC Huffman table to sizes/Codes huffman Table that can programmed to the JPEG encoder registers.
static HAL_StatusTypeDef | JPEG_DCHuff_BitsVals_To_SizeCodes (JPEG_DCHuffTableTypeDef *DC_BitsValsTable, JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable)
Transform a Bits/Vals DC Huffman table to sizes/Codes huffman Table that can programmed to the JPEG encoder registers.
static HAL_StatusTypeDef | JPEG_Set_HuffDC_Mem (JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, __IO uint32_t *DCTableAddress)
Set the JPEG register with an DC huffman table at the given DC table address.
static HAL_StatusTypeDef | JPEG_Set_HuffAC_Mem (JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, __IO uint32_t *ACTableAddress)
Set the JPEG register with an AC huffman table at the given AC table address.
static HAL_StatusTypeDef | JPEG_Set_HuffEnc_Mem (JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0, JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1)
Configure the JPEG encoder register huffman tables to used during the encdoing operation.
static void | JPEG_Set_Huff_DHTMem (JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0, JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1)
Configure the JPEG register huffman tables to be included in the JPEG file header (used for encoding only)
static HAL_StatusTypeDef | JPEG_Set_Quantization_Mem (JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, __IO uint32_t *QTableAddress)
Configure the JPEG registers with a given quantization table.
static void | JPEG_SetColorYCBCR (JPEG_HandleTypeDef *hjpeg)
Configure the JPEG registers for YCbCr color space.
static void | JPEG_SetColorGrayScale (JPEG_HandleTypeDef *hjpeg)
Configure the JPEG registers for GrayScale color space.
static void | JPEG_SetColorCMYK (JPEG_HandleTypeDef *hjpeg)
Configure the JPEG registers for CMYK color space.
static void | JPEG_Init_Process (JPEG_HandleTypeDef *hjpeg)
Init the JPEG encoding/decoding process in case of Polling or Interrupt and DMA.
static uint32_t | JPEG_Process (JPEG_HandleTypeDef *hjpeg)
JPEG encoding/decoding process in case of Polling or Interrupt.
static void | JPEG_StoreOutputData (JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords)
Store some output data from the JPEG peripheral to the output buffer.
static void | JPEG_ReadInputData (JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords)
Read some input Data from the input buffer.
static HAL_StatusTypeDef | JPEG_DMA_StartProcess (JPEG_HandleTypeDef *hjpeg)
Start the JPEG DMA process (encoding/decoding)
static uint32_t | JPEG_DMA_ContinueProcess (JPEG_HandleTypeDef *hjpeg)
Continue the current JPEG DMA process (encoding/decoding)
static uint32_t | JPEG_DMA_EndProcess (JPEG_HandleTypeDef *hjpeg)
Finalize the current JPEG DMA process (encoding/decoding)
static void | JPEG_DMA_PollResidualData (JPEG_HandleTypeDef *hjpeg)
Poll residual output data when DMA process (encoding/decoding)
static void | JPEG_MDMAInCpltCallback (MDMA_HandleTypeDef *hmdma)
DMA input transfer complete callback.
static void | JPEG_MDMAOutCpltCallback (MDMA_HandleTypeDef *hmdma)
DMA output transfer complete callback.
static void | JPEG_MDMAErrorCallback (MDMA_HandleTypeDef *hmdma)
DMA Transfer error callback.
static void | JPEG_MDMAOutAbortCallback (MDMA_HandleTypeDef *hmdma)
DMA output Abort callback.
static uint32_t | JPEG_GetQuality (JPEG_HandleTypeDef *hjpeg)
Calculate the decoded image quality (from 1 to 100)
static void | MDMA_SetConfig (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
Sets the MDMA Transfer parameter.

Function Documentation

static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes | ( | JPEG_ACHuffTableTypeDef * | AC_BitsValsTable,
 |  | JPEG_AC_HuffCodeTableTypeDef * | AC_SizeCodesTable
 | ) |  | [static]

Transform a Bits/Vals AC Huffman table to sizes/Codes huffman Table that can programmed to the JPEG encoder registers.

Parameters:
AC_BitsValsTable,: pointer to AC huffman bits/vals table
AC_SizeCodesTable,: pointer to AC huffman Sizes/Codes table
Return values:
HAL status

Definition at line 2034 of file stm32h7xx_hal_jpeg.c.

References JPEG_ACHuffTableTypeDef::Bits, JPEG_AC_HuffCodeTableTypeDef::CodeLength, JPEG_AC_HuffCodeTableTypeDef::HuffmanCode, JPEG_ACHuffTableTypeDef::HuffVal, JPEG_AC_HUFF_TABLE_SIZE, and JPEG_Bits_To_SizeCodes().

Referenced by JPEG_Set_HuffAC_Mem().

static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes | ( | uint8_t * | Bits,
 |  | uint8_t * | Huffsize,
 |  | uint32_t * | Huffcode,
 |  | uint32_t * | LastK
 | ) |  | [static]

Generates Huffman sizes/Codes Table from Bits/vals Table.

Parameters:
Bits,: pointer to bits table
Huffsize,: pointer to sizes table
Huffcode,: pointer to codes table
LastK,: pointer to last Coeff (table dimmension)
Return values:
HAL status

Definition at line 1982 of file stm32h7xx_hal_jpeg.c.

Referenced by JPEG_ACHuff_BitsVals_To_SizeCodes(), and JPEG_DCHuff_BitsVals_To_SizeCodes().

static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes | ( | JPEG_DCHuffTableTypeDef * | DC_BitsValsTable,
 |  | JPEG_DC_HuffCodeTableTypeDef * | DC_SizeCodesTable
 | ) |  | [static]

Transform a Bits/Vals DC Huffman table to sizes/Codes huffman Table that can programmed to the JPEG encoder registers.

Parameters:
DC_BitsValsTable,: pointer to DC huffman bits/vals table
DC_SizeCodesTable,: pointer to DC huffman Sizes/Codes table
Return values:
HAL status

Definition at line 2092 of file stm32h7xx_hal_jpeg.c.

References JPEG_DCHuffTableTypeDef::Bits, JPEG_DC_HuffCodeTableTypeDef::CodeLength, JPEG_DC_HuffCodeTableTypeDef::HuffmanCode, JPEG_DCHuffTableTypeDef::HuffVal, JPEG_Bits_To_SizeCodes(), and JPEG_DC_HUFF_TABLE_SIZE.

Referenced by JPEG_Set_HuffDC_Mem().

static uint32_t JPEG_DMA_ContinueProcess ( JPEG_HandleTypeDef * hjpeg ) [static]

Continue the current JPEG DMA process (encoding/decoding)

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING

Definition at line 3096 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_CLEAR_FLAG, __HAL_JPEG_DISABLE_IT, __HAL_JPEG_GET_FLAG, JPEG_HandleTypeDef::Conf, JPEG_HandleTypeDef::Context, HAL_JPEG_GetInfo(), HAL_JPEG_InfoReadyCallback(), HAL_MDMA_Abort_IT(), HAL_MDMA_STATE_BUSY, JPEG_HandleTypeDef::hdmain, JPEG_HandleTypeDef::hdmaout, JPEG_ConfTypeDef::ImageQuality, JPEG_HandleTypeDef::Instance, JPEG_CONTEXT_DECODE, JPEG_CONTEXT_ENDING_DMA, JPEG_CONTEXT_OPERATION_MASK, JPEG_DMA_EndProcess(), JPEG_FLAG_ALL, JPEG_FLAG_EOCF, JPEG_FLAG_HPDF, JPEG_INTERRUPT_MASK, JPEG_IT_HPD, JPEG_PROCESS_ONGOING, and __MDMA_HandleTypeDef::State.

Referenced by HAL_JPEG_IRQHandler().

static uint32_t JPEG_DMA_EndProcess ( JPEG_HandleTypeDef * hjpeg ) [static]

Finalize the current JPEG DMA process (encoding/decoding)

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
JPEG_PROCESS_DONE

Definition at line 3158 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_GET_FLAG, JPEG_HandleTypeDef::Context, HAL_JPEG_DataReadyCallback(), HAL_JPEG_DecodeCpltCallback(), HAL_JPEG_EncodeCpltCallback(), HAL_JPEG_STATE_READY, JPEG_HandleTypeDef::hdmaout, JPEG_HandleTypeDef::Instance, __MDMA_HandleTypeDef::Instance, JPEG_CONTEXT_CONF_ENCODING, JPEG_CONTEXT_CUSTOM_TABLES, JPEG_CONTEXT_DECODE, JPEG_CONTEXT_ENCODE, JPEG_CONTEXT_OPERATION_MASK, JPEG_CONTEXT_PAUSE_OUTPUT, JPEG_DMA_PollResidualData(), JPEG_FLAG_OFNEF, JPEG_PROCESS_DONE, JPEG_PROCESS_ONGOING, JPEG_HandleTypeDef::JpegOutCount, JPEG_HandleTypeDef::OutDataLength, JPEG_HandleTypeDef::pJpegOutBuffPtr, and JPEG_HandleTypeDef::State.

Referenced by JPEG_DMA_ContinueProcess(), and JPEG_MDMAOutAbortCallback().

static void JPEG_DMA_PollResidualData ( JPEG_HandleTypeDef * hjpeg ) [static]

Poll residual output data when DMA process (encoding/decoding)

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None.

Definition at line 3219 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_GET_FLAG, JPEG_HandleTypeDef::Context, HAL_JPEG_DataReadyCallback(), HAL_JPEG_DecodeCpltCallback(), HAL_JPEG_EncodeCpltCallback(), HAL_JPEG_STATE_READY, JPEG_HandleTypeDef::Instance, JPEG_CONTEXT_CONF_ENCODING, JPEG_CONTEXT_CUSTOM_TABLES, JPEG_CONTEXT_DECODE, JPEG_CONTEXT_ENCODE, JPEG_CONTEXT_OPERATION_MASK, JPEG_CONTEXT_PAUSE_OUTPUT, JPEG_FIFO_SIZE, JPEG_FLAG_OFNEF, JPEG_HandleTypeDef::JpegOutCount, JPEG_HandleTypeDef::OutDataLength, JPEG_HandleTypeDef::pJpegOutBuffPtr, and JPEG_HandleTypeDef::State.

Referenced by HAL_JPEG_Resume(), and JPEG_DMA_EndProcess().

static HAL_StatusTypeDef JPEG_DMA_StartProcess ( JPEG_HandleTypeDef * hjpeg ) [static]

Start the JPEG DMA process (encoding/decoding)

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING

Definition at line 3040 of file stm32h7xx_hal_jpeg.c.

References MDMA_InitTypeDef::BufferTransferLength, HAL_MDMA_Start_IT(), JPEG_HandleTypeDef::hdmain, JPEG_HandleTypeDef::hdmaout, JPEG_HandleTypeDef::InDataLength, __MDMA_HandleTypeDef::Init, JPEG_HandleTypeDef::Instance, JPEG_MDMAErrorCallback(), JPEG_MDMAInCpltCallback(), JPEG_MDMAOutAbortCallback(), JPEG_MDMAOutCpltCallback(), JPEG_HandleTypeDef::OutDataLength, JPEG_HandleTypeDef::pJpegInBuffPtr, JPEG_HandleTypeDef::pJpegOutBuffPtr, __MDMA_HandleTypeDef::XferAbortCallback, __MDMA_HandleTypeDef::XferCpltCallback, and __MDMA_HandleTypeDef::XferErrorCallback.

Referenced by HAL_JPEG_Decode_DMA(), and HAL_JPEG_Encode_DMA().

static uint32_t JPEG_GetQuality ( JPEG_HandleTypeDef * hjpeg ) [static]

Calculate the decoded image quality (from 1 to 100)

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
JPEG image quality from 1 to 100.

Definition at line 3408 of file stm32h7xx_hal_jpeg.c.

References JPEG_HandleTypeDef::Instance, JPEG_LUM_QuantTable, JPEG_QUANT_TABLE_SIZE, and JPEG_ZIGZAG_ORDER.

Referenced by HAL_JPEG_GetInfo().

static void JPEG_Init_Process ( JPEG_HandleTypeDef * hjpeg ) [static]

Init the JPEG encoding/decoding process in case of Polling or Interrupt and DMA.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 2725 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_CLEAR_FLAG, __HAL_JPEG_DISABLE_IT, __HAL_JPEG_ENABLE_IT, JPEG_HandleTypeDef::Context, JPEG_HandleTypeDef::Instance, JPEG_CONTEXT_DECODE, JPEG_CONTEXT_DMA, JPEG_CONTEXT_ENCODE, JPEG_CONTEXT_IT, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_OPERATION_MASK, JPEG_CONTEXT_PAUSE_INPUT, JPEG_CONTEXT_PAUSE_OUTPUT, JPEG_FLAG_ALL, JPEG_INTERRUPT_MASK, JPEG_IT_EOC, JPEG_IT_HPD, JPEG_IT_IFNF, JPEG_IT_IFT, JPEG_IT_OFNE, and JPEG_IT_OFT.

Referenced by HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), and HAL_JPEG_Encode_IT().

static void JPEG_MDMAErrorCallback ( MDMA_HandleTypeDef * hmdma ) [static]

DMA Transfer error callback.

Parameters:
hmdma,: pointer to a DMA_HandleTypeDef structure.
Return values:
None

Definition at line 3372 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_DISABLE_IT, JPEG_HandleTypeDef::ErrorCode, HAL_JPEG_ERROR_DMA, HAL_JPEG_ErrorCallback(), HAL_JPEG_STATE_READY, JPEG_HandleTypeDef::Instance, JPEG_INTERRUPT_MASK, and JPEG_HandleTypeDef::State.

Referenced by JPEG_DMA_StartProcess().

static void JPEG_MDMAInCpltCallback ( MDMA_HandleTypeDef * hmdma ) [static]

DMA input transfer complete callback.

Parameters:
hmdma,: pointer to a DMA_HandleTypeDef structure.
Return values:
None

Definition at line 3281 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_DISABLE_IT, __HAL_JPEG_ENABLE_IT, MDMA_InitTypeDef::BufferTransferLength, JPEG_HandleTypeDef::Context, HAL_JPEG_GetDataCallback(), HAL_MDMA_Start_IT(), JPEG_HandleTypeDef::hdmain, JPEG_HandleTypeDef::InDataLength, __MDMA_HandleTypeDef::Init, JPEG_HandleTypeDef::Instance, __MDMA_HandleTypeDef::Instance, JPEG_CONTEXT_DMA, JPEG_CONTEXT_ENDING_DMA, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_PAUSE_INPUT, JPEG_INTERRUPT_MASK, JPEG_IT_EOC, JPEG_IT_HPD, JPEG_HandleTypeDef::JpegInCount, and JPEG_HandleTypeDef::pJpegInBuffPtr.

Referenced by JPEG_DMA_StartProcess().

static void JPEG_MDMAOutAbortCallback ( MDMA_HandleTypeDef * hmdma ) [static]

DMA output Abort callback.

Parameters:
hmdma,: pointer to a DMA_HandleTypeDef structure.
Return values:
None

Definition at line 3392 of file stm32h7xx_hal_jpeg.c.

References JPEG_HandleTypeDef::Context, JPEG_CONTEXT_ENDING_DMA, and JPEG_DMA_EndProcess().

Referenced by JPEG_DMA_StartProcess().

static void JPEG_MDMAOutCpltCallback ( MDMA_HandleTypeDef * hmdma ) [static]

DMA output transfer complete callback.

Parameters:
hmdma,: pointer to a DMA_HandleTypeDef structure.
Return values:
None

Definition at line 3338 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_DISABLE_IT, __HAL_JPEG_ENABLE_IT, __HAL_JPEG_GET_FLAG, JPEG_HandleTypeDef::Context, HAL_JPEG_DataReadyCallback(), HAL_MDMA_Start_IT(), JPEG_HandleTypeDef::hdmaout, JPEG_HandleTypeDef::Instance, __MDMA_HandleTypeDef::Instance, JPEG_CONTEXT_DMA, JPEG_CONTEXT_ENDING_DMA, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_PAUSE_OUTPUT, JPEG_FLAG_EOCF, JPEG_INTERRUPT_MASK, JPEG_IT_EOC, JPEG_IT_HPD, JPEG_HandleTypeDef::JpegOutCount, JPEG_HandleTypeDef::OutDataLength, and JPEG_HandleTypeDef::pJpegOutBuffPtr.

Referenced by JPEG_DMA_StartProcess().

static uint32_t JPEG_Process ( JPEG_HandleTypeDef * hjpeg ) [static]

JPEG encoding/decoding process in case of Polling or Interrupt.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
JPEG_PROCESS_DONE if the process has ends else JPEG_PROCESS_ONGOING

Definition at line 2776 of file stm32h7xx_hal_jpeg.c.

References __HAL_JPEG_CLEAR_FLAG, __HAL_JPEG_DISABLE_IT, __HAL_JPEG_GET_FLAG, JPEG_HandleTypeDef::Conf, JPEG_HandleTypeDef::Context, HAL_JPEG_DataReadyCallback(), HAL_JPEG_DecodeCpltCallback(), HAL_JPEG_EncodeCpltCallback(), HAL_JPEG_GetInfo(), HAL_JPEG_InfoReadyCallback(), HAL_JPEG_STATE_READY, JPEG_ConfTypeDef::ImageQuality, JPEG_HandleTypeDef::Instance, JPEG_CONTEXT_CONF_ENCODING, JPEG_CONTEXT_CUSTOM_TABLES, JPEG_CONTEXT_DECODE, JPEG_CONTEXT_ENCODE, JPEG_CONTEXT_IT, JPEG_CONTEXT_METHOD_MASK, JPEG_CONTEXT_OPERATION_MASK, JPEG_CONTEXT_PAUSE_INPUT, JPEG_CONTEXT_PAUSE_OUTPUT, JPEG_FIFO_TH_SIZE, JPEG_FLAG_ALL, JPEG_FLAG_EOCF, JPEG_FLAG_HPDF, JPEG_FLAG_IFNFF, JPEG_FLAG_IFTF, JPEG_FLAG_OFNEF, JPEG_FLAG_OFTF, JPEG_INTERRUPT_MASK, JPEG_IT_HPD, JPEG_PROCESS_DONE, JPEG_PROCESS_ONGOING, JPEG_ReadInputData(), JPEG_StoreOutputData(), JPEG_HandleTypeDef::JpegOutCount, JPEG_HandleTypeDef::pJpegOutBuffPtr, and JPEG_HandleTypeDef::State.

Referenced by HAL_JPEG_Decode(), HAL_JPEG_Encode(), and HAL_JPEG_IRQHandler().

static void JPEG_ReadInputData | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint32_t | nbRequestWords
 | ) |  | [static]

Read some input Data from the input buffer.

This function is used when the JPEG peripheral needs new data in case of Polling or Interrupt process

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
nbRequestWords,: Number of input words (of 32 bits) that the JPE peripheral request
Return values:
None

Definition at line 2968 of file stm32h7xx_hal_jpeg.c.

References JPEG_HandleTypeDef::Context, HAL_JPEG_GetDataCallback(), HAL_JPEG_Pause(), JPEG_HandleTypeDef::InDataLength, JPEG_HandleTypeDef::Instance, JPEG_CONTEXT_PAUSE_INPUT, JPEG_PAUSE_RESUME_INPUT, JPEG_HandleTypeDef::JpegInCount, and JPEG_HandleTypeDef::pJpegInBuffPtr.

Referenced by JPEG_Process().

static void JPEG_Set_Huff_DHTMem | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | JPEG_ACHuffTableTypeDef * | HuffTableAC0,
 |  | JPEG_DCHuffTableTypeDef * | HuffTableDC0,
 |  | JPEG_ACHuffTableTypeDef * | HuffTableAC1,
 |  | JPEG_DCHuffTableTypeDef * | HuffTableDC1
 | ) |  | [static]

Configure the JPEG register huffman tables to be included in the JPEG file header (used for encoding only)

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
HuffTableAC0,: AC0 huffman table
HuffTableDC0,: DC0 huffman table
HuffTableAC1,: AC1 huffman table
HuffTableDC1,: DC1 huffman table
Return values:
None

Definition at line 2323 of file stm32h7xx_hal_jpeg.c.

References JPEG_ACHuffTableTypeDef::Bits, JPEG_DCHuffTableTypeDef::Bits, JPEG_ACHuffTableTypeDef::HuffVal, JPEG_DCHuffTableTypeDef::HuffVal, and JPEG_HandleTypeDef::Instance.

Referenced by JPEG_Set_HuffEnc_Mem().

static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | JPEG_ACHuffTableTypeDef * | HuffTableAC,
 |  | __IO uint32_t * | ACTableAddress
 | ) |  | [static]

Set the JPEG register with an AC huffman table at the given AC table address.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
HuffTableAC,: pointer to AC huffman table
ACTableAddress,: Encoder AC huffman table address it could be HUFFENC_AC0 or HUFFENC_AC1.
Return values:
HAL status

Definition at line 2193 of file stm32h7xx_hal_jpeg.c.

References JPEG_AC_HuffCodeTableTypeDef::CodeLength, JPEG_AC_HuffCodeTableTypeDef::HuffmanCode, JPEG_HandleTypeDef::Instance, JPEG_AC_HUFF_TABLE_SIZE, and JPEG_ACHuff_BitsVals_To_SizeCodes().

Referenced by JPEG_Set_HuffEnc_Mem().

static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | JPEG_DCHuffTableTypeDef * | HuffTableDC,
 |  | __IO uint32_t * | DCTableAddress
 | ) |  | [static]

Set the JPEG register with an DC huffman table at the given DC table address.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
HuffTableDC,: pointer to DC huffman table
DCTableAddress,: Encoder DC huffman table address it could be HUFFENC_DC0 or HUFFENC_DC1.
Return values:
HAL status

Definition at line 2136 of file stm32h7xx_hal_jpeg.c.

References JPEG_DC_HuffCodeTableTypeDef::CodeLength, JPEG_DC_HuffCodeTableTypeDef::HuffmanCode, JPEG_HandleTypeDef::Instance, JPEG_DC_HUFF_TABLE_SIZE, and JPEG_DCHuff_BitsVals_To_SizeCodes().

Referenced by JPEG_Set_HuffEnc_Mem().

static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | JPEG_ACHuffTableTypeDef * | HuffTableAC0,
 |  | JPEG_DCHuffTableTypeDef * | HuffTableDC0,
 |  | JPEG_ACHuffTableTypeDef * | HuffTableAC1,
 |  | JPEG_DCHuffTableTypeDef * | HuffTableDC1
 | ) |  | [static]

Configure the JPEG encoder register huffman tables to used during the encdoing operation.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
HuffTableAC0,: AC0 huffman table
HuffTableDC0,: DC0 huffman table
HuffTableAC1,: AC1 huffman table
HuffTableDC1,: DC1 huffman table
Return values:
None

Definition at line 2267 of file stm32h7xx_hal_jpeg.c.

References JPEG_HandleTypeDef::Instance, JPEG_Set_Huff_DHTMem(), JPEG_Set_HuffAC_Mem(), and JPEG_Set_HuffDC_Mem().

Referenced by HAL_JPEG_Init().

static HAL_StatusTypeDef JPEG_Set_Quantization_Mem | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint8_t * | QTable,
 |  | __IO uint32_t * | QTableAddress
 | ) |  | [static]

Configure the JPEG registers with a given quantization table.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
QTable,: pointer to an array of 64 bytes giving the quantization table
QTableAddress,: destination quantization address in the JPEG peripheral it could be QMEM0, QMEM1, QMEM2 or QMEM3
Return values:
None

Definition at line 2518 of file stm32h7xx_hal_jpeg.c.

References JPEG_HandleTypeDef::Conf, JPEG_ConfTypeDef::ImageQuality, JPEG_HandleTypeDef::Instance, JPEG_QUANT_TABLE_SIZE, and JPEG_ZIGZAG_ORDER.

Referenced by HAL_JPEG_ConfigEncoding().

static void JPEG_SetColorCMYK ( JPEG_HandleTypeDef * hjpeg ) [static]

Configure the JPEG registers for CMYK color space.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 2666 of file stm32h7xx_hal_jpeg.c.

References JPEG_ConfTypeDef::ChromaSubsampling, JPEG_HandleTypeDef::Conf, JPEG_HandleTypeDef::Instance, JPEG_420_SUBSAMPLING, and JPEG_422_SUBSAMPLING.

Referenced by HAL_JPEG_ConfigEncoding().

static void JPEG_SetColorGrayScale ( JPEG_HandleTypeDef * hjpeg ) [static]

Configure the JPEG registers for GrayScale color space.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 2646 of file stm32h7xx_hal_jpeg.c.

References JPEG_HandleTypeDef::Instance.

Referenced by HAL_JPEG_ConfigEncoding().

static void JPEG_SetColorYCBCR ( JPEG_HandleTypeDef * hjpeg ) [static]

Configure the JPEG registers for YCbCr color space.

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
Return values:
None

Definition at line 2585 of file stm32h7xx_hal_jpeg.c.

References JPEG_ConfTypeDef::ChromaSubsampling, JPEG_HandleTypeDef::Conf, JPEG_HandleTypeDef::Instance, JPEG_420_SUBSAMPLING, and JPEG_422_SUBSAMPLING.

Referenced by HAL_JPEG_ConfigEncoding().

static void JPEG_StoreOutputData | ( | JPEG_HandleTypeDef * | hjpeg,
 |  | uint32_t | nbOutputWords
 | ) |  | [static]

Store some output data from the JPEG peripheral to the output buffer.

This function is used when the JPEG peripheral has new data to output in case of Polling or Interrupt process

Parameters:
hjpeg,: pointer to a JPEG_HandleTypeDef structure that contains the configuration information for JPEG module
nbOutputWords,: Number of output words (of 32 bits) ready from the JPEG peripheral
Return values:
None

Definition at line 2894 of file stm32h7xx_hal_jpeg.c.

References HAL_JPEG_DataReadyCallback(), JPEG_HandleTypeDef::Instance, JPEG_HandleTypeDef::JpegOutCount, JPEG_HandleTypeDef::OutDataLength, and JPEG_HandleTypeDef::pJpegOutBuffPtr.

Referenced by JPEG_Process().

static void MDMA_SetConfig | ( | MDMA_HandleTypeDef * | hmdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | BlockDataLength,
 |  | uint32_t | BlockCount
 | ) |  | [static]

Sets the MDMA Transfer parameter.

Parameters:
hmdma,: pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
BlockDataLength : The length of a block transfer in bytes
BlockCount,: The number of a blocks to be transfer
Return values:
HAL status

Definition at line 1776 of file stm32h7xx_hal_mdma.c.

References __HAL_MDMA_CLEAR_FLAG, __MDMA_HandleTypeDef::FirstLinkedListNodeAddress, __MDMA_HandleTypeDef::Instance, MDMA_FLAG_CTC, and MDMA_FLAG_TE.

Referenced by HAL_MDMA_Start(), and HAL_MDMA_Start_IT().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
LPTIM Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize the LPTIM peripheral.
__weak void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM MSP.
__weak void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize LPTIM MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the LPTIM according to the specified parameters in the
          LPTIM_InitTypeDef and initialize the associated handle.
      (+) DeInitialize the LPTIM peripheral.
      (+) Initialize the LPTIM MSP.
      (+) DeInitialize the LPTIM MSP.

Function Documentation

HAL_StatusTypeDef HAL_LPTIM_DeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitialize the LPTIM peripheral.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL status

Definition at line 290 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, HAL_LPTIM_MspDeInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_RESET, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Init ( LPTIM_HandleTypeDef * hlptim )

Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and creates the associated handle.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL status

Definition at line 175 of file stm32h7xx_hal_lptim.c.

References LPTIM_TriggerConfigTypeDef::ActiveEdge, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_MspInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, LPTIM_HandleTypeDef::Init, LPTIM_InitTypeDef::Input1Source, LPTIM_InitTypeDef::Input2Source, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_CLOCK_PRESCALER, IS_LPTIM_CLOCK_SAMPLE_TIME, IS_LPTIM_CLOCK_SOURCE, IS_LPTIM_COUNTER_SOURCE, IS_LPTIM_EXT_TRG_POLARITY, IS_LPTIM_INPUT1_SOURCE, IS_LPTIM_INPUT2_SOURCE, IS_LPTIM_OUTPUT_POLARITY, IS_LPTIM_TRG_SOURCE, IS_LPTIM_TRIG_SAMPLE_TIME, IS_LPTIM_UPDATE_MODE, LPTIM_HandleTypeDef::Lock, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_InitTypeDef::OutputPolarity, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ULPClockConfigTypeDef::SampleTime, LPTIM_TriggerConfigTypeDef::SampleTime, LPTIM_ClockConfigTypeDef::Source, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, LPTIM_InitTypeDef::Trigger, LPTIM_InitTypeDef::UltraLowPowerClock, and LPTIM_InitTypeDef::UpdateMode.

__weak void HAL_LPTIM_MspDeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitialize LPTIM MSP.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 337 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_DeInit().

__weak void HAL_LPTIM_MspInit ( LPTIM_HandleTypeDef * hlptim )

Initialize the LPTIM MSP.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 322 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_Init().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM Start-Stop operation functions

Functions
LPTIM Start-Stop operation functions
LPTIM Exported Functions

Start-Stop operation functions. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface in nterrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode in interrupt mode.

Detailed Description

Start-Stop operation functions.

  ==============================================================================
                ##### LPTIM Start Stop operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start the PWM mode.
      (+) Stop the PWM mode.
      (+) Start the One pulse mode.
      (+) Stop the One pulse mode.
      (+) Start the Set once mode.
      (+) Stop the Set once mode.
      (+) Start the Encoder mode.
      (+) Stop the Encoder mode.
      (+) Start the Timeout mode.
      (+) Stop the Timeout mode.
      (+) Start the Counter mode.
      (+) Stop the Counter mode.

Function Documentation

HAL_StatusTypeDef HAL_LPTIM_Counter_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Counter mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1213 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Counter mode in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1277 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Counter mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1252 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Counter mode in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1322 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Starts the Encoder interface.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 882 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_PRESCALER_DIV1, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Encoder interface in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 969 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_IT_DOWN, LPTIM_IT_UP, LPTIM_PRESCALER_DIV1, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Encoder interface.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 941 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Encoder interface in nterrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1035 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_DOWN, LPTIM_IT_UP, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM One pulse generation.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 552 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 616 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM One pulse generation.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 589 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 672 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM PWM generation.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 386 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF
Return values:
HAL status

Definition at line 450 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM PWM generation.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 423 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 506 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM in Set once mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 718 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 782 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM Set once mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 755 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 838 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Start the Timeout function.

Note:
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.
Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | : Specifies the TimeOut value to rest the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1073 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Start the Timeout function in interrupt mode.

Note:
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.
Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | : Specifies the TimeOut value to rest the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1142 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_CMPM, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Timeout function.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1110 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Timeout function in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1182 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_CMPM, and LPTIM_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM Read operation functions

Functions
LPTIM Read operation functions
LPTIM Exported Functions

Read operation functions. More...

Functions

uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
Return the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
Return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
Return the current Compare (Pulse) value.

Detailed Description

Read operation functions.

  ==============================================================================
                  ##### LPTIM Read operation functions #####
  ==============================================================================
[..]  This section provides LPTIM Reading functions.
      (+) Read the counter value.
      (+) Read the period (Auto-reload) value.
      (+) Read the pulse (Compare)value.

Function Documentation

uint32_t HAL_LPTIM_ReadAutoReload ( LPTIM_HandleTypeDef * hlptim )

Return the current Autoreload (Period) value.

Parameters:
hlptim,: LPTIM handle
Return values:
Autoreload value.

Definition at line 1383 of file stm32h7xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCompare ( LPTIM_HandleTypeDef * hlptim )

Return the current Compare (Pulse) value.

Parameters:
hlptim,: LPTIM handle
Return values:
Compare value.

Definition at line 1396 of file stm32h7xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCounter ( LPTIM_HandleTypeDef * hlptim )

Return the current counter value.

Parameters:
hlptim,: LPTIM handle
Return values:
Counter value.

Definition at line 1370 of file stm32h7xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM IRQ handler and callbacks

Functions
LPTIM IRQ handler and callbacks
LPTIM Exported Functions

LPTIM IRQ handler. More...

Functions

void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
Handle LPTIM interrupt request.
__weak void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non-blocking mode.
__weak void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non-blocking mode.
__weak void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non-blocking mode.

Detailed Description

LPTIM IRQ handler.

  ==============================================================================
                      ##### LPTIM IRQ handler and callbacks  #####
  ==============================================================================
[..]  This section provides LPTIM IRQ handler and callback functions called within
      the IRQ handler.

Function Documentation

__weak void HAL_LPTIM_AutoReloadMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload match callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1543 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

__weak void HAL_LPTIM_AutoReloadWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload write callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1588 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

__weak void HAL_LPTIM_CompareMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Compare match callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1528 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

__weak void HAL_LPTIM_CompareWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Compare write callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1573 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

__weak void HAL_LPTIM_DirectionDownCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Up to Down callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1618 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

__weak void HAL_LPTIM_DirectionUpCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Down to Up callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1603 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

void HAL_LPTIM_IRQHandler ( LPTIM_HandleTypeDef * hlptim )

Handle LPTIM interrupt request.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 1429 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_GET_FLAG, __HAL_LPTIM_GET_IT_SOURCE, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_TriggerCallback(), LPTIM_FLAG_ARRM, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPM, LPTIM_FLAG_CMPOK, LPTIM_FLAG_DOWN, LPTIM_FLAG_EXTTRIG, LPTIM_FLAG_UP, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_DOWN, LPTIM_IT_EXTTRIG, and LPTIM_IT_UP.

__weak void HAL_LPTIM_TriggerCallback ( LPTIM_HandleTypeDef * hlptim )

Trigger detected callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1558 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
LPTIM Exported Functions

Peripheral State functions. More...

Functions

HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Returns the LPTIM state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState ( LPTIM_HandleTypeDef * hlptim )

Returns the LPTIM state.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL state

Definition at line 1651 of file stm32h7xx_hal_lptim.c.

References LPTIM_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM Exported Functions

Modules | Functions
LPTIM Exported Functions
LPTIM

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

LPTIM Start-Stop operation functions

Start-Stop operation functions.

LPTIM Read operation functions

Read operation functions.

LPTIM IRQ handler and callbacks

LPTIM IRQ handler.

Peripheral State functions

Peripheral State functions.

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize the LPTIM peripheral.
void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM MSP.
void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize LPTIM MSP.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface in nterrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode in interrupt mode.
uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
Return the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
Return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
Return the current Compare (Pulse) value.
void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
Handle LPTIM interrupt request.
void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non-blocking mode.
void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non-blocking mode.
void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non-blocking mode.
void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non-blocking mode.
void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non-blocking mode.
void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non-blocking mode.
void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non-blocking mode.
HAL_LPTIM_StateTypeDef | HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Returns the LPTIM state.

Function Documentation

void HAL_LPTIM_AutoReloadMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload match callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1543 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

void HAL_LPTIM_AutoReloadWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload write callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1588 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

void HAL_LPTIM_CompareMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Compare match callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1528 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

void HAL_LPTIM_CompareWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Compare write callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1573 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

HAL_StatusTypeDef HAL_LPTIM_Counter_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Counter mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1213 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Counter mode in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1277 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Counter mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1252 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Counter mode in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1322 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_DeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitialize the LPTIM peripheral.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL status

Definition at line 290 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, HAL_LPTIM_MspDeInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_RESET, and LPTIM_HandleTypeDef::State.

void HAL_LPTIM_DirectionDownCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Up to Down callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1618 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

void HAL_LPTIM_DirectionUpCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Down to Up callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1603 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Starts the Encoder interface.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 882 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_PRESCALER_DIV1, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Encoder interface in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 969 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_IT_DOWN, LPTIM_IT_UP, LPTIM_PRESCALER_DIV1, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Encoder interface.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 941 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Encoder interface in nterrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1035 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_DOWN, LPTIM_IT_UP, and LPTIM_HandleTypeDef::State.

HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState ( LPTIM_HandleTypeDef * hlptim )

Returns the LPTIM state.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL state

Definition at line 1651 of file stm32h7xx_hal_lptim.c.

References LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Init ( LPTIM_HandleTypeDef * hlptim )

Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and creates the associated handle.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL status

Definition at line 175 of file stm32h7xx_hal_lptim.c.

References LPTIM_TriggerConfigTypeDef::ActiveEdge, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_MspInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, LPTIM_HandleTypeDef::Init, LPTIM_InitTypeDef::Input1Source, LPTIM_InitTypeDef::Input2Source, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_CLOCK_PRESCALER, IS_LPTIM_CLOCK_SAMPLE_TIME, IS_LPTIM_CLOCK_SOURCE, IS_LPTIM_COUNTER_SOURCE, IS_LPTIM_EXT_TRG_POLARITY, IS_LPTIM_INPUT1_SOURCE, IS_LPTIM_INPUT2_SOURCE, IS_LPTIM_OUTPUT_POLARITY, IS_LPTIM_TRG_SOURCE, IS_LPTIM_TRIG_SAMPLE_TIME, IS_LPTIM_UPDATE_MODE, LPTIM_HandleTypeDef::Lock, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_InitTypeDef::OutputPolarity, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ULPClockConfigTypeDef::SampleTime, LPTIM_TriggerConfigTypeDef::SampleTime, LPTIM_ClockConfigTypeDef::Source, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, LPTIM_InitTypeDef::Trigger, LPTIM_InitTypeDef::UltraLowPowerClock, and LPTIM_InitTypeDef::UpdateMode.

void HAL_LPTIM_IRQHandler ( LPTIM_HandleTypeDef * hlptim )

Handle LPTIM interrupt request.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 1429 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_GET_FLAG, __HAL_LPTIM_GET_IT_SOURCE, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_TriggerCallback(), LPTIM_FLAG_ARRM, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPM, LPTIM_FLAG_CMPOK, LPTIM_FLAG_DOWN, LPTIM_FLAG_EXTTRIG, LPTIM_FLAG_UP, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_DOWN, LPTIM_IT_EXTTRIG, and LPTIM_IT_UP.

void HAL_LPTIM_MspDeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitialize LPTIM MSP.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 337 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_DeInit().

void HAL_LPTIM_MspInit ( LPTIM_HandleTypeDef * hlptim )

Initialize the LPTIM MSP.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 322 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_Init().

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM One pulse generation.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 552 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 616 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM One pulse generation.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 589 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 672 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM PWM generation.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 386 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF
Return values:
HAL status

Definition at line 450 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM PWM generation.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 423 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 506 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

uint32_t HAL_LPTIM_ReadAutoReload ( LPTIM_HandleTypeDef * hlptim )

Return the current Autoreload (Period) value.

Parameters:
hlptim,: LPTIM handle
Return values:
Autoreload value.

Definition at line 1383 of file stm32h7xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCompare ( LPTIM_HandleTypeDef * hlptim )

Return the current Compare (Pulse) value.

Parameters:
hlptim,: LPTIM handle
Return values:
Compare value.

Definition at line 1396 of file stm32h7xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCounter ( LPTIM_HandleTypeDef * hlptim )

Return the current counter value.

Parameters:
hlptim,: LPTIM handle
Return values:
Counter value.

Definition at line 1370 of file stm32h7xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM in Set once mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 718 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 782 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM Set once mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 755 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 838 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Start the Timeout function.

Note:
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.
Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | : Specifies the TimeOut value to rest the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1073 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Start the Timeout function in interrupt mode.

Note:
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.
Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | : Specifies the TimeOut value to rest the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1142 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_CMPM, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Timeout function.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1110 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Timeout function in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1182 of file stm32h7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_CMPM, and LPTIM_HandleTypeDef::State.

void HAL_LPTIM_TriggerCallback ( LPTIM_HandleTypeDef * hlptim )

Trigger detected callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1558 of file stm32h7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM Exported Types

Data Structures | Typedefs | Enumerations
LPTIM Exported Types
LPTIM

Data Structures

struct | LPTIM_ClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_ULPClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_TriggerConfigTypeDef
LPTIM Trigger configuration definition. More...
struct | LPTIM_InitTypeDef
LPTIM Initialization Structure definition. More...
struct | LPTIM_HandleTypeDef
LPTIM handle Structure definition. More...

Typedefs

typedef enum
__HAL_LPTIM_StateTypeDef 		HAL_LPTIM_StateTypeDef
HAL LPTIM State structure definition.

Enumerations

enum __HAL_LPTIM_StateTypeDef {
HAL_LPTIM_STATE_RESET = 0x00U, HAL_LPTIM_STATE_READY = 0x01U, HAL_LPTIM_STATE_BUSY = 0x02U, HAL_LPTIM_STATE_TIMEOUT = 0x03U,
HAL_LPTIM_STATE_ERROR = 0x04U
}
HAL LPTIM State structure definition. More...

Typedef Documentation

typedef enum __HAL_LPTIM_StateTypeDef HAL_LPTIM_StateTypeDef

HAL LPTIM State structure definition.

Enumeration Type Documentation

enum __HAL_LPTIM_StateTypeDef

HAL LPTIM State structure definition.

Enumerator:
HAL_LPTIM_STATE_RESET

Peripheral not yet initialized or disabled

HAL_LPTIM_STATE_READY

Peripheral Initialized and ready for use

HAL_LPTIM_STATE_BUSY

An internal process is ongoing

HAL_LPTIM_STATE_TIMEOUT

Timeout state

HAL_LPTIM_STATE_ERROR

Internal Process is ongoing

Definition at line 145 of file stm32h7xx_hal_lptim.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM_ClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_ClockConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Clock configuration definition. More...

#include <stm32h7xx_hal_lptim.h>

Data Fields

uint32_t | Source
uint32_t | Prescaler

Detailed Description

LPTIM Clock configuration definition.

Definition at line 65 of file stm32h7xx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_ClockConfigTypeDef::Prescaler

Specifies the counter clock Prescaler. This parameter can be a value of LPTIM Clock Prescaler

Definition at line 70 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_ClockConfigTypeDef::Source

Selects the clock source. This parameter can be a value of LPTIM Clock Source

Definition at line 67 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_lptim.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM_ULPClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_ULPClockConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Clock configuration definition. More...

#include <stm32h7xx_hal_lptim.h>

Data Fields

uint32_t | Polarity
uint32_t | SampleTime

Detailed Description

LPTIM Clock configuration definition.

Definition at line 78 of file stm32h7xx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_ULPClockConfigTypeDef::Polarity

Selects the polarity of the active edge for the counter unit if the ULPTIM input is selected. Note: This parameter is used only when Ultra low power clock source is used. Note: If the polarity is configured on 'both edges', an auxiliary clock (one of the Low power oscillator) must be active. This parameter can be a value of LPTIM Clock Polarity

Definition at line 80 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_ULPClockConfigTypeDef::SampleTime

Selects the clock sampling time to configure the clock glitch filter. Note: This parameter is used only when Ultra low power clock source is used. This parameter can be a value of LPTIM Clock Sample Time

Definition at line 87 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_lptim.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM_TriggerConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_TriggerConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Trigger configuration definition. More...

#include <stm32h7xx_hal_lptim.h>

Data Fields

uint32_t | Source
uint32_t | ActiveEdge
uint32_t | SampleTime

Detailed Description

LPTIM Trigger configuration definition.

Definition at line 96 of file stm32h7xx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_TriggerConfigTypeDef::ActiveEdge

Selects the Trigger active edge. Note: This parameter is used only when an external trigger is used. This parameter can be a value of LPTIM External Trigger Polarity

Definition at line 101 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_TriggerConfigTypeDef::SampleTime

Selects the trigger sampling time to configure the clock glitch filter. Note: This parameter is used only when an external trigger is used. This parameter can be a value of LPTIM Trigger Sample Time

Definition at line 105 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_TriggerConfigTypeDef::Source

Selects the Trigger source. This parameter can be a value of LPTIM Trigger Source

Definition at line 98 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_lptim.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_InitTypeDef Struct Reference
LPTIM Exported Types

LPTIM Initialization Structure definition. More...

#include <stm32h7xx_hal_lptim.h>

Data Fields

LPTIM_ClockConfigTypeDef Clock
LPTIM_ULPClockConfigTypeDef UltraLowPowerClock
LPTIM_TriggerConfigTypeDef Trigger
uint32_t | OutputPolarity
uint32_t | UpdateMode
uint32_t | CounterSource
uint32_t | Input1Source
uint32_t | Input2Source

Detailed Description

LPTIM Initialization Structure definition.

Definition at line 113 of file stm32h7xx_hal_lptim.h.

Field Documentation

LPTIM_ClockConfigTypeDef LPTIM_InitTypeDef::Clock

Specifies the clock parameters

Definition at line 115 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::CounterSource

Specifies whether the counter is incremented each internal event or each external event. This parameter can be a value of LPTIM Counter Source

Definition at line 128 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::Input1Source

Specifies source selected for input1 (GPIO or comparator output). This parameter can be a value of LPTIM Input1 Source

Definition at line 132 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::Input2Source

Specifies source selected for input2 (GPIO or comparator output). Note: This parameter is used only for encoder feature so is used only for LPTIM1 instance. This parameter can be a value of LPTIM Input2 Source

Definition at line 135 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::OutputPolarity

Specifies the Output polarity. This parameter can be a value of LPTIM Output Polarity

Definition at line 121 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

LPTIM_TriggerConfigTypeDef LPTIM_InitTypeDef::Trigger

Specifies the Trigger parameters

Definition at line 119 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

LPTIM_ULPClockConfigTypeDef LPTIM_InitTypeDef::UltraLowPowerClock

Specifies the Ultra Low Power clock parameters

Definition at line 117 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::UpdateMode

Specifies whether the update of the autorelaod and the compare values is done immediately or after the end of current period. This parameter can be a value of LPTIM Updating Mode

Definition at line 124 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_lptim.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_HandleTypeDef Struct Reference
LPTIM Exported Types

LPTIM handle Structure definition. More...

#include <stm32h7xx_hal_lptim.h>

Data Fields

LPTIM_TypeDef * | Instance
LPTIM_InitTypeDef Init
HAL_StatusTypeDef | Status
HAL_LockTypeDef | Lock
__IO HAL_LPTIM_StateTypeDef | State

Detailed Description

LPTIM handle Structure definition.

Definition at line 157 of file stm32h7xx_hal_lptim.h.

Field Documentation

LPTIM_InitTypeDef LPTIM_HandleTypeDef::Init

LPTIM required parameters

Definition at line 161 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

LPTIM_TypeDef* LPTIM_HandleTypeDef::Instance

Register base address

Definition at line 159 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_ReadAutoReload(), HAL_LPTIM_ReadCompare(), HAL_LPTIM_ReadCounter(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), and HAL_LPTIM_TimeOut_Stop_IT().

HAL_LockTypeDef LPTIM_HandleTypeDef::Lock

LPTIM locking object

Definition at line 165 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

__IO HAL_LPTIM_StateTypeDef LPTIM_HandleTypeDef::State

LPTIM peripheral state

Definition at line 167 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_DeInit(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_GetState(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), and HAL_LPTIM_TimeOut_Stop_IT().

HAL_StatusTypeDef LPTIM_HandleTypeDef::Status

LPTIM peripheral status

Definition at line 163 of file stm32h7xx_hal_lptim.h.

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_lptim.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM Clock Source

Defines
LPTIM Clock Source
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00U)
#define | LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL

Define Documentation

#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00U)

Definition at line 183 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), and HAL_LPTIM_Encoder_Start_IT().

#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL

Definition at line 184 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_Init().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM Clock Prescaler

Defines
LPTIM Clock Prescaler
LPTIM Exported Constants

Defines

#define | LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000U)
#define | LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
#define | LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
#define | LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
#define | LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC)

Define Documentation

#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000U)

Definition at line 192 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), and HAL_LPTIM_Encoder_Start_IT().

#define LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC)

Definition at line 199 of file stm32h7xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2

Definition at line 196 of file stm32h7xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0

Definition at line 193 of file stm32h7xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))

Definition at line 197 of file stm32h7xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1

Definition at line 194 of file stm32h7xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))

Definition at line 198 of file stm32h7xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))

Definition at line 195 of file stm32h7xx_hal_lptim.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM Output Polarity

Defines
LPTIM Output Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U)
#define | LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)

Define Documentation

#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U)

Definition at line 208 of file stm32h7xx_hal_lptim.h.

#define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)

Definition at line 209 of file stm32h7xx_hal_lptim.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM Clock Sample Time

Defines
LPTIM Clock Sample Time
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
#define | LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define | LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define | LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT

Define Documentation

#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0

Definition at line 218 of file stm32h7xx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1

Definition at line 219 of file stm32h7xx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT

Definition at line 220 of file stm32h7xx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)

Definition at line 217 of file stm32h7xx_hal_lptim.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM Clock Polarity

Defines
LPTIM Clock Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000U)
#define | LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Define Documentation

#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0

Definition at line 230 of file stm32h7xx_hal_lptim.h.

#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000U)

Definition at line 229 of file stm32h7xx_hal_lptim.h.

#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Definition at line 231 of file stm32h7xx_hal_lptim.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM Trigger Source

Defines
LPTIM Trigger Source
LPTIM Exported Constants

Defines

#define | LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFFU)
#define | LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000U)
#define | LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
#define | LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define | LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define | LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
#define | LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_6 ((uint32_t)LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL

Define Documentation

#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000U)

Definition at line 240 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)

Definition at line 241 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1

Definition at line 242 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)

Definition at line 243 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2

Definition at line 244 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)

Definition at line 245 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_6 ((uint32_t)LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)

Definition at line 246 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL

Definition at line 247 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFFU)

Definition at line 239 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM External Trigger Polarity

Defines
LPTIM External Trigger Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
#define | LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
#define | LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN

Define Documentation

#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1

Definition at line 256 of file stm32h7xx_hal_lptim.h.

#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0

Definition at line 255 of file stm32h7xx_hal_lptim.h.

#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN

Definition at line 257 of file stm32h7xx_hal_lptim.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM Trigger Sample Time

Defines
LPTIM Trigger Sample Time
LPTIM Exported Constants

Defines

#define | LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
#define | LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define | LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define | LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT

Define Documentation

#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0

Definition at line 266 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1

Definition at line 267 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT

Definition at line 268 of file stm32h7xx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)

Definition at line 265 of file stm32h7xx_hal_lptim.h.

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STM32H753xx HAL User Manual: LPTIM Updating Mode

Defines
LPTIM Updating Mode
LPTIM Exported Constants

Defines

#define | LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000U)
#define | LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

Define Documentation

#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

Definition at line 278 of file stm32h7xx_hal_lptim.h.

#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000U)

Definition at line 277 of file stm32h7xx_hal_lptim.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM Counter Source

Defines
LPTIM Counter Source
LPTIM Exported Constants

Defines

#define | LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000U)
#define | LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE

Define Documentation

#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE

Definition at line 288 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), and HAL_LPTIM_Counter_Start_IT().

#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000U)

Definition at line 287 of file stm32h7xx_hal_lptim.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM Input1 Source

Defines
LPTIM Input1 Source
LPTIM Exported Constants

Defines

#define | LPTIM_INPUT1SOURCE_GPIO ((uint32_t)0x00000000U)
#define | LPTIM_INPUT1SOURCE_COMP1 LPTIM_CFGR2_IN1_SEL0
#define | LPTIM_INPUT1SOURCE_COMP2 LPTIM_CFGR2_IN1_SEL1
#define | LPTIM_INPUT1SOURCE_COMP1_COMP2 (LPTIM_CFGR2_IN1_SEL0|LPTIM_CFGR2_IN1_SEL1)
#define | LPTIM_INPUT1SOURCE_SAI1_FSA LPTIM_CFGR2_IN1_SEL0
#define | LPTIM_INPUT1SOURCE_SAI1_FSB LPTIM_CFGR2_IN1_SEL1

Define Documentation

#define LPTIM_INPUT1SOURCE_COMP1 LPTIM_CFGR2_IN1_SEL0

For LPTIM1 and LPTIM2

Definition at line 298 of file stm32h7xx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_COMP1_COMP2 (LPTIM_CFGR2_IN1_SEL0|LPTIM_CFGR2_IN1_SEL1)

For LPTIM2

Definition at line 300 of file stm32h7xx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_COMP2 LPTIM_CFGR2_IN1_SEL1

For LPTIM2 and LPTIM2

Definition at line 299 of file stm32h7xx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_GPIO ((uint32_t)0x00000000U)

For LPTIM1, LPTIM2 and LPTIM3

Definition at line 297 of file stm32h7xx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_SAI1_FSA LPTIM_CFGR2_IN1_SEL0

For LPTIM3

Definition at line 301 of file stm32h7xx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_SAI1_FSB LPTIM_CFGR2_IN1_SEL1

For LPTIM3

Definition at line 302 of file stm32h7xx_hal_lptim.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM Input2 Source

Defines
LPTIM Input2 Source
LPTIM Exported Constants

Defines

#define | LPTIM_INPUT2SOURCE_GPIO ((uint32_t)0x00000000U)
#define | LPTIM_INPUT2SOURCE_COMP2 LPTIM_CFGR2_IN2_SEL0

Define Documentation

#define LPTIM_INPUT2SOURCE_COMP2 LPTIM_CFGR2_IN2_SEL0

For LPTIM1 and LPTIM2

Definition at line 312 of file stm32h7xx_hal_lptim.h.

#define LPTIM_INPUT2SOURCE_GPIO ((uint32_t)0x00000000U)

For LPTIM1 and LPTIM2

Definition at line 311 of file stm32h7xx_hal_lptim.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM Flags Definition

Defines
LPTIM Flags Definition
LPTIM Exported Constants

Defines

#define | LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
#define | LPTIM_FLAG_UP LPTIM_ISR_UP
#define | LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
#define | LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
#define | LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
#define | LPTIM_FLAG_CMPM LPTIM_ISR_CMPM

Define Documentation

#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM

Definition at line 326 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK

Definition at line 323 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM

Definition at line 327 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK

Definition at line 324 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN

Definition at line 321 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG

Definition at line 325 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_UP LPTIM_ISR_UP

Definition at line 322 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM Interrupts Definition

Defines
LPTIM Interrupts Definition
LPTIM Exported Constants

Defines

#define | LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define | LPTIM_IT_UP LPTIM_IER_UPIE
#define | LPTIM_IT_ARROK LPTIM_IER_ARROKIE
#define | LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
#define | LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
#define | LPTIM_IT_ARRM LPTIM_IER_ARRMIE
#define | LPTIM_IT_CMPM LPTIM_IER_CMPMIE

Define Documentation

#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE

Definition at line 341 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE

Definition at line 338 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE

Definition at line 342 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start_IT(), and HAL_LPTIM_TimeOut_Stop_IT().

#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE

Definition at line 339 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE

Definition at line 336 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop_IT(), and HAL_LPTIM_IRQHandler().

#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE

Definition at line 340 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_UP LPTIM_IER_UPIE

Definition at line 337 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop_IT(), and HAL_LPTIM_IRQHandler().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM Exported Macros

Defines
LPTIM Exported Macros
LPTIM

Defines

#define | __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
Reset LPTIM handle state.
#define | __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
Enable the LPTIM peripheral.
#define | __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))
Disable the LPTIM peripheral.
#define | __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
Start the LPTIM peripheral in Continuous mode.
#define | __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
Start the LPTIM peripheral in single mode.
#define | __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)
Reset the LPTIM Counter register in synchronous mode.
#define | __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)
Reset after read of the LPTIM Counter register in asynchronous mode.
#define | __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
Write the passed parameter in the Autoreload register.
#define | __HAL_LPTIM_COMPARE_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
Write the passed parameter in the Compare register.
#define | __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
Check whether the specified LPTIM flag is set or not.
#define | __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified LPTIM flag.
#define | __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified LPTIM interrupt.
#define | __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified LPTIM interrupt.
#define | __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified LPTIM interrupt is set or not.

Define Documentation

#define __HAL_LPTIM_AUTORELOAD_SET | ( | __HANDLE__,
 |  | __VALUE__
 | ) | ((__HANDLE__)->Instance->ARR = (__VALUE__))

Write the passed parameter in the Autoreload register.

Parameters:
__HANDLE__,: LPTIM handle
__VALUE__ : Autoreload value
Return values:
None

Definition at line 409 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified LPTIM flag.

Parameters:
__HANDLE__,: LPTIM handle.
__FLAG__ : LPTIM flag to clear. This parameter can be a value of:
  • LPTIM_FLAG_DOWN : Counter direction change up Flag.
  • LPTIM_FLAG_UP : Counter direction change down to up Flag.
  • LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
  • LPTIM_FLAG_CMPOK : Compare register update OK Flag.
  • LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
  • LPTIM_FLAG_ARRM : Autoreload match Flag.
  • LPTIM_FLAG_CMPM : Compare match Flag.
Return values:
None.

Definition at line 449 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define __HAL_LPTIM_COMPARE_SET | ( | __HANDLE__,
 |  | __VALUE__
 | ) | ((__HANDLE__)->Instance->CMP = (__VALUE__))

Write the passed parameter in the Compare register.

Parameters:
__HANDLE__,: LPTIM handle
__VALUE__ : Compare value
Return values:
None

Definition at line 417 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))

Disable the LPTIM peripheral.

Parameters:
__HANDLE__,: LPTIM handle
Return values:
None

Definition at line 374 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_DeInit(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Stop(), and HAL_LPTIM_TimeOut_Stop_IT().

#define __HAL_LPTIM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))

Disable the specified LPTIM interrupt.

Parameters:
__HANDLE__ : LPTIM handle.
__INTERRUPT__ : LPTIM interrupt to set. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
None.

Definition at line 481 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Stop_IT(), and HAL_LPTIM_TimeOut_Stop_IT().

#define __HAL_LPTIM_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))

Enable the LPTIM peripheral.

Parameters:
__HANDLE__,: LPTIM handle
Return values:
None

Definition at line 367 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enable the specified LPTIM interrupt.

Parameters:
__HANDLE__ : LPTIM handle.
__INTERRUPT__ : LPTIM interrupt to set. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
None.

Definition at line 465 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))

Check whether the specified LPTIM flag is set or not.

Parameters:
__HANDLE__,: LPTIM handle
__FLAG__ : LPTIM flag to check This parameter can be a value of:
  • LPTIM_FLAG_DOWN : Counter direction change up Flag.
  • LPTIM_FLAG_UP : Counter direction change down to up Flag.
  • LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
  • LPTIM_FLAG_CMPOK : Compare register update OK Flag.
  • LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
  • LPTIM_FLAG_ARRM : Autoreload match Flag.
  • LPTIM_FLAG_CMPM : Compare match Flag.
Return values:
The state of the specified flag (SET or RESET).

Definition at line 433 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define __HAL_LPTIM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified LPTIM interrupt is set or not.

Parameters:
__HANDLE__ : LPTIM handle.
__INTERRUPT__ : LPTIM interrupt to check. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
Interrupt status.

Definition at line 498 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define __HAL_LPTIM_RESET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)

Reset the LPTIM Counter register in synchronous mode.

Parameters:
__HANDLE__,: LPTIM handle
Return values:
None

Definition at line 394 of file stm32h7xx_hal_lptim.h.

#define __HAL_LPTIM_RESET_COUNTER_AFTERREAD ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)

Reset after read of the LPTIM Counter register in asynchronous mode.

Parameters:
__HANDLE__,: LPTIM handle
Return values:
None

Definition at line 401 of file stm32h7xx_hal_lptim.h.

#define __HAL_LPTIM_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)

Reset LPTIM handle state.

Parameters:
__HANDLE__,: LPTIM handle
Return values:
None

Definition at line 360 of file stm32h7xx_hal_lptim.h.

#define __HAL_LPTIM_START_CONTINUOUS ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)

Start the LPTIM peripheral in Continuous mode.

Parameters:
__HANDLE__,: LPTIM handle
Return values:
None

Definition at line 381 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_START_SINGLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)

Start the LPTIM peripheral in single mode.

Parameters:
__HANDLE__,: LPTIM handle
Return values:
None

Definition at line 387 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_SetOnce_Start(), and HAL_LPTIM_SetOnce_Start_IT().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM Private Constants

LPTIM Private Constants
LPTIM
Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM Private Macros

Defines
LPTIM Private Macros
LPTIM

Defines

#define | IS_LPTIM_CLOCK_SOURCE(__SOURCE__)
#define | IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__)
#define | IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
#define | IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_CLOCK_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRG_SOURCE(__TRIG__)
#define | IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_UPDATE_MODE(__MODE__)
#define | IS_LPTIM_COUNTER_SOURCE(__SOURCE__)
#define | IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFF)
#define | IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFF)
#define | IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFF)
#define | IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFF)
#define | IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)
#define | IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)

Define Documentation

#define IS_LPTIM_AUTORELOAD ( __AUTORELOAD__ ) ((__AUTORELOAD__) <= 0x0000FFFF)

Definition at line 571 of file stm32h7xx_hal_lptim.h.

#define IS_LPTIM_CLOCK_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))

Definition at line 542 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))

Definition at line 523 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_PRESCALERDIV1 ( __PRESCALER__ ) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)

Definition at line 532 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), and HAL_LPTIM_Counter_Start_IT().

#define IS_LPTIM_CLOCK_SAMPLE_TIME ( __SAMPLETIME__ )
Value:
(((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))

Definition at line 537 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
                                                 ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))

Definition at line 519 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_COMPARE ( __COMPARE__ ) ((__COMPARE__) <= 0x0000FFFF)

Definition at line 573 of file stm32h7xx_hal_lptim.h.

#define IS_LPTIM_COUNTER_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
                                                 ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))

Definition at line 568 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_EXT_TRG_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING         ) || \
                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))

Definition at line 556 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_INPUT1_SOURCE | ( | __INSTANCE__,
 |  | __SOURCE__
 | ) |
Value:
((((__INSTANCE__) == LPTIM1) &&                       \
     (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1)))        \
     ||                                                   \
     (((__INSTANCE__) == LPTIM2) &&                       \
     (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) ||       \
      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) ||       \
      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2)))  \
     ||                                                   \
     (((__INSTANCE__) == LPTIM3) &&                       \
     (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
      ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI1_FSA) ||    \
      ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI1_FSB))))

Definition at line 579 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_INPUT2_SOURCE | ( | __INSTANCE__,
 |  | __SOURCE__
 | ) |
Value:
(((__INSTANCE__) == LPTIM1) &&                       \
     (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) ||        \
      ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2))         \
      ||                                                  \
      ((__INSTANCE__) == LPTIM2) &&                       \
     (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) ||        \
      ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))

Definition at line 595 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_OUTPUT_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
                                                 ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))

Definition at line 534 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_PERIOD ( __PERIOD__ ) ((__PERIOD__) <= 0x0000FFFF)

Definition at line 575 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define IS_LPTIM_PULSE ( __PULSE__ ) ((__PULSE__) <= 0x0000FFFF)

Definition at line 577 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define IS_LPTIM_TRG_SOURCE ( __TRIG__ )
Value:
(((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_7))

Definition at line 546 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_TRIG_SAMPLE_TIME ( __SAMPLETIME__ )
Value:
(((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))

Definition at line 560 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_UPDATE_MODE ( __MODE__ )
Value:
(((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
                                                 ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))

Definition at line 565 of file stm32h7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LPTIM Private Functions

LPTIM Private Functions
LPTIM
Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and Configuration functions

Functions
Initialization and Configuration functions
LTDC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_LTDC_Init (LTDC_HandleTypeDef *hltdc)
Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef.
HAL_StatusTypeDef | HAL_LTDC_DeInit (LTDC_HandleTypeDef *hltdc)
De-initialize the LTDC peripheral.
__weak void | HAL_LTDC_MspInit (LTDC_HandleTypeDef *hltdc)
Initialize the LTDC MSP.
__weak void | HAL_LTDC_MspDeInit (LTDC_HandleTypeDef *hltdc)
De-initialize the LTDC MSP.
void | HAL_LTDC_ErrorCallback (LTDC_HandleTypeDef *hltdc)
Error LTDC callback.
void | HAL_LTDC_LineEventCallback (LTDC_HandleTypeDef *hltdc)
Line Event callback.
void | HAL_LTDC_ReloadEventCallback (LTDC_HandleTypeDef *hltdc)
Reload Event callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
                ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the LTDC
      (+) De-initialize the LTDC

Function Documentation

HAL_StatusTypeDef HAL_LTDC_DeInit ( LTDC_HandleTypeDef * hltdc )

De-initialize the LTDC peripheral.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
None

Definition at line 247 of file stm32h7xx_hal_ltdc.c.

References LTDC_HandleTypeDef::ErrorCode, HAL_LTDC_ERROR_NONE, HAL_LTDC_MspDeInit(), HAL_LTDC_STATE_RESET, and LTDC_HandleTypeDef::State.

void HAL_LTDC_ErrorCallback ( LTDC_HandleTypeDef * hltdc )

Error LTDC callback.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
None

Definition at line 419 of file stm32h7xx_hal_ltdc.c.

Referenced by HAL_LTDC_IRQHandler().

HAL_StatusTypeDef HAL_LTDC_Init ( LTDC_HandleTypeDef * hltdc )

Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
HAL status

Definition at line 158 of file stm32h7xx_hal_ltdc.c.

References __HAL_LTDC_ENABLE, __HAL_LTDC_ENABLE_IT, LTDC_InitTypeDef::AccumulatedActiveH, LTDC_InitTypeDef::AccumulatedActiveW, LTDC_InitTypeDef::AccumulatedHBP, LTDC_InitTypeDef::AccumulatedVBP, assert_param, LTDC_InitTypeDef::Backcolor, LTDC_ColorTypeDef::Blue, LTDC_InitTypeDef::DEPolarity, LTDC_HandleTypeDef::ErrorCode, LTDC_ColorTypeDef::Green, HAL_LTDC_ERROR_NONE, HAL_LTDC_MspInit(), HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, HAL_LTDC_STATE_RESET, LTDC_InitTypeDef::HorizontalSync, LTDC_InitTypeDef::HSPolarity, LTDC_HandleTypeDef::Init, LTDC_HandleTypeDef::Instance, IS_LTDC_AAH, IS_LTDC_AAW, IS_LTDC_AHBP, IS_LTDC_AVBP, IS_LTDC_DEPOL, IS_LTDC_HSPOL, IS_LTDC_HSYNC, IS_LTDC_PCPOL, IS_LTDC_TOTALH, IS_LTDC_TOTALW, IS_LTDC_VSPOL, IS_LTDC_VSYNC, LTDC_HandleTypeDef::Lock, LTDC_IT_FU, LTDC_IT_TE, LTDC_InitTypeDef::PCPolarity, LTDC_ColorTypeDef::Red, LTDC_HandleTypeDef::State, LTDC_InitTypeDef::TotalHeigh, LTDC_InitTypeDef::TotalWidth, LTDC_InitTypeDef::VerticalSync, and LTDC_InitTypeDef::VSPolarity.

void HAL_LTDC_LineEventCallback ( LTDC_HandleTypeDef * hltdc )

Line Event callback.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
None

Definition at line 435 of file stm32h7xx_hal_ltdc.c.

Referenced by HAL_LTDC_IRQHandler().

void HAL_LTDC_MspDeInit ( LTDC_HandleTypeDef * hltdc )

De-initialize the LTDC MSP.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
None

Definition at line 286 of file stm32h7xx_hal_ltdc.c.

Referenced by HAL_LTDC_DeInit().

void HAL_LTDC_MspInit ( LTDC_HandleTypeDef * hltdc )

Initialize the LTDC MSP.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
None

Definition at line 270 of file stm32h7xx_hal_ltdc.c.

Referenced by HAL_LTDC_Init().

void HAL_LTDC_ReloadEventCallback ( LTDC_HandleTypeDef * hltdc )

Reload Event callback.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
None

Definition at line 451 of file stm32h7xx_hal_ltdc.c.

Referenced by HAL_LTDC_IRQHandler().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
LTDC Exported Functions

IO operation functions. More...

Functions

void | HAL_LTDC_IRQHandler (LTDC_HandleTypeDef *hltdc)
Handle LTDC interrupt request.
__weak void | HAL_LTDC_ErrorCallback (LTDC_HandleTypeDef *hltdc)
Error LTDC callback.
__weak void | HAL_LTDC_LineEventCallback (LTDC_HandleTypeDef *hltdc)
Line Event callback.
__weak void | HAL_LTDC_ReloadEventCallback (LTDC_HandleTypeDef *hltdc)
Reload Event callback.

Detailed Description

IO operation functions.

 ===============================================================================
                      #####  IO operation functions  #####
 ===============================================================================
    [..]  This section provides function allowing to:
      (+) Handle LTDC interrupt request

Function Documentation

__weak void HAL_LTDC_ErrorCallback ( LTDC_HandleTypeDef * hltdc )

Error LTDC callback.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
None

Definition at line 419 of file stm32h7xx_hal_ltdc.c.

Referenced by HAL_LTDC_IRQHandler().

void HAL_LTDC_IRQHandler ( LTDC_HandleTypeDef * hltdc )

Handle LTDC interrupt request.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
HAL status

Definition at line 319 of file stm32h7xx_hal_ltdc.c.

References __HAL_LTDC_CLEAR_FLAG, __HAL_LTDC_DISABLE_IT, __HAL_LTDC_GET_FLAG, __HAL_LTDC_GET_IT_SOURCE, LTDC_HandleTypeDef::ErrorCode, HAL_LTDC_ERROR_FU, HAL_LTDC_ERROR_TE, HAL_LTDC_ErrorCallback(), HAL_LTDC_LineEventCallback(), HAL_LTDC_ReloadEventCallback(), HAL_LTDC_STATE_ERROR, HAL_LTDC_STATE_READY, LTDC_FLAG_FU, LTDC_FLAG_LI, LTDC_FLAG_RR, LTDC_FLAG_TE, LTDC_IT_FU, LTDC_IT_LI, LTDC_IT_RR, LTDC_IT_TE, and LTDC_HandleTypeDef::State.

__weak void HAL_LTDC_LineEventCallback ( LTDC_HandleTypeDef * hltdc )

Line Event callback.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
None

Definition at line 435 of file stm32h7xx_hal_ltdc.c.

Referenced by HAL_LTDC_IRQHandler().

__weak void HAL_LTDC_ReloadEventCallback ( LTDC_HandleTypeDef * hltdc )

Reload Event callback.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
None

Definition at line 451 of file stm32h7xx_hal_ltdc.c.

Referenced by HAL_LTDC_IRQHandler().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
LTDC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_LTDC_ConfigLayer (LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
Configure the LTDC Layer according to the specified parameters in the LTDC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_LTDC_ConfigColorKeying (LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
Configure the color keying.
HAL_StatusTypeDef | HAL_LTDC_ConfigCLUT (LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)
Load the color lookup table.
HAL_StatusTypeDef | HAL_LTDC_EnableColorKeying (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color keying.
HAL_StatusTypeDef | HAL_LTDC_DisableColorKeying (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color keying.
HAL_StatusTypeDef | HAL_LTDC_EnableCLUT (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color lookup table.
HAL_StatusTypeDef | HAL_LTDC_DisableCLUT (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color lookup table.
HAL_StatusTypeDef | HAL_LTDC_EnableDither (LTDC_HandleTypeDef *hltdc)
Enable Dither.
HAL_StatusTypeDef | HAL_LTDC_DisableDither (LTDC_HandleTypeDef *hltdc)
Disable Dither.
HAL_StatusTypeDef | HAL_LTDC_SetWindowSize (LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
Set the LTDC window size.
HAL_StatusTypeDef | HAL_LTDC_SetWindowPosition (LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
Set the LTDC window position.
HAL_StatusTypeDef | HAL_LTDC_SetPixelFormat (LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
Reconfigure the pixel format.
HAL_StatusTypeDef | HAL_LTDC_SetAlpha (LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
Reconfigure the layer alpha value.
HAL_StatusTypeDef | HAL_LTDC_SetAddress (LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
Reconfigure the frame buffer Address.
HAL_StatusTypeDef | HAL_LTDC_SetPitch (LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is larger than the one intended to be displayed on screen.
HAL_StatusTypeDef | HAL_LTDC_ProgramLineEvent (LTDC_HandleTypeDef *hltdc, uint32_t Line)
Define the position of the line interrupt.
HAL_StatusTypeDef | HAL_LTDC_Reload (LTDC_HandleTypeDef *hltdc, uint32_t ReloadType)
Reload LTDC Layers configuration.
HAL_StatusTypeDef | HAL_LTDC_ConfigLayer_NoReload (LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
Configure the LTDC Layer according to the specified without reloading parameters in the LTDC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_LTDC_SetWindowSize_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
Set the LTDC window size without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetWindowPosition_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
Set the LTDC window position without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetPixelFormat_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
Reconfigure the pixel format without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetAlpha_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
Reconfigure the layer alpha value without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetAddress_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
Reconfigure the frame buffer Address without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetPitch_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is larger than the one intended to be displayed on screen.
HAL_StatusTypeDef | HAL_LTDC_ConfigColorKeying_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
Configure the color keying without reloading.
HAL_StatusTypeDef | HAL_LTDC_EnableColorKeying_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color keying without reloading.
HAL_StatusTypeDef | HAL_LTDC_DisableColorKeying_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color keying without reloading.
HAL_StatusTypeDef | HAL_LTDC_EnableCLUT_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color lookup table without reloading.
HAL_StatusTypeDef | HAL_LTDC_DisableCLUT_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color lookup table without reloading.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                    ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the LTDC foreground or/and background parameters.
      (+) Set the active layer.
      (+) Configure the color keying.
      (+) Configure the C-LUT.
      (+) Enable / Disable the color keying.
      (+) Enable / Disable the C-LUT.
      (+) Update the layer position.
      (+) Update the layer size.
      (+) Update pixel format on the fly.
      (+) Update transparency on the fly.
      (+) Update address on the fly.

Function Documentation

HAL_StatusTypeDef HAL_LTDC_ConfigCLUT | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t * | pCLUT,
 |  | uint32_t | CLUTSize,
 |  | uint32_t | LayerIdx
 | ) |  |

Load the color lookup table.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
pCLUT | pointer to the color lookup table address.
CLUTSize | the color lookup table size.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 589 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LAYER, LTDC_HandleTypeDef::LayerCfg, LTDC_LAYER, LTDC_PIXEL_FORMAT_AL44, LTDC_LayerCfgTypeDef::PixelFormat, and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | RGBValue,
 |  | uint32_t | LayerIdx
 | ) |  |

Configure the color keying.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
RGBValue | the color key value
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 551 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, LTDC_HandleTypeDef::Instance, IS_LTDC_LAYER, LTDC_LAYER, and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | RGBValue,
 |  | uint32_t | LayerIdx
 | ) |  |

Configure the color keying without reloading.

Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
RGBValue | the color key value
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1589 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LAYER, LTDC_LAYER, and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_ConfigLayer | ( | LTDC_HandleTypeDef * | hltdc,
 |  | LTDC_LayerCfgTypeDef * | pLayerCfg,
 |  | uint32_t | LayerIdx
 | ) |  |

Configure the LTDC Layer according to the specified parameters in the LTDC_InitTypeDef and create the associated handle.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
pLayerCfg | pointer to a LTDC_LayerCfgTypeDef structure that contains the configuration information for the Layer.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 501 of file stm32h7xx_hal_ltdc.c.

References LTDC_LayerCfgTypeDef::Alpha, LTDC_LayerCfgTypeDef::Alpha0, assert_param, LTDC_LayerCfgTypeDef::BlendingFactor1, LTDC_LayerCfgTypeDef::BlendingFactor2, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, LTDC_LayerCfgTypeDef::ImageHeight, LTDC_LayerCfgTypeDef::ImageWidth, LTDC_HandleTypeDef::Instance, IS_LTDC_ALPHA, IS_LTDC_BLENDING_FACTOR1, IS_LTDC_BLENDING_FACTOR2, IS_LTDC_CFBLL, IS_LTDC_CFBLNBR, IS_LTDC_HCONFIGSP, IS_LTDC_HCONFIGST, IS_LTDC_LAYER, IS_LTDC_PIXEL_FORMAT, IS_LTDC_VCONFIGSP, IS_LTDC_VCONFIGST, LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), LTDC_LayerCfgTypeDef::PixelFormat, LTDC_HandleTypeDef::State, LTDC_LayerCfgTypeDef::WindowX0, LTDC_LayerCfgTypeDef::WindowX1, LTDC_LayerCfgTypeDef::WindowY0, and LTDC_LayerCfgTypeDef::WindowY1.

HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | LTDC_LayerCfgTypeDef * | pLayerCfg,
 |  | uint32_t | LayerIdx
 | ) |  |

Configure the LTDC Layer according to the specified without reloading parameters in the LTDC_InitTypeDef and create the associated handle.

Variant of the function HAL_LTDC_ConfigLayer without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
pLayerCfg | pointer to a LTDC_LayerCfgTypeDef structure that contains the configuration information for the Layer.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1225 of file stm32h7xx_hal_ltdc.c.

References LTDC_LayerCfgTypeDef::Alpha, LTDC_LayerCfgTypeDef::Alpha0, assert_param, LTDC_LayerCfgTypeDef::BlendingFactor1, LTDC_LayerCfgTypeDef::BlendingFactor2, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, LTDC_LayerCfgTypeDef::ImageHeight, LTDC_LayerCfgTypeDef::ImageWidth, IS_LTDC_ALPHA, IS_LTDC_BLENDING_FACTOR1, IS_LTDC_BLENDING_FACTOR2, IS_LTDC_CFBLL, IS_LTDC_CFBLNBR, IS_LTDC_HCONFIGSP, IS_LTDC_HCONFIGST, IS_LTDC_LAYER, IS_LTDC_PIXEL_FORMAT, IS_LTDC_VCONFIGSP, IS_LTDC_VCONFIGST, LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), LTDC_LayerCfgTypeDef::PixelFormat, LTDC_HandleTypeDef::State, LTDC_LayerCfgTypeDef::WindowX0, LTDC_LayerCfgTypeDef::WindowX1, LTDC_LayerCfgTypeDef::WindowY0, and LTDC_LayerCfgTypeDef::WindowY1.

HAL_StatusTypeDef HAL_LTDC_DisableCLUT | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | LayerIdx
 | ) |  |

Disable the color lookup table.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 744 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, LTDC_HandleTypeDef::Instance, IS_LTDC_LAYER, LTDC_LAYER, and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | LayerIdx
 | ) |  |

Disable the color lookup table without reloading.

Variant of the function HAL_LTDC_DisableCLUT without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1730 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LAYER, LTDC_LAYER, and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_DisableColorKeying | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | LayerIdx
 | ) |  |

Disable the color keying.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 674 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, LTDC_HandleTypeDef::Instance, IS_LTDC_LAYER, LTDC_LAYER, and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | LayerIdx
 | ) |  |

Disable the color keying without reloading.

Variant of the function HAL_LTDC_DisableColorKeying without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1660 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LAYER, LTDC_LAYER, and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_DisableDither ( LTDC_HandleTypeDef * hltdc )

Disable Dither.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
HAL status

Definition at line 804 of file stm32h7xx_hal_ltdc.c.

References HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_EnableCLUT | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | LayerIdx
 | ) |  |

Enable the color lookup table.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 709 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, LTDC_HandleTypeDef::Instance, IS_LTDC_LAYER, LTDC_LAYER, and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | LayerIdx
 | ) |  |

Enable the color lookup table without reloading.

Variant of the function HAL_LTDC_EnableCLUT without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1695 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LAYER, LTDC_LAYER, and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_EnableColorKeying | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | LayerIdx
 | ) |  |

Enable the color keying.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 639 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, LTDC_HandleTypeDef::Instance, IS_LTDC_LAYER, LTDC_LAYER, and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | LayerIdx
 | ) |  |

Enable the color keying without reloading.

Variant of the function HAL_LTDC_EnableColorKeying without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1625 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LAYER, LTDC_LAYER, and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_EnableDither ( LTDC_HandleTypeDef * hltdc )

Enable Dither.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
HAL status

Definition at line 777 of file stm32h7xx_hal_ltdc.c.

References HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | Line
 | ) |  |

Define the position of the line interrupt.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Line | Line Interrupt Position.
Note:
User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation.
Return values:
HAL status

Definition at line 1147 of file stm32h7xx_hal_ltdc.c.

References __HAL_LTDC_DISABLE_IT, __HAL_LTDC_ENABLE_IT, assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LIPOS, LTDC_IT_LI, and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_Reload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | ReloadType
 | ) |  |

Reload LTDC Layers configuration.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
ReloadType | This parameter can be one of the following values : LTDC_RELOAD_IMMEDIATE : Immediate Reload LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking
Note:
User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation.
Return values:
HAL status

Definition at line 1186 of file stm32h7xx_hal_ltdc.c.

References __HAL_LTDC_ENABLE_IT, assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, LTDC_HandleTypeDef::Instance, IS_LTDC_RELOAD, LTDC_IT_RR, and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_SetAddress | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | Address,
 |  | uint32_t | LayerIdx
 | ) |  |

Reconfigure the frame buffer Address.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Address | new address value.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
Return values:
HAL status

Definition at line 1031 of file stm32h7xx_hal_ltdc.c.

References assert_param, LTDC_LayerCfgTypeDef::FBStartAdress, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, LTDC_HandleTypeDef::Instance, IS_LTDC_LAYER, LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | Address,
 |  | uint32_t | LayerIdx
 | ) |  |

Reconfigure the frame buffer Address without reloading.

Variant of the function HAL_LTDC_SetAddress without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Address | new address value.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
Return values:
HAL status

Definition at line 1473 of file stm32h7xx_hal_ltdc.c.

References assert_param, LTDC_LayerCfgTypeDef::FBStartAdress, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LAYER, LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_SetAlpha | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | Alpha,
 |  | uint32_t | LayerIdx
 | ) |  |

Reconfigure the layer alpha value.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Alpha | new alpha value.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 987 of file stm32h7xx_hal_ltdc.c.

References LTDC_LayerCfgTypeDef::Alpha, assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, LTDC_HandleTypeDef::Instance, IS_LTDC_ALPHA, IS_LTDC_LAYER, LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | Alpha,
 |  | uint32_t | LayerIdx
 | ) |  |

Reconfigure the layer alpha value without reloading.

Variant of the function HAL_LTDC_SetAlpha without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Alpha | new alpha value.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1428 of file stm32h7xx_hal_ltdc.c.

References LTDC_LayerCfgTypeDef::Alpha, assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_ALPHA, IS_LTDC_LAYER, LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_SetPitch | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | LinePitchInPixels,
 |  | uint32_t | LayerIdx
 | ) |  |

Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is larger than the one intended to be displayed on screen.

Example of a buffer 800x480 attached to layer for which we want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().

Note:
This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
LinePitchInPixels | New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
LayerIdx | LTDC layer index concerned by the modification of line pitch.
Return values:
HAL status

Definition at line 1078 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LAYER, LTDC_HandleTypeDef::LayerCfg, LTDC_LAYER, LTDC_PIXEL_FORMAT_AL88, LTDC_PIXEL_FORMAT_ARGB1555, LTDC_PIXEL_FORMAT_ARGB4444, LTDC_PIXEL_FORMAT_ARGB8888, LTDC_PIXEL_FORMAT_RGB565, LTDC_PIXEL_FORMAT_RGB888, LTDC_LayerCfgTypeDef::PixelFormat, and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | LinePitchInPixels,
 |  | uint32_t | LayerIdx
 | ) |  |

Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is larger than the one intended to be displayed on screen.

Example of a buffer 800x480 attached to layer for which we want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().

Note:
This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). Variant of the function HAL_LTDC_SetPitch without immediate reload.
Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
LinePitchInPixels | New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
LayerIdx | LTDC layer index concerned by the modification of line pitch.
Return values:
HAL status

Definition at line 1520 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LAYER, LTDC_HandleTypeDef::LayerCfg, LTDC_LAYER, LTDC_PIXEL_FORMAT_AL88, LTDC_PIXEL_FORMAT_ARGB1555, LTDC_PIXEL_FORMAT_ARGB4444, LTDC_PIXEL_FORMAT_ARGB8888, LTDC_PIXEL_FORMAT_RGB565, LTDC_PIXEL_FORMAT_RGB888, LTDC_LayerCfgTypeDef::PixelFormat, and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_SetPixelFormat | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | Pixelformat,
 |  | uint32_t | LayerIdx
 | ) |  |

Reconfigure the pixel format.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Pixelformat | new pixel format value.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
Return values:
HAL status

Definition at line 942 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, LTDC_HandleTypeDef::Instance, IS_LTDC_LAYER, IS_LTDC_PIXEL_FORMAT, LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), LTDC_LayerCfgTypeDef::PixelFormat, and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | Pixelformat,
 |  | uint32_t | LayerIdx
 | ) |  |

Reconfigure the pixel format without reloading.

Variant of the function HAL_LTDC_SetPixelFormat without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDfef structure that contains the configuration information for the LTDC.
Pixelformat | new pixel format value.
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
Return values:
HAL status

Definition at line 1383 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, IS_LTDC_LAYER, IS_LTDC_PIXEL_FORMAT, LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), LTDC_LayerCfgTypeDef::PixelFormat, and LTDC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LTDC_SetWindowPosition | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | X0,
 |  | uint32_t | Y0,
 |  | uint32_t | LayerIdx
 | ) |  |

Set the LTDC window position.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
X0 | LTDC window X offset
Y0 | LTDC window Y offset
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 891 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, LTDC_LayerCfgTypeDef::ImageHeight, LTDC_LayerCfgTypeDef::ImageWidth, LTDC_HandleTypeDef::Instance, IS_LTDC_CFBLL, IS_LTDC_CFBLNBR, IS_LTDC_LAYER, LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), LTDC_HandleTypeDef::State, LTDC_LayerCfgTypeDef::WindowX0, LTDC_LayerCfgTypeDef::WindowX1, LTDC_LayerCfgTypeDef::WindowY0, and LTDC_LayerCfgTypeDef::WindowY1.

HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | X0,
 |  | uint32_t | Y0,
 |  | uint32_t | LayerIdx
 | ) |  |

Set the LTDC window position without reloading.

Variant of the function HAL_LTDC_SetWindowPosition without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
X0 | LTDC window X offset
Y0 | LTDC window Y offset
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1332 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, LTDC_LayerCfgTypeDef::ImageHeight, LTDC_LayerCfgTypeDef::ImageWidth, IS_LTDC_CFBLL, IS_LTDC_CFBLNBR, IS_LTDC_LAYER, LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), LTDC_HandleTypeDef::State, LTDC_LayerCfgTypeDef::WindowX0, LTDC_LayerCfgTypeDef::WindowX1, LTDC_LayerCfgTypeDef::WindowY0, and LTDC_LayerCfgTypeDef::WindowY1.

HAL_StatusTypeDef HAL_LTDC_SetWindowSize | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | XSize,
 |  | uint32_t | YSize,
 |  | uint32_t | LayerIdx
 | ) |  |

Set the LTDC window size.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
XSize | LTDC Pixel per line
YSize | LTDC Line number
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 835 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, LTDC_LayerCfgTypeDef::ImageHeight, LTDC_LayerCfgTypeDef::ImageWidth, LTDC_HandleTypeDef::Instance, IS_LTDC_CFBLL, IS_LTDC_CFBLNBR, IS_LTDC_LAYER, LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), LTDC_HandleTypeDef::State, LTDC_LayerCfgTypeDef::WindowX0, LTDC_LayerCfgTypeDef::WindowX1, LTDC_LayerCfgTypeDef::WindowY0, and LTDC_LayerCfgTypeDef::WindowY1.

HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload | ( | LTDC_HandleTypeDef * | hltdc,
 |  | uint32_t | XSize,
 |  | uint32_t | YSize,
 |  | uint32_t | LayerIdx
 | ) |  |

Set the LTDC window size without reloading.

Variant of the function HAL_LTDC_SetWindowSize without immediate reload.

Parameters:
hltdc | pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
XSize | LTDC Pixel per line
YSize | LTDC Line number
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
HAL status

Definition at line 1276 of file stm32h7xx_hal_ltdc.c.

References assert_param, HAL_LTDC_STATE_BUSY, HAL_LTDC_STATE_READY, LTDC_LayerCfgTypeDef::ImageHeight, LTDC_LayerCfgTypeDef::ImageWidth, IS_LTDC_CFBLL, IS_LTDC_CFBLNBR, IS_LTDC_LAYER, LTDC_HandleTypeDef::LayerCfg, LTDC_SetConfig(), LTDC_HandleTypeDef::State, LTDC_LayerCfgTypeDef::WindowX0, LTDC_LayerCfgTypeDef::WindowX1, LTDC_LayerCfgTypeDef::WindowY0, and LTDC_LayerCfgTypeDef::WindowY1.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
LTDC Exported Functions

Peripheral State and Errors functions. More...

Functions

HAL_LTDC_StateTypeDef | HAL_LTDC_GetState (LTDC_HandleTypeDef *hltdc)
Return the LTDC handle state.
uint32_t | HAL_LTDC_GetError (LTDC_HandleTypeDef *hltdc)
Return the LTDC handle error code.

Detailed Description

Peripheral State and Errors functions.

 ===============================================================================
                  ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the LTDC handle state.
      (+) Get the LTDC handle error code.

Function Documentation

uint32_t HAL_LTDC_GetError ( LTDC_HandleTypeDef * hltdc )

Return the LTDC handle error code.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
LTDC Error Code

Definition at line 1792 of file stm32h7xx_hal_ltdc.c.

References LTDC_HandleTypeDef::ErrorCode.

HAL_LTDC_StateTypeDef HAL_LTDC_GetState ( LTDC_HandleTypeDef * hltdc )

Return the LTDC handle state.

Parameters:
hltdc pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
Return values:
HAL state

Definition at line 1781 of file stm32h7xx_hal_ltdc.c.

References LTDC_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC Exported Functions

Modules | Functions
LTDC Exported Functions
LTDC

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State and Errors functions

Peripheral State and Errors functions.

Functions

static void LTDC_SetConfig (LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
Configures the LTDC peripheral.

Function Documentation

static void LTDC_SetConfig | ( | LTDC_HandleTypeDef * | hltdc,
 |  | LTDC_LayerCfgTypeDef * | pLayerCfg,
 |  | uint32_t | LayerIdx
 | ) |  | [static]

Configures the LTDC peripheral.

Parameters:
hltdc | : Pointer to a LTDC_HandleTypeDef structure that contains the configuration information for the LTDC.
pLayerCfg | Pointer LTDC Layer Configuration structure
LayerIdx | LTDC Layer index. This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
Return values:
None

Definition at line 1810 of file stm32h7xx_hal_ltdc.c.

References LTDC_LayerCfgTypeDef::Alpha, LTDC_LayerCfgTypeDef::Alpha0, LTDC_LayerCfgTypeDef::Backcolor, LTDC_LayerCfgTypeDef::BlendingFactor1, LTDC_LayerCfgTypeDef::BlendingFactor2, LTDC_ColorTypeDef::Blue, LTDC_LayerCfgTypeDef::FBStartAdress, LTDC_ColorTypeDef::Green, LTDC_LayerCfgTypeDef::ImageHeight, LTDC_LayerCfgTypeDef::ImageWidth, LTDC_HandleTypeDef::Instance, LTDC_LAYER, LTDC_PIXEL_FORMAT_AL88, LTDC_PIXEL_FORMAT_ARGB1555, LTDC_PIXEL_FORMAT_ARGB4444, LTDC_PIXEL_FORMAT_ARGB8888, LTDC_PIXEL_FORMAT_RGB565, LTDC_PIXEL_FORMAT_RGB888, LTDC_LayerCfgTypeDef::PixelFormat, LTDC_ColorTypeDef::Red, LTDC_LayerCfgTypeDef::WindowX0, LTDC_LayerCfgTypeDef::WindowX1, LTDC_LayerCfgTypeDef::WindowY0, and LTDC_LayerCfgTypeDef::WindowY1.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetAddress(), HAL_LTDC_SetAddress_NoReload(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetAlpha_NoReload(), HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetPixelFormat_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), and HAL_LTDC_SetWindowSize_NoReload().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC Exported Types

Data Structures | Defines | Enumerations
LTDC Exported Types
LTDC

Data Structures

struct | LTDC_ColorTypeDef
LTDC color structure definition. More...
struct | LTDC_InitTypeDef
LTDC Init structure definition. More...
struct | LTDC_LayerCfgTypeDef
LTDC Layer structure definition. More...
struct | LTDC_HandleTypeDef
LTDC handle Structure definition. More...

Defines

#define | MAX_LAYER 2U

Enumerations

enum HAL_LTDC_StateTypeDef {
HAL_LTDC_STATE_RESET = 0x00U, HAL_LTDC_STATE_READY = 0x01U, HAL_LTDC_STATE_BUSY = 0x02U, HAL_LTDC_STATE_TIMEOUT = 0x03U,
HAL_LTDC_STATE_ERROR = 0x04U
}
HAL LTDC State enumeration definition. More...

Define Documentation

#define MAX_LAYER 2U

Definition at line 63 of file stm32h7xx_hal_ltdc.h.

Enumeration Type Documentation

enum HAL_LTDC_StateTypeDef

HAL LTDC State enumeration definition.

Enumerator:
HAL_LTDC_STATE_RESET

LTDC not yet initialized or disabled

HAL_LTDC_STATE_READY

LTDC initialized and ready for use

HAL_LTDC_STATE_BUSY

LTDC internal process is ongoing

HAL_LTDC_STATE_TIMEOUT

LTDC Timeout state

HAL_LTDC_STATE_ERROR

LTDC state error

Definition at line 172 of file stm32h7xx_hal_ltdc.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC_ColorTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LTDC_ColorTypeDef Struct Reference
LTDC Exported Types

LTDC color structure definition. More...

#include <stm32h7xx_hal_ltdc.h>

Data Fields

uint8_t | Blue
uint8_t | Green
uint8_t | Red
uint8_t | Reserved

Detailed Description

LTDC color structure definition.

Definition at line 68 of file stm32h7xx_hal_ltdc.h.

Field Documentation

uint8_t LTDC_ColorTypeDef::Blue

Configures the blue value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

Definition at line 70 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init(), and LTDC_SetConfig().

uint8_t LTDC_ColorTypeDef::Green

Configures the green value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

Definition at line 73 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init(), and LTDC_SetConfig().

uint8_t LTDC_ColorTypeDef::Red

Configures the red value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

Definition at line 76 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init(), and LTDC_SetConfig().

uint8_t LTDC_ColorTypeDef::Reserved

Reserved 0xFF

Definition at line 79 of file stm32h7xx_hal_ltdc.h.

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_ltdc.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LTDC_InitTypeDef Struct Reference
LTDC Exported Types

LTDC Init structure definition. More...

#include <stm32h7xx_hal_ltdc.h>

Data Fields

uint32_t | HSPolarity
uint32_t | VSPolarity
uint32_t | DEPolarity
uint32_t | PCPolarity
uint32_t | HorizontalSync
uint32_t | VerticalSync
uint32_t | AccumulatedHBP
uint32_t | AccumulatedVBP
uint32_t | AccumulatedActiveW
uint32_t | AccumulatedActiveH
uint32_t | TotalWidth
uint32_t | TotalHeigh
LTDC_ColorTypeDef Backcolor

Detailed Description

LTDC Init structure definition.

Definition at line 85 of file stm32h7xx_hal_ltdc.h.

Field Documentation

uint32_t LTDC_InitTypeDef::AccumulatedActiveH

configures the accumulated active height. This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF.

Definition at line 114 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::AccumulatedActiveW

configures the accumulated active width. This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF.

Definition at line 111 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::AccumulatedHBP

configures the accumulated horizontal back porch width. This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF.

Definition at line 105 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::AccumulatedVBP

configures the accumulated vertical back porch height. This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF.

Definition at line 108 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

LTDC_ColorTypeDef LTDC_InitTypeDef::Backcolor

Configures the background color.

Definition at line 123 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::DEPolarity

configures the data enable polarity. This parameter can be one of value of LTDC DE POLARITY

Definition at line 93 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::HorizontalSync

configures the number of Horizontal synchronization width. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF.

Definition at line 99 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::HSPolarity

configures the horizontal synchronization polarity. This parameter can be one value of LTDC HS POLARITY

Definition at line 87 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::PCPolarity

configures the pixel clock polarity. This parameter can be one of value of LTDC PC POLARITY

Definition at line 96 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::TotalHeigh

configures the total height. This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF.

Definition at line 120 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::TotalWidth

configures the total width. This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF.

Definition at line 117 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::VerticalSync

configures the number of Vertical synchronization height. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF.

Definition at line 102 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

uint32_t LTDC_InitTypeDef::VSPolarity

configures the vertical synchronization polarity. This parameter can be one value of LTDC VS POLARITY

Definition at line 90 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_ltdc.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC_LayerCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LTDC_LayerCfgTypeDef Struct Reference
LTDC Exported Types

LTDC Layer structure definition. More...

#include <stm32h7xx_hal_ltdc.h>

Data Fields

uint32_t | WindowX0
uint32_t | WindowX1
uint32_t | WindowY0
uint32_t | WindowY1
uint32_t | PixelFormat
uint32_t | Alpha
uint32_t | Alpha0
uint32_t | BlendingFactor1
uint32_t | BlendingFactor2
uint32_t | FBStartAdress
uint32_t | ImageWidth
uint32_t | ImageHeight
LTDC_ColorTypeDef Backcolor

Detailed Description

LTDC Layer structure definition.

Definition at line 129 of file stm32h7xx_hal_ltdc.h.

Field Documentation

uint32_t LTDC_LayerCfgTypeDef::Alpha

Specifies the constant alpha used for blending. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

Definition at line 146 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetAlpha_NoReload(), and LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::Alpha0

Configures the default alpha value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

Definition at line 149 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), and LTDC_SetConfig().

LTDC_ColorTypeDef LTDC_LayerCfgTypeDef::Backcolor

Configures the layer background color.

Definition at line 166 of file stm32h7xx_hal_ltdc.h.

Referenced by LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::BlendingFactor1

Select the blending factor 1. This parameter can be one of value of LTDC Blending Factor1

Definition at line 152 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), and LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::BlendingFactor2

Select the blending factor 2. This parameter can be one of value of LTDC Blending Factor2

Definition at line 155 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), and LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::FBStartAdress

Configures the color frame buffer address

Definition at line 158 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_SetAddress(), HAL_LTDC_SetAddress_NoReload(), and LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::ImageHeight

Specifies the number of line in frame buffer. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF.

Definition at line 163 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), HAL_LTDC_SetWindowSize_NoReload(), and LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::ImageWidth

Configures the color frame buffer line length. This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF.

Definition at line 160 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), HAL_LTDC_SetWindowSize_NoReload(), and LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::PixelFormat

Specifies the pixel format. This parameter can be one of value of LTDC Pixel format

Definition at line 143 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigCLUT(), HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetPixelFormat_NoReload(), and LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::WindowX0

Configures the Window Horizontal Start Position. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF.

Definition at line 131 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), HAL_LTDC_SetWindowSize_NoReload(), and LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::WindowX1

Configures the Window Horizontal Stop Position. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF.

Definition at line 134 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), HAL_LTDC_SetWindowSize_NoReload(), and LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::WindowY0

Configures the Window vertical Start Position. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF.

Definition at line 137 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), HAL_LTDC_SetWindowSize_NoReload(), and LTDC_SetConfig().

uint32_t LTDC_LayerCfgTypeDef::WindowY1

Configures the Window vertical Stop Position. This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF.

Definition at line 140 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), HAL_LTDC_SetWindowSize_NoReload(), and LTDC_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_ltdc.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LTDC_HandleTypeDef Struct Reference
LTDC Exported Types

LTDC handle Structure definition. More...

#include <stm32h7xx_hal_ltdc.h>

Data Fields

LTDC_TypeDef * | Instance
LTDC_InitTypeDef Init
LTDC_LayerCfgTypeDef LayerCfg [MAX_LAYER]
HAL_LockTypeDef | Lock
__IO HAL_LTDC_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

LTDC handle Structure definition.

Definition at line 184 of file stm32h7xx_hal_ltdc.h.

Field Documentation

__IO uint32_t LTDC_HandleTypeDef::ErrorCode

LTDC Error code

Definition at line 196 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_DeInit(), HAL_LTDC_GetError(), HAL_LTDC_Init(), and HAL_LTDC_IRQHandler().

LTDC_InitTypeDef LTDC_HandleTypeDef::Init

LTDC parameters

Definition at line 188 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

LTDC_TypeDef* LTDC_HandleTypeDef::Instance

LTDC Register base address

Definition at line 186 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigColorKeying(), HAL_LTDC_ConfigLayer(), HAL_LTDC_DisableCLUT(), HAL_LTDC_DisableColorKeying(), HAL_LTDC_EnableCLUT(), HAL_LTDC_EnableColorKeying(), HAL_LTDC_Init(), HAL_LTDC_Reload(), HAL_LTDC_SetAddress(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowSize(), and LTDC_SetConfig().

LTDC_LayerCfgTypeDef LTDC_HandleTypeDef::LayerCfg[MAX_LAYER]

LTDC Layers parameters

Definition at line 190 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigCLUT(), HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetAddress(), HAL_LTDC_SetAddress_NoReload(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetAlpha_NoReload(), HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetPixelFormat_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), and HAL_LTDC_SetWindowSize_NoReload().

HAL_LockTypeDef LTDC_HandleTypeDef::Lock

LTDC Lock

Definition at line 192 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

__IO HAL_LTDC_StateTypeDef LTDC_HandleTypeDef::State

LTDC state

Definition at line 194 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigCLUT(), HAL_LTDC_ConfigColorKeying(), HAL_LTDC_ConfigColorKeying_NoReload(), HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_DeInit(), HAL_LTDC_DisableCLUT(), HAL_LTDC_DisableCLUT_NoReload(), HAL_LTDC_DisableColorKeying(), HAL_LTDC_DisableColorKeying_NoReload(), HAL_LTDC_DisableDither(), HAL_LTDC_EnableCLUT(), HAL_LTDC_EnableCLUT_NoReload(), HAL_LTDC_EnableColorKeying(), HAL_LTDC_EnableColorKeying_NoReload(), HAL_LTDC_EnableDither(), HAL_LTDC_GetState(), HAL_LTDC_Init(), HAL_LTDC_IRQHandler(), HAL_LTDC_ProgramLineEvent(), HAL_LTDC_Reload(), HAL_LTDC_SetAddress(), HAL_LTDC_SetAddress_NoReload(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetAlpha_NoReload(), HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetPixelFormat_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), and HAL_LTDC_SetWindowSize_NoReload().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_ltdc.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC Error Code

Defines
LTDC Error Code
LTDC Exported Constants

Defines

#define | HAL_LTDC_ERROR_NONE (0x00000000U)
#define | HAL_LTDC_ERROR_TE (0x00000001U)
#define | HAL_LTDC_ERROR_FU (0x00000002U)
#define | HAL_LTDC_ERROR_TIMEOUT (0x00000020U)

Define Documentation

#define HAL_LTDC_ERROR_FU (0x00000002U)

LTDC FIFO Underrun

Definition at line 213 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler().

#define HAL_LTDC_ERROR_NONE (0x00000000U)

LTDC No error

Definition at line 211 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_DeInit(), and HAL_LTDC_Init().

#define HAL_LTDC_ERROR_TE (0x00000001U)

LTDC Transfer error

Definition at line 212 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler().

#define HAL_LTDC_ERROR_TIMEOUT (0x00000020U)

LTDC Timeout error

Definition at line 214 of file stm32h7xx_hal_ltdc.h.

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STM32H753xx HAL User Manual: LTDC Layer

Defines
LTDC Layer
LTDC Exported Constants

Defines

#define | LTDC_LAYER_1 (0x00000000U)
#define | LTDC_LAYER_2 (0x00000001U)

Define Documentation

#define LTDC_LAYER_1 (0x00000000U)

LTDC Layer 1

Definition at line 222 of file stm32h7xx_hal_ltdc.h.

#define LTDC_LAYER_2 (0x00000001U)

LTDC Layer 2

Definition at line 223 of file stm32h7xx_hal_ltdc.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC HS POLARITY

Defines
LTDC HS POLARITY
LTDC Exported Constants

Defines

#define | LTDC_HSPOLARITY_AL (0x00000000U)
#define | LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL

Define Documentation

#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL

Horizontal Synchronization is active high.

Definition at line 233 of file stm32h7xx_hal_ltdc.h.

#define LTDC_HSPOLARITY_AL (0x00000000U)

Horizontal Synchronization is active low.

Definition at line 232 of file stm32h7xx_hal_ltdc.h.

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STM32H753xx HAL User Manual: LTDC VS POLARITY

Defines
LTDC VS POLARITY
LTDC Exported Constants

Defines

#define | LTDC_VSPOLARITY_AL (0x00000000U)
#define | LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL

Define Documentation

#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL

Vertical Synchronization is active high.

Definition at line 242 of file stm32h7xx_hal_ltdc.h.

#define LTDC_VSPOLARITY_AL (0x00000000U)

Vertical Synchronization is active low.

Definition at line 241 of file stm32h7xx_hal_ltdc.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC DE POLARITY

Defines
LTDC DE POLARITY
LTDC Exported Constants

Defines

#define | LTDC_DEPOLARITY_AL (0x00000000U)
#define | LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL

Define Documentation

#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL

Data Enable, is active high.

Definition at line 251 of file stm32h7xx_hal_ltdc.h.

#define LTDC_DEPOLARITY_AL (0x00000000U)

Data Enable, is active low.

Definition at line 250 of file stm32h7xx_hal_ltdc.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC PC POLARITY

Defines
LTDC PC POLARITY
LTDC Exported Constants

Defines

#define | LTDC_PCPOLARITY_IPC (0x00000000U)
#define | LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL

Define Documentation

#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL

inverted input pixel clock.

Definition at line 260 of file stm32h7xx_hal_ltdc.h.

#define LTDC_PCPOLARITY_IPC (0x00000000U)

input pixel clock.

Definition at line 259 of file stm32h7xx_hal_ltdc.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC SYNC

Defines
LTDC SYNC
LTDC Exported Constants

Defines

#define | LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16)
#define | LTDC_VERTICALSYNC LTDC_SSCR_VSH

Define Documentation

#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16)

Horizontal synchronization width.

Definition at line 268 of file stm32h7xx_hal_ltdc.h.

#define LTDC_VERTICALSYNC LTDC_SSCR_VSH

Vertical synchronization height.

Definition at line 269 of file stm32h7xx_hal_ltdc.h.

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STM32H753xx HAL User Manual: LTDC BACK COLOR

Defines
LTDC BACK COLOR
LTDC Exported Constants

Defines

#define LTDC_COLOR (0x000000FFU)

Define Documentation

#define LTDC_COLOR (0x000000FFU)

Color mask

Definition at line 277 of file stm32h7xx_hal_ltdc.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC Blending Factor1

Defines
LTDC Blending Factor1
LTDC Exported Constants

Defines

#define | LTDC_BLENDING_FACTOR1_CA (0x00000400U)
#define | LTDC_BLENDING_FACTOR1_PAxCA (0x00000600U)

Define Documentation

#define LTDC_BLENDING_FACTOR1_CA (0x00000400U)

Blending factor : Cte Alpha

Definition at line 285 of file stm32h7xx_hal_ltdc.h.

#define LTDC_BLENDING_FACTOR1_PAxCA (0x00000600U)

Blending factor : Cte Alpha x Pixel Alpha

Definition at line 286 of file stm32h7xx_hal_ltdc.h.

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STM32H753xx HAL User Manual: LTDC Blending Factor2

Defines
LTDC Blending Factor2
LTDC Exported Constants

Defines

#define | LTDC_BLENDING_FACTOR2_CA (0x00000005U)
#define | LTDC_BLENDING_FACTOR2_PAxCA (0x00000007U)

Define Documentation

#define LTDC_BLENDING_FACTOR2_CA (0x00000005U)

Blending factor : Cte Alpha

Definition at line 294 of file stm32h7xx_hal_ltdc.h.

#define LTDC_BLENDING_FACTOR2_PAxCA (0x00000007U)

Blending factor : Cte Alpha x Pixel Alpha

Definition at line 295 of file stm32h7xx_hal_ltdc.h.

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STM32H753xx HAL User Manual: LTDC Pixel format

Defines
LTDC Pixel format
LTDC Exported Constants

Defines

#define | LTDC_PIXEL_FORMAT_ARGB8888 (0x00000000U)
#define | LTDC_PIXEL_FORMAT_RGB888 (0x00000001U)
#define | LTDC_PIXEL_FORMAT_RGB565 (0x00000002U)
#define | LTDC_PIXEL_FORMAT_ARGB1555 (0x00000003U)
#define | LTDC_PIXEL_FORMAT_ARGB4444 (0x00000004U)
#define | LTDC_PIXEL_FORMAT_L8 (0x00000005U)
#define | LTDC_PIXEL_FORMAT_AL44 (0x00000006U)
#define | LTDC_PIXEL_FORMAT_AL88 (0x00000007U)

Define Documentation

#define LTDC_PIXEL_FORMAT_AL44 (0x00000006U)

AL44 LTDC pixel format

Definition at line 309 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigCLUT().

#define LTDC_PIXEL_FORMAT_AL88 (0x00000007U)

AL88 LTDC pixel format

Definition at line 310 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), and LTDC_SetConfig().

#define LTDC_PIXEL_FORMAT_ARGB1555 (0x00000003U)

ARGB1555 LTDC pixel format

Definition at line 306 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), and LTDC_SetConfig().

#define LTDC_PIXEL_FORMAT_ARGB4444 (0x00000004U)

ARGB4444 LTDC pixel format

Definition at line 307 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), and LTDC_SetConfig().

#define LTDC_PIXEL_FORMAT_ARGB8888 (0x00000000U)

ARGB8888 LTDC pixel format

Definition at line 303 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), and LTDC_SetConfig().

#define LTDC_PIXEL_FORMAT_L8 (0x00000005U)

L8 LTDC pixel format

Definition at line 308 of file stm32h7xx_hal_ltdc.h.

#define LTDC_PIXEL_FORMAT_RGB565 (0x00000002U)

RGB565 LTDC pixel format

Definition at line 305 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), and LTDC_SetConfig().

#define LTDC_PIXEL_FORMAT_RGB888 (0x00000001U)

RGB888 LTDC pixel format

Definition at line 304 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), and LTDC_SetConfig().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC Alpha

Defines
LTDC Alpha
LTDC Exported Constants

Defines

#define LTDC_ALPHA LTDC_LxCACR_CONSTA

Define Documentation

#define LTDC_ALPHA LTDC_LxCACR_CONSTA

LTDC Cte Alpha mask

Definition at line 318 of file stm32h7xx_hal_ltdc.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC LAYER Config

Defines
LTDC LAYER Config
LTDC Exported Constants

Defines

#define | LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16)
#define | LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS
#define | LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL
#define | LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR

Define Documentation

#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL

LTDC Layer Line length

Definition at line 329 of file stm32h7xx_hal_ltdc.h.

#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR

LTDC Layer Line number

Definition at line 330 of file stm32h7xx_hal_ltdc.h.

#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS

LTDC Layer start position

Definition at line 327 of file stm32h7xx_hal_ltdc.h.

#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16)

LTDC Layer stop position

Definition at line 326 of file stm32h7xx_hal_ltdc.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC Interrupts

Defines
LTDC Interrupts
LTDC Exported Constants

Defines

#define | LTDC_IT_LI LTDC_IER_LIE
#define | LTDC_IT_FU LTDC_IER_FUIE
#define | LTDC_IT_TE LTDC_IER_TERRIE
#define | LTDC_IT_RR LTDC_IER_RRIE

Define Documentation

#define LTDC_IT_FU LTDC_IER_FUIE

Definition at line 339 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init(), and HAL_LTDC_IRQHandler().

#define LTDC_IT_LI LTDC_IER_LIE

Definition at line 338 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler(), and HAL_LTDC_ProgramLineEvent().

#define LTDC_IT_RR LTDC_IER_RRIE

Definition at line 341 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler(), and HAL_LTDC_Reload().

#define LTDC_IT_TE LTDC_IER_TERRIE

Definition at line 340 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init(), and HAL_LTDC_IRQHandler().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC Flags

Defines
LTDC Flags
LTDC Exported Constants

Defines

#define | LTDC_FLAG_LI LTDC_ISR_LIF
#define | LTDC_FLAG_FU LTDC_ISR_FUIF
#define | LTDC_FLAG_TE LTDC_ISR_TERRIF
#define | LTDC_FLAG_RR LTDC_ISR_RRIF

Define Documentation

#define LTDC_FLAG_FU LTDC_ISR_FUIF

Definition at line 350 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler().

#define LTDC_FLAG_LI LTDC_ISR_LIF

Definition at line 349 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler().

#define LTDC_FLAG_RR LTDC_ISR_RRIF

Definition at line 352 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler().

#define LTDC_FLAG_TE LTDC_ISR_TERRIF

Definition at line 351 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler().

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STM32H753xx HAL User Manual: LTDC Reload Type

Defines
LTDC Reload Type
LTDC Exported Constants

Defines

#define | LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR
#define | LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR

Define Documentation

#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR

Immediate Reload

Definition at line 360 of file stm32h7xx_hal_ltdc.h.

#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR

Vertical Blanking Reload

Definition at line 361 of file stm32h7xx_hal_ltdc.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC Exported Macros

Defines
LTDC Exported Macros
LTDC

Defines

#define | __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
Reset LTDC handle state.
#define | __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
Enable the LTDC.
#define | __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
Disable the LTDC.
#define | __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
Enable the LTDC Layer.
#define | __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
Disable the LTDC Layer.
#define | __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
Reload immediately all LTDC Layers.
#define | __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR)
Reload during vertical blanking period all LTDC Layers.
#define | __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
Get the LTDC pending flags.
#define | __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clears the LTDC pending flags.
#define | __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enables the specified LTDC interrupts.
#define | __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
Disables the specified LTDC interrupts.
#define | __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
Checks whether the specified LTDC interrupt has occurred or not.

Define Documentation

#define __HAL_LTDC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clears the LTDC pending flags.

Parameters:
__HANDLE__,: LTDC handle
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • LTDC_FLAG_LI: Line Interrupt flag
  • LTDC_FLAG_FU: FIFO Underrun Interrupt flag
  • LTDC_FLAG_TE: Transfer Error interrupt flag
  • LTDC_FLAG_RR: Register Reload Interrupt Flag
Return values:
None

Definition at line 452 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler().

#define __HAL_LTDC_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))

Disable the LTDC.

Parameters:
__HANDLE__,: LTDC handle
Return values:
None.

Definition at line 393 of file stm32h7xx_hal_ltdc.h.

#define __HAL_LTDC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))

Disables the specified LTDC interrupts.

Parameters:
__HANDLE__,: LTDC handle
__INTERRUPT__,: specifies the LTDC interrupt sources to be disabled. This parameter can be any combination of the following values:
  • LTDC_IT_LI: Line Interrupt flag
  • LTDC_IT_FU: FIFO Underrun Interrupt flag
  • LTDC_IT_TE: Transfer Error interrupt flag
  • LTDC_IT_RR: Register Reload Interrupt Flag
Return values:
None

Definition at line 478 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler(), and HAL_LTDC_ProgramLineEvent().

#define __HAL_LTDC_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)

Enable the LTDC.

Parameters:
__HANDLE__,: LTDC handle
Return values:
None.

Definition at line 386 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define __HAL_LTDC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enables the specified LTDC interrupts.

Parameters:
__HANDLE__,: LTDC handle
__INTERRUPT__,: specifies the LTDC interrupt sources to be enabled. This parameter can be any combination of the following values:
  • LTDC_IT_LI: Line Interrupt flag
  • LTDC_IT_FU: FIFO Underrun Interrupt flag
  • LTDC_IT_TE: Transfer Error interrupt flag
  • LTDC_IT_RR: Register Reload Interrupt Flag
Return values:
None

Definition at line 465 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init(), HAL_LTDC_ProgramLineEvent(), and HAL_LTDC_Reload().

#define __HAL_LTDC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR & (__FLAG__))

Get the LTDC pending flags.

Parameters:
__HANDLE__,: LTDC handle
__FLAG__,: Get the specified flag. This parameter can be any combination of the following values:
  • LTDC_FLAG_LI: Line Interrupt flag
  • LTDC_FLAG_FU: FIFO Underrun Interrupt flag
  • LTDC_FLAG_TE: Transfer Error interrupt flag
  • LTDC_FLAG_RR: Register Reload Interrupt Flag
Return values:
The state of FLAG (SET or RESET).

Definition at line 439 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler().

#define __HAL_LTDC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER & (__INTERRUPT__))

Checks whether the specified LTDC interrupt has occurred or not.

Parameters:
__HANDLE__,: LTDC handle
__INTERRUPT__,: specifies the LTDC interrupt source to check. This parameter can be one of the following values:
  • LTDC_IT_LI: Line Interrupt flag
  • LTDC_IT_FU: FIFO Underrun Interrupt flag
  • LTDC_IT_TE: Transfer Error interrupt flag
  • LTDC_IT_RR: Register Reload Interrupt Flag
Return values:
The state of INTERRUPT (SET or RESET).

Definition at line 491 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_IRQHandler().

#define __HAL_LTDC_LAYER_DISABLE | ( | __HANDLE__,
 |  | __LAYER__
 | ) | ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)

Disable the LTDC Layer.

Parameters:
__HANDLE__ | LTDC handle
__LAYER__ | Specify the layer to be disabled. This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
Return values:
None.

Definition at line 411 of file stm32h7xx_hal_ltdc.h.

#define __HAL_LTDC_LAYER_ENABLE | ( | __HANDLE__,
 |  | __LAYER__
 | ) | ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)

Enable the LTDC Layer.

Parameters:
__HANDLE__ | LTDC handle
__LAYER__ | Specify the layer to be enabled. This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
Return values:
None.

Definition at line 402 of file stm32h7xx_hal_ltdc.h.

#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG ( __HANDLE__ ) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)

Reload immediately all LTDC Layers.

Parameters:
__HANDLE__ LTDC handle
Return values:
None.

Definition at line 418 of file stm32h7xx_hal_ltdc.h.

#define __HAL_LTDC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)

Reset LTDC handle state.

Parameters:
__HANDLE__ LTDC handle
Return values:
None

Definition at line 379 of file stm32h7xx_hal_ltdc.h.

#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG ( __HANDLE__ ) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR)

Reload during vertical blanking period all LTDC Layers.

Parameters:
__HANDLE__ LTDC handle
Return values:
None.

Definition at line 425 of file stm32h7xx_hal_ltdc.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC Private Types

LTDC Private Types
LTDC
Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC Private Variables

LTDC Private Variables
LTDC
Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC Private Constants

LTDC Private Constants
LTDC
Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC Private Macros

Defines
LTDC Private Macros
LTDC

Defines

#define | LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__)))))
#define | IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER)
#define | IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
#define | IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
#define | IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH))
#define | IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC))
#define | IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC)
#define | IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC)
#define | IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC)
#define | IS_LTDC_AVBP(__AVBP__) ((__AVBP__) <= LTDC_VERTICALSYNC)
#define | IS_LTDC_AAW(__AAW__) ((__AAW__) <= LTDC_HORIZONTALSYNC)
#define | IS_LTDC_AAH(__AAH__) ((__AAH__) <= LTDC_VERTICALSYNC)
#define | IS_LTDC_TOTALW(__TOTALW__) ((__TOTALW__) <= LTDC_HORIZONTALSYNC)
#define | IS_LTDC_TOTALH(__TOTALH__) ((__TOTALH__) <= LTDC_VERTICALSYNC)
#define | IS_LTDC_BLUEVALUE(__BBLUE__) ((__BBLUE__) <= LTDC_COLOR)
#define | IS_LTDC_GREENVALUE(__BGREEN__) ((__BGREEN__) <= LTDC_COLOR)
#define | IS_LTDC_REDVALUE(__BRED__) ((__BRED__) <= LTDC_COLOR)
#define | IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__)
#define | IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR2__)
#define | IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__)
#define | IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA)
#define | IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION)
#define | IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION)
#define | IS_LTDC_VCONFIGST(__VCONFIGST__) ((__VCONFIGST__) <= LTDC_STARTPOSITION)
#define | IS_LTDC_VCONFIGSP(__VCONFIGSP__) ((__VCONFIGSP__) <= LTDC_STOPPOSITION)
#define | IS_LTDC_CFBP(__CFBP__) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER)
#define | IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)
#define | IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER)
#define | IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU)
#define | IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))

Define Documentation

#define IS_LTDC_AAH ( __AAH__ ) ((__AAH__) <= LTDC_VERTICALSYNC)

Definition at line 623 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_AAW ( __AAW__ ) ((__AAW__) <= LTDC_HORIZONTALSYNC)

Definition at line 622 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_AHBP ( __AHBP__ ) ((__AHBP__) <= LTDC_HORIZONTALSYNC)

Definition at line 620 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_ALPHA ( __ALPHA__ ) ((__ALPHA__) <= LTDC_ALPHA)

Definition at line 639 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetAlpha(), and HAL_LTDC_SetAlpha_NoReload().

#define IS_LTDC_AVBP ( __AVBP__ ) ((__AVBP__) <= LTDC_VERTICALSYNC)

Definition at line 621 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_BLENDING_FACTOR1 ( __BLENDING_FACTOR1__ )
Value:
(((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \
                                                        ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA))

Definition at line 629 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), and HAL_LTDC_ConfigLayer_NoReload().

#define IS_LTDC_BLENDING_FACTOR2 ( __BLENDING_FACTOR2__ )
Value:
(((__BLENDING_FACTOR2__) == LTDC_BLENDING_FACTOR2_CA) || \
                                                        ((__BLENDING_FACTOR2__) == LTDC_BLENDING_FACTOR2_PAxCA))

Definition at line 631 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), and HAL_LTDC_ConfigLayer_NoReload().

#define IS_LTDC_BLUEVALUE ( __BBLUE__ ) ((__BBLUE__) <= LTDC_COLOR)

Definition at line 626 of file stm32h7xx_hal_ltdc.h.

#define IS_LTDC_CFBLL ( __CFBLL__ ) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)

Definition at line 645 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), and HAL_LTDC_SetWindowSize_NoReload().

#define IS_LTDC_CFBLNBR ( __CFBLNBR__ ) ((__CFBLNBR__) <= LTDC_LINE_NUMBER)

Definition at line 646 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), and HAL_LTDC_SetWindowSize_NoReload().

#define IS_LTDC_CFBP ( __CFBP__ ) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER)

Definition at line 644 of file stm32h7xx_hal_ltdc.h.

#define IS_LTDC_DEPOL ( __DEPOL__ ) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH))

Definition at line 616 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_GREENVALUE ( __BGREEN__ ) ((__BGREEN__) <= LTDC_COLOR)

Definition at line 627 of file stm32h7xx_hal_ltdc.h.

#define IS_LTDC_HCONFIGSP ( __HCONFIGSP__ ) ((__HCONFIGSP__) <= LTDC_STOPPOSITION)

Definition at line 641 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), and HAL_LTDC_ConfigLayer_NoReload().

#define IS_LTDC_HCONFIGST ( __HCONFIGST__ ) ((__HCONFIGST__) <= LTDC_STARTPOSITION)

Definition at line 640 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), and HAL_LTDC_ConfigLayer_NoReload().

#define IS_LTDC_HSPOL ( __HSPOL__ ) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH))

Definition at line 614 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_HSYNC ( __HSYNC__ ) ((__HSYNC__) <= LTDC_HORIZONTALSYNC)

Definition at line 618 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_LAYER ( __LAYER__ ) ((__LAYER__) < MAX_LAYER)

Definition at line 613 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigCLUT(), HAL_LTDC_ConfigColorKeying(), HAL_LTDC_ConfigColorKeying_NoReload(), HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_DisableCLUT(), HAL_LTDC_DisableCLUT_NoReload(), HAL_LTDC_DisableColorKeying(), HAL_LTDC_DisableColorKeying_NoReload(), HAL_LTDC_EnableCLUT(), HAL_LTDC_EnableCLUT_NoReload(), HAL_LTDC_EnableColorKeying(), HAL_LTDC_EnableColorKeying_NoReload(), HAL_LTDC_SetAddress(), HAL_LTDC_SetAddress_NoReload(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetAlpha_NoReload(), HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetPixelFormat_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), and HAL_LTDC_SetWindowSize_NoReload().

#define IS_LTDC_LIPOS ( __LIPOS__ ) ((__LIPOS__) <= 0x7FFU)

Definition at line 647 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ProgramLineEvent().

#define IS_LTDC_PCPOL ( __PCPOL__ ) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC))

Definition at line 617 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_PIXEL_FORMAT ( __PIXEL_FORMAT__ )
Value:
(((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888)   || \
                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565)   || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \
                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8)       || \
                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44)     || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))

Definition at line 634 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_SetPixelFormat(), and HAL_LTDC_SetPixelFormat_NoReload().

#define IS_LTDC_REDVALUE ( __BRED__ ) ((__BRED__) <= LTDC_COLOR)

Definition at line 628 of file stm32h7xx_hal_ltdc.h.

#define IS_LTDC_RELOAD ( __RELOADTYPE__ ) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))

Definition at line 648 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Reload().

#define IS_LTDC_TOTALH ( __TOTALH__ ) ((__TOTALH__) <= LTDC_VERTICALSYNC)

Definition at line 625 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_TOTALW ( __TOTALW__ ) ((__TOTALW__) <= LTDC_HORIZONTALSYNC)

Definition at line 624 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_VCONFIGSP ( __VCONFIGSP__ ) ((__VCONFIGSP__) <= LTDC_STOPPOSITION)

Definition at line 643 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), and HAL_LTDC_ConfigLayer_NoReload().

#define IS_LTDC_VCONFIGST ( __VCONFIGST__ ) ((__VCONFIGST__) <= LTDC_STARTPOSITION)

Definition at line 642 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigLayer(), and HAL_LTDC_ConfigLayer_NoReload().

#define IS_LTDC_VSPOL ( __VSPOL__ ) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH))

Definition at line 615 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define IS_LTDC_VSYNC ( __VSYNC__ ) ((__VSYNC__) <= LTDC_VERTICALSYNC)

Definition at line 619 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_Init().

#define LTDC_LAYER | ( | __HANDLE__,
 |  | __LAYER__
 | ) | ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__)))))

Definition at line 612 of file stm32h7xx_hal_ltdc.h.

Referenced by HAL_LTDC_ConfigCLUT(), HAL_LTDC_ConfigColorKeying(), HAL_LTDC_ConfigColorKeying_NoReload(), HAL_LTDC_DisableCLUT(), HAL_LTDC_DisableCLUT_NoReload(), HAL_LTDC_DisableColorKeying(), HAL_LTDC_DisableColorKeying_NoReload(), HAL_LTDC_EnableCLUT(), HAL_LTDC_EnableCLUT_NoReload(), HAL_LTDC_EnableColorKeying(), HAL_LTDC_EnableColorKeying_NoReload(), HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), and LTDC_SetConfig().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LTDC Private Functions

LTDC Private Functions
LTDC
Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
Initialization/de-initialization functions | MDIOS Exported Functions

MDIOS Read/Write functions. More...

Functions

HAL_StatusTypeDef | HAL_MDIOS_WriteReg (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data)
Writes to an MDIOS output register.
HAL_StatusTypeDef | HAL_MDIOS_ReadReg (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData)
Reads an MDIOS input register.
uint32_t | HAL_MDIOS_GetWrittenRegAddress (MDIOS_HandleTypeDef *hmdios)
Gets Written registers by MDIO master.
uint32_t | HAL_MDIOS_GetReadRegAddress (MDIOS_HandleTypeDef *hmdios)
Gets Read registers by MDIO master.
HAL_StatusTypeDef | HAL_MDIOS_ClearWriteRegAddress (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
Clears Write registers flag.
HAL_StatusTypeDef | HAL_MDIOS_ClearReadRegAddress (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
Clears Read register flag.
HAL_StatusTypeDef | HAL_MDIOS_EnableEvents (MDIOS_HandleTypeDef *hmdios)
Enables Events for MDIOS peripheral.
void | HAL_MDIOS_IRQHandler (MDIOS_HandleTypeDef *hmdios)
This function handles MDIOS interrupt request.
__weak void | HAL_MDIOS_WriteCpltCallback (MDIOS_HandleTypeDef *hmdios)
Write Complete Callback.
__weak void | HAL_MDIOS_ReadCpltCallback (MDIOS_HandleTypeDef *hmdios)
Read Complete Callback.
__weak void | HAL_MDIOS_ErrorCallback (MDIOS_HandleTypeDef *hmdios)
Error Callback.
__weak void | HAL_MDIOS_WakeUpCallback (MDIOS_HandleTypeDef *hmdios)
MDIOS WAKEUP interrupt callback.

Detailed Description

MDIOS Read/Write functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the MDIOS
    read and write operations.

    (#) APIs that allow to the MDIOS to read/write from/to the
        values of one of the DINn/DOUTn registers:
        (+) Read the value of a DINn register: HAL_MDIOS_ReadReg()
        (+) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()

    (#) APIs that provide if there are some Slave registres have been
        read or written by the Master:
        (+) DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()
        (+) DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()

    (#) APIs that Clear the read/write flags:
        (+) Clear read registers flags: HAL_MDIOS_ClearReadRegAddress()
        (+) Clear write registers flags: HAL_MDIOS_ClearWriteRegAddress()

    (#) A set of Callbacks are provided:
        (+) HAL_MDIOS_WriteCpltCallback()
        (+) HAL_MDIOS_ReadCpltCallback()
        (+) HAL_MDIOS_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress | ( | MDIOS_HandleTypeDef * | hmdios,
 |  | uint32_t | RegNum
 | ) |  |

Clears Read register flag.

Parameters:
hmdios,: mdios handle
RegNum,: registers addresses to be cleared
Return values:
HAL status

Definition at line 409 of file stm32h7xx_hal_mdios.c.

References assert_param, MDIOS_HandleTypeDef::Instance, and IS_MDIOS_REGISTER.

Referenced by HAL_MDIOS_IRQHandler().

HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress | ( | MDIOS_HandleTypeDef * | hmdios,
 |  | uint32_t | RegNum
 | ) |  |

Clears Write registers flag.

Parameters:
hmdios,: mdios handle
RegNum,: registers addresses to be cleared
Return values:
HAL status

Definition at line 386 of file stm32h7xx_hal_mdios.c.

References assert_param, MDIOS_HandleTypeDef::Instance, and IS_MDIOS_REGISTER.

Referenced by HAL_MDIOS_IRQHandler().

HAL_StatusTypeDef HAL_MDIOS_EnableEvents ( MDIOS_HandleTypeDef * hmdios )

Enables Events for MDIOS peripheral.

Parameters:
hmdios,: mdios handle
Return values:
HAL status

Definition at line 431 of file stm32h7xx_hal_mdios.c.

References __HAL_MDIOS_ENABLE_IT, MDIOS_IT_ERROR, MDIOS_IT_READ, and MDIOS_IT_WRITE.

void HAL_MDIOS_ErrorCallback ( MDIOS_HandleTypeDef * hmdios )

Error Callback.

Parameters:
hmdios,: mdios handle
Return values:
None

Definition at line 538 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_IRQHandler().

uint32_t HAL_MDIOS_GetReadRegAddress ( MDIOS_HandleTypeDef * hmdios )

Gets Read registers by MDIO master.

Parameters:
hmdios,: mdios handle
Return values:
bit map of read registers addresses

Definition at line 375 of file stm32h7xx_hal_mdios.c.

References MDIOS_HandleTypeDef::Instance.

Referenced by HAL_MDIOS_IRQHandler().

uint32_t HAL_MDIOS_GetWrittenRegAddress ( MDIOS_HandleTypeDef * hmdios )

Gets Written registers by MDIO master.

Parameters:
hmdios,: mdios handle
Return values:
bit map of written registers addresses

Definition at line 365 of file stm32h7xx_hal_mdios.c.

References MDIOS_HandleTypeDef::Instance.

Referenced by HAL_MDIOS_IRQHandler().

void HAL_MDIOS_IRQHandler ( MDIOS_HandleTypeDef * hmdios )

This function handles MDIOS interrupt request.

Parameters:
hmdios,: MDIOS handle
Return values:
None

Definition at line 450 of file stm32h7xx_hal_mdios.c.

References __HAL_MDIOS_CLEAR_ERROR_FLAG, __HAL_MDIOS_GET_ERROR_FLAG, __HAL_MDIOS_GET_IT_SOURCE, __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG, __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG, HAL_MDIOS_ClearReadRegAddress(), HAL_MDIOS_ClearWriteRegAddress(), HAL_MDIOS_ErrorCallback(), HAL_MDIOS_GetReadRegAddress(), HAL_MDIOS_GetWrittenRegAddress(), HAL_MDIOS_ReadCpltCallback(), HAL_MDIOS_WakeUpCallback(), HAL_MDIOS_WriteCpltCallback(), MDIOS_ALL_ERRORS_FLAG, MDIOS_ALL_REG_FLAG, MDIOS_IT_ERROR, MDIOS_IT_READ, MDIOS_IT_WRITE, and MDIOS_WAKEUP_EXTI_LINE.

void HAL_MDIOS_ReadCpltCallback ( MDIOS_HandleTypeDef * hmdios )

Read Complete Callback.

Parameters:
hmdios,: mdios handle
Return values:
None

Definition at line 523 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_IRQHandler().

HAL_StatusTypeDef HAL_MDIOS_ReadReg | ( | MDIOS_HandleTypeDef * | hmdios,
 |  | uint32_t | RegNum,
 |  | uint16_t * | pData
 | ) |  |

Reads an MDIOS input register.

Parameters:
hmdios,: mdios handle
RegNum,: MDIOS input register address
pData,: pointer to Data
Return values:
HAL status

Definition at line 338 of file stm32h7xx_hal_mdios.c.

References assert_param, IS_MDIOS_REGISTER, and MDIOS_DIN_BASE_ADDR.

void HAL_MDIOS_WakeUpCallback ( MDIOS_HandleTypeDef * hmdios )

MDIOS WAKEUP interrupt callback.

Parameters:
hmdios,: mdios handle
Return values:
None

Definition at line 553 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_IRQHandler().

void HAL_MDIOS_WriteCpltCallback ( MDIOS_HandleTypeDef * hmdios )

Write Complete Callback.

Parameters:
hmdios,: mdios handle
Return values:
None

Definition at line 508 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_IRQHandler().

HAL_StatusTypeDef HAL_MDIOS_WriteReg | ( | MDIOS_HandleTypeDef * | hmdios,
 |  | uint32_t | RegNum,
 |  | uint16_t | Data
 | ) |  |

Writes to an MDIOS output register.

Parameters:
hmdios,: mdios handle
RegNum,: MDIOS output register address
Data,: Data to write
Return values:
HAL status

Definition at line 309 of file stm32h7xx_hal_mdios.c.

References assert_param, IS_MDIOS_REGISTER, and MDIOS_DOUT_BASE_ADDR.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
Initialization/de-initialization functions | MDIOS Exported Functions

MDIOS control functions. More...

Functions

uint32_t | HAL_MDIOS_GetError (MDIOS_HandleTypeDef *hmdios)
Gets MDIOS error flags.
HAL_MDIOS_StateTypeDef | HAL_MDIOS_GetState (MDIOS_HandleTypeDef *hmdios)
Return the MDIOS HAL state.

Detailed Description

MDIOS control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the MDIOS.
     (+) HAL_MDIOS_GetState() API, helpful to check in run-time the state.
     (+) HAL_MDIOS_GetError() API, returns the errors occured during data transfer.

Function Documentation

uint32_t HAL_MDIOS_GetError ( MDIOS_HandleTypeDef * hmdios )

Gets MDIOS error flags.

Parameters:
hmdios,: mdios handle
Return values:
bit map of occured errors

Definition at line 588 of file stm32h7xx_hal_mdios.c.

References MDIOS_HandleTypeDef::Instance.

HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState ( MDIOS_HandleTypeDef * hmdios )

Return the MDIOS HAL state.

Parameters:
hmdios,: mdios handle
Return values:
HAL state

Definition at line 599 of file stm32h7xx_hal_mdios.c.

References MDIOS_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization/de-initialization functions

Modules | Functions
Initialization/de-initialization functions
MDIOS Exported Functions

Initialization and Configuration functions. More...

Modules

IO operation functions

MDIOS Read/Write functions.

Peripheral Control functions

MDIOS control functions.

Functions

HAL_StatusTypeDef | HAL_MDIOS_Init (MDIOS_HandleTypeDef *hmdios)
Initializes the MDIOS according to the specified parameters in the MDIOS_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_MDIOS_DeInit (MDIOS_HandleTypeDef *hmdios)
DeInitializes the MDIOS peripheral.
__weak void | HAL_MDIOS_MspInit (MDIOS_HandleTypeDef *hmdios)
MDIOS MSP Init.
__weak void | HAL_MDIOS_MspDeInit (MDIOS_HandleTypeDef *hmdios)
MDIOS MSP DeInit.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the MDIOS
      (+) The following parameters can be configured:
        (++) Port Address
        (++) Preamble Check

Function Documentation

HAL_StatusTypeDef HAL_MDIOS_DeInit ( MDIOS_HandleTypeDef * hmdios )

DeInitializes the MDIOS peripheral.

Parameters:
hmdios,: MDIOS handle
Return values:
HAL status

Definition at line 209 of file stm32h7xx_hal_mdios.c.

References __HAL_MDIOS_DISABLE, assert_param, HAL_MDIOS_MspDeInit(), HAL_MDIOS_STATE_BUSY, HAL_MDIOS_STATE_RESET, MDIOS_HandleTypeDef::Instance, and MDIOS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MDIOS_Init ( MDIOS_HandleTypeDef * hmdios )

Initializes the MDIOS according to the specified parameters in the MDIOS_InitTypeDef and creates the associated handle .

Parameters:
hmdios,: pointer to a MDIOS_HandleTypeDef structure that contains the configuration information for MDIOS module
Return values:
HAL status

Definition at line 152 of file stm32h7xx_hal_mdios.c.

References assert_param, HAL_MDIOS_MspInit(), HAL_MDIOS_STATE_BUSY, HAL_MDIOS_STATE_READY, HAL_MDIOS_STATE_RESET, MDIOS_HandleTypeDef::Init, MDIOS_HandleTypeDef::Instance, IS_MDIOS_PORTADDRESS, IS_MDIOS_PREAMBLECHECK, MDIOS_PORT_ADDRESS_SHIFT, MDIOS_InitTypeDef::PortAddress, MDIOS_InitTypeDef::PreambleCheck, and MDIOS_HandleTypeDef::State.

void HAL_MDIOS_MspDeInit ( MDIOS_HandleTypeDef * hmdios )

MDIOS MSP DeInit.

Parameters:
hmdios,: mdios handle
Return values:
None

Definition at line 259 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_DeInit().

void HAL_MDIOS_MspInit ( MDIOS_HandleTypeDef * hmdios )

MDIOS MSP Init.

Parameters:
hmdios,: mdios handle
Return values:
None

Definition at line 244 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_Init().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDIOS State structures definition

Enumerations
MDIOS State structures definition
MDIOS Exported Types

Enumerations

enum HAL_MDIOS_StateTypeDef { HAL_MDIOS_STATE_RESET = 0x00U, HAL_MDIOS_STATE_READY = 0x01U, HAL_MDIOS_STATE_BUSY = 0x02U, HAL_MDIOS_STATE_ERROR = 0x04U }

Enumeration Type Documentation

enum HAL_MDIOS_StateTypeDef
Enumerator:
HAL_MDIOS_STATE_RESET

Peripheral not yet Initialized or disabled

HAL_MDIOS_STATE_READY

Peripheral Initialized and ready for use

HAL_MDIOS_STATE_BUSY

an internal process is ongoing

HAL_MDIOS_STATE_ERROR

Reception process is ongoing

Definition at line 67 of file stm32h7xx_hal_mdios.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDIOS_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
MDIOS_InitTypeDef Struct Reference
MDIOS Init Structure definition

#include <stm32h7xx_hal_mdios.h>

Data Fields

uint32_t | PortAddress
uint32_t | PreambleCheck

Detailed Description

Definition at line 83 of file stm32h7xx_hal_mdios.h.

Field Documentation

uint32_t MDIOS_InitTypeDef::PortAddress

Specifies the MDIOS port address. This parameter can be a value from 0 to 31

Definition at line 85 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_Init().

uint32_t MDIOS_InitTypeDef::PreambleCheck

Specifies whether the preamble check is enabled or disabled. This parameter can be a value of MDIOS Preamble Check

Definition at line 87 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_mdios.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDIOS_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
MDIOS_HandleTypeDef Struct Reference
MDIOS handle Structure definition

#include <stm32h7xx_hal_mdios.h>

Data Fields

MDIOS_TypeDef * | Instance
MDIOS_InitTypeDef Init
__IO HAL_MDIOS_StateTypeDef | State
HAL_LockTypeDef | Lock

Detailed Description

Definition at line 99 of file stm32h7xx_hal_mdios.h.

Field Documentation

MDIOS_InitTypeDef MDIOS_HandleTypeDef::Init

MDIOS Init Structure

Definition at line 103 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_Init().

MDIOS_TypeDef* MDIOS_HandleTypeDef::Instance

Register base address

Definition at line 101 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_ClearReadRegAddress(), HAL_MDIOS_ClearWriteRegAddress(), HAL_MDIOS_DeInit(), HAL_MDIOS_GetError(), HAL_MDIOS_GetReadRegAddress(), HAL_MDIOS_GetWrittenRegAddress(), and HAL_MDIOS_Init().

HAL_LockTypeDef MDIOS_HandleTypeDef::Lock

MDIOS Lock

Definition at line 107 of file stm32h7xx_hal_mdios.h.

__IO HAL_MDIOS_StateTypeDef MDIOS_HandleTypeDef::State

MDIOS communication state

Definition at line 105 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_DeInit(), HAL_MDIOS_GetState(), and HAL_MDIOS_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_mdios.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDIOS Preamble Check

Defines
MDIOS Preamble Check
MDIOS Exported Constants

Defines

#define | MDIOS_PREAMBLE_CHECK_ENABLE ((uint32_t)0x00000000U)
#define | MDIOS_PREAMBLE_CHECK_DISABLE MDIOS_CR_DPC

Define Documentation

#define MDIOS_PREAMBLE_CHECK_DISABLE MDIOS_CR_DPC

Definition at line 127 of file stm32h7xx_hal_mdios.h.

#define MDIOS_PREAMBLE_CHECK_ENABLE ((uint32_t)0x00000000U)

Definition at line 126 of file stm32h7xx_hal_mdios.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDIOS Input Output Registers Definitions

Defines
MDIOS Input Output Registers Definitions
MDIOS Exported Constants

Defines

#define | MDIOS_REG0 ((uint32_t)0x00000000U)
#define | MDIOS_REG1 ((uint32_t)0x00000001U)
#define | MDIOS_REG2 ((uint32_t)0x00000002U)
#define | MDIOS_REG3 ((uint32_t)0x00000003U)
#define | MDIOS_REG4 ((uint32_t)0x00000004U)
#define | MDIOS_REG5 ((uint32_t)0x00000005U)
#define | MDIOS_REG6 ((uint32_t)0x00000006U)
#define | MDIOS_REG7 ((uint32_t)0x00000007U)
#define | MDIOS_REG8 ((uint32_t)0x00000008U)
#define | MDIOS_REG9 ((uint32_t)0x00000009U)
#define | MDIOS_REG10 ((uint32_t)0x0000000AU)
#define | MDIOS_REG11 ((uint32_t)0x0000000BU)
#define | MDIOS_REG12 ((uint32_t)0x0000000CU)
#define | MDIOS_REG13 ((uint32_t)0x0000000DU)
#define | MDIOS_REG14 ((uint32_t)0x0000000EU)
#define | MDIOS_REG15 ((uint32_t)0x0000000FU)
#define | MDIOS_REG16 ((uint32_t)0x00000010U)
#define | MDIOS_REG17 ((uint32_t)0x00000011U)
#define | MDIOS_REG18 ((uint32_t)0x00000012U)
#define | MDIOS_REG19 ((uint32_t)0x00000013U)
#define | MDIOS_REG20 ((uint32_t)0x00000014U)
#define | MDIOS_REG21 ((uint32_t)0x00000015U)
#define | MDIOS_REG22 ((uint32_t)0x00000016U)
#define | MDIOS_REG23 ((uint32_t)0x00000017U)
#define | MDIOS_REG24 ((uint32_t)0x00000018U)
#define | MDIOS_REG25 ((uint32_t)0x00000019U)
#define | MDIOS_REG26 ((uint32_t)0x0000001AU)
#define | MDIOS_REG27 ((uint32_t)0x0000001BU)
#define | MDIOS_REG28 ((uint32_t)0x0000001CU)
#define | MDIOS_REG29 ((uint32_t)0x0000001DU)
#define | MDIOS_REG30 ((uint32_t)0x0000001EU)
#define | MDIOS_REG31 ((uint32_t)0x0000001FU)

Define Documentation

#define MDIOS_REG0 ((uint32_t)0x00000000U)

Definition at line 135 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG1 ((uint32_t)0x00000001U)

Definition at line 136 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG10 ((uint32_t)0x0000000AU)

Definition at line 145 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG11 ((uint32_t)0x0000000BU)

Definition at line 146 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG12 ((uint32_t)0x0000000CU)

Definition at line 147 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG13 ((uint32_t)0x0000000DU)

Definition at line 148 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG14 ((uint32_t)0x0000000EU)

Definition at line 149 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG15 ((uint32_t)0x0000000FU)

Definition at line 150 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG16 ((uint32_t)0x00000010U)

Definition at line 151 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG17 ((uint32_t)0x00000011U)

Definition at line 152 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG18 ((uint32_t)0x00000012U)

Definition at line 153 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG19 ((uint32_t)0x00000013U)

Definition at line 154 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG2 ((uint32_t)0x00000002U)

Definition at line 137 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG20 ((uint32_t)0x00000014U)

Definition at line 155 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG21 ((uint32_t)0x00000015U)

Definition at line 156 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG22 ((uint32_t)0x00000016U)

Definition at line 157 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG23 ((uint32_t)0x00000017U)

Definition at line 158 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG24 ((uint32_t)0x00000018U)

Definition at line 159 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG25 ((uint32_t)0x00000019U)

Definition at line 160 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG26 ((uint32_t)0x0000001AU)

Definition at line 161 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG27 ((uint32_t)0x0000001BU)

Definition at line 162 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG28 ((uint32_t)0x0000001CU)

Definition at line 163 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG29 ((uint32_t)0x0000001DU)

Definition at line 164 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG3 ((uint32_t)0x00000003U)

Definition at line 138 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG30 ((uint32_t)0x0000001EU)

Definition at line 165 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG31 ((uint32_t)0x0000001FU)

Definition at line 166 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG4 ((uint32_t)0x00000004U)

Definition at line 139 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG5 ((uint32_t)0x00000005U)

Definition at line 140 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG6 ((uint32_t)0x00000006U)

Definition at line 141 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG7 ((uint32_t)0x00000007U)

Definition at line 142 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG8 ((uint32_t)0x00000008U)

Definition at line 143 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG9 ((uint32_t)0x00000009U)

Definition at line 144 of file stm32h7xx_hal_mdios.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDIOS Registers Flags

Defines
MDIOS Registers Flags
MDIOS Exported Constants

Defines

#define | MDIOS_REG0_FLAG ((uint32_t)0x00000001U)
#define | MDIOS_REG1_FLAG ((uint32_t)0x00000002U)
#define | MDIOS_REG2_FLAG ((uint32_t)0x00000004U)
#define | MDIOS_REG3_FLAG ((uint32_t)0x00000008U)
#define | MDIOS_REG4_FLAG ((uint32_t)0x00000010U)
#define | MDIOS_REG5_FLAG ((uint32_t)0x00000020U)
#define | MDIOS_REG6_FLAG ((uint32_t)0x00000040U)
#define | MDIOS_REG7_FLAG ((uint32_t)0x00000080U)
#define | MDIOS_REG8_FLAG ((uint32_t)0x00000100U)
#define | MDIOS_REG9_FLAG ((uint32_t)0x00000200U)
#define | MDIOS_REG10_FLAG ((uint32_t)0x00000400U)
#define | MDIOS_REG11_FLAG ((uint32_t)0x00000800U)
#define | MDIOS_REG12_FLAG ((uint32_t)0x00001000U)
#define | MDIOS_REG13_FLAG ((uint32_t)0x00002000U)
#define | MDIOS_REG14_FLAG ((uint32_t)0x00004000U)
#define | MDIOS_REG15_FLAG ((uint32_t)0x00008000U)
#define | MDIOS_REG16_FLAG ((uint32_t)0x00010000U)
#define | MDIOS_REG17_FLAG ((uint32_t)0x00020000U)
#define | MDIOS_REG18_FLAG ((uint32_t)0x00040000U)
#define | MDIOS_REG19_FLAG ((uint32_t)0x00080000U)
#define | MDIOS_REG20_FLAG ((uint32_t)0x00100000U)
#define | MDIOS_REG21_FLAG ((uint32_t)0x00200000U)
#define | MDIOS_REG22_FLAG ((uint32_t)0x00400000U)
#define | MDIOS_REG23_FLAG ((uint32_t)0x00800000U)
#define | MDIOS_REG24_FLAG ((uint32_t)0x01000000U)
#define | MDIOS_REG25_FLAG ((uint32_t)0x02000000U)
#define | MDIOS_REG26_FLAG ((uint32_t)0x04000000U)
#define | MDIOS_REG27_FLAG ((uint32_t)0x08000000U)
#define | MDIOS_REG28_FLAG ((uint32_t)0x10000000U)
#define | MDIOS_REG29_FLAG ((uint32_t)0x20000000U)
#define | MDIOS_REG30_FLAG ((uint32_t)0x40000000U)
#define | MDIOS_REG31_FLAG ((uint32_t)0x80000000U)
#define | MDIOS_ALLREG_FLAG ((uint32_t)0xFFFFFFFFU)

Define Documentation

#define MDIOS_ALLREG_FLAG ((uint32_t)0xFFFFFFFFU)

Definition at line 206 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG0_FLAG ((uint32_t)0x00000001U)

Definition at line 174 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG10_FLAG ((uint32_t)0x00000400U)

Definition at line 184 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG11_FLAG ((uint32_t)0x00000800U)

Definition at line 185 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG12_FLAG ((uint32_t)0x00001000U)

Definition at line 186 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG13_FLAG ((uint32_t)0x00002000U)

Definition at line 187 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG14_FLAG ((uint32_t)0x00004000U)

Definition at line 188 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG15_FLAG ((uint32_t)0x00008000U)

Definition at line 189 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG16_FLAG ((uint32_t)0x00010000U)

Definition at line 190 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG17_FLAG ((uint32_t)0x00020000U)

Definition at line 191 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG18_FLAG ((uint32_t)0x00040000U)

Definition at line 192 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG19_FLAG ((uint32_t)0x00080000U)

Definition at line 193 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG1_FLAG ((uint32_t)0x00000002U)

Definition at line 175 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG20_FLAG ((uint32_t)0x00100000U)

Definition at line 194 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG21_FLAG ((uint32_t)0x00200000U)

Definition at line 195 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG22_FLAG ((uint32_t)0x00400000U)

Definition at line 196 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG23_FLAG ((uint32_t)0x00800000U)

Definition at line 197 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG24_FLAG ((uint32_t)0x01000000U)

Definition at line 198 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG25_FLAG ((uint32_t)0x02000000U)

Definition at line 199 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG26_FLAG ((uint32_t)0x04000000U)

Definition at line 200 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG27_FLAG ((uint32_t)0x08000000U)

Definition at line 201 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG28_FLAG ((uint32_t)0x10000000U)

Definition at line 202 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG29_FLAG ((uint32_t)0x20000000U)

Definition at line 203 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG2_FLAG ((uint32_t)0x00000004U)

Definition at line 176 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG30_FLAG ((uint32_t)0x40000000U)

Definition at line 204 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG31_FLAG ((uint32_t)0x80000000U)

Definition at line 205 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG3_FLAG ((uint32_t)0x00000008U)

Definition at line 177 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG4_FLAG ((uint32_t)0x00000010U)

Definition at line 178 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG5_FLAG ((uint32_t)0x00000020U)

Definition at line 179 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG6_FLAG ((uint32_t)0x00000040U)

Definition at line 180 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG7_FLAG ((uint32_t)0x00000080U)

Definition at line 181 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG8_FLAG ((uint32_t)0x00000100U)

Definition at line 182 of file stm32h7xx_hal_mdios.h.

#define MDIOS_REG9_FLAG ((uint32_t)0x00000200U)

Definition at line 183 of file stm32h7xx_hal_mdios.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Interrupt Sources

Defines
Interrupt Sources
MDIOS Exported Constants

Defines

#define | MDIOS_IT_WRITE MDIOS_CR_WRIE
#define | MDIOS_IT_READ MDIOS_CR_RDIE
#define | MDIOS_IT_ERROR MDIOS_CR_EIE

Define Documentation

#define MDIOS_IT_ERROR MDIOS_CR_EIE

Definition at line 216 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_EnableEvents(), and HAL_MDIOS_IRQHandler().

#define MDIOS_IT_READ MDIOS_CR_RDIE

Definition at line 215 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_EnableEvents(), and HAL_MDIOS_IRQHandler().

#define MDIOS_IT_WRITE MDIOS_CR_WRIE

Definition at line 214 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_EnableEvents(), and HAL_MDIOS_IRQHandler().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDIOS Interrupt Flags

Defines
MDIOS Interrupt Flags
MDIOS Exported Constants

Defines

#define | MDIOS_TURNAROUND_ERROR_FLAG MDIOS_SR_TERF
#define | MDIOS_START_ERROR_FLAG MDIOS_SR_SERF
#define | MDIOS_PREAMBLE_ERROR_FLAG MDIOS_SR_PERF

Define Documentation

#define MDIOS_PREAMBLE_ERROR_FLAG MDIOS_SR_PERF

Definition at line 226 of file stm32h7xx_hal_mdios.h.

#define MDIOS_START_ERROR_FLAG MDIOS_SR_SERF

Definition at line 225 of file stm32h7xx_hal_mdios.h.

#define MDIOS_TURNAROUND_ERROR_FLAG MDIOS_SR_TERF

Definition at line 224 of file stm32h7xx_hal_mdios.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDIOS Wakeup Line

Defines
MDIOS Wakeup Line
MDIOS Exported Constants

Defines

#define MDIOS_WAKEUP_EXTI_LINE ((uint32_t)0x00000400) /* !< 42 - 32 = 10 */

Define Documentation

#define MDIOS_WAKEUP_EXTI_LINE ((uint32_t)0x00000400) /* !< 42 - 32 = 10 */

Definition at line 234 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_IRQHandler().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDIOS Exported Macros

Defines
MDIOS Exported Macros
MDIOS

Defines

#define | __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDIOS_STATE_RESET)
Reset MDIOS handle state.
#define | __HAL_MDIOS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN)
Enable/Disable the MDIOS peripheral.
#define | __HAL_MDIOS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~MDIOS_CR_EN)
#define | __HAL_MDIOS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the MDIOS device interrupt.
#define | __HAL_MDIOS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the MDIOS device interrupt.
#define | __HAL_MDIOS_GET_WRITE_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WRFR & (__FLAG__))
Set MDIOS slave get write register flag.
#define | __HAL_MDIOS_GET_READ_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RDFR & (__FLAG__))
MDIOS slave get read register flag.
#define | __HAL_MDIOS_GET_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__))
MDIOS slave get interrupt.
#define | __HAL_MDIOS_CLEAR_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR) |= (__FLAG__)
MDIOS slave clear interrupt.
#define | __HAL_MDIOS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
Checks whether the specified MDIOS interrupt is set or not.
#define | __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI_D1->IMR2 |= (__EXTI_LINE__))
Enable the MDIOS WAKEUP Exti Line.
#define | __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR2 & (__EXTI_LINE__))
checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not.
#define | __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR2 = (__EXTI_LINE__))
Clear the MDIOS WAKEUP Exti flag.
#define | __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__)
enable rising edge interrupt on selected EXTI line.
#define | __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__)
enable falling edge interrupt on selected EXTI line.
#define | __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__)
enable falling edge interrupt on selected EXTI line.
#define | __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER2 |= (__EXTI_LINE__))
Generates a Software interrupt on selected EXTI line.

Define Documentation

#define __HAL_MDIOS_CLEAR_ERROR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->CLRFR) |= (__FLAG__)

MDIOS slave clear interrupt.

Parameters:
__HANDLE__,: specifies the MDIOS handle.
__FLAG__ : specifies the Error flag. This parameter can be one or a combination of the following values:
  • MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
  • MDIOS_START_ERROR_FLAG: Register read interrupt
  • MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
Return values:
none

Definition at line 320 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_IRQHandler().

#define __HAL_MDIOS_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~MDIOS_CR_EN)

Definition at line 259 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_DeInit().

#define __HAL_MDIOS_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the MDIOS device interrupt.

Parameters:
__HANDLE__,: specifies the MDIOS handle.
__INTERRUPT__ : specifies the MDIOS interrupt sources to be disabled. This parameter can be one or a combination of the following values:
  • MDIOS_IT_WRITE: Register write interrupt
  • MDIOS_IT_READ: Register read interrupt
  • MDIOS_IT_ERROR: Error interrupt
Return values:
None

Definition at line 284 of file stm32h7xx_hal_mdios.h.

#define __HAL_MDIOS_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN)

Enable/Disable the MDIOS peripheral.

Parameters:
__HANDLE__,: specifies the MDIOS handle.
Return values:
None

Definition at line 258 of file stm32h7xx_hal_mdios.h.

#define __HAL_MDIOS_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the MDIOS device interrupt.

Parameters:
__HANDLE__,: specifies the MDIOS handle.
__INTERRUPT__ : specifies the MDIOS interrupt sources to be enabled. This parameter can be one or a combination of the following values:
  • MDIOS_IT_WRITE: Register write interrupt
  • MDIOS_IT_READ: Register read interrupt
  • MDIOS_IT_ERROR: Error interrupt
Return values:
None

Definition at line 272 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_EnableEvents().

#define __HAL_MDIOS_GET_ERROR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR & (__FLAG__))

MDIOS slave get interrupt.

Parameters:
__HANDLE__,: specifies the MDIOS handle.
__FLAG__ : specifies the Error flag. This parameter can be one or a combination of the following values:
  • MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
  • MDIOS_START_ERROR_FLAG: Register read interrupt
  • MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
Return values:
The state of the error flag

Definition at line 309 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_IRQHandler().

#define __HAL_MDIOS_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR & (__INTERRUPT__))

Checks whether the specified MDIOS interrupt is set or not.

Parameters:
__HANDLE__,: specifies the MDIOS handle.
__INTERRUPT__ : specifies the MDIOS interrupt sources This parameter can be one or a combination of the following values:
  • MDIOS_IT_WRITE: Register write interrupt
  • MDIOS_IT_READ: Register read interrupt
  • MDIOS_IT_ERROR: Error interrupt
Return values:
The state of the interrupt source

Definition at line 332 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_IRQHandler().

#define __HAL_MDIOS_GET_READ_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->RDFR & (__FLAG__))

MDIOS slave get read register flag.

Parameters:
__HANDLE__,: specifies the MDIOS handle.
__FLAG__,: specifies the read register flag
Return values:
The state of read flag

Definition at line 298 of file stm32h7xx_hal_mdios.h.

#define __HAL_MDIOS_GET_WRITE_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->WRFR & (__FLAG__))

Set MDIOS slave get write register flag.

Parameters:
__HANDLE__,: specifies the MDIOS handle.
__FLAG__,: specifies the write register flag
Return values:
The state of write flag

Definition at line 291 of file stm32h7xx_hal_mdios.h.

#define __HAL_MDIOS_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_MDIOS_STATE_RESET)

Reset MDIOS handle state.

Parameters:
__HANDLE__,: MDIOS handle.
Return values:
None

Definition at line 251 of file stm32h7xx_hal_mdios.h.

#define __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG ( __EXTI_LINE__ ) (EXTI_D1->PR2 = (__EXTI_LINE__))

Clear the MDIOS WAKEUP Exti flag.

Parameters:
__EXTI_LINE__,: specifies the MDIOS WAKEUP Exti sources to be cleared. This parameter can be:
  • MDIOS_WAKEUP_EXTI_LINE
Return values:
None.

Definition at line 359 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_IRQHandler().

#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE ( __EXTI_LINE__ )
Value:
(EXTI->RTSR2 &= ~(__EXTI_LINE__));\
                                                                 (EXTI->FTSR2 |= (__EXTI_LINE__))

enable falling edge interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__,: specifies the ETH WAKEUP EXTI sources to be disabled. This parameter can be:
  • ETH_WAKEUP_EXTI_LINE
Return values:
None

Definition at line 378 of file stm32h7xx_hal_mdios.h.

#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT ( __EXTI_LINE__ ) (EXTI_D1->IMR2 |= (__EXTI_LINE__))

Enable the MDIOS WAKEUP Exti Line.

Parameters:
__EXTI_LINE__,: specifies the MDIOS WAKEUP Exti sources to be enabled. This parameter can be:
  • MDIOS_WAKEUP_EXTI_LINE
Return values:
None.

Definition at line 341 of file stm32h7xx_hal_mdios.h.

#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE ( __EXTI_LINE__ )
Value:
(EXTI->FTSR2 &= ~(__EXTI_LINE__)); \
                                                                   (EXTI->RTSR2 |= (__EXTI_LINE__))

enable rising edge interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__,: specifies the ETH WAKEUP EXTI sources to be disabled. This parameter can be:
  • ETH_WAKEUP_EXTI_LINE
Return values:
None

Definition at line 368 of file stm32h7xx_hal_mdios.h.

#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE ( __EXTI_LINE__ )
Value:
(EXTI->RTSR2 |= (__EXTI_LINE__));\
                                                                          (EXTI->FTSR2 |= (__EXTI_LINE__))

enable falling edge interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__,: specifies the ETH WAKEUP EXTI sources to be disabled. This parameter can be:
  • ETH_WAKEUP_EXTI_LINE
Return values:
None

Definition at line 388 of file stm32h7xx_hal_mdios.h.

#define __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT ( __EXTI_LINE__ ) (EXTI->SWIER2 |= (__EXTI_LINE__))

Generates a Software interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__,: specifies the MDIOS WAKEUP EXTI sources to be disabled. This parameter can be:
  • MDIOS_WAKEUP_EXTI_LINE
Return values:
None

Definition at line 398 of file stm32h7xx_hal_mdios.h.

#define __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG ( __EXTI_LINE__ ) (EXTI_D1->PR2 & (__EXTI_LINE__))

checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not.

Parameters:
__EXTI_LINE__,: specifies the MDIOS WAKEUP Exti sources to be cleared. This parameter can be:
  • MDIOS_WAKEUP_EXTI_LINE
Return values:
EXTI MDIOS WAKEUP Line Status.

Definition at line 350 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_IRQHandler().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDIOS Private Types

MDIOS Private Types
MDIOS
Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDIOS Private Variables

MDIOS Private Variables
MDIOS
Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDIOS Private Constants

MDIOS Private Constants
MDIOS
Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDIOS Private Macros

Defines
MDIOS Private Macros
MDIOS

Defines

#define | IS_MDIOS_PORTADDRESS(__ADDR__) ((__ADDR__) < 32)
#define | IS_MDIOS_REGISTER(__REGISTER__) ((__REGISTER__) < 32)
#define | IS_MDIOS_PREAMBLECHECK(__PREAMBLECHECK__)

Define Documentation

#define IS_MDIOS_PORTADDRESS ( __ADDR__ ) ((__ADDR__) < 32)

Definition at line 486 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_Init().

#define IS_MDIOS_PREAMBLECHECK ( __PREAMBLECHECK__ )
Value:
(((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_ENABLE) || \
                                                   ((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_DISABLE))

Definition at line 490 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_Init().

#define IS_MDIOS_REGISTER ( __REGISTER__ ) ((__REGISTER__) < 32)

Definition at line 488 of file stm32h7xx_hal_mdios.h.

Referenced by HAL_MDIOS_ClearReadRegAddress(), HAL_MDIOS_ClearWriteRegAddress(), HAL_MDIOS_ReadReg(), and HAL_MDIOS_WriteReg().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDIOS Private Functions

MDIOS Private Functions
MDIOS
Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDIOS

Modules | Defines
MDIOS
STM32H7xx_HAL_Driver

HAL MDIOS module driver. More...

Modules

MDIOS Exported Functions
MDIOS Exported Types
MDIOS Exported Constants
MDIOS Exported Macros
MDIOS Private Types
MDIOS Private Variables
MDIOS Private Constants
MDIOS Private Macros
MDIOS Private Functions

Defines

#define | MDIOS_PORT_ADDRESS_SHIFT ((uint32_t)8)
#define | MDIOS_ALL_REG_FLAG ((uint32_t)0xFFFFFFFFU)
#define | MDIOS_ALL_ERRORS_FLAG ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF))
#define | MDIOS_DIN_BASE_ADDR (MDIOS_BASE + 0x100)
#define | MDIOS_DOUT_BASE_ADDR (MDIOS_BASE + 0x180)

Detailed Description

HAL MDIOS module driver.

Define Documentation

#define MDIOS_ALL_ERRORS_FLAG ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF))

Definition at line 114 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_IRQHandler().

#define MDIOS_ALL_REG_FLAG ((uint32_t)0xFFFFFFFFU)

Definition at line 113 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_IRQHandler().

#define MDIOS_DIN_BASE_ADDR (MDIOS_BASE + 0x100)

Definition at line 116 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_ReadReg().

#define MDIOS_DOUT_BASE_ADDR (MDIOS_BASE + 0x180)

Definition at line 117 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_WriteReg().

#define MDIOS_PORT_ADDRESS_SHIFT ((uint32_t)8)

Definition at line 112 of file stm32h7xx_hal_mdios.c.

Referenced by HAL_MDIOS_Init().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA Exported Types

Data Structures | Typedefs | Enumerations
MDMA Exported Types
MDMA

MDMA Exported Types. More...

Data Structures

struct | MDMA_InitTypeDef
MDMA Configuration Structure definition. More...
struct | MDMA_LinkNodeTypeDef
HAL MDMA linked list node structure definition. More...
struct | MDMA_LinkNodeConfTypeDef
HAL MDMA linked list node configuration structure definition. More...
struct | __MDMA_HandleTypeDef
MDMA handle Structure definition. More...

Typedefs

typedef struct __MDMA_HandleTypeDef | MDMA_HandleTypeDef
MDMA handle Structure definition.

Enumerations

enum HAL_MDMA_StateTypeDef {
HAL_MDMA_STATE_RESET = 0x00U, HAL_MDMA_STATE_READY = 0x01U, HAL_MDMA_STATE_BUSY = 0x02U, HAL_MDMA_STATE_ERROR = 0x03U,
HAL_MDMA_STATE_ABORT = 0x04U
}
HAL MDMA State structure definition. More...
enum | HAL_MDMA_LevelCompleteTypeDef { HAL_MDMA_FULL_TRANSFER = 0x00U, HAL_MDMA_BUFFER_TRANSFER = 0x01U, HAL_MDMA_BLOCK_TRANSFER = 0x02U, HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U }
HAL MDMA Level Complete structure definition. More...
enum HAL_MDMA_CallbackIDTypeDef {
HAL_MDMA_XFER_CPLT_CB_ID = 0x00U, HAL_MDMA_XFER_BUFFERCPLT_CB_ID = 0x01U, HAL_MDMA_XFER_BLOCKCPLT_CB_ID = 0x02U, HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID = 0x03U,
HAL_MDMA_XFER_ERROR_CB_ID = 0x04U, HAL_MDMA_XFER_ABORT_CB_ID = 0x05U, HAL_MDMA_XFER_ALL_CB_ID = 0x06U
}
HAL MDMA Callbacks IDs structure definition. More...

Detailed Description

MDMA Exported Types.

Typedef Documentation

typedef struct __MDMA_HandleTypeDef MDMA_HandleTypeDef

MDMA handle Structure definition.

Enumeration Type Documentation

enum HAL_MDMA_CallbackIDTypeDef

HAL MDMA Callbacks IDs structure definition.

Enumerator:
HAL_MDMA_XFER_CPLT_CB_ID

Full transfer

HAL_MDMA_XFER_BUFFERCPLT_CB_ID

Buffer Transfer

HAL_MDMA_XFER_BLOCKCPLT_CB_ID

Block Transfer

HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID

Repeated Block Transfer

HAL_MDMA_XFER_ERROR_CB_ID

Error

HAL_MDMA_XFER_ABORT_CB_ID

Abort

HAL_MDMA_XFER_ALL_CB_ID

All

Definition at line 205 of file stm32h7xx_hal_mdma.h.

enum HAL_MDMA_LevelCompleteTypeDef

HAL MDMA Level Complete structure definition.

Enumerator:
HAL_MDMA_FULL_TRANSFER

Full transfer

HAL_MDMA_BUFFER_TRANSFER

Buffer Transfer

HAL_MDMA_BLOCK_TRANSFER

Block Transfer

HAL_MDMA_REPEAT_BLOCK_TRANSFER

repeat block Transfer

Definition at line 193 of file stm32h7xx_hal_mdma.h.

enum HAL_MDMA_StateTypeDef

HAL MDMA State structure definition.

Enumerator:
HAL_MDMA_STATE_RESET

MDMA not yet initialized or disabled

HAL_MDMA_STATE_READY

MDMA initialized and ready for use

HAL_MDMA_STATE_BUSY

MDMA process is ongoing

HAL_MDMA_STATE_ERROR

MDMA error state

HAL_MDMA_STATE_ABORT

DMA Abort state

Definition at line 180 of file stm32h7xx_hal_mdma.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
MDMA_InitTypeDef Struct Reference
MDMA Exported Types

MDMA Configuration Structure definition. More...

#include <stm32h7xx_hal_mdma.h>

Data Fields

uint32_t | Request
uint32_t | TransferTriggerMode
uint32_t | Priority
uint32_t | Endianness
uint32_t | SourceInc
uint32_t | DestinationInc
uint32_t | SourceDataSize
uint32_t | DestDataSize
uint32_t | DataAlignment
uint32_t | BufferTransferLength
uint32_t | SourceBurst
uint32_t | DestBurst
int32_t | SourceBlockAddressOffset
int32_t | DestBlockAddressOffset

Detailed Description

MDMA Configuration Structure definition.

Definition at line 67 of file stm32h7xx_hal_mdma.h.

Field Documentation

uint32_t MDMA_InitTypeDef::BufferTransferLength

Specifies the buffer Transfer Length (number of bytes), this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)

Definition at line 99 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_JPEG_Resume(), HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), JPEG_DMA_StartProcess(), JPEG_MDMAInCpltCallback(), and MDMA_Init().

uint32_t MDMA_InitTypeDef::DataAlignment

Specifies the source to destination Memory data packing/padding mode. This parameter can be a value of MDMA data alignment

Definition at line 96 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

int32_t MDMA_InitTypeDef::DestBlockAddressOffset

this field specifies the Next block destination address offset signed value : if > 0 then increment the next block destination Address by offset from where the last block ends if < 0 then decrement the next block destination Address by offset from where the last block ends if == 0, the next block destination address starts from where the last block ends

Definition at line 125 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), and MDMA_Init().

uint32_t MDMA_InitTypeDef::DestBurst

Specifies the Burst transfer configuration for the destination memory transfers. It specifies the amount of data to be transferred in a single non interruptable transaction. This parameter can be a value of MDMA Destination burst

Note:
: the burst may be FIXED/INCR based on DestinationInc value , the BURST must be programmed as to ensure that the burst size will be lower than than BufferTransferLength

Definition at line 110 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

uint32_t MDMA_InitTypeDef::DestDataSize

Specifies the destination data size. This parameter can be a value of MDMA Destination data size

Definition at line 92 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), and MDMA_Init().

uint32_t MDMA_InitTypeDef::DestinationInc

Specifies if the Destination increment mode . This parameter can be a value of MDMA Destination increment mode

Definition at line 86 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), and MDMA_Init().

uint32_t MDMA_InitTypeDef::Endianness

Specifies if the MDMA transactions preserve the Little endianness. This parameter can be a value of MDMA Endianness

Definition at line 80 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), and MDMA_Init().

uint32_t MDMA_InitTypeDef::Priority

Specifies the software priority for the MDMAy channelx. This parameter can be a value of MDMA Priority level

Definition at line 77 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), and MDMA_Init().

uint32_t MDMA_InitTypeDef::Request

Specifies the MDMA request. This parameter can be a value of MDMA Request selection

Definition at line 70 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), HAL_MDMA_Start(), HAL_MDMA_Start_IT(), and MDMA_Init().

int32_t MDMA_InitTypeDef::SourceBlockAddressOffset

this field specifies the Next block source address offset signed value : if > 0 then increment the next block source Address by offset from where the last block ends if < 0 then decrement the next block source Address by offset from where the last block ends if == 0, the next block source address starts from where the last block ends

Definition at line 118 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), and MDMA_Init().

uint32_t MDMA_InitTypeDef::SourceBurst

Specifies the Burst transfer configuration for the source memory transfers. It specifies the amount of data to be transferred in a single non interruptable transaction. This parameter can be a value of MDMA Source burst

Note:
: the burst may be FIXED/INCR based on SourceInc value , the BURST must be programmed as to ensure that the burst size will be lower than than BufferTransferLength

Definition at line 102 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), and MDMA_Init().

uint32_t MDMA_InitTypeDef::SourceDataSize

Specifies the source data size. This parameter can be a value of MDMA Source data size

Definition at line 89 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

uint32_t MDMA_InitTypeDef::SourceInc

Specifies if the Source increment mode . This parameter can be a value of MDMA Source increment mode

Definition at line 83 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), and MDMA_Init().

uint32_t MDMA_InitTypeDef::TransferTriggerMode

Specifies the Trigger Transfer mode : each request triggers a : a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer This parameter can be a value of MDMA Transfer Trigger Mode

Definition at line 73 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), and MDMA_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_mdma.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA_LinkNodeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
MDMA_LinkNodeTypeDef Struct Reference
MDMA Exported Types

HAL MDMA linked list node structure definition. More...

#include <stm32h7xx_hal_mdma.h>

Data Fields

__IO uint32_t | CTCR
__IO uint32_t | CBNDTR
__IO uint32_t | CSAR
__IO uint32_t | CDAR
__IO uint32_t | CBRUR
__IO uint32_t | CLAR
__IO uint32_t | CTBR
__IO uint32_t | Reserved
__IO uint32_t | CMAR
__IO uint32_t | CMDR

Detailed Description

HAL MDMA linked list node structure definition.

Note:
The Linked list node allows to define a new MDMA configuration (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers). When CLAR register is configured to a non NULL value , each time a transfer ends, a new configuration (linked list node) is automatically loaded from the address given in CLAR register.

Definition at line 140 of file stm32h7xx_hal_mdma.h.

Field Documentation

__IO uint32_t MDMA_LinkNodeTypeDef::CBNDTR

New CBNDTR register configuration for the given MDMA linked list node

Definition at line 143 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

__IO uint32_t MDMA_LinkNodeTypeDef::CBRUR

New CBRUR register configuration for the given MDMA linked list node

Definition at line 146 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

__IO uint32_t MDMA_LinkNodeTypeDef::CDAR

New CDAR register configuration for the given MDMA linked list node

Definition at line 145 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

__IO uint32_t MDMA_LinkNodeTypeDef::CLAR

New CLAR register configuration for the given MDMA linked list node

Definition at line 147 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_AddNode(), HAL_MDMA_LinkedList_CreateNode(), HAL_MDMA_LinkedList_DisableCircularMode(), HAL_MDMA_LinkedList_EnableCircularMode(), and HAL_MDMA_LinkedList_RemoveNode().

__IO uint32_t MDMA_LinkNodeTypeDef::CMAR

New CMAR register configuration for the given MDMA linked list node

Definition at line 150 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

__IO uint32_t MDMA_LinkNodeTypeDef::CMDR

New CMDR register configuration for the given MDMA linked list node

Definition at line 151 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

__IO uint32_t MDMA_LinkNodeTypeDef::CSAR

New CSAR register configuration for the given MDMA linked list node

Definition at line 144 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

__IO uint32_t MDMA_LinkNodeTypeDef::CTBR

New CTBR register configuration for the given MDMA linked list node

Definition at line 148 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

__IO uint32_t MDMA_LinkNodeTypeDef::CTCR

New CTCR register configuration for the given MDMA linked list node

Definition at line 142 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

__IO uint32_t MDMA_LinkNodeTypeDef::Reserved

Reserved register

Definition at line 149 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_mdma.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA_LinkNodeConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
MDMA_LinkNodeConfTypeDef Struct Reference
MDMA Exported Types

HAL MDMA linked list node configuration structure definition. More...

#include <stm32h7xx_hal_mdma.h>

Data Fields

MDMA_InitTypeDef Init
uint32_t | SrcAddress
uint32_t | DstAddress
uint32_t | BlockDataLength
uint32_t | BlockCount
uint32_t | PostRequestMaskAddress
uint32_t | PostRequestMaskData

Detailed Description

HAL MDMA linked list node configuration structure definition.

Note:
used with HAL_MDMA_LinkedList_CreateNode function

Definition at line 159 of file stm32h7xx_hal_mdma.h.

Field Documentation

uint32_t MDMA_LinkNodeConfTypeDef::BlockCount

The number of a blocks to be transfer

Definition at line 165 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

uint32_t MDMA_LinkNodeConfTypeDef::BlockDataLength

The length of a block transfer in bytes

Definition at line 164 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

uint32_t MDMA_LinkNodeConfTypeDef::DstAddress

The destination memory address for the Linked list Node

Definition at line 163 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

MDMA_InitTypeDef MDMA_LinkNodeConfTypeDef::Init

configuration of the specified MDMA Linked List Node

Definition at line 161 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

uint32_t MDMA_LinkNodeConfTypeDef::PostRequestMaskAddress

specifies the address to be updated (written) with PostRequestMaskData after a request is served. PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served

Definition at line 167 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

uint32_t MDMA_LinkNodeConfTypeDef::PostRequestMaskData

specifies the value to be written to PostRequestMaskAddress after a request is served. PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served

Definition at line 170 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

uint32_t MDMA_LinkNodeConfTypeDef::SrcAddress

The source memory address for the Linked list Node

Definition at line 162 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_mdma.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: __MDMA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__MDMA_HandleTypeDef Struct Reference
MDMA Exported Types

MDMA handle Structure definition. More...

#include <stm32h7xx_hal_mdma.h>

Data Fields

MDMA_Channel_TypeDef * | Instance
MDMA_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_MDMA_StateTypeDef | State
void * | Parent
void(* | XferCpltCallback )(struct __MDMA_HandleTypeDef *hmdma)
void(* | XferBufferCpltCallback )(struct __MDMA_HandleTypeDef *hmdma)
void(* | XferBlockCpltCallback )(struct __MDMA_HandleTypeDef *hmdma)
void(* | XferRepeatBlockCpltCallback )(struct __MDMA_HandleTypeDef *hmdma)
void(* | XferErrorCallback )(struct __MDMA_HandleTypeDef *hmdma)
void(* | XferAbortCallback )(struct __MDMA_HandleTypeDef *hmdma)
MDMA_LinkNodeTypeDef * FirstLinkedListNodeAddress
MDMA_LinkNodeTypeDef * LastLinkedListNodeAddress
uint32_t | LinkedListNodeCounter
__IO uint32_t | ErrorCode

Detailed Description

MDMA handle Structure definition.

Definition at line 221 of file stm32h7xx_hal_mdma.h.

Field Documentation

__IO uint32_t __MDMA_HandleTypeDef::ErrorCode

MDMA Error code

Definition at line 259 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_Abort_IT(), HAL_MDMA_DeInit(), HAL_MDMA_GenerateSWRequest(), HAL_MDMA_GetError(), HAL_MDMA_Init(), HAL_MDMA_IRQHandler(), HAL_MDMA_PollForTransfer(), HAL_MDMA_Start(), and HAL_MDMA_Start_IT().

MDMA_LinkNodeTypeDef* __MDMA_HandleTypeDef::FirstLinkedListNodeAddress

specifies the first node address of the transfer list (after the initial node defined by the Init struct) this parameter is used internally by the MDMA driver to construct the liked list node

Definition at line 247 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_DeInit(), HAL_MDMA_Init(), HAL_MDMA_LinkedList_AddNode(), HAL_MDMA_LinkedList_DisableCircularMode(), HAL_MDMA_LinkedList_EnableCircularMode(), HAL_MDMA_LinkedList_RemoveNode(), and MDMA_SetConfig().

MDMA_InitTypeDef __MDMA_HandleTypeDef::Init

MDMA communication parameters

Definition at line 225 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_JPEG_Resume(), HAL_MDMA_Init(), HAL_MDMA_Start(), HAL_MDMA_Start_IT(), HAL_MMC_ConfigWideBusOperation(), HAL_MMC_InitCard(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), JPEG_DMA_StartProcess(), JPEG_MDMAInCpltCallback(), MDMA_Init(), and MMC_InitCard().

MDMA_Channel_TypeDef* __MDMA_HandleTypeDef::Instance

Register base address

Definition at line 223 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_ConfigPostRequestMask(), HAL_MDMA_DeInit(), HAL_MDMA_GenerateSWRequest(), HAL_MDMA_Init(), HAL_MDMA_IRQHandler(), HAL_MDMA_LinkedList_AddNode(), HAL_MDMA_LinkedList_RemoveNode(), HAL_MDMA_PollForTransfer(), HAL_MDMA_Start(), HAL_MDMA_Start_IT(), JPEG_DMA_EndProcess(), JPEG_MDMAInCpltCallback(), JPEG_MDMAOutCpltCallback(), MDMA_Init(), and MDMA_SetConfig().

MDMA_LinkNodeTypeDef* __MDMA_HandleTypeDef::LastLinkedListNodeAddress

specifies the last node address of the transfer list this parameter is used internally by the MDMA driver to construct the liked list node

Definition at line 253 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_DeInit(), HAL_MDMA_Init(), HAL_MDMA_LinkedList_AddNode(), HAL_MDMA_LinkedList_DisableCircularMode(), HAL_MDMA_LinkedList_EnableCircularMode(), and HAL_MDMA_LinkedList_RemoveNode().

uint32_t __MDMA_HandleTypeDef::LinkedListNodeCounter

Number of nodes in the MDMA linked list

Definition at line 257 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_DeInit(), HAL_MDMA_Init(), HAL_MDMA_LinkedList_AddNode(), HAL_MDMA_LinkedList_DisableCircularMode(), HAL_MDMA_LinkedList_EnableCircularMode(), and HAL_MDMA_LinkedList_RemoveNode().

HAL_LockTypeDef __MDMA_HandleTypeDef::Lock

MDMA locking object

Definition at line 228 of file stm32h7xx_hal_mdma.h.

void* __MDMA_HandleTypeDef::Parent

Parent object state

Definition at line 232 of file stm32h7xx_hal_mdma.h.

__IO HAL_MDMA_StateTypeDef __MDMA_HandleTypeDef::State

MDMA transfer state

Definition at line 230 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_Abort_IT(), HAL_MDMA_ConfigPostRequestMask(), HAL_MDMA_DeInit(), HAL_MDMA_GetState(), HAL_MDMA_Init(), HAL_MDMA_IRQHandler(), HAL_MDMA_LinkedList_AddNode(), HAL_MDMA_LinkedList_DisableCircularMode(), HAL_MDMA_LinkedList_EnableCircularMode(), HAL_MDMA_LinkedList_RemoveNode(), HAL_MDMA_PollForTransfer(), HAL_MDMA_RegisterCallback(), HAL_MDMA_Start(), HAL_MDMA_Start_IT(), HAL_MDMA_UnRegisterCallback(), and JPEG_DMA_ContinueProcess().

void(* __MDMA_HandleTypeDef::XferAbortCallback)(struct __MDMA_HandleTypeDef *hmdma)

MDMA transfer Abort callback

Definition at line 244 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), HAL_MDMA_RegisterCallback(), HAL_MDMA_UnRegisterCallback(), HAL_QSPI_Abort_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), and JPEG_DMA_StartProcess().

void(* __MDMA_HandleTypeDef::XferBlockCpltCallback)(struct __MDMA_HandleTypeDef *hmdma)

MDMA block transfer complete callback

Definition at line 238 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), HAL_MDMA_RegisterCallback(), HAL_MDMA_Start_IT(), and HAL_MDMA_UnRegisterCallback().

void(* __MDMA_HandleTypeDef::XferBufferCpltCallback)(struct __MDMA_HandleTypeDef *hmdma)

MDMA buffer transfer complete callback

Definition at line 236 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), HAL_MDMA_RegisterCallback(), HAL_MDMA_Start_IT(), and HAL_MDMA_UnRegisterCallback().

void(* __MDMA_HandleTypeDef::XferCpltCallback)(struct __MDMA_HandleTypeDef *hmdma)

MDMA transfer complete callback

Definition at line 234 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), HAL_MDMA_RegisterCallback(), HAL_MDMA_UnRegisterCallback(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), HAL_SDRAM_Read_DMA(), HAL_SDRAM_Write_DMA(), HAL_SRAM_Read_DMA(), HAL_SRAM_Write_DMA(), and JPEG_DMA_StartProcess().

void(* __MDMA_HandleTypeDef::XferErrorCallback)(struct __MDMA_HandleTypeDef *hmdma)

MDMA transfer error callback

Definition at line 242 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), HAL_MDMA_RegisterCallback(), HAL_MDMA_UnRegisterCallback(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), HAL_SDRAM_Read_DMA(), HAL_SDRAM_Write_DMA(), HAL_SRAM_Read_DMA(), HAL_SRAM_Write_DMA(), and JPEG_DMA_StartProcess().

void(* __MDMA_HandleTypeDef::XferRepeatBlockCpltCallback)(struct __MDMA_HandleTypeDef *hmdma)

MDMA block transfer repeat callback

Definition at line 240 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), HAL_MDMA_RegisterCallback(), HAL_MDMA_Start_IT(), and HAL_MDMA_UnRegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_mdma.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA Error Codes

Defines
MDMA Error Codes
MDMA Exported Constants

MDMA Error Codes. More...

Defines

#define | HAL_MDMA_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_MDMA_ERROR_READ_XFER ((uint32_t)0x00000001U)
#define | HAL_MDMA_ERROR_WRITE_XFER ((uint32_t)0x00000002U)
#define | HAL_MDMA_ERROR_MASK_DATA ((uint32_t)0x00000004U)
#define | HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U)
#define | HAL_MDMA_ERROR_ALIGNMENT ((uint32_t)0x00000010U)
#define | HAL_MDMA_ERROR_BLOCK_SIZE ((uint32_t)0x00000020U)
#define | HAL_MDMA_ERROR_TIMEOUT ((uint32_t)0x00000040U)
#define | HAL_MDMA_ERROR_NO_XFER ((uint32_t)0x00000080U)
#define | HAL_MDMA_ERROR_BUSY ((uint32_t)0x00000100U)

Detailed Description

MDMA Error Codes.

Define Documentation

#define HAL_MDMA_ERROR_ALIGNMENT ((uint32_t)0x00000010U)

Address/Size alignment error

Definition at line 283 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), and HAL_MDMA_PollForTransfer().

#define HAL_MDMA_ERROR_BLOCK_SIZE ((uint32_t)0x00000020U)

Block Size error

Definition at line 284 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), and HAL_MDMA_PollForTransfer().

#define HAL_MDMA_ERROR_BUSY ((uint32_t)0x00000100U)

DeInit or SW trigger requested with Xfer ongoing

Definition at line 287 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_DeInit(), and HAL_MDMA_GenerateSWRequest().

#define HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U)

Linked list Data error

Definition at line 282 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), and HAL_MDMA_PollForTransfer().

#define HAL_MDMA_ERROR_MASK_DATA ((uint32_t)0x00000004U)

Error Mask Data error

Definition at line 281 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), and HAL_MDMA_PollForTransfer().

#define HAL_MDMA_ERROR_NO_XFER ((uint32_t)0x00000080U)

Abort or SW trigger requested with no Xfer ongoing

Definition at line 286 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_Abort_IT(), HAL_MDMA_GenerateSWRequest(), and HAL_MDMA_PollForTransfer().

#define HAL_MDMA_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 278 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_DeInit(), HAL_MDMA_Init(), HAL_MDMA_IRQHandler(), HAL_MDMA_Start(), and HAL_MDMA_Start_IT().

#define HAL_MDMA_ERROR_READ_XFER ((uint32_t)0x00000001U)

Read Transfer error

Definition at line 279 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), and HAL_MDMA_PollForTransfer().

#define HAL_MDMA_ERROR_TIMEOUT ((uint32_t)0x00000040U)

Timeout error

Definition at line 285 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_Init(), and HAL_MDMA_PollForTransfer().

#define HAL_MDMA_ERROR_WRITE_XFER ((uint32_t)0x00000002U)

Write Transfer error

Definition at line 280 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), and HAL_MDMA_PollForTransfer().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA Request selection

Defines
MDMA Request selection
MDMA Exported Constants

MDMA_Request_selection. More...

Defines

#define | MDMA_REQUEST_DMA1_Stream0_TC ((uint32_t)0x00000000U)
#define | MDMA_REQUEST_DMA1_Stream1_TC ((uint32_t)0x00000001U)
#define | MDMA_REQUEST_DMA1_Stream2_TC ((uint32_t)0x00000002U)
#define | MDMA_REQUEST_DMA1_Stream3_TC ((uint32_t)0x00000003U)
#define | MDMA_REQUEST_DMA1_Stream4_TC ((uint32_t)0x00000004U)
#define | MDMA_REQUEST_DMA1_Stream5_TC ((uint32_t)0x00000005U)
#define | MDMA_REQUEST_DMA1_Stream6_TC ((uint32_t)0x00000006U)
#define | MDMA_REQUEST_DMA1_Stream7_TC ((uint32_t)0x00000007U)
#define | MDMA_REQUEST_DMA2_Stream0_TC ((uint32_t)0x00000008U)
#define | MDMA_REQUEST_DMA2_Stream1_TC ((uint32_t)0x00000009U)
#define | MDMA_REQUEST_DMA2_Stream2_TC ((uint32_t)0x0000000AU)
#define | MDMA_REQUEST_DMA2_Stream3_TC ((uint32_t)0x0000000BU)
#define | MDMA_REQUEST_DMA2_Stream4_TC ((uint32_t)0x0000000CU)
#define | MDMA_REQUEST_DMA2_Stream5_TC ((uint32_t)0x0000000DU)
#define | MDMA_REQUEST_DMA2_Stream6_TC ((uint32_t)0x0000000EU)
#define | MDMA_REQUEST_DMA2_Stream7_TC ((uint32_t)0x0000000FU)
#define | MDMA_REQUEST_LTDC_LINE_IT ((uint32_t)0x00000010U)
#define | MDMA_REQUEST_JPEG_INFIFO_TH ((uint32_t)0x00000011U)
#define | MDMA_REQUEST_JPEG_INFIFO_NF ((uint32_t)0x00000012U)
#define | MDMA_REQUEST_JPEG_OUTFIFO_TH ((uint32_t)0x00000013U)
#define | MDMA_REQUEST_JPEG_OUTFIFO_NE ((uint32_t)0x00000014U)
#define | MDMA_REQUEST_JPEG_END_CONVERSION ((uint32_t)0x00000015U)
#define | MDMA_REQUEST_QUADSPI_FIFO_TH ((uint32_t)0x00000016U)
#define | MDMA_REQUEST_QUADSPI_TC ((uint32_t)0x00000017U)
#define | MDMA_REQUEST_DMA2D_CLUT_TC ((uint32_t)0x00000018U)
#define | MDMA_REQUEST_DMA2D_TC ((uint32_t)0x00000019U)
#define | MDMA_REQUEST_DMA2D_TW ((uint32_t)0x0000001AU)
#define | MDMA_REQUEST_SDMMC1_END_DATA ((uint32_t)0x0000001DU)
#define | MDMA_REQUEST_SW ((uint32_t)0x40000000U)

Detailed Description

MDMA_Request_selection.

Define Documentation

#define MDMA_REQUEST_DMA1_Stream0_TC ((uint32_t)0x00000000U)

MDMA HW request is DMA1 Stream 0 Transfer Complete Flag

Definition at line 298 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA1_Stream1_TC ((uint32_t)0x00000001U)

MDMA HW request is DMA1 Stream 1 Transfer Complete Flag

Definition at line 299 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA1_Stream2_TC ((uint32_t)0x00000002U)

MDMA HW request is DMA1 Stream 2 Transfer Complete Flag

Definition at line 300 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA1_Stream3_TC ((uint32_t)0x00000003U)

MDMA HW request is DMA1 Stream 3 Transfer Complete Flag

Definition at line 301 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA1_Stream4_TC ((uint32_t)0x00000004U)

MDMA HW request is DMA1 Stream 4 Transfer Complete Flag

Definition at line 302 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA1_Stream5_TC ((uint32_t)0x00000005U)

MDMA HW request is DMA1 Stream 5 Transfer Complete Flag

Definition at line 303 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA1_Stream6_TC ((uint32_t)0x00000006U)

MDMA HW request is DMA1 Stream 6 Transfer Complete Flag

Definition at line 304 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA1_Stream7_TC ((uint32_t)0x00000007U)

MDMA HW request is DMA1 Stream 7 Transfer Complete Flag

Definition at line 305 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2_Stream0_TC ((uint32_t)0x00000008U)

MDMA HW request is DMA2 Stream 0 Transfer Complete Flag

Definition at line 306 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2_Stream1_TC ((uint32_t)0x00000009U)

MDMA HW request is DMA2 Stream 1 Transfer Complete Flag

Definition at line 307 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2_Stream2_TC ((uint32_t)0x0000000AU)

MDMA HW request is DMA2 Stream 2 Transfer Complete Flag

Definition at line 308 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2_Stream3_TC ((uint32_t)0x0000000BU)

MDMA HW request is DMA2 Stream 3 Transfer Complete Flag

Definition at line 309 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2_Stream4_TC ((uint32_t)0x0000000CU)

MDMA HW request is DMA2 Stream 4 Transfer Complete Flag

Definition at line 310 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2_Stream5_TC ((uint32_t)0x0000000DU)

MDMA HW request is DMA2 Stream 5 Transfer Complete Flag

Definition at line 311 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2_Stream6_TC ((uint32_t)0x0000000EU)

MDMA HW request is DMA2 Stream 6 Transfer Complete Flag

Definition at line 312 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2_Stream7_TC ((uint32_t)0x0000000FU)

MDMA HW request is DMA2 Stream 7 Transfer Complete Flag

Definition at line 313 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2D_CLUT_TC ((uint32_t)0x00000018U)

MDMA HW request is DMA2D CLUT Transfer Complete Flag

Definition at line 322 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2D_TC ((uint32_t)0x00000019U)

MDMA HW request is DMA2D Transfer Complete Flag

Definition at line 323 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_DMA2D_TW ((uint32_t)0x0000001AU)

MDMA HW request is DMA2D Transfer Watermark Flag

Definition at line 324 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_JPEG_END_CONVERSION ((uint32_t)0x00000015U)

MDMA HW request is JPEG End of conversion Flag

Definition at line 319 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_JPEG_INFIFO_NF ((uint32_t)0x00000012U)

MDMA HW request is JPEG Input FIFO not full Flag

Definition at line 316 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_JPEG_INFIFO_TH ((uint32_t)0x00000011U)

MDMA HW request is JPEG Input FIFO threshold Flag

Definition at line 315 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_JPEG_OUTFIFO_NE ((uint32_t)0x00000014U)

MDMA HW request is JPEG Output FIFO not empty Flag

Definition at line 318 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_JPEG_OUTFIFO_TH ((uint32_t)0x00000013U)

MDMA HW request is JPEG Output FIFO threshold Flag

Definition at line 317 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_LTDC_LINE_IT ((uint32_t)0x00000010U)

MDMA HW request is LTDC Line interrupt Flag

Definition at line 314 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_QUADSPI_FIFO_TH ((uint32_t)0x00000016U)

MDMA HW request is QSPI FIFO threshold Flag

Definition at line 320 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_QUADSPI_TC ((uint32_t)0x00000017U)

MDMA HW request is QSPI Transfer complete Flag

Definition at line 321 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_SDMMC1_END_DATA ((uint32_t)0x0000001DU)

MDMA HW request is SDMMC1 End of Data Flag

Definition at line 331 of file stm32h7xx_hal_mdma.h.

#define MDMA_REQUEST_SW ((uint32_t)0x40000000U)

MDMA SW request

Definition at line 333 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode(), HAL_MDMA_Start(), HAL_MDMA_Start_IT(), and MDMA_Init().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA Transfer Trigger Mode

Defines
MDMA Transfer Trigger Mode
MDMA Exported Constants

MDMA Transfer Trigger Mode. More...

Defines

#define | MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U)
#define | MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0)
#define | MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1)
#define | MDMA_FULL_TRANSFER ((uint32_t)MDMA_CTCR_TRGM)

Detailed Description

MDMA Transfer Trigger Mode.

Define Documentation

#define MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0)

Each MDMA request (SW or HW) triggers a block transfer

Definition at line 344 of file stm32h7xx_hal_mdma.h.

#define MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U)

Each MDMA request (SW or HW) triggers a buffer transfer

Definition at line 343 of file stm32h7xx_hal_mdma.h.

#define MDMA_FULL_TRANSFER ((uint32_t)MDMA_CTCR_TRGM)

Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any

Definition at line 346 of file stm32h7xx_hal_mdma.h.

#define MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1)

Each MDMA request (SW or HW) triggers a repeated block transfer

Definition at line 345 of file stm32h7xx_hal_mdma.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA Priority level

Defines
MDMA Priority level
MDMA Exported Constants

MDMA Priority level. More...

Defines

#define | MDMA_PRIORITY_LOW ((uint32_t)0x00000000U)
#define | MDMA_PRIORITY_MEDIUM ((uint32_t)MDMA_CCR_PL_0)
#define | MDMA_PRIORITY_HIGH ((uint32_t)MDMA_CCR_PL_1)
#define | MDMA_PRIORITY_VERY_HIGH ((uint32_t)MDMA_CCR_PL)

Detailed Description

MDMA Priority level.

Define Documentation

#define MDMA_PRIORITY_HIGH ((uint32_t)MDMA_CCR_PL_1)

Priority level: High

Definition at line 358 of file stm32h7xx_hal_mdma.h.

#define MDMA_PRIORITY_LOW ((uint32_t)0x00000000U)

Priority level: Low

Definition at line 356 of file stm32h7xx_hal_mdma.h.

#define MDMA_PRIORITY_MEDIUM ((uint32_t)MDMA_CCR_PL_0)

Priority level: Medium

Definition at line 357 of file stm32h7xx_hal_mdma.h.

#define MDMA_PRIORITY_VERY_HIGH ((uint32_t)MDMA_CCR_PL)

Priority level: Very High

Definition at line 359 of file stm32h7xx_hal_mdma.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA Endianness

Defines
MDMA Endianness
MDMA Exported Constants

MDMA Endianness. More...

Defines

#define | MDMA_LITTLE_ENDIANNESS_PRESERVE ((uint32_t)0x00000000U)
#define | MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX)
#define | MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX)
#define | MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX)

Detailed Description

MDMA Endianness.

Define Documentation

#define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX)

BYTEs endianness exchange when destination data size is > Byte

Definition at line 371 of file stm32h7xx_hal_mdma.h.

#define MDMA_LITTLE_ENDIANNESS_PRESERVE ((uint32_t)0x00000000U)

little endianness preserve

Definition at line 370 of file stm32h7xx_hal_mdma.h.

#define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX)

HALF WORDs endianness exchange when destination data size is > HALF WORD

Definition at line 372 of file stm32h7xx_hal_mdma.h.

#define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX)

WORDs endianness exchange when destination data size is > DOUBLE WORD

Definition at line 373 of file stm32h7xx_hal_mdma.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA Source increment mode

Defines
MDMA Source increment mode
MDMA Exported Constants

MDMA Source increment mode. More...

Defines

#define | MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U)
#define | MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1)
#define | MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0)
#define | MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1)
#define | MDMA_SRC_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS)
#define | MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC)
#define | MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0)
#define | MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1)
#define | MDMA_SRC_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS)

Detailed Description

MDMA Source increment mode.

Define Documentation

#define MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC)

Source address pointer is decremented by a BYTE (8 bits)

Definition at line 388 of file stm32h7xx_hal_mdma.h.

#define MDMA_SRC_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS)

Source address pointer is decremented by a double Word (64 bits))

Definition at line 391 of file stm32h7xx_hal_mdma.h.

#define MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0)

Source address pointer is decremented by a half Word (16 bits)

Definition at line 389 of file stm32h7xx_hal_mdma.h.

#define MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1)

Source address pointer is decremented by a Word (32 bits)

Definition at line 390 of file stm32h7xx_hal_mdma.h.

#define MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1)

Source address pointer is incremented by a BYTE (8 bits)

Definition at line 384 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_QSPI_Transmit_DMA().

#define MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U)

Source address pointer is fixed

Definition at line 383 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_QSPI_Receive_DMA().

#define MDMA_SRC_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS)

Source address pointer is incremented by a double Word (64 bits))

Definition at line 387 of file stm32h7xx_hal_mdma.h.

#define MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0)

Source address pointer is incremented by a half Word (16 bits)

Definition at line 385 of file stm32h7xx_hal_mdma.h.

#define MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1)

Source address pointer is incremented by a Word (32 bits)

Definition at line 386 of file stm32h7xx_hal_mdma.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA Destination increment mode

Defines
MDMA Destination increment mode
MDMA Exported Constants

MDMA Destination increment mode. More...

Defines

#define | MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U)
#define | MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1)
#define | MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0)
#define | MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1)
#define | MDMA_DEST_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS)
#define | MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC)
#define | MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0)
#define | MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1)
#define | MDMA_DEST_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS)

Detailed Description

MDMA Destination increment mode.

Define Documentation

#define MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC)

Source address pointer is decremented by a BYTE (8 bits)

Definition at line 406 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS)

Source address pointer is decremented by a double Word (64 bits))

Definition at line 409 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0)

Source address pointer is decremented by a half Word (16 bits)

Definition at line 407 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1)

Source address pointer is decremented by a Word (32 bits)

Definition at line 408 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1)

Source address pointer is incremented by a BYTE (8 bits)

Definition at line 402 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_QSPI_Receive_DMA().

#define MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U)

Source address pointer is fixed

Definition at line 401 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_QSPI_Transmit_DMA().

#define MDMA_DEST_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS)

Source address pointer is incremented by a double Word (64 bits))

Definition at line 405 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0)

Source address pointer is incremented by a half Word (16 bits)

Definition at line 403 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1)

Source address pointer is incremented by a Word (32 bits)

Definition at line 404 of file stm32h7xx_hal_mdma.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA Source data size

Defines
MDMA Source data size
MDMA Exported Constants

MDMA Source data size. More...

Defines

#define | MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U)
#define | MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0)
#define | MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1)
#define | MDMA_SRC_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_SSIZE)

Detailed Description

MDMA Source data size.

Define Documentation

#define MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U)

Source data size is Byte

Definition at line 419 of file stm32h7xx_hal_mdma.h.

#define MDMA_SRC_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_SSIZE)

Source data size is double word

Definition at line 422 of file stm32h7xx_hal_mdma.h.

#define MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0)

Source data size is half word

Definition at line 420 of file stm32h7xx_hal_mdma.h.

#define MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1)

Source data size is word

Definition at line 421 of file stm32h7xx_hal_mdma.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA Destination data size

Defines
MDMA Destination data size
MDMA Exported Constants

MDMA Destination data size. More...

Defines

#define | MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U)
#define | MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0)
#define | MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1)
#define | MDMA_DEST_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_DSIZE)

Detailed Description

MDMA Destination data size.

Define Documentation

#define MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U)

Destination data size is Byte

Definition at line 432 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_DSIZE)

Destination data size is double word

Definition at line 435 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0)

Destination data size is half word

Definition at line 433 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1)

Destination data size is word

Definition at line 434 of file stm32h7xx_hal_mdma.h.

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STM32H753xx HAL User Manual: MDMA data alignment

Defines
MDMA data alignment
MDMA Exported Constants

MDMA MDMA data alignment. More...

Defines

#define | MDMA_DATAALIGN_PACKENABLE ((uint32_t)MDMA_CTCR_PKE)
#define | MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
#define | MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0)
#define | MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1)

Detailed Description

MDMA MDMA data alignment.

Define Documentation

#define MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1)

Left Aligned (padded with 0s)

Definition at line 450 of file stm32h7xx_hal_mdma.h.

#define MDMA_DATAALIGN_PACKENABLE ((uint32_t)MDMA_CTCR_PKE)

The source data is packed/un-packed into the destination data size All data are right aligned, in Little Endien mode.

Definition at line 445 of file stm32h7xx_hal_mdma.h.

#define MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U)

Right Aligned, padded w/ 0s (default)

Definition at line 447 of file stm32h7xx_hal_mdma.h.

#define MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0)

Right Aligned, Sign extended , Note : this mode is allowed only if the Source data size smaller than Destination data size

Definition at line 448 of file stm32h7xx_hal_mdma.h.

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STM32H753xx HAL User Manual: MDMA Source burst

Defines
MDMA Source burst
MDMA Exported Constants

MDMA Source burst. More...

Defines

#define | MDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U)
#define | MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0)
#define | MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1)
#define | MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1)
#define | MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2)
#define | MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2)
#define | MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2)
#define | MDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST)

Detailed Description

MDMA Source burst.

Define Documentation

#define MDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST)

Burst 128 beats

Definition at line 467 of file stm32h7xx_hal_mdma.h.

#define MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2)

Burst 16 beats

Definition at line 464 of file stm32h7xx_hal_mdma.h.

#define MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0)

Burst 2 beats

Definition at line 461 of file stm32h7xx_hal_mdma.h.

#define MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2)

Burst 32 beats

Definition at line 465 of file stm32h7xx_hal_mdma.h.

#define MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1)

Burst 4 beats

Definition at line 462 of file stm32h7xx_hal_mdma.h.

#define MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2)

Burst 64 beats

Definition at line 466 of file stm32h7xx_hal_mdma.h.

#define MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1)

Burst 8 beats

Definition at line 463 of file stm32h7xx_hal_mdma.h.

#define MDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U)

single transfer

Definition at line 460 of file stm32h7xx_hal_mdma.h.

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STM32H753xx HAL User Manual: MDMA Destination burst

Defines
MDMA Destination burst
MDMA Exported Constants

MDMA Destination burst. More...

Defines

#define | MDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U)
#define | MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0)
#define | MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1)
#define | MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1)
#define | MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2)
#define | MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2)
#define | MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2)
#define | MDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST)

Detailed Description

MDMA Destination burst.

Define Documentation

#define MDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST)

Burst 128 beats

Definition at line 484 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2)

Burst 16 beats

Definition at line 481 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0)

Burst 2 beats

Definition at line 478 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2)

Burst 32 beats

Definition at line 482 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1)

Burst 4 beats

Definition at line 479 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2)

Burst 64 beats

Definition at line 483 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1)

Burst 8 beats

Definition at line 480 of file stm32h7xx_hal_mdma.h.

#define MDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U)

single transfer

Definition at line 477 of file stm32h7xx_hal_mdma.h.

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STM32H753xx HAL User Manual: MDMA interrupt enable definitions

Defines
MDMA interrupt enable definitions
MDMA Exported Constants

MDMA interrupt enable definitions. More...

Defines

#define | MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE)
#define | MDMA_IT_CTC ((uint32_t)MDMA_CCR_CTCIE)
#define | MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE)
#define | MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE)
#define | MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE)

Detailed Description

MDMA interrupt enable definitions.

Define Documentation

#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE)

Buffer Transfer Complete interrupt

Definition at line 498 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_IRQHandler(), and HAL_MDMA_Start_IT().

#define MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE)

Block Repeat Transfer interrupt

Definition at line 496 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_IRQHandler(), and HAL_MDMA_Start_IT().

#define MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE)

Block Transfer interrupt

Definition at line 497 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_IRQHandler(), and HAL_MDMA_Start_IT().

#define MDMA_IT_CTC ((uint32_t)MDMA_CCR_CTCIE)

Channel Transfer Complete interrupt

Definition at line 495 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_IRQHandler(), and HAL_MDMA_Start_IT().

#define MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE)

Transfer Error interrupt

Definition at line 494 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_IRQHandler(), and HAL_MDMA_Start_IT().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA flag definitions

Defines
MDMA flag definitions
MDMA Exported Constants

MDMA flag definitions. More...

Defines

#define | MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF)
#define | MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF)
#define | MDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF)
#define | MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF)
#define | MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF)
#define | MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA)

Detailed Description

MDMA flag definitions.

Define Documentation

#define MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF)

BuFfer Transfer complete flag

Definition at line 512 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_DeInit(), HAL_MDMA_IRQHandler(), and HAL_MDMA_PollForTransfer().

#define MDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF)

Block Repeat Transfer complete flag

Definition at line 510 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_DeInit(), HAL_MDMA_IRQHandler(), and HAL_MDMA_PollForTransfer().

#define MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF)

Block Transfer complete flag

Definition at line 511 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_DeInit(), HAL_MDMA_IRQHandler(), and HAL_MDMA_PollForTransfer().

#define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA)

Channel ReQest Active flag

Definition at line 513 of file stm32h7xx_hal_mdma.h.

#define MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF)

Channel Transfer Complete flag

Definition at line 509 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_DeInit(), HAL_MDMA_IRQHandler(), HAL_MDMA_PollForTransfer(), and MDMA_SetConfig().

#define MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF)

Transfer Error flag

Definition at line 508 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_DeInit(), HAL_MDMA_IRQHandler(), HAL_MDMA_PollForTransfer(), and MDMA_SetConfig().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA Exported Macros

Defines
MDMA Exported Macros
MDMA

Defines

#define | __HAL_MDMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= MDMA_CCR_EN)
Enable the specified MDMA Channel.
#define | __HAL_MDMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~MDMA_CCR_EN)
Disable the specified DMA Channel.
#define | __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CISR & (__FLAG__))
Get the MDMA Channel pending flags.
#define | __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__))
Clear the MDMA Stream pending flags.
#define | __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
Enables the specified DMA Channel interrupts.
#define | __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
Disables the specified MDMA Channel interrupts.
#define | __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
Checks whether the specified MDMA Channel interrupt is enabled or not.

Define Documentation

#define __HAL_MDMA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->CIFCR = (__FLAG__))

Clear the MDMA Stream pending flags.

Parameters:
__HANDLE__,: MDMA handle
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • MDMA_FLAG_TE : Transfer Error flag.
  • MDMA_FLAG_CTC : Channel Transfer Complete flag.
  • MDMA_FLAG_BRT : Block Repeat Transfer flag.
  • MDMA_FLAG_BT : Block Transfer complete flag.
  • MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
Return values:
None

Definition at line 570 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_DeInit(), HAL_MDMA_IRQHandler(), HAL_MDMA_PollForTransfer(), and MDMA_SetConfig().

#define __HAL_MDMA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CCR &= ~MDMA_CCR_EN)

Disable the specified DMA Channel.

Parameters:
__HANDLE__,: MDMA handle
Return values:
None

Definition at line 541 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), HAL_MDMA_Abort_IT(), HAL_MDMA_DeInit(), HAL_MDMA_Init(), HAL_MDMA_IRQHandler(), HAL_MDMA_Start(), HAL_MDMA_Start_IT(), and HAL_QSPI_IRQHandler().

#define __HAL_MDMA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))

Disables the specified MDMA Channel interrupts.

Parameters:
__HANDLE__,: MDMA handle
__INTERRUPT__,: specifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • MDMA_IT_TE : Transfer Error interrupt mask
  • MDMA_IT_CTC : Channel Transfer Complete interrupt mask
  • MDMA_IT_BRT : Block Repeat Transfer interrupt mask
  • MDMA_IT_BT : Block Transfer interrupt mask
  • MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
Return values:
None

Definition at line 598 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Abort(), and HAL_MDMA_IRQHandler().

#define __HAL_MDMA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CCR |= MDMA_CCR_EN)

Enable the specified MDMA Channel.

Parameters:
__HANDLE__,: MDMA handle
Return values:
None

Definition at line 534 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Start(), and HAL_MDMA_Start_IT().

#define __HAL_MDMA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))

Enables the specified DMA Channel interrupts.

Parameters:
__HANDLE__,: MDMA handle
__INTERRUPT__,: specifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • MDMA_IT_TE : Transfer Error interrupt mask
  • MDMA_IT_CTC : Channel Transfer Complete interrupt mask
  • MDMA_IT_BRT : Block Repeat Transfer interrupt mask
  • MDMA_IT_BT : Block Transfer interrupt mask
  • MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
Return values:
None

Definition at line 584 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Start_IT().

#define __HAL_MDMA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->CISR & (__FLAG__))

Get the MDMA Channel pending flags.

Parameters:
__HANDLE__,: MDMA handle
__FLAG__,: Get the specified flag. This parameter can be any combination of the following values:
  • MDMA_FLAG_TE : Transfer Error flag.
  • MDMA_FLAG_CTC : Channel Transfer Complete flag.
  • MDMA_FLAG_BRT : Block Repeat Transfer flag.
  • MDMA_FLAG_BT : Block Transfer complete flag.
  • MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
  • MDMA_FLAG_CRQA : Channel ReQest Active flag.
Return values:
The state of FLAG (SET or RESET).

Definition at line 556 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler(), and HAL_MDMA_PollForTransfer().

#define __HAL_MDMA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))

Checks whether the specified MDMA Channel interrupt is enabled or not.

Parameters:
__HANDLE__,: DMA handle
__INTERRUPT__,: specifies the DMA interrupt source to check.
  • MDMA_IT_TE : Transfer Error interrupt mask
  • MDMA_IT_CTC : Channel Transfer Complete interrupt mask
  • MDMA_IT_BRT : Block Repeat Transfer interrupt mask
  • MDMA_IT_BT : Block Transfer interrupt mask
  • MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
Return values:
The state of MDMA_IT (SET or RESET).

Definition at line 611 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_IRQHandler().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
MDMA Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_MDMA_Init (MDMA_HandleTypeDef *hmdma)
Initializes the MDMA according to the specified parameters in the MDMA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma)
DeInitializes the MDMA peripheral.
HAL_StatusTypeDef | HAL_MDMA_ConfigPostRequestMask (MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData)
Config the Post request Mask address and Mask data.
HAL_StatusTypeDef | HAL_MDMA_RegisterCallback (MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void(*pCallback)(MDMA_HandleTypeDef *_hmdma))
Register callbacks.
HAL_StatusTypeDef | HAL_MDMA_UnRegisterCallback (MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
             ##### Initialization and de-initialization functions  #####
 ===============================================================================
    [..]
    This section provides functions allowing to :
      Initialize and de-initialize the MDMA channel.
      Register and Unregister MDMA callbacks
    [..]
    The HAL_MDMA_Init() function follows the MDMA channel configuration procedures as described in
    reference manual.
    The HAL_MDMA_DeInit function allows to deinitialize the MDMA channel.
    HAL_MDMA_RegisterCallback and  HAL_MDMA_UnRegisterCallback functions allows
    respectevely to register/unregister an MDMA callback function.

Function Documentation

HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask | ( | MDMA_HandleTypeDef * | hmdma,
 |  | uint32_t | MaskAddress,
 |  | uint32_t | MaskData
 | ) |  |

Config the Post request Mask address and Mask data.

Parameters:
hmdma : pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
MaskAddress,: specifies the address to be updated (written) with MaskData after a request is served.
MaskData,: specifies the value to be written to MaskAddress after a request is served. MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served.
Return values:
HAL status

Definition at line 373 of file stm32h7xx_hal_mdma.c.

References HAL_MDMA_STATE_READY, __MDMA_HandleTypeDef::Instance, and __MDMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MDMA_DeInit ( MDMA_HandleTypeDef * hmdma )

DeInitializes the MDMA peripheral.

Parameters:
hmdma,: pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Stream.
Return values:
HAL status

Definition at line 313 of file stm32h7xx_hal_mdma.c.

References __HAL_MDMA_CLEAR_FLAG, __HAL_MDMA_DISABLE, __MDMA_HandleTypeDef::ErrorCode, __MDMA_HandleTypeDef::FirstLinkedListNodeAddress, HAL_MDMA_ERROR_BUSY, HAL_MDMA_ERROR_NONE, HAL_MDMA_STATE_BUSY, HAL_MDMA_STATE_RESET, __MDMA_HandleTypeDef::Instance, __MDMA_HandleTypeDef::LastLinkedListNodeAddress, __MDMA_HandleTypeDef::LinkedListNodeCounter, MDMA_FLAG_BFTC, MDMA_FLAG_BRT, MDMA_FLAG_BT, MDMA_FLAG_CTC, MDMA_FLAG_TE, and __MDMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MDMA_Init ( MDMA_HandleTypeDef * hmdma )

Initializes the MDMA according to the specified parameters in the MDMA_InitTypeDef and create the associated handle.

Parameters:
hmdma,: Pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Stream.
Return values:
HAL status

Definition at line 237 of file stm32h7xx_hal_mdma.c.

References __HAL_MDMA_DISABLE, assert_param, MDMA_InitTypeDef::BufferTransferLength, MDMA_InitTypeDef::DataAlignment, MDMA_InitTypeDef::DestBlockAddressOffset, MDMA_InitTypeDef::DestBurst, MDMA_InitTypeDef::DestDataSize, MDMA_InitTypeDef::DestinationInc, MDMA_InitTypeDef::Endianness, __MDMA_HandleTypeDef::ErrorCode, __MDMA_HandleTypeDef::FirstLinkedListNodeAddress, HAL_GetTick(), HAL_MDMA_ERROR_NONE, HAL_MDMA_ERROR_TIMEOUT, HAL_MDMA_STATE_BUSY, HAL_MDMA_STATE_ERROR, HAL_MDMA_STATE_READY, HAL_TIMEOUT_MDMA_ABORT, __MDMA_HandleTypeDef::Init, __MDMA_HandleTypeDef::Instance, IS_MDMA_BLOCK_ADDR_OFFSET, IS_MDMA_BUFFER_TRANSFER_LENGTH, IS_MDMA_DATA_ALIGNMENT, IS_MDMA_DESTINATION_BURST, IS_MDMA_DESTINATION_DATASIZE, IS_MDMA_DESTINATION_INC, IS_MDMA_ENDIANNESS_MODE, IS_MDMA_PRIORITY, IS_MDMA_REQUEST, IS_MDMA_SOURCE_BURST, IS_MDMA_SOURCE_DATASIZE, IS_MDMA_SOURCE_INC, IS_MDMA_TRANSFER_TRIGGER_MODE, __MDMA_HandleTypeDef::LastLinkedListNodeAddress, __MDMA_HandleTypeDef::LinkedListNodeCounter, MDMA_Init(), MDMA_InitTypeDef::Priority, MDMA_InitTypeDef::Request, MDMA_InitTypeDef::SourceBlockAddressOffset, MDMA_InitTypeDef::SourceBurst, MDMA_InitTypeDef::SourceDataSize, MDMA_InitTypeDef::SourceInc, __MDMA_HandleTypeDef::State, and MDMA_InitTypeDef::TransferTriggerMode.

Referenced by HAL_QSPI_Receive_DMA(), and HAL_QSPI_Transmit_DMA().

HAL_StatusTypeDef HAL_MDMA_RegisterCallback | ( | MDMA_HandleTypeDef * | hmdma,
 |  | HAL_MDMA_CallbackIDTypeDef | CallbackID,
 |  | void(*)(MDMA_HandleTypeDef *_hmdma) | pCallback
 | ) |  |

Register callbacks.

Parameters:
hmdma,: pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
CallbackID,: User Callback identifier
pCallback,: pointer to callbacsk function.
Return values:
HAL status

Definition at line 435 of file stm32h7xx_hal_mdma.c.

References HAL_MDMA_STATE_READY, HAL_MDMA_XFER_ABORT_CB_ID, HAL_MDMA_XFER_BLOCKCPLT_CB_ID, HAL_MDMA_XFER_BUFFERCPLT_CB_ID, HAL_MDMA_XFER_CPLT_CB_ID, HAL_MDMA_XFER_ERROR_CB_ID, HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID, __MDMA_HandleTypeDef::State, __MDMA_HandleTypeDef::XferAbortCallback, __MDMA_HandleTypeDef::XferBlockCpltCallback, __MDMA_HandleTypeDef::XferBufferCpltCallback, __MDMA_HandleTypeDef::XferCpltCallback, __MDMA_HandleTypeDef::XferErrorCallback, and __MDMA_HandleTypeDef::XferRepeatBlockCpltCallback.

HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback | ( | MDMA_HandleTypeDef * | hmdma,
 |  | HAL_MDMA_CallbackIDTypeDef | CallbackID
 | ) |  |

UnRegister callbacks.

Parameters:
hmdma,: pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
CallbackID,: User Callback identifier a HAL_MDMA_CallbackIDTypeDef ENUM as parameter.
Return values:
HAL status

Definition at line 500 of file stm32h7xx_hal_mdma.c.

References HAL_MDMA_STATE_READY, HAL_MDMA_XFER_ABORT_CB_ID, HAL_MDMA_XFER_ALL_CB_ID, HAL_MDMA_XFER_BLOCKCPLT_CB_ID, HAL_MDMA_XFER_BUFFERCPLT_CB_ID, HAL_MDMA_XFER_CPLT_CB_ID, HAL_MDMA_XFER_ERROR_CB_ID, HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID, __MDMA_HandleTypeDef::State, __MDMA_HandleTypeDef::XferAbortCallback, __MDMA_HandleTypeDef::XferBlockCpltCallback, __MDMA_HandleTypeDef::XferBufferCpltCallback, __MDMA_HandleTypeDef::XferCpltCallback, __MDMA_HandleTypeDef::XferErrorCallback, and __MDMA_HandleTypeDef::XferRepeatBlockCpltCallback.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Linked List operation functions

Functions
Linked List operation functions
MDMA Exported Functions

Linked list operation functions. More...

Functions

HAL_StatusTypeDef | HAL_MDMA_LinkedList_CreateNode (MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig)
Initializes an MDMA Link Node according to the specified parameters in the pMDMA_LinkedListNodeConfig .
HAL_StatusTypeDef | HAL_MDMA_LinkedList_AddNode (MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode)
Connect a node to the linked list.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_RemoveNode (MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode)
Disconnect/Remove a node from the transfer linked list.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_EnableCircularMode (MDMA_HandleTypeDef *hmdma)
Make the linked list circular by connecting the last node to the first.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_DisableCircularMode (MDMA_HandleTypeDef *hmdma)
Disable the linked list circular mode by setting the last node connection to null.

Detailed Description

Linked list operation functions.

 ===============================================================================
                      #####  Linked list operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Create a linked list node
      (+) Add a node to the MDMA linked list
      (+) Remove a node from the MDMA linked list
      (+) Enable/Disable linked list circular mode

Function Documentation

HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode | ( | MDMA_HandleTypeDef * | hmdma,
 |  | MDMA_LinkNodeTypeDef * | pNewNode,
 |  | MDMA_LinkNodeTypeDef * | pPrevNode
 | ) |  |

Connect a node to the linked list.

Parameters:
hmdma | : Pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
pNewNode | : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node to be add to the list.
pPrevNode | : Pointer to the new node position in the linked list or zero to insert the new node at the end of the list
Return values:
HAL status

Definition at line 737 of file stm32h7xx_hal_mdma.c.

References MDMA_LinkNodeTypeDef::CLAR, __MDMA_HandleTypeDef::FirstLinkedListNodeAddress, HAL_MDMA_STATE_BUSY, HAL_MDMA_STATE_READY, __MDMA_HandleTypeDef::Instance, __MDMA_HandleTypeDef::LastLinkedListNodeAddress, __MDMA_HandleTypeDef::LinkedListNodeCounter, and __MDMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode | ( | MDMA_LinkNodeTypeDef * | pNode,
 |  | MDMA_LinkNodeConfTypeDef * | pNodeConfig
 | ) |  |

Initializes an MDMA Link Node according to the specified parameters in the pMDMA_LinkedListNodeConfig .

Parameters:
pNode,: Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node registers configurations.
pNodeConfig,: Pointer to a MDMA_LinkNodeConfTypeDef structure that contains the configuration information for the specified MDMA Linked List Node.
Return values:
HAL status

Definition at line 594 of file stm32h7xx_hal_mdma.c.

References assert_param, MDMA_LinkNodeConfTypeDef::BlockCount, MDMA_LinkNodeConfTypeDef::BlockDataLength, MDMA_InitTypeDef::BufferTransferLength, MDMA_LinkNodeTypeDef::CBNDTR, MDMA_LinkNodeTypeDef::CBRUR, MDMA_LinkNodeTypeDef::CDAR, MDMA_LinkNodeTypeDef::CLAR, MDMA_LinkNodeTypeDef::CMAR, MDMA_LinkNodeTypeDef::CMDR, MDMA_LinkNodeTypeDef::CSAR, MDMA_LinkNodeTypeDef::CTBR, MDMA_LinkNodeTypeDef::CTCR, MDMA_InitTypeDef::DataAlignment, MDMA_InitTypeDef::DestBlockAddressOffset, MDMA_InitTypeDef::DestBurst, MDMA_InitTypeDef::DestDataSize, MDMA_InitTypeDef::DestinationInc, MDMA_LinkNodeConfTypeDef::DstAddress, MDMA_InitTypeDef::Endianness, MDMA_LinkNodeConfTypeDef::Init, IS_MDMA_BLOCK_ADDR_OFFSET, IS_MDMA_BLOCK_COUNT, IS_MDMA_BUFFER_TRANSFER_LENGTH, IS_MDMA_DATA_ALIGNMENT, IS_MDMA_DESTINATION_BURST, IS_MDMA_DESTINATION_DATASIZE, IS_MDMA_DESTINATION_INC, IS_MDMA_ENDIANNESS_MODE, IS_MDMA_PRIORITY, IS_MDMA_REQUEST, IS_MDMA_SOURCE_BURST, IS_MDMA_SOURCE_DATASIZE, IS_MDMA_SOURCE_INC, IS_MDMA_TRANSFER_LENGTH, IS_MDMA_TRANSFER_TRIGGER_MODE, MDMA_REQUEST_SW, MDMA_LinkNodeConfTypeDef::PostRequestMaskAddress, MDMA_LinkNodeConfTypeDef::PostRequestMaskData, MDMA_InitTypeDef::Priority, MDMA_InitTypeDef::Request, MDMA_LinkNodeTypeDef::Reserved, MDMA_InitTypeDef::SourceBlockAddressOffset, MDMA_InitTypeDef::SourceBurst, MDMA_InitTypeDef::SourceDataSize, MDMA_InitTypeDef::SourceInc, MDMA_LinkNodeConfTypeDef::SrcAddress, and MDMA_InitTypeDef::TransferTriggerMode.

HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode ( MDMA_HandleTypeDef * hmdma )

Disable the linked list circular mode by setting the last node connection to null.

Parameters:
hmdma : Pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
Return values:
HAL status

Definition at line 1027 of file stm32h7xx_hal_mdma.c.

References MDMA_LinkNodeTypeDef::CLAR, __MDMA_HandleTypeDef::FirstLinkedListNodeAddress, HAL_MDMA_STATE_BUSY, HAL_MDMA_STATE_READY, __MDMA_HandleTypeDef::LastLinkedListNodeAddress, __MDMA_HandleTypeDef::LinkedListNodeCounter, and __MDMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode ( MDMA_HandleTypeDef * hmdma )

Make the linked list circular by connecting the last node to the first.

Parameters:
hmdma : Pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
Return values:
HAL status

Definition at line 983 of file stm32h7xx_hal_mdma.c.

References MDMA_LinkNodeTypeDef::CLAR, __MDMA_HandleTypeDef::FirstLinkedListNodeAddress, HAL_MDMA_STATE_BUSY, HAL_MDMA_STATE_READY, __MDMA_HandleTypeDef::LastLinkedListNodeAddress, __MDMA_HandleTypeDef::LinkedListNodeCounter, and __MDMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode | ( | MDMA_HandleTypeDef * | hmdma,
 |  | MDMA_LinkNodeTypeDef * | pNode
 | ) |  |

Disconnect/Remove a node from the transfer linked list.

Parameters:
hmdma | : Pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
pNode | : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node to be removed from the list.
Return values:
HAL status

Definition at line 870 of file stm32h7xx_hal_mdma.c.

References MDMA_LinkNodeTypeDef::CLAR, __MDMA_HandleTypeDef::FirstLinkedListNodeAddress, HAL_MDMA_STATE_BUSY, HAL_MDMA_STATE_READY, __MDMA_HandleTypeDef::Instance, __MDMA_HandleTypeDef::LastLinkedListNodeAddress, __MDMA_HandleTypeDef::LinkedListNodeCounter, and __MDMA_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I/O operation functions

Functions
I/O operation functions
MDMA Exported Functions

I/O operation functions. More...

Functions

HAL_StatusTypeDef | HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
Starts the MDMA Transfer.
HAL_StatusTypeDef | HAL_MDMA_Start_IT (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
Starts the MDMA Transfer with interrupts enabled.
HAL_StatusTypeDef | HAL_MDMA_Abort (MDMA_HandleTypeDef *hmdma)
Aborts the MDMA Transfer.
HAL_StatusTypeDef | HAL_MDMA_Abort_IT (MDMA_HandleTypeDef *hmdma)
Aborts the MDMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_MDMA_PollForTransfer (MDMA_HandleTypeDef *hmdma, uint32_t CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
HAL_StatusTypeDef | HAL_MDMA_GenerateSWRequest (MDMA_HandleTypeDef *hmdma)
Generate an MDMA SW request trigger to activate the request on the given Channel.
void | HAL_MDMA_IRQHandler (MDMA_HandleTypeDef *hmdma)
Handles MDMA interrupt request.

Detailed Description

I/O operation functions.

 ===============================================================================
                      #####  IO operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the source, destination address and data length and Start MDMA transfer
      (+) Configure the source, destination address and data length and
          Start MDMA transfer with interrupt
      (+) Abort MDMA transfer
      (+) Poll for transfer complete
      (+) Generate a SW request (when Request is set to MDMA_REQUEST_SW)
      (+) Handle MDMA interrupt request

Function Documentation

HAL_StatusTypeDef HAL_MDMA_Abort ( MDMA_HandleTypeDef * hmdma )

Aborts the MDMA Transfer.

Parameters:
hmdma : pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
Note:
After disabling a MDMA Stream, a check for wait until the MDMA Channel is effectively disabled is added. If a Stream is disabled while a data transfer is ongoing, the current data will be transferred and the Stream will be effectively disabled only after the transfer of this single data is finished.
Return values:
HAL status

Definition at line 1243 of file stm32h7xx_hal_mdma.c.

References __HAL_MDMA_CLEAR_FLAG, __HAL_MDMA_DISABLE, __HAL_MDMA_DISABLE_IT, __MDMA_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_MDMA_ERROR_NO_XFER, HAL_MDMA_ERROR_TIMEOUT, HAL_MDMA_STATE_BUSY, HAL_MDMA_STATE_ERROR, HAL_MDMA_STATE_READY, HAL_TIMEOUT_MDMA_ABORT, __MDMA_HandleTypeDef::Instance, MDMA_FLAG_BFTC, MDMA_FLAG_BRT, MDMA_FLAG_BT, MDMA_FLAG_CTC, MDMA_FLAG_TE, MDMA_IT_BFTC, MDMA_IT_BRT, MDMA_IT_BT, MDMA_IT_CTC, MDMA_IT_TE, and __MDMA_HandleTypeDef::State.

Referenced by HAL_JPEG_Abort(), HAL_MDMA_PollForTransfer(), and HAL_QSPI_Abort().

HAL_StatusTypeDef HAL_MDMA_Abort_IT ( MDMA_HandleTypeDef * hmdma )

Aborts the MDMA Transfer in Interrupt mode.

Parameters:
hmdma : pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
Return values:
HAL status

Definition at line 1308 of file stm32h7xx_hal_mdma.c.

References __HAL_MDMA_DISABLE, __MDMA_HandleTypeDef::ErrorCode, HAL_MDMA_ERROR_NO_XFER, HAL_MDMA_STATE_ABORT, HAL_MDMA_STATE_BUSY, and __MDMA_HandleTypeDef::State.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_IRQHandler(), and JPEG_DMA_ContinueProcess().

HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest ( MDMA_HandleTypeDef * hmdma )

Generate an MDMA SW request trigger to activate the request on the given Channel.

Parameters:
hmdma,: pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Stream.
Return values:
HAL status

Definition at line 1484 of file stm32h7xx_hal_mdma.c.

References __MDMA_HandleTypeDef::ErrorCode, HAL_MDMA_ERROR_BUSY, HAL_MDMA_ERROR_NO_XFER, and __MDMA_HandleTypeDef::Instance.

void HAL_MDMA_IRQHandler ( MDMA_HandleTypeDef * hmdma )

Handles MDMA interrupt request.

Parameters:
hmdma,: pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Stream.
Return values:
None

Definition at line 1519 of file stm32h7xx_hal_mdma.c.

References __HAL_MDMA_CLEAR_FLAG, __HAL_MDMA_DISABLE, __HAL_MDMA_DISABLE_IT, __HAL_MDMA_GET_FLAG, __HAL_MDMA_GET_IT_SOURCE, __MDMA_HandleTypeDef::ErrorCode, HAL_MDMA_CHANNEL_SIZE, HAL_MDMA_ERROR_ALIGNMENT, HAL_MDMA_ERROR_BLOCK_SIZE, HAL_MDMA_ERROR_LINKED_LIST, HAL_MDMA_ERROR_MASK_DATA, HAL_MDMA_ERROR_NONE, HAL_MDMA_ERROR_READ_XFER, HAL_MDMA_ERROR_WRITE_XFER, HAL_MDMA_STATE_ABORT, HAL_MDMA_STATE_ERROR, HAL_MDMA_STATE_READY, __MDMA_HandleTypeDef::Instance, MDMA_FLAG_BFTC, MDMA_FLAG_BRT, MDMA_FLAG_BT, MDMA_FLAG_CTC, MDMA_FLAG_TE, MDMA_IT_BFTC, MDMA_IT_BRT, MDMA_IT_BT, MDMA_IT_CTC, MDMA_IT_TE, __MDMA_HandleTypeDef::State, __MDMA_HandleTypeDef::XferAbortCallback, __MDMA_HandleTypeDef::XferBlockCpltCallback, __MDMA_HandleTypeDef::XferBufferCpltCallback, __MDMA_HandleTypeDef::XferCpltCallback, __MDMA_HandleTypeDef::XferErrorCallback, and __MDMA_HandleTypeDef::XferRepeatBlockCpltCallback.

HAL_StatusTypeDef HAL_MDMA_PollForTransfer | ( | MDMA_HandleTypeDef * | hmdma,
 |  | uint32_t | CompleteLevel,
 |  | uint32_t | Timeout
 | ) |  |

Polling for transfer complete.

Parameters:
hmdma,: pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Channel.
CompleteLevel,: Specifies the MDMA level complete.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 1341 of file stm32h7xx_hal_mdma.c.

References __HAL_MDMA_CLEAR_FLAG, __HAL_MDMA_GET_FLAG, assert_param, __MDMA_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_MDMA_Abort(), HAL_MDMA_BLOCK_TRANSFER, HAL_MDMA_BUFFER_TRANSFER, HAL_MDMA_ERROR_ALIGNMENT, HAL_MDMA_ERROR_BLOCK_SIZE, HAL_MDMA_ERROR_LINKED_LIST, HAL_MDMA_ERROR_MASK_DATA, HAL_MDMA_ERROR_NO_XFER, HAL_MDMA_ERROR_READ_XFER, HAL_MDMA_ERROR_TIMEOUT, HAL_MDMA_ERROR_WRITE_XFER, HAL_MDMA_FULL_TRANSFER, HAL_MDMA_REPEAT_BLOCK_TRANSFER, HAL_MDMA_STATE_BUSY, HAL_MDMA_STATE_READY, __MDMA_HandleTypeDef::Instance, IS_MDMA_LEVEL_COMPLETE, MDMA_FLAG_BFTC, MDMA_FLAG_BRT, MDMA_FLAG_BT, MDMA_FLAG_CTC, MDMA_FLAG_TE, and __MDMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MDMA_Start | ( | MDMA_HandleTypeDef * | hmdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | BlockDataLength,
 |  | uint32_t | BlockCount
 | ) |  |

Starts the MDMA Transfer.

Parameters:
hmdma | : pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Stream.
SrcAddress | : The source memory Buffer address
DstAddress | : The destination memory Buffer address
BlockDataLength | : The length of a block transfer in bytes
BlockCount | : The number of a blocks to be transfer
Return values:
HAL status

Definition at line 1098 of file stm32h7xx_hal_mdma.c.

References __HAL_MDMA_DISABLE, __HAL_MDMA_ENABLE, assert_param, __MDMA_HandleTypeDef::ErrorCode, HAL_MDMA_ERROR_NONE, HAL_MDMA_STATE_BUSY, HAL_MDMA_STATE_READY, __MDMA_HandleTypeDef::Init, __MDMA_HandleTypeDef::Instance, IS_MDMA_BLOCK_COUNT, IS_MDMA_TRANSFER_LENGTH, MDMA_REQUEST_SW, MDMA_SetConfig(), MDMA_InitTypeDef::Request, and __MDMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MDMA_Start_IT | ( | MDMA_HandleTypeDef * | hmdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | BlockDataLength,
 |  | uint32_t | BlockCount
 | ) |  |

Starts the MDMA Transfer with interrupts enabled.

Parameters:
hmdma | : pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Stream.
SrcAddress | : The source memory Buffer address
DstAddress | : The destination memory Buffer address
BlockDataLength | : The length of a block transfer in bytes
BlockCount | : The number of a blocks to be transfer
Return values:
HAL status

Definition at line 1160 of file stm32h7xx_hal_mdma.c.

References __HAL_MDMA_DISABLE, __HAL_MDMA_ENABLE, __HAL_MDMA_ENABLE_IT, assert_param, __MDMA_HandleTypeDef::ErrorCode, HAL_MDMA_ERROR_NONE, HAL_MDMA_STATE_BUSY, HAL_MDMA_STATE_READY, __MDMA_HandleTypeDef::Init, __MDMA_HandleTypeDef::Instance, IS_MDMA_BLOCK_COUNT, IS_MDMA_TRANSFER_LENGTH, MDMA_IT_BFTC, MDMA_IT_BRT, MDMA_IT_BT, MDMA_IT_CTC, MDMA_IT_TE, MDMA_REQUEST_SW, MDMA_SetConfig(), MDMA_InitTypeDef::Request, __MDMA_HandleTypeDef::State, __MDMA_HandleTypeDef::XferBlockCpltCallback, __MDMA_HandleTypeDef::XferBufferCpltCallback, and __MDMA_HandleTypeDef::XferRepeatBlockCpltCallback.

Referenced by HAL_JPEG_Resume(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), HAL_SDRAM_Read_DMA(), HAL_SDRAM_Write_DMA(), HAL_SRAM_Read_DMA(), HAL_SRAM_Write_DMA(), JPEG_DMA_StartProcess(), JPEG_MDMAInCpltCallback(), and JPEG_MDMAOutCpltCallback().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
MDMA Exported Functions

Peripheral State functions. More...

Functions

HAL_MDMA_StateTypeDef | HAL_MDMA_GetState (MDMA_HandleTypeDef *hmdma)
Returns the MDMA state.
uint32_t | HAL_MDMA_GetError (MDMA_HandleTypeDef *hmdma)
Return the MDMA error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                    ##### State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the MDMA state
      (+) Get error code

Function Documentation

uint32_t HAL_MDMA_GetError ( MDMA_HandleTypeDef * hmdma )

Return the MDMA error code.

Parameters:
hmdma : pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Stream.
Return values:
MDMA Error Code

Definition at line 1749 of file stm32h7xx_hal_mdma.c.

References __MDMA_HandleTypeDef::ErrorCode.

HAL_MDMA_StateTypeDef HAL_MDMA_GetState ( MDMA_HandleTypeDef * hmdma )

Returns the MDMA state.

Parameters:
hmdma,: pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified MDMA Stream.
Return values:
HAL state

Definition at line 1738 of file stm32h7xx_hal_mdma.c.

References __MDMA_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA Private Types

MDMA Private Types
MDMA
Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA Private Defines

MDMA Private Defines
MDMA
Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA Private Variables

MDMA Private Variables
MDMA
Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA Private Constants

Defines
MDMA Private Constants
MDMA

Defines

#define | HAL_TIMEOUT_MDMA_ABORT ((uint32_t)5U) /* 5 ms */
#define | HAL_MDMA_CHANNEL_SIZE ((uint32_t)0x40U) /* an MDMA instance channel size is 64 byte */

Define Documentation

#define HAL_MDMA_CHANNEL_SIZE ((uint32_t)0x40U) /* an MDMA instance channel size is 64 byte */

Definition at line 188 of file stm32h7xx_hal_mdma.c.

Referenced by HAL_MDMA_IRQHandler().

#define HAL_TIMEOUT_MDMA_ABORT ((uint32_t)5U) /* 5 ms */

Definition at line 187 of file stm32h7xx_hal_mdma.c.

Referenced by HAL_MDMA_Abort(), and HAL_MDMA_Init().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA Private Macros

Defines
MDMA Private Macros
MDMA

Defines

#define | IS_MDMA_LEVEL_COMPLETE(__LEVEL__)
#define | IS_MDMA_PRIORITY(__PRIORITY__)
#define | IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__)
#define | IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_END_DATA))
#define | IS_MDMA_SOURCE_INC(__INC__)
#define | IS_MDMA_DESTINATION_INC(__INC__)
#define | IS_MDMA_SOURCE_DATASIZE(__SIZE__)
#define | IS_MDMA_DESTINATION_DATASIZE(__SIZE__)
#define | IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__)
#define | IS_MDMA_SOURCE_BURST(__BURST__)
#define | IS_MDMA_DESTINATION_BURST(__BURST__)
#define | IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__)
#define | IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001) && ((__LENGTH__) < 0x000000FF))
#define | IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0 ) && ((__COUNT__) <= 4096))
#define | IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0) && ((SIZE) <= 65536))
#define | IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536))

Define Documentation

#define IS_MDMA_BLOCK_ADDR_OFFSET ( __BLOCK_ADD_OFFSET__ ) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536))

Definition at line 814 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_BLOCK_COUNT ( __COUNT__ ) (((__COUNT__) > 0 ) && ((__COUNT__) <= 4096))

Definition at line 810 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode(), HAL_MDMA_Start(), and HAL_MDMA_Start_IT().

#define IS_MDMA_BUFFER_TRANSFER_LENGTH ( __LENGTH__ ) (((__LENGTH__) >= 0x00000001) && ((__LENGTH__) < 0x000000FF))

Definition at line 808 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_DATA_ALIGNMENT ( __ALIGNMENT__ )
Value:
(((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE )    || \
                                                 ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT )         || \
                                                 ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED )  || \
                                                 ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT))

Definition at line 778 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_DESTINATION_BURST ( __BURST__ )
Value:
(((__BURST__) == MDMA_DEST_BURST_SINGLE ) || \
                                              ((__BURST__) == MDMA_DEST_BURST_2BEATS ) || \
                                              ((__BURST__) == MDMA_DEST_BURST_4BEATS ) || \
                                              ((__BURST__) == MDMA_DEST_BURST_8BEATS)  || \
                                              ((__BURST__) == MDMA_DEST_BURST_16BEATS) || \
                                              ((__BURST__) == MDMA_DEST_BURST_32BEATS) || \
                                              ((__BURST__) == MDMA_DEST_BURST_64BEATS) || \
                                              ((__BURST__) == MDMA_DEST_BURST_128BEATS))

Definition at line 794 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_DESTINATION_DATASIZE ( __SIZE__ )
Value:
(((__SIZE__) == MDMA_DEST_DATASIZE_BYTE )     || \
                                                ((__SIZE__) == MDMA_DEST_DATASIZE_HALFWORD ) || \
                                                ((__SIZE__) == MDMA_DEST_DATASIZE_WORD )     || \
                                                ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD))

Definition at line 773 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_DESTINATION_INC ( __INC__ )
Value:
(((__INC__) == MDMA_DEST_INC_DISABLE )   || \
                                          ((__INC__) == MDMA_DEST_INC_BYTE )      || \
                                          ((__INC__) == MDMA_DEST_INC_HALFWORD )  || \
                                          ((__INC__) == MDMA_DEST_INC_WORD )      || \
                                          ((__INC__) == MDMA_DEST_INC_DOUBLEWORD) || \
                                          ((__INC__) == MDMA_DEST_DEC_BYTE)       || \
                                          ((__INC__) == MDMA_DEST_DEC_HALFWORD)   || \
                                          ((__INC__) == MDMA_DEST_DEC_WORD)       || \
                                          ((__INC__) == MDMA_DEST_DEC_DOUBLEWORD))

Definition at line 758 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_ENDIANNESS_MODE ( __ENDIANNESS__ )
Value:
(((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE )        || \
                                              ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE)     || \
                                              ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \
                                              ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE))

Definition at line 740 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_LEVEL_COMPLETE ( __LEVEL__ )
Value:
(((__LEVEL__) == HAL_MDMA_FULL_TRANSFER )  || \
                                           ((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| \
                                           ((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || \
                                           ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER ))

Definition at line 729 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_PollForTransfer().

#define IS_MDMA_PRIORITY ( __PRIORITY__ )
Value:
(((__PRIORITY__) == MDMA_PRIORITY_LOW )  || \
                                       ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \
                                       ((__PRIORITY__) == MDMA_PRIORITY_HIGH)   || \
                                       ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH))

Definition at line 735 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_REQUEST ( __REQUEST__ ) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_END_DATA))

Definition at line 746 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_SOURCE_BURST ( __BURST__ )
Value:
(((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \
                                         ((__BURST__) == MDMA_SOURCE_BURST_2BEATS ) || \
                                         ((__BURST__) == MDMA_SOURCE_BURST_4BEATS ) || \
                                         ((__BURST__) == MDMA_SOURCE_BURST_8BEATS)  || \
                                         ((__BURST__) == MDMA_SOURCE_BURST_16BEATS) || \
                                         ((__BURST__) == MDMA_SOURCE_BURST_32BEATS) || \
                                         ((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || \
                                         ((__BURST__) == MDMA_SOURCE_BURST_128BEATS))

Definition at line 784 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_SOURCE_DATASIZE ( __SIZE__ )
Value:
(((__SIZE__) == MDMA_SRC_DATASIZE_BYTE )     || \
                                           ((__SIZE__) == MDMA_SRC_DATASIZE_HALFWORD ) || \
                                           ((__SIZE__) == MDMA_SRC_DATASIZE_WORD )     || \
                                           ((__SIZE__) == MDMA_SRC_DATASIZE_DOUBLEWORD))

Definition at line 768 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_SOURCE_INC ( __INC__ )
Value:
(((__INC__) == MDMA_SRC_INC_DISABLE )   || \
                                     ((__INC__) == MDMA_SRC_INC_BYTE )      || \
                                     ((__INC__) == MDMA_SRC_INC_HALFWORD )  || \
                                     ((__INC__) == MDMA_SRC_INC_WORD )      || \
                                     ((__INC__) == MDMA_SRC_INC_DOUBLEWORD) || \
                                     ((__INC__) == MDMA_SRC_DEC_BYTE)       || \
                                     ((__INC__) == MDMA_SRC_DEC_HALFWORD)   || \
                                     ((__INC__) == MDMA_SRC_DEC_WORD)       || \
                                     ((__INC__) == MDMA_SRC_DEC_DOUBLEWORD))

Definition at line 748 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

#define IS_MDMA_TRANSFER_LENGTH ( SIZE ) (((SIZE) > 0) && ((SIZE) <= 65536))

Definition at line 812 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_LinkedList_CreateNode(), HAL_MDMA_Start(), and HAL_MDMA_Start_IT().

#define IS_MDMA_TRANSFER_TRIGGER_MODE ( __MODE__ )
Value:
(((__MODE__) == MDMA_BUFFER_TRANSFER )      || \
                                         ((__MODE__) == MDMA_BLOCK_TRANSFER )        || \
                                         ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \
                                         ((__MODE__) == MDMA_FULL_TRANSFER))

Definition at line 803 of file stm32h7xx_hal_mdma.h.

Referenced by HAL_MDMA_Init(), and HAL_MDMA_LinkedList_CreateNode().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA Private Functions Prototypes

Functions
MDMA Private Functions Prototypes
MDMA

Functions

static void MDMA_Init (MDMA_HandleTypeDef *hmdma)

Function Documentation

static void MDMA_Init ( MDMA_HandleTypeDef * hmdma ) [static]

Definition at line 1822 of file stm32h7xx_hal_mdma.c.

References MDMA_InitTypeDef::BufferTransferLength, MDMA_InitTypeDef::DestBlockAddressOffset, MDMA_InitTypeDef::DestDataSize, MDMA_InitTypeDef::DestinationInc, MDMA_InitTypeDef::Endianness, __MDMA_HandleTypeDef::Init, __MDMA_HandleTypeDef::Instance, MDMA_REQUEST_SW, MDMA_InitTypeDef::Priority, MDMA_InitTypeDef::Request, MDMA_InitTypeDef::SourceBlockAddressOffset, MDMA_InitTypeDef::SourceBurst, MDMA_InitTypeDef::SourceInc, and MDMA_InitTypeDef::TransferTriggerMode.

Referenced by HAL_MDMA_Init().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MDMA Private Functions

MDMA Private Functions
MDMA
Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MMC Private Functions

Functions
MMC Private Functions
MMC | MMC Exported Functions

Functions

static uint32_t | MMC_InitCard (MMC_HandleTypeDef *hmmc)
Initializes the mmc card.
static uint32_t | MMC_PowerON (MMC_HandleTypeDef *hmmc)
Enquires cards about their operating voltage and configures clock controls and stores MMC information that will be needed in future in the MMC handle.
static uint32_t | MMC_SendStatus (MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
Returns the current card's status.
static HAL_StatusTypeDef | MMC_PowerOFF (MMC_HandleTypeDef *hmmc)
Turns the SDMMC output signals off.
static HAL_StatusTypeDef | MMC_Write_IT (MMC_HandleTypeDef *hmmc)
Wrap up writing in non-blocking mode.
static HAL_StatusTypeDef | MMC_Read_IT (MMC_HandleTypeDef *hmmc)
Wrap up reading in non-blocking mode.
static HAL_StatusTypeDef | MMC_ReadExtCSD (MMC_HandleTypeDef *hmmc, uint32_t *pBlockNbr, uint32_t Timeout)
Reads extended CSD register to get the sectors number of the device.
__weak void | HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback (MMC_HandleTypeDef *hmmc)
Read DMA Buffer 0 Transfer completed callbacks.
__weak void | HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback (MMC_HandleTypeDef *hmmc)
Read DMA Buffer 1 Transfer completed callbacks.
__weak void | HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback (MMC_HandleTypeDef *hmmc)
Write DMA Buffer 0 Transfer completed callbacks.
__weak void | HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback (MMC_HandleTypeDef *hmmc)
Write DMA Buffer 1 Transfer completed callbacks.

Function Documentation

__weak void HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback ( MMC_HandleTypeDef * hmmc )

Read DMA Buffer 0 Transfer completed callbacks.

Parameters:
hmmc,: MMC handle
Return values:
None

Definition at line 2367 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_IRQHandler().

__weak void HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback ( MMC_HandleTypeDef * hmmc )

Read DMA Buffer 1 Transfer completed callbacks.

Parameters:
hmmc,: MMC handle
Return values:
None

Definition at line 2382 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_IRQHandler().

__weak void HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback ( MMC_HandleTypeDef * hmmc )

Write DMA Buffer 0 Transfer completed callbacks.

Parameters:
hmmc,: MMC handle
Return values:
None

Definition at line 2397 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_IRQHandler().

__weak void HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback ( MMC_HandleTypeDef * hmmc )

Write DMA Buffer 1 Transfer completed callbacks.

Parameters:
hmmc,: MMC handle
Return values:
None

Definition at line 2412 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_IRQHandler().

static uint32_t MMC_InitCard ( MMC_HandleTypeDef * hmmc ) [static]

Initializes the mmc card.

Parameters:
hmmc,: Pointer to MMC handle
Return values:
MMC Card error state

Definition at line 2026 of file stm32h7xx_hal_mmc.c.

References MMC_HandleTypeDef::CID, HAL_MMC_CardInfoTypeDef::Class, MMC_HandleTypeDef::CSD, MMC_HandleTypeDef::ErrorCode, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE, HAL_MMC_GetCardCSD(), MMC_HandleTypeDef::Init, __MDMA_HandleTypeDef::Init, MMC_HandleTypeDef::Instance, MMC_InitTypeDef, MMC_HandleTypeDef::MmcCard, and HAL_MMC_CardInfoTypeDef::RelCardAdd.

Referenced by HAL_MMC_InitCard().

static HAL_StatusTypeDef MMC_PowerOFF ( MMC_HandleTypeDef * hmmc ) [static]

Turns the SDMMC output signals off.

Parameters:
hmmc,: Pointer to MMC handle
Return values:
HAL status

Definition at line 2173 of file stm32h7xx_hal_mmc.c.

References MMC_HandleTypeDef::Instance.

Referenced by HAL_MMC_DeInit().

static uint32_t MMC_PowerON ( MMC_HandleTypeDef * hmmc ) [static]

Enquires cards about their operating voltage and configures clock controls and stores MMC information that will be needed in future in the MMC handle.

Parameters:
hmmc,: Pointer to MMC handle
Return values:
error state

Definition at line 2121 of file stm32h7xx_hal_mmc.c.

References HAL_MMC_CardInfoTypeDef::CardType, eMMC_HIGH_VOLTAGE_RANGE, HAL_MMC_ERROR_INVALID_VOLTRANGE, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_UNSUPPORTED_FEATURE, MMC_HandleTypeDef::Instance, MMC_HIGH_CAPACITY_CARD, MMC_LOW_CAPACITY_CARD, and MMC_HandleTypeDef::MmcCard.

Referenced by HAL_MMC_InitCard().

static HAL_StatusTypeDef MMC_Read_IT ( MMC_HandleTypeDef * hmmc ) [static]

Wrap up reading in non-blocking mode.

Parameters:
hmmc,: pointer to a MMC_HandleTypeDef structure that contains the configuration information.
Return values:
HAL status

Definition at line 2320 of file stm32h7xx_hal_mmc.c.

References MMC_HandleTypeDef::Instance, and MMC_HandleTypeDef::pRxBuffPtr.

Referenced by HAL_MMC_IRQHandler().

HAL_StatusTypeDef MMC_ReadExtCSD | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint32_t * | pBlockNbr,
 |  | uint32_t | Timeout
 | ) |  | [static]

Reads extended CSD register to get the sectors number of the device.

Parameters:
hmmc,: Pointer to MMC handle
pBlockNbr,: Pointer to the read buffer
Timeout,: Specify timeout value
Return values:
HAL status

Definition at line 2218 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_GET_FLAG, BLOCKSIZE, MMC_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_GetTick(), HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_TIMEOUT, HAL_MMC_STATE_READY, MMC_HandleTypeDef::Instance, MMC_HandleTypeDef::MmcCard, HAL_MMC_CardInfoTypeDef::RelCardAdd, and MMC_HandleTypeDef::State.

Referenced by HAL_MMC_GetCardCSD().

static uint32_t MMC_SendStatus | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint32_t * | pCardStatus
 | ) |  | [static]

Returns the current card's status.

Parameters:
hmmc,: pointer to MMC handle
pCardStatus,: pointer to the buffer that will contain the MMC card status (Card Status register)
Return values:
error state

Definition at line 2189 of file stm32h7xx_hal_mmc.c.

References HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_PARAM, MMC_HandleTypeDef::Instance, MMC_HandleTypeDef::MmcCard, and HAL_MMC_CardInfoTypeDef::RelCardAdd.

Referenced by HAL_MMC_GetCardState().

static HAL_StatusTypeDef MMC_Write_IT ( MMC_HandleTypeDef * hmmc ) [static]

Wrap up writing in non-blocking mode.

Parameters:
hmmc,: pointer to a MMC_HandleTypeDef structure that contains the configuration information.
Return values:
HAL status

Definition at line 2344 of file stm32h7xx_hal_mmc.c.

References MMC_HandleTypeDef::Instance, and MMC_HandleTypeDef::pTxBuffPtr.

Referenced by HAL_MMC_IRQHandler().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MMC State enumeration structure

Enumerations
MMC State enumeration structure
MMC Exported Types

Enumerations

enum HAL_MMC_StateTypeDef {
HAL_MMC_STATE_RESET = ((uint32_t)0x00000000U), HAL_MMC_STATE_READY = ((uint32_t)0x00000001U), HAL_MMC_STATE_TIMEOUT = ((uint32_t)0x00000002U), HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U),
HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU)
}

Enumeration Type Documentation

enum HAL_MMC_StateTypeDef
Enumerator:
HAL_MMC_STATE_RESET

MMC not yet initialized or disabled

HAL_MMC_STATE_READY

MMC initialized and ready for use

HAL_MMC_STATE_TIMEOUT

MMC Timeout state

HAL_MMC_STATE_BUSY

MMC process ongoing

HAL_MMC_STATE_PROGRAMMING

MMC Programming State

HAL_MMC_STATE_RECEIVING

MMC Receinving State

HAL_MMC_STATE_TRANSFER

MMC Transfert State

HAL_MMC_STATE_ERROR

MMC is in error state

Definition at line 65 of file stm32h7xx_hal_mmc.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MMC Card State enumeration structure

Enumerations
MMC Card State enumeration structure
MMC Exported Types

Enumerations

enum HAL_MMC_CardStateTypedef {
HAL_MMC_CARD_READY = ((uint32_t)0x00000001U), HAL_MMC_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), HAL_MMC_CARD_STANDBY = ((uint32_t)0x00000003U), HAL_MMC_CARD_TRANSFER = ((uint32_t)0x00000004U),
HAL_MMC_CARD_SENDING = ((uint32_t)0x00000005U), HAL_MMC_CARD_RECEIVING = ((uint32_t)0x00000006U), HAL_MMC_CARD_PROGRAMMING = ((uint32_t)0x00000007U), HAL_MMC_CARD_DISCONNECTED = ((uint32_t)0x00000008U),
HAL_MMC_CARD_ERROR = ((uint32_t)0x000000FFU)
}

Enumeration Type Documentation

enum HAL_MMC_CardStateTypedef
Enumerator:
HAL_MMC_CARD_READY

Card state is ready

HAL_MMC_CARD_IDENTIFICATION

Card is in identification state

HAL_MMC_CARD_STANDBY

Card is in standby state

HAL_MMC_CARD_TRANSFER

Card is in transfer state

HAL_MMC_CARD_SENDING

Card is sending an operation

HAL_MMC_CARD_RECEIVING

Card is receiving operation information

HAL_MMC_CARD_PROGRAMMING

Card is in programming state

HAL_MMC_CARD_DISCONNECTED

Card is disconnected

HAL_MMC_CARD_ERROR

Card response Error

Definition at line 83 of file stm32h7xx_hal_mmc.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MMC Handle Structure definition

Data Structures | Defines
MMC Handle Structure definition
MMC Exported Types

Data Structures

struct | HAL_MMC_CardInfoTypeDef
MMC Card Information Structure definition. More...
struct | MMC_HandleTypeDef
MMC handle Structure definition. More...

Defines

#define | MMC_InitTypeDef SDMMC_InitTypeDef
#define | MMC_TypeDef SDMMC_TypeDef

Define Documentation

#define MMC_InitTypeDef SDMMC_InitTypeDef

Definition at line 102 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ConfigWideBusOperation(), HAL_MMC_InitCard(), and MMC_InitCard().

#define MMC_TypeDef SDMMC_TypeDef

Definition at line 103 of file stm32h7xx_hal_mmc.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HAL_MMC_CardInfoTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_MMC_CardInfoTypeDef Struct Reference
MMC Handle Structure definition

MMC Card Information Structure definition. More...

#include <stm32h7xx_hal_mmc.h>

Data Fields

uint32_t | CardType
uint32_t | Class
uint32_t | RelCardAdd
uint32_t | BlockNbr
uint32_t | BlockSize
uint32_t | LogBlockNbr
uint32_t | LogBlockSize

Detailed Description

MMC Card Information Structure definition.

Definition at line 108 of file stm32h7xx_hal_mmc.h.

Field Documentation

uint32_t HAL_MMC_CardInfoTypeDef::BlockNbr

Specifies the Card Capacity in blocks

Definition at line 116 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD(), and HAL_MMC_GetCardInfo().

uint32_t HAL_MMC_CardInfoTypeDef::BlockSize

Specifies one block size in bytes

Definition at line 118 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD(), and HAL_MMC_GetCardInfo().

uint32_t HAL_MMC_CardInfoTypeDef::CardType

Specifies the card Type

Definition at line 110 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Erase(), HAL_MMC_GetCardCSD(), HAL_MMC_GetCardInfo(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), HAL_MMCEx_WriteBlocksDMAMultiBuffer(), and MMC_PowerON().

uint32_t HAL_MMC_CardInfoTypeDef::Class

Specifies the class of the card class

Definition at line 112 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Erase(), HAL_MMC_GetCardInfo(), and MMC_InitCard().

uint32_t HAL_MMC_CardInfoTypeDef::LogBlockNbr

Specifies the Card logical Capacity in blocks

Definition at line 120 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Erase(), HAL_MMC_GetCardCSD(), HAL_MMC_GetCardInfo(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), and HAL_MMCEx_WriteBlocksDMAMultiBuffer().

uint32_t HAL_MMC_CardInfoTypeDef::LogBlockSize

Specifies logical block size in bytes

Definition at line 122 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD(), and HAL_MMC_GetCardInfo().

uint32_t HAL_MMC_CardInfoTypeDef::RelCardAdd

Specifies the Relative Card Address

Definition at line 114 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ConfigWideBusOperation(), HAL_MMC_GetCardInfo(), MMC_InitCard(), MMC_ReadExtCSD(), and MMC_SendStatus().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_mmc.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MMC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
MMC_HandleTypeDef Struct Reference
MMC Handle Structure definition

MMC handle Structure definition. More...

#include <stm32h7xx_hal_mmc.h>

Data Fields

MMC_TypeDef * Instance
MMC_InitTypeDef Init
HAL_LockTypeDef | Lock
uint32_t * | pTxBuffPtr
uint32_t | TxXferSize
uint32_t * | pRxBuffPtr
uint32_t | RxXferSize
__IO uint32_t | Context
__IO HAL_MMC_StateTypeDef | State
__IO uint32_t | ErrorCode
HAL_MMC_CardInfoTypeDef MmcCard
uint32_t | CSD [4]
uint32_t | CID [4]

Detailed Description

MMC handle Structure definition.

Definition at line 130 of file stm32h7xx_hal_mmc.h.

Field Documentation

uint32_t MMC_HandleTypeDef::CID[4]

MMC card identification number table

Definition at line 156 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID(), and MMC_InitCard().

__IO uint32_t MMC_HandleTypeDef::Context

MMC transfer context

Definition at line 146 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Init(), HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), and HAL_MMCEx_WriteBlocksDMAMultiBuffer().

uint32_t MMC_HandleTypeDef::CSD[4]

MMC card specific data table

Definition at line 154 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD(), and MMC_InitCard().

__IO uint32_t MMC_HandleTypeDef::ErrorCode

MMC Card Error codes

Definition at line 150 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Abort(), HAL_MMC_Abort_IT(), HAL_MMC_ConfigWideBusOperation(), HAL_MMC_DeInit(), HAL_MMC_Erase(), HAL_MMC_GetCardState(), HAL_MMC_GetError(), HAL_MMC_Init(), HAL_MMC_InitCard(), HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), HAL_MMCEx_WriteBlocksDMAMultiBuffer(), MMC_InitCard(), and MMC_ReadExtCSD().

MMC_InitTypeDef MMC_HandleTypeDef::Init

MMC required parameters

Definition at line 134 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ConfigWideBusOperation(), HAL_MMC_Init(), and MMC_InitCard().

MMC_TypeDef* MMC_HandleTypeDef::Instance

MMC registers base address

Definition at line 132 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Abort(), HAL_MMC_Abort_IT(), HAL_MMC_ConfigWideBusOperation(), HAL_MMC_DeInit(), HAL_MMC_Erase(), HAL_MMC_GetCardState(), HAL_MMC_Init(), HAL_MMC_InitCard(), HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ChangeDMABuffer(), HAL_MMCEx_ConfigDMAMultiBuffer(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), HAL_MMCEx_WriteBlocksDMAMultiBuffer(), MMC_InitCard(), MMC_PowerOFF(), MMC_PowerON(), MMC_Read_IT(), MMC_ReadExtCSD(), MMC_SendStatus(), and MMC_Write_IT().

HAL_LockTypeDef MMC_HandleTypeDef::Lock

MMC locking object

Definition at line 136 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Init().

HAL_MMC_CardInfoTypeDef MMC_HandleTypeDef::MmcCard

MMC Card information

Definition at line 152 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ConfigWideBusOperation(), HAL_MMC_Erase(), HAL_MMC_GetCardCSD(), HAL_MMC_GetCardInfo(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), HAL_MMCEx_WriteBlocksDMAMultiBuffer(), MMC_InitCard(), MMC_PowerON(), MMC_ReadExtCSD(), and MMC_SendStatus().

uint32_t* MMC_HandleTypeDef::pRxBuffPtr

Pointer to MMC Rx transfer Buffer

Definition at line 142 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), and MMC_Read_IT().

uint32_t* MMC_HandleTypeDef::pTxBuffPtr

Pointer to MMC Tx transfer Buffer

Definition at line 138 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), and MMC_Write_IT().

uint32_t MMC_HandleTypeDef::RxXferSize

MMC Rx Transfer size

Definition at line 144 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ReadBlocks_DMA(), and HAL_MMC_ReadBlocks_IT().

__IO HAL_MMC_StateTypeDef MMC_HandleTypeDef::State

MMC card State

Definition at line 148 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Abort(), HAL_MMC_Abort_IT(), HAL_MMC_ConfigWideBusOperation(), HAL_MMC_DeInit(), HAL_MMC_Erase(), HAL_MMC_GetState(), HAL_MMC_Init(), HAL_MMC_InitCard(), HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ConfigDMAMultiBuffer(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), HAL_MMCEx_WriteBlocksDMAMultiBuffer(), and MMC_ReadExtCSD().

uint32_t MMC_HandleTypeDef::TxXferSize

MMC Tx Transfer size

Definition at line 140 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_WriteBlocks_DMA(), and HAL_MMC_WriteBlocks_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_mmc.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HAL_MMC_CardCSDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_MMC_CardCSDTypeDef Struct Reference
Card Specific Data: CSD Register

#include <stm32h7xx_hal_mmc.h>

Data Fields

__IO uint8_t | CSDStruct
__IO uint8_t | SysSpecVersion
__IO uint8_t | Reserved1
__IO uint8_t | TAAC
__IO uint8_t | NSAC
__IO uint8_t | MaxBusClkFrec
__IO uint16_t | CardComdClasses
__IO uint8_t | RdBlockLen
__IO uint8_t | PartBlockRead
__IO uint8_t | WrBlockMisalign
__IO uint8_t | RdBlockMisalign
__IO uint8_t | DSRImpl
__IO uint8_t | Reserved2
__IO uint32_t | DeviceSize
__IO uint8_t | MaxRdCurrentVDDMin
__IO uint8_t | MaxRdCurrentVDDMax
__IO uint8_t | MaxWrCurrentVDDMin
__IO uint8_t | MaxWrCurrentVDDMax
__IO uint8_t | DeviceSizeMul
__IO uint8_t | EraseGrSize
__IO uint8_t | EraseGrMul
__IO uint8_t | WrProtectGrSize
__IO uint8_t | WrProtectGrEnable
__IO uint8_t | ManDeflECC
__IO uint8_t | WrSpeedFact
__IO uint8_t | MaxWrBlockLen
__IO uint8_t | WriteBlockPaPartial
__IO uint8_t | Reserved3
__IO uint8_t | ContentProtectAppli
__IO uint8_t | FileFormatGrouop
__IO uint8_t | CopyFlag
__IO uint8_t | PermWrProtect
__IO uint8_t | TempWrProtect
__IO uint8_t | FileFormat
__IO uint8_t | ECC
__IO uint8_t | CSD_CRC
__IO uint8_t | Reserved4

Detailed Description

Definition at line 168 of file stm32h7xx_hal_mmc.h.

Field Documentation

__IO uint16_t HAL_MMC_CardCSDTypeDef::CardComdClasses

Card command classes

Definition at line 176 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::ContentProtectAppli

Content protection application

Definition at line 198 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::CopyFlag

Copy flag (OTP)

Definition at line 200 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::CSD_CRC

CSD CRC

Definition at line 205 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::CSDStruct

CSD structure

Definition at line 170 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint32_t HAL_MMC_CardCSDTypeDef::DeviceSize

Device Size

Definition at line 183 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::DeviceSizeMul

Device size multiplier

Definition at line 188 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::DSRImpl

DSR implemented

Definition at line 181 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::ECC

ECC code

Definition at line 204 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::EraseGrMul

Erase group size multiplier

Definition at line 190 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::EraseGrSize

Erase group size

Definition at line 189 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::FileFormat

File format

Definition at line 203 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::FileFormatGrouop

File format group

Definition at line 199 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::ManDeflECC

Manufacturer default ECC

Definition at line 193 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::MaxBusClkFrec

Max. bus clock frequency

Definition at line 175 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::MaxRdCurrentVDDMax

Max. read current @ VDD max

Definition at line 185 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::MaxRdCurrentVDDMin

Max. read current @ VDD min

Definition at line 184 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::MaxWrBlockLen

Max. write data block length

Definition at line 195 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::MaxWrCurrentVDDMax

Max. write current @ VDD max

Definition at line 187 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::MaxWrCurrentVDDMin

Max. write current @ VDD min

Definition at line 186 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::NSAC

Data read access time 2 in CLK cycles

Definition at line 174 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::PartBlockRead

Partial blocks for read allowed

Definition at line 178 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::PermWrProtect

Permanent write protection

Definition at line 201 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::RdBlockLen

Max. read data block length

Definition at line 177 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::RdBlockMisalign

Read block misalignment

Definition at line 180 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::Reserved1

Reserved

Definition at line 172 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::Reserved2

Reserved

Definition at line 182 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::Reserved3

Reserved

Definition at line 197 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::Reserved4

Always 1

Definition at line 206 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::SysSpecVersion

System specification version

Definition at line 171 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::TAAC

Data read access time 1

Definition at line 173 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::TempWrProtect

Temporary write protection

Definition at line 202 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::WrBlockMisalign

Write block misalignment

Definition at line 179 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::WriteBlockPaPartial

Partial blocks for write allowed

Definition at line 196 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::WrProtectGrEnable

Write protect group enable

Definition at line 192 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::WrProtectGrSize

Write protect group size

Definition at line 191 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

__IO uint8_t HAL_MMC_CardCSDTypeDef::WrSpeedFact

Write speed factor

Definition at line 194 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_mmc.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HAL_MMC_CardCIDTypedef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_MMC_CardCIDTypedef Struct Reference
Card Identification Data: CID Register

#include <stm32h7xx_hal_mmc.h>

Data Fields

__IO uint8_t | ManufacturerID
__IO uint16_t | OEM_AppliID
__IO uint32_t | ProdName1
__IO uint8_t | ProdName2
__IO uint8_t | ProdRev
__IO uint32_t | ProdSN
__IO uint8_t | Reserved1
__IO uint16_t | ManufactDate
__IO uint8_t | CID_CRC
__IO uint8_t | Reserved2

Detailed Description

Definition at line 216 of file stm32h7xx_hal_mmc.h.

Field Documentation

__IO uint8_t HAL_MMC_CardCIDTypedef::CID_CRC

CID CRC

Definition at line 226 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID().

__IO uint16_t HAL_MMC_CardCIDTypedef::ManufactDate

Manufacturing Date

Definition at line 225 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID().

__IO uint8_t HAL_MMC_CardCIDTypedef::ManufacturerID

Manufacturer ID

Definition at line 218 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID().

__IO uint16_t HAL_MMC_CardCIDTypedef::OEM_AppliID

OEM/Application ID

Definition at line 219 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID().

__IO uint32_t HAL_MMC_CardCIDTypedef::ProdName1

Product Name part1

Definition at line 220 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID().

__IO uint8_t HAL_MMC_CardCIDTypedef::ProdName2

Product Name part2

Definition at line 221 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID().

__IO uint8_t HAL_MMC_CardCIDTypedef::ProdRev

Product Revision

Definition at line 222 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID().

__IO uint32_t HAL_MMC_CardCIDTypedef::ProdSN

Product Serial Number

Definition at line 223 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID().

__IO uint8_t HAL_MMC_CardCIDTypedef::Reserved1

Reserved1

Definition at line 224 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID().

__IO uint8_t HAL_MMC_CardCIDTypedef::Reserved2

Always 1

Definition at line 227 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCID().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_mmc.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MMC Error status enumeration Structure definition

Defines
MMC Error status enumeration Structure definition
Exported Constants

Defines

#define | HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE
#define | HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL
#define | HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL
#define | HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT
#define | HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT
#define | HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN
#define | HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN
#define | HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED
#define | HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR
#define | HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR
#define | HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM
#define | HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION
#define | HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED
#define | HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED
#define | HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD
#define | HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED
#define | HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR
#define | HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR
#define | HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN
#define | HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN
#define | HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE
#define | HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP
#define | HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED
#define | HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET
#define | HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR
#define | HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE
#define | HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE
#define | HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE
#define | HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER
#define | HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE
#define | HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY
#define | HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA
#define | HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT

Define Documentation

#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED

Misaligned address

Definition at line 255 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE

Error when addressed block is out of range

Definition at line 277 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Erase(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), and HAL_MMCEx_WriteBlocksDMAMultiBuffer().

#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR

Error in sequence of authentication

Definition at line 275 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM

An invalid selection for erase groups

Definition at line 259 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR

Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length

Definition at line 256 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY

Error when transfer process is busy

Definition at line 281 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ReadBlocks(), and HAL_MMC_WriteBlocks().

#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED

Command has been executed without using internal ECC

Definition at line 272 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED

Card internal ECC was applied but failed to correct the data

Definition at line 265 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR

Internal card controller error

Definition at line 266 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE

CID/CSD overwrite error

Definition at line 270 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL

Command response received (but CRC check failed)

Definition at line 249 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT

Command response timeout

Definition at line 251 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED

CRC check of the previous command failed

Definition at line 263 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL

Data block sent/received (CRC check failed)

Definition at line 250 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ReadBlocks(), and HAL_MMC_WriteBlocks().

#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT

Data timeout

Definition at line 252 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ReadBlocks(), and HAL_MMC_WriteBlocks().

#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA

Error while DMA transfer

Definition at line 282 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET

Erase sequence was cleared before executing because an out of erase sequence command was received

Definition at line 273 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR

An error in the sequence of erase command occurs

Definition at line 258 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR

General or unknown error

Definition at line 267 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD

Command is not legal for the card state

Definition at line 264 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE

Error in case of invalid voltage range

Definition at line 276 of file stm32h7xx_hal_mmc.h.

Referenced by MMC_PowerON().

#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED

Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card

Definition at line 261 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Erase().

#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE

No error

Definition at line 248 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Abort(), HAL_MMC_Abort_IT(), HAL_MMC_ConfigWideBusOperation(), HAL_MMC_DeInit(), HAL_MMC_Erase(), HAL_MMC_GetCardState(), HAL_MMC_InitCard(), HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), HAL_MMCEx_WriteBlocksDMAMultiBuffer(), MMC_InitCard(), MMC_PowerON(), MMC_ReadExtCSD(), and MMC_SendStatus().

#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER

the used parameter is not valid

Definition at line 279 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ConfigWideBusOperation(), HAL_MMC_Erase(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), and MMC_SendStatus().

#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE

Error when command request is not applicable

Definition at line 278 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ConfigWideBusOperation(), HAL_MMC_Erase(), and MMC_InitCard().

#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN

Receive FIFO overrun

Definition at line 254 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ReadBlocks().

#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN

The card could not sustain data reading in stream rmode

Definition at line 268 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN

The card could not sustain data programming in stream mode

Definition at line 269 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT

Timeout error

Definition at line 283 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ReadBlocks(), and MMC_ReadExtCSD().

#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN

Transmit FIFO underrun

Definition at line 253 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_WriteBlocks().

#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE

Error when feature is not insupported

Definition at line 280 of file stm32h7xx_hal_mmc.h.

Referenced by MMC_PowerON().

#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP

Only partial address space was erased

Definition at line 271 of file stm32h7xx_hal_mmc.h.

#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION

Attempt to program a write protect block

Definition at line 260 of file stm32h7xx_hal_mmc.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MMC context enumeration

Defines
MMC context enumeration
Exported Constants

Defines

#define | MMC_CONTEXT_NONE ((uint32_t)0x00000000U)
#define | MMC_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U)
#define | MMC_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U)
#define | MMC_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U)
#define | MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)
#define | MMC_CONTEXT_IT ((uint32_t)0x00000008U)
#define | MMC_CONTEXT_DMA ((uint32_t)0x00000080U)

Define Documentation

#define MMC_CONTEXT_DMA ((uint32_t)0x00000080U)

Process in DMA mode

Definition at line 298 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_WriteBlocks_DMA(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), and HAL_MMCEx_WriteBlocksDMAMultiBuffer().

#define MMC_CONTEXT_IT ((uint32_t)0x00000008U)

Process in Interrupt mode

Definition at line 297 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks_IT(), and HAL_MMC_WriteBlocks_IT().

#define MMC_CONTEXT_NONE ((uint32_t)0x00000000U)

None

Definition at line 292 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Init().

#define MMC_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U)

Read multiple blocks operation

Definition at line 294 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), and HAL_MMCEx_ReadBlocksDMAMultiBuffer().

#define MMC_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U)

Read single block operation

Definition at line 293 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), and HAL_MMC_ReadBlocks_IT().

#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)

Write multiple blocks operation

Definition at line 296 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_IRQHandler(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), and HAL_MMCEx_WriteBlocksDMAMultiBuffer().

#define MMC_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U)

Write single block operation

Definition at line 295 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_IRQHandler(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), and HAL_MMC_WriteBlocks_IT().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MMC Voltage mode

Defines
MMC Voltage mode
Exported Constants

Defines

#define | MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U
#define | MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U
#define | eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U
#define | eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U
#define | MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U

Define Documentation

#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U

for eMMC > 2Gb sector mode

Definition at line 313 of file stm32h7xx_hal_mmc.h.

#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U

for eMMC > 2Gb sector mode

Definition at line 312 of file stm32h7xx_hal_mmc.h.

Referenced by MMC_PowerON().

#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U

VALUE OF ARGUMENT

Definition at line 311 of file stm32h7xx_hal_mmc.h.

#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U

VALUE OF ARGUMENT

Definition at line 310 of file stm32h7xx_hal_mmc.h.

#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U

Definition at line 314 of file stm32h7xx_hal_mmc.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MMC Memory Cards

Defines
MMC Memory Cards
Exported Constants

Defines

#define | MMC_LOW_CAPACITY_CARD ((uint32_t)0x00000000U)
#define | MMC_HIGH_CAPACITY_CARD ((uint32_t)0x00000001U)

Define Documentation

#define MMC_HIGH_CAPACITY_CARD ((uint32_t)0x00000001U)

MMC Card Capacity >2Gbytes and <2Tbytes

Definition at line 323 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Erase(), HAL_MMC_GetCardCSD(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), HAL_MMCEx_WriteBlocksDMAMultiBuffer(), and MMC_PowerON().

#define MMC_LOW_CAPACITY_CARD ((uint32_t)0x00000000U)

MMC Card Capacity <=2Gbytes

Definition at line 322 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_GetCardCSD(), and MMC_PowerON().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Exported Constants

Modules | Defines
Exported Constants
MMC

Modules

MMC Error status enumeration Structure definition
MMC context enumeration
MMC Voltage mode
MMC Memory Cards

Defines

#define BLOCKSIZE ((uint32_t)512U)

Define Documentation

#define BLOCKSIZE ((uint32_t)512U)

Block size is 512 bytes

Definition at line 243 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), HAL_MMCEx_WriteBlocksDMAMultiBuffer(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), HAL_SDEx_WriteBlocksDMAMultiBuffer(), and MMC_ReadExtCSD().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MMC Exported Macros

Defines
MMC Exported Macros
MMC

macros to handle interrupts and specific clock configurations More...

Defines

#define | __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Enable the MMC device interrupt.
#define | __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Disable the MMC device interrupt.
#define | __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
Check whether the specified MMC flag is set or not.
#define | __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
Clear the MMC's pending flags.
#define | __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Check whether the specified MMC interrupt has occurred or not.
#define | __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Clear the MMC's interrupt pending bits.

Detailed Description

macros to handle interrupts and specific clock configurations

Define Documentation

#define __HAL_MMC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))

Clear the MMC's pending flags.

Parameters:
__HANDLE__,: MMC Handle
__FLAG__,: specifies the flag to clear. This parameter can be one or a combination of the following values:
  • SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
  • SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
  • SDMMC_FLAG_CTIMEOUT: Command response timeout
  • SDMMC_FLAG_DTIMEOUT: Data timeout
  • SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
  • SDMMC_FLAG_RXOVERR: Received FIFO overrun error
  • SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
  • SDMMC_FLAG_CMDSENT: Command sent (no response required)
  • SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
  • SDMMC_FLAG_DHOLD: Data transfer Hold
  • SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
  • SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
  • SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
  • SDMMC_FLAG_SDIOIT: SD I/O interrupt received
  • SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
  • SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
  • SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
  • SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
  • SDMMC_FLAG_IDMATE: IDMA transfer error
  • SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
Return values:
None

Definition at line 468 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Abort(), HAL_MMC_Abort_IT(), HAL_MMC_ConfigWideBusOperation(), HAL_MMC_Erase(), HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks(), HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), and MMC_ReadExtCSD().

#define __HAL_MMC_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))

Clear the MMC's interrupt pending bits.

Parameters:
__HANDLE__,: MMC Handle
__INTERRUPT__,: specifies the interrupt pending bit to clear. This parameter can be one or a combination of the following values:
  • SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDMMC_IT_CTIMEOUT: Command response timeout interrupt
  • SDMMC_IT_DTIMEOUT: Data timeout interrupt
  • SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
  • SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
  • SDMMC_IT_DHOLD: Data transfer Hold interrupt
  • SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
  • SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
  • SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
  • SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
  • SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
  • SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
  • SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
  • SDMMC_IT_IDMATE: IDMA transfer error interrupt
  • SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
Return values:
None

Definition at line 535 of file stm32h7xx_hal_mmc.h.

#define __HAL_MMC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))

Disable the MMC device interrupt.

Parameters:
__HANDLE__,: MMC Handle
__INTERRUPT__,: specifies the SDMMC interrupt sources to be disabled. This parameter can be one or a combination of the following values:
  • SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDMMC_IT_CTIMEOUT: Command response timeout interrupt
  • SDMMC_IT_DTIMEOUT: Data timeout interrupt
  • SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
  • SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
  • SDMMC_IT_DHOLD: Data transfer Hold interrupt
  • SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
  • SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  • SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  • SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
  • SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
  • SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
  • SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
  • SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
  • SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
  • SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
  • SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
  • SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
Return values:
None

Definition at line 401 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_Abort(), HAL_MMC_Abort_IT(), HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks_DMA(), and HAL_MMC_WriteBlocks_DMA().

#define __HAL_MMC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))

Enable the MMC device interrupt.

Parameters:
__HANDLE__,: MMC Handle
__INTERRUPT__,: specifies the SDMMC interrupt sources to be enabled. This parameter can be one or a combination of the following values:
  • SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDMMC_IT_CTIMEOUT: Command response timeout interrupt
  • SDMMC_IT_DTIMEOUT: Data timeout interrupt
  • SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
  • SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
  • SDMMC_IT_DHOLD: Data transfer Hold interrupt
  • SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
  • SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  • SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  • SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
  • SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
  • SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
  • SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
  • SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
  • SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
  • SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
  • SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
  • SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
Return values:
None

Definition at line 369 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_ReadBlocks_DMA(), HAL_MMC_ReadBlocks_IT(), HAL_MMC_WriteBlocks_DMA(), HAL_MMC_WriteBlocks_IT(), HAL_MMCEx_ReadBlocksDMAMultiBuffer(), and HAL_MMCEx_WriteBlocksDMAMultiBuffer().

#define __HAL_MMC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))

Check whether the specified MMC flag is set or not.

Parameters:
__HANDLE__,: MMC Handle
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
  • SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
  • SDMMC_FLAG_CTIMEOUT: Command response timeout
  • SDMMC_FLAG_DTIMEOUT: Data timeout
  • SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
  • SDMMC_FLAG_RXOVERR: Received FIFO overrun error
  • SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
  • SDMMC_FLAG_CMDSENT: Command sent (no response required)
  • SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
  • SDMMC_FLAG_DHOLD: Data transfer Hold
  • SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
  • SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
  • SDMMC_FLAG_CPSMACT: Command path state machine active
  • SDMMC_FLAG_DPSMACT: Data path state machine active
  • SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
  • SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
  • SDMMC_FLAG_TXFIFOF: Transmit FIFO full
  • SDMMC_FLAG_RXFIFOF: Receive FIFO full
  • SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
  • SDMMC_FLAG_RXFIFOE: Receive FIFO empty
  • SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
  • SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
  • SDMMC_FLAG_SDIOIT: SD I/O interrupt received
  • SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
  • SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
  • SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
  • SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
  • SDMMC_FLAG_IDMATE: IDMA transfer error
  • SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
Return values:
The new state of MMC FLAG (SET or RESET).

Definition at line 439 of file stm32h7xx_hal_mmc.h.

Referenced by HAL_MMC_IRQHandler(), HAL_MMC_ReadBlocks(), HAL_MMC_WriteBlocks(), and MMC_ReadExtCSD().

#define __HAL_MMC_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))

Check whether the specified MMC interrupt has occurred or not.

Parameters:
__HANDLE__,: MMC Handle
__INTERRUPT__,: specifies the SDMMC interrupt source to check. This parameter can be one of the following values:
  • SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDMMC_IT_CTIMEOUT: Command response timeout interrupt
  • SDMMC_IT_DTIMEOUT: Data timeout interrupt
  • SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
  • SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
  • SDMMC_IT_DHOLD: Data transfer Hold interrupt
  • SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
  • SDMMC_IT_DPSMACT: Data path state machine active interrupt
  • SDMMC_IT_CPSMACT: Command path state machine active interrupt
  • SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  • SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  • SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
  • SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
  • SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
  • SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
  • SDMMC_IT_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
  • SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
  • SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
  • SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
  • SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
  • SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
  • SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
  • SDMMC_IT_IDMATE: IDMA transfer error interrupt
  • SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
Return values:
The new state of MMC IT (SET or RESET).

Definition at line 506 of file stm32h7xx_hal_mmc.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
MMC Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_MMC_Init (MMC_HandleTypeDef *hmmc)
Initializes the MMC according to the specified parameters in the MMC_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_MMC_InitCard (MMC_HandleTypeDef *hmmc)
Initializes the MMC Card.
HAL_StatusTypeDef | HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc)
De-Initializes the MMC card.
__weak void | HAL_MMC_MspInit (MMC_HandleTypeDef *hmmc)
Initializes the MMC MSP.
__weak void | HAL_MMC_MspDeInit (MMC_HandleTypeDef *hmmc)
De-Initialize MMC MSP.

Detailed Description

Initialization and de-initialization functions.

  ==============================================================================
          ##### Initialization and de-initialization functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to initialize/de-initialize the MMC
    card device to be ready for use.

Function Documentation

HAL_StatusTypeDef HAL_MMC_DeInit ( MMC_HandleTypeDef * hmmc )

De-Initializes the MMC card.

Parameters:
hmmc,: Pointer to MMC handle
Return values:
HAL status

Definition at line 342 of file stm32h7xx_hal_mmc.c.

References assert_param, MMC_HandleTypeDef::ErrorCode, HAL_MMC_ERROR_NONE, HAL_MMC_MspDeInit(), HAL_MMC_STATE_BUSY, HAL_MMC_STATE_RESET, MMC_HandleTypeDef::Instance, MMC_PowerOFF(), and MMC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MMC_Init ( MMC_HandleTypeDef * hmmc )

Initializes the MMC according to the specified parameters in the MMC_HandleTypeDef and create the associated handle.

Parameters:
hmmc,: Pointer to the MMC handle
Return values:
HAL status

Definition at line 238 of file stm32h7xx_hal_mmc.c.

References assert_param, MMC_HandleTypeDef::Context, MMC_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_MMC_InitCard(), HAL_MMC_MspInit(), HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, HAL_MMC_STATE_RESET, MMC_HandleTypeDef::Init, MMC_HandleTypeDef::Instance, MMC_HandleTypeDef::Lock, MMC_CONTEXT_NONE, and MMC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MMC_InitCard ( MMC_HandleTypeDef * hmmc )

Initializes the MMC Card.

Parameters:
hmmc,: Pointer to MMC handle
Note:
This function initializes the MMC card. It could be used when a card re-initialization is needed.
Return values:
HAL status

Definition at line 289 of file stm32h7xx_hal_mmc.c.

References MMC_HandleTypeDef::ErrorCode, HAL_MMC_ERROR_NONE, HAL_MMC_STATE_READY, __MDMA_HandleTypeDef::Init, MMC_HandleTypeDef::Instance, MMC_InitCard(), MMC_InitTypeDef, MMC_PowerON(), and MMC_HandleTypeDef::State.

Referenced by HAL_MMC_Init().

void HAL_MMC_MspDeInit ( MMC_HandleTypeDef * hmmc )

De-Initialize MMC MSP.

Parameters:
hmmc,: Pointer to MMC handle
Return values:
None

Definition at line 388 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_DeInit().

void HAL_MMC_MspInit ( MMC_HandleTypeDef * hmmc )

Initializes the MMC MSP.

Parameters:
hmmc,: Pointer to MMC handle
Return values:
None

Definition at line 373 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_Init().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
MMC Exported Functions

Data transfer functions. More...

Functions

HAL_StatusTypeDef | HAL_MMC_ReadBlocks (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_WriteBlocks (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Allows to write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_ReadBlocks_IT (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_WriteBlocks_IT (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_ReadBlocks_DMA (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_WriteBlocks_DMA (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_Erase (MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
Erases the specified memory area of the given MMC card.
void | HAL_MMC_IRQHandler (MMC_HandleTypeDef *hmmc)
This function handles MMC card interrupt request.
HAL_MMC_StateTypeDef | HAL_MMC_GetState (MMC_HandleTypeDef *hmmc)
return the MMC state
uint32_t | HAL_MMC_GetError (MMC_HandleTypeDef *hmmc)
Return the MMC error code.
__weak void | HAL_MMC_TxCpltCallback (MMC_HandleTypeDef *hmmc)
Tx Transfer completed callbacks.
__weak void | HAL_MMC_RxCpltCallback (MMC_HandleTypeDef *hmmc)
Rx Transfer completed callbacks.
__weak void | HAL_MMC_ErrorCallback (MMC_HandleTypeDef *hmmc)
MMC error callbacks.
__weak void | HAL_MMC_AbortCallback (MMC_HandleTypeDef *hmmc)
MMC Abort callbacks.

Detailed Description

Data transfer functions.

  ==============================================================================
                        ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the data
    transfer from/to MMC card.

Function Documentation

void HAL_MMC_AbortCallback ( MMC_HandleTypeDef * hmmc )

MMC Abort callbacks.

Parameters:
hmmc,: Pointer MMC handle
Return values:
None

Definition at line 1533 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_Abort_IT().

HAL_StatusTypeDef HAL_MMC_Erase | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint32_t | BlockStartAdd,
 |  | uint32_t | BlockEndAdd
 | ) |  |

Erases the specified memory area of the given MMC card.

Note:
This API should be followed by a check on the card state through HAL_MMC_GetCardState().
Parameters:
hmmc,: Pointer to MMC handle
BlockStartAdd,: Start Block address
BlockEndAdd,: End Block address
Return values:
HAL status

Definition at line 1184 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, HAL_MMC_CardInfoTypeDef::CardType, HAL_MMC_CardInfoTypeDef::Class, MMC_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_MMC_ERROR_ADDR_OUT_OF_RANGE, HAL_MMC_ERROR_LOCK_UNLOCK_FAILED, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_PARAM, HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE, HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, MMC_HandleTypeDef::Instance, HAL_MMC_CardInfoTypeDef::LogBlockNbr, MMC_HIGH_CAPACITY_CARD, MMC_HandleTypeDef::MmcCard, and MMC_HandleTypeDef::State.

void HAL_MMC_ErrorCallback ( MMC_HandleTypeDef * hmmc )

MMC error callbacks.

Parameters:
hmmc,: Pointer MMC handle
Return values:
None

Definition at line 1518 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_IRQHandler().

uint32_t HAL_MMC_GetError ( MMC_HandleTypeDef * hmmc )

Return the MMC error code.

Parameters:
hmmc : pointer to a MMC_HandleTypeDef structure that contains the configuration information.
Return values:
MMC Error Code

Definition at line 1478 of file stm32h7xx_hal_mmc.c.

References MMC_HandleTypeDef::ErrorCode.

HAL_MMC_StateTypeDef HAL_MMC_GetState ( MMC_HandleTypeDef * hmmc )

return the MMC state

Parameters:
hmmc,: Pointer to mmc handle
Return values:
HAL state

Definition at line 1467 of file stm32h7xx_hal_mmc.c.

References MMC_HandleTypeDef::State.

void HAL_MMC_IRQHandler ( MMC_HandleTypeDef * hmmc )

This function handles MMC card interrupt request.

Parameters:
hmmc,: Pointer to MMC handle
Return values:
None

Definition at line 1280 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_DISABLE_IT, __HAL_MMC_GET_FLAG, MMC_HandleTypeDef::Context, MMC_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_MMC_CARD_TRANSFER, HAL_MMC_ERROR_NONE, HAL_MMC_ErrorCallback(), HAL_MMC_GetCardState(), HAL_MMC_RxCpltCallback(), HAL_MMC_STATE_READY, HAL_MMC_TxCpltCallback(), HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback(), HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback(), HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback(), HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback(), MMC_HandleTypeDef::Instance, MMC_CONTEXT_DMA, MMC_CONTEXT_IT, MMC_CONTEXT_READ_MULTIPLE_BLOCK, MMC_CONTEXT_READ_SINGLE_BLOCK, MMC_CONTEXT_WRITE_MULTIPLE_BLOCK, MMC_CONTEXT_WRITE_SINGLE_BLOCK, MMC_DMA_BUFFER0, MMC_Read_IT(), MMC_Write_IT(), and MMC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MMC_ReadBlocks | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks,
 |  | uint32_t | Timeout
 | ) |  |

Reads block(s) from a specified address in a card.

The Data transfer is managed by polling mode.

Note:
This API should be followed by a check on the card state through HAL_MMC_GetCardState().
Parameters:
hmmc,: Pointer to MMC handle
pData,: pointer to the buffer that will contain the received data
BlockAdd,: Block Address from where data is to be read
NumberOfBlocks,: Number of MMC blocks to read
Timeout,: Specify timeout value
Return values:
HAL status

Definition at line 429 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_GET_FLAG, BLOCKSIZE, HAL_MMC_CardInfoTypeDef::CardType, MMC_HandleTypeDef::Context, MMC_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_GetTick(), HAL_MMC_ERROR_ADDR_OUT_OF_RANGE, HAL_MMC_ERROR_BUSY, HAL_MMC_ERROR_DATA_CRC_FAIL, HAL_MMC_ERROR_DATA_TIMEOUT, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_PARAM, HAL_MMC_ERROR_RX_OVERRUN, HAL_MMC_ERROR_TIMEOUT, HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, MMC_HandleTypeDef::Instance, HAL_MMC_CardInfoTypeDef::LogBlockNbr, MMC_CONTEXT_READ_MULTIPLE_BLOCK, MMC_CONTEXT_READ_SINGLE_BLOCK, MMC_HIGH_CAPACITY_CARD, MMC_HandleTypeDef::MmcCard, and MMC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Reads block(s) from a specified address in a card.

The Data transfer is managed by DMA mode.

Note:
This API should be followed by a check on the card state through HAL_MMC_GetCardState().
You could also check the DMA transfer process through the MMC Rx interrupt event.
Parameters:
hmmc,: Pointer MMC handle
pData,: Pointer to the buffer that will contain the received data
BlockAdd,: Block Address from where data is to be read
NumberOfBlocks,: Number of blocks to read.
Return values:
HAL status

Definition at line 971 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_DISABLE_IT, __HAL_MMC_ENABLE_IT, BLOCKSIZE, HAL_MMC_CardInfoTypeDef::CardType, MMC_HandleTypeDef::Context, MMC_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_MMC_ERROR_ADDR_OUT_OF_RANGE, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_PARAM, HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, MMC_HandleTypeDef::Instance, HAL_MMC_CardInfoTypeDef::LogBlockNbr, MMC_CONTEXT_DMA, MMC_CONTEXT_READ_MULTIPLE_BLOCK, MMC_CONTEXT_READ_SINGLE_BLOCK, MMC_HIGH_CAPACITY_CARD, MMC_HandleTypeDef::MmcCard, MMC_HandleTypeDef::pRxBuffPtr, MMC_HandleTypeDef::RxXferSize, and MMC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Reads block(s) from a specified address in a card.

The Data transfer is managed in interrupt mode.

Note:
This API should be followed by a check on the card state through HAL_MMC_GetCardState().
You could also check the IT transfer process through the MMC Rx interrupt event.
Parameters:
hmmc,: Pointer to MMC handle
pData,: Pointer to the buffer that will contain the received data
BlockAdd,: Block Address from where data is to be read
NumberOfBlocks,: Number of blocks to read.
Return values:
HAL status

Definition at line 766 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_ENABLE_IT, BLOCKSIZE, HAL_MMC_CardInfoTypeDef::CardType, MMC_HandleTypeDef::Context, MMC_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_MMC_ERROR_ADDR_OUT_OF_RANGE, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_PARAM, HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, MMC_HandleTypeDef::Instance, HAL_MMC_CardInfoTypeDef::LogBlockNbr, MMC_CONTEXT_IT, MMC_CONTEXT_READ_MULTIPLE_BLOCK, MMC_CONTEXT_READ_SINGLE_BLOCK, MMC_HIGH_CAPACITY_CARD, MMC_HandleTypeDef::MmcCard, MMC_HandleTypeDef::pRxBuffPtr, MMC_HandleTypeDef::RxXferSize, and MMC_HandleTypeDef::State.

void HAL_MMC_RxCpltCallback ( MMC_HandleTypeDef * hmmc )

Rx Transfer completed callbacks.

Parameters:
hmmc,: Pointer MMC handle
Return values:
None

Definition at line 1503 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_IRQHandler().

void HAL_MMC_TxCpltCallback ( MMC_HandleTypeDef * hmmc )

Tx Transfer completed callbacks.

Parameters:
hmmc,: Pointer to MMC handle
Return values:
None

Definition at line 1488 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_IRQHandler().

HAL_StatusTypeDef HAL_MMC_WriteBlocks | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks,
 |  | uint32_t | Timeout
 | ) |  |

Allows to write block(s) to a specified address in a card.

The Data transfer is managed by polling mode.

Note:
This API should be followed by a check on the card state through HAL_MMC_GetCardState().
Parameters:
hmmc,: Pointer to MMC handle
pData,: pointer to the buffer that will contain the data to transmit
BlockAdd,: Block Address where data will be written
NumberOfBlocks,: Number of MMC blocks to write
Timeout,: Specify timeout value
Return values:
HAL status

Definition at line 596 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_GET_FLAG, BLOCKSIZE, HAL_MMC_CardInfoTypeDef::CardType, MMC_HandleTypeDef::Context, MMC_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_GetTick(), HAL_MMC_ERROR_ADDR_OUT_OF_RANGE, HAL_MMC_ERROR_BUSY, HAL_MMC_ERROR_DATA_CRC_FAIL, HAL_MMC_ERROR_DATA_TIMEOUT, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_PARAM, HAL_MMC_ERROR_TX_UNDERRUN, HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, MMC_HandleTypeDef::Instance, HAL_MMC_CardInfoTypeDef::LogBlockNbr, MMC_CONTEXT_WRITE_MULTIPLE_BLOCK, MMC_CONTEXT_WRITE_SINGLE_BLOCK, MMC_HIGH_CAPACITY_CARD, MMC_HandleTypeDef::MmcCard, and MMC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Writes block(s) to a specified address in a card.

The Data transfer is managed by DMA mode.

Note:
This API should be followed by a check on the card state through HAL_MMC_GetCardState().
You could also check the DMA transfer process through the MMC Tx interrupt event.
Parameters:
hmmc,: Pointer to MMC handle
pData,: pointer to the buffer that will contain the data to transmit
BlockAdd,: Block Address where data will be written
NumberOfBlocks,: Number of blocks to write
Return values:
HAL status

Definition at line 1080 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_DISABLE_IT, __HAL_MMC_ENABLE_IT, BLOCKSIZE, HAL_MMC_CardInfoTypeDef::CardType, MMC_HandleTypeDef::Context, MMC_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_MMC_ERROR_ADDR_OUT_OF_RANGE, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_PARAM, HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, MMC_HandleTypeDef::Instance, HAL_MMC_CardInfoTypeDef::LogBlockNbr, MMC_CONTEXT_DMA, MMC_CONTEXT_WRITE_MULTIPLE_BLOCK, MMC_CONTEXT_WRITE_SINGLE_BLOCK, MMC_HIGH_CAPACITY_CARD, MMC_HandleTypeDef::MmcCard, MMC_HandleTypeDef::pTxBuffPtr, MMC_HandleTypeDef::State, and MMC_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Writes block(s) to a specified address in a card.

The Data transfer is managed in interrupt mode.

Note:
This API should be followed by a check on the card state through HAL_MMC_GetCardState().
You could also check the IT transfer process through the MMC Tx interrupt event.
Parameters:
hmmc,: Pointer to MMC handle
pData,: Pointer to the buffer that will contain the data to transmit
BlockAdd,: Block Address where data will be written
NumberOfBlocks,: Number of blocks to write
Return values:
HAL status

Definition at line 869 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_ENABLE_IT, BLOCKSIZE, HAL_MMC_CardInfoTypeDef::CardType, MMC_HandleTypeDef::Context, MMC_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_MMC_ERROR_ADDR_OUT_OF_RANGE, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_PARAM, HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, MMC_HandleTypeDef::Instance, HAL_MMC_CardInfoTypeDef::LogBlockNbr, MMC_CONTEXT_IT, MMC_CONTEXT_WRITE_MULTIPLE_BLOCK, MMC_CONTEXT_WRITE_SINGLE_BLOCK, MMC_HIGH_CAPACITY_CARD, MMC_HandleTypeDef::MmcCard, MMC_HandleTypeDef::pTxBuffPtr, MMC_HandleTypeDef::State, and MMC_HandleTypeDef::TxXferSize.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
MMC Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_MMC_GetCardCID (MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypedef *pCID)
Returns information the information of the card which are stored on the CID register.
HAL_StatusTypeDef | HAL_MMC_GetCardCSD (MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
Returns information the information of the card which are stored on the CSD register.
HAL_StatusTypeDef | HAL_MMC_GetCardInfo (MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
Gets the MMC card info.
HAL_StatusTypeDef | HAL_MMC_ConfigWideBusOperation (MMC_HandleTypeDef *hmmc, uint32_t WideMode)
Enables wide bus operation for the requested card if supported by card.
HAL_MMC_CardStateTypedef | HAL_MMC_GetCardState (MMC_HandleTypeDef *hmmc)
Gets the current mmc card data state.
HAL_StatusTypeDef | HAL_MMC_Abort (MMC_HandleTypeDef *hmmc)
Abort the current transfer and disable the MMC.
HAL_StatusTypeDef | HAL_MMC_Abort_IT (MMC_HandleTypeDef *hmmc)
Abort the current transfer and disable the MMC (IT mode).

Detailed Description

management functions

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control the MMC card
    operations and get the related information

Function Documentation

HAL_StatusTypeDef HAL_MMC_Abort ( MMC_HandleTypeDef * hmmc )

Abort the current transfer and disable the MMC.

Parameters:
hmmc,: pointer to a MMC_HandleTypeDef structure that contains the configuration information for MMC module.
Return values:
HAL status

Definition at line 1943 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_DISABLE_IT, MMC_HandleTypeDef::ErrorCode, HAL_MMC_CARD_RECEIVING, HAL_MMC_CARD_SENDING, HAL_MMC_ERROR_NONE, HAL_MMC_GetCardState(), HAL_MMC_STATE_READY, MMC_HandleTypeDef::Instance, and MMC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MMC_Abort_IT ( MMC_HandleTypeDef * hmmc )

Abort the current transfer and disable the MMC (IT mode).

Parameters:
hmmc,: pointer to a MMC_HandleTypeDef structure that contains the configuration information for MMC module.
Return values:
HAL status

Definition at line 1977 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_DISABLE_IT, MMC_HandleTypeDef::ErrorCode, HAL_MMC_AbortCallback(), HAL_MMC_CARD_RECEIVING, HAL_MMC_CARD_SENDING, HAL_MMC_ERROR_NONE, HAL_MMC_GetCardState(), HAL_MMC_STATE_READY, MMC_HandleTypeDef::Instance, and MMC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint32_t | WideMode
 | ) |  |

Enables wide bus operation for the requested card if supported by card.

Parameters:
hmmc,: Pointer to MMC handle
WideMode,: Specifies the MMC card wide bus mode This parameter can be one of the following values:
  • SDMMC_BUS_WIDE_8B: 8-bit data transfer
  • SDMMC_BUS_WIDE_4B: 4-bit data transfer
  • SDMMC_BUS_WIDE_1B: 1-bit data transfer
Return values:
HAL status

Definition at line 1801 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, assert_param, MMC_HandleTypeDef::ErrorCode, HAL_MMC_ERROR_NONE, HAL_MMC_ERROR_PARAM, HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE, HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, MMC_HandleTypeDef::Init, __MDMA_HandleTypeDef::Init, MMC_HandleTypeDef::Instance, MMC_InitTypeDef, MMC_HandleTypeDef::MmcCard, HAL_MMC_CardInfoTypeDef::RelCardAdd, and MMC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MMC_GetCardCID | ( | MMC_HandleTypeDef * | hmmc,
 |  | HAL_MMC_CardCIDTypedef * | pCID
 | ) |  |

Returns information the information of the card which are stored on the CID register.

Parameters:
hmmc,: Pointer to MMC handle
pCID,: Pointer to a HAL_MMC_CIDTypedef structure that contains all CID register parameters
Return values:
HAL status

Definition at line 1571 of file stm32h7xx_hal_mmc.c.

References MMC_HandleTypeDef::CID, HAL_MMC_CardCIDTypedef::CID_CRC, HAL_MMC_CardCIDTypedef::ManufactDate, HAL_MMC_CardCIDTypedef::ManufacturerID, HAL_MMC_CardCIDTypedef::OEM_AppliID, HAL_MMC_CardCIDTypedef::ProdName1, HAL_MMC_CardCIDTypedef::ProdName2, HAL_MMC_CardCIDTypedef::ProdRev, HAL_MMC_CardCIDTypedef::ProdSN, HAL_MMC_CardCIDTypedef::Reserved1, and HAL_MMC_CardCIDTypedef::Reserved2.

HAL_StatusTypeDef HAL_MMC_GetCardCSD | ( | MMC_HandleTypeDef * | hmmc,
 |  | HAL_MMC_CardCSDTypeDef * | pCSD
 | ) |  |

Returns information the information of the card which are stored on the CSD register.

Parameters:
hmmc,: Pointer to MMC handle
pCSD,: Pointer to a HAL_MMC_CardInfoTypedef structure that contains all CSD register parameters
Return values:
HAL status

< Reserved

Definition at line 1652 of file stm32h7xx_hal_mmc.c.

References HAL_MMC_CardInfoTypeDef::BlockNbr, HAL_MMC_CardInfoTypeDef::BlockSize, HAL_MMC_CardCSDTypeDef::CardComdClasses, HAL_MMC_CardInfoTypeDef::CardType, HAL_MMC_CardCSDTypeDef::ContentProtectAppli, HAL_MMC_CardCSDTypeDef::CopyFlag, MMC_HandleTypeDef::CSD, HAL_MMC_CardCSDTypeDef::CSD_CRC, HAL_MMC_CardCSDTypeDef::CSDStruct, HAL_MMC_CardCSDTypeDef::DeviceSize, HAL_MMC_CardCSDTypeDef::DeviceSizeMul, HAL_MMC_CardCSDTypeDef::DSRImpl, HAL_MMC_CardCSDTypeDef::ECC, HAL_MMC_CardCSDTypeDef::EraseGrMul, HAL_MMC_CardCSDTypeDef::EraseGrSize, HAL_MMC_CardCSDTypeDef::FileFormat, HAL_MMC_CardCSDTypeDef::FileFormatGrouop, HAL_MMC_CardInfoTypeDef::LogBlockNbr, HAL_MMC_CardInfoTypeDef::LogBlockSize, HAL_MMC_CardCSDTypeDef::ManDeflECC, HAL_MMC_CardCSDTypeDef::MaxBusClkFrec, HAL_MMC_CardCSDTypeDef::MaxRdCurrentVDDMax, HAL_MMC_CardCSDTypeDef::MaxRdCurrentVDDMin, HAL_MMC_CardCSDTypeDef::MaxWrBlockLen, HAL_MMC_CardCSDTypeDef::MaxWrCurrentVDDMax, HAL_MMC_CardCSDTypeDef::MaxWrCurrentVDDMin, MMC_HIGH_CAPACITY_CARD, MMC_LOW_CAPACITY_CARD, MMC_ReadExtCSD(), MMC_HandleTypeDef::MmcCard, HAL_MMC_CardCSDTypeDef::NSAC, HAL_MMC_CardCSDTypeDef::PartBlockRead, HAL_MMC_CardCSDTypeDef::PermWrProtect, HAL_MMC_CardCSDTypeDef::RdBlockLen, HAL_MMC_CardCSDTypeDef::RdBlockMisalign, HAL_MMC_CardCSDTypeDef::Reserved1, HAL_MMC_CardCSDTypeDef::Reserved2, HAL_MMC_CardCSDTypeDef::Reserved3, HAL_MMC_CardCSDTypeDef::Reserved4, HAL_MMC_CardCSDTypeDef::SysSpecVersion, HAL_MMC_CardCSDTypeDef::TAAC, HAL_MMC_CardCSDTypeDef::TempWrProtect, HAL_MMC_CardCSDTypeDef::WrBlockMisalign, HAL_MMC_CardCSDTypeDef::WriteBlockPaPartial, HAL_MMC_CardCSDTypeDef::WrProtectGrEnable, HAL_MMC_CardCSDTypeDef::WrProtectGrSize, and HAL_MMC_CardCSDTypeDef::WrSpeedFact.

Referenced by MMC_InitCard().

HAL_StatusTypeDef HAL_MMC_GetCardInfo | ( | MMC_HandleTypeDef * | hmmc,
 |  | HAL_MMC_CardInfoTypeDef * | pCardInfo
 | ) |  |

Gets the MMC card info.

Parameters:
hmmc,: Pointer to MMC handle
pCardInfo,: Pointer to the HAL_MMC_CardInfoTypeDef structure that will contain the MMC card status information
Return values:
HAL status

Definition at line 1777 of file stm32h7xx_hal_mmc.c.

References HAL_MMC_CardInfoTypeDef::BlockNbr, HAL_MMC_CardInfoTypeDef::BlockSize, HAL_MMC_CardInfoTypeDef::CardType, HAL_MMC_CardInfoTypeDef::Class, HAL_MMC_CardInfoTypeDef::LogBlockNbr, HAL_MMC_CardInfoTypeDef::LogBlockSize, MMC_HandleTypeDef::MmcCard, and HAL_MMC_CardInfoTypeDef::RelCardAdd.

HAL_MMC_CardStateTypedef HAL_MMC_GetCardState ( MMC_HandleTypeDef * hmmc )

Gets the current mmc card data state.

Parameters:
hmmc,: pointer to MMC handle
Return values:
Card state

Definition at line 1918 of file stm32h7xx_hal_mmc.c.

References MMC_HandleTypeDef::ErrorCode, HAL_MMC_CARD_TRANSFER, HAL_MMC_ERROR_NONE, MMC_HandleTypeDef::Instance, and MMC_SendStatus().

Referenced by HAL_MMC_Abort(), HAL_MMC_Abort_IT(), and HAL_MMC_IRQHandler().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MMC card related functions

Functions
MMC card related functions
MMC Exported Functions

Functions

HAL_MMC_CardStateTypedef | HAL_MMC_GetCardState (MMC_HandleTypeDef *hmmc)
Gets the current mmc card data state.
HAL_StatusTypeDef | HAL_MMC_GetCardCID (MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypedef *pCID)
Returns information the information of the card which are stored on the CID register.
HAL_StatusTypeDef | HAL_MMC_GetCardCSD (MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
Returns information the information of the card which are stored on the CSD register.
HAL_StatusTypeDef | HAL_MMC_GetCardInfo (MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
Gets the MMC card info.

Function Documentation

HAL_StatusTypeDef HAL_MMC_GetCardCID | ( | MMC_HandleTypeDef * | hmmc,
 |  | HAL_MMC_CardCIDTypedef * | pCID
 | ) |  |

Returns information the information of the card which are stored on the CID register.

Parameters:
hmmc,: Pointer to MMC handle
pCID,: Pointer to a HAL_MMC_CIDTypedef structure that contains all CID register parameters
Return values:
HAL status

Definition at line 1571 of file stm32h7xx_hal_mmc.c.

References MMC_HandleTypeDef::CID, HAL_MMC_CardCIDTypedef::CID_CRC, HAL_MMC_CardCIDTypedef::ManufactDate, HAL_MMC_CardCIDTypedef::ManufacturerID, HAL_MMC_CardCIDTypedef::OEM_AppliID, HAL_MMC_CardCIDTypedef::ProdName1, HAL_MMC_CardCIDTypedef::ProdName2, HAL_MMC_CardCIDTypedef::ProdRev, HAL_MMC_CardCIDTypedef::ProdSN, HAL_MMC_CardCIDTypedef::Reserved1, and HAL_MMC_CardCIDTypedef::Reserved2.

HAL_StatusTypeDef HAL_MMC_GetCardCSD | ( | MMC_HandleTypeDef * | hmmc,
 |  | HAL_MMC_CardCSDTypeDef * | pCSD
 | ) |  |

Returns information the information of the card which are stored on the CSD register.

Parameters:
hmmc,: Pointer to MMC handle
pCSD,: Pointer to a HAL_MMC_CardInfoTypedef structure that contains all CSD register parameters
Return values:
HAL status

< Reserved

Definition at line 1652 of file stm32h7xx_hal_mmc.c.

References HAL_MMC_CardInfoTypeDef::BlockNbr, HAL_MMC_CardInfoTypeDef::BlockSize, HAL_MMC_CardCSDTypeDef::CardComdClasses, HAL_MMC_CardInfoTypeDef::CardType, HAL_MMC_CardCSDTypeDef::ContentProtectAppli, HAL_MMC_CardCSDTypeDef::CopyFlag, MMC_HandleTypeDef::CSD, HAL_MMC_CardCSDTypeDef::CSD_CRC, HAL_MMC_CardCSDTypeDef::CSDStruct, HAL_MMC_CardCSDTypeDef::DeviceSize, HAL_MMC_CardCSDTypeDef::DeviceSizeMul, HAL_MMC_CardCSDTypeDef::DSRImpl, HAL_MMC_CardCSDTypeDef::ECC, HAL_MMC_CardCSDTypeDef::EraseGrMul, HAL_MMC_CardCSDTypeDef::EraseGrSize, HAL_MMC_CardCSDTypeDef::FileFormat, HAL_MMC_CardCSDTypeDef::FileFormatGrouop, HAL_MMC_CardInfoTypeDef::LogBlockNbr, HAL_MMC_CardInfoTypeDef::LogBlockSize, HAL_MMC_CardCSDTypeDef::ManDeflECC, HAL_MMC_CardCSDTypeDef::MaxBusClkFrec, HAL_MMC_CardCSDTypeDef::MaxRdCurrentVDDMax, HAL_MMC_CardCSDTypeDef::MaxRdCurrentVDDMin, HAL_MMC_CardCSDTypeDef::MaxWrBlockLen, HAL_MMC_CardCSDTypeDef::MaxWrCurrentVDDMax, HAL_MMC_CardCSDTypeDef::MaxWrCurrentVDDMin, MMC_HIGH_CAPACITY_CARD, MMC_LOW_CAPACITY_CARD, MMC_ReadExtCSD(), MMC_HandleTypeDef::MmcCard, HAL_MMC_CardCSDTypeDef::NSAC, HAL_MMC_CardCSDTypeDef::PartBlockRead, HAL_MMC_CardCSDTypeDef::PermWrProtect, HAL_MMC_CardCSDTypeDef::RdBlockLen, HAL_MMC_CardCSDTypeDef::RdBlockMisalign, HAL_MMC_CardCSDTypeDef::Reserved1, HAL_MMC_CardCSDTypeDef::Reserved2, HAL_MMC_CardCSDTypeDef::Reserved3, HAL_MMC_CardCSDTypeDef::Reserved4, HAL_MMC_CardCSDTypeDef::SysSpecVersion, HAL_MMC_CardCSDTypeDef::TAAC, HAL_MMC_CardCSDTypeDef::TempWrProtect, HAL_MMC_CardCSDTypeDef::WrBlockMisalign, HAL_MMC_CardCSDTypeDef::WriteBlockPaPartial, HAL_MMC_CardCSDTypeDef::WrProtectGrEnable, HAL_MMC_CardCSDTypeDef::WrProtectGrSize, and HAL_MMC_CardCSDTypeDef::WrSpeedFact.

Referenced by MMC_InitCard().

HAL_StatusTypeDef HAL_MMC_GetCardInfo | ( | MMC_HandleTypeDef * | hmmc,
 |  | HAL_MMC_CardInfoTypeDef * | pCardInfo
 | ) |  |

Gets the MMC card info.

Parameters:
hmmc,: Pointer to MMC handle
pCardInfo,: Pointer to the HAL_MMC_CardInfoTypeDef structure that will contain the MMC card status information
Return values:
HAL status

Definition at line 1777 of file stm32h7xx_hal_mmc.c.

References HAL_MMC_CardInfoTypeDef::BlockNbr, HAL_MMC_CardInfoTypeDef::BlockSize, HAL_MMC_CardInfoTypeDef::CardType, HAL_MMC_CardInfoTypeDef::Class, HAL_MMC_CardInfoTypeDef::LogBlockNbr, HAL_MMC_CardInfoTypeDef::LogBlockSize, MMC_HandleTypeDef::MmcCard, and HAL_MMC_CardInfoTypeDef::RelCardAdd.

HAL_MMC_CardStateTypedef HAL_MMC_GetCardState ( MMC_HandleTypeDef * hmmc )

Gets the current mmc card data state.

Parameters:
hmmc,: pointer to MMC handle
Return values:
Card state

Definition at line 1918 of file stm32h7xx_hal_mmc.c.

References MMC_HandleTypeDef::ErrorCode, HAL_MMC_CARD_TRANSFER, HAL_MMC_ERROR_NONE, MMC_HandleTypeDef::Instance, and MMC_SendStatus().

Referenced by HAL_MMC_Abort(), HAL_MMC_Abort_IT(), and HAL_MMC_IRQHandler().

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STM32H753xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
MMC Exported Functions

Functions

HAL_MMC_StateTypeDef | HAL_MMC_GetState (MMC_HandleTypeDef *hmmc)
return the MMC state
uint32_t | HAL_MMC_GetError (MMC_HandleTypeDef *hmmc)
Return the MMC error code.

Function Documentation

uint32_t HAL_MMC_GetError ( MMC_HandleTypeDef * hmmc )

Return the MMC error code.

Parameters:
hmmc : pointer to a MMC_HandleTypeDef structure that contains the configuration information.
Return values:
MMC Error Code

Definition at line 1478 of file stm32h7xx_hal_mmc.c.

References MMC_HandleTypeDef::ErrorCode.

HAL_MMC_StateTypeDef HAL_MMC_GetState ( MMC_HandleTypeDef * hmmc )

return the MMC state

Parameters:
hmmc,: Pointer to mmc handle
Return values:
HAL state

Definition at line 1467 of file stm32h7xx_hal_mmc.c.

References MMC_HandleTypeDef::State.

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STM32H753xx HAL User Manual: Perioheral Abort management

Functions
Perioheral Abort management
MMC Exported Functions

Functions

HAL_StatusTypeDef | HAL_MMC_Abort (MMC_HandleTypeDef *hmmc)
Abort the current transfer and disable the MMC.
HAL_StatusTypeDef | HAL_MMC_Abort_IT (MMC_HandleTypeDef *hmmc)
Abort the current transfer and disable the MMC (IT mode).

Function Documentation

HAL_StatusTypeDef HAL_MMC_Abort ( MMC_HandleTypeDef * hmmc )

Abort the current transfer and disable the MMC.

Parameters:
hmmc,: pointer to a MMC_HandleTypeDef structure that contains the configuration information for MMC module.
Return values:
HAL status

Definition at line 1943 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_DISABLE_IT, MMC_HandleTypeDef::ErrorCode, HAL_MMC_CARD_RECEIVING, HAL_MMC_CARD_SENDING, HAL_MMC_ERROR_NONE, HAL_MMC_GetCardState(), HAL_MMC_STATE_READY, MMC_HandleTypeDef::Instance, and MMC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_MMC_Abort_IT ( MMC_HandleTypeDef * hmmc )

Abort the current transfer and disable the MMC (IT mode).

Parameters:
hmmc,: pointer to a MMC_HandleTypeDef structure that contains the configuration information for MMC module.
Return values:
HAL status

Definition at line 1977 of file stm32h7xx_hal_mmc.c.

References __HAL_MMC_CLEAR_FLAG, __HAL_MMC_DISABLE_IT, MMC_HandleTypeDef::ErrorCode, HAL_MMC_AbortCallback(), HAL_MMC_CARD_RECEIVING, HAL_MMC_CARD_SENDING, HAL_MMC_ERROR_NONE, HAL_MMC_GetCardState(), HAL_MMC_STATE_READY, MMC_HandleTypeDef::Instance, and MMC_HandleTypeDef::State.

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STM32H753xx HAL User Manual: MMC Private Types

MMC Private Types
MMC Exported Functions
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STM32H753xx HAL User Manual: MMC Private Defines

MMC Private Defines
MMC Exported Functions | MMC
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STM32H753xx HAL User Manual: MMC Private Variables

MMC Private Variables
MMC Exported Functions
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STM32H753xx HAL User Manual: MMC Private Constants

MMC Private Constants
MMC Exported Functions
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STM32H753xx HAL User Manual: MMC Private Macros

MMC Private Macros
MMC Exported Functions
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STM32H753xx HAL User Manual: MMC Private Functions Prototypes

MMC Private Functions Prototypes
MMC Exported Functions
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STM32H753xx HAL User Manual: MMC Internal DMA Buffer structure

Enumerations
MMC Internal DMA Buffer structure
MMCEx Exported Types

Enumerations

enum HAL_MMCEx_DMABuffer_MemoryTypeDef { MMC_DMA_BUFFER0 = 0x00U, MMC_DMA_BUFFER1 = 0x01U }

Enumeration Type Documentation

enum HAL_MMCEx_DMABuffer_MemoryTypeDef
Enumerator:
MMC_DMA_BUFFER0

selects MMC internal DMA Buffer 0

MMC_DMA_BUFFER1

selects MMC internal DMA Buffer 1

Definition at line 66 of file stm32h7xx_hal_mmc_ex.h.

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STM32H753xx HAL User Manual: MultiBuffer functions

Functions
MultiBuffer functions
MMCEx Exported Functions

Multibuffer functions. More...

Functions

HAL_StatusTypeDef | HAL_MMCEx_ConfigDMAMultiBuffer (MMC_HandleTypeDef *hmmc, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, uint32_t BufferSize)
Configure DMA Dual Buffer mode.
HAL_StatusTypeDef | HAL_MMCEx_ReadBlocksDMAMultiBuffer (MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMCEx_WriteBlocksDMAMultiBuffer (MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMCEx_ChangeDMABuffer (MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
Change the DMA Buffer0 or Buffer1 address on the fly.
void | HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback (MMC_HandleTypeDef *hmmc)
Read DMA Buffer 0 Transfer completed callbacks.
void | HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback (MMC_HandleTypeDef *hmmc)
Read DMA Buffer 1 Transfer completed callbacks.
void | HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback (MMC_HandleTypeDef *hmmc)
Write DMA Buffer 0 Transfer completed callbacks.
void | HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback (MMC_HandleTypeDef *hmmc)
Write DMA Buffer 1 Transfer completed callbacks.

Detailed Description

Multibuffer functions.

  ==============================================================================
          ##### Multibuffer functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to configure the multibuffer mode and start read and write
    multibuffer mode for MMC HAL driver.

Function Documentation

HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer | ( | MMC_HandleTypeDef * | hmmc,
 |  | HAL_MMCEx_DMABuffer_MemoryTypeDef | Buffer,
 |  | uint32_t * | pDataBuffer
 | ) |  |

Change the DMA Buffer0 or Buffer1 address on the fly.

Parameters:
hmmc,: pointer to a MMC_HandleTypeDef structure.
Buffer,: the buffer to be changed, This parameter can be one of the following values: MMC_DMA_BUFFER0 or MMC_DMA_BUFFER1
pDataBuffer,: The new address
Note:
The BUFFER0 address can be changed only when the current transfer use BUFFER1 and the BUFFER1 address can be changed only when the current transfer use BUFFER0.
Return values:
HAL status

Definition at line 279 of file stm32h7xx_hal_mmc_ex.c.

References MMC_HandleTypeDef::Instance, and MMC_DMA_BUFFER0.

HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint32_t * | pDataBuffer0,
 |  | uint32_t * | pDataBuffer1,
 |  | uint32_t | BufferSize
 | ) |  |

Configure DMA Dual Buffer mode.

The Data transfer is managed by an Internal DMA.

Parameters:
hmmc,: MMC handle
pDataBuffer0,: Pointer to the buffer0 that will contain/receive the transfered data
pDataBuffer1,: Pointer to the buffer1 that will contain/receive the transfered data
BufferSize,: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
Return values:
HAL status

Definition at line 101 of file stm32h7xx_hal_mmc_ex.c.

References HAL_MMC_STATE_READY, MMC_HandleTypeDef::Instance, and MMC_HandleTypeDef::State.

void HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback ( MMC_HandleTypeDef * hmmc )

Read DMA Buffer 0 Transfer completed callbacks.

Parameters:
hmmc,: MMC handle
Return values:
None

Definition at line 2367 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_IRQHandler().

void HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback ( MMC_HandleTypeDef * hmmc )

Read DMA Buffer 1 Transfer completed callbacks.

Parameters:
hmmc,: MMC handle
Return values:
None

Definition at line 2382 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_IRQHandler().

HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Reads block(s) from a specified address in a card.

The received Data will be stored in Buffer0 and Buffer1. Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.

Parameters:
hmmc,: MMC handle
BlockAdd,: Block Address from where data is to be read
NumberOfBlocks,: Total number of blocks to read
Return values:
HAL status

Definition at line 125 of file stm32h7xx_hal_mmc_ex.c.

References __HAL_MMC_ENABLE_IT, BLOCKSIZE, HAL_MMC_CardInfoTypeDef::CardType, MMC_HandleTypeDef::Context, MMC_HandleTypeDef::ErrorCode, HAL_MMC_ERROR_ADDR_OUT_OF_RANGE, HAL_MMC_ERROR_NONE, HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, MMC_HandleTypeDef::Instance, HAL_MMC_CardInfoTypeDef::LogBlockNbr, MMC_CONTEXT_DMA, MMC_CONTEXT_READ_MULTIPLE_BLOCK, MMC_HIGH_CAPACITY_CARD, MMC_HandleTypeDef::MmcCard, and MMC_HandleTypeDef::State.

void HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback ( MMC_HandleTypeDef * hmmc )

Write DMA Buffer 0 Transfer completed callbacks.

Parameters:
hmmc,: MMC handle
Return values:
None

Definition at line 2397 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_IRQHandler().

void HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback ( MMC_HandleTypeDef * hmmc )

Write DMA Buffer 1 Transfer completed callbacks.

Parameters:
hmmc,: MMC handle
Return values:
None

Definition at line 2412 of file stm32h7xx_hal_mmc.c.

Referenced by HAL_MMC_IRQHandler().

HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer | ( | MMC_HandleTypeDef * | hmmc,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Write block(s) to a specified address in a card.

The transfered Data are stored in Buffer0 and Buffer1. Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.

Parameters:
hmmc,: MMC handle
BlockAdd,: Block Address from where data is to be read
NumberOfBlocks,: Total number of blocks to read
Return values:
HAL status

Definition at line 201 of file stm32h7xx_hal_mmc_ex.c.

References __HAL_MMC_ENABLE_IT, BLOCKSIZE, HAL_MMC_CardInfoTypeDef::CardType, MMC_HandleTypeDef::Context, MMC_HandleTypeDef::ErrorCode, HAL_MMC_ERROR_ADDR_OUT_OF_RANGE, HAL_MMC_ERROR_NONE, HAL_MMC_STATE_BUSY, HAL_MMC_STATE_READY, MMC_HandleTypeDef::Instance, HAL_MMC_CardInfoTypeDef::LogBlockNbr, MMC_CONTEXT_DMA, MMC_CONTEXT_WRITE_MULTIPLE_BLOCK, MMC_HIGH_CAPACITY_CARD, MMC_HandleTypeDef::MmcCard, and MMC_HandleTypeDef::State.

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STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
NAND Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_NAND_Init (NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
Perform NAND memory Initialization sequence.
HAL_StatusTypeDef | HAL_NAND_DeInit (NAND_HandleTypeDef *hnand)
Perform NAND memory De-Initialization sequence.
__weak void | HAL_NAND_MspInit (NAND_HandleTypeDef *hnand)
NAND MSP Init.
__weak void | HAL_NAND_MspDeInit (NAND_HandleTypeDef *hnand)
NAND MSP DeInit.
void | HAL_NAND_IRQHandler (NAND_HandleTypeDef *hnand)
This function handles NAND device interrupt request.
__weak void | HAL_NAND_ITCallback (NAND_HandleTypeDef *hnand)
NAND interrupt feature callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
            ##### NAND Initialization and de-initialization functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to initialize/de-initialize
    the NAND memory

Function Documentation

HAL_StatusTypeDef HAL_NAND_DeInit ( NAND_HandleTypeDef * hnand )

Perform NAND memory De-Initialization sequence.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL status

Definition at line 180 of file stm32h7xx_hal_nand.c.

References HAL_NAND_MspDeInit(), HAL_NAND_STATE_RESET, NAND_HandleTypeDef::Init, NAND_HandleTypeDef::Instance, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Init | ( | NAND_HandleTypeDef * | hnand,
 |  | FMC_NAND_PCC_TimingTypeDef * | ComSpace_Timing,
 |  | FMC_NAND_PCC_TimingTypeDef * | AttSpace_Timing
 | ) |  |

Perform NAND memory Initialization sequence.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
ComSpace_Timing,: pointer to Common space timing structure
AttSpace_Timing,: pointer to Attribute space timing structure
Return values:
HAL status

Definition at line 137 of file stm32h7xx_hal_nand.c.

References HAL_NAND_MspInit(), HAL_NAND_STATE_READY, HAL_NAND_STATE_RESET, NAND_HandleTypeDef::Init, NAND_HandleTypeDef::Instance, NAND_HandleTypeDef::Lock, and NAND_HandleTypeDef::State.

void HAL_NAND_IRQHandler ( NAND_HandleTypeDef * hnand )

This function handles NAND device interrupt request.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL status

Definition at line 236 of file stm32h7xx_hal_nand.c.

References HAL_NAND_ITCallback(), NAND_HandleTypeDef::Init, and NAND_HandleTypeDef::Instance.

void HAL_NAND_ITCallback ( NAND_HandleTypeDef * hnand )

NAND interrupt feature callback.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
None

Definition at line 286 of file stm32h7xx_hal_nand.c.

Referenced by HAL_NAND_IRQHandler().

void HAL_NAND_MspDeInit ( NAND_HandleTypeDef * hnand )

NAND MSP DeInit.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
None

Definition at line 219 of file stm32h7xx_hal_nand.c.

Referenced by HAL_NAND_DeInit().

void HAL_NAND_MspInit ( NAND_HandleTypeDef * hnand )

NAND MSP Init.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
None

Definition at line 203 of file stm32h7xx_hal_nand.c.

Referenced by HAL_NAND_Init().

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STM32H753xx HAL User Manual: Input and Output functions

Functions
Input and Output functions
NAND Exported Functions

Input Output and memory control functions. More...

Functions

HAL_StatusTypeDef | HAL_NAND_Read_ID (NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
Read the NAND memory electronic signature.
HAL_StatusTypeDef | HAL_NAND_Reset (NAND_HandleTypeDef *hnand)
NAND memory reset.
HAL_StatusTypeDef | HAL_NAND_ConfigDevice (NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
Configure the device: Enter the physical parameters of the device.
HAL_StatusTypeDef | HAL_NAND_Read_Page_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
Read Page(s) from NAND memory block (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Read_Page_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
Read Page(s) from NAND memory block (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_Page_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
Write Page(s) to NAND memory block (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_Page_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
Write Page(s) to NAND memory block (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Read_SpareArea_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
Read Spare area(s) from NAND memory (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Read_SpareArea_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
Read Spare area(s) from NAND memory (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_SpareArea_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
Write Spare area(s) to NAND memory (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_SpareArea_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
Write Spare area(s) to NAND memory (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Erase_Block (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
NAND memory Block erase.
uint32_t | HAL_NAND_Address_Inc (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
Increment the NAND memory address.

Detailed Description

Input Output and memory control functions.

  ==============================================================================
                    ##### NAND Input and Output functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to use and control the NAND
    memory

Function Documentation

uint32_t HAL_NAND_Address_Inc | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress
 | ) |  |

Increment the NAND memory address.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress,: pointer to NAND address structure
Return values:
The new status of the increment address operation. It can be:
  • NAND_VALID_ADDRESS: When the new address is valid address
  • NAND_INVALID_ADDRESS: When the new address is invalid address

Definition at line 1651 of file stm32h7xx_hal_nand.c.

References NAND_AddressTypeDef::Block, NAND_DeviceConfigTypeDef::BlockNbr, NAND_DeviceConfigTypeDef::BlockSize, NAND_HandleTypeDef::Config, NAND_INVALID_ADDRESS, NAND_VALID_ADDRESS, NAND_AddressTypeDef::Page, NAND_AddressTypeDef::Plane, and NAND_DeviceConfigTypeDef::PlaneSize.

HAL_StatusTypeDef HAL_NAND_ConfigDevice | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_DeviceConfigTypeDef * | pDeviceConfig
 | ) |  |

Configure the device: Enter the physical parameters of the device.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pDeviceConfig : pointer to NAND_DeviceConfigTypeDef structure
Return values:
HAL status

Definition at line 426 of file stm32h7xx_hal_nand.c.

References NAND_DeviceConfigTypeDef::BlockNbr, NAND_DeviceConfigTypeDef::BlockSize, NAND_HandleTypeDef::Config, NAND_DeviceConfigTypeDef::ExtraCommandEnable, NAND_DeviceConfigTypeDef::PageSize, NAND_DeviceConfigTypeDef::PlaneNbr, NAND_DeviceConfigTypeDef::PlaneSize, and NAND_DeviceConfigTypeDef::SpareAreaSize.

HAL_StatusTypeDef HAL_NAND_Erase_Block | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress
 | ) |  |

NAND memory Block erase.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress : pointer to NAND address structure
Return values:
HAL status

Definition at line 1601 of file stm32h7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_AREA, ARRAY_ADDRESS, CMD_AREA, HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_CMD_ERASE0, NAND_CMD_ERASE1, NAND_DEVICE, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Read_ID | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_IDTypeDef * | pNAND_ID
 | ) |  |

Read the NAND memory electronic signature.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pNAND_ID,: NAND ID structure
Return values:
HAL status

Definition at line 322 of file stm32h7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_4TH_CYCLE, ADDR_AREA, CMD_AREA, NAND_IDTypeDef::Device_Id, NAND_IDTypeDef::Fourth_Id, HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_HandleTypeDef::Init, NAND_IDTypeDef::Maker_Id, NAND_CMD_READID, NAND_DEVICE, NAND_HandleTypeDef::State, and NAND_IDTypeDef::Third_Id.

HAL_StatusTypeDef HAL_NAND_Read_Page_16b | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint16_t * | pBuffer,
 |  | uint32_t | NumPageToRead
 | ) |  |

Read Page(s) from NAND memory block (16-bits addressing)

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress | : pointer to NAND address structure
pBuffer | : pointer to destination read buffer. pBuffer should be 16bits aligned
NumPageToRead | : number of pages to read from block
Return values:
HAL status

Definition at line 593 of file stm32h7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_DeviceConfigTypeDef::BlockNbr, NAND_DeviceConfigTypeDef::BlockSize, CMD_AREA, NAND_HandleTypeDef::Config, NAND_DeviceConfigTypeDef::ExtraCommandEnable, HAL_GetTick(), HAL_NAND_Read_Status(), HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_CMD_AREA_A, NAND_CMD_AREA_TRUE1, NAND_DEVICE, NAND_READY, NAND_WRITE_TIMEOUT, NAND_DeviceConfigTypeDef::PageSize, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Read_Page_8b | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint8_t * | pBuffer,
 |  | uint32_t | NumPageToRead
 | ) |  |

Read Page(s) from NAND memory block (8-bits addressing)

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress | : pointer to NAND address structure
pBuffer | : pointer to destination read buffer
NumPageToRead | : number of pages to read from block
Return values:
HAL status

Definition at line 449 of file stm32h7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_DeviceConfigTypeDef::BlockNbr, NAND_DeviceConfigTypeDef::BlockSize, CMD_AREA, NAND_HandleTypeDef::Config, NAND_DeviceConfigTypeDef::ExtraCommandEnable, HAL_GetTick(), HAL_NAND_Read_Status(), HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_CMD_AREA_A, NAND_CMD_AREA_TRUE1, NAND_DEVICE, NAND_READY, NAND_WRITE_TIMEOUT, NAND_DeviceConfigTypeDef::PageSize, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint16_t * | pBuffer,
 |  | uint32_t | NumSpareAreaToRead
 | ) |  |

Read Spare area(s) from NAND memory (16-bits addressing)

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress : pointer to NAND address structure
pBuffer,: pointer to source buffer to write. pBuffer should be 16bits aligned.
NumSpareAreaToRead,: Number of spare area to read
Return values:
HAL status

Definition at line 1160 of file stm32h7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_DeviceConfigTypeDef::BlockNbr, NAND_DeviceConfigTypeDef::BlockSize, CMD_AREA, COLUMN_1ST_CYCLE, COLUMN_2ND_CYCLE, COLUMN_ADDRESS, NAND_HandleTypeDef::Config, NAND_DeviceConfigTypeDef::ExtraCommandEnable, HAL_GetTick(), HAL_NAND_Read_Status(), HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_CMD_AREA_A, NAND_CMD_AREA_C, NAND_CMD_AREA_TRUE1, NAND_DEVICE, NAND_READY, NAND_WRITE_TIMEOUT, NAND_DeviceConfigTypeDef::PageSize, NAND_DeviceConfigTypeDef::SpareAreaSize, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint8_t * | pBuffer,
 |  | uint32_t | NumSpareAreaToRead
 | ) |  |

Read Spare area(s) from NAND memory (8-bits addressing)

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress : pointer to NAND address structure
pBuffer,: pointer to source buffer to write
NumSpareAreaToRead,: Number of spare area to read
Return values:
HAL status

Definition at line 1011 of file stm32h7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_DeviceConfigTypeDef::BlockNbr, NAND_DeviceConfigTypeDef::BlockSize, CMD_AREA, COLUMN_1ST_CYCLE, COLUMN_2ND_CYCLE, COLUMN_ADDRESS, NAND_HandleTypeDef::Config, NAND_DeviceConfigTypeDef::ExtraCommandEnable, HAL_GetTick(), HAL_NAND_Read_Status(), HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_CMD_AREA_A, NAND_CMD_AREA_C, NAND_CMD_AREA_TRUE1, NAND_DEVICE, NAND_READY, NAND_WRITE_TIMEOUT, NAND_DeviceConfigTypeDef::PageSize, NAND_DeviceConfigTypeDef::SpareAreaSize, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Reset ( NAND_HandleTypeDef * hnand )

NAND memory reset.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL status

Definition at line 387 of file stm32h7xx_hal_nand.c.

References CMD_AREA, HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_DEVICE, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Write_Page_16b | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint16_t * | pBuffer,
 |  | uint32_t | NumPageToWrite
 | ) |  |

Write Page(s) to NAND memory block (16-bits addressing)

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress | : pointer to NAND address structure
pBuffer | : pointer to source buffer to write. pBuffer should be 16bits aligned
NumPageToWrite | : number of pages to write to block
Return values:
HAL status

Definition at line 873 of file stm32h7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_DeviceConfigTypeDef::BlockNbr, NAND_DeviceConfigTypeDef::BlockSize, CMD_AREA, NAND_HandleTypeDef::Config, HAL_GetTick(), HAL_NAND_Read_Status(), HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_CMD_AREA_A, NAND_CMD_WRITE0, NAND_CMD_WRITE_TRUE1, NAND_DEVICE, NAND_READY, NAND_WRITE_TIMEOUT, NAND_DeviceConfigTypeDef::PageSize, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Write_Page_8b | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint8_t * | pBuffer,
 |  | uint32_t | NumPageToWrite
 | ) |  |

Write Page(s) to NAND memory block (8-bits addressing)

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress | : pointer to NAND address structure
pBuffer | : pointer to source buffer to write
NumPageToWrite | : number of pages to write to block
Return values:
HAL status

Definition at line 735 of file stm32h7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_DeviceConfigTypeDef::BlockNbr, NAND_DeviceConfigTypeDef::BlockSize, CMD_AREA, NAND_HandleTypeDef::Config, HAL_GetTick(), HAL_NAND_Read_Status(), HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_CMD_AREA_A, NAND_CMD_WRITE0, NAND_CMD_WRITE_TRUE1, NAND_DEVICE, NAND_READY, NAND_WRITE_TIMEOUT, NAND_DeviceConfigTypeDef::PageSize, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint16_t * | pBuffer,
 |  | uint32_t | NumSpareAreaTowrite
 | ) |  |

Write Spare area(s) to NAND memory (16-bits addressing)

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress | : pointer to NAND address structure
pBuffer | : pointer to source buffer to write. pBuffer should be 16bits aligned.
NumSpareAreaTowrite | : number of spare areas to write to block
Return values:
HAL status

Definition at line 1456 of file stm32h7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_DeviceConfigTypeDef::BlockNbr, NAND_DeviceConfigTypeDef::BlockSize, CMD_AREA, COLUMN_1ST_CYCLE, COLUMN_2ND_CYCLE, COLUMN_ADDRESS, NAND_HandleTypeDef::Config, HAL_GetTick(), HAL_NAND_Read_Status(), HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_CMD_AREA_A, NAND_CMD_AREA_C, NAND_CMD_WRITE0, NAND_CMD_WRITE_TRUE1, NAND_DEVICE, NAND_READY, NAND_WRITE_TIMEOUT, NAND_DeviceConfigTypeDef::PageSize, NAND_DeviceConfigTypeDef::SpareAreaSize, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint8_t * | pBuffer,
 |  | uint32_t | NumSpareAreaTowrite
 | ) |  |

Write Spare area(s) to NAND memory (8-bits addressing)

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress | : pointer to NAND address structure
pBuffer | : pointer to source buffer to write
NumSpareAreaTowrite | : number of spare areas to write to block
Return values:
HAL status

Definition at line 1309 of file stm32h7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_DeviceConfigTypeDef::BlockNbr, NAND_DeviceConfigTypeDef::BlockSize, CMD_AREA, COLUMN_1ST_CYCLE, COLUMN_2ND_CYCLE, COLUMN_ADDRESS, NAND_HandleTypeDef::Config, HAL_GetTick(), HAL_NAND_Read_Status(), HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_CMD_AREA_A, NAND_CMD_AREA_C, NAND_CMD_WRITE0, NAND_CMD_WRITE_TRUE1, NAND_DEVICE, NAND_READY, NAND_WRITE_TIMEOUT, NAND_DeviceConfigTypeDef::PageSize, NAND_DeviceConfigTypeDef::SpareAreaSize, and NAND_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
NAND Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_NAND_ECC_Enable (NAND_HandleTypeDef *hnand)
Enables dynamically NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_ECC_Disable (NAND_HandleTypeDef *hnand)
Disables dynamically FMC_NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_GetECC (NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
Disables dynamically NAND ECC feature.

Detailed Description

management functions

  ==============================================================================
                         ##### NAND Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control dynamically
    the NAND interface.

Function Documentation

HAL_StatusTypeDef HAL_NAND_ECC_Disable ( NAND_HandleTypeDef * hnand )

Disables dynamically FMC_NAND ECC feature.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL status

Definition at line 1730 of file stm32h7xx_hal_nand.c.

References HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_HandleTypeDef::Init, NAND_HandleTypeDef::Instance, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_ECC_Enable ( NAND_HandleTypeDef * hnand )

Enables dynamically NAND ECC feature.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL status

Definition at line 1704 of file stm32h7xx_hal_nand.c.

References HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_HandleTypeDef::Init, NAND_HandleTypeDef::Instance, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_GetECC | ( | NAND_HandleTypeDef * | hnand,
 |  | uint32_t * | ECCval,
 |  | uint32_t | Timeout
 | ) |  |

Disables dynamically NAND ECC feature.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
ECCval,: pointer to ECC value
Timeout,: maximum timeout to wait
Return values:
HAL status

Definition at line 1758 of file stm32h7xx_hal_nand.c.

References HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_HandleTypeDef::Init, NAND_HandleTypeDef::Instance, and NAND_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
NAND Exported Functions

Peripheral State functions. More...

Functions

HAL_NAND_StateTypeDef | HAL_NAND_GetState (NAND_HandleTypeDef *hnand)
return the NAND state
uint32_t | HAL_NAND_Read_Status (NAND_HandleTypeDef *hnand)
NAND memory read status.

Detailed Description

Peripheral State functions.

  ==============================================================================
                         ##### NAND State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the NAND controller
    and the data flow.

Function Documentation

HAL_NAND_StateTypeDef HAL_NAND_GetState ( NAND_HandleTypeDef * hnand )

return the NAND state

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL state

Definition at line 1806 of file stm32h7xx_hal_nand.c.

References NAND_HandleTypeDef::State.

uint32_t HAL_NAND_Read_Status ( NAND_HandleTypeDef * hnand )

NAND memory read status.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
NAND status

Definition at line 1817 of file stm32h7xx_hal_nand.c.

References CMD_AREA, NAND_BUSY, NAND_CMD_STATUS, NAND_DEVICE, NAND_ERROR, and NAND_READY.

Referenced by HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: NAND Exported Types

Data Structures | Enumerations
NAND Exported Types
NAND

Data Structures

struct | NAND_IDTypeDef
NAND Memory electronic signature Structure definition. More...
struct | NAND_AddressTypeDef
NAND Memory address Structure definition. More...
struct | NAND_DeviceConfigTypeDef
NAND Memory info Structure definition. More...
struct | NAND_HandleTypeDef
NAND handle Structure definition. More...

Enumerations

enum | HAL_NAND_StateTypeDef { HAL_NAND_STATE_RESET = 0x00U, HAL_NAND_STATE_READY = 0x01U, HAL_NAND_STATE_BUSY = 0x02U, HAL_NAND_STATE_ERROR = 0x03U }
HAL NAND State structures definition. More...

Enumeration Type Documentation

enum HAL_NAND_StateTypeDef

HAL NAND State structures definition.

Enumerator:
HAL_NAND_STATE_RESET

NAND not yet initialized or disabled

HAL_NAND_STATE_READY

NAND initialized and ready for use

HAL_NAND_STATE_BUSY

NAND internal process is ongoing

HAL_NAND_STATE_ERROR

NAND error state

Definition at line 66 of file stm32h7xx_hal_nand.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: NAND_IDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NAND_IDTypeDef Struct Reference
NAND Exported Types

NAND Memory electronic signature Structure definition. More...

#include <stm32h7xx_hal_nand.h>

Data Fields

uint8_t | Maker_Id
uint8_t | Device_Id
uint8_t | Third_Id
uint8_t | Fourth_Id

Detailed Description

NAND Memory electronic signature Structure definition.

Definition at line 77 of file stm32h7xx_hal_nand.h.

Field Documentation

uint8_t NAND_IDTypeDef::Device_Id

Definition at line 83 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

uint8_t NAND_IDTypeDef::Fourth_Id

Definition at line 87 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

uint8_t NAND_IDTypeDef::Maker_Id

Definition at line 81 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

uint8_t NAND_IDTypeDef::Third_Id

Definition at line 85 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_nand.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: NAND_AddressTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NAND_AddressTypeDef Struct Reference
NAND Exported Types

NAND Memory address Structure definition. More...

#include <stm32h7xx_hal_nand.h>

Data Fields

uint16_t | Page
uint16_t | Plane
uint16_t | Block

Detailed Description

NAND Memory address Structure definition.

Definition at line 93 of file stm32h7xx_hal_nand.h.

Field Documentation

uint16_t NAND_AddressTypeDef::Block

NAND memory Block address

Definition at line 99 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc().

uint16_t NAND_AddressTypeDef::Page

NAND memory Page address

Definition at line 95 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc().

uint16_t NAND_AddressTypeDef::Plane

NAND memory Zone address

Definition at line 97 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_nand.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: NAND_DeviceConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NAND_DeviceConfigTypeDef Struct Reference
NAND Exported Types

NAND Memory info Structure definition. More...

#include <stm32h7xx_hal_nand.h>

Data Fields

uint32_t | PageSize
uint32_t | SpareAreaSize
uint32_t | BlockSize
uint32_t | BlockNbr
uint32_t | PlaneNbr
uint32_t | PlaneSize
FunctionalState | ExtraCommandEnable

Detailed Description

NAND Memory info Structure definition.

Definition at line 106 of file stm32h7xx_hal_nand.h.

Field Documentation

uint32_t NAND_DeviceConfigTypeDef::BlockNbr

NAND memory number of total blocks

Definition at line 116 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc(), HAL_NAND_ConfigDevice(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

uint32_t NAND_DeviceConfigTypeDef::BlockSize

NAND memory block size measured in number of pages

Definition at line 114 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc(), HAL_NAND_ConfigDevice(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

FunctionalState NAND_DeviceConfigTypeDef::ExtraCommandEnable

NAND extra command needed for Page reading mode. This parameter is mandatory for some NAND parts after the read command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. Example: Toshiba THTH58BYG3S0HBAI6. This parameter could be ENABLE or DISABLE Please check the Read Mode sequnece in the NAND device datasheet

Definition at line 122 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_ConfigDevice(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), and HAL_NAND_Read_SpareArea_8b().

uint32_t NAND_DeviceConfigTypeDef::PageSize

NAND memory page (without spare area) size measured in bytes for 8 bits adressing or words for 16 bits addressing

Definition at line 108 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_ConfigDevice(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

uint32_t NAND_DeviceConfigTypeDef::PlaneNbr

NAND memory number of planes

Definition at line 118 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_ConfigDevice().

uint32_t NAND_DeviceConfigTypeDef::PlaneSize

NAND memory zone size measured in number of blocks

Definition at line 120 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc(), and HAL_NAND_ConfigDevice().

uint32_t NAND_DeviceConfigTypeDef::SpareAreaSize

NAND memory spare area size measured in bytes for 8 bits adressing or words for 16 bits addressing

Definition at line 111 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_ConfigDevice(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_nand.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: NAND_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NAND_HandleTypeDef Struct Reference
NAND Exported Types

NAND handle Structure definition. More...

#include <stm32h7xx_hal_nand.h>

Data Fields

FMC_NAND_TypeDef * | Instance
FMC_NAND_InitTypeDef | Init
HAL_LockTypeDef | Lock
__IO HAL_NAND_StateTypeDef | State
NAND_DeviceConfigTypeDef Config

Detailed Description

NAND handle Structure definition.

Definition at line 133 of file stm32h7xx_hal_nand.h.

Field Documentation

NAND_DeviceConfigTypeDef NAND_HandleTypeDef::Config

NAND phusical characteristic information structure

Definition at line 143 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc(), HAL_NAND_ConfigDevice(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

FMC_NAND_InitTypeDef NAND_HandleTypeDef::Init

NAND device control configuration parameters

Definition at line 137 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_DeInit(), HAL_NAND_ECC_Disable(), HAL_NAND_ECC_Enable(), HAL_NAND_GetECC(), HAL_NAND_Init(), HAL_NAND_IRQHandler(), and HAL_NAND_Read_ID().

FMC_NAND_TypeDef* NAND_HandleTypeDef::Instance

Register base address

Definition at line 135 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_DeInit(), HAL_NAND_ECC_Disable(), HAL_NAND_ECC_Enable(), HAL_NAND_GetECC(), HAL_NAND_Init(), and HAL_NAND_IRQHandler().

HAL_LockTypeDef NAND_HandleTypeDef::Lock

NAND locking object

Definition at line 139 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Init().

__IO HAL_NAND_StateTypeDef NAND_HandleTypeDef::State

NAND device access state

Definition at line 141 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_DeInit(), HAL_NAND_ECC_Disable(), HAL_NAND_ECC_Enable(), HAL_NAND_Erase_Block(), HAL_NAND_GetECC(), HAL_NAND_GetState(), HAL_NAND_Init(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Reset(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_nand.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: NAND Exported Macros

Defines
NAND Exported Macros
NAND

Defines

#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
Reset NAND handle state.

Define Documentation

#define __HAL_NAND_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)

Reset NAND handle state.

Parameters:
__HANDLE__,: specifies the NAND handle.
Return values:
None

Definition at line 160 of file stm32h7xx_hal_nand.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: NAND Private Constants

Defines
NAND Private Constants
NAND

Defines

#define | NAND_DEVICE ((uint32_t)0x80000000U)
#define | NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)
#define | CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
#define | ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
#define | NAND_CMD_AREA_A ((uint8_t)0x00U)
#define | NAND_CMD_AREA_B ((uint8_t)0x01U)
#define | NAND_CMD_AREA_C ((uint8_t)0x50U)
#define | NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
#define | NAND_CMD_WRITE0 ((uint8_t)0x80U)
#define | NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
#define | NAND_CMD_ERASE0 ((uint8_t)0x60U)
#define | NAND_CMD_ERASE1 ((uint8_t)0xD0U)
#define | NAND_CMD_READID ((uint8_t)0x90U)
#define | NAND_CMD_STATUS ((uint8_t)0x70U)
#define | NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
#define | NAND_CMD_RESET ((uint8_t)0xFFU)
#define | NAND_VALID_ADDRESS ((uint32_t)0x00000100U)
#define | NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)
#define | NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)
#define | NAND_BUSY ((uint32_t)0x00000000U)
#define | NAND_ERROR ((uint32_t)0x00000001U)
#define | NAND_READY ((uint32_t)0x00000040U)

Define Documentation

#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */

Definition at line 253 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */

Definition at line 252 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Read_Status(), HAL_NAND_Reset(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define NAND_BUSY ((uint32_t)0x00000000U)

Definition at line 273 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_Status().

#define NAND_CMD_AREA_A ((uint8_t)0x00U)

Definition at line 255 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define NAND_CMD_AREA_B ((uint8_t)0x01U)

Definition at line 256 of file stm32h7xx_hal_nand.h.

#define NAND_CMD_AREA_C ((uint8_t)0x50U)

Definition at line 257 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)

Definition at line 258 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), and HAL_NAND_Read_SpareArea_8b().

#define NAND_CMD_ERASE0 ((uint8_t)0x60U)

Definition at line 262 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block().

#define NAND_CMD_ERASE1 ((uint8_t)0xD0U)

Definition at line 263 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block().

#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)

Definition at line 266 of file stm32h7xx_hal_nand.h.

#define NAND_CMD_READID ((uint8_t)0x90U)

Definition at line 264 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

#define NAND_CMD_RESET ((uint8_t)0xFFU)

Definition at line 267 of file stm32h7xx_hal_nand.h.

#define NAND_CMD_STATUS ((uint8_t)0x70U)

Definition at line 265 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_Status().

#define NAND_CMD_WRITE0 ((uint8_t)0x80U)

Definition at line 260 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)

Definition at line 261 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define NAND_DEVICE ((uint32_t)0x80000000U)

Definition at line 249 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Read_Status(), HAL_NAND_Reset(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define NAND_ERROR ((uint32_t)0x00000001U)

Definition at line 274 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_Status().

#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)

Definition at line 271 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc().

#define NAND_READY ((uint32_t)0x00000040U)

Definition at line 275 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Read_Status(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)

Definition at line 272 of file stm32h7xx_hal_nand.h.

#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U)

Definition at line 270 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc().

#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)

Definition at line 250 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: NAND Private Macros

Defines
NAND Private Macros
NAND

Defines

#define | ARRAY_ADDRESS(__ADDRESS__, __HANDLE__)
NAND memory address computation.
#define | COLUMN_ADDRESS(__HANDLE__) ((__HANDLE__)->Config.PageSize)
#define | ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
NAND memory address cycling.
#define | ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
#define | ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
#define | ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
#define | COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
NAND memory Columns cycling.
#define | COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */

Define Documentation

#define ADDR_1ST_CYCLE ( __ADDRESS__ ) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */

NAND memory address cycling.

Parameters:
__ADDRESS__,: NAND memory address.
Return values:
NAND address cycling value.

Definition at line 301 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define ADDR_2ND_CYCLE ( __ADDRESS__ ) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */

Definition at line 302 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define ADDR_3RD_CYCLE ( __ADDRESS__ ) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */

Definition at line 303 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define ADDR_4TH_CYCLE ( __ADDRESS__ ) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */

Definition at line 304 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

#define ARRAY_ADDRESS | ( | __ADDRESS__,
 |  | __HANDLE__
 | ) |
Value:
((__ADDRESS__)->Page + \
                         (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))

NAND memory address computation.

Parameters:
__ADDRESS__,: NAND memory address.
__HANDLE__ : NAND handle.
Return values:
NAND Raw address value

Definition at line 291 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_Page_8b(), HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define COLUMN_1ST_CYCLE ( __ADDRESS__ ) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */

NAND memory Columns cycling.

Parameters:
__ADDRESS__,: NAND memory address.
Return values:
NAND Column address cycling value.

Definition at line 311 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define COLUMN_2ND_CYCLE ( __ADDRESS__ ) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */

Definition at line 312 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

#define COLUMN_ADDRESS ( __HANDLE__ ) ((__HANDLE__)->Config.PageSize)

Definition at line 294 of file stm32h7xx_hal_nand.h.

Referenced by HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_SpareArea_16b(), and HAL_NAND_Write_SpareArea_8b().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: NOR Private Defines

Defines
NOR Private Defines
NOR

Defines

#define | NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
#define | NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
#define | NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
#define | NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
#define | NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
#define | NOR_CMD_DATA_FIRST (uint16_t)0x00AA
#define | NOR_CMD_DATA_SECOND (uint16_t)0x0055
#define | NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
#define | NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
#define | NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
#define | NOR_CMD_DATA_CFI (uint16_t)0x0098
#define | NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
#define | NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
#define | NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
#define | NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
#define | NOR_MASK_STATUS_DQ6 (uint16_t)0x0040

Define Documentation

#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA

Definition at line 111 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), and HAL_NOR_Erase_Chip().

#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555

Definition at line 106 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055

Definition at line 107 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Read_CFI().

#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555

Definition at line 110 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), and HAL_NOR_Erase_Chip().

#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA

Definition at line 108 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555

Definition at line 112 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Chip().

#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555

Definition at line 109 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_Read(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090

Definition at line 118 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Read_ID().

#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30

Definition at line 128 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block().

#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25

Definition at line 126 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_ProgramBuffer().

#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29

Definition at line 127 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_ProgramBuffer().

#define NOR_CMD_DATA_CFI (uint16_t)0x0098

Definition at line 124 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Read_CFI().

#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055

Definition at line 122 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), and HAL_NOR_Erase_Chip().

#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA

Definition at line 121 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), and HAL_NOR_Erase_Chip().

#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080

Definition at line 120 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), and HAL_NOR_Erase_Chip().

#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010

Definition at line 123 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Chip().

#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA

Definition at line 116 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0

Definition at line 119 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Program().

#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0

Definition at line 115 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Read(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

#define NOR_CMD_DATA_SECOND (uint16_t)0x0055

Definition at line 117 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020

Definition at line 131 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_GetStatus().

#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040

Definition at line 132 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_GetStatus().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: NOR Private Variables

Variables
NOR Private Variables
NOR

Variables

static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B

Variable Documentation

uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B [static]

Definition at line 144 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Init(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
NOR Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_NOR_Init (NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Perform the NOR memory Initialization sequence.
HAL_StatusTypeDef | HAL_NOR_DeInit (NOR_HandleTypeDef *hnor)
Perform NOR memory De-Initialization sequence.
__weak void | HAL_NOR_MspInit (NOR_HandleTypeDef *hnor)
NOR MSP Init.
__weak void | HAL_NOR_MspDeInit (NOR_HandleTypeDef *hnor)
NOR MSP DeInit.
__weak void | HAL_NOR_MspWait (NOR_HandleTypeDef *hnor, uint32_t Timeout)
NOR MSP Wait for Ready/Busy signal.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
           ##### NOR Initialization and de_initialization functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to initialize/de-initialize
    the NOR memory

Function Documentation

HAL_StatusTypeDef HAL_NOR_DeInit ( NOR_HandleTypeDef * hnor )

Perform NOR memory De-Initialization sequence.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
HAL status

Definition at line 232 of file stm32h7xx_hal_nor.c.

References NOR_HandleTypeDef::Extended, HAL_NOR_MspDeInit(), HAL_NOR_STATE_RESET, NOR_HandleTypeDef::Init, NOR_HandleTypeDef::Instance, and NOR_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NOR_Init | ( | NOR_HandleTypeDef * | hnor,
 |  | FMC_NORSRAM_TimingTypeDef * | Timing,
 |  | FMC_NORSRAM_TimingTypeDef * | ExtTiming
 | ) |  |

Perform the NOR memory Initialization sequence.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Timing,: pointer to NOR control timing structure
ExtTiming,: pointer to NOR extended mode timing structure
Return values:
HAL status

Definition at line 179 of file stm32h7xx_hal_nor.c.

References NOR_HandleTypeDef::Extended, HAL_NOR_MspInit(), HAL_NOR_STATE_READY, HAL_NOR_STATE_RESET, NOR_HandleTypeDef::Init, NOR_HandleTypeDef::Instance, NOR_HandleTypeDef::Lock, NOR_MEMORY_16B, NOR_MEMORY_8B, NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

void HAL_NOR_MspDeInit ( NOR_HandleTypeDef * hnor )

NOR MSP DeInit.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
None

Definition at line 271 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_DeInit().

void HAL_NOR_MspInit ( NOR_HandleTypeDef * hnor )

NOR MSP Init.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
None

Definition at line 255 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_Init().

void HAL_NOR_MspWait | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | Timeout
 | ) |  |

NOR MSP Wait for Ready/Busy signal.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Timeout,: Maximum timeout value
Return values:
None

Definition at line 288 of file stm32h7xx_hal_nor.c.

Referenced by HAL_NOR_GetStatus().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Input and Output functions

Functions
Input and Output functions
NOR Exported Functions

Input Output and memory control functions. More...

Functions

HAL_StatusTypeDef | HAL_NOR_Read_ID (NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
Read NOR flash IDs.
HAL_StatusTypeDef | HAL_NOR_ReturnToReadMode (NOR_HandleTypeDef *hnor)
Returns the NOR memory to Read mode.
HAL_StatusTypeDef | HAL_NOR_Read (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Read data from NOR memory.
HAL_StatusTypeDef | HAL_NOR_Program (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Program data to NOR memory.
HAL_StatusTypeDef | HAL_NOR_ReadBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Reads a half-word buffer from the NOR memory.
HAL_StatusTypeDef | HAL_NOR_ProgramBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Writes a half-word buffer to the NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Block (NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
Erase the specified block of the NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Chip (NOR_HandleTypeDef *hnor, uint32_t Address)
Erase the entire NOR chip.
HAL_StatusTypeDef | HAL_NOR_Read_CFI (NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
Read NOR flash CFI IDs.

Detailed Description

Input Output and memory control functions.

  ==============================================================================
                ##### NOR Input and Output functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to use and control the NOR memory

Function Documentation

HAL_StatusTypeDef HAL_NOR_Erase_Block | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | BlockAddress,
 |  | uint32_t | Address
 | ) |  |

Erase the specified block of the NOR memory.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
BlockAddress : Block to erase address
Address,: Device address
Return values:
HAL status

Definition at line 698 of file stm32h7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIFTH, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_FOURTH, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_BLOCK_ERASE, NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH, NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH, NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_SECOND, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_Erase_Chip | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | Address
 | ) |  |

Erase the entire NOR chip.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Address : Device address
Return values:
HAL status

Definition at line 757 of file stm32h7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIFTH, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_FOURTH, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_SIXTH, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH, NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH, NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD, NOR_CMD_DATA_CHIP_ERASE, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_SECOND, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_Program | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pData
 | ) |  |

Program data to NOR memory.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
pAddress,: Device address
pData : pointer to the data to write
Return values:
HAL status

Definition at line 493 of file stm32h7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_PROGRAM, NOR_CMD_DATA_SECOND, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_ProgramBuffer | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | uwAddress,
 |  | uint16_t * | pData,
 |  | uint32_t | uwBufferSize
 | ) |  |

Writes a half-word buffer to the NOR memory.

This function must be used only with S29GL128P NOR memory.

Parameters:
hnor,: pointer to the NOR handle
uwAddress,: NOR memory internal start write address
pData,: pointer to source data buffer.
uwBufferSize,: Size of the buffer to write
Return values:
HAL status

Definition at line 618 of file stm32h7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_SECOND, NOR_CMD_DATA_BUFFER_AND_PROG, NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_SECOND, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_Read | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pData
 | ) |  |

Read data from NOR memory.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
pAddress,: pointer to Device address
pData : pointer to read data
Return values:
HAL status

Definition at line 434 of file stm32h7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_READ_RESET, NOR_CMD_DATA_SECOND, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_Read_CFI | ( | NOR_HandleTypeDef * | hnor,
 |  | NOR_CFITypeDef * | pNOR_CFI
 | ) |  |

Read NOR flash CFI IDs.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
pNOR_CFI : pointer to NOR CFI IDs structure
Return values:
HAL status

Definition at line 815 of file stm32h7xx_hal_nor.c.

References CFI1_ADDRESS, CFI2_ADDRESS, CFI3_ADDRESS, CFI4_ADDRESS, NOR_CFITypeDef::CFI_1, NOR_CFITypeDef::CFI_2, NOR_CFITypeDef::CFI_3, NOR_CFITypeDef::CFI_4, HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST_CFI, NOR_CMD_DATA_CFI, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_Read_ID | ( | NOR_HandleTypeDef * | hnor,
 |  | NOR_IDTypeDef * | pNOR_ID
 | ) |  |

Read NOR flash IDs.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
pNOR_ID : pointer to NOR ID structure
Return values:
HAL status

Definition at line 324 of file stm32h7xx_hal_nor.c.

References NOR_IDTypeDef::Device_Code1, DEVICE_CODE1_ADDR, NOR_IDTypeDef::Device_Code2, DEVICE_CODE2_ADDR, NOR_IDTypeDef::Device_Code3, DEVICE_CODE3_ADDR, HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_IDTypeDef::Manufacturer_Code, MC_ADDRESS, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_AUTO_SELECT, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_SECOND, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_ReadBuffer | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | uwAddress,
 |  | uint16_t * | pData,
 |  | uint32_t | uwBufferSize
 | ) |  |

Reads a half-word buffer from the NOR memory.

Parameters:
hnor,: pointer to the NOR handle
uwAddress,: NOR memory internal address to read from.
pData,: pointer to the buffer that receives the data read from the NOR memory.
uwBufferSize : number of Half word to read.
Return values:
HAL status

Definition at line 553 of file stm32h7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_READ_RESET, NOR_CMD_DATA_SECOND, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_ReturnToReadMode ( NOR_HandleTypeDef * hnor )

Returns the NOR memory to Read mode.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
HAL status

Definition at line 384 of file stm32h7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_CMD_DATA_READ_RESET, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, and NOR_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: NOR Control functions

Functions
NOR Control functions
NOR Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_NOR_WriteOperation_Enable (NOR_HandleTypeDef *hnor)
Enables dynamically NOR write operation.
HAL_StatusTypeDef | HAL_NOR_WriteOperation_Disable (NOR_HandleTypeDef *hnor)
Disables dynamically NOR write operation.

Detailed Description

management functions

  ==============================================================================
                        ##### NOR Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control dynamically
    the NOR interface.

Function Documentation

HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable ( NOR_HandleTypeDef * hnor )

Disables dynamically NOR write operation.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
HAL status

Definition at line 915 of file stm32h7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_PROTECTED, NOR_HandleTypeDef::Init, NOR_HandleTypeDef::Instance, and NOR_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable ( NOR_HandleTypeDef * hnor )

Enables dynamically NOR write operation.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
HAL status

Definition at line 892 of file stm32h7xx_hal_nor.c.

References HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_HandleTypeDef::Instance, and NOR_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: NOR State functions

Functions
NOR State functions
NOR Exported Functions

Peripheral State functions. More...

Functions

HAL_NOR_StateTypeDef | HAL_NOR_GetState (NOR_HandleTypeDef *hnor)
return the NOR controller state
HAL_NOR_StatusTypeDef | HAL_NOR_GetStatus (NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
Returns the NOR operation status.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### NOR State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the NOR controller
    and the data flow.

Function Documentation

HAL_NOR_StateTypeDef HAL_NOR_GetState ( NOR_HandleTypeDef * hnor )

return the NOR controller state

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
NOR controller state

Definition at line 960 of file stm32h7xx_hal_nor.c.

References NOR_HandleTypeDef::State.

HAL_NOR_StatusTypeDef HAL_NOR_GetStatus | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | Address,
 |  | uint32_t | Timeout
 | ) |  |

Returns the NOR operation status.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Address,: Device address
Timeout,: NOR programming Timeout
Return values:
NOR_Status,: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR or HAL_NOR_STATUS_TIMEOUT

Definition at line 974 of file stm32h7xx_hal_nor.c.

References HAL_GetTick(), HAL_NOR_MspWait(), HAL_NOR_STATUS_ERROR, HAL_NOR_STATUS_ONGOING, HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_TIMEOUT, NOR_MASK_STATUS_DQ5, and NOR_MASK_STATUS_DQ6.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: NOR Exported Types

Data Structures | Enumerations
NOR Exported Types
NOR

Data Structures

struct | NOR_IDTypeDef
FMC NOR ID typedef. More...
struct | NOR_CFITypeDef
FMC NOR CFI typedef. More...
struct | NOR_HandleTypeDef
NOR handle Structure definition. More...

Enumerations

enum HAL_NOR_StateTypeDef {
HAL_NOR_STATE_RESET = 0x00U, HAL_NOR_STATE_READY = 0x01U, HAL_NOR_STATE_BUSY = 0x02U, HAL_NOR_STATE_ERROR = 0x03U,
HAL_NOR_STATE_PROTECTED = 0x04U
}
HAL SRAM State structures definition. More...
enum | HAL_NOR_StatusTypeDef { HAL_NOR_STATUS_SUCCESS = 0U, HAL_NOR_STATUS_ONGOING, HAL_NOR_STATUS_ERROR, HAL_NOR_STATUS_TIMEOUT }
FMC NOR Status typedef. More...

Enumeration Type Documentation

enum HAL_NOR_StateTypeDef

HAL SRAM State structures definition.

Enumerator:
HAL_NOR_STATE_RESET

NOR not yet initialized or disabled

HAL_NOR_STATE_READY

NOR initialized and ready for use

HAL_NOR_STATE_BUSY

NOR internal processing is ongoing

HAL_NOR_STATE_ERROR

NOR error state

HAL_NOR_STATE_PROTECTED

NOR NORSRAM device write protected

Definition at line 66 of file stm32h7xx_hal_nor.h.

enum HAL_NOR_StatusTypeDef

FMC NOR Status typedef.

Enumerator:
HAL_NOR_STATUS_SUCCESS
HAL_NOR_STATUS_ONGOING
HAL_NOR_STATUS_ERROR
HAL_NOR_STATUS_TIMEOUT

Definition at line 78 of file stm32h7xx_hal_nor.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: NOR_IDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NOR_IDTypeDef Struct Reference
NOR Exported Types

FMC NOR ID typedef. More...

#include <stm32h7xx_hal_nor.h>

Data Fields

uint16_t | Manufacturer_Code
uint16_t | Device_Code1
uint16_t | Device_Code2
uint16_t | Device_Code3

Detailed Description

FMC NOR ID typedef.

Definition at line 89 of file stm32h7xx_hal_nor.h.

Field Documentation

uint16_t NOR_IDTypeDef::Device_Code1

Definition at line 93 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

uint16_t NOR_IDTypeDef::Device_Code2

Definition at line 95 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

uint16_t NOR_IDTypeDef::Device_Code3

Defines the device's codes used to identify the memory. These codes can be accessed by performing read operations with specific control signals and addresses set.They can also be accessed by issuing an Auto Select command.

Definition at line 97 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

uint16_t NOR_IDTypeDef::Manufacturer_Code

Defines the device's manufacturer code used to identify the memory.

Definition at line 91 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_nor.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: NOR_CFITypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NOR_CFITypeDef Struct Reference
NOR Exported Types

FMC NOR CFI typedef. More...

#include <stm32h7xx_hal_nor.h>

Data Fields

uint16_t | CFI_1
uint16_t | CFI_2
uint16_t | CFI_3
uint16_t | CFI_4

Detailed Description

FMC NOR CFI typedef.

Definition at line 106 of file stm32h7xx_hal_nor.h.

Field Documentation

uint16_t NOR_CFITypeDef::CFI_1

< Defines the information stored in the memory's Common flash interface which contains a description of various electrical and timing parameters, density information and functions supported by the memory

Definition at line 112 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

uint16_t NOR_CFITypeDef::CFI_2

Definition at line 114 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

uint16_t NOR_CFITypeDef::CFI_3

Definition at line 116 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

uint16_t NOR_CFITypeDef::CFI_4

Definition at line 118 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_nor.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: NOR_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NOR_HandleTypeDef Struct Reference
NOR Exported Types

NOR handle Structure definition. More...

#include <stm32h7xx_hal_nor.h>

Data Fields

FMC_NORSRAM_TypeDef * | Instance
FMC_NORSRAM_EXTENDED_TypeDef * | Extended
FMC_NORSRAM_InitTypeDef | Init
HAL_LockTypeDef | Lock
__IO HAL_NOR_StateTypeDef | State

Detailed Description

NOR handle Structure definition.

Definition at line 124 of file stm32h7xx_hal_nor.h.

Field Documentation

FMC_NORSRAM_EXTENDED_TypeDef* NOR_HandleTypeDef::Extended

Extended mode register base address

Definition at line 128 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_DeInit(), and HAL_NOR_Init().

FMC_NORSRAM_InitTypeDef NOR_HandleTypeDef::Init

NOR device control configuration parameters

Definition at line 130 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_DeInit(), HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Init(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), HAL_NOR_ReturnToReadMode(), HAL_NOR_WriteOperation_Disable(), and HAL_NOR_WriteOperation_Enable().

FMC_NORSRAM_TypeDef* NOR_HandleTypeDef::Instance

Register base address

Definition at line 126 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_DeInit(), HAL_NOR_Init(), HAL_NOR_WriteOperation_Disable(), and HAL_NOR_WriteOperation_Enable().

HAL_LockTypeDef NOR_HandleTypeDef::Lock

NOR locking object

Definition at line 132 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Init().

__IO HAL_NOR_StateTypeDef NOR_HandleTypeDef::State

NOR device access state

Definition at line 134 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_DeInit(), HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_GetState(), HAL_NOR_Init(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), HAL_NOR_ReturnToReadMode(), HAL_NOR_WriteOperation_Disable(), and HAL_NOR_WriteOperation_Enable().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_nor.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: NOR Exported Macros

Defines
NOR Exported Macros
NOR

Defines

#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
Reset NOR handle state.

Define Documentation

#define __HAL_NOR_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)

Reset NOR handle state.

Parameters:
__HANDLE__,: specifies the NOR handle.
Return values:
None

Definition at line 150 of file stm32h7xx_hal_nor.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: NOR Private Constants

Defines
NOR Private Constants
NOR

Defines

#define | MC_ADDRESS ((uint16_t)0x0000U)
#define | DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
#define | DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
#define | DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
#define | CFI1_ADDRESS ((uint16_t)0x61U)
#define | CFI2_ADDRESS ((uint16_t)0x62U)
#define | CFI3_ADDRESS ((uint16_t)0x63U)
#define | CFI4_ADDRESS ((uint16_t)0x64U)
#define | NOR_TMEOUT ((uint16_t)0xFFFFU)
#define | NOR_MEMORY_8B ((uint8_t)0x0U)
#define | NOR_MEMORY_16B ((uint8_t)0x1U)
#define | NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)
#define | NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)
#define | NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)
#define | NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)

Define Documentation

#define CFI1_ADDRESS ((uint16_t)0x61U)

Definition at line 233 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

#define CFI2_ADDRESS ((uint16_t)0x62U)

Definition at line 234 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

#define CFI3_ADDRESS ((uint16_t)0x63U)

Definition at line 235 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

#define CFI4_ADDRESS ((uint16_t)0x64U)

Definition at line 236 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)

Definition at line 228 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)

Definition at line 229 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)

Definition at line 230 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

#define MC_ADDRESS ((uint16_t)0x0000U)

Definition at line 227 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

#define NOR_MEMORY_16B ((uint8_t)0x1U)

Definition at line 243 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Init().

#define NOR_MEMORY_8B ((uint8_t)0x0U)

Definition at line 242 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Init().

#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)

Definition at line 246 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)

Definition at line 247 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)

Definition at line 248 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)

Definition at line 249 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

#define NOR_TMEOUT ((uint16_t)0xFFFFU)

Definition at line 239 of file stm32h7xx_hal_nor.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: NOR Private Macros

Defines
NOR Private Macros
NOR

Defines

#define | NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)
NOR memory address shifting.
#define | NOR_WRITE(__ADDRESS__, __DATA__)
NOR memory write data to specified address.

Define Documentation

#define NOR_ADDR_SHIFT | ( | __NOR_ADDRESS,
 |  | __NOR_MEMORY_WIDTH_,
 |  | __ADDRESS__
 | ) |
Value:
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?              \
              ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))):              \
              ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))

NOR memory address shifting.

Parameters:
__NOR_ADDRESS,: NOR base address
__NOR_MEMORY_WIDTH_,: NOR memory width
__ADDRESS__,: NOR memory address
Return values:
NOR shifted address value

Definition at line 265 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_WRITE | ( | __ADDRESS__,
 |  | __DATA__
 | ) |
Value:
do{                                                             \
                                                 (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
                                                 __DSB();                                                    \
                                               } while(0)

NOR memory write data to specified address.

Parameters:
__ADDRESS__,: NOR memory address
__DATA__,: Data to write
Return values:
None

Definition at line 276 of file stm32h7xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
OPAMP Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_OPAMP_Init (OPAMP_HandleTypeDef *hopamp)
Initialize the OPAMP according to the specified parameters in the OPAMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp)
DeInitialize the OPAMP peripheral.
__weak void | HAL_OPAMP_MspInit (OPAMP_HandleTypeDef *hopamp)
Initialize the OPAMP MSP.
__weak void | HAL_OPAMP_MspDeInit (OPAMP_HandleTypeDef *hopamp)
DeInitialize OPAMP MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================

Function Documentation

HAL_StatusTypeDef HAL_OPAMP_DeInit ( OPAMP_HandleTypeDef * hopamp )

DeInitialize the OPAMP peripheral.

Note:
Deinitialization can be performed if the OPAMP configuration is locked. (the lock is SW in H7)
Parameters:
hopamp,: OPAMP handle
Return values:
HAL status

Definition at line 419 of file stm32h7xx_hal_opamp.c.

References assert_param, HAL_OPAMP_MspDeInit(), HAL_OPAMP_STATE_CALIBBUSY, HAL_OPAMP_STATE_RESET, OPAMP_HandleTypeDef::Instance, OPAMP_CSR_RESET_BITS, OPAMP_CSR_RESET_VALUE, and OPAMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OPAMP_Init ( OPAMP_HandleTypeDef * hopamp )

Initialize the OPAMP according to the specified parameters in the OPAMP_InitTypeDef and initialize the associated handle.

Note:
If the selected opamp is locked, initialization can't be performed. To unlock the configuration, perform a system reset.
Parameters:
hopamp,: OPAMP handle
Return values:
HAL status

Definition at line 284 of file stm32h7xx_hal_opamp.c.

References assert_param, HAL_OPAMP_MspInit(), HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_CALIBBUSY, HAL_OPAMP_STATE_READY, HAL_OPAMP_STATE_RESET, OPAMP_HandleTypeDef::Init, OPAMP_HandleTypeDef::Instance, OPAMP_InitTypeDef::InvertingInput, IS_OPAMP_FUNCTIONAL_NORMALMODE, IS_OPAMP_INVERTING_INPUT_STANDALONE, IS_OPAMP_NONINVERTING_INPUT, IS_OPAMP_PGA_GAIN, IS_OPAMP_PGACONNECT, IS_OPAMP_POWERMODE, IS_OPAMP_TRIMMING, IS_OPAMP_TRIMMINGVALUE, OPAMP_HandleTypeDef::Lock, OPAMP_InitTypeDef::Mode, OPAMP_InitTypeDef::NonInvertingInput, OPAMP_CSR_INIT_MASK_FOLLOWER, OPAMP_CSR_INIT_MASK_PGA, OPAMP_CSR_INIT_MASK_STANDALONE, OPAMP_FOLLOWER_MODE, OPAMP_INPUT_NONINVERTING, OPAMP_PGA_MODE, OPAMP_POWERMODE_HIGHSPEED, OPAMP_POWERMODE_NORMAL, OPAMP_STANDALONE_MODE, OPAMP_TRIMMING_USER, OPAMP_InitTypeDef::PgaConnect, OPAMP_InitTypeDef::PgaGain, OPAMP_InitTypeDef::PowerMode, OPAMP_HandleTypeDef::State, OPAMP_InitTypeDef::TrimmingValueN, OPAMP_InitTypeDef::TrimmingValueNHighSpeed, OPAMP_InitTypeDef::TrimmingValueP, OPAMP_InitTypeDef::TrimmingValuePHighSpeed, and OPAMP_InitTypeDef::UserTrimming.

void HAL_OPAMP_MspDeInit ( OPAMP_HandleTypeDef * hopamp )

DeInitialize OPAMP MSP.

Parameters:
hopamp,: OPAMP handle
Return values:
None

Definition at line 474 of file stm32h7xx_hal_opamp.c.

Referenced by HAL_OPAMP_DeInit().

void HAL_OPAMP_MspInit ( OPAMP_HandleTypeDef * hopamp )

Initialize the OPAMP MSP.

Parameters:
hopamp,: OPAMP handle
Return values:
None

Definition at line 459 of file stm32h7xx_hal_opamp.c.

Referenced by HAL_OPAMP_Init().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
OPAMP Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_OPAMP_Start (OPAMP_HandleTypeDef *hopamp)
Start the OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_Stop (OPAMP_HandleTypeDef *hopamp)
Stop the OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_SelfCalibrate (OPAMP_HandleTypeDef *hopamp)
Run the self calibration of one OPAMP.

Detailed Description

IO operation functions.

 ===============================================================================
                        ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the OPAMP
    start, stop and calibration actions.

Function Documentation

HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate ( OPAMP_HandleTypeDef * hopamp )

Run the self calibration of one OPAMP.

Note:
Calibration is performed in the mode specified in OPAMP init structure (mode normal or high-speed). To perform calibration for both modes, repeat this function twice after OPAMP init structure accordingly updated.
Parameters:
hopamp handle
Return values:
Updated | offset trimming values (PMOS & NMOS), user trimming is enabled
HAL | status

Definition at line 592 of file stm32h7xx_hal_opamp.c.

References assert_param, HAL_Delay(), HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_READY, OPAMP_HandleTypeDef::Init, OPAMP_HandleTypeDef::Instance, IS_OPAMP_POWERMODE, OPAMP_INPUT_NONINVERTING, OPAMP_POWERMODE_HIGHSPEED, OPAMP_POWERMODE_NORMAL, OPAMP_STANDALONE_MODE, OPAMP_TRIMMING_DELAY, OPAMP_TRIMMING_USER, OPAMP_VREF_10VDDA, OPAMP_VREF_90VDDA, OPAMP_InitTypeDef::PowerMode, OPAMP_HandleTypeDef::State, OPAMP_InitTypeDef::TrimmingValueN, OPAMP_InitTypeDef::TrimmingValueNHighSpeed, OPAMP_InitTypeDef::TrimmingValueP, OPAMP_InitTypeDef::TrimmingValuePHighSpeed, and OPAMP_InitTypeDef::UserTrimming.

HAL_StatusTypeDef HAL_OPAMP_Start ( OPAMP_HandleTypeDef * hopamp )

Start the OPAMP.

Parameters:
hopamp,: OPAMP handle
Return values:
HAL status

Definition at line 509 of file stm32h7xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_BUSY, HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_READY, OPAMP_HandleTypeDef::Instance, and OPAMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OPAMP_Stop ( OPAMP_HandleTypeDef * hopamp )

Stop the OPAMP.

Parameters:
hopamp,: OPAMP handle
Return values:
HAL status

Definition at line 547 of file stm32h7xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_BUSY, HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_CALIBBUSY, HAL_OPAMP_STATE_READY, OPAMP_HandleTypeDef::Instance, and OPAMP_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
OPAMP Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_OPAMP_Lock (OPAMP_HandleTypeDef *hopamp)
Lock the selected OPAMP configuration.
HAL_OPAMP_TrimmingValueTypeDef | HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
Return the OPAMP factory trimming value.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the OPAMP data
    transfers.

Function Documentation

HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset | ( | OPAMP_HandleTypeDef * | hopamp,
 |  | uint32_t | trimmingoffset
 | ) |  |

Return the OPAMP factory trimming value.

Note:
On STM32H7 OPAMP, user can retrieve factory trimming if OPAMP has never been set to user trimming before. Therefore, this function must be called when OPAMP init parameter "UserTrimming" is set to trimming factory, and before OPAMP calibration (function "HAL_OPAMP_SelfCalibrate()"). Otherwise, factory trimming value cannot be retrieved and error status is returned.
Parameters:
hopamp | : OPAMP handle
trimmingoffset | : Trimming offset (P or N) This parameter must be a value of OPAMP Factory Trimming
Note:
Calibration parameter retrieved is corresponding to the mode specified in OPAMP init structure (mode normal or high-speed). To retrieve calibration parameters for both modes, repeat this function after OPAMP init structure accordingly updated.
Return values:
Trimming value (P or N): range: 0->31 or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available

Definition at line 873 of file stm32h7xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_BUSY, HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_CALIBBUSY, HAL_OPAMP_STATE_RESET, OPAMP_HandleTypeDef::Init, OPAMP_HandleTypeDef::Instance, IS_OPAMP_FACTORYTRIMMING, IS_OPAMP_POWERMODE, OPAMP_FACTORYTRIMMING_DUMMY, OPAMP_FACTORYTRIMMING_P, OPAMP_INPUT_NONINVERTING, OPAMP_POWERMODE_NORMAL, OPAMP_InitTypeDef::PowerMode, and OPAMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OPAMP_Lock ( OPAMP_HandleTypeDef * hopamp )

Lock the selected OPAMP configuration.

Note:
On STM32H7, HAL OPAMP lock is software lock only (in contrast of hardware lock available on some other STM32 devices)
Parameters:
hopamp,: OPAMP handle
Return values:
HAL status

Definition at line 823 of file stm32h7xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_CALIBBUSY, HAL_OPAMP_STATE_READY, HAL_OPAMP_STATE_RESET, OPAMP_HandleTypeDef::Instance, and OPAMP_HandleTypeDef::State.

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STM32H753xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
OPAMP Exported Functions

Peripheral State functions. More...

Functions

HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState (OPAMP_HandleTypeDef *hopamp)
Return the OPAMP handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState ( OPAMP_HandleTypeDef * hopamp )

Return the OPAMP handle state.

Parameters:
hopamp : OPAMP handle
Return values:
HAL state

Definition at line 956 of file stm32h7xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_RESET, OPAMP_HandleTypeDef::Instance, and OPAMP_HandleTypeDef::State.

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STM32H753xx HAL User Manual: OPAMP Exported Types

Data Structures | Typedefs | Enumerations
OPAMP Exported Types
OPAMP

Data Structures

struct | OPAMP_InitTypeDef
OPAMP Init structure definition. More...
struct | OPAMP_HandleTypeDef
OPAMP Handle Structure definition. More...

Typedefs

typedef uint32_t | HAL_OPAMP_TrimmingValueTypeDef
HAl_OPAMP_TrimmingValueTypeDef definition.

Enumerations

enum HAL_OPAMP_StateTypeDef {
HAL_OPAMP_STATE_RESET = 0x00000000, HAL_OPAMP_STATE_READY = 0x00000001, HAL_OPAMP_STATE_CALIBBUSY = 0x00000002, HAL_OPAMP_STATE_BUSY = 0x00000004,
HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005
}
HAL State structures definition. More...

Typedef Documentation

typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef

HAl_OPAMP_TrimmingValueTypeDef definition.

Definition at line 158 of file stm32h7xx_hal_opamp.h.

Enumeration Type Documentation

enum HAL_OPAMP_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_OPAMP_STATE_RESET

OPAMP is not yet Initialized

HAL_OPAMP_STATE_READY

OPAMP is initialized and ready for use

HAL_OPAMP_STATE_CALIBBUSY

OPAMP is enabled in auto calibration mode

HAL_OPAMP_STATE_BUSY

OPAMP is enabled and running in normal mode

HAL_OPAMP_STATE_BUSYLOCKED

OPAMP is locked only system reset allows reconfiguring the opamp.

Definition at line 128 of file stm32h7xx_hal_opamp.h.

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STM32H753xx HAL User Manual: OPAMP_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
OPAMP_InitTypeDef Struct Reference
OPAMP Exported Types

OPAMP Init structure definition. More...

#include <stm32h7xx_hal_opamp.h>

Data Fields

uint32_t | PowerMode
uint32_t | Mode
uint32_t | InvertingInput
uint32_t | NonInvertingInput
uint32_t | PgaGain
uint32_t | PgaConnect
uint32_t | UserTrimming
uint32_t | TrimmingValueP
uint32_t | TrimmingValueN
uint32_t | TrimmingValuePHighSpeed
uint32_t | TrimmingValueNHighSpeed

Detailed Description

OPAMP Init structure definition.

Definition at line 67 of file stm32h7xx_hal_opamp.h.

Field Documentation

uint32_t OPAMP_InitTypeDef::InvertingInput

Specifies the inverting input in Standalone & PGA modes

  • In Standalone mode i.e when mode is OPAMP_STANDALONE_MODE This parameter must be a value of OPAMP Inverting Input
  • In Follower mode i.e when mode is OPAMP_FOLLOWER_MODE & In PGA mode i.e when mode is OPAMP_PGA_MODE This parameter is Not Applicable

Definition at line 77 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::Mode

Specifies the OPAMP mode This parameter must be a value of OPAMP Mode mode is either Standalone, - Follower or PGA

Definition at line 73 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::NonInvertingInput

Specifies the non inverting input of the opamp: This parameter must be a value of OPAMP Non Inverting Input

Definition at line 84 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::PgaConnect

Specifies the inverting pin in PGA mode i.e. when mode is OPAMP_PGA_MODE This parameter must be a value of OPAMP Pga Connect Either: not connected, connected to VINM0, connected to VINM1 (VINM0 or VINM1 are typically used for external filtering)

Definition at line 91 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::PgaGain

Specifies the gain in PGA mode i.e. when mode is OPAMP_PGA_MODE. This parameter must be a value of OPAMP Pga Gain

Definition at line 87 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::PowerMode

Specifies the power mode Normal or High Speed. This parameter must be a value of OPAMP PowerMode

Definition at line 70 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

uint32_t OPAMP_InitTypeDef::TrimmingValueN

Specifies the offset trimming value (NMOS) in Normal Mode i.e. when UserTrimming is OPAMP_TRIMMING_USER. This parameter must be a number between Min_Data = 0 and Max_Data = 31. 16 is typical default value

Definition at line 107 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

uint32_t OPAMP_InitTypeDef::TrimmingValueNHighSpeed

Specifies the offset trimming value (NMOS) in High Speed Mode i.e. when UserTrimming is OPAMP_TRIMMING_USER. This parameter must be a number between Min_Data = 0 and Max_Data = 31. 16 is typical default value

Definition at line 117 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

uint32_t OPAMP_InitTypeDef::TrimmingValueP

Specifies the offset trimming value (PMOS) in Normal Mode

i.e. when UserTrimming is OPAMP_TRIMMING_USER. This parameter must be a number between Min_Data = 0 and Max_Data = 31. 16 is typical default value

Definition at line 101 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

uint32_t OPAMP_InitTypeDef::TrimmingValuePHighSpeed

Specifies the offset trimming value (PMOS) in High Speed Mode i.e. when UserTrimming is OPAMP_TRIMMING_USER. This parameter must be a number between Min_Data = 0 and Max_Data = 31. 16 is typical default value

Definition at line 112 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

uint32_t OPAMP_InitTypeDef::UserTrimming

Specifies the trimming mode This parameter must be a value of OPAMP User Trimming UserTrimming is either factory or user trimming.

Definition at line 97 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_opamp.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: OPAMP_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
OPAMP_HandleTypeDef Struct Reference
OPAMP Exported Types

OPAMP Handle Structure definition. More...

#include <stm32h7xx_hal_opamp.h>

Data Fields

OPAMP_TypeDef * | Instance
OPAMP_InitTypeDef Init
HAL_StatusTypeDef | Status
HAL_LockTypeDef | Lock
__IO HAL_OPAMP_StateTypeDef | State

Detailed Description

OPAMP Handle Structure definition.

Definition at line 144 of file stm32h7xx_hal_opamp.h.

Field Documentation

OPAMP_InitTypeDef OPAMP_HandleTypeDef::Init

OPAMP required parameters

Definition at line 147 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

OPAMP_TypeDef* OPAMP_HandleTypeDef::Instance

OPAMP instance's registers base address

Definition at line 146 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_DeInit(), HAL_OPAMP_GetState(), HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_Lock(), HAL_OPAMP_SelfCalibrate(), HAL_OPAMP_Start(), HAL_OPAMP_Stop(), HAL_OPAMPEx_SelfCalibrateAll(), and HAL_OPAMPEx_Unlock().

HAL_LockTypeDef OPAMP_HandleTypeDef::Lock

Locking object

Definition at line 149 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

__IO HAL_OPAMP_StateTypeDef OPAMP_HandleTypeDef::State

OPAMP communication state

Definition at line 150 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_DeInit(), HAL_OPAMP_GetState(), HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_Lock(), HAL_OPAMP_SelfCalibrate(), HAL_OPAMP_Start(), HAL_OPAMP_Stop(), HAL_OPAMPEx_SelfCalibrateAll(), and HAL_OPAMPEx_Unlock().

HAL_StatusTypeDef OPAMP_HandleTypeDef::Status

OPAMP peripheral status

Definition at line 148 of file stm32h7xx_hal_opamp.h.

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_opamp.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: OPAMP Mode

Defines
OPAMP Mode
OPAMP Exported Constants

Defines

#define | OPAMP_STANDALONE_MODE ((uint32_t)0x00000000)
#define | OPAMP_PGA_MODE OPAMP_CSR_VMSEL_1
#define | OPAMP_FOLLOWER_MODE (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0)

Define Documentation

#define OPAMP_FOLLOWER_MODE (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0)

follower mode

Definition at line 175 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define OPAMP_PGA_MODE OPAMP_CSR_VMSEL_1

PGA mode

Definition at line 174 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define OPAMP_STANDALONE_MODE ((uint32_t)0x00000000)

standalone mode

Definition at line 173 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: OPAMP Non Inverting Input

Defines
OPAMP Non Inverting Input
OPAMP Exported Constants

Defines

#define | OPAMP_NONINVERTINGINPUT_IO0 ((uint32_t)0x00000000)
#define | OPAMP_NONINVERTINGINPUT_DAC_CH OPAMP_CSR_VPSEL_0

Define Documentation

#define OPAMP_NONINVERTINGINPUT_DAC_CH OPAMP_CSR_VPSEL_0

OPAMP non-inverting input connected internally to DAC channel

Definition at line 186 of file stm32h7xx_hal_opamp.h.

#define OPAMP_NONINVERTINGINPUT_IO0 ((uint32_t)0x00000000)

OPAMP non-inverting input connected to dedicated IO pin

Definition at line 185 of file stm32h7xx_hal_opamp.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: OPAMP Inverting Input

Defines
OPAMP Inverting Input
OPAMP Exported Constants

Defines

#define | OPAMP_INVERTINGINPUT_IO0 ((uint32_t)0x00000000)
#define | OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0

Define Documentation

#define OPAMP_INVERTINGINPUT_IO0 ((uint32_t)0x00000000)

OPAMP inverting input connected to dedicated IO pin

Definition at line 196 of file stm32h7xx_hal_opamp.h.

#define OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0

OPAMP inverting input connected to dedicated IO pin

Definition at line 197 of file stm32h7xx_hal_opamp.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: OPAMP Pga Connect

Defines
OPAMP Pga Connect
OPAMP Exported Constants

Defines

#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_NO ((uint32_t)0x00000000)
#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_CSR_PGGAIN_2
#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS OPAMP_CSR_PGGAIN_3
#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_3)

Define Documentation

#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_CSR_PGGAIN_2

In PGA mode, the inverting input is connected to VINM0

Definition at line 208 of file stm32h7xx_hal_opamp.h.

#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS OPAMP_CSR_PGGAIN_3

In PGA mode, the inverting input is connected to VINM0 or bias

Definition at line 209 of file stm32h7xx_hal_opamp.h.

#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_3)

In PGA mode, the inverting input is connected to VINM0 or bias , VINM1 connected for filtering

Definition at line 210 of file stm32h7xx_hal_opamp.h.

#define OPAMP_PGA_CONNECT_INVERTINGINPUT_NO ((uint32_t)0x00000000)

In PGA mode, the inverting input is not connected

Definition at line 207 of file stm32h7xx_hal_opamp.h.

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STM32H753xx HAL User Manual: OPAMP Pga Gain

Defines
OPAMP Pga Gain
OPAMP Exported Constants

Defines

#define | OPAMP_PGA_GAIN_2_OR_MINUS_1 ((uint32_t)0x00000000)
#define | OPAMP_PGA_GAIN_4_OR_MINUS_3 OPAMP_CSR_PGGAIN_0
#define | OPAMP_PGA_GAIN_8_OR_MINUS_7 OPAMP_CSR_PGGAIN_1
#define | OPAMP_PGA_GAIN_16_OR_MINUS_15 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1)

Define Documentation

#define OPAMP_PGA_GAIN_16_OR_MINUS_15 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1)

PGA gain could be 16 or -15

Definition at line 224 of file stm32h7xx_hal_opamp.h.

#define OPAMP_PGA_GAIN_2_OR_MINUS_1 ((uint32_t)0x00000000)

PGA gain could be 2 or -1

Definition at line 221 of file stm32h7xx_hal_opamp.h.

#define OPAMP_PGA_GAIN_4_OR_MINUS_3 OPAMP_CSR_PGGAIN_0

PGA gain could be 4 or -3

Definition at line 222 of file stm32h7xx_hal_opamp.h.

#define OPAMP_PGA_GAIN_8_OR_MINUS_7 OPAMP_CSR_PGGAIN_1

PGA gain could be 8 or -7

Definition at line 223 of file stm32h7xx_hal_opamp.h.

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STM32H753xx HAL User Manual: OPAMP PowerMode

Defines
OPAMP PowerMode
OPAMP Exported Constants

Defines

#define | OPAMP_POWERMODE_NORMAL ((uint32_t)0x00000000)
#define | OPAMP_POWERMODE_HIGHSPEED OPAMP_CSR_OPAHSM

Define Documentation

#define OPAMP_POWERMODE_HIGHSPEED OPAMP_CSR_OPAHSM

Definition at line 234 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

#define OPAMP_POWERMODE_NORMAL ((uint32_t)0x00000000)

Definition at line 233 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: OPAMP VREF

Defines
OPAMP VREF
OPAMP Exported Constants

Defines

#define | OPAMP_VREF_3VDDA ((uint32_t)0x00000000)
#define | OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0
#define | OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1
#define | OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL

Define Documentation

#define OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0

OPAMP Vref = 10% VDDA

Definition at line 246 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

#define OPAMP_VREF_3VDDA ((uint32_t)0x00000000)

OPAMP Vref = 3.3% VDDA

Definition at line 245 of file stm32h7xx_hal_opamp.h.

#define OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1

OPAMP Vref = 50% VDDA

Definition at line 247 of file stm32h7xx_hal_opamp.h.

#define OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL

OPAMP Vref = 90% VDDA

Definition at line 248 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: OPAMP User Trimming

Defines
OPAMP User Trimming
OPAMP Exported Constants

Defines

#define | OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000)
#define | OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM

Define Documentation

#define OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000)

Factory trimming

Definition at line 257 of file stm32h7xx_hal_opamp.h.

#define OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM

User trimming

Definition at line 258 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: OPAMP Factory Trimming

Defines
OPAMP Factory Trimming
OPAMP Exported Constants

Defines

#define | OPAMP_FACTORYTRIMMING_DUMMY ((uint32_t)0xFFFFFFFF)
#define | OPAMP_FACTORYTRIMMING_N ((uint32_t)0x00000000)
#define | OPAMP_FACTORYTRIMMING_P ((uint32_t)0x00000001)

Define Documentation

#define OPAMP_FACTORYTRIMMING_DUMMY ((uint32_t)0xFFFFFFFF)

Dummy value if trimming value could not be retrieved

Definition at line 268 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset().

#define OPAMP_FACTORYTRIMMING_N ((uint32_t)0x00000000)

Offset trimming N

Definition at line 270 of file stm32h7xx_hal_opamp.h.

#define OPAMP_FACTORYTRIMMING_P ((uint32_t)0x00000001)

Offset trimming P

Definition at line 271 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset().

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STM32H753xx HAL User Manual: OPAMP Private Constants

Defines
OPAMP Private Constants
OPAMP

OPAMP Private constants and defines. More...

Defines

#define | OPAMP_CSR_RESET_VALUE ((uint32_t)0x00000000)
#define | OPAMP_CSR_RESET_BITS
#define | OPAMP_CSR_INIT_MASK_PGA
#define | OPAMP_CSR_INIT_MASK_FOLLOWER
#define | OPAMP_CSR_INIT_MASK_STANDALONE
#define | OPAMP_INPUT_NONINVERTING ((uint32_t) 8)
#define | OPAMP_TRIMMING_DELAY ((uint32_t) 2)

Detailed Description

OPAMP Private constants and defines.

Define Documentation

#define OPAMP_CSR_INIT_MASK_FOLLOWER
Value:
(OPAMP_CSR_OPAHSM | OPAMP_CSR_VMSEL| OPAMP_CSR_VPSEL \
                                    | OPAMP_CSR_USERTRIM)

Definition at line 246 of file stm32h7xx_hal_opamp.c.

Referenced by HAL_OPAMP_Init().

#define OPAMP_CSR_INIT_MASK_PGA
Value:
(OPAMP_CSR_OPAHSM | OPAMP_CSR_VMSEL | OPAMP_CSR_PGGAIN | OPAMP_CSR_PGGAIN  \
                                | OPAMP_CSR_VPSEL | OPAMP_CSR_USERTRIM)

Definition at line 242 of file stm32h7xx_hal_opamp.c.

Referenced by HAL_OPAMP_Init().

#define OPAMP_CSR_INIT_MASK_STANDALONE
Value:
(OPAMP_CSR_OPAHSM | OPAMP_CSR_VMSEL | OPAMP_CSR_VPSEL  \
                                       | OPAMP_CSR_VMSEL | OPAMP_CSR_USERTRIM)

Definition at line 250 of file stm32h7xx_hal_opamp.c.

Referenced by HAL_OPAMP_Init().

#define OPAMP_CSR_RESET_BITS
Value:
(OPAMP_CSR_OPAMPxEN | OPAMP_CSR_OPAHSM  | OPAMP_CSR_VMSEL  \
                                 | OPAMP_CSR_PGGAIN | OPAMP_CSR_VMSEL | OPAMP_CSR_VPSEL  \
                                 | OPAMP_CSR_CALON  | OPAMP_CSR_USERTRIM)

Definition at line 237 of file stm32h7xx_hal_opamp.c.

Referenced by HAL_OPAMP_DeInit().

#define OPAMP_CSR_RESET_VALUE ((uint32_t)0x00000000)

Definition at line 234 of file stm32h7xx_hal_opamp.c.

Referenced by HAL_OPAMP_DeInit().

#define OPAMP_INPUT_NONINVERTING ((uint32_t) 8)

Non inverting input

Definition at line 288 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

#define OPAMP_TRIMMING_DELAY ((uint32_t) 2)

Definition at line 294 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

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STM32H753xx HAL User Manual: OPAMP Exported Macros

Defines
OPAMP Exported Macros
OPAMP

Defines

#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
Reset OPAMP handle state.

Define Documentation

#define __HAL_OPAMP_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)

Reset OPAMP handle state.

Parameters:
__HANDLE__,: OPAMP handle.
Return values:
None

Definition at line 309 of file stm32h7xx_hal_opamp.h.

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STM32H753xx HAL User Manual: OPAMP Private Macros

Defines
OPAMP Private Macros
OPAMP

Defines

#define | IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT)
#define | IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT)
#define | IS_OPAMP_NONINVERTING_INPUT(INPUT)
#define | IS_OPAMP_PGACONNECT(CONNECT)
#define | IS_OPAMP_PGA_GAIN(GAIN)
#define | IS_OPAMP_VREF(VREF)
#define | IS_OPAMP_POWERMODE(TRIMMING)
#define | IS_OPAMP_TRIMMING(TRIMMING)
#define | IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
#define | IS_OPAMP_FACTORYTRIMMING(TRIMMING)

Define Documentation

#define IS_OPAMP_FACTORYTRIMMING ( TRIMMING )
Value:
(((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
                                             ((TRIMMING) == OPAMP_FACTORYTRIMMING_P))

Definition at line 358 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset().

#define IS_OPAMP_FUNCTIONAL_NORMALMODE ( INPUT )
Value:
(((INPUT) == OPAMP_STANDALONE_MODE) || \
                                               ((INPUT) == OPAMP_PGA_MODE) || \
                                               ((INPUT) == OPAMP_FOLLOWER_MODE))

Definition at line 321 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_INVERTING_INPUT_STANDALONE ( INPUT )
Value:
(((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
                                                    ((INPUT) == OPAMP_INVERTINGINPUT_IO1))

Definition at line 325 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_NONINVERTING_INPUT ( INPUT )
Value:
(((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
                                            ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH))

Definition at line 329 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_PGA_GAIN ( GAIN )
Value:
(((GAIN) == OPAMP_PGA_GAIN_2_OR_MINUS_1) || \
                                 ((GAIN) == OPAMP_PGA_GAIN_4_OR_MINUS_3) || \
                                 ((GAIN) == OPAMP_PGA_GAIN_8_OR_MINUS_7) || \
                                 ((GAIN) == OPAMP_PGA_GAIN_16_OR_MINUS_15))

Definition at line 337 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_PGACONNECT ( CONNECT )
Value:
(((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_NO)  || \
                                      ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0) || \
                                      ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS) || \
                                      ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS))

Definition at line 332 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_POWERMODE ( TRIMMING )
Value:
(((TRIMMING) == OPAMP_POWERMODE_NORMAL) || \
                                      ((TRIMMING) == OPAMP_POWERMODE_HIGHSPEED) )

Definition at line 348 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

#define IS_OPAMP_TRIMMING ( TRIMMING )
Value:
(((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
                                     ((TRIMMING) == OPAMP_TRIMMING_USER))

Definition at line 352 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_TRIMMINGVALUE ( TRIMMINGVALUE ) ((TRIMMINGVALUE) <= 0x1F)

Definition at line 356 of file stm32h7xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_VREF ( VREF )
Value:
(((VREF) == OPAMP_VREF_3VDDA)  || \
                             ((VREF) == OPAMP_VREF_10VDDA) || \
                             ((VREF) == OPAMP_VREF_50VDDA) || \
                             ((VREF) == OPAMP_VREF_90VDDA))

Definition at line 343 of file stm32h7xx_hal_opamp.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PCD Private Macros

Defines
PCD Private Macros
PCD

Defines

#define | PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define | PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))

Define Documentation

#define PCD_MAX | ( | a,
 |  | b
 | ) | (((a) > (b)) ? (a) : (b))

Definition at line 97 of file stm32h7xx_hal_pcd.c.

#define PCD_MIN | ( | a,
 |  | b
 | ) | (((a) < (b)) ? (a) : (b))

Definition at line 96 of file stm32h7xx_hal_pcd.c.

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STM32H753xx HAL User Manual: PCD Private Functions

Functions
PCD Private Functions
PCD

Functions

static HAL_StatusTypeDef PCD_WriteEmptyTxFifo (PCD_HandleTypeDef *hpcd, uint32_t epnum)
DCD_WriteEmptyTxFifo check FIFO for the next packet to be loaded.

Function Documentation

static HAL_StatusTypeDef PCD_WriteEmptyTxFifo | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint32_t | epnum
 | ) |  | [static]

DCD_WriteEmptyTxFifo check FIFO for the next packet to be loaded.

Parameters:
hpcd,: PCD handle
epnum : endpoint number
Return values:
HAL status

Definition at line 1140 of file stm32h7xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Init, and PCD_HandleTypeDef::Instance.

Referenced by HAL_PCD_IRQHandler().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
PCD Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:

Function Documentation

HAL_StatusTypeDef HAL_PCD_DeInit ( PCD_HandleTypeDef * hpcd )

DeInitializes the PCD peripheral.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 216 of file stm32h7xx_hal_pcd.c.

References HAL_PCD_MspDeInit(), HAL_PCD_STATE_BUSY, HAL_PCD_STATE_RESET, HAL_PCD_Stop(), and PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_Init ( PCD_HandleTypeDef * hpcd )

Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and create the associated handle.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 135 of file stm32h7xx_hal_pcd.c.

References __HAL_PCD_DISABLE, assert_param, HAL_PCD_MspInit(), HAL_PCD_STATE_BUSY, HAL_PCD_STATE_READY, HAL_PCDEx_ActivateBCD(), HAL_PCDEx_ActivateLPM(), PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Init, PCD_HandleTypeDef::Instance, IS_PCD_ALL_INSTANCE, PCD_HandleTypeDef::OUT_ep, and PCD_HandleTypeDef::State.

void HAL_PCD_MspDeInit ( PCD_HandleTypeDef * hpcd )

DeInitializes PCD MSP.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 254 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_DeInit().

void HAL_PCD_MspInit ( PCD_HandleTypeDef * hpcd )

Initializes the PCD MSP.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 242 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_Init().

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STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
PCD Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start The USB OTG Device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop The USB OTG Device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
This function handles PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data out stage callbacks.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callbacks.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callbacks.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callbacks.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callbacks.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callbacks.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callbacks.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callbacks.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callbacks.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callbacks.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the PCD data
    transfers.

Function Documentation

void HAL_PCD_ConnectCallback ( PCD_HandleTypeDef * hpcd )

Connection event callbacks.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 737 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_DataInStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Data IN stage callbacks.

Parameters:
hpcd,: PCD handle
epnum,: endpoint number
Return values:
None

Definition at line 639 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_DataOutStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Data out stage callbacks.

Parameters:
hpcd,: PCD handle
epnum,: endpoint number
Return values:
None

Definition at line 626 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_DisconnectCallback ( PCD_HandleTypeDef * hpcd )

Disconnection event callbacks.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 749 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_IRQHandler ( PCD_HandleTypeDef * hpcd )

This function handles PCD interrupt request.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 314 of file stm32h7xx_hal_pcd.c.

References __HAL_PCD_CLEAR_FLAG, __HAL_PCD_GET_FLAG, __HAL_PCD_IS_INVALID_INTERRUPT, PCD_HandleTypeDef::BESL, HAL_PCD_ConnectCallback(), HAL_PCD_DataInStageCallback(), HAL_PCD_DataOutStageCallback(), HAL_PCD_DisconnectCallback(), HAL_PCD_ISOINIncompleteCallback(), HAL_PCD_ISOOUTIncompleteCallback(), HAL_PCD_ResetCallback(), HAL_PCD_ResumeCallback(), HAL_PCD_SetupStageCallback(), HAL_PCD_SOFCallback(), HAL_PCD_SuspendCallback(), HAL_PCDEx_LPM_Callback(), PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Init, PCD_HandleTypeDef::Instance, LPM_L0, LPM_L1, PCD_HandleTypeDef::LPM_State, PCD_HandleTypeDef::OUT_ep, PCD_LPM_L0_ACTIVE, PCD_LPM_L1_ACTIVE, PCD_WriteEmptyTxFifo(), PCD_HandleTypeDef::Setup, USBD_FS_TRDT_VALUE, and USBD_HS_TRDT_VALUE.

void HAL_PCD_ISOINIncompleteCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Incomplete ISO IN callbacks.

Parameters:
hpcd,: PCD handle
epnum,: endpoint number
Return values:
None

Definition at line 725 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_ISOOUTIncompleteCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Incomplete ISO OUT callbacks.

Parameters:
hpcd,: PCD handle
epnum,: endpoint number
Return values:
None

Definition at line 712 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_ResetCallback ( PCD_HandleTypeDef * hpcd )

USB Reset callbacks.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 674 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_ResumeCallback ( PCD_HandleTypeDef * hpcd )

Resume event callbacks.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 699 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_SetupStageCallback ( PCD_HandleTypeDef * hpcd )

Setup stage callback.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 650 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_SOFCallback ( PCD_HandleTypeDef * hpcd )

USB Start Of Frame callbacks.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 662 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

HAL_StatusTypeDef HAL_PCD_Start ( PCD_HandleTypeDef * hpcd )

Start The USB OTG Device.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 285 of file stm32h7xx_hal_pcd.c.

References __HAL_PCD_ENABLE, and PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_Stop ( PCD_HandleTypeDef * hpcd )

Stop The USB OTG Device.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 299 of file stm32h7xx_hal_pcd.c.

References __HAL_PCD_DISABLE, and PCD_HandleTypeDef::Instance.

Referenced by HAL_PCD_DeInit().

void HAL_PCD_SuspendCallback ( PCD_HandleTypeDef * hpcd )

Suspend event callbacks.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 687 of file stm32h7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PCD Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
uint16_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
HAL_PCD_ActivateRemoteWakeup : Active remote wake-up signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
HAL_PCD_DeActivateRemoteWakeup : de-active remote wake-up signalling.

Detailed Description

management functions

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the PCD data
    transfers.

Function Documentation

HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup ( PCD_HandleTypeDef * hpcd )

HAL_PCD_ActivateRemoteWakeup : Active remote wake-up signalling.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 1067 of file stm32h7xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup ( PCD_HandleTypeDef * hpcd )

HAL_PCD_DeActivateRemoteWakeup : de-active remote wake-up signalling.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 1084 of file stm32h7xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DevConnect ( PCD_HandleTypeDef * hpcd )

Connect the USB device.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 780 of file stm32h7xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DevDisconnect ( PCD_HandleTypeDef * hpcd )

Disconnect the USB device.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 793 of file stm32h7xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_EP_Close | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Deactivate an endpoint.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
Return values:
HAL status

Definition at line 864 of file stm32h7xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Instance, and PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_ClrStall | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Clear a STALL condition over in an endpoint.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
Return values:
HAL status

Definition at line 1014 of file stm32h7xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Instance, and PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Flush | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Flush an endpoint.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
Return values:
HAL status

Definition at line 1044 of file stm32h7xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

uint16_t HAL_PCD_EP_GetRxCount | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Get Received Data Size.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
Return values:
Data Size

Definition at line 931 of file stm32h7xx_hal_pcd.c.

References PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Open | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint16_t | ep_mps,
 |  | uint8_t | ep_type
 | ) |  |

Open and configure an endpoint.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
ep_mps,: endpoint max packet size
ep_type,: endpoint type
Return values:
HAL status

Definition at line 822 of file stm32h7xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Instance, and PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Receive | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pBuf,
 |  | uint32_t | len
 | ) |  |

Receive an amount of data.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
pBuf,: pointer to the reception buffer
len,: amount of data to be received
Return values:
HAL status

Definition at line 895 of file stm32h7xx_hal_pcd.c.

References PCD_HandleTypeDef::Init, PCD_HandleTypeDef::Instance, and PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_SetStall | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Set a STALL condition over an endpoint.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
Return values:
HAL status

Definition at line 979 of file stm32h7xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Init, PCD_HandleTypeDef::Instance, PCD_HandleTypeDef::OUT_ep, and PCD_HandleTypeDef::Setup.

HAL_StatusTypeDef HAL_PCD_EP_Transmit | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pBuf,
 |  | uint32_t | len
 | ) |  |

Send an amount of data.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
pBuf,: pointer to the transmission buffer
len,: amount of data to be sent
Return values:
HAL status

Definition at line 943 of file stm32h7xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Init, and PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_SetAddress | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | address
 | ) |  |

Set the USB Device address.

Parameters:
hpcd,: PCD handle
address,: new device address
Return values:
HAL status

Definition at line 807 of file stm32h7xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
PCD Exported Functions

Peripheral State functions. More...

Functions

PCD_StateTypeDef HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

PCD_StateTypeDef HAL_PCD_GetState ( PCD_HandleTypeDef * hpcd )

Return the PCD state.

Parameters:
hpcd,: PCD handle
Return values:
HAL state

Definition at line 1116 of file stm32h7xx_hal_pcd.c.

References PCD_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PCD Exported Types

Data Structures | Typedefs | Enumerations
PCD Exported Types
PCD

Data Structures

struct | PCD_HandleTypeDef
PCD Handle Structure definition. More...

Typedefs

typedef USB_OTG_GlobalTypeDef | PCD_TypeDef
typedef USB_OTG_CfgTypeDef | PCD_InitTypeDef
typedef USB_OTG_EPTypeDef | PCD_EPTypeDef

Enumerations

enum PCD_StateTypeDef {
HAL_PCD_STATE_RESET = 0x00, HAL_PCD_STATE_READY = 0x01, HAL_PCD_STATE_ERROR = 0x02, HAL_PCD_STATE_BUSY = 0x03,
HAL_PCD_STATE_TIMEOUT = 0x04
}
PCD State structure definition. More...
enum | PCD_LPM_StateTypeDef { LPM_L0 = 0x00, LPM_L1 = 0x01, LPM_L2 = 0x02, LPM_L3 = 0x03 }

Typedef Documentation

typedef USB_OTG_EPTypeDef PCD_EPTypeDef

Definition at line 85 of file stm32h7xx_hal_pcd.h.

typedef USB_OTG_CfgTypeDef PCD_InitTypeDef

Definition at line 84 of file stm32h7xx_hal_pcd.h.

typedef USB_OTG_GlobalTypeDef PCD_TypeDef

Definition at line 83 of file stm32h7xx_hal_pcd.h.

Enumeration Type Documentation

enum PCD_LPM_StateTypeDef
Enumerator:
LPM_L0
LPM_L1
LPM_L2
LPM_L3

Definition at line 75 of file stm32h7xx_hal_pcd.h.

enum PCD_StateTypeDef

PCD State structure definition.

Enumerator:
HAL_PCD_STATE_RESET
HAL_PCD_STATE_READY
HAL_PCD_STATE_ERROR
HAL_PCD_STATE_BUSY
HAL_PCD_STATE_TIMEOUT

Definition at line 65 of file stm32h7xx_hal_pcd.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PCD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PCD_HandleTypeDef Struct Reference
PCD Exported Types

PCD Handle Structure definition. More...

#include <stm32h7xx_hal_pcd.h>

Data Fields

PCD_TypeDef * Instance
PCD_InitTypeDef Init
PCD_EPTypeDef | IN_ep [15]
PCD_EPTypeDef | OUT_ep [15]
HAL_LockTypeDef | Lock
__IO PCD_StateTypeDef | State
uint32_t | Setup [12]
PCD_LPM_StateTypeDef LPM_State
uint32_t | BESL
uint32_t | lpm_active
uint32_t | battery_charging_active
void * | pData

Detailed Description

PCD Handle Structure definition.

Definition at line 90 of file stm32h7xx_hal_pcd.h.

Field Documentation

uint32_t PCD_HandleTypeDef::battery_charging_active

Enable or disable Battery charging. This parameter can be set to ENABLE or DISABLE

Definition at line 103 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCDEx_ActivateBCD(), and HAL_PCDEx_DeActivateBCD().

uint32_t PCD_HandleTypeDef::BESL

Definition at line 100 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

PCD_EPTypeDef PCD_HandleTypeDef::IN_ep[15]

IN endpoint parameters

Definition at line 94 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_Open(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCD_IRQHandler(), and PCD_WriteEmptyTxFifo().

PCD_InitTypeDef PCD_HandleTypeDef::Init

PCD required parameters

Definition at line 93 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCD_IRQHandler(), and PCD_WriteEmptyTxFifo().

PCD_TypeDef* PCD_HandleTypeDef::Instance

Register base address

Definition at line 92 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_ActivateRemoteWakeup(), HAL_PCD_DeActivateRemoteWakeup(), HAL_PCD_DevConnect(), HAL_PCD_DevDisconnect(), HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_Flush(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_SetAddress(), HAL_PCD_Start(), HAL_PCD_Stop(), HAL_PCDEx_ActivateBCD(), HAL_PCDEx_ActivateLPM(), HAL_PCDEx_BCD_VBUSDetect(), HAL_PCDEx_DeActivateBCD(), HAL_PCDEx_DeActivateLPM(), HAL_PCDEx_SetRxFiFo(), HAL_PCDEx_SetTxFiFo(), and PCD_WriteEmptyTxFifo().

HAL_LockTypeDef PCD_HandleTypeDef::Lock

PCD peripheral status

Definition at line 96 of file stm32h7xx_hal_pcd.h.

uint32_t PCD_HandleTypeDef::lpm_active

Enable or disable the Link Power Management . This parameter can be set to ENABLE or DISABLE

Definition at line 101 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCDEx_ActivateLPM(), and HAL_PCDEx_DeActivateLPM().

PCD_LPM_StateTypeDef PCD_HandleTypeDef::LPM_State

LPM State

Definition at line 99 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler(), and HAL_PCDEx_ActivateLPM().

PCD_EPTypeDef PCD_HandleTypeDef::OUT_ep[15]

OUT endpoint parameters

Definition at line 95 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_GetRxCount(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_Init(), and HAL_PCD_IRQHandler().

void* PCD_HandleTypeDef::pData

Pointer to upper stack Handler

Definition at line 106 of file stm32h7xx_hal_pcd.h.

uint32_t PCD_HandleTypeDef::Setup[12]

Setup packet buffer

Definition at line 98 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_EP_SetStall(), and HAL_PCD_IRQHandler().

__IO PCD_StateTypeDef PCD_HandleTypeDef::State

PCD communication state

Definition at line 97 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_DeInit(), HAL_PCD_GetState(), and HAL_PCD_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_pcd.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PCD Speed

Defines
PCD Speed
PCD Exported Constants

Defines

#define | PCD_SPEED_HIGH 0
#define | PCD_SPEED_HIGH_IN_FULL 1
#define | PCD_SPEED_FULL 2

Define Documentation

#define PCD_SPEED_FULL 2

Definition at line 126 of file stm32h7xx_hal_pcd.h.

#define PCD_SPEED_HIGH 0

Definition at line 124 of file stm32h7xx_hal_pcd.h.

#define PCD_SPEED_HIGH_IN_FULL 1

Definition at line 125 of file stm32h7xx_hal_pcd.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PCD PHY Module

Defines
PCD PHY Module
PCD Exported Constants

Defines

#define | PCD_PHY_ULPI 1
#define | PCD_PHY_EMBEDDED 2

Define Documentation

#define PCD_PHY_EMBEDDED 2

Definition at line 135 of file stm32h7xx_hal_pcd.h.

#define PCD_PHY_ULPI 1

Definition at line 134 of file stm32h7xx_hal_pcd.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Turnaround Timeout Value

Defines
Turnaround Timeout Value
PCD Exported Constants

Defines

#define | USBD_HS_TRDT_VALUE 9
#define | USBD_FS_TRDT_VALUE 5

Define Documentation

#define USBD_FS_TRDT_VALUE 5

Definition at line 147 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define USBD_HS_TRDT_VALUE 9

Definition at line 144 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PCD Instance definition

Defines
PCD Instance definition
PCD Exported Macros

Defines

#define IS_PCD_ALL_INSTANCE(INSTANCE)

Define Documentation

#define IS_PCD_ALL_INSTANCE ( INSTANCE )
Value:
(((INSTANCE) == USB1_OTG_HS) || \
                                       ((INSTANCE) == USB2_OTG_FS))

Definition at line 310 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_Init().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PCD Exported Macros

Modules | Defines
PCD Exported Macros
PCD

macros to handle interrupts and specific clock configurations More...

Modules

PCD Instance definition
PCD Exported Functions

Defines

#define | __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define | __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
#define | __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)
#define | __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
#define | __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
#define | USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)
#define | USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)
#define | USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)
#define | USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)
#define | USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)
#define | USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)
#define | USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR2_IM43)
#define | USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR2_IM44)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI_D1->IMR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI_D1->IMR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI_D1->PR2 & (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI_D1->PR2 = (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE()
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER2 |= USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI_D1->IMR2 |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI_D1->IMR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI_D1->PR2 & (USB_OTG_FS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI_D1->PR2 = USB_OTG_FS_WAKEUP_EXTI_LINE
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE()
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER2 |= USB_OTG_FS_WAKEUP_EXTI_LINE)

Detailed Description

macros to handle interrupts and specific clock configurations

Define Documentation

#define __HAL_PCD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))

Definition at line 167 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define __HAL_PCD_DISABLE ( __HANDLE__ ) USB_DisableGlobalInt ((__HANDLE__)->Instance)

Definition at line 164 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), and HAL_PCD_Stop().

#define __HAL_PCD_ENABLE ( __HANDLE__ ) USB_EnableGlobalInt ((__HANDLE__)->Instance)

Definition at line 163 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_Start().

#define __HAL_PCD_GATE_PHYCLOCK ( __HANDLE__ ) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK

Definition at line 174 of file stm32h7xx_hal_pcd.h.

#define __HAL_PCD_GET_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))

Definition at line 166 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define __HAL_PCD_IS_INVALID_INTERRUPT ( __HANDLE__ ) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)

Definition at line 168 of file stm32h7xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define __HAL_PCD_IS_PHY_SUSPENDED ( __HANDLE__ ) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)

Definition at line 176 of file stm32h7xx_hal_pcd.h.

#define __HAL_PCD_UNGATE_PHYCLOCK ( __HANDLE__ )
Value:
*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
                                                       ~(USB_OTG_PCGCCTL_STOPCLK)

Definition at line 171 of file stm32h7xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG ( ) EXTI_D1->PR2 = USB_OTG_FS_WAKEUP_EXTI_LINE

Definition at line 218 of file stm32h7xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT ( ) EXTI_D1->IMR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)

Definition at line 216 of file stm32h7xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE ( )
Value:
EXTI->FTSR2 |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
                                                            EXTI->RTSR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)

Definition at line 222 of file stm32h7xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT ( ) EXTI_D1->IMR2 |= USB_OTG_FS_WAKEUP_EXTI_LINE

Definition at line 215 of file stm32h7xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE ( )
Value:
EXTI->FTSR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
                                                          EXTI->RTSR2 |= USB_OTG_FS_WAKEUP_EXTI_LINE

Definition at line 219 of file stm32h7xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
EXTI->RTSR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
                                                                   EXTI->FTSR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
                                                                   EXTI->RTSR2 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
                                                                   EXTI->FTSR2 |= USB_OTG_FS_WAKEUP_EXTI_LINE

Definition at line 225 of file stm32h7xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER2 |= USB_OTG_FS_WAKEUP_EXTI_LINE)

Definition at line 230 of file stm32h7xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG ( ) EXTI_D1->PR2 & (USB_OTG_FS_WAKEUP_EXTI_LINE)

Definition at line 217 of file stm32h7xx_hal_pcd.h.

#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG ( ) EXTI_D1->PR2 = (USB_OTG_HS_WAKEUP_EXTI_LINE)

Definition at line 196 of file stm32h7xx_hal_pcd.h.

#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT ( ) EXTI_D1->IMR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)

Definition at line 194 of file stm32h7xx_hal_pcd.h.

#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE ( )
Value:
EXTI->FTSR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
                                                            EXTI->RTSR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)

Definition at line 201 of file stm32h7xx_hal_pcd.h.

#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT ( ) EXTI_D1->IMR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE)

Definition at line 193 of file stm32h7xx_hal_pcd.h.

#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE ( )
Value:
EXTI->FTSR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
                                                          EXTI->RTSR2 |= USB_OTG_HS_WAKEUP_EXTI_LINE

Definition at line 198 of file stm32h7xx_hal_pcd.h.

#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
EXTI->RTSR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
                                                                    EXTI->FTSR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE;)\
                                                                    EXTI->RTSR2 |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
                                                                    EXTI->FTSR2 |= USB_OTG_HS_WAKEUP_EXTI_LINE

Definition at line 204 of file stm32h7xx_hal_pcd.h.

#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER2 |= USB_OTG_HS_WAKEUP_EXTI_LINE)

Definition at line 209 of file stm32h7xx_hal_pcd.h.

#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG ( ) EXTI_D1->PR2 & (USB_OTG_HS_WAKEUP_EXTI_LINE)

Definition at line 195 of file stm32h7xx_hal_pcd.h.

#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)

Definition at line 179 of file stm32h7xx_hal_pcd.h.

#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR2_IM44)

External interrupt line 44 Connected to the USB FS EXTI Line

Definition at line 189 of file stm32h7xx_hal_pcd.h.

#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)

Definition at line 178 of file stm32h7xx_hal_pcd.h.

#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)

Definition at line 180 of file stm32h7xx_hal_pcd.h.

#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)

Definition at line 183 of file stm32h7xx_hal_pcd.h.

#define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR2_IM43)

External interrupt line 43 Connected to the USB HS EXTI Line

Definition at line 186 of file stm32h7xx_hal_pcd.h.

#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)

Definition at line 182 of file stm32h7xx_hal_pcd.h.

#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)

Definition at line 184 of file stm32h7xx_hal_pcd.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PCDEx Exported Functions

PCDEx control functions. More...

Functions

HAL_StatusTypeDef | HAL_PCDEx_SetTxFiFo (PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
Set Tx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_SetRxFiFo (PCD_HandleTypeDef *hpcd, uint16_t size)
Set Rx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_ActivateLPM (PCD_HandleTypeDef *hpcd)
HAL_PCDEx_ActivateLPM : active LPM Feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateLPM (PCD_HandleTypeDef *hpcd)
HAL_PCDEx_DeActivateLPM : de-active LPM feature.
void | HAL_PCDEx_BCD_VBUSDetect (PCD_HandleTypeDef *hpcd)
Handle BatteryCharging Process.
HAL_StatusTypeDef | HAL_PCDEx_ActivateBCD (PCD_HandleTypeDef *hpcd)
Activate BatteryCharging feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateBCD (PCD_HandleTypeDef *hpcd)
Deactivate BatteryCharging feature.
__weak void | HAL_PCDEx_LPM_Callback (PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
Send LPM message to user layer callback.
__weak void | HAL_PCDEx_BCD_Callback (PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
Send BatteryCharging message to user layer callback.

Detailed Description

PCDEx control functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Update FIFO configuration

Function Documentation

HAL_StatusTypeDef HAL_PCDEx_ActivateBCD ( PCD_HandleTypeDef * hpcd )

Activate BatteryCharging feature.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 242 of file stm32h7xx_hal_pcd_ex.c.

References PCD_HandleTypeDef::battery_charging_active, and PCD_HandleTypeDef::Instance.

Referenced by HAL_PCD_Init().

HAL_StatusTypeDef HAL_PCDEx_ActivateLPM ( PCD_HandleTypeDef * hpcd )

HAL_PCDEx_ActivateLPM : active LPM Feature.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 142 of file stm32h7xx_hal_pcd_ex.c.

References PCD_HandleTypeDef::Instance, PCD_HandleTypeDef::lpm_active, LPM_L0, and PCD_HandleTypeDef::LPM_State.

Referenced by HAL_PCD_Init().

void HAL_PCDEx_BCD_Callback | ( | PCD_HandleTypeDef * | hpcd,
 |  | PCD_BCD_MsgTypeDef | msg
 | ) |  |

Send BatteryCharging message to user layer callback.

Parameters:
hpcd,: PCD handle
msg,: LPM message
Return values:
HAL status

Definition at line 291 of file stm32h7xx_hal_pcd_ex.c.

Referenced by HAL_PCDEx_BCD_VBUSDetect().

void HAL_PCDEx_BCD_VBUSDetect ( PCD_HandleTypeDef * hpcd )

Handle BatteryCharging Process.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 175 of file stm32h7xx_hal_pcd_ex.c.

References HAL_Delay(), HAL_GetTick(), HAL_PCDEx_BCD_Callback(), PCD_HandleTypeDef::Instance, PCD_BCD_CHARGING_DOWNSTREAM_PORT, PCD_BCD_CONTACT_DETECTION, PCD_BCD_DEDICATED_CHARGING_PORT, PCD_BCD_DISCOVERY_COMPLETED, PCD_BCD_ERROR, and PCD_BCD_STD_DOWNSTREAM_PORT.

HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD ( PCD_HandleTypeDef * hpcd )

Deactivate BatteryCharging feature.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 259 of file stm32h7xx_hal_pcd_ex.c.

References PCD_HandleTypeDef::battery_charging_active, and PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM ( PCD_HandleTypeDef * hpcd )

HAL_PCDEx_DeActivateLPM : de-active LPM feature.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 159 of file stm32h7xx_hal_pcd_ex.c.

References PCD_HandleTypeDef::Instance, and PCD_HandleTypeDef::lpm_active.

void HAL_PCDEx_LPM_Callback | ( | PCD_HandleTypeDef * | hpcd,
 |  | PCD_LPM_MsgTypeDef | msg
 | ) |  |

Send LPM message to user layer callback.

Parameters:
hpcd,: PCD handle
msg,: LPM message
Return values:
HAL status

Definition at line 274 of file stm32h7xx_hal_pcd_ex.c.

Referenced by HAL_PCD_IRQHandler().

HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint16_t | size
 | ) |  |

Set Rx FIFO.

Parameters:
hpcd,: PCD handle
size,: Size of Rx fifo
Return values:
HAL status

Definition at line 130 of file stm32h7xx_hal_pcd_ex.c.

References PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | fifo,
 |  | uint16_t | size
 | ) |  |

Set Tx FIFO.

Parameters:
hpcd,: PCD handle
fifo,: The number of Tx fifo
size,: Fifo size
Return values:
HAL status

Definition at line 87 of file stm32h7xx_hal_pcd_ex.c.

References PCD_HandleTypeDef::Instance.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PCDEx

Modules | Enumerations
PCDEx
STM32H7xx_HAL_Driver

PCD Extended HAL module driver. More...

Modules

PCDEx Exported Functions

Enumerations

enum PCD_LPM_MsgTypeDef { PCD_LPM_L0_ACTIVE = 0x00, PCD_LPM_L1_ACTIVE = 0x01 }
enum PCD_BCD_MsgTypeDef {
PCD_BCD_ERROR = 0xFF, PCD_BCD_CONTACT_DETECTION = 0xFE, PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, PCD_BCD_DISCOVERY_COMPLETED = 0x00
}

Detailed Description

PCD Extended HAL module driver.

Enumeration Type Documentation

enum PCD_BCD_MsgTypeDef
Enumerator:
PCD_BCD_ERROR
PCD_BCD_CONTACT_DETECTION
PCD_BCD_STD_DOWNSTREAM_PORT
PCD_BCD_CHARGING_DOWNSTREAM_PORT
PCD_BCD_DEDICATED_CHARGING_PORT
PCD_BCD_DISCOVERY_COMPLETED

Definition at line 64 of file stm32h7xx_hal_pcd_ex.h.

enum PCD_LPM_MsgTypeDef
Enumerator:
PCD_LPM_L0_ACTIVE
PCD_LPM_L1_ACTIVE

Definition at line 57 of file stm32h7xx_hal_pcd_ex.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and De-Initialization functions

Functions
Initialization and De-Initialization functions
PWR Exported Functions

Initialization and De-Initialization functions. More...

Functions

void | HAL_PWR_DeInit (void)
Deinitialize the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Detailed Description

Initialization and De-Initialization functions.

 ===============================================================================
              ##### Initialization and De-Initialization functions #####
 ===============================================================================
    [..]
      After reset, the backup domain (RTC registers, RTC backup data
      registers and backup SRAM) is protected against possible unwanted
      write accesses.
      To enable access to the RTC Domain and RTC registers, proceed as follows:
        (+) Enable the Power Controller (PWR) APB1 interface clock using the
            __HAL_RCC_PWR_CLK_ENABLE() macro.
        (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.

Function Documentation

void HAL_PWR_DeInit ( void )

Deinitialize the HAL PWR peripheral registers to their default reset values.

Note:
This functionality is not available in this product. The prototype is kept just to maintain compatibility with other products.
Return values:
None

Definition at line 113 of file stm32h7xx_hal_pwr.c.

void HAL_PWR_DisableBkUpAccess ( void )

Disable access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Note:
If the HSE divided by 2, 3, ..31 is used as the RTC clock, the Backup Domain Access should be kept enabled.
Return values:
None

Definition at line 137 of file stm32h7xx_hal_pwr.c.

void HAL_PWR_EnableBkUpAccess ( void )

Enable access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Note:
If the HSE divided by 2, 3, ..31 is used as the RTC clock, the Backup Domain Access should be kept enabled.
Return values:
None

Definition at line 124 of file stm32h7xx_hal_pwr.c.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PWR Exported Functions

Low Power modes configuration functions. More...

Functions

void | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configure the voltage threshold detected by the Power Voltage Detector(PVD).
void | HAL_PWR_EnablePVD (void)
Enable the Power Voltage Detector(PVD).
void | HAL_PWR_DisablePVD (void)
Disable the Power Voltage Detector(PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
Enable the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disable the WakeUp PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enter CM7 core to Sleep mode.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enter the system to STOP mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enter the system to STANDBY mode.
void | HAL_PWR_EnableSleepOnExit (void)
Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enable CORTEX SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disable CORTEX SEVONPEND bit.
void | HAL_PWR_PVD_IRQHandler (void)
This function handles the PWR PVD interrupt request.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.

Detailed Description

Low Power modes configuration functions.

 ===============================================================================
                 ##### Peripheral Control functions #####
 ===============================================================================

    *** PVD configuration ***
    =========================
    [..]
      (+) The PVD is used to monitor the VDD power supply by comparing it to a
          threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1 register).
      (+) A PVDO flag is available to indicate if VDD is higher or lower
          than the PVD threshold. This event is internally connected to the EXTI
          line 16 to generate an interrupt if enabled.
          It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
      (+) The PVD is stopped in Standby mode.

    *** Wake-up pin configuration ***
    ================================
    [..]
      (+) Wake-up pin is used to wake up the system from Standby mode.
          The pin pull is configurable through the WKUPEPR register to be in No pull-up, Pull-up and Pull-down.
          The pin polarity is configurable through the WKUPEPR register to be active on rising or falling edges.
      (+) There are up to six Wake-up pin in the STM32H7 devices family.

    *** Low Power modes configuration ***
    =====================================
    [..]
     The device present 3 principles low-power modes features:
      (+) SLEEP mode: Cortex-M7 core stopped and D1, D2 and D3 peripherals kept running.
      (+) STOP mode: all clocks are stoppedand the regulator running in main or low power mode.
      (+) STANDBY mode: D1, D2 and D3 domains enter DSTANDBY mode and the VCORE supply
                        regulator is powered off.

   *** SLEEP mode ***
   ==================
    [..]
      (+) Entry:
        The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, SLEEPEntry)
        function.

          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction

      -@@- The Regulator parameter is not used for the STM32H7 family
              and is kept as parameter just to maintain compatibility with the
              lower power families (STM32L).
      (+) Exit:
        Any peripheral interrupt acknowledged by the nested vectored interrupt
        controller (NVIC) can wake up the device from Sleep mode.

   *** STOP mode ***
   =================
    [..]
      In system Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
      and the HSE RC oscillators are disabled. Internal SRAM and register contents
      are preserved.
      The voltage regulator can be configured either in normal or low-power mode.
      To minimize the consumption In Stop mode, FLASH can be powered off before
      entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
      It can be switched on again by software after exiting the Stop mode using
      the HAL_PWREx_DisableFlashPowerDown() function.

      (+) Entry:
         The Stop mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, STOPEntry)
         function with:
         (++) Regulator:
          (+++) PWR_MAINREGULATOR_ON: Main regulator ON.
          (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
         (++) STOPEntry:
          (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction
          (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
      (+) Exit:
        Any EXTI Line (Internal or External) configured in Interrupt/Event mode.

   *** STANDBY mode ***
   ====================
    [..]
    (+)
      The system Standby mode allows to achieve the lowest power consumption. It is based
      on the Cortex-M7 deep sleep mode, with the voltage regulator disabled.
      The system is consequently powered off. The PLL, the HSI oscillator and
      the HSE oscillator are also switched off. SRAM and register contents are lost
      except for the RTC registers, RTC backup registers, backup SRAM and Standby
      circuitry.
    [..]
      The voltage regulator is OFF.
      (++) Entry:
        (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
      (++) Exit:
        (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
              wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.

   *** Auto-wakeup (AWU) from low-power mode ***
   =============================================
    [..]
     (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
      Wakeup event, a tamper event or a time-stamp event, without depending on
      an external interrupt (Auto-wakeup mode).
     (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes
       (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
            configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
       (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
            is necessary to configure the RTC to detect the tamper or time stamp event using the
            HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
       (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
            configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.

Function Documentation

void HAL_PWR_ConfigPVD ( PWR_PVDTypeDef * sConfigPVD )

Configure the voltage threshold detected by the Power Voltage Detector(PVD).

Parameters:
sConfigPVD,: pointer to an PWR_PVDTypeDef structure that contains the configuration information for the PVD.
Note:
Refer to the electrical characteristics of your device datasheet for more details about the voltage threshold corresponding to each detection level.
Return values:
None

Definition at line 271 of file stm32h7xx_hal_pwr.c.

References __HAL_PWR_PVD_EXTI_DISABLE_EVENT, __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_PVD_EXTI_DISABLE_IT, __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_PVD_EXTI_ENABLE_EVENT, __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_PVD_EXTI_ENABLE_IT, __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE, assert_param, IS_PWR_PVD_LEVEL, IS_PWR_PVD_MODE, PWR_PVDTypeDef::Mode, PVD_FALLING_EDGE, PVD_MODE_EVT, PVD_MODE_IT, PVD_RISING_EDGE, and PWR_PVDTypeDef::PVDLevel.

void HAL_PWR_DisablePVD ( void )

Disable the Power Voltage Detector(PVD).

Return values:
None

Definition at line 324 of file stm32h7xx_hal_pwr.c.

void HAL_PWR_DisableSEVOnPend ( void )

Disable CORTEX SEVONPEND bit.

Note:
Clears SEVONPEND bit of SCR register. When this bit is set, this causes WFE to wake up when an interrupt moves from inactive to pended.
Return values:
None

Definition at line 558 of file stm32h7xx_hal_pwr.c.

void HAL_PWR_DisableSleepOnExit ( void )

Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.

Note:
Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor re-enters SLEEP mode when an interruption handling is over.
Return values:
None

Definition at line 534 of file stm32h7xx_hal_pwr.c.

void HAL_PWR_DisableWakeUpPin ( uint32_t WakeUpPinx )

Disable the WakeUp PINx functionality.

Parameters:
WakeUpPinx,: Specifies the Power Wake-Up pin to disable. This parameter can be one of the following values:
  • PWR_WAKEUP_PIN1
  • PWR_WAKEUP_PIN2
  • PWR_WAKEUP_PIN3
  • PWR_WAKEUP_PIN4
  • PWR_WAKEUP_PIN5
  • PWR_WAKEUP_PIN6
Return values:
None

Definition at line 368 of file stm32h7xx_hal_pwr.c.

References assert_param, and IS_PWR_WAKEUP_PIN.

void HAL_PWR_EnablePVD ( void )

Enable the Power Voltage Detector(PVD).

Return values:
None

Definition at line 314 of file stm32h7xx_hal_pwr.c.

void HAL_PWR_EnableSEVOnPend ( void )

Enable CORTEX SEVONPEND bit.

Note:
Sets SEVONPEND bit of SCR register. When this bit is set, this causes WFE to wake up when an interrupt moves from inactive to pended.
Return values:
None

Definition at line 546 of file stm32h7xx_hal_pwr.c.

void HAL_PWR_EnableSleepOnExit ( void )

Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.

Note:
Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor re-enters SLEEP mode when an interruption handling is over. Setting this bit is useful when the processor is expected to run only on interruptions handling.
Return values:
None

Definition at line 521 of file stm32h7xx_hal_pwr.c.

void HAL_PWR_EnableWakeUpPin ( uint32_t WakeUpPinPolarity )

Enable the WakeUp PINx functionality.

Parameters:
WakeUpPinPolarity,: Specifies which Wake-Up pin to enable. This parameter can be one of the following legacy values, which sets the default: polarity detection on high level (rising edge):
  • PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6 or one of the following values where the user can explicitly states the enabled pin and the chosen polarity.
  • PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
  • PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
  • PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
  • PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
  • PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
  • PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW
Note:
PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
Return values:
None

Definition at line 347 of file stm32h7xx_hal_pwr.c.

References assert_param, IS_PWR_WAKEUP_PIN, and PWR_EWUP_MASK.

void HAL_PWR_EnterSLEEPMode | ( | uint32_t | Regulator,
 |  | uint8_t | SLEEPEntry
 | ) |  |

Enter CM7 core to Sleep mode.

Parameters:
Regulator,: Specifies the regulator state in SLEEP mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
  • PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
Note:
This parameter is not used for the STM32H7 family and is kept as parameter just to maintain compatibility with the lower power families.
Parameters:
SLEEPEntry,: Specifies if SLEEP mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
  • PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
Return values:
None

Definition at line 389 of file stm32h7xx_hal_pwr.c.

References assert_param, IS_PWR_REGULATOR, IS_PWR_SLEEP_ENTRY, and PWR_SLEEPENTRY_WFI.

void HAL_PWR_EnterSTANDBYMode ( void )

Enter the system to STANDBY mode.

Note:
The system enters Standby mode only when the D1, D2 and D3 domains are in DStandby.
When the System exit STANDBY mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock.
Return values:
None.

Definition at line 491 of file stm32h7xx_hal_pwr.c.

void HAL_PWR_EnterSTOPMode | ( | uint32_t | Regulator,
 |  | uint8_t | STOPEntry
 | ) |  |

Enter the system to STOP mode.

Note:
In System Stop mode, all I/O pins keep the same state as in Run mode.
When exiting System Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as default system wakeup clock.
In System STOP mode, when the voltage regulator operates in low power mode, an additional startup delay is incurred when the system is waking up. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.
Parameters:
Regulator,: Specifies the regulator state in Stop mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON: Stop mode with regulator ON
  • PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
STOPEntry,: Specifies if Stop mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
  • PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
Return values:
None

Definition at line 432 of file stm32h7xx_hal_pwr.c.

References assert_param, IS_PWR_REGULATOR, IS_PWR_STOP_ENTRY, and PWR_STOPENTRY_WFI.

void HAL_PWR_PVD_IRQHandler ( void )

This function handles the PWR PVD interrupt request.

Note:
This API should be called under the PVD_IRQHandler().
Return values:
None

Definition at line 569 of file stm32h7xx_hal_pwr.c.

References __HAL_PWR_PVD_EXTI_CLEAR_FLAG, __HAL_PWR_PVD_EXTI_GET_FLAG, and HAL_PWR_PVDCallback().

void HAL_PWR_PVDCallback ( void )

PWR PVD interrupt callback.

Return values:
None

Definition at line 586 of file stm32h7xx_hal_pwr.c.

Referenced by HAL_PWR_PVD_IRQHandler(), and HAL_PWREx_PVD_AVD_IRQHandler().

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STM32H753xx HAL User Manual: PWR_PVDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PWR_PVDTypeDef Struct Reference
PWR Exported Types

PWR PVD configuration structure definition. More...

#include <stm32h7xx_hal_pwr.h>

Data Fields

uint32_t | PVDLevel
uint32_t | Mode

Detailed Description

PWR PVD configuration structure definition.

Definition at line 66 of file stm32h7xx_hal_pwr.h.

Field Documentation

uint32_t PWR_PVDTypeDef::Mode

Mode: Specifies the operating mode for the selected pins. This parameter can be a value of PWR PVD Mode

Definition at line 71 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

uint32_t PWR_PVDTypeDef::PVDLevel

PVDLevel: Specifies the PVD detection level. This parameter can be a value of PWR PVD detection level

Definition at line 68 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_pwr.h
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STM32H753xx HAL User Manual: PWR PVD detection level

Defines
PWR PVD detection level
PWR Exported Constants

Defines

#define | PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0
#define | PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1
#define | PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2
#define | PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3
#define | PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4
#define | PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5
#define | PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6
#define | PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7/* External input analog voltage (Compare internally to VREFINT) */

Define Documentation

#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0

Definition at line 87 of file stm32h7xx_hal_pwr.h.

#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1

Definition at line 88 of file stm32h7xx_hal_pwr.h.

#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2

Definition at line 89 of file stm32h7xx_hal_pwr.h.

#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3

Definition at line 90 of file stm32h7xx_hal_pwr.h.

#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4

Definition at line 91 of file stm32h7xx_hal_pwr.h.

#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5

Definition at line 92 of file stm32h7xx_hal_pwr.h.

#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6

Definition at line 93 of file stm32h7xx_hal_pwr.h.

#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7/* External input analog voltage (Compare internally to VREFINT) */

Definition at line 94 of file stm32h7xx_hal_pwr.h.

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STM32H753xx HAL User Manual: PWR PVD Mode

Defines
PWR PVD Mode
PWR Exported Constants

Defines

#define | PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U)
#define | PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U)
#define | PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U)
#define | PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U)
#define | PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U)
#define | PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U)
#define | PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U)

Define Documentation

#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U)

Event Mode with Falling edge trigger detection

Definition at line 107 of file stm32h7xx_hal_pwr.h.

#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U)

Event Mode with Rising edge trigger detection

Definition at line 106 of file stm32h7xx_hal_pwr.h.

#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U)

Event Mode with Rising/Falling edge trigger detection

Definition at line 108 of file stm32h7xx_hal_pwr.h.

#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U)

External Interrupt Mode with Falling edge trigger detection

Definition at line 104 of file stm32h7xx_hal_pwr.h.

#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U)

External Interrupt Mode with Rising edge trigger detection

Definition at line 103 of file stm32h7xx_hal_pwr.h.

#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 105 of file stm32h7xx_hal_pwr.h.

#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U)

Basic mode is used

Definition at line 102 of file stm32h7xx_hal_pwr.h.

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STM32H753xx HAL User Manual: PWR Regulator state in SLEEP/STOP mode

Defines
PWR Regulator state in SLEEP/STOP mode
PWR Exported Constants

Defines

#define | PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)
#define | PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS

Define Documentation

#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS

Definition at line 117 of file stm32h7xx_hal_pwr.h.

#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)

Definition at line 116 of file stm32h7xx_hal_pwr.h.

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STM32H753xx HAL User Manual: PWR SLEEP mode entry

Defines
PWR SLEEP mode entry
PWR Exported Constants

Defines

#define | PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)
#define | PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)

Define Documentation

#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)

Definition at line 126 of file stm32h7xx_hal_pwr.h.

#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)

Definition at line 125 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

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STM32H753xx HAL User Manual: PWR STOP mode entry

Defines
PWR STOP mode entry
PWR Exported Constants

Defines

#define | PWR_STOPENTRY_WFI ((uint8_t)0x01U)
#define | PWR_STOPENTRY_WFE ((uint8_t)0x02U)

Define Documentation

#define PWR_STOPENTRY_WFE ((uint8_t)0x02U)

Definition at line 135 of file stm32h7xx_hal_pwr.h.

#define PWR_STOPENTRY_WFI ((uint8_t)0x01U)

Definition at line 134 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTOPMode(), and HAL_PWREx_EnterSTOPMode().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PWR Regulator Voltage Scale

Defines
PWR Regulator Voltage Scale
PWR Exported Constants

Defines

#define | PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
#define | PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1)
#define | PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0)

Define Documentation

#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)

Definition at line 143 of file stm32h7xx_hal_pwr.h.

#define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1)

Definition at line 144 of file stm32h7xx_hal_pwr.h.

#define PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0)

Definition at line 145 of file stm32h7xx_hal_pwr.h.

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STM32H753xx HAL User Manual: PWR Flag

Defines
PWR Flag
PWR Exported Constants

Defines

#define | PWR_FLAG_STOP ((uint8_t)0x01U)
#define | PWR_FLAG_SB_D1 ((uint8_t)0x02U)
#define | PWR_FLAG_SB_D2 ((uint8_t)0x03U)
#define | PWR_FLAG_SB ((uint8_t)0x04U)
#define | PWR_FLAG_PVDO ((uint8_t)0x07U)
#define | PWR_FLAG_AVDO ((uint8_t)0x08U)
#define | PWR_FLAG_ACTVOSRDY ((uint8_t)0x09U)
#define | PWR_FLAG_ACTVOS ((uint8_t)0x0AU)
#define | PWR_FLAG_BRR ((uint8_t)0x0BU)
#define | PWR_FLAG_VOSRDY ((uint8_t)0x0CU)
#define | PWR_FLAG_SCUEN ((uint8_t)0x0DU)

Define Documentation

#define PWR_FLAG_ACTVOS ((uint8_t)0x0AU)

Definition at line 160 of file stm32h7xx_hal_pwr.h.

#define PWR_FLAG_ACTVOSRDY ((uint8_t)0x09U)

Definition at line 159 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWREx_ConfigSupply().

#define PWR_FLAG_AVDO ((uint8_t)0x08U)

Definition at line 158 of file stm32h7xx_hal_pwr.h.

#define PWR_FLAG_BRR ((uint8_t)0x0BU)

Definition at line 161 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWREx_DisableBkUpReg(), and HAL_PWREx_EnableBkUpReg().

#define PWR_FLAG_PVDO ((uint8_t)0x07U)

Definition at line 157 of file stm32h7xx_hal_pwr.h.

#define PWR_FLAG_SB ((uint8_t)0x04U)

Definition at line 156 of file stm32h7xx_hal_pwr.h.

#define PWR_FLAG_SB_D1 ((uint8_t)0x02U)

Definition at line 154 of file stm32h7xx_hal_pwr.h.

#define PWR_FLAG_SB_D2 ((uint8_t)0x03U)

Definition at line 155 of file stm32h7xx_hal_pwr.h.

#define PWR_FLAG_SCUEN ((uint8_t)0x0DU)

Definition at line 163 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWREx_ConfigSupply().

#define PWR_FLAG_STOP ((uint8_t)0x01U)

Definition at line 153 of file stm32h7xx_hal_pwr.h.

#define PWR_FLAG_VOSRDY ((uint8_t)0x0CU)

Definition at line 162 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWREx_ControlVoltageScaling().

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STM32H753xx HAL User Manual: PWR Enable WUP Mask

Defines
PWR Enable WUP Mask
PWR Exported Constants

Defines

#define PWR_EWUP_MASK ((uint32_t)0x0FFF3F3FU)

Define Documentation

#define PWR_EWUP_MASK ((uint32_t)0x0FFF3F3FU)

Definition at line 171 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_EnableWakeUpPin(), and HAL_PWREx_EnableWakeUpPin().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PWR Exported Macro

Defines
PWR Exported Macro
PWR

Defines

#define | __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)
macros configure the main internal regulator output voltage.
#define | __HAL_PWR_GET_FLAG(__FLAG__)
Check PWR PVD/AVD and VOSflags are set or not.
#define | __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
Clear the PWR's flags.
#define | __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_PVD)
Enable the PVD EXTI Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_PVD)
Disable the PVD EXTI Line 16.
#define | __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_PVD)
Enable event on PVD EXTI Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_PVD)
Disable event on PVD EXTI Line 16.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
PVD EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_GET_FLAG() READ_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_PVD)
Check whether the specified PVD EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_PVD)
Clear the PVD EXTI flag.
#define | __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
Generates a Software interrupt on PVD EXTI line.

Define Documentation

#define __HAL_PWR_CLEAR_FLAG ( __FLAG__ ) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)

Clear the PWR's flags.

Parameters:
__FLAG__,: specifies the flag to clear. This parameter can be one of the following values:
  • PWR_FLAG_SB: StandBy flag.
  • PWR_CPU_FLAGS: Clear STOPF, SBF, SBF_D1, and SBF_D2 CPU flags.
Return values:
None.

Definition at line 247 of file stm32h7xx_hal_pwr.h.

#define __HAL_PWR_GET_FLAG ( __FLAG__ )
Value:
( \
((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \
((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \
((__FLAG__) == PWR_FLAG_ACTVOSRDY)?((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) : \
((__FLAG__) == PWR_FLAG_VOSRDY)?((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) : \
((__FLAG__) == PWR_FLAG_SCUEN)?((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) : \
((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \
((__FLAG__) == PWR_FLAG_SB)?((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) : \
((__FLAG__) == PWR_FLAG_STOP)?((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : \
((__FLAG__) == PWR_FLAG_SB_D1)?((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) : \
((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2))

Check PWR PVD/AVD and VOSflags are set or not.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode For this reason, this bit is equal to 0 after Standby or reset until the PVDE bit is set.
  • PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode For this reason, this bit is equal to 0 after Standby or reset until the AVDE bit is set.
  • PWR_FLAG_ACTVOSRDY: This flag indicates that the Regulator voltage scaling output selection is ready.
  • PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage scaling output selection is ready.
  • PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset when the device wakes up from Standby mode or by a system reset or power reset.
  • PWR_FLAG_SB: StandBy flag
  • PWR_FLAG_STOP: STOP flag
  • PWR_FLAG_SB_D1: StandBy D1 flag
  • PWR_FLAG_SB_D2: StandBy D2 flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 227 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWREx_ConfigSupply(), HAL_PWREx_ControlVoltageScaling(), HAL_PWREx_DisableBkUpReg(), and HAL_PWREx_EnableBkUpReg().

#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG ( ) SET_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_PVD)

Clear the PVD EXTI flag.

Return values:
None.

Definition at line 334 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_PVD_IRQHandler(), and HAL_PWREx_PVD_AVD_IRQHandler().

#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_PVD)

Disable event on PVD EXTI Line 16.

Return values:
None.

Definition at line 274 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt Falling Trigger.

Return values:
None.

Definition at line 300 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_PVD)

Disable the PVD EXTI Line 16.

Return values:
None.

Definition at line 260 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt Rising Trigger.

Return values:
None.

Definition at line 287 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
      __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
      __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
} while(0);

Disable the PVD Extended Interrupt Rising & Falling Trigger.

Return values:
None.

Definition at line 317 of file stm32h7xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_PVD)

Enable event on PVD EXTI Line 16.

Return values:
None.

Definition at line 267 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)

Enable the PVD Extended Interrupt Falling Trigger.

Return values:
None.

Definition at line 293 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_IT ( ) SET_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_PVD)

Enable the PVD EXTI Line 16.

Return values:
None.

Definition at line 253 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)

Enable the PVD Extended Interrupt Rising Trigger.

Return values:
None.

Definition at line 281 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
      __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
} while(0);

PVD EXTI line configuration: set rising & falling edge trigger.

Return values:
None.

Definition at line 307 of file stm32h7xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)

Generates a Software interrupt on PVD EXTI line.

Return values:
None.

Definition at line 341 of file stm32h7xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_GET_FLAG ( ) READ_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_PVD)

Check whether the specified PVD EXTI interrupt flag is set or not.

Return values:
EXTI PVD Line Status.

Definition at line 327 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_PVD_IRQHandler(), and HAL_PWREx_PVD_AVD_IRQHandler().

#define __HAL_PWR_VOLTAGESCALING_CONFIG ( __REGULATOR__ )
Value:
do { \
      __IO uint32_t tmpreg = 0x00; \
      MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \
      /* Delay after an RCC peripheral clock enabling */  \
      tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
      UNUSED(tmpreg); \
} while(0)

macros configure the main internal regulator output voltage.

Parameters:
__REGULATOR__,: specifies the regulator output voltage to achieve a tradeoff between performance and power consumption when the device does not operate at the maximum frequency (refer to the datasheets for more details). This parameter can be one of the following values:
  • PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
  • PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
  • PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
Return values:
None

Definition at line 194 of file stm32h7xx_hal_pwr.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PWR PVD Mode Mask

Defines
PWR PVD Mode Mask
PWR Private Constants

Defines

#define | PVD_MODE_IT ((uint32_t)0x00010000U)
#define | PVD_MODE_EVT ((uint32_t)0x00020000U)
#define | PVD_RISING_EDGE ((uint32_t)0x00000001U)
#define | PVD_FALLING_EDGE ((uint32_t)0x00000002U)
#define | PVD_RISING_FALLING_EDGE ((uint32_t)0x00000003U)

Define Documentation

#define PVD_FALLING_EDGE ((uint32_t)0x00000002U)

Definition at line 69 of file stm32h7xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_MODE_EVT ((uint32_t)0x00020000U)

Definition at line 67 of file stm32h7xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_MODE_IT ((uint32_t)0x00010000U)

Definition at line 66 of file stm32h7xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_RISING_EDGE ((uint32_t)0x00000001U)

Definition at line 68 of file stm32h7xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_RISING_FALLING_EDGE ((uint32_t)0x00000003U)

Definition at line 70 of file stm32h7xx_hal_pwr.c.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PWR PVD EXTI Line

Defines
PWR PVD EXTI Line
PWR Private Constants

Defines

#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR1_IM16)

Define Documentation

#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR1_IM16)

< External interrupt line 16 Connected to the PVD EXTI Line

Definition at line 412 of file stm32h7xx_hal_pwr.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PWR Private macros to check input parameters

Defines
PWR Private macros to check input parameters
PWR Private Macros

Defines

#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | IS_PWR_PVD_MODE(MODE)
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define | IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
#define | IS_PWR_REGULATOR_VOLTAGE(VOLTAGE)

Define Documentation

#define IS_PWR_PVD_LEVEL ( LEVEL )
Value:
(((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))

Definition at line 428 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define IS_PWR_PVD_MODE ( MODE )
Value:
(((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
                              ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
                              ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
                              ((MODE) == PWR_PVD_MODE_NORMAL))

Definition at line 432 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define IS_PWR_REGULATOR ( REGULATOR )
Value:
(((REGULATOR) == PWR_MAINREGULATOR_ON) || \
                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))

Definition at line 436 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode(), HAL_PWR_EnterSTOPMode(), and HAL_PWREx_EnterSTOPMode().

#define IS_PWR_REGULATOR_VOLTAGE ( VOLTAGE )
Value:
(((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))

Definition at line 440 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWREx_ControlVoltageScaling().

#define IS_PWR_SLEEP_ENTRY ( ENTRY ) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))

Definition at line 438 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

#define IS_PWR_STOP_ENTRY ( ENTRY ) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))

Definition at line 439 of file stm32h7xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTOPMode(), and HAL_PWREx_EnterSTOPMode().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Power supply control functions

Functions
Power supply control functions
PWREx Exported Functions

Power supply control functions. More...

Functions

HAL_StatusTypeDef | HAL_PWREx_ConfigSupply (uint32_t SupplySource)
Configure the system Power Supply.
uint32_t | HAL_PWREx_GetSupplyConfig (void)
Get the power supply configuration.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configure the main internal regulator output voltage.
uint32_t | HAL_PWREx_GetVoltageRange (void)
Get the main internal regulator output voltage.
HAL_StatusTypeDef | HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling)
Configure the main internal regulator output voltage in STOP mode.
uint32_t | HAL_PWREx_GetStopModeVoltageRange (void)
Get the main internal regulator output voltage in STOP mode.

Detailed Description

Power supply control functions.

 ===============================================================================
                 ##### Power supply control functions #####
 ===============================================================================

    *** Power supply configuration ***
    ==================================
    [..]
      When the system is powered on, the POR monitors VDD supply. Once VDD is above the
      POR threshold level, the voltage regulator is enabled in the default supply
      configuration:
      (+) The Voltage converter output level is set at 1.0 V in accordance with the VOS3
          level configured in PWR D3 domain control register (PWR_D3CR).
      (+) The system is kept in reset mode as long as VCORE is not ok.
      (+) Once VCORE is ok, the system is taken out of reset and the HSI oscillator is enabled.
      (+) Once the oscillator is stable, the system is initialized: Flash memory and option
          bytes are loaded and the CPU starts in Run* mode.
      (+) The software shall then initialize the system including supply configuration
          programming using the HAL_PWREx_ConfigSupply(SupplySource) with:
       (++) SupplySource:
        (+++) PWR_LDO_SUPPLY: VCORE Power Domains are supplied from the LDO according to
                              VOS. LDO power mode (Main, LP, Off) will follow system low-power
                              modes.
        (+++) PWR_EXTERNAL_SOURCE_SUPPLY: VCORE supplied from external source and LDO bypassed,
                                          voltage monitoring still active.
      (+) Once the supply configuration  has been configured, the HAL_PWREx_ConfigSupply
          function checks the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1)
          to guarantee a valid voltage levels:
       (++) As long as ACTVOSRDY indicates that voltage levels are invalid, the system is in
            limited Run* mode, write accesses to the RAMs are not permitted and VOS shall
            not be changed.
       (++) Once ACTVOSRDY indicates that voltage levels are valid, the system is in normal
            Run mode, write accesses to RAMs are allowed and VOS can be changed.

Function Documentation

HAL_StatusTypeDef HAL_PWREx_ConfigSupply ( uint32_t SupplySource )

Configure the system Power Supply.

Parameters:
SupplySource,: Specifies the Power Supply source. This parameter can be one of the following values:
  • PWR_LDO_SUPPLY: The LDO supplies the Vcore Power Domains.
  • PWR_EXTERNAL_SOURCE_SUPPLY: The Vcore Power Domains are supplied from external power source. The LDO is Bypassed.
Return values:
HAL status.

Definition at line 149 of file stm32h7xx_hal_pwr_ex.c.

References __HAL_PWR_GET_FLAG, assert_param, HAL_GetTick(), IS_PWR_SUPPLY, PWR_FLAG_ACTVOSRDY, PWR_FLAG_SCUEN, PWR_FLAG_SETTING_DELAY_US, and PWR_SUPPLY_CONFIG_MASK.

HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling ( uint32_t VoltageScaling )

Configure the main internal regulator output voltage in STOP mode.

Parameters:
VoltageScaling,: Specifies the regulator output voltage when the system enters STOP mode to achieve a tradeoff between performance and power consumption. This parameter can be one of the following values:
  • PWR_REGULATOR_SVOS_SCALE3: Regulator voltage output range 3 mode.
  • PWR_REGULATOR_SVOS_SCALE4: Regulator voltage output range 4 mode.
  • PWR_REGULATOR_SVOS_SCALE5: Regulator voltage output range 5 mode.
Note:
The Stop mode voltage scaling for SVOS4 and SVOS5 sets the voltage regulator in Low-power (LP) mode to further reduce power consumption. When preselecting SVOS3, the use of the voltage regulator low-power mode (LP) can be selected by LPDS register bit.
The selected SVOS4 and SVOS5 levels add an additional startup delay when exiting from system Stop mode.
Return values:
HAL Status

Definition at line 252 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, and IS_PWR_STOP_MODE_REGULATOR_VOLTAGE.

HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling ( uint32_t VoltageScaling )

Configure the main internal regulator output voltage.

Parameters:
VoltageScaling,: Specifies the regulator output voltage to achieve a tradeoff between performance and power consumption. This parameter can be one of the following values:
  • PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode.
  • PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode.
  • PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode.
Note:
When moving from Range 1 to Range 2, the system frequency must be decreased before calling HAL_PWREx_ControlVoltageScaling() API. When moving from Range 2 to Range 1, the system frequency can be increased after calling HAL_PWREx_ControlVoltageScaling() API.
When moving from a Range to an other one, the API waits for VOSRDY flag to be set before returning the status. If the flag is not set within 1000 microseconds, HAL_TIMEOUT status is reported.
Return values:
HAL Status

Definition at line 202 of file stm32h7xx_hal_pwr_ex.c.

References __HAL_PWR_GET_FLAG, assert_param, HAL_GetTick(), IS_PWR_REGULATOR_VOLTAGE, PWR_FLAG_SETTING_DELAY_US, and PWR_FLAG_VOSRDY.

uint32_t HAL_PWREx_GetStopModeVoltageRange ( void )

Get the main internal regulator output voltage in STOP mode.

Return values:
The actual applied VOS for VDD11 Voltage Scaling selection.

Definition at line 266 of file stm32h7xx_hal_pwr_ex.c.

uint32_t HAL_PWREx_GetSupplyConfig ( void )

Get the power supply configuration.

Return values:
The supply configuration.

Definition at line 179 of file stm32h7xx_hal_pwr_ex.c.

References PWR_SUPPLY_CONFIG_MASK.

uint32_t HAL_PWREx_GetVoltageRange ( void )

Get the main internal regulator output voltage.

Reflecting the last VOS value applied to the PMU.

Return values:
The actual applied VOS for VDD11 Voltage Scaling selection.

Definition at line 231 of file stm32h7xx_hal_pwr_ex.c.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Low power control functions

Functions
Low power control functions
PWREx Exported Functions

Low power control functions. More...

Functions

void | HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain)
Enter a Domain to DSTOP mode.
void | HAL_PWREx_EnterSTANDBYMode (uint32_t Domain)
Enter a Domain to DSTANDBY mode.
void | HAL_PWREx_ConfigD3Domain (uint32_t D3State)
Configure the D3 Domain state when the CPU is in low power mode.
void | HAL_PWREx_EnableFlashPowerDown (void)
Enable the Flash Power Down in Stop mode.
void | HAL_PWREx_DisableFlashPowerDown (void)
Disable the Flash Power Down in Stop mode.
void | HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams)
Enable the Wake-up PINx functionality.
void | HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the Wake-up PINx functionality.
uint32_t | HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag)
Get the Wake-Up Pin flag.
HAL_StatusTypeDef | HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag)
Clear the Wake-Up pin flag.
void | HAL_PWREx_WAKEUP_PIN_IRQHandler (void)
This function handles the PWR WAKEUP PIN interrupt request.
__weak void | HAL_PWREx_WKUP1_Callback (void)
PWR WKUP1 interrupt callback.
__weak void | HAL_PWREx_WKUP2_Callback (void)
PWR WKUP2 interrupt callback.
__weak void | HAL_PWREx_WKUP3_Callback (void)
PWR WKUP3 interrupt callback.
__weak void | HAL_PWREx_WKUP4_Callback (void)
PWR WKUP4 interrupt callback.
__weak void | HAL_PWREx_WKUP5_Callback (void)
PWR WKUP5 interrupt callback.
__weak void | HAL_PWREx_WKUP6_Callback (void)
PWR WKUP6 interrupt callback.

Detailed Description

Low power control functions.

 ===============================================================================
                 ##### Low power control functions #####
 ===============================================================================

    *** Domains Low Power modes configuration ***
    =============================================
    [..]
      The system present 3 principles domains (D1, D2 and D3) that can be operated
      in low-power modes (DSTOP or DSTANDBY mode):

      (+) DSTOP mode to enters a domain to STOP mode:
       (++) D1 domain and/or D2 domain enters DSTOP mode only when the CPU
            subsystem is in CSTOP mode and has allocated peripheral in the domain.
            In DSTOP mode the domain bus matrix clock is stopped.
       (++) The system enters STOP mode using one of the following scenarios:
        (+++) D1 domain enters DSTANDBY mode (powered off) and D2, D3 domains enter DSTOP mode.
        (+++) D2 domain enters DSTANDBY mode (powered off) and D1, D3 domains enter DSTOP mode.
        (+++) D3 domain enters DSTANDBY mode (powered off) and D1, D2 domains enter DSTOP mode.
        (+++) D1 and D2 domains enter DSTANDBY mode (powered off) and D3 domain enters DSTOP mode.
        (+++) D1 and D3 domains enter DSTANDBY mode (powered off) and D2 domain enters DSTOP mode.
        (+++) D2 and D3 domains enter DSTANDBY mode (powered off) and D1 domain enters DSTOP mode.
        (+++) D1, D2 and D3 domains enter DSTOP mode.
       (++) When the system enters STOP mode, the clocks are stopped and the regulator is running
            in main or low power mode.
       (++) D3 domain can be kept in Run mode regardless of the CPU status when enter
            STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function.

      (+) DSTANDBY mode to enters a domain to STANDBY mode:
       (++) The DSTANDBY mode is entered when the PDDS_Dn bit in PWR CPU control register
            (PWR_CPUCR) for the Dn domain selects Standby mode.
       (++) The system enters STANDBY mode only when D1, D2 and D3 domains enter DSTANDBY mode.
            Consequently the VCORE supply regulator is powered off.

   *** DSTOP mode ***
   ==================
    [..]
      In DStop mode the domain bus matrix clock is stopped.
      The Flash memory can enter low-power Stop mode when it is enabled through FLPS in
      PWR_CR1 register. This allows a trade-off between domain DStop restart time and low
      power consumption.
    [..]
      In DStop mode domain peripherals using the LSI or LSE clock and peripherals having a
      kernel clock request are still able to operate.
    [..]
      Before entering DSTOP mode it is recommended to call SCB_CleanDCache function
      in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.

      (+) Entry:
         The DSTOP mode is entered using the HAL_PWREx_EnterSTOPMode(Regulator, STOPEntry, Domain)
         function with:
         (++) Regulator:
          (+++) PWR_MAINREGULATOR_ON: Main regulator ON.
          (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
         (++) STOPEntry:
          (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction
          (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
         (++) Domain:
          (+++) PWR_D1_DOMAIN: Enters D1 domain to DSTOP mode.
          (+++) PWR_D2_DOMAIN: Enters D2 domain to DSTOP mode.
          (+++) PWR_D3_DOMAIN: Enters D3 domain to DSTOP mode.

      (+) Exit:
        Any EXTI Line (Internal or External) configured in Interrupt/Event mode.

   *** DSTANDBY mode ***
   ====================
    [..]
      In DStandby mode:
        (+) The domain bus matrix clock is stopped.
        (+) The domain is powered down and the domain RAM and register contents are lost.
    [..]
      Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache function
      in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.

      (+) Entry:
         The DSTANDBY mode is entered using the HAL_PWREx_EnterSTANDBYMode(Domain) function with:
       (++) Domain:
        (+++) PWR_D1_DOMAIN: Enters D1 domain to DSTANDBY mode.
        (+++) PWR_D2_DOMAIN: Enters D2 domain to DSTANDBY mode.
        (+++) PWR_D3_DOMAIN: Enters D3 domain to DSTANDBY mode.

      (+) Exit:
        WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
        wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.

   *** Keep D3 in RUN mode ***
   ===========================
    [..]
      D3 domain can be kept in Run mode regardless of the CPU status when enter
      STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function with:
       (+) D3State:
        (++) PWR_D3_DOMAIN_STOP: D3 domain will follow the CPU sub-system mode.
        (++) PWR_D3_DOMAIN_RUN: D3 domain remains in Run mode regardless of CPU subsystem mode.

    *** FLASH Power Down configuration ****
    =======================================
    [..]
      By setting the FLPS bit in the PWR_CR1 register using the HAL_PWREx_EnableFlashPowerDown()
      function, the Flash memory also enters power down mode when the device enters Stop mode.
      When the Flash memory is in power down mode, an additional startup delay is incurred when
      waking up from Stop mode.

    *** Wakeup Pins configuration ****
    ===================================
    [..]
      Wakeup pins allow the system to exit from Standby mode. The configuration of
      wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams) function with:
       (+) sPinParams: structure to enable and configure a wakeup pin:
        (++) WakeUpPin: Wakeup pin to be enabled.
        (++) PinPolarity: Wakeup pin polarity (rising or falling edge).
        (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down).
    [..]
      The wakeup pins are internally connected to the EXTI lines [55-60] to generate an interrupt
      if enabled. The EXTI lines configuration is done in the HAL_PWREx_EnableWakeUpPin() function.
    [..]
      When a wakeup pin event is received the HAL_PWREx_WAKEUP_PIN_IRQHandler is called
      and the appropriate flag is set in the PWR_WKUPFR register. Then in the HAL_PWREx_WAKEUP_PIN_IRQHandler
      function the wakeup pin flag will be cleared and the appropriate user callback will be called.
      The user can add his own code by customization of function pointer HAL_PWREx_WKUPx_Callback.

Function Documentation

HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag ( uint32_t WakeUpFlag )

Clear the Wake-Up pin flag.

Parameters:
WakeUpFlag,: Specifies the Wake-Up PIN flag to clear. This parameter can be one of the following values:
  • PWR_WAKEUP_FLAG1: Clear the wakeup event received from PA0.
  • PWR_WAKEUP_FLAG2: Clear the wakeup event received from PA2.
  • PWR_WAKEUP_FLAG3: Clear the wakeup event received from PC1.
  • PWR_WAKEUP_FLAG4: Clear the wakeup event received from PC13.
  • PWR_WAKEUP_FLAG5: Clear the wakeup event received from PI8.
  • PWR_WAKEUP_FLAG6: Clear the wakeup event received from PI11.
Return values:
HAL status.

Definition at line 665 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, and IS_PWR_WAKEUP_FLAG.

void HAL_PWREx_ConfigD3Domain ( uint32_t D3State )

Configure the D3 Domain state when the CPU is in low power mode.

Parameters:
D3State,: Specifies the D3 state. This parameter can be one of the following values:
  • PWR_D3_DOMAIN_STOP: D3 domain will follow the CPU sub-system mode.
  • PWR_D3_DOMAIN_RUN : D3 domain will stay in RUN mode regardless of the CPU sub-system mode.
Return values:
None

Definition at line 552 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, and IS_D3_STATE.

void HAL_PWREx_DisableFlashPowerDown ( void )

Disable the Flash Power Down in Stop mode.

Return values:
None

Definition at line 579 of file stm32h7xx_hal_pwr_ex.c.

void HAL_PWREx_DisableWakeUpPin ( uint32_t WakeUpPin )

Disable the Wake-up PINx functionality.

Parameters:
WakeUpPin,: Specifies the Wake-Up pin to be disabled. This parameter can be one of the following values:
  • PWR_WAKEUP_PIN1: Disable PA0 wake-up PIN.
  • PWR_WAKEUP_PIN2: Disable PA2 wake-up PIN..
  • PWR_WAKEUP_PIN3: Disable PI8 wake-up PIN..
  • PWR_WAKEUP_PIN4: Disable PC13 wake-up PIN..
  • PWR_WAKEUP_PIN5: Disable PI11 wake-up PIN..
  • PWR_WAKEUP_PIN6: Disable PC1 wake-up PIN..
Return values:
None

Definition at line 624 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, and IS_PWR_WAKEUP_PIN.

void HAL_PWREx_EnableFlashPowerDown ( void )

Enable the Flash Power Down in Stop mode.

Return values:
None

Definition at line 569 of file stm32h7xx_hal_pwr_ex.c.

void HAL_PWREx_EnableWakeUpPin ( PWREx_WakeupPinTypeDef * sPinParams )

Enable the Wake-up PINx functionality.

Parameters:
sPinParams,: pointer to an PWREx_WakeupPinTypeDef structure that contains the configuration informations for the wake-up Pin.
Return values:
None

Definition at line 591 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, IS_PWR_WAKEUP_PIN, IS_PWR_WAKEUP_PIN_POLARITY, IS_PWR_WAKEUP_PIN_PULL, PWREx_WakeupPinTypeDef::PinPolarity, PWREx_WakeupPinTypeDef::PinPull, PWR_EWUP_MASK, PWR_EXTI_WAKEUP_PINS_MASK, and PWREx_WakeupPinTypeDef::WakeUpPin.

void HAL_PWREx_EnterSTANDBYMode ( uint32_t Domain )

Enter a Domain to DSTANDBY mode.

Note:
The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for the Dn domain select Standby mode. When the system enters Standby mode, the voltage regulator is disabled.
When D2 or D3 domain is in DStandby mode and the CPU sets the domain PDDS_Dn bit to select Stop mode, the domain remains in DStandby mode. The domain will only exit DStandby when the CPU allocates a peripheral in the domain.
The system D3 domain enters Standby mode only when the D1 and D2 domain are in DStandby.
Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache function in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.
Parameters:
Domain,: Specifies the Domain to enter to STANDBY mode. This parameter can be one of the following values:
  • PWR_D1_DOMAIN: Enter D1 Domain to DSTANDBY mode.
  • PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode.
  • PWR_D3_DOMAIN: Enter D3 Domain to DSTANDBY mode.
Return values:
None

Definition at line 506 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, IS_PWR_DOMAIN, PWR_D1_DOMAIN, and PWR_D2_DOMAIN.

void HAL_PWREx_EnterSTOPMode | ( | uint32_t | Regulator,
 |  | uint8_t | STOPEntry,
 |  | uint32_t | Domain
 | ) |  |

Enter a Domain to DSTOP mode.

Note:
In DStop mode the domain bus matrix clock is stopped.
The system D3 domain enters Stop mode only when the CPU subsystem is in CStop mode, the EXTI wakeup sources are inactive and at least one PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for any domain request Stop.
In system D3 domain Stop mode, D1 domain and D2 domain are either in DStop and/or DStandby mode.
Before entering DSTOP mode it is recommended to call SCB_CleanDCache function in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.
In System Stop mode, the domain peripherals that use the LSI or LSE clock, and the peripherals that have a kernel clock request to select HSI or CSI as source, are still able to operate.
Parameters:
Regulator,: Specifies the regulator state in Stop mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON: Stop mode with regulator ON
  • PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
STOPEntry,: Specifies if Stop mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_STOPENTRY_WFI: Enter DStop mode with WFI instruction
  • PWR_STOPENTRY_WFE: Enter DStop mode with WFE instruction
Domain,: Specifies the Domain to enter STOP mode. This parameter can be one of the following values:
  • PWR_D1_DOMAIN: Enter D1 Domain to DSTOP mode.
  • PWR_D2_DOMAIN: Enter D2 Domain to DSTOP mode.
  • PWR_D3_DOMAIN: Enter D3 Domain to DSTOP mode.
Return values:
None

Definition at line 432 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, IS_PWR_DOMAIN, IS_PWR_REGULATOR, IS_PWR_STOP_ENTRY, PWR_D1_DOMAIN, PWR_D2_DOMAIN, and PWR_STOPENTRY_WFI.

uint32_t HAL_PWREx_GetWakeupFlag ( uint32_t WakeUpFlag )

Get the Wake-Up Pin flag.

Parameters:
WakeUpFlag,: Specifies the Wake-Up PIN flag to check. This parameter can be one of the following values:
  • PWR_WAKEUP_FLAG1: A wakeup event was received from PA0.
  • PWR_WAKEUP_FLAG2: A wakeup event was received from PA2.
  • PWR_WAKEUP_FLAG3: A wakeup event was received from PC1.
  • PWR_WAKEUP_FLAG4: A wakeup event was received from PC13.
  • PWR_WAKEUP_FLAG5: A wakeup event was received from PI8.
  • PWR_WAKEUP_FLAG6: A wakeup event was received from PI11.
Return values:
The Wake-Up pin flag.

Definition at line 645 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, and IS_PWR_WAKEUP_FLAG.

void HAL_PWREx_WAKEUP_PIN_IRQHandler ( void )

This function handles the PWR WAKEUP PIN interrupt request.

Note:
This API should be called under the WAKEUP_PIN_IRQHandler().
Return values:
None

Definition at line 685 of file stm32h7xx_hal_pwr_ex.c.

References HAL_PWREx_WKUP1_Callback(), HAL_PWREx_WKUP2_Callback(), HAL_PWREx_WKUP3_Callback(), HAL_PWREx_WKUP4_Callback(), HAL_PWREx_WKUP5_Callback(), and HAL_PWREx_WKUP6_Callback().

void HAL_PWREx_WKUP1_Callback ( void )

PWR WKUP1 interrupt callback.

Return values:
None

Definition at line 742 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_WAKEUP_PIN_IRQHandler().

void HAL_PWREx_WKUP2_Callback ( void )

PWR WKUP2 interrupt callback.

Return values:
None

Definition at line 753 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_WAKEUP_PIN_IRQHandler().

void HAL_PWREx_WKUP3_Callback ( void )

PWR WKUP3 interrupt callback.

Return values:
None

Definition at line 764 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_WAKEUP_PIN_IRQHandler().

void HAL_PWREx_WKUP4_Callback ( void )

PWR WKUP4 interrupt callback.

Return values:
None

Definition at line 775 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_WAKEUP_PIN_IRQHandler().

void HAL_PWREx_WKUP5_Callback ( void )

PWR WKUP5 interrupt callback.

Return values:
None

Definition at line 786 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_WAKEUP_PIN_IRQHandler().

void HAL_PWREx_WKUP6_Callback ( void )

PWR WKUP6 interrupt callback.

Return values:
None

Definition at line 797 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_WAKEUP_PIN_IRQHandler().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripherals control functions

Functions
Peripherals control functions
PWREx Exported Functions

Peripherals control functions. More...

Functions

HAL_StatusTypeDef | HAL_PWREx_EnableBkUpReg (void)
Enable the Backup Regulator.
HAL_StatusTypeDef | HAL_PWREx_DisableBkUpReg (void)
Disable the Backup Regulator.
HAL_StatusTypeDef | HAL_PWREx_EnableUSBReg (void)
Enable the USB Regulator.
HAL_StatusTypeDef | HAL_PWREx_DisableUSBReg (void)
Disable the USB Regulator.
void | HAL_PWREx_EnableUSBVoltageDetector (void)
Enable the USB voltage level detector.
void | HAL_PWREx_DisableUSBVoltageDetector (void)
Disable the USB voltage level detector.
void | HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue)
Enable the Battery charging.
void | HAL_PWREx_DisableBatteryCharging (void)
Disable the Battery charging.

Detailed Description

Peripherals control functions.

 ===============================================================================
                 ##### Peripherals control functions #####
 ===============================================================================

    *** Main and Backup Regulators configuration ***
    ================================================
    [..]
      (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
          the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
          retained even in Standby or VBAT mode when the low power backup regulator
          is enabled. It can be considered as an internal EEPROM when VBAT is
          always present. You can use the HAL_PWREx_EnableBkUpReg() function to
          enable the low power backup regulator.
      (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
          the backup SRAM is powered from VDD which replaces the VBAT power supply to
          save battery life.
      (+) The backup SRAM is not mass erased by a tamper event. It is read
          protected to prevent confidential data, such as cryptographic private
          key, from being accessed. The backup SRAM can be erased only through
          the Flash interface when a protection level change from level 1 to
          level 0 is requested.
      -@- Refer to the description of Read protection (RDP) in the Flash
          programming manual.
      (+) The main internal regulator can be configured to have a tradeoff between
          performance and power consumption when the device does not operate at
          the maximum frequency. This is done through HAL_PWREx_ControlVoltageScaling(VOS)
          function which configure the VOS bit in PWR_D3CR register.
      (+) The main internal regulator can be configured to operate in Low Power mode
          when the system enter STOP mode to further reduce power consumption.
          This is done through HAL_PWREx_ControlStopModeVoltageScaling(SVOS)
          function which configure the SVOS bit in PWR_CR1 register.
          The selected SVOS4 and SVOS5 levels add an additional startup delay when exiting from
          system Stop mode.
    -@- Refer to the product datasheets for more details.

    *** USB Regulator configuration ***
    ===================================
    [..]
      (+) The USB transceivers are supplied from a dedicated VDD33USB supply that can be
          provided either by the integrated USB regulator, or by an external USB supply.
      (+) The USB regulator is enabled by HAL_PWREx_EnableUSBReg() function, the VDD33USB
          is then provided from the USB regulator.
      (+) When the USB regulator is enabled, the VDD33USB supply level detector shall
          be enabled through  HAL_PWREx_EnableUSBVoltageDetector() function.
      (+) The USB regulator is disabled through HAL_PWREx_DisableUSBReg() function and VDD33USB
          can be provided from an external supply. In this case VDD33USB and VDD50USB shall
          be connected together

    *** VBAT battery charging ***
    =============================
    [..]
      (+) When VDD is present, the external battery connected to VBAT can be charged through an
          internal resistance. VBAT charging can be performed either through a 5 KOhm resistor
          or through a 1.5 KOhm resistor.
      (+) VBAT charging is enabled by HAL_PWREx_EnableBatteryCharging(ResistorValue) function
          with:
       (++) ResistorValue:
        (+++) PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor.
        (+++) PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor.
      (+) VBAT charging is disabled by HAL_PWREx_DisableBatteryCharging() function.

Function Documentation

void HAL_PWREx_DisableBatteryCharging ( void )

Disable the Battery charging.

Return values:
None

Definition at line 1025 of file stm32h7xx_hal_pwr_ex.c.

HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg ( void )

Disable the Backup Regulator.

Return values:
HAL status

Definition at line 907 of file stm32h7xx_hal_pwr_ex.c.

References __HAL_PWR_GET_FLAG, HAL_GetTick(), PWR_FLAG_BRR, and PWR_FLAG_SETTING_DELAY_US.

HAL_StatusTypeDef HAL_PWREx_DisableUSBReg ( void )

Disable the USB Regulator.

Return values:
HAL status

Definition at line 958 of file stm32h7xx_hal_pwr_ex.c.

References HAL_GetTick(), and PWR_FLAG_SETTING_DELAY_US.

void HAL_PWREx_DisableUSBVoltageDetector ( void )

Disable the USB voltage level detector.

Return values:
None

Definition at line 993 of file stm32h7xx_hal_pwr_ex.c.

void HAL_PWREx_EnableBatteryCharging ( uint32_t ResistorValue )

Enable the Battery charging.

When VDD is present, charge the external battery through an internal resistor.

Parameters:
ResistorValue,: Specifies the charging resistor. This parameter can be one of the following values:
  • PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor.
  • PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor.
Return values:
None

Definition at line 1009 of file stm32h7xx_hal_pwr_ex.c.

References assert_param, and IS_PWR_BATTERY_RESISTOR_SELECT.

HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg ( void )

Enable the Backup Regulator.

Return values:
HAL status

Definition at line 882 of file stm32h7xx_hal_pwr_ex.c.

References __HAL_PWR_GET_FLAG, HAL_GetTick(), PWR_FLAG_BRR, and PWR_FLAG_SETTING_DELAY_US.

HAL_StatusTypeDef HAL_PWREx_EnableUSBReg ( void )

Enable the USB Regulator.

Return values:
HAL status

Definition at line 932 of file stm32h7xx_hal_pwr_ex.c.

References HAL_GetTick(), and PWR_FLAG_SETTING_DELAY_US.

void HAL_PWREx_EnableUSBVoltageDetector ( void )

Enable the USB voltage level detector.

Return values:
None

Definition at line 983 of file stm32h7xx_hal_pwr_ex.c.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Power Monitoring functions

Functions
Power Monitoring functions
PWREx Exported Functions

Power Monitoring functions. More...

Functions

void | HAL_PWREx_EnableMonitoring (void)
Enable the VBAT and temperature monitoring.
void | HAL_PWREx_DisableMonitoring (void)
Disable the VBAT and temperature monitoring.
uint32_t | HAL_PWREx_GetTemperatureLevel (void)
Indicate whether the junction temperature is between, above or below the threshold.
uint32_t | HAL_PWREx_GetVBATLevel (void)
Indicate whether the Battery voltage level is between, above or below the threshold.
void | HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD)
Configure the analog voltage threshold detected by the Analog Voltage Detector(AVD).
void | HAL_PWREx_EnableAVD (void)
Enable the Analog Voltage Detector(AVD).
void | HAL_PWREx_DisableAVD (void)
Disable the Analog Voltage Detector(AVD).
void | HAL_PWREx_PVD_AVD_IRQHandler (void)
This function handles the PWR PVD/AVD interrupt request.
__weak void | HAL_PWREx_AVDCallback (void)
PWR AVD interrupt callback.

Detailed Description

Power Monitoring functions.

 ===============================================================================
                 ##### Power Monitoring functions #####
 ===============================================================================

    *** VBAT and Temperature supervision ***
    ========================================
    [..]
      (+) The VBAT battery voltage supply can be monitored by comparing it with two threshold
          levels: VBAThigh and VBATlow. VBATH flag and VBATL flags in the PWR control register 2
          (PWR_CR2), indicate if VBAT is higher or lower than the threshold.
      (+) The temperature can be monitored by comparing it with two threshold levels, TEMPhigh
          and TEMPlow. TEMPH and TEMPL flags, in the PWR control register 2 (PWR_CR2),
          indicate whether the device temperature is higher or lower than the threshold.
      (+) The VBAT and the temperature monitoring is enabled by HAL_PWREx_EnableMonitoring()
          function and disabled by HAL_PWREx_DisableMonitoring() function.
      (+) The HAL_PWREx_GetVBATLevel() function return the VBAT level which can be:
          PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or
          PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD.
      (+) The HAL_PWREx_GetTemperatureLevel() function return the Temperature level which
          can be: PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or
          PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD.

    *** AVD configuration ***
    =========================
    [..]
      (+) The AVD is used to monitor the VDDA power supply by comparing it to a
          threshold selected by the AVD Level (ALS[3:0] bits in the PWR_CR1 register).
      (+) A AVDO flag is available to indicate if VDDA is higher or lower
          than the AVD threshold. This event is internally connected to the EXTI
          line 16 to generate an interrupt if enabled.
          It is configurable through __HAL_PWR_AVD_EXTI_ENABLE_IT() macro.
      (+) The AVD is stopped in System Standby mode.

Function Documentation

void HAL_PWREx_AVDCallback ( void )

PWR AVD interrupt callback.

Return values:
None

Definition at line 1262 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_PVD_AVD_IRQHandler().

void HAL_PWREx_ConfigAVD ( PWREx_AVDTypeDef * sConfigAVD )

Configure the analog voltage threshold detected by the Analog Voltage Detector(AVD).

Parameters:
sConfigAVD,: pointer to an PWR_AVDTypeDef structure that contains the configuration information for the AVD.
Note:
Refer to the electrical characteristics of your device datasheet for more details about the voltage threshold corresponding to each detection level.
Return values:
None

Definition at line 1163 of file stm32h7xx_hal_pwr_ex.c.

References __HAL_PWR_AVD_EXTI_DISABLE_EVENT, __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_AVD_EXTI_DISABLE_IT, __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_AVD_EXTI_ENABLE_EVENT, __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_AVD_EXTI_ENABLE_IT, __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE, assert_param, AVD_FALLING_EDGE, AVD_MODE_EVT, AVD_MODE_IT, AVD_RISING_EDGE, PWREx_AVDTypeDef::AVDLevel, IS_PWR_AVD_LEVEL, IS_PWR_AVD_MODE, and PWREx_AVDTypeDef::Mode.

void HAL_PWREx_DisableAVD ( void )

Disable the Analog Voltage Detector(AVD).

Return values:
None

Definition at line 1216 of file stm32h7xx_hal_pwr_ex.c.

void HAL_PWREx_DisableMonitoring ( void )

Disable the VBAT and temperature monitoring.

Return values:
HAL status

Definition at line 1091 of file stm32h7xx_hal_pwr_ex.c.

void HAL_PWREx_EnableAVD ( void )

Enable the Analog Voltage Detector(AVD).

Return values:
None

Definition at line 1206 of file stm32h7xx_hal_pwr_ex.c.

void HAL_PWREx_EnableMonitoring ( void )

Enable the VBAT and temperature monitoring.

Return values:
HAL status

Definition at line 1081 of file stm32h7xx_hal_pwr_ex.c.

uint32_t HAL_PWREx_GetTemperatureLevel ( void )

Indicate whether the junction temperature is between, above or below the threshold.

Return values:
Temperature level.

Definition at line 1101 of file stm32h7xx_hal_pwr_ex.c.

References PWR_TEMP_ABOVE_HIGH_THRESHOLD, PWR_TEMP_BELOW_LOW_THRESHOLD, and PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD.

uint32_t HAL_PWREx_GetVBATLevel ( void )

Indicate whether the Battery voltage level is between, above or below the threshold.

Return values:
VBAT level.

Definition at line 1130 of file stm32h7xx_hal_pwr_ex.c.

References PWR_VBAT_ABOVE_HIGH_THRESHOLD, PWR_VBAT_BELOW_LOW_THRESHOLD, and PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD.

void HAL_PWREx_PVD_AVD_IRQHandler ( void )

This function handles the PWR PVD/AVD interrupt request.

Note:
This API should be called under the PVD_AVD_IRQHandler().
Return values:
None

Definition at line 1227 of file stm32h7xx_hal_pwr_ex.c.

References __HAL_PWR_AVD_EXTI_CLEAR_FLAG, __HAL_PWR_AVD_EXTI_GET_FLAG, __HAL_PWR_PVD_EXTI_CLEAR_FLAG, __HAL_PWR_PVD_EXTI_GET_FLAG, HAL_PWR_PVDCallback(), and HAL_PWREx_AVDCallback().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PWREx_AVDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PWREx_AVDTypeDef Struct Reference
PWREx Exported Types

PWREx AVD configuration structure definition. More...

#include <stm32h7xx_hal_pwr_ex.h>

Data Fields

uint32_t | AVDLevel
uint32_t | Mode

Detailed Description

PWREx AVD configuration structure definition.

Definition at line 64 of file stm32h7xx_hal_pwr_ex.h.

Field Documentation

uint32_t PWREx_AVDTypeDef::AVDLevel

AVDLevel: Specifies the AVD detection level. This parameter can be a value of PWREx AVD detection level

Definition at line 66 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

uint32_t PWREx_AVDTypeDef::Mode

Mode: Specifies the operating mode for the selected pins. This parameter can be a value of PWREx AVD Mode

Definition at line 69 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_pwr_ex.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PWREx_WakeupPinTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PWREx_WakeupPinTypeDef Struct Reference
PWREx Exported Types

PWREx Wakeup pin configuration structure definition. More...

#include <stm32h7xx_hal_pwr_ex.h>

Data Fields

uint32_t | WakeUpPin
uint32_t | PinPolarity
uint32_t | PinPull

Detailed Description

PWREx Wakeup pin configuration structure definition.

Definition at line 76 of file stm32h7xx_hal_pwr_ex.h.

Field Documentation

uint32_t PWREx_WakeupPinTypeDef::PinPolarity

PinPolarity: Specifies the Wake-Up pin polarity. This parameter can be a value of PWREx Pin Polarity configuration

Definition at line 81 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnableWakeUpPin().

uint32_t PWREx_WakeupPinTypeDef::PinPull

PinPull: Specifies the Wake-Up pin pull. This parameter can be a value of PWREx Pin Pull configuration

Definition at line 84 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnableWakeUpPin().

uint32_t PWREx_WakeupPinTypeDef::WakeUpPin

WakeUpPin: Specifies the Wake-Up pin to be enabled. This parameter can be a value of PWREx Wake-Up Pins

Definition at line 78 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnableWakeUpPin().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_pwr_ex.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PWREx Wake-Up Pins

Defines
PWREx Wake-Up Pins
PWREx Exported Constants

Defines

#define | PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN_6
#define | PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN_5
#define | PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN_4
#define | PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN_3
#define | PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN_2
#define | PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN_1
#define | PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN_6
#define | PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN_5
#define | PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN_4
#define | PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN_3
#define | PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN_2
#define | PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN_1
#define | PWR_WAKEUP_PIN6_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_6 | PWR_WKUPEPR_WKUPEN_6)
#define | PWR_WAKEUP_PIN5_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_5 | PWR_WKUPEPR_WKUPEN_5)
#define | PWR_WAKEUP_PIN4_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_4 | PWR_WKUPEPR_WKUPEN_4)
#define | PWR_WAKEUP_PIN3_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_3 | PWR_WKUPEPR_WKUPEN_3)
#define | PWR_WAKEUP_PIN2_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_2 | PWR_WKUPEPR_WKUPEN_2)
#define | PWR_WAKEUP_PIN1_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_1 | PWR_WKUPEPR_WKUPEN_1)
#define | PWR_EXTI_WAKEUP_PINS_MASK

Define Documentation

#define PWR_EXTI_WAKEUP_PINS_MASK
Value:
(uint32_t)(EXTI_IMR2_IM55 | EXTI_IMR2_IM56 | \
                                              EXTI_IMR2_IM57 | EXTI_IMR2_IM58 | \
                                              EXTI_IMR2_IM59 | EXTI_IMR2_IM60)

Definition at line 121 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnableWakeUpPin().

#define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN_1

Definition at line 104 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN_1

Definition at line 111 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN1_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_1 | PWR_WKUPEPR_WKUPEN_1)

Definition at line 118 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN_2

Definition at line 103 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN_2

Definition at line 110 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN2_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_2 | PWR_WKUPEPR_WKUPEN_2)

Definition at line 117 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN_3

Definition at line 102 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN_3

Definition at line 109 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN3_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_3 | PWR_WKUPEPR_WKUPEN_3)

Definition at line 116 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN_4

Definition at line 101 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN_4

Definition at line 108 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN4_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_4 | PWR_WKUPEPR_WKUPEN_4)

Definition at line 115 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN_5

Definition at line 100 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN_5

Definition at line 107 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN5_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_5 | PWR_WKUPEPR_WKUPEN_5)

Definition at line 114 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN_6

Definition at line 99 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN_6

Definition at line 106 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN6_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_6 | PWR_WKUPEPR_WKUPEN_6)

Definition at line 113 of file stm32h7xx_hal_pwr_ex.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PWREx Pin Polarity configuration

Defines
PWREx Pin Polarity configuration
PWREx Exported Constants

Defines

#define | PWR_PIN_POLARITY_HIGH ((uint32_t)0x00000000U)
#define | PWR_PIN_POLARITY_LOW ((uint32_t)0x00000001U)

Define Documentation

#define PWR_PIN_POLARITY_HIGH ((uint32_t)0x00000000U)

Definition at line 131 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_PIN_POLARITY_LOW ((uint32_t)0x00000001U)

Definition at line 132 of file stm32h7xx_hal_pwr_ex.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PWREx Pin Pull configuration

Defines
PWREx Pin Pull configuration
PWREx Exported Constants

Defines

#define | PWR_PIN_NO_PULL ((uint32_t)0x00000000U)
#define | PWR_PIN_PULL_UP ((uint32_t)0x00000001U)
#define | PWR_PIN_PULL_DOWN ((uint32_t)0x00000002U)

Define Documentation

#define PWR_PIN_NO_PULL ((uint32_t)0x00000000U)

Definition at line 140 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_PIN_PULL_DOWN ((uint32_t)0x00000002U)

Definition at line 142 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_PIN_PULL_UP ((uint32_t)0x00000001U)

Definition at line 141 of file stm32h7xx_hal_pwr_ex.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PWREx Wakeup Pins Flags.

Defines
PWREx Wakeup Pins Flags.
PWREx Exported Constants

Defines

#define | PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1
#define | PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2
#define | PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3
#define | PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4
#define | PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5
#define | PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6

Define Documentation

#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1

Wakeup event on pin 1

Definition at line 151 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2

Wakeup event on pin 2

Definition at line 152 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3

Wakeup event on pin 3

Definition at line 153 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4

Wakeup event on pin 4

Definition at line 154 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5

Wakeup event on pin 5

Definition at line 155 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6

Wakeup event on pin 6

Definition at line 156 of file stm32h7xx_hal_pwr_ex.h.

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STM32H753xx HAL User Manual: PWREx Domains definition

Defines
PWREx Domains definition
PWREx Exported Constants

Defines

#define | PWR_D1_DOMAIN ((uint32_t)0x00000000U)
#define | PWR_D2_DOMAIN ((uint32_t)0x00000001U)
#define | PWR_D3_DOMAIN ((uint32_t)0x00000002U)

Define Documentation

#define PWR_D1_DOMAIN ((uint32_t)0x00000000U)

Definition at line 165 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnterSTANDBYMode(), and HAL_PWREx_EnterSTOPMode().

#define PWR_D2_DOMAIN ((uint32_t)0x00000001U)

Definition at line 166 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnterSTANDBYMode(), and HAL_PWREx_EnterSTOPMode().

#define PWR_D3_DOMAIN ((uint32_t)0x00000002U)

Definition at line 167 of file stm32h7xx_hal_pwr_ex.h.

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STM32H753xx HAL User Manual: PWREx Domain Flags definition

Defines
PWREx Domain Flags definition
PWREx Exported Constants

Defines

#define PWR_CPU_FLAGS ((uint32_t)0x00000000U)

Define Documentation

#define PWR_CPU_FLAGS ((uint32_t)0x00000000U)

Definition at line 175 of file stm32h7xx_hal_pwr_ex.h.

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STM32H753xx HAL User Manual: PWREx D3 Domain State

Defines
PWREx D3 Domain State
PWREx Exported Constants

Defines

#define | PWR_D3_DOMAIN_STOP ((uint32_t)0x00000000U)
#define | PWR_D3_DOMAIN_RUN ((uint32_t)0x00000800U)

Define Documentation

#define PWR_D3_DOMAIN_RUN ((uint32_t)0x00000800U)

Definition at line 184 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_D3_DOMAIN_STOP ((uint32_t)0x00000000U)

Definition at line 183 of file stm32h7xx_hal_pwr_ex.h.

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STM32H753xx HAL User Manual: PWREx Supply configuration

Defines
PWREx Supply configuration
PWREx Exported Constants

Defines

#define | PWR_LDO_SUPPLY PWR_CR3_LDOEN /* Core domains are suppplied from the LDO */
#define | PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /* The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source */
#define | PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)

Define Documentation

#define PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /* The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source */

Definition at line 195 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_LDO_SUPPLY PWR_CR3_LDOEN /* Core domains are suppplied from the LDO */

Definition at line 193 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)

Definition at line 197 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigSupply(), and HAL_PWREx_GetSupplyConfig().

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STM32H753xx HAL User Manual: PWREx AVD detection level

Defines
PWREx AVD detection level
PWREx Exported Constants

Defines

#define | PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0
#define | PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1
#define | PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2
#define | PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3

Define Documentation

#define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0

Definition at line 206 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1

Definition at line 207 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2

Definition at line 208 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3

Definition at line 209 of file stm32h7xx_hal_pwr_ex.h.

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STM32H753xx HAL User Manual: PWREx AVD Mode

Defines
PWREx AVD Mode
PWREx Exported Constants

Defines

#define | PWR_AVD_MODE_NORMAL ((uint32_t)0x00000000U)
#define | PWR_AVD_MODE_IT_RISING ((uint32_t)0x00010001U)
#define | PWR_AVD_MODE_IT_FALLING ((uint32_t)0x00010002U)
#define | PWR_AVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U)
#define | PWR_AVD_MODE_EVENT_RISING ((uint32_t)0x00020001U)
#define | PWR_AVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U)
#define | PWR_AVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U)

Define Documentation

#define PWR_AVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U)

Event Mode with Falling edge trigger detection

Definition at line 222 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_AVD_MODE_EVENT_RISING ((uint32_t)0x00020001U)

Event Mode with Rising edge trigger detection

Definition at line 221 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_AVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U)

Event Mode with Rising/Falling edge trigger detection

Definition at line 223 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_AVD_MODE_IT_FALLING ((uint32_t)0x00010002U)

External Interrupt Mode with Falling edge trigger detection

Definition at line 219 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_AVD_MODE_IT_RISING ((uint32_t)0x00010001U)

External Interrupt Mode with Rising edge trigger detection

Definition at line 218 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_AVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 220 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_AVD_MODE_NORMAL ((uint32_t)0x00000000U)

Basic mode is used

Definition at line 217 of file stm32h7xx_hal_pwr_ex.h.

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STM32H753xx HAL User Manual: PWREx Regulator Voltage Scale

Defines
PWREx Regulator Voltage Scale
PWREx Exported Constants

Defines

#define | PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0)
#define | PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1)
#define | PWR_REGULATOR_SVOS_SCALE3 (uint32_t)(PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)

Define Documentation

#define PWR_REGULATOR_SVOS_SCALE3 (uint32_t)(PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)

Definition at line 233 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1)

Definition at line 232 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0)

Definition at line 231 of file stm32h7xx_hal_pwr_ex.h.

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STM32H753xx HAL User Manual: PWR battery charging resistor selection

Defines
PWR battery charging resistor selection
PWREx Exported Constants

Defines

#define | PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000U)
#define | PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS

Define Documentation

#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS

VBAT charging through a 1.5 kOhms resistor

Definition at line 242 of file stm32h7xx_hal_pwr_ex.h.

#define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000U)

VBAT charging through a 5 kOhms resistor

Definition at line 241 of file stm32h7xx_hal_pwr_ex.h.

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STM32H753xx HAL User Manual: PWREx VBAT Thresholds

Defines
PWREx VBAT Thresholds
PWREx Exported Constants

Defines

#define | PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U)
#define | PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL
#define | PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH

Define Documentation

#define PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH

Definition at line 252 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_GetVBATLevel().

#define PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL

Definition at line 251 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_GetVBATLevel().

#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U)

Definition at line 250 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_GetVBATLevel().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PWREx Temperature Thresholds

Defines
PWREx Temperature Thresholds
PWREx Exported Constants

Defines

#define | PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U)
#define | PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL
#define | PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH

Define Documentation

#define PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH

Definition at line 262 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_GetTemperatureLevel().

#define PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL

Definition at line 261 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_GetTemperatureLevel().

#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U)

Definition at line 260 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_GetTemperatureLevel().

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STM32H753xx HAL User Manual: PWREx AVD EXTI Line 16

Defines
PWREx AVD EXTI Line 16
PWREx Exported Constants

Defines

#define PWR_EXTI_LINE_AVD ((uint32_t)EXTI_IMR1_IM16)

Define Documentation

#define PWR_EXTI_LINE_AVD ((uint32_t)EXTI_IMR1_IM16)

External interrupt line 16 Connected to the AVD EXTI Line

Definition at line 269 of file stm32h7xx_hal_pwr_ex.h.

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STM32H753xx HAL User Manual: PWREx Exported Macro

Defines
PWREx Exported Macro
PWREx

Defines

#define | __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_AVD)
Enable the AVD EXTI Line 16.
#define | __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_AVD)
Disable the AVD EXTI Line 16.
#define | __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_AVD)
Enable event on AVD EXTI Line 16.
#define | __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_AVD)
Disable event on AVD EXTI Line 16.
#define | __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
Enable the AVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
Disable the AVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
Enable the AVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
Disable the AVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE()
AVD EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the AVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_AVD_EXTI_GET_FLAG() READ_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_AVD)
Check whether the specified AVD EXTI interrupt flag is set or not.
#define | __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_AVD)
Clear the AVD EXTI flag.

Define Documentation

#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG ( ) SET_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_AVD)

Clear the AVD EXTI flag.

Return values:
None.

Definition at line 365 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_AVD_IRQHandler().

#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_AVD)

Disable event on AVD EXTI Line 16.

Return values:
None.

Definition at line 306 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)

Disable the AVD Extended Interrupt Falling Trigger.

Return values:
None.

Definition at line 332 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

#define __HAL_PWR_AVD_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_AVD)

Disable the AVD EXTI Line 16.

Return values:
None.

Definition at line 292 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)

Disable the AVD Extended Interrupt Rising Trigger.

Return values:
None.

Definition at line 319 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
  __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \
  __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \
} while(0);

Disable the AVD Extended Interrupt Rising & Falling Trigger.

Return values:
None.

Definition at line 348 of file stm32h7xx_hal_pwr_ex.h.

#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_AVD)

Enable event on AVD EXTI Line 16.

Return values:
None.

Definition at line 299 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)

Enable the AVD Extended Interrupt Falling Trigger.

Return values:
None.

Definition at line 325 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

#define __HAL_PWR_AVD_EXTI_ENABLE_IT ( ) SET_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_AVD)

Enable the AVD EXTI Line 16.

Return values:
None.

Definition at line 285 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)

Enable the AVD Extended Interrupt Rising Trigger.

Return values:
None.

Definition at line 313 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
  __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \
  __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \
} while(0);

AVD EXTI line configuration: set rising & falling edge trigger.

Return values:
None.

Definition at line 339 of file stm32h7xx_hal_pwr_ex.h.

#define __HAL_PWR_AVD_EXTI_GET_FLAG ( ) READ_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_AVD)

Check whether the specified AVD EXTI interrupt flag is set or not.

Return values:
EXTI AVD Line Status.

Definition at line 358 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_AVD_IRQHandler().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PWREx Private macros to check input parameters

Defines
PWREx Private macros to check input parameters
PWREx Private Macros

Defines

#define | IS_PWR_SUPPLY(PWR_SOURCE)
#define | IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE)
#define | IS_PWR_DOMAIN(DOMAIN)
#define | IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) || ((STATE) == PWR_D3_DOMAIN_RUN))
#define | IS_PWR_WAKEUP_PIN(PIN)
#define | IS_PWR_WAKEUP_PIN_POLARITY(POLARITY)
#define | IS_PWR_WAKEUP_PIN_PULL(PULL)
#define | IS_PWR_WAKEUP_FLAG(FLAG)
#define | IS_PWR_AVD_LEVEL(LEVEL)
#define | IS_PWR_AVD_MODE(MODE)
#define | IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR)

Define Documentation

#define IS_D3_STATE ( STATE ) (((STATE) == PWR_D3_DOMAIN_STOP) || ((STATE) == PWR_D3_DOMAIN_RUN))

Definition at line 486 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigD3Domain().

#define IS_PWR_AVD_LEVEL ( LEVEL )
Value:
(((LEVEL) == PWR_AVDLEVEL_0) || ((LEVEL) == PWR_AVDLEVEL_1) || \
                                  ((LEVEL) == PWR_AVDLEVEL_2) || ((LEVEL) == PWR_AVDLEVEL_3))

Definition at line 521 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

#define IS_PWR_AVD_MODE ( MODE )
Value:
(((MODE) == PWR_AVD_MODE_IT_RISING)|| ((MODE) == PWR_AVD_MODE_IT_FALLING) || \
                                ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_AVD_MODE_EVENT_RISING) || \
                                ((MODE) == PWR_AVD_MODE_EVENT_FALLING) || ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING) || \
                                ((MODE) == PWR_AVD_MODE_NORMAL))

Definition at line 524 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigAVD().

#define IS_PWR_BATTERY_RESISTOR_SELECT ( RESISTOR )
Value:
(((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
                                                   ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))

Definition at line 529 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnableBatteryCharging().

#define IS_PWR_DOMAIN ( DOMAIN )
Value:
(((DOMAIN) == PWR_D1_DOMAIN) || \
                                ((DOMAIN) == PWR_D2_DOMAIN) || \
                                ((DOMAIN) == PWR_D3_DOMAIN))

Definition at line 482 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnterSTANDBYMode(), and HAL_PWREx_EnterSTOPMode().

#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE ( VOLTAGE )
Value:
(((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3)  || \
                                                      ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4)  || \
                                                      ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5))

Definition at line 478 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ControlStopModeVoltageScaling().

#define IS_PWR_SUPPLY ( PWR_SOURCE )
Value:
(((PWR_SOURCE) == PWR_LDO_SUPPLY) || \
                                    ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))

Definition at line 475 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigSupply().

#define IS_PWR_WAKEUP_FLAG ( FLAG )
Value:
(((FLAG) == PWR_WAKEUP_FLAG1)  || \
                                   ((FLAG) == PWR_WAKEUP_FLAG2)  || \
                                   ((FLAG) == PWR_WAKEUP_FLAG3)  || \
                                   ((FLAG) == PWR_WAKEUP_FLAG4)  || \
                                   ((FLAG) == PWR_WAKEUP_FLAG5)  || \
                                   ((FLAG) == PWR_WAKEUP_FLAG6))

Definition at line 514 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ClearWakeupFlag(), and HAL_PWREx_GetWakeupFlag().

#define IS_PWR_WAKEUP_PIN ( PIN )
Value:
(((PIN) == PWR_WAKEUP_PIN1)       || \
                                 ((PIN) == PWR_WAKEUP_PIN2)       || \
                                 ((PIN) == PWR_WAKEUP_PIN3)       || \
                                 ((PIN) == PWR_WAKEUP_PIN4)       || \
                                 ((PIN) == PWR_WAKEUP_PIN5)       || \
                                 ((PIN) == PWR_WAKEUP_PIN6)       || \
                                 ((PIN) == PWR_WAKEUP_PIN1_HIGH)  || \
                                 ((PIN) == PWR_WAKEUP_PIN2_HIGH)  || \
                                 ((PIN) == PWR_WAKEUP_PIN3_HIGH)  || \
                                 ((PIN) == PWR_WAKEUP_PIN4_HIGH)  || \
                                 ((PIN) == PWR_WAKEUP_PIN5_HIGH)  || \
                                 ((PIN) == PWR_WAKEUP_PIN6_HIGH)  || \
                                 ((PIN) == PWR_WAKEUP_PIN1_LOW)   || \
                                 ((PIN) == PWR_WAKEUP_PIN2_LOW)   || \
                                 ((PIN) == PWR_WAKEUP_PIN3_LOW)   || \
                                 ((PIN) == PWR_WAKEUP_PIN4_LOW)   || \
                                 ((PIN) == PWR_WAKEUP_PIN5_LOW)    || \
                                 ((PIN) == PWR_WAKEUP_PIN6_LOW))

Definition at line 488 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWR_DisableWakeUpPin(), HAL_PWR_EnableWakeUpPin(), HAL_PWREx_DisableWakeUpPin(), and HAL_PWREx_EnableWakeUpPin().

#define IS_PWR_WAKEUP_PIN_POLARITY ( POLARITY )
Value:
(((POLARITY) == PWR_PIN_POLARITY_HIGH) || \
                                               ((POLARITY) == PWR_PIN_POLARITY_LOW))

Definition at line 507 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnableWakeUpPin().

#define IS_PWR_WAKEUP_PIN_PULL ( PULL )
Value:
(((PULL) == PWR_PIN_NO_PULL)  || \
                                       ((PULL) == PWR_PIN_PULL_UP)  || \
                                       ((PULL) == PWR_PIN_PULL_DOWN))

Definition at line 510 of file stm32h7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnableWakeUpPin().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PWR Extended AVD Mode Mask

Defines
PWR Extended AVD Mode Mask
PWREx_Private_Constants

Defines

#define | AVD_MODE_IT ((uint32_t)0x00010000U)
#define | AVD_MODE_EVT ((uint32_t)0x00020000U)
#define | AVD_RISING_EDGE ((uint32_t)0x00000001U)
#define | AVD_FALLING_EDGE ((uint32_t)0x00000002U)
#define | AVD_RISING_FALLING_EDGE ((uint32_t)0x00000003U)

Define Documentation

#define AVD_FALLING_EDGE ((uint32_t)0x00000002U)

Definition at line 68 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigAVD().

#define AVD_MODE_EVT ((uint32_t)0x00020000U)

Definition at line 66 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigAVD().

#define AVD_MODE_IT ((uint32_t)0x00010000U)

Definition at line 65 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigAVD().

#define AVD_RISING_EDGE ((uint32_t)0x00000001U)

Definition at line 67 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigAVD().

#define AVD_RISING_FALLING_EDGE ((uint32_t)0x00000003U)

Definition at line 69 of file stm32h7xx_hal_pwr_ex.c.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PWR Extended Flag Setting Time Out Value

Defines
PWR Extended Flag Setting Time Out Value
PWREx_Private_Constants

Defines

#define PWR_FLAG_SETTING_DELAY_US ((uint32_t)1000U)

Define Documentation

#define PWR_FLAG_SETTING_DELAY_US ((uint32_t)1000U)

Definition at line 77 of file stm32h7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigSupply(), HAL_PWREx_ControlVoltageScaling(), HAL_PWREx_DisableBkUpReg(), HAL_PWREx_DisableUSBReg(), HAL_PWREx_EnableBkUpReg(), and HAL_PWREx_EnableUSBReg().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: QSPI Private Constants

Defines
QSPI Private Constants
QSPI

Defines

#define | QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000)
#define | QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0)
#define | QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1)
#define | QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE)

Define Documentation

#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1)

Automatic polling mode

Definition at line 189 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0)

Indirect read mode

Definition at line 188 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), and HAL_QSPI_Receive_IT().

#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000)

Indirect write mode

Definition at line 187 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE)

Memory-mapped mode

Definition at line 190 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_MemoryMapped(), and QSPI_Config().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: QSPI Private Macros

Defines
QSPI Private Macros
QSPI

Defines

#define | IS_QSPI_FUNCTIONAL_MODE(MODE)
#define | IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
#define | IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 32))
#define | IS_QSPI_SSHIFT(SSHIFT)
#define | IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))
#define | IS_QSPI_CS_HIGH_TIME(CSHTIME)
#define | IS_QSPI_CLOCK_MODE(CLKMODE)
#define | IS_QSPI_FLASH_ID(FLASH)
#define | IS_QSPI_DUAL_FLASH_MODE(MODE)
#define | IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
#define | IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)
#define | IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE)
#define | IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31)
#define | IS_QSPI_INSTRUCTION_MODE(MODE)
#define | IS_QSPI_ADDRESS_MODE(MODE)
#define | IS_QSPI_ALTERNATE_BYTES_MODE(MODE)
#define | IS_QSPI_DATA_MODE(MODE)
#define | IS_QSPI_DDR_MODE(DDR_MODE)
#define | IS_QSPI_DDR_HHC(DDR_HHC)
#define | IS_QSPI_SIOO_MODE(SIOO_MODE)
#define | IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
#define | IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))
#define | IS_QSPI_MATCH_MODE(MODE)
#define | IS_QSPI_AUTOMATIC_STOP(APMS)
#define | IS_QSPI_TIMEOUT_ACTIVATION(TCEN)
#define | IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)

Define Documentation

#define IS_QSPI_ADDRESS_MODE ( MODE )
Value:
(((MODE) == QSPI_ADDRESS_NONE)    || \
                                            ((MODE) == QSPI_ADDRESS_1_LINE)  || \
                                            ((MODE) == QSPI_ADDRESS_2_LINES) || \
                                            ((MODE) == QSPI_ADDRESS_4_LINES))

Definition at line 637 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_ADDRESS_SIZE ( ADDR_SIZE )
Value:
(((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \
                                            ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
                                            ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
                                            ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))

Definition at line 620 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_ALTERNATE_BYTES_MODE ( MODE )
Value:
(((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \
                                            ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \
                                            ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
                                            ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))

Definition at line 642 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_ALTERNATE_BYTES_SIZE ( SIZE )
Value:
(((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \
                                            ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
                                            ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
                                            ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))

Definition at line 625 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_AUTOMATIC_STOP ( APMS )
Value:
(((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
                                            ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))

Definition at line 668 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling_IT().

#define IS_QSPI_CLOCK_MODE ( CLKMODE )
Value:
(((CLKMODE) == QSPI_CLOCK_MODE_0) || \
                                            ((CLKMODE) == QSPI_CLOCK_MODE_3))

Definition at line 608 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_CLOCK_PRESCALER ( PRESCALER ) ((PRESCALER) <= 0xFF)

Definition at line 590 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_CS_HIGH_TIME ( CSHTIME )
Value:
(((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))

Definition at line 599 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_DATA_MODE ( MODE )
Value:
(((MODE) == QSPI_DATA_NONE)    || \
                                            ((MODE) == QSPI_DATA_1_LINE)  || \
                                            ((MODE) == QSPI_DATA_2_LINES) || \
                                            ((MODE) == QSPI_DATA_4_LINES))

Definition at line 647 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_DDR_HHC ( DDR_HHC )
Value:
(((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
                                            ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))

Definition at line 655 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_DDR_MODE ( DDR_MODE )
Value:
(((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
                                            ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))

Definition at line 652 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_DUAL_FLASH_MODE ( MODE )
Value:
(((MODE) == QSPI_DUALFLASH_ENABLE) || \
                                            ((MODE) == QSPI_DUALFLASH_DISABLE))

Definition at line 615 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_DUMMY_CYCLES ( DCY ) ((DCY) <= 31)

Definition at line 630 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_FIFO_THRESHOLD ( THR ) (((THR) > 0) && ((THR) <= 32))

Definition at line 592 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_FLASH_ID ( FLASH )
Value:
(((FLASH) == QSPI_FLASH_ID_1) || \
                                            ((FLASH) == QSPI_FLASH_ID_2))

Definition at line 612 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_FLASH_SIZE ( FSIZE ) (((FSIZE) <= 31))

Definition at line 597 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_FUNCTIONAL_MODE ( MODE )
Value:
(((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
                                       ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \
                                       ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \
                                       ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))

Definition at line 199 of file stm32h7xx_hal_qspi.c.

Referenced by QSPI_Config().

#define IS_QSPI_INSTRUCTION ( INSTRUCTION ) ((INSTRUCTION) <= 0xFF)

Definition at line 618 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_INSTRUCTION_MODE ( MODE )
Value:
(((MODE) == QSPI_INSTRUCTION_NONE)    || \
                                            ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \
                                            ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
                                            ((MODE) == QSPI_INSTRUCTION_4_LINES))

Definition at line 632 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_INTERVAL ( INTERVAL ) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)

Definition at line 661 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

#define IS_QSPI_MATCH_MODE ( MODE )
Value:
(((MODE) == QSPI_MATCH_MODE_AND) || \
                                            ((MODE) == QSPI_MATCH_MODE_OR))

Definition at line 665 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

#define IS_QSPI_SIOO_MODE ( SIOO_MODE )
Value:
(((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
                                            ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))

Definition at line 658 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_SSHIFT ( SSHIFT )
Value:
(((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
                                            ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))

Definition at line 594 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_STATUS_BYTES_SIZE ( SIZE ) (((SIZE) >= 1) && ((SIZE) <= 4))

Definition at line 663 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

#define IS_QSPI_TIMEOUT_ACTIVATION ( TCEN )
Value:
(((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
                                            ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))

Definition at line 671 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_MemoryMapped().

#define IS_QSPI_TIMEOUT_PERIOD ( PERIOD ) ((PERIOD) <= 0xFFFF)

Definition at line 674 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_MemoryMapped().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
QSPI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI mode according to the specified parameters in the QSPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi)
De-Initialize the QSPI peripheral.
__weak void | HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI MSP.
__weak void | HAL_QSPI_MspDeInit (QSPI_HandleTypeDef *hqspi)
DeInitialize the QSPI MSP.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to :
      (+) Initialize the QuadSPI.
      (+) De-initialize the QuadSPI.

Function Documentation

HAL_StatusTypeDef HAL_QSPI_DeInit ( QSPI_HandleTypeDef * hqspi )

De-Initialize the QSPI peripheral.

Parameters:
hqspi,: QSPI handle
Return values:
HAL status

Definition at line 327 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_DISABLE, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_NONE, HAL_QSPI_MspDeInit(), HAL_QSPI_STATE_RESET, and QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_Init ( QSPI_HandleTypeDef * hqspi )

Initialize the QSPI mode according to the specified parameters in the QSPI_InitTypeDef and initialize the associated handle.

Parameters:
hqspi,: QSPI handle
Return values:
HAL status

Definition at line 245 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_ENABLE, assert_param, QSPI_InitTypeDef::ChipSelectHighTime, QSPI_InitTypeDef::ClockMode, QSPI_InitTypeDef::ClockPrescaler, QSPI_InitTypeDef::DualFlash, QSPI_HandleTypeDef::ErrorCode, QSPI_InitTypeDef::FifoThreshold, QSPI_InitTypeDef::FlashID, QSPI_InitTypeDef::FlashSize, HAL_GetTick(), HAL_QPSI_TIMEOUT_DEFAULT_VALUE, HAL_QSPI_ERROR_NONE, HAL_QSPI_MspInit(), HAL_QSPI_SetTimeout(), HAL_QSPI_STATE_READY, HAL_QSPI_STATE_RESET, QSPI_HandleTypeDef::Init, QSPI_HandleTypeDef::Instance, IS_QSPI_CLOCK_MODE, IS_QSPI_CLOCK_PRESCALER, IS_QSPI_CS_HIGH_TIME, IS_QSPI_DUAL_FLASH_MODE, IS_QSPI_FIFO_THRESHOLD, IS_QSPI_FLASH_ID, IS_QSPI_FLASH_SIZE, IS_QSPI_SSHIFT, QSPI_HandleTypeDef::Lock, QSPI_DUALFLASH_ENABLE, QSPI_FLAG_BUSY, QSPI_WaitFlagStateUntilTimeout(), QSPI_InitTypeDef::SampleShifting, QSPI_HandleTypeDef::State, and QSPI_HandleTypeDef::Timeout.

__weak void HAL_QSPI_MspDeInit ( QSPI_HandleTypeDef * hqspi )

DeInitialize the QSPI MSP.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 376 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_DeInit().

__weak void HAL_QSPI_MspInit ( QSPI_HandleTypeDef * hqspi )

Initialize the QSPI MSP.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 361 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_Init().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
QSPI Exported Functions

QSPI Transmit/Receive functions. More...

Functions

void | HAL_QSPI_IRQHandler (QSPI_HandleTypeDef *hqspi)
Handle QSPI interrupt request.
HAL_StatusTypeDef | HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
Set the command configuration.
HAL_StatusTypeDef | HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
Set the command configuration in interrupt mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
Configure the QSPI Automatic Polling Mode in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
Configure the QSPI Automatic Polling Mode in non-blocking mode.
HAL_StatusTypeDef | HAL_QSPI_MemoryMapped (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
Configure the Memory Mapped mode.
__weak void | HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi)
Transfer Error callback.
__weak void | HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi)
Abort completed callback.
__weak void | HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi)
Command completed callback.
__weak void | HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Transfer completed callback.
__weak void | HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Transfer completed callback.
__weak void | HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Half Transfer completed callback.
__weak void | HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Half Transfer completed callback.
__weak void | HAL_QSPI_FifoThresholdCallback (QSPI_HandleTypeDef *hqspi)
FIFO Threshold callback.
__weak void | HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi)
Status Match callback.
__weak void | HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi)
Timeout callback.

Detailed Description

QSPI Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to :
      (+) Handle the interrupts.
      (+) Handle the command sequence.
      (+) Transmit data in blocking, interrupt or DMA mode.
      (+) Receive data in blocking, interrupt or DMA mode.
      (+) Manage the auto-polling functional mode.
      (+) Manage the memory-mapped functional mode.

Function Documentation

__weak void HAL_QSPI_AbortCpltCallback ( QSPI_HandleTypeDef * hqspi )

Abort completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1605 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

HAL_StatusTypeDef HAL_QSPI_AutoPolling | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | QSPI_AutoPollingTypeDef * | cfg,
 |  | uint32_t | Timeout
 | ) |  |

Configure the QSPI Automatic Polling Mode in blocking mode.

Parameters:
hqspi,: QSPI handle
cmd,: structure that contains the command configuration information.
cfg,: structure that contains the polling configuration information.
Timeout : Timeout duration
Note:
This function is used only in Automatic Polling Mode
Return values:
HAL status

Definition at line 1300 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_AUTO_POLLING, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, QSPI_AutoPollingTypeDef::Interval, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_INTERVAL, IS_QSPI_MATCH_MODE, IS_QSPI_SIOO_MODE, IS_QSPI_STATUS_BYTES_SIZE, QSPI_AutoPollingTypeDef::Mask, QSPI_AutoPollingTypeDef::Match, QSPI_AutoPollingTypeDef::MatchMode, QSPI_CommandTypeDef::NbData, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_AUTOMATIC_STOP_ENABLE, QSPI_Config(), QSPI_FLAG_BUSY, QSPI_FLAG_SM, QSPI_FUNCTIONAL_MODE_AUTO_POLLING, QSPI_INSTRUCTION_NONE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, QSPI_HandleTypeDef::State, and QSPI_AutoPollingTypeDef::StatusBytesSize.

HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | QSPI_AutoPollingTypeDef * | cfg
 | ) |  |

Configure the QSPI Automatic Polling Mode in non-blocking mode.

Parameters:
hqspi,: QSPI handle
cmd,: structure that contains the command configuration information.
cfg,: structure that contains the polling configuration information.
Note:
This function is used only in Automatic Polling Mode
Return values:
HAL status

Definition at line 1400 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_AutoPollingTypeDef::AutomaticStop, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_AUTO_POLLING, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, QSPI_AutoPollingTypeDef::Interval, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_AUTOMATIC_STOP, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_INTERVAL, IS_QSPI_MATCH_MODE, IS_QSPI_SIOO_MODE, IS_QSPI_STATUS_BYTES_SIZE, QSPI_AutoPollingTypeDef::Mask, QSPI_AutoPollingTypeDef::Match, QSPI_AutoPollingTypeDef::MatchMode, QSPI_CommandTypeDef::NbData, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_FLAG_BUSY, QSPI_FLAG_SM, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_AUTO_POLLING, QSPI_INSTRUCTION_NONE, QSPI_IT_SM, QSPI_IT_TE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, QSPI_HandleTypeDef::State, QSPI_AutoPollingTypeDef::StatusBytesSize, and QSPI_HandleTypeDef::Timeout.

__weak void HAL_QSPI_CmdCpltCallback ( QSPI_HandleTypeDef * hqspi )

Command completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1620 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

HAL_StatusTypeDef HAL_QSPI_Command | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | uint32_t | Timeout
 | ) |  |

Set the command configuration.

Parameters:
hqspi,: QSPI handle
cmd | : structure that contains the command configuration information
Timeout | : Timeout duration
Note:
This function is used only in Indirect Read or Write Modes
Return values:
HAL status

Definition at line 634 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY, HAL_QSPI_STATE_READY, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_SIOO_MODE, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_DATA_NONE, QSPI_FLAG_BUSY, QSPI_FLAG_TC, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_INSTRUCTION_NONE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, and QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_Command_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd
 | ) |  |

Set the command configuration in interrupt mode.

Parameters:
hqspi,: QSPI handle
cmd : structure that contains the command configuration information
Note:
This function is used only in Indirect Read or Write Modes
Return values:
HAL status

Definition at line 724 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY, HAL_QSPI_STATE_READY, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_SIOO_MODE, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_DATA_NONE, QSPI_FLAG_BUSY, QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_INSTRUCTION_NONE, QSPI_IT_TC, QSPI_IT_TE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, QSPI_HandleTypeDef::State, and QSPI_HandleTypeDef::Timeout.

__weak void HAL_QSPI_ErrorCallback ( QSPI_HandleTypeDef * hqspi )

Transfer Error callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1590 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler(), and QSPI_DMAAbortCplt().

__weak void HAL_QSPI_FifoThresholdCallback ( QSPI_HandleTypeDef * hqspi )

FIFO Threshold callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1695 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

void HAL_QSPI_IRQHandler ( QSPI_HandleTypeDef * hqspi )

Handle QSPI interrupt request.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 415 of file stm32h7xx_hal_qspi.c.

References __HAL_MDMA_DISABLE, __HAL_QSPI_DISABLE_IT, __HAL_QSPI_GET_FLAG, QSPI_HandleTypeDef::ErrorCode, HAL_MDMA_Abort_IT(), HAL_QSPI_AbortCpltCallback(), HAL_QSPI_CmdCpltCallback(), HAL_QSPI_ERROR_NONE, HAL_QSPI_ERROR_TRANSFER, HAL_QSPI_ErrorCallback(), HAL_QSPI_FifoThresholdCallback(), HAL_QSPI_RxCpltCallback(), HAL_QSPI_STATE_ABORT, HAL_QSPI_STATE_BUSY, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, HAL_QSPI_StatusMatchCallback(), HAL_QSPI_TimeOutCallback(), HAL_QSPI_TxCpltCallback(), QSPI_HandleTypeDef::hmdma, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pRxBuffPtr, QSPI_HandleTypeDef::pTxBuffPtr, QSPI_DMAAbortCplt(), QSPI_FLAG_FT, QSPI_FLAG_SM, QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FLAG_TO, QSPI_IT_FT, QSPI_IT_SM, QSPI_IT_TC, QSPI_IT_TE, QSPI_IT_TO, QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::TxXferCount, and __MDMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_QSPI_MemoryMapped | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | QSPI_MemoryMappedTypeDef * | cfg
 | ) |  |

Configure the Memory Mapped mode.

Parameters:
hqspi,: QSPI handle
cmd,: structure that contains the command configuration information.
cfg,: structure that contains the memory mapped configuration information.
Note:
This function is used only in Memory mapped Mode
Return values:
HAL status

Definition at line 1504 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_MEM_MAPPED, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_SIOO_MODE, IS_QSPI_TIMEOUT_ACTIVATION, IS_QSPI_TIMEOUT_PERIOD, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_FLAG_BUSY, QSPI_FLAG_TO, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED, QSPI_INSTRUCTION_NONE, QSPI_IT_TO, QSPI_TIMEOUT_COUNTER_ENABLE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::Timeout, QSPI_MemoryMappedTypeDef::TimeOutActivation, and QSPI_MemoryMappedTypeDef::TimeOutPeriod.

HAL_StatusTypeDef HAL_QSPI_Receive | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Timeout : Timeout duration
Note:
This function is used only in Indirect Read Mode
Return values:
HAL status

Definition at line 906 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pRxBuffPtr, QSPI_FLAG_FT, QSPI_FLAG_TC, QSPI_FUNCTIONAL_MODE_INDIRECT_READ, QSPI_WaitFlagStateUntilTimeout(), QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::RxXferSize, and QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_Receive_DMA | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer.
Note:
This function is used only in Indirect Read Mode
Return values:
HAL status

Definition at line 1203 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, MDMA_InitTypeDef::DestinationInc, QSPI_HandleTypeDef::ErrorCode, HAL_MDMA_Init(), HAL_MDMA_Start_IT(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::hmdma, __MDMA_HandleTypeDef::Init, QSPI_HandleTypeDef::Instance, MDMA_DEST_INC_BYTE, MDMA_SRC_INC_DISABLE, QSPI_HandleTypeDef::pRxBuffPtr, QSPI_DMAError(), QSPI_DMARxCplt(), QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ, QSPI_IT_TE, QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::RxXferSize, MDMA_InitTypeDef::SourceInc, QSPI_HandleTypeDef::State, __MDMA_HandleTypeDef::XferAbortCallback, __MDMA_HandleTypeDef::XferCpltCallback, and __MDMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_QSPI_Receive_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Receive an amount of data in non-blocking mode with interrupt.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Note:
This function is used only in Indirect Read Mode
Return values:
HAL status

Definition at line 1049 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pRxBuffPtr, QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ, QSPI_IT_FT, QSPI_IT_TC, QSPI_IT_TE, QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::RxXferSize, and QSPI_HandleTypeDef::State.

__weak void HAL_QSPI_RxCpltCallback ( QSPI_HandleTypeDef * hqspi )

Rx Transfer completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1635 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

__weak void HAL_QSPI_RxHalfCpltCallback ( QSPI_HandleTypeDef * hqspi )

Rx Half Transfer completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1665 of file stm32h7xx_hal_qspi.c.

__weak void HAL_QSPI_StatusMatchCallback ( QSPI_HandleTypeDef * hqspi )

Status Match callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1710 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

__weak void HAL_QSPI_TimeOutCallback ( QSPI_HandleTypeDef * hqspi )

Timeout callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1725 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

HAL_StatusTypeDef HAL_QSPI_Transmit | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Timeout : Timeout duration
Note:
This function is used only in Indirect Write Mode
Return values:
HAL status

Definition at line 824 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pTxBuffPtr, QSPI_FLAG_FT, QSPI_FLAG_TC, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_WaitFlagStateUntilTimeout(), QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::TxXferCount, and QSPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_QSPI_Transmit_DMA | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Send an amount of data in non-blocking mode with DMA.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Note:
This function is used only in Indirect Write Mode
If MDMA peripheral access is configured as halfword, the number of data and the fifo threshold should be aligned on halfword
If MDMA peripheral access is configured as word, the number of data and the fifo threshold should be aligned on word
Return values:
HAL status

Definition at line 1117 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, MDMA_InitTypeDef::DestinationInc, QSPI_HandleTypeDef::ErrorCode, HAL_MDMA_Init(), HAL_MDMA_Start_IT(), HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::hmdma, __MDMA_HandleTypeDef::Init, QSPI_HandleTypeDef::Instance, MDMA_DEST_INC_DISABLE, MDMA_SRC_INC_BYTE, QSPI_HandleTypeDef::pTxBuffPtr, QSPI_DMAError(), QSPI_DMATxCplt(), QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_IT_TE, MDMA_InitTypeDef::SourceInc, QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::TxXferCount, QSPI_HandleTypeDef::TxXferSize, __MDMA_HandleTypeDef::XferAbortCallback, __MDMA_HandleTypeDef::XferCpltCallback, and __MDMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_QSPI_Transmit_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Send an amount of data in non-blocking mode with interrupt.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Note:
This function is used only in Indirect Write Mode
Return values:
HAL status

Definition at line 989 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pTxBuffPtr, QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_IT_FT, QSPI_IT_TC, QSPI_IT_TE, QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::TxXferCount, and QSPI_HandleTypeDef::TxXferSize.

__weak void HAL_QSPI_TxCpltCallback ( QSPI_HandleTypeDef * hqspi )

Tx Transfer completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1650 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

__weak void HAL_QSPI_TxHalfCpltCallback ( QSPI_HandleTypeDef * hqspi )

Tx Half Transfer completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1680 of file stm32h7xx_hal_qspi.c.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control and State functions

Functions
Peripheral Control and State functions
QSPI Exported Functions

QSPI control and State functions. More...

Functions

HAL_QSPI_StateTypeDef | HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi)
Return the QSPI handle state.
uint32_t | HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi)
Return the QSPI error code.
HAL_StatusTypeDef | HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi)
Abort the current transmission.
HAL_StatusTypeDef | HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi)
Abort the current transmission (non-blocking function)
void | HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
Set QSPI timeout.
HAL_StatusTypeDef | HAL_QSPI_SetFifoThreshold (QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
Set QSPI Fifo threshold.
uint32_t | HAL_QSPI_GetFifoThreshold (QSPI_HandleTypeDef *hqspi)
Get QSPI Fifo threshold.

Detailed Description

QSPI control and State functions.

 ===============================================================================
                  ##### Peripheral Control and State functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to :
      (+) Check in run-time the state of the driver.
      (+) Check the error code set during last operation.
      (+) Abort any operation.

Function Documentation

HAL_StatusTypeDef HAL_QSPI_Abort ( QSPI_HandleTypeDef * hqspi )

Abort the current transmission.

Parameters:
hqspi,: QSPI handle
Return values:
HAL status

Definition at line 1783 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_MDMA_Abort(), HAL_QSPI_ERROR_DMA, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::hmdma, QSPI_HandleTypeDef::Instance, QSPI_FLAG_BUSY, QSPI_FLAG_TC, QSPI_WaitFlagStateUntilTimeout(), QSPI_HandleTypeDef::State, and QSPI_HandleTypeDef::Timeout.

HAL_StatusTypeDef HAL_QSPI_Abort_IT ( QSPI_HandleTypeDef * hqspi )

Abort the current transmission (non-blocking function)

Parameters:
hqspi,: QSPI handle
Return values:
HAL status

Definition at line 1836 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_DISABLE_IT, __HAL_QSPI_ENABLE_IT, HAL_MDMA_Abort_IT(), HAL_QSPI_STATE_ABORT, QSPI_HandleTypeDef::hmdma, QSPI_HandleTypeDef::Instance, QSPI_DMAAbortCplt(), QSPI_FLAG_TC, QSPI_IT_FT, QSPI_IT_SM, QSPI_IT_TC, QSPI_IT_TE, QSPI_IT_TO, QSPI_HandleTypeDef::State, and __MDMA_HandleTypeDef::XferAbortCallback.

Referenced by QSPI_DMAError().

uint32_t HAL_QSPI_GetError ( QSPI_HandleTypeDef * hqspi )

Return the QSPI error code.

Parameters:
hqspi,: QSPI handle
Return values:
QSPI Error Code

Definition at line 1773 of file stm32h7xx_hal_qspi.c.

References QSPI_HandleTypeDef::ErrorCode.

uint32_t HAL_QSPI_GetFifoThreshold ( QSPI_HandleTypeDef * hqspi )

Get QSPI Fifo threshold.

Parameters:
hqspi,: QSPI handle.
Return values:
Fifo threshold (value between 1 and 16)

Definition at line 1923 of file stm32h7xx_hal_qspi.c.

References QSPI_HandleTypeDef::Instance.

HAL_QSPI_StateTypeDef HAL_QSPI_GetState ( QSPI_HandleTypeDef * hqspi )

Return the QSPI handle state.

Parameters:
hqspi,: QSPI handle
Return values:
HAL state

Definition at line 1762 of file stm32h7xx_hal_qspi.c.

References QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint32_t | Threshold
 | ) |  |

Set QSPI Fifo threshold.

Parameters:
hqspi,: QSPI handle.
Threshold,: Threshold of the Fifo (value between 1 and 16).
Return values:
HAL status

Definition at line 1891 of file stm32h7xx_hal_qspi.c.

References QSPI_InitTypeDef::FifoThreshold, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Init, QSPI_HandleTypeDef::Instance, and QSPI_HandleTypeDef::State.

void HAL_QSPI_SetTimeout | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint32_t | Timeout
 | ) |  |

Set QSPI timeout.

Parameters:
hqspi,: QSPI handle.
Timeout,: Timeout for the QSPI memory access.
Return values:
None

Definition at line 1881 of file stm32h7xx_hal_qspi.c.

References QSPI_HandleTypeDef::Timeout.

Referenced by HAL_QSPI_Init().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: QSPI Exported Functions

Modules | Functions
QSPI Exported Functions
QSPI

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

QSPI Transmit/Receive functions.

Peripheral Control and State functions

QSPI control and State functions.

Functions

HAL_StatusTypeDef | HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI mode according to the specified parameters in the QSPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi)
De-Initialize the QSPI peripheral.
void | HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI MSP.
void | HAL_QSPI_MspDeInit (QSPI_HandleTypeDef *hqspi)
DeInitialize the QSPI MSP.
void | HAL_QSPI_IRQHandler (QSPI_HandleTypeDef *hqspi)
Handle QSPI interrupt request.
HAL_StatusTypeDef | HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
Set the command configuration.
HAL_StatusTypeDef | HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
Set the command configuration in interrupt mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
Configure the QSPI Automatic Polling Mode in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
Configure the QSPI Automatic Polling Mode in non-blocking mode.
HAL_StatusTypeDef | HAL_QSPI_MemoryMapped (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
Configure the Memory Mapped mode.
void | HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi)
Transfer Error callback.
void | HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi)
Abort completed callback.
void | HAL_QSPI_FifoThresholdCallback (QSPI_HandleTypeDef *hqspi)
FIFO Threshold callback.
void | HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi)
Command completed callback.
void | HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Transfer completed callback.
void | HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Transfer completed callback.
void | HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Half Transfer completed callback.
void | HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Half Transfer completed callback.
void | HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi)
Status Match callback.
void | HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi)
Timeout callback.
HAL_QSPI_StateTypeDef | HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi)
Return the QSPI handle state.
uint32_t | HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi)
Return the QSPI error code.
HAL_StatusTypeDef | HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi)
Abort the current transmission.
HAL_StatusTypeDef | HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi)
Abort the current transmission (non-blocking function)
void | HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
Set QSPI timeout.
HAL_StatusTypeDef | HAL_QSPI_SetFifoThreshold (QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
Set QSPI Fifo threshold.
uint32_t | HAL_QSPI_GetFifoThreshold (QSPI_HandleTypeDef *hqspi)
Get QSPI Fifo threshold.
static void | QSPI_DMARxCplt (MDMA_HandleTypeDef *hmdma)
DMA QSPI receive process complete callback.
static void | QSPI_DMATxCplt (MDMA_HandleTypeDef *hmdma)
DMA QSPI transmit process complete callback.
static void | QSPI_DMAError (MDMA_HandleTypeDef *hmdma)
DMA QSPI communication error callback.
static void | QSPI_DMAAbortCplt (MDMA_HandleTypeDef *hmdma)
MDMA QSPI abort complete callback.
static HAL_StatusTypeDef | QSPI_WaitFlagStateUntilTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t tickstart, uint32_t Timeout)
Wait for a flag state until timeout.
static void | QSPI_Config (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
Configure the communication registers.

Function Documentation

HAL_StatusTypeDef HAL_QSPI_Abort ( QSPI_HandleTypeDef * hqspi )

Abort the current transmission.

Parameters:
hqspi,: QSPI handle
Return values:
HAL status

Definition at line 1783 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_MDMA_Abort(), HAL_QSPI_ERROR_DMA, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::hmdma, QSPI_HandleTypeDef::Instance, QSPI_FLAG_BUSY, QSPI_FLAG_TC, QSPI_WaitFlagStateUntilTimeout(), QSPI_HandleTypeDef::State, and QSPI_HandleTypeDef::Timeout.

HAL_StatusTypeDef HAL_QSPI_Abort_IT ( QSPI_HandleTypeDef * hqspi )

Abort the current transmission (non-blocking function)

Parameters:
hqspi,: QSPI handle
Return values:
HAL status

Definition at line 1836 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_DISABLE_IT, __HAL_QSPI_ENABLE_IT, HAL_MDMA_Abort_IT(), HAL_QSPI_STATE_ABORT, QSPI_HandleTypeDef::hmdma, QSPI_HandleTypeDef::Instance, QSPI_DMAAbortCplt(), QSPI_FLAG_TC, QSPI_IT_FT, QSPI_IT_SM, QSPI_IT_TC, QSPI_IT_TE, QSPI_IT_TO, QSPI_HandleTypeDef::State, and __MDMA_HandleTypeDef::XferAbortCallback.

Referenced by QSPI_DMAError().

void HAL_QSPI_AbortCpltCallback ( QSPI_HandleTypeDef * hqspi )

Abort completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1605 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

HAL_StatusTypeDef HAL_QSPI_AutoPolling | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | QSPI_AutoPollingTypeDef * | cfg,
 |  | uint32_t | Timeout
 | ) |  |

Configure the QSPI Automatic Polling Mode in blocking mode.

Parameters:
hqspi,: QSPI handle
cmd,: structure that contains the command configuration information.
cfg,: structure that contains the polling configuration information.
Timeout : Timeout duration
Note:
This function is used only in Automatic Polling Mode
Return values:
HAL status

Definition at line 1300 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_AUTO_POLLING, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, QSPI_AutoPollingTypeDef::Interval, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_INTERVAL, IS_QSPI_MATCH_MODE, IS_QSPI_SIOO_MODE, IS_QSPI_STATUS_BYTES_SIZE, QSPI_AutoPollingTypeDef::Mask, QSPI_AutoPollingTypeDef::Match, QSPI_AutoPollingTypeDef::MatchMode, QSPI_CommandTypeDef::NbData, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_AUTOMATIC_STOP_ENABLE, QSPI_Config(), QSPI_FLAG_BUSY, QSPI_FLAG_SM, QSPI_FUNCTIONAL_MODE_AUTO_POLLING, QSPI_INSTRUCTION_NONE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, QSPI_HandleTypeDef::State, and QSPI_AutoPollingTypeDef::StatusBytesSize.

HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | QSPI_AutoPollingTypeDef * | cfg
 | ) |  |

Configure the QSPI Automatic Polling Mode in non-blocking mode.

Parameters:
hqspi,: QSPI handle
cmd,: structure that contains the command configuration information.
cfg,: structure that contains the polling configuration information.
Note:
This function is used only in Automatic Polling Mode
Return values:
HAL status

Definition at line 1400 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_AutoPollingTypeDef::AutomaticStop, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_AUTO_POLLING, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, QSPI_AutoPollingTypeDef::Interval, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_AUTOMATIC_STOP, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_INTERVAL, IS_QSPI_MATCH_MODE, IS_QSPI_SIOO_MODE, IS_QSPI_STATUS_BYTES_SIZE, QSPI_AutoPollingTypeDef::Mask, QSPI_AutoPollingTypeDef::Match, QSPI_AutoPollingTypeDef::MatchMode, QSPI_CommandTypeDef::NbData, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_FLAG_BUSY, QSPI_FLAG_SM, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_AUTO_POLLING, QSPI_INSTRUCTION_NONE, QSPI_IT_SM, QSPI_IT_TE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, QSPI_HandleTypeDef::State, QSPI_AutoPollingTypeDef::StatusBytesSize, and QSPI_HandleTypeDef::Timeout.

void HAL_QSPI_CmdCpltCallback ( QSPI_HandleTypeDef * hqspi )

Command completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1620 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

HAL_StatusTypeDef HAL_QSPI_Command | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | uint32_t | Timeout
 | ) |  |

Set the command configuration.

Parameters:
hqspi,: QSPI handle
cmd | : structure that contains the command configuration information
Timeout | : Timeout duration
Note:
This function is used only in Indirect Read or Write Modes
Return values:
HAL status

Definition at line 634 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY, HAL_QSPI_STATE_READY, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_SIOO_MODE, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_DATA_NONE, QSPI_FLAG_BUSY, QSPI_FLAG_TC, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_INSTRUCTION_NONE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, and QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_Command_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd
 | ) |  |

Set the command configuration in interrupt mode.

Parameters:
hqspi,: QSPI handle
cmd : structure that contains the command configuration information
Note:
This function is used only in Indirect Read or Write Modes
Return values:
HAL status

Definition at line 724 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY, HAL_QSPI_STATE_READY, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_SIOO_MODE, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_DATA_NONE, QSPI_FLAG_BUSY, QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_INSTRUCTION_NONE, QSPI_IT_TC, QSPI_IT_TE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, QSPI_HandleTypeDef::State, and QSPI_HandleTypeDef::Timeout.

HAL_StatusTypeDef HAL_QSPI_DeInit ( QSPI_HandleTypeDef * hqspi )

De-Initialize the QSPI peripheral.

Parameters:
hqspi,: QSPI handle
Return values:
HAL status

Definition at line 327 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_DISABLE, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_NONE, HAL_QSPI_MspDeInit(), HAL_QSPI_STATE_RESET, and QSPI_HandleTypeDef::State.

void HAL_QSPI_ErrorCallback ( QSPI_HandleTypeDef * hqspi )

Transfer Error callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1590 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler(), and QSPI_DMAAbortCplt().

void HAL_QSPI_FifoThresholdCallback ( QSPI_HandleTypeDef * hqspi )

FIFO Threshold callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1695 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

uint32_t HAL_QSPI_GetError ( QSPI_HandleTypeDef * hqspi )

Return the QSPI error code.

Parameters:
hqspi,: QSPI handle
Return values:
QSPI Error Code

Definition at line 1773 of file stm32h7xx_hal_qspi.c.

References QSPI_HandleTypeDef::ErrorCode.

uint32_t HAL_QSPI_GetFifoThreshold ( QSPI_HandleTypeDef * hqspi )

Get QSPI Fifo threshold.

Parameters:
hqspi,: QSPI handle.
Return values:
Fifo threshold (value between 1 and 16)

Definition at line 1923 of file stm32h7xx_hal_qspi.c.

References QSPI_HandleTypeDef::Instance.

HAL_QSPI_StateTypeDef HAL_QSPI_GetState ( QSPI_HandleTypeDef * hqspi )

Return the QSPI handle state.

Parameters:
hqspi,: QSPI handle
Return values:
HAL state

Definition at line 1762 of file stm32h7xx_hal_qspi.c.

References QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_Init ( QSPI_HandleTypeDef * hqspi )

Initialize the QSPI mode according to the specified parameters in the QSPI_InitTypeDef and initialize the associated handle.

Parameters:
hqspi,: QSPI handle
Return values:
HAL status

Definition at line 245 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_ENABLE, assert_param, QSPI_InitTypeDef::ChipSelectHighTime, QSPI_InitTypeDef::ClockMode, QSPI_InitTypeDef::ClockPrescaler, QSPI_InitTypeDef::DualFlash, QSPI_HandleTypeDef::ErrorCode, QSPI_InitTypeDef::FifoThreshold, QSPI_InitTypeDef::FlashID, QSPI_InitTypeDef::FlashSize, HAL_GetTick(), HAL_QPSI_TIMEOUT_DEFAULT_VALUE, HAL_QSPI_ERROR_NONE, HAL_QSPI_MspInit(), HAL_QSPI_SetTimeout(), HAL_QSPI_STATE_READY, HAL_QSPI_STATE_RESET, QSPI_HandleTypeDef::Init, QSPI_HandleTypeDef::Instance, IS_QSPI_CLOCK_MODE, IS_QSPI_CLOCK_PRESCALER, IS_QSPI_CS_HIGH_TIME, IS_QSPI_DUAL_FLASH_MODE, IS_QSPI_FIFO_THRESHOLD, IS_QSPI_FLASH_ID, IS_QSPI_FLASH_SIZE, IS_QSPI_SSHIFT, QSPI_HandleTypeDef::Lock, QSPI_DUALFLASH_ENABLE, QSPI_FLAG_BUSY, QSPI_WaitFlagStateUntilTimeout(), QSPI_InitTypeDef::SampleShifting, QSPI_HandleTypeDef::State, and QSPI_HandleTypeDef::Timeout.

void HAL_QSPI_IRQHandler ( QSPI_HandleTypeDef * hqspi )

Handle QSPI interrupt request.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 415 of file stm32h7xx_hal_qspi.c.

References __HAL_MDMA_DISABLE, __HAL_QSPI_DISABLE_IT, __HAL_QSPI_GET_FLAG, QSPI_HandleTypeDef::ErrorCode, HAL_MDMA_Abort_IT(), HAL_QSPI_AbortCpltCallback(), HAL_QSPI_CmdCpltCallback(), HAL_QSPI_ERROR_NONE, HAL_QSPI_ERROR_TRANSFER, HAL_QSPI_ErrorCallback(), HAL_QSPI_FifoThresholdCallback(), HAL_QSPI_RxCpltCallback(), HAL_QSPI_STATE_ABORT, HAL_QSPI_STATE_BUSY, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, HAL_QSPI_StatusMatchCallback(), HAL_QSPI_TimeOutCallback(), HAL_QSPI_TxCpltCallback(), QSPI_HandleTypeDef::hmdma, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pRxBuffPtr, QSPI_HandleTypeDef::pTxBuffPtr, QSPI_DMAAbortCplt(), QSPI_FLAG_FT, QSPI_FLAG_SM, QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FLAG_TO, QSPI_IT_FT, QSPI_IT_SM, QSPI_IT_TC, QSPI_IT_TE, QSPI_IT_TO, QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::TxXferCount, and __MDMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_QSPI_MemoryMapped | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | QSPI_MemoryMappedTypeDef * | cfg
 | ) |  |

Configure the Memory Mapped mode.

Parameters:
hqspi,: QSPI handle
cmd,: structure that contains the command configuration information.
cfg,: structure that contains the memory mapped configuration information.
Note:
This function is used only in Memory mapped Mode
Return values:
HAL status

Definition at line 1504 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_MEM_MAPPED, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_SIOO_MODE, IS_QSPI_TIMEOUT_ACTIVATION, IS_QSPI_TIMEOUT_PERIOD, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_FLAG_BUSY, QSPI_FLAG_TO, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED, QSPI_INSTRUCTION_NONE, QSPI_IT_TO, QSPI_TIMEOUT_COUNTER_ENABLE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::Timeout, QSPI_MemoryMappedTypeDef::TimeOutActivation, and QSPI_MemoryMappedTypeDef::TimeOutPeriod.

void HAL_QSPI_MspDeInit ( QSPI_HandleTypeDef * hqspi )

DeInitialize the QSPI MSP.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 376 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_DeInit().

void HAL_QSPI_MspInit ( QSPI_HandleTypeDef * hqspi )

Initialize the QSPI MSP.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 361 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_Init().

HAL_StatusTypeDef HAL_QSPI_Receive | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Timeout : Timeout duration
Note:
This function is used only in Indirect Read Mode
Return values:
HAL status

Definition at line 906 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pRxBuffPtr, QSPI_FLAG_FT, QSPI_FLAG_TC, QSPI_FUNCTIONAL_MODE_INDIRECT_READ, QSPI_WaitFlagStateUntilTimeout(), QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::RxXferSize, and QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_Receive_DMA | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer.
Note:
This function is used only in Indirect Read Mode
Return values:
HAL status

Definition at line 1203 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, MDMA_InitTypeDef::DestinationInc, QSPI_HandleTypeDef::ErrorCode, HAL_MDMA_Init(), HAL_MDMA_Start_IT(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::hmdma, __MDMA_HandleTypeDef::Init, QSPI_HandleTypeDef::Instance, MDMA_DEST_INC_BYTE, MDMA_SRC_INC_DISABLE, QSPI_HandleTypeDef::pRxBuffPtr, QSPI_DMAError(), QSPI_DMARxCplt(), QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ, QSPI_IT_TE, QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::RxXferSize, MDMA_InitTypeDef::SourceInc, QSPI_HandleTypeDef::State, __MDMA_HandleTypeDef::XferAbortCallback, __MDMA_HandleTypeDef::XferCpltCallback, and __MDMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_QSPI_Receive_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Receive an amount of data in non-blocking mode with interrupt.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Note:
This function is used only in Indirect Read Mode
Return values:
HAL status

Definition at line 1049 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pRxBuffPtr, QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ, QSPI_IT_FT, QSPI_IT_TC, QSPI_IT_TE, QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::RxXferSize, and QSPI_HandleTypeDef::State.

void HAL_QSPI_RxCpltCallback ( QSPI_HandleTypeDef * hqspi )

Rx Transfer completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1635 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

void HAL_QSPI_RxHalfCpltCallback ( QSPI_HandleTypeDef * hqspi )

Rx Half Transfer completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1665 of file stm32h7xx_hal_qspi.c.

HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint32_t | Threshold
 | ) |  |

Set QSPI Fifo threshold.

Parameters:
hqspi,: QSPI handle.
Threshold,: Threshold of the Fifo (value between 1 and 16).
Return values:
HAL status

Definition at line 1891 of file stm32h7xx_hal_qspi.c.

References QSPI_InitTypeDef::FifoThreshold, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Init, QSPI_HandleTypeDef::Instance, and QSPI_HandleTypeDef::State.

void HAL_QSPI_SetTimeout | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint32_t | Timeout
 | ) |  |

Set QSPI timeout.

Parameters:
hqspi,: QSPI handle.
Timeout,: Timeout for the QSPI memory access.
Return values:
None

Definition at line 1881 of file stm32h7xx_hal_qspi.c.

References QSPI_HandleTypeDef::Timeout.

Referenced by HAL_QSPI_Init().

void HAL_QSPI_StatusMatchCallback ( QSPI_HandleTypeDef * hqspi )

Status Match callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1710 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

void HAL_QSPI_TimeOutCallback ( QSPI_HandleTypeDef * hqspi )

Timeout callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1725 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

HAL_StatusTypeDef HAL_QSPI_Transmit | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Timeout : Timeout duration
Note:
This function is used only in Indirect Write Mode
Return values:
HAL status

Definition at line 824 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pTxBuffPtr, QSPI_FLAG_FT, QSPI_FLAG_TC, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_WaitFlagStateUntilTimeout(), QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::TxXferCount, and QSPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_QSPI_Transmit_DMA | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Send an amount of data in non-blocking mode with DMA.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Note:
This function is used only in Indirect Write Mode
If MDMA peripheral access is configured as halfword, the number of data and the fifo threshold should be aligned on halfword
If MDMA peripheral access is configured as word, the number of data and the fifo threshold should be aligned on word
Return values:
HAL status

Definition at line 1117 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, MDMA_InitTypeDef::DestinationInc, QSPI_HandleTypeDef::ErrorCode, HAL_MDMA_Init(), HAL_MDMA_Start_IT(), HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::hmdma, __MDMA_HandleTypeDef::Init, QSPI_HandleTypeDef::Instance, MDMA_DEST_INC_DISABLE, MDMA_SRC_INC_BYTE, QSPI_HandleTypeDef::pTxBuffPtr, QSPI_DMAError(), QSPI_DMATxCplt(), QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_IT_TE, MDMA_InitTypeDef::SourceInc, QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::TxXferCount, QSPI_HandleTypeDef::TxXferSize, __MDMA_HandleTypeDef::XferAbortCallback, __MDMA_HandleTypeDef::XferCpltCallback, and __MDMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_QSPI_Transmit_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Send an amount of data in non-blocking mode with interrupt.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Note:
This function is used only in Indirect Write Mode
Return values:
HAL status

Definition at line 989 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pTxBuffPtr, QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_IT_FT, QSPI_IT_TC, QSPI_IT_TE, QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::TxXferCount, and QSPI_HandleTypeDef::TxXferSize.

void HAL_QSPI_TxCpltCallback ( QSPI_HandleTypeDef * hqspi )

Tx Transfer completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1650 of file stm32h7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

void HAL_QSPI_TxHalfCpltCallback ( QSPI_HandleTypeDef * hqspi )

Tx Half Transfer completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1680 of file stm32h7xx_hal_qspi.c.

static void QSPI_Config | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | uint32_t | FunctionalMode
 | ) |  | [static]

Configure the communication registers.

Parameters:
hqspi,: QSPI handle
cmd,: structure that contains the command configuration information
FunctionalMode,: functional mode to configured This parameter can be one of the following values:
  • QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
  • QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
  • QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
  • QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
Return values:
None

Definition at line 2056 of file stm32h7xx_hal_qspi.c.

References QSPI_CommandTypeDef::Address, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytes, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_FUNCTIONAL_MODE, QSPI_CommandTypeDef::NbData, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_DATA_NONE, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED, QSPI_INSTRUCTION_NONE, and QSPI_CommandTypeDef::SIOOMode.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

static void QSPI_DMAAbortCplt ( MDMA_HandleTypeDef * hmdma ) [static]

MDMA QSPI abort complete callback.

Parameters:
hmdma,: MDMA handle
Return values:
None

Definition at line 1985 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, HAL_QSPI_ErrorCallback(), HAL_QSPI_STATE_ABORT, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_FLAG_TC, QSPI_IT_TC, QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::State, and QSPI_HandleTypeDef::TxXferCount.

Referenced by HAL_QSPI_Abort_IT(), and HAL_QSPI_IRQHandler().

static void QSPI_DMAError ( MDMA_HandleTypeDef * hmdma ) [static]

DMA QSPI communication error callback.

Parameters:
hmdma,: MDMA handle
Return values:
None

Definition at line 1965 of file stm32h7xx_hal_qspi.c.

References QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_Abort_IT(), HAL_QSPI_ERROR_DMA, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::RxXferCount, and QSPI_HandleTypeDef::TxXferCount.

Referenced by HAL_QSPI_Receive_DMA(), and HAL_QSPI_Transmit_DMA().

static void QSPI_DMARxCplt ( MDMA_HandleTypeDef * hmdma ) [static]

DMA QSPI receive process complete callback.

Parameters:
hmdma,: MDMA handle
Return values:
None

Definition at line 1937 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_ENABLE_IT, QSPI_IT_TC, and QSPI_HandleTypeDef::RxXferCount.

Referenced by HAL_QSPI_Receive_DMA().

static void QSPI_DMATxCplt ( MDMA_HandleTypeDef * hmdma ) [static]

DMA QSPI transmit process complete callback.

Parameters:
hmdma,: MDMA handle
Return values:
None

Definition at line 1951 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_ENABLE_IT, QSPI_IT_TC, and QSPI_HandleTypeDef::TxXferCount.

Referenced by HAL_QSPI_Transmit_DMA().

static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint32_t | Flag,
 |  | FlagStatus | State,
 |  | uint32_t | tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Wait for a flag state until timeout.

Parameters:
hqspi,: QSPI handle
Flag,: Flag checked
State,: Value of the flag expected
tickstart,: Tick start value
Timeout,: Duration of the timeout
Return values:
HAL status

Definition at line 2023 of file stm32h7xx_hal_qspi.c.

References __HAL_QSPI_GET_FLAG, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_TIMEOUT, HAL_QSPI_STATE_ERROR, and QSPI_HandleTypeDef::State.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_Init(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), and HAL_QSPI_Transmit().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: QSPI Exported Types

Data Structures | Enumerations
QSPI Exported Types
QSPI

Data Structures

struct | QSPI_InitTypeDef
QSPI Init structure definition. More...
struct | QSPI_HandleTypeDef
QSPI Handle Structure definition. More...
struct | QSPI_CommandTypeDef
QSPI Command structure definition. More...
struct | QSPI_AutoPollingTypeDef
QSPI Auto Polling mode configuration structure definition. More...
struct | QSPI_MemoryMappedTypeDef
QSPI Memory Mapped mode configuration structure definition. More...

Enumerations

enum HAL_QSPI_StateTypeDef {
HAL_QSPI_STATE_RESET = 0x00U, HAL_QSPI_STATE_READY = 0x01U, HAL_QSPI_STATE_BUSY = 0x02U, HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U,
HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, HAL_QSPI_STATE_ABORT = 0x08U,
HAL_QSPI_STATE_ERROR = 0x04U
}
HAL QSPI State structures definition. More...

Enumeration Type Documentation

enum HAL_QSPI_StateTypeDef

HAL QSPI State structures definition.

Enumerator:
HAL_QSPI_STATE_RESET

Peripheral not initialized

HAL_QSPI_STATE_READY

Peripheral initialized and ready for use

HAL_QSPI_STATE_BUSY

Peripheral in indirect mode and busy

HAL_QSPI_STATE_BUSY_INDIRECT_TX

Peripheral in indirect mode with transmission ongoing

HAL_QSPI_STATE_BUSY_INDIRECT_RX

Peripheral in indirect mode with reception ongoing

HAL_QSPI_STATE_BUSY_AUTO_POLLING

Peripheral in auto polling mode ongoing

HAL_QSPI_STATE_BUSY_MEM_MAPPED

Peripheral in memory mapped mode ongoing

HAL_QSPI_STATE_ABORT

Peripheral with abort request ongoing

HAL_QSPI_STATE_ERROR

Peripheral in error

Definition at line 102 of file stm32h7xx_hal_qspi.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: QSPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
QSPI_InitTypeDef Struct Reference
QSPI Exported Types

QSPI Init structure definition. More...

#include <stm32h7xx_hal_qspi.h>

Data Fields

uint32_t | ClockPrescaler
uint32_t | FifoThreshold
uint32_t | SampleShifting
uint32_t | FlashSize
uint32_t | ChipSelectHighTime
uint32_t | ClockMode
uint32_t | FlashID
uint32_t | DualFlash

Detailed Description

QSPI Init structure definition.

Definition at line 67 of file stm32h7xx_hal_qspi.h.

Field Documentation

uint32_t QSPI_InitTypeDef::ChipSelectHighTime

Definition at line 85 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint32_t QSPI_InitTypeDef::ClockMode

Definition at line 89 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint32_t QSPI_InitTypeDef::ClockPrescaler

Definition at line 69 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint32_t QSPI_InitTypeDef::DualFlash

Definition at line 95 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint32_t QSPI_InitTypeDef::FifoThreshold

Definition at line 72 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init(), and HAL_QSPI_SetFifoThreshold().

uint32_t QSPI_InitTypeDef::FlashID

Definition at line 92 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint32_t QSPI_InitTypeDef::FlashSize

Definition at line 79 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint32_t QSPI_InitTypeDef::SampleShifting

Definition at line 75 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_qspi.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: QSPI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
QSPI_HandleTypeDef Struct Reference
QSPI Exported Types

QSPI Handle Structure definition. More...

#include <stm32h7xx_hal_qspi.h>

Data Fields

QUADSPI_TypeDef * | Instance
QSPI_InitTypeDef Init
uint8_t * | pTxBuffPtr
__IO uint32_t | TxXferSize
__IO uint32_t | TxXferCount
uint8_t * | pRxBuffPtr
__IO uint32_t | RxXferSize
__IO uint32_t | RxXferCount
MDMA_HandleTypeDef * hmdma
__IO HAL_LockTypeDef | Lock
__IO HAL_QSPI_StateTypeDef | State
__IO uint32_t | ErrorCode
uint32_t | Timeout

Detailed Description

QSPI Handle Structure definition.

Definition at line 118 of file stm32h7xx_hal_qspi.h.

Field Documentation

__IO uint32_t QSPI_HandleTypeDef::ErrorCode

Definition at line 131 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_DeInit(), HAL_QSPI_GetError(), HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), QSPI_DMAError(), and QSPI_WaitFlagStateUntilTimeout().

MDMA_HandleTypeDef* QSPI_HandleTypeDef::hmdma

Definition at line 128 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_Abort_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_DMA(), and HAL_QSPI_Transmit_DMA().

QSPI_InitTypeDef QSPI_HandleTypeDef::Init

Definition at line 121 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init(), and HAL_QSPI_SetFifoThreshold().

QUADSPI_TypeDef* QSPI_HandleTypeDef::Instance

Definition at line 120 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_Abort_IT(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_GetFifoThreshold(), HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_SetFifoThreshold(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), QSPI_Config(), QSPI_DMAAbortCplt(), and QSPI_DMAError().

__IO HAL_LockTypeDef QSPI_HandleTypeDef::Lock

Definition at line 129 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint8_t* QSPI_HandleTypeDef::pRxBuffPtr

Definition at line 125 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), and HAL_QSPI_Receive_IT().

uint8_t* QSPI_HandleTypeDef::pTxBuffPtr

Definition at line 122 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

__IO uint32_t QSPI_HandleTypeDef::RxXferCount

Definition at line 127 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), QSPI_DMAAbortCplt(), QSPI_DMAError(), and QSPI_DMARxCplt().

__IO uint32_t QSPI_HandleTypeDef::RxXferSize

Definition at line 126 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), and HAL_QSPI_Receive_IT().

__IO HAL_QSPI_StateTypeDef QSPI_HandleTypeDef::State

Definition at line 130 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_Abort_IT(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_DeInit(), HAL_QSPI_GetState(), HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_SetFifoThreshold(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), QSPI_DMAAbortCplt(), and QSPI_WaitFlagStateUntilTimeout().

uint32_t QSPI_HandleTypeDef::Timeout

Definition at line 132 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command_IT(), HAL_QSPI_Init(), HAL_QSPI_MemoryMapped(), and HAL_QSPI_SetTimeout().

__IO uint32_t QSPI_HandleTypeDef::TxXferCount

Definition at line 124 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), QSPI_DMAAbortCplt(), QSPI_DMAError(), and QSPI_DMATxCplt().

__IO uint32_t QSPI_HandleTypeDef::TxXferSize

Definition at line 123 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_qspi.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: QSPI_CommandTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
QSPI_CommandTypeDef Struct Reference
QSPI Exported Types

QSPI Command structure definition. More...

#include <stm32h7xx_hal_qspi.h>

Data Fields

uint32_t | Instruction
uint32_t | Address
uint32_t | AlternateBytes
uint32_t | AddressSize
uint32_t | AlternateBytesSize
uint32_t | DummyCycles
uint32_t | InstructionMode
uint32_t | AddressMode
uint32_t | AlternateByteMode
uint32_t | DataMode
uint32_t | NbData
uint32_t | DdrMode
uint32_t | DdrHoldHalfCycle
uint32_t | SIOOMode

Detailed Description

QSPI Command structure definition.

Definition at line 138 of file stm32h7xx_hal_qspi.h.

Field Documentation

uint32_t QSPI_CommandTypeDef::Address

Definition at line 142 of file stm32h7xx_hal_qspi.h.

Referenced by QSPI_Config().

uint32_t QSPI_CommandTypeDef::AddressMode

Definition at line 154 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::AddressSize

Definition at line 146 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::AlternateByteMode

Definition at line 156 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::AlternateBytes

Definition at line 144 of file stm32h7xx_hal_qspi.h.

Referenced by QSPI_Config().

uint32_t QSPI_CommandTypeDef::AlternateBytesSize

Definition at line 148 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::DataMode

Definition at line 158 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::DdrHoldHalfCycle

Definition at line 165 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::DdrMode

Definition at line 163 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::DummyCycles

Definition at line 150 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::Instruction

Definition at line 140 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::InstructionMode

Definition at line 152 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::NbData

Definition at line 160 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::SIOOMode

Definition at line 168 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_qspi.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: QSPI_AutoPollingTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
QSPI_AutoPollingTypeDef Struct Reference
QSPI Exported Types

QSPI Auto Polling mode configuration structure definition. More...

#include <stm32h7xx_hal_qspi.h>

Data Fields

uint32_t | Match
uint32_t | Mask
uint32_t | Interval
uint32_t | StatusBytesSize
uint32_t | MatchMode
uint32_t | AutomaticStop

Detailed Description

QSPI Auto Polling mode configuration structure definition.

Definition at line 175 of file stm32h7xx_hal_qspi.h.

Field Documentation

uint32_t QSPI_AutoPollingTypeDef::AutomaticStop

Definition at line 187 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling_IT().

uint32_t QSPI_AutoPollingTypeDef::Interval

Definition at line 181 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

uint32_t QSPI_AutoPollingTypeDef::Mask

Definition at line 179 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

uint32_t QSPI_AutoPollingTypeDef::Match

Definition at line 177 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

uint32_t QSPI_AutoPollingTypeDef::MatchMode

Definition at line 185 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

uint32_t QSPI_AutoPollingTypeDef::StatusBytesSize

Definition at line 183 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_qspi.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: QSPI_MemoryMappedTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
QSPI_MemoryMappedTypeDef Struct Reference
QSPI Exported Types

QSPI Memory Mapped mode configuration structure definition. More...

#include <stm32h7xx_hal_qspi.h>

Data Fields

uint32_t | TimeOutPeriod
uint32_t | TimeOutActivation

Detailed Description

QSPI Memory Mapped mode configuration structure definition.

Definition at line 194 of file stm32h7xx_hal_qspi.h.

Field Documentation

uint32_t QSPI_MemoryMappedTypeDef::TimeOutActivation

Definition at line 198 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_MemoryMapped().

uint32_t QSPI_MemoryMappedTypeDef::TimeOutPeriod

Definition at line 196 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_MemoryMapped().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_qspi.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: QSPI Error Code

Defines
QSPI Error Code
QSPI Exported Constants

Defines

#define | HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U)
#define | HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U)
#define | HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U)
#define | HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U)

Define Documentation

#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U)

DMA transfer error

Definition at line 217 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), and QSPI_DMAError().

#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U)

Invalid parameters error

Definition at line 218 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Receive(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 214 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_DeInit(), HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U)

Timeout error

Definition at line 215 of file stm32h7xx_hal_qspi.h.

Referenced by QSPI_WaitFlagStateUntilTimeout().

#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U)

Transfer error

Definition at line 216 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler().

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STM32H753xx HAL User Manual: QSPI Sample Shifting

Defines
QSPI Sample Shifting
QSPI Exported Constants

Defines

#define | QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U)
#define | QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT)

Define Documentation

#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT)

1/2 clock cycle shift to sample data

Definition at line 227 of file stm32h7xx_hal_qspi.h.

#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U)

No clock cycle shift to sample data

Definition at line 226 of file stm32h7xx_hal_qspi.h.

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STM32H753xx HAL User Manual: QSPI ChipSelect High Time

Defines
QSPI ChipSelect High Time
QSPI Exported Constants

Defines

#define | QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000U)
#define | QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0)
#define | QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2)
#define | QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0)
#define | QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT)

Define Documentation

#define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000U)

nCS stay high for at least 1 clock cycle between commands

Definition at line 235 of file stm32h7xx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0)

nCS stay high for at least 2 clock cycles between commands

Definition at line 236 of file stm32h7xx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1)

nCS stay high for at least 3 clock cycles between commands

Definition at line 237 of file stm32h7xx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1)

nCS stay high for at least 4 clock cycles between commands

Definition at line 238 of file stm32h7xx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2)

nCS stay high for at least 5 clock cycles between commands

Definition at line 239 of file stm32h7xx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0)

nCS stay high for at least 6 clock cycles between commands

Definition at line 240 of file stm32h7xx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1)

nCS stay high for at least 7 clock cycles between commands

Definition at line 241 of file stm32h7xx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT)

nCS stay high for at least 8 clock cycles between commands

Definition at line 242 of file stm32h7xx_hal_qspi.h.

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STM32H753xx HAL User Manual: QSPI Clock Mode

Defines
QSPI Clock Mode
QSPI Exported Constants

Defines

#define | QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000)
#define | QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE)

Define Documentation

#define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000)

Clk stays low while nCS is released

Definition at line 250 of file stm32h7xx_hal_qspi.h.

#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE)

Clk goes high while nCS is released

Definition at line 251 of file stm32h7xx_hal_qspi.h.

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STM32H753xx HAL User Manual: QSPI Flash Select

Defines
QSPI Flash Select
QSPI Exported Constants

Defines

#define | QSPI_FLASH_ID_1 ((uint32_t)0x00000000)
#define | QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)

Define Documentation

#define QSPI_FLASH_ID_1 ((uint32_t)0x00000000)

FLASH 1 selected

Definition at line 259 of file stm32h7xx_hal_qspi.h.

#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)

FLASH 2 selected

Definition at line 260 of file stm32h7xx_hal_qspi.h.

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STM32H753xx HAL User Manual: QSPI Dual Flash Mode

Defines
QSPI Dual Flash Mode
QSPI Exported Constants

Defines

#define | QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
#define | QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000)

Dual-flash mode disabled

Definition at line 269 of file stm32h7xx_hal_qspi.h.

#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)

Dual-flash mode enabled

Definition at line 268 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

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STM32H753xx HAL User Manual: QSPI Address Size

Defines
QSPI Address Size
QSPI Exported Constants

Defines

#define | QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000)
#define | QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0)
#define | QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1)
#define | QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE)

Define Documentation

#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0)

16-bit address

Definition at line 278 of file stm32h7xx_hal_qspi.h.

#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1)

24-bit address

Definition at line 279 of file stm32h7xx_hal_qspi.h.

#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE)

32-bit address

Definition at line 280 of file stm32h7xx_hal_qspi.h.

#define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000)

8-bit address

Definition at line 277 of file stm32h7xx_hal_qspi.h.

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STM32H753xx HAL User Manual: QSPI Alternate Bytes Size

Defines
QSPI Alternate Bytes Size
QSPI Exported Constants

Defines

#define | QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000)
#define | QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0)
#define | QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1)
#define | QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE)

Define Documentation

#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0)

16-bit alternate bytes

Definition at line 289 of file stm32h7xx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1)

24-bit alternate bytes

Definition at line 290 of file stm32h7xx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE)

32-bit alternate bytes

Definition at line 291 of file stm32h7xx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000)

8-bit alternate bytes

Definition at line 288 of file stm32h7xx_hal_qspi.h.

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STM32H753xx HAL User Manual: QSPI Instruction Mode

Defines
QSPI Instruction Mode
QSPI Exported Constants

Defines

#define | QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000)
#define | QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0)
#define | QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1)
#define | QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE)

Define Documentation

#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0)

Instruction on a single line

Definition at line 300 of file stm32h7xx_hal_qspi.h.

#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1)

Instruction on two lines

Definition at line 301 of file stm32h7xx_hal_qspi.h.

#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE)

Instruction on four lines

Definition at line 302 of file stm32h7xx_hal_qspi.h.

#define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000)

No instruction

Definition at line 299 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: QSPI Address Mode

Defines
QSPI Address Mode
QSPI Exported Constants

Defines

#define | QSPI_ADDRESS_NONE ((uint32_t)0x00000000)
#define | QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0)
#define | QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1)
#define | QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE)

Define Documentation

#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0)

Address on a single line

Definition at line 311 of file stm32h7xx_hal_qspi.h.

#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1)

Address on two lines

Definition at line 312 of file stm32h7xx_hal_qspi.h.

#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE)

Address on four lines

Definition at line 313 of file stm32h7xx_hal_qspi.h.

#define QSPI_ADDRESS_NONE ((uint32_t)0x00000000)

No address

Definition at line 310 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: QSPI Alternate Bytes Mode

Defines
QSPI Alternate Bytes Mode
QSPI Exported Constants

Defines

#define | QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000)
#define | QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0)
#define | QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1)
#define | QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE)

Define Documentation

#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0)

Alternate bytes on a single line

Definition at line 322 of file stm32h7xx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1)

Alternate bytes on two lines

Definition at line 323 of file stm32h7xx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE)

Alternate bytes on four lines

Definition at line 324 of file stm32h7xx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000)

No alternate bytes

Definition at line 321 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

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STM32H753xx HAL User Manual: QSPI Data Mode

Defines
QSPI Data Mode
QSPI Exported Constants

Defines

#define | QSPI_DATA_NONE ((uint32_t)0X00000000)
#define | QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0)
#define | QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1)
#define | QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE)

Define Documentation

#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0)

Data on a single line

Definition at line 333 of file stm32h7xx_hal_qspi.h.

#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1)

Data on two lines

Definition at line 334 of file stm32h7xx_hal_qspi.h.

#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE)

Data on four lines

Definition at line 335 of file stm32h7xx_hal_qspi.h.

#define QSPI_DATA_NONE ((uint32_t)0X00000000)

No data

Definition at line 332 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and QSPI_Config().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: QSPI DDR Mode

Defines
QSPI DDR Mode
QSPI Exported Constants

Defines

#define | QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000)
#define | QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM)

Define Documentation

#define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000)

Double data rate mode disabled

Definition at line 343 of file stm32h7xx_hal_qspi.h.

#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM)

Double data rate mode enabled

Definition at line 344 of file stm32h7xx_hal_qspi.h.

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STM32H753xx HAL User Manual: QSPI DDR Data Output Delay

Defines
QSPI DDR Data Output Delay
QSPI Exported Constants

Defines

#define | QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000)
#define | QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC)

Define Documentation

#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000)

Delay the data output using analog delay in DDR mode

Definition at line 352 of file stm32h7xx_hal_qspi.h.

#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC)

Delay the data output by 1/2 clock cycle in DDR mode

Definition at line 353 of file stm32h7xx_hal_qspi.h.

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STM32H753xx HAL User Manual: QSPI Send Instruction Mode

Defines
QSPI Send Instruction Mode
QSPI Exported Constants

Defines

#define | QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000)
#define | QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO)

Define Documentation

#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000)

Send instruction on every transaction

Definition at line 361 of file stm32h7xx_hal_qspi.h.

#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO)

Send instruction only for the first command

Definition at line 362 of file stm32h7xx_hal_qspi.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: QSPI Match Mode

Defines
QSPI Match Mode
QSPI Exported Constants

Defines

#define | QSPI_MATCH_MODE_AND ((uint32_t)0x00000000)
#define | QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM)

Define Documentation

#define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000)

AND match mode between unmasked bits

Definition at line 370 of file stm32h7xx_hal_qspi.h.

#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM)

OR match mode between unmasked bits

Definition at line 371 of file stm32h7xx_hal_qspi.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: QSPI Automatic Stop

Defines
QSPI Automatic Stop
QSPI Exported Constants

Defines

#define | QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000)
#define | QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS)

Define Documentation

#define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000)

AutoPolling stops only with abort or QSPI disabling

Definition at line 379 of file stm32h7xx_hal_qspi.h.

#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS)

AutoPolling stops as soon as there is a match

Definition at line 380 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling().

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STM32H753xx HAL User Manual: QSPI Timeout Activation

Defines
QSPI Timeout Activation
QSPI Exported Constants

Defines

#define | QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000)
#define | QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN)

Define Documentation

#define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000)

Timeout counter disabled, nCS remains active

Definition at line 388 of file stm32h7xx_hal_qspi.h.

#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN)

Timeout counter enabled, nCS released when timeout expires

Definition at line 389 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_MemoryMapped().

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STM32H753xx HAL User Manual: QSPI Flags

Defines
QSPI Flags
QSPI Exported Constants

Defines

#define | QSPI_FLAG_BUSY QUADSPI_SR_BUSY
#define | QSPI_FLAG_TO QUADSPI_SR_TOF
#define | QSPI_FLAG_SM QUADSPI_SR_SMF
#define | QSPI_FLAG_FT QUADSPI_SR_FTF
#define | QSPI_FLAG_TC QUADSPI_SR_TCF
#define | QSPI_FLAG_TE QUADSPI_SR_TEF

Define Documentation

#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY

Busy flag: operation is ongoing

Definition at line 397 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_Init(), and HAL_QSPI_MemoryMapped().

#define QSPI_FLAG_FT QUADSPI_SR_FTF

Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete

Definition at line 400 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Receive(), and HAL_QSPI_Transmit().

#define QSPI_FLAG_SM QUADSPI_SR_SMF

Status match flag: received data matches in autopolling mode

Definition at line 399 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), and HAL_QSPI_IRQHandler().

#define QSPI_FLAG_TC QUADSPI_SR_TCF

Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted

Definition at line 401 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_Abort_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), and QSPI_DMAAbortCplt().

#define QSPI_FLAG_TE QUADSPI_SR_TEF

Transfer error flag: invalid address is being accessed

Definition at line 402 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

#define QSPI_FLAG_TO QUADSPI_SR_TOF

Timeout flag: timeout occurs in memory-mapped mode

Definition at line 398 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), and HAL_QSPI_MemoryMapped().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: QSPI Interrupts

Defines
QSPI Interrupts
QSPI Exported Constants

Defines

#define | QSPI_IT_TO QUADSPI_CR_TOIE
#define | QSPI_IT_SM QUADSPI_CR_SMIE
#define | QSPI_IT_FT QUADSPI_CR_FTIE
#define | QSPI_IT_TC QUADSPI_CR_TCIE
#define | QSPI_IT_TE QUADSPI_CR_TEIE

Define Documentation

#define QSPI_IT_FT QUADSPI_CR_FTIE

Interrupt on the fifo threshold flag

Definition at line 412 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_IT(), and HAL_QSPI_Transmit_IT().

#define QSPI_IT_SM QUADSPI_CR_SMIE

Interrupt on the status match flag

Definition at line 411 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_AutoPolling_IT(), and HAL_QSPI_IRQHandler().

#define QSPI_IT_TC QUADSPI_CR_TCIE

Interrupt on the transfer complete flag

Definition at line 413 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_Command_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit_IT(), QSPI_DMAAbortCplt(), QSPI_DMARxCplt(), and QSPI_DMATxCplt().

#define QSPI_IT_TE QUADSPI_CR_TEIE

Interrupt on the transfer error flag

Definition at line 414 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

#define QSPI_IT_TO QUADSPI_CR_TOIE

Interrupt on the timeout flag

Definition at line 410 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_IRQHandler(), and HAL_QSPI_MemoryMapped().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: QSPI Timeout definition

Defines
QSPI Timeout definition
QSPI Exported Constants

QSPI Timeout definition. More...

Defines

#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */

Detailed Description

QSPI Timeout definition.

Define Documentation

#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */

Definition at line 423 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: QSPI Exported Macros

Defines
QSPI Exported Macros
QSPI

Defines

#define | __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
Reset QSPI handle state.
#define | __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
Enable the QSPI peripheral.
#define | __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
Disable the QSPI peripheral.
#define | __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Enable the specified QSPI interrupt.
#define | __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Disable the specified QSPI interrupt.
#define | __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified QSPI interrupt source is enabled or not.
#define | __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
Check whether the selected QSPI flag is set or not.
#define | __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
Clears the specified QSPI's flag status.

Define Documentation

#define __HAL_QSPI_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))

Clears the specified QSPI's flag status.

Parameters:
__HANDLE__,: specifies the QSPI Handle.
__FLAG__,: specifies the QSPI clear register flag that needs to be set This parameter can be one of the following values:
  • QSPI_FLAG_TO: QSPI Timeout flag
  • QSPI_FLAG_SM: QSPI Status match flag
  • QSPI_FLAG_TC: QSPI Transfer complete flag
  • QSPI_FLAG_TE: QSPI Transfer error flag
Return values:
None

Definition at line 519 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_Abort_IT(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), and QSPI_DMAAbortCplt().

#define __HAL_QSPI_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)

Disable the QSPI peripheral.

Parameters:
__HANDLE__,: specifies the QSPI Handle.
Return values:
None

Definition at line 452 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_DeInit().

#define __HAL_QSPI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))

Disable the specified QSPI interrupt.

Parameters:
__HANDLE__,: specifies the QSPI Handle.
__INTERRUPT__,: specifies the QSPI interrupt source to disable. This parameter can be one of the following values:
  • QSPI_IT_TO: QSPI Timeout interrupt
  • QSPI_IT_SM: QSPI Status match interrupt
  • QSPI_IT_FT: QSPI FIFO threshold interrupt
  • QSPI_IT_TC: QSPI Transfer complete interrupt
  • QSPI_IT_TE: QSPI Transfer error interrupt
Return values:
None

Definition at line 479 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), and HAL_QSPI_IRQHandler().

#define __HAL_QSPI_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)

Enable the QSPI peripheral.

Parameters:
__HANDLE__,: specifies the QSPI Handle.
Return values:
None

Definition at line 446 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define __HAL_QSPI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))

Enable the specified QSPI interrupt.

Parameters:
__HANDLE__,: specifies the QSPI Handle.
__INTERRUPT__,: specifies the QSPI interrupt source to enable. This parameter can be one of the following values:
  • QSPI_IT_TO: QSPI Timeout interrupt
  • QSPI_IT_SM: QSPI Status match interrupt
  • QSPI_IT_FT: QSPI FIFO threshold interrupt
  • QSPI_IT_TC: QSPI Transfer complete interrupt
  • QSPI_IT_TE: QSPI Transfer error interrupt
Return values:
None

Definition at line 465 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), QSPI_DMAAbortCplt(), QSPI_DMARxCplt(), and QSPI_DMATxCplt().

#define __HAL_QSPI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)

Check whether the selected QSPI flag is set or not.

Parameters:
__HANDLE__,: specifies the QSPI Handle.
__FLAG__,: specifies the QSPI flag to check. This parameter can be one of the following values:
  • QSPI_FLAG_BUSY: QSPI Busy flag
  • QSPI_FLAG_TO: QSPI Timeout flag
  • QSPI_FLAG_SM: QSPI Status match flag
  • QSPI_FLAG_FT: QSPI FIFO threshold flag
  • QSPI_FLAG_TC: QSPI Transfer complete flag
  • QSPI_FLAG_TE: QSPI Transfer error flag
Return values:
None

Definition at line 507 of file stm32h7xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), and QSPI_WaitFlagStateUntilTimeout().

#define __HAL_QSPI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified QSPI interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the QSPI Handle.
__INTERRUPT__,: specifies the QSPI interrupt source to check. This parameter can be one of the following values:
  • QSPI_IT_TO: QSPI Timeout interrupt
  • QSPI_IT_SM: QSPI Status match interrupt
  • QSPI_IT_FT: QSPI FIFO threshold interrupt
  • QSPI_IT_TC: QSPI Transfer complete interrupt
  • QSPI_IT_TE: QSPI Transfer error interrupt
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 492 of file stm32h7xx_hal_qspi.h.

#define __HAL_QSPI_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)

Reset QSPI handle state.

Parameters:
__HANDLE__,: QSPI handle.
Return values:
None

Definition at line 440 of file stm32h7xx_hal_qspi.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC Private macros to check input parameters

Defines
RCC Private macros to check input parameters
RCC Private Macros

Defines

#define | IS_RCC_OSCILLATORTYPE(OSCILLATOR)
#define | IS_RCC_HSE(HSE)
#define | IS_RCC_LSE(LSE)
#define | IS_RCC_HSI(HSI)
#define | IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
#define | IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
#define | IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON))
#define | IS_RCC_PLL(PLL)
#define | IS_RCC_PLLSOURCE(SOURCE)
#define | IS_RCC_PLLM_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 63))
#define | IS_RCC_PLLN_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512))
#define | IS_RCC_PLLP_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
#define | IS_RCC_PLLQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
#define | IS_RCC_PLLR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
#define | IS_RCC_PLLCLOCKOUT_VALUE(VALUE)
#define | IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 0x3F))
#define | IS_RCC_SYSCLKSOURCE(SOURCE)
#define | IS_RCC_SYSCLK(SYSCLK)
#define | IS_RCC_HCLK(HCLK)
#define | IS_RCC_D1PCLK1(D1PCLK1)
#define | IS_RCC_PCLK1(PCLK1)
#define | IS_RCC_PCLK2(PCLK2)
#define | IS_RCC_D3PCLK1(D3PCLK1)
#define | IS_RCC_RTCCLKSOURCE(SOURCE)
#define | IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
#define | IS_RCC_MCO1SOURCE(SOURCE)
#define | IS_RCC_MCO2SOURCE(SOURCE)
#define | IS_RCC_MCODIV(DIV)
#define | IS_RCC_FLAG(FLAG)
#define | IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0xFFF)
#define | IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
#define | IS_RCC_STOP_WAKEUPCLOCK(SOURCE)
#define | IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE)

Define Documentation

#define IS_RCC_CALIBRATION_VALUE ( VALUE ) ((VALUE) <= 0xFFF)

Definition at line 3035 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_CLOCKTYPE ( CLK ) ((1 <= (CLK)) && ((CLK) <= 0x3F))

Definition at line 2932 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_CSI ( CSI ) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON))

Definition at line 2913 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_CSICALIBRATION_VALUE ( VALUE ) ((VALUE) <= 0x1F)

Definition at line 3036 of file stm32h7xx_hal_rcc.h.

#define IS_RCC_D1PCLK1 ( D1PCLK1 )
Value:
(((D1PCLK1) == RCC_APB3_DIV1) || ((D1PCLK1) == RCC_APB3_DIV2) || \
                                 ((D1PCLK1) == RCC_APB3_DIV4) || ((D1PCLK1) == RCC_APB3_DIV8) || \
                                 ((D1PCLK1) == RCC_APB3_DIV16))

Definition at line 2952 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_D3PCLK1 ( D3PCLK1 )
Value:
(((D3PCLK1) == RCC_APB4_DIV1) || ((D3PCLK1) == RCC_APB4_DIV2) || \
                                 ((D3PCLK1) == RCC_APB4_DIV4) || ((D3PCLK1) == RCC_APB4_DIV8) || \
                                 ((D3PCLK1) == RCC_APB4_DIV16))

Definition at line 2964 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_FLAG ( FLAG )
Value:
(((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \
                           ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
                           ((FLAG) == RCC_FLAG_D1CKRDY)   || ((FLAG) == RCC_FLAG_D2CKRDY) || \
                           ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \
                           ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \
                           ((FLAG) == RCC_FLAG_LSIRDY)    || ((FLAG) == RCC_FLAG_RMVF)    || \
                           ((FLAG) == RCC_FLAG_CPURST)    || ((FLAG) == RCC_FLAG_D1RST)   || \
                           ((FLAG) == RCC_FLAG_D2RST)     || ((FLAG) == RCC_FLAG_BORRST)  || \
                           ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \
                           ((FLAG) == RCC_FLAG_SFTRST)    || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
                           ((FLAG) == RCC_FLAG_WWDGR1ST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
                           ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV ))

Definition at line 3021 of file stm32h7xx_hal_rcc.h.

#define IS_RCC_HCLK ( HCLK )
Value:
(((HCLK) == RCC_HCLK_DIV1)   || ((HCLK) == RCC_HCLK_DIV2)   || \
                           ((HCLK) == RCC_HCLK_DIV4)   || ((HCLK) == RCC_HCLK_DIV8)   || \
                           ((HCLK) == RCC_HCLK_DIV16)  || ((HCLK) == RCC_HCLK_DIV64)  || \
                           ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \
                           ((HCLK) == RCC_HCLK_DIV512))

Definition at line 2946 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_HSE ( HSE )
Value:
(((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
                         ((HSE) == RCC_HSE_BYPASS))

Definition at line 2899 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_HSI ( HSI )
Value:
(((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)    || \
                         ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \
                         ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8))

Definition at line 2905 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_HSI48 ( HSI48 ) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))

Definition at line 2909 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_LSE ( LSE )
Value:
(((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
                         ((LSE) == RCC_LSE_BYPASS))

Definition at line 2902 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_LSI ( LSI ) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))

Definition at line 2911 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_MCO ( MCOx ) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))

Definition at line 3001 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCO1SOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE)       || \
                                   ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK)  || \
                                   ((SOURCE) == RCC_MCO1SOURCE_HSI48))

Definition at line 3003 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCO2SOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_MCO2SOURCE_SYSCLK)    || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \
                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)       || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)   || \
                                   ((SOURCE) == RCC_MCO2SOURCE_CSICLK)    || ((SOURCE) == RCC_MCO2SOURCE_LSICLK))

Definition at line 3007 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCODIV ( DIV )
Value:
(((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2)   || \
                            ((DIV) == RCC_MCODIV_3)  || ((DIV) == RCC_MCODIV_4)   || \
                            ((DIV) == RCC_MCODIV_5)  || ((DIV) == RCC_MCODIV_6)   || \
                            ((DIV) == RCC_MCODIV_7)  || ((DIV) == RCC_MCODIV_8)   || \
                            ((DIV) == RCC_MCODIV_9)  || ((DIV) == RCC_MCODIV_10)  || \
                            ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12)  || \
                            ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14)  || \
                            ((DIV) == RCC_MCODIV_15))

Definition at line 3011 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_OSCILLATORTYPE ( OSCILLATOR )
Value:
(((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE)                           || \
                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \
                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))

Definition at line 2891 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PCLK1 ( PCLK1 )
Value:
(((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \
                             ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \
                            ((PCLK1) == RCC_APB1_DIV16))

Definition at line 2956 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_PCLK2 ( PCLK2 )
Value:
(((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \
                             ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \
                             ((PCLK2) == RCC_APB2_DIV16))

Definition at line 2960 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_PLL ( PLL )
Value:
(((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \
                         ((PLL) == RCC_PLL_ON))

Definition at line 2915 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLCLOCKOUT_VALUE ( VALUE )
Value:
(((VALUE) == RCC_PLL1_DIVP) || \
                                         ((VALUE) == RCC_PLL1_DIVQ) || \
                                         ((VALUE) == RCC_PLL1_DIVR))

Definition at line 2928 of file stm32h7xx_hal_rcc.h.

#define IS_RCC_PLLM_VALUE ( VALUE ) ((1 <= (VALUE)) && ((VALUE) <= 63))

Definition at line 2922 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLN_VALUE ( VALUE ) ((4 <= (VALUE)) && ((VALUE) <= 512))

Definition at line 2923 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLP_VALUE ( VALUE ) ((1 <= (VALUE)) && ((VALUE) <= 128))

Definition at line 2924 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLQ_VALUE ( VALUE ) ((1 <= (VALUE)) && ((VALUE) <= 128))

Definition at line 2925 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLR_VALUE ( VALUE ) ((1 <= (VALUE)) && ((VALUE) <= 128))

Definition at line 2926 of file stm32h7xx_hal_rcc.h.

#define IS_RCC_PLLSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_PLLSOURCE_CSI)  || \
                                  ((SOURCE) == RCC_PLLSOURCE_HSI)  || \
                                  ((SOURCE) == RCC_PLLSOURCE_NONE) || \
                                  ((SOURCE) == RCC_PLLSOURCE_HSE))

Definition at line 2918 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_RTCCLKSOURCE ( SOURCE )

Definition at line 2968 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_STOP_KERWAKEUPCLOCK ( SOURCE )
Value:
(((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \
                                          ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI))

Definition at line 3041 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_KerWakeUpStopCLKConfig().

#define IS_RCC_STOP_WAKEUPCLOCK ( SOURCE )
Value:
(((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \
                                         ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI))

Definition at line 3038 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_WakeUpStopCLKConfig().

#define IS_RCC_SYSCLK ( SYSCLK )
Value:
(((SYSCLK) == RCC_SYSCLK_DIV1)   || ((SYSCLK) == RCC_SYSCLK_DIV2)   || \
                               ((SYSCLK) == RCC_SYSCLK_DIV4)   || ((SYSCLK) == RCC_SYSCLK_DIV8)   || \
                               ((SYSCLK) == RCC_SYSCLK_DIV16)  || ((SYSCLK) == RCC_SYSCLK_DIV64)  || \
                               ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \
                               ((SYSCLK) == RCC_SYSCLK_DIV512))

Definition at line 2939 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_SYSCLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \
                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))

Definition at line 2934 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC Private Macros

Modules | Defines
RCC Private Macros
RCC

Modules

RCC Private macros to check input parameters

Defines

#define | __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO1_GPIO_PORT GPIOA
#define | MCO1_PIN GPIO_PIN_8
#define | __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define | MCO2_GPIO_PORT GPIOC
#define | MCO2_PIN GPIO_PIN_9

Define Documentation

#define __MCO1_CLK_ENABLE ( ) __HAL_RCC_GPIOA_CLK_ENABLE()

Definition at line 106 of file stm32h7xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define __MCO2_CLK_ENABLE ( ) __HAL_RCC_GPIOC_CLK_ENABLE()

Definition at line 110 of file stm32h7xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO1_GPIO_PORT GPIOA

Definition at line 107 of file stm32h7xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO1_PIN GPIO_PIN_8

Definition at line 108 of file stm32h7xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO2_GPIO_PORT GPIOC

Definition at line 111 of file stm32h7xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO2_PIN GPIO_PIN_9

Definition at line 112 of file stm32h7xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC Private Variables

RCC Private Variables
RCC
Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RCC Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
__weak HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initializes the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
           ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]
      This section provides functions allowing to configure the internal/external oscillators
      (HSE, HSI, LSE,CSI, LSI,HSI48, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB3, AHB1
       AHB2,AHB4,APB3, APB1L, APB1H, APB2, and APB4).

    [..] Internal/external clock and PLL configuration
         (#) HSI (high-speed internal), 64 MHz factory-trimmed RC used directly or through
             the PLL as System clock source.
         (#) CSI is a low-power RC oscillator which can be used directly as system clock, peripheral
             clock, or PLL input.But even with frequency calibration, is less accurate than an
             external crystal oscillator or ceramic resonator.
         (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
             clock source.

         (#) HSE (high-speed external), 4 to 48 MHz crystal oscillator used directly or
             through the PLL as System clock source. Can be used also as RTC clock source.

         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.

         (#) PLL , The RCC features three independent PLLs (clocked by HSI , HSE or CSI),
             featuring three different output clocks and able  to work either in integer or Fractional mode.
           (++) A main PLL, PLL1, which is generally used to provide clocks to the CPU
                and to some peripherals.
           (++) Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for peripherals.

         (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
            (HSE used directly or through PLL as System clock source), the System clock
             is automatically switched to HSI and an interrupt is generated if enabled.
             The interrupt is linked to the Cortex-M NMI (Non-Mask-able Interrupt)
             exception vector.

         (#) MCO1 (micro controller clock output), used to output HSI, LSE, HSE, PLL1(PLL1_Q)
             or HSI48 clock (through a configurable pre-scaler) on PA8 pin.

         (#) MCO2 (micro controller clock output), used to output HSE, PLL2(PLL2_P), SYSCLK,
             LSI, CSI, or PLL1(PLL1_P) clock (through a configurable pre-scaler) on PC9 pin.

    [..] System, AHB and APB buses clocks configuration
         (#) Several clock sources can be used to drive the System clock (SYSCLK): CSI,HSI,
             HSE and PLL.
             The AHB clock (HCLK) is derived from System core clock through configurable
             pre-scaler and used to clock the CPU, memory and peripherals mapped
             on AHB and APB bus of the 3 Domains (D1, D2, D3) through configurable pre-scalers
             and used to clock the peripherals mapped on these buses. You can use
             "HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency.

         -@- All the peripheral clocks are derived from the System clock (SYSCLK) except those
             with dual clock domain where kernel source clock could be selected through
             RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R and RCC_D3CCIPR registers.

Function Documentation

HAL_StatusTypeDef HAL_RCC_ClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t | FLatency
 | ) |  |

Initializes the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.

Parameters:
RCC_ClkInitStruct,: pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC peripheral.
FLatency,: FLASH Latency, this parameter depend on device selected
Note:
The SystemCoreClock CMSIS variable is used to store System Clock Frequency and updated by HAL_InitTick() function called within this function
The HSI is used (enabled by hardware) as system clock source after start-up from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
A switch from one clock source to another occurs only if the target clock source is ready (clock stable after start-up delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use HAL_RCC_GetClockConfig() function to know which clock is currently used as system clock source.
Depending on the device voltage range, the software has to set correctly D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency (for more details refer to section above "Initialization/de-initialization functions")
Return values:
None

Definition at line 736 of file stm32h7xx_hal_rcc.c.

References __HAL_FLASH_SET_LATENCY, __HAL_RCC_GET_FLAG, __HAL_RCC_GET_SYSCLK_SOURCE, RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, RCC_ClkInitTypeDef::APB2CLKDivider, RCC_ClkInitTypeDef::APB3CLKDivider, RCC_ClkInitTypeDef::APB4CLKDivider, assert_param, CLOCKSWITCH_TIMEOUT_VALUE, RCC_ClkInitTypeDef::ClockType, HAL_GetTick(), HAL_InitTick(), HAL_RCC_GetSysClockFreq(), IS_FLASH_LATENCY, IS_RCC_CLOCKTYPE, IS_RCC_D1PCLK1, IS_RCC_D3PCLK1, IS_RCC_HCLK, IS_RCC_PCLK1, IS_RCC_PCLK2, IS_RCC_SYSCLK, IS_RCC_SYSCLKSOURCE, RCC_CLOCKTYPE_D1PCLK1, RCC_CLOCKTYPE_D3PCLK1, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_PCLK2, RCC_CLOCKTYPE_SYSCLK, RCC_FLAG_CSIRDY, RCC_FLAG_HSERDY, RCC_FLAG_HSIRDY, RCC_FLAG_PLLRDY, RCC_SYSCLKSOURCE_CSI, RCC_SYSCLKSOURCE_HSE, RCC_SYSCLKSOURCE_PLLCLK, RCC_ClkInitTypeDef::SYSCLKDivider, RCC_ClkInitTypeDef::SYSCLKSource, and TICK_INT_PRIORITY.

void HAL_RCC_DeInit ( void )

Resets the RCC clock configuration to the default reset state.

Note:
The default reset state of the clock configuration is given below:
  • HSI ON and used as system clock source
  • HSE, PLL1, PLL2 and PLL3 OFF
  • AHB, APB Bus pre-scaler set to 1.
  • CSS, MCO1 and MCO2 OFF
  • All interrupts disabled
This function doesn't modify the configuration of the
  • Peripheral clocks
  • LSI, LSE and RTC clocks
Return values:
None

Definition at line 206 of file stm32h7xx_hal_rcc.c.

HAL_StatusTypeDef HAL_RCC_OscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.

Parameters:
RCC_OscInitStruct,: pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC Oscillators.
Note:
The PLL is not disabled when used as system clock.
Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this function. User should request a transition to LSE Off first and then LSE On or LSE Bypass.
Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this function. User should request a transition to HSE Off first and then HSE On or HSE Bypass.
Return values:
HAL status

Definition at line 272 of file stm32h7xx_hal_rcc.c.

References __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST, __HAL_RCC_CSI_DISABLE, __HAL_RCC_CSI_ENABLE, __HAL_RCC_GET_FLAG, __HAL_RCC_GET_SYSCLK_SOURCE, __HAL_RCC_HSE_CONFIG, __HAL_RCC_HSI48_DISABLE, __HAL_RCC_HSI48_ENABLE, __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST, __HAL_RCC_HSI_CONFIG, __HAL_RCC_HSI_DISABLE, __HAL_RCC_LSE_CONFIG, __HAL_RCC_LSI_DISABLE, __HAL_RCC_LSI_ENABLE, __HAL_RCC_PLL_CONFIG, __HAL_RCC_PLL_DISABLE, __HAL_RCC_PLL_ENABLE, __HAL_RCC_PLL_VCIRANGE, __HAL_RCC_PLL_VCORANGE, __HAL_RCC_PLLCLKOUT_ENABLE, __HAL_RCC_PLLFRACN_CONFIG, __HAL_RCC_PLLFRACN_ENABLE, assert_param, CSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::CSICalibrationValue, RCC_OscInitTypeDef::CSIState, HAL_GetTick(), HSE_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSEState, HSI48_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSI48State, HSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, IS_RCC_CALIBRATION_VALUE, IS_RCC_CSI, IS_RCC_HSE, IS_RCC_HSI, IS_RCC_HSI48, IS_RCC_LSE, IS_RCC_LSI, IS_RCC_OSCILLATORTYPE, IS_RCC_PLL, IS_RCC_PLLM_VALUE, IS_RCC_PLLN_VALUE, IS_RCC_PLLP_VALUE, IS_RCC_PLLQ_VALUE, IS_RCC_PLLSOURCE, RCC_OscInitTypeDef::LSEState, LSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, PLL_TIMEOUT_VALUE, RCC_PLLInitTypeDef::PLLFRACN, RCC_PLLInitTypeDef::PLLM, RCC_PLLInitTypeDef::PLLN, RCC_PLLInitTypeDef::PLLP, RCC_PLLInitTypeDef::PLLQ, RCC_PLLInitTypeDef::PLLR, RCC_PLLInitTypeDef::PLLRGE, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_PLLInitTypeDef::PLLVCOSEL, RCC_CSI_OFF, RCC_CSI_ON, RCC_DBP_TIMEOUT_VALUE, RCC_FLAG_CSIRDY, RCC_FLAG_HSERDY, RCC_FLAG_HSI48RDY, RCC_FLAG_HSIRDY, RCC_FLAG_LSERDY, RCC_FLAG_LSIRDY, RCC_FLAG_PLLRDY, RCC_HSE_OFF, RCC_HSI48_OFF, RCC_HSI_OFF, RCC_LSE_ON, RCC_LSE_TIMEOUT_VALUE, RCC_LSI_OFF, RCC_OSCILLATORTYPE_CSI, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_HSI48, RCC_OSCILLATORTYPE_LSE, RCC_OSCILLATORTYPE_LSI, RCC_PLL1_DIVP, RCC_PLL1_DIVQ, RCC_PLL1_DIVR, RCC_PLL_NONE, and RCC_PLL_ON.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RCC Exported Functions

RCC clocks control functions. More...

Functions

void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
void | HAL_RCC_EnableCSS (void)
Enables the Clock Security System.
uint32_t | HAL_RCC_GetSysClockFreq (void)
Returns the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Returns the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Returns the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Returns the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
This function handles the RCC CSS interrupt request.
__weak void | HAL_RCC_CCSCallback (void)
RCC Clock Security System interrupt callback.

Detailed Description

RCC clocks control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the RCC Clocks
    frequencies.

Function Documentation

__weak void HAL_RCC_CCSCallback ( void )

RCC Clock Security System interrupt callback.

Return values:
none

Definition at line 1334 of file stm32h7xx_hal_rcc.c.

Referenced by HAL_RCC_NMI_IRQHandler().

void HAL_RCC_EnableCSS ( void )

Enables the Clock Security System.

Note:
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M NMI (Non-Mask-able Interrupt) exception vector.
Return values:
None

Definition at line 1008 of file stm32h7xx_hal_rcc.c.

void HAL_RCC_GetClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t * | pFLatency
 | ) |  |

Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_ClkInitStruct,: pointer to an RCC_ClkInitTypeDef structure that will be configured.
pFLatency,: Pointer on the Flash Latency.
Return values:
None

Definition at line 1280 of file stm32h7xx_hal_rcc.c.

References RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, RCC_ClkInitTypeDef::APB2CLKDivider, RCC_ClkInitTypeDef::APB3CLKDivider, RCC_ClkInitTypeDef::APB4CLKDivider, RCC_ClkInitTypeDef::ClockType, RCC_CLOCKTYPE_D1PCLK1, RCC_CLOCKTYPE_D3PCLK1, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_PCLK2, RCC_CLOCKTYPE_SYSCLK, RCC_ClkInitTypeDef::SYSCLKDivider, and RCC_ClkInitTypeDef::SYSCLKSource.

uint32_t HAL_RCC_GetHCLKFreq ( void )

Returns the HCLK frequency.

Note:
Each time HCLK changes, this function must be called to update the right HCLK value. Otherwise, any configuration based on this function will be incorrect.
The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency and updated within this function
Return values:
HCLK frequency

Definition at line 1136 of file stm32h7xx_hal_rcc.c.

References HAL_RCCEx_GetD1SysClockFreq().

Referenced by ETH_MAC_MDIO_ClkConfig(), HAL_ETH_Init(), HAL_ETH_SetMDIOClockRange(), HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCCEx_GetD1PCLK1Freq(), and HAL_RCCEx_GetD3PCLK1Freq().

void HAL_RCC_GetOscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Configures the RCC_OscInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_OscInitStruct,: pointer to an RCC_OscInitTypeDef structure that will be configured.
Return values:
None

Definition at line 1175 of file stm32h7xx_hal_rcc.c.

References RCC_OscInitTypeDef::CSICalibrationValue, RCC_OscInitTypeDef::CSIState, RCC_OscInitTypeDef::HSEState, RCC_OscInitTypeDef::HSI48State, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, RCC_OscInitTypeDef::LSEState, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, RCC_PLLInitTypeDef::PLLM, RCC_PLLInitTypeDef::PLLN, RCC_PLLInitTypeDef::PLLP, RCC_PLLInitTypeDef::PLLQ, RCC_PLLInitTypeDef::PLLR, RCC_PLLInitTypeDef::PLLRGE, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_PLLInitTypeDef::PLLVCOSEL, RCC_CSI_OFF, RCC_CSI_ON, RCC_HSE_BYPASS, RCC_HSE_OFF, RCC_HSE_ON, RCC_HSI48_OFF, RCC_HSI48_ON, RCC_HSI_OFF, RCC_HSI_ON, RCC_LSE_BYPASS, RCC_LSE_OFF, RCC_LSE_ON, RCC_LSI_OFF, RCC_LSI_ON, RCC_OSCILLATORTYPE_CSI, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_HSI48, RCC_OSCILLATORTYPE_LSI, RCC_PLL_OFF, and RCC_PLL_ON.

uint32_t HAL_RCC_GetPCLK1Freq ( void )

Returns the PCLK1 frequency.

Note:
Each time PCLK1 changes, this function must be called to update the right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK1 frequency

Definition at line 1149 of file stm32h7xx_hal_rcc.c.

References HAL_RCC_GetHCLKFreq().

Referenced by IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetPCLK2Freq ( void )

Returns the PCLK2 frequency.

Note:
Each time PCLK2 changes, this function must be called to update the right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK1 frequency

Definition at line 1162 of file stm32h7xx_hal_rcc.c.

References HAL_RCC_GetHCLKFreq().

Referenced by IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetSysClockFreq ( void )

Returns the SYSCLK frequency.

Note:
The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
If SYSCLK source is CSI, function returns values based on CSI_VALUE(*)
If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
If SYSCLK source is PLL, function returns values based on CSI_VALUE(*), HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
(*) CSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value 4 MHz) but the real value may vary depending on the variations in voltage and temperature.
(**) HSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value 64 MHz) but the real value may vary depending on the variations in voltage and temperature.
(***) HSE_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value 25 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
The result of this function could be not correct when using fractional value for HSE crystal.
This function can be used by the user application to compute the baud rate for the communication peripherals or configure other parameters.
Each time SYSCLK changes, this function must be called to update the right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
Return values:
SYSCLK frequency

Definition at line 1047 of file stm32h7xx_hal_rcc.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_HSI_DIVIDER, CSI_VALUE, HSE_VALUE, HSI_VALUE, and RCC_FLAG_HSIDIV.

Referenced by HAL_RCC_ClockConfig(), HAL_RCCEx_GetD1SysClockFreq(), and IRDA_SetConfig().

void HAL_RCC_MCOConfig | ( | uint32_t | RCC_MCOx,
 |  | uint32_t | RCC_MCOSource,
 |  | uint32_t | RCC_MCODiv
 | ) |  |

Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).

Note:
PA8/PC9 should be configured in alternate function mode.
Parameters:
RCC_MCOx,: specifies the output direction for the clock source. This parameter can be one of the following values:
  • RCC_MCO1: Clock source to output on MCO1 pin(PA8).
  • RCC_MCO2: Clock source to output on MCO2 pin(PC9).
RCC_MCOSource,: specifies the clock source to output. This parameter can be one of the following values:
  • RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
  • RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
  • RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
  • RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source
  • RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source
  • RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
  • RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source
  • RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
  • RCC_MCO2SOURCE_PLLCLK: PLL1P clock selected as MCO2 source
  • RCC_MCO2SOURCE_CSICLK: CSI clock selected as MCO2 source
  • RCC_MCO2SOURCE_LSICLK: LSI clock selected as MCO2 source
RCC_MCODiv,: specifies the MCOx pre-scaler. This parameter can be one of the following values:
  • RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCOx clock
Return values:
None

Definition at line 954 of file stm32h7xx_hal_rcc.c.

References __MCO1_CLK_ENABLE, __MCO2_CLK_ENABLE, GPIO_InitTypeDef::Alternate, assert_param, GPIO_AF0_MCO, GPIO_MODE_AF_PP, GPIO_NOPULL, GPIO_SPEED_FREQ_VERY_HIGH, HAL_GPIO_Init(), IS_RCC_MCO, IS_RCC_MCO1SOURCE, IS_RCC_MCO2SOURCE, IS_RCC_MCODIV, MCO1_GPIO_PORT, MCO1_PIN, MCO2_GPIO_PORT, MCO2_PIN, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, RCC_MCO1, and GPIO_InitTypeDef::Speed.

void HAL_RCC_NMI_IRQHandler ( void )

This function handles the RCC CSS interrupt request.

Note:
This API should be called under the NMI_Handler().
Return values:
None

Definition at line 1317 of file stm32h7xx_hal_rcc.c.

References __HAL_RCC_CLEAR_IT, __HAL_RCC_GET_IT, HAL_RCC_CCSCallback(), and RCC_IT_CSS.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC_Exported_Functions_Group2

Functions
RCC_Exported_Functions_Group2
RCC Exported Functions

Functions

void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
void | HAL_RCC_EnableCSS (void)
Enables the Clock Security System.
void | HAL_RCC_DisableCSS (void)
uint32_t | HAL_RCC_GetSysClockFreq (void)
Returns the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Returns the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Returns the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Returns the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
This function handles the RCC CSS interrupt request.
void | HAL_RCC_CCSCallback (void)
RCC Clock Security System interrupt callback.

Function Documentation

void HAL_RCC_CCSCallback ( void )

RCC Clock Security System interrupt callback.

Return values:
none

Definition at line 1334 of file stm32h7xx_hal_rcc.c.

Referenced by HAL_RCC_NMI_IRQHandler().

void HAL_RCC_DisableCSS ( void )
void HAL_RCC_EnableCSS ( void )

Enables the Clock Security System.

Note:
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M NMI (Non-Mask-able Interrupt) exception vector.
Return values:
None

Definition at line 1008 of file stm32h7xx_hal_rcc.c.

void HAL_RCC_GetClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t * | pFLatency
 | ) |  |

Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_ClkInitStruct,: pointer to an RCC_ClkInitTypeDef structure that will be configured.
pFLatency,: Pointer on the Flash Latency.
Return values:
None

Definition at line 1280 of file stm32h7xx_hal_rcc.c.

References RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, RCC_ClkInitTypeDef::APB2CLKDivider, RCC_ClkInitTypeDef::APB3CLKDivider, RCC_ClkInitTypeDef::APB4CLKDivider, RCC_ClkInitTypeDef::ClockType, RCC_CLOCKTYPE_D1PCLK1, RCC_CLOCKTYPE_D3PCLK1, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_PCLK2, RCC_CLOCKTYPE_SYSCLK, RCC_ClkInitTypeDef::SYSCLKDivider, and RCC_ClkInitTypeDef::SYSCLKSource.

uint32_t HAL_RCC_GetHCLKFreq ( void )

Returns the HCLK frequency.

Note:
Each time HCLK changes, this function must be called to update the right HCLK value. Otherwise, any configuration based on this function will be incorrect.
The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency and updated within this function
Return values:
HCLK frequency

Definition at line 1136 of file stm32h7xx_hal_rcc.c.

References HAL_RCCEx_GetD1SysClockFreq().

Referenced by ETH_MAC_MDIO_ClkConfig(), HAL_ETH_Init(), HAL_ETH_SetMDIOClockRange(), HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCCEx_GetD1PCLK1Freq(), and HAL_RCCEx_GetD3PCLK1Freq().

void HAL_RCC_GetOscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Configures the RCC_OscInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_OscInitStruct,: pointer to an RCC_OscInitTypeDef structure that will be configured.
Return values:
None

Definition at line 1175 of file stm32h7xx_hal_rcc.c.

References RCC_OscInitTypeDef::CSICalibrationValue, RCC_OscInitTypeDef::CSIState, RCC_OscInitTypeDef::HSEState, RCC_OscInitTypeDef::HSI48State, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, RCC_OscInitTypeDef::LSEState, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, RCC_PLLInitTypeDef::PLLM, RCC_PLLInitTypeDef::PLLN, RCC_PLLInitTypeDef::PLLP, RCC_PLLInitTypeDef::PLLQ, RCC_PLLInitTypeDef::PLLR, RCC_PLLInitTypeDef::PLLRGE, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_PLLInitTypeDef::PLLVCOSEL, RCC_CSI_OFF, RCC_CSI_ON, RCC_HSE_BYPASS, RCC_HSE_OFF, RCC_HSE_ON, RCC_HSI48_OFF, RCC_HSI48_ON, RCC_HSI_OFF, RCC_HSI_ON, RCC_LSE_BYPASS, RCC_LSE_OFF, RCC_LSE_ON, RCC_LSI_OFF, RCC_LSI_ON, RCC_OSCILLATORTYPE_CSI, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_HSI48, RCC_OSCILLATORTYPE_LSI, RCC_PLL_OFF, and RCC_PLL_ON.

uint32_t HAL_RCC_GetPCLK1Freq ( void )

Returns the PCLK1 frequency.

Note:
Each time PCLK1 changes, this function must be called to update the right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK1 frequency

Definition at line 1149 of file stm32h7xx_hal_rcc.c.

References HAL_RCC_GetHCLKFreq().

Referenced by IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetPCLK2Freq ( void )

Returns the PCLK2 frequency.

Note:
Each time PCLK2 changes, this function must be called to update the right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK1 frequency

Definition at line 1162 of file stm32h7xx_hal_rcc.c.

References HAL_RCC_GetHCLKFreq().

Referenced by IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetSysClockFreq ( void )

Returns the SYSCLK frequency.

Note:
The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
If SYSCLK source is CSI, function returns values based on CSI_VALUE(*)
If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
If SYSCLK source is PLL, function returns values based on CSI_VALUE(*), HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
(*) CSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value 4 MHz) but the real value may vary depending on the variations in voltage and temperature.
(**) HSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value 64 MHz) but the real value may vary depending on the variations in voltage and temperature.
(***) HSE_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value 25 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
The result of this function could be not correct when using fractional value for HSE crystal.
This function can be used by the user application to compute the baud rate for the communication peripherals or configure other parameters.
Each time SYSCLK changes, this function must be called to update the right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
Return values:
SYSCLK frequency

Definition at line 1047 of file stm32h7xx_hal_rcc.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_HSI_DIVIDER, CSI_VALUE, HSE_VALUE, HSI_VALUE, and RCC_FLAG_HSIDIV.

Referenced by HAL_RCC_ClockConfig(), HAL_RCCEx_GetD1SysClockFreq(), and IRDA_SetConfig().

void HAL_RCC_MCOConfig | ( | uint32_t | RCC_MCOx,
 |  | uint32_t | RCC_MCOSource,
 |  | uint32_t | RCC_MCODiv
 | ) |  |

Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).

Note:
PA8/PC9 should be configured in alternate function mode.
Parameters:
RCC_MCOx,: specifies the output direction for the clock source. This parameter can be one of the following values:
  • RCC_MCO1: Clock source to output on MCO1 pin(PA8).
  • RCC_MCO2: Clock source to output on MCO2 pin(PC9).
RCC_MCOSource,: specifies the clock source to output. This parameter can be one of the following values:
  • RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
  • RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
  • RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
  • RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source
  • RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source
  • RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
  • RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source
  • RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
  • RCC_MCO2SOURCE_PLLCLK: PLL1P clock selected as MCO2 source
  • RCC_MCO2SOURCE_CSICLK: CSI clock selected as MCO2 source
  • RCC_MCO2SOURCE_LSICLK: LSI clock selected as MCO2 source
RCC_MCODiv,: specifies the MCOx pre-scaler. This parameter can be one of the following values:
  • RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCOx clock
Return values:
None

Definition at line 954 of file stm32h7xx_hal_rcc.c.

References __MCO1_CLK_ENABLE, __MCO2_CLK_ENABLE, GPIO_InitTypeDef::Alternate, assert_param, GPIO_AF0_MCO, GPIO_MODE_AF_PP, GPIO_NOPULL, GPIO_SPEED_FREQ_VERY_HIGH, HAL_GPIO_Init(), IS_RCC_MCO, IS_RCC_MCO1SOURCE, IS_RCC_MCO2SOURCE, IS_RCC_MCODIV, MCO1_GPIO_PORT, MCO1_PIN, MCO2_GPIO_PORT, MCO2_PIN, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, RCC_MCO1, and GPIO_InitTypeDef::Speed.

void HAL_RCC_NMI_IRQHandler ( void )

This function handles the RCC CSS interrupt request.

Note:
This API should be called under the NMI_Handler().
Return values:
None

Definition at line 1317 of file stm32h7xx_hal_rcc.c.

References __HAL_RCC_CLEAR_IT, __HAL_RCC_GET_IT, HAL_RCC_CCSCallback(), and RCC_IT_CSS.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC_PLLInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PLLInitTypeDef Struct Reference
RCC Exported Types

RCC PLL configuration structure definition. More...

#include <stm32h7xx_hal_rcc.h>

Data Fields

uint32_t | PLLState
uint32_t | PLLSource
uint32_t | PLLM
uint32_t | PLLN
uint32_t | PLLP
uint32_t | PLLQ
uint32_t | PLLR
uint32_t | PLLRGE
uint32_t | PLLVCOSEL
uint32_t | PLLFRACN

Detailed Description

RCC PLL configuration structure definition.

Definition at line 66 of file stm32h7xx_hal_rcc.h.

Field Documentation

uint32_t RCC_PLLInitTypeDef::PLLFRACN

PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for PLL1 VCO It should be a value between 0 and 8191

Definition at line 94 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLM

PLLM: Division factor for PLL VCO input clock. This parameter must be a number between Min_Data = 1 and Max_Data = 63

Definition at line 74 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLN

PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 4 and Max_Data = 512

Definition at line 77 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLP

PLLP: Division factor for system clock. This parameter must be a number between Min_Data = 2 and Max_Data = 128 odd division factors are not allowed

Definition at line 80 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLQ

PLLQ: Division factor for peripheral clocks. This parameter must be a number between Min_Data = 1 and Max_Data = 128

Definition at line 84 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLR

PLLR: Division factor for peripheral clocks. This parameter must be a number between Min_Data = 1 and Max_Data = 128

Definition at line 87 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLRGE

PLLRGE: PLL1 clock Input range This parameter must be a value of RCC PLL1 VCI Range

Definition at line 89 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLSource

RCC_PLLSource: PLL entry clock source. This parameter must be a value of RCC PLL Clock Source

Definition at line 71 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLState

The new state of the PLL. This parameter can be a value of RCC PLL Config

Definition at line 68 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLVCOSEL

PLLVCOSEL: PLL1 clock Output range This parameter must be a value of RCC PLL1 VCO Range

Definition at line 91 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC_OscInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_OscInitTypeDef Struct Reference
RCC Exported Types

RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition. More...

#include <stm32h7xx_hal_rcc.h>

Data Fields

uint32_t | OscillatorType
uint32_t | HSEState
uint32_t | LSEState
uint32_t | HSIState
uint32_t | HSICalibrationValue
uint32_t | LSIState
uint32_t | HSI48State
uint32_t | CSIState
uint32_t | CSICalibrationValue
RCC_PLLInitTypeDef PLL

Detailed Description

RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition.

Definition at line 103 of file stm32h7xx_hal_rcc.h.

Field Documentation

uint32_t RCC_OscInitTypeDef::CSICalibrationValue

The calibration trimming value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F

Definition at line 129 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::CSIState

The new state of the CSI. This parameter can be a value of RCC CSI Config

Definition at line 126 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSEState

The new state of the HSE. This parameter can be a value of RCC HSE Config

Definition at line 108 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSI48State

The new state of the HSI48. This parameter can be a value of RCC HSI48 Config

Definition at line 123 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSICalibrationValue

The calibration trimming value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F

Definition at line 117 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSIState

The new state of the HSI. This parameter can be a value of RCC HSI Config

Definition at line 114 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::LSEState

The new state of the LSE. This parameter can be a value of RCC LSE Config

Definition at line 111 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::LSIState

The new state of the LSI. This parameter can be a value of RCC LSI Config

Definition at line 120 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::OscillatorType

The oscillators to be configured. This parameter can be a value of RCC Oscillator Type

Definition at line 105 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

RCC_PLLInitTypeDef RCC_OscInitTypeDef::PLL

PLL structure parameters

Definition at line 132 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC_ClkInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_ClkInitTypeDef Struct Reference
RCC Exported Types

RCC System, AHB and APB busses clock configuration structure definition. More...

#include <stm32h7xx_hal_rcc.h>

Data Fields

uint32_t | ClockType
uint32_t | SYSCLKSource
uint32_t | SYSCLKDivider
uint32_t | AHBCLKDivider
uint32_t | APB3CLKDivider
uint32_t | APB1CLKDivider
uint32_t | APB2CLKDivider
uint32_t | APB4CLKDivider

Detailed Description

RCC System, AHB and APB busses clock configuration structure definition.

Definition at line 139 of file stm32h7xx_hal_rcc.h.

Field Documentation

uint32_t RCC_ClkInitTypeDef::AHBCLKDivider

The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of RCC HCLK Clock Source

Definition at line 150 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB1CLKDivider

The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of RCC APB1 Clock Source

Definition at line 156 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB2CLKDivider

The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of RCC APB2 Clock Source

Definition at line 158 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB3CLKDivider

The APB3 clock (D1PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of RCC APB3 Clock Source

Definition at line 153 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB4CLKDivider

The APB4 clock (D3PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of RCC APB4 Clock Source

Definition at line 160 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::ClockType

The clock to be configured. This parameter can be a value of RCC System Clock Type

Definition at line 141 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::SYSCLKDivider

The system clock divider. This parameter can be a value of RCC SYS Clock Source

Definition at line 147 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::SYSCLKSource

The clock source (SYSCLKS) used as system clock. This parameter can be a value of RCC System Clock Source

Definition at line 144 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC Oscillator Type

Defines
RCC Oscillator Type
RCC Exported Constants

Defines

#define | RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
#define | RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
#define | RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
#define | RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
#define | RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
#define | RCC_OSCILLATORTYPE_CSI ((uint32_t)0x00000010)
#define | RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)

Define Documentation

#define RCC_OSCILLATORTYPE_CSI ((uint32_t)0x00000010)

Definition at line 182 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)

Definition at line 178 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)

Definition at line 179 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)

Definition at line 183 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)

Definition at line 180 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)

Definition at line 181 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)

Definition at line 177 of file stm32h7xx_hal_rcc.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC HSE Config

Defines
RCC HSE Config
RCC Exported Constants

Defines

#define | RCC_HSE_OFF ((uint32_t)0x00000000)
#define | RCC_HSE_ON RCC_CR_HSEON
#define | RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))

Define Documentation

#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))

Definition at line 194 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_HSE_OFF ((uint32_t)0x00000000)

Definition at line 192 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSE_ON RCC_CR_HSEON

Definition at line 193 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC LSE Config

Defines
RCC LSE Config
RCC Exported Constants

Defines

#define | RCC_LSE_OFF ((uint32_t)0x00000000)
#define | RCC_LSE_ON RCC_BDCR_LSEON
#define | RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))

Define Documentation

#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))

Definition at line 205 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_LSE_OFF ((uint32_t)0x00000000)

Definition at line 203 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_LSE_ON RCC_BDCR_LSEON

Definition at line 204 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC HSI Config

Defines
RCC HSI Config
RCC Exported Constants

Defines

#define | RCC_HSI_OFF ((uint32_t)0x00000000)
#define | RCC_HSI_ON RCC_CR_HSION
#define | RCC_HSI_DIV1 (RCC_CR_HSIDIV_1 | RCC_CR_HSION)
#define | RCC_HSI_DIV2 (RCC_CR_HSIDIV_2 | RCC_CR_HSION)
#define | RCC_HSI_DIV4 (RCC_CR_HSIDIV_4 | RCC_CR_HSION)
#define | RCC_HSI_DIV8 (RCC_CR_HSIDIV | RCC_CR_HSION)
#define | RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x20U) /* Default HSI calibration trimming value */

Define Documentation

#define RCC_HSI_DIV1 (RCC_CR_HSIDIV_1 | RCC_CR_HSION)

HSI_DIV1 clock activation

Definition at line 217 of file stm32h7xx_hal_rcc.h.

#define RCC_HSI_DIV2 (RCC_CR_HSIDIV_2 | RCC_CR_HSION)

HSI_DIV2 clock activation

Definition at line 218 of file stm32h7xx_hal_rcc.h.

#define RCC_HSI_DIV4 (RCC_CR_HSIDIV_4 | RCC_CR_HSION)

HSI_DIV4 clock activation

Definition at line 219 of file stm32h7xx_hal_rcc.h.

#define RCC_HSI_DIV8 (RCC_CR_HSIDIV | RCC_CR_HSION)

HSI_DIV8 clock activation

Definition at line 220 of file stm32h7xx_hal_rcc.h.

#define RCC_HSI_OFF ((uint32_t)0x00000000)

HSI clock deactivation

Definition at line 214 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSI_ON RCC_CR_HSION

HSI clock activation

Definition at line 215 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x20U) /* Default HSI calibration trimming value */

Definition at line 224 of file stm32h7xx_hal_rcc.h.

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC HSI48 Config

Defines
RCC HSI48 Config
RCC Exported Constants

Defines

#define | RCC_HSI48_OFF ((uint8_t)0x00)
#define | RCC_HSI48_ON ((uint8_t)0x01)

Define Documentation

#define RCC_HSI48_OFF ((uint8_t)0x00)

Definition at line 232 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSI48_ON ((uint8_t)0x01)

Definition at line 233 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Fri Apr 28 2017 15:42:49 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC LSI Config

Defines
RCC LSI Config
RCC Exported Constants

Defines

#define | RCC_LSI_OFF ((uint32_t)0x00000000)
#define | RCC_LSI_ON RCC_CSR_LSION

Define Documentation

#define RCC_LSI_OFF ((uint32_t)0x00000000)

Definition at line 242 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_LSI_ON RCC_CSR_LSION

Definition at line 243 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

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STM32H753xx HAL User Manual: RCC CSI Config

Defines
RCC CSI Config
RCC Exported Constants

Defines

#define | RCC_CSI_OFF ((uint32_t)0x00000000)
#define | RCC_CSI_ON RCC_CR_CSION
#define | RCC_CSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default CSI calibration trimming value */

Define Documentation

#define RCC_CSI_OFF ((uint32_t)0x00000000)

Definition at line 252 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_CSI_ON RCC_CR_CSION

Definition at line 253 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_CSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default CSI calibration trimming value */

Definition at line 255 of file stm32h7xx_hal_rcc.h.

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STM32H753xx HAL User Manual: RCC PLL Config

Defines
RCC PLL Config
RCC Exported Constants

Defines

#define | RCC_PLL_NONE ((uint32_t)0x00000000)
#define | RCC_PLL_OFF ((uint32_t)0x00000001)
#define | RCC_PLL_ON ((uint32_t)0x00000002)

Define Documentation

#define RCC_PLL_NONE ((uint32_t)0x00000000)

Definition at line 264 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_PLL_OFF ((uint32_t)0x00000001)

Definition at line 265 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_PLL_ON ((uint32_t)0x00000002)

Definition at line 266 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC PLL Clock Source

Defines
RCC PLL Clock Source
RCC Exported Constants

Defines

#define | RCC_PLLSOURCE_HSI ((uint32_t)0x00000000)
#define | RCC_PLLSOURCE_CSI ((uint32_t)0x00000001)
#define | RCC_PLLSOURCE_HSE ((uint32_t)0x00000002)
#define | RCC_PLLSOURCE_NONE ((uint32_t)0x00000003)

Define Documentation

#define RCC_PLLSOURCE_CSI ((uint32_t)0x00000001)

Definition at line 277 of file stm32h7xx_hal_rcc.h.

#define RCC_PLLSOURCE_HSE ((uint32_t)0x00000002)

Definition at line 278 of file stm32h7xx_hal_rcc.h.

#define RCC_PLLSOURCE_HSI ((uint32_t)0x00000000)

Definition at line 276 of file stm32h7xx_hal_rcc.h.

#define RCC_PLLSOURCE_NONE ((uint32_t)0x00000003)

Definition at line 279 of file stm32h7xx_hal_rcc.h.

Referenced by RCCEx_PLL2_Config(), and RCCEx_PLL3_Config().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC PLL Clock Output

Defines
RCC PLL Clock Output
RCC Exported Constants

Defines

#define | RCC_PLL1_DIVP RCC_PLLCFGR_DIVP1EN
#define | RCC_PLL1_DIVQ RCC_PLLCFGR_DIVQ1EN
#define | RCC_PLL1_DIVR RCC_PLLCFGR_DIVR1EN

Define Documentation

#define RCC_PLL1_DIVP RCC_PLLCFGR_DIVP1EN

Definition at line 287 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_PLL1_DIVQ RCC_PLLCFGR_DIVQ1EN

Definition at line 288 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PLL1_DIVR RCC_PLLCFGR_DIVR1EN

Definition at line 289 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC PLL1 VCI Range

Defines
RCC PLL1 VCI Range
RCC Exported Constants

Defines

#define | RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0
#define | RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1
#define | RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2
#define | RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3

Define Documentation

#define RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0

Definition at line 300 of file stm32h7xx_hal_rcc.h.

#define RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1

Definition at line 301 of file stm32h7xx_hal_rcc.h.

#define RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2

Definition at line 302 of file stm32h7xx_hal_rcc.h.

#define RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3

Definition at line 303 of file stm32h7xx_hal_rcc.h.

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STM32H753xx HAL User Manual: RCC PLL1 VCO Range

Defines
RCC PLL1 VCO Range
RCC Exported Constants

Defines

#define | RCC_PLL1VCOWIDE ((uint32_t)0x00000000)
#define | RCC_PLL1VCOMEDIUM RCC_PLLCFGR_PLL1VCOSEL

Define Documentation

#define RCC_PLL1VCOMEDIUM RCC_PLLCFGR_PLL1VCOSEL

Definition at line 315 of file stm32h7xx_hal_rcc.h.

#define RCC_PLL1VCOWIDE ((uint32_t)0x00000000)

Definition at line 314 of file stm32h7xx_hal_rcc.h.

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STM32H753xx HAL User Manual: RCC System Clock Type

Defines
RCC System Clock Type
RCC Exported Constants

Defines

#define | RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
#define | RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
#define | RCC_CLOCKTYPE_D1PCLK1 ((uint32_t)0x00000004)
#define | RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000008)
#define | RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000010)
#define | RCC_CLOCKTYPE_D3PCLK1 ((uint32_t)0x00000020)

Define Documentation

#define RCC_CLOCKTYPE_D1PCLK1 ((uint32_t)0x00000004)

Definition at line 327 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_D3PCLK1 ((uint32_t)0x00000020)

Definition at line 330 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)

Definition at line 326 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000008)

Definition at line 328 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000010)

Definition at line 329 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)

Definition at line 325 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC System Clock Source

Defines
RCC System Clock Source
RCC Exported Constants

Defines

#define | RCC_SYSCLKSOURCE_CSI RCC_CFGR_SW_CSI
#define | RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL1

Define Documentation

#define RCC_SYSCLKSOURCE_CSI RCC_CFGR_SW_CSI

Definition at line 339 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE

Definition at line 341 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI

Definition at line 340 of file stm32h7xx_hal_rcc.h.

#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL1

Definition at line 342 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC SYS Clock Source

Defines
RCC SYS Clock Source
RCC Exported Constants

Defines

#define | RCC_SYSCLK_DIV1 RCC_D1CFGR_D1CPRE_DIV1
#define | RCC_SYSCLK_DIV2 RCC_D1CFGR_D1CPRE_DIV2
#define | RCC_SYSCLK_DIV4 RCC_D1CFGR_D1CPRE_DIV4
#define | RCC_SYSCLK_DIV8 RCC_D1CFGR_D1CPRE_DIV8
#define | RCC_SYSCLK_DIV16 RCC_D1CFGR_D1CPRE_DIV16
#define | RCC_SYSCLK_DIV64 RCC_D1CFGR_D1CPRE_DIV64
#define | RCC_SYSCLK_DIV128 RCC_D1CFGR_D1CPRE_DIV128
#define | RCC_SYSCLK_DIV256 RCC_D1CFGR_D1CPRE_DIV256
#define | RCC_SYSCLK_DIV512 RCC_D1CFGR_D1CPRE_DIV512

Define Documentation

#define RCC_SYSCLK_DIV1 RCC_D1CFGR_D1CPRE_DIV1

Definition at line 351 of file stm32h7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV128 RCC_D1CFGR_D1CPRE_DIV128

Definition at line 357 of file stm32h7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV16 RCC_D1CFGR_D1CPRE_DIV16

Definition at line 355 of file stm32h7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV2 RCC_D1CFGR_D1CPRE_DIV2

Definition at line 352 of file stm32h7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV256 RCC_D1CFGR_D1CPRE_DIV256

Definition at line 358 of file stm32h7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV4 RCC_D1CFGR_D1CPRE_DIV4

Definition at line 353 of file stm32h7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV512 RCC_D1CFGR_D1CPRE_DIV512

Definition at line 359 of file stm32h7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV64 RCC_D1CFGR_D1CPRE_DIV64

Definition at line 356 of file stm32h7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV8 RCC_D1CFGR_D1CPRE_DIV8

Definition at line 354 of file stm32h7xx_hal_rcc.h.

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STM32H753xx HAL User Manual: RCC HCLK Clock Source

Defines
RCC HCLK Clock Source
RCC Exported Constants

Defines

#define | RCC_HCLK_DIV1 RCC_D1CFGR_HPRE_DIV1
#define | RCC_HCLK_DIV2 RCC_D1CFGR_HPRE_DIV2
#define | RCC_HCLK_DIV4 RCC_D1CFGR_HPRE_DIV4
#define | RCC_HCLK_DIV8 RCC_D1CFGR_HPRE_DIV8
#define | RCC_HCLK_DIV16 RCC_D1CFGR_HPRE_DIV16
#define | RCC_HCLK_DIV64 RCC_D1CFGR_HPRE_DIV64
#define | RCC_HCLK_DIV128 RCC_D1CFGR_HPRE_DIV128
#define | RCC_HCLK_DIV256 RCC_D1CFGR_HPRE_DIV256
#define | RCC_HCLK_DIV512 RCC_D1CFGR_HPRE_DIV512

Define Documentation

#define RCC_HCLK_DIV1 RCC_D1CFGR_HPRE_DIV1

Definition at line 369 of file stm32h7xx_hal_rcc.h.

#define RCC_HCLK_DIV128 RCC_D1CFGR_HPRE_DIV128

Definition at line 375 of file stm32h7xx_hal_rcc.h.

#define RCC_HCLK_DIV16 RCC_D1CFGR_HPRE_DIV16

Definition at line 373 of file stm32h7xx_hal_rcc.h.

#define RCC_HCLK_DIV2 RCC_D1CFGR_HPRE_DIV2

Definition at line 370 of file stm32h7xx_hal_rcc.h.

#define RCC_HCLK_DIV256 RCC_D1CFGR_HPRE_DIV256

Definition at line 376 of file stm32h7xx_hal_rcc.h.

#define RCC_HCLK_DIV4 RCC_D1CFGR_HPRE_DIV4

Definition at line 371 of file stm32h7xx_hal_rcc.h.

#define RCC_HCLK_DIV512 RCC_D1CFGR_HPRE_DIV512

Definition at line 377 of file stm32h7xx_hal_rcc.h.

#define RCC_HCLK_DIV64 RCC_D1CFGR_HPRE_DIV64

Definition at line 374 of file stm32h7xx_hal_rcc.h.

#define RCC_HCLK_DIV8 RCC_D1CFGR_HPRE_DIV8

Definition at line 372 of file stm32h7xx_hal_rcc.h.

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STM32H753xx HAL User Manual: RCC APB3 Clock Source

Defines
RCC APB3 Clock Source
RCC Exported Constants

Defines

#define | RCC_APB3_DIV1 RCC_D1CFGR_D1PPRE_DIV1
#define | RCC_APB3_DIV2 RCC_D1CFGR_D1PPRE_DIV2
#define | RCC_APB3_DIV4 RCC_D1CFGR_D1PPRE_DIV4
#define | RCC_APB3_DIV8 RCC_D1CFGR_D1PPRE_DIV8
#define | RCC_APB3_DIV16 RCC_D1CFGR_D1PPRE_DIV16

Define Documentation

#define RCC_APB3_DIV1 RCC_D1CFGR_D1PPRE_DIV1

Definition at line 386 of file stm32h7xx_hal_rcc.h.

#define RCC_APB3_DIV16 RCC_D1CFGR_D1PPRE_DIV16

Definition at line 390 of file stm32h7xx_hal_rcc.h.

#define RCC_APB3_DIV2 RCC_D1CFGR_D1PPRE_DIV2

Definition at line 387 of file stm32h7xx_hal_rcc.h.

#define RCC_APB3_DIV4 RCC_D1CFGR_D1PPRE_DIV4

Definition at line 388 of file stm32h7xx_hal_rcc.h.

#define RCC_APB3_DIV8 RCC_D1CFGR_D1PPRE_DIV8

Definition at line 389 of file stm32h7xx_hal_rcc.h.

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STM32H753xx HAL User Manual: RCC APB1 Clock Source

Defines
RCC APB1 Clock Source
RCC Exported Constants

Defines

#define | RCC_APB1_DIV1 RCC_D2CFGR_D2PPRE1_DIV1
#define | RCC_APB1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2
#define | RCC_APB1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4
#define | RCC_APB1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8
#define | RCC_APB1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16

Define Documentation

#define RCC_APB1_DIV1 RCC_D2CFGR_D2PPRE1_DIV1

Definition at line 399 of file stm32h7xx_hal_rcc.h.

#define RCC_APB1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16

Definition at line 403 of file stm32h7xx_hal_rcc.h.

#define RCC_APB1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2

Definition at line 400 of file stm32h7xx_hal_rcc.h.

#define RCC_APB1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4

Definition at line 401 of file stm32h7xx_hal_rcc.h.

#define RCC_APB1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8

Definition at line 402 of file stm32h7xx_hal_rcc.h.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC APB2 Clock Source

Defines
RCC APB2 Clock Source
RCC Exported Constants

Defines

#define | RCC_APB2_DIV1 RCC_D2CFGR_D2PPRE2_DIV1
#define | RCC_APB2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2
#define | RCC_APB2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4
#define | RCC_APB2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8
#define | RCC_APB2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16

Define Documentation

#define RCC_APB2_DIV1 RCC_D2CFGR_D2PPRE2_DIV1

Definition at line 412 of file stm32h7xx_hal_rcc.h.

#define RCC_APB2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16

Definition at line 416 of file stm32h7xx_hal_rcc.h.

#define RCC_APB2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2

Definition at line 413 of file stm32h7xx_hal_rcc.h.

#define RCC_APB2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4

Definition at line 414 of file stm32h7xx_hal_rcc.h.

#define RCC_APB2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8

Definition at line 415 of file stm32h7xx_hal_rcc.h.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC APB4 Clock Source

Defines
RCC APB4 Clock Source
RCC Exported Constants

Defines

#define | RCC_APB4_DIV1 RCC_D3CFGR_D3PPRE_DIV1
#define | RCC_APB4_DIV2 RCC_D3CFGR_D3PPRE_DIV2
#define | RCC_APB4_DIV4 RCC_D3CFGR_D3PPRE_DIV4
#define | RCC_APB4_DIV8 RCC_D3CFGR_D3PPRE_DIV8
#define | RCC_APB4_DIV16 RCC_D3CFGR_D3PPRE_DIV16

Define Documentation

#define RCC_APB4_DIV1 RCC_D3CFGR_D3PPRE_DIV1

Definition at line 425 of file stm32h7xx_hal_rcc.h.

#define RCC_APB4_DIV16 RCC_D3CFGR_D3PPRE_DIV16

Definition at line 429 of file stm32h7xx_hal_rcc.h.

#define RCC_APB4_DIV2 RCC_D3CFGR_D3PPRE_DIV2

Definition at line 426 of file stm32h7xx_hal_rcc.h.

#define RCC_APB4_DIV4 RCC_D3CFGR_D3PPRE_DIV4

Definition at line 427 of file stm32h7xx_hal_rcc.h.

#define RCC_APB4_DIV8 RCC_D3CFGR_D3PPRE_DIV8

Definition at line 428 of file stm32h7xx_hal_rcc.h.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC RTC Clock Source

Defines
RCC RTC Clock Source
RCC Exported Constants

Defines

#define | RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)
#define | RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)
#define | RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00002300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00003300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00004300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00005300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00006300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00007300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00008300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00009300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x0000A300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x0000B300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x0000C300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x0000D300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x0000E300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x0000F300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00010300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00011300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00012300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00013300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00014300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00015300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00016300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00017300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00018300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00019300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x0001A300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x0001B300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x0001C300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x0001D300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x0001E300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x0001F300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV32 ((uint32_t)0x00020300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV33 ((uint32_t)0x00021300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV34 ((uint32_t)0x00022300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV35 ((uint32_t)0x00023300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV36 ((uint32_t)0x00024300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV37 ((uint32_t)0x00025300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV38 ((uint32_t)0x00026300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV39 ((uint32_t)0x00027300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV40 ((uint32_t)0x00028300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV41 ((uint32_t)0x00029300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV42 ((uint32_t)0x0002A300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV43 ((uint32_t)0x0002B300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV44 ((uint32_t)0x0002C300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV45 ((uint32_t)0x0002D300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV46 ((uint32_t)0x0002E300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV47 ((uint32_t)0x0002F300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV48 ((uint32_t)0x00030300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV49 ((uint32_t)0x00031300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV50 ((uint32_t)0x00032300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV51 ((uint32_t)0x00033300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV52 ((uint32_t)0x00034300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV53 ((uint32_t)0x00035300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV54 ((uint32_t)0x00036300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV55 ((uint32_t)0x00037300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV56 ((uint32_t)0x00038300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV57 ((uint32_t)0x00039300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV58 ((uint32_t)0x0003A300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV59 ((uint32_t)0x0003B300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV60 ((uint32_t)0x0003C300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV61 ((uint32_t)0x0003D300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV62 ((uint32_t)0x0003E300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV63 ((uint32_t)0x0003F300U)

Define Documentation

#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x0000A300U)

Definition at line 448 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x0000B300U)

Definition at line 449 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x0000C300U)

Definition at line 450 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x0000D300U)

Definition at line 451 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x0000E300U)

Definition at line 452 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x0000F300U)

Definition at line 453 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00010300U)

Definition at line 454 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00011300U)

Definition at line 455 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00012300U)

Definition at line 456 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00013300U)

Definition at line 457 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00002300U)

Definition at line 440 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00014300U)

Definition at line 458 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00015300U)

Definition at line 459 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00016300U)

Definition at line 460 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00017300U)

Definition at line 461 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00018300U)

Definition at line 462 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00019300U)

Definition at line 463 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x0001A300U)

Definition at line 464 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x0001B300U)

Definition at line 465 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x0001C300U)

Definition at line 466 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x0001D300U)

Definition at line 467 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00003300U)

Definition at line 441 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x0001E300U)

Definition at line 468 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x0001F300U)

Definition at line 469 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV32 ((uint32_t)0x00020300U)

Definition at line 470 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV33 ((uint32_t)0x00021300U)

Definition at line 471 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV34 ((uint32_t)0x00022300U)

Definition at line 472 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV35 ((uint32_t)0x00023300U)

Definition at line 473 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV36 ((uint32_t)0x00024300U)

Definition at line 474 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV37 ((uint32_t)0x00025300U)

Definition at line 475 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV38 ((uint32_t)0x00026300U)

Definition at line 476 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV39 ((uint32_t)0x00027300U)

Definition at line 477 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00004300U)

Definition at line 442 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV40 ((uint32_t)0x00028300U)

Definition at line 478 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV41 ((uint32_t)0x00029300U)

Definition at line 479 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV42 ((uint32_t)0x0002A300U)

Definition at line 480 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV43 ((uint32_t)0x0002B300U)

Definition at line 481 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV44 ((uint32_t)0x0002C300U)

Definition at line 482 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV45 ((uint32_t)0x0002D300U)

Definition at line 483 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV46 ((uint32_t)0x0002E300U)

Definition at line 484 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV47 ((uint32_t)0x0002F300U)

Definition at line 485 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV48 ((uint32_t)0x00030300U)

Definition at line 486 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV49 ((uint32_t)0x00031300U)

Definition at line 487 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00005300U)

Definition at line 443 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV50 ((uint32_t)0x00032300U)

Definition at line 488 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV51 ((uint32_t)0x00033300U)

Definition at line 489 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV52 ((uint32_t)0x00034300U)

Definition at line 490 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV53 ((uint32_t)0x00035300U)

Definition at line 491 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV54 ((uint32_t)0x00036300U)

Definition at line 492 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV55 ((uint32_t)0x00037300U)

Definition at line 493 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV56 ((uint32_t)0x00038300U)

Definition at line 494 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV57 ((uint32_t)0x00039300U)

Definition at line 495 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV58 ((uint32_t)0x0003A300U)

Definition at line 496 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV59 ((uint32_t)0x0003B300U)

Definition at line 497 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00006300U)

Definition at line 444 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV60 ((uint32_t)0x0003C300U)

Definition at line 498 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV61 ((uint32_t)0x0003D300U)

Definition at line 499 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV62 ((uint32_t)0x0003E300U)

Definition at line 500 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV63 ((uint32_t)0x0003F300U)

Definition at line 501 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00007300U)

Definition at line 445 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00008300U)

Definition at line 446 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00009300U)

Definition at line 447 of file stm32h7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)

Definition at line 438 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)

Definition at line 439 of file stm32h7xx_hal_rcc.h.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC MCO Index

Defines
RCC MCO Index
RCC Exported Constants

Defines

#define | RCC_MCO1 ((uint32_t)0x00000000)
#define | RCC_MCO2 ((uint32_t)0x00000001)

Define Documentation

#define RCC_MCO1 ((uint32_t)0x00000000)

Definition at line 512 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define RCC_MCO2 ((uint32_t)0x00000001)

Definition at line 513 of file stm32h7xx_hal_rcc.h.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC MCO1 Clock Source

Defines
RCC MCO1 Clock Source
RCC Exported Constants

Defines

#define | RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
#define | RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
#define | RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
#define | RCC_MCO1SOURCE_PLL1QCLK ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1)
#define | RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO1_2

Define Documentation

#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1

Definition at line 524 of file stm32h7xx_hal_rcc.h.

#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)

Definition at line 522 of file stm32h7xx_hal_rcc.h.

#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO1_2

Definition at line 526 of file stm32h7xx_hal_rcc.h.

#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0

Definition at line 523 of file stm32h7xx_hal_rcc.h.

#define RCC_MCO1SOURCE_PLL1QCLK ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1)

Definition at line 525 of file stm32h7xx_hal_rcc.h.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC MCO2 Clock Source

Defines
RCC MCO2 Clock Source
RCC Exported Constants

Defines

#define | RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
#define | RCC_MCO2SOURCE_PLL2PCLK RCC_CFGR_MCO2_0
#define | RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
#define | RCC_MCO2SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1)
#define | RCC_MCO2SOURCE_CSICLK RCC_CFGR_MCO2_2
#define | RCC_MCO2SOURCE_LSICLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2)

Define Documentation

#define RCC_MCO2SOURCE_CSICLK RCC_CFGR_MCO2_2

Definition at line 539 of file stm32h7xx_hal_rcc.h.

#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1

Definition at line 537 of file stm32h7xx_hal_rcc.h.

#define RCC_MCO2SOURCE_LSICLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2)

Definition at line 540 of file stm32h7xx_hal_rcc.h.

#define RCC_MCO2SOURCE_PLL2PCLK RCC_CFGR_MCO2_0

Definition at line 536 of file stm32h7xx_hal_rcc.h.

#define RCC_MCO2SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1)

Definition at line 538 of file stm32h7xx_hal_rcc.h.

#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)

Definition at line 535 of file stm32h7xx_hal_rcc.h.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC MCOx Clock Prescaler

Defines
RCC MCOx Clock Prescaler
RCC Exported Constants

Defines

#define | RCC_MCODIV_1 RCC_CFGR_MCO1PRE_0
#define | RCC_MCODIV_2 RCC_CFGR_MCO1PRE_1
#define | RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
#define | RCC_MCODIV_4 RCC_CFGR_MCO1PRE_2
#define | RCC_MCODIV_5 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
#define | RCC_MCODIV_6 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
#define | RCC_MCODIV_7 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
#define | RCC_MCODIV_8 RCC_CFGR_MCO1PRE_3
#define | RCC_MCODIV_9 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_10 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_11 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_12 ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_13 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_14 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_15 RCC_CFGR_MCO1PRE

Define Documentation

#define RCC_MCODIV_1 RCC_CFGR_MCO1PRE_0

Definition at line 549 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_10 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)

Definition at line 558 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_11 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)

Definition at line 559 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_12 ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)

Definition at line 560 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_13 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)

Definition at line 561 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_14 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)

Definition at line 562 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_15 RCC_CFGR_MCO1PRE

Definition at line 563 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_1

Definition at line 550 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)

Definition at line 551 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_4 RCC_CFGR_MCO1PRE_2

Definition at line 552 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_5 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)

Definition at line 553 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_6 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)

Definition at line 554 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_7 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)

Definition at line 555 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_8 RCC_CFGR_MCO1PRE_3

Definition at line 556 of file stm32h7xx_hal_rcc.h.

#define RCC_MCODIV_9 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)

Definition at line 557 of file stm32h7xx_hal_rcc.h.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC Interrupt

Defines
RCC Interrupt
RCC Exported Constants

Defines

#define | RCC_IT_LSIRDY ((uint32_t)0x00000001)
#define | RCC_IT_LSERDY ((uint32_t)0x00000002)
#define | RCC_IT_HSIRDY ((uint32_t)0x00000004)
#define | RCC_IT_HSERDY ((uint32_t)0x00000008)
#define | RCC_IT_CSIRDY ((uint32_t)0x00000010)
#define | RCC_IT_HSI48RDY ((uint32_t)0x00000020)
#define | RCC_IT_PLLRDY ((uint32_t)0x00000040)
#define | RCC_IT_PLL2RDY ((uint32_t)0x00000080)
#define | RCC_IT_PLL3RDY ((uint32_t)0x00000100)
#define | RCC_IT_LSECSS ((uint32_t)0x00000200)
#define | RCC_IT_CSS ((uint32_t)0x00000400)

Define Documentation

#define RCC_IT_CSIRDY ((uint32_t)0x00000010)

Definition at line 577 of file stm32h7xx_hal_rcc.h.

#define RCC_IT_CSS ((uint32_t)0x00000400)

Definition at line 583 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler().

#define RCC_IT_HSERDY ((uint32_t)0x00000008)

Definition at line 576 of file stm32h7xx_hal_rcc.h.

#define RCC_IT_HSI48RDY ((uint32_t)0x00000020)

Definition at line 578 of file stm32h7xx_hal_rcc.h.

#define RCC_IT_HSIRDY ((uint32_t)0x00000004)

Definition at line 575 of file stm32h7xx_hal_rcc.h.

#define RCC_IT_LSECSS ((uint32_t)0x00000200)

Definition at line 582 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_DisableLSECSS().

#define RCC_IT_LSERDY ((uint32_t)0x00000002)

Definition at line 574 of file stm32h7xx_hal_rcc.h.

#define RCC_IT_LSIRDY ((uint32_t)0x00000001)

Definition at line 573 of file stm32h7xx_hal_rcc.h.

#define RCC_IT_PLL2RDY ((uint32_t)0x00000080)

Definition at line 580 of file stm32h7xx_hal_rcc.h.

#define RCC_IT_PLL3RDY ((uint32_t)0x00000100)

Definition at line 581 of file stm32h7xx_hal_rcc.h.

#define RCC_IT_PLLRDY ((uint32_t)0x00000040)

Definition at line 579 of file stm32h7xx_hal_rcc.h.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC Flag

Defines
RCC Flag
RCC Exported Constants

Elements values convention: 0XXYYYYYb. More...

Defines

#define | RCC_FLAG_HSIRDY ((uint8_t)0x22)
#define | RCC_FLAG_HSIDIV ((uint8_t)0x25)
#define | RCC_FLAG_CSIRDY ((uint8_t)0x28)
#define | RCC_FLAG_HSI48RDY ((uint8_t)0x2D)
#define | RCC_FLAG_D1CKRDY ((uint8_t)0x2E)
#define | RCC_FLAG_D2CKRDY ((uint8_t)0x2F)
#define | RCC_FLAG_HSERDY ((uint8_t)0x31)
#define | RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define | RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
#define | RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
#define | RCC_FLAG_LSERDY ((uint8_t)0x41)
#define | RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define | RCC_FLAG_RMVF ((uint8_t)0x90)
#define | RCC_FLAG_CPURST ((uint8_t)0x91)
#define | RCC_FLAG_D1RST ((uint8_t)0x93)
#define | RCC_FLAG_D2RST ((uint8_t)0x94)
#define | RCC_FLAG_BORRST ((uint8_t)0x95)
#define | RCC_FLAG_PINRST ((uint8_t)0x96)
#define | RCC_FLAG_PORRST ((uint8_t)0x97)
#define | RCC_FLAG_SFTRST ((uint8_t)0x98)
#define | RCC_FLAG_IWDG1RST ((uint8_t)0x9A)
#define | RCC_FLAG_WWDG1RST ((uint8_t)0x9C)
#define | RCC_FLAG_LPWR1RST ((uint8_t)0x9E)
#define | RCC_FLAG_LPWR2RST ((uint8_t)0x9F)

Detailed Description

Elements values convention: 0XXYYYYYb.

  • YYYYY : Flag position in the register
  • 0XX : Register index
    • 01: CR register
    • 10: BDCR register
    • 11: CSR register

Define Documentation

#define RCC_FLAG_BORRST ((uint8_t)0x95)

Definition at line 621 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_CPURST ((uint8_t)0x91)

Definition at line 616 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_CSIRDY ((uint8_t)0x28)

Definition at line 600 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define RCC_FLAG_D1CKRDY ((uint8_t)0x2E)

Definition at line 602 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_D1RST ((uint8_t)0x93)

Definition at line 619 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_D2CKRDY ((uint8_t)0x2F)

Definition at line 603 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_D2RST ((uint8_t)0x94)

Definition at line 620 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_HSERDY ((uint8_t)0x31)

Definition at line 604 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define RCC_FLAG_HSI48RDY ((uint8_t)0x2D)

Definition at line 601 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_FLAG_HSIDIV ((uint8_t)0x25)

Definition at line 599 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPLL1ClockFreq(), HAL_RCCEx_GetPLL2ClockFreq(), HAL_RCCEx_GetPLL3ClockFreq(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define RCC_FLAG_HSIRDY ((uint8_t)0x22)

Definition at line 598 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define RCC_FLAG_IWDG1RST ((uint8_t)0x9A)

Definition at line 625 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_LPWR1RST ((uint8_t)0x9E)

Definition at line 627 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_LPWR2RST ((uint8_t)0x9F)

Definition at line 628 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_LSERDY ((uint8_t)0x41)

Definition at line 609 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_FLAG_LSIRDY ((uint8_t)0x61)

Definition at line 612 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_FLAG_PINRST ((uint8_t)0x96)

Definition at line 622 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)

Definition at line 606 of file stm32h7xx_hal_rcc.h.

Referenced by RCCEx_PLL2_Config().

#define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)

Definition at line 607 of file stm32h7xx_hal_rcc.h.

Referenced by RCCEx_PLL3_Config().

#define RCC_FLAG_PLLRDY ((uint8_t)0x39)

Definition at line 605 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define RCC_FLAG_PORRST ((uint8_t)0x97)

Definition at line 623 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_RMVF ((uint8_t)0x90)

Definition at line 615 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_SFTRST ((uint8_t)0x98)

Definition at line 624 of file stm32h7xx_hal_rcc.h.

#define RCC_FLAG_WWDG1RST ((uint8_t)0x9C)

Definition at line 626 of file stm32h7xx_hal_rcc.h.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LSE Drive Config

Defines
LSE Drive Config
RCC Exported Constants

Defines

#define | RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)
#define | RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
#define | RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
#define | RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

Define Documentation

#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

LSE high drive capability

Definition at line 643 of file stm32h7xx_hal_rcc.h.

#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)

LSE low drive capability

Definition at line 638 of file stm32h7xx_hal_rcc.h.

#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1

LSE medium high drive capability

Definition at line 641 of file stm32h7xx_hal_rcc.h.

#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0

LSE medium low drive capability

Definition at line 639 of file stm32h7xx_hal_rcc.h.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC Stop WakeUpClock

Defines
RCC Stop WakeUpClock
RCC Exported Constants

Defines

#define | RCC_STOP_WAKEUPCLOCK_HSI ((uint32_t)0x00000000)
#define | RCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR_STOPWUCK

Define Documentation

#define RCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR_STOPWUCK

Definition at line 652 of file stm32h7xx_hal_rcc.h.

#define RCC_STOP_WAKEUPCLOCK_HSI ((uint32_t)0x00000000)

Definition at line 651 of file stm32h7xx_hal_rcc.h.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC Stop KernelWakeUpClock

Defines
RCC Stop KernelWakeUpClock
RCC Exported Constants

Defines

#define | RCC_STOP_KERWAKEUPCLOCK_HSI ((uint32_t)0x00000000)
#define | RCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR_STOPKERWUCK

Define Documentation

#define RCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR_STOPKERWUCK

Definition at line 662 of file stm32h7xx_hal_rcc.h.

#define RCC_STOP_KERWAKEUPCLOCK_HSI ((uint32_t)0x00000000)

Definition at line 661 of file stm32h7xx_hal_rcc.h.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: LSE Configuration

Defines
LSE Configuration
RCC Exported Macros

Defines

#define __HAL_RCC_LSE_CONFIG(__STATE__)
Macro to configure the External Low Speed oscillator (LSE).

Define Documentation

#define __HAL_RCC_LSE_CONFIG ( __STATE__ )
Value:
do {                                       \
                      if((__STATE__) == RCC_LSE_ON)            \
                      {                                        \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
                      }                                        \
                      else if((__STATE__) == RCC_LSE_OFF)      \
                      {                                        \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
                      }                                        \
                      else if((__STATE__) == RCC_LSE_BYPASS)   \
                      {                                        \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
                      }                                        \
                      else                                     \
                      {                                        \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
                      }                                        \
                    } while(0)

Macro to configure the External Low Speed oscillator (LSE).

Note:
Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. User should request a transition to LSE Off first and then LSE On or LSE Bypass.
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
Parameters:
__STATE__,: specifies the new state of the LSE. This parameter can be one of the following values:
  • RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
  • RCC_LSE_ON: turn ON the LSE oscillator.
  • RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.

Definition at line 2418 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Flags Interrupts Management

Defines
Flags Interrupts Management
RCC Exported Macros

macros to manage the specified RCC Flags and interrupts. More...

Defines

#define | __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
Enable RCC interrupt.
#define | __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
Disable RCC interrupt.
#define | __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
Clear the RCC's interrupt pending bits.
#define | __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
Check the RCC's interrupt has occurred or not.
#define | __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF)
Set RMVF bit to clear the reset flags.
#define | RCC_FLAG_MASK ((uint8_t)0x1F)
Check RCC flag is set or not.
#define | __HAL_RCC_GET_FLAG(__FLAG__)

Detailed Description

macros to manage the specified RCC Flags and interrupts.

Define Documentation

#define __HAL_RCC_CLEAR_IT ( __INTERRUPT__ ) (RCC->CICR = (__INTERRUPT__))

Clear the RCC's interrupt pending bits.

Parameters:
__INTERRUPT__,: specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_CSIRDY: CSI ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_HSI48RDY: HSI48 ready interrupt
  • RCC_IT_PLLRDY: main PLL ready interrupt
  • RCC_IT_PLL2RDY: PLL2 ready interrupt
  • RCC_IT_PLL3RDY: PLL3 ready interrupt
  • RCC_IT_HSECSS: HSE Clock Security interrupt
  • RCC_IT_LSECSS: Clock security system interrupt

Definition at line 2744 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler().

#define __HAL_RCC_CLEAR_RESET_FLAGS ( ) (RCC->RSR |= RCC_RSR_RMVF)

Set RMVF bit to clear the reset flags.

Definition at line 2766 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DISABLE_IT ( __INTERRUPT__ ) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))

Disable RCC interrupt.

Parameters:
__INTERRUPT__,: specifies the RCC interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_CSIRDY: HSI ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_HSI48RDY: HSI48 ready interrupt
  • RCC_IT_PLLRDY: main PLL ready interrupt
  • RCC_IT_PLL2RDY: PLL2 ready interrupt
  • RCC_IT_PLL3RDY: PLL3 ready interrupt
  • RCC_IT_LSECSS: Clock security system interrupt

Definition at line 2727 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_DisableLSECSS().

#define __HAL_RCC_ENABLE_IT ( __INTERRUPT__ ) SET_BIT(RCC->CIER, (__INTERRUPT__))

Enable RCC interrupt.

Parameters:
__INTERRUPT__,: specifies the RCC interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_CSIRDY: HSI ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_HSI48RDY: HSI48 ready interrupt
  • RCC_IT_PLLRDY: main PLL ready interrupt
  • RCC_IT_PLL2RDY: PLL2 ready interrupt
  • RCC_IT_PLL3RDY: PLL3 ready interrupt
  • RCC_IT_LSECSS: Clock security system interrupt

Definition at line 2711 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GET_FLAG ( __FLAG__ )
Value:
(((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR : \
((((__FLAG__) >> 5) == 3)? RCC->CSR : ((((__FLAG__) >> 5) == 4)? RCC->RSR :RCC->CIFR))))  & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)

Definition at line 2801 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_GetSysClockFreq(), HAL_RCC_OscConfig(), HAL_RCCEx_GetPLL1ClockFreq(), HAL_RCCEx_GetPLL2ClockFreq(), HAL_RCCEx_GetPLL3ClockFreq(), HAL_RCCEx_PeriphCLKConfig(), RCCEx_PLL2_Config(), RCCEx_PLL3_Config(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define __HAL_RCC_GET_IT ( __INTERRUPT__ ) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))

Check the RCC's interrupt has occurred or not.

Parameters:
__INTERRUPT__,: specifies the RCC interrupt source to check. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_CSIRDY: CSI ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_HSI48RDY: HSI48 ready interrupt
  • RCC_IT_PLLRDY: main PLL ready interrupt
  • RCC_IT_PLL2RDY: PLL2 ready interrupt
  • RCC_IT_PLL3RDY: PLL3 ready interrupt
  • RCC_IT_HSECSS: HSE Clock Security interrupt
  • RCC_IT_LSECSS: Clock security system interrupt
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 2762 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler().

#define RCC_FLAG_MASK ((uint8_t)0x1F)

Check RCC flag is set or not.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • RCC_FLAG_HSIRDY: HSI oscillator clock ready
  • RCC_FLAG_HSIDIV: HSI divider flag
  • RCC_FLAG_CSIRDY: CSI oscillator clock ready
  • RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready
  • RCC_FLAG_HSERDY: HSE oscillator clock ready
  • RCC_FLAG_D1CKRDY: Domain1 clock ready
  • RCC_FLAG_D2CKRDY: Domain2 clock ready
  • RCC_FLAG_PLLRDY: PLL1 clock ready
  • RCC_FLAG_PLL2RDY: PLL2 clock ready
  • RCC_FLAG_PLL3RDY: PLL3 clock ready
  • RCC_FLAG_LSERDY: LSE oscillator clock ready
  • RCC_FLAG_LSIRDY: LSI oscillator clock ready
  • RCC_FLAG_RMVF: Remove reset Flag
  • RCC_FLAG_CPURST: CPU reset flag
  • RCC_FLAG_D1RST: D1 domain power switch reset flag
  • RCC_FLAG_D2RST: D2 domain power switch reset flag
  • RCC_FLAG_BORRST: BOR reset flag
  • RCC_FLAG_PINRST: Pin reset
  • RCC_FLAG_PORRST: POR/PDR reset
  • RCC_FLAG_SFTRST: System reset from CPU reset flag
  • RCC_FLAG_BORRST: D2 domain power switch reset flag
  • RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset
  • RCC_FLAG_WWDG1RST: Window Watchdog1 reset
  • RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag
  • RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 2800 of file stm32h7xx_hal_rcc.h.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC Exported Macros

Modules | Defines
RCC Exported Macros
RCC

Modules

LSE Configuration
Flags Interrupts Management

macros to manage the specified RCC Flags and interrupts.

Defines

#define | __HAL_RCC_MDMA_CLK_ENABLE()
Enable or disable the AHB3 peripheral clock.
#define | __HAL_RCC_DMA2D_CLK_ENABLE()
#define | __HAL_RCC_JPGDECEN_CLK_ENABLE()
#define | __HAL_RCC_FLASH_CLK_ENABLE()
#define | __HAL_RCC_FMC_CLK_ENABLE()
#define | __HAL_RCC_QSPI_CLK_ENABLE()
#define | __HAL_RCC_SDMMC1_CLK_ENABLE()
#define | __HAL_RCC_MDMA_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
#define | __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
#define | __HAL_RCC_JPGDECEN_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
#define | __HAL_RCC_FLASH_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FLASHEN))
#define | __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
#define | __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
#define | __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
#define | __HAL_RCC_DMA1_CLK_ENABLE()
Enable or disable the AHB1 peripheral clock.
#define | __HAL_RCC_DMA2_CLK_ENABLE()
#define | __HAL_RCC_ADC12_CLK_ENABLE()
#define | __HAL_RCC_ETH1MAC_CLK_ENABLE()
#define | __HAL_RCC_ETH1TX_CLK_ENABLE()
#define | __HAL_RCC_ETH1RX_CLK_ENABLE()
#define | __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
#define | __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
#define | __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
#define | __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
#define | __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
#define | __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
#define | __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
#define | __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
#define | __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
#define | __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
#define | __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
#define | __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
#define | __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
#define | __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
#define | __HAL_RCC_DCMI_CLK_ENABLE()
Enable or disable the AHB2 peripheral clock.
#define | __HAL_RCC_CRYP_CLK_ENABLE()
#define | __HAL_RCC_HASH_CLK_ENABLE()
#define | __HAL_RCC_RNG_CLK_ENABLE()
#define | __HAL_RCC_SDMMC2_CLK_ENABLE()
#define | __HAL_RCC_D2SRAM1_CLK_ENABLE()
#define | __HAL_RCC_D2SRAM2_CLK_ENABLE()
#define | __HAL_RCC_D2SRAM3_CLK_ENABLE()
#define | __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
#define | __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
#define | __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
#define | __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
#define | __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
#define | __HAL_RCC_D2SRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
#define | __HAL_RCC_D2SRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
#define | __HAL_RCC_D2SRAM3_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
#define | __HAL_RCC_GPIOA_CLK_ENABLE()
Enable or disable the AHB4 peripheral clock.
#define | __HAL_RCC_GPIOB_CLK_ENABLE()
#define | __HAL_RCC_GPIOC_CLK_ENABLE()
#define | __HAL_RCC_GPIOD_CLK_ENABLE()
#define | __HAL_RCC_GPIOE_CLK_ENABLE()
#define | __HAL_RCC_GPIOF_CLK_ENABLE()
#define | __HAL_RCC_GPIOG_CLK_ENABLE()
#define | __HAL_RCC_GPIOH_CLK_ENABLE()
#define | __HAL_RCC_GPIOI_CLK_ENABLE()
#define | __HAL_RCC_GPIOJ_CLK_ENABLE()
#define | __HAL_RCC_GPIOK_CLK_ENABLE()
#define | __HAL_RCC_CRC_CLK_ENABLE()
#define | __HAL_RCC_BDMA_CLK_ENABLE()
#define | __HAL_RCC_ADC3_CLK_ENABLE()
#define | __HAL_RCC_HSEM_CLK_ENABLE()
#define | __HAL_RCC_BKPRAM_CLK_ENABLE()
#define | __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
#define | __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
#define | __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
#define | __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
#define | __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
#define | __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
#define | __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
#define | __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
#define | __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
#define | __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
#define | __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
#define | __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
#define | __HAL_RCC_BDMA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
#define | __HAL_RCC_ADC3_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
#define | __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
#define | __HAL_RCC_BKPRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
#define | __HAL_RCC_LTDC_CLK_ENABLE()
Enable or disable the APB3 peripheral clock.
#define | __HAL_RCC_WWDG1_CLK_ENABLE()
#define | __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
#define | __HAL_RCC_WWDG1_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
#define | __HAL_RCC_TIM2_CLK_ENABLE()
Enable or disable the APB1 peripheral clock.
#define | __HAL_RCC_TIM3_CLK_ENABLE()
#define | __HAL_RCC_TIM4_CLK_ENABLE()
#define | __HAL_RCC_TIM5_CLK_ENABLE()
#define | __HAL_RCC_TIM6_CLK_ENABLE()
#define | __HAL_RCC_TIM7_CLK_ENABLE()
#define | __HAL_RCC_TIM12_CLK_ENABLE()
#define | __HAL_RCC_TIM13_CLK_ENABLE()
#define | __HAL_RCC_TIM14_CLK_ENABLE()
#define | __HAL_RCC_LPTIM1_CLK_ENABLE()
#define | __HAL_RCC_SPI2_CLK_ENABLE()
#define | __HAL_RCC_SPI3_CLK_ENABLE()
#define | __HAL_RCC_SPDIFRX_CLK_ENABLE()
#define | __HAL_RCC_USART2_CLK_ENABLE()
#define | __HAL_RCC_USART3_CLK_ENABLE()
#define | __HAL_RCC_UART4_CLK_ENABLE()
#define | __HAL_RCC_UART5_CLK_ENABLE()
#define | __HAL_RCC_I2C1_CLK_ENABLE()
#define | __HAL_RCC_I2C2_CLK_ENABLE()
#define | __HAL_RCC_I2C3_CLK_ENABLE()
#define | __HAL_RCC_CEC_CLK_ENABLE()
#define | __HAL_RCC_DAC12_CLK_ENABLE()
#define | __HAL_RCC_UART7_CLK_ENABLE()
#define | __HAL_RCC_UART8_CLK_ENABLE()
#define | __HAL_RCC_CRS_CLK_ENABLE()
#define | __HAL_RCC_SWPMI1_CLK_ENABLE()
#define | __HAL_RCC_OPAMP_CLK_ENABLE()
#define | __HAL_RCC_MDIOS_CLK_ENABLE()
#define | __HAL_RCC_FDCAN_CLK_ENABLE()
#define | __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
#define | __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
#define | __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
#define | __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
#define | __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
#define | __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
#define | __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
#define | __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
#define | __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
#define | __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
#define | __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
#define | __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
#define | __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
#define | __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
#define | __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
#define | __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
#define | __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
#define | __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
#define | __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
#define | __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
#define | __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
#define | __HAL_RCC_DAC12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
#define | __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
#define | __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
#define | __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
#define | __HAL_RCC_SWPMI1_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
#define | __HAL_RCC_OPAMP_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
#define | __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
#define | __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
#define | __HAL_RCC_TIM1_CLK_ENABLE()
Enable or disable the APB2 peripheral clock.
#define | __HAL_RCC_TIM8_CLK_ENABLE()
#define | __HAL_RCC_USART1_CLK_ENABLE()
#define | __HAL_RCC_USART6_CLK_ENABLE()
#define | __HAL_RCC_SPI1_CLK_ENABLE()
#define | __HAL_RCC_SPI4_CLK_ENABLE()
#define | __HAL_RCC_TIM15_CLK_ENABLE()
#define | __HAL_RCC_TIM16_CLK_ENABLE()
#define | __HAL_RCC_TIM17_CLK_ENABLE()
#define | __HAL_RCC_SPI5_CLK_ENABLE()
#define | __HAL_RCC_SAI1_CLK_ENABLE()
#define | __HAL_RCC_SAI2_CLK_ENABLE()
#define | __HAL_RCC_SAI3_CLK_ENABLE()
#define | __HAL_RCC_DFSDM1_CLK_ENABLE()
#define | __HAL_RCC_HRTIM1_CLK_ENABLE()
#define | __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
#define | __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
#define | __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
#define | __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
#define | __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
#define | __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
#define | __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
#define | __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
#define | __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
#define | __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
#define | __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
#define | __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
#define | __HAL_RCC_SAI3_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
#define | __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
#define | __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
#define | __HAL_RCC_SYSCFG_CLK_ENABLE()
Enable or disable the APB4 peripheral clock.
#define | __HAL_RCC_LPUART1_CLK_ENABLE()
#define | __HAL_RCC_SPI6_CLK_ENABLE()
#define | __HAL_RCC_I2C4_CLK_ENABLE()
#define | __HAL_RCC_LPTIM2_CLK_ENABLE()
#define | __HAL_RCC_LPTIM3_CLK_ENABLE()
#define | __HAL_RCC_LPTIM4_CLK_ENABLE()
#define | __HAL_RCC_LPTIM5_CLK_ENABLE()
#define | __HAL_RCC_COMP12_CLK_ENABLE()
#define | __HAL_RCC_VREF_CLK_ENABLE()
#define | __HAL_RCC_SAI4_CLK_ENABLE()
#define | __HAL_RCC_RTC_CLK_ENABLE()
#define | __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
#define | __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
#define | __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
#define | __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
#define | __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
#define | __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
#define | __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
#define | __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
#define | __HAL_RCC_COMP12_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
#define | __HAL_RCC_VREF_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
#define | __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
#define | __HAL_RCC_SAI4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
#define | __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
Enable or disable the AHB3 peripheral reset.
#define | __HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))
#define | __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))
#define | __HAL_RCC_JPGDECRST_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST))
#define | __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
#define | __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
#define | __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST))
#define | __HAL_RCC_CPU_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_CPURST))
#define | __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
#define | __HAL_RCC_MDMA_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))
#define | __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))
#define | __HAL_RCC_JPGDECRST_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST))
#define | __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))
#define | __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST))
#define | __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))
#define | __HAL_RCC_CPU_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_CPURST))
#define | __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
Force or release the AHB1 peripheral reset.
#define | __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
#define | __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
#define | __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST))
#define | __HAL_RCC_ETH1MAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST))
#define | __HAL_RCC_USB1_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST))
#define | __HAL_RCC_USB2_OTG_FS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST))
#define | __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
#define | __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST))
#define | __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST))
#define | __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST))
#define | __HAL_RCC_ETH1MAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST))
#define | __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST))
#define | __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST))
#define | __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
Force or release the AHB2 peripheral reset.
#define | __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
#define | __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
#define | __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
#define | __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
#define | __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))
#define | __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
#define | __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST))
#define | __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST))
#define | __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST))
#define | __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))
#define | __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))
#define | __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0xFFFFFFFF)
Force or release the AHB4 peripheral reset.
#define | __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST)
#define | __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST)
#define | __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST)
#define | __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST)
#define | __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST)
#define | __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST)
#define | __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST)
#define | __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST)
#define | __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST)
#define | __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST)
#define | __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST)
#define | __HAL_RCC_PWR_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_PWRRST)
#define | __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST)
#define | __HAL_RCC_BDMA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST)
#define | __HAL_RCC_ADC3_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST)
#define | __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST)
#define | __HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTR = 0x00)
#define | __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST)
#define | __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST)
#define | __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST)
#define | __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST)
#define | __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST)
#define | __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)
#define | __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)
#define | __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)
#define | __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST)
#define | __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)
#define | __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)
#define | __HAL_RCC_PWR_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_PWRRST)
#define | __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST)
#define | __HAL_RCC_BDMA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST)
#define | __HAL_RCC_ADC3_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST)
#define | __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST)
#define | __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0xFFFFFFFF)
Force or release the APB3 peripheral reset.
#define | __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST)
#define | __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTR = 0x00)
#define | __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST)
#define | __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xFFFFFFFF)
Force or release the APB1 peripheral reset.
#define | __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0xFFFFFFFF)
#define | __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST)
#define | __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST)
#define | __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST)
#define | __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST)
#define | __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST)
#define | __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST)
#define | __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST)
#define | __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST)
#define | __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST)
#define | __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST)
#define | __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST)
#define | __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST)
#define | __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST)
#define | __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST)
#define | __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST)
#define | __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST)
#define | __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST)
#define | __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST)
#define | __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST)
#define | __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST)
#define | __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST)
#define | __HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST)
#define | __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST)
#define | __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST)
#define | __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST)
#define | __HAL_RCC_SWPMI1_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST)
#define | __HAL_RCC_OPAMP_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST)
#define | __HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST)
#define | __HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST)
#define | __HAL_RCC_APB1L_RELEASE_RESET() (RCC->APB1LRSTR = 0x00)
#define | __HAL_RCC_APB1H_RELEASE_RESET() (RCC->APB1HRSTR = 0x00)
#define | __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST)
#define | __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST)
#define | __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST)
#define | __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST)
#define | __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST)
#define | __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST)
#define | __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST)
#define | __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST)
#define | __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST)
#define | __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST)
#define | __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST)
#define | __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST)
#define | __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST)
#define | __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)
#define | __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST)
#define | __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST)
#define | __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST)
#define | __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)
#define | __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)
#define | __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)
#define | __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)
#define | __HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)
#define | __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)
#define | __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST)
#define | __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST)
#define | __HAL_RCC_SWPMI1_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST)
#define | __HAL_RCC_OPAMP_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)
#define | __HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)
#define | __HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)
#define | __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Force or release the APB2 peripheral reset.
#define | __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST)
#define | __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST)
#define | __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST)
#define | __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST)
#define | __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST)
#define | __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST)
#define | __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST)
#define | __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST)
#define | __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST)
#define | __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST)
#define | __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST)
#define | __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST)
#define | __HAL_RCC_SAI3_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST)
#define | __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST)
#define | __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST)
#define | __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
#define | __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST)
#define | __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST)
#define | __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST)
#define | __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST)
#define | __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST)
#define | __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST)
#define | __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST)
#define | __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST)
#define | __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)
#define | __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)
#define | __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)
#define | __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST)
#define | __HAL_RCC_SAI3_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST)
#define | __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST)
#define | __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST)
#define | __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0xFFFFFFFF)
Force or release the APB4 peripheral reset.
#define | __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST)
#define | __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST)
#define | __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST)
#define | __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST)
#define | __HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST)
#define | __HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST)
#define | __HAL_RCC_LPTIM4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST)
#define | __HAL_RCC_LPTIM5_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST)
#define | __HAL_RCC_COMP12_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST)
#define | __HAL_RCC_VREF_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST)
#define | __HAL_RCC_SAI4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST)
#define | __HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTR = 0x00)
#define | __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST)
#define | __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST)
#define | __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST)
#define | __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST)
#define | __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST)
#define | __HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST)
#define | __HAL_RCC_LPTIM4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST)
#define | __HAL_RCC_LPTIM5_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST)
#define | __HAL_RCC_COMP12_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST)
#define | __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST)
#define | __HAL_RCC_SAI4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST)
#define | __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
#define | __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
#define | __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
#define | __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
#define | __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
#define | __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
#define | __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
#define | __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
#define | __HAL_RCC_ITCM_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
#define | __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
#define | __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
#define | __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
#define | __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
#define | __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
#define | __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
#define | __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
#define | __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
#define | __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
#define | __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
#define | __HAL_RCC_ITCM_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
#define | __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
#define | __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
#define | __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
#define | __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
#define | __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
#define | __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
#define | __HAL_RCC_ETH1PTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1PTPLPEN))
#define | __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
#define | __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
#define | __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
#define | __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
#define | __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
#define | __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
#define | __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
#define | __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
#define | __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
#define | __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
#define | __HAL_RCC_ETH1PTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1PTPLPEN))
#define | __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
#define | __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
#define | __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
#define | __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
#define | __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
#define | __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
#define | __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
#define | __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
#define | __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
#define | __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
#define | __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
#define | __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
#define | __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
#define | __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
#define | __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
#define | __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
#define | __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
#define | __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
#define | __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
#define | __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
#define | __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
#define | __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
#define | __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
#define | __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
#define | __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
#define | __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
#define | __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_PWRLPEN)
#define | __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
#define | __HAL_RCC_BDMA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
#define | __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
#define | __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
#define | __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN))
#define | __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
#define | __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
#define | __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
#define | __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
#define | __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
#define | __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
#define | __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
#define | __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
#define | __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_PWRLPEN)
#define | __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
#define | __HAL_RCC_BDMA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
#define | __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
#define | __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
#define | __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
#define | __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
#define | __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
#define | __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
#define | __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
#define | __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
#define | __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
#define | __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
#define | __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
#define | __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
#define | __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
#define | __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
#define | __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
#define | __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
#define | __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
#define | __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
#define | __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
#define | __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
#define | __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
#define | __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
#define | __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
#define | __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
#define | __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
#define | __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
#define | __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
#define | __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
#define | __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
#define | __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
#define | __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
#define | __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
#define | __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
#define | __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
#define | __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
#define | __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
#define | __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
#define | __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
#define | __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
#define | __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
#define | __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
#define | __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
#define | __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
#define | __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
#define | __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
#define | __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
#define | __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
#define | __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
#define | __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
#define | __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
#define | __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
#define | __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
#define | __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
#define | __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
#define | __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
#define | __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
#define | __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
#define | __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
#define | __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
#define | __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
#define | __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
#define | __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
#define | __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
#define | __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
#define | __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
#define | __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
#define | __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
#define | __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
#define | __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
#define | __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
#define | __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
#define | __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
#define | __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
#define | __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
#define | __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
#define | __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
#define | __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
#define | __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
#define | __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
#define | __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
#define | __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
#define | __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
#define | __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
#define | __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
#define | __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
#define | __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
#define | __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
#define | __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
#define | __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
#define | __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
#define | __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
#define | __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
#define | __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
#define | __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
#define | __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
#define | __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
#define | __HAL_RCC_COMP12_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
#define | __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
#define | __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
#define | __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
#define | __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
#define | __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
#define | __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
#define | __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
#define | __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
#define | __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
#define | __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
#define | __HAL_RCC_COMP12_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
#define | __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
#define | __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
#define | __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
#define | __HAL_RCC_BDMA_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN)
Enable or disable peripheral bus clock when D3 domain is in DRUN.
#define | __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN)
#define | __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN)
#define | __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN)
#define | __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN)
#define | __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN)
#define | __HAL_RCC_LPTIM4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN)
#define | __HAL_RCC_LPTIM5_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN)
#define | __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN)
#define | __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN)
#define | __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN)
#define | __HAL_RCC_CRC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN)
#define | __HAL_RCC_SAI4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN)
#define | __HAL_RCC_ADC3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN)
#define | __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN)
#define | __HAL_RCC_D3SRAM1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN)
#define | __HAL_RCC_BDMA_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN)
#define | __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN)
#define | __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN)
#define | __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN)
#define | __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN)
#define | __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN)
#define | __HAL_RCC_LPTIM4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN)
#define | __HAL_RCC_LPTIM5_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN)
#define | __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN)
#define | __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN)
#define | __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_RTCAMEN)
#define | __HAL_RCC_CRC_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_CRCAMEN)
#define | __HAL_RCC_SAI4_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_SAI4AMEN)
#define | __HAL_RCC_ADC3_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_ADC3AMEN)
#define | __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN)
#define | __HAL_RCC_D3SRAM1_CLKAM_DISABLE() (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN)
#define | __HAL_RCC_HSI_CONFIG(__STATE__) MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__))
Macro to enable or disable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))
Macro to get the HSI divider.
#define | __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
Macros to enable or disable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
#define | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_ICSCR_HSITRIM))
Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
#define | __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for some peripherals.
#define | __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
#define | __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON);
Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
#define | __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
#define | __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION)
Macros to enable or disable the Internal oscillator (CSI).
#define | __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION)
#define | __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) MODIFY_REG(RCC->ICSCR, RCC_ICSCR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << POSITION_VAL(RCC_ICSCR_CSITRIM))
Macro Adjusts the Internal oscillator (CSI) calibration value.
#define | __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON)
Macros to enable or disable the force of the Low-power Internal oscillator (CSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
#define | __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)
#define | __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
Macros to enable or disable the Internal Low Speed oscillator (LSI).
#define | __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
#define | __HAL_RCC_HSE_CONFIG(__STATE__)
Macro to configure the External High Speed oscillator (__HSE__).
#define | __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Macros to enable or disable the the RTC clock.
#define | __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
#define | __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__)
Macros to configure the RTC clock (RTCCLK).
#define | __HAL_RCC_RTC_CONFIG(__RTCCLKSource__)
#define | __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
#define | __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Macros to force or release the Backup domain reset.
#define | __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
#define | __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON)
Macros to enable or disable the main PLL.
#define | __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)
#define | __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)
#define | __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
#define | __HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO.
#define | __HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
#define | __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__, __PLLR1__)
Macro to configures the main PLL clock source, multiplication and division factors.
#define | __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))
Macro to configure the PLLs clock source.
#define | __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << POSITION_VAL(RCC_PLL1FRACR_FRACN1))
Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor.
#define | __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))
Macro to select the PLL1 reference frequency range.
#define | __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))
Macro to select the PLL1 reference frequency range.
#define | __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Macro to get the clock source used as system clock.
#define | __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
Macro to configure the system clock source.
#define | __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))
Macro to get the oscillator used as PLL clock source.
#define | __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
Macro to configure the External Low Speed oscillator (LSE) drive capability.
#define | __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))
Macro to configure the wake up from stop clock.
#define | __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))
Macro to configure the Kernel wake up from stop clock.
#define | RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> POSITION_VAL(RCC_PLLCKSELR_PLLSRC))

Define Documentation

#define __HAL_RCC_ADC12_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))

Definition at line 837 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC12_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 771 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))

Definition at line 1935 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))

Definition at line 1923 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC12_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST))

Definition at line 1665 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC12_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST))

Definition at line 1674 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC3_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)

Definition at line 1073 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC3_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1035 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)

Definition at line 2009 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)

Definition at line 1991 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC3_CLKAM_DISABLE ( ) (RCC->D3AMR) &= ~(RCC_D3AMR_ADC3AMEN)

Definition at line 2210 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC3_CLKAM_ENABLE ( ) (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN)

Definition at line 2191 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC3_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST)

Definition at line 1715 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ADC3_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST)

Definition at line 1733 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_AHB1_FORCE_RESET ( ) (RCC->AHB1RSTR = 0xFFFFFFFF)

Force or release the AHB1 peripheral reset.

Definition at line 1662 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB1_RELEASE_RESET ( ) (RCC->AHB1RSTR = 0x00)

Definition at line 1671 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB2_FORCE_RESET ( ) (RCC->AHB2RSTR = 0xFFFFFFFF)

Force or release the AHB2 peripheral reset.

Definition at line 1682 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB2_RELEASE_RESET ( ) (RCC->AHB2RSTR = 0x00)

Definition at line 1689 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB3_FORCE_RESET ( ) (RCC->AHB3RSTR = 0xFFFFFFFF)

Enable or disable the AHB3 peripheral reset.

Definition at line 1639 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB3_RELEASE_RESET ( ) (RCC->AHB3RSTR = 0x00)

Definition at line 1649 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB4_FORCE_RESET ( ) (RCC->AHB4RSTR = 0xFFFFFFFF)

Force or release the AHB4 peripheral reset.

Definition at line 1700 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB4_RELEASE_RESET ( ) (RCC->AHB4RSTR = 0x00)

Definition at line 1718 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB1H_FORCE_RESET ( ) (RCC->APB1HRSTR = 0xFFFFFFFF)

Definition at line 1749 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB1H_RELEASE_RESET ( ) (RCC->APB1HRSTR = 0x00)

Definition at line 1781 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB1L_FORCE_RESET ( ) (RCC->APB1LRSTR = 0xFFFFFFFF)

Force or release the APB1 peripheral reset.

Definition at line 1748 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB1L_RELEASE_RESET ( ) (RCC->APB1LRSTR = 0x00)

Definition at line 1780 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB2_FORCE_RESET ( ) (RCC->APB2RSTR = 0xFFFFFFFF)

Force or release the APB2 peripheral reset.

Definition at line 1814 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB2_RELEASE_RESET ( ) (RCC->APB2RSTR = 0x00)

Definition at line 1831 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB3_FORCE_RESET ( ) (RCC->APB3RSTR = 0xFFFFFFFF)

Force or release the APB3 peripheral reset.

Definition at line 1739 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB3_RELEASE_RESET ( ) (RCC->APB3RSTR = 0x00)

Definition at line 1742 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB4_FORCE_RESET ( ) (RCC->APB4RSTR = 0xFFFFFFFF)

Force or release the APB4 peripheral reset.

Definition at line 1851 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB4_RELEASE_RESET ( ) (RCC->APB4RSTR = 0x00)

Definition at line 1865 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_BACKUPRESET_FORCE ( ) SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)

Macros to force or release the Backup domain reset.

Note:
This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_CSR register.
The BKPSRAM is not affected by this reset.

Definition at line 2486 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_BACKUPRESET_RELEASE ( ) CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)

Definition at line 2487 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_BDMA_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)

Definition at line 1072 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1027 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)

Definition at line 2008 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)

Definition at line 1990 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA_CLKAM_DISABLE ( ) (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN)

Definition at line 2197 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA_CLKAM_ENABLE ( ) (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN)

Enable or disable peripheral bus clock when D3 domain is in DRUN.

Note:
After reset, peripheral clock is disabled when CPU is in CSTOP

Definition at line 2178 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST)

Definition at line 1714 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BDMA_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST)

Definition at line 1732 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BKPRAM_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)

Definition at line 1075 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BKPRAM_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1051 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)

Definition at line 2010 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)

Definition at line 1992 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BKPRAM_CLKAM_DISABLE ( ) (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN)

Definition at line 2213 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_BKPRAM_CLKAM_ENABLE ( ) (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN)

Definition at line 2194 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CEC_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)

Definition at line 1366 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CEC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1271 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)

Definition at line 2089 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)

Definition at line 2056 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CEC_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST)

Definition at line 1770 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CEC_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)

Definition at line 1802 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_COMP12_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)

Definition at line 1629 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_COMP12_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1588 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)

Definition at line 2167 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)

Definition at line 2153 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_COMP12_CLKAM_DISABLE ( ) (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN)

Definition at line 2205 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_COMP12_CLKAM_ENABLE ( ) (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN)

Definition at line 2186 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_COMP12_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST)

Definition at line 1860 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_COMP12_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST)

Definition at line 1874 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CPU_FORCE_RESET ( ) (RCC->AHB3RSTR |= (RCC_AHB3RSTR_CPURST))

Definition at line 1646 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CPU_RELEASE_RESET ( ) (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_CPURST))

Definition at line 1656 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)

Definition at line 1071 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1019 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)

Definition at line 2007 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)

Definition at line 1989 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLKAM_DISABLE ( ) (RCC->D3AMR) &= ~(RCC_D3AMR_CRCAMEN)

Definition at line 2208 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLKAM_ENABLE ( ) (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN)

Definition at line 2189 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRC_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST)

Definition at line 1713 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRC_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST)

Definition at line 1731 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRS_CLK_DISABLE ( ) (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)

Definition at line 1370 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRS_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1303 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE ( ) (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)

Definition at line 2093 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE ( ) (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)

Definition at line 2060 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRS_FORCE_RESET ( ) (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST)

Definition at line 1774 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_CRSConfig().

#define __HAL_RCC_CRS_RELEASE_RESET ( ) (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST)

Definition at line 1806 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_CRSConfig().

#define __HAL_RCC_CRYP_CLK_DISABLE ( ) (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))

Definition at line 917 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRYP_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 860 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE ( ) (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))

Definition at line 1962 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE ( ) (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))

Definition at line 1953 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRYP_FORCE_RESET ( ) (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))

Definition at line 1684 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CRYP_RELEASE_RESET ( ) (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST))

Definition at line 1691 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST ( __CSICalibrationValue__ ) MODIFY_REG(RCC->ICSCR, RCC_ICSCR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << POSITION_VAL(RCC_ICSCR_CSITRIM))

Macro Adjusts the Internal oscillator (CSI) calibration value.

Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal CSI RC.
Parameters:
__CSICalibrationValue__,: specifies the calibration trimming value. This parameter must be a number between 0 and 0x1F.

Definition at line 2327 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_CSI_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_CSION)

Definition at line 2319 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_CSI_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_CSION)

Macros to enable or disable the Internal oscillator (CSI).

Note:
The CSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after start-up from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
CSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the CSI.
After enabling the CSI, the application software should wait on CSIRDY flag to be set indicating that CSI clock is stable and can be used as system clock source.
When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator clock cycles.

Definition at line 2318 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_CSISTOP_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)

Definition at line 2340 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_CSISTOP_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_CSIKERON)

Macros to enable or disable the force of the Low-power Internal oscillator (CSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.

Note:
Keeping the CSI ON in STOP mode allows to avoid slowing down the communication speed because of the CSI start-up time.
The enable of this function has not effect on the CSION bit. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2339 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))

Definition at line 1910 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))

Definition at line 1897 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D2SRAM1_CLK_DISABLE ( ) (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))

Definition at line 921 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D2SRAM1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 892 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE ( ) (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))

Definition at line 1966 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE ( ) (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))

Definition at line 1957 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D2SRAM2_CLK_DISABLE ( ) (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))

Definition at line 922 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D2SRAM2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 900 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE ( ) (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))

Definition at line 1967 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE ( ) (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))

Definition at line 1958 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D2SRAM3_CLK_DISABLE ( ) (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))

Definition at line 923 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D2SRAM3_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 908 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE ( ) (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))

Definition at line 1968 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE ( ) (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))

Definition at line 1959 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))

Definition at line 2011 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN))

Definition at line 1993 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D3SRAM1_CLKAM_DISABLE ( ) (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN)

Definition at line 2214 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_D3SRAM1_CLKAM_ENABLE ( ) (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN)

Definition at line 2195 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC12_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)

Definition at line 1367 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC12_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1279 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)

Definition at line 2090 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)

Definition at line 2057 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC12_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST)

Definition at line 1771 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DAC12_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)

Definition at line 1803 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_CLK_DISABLE ( ) (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))

Definition at line 916 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the AHB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 852 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE ( ) (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))

Definition at line 1961 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE ( ) (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))

ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
By default, all peripheral clocks are ENABLEd during SLEEP mode.

Definition at line 1952 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_FORCE_RESET ( ) (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))

Definition at line 1683 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DCMI_RELEASE_RESET ( ) (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST))

Definition at line 1690 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM1_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)

Definition at line 1515 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1486 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)

Definition at line 2135 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)

Definition at line 2119 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM1_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST)

Definition at line 1828 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DFSDM1_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST)

Definition at line 1845 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))

Definition at line 835 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the AHB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 755 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))

Definition at line 1933 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))

ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
By default, all peripheral clocks are ENABLEd during SLEEP mode.

Definition at line 1921 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))

Definition at line 1663 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST))

Definition at line 1672 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))

Definition at line 836 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 763 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))

Definition at line 1934 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))

Definition at line 1922 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))

Definition at line 1664 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST))

Definition at line 1673 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2D_CLK_DISABLE ( ) (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))

Definition at line 741 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2D_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 691 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))

Definition at line 1901 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))

Definition at line 1888 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2D_FORCE_RESET ( ) (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))

Definition at line 1641 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DMA2D_RELEASE_RESET ( ) (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))

Definition at line 1651 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))

Definition at line 1907 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))

Definition at line 1894 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))

Definition at line 1908 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))

Definition at line 1895 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ETH1MAC_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))

Definition at line 838 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ETH1MAC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 779 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))

Definition at line 1936 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))

Definition at line 1924 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ETH1MAC_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST))

Definition at line 1666 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ETH1MAC_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST))

Definition at line 1675 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ETH1PTP_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1PTPLPEN))

Definition at line 1939 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ETH1PTP_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1PTPLPEN))

Definition at line 1927 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ETH1RX_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))

Definition at line 840 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ETH1RX_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 795 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))

Definition at line 1938 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))

Definition at line 1926 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ETH1TX_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))

Definition at line 839 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ETH1TX_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 787 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))

Definition at line 1937 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))

Definition at line 1925 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_CLK_DISABLE ( ) (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)

Definition at line 1374 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1335 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE ( ) (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)

Definition at line 2097 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE ( ) (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)

Definition at line 2064 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_FORCE_RESET ( ) (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST)

Definition at line 1778 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_RELEASE_RESET ( ) (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)

Definition at line 1810 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_DISABLE ( ) (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FLASHEN))

Definition at line 743 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FLASHEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FLASHEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 707 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))

Definition at line 1903 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))

Definition at line 1890 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FMC_CLK_DISABLE ( ) (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))

Definition at line 744 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FMC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 715 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))

Definition at line 1904 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))

Definition at line 1891 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FMC_FORCE_RESET ( ) (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))

Definition at line 1643 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_FMC_RELEASE_RESET ( ) (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))

Definition at line 1653 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GET_HSI_DIVIDER ( ) ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))

Macro to get the HSI divider.

Return values:
The HSI divider. The returned value can be one of the following:
  • RCC_CR_HSIDIV_1 HSI oscillator divided by 1 (default after reset)
  • RCC_CR_HSIDIV_2 HSI oscillator divided by 2
  • RCC_CR_HSIDIV_4 HSI oscillator divided by 4
  • RCC_CR_HSIDIV_8 HSI oscillator divided by 8

Definition at line 2248 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPLL1ClockFreq(), HAL_RCCEx_GetPLL2ClockFreq(), HAL_RCCEx_GetPLL3ClockFreq(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define __HAL_RCC_GET_PLL_OSCSOURCE ( ) ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))

Macro to get the oscillator used as PLL clock source.

Return values:
The oscillator used as PLL clock source. The returned value can be one of the following:
  • RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
  • RCC_PLLSOURCE_CSI: CSI oscillator is used as PLL clock source.
  • RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
  • RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.

Definition at line 2653 of file stm32h7xx_hal_rcc.h.

Referenced by RCCEx_PLL2_Config(), and RCCEx_PLL3_Config().

#define __HAL_RCC_GET_RTC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))

Definition at line 2478 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SYSCLK_SOURCE ( ) ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))

Macro to get the clock source used as system clock.

Return values:
The clock source used as system clock. The returned value can be one of the following:
  • RCC_CFGR_SWS_CSI: CSI used as system clock.
  • RCC_CFGR_SWS_HSI: HSI used as system clock.
  • RCC_CFGR_SWS_HSE: HSE used as system clock.
  • RCC_CFGR_SWS_PLL: PLL used as system clock.

Definition at line 2631 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define __HAL_RCC_GPIOA_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)

Definition at line 1060 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the AHB4 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 931 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)

Definition at line 1995 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)

ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
By default, all peripheral clocks are ENABLEd during SLEEP mode.

Definition at line 1977 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST)

Definition at line 1701 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST)

Definition at line 1719 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)

Definition at line 1061 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 939 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)

Definition at line 1996 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)

Definition at line 1978 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST)

Definition at line 1702 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST)

Definition at line 1720 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)

Definition at line 1062 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 947 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)

Definition at line 1997 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)

Definition at line 1979 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST)

Definition at line 1703 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST)

Definition at line 1721 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)

Definition at line 1063 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 955 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)

Definition at line 1998 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)

Definition at line 1980 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST)

Definition at line 1704 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST)

Definition at line 1722 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)

Definition at line 1064 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 963 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)

Definition at line 1999 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)

Definition at line 1981 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST)

Definition at line 1705 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST)

Definition at line 1723 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)

Definition at line 1065 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 971 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)

Definition at line 2000 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)

Definition at line 1982 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST)

Definition at line 1706 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)

Definition at line 1724 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)

Definition at line 1066 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 979 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)

Definition at line 2001 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)

Definition at line 1983 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST)

Definition at line 1707 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)

Definition at line 1725 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)

Definition at line 1067 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 987 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)

Definition at line 2002 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)

Definition at line 1984 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST)

Definition at line 1708 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)

Definition at line 1726 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOI_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)

Definition at line 1068 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOI_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 995 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)

Definition at line 2003 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)

Definition at line 1985 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOI_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST)

Definition at line 1709 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOI_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST)

Definition at line 1727 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOJ_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)

Definition at line 1069 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOJ_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1003 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)

Definition at line 2004 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)

Definition at line 1986 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOJ_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST)

Definition at line 1710 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOJ_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)

Definition at line 1728 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOK_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)

Definition at line 1070 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOK_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1011 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)

Definition at line 2005 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)

Definition at line 1987 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOK_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST)

Definition at line 1711 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_GPIOK_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)

Definition at line 1729 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HASH_CLK_DISABLE ( ) (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))

Definition at line 918 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HASH_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 868 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE ( ) (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))

Definition at line 1963 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE ( ) (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))

Definition at line 1954 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HASH_FORCE_RESET ( ) (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))

Definition at line 1685 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HASH_RELEASE_RESET ( ) (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST))

Definition at line 1692 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HRTIM1_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)

Definition at line 1516 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HRTIM1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1494 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_HRTIM_Init().

#define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)

Definition at line 2136 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)

Definition at line 2120 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HRTIM1_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST)

Definition at line 1829 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HRTIM1_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST)

Definition at line 1846 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HSE_CONFIG ( __STATE__ )
Value:
do {                                        \
                      if ((__STATE__) == RCC_HSE_ON)            \
                      {                                         \
                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
                      }                                         \
                      else if ((__STATE__) == RCC_HSE_OFF)      \
                      {                                         \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
                      }                                         \
                      else if ((__STATE__) == RCC_HSE_BYPASS)   \
                      {                                         \
                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);        \
                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
                      }                                         \
                      else                                      \
                      {                                         \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
                      }                                         \
                    } while(0)

Macro to configure the External High Speed oscillator (__HSE__).

Note:
After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock.
HSE state can not be changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it).
The HSE is stopped by hardware when entering STOP and STANDBY modes.
This function reset the CSSON bit, so if the clock security system(CSS) was previously enabled you have to enable it again after calling this function.
Parameters:
__STATE__,: specifies the new state of the HSE. This parameter can be one of the following values:
  • RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles.
  • RCC_HSE_ON: turn ON the HSE oscillator.
  • RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.

Definition at line 2373 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSEM_CLK_DISABLE ( ) (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)

Definition at line 1074 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HSEM_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1043 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HSEM_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST)

Definition at line 1716 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HSEM_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST)

Definition at line 1734 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HSI48_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);

Definition at line 2300 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI48_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_HSI48ON);

Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).

Note:
After enabling the HSI48, the application software should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be used to clock the USB.
The HSI48 is stopped by hardware when entering STOP and STANDBY modes.

Definition at line 2298 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST ( __HSICalibrationValue__ ) MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_ICSCR_HSITRIM))

Macro to adjust the Internal High Speed oscillator (HSI) calibration value.

Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC.
Parameters:
__HSICalibrationValue__,: specifies the calibration trimming value. This parameter must be a number between 0 and 0x3F.

Definition at line 2275 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_CONFIG ( __STATE__ ) MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__))

Macro to enable or disable the Internal High Speed oscillator (HSI).

Note:
After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used to clock the PLL and/or system clock.
HSI can not be stopped if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then stop the HSI.
The HSI is stopped by hardware when entering STOP and STANDBY modes.
Parameters:
__STATE__ specifies the new state of the HSI. This parameter can be one of the following values:
  • RCC_HSI_OFF turn OFF the HSI oscillator
  • RCC_HSI_ON turn ON the HSI oscillator
  • RCC_HSI_DIV1 turn ON the HSI oscillator and divide it by 1 (default after reset)
  • RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2
  • RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4
  • RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8
Note:
When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.

Definition at line 2236 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_HSION)

Definition at line 2266 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_HSION)

Macros to enable or disable the Internal High Speed oscillator (HSI).

Note:
The HSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after start-up from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
HSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the HSI.
After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used as system clock source. This parameter can be: ENABLE or DISABLE.
When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.

Definition at line 2265 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HSISTOP_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)

Definition at line 2288 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_HSISTOP_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_HSIKERON)

Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for some peripherals.

Note:
Keeping the HSI ON in STOP mode allows to avoid slowing down the communication speed because of the HSI start-up time.
The enable of this function has not effect on the HSION bit. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2287 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)

Definition at line 1363 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1247 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)

Definition at line 2086 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)

Definition at line 2053 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C1_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST)

Definition at line 1767 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C1_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)

Definition at line 1799 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)

Definition at line 1364 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1255 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)

Definition at line 2087 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)

Definition at line 2054 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C2_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST)

Definition at line 1768 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C2_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)

Definition at line 1800 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)

Definition at line 1365 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1263 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)

Definition at line 2088 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)

Definition at line 2055 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C3_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST)

Definition at line 1769 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C3_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)

Definition at line 1801 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C4_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)

Definition at line 1624 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C4_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1548 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)

Definition at line 2162 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)

Definition at line 2148 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C4_CLKAM_DISABLE ( ) (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN)

Definition at line 2200 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C4_CLKAM_ENABLE ( ) (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN)

Definition at line 2181 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C4_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST)

Definition at line 1855 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_I2C4_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST)

Definition at line 1869 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))

Definition at line 1909 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))

Definition at line 1896 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))

Definition at line 1902 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))

Definition at line 1889 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_JPGDECEN_CLK_DISABLE ( ) (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))

Definition at line 742 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_JPGDECEN_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 699 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_JPGDECRST_FORCE_RESET ( ) (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST))

Definition at line 1642 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_JPGDECRST_RELEASE_RESET ( ) (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST))

Definition at line 1652 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG ( __RCC_STOPKERWUCLK__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))

Macro to configure the Kernel wake up from stop clock.

Parameters:
__RCC_STOPKERWUCLK__,: specifies the Kernel clock source used after wake up from stop This parameter can be one of the following values:
  • RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source
  • RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source
Return values:
None

Definition at line 2690 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_KerWakeUpStopCLKConfig().

#define __HAL_RCC_LPTIM1_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)

Definition at line 1353 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1182 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)

Definition at line 2076 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)

Definition at line 2043 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST)

Definition at line 1759 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST)

Definition at line 1791 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)

Definition at line 1625 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1556 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)

Definition at line 2163 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)

Definition at line 2149 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLKAM_DISABLE ( ) (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN)

Definition at line 2201 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLKAM_ENABLE ( ) (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN)

Definition at line 2182 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST)

Definition at line 1856 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST)

Definition at line 1870 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM3_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)

Definition at line 1626 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM3_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1564 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)

Definition at line 2164 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)

Definition at line 2150 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM3_CLKAM_DISABLE ( ) (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN)

Definition at line 2202 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM3_CLKAM_ENABLE ( ) (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN)

Definition at line 2183 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM3_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST)

Definition at line 1857 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM3_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST)

Definition at line 1871 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM4_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)

Definition at line 1627 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM4_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1572 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)

Definition at line 2165 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)

Definition at line 2151 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM4_CLKAM_DISABLE ( ) (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN)

Definition at line 2203 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM4_CLKAM_ENABLE ( ) (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN)

Definition at line 2184 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM4_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST)

Definition at line 1858 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM4_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST)

Definition at line 1872 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM5_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)

Definition at line 1628 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM5_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1580 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)

Definition at line 2166 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)

Definition at line 2152 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM5_CLKAM_DISABLE ( ) (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN)

Definition at line 2204 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM5_CLKAM_ENABLE ( ) (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN)

Definition at line 2185 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM5_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST)

Definition at line 1859 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPTIM5_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST)

Definition at line 1873 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)

Definition at line 1622 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1532 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)

Definition at line 2160 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)

Definition at line 2146 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLKAM_DISABLE ( ) (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN)

Definition at line 2198 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLKAM_ENABLE ( ) (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN)

Definition at line 2179 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST)

Definition at line 1853 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST)

Definition at line 1867 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LSEDRIVE_CONFIG ( __LSEDRIVE__ ) MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))

Macro to configure the External Low Speed oscillator (LSE) drive capability.

Note:
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
Parameters:
__LSEDRIVE__,: specifies the new state of the LSE drive capability. This parameter can be one of the following values:
  • RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
  • RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
  • RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
  • RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
Return values:
None

Definition at line 2669 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LSI_DISABLE ( ) CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)

Definition at line 2352 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_LSI_ENABLE ( ) SET_BIT(RCC->CSR, RCC_CSR_LSION)

Macros to enable or disable the Internal Low Speed oscillator (LSI).

Note:
After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.
LSI can not be disabled if the IWDG is running.
When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.

Definition at line 2351 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_LTDC_CLK_DISABLE ( ) (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)

Definition at line 1101 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LTDC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the APB3 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1084 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE ( ) (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)

Definition at line 2023 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE ( ) (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)

ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
By default, all peripheral clocks are ENABLEd during SLEEP mode.

Definition at line 2020 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LTDC_FORCE_RESET ( ) (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST)

Definition at line 1740 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_LTDC_RELEASE_RESET ( ) (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST)

Definition at line 1743 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDIOS_CLK_DISABLE ( ) (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)

Definition at line 1373 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDIOS_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1327 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE ( ) (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)

Definition at line 2096 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE ( ) (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)

Definition at line 2063 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDIOS_FORCE_RESET ( ) (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST)

Definition at line 1777 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDIOS_RELEASE_RESET ( ) (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)

Definition at line 1809 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDMA_CLK_DISABLE ( ) (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))

Definition at line 740 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDMA_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the AHB3 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 683 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))

Definition at line 1900 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))

Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 1887 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDMA_FORCE_RESET ( ) (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))

Definition at line 1640 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_MDMA_RELEASE_RESET ( ) (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))

Definition at line 1650 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_CLK_DISABLE ( ) (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)

Definition at line 1372 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1319 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE ( ) (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)

Definition at line 2095 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE ( ) (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)

Definition at line 2062 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_FORCE_RESET ( ) (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST)

Definition at line 1776 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_RELEASE_RESET ( ) (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)

Definition at line 1808 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_PLL_CONFIG | ( | __RCC_PLLSOURCE__,
 |  | __PLLM1__,
 |  | __PLLN1__,
 |  | __PLLP1__,
 |  | __PLLQ1__,
 |  | __PLLR1__
 | ) |
Value:
do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U)));  \
                      WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \
                                ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \
                    } while(0)

Macro to configures the main PLL clock source, multiplication and division factors.

Note:
This function must be used only when the main PLL is disabled.
Parameters:
__RCC_PLLSOURCE__,: specifies the PLL entry clock source. This parameter can be one of the following values:
  • RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Note:
This clock source (__RCC_PLLSource__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 .
Parameters:
__PLLM1__,: specifies the division factor for PLL VCO input clock This parameter must be a number between 1 and 63.
Note:
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 16 MHz.
Parameters:
__PLLN1__,: specifies the multiplication factor for PLL VCO output clock This parameter must be a number between 4 and 512.
Note:
You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 150 and 420 MHz (when in medium VCO range) or between 192 and 836 MHZ (when in wide VCO range)
Parameters:
__PLLP1__,: specifies the division factor for system clock. This parameter must be a number between 2 and 128 (where odd numbers not allowed)
__PLLQ1__,: specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128
__PLLR1__,: specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128
Return values:
None

Definition at line 2561 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)

Definition at line 2497 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_PLL1ON)

Macros to enable or disable the main PLL.

Note:
After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.
The main PLL can not be disabled if it is used as system clock source
The main PLL is disabled by hardware when entering STOP and STANDBY modes.

Definition at line 2496 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_PLLSOURCE_CONFIG ( __PLLSOURCE__ ) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))

Macro to configure the PLLs clock source.

Note:
This function must be used only when all PLLs are disabled.
Parameters:
__PLLSOURCE__,: specifies the PLLs entry clock source. This parameter can be one of the following values:
  • RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry

Definition at line 2577 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_PLL_VCIRANGE ( __RCC_PLL1VCIRange__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))

Macro to select the PLL1 reference frequency range.

Parameters:
__RCC_PLL1VCIRange__,: specifies the PLL1 input frequency range This parameter can be one of the following values:
  • RCC_PLL1VCIRANGE_0: Range frequency is between 1 and 2 MHz
  • RCC_PLL1VCIRANGE_1: Range frequency is between 2 and 4 MHz
  • RCC_PLL1VCIRANGE_2: Range frequency is between 4 and 8 MHz
  • RCC_PLL1VCIRANGE_3: Range frequency is between 8 and 16 MHz
Return values:
None

Definition at line 2607 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_VCORANGE ( __RCC_PLL1VCORange__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))

Macro to select the PLL1 reference frequency range.

Parameters:
__RCC_PLL1VCORange__,: specifies the PLL1 input frequency range This parameter can be one of the following values:
  • RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz
  • RCC_PLL1VCOMEDIUM: Range frequency is between 150 and 420 MHz
Return values:
None

Definition at line 2618 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLLCLKOUT_DISABLE ( __RCC_PLL1ClockOut__ ) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))

Definition at line 2513 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_PLLCLKOUT_ENABLE ( __RCC_PLL1ClockOut__ ) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))

Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)

Note:
Enabling/disabling Those Clocks can be any time without the need to stop the PLL, (except the ck_pll_p of the System PLL that cannot be stopped if used as System Clock.This is mainly used to save Power.
Parameters:
__RCC_PLL1ClockOut__,: specifies the PLL clock to be outputted This parameter can be one of the following values:
  • RCC_PLL1_DIVP: This clock is used to generate system clock (up to 400MHZ)
  • RCC_PLL1_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ)
  • RCC_PLL1_DIVR: This clock is used to generate peripherals clock (up to 400MHZ)
Return values:
None

Definition at line 2511 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLFRACN_CONFIG ( __RCC_PLL1FRACN__ ) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << POSITION_VAL(RCC_PLL1FRACR_FRACN1))

Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor.

Note:
These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO
Parameters:
__RCC_PLL1FRACN__,: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO It should be a value between 0 and 8191
Note:
Warning: The software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: 192 to 836 MHz if PLL1VCOSEL = 0 150 to 420 MHz if PLL1VCOSEL = 1.
Return values:
None

Definition at line 2595 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLLFRACN_DISABLE ( ) CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)

Definition at line 2523 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_PLLFRACN_ENABLE ( ) SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)

Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO.

Note:
Enabling/disabling Fractional Part can be any time without the need to stop the PLL1
Return values:
None

Definition at line 2521 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE ( ) (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_PWRLPEN)

Definition at line 2006 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_PWRLPEN)

Definition at line 1988 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_PWR_FORCE_RESET ( ) (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_PWRRST)

Definition at line 1712 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_PWR_RELEASE_RESET ( ) (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_PWRRST)

Definition at line 1730 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_QSPI_CLK_DISABLE ( ) (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))

Definition at line 745 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_QSPI_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 723 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))

Definition at line 1905 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))

Definition at line 1892 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_QSPI_FORCE_RESET ( ) (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))

Definition at line 1644 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_QSPI_RELEASE_RESET ( ) (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST))

Definition at line 1654 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_DISABLE ( ) (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))

Definition at line 919 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 876 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE ( ) (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))

Definition at line 1964 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE ( ) (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))

Definition at line 1955 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RNG_FORCE_RESET ( ) (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))

Definition at line 1686 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RNG_RELEASE_RESET ( ) (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))

Definition at line 1693 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)

Definition at line 1631 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1612 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)

Definition at line 2169 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)

Definition at line 2155 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_CLKAM_DISABLE ( ) (RCC->D3AMR) &= ~(RCC_D3AMR_RTCAMEN)

Definition at line 2207 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_CLKAM_ENABLE ( ) (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN)

Definition at line 2188 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_CLKPRESCALER ( __RTCCLKSource__ )
Value:
(((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \
                                                 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFF) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)

Macros to configure the RTC clock (RTCCLK).

Note:
As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using the Power Backup Access macro before to configure the RTC clock source (to be done once after reset).
Once the RTC clock is configured it can't be changed unless the Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by a Power On Reset (POR).
Parameters:
__RTCCLKSource__,: specifies the RTC clock source. This parameter can be one of the following values:
  • RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
  • RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
  • RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected as RTC clock, where x:[2,31]
Note:
If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.
The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).

Definition at line 2471 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_CONFIG ( __RTCCLKSource__ )
Value:
do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF);  \
                                                   } while (0)

Definition at line 2474 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_RTC_DISABLE ( ) CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)

Definition at line 2448 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_RTC_ENABLE ( ) SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)

Macros to enable or disable the the RTC clock.

Note:
These macros must be used only after the RTC clock source was selected.

Definition at line 2447 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI1_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)

Definition at line 1512 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1462 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)

Definition at line 2132 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)

Definition at line 2116 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI1_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST)

Definition at line 1825 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI1_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)

Definition at line 1842 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI2_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)

Definition at line 1513 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1470 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)

Definition at line 2133 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)

Definition at line 2117 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI2_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST)

Definition at line 1826 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI2_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST)

Definition at line 1843 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI3_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)

Definition at line 1514 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI3_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1478 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)

Definition at line 2134 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)

Definition at line 2118 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI3_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST)

Definition at line 1827 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI3_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST)

Definition at line 1844 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI4_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)

Definition at line 1632 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI4_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1604 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)

Definition at line 2170 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)

Definition at line 2156 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI4_CLKAM_DISABLE ( ) (RCC->D3AMR) &= ~(RCC_D3AMR_SAI4AMEN)

Definition at line 2209 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI4_CLKAM_ENABLE ( ) (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN)

Definition at line 2190 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI4_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST)

Definition at line 1862 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SAI4_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST)

Definition at line 1876 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_CLK_DISABLE ( ) (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))

Definition at line 746 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 731 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))

Definition at line 1906 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))

Definition at line 1893 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_FORCE_RESET ( ) (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST))

Definition at line 1645 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_RELEASE_RESET ( ) (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))

Definition at line 1655 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC2_CLK_DISABLE ( ) (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))

Definition at line 920 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 884 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE ( ) (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))

Definition at line 1965 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE ( ) (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))

Definition at line 1956 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC2_FORCE_RESET ( ) (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))

Definition at line 1687 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SDMMC2_RELEASE_RESET ( ) (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))

Definition at line 1694 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPDIFRX_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)

Definition at line 1358 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPDIFRX_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1207 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)

Definition at line 2081 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)

Definition at line 2048 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPDIFRX_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST)

Definition at line 1762 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPDIFRX_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST)

Definition at line 1794 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)

Definition at line 1506 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1414 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)

Definition at line 2126 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)

Definition at line 2110 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI1_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST)

Definition at line 1819 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI1_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST)

Definition at line 1836 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)

Definition at line 1356 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1191 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)

Definition at line 2079 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)

Definition at line 2046 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI2_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST)

Definition at line 1760 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI2_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST)

Definition at line 1792 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI3_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)

Definition at line 1357 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI3_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1199 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)

Definition at line 2080 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)

Definition at line 2047 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI3_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST)

Definition at line 1761 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI3_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST)

Definition at line 1793 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI4_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)

Definition at line 1507 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI4_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1422 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)

Definition at line 2127 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)

Definition at line 2111 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI4_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST)

Definition at line 1820 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI4_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST)

Definition at line 1837 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI5_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)

Definition at line 1511 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI5_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1454 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)

Definition at line 2131 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)

Definition at line 2115 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI5_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST)

Definition at line 1824 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI5_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)

Definition at line 1841 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI6_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)

Definition at line 1623 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI6_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1540 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)

Definition at line 2161 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)

Definition at line 2147 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI6_CLKAM_DISABLE ( ) (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN)

Definition at line 2199 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI6_CLKAM_ENABLE ( ) (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN)

Definition at line 2180 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI6_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST)

Definition at line 1854 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SPI6_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST)

Definition at line 1868 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_CLK_DISABLE ( ) (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)

Definition at line 1371 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1311 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE ( ) (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)

Definition at line 2094 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE ( ) (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)

Definition at line 2061 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_FORCE_RESET ( ) (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST)

Definition at line 1775 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_RELEASE_RESET ( ) (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST)

Definition at line 1807 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)

Definition at line 1621 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the APB4 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1524 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_ETH_Init(), HAL_GPIO_Init(), HAL_I2CEx_DisableFastModePlus(), and HAL_I2CEx_EnableFastModePlus().

#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)

Definition at line 2159 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)

ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
By default, all peripheral clocks are ENABLEd during SLEEP mode.

Definition at line 2145 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST)

Definition at line 1852 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST)

Definition at line 1866 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_SYSCLK_CONFIG ( __RCC_SYSCLKSOURCE__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))

Macro to configure the system clock source.

Parameters:
__RCC_SYSCLKSOURCE__,: specifies the system clock source. This parameter can be one of the following values:
  • RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.

Definition at line 2643 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM12_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)

Definition at line 1350 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM12_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1158 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)

Definition at line 2073 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)

Definition at line 2040 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM12_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST)

Definition at line 1756 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM12_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST)

Definition at line 1788 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM13_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)

Definition at line 1351 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM13_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1166 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)

Definition at line 2074 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)

Definition at line 2041 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM13_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST)

Definition at line 1757 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM13_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST)

Definition at line 1789 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM14_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)

Definition at line 1352 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM14_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1174 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)

Definition at line 2075 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)

Definition at line 2042 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM14_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST)

Definition at line 1758 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM14_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST)

Definition at line 1790 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM15_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)

Definition at line 1508 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM15_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1430 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)

Definition at line 2128 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)

Definition at line 2112 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM15_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST)

Definition at line 1821 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM15_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST)

Definition at line 1838 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)

Definition at line 1509 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1438 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)

Definition at line 2129 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)

Definition at line 2113 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM16_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST)

Definition at line 1822 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM16_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST)

Definition at line 1839 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)

Definition at line 1510 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1446 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)

Definition at line 2130 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)

Definition at line 2114 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM17_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST)

Definition at line 1823 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM17_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)

Definition at line 1840 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)

Definition at line 1502 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the APB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1382 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)

Definition at line 2122 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)

ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
By default, all peripheral clocks are ENABLEd during SLEEP mode.

Definition at line 2106 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM1_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST)

Definition at line 1815 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM1_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST)

Definition at line 1832 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)

Definition at line 1344 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the APB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1110 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)

Definition at line 2067 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)

ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
By default, all peripheral clocks are ENABLEd during SLEEP mode.

Definition at line 2034 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM2_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST)

Definition at line 1750 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM2_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST)

Definition at line 1782 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)

Definition at line 1345 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1118 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)

Definition at line 2068 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)

Definition at line 2035 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM3_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST)

Definition at line 1751 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM3_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST)

Definition at line 1783 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM4_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)

Definition at line 1346 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM4_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1126 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)

Definition at line 2069 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)

Definition at line 2036 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM4_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST)

Definition at line 1752 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM4_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST)

Definition at line 1784 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM5_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)

Definition at line 1347 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM5_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1134 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)

Definition at line 2070 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)

Definition at line 2037 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM5_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST)

Definition at line 1753 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM5_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST)

Definition at line 1785 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)

Definition at line 1348 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1142 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)

Definition at line 2071 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)

Definition at line 2038 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM6_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST)

Definition at line 1754 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM6_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST)

Definition at line 1786 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM7_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)

Definition at line 1349 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM7_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1150 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)

Definition at line 2072 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)

Definition at line 2039 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM7_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST)

Definition at line 1755 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM7_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST)

Definition at line 1787 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM8_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)

Definition at line 1503 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM8_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1390 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)

Definition at line 2123 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)

Definition at line 2107 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM8_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST)

Definition at line 1816 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_TIM8_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST)

Definition at line 1833 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART4_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)

Definition at line 1361 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART4_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1231 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)

Definition at line 2084 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)

Definition at line 2051 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART4_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST)

Definition at line 1765 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART4_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST)

Definition at line 1797 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART5_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)

Definition at line 1362 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART5_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1239 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)

Definition at line 2085 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)

Definition at line 2052 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART5_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST)

Definition at line 1766 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART5_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST)

Definition at line 1798 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART7_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)

Definition at line 1368 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART7_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1287 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)

Definition at line 2091 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)

Definition at line 2058 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART7_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST)

Definition at line 1772 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART7_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)

Definition at line 1804 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART8_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)

Definition at line 1369 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART8_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1295 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)

Definition at line 2092 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)

Definition at line 2059 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART8_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST)

Definition at line 1773 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_UART8_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST)

Definition at line 1805 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)

Definition at line 1504 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1398 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)

Definition at line 2124 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)

Definition at line 2108 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART1_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST)

Definition at line 1817 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART1_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST)

Definition at line 1834 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)

Definition at line 1359 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1215 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)

Definition at line 2082 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)

Definition at line 2049 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART2_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST)

Definition at line 1763 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART2_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)

Definition at line 1795 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_DISABLE ( ) (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)

Definition at line 1360 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1223 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE ( ) (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)

Definition at line 2083 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)

Definition at line 2050 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART3_FORCE_RESET ( ) (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST)

Definition at line 1764 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART3_RELEASE_RESET ( ) (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST)

Definition at line 1796 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART6_CLK_DISABLE ( ) (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)

Definition at line 1505 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART6_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1406 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)

Definition at line 2125 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)

Definition at line 2109 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART6_FORCE_RESET ( ) (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST)

Definition at line 1818 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USART6_RELEASE_RESET ( ) (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST)

Definition at line 1835 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))

Definition at line 841 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 803 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))

Definition at line 1940 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))

Definition at line 1928 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST))

Definition at line 1667 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST))

Definition at line 1676 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))

Definition at line 842 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 811 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))

Definition at line 1941 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))

Definition at line 1929 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB2_OTG_FS_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))

Definition at line 843 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 819 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))

Definition at line 1942 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))

Definition at line 1930 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB2_OTG_FS_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST))

Definition at line 1668 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB2_OTG_FS_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST))

Definition at line 1677 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))

Definition at line 844 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 827 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))

Definition at line 1943 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))

Definition at line 1931 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_VREF_CLK_DISABLE ( ) (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)

Definition at line 1630 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_VREF_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1596 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE ( ) (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)

Definition at line 2168 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)

Definition at line 2154 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_VREF_CLKAM_DISABLE ( ) (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN)

Definition at line 2206 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_VREF_CLKAM_ENABLE ( ) (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN)

Definition at line 2187 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_VREF_FORCE_RESET ( ) (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST)

Definition at line 1861 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_VREF_RELEASE_RESET ( ) (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST)

Definition at line 1875 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG ( __RCC_STOPWUCLK__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))

Macro to configure the wake up from stop clock.

Parameters:
__RCC_STOPWUCLK__,: specifies the clock source used after wake up from stop This parameter can be one of the following values:
  • RCC_STOP_WAKEUPCLOCK_CSI: CSI selected as system clock source
  • RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
Return values:
None

Definition at line 2679 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCCEx_WakeUpStopCLKConfig().

#define __HAL_RCC_WWDG1_CLK_DISABLE ( ) (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)

Definition at line 1102 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_WWDG1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Definition at line 1093 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE ( ) (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)

Definition at line 2025 of file stm32h7xx_hal_rcc.h.

#define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE ( ) (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)

Definition at line 2021 of file stm32h7xx_hal_rcc.h.

#define RCC_GET_PLL_OSCSOURCE ( ) ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> POSITION_VAL(RCC_PLLCKSELR_PLLSRC))

Definition at line 2809 of file stm32h7xx_hal_rcc.h.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC Private Constants

Defines
RCC Private Constants
RCC

Defines

#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define | HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define | HSI48_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define | CSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define | LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define | PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define | CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
#define | RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
#define | RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT

Define Documentation

#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */

Definition at line 2874 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define CSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */

Definition at line 2871 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT

Definition at line 2868 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define HSI48_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */

Definition at line 2870 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */

Definition at line 2869 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */

Definition at line 2872 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */

Definition at line 2873 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)

Definition at line 2875 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT

Definition at line 2876 of file stm32h7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Private Defines

Defines
Private Defines
RCCEx

Defines

#define | PLL2_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define | PLL3_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define | PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */

Define Documentation

#define PLL2_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */

Definition at line 61 of file stm32h7xx_hal_rcc_ex.c.

Referenced by RCCEx_PLL2_Config().

#define PLL3_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */

Definition at line 62 of file stm32h7xx_hal_rcc_ex.c.

Referenced by RCCEx_PLL3_Config().

#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */

Definition at line 63 of file stm32h7xx_hal_rcc_ex.c.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC Private macros to check input parameters

Defines
RCC Private macros to check input parameters
RCCEx Private Macros

Defines

#define | IS_RCC_PERIPHCLOCK(SELECTION)
#define | IS_RCC_PLL2CLOCKOUT_VALUE(VALUE)
#define | IS_RCC_PLL3CLOCKOUT_VALUE(VALUE)
#define | IS_RCC_USART1CLKSOURCE(SOURCE)
#define | IS_RCC_USART2CLKSOURCE(SOURCE)
#define | IS_RCC_USART3CLKSOURCE(SOURCE)
#define | IS_RCC_UART4CLKSOURCE(SOURCE)
#define | IS_RCC_UART5CLKSOURCE(SOURCE)
#define | IS_RCC_USART6CLKSOURCE(SOURCE)
#define | IS_RCC_UART7CLKSOURCE(SOURCE)
#define | IS_RCC_UART8CLKSOURCE(SOURCE)
#define | IS_RCC_LPUART1CLKSOURCE(SOURCE)
#define | IS_RCC_I2C1CLKSOURCE(SOURCE)
#define | IS_RCC_I2C2CLKSOURCE(SOURCE)
#define | IS_RCC_I2C3CLKSOURCE(SOURCE)
#define | IS_RCC_I2C4CLKSOURCE(SOURCE)
#define | IS_RCC_RNGCLKSOURCE(SOURCE)
#define | IS_RCC_HRTIM1CLKSOURCE(SOURCE)
#define | IS_RCC_USBCLKSOURCE(SOURCE)
#define | IS_RCC_USBCLKSOURCE(SOURCE)
#define | IS_RCC_SAI1CLK(__SOURCE__)
#define | IS_RCC_SAI2CLK(__SOURCE__)
#define | IS_RCC_SPI1CLK(__SOURCE__)
#define | IS_RCC_SPI2CLK(__SOURCE__)
#define | IS_RCC_SPI3CLK(__SOURCE__)
#define | IS_RCC_SPI4CLK(__SOURCE__)
#define | IS_RCC_SPI5CLK(__SOURCE__)
#define | IS_RCC_SPI6CLK(__SOURCE__)
#define | IS_RCC_SAI3CLK(__SOURCE__)
#define | IS_RCC_SAI4ACLK(__SOURCE__)
#define | IS_RCC_SAI4BCLK(__SOURCE__)
#define | IS_RCC_PLL3M_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 63))
#define | IS_RCC_PLL3N_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512))
#define | IS_RCC_PLL3P_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
#define | IS_RCC_PLL3Q_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
#define | IS_RCC_PLL3R_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
#define | IS_RCC_PLL2M_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 63))
#define | IS_RCC_PLL2N_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512))
#define | IS_RCC_PLL2P_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
#define | IS_RCC_PLL2Q_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
#define | IS_RCC_PLL2R_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
#define | IS_RCC_LPTIM1CLK(SOURCE)
#define | IS_RCC_LPTIM2CLK(SOURCE)
#define | IS_RCC_LPTIM3CLK(SOURCE)
#define | IS_RCC_LPTIM4CLK(SOURCE)
#define | IS_RCC_LPTIM5CLK(SOURCE)
#define | IS_RCC_QSPICLK(__SOURCE__)
#define | IS_RCC_FMCCLK(__SOURCE__)
#define | IS_RCC_FDCANCLK(__SOURCE__)
#define | IS_RCC_SDMMC(__SOURCE__)
#define | IS_RCC_ADCCLKSOURCE(SOURCE)
#define | IS_RCC_SWPMI1CLKSOURCE(SOURCE)
#define | IS_RCC_DFSDM1CLKSOURCE(SOURCE)
#define | IS_RCC_SPDIFRXCLKSOURCE(SOURCE)
#define | IS_RCC_CECCLKSOURCE(SOURCE)
#define | IS_RCC_CLKPSOURCE(SOURCE)
#define | IS_RCC_TIMPRES(VALUE)
#define | IS_RCC_SCOPE_WWDG(WWDG) ((WWDG) == RCC_WWDG1)
#define | IS_RCC_CRS_SYNC_SOURCE(__SOURCE__)
#define | IS_RCC_CRS_SYNC_DIV(__DIV__)
#define | IS_RCC_CRS_SYNC_POLARITY(__POLARITY__)
#define | IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
#define | IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
#define | IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
#define | IS_RCC_CRS_FREQERRORDIR(__DIR__)

Define Documentation

#define IS_RCC_ADCCLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \
                                        ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \
                                        ((SOURCE) == RCC_ADCCLKSOURCE_CLKP))

Definition at line 2920 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_CECCLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_CECCLKSOURCE_LSE) || \
                                      ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \
                                      ((SOURCE) == RCC_CECCLKSOURCE_CSI))

Definition at line 2935 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_CLKPSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_CLKPSOURCE_HSI)  || \
                                      ((SOURCE) == RCC_CLKPSOURCE_CSI) || \
                                      ((SOURCE) == RCC_CLKPSOURCE_HSE))

Definition at line 2939 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_CRS_ERRORLIMIT ( __VALUE__ ) (((__VALUE__) <= 0xFFU))

Definition at line 2964 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_FREQERRORDIR ( __DIR__ )
Value:
(((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
                                            ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))

Definition at line 2968 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_CRS_HSI48CALIBRATION ( __VALUE__ ) (((__VALUE__) <= 0x3FU))

Definition at line 2966 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_RELOADVALUE ( __VALUE__ ) (((__VALUE__) <= 0xFFFFU))

Definition at line 2962 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_SYNC_DIV ( __DIV__ )
Value:
(((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \
                                            ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \
                                            ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
                                            ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))

Definition at line 2954 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_SYNC_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
                                                ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))

Definition at line 2959 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_SYNC_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \
                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1))

Definition at line 2950 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_DFSDM1CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \
                                        ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS))

Definition at line 2927 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_FDCANCLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)  || \
                ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL)  || \
                ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2))

Definition at line 2906 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_FMCCLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK)  || \
                ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL)     || \
                ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2)    || \
                ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP))

Definition at line 2899 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_HRTIM1CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \
                                        ((SOURCE) == RCC_HRTIM1CLK_CPUCLK))

Definition at line 2758 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2C1CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_I2C1CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)    || \
                                        ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \
                                        ((SOURCE) == RCC_I2C1CLKSOURCE_CSI))

Definition at line 2733 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2C2CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_I2C2CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_I2C2CLKSOURCE_HSI)    || \
                                        ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \
                                        ((SOURCE) == RCC_I2C2CLKSOURCE_CSI))

Definition at line 2738 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2C3CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_I2C3CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_I2C3CLKSOURCE_HSI)    || \
                                        ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \
                                        ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))

Definition at line 2743 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2C4CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_I2C4CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)    || \
                                        ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \
                                        ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))

Definition at line 2748 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LPTIM1CLK ( SOURCE )
Value:
(((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \
                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2)   || \
                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)    || \
                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI)    || \
                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP))

Definition at line 2857 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_LPTIM2CLK ( SOURCE )
Value:
(((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \
                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2)   || \
                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE)    || \
                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI)    || \
                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP))

Definition at line 2864 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_LPTIM3CLK ( SOURCE )
Value:
(((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1)|| \
                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2)   || \
                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE)    || \
                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI)    || \
                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP))

Definition at line 2871 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_LPTIM4CLK ( SOURCE )
Value:
(((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \
                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2)   || \
                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE)    || \
                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI)    || \
                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP))

Definition at line 2878 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_LPTIM5CLK ( SOURCE )
Value:
(((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \
                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2)   || \
                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE)    || \
                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI)    || \
                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP))

Definition at line 2885 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_LPUART1CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \
                                        ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2)     || \
                                        ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3)     || \
                                        ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI)      || \
                                        ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE)      || \
                                        ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))

Definition at line 2726 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_PERIPHCLOCK ( SELECTION )

Definition at line 2617 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_PLL2CLOCKOUT_VALUE ( VALUE )
Value:
(((VALUE) == RCC_PLL2_DIVP) || \
                                         ((VALUE) == RCC_PLL2_DIVQ)  || \
                                         ((VALUE) == RCC_PLL2_DIVR))

Definition at line 2662 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_PLL2M_VALUE ( VALUE ) ((1 <= (VALUE)) && ((VALUE) <= 63))

Definition at line 2851 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define IS_RCC_PLL2N_VALUE ( VALUE ) ((4 <= (VALUE)) && ((VALUE) <= 512))

Definition at line 2852 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define IS_RCC_PLL2P_VALUE ( VALUE ) ((1 <= (VALUE)) && ((VALUE) <= 128))

Definition at line 2853 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define IS_RCC_PLL2Q_VALUE ( VALUE ) ((1 <= (VALUE)) && ((VALUE) <= 128))

Definition at line 2854 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define IS_RCC_PLL2R_VALUE ( VALUE ) ((1 <= (VALUE)) && ((VALUE) <= 128))

Definition at line 2855 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define IS_RCC_PLL3CLOCKOUT_VALUE ( VALUE )
Value:
(((VALUE) == RCC_PLL3_DIVP) || \
                                          ((VALUE) == RCC_PLL3_DIVQ) || \
                                          ((VALUE) == RCC_PLL3_DIVR))

Definition at line 2666 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_PLL3M_VALUE ( VALUE ) ((1 <= (VALUE)) && ((VALUE) <= 63))

Definition at line 2845 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define IS_RCC_PLL3N_VALUE ( VALUE ) ((4 <= (VALUE)) && ((VALUE) <= 512))

Definition at line 2846 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define IS_RCC_PLL3P_VALUE ( VALUE ) ((1 <= (VALUE)) && ((VALUE) <= 128))

Definition at line 2847 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define IS_RCC_PLL3Q_VALUE ( VALUE ) ((1 <= (VALUE)) && ((VALUE) <= 128))

Definition at line 2848 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define IS_RCC_PLL3R_VALUE ( VALUE ) ((1 <= (VALUE)) && ((VALUE) <= 128))

Definition at line 2849 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define IS_RCC_QSPICLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK)  || \
                ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL)     || \
                ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2)    || \
                ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP))

Definition at line 2892 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_RNGCLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \
                                        ((SOURCE) == RCC_RNGCLKSOURCE_PLL)  || \
                                        ((SOURCE) == RCC_RNGCLKSOURCE_LSE)  || \
                                        ((SOURCE) == RCC_RNGCLKSOURCE_LSI))

Definition at line 2753 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SAI1CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)  || \
                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \
                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \
                ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \
                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))

Definition at line 2765 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SAI2CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL)  || \
                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \
                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \
                ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \
                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))

Definition at line 2772 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SAI3CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL)  || \
                ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \
                ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \
                ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \
                ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN))

Definition at line 2824 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SAI4ACLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL)  || \
                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \
                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \
                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \
                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN))

Definition at line 2831 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SAI4BCLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL)  || \
                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \
                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \
                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \
                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN))

Definition at line 2838 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SCOPE_WWDG ( WWDG ) ((WWDG) == RCC_WWDG1)

Definition at line 2947 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_WWDGxSysResetConfig().

#define IS_RCC_SDMMC ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL)  || \
                ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2))

Definition at line 2912 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_SPDIFRXCLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL)  || \
                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \
                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \
                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI))

Definition at line 2930 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SPI1CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL)  || \
                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \
                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \
                ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \
                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN))

Definition at line 2779 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SPI2CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL)  || \
                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \
                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \
                ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \
                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN))

Definition at line 2786 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SPI3CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL)  || \
                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \
                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \
                ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \
                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))

Definition at line 2793 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SPI4CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1)  || \
                ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2)     || \
                ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3)     || \
                ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI)      || \
                ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI)      || \
                ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))

Definition at line 2800 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SPI5CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)|| \
                ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2)   || \
                ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3)   || \
                ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI)    || \
                ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI)    || \
                ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE))

Definition at line 2808 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SPI6CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \
                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2)    || \
                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3)    || \
                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI)     || \
                ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI)     || \
                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE))

Definition at line 2816 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_SWPMI1CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \
                                        ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI))

Definition at line 2924 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_TIMPRES ( VALUE )
Value:
(((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
                ((VALUE) == RCC_TIMPRES_ACTIVATED))

Definition at line 2942 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_UART4CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \
                                        ((SOURCE) == RCC_UART4CLKSOURCE_PLL2)   || \
                                        ((SOURCE) == RCC_UART4CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_UART4CLKSOURCE_CSI)    || \
                                        ((SOURCE) == RCC_UART4CLKSOURCE_LSE)    || \
                                        ((SOURCE) == RCC_UART4CLKSOURCE_HSI))

Definition at line 2691 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_UART5CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \
                                        ((SOURCE) == RCC_UART5CLKSOURCE_PLL2)   || \
                                        ((SOURCE) == RCC_UART5CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_UART5CLKSOURCE_CSI)    || \
                                        ((SOURCE) == RCC_UART5CLKSOURCE_LSE)    || \
                                        ((SOURCE) == RCC_UART5CLKSOURCE_HSI))

Definition at line 2698 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_UART7CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1)|| \
                                        ((SOURCE) == RCC_UART7CLKSOURCE_PLL2)  || \
                                        ((SOURCE) == RCC_UART7CLKSOURCE_PLL3)  || \
                                        ((SOURCE) == RCC_UART7CLKSOURCE_CSI)   || \
                                        ((SOURCE) == RCC_UART7CLKSOURCE_LSE)   || \
                                        ((SOURCE) == RCC_UART7CLKSOURCE_HSI))

Definition at line 2712 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_UART8CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1)|| \
                                        ((SOURCE) == RCC_UART8CLKSOURCE_PLL2)  || \
                                        ((SOURCE) == RCC_UART8CLKSOURCE_PLL3)  || \
                                        ((SOURCE) == RCC_UART8CLKSOURCE_CSI)   || \
                                        ((SOURCE) == RCC_UART8CLKSOURCE_LSE)   || \
                                        ((SOURCE) == RCC_UART8CLKSOURCE_HSI))

Definition at line 2719 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_USART1CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \
                                        ((SOURCE) == RCC_USART1CLKSOURCE_PLL2)   || \
                                        ((SOURCE) == RCC_USART1CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_USART1CLKSOURCE_CSI)    || \
                                        ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \
                                        ((SOURCE) == RCC_USART1CLKSOURCE_HSI))

Definition at line 2670 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_USART2CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \
                                        ((SOURCE) == RCC_USART2CLKSOURCE_PLL2)   || \
                                        ((SOURCE) == RCC_USART2CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_USART2CLKSOURCE_CSI)    || \
                                        ((SOURCE) == RCC_USART2CLKSOURCE_LSE)    || \
                                        ((SOURCE) == RCC_USART2CLKSOURCE_HSI))

Definition at line 2677 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_USART3CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \
                                        ((SOURCE) == RCC_USART3CLKSOURCE_PLL2)   || \
                                        ((SOURCE) == RCC_USART3CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_USART3CLKSOURCE_CSI)    || \
                                        ((SOURCE) == RCC_USART3CLKSOURCE_LSE)    || \
                                        ((SOURCE) == RCC_USART3CLKSOURCE_HSI))

Definition at line 2684 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_USART6CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \
                                        ((SOURCE) == RCC_USART6CLKSOURCE_PLL2)   || \
                                        ((SOURCE) == RCC_USART6CLKSOURCE_PLL3)   || \
                                        ((SOURCE) == RCC_USART6CLKSOURCE_CSI)    || \
                                        ((SOURCE) == RCC_USART6CLKSOURCE_LSE)    || \
                                        ((SOURCE) == RCC_USART6CLKSOURCE_HSI))

Definition at line 2705 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_USBCLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_USBCLKSOURCE_PLL)  || \
                                        ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \
                                        ((SOURCE) == RCC_USBCLKSOURCE_HSI48))

Definition at line 2916 of file stm32h7xx_hal_rcc_ex.h.

#define IS_RCC_USBCLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_USBCLKSOURCE_PLL)  || \
                                        ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \
                                        ((SOURCE) == RCC_USBCLKSOURCE_HSI48))

Definition at line 2916 of file stm32h7xx_hal_rcc_ex.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Extended Clock Recovery System Control functions

Functions
Extended Clock Recovery System Control functions
Extended Peripheral Control functions | RCCEx

Extended Clock Recovery System Control functions. More...

Functions

void | HAL_RCCEx_CRSConfig (RCC_CRSInitTypeDef *pInit)
Start automatic synchronization for polling mode.
void | HAL_RCCEx_CRSSoftwareSynchronizationGenerate (void)
Generate the software synchronization event.
void | HAL_RCCEx_CRSGetSynchronizationInfo (RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
Return synchronization info.
uint32_t | HAL_RCCEx_CRSWaitSynchronization (uint32_t Timeout)
Wait for CRS Synchronization status.
void | HAL_RCCEx_CRS_IRQHandler (void)
Handle the Clock Recovery System interrupt request.
__weak void | HAL_RCCEx_CRS_SyncOkCallback (void)
RCCEx Clock Recovery System SYNCOK interrupt callback.
__weak void | HAL_RCCEx_CRS_SyncWarnCallback (void)
RCCEx Clock Recovery System SYNCWARN interrupt callback.
__weak void | HAL_RCCEx_CRS_ExpectedSyncCallback (void)
RCCEx Clock Recovery System Expected SYNC interrupt callback.
__weak void | HAL_RCCEx_CRS_ErrorCallback (uint32_t Error)
RCCEx Clock Recovery System Error interrupt callback.

Detailed Description

Extended Clock Recovery System Control functions.

 ===============================================================================
                ##### Extended Clock Recovery System Control functions  #####
 ===============================================================================
    [..]
      For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:

      (#) In System clock config, HSI48 needs to be enabled

      (#) Enable CRS clock in IP MSP init which will use CRS functions

      (#) Call CRS functions as follows:
          (##) Prepare synchronization configuration necessary for HSI48 calibration
              (+++) Default values can be set for frequency Error Measurement (reload and error limit)
                        and also HSI48 oscillator smooth trimming.
              (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
                        directly reload value with target and synchronization frequencies values
          (##) Call function HAL_RCCEx_CRSConfig which
              (+++) Resets CRS registers to their default values.
              (+++) Configures CRS registers with synchronization configuration
              (+++) Enables automatic calibration and frequency error counter feature
           Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
           periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
           provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
           precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
           should be used as SYNC signal.

          (##) A polling function is provided to wait for complete synchronization
              (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
              (+++) According to CRS status, user can decide to adjust again the calibration or continue
                        application if synchronization is OK

      (#) User can retrieve information related to synchronization in calling function
            HAL_RCCEx_CRSGetSynchronizationInfo()

      (#) Regarding synchronization status and synchronization information, user can try a new calibration
           in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
           Note: When the SYNC event is detected during the down-counting phase (before reaching the zero value),
           it means that the actual frequency is lower than the target (and so, that the TRIM value should be
           incremented), while when it is detected during the up-counting phase it means that the actual frequency
           is higher (and that the TRIM value should be decremented).

      (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
          through CRS Handler (CRS_IRQn/CRS_IRQHandler)
              (++) Call function HAL_RCCEx_CRSConfig()
              (++) Enable CRS_IRQn (thanks to NVIC functions)
              (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
              (++) Implement CRS status management in the following user callbacks called from
                   HAL_RCCEx_CRS_IRQHandler():
                   (+++) HAL_RCCEx_CRS_SyncOkCallback()
                   (+++) HAL_RCCEx_CRS_SyncWarnCallback()
                   (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
                   (+++) HAL_RCCEx_CRS_ErrorCallback()

      (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
          This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)

Function Documentation

void HAL_RCCEx_CRS_ErrorCallback ( uint32_t Error )

RCCEx Clock Recovery System Error interrupt callback.

Parameters:
Error Combination of Error status. This parameter can be a combination of the following values:
  • RCC_CRS_SYNCERR
  • RCC_CRS_SYNCMISS
  • RCC_CRS_TRIMOVF
Return values:
none

Definition at line 3236 of file stm32h7xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_CRS_IRQHandler().

void HAL_RCCEx_CRS_ExpectedSyncCallback ( void )

RCCEx Clock Recovery System Expected SYNC interrupt callback.

Return values:
none

Definition at line 3220 of file stm32h7xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_CRS_IRQHandler().

void HAL_RCCEx_CRS_IRQHandler ( void )

Handle the Clock Recovery System interrupt request.

Return values:
None

Definition at line 3133 of file stm32h7xx_hal_rcc_ex.c.

References HAL_RCCEx_CRS_ErrorCallback(), HAL_RCCEx_CRS_ExpectedSyncCallback(), HAL_RCCEx_CRS_SyncOkCallback(), HAL_RCCEx_CRS_SyncWarnCallback(), RCC_CRS_FLAG_ERR, RCC_CRS_FLAG_ESYNC, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS, RCC_CRS_FLAG_SYNCOK, RCC_CRS_FLAG_SYNCWARN, RCC_CRS_FLAG_TRIMOVF, RCC_CRS_IT_ERR, RCC_CRS_IT_ESYNC, RCC_CRS_IT_SYNCOK, RCC_CRS_IT_SYNCWARN, RCC_CRS_NONE, RCC_CRS_SYNCERR, RCC_CRS_SYNCMISS, and RCC_CRS_TRIMOVF.

void HAL_RCCEx_CRS_SyncOkCallback ( void )

RCCEx Clock Recovery System SYNCOK interrupt callback.

Return values:
none

Definition at line 3198 of file stm32h7xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_CRS_IRQHandler().

void HAL_RCCEx_CRS_SyncWarnCallback ( void )

RCCEx Clock Recovery System SYNCWARN interrupt callback.

Return values:
none

Definition at line 3209 of file stm32h7xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_CRS_IRQHandler().

void HAL_RCCEx_CRSConfig ( RCC_CRSInitTypeDef * pInit )

Start automatic synchronization for polling mode.

Parameters:
pInit Pointer on RCC_CRSInitTypeDef structure
Return values:
None

Definition at line 2965 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_CRS_FORCE_RESET, __HAL_RCC_CRS_RELEASE_RESET, assert_param, RCC_CRSInitTypeDef::ErrorLimitValue, RCC_CRSInitTypeDef::HSI48CalibrationValue, IS_RCC_CRS_ERRORLIMIT, IS_RCC_CRS_HSI48CALIBRATION, IS_RCC_CRS_RELOADVALUE, IS_RCC_CRS_SYNC_DIV, IS_RCC_CRS_SYNC_POLARITY, IS_RCC_CRS_SYNC_SOURCE, RCC_CRSInitTypeDef::Polarity, RCC_CRSInitTypeDef::Prescaler, RCC_CRSInitTypeDef::ReloadValue, and RCC_CRSInitTypeDef::Source.

void HAL_RCCEx_CRSGetSynchronizationInfo ( RCC_CRSSynchroInfoTypeDef * pSynchroInfo )

Return synchronization info.

Parameters:
pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
Return values:
None

Definition at line 3017 of file stm32h7xx_hal_rcc_ex.c.

References assert_param, RCC_CRSSynchroInfoTypeDef::FreqErrorCapture, RCC_CRSSynchroInfoTypeDef::FreqErrorDirection, RCC_CRSSynchroInfoTypeDef::HSI48CalibrationValue, and RCC_CRSSynchroInfoTypeDef::ReloadValue.

void HAL_RCCEx_CRSSoftwareSynchronizationGenerate ( void )

Generate the software synchronization event.

Return values:
None

Definition at line 3007 of file stm32h7xx_hal_rcc_ex.c.

uint32_t HAL_RCCEx_CRSWaitSynchronization ( uint32_t Timeout )

Wait for CRS Synchronization status.

Parameters:
Timeout Duration of the time-out
Note:
Timeout is based on the maximum time to receive a SYNC event based on synchronization frequency.
If Time-out set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
Return values:
Combination of Synchronization status This parameter can be a combination of the following values:
  • RCC_CRS_TIMEOUT
  • RCC_CRS_SYNCOK
  • RCC_CRS_SYNCWARN
  • RCC_CRS_SYNCERR
  • RCC_CRS_SYNCMISS
  • RCC_CRS_TRIMOVF

Definition at line 3050 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_CRS_CLEAR_FLAG, __HAL_RCC_CRS_GET_FLAG, HAL_GetTick(), RCC_CRS_FLAG_ESYNC, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS, RCC_CRS_FLAG_SYNCOK, RCC_CRS_FLAG_SYNCWARN, RCC_CRS_FLAG_TRIMOVF, RCC_CRS_NONE, RCC_CRS_SYNCERR, RCC_CRS_SYNCMISS, RCC_CRS_SYNCOK, RCC_CRS_SYNCWARN, RCC_CRS_TIMEOUT, and RCC_CRS_TRIMOVF.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Extended Peripheral Control functions

Modules | Functions
Extended Peripheral Control functions
Exported Functions | RCCEx

Extended Peripheral Control functions. More...

Modules

Extended Clock Recovery System Control functions

Extended Clock Recovery System Control functions.

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Return the peripheral clock frequency for a given peripheral(SAI..)
uint32_t | HAL_RCCEx_GetD1PCLK1Freq (void)
Returns the D1PCLK1 frequency.
uint32_t | HAL_RCCEx_GetD3PCLK1Freq (void)
Returns the D3PCLK1 frequency.
void | HAL_RCCEx_GetPLL2ClockFreq (PLL2_ClocksTypeDef *PLL2_Clocks)
Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency.
void | HAL_RCCEx_GetPLL3ClockFreq (PLL3_ClocksTypeDef *PLL3_Clocks)
Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency.
void | HAL_RCCEx_GetPLL1ClockFreq (PLL1_ClocksTypeDef *PLL1_Clocks)
Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency.
uint32_t | HAL_RCCEx_GetD1SysClockFreq (void)
Returns the main Core frequency.
void | HAL_RCCEx_EnableLSECSS (void)
Enables the LSE Clock Security System.
void | HAL_RCCEx_DisableLSECSS (void)
Disables the LSE Clock Security System.
void | HAL_RCCEx_WakeUpStopCLKConfig (uint32_t WakeUpClk)
Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
void | HAL_RCCEx_KerWakeUpStopCLKConfig (uint32_t WakeUpClk)
Configure the oscillator Kernel clock source for wakeup from Stop.
void | HAL_RCCEx_WWDGxSysResetConfig (uint32_t RCC_WWDGx)
Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                ##### Extended Peripheral Control functions  #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the RCC Clocks
    frequencies.
    [..]
    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
        select the RTC clock source; in this case the Backup domain will be reset in
        order to modify the RTC Clock source, as consequence RTC registers (including
        the backup registers) and RCC_BDCR register are set to their reset values.

Function Documentation

void HAL_RCCEx_DisableLSECSS ( void )

Disables the LSE Clock Security System.

Note:
LSE Clock Security System can only be disabled after a LSE failure detection.
Return values:
None

Definition at line 2838 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_DISABLE_IT, and RCC_IT_LSECSS.

void HAL_RCCEx_EnableLSECSS ( void )

Enables the LSE Clock Security System.

Note:
Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC clock with HAL_RCCEx_PeriphCLKConfig().
Return values:
None

Definition at line 2828 of file stm32h7xx_hal_rcc_ex.c.

uint32_t HAL_RCCEx_GetD1PCLK1Freq ( void )

Returns the D1PCLK1 frequency.

Note:
Each time D1PCLK1 changes, this function must be called to update the right D1PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
D1PCLK1 frequency

Definition at line 2614 of file stm32h7xx_hal_rcc_ex.c.

References HAL_RCC_GetHCLKFreq().

uint32_t HAL_RCCEx_GetD1SysClockFreq ( void )

Returns the main Core frequency.

Note:
Each time core clock changes, this function must be called to update the right system core clock value. Otherwise, any configuration based on this function will be incorrect.
The SystemCoreClock CMSIS variable is used to store System Clock Frequency and updated within this function
Return values:
HCLK frequency

Definition at line 2815 of file stm32h7xx_hal_rcc_ex.c.

References HAL_RCC_GetSysClockFreq().

Referenced by HAL_RCC_GetHCLKFreq().

uint32_t HAL_RCCEx_GetD3PCLK1Freq ( void )

Returns the D3PCLK1 frequency.

Note:
Each time D3PCLK1 changes, this function must be called to update the right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
D3PCLK1 frequency

Definition at line 2626 of file stm32h7xx_hal_rcc_ex.c.

References HAL_RCC_GetHCLKFreq().

Referenced by UART_SetConfig().

void HAL_RCCEx_GetPeriphCLKConfig ( RCC_PeriphCLKInitTypeDef * PeriphClkInit )

Get the RCC_ClkInitStruct according to the internal RCC configuration registers.

Parameters:
PeriphClkInit,: pointer to an RCC_PeriphCLKInitTypeDef structure that returns the configuration information for the Extended Peripherals clocks : (SDMMC, CKPER, FMC, QSPI, DSI, SPI45, SPDIF, DFSDM1, FDCAN, SWPMI,SAI23, SAI1, SPI123, USART234578, USART16, RNG,HRTIM1, I2C123, USB,CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC, SAI4A,SAI4B,SPI6,RTC,TIM).
Return values:
None

Definition at line 2044 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_GET_ADC_SOURCE, __HAL_RCC_GET_CEC_SOURCE, __HAL_RCC_GET_CLKP_SOURCE, __HAL_RCC_GET_DFSDM1_SOURCE, __HAL_RCC_GET_FDCAN_SOURCE, __HAL_RCC_GET_FMC_SOURCE, __HAL_RCC_GET_HRTIM1_SOURCE, __HAL_RCC_GET_I2C1_SOURCE, __HAL_RCC_GET_I2C2_SOURCE, __HAL_RCC_GET_I2C3_SOURCE, __HAL_RCC_GET_LPTIM1_SOURCE, __HAL_RCC_GET_LPTIM2_SOURCE, __HAL_RCC_GET_LPTIM3_SOURCE, __HAL_RCC_GET_LPTIM4_SOURCE, __HAL_RCC_GET_LPTIM5_SOURCE, __HAL_RCC_GET_LPUART1_SOURCE, __HAL_RCC_GET_QSPI_SOURCE, __HAL_RCC_GET_RNG_SOURCE, __HAL_RCC_GET_RTC_SOURCE, __HAL_RCC_GET_SAI1_SOURCE, __HAL_RCC_GET_SAI2_SOURCE, __HAL_RCC_GET_SAI3_SOURCE, __HAL_RCC_GET_SAI4A_SOURCE, __HAL_RCC_GET_SAI4B_SOURCE, __HAL_RCC_GET_SDMMC_SOURCE, __HAL_RCC_GET_SPDIFRX_SOURCE, __HAL_RCC_GET_SPI1_SOURCE, __HAL_RCC_GET_SPI2_SOURCE, __HAL_RCC_GET_SPI3_SOURCE, __HAL_RCC_GET_SPI4_SOURCE, __HAL_RCC_GET_SPI5_SOURCE, __HAL_RCC_GET_SPI6_SOURCE, __HAL_RCC_GET_SWPMI1_SOURCE, __HAL_RCC_GET_UART4_SOURCE, __HAL_RCC_GET_UART5_SOURCE, __HAL_RCC_GET_UART7_SOURCE, __HAL_RCC_GET_UART8_SOURCE, __HAL_RCC_GET_USART1_SOURCE, __HAL_RCC_GET_USART2_SOURCE, __HAL_RCC_GET_USART3_SOURCE, __HAL_RCC_GET_USART6_SOURCE, __HAL_RCC_GET_USB_SOURCE, RCC_PeriphCLKInitTypeDef::AdcClockSelection, RCC_PeriphCLKInitTypeDef::CecClockSelection, RCC_PeriphCLKInitTypeDef::CkperClockSelection, RCC_PeriphCLKInitTypeDef::Dfsdm1ClockSelection, RCC_PeriphCLKInitTypeDef::FdcanClockSelection, RCC_PeriphCLKInitTypeDef::FmcClockSelection, RCC_PeriphCLKInitTypeDef::Hrtim1ClockSelection, RCC_PeriphCLKInitTypeDef::I2c1ClockSelection, RCC_PeriphCLKInitTypeDef::I2c2ClockSelection, RCC_PeriphCLKInitTypeDef::I2c3ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim3ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim4ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim5ClockSelection, RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection, RCC_PeriphCLKInitTypeDef::PeriphClockSelection, RCC_PeriphCLKInitTypeDef::PLL2, RCC_PLL2InitTypeDef::PLL2M, RCC_PLL2InitTypeDef::PLL2N, RCC_PLL2InitTypeDef::PLL2P, RCC_PLL2InitTypeDef::PLL2Q, RCC_PLL2InitTypeDef::PLL2R, RCC_PLL2InitTypeDef::PLL2RGE, RCC_PLL2InitTypeDef::PLL2VCOSEL, RCC_PeriphCLKInitTypeDef::PLL3, RCC_PLL3InitTypeDef::PLL3M, RCC_PLL3InitTypeDef::PLL3N, RCC_PLL3InitTypeDef::PLL3P, RCC_PLL3InitTypeDef::PLL3Q, RCC_PLL3InitTypeDef::PLL3R, RCC_PLL3InitTypeDef::PLL3RGE, RCC_PLL3InitTypeDef::PLL3VCOSEL, RCC_PeriphCLKInitTypeDef::QspiClockSelection, RCC_PERIPHCLK_ADC, RCC_PERIPHCLK_CEC, RCC_PERIPHCLK_CKPER, RCC_PERIPHCLK_DFSDM1, RCC_PERIPHCLK_DSI, RCC_PERIPHCLK_FDCAN, RCC_PERIPHCLK_FMC, RCC_PERIPHCLK_HRTIM1, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_I2C2, RCC_PERIPHCLK_I2C3, RCC_PERIPHCLK_I2C4, RCC_PERIPHCLK_LPTIM1, RCC_PERIPHCLK_LPTIM2, RCC_PERIPHCLK_LPTIM3, RCC_PERIPHCLK_LPTIM4, RCC_PERIPHCLK_LPTIM5, RCC_PERIPHCLK_LPUART1, RCC_PERIPHCLK_LTDC, RCC_PERIPHCLK_QSPI, RCC_PERIPHCLK_RNG, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_SAI1, RCC_PERIPHCLK_SAI2, RCC_PERIPHCLK_SAI3, RCC_PERIPHCLK_SAI4A, RCC_PERIPHCLK_SAI4B, RCC_PERIPHCLK_SDMMC, RCC_PERIPHCLK_SPDIFRX, RCC_PERIPHCLK_SPI1, RCC_PERIPHCLK_SPI2, RCC_PERIPHCLK_SPI3, RCC_PERIPHCLK_SPI4, RCC_PERIPHCLK_SPI5, RCC_PERIPHCLK_SPI6, RCC_PERIPHCLK_SWPMI1, RCC_PERIPHCLK_TIM, RCC_PERIPHCLK_UART4, RCC_PERIPHCLK_UART5, RCC_PERIPHCLK_UART7, RCC_PERIPHCLK_UART8, RCC_PERIPHCLK_USART1, RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_USART3, RCC_PERIPHCLK_USART6, RCC_PERIPHCLK_USB, RCC_TIMPRES_ACTIVATED, RCC_TIMPRES_DESACTIVATED, RCC_PeriphCLKInitTypeDef::RngClockSelection, RCC_PeriphCLKInitTypeDef::RTCClockSelection, RCC_PeriphCLKInitTypeDef::Sai1ClockSelection, RCC_PeriphCLKInitTypeDef::Sai2ClockSelection, RCC_PeriphCLKInitTypeDef::Sai3ClockSelection, RCC_PeriphCLKInitTypeDef::Sai4AClockSelection, RCC_PeriphCLKInitTypeDef::Sai4BClockSelection, RCC_PeriphCLKInitTypeDef::SdmmcClockSelection, RCC_PeriphCLKInitTypeDef::SpdifrxClockSelection, RCC_PeriphCLKInitTypeDef::Spi1ClockSelection, RCC_PeriphCLKInitTypeDef::Spi2ClockSelection, RCC_PeriphCLKInitTypeDef::Spi3ClockSelection, RCC_PeriphCLKInitTypeDef::Spi4ClockSelection, RCC_PeriphCLKInitTypeDef::Spi5ClockSelection, RCC_PeriphCLKInitTypeDef::Spi6ClockSelection, RCC_PeriphCLKInitTypeDef::Swpmi1ClockSelection, RCC_PeriphCLKInitTypeDef::TIMPresSelection, RCC_PeriphCLKInitTypeDef::Uart4ClockSelection, RCC_PeriphCLKInitTypeDef::Uart5ClockSelection, RCC_PeriphCLKInitTypeDef::UART7ClockSelection, RCC_PeriphCLKInitTypeDef::UART8ClockSelection, RCC_PeriphCLKInitTypeDef::Usart1ClockSelection, RCC_PeriphCLKInitTypeDef::Usart2ClockSelection, RCC_PeriphCLKInitTypeDef::Usart3ClockSelection, RCC_PeriphCLKInitTypeDef::Usart6ClockSelection, and RCC_PeriphCLKInitTypeDef::UsbClockSelection.

uint32_t HAL_RCCEx_GetPeriphCLKFreq ( uint32_t PeriphClk )

Return the peripheral clock frequency for a given peripheral(SAI..)

Note:
Return 0 if peripheral clock identifier not managed by this API
Parameters:
PeriphClk,: Peripheral clock identifier This parameter can be one of the following values:
  • RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
  • RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
  • RCC_PERIPHCLK_SAI3: SAI3 peripheral clock
  • RCC_PERIPHCLK_SAI4: SAI4 peripheral clock
  • RCC_PERIPHCLK_SPI1: SPI1 peripheral clock
  • RCC_PERIPHCLK_SPI2: SPI2 peripheral clock
  • RCC_PERIPHCLK_SPI3: SPI3 peripheral clock
Return values:
Frequency in KHz

Definition at line 2190 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_GET_CLKP_SOURCE, __HAL_RCC_GET_SAI1_SOURCE, __HAL_RCC_GET_SAI2_SOURCE, __HAL_RCC_GET_SAI3_SOURCE, __HAL_RCC_GET_SAI4A_SOURCE, __HAL_RCC_GET_SAI4B_SOURCE, __HAL_RCC_GET_SPI3_SOURCE, CSI_VALUE, EXTERNAL_CLOCK_VALUE, HAL_RCCEx_GetPLL1ClockFreq(), HAL_RCCEx_GetPLL2ClockFreq(), HAL_RCCEx_GetPLL3ClockFreq(), HSE_VALUE, HSI_VALUE, PLL1_ClocksTypeDef::PLL1_Q_Frequency, PLL2_ClocksTypeDef::PLL2_P_Frequency, PLL3_ClocksTypeDef::PLL3_P_Frequency, RCC_CLKPSOURCE_CSI, RCC_CLKPSOURCE_HSE, RCC_CLKPSOURCE_HSI, RCC_PERIPHCLK_SAI1, RCC_PERIPHCLK_SAI2, RCC_PERIPHCLK_SAI3, RCC_PERIPHCLK_SAI4A, RCC_PERIPHCLK_SAI4B, RCC_PERIPHCLK_SPI1, RCC_PERIPHCLK_SPI2, and RCC_PERIPHCLK_SPI3.

Referenced by HAL_I2S_Init(), and HAL_SAI_Init().

void HAL_RCCEx_GetPLL1ClockFreq ( PLL1_ClocksTypeDef * PLL1_Clocks )

Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency.

Note:
The PLL1 clock frequencies computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
This function can be used by the user application to compute the baud-rate for the communication peripherals or configure other parameters.
Each time PLL1CLK changes, this function must be called to update the right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
Parameters:
PLL1_Clocks structure.
Return values:
None

Definition at line 2764 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_HSI_DIVIDER, CSI_VALUE, HSE_VALUE, HSI_VALUE, PLL1_ClocksTypeDef::PLL1_P_Frequency, PLL1_ClocksTypeDef::PLL1_Q_Frequency, PLL1_ClocksTypeDef::PLL1_R_Frequency, and RCC_FLAG_HSIDIV.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

void HAL_RCCEx_GetPLL2ClockFreq ( PLL2_ClocksTypeDef * PLL2_Clocks )

Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency.

Note:
The PLL2 clock frequencies computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
This function can be used by the user application to compute the baud-rate for the communication peripherals or configure other parameters.
Each time PLL2CLK changes, this function must be called to update the right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
Parameters:
PLL2_Clocks structure.
Return values:
None

Definition at line 2645 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_HSI_DIVIDER, CSI_VALUE, HSE_VALUE, HSI_VALUE, PLL2_ClocksTypeDef::PLL2_P_Frequency, PLL2_ClocksTypeDef::PLL2_Q_Frequency, PLL2_ClocksTypeDef::PLL2_R_Frequency, and RCC_FLAG_HSIDIV.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

void HAL_RCCEx_GetPLL3ClockFreq ( PLL3_ClocksTypeDef * PLL3_Clocks )

Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency.

Note:
The PLL3 clock frequencies computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
This function can be used by the user application to compute the baud-rate for the communication peripherals or configure other parameters.
Each time PLL3CLK changes, this function must be called to update the right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
Parameters:
PLL3_Clocks structure.
Return values:
None

Definition at line 2707 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_HSI_DIVIDER, CSI_VALUE, HSE_VALUE, HSI_VALUE, PLL3_ClocksTypeDef::PLL3_P_Frequency, PLL3_ClocksTypeDef::PLL3_Q_Frequency, PLL3_ClocksTypeDef::PLL3_R_Frequency, and RCC_FLAG_HSIDIV.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

void HAL_RCCEx_KerWakeUpStopCLKConfig ( uint32_t WakeUpClk )

Configure the oscillator Kernel clock source for wakeup from Stop.

Parameters:
WakeUpClk,: Kernel Wakeup clock This parameter can be one of the following values:
  • RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection
  • RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection
Return values:
None

Definition at line 2870 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG, assert_param, and IS_RCC_STOP_KERWAKEUPCLOCK.

HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig ( RCC_PeriphCLKInitTypeDef * PeriphClkInit )

Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.

Parameters:
PeriphClkInit,: pointer to an RCC_PeriphCLKInitTypeDef structure that contains the configuration information for the Extended Peripherals clocks(SDMMC, CKPER, FMC, QSPI, DSI, SPI45, SPDIF, DFSDM1, FDCAN, SWPMI,SAI23, SAI1, SPI123, USART234578, USART16, RNG, HRTIM1, I2C123, USB,CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC, SAI4A,SAI4B,SPI6,RTC).
Note:
Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select the RTC clock source; in this case the Backup domain will be reset in order to modify the RTC Clock source, as consequence RTC registers (including the backup registers) are set to their reset values.
Return values:
HAL status

Definition at line 124 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_ADC_CONFIG, __HAL_RCC_BACKUPRESET_FORCE, __HAL_RCC_BACKUPRESET_RELEASE, __HAL_RCC_DFSDM1_CONFIG, __HAL_RCC_FDCAN_CONFIG, __HAL_RCC_FMC_CONFIG, __HAL_RCC_GET_FLAG, __HAL_RCC_HRTIM1_CONFIG, __HAL_RCC_I2C1_CONFIG, __HAL_RCC_I2C2_CONFIG, __HAL_RCC_I2C3_CONFIG, __HAL_RCC_I2C4_CONFIG, __HAL_RCC_LPTIM1_CONFIG, __HAL_RCC_LPTIM2_CONFIG, __HAL_RCC_LPTIM3_CONFIG, __HAL_RCC_LPTIM4_CONFIG, __HAL_RCC_LPTIM5_CONFIG, __HAL_RCC_LPUART1_CONFIG, __HAL_RCC_PLL2CLKOUT_ENABLE, __HAL_RCC_PLL3CLKOUT_ENABLE, __HAL_RCC_PLLCLKOUT_ENABLE, __HAL_RCC_QSPI_CONFIG, __HAL_RCC_RNG_CONFIG, __HAL_RCC_RTC_CONFIG, __HAL_RCC_SAI1_CONFIG, __HAL_RCC_SAI2_CONFIG, __HAL_RCC_SAI3_CONFIG, __HAL_RCC_SAI4A_CONFIG, __HAL_RCC_SAI4B_CONFIG, __HAL_RCC_SDMMC_CONFIG, __HAL_RCC_SPDIFRX_CONFIG, __HAL_RCC_SPI1_CONFIG, __HAL_RCC_SPI2_CONFIG, __HAL_RCC_SPI3_CONFIG, __HAL_RCC_SPI4_CONFIG, __HAL_RCC_SPI5_CONFIG, __HAL_RCC_SPI6_CONFIG, __HAL_RCC_SWPMI1_CONFIG, __HAL_RCC_TIMCLKPRESCALER, __HAL_RCC_UART4_CONFIG, __HAL_RCC_UART5_CONFIG, __HAL_RCC_UART7_CONFIG, __HAL_RCC_UART8_CONFIG, __HAL_RCC_USART1_CONFIG, __HAL_RCC_USART2_CONFIG, __HAL_RCC_USART3_CONFIG, __HAL_RCC_USART6_CONFIG, __HAL_RCC_USB_CONFIG, RCC_PeriphCLKInitTypeDef::AdcClockSelection, assert_param, RCC_PeriphCLKInitTypeDef::Dfsdm1ClockSelection, RCC_PeriphCLKInitTypeDef::FdcanClockSelection, RCC_PeriphCLKInitTypeDef::FmcClockSelection, HAL_GetTick(), RCC_PeriphCLKInitTypeDef::Hrtim1ClockSelection, RCC_PeriphCLKInitTypeDef::I2c1ClockSelection, RCC_PeriphCLKInitTypeDef::I2c2ClockSelection, RCC_PeriphCLKInitTypeDef::I2c3ClockSelection, RCC_PeriphCLKInitTypeDef::I2c4ClockSelection, IS_RCC_DFSDM1CLKSOURCE, IS_RCC_HRTIM1CLKSOURCE, IS_RCC_I2C1CLKSOURCE, IS_RCC_I2C2CLKSOURCE, IS_RCC_I2C3CLKSOURCE, IS_RCC_I2C4CLKSOURCE, IS_RCC_PERIPHCLOCK, IS_RCC_RTCCLKSOURCE, IS_RCC_SDMMC, IS_RCC_SWPMI1CLKSOURCE, IS_RCC_TIMPRES, RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim3ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim4ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim5ClockSelection, RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection, RCC_PeriphCLKInitTypeDef::PeriphClockSelection, RCC_PeriphCLKInitTypeDef::PLL2, RCC_PeriphCLKInitTypeDef::PLL3, RCC_PeriphCLKInitTypeDef::QspiClockSelection, RCC_ADCCLKSOURCE_CLKP, RCC_ADCCLKSOURCE_PLL2, RCC_ADCCLKSOURCE_PLL3, RCC_DBP_TIMEOUT_VALUE, RCC_FDCANCLKSOURCE_HSE, RCC_FDCANCLKSOURCE_PLL, RCC_FDCANCLKSOURCE_PLL2, RCC_FLAG_LSERDY, RCC_FMCCLKSOURCE_CLKP, RCC_FMCCLKSOURCE_D1HCLK, RCC_FMCCLKSOURCE_PLL, RCC_FMCCLKSOURCE_PLL2, RCC_I2C1CLKSOURCE_PLL3, RCC_I2C2CLKSOURCE_PLL3, RCC_I2C3CLKSOURCE_PLL3, RCC_I2C4CLKSOURCE_PLL3, RCC_LPTIM1CLKSOURCE_CLKP, RCC_LPTIM1CLKSOURCE_D2PCLK1, RCC_LPTIM1CLKSOURCE_LSE, RCC_LPTIM1CLKSOURCE_LSI, RCC_LPTIM1CLKSOURCE_PLL2, RCC_LPTIM1CLKSOURCE_PLL3, RCC_LPTIM2CLKSOURCE_CLKP, RCC_LPTIM2CLKSOURCE_D3PCLK1, RCC_LPTIM2CLKSOURCE_LSE, RCC_LPTIM2CLKSOURCE_LSI, RCC_LPTIM2CLKSOURCE_PLL2, RCC_LPTIM2CLKSOURCE_PLL3, RCC_LPTIM3CLKSOURCE_CLKP, RCC_LPTIM3CLKSOURCE_D3PCLK1, RCC_LPTIM3CLKSOURCE_LSE, RCC_LPTIM3CLKSOURCE_LSI, RCC_LPTIM3CLKSOURCE_PLL2, RCC_LPTIM3CLKSOURCE_PLL3, RCC_LPTIM4CLKSOURCE_CLKP, RCC_LPTIM4CLKSOURCE_D3PCLK1, RCC_LPTIM4CLKSOURCE_LSE, RCC_LPTIM4CLKSOURCE_LSI, RCC_LPTIM4CLKSOURCE_PLL2, RCC_LPTIM4CLKSOURCE_PLL3, RCC_LPTIM5CLKSOURCE_CLKP, RCC_LPTIM5CLKSOURCE_D3PCLK1, RCC_LPTIM5CLKSOURCE_LSE, RCC_LPTIM5CLKSOURCE_LSI, RCC_LPTIM5CLKSOURCE_PLL2, RCC_LPTIM5CLKSOURCE_PLL3, RCC_LPUART1CLKSOURCE_CSI, RCC_LPUART1CLKSOURCE_D3PCLK1, RCC_LPUART1CLKSOURCE_HSI, RCC_LPUART1CLKSOURCE_LSE, RCC_LPUART1CLKSOURCE_PLL2, RCC_LPUART1CLKSOURCE_PLL3, RCC_LSE_TIMEOUT_VALUE, RCC_PERIPHCLK_ADC, RCC_PERIPHCLK_DFSDM1, RCC_PERIPHCLK_FDCAN, RCC_PERIPHCLK_FMC, RCC_PERIPHCLK_HRTIM1, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_I2C2, RCC_PERIPHCLK_I2C3, RCC_PERIPHCLK_I2C4, RCC_PERIPHCLK_LPTIM1, RCC_PERIPHCLK_LPTIM2, RCC_PERIPHCLK_LPTIM3, RCC_PERIPHCLK_LPTIM4, RCC_PERIPHCLK_LPTIM5, RCC_PERIPHCLK_LPUART1, RCC_PERIPHCLK_LTDC, RCC_PERIPHCLK_QSPI, RCC_PERIPHCLK_RNG, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_SAI1, RCC_PERIPHCLK_SAI2, RCC_PERIPHCLK_SAI3, RCC_PERIPHCLK_SAI4A, RCC_PERIPHCLK_SAI4B, RCC_PERIPHCLK_SDMMC, RCC_PERIPHCLK_SPDIFRX, RCC_PERIPHCLK_SPI1, RCC_PERIPHCLK_SPI2, RCC_PERIPHCLK_SPI3, RCC_PERIPHCLK_SPI4, RCC_PERIPHCLK_SPI5, RCC_PERIPHCLK_SPI6, RCC_PERIPHCLK_SWPMI1, RCC_PERIPHCLK_TIM, RCC_PERIPHCLK_UART4, RCC_PERIPHCLK_UART5, RCC_PERIPHCLK_UART7, RCC_PERIPHCLK_UART8, RCC_PERIPHCLK_USART1, RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_USART3, RCC_PERIPHCLK_USART6, RCC_PERIPHCLK_USB, RCC_PLL1_DIVQ, RCC_PLL2_DIVP, RCC_PLL2_DIVQ, RCC_PLL2_DIVR, RCC_PLL3_DIVP, RCC_PLL3_DIVQ, RCC_PLL3_DIVR, RCC_QSPICLKSOURCE_CLKP, RCC_QSPICLKSOURCE_D1HCLK, RCC_QSPICLKSOURCE_PLL, RCC_QSPICLKSOURCE_PLL2, RCC_RNGCLKSOURCE_LSE, RCC_RNGCLKSOURCE_LSI, RCC_RNGCLKSOURCE_PLL, RCC_RTCCLKSOURCE_LSE, RCC_SAI1CLKSOURCE_CLKP, RCC_SAI1CLKSOURCE_PIN, RCC_SAI1CLKSOURCE_PLL, RCC_SAI1CLKSOURCE_PLL2, RCC_SAI1CLKSOURCE_PLL3, RCC_SAI2CLKSOURCE_CLKP, RCC_SAI2CLKSOURCE_PIN, RCC_SAI2CLKSOURCE_PLL, RCC_SAI2CLKSOURCE_PLL2, RCC_SAI2CLKSOURCE_PLL3, RCC_SAI3CLKSOURCE_CLKP, RCC_SAI3CLKSOURCE_PIN, RCC_SAI3CLKSOURCE_PLL, RCC_SAI3CLKSOURCE_PLL2, RCC_SAI3CLKSOURCE_PLL3, RCC_SAI4ACLKSOURCE_CLKP, RCC_SAI4ACLKSOURCE_PIN, RCC_SAI4ACLKSOURCE_PLL, RCC_SAI4ACLKSOURCE_PLL2, RCC_SAI4ACLKSOURCE_PLL3, RCC_SAI4BCLKSOURCE_CLKP, RCC_SAI4BCLKSOURCE_PIN, RCC_SAI4BCLKSOURCE_PLL, RCC_SAI4BCLKSOURCE_PLL2, RCC_SAI4BCLKSOURCE_PLL3, RCC_SDMMCCLKSOURCE_PLL, RCC_SDMMCCLKSOURCE_PLL2, RCC_SPDIFRXCLKSOURCE_HSI, RCC_SPDIFRXCLKSOURCE_PLL, RCC_SPDIFRXCLKSOURCE_PLL2, RCC_SPDIFRXCLKSOURCE_PLL3, RCC_SPI1CLKSOURCE_CLKP, RCC_SPI1CLKSOURCE_PIN, RCC_SPI1CLKSOURCE_PLL, RCC_SPI1CLKSOURCE_PLL2, RCC_SPI1CLKSOURCE_PLL3, RCC_SPI2CLKSOURCE_CLKP, RCC_SPI2CLKSOURCE_PIN, RCC_SPI2CLKSOURCE_PLL, RCC_SPI2CLKSOURCE_PLL2, RCC_SPI2CLKSOURCE_PLL3, RCC_SPI3CLKSOURCE_CLKP, RCC_SPI3CLKSOURCE_PIN, RCC_SPI3CLKSOURCE_PLL, RCC_SPI3CLKSOURCE_PLL2, RCC_SPI3CLKSOURCE_PLL3, RCC_SPI4CLKSOURCE_CSI, RCC_SPI4CLKSOURCE_D2PCLK1, RCC_SPI4CLKSOURCE_HSE, RCC_SPI4CLKSOURCE_HSI, RCC_SPI4CLKSOURCE_PLL2, RCC_SPI4CLKSOURCE_PLL3, RCC_SPI5CLKSOURCE_CSI, RCC_SPI5CLKSOURCE_D2PCLK1, RCC_SPI5CLKSOURCE_HSE, RCC_SPI5CLKSOURCE_HSI, RCC_SPI5CLKSOURCE_PLL2, RCC_SPI5CLKSOURCE_PLL3, RCC_SPI6CLKSOURCE_CSI, RCC_SPI6CLKSOURCE_D3PCLK1, RCC_SPI6CLKSOURCE_HSE, RCC_SPI6CLKSOURCE_HSI, RCC_SPI6CLKSOURCE_PLL2, RCC_SPI6CLKSOURCE_PLL3, RCC_UART4CLKSOURCE_CSI, RCC_UART4CLKSOURCE_D2PCLK1, RCC_UART4CLKSOURCE_HSI, RCC_UART4CLKSOURCE_LSE, RCC_UART4CLKSOURCE_PLL2, RCC_UART4CLKSOURCE_PLL3, RCC_UART5CLKSOURCE_CSI, RCC_UART5CLKSOURCE_D2PCLK1, RCC_UART5CLKSOURCE_HSI, RCC_UART5CLKSOURCE_LSE, RCC_UART5CLKSOURCE_PLL2, RCC_UART5CLKSOURCE_PLL3, RCC_UART7CLKSOURCE_CSI, RCC_UART7CLKSOURCE_D2PCLK1, RCC_UART7CLKSOURCE_HSI, RCC_UART7CLKSOURCE_LSE, RCC_UART7CLKSOURCE_PLL2, RCC_UART7CLKSOURCE_PLL3, RCC_UART8CLKSOURCE_CSI, RCC_UART8CLKSOURCE_D2PCLK1, RCC_UART8CLKSOURCE_HSI, RCC_UART8CLKSOURCE_LSE, RCC_UART8CLKSOURCE_PLL2, RCC_UART8CLKSOURCE_PLL3, RCC_USART1CLKSOURCE_CSI, RCC_USART1CLKSOURCE_D2PCLK2, RCC_USART1CLKSOURCE_HSI, RCC_USART1CLKSOURCE_LSE, RCC_USART1CLKSOURCE_PLL2, RCC_USART1CLKSOURCE_PLL3, RCC_USART2CLKSOURCE_CSI, RCC_USART2CLKSOURCE_D2PCLK1, RCC_USART2CLKSOURCE_HSI, RCC_USART2CLKSOURCE_LSE, RCC_USART2CLKSOURCE_PLL2, RCC_USART2CLKSOURCE_PLL3, RCC_USART3CLKSOURCE_CSI, RCC_USART3CLKSOURCE_D2PCLK1, RCC_USART3CLKSOURCE_HSI, RCC_USART3CLKSOURCE_LSE, RCC_USART3CLKSOURCE_PLL2, RCC_USART3CLKSOURCE_PLL3, RCC_USART6CLKSOURCE_CSI, RCC_USART6CLKSOURCE_D2PCLK2, RCC_USART6CLKSOURCE_HSI, RCC_USART6CLKSOURCE_LSE, RCC_USART6CLKSOURCE_PLL2, RCC_USART6CLKSOURCE_PLL3, RCC_USBCLKSOURCE_HSI48, RCC_USBCLKSOURCE_PLL, RCC_USBCLKSOURCE_PLL3, RCCEx_PLL2_Config(), RCCEx_PLL3_Config(), RCC_PeriphCLKInitTypeDef::RngClockSelection, RCC_PeriphCLKInitTypeDef::RTCClockSelection, RCC_PeriphCLKInitTypeDef::Sai1ClockSelection, RCC_PeriphCLKInitTypeDef::Sai2ClockSelection, RCC_PeriphCLKInitTypeDef::Sai3ClockSelection, RCC_PeriphCLKInitTypeDef::Sai4AClockSelection, RCC_PeriphCLKInitTypeDef::Sai4BClockSelection, RCC_PeriphCLKInitTypeDef::SdmmcClockSelection, RCC_PeriphCLKInitTypeDef::SpdifrxClockSelection, RCC_PeriphCLKInitTypeDef::Spi1ClockSelection, RCC_PeriphCLKInitTypeDef::Spi2ClockSelection, RCC_PeriphCLKInitTypeDef::Spi3ClockSelection, RCC_PeriphCLKInitTypeDef::Spi4ClockSelection, RCC_PeriphCLKInitTypeDef::Spi5ClockSelection, RCC_PeriphCLKInitTypeDef::Spi6ClockSelection, RCC_PeriphCLKInitTypeDef::Swpmi1ClockSelection, RCC_PeriphCLKInitTypeDef::TIMPresSelection, RCC_PeriphCLKInitTypeDef::Uart4ClockSelection, RCC_PeriphCLKInitTypeDef::Uart5ClockSelection, RCC_PeriphCLKInitTypeDef::UART7ClockSelection, RCC_PeriphCLKInitTypeDef::UART8ClockSelection, RCC_PeriphCLKInitTypeDef::Usart1ClockSelection, RCC_PeriphCLKInitTypeDef::Usart2ClockSelection, RCC_PeriphCLKInitTypeDef::Usart3ClockSelection, RCC_PeriphCLKInitTypeDef::Usart6ClockSelection, and RCC_PeriphCLKInitTypeDef::UsbClockSelection.

void HAL_RCCEx_WakeUpStopCLKConfig ( uint32_t WakeUpClk )

Configure the oscillator clock source for wakeup from Stop and CSS backup clock.

Parameters:
WakeUpClk,: Wakeup clock This parameter can be one of the following values:
  • RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection
  • RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection
Note:
This function shall not be called after the Clock Security System on HSE has been enabled.
Return values:
None

Definition at line 2855 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_WAKEUPSTOP_CLK_CONFIG, assert_param, and IS_RCC_STOP_WAKEUPCLOCK.

void HAL_RCCEx_WWDGxSysResetConfig ( uint32_t RCC_WWDGx )

Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs.

Parameters:
RCC_WWDGx,: WWDGx to be configured This parameter can be one of the following values:
  • RCC_WWDG1: WWDG1 generates system reset
Note:
This bit can be set by software but is cleared by hardware during a system reset
Return values:
None

Definition at line 2888 of file stm32h7xx_hal_rcc_ex.c.

References assert_param, and IS_RCC_SCOPE_WWDG.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Private Functions

Functions
Private Functions
Exported Functions

Functions

static HAL_StatusTypeDef | RCCEx_PLL2_Config (RCC_PLL2InitTypeDef *pll2)
Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it.
static HAL_StatusTypeDef | RCCEx_PLL3_Config (RCC_PLL3InitTypeDef *pll3)
Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it.

Function Documentation

static HAL_StatusTypeDef RCCEx_PLL2_Config ( RCC_PLL2InitTypeDef * pll2 ) [static]

Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it.

Parameters:
pll2,: Pointer to an RCC_PLL2InitTypeDef structure that contains the configuration parameters as well as VCI, VCO clock ranges.
Note:
PLL2 is temporary disable to apply new parameters
Return values:
HAL status

Definition at line 3269 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_PLL_OSCSOURCE, __HAL_RCC_PLL2_CONFIG, __HAL_RCC_PLL2_DISABLE, __HAL_RCC_PLL2_ENABLE, __HAL_RCC_PLL2_VCIRANGE, __HAL_RCC_PLL2_VCORANGE, assert_param, HAL_GetTick(), IS_RCC_PLL2M_VALUE, IS_RCC_PLL2N_VALUE, IS_RCC_PLL2P_VALUE, IS_RCC_PLL2Q_VALUE, IS_RCC_PLL2R_VALUE, PLL2_TIMEOUT_VALUE, RCC_PLL2InitTypeDef::PLL2M, RCC_PLL2InitTypeDef::PLL2N, RCC_PLL2InitTypeDef::PLL2P, RCC_PLL2InitTypeDef::PLL2Q, RCC_PLL2InitTypeDef::PLL2R, RCC_PLL2InitTypeDef::PLL2RGE, RCC_PLL2InitTypeDef::PLL2VCOSEL, RCC_FLAG_PLL2RDY, and RCC_PLLSOURCE_NONE.

Referenced by HAL_RCCEx_PeriphCLKConfig().

static HAL_StatusTypeDef RCCEx_PLL3_Config ( RCC_PLL3InitTypeDef * pll3 ) [static]

Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it.

Parameters:
pll3,: Pointer to an RCC_PLL3InitTypeDef structure that contains the configuration parameters as well as VCI, VCO clock ranges.
Note:
PLL3 is temporary disable to apply new parameters
Return values:
HAL status

Definition at line 3348 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_PLL_OSCSOURCE, __HAL_RCC_PLL3_CONFIG, __HAL_RCC_PLL3_DISABLE, __HAL_RCC_PLL3_ENABLE, __HAL_RCC_PLL3_VCIRANGE, __HAL_RCC_PLL3_VCORANGE, assert_param, HAL_GetTick(), IS_RCC_PLL3M_VALUE, IS_RCC_PLL3N_VALUE, IS_RCC_PLL3P_VALUE, IS_RCC_PLL3Q_VALUE, IS_RCC_PLL3R_VALUE, PLL3_TIMEOUT_VALUE, RCC_PLL3InitTypeDef::PLL3M, RCC_PLL3InitTypeDef::PLL3N, RCC_PLL3InitTypeDef::PLL3P, RCC_PLL3InitTypeDef::PLL3Q, RCC_PLL3InitTypeDef::PLL3R, RCC_PLL3InitTypeDef::PLL3RGE, RCC_PLL3InitTypeDef::PLL3VCOSEL, RCC_FLAG_PLL3RDY, and RCC_PLLSOURCE_NONE.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC_PLL2InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PLL2InitTypeDef Struct Reference
RCCEx Exported Types

PLL2 Clock structure definition. More...

#include <stm32h7xx_hal_rcc_ex.h>

Data Fields

uint32_t | PLL2M
uint32_t | PLL2N
uint32_t | PLL2P
uint32_t | PLL2Q
uint32_t | PLL2R
uint32_t | PLL2RGE
uint32_t | PLL2VCOSEL
uint32_t | PLL2FRACN

Detailed Description

PLL2 Clock structure definition.

Definition at line 65 of file stm32h7xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_PLL2InitTypeDef::PLL2FRACN

PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for PLL2 VCO It should be a value between 0 and 8191

Definition at line 88 of file stm32h7xx_hal_rcc_ex.h.

uint32_t RCC_PLL2InitTypeDef::PLL2M

PLL2M: Division factor for PLL2 VCO input clock. This parameter must be a number between Min_Data = 1 and Max_Data = 63

Definition at line 68 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL2_Config().

uint32_t RCC_PLL2InitTypeDef::PLL2N

PLL2N: Multiplication factor for PLL2 VCO output clock. This parameter must be a number between Min_Data = 4 and Max_Data = 512

Definition at line 71 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL2_Config().

uint32_t RCC_PLL2InitTypeDef::PLL2P

PLL2P: Division factor for system clock. This parameter must be a number between Min_Data = 2 and Max_Data = 128 odd division factors are not allowed

Definition at line 74 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL2_Config().

uint32_t RCC_PLL2InitTypeDef::PLL2Q

PLL2Q: Division factor for peripheral clocks. This parameter must be a number between Min_Data = 1 and Max_Data = 128

Definition at line 78 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL2_Config().

uint32_t RCC_PLL2InitTypeDef::PLL2R

PLL2R: Division factor for peripheral clocks. This parameter must be a number between Min_Data = 1 and Max_Data = 128

Definition at line 81 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL2_Config().

uint32_t RCC_PLL2InitTypeDef::PLL2RGE

PLL2RGE: PLL2 clock Input range This parameter must be a value of RCC PLL2 VCI Range

Definition at line 83 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL2_Config().

uint32_t RCC_PLL2InitTypeDef::PLL2VCOSEL

PLL2VCOSEL: PLL2 clock Output range This parameter must be a value of RCC PLL2 VCO Range

Definition at line 85 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL2_Config().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc_ex.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC_PLL3InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PLL3InitTypeDef Struct Reference
RCCEx Exported Types

PLL3 Clock structure definition. More...

#include <stm32h7xx_hal_rcc_ex.h>

Data Fields

uint32_t | PLL3M
uint32_t | PLL3N
uint32_t | PLL3P
uint32_t | PLL3Q
uint32_t | PLL3R
uint32_t | PLL3RGE
uint32_t | PLL3VCOSEL
uint32_t | PLL3FRACN

Detailed Description

PLL3 Clock structure definition.

Definition at line 96 of file stm32h7xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_PLL3InitTypeDef::PLL3FRACN

PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for PLL3 VCO It should be a value between 0 and 8191

Definition at line 119 of file stm32h7xx_hal_rcc_ex.h.

uint32_t RCC_PLL3InitTypeDef::PLL3M

PLL3M: Division factor for PLL3 VCO input clock. This parameter must be a number between Min_Data = 1 and Max_Data = 63

Definition at line 99 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL3_Config().

uint32_t RCC_PLL3InitTypeDef::PLL3N

PLL3N: Multiplication factor for PLL3 VCO output clock. This parameter must be a number between Min_Data = 4 and Max_Data = 512

Definition at line 102 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL3_Config().

uint32_t RCC_PLL3InitTypeDef::PLL3P

PLL3P: Division factor for system clock. This parameter must be a number between Min_Data = 2 and Max_Data = 128 odd division factors are not allowed

Definition at line 105 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL3_Config().

uint32_t RCC_PLL3InitTypeDef::PLL3Q

PLL3Q: Division factor for peripheral clocks. This parameter must be a number between Min_Data = 1 and Max_Data = 128

Definition at line 109 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL3_Config().

uint32_t RCC_PLL3InitTypeDef::PLL3R

PLL3R: Division factor for peripheral clocks. This parameter must be a number between Min_Data = 1 and Max_Data = 128

Definition at line 112 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL3_Config().

uint32_t RCC_PLL3InitTypeDef::PLL3RGE

PLL3RGE: PLL3 clock Input range This parameter must be a value of RCC PLL3 VCI Range

Definition at line 114 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL3_Config().

uint32_t RCC_PLL3InitTypeDef::PLL3VCOSEL

PLL3VCOSEL: PLL3 clock Output range This parameter must be a value of RCC PLL3 VCO Range

Definition at line 116 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLL3_Config().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc_ex.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PLL1_ClocksTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PLL1_ClocksTypeDef Struct Reference
RCCEx Exported Types

RCC PLL1 Clocks structure definition. More...

#include <stm32h7xx_hal_rcc_ex.h>

Data Fields

uint32_t | PLL1_P_Frequency
uint32_t | PLL1_Q_Frequency
uint32_t | PLL1_R_Frequency

Detailed Description

RCC PLL1 Clocks structure definition.

Definition at line 126 of file stm32h7xx_hal_rcc_ex.h.

Field Documentation

uint32_t PLL1_ClocksTypeDef::PLL1_P_Frequency

Definition at line 128 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPLL1ClockFreq().

uint32_t PLL1_ClocksTypeDef::PLL1_Q_Frequency

Definition at line 129 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_GetPLL1ClockFreq().

uint32_t PLL1_ClocksTypeDef::PLL1_R_Frequency

Definition at line 130 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPLL1ClockFreq().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc_ex.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PLL2_ClocksTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PLL2_ClocksTypeDef Struct Reference
RCCEx Exported Types

RCC PLL2 Clocks structure definition. More...

#include <stm32h7xx_hal_rcc_ex.h>

Data Fields

uint32_t | PLL2_P_Frequency
uint32_t | PLL2_Q_Frequency
uint32_t | PLL2_R_Frequency

Detailed Description

RCC PLL2 Clocks structure definition.

Definition at line 136 of file stm32h7xx_hal_rcc_ex.h.

Field Documentation

uint32_t PLL2_ClocksTypeDef::PLL2_P_Frequency

Definition at line 138 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_GetPLL2ClockFreq().

uint32_t PLL2_ClocksTypeDef::PLL2_Q_Frequency

Definition at line 139 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPLL2ClockFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t PLL2_ClocksTypeDef::PLL2_R_Frequency

Definition at line 140 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPLL2ClockFreq().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc_ex.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: PLL3_ClocksTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PLL3_ClocksTypeDef Struct Reference
RCCEx Exported Types

RCC PLL3 Clocks structure definition. More...

#include <stm32h7xx_hal_rcc_ex.h>

Data Fields

uint32_t | PLL3_P_Frequency
uint32_t | PLL3_Q_Frequency
uint32_t | PLL3_R_Frequency

Detailed Description

RCC PLL3 Clocks structure definition.

Definition at line 146 of file stm32h7xx_hal_rcc_ex.h.

Field Documentation

uint32_t PLL3_ClocksTypeDef::PLL3_P_Frequency

Definition at line 148 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_GetPLL3ClockFreq().

uint32_t PLL3_ClocksTypeDef::PLL3_Q_Frequency

Definition at line 149 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPLL3ClockFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t PLL3_ClocksTypeDef::PLL3_R_Frequency

Definition at line 150 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPLL3ClockFreq().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc_ex.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC_PeriphCLKInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PeriphCLKInitTypeDef Struct Reference
RCCEx Exported Types

RCC extended clocks structure definition. More...

#include <stm32h7xx_hal_rcc_ex.h>

Data Fields

uint32_t | PeriphClockSelection
RCC_PLL2InitTypeDef PLL2
RCC_PLL3InitTypeDef PLL3
uint32_t | FmcClockSelection
uint32_t | QspiClockSelection
uint32_t | SdmmcClockSelection
uint32_t | CkperClockSelection
uint32_t | Sai1ClockSelection
uint32_t | Sai2ClockSelection
uint32_t | Sai3ClockSelection
uint32_t | Spi1ClockSelection
uint32_t | Spi2ClockSelection
uint32_t | Spi3ClockSelection
uint32_t | Spi4ClockSelection
uint32_t | Spi5ClockSelection
uint32_t | SpdifrxClockSelection
uint32_t | Dfsdm1ClockSelection
uint32_t | FdcanClockSelection
uint32_t | Swpmi1ClockSelection
uint32_t | Usart2ClockSelection
uint32_t | Usart3ClockSelection
uint32_t | Uart4ClockSelection
uint32_t | Uart5ClockSelection
uint32_t | UART7ClockSelection
uint32_t | UART8ClockSelection
uint32_t | Usart1ClockSelection
uint32_t | Usart6ClockSelection
uint32_t | RngClockSelection
uint32_t | I2c1ClockSelection
uint32_t | I2c2ClockSelection
uint32_t | I2c3ClockSelection
uint32_t | UsbClockSelection
uint32_t | CecClockSelection
uint32_t | Lptim1ClockSelection
uint32_t | Lpuart1ClockSelection
uint32_t | I2c4ClockSelection
uint32_t | Lptim2ClockSelection
uint32_t | Lptim3ClockSelection
uint32_t | Lptim4ClockSelection
uint32_t | Lptim5ClockSelection
uint32_t | AdcClockSelection
uint32_t | Sai4AClockSelection
uint32_t | Sai4BClockSelection
uint32_t | Spi6ClockSelection
uint32_t | RTCClockSelection
uint32_t | Hrtim1ClockSelection
uint32_t | TIMPresSelection

Detailed Description

RCC extended clocks structure definition.

Definition at line 157 of file stm32h7xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_PeriphCLKInitTypeDef::AdcClockSelection

Specifies ADC interface clock source This parameter can be a value of RCCEx ADC Clock Source

Definition at line 280 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::CecClockSelection

Specifies CEC clock source This parameter can be a value of RCCEx CEC Clock Source

Definition at line 256 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::CkperClockSelection

Specifies CKPER clock source This parameter can be a value of RCCEx CLKP Clock Source

Definition at line 177 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Dfsdm1ClockSelection

Specifies DFSDM1 Clock clock source This parameter can be a value of RCCEx DFSDM1 Clock Source

Definition at line 207 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::FdcanClockSelection

Specifies FDCAN Clock clock source This parameter can be a value of RCCEx FDCAN Clock Source

Definition at line 210 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::FmcClockSelection

Specifies FMC clock source This parameter can be a value of RCCEx FMC Clock Source

Definition at line 168 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Hrtim1ClockSelection

Specifies HRTIM1 Clock clock source This parameter can be a value of RCC Extended HRTIM1 Clock Source

Definition at line 294 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c1ClockSelection

Specifies I2C1 clock source This parameter can be a value of RCCEx I2C1 Clock Source

Definition at line 244 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c2ClockSelection

Specifies I2C2 clock source This parameter can be a value of RCCEx I2C2 Clock Source

Definition at line 247 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c3ClockSelection

Specifies I2C3 clock source This parameter can be a value of RCCEx I2C3 Clock Source

Definition at line 250 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c4ClockSelection

Specifies I2C4 clock source This parameter can be a value of RCCEx I2C4 Clock Source

Definition at line 265 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection

Specifies LPTIM1 clock source This parameter can be a value of RCCEx LPTIM1 Clock Source

Definition at line 259 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection

Specifies LPTIM2 clock source This parameter can be a value of RCCEx LPTIM2 Clock Source

Definition at line 268 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lptim3ClockSelection

Specifies LPTIM3 clock source This parameter can be a value of RCCEx LPTIM3 Clock Source

Definition at line 271 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lptim4ClockSelection

Specifies LPTIM4 clock source This parameter can be a value of RCCEx LPTIM4 Clock Source

Definition at line 274 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lptim5ClockSelection

Specifies LPTIM5 clock source This parameter can be a value of RCCEx LPTIM5 Clock Source

Definition at line 277 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection

Specifies LPUART1 clock source This parameter can be a value of RCCEx LPUART1 Clock Source

Definition at line 262 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::PeriphClockSelection

The Extended Clock to be configured. This parameter can be a value of RCCEx Periph Clock Selection

Definition at line 159 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

RCC_PLL2InitTypeDef RCC_PeriphCLKInitTypeDef::PLL2

PLL2structure parameters. This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals

Definition at line 162 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

RCC_PLL3InitTypeDef RCC_PeriphCLKInitTypeDef::PLL3

PLL3 structure parameters. This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals

Definition at line 165 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::QspiClockSelection

Specifies QSPI clock source This parameter can be a value of RCCEx QSPI Clock Source

Definition at line 171 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::RngClockSelection

Specifies RNG clock source This parameter can be a value of RCCEx RNG Clock Source

Definition at line 241 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::RTCClockSelection

Specifies RTC Clock clock source This parameter can be a value of RCC RTC Clock Source

Definition at line 291 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Sai1ClockSelection

Specifies SAI1 clock source This parameter can be a value of SAI1 Clock Source

Definition at line 180 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Sai2ClockSelection

Specifies SAI2 clock source This parameter can be a value of SAI2 Clock Source

Definition at line 183 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Sai3ClockSelection

Specifies SAI3 clock source This parameter can be a value of SAI3 Clock Source

Definition at line 186 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Sai4AClockSelection

Specifies SAI4A clock source This parameter can be a value of SAI4A Clock Source

Definition at line 282 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Sai4BClockSelection

Specifies SAI4B clock source This parameter can be a value of SAI4B Clock Source

Definition at line 285 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::SdmmcClockSelection

Specifies SDMMC clock source This parameter can be a value of RCCEx SDMMC Clock Source

Definition at line 174 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::SpdifrxClockSelection

Specifies SPDIFRX Clock clock source This parameter can be a value of RCCEx SPDIFRX Clock Source

Definition at line 204 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Spi1ClockSelection

Specifies SPI1 clock source This parameter can be a value of SPI1 Clock Source

Definition at line 189 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Spi2ClockSelection

Specifies SPI2 clock source This parameter can be a value of SPI2 Clock Source

Definition at line 192 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Spi3ClockSelection

Specifies SPI3 clock source This parameter can be a value of SPI3 Clock Source

Definition at line 195 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Spi4ClockSelection

Specifies SPI4 clock source This parameter can be a value of SPI4 Clock Source

Definition at line 198 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Spi5ClockSelection

Specifies SPI5 clock source This parameter can be a value of SPI5 Clock Source

Definition at line 201 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Spi6ClockSelection

Specifies SPI6 clock source This parameter can be a value of SPI6 Clock Source

Definition at line 288 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Swpmi1ClockSelection

Specifies SWPMI1 Clock clock source This parameter can be a value of RCCEx SWPMI1 Clock Source

Definition at line 214 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::TIMPresSelection

Specifies TIM Clock Prescalers Selection. This parameter can be a value of RCCEx TIM Prescaler Selection

Definition at line 296 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Uart4ClockSelection

Specifies UART4 clock source This parameter can be a value of RCCEx UART4 Clock Source

Definition at line 223 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Uart5ClockSelection

Specifies UART5 clock source This parameter can be a value of RCCEx UART5 Clock Source

Definition at line 226 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::UART7ClockSelection

Specifies UART7 clock source This parameter can be a value of RCCEx UART7 Clock Source

Definition at line 229 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::UART8ClockSelection

Specifies UART8 clock source This parameter can be a value of RCCEx UART8 Clock Source

Definition at line 232 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart1ClockSelection

Specifies USART1 clock source This parameter can be a value of RCCEx USART1 Clock Source

Definition at line 235 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart2ClockSelection

Specifies USART2 clock source This parameter can be a value of RCCEx USART2 Clock Source

Definition at line 217 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart3ClockSelection

Specifies USART3 clock source This parameter can be a value of RCCEx USART3 Clock Source

Definition at line 220 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart6ClockSelection

Specifies USART6 clock source This parameter can be a value of RCCEx USART6 Clock Source

Definition at line 238 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::UsbClockSelection

Specifies USB clock source This parameter can be a value of RCCEx USB Clock Source

Definition at line 253 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc_ex.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC_CRSInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_CRSInitTypeDef Struct Reference
RCCEx Exported Types

RCC_CRS Init structure definition. More...

#include <stm32h7xx_hal_rcc_ex.h>

Data Fields

uint32_t | Prescaler
uint32_t | Source
uint32_t | Polarity
uint32_t | ReloadValue
uint32_t | ErrorLimitValue
uint32_t | HSI48CalibrationValue

Detailed Description

RCC_CRS Init structure definition.

Definition at line 304 of file stm32h7xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_CRSInitTypeDef::ErrorLimitValue

Specifies the value to be used to evaluate the captured frequency error value. This parameter must be a number between 0 and 0xFF or a value of RCCEx CRS ErrorLimitDefault

Definition at line 319 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::HSI48CalibrationValue

Specifies a user-programmable trimming value to the HSI48 oscillator. This parameter must be a number between 0 and 0x3F or a value of RCCEx CRS HSI48CalibrationDefault

Definition at line 322 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::Polarity

Specifies the input polarity for the SYNC signal source. This parameter can be a value of RCCEx CRS SynchroPolarity

Definition at line 312 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::Prescaler

Specifies the division factor of the SYNC signal. This parameter can be a value of RCCEx CRS SynchroDivider

Definition at line 306 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::ReloadValue

Specifies the value to be loaded in the frequency error counter with each SYNC event. It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) This parameter must be a number between 0 and 0xFFFF or a value of RCCEx CRS ReloadValueDefault .

Definition at line 315 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::Source

Specifies the SYNC signal source. This parameter can be a value of RCCEx CRS SynchroSource

Definition at line 309 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc_ex.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC_CRSSynchroInfoTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_CRSSynchroInfoTypeDef Struct Reference
RCCEx Exported Types

RCC_CRS Synchronization structure definition. More...

#include <stm32h7xx_hal_rcc_ex.h>

Data Fields

uint32_t | ReloadValue
uint32_t | HSI48CalibrationValue
uint32_t | FreqErrorCapture
uint32_t | FreqErrorDirection

Detailed Description

RCC_CRS Synchronization structure definition.

Definition at line 330 of file stm32h7xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_CRSSynchroInfoTypeDef::FreqErrorCapture

Specifies the value loaded in the .FECAP, the frequency error counter value latched in the time of the last SYNC event. This parameter must be a number between 0 and 0xFFFF

Definition at line 338 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

uint32_t RCC_CRSSynchroInfoTypeDef::FreqErrorDirection

Specifies the value loaded in the .FEDIR, the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. This parameter must be a value of RCCEx CRS FreqErrorDirection

Definition at line 342 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

uint32_t RCC_CRSSynchroInfoTypeDef::HSI48CalibrationValue

Specifies value loaded in HSI48 oscillator smooth trimming. This parameter must be a number between 0 and 0x3F

Definition at line 335 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

uint32_t RCC_CRSSynchroInfoTypeDef::ReloadValue

Specifies the value loaded in the Counter reload value. This parameter must be a number between 0 and 0xFFFF

Definition at line 332 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rcc_ex.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx Periph Clock Selection

Defines
RCCEx Periph Clock Selection
RCCEx Exported Constants

Defines

#define | RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
#define | RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
#define | RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
#define | RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
#define | RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
#define | RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000020)
#define | RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000040)
#define | RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000080)
#define | RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
#define | RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000200)
#define | RCC_PERIPHCLK_LPTIM2 ((uint32_t)0x00000400)
#define | RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000800)
#define | RCC_PERIPHCLK_SAI2 ((uint32_t)0x00001000)
#define | RCC_PERIPHCLK_USB ((uint32_t)0x00002000)
#define | RCC_PERIPHCLK_ADC ((uint32_t)0x00004000)
#define | RCC_PERIPHCLK_SWPMI1 ((uint32_t)0x00008000)
#define | RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x00010000)
#define | RCC_PERIPHCLK_RTC ((uint32_t)0x00020000)
#define | RCC_PERIPHCLK_CEC ((uint32_t)0x00040000)
#define | RCC_PERIPHCLK_USART6 ((uint32_t)0x00080000)
#define | RCC_PERIPHCLK_UART7 ((uint32_t)0x00100000)
#define | RCC_PERIPHCLK_UART8 ((uint32_t)0x00200000)
#define | RCC_PERIPHCLK_I2C4 ((uint32_t)0x00400000)
#define | RCC_PERIPHCLK_LPTIM3 ((uint32_t)0x00800000)
#define | RCC_PERIPHCLK_LPTIM4 ((uint32_t)0x01000000)
#define | RCC_PERIPHCLK_LPTIM5 ((uint32_t)0x02000000)
#define | RCC_PERIPHCLK_SAI3 ((uint32_t)0x04000000)
#define | RCC_PERIPHCLK_SAI4A ((uint32_t)0x08000000)
#define | RCC_PERIPHCLK_SAI4B ((uint32_t)0x10000000)
#define | RCC_PERIPHCLK_FMC ((uint32_t)0x20000000)
#define | RCC_PERIPHCLK_QSPI ((uint32_t)0x40000000)
#define | RCC_PERIPHCLK_DSI ((uint32_t)0x80000000)
#define | RCC_PERIPHCLK_CKPER ((uint32_t)0x80000001)
#define | RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x80000002)
#define | RCC_PERIPHCLK_FDCAN ((uint32_t)0x80000004)
#define | RCC_PERIPHCLK_SPI1 ((uint32_t)0x80000008)
#define | RCC_PERIPHCLK_SPI2 ((uint32_t)0x80000010)
#define | RCC_PERIPHCLK_SPI3 ((uint32_t)0x80000020)
#define | RCC_PERIPHCLK_SPI4 ((uint32_t)0x80000040)
#define | RCC_PERIPHCLK_SPI5 ((uint32_t)0x80000080)
#define | RCC_PERIPHCLK_SPI6 ((uint32_t)0x80000100)
#define | RCC_PERIPHCLK_SDMMC ((uint32_t)0x80000200)
#define | RCC_PERIPHCLK_LTDC ((uint32_t)0x80000400)
#define | RCC_PERIPHCLK_RNG ((uint32_t)0x80000800)
#define | RCC_PERIPHCLK_HRTIM1 ((uint32_t)0x80001000)
#define | RCC_PERIPHCLK_TIM ((uint32_t)0x80002000)

Define Documentation

#define RCC_PERIPHCLK_ADC ((uint32_t)0x00004000)

Definition at line 377 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_CEC ((uint32_t)0x00040000)

Definition at line 381 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define RCC_PERIPHCLK_CKPER ((uint32_t)0x80000001)

Definition at line 395 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x00010000)

Definition at line 379 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_DSI ((uint32_t)0x80000000)

Definition at line 394 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define RCC_PERIPHCLK_FDCAN ((uint32_t)0x80000004)

Definition at line 397 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_FMC ((uint32_t)0x20000000)

Definition at line 392 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_HRTIM1 ((uint32_t)0x80001000)

Definition at line 407 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000040)

Definition at line 369 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000080)

Definition at line 370 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)

Definition at line 371 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00400000)

Definition at line 385 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000200)

Definition at line 372 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPTIM2 ((uint32_t)0x00000400)

Definition at line 373 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPTIM3 ((uint32_t)0x00800000)

Definition at line 386 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPTIM4 ((uint32_t)0x01000000)

Definition at line 387 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPTIM5 ((uint32_t)0x02000000)

Definition at line 388 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000020)

Definition at line 368 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LTDC ((uint32_t)0x80000400)

Definition at line 405 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_QSPI ((uint32_t)0x40000000)

Definition at line 393 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_RNG ((uint32_t)0x80000800)

Definition at line 406 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_RTC ((uint32_t)0x00020000)

Definition at line 380 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000800)

Definition at line 374 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), and HAL_SAI_Init().

#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00001000)

Definition at line 375 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), and HAL_SAI_Init().

#define RCC_PERIPHCLK_SAI3 ((uint32_t)0x04000000)

Definition at line 389 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), and HAL_SAI_Init().

#define RCC_PERIPHCLK_SAI4A ((uint32_t)0x08000000)

Definition at line 390 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), and HAL_SAI_Init().

#define RCC_PERIPHCLK_SAI4B ((uint32_t)0x10000000)

Definition at line 391 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), and HAL_SAI_Init().

#define RCC_PERIPHCLK_SDMMC ((uint32_t)0x80000200)

Definition at line 404 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x80000002)

Definition at line 396 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_SPI1 ((uint32_t)0x80000008)

Definition at line 398 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_I2S_Init(), HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_SPI2 ((uint32_t)0x80000010)

Definition at line 399 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_SPI3 ((uint32_t)0x80000020)

Definition at line 400 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_SPI4 ((uint32_t)0x80000040)

Definition at line 401 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_SPI5 ((uint32_t)0x80000080)

Definition at line 402 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_SPI6 ((uint32_t)0x80000100)

Definition at line 403 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_SWPMI1 ((uint32_t)0x00008000)

Definition at line 378 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_TIM ((uint32_t)0x80002000)

Definition at line 408 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)

Definition at line 366 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)

Definition at line 367 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_UART7 ((uint32_t)0x00100000)

Definition at line 383 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_UART8 ((uint32_t)0x00200000)

Definition at line 384 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)

Definition at line 363 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)

Definition at line 364 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)

Definition at line 365 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART6 ((uint32_t)0x00080000)

Definition at line 382 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USB ((uint32_t)0x00002000)

Definition at line 376 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC PLL2 Clock Output

Defines
RCC PLL2 Clock Output
RCCEx Exported Constants

Defines

#define | RCC_PLL2_DIVP RCC_PLLCFGR_DIVP2EN
#define | RCC_PLL2_DIVQ RCC_PLLCFGR_DIVQ2EN
#define | RCC_PLL2_DIVR RCC_PLLCFGR_DIVR2EN

Define Documentation

#define RCC_PLL2_DIVP RCC_PLLCFGR_DIVP2EN

Definition at line 419 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_PLL2_DIVQ RCC_PLLCFGR_DIVQ2EN

Definition at line 420 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_PLL2_DIVR RCC_PLLCFGR_DIVR2EN

Definition at line 421 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC PLL3 Clock Output

Defines
RCC PLL3 Clock Output
RCCEx Exported Constants

Defines

#define | RCC_PLL3_DIVP RCC_PLLCFGR_DIVP3EN
#define | RCC_PLL3_DIVQ RCC_PLLCFGR_DIVQ3EN
#define | RCC_PLL3_DIVR RCC_PLLCFGR_DIVR3EN

Define Documentation

#define RCC_PLL3_DIVP RCC_PLLCFGR_DIVP3EN

Definition at line 430 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_PLL3_DIVQ RCC_PLLCFGR_DIVQ3EN

Definition at line 431 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_PLL3_DIVR RCC_PLLCFGR_DIVR3EN

Definition at line 432 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC PLL2 VCI Range

Defines
RCC PLL2 VCI Range
RCCEx Exported Constants

Defines

#define | RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0
#define | RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1
#define | RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2
#define | RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3

Define Documentation

#define RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0

Definition at line 441 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1

Definition at line 442 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2

Definition at line 443 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3

Definition at line 444 of file stm32h7xx_hal_rcc_ex.h.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC PLL2 VCO Range

Defines
RCC PLL2 VCO Range
RCCEx Exported Constants

Defines

#define | RCC_PLL2VCOWIDE ((uint32_t)0x00000000)
#define | RCC_PLL2VCOMEDIUM RCC_PLLCFGR_PLL2VCOSEL

Define Documentation

#define RCC_PLL2VCOMEDIUM RCC_PLLCFGR_PLL2VCOSEL

Definition at line 455 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PLL2VCOWIDE ((uint32_t)0x00000000)

Definition at line 454 of file stm32h7xx_hal_rcc_ex.h.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC PLL3 VCI Range

Defines
RCC PLL3 VCI Range
RCCEx Exported Constants

Defines

#define | RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0
#define | RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1
#define | RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2
#define | RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3

Define Documentation

#define RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0

Definition at line 464 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1

Definition at line 465 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2

Definition at line 466 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3

Definition at line 467 of file stm32h7xx_hal_rcc_ex.h.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC PLL3 VCO Range

Defines
RCC PLL3 VCO Range
RCCEx Exported Constants

Defines

#define | RCC_PLL3VCOWIDE ((uint32_t)0x00000000)
#define | RCC_PLL3VCOMEDIUM RCC_PLLCFGR_PLL3VCOSEL

Define Documentation

#define RCC_PLL3VCOMEDIUM RCC_PLLCFGR_PLL3VCOSEL

Definition at line 478 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_PLL3VCOWIDE ((uint32_t)0x00000000)

Definition at line 477 of file stm32h7xx_hal_rcc_ex.h.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx USART1 Clock Source

Defines
RCCEx USART1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART1CLKSOURCE_D2PCLK2 ((uint32_t)0x00000000)
#define | RCC_USART1CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16SEL_0
#define | RCC_USART1CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16SEL_1
#define | RCC_USART1CLKSOURCE_HSI (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
#define | RCC_USART1CLKSOURCE_CSI RCC_D2CCIP2R_USART16SEL_2
#define | RCC_USART1CLKSOURCE_LSE (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)

Define Documentation

#define RCC_USART1CLKSOURCE_CSI RCC_D2CCIP2R_USART16SEL_2

Definition at line 491 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART1CLKSOURCE_D2PCLK2 ((uint32_t)0x00000000)

Definition at line 487 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART1CLKSOURCE_HSI (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)

Definition at line 490 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART1CLKSOURCE_LSE (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)

Definition at line 492 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART1CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16SEL_0

Definition at line 488 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART1CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16SEL_1

Definition at line 489 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx USART2 Clock Source

Defines
RCCEx USART2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART2CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_USART2CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0
#define | RCC_USART2CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1
#define | RCC_USART2CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
#define | RCC_USART2CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2
#define | RCC_USART2CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)

Define Documentation

#define RCC_USART2CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2

Definition at line 505 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART2CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)

Definition at line 501 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART2CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)

Definition at line 504 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART2CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)

Definition at line 506 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART2CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0

Definition at line 502 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART2CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1

Definition at line 503 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx USART3 Clock Source

Defines
RCCEx USART3 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART3CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_USART3CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0
#define | RCC_USART3CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1
#define | RCC_USART3CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
#define | RCC_USART3CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2
#define | RCC_USART3CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)

Define Documentation

#define RCC_USART3CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2

Definition at line 520 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART3CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)

Definition at line 516 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART3CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)

Definition at line 519 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART3CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)

Definition at line 521 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART3CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0

Definition at line 517 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART3CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1

Definition at line 518 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx UART4 Clock Source

Defines
RCCEx UART4 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_UART4CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_UART4CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0
#define | RCC_UART4CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1
#define | RCC_UART4CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
#define | RCC_UART4CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2
#define | RCC_UART4CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)

Define Documentation

#define RCC_UART4CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2

Definition at line 535 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_UART4CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)

Definition at line 531 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_UART4CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)

Definition at line 534 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_UART4CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)

Definition at line 536 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_UART4CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0

Definition at line 532 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_UART4CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1

Definition at line 533 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx UART5 Clock Source

Defines
RCCEx UART5 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_UART5CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_UART5CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0
#define | RCC_UART5CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1
#define | RCC_UART5CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
#define | RCC_UART5CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2
#define | RCC_UART5CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)

Define Documentation

#define RCC_UART5CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2

Definition at line 549 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_UART5CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)

Definition at line 545 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_UART5CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)

Definition at line 548 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_UART5CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)

Definition at line 550 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_UART5CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0

Definition at line 546 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_UART5CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1

Definition at line 547 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx USART6 Clock Source

Defines
RCCEx USART6 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART6CLKSOURCE_D2PCLK2 ((uint32_t)0x00000000)
#define | RCC_USART6CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16SEL_0
#define | RCC_USART6CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16SEL_1
#define | RCC_USART6CLKSOURCE_HSI (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
#define | RCC_USART6CLKSOURCE_CSI RCC_D2CCIP2R_USART16SEL_2
#define | RCC_USART6CLKSOURCE_LSE (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)

Define Documentation

#define RCC_USART6CLKSOURCE_CSI RCC_D2CCIP2R_USART16SEL_2

Definition at line 564 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART6CLKSOURCE_D2PCLK2 ((uint32_t)0x00000000)

Definition at line 560 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART6CLKSOURCE_HSI (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)

Definition at line 563 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART6CLKSOURCE_LSE (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)

Definition at line 565 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART6CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16SEL_0

Definition at line 561 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USART6CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16SEL_1

Definition at line 562 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx UART7 Clock Source

Defines
RCCEx UART7 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_UART7CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_UART7CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0
#define | RCC_UART7CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1
#define | RCC_UART7CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
#define | RCC_UART7CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2
#define | RCC_UART7CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)

Define Documentation

#define RCC_UART7CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2

Definition at line 579 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_UART7CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)

Definition at line 575 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_UART7CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)

Definition at line 578 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_UART7CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)

Definition at line 580 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_UART7CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0

Definition at line 576 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_UART7CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1

Definition at line 577 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx UART8 Clock Source

Defines
RCCEx UART8 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_UART8CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_UART8CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0
#define | RCC_UART8CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1
#define | RCC_UART8CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
#define | RCC_UART8CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2
#define | RCC_UART8CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)

Define Documentation

#define RCC_UART8CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2

Definition at line 593 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_UART8CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)

Definition at line 589 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_UART8CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)

Definition at line 592 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_UART8CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)

Definition at line 594 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_UART8CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0

Definition at line 590 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_UART8CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1

Definition at line 591 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx LPUART1 Clock Source

Defines
RCCEx LPUART1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPUART1CLKSOURCE_D3PCLK1 ((uint32_t)0x00000000)
#define | RCC_LPUART1CLKSOURCE_PLL2 RCC_D3CCIPR_LPUART1SEL_0
#define | RCC_LPUART1CLKSOURCE_PLL3 RCC_D3CCIPR_LPUART1SEL_1
#define | RCC_LPUART1CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)
#define | RCC_LPUART1CLKSOURCE_CSI RCC_D3CCIPR_LPUART1SEL_2
#define | RCC_LPUART1CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0)

Define Documentation

#define RCC_LPUART1CLKSOURCE_CSI RCC_D3CCIPR_LPUART1SEL_2

Definition at line 609 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPUART1CLKSOURCE_D3PCLK1 ((uint32_t)0x00000000)

Definition at line 605 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPUART1CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)

Definition at line 608 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPUART1CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0)

Definition at line 610 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPUART1CLKSOURCE_PLL2 RCC_D3CCIPR_LPUART1SEL_0

Definition at line 606 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPUART1CLKSOURCE_PLL3 RCC_D3CCIPR_LPUART1SEL_1

Definition at line 607 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx I2C1 Clock Source

Defines
RCCEx I2C1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C1CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_I2C1CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0
#define | RCC_I2C1CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1
#define | RCC_I2C1CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)

Define Documentation

#define RCC_I2C1CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)

Definition at line 623 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C1CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)

Definition at line 620 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C1CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1

Definition at line 622 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C1CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0

Definition at line 621 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx I2C2 Clock Source

Defines
RCCEx I2C2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C2CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_I2C2CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0
#define | RCC_I2C2CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1
#define | RCC_I2C2CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)

Define Documentation

#define RCC_I2C2CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)

Definition at line 637 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C2CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)

Definition at line 634 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C2CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1

Definition at line 636 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C2CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0

Definition at line 635 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx I2C3 Clock Source

Defines
RCCEx I2C3 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C3CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_I2C3CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0
#define | RCC_I2C3CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1
#define | RCC_I2C3CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)

Define Documentation

#define RCC_I2C3CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)

Definition at line 651 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C3CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)

Definition at line 648 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C3CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1

Definition at line 650 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C3CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0

Definition at line 649 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx I2C4 Clock Source

Defines
RCCEx I2C4 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C4CLKSOURCE_D3PCLK1 ((uint32_t)0x00000000)
#define | RCC_I2C4CLKSOURCE_PLL3 RCC_D3CCIPR_I2C4SEL_0
#define | RCC_I2C4CLKSOURCE_HSI RCC_D3CCIPR_I2C4SEL_1
#define | RCC_I2C4CLKSOURCE_CSI (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)

Define Documentation

#define RCC_I2C4CLKSOURCE_CSI (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)

Definition at line 665 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C4CLKSOURCE_D3PCLK1 ((uint32_t)0x00000000)

Definition at line 662 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C4CLKSOURCE_HSI RCC_D3CCIPR_I2C4SEL_1

Definition at line 664 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_I2C4CLKSOURCE_PLL3 RCC_D3CCIPR_I2C4SEL_0

Definition at line 663 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx RNG Clock Source

Defines
RCCEx RNG Clock Source
RCCEx Exported Constants

Defines

#define | RCC_RNGCLKSOURCE_HSI48 ((uint32_t)0x00000000)
#define | RCC_RNGCLKSOURCE_PLL RCC_D2CCIP2R_RNGSEL_0
#define | RCC_RNGCLKSOURCE_LSE RCC_D2CCIP2R_RNGSEL_1
#define | RCC_RNGCLKSOURCE_LSI RCC_D2CCIP2R_RNGSEL

Define Documentation

#define RCC_RNGCLKSOURCE_HSI48 ((uint32_t)0x00000000)

Definition at line 675 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_RNGCLKSOURCE_LSE RCC_D2CCIP2R_RNGSEL_1

Definition at line 677 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_RNGCLKSOURCE_LSI RCC_D2CCIP2R_RNGSEL

Definition at line 678 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_RNGCLKSOURCE_PLL RCC_D2CCIP2R_RNGSEL_0

Definition at line 676 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC Extended HRTIM1 Clock Source

Defines
RCC Extended HRTIM1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_HRTIM1CLK_TIMCLK ((uint32_t)0x00000000)
#define | RCC_HRTIM1CLK_CPUCLK RCC_CFGR_HRTIMSEL

Define Documentation

#define RCC_HRTIM1CLK_CPUCLK RCC_CFGR_HRTIMSEL

Definition at line 689 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_HRTIM1CLK_TIMCLK ((uint32_t)0x00000000)

Definition at line 688 of file stm32h7xx_hal_rcc_ex.h.

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STM32H753xx HAL User Manual: SAI1 Clock Source

Defines
SAI1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SAI1CLKSOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_SAI1CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI1SEL_0
#define | RCC_SAI1CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI1SEL_1
#define | RCC_SAI1CLKSOURCE_PIN (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)
#define | RCC_SAI1CLKSOURCE_CLKP RCC_D2CCIP1R_SAI1SEL_2

Define Documentation

#define RCC_SAI1CLKSOURCE_CLKP RCC_D2CCIP1R_SAI1SEL_2

Definition at line 708 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI1CLKSOURCE_PIN (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)

Definition at line 707 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI1CLKSOURCE_PLL ((uint32_t)0x00000000)

Definition at line 704 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI1CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI1SEL_0

Definition at line 705 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI1CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI1SEL_1

Definition at line 706 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI2 Clock Source

Defines
SAI2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SAI2CLKSOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_SAI2CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI23SEL_0
#define | RCC_SAI2CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI23SEL_1
#define | RCC_SAI2CLKSOURCE_PIN (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
#define | RCC_SAI2CLKSOURCE_CLKP RCC_D2CCIP1R_SAI23SEL_2

Define Documentation

#define RCC_SAI2CLKSOURCE_CLKP RCC_D2CCIP1R_SAI23SEL_2

Definition at line 723 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI2CLKSOURCE_PIN (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)

Definition at line 722 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI2CLKSOURCE_PLL ((uint32_t)0x00000000)

Definition at line 719 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI2CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI23SEL_0

Definition at line 720 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI2CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI23SEL_1

Definition at line 721 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32H753xx HAL User Manual: SPI1 Clock Source

Defines
SPI1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SPI1CLKSOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_SPI1CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI123SEL_0
#define | RCC_SPI1CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI123SEL_1
#define | RCC_SPI1CLKSOURCE_PIN (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
#define | RCC_SPI1CLKSOURCE_CLKP RCC_D2CCIP1R_SPI123SEL_2

Define Documentation

#define RCC_SPI1CLKSOURCE_CLKP RCC_D2CCIP1R_SPI123SEL_2

Definition at line 737 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI1CLKSOURCE_PIN (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)

Definition at line 736 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI1CLKSOURCE_PLL ((uint32_t)0x00000000)

Definition at line 733 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI1CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI123SEL_0

Definition at line 734 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI1CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI123SEL_1

Definition at line 735 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32H753xx HAL User Manual: SPI2 Clock Source

Defines
SPI2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SPI2CLKSOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_SPI2CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI123SEL
#define | RCC_SPI2CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI123SEL_1
#define | RCC_SPI2CLKSOURCE_PIN (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
#define | RCC_SPI2CLKSOURCE_CLKP RCC_D2CCIP1R_SPI123SEL_2

Define Documentation

#define RCC_SPI2CLKSOURCE_CLKP RCC_D2CCIP1R_SPI123SEL_2

Definition at line 750 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI2CLKSOURCE_PIN (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)

Definition at line 749 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI2CLKSOURCE_PLL ((uint32_t)0x00000000)

Definition at line 746 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI2CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI123SEL

Definition at line 747 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI2CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI123SEL_1

Definition at line 748 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32H753xx HAL User Manual: SPI3 Clock Source

Defines
SPI3 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SPI3CLKSOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_SPI3CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI123SEL
#define | RCC_SPI3CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI123SEL_1
#define | RCC_SPI3CLKSOURCE_PIN (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
#define | RCC_SPI3CLKSOURCE_CLKP RCC_D2CCIP1R_SPI123SEL_2

Define Documentation

#define RCC_SPI3CLKSOURCE_CLKP RCC_D2CCIP1R_SPI123SEL_2

Definition at line 764 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI3CLKSOURCE_PIN (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)

Definition at line 763 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI3CLKSOURCE_PLL ((uint32_t)0x00000000)

Definition at line 760 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI3CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI123SEL

Definition at line 761 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI3CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI123SEL_1

Definition at line 762 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32H753xx HAL User Manual: SPI4 Clock Source

Defines
SPI4 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SPI4CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_SPI4CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI45SEL_0
#define | RCC_SPI4CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI45SEL_1
#define | RCC_SPI4CLKSOURCE_HSI (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
#define | RCC_SPI4CLKSOURCE_CSI RCC_D2CCIP1R_SPI45SEL_2
#define | RCC_SPI4CLKSOURCE_HSE (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)

Define Documentation

#define RCC_SPI4CLKSOURCE_CSI RCC_D2CCIP1R_SPI45SEL_2

Definition at line 777 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI4CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)

Definition at line 773 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI4CLKSOURCE_HSE (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)

Definition at line 778 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI4CLKSOURCE_HSI (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)

Definition at line 776 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI4CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI45SEL_0

Definition at line 774 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI4CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI45SEL_1

Definition at line 775 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32H753xx HAL User Manual: SPI5 Clock Source

Defines
SPI5 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SPI5CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_SPI5CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI45SEL_0
#define | RCC_SPI5CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI45SEL_1
#define | RCC_SPI5CLKSOURCE_HSI (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
#define | RCC_SPI5CLKSOURCE_CSI RCC_D2CCIP1R_SPI45SEL_2
#define | RCC_SPI5CLKSOURCE_HSE (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)

Define Documentation

#define RCC_SPI5CLKSOURCE_CSI RCC_D2CCIP1R_SPI45SEL_2

Definition at line 791 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI5CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)

Definition at line 787 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI5CLKSOURCE_HSE (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)

Definition at line 792 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI5CLKSOURCE_HSI (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)

Definition at line 790 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI5CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI45SEL_0

Definition at line 788 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI5CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI45SEL_1

Definition at line 789 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI6 Clock Source

Defines
SPI6 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SPI6CLKSOURCE_D3PCLK1 ((uint32_t)0x00000000)
#define | RCC_SPI6CLKSOURCE_PLL2 RCC_D3CCIPR_SPI6SEL_0
#define | RCC_SPI6CLKSOURCE_PLL3 RCC_D3CCIPR_SPI6SEL_1
#define | RCC_SPI6CLKSOURCE_HSI (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)
#define | RCC_SPI6CLKSOURCE_CSI RCC_D3CCIPR_SPI6SEL_2
#define | RCC_SPI6CLKSOURCE_HSE (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)

Define Documentation

#define RCC_SPI6CLKSOURCE_CSI RCC_D3CCIPR_SPI6SEL_2

Definition at line 806 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI6CLKSOURCE_D3PCLK1 ((uint32_t)0x00000000)

Definition at line 802 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI6CLKSOURCE_HSE (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)

Definition at line 807 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI6CLKSOURCE_HSI (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)

Definition at line 805 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI6CLKSOURCE_PLL2 RCC_D3CCIPR_SPI6SEL_0

Definition at line 803 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPI6CLKSOURCE_PLL3 RCC_D3CCIPR_SPI6SEL_1

Definition at line 804 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI3 Clock Source

Defines
SAI3 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SAI3CLKSOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_SAI3CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI23SEL_0
#define | RCC_SAI3CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI23SEL_1
#define | RCC_SAI3CLKSOURCE_PIN (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
#define | RCC_SAI3CLKSOURCE_CLKP RCC_D2CCIP1R_SAI23SEL_2

Define Documentation

#define RCC_SAI3CLKSOURCE_CLKP RCC_D2CCIP1R_SAI23SEL_2

Definition at line 825 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI3CLKSOURCE_PIN (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)

Definition at line 824 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI3CLKSOURCE_PLL ((uint32_t)0x00000000)

Definition at line 821 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI3CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI23SEL_0

Definition at line 822 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI3CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI23SEL_1

Definition at line 823 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32H753xx HAL User Manual: SAI4A Clock Source

Defines
SAI4A Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SAI4ACLKSOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_SAI4ACLKSOURCE_PLL2 RCC_D3CCIPR_SAI4ASEL_0
#define | RCC_SAI4ACLKSOURCE_PLL3 RCC_D3CCIPR_SAI4ASEL_1
#define | RCC_SAI4ACLKSOURCE_PIN (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
#define | RCC_SAI4ACLKSOURCE_CLKP RCC_D3CCIPR_SAI4ASEL_2

Define Documentation

#define RCC_SAI4ACLKSOURCE_CLKP RCC_D3CCIPR_SAI4ASEL_2

Definition at line 840 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI4ACLKSOURCE_PIN (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)

Definition at line 839 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI4ACLKSOURCE_PLL ((uint32_t)0x00000000)

Definition at line 836 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI4ACLKSOURCE_PLL2 RCC_D3CCIPR_SAI4ASEL_0

Definition at line 837 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI4ACLKSOURCE_PLL3 RCC_D3CCIPR_SAI4ASEL_1

Definition at line 838 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI4B Clock Source

Defines
SAI4B Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SAI4BCLKSOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_SAI4BCLKSOURCE_PLL2 RCC_D3CCIPR_SAI4BSEL_0
#define | RCC_SAI4BCLKSOURCE_PLL3 RCC_D3CCIPR_SAI4BSEL_1
#define | RCC_SAI4BCLKSOURCE_PIN (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
#define | RCC_SAI4BCLKSOURCE_CLKP RCC_D3CCIPR_SAI4BSEL_2

Define Documentation

#define RCC_SAI4BCLKSOURCE_CLKP RCC_D3CCIPR_SAI4BSEL_2

Definition at line 855 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI4BCLKSOURCE_PIN (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)

Definition at line 854 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI4BCLKSOURCE_PLL ((uint32_t)0x00000000)

Definition at line 851 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI4BCLKSOURCE_PLL2 RCC_D3CCIPR_SAI4BSEL_0

Definition at line 852 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI4BCLKSOURCE_PLL3 RCC_D3CCIPR_SAI4BSEL_1

Definition at line 853 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx LPTIM1 Clock Source

Defines
RCCEx LPTIM1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPTIM1CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_LPTIM1CLKSOURCE_PLL2 RCC_D2CCIP2R_LPTIM1SEL_0
#define | RCC_LPTIM1CLKSOURCE_PLL3 RCC_D2CCIP2R_LPTIM1SEL_1
#define | RCC_LPTIM1CLKSOURCE_LSE (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)
#define | RCC_LPTIM1CLKSOURCE_LSI RCC_D2CCIP2R_LPTIM1SEL_2
#define | RCC_LPTIM1CLKSOURCE_CLKP (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)

Define Documentation

#define RCC_LPTIM1CLKSOURCE_CLKP (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)

Definition at line 870 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM1CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)

Definition at line 865 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM1CLKSOURCE_LSE (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)

Definition at line 868 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM1CLKSOURCE_LSI RCC_D2CCIP2R_LPTIM1SEL_2

Definition at line 869 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM1CLKSOURCE_PLL2 RCC_D2CCIP2R_LPTIM1SEL_0

Definition at line 866 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM1CLKSOURCE_PLL3 RCC_D2CCIP2R_LPTIM1SEL_1

Definition at line 867 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx LPTIM2 Clock Source

Defines
RCCEx LPTIM2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPTIM2CLKSOURCE_D3PCLK1 ((uint32_t)0x00000000)
#define | RCC_LPTIM2CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM2SEL_0
#define | RCC_LPTIM2CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM2SEL_1
#define | RCC_LPTIM2CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)
#define | RCC_LPTIM2CLKSOURCE_LSI RCC_D3CCIPR_LPTIM2SEL_2
#define | RCC_LPTIM2CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)

Define Documentation

#define RCC_LPTIM2CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)

Definition at line 885 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM2CLKSOURCE_D3PCLK1 ((uint32_t)0x00000000)

Definition at line 880 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM2CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)

Definition at line 883 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM2CLKSOURCE_LSI RCC_D3CCIPR_LPTIM2SEL_2

Definition at line 884 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM2CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM2SEL_0

Definition at line 881 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM2CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM2SEL_1

Definition at line 882 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx LPTIM3 Clock Source

Defines
RCCEx LPTIM3 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPTIM3CLKSOURCE_D3PCLK1 ((uint32_t)0x00000000)
#define | RCC_LPTIM3CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM345SEL_0
#define | RCC_LPTIM3CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM345SEL_1
#define | RCC_LPTIM3CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
#define | RCC_LPTIM3CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2
#define | RCC_LPTIM3CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)

Define Documentation

#define RCC_LPTIM3CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)

Definition at line 900 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM3CLKSOURCE_D3PCLK1 ((uint32_t)0x00000000)

Definition at line 895 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM3CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)

Definition at line 898 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM3CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2

Definition at line 899 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM3CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM345SEL_0

Definition at line 896 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM3CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM345SEL_1

Definition at line 897 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32H753xx HAL User Manual: RCCEx LPTIM4 Clock Source

Defines
RCCEx LPTIM4 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPTIM4CLKSOURCE_D3PCLK1 ((uint32_t)0x00000000)
#define | RCC_LPTIM4CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM345SEL_0
#define | RCC_LPTIM4CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM345SEL_1
#define | RCC_LPTIM4CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
#define | RCC_LPTIM4CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2
#define | RCC_LPTIM4CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)

Define Documentation

#define RCC_LPTIM4CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)

Definition at line 915 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM4CLKSOURCE_D3PCLK1 ((uint32_t)0x00000000)

Definition at line 910 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM4CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)

Definition at line 913 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM4CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2

Definition at line 914 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM4CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM345SEL_0

Definition at line 911 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM4CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM345SEL_1

Definition at line 912 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32H753xx HAL User Manual: RCCEx LPTIM5 Clock Source

Defines
RCCEx LPTIM5 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPTIM5CLKSOURCE_D3PCLK1 ((uint32_t)0x00000000)
#define | RCC_LPTIM5CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM345SEL_0
#define | RCC_LPTIM5CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM345SEL_1
#define | RCC_LPTIM5CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
#define | RCC_LPTIM5CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2
#define | RCC_LPTIM5CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)

Define Documentation

#define RCC_LPTIM5CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)

Definition at line 930 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM5CLKSOURCE_D3PCLK1 ((uint32_t)0x00000000)

Definition at line 925 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM5CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)

Definition at line 928 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM5CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2

Definition at line 929 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM5CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM345SEL_0

Definition at line 926 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_LPTIM5CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM345SEL_1

Definition at line 927 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32H753xx HAL User Manual: RCCEx QSPI Clock Source

Defines
RCCEx QSPI Clock Source
RCCEx Exported Constants

Defines

#define | RCC_QSPICLKSOURCE_D1HCLK ((uint32_t)0x00000000)
#define | RCC_QSPICLKSOURCE_PLL RCC_D1CCIPR_QSPISEL_0
#define | RCC_QSPICLKSOURCE_PLL2 RCC_D1CCIPR_QSPISEL_1
#define | RCC_QSPICLKSOURCE_CLKP RCC_D1CCIPR_QSPISEL

Define Documentation

#define RCC_QSPICLKSOURCE_CLKP RCC_D1CCIPR_QSPISEL

Definition at line 943 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_QSPICLKSOURCE_D1HCLK ((uint32_t)0x00000000)

Definition at line 940 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_QSPICLKSOURCE_PLL RCC_D1CCIPR_QSPISEL_0

Definition at line 941 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_QSPICLKSOURCE_PLL2 RCC_D1CCIPR_QSPISEL_1

Definition at line 942 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32H753xx HAL User Manual: RCCEx FMC Clock Source

Defines
RCCEx FMC Clock Source
RCCEx Exported Constants

Defines

#define | RCC_FMCCLKSOURCE_D1HCLK ((uint32_t)0x00000000)
#define | RCC_FMCCLKSOURCE_PLL RCC_D1CCIPR_FMCSEL_0
#define | RCC_FMCCLKSOURCE_PLL2 RCC_D1CCIPR_FMCSEL_1
#define | RCC_FMCCLKSOURCE_CLKP RCC_D1CCIPR_FMCSEL

Define Documentation

#define RCC_FMCCLKSOURCE_CLKP RCC_D1CCIPR_FMCSEL

Definition at line 957 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_FMCCLKSOURCE_D1HCLK ((uint32_t)0x00000000)

Definition at line 954 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_FMCCLKSOURCE_PLL RCC_D1CCIPR_FMCSEL_0

Definition at line 955 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_FMCCLKSOURCE_PLL2 RCC_D1CCIPR_FMCSEL_1

Definition at line 956 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32H753xx HAL User Manual: RCCEx FDCAN Clock Source

Defines
RCCEx FDCAN Clock Source
RCCEx Exported Constants

Defines

#define | RCC_FDCANCLKSOURCE_HSE ((uint32_t)0x00000000)
#define | RCC_FDCANCLKSOURCE_PLL RCC_D2CCIP1R_FDCANSEL_0
#define | RCC_FDCANCLKSOURCE_PLL2 RCC_D2CCIP1R_FDCANSEL_1

Define Documentation

#define RCC_FDCANCLKSOURCE_HSE ((uint32_t)0x00000000)

Definition at line 968 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_FDCANCLKSOURCE_PLL RCC_D2CCIP1R_FDCANSEL_0

Definition at line 969 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_FDCANCLKSOURCE_PLL2 RCC_D2CCIP1R_FDCANSEL_1

Definition at line 970 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32H753xx HAL User Manual: RCCEx SDMMC Clock Source

Defines
RCCEx SDMMC Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SDMMCCLKSOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_SDMMCCLKSOURCE_PLL2 RCC_D1CCIPR_SDMMCSEL

Define Documentation

#define RCC_SDMMCCLKSOURCE_PLL ((uint32_t)0x00000000)

Definition at line 982 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SDMMCCLKSOURCE_PLL2 RCC_D1CCIPR_SDMMCSEL

Definition at line 983 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32H753xx HAL User Manual: RCCEx USB Clock Source

RCCEx USB Clock Source
RCCEx Exported Constants
Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx ADC Clock Source

Defines
RCCEx ADC Clock Source
RCCEx Exported Constants

Defines

#define | RCC_ADCCLKSOURCE_PLL2 ((uint32_t)0x00000000)
#define | RCC_ADCCLKSOURCE_PLL3 RCC_D3CCIPR_ADCSEL_0
#define | RCC_ADCCLKSOURCE_CLKP RCC_D3CCIPR_ADCSEL_1

Define Documentation

#define RCC_ADCCLKSOURCE_CLKP RCC_D3CCIPR_ADCSEL_1

Definition at line 1007 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_ADCCLKSOURCE_PLL2 ((uint32_t)0x00000000)

Definition at line 1005 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_ADCCLKSOURCE_PLL3 RCC_D3CCIPR_ADCSEL_0

Definition at line 1006 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32H753xx HAL User Manual: RCCEx SWPMI1 Clock Source

Defines
RCCEx SWPMI1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SWPMI1CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_SWPMI1CLKSOURCE_HSI RCC_D2CCIP1R_SWPSEL

Define Documentation

#define RCC_SWPMI1CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)

Definition at line 1020 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_SWPMI1CLKSOURCE_HSI RCC_D2CCIP1R_SWPSEL

Definition at line 1021 of file stm32h7xx_hal_rcc_ex.h.

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STM32H753xx HAL User Manual: RCCEx DFSDM1 Clock Source

Defines
RCCEx DFSDM1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_DFSDM1CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_DFSDM1CLKSOURCE_SYS RCC_D2CCIP1R_DFSDM1SEL

Define Documentation

#define RCC_DFSDM1CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)

Definition at line 1030 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_DFSDM1CLKSOURCE_SYS RCC_D2CCIP1R_DFSDM1SEL

Definition at line 1031 of file stm32h7xx_hal_rcc_ex.h.

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STM32H753xx HAL User Manual: RCCEx SPDIFRX Clock Source

Defines
RCCEx SPDIFRX Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SPDIFRXCLKSOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_SPDIFRXCLKSOURCE_PLL2 RCC_D2CCIP1R_SPDIFSEL_0
#define | RCC_SPDIFRXCLKSOURCE_PLL3 RCC_D2CCIP1R_SPDIFSEL_1
#define | RCC_SPDIFRXCLKSOURCE_HSI RCC_D2CCIP1R_SPDIFSEL

Define Documentation

#define RCC_SPDIFRXCLKSOURCE_HSI RCC_D2CCIP1R_SPDIFSEL

Definition at line 1044 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPDIFRXCLKSOURCE_PLL ((uint32_t)0x00000000)

Definition at line 1041 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPDIFRXCLKSOURCE_PLL2 RCC_D2CCIP1R_SPDIFSEL_0

Definition at line 1042 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_D2CCIP1R_SPDIFSEL_1

Definition at line 1043 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32H753xx HAL User Manual: RCCEx CEC Clock Source

Defines
RCCEx CEC Clock Source
RCCEx Exported Constants

Defines

#define | RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000)
#define | RCC_CECCLKSOURCE_LSI RCC_D2CCIP2R_CECSEL_0
#define | RCC_CECCLKSOURCE_CSI RCC_D2CCIP2R_CECSEL_1

Define Documentation

#define RCC_CECCLKSOURCE_CSI RCC_D2CCIP2R_CECSEL_1

Definition at line 1055 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000)

Definition at line 1053 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CECCLKSOURCE_LSI RCC_D2CCIP2R_CECSEL_0

Definition at line 1054 of file stm32h7xx_hal_rcc_ex.h.

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STM32H753xx HAL User Manual: RCCEx CLKP Clock Source

Defines
RCCEx CLKP Clock Source
RCCEx Exported Constants

Defines

#define | RCC_CLKPSOURCE_HSI ((uint32_t)0x00000000)
#define | RCC_CLKPSOURCE_CSI RCC_D1CCIPR_CKPERSEL_0
#define | RCC_CLKPSOURCE_HSE RCC_D1CCIPR_CKPERSEL_1

Define Documentation

#define RCC_CLKPSOURCE_CSI RCC_D1CCIPR_CKPERSEL_0

Definition at line 1066 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_CLKPSOURCE_HSE RCC_D1CCIPR_CKPERSEL_1

Definition at line 1067 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_CLKPSOURCE_HSI ((uint32_t)0x00000000)

Definition at line 1065 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32H753xx HAL User Manual: RCCEx TIM Prescaler Selection

Defines
RCCEx TIM Prescaler Selection
RCCEx Exported Constants

Defines

#define | RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U)
#define | RCC_TIMPRES_ACTIVATED RCC_CFGR_TIMPRE

Define Documentation

#define RCC_TIMPRES_ACTIVATED RCC_CFGR_TIMPRE

Definition at line 1077 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U)

Definition at line 1076 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

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STM32H753xx HAL User Manual: RCCEx RCC WWDGx

Defines
RCCEx RCC WWDGx
RCCEx Exported Constants

Defines

#define RCC_WWDG1 RCC_GCR_WW1RSC

Define Documentation

#define RCC_WWDG1 RCC_GCR_WW1RSC

Definition at line 1088 of file stm32h7xx_hal_rcc_ex.h.

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STM32H753xx HAL User Manual: RCCEx CRS Status

Defines
RCCEx CRS Status
RCCEx Exported Constants

Defines

#define | RCC_CRS_NONE ((uint32_t)0x00000000U)
#define | RCC_CRS_TIMEOUT ((uint32_t)0x00000001U)
#define | RCC_CRS_SYNCOK ((uint32_t)0x00000002U)
#define | RCC_CRS_SYNCWARN ((uint32_t)0x00000004U)
#define | RCC_CRS_SYNCERR ((uint32_t)0x00000008U)
#define | RCC_CRS_SYNCMISS ((uint32_t)0x00000010U)
#define | RCC_CRS_TRIMOVF ((uint32_t)0x00000020U)

Define Documentation

#define RCC_CRS_NONE ((uint32_t)0x00000000U)

Definition at line 1098 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_SYNCERR ((uint32_t)0x00000008U)

Definition at line 1102 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010U)

Definition at line 1103 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_SYNCOK ((uint32_t)0x00000002U)

Definition at line 1100 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_SYNCWARN ((uint32_t)0x00000004U)

Definition at line 1101 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001U)

Definition at line 1099 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_TRIMOVF ((uint32_t)0x00000020U)

Definition at line 1104 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

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STM32H753xx HAL User Manual: RCCEx CRS SynchroSource

Defines
RCCEx CRS SynchroSource
RCCEx Exported Constants

Defines

#define | RCC_CRS_SYNC_SOURCE_USB2 ((uint32_t)0x00000000U)
#define | RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0
#define | RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1

Define Documentation

#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0

Synchro Signal source LSE

Definition at line 1113 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1

Synchro Signal source USB1 SOF (default)

Definition at line 1114 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_SOURCE_USB2 ((uint32_t)0x00000000U)

Synchro Signal source USB2 SOF

Definition at line 1112 of file stm32h7xx_hal_rcc_ex.h.

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STM32H753xx HAL User Manual: RCCEx CRS SynchroDivider

Defines
RCCEx CRS SynchroDivider
RCCEx Exported Constants

Defines

#define | RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U)
#define | RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0
#define | RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1
#define | RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)
#define | RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2
#define | RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)
#define | RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)
#define | RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV

Define Documentation

#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U)

Synchro Signal not divided (default)

Definition at line 1124 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV

Synchro Signal divided by 128

Definition at line 1131 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2

Synchro Signal divided by 16

Definition at line 1128 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0

Synchro Signal divided by 2

Definition at line 1125 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)

Synchro Signal divided by 32

Definition at line 1129 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1

Synchro Signal divided by 4

Definition at line 1126 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)

Synchro Signal divided by 64

Definition at line 1130 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)

Synchro Signal divided by 8

Definition at line 1127 of file stm32h7xx_hal_rcc_ex.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx CRS SynchroPolarity

Defines
RCCEx CRS SynchroPolarity
RCCEx Exported Constants

Defines

#define | RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U)
#define | RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL

Define Documentation

#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL

Synchro Active on falling edge

Definition at line 1140 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U)

Synchro Active on rising edge (default)

Definition at line 1139 of file stm32h7xx_hal_rcc_ex.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx CRS ReloadValueDefault

Defines
RCCEx CRS ReloadValueDefault
RCCEx Exported Constants

Defines

#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU)

Define Documentation

#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU)

The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB).

Definition at line 1148 of file stm32h7xx_hal_rcc_ex.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx CRS ErrorLimitDefault

Defines
RCCEx CRS ErrorLimitDefault
RCCEx Exported Constants

Defines

#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U)

Define Documentation

#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U)

Default Frequency error limit

Definition at line 1157 of file stm32h7xx_hal_rcc_ex.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx CRS HSI48CalibrationDefault

Defines
RCCEx CRS HSI48CalibrationDefault
RCCEx Exported Constants

Defines

#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U)

Define Documentation

#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U)

The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency

Definition at line 1165 of file stm32h7xx_hal_rcc_ex.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx CRS FreqErrorDirection

Defines
RCCEx CRS FreqErrorDirection
RCCEx Exported Constants

Defines

#define | RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U)
#define | RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR)

Define Documentation

#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR)

Downcounting direction, the actual frequency is below the target

Definition at line 1176 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U)

Upcounting direction, the actual frequency is above the target

Definition at line 1175 of file stm32h7xx_hal_rcc_ex.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx CRS Interrupt Sources

Defines
RCCEx CRS Interrupt Sources
RCCEx Exported Constants

Defines

#define | RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE
#define | RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE
#define | RCC_CRS_IT_ERR CRS_CR_ERRIE
#define | RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE
#define | RCC_CRS_IT_SYNCERR CRS_CR_ERRIE
#define | RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE
#define | RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE

Define Documentation

#define RCC_CRS_IT_ERR CRS_CR_ERRIE

Error

Definition at line 1186 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE

Expected SYNC

Definition at line 1187 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE

SYNC error

Definition at line 1188 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE

SYNC missed

Definition at line 1189 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE

SYNC event OK

Definition at line 1184 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE

SYNC warning

Definition at line 1185 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE

Trimming overflow or underflow

Definition at line 1190 of file stm32h7xx_hal_rcc_ex.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx CRS Flags

Defines
RCCEx CRS Flags
RCCEx Exported Constants

Defines

#define | RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF
#define | RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF
#define | RCC_CRS_FLAG_ERR CRS_ISR_ERRF
#define | RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF
#define | RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR
#define | RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS
#define | RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF

Define Documentation

#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF

Error flag

Definition at line 1201 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF

Expected SYNC flag

Definition at line 1202 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR

SYNC error

Definition at line 1203 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS

SYNC missed

Definition at line 1204 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF

SYNC event OK flag

Definition at line 1199 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF

SYNC warning flag

Definition at line 1200 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF

Trimming overflow or underflow

Definition at line 1205 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx Exported Constants

Modules | Defines
RCCEx Exported Constants
RCCEx

Modules

RCCEx Periph Clock Selection
RCC PLL2 Clock Output
RCC PLL3 Clock Output
RCC PLL2 VCI Range
RCC PLL2 VCO Range
RCC PLL3 VCI Range
RCC PLL3 VCO Range
RCCEx USART1 Clock Source
RCCEx USART2 Clock Source
RCCEx USART3 Clock Source
RCCEx UART4 Clock Source
RCCEx UART5 Clock Source
RCCEx USART6 Clock Source
RCCEx UART7 Clock Source
RCCEx UART8 Clock Source
RCCEx LPUART1 Clock Source
RCCEx I2C1 Clock Source
RCCEx I2C2 Clock Source
RCCEx I2C3 Clock Source
RCCEx I2C4 Clock Source
RCCEx RNG Clock Source
RCC Extended HRTIM1 Clock Source
SAI1 Clock Source
SAI2 Clock Source
SPI1 Clock Source
SPI2 Clock Source
SPI3 Clock Source
SPI4 Clock Source
SPI5 Clock Source
SPI6 Clock Source
SAI3 Clock Source
SAI4A Clock Source
SAI4B Clock Source
RCCEx LPTIM1 Clock Source
RCCEx LPTIM2 Clock Source
RCCEx LPTIM3 Clock Source
RCCEx LPTIM4 Clock Source
RCCEx LPTIM5 Clock Source
RCCEx QSPI Clock Source
RCCEx FMC Clock Source
RCCEx FDCAN Clock Source
RCCEx SDMMC Clock Source
RCCEx USB Clock Source
RCCEx ADC Clock Source
RCCEx SWPMI1 Clock Source
RCCEx DFSDM1 Clock Source
RCCEx SPDIFRX Clock Source
RCCEx CEC Clock Source
RCCEx CLKP Clock Source
RCCEx TIM Prescaler Selection
RCCEx RCC WWDGx
RCCEx CRS Status
RCCEx CRS SynchroSource
RCCEx CRS SynchroDivider
RCCEx CRS SynchroPolarity
RCCEx CRS ReloadValueDefault
RCCEx CRS ErrorLimitDefault
RCCEx CRS HSI48CalibrationDefault
RCCEx CRS FreqErrorDirection
RCCEx CRS Interrupt Sources
RCCEx CRS Flags

Defines

#define | RCC_USBCLKSOURCE_PLL RCC_D2CCIP2R_USBSEL_0
#define | RCC_USBCLKSOURCE_PLL RCC_D2CCIP2R_USBSEL_0
#define | RCC_USBCLKSOURCE_PLL3 RCC_D2CCIP2R_USBSEL_1
#define | RCC_USBCLKSOURCE_PLL3 RCC_D2CCIP2R_USBSEL_1
#define | RCC_USBCLKSOURCE_HSI48 RCC_D2CCIP2R_USBSEL
#define | RCC_USBCLKSOURCE_HSI48 RCC_D2CCIP2R_USBSEL

Define Documentation

#define RCC_USBCLKSOURCE_HSI48 RCC_D2CCIP2R_USBSEL

Definition at line 996 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USBCLKSOURCE_HSI48 RCC_D2CCIP2R_USBSEL

Definition at line 996 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USBCLKSOURCE_PLL RCC_D2CCIP2R_USBSEL_0

Definition at line 994 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USBCLKSOURCE_PLL RCC_D2CCIP2R_USBSEL_0

Definition at line 994 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_USBCLKSOURCE_PLL3 RCC_D2CCIP2R_USBSEL_1

Definition at line 995 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USBCLKSOURCE_PLL3 RCC_D2CCIP2R_USBSEL_1

Definition at line 995 of file stm32h7xx_hal_rcc_ex.h.

Generated on Fri Apr 28 2017 15:42:50 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCC Extended HRTIMx Clock Config

Defines
RCC Extended HRTIMx Clock Config
RCCEx Exported Macros

Defines

#define | __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__))
Macro to configure the HRTIM1 prescaler clock source.
#define | __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)))
Macro to get the HRTIM1 clock source.
#define | __HAL_RCC_TIMCLKPRESCALER(__PRESC__)
Macro to configure the Timers clocks prescalers.

Define Documentation

#define __HAL_RCC_GET_HRTIM1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)))

Macro to get the HRTIM1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock
  • RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock

Definition at line 2385 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_HRTIM1_CONFIG ( __HRTIM1CLKSource__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__))

Macro to configure the HRTIM1 prescaler clock source.

Parameters:
__HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source. This parameter can be one of the following values:
  • RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock
  • RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock

Definition at line 2377 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_TIMCLKPRESCALER ( __PRESC__ )
Value:
do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\
                                                 RCC->CFGR |= (__PRESC__);       \
                                                }while(0)

Macro to configure the Timers clocks prescalers.

Parameters:
__PRESC__ : specifies the Timers clocks prescalers selection This parameter can be one of the following values:
  • RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2, else it is equal to 2 x Frcc_pclkx_d2 (default after reset)
  • RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4, else it is equal to 4 x Frcc_pclkx_d2

Definition at line 2397 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx CRS Extended Features

Defines
RCCEx CRS Extended Features
RCCEx Exported Macros

Defines

#define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
Enable the oscillator clock for frequency error counter.
#define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
Disable the oscillator clock for frequency error counter.
#define | __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
Enable the automatic hardware adjustment of TRIM bits.
#define | __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
Enable or disable the automatic hardware adjustment of TRIM bits.
#define | __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Define Documentation

#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE ( ) CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)

Enable or disable the automatic hardware adjustment of TRIM bits.

Return values:
None

Definition at line 2535 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE ( ) SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)

Enable the automatic hardware adjustment of TRIM bits.

Note:
When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
Return values:
None

Definition at line 2529 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE ( ) CLEAR_BIT(CRS->CR, CRS_CR_CEN)

Disable the oscillator clock for frequency error counter.

Return values:
None

Definition at line 2522 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE ( ) SET_BIT(CRS->CR, CRS_CR_CEN)

Enable the oscillator clock for frequency error counter.

Note:
when the CEN bit is set the CRS_CFGR register becomes write-protected.
Return values:
None

Definition at line 2516 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE | ( | __FTARGET__,
 |  | __FSYNC__
 | ) | (((__FTARGET__) / (__FSYNC__)) - 1U)

Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Note:
The RELOAD value should be selected according to the ratio between the target frequency and the frequency of the synchronization source after pre-scaling. It is then decreased by one in order to reach the expected synchronization on the zero value. The formula is the following: RELOAD = (fTARGET / fSYNC) -1
Parameters:
__FTARGET__ | Target frequency (value in Hz)
__FSYNC__ | Synchronization signal frequency (value in Hz)
Return values:
None

Definition at line 2547 of file stm32h7xx_hal_rcc_ex.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx Exported Macros

Modules | Defines
RCCEx Exported Macros
RCCEx

Modules

RCC Extended HRTIMx Clock Config
RCCEx CRS Extended Features

Defines

#define | __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON)
Macros to enable or disable PLL2.
#define | __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)
#define | __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)
#define | __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
#define | __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO.
#define | __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
#define | __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__)
Macro to configures the PLL2 multiplication and division factors.
#define | __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,(uint32_t)(__RCC_PLL2FRACN__) << POSITION_VAL(RCC_PLL2FRACR_FRACN2))
Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor.
#define | __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))
Macro to select the PLL2 reference frequency range.
#define | __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))
Macro to select the PLL2 reference frequency range.
#define | __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON)
Macros to enable or disable the main PLL3.
#define | __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)
#define | __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO.
#define | __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
#define | __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)
#define | __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
#define | __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__)
Macro to configures the PLL3 multiplication and division factors.
#define | __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << POSITION_VAL(RCC_PLL3FRACR_FRACN3))
Macro to configures PLL3 clock Fractional Part of The Multiplication Factor.
#define | __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))
Macro to select the PLL3 reference frequency range.
#define | __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))
Macro to select the PLL3 reference frequency range.
#define | __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
Macro to Configure the SAI1 clock source.
#define | __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL)))
Macro to get the SAI1 clock source.
#define | __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
Macro to Configure the SPDIFRX clock source.
#define | __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)))
Macro to get the SPDIFRX clock source.
#define | __HAL_RCC_SAI2_CONFIG(__RCC_SAI2CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI2CLKSource__))
Macro to Configure the SAI2 clock source.
#define | __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
Macro to get the SAI2 clock source.
#define | __HAL_RCC_SAI3_CONFIG(__RCC_SAI3CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI3CLKSource__))
Macro to Configure the SAI3 clock source.
#define | __HAL_RCC_GET_SAI3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
Macro to get the SAI3 clock source.
#define | __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))
Macro to Configure the SAI4A clock source.
#define | __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL)))
Macro to get the SAI4A clock source.
#define | __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))
Macro to Configure the SAI4B clock source.
#define | __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))
Macro to get the SAI4B clock source.
#define | __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1CLKSource__))
macro to configure the I2C1 clock (I2C1CLK).
#define | __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
macro to get the I2C1 clock source.
#define | __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C2CLKSource__))
macro to configure the I2C2 clock (I2C2CLK).
#define | __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
macro to get the I2C2 clock source.
#define | __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C3CLKSource__))
macro to configure the I2C3 clock (I2C3CLK).
#define | __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
macro to get the I2C3 clock source.
#define | __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
macro to configure the I2C4 clock (I2C4CLK).
#define | __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))
macro to get the I2C4 clock source.
#define | __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART1CLKSource__))
macro to configure the USART1 clock (USART1CLK).
#define | __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
macro to get the USART1 clock source.
#define | __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART2CLKSource__))
macro to configure the USART2 clock (USART2CLK).
#define | __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
macro to get the USART2 clock source.
#define | __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART3CLKSource__))
macro to configure the USART3 clock (USART3CLK).
#define | __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
macro to get the USART3 clock source.
#define | __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART4CLKSource__))
macro to configure the UART4 clock (UART4CLK).
#define | __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
macro to get the UART4 clock source.
#define | __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART5CLKSource__))
macro to configure the UART5 clock (UART5CLK).
#define | __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
macro to get the UART5 clock source.
#define | __HAL_RCC_USART6_CONFIG(__USART6CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART6CLKSource__))
macro to configure the USART6 clock (USART6CLK).
#define | __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
macro to get the USART6 clock source.
#define | __HAL_RCC_UART7_CONFIG(__UART7CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART7CLKSource__))
macro to configure the UART5 clock (UART7CLK).
#define | __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
macro to get the UART7 clock source.
#define | __HAL_RCC_UART8_CONFIG(__UART8CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART8CLKSource__))
macro to configure the UART8 clock (UART8CLK).
#define | __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
macro to get the UART8 clock source.
#define | __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
macro to configure the LPUART1 clock (LPUART1CLK).
#define | __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))
macro to get the LPUART1 clock source.
#define | __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
macro to get the LPTIM1 clock source.
#define | __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))
macro to get the LPTIM1 clock source.
#define | __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
macro to get the LPTIM2 clock source.
#define | __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))
macro to get the LPTIM2 clock source.
#define | __HAL_RCC_LPTIM3_CONFIG(__LPTIM3CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM3CLKSource__))
macro to get the LPTIM3 clock source.
#define | __HAL_RCC_GET_LPTIM3_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
macro to get the LPTIM3 clock source.
#define | __HAL_RCC_LPTIM4_CONFIG(__LPTIM4CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM4CLKSource__))
macro to get the LPTIM4 clock source.
#define | __HAL_RCC_GET_LPTIM4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
macro to get the LPTIM4 clock source.
#define | __HAL_RCC_LPTIM5_CONFIG(__LPTIM5CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM5CLKSource__))
macro to configure the LPTIM5 clock source.
#define | __HAL_RCC_GET_LPTIM5_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
macro to get the LPTIM5 clock source.
#define | __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__))
macro to configure the QSPI clock source.
#define | __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)))
macro to get the QSPI clock source.
#define | __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
macro to configure the FMC clock source.
#define | __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))
macro to get the FMC clock source.
#define | __HAL_RCC_USB_CONFIG(__USBCLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
Macro to configure the USB clock (USBCLK).
#define | __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)))
Macro to get the USB clock source.
#define | __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
Macro to configure the ADC clock.
#define | __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))
Macro to get the ADC clock source.
#define | __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
Macro to configure the SWPMI1 clock.
#define | __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))
Macro to get the SWPMI1 clock source.
#define | __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
Macro to configure the DFSDM1 clock.
#define | __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)))
Macro to get the DFSDM1 clock source.
#define | __HAL_RCC_CEC_CONFIG(__CECCLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
macro to configure the CEC clock (CECCLK).
#define | __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)))
macro to get the CEC clock source.
#define | __HAL_RCC_CLKP_CONFIG(__CLKPSource__) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
Macro to configure the CLKP : Oscillator clock for peripheral.
#define | __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)))
Macro to get the Oscillator clock for peripheral source.
#define | __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
Macro to configure the FDCAN clock.
#define | __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)))
Macro to get the FDCAN clock.
#define | __HAL_RCC_SPI1_CONFIG(__RCC_SPI1CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI1CLKSource__))
Macro to Configure the SPI1 clock source.
#define | __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
Macro to get the SPI1 clock source.
#define | __HAL_RCC_SPI2_CONFIG(__RCC_SPI2CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI2CLKSource__))
Macro to Configure the SPI2 clock source.
#define | __HAL_RCC_GET_SPI2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
Macro to get the SPI2 clock source.
#define | __HAL_RCC_SPI3_CONFIG(__RCC_SPI3CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI3CLKSource__))
Macro to Configure the SPI3 clock source.
#define | __HAL_RCC_GET_SPI3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
Macro to get the SPI3 clock source.
#define | __HAL_RCC_SPI4_CONFIG(__RCC_SPI4CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI4CLKSource__))
Macro to Configure the SPI4 clock source.
#define | __HAL_RCC_GET_SPI4_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
Macro to get the SPI4 clock source.
#define | __HAL_RCC_SPI5_CONFIG(__RCC_SPI5CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI5CLKSource__))
Macro to Configure the SPI5 clock source.
#define | __HAL_RCC_GET_SPI5_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
Macro to get the SPI5 clock source.
#define | __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
Macro to Configure the SPI6 clock source.
#define | __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))
Macro to get the SPI6 clock source.
#define | __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
Macro to configure the SDMMC clock.
#define | __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)))
Macro to get the SDMMC clock.
#define | __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
macro to configure the RNG clock (RNGCLK).
#define | __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)))
macro to get the RNG clock source.
#define | __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
Enable the specified CRS interrupts.
#define | __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
Disable the specified CRS interrupts.
#define | __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the CRS interrupt has occurred or not.
#define | RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
Clear the CRS interrupt pending bits.
#define | __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)
#define | __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
Check whether the specified CRS flag is set or not.
#define | RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
Clear the CRS specified FLAG.
#define | __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)

Define Documentation

#define __HAL_RCC_ADC_CONFIG ( __ADCCLKSource__ ) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))

Macro to configure the ADC clock.

Parameters:
__ADCCLKSource__,: specifies the ADC digital interface clock source. This parameter can be one of the following values:
  • RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock

Definition at line 2075 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_CEC_CONFIG ( __CECCLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))

macro to configure the CEC clock (CECCLK).

Parameters:
__CECCLKSource__,: specifies the CEC clock source. This parameter can be one of the following values:
  • RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
  • RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
  • RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock

Definition at line 2126 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_CLKP_CONFIG ( __CLKPSource__ ) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))

Macro to configure the CLKP : Oscillator clock for peripheral.

Parameters:
__CLKPSource__,: specifies Oscillator clock for peripheral This parameter can be one of the following values:
  • RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
  • RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
  • RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral

Definition at line 2145 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_CLEAR_FLAG ( __FLAG__ )
Value:
do { \
                                                 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \
                                                 { \
                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
                                                 } \
                                                 else \
                                                 { \
                                                   WRITE_REG(CRS->ICR, (__FLAG__)); \
                                                 } \
                                               } while(0)

Definition at line 2497 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define __HAL_RCC_CRS_CLEAR_IT ( __INTERRUPT__ )
Value:
do { \
                                                 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
                                                 { \
                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
                                                 } \
                                                 else \
                                                 { \
                                                   WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
                                                 } \
                                               } while(0)

Definition at line 2453 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_DISABLE_IT ( __INTERRUPT__ ) CLEAR_BIT(CRS->CR, (__INTERRUPT__))

Disable the specified CRS interrupts.

Parameters:
__INTERRUPT__ specifies the CRS interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RCC_CRS_IT_SYNCOK SYNC event OK interrupt
  • RCC_CRS_IT_SYNCWARN SYNC warning interrupt
  • RCC_CRS_IT_ERR Synchronization or trimming error interrupt
  • RCC_CRS_IT_ESYNC Expected SYNC interrupt
Return values:
None

Definition at line 2426 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_ENABLE_IT ( __INTERRUPT__ ) SET_BIT(CRS->CR, (__INTERRUPT__))

Enable the specified CRS interrupts.

Parameters:
__INTERRUPT__ specifies the CRS interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RCC_CRS_IT_SYNCOK SYNC event OK interrupt
  • RCC_CRS_IT_SYNCWARN SYNC warning interrupt
  • RCC_CRS_IT_ERR Synchronization or trimming error interrupt
  • RCC_CRS_IT_ESYNC Expected SYNC interrupt
Return values:
None

Definition at line 2414 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_GET_FLAG ( __FLAG__ ) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))

Check whether the specified CRS flag is set or not.

Parameters:
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • RCC_CRS_FLAG_SYNCOK SYNC event OK
  • RCC_CRS_FLAG_SYNCWARN SYNC warning
  • RCC_CRS_FLAG_ERR Error
  • RCC_CRS_FLAG_ESYNC Expected SYNC
  • RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
  • RCC_CRS_FLAG_SYNCERR SYNC error
  • RCC_CRS_FLAG_SYNCMISS SYNC missed
Return values:
The new state of _FLAG_ (TRUE or FALSE).

Definition at line 2477 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define __HAL_RCC_CRS_GET_IT_SOURCE ( __INTERRUPT__ ) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the CRS interrupt has occurred or not.

Parameters:
__INTERRUPT__ specifies the CRS interrupt source to check. This parameter can be one of the following values:
  • RCC_CRS_IT_SYNCOK SYNC event OK interrupt
  • RCC_CRS_IT_SYNCWARN SYNC warning interrupt
  • RCC_CRS_IT_ERR Synchronization or trimming error interrupt
  • RCC_CRS_IT_ESYNC Expected SYNC interrupt
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 2437 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_DFSDM1_CONFIG ( __DFSDM1CLKSource__ ) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))

Macro to configure the DFSDM1 clock.

Parameters:
__DFSDM1CLKSource__,: specifies the DFSDM1 clock source. This parameter can be one of the following values:
  • RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock
  • RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock

Definition at line 2108 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_FDCAN_CONFIG ( __FDCANCLKSource__ ) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))

Macro to configure the FDCAN clock.

Parameters:
__FDCANCLKSource__,: specifies clock source for FDCAN This parameter can be one of the following values:
  • RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
  • RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
  • RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock

Definition at line 2164 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_FMC_CONFIG ( __FMCCLKSource__ ) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))

macro to configure the FMC clock source.

Return values:
The clock source can be one of the following values:
  • RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
  • RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock
  • RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock
  • RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock

Definition at line 2036 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_GET_ADC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))

Macro to get the ADC clock source.

Return values:
The clock source can be one of the following values:
  • RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock

Definition at line 2084 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_CEC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)))

macro to get the CEC clock source.

Return values:
The clock source can be one of the following values:
  • RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
  • RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
  • RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock

Definition at line 2135 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_CLKP_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)))

Macro to get the Oscillator clock for peripheral source.

Return values:
The clock source can be one of the following values:
  • RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
  • RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
  • RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral

Definition at line 2154 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_DFSDM1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)))

Macro to get the DFSDM1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock
  • RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock

Definition at line 2116 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_FDCAN_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)))

Macro to get the FDCAN clock.

Return values:
The clock source can be one of the following values:
  • RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
  • RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
  • RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock

Definition at line 2173 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_FMC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))

macro to get the FMC clock source.

Return values:
The clock source can be one of the following values:
  • RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
  • RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock
  • RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock
  • RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock

Definition at line 2047 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_I2C1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))

macro to get the I2C1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock

Definition at line 1598 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_I2C2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))

macro to get the I2C2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock

Definition at line 1619 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_I2C3_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))

macro to get the I2C3 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock

Definition at line 1640 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_I2C4_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))

macro to get the I2C4 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock

Definition at line 1661 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_LPTIM1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))

macro to get the LPTIM1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock

Definition at line 1910 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_LPTIM2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))

macro to get the LPTIM2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock

Definition at line 1934 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_LPTIM3_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))

macro to get the LPTIM3 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock

Definition at line 1958 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_LPTIM4_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))

macro to get the LPTIM4 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
  • RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
  • RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
  • RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
  • RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
  • RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock

Definition at line 1982 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_LPTIM5_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))

macro to get the LPTIM5 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
  • RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
  • RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
  • RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
  • RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
  • RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock

Definition at line 2006 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_LPUART1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))

macro to get the LPUART1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock

Definition at line 1886 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_QSPI_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)))

macro to get the QSPI clock source.

Return values:
The clock source can be one of the following values:
  • RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock
  • RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock
  • RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock
  • RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock

Definition at line 2026 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_RNG_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)))

macro to get the RNG clock source.

Return values:
The clock source can be one of the following values:
  • RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
  • RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
  • RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
  • RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock

Definition at line 2365 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SAI1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL)))

Macro to get the SAI1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SAI1CLK_PLL: SAI1 clock = PLL
  • RCC_SAI1CLK_PLL2: SAI1 clock = PLL2
  • RCC_SAI1CLK_PLL3: SAI1 clock = PLL3
  • RCC_SAI1CLK_CLKP: SAI1 clock = CLKP
  • RCC_SAI1CLK_PIN: SAI1 clock = External Clock

Definition at line 1458 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SAI2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))

Macro to get the SAI2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SAI2CLK_PLL: SAI2 clock = PLL
  • RCC_SAI2CLK_PLL2: SAI2 clock = PLL2
  • RCC_SAI2CLK_PLL3: SAI2 clock = PLL3
  • RCC_SAI2CLK_CLKP: SAI2 clock = CLKP
  • RCC_SAI2CLK_PIN: SAI2 clock = External Clock

Definition at line 1502 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SAI3_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))

Macro to get the SAI3 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SAI3CLK_PLL: SAI3 clock = PLL
  • RCC_SAI3CLK_PLL2: SAI3 clock = PLL2
  • RCC_SAI3CLK_PLL3: SAI3 clock = PLL3
  • RCC_SAI3CLK_CLKP: SAI3 clock = CLKP
  • RCC_SAI3CLK_PIN: SAI3 clock = External Clock

Definition at line 1527 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SAI4A_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL)))

Macro to get the SAI4A clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SAI4ACLK_PLL: SAI4B clock = PLL
  • RCC_SAI4ACLK_PLL2: SAI4B clock = PLL2
  • RCC_SAI4ACLK_PLL3: SAI4B clock = PLL3
  • RCC_SAI4ACLK_CLKP: SAI4B clock = CLKP
  • RCC_SAI4ACLK_PIN: SAI4B clock = External Clock

Definition at line 1552 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SAI4B_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))

Macro to get the SAI4B clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SAI4BCLK_PLL: SAI4B clock = PLL
  • RCC_SAI4BCLK_PLL2: SAI4B clock = PLL2
  • RCC_SAI4BCLK_PLL3: SAI4B clock = PLL3
  • RCC_SAI4BCLK_CLKP: SAI4B clock = CLKP
  • RCC_SAI4BCLK_PIN: SAI4B clock = External Clock

Definition at line 1577 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SDMMC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)))

Macro to get the SDMMC clock.

Definition at line 2344 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SPDIFRX_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)))

Macro to get the SPDIFRX clock source.

Return values:
None

Definition at line 1477 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SPI1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))

Macro to get the SPI1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SPI1CLK_PLL: SPI1 clock = PLL
  • RCC_SPI1CLK_PLL2: SPI1 clock = PLL2
  • RCC_SPI1CLK_PLL3: SPI1 clock = PLL3
  • RCC_SPI1CLK_CLKP: SPI1 clock = CLKP
  • RCC_SPI1CLK_PIN: SPI1 clock = External Clock

Definition at line 2198 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SPI2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))

Macro to get the SPI2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SPI2CLK_PLL: SPI2 clock = PLL
  • RCC_SPI2CLK_PLL2: SPI2 clock = PLL2
  • RCC_SPI2CLK_PLL3: SPI2 clock = PLL3
  • RCC_SPI2CLK_CLKP: SPI2 clock = CLKP
  • RCC_SPI2CLK_PIN: SPI2 clock = External Clock

Definition at line 2223 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SPI3_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))

Macro to get the SPI3 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SPI3CLK_PLL: SPI3 clock = PLL
  • RCC_SPI3CLK_PLL2: SPI3 clock = PLL2
  • RCC_SPI3CLK_PLL3: SPI3 clock = PLL3
  • RCC_SPI3CLK_CLKP: SPI3 clock = CLKP
  • RCC_SPI3CLK_PIN: SPI3 clock = External Clock

Definition at line 2248 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SPI4_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))

Macro to get the SPI4 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
  • RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2
  • RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3
  • RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI
  • RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI
  • RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE

Definition at line 2276 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SPI5_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))

Macro to get the SPI5 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
  • RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2
  • RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3
  • RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI
  • RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI
  • RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE

Definition at line 2304 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SPI6_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))

Macro to get the SPI6 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
  • RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2
  • RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3
  • RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI
  • RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI
  • RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE

Definition at line 2331 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SWPMI1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))

Macro to get the SWPMI1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock
  • RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock

Definition at line 2100 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_UART4_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))

macro to get the UART4 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
  • RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock

Definition at line 1761 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_UART5_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))

macro to get the UART5 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
  • RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock

Definition at line 1786 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_UART7_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))

macro to get the UART7 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
  • RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock

Definition at line 1836 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_UART8_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))

macro to get the UART8 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
  • RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock

Definition at line 1861 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_USART1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))

macro to get the USART1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
  • RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock

Definition at line 1686 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_USART2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))

macro to get the USART2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
  • RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock

Definition at line 1711 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_USART3_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))

macro to get the USART3 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
  • RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock

Definition at line 1736 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_USART6_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))

macro to get the USART6 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
  • RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock

Definition at line 1811 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_USB_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)))

Macro to get the USB clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock
  • RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock
  • RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock

Definition at line 2065 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_I2C1_CONFIG ( __I2C1CLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1CLKSource__))

macro to configure the I2C1 clock (I2C1CLK).

Parameters:
__I2C1CLKSource__,: specifies the I2C1 clock source. This parameter can be one of the following values:
  • RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock

Definition at line 1588 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_I2C2_CONFIG ( __I2C2CLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C2CLKSource__))

macro to configure the I2C2 clock (I2C2CLK).

Parameters:
__I2C2CLKSource__,: specifies the I2C2 clock source. This parameter can be one of the following values:
  • RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock

Definition at line 1609 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_I2C3_CONFIG ( __I2C3CLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C3CLKSource__))

macro to configure the I2C3 clock (I2C3CLK).

Parameters:
__I2C3CLKSource__,: specifies the I2C3 clock source. This parameter can be one of the following values:
  • RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock

Definition at line 1630 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_I2C4_CONFIG ( __I2C4CLKSource__ ) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))

macro to configure the I2C4 clock (I2C4CLK).

Parameters:
__I2C4CLKSource__,: specifies the I2C4 clock source. This parameter can be one of the following values:
  • RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock

Definition at line 1651 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_LPTIM1_CONFIG ( __LPTIM1CLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))

macro to get the LPTIM1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock

Definition at line 1897 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_LPTIM2_CONFIG ( __LPTIM2CLKSource__ ) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))

macro to get the LPTIM2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock

Definition at line 1921 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_LPTIM3_CONFIG ( __LPTIM3CLKSource__ ) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM3CLKSource__))

macro to get the LPTIM3 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock

Definition at line 1945 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_LPTIM4_CONFIG ( __LPTIM4CLKSource__ ) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM4CLKSource__))

macro to get the LPTIM4 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
  • RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
  • RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
  • RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
  • RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
  • RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock

Definition at line 1969 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_LPTIM5_CONFIG ( __LPTIM5CLKSource__ ) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM5CLKSource__))

macro to configure the LPTIM5 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
  • RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
  • RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
  • RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
  • RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
  • RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock

Definition at line 1993 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_LPUART1_CONFIG ( __LPUART1CLKSource__ ) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))

macro to configure the LPUART1 clock (LPUART1CLK).

Parameters:
__LPUART1CLKSource__,: specifies the LPUART1 clock source. This parameter can be one of the following values:
  • RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock

Definition at line 1874 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLL2_CONFIG | ( | __PLL2M__,
 |  | __PLL2N__,
 |  | __PLL2P__,
 |  | __PLL2Q__,
 |  | __PLL2R__
 | ) |
Value:
do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U));  \
                         WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \
                                   ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \
                       } while(0)

Macro to configures the PLL2 multiplication and division factors.

Note:
This function must be used only when PLL2 is disabled.
Parameters:
__PLL2M__,: specifies the division factor for PLL2 VCO input clock This parameter must be a number between 1 and 63.
Note:
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 16 MHz.
Parameters:
__PLL2N__,: specifies the multiplication factor for PLL2 VCO output clock This parameter must be a number between 4 and 512.
Note:
You have to set the PLL2N parameter correctly to ensure that the VCO output frequency is between 150 and 420 MHz (when in medium VCO range) or between 192 and 836 MHZ (when in wide VCO range)
Parameters:
__PLL2P__,: specifies the division factor for peripheral kernel clocks This parameter must be a number between 2 and 128 (where odd numbers not allowed)
__PLL2Q__,: specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128
__PLL2R__,: specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128
Return values:
None

Definition at line 1283 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL2_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)

Definition at line 1229 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL2_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_PLL2ON)

Macros to enable or disable PLL2.

Note:
After enabling PLL2, the application software should wait on PLL2RDY flag to be set indicating that PLL2 clock is stable and can be used as kernel clock source.
PLL2 is disabled by hardware when entering STOP and STANDBY modes.

Definition at line 1228 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL2_VCIRANGE ( __RCC_PLL2VCIRange__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))

Macro to select the PLL2 reference frequency range.

Parameters:
__RCC_PLL2VCIRange__,: specifies the PLL2 input frequency range This parameter can be one of the following values:
  • RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz
  • RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz
  • RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz
  • RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz
Return values:
None

Definition at line 1314 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL2_VCORANGE ( __RCC_PLL2VCORange__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))

Macro to select the PLL2 reference frequency range.

Parameters:
__RCC_PLL2VCORange__,: Specifies the PLL2 input frequency range This parameter can be one of the following values:
  • RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz
  • RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz
Return values:
None

Definition at line 1325 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL2_Config().

#define __HAL_RCC_PLL2CLKOUT_DISABLE ( __RCC_PLL2ClockOut__ ) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))

Definition at line 1244 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLL2CLKOUT_ENABLE ( __RCC_PLL2ClockOut__ ) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))

Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)

Note:
Enabling/disabling Those Clocks can be any time without the need to stop the PLL2, This is mainly used to save Power.
Parameters:
__RCC_PLL2ClockOut__,: Specifies the PLL2 clock to be outputted This parameter can be one of the following values:
  • RCC_PLL2_DIVP: This clock is used to generate system clock (up to 400MHZ)
  • RCC_PLL2_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ)
  • RCC_PLL2_DIVR: This clock is used to generate peripherals clock (up to 400MHZ)
Return values:
None

Definition at line 1242 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLL2FRACN_CONFIG ( __RCC_PLL2FRACN__ ) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,(uint32_t)(__RCC_PLL2FRACN__) << POSITION_VAL(RCC_PLL2FRACR_FRACN2))

Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor.

Note:
These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO
Parameters:
__RCC_PLL2FRACN__,: Specifies Fractional Part Of The Multiplication factor for PLL2 VCO It should be a value between 0 and 8191
Note:
Warning: the software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: 192 to 836 MHz if PLL2VCOSEL = 0 150 to 420 MHz if PLL2VCOSEL = 1.
Return values:
None

Definition at line 1303 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLL2FRACN_DISABLE ( ) CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)

Definition at line 1253 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLL2FRACN_ENABLE ( ) SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)

Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO.

Note:
Enabling/disabling Fractional Part can be any time without the need to stop the PLL2
Return values:
None

Definition at line 1251 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLL3_CONFIG | ( | __PLL3M__,
 |  | __PLL3N__,
 |  | __PLL3P__,
 |  | __PLL3Q__,
 |  | __PLL3R__
 | ) |
Value:
do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U));  \
                         WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \
                                   ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \
                       } while(0)

Macro to configures the PLL3 multiplication and division factors.

Note:
This function must be used only when PLL3 is disabled.
Parameters:
__PLL3M__,: specifies the division factor for PLL3 VCO input clock This parameter must be a number between 1 and 63.
Note:
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 16 MHz.
Parameters:
__PLL3N__,: specifies the multiplication factor for PLL3 VCO output clock This parameter must be a number between 4 and 512.
Note:
You have to set the PLL3N parameter correctly to ensure that the VCO output frequency is between 150 and 420 MHz (when in medium VCO range) or between 192 and 836 MHZ (when in wide VCO range)
Parameters:
__PLL3P__,: specifies the division factor for peripheral kernel clocks This parameter must be a number between 2 and 128 (where odd numbers not allowed)
__PLL3Q__,: specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128
__PLL3R__,: specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128
Return values:
None

Definition at line 1388 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_PLL3_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)

Definition at line 1335 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_PLL3_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_PLL3ON)

Macros to enable or disable the main PLL3.

Note:
After enabling PLL3, the application software should wait on PLL3RDY flag to be set indicating that PLL3 clock is stable and can be used as kernel clock source.
PLL3 is disabled by hardware when entering STOP and STANDBY modes.

Definition at line 1334 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_PLL3_VCIRANGE ( __RCC_PLL3VCIRange__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))

Macro to select the PLL3 reference frequency range.

Parameters:
__RCC_PLL3VCIRange__,: specifies the PLL1 input frequency range This parameter can be one of the following values:
  • RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz
  • RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz
  • RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz
  • RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz
Return values:
None

Definition at line 1422 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_PLL3_VCORANGE ( __RCC_PLL3VCORange__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))

Macro to select the PLL3 reference frequency range.

Parameters:
__RCC_PLL3VCORange__,: specifies the PLL1 input frequency range This parameter can be one of the following values:
  • RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz
  • RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz
Return values:
None

Definition at line 1433 of file stm32h7xx_hal_rcc_ex.h.

Referenced by RCCEx_PLL3_Config().

#define __HAL_RCC_PLL3CLKOUT_DISABLE ( __RCC_PLL3ClockOut__ ) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))

Definition at line 1359 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLL3CLKOUT_ENABLE ( __RCC_PLL3ClockOut__ ) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))

Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)

Note:
Enabling/disabling Those Clocks can be any time without the need to stop the PLL3, This is mainly used to save Power.
Parameters:
__RCC_PLL3ClockOut__,: specifies the PLL3 clock to be outputted This parameter can be one of the following values:
  • RCC_PLL3_DIVP: This clock is used to generate system clock (up to 400MHZ)
  • RCC_PLL3_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ)
  • RCC_PLL3_DIVR: This clock is used to generate peripherals clock (up to 400MHZ)
Return values:
None

Definition at line 1357 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLL3FRACN_CONFIG ( __RCC_PLL3FRACN__ ) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << POSITION_VAL(RCC_PLL3FRACR_FRACN3))

Macro to configures PLL3 clock Fractional Part of The Multiplication Factor.

Note:
These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO
Parameters:
__RCC_PLL3FRACN__,: specifies Fractional Part Of The Multiplication Factor for PLL3 VCO It should be a value between 0 and 8191
Note:
Warning: the software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: 192 to 836 MHz if PLL3VCOSEL = 0 150 to 420 MHz if PLL3VCOSEL = 1.
Return values:
None

Definition at line 1411 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLL3FRACN_DISABLE ( ) CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)

Definition at line 1344 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLL3FRACN_ENABLE ( ) SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)

Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO.

Note:
Enabling/disabling Fractional Part can be any time without the need to stop the PLL3
Return values:
None

Definition at line 1342 of file stm32h7xx_hal_rcc_ex.h.

#define __HAL_RCC_QSPI_CONFIG ( __QSPICLKSource__ ) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__))

macro to configure the QSPI clock source.

Return values:
The clock source can be one of the following values:
  • RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock
  • RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock
  • RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock
  • RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock

Definition at line 2015 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_RNG_CONFIG ( __RNGCLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))

macro to configure the RNG clock (RNGCLK).

Parameters:
__RNGCLKSource__,: specifies the RNG clock source. This parameter can be one of the following values:
  • RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
  • RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
  • RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
  • RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock

Definition at line 2355 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SAI1_CONFIG ( __RCC_SAI1CLKSource__ ) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))

Macro to Configure the SAI1 clock source.

Parameters:
__RCC_SAI1CLKSource__,: defines the SAI1 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:
  • RCC_SAI1CLK_PLL: SAI1 clock = PLL
  • RCC_SAI1CLK_PLL2: SAI1 clock = PLL2
  • RCC_SAI1CLK_PLL3: SAI1 clock = PLL3
  • RCC_SAI1CLK_OSC: SAI1 clock = OSC
  • RCC_SAI1CLK_PIN: SAI1 clock = External Clock
Return values:
None

Definition at line 1447 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SAI2_CONFIG ( __RCC_SAI2CLKSource__ ) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI2CLKSource__))

Macro to Configure the SAI2 clock source.

Parameters:
__RCC_SAI2CLKSource__,: defines the SAI2 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:
  • RCC_SAI2CLK_PLL: SAI2 clock = PLL
  • RCC_SAI2CLK_PLL2: SAI2 clock = PLL2
  • RCC_SAI2CLK_PLL3: SAI2 clock = PLL3
  • RCC_SAI2CLK_CLKP: SAI2 clock = CLKP
  • RCC_SAI2CLK_PIN: SAI2 clock = External Clock
Return values:
None

Definition at line 1491 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SAI3_CONFIG ( __RCC_SAI3CLKSource__ ) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI3CLKSource__))

Macro to Configure the SAI3 clock source.

Parameters:
__RCC_SAI3CLKSource__,: defines the SAI3 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:
  • RCC_SAI3CLK_PLL: SAI3 clock = PLL
  • RCC_SAI3CLK_PLL2: SAI3 clock = PLL2
  • RCC_SAI3CLK_PLL3: SAI3 clock = PLL3
  • RCC_SAI3CLK_CLKP: SAI3 clock = CLKP
  • RCC_SAI3CLK_PIN: SAI3 clock = External Clock
Return values:
None

Definition at line 1516 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SAI4A_CONFIG ( __RCC_SAI4ACLKSource__ ) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))

Macro to Configure the SAI4A clock source.

Parameters:
__RCC_SAI4ACLKSource__,: defines the SAI4A clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:
  • RCC_SAI4ACLK_PLL: SAI4A clock = PLL
  • RCC_SAI4ACLK_PLL2: SAI4A clock = PLL2
  • RCC_SAI4ACLK_PLL3: SAI4A clock = PLL3
  • RCC_SAI4ACLK_CLKP: SAI4A clock = CLKP
  • RCC_SAI4ACLK_PIN: SAI4A clock = External Clock
Return values:
None

Definition at line 1541 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SAI4B_CONFIG ( __RCC_SAI4BCLKSource__ ) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))

Macro to Configure the SAI4B clock source.

Parameters:
__RCC_SAI4BCLKSource__,: defines the SAI4B clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:
  • RCC_SAI4BCLK_PLL: SAI4B clock = PLL
  • RCC_SAI4BCLK_PLL2: SAI4B clock = PLL2
  • RCC_SAI4BCLK_PLL3: SAI4B clock = PLL3
  • RCC_SAI4BCLK_CLKP: SAI4B clock = CLKP
  • RCC_SAI4BCLK_PIN: SAI4B clock = External Clock
Return values:
None

Definition at line 1566 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SDMMC_CONFIG ( __SDMMCCLKSource__ ) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))

Macro to configure the SDMMC clock.

Parameters:
__SDMMCCLKSource__,: specifies clock source for SDMMC This parameter can be one of the following values:
  • RCC_SDMMCCLKSOURCE_PLL: PLLQ selected as SDMMC clock
  • RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock

Definition at line 2339 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SPDIFRX_CONFIG ( __RCC_SPDIFCLKSource__ ) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))

Macro to Configure the SPDIFRX clock source.

Parameters:
__RCC_SPDIFCLKSource__,: defines the SPDIFRX clock source. This clock is derived from system PLL, PLL2, PLL3, or internal OSC clock This parameter can be one of the following values:
  • RCC_SPDIFRXCLKSOURCE_PLL: SPDIFRX clock = PLL
  • RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2
  • RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3
  • RCC_SPDIFRXCLKSOURCE_HSI: SPDIFRX clock = HSI
Return values:
None

Definition at line 1471 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SPI1_CONFIG ( __RCC_SPI1CLKSource__ ) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI1CLKSource__))

Macro to Configure the SPI1 clock source.

Parameters:
__RCC_SPI1CLKSource__,: defines the SPI1 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:
  • RCC_SPI1CLK_PLL: SPI1 clock = PLL
  • RCC_SPI1CLK_PLL2: SPI1 clock = PLL2
  • RCC_SPI1CLK_PLL3: SPI1 clock = PLL3
  • RCC_SPI1CLK_CLKP: SPI1 clock = CLKP
  • RCC_SPI1CLK_PIN: SPI1 clock = External Clock
Return values:
None

Definition at line 2187 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SPI2_CONFIG ( __RCC_SPI2CLKSource__ ) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI2CLKSource__))

Macro to Configure the SPI2 clock source.

Parameters:
__RCC_SPI2CLKSource__,: defines the SPI2 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:
  • RCC_SPI2CLK_PLL: SPI2 clock = PLL
  • RCC_SPI2CLK_PLL2: SPI2 clock = PLL2
  • RCC_SPI2CLK_PLL3: SPI2 clock = PLL3
  • RCC_SPI2CLK_CLKP: SPI2 clock = CLKP
  • RCC_SPI2CLK_PIN: SPI2 clock = External Clock
Return values:
None

Definition at line 2212 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SPI3_CONFIG ( __RCC_SPI3CLKSource__ ) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI3CLKSource__))

Macro to Configure the SPI3 clock source.

Parameters:
__RCC_SPI3CLKSource__,: defines the SPI3 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:
  • RCC_SPI3CLK_PLL: SPI3 clock = PLL
  • RCC_SPI3CLK_PLL2: SPI3 clock = PLL2
  • RCC_SPI3CLK_PLL3: SPI3 clock = PLL3
  • RCC_SPI3CLK_CLKP: SPI3 clock = CLKP
  • RCC_SPI3CLK_PIN: SPI3 clock = External Clock
Return values:
None

Definition at line 2237 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SPI4_CONFIG ( __RCC_SPI4CLKSource__ ) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI4CLKSource__))

Macro to Configure the SPI4 clock source.

Parameters:
__RCC_SPI4CLKSource__,: defines the SPI4 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values:
  • RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
  • RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2
  • RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3
  • RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI
  • RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI
  • RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE
Return values:
None

Definition at line 2264 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SPI5_CONFIG ( __RCC_SPI5CLKSource__ ) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI5CLKSource__))

Macro to Configure the SPI5 clock source.

Parameters:
__RCC_SPI5CLKSource__,: defines the SPI5 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values:
  • RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
  • RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2
  • RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3
  • RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI
  • RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI
  • RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE
Return values:
None

Definition at line 2292 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SPI6_CONFIG ( __RCC_SPI6CLKSource__ ) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))

Macro to Configure the SPI6 clock source.

Parameters:
__RCC_SPI6CLKSource__,: defines the SPI6 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values:
  • RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
  • RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2
  • RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3
  • RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI
  • RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI
  • RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE
Return values:
None

Definition at line 2319 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SWPMI1_CONFIG ( __SWPMI1CLKSource__ ) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))

Macro to configure the SWPMI1 clock.

Parameters:
__SWPMI1CLKSource__,: specifies the SWPMI1 clock source. This parameter can be one of the following values:
  • RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock
  • RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock

Definition at line 2092 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_UART4_CONFIG ( __UART4CLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART4CLKSource__))

macro to configure the UART4 clock (UART4CLK).

Parameters:
__UART4CLKSource__,: specifies the UART4 clock source. This parameter can be one of the following values:
  • RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
  • RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock

Definition at line 1749 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_UART5_CONFIG ( __UART5CLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART5CLKSource__))

macro to configure the UART5 clock (UART5CLK).

Parameters:
__UART5CLKSource__,: specifies the UART5 clock source. This parameter can be one of the following values:
  • RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
  • RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock

Definition at line 1774 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_UART7_CONFIG ( __UART7CLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART7CLKSource__))

macro to configure the UART5 clock (UART7CLK).

Parameters:
__UART7CLKSource__,: specifies the UART7 clock source. This parameter can be one of the following values:
  • RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
  • RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock

Definition at line 1824 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_UART8_CONFIG ( __UART8CLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART8CLKSource__))

macro to configure the UART8 clock (UART8CLK).

Parameters:
__UART8CLKSource__,: specifies the UART8 clock source. This parameter can be one of the following values:
  • RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
  • RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock

Definition at line 1849 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART1_CONFIG ( __USART1CLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART1CLKSource__))

macro to configure the USART1 clock (USART1CLK).

Parameters:
__USART1CLKSource__,: specifies the USART1 clock source. This parameter can be one of the following values:
  • RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
  • RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock

Definition at line 1674 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART2_CONFIG ( __USART2CLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART2CLKSource__))

macro to configure the USART2 clock (USART2CLK).

Parameters:
__USART2CLKSource__,: specifies the USART2 clock source. This parameter can be one of the following values:
  • RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
  • RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock

Definition at line 1699 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART3_CONFIG ( __USART3CLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART3CLKSource__))

macro to configure the USART3 clock (USART3CLK).

Parameters:
__USART3CLKSource__,: specifies the USART3 clock source. This parameter can be one of the following values:
  • RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
  • RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock

Definition at line 1724 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART6_CONFIG ( __USART6CLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART6CLKSource__))

macro to configure the USART6 clock (USART6CLK).

Parameters:
__USART6CLKSource__,: specifies the USART6 clock source. This parameter can be one of the following values:
  • RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
  • RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock

Definition at line 1799 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USB_CONFIG ( __USBCLKSource__ ) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))

Macro to configure the USB clock (USBCLK).

Parameters:
__USBCLKSource__,: specifies the USB clock source. This parameter can be one of the following values:
  • RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock
  • RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock
  • RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock

Definition at line 2056 of file stm32h7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))

Clear the CRS specified FLAG.

Parameters:
__FLAG__ specifies the flag to clear. This parameter can be one of the following values:
  • RCC_CRS_FLAG_SYNCOK SYNC event OK
  • RCC_CRS_FLAG_SYNCWARN SYNC warning
  • RCC_CRS_FLAG_ERR Error
  • RCC_CRS_FLAG_ESYNC Expected SYNC
  • RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
  • RCC_CRS_FLAG_SYNCERR SYNC error
  • RCC_CRS_FLAG_SYNCMISS SYNC missed
Note:
RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
Return values:
None

Definition at line 2495 of file stm32h7xx_hal_rcc_ex.h.

#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))

Clear the CRS interrupt pending bits.

Parameters:
__INTERRUPT__ specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
  • RCC_CRS_IT_SYNCOK SYNC event OK interrupt
  • RCC_CRS_IT_SYNCWARN SYNC warning interrupt
  • RCC_CRS_IT_ERR Synchronization or trimming error interrupt
  • RCC_CRS_IT_ESYNC Expected SYNC interrupt
  • RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
  • RCC_CRS_IT_SYNCERR SYNC error interrupt
  • RCC_CRS_IT_SYNCMISS SYNC missed interrupt

Definition at line 2451 of file stm32h7xx_hal_rcc_ex.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RCCEx_Exported_Functions_Group2

Functions
RCCEx_Exported_Functions_Group2
RCCEx

Functions

void | HAL_RCCEx_WakeUpStopCLKConfig (uint32_t WakeUpClk)
Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
void | HAL_RCCEx_KerWakeUpStopCLKConfig (uint32_t WakeUpClk)
Configure the oscillator Kernel clock source for wakeup from Stop.
void | HAL_RCCEx_EnableLSECSS (void)
Enables the LSE Clock Security System.
void | HAL_RCCEx_DisableLSECSS (void)
Disables the LSE Clock Security System.
void | HAL_RCCEx_WWDGxSysResetConfig (uint32_t RCC_WWDGx)
Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs.

Function Documentation

void HAL_RCCEx_DisableLSECSS ( void )

Disables the LSE Clock Security System.

Note:
LSE Clock Security System can only be disabled after a LSE failure detection.
Return values:
None

Definition at line 2838 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_DISABLE_IT, and RCC_IT_LSECSS.

void HAL_RCCEx_EnableLSECSS ( void )

Enables the LSE Clock Security System.

Note:
Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC clock with HAL_RCCEx_PeriphCLKConfig().
Return values:
None

Definition at line 2828 of file stm32h7xx_hal_rcc_ex.c.

void HAL_RCCEx_KerWakeUpStopCLKConfig ( uint32_t WakeUpClk )

Configure the oscillator Kernel clock source for wakeup from Stop.

Parameters:
WakeUpClk,: Kernel Wakeup clock This parameter can be one of the following values:
  • RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection
  • RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection
Return values:
None

Definition at line 2870 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG, assert_param, and IS_RCC_STOP_KERWAKEUPCLOCK.

void HAL_RCCEx_WakeUpStopCLKConfig ( uint32_t WakeUpClk )

Configure the oscillator clock source for wakeup from Stop and CSS backup clock.

Parameters:
WakeUpClk,: Wakeup clock This parameter can be one of the following values:
  • RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection
  • RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection
Note:
This function shall not be called after the Clock Security System on HSE has been enabled.
Return values:
None

Definition at line 2855 of file stm32h7xx_hal_rcc_ex.c.

References __HAL_RCC_WAKEUPSTOP_CLK_CONFIG, assert_param, and IS_RCC_STOP_WAKEUPCLOCK.

void HAL_RCCEx_WWDGxSysResetConfig ( uint32_t RCC_WWDGx )

Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs.

Parameters:
RCC_WWDGx,: WWDGx to be configured This parameter can be one of the following values:
  • RCC_WWDG1: WWDG1 generates system reset
Note:
This bit can be set by software but is cleared by hardware during a system reset
Return values:
None

Definition at line 2888 of file stm32h7xx_hal_rcc_ex.c.

References assert_param, and IS_RCC_SCOPE_WWDG.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RTC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initialize the RTC according to the specified parameters in the RTC_InitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC peripheral.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initialize the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
   [..] This section provide functions allowing to initialize and configure the
         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
         RTC registers Write protection, enter and exit the RTC initialization mode,
         RTC registers synchronization check and reference clock detection enable.
         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
             It is split into 2 programmable prescalers to minimize power consumption.
             (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
             (++) When both prescalers are used, it is recommended to configure the
                 asynchronous prescaler to a high value to minimize power consumption.
         (#) All RTC registers are Write protected. Writing to the RTC registers
             is enabled by writing a key into the Write Protection register, RTC_WPR.
         (#) To configure the RTC Calendar, user application should enter
             initialization mode. In this mode, the calendar counter is stopped
             and its value can be updated. When the initialization sequence is
             complete, the calendar restarts counting after 4 RTCCLK cycles.
         (#) To read the calendar through the shadow registers after Calendar
             initialization, calendar update or after wakeup from low power modes
             the software must first clear the RSF flag. The software must then
             wait until it is set again before reading the calendar, which means
             that the calendar registers have been correctly copied into the
             RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
             implements the above software sequence (RSF clear and RSF check).

Function Documentation

HAL_StatusTypeDef HAL_RTC_DeInit ( RTC_HandleTypeDef * hrtc )

DeInitialize the RTC peripheral.

Parameters:
hrtc,: RTC handle
Note:
This function doesn't reset the RTC Backup Data registers.
Return values:
HAL status

Definition at line 262 of file stm32h7xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_MspDeInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_RESET, HAL_RTC_STATE_TIMEOUT, HAL_RTC_WaitForSynchro(), RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_Init ( RTC_HandleTypeDef * hrtc )

Initialize the RTC according to the specified parameters in the RTC_InitTypeDef structure and initialize the associated handle.

Parameters:
hrtc,: RTC handle
Return values:
HAL status

Definition at line 186 of file stm32h7xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_InitTypeDef::AsynchPrediv, HAL_RTC_MspInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_RESET, RTC_InitTypeDef::HourFormat, RTC_HandleTypeDef::Init, RTC_HandleTypeDef::Instance, IS_RTC_ASYNCH_PREDIV, IS_RTC_HOUR_FORMAT, IS_RTC_OUTPUT, IS_RTC_OUTPUT_POL, IS_RTC_OUTPUT_REMAP, IS_RTC_OUTPUT_TYPE, IS_RTC_SYNCH_PREDIV, RTC_HandleTypeDef::Lock, RTC_InitTypeDef::OutPut, RTC_InitTypeDef::OutPutPolarity, RTC_InitTypeDef::OutPutRemap, RTC_InitTypeDef::OutPutType, RTC_EnterInitMode(), RTC_HandleTypeDef::State, and RTC_InitTypeDef::SynchPrediv.

void HAL_RTC_MspDeInit ( RTC_HandleTypeDef * hrtc )

DeInitialize the RTC MSP.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 380 of file stm32h7xx_hal_rtc.c.

Referenced by HAL_RTC_DeInit().

void HAL_RTC_MspInit ( RTC_HandleTypeDef * hrtc )

Initialize the RTC MSP.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 365 of file stm32h7xx_hal_rtc.c.

Referenced by HAL_RTC_Init().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Time and Date functions

Functions
RTC Time and Date functions
RTC Exported Functions

RTC Time and Date functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Set RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Get RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Set RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Get RTC current date.

Detailed Description

RTC Time and Date functions.

 ===============================================================================
                 ##### RTC Time and Date functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Time and Date features

Function Documentation

HAL_StatusTypeDef HAL_RTC_GetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Get RTC current date.

Parameters:
hrtc,: RTC handle
sDate,: Pointer to Date structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Note:
You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values in the higher-order calendar shadow registers to ensure consistency between the time and date values. Reading RTC current time locks the values in calendar shadow registers until Current date is read.
Return values:
HAL status

Definition at line 708 of file stm32h7xx_hal_rtc.c.

References assert_param, RTC_DateTypeDef::Date, RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_DR_RESERVED_MASK, RTC_FORMAT_BIN, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_GetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Get RTC current time.

Parameters:
hrtc,: RTC handle
sTime,: Pointer to Time structure with Hours, Minutes and Seconds fields returned with input format (BIN or BCD), also SubSeconds field returning the RTC_SSR register content and SecondFraction field the Synchronous pre-scaler factor to be used for second fraction ratio computation.
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Note:
You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds value in second fraction ratio with time unit following generic formula: Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values in the higher-order calendar shadow registers to ensure consistency between the time and date values. Reading RTC current time locks the values in calendar shadow registers until Current date is read to ensure consistency between the time and date values.
Return values:
HAL status

Definition at line 553 of file stm32h7xx_hal_rtc.c.

References assert_param, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::SecondFraction, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_SetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Set RTC current date.

Parameters:
hrtc,: RTC handle
sDate,: Pointer to date structure
Format,: specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 597 of file stm32h7xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_DateTypeDef::Date, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_WaitForSynchro(), RTC_HandleTypeDef::Instance, IS_RTC_DATE, IS_RTC_FORMAT, IS_RTC_MONTH, IS_RTC_WEEKDAY, IS_RTC_YEAR, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_DR_RESERVED_MASK, RTC_EnterInitMode(), RTC_FORMAT_BIN, RTC_HandleTypeDef::State, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_SetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Set RTC current time.

Parameters:
hrtc,: RTC handle
sTime,: Pointer to Time structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 418 of file stm32h7xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_TimeTypeDef::DayLightSaving, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_WaitForSynchro(), RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_DAYLIGHT_SAVING, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, IS_RTC_STORE_OPERATION, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_EnterInitMode(), RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, RTC_HandleTypeDef::State, RTC_TimeTypeDef::StoreOperation, and RTC_TimeTypeDef::TimeFormat.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Alarm functions

Functions
RTC Alarm functions
RTC Exported Functions

RTC Alarm functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Get the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Alarm interrupt request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle AlarmA Polling request.

Detailed Description

RTC Alarm functions.

 ===============================================================================
                 ##### RTC Alarm functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Alarm feature

Function Documentation

void HAL_RTC_AlarmAEventCallback ( RTC_HandleTypeDef * hrtc )

Alarm A callback.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 1321 of file stm32h7xx_hal_rtc.c.

Referenced by HAL_RTC_AlarmIRQHandler().

void HAL_RTC_AlarmIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle Alarm interrupt request.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 1276 of file stm32h7xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_EXTI_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARM_GET_IT_SOURCE, HAL_RTC_AlarmAEventCallback(), HAL_RTC_STATE_READY, HAL_RTCEx_AlarmBEventCallback(), RTC_FLAG_ALRAF, RTC_FLAG_ALRBF, RTC_IT_ALRA, RTC_IT_ALRB, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_DeactivateAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Alarm
 | ) |  |

Deactivate the specified RTC Alarm.

Parameters:
hrtc,: RTC handle
Alarm,: Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A: AlarmA
  • RTC_ALARM_B: AlarmB
Return values:
HAL status

Definition at line 1131 of file stm32h7xx_hal_rtc.c.

References __HAL_RTC_ALARM_DISABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, IS_RTC_ALARM, RTC_ALARM_A, RTC_FLAG_ALRAWF, RTC_FLAG_ALRBWF, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_GetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Alarm,
 |  | uint32_t | Format
 | ) |  |

Get the RTC Alarm value and masks.

Parameters:
hrtc,: RTC handle
sAlarm,: Pointer to Date structure
Alarm,: Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A: AlarmA
  • RTC_ALARM_B: AlarmB
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 1225 of file stm32h7xx_hal_rtc.c.

References RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmTime, assert_param, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARM_B, RTC_ALARMMASK_ALL, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle AlarmA Polling request.

Parameters:
hrtc,: RTC handle
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1337 of file stm32h7xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_ALRAF, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_SetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Set the specified RTC Alarm.

Parameters:
hrtc,: RTC handle
sAlarm,: Pointer to Alarm structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 762 of file stm32h7xx_hal_rtc.c.

References __HAL_RTC_ALARM_DISABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMA_ENABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_ALARMB_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmSubSecondMask, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_ALARM_MASK, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARMDATEWEEKDAYSEL_DATE, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_FLAG_ALRAWF, RTC_FLAG_ALRBWF, RTC_FORMAT_BIN, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, RTC_TimeTypeDef::Seconds, RTC_HandleTypeDef::State, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_SetAlarm_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Set the specified RTC Alarm with Interrupt.

Parameters:
hrtc,: RTC handle
sAlarm,: Pointer to Alarm structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Note:
The Alarm register can only be written when the corresponding Alarm is disabled (Use the HAL_RTC_DeactivateAlarm()).
The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
Return values:
HAL status

Definition at line 946 of file stm32h7xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_ENABLE_IT, __HAL_RTC_ALARM_EXTI_ENABLE_IT, __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMA_ENABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_ALARMB_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmSubSecondMask, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_ALARM_MASK, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARMDATEWEEKDAYSEL_DATE, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_FLAG_ALRAF, RTC_FLAG_ALRAWF, RTC_FLAG_ALRBF, RTC_FLAG_ALRBWF, RTC_FORMAT_BIN, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, RTC_TimeTypeDef::Seconds, RTC_HandleTypeDef::State, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RTC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                     ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Wait for RTC Time and Date Synchronization

Function Documentation

HAL_StatusTypeDef HAL_RTC_WaitForSynchro ( RTC_HandleTypeDef * hrtc )

Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Note:
The RTC Resynchronization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers.
Parameters:
hrtc,: RTC handle
Return values:
HAL status

Definition at line 1396 of file stm32h7xx_hal_rtc.c.

References HAL_GetTick(), RTC_HandleTypeDef::Instance, RTC_RSF_MASK, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeInit(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_SetSynchroShift().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
RTC Exported Functions

Peripheral State functions. More...

Functions

HAL_RTCStateTypeDef HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Return the RTC handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                     ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Get RTC state

Function Documentation

HAL_RTCStateTypeDef HAL_RTC_GetState ( RTC_HandleTypeDef * hrtc )

Return the RTC handle state.

Parameters:
hrtc,: RTC handle
Return values:
HAL state

Definition at line 1440 of file stm32h7xx_hal_rtc.c.

References RTC_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Private functions

Functions
RTC Private functions
RTC

Functions

HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enter the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.

Function Documentation

uint8_t RTC_Bcd2ToByte ( uint8_t Value )

Convert from 2 digit BCD to Binary.

Parameters:
Value,: BCD value to be converted
Return values:
Converted word

Definition at line 1512 of file stm32h7xx_hal_rtc.c.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_ByteToBcd2 ( uint8_t Value )

Convert a 2 digit decimal to BCD format.

Parameters:
Value,: Byte to be converted
Return values:
Converted byte

Definition at line 1494 of file stm32h7xx_hal_rtc.c.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), and HAL_RTC_SetTime().

HAL_StatusTypeDef RTC_EnterInitMode ( RTC_HandleTypeDef * hrtc )

Enter the RTC Initialization mode.

Note:
The RTC Initialization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
Parameters:
hrtc,: RTC handle
Return values:
HAL status

Definition at line 1464 of file stm32h7xx_hal_rtc.c.

References HAL_GetTick(), RTC_HandleTypeDef::Instance, RTC_INIT_MASK, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateRefClock(), and HAL_RTCEx_SetRefClock().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Exported Types

Data Structures | Enumerations
RTC Exported Types
RTC

Data Structures

struct | RTC_InitTypeDef
RTC Configuration Structure definition. More...
struct | RTC_TimeTypeDef
RTC Time structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | RTC_HandleTypeDef
Time Handle Structure definition. More...

Enumerations

enum HAL_RTCStateTypeDef {
HAL_RTC_STATE_RESET = 0x00, HAL_RTC_STATE_READY = 0x01, HAL_RTC_STATE_BUSY = 0x02, HAL_RTC_STATE_TIMEOUT = 0x03,
HAL_RTC_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_RTCStateTypeDef

HAL State structures definition.

Enumerator:
HAL_RTC_STATE_RESET

RTC not yet initialized or disabled

HAL_RTC_STATE_READY

RTC initialized and ready for use

HAL_RTC_STATE_BUSY

RTC process is ongoing

HAL_RTC_STATE_TIMEOUT

RTC timeout state

HAL_RTC_STATE_ERROR

RTC error state

Definition at line 64 of file stm32h7xx_hal_rtc.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_InitTypeDef Struct Reference
RTC Exported Types

RTC Configuration Structure definition. More...

#include <stm32h7xx_hal_rtc.h>

Data Fields

uint32_t | HourFormat
uint32_t | AsynchPrediv
uint32_t | SynchPrediv
uint32_t | OutPut
uint32_t | OutPutRemap
uint32_t | OutPutPolarity
uint32_t | OutPutType

Detailed Description

RTC Configuration Structure definition.

Definition at line 77 of file stm32h7xx_hal_rtc.h.

Field Documentation

uint32_t RTC_InitTypeDef::AsynchPrediv

Specifies the RTC Asynchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F

Definition at line 82 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::HourFormat

Specifies the RTC Hour Format. This parameter can be a value of RTC Hour Formats

Definition at line 79 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPut

Specifies which signal will be routed to the RTC output. This parameter can be a value of RTC Output Selection Definitions

Definition at line 88 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutPolarity

Specifies the polarity of the output signal. This parameter can be a value of RTC Output Polarity Definitions

Definition at line 94 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutRemap

Specifies the remap for RTC output. This parameter can be a value of RTC Output ALARM OUT Remap

Definition at line 91 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutType

Specifies the RTC Output Pin mode. This parameter can be a value of RTC Output Type ALARM OUT

Definition at line 97 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::SynchPrediv

Specifies the RTC Synchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF

Definition at line 85 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rtc.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC_TimeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_TimeTypeDef Struct Reference
RTC Exported Types

RTC Time structure definition. More...

#include <stm32h7xx_hal_rtc.h>

Data Fields

uint8_t | Hours
uint8_t | Minutes
uint8_t | Seconds
uint8_t | TimeFormat
uint32_t | SubSeconds
uint32_t | SecondFraction
uint32_t | DayLightSaving
uint32_t | StoreOperation

Detailed Description

RTC Time structure definition.

Definition at line 105 of file stm32h7xx_hal_rtc.h.

Field Documentation

uint32_t RTC_TimeTypeDef::DayLightSaving

Specifies RTC_DayLightSaveOperation: the value of hour adjustment. This parameter can be a value of RTC DayLight Saving Definitions

Definition at line 130 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

uint8_t RTC_TimeTypeDef::Hours

Specifies the RTC Time Hour. This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected

Definition at line 107 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_TimeTypeDef::Minutes

Specifies the RTC Time Minutes. This parameter must be a number between Min_Data = 0 and Max_Data = 59

Definition at line 111 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint32_t RTC_TimeTypeDef::SecondFraction

Specifies the range or granularity of Sub Second register content corresponding to Synchronous pre-scaler factor value (PREDIV_S) This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity. This field will be used only by HAL_RTC_GetTime function

Definition at line 124 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetTime().

uint8_t RTC_TimeTypeDef::Seconds

Specifies the RTC Time Seconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59

Definition at line 114 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint32_t RTC_TimeTypeDef::StoreOperation

Specifies RTC_StoreOperation value to be written in the BCK bit in CR register to store the operation. This parameter can be a value of RTC Store Operation Definitions

Definition at line 133 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

uint32_t RTC_TimeTypeDef::SubSeconds

Specifies the RTC_SSR RTC Sub Second register content. This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity

Definition at line 120 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_TimeTypeDef::TimeFormat

Specifies the RTC AM/PM Time. This parameter can be a value of RTC AM PM Definitions

Definition at line 117 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rtc.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC_DateTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_DateTypeDef Struct Reference
RTC Exported Types

RTC Date structure definition. More...

#include <stm32h7xx_hal_rtc.h>

Data Fields

uint8_t | WeekDay
uint8_t | Month
uint8_t | Date
uint8_t | Year

Detailed Description

RTC Date structure definition.

Definition at line 141 of file stm32h7xx_hal_rtc.h.

Field Documentation

uint8_t RTC_DateTypeDef::Date

Specifies the RTC Date. This parameter must be a number between Min_Data = 1 and Max_Data = 31

Definition at line 149 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::Month

Specifies the RTC Date Month (in BCD format). This parameter can be a value of RTC Month Date Definitions

Definition at line 146 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::WeekDay

Specifies the RTC Date WeekDay. This parameter can be a value of RTC WeekDay Definitions

Definition at line 143 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::Year

Specifies the RTC Date Year. This parameter must be a number between Min_Data = 0 and Max_Data = 99

Definition at line 152 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rtc.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC_AlarmTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_AlarmTypeDef Struct Reference
RTC Exported Types

RTC Alarm structure definition. More...

#include <stm32h7xx_hal_rtc.h>

Data Fields

RTC_TimeTypeDef AlarmTime
uint32_t | AlarmMask
uint32_t | AlarmSubSecondMask
uint32_t | AlarmDateWeekDaySel
uint8_t | AlarmDateWeekDay
uint32_t | Alarm

Detailed Description

RTC Alarm structure definition.

Definition at line 160 of file stm32h7xx_hal_rtc.h.

Field Documentation

uint32_t RTC_AlarmTypeDef::Alarm

Specifies the alarm . This parameter can be a value of RTC Alarms Definitions

Definition at line 177 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint8_t RTC_AlarmTypeDef::AlarmDateWeekDay

Specifies the RTC Alarm Date/WeekDay. If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. If the Alarm WeekDay is selected, this parameter can be a value of RTC WeekDay Definitions

Definition at line 173 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmDateWeekDaySel

Specifies the RTC Alarm is on Date or WeekDay. This parameter can be a value of RTC Alarm Date WeekDay Definitions

Definition at line 170 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmMask

Specifies the RTC Alarm Masks. This parameter can be a value of RTC Alarm Mask Definitions

Definition at line 164 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmSubSecondMask

Specifies the RTC Alarm SubSeconds Masks. This parameter can be a value of RTC Alarm Sub Seconds Masks Definitions

Definition at line 167 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

RTC_TimeTypeDef RTC_AlarmTypeDef::AlarmTime

Specifies the RTC Alarm Time members

Definition at line 162 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rtc.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_HandleTypeDef Struct Reference
RTC Exported Types

Time Handle Structure definition. More...

#include <stm32h7xx_hal_rtc.h>

Data Fields

RTC_TypeDef * | Instance
RTC_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_RTCStateTypeDef | State

Detailed Description

Time Handle Structure definition.

Definition at line 184 of file stm32h7xx_hal_rtc.h.

Field Documentation

RTC_InitTypeDef RTC_HandleTypeDef::Init

RTC required parameters

Definition at line 188 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

RTC_TypeDef* RTC_HandleTypeDef::Instance

Register base address

Definition at line 186 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeInit(), HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_BKUPRead(), HAL_RTCEx_BKUPWrite(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_GetWakeUpTimer(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), and RTC_EnterInitMode().

HAL_LockTypeDef RTC_HandleTypeDef::Lock

RTC locking object

Definition at line 190 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

__IO HAL_RTCStateTypeDef RTC_HandleTypeDef::State

Time communication state

Definition at line 192 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_GetState(), HAL_RTC_Init(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_PollForAlarmBEvent(), HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_RTCEx_TamperTimeStampIRQHandler(), and HAL_RTCEx_WakeUpTimerIRQHandler().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rtc.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Hour Formats

Defines
RTC Hour Formats
RTC Exported Constants

Defines

#define | RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
#define | RTC_HOURFORMAT_12 ((uint32_t)0x00000040)

Define Documentation

#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040)

Definition at line 209 of file stm32h7xx_hal_rtc.h.

#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000)

Definition at line 208 of file stm32h7xx_hal_rtc.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Output Polarity Definitions

Defines
RTC Output Polarity Definitions
RTC Exported Constants

Defines

#define | RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
#define | RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)

Define Documentation

#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)

Definition at line 217 of file stm32h7xx_hal_rtc.h.

#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)

Definition at line 218 of file stm32h7xx_hal_rtc.h.

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STM32H753xx HAL User Manual: RTC Output Type ALARM OUT

Defines
RTC Output Type ALARM OUT
RTC Exported Constants

Defines

#define | RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
#define | RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE)

Define Documentation

#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)

Definition at line 226 of file stm32h7xx_hal_rtc.h.

#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE)

Definition at line 227 of file stm32h7xx_hal_rtc.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Output ALARM OUT Remap

Defines
RTC Output ALARM OUT Remap
RTC Exported Constants

Defines

#define | RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000)
#define | RTC_OUTPUT_REMAP_POS1 ((uint32_t)RTC_OR_OUT_RMP)

Define Documentation

#define RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000)

Definition at line 235 of file stm32h7xx_hal_rtc.h.

#define RTC_OUTPUT_REMAP_POS1 ((uint32_t)RTC_OR_OUT_RMP)

Definition at line 236 of file stm32h7xx_hal_rtc.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC AM PM Definitions

Defines
RTC AM PM Definitions
RTC Exported Constants

Defines

#define | RTC_HOURFORMAT12_AM ((uint8_t)0x00)
#define | RTC_HOURFORMAT12_PM ((uint8_t)0x40)

Define Documentation

#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)

Definition at line 244 of file stm32h7xx_hal_rtc.h.

#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)

Definition at line 245 of file stm32h7xx_hal_rtc.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC DayLight Saving Definitions

Defines
RTC DayLight Saving Definitions
RTC Exported Constants

Defines

#define | RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)
#define | RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)
#define | RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)

Define Documentation

#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)

Definition at line 254 of file stm32h7xx_hal_rtc.h.

#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)

Definition at line 255 of file stm32h7xx_hal_rtc.h.

#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)

Definition at line 253 of file stm32h7xx_hal_rtc.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Store Operation Definitions

Defines
RTC Store Operation Definitions
RTC Exported Constants

Defines

#define | RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
#define | RTC_STOREOPERATION_SET ((uint32_t)0x00040000)

Define Documentation

#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)

Definition at line 263 of file stm32h7xx_hal_rtc.h.

#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000)

Definition at line 264 of file stm32h7xx_hal_rtc.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Input Parameter Format Definitions

Defines
RTC Input Parameter Format Definitions
RTC Exported Constants

Defines

#define | RTC_FORMAT_BIN ((uint32_t)0x000000000)
#define | RTC_FORMAT_BCD ((uint32_t)0x000000001)

Define Documentation

#define RTC_FORMAT_BCD ((uint32_t)0x000000001)

Definition at line 273 of file stm32h7xx_hal_rtc.h.

#define RTC_FORMAT_BIN ((uint32_t)0x000000000)

Definition at line 272 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Month Date Definitions

Defines
RTC Month Date Definitions
RTC Exported Constants

Defines

#define | RTC_MONTH_JANUARY ((uint8_t)0x01)
#define | RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define | RTC_MONTH_MARCH ((uint8_t)0x03)
#define | RTC_MONTH_APRIL ((uint8_t)0x04)
#define | RTC_MONTH_MAY ((uint8_t)0x05)
#define | RTC_MONTH_JUNE ((uint8_t)0x06)
#define | RTC_MONTH_JULY ((uint8_t)0x07)
#define | RTC_MONTH_AUGUST ((uint8_t)0x08)
#define | RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
#define | RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define | RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define | RTC_MONTH_DECEMBER ((uint8_t)0x12)

Define Documentation

#define RTC_MONTH_APRIL ((uint8_t)0x04)

Definition at line 286 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_AUGUST ((uint8_t)0x08)

Definition at line 290 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_DECEMBER ((uint8_t)0x12)

Definition at line 294 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)

Definition at line 284 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_JANUARY ((uint8_t)0x01)

Definition at line 283 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_JULY ((uint8_t)0x07)

Definition at line 289 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_JUNE ((uint8_t)0x06)

Definition at line 288 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_MARCH ((uint8_t)0x03)

Definition at line 285 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_MAY ((uint8_t)0x05)

Definition at line 287 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)

Definition at line 293 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_OCTOBER ((uint8_t)0x10)

Definition at line 292 of file stm32h7xx_hal_rtc.h.

#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)

Definition at line 291 of file stm32h7xx_hal_rtc.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC WeekDay Definitions

Defines
RTC WeekDay Definitions
RTC Exported Constants

Defines

#define | RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define | RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define | RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
#define | RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
#define | RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define | RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define | RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)

Define Documentation

#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)

Definition at line 306 of file stm32h7xx_hal_rtc.h.

#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)

Definition at line 302 of file stm32h7xx_hal_rtc.h.

#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)

Definition at line 307 of file stm32h7xx_hal_rtc.h.

#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)

Definition at line 308 of file stm32h7xx_hal_rtc.h.

#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)

Definition at line 305 of file stm32h7xx_hal_rtc.h.

#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)

Definition at line 303 of file stm32h7xx_hal_rtc.h.

#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)

Definition at line 304 of file stm32h7xx_hal_rtc.h.

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STM32H753xx HAL User Manual: RTC Alarm Date WeekDay Definitions

Defines
RTC Alarm Date WeekDay Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
#define | RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)

Define Documentation

#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)

Definition at line 316 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)

Definition at line 317 of file stm32h7xx_hal_rtc.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Alarm Mask Definitions

Defines
RTC Alarm Mask Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
#define | RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define | RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define | RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define | RTC_ALARMMASK_ALL ((uint32_t)0x80808080)

Define Documentation

#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080)

Definition at line 331 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm().

#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4

Definition at line 327 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3

Definition at line 328 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2

Definition at line 329 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)

Definition at line 326 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1

Definition at line 330 of file stm32h7xx_hal_rtc.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Alarms Definitions

Defines
RTC Alarms Definitions
RTC Exported Constants

Defines

#define | RTC_ALARM_A RTC_CR_ALRAE
#define | RTC_ALARM_B RTC_CR_ALRBE

Define Documentation

#define RTC_ALARM_A RTC_CR_ALRAE

Definition at line 339 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_ALARM_B RTC_CR_ALRBE

Definition at line 340 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Alarm Sub Seconds Masks Definitions

Defines
RTC Alarm Sub Seconds Masks Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000)
#define | RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000)
#define | RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000)

Define Documentation

#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000)

All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm

Definition at line 348 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000)

SS[14:0] are compared and must match to activate alarm.

Definition at line 379 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000)

SS[14] is don't care in Alarm comparison.Only SS[13:0] are compared

Definition at line 377 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000)

SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared.

Definition at line 351 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000)

SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared

Definition at line 369 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000)

SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared

Definition at line 371 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000)

SS[14:12] are don't care in Alarm comparison.Only SS[11:0] are compared

Definition at line 373 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000)

SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared

Definition at line 375 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000)

SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared

Definition at line 353 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000)

SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared

Definition at line 355 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000)

SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared

Definition at line 357 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000)

SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared

Definition at line 359 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000)

SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared

Definition at line 361 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000)

SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared

Definition at line 363 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000)

SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared

Definition at line 365 of file stm32h7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000)

SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared

Definition at line 367 of file stm32h7xx_hal_rtc.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Interrupts Definitions

Defines
RTC Interrupts Definitions
RTC Exported Constants

Defines

#define | RTC_IT_TS ((uint32_t)RTC_CR_TSIE)
#define | RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE)
#define | RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE)
#define | RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE)
#define | RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE)
#define | RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE)
#define | RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE)
#define | RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE)

Define Documentation

#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE)

Enable Alarm A Interrupt

Definition at line 390 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE)

Enable Alarm B Interrupt

Definition at line 391 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE)

Enable all Tamper Interrupt

Definition at line 392 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTamper(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE)

Enable Tamper 1 Interrupt

Definition at line 393 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTamper(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE)

Enable Tamper 2 Interrupt

Definition at line 394 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTamper(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE)

Enable Tamper 3 Interrupt

Definition at line 395 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTamper(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_IT_TS ((uint32_t)RTC_CR_TSIE)

Enable Timestamp Interrupt

Definition at line 388 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE)

Enable Wakeup timer Interrupt

Definition at line 389 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Flags Definitions

Defines
RTC Flags Definitions
RTC Exported Constants

Defines

#define | RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF)
#define | RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F)
#define | RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F)
#define | RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F)
#define | RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF)
#define | RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF)
#define | RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF)
#define | RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF)
#define | RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF)
#define | RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF)
#define | RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF)
#define | RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF)
#define | RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS)
#define | RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF)
#define | RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF)
#define | RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF)
#define | RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF)

Define Documentation

#define RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF)

Definition at line 412 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_PollForAlarmAEvent(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF)

Definition at line 419 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF)

Definition at line 411 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF)

Definition at line 418 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF)

Definition at line 413 of file stm32h7xx_hal_rtc.h.

#define RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS)

Definition at line 415 of file stm32h7xx_hal_rtc.h.

#define RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF)

Definition at line 409 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTCEx_GetTimeStamp().

#define RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF)

Definition at line 403 of file stm32h7xx_hal_rtc.h.

#define RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF)

Definition at line 414 of file stm32h7xx_hal_rtc.h.

#define RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF)

Definition at line 416 of file stm32h7xx_hal_rtc.h.

#define RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F)

Definition at line 406 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTamper1Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F)

Definition at line 405 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTamper2Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F)

Definition at line 404 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTamper3Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF)

Definition at line 408 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_PollForTimeStampEvent(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF)

Definition at line 407 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTimeStampEvent().

#define RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF)

Definition at line 410 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetWakeUpTimer_IT(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF)

Definition at line 417 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Exported Macros

Defines
RTC Exported Macros
RTC

Defines

#define | __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
Reset RTC handle state.
#define | __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)
Disable the write protection for RTC registers.
#define | __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)
Enable the write protection for RTC registers.
#define | __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
Enable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
Disable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
Enable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
Disable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
Check whether the specified RTC Alarm interrupt has occurred or not.
#define | __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC Alarm's flag status.
#define | __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Alarm's pending flags.
#define | __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Alarm interrupt is enabled or not.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI_D1->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI_D1->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI_D1->PR1 & RTC_EXTI_LINE_ALARM_EVENT)
Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI_D1->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))
Clear the RTC Alarm associated Exti line flag.
#define | __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)
Generate a Software interrupt on RTC Alarm associated Exti line.

Define Documentation

#define __HAL_RTC_ALARM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Alarm's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Alarm Flag sources to clear. This parameter can be:
  • RTC_FLAG_ALRAF
  • RTC_FLAG_ALRBF
Return values:
None

Definition at line 544 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define __HAL_RTC_ALARM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC Alarm interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Alarm interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 509 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), and HAL_RTC_SetAlarm().

#define __HAL_RTC_ALARM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC Alarm interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Alarm interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 498 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG ( ) (EXTI_D1->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))

Clear the RTC Alarm associated Exti line flag.

Return values:
None.

Definition at line 631 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler().

#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT ( ) (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable event on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 579 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 591 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_IT ( ) (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable interrupt on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 567 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable rising edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 603 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                             __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();  \
                                                             __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
                                                           } while(0)

Disable rising & falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 617 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT ( ) (EXTI_D1->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable event on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 573 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 585 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_IT ( ) (EXTI_D1->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable interrupt on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 561 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable rising edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 597 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                             __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();  \
                                                             __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
                                                           } while(0)

Enable rising & falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 609 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)

Generate a Software interrupt on RTC Alarm associated Exti line.

Return values:
None

Definition at line 637 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_GET_FLAG ( ) (EXTI_D1->PR1 & RTC_EXTI_LINE_ALARM_EVENT)

Check whether the RTC Alarm associated Exti line interrupt flag is set or not.

Return values:
Line Status.

Definition at line 625 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)

Get the selected RTC Alarm's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Alarm Flag sources to check. This parameter can be:
  • RTC_FLAG_ALRAF
  • RTC_FLAG_ALRBF
  • RTC_FLAG_ALRAWF
  • RTC_FLAG_ALRBWF
Return values:
None

Definition at line 533 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define __HAL_RTC_ALARM_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)

Check whether the specified RTC Alarm interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Alarm interrupt sources to check. This parameter can be:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 520 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the specified RTC Alarm interrupt is enabled or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Alarm interrupt sources to check. This parameter can be:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 555 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler().

#define __HAL_RTC_ALARMA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))

Disable the RTC ALARMA peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 473 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))

Enable the RTC ALARMA peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 466 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMB_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))

Disable the RTC ALARMB peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 487 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMB_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))

Enable the RTC ALARMB peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 480 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)

Reset RTC handle state.

Parameters:
__HANDLE__,: RTC handle.
Return values:
None

Definition at line 437 of file stm32h7xx_hal_rtc.h.

#define __HAL_RTC_WRITEPROTECTION_DISABLE ( __HANDLE__ )
Value:
do{                                       \
                            (__HANDLE__)->Instance->WPR = 0xCA;   \
                            (__HANDLE__)->Instance->WPR = 0x53;   \
                          } while(0)

Disable the write protection for RTC registers.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 444 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WRITEPROTECTION_ENABLE ( __HANDLE__ )
Value:
do{                                       \
                            (__HANDLE__)->Instance->WPR = 0xFF;   \
                          } while(0)

Enable the write protection for RTC registers.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 455 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Private Constants

Defines
RTC Private Constants
RTC

Defines

#define | RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
#define | RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
#define | RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)
#define | RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU)
#define | RTC_TIMEOUT_VALUE 1000
#define | RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000)

Define Documentation

#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)

Definition at line 721 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000)

External interrupt line 17 Connected to the RTC Alarm event

Definition at line 727 of file stm32h7xx_hal_rtc.h.

#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)

Definition at line 722 of file stm32h7xx_hal_rtc.h.

Referenced by RTC_EnterInitMode().

#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU)

Definition at line 723 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_WaitForSynchro().

#define RTC_TIMEOUT_VALUE 1000

Definition at line 725 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), and RTC_EnterInitMode().

#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)

Definition at line 720 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetTime(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Private macros to check input parameters

Defines
RTC Private macros to check input parameters
RTC Private Macros

Defines

#define | IS_RTC_HOUR_FORMAT(FORMAT)
#define | IS_RTC_OUTPUT_POL(POL)
#define | IS_RTC_OUTPUT_TYPE(TYPE)
#define | IS_RTC_OUTPUT_REMAP(REMAP)
#define | IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
#define | IS_RTC_DAYLIGHT_SAVING(SAVE)
#define | IS_RTC_STORE_OPERATION(OPERATION)
#define | IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
#define | IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
#define | IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
#define | IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
#define | IS_RTC_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
#define | IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL)
#define | IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
#define | IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
#define | IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
#define | IS_RTC_ALARM_SUB_SECOND_MASK(MASK)
#define | IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
#define | IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF)
#define | IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
#define | IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
#define | IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
#define | IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)

Define Documentation

#define IS_RTC_ALARM ( ALARM ) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))

Definition at line 794 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_DATE ( DATE ) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))

Definition at line 779 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_SEL ( SEL )
Value:
(((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
                                            ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))

Definition at line 789 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY ( WEEKDAY )
Value:
(((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))

Definition at line 781 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_MASK ( MASK ) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)

Definition at line 792 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_SUB_SECOND_MASK ( MASK )
Value:
(((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))

Definition at line 798 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_SUB_SECOND_VALUE ( VALUE ) ((VALUE) <= (uint32_t)0x00007FFF)

Definition at line 796 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ASYNCH_PREDIV ( PREDIV ) ((PREDIV) <= (uint32_t)0x7F)

Definition at line 815 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_DATE ( DATE ) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))

Definition at line 769 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_DAYLIGHT_SAVING ( SAVE )
Value:
(((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
                                      ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
                                      ((SAVE) == RTC_DAYLIGHTSAVING_NONE))

Definition at line 756 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

#define IS_RTC_FORMAT ( FORMAT ) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))

Definition at line 763 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

#define IS_RTC_HOUR12 ( HOUR ) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))

Definition at line 819 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_HOUR24 ( HOUR ) ((HOUR) <= (uint32_t)23)

Definition at line 821 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_HOUR_FORMAT ( FORMAT )
Value:
(((FORMAT) == RTC_HOURFORMAT_12) || \
                                        ((FORMAT) == RTC_HOURFORMAT_24))

Definition at line 742 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_HOURFORMAT12 ( PM ) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))

Definition at line 754 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_MINUTES ( MINUTES ) ((MINUTES) <= (uint32_t)59)

Definition at line 823 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_MONTH ( MONTH ) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))

Definition at line 767 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_OUTPUT_POL ( POL )
Value:
(((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
                                ((POL) == RTC_OUTPUT_POLARITY_LOW))

Definition at line 745 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_REMAP ( REMAP )
Value:
(((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
                                        ((REMAP) == RTC_OUTPUT_REMAP_POS1))

Definition at line 751 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_TYPE ( TYPE )
Value:
(((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
                                  ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))

Definition at line 748 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_SECONDS ( SECONDS ) ((SECONDS) <= (uint32_t)59)

Definition at line 825 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_STORE_OPERATION ( OPERATION )
Value:
(((OPERATION) == RTC_STOREOPERATION_RESET) || \
                                           ((OPERATION) == RTC_STOREOPERATION_SET))

Definition at line 760 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

#define IS_RTC_SYNCH_PREDIV ( PREDIV ) ((PREDIV) <= (uint32_t)0x7FFF)

Definition at line 817 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_WEEKDAY ( WEEKDAY )
Value:
(((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                 ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
                                 ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
                                 ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
                                 ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
                                 ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
                                 ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))

Definition at line 771 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_YEAR ( YEAR ) ((YEAR) <= (uint32_t)99)

Definition at line 765 of file stm32h7xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC TimeStamp and Tamper functions

Functions
RTC TimeStamp and Tamper functions
RTCEx Exported Functions

RTC TimeStamp and Tamper functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Set Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Get the RTC TimeStamp value.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivate Tamper.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
Handle TimeStamp interrupt request.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper2 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper3Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper3 Polling.

Detailed Description

RTC TimeStamp and Tamper functions.

 ===============================================================================
                 ##### RTC TimeStamp and Tamper functions #####
 ===============================================================================

 [..] This section provide functions allowing to configure TimeStamp feature

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp ( RTC_HandleTypeDef * hrtc )

Deactivate Internal TimeStamp.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 358 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Tamper
 | ) |  |

Deactivate Tamper.

Parameters:
hrtc,: RTC handle
Tamper,: Selected tamper pin. This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3.
Return values:
HAL status

Definition at line 630 of file stm32h7xx_hal_rtc_ex.c.

References assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, RTC_IT_TAMP, RTC_IT_TAMP1, RTC_IT_TAMP2, RTC_IT_TAMP3, RTC_TAMPER_1, RTC_TAMPER_2, RTC_TAMPER_3, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp ( RTC_HandleTypeDef * hrtc )

Deactivate TimeStamp.

Parameters:
hrtc,: RTC handle
Return values:
HAL status

Definition at line 287 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_DISABLE_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_IT_TS, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTimeStamp,
 |  | RTC_DateTypeDef * | sTimeStampDate,
 |  | uint32_t | Format
 | ) |  |

Get the RTC TimeStamp value.

Parameters:
hrtc,: RTC handle
sTimeStamp,: Pointer to Time structure
sTimeStampDate,: Pointer to Date structure
Format,: specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 394 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_CLEAR_FLAG, assert_param, RTC_DateTypeDef::Date, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_DR_RESERVED_MASK, RTC_FLAG_ITSF, RTC_FLAG_TSF, RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, RTC_TimeTypeDef::TimeFormat, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Tamper1 Polling.

Parameters:
hrtc,: RTC handle
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 839 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP1F, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Tamper2 Polling.

Parameters:
hrtc,: RTC handle
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 871 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP2F, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Tamper3 Polling.

Parameters:
hrtc,: RTC handle
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 903 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP3F, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle TimeStamp polling request.

Parameters:
hrtc,: RTC handle
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 800 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TSF, RTC_FLAG_TSOVF, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp ( RTC_HandleTypeDef * hrtc )

Set Internal TimeStamp.

Note:
This API must be called before enabling the internal TimeStamp feature.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 326 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Set Tamper.

Note:
By calling this API we disable the tamper interrupt for all tampers.
Parameters:
hrtc,: RTC handle
sTamper,: Pointer to Tamper Structure.
Return values:
HAL status

Definition at line 446 of file stm32h7xx_hal_rtc_ex.c.

References assert_param, RTC_TamperTypeDef::Filter, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, IS_RTC_TAMPER_ERASE_MODE, IS_RTC_TAMPER_FILTER, IS_RTC_TAMPER_MASKFLAG_STATE, IS_RTC_TAMPER_PRECHARGE_DURATION, IS_RTC_TAMPER_PULLUP_STATE, IS_RTC_TAMPER_SAMPLING_FREQ, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, IS_RTC_TAMPER_TRIGGER, RTC_TamperTypeDef::MaskFlag, RTC_TamperTypeDef::NoErase, RTC_TamperTypeDef::PrechargeDuration, RTC_TAMPER_1, RTC_TAMPER_2, RTC_TAMPER_3, RTC_TAMPER_ERASE_BACKUP_ENABLE, RTC_TAMPERMASK_FLAG_DISABLE, RTC_TAMPERTRIGGER_RISINGEDGE, RTC_TamperTypeDef::SamplingFrequency, RTC_HandleTypeDef::State, RTC_TamperTypeDef::Tamper, RTC_TamperTypeDef::TamperPullUp, RTC_TamperTypeDef::TimeStampOnTamperDetection, and RTC_TamperTypeDef::Trigger.

HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Set Tamper with interrupt.

Note:
By calling this API we force the tamper interrupt for all tampers.
Parameters:
hrtc,: RTC handle
sTamper,: Pointer to RTC Tamper.
Return values:
HAL status

Definition at line 534 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT, __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE, assert_param, RTC_TamperTypeDef::Filter, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_TamperTypeDef::Interrupt, IS_RTC_TAMPER, IS_RTC_TAMPER_ERASE_MODE, IS_RTC_TAMPER_FILTER, IS_RTC_TAMPER_INTERRUPT, IS_RTC_TAMPER_MASKFLAG_STATE, IS_RTC_TAMPER_PRECHARGE_DURATION, IS_RTC_TAMPER_PULLUP_STATE, IS_RTC_TAMPER_SAMPLING_FREQ, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, IS_RTC_TAMPER_TRIGGER, RTC_TamperTypeDef::MaskFlag, RTC_TamperTypeDef::NoErase, RTC_TamperTypeDef::PrechargeDuration, RTC_TAMPER_1, RTC_TAMPER_2, RTC_TAMPER_3, RTC_TAMPER_ERASE_BACKUP_ENABLE, RTC_TAMPERMASK_FLAG_DISABLE, RTC_TAMPERTRIGGER_RISINGEDGE, RTC_TamperTypeDef::SamplingFrequency, RTC_HandleTypeDef::State, RTC_TamperTypeDef::Tamper, RTC_TamperTypeDef::TamperPullUp, RTC_TamperTypeDef::TimeStampOnTamperDetection, and RTC_TamperTypeDef::Trigger.

HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | TimeStampEdge,
 |  | uint32_t | RTC_TimeStampPin
 | ) |  |

Set TimeStamp.

Note:
This API must be called before enabling the TimeStamp feature.
Parameters:
hrtc,: RTC handle
TimeStampEdge,: Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following values:
  • RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the falling edge of the related pin.
RTC_TimeStampPin,: specifies the RTC TimeStamp Pin. This parameter can be one of the following values:
  • RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. The RTC TimeStamp Pin is per default PC13, but for reasons of compatibility, this parameter is required.
Return values:
HAL status

Definition at line 179 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TIMESTAMP_PIN, IS_TIMESTAMP_EDGE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | TimeStampEdge,
 |  | uint32_t | RTC_TimeStampPin
 | ) |  |

Set TimeStamp with Interrupt.

Parameters:
hrtc,: RTC handle
Note:
This API must be called before enabling the TimeStamp feature.
Parameters:
TimeStampEdge,: Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following values:
  • RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the falling edge of the related pin.
RTC_TimeStampPin,: Specifies the RTC TimeStamp Pin. This parameter can be one of the following values:
  • RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. The RTC TimeStamp Pin is per default PC13, but for reasons of compatibility, this parameter is required.
Return values:
HAL status

Definition at line 235 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT, __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE, __HAL_RTC_TIMESTAMP_ENABLE, __HAL_RTC_TIMESTAMP_ENABLE_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TIMESTAMP_PIN, IS_TIMESTAMP_EDGE, RTC_IT_TS, and RTC_HandleTypeDef::State.

void HAL_RTCEx_Tamper1EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 1 callback.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 757 of file stm32h7xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_Tamper2EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 2 callback.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 771 of file stm32h7xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_Tamper3EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 3 callback.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 785 of file stm32h7xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_TamperTimeStampIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle TimeStamp interrupt request.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 671 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, __HAL_RTC_TAMPER_GET_IT_SOURCE, __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_GET_FLAG, __HAL_RTC_TIMESTAMP_GET_IT_SOURCE, HAL_RTC_STATE_READY, HAL_RTCEx_Tamper1EventCallback(), HAL_RTCEx_Tamper2EventCallback(), HAL_RTCEx_Tamper3EventCallback(), HAL_RTCEx_TimeStampEventCallback(), RTC_FLAG_TAMP1F, RTC_FLAG_TAMP2F, RTC_FLAG_TAMP3F, RTC_FLAG_TSF, RTC_IT_TAMP, RTC_IT_TAMP1, RTC_IT_TAMP2, RTC_IT_TAMP3, RTC_IT_TS, and RTC_HandleTypeDef::State.

void HAL_RTCEx_TimeStampEventCallback ( RTC_HandleTypeDef * hrtc )

TimeStamp callback.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 743 of file stm32h7xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Wake-up functions

Functions
RTC Wake-up functions
RTCEx Exported Functions

RTC Wake-up functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer with interrupt.
uint32_t | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivate wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Get wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Wake Up Timer Polling.

Detailed Description

RTC Wake-up functions.

 ===============================================================================
                        ##### RTC Wake-up functions #####
 ===============================================================================

 [..] This section provide functions allowing to configure Wake-up feature

Function Documentation

uint32_t HAL_RTCEx_DeactivateWakeUpTimer ( RTC_HandleTypeDef * hrtc )

Deactivate wake up timer counter.

Parameters:
hrtc,: RTC handle
Return values:
HAL status

Definition at line 1142 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_DISABLE_IT, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_WUTWF, RTC_IT_WUT, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

uint32_t HAL_RTCEx_GetWakeUpTimer ( RTC_HandleTypeDef * hrtc )

Get wake up timer counter.

Parameters:
hrtc,: RTC handle
Return values:
Counter value

Definition at line 1194 of file stm32h7xx_hal_rtc_ex.c.

References RTC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Wake Up Timer Polling.

Parameters:
hrtc,: RTC handle
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1244 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_WUTF, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | WakeUpCounter,
 |  | uint32_t | WakeUpClock
 | ) |  |

Set wake up timer.

Parameters:
hrtc,: RTC handle
WakeUpCounter,: Wake up counter
WakeUpClock,: Wake up clock
Return values:
HAL status

Definition at line 954 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_ENABLE, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_HandleTypeDef::Instance, IS_RTC_WAKEUP_CLOCK, IS_RTC_WAKEUP_COUNTER, RTC_FLAG_WUTWF, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | WakeUpCounter,
 |  | uint32_t | WakeUpClock
 | ) |  |

Set wake up timer with interrupt.

Parameters:
hrtc,: RTC handle
WakeUpCounter,: Wake up counter
WakeUpClock,: Wake up clock
Return values:
HAL status

Definition at line 1043 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_ENABLE, __HAL_RTC_WAKEUPTIMER_ENABLE_IT, __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT, __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_HandleTypeDef::Instance, IS_RTC_WAKEUP_CLOCK, IS_RTC_WAKEUP_COUNTER, RTC_FLAG_WUTF, RTC_FLAG_WUTWF, RTC_IT_WUT, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

void HAL_RTCEx_WakeUpTimerEventCallback ( RTC_HandleTypeDef * hrtc )

Wake Up Timer callback.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 1228 of file stm32h7xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_WakeUpTimerIRQHandler().

void HAL_RTCEx_WakeUpTimerIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle Wake Up Timer interrupt request.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 1205 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_GET_FLAG, HAL_RTC_STATE_READY, HAL_RTCEx_WakeUpTimerEventCallback(), RTC_FLAG_WUTF, and RTC_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
RTCEx Exported Functions

Extended Peripheral Control functions. More...

Functions

void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Write a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Read data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
Set the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configure the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disable the Bypass Shadow feature.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
              ##### Extended Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Write a data in a specified RTC Backup data register
      (+) Read a data in a specified RTC Backup data register
      (+) Set the Coarse calibration parameters.
      (+) Deactivate the Coarse calibration parameters
      (+) Set the Smooth calibration parameters.
      (+) Configure the Synchronization Shift Control Settings.
      (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
      (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
      (+) Enable the RTC reference clock detection.
      (+) Disable the RTC reference clock detection.
      (+) Enable the Bypass Shadow feature.
      (+) Disable the Bypass Shadow feature.

Function Documentation

uint32_t HAL_RTCEx_BKUPRead | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister
 | ) |  |

Read data from the specified RTC Backup data Register.

Parameters:
hrtc,: RTC handle
BackupRegister,: RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
Return values:
Read value

Definition at line 1332 of file stm32h7xx_hal_rtc_ex.c.

References assert_param, RTC_HandleTypeDef::Instance, and IS_RTC_BKP.

void HAL_RTCEx_BKUPWrite | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister,
 |  | uint32_t | Data
 | ) |  |

Write a data in a specified RTC Backup data register.

Parameters:
hrtc,: RTC handle
BackupRegister,: RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
Data,: Data to be written in the specified RTC Backup data register.
Return values:
None

Definition at line 1310 of file stm32h7xx_hal_rtc_ex.c.

References assert_param, RTC_HandleTypeDef::Instance, and IS_RTC_BKP.

HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut ( RTC_HandleTypeDef * hrtc )

Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
hrtc,: RTC handle
Return values:
HAL status

Definition at line 1564 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_CALIBRATION_OUTPUT_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock ( RTC_HandleTypeDef * hrtc )

Disable the RTC reference clock detection.

Parameters:
hrtc,: RTC handle
Return values:
HAL status

Definition at line 1642 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_CLOCKREF_DETECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow ( RTC_HandleTypeDef * hrtc )

Disable the Bypass Shadow feature.

Parameters:
hrtc,: RTC handle
Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Return values:
HAL status

Definition at line 1725 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow ( RTC_HandleTypeDef * hrtc )

Enable the Bypass Shadow feature.

Parameters:
hrtc,: RTC handle
Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Return values:
HAL status

Definition at line 1693 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | CalibOutput
 | ) |  |

Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
hrtc,: RTC handle
CalibOutput : Select the Calibration output Selection . This parameter can be one of the following values:
  • RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
  • RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
Return values:
HAL status

Definition at line 1526 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_CALIBRATION_OUTPUT_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_CALIB_OUTPUT, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetRefClock ( RTC_HandleTypeDef * hrtc )

Enable the RTC reference clock detection.

Parameters:
hrtc,: RTC handle
Return values:
HAL status

Definition at line 1593 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_CLOCKREF_DETECTION_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | SmoothCalibPeriod,
 |  | uint32_t | SmoothCalibPlusPulses,
 |  | uint32_t | SmoothCalibMinusPulsesValue
 | ) |  |

Set the Smooth calibration parameters.

Parameters:
hrtc,: RTC handle
SmoothCalibPeriod,: Select the Smooth Calibration Period. This parameter can be can be one of the following values :
  • RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
  • RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
  • RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
SmoothCalibPlusPulses,: Select to Set or reset the CALP bit. This parameter can be one of the following values:
  • RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
SmoothCalibMinusPulsesValue,: Select the value of CALM[8:0] bits. This parameter can be one any value from 0 to 0x000001FF.
Note:
To deactivate the smooth calibration, the field SmoothCalibPlusPulses must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field SmoothCalibMinusPulsesValue must be equal to 0.
Return values:
HAL status

Definition at line 1365 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_HandleTypeDef::Instance, IS_RTC_SMOOTH_CALIB_MINUS, IS_RTC_SMOOTH_CALIB_PERIOD, IS_RTC_SMOOTH_CALIB_PLUS, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | ShiftAdd1S,
 |  | uint32_t | ShiftSubFS
 | ) |  |

Configure the Synchronization Shift Control Settings.

Note:
When REFCKON is set, firmware must not write to Shift control register.
Parameters:
hrtc,: RTC handle
ShiftAdd1S,: Select to add or not 1 second to the time calendar. This parameter can be one of the following values :
  • RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
  • RTC_SHIFTADD1S_RESET: No effect.
ShiftSubFS,: Select the number of Second Fractions to substitute. This parameter can be one any value from 0 to 0x7FFF.
Return values:
HAL status

Definition at line 1433 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, HAL_RTC_WaitForSynchro(), RTC_HandleTypeDef::Instance, IS_RTC_SHIFT_ADD1S, IS_RTC_SHIFT_SUBFS, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Extended features functions

Functions
Extended features functions
RTCEx Exported Functions

Extended features functions. More...

Functions

__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Alarm B Polling request.

Detailed Description

Extended features functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) RTC Alarm B callback
      (+) RTC Poll for Alarm B request

Function Documentation

void HAL_RTCEx_AlarmBEventCallback ( RTC_HandleTypeDef * hrtc )

Alarm B callback.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 1774 of file stm32h7xx_hal_rtc_ex.c.

Referenced by HAL_RTC_AlarmIRQHandler().

HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Alarm B Polling request.

Parameters:
hrtc,: RTC handle
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1790 of file stm32h7xx_hal_rtc_ex.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_ALRBF, and RTC_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC_TamperTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_TamperTypeDef Struct Reference
RTCEx Exported Types

RTC Tamper structure definition. More...

#include <stm32h7xx_hal_rtc_ex.h>

Data Fields

uint32_t | Tamper
uint32_t | Interrupt
uint32_t | Trigger
uint32_t | NoErase
uint32_t | MaskFlag
uint32_t | Filter
uint32_t | SamplingFrequency
uint32_t | PrechargeDuration
uint32_t | TamperPullUp
uint32_t | TimeStampOnTamperDetection

Detailed Description

RTC Tamper structure definition.

Definition at line 64 of file stm32h7xx_hal_rtc_ex.h.

Field Documentation

uint32_t RTC_TamperTypeDef::Filter

Specifies the RTC Filter Tamper. This parameter can be a value of RTC Tamper Filter Definitions

Definition at line 81 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Interrupt

Specifies the Tamper Interrupt. This parameter can be a value of RTC Tamper Interrupts Definitions

Definition at line 69 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::MaskFlag

Specifies the Tamper Flag masking. This parameter can be a value of RTC Tamper Mask Flag Definitions

Definition at line 78 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::NoErase

Specifies the Tamper no erase mode. This parameter can be a value of RTC Tamper EraseBackUp Definitions

Definition at line 75 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::PrechargeDuration

Specifies the Precharge Duration . This parameter can be a value of RTC Tamper Pin Precharge Duration Definitions

Definition at line 87 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::SamplingFrequency

Specifies the sampling frequency. This parameter can be a value of RTC Tamper Sampling Frequencies Definitions

Definition at line 84 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Tamper

Specifies the Tamper Pin. This parameter can be a value of RTC Tamper Pins Definitions

Definition at line 66 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::TamperPullUp

Specifies the Tamper PullUp . This parameter can be a value of RTC Tamper Pull Up Definitions

Definition at line 90 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::TimeStampOnTamperDetection

Specifies the TimeStampOnTamperDetection. This parameter can be a value of RTC Tamper TimeStamp On Tamper Detection Definitions

Definition at line 93 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Trigger

Specifies the Tamper Trigger. This parameter can be a value of RTC Tamper Triggers Definitions

Definition at line 72 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rtc_ex.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Output Selection Definitions

Defines
RTC Output Selection Definitions
RTCEx Exported Constants

Defines

#define | RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)
#define | RTC_OUTPUT_ALARMA ((uint32_t)0x00200000)
#define | RTC_OUTPUT_ALARMB ((uint32_t)0x00400000)
#define | RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000)

Define Documentation

#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000)

Definition at line 110 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000)

Definition at line 111 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)

Definition at line 109 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000)

Definition at line 112 of file stm32h7xx_hal_rtc_ex.h.

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STM32H753xx HAL User Manual: RTC Backup Registers Definitions

Defines
RTC Backup Registers Definitions
RTCEx Exported Constants

Defines

#define | RTC_BKP_DR0 ((uint32_t)0x00000000)
#define | RTC_BKP_DR1 ((uint32_t)0x00000001)
#define | RTC_BKP_DR2 ((uint32_t)0x00000002)
#define | RTC_BKP_DR3 ((uint32_t)0x00000003)
#define | RTC_BKP_DR4 ((uint32_t)0x00000004)
#define | RTC_BKP_DR5 ((uint32_t)0x00000005)
#define | RTC_BKP_DR6 ((uint32_t)0x00000006)
#define | RTC_BKP_DR7 ((uint32_t)0x00000007)
#define | RTC_BKP_DR8 ((uint32_t)0x00000008)
#define | RTC_BKP_DR9 ((uint32_t)0x00000009)
#define | RTC_BKP_DR10 ((uint32_t)0x0000000A)
#define | RTC_BKP_DR11 ((uint32_t)0x0000000B)
#define | RTC_BKP_DR12 ((uint32_t)0x0000000C)
#define | RTC_BKP_DR13 ((uint32_t)0x0000000D)
#define | RTC_BKP_DR14 ((uint32_t)0x0000000E)
#define | RTC_BKP_DR15 ((uint32_t)0x0000000F)
#define | RTC_BKP_DR16 ((uint32_t)0x00000010)
#define | RTC_BKP_DR17 ((uint32_t)0x00000011)
#define | RTC_BKP_DR18 ((uint32_t)0x00000012)
#define | RTC_BKP_DR19 ((uint32_t)0x00000013)
#define | RTC_BKP_DR20 ((uint32_t)0x00000014)
#define | RTC_BKP_DR21 ((uint32_t)0x00000015)
#define | RTC_BKP_DR22 ((uint32_t)0x00000016)
#define | RTC_BKP_DR23 ((uint32_t)0x00000017)
#define | RTC_BKP_DR24 ((uint32_t)0x00000018)
#define | RTC_BKP_DR25 ((uint32_t)0x00000019)
#define | RTC_BKP_DR26 ((uint32_t)0x0000001A)
#define | RTC_BKP_DR27 ((uint32_t)0x0000001B)
#define | RTC_BKP_DR28 ((uint32_t)0x0000001C)
#define | RTC_BKP_DR29 ((uint32_t)0x0000001D)
#define | RTC_BKP_DR30 ((uint32_t)0x0000001E)
#define | RTC_BKP_DR31 ((uint32_t)0x0000001F)

Define Documentation

#define RTC_BKP_DR0 ((uint32_t)0x00000000)

Definition at line 121 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR1 ((uint32_t)0x00000001)

Definition at line 122 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR10 ((uint32_t)0x0000000A)

Definition at line 131 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR11 ((uint32_t)0x0000000B)

Definition at line 132 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR12 ((uint32_t)0x0000000C)

Definition at line 133 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR13 ((uint32_t)0x0000000D)

Definition at line 134 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR14 ((uint32_t)0x0000000E)

Definition at line 135 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR15 ((uint32_t)0x0000000F)

Definition at line 136 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR16 ((uint32_t)0x00000010)

Definition at line 137 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR17 ((uint32_t)0x00000011)

Definition at line 138 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR18 ((uint32_t)0x00000012)

Definition at line 139 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR19 ((uint32_t)0x00000013)

Definition at line 140 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR2 ((uint32_t)0x00000002)

Definition at line 123 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR20 ((uint32_t)0x00000014)

Definition at line 141 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR21 ((uint32_t)0x00000015)

Definition at line 142 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR22 ((uint32_t)0x00000016)

Definition at line 143 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR23 ((uint32_t)0x00000017)

Definition at line 144 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR24 ((uint32_t)0x00000018)

Definition at line 145 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR25 ((uint32_t)0x00000019)

Definition at line 146 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR26 ((uint32_t)0x0000001A)

Definition at line 147 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR27 ((uint32_t)0x0000001B)

Definition at line 148 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR28 ((uint32_t)0x0000001C)

Definition at line 149 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR29 ((uint32_t)0x0000001D)

Definition at line 150 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR3 ((uint32_t)0x00000003)

Definition at line 124 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR30 ((uint32_t)0x0000001E)

Definition at line 151 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR31 ((uint32_t)0x0000001F)

Definition at line 152 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR4 ((uint32_t)0x00000004)

Definition at line 125 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR5 ((uint32_t)0x00000005)

Definition at line 126 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR6 ((uint32_t)0x00000006)

Definition at line 127 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR7 ((uint32_t)0x00000007)

Definition at line 128 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR8 ((uint32_t)0x00000008)

Definition at line 129 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_BKP_DR9 ((uint32_t)0x00000009)

Definition at line 130 of file stm32h7xx_hal_rtc_ex.h.

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STM32H753xx HAL User Manual: RTC TimeStamp Edges Definitions

Defines
RTC TimeStamp Edges Definitions
RTCEx Exported Constants

Defines

#define | RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)
#define | RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008)

Define Documentation

#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008)

Definition at line 162 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)

Definition at line 161 of file stm32h7xx_hal_rtc_ex.h.

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STM32H753xx HAL User Manual: RTC TimeStamp Pins Selection

Defines
RTC TimeStamp Pins Selection
RTCEx Exported Constants

Defines

#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)

Define Documentation

#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)

Definition at line 171 of file stm32h7xx_hal_rtc_ex.h.

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STM32H753xx HAL User Manual: RTC Tamper Pins Definitions

Defines
RTC Tamper Pins Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_1 RTC_TAMPCR_TAMP1E
#define | RTC_TAMPER_2 RTC_TAMPCR_TAMP2E
#define | RTC_TAMPER_3 RTC_TAMPCR_TAMP3E

Define Documentation

#define RTC_TAMPER_1 RTC_TAMPCR_TAMP1E

Definition at line 179 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define RTC_TAMPER_2 RTC_TAMPCR_TAMP2E

Definition at line 180 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define RTC_TAMPER_3 RTC_TAMPCR_TAMP3E

Definition at line 181 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

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STM32H753xx HAL User Manual: RTC Tamper Interrupts Definitions

Defines
RTC Tamper Interrupts Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE
#define | RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE
#define | RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE
#define | RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE

Define Documentation

#define RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE

Definition at line 192 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE

Definition at line 189 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE

Definition at line 190 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE

Definition at line 191 of file stm32h7xx_hal_rtc_ex.h.

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STM32H753xx HAL User Manual: RTC Tamper Triggers Definitions

Defines
RTC Tamper Triggers Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)
#define | RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002)
#define | RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define | RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE

Define Documentation

#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002)

Definition at line 201 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE

Definition at line 203 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE

Definition at line 202 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)

Definition at line 200 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Tamper EraseBackUp Definitions

Defines
RTC Tamper EraseBackUp Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000)
#define | RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000)

Define Documentation

#define RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000)

Definition at line 213 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000)

Definition at line 212 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Tamper Mask Flag Definitions

Defines
RTC Tamper Mask Flag Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000)
#define | RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000)

Define Documentation

#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000)

Definition at line 221 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000)

Definition at line 222 of file stm32h7xx_hal_rtc_ex.h.

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STM32H753xx HAL User Manual: RTC Tamper Filter Definitions

Defines
RTC Tamper Filter Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000)
#define | RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800)
#define | RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000)
#define | RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800)

Define Documentation

#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800)

Tamper is activated after 2 consecutive samples at the active level

Definition at line 232 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000)

Tamper is activated after 4 consecutive samples at the active level

Definition at line 234 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800)

Tamper is activated after 8 consecutive samples at the active level.

Definition at line 236 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000)

Tamper filter is disabled

Definition at line 230 of file stm32h7xx_hal_rtc_ex.h.

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STM32H753xx HAL User Manual: RTC Tamper Sampling Frequencies Definitions

Defines
RTC Tamper Sampling Frequencies Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700)

Define Documentation

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024

Definition at line 255 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384

Definition at line 247 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048

Definition at line 253 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 256

Definition at line 259 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768

Definition at line 245 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096

Definition at line 251 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 512

Definition at line 257 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192

Definition at line 249 of file stm32h7xx_hal_rtc_ex.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Tamper Pin Precharge Duration Definitions

Defines
RTC Tamper Pin Precharge Duration Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000)
#define | RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000)
#define | RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000)
#define | RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000)

Define Documentation

#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000)

Tamper pins are pre-charged before sampling during 1 RTCCLK cycle

Definition at line 268 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000)

Tamper pins are pre-charged before sampling during 2 RTCCLK cycles

Definition at line 270 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000)

Tamper pins are pre-charged before sampling during 4 RTCCLK cycles

Definition at line 272 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000)

Tamper pins are pre-charged before sampling during 8 RTCCLK cycles

Definition at line 274 of file stm32h7xx_hal_rtc_ex.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Tamper TimeStamp On Tamper Detection Definitions

Defines
RTC Tamper TimeStamp On Tamper Detection Definitions
RTCEx Exported Constants

Defines

#define | RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAMPCR_TAMPTS)
#define | RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000)

TimeStamp on Tamper Detection event is not saved

Definition at line 284 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAMPCR_TAMPTS)

TimeStamp on Tamper Detection event saved

Definition at line 283 of file stm32h7xx_hal_rtc_ex.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Tamper Pull Up Definitions

Defines
RTC Tamper Pull Up Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000)
#define | RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS)

Define Documentation

#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS)

TimeStamp on Tamper Detection event is not saved

Definition at line 293 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000)

TimeStamp on Tamper Detection event saved

Definition at line 292 of file stm32h7xx_hal_rtc_ex.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Wakeup Timer Definitions

Defines
RTC Wakeup Timer Definitions
RTCEx Exported Constants

Defines

#define | RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003)
#define | RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004)
#define | RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006)

Define Documentation

#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004)

Definition at line 305 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006)

Definition at line 306 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)

Definition at line 301 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003)

Definition at line 304 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002)

Definition at line 303 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001)

Definition at line 302 of file stm32h7xx_hal_rtc_ex.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Smooth Calib Period Definitions

Defines
RTC Smooth Calib Period Definitions
RTCEx Exported Constants

Defines

#define | RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000)
#define | RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000)
#define | RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000)

Define Documentation

#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000)

If RTCCLK = 32768 Hz, Smooth calibration period is 16s, else 2exp19 RTCCLK seconds

Definition at line 316 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000)

If RTCCLK = 32768 Hz, Smooth calibration period is 32s, else 2exp20 RTCCLK seconds

Definition at line 314 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000)

If RTCCLK = 32768 Hz, Smooth calibration period is 8s, else 2exp18 RTCCLK seconds

Definition at line 318 of file stm32h7xx_hal_rtc_ex.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Smooth Calib Plus Pulses Definitions

Defines
RTC Smooth Calib Plus Pulses Definitions
RTCEx Exported Constants

Defines

#define | RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000)
#define | RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000)

Define Documentation

#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000)

The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0]

Definition at line 330 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000)

The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0] with Y = 512, 256, 128 when X = 32, 16, 8

Definition at line 327 of file stm32h7xx_hal_rtc_ex.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Calib Output Selection Definitions

Defines
RTC Calib Output Selection Definitions
RTCEx Exported Constants

Defines

#define | RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)
#define | RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000)

Define Documentation

#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000)

Definition at line 340 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)

Definition at line 339 of file stm32h7xx_hal_rtc_ex.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Add 1 Second Parameter Definitions

Defines
RTC Add 1 Second Parameter Definitions
RTCEx Exported Constants

Defines

#define | RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)
#define | RTC_SHIFTADD1S_SET ((uint32_t)0x80000000)

Define Documentation

#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)

Definition at line 348 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000)

Definition at line 349 of file stm32h7xx_hal_rtc_ex.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTCEx Exported Macros

Defines
RTCEx Exported Macros
RTCEx

Defines

#define | __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
Enable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
Disable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Wake Up timer interrupt is enabled or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC WakeUpTimer's flag status.
#define | __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Wake Up timer's pending flags.
#define | __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))
Enable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
Disable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))
Enable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
Disable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))
Enable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
Disable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
Enable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
Disable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified RTC Tamper interrupt has occurred or not.
#define | __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Tamper interrupt is enabled or not.
#define | __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC Tamper's flag status.
#define | __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Tamper's pending flags.
#define | __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
Enable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
Disable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
Check whether the specified RTC TimeStamp interrupt has occurred or not.
#define | __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Time Stamp interrupt is enabled or not.
#define | __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC TimeStamp's flag status.
#define | __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Time Stamp's pending flags.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
Enable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
Disable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC Internal Time Stamp's flag status.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Internal Time Stamp's pending flags.
#define | __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
Enable the RTC calibration output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
Disable the calibration output.
#define | __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
Enable the clock reference detection.
#define | __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
Disable the clock reference detection.
#define | __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC shift operation's flag status.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI_D1->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI_D1->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTID3_ENABLE_EVENT() (EXTI->D3PMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated D3 Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTID3_DISABLE_EVENT() (EXTI->D3PMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated D3 Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI_D1->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI_D1->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the RTC WakeUp Timer associated Exti line flag.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI_D1->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI_D1->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTID3_GET_FLAG() (EXTI_D3->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the RTC WakeUp Timer associated D3 Exti line interrupt flag is set or not.
#define | __HAL_RTC_WAKEUPTIMER_EXTID3_CLEAR_FLAG() (EXTI_D3->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the RTC WakeUp Timer associated D3 Exti line flag.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI_D1->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI_D1->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Clear the RTC Tamper and Timestamp associated Exti line flag.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line.

Define Documentation

#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))

Disable the calibration output.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 679 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateCalibrationOutPut().

#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))

Enable the RTC calibration output.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 672 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetCalibrationOutPut().

#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))

Disable the clock reference detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 693 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateRefClock().

#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))

Enable the clock reference detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 686 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetRefClock().

#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Internal Time Stamp's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Internal Time Stamp Flag source to clear. This parameter can be:
  • RTC_FLAG_ITSF
Return values:
None

Definition at line 665 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_GetTimeStamp().

#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))

Disable the RTC internal TimeStamp peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 645 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateInternalTimeStamp().

#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))

Enable the RTC internal TimeStamp peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 638 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetInternalTimeStamp().

#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)

Get the selected RTC Internal Time Stamp's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Internal Time Stamp Flag is pending or not. This parameter can be:
  • RTC_FLAG_ITSF
Return values:
None

Definition at line 655 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_SHIFT_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)

Get the selected RTC shift operation's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC shift operation Flag is pending or not. This parameter can be:
  • RTC_FLAG_SHPF
Return values:
None

Definition at line 703 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER1_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))

Disable the RTC Tamper1 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 450 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER1_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))

Enable the RTC Tamper1 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 443 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER2_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))

Disable the RTC Tamper2 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 464 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER2_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))

Enable the RTC Tamper2 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 457 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER3_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))

Disable the RTC Tamper3 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 478 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER3_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))

Enable the RTC Tamper3 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 471 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Tamper's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Tamper Flag sources to clear. This parameter can be:
  • RTC_FLAG_TAMP1F: Tamper1 flag
  • RTC_FLAG_TAMP2F: Tamper2 flag
  • RTC_FLAG_TAMP3F: Tamper3 flag
Return values:
None

Definition at line 555 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TAMPER_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))

Disable the RTC Tamper interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Tamper interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RTC_IT_TAMP: All tampers interrupts
  • RTC_IT_TAMP1: Tamper1 interrupt
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt
Return values:
None

Definition at line 504 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))

Enable the RTC Tamper interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Tamper interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RTC_IT_TAMP: All tampers interrupts
  • RTC_IT_TAMP1: Tamper1 interrupt
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt
Return values:
None

Definition at line 491 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)

Get the selected RTC Tamper's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Tamper Flag is pending or not. This parameter can be:
  • RTC_FLAG_TAMP1F: Tamper1 flag
  • RTC_FLAG_TAMP2F: Tamper2 flag
  • RTC_FLAG_TAMP3F: Tamper3 flag
Return values:
None

Definition at line 543 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TAMPER_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \
                                                                      ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \
                                                                      (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))

Check whether the specified RTC Tamper interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Tamper interrupt to check. This parameter can be:
  • RTC_IT_TAMP1: Tamper1 interrupt
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt
Return values:
None

Definition at line 516 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the specified RTC Tamper interrupt is enabled or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Tamper interrupt source to check. This parameter can be:
  • RTC_IT_TAMP: All tampers interrupts
  • RTC_IT_TAMP1: Tamper1 interrupt
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt
Return values:
None

Definition at line 531 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG ( ) (EXTI_D1->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Clear the RTC Tamper and Timestamp associated Exti line flag.

Return values:
None

Definition at line 886 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT ( ) (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable event on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 815 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 846 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT ( ) (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable interrupt on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 803 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 858 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();  \
                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \
                                                                       } while(0)

Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 872 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT ( ) (EXTI_D1->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable event on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 809 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 840 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT ( ) (EXTI_D1->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable interrupt on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 797 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper_IT(), and HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 852 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper_IT(), and HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();  \
                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
                                                                      } while(0)

Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 864 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 892 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG ( ) (EXTI_D1->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.

Return values:
Line Status

Definition at line 880 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Time Stamp's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Alarm Flag sources to clear. This parameter can be:
  • RTC_FLAG_TSF
  • RTC_FLAG_TSOVF
Return values:
None

Definition at line 631 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_PollForTimeStampEvent(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TIMESTAMP_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))

Disable the RTC TimeStamp peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 569 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC TimeStamp interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC TimeStamp interrupt source to be disabled. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 589 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTimeStamp().

#define __HAL_RTC_TIMESTAMP_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))

Enable the RTC TimeStamp peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 562 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TIMESTAMP_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC TimeStamp interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC TimeStamp interrupt source to be enabled. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 579 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TIMESTAMP_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)

Get the selected RTC TimeStamp's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC TimeStamp Flag is pending or not. This parameter can be:
  • RTC_FLAG_TSF
  • RTC_FLAG_TSOVF
Return values:
None

Definition at line 620 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTimeStampEvent(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TIMESTAMP_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)

Check whether the specified RTC TimeStamp interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC TimeStamp interrupt source to check. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 599 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the specified RTC Time Stamp interrupt is enabled or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Time Stamp interrupt source to check. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 609 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Wake Up timer's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC WakeUpTimer Flag to clear. This parameter can be:
  • RTC_FLAG_WUTF
Return values:
None

Definition at line 436 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetWakeUpTimer_IT(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))

Disable the RTC WakeUp Timer peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 375 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC WakeUpTimer interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC WakeUpTimer interrupt sources to be disabled. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer interrupt
Return values:
None

Definition at line 395 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer().

#define __HAL_RTC_WAKEUPTIMER_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))

Enable the RTC WakeUp Timer peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 368 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC WakeUpTimer interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC WakeUpTimer interrupt sources to be enabled. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer interrupt
Return values:
None

Definition at line 385 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG ( ) (EXTI_D1->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Clear the RTC WakeUp Timer associated Exti line flag.

Return values:
None

Definition at line 791 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT ( ) (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable event on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 727 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 750 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT ( ) (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 715 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 762 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();  \
                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \
                                                                  } while(0)

Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.

This parameter can be:

Return values:
None

Definition at line 777 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT ( ) (EXTI_D1->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable event on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 721 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 744 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT ( ) (EXTI_D1->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 709 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 756 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();  \
                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \
                                                                 } while(0)

Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 768 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 833 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG ( ) (EXTI_D1->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.

Return values:
Line Status.

Definition at line 785 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTID3_CLEAR_FLAG ( ) (EXTI_D3->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Clear the RTC WakeUp Timer associated D3 Exti line flag.

Return values:
None.

Definition at line 827 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTID3_DISABLE_EVENT ( ) (EXTI->D3PMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable event on the RTC WakeUp Timer associated D3 Exti line.

Return values:
None

Definition at line 738 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTID3_ENABLE_EVENT ( ) (EXTI->D3PMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable event on the RTC WakeUp Timer associated D3 Exti line.

Return values:
None

Definition at line 732 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTID3_GET_FLAG ( ) (EXTI_D3->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Check whether the RTC WakeUp Timer associated D3 Exti line interrupt flag is set or not.

Return values:
Line Status

Definition at line 821 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)

Get the selected RTC WakeUpTimer's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC WakeUpTimer Flag is pending or not. This parameter can be:
  • RTC_FLAG_WUTF
  • RTC_FLAG_WUTWF
Return values:
None

Definition at line 426 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)

Check whether the specified RTC WakeUpTimer interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC WakeUpTimer interrupt sources to check. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer interrupt
Return values:
None

Definition at line 405 of file stm32h7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the specified RTC Wake Up timer interrupt is enabled or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Wake Up timer interrupt sources to check. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer interrupt
Return values:
None

Definition at line 415 of file stm32h7xx_hal_rtc_ex.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTCEx Private Constants

Defines
RTCEx Private Constants
RTCEx

Defines

#define | RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00040000)
#define | RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00080000)
#define | RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))
#define | RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))

Define Documentation

#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00040000)

External interrupt line 18 Connected to the RTC Tamper and Time Stamp events

Definition at line 986 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00080000)

External interrupt line 19 Connected to the RTC Wakeup event

Definition at line 987 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))

Definition at line 990 of file stm32h7xx_hal_rtc_ex.h.

#define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))

Definition at line 991 of file stm32h7xx_hal_rtc_ex.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Private macros to check input parameters

Defines
Private macros to check input parameters
RTCEx Private Macros

Defines

#define | IS_RTC_OUTPUT(OUTPUT)
#define | IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
#define | IS_TIMESTAMP_EDGE(EDGE)
#define | IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXE))) == 0x00U) && ((__TAMPER__) != (uint32_t)RESET))
#define | IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & (uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXIE)) == 0x00U) && ((__INTERRUPT__) != (uint32_t)RESET))
#define | IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
#define | IS_RTC_TAMPER_TRIGGER(TRIGGER)
#define | IS_RTC_TAMPER_ERASE_MODE(MODE)
#define | IS_RTC_TAMPER_MASKFLAG_STATE(STATE)
#define | IS_RTC_TAMPER_FILTER(FILTER)
#define | IS_RTC_TAMPER_SAMPLING_FREQ(FREQ)
#define | IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION)
#define | IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION)
#define | IS_RTC_TAMPER_PULLUP_STATE(STATE)
#define | IS_RTC_WAKEUP_CLOCK(CLOCK)
#define | IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
#define | IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD)
#define | IS_RTC_SMOOTH_CALIB_PLUS(PLUS)
#define | IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
#define | IS_RTC_SHIFT_ADD1S(SEL)
#define | IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
#define | IS_RTC_CALIB_OUTPUT(OUTPUT)

Define Documentation

#define IS_RTC_BKP ( BKP ) ((BKP) < (uint32_t) RTC_BKP_NUMBER)

Definition at line 1011 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_BKUPRead(), and HAL_RTCEx_BKUPWrite().

#define IS_RTC_CALIB_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
                                      ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))

Definition at line 1081 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetCalibrationOutPut().

#define IS_RTC_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == RTC_OUTPUT_DISABLE)     || \
                               ((OUTPUT) == RTC_OUTPUT_ALARMA)      || \
                               ((OUTPUT) == RTC_OUTPUT_ALARMB)      || \
                               ((OUTPUT) == RTC_OUTPUT_WAKEUP))

Definition at line 1006 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_SHIFT_ADD1S ( SEL )
Value:
(((SEL) == RTC_SHIFTADD1S_RESET) || \
                                 ((SEL) == RTC_SHIFTADD1S_SET))

Definition at line 1076 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSynchroShift().

#define IS_RTC_SHIFT_SUBFS ( FS ) ((FS) <= 0x00007FFF)

Definition at line 1079 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSynchroShift().

#define IS_RTC_SMOOTH_CALIB_MINUS ( VALUE ) ((VALUE) <= 0x000001FF)

Definition at line 1074 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_SMOOTH_CALIB_PERIOD ( PERIOD )
Value:
(((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))

Definition at line 1067 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_SMOOTH_CALIB_PLUS ( PLUS )
Value:
(((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
                                        ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))

Definition at line 1071 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_TAMPER ( __TAMPER__ ) ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXE))) == 0x00U) && ((__TAMPER__) != (uint32_t)RESET))

Definition at line 1016 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_ERASE_MODE ( MODE )
Value:
(((MODE) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
                                                    ((MODE) == RTC_TAMPER_ERASE_BACKUP_DISABLE))

Definition at line 1027 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_FILTER ( FILTER )
Value:
(((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
                                       ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
                                       ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
                                       ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))

Definition at line 1033 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_INTERRUPT ( __INTERRUPT__ ) ((((__INTERRUPT__) & (uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXIE)) == 0x00U) && ((__INTERRUPT__) != (uint32_t)RESET))

Definition at line 1018 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_MASKFLAG_STATE ( STATE )
Value:
(((STATE) == RTC_TAMPERMASK_FLAG_ENABLE) || \
                                                    ((STATE) == RTC_TAMPERMASK_FLAG_DISABLE))

Definition at line 1030 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_PRECHARGE_DURATION ( DURATION )
Value:
(((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
                                                   ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))

Definition at line 1047 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_PULLUP_STATE ( STATE )
Value:
(((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
                                           ((STATE) == RTC_TAMPER_PULLUP_DISABLE))

Definition at line 1055 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_SAMPLING_FREQ ( FREQ )
Value:
(((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
                                          ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))

Definition at line 1038 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION ( DETECTION )
Value:
(((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
                                                              ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))

Definition at line 1052 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE)    || \
                                        ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE)   || \
                                        ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL)      || \
                                        ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))

Definition at line 1022 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TIMESTAMP_PIN ( PIN ) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))

Definition at line 1020 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

#define IS_RTC_WAKEUP_CLOCK ( CLOCK )
Value:
(((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)       || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))

Definition at line 1058 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define IS_RTC_WAKEUP_COUNTER ( COUNTER ) ((COUNTER) <= 0xFFFF)

Definition at line 1065 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define IS_TIMESTAMP_EDGE ( EDGE )
Value:
(((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
                                 ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))

Definition at line 1013 of file stm32h7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Private Typedefs

Enumerations
SAI Private Typedefs
SAI

Enumerations

enum SAI_ModeTypedef { SAI_MODE_DMA, SAI_MODE_IT }

Enumeration Type Documentation

enum SAI_ModeTypedef
Enumerator:
SAI_MODE_DMA
SAI_MODE_IT

Definition at line 194 of file stm32h7xx_hal_sai.c.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Private Constants

Defines
SAI Private Constants
SAI

Defines

#define | SAI_FIFO_SIZE 8U
#define | SAI_DEFAULT_TIMEOUT 4U /* 4ms */
#define | SAI_LONG_TIMEOUT 1000U
#define | SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT)
#define | SAI_PDMCR_MICNBR_OFFSET POSITION_VAL(SAI_PDMCR_MICNBR)

Define Documentation

#define SAI_DEFAULT_TIMEOUT 4U /* 4ms */

Definition at line 208 of file stm32h7xx_hal_sai.c.

Referenced by SAI_Disable().

#define SAI_FIFO_SIZE 8U

Definition at line 207 of file stm32h7xx_hal_sai.c.

#define SAI_LONG_TIMEOUT 1000U

Definition at line 209 of file stm32h7xx_hal_sai.c.

Referenced by HAL_SAI_Transmit_DMA().

#define SAI_PDMCR_MICNBR_OFFSET POSITION_VAL(SAI_PDMCR_MICNBR)

Definition at line 211 of file stm32h7xx_hal_sai.c.

Referenced by HAL_SAI_Init().

#define SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT)

Definition at line 210 of file stm32h7xx_hal_sai.c.

Referenced by HAL_SAI_EnableRxMuteMode().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Private Functions

Functions
SAI Private Functions
SAI

Private functions. More...

Functions

static void | SAI_FillFifo (SAI_HandleTypeDef *hsai)
Fill the fifo.
static uint32_t | SAI_InterruptFlag (SAI_HandleTypeDef *hsai, uint32_t mode)
Return the interrupt flag to set according the SAI setup.
static HAL_StatusTypeDef | SAI_InitI2S (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the SAI I2S protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_InitPCM (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the SAI PCM protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_Disable (SAI_HandleTypeDef *hsai)
Disable the SAI and wait for the disabling.
static void | SAI_Transmit_IT8Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
static void | SAI_Transmit_IT16Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
static void | SAI_Transmit_IT32Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
static void | SAI_Receive_IT8Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode 8-Bit transfer.
static void | SAI_Receive_IT16Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
static void | SAI_Receive_IT32Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
static void | SAI_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process complete callback.
static void | SAI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process half complete callback.
static void | SAI_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process complete callback.
static void | SAI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process half complete callback.
static void | SAI_DMAError (DMA_HandleTypeDef *hdma)
DMA SAI communication error callback.
static void | SAI_DMAAbort (DMA_HandleTypeDef *hdma)
DMA SAI Abort callback.

Detailed Description

Private functions.

Function Documentation

static HAL_StatusTypeDef SAI_Disable ( SAI_HandleTypeDef * hsai ) [static]

Disable the SAI and wait for the disabling.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2002 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_DISABLE, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_TIMEOUT, __SAI_HandleTypeDef::Instance, and SAI_DEFAULT_TIMEOUT.

Referenced by HAL_SAI_Abort(), HAL_SAI_DeInit(), HAL_SAI_DMAStop(), HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Transmit(), SAI_DMAAbort(), and SAI_DMAError().

static void SAI_DMAAbort ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI Abort callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2294 of file stm32h7xx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_WCKCFG, HAL_SAI_ErrorCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, SAI_Disable(), __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_IRQHandler().

static void SAI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI communication error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2258 of file stm32h7xx_hal_sai.c.

References __DMA_HandleTypeDef::ErrorCode, __SAI_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_FE, HAL_DMA_ERROR_TE, HAL_DMA_GetError(), HAL_SAI_ERROR_DMA, HAL_SAI_ErrorCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, SAI_Disable(), __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_DMA(), and HAL_SAI_Transmit_DMA().

static void SAI_DMARxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2222 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, DMA_CIRCULAR, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __DMA_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, SAI_InterruptFlag(), SAI_MODE_DMA, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_DMA().

static void SAI_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI receive process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2246 of file stm32h7xx_hal_sai.c.

References HAL_SAI_RxHalfCpltCallback().

Referenced by HAL_SAI_Receive_DMA().

static void SAI_DMATxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI transmit process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2184 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, DMA_CIRCULAR, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __DMA_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, SAI_InterruptFlag(), SAI_MODE_DMA, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_DMA().

static void SAI_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI transmit process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2209 of file stm32h7xx_hal_sai.c.

References HAL_SAI_TxHalfCpltCallback().

Referenced by HAL_SAI_Transmit_DMA().

static void SAI_FillFifo ( SAI_HandleTypeDef * hsai ) [static]

Fill the fifo.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1939 of file stm32h7xx_hal_sai.c.

References SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_FIFOSTATUS_FULL, SAI_NOCOMPANDING, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit(), and HAL_SAI_Transmit_IT().

static HAL_StatusTypeDef SAI_InitI2S | ( | SAI_HandleTypeDef * | hsai,
 |  | uint32_t | protocol,
 |  | uint32_t | datasize,
 |  | uint32_t | nbslot
 | ) |  | [static]

Initialize the SAI I2S protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
protocol,: one of the supported protocol.
datasize,: one of the supported datasize SAI protocol data size the configuration information for SAI module.
nbslot,: number of slot minimum value is 2 and max is 16. the value must be a multiple of 2.
Return values:
HAL status

Definition at line 1779 of file stm32h7xx_hal_sai.c.

References SAI_FrameInitTypeDef::ActiveFrameLength, SAI_InitTypeDef::AudioMode, SAI_InitTypeDef::ClockStrobing, SAI_InitTypeDef::DataSize, SAI_InitTypeDef::FirstBit, SAI_SlotInitTypeDef::FirstBitOffset, __SAI_HandleTypeDef::FrameInit, SAI_FrameInitTypeDef::FrameLength, SAI_FrameInitTypeDef::FSDefinition, SAI_FrameInitTypeDef::FSOffset, SAI_FrameInitTypeDef::FSPolarity, __SAI_HandleTypeDef::Init, SAI_InitTypeDef::Protocol, SAI_CLOCKSTROBING_FALLINGEDGE, SAI_CLOCKSTROBING_RISINGEDGE, SAI_DATASIZE_16, SAI_DATASIZE_24, SAI_DATASIZE_32, SAI_FIRSTBIT_MSB, SAI_FREE_PROTOCOL, SAI_FS_ACTIVE_HIGH, SAI_FS_ACTIVE_LOW, SAI_FS_BEFOREFIRSTBIT, SAI_FS_CHANNEL_IDENTIFICATION, SAI_FS_FIRSTBIT, SAI_I2S_LSBJUSTIFIED, SAI_I2S_MSBJUSTIFIED, SAI_I2S_STANDARD, SAI_MODEMASTER_TX, SAI_MODESLAVE_TX, SAI_PROTOCOL_DATASIZE_16BIT, SAI_PROTOCOL_DATASIZE_16BITEXTENDED, SAI_PROTOCOL_DATASIZE_24BIT, SAI_PROTOCOL_DATASIZE_32BIT, SAI_SLOTACTIVE_ALL, SAI_SLOTSIZE_16B, SAI_SLOTSIZE_32B, SAI_SlotInitTypeDef::SlotActive, __SAI_HandleTypeDef::SlotInit, SAI_SlotInitTypeDef::SlotNumber, and SAI_SlotInitTypeDef::SlotSize.

Referenced by HAL_SAI_InitProtocol().

static HAL_StatusTypeDef SAI_InitPCM | ( | SAI_HandleTypeDef * | hsai,
 |  | uint32_t | protocol,
 |  | uint32_t | datasize,
 |  | uint32_t | nbslot
 | ) |  | [static]

Initialize the SAI PCM protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
protocol,: one of the supported protocol
datasize,: one of the supported datasize SAI protocol data size
nbslot,: number of slot minimum value is 1 and the max is 16.
Return values:
HAL status

Definition at line 1872 of file stm32h7xx_hal_sai.c.

References SAI_FrameInitTypeDef::ActiveFrameLength, SAI_InitTypeDef::AudioMode, SAI_InitTypeDef::ClockStrobing, SAI_InitTypeDef::DataSize, SAI_InitTypeDef::FirstBit, SAI_SlotInitTypeDef::FirstBitOffset, __SAI_HandleTypeDef::FrameInit, SAI_FrameInitTypeDef::FrameLength, SAI_FrameInitTypeDef::FSDefinition, SAI_FrameInitTypeDef::FSOffset, SAI_FrameInitTypeDef::FSPolarity, __SAI_HandleTypeDef::Init, SAI_InitTypeDef::Protocol, SAI_CLOCKSTROBING_FALLINGEDGE, SAI_CLOCKSTROBING_RISINGEDGE, SAI_DATASIZE_16, SAI_DATASIZE_24, SAI_DATASIZE_32, SAI_FIRSTBIT_MSB, SAI_FREE_PROTOCOL, SAI_FS_ACTIVE_HIGH, SAI_FS_BEFOREFIRSTBIT, SAI_FS_STARTFRAME, SAI_MODEMASTER_TX, SAI_MODESLAVE_TX, SAI_PCM_LONG, SAI_PCM_SHORT, SAI_PROTOCOL_DATASIZE_16BIT, SAI_PROTOCOL_DATASIZE_16BITEXTENDED, SAI_PROTOCOL_DATASIZE_24BIT, SAI_PROTOCOL_DATASIZE_32BIT, SAI_SLOTACTIVE_ALL, SAI_SLOTSIZE_16B, SAI_SLOTSIZE_32B, SAI_SlotInitTypeDef::SlotActive, __SAI_HandleTypeDef::SlotInit, SAI_SlotInitTypeDef::SlotNumber, and SAI_SlotInitTypeDef::SlotSize.

Referenced by HAL_SAI_InitProtocol().

static uint32_t SAI_InterruptFlag | ( | SAI_HandleTypeDef * | hsai,
 |  | uint32_t | mode
 | ) |  | [static]

Return the interrupt flag to set according the SAI setup.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
mode,: SAI_MODE_DMA or SAI_MODE_IT
Return values:
the list of the IT flag to enable

Definition at line 1969 of file stm32h7xx_hal_sai.c.

References SAI_InitTypeDef::AudioMode, __SAI_HandleTypeDef::Init, SAI_InitTypeDef::Protocol, SAI_AC97_PROTOCOL, SAI_IT_AFSDET, SAI_IT_CNRDY, SAI_IT_FREQ, SAI_IT_LFSDET, SAI_IT_OVRUDR, SAI_IT_WCKCFG, SAI_MODE_IT, SAI_MODEMASTER_RX, SAI_MODESLAVE_RX, and SAI_MODESLAVE_TX.

Referenced by HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

static void SAI_Receive_IT16Bit ( SAI_HandleTypeDef * hsai ) [static]

Rx Handler for Receive in Interrupt mode for 16-Bit transfer.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2131 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __HAL_SAI_DISABLE_IT, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_FLAG_OVRUDR, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_IT().

static void SAI_Receive_IT32Bit ( SAI_HandleTypeDef * hsai ) [static]

Rx Handler for Receive in Interrupt mode for 32-Bit transfer.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2157 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __HAL_SAI_DISABLE_IT, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_FLAG_OVRUDR, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_IT().

static void SAI_Receive_IT8Bit ( SAI_HandleTypeDef * hsai ) [static]

Rx Handler for Receive in Interrupt mode 8-Bit transfer.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2105 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __HAL_SAI_DISABLE_IT, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_FLAG_OVRUDR, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_IT().

static void SAI_Transmit_IT16Bit ( SAI_HandleTypeDef * hsai ) [static]

Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2055 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_IT().

static void SAI_Transmit_IT32Bit ( SAI_HandleTypeDef * hsai ) [static]

Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2080 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_IT().

static void SAI_Transmit_IT8Bit ( SAI_HandleTypeDef * hsai ) [static]

Tx Handler for Transmit in Interrupt mode 8-Bit transfer.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2031 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_IT().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SAI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SAI_InitProtocol (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.
HAL_StatusTypeDef | HAL_SAI_Init (SAI_HandleTypeDef *hsai)
Initialize the SAI according to the specified parameters.
HAL_StatusTypeDef | HAL_SAI_DeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI peripheral.
__weak void | HAL_SAI_MspInit (SAI_HandleTypeDef *hsai)
Initialize the SAI MSP.
__weak void | HAL_SAI_MspDeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
             ##### Initialization and de-initialization functions #####
 ===============================================================================
  [..]  This subsection provides a set of functions allowing to initialize and
        de-initialize the SAIx peripheral:

      (+) User must implement HAL_SAI_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_SAI_Init() to configure the selected device with
          the selected configuration:
        (++) Mode (Master/slave TX/RX)
        (++) Protocol
        (++) Data Size
        (++) MCLK Output
        (++) Audio frequency
        (++) FIFO Threshold
        (++) Frame Config
        (++) Slot Config
    (++) PDM Config

      (+) Call the function HAL_SAI_DeInit() to restore the default configuration
          of the selected SAI peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SAI_DeInit ( SAI_HandleTypeDef * hsai )

DeInitialize the SAI peripheral.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 615 of file stm32h7xx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_NONE, HAL_SAI_MspDeInit(), HAL_SAI_STATE_BUSY, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, SAI_Disable(), and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_Init ( SAI_HandleTypeDef * hsai )

Initialize the SAI according to the specified parameters.

in the SAI_InitTypeDef structure and initialize the associated handle.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 335 of file stm32h7xx_hal_sai.c.

References SAI_PdmInitTypeDef::Activation, SAI_FrameInitTypeDef::ActiveFrameLength, assert_param, SAI_InitTypeDef::AudioFrequency, SAI_InitTypeDef::AudioMode, SAI_PdmInitTypeDef::ClockEnable, SAI_InitTypeDef::ClockStrobing, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, SAI_InitTypeDef::FIFOThreshold, SAI_InitTypeDef::FirstBit, SAI_SlotInitTypeDef::FirstBitOffset, __SAI_HandleTypeDef::FrameInit, SAI_FrameInitTypeDef::FrameLength, SAI_FrameInitTypeDef::FSDefinition, SAI_FrameInitTypeDef::FSOffset, SAI_FrameInitTypeDef::FSPolarity, HAL_RCCEx_GetPeriphCLKFreq(), HAL_SAI_ERROR_NONE, HAL_SAI_MspInit(), HAL_SAI_STATE_BUSY, HAL_SAI_STATE_READY, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, IS_SAI_AUDIO_FREQUENCY, IS_SAI_BLOCK_ACTIVE_FRAME, IS_SAI_BLOCK_CLOCK_STROBING, IS_SAI_BLOCK_COMPANDING_MODE, IS_SAI_BLOCK_DATASIZE, IS_SAI_BLOCK_FIFO_THRESHOLD, IS_SAI_BLOCK_FIRST_BIT, IS_SAI_BLOCK_FIRSTBIT_OFFSET, IS_SAI_BLOCK_FRAME_LENGTH, IS_SAI_BLOCK_FS_DEFINITION, IS_SAI_BLOCK_FS_OFFSET, IS_SAI_BLOCK_FS_POLARITY, IS_SAI_BLOCK_MCK_OVERSAMPLING, IS_SAI_BLOCK_MODE, IS_SAI_BLOCK_NODIVIDER, IS_SAI_BLOCK_OUTPUT_DRIVE, IS_SAI_BLOCK_PROTOCOL, IS_SAI_BLOCK_SLOT_NUMBER, IS_SAI_BLOCK_SLOT_SIZE, IS_SAI_BLOCK_SYNCEXT, IS_SAI_BLOCK_SYNCHRO, IS_SAI_BLOCK_TRISTATE_MANAGEMENT, IS_SAI_MONO_STEREO_MODE, IS_SAI_PDM_CLOCK_ENABLE, IS_SAI_PDM_MIC_PAIRS_NUMBER, IS_SAI_SLOT_ACTIVE, __SAI_HandleTypeDef::Lock, SAI_InitTypeDef::Mckdiv, SAI_InitTypeDef::MckOverSampling, SAI_PdmInitTypeDef::MicPairsNbr, SAI_InitTypeDef::MonoStereoMode, SAI_InitTypeDef::NoDivider, SAI_InitTypeDef::OutputDrive, SAI_InitTypeDef::PdmInit, SAI_InitTypeDef::Protocol, RCC_PERIPHCLK_SAI1, RCC_PERIPHCLK_SAI2, RCC_PERIPHCLK_SAI3, RCC_PERIPHCLK_SAI4A, RCC_PERIPHCLK_SAI4B, SAI_ASYNCHRONOUS, SAI_AUDIO_FREQUENCY_MCKDIV, SAI_CLOCKSTROBING_RISINGEDGE, SAI_Disable(), SAI_FREE_PROTOCOL, SAI_MASTERDIVIDER_DISABLE, SAI_MCK_OVERSAMPLING_ENABLE, SAI_MODEMASTER_RX, SAI_MODEMASTER_TX, SAI_MODESLAVE_TX, SAI_PDMCR_MICNBR_OFFSET, SAI_SYNCEXT_DISABLE, SAI_SYNCEXT_OUTBLOCKA_ENABLE, SAI_SYNCEXT_OUTBLOCKB_ENABLE, SAI_SYNCHRONOUS, SAI_SYNCHRONOUS_EXT_SAI1, SAI_SYNCHRONOUS_EXT_SAI2, SAI_SlotInitTypeDef::SlotActive, __SAI_HandleTypeDef::SlotInit, SAI_SlotInitTypeDef::SlotNumber, SAI_SlotInitTypeDef::SlotSize, __SAI_HandleTypeDef::State, SAI_InitTypeDef::Synchro, SAI_InitTypeDef::SynchroExt, and SAI_InitTypeDef::TriState.

Referenced by HAL_SAI_InitProtocol().

HAL_StatusTypeDef HAL_SAI_InitProtocol | ( | SAI_HandleTypeDef * | hsai,
 |  | uint32_t | protocol,
 |  | uint32_t | datasize,
 |  | uint32_t | nbslot
 | ) |  |

Initialize the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
protocol,: one of the supported protocol SAI Supported protocol
datasize,: one of the supported datasize SAI protocol data size the configuration information for SAI module.
nbslot,: Number of slot.
Return values:
HAL status

Definition at line 296 of file stm32h7xx_hal_sai.c.

References assert_param, HAL_SAI_Init(), IS_SAI_PROTOCOL_DATASIZE, IS_SAI_SUPPORTED_PROTOCOL, SAI_I2S_LSBJUSTIFIED, SAI_I2S_MSBJUSTIFIED, SAI_I2S_STANDARD, SAI_InitI2S(), SAI_InitPCM(), SAI_PCM_LONG, and SAI_PCM_SHORT.

void HAL_SAI_MspDeInit ( SAI_HandleTypeDef * hsai )

DeInitialize the SAI MSP.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 687 of file stm32h7xx_hal_sai.c.

Referenced by HAL_SAI_DeInit().

void HAL_SAI_MspInit ( SAI_HandleTypeDef * hsai )

Initialize the SAI MSP.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 671 of file stm32h7xx_hal_sai.c.

Referenced by HAL_SAI_Init().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
SAI Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_SAI_Transmit (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Receive (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Transmit_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Receive_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_DMAPause (SAI_HandleTypeDef *hsai)
Pause the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAResume (SAI_HandleTypeDef *hsai)
Resume the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAStop (SAI_HandleTypeDef *hsai)
Stop the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_Abort (SAI_HandleTypeDef *hsai)
Abort the current transfer and disable the SAI.
HAL_StatusTypeDef | HAL_SAI_Transmit_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_Receive_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_EnableTxMuteMode (SAI_HandleTypeDef *hsai, uint16_t val)
Enable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_DisableTxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_EnableRxMuteMode (SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
Enable the Rx mute detection.
HAL_StatusTypeDef | HAL_SAI_DisableRxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Rx mute detection.
void | HAL_SAI_IRQHandler (SAI_HandleTypeDef *hsai)
Handle SAI interrupt request.
__weak void | HAL_SAI_TxCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer completed callback.
__weak void | HAL_SAI_TxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer Half completed callback.
__weak void | HAL_SAI_RxCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer completed callback.
__weak void | HAL_SAI_RxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer half completed callback.
__weak void | HAL_SAI_ErrorCallback (SAI_HandleTypeDef *hsai)
SAI error callback.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the SAI data
    transfers.

    (+) There are two modes of transfer:
      (++) Blocking mode : The communication is performed in the polling mode.
           The status of all data processing is returned by the same function
           after finishing transfer.
      (++) No-Blocking mode : The communication is performed using Interrupts
           or DMA. These functions return the status of the transfer startup.
           The end of the data processing will be indicated through the
           dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.

    (+) Blocking mode functions are :
      (++) HAL_SAI_Transmit()
      (++) HAL_SAI_Receive()
      (++) HAL_SAI_TransmitReceive()

    (+) Non Blocking mode functions with Interrupt are :
      (++) HAL_SAI_Transmit_IT()
      (++) HAL_SAI_Receive_IT()
      (++) HAL_SAI_TransmitReceive_IT()

    (+) Non Blocking mode functions with DMA are :
      (++) HAL_SAI_Transmit_DMA()
      (++) HAL_SAI_Receive_DMA()
      (++) HAL_SAI_TransmitReceive_DMA()

    (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
      (++) HAL_SAI_TxCpltCallback()
      (++) HAL_SAI_RxCpltCallback()
      (++) HAL_SAI_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_SAI_Abort ( SAI_HandleTypeDef * hsai )

Abort the current transfer and disable the SAI.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1173 of file stm32h7xx_hal_sai.c.

References HAL_DMA_Abort(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, SAI_Disable(), and __SAI_HandleTypeDef::State.

Referenced by HAL_SAI_IRQHandler().

HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode ( SAI_HandleTypeDef * hsai )

Disable the Rx mute detection.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1444 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::mutecallback, SAI_IT_MUTEDET, and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode ( SAI_HandleTypeDef * hsai )

Disable the Tx mute mode.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1403 of file stm32h7xx_hal_sai.c.

References HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_DMAPause ( SAI_HandleTypeDef * hsai )

Pause the audio stream playing from the Media.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1072 of file stm32h7xx_hal_sai.c.

References __SAI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SAI_DMAResume ( SAI_HandleTypeDef * hsai )

Resume the audio stream playing from the Media.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1092 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_ENABLE, and __SAI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SAI_DMAStop ( SAI_HandleTypeDef * hsai )

Stop the audio stream playing from the Media.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1119 of file stm32h7xx_hal_sai.c.

References __DMA_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_ERROR_NO_XFER, HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, SAI_Disable(), and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode | ( | SAI_HandleTypeDef * | hsai,
 |  | SAIcallback | callback,
 |  | uint16_t | counter
 | ) |  |

Enable the Rx mute detection.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
callback,: function called when the mute is detected.
counter,: number a data before mute detection max 63.
Return values:
HAL status

Definition at line 1421 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_ENABLE_IT, assert_param, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, IS_SAI_BLOCK_MUTE_COUNTER, __SAI_HandleTypeDef::mutecallback, SAI_IT_MUTEDET, SAI_xCR2_MUTECNT_OFFSET, and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode | ( | SAI_HandleTypeDef * | hsai,
 |  | uint16_t | val
 | ) |  |

Enable the Tx mute mode.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
val,: value sent during the mute SAI Block Mute Value
Return values:
HAL status

Definition at line 1384 of file stm32h7xx_hal_sai.c.

References assert_param, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, IS_SAI_BLOCK_MUTE_VALUE, and __SAI_HandleTypeDef::State.

void HAL_SAI_ErrorCallback ( SAI_HandleTypeDef * hsai )

SAI error callback.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1703 of file stm32h7xx_hal_sai.c.

Referenced by HAL_SAI_IRQHandler(), SAI_DMAAbort(), and SAI_DMAError().

void HAL_SAI_IRQHandler ( SAI_HandleTypeDef * hsai )

Handle SAI interrupt request.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1463 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __SAI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SAI_Abort(), HAL_SAI_ERROR_AFSDET, HAL_SAI_ERROR_CNREADY, HAL_SAI_ERROR_LFSDET, HAL_SAI_ERROR_OVR, HAL_SAI_ERROR_UDR, HAL_SAI_ERROR_WCKCFG, HAL_SAI_ErrorCallback(), HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::InterruptServiceRoutine, __SAI_HandleTypeDef::mutecallback, SAI_DMAAbort(), SAI_FLAG_AFSDET, SAI_FLAG_CNRDY, SAI_FLAG_LFSDET, SAI_FLAG_MUTEDET, SAI_FLAG_OVRUDR, SAI_FLAG_WCKCFG, SAI_IT_AFSDET, SAI_IT_CNRDY, SAI_IT_FREQ, SAI_IT_LFSDET, SAI_IT_MUTEDET, SAI_IT_OVRUDR, SAI_IT_WCKCFG, __SAI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, and __SAI_HandleTypeDef::XferCount.

HAL_StatusTypeDef HAL_SAI_Receive | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 855 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_ENABLE, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SAI_ERROR_NONE, HAL_SAI_ERROR_TIMEOUT, HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_Disable(), SAI_FIFOSTATUS_EMPTY, SAI_NOCOMPANDING, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Receive_DMA | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Return values:
HAL status

Definition at line 1315 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, __SAI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SAI_ERROR_NONE, HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DMAError(), SAI_DMARxCplt(), SAI_DMARxHalfCplt(), SAI_InterruptFlag(), SAI_MODE_DMA, __SAI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __SAI_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Receive_IT | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Return values:
HAL status

Definition at line 1014 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_NONE, HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::InterruptServiceRoutine, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_InterruptFlag(), SAI_MODE_IT, SAI_NOCOMPANDING, SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

void HAL_SAI_RxCpltCallback ( SAI_HandleTypeDef * hsai )

Rx Transfer completed callback.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1671 of file stm32h7xx_hal_sai.c.

Referenced by SAI_DMARxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), and SAI_Receive_IT8Bit().

void HAL_SAI_RxHalfCpltCallback ( SAI_HandleTypeDef * hsai )

Rx Transfer half completed callback.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1687 of file stm32h7xx_hal_sai.c.

Referenced by SAI_DMARxHalfCplt().

HAL_StatusTypeDef HAL_SAI_Transmit | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 755 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_ENABLE, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SAI_ERROR_NONE, HAL_SAI_ERROR_TIMEOUT, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_Disable(), SAI_FIFOSTATUS_FULL, SAI_FillFifo(), SAI_NOCOMPANDING, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Transmit_DMA | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 1228 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, __SAI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_GetTick(), HAL_SAI_ERROR_NONE, HAL_SAI_ERROR_TIMEOUT, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DMAError(), SAI_DMATxCplt(), SAI_DMATxHalfCplt(), SAI_FIFOSTATUS_EMPTY, SAI_InterruptFlag(), SAI_LONG_TIMEOUT, SAI_MODE_DMA, __SAI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __SAI_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Transmit_IT | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 952 of file stm32h7xx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_NONE, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::InterruptServiceRoutine, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_FillFifo(), SAI_InterruptFlag(), SAI_MODE_IT, SAI_NOCOMPANDING, SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), SAI_Transmit_IT8Bit(), __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

void HAL_SAI_TxCpltCallback ( SAI_HandleTypeDef * hsai )

Tx Transfer completed callback.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1639 of file stm32h7xx_hal_sai.c.

Referenced by SAI_DMATxCplt(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

void HAL_SAI_TxHalfCpltCallback ( SAI_HandleTypeDef * hsai )

Tx Transfer Half completed callback.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1655 of file stm32h7xx_hal_sai.c.

Referenced by SAI_DMATxHalfCplt().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
SAI Exported Functions

Peripheral State functions. More...

Functions

HAL_SAI_StateTypeDef | HAL_SAI_GetState (SAI_HandleTypeDef *hsai)
Return the SAI handle state.
uint32_t | HAL_SAI_GetError (SAI_HandleTypeDef *hsai)
Return the SAI error code.

Detailed Description

Peripheral State functions.

  ===============================================================================
                ##### Peripheral State and Errors functions #####
  ===============================================================================
  [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_SAI_GetError ( SAI_HandleTypeDef * hsai )

Return the SAI error code.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for the specified SAI Block.
Return values:
SAI Error Code

Definition at line 1750 of file stm32h7xx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCode.

HAL_SAI_StateTypeDef HAL_SAI_GetState ( SAI_HandleTypeDef * hsai )

Return the SAI handle state.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL state

Definition at line 1739 of file stm32h7xx_hal_sai.c.

References __SAI_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI_PdmInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_PdmInitTypeDef Struct Reference
SAI PDM Structure definition

#include <stm32h7xx_hal_sai.h>

Data Fields

FunctionalState | Activation
uint32_t | MicPairsNbr
uint32_t | ClockEnable

Detailed Description

Definition at line 84 of file stm32h7xx_hal_sai.h.

Field Documentation

FunctionalState SAI_PdmInitTypeDef::Activation

Enable/Disable PDM interface

Definition at line 86 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_PdmInitTypeDef::ClockEnable

Specifies which clock must be enabled. This parameter can be a values combination of SAI PDM Clock Enable

Definition at line 89 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_PdmInitTypeDef::MicPairsNbr

Specifies the number of microphone pairs used. This parameter must be a number between Min_Data = 1 and Max_Data = 4.

Definition at line 87 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sai.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_InitTypeDef Struct Reference
SAI Init Structure definition

#include <stm32h7xx_hal_sai.h>

Data Fields

uint32_t | AudioMode
uint32_t | Synchro
uint32_t | SynchroExt
uint32_t | OutputDrive
uint32_t | NoDivider
uint32_t | FIFOThreshold
uint32_t | AudioFrequency
uint32_t | Mckdiv
uint32_t | MckOverSampling
uint32_t | MonoStereoMode
uint32_t | CompandingMode
uint32_t | TriState
SAI_PdmInitTypeDef PdmInit
uint32_t | Protocol
uint32_t | DataSize
uint32_t | FirstBit
uint32_t | ClockStrobing

Detailed Description

Definition at line 101 of file stm32h7xx_hal_sai.h.

Field Documentation

uint32_t SAI_InitTypeDef::AudioFrequency

Specifies the audio frequency sampling. This parameter can be a value of SAI Audio Frequency

Definition at line 132 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::AudioMode

Specifies the SAI Block audio Mode. This parameter can be a value of SAI Block Mode

Definition at line 103 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

uint32_t SAI_InitTypeDef::ClockStrobing

Specifies the SAI Block clock strobing edge sensitivity. This parameter can be a value of SAI Block Clock Strobing

Definition at line 165 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_InitTypeDef::CompandingMode

Specifies the companding mode type. This parameter can be a value of SAI Block Companding Mode

Definition at line 145 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), and SAI_FillFifo().

uint32_t SAI_InitTypeDef::DataSize

Specifies the SAI Block data size. This parameter can be a value of SAI Block Data Size

Definition at line 159 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), SAI_FillFifo(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_InitTypeDef::FIFOThreshold

Specifies SAI Block FIFO threshold. This parameter can be a value of SAI Block Fifo Threshold

Definition at line 129 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::FirstBit

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of SAI Block MSB LSB transmission

Definition at line 162 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_InitTypeDef::Mckdiv

Specifies the master clock divider, the parameter will be used if for AudioFrequency the user choice This parameter must be a number between Min_Data = 0 and Max_Data = 63

Definition at line 135 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::MckOverSampling

Specifies the master clock oversampling. This parameter can be a value of SAI Block Master Clock OverSampling

Definition at line 139 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::MonoStereoMode

Specifies if the mono or stereo mode is selected. This parameter can be a value of SAI Mono Stereo Mode

Definition at line 142 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::NoDivider

Specifies whether master clock will be divided or not. This parameter can be a value of SAI Block NoDivider

Note:
: If bit NOMCK in the SAI_xCR1 register is cleared, the frame length should be aligned to a number equal to a power of 2, from 8 to 256. If bit NOMCK in the SAI_xCR1 register is set, the frame length can take any of the values without constraint since the input clock of the audio block should be equal to the bit clock. There is no MCLK_x clock which can be output.

Definition at line 120 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::OutputDrive

Specifies when SAI Block outputs are driven. This parameter can be a value of SAI Block Output Drive

Note:
this value has to be set before enabling the audio block but after the audio block configuration.

Definition at line 115 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

SAI_PdmInitTypeDef SAI_InitTypeDef::PdmInit

Specifies the PDM configuration.

Definition at line 151 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::Protocol

Specifies the SAI Block protocol. This parameter can be a value of SAI Block Protocol

Definition at line 156 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

uint32_t SAI_InitTypeDef::Synchro

Specifies SAI Block synchronization This parameter can be a value of SAI Block Synchronization

Definition at line 106 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::SynchroExt

Specifies SAI external output synchronization, this setup is common for BlockA and BlockB This parameter can be a value of SAI External synchronisation

Note:
: If both audio blocks of same SAI are used, this parameter has to be set to the same value for each audio block

Definition at line 109 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::TriState

Specifies the companding mode type. This parameter can be a value of SAI TRIState Management

Definition at line 148 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sai.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI_FrameInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_FrameInitTypeDef Struct Reference
SAI Frame Structure definition

#include <stm32h7xx_hal_sai.h>

Data Fields

uint32_t | FrameLength
uint32_t | ActiveFrameLength
uint32_t | FSDefinition
uint32_t | FSPolarity
uint32_t | FSOffset

Detailed Description

Definition at line 176 of file stm32h7xx_hal_sai.h.

Field Documentation

uint32_t SAI_FrameInitTypeDef::ActiveFrameLength

Specifies the Frame synchronization active level length. This Parameter specifies the length in number of bit clock (SCK + 1) of the active level of FS signal in audio frame. This parameter must be a number between Min_Data = 1 and Max_Data = 128

Definition at line 185 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FrameLength

Specifies the Frame length, the number of SCK clocks for each audio frame. This parameter must be a number between Min_Data = 8 and Max_Data = 256.

Note:
: If master clock MCLK_x pin is declared as an output, the frame length should be aligned to a number equal to power of 2 in order to keep in an audio frame, an integer number of MCLK pulses by bit Clock.

Definition at line 179 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FSDefinition

Specifies the Frame synchronization definition. This parameter can be a value of SAI Block FS Definition

Definition at line 190 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FSOffset

Specifies the Frame synchronization Offset. This parameter can be a value of SAI Block FS Offset

Definition at line 196 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FSPolarity

Specifies the Frame synchronization Polarity. This parameter can be a value of SAI Block FS Polarity

Definition at line 193 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sai.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI_SlotInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_SlotInitTypeDef Struct Reference
SAI Slot Structure definition

#include <stm32h7xx_hal_sai.h>

Data Fields

uint32_t | FirstBitOffset
uint32_t | SlotSize
uint32_t | SlotNumber
uint32_t | SlotActive

Detailed Description

Definition at line 208 of file stm32h7xx_hal_sai.h.

Field Documentation

uint32_t SAI_SlotInitTypeDef::FirstBitOffset

Specifies the position of first data transfer bit in the slot. This parameter must be a number between Min_Data = 0 and Max_Data = 24

Definition at line 210 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_SlotInitTypeDef::SlotActive

Specifies the slots in audio frame that will be activated. This parameter can be a value of SAI Block Slot Active

Definition at line 219 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_SlotInitTypeDef::SlotNumber

Specifies the number of slot in the audio frame. This parameter must be a number between Min_Data = 1 and Max_Data = 16

Definition at line 216 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_SlotInitTypeDef::SlotSize

Specifies the Slot Size. This parameter can be a value of SAI Block Slot Size

Definition at line 213 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sai.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Handle Structure definition

Data Structures | Typedefs
SAI Handle Structure definition
SAI Exported Types

SAI handle Structure definition. More...

Data Structures

struct | __SAI_HandleTypeDef

Typedefs

typedef struct __SAI_HandleTypeDef | SAI_HandleTypeDef

Detailed Description

SAI handle Structure definition.

Typedef Documentation

typedef struct __SAI_HandleTypeDef SAI_HandleTypeDef
Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: __SAI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SAI_HandleTypeDef Struct Reference
SAI Handle Structure definition

#include <stm32h7xx_hal_sai.h>

Data Fields

SAI_Block_TypeDef * | Instance
SAI_InitTypeDef Init
SAI_FrameInitTypeDef FrameInit
SAI_SlotInitTypeDef SlotInit
uint8_t * | pBuffPtr
uint16_t | XferSize
uint16_t | XferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
SAIcallback mutecallback
void(* | InterruptServiceRoutine )(struct __SAI_HandleTypeDef *hsai)
HAL_LockTypeDef | Lock
__IO HAL_SAI_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

Definition at line 230 of file stm32h7xx_hal_sai.h.

Field Documentation

__IO uint32_t __SAI_HandleTypeDef::ErrorCode

SAI Error code

Definition at line 258 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_DeInit(), HAL_SAI_GetError(), HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_Disable(), SAI_DMAAbort(), and SAI_DMAError().

SAI_FrameInitTypeDef __SAI_HandleTypeDef::FrameInit

SAI Frame configuration parameters

Definition at line 236 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

DMA_HandleTypeDef* __SAI_HandleTypeDef::hdmarx

SAI Rx DMA handle parameters

Definition at line 248 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DMAStop(), HAL_SAI_IRQHandler(), HAL_SAI_Receive_DMA(), and SAI_DMAError().

DMA_HandleTypeDef* __SAI_HandleTypeDef::hdmatx

SAI Tx DMA handle parameters

Definition at line 246 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DMAStop(), HAL_SAI_IRQHandler(), HAL_SAI_Transmit_DMA(), and SAI_DMAError().

SAI_InitTypeDef __SAI_HandleTypeDef::Init

SAI communication parameters

Definition at line 234 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), HAL_SD_ConfigWideBusOperation(), HAL_SD_InitCard(), SAI_FillFifo(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

SAI_Block_TypeDef* __SAI_HandleTypeDef::Instance

SAI Blockx registers base address

Definition at line 232 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DeInit(), HAL_SAI_DisableTxMuteMode(), HAL_SAI_DMAPause(), HAL_SAI_DMAResume(), HAL_SAI_DMAStop(), HAL_SAI_EnableRxMuteMode(), HAL_SAI_EnableTxMuteMode(), HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), HAL_SAIEx_ConfigPdmMicDelay(), SAI_Disable(), SAI_DMAAbort(), SAI_DMAError(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_FillFifo(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

void(* __SAI_HandleTypeDef::InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai)

Definition at line 252 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), HAL_SAI_Receive_IT(), and HAL_SAI_Transmit_IT().

HAL_LockTypeDef __SAI_HandleTypeDef::Lock

SAI locking object

Definition at line 254 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

SAIcallback __SAI_HandleTypeDef::mutecallback

SAI mute callback

Definition at line 250 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_DisableRxMuteMode(), HAL_SAI_EnableRxMuteMode(), and HAL_SAI_IRQHandler().

uint8_t* __SAI_HandleTypeDef::pBuffPtr

Pointer to SAI transfer Buffer

Definition at line 240 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_FillFifo(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

SAI_SlotInitTypeDef __SAI_HandleTypeDef::SlotInit

SAI Slot configuration parameters

Definition at line 238 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

__IO HAL_SAI_StateTypeDef __SAI_HandleTypeDef::State

SAI communication state

Definition at line 256 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DeInit(), HAL_SAI_DisableRxMuteMode(), HAL_SAI_DisableTxMuteMode(), HAL_SAI_DMAStop(), HAL_SAI_EnableRxMuteMode(), HAL_SAI_EnableTxMuteMode(), HAL_SAI_GetState(), HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), HAL_SAIEx_ConfigPdmMicDelay(), SAI_DMAAbort(), SAI_DMAError(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

uint16_t __SAI_HandleTypeDef::XferCount

SAI transfer counter

Definition at line 244 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_DMAAbort(), SAI_DMAError(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_FillFifo(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

uint16_t __SAI_HandleTypeDef::XferSize

SAI transfer size

Definition at line 242 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sai.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Exported Types

Modules | Typedefs | Enumerations
SAI Exported Types
SAI

Modules

SAI PDM Structure definition

SAI PDM Init structure definition.

SAI Init Structure definition

SAI Init Structure definition.

SAI Frame Structure definition

SAI Frame Init structure definition.

SAI Slot Structure definition

SAI Block Slot Init Structure definition.

SAI Handle Structure definition

SAI handle Structure definition.

Typedefs

typedef void(* SAIcallback )(void)
SAI Callback prototype.

Enumerations

enum HAL_SAI_StateTypeDef {
HAL_SAI_STATE_RESET = 0x00U, HAL_SAI_STATE_READY = 0x01U, HAL_SAI_STATE_BUSY = 0x02U, HAL_SAI_STATE_BUSY_TX = 0x12U,
HAL_SAI_STATE_BUSY_RX = 0x22U
}
HAL State structures definition. More...

Typedef Documentation

typedef void(* SAIcallback)(void)

SAI Callback prototype.

Definition at line 78 of file stm32h7xx_hal_sai.h.

Enumeration Type Documentation

enum HAL_SAI_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_SAI_STATE_RESET

SAI not yet initialized or disabled

HAL_SAI_STATE_READY

SAI initialized and ready for use

HAL_SAI_STATE_BUSY

SAI internal process is ongoing

HAL_SAI_STATE_BUSY_TX

Data transmission process is ongoing

HAL_SAI_STATE_BUSY_RX

Data reception process is ongoing

Definition at line 66 of file stm32h7xx_hal_sai.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Error Code

Defines
SAI Error Code
SAI Exported Constants

Defines

#define | HAL_SAI_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_SAI_ERROR_OVR ((uint32_t)0x00000001U)
#define | HAL_SAI_ERROR_UDR ((uint32_t)0x00000002U)
#define | HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004U)
#define | HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008U)
#define | HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U)
#define | HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020U)
#define | HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U)
#define | HAL_SAI_ERROR_DMA ((uint32_t)0x00000080U)

Define Documentation

#define HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004U)

Anticipated Frame synchronisation detection

Definition at line 280 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U)

codec not ready

Definition at line 282 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_DMA ((uint32_t)0x00000080U)

DMA error

Definition at line 285 of file stm32h7xx_hal_sai.h.

Referenced by SAI_DMAError().

#define HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008U)

Late Frame synchronisation detection

Definition at line 281 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 277 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_DeInit(), HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001U)

Overrun Error

Definition at line 278 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U)

Timeout error

Definition at line 284 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and SAI_Disable().

#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002U)

Underrun error

Definition at line 279 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020U)

Wrong clock configuration

Definition at line 283 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_DMAAbort().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI External synchronisation

Defines
SAI External synchronisation
SAI Exported Constants

Defines

#define | SAI_SYNCEXT_DISABLE 0
#define | SAI_SYNCEXT_OUTBLOCKA_ENABLE 1
#define | SAI_SYNCEXT_OUTBLOCKB_ENABLE 2

Define Documentation

#define SAI_SYNCEXT_DISABLE 0

Definition at line 293 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1

Definition at line 294 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2

Definition at line 295 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Supported protocol

Defines
SAI Supported protocol
SAI Exported Constants

Defines

#define | SAI_I2S_STANDARD 0
#define | SAI_I2S_MSBJUSTIFIED 1
#define | SAI_I2S_LSBJUSTIFIED 2
#define | SAI_PCM_LONG 3
#define | SAI_PCM_SHORT 4

Define Documentation

#define SAI_I2S_LSBJUSTIFIED 2

Definition at line 305 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitI2S().

#define SAI_I2S_MSBJUSTIFIED 1

Definition at line 304 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitI2S().

#define SAI_I2S_STANDARD 0

Definition at line 303 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitI2S().

#define SAI_PCM_LONG 3

Definition at line 306 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitPCM().

#define SAI_PCM_SHORT 4

Definition at line 307 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitPCM().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI protocol data size

Defines
SAI protocol data size
SAI Exported Constants

Defines

#define | SAI_PROTOCOL_DATASIZE_16BIT 0
#define | SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1
#define | SAI_PROTOCOL_DATASIZE_24BIT 2
#define | SAI_PROTOCOL_DATASIZE_32BIT 3

Define Documentation

#define SAI_PROTOCOL_DATASIZE_16BIT 0

Definition at line 315 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1

Definition at line 316 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_PROTOCOL_DATASIZE_24BIT 2

Definition at line 317 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_PROTOCOL_DATASIZE_32BIT 3

Definition at line 318 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Audio Frequency

Defines
SAI Audio Frequency
SAI Exported Constants

Defines

#define | SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000U)
#define | SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000U)
#define | SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000U)
#define | SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100U)
#define | SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000U)
#define | SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050U)
#define | SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000U)
#define | SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025U)
#define | SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000U)
#define | SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0U)

Define Documentation

#define SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025U)

Definition at line 333 of file stm32h7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000U)

Definition at line 332 of file stm32h7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000U)

Definition at line 326 of file stm32h7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050U)

Definition at line 331 of file stm32h7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000U)

Definition at line 330 of file stm32h7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100U)

Definition at line 329 of file stm32h7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000U)

Definition at line 328 of file stm32h7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000U)

Definition at line 334 of file stm32h7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000U)

Definition at line 327 of file stm32h7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0U)

Definition at line 335 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Block Master Clock OverSampling

Defines
SAI Block Master Clock OverSampling
SAI Exported Constants

Defines

#define | SAI_MCK_OVERSAMPLING_DISABLE ((uint32_t)0x00000000U)
#define | SAI_MCK_OVERSAMPLING_ENABLE ((uint32_t)SAI_xCR1_OSR)

Define Documentation

#define SAI_MCK_OVERSAMPLING_DISABLE ((uint32_t)0x00000000U)

Definition at line 343 of file stm32h7xx_hal_sai.h.

#define SAI_MCK_OVERSAMPLING_ENABLE ((uint32_t)SAI_xCR1_OSR)

Definition at line 344 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI PDM Clock Enable

Defines
SAI PDM Clock Enable
SAI Exported Constants

Defines

#define | SAI_PDM_CLOCK1_ENABLE ((uint32_t)SAI_PDMCR_CKEN1)
#define | SAI_PDM_CLOCK2_ENABLE ((uint32_t)SAI_PDMCR_CKEN2)
#define | SAI_PDM_CLOCK3_ENABLE ((uint32_t)SAI_PDMCR_CKEN3)
#define | SAI_PDM_CLOCK4_ENABLE ((uint32_t)SAI_PDMCR_CKEN4)

Define Documentation

#define SAI_PDM_CLOCK1_ENABLE ((uint32_t)SAI_PDMCR_CKEN1)

Definition at line 352 of file stm32h7xx_hal_sai.h.

#define SAI_PDM_CLOCK2_ENABLE ((uint32_t)SAI_PDMCR_CKEN2)

Definition at line 353 of file stm32h7xx_hal_sai.h.

#define SAI_PDM_CLOCK3_ENABLE ((uint32_t)SAI_PDMCR_CKEN3)

Definition at line 354 of file stm32h7xx_hal_sai.h.

#define SAI_PDM_CLOCK4_ENABLE ((uint32_t)SAI_PDMCR_CKEN4)

Definition at line 355 of file stm32h7xx_hal_sai.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Block Mode

Defines
SAI Block Mode
SAI Exported Constants

Defines

#define | SAI_MODEMASTER_TX ((uint32_t)0x00000000U)
#define | SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0)
#define | SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1)
#define | SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))

Define Documentation

#define SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0)

Definition at line 364 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), and SAI_InterruptFlag().

#define SAI_MODEMASTER_TX ((uint32_t)0x00000000U)

Definition at line 363 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

#define SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))

Definition at line 366 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InterruptFlag().

#define SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1)

Definition at line 365 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Block Protocol

Defines
SAI Block Protocol
SAI Exported Constants

Defines

#define | SAI_FREE_PROTOCOL ((uint32_t)0x00000000U)
#define | SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0)
#define | SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1)

Define Documentation

#define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1)

Definition at line 377 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InterruptFlag().

#define SAI_FREE_PROTOCOL ((uint32_t)0x00000000U)

Definition at line 375 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

#define SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0)

Definition at line 376 of file stm32h7xx_hal_sai.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Block Data Size

Defines
SAI Block Data Size
SAI Exported Constants

Defines

#define | SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1)
#define | SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
#define | SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2)
#define | SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
#define | SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
#define | SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))

Define Documentation

#define SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))

Definition at line 386 of file stm32h7xx_hal_sai.h.

#define SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2)

Definition at line 387 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), SAI_FillFifo(), SAI_InitI2S(), and SAI_InitPCM().

#define SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))

Definition at line 388 of file stm32h7xx_hal_sai.h.

#define SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))

Definition at line 389 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))

Definition at line 390 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1)

Definition at line 385 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), and SAI_FillFifo().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Block MSB LSB transmission

Defines
SAI Block MSB LSB transmission
SAI Exported Constants

Defines

#define | SAI_FIRSTBIT_MSB ((uint32_t)0x00000000U)
#define | SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST)

Define Documentation

#define SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST)

Definition at line 399 of file stm32h7xx_hal_sai.h.

#define SAI_FIRSTBIT_MSB ((uint32_t)0x00000000U)

Definition at line 398 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Block Clock Strobing

Defines
SAI Block Clock Strobing
SAI Exported Constants

Defines

#define | SAI_CLOCKSTROBING_FALLINGEDGE 0
#define | SAI_CLOCKSTROBING_RISINGEDGE 1

Define Documentation

#define SAI_CLOCKSTROBING_FALLINGEDGE 0

Definition at line 407 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_CLOCKSTROBING_RISINGEDGE 1

Definition at line 408 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Block Synchronization

Defines
SAI Block Synchronization
SAI Exported Constants

Defines

#define | SAI_ASYNCHRONOUS 0
#define | SAI_SYNCHRONOUS 1
#define | SAI_SYNCHRONOUS_EXT_SAI1 2
#define | SAI_SYNCHRONOUS_EXT_SAI2 3

Define Documentation

#define SAI_ASYNCHRONOUS 0

Asynchronous

Definition at line 416 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_SYNCHRONOUS 1

Synchronous with other block of same SAI

Definition at line 417 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_SYNCHRONOUS_EXT_SAI1 2

Synchronous with other SAI, SAI1

Definition at line 418 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_SYNCHRONOUS_EXT_SAI2 3

Synchronous with other SAI, SAI2

Definition at line 419 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Block Output Drive

Defines
SAI Block Output Drive
SAI Exported Constants

Defines

#define | SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000U)
#define | SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV)

Define Documentation

#define SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000U)

Definition at line 427 of file stm32h7xx_hal_sai.h.

#define SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV)

Definition at line 428 of file stm32h7xx_hal_sai.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Block NoDivider

Defines
SAI Block NoDivider
SAI Exported Constants

Defines

#define | SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000U)
#define | SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NOMCK)

Define Documentation

#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NOMCK)

Definition at line 437 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000U)

Definition at line 436 of file stm32h7xx_hal_sai.h.

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STM32H753xx HAL User Manual: SAI Block FS Definition

Defines
SAI Block FS Definition
SAI Exported Constants

Defines

#define | SAI_FS_STARTFRAME ((uint32_t)0x00000000U)
#define | SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF)

Define Documentation

#define SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF)

Definition at line 447 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S().

#define SAI_FS_STARTFRAME ((uint32_t)0x00000000U)

Definition at line 446 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitPCM().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Block FS Polarity

Defines
SAI Block FS Polarity
SAI Exported Constants

Defines

#define | SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000U)
#define | SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPOL)

Define Documentation

#define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPOL)

Definition at line 456 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000U)

Definition at line 455 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S().

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STM32H753xx HAL User Manual: SAI Block FS Offset

Defines
SAI Block FS Offset
SAI Exported Constants

Defines

#define | SAI_FS_FIRSTBIT ((uint32_t)0x00000000U)
#define | SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF)

Define Documentation

#define SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF)

Definition at line 465 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_FS_FIRSTBIT ((uint32_t)0x00000000U)

Definition at line 464 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Block Slot Size

Defines
SAI Block Slot Size
SAI Exported Constants

Defines

#define | SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000U)
#define | SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
#define | SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1)

Define Documentation

#define SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0)

Definition at line 475 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1)

Definition at line 476 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000U)

Definition at line 474 of file stm32h7xx_hal_sai.h.

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STM32H753xx HAL User Manual: SAI Block Slot Active

Defines
SAI Block Slot Active
SAI Exported Constants

Defines

#define | SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000U)
#define | SAI_SLOTACTIVE_0 ((uint32_t)0x00000001U)
#define | SAI_SLOTACTIVE_1 ((uint32_t)0x00000002U)
#define | SAI_SLOTACTIVE_2 ((uint32_t)0x00000004U)
#define | SAI_SLOTACTIVE_3 ((uint32_t)0x00000008U)
#define | SAI_SLOTACTIVE_4 ((uint32_t)0x00000010U)
#define | SAI_SLOTACTIVE_5 ((uint32_t)0x00000020U)
#define | SAI_SLOTACTIVE_6 ((uint32_t)0x00000040U)
#define | SAI_SLOTACTIVE_7 ((uint32_t)0x00000080U)
#define | SAI_SLOTACTIVE_8 ((uint32_t)0x00000100U)
#define | SAI_SLOTACTIVE_9 ((uint32_t)0x00000200U)
#define | SAI_SLOTACTIVE_10 ((uint32_t)0x00000400U)
#define | SAI_SLOTACTIVE_11 ((uint32_t)0x00000800U)
#define | SAI_SLOTACTIVE_12 ((uint32_t)0x00001000U)
#define | SAI_SLOTACTIVE_13 ((uint32_t)0x00002000U)
#define | SAI_SLOTACTIVE_14 ((uint32_t)0x00004000U)
#define | SAI_SLOTACTIVE_15 ((uint32_t)0x00008000U)
#define | SAI_SLOTACTIVE_ALL ((uint32_t)0x0000FFFFU)

Define Documentation

#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000U)

Definition at line 484 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_0 ((uint32_t)0x00000001U)

Definition at line 485 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_1 ((uint32_t)0x00000002U)

Definition at line 486 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_10 ((uint32_t)0x00000400U)

Definition at line 495 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_11 ((uint32_t)0x00000800U)

Definition at line 496 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_12 ((uint32_t)0x00001000U)

Definition at line 497 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_13 ((uint32_t)0x00002000U)

Definition at line 498 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_14 ((uint32_t)0x00004000U)

Definition at line 499 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_15 ((uint32_t)0x00008000U)

Definition at line 500 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_2 ((uint32_t)0x00000004U)

Definition at line 487 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_3 ((uint32_t)0x00000008U)

Definition at line 488 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_4 ((uint32_t)0x00000010U)

Definition at line 489 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_5 ((uint32_t)0x00000020U)

Definition at line 490 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_6 ((uint32_t)0x00000040U)

Definition at line 491 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_7 ((uint32_t)0x00000080U)

Definition at line 492 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_8 ((uint32_t)0x00000100U)

Definition at line 493 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_9 ((uint32_t)0x00000200U)

Definition at line 494 of file stm32h7xx_hal_sai.h.

#define SAI_SLOTACTIVE_ALL ((uint32_t)0x0000FFFFU)

Definition at line 501 of file stm32h7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

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STM32H753xx HAL User Manual: SAI Mono Stereo Mode

Defines
SAI Mono Stereo Mode
SAI Exported Constants

Defines

#define | SAI_STEREOMODE ((uint32_t)0x00000000U)
#define | SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)

Define Documentation

#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)

Definition at line 510 of file stm32h7xx_hal_sai.h.

#define SAI_STEREOMODE ((uint32_t)0x00000000U)

Definition at line 509 of file stm32h7xx_hal_sai.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI TRIState Management

Defines
SAI TRIState Management
SAI Exported Constants

Defines

#define | SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000U)
#define | SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS)

Define Documentation

#define SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000U)

Definition at line 518 of file stm32h7xx_hal_sai.h.

#define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS)

Definition at line 519 of file stm32h7xx_hal_sai.h.

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STM32H753xx HAL User Manual: SAI Block Fifo Threshold

Defines
SAI Block Fifo Threshold
SAI Exported Constants

Defines

#define | SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000U)
#define | SAI_FIFOTHRESHOLD_1QF ((uint32_t)(SAI_xCR2_FTH_0))
#define | SAI_FIFOTHRESHOLD_HF ((uint32_t)(SAI_xCR2_FTH_1))
#define | SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
#define | SAI_FIFOTHRESHOLD_FULL ((uint32_t)(SAI_xCR2_FTH_2))

Define Documentation

#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)(SAI_xCR2_FTH_0))

Definition at line 528 of file stm32h7xx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))

Definition at line 530 of file stm32h7xx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000U)

Definition at line 527 of file stm32h7xx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)(SAI_xCR2_FTH_2))

Definition at line 531 of file stm32h7xx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_HF ((uint32_t)(SAI_xCR2_FTH_1))

Definition at line 529 of file stm32h7xx_hal_sai.h.

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STM32H753xx HAL User Manual: SAI Block Companding Mode

Defines
SAI Block Companding Mode
SAI Exported Constants

Defines

#define | SAI_NOCOMPANDING ((uint32_t)0x00000000U)
#define | SAI_ULAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1))
#define | SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
#define | SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
#define | SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))

Define Documentation

#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))

Definition at line 541 of file stm32h7xx_hal_sai.h.

#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))

Definition at line 543 of file stm32h7xx_hal_sai.h.

#define SAI_NOCOMPANDING ((uint32_t)0x00000000U)

Definition at line 539 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), and SAI_FillFifo().

#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1))

Definition at line 540 of file stm32h7xx_hal_sai.h.

#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))

Definition at line 542 of file stm32h7xx_hal_sai.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Block Mute Value

Defines
SAI Block Mute Value
SAI Exported Constants

Defines

#define | SAI_ZERO_VALUE ((uint32_t)0x00000000U)
#define | SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL)

Define Documentation

#define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL)

Definition at line 552 of file stm32h7xx_hal_sai.h.

#define SAI_ZERO_VALUE ((uint32_t)0x00000000U)

Definition at line 551 of file stm32h7xx_hal_sai.h.

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STM32H753xx HAL User Manual: SAI Block Interrupts Definition

Defines
SAI Block Interrupts Definition
SAI Exported Constants

Defines

#define | SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)
#define | SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)
#define | SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)
#define | SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)
#define | SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)
#define | SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)
#define | SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)

Define Documentation

#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)

Definition at line 565 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)

Definition at line 564 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)

Definition at line 563 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)

Definition at line 566 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)

Definition at line 561 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_DisableRxMuteMode(), HAL_SAI_EnableRxMuteMode(), and HAL_SAI_IRQHandler().

#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)

Definition at line 560 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)

Definition at line 562 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Block Flags Definition

Defines
SAI Block Flags Definition
SAI Exported Constants

Defines

#define | SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)
#define | SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)
#define | SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)
#define | SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)
#define | SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)
#define | SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)
#define | SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)

Define Documentation

#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)

Definition at line 579 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)

Definition at line 578 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)

Definition at line 577 of file stm32h7xx_hal_sai.h.

#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)

Definition at line 580 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)

Definition at line 575 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)

Definition at line 574 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), and SAI_Receive_IT8Bit().

#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)

Definition at line 576 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Block Fifo Status Level

Defines
SAI Block Fifo Status Level
SAI Exported Constants

Defines

#define | SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000U)
#define | SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000U)
#define | SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000U)
#define | SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000U)
#define | SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000U)
#define | SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000U)

Define Documentation

#define SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000U)

Definition at line 590 of file stm32h7xx_hal_sai.h.

#define SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000U)

Definition at line 592 of file stm32h7xx_hal_sai.h.

#define SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000U)

Definition at line 588 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), and HAL_SAI_Transmit_DMA().

#define SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000U)

Definition at line 593 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Transmit(), and SAI_FillFifo().

#define SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000U)

Definition at line 591 of file stm32h7xx_hal_sai.h.

#define SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000U)

Definition at line 589 of file stm32h7xx_hal_sai.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Exported Macros

Defines
SAI Exported Macros
SAI

macros to handle interrupts and specific configurations More...

Defines

#define | __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
Reset SAI handle state.
#define | __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
Enable or disable the specified SAI interrupts.
#define | __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
#define | __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SAI interrupt source is enabled or not.
#define | __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SAI flag is set or not.
#define | __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
Clear the specified SAI pending flag.
#define | __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
#define | __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)

Detailed Description

macros to handle interrupts and specific configurations

Define Documentation

#define __HAL_SAI_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->CLRFR = (__FLAG__))

Clear the specified SAI pending flag.

Parameters:
__HANDLE__,: specifies the SAI Handle.
__FLAG__,: specifies the flag to check. This parameter can be any combination of the following values:
  • SAI_FLAG_OVRUDR: Clear Overrun underrun
  • SAI_FLAG_MUTEDET: Clear Mute detection
  • SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
  • SAI_FLAG_FREQ: Clear FIFO request
  • SAI_FLAG_CNRDY: Clear Codec not ready
  • SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
  • SAI_FLAG_LFSDET: Clear Late frame synchronization detection
Return values:
None

Definition at line 675 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), and SAI_Receive_IT8Bit().

#define __HAL_SAI_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)

Definition at line 678 of file stm32h7xx_hal_sai.h.

Referenced by SAI_Disable().

#define __HAL_SAI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))

Definition at line 629 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_DisableRxMuteMode(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

#define __HAL_SAI_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)

Definition at line 677 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_DMAResume(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

#define __HAL_SAI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))

Enable or disable the specified SAI interrupts.

Parameters:
__HANDLE__,: specifies the SAI Handle.
__INTERRUPT__,: specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • SAI_IT_OVRUDR: Overrun underrun interrupt enable
  • SAI_IT_MUTEDET: Mute detection interrupt enable
  • SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
  • SAI_IT_FREQ: FIFO request interrupt enable
  • SAI_IT_CNRDY: Codec not ready interrupt enable
  • SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
  • SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
Return values:
None

Definition at line 628 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_EnableRxMuteMode(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

#define __HAL_SAI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Check whether the specified SAI flag is set or not.

Parameters:
__HANDLE__,: specifies the SAI Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SAI_FLAG_OVRUDR: Overrun underrun flag.
  • SAI_FLAG_MUTEDET: Mute detection flag.
  • SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
  • SAI_FLAG_FREQ: FIFO request flag.
  • SAI_FLAG_CNRDY: Codec not ready flag.
  • SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
  • SAI_FLAG_LFSDET: Late frame synchronization detection flag.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 659 of file stm32h7xx_hal_sai.h.

#define __HAL_SAI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SAI interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the SAI Handle.
__INTERRUPT__,: specifies the SAI interrupt source to check. This parameter can be one of the following values:
  • SAI_IT_OVRUDR: Overrun underrun interrupt enable
  • SAI_IT_MUTEDET: Mute detection interrupt enable
  • SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
  • SAI_IT_FREQ: FIFO request interrupt enable
  • SAI_IT_CNRDY: Codec not ready interrupt enable
  • SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
  • SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 644 of file stm32h7xx_hal_sai.h.

#define __HAL_SAI_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)

Reset SAI handle state.

Parameters:
__HANDLE__,: specifies the SAI Handle.
Return values:
None

Definition at line 613 of file stm32h7xx_hal_sai.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI_Private_Macros

Defines
SAI_Private_Macros
SAI

Defines

#define | IS_SAI_BLOCK_SYNCEXT(STATE)
#define | IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)
#define | IS_SAI_PROTOCOL_DATASIZE(DATASIZE)
#define | IS_SAI_AUDIO_FREQUENCY(AUDIO)
#define | IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE)
#define | IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 4U))
#define | IS_SAI_PDM_CLOCK_ENABLE(CLOCK)
#define | IS_SAI_BLOCK_MODE(MODE)
#define | IS_SAI_BLOCK_PROTOCOL(PROTOCOL)
#define | IS_SAI_BLOCK_DATASIZE(DATASIZE)
#define | IS_SAI_BLOCK_FIRST_BIT(BIT)
#define | IS_SAI_BLOCK_CLOCK_STROBING(CLOCK)
#define | IS_SAI_BLOCK_SYNCHRO(SYNCHRO)
#define | IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE)
#define | IS_SAI_BLOCK_NODIVIDER(NODIVIDER)
#define | IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
#define | IS_SAI_BLOCK_MUTE_VALUE(VALUE)
#define | IS_SAI_BLOCK_COMPANDING_MODE(MODE)
#define | IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD)
#define | IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE)
#define | IS_SAI_MONO_STEREO_MODE(MODE)
#define | IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
#define | IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
#define | IS_SAI_BLOCK_SLOT_SIZE(SIZE)
#define | IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
#define | IS_SAI_BLOCK_FS_OFFSET(OFFSET)
#define | IS_SAI_BLOCK_FS_POLARITY(POLARITY)
#define | IS_SAI_BLOCK_FS_DEFINITION(DEFINITION)
#define | IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
#define | IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
#define | IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))

Define Documentation

#define IS_SAI_AUDIO_FREQUENCY ( AUDIO )
Value:
(((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_48K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_32K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_16K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_8K)   || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))

Definition at line 781 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_ACTIVE_FRAME ( LENGTH ) ((1 <= (LENGTH)) && ((LENGTH) <= 128))

Definition at line 875 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_CLOCK_STROBING ( CLOCK )
Value:
(((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
                                            ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))

Definition at line 815 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_COMPANDING_MODE ( MODE )
Value:
(((MODE) == SAI_NOCOMPANDING)         || \
                                               ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
                                               ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
                                               ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
                                               ((MODE) == SAI_ALAW_2CPL_COMPANDING))

Definition at line 834 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_DATASIZE ( DATASIZE )
Value:
(((DATASIZE) == SAI_DATASIZE_8)  || \
                                         ((DATASIZE) == SAI_DATASIZE_10) || \
                                         ((DATASIZE) == SAI_DATASIZE_16) || \
                                         ((DATASIZE) == SAI_DATASIZE_20) || \
                                         ((DATASIZE) == SAI_DATASIZE_24) || \
                                         ((DATASIZE) == SAI_DATASIZE_32))

Definition at line 805 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FIFO_THRESHOLD ( THRESHOLD )
Value:
(((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY)   || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF)     || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF)      || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF)     || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))

Definition at line 840 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FIRST_BIT ( BIT )
Value:
(((BIT) == SAI_FIRSTBIT_MSB) || \
                                     ((BIT) == SAI_FIRSTBIT_LSB))

Definition at line 812 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FIRSTBIT_OFFSET ( OFFSET ) ((OFFSET) <= 24)

Definition at line 860 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FRAME_LENGTH ( LENGTH ) ((8 <= (LENGTH)) && ((LENGTH) <= 256))

Definition at line 873 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FS_DEFINITION ( DEFINITION )
Value:
(((DEFINITION) == SAI_FS_STARTFRAME) || \
                                                ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))

Definition at line 868 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FS_OFFSET ( OFFSET )
Value:
(((OFFSET) == SAI_FS_FIRSTBIT) || \
                                        ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))

Definition at line 862 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FS_POLARITY ( POLARITY )
Value:
(((POLARITY) == SAI_FS_ACTIVE_LOW) || \
                                            ((POLARITY) == SAI_FS_ACTIVE_HIGH))

Definition at line 865 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_MASTER_DIVIDER ( DIVIDER ) ((DIVIDER) <= 15)

Definition at line 871 of file stm32h7xx_hal_sai.h.

#define IS_SAI_BLOCK_MCK_OVERSAMPLING ( VALUE )
Value:
(((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \
                                              ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE))

Definition at line 787 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_MODE ( MODE )
Value:
(((MODE) == SAI_MODEMASTER_TX) || \
                                  ((MODE) == SAI_MODEMASTER_RX) || \
                                  ((MODE) == SAI_MODESLAVE_TX)  || \
                                  ((MODE) == SAI_MODESLAVE_RX))

Definition at line 796 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_MUTE_COUNTER ( COUNTER ) ((COUNTER) <= 63)

Definition at line 829 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_EnableRxMuteMode().

#define IS_SAI_BLOCK_MUTE_VALUE ( VALUE )
Value:
(((VALUE) == SAI_ZERO_VALUE)     || \
                                           ((VALUE) == SAI_LAST_SENT_VALUE))

Definition at line 831 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_EnableTxMuteMode().

#define IS_SAI_BLOCK_NODIVIDER ( NODIVIDER )
Value:
(((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
                                           ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))

Definition at line 826 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_OUTPUT_DRIVE ( DRIVE )
Value:
(((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
                                          ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))

Definition at line 823 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_PROTOCOL ( PROTOCOL )
Value:
(((PROTOCOL) == SAI_FREE_PROTOCOL)  || \
                                         ((PROTOCOL) == SAI_AC97_PROTOCOL)  || \
                                         ((PROTOCOL) == SAI_SPDIF_PROTOCOL))

Definition at line 801 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SLOT_NUMBER ( NUMBER ) ((1 <= (NUMBER)) && ((NUMBER) <= 16))

Definition at line 854 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SLOT_SIZE ( SIZE )
Value:
(((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
                                      ((SIZE) == SAI_SLOTSIZE_16B)      || \
                                      ((SIZE) == SAI_SLOTSIZE_32B))

Definition at line 856 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SYNCEXT ( STATE )
Value:
(((STATE) == SAI_SYNCEXT_DISABLE) ||\
                                     ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
                                     ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))

Definition at line 766 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SYNCHRO ( SYNCHRO )
Value:
(((SYNCHRO) == SAI_ASYNCHRONOUS)         || \
                                       ((SYNCHRO) == SAI_SYNCHRONOUS)          || \
                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \
                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))

Definition at line 818 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT ( STATE )
Value:
(((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
                                                 ((STATE) == SAI_OUTPUT_RELEASED))

Definition at line 846 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_MONO_STEREO_MODE ( MODE )
Value:
(((MODE) == SAI_MONOMODE) ||\
                                       ((MODE) == SAI_STEREOMODE))

Definition at line 849 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_PDM_CLOCK_ENABLE ( CLOCK )
Value:
(((CLOCK) != 0U) && \
                                       (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE | \
                                                     SAI_PDM_CLOCK3_ENABLE | SAI_PDM_CLOCK4_ENABLE)) == 0U))

Definition at line 792 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_PDM_MIC_PAIRS_NUMBER ( VALUE ) ((1U <= (VALUE)) && ((VALUE) <= 4U))

Definition at line 790 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), and HAL_SAIEx_ConfigPdmMicDelay().

#define IS_SAI_PROTOCOL_DATASIZE ( DATASIZE )
Value:
(((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT)         ||\
                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT)         ||\
                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))

Definition at line 776 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol().

#define IS_SAI_SLOT_ACTIVE ( ACTIVE ) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)

Definition at line 852 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_SUPPORTED_PROTOCOL ( PROTOCOL )
Value:
(((PROTOCOL) == SAI_I2S_STANDARD)     ||\
                                               ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
                                               ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
                                               ((PROTOCOL) == SAI_PCM_LONG)         ||\
                                               ((PROTOCOL) == SAI_PCM_SHORT))

Definition at line 770 of file stm32h7xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol().

Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
SAIEx Extended Exported Functions

SAIEx control functions. More...

Functions

HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay (SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
Configure PDM microphone delays.

Detailed Description

SAIEx control functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Modify PDM microphone delays

Function Documentation

HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay | ( | SAI_HandleTypeDef * | hsai,
 |  | SAIEx_PdmMicDelayParamTypeDef * | pdmMicDelay
 | ) |  |

Configure PDM microphone delays.

Parameters:
hsai,: SAI handle.
pdmMicDelay,: Microphone delays configuration.
Return values:
HAL status

Definition at line 91 of file stm32h7xx_hal_sai_ex.c.

References assert_param, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, IS_SAI_PDM_MIC_DELAY, IS_SAI_PDM_MIC_PAIRS_NUMBER, SAIEx_PdmMicDelayParamTypeDef::LeftDelay, SAIEx_PdmMicDelayParamTypeDef::MicPair, SAIEx_PdmMicDelayParamTypeDef::RightDelay, SAI_PDM_DELAY_MASK, SAI_PDM_DELAY_OFFSET, SAI_PDM_RIGHT_DELAY_OFFSET, and __SAI_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAIEx_PdmMicDelayParamTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAIEx_PdmMicDelayParamTypeDef Struct Reference
SAIEx Exported Types

PDM microphone delay structure definition. More...

#include <stm32h7xx_hal_sai_ex.h>

Data Fields

uint32_t | MicPair
uint32_t | LeftDelay
uint32_t | RightDelay

Detailed Description

PDM microphone delay structure definition.

Definition at line 66 of file stm32h7xx_hal_sai_ex.h.

Field Documentation

uint32_t SAIEx_PdmMicDelayParamTypeDef::LeftDelay

Specifies the delay in PDM clock unit to apply on left microphone. This parameter must be a number between Min_Data = 0 and Max_Data = 7.

Definition at line 71 of file stm32h7xx_hal_sai_ex.h.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

uint32_t SAIEx_PdmMicDelayParamTypeDef::MicPair

Specifies which pair of microphones is selected. This parameter must be a number between Min_Data = 1 and Max_Data = 4.

Definition at line 68 of file stm32h7xx_hal_sai_ex.h.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

uint32_t SAIEx_PdmMicDelayParamTypeDef::RightDelay

Specifies the delay in PDM clock unit to apply on right microphone. This parameter must be a number between Min_Data = 0 and Max_Data = 7.

Definition at line 74 of file stm32h7xx_hal_sai_ex.h.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sai_ex.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAIEx Extended Private Macros

Defines
SAIEx Extended Private Macros
SAIEx

Defines

#define IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U)

Define Documentation

#define IS_SAI_PDM_MIC_DELAY ( VALUE ) ((VALUE) <= 7U)

Definition at line 110 of file stm32h7xx_hal_sai_ex.h.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAIEx

Modules | Defines
SAIEx
STM32H7xx_HAL_Driver

SAI Extended HAL module driver. More...

Modules

SAIEx Extended Exported Functions
SAIEx Exported Types
SAIEx Extended Private Macros

Defines

#define | SAI_PDM_DELAY_MASK 0x77U
#define | SAI_PDM_DELAY_OFFSET 8U
#define | SAI_PDM_RIGHT_DELAY_OFFSET 4U

Detailed Description

SAI Extended HAL module driver.

Define Documentation

#define SAI_PDM_DELAY_MASK 0x77U

Definition at line 59 of file stm32h7xx_hal_sai_ex.c.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

#define SAI_PDM_DELAY_OFFSET 8U

Definition at line 60 of file stm32h7xx_hal_sai_ex.c.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

#define SAI_PDM_RIGHT_DELAY_OFFSET 4U

Definition at line 61 of file stm32h7xx_hal_sai_ex.c.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SD Card Internal DMA Buffer structure

Enumerations
SD Card Internal DMA Buffer structure
SDEx Exported Types

Enumerations

enum HAL_SDEx_DMABuffer_MemoryTypeDef { SD_DMA_BUFFER0 = 0x00U, SD_DMA_BUFFER1 = 0x01U }

Enumeration Type Documentation

enum HAL_SDEx_DMABuffer_MemoryTypeDef
Enumerator:
SD_DMA_BUFFER0

selects SD internal DMA Buffer 0

SD_DMA_BUFFER1

selects SD internal DMA Buffer 1

Definition at line 66 of file stm32h7xx_hal_sd_ex.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: MultiBuffer functions

Functions
MultiBuffer functions
SDEx Exported Functions

Multibuffer functions. More...

Functions

HAL_StatusTypeDef | HAL_SDEx_ConfigDMAMultiBuffer (SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, uint32_t BufferSize)
Configure DMA Dual Buffer mode.
HAL_StatusTypeDef | HAL_SDEx_ReadBlocksDMAMultiBuffer (SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SDEx_WriteBlocksDMAMultiBuffer (SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SDEx_ChangeDMABuffer (SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
Change the DMA Buffer0 or Buffer1 address on the fly.
void | HAL_SDEx_Read_DMADoubleBuffer0CpltCallback (SD_HandleTypeDef *hsd)
Read DMA Buffer 0 Transfer completed callbacks.
void | HAL_SDEx_Read_DMADoubleBuffer1CpltCallback (SD_HandleTypeDef *hsd)
Read DMA Buffer 1 Transfer completed callbacks.
void | HAL_SDEx_Write_DMADoubleBuffer0CpltCallback (SD_HandleTypeDef *hsd)
Write DMA Buffer 0 Transfer completed callbacks.
void | HAL_SDEx_Write_DMADoubleBuffer1CpltCallback (SD_HandleTypeDef *hsd)
Write DMA Buffer 1 Transfer completed callbacks.

Detailed Description

Multibuffer functions.

  ==============================================================================
          ##### Multibuffer functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to configure the multibuffer mode and start read and write
    multibuffer mode for SD HAL driver.

Function Documentation

HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SDEx_DMABuffer_MemoryTypeDef | Buffer,
 |  | uint32_t * | pDataBuffer
 | ) |  |

Change the DMA Buffer0 or Buffer1 address on the fly.

Parameters:
hsd,: pointer to a SD_HandleTypeDef structure.
Buffer,: the buffer to be changed, This parameter can be one of the following values: SD_DMA_BUFFER0 or SD_DMA_BUFFER1
pDataBuffer,: The new address
Note:
The BUFFER0 address can be changed only when the current transfer use BUFFER1 and the BUFFER1 address can be changed only when the current transfer use BUFFER0.
Return values:
HAL status

Definition at line 279 of file stm32h7xx_hal_sd_ex.c.

References SD_HandleTypeDef::Instance, and SD_DMA_BUFFER0.

HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pDataBuffer0,
 |  | uint32_t * | pDataBuffer1,
 |  | uint32_t | BufferSize
 | ) |  |

Configure DMA Dual Buffer mode.

The Data transfer is managed by an Internal DMA.

Parameters:
hsd,: SD handle
pDataBuffer0,: Pointer to the buffer0 that will contain/receive the transfered data
pDataBuffer1,: Pointer to the buffer1 that will contain/receive the transfered data
BufferSize,: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
Return values:
HAL status

Definition at line 101 of file stm32h7xx_hal_sd_ex.c.

References HAL_SD_STATE_READY, SD_HandleTypeDef::Instance, and SD_HandleTypeDef::State.

void HAL_SDEx_Read_DMADoubleBuffer0CpltCallback ( SD_HandleTypeDef * hsd )

Read DMA Buffer 0 Transfer completed callbacks.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 2879 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_IRQHandler().

void HAL_SDEx_Read_DMADoubleBuffer1CpltCallback ( SD_HandleTypeDef * hsd )

Read DMA Buffer 1 Transfer completed callbacks.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 2894 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_IRQHandler().

HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Reads block(s) from a specified address in a card.

The received Data will be stored in Buffer0 and Buffer1. Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function.

Parameters:
hsd,: SD handle
BlockAdd,: Block Address from where data is to be read
NumberOfBlocks,: Total number of blocks to read
Return values:
HAL status

Definition at line 125 of file stm32h7xx_hal_sd_ex.c.

References __HAL_SD_ENABLE_IT, BLOCKSIZE, CARD_SDHC_SDXC, HAL_SD_CardInfoTypeDef::CardType, SD_HandleTypeDef::Context, SD_HandleTypeDef::ErrorCode, HAL_SD_ERROR_ADDR_OUT_OF_RANGE, HAL_SD_ERROR_NONE, HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::LogBlockNbr, SD_CONTEXT_DMA, SD_CONTEXT_READ_MULTIPLE_BLOCK, SD_HandleTypeDef::SdCard, and SD_HandleTypeDef::State.

void HAL_SDEx_Write_DMADoubleBuffer0CpltCallback ( SD_HandleTypeDef * hsd )

Write DMA Buffer 0 Transfer completed callbacks.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 2909 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_IRQHandler().

void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback ( SD_HandleTypeDef * hsd )

Write DMA Buffer 1 Transfer completed callbacks.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 2924 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_IRQHandler().

HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Write block(s) to a specified address in a card.

The transfered Data are stored in Buffer0 and Buffer1. Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function.

Parameters:
hsd,: SD handle
BlockAdd,: Block Address from where data is to be read
NumberOfBlocks,: Total number of blocks to read
Return values:
HAL status

Definition at line 201 of file stm32h7xx_hal_sd_ex.c.

References __HAL_SD_ENABLE_IT, BLOCKSIZE, CARD_SDHC_SDXC, HAL_SD_CardInfoTypeDef::CardType, SD_HandleTypeDef::Context, SD_HandleTypeDef::ErrorCode, HAL_SD_ERROR_ADDR_OUT_OF_RANGE, HAL_SD_ERROR_NONE, HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::LogBlockNbr, SD_CONTEXT_DMA, SD_CONTEXT_WRITE_MULTIPLE_BLOCK, SD_HandleTypeDef::SdCard, and SD_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SDRAM Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SDRAM_Init (SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
Performs the SDRAM device initialization sequence.
HAL_StatusTypeDef | HAL_SDRAM_DeInit (SDRAM_HandleTypeDef *hsdram)
Perform the SDRAM device initialization sequence.
__weak void | HAL_SDRAM_MspInit (SDRAM_HandleTypeDef *hsdram)
SDRAM MSP Init.
__weak void | HAL_SDRAM_MspDeInit (SDRAM_HandleTypeDef *hsdram)
SDRAM MSP DeInit.
void | HAL_SDRAM_IRQHandler (SDRAM_HandleTypeDef *hsdram)
This function handles SDRAM refresh error interrupt request.
__weak void | HAL_SDRAM_RefreshErrorCallback (SDRAM_HandleTypeDef *hsdram)
SDRAM Refresh error callback.
__weak void | HAL_SDRAM_DMA_XferCpltCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete callback.
__weak void | HAL_SDRAM_DMA_XferErrorCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete error callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
           ##### SDRAM Initialization and de_initialization functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to initialize/de-initialize
    the SDRAM memory

Function Documentation

HAL_StatusTypeDef HAL_SDRAM_DeInit ( SDRAM_HandleTypeDef * hsdram )

Perform the SDRAM device initialization sequence.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
HAL status

Definition at line 178 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_MspDeInit(), HAL_SDRAM_STATE_RESET, SDRAM_HandleTypeDef::Init, SDRAM_HandleTypeDef::Instance, and SDRAM_HandleTypeDef::State.

void HAL_SDRAM_DMA_XferCpltCallback ( MDMA_HandleTypeDef * hmdma )

DMA transfer complete callback.

Parameters:
hmdma,: pointer to a MDMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 268 of file stm32h7xx_hal_sdram.c.

Referenced by HAL_SDRAM_Read_DMA(), and HAL_SDRAM_Write_DMA().

void HAL_SDRAM_DMA_XferErrorCallback ( MDMA_HandleTypeDef * hmdma )

DMA transfer complete error callback.

Parameters:
hmdma,: DMA handle
Return values:
None

Definition at line 283 of file stm32h7xx_hal_sdram.c.

Referenced by HAL_SDRAM_Read_DMA(), and HAL_SDRAM_Write_DMA().

HAL_StatusTypeDef HAL_SDRAM_Init | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | FMC_SDRAM_TimingTypeDef * | Timing
 | ) |  |

Performs the SDRAM device initialization sequence.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Timing,: Pointer to SDRAM control timing structure
Return values:
HAL status

Definition at line 138 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_MspInit(), HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_READY, HAL_SDRAM_STATE_RESET, SDRAM_HandleTypeDef::Init, SDRAM_HandleTypeDef::Instance, SDRAM_HandleTypeDef::Lock, and SDRAM_HandleTypeDef::State.

void HAL_SDRAM_IRQHandler ( SDRAM_HandleTypeDef * hsdram )

This function handles SDRAM refresh error interrupt request.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
HAL status

Definition at line 233 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_RefreshErrorCallback(), and SDRAM_HandleTypeDef::Instance.

void HAL_SDRAM_MspDeInit ( SDRAM_HandleTypeDef * hsdram )

SDRAM MSP DeInit.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
None

Definition at line 217 of file stm32h7xx_hal_sdram.c.

Referenced by HAL_SDRAM_DeInit().

void HAL_SDRAM_MspInit ( SDRAM_HandleTypeDef * hsdram )

SDRAM MSP Init.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
None

Definition at line 201 of file stm32h7xx_hal_sdram.c.

Referenced by HAL_SDRAM_Init().

void HAL_SDRAM_RefreshErrorCallback ( SDRAM_HandleTypeDef * hsdram )

SDRAM Refresh error callback.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
None

Definition at line 252 of file stm32h7xx_hal_sdram.c.

Referenced by HAL_SDRAM_IRQHandler().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Input and Output functions

Functions
Input and Output functions
SDRAM Exported Functions

Input Output and memory control functions. More...

Functions

HAL_StatusTypeDef | HAL_SDRAM_Read_8b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
Reads 8-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_8b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
Writes 8-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_16b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
Reads 16-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_16b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
Writes 16-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_32b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads 32-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_32b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes 32-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_DMA (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads a Words data from the SDRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SDRAM_Write_DMA (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes a Words data buffer to SDRAM memory using DMA transfer.

Detailed Description

Input Output and memory control functions.

  ==============================================================================
                    ##### SDRAM Input and Output functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to use and control the SDRAM memory

Function Documentation

HAL_StatusTypeDef HAL_SDRAM_Read_16b | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads 16-bit data buffer from the SDRAM memory.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress,: Pointer to read start address
pDstBuffer,: Pointer to destination buffer
BufferSize,: Size of the buffer to read from memory
Return values:
HAL status

Definition at line 405 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_PRECHARGED, and SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_Read_32b | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads 32-bit data buffer from the SDRAM memory.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress,: Pointer to read start address
pDstBuffer,: Pointer to destination buffer
BufferSize,: Size of the buffer to read from memory
Return values:
HAL status

Definition at line 488 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_PRECHARGED, and SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_Read_8b | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint8_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads 8-bit data buffer from the SDRAM memory.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress,: Pointer to read start address
pDstBuffer,: Pointer to destination buffer
BufferSize,: Size of the buffer to read from memory
Return values:
HAL status

Definition at line 320 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_PRECHARGED, and SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_Read_DMA | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads a Words data from the SDRAM memory using DMA transfer.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress,: Pointer to read start address
pDstBuffer,: Pointer to destination buffer
BufferSize,: Size of the buffer to read from memory
Return values:
HAL status

Definition at line 571 of file stm32h7xx_hal_sdram.c.

References HAL_MDMA_Start_IT(), HAL_SDRAM_DMA_XferCpltCallback(), HAL_SDRAM_DMA_XferErrorCallback(), HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_PRECHARGED, SDRAM_HandleTypeDef::hmdma, SDRAM_HandleTypeDef::State, __MDMA_HandleTypeDef::XferCpltCallback, and __MDMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SDRAM_Write_16b | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes 16-bit data buffer to SDRAM memory.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress,: Pointer to write start address
pSrcBuffer,: Pointer to source buffer to write
BufferSize,: Size of the buffer to write to memory
Return values:
HAL status

Definition at line 445 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_PRECHARGED, HAL_SDRAM_STATE_WRITE_PROTECTED, and SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_Write_32b | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes 32-bit data buffer to SDRAM memory.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress,: Pointer to write start address
pSrcBuffer,: Pointer to source buffer to write
BufferSize,: Size of the buffer to write to memory
Return values:
HAL status

Definition at line 528 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_PRECHARGED, HAL_SDRAM_STATE_WRITE_PROTECTED, and SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_Write_8b | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint8_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes 8-bit data buffer to SDRAM memory.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress,: Pointer to write start address
pSrcBuffer,: Pointer to source buffer to write
BufferSize,: Size of the buffer to write to memory
Return values:
HAL status

Definition at line 361 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_PRECHARGED, HAL_SDRAM_STATE_WRITE_PROTECTED, and SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_Write_DMA | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes a Words data buffer to SDRAM memory using DMA transfer.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress,: Pointer to write start address
pSrcBuffer,: Pointer to source buffer to write
BufferSize,: Size of the buffer to write to memory
Return values:
HAL status

Definition at line 612 of file stm32h7xx_hal_sdram.c.

References HAL_MDMA_Start_IT(), HAL_SDRAM_DMA_XferCpltCallback(), HAL_SDRAM_DMA_XferErrorCallback(), HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_PRECHARGED, HAL_SDRAM_STATE_WRITE_PROTECTED, SDRAM_HandleTypeDef::hmdma, SDRAM_HandleTypeDef::State, __MDMA_HandleTypeDef::XferCpltCallback, and __MDMA_HandleTypeDef::XferErrorCallback.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Control functions

Functions
Control functions
SDRAM Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_SDRAM_WriteProtection_Enable (SDRAM_HandleTypeDef *hsdram)
Enables dynamically SDRAM write protection.
HAL_StatusTypeDef | HAL_SDRAM_WriteProtection_Disable (SDRAM_HandleTypeDef *hsdram)
Disables dynamically SDRAM write protection.
HAL_StatusTypeDef | HAL_SDRAM_SendCommand (SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
Sends Command to the SDRAM bank.
HAL_StatusTypeDef | HAL_SDRAM_ProgramRefreshRate (SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
Programs the SDRAM Memory Refresh rate.
HAL_StatusTypeDef | HAL_SDRAM_SetAutoRefreshNumber (SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
Sets the Number of consecutive SDRAM Memory auto Refresh commands.
uint32_t | HAL_SDRAM_GetModeStatus (SDRAM_HandleTypeDef *hsdram)
Returns the SDRAM memory current mode.

Detailed Description

management functions

  ==============================================================================
                         ##### SDRAM Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control dynamically
    the SDRAM interface.

Function Documentation

uint32_t HAL_SDRAM_GetModeStatus ( SDRAM_HandleTypeDef * hsdram )

Returns the SDRAM memory current mode.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
The SDRAM memory mode.

Definition at line 810 of file stm32h7xx_hal_sdram.c.

References SDRAM_HandleTypeDef::Init, and SDRAM_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t | RefreshRate
 | ) |  |

Programs the SDRAM Memory Refresh rate.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
RefreshRate,: The SDRAM refresh rate value
Return values:
HAL status

Definition at line 757 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_READY, SDRAM_HandleTypeDef::Instance, and SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_SendCommand | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | FMC_SDRAM_CommandTypeDef * | Command,
 |  | uint32_t | Timeout
 | ) |  |

Sends Command to the SDRAM bank.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Command,: SDRAM command structure
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 723 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_PRECHARGED, HAL_SDRAM_STATE_READY, SDRAM_HandleTypeDef::Instance, and SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t | AutoRefreshNumber
 | ) |  |

Sets the Number of consecutive SDRAM Memory auto Refresh commands.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
AutoRefreshNumber,: The SDRAM auto Refresh number
Return values:
HAL status

Definition at line 784 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_READY, SDRAM_HandleTypeDef::Instance, and SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable ( SDRAM_HandleTypeDef * hsdram )

Disables dynamically SDRAM write protection.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
HAL status

Definition at line 695 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_READY, SDRAM_HandleTypeDef::Init, SDRAM_HandleTypeDef::Instance, and SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable ( SDRAM_HandleTypeDef * hsdram )

Enables dynamically SDRAM write protection.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
HAL status

Definition at line 669 of file stm32h7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_WRITE_PROTECTED, SDRAM_HandleTypeDef::Init, SDRAM_HandleTypeDef::Instance, and SDRAM_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: State functions

Functions
State functions
SDRAM Exported Functions

Peripheral State functions. More...

Functions

HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState (SDRAM_HandleTypeDef *hsdram)
Returns the SDRAM state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### SDRAM State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the SDRAM controller
    and the data flow.

Function Documentation

HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState ( SDRAM_HandleTypeDef * hsdram )

Returns the SDRAM state.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
HAL state

Definition at line 841 of file stm32h7xx_hal_sdram.c.

References SDRAM_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SDRAM Exported Types

Data Structures | Enumerations
SDRAM Exported Types
SDRAM

Data Structures

struct SDRAM_HandleTypeDef
SDRAM handle Structure definition. More...

Enumerations

enum HAL_SDRAM_StateTypeDef {
HAL_SDRAM_STATE_RESET = 0x00U, HAL_SDRAM_STATE_READY = 0x01U, HAL_SDRAM_STATE_BUSY = 0x02U, HAL_SDRAM_STATE_ERROR = 0x03U,
HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U, HAL_SDRAM_STATE_PRECHARGED = 0x05U
}
HAL SDRAM State structure definition. More...

Enumeration Type Documentation

enum HAL_SDRAM_StateTypeDef

HAL SDRAM State structure definition.

Enumerator:
HAL_SDRAM_STATE_RESET

SDRAM not yet initialized or disabled

HAL_SDRAM_STATE_READY

SDRAM initialized and ready for use

HAL_SDRAM_STATE_BUSY

SDRAM internal process is ongoing

HAL_SDRAM_STATE_ERROR

SDRAM error state

HAL_SDRAM_STATE_WRITE_PROTECTED

SDRAM device write protected

HAL_SDRAM_STATE_PRECHARGED

SDRAM device precharged

Definition at line 67 of file stm32h7xx_hal_sdram.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SDRAM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SDRAM_HandleTypeDef Struct Reference
SDRAM Exported Types

SDRAM handle Structure definition. More...

#include <stm32h7xx_hal_sdram.h>

Data Fields

FMC_SDRAM_TypeDef * | Instance
FMC_SDRAM_InitTypeDef | Init
__IO HAL_SDRAM_StateTypeDef | State
HAL_LockTypeDef | Lock
MDMA_HandleTypeDef * hmdma

Detailed Description

SDRAM handle Structure definition.

Definition at line 81 of file stm32h7xx_hal_sdram.h.

Field Documentation

MDMA_HandleTypeDef* SDRAM_HandleTypeDef::hmdma

Pointer MDMA handler

Definition at line 91 of file stm32h7xx_hal_sdram.h.

Referenced by HAL_SDRAM_Read_DMA(), and HAL_SDRAM_Write_DMA().

FMC_SDRAM_InitTypeDef SDRAM_HandleTypeDef::Init

SDRAM device configuration parameters

Definition at line 85 of file stm32h7xx_hal_sdram.h.

Referenced by HAL_SDRAM_DeInit(), HAL_SDRAM_GetModeStatus(), HAL_SDRAM_Init(), HAL_SDRAM_WriteProtection_Disable(), and HAL_SDRAM_WriteProtection_Enable().

FMC_SDRAM_TypeDef* SDRAM_HandleTypeDef::Instance

Register base address

Definition at line 83 of file stm32h7xx_hal_sdram.h.

Referenced by HAL_SDRAM_DeInit(), HAL_SDRAM_GetModeStatus(), HAL_SDRAM_Init(), HAL_SDRAM_IRQHandler(), HAL_SDRAM_ProgramRefreshRate(), HAL_SDRAM_SendCommand(), HAL_SDRAM_SetAutoRefreshNumber(), HAL_SDRAM_WriteProtection_Disable(), and HAL_SDRAM_WriteProtection_Enable().

HAL_LockTypeDef SDRAM_HandleTypeDef::Lock

SDRAM locking object

Definition at line 89 of file stm32h7xx_hal_sdram.h.

Referenced by HAL_SDRAM_Init().

__IO HAL_SDRAM_StateTypeDef SDRAM_HandleTypeDef::State

SDRAM access state

Definition at line 87 of file stm32h7xx_hal_sdram.h.

Referenced by HAL_SDRAM_DeInit(), HAL_SDRAM_GetState(), HAL_SDRAM_Init(), HAL_SDRAM_ProgramRefreshRate(), HAL_SDRAM_Read_16b(), HAL_SDRAM_Read_32b(), HAL_SDRAM_Read_8b(), HAL_SDRAM_Read_DMA(), HAL_SDRAM_SendCommand(), HAL_SDRAM_SetAutoRefreshNumber(), HAL_SDRAM_Write_16b(), HAL_SDRAM_Write_32b(), HAL_SDRAM_Write_8b(), HAL_SDRAM_Write_DMA(), HAL_SDRAM_WriteProtection_Disable(), and HAL_SDRAM_WriteProtection_Enable().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sdram.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SDRAM Exported Macros

Defines
SDRAM Exported Macros
SDRAM

Defines

#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
Reset SDRAM handle state.

Define Documentation

#define __HAL_SDRAM_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)

Reset SDRAM handle state.

Parameters:
__HANDLE__,: specifies the SDRAM handle.
Return values:
None

Definition at line 109 of file stm32h7xx_hal_sdram.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD Private Constants

Defines
SMARTCARD Private Constants
SMARTCARD

Defines

#define | SMARTCARD_TEACK_REACK_TIMEOUT 1000
#define | USART_CR1_FIELDS
#define | USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL))
#define | USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP))
#define | USART_CR3_FIELDS

Define Documentation

#define SMARTCARD_TEACK_REACK_TIMEOUT 1000

SMARTCARD TX or RX enable acknowledge time-out value

Definition at line 154 of file stm32h7xx_hal_smartcard.c.

Referenced by SMARTCARD_CheckIdleState().

#define USART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
                                          USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 | \
                                          USART_CR1_FIFOEN))

USART CR1 fields of parameters set by SMARTCARD_SetConfig API

Definition at line 156 of file stm32h7xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL))

SMARTCARD clock-related USART CR2 fields of parameters

Definition at line 159 of file stm32h7xx_hal_smartcard.c.

#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP))

USART CR2 fields of parameters set by SMARTCARD_SetConfig API

Definition at line 160 of file stm32h7xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_CR3_FIELDS
Value:
((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT|\
                                          USART_CR3_TXFTCFG|USART_CR3_RXFTCFG))

USART CR3 fields of parameters set by SMARTCARD_SetConfig API

Definition at line 161 of file stm32h7xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SMARTCARD Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD MSP.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the USARTx
  associated to the SmartCard.
  (+) These parameters can be configured:
      (++) Baud Rate
      (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
      (++) Receiver/transmitter modes
      (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
      (++) Prescaler value
      (++) Guard bit time
      (++) NACK enabling or disabling on transmission error

  (+) The following advanced features can be configured as well:
      (++) TX and/or RX pin level inversion
      (++) data logical level inversion
      (++) RX and TX pins swap
      (++) RX overrun detection disabling
      (++) DMA disabling on RX error
      (++) MSB first on communication line
      (++) Time out enabling (and if activated, timeout value)
      (++) Block length
      (++) Auto-retry counter
  [..]
  The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
  (details for the procedures are available in reference manual).

The USART frame format is given in the following table:

Table 1. USART frame format. +---------------------------------------------------------------+ | M1M0 bits | PCE bit | USART frame | |-----------------------|---------------------------------------| | 01 | 1 | | SB | 8 bit data | PB | STB | | +---------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARD_DeInit ( SMARTCARD_HandleTypeDef * hsmartcard )

DeInitialize the SMARTCARD peripheral.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 316 of file stm32h7xx_hal_smartcard.c.

References assert_param, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_MspDeInit(), HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_RESET, SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_SMARTCARD_Init ( SMARTCARD_HandleTypeDef * hsmartcard )

Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 255 of file stm32h7xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_MspInit(), HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_RESET, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::Lock, SMARTCARD_ADVFEATURE_NO_INIT, SMARTCARD_AdvFeatureConfig(), SMARTCARD_CheckIdleState(), SMARTCARD_SetConfig(), and SMARTCARD_TRANSMISSION_COMPLETION_SETTING.

void HAL_SMARTCARD_MspDeInit ( SMARTCARD_HandleTypeDef * hsmartcard )

DeInitialize the SMARTCARD MSP.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 373 of file stm32h7xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_DeInit().

void HAL_SMARTCARD_MspInit ( SMARTCARD_HandleTypeDef * hsmartcard )

Initialize the SMARTCARD MSP.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 357 of file stm32h7xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_Init().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
SMARTCARD Exported Functions

SMARTCARD Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Abort (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_Abort_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsmartcard)
Handle SMARTCARD interrupt requests.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Tx Transfer completed callback.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Rx Transfer completed callback.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD error callback.
__weak void | HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Receive Complete callback.

Detailed Description

SMARTCARD Transmit and Receive functions.

  ==============================================================================
                         ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.

  [..]
    Smartcard is a single wire half duplex communication protocol.
    The Smartcard interface is designed to support asynchronous protocol Smartcards as
    defined in the ISO 7816-3 standard. The USART should be configured as:
    (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
    (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.

  [..]
    (+) There are two modes of transfer:
        (++) Blocking mode: The communication is performed in polling mode.
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (++) Non-Blocking mode: The communication is performed using Interrupts
             or DMA, the relevant API's return the HAL status.
             The end of the data processing will be indicated through the
             dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
        (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
             will be executed respectively at the end of the Transmit or Receive process
             The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
             error is detected.

    (+) Blocking mode APIs are :
        (++) HAL_SMARTCARD_Transmit()
        (++) HAL_SMARTCARD_Receive()

    (+) Non Blocking mode APIs with Interrupt are :
        (++) HAL_SMARTCARD_Transmit_IT()
        (++) HAL_SMARTCARD_Receive_IT()
        (++) HAL_SMARTCARD_IRQHandler()

    (+) Non Blocking mode functions with DMA are :
        (++) HAL_SMARTCARD_Transmit_DMA()
        (++) HAL_SMARTCARD_Receive_DMA()

    (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_SMARTCARD_TxCpltCallback()
        (++) HAL_SMARTCARD_RxCpltCallback()
        (++) HAL_SMARTCARD_ErrorCallback()

    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (+) HAL_SMARTCARD_Abort()
        (+) HAL_SMARTCARD_AbortTransmit()
        (+) HAL_SMARTCARD_AbortReceive()
        (+) HAL_SMARTCARD_Abort_IT()
        (+) HAL_SMARTCARD_AbortTransmit_IT()
        (+) HAL_SMARTCARD_AbortReceive_IT()

    (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
        (+) HAL_SMARTCARD_AbortCpltCallback()
        (+) HAL_SMARTCARD_AbortTransmitCpltCallback()
        (+) HAL_SMARTCARD_AbortReceiveCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
           and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
           If user wants to abort it, Abort services should be called by user.
       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
           This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
           Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARD_Abort ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing transfers (blocking mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 874 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing transfers (Interrupt mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1052 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SMARTCARD_AbortCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD Abort Complete callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1580 of file stm32h7xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_Abort_IT(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Receive transfer (blocking mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 996 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Receive transfer (Interrupt mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1255 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_DMARxOnlyAbortCallback(), and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SMARTCARD_AbortReceiveCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD Abort Receive Complete callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1612 of file stm32h7xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_AbortReceive_IT(), and SMARTCARD_DMARxOnlyAbortCallback().

HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Transmit transfer (blocking mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 942 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_CLEAR_FEF, SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Transmit transfer (Interrupt mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1178 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_CLEAR_FEF, SMARTCARD_DMATxOnlyAbortCallback(), SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SMARTCARD_AbortTransmitCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD Abort Complete callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1596 of file stm32h7xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_AbortTransmit_IT(), and SMARTCARD_DMATxOnlyAbortCallback().

void HAL_SMARTCARD_ErrorCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD error callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1564 of file stm32h7xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMAAbortOnError(), and SMARTCARD_DMAError().

void HAL_SMARTCARD_IRQHandler ( SMARTCARD_HandleTypeDef * hsmartcard )

Handle SMARTCARD interrupt requests.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1326 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_IT, __HAL_SMARTCARD_GET_IT, __HAL_SMARTCARD_GET_IT_SOURCE, SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_ERROR_FE, HAL_SMARTCARD_ERROR_NE, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_ERROR_ORE, HAL_SMARTCARD_ERROR_PE, HAL_SMARTCARD_ERROR_RTO, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_DMAAbortOnError(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_Receive_IT(), SMARTCARD_Transmit_IT(), SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Receive | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be received.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 556 of file stm32h7xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_FLAG_RXNE, and SMARTCARD_WaitOnFlagUntilTimeout().

HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be received.
Note:
The SMARTCARD-associated USART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
Return values:
HAL status

Definition at line 809 of file stm32h7xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pRxBuffPtr, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be received.
Return values:
HAL status

Definition at line 679 of file stm32h7xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pRxBuffPtr, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, and SMARTCARD_HandleTypeDef::RxXferSize.

void HAL_SMARTCARD_RxCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

Rx Transfer completed callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1548 of file stm32h7xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMAReceiveCplt(), and SMARTCARD_Receive_IT().

HAL_StatusTypeDef HAL_SMARTCARD_Transmit | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be sent.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 474 of file stm32h7xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Init, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_InitTypeDef::Mode, SMARTCARD_FLAG_TXE, SMARTCARD_MODE_TX_RX, SMARTCARD_RXDATA_FLUSH_REQUEST, SMARTCARD_TRANSMISSION_COMPLETION_FLAG, SMARTCARD_WaitOnFlagUntilTimeout(), SMARTCARD_HandleTypeDef::TxXferCount, and SMARTCARD_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be sent.
Return values:
HAL status

Definition at line 735 of file stm32h7xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_DMAError(), SMARTCARD_DMATransmitCplt(), SMARTCARD_RXDATA_FLUSH_REQUEST, SMARTCARD_HandleTypeDef::TxXferCount, SMARTCARD_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be sent.
Return values:
HAL status

Definition at line 614 of file stm32h7xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_RXDATA_FLUSH_REQUEST, SMARTCARD_HandleTypeDef::TxXferCount, and SMARTCARD_HandleTypeDef::TxXferSize.

void HAL_SMARTCARD_TxCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

Tx Transfer completed callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1532 of file stm32h7xx_hal_smartcard.c.

Referenced by SMARTCARD_EndTransmit_IT().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SMARTCARD Exported Functions

SMARTCARD State and Errors functions. More...

Functions

HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle state.
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle error code.

Detailed Description

SMARTCARD State and Errors functions.

  ==============================================================================
                  ##### Peripheral State and Errors functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to return the State of SmartCard
    handle and also return Peripheral Errors occurred during communication process
     (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
         of the SMARTCARD peripheral.
     (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
         communication.

Function Documentation

uint32_t HAL_SMARTCARD_GetError ( SMARTCARD_HandleTypeDef * hsmartcard )

Return the SMARTCARD handle error code.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
SMARTCARD handle Error Code

Definition at line 1667 of file stm32h7xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode.

HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState ( SMARTCARD_HandleTypeDef * hsmartcard )

Return the SMARTCARD handle state.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
SMARTCARD handle state

Definition at line 1651 of file stm32h7xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::gState, and SMARTCARD_HandleTypeDef::RxState.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD Private Functions

Functions
SMARTCARD Private Functions
SMARTCARD

Functions

static HAL_StatusTypeDef | SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral.
static void | SMARTCARD_AdvFeatureConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral advanced features.
static HAL_StatusTypeDef | SMARTCARD_CheckIdleState (SMARTCARD_HandleTypeDef *hsmartcard)
Check the SMARTCARD Idle State.
static HAL_StatusTypeDef | SMARTCARD_WaitOnFlagUntilTimeout (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle SMARTCARD Communication Timeout.
static void | SMARTCARD_EndTxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
static void | SMARTCARD_EndRxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | SMARTCARD_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD transmit process complete callback.
static void | SMARTCARD_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD receive process complete callback.
static void | SMARTCARD_DMAError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication error callback.
static void | SMARTCARD_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SMARTCARD_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SMARTCARD_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | SMARTCARD_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | SMARTCARD_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static HAL_StatusTypeDef | SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | SMARTCARD_EndTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Wrap up transmission in non-blocking mode.
static HAL_StatusTypeDef | SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.

Function Documentation

static void SMARTCARD_AdvFeatureConfig ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Configure the SMARTCARD associated USART peripheral advanced features.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1815 of file stm32h7xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, SMARTCARD_AdvFeatureInitTypeDef::DataInvert, SMARTCARD_AdvFeatureInitTypeDef::DMADisableonRxError, SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_ADVFEATURE_DATAINV, IS_SMARTCARD_ADVFEATURE_DMAONRXERROR, IS_SMARTCARD_ADVFEATURE_INIT, IS_SMARTCARD_ADVFEATURE_MSBFIRST, IS_SMARTCARD_ADVFEATURE_RXINV, IS_SMARTCARD_ADVFEATURE_SWAP, IS_SMARTCARD_ADVFEATURE_TXINV, IS_SMARTCARD_OVERRUN, SMARTCARD_AdvFeatureInitTypeDef::MSBFirst, SMARTCARD_AdvFeatureInitTypeDef::OverrunDisable, SMARTCARD_AdvFeatureInitTypeDef::RxPinLevelInvert, SMARTCARD_ADVFEATURE_DATAINVERT_INIT, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT, SMARTCARD_ADVFEATURE_MSBFIRST_INIT, SMARTCARD_ADVFEATURE_RXINVERT_INIT, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT, SMARTCARD_ADVFEATURE_SWAP_INIT, SMARTCARD_ADVFEATURE_TXINVERT_INIT, SMARTCARD_AdvFeatureInitTypeDef::Swap, and SMARTCARD_AdvFeatureInitTypeDef::TxPinLevelInvert.

Referenced by HAL_SMARTCARD_Init().

static HAL_StatusTypeDef SMARTCARD_CheckIdleState ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Check the SMARTCARD Idle State.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 1877 of file stm32h7xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_TEACK_REACK_TIMEOUT, and SMARTCARD_WaitOnFlagUntilTimeout().

Referenced by HAL_SMARTCARD_Init().

static void SMARTCARD_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2069 of file stm32h7xx_hal_smartcard.c.

References HAL_SMARTCARD_ErrorCallback(), __DMA_HandleTypeDef::Parent, SMARTCARD_HandleTypeDef::RxXferCount, and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_IRQHandler().

static void SMARTCARD_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD communication error callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2039 of file stm32h7xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_BUSY_TX, SMARTCARD_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_EndRxTransfer(), SMARTCARD_EndTxTransfer(), and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Receive_DMA(), and HAL_SMARTCARD_Transmit_DMA().

static void SMARTCARD_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD receive process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2014 of file stm32h7xx_hal_smartcard.c.

References HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, SMARTCARD_HandleTypeDef::RxState, and SMARTCARD_HandleTypeDef::RxXferCount.

Referenced by HAL_SMARTCARD_Receive_DMA().

static void SMARTCARD_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2128 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SMARTCARD_Abort_IT().

static void SMARTCARD_DMARxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2194 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_STATE_READY, __DMA_HandleTypeDef::Parent, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, and SMARTCARD_CLEAR_RTOF.

Referenced by HAL_SMARTCARD_AbortReceive_IT().

static void SMARTCARD_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD transmit process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1995 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Transmit_DMA().

static void SMARTCARD_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2086 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SMARTCARD_Abort_IT().

static void SMARTCARD_DMATxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2170 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_STATE_READY, __DMA_HandleTypeDef::Parent, SMARTCARD_CLEAR_FEF, and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_AbortTransmit_IT().

static void SMARTCARD_EndRxTransfer ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1978 of file stm32h7xx_hal_smartcard.c.

References HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_HandleTypeDef::RxState.

Referenced by HAL_SMARTCARD_IRQHandler(), and SMARTCARD_DMAError().

static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Wrap up transmission in non-blocking mode.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 2253 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_DISABLE_IT, SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_READY, HAL_SMARTCARD_TxCpltCallback(), SMARTCARD_HandleTypeDef::Init, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_InitTypeDef::Mode, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_MODE_TX_RX, and SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication.

Referenced by HAL_SMARTCARD_IRQHandler().

static void SMARTCARD_EndTxTransfer ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1961 of file stm32h7xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_READY, and SMARTCARD_HandleTypeDef::Instance.

Referenced by HAL_SMARTCARD_IRQHandler(), and SMARTCARD_DMAError().

static HAL_StatusTypeDef SMARTCARD_Receive_IT ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Receive an amount of data in non-blocking mode.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module. Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
Return values:
HAL status

Definition at line 2291 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_SEND_REQ, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pRxBuffPtr, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, and SMARTCARD_RXDATA_FLUSH_REQUEST.

Referenced by HAL_SMARTCARD_IRQHandler().

static HAL_StatusTypeDef SMARTCARD_SetConfig ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Configure the SMARTCARD associated USART peripheral.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 1690 of file stm32h7xx_hal_smartcard.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_HSI_DIVIDER, assert_param, SMARTCARD_InitTypeDef::AutoRetryCount, SMARTCARD_InitTypeDef::BaudRate, SMARTCARD_InitTypeDef::BlockLength, SMARTCARD_InitTypeDef::CLKLastBit, SMARTCARD_InitTypeDef::CLKPhase, SMARTCARD_InitTypeDef::CLKPolarity, CSI_VALUE, SMARTCARD_InitTypeDef::FIFOMode, SMARTCARD_InitTypeDef::GuardTime, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCCEx_GetPLL2ClockFreq(), HAL_RCCEx_GetPLL3ClockFreq(), HSI_VALUE, SMARTCARD_HandleTypeDef::Init, SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_AUTORETRY_COUNT, IS_SMARTCARD_BAUDRATE, IS_SMARTCARD_FIFO_MODE_STATE, IS_SMARTCARD_LASTBIT, IS_SMARTCARD_MODE, IS_SMARTCARD_NACK, IS_SMARTCARD_ONE_BIT_SAMPLE, IS_SMARTCARD_PARITY, IS_SMARTCARD_PHASE, IS_SMARTCARD_POLARITY, IS_SMARTCARD_RXFIFO_THRESHOLD, IS_SMARTCARD_STOPBITS, IS_SMARTCARD_TIMEOUT, IS_SMARTCARD_TIMEOUT_VALUE, IS_SMARTCARD_TXFIFO_THRESHOLD, IS_SMARTCARD_WORD_LENGTH, LSE_VALUE, SMARTCARD_InitTypeDef::Mode, SMARTCARD_InitTypeDef::NACKEnable, SMARTCARD_InitTypeDef::OneBitSampling, SMARTCARD_InitTypeDef::Parity, PLL2_ClocksTypeDef::PLL2_Q_Frequency, PLL3_ClocksTypeDef::PLL3_Q_Frequency, SMARTCARD_InitTypeDef::Prescaler, RCC_FLAG_HSIDIV, SMARTCARD_InitTypeDef::RXFIFOThreshold, SMARTCARD_CLOCKSOURCE_CSI, SMARTCARD_CLOCKSOURCE_D2PCLK1, SMARTCARD_CLOCKSOURCE_D2PCLK2, SMARTCARD_CLOCKSOURCE_HSI, SMARTCARD_CLOCKSOURCE_LSE, SMARTCARD_CLOCKSOURCE_PLL2Q, SMARTCARD_CLOCKSOURCE_PLL3Q, SMARTCARD_CLOCKSOURCE_UNDEFINED, SMARTCARD_CR3_SCARCNT_LSB_POS, SMARTCARD_GETCLOCKSOURCE, SMARTCARD_GTPR_GT_LSB_POS, SMARTCARD_RTOR_BLEN_LSB_POS, SMARTCARD_TIMEOUT_ENABLE, SMARTCARD_InitTypeDef::StopBits, SMARTCARD_InitTypeDef::TimeOutEnable, SMARTCARD_InitTypeDef::TimeOutValue, SMARTCARD_InitTypeDef::TXFIFOThreshold, UART_FIFOMODE_ENABLE, USART_CR1_FIELDS, USART_CR2_FIELDS, USART_CR3_FIELDS, and SMARTCARD_InitTypeDef::WordLength.

Referenced by HAL_SMARTCARD_Init().

static HAL_StatusTypeDef SMARTCARD_Transmit_IT ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Send an amount of data in non-blocking mode.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module. Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
Return values:
HAL status

Definition at line 2218 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY_TX, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_IRQHandler().

static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle SMARTCARD Communication Timeout.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Flag | Specifies the SMARTCARD flag to check.
Status | The new Flag status (SET or RESET).
Tickstart | Tick start value
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 1928 of file stm32h7xx_hal_smartcard.c.

References __HAL_SMARTCARD_GET_FLAG, SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_HandleTypeDef::RxState.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Transmit(), and SMARTCARD_CheckIdleState().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD Exported Types

Data Structures | Enumerations
SMARTCARD Exported Types
SMARTCARD

Data Structures

struct | SMARTCARD_InitTypeDef
SMARTCARD Init Structure definition. More...
struct | SMARTCARD_AdvFeatureInitTypeDef
SMARTCARD advanced features initalization structure definition. More...
struct | SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition. More...

Enumerations

enum HAL_SMARTCARD_StateTypeDef {
HAL_SMARTCARD_STATE_RESET = 0x00U, HAL_SMARTCARD_STATE_READY = 0x20U, HAL_SMARTCARD_STATE_BUSY = 0x24U, HAL_SMARTCARD_STATE_BUSY_TX = 0x21U,
HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, HAL_SMARTCARD_STATE_ERROR = 0xE0U
}
HAL SMARTCARD State structures definition. More...
enum HAL_SMARTCARD_ErrorTypeDef {
HAL_SMARTCARD_ERROR_NONE = 0x00, HAL_SMARTCARD_ERROR_PE = 0x01, HAL_SMARTCARD_ERROR_NE = 0x02, HAL_SMARTCARD_ERROR_FE = 0x04,
HAL_SMARTCARD_ERROR_ORE = 0x08, HAL_SMARTCARD_ERROR_DMA = 0x10, HAL_SMARTCARD_ERROR_UDR = 0x11, HAL_SMARTCARD_ERROR_RTO = 0x20
}
HAL SMARTCARD Error Code structure definition. More...
enum SMARTCARD_ClockSourceTypeDef {
SMARTCARD_CLOCKSOURCE_D2PCLK1 = 0x00, SMARTCARD_CLOCKSOURCE_D2PCLK2 = 0x01, SMARTCARD_CLOCKSOURCE_D3PCLK1 = 0x02, SMARTCARD_CLOCKSOURCE_PLL2Q = 0x04,
SMARTCARD_CLOCKSOURCE_HSI = 0x08, SMARTCARD_CLOCKSOURCE_CSI = 0x10, SMARTCARD_CLOCKSOURCE_LSE = 0x20, SMARTCARD_CLOCKSOURCE_PLL3Q = 0x40,
SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x80
}
SMARTCARD clock sources. More...

Enumeration Type Documentation

enum HAL_SMARTCARD_ErrorTypeDef

HAL SMARTCARD Error Code structure definition.

Enumerator:
HAL_SMARTCARD_ERROR_NONE

No error

HAL_SMARTCARD_ERROR_PE

Parity error

HAL_SMARTCARD_ERROR_NE

Noise error

HAL_SMARTCARD_ERROR_FE

frame error

HAL_SMARTCARD_ERROR_ORE

Overrun error

HAL_SMARTCARD_ERROR_DMA

DMA transfer error

HAL_SMARTCARD_ERROR_UDR

SPI UnderRun error

HAL_SMARTCARD_ERROR_RTO

Receiver TimeOut error

Definition at line 233 of file stm32h7xx_hal_smartcard.h.

enum HAL_SMARTCARD_StateTypeDef

HAL SMARTCARD State structures definition.

Note:
HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
  • gState contains SMARTCARD state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (IP busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.
Enumerator:
HAL_SMARTCARD_STATE_RESET

Peripheral is not initialized Value is allowed for gState and RxState

HAL_SMARTCARD_STATE_READY

Peripheral Initialized and ready for use Value is allowed for gState and RxState

HAL_SMARTCARD_STATE_BUSY

an internal process is ongoing Value is allowed for gState only

HAL_SMARTCARD_STATE_BUSY_TX

Data Transmission process is ongoing Value is allowed for gState only

HAL_SMARTCARD_STATE_BUSY_RX

Data Reception process is ongoing Value is allowed for RxState only

HAL_SMARTCARD_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

HAL_SMARTCARD_STATE_TIMEOUT

Timeout state Value is allowed for gState only

HAL_SMARTCARD_STATE_ERROR

Error Value is allowed for gState only

Definition at line 209 of file stm32h7xx_hal_smartcard.h.

enum SMARTCARD_ClockSourceTypeDef

SMARTCARD clock sources.

Enumerator:
SMARTCARD_CLOCKSOURCE_D2PCLK1

Domain2 PCLK1 clock source

SMARTCARD_CLOCKSOURCE_D2PCLK2

Domain2 PCLK2 clock source

SMARTCARD_CLOCKSOURCE_D3PCLK1

Domain3 PCLK1 clock source

SMARTCARD_CLOCKSOURCE_PLL2Q

PLL2Q clock source

SMARTCARD_CLOCKSOURCE_HSI

HSI clock source

SMARTCARD_CLOCKSOURCE_CSI

CSI clock source

SMARTCARD_CLOCKSOURCE_LSE

LSE clock source

SMARTCARD_CLOCKSOURCE_PLL3Q

PCLK2 clock source

SMARTCARD_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 288 of file stm32h7xx_hal_smartcard.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_InitTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD Init Structure definition. More...

#include <stm32h7xx_hal_smartcard.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint16_t | Parity
uint16_t | Mode
uint16_t | CLKPolarity
uint16_t | CLKPhase
uint16_t | CLKLastBit
uint16_t | OneBitSampling
uint8_t | Prescaler
uint8_t | GuardTime
uint16_t | NACKEnable
uint32_t | TimeOutEnable
uint32_t | TimeOutValue
uint8_t | BlockLength
uint8_t | AutoRetryCount
uint32_t | FIFOMode
uint32_t | TXFIFOThreshold
uint32_t | RXFIFOThreshold

Detailed Description

SMARTCARD Init Structure definition.

Definition at line 65 of file stm32h7xx_hal_smartcard.h.

Field Documentation

uint8_t SMARTCARD_InitTypeDef::AutoRetryCount

Specifies the SmartCard auto-retry count (number of retries in receive and transmit mode). When set to 0, retransmission is disabled. Otherwise, its maximum value is 7 (before signalling an error)

Definition at line 118 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::BaudRate

Configures the SmartCard communication baud rate. The baud rate register is computed using the following formula: Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate)))

Definition at line 67 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint8_t SMARTCARD_InitTypeDef::BlockLength

Specifies the SmartCard Block Length in T=1 Reception mode. This parameter can be any value from 0x0 to 0xFF

Definition at line 115 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::CLKLastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of SMARTCARD Last Bit

Definition at line 92 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::CLKPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of SMARTCARD Clock Phase

Definition at line 89 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::CLKPolarity

Specifies the steady state of the serial clock. This parameter can be a value of SMARTCARD Clock Polarity

Definition at line 86 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::FIFOMode

Specifies if the FIFO mode will be used. This parameter can be a value of SMARTCARD FIFO mode

Definition at line 123 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint8_t SMARTCARD_InitTypeDef::GuardTime

Specifies the SmartCard Guard Time applied after stop bits.

Definition at line 102 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of SMARTCARD Transfer Mode

Definition at line 83 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::NACKEnable

Specifies whether the SmartCard NACK transmission is enabled in case of parity error. This parameter can be a value of SMARTCARD NACK Enable

Definition at line 104 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::OneBitSampling

Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of SMARTCARD One Bit Sampling Method.

Definition at line 96 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of SMARTCARD Parity

Note:
The parity is enabled by default (PCE is forced to 1). Since the WordLength is forced to 8 bits + parity, M is forced to 1 and the parity bit is the 9th bit.

Definition at line 77 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint8_t SMARTCARD_InitTypeDef::Prescaler

Specifies the SmartCard Prescaler.

Definition at line 100 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::RXFIFOThreshold

Specifies the RXFIFO threshold level. This parameter can be a value of SMARTCARD RXFIFO threshold level

Definition at line 129 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::StopBits

Specifies the number of stop bits. This parameter can be a value of SMARTCARD Number of Stop Bits.

Definition at line 74 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::TimeOutEnable

Specifies whether the receiver timeout is enabled. This parameter can be a value of SMARTCARD Timeout Enable

Definition at line 108 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::TimeOutValue

Specifies the receiver time out value in number of baud blocks: it is used to implement the Character Wait Time (CWT) and Block Wait Time (BWT). It is coded over 24 bits.

Definition at line 111 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_TimeOut_Config(), and SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::TXFIFOThreshold

Specifies the TXFIFO threshold level. This parameter can be a value of SMARTCARD TXFIFO threshold level

Definition at line 126 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter SMARTCARD Word Length can only be set to 9 (8 data + 1 parity bits).

Definition at line 71 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_smartcard.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD_AdvFeatureInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_AdvFeatureInitTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD advanced features initalization structure definition. More...

#include <stm32h7xx_hal_smartcard.h>

Data Fields

uint32_t | AdvFeatureInit
uint32_t | TxPinLevelInvert
uint32_t | RxPinLevelInvert
uint32_t | DataInvert
uint32_t | Swap
uint32_t | OverrunDisable
uint32_t | DMADisableonRxError
uint32_t | MSBFirst
uint16_t | TxCompletionIndication

Detailed Description

SMARTCARD advanced features initalization structure definition.

Definition at line 137 of file stm32h7xx_hal_smartcard.h.

Field Documentation

uint32_t SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit

Specifies which advanced SMARTCARD features is initialized. Several advanced features may be initialized at the same time. This parameter can be a value of SMARTCARD advanced feature initialization type

Definition at line 139 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), and SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::DataInvert

Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). This parameter can be a value of SMARTCARD advanced feature Binary Data inversion

Definition at line 149 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::DMADisableonRxError

Specifies whether the DMA is disabled in case of reception error. This parameter can be a value of SMARTCARD advanced feature DMA Disable on Rx Error

Definition at line 159 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::MSBFirst

Specifies whether MSB is sent first on UART line. This parameter can be a value of SMARTCARD advanced feature MSB first

Definition at line 162 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::OverrunDisable

Specifies whether the reception overrun detection is disabled. This parameter can be a value of SMARTCARD advanced feature Overrun Disable

Definition at line 156 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::RxPinLevelInvert

Specifies whether the RX pin active level is inverted. This parameter can be a value of SMARTCARD advanced feature RX pin active level inversion

Definition at line 146 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::Swap

Specifies whether TX and RX pins are swapped. This parameter can be a value of SMARTCARD advanced feature RX TX pins swap

Definition at line 153 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint16_t SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication

Specifies which transmission completion indication is used: before (when relevant flag is available) or once guard time period has elapsed. This parameter can be a value of SMARTCARD Transmission Completion Indication.

Definition at line 165 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_Transmit_IT().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::TxPinLevelInvert

Specifies whether the TX pin active level is inverted. This parameter can be a value of SMARTCARD advanced feature TX pin active level inversion

Definition at line 143 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_smartcard.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_HandleTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD handle Structure definition. More...

#include <stm32h7xx_hal_smartcard.h>

Data Fields

USART_TypeDef * | Instance
SMARTCARD_InitTypeDef Init
SMARTCARD_AdvFeatureInitTypeDef AdvancedInit
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SMARTCARD_StateTypeDef | gState
__IO HAL_SMARTCARD_StateTypeDef | RxState
uint32_t | ErrorCode

Detailed Description

SMARTCARD handle Structure definition.

Definition at line 248 of file stm32h7xx_hal_smartcard.h.

Field Documentation

SMARTCARD_AdvFeatureInitTypeDef SMARTCARD_HandleTypeDef::AdvancedInit

SmartCard advanced features initialization parameters

Definition at line 254 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_Transmit_IT().

uint32_t SMARTCARD_HandleTypeDef::ErrorCode

SmartCard Error code

Definition at line 281 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetError(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

__IO HAL_SMARTCARD_StateTypeDef SMARTCARD_HandleTypeDef::gState

SmartCard state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_SMARTCARD_StateTypeDef

Definition at line 274 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetState(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_Receive_IT(), SMARTCARD_Transmit_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* SMARTCARD_HandleTypeDef::hdmarx

SmartCard Rx DMA Handle parameters

Definition at line 270 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_DMA(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

DMA_HandleTypeDef* SMARTCARD_HandleTypeDef::hdmatx

SmartCard Tx DMA Handle parameters

Definition at line 268 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit_DMA(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

SMARTCARD_InitTypeDef SMARTCARD_HandleTypeDef::Init

SmartCard communication parameters

Definition at line 252 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARDEx_TimeOut_Config(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_SetConfig().

USART_TypeDef* SMARTCARD_HandleTypeDef::Instance

USART registers base address

Definition at line 250 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARDEx_BlockLength_Config(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), HAL_SMARTCARDEx_TimeOut_Config(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_Receive_IT(), SMARTCARD_SetConfig(), SMARTCARD_Transmit_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

HAL_LockTypeDef SMARTCARD_HandleTypeDef::Lock

Locking object

Definition at line 272 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init().

uint8_t* SMARTCARD_HandleTypeDef::pRxBuffPtr

Pointer to SmartCard Rx transfer Buffer

Definition at line 262 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), and SMARTCARD_Receive_IT().

uint8_t* SMARTCARD_HandleTypeDef::pTxBuffPtr

Pointer to SmartCard Tx transfer Buffer

Definition at line 256 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), and SMARTCARD_Transmit_IT().

__IO HAL_SMARTCARD_StateTypeDef SMARTCARD_HandleTypeDef::RxState

SmartCard state information related to Rx operations. This parameter can be a value of HAL_SMARTCARD_StateTypeDef

Definition at line 278 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetState(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_Receive_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

__IO uint16_t SMARTCARD_HandleTypeDef::RxXferCount

SmartCard Rx Transfer Counter

Definition at line 266 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_Receive_IT().

uint16_t SMARTCARD_HandleTypeDef::RxXferSize

SmartCard Rx Transfer size

Definition at line 264 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), and HAL_SMARTCARD_Receive_IT().

__IO uint16_t SMARTCARD_HandleTypeDef::TxXferCount

SmartCard Tx Transfer Counter

Definition at line 260 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATransmitCplt(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), and SMARTCARD_Transmit_IT().

uint16_t SMARTCARD_HandleTypeDef::TxXferSize

SmartCard Tx Transfer size

Definition at line 258 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), and HAL_SMARTCARD_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_smartcard.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD Word Length

Defines
SMARTCARD Word Length
SMARTCARD Exported Constants

Defines

#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

Define Documentation

#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

SMARTCARD frame length

Definition at line 313 of file stm32h7xx_hal_smartcard.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD Number of Stop Bits

Defines
SMARTCARD Number of Stop Bits
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define | SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))

Define Documentation

#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)

SMARTCARD frame with 0.5 stop bit

Definition at line 321 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))

SMARTCARD frame with 1.5 stop bits

Definition at line 322 of file stm32h7xx_hal_smartcard.h.

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STM32H753xx HAL User Manual: SMARTCARD Parity

Defines
SMARTCARD Parity
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

SMARTCARD frame even parity

Definition at line 330 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

SMARTCARD frame odd parity

Definition at line 331 of file stm32h7xx_hal_smartcard.h.

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STM32H753xx HAL User Manual: SMARTCARD Transfer Mode

Defines
SMARTCARD Transfer Mode
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
#define | SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
#define | SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)

SMARTCARD RX mode

Definition at line 339 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)

SMARTCARD TX mode

Definition at line 340 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

SMARTCARD RX and TX mode

Definition at line 341 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), and SMARTCARD_EndTransmit_IT().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD Clock Polarity

Defines
SMARTCARD Clock Polarity
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000)
#define | SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

Define Documentation

#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

SMARTCARD frame high polarity

Definition at line 350 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000)

SMARTCARD frame low polarity

Definition at line 349 of file stm32h7xx_hal_smartcard.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD Clock Phase

Defines
SMARTCARD Clock Phase
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000)
#define | SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

Define Documentation

#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000)

SMARTCARD frame phase on first clock transition

Definition at line 358 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

SMARTCARD frame phase on second clock transition

Definition at line 359 of file stm32h7xx_hal_smartcard.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD Last Bit

Defines
SMARTCARD Last Bit
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

Define Documentation

#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000)

SMARTCARD frame last data bit clock pulse not output to SCLK pin

Definition at line 367 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

SMARTCARD frame last data bit clock pulse output to SCLK pin

Definition at line 368 of file stm32h7xx_hal_smartcard.h.

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STM32H753xx HAL User Manual: SMARTCARD FIFO mode

Defines
SMARTCARD FIFO mode
SMARTCARD Exported Constants

SMARTCARD FIFO mode. More...

Defines

#define | SMARTCARD_FIFOMODE_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_FIFOMODE_ENABLE ((uint32_t)USART_CR1_FIFOEN)

Detailed Description

SMARTCARD FIFO mode.

Define Documentation

#define SMARTCARD_FIFOMODE_DISABLE ((uint32_t)0x00000000)

FIFO mode disable

Definition at line 377 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_FIFOMODE_ENABLE ((uint32_t)USART_CR1_FIFOEN)

FIFO mode enable

Definition at line 378 of file stm32h7xx_hal_smartcard.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD TXFIFO threshold level

Defines
SMARTCARD TXFIFO threshold level
SMARTCARD Exported Constants

SMARTCARD TXFIFO level. More...

Defines

#define | SMARTCARD_TXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000)
#define | SMARTCARD_TXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_TXFTCFG_0)
#define | SMARTCARD_TXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_TXFTCFG_1)
#define | SMARTCARD_TXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1))
#define | SMARTCARD_TXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_TXFTCFG_2)
#define | SMARTCARD_TXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0))

Detailed Description

SMARTCARD TXFIFO level.

Define Documentation

#define SMARTCARD_TXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_TXFTCFG_1)

TXFIFO threshold half full configuration

Definition at line 389 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_TXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_TXFTCFG_0)

TXFIFO threshold 1 quart full configuration

Definition at line 388 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_TXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000)

TXFIFO threshold 1 eighth full configuration

Definition at line 387 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_TXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1))

TXFIFO threshold 3 quarts full configuration

Definition at line 390 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_TXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_TXFTCFG_2)

TXFIFO threshold 7 eighth full configuration

Definition at line 391 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_TXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0))

TXFIFO becomes empty

Definition at line 392 of file stm32h7xx_hal_smartcard.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD RXFIFO threshold level

Defines
SMARTCARD RXFIFO threshold level
SMARTCARD Exported Constants

SMARTCARD RXFIFO level. More...

Defines

#define | SMARTCARD_RXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000)
#define | SMARTCARD_RXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_RXFTCFG_0)
#define | SMARTCARD_RXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_RXFTCFG_1)
#define | SMARTCARD_RXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1))
#define | SMARTCARD_RXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_RXFTCFG_2)
#define | SMARTCARD_RXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0))

Detailed Description

SMARTCARD RXFIFO level.

Define Documentation

#define SMARTCARD_RXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_RXFTCFG_1)

RXFIFO threshold half full configuration

Definition at line 403 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_RXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_RXFTCFG_0)

RXFIFO threshold 1 quart full configuration

Definition at line 402 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_RXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000)

RXFIFO threshold 1 eighth full configuration

Definition at line 401 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_RXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1))

RXFIFO threshold 3 quarts full configuration

Definition at line 404 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_RXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_RXFTCFG_2)

RXFIFO threshold 7 eighth full configuration

Definition at line 405 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_RXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0))

RXFIFO becomes Full

Definition at line 406 of file stm32h7xx_hal_smartcard.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD One Bit Sampling Method

Defines
SMARTCARD One Bit Sampling Method
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

Define Documentation

#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)

SMARTCARD frame one-bit sample disabled

Definition at line 414 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

SMARTCARD frame one-bit sample enabled

Definition at line 415 of file stm32h7xx_hal_smartcard.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD NACK Enable

Defines
SMARTCARD NACK Enable
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define | SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000)

SMARTCARD NACK transmission enabled

Definition at line 425 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)

SMARTCARD NACK transmission disabled

Definition at line 424 of file stm32h7xx_hal_smartcard.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD Timeout Enable

Defines
SMARTCARD Timeout Enable
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)

Define Documentation

#define SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000)

SMARTCARD receiver timeout disabled

Definition at line 433 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)

SMARTCARD receiver timeout enabled

Definition at line 434 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

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STM32H753xx HAL User Manual: SMARTCARD advanced feature TX pin active level inversion

Defines
SMARTCARD advanced feature TX pin active level inversion
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)

Define Documentation

#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)

TX pin active level inversion disable

Definition at line 442 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)

TX pin active level inversion enable

Definition at line 443 of file stm32h7xx_hal_smartcard.h.

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STM32H753xx HAL User Manual: SMARTCARD advanced feature RX pin active level inversion

Defines
SMARTCARD advanced feature RX pin active level inversion
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)

Define Documentation

#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)

RX pin active level inversion disable

Definition at line 451 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)

RX pin active level inversion enable

Definition at line 452 of file stm32h7xx_hal_smartcard.h.

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STM32H753xx HAL User Manual: SMARTCARD advanced feature Binary Data inversion

Defines
SMARTCARD advanced feature Binary Data inversion
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)

Define Documentation

#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)

Binary data inversion disable

Definition at line 460 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)

Binary data inversion enable

Definition at line 461 of file stm32h7xx_hal_smartcard.h.

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STM32H753xx HAL User Manual: SMARTCARD advanced feature RX TX pins swap

Defines
SMARTCARD advanced feature RX TX pins swap
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)

Define Documentation

#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)

TX/RX pins swap disable

Definition at line 469 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)

TX/RX pins swap enable

Definition at line 470 of file stm32h7xx_hal_smartcard.h.

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STM32H753xx HAL User Manual: SMARTCARD advanced feature Overrun Disable

Defines
SMARTCARD advanced feature Overrun Disable
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)

Define Documentation

#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)

RX overrun disable

Definition at line 479 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)

RX overrun enable

Definition at line 478 of file stm32h7xx_hal_smartcard.h.

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STM32H753xx HAL User Manual: SMARTCARD advanced feature DMA Disable on Rx Error

Defines
SMARTCARD advanced feature DMA Disable on Rx Error
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)

Define Documentation

#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)

DMA disable on Reception Error

Definition at line 488 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)

DMA enable on Reception Error

Definition at line 487 of file stm32h7xx_hal_smartcard.h.

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STM32H753xx HAL User Manual: SMARTCARD advanced feature MSB first

Defines
SMARTCARD advanced feature MSB first
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)

Define Documentation

#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)

Most significant bit sent/received first disable

Definition at line 496 of file stm32h7xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)

Most significant bit sent/received first enable

Definition at line 497 of file stm32h7xx_hal_smartcard.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD Request Parameters

Defines
SMARTCARD Request Parameters
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ)
#define | SMARTCARD_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ)

Define Documentation

#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ)

Receive data flush request

Definition at line 505 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), and SMARTCARD_Receive_IT().

#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ)

Transmit data flush request

Definition at line 506 of file stm32h7xx_hal_smartcard.h.

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STM32H753xx HAL User Manual: SMARTCARD auto retry counter LSB position in CR3 register

Defines
SMARTCARD auto retry counter LSB position in CR3 register
SMARTCARD Exported Constants

Defines

#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17)

Define Documentation

#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17)

SMARTCARD auto retry counter LSB position in CR3 register

Definition at line 514 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD guard time value LSB position in GTPR register

Defines
SMARTCARD guard time value LSB position in GTPR register
SMARTCARD Exported Constants

Defines

#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8)

Define Documentation

#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8)

SMARTCARD guard time value LSB position in GTPR register

Definition at line 522 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD block length LSB position in RTOR register

Defines
SMARTCARD block length LSB position in RTOR register
SMARTCARD Exported Constants

Defines

#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24)

Define Documentation

#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24)

SMARTCARD block length LSB position in RTOR register

Definition at line 530 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_BlockLength_Config(), and SMARTCARD_SetConfig().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD interruptions flags mask

Defines
SMARTCARD interruptions flags mask
SMARTCARD Exported Constants

Defines

#define SMARTCARD_IT_MASK ((uint16_t)0x001F)

Define Documentation

#define SMARTCARD_IT_MASK ((uint16_t)0x001F)

SMARTCARD interruptions flags mask

Definition at line 538 of file stm32h7xx_hal_smartcard.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD Exported Macros

Defines
SMARTCARD Exported Macros
SMARTCARD

Defines

#define | __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)
Reset SMARTCARD handle state.
#define | __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)
Flush the Smartcard Data registers.
#define | __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified SMARTCARD pending flag.
#define | __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
Clear the SMARTCARD PE pending flag.
#define | __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
Clear the SMARTCARD FE pending flag.
#define | __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
Clear the SMARTCARD NE pending flag.
#define | __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
Clear the SMARTCARD ORE pending flag.
#define | __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
Clear the SMARTCARD IDLE pending flag.
#define | __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified Smartcard flag is set or not.
#define | __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
Check whether the specified SmartCard interrupt has occurred or not.
#define | __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified SmartCard interrupt source is enabled or not.
#define | __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
#define | __HAL_SMARTCARD_CLEAR_TXFECF(__HANDLE__) __HAL_SMARTCARD_CLEAR_IT((__HANDLE__), SMARTCARD_CLEAR_TXFECF)
Clear the SMARTCARD TX FIFO empty clear flag.
#define | __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific SMARTCARD request flag.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable the USART associated to the SMARTCARD Handle.

Define Documentation

#define __HAL_SMARTCARD_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)

Clear the SMARTCARD FE pending flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 599 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified SMARTCARD pending flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
__FLAG__,: specifies the flag to check. This parameter can be any combination of the following values:
  • SMARTCARD_CLEAR_PEF Parity error clear flag
  • SMARTCARD_CLEAR_FEF Framing error clear flag
  • SMARTCARD_CLEAR_NEF Noise detected clear flag
  • SMARTCARD_CLEAR_OREF OverRun error clear flag
  • SMARTCARD_CLEAR_IDLEF Idle line detected clear flag
  • SMARTCARD_CLEAR_TCF Transmission complete clear flag
  • SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag
  • SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
  • SMARTCARD_CLEAR_EOBF End of block clear flag
Return values:
None

Definition at line 586 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_DMATxOnlyAbortCallback().

#define __HAL_SMARTCARD_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)

Clear the SMARTCARD IDLE pending flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 617 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
__IT_CLEAR__,: specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt. This parameter can be one of the following values:
  • SMARTCARD_CLEAR_PEF Parity error clear flag
  • SMARTCARD_CLEAR_FEF Framing error clear flag
  • SMARTCARD_CLEAR_NEF Noise detected clear flag
  • SMARTCARD_CLEAR_OREF OverRun error clear flag
  • SMARTCARD_CLEAR_IDLEF Idle line detection clear flag
  • SMARTCARD_CLEAR_TCF Transmission complete clear flag
  • SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
  • SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
  • SMARTCARD_CLEAR_EOBF End of block clear flag
Return values:
None

Definition at line 736 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)

Clear the SMARTCARD NE pending flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 605 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)

Clear the SMARTCARD ORE pending flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 611 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)

Clear the SMARTCARD PE pending flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 592 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_TXFECF ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_IT((__HANDLE__), SMARTCARD_CLEAR_TXFECF)

Clear the SMARTCARD TX FIFO empty clear flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 742 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable the USART associated to the SMARTCARD Handle.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 777 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))

Disable the specified SmartCard interrupt.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
__INTERRUPT__,: specifies the SMARTCARD interrupt to disable. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
Return values:
None

Definition at line 676 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_EndTransmit_IT().

#define __HAL_SMARTCARD_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable the USART associated to the SMARTCARD Handle.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 771 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))

Enable the specified SmartCard interrupt.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
__INTERRUPT__,: specifies the SMARTCARD interrupt to enable. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
Return values:
None

Definition at line 657 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_DMATransmitCplt(), and SMARTCARD_Transmit_IT().

#define __HAL_SMARTCARD_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                                                                              \
      SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
      SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
      } while(0)

Flush the Smartcard Data registers.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 565 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified Smartcard flag is set or not.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag
  • SMARTCARD_FLAG_REACK Receive enable acknowledge flag
  • SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
  • SMARTCARD_FLAG_BUSY Busy flag
  • SMARTCARD_FLAG_EOBF End of block flag
  • SMARTCARD_FLAG_RTOF Receiver timeout flag
  • SMARTCARD_FLAG_TXE Transmit data register empty flag
  • SMARTCARD_FLAG_TC Transmission complete flag
  • SMARTCARD_FLAG_RXNE Receive data register not empty flag
  • SMARTCARD_FLAG_IDLE Idle line detection flag
  • SMARTCARD_FLAG_ORE Overrun error flag
  • SMARTCARD_FLAG_NE Noise error flag
  • SMARTCARD_FLAG_FE Framing error flag
  • SMARTCARD_FLAG_PE Parity error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 639 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_WaitOnFlagUntilTimeout().

#define __HAL_SMARTCARD_GET_IT | ( | __HANDLE__,
 |  | __IT__
 | ) | ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))

Check whether the specified SmartCard interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
__IT__,: specifies the SMARTCARD interrupt to check. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_ORE Overrun error interrupt
  • SMARTCARD_IT_NE Noise error interrupt
  • SMARTCARD_IT_FE Framing error interrupt
  • SMARTCARD_IT_PE Parity error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 698 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1 : \
                                                           (((((uint8_t)(__IT__)) >> 5U) == 2)? (__HANDLE__)->Instance->CR2 : \
                                                           (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))

Check whether the specified SmartCard interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
__IT__,: specifies the SMARTCARD interrupt source to check. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_ERR Framing, overrun or noise error interrupt
  • SMARTCARD_IT_PE Parity error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 715 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

Disable the SMARTCARD one bit sample method.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 765 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the SMARTCARD one bit sample method.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 759 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                       \
                                                           (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
                                                           (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
                                                          } while(0)

Reset SMARTCARD handle state.

Parameters:
__HANDLE__,: SMARTCARD handle.
Return values:
None

Definition at line 556 of file stm32h7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific SMARTCARD request flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
__REQ__,: specifies the request flag to set This parameter can be one of the following values:
  • SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
  • SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 753 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_Receive_IT().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD Private Macros

Defines
SMARTCARD Private Macros
SMARTCARD

Defines

#define | IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
Check the Baud rate range.
#define | IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)
Check the block length range.
#define | IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF)
Check the receiver timeout value.
#define | IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7)
Check the SMARTCARD autoretry counter value.
#define | IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
Ensure that SMARTCARD frame length is valid.
#define | IS_SMARTCARD_STOPBITS(__STOPBITS__)
Ensure that SMARTCARD frame number of stop bits is valid.
#define | IS_SMARTCARD_PARITY(__PARITY__)
Ensure that SMARTCARD frame parity is valid.
#define | IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3) == 0x00) && ((__MODE__) != (uint16_t)0x00))
Ensure that SMARTCARD communication mode is valid.
#define | IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
Ensure that SMARTCARD frame polarity is valid.
#define | IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
Ensure that SMARTCARD frame phase is valid.
#define | IS_SMARTCARD_LASTBIT(__LASTBIT__)
Ensure that SMARTCARD frame last bit clock pulse setting is valid.
#define | IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that SMARTCARD frame sampling is valid.
#define | IS_SMARTCARD_NACK(__NACK__)
Ensure that SMARTCARD NACK transmission setting is valid.
#define | IS_SMARTCARD_TIMEOUT(__TIMEOUT__)
Ensure that SMARTCARD receiver timeout setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_INIT(__INIT__)
Ensure that SMARTCARD advanced features initialization is valid.
#define | IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__)
Ensure that SMARTCARD frame TX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__)
Ensure that SMARTCARD frame RX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that SMARTCARD frame data inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__)
Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
#define | IS_SMARTCARD_OVERRUN(__OVERRUN__)
Ensure that SMARTCARD frame overrun setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that SMARTCARD frame MSB first setting is valid.
#define | IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__)
Ensure that SMARTCARD request parameter is valid.
#define | IS_SMARTCARD_FIFO_MODE_STATE(__STATE__)
Ensure that SMARTCARD FIFO mode is valid.
#define | IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that SMARTCARD TXFIFO threshold level is valid.
#define | IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that SMARTCARD RXFIFO threshold level is valid.

Define Documentation

#define IS_SMARTCARD_ADVFEATURE_DATAINV ( __DATAINV__ )
Value:
(((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
                                                      ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))

Ensure that SMARTCARD frame data inversion setting is valid.

Parameters:
__DATAINV__,: SMARTCARD frame data inversion setting.
Return values:
SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)

Definition at line 928 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR ( __DMA__ )
Value:
(((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
                                                       ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))

Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.

Parameters:
__DMA__,: SMARTCARD DMA enabling or disabling on error setting.
Return values:
SET (__DMA__ is valid) or RESET (__DMA__ is invalid)

Definition at line 952 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_INIT ( __INIT__ )
Value:
((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \
                                                               SMARTCARD_ADVFEATURE_TXINVERT_INIT          | \
                                                               SMARTCARD_ADVFEATURE_RXINVERT_INIT          | \
                                                               SMARTCARD_ADVFEATURE_DATAINVERT_INIT        | \
                                                               SMARTCARD_ADVFEATURE_SWAP_INIT              | \
                                                               SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
                                                               SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
                                                               SMARTCARD_ADVFEATURE_MSBFIRST_INIT))

Ensure that SMARTCARD advanced features initialization is valid.

Parameters:
__INIT__,: SMARTCARD advanced features initialization.
Return values:
SET (__INIT__ is valid) or RESET (__INIT__ is invalid)

Definition at line 898 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_MSBFIRST ( __MSBFIRST__ )
Value:
(((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
                                                        ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))

Ensure that SMARTCARD frame MSB first setting is valid.

Parameters:
__MSBFIRST__,: SMARTCARD frame MSB first setting.
Return values:
SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)

Definition at line 960 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_RXINV ( __RXINV__ )
Value:
(((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
                                                  ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))

Ensure that SMARTCARD frame RX inversion setting is valid.

Parameters:
__RXINV__,: SMARTCARD frame RX inversion setting.
Return values:
SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)

Definition at line 920 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_SWAP ( __SWAP__ )
Value:
(((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
                                                ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))

Ensure that SMARTCARD frame RX/TX pins swap setting is valid.

Parameters:
__SWAP__,: SMARTCARD frame RX/TX pins swap setting.
Return values:
SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)

Definition at line 936 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_TXINV ( __TXINV__ )
Value:
(((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
                                                  ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))

Ensure that SMARTCARD frame TX inversion setting is valid.

Parameters:
__TXINV__,: SMARTCARD frame TX inversion setting.
Return values:
SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)

Definition at line 912 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_AUTORETRY_COUNT ( __COUNT__ ) ((__COUNT__) <= 0x7)

Check the SMARTCARD autoretry counter value.

Note:
The maximum number of retransmissions is 0x7.
Parameters:
__COUNT__,: number of retransmissions.
Return values:
Test result (TRUE or FALSE)

Definition at line 815 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 12500001U)

Check the Baud rate range.

Parameters:
__BAUDRATE__,: Baudrate specified by the user. The maximum Baud Rate is derived from the maximum clock on H7 (i.e. 100 MHz) divided by the smallest oversampling used on the SMARTCARD (i.e. 8).
Return values:
Test result (TRUE or FALSE).

Definition at line 794 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_BLOCKLENGTH ( __LENGTH__ ) ((__LENGTH__) <= 0xFF)

Check the block length range.

Note:
The maximum SMARTCARD block length is 0xFF.
Parameters:
__LENGTH__,: block length.
Return values:
Test result (TRUE or FALSE)

Definition at line 801 of file stm32h7xx_hal_smartcard.h.

#define IS_SMARTCARD_FIFO_MODE_STATE ( __STATE__ )
Value:
(((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
                                                 ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))

Ensure that SMARTCARD FIFO mode is valid.

Parameters:
__STATE__,: SMARTCARD FIFO mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 976 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_LASTBIT ( __LASTBIT__ )
Value:
(((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
                                           ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))

Ensure that SMARTCARD frame last bit clock pulse setting is valid.

Parameters:
__LASTBIT__,: SMARTCARD frame last bit clock pulse setting.
Return values:
SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)

Definition at line 866 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_MODE ( __MODE__ ) ((((__MODE__) & (uint16_t)0xFFF3) == 0x00) && ((__MODE__) != (uint16_t)0x00))

Ensure that SMARTCARD communication mode is valid.

Parameters:
__MODE__,: SMARTCARD communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 845 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_NACK ( __NACK__ )
Value:
(((__NACK__) == SMARTCARD_NACK_ENABLE) || \
                                     ((__NACK__) == SMARTCARD_NACK_DISABLE))

Ensure that SMARTCARD NACK transmission setting is valid.

Parameters:
__NACK__,: SMARTCARD NACK transmission setting.
Return values:
SET (__NACK__ is valid) or RESET (__NACK__ is invalid)

Definition at line 882 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
                                                 ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))

Ensure that SMARTCARD frame sampling is valid.

Parameters:
__ONEBIT__,: SMARTCARD frame sampling.
Return values:
SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

Definition at line 874 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_OVERRUN ( __OVERRUN__ )
Value:
(((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
                                           ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))

Ensure that SMARTCARD frame overrun setting is valid.

Parameters:
__OVERRUN__,: SMARTCARD frame overrun setting.
Return values:
SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)

Definition at line 944 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
                                         ((__PARITY__) == SMARTCARD_PARITY_ODD))

Ensure that SMARTCARD frame parity is valid.

Parameters:
__PARITY__,: SMARTCARD frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 837 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_PHASE ( __CPHA__ ) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))

Ensure that SMARTCARD frame phase is valid.

Parameters:
__CPHA__,: SMARTCARD frame phase.
Return values:
SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)

Definition at line 859 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_POLARITY ( __CPOL__ ) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))

Ensure that SMARTCARD frame polarity is valid.

Parameters:
__CPOL__,: SMARTCARD frame polarity.
Return values:
SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)

Definition at line 852 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
                                                   ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))

Ensure that SMARTCARD request parameter is valid.

Parameters:
__PARAM__,: SMARTCARD request parameter.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 968 of file stm32h7xx_hal_smartcard.h.

#define IS_SMARTCARD_RXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))

Ensure that SMARTCARD RXFIFO threshold level is valid.

Parameters:
__THRESHOLD__,: SMARTCARD RXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 996 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
                                             ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))

Ensure that SMARTCARD frame number of stop bits is valid.

Parameters:
__STOPBITS__,: SMARTCARD frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 829 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_TIMEOUT ( __TIMEOUT__ )
Value:
(((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
                                           ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))

Ensure that SMARTCARD receiver timeout setting is valid.

Parameters:
__TIMEOUT__,: SMARTCARD receiver timeout setting.
Return values:
SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)

Definition at line 890 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_TIMEOUT_VALUE ( __TIMEOUTVALUE__ ) ((__TIMEOUTVALUE__) <= 0xFFFFFF)

Check the receiver timeout value.

Note:
The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
Parameters:
__TIMEOUTVALUE__,: receiver timeout value.
Return values:
Test result (TRUE or FALSE)

Definition at line 808 of file stm32h7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_TimeOut_Config(), and SMARTCARD_SetConfig().

#define IS_SMARTCARD_TXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))

Ensure that SMARTCARD TXFIFO threshold level is valid.

Parameters:
__THRESHOLD__,: SMARTCARD TXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 984 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_WORD_LENGTH ( __LENGTH__ ) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)

Ensure that SMARTCARD frame length is valid.

Parameters:
__LENGTH__,: SMARTCARD frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 822 of file stm32h7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
SMARTCARD Extended Exported Functions

Extended control functions. More...

Functions

void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the SMARTCARD receiver timeout feature.

Detailed Description

Extended control functions.

  ===============================================================================
                      ##### Peripheral Control functions #####
  ===============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the SMARTCARD.
     (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
     (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
     (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
     (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature

Function Documentation

void HAL_SMARTCARDEx_BlockLength_Config | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t | BlockLength
 | ) |  |

Update on the fly the SMARTCARD block length in RTOR register.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
BlockLength,: SMARTCARD block length (8-bit long at most)
Return values:
None

Definition at line 107 of file stm32h7xx_hal_smartcard_ex.c.

References SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_RTOR_BLEN_LSB_POS.

HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut ( SMARTCARD_HandleTypeDef * hsmartcard )

Disable the SMARTCARD receiver timeout feature.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 164 of file stm32h7xx_hal_smartcard_ex.c.

References SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, and SMARTCARD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut ( SMARTCARD_HandleTypeDef * hsmartcard )

Enable the SMARTCARD receiver timeout feature.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 132 of file stm32h7xx_hal_smartcard_ex.c.

References SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, and SMARTCARD_HandleTypeDef::Instance.

void HAL_SMARTCARDEx_TimeOut_Config | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | TimeOutValue
 | ) |  |

Update on the fly the receiver timeout value in RTOR register.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
TimeOutValue,: receiver timeout value in number of baud blocks. The timeout value must be less or equal to 0x0FFFFFFFF.
Return values:
None

Definition at line 120 of file stm32h7xx_hal_smartcard_ex.c.

References assert_param, SMARTCARD_HandleTypeDef::Init, SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_TIMEOUT_VALUE, and SMARTCARD_InitTypeDef::TimeOutValue.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD Extended Private Macros

Defines
SMARTCARD Extended Private Macros
SMARTCARDEx

Defines

#define | SMARTCARD_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the SMARTCARD clock source.
#define | SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)
Set the Transmission Completion flag.
#define | SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
Return the transmission completion flag.
#define | IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__)
Ensure that SMARTCARD frame transmission completion used flag is valid.

Define Documentation

#define IS_SMARTCARD_TRANSMISSION_COMPLETION ( __TXCOMPLETE__ )
Value:
(((__TXCOMPLETE__) == SMARTCARD_TCBGT) ||\
                                                              ((__TXCOMPLETE__) == SMARTCARD_TC))

Ensure that SMARTCARD frame transmission completion used flag is valid.

Parameters:
__TXCOMPLETE__,: SMARTCARD frame transmission completion used flag.
Return values:
SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)

Definition at line 314 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the SMARTCARD clock source.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
__CLOCKSOURCE__,: output variable.
Return values:
the SMARTCARD clocking source, written in __CLOCKSOURCE__.

Definition at line 185 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_SetConfig().

#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG ( __HANDLE__ ) (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))

Return the transmission completion flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Note:
Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
Return values:
Transmission completion flag

Definition at line 306 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Transmit().

#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING ( __HANDLE__ )
Value:
do {                                                                                                       \
    if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION))        \
    {                                                                                                        \
     (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC;                                       \
    }                                                                                                        \
    else                                                                                                     \
    {                                                                                                        \
      assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
    }                                                                                                        \
  } while(0)

Set the Transmission Completion flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 289 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Init().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD Transmission Completion Indication

Defines
SMARTCARD Transmission Completion Indication
SMARTCARD Extended Exported Constants

Defines

#define | SMARTCARD_TCBGT SMARTCARD_IT_TCBGT
#define | SMARTCARD_TC SMARTCARD_IT_TC

Define Documentation

#define SMARTCARD_TC SMARTCARD_IT_TC

SMARTCARD transmission complete (flag raised when guard time has elapsed)

Definition at line 68 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_TCBGT SMARTCARD_IT_TCBGT

SMARTCARD transmission complete before guard time

Definition at line 67 of file stm32h7xx_hal_smartcard_ex.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD advanced feature initialization type

Defines
SMARTCARD advanced feature initialization type
SMARTCARD Extended Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)
#define | SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)
#define | SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)
#define | SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)
#define | SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)
#define | SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)
#define | SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)
#define | SMARTCARD_ADVFEATURE_TXCOMPLETION ((uint32_t)0x00000100)

Define Documentation

#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)

Binary data inversion

Definition at line 79 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)

DMA disable on Reception Error

Definition at line 82 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)

Most significant bit sent/received first

Definition at line 83 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)

No advanced feature initialization

Definition at line 76 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Init().

#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)

RX pin active level inversion

Definition at line 78 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)

RX overrun disable

Definition at line 81 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)

TX/RX pins swap

Definition at line 80 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_TXCOMPLETION ((uint32_t)0x00000100)

TX completion indication before of after guard time

Definition at line 84 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)

TX pin active level inversion

Definition at line 77 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD Flags

Defines
SMARTCARD Flags
SMARTCARD Extended Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT
#define | SMARTCARD_FLAG_REACK USART_ISR_REACK
#define | SMARTCARD_FLAG_TEACK USART_ISR_TEACK
#define | SMARTCARD_FLAG_BUSY USART_ISR_BUSY
#define | SMARTCARD_FLAG_EOBF USART_ISR_EOBF
#define | SMARTCARD_FLAG_RTOF USART_ISR_RTOF
#define | SMARTCARD_FLAG_TXE USART_ISR_TXE
#define | SMARTCARD_FLAG_TC USART_ISR_TC
#define | SMARTCARD_FLAG_RXNE USART_ISR_RXNE
#define | SMARTCARD_FLAG_IDLE USART_ISR_IDLE
#define | SMARTCARD_FLAG_ORE USART_ISR_ORE
#define | SMARTCARD_FLAG_NE USART_ISR_NE
#define | SMARTCARD_FLAG_FE USART_ISR_FE
#define | SMARTCARD_FLAG_PE USART_ISR_PE
#define | SMARTCARD_FLAG_TXFT USART_ISR_TXFT
#define | SMARTCARD_FLAG_RXFT USART_ISR_RXFT
#define | SMARTCARD_FLAG_RXFF USART_ISR_RXFF
#define | SMARTCARD_FLAG_TXFE USART_ISR_TXFE

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY

SMARTCARD busy flag

Definition at line 100 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF

SMARTCARD end of block flag

Definition at line 101 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_FE USART_ISR_FE

SMARTCARD frame error

Definition at line 109 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE

SMARTCARD idle line detection

Definition at line 106 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_NE USART_ISR_NE

SMARTCARD noise error

Definition at line 108 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_ORE USART_ISR_ORE

SMARTCARD overrun error

Definition at line 107 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_PE USART_ISR_PE

SMARTCARD parity error

Definition at line 110 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_REACK USART_ISR_REACK

SMARTCARD receive enable acknowledge flag

Definition at line 98 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF

SMARTCARD receiver timeout flag

Definition at line 102 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RXFF USART_ISR_RXFF

SMARTCARD RXFIFO Fullflag

Definition at line 113 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RXFT USART_ISR_RXFT

SMARTCARD RXFIFO threshold flag

Definition at line 112 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE

SMARTCARD read data register not empty

Definition at line 105 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Receive().

#define SMARTCARD_FLAG_TC USART_ISR_TC

SMARTCARD transmission complete

Definition at line 104 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT

SMARTCARD transmission complete before guard time completion

Definition at line 97 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK

SMARTCARD transmit enable acknowledge flag

Definition at line 99 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TXE USART_ISR_TXE

SMARTCARD transmit data register empty

Definition at line 103 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Transmit().

#define SMARTCARD_FLAG_TXFE USART_ISR_TXFE

SMARTCARD TXFIFO Empty flag

Definition at line 114 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TXFT USART_ISR_TXFT

SMARTCARD TXFIFO threshold flag

Definition at line 111 of file stm32h7xx_hal_smartcard_ex.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD Interrupts Definition

Defines
SMARTCARD Interrupts Definition
SMARTCARD Extended Exported Constants

Elements values convention: 000ZZZZZ0XXYYYYYb. More...

Defines

#define | SMARTCARD_IT_PE ((uint16_t)0x0028)
#define | SMARTCARD_IT_TXE ((uint16_t)0x0727)
#define | SMARTCARD_IT_TC ((uint16_t)0x0626)
#define | SMARTCARD_IT_RXNE ((uint16_t)0x0525)
#define | SMARTCARD_IT_IDLE ((uint16_t)0x0424)
#define | SMARTCARD_IT_ERR ((uint16_t)0x0060)
#define | SMARTCARD_IT_ORE ((uint16_t)0x0300)
#define | SMARTCARD_IT_NE ((uint16_t)0x0200)
#define | SMARTCARD_IT_FE ((uint16_t)0x0100)
#define | SMARTCARD_IT_EOB ((uint16_t)0x0C3B)
#define | SMARTCARD_IT_RTO ((uint16_t)0x0B3A)
#define | SMARTCARD_IT_RXFF ((uint16_t)0x183F)
#define | SMARTCARD_IT_TXFE ((uint16_t)0x173E)
#define | SMARTCARD_IT_RXFT ((uint16_t)0x187C)
#define | SMARTCARD_IT_TXFT ((uint16_t)0x1B77)
#define | SMARTCARD_IT_TCBGT ((uint16_t)0x1978)

Detailed Description

Elements values convention: 000ZZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5 bits)
  • XX : Interrupt source register (2 bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZZ : Flag position in the ISR register(5 bits)

Define Documentation

#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B)

SMARTCARD end of block interruption

Definition at line 141 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_ERR ((uint16_t)0x0060)

SMARTCARD error interruption

Definition at line 136 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_FE ((uint16_t)0x0100)

SMARTCARD frame error interruption

Definition at line 139 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_IDLE ((uint16_t)0x0424)

SMARTCARD idle line detection interruption

Definition at line 134 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_NE ((uint16_t)0x0200)

SMARTCARD noise error interruption

Definition at line 138 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_ORE ((uint16_t)0x0300)

SMARTCARD overrun error interruption

Definition at line 137 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_PE ((uint16_t)0x0028)

SMARTCARD parity error interruption

Definition at line 130 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A)

SMARTCARD receiver timeout interruption

Definition at line 142 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RXFF ((uint16_t)0x183F)

Definition at line 144 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RXFT ((uint16_t)0x187C)

Definition at line 146 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RXNE ((uint16_t)0x0525)

SMARTCARD read data register not empty interruption

Definition at line 133 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TC ((uint16_t)0x0626)

SMARTCARD transmission complete interruption

Definition at line 132 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TCBGT ((uint16_t)0x1978)

SMARTCARD transmission complete before guard time completion interruption

Definition at line 148 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TXE ((uint16_t)0x0727)

SMARTCARD transmit data register empty interruption

Definition at line 131 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TXFE ((uint16_t)0x173E)

Definition at line 145 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TXFT ((uint16_t)0x1B77)

Definition at line 147 of file stm32h7xx_hal_smartcard_ex.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD Interruption Clear Flags

Defines
SMARTCARD Interruption Clear Flags
SMARTCARD Extended Exported Constants

Defines

#define | SMARTCARD_CLEAR_PEF USART_ICR_PECF
#define | SMARTCARD_CLEAR_FEF USART_ICR_FECF
#define | SMARTCARD_CLEAR_NEF USART_ICR_NCF
#define | SMARTCARD_CLEAR_OREF USART_ICR_ORECF
#define | SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF
#define | SMARTCARD_CLEAR_TCF USART_ICR_TCCF
#define | SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF
#define | SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF
#define | SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF
#define | SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF
#define | SMARTCARD_CLEAR_UDRCF USART_ICR_UDRCF

Define Documentation

#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF

SMARTCARD end of block clear flag

Definition at line 164 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_FEF USART_ICR_FECF

SMARTCARD framing error clear flag

Definition at line 157 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_DMATxOnlyAbortCallback().

#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF

SMARTCARD idle line detected clear flag

Definition at line 160 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_CLEAR_NEF USART_ICR_NCF

SMARTCARD noise detected clear flag

Definition at line 158 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF

SMARTCARD overrun error clear flag

Definition at line 159 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_PEF USART_ICR_PECF

SMARTCARD parity error clear flag

Definition at line 156 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF

SMARTCARD receiver time out clear flag

Definition at line 163 of file stm32h7xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF

SMARTCARD transmission complete before guard time completion clear flag

Definition at line 162 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF

SMARTCARD transmission complete clear flag

Definition at line 161 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF

SMARTCARD TXFIFO empty clear flag

Definition at line 165 of file stm32h7xx_hal_smartcard_ex.h.

#define SMARTCARD_CLEAR_UDRCF USART_ICR_UDRCF

SMARTCARD UnderRun Error Clear Flag

Definition at line 166 of file stm32h7xx_hal_smartcard_ex.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMBUS Private Constants

Defines
SMBUS Private Constants
SMBUS

Defines

#define | TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! SMBUS TIMING clear register Mask */
#define | HAL_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */
#define | HAL_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_TC ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */
#define | MAX_NBYTE_SIZE 255

Define Documentation

#define HAL_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */

Definition at line 147 of file stm32h7xx_hal_smbus.c.

#define HAL_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */

Definition at line 148 of file stm32h7xx_hal_smbus.c.

#define HAL_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */

Definition at line 149 of file stm32h7xx_hal_smbus.c.

#define HAL_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */

Definition at line 150 of file stm32h7xx_hal_smbus.c.

#define HAL_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */

Definition at line 151 of file stm32h7xx_hal_smbus.c.

#define HAL_TIMEOUT_TC ((uint32_t)25) /* 25 ms */

Definition at line 152 of file stm32h7xx_hal_smbus.c.

#define HAL_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */

Definition at line 153 of file stm32h7xx_hal_smbus.c.

#define HAL_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */

Definition at line 154 of file stm32h7xx_hal_smbus.c.

#define MAX_NBYTE_SIZE 255

Definition at line 155 of file stm32h7xx_hal_smbus.c.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! SMBUS TIMING clear register Mask */

Definition at line 146 of file stm32h7xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SMBUS Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SMBUS_Init (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS peripheral.
__weak void | HAL_SMBUS_MspInit (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS MSP.
__weak void | HAL_SMBUS_MspDeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the SMBUSx peripheral:

      (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, IT and NVIC ).

      (+) Call the function HAL_SMBUS_Init() to configure the selected device with
          the selected configuration:
        (++) Clock Timing
        (++) Bus Timeout
        (++) Analog Filer mode
        (++) Own Address 1
        (++) Addressing mode (Master, Slave)
        (++) Dual Addressing mode
        (++) Own Address 2
        (++) Own Address 2 Mask
        (++) General call mode
        (++) Nostretch mode
        (++) Packet Error Check mode
        (++) Peripheral mode

      (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
          of the selected SMBUSx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_DeInit ( SMBUS_HandleTypeDef * hsmbus )

DeInitialize the SMBUS peripheral.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 331 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_MspDeInit(), HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_RESET, SMBUS_HandleTypeDef::Instance, SMBUS_HandleTypeDef::PreviousState, and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Init ( SMBUS_HandleTypeDef * hsmbus )

Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 229 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, SMBUS_InitTypeDef::AddressingMode, SMBUS_InitTypeDef::AnalogFilter, assert_param, SMBUS_InitTypeDef::DualAddressMode, SMBUS_HandleTypeDef::ErrorCode, SMBUS_InitTypeDef::GeneralCallMode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_MspInit(), HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_RESET, SMBUS_HandleTypeDef::Init, SMBUS_HandleTypeDef::Instance, IS_SMBUS_ADDRESSING_MODE, IS_SMBUS_ANALOG_FILTER, IS_SMBUS_DUAL_ADDRESS, IS_SMBUS_GENERAL_CALL, IS_SMBUS_NO_STRETCH, IS_SMBUS_OWN_ADDRESS1, IS_SMBUS_OWN_ADDRESS2, IS_SMBUS_OWN_ADDRESS2_MASK, IS_SMBUS_PEC, IS_SMBUS_PERIPHERAL_MODE, SMBUS_HandleTypeDef::Lock, SMBUS_InitTypeDef::NoStretchMode, SMBUS_InitTypeDef::OwnAddress1, SMBUS_InitTypeDef::OwnAddress2, SMBUS_InitTypeDef::OwnAddress2Masks, SMBUS_InitTypeDef::PacketErrorCheckMode, SMBUS_InitTypeDef::PeripheralMode, SMBUS_HandleTypeDef::PreviousState, SMBUS_ADDRESSINGMODE_10BIT, SMBUS_ADDRESSINGMODE_7BIT, SMBUS_PEC_ENABLE, SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE, SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP, SMBUS_InitTypeDef::SMBusTimeout, SMBUS_HandleTypeDef::State, SMBUS_InitTypeDef::Timing, and TIMING_CLEAR_MASK.

void HAL_SMBUS_MspDeInit ( SMBUS_HandleTypeDef * hsmbus )

DeInitialize the SMBUS MSP.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 382 of file stm32h7xx_hal_smbus.c.

Referenced by HAL_SMBUS_DeInit().

void HAL_SMBUS_MspInit ( SMBUS_HandleTypeDef * hsmbus )

Initialize the SMBUS MSP.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 366 of file stm32h7xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Blocking mode Polling

Functions
Blocking mode Polling
Input and Output operation functions

Functions

HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Check if target device is ready for communication.

Note:
This function is used with Memory devices
Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress,: Target device address
Trials,: Number of trials
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 935 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_GET_FLAG, SMBUS_InitTypeDef::AddressingMode, SMBUS_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_TIMEOUT, SMBUS_HandleTypeDef::Init, SMBUS_HandleTypeDef::Instance, SMBUS_FLAG_AF, SMBUS_FLAG_BUSY, SMBUS_FLAG_STOPF, SMBUS_GENERATE_START, SMBUS_WaitOnFlagUntilTimeout(), and SMBUS_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Non-Blocking mode Interrupt

Functions
Non-Blocking mode Interrupt
Input and Output operation functions

Functions

HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 914 of file stm32h7xx_hal_smbus.c.

References SMBUS_HandleTypeDef::Instance, SMBUS_Disable_IRQ(), and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the Address listen mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 871 of file stm32h7xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, SMBUS_Disable_IRQ(), SMBUS_IT_ADDR, and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 895 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, SMBUS_HandleTypeDef::Instance, SMBUS_Enable_IRQ(), SMBUS_FLAG_ALERT, and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the Address listen mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 855 of file stm32h7xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, SMBUS_Enable_IRQ(), SMBUS_IT_ADDR, and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master/host SMBUS process communication with Interrupt.

Note:
This abort can be called only if state is ready
Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress,: Target device address
Return values:
HAL status

Definition at line 624 of file stm32h7xx_hal_smbus.c.

References SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_Enable_IRQ(), SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_TransferConfig(), and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
XferOptions,: Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 541 of file stm32h7xx_hal_smbus.c.

References assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_READ, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
XferOptions,: Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 449 of file stm32h7xx_hal_smbus.c.

References assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_WRITE, SMBUS_GET_PEC_MODE, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
XferOptions,: Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 778 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_RX, SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
XferOptions,: Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 685 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_TX, SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRQ Handler and Callbacks

Functions
IRQ Handler and Callbacks
SMBUS Exported Functions | Input and Output operation functions

Functions

void | HAL_SMBUS_EV_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS event interrupt request.
void | HAL_SMBUS_ER_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS error interrupt request.
__weak void | HAL_SMBUS_MasterTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Tx Transfer completed callback.
__weak void | HAL_SMBUS_MasterRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Rx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Tx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Rx Transfer completed callback.
__weak void | HAL_SMBUS_AddrCallback (SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_SMBUS_ListenCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Listen Complete callback.
__weak void | HAL_SMBUS_ErrorCallback (SMBUS_HandleTypeDef *hsmbus)
SMBUS error callback.

Function Documentation

void HAL_SMBUS_AddrCallback | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t | TransferDirection,
 |  | uint16_t | AddrMatchCode
 | ) |  |

Slave Address Match callback.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
TransferDirection,: Master request Transfer Direction (Write/Read)
AddrMatchCode,: Address Match Code
Return values:
None

Definition at line 1259 of file stm32h7xx_hal_smbus.c.

Referenced by SMBUS_Slave_ISR().

void HAL_SMBUS_ER_IRQHandler ( SMBUS_HandleTypeDef * hsmbus )

Handle SMBUS error interrupt request.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1111 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_GET_FLAG, __HAL_SMBUS_GET_IT_SOURCE, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_ACKF, HAL_SMBUS_ERROR_ALERT, HAL_SMBUS_ERROR_ARLO, HAL_SMBUS_ERROR_BERR, HAL_SMBUS_ERROR_BUSTIMEOUT, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_ERROR_OVR, HAL_SMBUS_ERROR_PECERR, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_SLAVE_BUSY_RX, HAL_SMBUS_STATE_SLAVE_BUSY_TX, SMBUS_HandleTypeDef::PreviousState, SMBUS_FLAG_ALERT, SMBUS_FLAG_ARLO, SMBUS_FLAG_BERR, SMBUS_FLAG_OVR, SMBUS_FLAG_PECERR, SMBUS_FLAG_TIMEOUT, SMBUS_IT_ERRI, and SMBUS_HandleTypeDef::State.

void HAL_SMBUS_ErrorCallback ( SMBUS_HandleTypeDef * hsmbus )

SMBUS error callback.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1293 of file stm32h7xx_hal_smbus.c.

Referenced by HAL_SMBUS_ER_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

void HAL_SMBUS_EV_IRQHandler ( SMBUS_HandleTypeDef * hsmbus )

Handle SMBUS event interrupt request.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1056 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_GET_IT_SOURCE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_SLAVE_BUSY_RX, HAL_SMBUS_STATE_SLAVE_BUSY_TX, SMBUS_CHECK_FLAG, SMBUS_FLAG_ADDR, SMBUS_FLAG_AF, SMBUS_FLAG_RXNE, SMBUS_FLAG_STOPF, SMBUS_FLAG_TC, SMBUS_FLAG_TCR, SMBUS_FLAG_TXIS, SMBUS_GET_ISR_REG, SMBUS_IT_ADDRI, SMBUS_IT_NACKI, SMBUS_IT_RXI, SMBUS_IT_STOPI, SMBUS_IT_TCI, SMBUS_IT_TXI, SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_HandleTypeDef::State.

void HAL_SMBUS_ListenCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Listen Complete callback.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1277 of file stm32h7xx_hal_smbus.c.

Referenced by SMBUS_Slave_ISR().

void HAL_SMBUS_MasterRxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Master Rx Transfer completed callback.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1210 of file stm32h7xx_hal_smbus.c.

Referenced by SMBUS_Master_ISR().

void HAL_SMBUS_MasterTxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Master Tx Transfer completed callback.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1194 of file stm32h7xx_hal_smbus.c.

Referenced by SMBUS_Master_ISR().

void HAL_SMBUS_SlaveRxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Slave Rx Transfer completed callback.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1241 of file stm32h7xx_hal_smbus.c.

Referenced by SMBUS_Slave_ISR().

void HAL_SMBUS_SlaveTxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Slave Tx Transfer completed callback.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1225 of file stm32h7xx_hal_smbus.c.

Referenced by SMBUS_Slave_ISR().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SMBUS Exported Functions | Input and Output operation functions

Peripheral State and Errors functions. More...

Functions

uint32_t | HAL_SMBUS_GetState (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS handle state.
uint32_t | HAL_SMBUS_GetError (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS error code.

Detailed Description

Peripheral State and Errors functions.

 ===============================================================================
            ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_SMBUS_GetError ( SMBUS_HandleTypeDef * hsmbus )

Return the SMBUS error code.

Parameters:
hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
SMBUS Error Code

Definition at line 1340 of file stm32h7xx_hal_smbus.c.

References SMBUS_HandleTypeDef::ErrorCode.

uint32_t HAL_SMBUS_GetState ( SMBUS_HandleTypeDef * hsmbus )

Return the SMBUS handle state.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL state

Definition at line 1328 of file stm32h7xx_hal_smbus.c.

References SMBUS_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Input and Output operation functions

Modules | Functions
Input and Output operation functions
SMBUS Exported Functions

Data transfers functions. More...

Modules

Blocking mode Polling
Non-Blocking mode Interrupt
IRQ Handler and Callbacks
Peripheral State and Errors functions

Peripheral State and Errors functions.

Functions

HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the SMBUS data
    transfers.

    (#) Blocking mode function to check if device is ready for usage is :
        (++) HAL_SMBUS_IsDeviceReady()

    (#) There is only one mode of transfer:
       (++) Non-Blocking mode : The communication is performed using Interrupts.
            These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated SMBUS IRQ when using Interrupt mode.

    (#) Non-Blocking mode functions with Interrupt are :
        (++) HAL_SMBUS_Master_Transmit_IT()
        (++) HAL_SMBUS_Master_Receive_IT()
        (++) HAL_SMBUS_Slave_Transmit_IT()
        (++) HAL_SMBUS_Slave_Receive_IT()
        (++) HAL_SMBUS_EnableListen_IT()
        (++) HAL_SMBUS_DisableListen_IT()
        (++) HAL_SMBUS_EnableAlert_IT()
        (++) HAL_SMBUS_DisableAlert_IT()

    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
        (++) HAL_SMBUS_MasterTxCpltCallback()
        (++) HAL_SMBUS_MasterRxCpltCallback()
        (++) HAL_SMBUS_SlaveTxCpltCallback()
        (++) HAL_SMBUS_SlaveRxCpltCallback()
        (++) HAL_SMBUS_AddrCallback()
        (++) HAL_SMBUS_ListenCpltCallback()
        (++) HAL_SMBUS_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 914 of file stm32h7xx_hal_smbus.c.

References SMBUS_HandleTypeDef::Instance, SMBUS_Disable_IRQ(), and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the Address listen mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 871 of file stm32h7xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, SMBUS_Disable_IRQ(), SMBUS_IT_ADDR, and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 895 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, SMBUS_HandleTypeDef::Instance, SMBUS_Enable_IRQ(), SMBUS_FLAG_ALERT, and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the Address listen mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 855 of file stm32h7xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, SMBUS_Enable_IRQ(), SMBUS_IT_ADDR, and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Check if target device is ready for communication.

Note:
This function is used with Memory devices
Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress,: Target device address
Trials,: Number of trials
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 935 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_GET_FLAG, SMBUS_InitTypeDef::AddressingMode, SMBUS_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_TIMEOUT, SMBUS_HandleTypeDef::Init, SMBUS_HandleTypeDef::Instance, SMBUS_FLAG_AF, SMBUS_FLAG_BUSY, SMBUS_FLAG_STOPF, SMBUS_GENERATE_START, SMBUS_WaitOnFlagUntilTimeout(), and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master/host SMBUS process communication with Interrupt.

Note:
This abort can be called only if state is ready
Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress,: Target device address
Return values:
HAL status

Definition at line 624 of file stm32h7xx_hal_smbus.c.

References SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_Enable_IRQ(), SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_TransferConfig(), and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
XferOptions,: Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 541 of file stm32h7xx_hal_smbus.c.

References assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_READ, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
XferOptions,: Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 449 of file stm32h7xx_hal_smbus.c.

References assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_WRITE, SMBUS_GET_PEC_MODE, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
XferOptions,: Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 778 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_RX, SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
XferOptions,: Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 685 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_TX, SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMBUS Private Functions

Functions
SMBUS Private Functions
SMBUS Exported Functions | SMBUS

Data transfers Private functions. More...

Functions

static HAL_StatusTypeDef | SMBUS_WaitOnFlagUntilTimeout (SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
Handle SMBUS Communication Timeout.
static HAL_StatusTypeDef | SMBUS_Enable_IRQ (SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static HAL_StatusTypeDef | SMBUS_Disable_IRQ (SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static HAL_StatusTypeDef | SMBUS_Master_ISR (SMBUS_HandleTypeDef *hsmbus)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
static HAL_StatusTypeDef | SMBUS_Slave_ISR (SMBUS_HandleTypeDef *hsmbus)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
static void | SMBUS_ConvertOtherXferOptions (SMBUS_HandleTypeDef *hsmbus)
Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
static void | SMBUS_TransferConfig (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).

Detailed Description

Data transfers Private functions.

Function Documentation

static void SMBUS_ConvertOtherXferOptions ( SMBUS_HandleTypeDef * hsmbus ) [static]

Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.

Parameters:
hsmbus SMBUS handle.
Return values:
None

Definition at line 2004 of file stm32h7xx_hal_smbus.c.

References SMBUS_FIRST_AND_LAST_FRAME_NO_PEC, SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC, SMBUS_FIRST_FRAME, SMBUS_OTHER_AND_LAST_FRAME_NO_PEC, SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC, SMBUS_OTHER_FRAME_NO_PEC, SMBUS_OTHER_FRAME_WITH_PEC, SMBUS_SENDPEC_MODE, and SMBUS_HandleTypeDef::XferOptions.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

static HAL_StatusTypeDef SMBUS_Disable_IRQ | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the disabling of Interrupts.

Parameters:
hsmbus | : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
InterruptRequest | : Value of SMBUS Interrupt configuration definition.
Return values:
HAL status

Definition at line 1832 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE_IT, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, SMBUS_GET_ALERT_ENABLED, SMBUS_IT_ADDR, SMBUS_IT_ADDRI, SMBUS_IT_ALERT, SMBUS_IT_ERRI, SMBUS_IT_NACKI, SMBUS_IT_RX, SMBUS_IT_RXI, SMBUS_IT_STOPI, SMBUS_IT_TCI, SMBUS_IT_TX, SMBUS_IT_TXI, and SMBUS_HandleTypeDef::State.

Referenced by HAL_SMBUS_DisableAlert_IT(), HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

static HAL_StatusTypeDef SMBUS_Enable_IRQ | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the enabling of Interrupts.

Parameters:
hsmbus | : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
InterruptRequest | : Value of SMBUS Interrupt configuration definition.
Return values:
HAL status

Definition at line 1790 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_ENABLE_IT, SMBUS_IT_ADDR, SMBUS_IT_ADDRI, SMBUS_IT_ALERT, SMBUS_IT_ERRI, SMBUS_IT_NACKI, SMBUS_IT_RX, SMBUS_IT_RXI, SMBUS_IT_STOPI, SMBUS_IT_TCI, SMBUS_IT_TX, and SMBUS_IT_TXI.

Referenced by HAL_SMBUS_EnableAlert_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

static HAL_StatusTypeDef SMBUS_Master_ISR ( SMBUS_HandleTypeDef * hsmbus ) [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1364 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, __HAL_SMBUS_GET_FLAG, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_ACKF, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_MasterRxCpltCallback(), HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, SMBUS_HandleTypeDef::Instance, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_Disable_IRQ(), SMBUS_FLAG_AF, SMBUS_FLAG_RXNE, SMBUS_FLAG_STOPF, SMBUS_FLAG_TC, SMBUS_FLAG_TCR, SMBUS_FLAG_TXIS, SMBUS_GET_PEC_MODE, SMBUS_GET_STOP_MODE, SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_RESET_CR2, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

Referenced by HAL_SMBUS_EV_IRQHandler().

static HAL_StatusTypeDef SMBUS_Slave_ISR ( SMBUS_HandleTypeDef * hsmbus ) [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1573 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_DISABLE_IT, __HAL_SMBUS_GET_FLAG, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_AddrCallback(), HAL_SMBUS_ERROR_ACKF, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_ListenCpltCallback(), HAL_SMBUS_SlaveRxCpltCallback(), HAL_SMBUS_SlaveTxCpltCallback(), HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_SLAVE_BUSY_RX, HAL_SMBUS_STATE_SLAVE_BUSY_TX, SMBUS_HandleTypeDef::Instance, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_HandleTypeDef::PreviousState, SMBUS_Disable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_FLAG_AF, SMBUS_FLAG_RXNE, SMBUS_FLAG_STOPF, SMBUS_FLAG_TCR, SMBUS_FLAG_TXIS, SMBUS_GET_ADDR_MATCH, SMBUS_GET_DIR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_ADDRI, SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_RESET_CR2, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

Referenced by HAL_SMBUS_EV_IRQHandler().

static void SMBUS_TransferConfig | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t | Size,
 |  | uint32_t | Mode,
 |  | uint32_t | Request
 | ) |  | [static]

Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).

Parameters:
hsmbus,: SMBUS handle.
DevAddress,: specifies the slave address to be programmed.
Size,: specifies the number of bytes to be programmed. This parameter must be a value between 0 and 255.
Mode,: new state of the SMBUS START condition generation. This parameter can be one or a combination of the following values:
  • SMBUS_NO_MODE: No specific mode enabled.
  • SMBUS_RELOAD_MODE: Enable Reload mode.
  • SMBUS_AUTOEND_MODE: Enable Automatic end mode.
  • SMBUS_SOFTEND_MODE: Enable Software end mode and Reload mode.
Request,: new state of the SMBUS START condition generation. This parameter can be one of the following values:
  • SMBUS_NO_STARTSTOP: Don't Generate stop and start condition.
  • SMBUS_GENERATE_STOP: Generate stop condition (Size should be set to 0).
  • SMBUS_GENERATE_START_READ: Generate Restart for read request.
  • SMBUS_GENERATE_START_WRITE: Generate Restart for write request.
Return values:
None

Definition at line 1976 of file stm32h7xx_hal_smbus.c.

References assert_param, SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_MODE, and IS_SMBUS_TRANSFER_REQUEST.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle SMBUS Communication Timeout.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Flag,: specifies the SMBUS flag to check.
Status,: The new Flag status (SET or RESET).
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1908 of file stm32h7xx_hal_smbus.c.

References __HAL_SMBUS_GET_FLAG, HAL_GetTick(), HAL_SMBUS_STATE_READY, SMBUS_HandleTypeDef::PreviousState, and SMBUS_HandleTypeDef::State.

Referenced by HAL_SMBUS_IsDeviceReady().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMBUS_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMBUS_InitTypeDef Struct Reference
SMBUS Configuration Structure definition

#include <stm32h7xx_hal_smbus.h>

Data Fields

uint32_t | Timing
uint32_t | AnalogFilter
uint32_t | OwnAddress1
uint32_t | AddressingMode
uint32_t | DualAddressMode
uint32_t | OwnAddress2
uint32_t | OwnAddress2Masks
uint32_t | GeneralCallMode
uint32_t | NoStretchMode
uint32_t | PacketErrorCheckMode
uint32_t | PeripheralMode
uint32_t | SMBusTimeout

Detailed Description

Definition at line 66 of file stm32h7xx_hal_smbus.h.

Field Documentation

uint32_t SMBUS_InitTypeDef::AddressingMode

Specifies if 7-bit or 10-bit addressing mode for master is selected. This parameter can be a value of SMBUS addressing mode

Definition at line 77 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), and HAL_SMBUS_IsDeviceReady().

uint32_t SMBUS_InitTypeDef::AnalogFilter

Specifies if Analog Filter is enable or not. This parameter can be a value of SMBUS Analog Filter

Definition at line 71 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::DualAddressMode

Specifies if dual addressing mode is selected. This parameter can be a value of SMBUS dual addressing mode

Definition at line 80 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::GeneralCallMode

Specifies if general call mode is selected. This parameter can be a value of SMBUS general call addressing mode.

Definition at line 89 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::NoStretchMode

Specifies if nostretch mode is selected. This parameter can be a value of SMBUS nostretch mode

Definition at line 92 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::OwnAddress1

Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.

Definition at line 74 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::OwnAddress2

Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address.

Definition at line 83 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::OwnAddress2Masks

Specifies the acknoledge mask address second device own address if dual addressing mode is selected This parameter can be a value of SMBUS own address2 masks.

Definition at line 86 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::PacketErrorCheckMode

Specifies if Packet Error Check mode is selected. This parameter can be a value of SMBUS packet error check mode

Definition at line 95 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::PeripheralMode

Specifies which mode of Periphal is selected. This parameter can be a value of SMBUS peripheral mode

Definition at line 98 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::SMBusTimeout

Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. (Enable bits and different timeout values) This parameter calculated by referring to SMBUS initialization section in Reference manual

Definition at line 101 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::Timing

Specifies the SMBUS_TIMINGR_register value. This parameter calculated by referring to SMBUS initialization section in Reference manual

Definition at line 68 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_smbus.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HAL state definition

Defines
HAL state definition
SMBUS Exported Types

HAL State definition. More...

Defines

#define | HAL_SMBUS_STATE_RESET (0x00000000U)
#define | HAL_SMBUS_STATE_READY (0x00000001U)
#define | HAL_SMBUS_STATE_BUSY (0x00000002U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U)
#define | HAL_SMBUS_STATE_TIMEOUT (0x00000003U)
#define | HAL_SMBUS_STATE_ERROR (0x00000004U)
#define | HAL_SMBUS_STATE_LISTEN (0x00000008U)

Detailed Description

HAL State definition.

Define Documentation

#define HAL_SMBUS_STATE_BUSY (0x00000002U)

SMBUS internal process is ongoing

Definition at line 116 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), and HAL_SMBUS_IsDeviceReady().

#define HAL_SMBUS_STATE_ERROR (0x00000004U)

Reception process is ongoing

Definition at line 122 of file stm32h7xx_hal_smbus.h.

#define HAL_SMBUS_STATE_LISTEN (0x00000008U)

Address Listen Mode is ongoing

Definition at line 123 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_ER_IRQHandler(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U)

Master Data Reception process is ongoing

Definition at line 118 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), and SMBUS_Master_ISR().

#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U)

Master Data Transmission process is ongoing

Definition at line 117 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Transmit_IT(), and SMBUS_Master_ISR().

#define HAL_SMBUS_STATE_READY (0x00000001U)

SMBUS initialized and ready for use

Definition at line 115 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_ER_IRQHandler(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

#define HAL_SMBUS_STATE_RESET (0x00000000U)

SMBUS not yet initialized or disabled

Definition at line 114 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), and HAL_SMBUS_Init().

#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U)

Slave Data Reception process is ongoing

Definition at line 120 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Receive_IT(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U)

Slave Data Transmission process is ongoing

Definition at line 119 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Transmit_IT(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U)

Timeout state

Definition at line 121 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMBUS Error Code definition

Defines
SMBUS Error Code definition
SMBUS Exported Types

SMBUS Error Code definition. More...

Defines

#define | HAL_SMBUS_ERROR_NONE (0x00000000U)
#define | HAL_SMBUS_ERROR_BERR (0x00000001U)
#define | HAL_SMBUS_ERROR_ARLO (0x00000002U)
#define | HAL_SMBUS_ERROR_ACKF (0x00000004U)
#define | HAL_SMBUS_ERROR_OVR (0x00000008U)
#define | HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U)
#define | HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U)
#define | HAL_SMBUS_ERROR_ALERT (0x00000040U)
#define | HAL_SMBUS_ERROR_PECERR (0x00000080U)

Detailed Description

SMBUS Error Code definition.

Define Documentation

#define HAL_SMBUS_ERROR_ACKF (0x00000004U)

ACKF error

Definition at line 135 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_ERROR_ALERT (0x00000040U)

Alert error

Definition at line 139 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

#define HAL_SMBUS_ERROR_ARLO (0x00000002U)

ARLO error

Definition at line 134 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

#define HAL_SMBUS_ERROR_BERR (0x00000001U)

BERR error

Definition at line 133 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U)

Bus Timeout error

Definition at line 138 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U)

Timeout error

Definition at line 137 of file stm32h7xx_hal_smbus.h.

#define HAL_SMBUS_ERROR_NONE (0x00000000U)

No error

Definition at line 132 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_ER_IRQHandler(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

#define HAL_SMBUS_ERROR_OVR (0x00000008U)

OVR error

Definition at line 136 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

#define HAL_SMBUS_ERROR_PECERR (0x00000080U)

PEC error

Definition at line 140 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMBUS_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMBUS_HandleTypeDef Struct Reference
SMBUS handle Structure definition

#include <stm32h7xx_hal_smbus.h>

Data Fields

I2C_TypeDef * | Instance
SMBUS_InitTypeDef Init
uint8_t * | pBuffPtr
uint16_t | XferSize
__IO uint16_t | XferCount
__IO uint32_t | XferOptions
__IO uint32_t | PreviousState
HAL_LockTypeDef | Lock
__IO uint32_t | State
__IO uint32_t | ErrorCode

Detailed Description

Definition at line 149 of file stm32h7xx_hal_smbus.h.

Field Documentation

__IO uint32_t SMBUS_HandleTypeDef::ErrorCode

SMBUS Error code

Definition at line 169 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_ER_IRQHandler(), HAL_SMBUS_GetError(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

SMBUS_InitTypeDef SMBUS_HandleTypeDef::Init

SMBUS communication parameters

Definition at line 153 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), and HAL_SMBUS_IsDeviceReady().

I2C_TypeDef* SMBUS_HandleTypeDef::Instance

SMBUS registers base address

Definition at line 151 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_DisableAlert_IT(), HAL_SMBUS_EnableAlert_IT(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_TransferConfig().

HAL_LockTypeDef SMBUS_HandleTypeDef::Lock

SMBUS locking object

Definition at line 165 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint8_t* SMBUS_HandleTypeDef::pBuffPtr

Pointer to SMBUS transfer buffer

Definition at line 155 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

__IO uint32_t SMBUS_HandleTypeDef::PreviousState

SMBUS communication Previous state

Definition at line 163 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_ER_IRQHandler(), HAL_SMBUS_Init(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

__IO uint32_t SMBUS_HandleTypeDef::State

SMBUS communication state

Definition at line 167 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_ER_IRQHandler(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_GetState(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

__IO uint16_t SMBUS_HandleTypeDef::XferCount

SMBUS transfer counter

Definition at line 159 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

__IO uint32_t SMBUS_HandleTypeDef::XferOptions

SMBUS transfer options

Definition at line 161 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ConvertOtherXferOptions(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

uint16_t SMBUS_HandleTypeDef::XferSize

SMBUS transfer size

Definition at line 157 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_smbus.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMBUS Analog Filter

Defines
SMBUS Analog Filter
SMBUS Exported Constants

Defines

#define | SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
#define | SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Define Documentation

#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Definition at line 189 of file stm32h7xx_hal_smbus.h.

#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)

Definition at line 188 of file stm32h7xx_hal_smbus.h.

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STM32H753xx HAL User Manual: SMBUS addressing mode

Defines
SMBUS addressing mode
SMBUS Exported Constants

Defines

#define | SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
#define | SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)

Define Documentation

#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)

Definition at line 198 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)

Definition at line 197 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

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STM32H753xx HAL User Manual: SMBUS dual addressing mode

Defines
SMBUS dual addressing mode
SMBUS Exported Constants

Defines

#define | SMBUS_DUALADDRESS_DISABLE (0x00000000U)
#define | SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Define Documentation

#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)

Definition at line 207 of file stm32h7xx_hal_smbus.h.

#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Definition at line 208 of file stm32h7xx_hal_smbus.h.

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STM32H753xx HAL User Manual: SMBUS own address2 masks

Defines
SMBUS own address2 masks
SMBUS Exported Constants

Defines

#define | SMBUS_OA2_NOMASK ((uint8_t)0x00U)
#define | SMBUS_OA2_MASK01 ((uint8_t)0x01U)
#define | SMBUS_OA2_MASK02 ((uint8_t)0x02U)
#define | SMBUS_OA2_MASK03 ((uint8_t)0x03U)
#define | SMBUS_OA2_MASK04 ((uint8_t)0x04U)
#define | SMBUS_OA2_MASK05 ((uint8_t)0x05U)
#define | SMBUS_OA2_MASK06 ((uint8_t)0x06U)
#define | SMBUS_OA2_MASK07 ((uint8_t)0x07U)

Define Documentation

#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)

Definition at line 218 of file stm32h7xx_hal_smbus.h.

#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)

Definition at line 219 of file stm32h7xx_hal_smbus.h.

#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)

Definition at line 220 of file stm32h7xx_hal_smbus.h.

#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)

Definition at line 221 of file stm32h7xx_hal_smbus.h.

#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)

Definition at line 222 of file stm32h7xx_hal_smbus.h.

#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)

Definition at line 223 of file stm32h7xx_hal_smbus.h.

#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)

Definition at line 224 of file stm32h7xx_hal_smbus.h.

#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)

Definition at line 217 of file stm32h7xx_hal_smbus.h.

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STM32H753xx HAL User Manual: SMBUS general call addressing mode

Defines
SMBUS general call addressing mode
SMBUS Exported Constants

Defines

#define | SMBUS_GENERALCALL_DISABLE (0x00000000U)
#define | SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN

Define Documentation

#define SMBUS_GENERALCALL_DISABLE (0x00000000U)

Definition at line 233 of file stm32h7xx_hal_smbus.h.

#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN

Definition at line 234 of file stm32h7xx_hal_smbus.h.

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STM32H753xx HAL User Manual: SMBUS nostretch mode

Defines
SMBUS nostretch mode
SMBUS Exported Constants

Defines

#define | SMBUS_NOSTRETCH_DISABLE (0x00000000U)
#define | SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Define Documentation

#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)

Definition at line 242 of file stm32h7xx_hal_smbus.h.

#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Definition at line 243 of file stm32h7xx_hal_smbus.h.

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STM32H753xx HAL User Manual: SMBUS packet error check mode

Defines
SMBUS packet error check mode
SMBUS Exported Constants

Defines

#define | SMBUS_PEC_DISABLE (0x00000000U)
#define | SMBUS_PEC_ENABLE I2C_CR1_PECEN

Define Documentation

#define SMBUS_PEC_DISABLE (0x00000000U)

Definition at line 251 of file stm32h7xx_hal_smbus.h.

#define SMBUS_PEC_ENABLE I2C_CR1_PECEN

Definition at line 252 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

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STM32H753xx HAL User Manual: SMBUS peripheral mode

Defines
SMBUS peripheral mode
SMBUS Exported Constants

Defines

#define | SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN

Define Documentation

#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN

Definition at line 260 of file stm32h7xx_hal_smbus.h.

#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)

Definition at line 261 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN

Definition at line 262 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

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STM32H753xx HAL User Manual: SMBUS ReloadEndMode definition

Defines
SMBUS ReloadEndMode definition
SMBUS Exported Constants

Defines

#define | SMBUS_SOFTEND_MODE (0x00000000U)
#define | SMBUS_RELOAD_MODE I2C_CR2_RELOAD
#define | SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
#define | SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE

Define Documentation

#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND

Definition at line 273 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), and SMBUS_Master_ISR().

#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD

Definition at line 272 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE

Definition at line 274 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ConvertOtherXferOptions(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_SOFTEND_MODE (0x00000000U)

Definition at line 271 of file stm32h7xx_hal_smbus.h.

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STM32H753xx HAL User Manual: SMBUS StartStopMode definition

Defines
SMBUS StartStopMode definition
SMBUS Exported Constants

Defines

#define | SMBUS_NO_STARTSTOP (0x00000000U)
#define | SMBUS_GENERATE_STOP I2C_CR2_STOP
#define | SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | SMBUS_GENERATE_START_WRITE I2C_CR2_START

Define Documentation

#define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)

Definition at line 285 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT().

#define SMBUS_GENERATE_START_WRITE I2C_CR2_START

Definition at line 286 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Transmit_IT().

#define SMBUS_GENERATE_STOP I2C_CR2_STOP

Definition at line 284 of file stm32h7xx_hal_smbus.h.

#define SMBUS_NO_STARTSTOP (0x00000000U)

Definition at line 283 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

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STM32H753xx HAL User Manual: SMBUS XferOptions definition

Defines
SMBUS XferOptions definition
SMBUS Exported Constants

Defines

#define | SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
#define | SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define | SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
#define | SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
#define | SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
#define | SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)

Define Documentation

#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE

Definition at line 301 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))

Definition at line 303 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE

Definition at line 299 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE

Definition at line 302 of file stm32h7xx_hal_smbus.h.

#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))

Definition at line 304 of file stm32h7xx_hal_smbus.h.

#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))

Definition at line 300 of file stm32h7xx_hal_smbus.h.

#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)

Definition at line 311 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)

Definition at line 312 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)

Definition at line 309 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)

Definition at line 310 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

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STM32H753xx HAL User Manual: SMBUS Interrupt configuration definition

Defines
SMBUS Interrupt configuration definition
SMBUS Exported Constants

SMBUS Interrupt definition Elements values convention: 0xXXXXXXXX. More...

Defines

#define | SMBUS_IT_ERRI I2C_CR1_ERRIE
#define | SMBUS_IT_TCI I2C_CR1_TCIE
#define | SMBUS_IT_STOPI I2C_CR1_STOPIE
#define | SMBUS_IT_NACKI I2C_CR1_NACKIE
#define | SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define | SMBUS_IT_RXI I2C_CR1_RXIE
#define | SMBUS_IT_TXI I2C_CR1_TXIE
#define | SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
#define | SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
#define | SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define | SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)

Detailed Description

SMBUS Interrupt definition Elements values convention: 0xXXXXXXXX.

  • XXXXXXXX : Interrupt control mask

Define Documentation

#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)

Definition at line 333 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), and SMBUS_Slave_ISR().

#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE

Definition at line 327 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), and SMBUS_Slave_ISR().

#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)

Definition at line 332 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableAlert_IT(), HAL_SMBUS_EnableAlert_IT(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_ERRI I2C_CR1_ERRIE

Definition at line 323 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_NACKI I2C_CR1_NACKIE

Definition at line 326 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)

Definition at line 331 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Slave_Receive_IT(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_IT_RXI I2C_CR1_RXIE

Definition at line 328 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_STOPI I2C_CR1_STOPIE

Definition at line 325 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_TCI I2C_CR1_TCIE

Definition at line 324 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)

Definition at line 330 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_IT_TXI I2C_CR1_TXIE

Definition at line 329 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMBUS Flag definition

Defines
SMBUS Flag definition
SMBUS Exported Constants

Flag definition Elements values convention: 0xXXXXYYYY. More...

Defines

#define | SMBUS_FLAG_TXE I2C_ISR_TXE
#define | SMBUS_FLAG_TXIS I2C_ISR_TXIS
#define | SMBUS_FLAG_RXNE I2C_ISR_RXNE
#define | SMBUS_FLAG_ADDR I2C_ISR_ADDR
#define | SMBUS_FLAG_AF I2C_ISR_NACKF
#define | SMBUS_FLAG_STOPF I2C_ISR_STOPF
#define | SMBUS_FLAG_TC I2C_ISR_TC
#define | SMBUS_FLAG_TCR I2C_ISR_TCR
#define | SMBUS_FLAG_BERR I2C_ISR_BERR
#define | SMBUS_FLAG_ARLO I2C_ISR_ARLO
#define | SMBUS_FLAG_OVR I2C_ISR_OVR
#define | SMBUS_FLAG_PECERR I2C_ISR_PECERR
#define | SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | SMBUS_FLAG_ALERT I2C_ISR_ALERT
#define | SMBUS_FLAG_BUSY I2C_ISR_BUSY
#define | SMBUS_FLAG_DIR I2C_ISR_DIR

Detailed Description

Flag definition Elements values convention: 0xXXXXYYYY.

  • XXXXXXXX : Flag mask

Define Documentation

#define SMBUS_FLAG_ADDR I2C_ISR_ADDR

Definition at line 348 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_AF I2C_ISR_NACKF

Definition at line 349 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_IsDeviceReady(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_ALERT I2C_ISR_ALERT

Definition at line 358 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EnableAlert_IT(), and HAL_SMBUS_ER_IRQHandler().

#define SMBUS_FLAG_ARLO I2C_ISR_ARLO

Definition at line 354 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

#define SMBUS_FLAG_BERR I2C_ISR_BERR

Definition at line 353 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

#define SMBUS_FLAG_BUSY I2C_ISR_BUSY

Definition at line 359 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady().

#define SMBUS_FLAG_DIR I2C_ISR_DIR

Definition at line 360 of file stm32h7xx_hal_smbus.h.

#define SMBUS_FLAG_OVR I2C_ISR_OVR

Definition at line 355 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

#define SMBUS_FLAG_PECERR I2C_ISR_PECERR

Definition at line 356 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

#define SMBUS_FLAG_RXNE I2C_ISR_RXNE

Definition at line 347 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_STOPF I2C_ISR_STOPF

Definition at line 350 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_IsDeviceReady(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_TC I2C_ISR_TC

Definition at line 351 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), and SMBUS_Master_ISR().

#define SMBUS_FLAG_TCR I2C_ISR_TCR

Definition at line 352 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT

Definition at line 357 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

#define SMBUS_FLAG_TXE I2C_ISR_TXE

Definition at line 345 of file stm32h7xx_hal_smbus.h.

#define SMBUS_FLAG_TXIS I2C_ISR_TXIS

Definition at line 346 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMBUS Exported Macros

Defines
SMBUS Exported Macros
SMBUS

Defines

#define | __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
Reset SMBUS handle state.
#define | __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified SMBUS interrupts.
#define | __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified SMBUS interrupts.
#define | __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SMBUS interrupt source is enabled or not.
#define | SMBUS_FLAG_MASK (0x0001FFFFU)
Check whether the specified SMBUS flag is set or not.
#define | __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
#define | __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified SMBUS peripheral.
#define | __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified SMBUS peripheral.
#define | __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge SMBUS peripheral in Slave mode.

Define Documentation

#define __HAL_SMBUS_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.

Parameters:
__HANDLE__,: specifies the SMBUS Handle.
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • SMBUS_FLAG_ADDR: Address matched (slave mode)
  • SMBUS_FLAG_AF: NACK received flag
  • SMBUS_FLAG_STOPF: STOP detection flag
  • SMBUS_FLAG_BERR: Bus error
  • SMBUS_FLAG_ARLO: Arbitration lost
  • SMBUS_FLAG_OVR: Overrun/Underrun
  • SMBUS_FLAG_PECERR: PEC error in reception
  • SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag
  • SMBUS_FLAG_ALERT: SMBus alert
Return values:
None

Definition at line 470 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EnableAlert_IT(), HAL_SMBUS_ER_IRQHandler(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define __HAL_SMBUS_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Disable the specified SMBUS peripheral.

Parameters:
__HANDLE__,: specifies the SMBUS Handle.
Return values:
None

Definition at line 482 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), and SMBUS_Master_ISR().

#define __HAL_SMBUS_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))

Disable the specified SMBUS interrupts.

Parameters:
__HANDLE__,: specifies the SMBUS Handle.
__INTERRUPT__,: specifies the interrupt source to disable. This parameter can be one of the following values:
  • SMBUS_IT_ERRI: Errors interrupt enable
  • SMBUS_IT_TCI: Transfer complete interrupt enable
  • SMBUS_IT_STOPI: STOP detection interrupt enable
  • SMBUS_IT_NACKI: NACK received interrupt enable
  • SMBUS_IT_ADDRI: Address match interrupt enable
  • SMBUS_IT_RXI: RX interrupt enable
  • SMBUS_IT_TXI: TX interrupt enable
Return values:
None

Definition at line 410 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_Disable_IRQ(), and SMBUS_Slave_ISR().

#define __HAL_SMBUS_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Enable the specified SMBUS peripheral.

Parameters:
__HANDLE__,: specifies the SMBUS Handle.
Return values:
None

Definition at line 476 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), and SMBUS_Master_ISR().

#define __HAL_SMBUS_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))

Enable the specified SMBUS interrupts.

Parameters:
__HANDLE__,: specifies the SMBUS Handle.
__INTERRUPT__,: specifies the interrupt source to enable. This parameter can be one of the following values:
  • SMBUS_IT_ERRI: Errors interrupt enable
  • SMBUS_IT_TCI: Transfer complete interrupt enable
  • SMBUS_IT_STOPI: STOP detection interrupt enable
  • SMBUS_IT_NACKI: NACK received interrupt enable
  • SMBUS_IT_ADDRI: Address match interrupt enable
  • SMBUS_IT_RXI: RX interrupt enable
  • SMBUS_IT_TXI: TX interrupt enable
Return values:
None

Definition at line 394 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_Enable_IRQ().

#define __HAL_SMBUS_GENERATE_NACK ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))

Generate a Non-Acknowledge SMBUS peripheral in Slave mode.

Parameters:
__HANDLE__,: specifies the SMBUS Handle.
Return values:
None

Definition at line 488 of file stm32h7xx_hal_smbus.h.

#define __HAL_SMBUS_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))

Definition at line 452 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler(), HAL_SMBUS_IsDeviceReady(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

#define __HAL_SMBUS_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SMBUS interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the SMBUS Handle.
__INTERRUPT__,: specifies the SMBUS interrupt source to check. This parameter can be one of the following values:
  • SMBUS_IT_ERRI: Errors interrupt enable
  • SMBUS_IT_TCI: Transfer complete interrupt enable
  • SMBUS_IT_STOPI: STOP detection interrupt enable
  • SMBUS_IT_NACKI: NACK received interrupt enable
  • SMBUS_IT_ADDRI: Address match interrupt enable
  • SMBUS_IT_RXI: RX interrupt enable
  • SMBUS_IT_TXI: TX interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 426 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler(), and HAL_SMBUS_EV_IRQHandler().

#define __HAL_SMBUS_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)

Reset SMBUS handle state.

Parameters:
__HANDLE__,: specifies the SMBUS Handle.
Return values:
None

Definition at line 378 of file stm32h7xx_hal_smbus.h.

#define SMBUS_FLAG_MASK (0x0001FFFFU)

Check whether the specified SMBUS flag is set or not.

Parameters:
__HANDLE__,: specifies the SMBUS Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SMBUS_FLAG_TXE: Transmit data register empty
  • SMBUS_FLAG_TXIS: Transmit interrupt status
  • SMBUS_FLAG_RXNE: Receive data register not empty
  • SMBUS_FLAG_ADDR: Address matched (slave mode)
  • SMBUS_FLAG_AF: NACK received flag
  • SMBUS_FLAG_STOPF: STOP detection flag
  • SMBUS_FLAG_TC: Transfer complete (master mode)
  • SMBUS_FLAG_TCR: Transfer complete reload
  • SMBUS_FLAG_BERR: Bus error
  • SMBUS_FLAG_ARLO: Arbitration lost
  • SMBUS_FLAG_OVR: Overrun/Underrun
  • SMBUS_FLAG_PECERR: PEC error in reception
  • SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag
  • SMBUS_FLAG_ALERT: SMBus alert
  • SMBUS_FLAG_BUSY: Bus busy
  • SMBUS_FLAG_DIR: Transfer direction (slave mode)
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 451 of file stm32h7xx_hal_smbus.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMBUS Private Macros

Defines
SMBUS Private Macros
SMBUS

Defines

#define | IS_SMBUS_ANALOG_FILTER(FILTER)
#define | IS_SMBUS_ADDRESSING_MODE(MODE)
#define | IS_SMBUS_DUAL_ADDRESS(ADDRESS)
#define | IS_SMBUS_OWN_ADDRESS2_MASK(MASK)
#define | IS_SMBUS_GENERAL_CALL(CALL)
#define | IS_SMBUS_NO_STRETCH(STRETCH)
#define | IS_SMBUS_PEC(PEC)
#define | IS_SMBUS_PERIPHERAL_MODE(MODE)
#define | IS_SMBUS_TRANSFER_MODE(MODE)
#define | IS_SMBUS_TRANSFER_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)
#define | SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
#define | SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | SMBUS_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)
#define | SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
#define | SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define | SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
#define | SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
#define | SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
#define | IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)

Define Documentation

#define IS_SMBUS_ADDRESSING_MODE ( MODE )
Value:
(((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
                                                          ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))

Definition at line 505 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_ANALOG_FILTER ( FILTER )
Value:
(((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
                                                          ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))

Definition at line 502 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_DUAL_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
                                                          ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))

Definition at line 508 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_GENERAL_CALL ( CALL )
Value:
(((CALL) == SMBUS_GENERALCALL_DISABLE) || \
                                                         ((CALL) == SMBUS_GENERALCALL_ENABLE))

Definition at line 520 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_NO_STRETCH ( STRETCH )
Value:
(((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
                                                         ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))

Definition at line 523 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_OWN_ADDRESS1 ( ADDRESS1 ) ((ADDRESS1) <= 0x000003FFU)

Definition at line 577 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_OWN_ADDRESS2 ( ADDRESS2 ) ((ADDRESS2) <= (uint16_t)0x00FFU)

Definition at line 578 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_OWN_ADDRESS2_MASK ( MASK )
Value:
(((MASK) == SMBUS_OA2_NOMASK)    || \
                                                         ((MASK) == SMBUS_OA2_MASK01)    || \
                                                         ((MASK) == SMBUS_OA2_MASK02)    || \
                                                         ((MASK) == SMBUS_OA2_MASK03)    || \
                                                         ((MASK) == SMBUS_OA2_MASK04)    || \
                                                         ((MASK) == SMBUS_OA2_MASK05)    || \
                                                         ((MASK) == SMBUS_OA2_MASK06)    || \
                                                         ((MASK) == SMBUS_OA2_MASK07))

Definition at line 511 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_PEC ( PEC )
Value:
(((PEC) == SMBUS_PEC_DISABLE) || \
                                                          ((PEC) == SMBUS_PEC_ENABLE))

Definition at line 526 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_PERIPHERAL_MODE ( MODE )
Value:
(((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)    || \
                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))

Definition at line 529 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_TRANSFER_MODE ( MODE )
Value:
(((MODE) == SMBUS_RELOAD_MODE)                           || \
                                                          ((MODE) == SMBUS_AUTOEND_MODE)                         || \
                                                          ((MODE) == SMBUS_SOFTEND_MODE)                         || \
                                                          ((MODE) == SMBUS_SENDPEC_MODE)                         || \
                                                          ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))

Definition at line 533 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_TransferConfig().

#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == SMBUS_FIRST_FRAME)                        || \
                                                          ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
                                                          ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
                                                          ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
                                                          ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
                                                          ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)               || \
                                                          IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))

Definition at line 549 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)                || \
                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)       || \
                                                          ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)              || \
                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))

Definition at line 557 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), and HAL_SMBUS_Master_Transmit_IT().

#define IS_SMBUS_TRANSFER_REQUEST ( REQUEST )
Value:
(((REQUEST) == SMBUS_GENERATE_STOP)              || \
                                                          ((REQUEST) == SMBUS_GENERATE_START_READ)       || \
                                                          ((REQUEST) == SMBUS_GENERATE_START_WRITE)      || \
                                                          ((REQUEST) == SMBUS_NO_STARTSTOP))

Definition at line 543 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_TransferConfig().

#define SMBUS_CHECK_FLAG | ( | __ISR__,
 |  | __FLAG__
 | ) | ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))

Definition at line 575 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler().

#define SMBUS_GENERATE_START | ( | __ADDMODE__,
 |  | __ADDRESS__
 | ) |
Value:
(((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
                                                                  (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))

Definition at line 565 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady().

#define SMBUS_GET_ADDR_MATCH ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)

Definition at line 568 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_Slave_ISR().

#define SMBUS_GET_ALERT_ENABLED ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)

Definition at line 572 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_Disable_IRQ().

#define SMBUS_GET_DIR ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)

Definition at line 569 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_Slave_ISR().

#define SMBUS_GET_ISR_REG ( __HANDLE__ ) ((__HANDLE__)->Instance->ISR)

Definition at line 574 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler().

#define SMBUS_GET_PEC_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)

Definition at line 571 of file stm32h7xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_GET_STOP_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)

Definition at line 570 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_Master_ISR().

#define SMBUS_RESET_CR1 ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))

Definition at line 562 of file stm32h7xx_hal_smbus.h.

#define SMBUS_RESET_CR2 ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))

Definition at line 563 of file stm32h7xx_hal_smbus.h.

Referenced by SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SPDIFRX Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SPDIFRX_Init (SPDIFRX_HandleTypeDef *hspdif)
Initializes the SPDIFRX according to the specified parameters in the SPDIFRX_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif)
DeInitializes the SPDIFRX peripheral.
__weak void | HAL_SPDIFRX_MspInit (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX MSP Init.
__weak void | HAL_SPDIFRX_MspDeInit (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX MSP DeInit.
HAL_StatusTypeDef | HAL_SPDIFRX_SetDataFormat (SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)
Sets the SPDIFRX dtat format according to the specified parameters in the SPDIFRX_InitTypeDef.

Detailed Description

Initialization and Configuration functions.

  ===============================================================================
  ##### Initialization and de-initialization functions #####
  ===============================================================================
  [..]  This subsection provides a set of functions allowing to initialize and
        de-initialize the SPDIFRX peripheral:

  (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures
      all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

  (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with
      the selected configuration:
  (++) Input Selection (IN0, IN1,...)
  (++) Maximum allowed re-tries during synchronization phase
  (++) Wait for activity on SPDIF selected input
  (++) Channel status selection (from channel A or B)
  (++) Data format (LSB, MSB, ...)
  (++) Stereo mode
  (++) User bits masking (PT,C,U,V,...)

  (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration
      of the selected SPDIFRXx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SPDIFRX_DeInit ( SPDIFRX_HandleTypeDef * hspdif )

DeInitializes the SPDIFRX peripheral.

Parameters:
hspdif,: SPDIFRX handle
Return values:
HAL status

Definition at line 271 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_IDLE, assert_param, SPDIFRX_HandleTypeDef::ErrorCode, HAL_SPDIFRX_ERROR_NONE, HAL_SPDIFRX_MspDeInit(), HAL_SPDIFRX_STATE_BUSY, HAL_SPDIFRX_STATE_RESET, SPDIFRX_HandleTypeDef::Instance, and SPDIFRX_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPDIFRX_Init ( SPDIFRX_HandleTypeDef * hspdif )

Initializes the SPDIFRX according to the specified parameters in the SPDIFRX_InitTypeDef and create the associated handle.

Parameters:
hspdif,: SPDIFRX handle
Return values:
HAL status

Definition at line 201 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_IDLE, assert_param, SPDIFRX_InitTypeDef::ChannelSelection, SPDIFRX_InitTypeDef::ChannelStatusMask, SPDIFRX_InitTypeDef::DataFormat, SPDIFRX_HandleTypeDef::ErrorCode, HAL_SPDIFRX_ERROR_NONE, HAL_SPDIFRX_MspInit(), HAL_SPDIFRX_STATE_BUSY, HAL_SPDIFRX_STATE_READY, HAL_SPDIFRX_STATE_RESET, SPDIFRX_HandleTypeDef::Init, SPDIFRX_InitTypeDef::InputSelection, SPDIFRX_HandleTypeDef::Instance, IS_CHANNEL_STATUS_MASK, IS_PARITY_ERROR_MASK, IS_PREAMBLE_TYPE_MASK, IS_SPDIFRX_CHANNEL, IS_SPDIFRX_DATA_FORMAT, IS_SPDIFRX_INPUT_SELECT, IS_SPDIFRX_MAX_RETRIES, IS_SPDIFRX_WAIT_FOR_ACTIVITY, IS_STEREO_MODE, IS_VALIDITY_MASK, SPDIFRX_HandleTypeDef::Lock, SPDIFRX_InitTypeDef::ParityErrorMask, SPDIFRX_InitTypeDef::PreambleTypeMask, SPDIFRX_InitTypeDef::Retries, SPDIFRX_HandleTypeDef::State, SPDIFRX_InitTypeDef::StereoMode, SPDIFRX_InitTypeDef::ValidityBitMask, and SPDIFRX_InitTypeDef::WaitForActivity.

void HAL_SPDIFRX_MspDeInit ( SPDIFRX_HandleTypeDef * hspdif )

SPDIFRX MSP DeInit.

Parameters:
hspdif,: SPDIFRX handle
Return values:
None

Definition at line 321 of file stm32h7xx_hal_spdifrx.c.

Referenced by HAL_SPDIFRX_DeInit().

void HAL_SPDIFRX_MspInit ( SPDIFRX_HandleTypeDef * hspdif )

SPDIFRX MSP Init.

Parameters:
hspdif,: SPDIFRX handle
Return values:
None

Definition at line 306 of file stm32h7xx_hal_spdifrx.c.

Referenced by HAL_SPDIFRX_Init().

HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | SPDIFRX_SetDataFormatTypeDef | sDataFormat
 | ) |  |

Sets the SPDIFRX dtat format according to the specified parameters in the SPDIFRX_InitTypeDef.

Parameters:
hspdif,: SPDIFRX handle
sDataFormat,: SPDIFRX data format
Return values:
HAL status

Definition at line 338 of file stm32h7xx_hal_spdifrx.c.

References assert_param, SPDIFRX_SetDataFormatTypeDef::ChannelStatusMask, SPDIFRX_SetDataFormatTypeDef::DataFormat, SPDIFRX_HandleTypeDef::Instance, IS_CHANNEL_STATUS_MASK, IS_PARITY_ERROR_MASK, IS_PREAMBLE_TYPE_MASK, IS_SPDIFRX_DATA_FORMAT, IS_STEREO_MODE, IS_VALIDITY_MASK, SPDIFRX_SetDataFormatTypeDef::ParityErrorMask, SPDIFRX_SetDataFormatTypeDef::PreambleTypeMask, SPDIFRX_STATE_RCV, SPDIFRX_SetDataFormatTypeDef::StereoMode, and SPDIFRX_SetDataFormatTypeDef::ValidityBitMask.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
SPDIFRX Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data (Data Flow) in blocking mode.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveControlFlow (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data (Control Flow) in blocking mode.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow_IT (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Data Flow) in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveControlFlow_IT (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Control Flow) with Interrupt.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow_DMA (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Data Flow) mode with DMA.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveControlFlow_DMA (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Control Flow) with DMA.
HAL_StatusTypeDef | HAL_SPDIFRX_DMAStop (SPDIFRX_HandleTypeDef *hspdif)
stop the audio stream receive from the Media.
void | HAL_SPDIFRX_IRQHandler (SPDIFRX_HandleTypeDef *hspdif)
This function handles SPDIFRX interrupt request.
__weak void | HAL_SPDIFRX_RxHalfCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Data flow) half completed callbacks.
__weak void | HAL_SPDIFRX_RxCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Data flow) completed callbacks.
__weak void | HAL_SPDIFRX_CxHalfCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx (Control flow) Transfer half completed callbacks.
__weak void | HAL_SPDIFRX_CxCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Control flow) completed callbacks.
__weak void | HAL_SPDIFRX_ErrorCallback (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX error callbacks.

Detailed Description

Data transfers functions.

===============================================================================
                     ##### IO operation functions #####
===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the SPDIFRX data
    transfers.

    (#) There is two mode of transfer:
        (++) Blocking mode : The communication is performed in the polling mode.
             The status of all data processing is returned by the same function
             after finishing transfer.
        (++) No-Blocking mode : The communication is performed using Interrupts
             or DMA. These functions return the status of the transfer start-up.
             The end of the data processing will be indicated through the
             dedicated SPDIFRX IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_SPDIFRX_ReceiveDataFlow()
        (++) HAL_SPDIFRX_ReceiveControlFlow()
                (+@) Do not use blocking mode to receive both control and data flow at the same time.

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_SPDIFRX_ReceiveControlFlow_IT()
        (++) HAL_SPDIFRX_ReceiveDataFlow_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_SPDIFRX_ReceiveControlFlow_DMA()
        (++) HAL_SPDIFRX_ReceiveDataFlow_DMA()

    (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
        (++) HAL_SPDIFRX_RxCpltCallback()
        (++) HAL_SPDIFRX_ErrorCallback()

Function Documentation

void HAL_SPDIFRX_CxCpltCallback ( SPDIFRX_HandleTypeDef * hspdif )

Rx Transfer (Control flow) completed callbacks.

Parameters:
hspdif,: SPDIFRX handle
Return values:
None

Definition at line 976 of file stm32h7xx_hal_spdifrx.c.

Referenced by SPDIFRX_DMACxCplt(), and SPDIFRX_ReceiveControlFlow_IT().

void HAL_SPDIFRX_CxHalfCpltCallback ( SPDIFRX_HandleTypeDef * hspdif )

Rx (Control flow) Transfer half completed callbacks.

Parameters:
hspdif,: SPDIFRX handle
Return values:
None

Definition at line 961 of file stm32h7xx_hal_spdifrx.c.

Referenced by SPDIFRX_DMACxHalfCplt().

HAL_StatusTypeDef HAL_SPDIFRX_DMAStop ( SPDIFRX_HandleTypeDef * hspdif )

stop the audio stream receive from the Media.

Parameters:
hspdif,: SPDIFRX handle
Return values:
None

Definition at line 856 of file stm32h7xx_hal_spdifrx.c.

References __HAL_DMA_DISABLE, __HAL_SPDIFRX_IDLE, HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::hdmaCsRx, SPDIFRX_HandleTypeDef::hdmaDrRx, SPDIFRX_HandleTypeDef::Instance, and SPDIFRX_HandleTypeDef::State.

void HAL_SPDIFRX_ErrorCallback ( SPDIFRX_HandleTypeDef * hspdif )

SPDIFRX error callbacks.

Parameters:
hspdif,: SPDIFRX handle
Return values:
None

Definition at line 991 of file stm32h7xx_hal_spdifrx.c.

Referenced by HAL_SPDIFRX_IRQHandler(), and SPDIFRX_DMAError().

void HAL_SPDIFRX_IRQHandler ( SPDIFRX_HandleTypeDef * hspdif )

This function handles SPDIFRX interrupt request.

Parameters:
hspdif,: SPDIFRX handle
Return values:
HAL status

Definition at line 885 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_CLEAR_IT, __HAL_SPDIFRX_GET_FLAG, __HAL_SPDIFRX_GET_IT_SOURCE, SPDIFRX_HandleTypeDef::ErrorCode, HAL_SPDIFRX_ERROR_OVR, HAL_SPDIFRX_ERROR_PE, HAL_SPDIFRX_ErrorCallback(), SPDIFRX_FLAG_CSRNE, SPDIFRX_FLAG_OVR, SPDIFRX_FLAG_PERR, SPDIFRX_FLAG_RXNE, SPDIFRX_IT_CSRNE, SPDIFRX_IT_OVRIE, SPDIFRX_IT_PERRIE, SPDIFRX_IT_RXNE, SPDIFRX_ReceiveControlFlow_IT(), and SPDIFRX_ReceiveDataFlow_IT().

HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | uint32_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receives an amount of data (Control Flow) in blocking mode.

Parameters:
hspdif,: pointer to a SPDIFRX_HandleTypeDef structure that contains the configuration information for SPDIFRX module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 508 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_RCV, __HAL_SPDIFRX_SYNC, HAL_GetTick(), HAL_SPDIFRX_STATE_BUSY, HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::Instance, SPDIFRX_FLAG_CSRNE, SPDIFRX_FLAG_SYNCD, SPDIFRX_WaitOnFlagUntilTimeout(), and SPDIFRX_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data (Control Flow) with DMA.

Parameters:
hspdif,: SPDIFRX handle
pData,: a 32-bit pointer to the Receive data buffer.
Size,: number of data (Control Flow) sample to be received :
Return values:
HAL status

Definition at line 786 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_RCV, __HAL_SPDIFRX_SYNC, SPDIFRX_HandleTypeDef::CsXferCount, SPDIFRX_HandleTypeDef::CsXferSize, SPDIFRX_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_GetTick(), HAL_SPDIFRX_ERROR_NONE, HAL_SPDIFRX_STATE_BUSY_CX, HAL_SPDIFRX_STATE_BUSY_RX, HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::hdmaCsRx, SPDIFRX_HandleTypeDef::Instance, SPDIFRX_HandleTypeDef::pCsBuffPtr, SPDIFRX_DMACxCplt(), SPDIFRX_DMACxHalfCplt(), SPDIFRX_DMAError(), SPDIFRX_FLAG_SYNCD, SPDIFRX_STATE_SYNC, SPDIFRX_TIMEOUT_VALUE, SPDIFRX_WaitOnFlagUntilTimeout(), SPDIFRX_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data (Control Flow) with Interrupt.

Parameters:
hspdif,: SPDIFRX handle
pData,: a 32-bit pointer to the Receive data buffer.
Size,: number of data sample (Control Flow) to be received :
Return values:
HAL status

Definition at line 645 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_ENABLE_IT, __HAL_SPDIFRX_RCV, __HAL_SPDIFRX_SYNC, SPDIFRX_HandleTypeDef::CsXferCount, SPDIFRX_HandleTypeDef::CsXferSize, SPDIFRX_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPDIFRX_ERROR_NONE, HAL_SPDIFRX_STATE_BUSY_CX, HAL_SPDIFRX_STATE_BUSY_RX, HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::pCsBuffPtr, SPDIFRX_FLAG_SYNCD, SPDIFRX_IT_CSRNE, SPDIFRX_IT_OVRIE, SPDIFRX_IT_PERRIE, SPDIFRX_STATE_SYNC, SPDIFRX_TIMEOUT_VALUE, SPDIFRX_WaitOnFlagUntilTimeout(), and SPDIFRX_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | uint32_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receives an amount of data (Data Flow) in blocking mode.

Parameters:
hspdif,: pointer to SPDIFRX_HandleTypeDef structure that contains the configuration information for SPDIFRX module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 438 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_RCV, __HAL_SPDIFRX_SYNC, HAL_GetTick(), HAL_SPDIFRX_STATE_BUSY, HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::Instance, SPDIFRX_FLAG_RXNE, SPDIFRX_FLAG_SYNCD, SPDIFRX_WaitOnFlagUntilTimeout(), and SPDIFRX_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data (Data Flow) mode with DMA.

Parameters:
hspdif,: SPDIFRX handle
pData,: a 32-bit pointer to the Receive data buffer.
Size,: number of data sample to be received :
Return values:
HAL status

Definition at line 714 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_RCV, __HAL_SPDIFRX_SYNC, SPDIFRX_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_GetTick(), HAL_SPDIFRX_ERROR_NONE, HAL_SPDIFRX_STATE_BUSY_CX, HAL_SPDIFRX_STATE_BUSY_RX, HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::hdmaDrRx, SPDIFRX_HandleTypeDef::Instance, SPDIFRX_HandleTypeDef::pRxBuffPtr, SPDIFRX_HandleTypeDef::RxXferCount, SPDIFRX_HandleTypeDef::RxXferSize, SPDIFRX_DMAError(), SPDIFRX_DMARxCplt(), SPDIFRX_DMARxHalfCplt(), SPDIFRX_FLAG_SYNCD, SPDIFRX_STATE_SYNC, SPDIFRX_TIMEOUT_VALUE, SPDIFRX_WaitOnFlagUntilTimeout(), SPDIFRX_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data (Data Flow) in non-blocking mode with Interrupt.

Parameters:
hspdif,: SPDIFRX handle
pData,: a 32-bit pointer to the Receive data buffer.
Size,: number of data sample to be received .
Return values:
HAL status

Definition at line 576 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_ENABLE_IT, __HAL_SPDIFRX_RCV, __HAL_SPDIFRX_SYNC, SPDIFRX_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPDIFRX_ERROR_NONE, HAL_SPDIFRX_STATE_BUSY_CX, HAL_SPDIFRX_STATE_BUSY_RX, HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::pRxBuffPtr, SPDIFRX_HandleTypeDef::RxXferCount, SPDIFRX_HandleTypeDef::RxXferSize, SPDIFRX_FLAG_SYNCD, SPDIFRX_IT_OVRIE, SPDIFRX_IT_PERRIE, SPDIFRX_IT_RXNE, SPDIFRX_STATE_SYNC, SPDIFRX_TIMEOUT_VALUE, SPDIFRX_WaitOnFlagUntilTimeout(), and SPDIFRX_HandleTypeDef::State.

void HAL_SPDIFRX_RxCpltCallback ( SPDIFRX_HandleTypeDef * hspdif )

Rx Transfer (Data flow) completed callbacks.

Parameters:
hspdif,: SPDIFRX handle
Return values:
None

Definition at line 946 of file stm32h7xx_hal_spdifrx.c.

Referenced by SPDIFRX_DMARxCplt(), and SPDIFRX_ReceiveDataFlow_IT().

void HAL_SPDIFRX_RxHalfCpltCallback ( SPDIFRX_HandleTypeDef * hspdif )

Rx Transfer (Data flow) half completed callbacks.

Parameters:
hspdif,: SPDIFRX handle
Return values:
None

Definition at line 931 of file stm32h7xx_hal_spdifrx.c.

Referenced by SPDIFRX_DMARxHalfCplt().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SPDIFRX Exported Functions

Peripheral State functions. More...

Functions

HAL_SPDIFRX_StateTypeDef | HAL_SPDIFRX_GetState (SPDIFRX_HandleTypeDef *hspdif)
Return the SPDIFRX state.
uint32_t | HAL_SPDIFRX_GetError (SPDIFRX_HandleTypeDef *hspdif)
Return the SPDIFRX error code.

Detailed Description

Peripheral State functions.

===============================================================================
##### Peripheral State and Errors functions #####
===============================================================================
[..]
This subsection permit to get in run-time the status of the peripheral
and the data flow.

Function Documentation

uint32_t HAL_SPDIFRX_GetError ( SPDIFRX_HandleTypeDef * hspdif )

Return the SPDIFRX error code.

Parameters:
hspdif : SPDIFRX handle
Return values:
SPDIFRX Error Code

Definition at line 1035 of file stm32h7xx_hal_spdifrx.c.

References SPDIFRX_HandleTypeDef::ErrorCode.

HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState ( SPDIFRX_HandleTypeDef * hspdif )

Return the SPDIFRX state.

Parameters:
hspdif : SPDIFRX handle
Return values:
HAL state

Definition at line 1025 of file stm32h7xx_hal_spdifrx.c.

References SPDIFRX_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPDIFRX Exported Functions

Modules | Functions
SPDIFRX Exported Functions
SPDIFRX

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State and Errors functions

Peripheral State functions.

Functions

static void | SPDIFRX_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Data flow) complete callback.
static void | SPDIFRX_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Data flow) half complete callback.
static void | SPDIFRX_DMACxCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Control flow) complete callback.
static void | SPDIFRX_DMACxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Control flow) half complete callback.
static void | SPDIFRX_DMAError (DMA_HandleTypeDef *hdma)
DMA SPDIFRX communication error callback.
static void | SPDIFRX_ReceiveDataFlow_IT (SPDIFRX_HandleTypeDef *hspdif)
Receive an amount of data (Data Flow) with Interrupt.
static void | SPDIFRX_ReceiveControlFlow_IT (SPDIFRX_HandleTypeDef *hspdif)
Receive an amount of data (Control Flow) with Interrupt.
static HAL_StatusTypeDef | SPDIFRX_WaitOnFlagUntilTimeout (SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart)
This function handles SPDIFRX Communication Timeout.

Function Documentation

static void SPDIFRX_DMACxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPDIFRX receive process (Control flow) complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 1081 of file stm32h7xx_hal_spdifrx.c.

References SPDIFRX_HandleTypeDef::CsXferCount, HAL_SPDIFRX_CxCpltCallback(), HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::Instance, and SPDIFRX_HandleTypeDef::State.

Referenced by HAL_SPDIFRX_ReceiveControlFlow_DMA().

static void SPDIFRX_DMACxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPDIFRX receive process (Control flow) half complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 1098 of file stm32h7xx_hal_spdifrx.c.

References HAL_SPDIFRX_CxHalfCpltCallback().

Referenced by HAL_SPDIFRX_ReceiveControlFlow_DMA().

static void SPDIFRX_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SPDIFRX communication error callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 1110 of file stm32h7xx_hal_spdifrx.c.

References SPDIFRX_HandleTypeDef::ErrorCode, HAL_SPDIFRX_ERROR_DMA, HAL_SPDIFRX_ErrorCallback(), HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::Instance, SPDIFRX_HandleTypeDef::RxXferCount, and SPDIFRX_HandleTypeDef::State.

Referenced by HAL_SPDIFRX_ReceiveControlFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_DMA().

static void SPDIFRX_DMARxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPDIFRX receive process (Data flow) complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 1049 of file stm32h7xx_hal_spdifrx.c.

References DMA_CIRCULAR, HAL_SPDIFRX_RxCpltCallback(), HAL_SPDIFRX_STATE_READY, __DMA_HandleTypeDef::Init, SPDIFRX_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, SPDIFRX_HandleTypeDef::RxXferCount, and SPDIFRX_HandleTypeDef::State.

Referenced by HAL_SPDIFRX_ReceiveDataFlow_DMA().

static void SPDIFRX_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPDIFRX receive process (Data flow) half complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 1068 of file stm32h7xx_hal_spdifrx.c.

References HAL_SPDIFRX_RxHalfCpltCallback().

Referenced by HAL_SPDIFRX_ReceiveDataFlow_DMA().

static void SPDIFRX_ReceiveControlFlow_IT ( SPDIFRX_HandleTypeDef * hspdif ) [static]

Receive an amount of data (Control Flow) with Interrupt.

Parameters:
hspdif,: SPDIFRX handle
Return values:
None

Definition at line 1155 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_DISABLE_IT, SPDIFRX_HandleTypeDef::CsXferCount, HAL_SPDIFRX_CxCpltCallback(), HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::Instance, SPDIFRX_HandleTypeDef::pCsBuffPtr, SPDIFRX_IT_CSRNE, and SPDIFRX_HandleTypeDef::State.

Referenced by HAL_SPDIFRX_IRQHandler().

static void SPDIFRX_ReceiveDataFlow_IT ( SPDIFRX_HandleTypeDef * hspdif ) [static]

Receive an amount of data (Data Flow) with Interrupt.

Parameters:
hspdif,: SPDIFRX handle
Return values:
None

Definition at line 1130 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_DISABLE_IT, HAL_SPDIFRX_RxCpltCallback(), HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::Instance, SPDIFRX_HandleTypeDef::pRxBuffPtr, SPDIFRX_HandleTypeDef::RxXferCount, SPDIFRX_IT_OVRIE, SPDIFRX_IT_PERRIE, SPDIFRX_IT_RXNE, and SPDIFRX_HandleTypeDef::State.

Referenced by HAL_SPDIFRX_IRQHandler().

static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout,
 |  | uint32_t | tickstart
 | ) |  | [static]

This function handles SPDIFRX Communication Timeout.

Parameters:
hspdif,: SPDIFRX handle
Flag,: Flag checked
Status,: Value of the flag expected
Timeout,: Duration of the timeout
tickstart,: Tick start value
Return values:
HAL status

Definition at line 1184 of file stm32h7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_DISABLE_IT, __HAL_SPDIFRX_GET_FLAG, HAL_GetTick(), HAL_SPDIFRX_STATE_READY, SPDIFRX_IT_CSRNE, SPDIFRX_IT_IFEIE, SPDIFRX_IT_OVRIE, SPDIFRX_IT_PERRIE, SPDIFRX_IT_RXNE, SPDIFRX_IT_SBLKIE, SPDIFRX_IT_SYNCDIE, and SPDIFRX_HandleTypeDef::State.

Referenced by HAL_SPDIFRX_ReceiveControlFlow(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPDIFRX Exported Types

Data Structures | Enumerations
SPDIFRX Exported Types
SPDIFRX

Data Structures

struct | SPDIFRX_InitTypeDef
SPDIFRX Init structure definition. More...
struct | SPDIFRX_SetDataFormatTypeDef
SPDIFRX SetDataFormat structure definition. More...
struct | SPDIFRX_HandleTypeDef
SPDIFRX handle Structure definition. More...

Enumerations

enum HAL_SPDIFRX_StateTypeDef {
HAL_SPDIFRX_STATE_RESET = 0x00U, HAL_SPDIFRX_STATE_READY = 0x01U, HAL_SPDIFRX_STATE_BUSY = 0x02U, HAL_SPDIFRX_STATE_BUSY_RX = 0x03U,
HAL_SPDIFRX_STATE_BUSY_CX = 0x04U, HAL_SPDIFRX_STATE_ERROR = 0x07U
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_SPDIFRX_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_SPDIFRX_STATE_RESET

SPDIFRX not yet initialized or disabled

HAL_SPDIFRX_STATE_READY

SPDIFRX initialized and ready for use

HAL_SPDIFRX_STATE_BUSY

SPDIFRX internal process is ongoing

HAL_SPDIFRX_STATE_BUSY_RX

SPDIFRX internal Data Flow RX process is ongoing

HAL_SPDIFRX_STATE_BUSY_CX

SPDIFRX internal Control Flow RX process is ongoing

HAL_SPDIFRX_STATE_ERROR

SPDIFRX error state

Definition at line 128 of file stm32h7xx_hal_spdifrx.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPDIFRX_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SPDIFRX_InitTypeDef Struct Reference
SPDIFRX Exported Types

SPDIFRX Init structure definition. More...

#include <stm32h7xx_hal_spdifrx.h>

Data Fields

uint32_t | InputSelection
uint32_t | Retries
uint32_t | WaitForActivity
uint32_t | ChannelSelection
uint32_t | DataFormat
uint32_t | StereoMode
uint32_t | PreambleTypeMask
uint32_t | ChannelStatusMask
uint32_t | ValidityBitMask
uint32_t | ParityErrorMask

Detailed Description

SPDIFRX Init structure definition.

Definition at line 66 of file stm32h7xx_hal_spdifrx.h.

Field Documentation

uint32_t SPDIFRX_InitTypeDef::ChannelSelection

Specifies whether the control flow will take the channel status from channel A or B. This parameter can be a value of SPDIFRX Channel Selection

Definition at line 77 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::ChannelStatusMask

Specifies whether the channel status and user bits are copied or not into the received frame. This parameter can be a value of SPDIFRX Channel Status Mask

Definition at line 89 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::DataFormat

Specifies the Data samples format (LSB, MSB, ...). This parameter can be a value of SPDIFRX Data Format

Definition at line 80 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::InputSelection

Specifies the SPDIF input selection. This parameter can be a value of SPDIFRX Input Selection

Definition at line 68 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::ParityErrorMask

Specifies whether the parity error bit is copied or not into the received frame. This parameter can be a value of SPDIFRX Parity Error Mask

Definition at line 95 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::PreambleTypeMask

Specifies whether The preamble type bits are copied or not into the received frame. This parameter can be a value of SPDIFRX Preamble Type Mask

Definition at line 86 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::Retries

Specifies the Maximum allowed re-tries during synchronization phase. This parameter can be a value of SPDIFRX Maximum Retries

Definition at line 71 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::StereoMode

Specifies whether the peripheral is in stereo or mono mode. This parameter can be a value of SPDIFRX Stereo Mode

Definition at line 83 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::ValidityBitMask

Specifies whether the validity bit is copied or not into the received frame. This parameter can be a value of SPDIFRX Validity Mask

Definition at line 92 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::WaitForActivity

Specifies the wait for activity on SPDIF selected input. This parameter can be a value of SPDIFRX Wait For Activity.

Definition at line 74 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_spdifrx.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPDIFRX_SetDataFormatTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SPDIFRX_SetDataFormatTypeDef Struct Reference
SPDIFRX Exported Types

SPDIFRX SetDataFormat structure definition. More...

#include <stm32h7xx_hal_spdifrx.h>

Data Fields

uint32_t | DataFormat
uint32_t | StereoMode
uint32_t | PreambleTypeMask
uint32_t | ChannelStatusMask
uint32_t | ValidityBitMask
uint32_t | ParityErrorMask

Detailed Description

SPDIFRX SetDataFormat structure definition.

Definition at line 103 of file stm32h7xx_hal_spdifrx.h.

Field Documentation

uint32_t SPDIFRX_SetDataFormatTypeDef::ChannelStatusMask

Specifies whether the channel status and user bits are copied or not into the received frame. This parameter can be a value of SPDIFRX Channel Status Mask

Definition at line 114 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_SetDataFormat().

uint32_t SPDIFRX_SetDataFormatTypeDef::DataFormat

Specifies the Data samples format (LSB, MSB, ...). This parameter can be a value of SPDIFRX Data Format

Definition at line 105 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_SetDataFormat().

uint32_t SPDIFRX_SetDataFormatTypeDef::ParityErrorMask

Specifies whether the parity error bit is copied or not into the received frame. This parameter can be a value of SPDIFRX Parity Error Mask

Definition at line 120 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_SetDataFormat().

uint32_t SPDIFRX_SetDataFormatTypeDef::PreambleTypeMask

Specifies whether The preamble type bits are copied or not into the received frame. This parameter can be a value of SPDIFRX Preamble Type Mask

Definition at line 111 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_SetDataFormat().

uint32_t SPDIFRX_SetDataFormatTypeDef::StereoMode

Specifies whether the peripheral is in stereo or mono mode. This parameter can be a value of SPDIFRX Stereo Mode

Definition at line 108 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_SetDataFormat().

uint32_t SPDIFRX_SetDataFormatTypeDef::ValidityBitMask

Specifies whether the validity bit is copied or not into the received frame. This parameter can be a value of SPDIFRX Validity Mask

Definition at line 117 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_SetDataFormat().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_spdifrx.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPDIFRX_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SPDIFRX_HandleTypeDef Struct Reference
SPDIFRX Exported Types

SPDIFRX handle Structure definition. More...

#include <stm32h7xx_hal_spdifrx.h>

Data Fields

SPDIFRX_TypeDef * | Instance
SPDIFRX_InitTypeDef Init
uint32_t * | pRxBuffPtr
uint32_t * | pCsBuffPtr
__IO uint16_t | RxXferSize
__IO uint16_t | RxXferCount
__IO uint16_t | CsXferSize
__IO uint16_t | CsXferCount
DMA_HandleTypeDef * hdmaCsRx
DMA_HandleTypeDef * hdmaDrRx
__IO HAL_LockTypeDef | Lock
__IO HAL_SPDIFRX_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

SPDIFRX handle Structure definition.

Definition at line 141 of file stm32h7xx_hal_spdifrx.h.

Field Documentation

__IO uint16_t SPDIFRX_HandleTypeDef::CsXferCount

Definition at line 162 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), SPDIFRX_DMACxCplt(), and SPDIFRX_ReceiveControlFlow_IT().

__IO uint16_t SPDIFRX_HandleTypeDef::CsXferSize

Definition at line 160 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveControlFlow_DMA(), and HAL_SPDIFRX_ReceiveControlFlow_IT().

__IO uint32_t SPDIFRX_HandleTypeDef::ErrorCode

Definition at line 177 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DeInit(), HAL_SPDIFRX_GetError(), HAL_SPDIFRX_Init(), HAL_SPDIFRX_IRQHandler(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_DMAError().

DMA_HandleTypeDef* SPDIFRX_HandleTypeDef::hdmaCsRx

Definition at line 169 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DMAStop(), and HAL_SPDIFRX_ReceiveControlFlow_DMA().

DMA_HandleTypeDef* SPDIFRX_HandleTypeDef::hdmaDrRx

Definition at line 171 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DMAStop(), and HAL_SPDIFRX_ReceiveDataFlow_DMA().

SPDIFRX_InitTypeDef SPDIFRX_HandleTypeDef::Init

Definition at line 145 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

SPDIFRX_TypeDef* SPDIFRX_HandleTypeDef::Instance

Definition at line 143 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DeInit(), HAL_SPDIFRX_DMAStop(), HAL_SPDIFRX_Init(), HAL_SPDIFRX_ReceiveControlFlow(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_SetDataFormat(), SPDIFRX_DMACxCplt(), SPDIFRX_DMAError(), SPDIFRX_DMARxCplt(), SPDIFRX_ReceiveControlFlow_IT(), and SPDIFRX_ReceiveDataFlow_IT().

__IO HAL_LockTypeDef SPDIFRX_HandleTypeDef::Lock

Definition at line 173 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t* SPDIFRX_HandleTypeDef::pCsBuffPtr

Definition at line 149 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), and SPDIFRX_ReceiveControlFlow_IT().

uint32_t* SPDIFRX_HandleTypeDef::pRxBuffPtr

Definition at line 147 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_ReceiveDataFlow_IT().

__IO uint16_t SPDIFRX_HandleTypeDef::RxXferCount

Definition at line 153 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), SPDIFRX_DMAError(), SPDIFRX_DMARxCplt(), and SPDIFRX_ReceiveDataFlow_IT().

__IO uint16_t SPDIFRX_HandleTypeDef::RxXferSize

Definition at line 151 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

__IO HAL_SPDIFRX_StateTypeDef SPDIFRX_HandleTypeDef::State

Definition at line 175 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DeInit(), HAL_SPDIFRX_DMAStop(), HAL_SPDIFRX_GetState(), HAL_SPDIFRX_Init(), HAL_SPDIFRX_ReceiveControlFlow(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), SPDIFRX_DMACxCplt(), SPDIFRX_DMAError(), SPDIFRX_DMARxCplt(), SPDIFRX_ReceiveControlFlow_IT(), SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_spdifrx.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPDIFRX Error Code

Defines
SPDIFRX Error Code
SPDIFRX Exported Constants

Defines

#define | HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001U)
#define | HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002U)
#define | HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004U)
#define | HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008U)
#define | HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010U)

Define Documentation

#define HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008U)

DMA transfer error

Definition at line 195 of file stm32h7xx_hal_spdifrx.h.

Referenced by SPDIFRX_DMAError().

#define HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 191 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DeInit(), HAL_SPDIFRX_Init(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

#define HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002U)

OVR error

Definition at line 193 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler().

#define HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004U)

Parity error

Definition at line 194 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler().

#define HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001U)

Timeout error

Definition at line 192 of file stm32h7xx_hal_spdifrx.h.

#define HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010U)

Unknown Error error

Definition at line 196 of file stm32h7xx_hal_spdifrx.h.

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STM32H753xx HAL User Manual: SPDIFRX Input Selection

Defines
SPDIFRX Input Selection
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000U)
#define | SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000U)
#define | SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000U)
#define | SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000U)

Define Documentation

#define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000U)

Definition at line 204 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000U)

Definition at line 205 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000U)

Definition at line 206 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000U)

Definition at line 207 of file stm32h7xx_hal_spdifrx.h.

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STM32H753xx HAL User Manual: SPDIFRX Maximum Retries

Defines
SPDIFRX Maximum Retries
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000U)
#define | SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000U)
#define | SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000U)
#define | SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000U)

Define Documentation

#define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000U)

Definition at line 217 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000U)

Definition at line 216 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000U)

Definition at line 218 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000U)

Definition at line 215 of file stm32h7xx_hal_spdifrx.h.

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STM32H753xx HAL User Manual: SPDIFRX Wait For Activity

Defines
SPDIFRX Wait For Activity
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000U)
#define | SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)

Define Documentation

#define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000U)

Definition at line 226 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)

Definition at line 227 of file stm32h7xx_hal_spdifrx.h.

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STM32H753xx HAL User Manual: SPDIFRX Preamble Type Mask

Defines
SPDIFRX Preamble Type Mask
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000U)
#define | SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)

Define Documentation

#define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000U)

Definition at line 235 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)

Definition at line 236 of file stm32h7xx_hal_spdifrx.h.

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STM32H753xx HAL User Manual: SPDIFRX Channel Status Mask

Defines
SPDIFRX Channel Status Mask
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied into the SPDIF_DR */
#define | SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/

Define Documentation

#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied into the SPDIF_DR */

Definition at line 244 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/

Definition at line 245 of file stm32h7xx_hal_spdifrx.h.

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STM32H753xx HAL User Manual: SPDIFRX Validity Mask

Defines
SPDIFRX Validity Mask
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U)
#define | SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)

Define Documentation

#define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U)

Definition at line 253 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)

Definition at line 254 of file stm32h7xx_hal_spdifrx.h.

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STM32H753xx HAL User Manual: SPDIFRX Parity Error Mask

Defines
SPDIFRX Parity Error Mask
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000U)
#define | SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)

Define Documentation

#define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000U)

Definition at line 262 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)

Definition at line 263 of file stm32h7xx_hal_spdifrx.h.

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STM32H753xx HAL User Manual: SPDIFRX Channel Selection

Defines
SPDIFRX Channel Selection
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_CHANNEL_A ((uint32_t)0x00000000U)
#define | SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)

Define Documentation

#define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000U)

Definition at line 271 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)

Definition at line 272 of file stm32h7xx_hal_spdifrx.h.

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STM32H753xx HAL User Manual: SPDIFRX Data Format

Defines
SPDIFRX Data Format
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000U)
#define | SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010U)
#define | SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020U)

Define Documentation

#define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020U)

Definition at line 282 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000U)

Definition at line 280 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010U)

Definition at line 281 of file stm32h7xx_hal_spdifrx.h.

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STM32H753xx HAL User Manual: SPDIFRX Stereo Mode

Defines
SPDIFRX Stereo Mode
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000U)
#define | SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)

Define Documentation

#define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000U)

Definition at line 290 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)

Definition at line 291 of file stm32h7xx_hal_spdifrx.h.

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STM32H753xx HAL User Manual: SPDIFRX State

Defines
SPDIFRX State
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFCU)
#define | SPDIFRX_STATE_SYNC ((uint32_t)0x00000001U)
#define | SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN)

Define Documentation

#define SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFCU)

Definition at line 300 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN)

Definition at line 302 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_SetDataFormat().

#define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001U)

Definition at line 301 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

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STM32H753xx HAL User Manual: SPDIFRX Interrupts Definition

Defines
SPDIFRX Interrupts Definition
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)
#define | SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)
#define | SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)
#define | SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)
#define | SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)
#define | SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)
#define | SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )

Define Documentation

#define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)

Definition at line 311 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler(), HAL_SPDIFRX_ReceiveControlFlow_IT(), SPDIFRX_ReceiveControlFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

#define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )

Definition at line 316 of file stm32h7xx_hal_spdifrx.h.

Referenced by SPDIFRX_WaitOnFlagUntilTimeout().

#define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)

Definition at line 313 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_IT(), SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

#define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)

Definition at line 312 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_IT(), SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

#define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)

Definition at line 310 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler(), HAL_SPDIFRX_ReceiveDataFlow_IT(), SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

#define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)

Definition at line 314 of file stm32h7xx_hal_spdifrx.h.

Referenced by SPDIFRX_WaitOnFlagUntilTimeout().

#define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)

Definition at line 315 of file stm32h7xx_hal_spdifrx.h.

Referenced by SPDIFRX_WaitOnFlagUntilTimeout().

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STM32H753xx HAL User Manual: SPDIFRX Flags Definition

Defines
SPDIFRX Flags Definition
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)
#define | SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)
#define | SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)
#define | SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)
#define | SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)
#define | SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)
#define | SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)
#define | SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)
#define | SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)

Define Documentation

#define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)

Definition at line 325 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler(), and HAL_SPDIFRX_ReceiveControlFlow().

#define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)

Definition at line 330 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)

Definition at line 327 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler().

#define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)

Definition at line 326 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler().

#define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)

Definition at line 324 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler(), and HAL_SPDIFRX_ReceiveDataFlow().

#define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)

Definition at line 328 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)

Definition at line 331 of file stm32h7xx_hal_spdifrx.h.

#define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)

Definition at line 329 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveControlFlow(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

#define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)

Definition at line 332 of file stm32h7xx_hal_spdifrx.h.

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STM32H753xx HAL User Manual: SPDIFRX Exported Macros

Defines
SPDIFRX Exported Macros
SPDIFRX

Defines

#define | __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN)
Reset SPDIFRX handle state.
#define | __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)
Disable the specified SPDIFRX peripheral (IDLE State).
#define | __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)
Enable the specified SPDIFRX peripheral (SYNC State).
#define | __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)
Enable the specified SPDIFRX peripheral (RCV State).
#define | __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
Enable or disable the specified SPDIFRX interrupts.
#define | __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
#define | __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified SPDIFRX interrupt source is enabled or disabled.
#define | __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Checks whether the specified SPDIFRX flag is set or not.
#define | __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))
Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.

Define Documentation

#define __HAL_SPDIFRX_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))

Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.

Parameters:
__HANDLE__,: specifies the USART Handle.
__IT_CLEAR__,: specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt This parameter can be one of the following values:
  • SPDIFRX_FLAG_PERR
  • SPDIFRX_FLAG_OVR
  • SPDIFRX_SR_SBD
  • SPDIFRX_SR_SYNCD
Return values:
None

Definition at line 431 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler().

#define __HAL_SPDIFRX_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))

Definition at line 386 of file stm32h7xx_hal_spdifrx.h.

Referenced by SPDIFRX_ReceiveControlFlow_IT(), SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

#define __HAL_SPDIFRX_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))

Enable or disable the specified SPDIFRX interrupts.

Parameters:
__HANDLE__,: specifies the SPDIFRX Handle.
__INTERRUPT__,: specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • SPDIFRX_IT_RXNE
  • SPDIFRX_IT_CSRNE
  • SPDIFRX_IT_PERRIE
  • SPDIFRX_IT_OVRIE
  • SPDIFRX_IT_SBLKIE
  • SPDIFRX_IT_SYNCDIE
  • SPDIFRX_IT_IFEIE
Return values:
None

Definition at line 385 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveControlFlow_IT(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

#define __HAL_SPDIFRX_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Checks whether the specified SPDIFRX flag is set or not.

Parameters:
__HANDLE__,: specifies the SPDIFRX Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SPDIFRX_FLAG_RXNE
  • SPDIFRX_FLAG_CSRNE
  • SPDIFRX_FLAG_PERR
  • SPDIFRX_FLAG_OVR
  • SPDIFRX_FLAG_SBD
  • SPDIFRX_FLAG_SYNCD
  • SPDIFRX_FLAG_FERR
  • SPDIFRX_FLAG_SERR
  • SPDIFRX_FLAG_TERR
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 418 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler(), and SPDIFRX_WaitOnFlagUntilTimeout().

#define __HAL_SPDIFRX_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks if the specified SPDIFRX interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: specifies the SPDIFRX Handle.
__INTERRUPT__,: specifies the SPDIFRX interrupt source to check. This parameter can be one of the following values:
  • SPDIFRX_IT_RXNE
  • SPDIFRX_IT_CSRNE
  • SPDIFRX_IT_PERRIE
  • SPDIFRX_IT_OVRIE
  • SPDIFRX_IT_SBLKIE
  • SPDIFRX_IT_SYNCDIE
  • SPDIFRX_IT_IFEIE
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 401 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler().

#define __HAL_SPDIFRX_IDLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)

Disable the specified SPDIFRX peripheral (IDLE State).

Parameters:
__HANDLE__,: specifies the SPDIFRX Handle.
Return values:
None

Definition at line 356 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DeInit(), HAL_SPDIFRX_DMAStop(), and HAL_SPDIFRX_Init().

#define __HAL_SPDIFRX_RCV ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)

Enable the specified SPDIFRX peripheral (RCV State).

Parameters:
__HANDLE__,: specifies the SPDIFRX Handle.
Return values:
None

Definition at line 369 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveControlFlow(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

#define __HAL_SPDIFRX_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN)

Reset SPDIFRX handle state.

Parameters:
__HANDLE__,: SPDIFRX handle.
Return values:
None

Definition at line 350 of file stm32h7xx_hal_spdifrx.h.

#define __HAL_SPDIFRX_SYNC ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)

Enable the specified SPDIFRX peripheral (SYNC State).

Parameters:
__HANDLE__,: specifies the SPDIFRX Handle.
Return values:
None

Definition at line 362 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveControlFlow(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPDIFRX Private Macros

Defines
SPDIFRX Private Macros
SPDIFRX

Defines

#define | IS_SPDIFRX_INPUT_SELECT(INPUT)
#define | IS_SPDIFRX_MAX_RETRIES(RET)
#define | IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL)
#define | IS_PREAMBLE_TYPE_MASK(VAL)
#define | IS_VALIDITY_MASK(VAL)
#define | IS_PARITY_ERROR_MASK(VAL)
#define | IS_SPDIFRX_CHANNEL(CHANNEL)
#define | IS_SPDIFRX_DATA_FORMAT(FORMAT)
#define | IS_STEREO_MODE(MODE)
#define | IS_CHANNEL_STATUS_MASK(VAL)

Define Documentation

#define IS_CHANNEL_STATUS_MASK ( VAL )
Value:
(((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
                                              ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))

Definition at line 528 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), and HAL_SPDIFRX_SetDataFormat().

#define IS_PARITY_ERROR_MASK ( VAL )
Value:
(((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
                                             ((VAL) == SPDIFRX_PARITYERRORMASK_ON))

Definition at line 518 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), and HAL_SPDIFRX_SetDataFormat().

#define IS_PREAMBLE_TYPE_MASK ( VAL )
Value:
(((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
                                             ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))

Definition at line 514 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), and HAL_SPDIFRX_SetDataFormat().

#define IS_SPDIFRX_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == SPDIFRX_CHANNEL_A) || \
                                       ((CHANNEL) == SPDIFRX_CHANNEL_B))

Definition at line 520 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

#define IS_SPDIFRX_DATA_FORMAT ( FORMAT )
Value:
(((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
                                                 ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \
                                                 ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))

Definition at line 522 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), and HAL_SPDIFRX_SetDataFormat().

#define IS_SPDIFRX_INPUT_SELECT ( INPUT )
Value:
(((INPUT) == SPDIFRX_INPUT_IN1) || \
                                         ((INPUT) == SPDIFRX_INPUT_IN2) || \
                                         ((INPUT) == SPDIFRX_INPUT_IN3)  || \
                                         ((INPUT) == SPDIFRX_INPUT_IN0))

Definition at line 504 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

#define IS_SPDIFRX_MAX_RETRIES ( RET )
Value:
(((RET) == SPDIFRX_MAXRETRIES_NONE) || \
                                      ((RET) == SPDIFRX_MAXRETRIES_3)  || \
                                      ((RET) == SPDIFRX_MAXRETRIES_15) || \
                                      ((RET) == SPDIFRX_MAXRETRIES_63))

Definition at line 508 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

#define IS_SPDIFRX_WAIT_FOR_ACTIVITY ( VAL )
Value:
(((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
                                               ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))

Definition at line 512 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

#define IS_STEREO_MODE ( MODE )
Value:
(((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
                                             ((MODE) == SPDIFRX_STEREOMODE_ENABLE))

Definition at line 525 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), and HAL_SPDIFRX_SetDataFormat().

#define IS_VALIDITY_MASK ( VAL )
Value:
(((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \
                                             ((VAL) == SPDIFRX_VALIDITYMASK_ON))

Definition at line 516 of file stm32h7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), and HAL_SPDIFRX_SetDataFormat().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPDIFRX Private Functions

SPDIFRX Private Functions
SPDIFRX
Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPDIFRX

Modules | Defines
SPDIFRX
STM32H7xx_HAL_Driver

SPDIFRX HAL module driver. More...

Modules

SPDIFRX Exported Functions
SPDIFRX Exported Types
SPDIFRX Exported Constants
SPDIFRX Exported Macros
SPDIFRX Private Macros
SPDIFRX Private Functions

Defines

#define SPDIFRX_TIMEOUT_VALUE 0xFFFFU

Detailed Description

SPDIFRX HAL module driver.

Define Documentation

#define SPDIFRX_TIMEOUT_VALUE 0xFFFFU

Definition at line 141 of file stm32h7xx_hal_spdifrx.c.

Referenced by HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Private Constants

Defines
SPI Private Constants
SPI

Defines

#define SPI_DEFAULT_TIMEOUT 100U

Define Documentation

#define SPI_DEFAULT_TIMEOUT 100U

Definition at line 106 of file stm32h7xx_hal_spi.c.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Private Functions

Functions
SPI Private Functions
SPI

Private functions. More...

Functions

static void | SPI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit process complete callback.
static void | SPI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI receive process complete callback.
static void | SPI_DMATransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit receive process complete callback.
static void | SPI_DMAHalfTransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit process complete callback.
static void | SPI_DMAHalfReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half receive process complete callback.
static void | SPI_DMAHalfTransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit receive process complete callback.
static void | SPI_DMAError (DMA_HandleTypeDef *hdma)
DMA SPI communication error callback.
static void | SPI_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SPI_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SPI_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | SPI_WaitFlagStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI Communication Timeout.
static HAL_StatusTypeDef | SPI_WaitFifoStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI FIFO Communication Timeout.
static void | SPI_TxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 8-bit transmit in Interrupt mode.
static void | SPI_TxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 16-bit transmit in Interrupt mode.
static void | SPI_TxISR_32BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 32-bit transmit in Interrupt mode.
static void | SPI_RxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Manage the receive 8-bit in Interrupt context.
static void | SPI_RxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Manage the 16-bit receive in Interrupt context.
static void | SPI_RxISR_32BIT (struct __SPI_HandleTypeDef *hspi)
Manage the 32-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Tx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Tx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_32BIT (struct __SPI_HandleTypeDef *hspi)
Tx 32-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Rx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_32BIT (struct __SPI_HandleTypeDef *hspi)
Rx 32-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_AbortRx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Rx transaction.
static void | SPI_AbortTx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Tx or Rx/Tx transaction.
static void | SPI_CloseRxTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.
static void | SPI_CloseRx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RX transaction.
static void | SPI_CloseTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the TX transaction.
static HAL_StatusTypeDef | SPI_EndRxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RX transaction complete.
static HAL_StatusTypeDef | SPI_EndRxTxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RXTX or TX transaction complete.

Detailed Description

Private functions.

Function Documentation

static void SPI_2linesRxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 16-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3189 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_IT_RXNE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesRxISR_32BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 32-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3215 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_IT_RXNE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesRxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3159 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_IT_RXNE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesTxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Tx 16-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3271 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_IT_TXE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesTxISR_32BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Tx 32-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3298 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_IT_TXE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesTxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Tx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3241 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_IT_TXE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_AbortRx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle abort a Rx transaction.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3810 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_ABORT, HAL_SPI_STATE_ABORT, __SPI_HandleTypeDef::Instance, SPI_DEFAULT_TIMEOUT, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_WaitFifoStateUntilTimeout(), and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Abort(), and HAL_SPI_Abort_IT().

static void SPI_AbortTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle abort a Tx or Rx/Tx transaction.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3846 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_ABORT, HAL_SPI_STATE_ABORT, __SPI_HandleTypeDef::Instance, SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_WaitFifoStateUntilTimeout(), and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Abort(), and HAL_SPI_Abort_IT().

static void SPI_CloseRx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the RX transaction.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3732 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_CLEAR_EOTFLAG, __HAL_SPI_CLEAR_TXTFFLAG, __HAL_SPI_CLEAR_UDRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_DIRECTION_1LINE, SPI_FLAG_CRCERR, SPI_IT_ERR, SPI_IT_RXNE, and __SPI_HandleTypeDef::State.

Referenced by SPI_RxISR_16BIT(), SPI_RxISR_32BIT(), and SPI_RxISR_8BIT().

static void SPI_CloseRxTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the RXTX transaction.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3683 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_CLEAR_EOTFLAG, __HAL_SPI_CLEAR_TXTFFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TxRxCpltCallback(), SPI_FLAG_CRCERR, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, and __SPI_HandleTypeDef::State.

Referenced by SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_32BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_32BIT(), and SPI_2linesTxISR_8BIT().

static void SPI_CloseTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the TX transaction.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3779 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_CLEAR_EOTFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_CLEAR_TXTFFLAG, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxCpltCallback(), __SPI_HandleTypeDef::Init, SPI_DIRECTION_2LINES, SPI_IT_ERR, SPI_IT_TXE, and __SPI_HandleTypeDef::State.

Referenced by SPI_TxISR_16BIT(), SPI_TxISR_32BIT(), and SPI_TxISR_8BIT().

static void SPI_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2993 of file stm32h7xx_hal_spi.c.

References HAL_SPI_ErrorCallback(), __SPI_HandleTypeDef::RxXferCount, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_IRQHandler().

static void SPI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI communication error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2960 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_DMA, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAHalfReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2934 of file stm32h7xx_hal_spi.c.

References HAL_SPI_RxHalfCpltCallback().

Referenced by HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAHalfTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half transmit process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2921 of file stm32h7xx_hal_spi.c.

References HAL_SPI_TxHalfCpltCallback().

Referenced by HAL_SPI_Transmit_DMA().

static void SPI_DMAHalfTransmitReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half transmit receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2947 of file stm32h7xx_hal_spi.c.

References HAL_SPI_TxRxHalfCpltCallback().

Referenced by HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2797 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_CLEAR_EOTFLAG, __HAL_SPI_CLEAR_TXTFFLAG, __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_READY, __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_FLAG_CRCERR, SPI_IT_ERR, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3088 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_CLEAR_UDRFLAG, __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_DEFAULT_TIMEOUT, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SPI_Abort_IT().

static void SPI_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI transmit process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2736 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_CLEAR_EOTFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_CLEAR_TXTFFLAG, __HAL_SPI_CLEAR_UDRFLAG, __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, __HAL_SPI_ENABLE, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxCpltCallback(), __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::Instance, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_IT_ERR, __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_DMA().

static void SPI_DMATransmitReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI transmit receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2855 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxRxCpltCallback(), __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_CRCERR, SPI_IT_ERR, __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_DMA().

static void SPI_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3010 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_CLEAR_UDRFLAG, __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SPI_Abort_IT().

static HAL_StatusTypeDef SPI_EndRxTransaction | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle the check of the RX transaction complete.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Timeout,: Timeout duration
Tickstart,: tick start value
Return values:
None.

Definition at line 3529 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_CLEAR_EOTFLAG, __HAL_SPI_CLEAR_TXTFFLAG, SPI_InitTypeDef::DataSize, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FLAG, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DEFAULT_TIMEOUT, SPI_FLAG_EOT, SPI_FLAG_FRLVL, SPI_FLAG_RXWNE, SPI_FRLVL_EMPTY, SPI_FRLVL_QUARTER_FULL, and SPI_WaitFlagStateUntilTimeout().

Referenced by HAL_SPI_Receive().

static HAL_StatusTypeDef SPI_EndRxTxTransaction | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle the check of the RXTX or TX transaction complete.

Parameters:
hspi,: SPI handle
Timeout,: Timeout duration
Tickstart,: tick start value

Definition at line 3601 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_CLEAR_EOTFLAG, __HAL_SPI_CLEAR_TXTFFLAG, SPI_InitTypeDef::DataSize, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FLAG, HAL_SPIEx_FlushRxFifo(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DEFAULT_TIMEOUT, SPI_FLAG_EOT, SPI_FLAG_FRLVL, SPI_FLAG_RXWNE, SPI_FRLVL_EMPTY, SPI_FRLVL_QUARTER_FULL, and SPI_WaitFlagStateUntilTimeout().

Referenced by HAL_SPI_Abort(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_AbortTx_ISR(), SPI_DMATransmitReceiveCplt(), and SPI_DMATxAbortCallback().

static void SPI_RxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the 16-bit receive in Interrupt context.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3344 of file stm32h7xx_hal_spi.c.

References __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxXferCount, and SPI_CloseRx_ISR().

Referenced by HAL_SPI_Receive_IT().

static void SPI_RxISR_32BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the 32-bit receive in Interrupt context.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3363 of file stm32h7xx_hal_spi.c.

References __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxXferCount, and SPI_CloseRx_ISR().

Referenced by HAL_SPI_Receive_IT().

static void SPI_RxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the receive 8-bit in Interrupt context.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3325 of file stm32h7xx_hal_spi.c.

References __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxXferCount, and SPI_CloseRx_ISR().

Referenced by HAL_SPI_Receive_IT().

static void SPI_TxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Handle the data 16-bit transmit in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3400 of file stm32h7xx_hal_spi.c.

References __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_CloseTx_ISR(), and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_IT().

static void SPI_TxISR_32BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Handle the data 32-bit transmit in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3419 of file stm32h7xx_hal_spi.c.

References __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_CloseTx_ISR(), and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_IT().

static void SPI_TxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Handle the data 8-bit transmit in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3382 of file stm32h7xx_hal_spi.c.

References __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_CloseTx_ISR(), and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_IT().

static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Fifo,
 |  | uint32_t | State,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle SPI FIFO Communication Timeout.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Fifo,: Fifo to check
State,: Fifo state to check
Timeout,: Timeout duration
Tickstart,: tick start value
Return values:
HAL status

Definition at line 3485 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::Direction, HAL_GetTick(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Abort(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Flag,
 |  | uint32_t | State,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle SPI Communication Timeout.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Flag,: SPI flag to check
State,: flag state to check
Timeout,: Timeout duration
Tickstart,: Tick start value
Return values:
HAL status

Definition at line 3443 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::Direction, HAL_GetTick(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, and __SPI_HandleTypeDef::State.

Referenced by SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SPI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the SPIx peripheral:

      (+) User must implement HAL_SPI_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_SPI_Init() to configure the selected device with
          the selected configuration:
        (++) Mode
        (++) Direction
        (++) Data Size
        (++) Clock Polarity and Phase
        (++) NSS Management
        (++) BaudRate Prescaler
        (++) FirstBit
        (++) TIMode
        (++) CRC Calculation
        (++) CRC Polynomial if CRC enabled
        (++) CRC Length, used only with Data8 and Data16
        (++) FIFO reception threshold
        (++) FIFO transmission threshold

      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
          of the selected SPIx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SPI_DeInit ( SPI_HandleTypeDef * hspi )

De-Initialize the SPI peripheral.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL status

Definition at line 369 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE, assert_param, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_MspDeInit(), HAL_SPI_STATE_BUSY, HAL_SPI_STATE_RESET, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPI_Init ( SPI_HandleTypeDef * hspi )

Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL status

Definition at line 202 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE, assert_param, SPI_InitTypeDef::BaudRatePrescaler, SPI_InitTypeDef::CLKPhase, SPI_InitTypeDef::CLKPolarity, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::CRCPolynomial, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, SPI_InitTypeDef::FifoThreshold, SPI_InitTypeDef::FirstBit, HAL_SPI_ERROR_NONE, HAL_SPI_MspInit(), HAL_SPI_STATE_BUSY, HAL_SPI_STATE_READY, HAL_SPI_STATE_RESET, HAL_SPIEx_DisableLockConfiguration(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::IOSwap, IS_SPI_BAUDRATE_PRESCALER, IS_SPI_CPHA, IS_SPI_CPOL, IS_SPI_CRC_CALCULATION, IS_SPI_CRC_INITIALIZATION_PATTERN, IS_SPI_CRC_LENGTH, IS_SPI_CRC_POLYNOMIAL, IS_SPI_DATASIZE, IS_SPI_DIRECTION, IS_SPI_FIFOTHRESHOLD, IS_SPI_FIRST_BIT, IS_SPI_MODE, IS_SPI_NSS, IS_SPI_NSSP, IS_SPI_TIMODE, __SPI_HandleTypeDef::Lock, SPI_InitTypeDef::MasterInterDataIdleness, SPI_InitTypeDef::MasterKeepIOState, SPI_InitTypeDef::MasterSSIdleness, SPI_InitTypeDef::Mode, SPI_InitTypeDef::NSS, SPI_InitTypeDef::NSSPMode, SPI_InitTypeDef::NSSPolarity, SPI_InitTypeDef::RxCRCInitializationPattern, SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN, SPI_CRC_LENGTH_16BIT, SPI_CRC_LENGTH_32BIT, SPI_CRC_LENGTH_DATASIZE, SPI_CRCCALCULATION_DISABLE, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_32BIT, SPI_MODE_MASTER, SPI_MODE_SLAVE, SPI_NSS_POLARITY_LOW, SPI_NSS_SOFT, SPI_TIMODE_DISABLE, __SPI_HandleTypeDef::State, SPI_InitTypeDef::TIMode, and SPI_InitTypeDef::TxCRCInitializationPattern.

void HAL_SPI_MspDeInit ( SPI_HandleTypeDef * hspi )

De-Initialize the SPI MSP.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 419 of file stm32h7xx_hal_spi.c.

Referenced by HAL_SPI_DeInit().

void HAL_SPI_MspInit ( SPI_HandleTypeDef * hspi )

Initialize the SPI MSP.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 403 of file stm32h7xx_hal_spi.c.

Referenced by HAL_SPI_Init().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
SPI Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Abort (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_SPI_Abort_IT (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
__weak void | HAL_SPI_AbortCpltCallback (SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]
    This subsection provides a set of functions allowing to manage the SPI
    data transfers.

    [..] The SPI supports master and slave mode :

    (#) There are two modes of transfer:
       (##) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (##) No-Blocking mode: The communication is performed using Interrupts
            or DMA, These APIs return the HAL status.
            The end of the data processing will be indicated through the
            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.
            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
            will be executed respectively at the end of the transmit or Receive process
            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected

    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
        exist for 1Line (simplex) and 2Lines (full duplex) modes.

Function Documentation

HAL_StatusTypeDef HAL_SPI_Abort ( SPI_HandleTypeDef * hspi )

Abort ongoing transfer (blocking mode).

Parameters:
hspi SPI handle.
Note:
This procedure could be used for aborting any ongoing transfer (Tx and Rx), started in Interrupt or DMA mode.
This procedure performs following operations : + Disable SPI Interrupts (depending of transfer direction) + Disable the DMA transfer in the peripheral register (if enabled) + Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + Set handle State to READY.
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1955 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_CLEAR_UDRFLAG, __HAL_SPI_DISABLE, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_GetTick(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_ABORT, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_WaitFifoStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SPI_Abort_IT ( SPI_HandleTypeDef * hspi )

Abort ongoing transfer (Interrupt mode).

Parameters:
hspi SPI handle.
Note:
This procedure could be used for aborting any ongoing transfer (Tx and Rx), started in Interrupt or DMA mode.
This procedure performs following operations : + Disable SPI Interrupts (depending of transfer direction) + Disable the DMA transfer in the peripheral register (if enabled) + Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + Set handle State to READY + At abort completion, call user abort complete callback.
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 2105 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_CLEAR_UDRFLAG, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_ABORT, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DEFAULT_TIMEOUT, SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SPI_AbortCpltCallback ( SPI_HandleTypeDef * hspi )

SPI Abort Complete callback.

Parameters:
hspi SPI handle.
Return values:
None

Definition at line 2664 of file stm32h7xx_hal_spi.c.

Referenced by HAL_SPI_Abort_IT(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

HAL_StatusTypeDef HAL_SPI_DMAPause ( SPI_HandleTypeDef * hspi )

Pause the DMA Transfer.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 2296 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, and __SPI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SPI_DMAResume ( SPI_HandleTypeDef * hspi )

Resume the DMA Transfer.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 2331 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, and __SPI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SPI_DMAStop ( SPI_HandleTypeDef * hspi )

Stop the DMA Transfer.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 2366 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, HAL_DMA_Abort(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

void HAL_SPI_ErrorCallback ( SPI_HandleTypeDef * hspi )

SPI error callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2646 of file stm32h7xx_hal_spi.c.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAAbortOnError(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

void HAL_SPI_IRQHandler ( SPI_HandleTypeDef * hspi )

Handle SPI interrupt request.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
None

Definition at line 2414 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_MODFFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_CLEAR_UDRFLAG, __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, __HAL_SPI_ENABLE, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SPI_ERROR_FRE, HAL_SPI_ERROR_MODF, HAL_SPI_ERROR_NONE, HAL_SPI_ERROR_OVR, HAL_SPI_ERROR_UDR, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxISR, SPI_DMAAbortOnError(), SPI_FLAG_EOT, SPI_FLAG_FRE, SPI_FLAG_MODF, SPI_FLAG_OVR, SPI_FLAG_RXNE, SPI_FLAG_TXE, SPI_FLAG_UDR, SPI_IT_EOT, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SPI_Receive | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 707 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, assert_param, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ERROR_TIMEOUT, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_EndRxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_FRLVL, SPI_FLAG_RXNE, SPI_FLAG_RXWNE, SPI_FRLVL_QUARTER_FULL, SPI_MODE_MASTER, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_Receive_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Note:
When the CRC feature is enabled the pData Length must be Size + 1.
Parameters:
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1637 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_MDATAALIGN_HALFWORD, DMA_MDATAALIGN_WORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive_DMA(), __SPI_HandleTypeDef::hdmarx, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY, DMA_InitTypeDef::MemDataAlignment, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_DMAError(), SPI_DMAHalfReceiveCplt(), SPI_DMAReceiveCplt(), SPI_FIFO_THRESHOLD_08DATA, SPI_FIFO_THRESHOLD_16DATA, SPI_IT_ERR, SPI_MODE_MASTER, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_Receive_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1311 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive_IT(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_IT_EOT, SPI_IT_ERR, SPI_IT_RXNE, SPI_MODE_MASTER, SPI_RxISR_16BIT(), SPI_RxISR_32BIT(), SPI_RxISR_8BIT(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

void HAL_SPI_RxCpltCallback ( SPI_HandleTypeDef * hspi )

Rx Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2566 of file stm32h7xx_hal_spi.c.

Referenced by SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), and SPI_DMAReceiveCplt().

void HAL_SPI_RxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Rx Half Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2614 of file stm32h7xx_hal_spi.c.

Referenced by SPI_DMAHalfReceiveCplt().

HAL_StatusTypeDef HAL_SPI_Transmit | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 475 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_CLEAR_UDRFLAG, __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, assert_param, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, SPI_InitTypeDef::FifoThreshold, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ERROR_TIMEOUT, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), SPI_FIFO_THRESHOLD_01DATA, SPI_FIFO_THRESHOLD_03DATA, SPI_FLAG_TXE, SPI_FLAG_UDR, SPI_MODE_MASTER, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_Transmit_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1501 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_MDATAALIGN_HALFWORD, DMA_MDATAALIGN_WORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY, DMA_InitTypeDef::MemDataAlignment, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DMAError(), SPI_DMAHalfTransmitCplt(), SPI_DMATransmitCplt(), SPI_FIFO_THRESHOLD_08DATA, SPI_FIFO_THRESHOLD_16DATA, SPI_IT_ERR, SPI_MODE_MASTER, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_Transmit_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1213 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_CLEAR_UDRFLAG, __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, __HAL_SPI_GET_FLAG, assert_param, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_FLAG_UDR, SPI_IT_ERR, SPI_IT_TXE, SPI_MODE_MASTER, SPI_TxISR_16BIT(), SPI_TxISR_32BIT(), SPI_TxISR_8BIT(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_TransmitReceive | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit and Receive an amount of data in blocking mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData,: pointer to transmission data buffer
pRxData,: pointer to reception data buffer
Size,: amount of data to be sent and received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 941 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_CLEAR_TXTFFLAG, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, SPI_InitTypeDef::FifoThreshold, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ERROR_TIMEOUT, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), SPI_FIFO_THRESHOLD_01DATA, SPI_FIFO_THRESHOLD_03DATA, SPI_FLAG_CRCERR, SPI_FLAG_FRLVL, SPI_FLAG_RXNE, SPI_FLAG_RXWNE, SPI_FLAG_TXE, SPI_FLAG_TXTF, SPI_FRLVL_QUARTER_FULL, SPI_MODE_MASTER, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Receive().

HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in non-blocking mode with DMA.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData,: pointer to transmission data buffer
pRxData,: pointer to reception data buffer
Note:
When the CRC feature is enabled the pRxData Length must be Size + 1
Parameters:
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1776 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_MDATAALIGN_HALFWORD, DMA_MDATAALIGN_WORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, DMA_InitTypeDef::MemDataAlignment, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_DMAError(), SPI_DMAHalfReceiveCplt(), SPI_DMAHalfTransmitReceiveCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_FIFO_THRESHOLD_08DATA, SPI_FIFO_THRESHOLD_16DATA, SPI_IT_ERR, SPI_MODE_MASTER, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_SPI_Receive_DMA().

HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData,: pointer to transmission data buffer
pRxData,: pointer to reception data buffer
Size,: amount of data to be sent and received
Return values:
HAL status

Definition at line 1412 of file stm32h7xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_32BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_32BIT(), SPI_2linesTxISR_8BIT(), SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_IT_EOT, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Receive_IT().

void HAL_SPI_TxCpltCallback ( SPI_HandleTypeDef * hspi )

Tx Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2550 of file stm32h7xx_hal_spi.c.

Referenced by SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

void HAL_SPI_TxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Tx Half Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2598 of file stm32h7xx_hal_spi.c.

Referenced by SPI_DMAHalfTransmitCplt().

void HAL_SPI_TxRxCpltCallback ( SPI_HandleTypeDef * hspi )

Tx and Rx Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2582 of file stm32h7xx_hal_spi.c.

Referenced by SPI_CloseRxTx_ISR(), and SPI_DMATransmitReceiveCplt().

void HAL_SPI_TxRxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Tx and Rx Half Transfer callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2630 of file stm32h7xx_hal_spi.c.

Referenced by SPI_DMAHalfTransmitReceiveCplt().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SPI Exported Functions

SPI control functions. More...

Functions

HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

SPI control functions.

 ===============================================================================
                      ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the SPI.
     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication

Function Documentation

uint32_t HAL_SPI_GetError ( SPI_HandleTypeDef * hspi )

Return the SPI error code.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
SPI error code in bitmap format

Definition at line 2711 of file stm32h7xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode.

HAL_SPI_StateTypeDef HAL_SPI_GetState ( SPI_HandleTypeDef * hspi )

Return the SPI handle state.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
SPI state

Definition at line 2699 of file stm32h7xx_hal_spi.c.

References __SPI_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Exported Types

Data Structures | Typedefs | Enumerations
SPI Exported Types
SPI

Data Structures

struct | SPI_InitTypeDef
SPI Configuration Structure definition. More...
struct | __SPI_HandleTypeDef
SPI handle Structure definition. More...

Typedefs

typedef struct __SPI_HandleTypeDef | SPI_HandleTypeDef
SPI handle Structure definition.

Enumerations

enum HAL_SPI_StateTypeDef {
HAL_SPI_STATE_RESET = 0x00U, HAL_SPI_STATE_READY = 0x01U, HAL_SPI_STATE_BUSY = 0x02U, HAL_SPI_STATE_BUSY_TX = 0x03U,
HAL_SPI_STATE_BUSY_RX = 0x04U, HAL_SPI_STATE_BUSY_TX_RX = 0x05U, HAL_SPI_STATE_ERROR = 0x06U, HAL_SPI_STATE_ABORT = 0x07U
}
HAL SPI State structure definition. More...

Typedef Documentation

typedef struct __SPI_HandleTypeDef SPI_HandleTypeDef

SPI handle Structure definition.

Enumeration Type Documentation

enum HAL_SPI_StateTypeDef

HAL SPI State structure definition.

Enumerator:
HAL_SPI_STATE_RESET

Peripheral not Initialized

HAL_SPI_STATE_READY

Peripheral Initialized and ready for use

HAL_SPI_STATE_BUSY

an internal process is ongoing

HAL_SPI_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_SPI_STATE_BUSY_RX

Data Reception process is ongoing

HAL_SPI_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing

HAL_SPI_STATE_ERROR

SPI error state

HAL_SPI_STATE_ABORT

SPI abort is ongoing

Definition at line 151 of file stm32h7xx_hal_spi.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SPI_InitTypeDef Struct Reference
SPI Exported Types

SPI Configuration Structure definition. More...

#include <stm32h7xx_hal_spi.h>

Data Fields

uint32_t | Mode
uint32_t | Direction
uint32_t | DataSize
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | NSS
uint32_t | BaudRatePrescaler
uint32_t | FirstBit
uint32_t | TIMode
uint32_t | CRCCalculation
uint32_t | CRCPolynomial
uint32_t | CRCLength
uint32_t | NSSPMode
uint32_t | NSSPolarity
uint32_t | FifoThreshold
uint32_t | TxCRCInitializationPattern
uint32_t | RxCRCInitializationPattern
uint32_t | MasterSSIdleness
uint32_t | MasterInterDataIdleness
uint32_t | MasterReceiverAutoSusp
uint32_t | MasterKeepIOState
uint32_t | IOSwap

Detailed Description

SPI Configuration Structure definition.

Definition at line 65 of file stm32h7xx_hal_spi.h.

Field Documentation

uint32_t SPI_InitTypeDef::BaudRatePrescaler

Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of SPI BaudRate Prescaler

Note:
The communication clock is derived from the master clock. The slave clock does not need to be set.

Definition at line 86 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CLKPhase

Specifies the clock active edge for the bit capture. This parameter can be a value of SPI Clock Phase

Definition at line 79 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CLKPolarity

Specifies the serial clock steady state. This parameter can be a value of SPI Clock Polarity

Definition at line 76 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CRCCalculation

Specifies if the CRC calculation is enabled or not. This parameter can be a value of SPI CRC Calculation

Definition at line 98 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), and HAL_SPI_TransmitReceive().

uint32_t SPI_InitTypeDef::CRCLength

Specifies the CRC Length used for the CRC calculation. CRC Length is only used with Data8 and Data16, not other data size This parameter can be a value of SPI CRC Length

Definition at line 104 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CRCPolynomial

Specifies the polynomial used for the CRC calculation. This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535

Definition at line 101 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::DataSize

Specifies the SPI data size. This parameter can be a value of SPI Data Size

Definition at line 73 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

uint32_t SPI_InitTypeDef::Direction

Specifies the SPI bidirectional mode state. This parameter can be a value of SPI Direction Mode

Definition at line 70 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_CloseTx_ISR(), SPI_DMATransmitCplt(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::FifoThreshold

Specifies the FIFO threshold level. This parameter can be a value of SPI Fifo Threshold

Definition at line 119 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

uint32_t SPI_InitTypeDef::FirstBit

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of SPI MSB LSB Transmission

Definition at line 92 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::IOSwap

Invert MISO/MOSI alternate functions This parameter can be a value of Control SPI IO Swap

Definition at line 143 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::MasterInterDataIdleness

Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between two consecutive data frames in master mode This parameter can be a value of SPI Master Inter-Data Ideleness

Definition at line 132 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::MasterKeepIOState

Control of Alternate function GPIOs state This parameter can be a value of Keep IO State

Definition at line 140 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::MasterReceiverAutoSusp

Control continuous SPI transfer in master receiver mode and automatic management in order to avoid overrun condition. This parameter can be a value of SPI Master Receiver AutoSuspend

Definition at line 136 of file stm32h7xx_hal_spi.h.

uint32_t SPI_InitTypeDef::MasterSSIdleness

Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted additionally between active edge of SS and first data transaction start in master mode. This parameter can be a value of SPI Master SS Ideleness

Definition at line 128 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::Mode

Specifies the SPI operating mode. This parameter can be a value of SPI Mode

Definition at line 67 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPIEx_ConfigureUnderrun(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::NSS

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of SPI Slave Select Management

Definition at line 82 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::NSSPMode

Specifies whether the NSSP signal is enabled or not . This parameter can be a value of SPI NSS Pulse Mode This mode is activated by the NSSP bit in the SPIx_CR2 register and it takes effect only if the SPI interface is configured as Motorola SPI master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, CPOL setting is ignored).

Definition at line 108 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::NSSPolarity

Specifies which level of SS input/output external signal (present on SS pin) is considered as active one. This parameter can be a value of SPI NSS Polarity

Definition at line 115 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::RxCRCInitializationPattern

Specifies the receiver CRC initialization Pattern used for the CRC calculation. This parameter can be a value of SPI CRC Calculation Initialization Pattern

Definition at line 125 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::TIMode

Specifies if the TI mode is enabled or not. This parameter can be a value of SPI TI Mode

Definition at line 95 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::TxCRCInitializationPattern

Specifies the transmitter CRC initialization Pattern used for the CRC calculation. This parameter can be a value of SPI CRC Calculation Initialization Pattern

Definition at line 122 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_spi.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: __SPI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SPI_HandleTypeDef Struct Reference
SPI Exported Types

SPI handle Structure definition. More...

#include <stm32h7xx_hal_spi.h>

Data Fields

SPI_TypeDef * | Instance
SPI_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint32_t | CRCSize
void(* | RxISR )(struct __SPI_HandleTypeDef *hspi)
void(* | TxISR )(struct __SPI_HandleTypeDef *hspi)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SPI_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

SPI handle Structure definition.

Definition at line 166 of file stm32h7xx_hal_spi.h.

Field Documentation

uint32_t __SPI_HandleTypeDef::CRCSize

SPI CRC size used for the transfer

Definition at line 184 of file stm32h7xx_hal_spi.h.

__IO uint32_t __SPI_HandleTypeDef::ErrorCode

SPI Error code

Definition at line 198 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_GetError(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

DMA_HandleTypeDef* __SPI_HandleTypeDef::hdmarx

SPI Rx DMA Handle parameters

Definition at line 192 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DMAStop(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

DMA_HandleTypeDef* __SPI_HandleTypeDef::hdmatx

SPI Tx DMA Handle parameters

Definition at line 190 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DMAStop(), HAL_SPI_IRQHandler(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

SPI_InitTypeDef __SPI_HandleTypeDef::Init

SPI communication parameters

Definition at line 170 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPIEx_ConfigureUnderrun(), SPI_CloseRx_ISR(), SPI_CloseTx_ISR(), SPI_DMATransmitCplt(), SPI_EndRxTransaction(), SPI_EndRxTxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

SPI_TypeDef* __SPI_HandleTypeDef::Instance

SPI registers base address

Definition at line 168 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_DMAPause(), HAL_SPI_DMAResume(), HAL_SPI_DMAStop(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPIEx_ConfigureUnderrun(), HAL_SPIEx_DisableLockConfiguration(), HAL_SPIEx_EnableLockConfiguration(), HAL_SPIEx_FlushRxFifo(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_32BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_32BIT(), SPI_2linesTxISR_8BIT(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), SPI_EndRxTxTransaction(), SPI_RxISR_16BIT(), SPI_RxISR_32BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_32BIT(), SPI_TxISR_8BIT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

HAL_LockTypeDef __SPI_HandleTypeDef::Lock

Locking object

Definition at line 194 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint8_t* __SPI_HandleTypeDef::pRxBuffPtr

Pointer to SPI Rx transfer Buffer

Definition at line 178 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_32BIT(), SPI_2linesRxISR_8BIT(), SPI_EndRxTransaction(), SPI_EndRxTxTransaction(), SPI_RxISR_16BIT(), SPI_RxISR_32BIT(), and SPI_RxISR_8BIT().

uint8_t* __SPI_HandleTypeDef::pTxBuffPtr

Pointer to SPI Tx transfer Buffer

Definition at line 172 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_32BIT(), SPI_2linesTxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_32BIT(), and SPI_TxISR_8BIT().

void(* __SPI_HandleTypeDef::RxISR)(struct __SPI_HandleTypeDef *hspi)

function pointer on Rx ISR

Definition at line 186 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

__IO uint16_t __SPI_HandleTypeDef::RxXferCount

SPI Rx Transfer Counter

Definition at line 182 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_32BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_32BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAAbortOnError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), SPI_EndRxTxTransaction(), SPI_RxISR_16BIT(), SPI_RxISR_32BIT(), and SPI_RxISR_8BIT().

uint16_t __SPI_HandleTypeDef::RxXferSize

SPI Rx Transfer size

Definition at line 180 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

__IO HAL_SPI_StateTypeDef __SPI_HandleTypeDef::State

SPI communication state

Definition at line 196 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_DMAStop(), HAL_SPI_GetState(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPIEx_ConfigureUnderrun(), HAL_SPIEx_DisableLockConfiguration(), HAL_SPIEx_EnableLockConfiguration(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

void(* __SPI_HandleTypeDef::TxISR)(struct __SPI_HandleTypeDef *hspi)

function pointer on Tx ISR

Definition at line 188 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

__IO uint16_t __SPI_HandleTypeDef::TxXferCount

SPI Tx Transfer Counter

Definition at line 176 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_32BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_32BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAAbortOnError(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_TxISR_16BIT(), SPI_TxISR_32BIT(), and SPI_TxISR_8BIT().

uint16_t __SPI_HandleTypeDef::TxXferSize

SPI Tx Transfer size

Definition at line 174 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_spi.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI FIFO Type

Defines
SPI FIFO Type
SPI Exported Constants

Defines

#define | SPI_LOWEND_FIFO_SIZE 8U
#define | SPI_HIGHEND_FIFO_SIZE 16U

Define Documentation

#define SPI_HIGHEND_FIFO_SIZE 16U

Definition at line 216 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPIEx_FlushRxFifo().

#define SPI_LOWEND_FIFO_SIZE 8U

Definition at line 215 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPIEx_FlushRxFifo().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Error Codes

Defines
SPI Error Codes
SPI Exported Constants

Defines

#define | HAL_SPI_ERROR_NONE (0x00000000U)
#define | HAL_SPI_ERROR_MODF (0x00000001U)
#define | HAL_SPI_ERROR_CRC (0x00000002U)
#define | HAL_SPI_ERROR_OVR (0x00000004U)
#define | HAL_SPI_ERROR_FRE (0x00000008U)
#define | HAL_SPI_ERROR_DMA (0x00000010U)
#define | HAL_SPI_ERROR_FLAG (0x00000020U)
#define | HAL_SPI_ERROR_ABORT (0x00000040U)
#define | HAL_SPI_ERROR_UDR (0x00000080U)
#define | HAL_SPI_ERROR_TIMEOUT (0x00000100U)
#define | HAL_SPI_ERROR_UNKNOW (0x00000200U)

Define Documentation

#define HAL_SPI_ERROR_ABORT (0x00000040U)

Error during SPI Abort procedure

Definition at line 231 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

#define HAL_SPI_ERROR_CRC (0x00000002U)

CRC error

Definition at line 226 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define HAL_SPI_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 229 of file stm32h7xx_hal_spi.h.

Referenced by SPI_DMAError().

#define HAL_SPI_ERROR_FLAG (0x00000020U)

Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag

Definition at line 230 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_DMATransmitReceiveCplt(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define HAL_SPI_ERROR_FRE (0x00000008U)

FRE error

Definition at line 228 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_MODF (0x00000001U)

MODF error

Definition at line 225 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_NONE (0x00000000U)

No error

Definition at line 224 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), I2S_CloseTx_ISR(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), and SPI_DMATxAbortCallback().

#define HAL_SPI_ERROR_OVR (0x00000004U)

OVR error

Definition at line 227 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_TIMEOUT (0x00000100U)

Timeout error

Definition at line 233 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

#define HAL_SPI_ERROR_UDR (0x00000080U)

Underrun error

Definition at line 232 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_UNKNOW (0x00000200U)

Unknow error

Definition at line 234 of file stm32h7xx_hal_spi.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Mode

Defines
SPI Mode
SPI Exported Constants

Defines

#define | SPI_MODE_SLAVE (0x00000000U)
#define | SPI_MODE_MASTER SPI_CFG2_MASTER

Define Documentation

#define SPI_MODE_MASTER SPI_CFG2_MASTER

Definition at line 243 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_MODE_SLAVE (0x00000000U)

Definition at line 242 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), and HAL_SPIEx_ConfigureUnderrun().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Direction Mode

Defines
SPI Direction Mode
SPI Exported Constants

Defines

#define | SPI_DIRECTION_2LINES (0x00000000U)
#define | SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0
#define | SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1
#define | SPI_DIRECTION_1LINE SPI_CFG2_COMM

Define Documentation

#define SPI_DIRECTION_1LINE SPI_CFG2_COMM

Definition at line 254 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), SPI_CloseRx_ISR(), SPI_DMATransmitCplt(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_DIRECTION_2LINES (0x00000000U)

Definition at line 251 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

#define SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1

Definition at line 253 of file stm32h7xx_hal_spi.h.

Referenced by SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0

Definition at line 252 of file stm32h7xx_hal_spi.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Data Size

Defines
SPI Data Size
SPI Exported Constants

Defines

#define | SPI_DATASIZE_4BIT (0x00000003U)
#define | SPI_DATASIZE_5BIT (0x00000004U)
#define | SPI_DATASIZE_6BIT (0x00000005U)
#define | SPI_DATASIZE_7BIT (0x00000006U)
#define | SPI_DATASIZE_8BIT (0x00000007U)
#define | SPI_DATASIZE_9BIT (0x00000008U)
#define | SPI_DATASIZE_10BIT (0x00000009U)
#define | SPI_DATASIZE_11BIT (0x0000000AU)
#define | SPI_DATASIZE_12BIT (0x0000000BU)
#define | SPI_DATASIZE_13BIT (0x0000000CU)
#define | SPI_DATASIZE_14BIT (0x0000000DU)
#define | SPI_DATASIZE_15BIT (0x0000000EU)
#define | SPI_DATASIZE_16BIT (0x0000000FU)
#define | SPI_DATASIZE_17BIT (0x00000010U)
#define | SPI_DATASIZE_18BIT (0x00000011U)
#define | SPI_DATASIZE_19BIT (0x00000012U)
#define | SPI_DATASIZE_20BIT (0x00000013U)
#define | SPI_DATASIZE_21BIT (0x00000014U)
#define | SPI_DATASIZE_22BIT (0x00000015U)
#define | SPI_DATASIZE_23BIT (0x00000016U)
#define | SPI_DATASIZE_24BIT (0x00000017U)
#define | SPI_DATASIZE_25BIT (0x00000018U)
#define | SPI_DATASIZE_26BIT (0x00000019U)
#define | SPI_DATASIZE_27BIT (0x0000001AU)
#define | SPI_DATASIZE_28BIT (0x0000001BU)
#define | SPI_DATASIZE_29BIT (0x0000001CU)
#define | SPI_DATASIZE_30BIT (0x0000001DU)
#define | SPI_DATASIZE_31BIT (0x0000001EU)
#define | SPI_DATASIZE_32BIT (0x0000001FU)

Define Documentation

#define SPI_DATASIZE_10BIT (0x00000009U)

Definition at line 268 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_11BIT (0x0000000AU)

Definition at line 269 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_12BIT (0x0000000BU)

Definition at line 270 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_13BIT (0x0000000CU)

Definition at line 271 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_14BIT (0x0000000DU)

Definition at line 272 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_15BIT (0x0000000EU)

Definition at line 273 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_16BIT (0x0000000FU)

Definition at line 274 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define SPI_DATASIZE_17BIT (0x00000010U)

Definition at line 275 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_18BIT (0x00000011U)

Definition at line 276 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_19BIT (0x00000012U)

Definition at line 277 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_20BIT (0x00000013U)

Definition at line 278 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_21BIT (0x00000014U)

Definition at line 279 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_22BIT (0x00000015U)

Definition at line 280 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_23BIT (0x00000016U)

Definition at line 281 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_24BIT (0x00000017U)

Definition at line 282 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_25BIT (0x00000018U)

Definition at line 283 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_26BIT (0x00000019U)

Definition at line 284 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_27BIT (0x0000001AU)

Definition at line 285 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_28BIT (0x0000001BU)

Definition at line 286 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_29BIT (0x0000001CU)

Definition at line 287 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_30BIT (0x0000001DU)

Definition at line 288 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_31BIT (0x0000001EU)

Definition at line 289 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_32BIT (0x0000001FU)

Definition at line 290 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_DATASIZE_4BIT (0x00000003U)

Definition at line 262 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_5BIT (0x00000004U)

Definition at line 263 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_6BIT (0x00000005U)

Definition at line 264 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_7BIT (0x00000006U)

Definition at line 265 of file stm32h7xx_hal_spi.h.

#define SPI_DATASIZE_8BIT (0x00000007U)

Definition at line 266 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define SPI_DATASIZE_9BIT (0x00000008U)

Definition at line 267 of file stm32h7xx_hal_spi.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Clock Polarity

Defines
SPI Clock Polarity
SPI Exported Constants

Defines

#define | SPI_POLARITY_LOW (0x00000000U)
#define | SPI_POLARITY_HIGH SPI_CFG2_CPOL

Define Documentation

#define SPI_POLARITY_HIGH SPI_CFG2_CPOL

Definition at line 299 of file stm32h7xx_hal_spi.h.

#define SPI_POLARITY_LOW (0x00000000U)

Definition at line 298 of file stm32h7xx_hal_spi.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Clock Phase

Defines
SPI Clock Phase
SPI Exported Constants

Defines

#define | SPI_PHASE_1EDGE (0x00000000U)
#define | SPI_PHASE_2EDGE SPI_CFG2_CPHA

Define Documentation

#define SPI_PHASE_1EDGE (0x00000000U)

Definition at line 307 of file stm32h7xx_hal_spi.h.

#define SPI_PHASE_2EDGE SPI_CFG2_CPHA

Definition at line 308 of file stm32h7xx_hal_spi.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Slave Select Management

Defines
SPI Slave Select Management
SPI Exported Constants

Defines

#define | SPI_NSS_SOFT SPI_CFG2_SSM
#define | SPI_NSS_HARD_INPUT (0x00000000U)
#define | SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE

Define Documentation

#define SPI_NSS_HARD_INPUT (0x00000000U)

Definition at line 317 of file stm32h7xx_hal_spi.h.

#define SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE

Definition at line 318 of file stm32h7xx_hal_spi.h.

#define SPI_NSS_SOFT SPI_CFG2_SSM

Definition at line 316 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI NSS Pulse Mode

Defines
SPI NSS Pulse Mode
SPI Exported Constants

Defines

#define | SPI_NSS_PULSE_DISABLE (0x00000000U)
#define | SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM

Define Documentation

#define SPI_NSS_PULSE_DISABLE (0x00000000U)

Definition at line 326 of file stm32h7xx_hal_spi.h.

#define SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM

Definition at line 327 of file stm32h7xx_hal_spi.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI BaudRate Prescaler

Defines
SPI BaudRate Prescaler
SPI Exported Constants

Defines

#define | SPI_BAUDRATEPRESCALER_2 (0x00000000U)
#define | SPI_BAUDRATEPRESCALER_4 (0x10000000U)
#define | SPI_BAUDRATEPRESCALER_8 (0x20000000U)
#define | SPI_BAUDRATEPRESCALER_16 (0x30000000U)
#define | SPI_BAUDRATEPRESCALER_32 (0x40000000U)
#define | SPI_BAUDRATEPRESCALER_64 (0x50000000U)
#define | SPI_BAUDRATEPRESCALER_128 (0x60000000U)
#define | SPI_BAUDRATEPRESCALER_256 (0x70000000U)

Define Documentation

#define SPI_BAUDRATEPRESCALER_128 (0x60000000U)

Definition at line 341 of file stm32h7xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_16 (0x30000000U)

Definition at line 338 of file stm32h7xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)

Definition at line 335 of file stm32h7xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_256 (0x70000000U)

Definition at line 342 of file stm32h7xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_32 (0x40000000U)

Definition at line 339 of file stm32h7xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_4 (0x10000000U)

Definition at line 336 of file stm32h7xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_64 (0x50000000U)

Definition at line 340 of file stm32h7xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_8 (0x20000000U)

Definition at line 337 of file stm32h7xx_hal_spi.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI MSB LSB Transmission

Defines
SPI MSB LSB Transmission
SPI Exported Constants

Defines

#define | SPI_FIRSTBIT_MSB (0x00000000U)
#define | SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST

Define Documentation

#define SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST

Definition at line 351 of file stm32h7xx_hal_spi.h.

#define SPI_FIRSTBIT_MSB (0x00000000U)

Definition at line 350 of file stm32h7xx_hal_spi.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI TI Mode

Defines
SPI TI Mode
SPI Exported Constants

Defines

#define | SPI_TIMODE_DISABLE (0x00000000U)
#define | SPI_TIMODE_ENABLE SPI_CFG2_SP_0

Define Documentation

#define SPI_TIMODE_DISABLE (0x00000000U)

Definition at line 359 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_TIMODE_ENABLE SPI_CFG2_SP_0

Definition at line 360 of file stm32h7xx_hal_spi.h.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI CRC Calculation

Defines
SPI CRC Calculation
SPI Exported Constants

Defines

#define | SPI_CRCCALCULATION_DISABLE (0x00000000U)
#define | SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN

Define Documentation

#define SPI_CRCCALCULATION_DISABLE (0x00000000U)

Definition at line 368 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN

Definition at line 369 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), and HAL_SPI_TransmitReceive().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI CRC Length

Defines
SPI CRC Length
SPI Exported Constants

Defines

#define | SPI_CRC_LENGTH_DATASIZE (0x00000000U)
#define | SPI_CRC_LENGTH_4BIT (0x00030000U)
#define | SPI_CRC_LENGTH_5BIT (0x00040000U)
#define | SPI_CRC_LENGTH_6BIT (0x00050000U)
#define | SPI_CRC_LENGTH_7BIT (0x00060000U)
#define | SPI_CRC_LENGTH_8BIT (0x00070000U)
#define | SPI_CRC_LENGTH_9BIT (0x00080000U)
#define | SPI_CRC_LENGTH_10BIT (0x00090000U)
#define | SPI_CRC_LENGTH_11BIT (0x000A0000U)
#define | SPI_CRC_LENGTH_12BIT (0x000B0000U)
#define | SPI_CRC_LENGTH_13BIT (0x000C0000U)
#define | SPI_CRC_LENGTH_14BIT (0x000D0000U)
#define | SPI_CRC_LENGTH_15BIT (0x000E0000U)
#define | SPI_CRC_LENGTH_16BIT (0x000F0000U)
#define | SPI_CRC_LENGTH_17BIT (0x00100000U)
#define | SPI_CRC_LENGTH_18BIT (0x00110000U)
#define | SPI_CRC_LENGTH_19BIT (0x00120000U)
#define | SPI_CRC_LENGTH_20BIT (0x00130000U)
#define | SPI_CRC_LENGTH_21BIT (0x00140000U)
#define | SPI_CRC_LENGTH_22BIT (0x00150000U)
#define | SPI_CRC_LENGTH_23BIT (0x00160000U)
#define | SPI_CRC_LENGTH_24BIT (0x00170000U)
#define | SPI_CRC_LENGTH_25BIT (0x00180000U)
#define | SPI_CRC_LENGTH_26BIT (0x00190000U)
#define | SPI_CRC_LENGTH_27BIT (0x001A0000U)
#define | SPI_CRC_LENGTH_28BIT (0x001B0000U)
#define | SPI_CRC_LENGTH_29BIT (0x001C0000U)
#define | SPI_CRC_LENGTH_30BIT (0x001D0000U)
#define | SPI_CRC_LENGTH_31BIT (0x001E0000U)
#define | SPI_CRC_LENGTH_32BIT (0x001F0000U)

Define Documentation

#define SPI_CRC_LENGTH_10BIT (0x00090000U)

Definition at line 384 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_11BIT (0x000A0000U)

Definition at line 385 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_12BIT (0x000B0000U)

Definition at line 386 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_13BIT (0x000C0000U)

Definition at line 387 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_14BIT (0x000D0000U)

Definition at line 388 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_15BIT (0x000E0000U)

Definition at line 389 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_16BIT (0x000F0000U)

Definition at line 390 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_CRC_LENGTH_17BIT (0x00100000U)

Definition at line 391 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_18BIT (0x00110000U)

Definition at line 392 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_19BIT (0x00120000U)

Definition at line 393 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_20BIT (0x00130000U)

Definition at line 394 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_21BIT (0x00140000U)

Definition at line 395 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_22BIT (0x00150000U)

Definition at line 396 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_23BIT (0x00160000U)

Definition at line 397 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_24BIT (0x00170000U)

Definition at line 398 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_25BIT (0x00180000U)

Definition at line 399 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_26BIT (0x00190000U)

Definition at line 400 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_27BIT (0x001A0000U)

Definition at line 401 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_28BIT (0x001B0000U)

Definition at line 402 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_29BIT (0x001C0000U)

Definition at line 403 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_30BIT (0x001D0000U)

Definition at line 404 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_31BIT (0x001E0000U)

Definition at line 405 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_32BIT (0x001F0000U)

Definition at line 406 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_CRC_LENGTH_4BIT (0x00030000U)

Definition at line 378 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_5BIT (0x00040000U)

Definition at line 379 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_6BIT (0x00050000U)

Definition at line 380 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_7BIT (0x00060000U)

Definition at line 381 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_8BIT (0x00070000U)

Definition at line 382 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_9BIT (0x00080000U)

Definition at line 383 of file stm32h7xx_hal_spi.h.

#define SPI_CRC_LENGTH_DATASIZE (0x00000000U)

Definition at line 377 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Fifo Threshold

Defines
SPI Fifo Threshold
SPI Exported Constants

Defines

#define | SPI_FIFO_THRESHOLD_01DATA (0x00000000U)
#define | SPI_FIFO_THRESHOLD_02DATA (0x00000020U)
#define | SPI_FIFO_THRESHOLD_03DATA (0x00000040U)
#define | SPI_FIFO_THRESHOLD_04DATA (0x00000060U)
#define | SPI_FIFO_THRESHOLD_05DATA (0x00000080U)
#define | SPI_FIFO_THRESHOLD_06DATA (0x000000A0U)
#define | SPI_FIFO_THRESHOLD_07DATA (0x000000C0U)
#define | SPI_FIFO_THRESHOLD_08DATA (0x000000E0U)
#define | SPI_FIFO_THRESHOLD_09DATA (0x00000100U)
#define | SPI_FIFO_THRESHOLD_10DATA (0x00000120U)
#define | SPI_FIFO_THRESHOLD_11DATA (0x00000140U)
#define | SPI_FIFO_THRESHOLD_12DATA (0x00000160U)
#define | SPI_FIFO_THRESHOLD_13DATA (0x00000180U)
#define | SPI_FIFO_THRESHOLD_14DATA (0x000001A0U)
#define | SPI_FIFO_THRESHOLD_15DATA (0x000001C0U)
#define | SPI_FIFO_THRESHOLD_16DATA (0x000001E0U)

Define Documentation

#define SPI_FIFO_THRESHOLD_01DATA (0x00000000U)

Definition at line 414 of file stm32h7xx_hal_spi.h.

Referenced by HAL_I2S_Transmit(), HAL_I2SEx_TransmitReceive(), HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

#define SPI_FIFO_THRESHOLD_02DATA (0x00000020U)

Definition at line 415 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_03DATA (0x00000040U)

Definition at line 416 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

#define SPI_FIFO_THRESHOLD_04DATA (0x00000060U)

Definition at line 417 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_05DATA (0x00000080U)

Definition at line 418 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_06DATA (0x000000A0U)

Definition at line 419 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_07DATA (0x000000C0U)

Definition at line 420 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_08DATA (0x000000E0U)

Definition at line 421 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

#define SPI_FIFO_THRESHOLD_09DATA (0x00000100U)

Definition at line 422 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_10DATA (0x00000120U)

Definition at line 423 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_11DATA (0x00000140U)

Definition at line 424 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_12DATA (0x00000160U)

Definition at line 425 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_13DATA (0x00000180U)

Definition at line 426 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_14DATA (0x000001A0U)

Definition at line 427 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_15DATA (0x000001C0U)

Definition at line 428 of file stm32h7xx_hal_spi.h.

#define SPI_FIFO_THRESHOLD_16DATA (0x000001E0U)

Definition at line 429 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI CRC Calculation Initialization Pattern

Defines
SPI CRC Calculation Initialization Pattern
SPI Exported Constants

Defines

#define | SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000U)
#define | SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001U)

Define Documentation

#define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001U)

Definition at line 438 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000U)

Definition at line 437 of file stm32h7xx_hal_spi.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI NSS Polarity

Defines
SPI NSS Polarity
SPI Exported Constants

Defines

#define | SPI_NSS_POLARITY_LOW (0x00000000U)
#define | SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP

Define Documentation

#define SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP

Definition at line 447 of file stm32h7xx_hal_spi.h.

#define SPI_NSS_POLARITY_LOW (0x00000000U)

Definition at line 446 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Keep IO State

Defines
Keep IO State
SPI Exported Constants

Defines

#define | SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)
#define | SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR

Define Documentation

#define SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)

Definition at line 455 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR

Definition at line 456 of file stm32h7xx_hal_spi.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Control SPI IO Swap

Defines
Control SPI IO Swap
SPI Exported Constants

Defines

#define | SPI_IO_SWAP_DISABLE (0x00000000U)
#define | SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP

Define Documentation

#define SPI_IO_SWAP_DISABLE (0x00000000U)

Definition at line 464 of file stm32h7xx_hal_spi.h.

#define SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP

Definition at line 465 of file stm32h7xx_hal_spi.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Master SS Ideleness

Defines
SPI Master SS Ideleness
SPI Exported Constants

Defines

#define | SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000U)
#define | SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001U)
#define | SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002U)
#define | SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003U)
#define | SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004U)
#define | SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005U)
#define | SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006U)
#define | SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007U)
#define | SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008U)
#define | SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009U)
#define | SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AU)
#define | SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BU)
#define | SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CU)
#define | SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DU)
#define | SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EU)
#define | SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FU)

Define Documentation

#define SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000U)

Definition at line 473 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001U)

Definition at line 474 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002U)

Definition at line 475 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003U)

Definition at line 476 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004U)

Definition at line 477 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005U)

Definition at line 478 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006U)

Definition at line 479 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007U)

Definition at line 480 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008U)

Definition at line 481 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009U)

Definition at line 482 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AU)

Definition at line 483 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BU)

Definition at line 484 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CU)

Definition at line 485 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DU)

Definition at line 486 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EU)

Definition at line 487 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FU)

Definition at line 488 of file stm32h7xx_hal_spi.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Master Inter-Data Ideleness

Defines
SPI Master Inter-Data Ideleness
SPI Exported Constants

Defines

#define | SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000U)
#define | SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000001U)
#define | SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000002U)
#define | SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000003U)
#define | SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000004U)
#define | SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000005U)
#define | SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000006U)
#define | SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000007U)
#define | SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000008U)
#define | SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000009U)
#define | SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x0000000AU)
#define | SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x0000000BU)
#define | SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x0000000CU)
#define | SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x0000000DU)
#define | SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x0000000EU)
#define | SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x0000000FU)

Define Documentation

#define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000U)

Definition at line 496 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000001U)

Definition at line 497 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000002U)

Definition at line 498 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000003U)

Definition at line 499 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000004U)

Definition at line 500 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000005U)

Definition at line 501 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000006U)

Definition at line 502 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000007U)

Definition at line 503 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000008U)

Definition at line 504 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000009U)

Definition at line 505 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x0000000AU)

Definition at line 506 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x0000000BU)

Definition at line 507 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x0000000CU)

Definition at line 508 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x0000000DU)

Definition at line 509 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x0000000EU)

Definition at line 510 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x0000000FU)

Definition at line 511 of file stm32h7xx_hal_spi.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Master Receiver AutoSuspend

Defines
SPI Master Receiver AutoSuspend
SPI Exported Constants

Defines

#define | SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000U)
#define | SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX

Define Documentation

#define SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000U)

Definition at line 519 of file stm32h7xx_hal_spi.h.

#define SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX

Definition at line 520 of file stm32h7xx_hal_spi.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Underrun Detection

Defines
SPI Underrun Detection
SPI Exported Constants

Defines

#define | SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000U)
#define | SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0
#define | SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1

Define Documentation

#define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1

Definition at line 530 of file stm32h7xx_hal_spi.h.

#define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000U)

Definition at line 528 of file stm32h7xx_hal_spi.h.

#define SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0

Definition at line 529 of file stm32h7xx_hal_spi.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Underrun Behaviour

Defines
SPI Underrun Behaviour
SPI Exported Constants

Defines

#define | SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000U)
#define | SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG_0
#define | SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED SPI_CFG1_UDRCFG_1

Define Documentation

#define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG_0

Definition at line 539 of file stm32h7xx_hal_spi.h.

#define SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED SPI_CFG1_UDRCFG_1

Definition at line 540 of file stm32h7xx_hal_spi.h.

#define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000U)

Definition at line 538 of file stm32h7xx_hal_spi.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Interrupt Definition

Defines
SPI Interrupt Definition
SPI Exported Constants

Defines

#define | SPI_IT_TXE SPI_IER_TXPIE
#define | SPI_IT_RXNE SPI_IER_RXPIE
#define | SPI_IT_EOT SPI_IER_EOTIE
#define | SPI_IT_TXTF SPI_IER_TXTFIE
#define | SPI_IT_ERR (SPI_IER_UDRIE | SPI_IER_OVRIE | SPI_IER_TIFREIE | SPI_IER_MODFIE)

Define Documentation

#define SPI_IT_EOT SPI_IER_EOTIE

Definition at line 550 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_IT(), and HAL_SPI_TransmitReceive_IT().

#define SPI_IT_ERR (SPI_IER_UDRIE | SPI_IER_OVRIE | SPI_IER_TIFREIE | SPI_IER_MODFIE)

Definition at line 552 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_IT_RXNE SPI_IER_RXPIE

Definition at line 549 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_32BIT(), SPI_2linesRxISR_8BIT(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_IT_TXE SPI_IER_TXPIE

Definition at line 548 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_32BIT(), SPI_2linesTxISR_8BIT(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_IT_TXTF SPI_IER_TXTFIE

Definition at line 551 of file stm32h7xx_hal_spi.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Flags Definition

Defines
SPI Flags Definition
SPI Exported Constants

Defines

#define | SPI_FLAG_TXE SPI_SR_TXP /* SPI status flag: Tx buffer empty flag */
#define | SPI_FLAG_RXNE SPI_SR_RXP /* SPI status flag: Rx buffer not empty flag */
#define | SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag: Underrun flag */
#define | SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define | SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag: TI mode frame format error flag */
#define | SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag: CRC error flag */
#define | SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define | SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI fifo reception level */
#define | SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI RxFIFO Word Not Empty */
#define | SPI_FLAG_TXTF SPI_SR_TXTF /* SPI Transmission Transfer Filled flag */
#define | SPI_FLAG_EOT SPI_SR_EOT /* SPI fifo transmision complete */

Define Documentation

#define SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag: CRC error flag */

Definition at line 565 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define SPI_FLAG_EOT SPI_SR_EOT /* SPI fifo transmision complete */

Definition at line 570 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag: TI mode frame format error flag */

Definition at line 564 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI fifo reception level */

Definition at line 567 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), HAL_SPIEx_FlushRxFifo(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */

Definition at line 566 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */

Definition at line 563 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_RXNE SPI_SR_RXP /* SPI status flag: Rx buffer not empty flag */

Definition at line 561 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive(), and HAL_SPI_TransmitReceive().

#define SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI RxFIFO Word Not Empty */

Definition at line 568 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), HAL_SPIEx_FlushRxFifo(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define SPI_FLAG_TXE SPI_SR_TXP /* SPI status flag: Tx buffer empty flag */

Definition at line 560 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

#define SPI_FLAG_TXTF SPI_SR_TXTF /* SPI Transmission Transfer Filled flag */

Definition at line 569 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_TransmitReceive().

#define SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag: Underrun flag */

Definition at line 562 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit(), and HAL_SPI_Transmit_IT().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Reception FIFO Status Level

Defines
SPI Reception FIFO Status Level
SPI Exported Constants

Defines

#define | SPI_FRLVL_EMPTY (0x00000000U)
#define | SPI_FRLVL_QUARTER_FULL (0x00002000U)
#define | SPI_FRLVL_HALF_FULL (0x00004000U)
#define | SPI_FRLVL_FULL (0x00006000U)

Define Documentation

#define SPI_FRLVL_EMPTY (0x00000000U)

Definition at line 578 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPIEx_FlushRxFifo(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define SPI_FRLVL_FULL (0x00006000U)

Definition at line 581 of file stm32h7xx_hal_spi.h.

#define SPI_FRLVL_HALF_FULL (0x00004000U)

Definition at line 580 of file stm32h7xx_hal_spi.h.

#define SPI_FRLVL_QUARTER_FULL (0x00002000U)

Definition at line 579 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Exported Macros

Defines
SPI Exported Macros
SPI

Defines

#define | __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
Reset SPI handle state.
#define | __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified SPI interrupts.
#define | __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified SPI interrupts.
#define | __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SPI interrupt source is enabled or not.
#define | __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SPI flag is set or not.
#define | __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC)
Clear the SPI CRCERR pending flag.
#define | __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC));
Clear the SPI MODF pending flag.
#define | __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
Clear the SPI OVR pending flag.
#define | __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
Clear the SPI FRE pending flag.
#define | __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
Clear the SPI UDR pending flag.
#define | __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC)
Clear the SPI EOT pending flag.
#define | __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC)
Clear the SPI UDR pending flag.
#define | __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
Enable the SPI peripheral.
#define | __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
Disable the SPI peripheral.

Define Documentation

#define __HAL_SPI_CLEAR_CRCERRFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC)

Clear the SPI CRCERR pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle.
Return values:
None

Definition at line 662 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define __HAL_SPI_CLEAR_EOTFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC)

Clear the SPI EOT pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle.
Return values:
None

Definition at line 692 of file stm32h7xx_hal_spi.h.

Referenced by SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define __HAL_SPI_CLEAR_FREFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)

Clear the SPI FRE pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle.
Return values:
None

Definition at line 680 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

#define __HAL_SPI_CLEAR_MODFFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC));

Clear the SPI MODF pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle.
Return values:
None

Definition at line 668 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define __HAL_SPI_CLEAR_OVRFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)

Clear the SPI OVR pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle.
Return values:
None

Definition at line 674 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Transmit(), SPI_CloseTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), and SPI_DMATxAbortCallback().

#define __HAL_SPI_CLEAR_TXTFFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC)

Clear the SPI UDR pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle.
Return values:
None

Definition at line 698 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define __HAL_SPI_CLEAR_UDRFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)

Clear the SPI UDR pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle.
Return values:
None

Definition at line 686 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Transmit(), HAL_SPI_Transmit_IT(), SPI_CloseRx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), and SPI_DMATxAbortCallback().

#define __HAL_SPI_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)

Disable the SPI peripheral.

Parameters:
__HANDLE__,: specifies the SPI Handle.
Return values:
None

Definition at line 710 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_DeInit(), HAL_SPI_DMAPause(), HAL_SPI_DMAResume(), HAL_SPI_DMAStop(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_DMA(), HAL_SPIEx_ConfigureUnderrun(), HAL_SPIEx_DisableLockConfiguration(), HAL_SPIEx_EnableLockConfiguration(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))

Disable the specified SPI interrupts.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
__INTERRUPT__,: specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 624 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_32BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_32BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)

Enable the SPI peripheral.

Parameters:
__HANDLE__,: specifies the SPI Handle.
Return values:
None

Definition at line 704 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_DMAPause(), HAL_SPI_DMAResume(), HAL_SPI_DMAStop(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPIEx_ConfigureUnderrun(), HAL_SPIEx_DisableLockConfiguration(), HAL_SPIEx_EnableLockConfiguration(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), and SPI_DMATxAbortCallback().

#define __HAL_SPI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enable the specified SPI interrupts.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
__INTERRUPT__,: specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 612 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define __HAL_SPI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Check whether the specified SPI flag is set or not.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SPI_FLAG_TXE : Tx buffer empty flag
  • SPI_FLAG_RXNE : Rx buffer not empty flag
  • SPI_FLAG_UDR : Underrun flag
  • SPI_FLAG_OVR : Overrun flag
  • SPI_FLAG_FRE : TI mode frame format error flag
  • SPI_FLAG_CRCERR: CRC error flag
  • SPI_FLAG_MODF : Mode fault flag
  • SPI_FLAG_FRLVL : fifo reception level
  • SPI_FLAG_RXWNE : RxFIFO Word Not Empty
  • SPI_FLAG_TXTF : Transmission Transfer Filled flag
  • SPI_FLAG_EOT : fifo transmision complete
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 656 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define __HAL_SPI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SPI interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
__INTERRUPT__,: specifies the SPI interrupt source to check. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 636 of file stm32h7xx_hal_spi.h.

#define __HAL_SPI_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)

Reset SPI handle state.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
Return values:
None

Definition at line 600 of file stm32h7xx_hal_spi.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Private Macros

Defines
SPI Private Macros
SPI

Defines

#define | SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR)
Set the SPI transmit-only mode.
#define | SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR)
Set the SPI receive-only mode.
#define | IS_SPI_MODE(MODE)
#define | IS_SPI_DIRECTION(MODE)
#define | IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE)
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE)
#define | IS_SPI_DATASIZE(DATASIZE)
#define | IS_SPI_FIFOTHRESHOLD(THRESHOLD)
#define | IS_SPI_CPOL(CPOL)
#define | IS_SPI_CPHA(CPHA)
#define | IS_SPI_NSS(NSS)
#define | IS_SPI_NSSP(NSSP)
#define | IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
#define | IS_SPI_FIRST_BIT(BIT)
#define | IS_SPI_TIMODE(MODE)
#define | IS_SPI_CRC_CALCULATION(CALCULATION)
#define | IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN)
#define | IS_SPI_CRC_LENGTH(LENGTH)
#define | IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFFFFFF))
#define | IS_SPI_UNDERRUN_DETECTION(MODE)
#define | IS_SPI_UNDERRUN_BEHAVIOUR(MODE)

Define Documentation

#define IS_SPI_BAUDRATE_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))

Definition at line 890 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CPHA ( CPHA )
Value:
(((CPHA) == SPI_PHASE_1EDGE) || \
                           ((CPHA) == SPI_PHASE_2EDGE))

Definition at line 880 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CPOL ( CPOL )
Value:
(((CPOL) == SPI_POLARITY_LOW) || \
                           ((CPOL) == SPI_POLARITY_HIGH))

Definition at line 877 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_CALCULATION ( CALCULATION )
Value:
(((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
                                             ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))

Definition at line 905 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_INITIALIZATION_PATTERN ( PATTERN )
Value:
(((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \
                                                    ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN))

Definition at line 908 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_LENGTH ( LENGTH )
Value:
(((LENGTH) == SPI_CRC_LENGTH_DATASIZE)  ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_32BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_31BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_30BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_29BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_28BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_27BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_26BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_25BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_24BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_23BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_22BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_21BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_20BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_19BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_18BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_17BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_16BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_15BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_14BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_13BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_12BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_11BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_10BIT)     ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_9BIT)      ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_8BIT)      ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_7BIT)      ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_6BIT)      ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_5BIT)      ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_4BIT))

Definition at line 911 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_POLYNOMIAL ( POLYNOMIAL ) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFFFFFF))

Definition at line 942 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DATASIZE ( DATASIZE )
Value:
(((DATASIZE) == SPI_DATASIZE_32BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_31BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_30BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_29BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_28BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_27BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_26BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_25BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_24BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_23BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_22BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_21BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_20BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_22BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_19BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_18BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_17BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_16BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_15BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_14BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_13BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_12BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_11BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_10BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_9BIT)  || \
                                   ((DATASIZE) == SPI_DATASIZE_8BIT)  || \
                                   ((DATASIZE) == SPI_DATASIZE_7BIT)  || \
                                   ((DATASIZE) == SPI_DATASIZE_6BIT)  || \
                                   ((DATASIZE) == SPI_DATASIZE_5BIT)  || \
                                   ((DATASIZE) == SPI_DATASIZE_4BIT))

Definition at line 829 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DIRECTION ( MODE )
Value:
(((MODE) == SPI_DIRECTION_2LINES)        || \
                                  ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
                                  ((MODE) == SPI_DIRECTION_1LINE)         || \
                                  ((MODE) == SPI_DIRECTION_2LINES_TXONLY))

Definition at line 812 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DIRECTION_2LINES ( MODE ) ((MODE) == SPI_DIRECTION_2LINES)

Definition at line 817 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY ( MODE )
Value:
(    \
                                  ((MODE) == SPI_DIRECTION_2LINES)|| \
                                  ((MODE) == SPI_DIRECTION_1LINE) || \
                                  ((MODE) == SPI_DIRECTION_2LINES_RXONLY))

Definition at line 824 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), and HAL_SPI_Receive_IT().

#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY ( MODE )
Value:
(    \
                                  ((MODE) == SPI_DIRECTION_2LINES)|| \
                                  ((MODE) == SPI_DIRECTION_1LINE) || \
                                  ((MODE) == SPI_DIRECTION_2LINES_TXONLY))

Definition at line 819 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), and HAL_SPI_Transmit_IT().

#define IS_SPI_FIFOTHRESHOLD ( THRESHOLD )
Value:
(((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \
                                         ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \
                                         ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \
                                         ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \
                                         ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \
                                         ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \
                                         ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \
                                         ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \
                                         ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \
                                         ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \
                                         ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \
                                         ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \
                                         ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \
                                         ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \
                                         ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \
                                         ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA))

Definition at line 860 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_FIRST_BIT ( BIT )
Value:
(((BIT) == SPI_FIRSTBIT_MSB) || \
                               ((BIT) == SPI_FIRSTBIT_LSB))

Definition at line 899 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_MODE ( MODE )
Value:
(((MODE) == SPI_MODE_SLAVE) || \
                           ((MODE) == SPI_MODE_MASTER))

Definition at line 809 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_NSS ( NSS )
Value:
(((NSS) == SPI_NSS_SOFT)       || \
                         ((NSS) == SPI_NSS_HARD_INPUT) || \
                         ((NSS) == SPI_NSS_HARD_OUTPUT))

Definition at line 883 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_NSSP ( NSSP )
Value:
(((NSSP) == SPI_NSS_PULSE_ENABLE) || \
                           ((NSSP) == SPI_NSS_PULSE_DISABLE))

Definition at line 887 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_TIMODE ( MODE )
Value:
(((MODE) == SPI_TIMODE_DISABLE) || \
                             ((MODE) == SPI_TIMODE_ENABLE))

Definition at line 902 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_UNDERRUN_BEHAVIOUR ( MODE )
Value:
(((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \
                                         ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED)    || \
                                         ((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED))

Definition at line 948 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPIEx_ConfigureUnderrun().

#define IS_SPI_UNDERRUN_DETECTION ( MODE )
Value:
(((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \
                                         ((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME)   || \
                                         ((MODE) == SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS))

Definition at line 944 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPIEx_ConfigureUnderrun().

#define SPI_1LINE_RX ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR)

Set the SPI receive-only mode.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 807 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), and HAL_SPI_Receive_IT().

#define SPI_1LINE_TX ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR)

Set the SPI transmit-only mode.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 800 of file stm32h7xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), and HAL_SPI_Transmit_IT().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
SPIEx Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_SPIEx_FlushRxFifo (SPI_HandleTypeDef *hspi)
Flush the RX fifo.
HAL_StatusTypeDef | HAL_SPIEx_EnableLockConfiguration (SPI_HandleTypeDef *hspi)
Enable the Lock for the AF configuration of associated IOs and write protect the Content of Configuartion register 2 when SPI is enabled.
HAL_StatusTypeDef | HAL_SPIEx_DisableLockConfiguration (SPI_HandleTypeDef *hspi)
Disable the Lock for the AF configuration of associated IOs.
HAL_StatusTypeDef | HAL_SPIEx_ConfigureUnderrun (SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour)
Configure the UNDERRUN condition and behavior of slave transmitter.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]
    This subsection provides a set of extended functions to manage the SPI
    data transfers.

    (#) SPIEx function:
        (++) HAL_SPIEx_FlushRxFifo()
        (++) HAL_SPIEx_FlushRxFifo()
        (++) HAL_SPIEx_EnableLockConfiguration()
        (++) HAL_SPIEx_DisableLockConfiguration()
        (++) HAL_SPIEx_ConfigureUnderrun()

Function Documentation

HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | UnderrunDetection,
 |  | uint32_t | UnderrunBehaviour
 | ) |  |

Configure the UNDERRUN condition and behavior of slave transmitter.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
UnderrunDetection | : Detection of underrun condition at slave transmitter This parameter can be a value of SPI Underrun Detection.
UnderrunBehaviour | : Behavior of slave transmitter at underrun condition This parameter can be a value of SPI Underrun Behaviour.
Return values:
None

Definition at line 226 of file stm32h7xx_hal_spi_ex.c.

References __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, assert_param, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_UNDERRUN_BEHAVIOUR, IS_SPI_UNDERRUN_DETECTION, SPI_InitTypeDef::Mode, SPI_MODE_SLAVE, and __SPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPIEx_DisableLockConfiguration ( SPI_HandleTypeDef * hspi )

Disable the Lock for the AF configuration of associated IOs.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 176 of file stm32h7xx_hal_spi_ex.c.

References __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Init().

HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration ( SPI_HandleTypeDef * hspi )

Enable the Lock for the AF configuration of associated IOs and write protect the Content of Configuartion register 2 when SPI is enabled.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 132 of file stm32h7xx_hal_spi_ex.c.

References __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo ( SPI_HandleTypeDef * hspi )

Flush the RX fifo.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 95 of file stm32h7xx_hal_spi_ex.c.

References __SPI_HandleTypeDef::Instance, SPI_FLAG_FRLVL, SPI_FLAG_RXWNE, SPI_FRLVL_EMPTY, SPI_HIGHEND_FIFO_SIZE, and SPI_LOWEND_FIFO_SIZE.

Referenced by SPI_EndRxTxTransaction().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SRAM Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SRAM_Init (SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Performs the SRAM device initialization sequence.
HAL_StatusTypeDef | HAL_SRAM_DeInit (SRAM_HandleTypeDef *hsram)
Performs the SRAM device De-initialization sequence.
__weak void | HAL_SRAM_MspInit (SRAM_HandleTypeDef *hsram)
SRAM MSP Init.
__weak void | HAL_SRAM_MspDeInit (SRAM_HandleTypeDef *hsram)
SRAM MSP DeInit.
__weak void | HAL_SRAM_DMA_XferCpltCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete callback.
__weak void | HAL_SRAM_DMA_XferErrorCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete error callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
           ##### SRAM Initialization and de_initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to initialize/de-initialize
          the SRAM memory

Function Documentation

HAL_StatusTypeDef HAL_SRAM_DeInit ( SRAM_HandleTypeDef * hsram )

Performs the SRAM device De-initialization sequence.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
HAL status

Definition at line 179 of file stm32h7xx_hal_sram.c.

References SRAM_HandleTypeDef::Extended, HAL_SRAM_MspDeInit(), HAL_SRAM_STATE_RESET, SRAM_HandleTypeDef::Init, SRAM_HandleTypeDef::Instance, and SRAM_HandleTypeDef::State.

__weak void HAL_SRAM_DMA_XferCpltCallback ( MDMA_HandleTypeDef * hmdma )

DMA transfer complete callback.

Parameters:
hmdma,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 233 of file stm32h7xx_hal_sram.c.

Referenced by HAL_SRAM_Read_DMA(), and HAL_SRAM_Write_DMA().

__weak void HAL_SRAM_DMA_XferErrorCallback ( MDMA_HandleTypeDef * hmdma )

DMA transfer complete error callback.

Parameters:
hmdma,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 249 of file stm32h7xx_hal_sram.c.

Referenced by HAL_SRAM_Read_DMA(), and HAL_SRAM_Write_DMA().

HAL_StatusTypeDef HAL_SRAM_Init | ( | SRAM_HandleTypeDef * | hsram,
 |  | FMC_NORSRAM_TimingTypeDef * | Timing,
 |  | FMC_NORSRAM_TimingTypeDef * | ExtTiming
 | ) |  |

Performs the SRAM device initialization sequence.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Timing,: Pointer to SRAM control timing structure
ExtTiming,: Pointer to SRAM extended mode timing structure
Return values:
HAL status

Definition at line 139 of file stm32h7xx_hal_sram.c.

References SRAM_HandleTypeDef::Extended, HAL_SRAM_MspInit(), HAL_SRAM_STATE_RESET, SRAM_HandleTypeDef::Init, SRAM_HandleTypeDef::Instance, SRAM_HandleTypeDef::Lock, and SRAM_HandleTypeDef::State.

void HAL_SRAM_MspDeInit ( SRAM_HandleTypeDef * hsram )

SRAM MSP DeInit.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 217 of file stm32h7xx_hal_sram.c.

Referenced by HAL_SRAM_DeInit().

void HAL_SRAM_MspInit ( SRAM_HandleTypeDef * hsram )

SRAM MSP Init.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 201 of file stm32h7xx_hal_sram.c.

Referenced by HAL_SRAM_Init().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Input Output and memory control functions

Functions
Input Output and memory control functions
SRAM Exported Functions

Input Output and memory control functions. More...

Functions

HAL_StatusTypeDef | HAL_SRAM_Read_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
Reads 8-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
Writes 8-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
Reads 16-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
Writes 16-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads 32-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes 32-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads a Words data from the SRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SRAM_Write_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes a Words data buffer to SRAM memory using DMA transfer.
void | HAL_SRAM_DMA_XferCpltCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete callback.
void | HAL_SRAM_DMA_XferErrorCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete error callback.

Detailed Description

Input Output and memory control functions.

  ==============================================================================
                  ##### SRAM Input and Output functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to use and control the SRAM memory

Function Documentation

void HAL_SRAM_DMA_XferCpltCallback ( MDMA_HandleTypeDef * hmdma )

DMA transfer complete callback.

Parameters:
hmdma,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 233 of file stm32h7xx_hal_sram.c.

Referenced by HAL_SRAM_Read_DMA(), and HAL_SRAM_Write_DMA().

void HAL_SRAM_DMA_XferErrorCallback ( MDMA_HandleTypeDef * hmdma )

DMA transfer complete error callback.

Parameters:
hmdma,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 249 of file stm32h7xx_hal_sram.c.

Referenced by HAL_SRAM_Read_DMA(), and HAL_SRAM_Write_DMA().

HAL_StatusTypeDef HAL_SRAM_Read_16b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads 16-bit buffer from SRAM memory.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to read start address
pDstBuffer,: Pointer to destination buffer
BufferSize,: Size of the buffer to read from memory
Return values:
HAL status

Definition at line 364 of file stm32h7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_READY, and SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Read_32b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads 32-bit buffer from SRAM memory.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to read start address
pDstBuffer,: Pointer to destination buffer
BufferSize,: Size of the buffer to read from memory
Return values:
HAL status

Definition at line 442 of file stm32h7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_READY, and SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Read_8b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint8_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads 8-bit buffer from SRAM memory.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to read start address
pDstBuffer,: Pointer to destination buffer
BufferSize,: Size of the buffer to read from memory
Return values:
HAL status

Definition at line 286 of file stm32h7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_READY, and SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Read_DMA | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads a Words data from the SRAM memory using DMA transfer.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to read start address
pDstBuffer,: Pointer to destination buffer
BufferSize,: Size of the buffer to read from memory
Return values:
HAL status

Definition at line 516 of file stm32h7xx_hal_sram.c.

References HAL_MDMA_Start_IT(), HAL_SRAM_DMA_XferCpltCallback(), HAL_SRAM_DMA_XferErrorCallback(), HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_READY, SRAM_HandleTypeDef::hmdma, SRAM_HandleTypeDef::State, __MDMA_HandleTypeDef::XferCpltCallback, and __MDMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SRAM_Write_16b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes 16-bit buffer to SRAM memory.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to write start address
pSrcBuffer,: Pointer to source buffer to write
BufferSize,: Size of the buffer to write to memory
Return values:
HAL status

Definition at line 400 of file stm32h7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_PROTECTED, HAL_SRAM_STATE_READY, and SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Write_32b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes 32-bit buffer to SRAM memory.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to write start address
pSrcBuffer,: Pointer to source buffer to write
BufferSize,: Size of the buffer to write to memory
Return values:
HAL status

Definition at line 476 of file stm32h7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_PROTECTED, HAL_SRAM_STATE_READY, and SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Write_8b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint8_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes 8-bit buffer to SRAM memory.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to write start address
pSrcBuffer,: Pointer to source buffer to write
BufferSize,: Size of the buffer to write to memory
Return values:
HAL status

Definition at line 322 of file stm32h7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_PROTECTED, HAL_SRAM_STATE_READY, and SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Write_DMA | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes a Words data buffer to SRAM memory using DMA transfer.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to write start address
pSrcBuffer,: Pointer to source buffer to write
BufferSize,: Size of the buffer to write to memory
Return values:
HAL status

Definition at line 549 of file stm32h7xx_hal_sram.c.

References HAL_MDMA_Start_IT(), HAL_SRAM_DMA_XferCpltCallback(), HAL_SRAM_DMA_XferErrorCallback(), HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_PROTECTED, HAL_SRAM_STATE_READY, SRAM_HandleTypeDef::hmdma, SRAM_HandleTypeDef::State, __MDMA_HandleTypeDef::XferCpltCallback, and __MDMA_HandleTypeDef::XferErrorCallback.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Control functions

Functions
Control functions
SRAM Exported Functions

Control functions. More...

Functions

HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Enable (SRAM_HandleTypeDef *hsram)
Enables dynamically SRAM write operation.
HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Disable (SRAM_HandleTypeDef *hsram)
Disables dynamically SRAM write operation.

Detailed Description

Control functions.

  ==============================================================================
                        ##### SRAM Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control dynamically
    the SRAM interface.

Function Documentation

HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable ( SRAM_HandleTypeDef * hsram )

Disables dynamically SRAM write operation.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
HAL status

Definition at line 627 of file stm32h7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_PROTECTED, SRAM_HandleTypeDef::Init, SRAM_HandleTypeDef::Instance, and SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable ( SRAM_HandleTypeDef * hsram )

Enables dynamically SRAM write operation.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
HAL status

Definition at line 604 of file stm32h7xx_hal_sram.c.

References HAL_SRAM_STATE_READY, SRAM_HandleTypeDef::Init, SRAM_HandleTypeDef::Instance, and SRAM_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
SRAM Exported Functions

Peripheral State functions. More...

Functions

HAL_SRAM_StateTypeDef HAL_SRAM_GetState (SRAM_HandleTypeDef *hsram)
Returns the SRAM controller state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### SRAM State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the SRAM controller
    and the data flow.

Function Documentation

HAL_SRAM_StateTypeDef HAL_SRAM_GetState ( SRAM_HandleTypeDef * hsram )

Returns the SRAM controller state.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
HAL state

Definition at line 672 of file stm32h7xx_hal_sram.c.

References SRAM_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SRAM Exported Types

Data Structures | Enumerations
SRAM Exported Types
SRAM

Data Structures

struct SRAM_HandleTypeDef
SRAM handle Structure definition. More...

Enumerations

enum HAL_SRAM_StateTypeDef {
HAL_SRAM_STATE_RESET = 0x00U, HAL_SRAM_STATE_READY = 0x01U, HAL_SRAM_STATE_BUSY = 0x02U, HAL_SRAM_STATE_ERROR = 0x03U,
HAL_SRAM_STATE_PROTECTED = 0x04U
}
HAL SRAM State structures definition. More...

Enumeration Type Documentation

enum HAL_SRAM_StateTypeDef

HAL SRAM State structures definition.

Enumerator:
HAL_SRAM_STATE_RESET

SRAM not yet initialized or disabled

HAL_SRAM_STATE_READY

SRAM initialized and ready for use

HAL_SRAM_STATE_BUSY

SRAM internal process is ongoing

HAL_SRAM_STATE_ERROR

SRAM error state

HAL_SRAM_STATE_PROTECTED

SRAM peripheral NORSRAM device write protected

Definition at line 65 of file stm32h7xx_hal_sram.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SRAM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SRAM_HandleTypeDef Struct Reference
SRAM Exported Types

SRAM handle Structure definition. More...

#include <stm32h7xx_hal_sram.h>

Data Fields

FMC_NORSRAM_TypeDef * | Instance
FMC_NORSRAM_EXTENDED_TypeDef * | Extended
FMC_NORSRAM_InitTypeDef | Init
HAL_LockTypeDef | Lock
__IO HAL_SRAM_StateTypeDef | State
MDMA_HandleTypeDef * hmdma

Detailed Description

SRAM handle Structure definition.

Definition at line 78 of file stm32h7xx_hal_sram.h.

Field Documentation

FMC_NORSRAM_EXTENDED_TypeDef* SRAM_HandleTypeDef::Extended

Extended mode register base address

Definition at line 82 of file stm32h7xx_hal_sram.h.

Referenced by HAL_SRAM_DeInit(), and HAL_SRAM_Init().

MDMA_HandleTypeDef* SRAM_HandleTypeDef::hmdma

Pointer DMA handler

Definition at line 90 of file stm32h7xx_hal_sram.h.

Referenced by HAL_SRAM_Read_DMA(), and HAL_SRAM_Write_DMA().

FMC_NORSRAM_InitTypeDef SRAM_HandleTypeDef::Init

SRAM device control configuration parameters

Definition at line 84 of file stm32h7xx_hal_sram.h.

Referenced by HAL_SRAM_DeInit(), HAL_SRAM_Init(), HAL_SRAM_WriteOperation_Disable(), and HAL_SRAM_WriteOperation_Enable().

FMC_NORSRAM_TypeDef* SRAM_HandleTypeDef::Instance

Register base address

Definition at line 80 of file stm32h7xx_hal_sram.h.

Referenced by HAL_SRAM_DeInit(), HAL_SRAM_Init(), HAL_SRAM_WriteOperation_Disable(), and HAL_SRAM_WriteOperation_Enable().

HAL_LockTypeDef SRAM_HandleTypeDef::Lock

SRAM locking object

Definition at line 86 of file stm32h7xx_hal_sram.h.

Referenced by HAL_SRAM_Init().

__IO HAL_SRAM_StateTypeDef SRAM_HandleTypeDef::State

SRAM device access state

Definition at line 88 of file stm32h7xx_hal_sram.h.

Referenced by HAL_SRAM_DeInit(), HAL_SRAM_GetState(), HAL_SRAM_Init(), HAL_SRAM_Read_16b(), HAL_SRAM_Read_32b(), HAL_SRAM_Read_8b(), HAL_SRAM_Read_DMA(), HAL_SRAM_Write_16b(), HAL_SRAM_Write_32b(), HAL_SRAM_Write_8b(), HAL_SRAM_Write_DMA(), HAL_SRAM_WriteOperation_Disable(), and HAL_SRAM_WriteOperation_Enable().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sram.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SRAM Exported Macros

Defines
SRAM Exported Macros
SRAM

Defines

#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
Reset SRAM handle state.

Define Documentation

#define __HAL_SRAM_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)

Reset SRAM handle state.

Parameters:
__HANDLE__,: SRAM handle
Return values:
None

Definition at line 109 of file stm32h7xx_hal_sram.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization/de-initialization methods

Functions
Initialization/de-initialization methods
SWPMI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SWPMI_Init (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.
HAL_StatusTypeDef | HAL_SWPMI_DeInit (SWPMI_HandleTypeDef *hswpmi)
De-initialize the SWPMI peripheral.
__weak void | HAL_SWPMI_MspInit (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI MSP.
__weak void | HAL_SWPMI_MspDeInit (SWPMI_HandleTypeDef *hswpmi)
DeInitialize the SWPMI MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the SWPMI peripheral.
      (+) De-initialize the SWPMI peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SWPMI_DeInit ( SWPMI_HandleTypeDef * hswpmi )

De-initialize the SWPMI peripheral.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL status

Definition at line 209 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_TRANSCEIVER_DISABLE, assert_param, SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_MspDeInit(), HAL_SWPMI_STATE_BUSY, HAL_SWPMI_STATE_RESET, SWPMI_HandleTypeDef::Instance, and SWPMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SWPMI_Init ( SWPMI_HandleTypeDef * hswpmi )

Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL status

Definition at line 146 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_TRANSCEIVER_ENABLE, assert_param, SWPMI_InitTypeDef::BitRate, SWPMI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SWPMI_ERROR_NONE, HAL_SWPMI_MspInit(), HAL_SWPMI_STATE_BUSY, HAL_SWPMI_STATE_READY, HAL_SWPMI_STATE_RESET, SWPMI_HandleTypeDef::Init, SWPMI_HandleTypeDef::Instance, IS_SWPMI_BITRATE_VALUE, IS_SWPMI_RX_BUFFERING_MODE, IS_SWPMI_TX_BUFFERING_MODE, IS_SWPMI_VOLTAGE_CLASS, SWPMI_HandleTypeDef::Lock, SWPMI_InitTypeDef::RxBufferingMode, SWPMI_HandleTypeDef::State, SWPMI_FLAG_RDYF, SWPMI_TIMEOUT_VALUE, SWPMI_WaitOnFlagSetUntilTimeout(), SWPMI_InitTypeDef::TxBufferingMode, and SWPMI_InitTypeDef::VoltageClass.

__weak void HAL_SWPMI_MspDeInit ( SWPMI_HandleTypeDef * hswpmi )

DeInitialize the SWPMI MSP.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 265 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_DeInit().

__weak void HAL_SWPMI_MspInit ( SWPMI_HandleTypeDef * hswpmi )

Initialize the SWPMI MSP.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 250 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_Init().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IO operation methods

Functions
IO operation methods
SWPMI Exported Functions

SWPMI Transmit/Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_SWPMI_Transmit (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Receive (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_DMAStop (SWPMI_HandleTypeDef *hswpmi)
Stop all DMA transfers.
HAL_StatusTypeDef | HAL_SWPMI_EnableLoopback (SWPMI_HandleTypeDef *hswpmi)
Enable the Loopback mode.
HAL_StatusTypeDef | HAL_SWPMI_DisableLoopback (SWPMI_HandleTypeDef *hswpmi)
Disable the Loopback mode.

Detailed Description

SWPMI Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation methods #####
 ===============================================================================
 [..]
    This subsection provides a set of functions allowing to manage the SWPMI
     data transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (++) Non-Blocking mode: The communication is performed using Interrupts
           or DMA. The end of the data processing will be indicated through the
           dedicated SWPMI Interrupt handler (HAL_SWPMI_IRQHandler()) when using Interrupt mode or
           the selected DMA channel interrupt handler when using DMA mode.
           The HAL_SWPMI_TxCpltCallback(), HAL_SWPMI_RxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or receive process.
           The HAL_SWPMI_ErrorCallback() user callback will be executed when a communication error is detected.

    (#) Blocking mode API's are:
        (++) HAL_SWPMI_Transmit()
        (++) HAL_SWPMI_Receive()

    (#) Non-Blocking mode API's with Interrupt are:
        (++) HAL_SWPMI_Transmit_IT()
        (++) HAL_SWPMI_Receive_IT()
        (++) HAL_SWPMI_IRQHandler()

    (#) Non-Blocking mode API's with DMA are:
        (++) HAL_SWPMI_Transmit_DMA()
        (++) HAL_SWPMI_Receive_DMA()
        (++) HAL_SWPMI_DMAPause()
        (++) HAL_SWPMI_DMAResume()
        (++) HAL_SWPMI_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non-Blocking mode:
        (++) HAL_SWPMI_TxHalfCpltCallback()
        (++) HAL_SWPMI_TxCpltCallback()
        (++) HAL_SWPMI_RxHalfCpltCallback()
        (++) HAL_SWPMI_RxCpltCallback()
        (++) HAL_SWPMI_ErrorCallback()

    (#) The capability to launch the above IO operations in loopback mode for
        user application verification:
        (++) HAL_SWPMI_EnableLoopback()
        (++) HAL_SWPMI_DisableLoopback()

Function Documentation

HAL_StatusTypeDef HAL_SWPMI_DisableLoopback ( SWPMI_HandleTypeDef * hswpmi )

Disable the Loopback mode.

Parameters:
hswpmi,: SWPMI handle
Note:
Loopback mode is to be used only for test purposes
Return values:
HAL_OK / HAL_BUSY

Definition at line 881 of file stm32h7xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SWPMI_DMAStop ( SWPMI_HandleTypeDef * hswpmi )

Stop all DMA transfers.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL_OK

Definition at line 814 of file stm32h7xx_hal_swpmi.c.

References HAL_DMA_Abort(), HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::hdmarx, SWPMI_HandleTypeDef::hdmatx, SWPMI_HandleTypeDef::Instance, and SWPMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SWPMI_EnableLoopback ( SWPMI_HandleTypeDef * hswpmi )

Enable the Loopback mode.

Parameters:
hswpmi,: SWPMI handle
Note:
Loopback mode is to be used only for test purposes
Return values:
HAL_OK / HAL_BUSY

Definition at line 851 of file stm32h7xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SWPMI_Receive | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hswpmi,: pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for SWPMI module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 444 of file stm32h7xx_hal_swpmi.c.

References HAL_GetTick(), HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::State, SWPMI_FLAG_RXBFF, SWPMI_FLAG_RXNE, SWPMI_IT_RIE, SWPMI_IT_RXBERIE, SWPMI_IT_RXBFIE, SWPMI_IT_RXOVRIE, and SWPMI_IT_SRIE.

HAL_StatusTypeDef HAL_SWPMI_Receive_DMA | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA interrupt.

Parameters:
hswpmi,: SWPMI handle
pData,: pointer to data buffer
Size,: amount of data to be received
Return values:
HAL status

Definition at line 742 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_ENABLE_IT, SWPMI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::hdmarx, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::pRxBuffPtr, SWPMI_HandleTypeDef::RxXferSize, SWPMI_HandleTypeDef::State, SWPMI_DMAError(), SWPMI_DMAReceiveCplt(), SWPMI_DMARxHalfCplt(), SWPMI_IT_RXBERIE, SWPMI_IT_RXOVRIE, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SWPMI_Receive_IT | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with interrupt.

Parameters:
hswpmi,: SWPMI handle
pData,: pointer to data buffer
Size,: amount of data to be received
Return values:
HAL status

Definition at line 606 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_ENABLE_IT, SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::pRxBuffPtr, SWPMI_HandleTypeDef::RxXferCount, SWPMI_HandleTypeDef::RxXferSize, SWPMI_HandleTypeDef::State, SWPMI_IT_RIE, SWPMI_IT_RXBERIE, SWPMI_IT_RXBFIE, and SWPMI_IT_RXOVRIE.

HAL_StatusTypeDef HAL_SWPMI_Transmit | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hswpmi,: pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for SWPMI module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 343 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_CLEAR_FLAG, __HAL_SWPMI_DISABLE_IT, HAL_GetTick(), HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::State, SWPMI_FLAG_TCF, SWPMI_FLAG_TXBEF, SWPMI_FLAG_TXE, SWPMI_FLAG_TXUNRF, SWPMI_IT_TCIE, SWPMI_IT_TIE, SWPMI_IT_TXBEIE, SWPMI_IT_TXUNRIE, and SWPMI_WaitOnFlagSetUntilTimeout().

HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA interrupt.

Parameters:
hswpmi,: SWPMI handle
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 667 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_ENABLE_IT, SWPMI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::hdmatx, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::pTxBuffPtr, SWPMI_HandleTypeDef::State, SWPMI_DMAError(), SWPMI_DMATransmitCplt(), SWPMI_DMATxHalfCplt(), SWPMI_IT_TXUNRIE, SWPMI_HandleTypeDef::TxXferCount, SWPMI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SWPMI_Transmit_IT | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with interrupt.

Parameters:
hswpmi,: pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for SWPMI module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 541 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_ENABLE_IT, SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::pTxBuffPtr, SWPMI_HandleTypeDef::State, SWPMI_IT_TCIE, SWPMI_IT_TIE, SWPMI_IT_TXBEIE, SWPMI_IT_TXUNRIE, SWPMI_HandleTypeDef::TxXferCount, and SWPMI_HandleTypeDef::TxXferSize.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SWPMI IRQ handler and callbacks

Functions
SWPMI IRQ handler and callbacks
SWPMI Exported Functions

SWPMI IRQ handler. More...

Functions

void | HAL_SWPMI_IRQHandler (SWPMI_HandleTypeDef *hswpmi)
Handle SWPMI interrupt request.
__weak void | HAL_SWPMI_TxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Transfer completed callback.
__weak void | HAL_SWPMI_TxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Half Transfer completed callback.
__weak void | HAL_SWPMI_RxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Transfer completed callback.
__weak void | HAL_SWPMI_RxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Half Transfer completed callback.
__weak void | HAL_SWPMI_ErrorCallback (SWPMI_HandleTypeDef *hswpmi)
SWPMI error callback.

Detailed Description

SWPMI IRQ handler.

  ==============================================================================
                      ##### SWPMI IRQ handler and callbacks  #####
  ==============================================================================
[..]  This section provides SWPMI IRQ handler and callback functions called within
      the IRQ handler.

Function Documentation

__weak void HAL_SWPMI_ErrorCallback ( SWPMI_HandleTypeDef * hswpmi )

SWPMI error callback.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 1145 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_IRQHandler(), SWPMI_DMAAbortOnError(), SWPMI_DMAError(), and SWPMI_DMATransmitCplt().

void HAL_SWPMI_IRQHandler ( SWPMI_HandleTypeDef * hswpmi )

Handle SWPMI interrupt request.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 928 of file stm32h7xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SWPMI_ERROR_CRC, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_ERROR_OVR, HAL_SWPMI_ERROR_UDR, HAL_SWPMI_ErrorCallback(), HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::hdmarx, SWPMI_HandleTypeDef::hdmatx, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::State, SWPMI_DMAAbortOnError(), SWPMI_EndReceive_IT(), SWPMI_EndTransmit_IT(), SWPMI_EndTransmitReceive_IT(), SWPMI_FLAG_RXBERF, SWPMI_FLAG_RXBFF, SWPMI_FLAG_RXNE, SWPMI_FLAG_RXOVRF, SWPMI_FLAG_TCF, SWPMI_FLAG_TXBEF, SWPMI_FLAG_TXE, SWPMI_FLAG_TXUNRF, SWPMI_IT_RIE, SWPMI_IT_RXBERIE, SWPMI_IT_RXBFIE, SWPMI_IT_RXOVRIE, SWPMI_IT_TCIE, SWPMI_IT_TIE, SWPMI_IT_TXBEIE, SWPMI_IT_TXUNRIE, SWPMI_Receive_IT(), SWPMI_Transmit_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

__weak void HAL_SWPMI_RxCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Rx Transfer completed callback.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 1115 of file stm32h7xx_hal_swpmi.c.

Referenced by SWPMI_DMAReceiveCplt(), and SWPMI_Receive_IT().

__weak void HAL_SWPMI_RxHalfCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Rx Half Transfer completed callback.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 1130 of file stm32h7xx_hal_swpmi.c.

Referenced by SWPMI_DMARxHalfCplt().

__weak void HAL_SWPMI_TxCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Tx Transfer completed callback.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 1085 of file stm32h7xx_hal_swpmi.c.

Referenced by SWPMI_DMATransmitCplt(), and SWPMI_EndTransmit_IT().

__weak void HAL_SWPMI_TxHalfCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Tx Half Transfer completed callback.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 1100 of file stm32h7xx_hal_swpmi.c.

Referenced by SWPMI_DMATxHalfCplt().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control methods

Functions
Peripheral Control methods
SWPMI Exported Functions

SWPMI control functions. More...

Functions

HAL_SWPMI_StateTypeDef | HAL_SWPMI_GetState (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI handle state.
uint32_t | HAL_SWPMI_GetError (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI error code.

Detailed Description

SWPMI control functions.

 ===============================================================================
                      ##### Peripheral Control methods #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the SWPMI.
     (+) HAL_SWPMI_GetState() API is helpful to check in run-time the state of the SWPMI peripheral
     (+) HAL_SWPMI_GetError() API is helpful to check in run-time the error state of the SWPMI peripheral

Function Documentation

uint32_t HAL_SWPMI_GetError ( SWPMI_HandleTypeDef * hswpmi )

Return the SWPMI error code.

Parameters:
hswpmi : pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for the specified SWPMI.
Return values:
SWPMI Error Code

Definition at line 1191 of file stm32h7xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::ErrorCode.

HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState ( SWPMI_HandleTypeDef * hswpmi )

Return the SWPMI handle state.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL state

Definition at line 1179 of file stm32h7xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SWPMI Exported Functions

Modules | Functions
SWPMI Exported Functions
SWPMI

Modules

Initialization/de-initialization methods

Initialization and Configuration functions.

IO operation methods

SWPMI Transmit/Receive functions.

SWPMI IRQ handler and callbacks

SWPMI IRQ handler.

Peripheral Control methods

SWPMI control functions.

Functions

HAL_StatusTypeDef | HAL_SWPMI_Init (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.
HAL_StatusTypeDef | HAL_SWPMI_DeInit (SWPMI_HandleTypeDef *hswpmi)
De-initialize the SWPMI peripheral.
void | HAL_SWPMI_MspInit (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI MSP.
void | HAL_SWPMI_MspDeInit (SWPMI_HandleTypeDef *hswpmi)
DeInitialize the SWPMI MSP.
HAL_StatusTypeDef | HAL_SWPMI_Transmit (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Receive (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_DMAStop (SWPMI_HandleTypeDef *hswpmi)
Stop all DMA transfers.
HAL_StatusTypeDef | HAL_SWPMI_EnableLoopback (SWPMI_HandleTypeDef *hswpmi)
Enable the Loopback mode.
HAL_StatusTypeDef | HAL_SWPMI_DisableLoopback (SWPMI_HandleTypeDef *hswpmi)
Disable the Loopback mode.
void | HAL_SWPMI_IRQHandler (SWPMI_HandleTypeDef *hswpmi)
Handle SWPMI interrupt request.
void | HAL_SWPMI_TxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Transfer completed callback.
void | HAL_SWPMI_TxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Half Transfer completed callback.
void | HAL_SWPMI_RxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Transfer completed callback.
void | HAL_SWPMI_RxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Half Transfer completed callback.
void | HAL_SWPMI_ErrorCallback (SWPMI_HandleTypeDef *hswpmi)
SWPMI error callback.
HAL_SWPMI_StateTypeDef | HAL_SWPMI_GetState (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI handle state.
uint32_t | HAL_SWPMI_GetError (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI error code.

Function Documentation

HAL_StatusTypeDef HAL_SWPMI_DeInit ( SWPMI_HandleTypeDef * hswpmi )

De-initialize the SWPMI peripheral.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL status

Definition at line 209 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_TRANSCEIVER_DISABLE, assert_param, SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_MspDeInit(), HAL_SWPMI_STATE_BUSY, HAL_SWPMI_STATE_RESET, SWPMI_HandleTypeDef::Instance, and SWPMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SWPMI_DisableLoopback ( SWPMI_HandleTypeDef * hswpmi )

Disable the Loopback mode.

Parameters:
hswpmi,: SWPMI handle
Note:
Loopback mode is to be used only for test purposes
Return values:
HAL_OK / HAL_BUSY

Definition at line 881 of file stm32h7xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SWPMI_DMAStop ( SWPMI_HandleTypeDef * hswpmi )

Stop all DMA transfers.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL_OK

Definition at line 814 of file stm32h7xx_hal_swpmi.c.

References HAL_DMA_Abort(), HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::hdmarx, SWPMI_HandleTypeDef::hdmatx, SWPMI_HandleTypeDef::Instance, and SWPMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SWPMI_EnableLoopback ( SWPMI_HandleTypeDef * hswpmi )

Enable the Loopback mode.

Parameters:
hswpmi,: SWPMI handle
Note:
Loopback mode is to be used only for test purposes
Return values:
HAL_OK / HAL_BUSY

Definition at line 851 of file stm32h7xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::Instance.

void HAL_SWPMI_ErrorCallback ( SWPMI_HandleTypeDef * hswpmi )

SWPMI error callback.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 1145 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_IRQHandler(), SWPMI_DMAAbortOnError(), SWPMI_DMAError(), and SWPMI_DMATransmitCplt().

uint32_t HAL_SWPMI_GetError ( SWPMI_HandleTypeDef * hswpmi )

Return the SWPMI error code.

Parameters:
hswpmi : pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for the specified SWPMI.
Return values:
SWPMI Error Code

Definition at line 1191 of file stm32h7xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::ErrorCode.

HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState ( SWPMI_HandleTypeDef * hswpmi )

Return the SWPMI handle state.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL state

Definition at line 1179 of file stm32h7xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SWPMI_Init ( SWPMI_HandleTypeDef * hswpmi )

Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL status

Definition at line 146 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_TRANSCEIVER_ENABLE, assert_param, SWPMI_InitTypeDef::BitRate, SWPMI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SWPMI_ERROR_NONE, HAL_SWPMI_MspInit(), HAL_SWPMI_STATE_BUSY, HAL_SWPMI_STATE_READY, HAL_SWPMI_STATE_RESET, SWPMI_HandleTypeDef::Init, SWPMI_HandleTypeDef::Instance, IS_SWPMI_BITRATE_VALUE, IS_SWPMI_RX_BUFFERING_MODE, IS_SWPMI_TX_BUFFERING_MODE, IS_SWPMI_VOLTAGE_CLASS, SWPMI_HandleTypeDef::Lock, SWPMI_InitTypeDef::RxBufferingMode, SWPMI_HandleTypeDef::State, SWPMI_FLAG_RDYF, SWPMI_TIMEOUT_VALUE, SWPMI_WaitOnFlagSetUntilTimeout(), SWPMI_InitTypeDef::TxBufferingMode, and SWPMI_InitTypeDef::VoltageClass.

void HAL_SWPMI_IRQHandler ( SWPMI_HandleTypeDef * hswpmi )

Handle SWPMI interrupt request.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 928 of file stm32h7xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SWPMI_ERROR_CRC, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_ERROR_OVR, HAL_SWPMI_ERROR_UDR, HAL_SWPMI_ErrorCallback(), HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::hdmarx, SWPMI_HandleTypeDef::hdmatx, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::State, SWPMI_DMAAbortOnError(), SWPMI_EndReceive_IT(), SWPMI_EndTransmit_IT(), SWPMI_EndTransmitReceive_IT(), SWPMI_FLAG_RXBERF, SWPMI_FLAG_RXBFF, SWPMI_FLAG_RXNE, SWPMI_FLAG_RXOVRF, SWPMI_FLAG_TCF, SWPMI_FLAG_TXBEF, SWPMI_FLAG_TXE, SWPMI_FLAG_TXUNRF, SWPMI_IT_RIE, SWPMI_IT_RXBERIE, SWPMI_IT_RXBFIE, SWPMI_IT_RXOVRIE, SWPMI_IT_TCIE, SWPMI_IT_TIE, SWPMI_IT_TXBEIE, SWPMI_IT_TXUNRIE, SWPMI_Receive_IT(), SWPMI_Transmit_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SWPMI_MspDeInit ( SWPMI_HandleTypeDef * hswpmi )

DeInitialize the SWPMI MSP.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 265 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_DeInit().

void HAL_SWPMI_MspInit ( SWPMI_HandleTypeDef * hswpmi )

Initialize the SWPMI MSP.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 250 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_Init().

HAL_StatusTypeDef HAL_SWPMI_Receive | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hswpmi,: pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for SWPMI module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 444 of file stm32h7xx_hal_swpmi.c.

References HAL_GetTick(), HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::State, SWPMI_FLAG_RXBFF, SWPMI_FLAG_RXNE, SWPMI_IT_RIE, SWPMI_IT_RXBERIE, SWPMI_IT_RXBFIE, SWPMI_IT_RXOVRIE, and SWPMI_IT_SRIE.

HAL_StatusTypeDef HAL_SWPMI_Receive_DMA | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA interrupt.

Parameters:
hswpmi,: SWPMI handle
pData,: pointer to data buffer
Size,: amount of data to be received
Return values:
HAL status

Definition at line 742 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_ENABLE_IT, SWPMI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::hdmarx, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::pRxBuffPtr, SWPMI_HandleTypeDef::RxXferSize, SWPMI_HandleTypeDef::State, SWPMI_DMAError(), SWPMI_DMAReceiveCplt(), SWPMI_DMARxHalfCplt(), SWPMI_IT_RXBERIE, SWPMI_IT_RXOVRIE, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SWPMI_Receive_IT | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with interrupt.

Parameters:
hswpmi,: SWPMI handle
pData,: pointer to data buffer
Size,: amount of data to be received
Return values:
HAL status

Definition at line 606 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_ENABLE_IT, SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::pRxBuffPtr, SWPMI_HandleTypeDef::RxXferCount, SWPMI_HandleTypeDef::RxXferSize, SWPMI_HandleTypeDef::State, SWPMI_IT_RIE, SWPMI_IT_RXBERIE, SWPMI_IT_RXBFIE, and SWPMI_IT_RXOVRIE.

void HAL_SWPMI_RxCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Rx Transfer completed callback.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 1115 of file stm32h7xx_hal_swpmi.c.

Referenced by SWPMI_DMAReceiveCplt(), and SWPMI_Receive_IT().

void HAL_SWPMI_RxHalfCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Rx Half Transfer completed callback.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 1130 of file stm32h7xx_hal_swpmi.c.

Referenced by SWPMI_DMARxHalfCplt().

HAL_StatusTypeDef HAL_SWPMI_Transmit | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hswpmi,: pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for SWPMI module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 343 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_CLEAR_FLAG, __HAL_SWPMI_DISABLE_IT, HAL_GetTick(), HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::State, SWPMI_FLAG_TCF, SWPMI_FLAG_TXBEF, SWPMI_FLAG_TXE, SWPMI_FLAG_TXUNRF, SWPMI_IT_TCIE, SWPMI_IT_TIE, SWPMI_IT_TXBEIE, SWPMI_IT_TXUNRIE, and SWPMI_WaitOnFlagSetUntilTimeout().

HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA interrupt.

Parameters:
hswpmi,: SWPMI handle
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 667 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_ENABLE_IT, SWPMI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::hdmatx, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::pTxBuffPtr, SWPMI_HandleTypeDef::State, SWPMI_DMAError(), SWPMI_DMATransmitCplt(), SWPMI_DMATxHalfCplt(), SWPMI_IT_TXUNRIE, SWPMI_HandleTypeDef::TxXferCount, SWPMI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SWPMI_Transmit_IT | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with interrupt.

Parameters:
hswpmi,: pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for SWPMI module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 541 of file stm32h7xx_hal_swpmi.c.

References __HAL_SWPMI_ENABLE_IT, SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::pTxBuffPtr, SWPMI_HandleTypeDef::State, SWPMI_IT_TCIE, SWPMI_IT_TIE, SWPMI_IT_TXBEIE, SWPMI_IT_TXUNRIE, SWPMI_HandleTypeDef::TxXferCount, and SWPMI_HandleTypeDef::TxXferSize.

void HAL_SWPMI_TxCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Tx Transfer completed callback.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 1085 of file stm32h7xx_hal_swpmi.c.

Referenced by SWPMI_DMATransmitCplt(), and SWPMI_EndTransmit_IT().

void HAL_SWPMI_TxHalfCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Tx Half Transfer completed callback.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 1100 of file stm32h7xx_hal_swpmi.c.

Referenced by SWPMI_DMATxHalfCplt().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SWPMI Private Functions

Functions
SWPMI Private Functions
SWPMI

Functions

static HAL_StatusTypeDef | SWPMI_Transmit_IT (SWPMI_HandleTypeDef *hswpmi)
Transmit an amount of data in interrupt mode.
static HAL_StatusTypeDef | SWPMI_EndTransmit_IT (SWPMI_HandleTypeDef *hswpmi)
Wraps up transmission in non-blocking mode.
static HAL_StatusTypeDef | SWPMI_Receive_IT (SWPMI_HandleTypeDef *hswpmi)
Receive an amount of data in interrupt mode.
static HAL_StatusTypeDef | SWPMI_EndReceive_IT (SWPMI_HandleTypeDef *hswpmi)
Wraps up reception in non-blocking mode.
static HAL_StatusTypeDef | SWPMI_EndTransmitReceive_IT (SWPMI_HandleTypeDef *hswpmi)
Wraps up transmission and reception in non-blocking mode.
static void | SWPMI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI transmit process complete callback.
static void | SWPMI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI transmit process half complete callback.
static void | SWPMI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI receive process complete callback.
static void | SWPMI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI receive process half complete callback.
static void | SWPMI_DMAError (DMA_HandleTypeDef *hdma)
DMA SWPMI communication error callback.
static void | SWPMI_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SWPMI communication abort callback.
static HAL_StatusTypeDef | SWPMI_WaitOnFlagSetUntilTimeout (SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout)
Handle SWPMI Communication Timeout.

Function Documentation

static void SWPMI_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA SWPMI communication abort callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1478 of file stm32h7xx_hal_swpmi.c.

References HAL_SWPMI_ErrorCallback(), HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::RxXferCount, SWPMI_HandleTypeDef::State, and SWPMI_HandleTypeDef::TxXferCount.

Referenced by HAL_SWPMI_IRQHandler().

static void SWPMI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SWPMI communication error callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1461 of file stm32h7xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_DMA, HAL_SWPMI_ErrorCallback(), HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::RxXferCount, SWPMI_HandleTypeDef::State, and SWPMI_HandleTypeDef::TxXferCount.

Referenced by HAL_SWPMI_Receive_DMA(), and HAL_SWPMI_Transmit_DMA().

static void SWPMI_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SWPMI receive process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1418 of file stm32h7xx_hal_swpmi.c.

References HAL_SWPMI_RxCpltCallback(), HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, SWPMI_HandleTypeDef::RxXferCount, and SWPMI_HandleTypeDef::State.

Referenced by HAL_SWPMI_Receive_DMA().

static void SWPMI_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SWPMI receive process half complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 1449 of file stm32h7xx_hal_swpmi.c.

References HAL_SWPMI_RxHalfCpltCallback().

Referenced by HAL_SWPMI_Receive_DMA().

static void SWPMI_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SWPMI transmit process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1354 of file stm32h7xx_hal_swpmi.c.

References HAL_GetTick(), HAL_SWPMI_ErrorCallback(), HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, HAL_SWPMI_TxCpltCallback(), SWPMI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, SWPMI_HandleTypeDef::State, SWPMI_FLAG_TXBEF, SWPMI_TIMEOUT_VALUE, SWPMI_WaitOnFlagSetUntilTimeout(), and SWPMI_HandleTypeDef::TxXferCount.

Referenced by HAL_SWPMI_Transmit_DMA().

static void SWPMI_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SWPMI transmit process half complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 1405 of file stm32h7xx_hal_swpmi.c.

References HAL_SWPMI_TxHalfCpltCallback().

Referenced by HAL_SWPMI_Transmit_DMA().

static HAL_StatusTypeDef SWPMI_EndReceive_IT ( SWPMI_HandleTypeDef * hswpmi ) [static]

Wraps up reception in non-blocking mode.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL | status
HAL | status

Definition at line 1303 of file stm32h7xx_hal_swpmi.c.

References HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::State, SWPMI_FLAG_RXBFF, SWPMI_IT_RIE, SWPMI_IT_RXBERIE, SWPMI_IT_RXBFIE, and SWPMI_IT_RXOVRIE.

Referenced by HAL_SWPMI_IRQHandler().

static HAL_StatusTypeDef SWPMI_EndTransmit_IT ( SWPMI_HandleTypeDef * hswpmi ) [static]

Wraps up transmission in non-blocking mode.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL | status
HAL | status

Definition at line 1247 of file stm32h7xx_hal_swpmi.c.

References HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, HAL_SWPMI_TxCpltCallback(), SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::State, SWPMI_FLAG_TXBEF, SWPMI_IT_TIE, SWPMI_IT_TXBEIE, and SWPMI_IT_TXUNRIE.

Referenced by HAL_SWPMI_IRQHandler().

static HAL_StatusTypeDef SWPMI_EndTransmitReceive_IT ( SWPMI_HandleTypeDef * hswpmi ) [static]

Wraps up transmission and reception in non-blocking mode.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL | status
HAL | status

Definition at line 1329 of file stm32h7xx_hal_swpmi.c.

References HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::State, SWPMI_FLAG_TCF, and SWPMI_IT_TCIE.

Referenced by HAL_SWPMI_IRQHandler().

static HAL_StatusTypeDef SWPMI_Receive_IT ( SWPMI_HandleTypeDef * hswpmi ) [static]

Receive an amount of data in interrupt mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Receive_IT()
Parameters:
hswpmi,: SWPMI handle
Return values:
HAL status

Definition at line 1275 of file stm32h7xx_hal_swpmi.c.

References HAL_SWPMI_RxCpltCallback(), HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX_RX, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::pRxBuffPtr, SWPMI_HandleTypeDef::RxXferCount, and SWPMI_HandleTypeDef::State.

Referenced by HAL_SWPMI_IRQHandler().

static HAL_StatusTypeDef SWPMI_Transmit_IT ( SWPMI_HandleTypeDef * hswpmi ) [static]

Transmit an amount of data in interrupt mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Transmit_IT()
Parameters:
hswpmi,: SWPMI handle
Return values:
HAL status

Definition at line 1216 of file stm32h7xx_hal_swpmi.c.

References HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::pTxBuffPtr, SWPMI_HandleTypeDef::State, SWPMI_IT_TIE, SWPMI_IT_TXUNRIE, and SWPMI_HandleTypeDef::TxXferCount.

Referenced by HAL_SWPMI_IRQHandler().

static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t | Flag,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle SWPMI Communication Timeout.

Parameters:
hswpmi,: SWPMI handle
Flag,: specifies the SWPMI flag to check.
Tickstart | Tick start value
Timeout | timeout duration.
Return values:
HAL status

Definition at line 1498 of file stm32h7xx_hal_swpmi.c.

References HAL_GetTick(), HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, and SWPMI_HandleTypeDef::State.

Referenced by HAL_SWPMI_Init(), HAL_SWPMI_Transmit(), and SWPMI_DMATransmitCplt().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SWPMI Exported Types

Data Structures | Enumerations
SWPMI Exported Types
SWPMI

Data Structures

struct | SWPMI_InitTypeDef
SWPMI Init Structure definition. More...
struct | SWPMI_HandleTypeDef
SWPMI handle Structure definition. More...

Enumerations

enum HAL_SWPMI_StateTypeDef {
HAL_SWPMI_STATE_RESET = 0x00, HAL_SWPMI_STATE_READY = 0x01, HAL_SWPMI_STATE_BUSY = 0x02, HAL_SWPMI_STATE_BUSY_TX = 0x12,
HAL_SWPMI_STATE_BUSY_RX = 0x22, HAL_SWPMI_STATE_BUSY_TX_RX = 0x32, HAL_SWPMI_STATE_TIMEOUT = 0x03, HAL_SWPMI_STATE_ERROR = 0x04
}
HAL SWPMI State structures definition. More...

Enumeration Type Documentation

enum HAL_SWPMI_StateTypeDef

HAL SWPMI State structures definition.

Enumerator:
HAL_SWPMI_STATE_RESET

Peripheral Reset state

HAL_SWPMI_STATE_READY

Peripheral Initialized and ready for use

HAL_SWPMI_STATE_BUSY

an internal process is ongoing

HAL_SWPMI_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_SWPMI_STATE_BUSY_RX

Data Reception process is ongoing

HAL_SWPMI_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing

HAL_SWPMI_STATE_TIMEOUT

Timeout state

HAL_SWPMI_STATE_ERROR

Error

Definition at line 88 of file stm32h7xx_hal_swpmi.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SWPMI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SWPMI_InitTypeDef Struct Reference
SWPMI Exported Types

SWPMI Init Structure definition. More...

#include <stm32h7xx_hal_swpmi.h>

Data Fields

uint32_t | VoltageClass
uint32_t | BitRate
uint32_t | TxBufferingMode
uint32_t | RxBufferingMode

Detailed Description

SWPMI Init Structure definition.

Definition at line 65 of file stm32h7xx_hal_swpmi.h.

Field Documentation

uint32_t SWPMI_InitTypeDef::BitRate

Specifies the SWPMI Bitrate. This parameter must be a number between 0 and 63. The Bitrate is computed using the following formula: SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4)

Definition at line 70 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

uint32_t SWPMI_InitTypeDef::RxBufferingMode

Specifies the reception buffering mode. This parameter can be a value of SWPMI Rx Buffering Mode

Definition at line 79 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

uint32_t SWPMI_InitTypeDef::TxBufferingMode

Specifies the transmission buffering mode. This parameter can be a value of SWPMI Tx Buffering Mode

Definition at line 76 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

uint32_t SWPMI_InitTypeDef::VoltageClass

Specifies the SWP Voltage Class. This parameter can be a value of SWPMI Voltage Class

Definition at line 67 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_swpmi.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SWPMI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SWPMI_HandleTypeDef Struct Reference
SWPMI Exported Types

SWPMI handle Structure definition. More...

#include <stm32h7xx_hal_swpmi.h>

Data Fields

SWPMI_TypeDef * | Instance
SWPMI_InitTypeDef Init
uint32_t * | pTxBuffPtr
uint32_t | TxXferSize
uint32_t | TxXferCount
uint32_t * | pRxBuffPtr
uint32_t | RxXferSize
uint32_t | RxXferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SWPMI_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

SWPMI handle Structure definition.

Definition at line 103 of file stm32h7xx_hal_swpmi.h.

Field Documentation

__IO uint32_t SWPMI_HandleTypeDef::ErrorCode

Definition at line 129 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_DeInit(), HAL_SWPMI_GetError(), HAL_SWPMI_Init(), HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Receive_IT(), HAL_SWPMI_Transmit_DMA(), HAL_SWPMI_Transmit_IT(), and SWPMI_DMAError().

DMA_HandleTypeDef* SWPMI_HandleTypeDef::hdmarx

Definition at line 123 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_DMAStop(), HAL_SWPMI_IRQHandler(), and HAL_SWPMI_Receive_DMA().

DMA_HandleTypeDef* SWPMI_HandleTypeDef::hdmatx

Definition at line 121 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_DMAStop(), HAL_SWPMI_IRQHandler(), and HAL_SWPMI_Transmit_DMA().

SWPMI_InitTypeDef SWPMI_HandleTypeDef::Init

Definition at line 107 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

SWPMI_TypeDef* SWPMI_HandleTypeDef::Instance

Definition at line 105 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_DeInit(), HAL_SWPMI_DisableLoopback(), HAL_SWPMI_DMAStop(), HAL_SWPMI_EnableLoopback(), HAL_SWPMI_Init(), HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Receive_IT(), HAL_SWPMI_Transmit(), HAL_SWPMI_Transmit_DMA(), HAL_SWPMI_Transmit_IT(), SWPMI_DMAReceiveCplt(), SWPMI_DMATransmitCplt(), SWPMI_EndReceive_IT(), SWPMI_EndTransmit_IT(), SWPMI_EndTransmitReceive_IT(), SWPMI_Receive_IT(), SWPMI_Transmit_IT(), and SWPMI_WaitOnFlagSetUntilTimeout().

HAL_LockTypeDef SWPMI_HandleTypeDef::Lock

Definition at line 125 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

uint32_t* SWPMI_HandleTypeDef::pRxBuffPtr

Definition at line 115 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Receive_IT(), and SWPMI_Receive_IT().

uint32_t* SWPMI_HandleTypeDef::pTxBuffPtr

Definition at line 109 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Transmit_DMA(), HAL_SWPMI_Transmit_IT(), and SWPMI_Transmit_IT().

uint32_t SWPMI_HandleTypeDef::RxXferCount

Definition at line 119 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Receive_IT(), SWPMI_DMAAbortOnError(), SWPMI_DMAError(), SWPMI_DMAReceiveCplt(), and SWPMI_Receive_IT().

uint32_t SWPMI_HandleTypeDef::RxXferSize

Definition at line 117 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Receive_DMA(), and HAL_SWPMI_Receive_IT().

__IO HAL_SWPMI_StateTypeDef SWPMI_HandleTypeDef::State

Definition at line 127 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_DeInit(), HAL_SWPMI_DMAStop(), HAL_SWPMI_GetState(), HAL_SWPMI_Init(), HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Receive_IT(), HAL_SWPMI_Transmit(), HAL_SWPMI_Transmit_DMA(), HAL_SWPMI_Transmit_IT(), SWPMI_DMAAbortOnError(), SWPMI_DMAError(), SWPMI_DMAReceiveCplt(), SWPMI_DMATransmitCplt(), SWPMI_EndReceive_IT(), SWPMI_EndTransmit_IT(), SWPMI_EndTransmitReceive_IT(), SWPMI_Receive_IT(), SWPMI_Transmit_IT(), and SWPMI_WaitOnFlagSetUntilTimeout().

uint32_t SWPMI_HandleTypeDef::TxXferCount

Definition at line 113 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Transmit_DMA(), HAL_SWPMI_Transmit_IT(), SWPMI_DMAAbortOnError(), SWPMI_DMAError(), SWPMI_DMATransmitCplt(), and SWPMI_Transmit_IT().

uint32_t SWPMI_HandleTypeDef::TxXferSize

Definition at line 111 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Transmit_DMA(), and HAL_SWPMI_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_swpmi.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SWPMI Error Code Bitmap

Defines
SWPMI Error Code Bitmap
SWPMI Exported Constants

Defines

#define | HAL_SWPMI_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_SWPMI_ERROR_CRC ((uint32_t)0x00000004)
#define | HAL_SWPMI_ERROR_OVR ((uint32_t)0x00000008)
#define | HAL_SWPMI_ERROR_UDR ((uint32_t)0x0000000C)
#define | HAL_SWPMI_ERROR_DMA ((uint32_t)0x00000010)

Define Documentation

#define HAL_SWPMI_ERROR_CRC ((uint32_t)0x00000004)

frame error

Definition at line 147 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler().

#define HAL_SWPMI_ERROR_DMA ((uint32_t)0x00000010)

DMA transfer error

Definition at line 150 of file stm32h7xx_hal_swpmi.h.

Referenced by SWPMI_DMAError().

#define HAL_SWPMI_ERROR_NONE ((uint32_t)0x00000000)

No error

Definition at line 146 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_DeInit(), HAL_SWPMI_Init(), HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Receive_IT(), HAL_SWPMI_Transmit_DMA(), and HAL_SWPMI_Transmit_IT().

#define HAL_SWPMI_ERROR_OVR ((uint32_t)0x00000008)

Overrun error

Definition at line 148 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler().

#define HAL_SWPMI_ERROR_UDR ((uint32_t)0x0000000C)

Underrun error

Definition at line 149 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SWPMI Voltage Class

Defines
SWPMI Voltage Class
SWPMI Exported Constants

Defines

#define | SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000)
#define | SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS

Define Documentation

#define SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS

Definition at line 159 of file stm32h7xx_hal_swpmi.h.

#define SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000)

Definition at line 158 of file stm32h7xx_hal_swpmi.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SWPMI Tx Buffering Mode

Defines
SWPMI Tx Buffering Mode
SWPMI Exported Constants

Defines

#define | SWPMI_TX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_TX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_TX_MULTI_SOFTWAREBUFFER SWPMI_CR_TXMODE

Define Documentation

#define SWPMI_TX_MULTI_SOFTWAREBUFFER SWPMI_CR_TXMODE

Definition at line 169 of file stm32h7xx_hal_swpmi.h.

#define SWPMI_TX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)

Definition at line 167 of file stm32h7xx_hal_swpmi.h.

#define SWPMI_TX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)

Definition at line 168 of file stm32h7xx_hal_swpmi.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SWPMI Rx Buffering Mode

Defines
SWPMI Rx Buffering Mode
SWPMI Exported Constants

Defines

#define | SWPMI_RX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_RX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_RX_MULTI_SOFTWAREBUFFER SWPMI_CR_RXMODE

Define Documentation

#define SWPMI_RX_MULTI_SOFTWAREBUFFER SWPMI_CR_RXMODE

Definition at line 179 of file stm32h7xx_hal_swpmi.h.

#define SWPMI_RX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)

Definition at line 177 of file stm32h7xx_hal_swpmi.h.

#define SWPMI_RX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)

Definition at line 178 of file stm32h7xx_hal_swpmi.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SWPMI Status Flags

Defines
SWPMI Status Flags
SWPMI Exported Constants

Elements values convention: 0xXXXXXXXX. More...

Defines

#define | SWPMI_FLAG_RXBFF SWPMI_ISR_RXBFF
#define | SWPMI_FLAG_TXBEF SWPMI_ISR_TXBEF
#define | SWPMI_FLAG_RXBERF SWPMI_ISR_RXBERF
#define | SWPMI_FLAG_RXOVRF SWPMI_ISR_RXOVRF
#define | SWPMI_FLAG_TXUNRF SWPMI_ISR_TXUNRF
#define | SWPMI_FLAG_RXNE SWPMI_ISR_RXNE
#define | SWPMI_FLAG_TXE SWPMI_ISR_TXE
#define | SWPMI_FLAG_TCF SWPMI_ISR_TCF
#define | SWPMI_FLAG_SRF SWPMI_ISR_SRF
#define | SWPMI_FLAG_SUSP SWPMI_ISR_SUSP
#define | SWPMI_FLAG_DEACTF SWPMI_ISR_DEACTF
#define | SWPMI_FLAG_RDYF SWPMI_ISR_RDYF

Detailed Description

Elements values convention: 0xXXXXXXXX.

  • 0xXXXXXXXX : Flag mask in the ISR register

Define Documentation

#define SWPMI_FLAG_DEACTF SWPMI_ISR_DEACTF

Definition at line 199 of file stm32h7xx_hal_swpmi.h.

#define SWPMI_FLAG_RDYF SWPMI_ISR_RDYF

Definition at line 200 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

#define SWPMI_FLAG_RXBERF SWPMI_ISR_RXBERF

Definition at line 191 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler().

#define SWPMI_FLAG_RXBFF SWPMI_ISR_RXBFF

Definition at line 189 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive(), and SWPMI_EndReceive_IT().

#define SWPMI_FLAG_RXNE SWPMI_ISR_RXNE

Definition at line 194 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), and HAL_SWPMI_Receive().

#define SWPMI_FLAG_RXOVRF SWPMI_ISR_RXOVRF

Definition at line 192 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler().

#define SWPMI_FLAG_SRF SWPMI_ISR_SRF

Definition at line 197 of file stm32h7xx_hal_swpmi.h.

#define SWPMI_FLAG_SUSP SWPMI_ISR_SUSP

Definition at line 198 of file stm32h7xx_hal_swpmi.h.

#define SWPMI_FLAG_TCF SWPMI_ISR_TCF

Definition at line 196 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Transmit(), and SWPMI_EndTransmitReceive_IT().

#define SWPMI_FLAG_TXBEF SWPMI_ISR_TXBEF

Definition at line 190 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Transmit(), SWPMI_DMATransmitCplt(), and SWPMI_EndTransmit_IT().

#define SWPMI_FLAG_TXE SWPMI_ISR_TXE

Definition at line 195 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), and HAL_SWPMI_Transmit().

#define SWPMI_FLAG_TXUNRF SWPMI_ISR_TXUNRF

Definition at line 193 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), and HAL_SWPMI_Transmit().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SWPMI Interrupts Definition

Defines
SWPMI Interrupts Definition
SWPMI Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | SWPMI_IT_RDYIE SWPMI_IER_RDYIE
#define | SWPMI_IT_SRIE SWPMI_IER_SRIE
#define | SWPMI_IT_TCIE SWPMI_IER_TCIE
#define | SWPMI_IT_TIE SWPMI_IER_TIE
#define | SWPMI_IT_RIE SWPMI_IER_RIE
#define | SWPMI_IT_TXUNRIE SWPMI_IER_TXUNRIE
#define | SWPMI_IT_RXOVRIE SWPMI_IER_RXOVRIE
#define | SWPMI_IT_RXBERIE SWPMI_IER_RXBERIE
#define | SWPMI_IT_TXBEIE SWPMI_IER_TXBEIE
#define | SWPMI_IT_RXBFIE SWPMI_IER_RXBFIE

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the IER register

Define Documentation

#define SWPMI_IT_RDYIE SWPMI_IER_RDYIE

Definition at line 210 of file stm32h7xx_hal_swpmi.h.

#define SWPMI_IT_RIE SWPMI_IER_RIE

Definition at line 214 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive(), HAL_SWPMI_Receive_IT(), and SWPMI_EndReceive_IT().

#define SWPMI_IT_RXBERIE SWPMI_IER_RXBERIE

Definition at line 217 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Receive_IT(), and SWPMI_EndReceive_IT().

#define SWPMI_IT_RXBFIE SWPMI_IER_RXBFIE

Definition at line 219 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive(), HAL_SWPMI_Receive_IT(), and SWPMI_EndReceive_IT().

#define SWPMI_IT_RXOVRIE SWPMI_IER_RXOVRIE

Definition at line 216 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Receive_IT(), and SWPMI_EndReceive_IT().

#define SWPMI_IT_SRIE SWPMI_IER_SRIE

Definition at line 211 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Receive().

#define SWPMI_IT_TCIE SWPMI_IER_TCIE

Definition at line 212 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Transmit(), HAL_SWPMI_Transmit_IT(), and SWPMI_EndTransmitReceive_IT().

#define SWPMI_IT_TIE SWPMI_IER_TIE

Definition at line 213 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Transmit(), HAL_SWPMI_Transmit_IT(), SWPMI_EndTransmit_IT(), and SWPMI_Transmit_IT().

#define SWPMI_IT_TXBEIE SWPMI_IER_TXBEIE

Definition at line 218 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Transmit(), HAL_SWPMI_Transmit_IT(), and SWPMI_EndTransmit_IT().

#define SWPMI_IT_TXUNRIE SWPMI_IER_TXUNRIE

Definition at line 215 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Transmit(), HAL_SWPMI_Transmit_DMA(), HAL_SWPMI_Transmit_IT(), SWPMI_EndTransmit_IT(), and SWPMI_Transmit_IT().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SWPMI Exported Macros

Defines
SWPMI Exported Macros
SWPMI

Defines

#define | __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET)
Reset SWPMI handle state.
#define | __HAL_SWPMI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
Enable the SWPMI peripheral.
#define | __HAL_SWPMI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
Disable the SWPMI peripheral.
#define | __HAL_SWPMI_TRANSCEIVER_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)
Enable/Disable the SWPMI transceiver.
#define | __HAL_SWPMI_TRANSCEIVER_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)
#define | __HAL_SWPMI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__))
Check whether the specified SWPMI flag is set or not.
#define | __HAL_SWPMI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__))
Clear the specified SWPMI ISR flag.
#define | __HAL_SWPMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
Enable the specified SWPMI interrupt.
#define | __HAL_SWPMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
Disable the specified SWPMI interrupt.
#define | __HAL_SWPMI_GET_IT(__HANDLE__, __IT__) (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__))
Check whether the specified SWPMI interrupt has occurred or not.
#define | __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET)
Check whether the specified SWPMI interrupt source is enabled or not.

Define Documentation

#define __HAL_SWPMI_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__))

Clear the specified SWPMI ISR flag.

Parameters:
__HANDLE__,: specifies the SWPMI Handle.
__FLAG__,: specifies the flag to clear. This parameter can be one of the following values:
  • SWPMI_FLAG_RXBFF : Receive buffer full flag.
  • SWPMI_FLAG_TXBEF : Transmit buffer empty flag.
  • SWPMI_FLAG_RXBERF : Receive CRC error flag.
  • SWPMI_FLAG_RXOVRF : Receive overrun error flag.
  • SWPMI_FLAG_TXUNRF : Transmit underrun error flag.
  • SWPMI_FLAG_TCF : Transfer complete flag.
  • SWPMI_FLAG_SRF : Slave resume flag.
  • SWPMI_FLAG_RDYF: Transceiver ready flag
Return values:
None

Definition at line 294 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Transmit().

#define __HAL_SWPMI_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)

Disable the SWPMI peripheral.

Parameters:
__HANDLE__,: SWPMI handle
Return values:
None

Definition at line 251 of file stm32h7xx_hal_swpmi.h.

#define __HAL_SWPMI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))

Disable the specified SWPMI interrupt.

Parameters:
__HANDLE__,: specifies the SWPMI Handle.
__INTERRUPT__,: specifies the SWPMI interrupt source to disable. This parameter can be one of the following values:
  • SWPMI_IT_SRIE : Slave resume interrupt.
  • SWPMI_IT_TCIE : Transmit complete interrupt.
  • SWPMI_IT_TIE : Transmit interrupt.
  • SWPMI_IT_RIE : Receive interrupt.
  • SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
  • SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
  • SWPMI_IT_RXBEIE : Receive CRC error interrupt.
  • SWPMI_IT_TXBEIE : Transmit buffer empty interrupt.
  • SWPMI_IT_RXBFIE : Receive buffer full interrupt.
Return values:
None

Definition at line 328 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Transmit().

#define __HAL_SWPMI_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)

Enable the SWPMI peripheral.

Parameters:
__HANDLE__,: SWPMI handle
Return values:
None

Definition at line 244 of file stm32h7xx_hal_swpmi.h.

#define __HAL_SWPMI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))

Enable the specified SWPMI interrupt.

Parameters:
__HANDLE__,: specifies the SWPMI Handle.
__INTERRUPT__,: specifies the SWPMI interrupt source to enable. This parameter can be one of the following values:
  • SWPMI_IT_SRIE : Slave resume interrupt.
  • SWPMI_IT_TCIE : Transmit complete interrupt.
  • SWPMI_IT_TIE : Transmit interrupt.
  • SWPMI_IT_RIE : Receive interrupt.
  • SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
  • SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
  • SWPMI_IT_RXBEIE : Receive CRC error interrupt.
  • SWPMI_IT_TXBEIE : Transmit buffer empty interrupt.
  • SWPMI_IT_RXBFIE : Receive buffer full interrupt.
Return values:
None

Definition at line 311 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Receive_IT(), HAL_SWPMI_Transmit_DMA(), and HAL_SWPMI_Transmit_IT().

#define __HAL_SWPMI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__))

Check whether the specified SWPMI flag is set or not.

Parameters:
__HANDLE__,: specifies the SWPMI Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SWPMI_FLAG_RXBFF : Receive buffer full flag.
  • SWPMI_FLAG_TXBEF : Transmit buffer empty flag.
  • SWPMI_FLAG_RXBERF : Receive CRC error flag.
  • SWPMI_FLAG_RXOVRF : Receive overrun error flag.
  • SWPMI_FLAG_TXUNRF : Transmit underrun error flag.
  • SWPMI_FLAG_RXNE : Receive data register not empty.
  • SWPMI_FLAG_TXE : Transmit data register empty.
  • SWPMI_FLAG_TCF : Transfer complete flag.
  • SWPMI_FLAG_SRF : Slave resume flag.
  • SWPMI_FLAG_SUSP : SUSPEND flag.
  • SWPMI_FLAG_DEACTF : DEACTIVATED flag.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 278 of file stm32h7xx_hal_swpmi.h.

#define __HAL_SWPMI_GET_IT | ( | __HANDLE__,
 |  | __IT__
 | ) | (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__))

Check whether the specified SWPMI interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the SWPMI Handle.
__IT__,: specifies the SWPMI interrupt to check. This parameter can be one of the following values:
  • SWPMI_IT_SRIE : Slave resume interrupt.
  • SWPMI_IT_TCIE : Transmit complete interrupt.
  • SWPMI_IT_TIE : Transmit interrupt.
  • SWPMI_IT_RIE : Receive interrupt.
  • SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
  • SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
  • SWPMI_IT_RXBERIE : Receive CRC error interrupt.
  • SWPMI_IT_TXBEIE : Transmit buffer empty interrupt.
  • SWPMI_IT_RXBFIE : Receive buffer full interrupt.
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 345 of file stm32h7xx_hal_swpmi.h.

#define __HAL_SWPMI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) | ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET)

Check whether the specified SWPMI interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the SWPMI Handle.
__IT__,: specifies the SWPMI interrupt source to check. This parameter can be one of the following values:
  • SWPMI_IT_SRIE : Slave resume interrupt.
  • SWPMI_IT_TCIE : Transmit complete interrupt.
  • SWPMI_IT_TIE : Transmit interrupt.
  • SWPMI_IT_RIE : Receive interrupt.
  • SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
  • SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
  • SWPMI_IT_RXBERIE : Receive CRC error interrupt.
  • SWPMI_IT_TXBEIE : Transmit buffer empty interrupt.
  • SWPMI_IT_RXBFIE : Receive buffer full interrupt.
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 362 of file stm32h7xx_hal_swpmi.h.

#define __HAL_SWPMI_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET)

Reset SWPMI handle state.

Parameters:
__HANDLE__,: specifies the SWPMI Handle.
Return values:
None

Definition at line 237 of file stm32h7xx_hal_swpmi.h.

#define __HAL_SWPMI_TRANSCEIVER_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)

Definition at line 259 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_DeInit().

#define __HAL_SWPMI_TRANSCEIVER_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)

Enable/Disable the SWPMI transceiver.

Parameters:
__HANDLE__,: SWPMI handle
Return values:
None

Definition at line 258 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SWPMI Private Types

SWPMI Private Types
SWPMI
Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SWPMI Private Variables

SWPMI Private Variables
SWPMI
Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SWPMI Private Constants

Defines
SWPMI Private Constants
SWPMI

Defines

#define SWPMI_TIMEOUT_VALUE ((uint32_t) 22000U)

Define Documentation

#define SWPMI_TIMEOUT_VALUE ((uint32_t) 22000U)

Definition at line 98 of file stm32h7xx_hal_swpmi.c.

Referenced by HAL_SWPMI_Init(), and SWPMI_DMATransmitCplt().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SWPMI Private Macros

Defines
SWPMI Private Macros
SWPMI

Defines

#define | IS_SWPMI_VOLTAGE_CLASS(__CLASS__)
#define | IS_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 63))
#define | IS_SWPMI_TX_BUFFERING_MODE(__MODE__)
#define | IS_SWPMI_RX_BUFFERING_MODE(__MODE__)

Define Documentation

#define IS_SWPMI_BITRATE_VALUE ( __VALUE__ ) (((__VALUE__) <= 63))

Definition at line 439 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

#define IS_SWPMI_RX_BUFFERING_MODE ( __MODE__ )
Value:
(((__MODE__) == SWPMI_RX_NO_SOFTWAREBUFFER) || \
                                              ((__MODE__) == SWPMI_RX_MULTI_SOFTWAREBUFFER))

Definition at line 446 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

#define IS_SWPMI_TX_BUFFERING_MODE ( __MODE__ )
Value:
(((__MODE__) == SWPMI_TX_NO_SOFTWAREBUFFER) || \
                                              ((__MODE__) == SWPMI_TX_MULTI_SOFTWAREBUFFER))

Definition at line 442 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

#define IS_SWPMI_VOLTAGE_CLASS ( __CLASS__ )
Value:
(((__CLASS__) == SWPMI_VOLTAGE_CLASS_C) || \
                                              ((__CLASS__) == SWPMI_VOLTAGE_CLASS_B))

Definition at line 436 of file stm32h7xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Time Base functions

Functions
Time Base functions
TIM Exported Functions

TIM Time Base functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initialize the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initialize the TIM Time Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Time Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Time Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Time Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Time Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Time Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Time Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Time Base generation in DMA mode.

Detailed Description

TIM Time Base functions.

Time Base functions.

  ==============================================================================
              ##### TIM Time Base functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Time base.
    (+) De-initialize the TIM Time base.
    (+) Start the TIM Time Base.
    (+) Stop the TIM Time Base.
    (+) Start the TIM Time Base and enable interrupt.
    (+) Stop the TIM Time Base and disable interrupt.
    (+) Start the TIM Time Base and enable DMA transfer.
    (+) Stop the TIM Time Base and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_Base_DeInit ( TIM_HandleTypeDef * htim )

DeInitialize the TIM Base peripheral.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 232 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_Base_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Init ( TIM_HandleTypeDef * htim )

Initialize the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 193 of file stm32h7xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_Base_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_Base_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitialize TIM Time Base MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 275 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_Base_DeInit().

void HAL_TIM_Base_MspInit ( TIM_HandleTypeDef * htim )

Initialize the TIM Time Base MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 260 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_Base_Init().

HAL_StatusTypeDef HAL_TIM_Base_Start ( TIM_HandleTypeDef * htim )

Starts the TIM Time Base generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 291 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Time Base generation in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
pData,: The source Buffer address.
Length,: The length of data to be transferred from memory to peripheral.
Return values:
HAL status

Definition at line 382 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_DMAError(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_DMA_ID_UPDATE, TIM_DMA_UPDATE, TIM_DMAPeriodElapsedCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_Base_Start_IT ( TIM_HandleTypeDef * htim )

Starts the TIM Time Base generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 339 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, and TIM_IT_UPDATE.

HAL_StatusTypeDef HAL_TIM_Base_Stop ( TIM_HandleTypeDef * htim )

Stops the TIM Time Base generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 315 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA ( TIM_HandleTypeDef * htim )

Stops the TIM Time Base generation in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 427 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_Base_Stop_IT ( TIM_HandleTypeDef * htim )

Stops the TIM Time Base generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 360 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, TIM_HandleTypeDef::Instance, and TIM_IT_UPDATE.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Time Output Compare functions

Functions
Time Output Compare functions
TIM Exported Functions

Time Output Compare functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initialize the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initialize the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.

Detailed Description

Time Output Compare functions.

  ==============================================================================
                  ##### TIM Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Output Compare.
    (+) De-initialize the TIM Output Compare.
    (+) Start the TIM Output Compare.
    (+) Stop the TIM Output Compare.
    (+) Start the TIM Output Compare and enable interrupt.
    (+) Stop the TIM Output Compare and disable interrupt.
    (+) Start the TIM Output Compare and enable DMA transfer.
    (+) Stop the TIM Output Compare and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_OC_DeInit ( TIM_HandleTypeDef * htim )

DeInitialize the TIM peripheral.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 517 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_OC_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_OC_Init ( TIM_HandleTypeDef * htim )

Initialize the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 477 of file stm32h7xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_OC_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_OC_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitialize TIM Output Compare MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 561 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_OC_DeInit().

void HAL_TIM_OC_MspInit ( TIM_HandleTypeDef * htim )

Initialize the TIM Output Compare MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 545 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_OC_Init().

HAL_StatusTypeDef HAL_TIM_OC_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 583 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_OC_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Output Compare signal generation in DMA mode.

Parameters:
htim : TIM Output Compare handle
Channel : TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData,: The source Buffer address.
Length,: The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 784 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_DMAError(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_OC_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 649 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_OC_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 616 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 902 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIM_OC_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 716 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Time PWM functions

Functions
Time PWM functions
TIM Exported Functions

Time PWM functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initialize the TIM PWM mode according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initialize the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.

Detailed Description

Time PWM functions.

  ==============================================================================
                          ##### TIM PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM PWM mode.
    (+) De-initialize the TIM PWM mode.
    (+) Start the TIM PWM mode.
    (+) Stop the TIM PWM mode.
    (+) Start the TIM PWM mode and enable interrupt.
    (+) Stop the TIM PWM mode and disable interrupt.
    (+) Start the TIM PWM mode and enable DMA transfer.
    (+) Stop the TIM PWM mode and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_PWM_DeInit ( TIM_HandleTypeDef * htim )

DeInitialize the TIM peripheral.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 1032 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_PWM_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_PWM_Init ( TIM_HandleTypeDef * htim )

Initialize the TIM PWM mode according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 992 of file stm32h7xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_PWM_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_PWM_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitialize TIM PWM MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 1076 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_PWM_DeInit().

void HAL_TIM_PWM_MspInit ( TIM_HandleTypeDef * htim )

Initialize the TIM PWM MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 1060 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_PWM_Init().

HAL_StatusTypeDef HAL_TIM_PWM_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1098 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM PWM signal generation in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData,: The source Buffer address.
Length,: The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1303 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_DMAError(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_PWM_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1167 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_PWM_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1131 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM PWM signal generation in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1421 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1234 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Time Input Capture functions

Functions
Time Input Capture functions
TIM Exported Functions

Time Input Capture functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initialize the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initialize the TIM Input Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement on in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement on in DMA mode.

Detailed Description

Time Input Capture functions.

  ==============================================================================
              ##### TIM Input Capture functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
   (+) Initialize and configure the TIM Input Capture.
   (+) De-initialize the TIM Input Capture.
   (+) Start the TIM Input Capture mode.
   (+) Stop the TIM Input Capture mode.
   (+) Start the TIM Input Capture mode and enable interrupt.
   (+) Stop the TIM Input Capture mode and disable interrupt.
   (+) Start the TIM Input Capture mode and enable DMA transfer.
   (+) Stop the TIM Input Capture mode and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_IC_DeInit ( TIM_HandleTypeDef * htim )

DeInitialize the TIM peripheral.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 1551 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_IC_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_IC_Init ( TIM_HandleTypeDef * htim )

Initialize the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 1511 of file stm32h7xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_IC_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_IC_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitialize TIM Input Capture MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 1595 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_IC_DeInit().

void HAL_TIM_IC_MspInit ( TIM_HandleTypeDef * htim )

Initialize the TIM Input Capture MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 1579 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_IC_Init().

HAL_StatusTypeDef HAL_TIM_IC_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Input Capture measurement.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1617 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_IC_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Input Capture measurement on in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData,: The destination Buffer address.
Length,: The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 1794 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_DMACaptureCplt(), HAL_TIM_DMAError(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_IC_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Input Capture measurement in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1671 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_IC_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1644 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement on in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1908 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIM_IC_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1731 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Time One Pulse functions

Functions
Time One Pulse functions
TIM Exported Functions

Time One Pulse functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initialize the TIM One Pulse mode according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM One Pulse mode.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initialize the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.

Detailed Description

Time One Pulse functions.

  ==============================================================================
                        ##### TIM One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM One Pulse mode.
    (+) De-initialize the TIM One Pulse mode.
    (+) Start the TIM One Pulse mode.
    (+) Stop the TIM One Pulse mode.
    (+) Start the TIM One Pulse mode and enable interrupt.
    (+) Stop the TIM One Pulse mode and disable interrupt.
    (+) Start the TIM One Pulse mode and enable DMA transfer.
    (+) Stop the TIM One Pulse mode and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit ( TIM_HandleTypeDef * htim )

DeInitialize the TIM One Pulse mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 2043 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_OnePulse_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_OnePulse_Init | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OnePulseMode
 | ) |  |

Initialize the TIM One Pulse mode according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OnePulseMode,: Select the One pulse mode. This parameter can be one of the following values:
  • TIM_OPMODE_SINGLE: Only one pulse will be generated.
  • TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
Return values:
HAL status

Definition at line 1996 of file stm32h7xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_OnePulse_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_OPM_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_OnePulse_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitialize TIM One Pulse MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 2087 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_OnePulse_DeInit().

void HAL_TIM_OnePulse_MspInit ( TIM_HandleTypeDef * htim )

Initialize the TIM One Pulse MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 2071 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_OnePulse_Init().

HAL_StatusTypeDef HAL_TIM_OnePulse_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OutputChannel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2107 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_MOE_ENABLE, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OutputChannel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2181 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OutputChannel : TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2144 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OutputChannel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2224 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Time Encoder functions

Functions
Time Encoder functions
TIM Exported Functions

TIM Encoder functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initialize the TIM Encoder Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initialize the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.

Detailed Description

TIM Encoder functions.

Time Encoder functions.

  ==============================================================================
                          ##### TIM Encoder functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Encoder.
    (+) De-initialize the TIM Encoder mode.
    (+) Start the Time Encoder mode.
    (+) Stop the Time Encoder mode.
    (+) Start the Time Encoder mode and enable interrupt.
    (+) Stop the Time Encoder mode and disable interrupt.
    (+) Start the Time Encoder mode and enable DMA transfer.
    (+) Stop the Time Encoder mode and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_Encoder_DeInit ( TIM_HandleTypeDef * htim )

DeInitialize the TIM Encoder interface.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 2379 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_Encoder_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Encoder_Init | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_Encoder_InitTypeDef * | sConfig
 | ) |  |

Initialize the TIM Encoder Interface and initialize the associated handle.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sConfig,: TIM Encoder Interface configuration structure.
Return values:
HAL status

Definition at line 2288 of file stm32h7xx_hal_tim.c.

References assert_param, TIM_Encoder_InitTypeDef::EncoderMode, HAL_TIM_Encoder_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_Encoder_InitTypeDef::IC1Filter, TIM_Encoder_InitTypeDef::IC1Polarity, TIM_Encoder_InitTypeDef::IC1Prescaler, TIM_Encoder_InitTypeDef::IC1Selection, TIM_Encoder_InitTypeDef::IC2Filter, TIM_Encoder_InitTypeDef::IC2Polarity, TIM_Encoder_InitTypeDef::IC2Prescaler, TIM_Encoder_InitTypeDef::IC2Selection, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_ENCODER_MODE, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_Encoder_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitialize TIM Encoder Interface MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 2423 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_Encoder_DeInit().

void HAL_TIM_Encoder_MspInit ( TIM_HandleTypeDef * htim )

Initialize the TIM Encoder Interface MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 2407 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_Encoder_Init().

HAL_StatusTypeDef HAL_TIM_Encoder_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Encoder Interface.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2444 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData1,
 |  | uint32_t * | pData2,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Encoder Interface in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
pData1,: The destination Buffer address for Input Capture Channel1.
pData2,: The destination Buffer address for Input Capture Channel2.
Length,: The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 2636 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_DMACaptureCplt(), HAL_TIM_DMAError(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_ALL, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Encoder Interface in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2532 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2487 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2754 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_DMA_CC1, and TIM_DMA_CC2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2581 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM IRQ handler management

Functions
TIM IRQ handler management
TIM Exported Functions

IRQ handler management. More...

Functions

void HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.

Detailed Description

IRQ handler management.

  ==============================================================================
                        ##### IRQ handler management #####
  ==============================================================================
  [..]
    This section provides TIM IRQ handler function.

Function Documentation

void HAL_TIM_IRQHandler ( TIM_HandleTypeDef * htim )

This function handles TIM interrupts requests.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 2817 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_CLEAR_IT, __HAL_TIM_GET_FLAG, __HAL_TIM_GET_IT_SOURCE, TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_OC_DelayElapsedCallback(), HAL_TIM_PeriodElapsedCallback(), HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_TriggerCallback(), HAL_TIMEx_BreakCallback(), HAL_TIMEx_CommutationCallback(), TIM_HandleTypeDef::Instance, TIM_FLAG_BREAK, TIM_FLAG_BREAK2, TIM_FLAG_CC1, TIM_FLAG_CC2, TIM_FLAG_CC3, TIM_FLAG_CC4, TIM_FLAG_COM, TIM_FLAG_TRIGGER, TIM_FLAG_UPDATE, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4, TIM_IT_COM, TIM_IT_TRIGGER, and TIM_IT_UPDATE.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
TIM Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initialize the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initialize the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initialize the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initialize the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.

Detailed Description

Peripheral Control functions.

  ==============================================================================
                   ##### Peripheral Control functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
      (+) Configure The Input/Output channels for Output Compare, PWM, Input Capture
          or One Pulse mode.
      (+) Configure External Clock source.
      (+) Configure Complementary channels, break features and dead time.
      (+) Configure Master and the Slave synchronization.
      (+) Configure the DMA Burst Mode.

Function Documentation

HAL_StatusTypeDef HAL_TIM_ConfigClockSource | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_ClockConfigTypeDef * | sClockSourceConfig
 | ) |  |

Configures the clock source to be used.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sClockSourceConfig,: pointer to a TIM_ClockConfigTypeDef structure that contains the clock source information for the TIM peripheral.
Return values:
HAL status

Definition at line 4107 of file stm32h7xx_hal_tim.c.

References assert_param, TIM_ClockConfigTypeDef::ClockFilter, TIM_ClockConfigTypeDef::ClockPolarity, TIM_ClockConfigTypeDef::ClockPrescaler, TIM_ClockConfigTypeDef::ClockSource, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKFILTER, IS_TIM_CLOCKPOLARITY, IS_TIM_CLOCKPRESCALER, IS_TIM_CLOCKSOURCE, TIM_HandleTypeDef::State, TIM_CLOCKSOURCE_ETRMODE1, TIM_CLOCKSOURCE_ETRMODE2, TIM_CLOCKSOURCE_INTERNAL, TIM_CLOCKSOURCE_ITR0, TIM_CLOCKSOURCE_ITR1, TIM_CLOCKSOURCE_ITR2, TIM_CLOCKSOURCE_ITR3, TIM_CLOCKSOURCE_TI1, TIM_CLOCKSOURCE_TI1ED, TIM_CLOCKSOURCE_TI2, TIM_ETR_SetConfig(), TIM_ITRx_SetConfig(), TIM_SLAVEMODE_EXTERNAL1, TIM_TI1_ConfigInputStage(), and TIM_TI2_ConfigInputStage().

HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_ClearInputConfigTypeDef * | sClearInputConfig,
 |  | uint32_t | Channel
 | ) |  |

Configures the OCRef clear feature.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sClearInputConfig,: pointer to a TIM_ClearInputConfigTypeDef structure that contains the OCREF clear feature and parameters for the TIM peripheral.
Channel,: specifies the TIM Channel. This parameter can be one of the following values:
  • TIM_Channel_1: TIM Channel 1
  • TIM_Channel_2: TIM Channel 2
  • TIM_Channel_3: TIM Channel 3
  • TIM_Channel_4: TIM Channel 4
  • TIM_Channel_5: TIM Channel 5
  • TIM_Channel_6: TIM Channel 6
Return values:
None

Definition at line 3955 of file stm32h7xx_hal_tim.c.

References assert_param, TIM_ClearInputConfigTypeDef::ClearInputFilter, TIM_ClearInputConfigTypeDef::ClearInputPolarity, TIM_ClearInputConfigTypeDef::ClearInputPrescaler, TIM_ClearInputConfigTypeDef::ClearInputSource, TIM_ClearInputConfigTypeDef::ClearInputState, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CLEARINPUT_FILTER, IS_TIM_CLEARINPUT_POLARITY, IS_TIM_CLEARINPUT_PRESCALER, IS_TIM_CLEARINPUT_SOURCE, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_5, TIM_CHANNEL_6, TIM_CLEARINPUTSOURCE_ETR, TIM_CLEARINPUTSOURCE_NONE, and TIM_ETR_SetConfig().

HAL_StatusTypeDef HAL_TIM_ConfigTI1Input | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | TI1_Selection
 | ) |  |

Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
TI1_Selection,: Indicate whether or not channel 1 is connected to the output of a XOR gate. This parameter can be one of the following values:
  • TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
  • TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Return values:
HAL status

Definition at line 4281 of file stm32h7xx_hal_tim.c.

References assert_param, TIM_HandleTypeDef::Instance, and IS_TIM_TI1SELECTION.

HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength
 | ) |  |

Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
BurstBaseAddress,: TIM Base address from when the DMA will starts the Data read. This parameters can be on of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_DCR
BurstRequestSrc,: TIM DMA Request sources. This parameters can be on of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer,: The Buffer address.
BurstLength,: DMA Burst length. This parameter can be one value between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
Return values:
HAL status

Definition at line 3708 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_DMACaptureCplt(), HAL_TIM_DMAError(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIMEx_DMACommutationCplt(), TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, IS_TIM_DMA_BASE, IS_TIM_DMA_LENGTH, IS_TIM_DMA_SOURCE, TIM_HandleTypeDef::State, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, TIM_DMA_UPDATE, TIM_DMAPeriodElapsedCplt(), TIM_DMATriggerCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstRequestSrc
 | ) |  |

Stop the DMA burst reading.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
BurstRequestSrc,: TIM DMA Request sources to disable.
Return values:
HAL status

Definition at line 3841 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort(), TIM_HandleTypeDef::hdma, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength
 | ) |  |

Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
BurstBaseAddress,: TIM Base address from when the DMA will starts the Data write. This parameters can be on of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_DCR
BurstRequestSrc,: TIM DMA Request sources. This parameters can be on of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer,: The Buffer address.
BurstLength,: DMA Burst length. This parameter can be one value between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
Return values:
HAL status

Definition at line 3483 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_DMAError(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIMEx_DMACommutationCplt(), TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, IS_TIM_DMA_BASE, IS_TIM_DMA_LENGTH, IS_TIM_DMA_SOURCE, TIM_HandleTypeDef::State, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, TIM_DMA_UPDATE, TIM_DMAPeriodElapsedCplt(), TIM_DMATriggerCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstRequestSrc
 | ) |  |

Stops the TIM DMA Burst mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
BurstRequestSrc,: TIM DMA Request sources to disable
Return values:
HAL status

Definition at line 3615 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort(), TIM_HandleTypeDef::hdma, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_GenerateEvent | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | EventSource
 | ) |  |

Generate a software event.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
EventSource,: specifies the event source. This parameter can be one of the following values:
  • TIM_EVENTSOURCE_UPDATE: Timer update Event source
  • TIM_EVENTSOURCE_CC1: TIM Capture Compare 1 Event source
  • TIM_EVENTSOURCE_CC2: TIM Capture Compare 2 Event source
  • TIM_EVENTSOURCE_CC3: TIM Capture Compare 3 Event source
  • TIM_EVENTSOURCE_CC4: TIM Capture Compare 4 Event source
  • TIM_EVENTSOURCE_COM: TIM COM event source
  • TIM_EVENTSOURCE_TRIGGER: TIM Trigger Event source
  • TIM_EVENTSOURCE_BREAK: TIM Break event source
  • TIM_EVENTSOURCE_BREAK2: TIM Break2 event source
Note:
TIM6 and TIM7 can only generate an update event.
TIM_EVENTSOURCE_COM, TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are used only with TIM1 and TIM8.
Return values:
HAL status

Definition at line 3915 of file stm32h7xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_EVENT_SOURCE, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_IC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initialize the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sConfig,: TIM Input Capture configuration structure.
Channel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 3094 of file stm32h7xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_IC_InitTypeDef::ICFilter, TIM_IC_InitTypeDef::ICPolarity, TIM_IC_InitTypeDef::ICPrescaler, TIM_IC_InitTypeDef::ICSelection, TIM_HandleTypeDef::Instance, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_TI1_SetConfig(), TIM_TI2_SetConfig(), TIM_TI3_SetConfig(), and TIM_TI4_SetConfig().

HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initialize the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sConfig,: TIM Output Compare configuration structure.
Channel : TIM Channels to configure. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 2993 of file stm32h7xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_5, TIM_CHANNEL_6, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OnePulse_InitTypeDef * | sConfig,
 |  | uint32_t | OutputChannel,
 |  | uint32_t | InputChannel
 | ) |  |

Initialize the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sConfig,: TIM One Pulse configuration structure.
OutputChannel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
InputChannel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 3345 of file stm32h7xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_OnePulse_InitTypeDef::ICFilter, TIM_OnePulse_InitTypeDef::ICPolarity, TIM_OnePulse_InitTypeDef::ICSelection, TIM_HandleTypeDef::Instance, IS_TIM_OPM_CHANNELS, TIM_OC_InitTypeDef::OCIdleState, TIM_OnePulse_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OnePulse_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OnePulse_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OnePulse_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OnePulse_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, TIM_OnePulse_InitTypeDef::Pulse, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_SLAVEMODE_TRIGGER, TIM_TI1_SetConfig(), TIM_TI2_SetConfig(), TIM_TS_TI1FP1, and TIM_TS_TI2FP2.

HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initialize the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sConfig,: TIM PWM configuration structure.
Channel : TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 3194 of file stm32h7xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_FAST_STATE, IS_TIM_OC_POLARITY, IS_TIM_PWM_MODE, TIM_OC_InitTypeDef::OCFastMode, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_5, TIM_CHANNEL_6, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t HAL_TIM_ReadCapturedValue | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Read the captured value from Capture Compare unit.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
Captured value

Definition at line 4389 of file stm32h7xx_hal_tim.c.

References assert_param, TIM_HandleTypeDef::Instance, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, and TIM_CHANNEL_4.

HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  |

Configures the TIM in Slave mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sSlaveConfig,: pointer to a TIM_SlaveConfigTypeDef structure that contains the selected trigger (internal trigger input, filtered timer input or external trigger input) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1).
Return values:
HAL status

Definition at line 4314 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_SlaveConfigTypeDef::InputTrigger, TIM_HandleTypeDef::Instance, IS_TIM_SLAVE_MODE, IS_TIM_TRIGGER_SELECTION, TIM_SlaveConfigTypeDef::SlaveMode, TIM_HandleTypeDef::State, TIM_DMA_TRIGGER, TIM_IT_TRIGGER, and TIM_SlaveTimer_SetConfig().

HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  |

Configures the TIM in Slave mode in interrupt mode.

Parameters:
htim,: TIM handle.
sSlaveConfig,: pointer to a TIM_SlaveConfigTypeDef structure that contains the selected trigger (internal trigger input, filtered timer input or external trigger input) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1).
Return values:
HAL status

Definition at line 4350 of file stm32h7xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_ENABLE_IT, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_SlaveConfigTypeDef::InputTrigger, TIM_HandleTypeDef::Instance, IS_TIM_SLAVE_MODE, IS_TIM_TRIGGER_SELECTION, TIM_SlaveConfigTypeDef::SlaveMode, TIM_HandleTypeDef::State, TIM_DMA_TRIGGER, TIM_IT_TRIGGER, and TIM_SlaveTimer_SetConfig().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Callbacks functions

Functions
TIM Callbacks functions
TIM Exported Functions

TIM Callbacks functions. More...

Functions

__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
TIM error callback in non blocking mode.

Detailed Description

TIM Callbacks functions.

  ==============================================================================
                        ##### TIM Callbacks functions #####
  ==============================================================================
 [..]
   This section provides TIM callback functions:
   (+) TIM Period elapsed callback
   (+) TIM Output Compare callback
   (+) TIM Input capture callback
   (+) TIM Trigger callback
   (+) TIM Error callback

Function Documentation

void HAL_TIM_ErrorCallback ( TIM_HandleTypeDef * htim )

TIM error callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 4556 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_DMAError().

void HAL_TIM_IC_CaptureCallback ( TIM_HandleTypeDef * htim )

Input Capture callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 4508 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_DMACaptureCplt(), and HAL_TIM_IRQHandler().

void HAL_TIM_OC_DelayElapsedCallback ( TIM_HandleTypeDef * htim )

Output Compare callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 4493 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler().

void HAL_TIM_PeriodElapsedCallback ( TIM_HandleTypeDef * htim )

Period elapsed callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 4477 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), and TIM_DMAPeriodElapsedCplt().

void HAL_TIM_PWM_PulseFinishedCallback ( TIM_HandleTypeDef * htim )

PWM Pulse finished callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 4524 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_DMADelayPulseCplt(), and HAL_TIM_IRQHandler().

void HAL_TIM_TriggerCallback ( TIM_HandleTypeDef * htim )

Hall Trigger detection callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 4540 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), and TIM_DMATriggerCplt().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
TIM Exported Functions

Peripheral State functions. More...

Functions

HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Output Compare handle state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM handle state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode handle state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                        ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_TIM_StateTypeDef HAL_TIM_Base_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Base handle state.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL state

Definition at line 4591 of file stm32h7xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Encoder Mode state.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL state

Definition at line 4645 of file stm32h7xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_IC_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Input Capture handle state.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL state

Definition at line 4623 of file stm32h7xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_OC_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Output Compare handle state.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL state

Definition at line 4602 of file stm32h7xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState ( TIM_HandleTypeDef * htim )

Return the TIM One Pulse Mode handle state.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL state

Definition at line 4634 of file stm32h7xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState ( TIM_HandleTypeDef * htim )

Return the TIM PWM handle state.

Parameters:
htim,: TIM handle
Return values:
HAL state

Definition at line 4612 of file stm32h7xx_hal_tim.c.

References TIM_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Exported Functions

Modules | Functions
TIM Exported Functions
TIM

Modules

Time Base functions

TIM Time Base functions.

Time Output Compare functions

Time Output Compare functions.

Time PWM functions

Time PWM functions.

Time Input Capture functions

Time Input Capture functions.

Time One Pulse functions

Time One Pulse functions.

Time Encoder functions

TIM Encoder functions.

TIM IRQ handler management

IRQ handler management.

Peripheral Control functions

Peripheral Control functions.

TIM Callbacks functions

TIM Callbacks functions.

Peripheral State functions

Peripheral State functions.

Functions

void | HAL_TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | HAL_TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | HAL_TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM Output Compare 1 configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM Output Compare 2 configuration.
void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM Output Compare 3 configuration.
void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM Output Compare 4 configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.
static void | TIM_DMAPeriodElapsedCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse complete callback.
static void | TIM_DMATriggerCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger callback.
static void | TIM_OC5_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM Output Compare 5 configuration.
static void | TIM_OC6_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM Output Compare 6 configuration.
static void | TIM_SlaveTimer_SetConfig (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
TIM Slave mode configuration.
static void | TIM_TI1_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI1.
static void | TIM_TI2_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TIM_TI2_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI2.
static void | TIM_TI3_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TIM_TI4_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI4 as Input.
static void | TIM_ITRx_SetConfig (TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
Selects the Input Trigger source.

Function Documentation

void HAL_TIM_DMACaptureCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Capture complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4708 of file stm32h7xx_hal_tim.c.

References TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), and HAL_TIMEx_HallSensor_Start_DMA().

void HAL_TIM_DMADelayPulseCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Delay Pulse complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4675 of file stm32h7xx_hal_tim.c.

References TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_WriteStart(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void HAL_TIM_DMAError ( DMA_HandleTypeDef * hdma )

TIM DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4660 of file stm32h7xx_hal_tim.c.

References HAL_TIM_ErrorCallback(), HAL_TIM_STATE_READY, and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void TIM_Base_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_Base_InitTypeDef * | Structure
 | ) |  |

Time Base configuration.

Parameters:
TIMx,: TIM periheral
Structure,: TIM Base configuration structure
Return values:
None

Definition at line 4772 of file stm32h7xx_hal_tim.c.

References TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, TIM_Base_InitTypeDef::Period, TIM_Base_InitTypeDef::Prescaler, and TIM_Base_InitTypeDef::RepetitionCounter.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

void TIM_CCxChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelState
 | ) |  |

Enables or disables the TIM Capture Compare Channel x.

Parameters:
TIMx to select the TIM peripheral
Channel,: specifies the TIM Channel This parameter can be one of the following values:
  • TIM_Channel_1: TIM Channel 1
  • TIM_Channel_2: TIM Channel 2
  • TIM_Channel_3: TIM Channel 3
  • TIM_Channel_4: TIM Channel 4
ChannelState,: specifies the TIM Channel CCxE bit new state. This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
Return values:
None

Definition at line 5677 of file stm32h7xx_hal_tim.c.

References assert_param, and IS_TIM_CHANNELS.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), and HAL_TIMEx_HallSensor_Stop_IT().

static void TIM_DMAPeriodElapsedCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Period Elapse complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4742 of file stm32h7xx_hal_tim.c.

References HAL_TIM_PeriodElapsedCallback(), HAL_TIM_STATE_READY, and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

static void TIM_DMATriggerCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Trigger callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4757 of file stm32h7xx_hal_tim.c.

References HAL_TIM_STATE_READY, HAL_TIM_TriggerCallback(), and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

void TIM_ETR_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ExtTRGPrescaler,
 |  | uint32_t | TIM_ExtTRGPolarity,
 |  | uint32_t | ExtTRGFilter
 | ) |  |

Configures the TIMx External Trigger (ETR).

Parameters:
TIMx to select the TIM peripheral
TIM_ExtTRGPrescaler,: The external Trigger Prescaler. This parameter can be one of the following values:
  • TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
  • TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
  • TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
  • TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
TIM_ExtTRGPolarity,: The external Trigger Polarity. This parameter can be one of the following values:
  • TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
  • TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
ExtTRGFilter,: External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 5647 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), and TIM_SlaveTimer_SetConfig().

static void TIM_ITRx_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | InputTriggerSource
 | ) |  | [static]

Selects the Input Trigger source.

Parameters:
TIMx to select the TIM peripheral
InputTriggerSource,: The Input Trigger source. This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal Trigger 0
  • TIM_TS_ITR1: Internal Trigger 1
  • TIM_TS_ITR2: Internal Trigger 2
  • TIM_TS_ITR3: Internal Trigger 3
  • TIM_TS_TI1F_ED: TI1 Edge Detector
  • TIM_TS_TI1FP1: Filtered Timer Input 1
  • TIM_TS_TI2FP2: Filtered Timer Input 2
  • TIM_TS_ETRF: External Trigger input
Return values:
None

Definition at line 5617 of file stm32h7xx_hal_tim.c.

References TIM_SLAVEMODE_EXTERNAL1.

Referenced by HAL_TIM_ConfigClockSource().

void TIM_OC1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

TIM Output Compare 1 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The Output configuration structure
Return values:
None

Definition at line 4819 of file stm32h7xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_1.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_OC2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

TIM Output Compare 2 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The Output configuration structure
Return values:
None

Definition at line 4893 of file stm32h7xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_2.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

void TIM_OC3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

TIM Output Compare 3 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The output configuration structure
Return values:
None

Definition at line 4970 of file stm32h7xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_3.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_OC4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

TIM Output Compare 4 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The Output configuration structure
Return values:
None

Definition at line 5045 of file stm32h7xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_OC5_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

TIM Output Compare 5 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The Output configuration structure
Return values:
None

Definition at line 5103 of file stm32h7xx_hal_tim.c.

References TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_OC6_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

TIM Output Compare 6 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The Output configuration structure
Return values:
None

Definition at line 5155 of file stm32h7xx_hal_tim.c.

References TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_SlaveTimer_SetConfig | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  | [static]

TIM Slave mode configuration.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sSlaveConfig,: The slave configuration structure
Return values:
None

Definition at line 5209 of file stm32h7xx_hal_tim.c.

References assert_param, TIM_SlaveConfigTypeDef::InputTrigger, TIM_HandleTypeDef::Instance, IS_TIM_TRIGGERFILTER, IS_TIM_TRIGGERPOLARITY, IS_TIM_TRIGGERPRESCALER, TIM_SlaveConfigTypeDef::SlaveMode, TIM_ETR_SetConfig(), TIM_TI1_ConfigInputStage(), TIM_TI2_ConfigInputStage(), TIM_TS_ETRF, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, TIM_TS_ITR3, TIM_TS_TI1F_ED, TIM_TS_TI1FP1, TIM_TS_TI2FP2, TIM_SlaveConfigTypeDef::TriggerFilter, TIM_SlaveConfigTypeDef::TriggerPolarity, and TIM_SlaveConfigTypeDef::TriggerPrescaler.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

static void TIM_TI1_ConfigInputStage | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the Polarity and Filter for TI1.

Parameters:
TIMx to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 5400 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_SlaveTimer_SetConfig().

void TIM_TI1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  |

Configure the TI1 as Input.

Parameters:
TIMx to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
  • TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
  • TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 (on channel2 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 5353 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

static void TIM_TI2_ConfigInputStage | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the Polarity and Filter for TI2.

Parameters:
TIMx to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 5483 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_SlaveTimer_SetConfig().

static void TIM_TI2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI2 as Input.

Parameters:
TIMx to select the TIM peripheral
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
  • TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
  • TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 (on channel1 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 5443 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), and HAL_TIM_OnePulse_ConfigChannel().

static void TIM_TI3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI3 as Input.

Parameters:
TIMx to select the TIM peripheral
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
  • TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
  • TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 (on channel1 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.

Definition at line 5526 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel().

static void TIM_TI4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI4 as Input.

Parameters:
TIMx to select the TIM peripheral
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
  • TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
  • TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 (on channel1 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.

Definition at line 5574 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Exported Types

Data Structures | Enumerations
TIM Exported Types
TIM

Data Structures

struct | TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition. More...
struct | TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition. More...
struct | TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition. More...
struct | TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition. More...
struct | TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition. More...
struct | TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition. More...
struct | TIM_ClearInputConfigTypeDef
Clear Input Configuration Handle Structure definition. More...
struct | TIM_MasterConfigTypeDef
TIM Master configuration Structure definition. More...
struct | TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition. More...
struct | TIM_BreakDeadTimeConfigTypeDef
TIM Break input(s) and Dead time configuration Structure definition. More...
struct | TIM_HandleTypeDef
TIM Time Base Handle Structure definition. More...

Enumerations

enum HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
}
HAL Active channel structures definition. More...

Enumeration Type Documentation

enum HAL_TIM_ActiveChannel

HAL Active channel structures definition.

Enumerator:
HAL_TIM_ACTIVE_CHANNEL_1

The active channel is 1

HAL_TIM_ACTIVE_CHANNEL_2

The active channel is 2

HAL_TIM_ACTIVE_CHANNEL_3

The active channel is 3

HAL_TIM_ACTIVE_CHANNEL_4

The active channel is 4

HAL_TIM_ACTIVE_CHANNEL_5

The active channel is 5

HAL_TIM_ACTIVE_CHANNEL_6

The active channel is 6

HAL_TIM_ACTIVE_CHANNEL_CLEARED

All active channels cleared

Definition at line 322 of file stm32h7xx_hal_tim.h.

enum HAL_TIM_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_TIM_STATE_RESET

Peripheral not yet initialized or disabled

HAL_TIM_STATE_READY

Peripheral Initialized and ready for use

HAL_TIM_STATE_BUSY

An internal process is ongoing

HAL_TIM_STATE_TIMEOUT

Timeout state

HAL_TIM_STATE_ERROR

Reception process is ongoing

Definition at line 310 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM_Base_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_Base_InitTypeDef Struct Reference
TIM Exported Types

TIM Time base Configuration Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

uint32_t | Prescaler
uint32_t | CounterMode
uint32_t | Period
uint32_t | ClockDivision
uint32_t | RepetitionCounter
uint32_t | AutoReloadPreload

Detailed Description

TIM Time base Configuration Structure definition.

Definition at line 65 of file stm32h7xx_hal_tim.h.

Field Documentation

uint32_t TIM_Base_InitTypeDef::AutoReloadPreload

Specifies the auto-reload preload. This parameter can be a value of TIM Auto-Reload Preload

Definition at line 88 of file stm32h7xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::ClockDivision

Specifies the clock division. This parameter can be a value of TIM Clock Division

Definition at line 77 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::CounterMode

Specifies the counter mode. This parameter can be a value of TIM Counter Mode

Definition at line 70 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::Period

Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

Definition at line 73 of file stm32h7xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::Prescaler

Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 67 of file stm32h7xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::RepetitionCounter

Specifies the repetition counter value. Each time the RCR down-counter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to:

  • the number of PWM periods in edge-aligned mode
  • the number of half PWM period in center-aligned mode This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
    Note:
    This parameter is valid only for TIM1 and TIM8.

Definition at line 80 of file stm32h7xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM_OC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_OC_InitTypeDef Struct Reference
TIM Exported Types

TIM Output Compare Configuration Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | Pulse
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCFastMode
uint32_t | OCIdleState
uint32_t | OCNIdleState

Detailed Description

TIM Output Compare Configuration Structure definition.

Definition at line 95 of file stm32h7xx_hal_tim.h.

Field Documentation

uint32_t TIM_OC_InitTypeDef::OCFastMode

Specifies the Fast mode state. This parameter can be a value of TIM Output Fast State

Note:
This parameter is valid only in PWM1 and PWM2 mode.

Definition at line 110 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

uint32_t TIM_OC_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 115 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCMode

Specifies the TIM mode. This parameter can be a value of TIM Output Compare and PWM Modes

Definition at line 97 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Complementary Output Compare Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 119 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of TIM Complementary Output Compare Polarity

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 106 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of TIM Output Compare Polarity

Definition at line 103 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t TIM_OC_InitTypeDef::Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 100 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM_OnePulse_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_OnePulse_InitTypeDef Struct Reference
TIM Exported Types

TIM One Pulse Mode Configuration Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | Pulse
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCIdleState
uint32_t | OCNIdleState
uint32_t | ICPolarity
uint32_t | ICSelection
uint32_t | ICFilter

Detailed Description

TIM One Pulse Mode Configuration Structure definition.

Definition at line 127 of file stm32h7xx_hal_tim.h.

Field Documentation

uint32_t TIM_OnePulse_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 156 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 150 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::ICSelection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 153 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 142 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCMode

Specifies the TIM mode. This parameter can be a value of TIM Output Compare and PWM Modes

Definition at line 129 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Complementary Output Compare Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 146 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of TIM Complementary Output Compare Polarity

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 138 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of TIM Output Compare Polarity

Definition at line 135 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 132 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM_IC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_IC_InitTypeDef Struct Reference
TIM Exported Types

TIM Input Capture Configuration Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

uint32_t | ICPolarity
uint32_t | ICSelection
uint32_t | ICPrescaler
uint32_t | ICFilter

Detailed Description

TIM Input Capture Configuration Structure definition.

Definition at line 164 of file stm32h7xx_hal_tim.h.

Field Documentation

uint32_t TIM_IC_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 175 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 166 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICPrescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 172 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICSelection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 169 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM_Encoder_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_Encoder_InitTypeDef Struct Reference
TIM Exported Types

TIM Encoder Configuration Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

uint32_t | EncoderMode
uint32_t | IC1Polarity
uint32_t | IC1Selection
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | IC2Polarity
uint32_t | IC2Selection
uint32_t | IC2Prescaler
uint32_t | IC2Filter

Detailed Description

TIM Encoder Configuration Structure definition.

Definition at line 182 of file stm32h7xx_hal_tim.h.

Field Documentation

uint32_t TIM_Encoder_InitTypeDef::EncoderMode

Specifies the active edge of the input signal. This parameter can be a value of TIM Encoder Mode

Definition at line 184 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 196 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 187 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 193 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Selection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 190 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 208 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 199 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 205 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Selection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 202 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM_ClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_ClockConfigTypeDef Struct Reference
TIM Exported Types

Clock Configuration Handle Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

uint32_t | ClockSource
uint32_t | ClockPolarity
uint32_t | ClockPrescaler
uint32_t | ClockFilter

Detailed Description

Clock Configuration Handle Structure definition.

Definition at line 216 of file stm32h7xx_hal_tim.h.

Field Documentation

uint32_t TIM_ClockConfigTypeDef::ClockFilter

TIM clock filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 224 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockPolarity

TIM clock polarity This parameter can be a value of TIM Clock Polarity

Definition at line 220 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockPrescaler

TIM clock prescaler This parameter can be a value of TIM Clock Prescaler

Definition at line 222 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockSource

TIM clock sources This parameter can be a value of TIM Clock Source

Definition at line 218 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM_ClearInputConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_ClearInputConfigTypeDef Struct Reference
TIM Exported Types

Clear Input Configuration Handle Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

uint32_t | ClearInputState
uint32_t | ClearInputSource
uint32_t | ClearInputPolarity
uint32_t | ClearInputPrescaler
uint32_t | ClearInputFilter

Detailed Description

Clear Input Configuration Handle Structure definition.

Definition at line 231 of file stm32h7xx_hal_tim.h.

Field Documentation

uint32_t TIM_ClearInputConfigTypeDef::ClearInputFilter

TIM Clear Input filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 241 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputPolarity

TIM Clear Input polarity This parameter can be a value of TIM Clear Input Polarity

Definition at line 237 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputPrescaler

TIM Clear Input prescaler This parameter can be a value of TIM Clear Input Prescaler

Definition at line 239 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputSource

TIM clear Input sources This parameter can be a value of TIM Extended Clear Input Source

Definition at line 235 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputState

TIM clear Input state This parameter can be ENABLE or DISABLE

Definition at line 233 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM_MasterConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_MasterConfigTypeDef Struct Reference
TIM Exported Types

TIM Master configuration Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

uint32_t | MasterOutputTrigger
uint32_t | MasterOutputTrigger2
uint32_t | MasterSlaveMode

Detailed Description

TIM Master configuration Structure definition.

Note:
Advanced timers provide TRGO2 internal line which is redirected to the ADC

Definition at line 250 of file stm32h7xx_hal_tim.h.

Field Documentation

uint32_t TIM_MasterConfigTypeDef::MasterOutputTrigger

Trigger output (TRGO) selection This parameter can be a value of TIM Master Mode Selection

Definition at line 251 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

uint32_t TIM_MasterConfigTypeDef::MasterOutputTrigger2

Trigger output2 (TRGO2) selection This parameter can be a value of TIM Master Mode Selection 2 (TRGO2)

Definition at line 253 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

uint32_t TIM_MasterConfigTypeDef::MasterSlaveMode

Master/slave mode selection This parameter can be a value of TIM Master/Slave Mode

Definition at line 255 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM_SlaveConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_SlaveConfigTypeDef Struct Reference
TIM Exported Types

TIM Slave configuration Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

uint32_t | SlaveMode
uint32_t | InputTrigger
uint32_t | TriggerPolarity
uint32_t | TriggerPrescaler
uint32_t | TriggerFilter

Detailed Description

TIM Slave configuration Structure definition.

Definition at line 262 of file stm32h7xx_hal_tim.h.

Field Documentation

uint32_t TIM_SlaveConfigTypeDef::InputTrigger

Input Trigger source This parameter can be a value of TIM Trigger Selection

Definition at line 265 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::SlaveMode

Slave mode selection This parameter can be a value of TIM Slave mode

Definition at line 263 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerFilter

Input trigger filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 271 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerPolarity

Input Trigger polarity This parameter can be a value of TIM Trigger Polarity

Definition at line 267 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerPrescaler

Input trigger prescaler This parameter can be a value of TIM Trigger Prescaler

Definition at line 269 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM_BreakDeadTimeConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_BreakDeadTimeConfigTypeDef Struct Reference
TIM Exported Types

TIM Break input(s) and Dead time configuration Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

uint32_t | OffStateRunMode
uint32_t | OffStateIDLEMode
uint32_t | LockLevel
uint32_t | DeadTime
uint32_t | BreakState
uint32_t | BreakPolarity
uint32_t | BreakFilter
uint32_t | Break2State
uint32_t | Break2Polarity
uint32_t | Break2Filter
uint32_t | AutomaticOutput

Detailed Description

TIM Break input(s) and Dead time configuration Structure definition.

Note:
2 break inputs can be configured (BKIN and BKIN2) with configurable filter and polarity.

Definition at line 281 of file stm32h7xx_hal_tim.h.

Field Documentation

uint32_t TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput

TIM Automatic Output Enable state This parameter can be a value of TIM Automatic Output Enable

Definition at line 303 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2Filter

TIM break2 input filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 301 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2Polarity

TIM Break2 input polarity This parameter can be a value of TIM Extended Break Input 2 Polarity

Definition at line 299 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2State

TIM Break2 State This parameter can be a value of TIMEX Break input 2 Enable

Definition at line 297 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakFilter

Specifies the break input filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 295 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakPolarity

TIM Break input polarity This parameter can be a value of TIM Break Input Polarity

Definition at line 293 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakState

TIM Break State This parameter can be a value of TIM Break Input Enable

Definition at line 291 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::DeadTime

TIM dead Time This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 289 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::LockLevel

TIM Lock level This parameter can be a value of TIM Lock Configuration

Definition at line 287 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode

TIM off state in IDLE mode This parameter can be a value of TIM Off-state Selection for Idle Mode

Definition at line 285 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode

TIM off state in run mode This parameter can be a value of TIM Off-state Selection for Run Mode

Definition at line 283 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_HandleTypeDef Struct Reference
TIM Exported Types

TIM Time Base Handle Structure definition. More...

#include <stm32h7xx_hal_tim.h>

Data Fields

TIM_TypeDef * | Instance
TIM_Base_InitTypeDef Init
HAL_TIM_ActiveChannel Channel
DMA_HandleTypeDef * | hdma [7]
HAL_LockTypeDef | Lock
__IO HAL_TIM_StateTypeDef | State

Detailed Description

TIM Time Base Handle Structure definition.

Definition at line 336 of file stm32h7xx_hal_tim.h.

Field Documentation

HAL_TIM_ActiveChannel TIM_HandleTypeDef::Channel

Active channel

Definition at line 340 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMACaptureCplt(), HAL_TIM_DMADelayPulseCplt(), and HAL_TIM_IRQHandler().

DMA_HandleTypeDef* TIM_HandleTypeDef::hdma[7]

DMA Handlers array This array is accessed by a TIM DMA Handle Index

Definition at line 341 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_DMACaptureCplt(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

TIM_Base_InitTypeDef TIM_HandleTypeDef::Init

TIM Time Base required parameters

Definition at line 339 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

TIM_TypeDef* TIM_HandleTypeDef::Instance

Register base address

Definition at line 338 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_ConfigTI1Input(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_ConfigBreakInput(), HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), HAL_TIMEx_GroupChannel5(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_RemapConfig(), HAL_TIMEx_TISelection(), and TIM_SlaveTimer_SetConfig().

HAL_LockTypeDef TIM_HandleTypeDef::Lock

Locking object

Definition at line 342 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

__IO HAL_TIM_StateTypeDef TIM_HandleTypeDef::State

TIM operation state

Definition at line 343 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_GetState(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMACaptureCplt(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_DMAError(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_GetState(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_GetState(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_GetState(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_GetState(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_GetState(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_DMACommutationCplt(), HAL_TIMEx_GroupChannel5(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_GetState(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_RemapConfig(), HAL_TIMEx_TISelection(), TIM_DMAPeriodElapsedCplt(), and TIM_DMATriggerCplt().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Extended Event Source

Defines
TIM Extended Event Source
TIM Exported Constants | TIM Extended Exported Constants

Defines

#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG
#define | TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G
#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG
#define | TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G

Define Documentation

#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG

A break event is generated

Definition at line 195 of file stm32h7xx_hal_tim_ex.h.

#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG

A break event is generated

Definition at line 366 of file stm32h7xx_hal_tim.h.

#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G

A break 2 event is generated

Definition at line 196 of file stm32h7xx_hal_tim_ex.h.

#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G

A break 2 event is generated

Definition at line 367 of file stm32h7xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G

A capture/compare event is generated on channel 1

Definition at line 189 of file stm32h7xx_hal_tim_ex.h.

#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G

A capture/compare event is generated on channel 1

Definition at line 360 of file stm32h7xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G

A capture/compare event is generated on channel 2

Definition at line 190 of file stm32h7xx_hal_tim_ex.h.

#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G

A capture/compare event is generated on channel 2

Definition at line 361 of file stm32h7xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G

A capture/compare event is generated on channel 3

Definition at line 191 of file stm32h7xx_hal_tim_ex.h.

#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G

A capture/compare event is generated on channel 3

Definition at line 362 of file stm32h7xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G

A capture/compare event is generated on channel 4

Definition at line 192 of file stm32h7xx_hal_tim_ex.h.

#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G

A capture/compare event is generated on channel 4

Definition at line 363 of file stm32h7xx_hal_tim.h.

#define TIM_EVENTSOURCE_COM TIM_EGR_COMG

A commutation event is generated

Definition at line 193 of file stm32h7xx_hal_tim_ex.h.

#define TIM_EVENTSOURCE_COM TIM_EGR_COMG

A commutation event is generated

Definition at line 364 of file stm32h7xx_hal_tim.h.

#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG

A trigger event is generated

Definition at line 194 of file stm32h7xx_hal_tim_ex.h.

#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG

A trigger event is generated

Definition at line 365 of file stm32h7xx_hal_tim.h.

#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG

Reinitialize the counter and generates an update of the registers

Definition at line 188 of file stm32h7xx_hal_tim_ex.h.

#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG

Reinitialize the counter and generates an update of the registers

Definition at line 359 of file stm32h7xx_hal_tim.h.

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STM32H753xx HAL User Manual: TIM Input Channel polarity

Defines
TIM Input Channel polarity
TIM Exported Constants

Defines

#define | TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U)
#define | TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P)
#define | TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Define Documentation

#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Polarity for TIx source

Definition at line 377 of file stm32h7xx_hal_tim.h.

#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P)

Polarity for TIx source

Definition at line 376 of file stm32h7xx_hal_tim.h.

#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U)

Polarity for TIx source

Definition at line 375 of file stm32h7xx_hal_tim.h.

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STM32H753xx HAL User Manual: TIM ETR Polarity

Defines
TIM ETR Polarity
TIM Exported Constants

Defines

#define | TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP)
#define | TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000U)

Define Documentation

#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP)

Polarity for ETR source

Definition at line 385 of file stm32h7xx_hal_tim.h.

#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000U)

Polarity for ETR source

Definition at line 386 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM ETR Prescaler

Defines
TIM ETR Prescaler
TIM Exported Constants

Defines

#define | TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000U)
#define | TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0)
#define | TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1)
#define | TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS)

Define Documentation

#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000U)

No prescaler is used

Definition at line 394 of file stm32h7xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0)

ETR input source is divided by 2

Definition at line 395 of file stm32h7xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1)

ETR input source is divided by 4

Definition at line 396 of file stm32h7xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS)

ETR input source is divided by 8

Definition at line 397 of file stm32h7xx_hal_tim.h.

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STM32H753xx HAL User Manual: TIM Counter Mode

Defines
TIM Counter Mode
TIM Exported Constants

Defines

#define | TIM_COUNTERMODE_UP ((uint32_t)0x0000U)
#define | TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define | TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define | TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS

Define Documentation

#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0

Center-aligned counting mode 1

Definition at line 408 of file stm32h7xx_hal_tim.h.

#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1

Center-aligned counting mode 2

Definition at line 409 of file stm32h7xx_hal_tim.h.

#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS

Center-aligned counting mode 3

Definition at line 410 of file stm32h7xx_hal_tim.h.

#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR

Down counting mode

Definition at line 407 of file stm32h7xx_hal_tim.h.

#define TIM_COUNTERMODE_UP ((uint32_t)0x0000U)

Up counting mode

Definition at line 406 of file stm32h7xx_hal_tim.h.

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STM32H753xx HAL User Manual: TIM Clock Division

Defines
TIM Clock Division
TIM Exported Constants

Defines

#define | TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000U)
#define | TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
#define | TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)

Define Documentation

#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000U)

Clock Division DIV1

Definition at line 420 of file stm32h7xx_hal_tim.h.

#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)

Clock Division DIV2

Definition at line 421 of file stm32h7xx_hal_tim.h.

#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)

Clock Division DIV4

Definition at line 422 of file stm32h7xx_hal_tim.h.

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STM32H753xx HAL User Manual: TIM Output Compare State

Defines
TIM Output Compare State
TIM Exported Constants

Defines

#define | TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000U)
#define | TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)

Define Documentation

#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000U)

Output State disabled

Definition at line 431 of file stm32h7xx_hal_tim.h.

#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)

Output State enabled

Definition at line 432 of file stm32h7xx_hal_tim.h.

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STM32H753xx HAL User Manual: TIM Auto-Reload Preload

Defines
TIM Auto-Reload Preload
TIM Exported Constants

Defines

#define | TIM_AUTORELOAD_PRELOAD_DISABLE ((uint32_t)0x0000U)
#define | TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE)

Define Documentation

#define TIM_AUTORELOAD_PRELOAD_DISABLE ((uint32_t)0x0000U)

TIMx_ARR register is not buffered

Definition at line 440 of file stm32h7xx_hal_tim.h.

#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE)

TIMx_ARR register is buffered

Definition at line 441 of file stm32h7xx_hal_tim.h.

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STM32H753xx HAL User Manual: TIM Output Fast State

Defines
TIM Output Fast State
TIM Exported Constants

Defines

#define | TIM_OCFAST_DISABLE ((uint32_t)0x0000U)
#define | TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)

Define Documentation

#define TIM_OCFAST_DISABLE ((uint32_t)0x0000U)

Definition at line 450 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)

Definition at line 451 of file stm32h7xx_hal_tim.h.

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STM32H753xx HAL User Manual: TIM Output Compare Polarity

Defines
TIM Output Compare Polarity
TIM Exported Constants

Defines

#define | TIM_OCPOLARITY_HIGH ((uint32_t)0x0000U)
#define | TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)

Define Documentation

#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000U)

Definition at line 461 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)

Definition at line 462 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Complementary Output Compare Polarity

Defines
TIM Complementary Output Compare Polarity
TIM Exported Constants

Defines

#define | TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000U)
#define | TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)

Define Documentation

#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000U)

Definition at line 472 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)

Definition at line 473 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Output Compare Idle State

Defines
TIM Output Compare Idle State
TIM Exported Constants

Defines

#define | TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
#define | TIM_OCIDLESTATE_RESET ((uint32_t)0x0000U)

Define Documentation

#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000U)

Definition at line 484 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)

Definition at line 483 of file stm32h7xx_hal_tim.h.

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STM32H753xx HAL User Manual: TIM Complementary Output Compare Idle State

Defines
TIM Complementary Output Compare Idle State
TIM Exported Constants

Defines

#define | TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
#define | TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000U)

Define Documentation

#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000U)

Definition at line 495 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)

Definition at line 494 of file stm32h7xx_hal_tim.h.

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STM32H753xx HAL User Manual: TIM Input Capture Polarity

Defines
TIM Input Capture Polarity
TIM Exported Constants

Defines

#define | TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Definition at line 509 of file stm32h7xx_hal_tim.h.

#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Definition at line 508 of file stm32h7xx_hal_tim.h.

#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Definition at line 507 of file stm32h7xx_hal_tim.h.

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STM32H753xx HAL User Manual: TIM Input Capture Selection

Defines
TIM Input Capture Selection
TIM Exported Constants

Defines

#define | TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0)
#define | TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1)
#define | TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S)

Define Documentation

#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0)

TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively

Definition at line 519 of file stm32h7xx_hal_tim.h.

#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1)

TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively

Definition at line 521 of file stm32h7xx_hal_tim.h.

#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S)

TIM Input 1, 2, 3 or 4 is selected to be connected to TRC

Definition at line 523 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Input Capture Prescaler

Defines
TIM Input Capture Prescaler
TIM Exported Constants

Defines

#define | TIM_ICPSC_DIV1 ((uint32_t)0x0000U)
#define | TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0)
#define | TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1)
#define | TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC)

Define Documentation

#define TIM_ICPSC_DIV1 ((uint32_t)0x0000U)

Capture performed each time an edge is detected on the capture input

Definition at line 533 of file stm32h7xx_hal_tim.h.

#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0)

Capture performed once every 2 events

Definition at line 534 of file stm32h7xx_hal_tim.h.

#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1)

Capture performed once every 4 events

Definition at line 535 of file stm32h7xx_hal_tim.h.

#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC)

Capture performed once every 8 events

Definition at line 536 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM One Pulse Mode

Defines
TIM One Pulse Mode
TIM Exported Constants

Defines

#define | TIM_OPMODE_SINGLE (TIM_CR1_OPM)
#define | TIM_OPMODE_REPETITIVE ((uint32_t)0x0000U)

Define Documentation

#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000U)

Definition at line 547 of file stm32h7xx_hal_tim.h.

#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)

Definition at line 546 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Encoder Mode

Defines
TIM Encoder Mode
TIM Exported Constants

Defines

#define | TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
#define | TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
#define | TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Define Documentation

#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)

Definition at line 555 of file stm32h7xx_hal_tim.h.

#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Definition at line 557 of file stm32h7xx_hal_tim.h.

#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)

Definition at line 556 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM interrupt Definition

Defines
TIM interrupt Definition
TIM Exported Constants

Defines

#define | TIM_IT_UPDATE (TIM_DIER_UIE)
#define | TIM_IT_CC1 (TIM_DIER_CC1IE)
#define | TIM_IT_CC2 (TIM_DIER_CC2IE)
#define | TIM_IT_CC3 (TIM_DIER_CC3IE)
#define | TIM_IT_CC4 (TIM_DIER_CC4IE)
#define | TIM_IT_COM (TIM_DIER_COMIE)
#define | TIM_IT_TRIGGER (TIM_DIER_TIE)
#define | TIM_IT_BREAK (TIM_DIER_BIE)

Define Documentation

#define TIM_IT_BREAK (TIM_DIER_BIE)

Definition at line 572 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC1 (TIM_DIER_CC1IE)

Definition at line 566 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC2 (TIM_DIER_CC2IE)

Definition at line 567 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC3 (TIM_DIER_CC3IE)

Definition at line 568 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC4 (TIM_DIER_CC4IE)

Definition at line 569 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_Start_IT(), and HAL_TIM_PWM_Stop_IT().

#define TIM_IT_COM (TIM_DIER_COMIE)

Definition at line 570 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), and HAL_TIMEx_ConfigCommutationEvent_IT().

#define TIM_IT_TRIGGER (TIM_DIER_TIE)

Definition at line 571 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define TIM_IT_UPDATE (TIM_DIER_UIE)

Definition at line 565 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop_IT(), and HAL_TIM_IRQHandler().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Commutation Source

Defines
TIM Commutation Source
TIM Exported Constants

Defines

#define | TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
#define | TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000U)

Define Documentation

#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000U)

Definition at line 581 of file stm32h7xx_hal_tim.h.

#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)

Definition at line 580 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM DMA Sources

Defines
TIM DMA Sources
TIM Exported Constants

Defines

#define | TIM_DMA_UPDATE (TIM_DIER_UDE)
#define | TIM_DMA_CC1 (TIM_DIER_CC1DE)
#define | TIM_DMA_CC2 (TIM_DIER_CC2DE)
#define | TIM_DMA_CC3 (TIM_DIER_CC3DE)
#define | TIM_DMA_CC4 (TIM_DIER_CC4DE)
#define | TIM_DMA_COM (TIM_DIER_COMDE)
#define | TIM_DMA_TRIGGER (TIM_DIER_TDE)

Define Documentation

#define TIM_DMA_CC1 (TIM_DIER_CC1DE)

Definition at line 592 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC2 (TIM_DIER_CC2DE)

Definition at line 593 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC3 (TIM_DIER_CC3DE)

Definition at line 594 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC4 (TIM_DIER_CC4DE)

Definition at line 595 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), and HAL_TIM_PWM_Stop_DMA().

#define TIM_DMA_COM (TIM_DIER_COMDE)

Definition at line 596 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), and HAL_TIMEx_ConfigCommutationEvent_DMA().

#define TIM_DMA_TRIGGER (TIM_DIER_TDE)

Definition at line 597 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define TIM_DMA_UPDATE (TIM_DIER_UDE)

Definition at line 591 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Flag Definition

Defines
TIM Flag Definition
TIM Exported Constants

Defines

#define | TIM_FLAG_UPDATE (TIM_SR_UIF)
#define | TIM_FLAG_CC1 (TIM_SR_CC1IF)
#define | TIM_FLAG_CC2 (TIM_SR_CC2IF)
#define | TIM_FLAG_CC3 (TIM_SR_CC3IF)
#define | TIM_FLAG_CC4 (TIM_SR_CC4IF)
#define | TIM_FLAG_CC5 (TIM_SR_CC5IF)
#define | TIM_FLAG_CC6 (TIM_SR_CC6IF)
#define | TIM_FLAG_COM (TIM_SR_COMIF)
#define | TIM_FLAG_TRIGGER (TIM_SR_TIF)
#define | TIM_FLAG_BREAK (TIM_SR_BIF)
#define | TIM_FLAG_BREAK2 (TIM_SR_B2IF)
#define | TIM_FLAG_SYSTEM_BREAK (TIM_SR_SBIF)
#define | TIM_FLAG_CC1OF (TIM_SR_CC1OF)
#define | TIM_FLAG_CC2OF (TIM_SR_CC2OF)
#define | TIM_FLAG_CC3OF (TIM_SR_CC3OF)
#define | TIM_FLAG_CC4OF (TIM_SR_CC4OF)

Define Documentation

#define TIM_FLAG_BREAK (TIM_SR_BIF)

Definition at line 616 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_BREAK2 (TIM_SR_B2IF)

Definition at line 617 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC1 (TIM_SR_CC1IF)

Definition at line 608 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)

Definition at line 619 of file stm32h7xx_hal_tim.h.

#define TIM_FLAG_CC2 (TIM_SR_CC2IF)

Definition at line 609 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)

Definition at line 620 of file stm32h7xx_hal_tim.h.

#define TIM_FLAG_CC3 (TIM_SR_CC3IF)

Definition at line 610 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)

Definition at line 621 of file stm32h7xx_hal_tim.h.

#define TIM_FLAG_CC4 (TIM_SR_CC4IF)

Definition at line 611 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)

Definition at line 622 of file stm32h7xx_hal_tim.h.

#define TIM_FLAG_CC5 (TIM_SR_CC5IF)

Definition at line 612 of file stm32h7xx_hal_tim.h.

#define TIM_FLAG_CC6 (TIM_SR_CC6IF)

Definition at line 613 of file stm32h7xx_hal_tim.h.

#define TIM_FLAG_COM (TIM_SR_COMIF)

Definition at line 614 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_SYSTEM_BREAK (TIM_SR_SBIF)

Definition at line 618 of file stm32h7xx_hal_tim.h.

#define TIM_FLAG_TRIGGER (TIM_SR_TIF)

Definition at line 615 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_UPDATE (TIM_SR_UIF)

Definition at line 607 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Clock Source

Defines
TIM Clock Source
TIM Exported Constants

Defines

#define | TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
#define | TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
#define | TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000U)
#define | TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
#define | TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)

Define Documentation

#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)

Definition at line 640 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)

Definition at line 631 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)

Definition at line 632 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000U)

Definition at line 633 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)

Definition at line 634 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)

Definition at line 635 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)

Definition at line 636 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)

Definition at line 638 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)

Definition at line 637 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)

Definition at line 639 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Clock Polarity

Defines
TIM Clock Polarity
TIM Exported Constants

Defines

#define | TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Polarity for TIx clock sources

Definition at line 653 of file stm32h7xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Polarity for TIx clock sources

Definition at line 652 of file stm32h7xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx clock sources

Definition at line 649 of file stm32h7xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx clock sources

Definition at line 650 of file stm32h7xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Polarity for TIx clock sources

Definition at line 651 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Clock Prescaler

Defines
TIM Clock Prescaler
TIM Exported Constants

Defines

#define | TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 661 of file stm32h7xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR Clock: Capture performed once every 2 events.

Definition at line 662 of file stm32h7xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR Clock: Capture performed once every 4 events.

Definition at line 663 of file stm32h7xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR Clock: Capture performed once every 8 events.

Definition at line 664 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Clear Input Polarity

Defines
TIM Clear Input Polarity
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Define Documentation

#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx pin

Definition at line 673 of file stm32h7xx_hal_tim.h.

#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx pin

Definition at line 674 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Clear Input Prescaler

Defines
TIM Clear Input Prescaler
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 683 of file stm32h7xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR pin: Capture performed once every 2 events.

Definition at line 684 of file stm32h7xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR pin: Capture performed once every 4 events.

Definition at line 685 of file stm32h7xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR pin: Capture performed once every 8 events.

Definition at line 686 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Off-state Selection for Run Mode

Defines
TIM Off-state Selection for Run Mode
TIM Exported Constants

Defines

#define | TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
#define | TIM_OSSR_DISABLE ((uint32_t)0x0000U)

Define Documentation

#define TIM_OSSR_DISABLE ((uint32_t)0x0000U)

Definition at line 696 of file stm32h7xx_hal_tim.h.

#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)

Definition at line 695 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Off-state Selection for Idle Mode

Defines
TIM Off-state Selection for Idle Mode
TIM Exported Constants

Defines

#define | TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
#define | TIM_OSSI_DISABLE ((uint32_t)0x0000U)

Define Documentation

#define TIM_OSSI_DISABLE ((uint32_t)0x0000U)

Definition at line 706 of file stm32h7xx_hal_tim.h.

#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)

Definition at line 705 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Lock Configuration

Defines
TIM Lock Configuration
TIM Exported Constants

Defines

#define | TIM_LOCKLEVEL_OFF ((uint32_t)0x0000U)
#define | TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
#define | TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
#define | TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)

Define Documentation

#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)

Definition at line 715 of file stm32h7xx_hal_tim.h.

#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)

Definition at line 716 of file stm32h7xx_hal_tim.h.

#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)

Definition at line 717 of file stm32h7xx_hal_tim.h.

#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000U)

Definition at line 714 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Break Input Enable

Defines
TIM Break Input Enable
TIM Exported Constants

Defines

#define | TIM_BREAK_ENABLE (TIM_BDTR_BKE)
#define | TIM_BREAK_DISABLE ((uint32_t)0x0000U)

Define Documentation

#define TIM_BREAK_DISABLE ((uint32_t)0x0000U)

Definition at line 726 of file stm32h7xx_hal_tim.h.

#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)

Definition at line 725 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Break Input Polarity

Defines
TIM Break Input Polarity
TIM Exported Constants

Defines

#define | TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000U)
#define | TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)

Define Documentation

#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)

Definition at line 736 of file stm32h7xx_hal_tim.h.

#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000U)

Definition at line 735 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Automatic Output Enable

Defines
TIM Automatic Output Enable
TIM Exported Constants

Defines

#define | TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
#define | TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000U)

Define Documentation

#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000U)

Definition at line 745 of file stm32h7xx_hal_tim.h.

#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)

Definition at line 744 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Master Mode Selection

Defines
TIM Master Mode Selection
TIM Exported Constants

Defines

#define | TIM_TRGO_RESET ((uint32_t)0x0000U)
#define | TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
#define | TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
#define | TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
#define | TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
#define | TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))

Define Documentation

#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)

Definition at line 756 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))

Definition at line 758 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)

Definition at line 759 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))

Definition at line 760 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))

Definition at line 761 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))

Definition at line 762 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO_RESET ((uint32_t)0x0000U)

Definition at line 755 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)

Definition at line 757 of file stm32h7xx_hal_tim.h.

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STM32H753xx HAL User Manual: TIM Master Mode Selection 2 (TRGO2)

Defines
TIM Master Mode Selection 2 (TRGO2)
TIM Exported Constants

Defines

#define | TIM_TRGO2_RESET ((uint32_t)0x00000000U)
#define | TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
#define | TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
#define | TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
#define | TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))

Define Documentation

#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))

Definition at line 771 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))

Definition at line 773 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))

Definition at line 774 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))

Definition at line 775 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))

Definition at line 776 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))

Definition at line 777 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))

Definition at line 783 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))

Definition at line 782 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))

Definition at line 780 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))

Definition at line 778 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))

Definition at line 785 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))

Definition at line 784 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))

Definition at line 779 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))

Definition at line 781 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_RESET ((uint32_t)0x00000000U)

Definition at line 770 of file stm32h7xx_hal_tim.h.

#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))

Definition at line 772 of file stm32h7xx_hal_tim.h.

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STM32H753xx HAL User Manual: TIM Master/Slave Mode

Defines
TIM Master/Slave Mode
TIM Exported Constants

Defines

#define | TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080U)
#define | TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000U)

Define Documentation

#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000U)

Definition at line 795 of file stm32h7xx_hal_tim.h.

#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080U)

Definition at line 794 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Slave mode

Defines
TIM Slave mode
TIM Exported Constants

Defines

#define | TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000U)
#define | TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
#define | TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
#define | TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
#define | TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
#define | TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))

Define Documentation

#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))

Definition at line 809 of file stm32h7xx_hal_tim.h.

#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000U)

Definition at line 804 of file stm32h7xx_hal_tim.h.

#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))

Definition at line 808 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_ITRx_SetConfig().

#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))

Definition at line 806 of file stm32h7xx_hal_tim.h.

#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))

Definition at line 805 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))

Definition at line 807 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Trigger Selection

Defines
TIM Trigger Selection
TIM Exported Constants

Defines

#define | TIM_TS_ITR0 ((uint32_t)0x0000U)
#define | TIM_TS_ITR1 ((uint32_t)0x0010U)
#define | TIM_TS_ITR2 ((uint32_t)0x0020U)
#define | TIM_TS_ITR3 ((uint32_t)0x0030U)
#define | TIM_TS_TI1F_ED ((uint32_t)0x0040U)
#define | TIM_TS_TI1FP1 ((uint32_t)0x0050U)
#define | TIM_TS_TI2FP2 ((uint32_t)0x0060U)
#define | TIM_TS_ETRF ((uint32_t)0x0070U)
#define | TIM_TS_NONE ((uint32_t)0xFFFFU)

Define Documentation

#define TIM_TS_ETRF ((uint32_t)0x0070U)

Definition at line 825 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR0 ((uint32_t)0x0000U)

Definition at line 818 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR1 ((uint32_t)0x0010U)

Definition at line 819 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR2 ((uint32_t)0x0020U)

Definition at line 820 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR3 ((uint32_t)0x0030U)

Definition at line 821 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_NONE ((uint32_t)0xFFFFU)

Definition at line 826 of file stm32h7xx_hal_tim.h.

#define TIM_TS_TI1F_ED ((uint32_t)0x0040U)

Definition at line 822 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_TI1FP1 ((uint32_t)0x0050U)

Definition at line 823 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_TI2FP2 ((uint32_t)0x0060U)

Definition at line 824 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), and TIM_SlaveTimer_SetConfig().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Trigger Polarity

Defines
TIM Trigger Polarity
TIM Exported Constants

Defines

#define | TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 839 of file stm32h7xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 838 of file stm32h7xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx trigger sources

Definition at line 835 of file stm32h7xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx trigger sources

Definition at line 836 of file stm32h7xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 837 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Trigger Prescaler

Defines
TIM Trigger Prescaler
TIM Exported Constants

Defines

#define | TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 848 of file stm32h7xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR Trigger: Capture performed once every 2 events.

Definition at line 849 of file stm32h7xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR Trigger: Capture performed once every 4 events.

Definition at line 850 of file stm32h7xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR Trigger: Capture performed once every 8 events.

Definition at line 851 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM TI1 Input Selection

Defines
TIM TI1 Input Selection
TIM Exported Constants

Defines

#define | TIM_TI1SELECTION_CH1 ((uint32_t)0x0000U)
#define | TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)

Define Documentation

#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000U)

Definition at line 861 of file stm32h7xx_hal_tim.h.

#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)

Definition at line 862 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM DMA Burst Length

Defines
TIM DMA Burst Length
TIM Exported Constants

Defines

#define | TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
#define | TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
#define | TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
#define | TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
#define | TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
#define | TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
#define | TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
#define | TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
#define | TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
#define | TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
#define | TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
#define | TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
#define | TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
#define | TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
#define | TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
#define | TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
#define | TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
#define | TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)

Define Documentation

#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)

Definition at line 880 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)

Definition at line 881 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)

Definition at line 882 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)

Definition at line 883 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)

Definition at line 884 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)

Definition at line 885 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)

Definition at line 886 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)

Definition at line 887 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)

Definition at line 888 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)

Definition at line 871 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)

Definition at line 872 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)

Definition at line 873 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)

Definition at line 874 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)

Definition at line 875 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)

Definition at line 876 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)

Definition at line 877 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)

Definition at line 878 of file stm32h7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)

Definition at line 879 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM DMA Handle Index

Defines
TIM DMA Handle Index
TIM Exported Constants

Defines

#define | TIM_DMA_ID_UPDATE ((uint16_t) 0x0U)
#define | TIM_DMA_ID_CC1 ((uint16_t) 0x1U)
#define | TIM_DMA_ID_CC2 ((uint16_t) 0x2U)
#define | TIM_DMA_ID_CC3 ((uint16_t) 0x3U)
#define | TIM_DMA_ID_CC4 ((uint16_t) 0x4U)
#define | TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U)
#define | TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U)

Define Documentation

#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U)

Index of the DMA handle used for Capture/Compare 1 DMA requests

Definition at line 898 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_DMACaptureCplt(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U)

Index of the DMA handle used for Capture/Compare 2 DMA requests

Definition at line 899 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_DMACaptureCplt(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U)

Index of the DMA handle used for Capture/Compare 3 DMA requests

Definition at line 900 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_DMACaptureCplt(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U)

Index of the DMA handle used for Capture/Compare 4 DMA requests

Definition at line 901 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_DMACaptureCplt(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), and HAL_TIM_PWM_Start_DMA().

#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U)

Index of the DMA handle used for Commutation DMA requests

Definition at line 902 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), and HAL_TIMEx_ConfigCommutationEvent_DMA().

#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U)

Index of the DMA handle used for Trigger DMA requests

Definition at line 903 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U)

Index of the DMA handle used for Update DMA requests

Definition at line 897 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Capture/Compare Channel State

Defines
TIM Capture/Compare Channel State
TIM Exported Constants

Defines

#define | TIM_CCx_ENABLE ((uint32_t)0x0001U)
#define | TIM_CCx_DISABLE ((uint32_t)0x0000U)
#define | TIM_CCxN_ENABLE ((uint32_t)0x0004U)
#define | TIM_CCxN_DISABLE ((uint32_t)0x0000U)

Define Documentation

#define TIM_CCx_DISABLE ((uint32_t)0x0000U)

Definition at line 912 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), and HAL_TIMEx_HallSensor_Stop_IT().

#define TIM_CCx_ENABLE ((uint32_t)0x0001U)

Definition at line 911 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), and HAL_TIMEx_HallSensor_Start_IT().

#define TIM_CCxN_DISABLE ((uint32_t)0x0000U)

Definition at line 914 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_CCxN_ENABLE ((uint32_t)0x0004U)

Definition at line 913 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Exported Macros

Defines
TIM Exported Macros
TIM

Defines

#define | __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
Reset TIM handle state.
#define | __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
Enable the TIM peripheral.
#define | __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
Set the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
Enable the TIM main Output.
#define | TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define | TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
#define | __HAL_TIM_DISABLE(__HANDLE__)
Disable the TIM peripheral.
#define | __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_MOE_DISABLE(__HANDLE__)
Disable the TIM main Output.
#define | __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) ((__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE))
Disable the TIM main Output.
#define | __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
Enable the specified TIM interrupt.
#define | __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
Disable the specified TIM interrupt.
#define | __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
Enable the specified DMA request.
#define | __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
Disable the specified DMA request.
#define | __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
Check whether the specified TIM interrupt flag is set or not.
#define | __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the specified TIM interrupt flag.
#define | __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified TIM interrupt source is enabled or not.
#define | __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(uint32_t)(__INTERRUPT__))
Clear the TIM interrupt pending bits.
#define | __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
Indicates whether or not the TIM Counter is used as downcounter.
#define | __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
Set the TIM Prescaler on runtime.
#define | TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
#define | TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
#define | TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
#define | TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)
#define | __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
Set the TIM Counter Register value on runtime.
#define | __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
Get the TIM Counter Register value on runtime.
#define | __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)
Set the TIM Autoreload Register value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
Get the TIM Autoreload Register value on runtime.
#define | __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__)
Set the TIM Clock Division value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
Get the TIM Clock Division value on runtime.
#define | __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)
Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
#define | __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)
Get the TIM Input Capture prescaler on runtime.
#define | __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Set the TIM Capture x input polarity on runtime.
#define | __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__)
Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
#define | __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__)
Get the TIM Capture Compare Register value on runtime.

Define Documentation

#define __HAL_TIM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clear the specified TIM interrupt flag.

Parameters:
__HANDLE__,: specifies the TIM Handle.
__FLAG__,: specifies the TIM interrupt flag to clear. This parameter can be one of the following values:
  • TIM_FLAG_UPDATE: Update interrupt flag
  • TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  • TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  • TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  • TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  • TIM_FLAG_CC5: Compare 5 interrupt flag
  • TIM_FLAG_CC6: Compare 6 interrupt flag
  • TIM_FLAG_COM: Commutation interrupt flag
  • TIM_FLAG_TRIGGER: Trigger interrupt flag
  • TIM_FLAG_BREAK: Break interrupt flag
  • TIM_FLAG_BREAK2: Break 2 interrupt flag
  • TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
  • TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  • TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  • TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  • TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 1128 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->SR = ~(uint32_t)(__INTERRUPT__))

Clear the TIM interrupt pending bits.

Parameters:
__HANDLE__,: TIM handle
__INTERRUPT__,: specifies the interrupt pending bit to clear. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
None

Definition at line 1161 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_DISABLE ( __HANDLE__ )
Value:
do { \
                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
                            { \
                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
                            { \
                              (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
                            } \
                          } \
                        } while(0)

Disable the TIM peripheral.

Parameters:
__HANDLE__,: TIM handle
Return values:
None

Definition at line 969 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_DISABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->DIER &= ~(__DMA__))

Disable the specified DMA request.

Parameters:
__HANDLE__,: specifies the TIM Handle.
__DMA__,: specifies the TIM DMA request to disable. This parameter can be one of the following values:
  • TIM_DMA_UPDATE: Update DMA request
  • TIM_DMA_CC1: Capture/Compare 1 DMA request
  • TIM_DMA_CC2: Capture/Compare 2 DMA request
  • TIM_DMA_CC3: Capture/Compare 3 DMA request
  • TIM_DMA_CC4: Capture/Compare 4 DMA request
  • TIM_DMA_COM: Commutation DMA request
  • TIM_DMA_TRIGGER: Trigger DMA request
  • TIM_DMA_BREAK: Break DMA request
Return values:
None

Definition at line 1080 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define __HAL_TIM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))

Disable the specified TIM interrupt.

Parameters:
__HANDLE__,: specifies the TIM Handle.
__INTERRUPT__,: specifies the TIM interrupt source to disable. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
None

Definition at line 1049 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Stop_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))

Enable the TIM peripheral.

Parameters:
__HANDLE__,: TIM handle
Return values:
None

Definition at line 940 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_ENABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->DIER |= (__DMA__))

Enable the specified DMA request.

Parameters:
__HANDLE__,: specifies the TIM Handle.
__DMA__,: specifies the TIM DMA request to enable. This parameter can be one of the following values:
  • TIM_DMA_UPDATE: Update DMA request
  • TIM_DMA_CC1: Capture/Compare 1 DMA request
  • TIM_DMA_CC2: Capture/Compare 2 DMA request
  • TIM_DMA_CC3: Capture/Compare 3 DMA request
  • TIM_DMA_CC4: Capture/Compare 4 DMA request
  • TIM_DMA_COM: Commutation DMA request
  • TIM_DMA_TRIGGER: Trigger DMA request
Return values:
None

Definition at line 1064 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

#define __HAL_TIM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))

Enable the specified TIM interrupt.

Parameters:
__HANDLE__,: specifies the TIM Handle.
__INTERRUPT__,: specifies the TIM interrupt source to enable. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
None

Definition at line 1033 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_IT(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_ConfigCommutationEvent_IT(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start_IT(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_GET_AUTORELOAD ( __HANDLE__ ) ((__HANDLE__)->Instance->ARR)

Get the TIM Autoreload Register value on runtime.

Parameters:
__HANDLE__,: TIM handle.
Return values:
16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)

Definition at line 1236 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_GET_CLOCKDIVISION ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)

Get the TIM Clock Division value on runtime.

Parameters:
__HANDLE__,: TIM handle.
Return values:
The clock division can be one of the following values:
  • TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
  • TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
  • TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT

Definition at line 1263 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_GET_COMPARE | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
 ((__HANDLE__)->Instance->CCR6))

Get the TIM Capture Compare Register value on runtime.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__,: TIM Channel associated with the capture compare register This parameter can be one of the following values:
  • TIM_CHANNEL_1: get capture/compare 1 register value
  • TIM_CHANNEL_2: get capture/compare 2 register value
  • TIM_CHANNEL_3: get capture/compare 3 register value
  • TIM_CHANNEL_4: get capture/compare 4 register value
  • TIM_CHANNEL_5: get capture/compare 5 register value
  • TIM_CHANNEL_6: get capture/compare 6 register value
Return values:
None | by
16-bit | or 32-bit value of the capture/compare register (TIMx_CCRy)

Definition at line 1365 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_GET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->CNT)

Get the TIM Counter Register value on runtime.

Parameters:
__HANDLE__,: TIM handle.
Return values:
16-bit or 32-bit value of the timer counter register (TIMx_CNT)

Definition at line 1217 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))

Check whether the specified TIM interrupt flag is set or not.

Parameters:
__HANDLE__,: specifies the TIM Handle.
__FLAG__,: specifies the TIM interrupt flag to check. This parameter can be one of the following values:
  • TIM_FLAG_UPDATE: Update interrupt flag
  • TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  • TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  • TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  • TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  • TIM_FLAG_CC5: Compare 5 interrupt flag
  • TIM_FLAG_CC6: Compare 6 interrupt flag
  • TIM_FLAG_COM: Commutation interrupt flag
  • TIM_FLAG_TRIGGER: Trigger interrupt flag
  • TIM_FLAG_BREAK: Break interrupt flag
  • TIM_FLAG_BREAK2: Break 2 interrupt flag
  • TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
  • TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  • TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  • TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  • TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 1104 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_GET_ICPRESCALER | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)

Get the TIM Input Capture prescaler on runtime.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__,: TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: get input capture 1 prescaler value
  • TIM_CHANNEL_2: get input capture 2 prescaler value
  • TIM_CHANNEL_3: get input capture 3 prescaler value
  • TIM_CHANNEL_4: get input capture 4 prescaler value
Return values:
The input capture prescaler can be one of the following values:
  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events

Definition at line 1304 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified TIM interrupt source is enabled or not.

Parameters:
__HANDLE__,: TIM handle
__INTERRUPT__,: specifies the TIM interrupt source to check. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
The state of TIM_IT (SET or RESET).

Definition at line 1145 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_IS_TIM_COUNTING_DOWN ( __HANDLE__ ) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))

Indicates whether or not the TIM Counter is used as downcounter.

Parameters:
__HANDLE__,: TIM handle.
Return values:
False (Counter used as upcounter) or True (Counter used as downcounter)
Note:
This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder mode.

Definition at line 1170 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_MOE_DISABLE ( __HANDLE__ )
Value:
do { \
                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
                          { \
                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
                            { \
                              (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
                            } \
                            } \
                        } while(0)

Disable the TIM main Output.

Parameters:
__HANDLE__,: TIM handle
Note:
The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
Return values:
None

Definition at line 999 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY ( __HANDLE__ ) ((__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE))

Disable the TIM main Output.

Parameters:
__HANDLE__,: TIM handle
Return values:
None
Note:
The Main Output Enable of a timer instance is disabled uncondiotionally

Definition at line 1017 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_MOE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))

Enable the TIM main Output.

Parameters:
__HANDLE__,: TIM handle
Return values:
None

Definition at line 957 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)

Reset TIM handle state.

Parameters:
__HANDLE__,: TIM handle.
Return values:
None

Definition at line 933 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_SET_AUTORELOAD | ( | __HANDLE__,
 |  | __AUTORELOAD__
 | ) |
Value:
do{                                                    \
                              (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
                              (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
                          } while(0)

Set the TIM Autoreload Register value on runtime without calling another time any Init function.

Parameters:
__HANDLE__,: TIM handle.
__AUTORELOAD__,: specifies the Counter register new value.
Return values:
None

Definition at line 1225 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_SET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __POLARITY__
 | ) |
Value:
do{                                                                     \
          TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
          TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
        }while(0)

Set the TIM Capture x input polarity on runtime.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__,: TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__POLARITY__,: Polarity for TIx source
  • TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
  • TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
Return values:
None

Definition at line 1325 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_SET_CLOCKDIVISION | ( | __HANDLE__,
 |  | __CKD__
 | ) |
Value:
do{                                                    \
                              (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
                              (__HANDLE__)->Instance->CR1 |= (__CKD__);                   \
                              (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
                          } while(0)

Set the TIM Clock Division value on runtime without calling another time any Init function.

Parameters:
__HANDLE__,: TIM handle.
__CKD__,: specifies the clock division value. This parameter can be one of the following value:
  • TIM_CLOCKDIVISION_DIV1
  • TIM_CLOCKDIVISION_DIV2
  • TIM_CLOCKDIVISION_DIV4
Return values:
None

Definition at line 1248 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_SET_COMPARE | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __COMPARE__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))

Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__,: TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
__COMPARE__,: specifies the Capture Compare register new value.
Return values:
None

Definition at line 1344 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_SET_COUNTER | ( | __HANDLE__,
 |  | __COUNTER__
 | ) | ((__HANDLE__)->Instance->CNT = (__COUNTER__))

Set the TIM Counter Register value on runtime.

Parameters:
__HANDLE__,: TIM handle.
__COUNTER__,: specifies the Counter register new value.
Return values:
None

Definition at line 1209 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_SET_ICPRESCALER | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __ICPSC__
 | ) |
Value:
do{                                                    \
                              TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
                              TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
                          } while(0)

Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__,: TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__ICPSC__,: specifies the Input Capture4 prescaler new value. This parameter can be one of the following values:
  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1283 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_SET_PRESCALER | ( | __HANDLE__,
 |  | __PRESC__
 | ) | ((__HANDLE__)->Instance->PSC = (__PRESC__))

Set the TIM Prescaler on runtime.

Parameters:
__HANDLE__,: TIM handle.
__PRESC__,: specifies the Prescaler new value.
Return values:
None

Definition at line 1178 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_URS_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))

Reset the Update Request Source (URS) bit of the TIMx_CR1 register.

Parameters:
__HANDLE__,: TIM handle.
Note:
When the USR bit of the TIMx_CR1 register is reset, any of the following events generate an update interrupt or DMA request (if enabled): _ Counter overflow underflow _ Setting the UG bit _ Update generation through the slave mode controller
Return values:
None

Definition at line 990 of file stm32h7xx_hal_tim.h.

#define __HAL_TIM_URS_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))

Set the Update Request Source (URS) bit of the TIMx_CR1 register.

Parameters:
__HANDLE__,: TIM handle.
Note:
When the USR bit of the TIMx_CR1 register is set, only counter overflow/underflow generates an update interrupt or DMA request (if enabled)
Return values:
None

Definition at line 950 of file stm32h7xx_hal_tim.h.

#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))

Definition at line 961 of file stm32h7xx_hal_tim.h.

#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))

Definition at line 962 of file stm32h7xx_hal_tim.h.

#define TIM_RESET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
 ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))

Definition at line 1198 of file stm32h7xx_hal_tim.h.

#define TIM_RESET_ICPRESCALERVALUE | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))

Definition at line 1186 of file stm32h7xx_hal_tim.h.

#define TIM_SET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __POLARITY__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12))))

Definition at line 1192 of file stm32h7xx_hal_tim.h.

#define TIM_SET_ICPRESCALERVALUE | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __ICPSC__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))

Definition at line 1180 of file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Private Constants

TIM Private Constants
TIM
Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Private Macros

Defines
TIM Private Macros
TIM

Defines

#define | IS_TIM_CLEARINPUT_SOURCE(__MODE__)
#define | IS_TIM_DMA_BASE(__BASE__)
#define | IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define | IS_TIM_COUNTER_MODE(__MODE__)
#define | IS_TIM_CLOCKDIVISION_DIV(__DIV__)
#define | IS_TIM_AUTORELOAD_PRELOAD(PRELOAD)
#define | IS_TIM_FAST_STATE(__STATE__)
#define | IS_TIM_OC_POLARITY(__POLARITY__)
#define | IS_TIM_OCN_POLARITY(__POLARITY__)
#define | IS_TIM_OCIDLE_STATE(__STATE__)
#define | IS_TIM_OCNIDLE_STATE(__STATE__)
#define | IS_TIM_IC_POLARITY(__POLARITY__)
#define | IS_TIM_IC_SELECTION(__SELECTION__)
#define | IS_TIM_IC_PRESCALER(__PRESCALER__)
#define | IS_TIM_OPM_MODE(__MODE__)
#define | IS_TIM_ENCODER_MODE(__MODE__)
#define | IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define | IS_TIM_CHANNELS(__CHANNEL__)
#define | IS_TIM_OPM_CHANNELS(__CHANNEL__)
#define | IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__)
#define | IS_TIM_CLOCKSOURCE(__CLOCK__)
#define | IS_TIM_CLOCKPOLARITY(__POLARITY__)
#define | IS_TIM_CLOCKPRESCALER(__PRESCALER__)
#define | IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
#define | IS_TIM_CLEARINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__)
#define | IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_OSSR_STATE(__STATE__)
#define | IS_TIM_OSSI_STATE(__STATE__)
#define | IS_TIM_LOCK_LEVEL(__LEVEL__)
#define | IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xF)
#define | IS_TIM_BREAK_STATE(__STATE__)
#define | IS_TIM_BREAK_POLARITY(__POLARITY__)
#define | IS_TIM_BREAK2_STATE(__STATE__)
#define | IS_TIM_BREAK2_POLARITY(__POLARITY__)
#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__)
#define | IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
#define | IS_TIM_TRGO_SOURCE(__SOURCE__)
#define | IS_TIM_TRGO2_SOURCE(__SOURCE__)
#define | IS_TIM_MSM_STATE(__STATE__)
#define | IS_TIM_SLAVE_MODE(__MODE__)
#define | IS_TIM_PWM_MODE(__MODE__)
#define | IS_TIM_OC_MODE(__MODE__)
#define | IS_TIM_TRIGGER_SELECTION(__SELECTION__)
#define | IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__)
#define | IS_TIM_TRIGGERPOLARITY(__POLARITY__)
#define | IS_TIM_TRIGGERPRESCALER(__PRESCALER__)
#define | IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_TI1SELECTION(__TI1SELECTION__)
#define | IS_TIM_DMA_LENGTH(__LENGTH__)
#define | IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
#define | IS_TIM_BREAK_SYSTEM(__CONFIG__)

Define Documentation

#define IS_TIM_AUTOMATIC_OUTPUT_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))

Definition at line 1553 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_AUTORELOAD_PRELOAD ( PRELOAD )
Value:
(((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))

Definition at line 1436 of file stm32h7xx_hal_tim.h.

#define IS_TIM_BREAK2_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))

Definition at line 1550 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK2_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_BREAK2_ENABLE) || \
                                            ((__STATE__) == TIM_BREAK2_DISABLE))

Definition at line 1547 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_FILTER ( __BRKFILTER__ ) ((__BRKFILTER__) <= 0xF)

Definition at line 1538 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))

Definition at line 1544 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_BREAK_ENABLE) || \
                                            ((__STATE__) == TIM_BREAK_DISABLE))

Definition at line 1541 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_SYSTEM ( __CONFIG__ )
Value:
(((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                 || \
                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                 || \
                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR)  || \
                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))

Definition at line 1666 of file stm32h7xx_hal_tim.h.

#define IS_TIM_CHANNELS ( __CHANNEL__ )
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_5) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_6) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))

Definition at line 1477 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and TIM_CCxChannelCmd().

#define IS_TIM_CLEARINPUT_FILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xFU)

Definition at line 1524 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))

Definition at line 1516 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))

Definition at line 1519 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_SOURCE ( __MODE__ )
Value:
(((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)      || \
                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))

Definition at line 1393 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLOCKDIVISION_DIV ( __DIV__ )
Value:
(((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))

Definition at line 1432 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_CLOCKFILTER ( ICFILTER ) ((ICFILTER) <= 0xF)

Definition at line 1514 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKPOLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))

Definition at line 1503 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKPRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))

Definition at line 1509 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKSOURCE ( __CLOCK__ )
Value:
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))

Definition at line 1492 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_COMPLEMENTARY_CHANNELS ( __CHANNEL__ )
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) || \
                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \
                                                    ((__CHANNEL__) == TIM_CHANNEL_3))

Definition at line 1488 of file stm32h7xx_hal_tim.h.

#define IS_TIM_COUNTER_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_COUNTERMODE_UP)              || \
                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))

Definition at line 1426 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_DEADTIME ( __DEADTIME__ ) ((__DEADTIME__) <= 0xFFU)

Definition at line 1664 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_DMA_BASE ( __BASE__ )
Value:
(((__BASE__) == TIM_DMABASE_CR1)   || \
                                   ((__BASE__) == TIM_DMABASE_CR2)   || \
                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \
                                   ((__BASE__) == TIM_DMABASE_DIER)  || \
                                   ((__BASE__) == TIM_DMABASE_SR)    || \
                                   ((__BASE__) == TIM_DMABASE_EGR)   || \
                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
                                   ((__BASE__) == TIM_DMABASE_CCER)  || \
                                   ((__BASE__) == TIM_DMABASE_CNT)   || \
                                   ((__BASE__) == TIM_DMABASE_PSC)   || \
                                   ((__BASE__) == TIM_DMABASE_ARR)   || \
                                   ((__BASE__) == TIM_DMABASE_RCR)   || \
                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \
                                   ((__BASE__) == TIM_DMABASE_BDTR)  || \
                                   ((__BASE__) == TIM_DMABASE_CCMR3) || \
                                   ((__BASE__) == TIM_DMABASE_CCR5)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR6)  || \
                                   ((__BASE__) == TIM_DMABASE_AF1)   || \
                                   ((__BASE__) == TIM_DMABASE_AF2)   || \
                                   ((__BASE__) == TIM_DMABASE_TISEL))

Definition at line 1397 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

#define IS_TIM_DMA_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))

Definition at line 1643 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

#define IS_TIM_DMA_SOURCE ( __SOURCE__ ) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))

Definition at line 1475 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

#define IS_TIM_ENCODER_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_ENCODERMODE_TI1) || \
                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \
                                            ((__MODE__) == TIM_ENCODERMODE_TI12))

Definition at line 1471 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

#define IS_TIM_EVENT_SOURCE ( __SOURCE__ ) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))

Definition at line 1423 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_GenerateEvent().

#define IS_TIM_FAST_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OCFAST_DISABLE) || \
                                            ((__STATE__) == TIM_OCFAST_ENABLE))

Definition at line 1440 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_GROUPCH5 ( __OCREF__ ) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))

Definition at line 1556 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_GroupChannel5().

#define IS_TIM_IC_FILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xFU)

Definition at line 1662 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))

Definition at line 1455 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_ICPSC_DIV1) || \
                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))

Definition at line 1463 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_SELECTION ( __SELECTION__ )
Value:
(((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))

Definition at line 1459 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), and HAL_TIM_IC_ConfigChannel().

#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION ( __SELECTION__ )
Value:
(((__SELECTION__) == TIM_TS_ITR0) || \
                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
                                                               ((__SELECTION__) == TIM_TS_NONE))

Definition at line 1620 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), and HAL_TIMEx_ConfigCommutationEvent_IT().

#define IS_TIM_LOCK_LEVEL ( __LEVEL__ )
Value:
(((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))

Definition at line 1533 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_MSM_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))

Definition at line 1585 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_OC_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_OCMODE_TIMING)             || \
                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))

Definition at line 1602 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel().

#define IS_TIM_OC_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))

Definition at line 1443 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_OCIDLE_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OCIDLESTATE_SET) || \
                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))

Definition at line 1449 of file stm32h7xx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

#define IS_TIM_OCN_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))

Definition at line 1446 of file stm32h7xx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

#define IS_TIM_OCNIDLE_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OCNIDLESTATE_SET) || \
                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))

Definition at line 1452 of file stm32h7xx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

#define IS_TIM_OPM_CHANNELS ( __CHANNEL__ )
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_2))

Definition at line 1485 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

#define IS_TIM_OPM_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_OPMODE_SINGLE) || \
                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))

Definition at line 1468 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_Init().

#define IS_TIM_OSSI_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OSSI_ENABLE) || \
                                            ((__STATE__) == TIM_OSSI_DISABLE))

Definition at line 1530 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_OSSR_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OSSR_ENABLE) || \
                                            ((__STATE__) == TIM_OSSR_DISABLE))

Definition at line 1527 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_PWM_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_OCMODE_PWM1)               || \
                                   ((__MODE__) == TIM_OCMODE_PWM2)               || \
                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))

Definition at line 1595 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_SLAVE_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
                                     ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))

Definition at line 1588 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define IS_TIM_TI1SELECTION ( __TI1SELECTION__ )
Value:
(((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))

Definition at line 1640 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigTI1Input().

#define IS_TIM_TRGO2_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == TIM_TRGO2_RESET)                        || \
                                         ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
                                         ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
                                         ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))

Definition at line 1567 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_TRGO_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == TIM_TRGO_RESET)  || \
                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \
                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
                                        ((__SOURCE__) == TIM_TRGO_OC4REF))

Definition at line 1558 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_TRIGGER_SELECTION ( __SELECTION__ )
Value:
(((__SELECTION__) == TIM_TS_ITR0) || \
                                                 ((__SELECTION__) == TIM_TS_ITR1) || \
                                                 ((__SELECTION__) == TIM_TS_ITR2) || \
                                                 ((__SELECTION__) == TIM_TS_ITR3) || \
                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \
                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \
                                                 ((__SELECTION__) == TIM_TS_ETRF))

Definition at line 1611 of file stm32h7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define IS_TIM_TRIGGERFILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xFU)

Definition at line 1638 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define IS_TIM_TRIGGERPOLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))

Definition at line 1627 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define IS_TIM_TRIGGERPRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))

Definition at line 1633 of file stm32h7xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Private Functions

Functions
TIM Private Functions
TIM

Functions

void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM Output Compare 1 configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM Output Compare 2 configuration.
void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM Output Compare 3 configuration.
void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM Output Compare 4 configuration.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | HAL_TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | HAL_TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | HAL_TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.

Function Documentation

void HAL_TIM_DMACaptureCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Capture complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4708 of file stm32h7xx_hal_tim.c.

References TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), and HAL_TIMEx_HallSensor_Start_DMA().

void HAL_TIM_DMADelayPulseCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Delay Pulse complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4675 of file stm32h7xx_hal_tim.c.

References TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_WriteStart(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void HAL_TIM_DMAError ( DMA_HandleTypeDef * hdma )

TIM DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4660 of file stm32h7xx_hal_tim.c.

References HAL_TIM_ErrorCallback(), HAL_TIM_STATE_READY, and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void TIM_Base_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_Base_InitTypeDef * | Structure
 | ) |  |

Time Base configuration.

Parameters:
TIMx,: TIM periheral
Structure,: TIM Base configuration structure
Return values:
None

Definition at line 4772 of file stm32h7xx_hal_tim.c.

References TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, TIM_Base_InitTypeDef::Period, TIM_Base_InitTypeDef::Prescaler, and TIM_Base_InitTypeDef::RepetitionCounter.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

void TIM_CCxChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelState
 | ) |  |

Enables or disables the TIM Capture Compare Channel x.

Parameters:
TIMx to select the TIM peripheral
Channel,: specifies the TIM Channel This parameter can be one of the following values:
  • TIM_Channel_1: TIM Channel 1
  • TIM_Channel_2: TIM Channel 2
  • TIM_Channel_3: TIM Channel 3
  • TIM_Channel_4: TIM Channel 4
ChannelState,: specifies the TIM Channel CCxE bit new state. This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
Return values:
None

Definition at line 5677 of file stm32h7xx_hal_tim.c.

References assert_param, and IS_TIM_CHANNELS.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), and HAL_TIMEx_HallSensor_Stop_IT().

void TIM_ETR_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ExtTRGPrescaler,
 |  | uint32_t | TIM_ExtTRGPolarity,
 |  | uint32_t | ExtTRGFilter
 | ) |  |

Configures the TIMx External Trigger (ETR).

Parameters:
TIMx to select the TIM peripheral
TIM_ExtTRGPrescaler,: The external Trigger Prescaler. This parameter can be one of the following values:
  • TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
  • TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
  • TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
  • TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
TIM_ExtTRGPolarity,: The external Trigger Polarity. This parameter can be one of the following values:
  • TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
  • TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
ExtTRGFilter,: External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 5647 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), and TIM_SlaveTimer_SetConfig().

void TIM_OC1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

TIM Output Compare 1 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The Output configuration structure
Return values:
None

Definition at line 4819 of file stm32h7xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_1.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_OC2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

TIM Output Compare 2 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The Output configuration structure
Return values:
None

Definition at line 4893 of file stm32h7xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_2.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

void TIM_OC3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

TIM Output Compare 3 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The output configuration structure
Return values:
None

Definition at line 4970 of file stm32h7xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_3.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_OC4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

TIM Output Compare 4 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The Output configuration structure
Return values:
None

Definition at line 5045 of file stm32h7xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_TI1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  |

Configure the TI1 as Input.

Parameters:
TIMx to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
  • TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
  • TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 (on channel2 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 5353 of file stm32h7xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Extended Timer Hall Sensor functions

Functions
Extended Timer Hall Sensor functions
TIM Extended Exported Functions

TIM Hall Sensor functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.

Detailed Description

TIM Hall Sensor functions.

Timer Hall Sensor functions.

  ==============================================================================
                      ##### TIM Hall Sensor functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure TIM HAL Sensor.
    (+) De-initialize TIM HAL Sensor.
    (+) Start the Hall Sensor Interface.
    (+) Stop the Hall Sensor Interface.
    (+) Start the Hall Sensor Interface and enable interrupts.
    (+) Stop the Hall Sensor Interface and disable interrupts.
    (+) Start the Hall Sensor Interface and enable DMA transfers.
    (+) Stop the Hall Sensor Interface and disable DMA transfers.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit ( TIM_HandleTypeDef * htim )

DeInitialize the TIM Hall Sensor interface.

Parameters:
htim,: TIM Hall Sensor handle.
Return values:
HAL status

Definition at line 238 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, HAL_TIMEx_HallSensor_MspDeInit(), TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_HallSensor_InitTypeDef * | sConfig
 | ) |  |

Initializes the TIM Hall Sensor Interface and initialize the associated handle.

Parameters:
htim,: TIM Encoder Interface handle
sConfig,: TIM Hall Sensor configuration structure.
Return values:
HAL status

Definition at line 160 of file stm32h7xx_hal_tim_ex.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_HallSensor_InitTypeDef::Commutation_Delay, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, HAL_TIMEx_HallSensor_MspInit(), TIM_HallSensor_InitTypeDef::IC1Filter, TIM_HallSensor_InitTypeDef::IC1Polarity, TIM_HallSensor_InitTypeDef::IC1Prescaler, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, TIM_HandleTypeDef::Lock, TIM_OC_InitTypeDef::OCFastMode, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_ICSELECTION_TRC, TIM_OC2_SetConfig(), TIM_OCFAST_DISABLE, TIM_OCIDLESTATE_RESET, TIM_OCMODE_PWM2, TIM_OCNIDLESTATE_RESET, TIM_OCNPOLARITY_HIGH, TIM_OCPOLARITY_HIGH, TIM_SLAVEMODE_RESET, TIM_TI1_SetConfig(), TIM_TRGO_OC2REF, and TIM_TS_TI1F_ED.

void HAL_TIMEx_HallSensor_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitialize TIM Hall Sensor MSP.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 280 of file stm32h7xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_HallSensor_DeInit().

void HAL_TIMEx_HallSensor_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Hall Sensor MSP.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 265 of file stm32h7xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_HallSensor_Init().

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start ( TIM_HandleTypeDef * htim )

Starts the TIM Hall Sensor Interface.

Parameters:
htim : TIM Hall Sensor handle
Return values:
HAL status

Definition at line 295 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), and TIM_CHANNEL_1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Hall Sensor Interface in DMA mode.

Parameters:
htim : TIM Hall Sensor handle.
pData,: The destination Buffer address.
Length,: The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 387 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_DMACaptureCplt(), HAL_TIM_DMAError(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_DMA_CC1, TIM_DMA_ID_CC1, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT ( TIM_HandleTypeDef * htim )

Starts the TIM Hall Sensor Interface in interrupt mode.

Parameters:
htim : TIM Hall Sensor handle.
Return values:
HAL status

Definition at line 337 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_IT_CC1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop ( TIM_HandleTypeDef * htim )

Stops the TIM Hall sensor Interface.

Parameters:
htim : TIM Hall Sensor handle
Return values:
HAL status

Definition at line 316 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), and TIM_CHANNEL_1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA ( TIM_HandleTypeDef * htim )

Stops the TIM Hall Sensor Interface in DMA mode.

Parameters:
htim : TIM handle.
Return values:
HAL status

Definition at line 434 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_DMA_CC1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT ( TIM_HandleTypeDef * htim )

Stops the TIM Hall Sensor Interface in interrupt mode.

Parameters:
htim : TIM handle.
Return values:
HAL status

Definition at line 361 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_IT_CC1.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Extended Timer Complementary Output Compare functions

Functions
Extended Timer Complementary Output Compare functions
TIM Extended Exported Functions

TIM Complementary Output Compare functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.

Detailed Description

TIM Complementary Output Compare functions.

Timer Complementary Output Compare functions.

  ==============================================================================
              ##### TIM Complementary Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary Output Compare/PWM.
    (+) Stop the Complementary Output Compare/PWM.
    (+) Start the Complementary Output Compare/PWM and enable interrupts.
    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_OCN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation on the complementary output.

Parameters:
htim : TIM Output Compare handle
Channel : TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 490 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Output Compare signal generation in DMA mode on the complementary output.

Parameters:
htim : TIM Output Compare handle
Channel : TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
pData,: The source Buffer address.
Length,: The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 675 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_DMAError(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.

Parameters:
htim : TIM OC handle
Channel : TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 549 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, and TIM_IT_CC3.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation on the complementary output.

Parameters:
htim : TIM handle
Channel : TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 520 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in DMA mode on the complementary output.

Parameters:
htim : TIM Output Compare handle
Channel : TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 773 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_DMA_CC1, TIM_DMA_CC2, and TIM_DMA_CC3.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.

Parameters:
htim : TIM Output Compare handle.
Channel : TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 608 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, and TIM_IT_CC3.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Extended Timer Complementary PWM functions

Functions
Extended Timer Complementary PWM functions
TIM Extended Exported Functions

TIM Complementary PWM functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Start the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.

Detailed Description

TIM Complementary PWM functions.

Timer Complementary PWM functions.

  ==============================================================================
                 ##### TIM Complementary PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary PWM.
    (+) Stop the Complementary PWM.
    (+) Start the Complementary PWM and enable interrupts.
    (+) Stop the Complementary PWM and disable interrupts.
    (+) Start the Complementary PWM and enable DMA transfers.
    (+) Stop the Complementary PWM and disable DMA transfers.
    (+) Start the Complementary Input Capture measurement.
    (+) Stop the Complementary Input Capture.
    (+) Start the Complementary Input Capture and enable interrupts.
    (+) Stop the Complementary Input Capture and disable interrupts.
    (+) Start the Complementary Input Capture and enable DMA transfers.
    (+) Stop the Complementary Input Capture and disable DMA transfers.
    (+) Start the Complementary One Pulse generation.
    (+) Stop the Complementary One Pulse.
    (+) Start the Complementary One Pulse and enable interrupts.
    (+) Stop the Complementary One Pulse and disable interrupts.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation on the complementary output.

Parameters:
htim : TIM handle
Channel : TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 866 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Start the TIM PWM signal generation in DMA mode on the complementary output.

Parameters:
htim : TIM handle
Channel : TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
pData,: The source Buffer address.
Length,: The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1050 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_DMAError(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation in interrupt mode on the complementary output.

Parameters:
htim : TIM handle
Channel : TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 924 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, and TIM_IT_CC3.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation on the complementary output.

Parameters:
htim : TIM handle
Channel : TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 895 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM PWM signal generation in DMA mode on the complementary output.

Parameters:
htim : TIM handle
Channel : TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 1148 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_DMA_CC1, TIM_DMA_CC2, and TIM_DMA_CC3.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation in interrupt mode on the complementary output.

Parameters:
htim : TIM handle
Channel : TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 983 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, and TIM_IT_CC3.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Extended Timer Complementary One Pulse functions

Functions
Extended Timer Complementary One Pulse functions
TIM Extended Exported Functions

TIM Complementary One Pulse functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complemetary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Detailed Description

TIM Complementary One Pulse functions.

Timer Complementary One Pulse functions.

  ==============================================================================
                ##### TIM Complementary One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary One Pulse generation.
    (+) Stop the Complementary One Pulse.
    (+) Start the Complementary One Pulse and enable interrupts.
    (+) Stop the Complementary One Pulse and disable interrupts.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation on the complemetary output.

Parameters:
htim : TIM One Pulse handle
OutputChannel : TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1228 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Parameters:
htim : TIM One Pulse handle
OutputChannel : TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1282 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation on the complementary output.

Parameters:
htim : TIM One Pulse handle
OutputChannel : TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1253 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Parameters:
htim : TIM One Pulse handle
OutputChannel : TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1313 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_IT_CC1, and TIM_IT_CC2.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
TIM Extended Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
Configures the break input source.
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIMx Remapping input capabilities.
HAL_StatusTypeDef | HAL_TIMEx_TISelection (TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
Configures the TIMx input Selection capabilities.
HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t Channels)
Group channel 5 and channel 1, 2 or 3.

Detailed Description

Peripheral Control functions.

  ==============================================================================
                    ##### Peripheral Control functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
      (+) Configure the commutation event in case of use of the Hall sensor interface.
      (+) Configure Output channels for OC and PWM mode.
      (+) Configure Complementary channels, break features and dead time.
      (+) Configure Master synchronization.
      (+) Configure timer remapping capabilities.
      (+) Enable or disable channel grouping

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_BreakDeadTimeConfigTypeDef * | sBreakDeadTimeConfig
 | ) |  |

Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).

Parameters:
htim,: TIM handle
sBreakDeadTimeConfig,: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that contains the BDTR Register configuration information for the TIM peripheral.
Return values:
HAL status

Definition at line 1588 of file stm32h7xx_hal_tim_ex.c.

References assert_param, TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput, BDTR_BK2F_SHIFT, BDTR_BKF_SHIFT, TIM_BreakDeadTimeConfigTypeDef::Break2Filter, TIM_BreakDeadTimeConfigTypeDef::Break2Polarity, TIM_BreakDeadTimeConfigTypeDef::Break2State, TIM_BreakDeadTimeConfigTypeDef::BreakFilter, TIM_BreakDeadTimeConfigTypeDef::BreakPolarity, TIM_BreakDeadTimeConfigTypeDef::BreakState, TIM_BreakDeadTimeConfigTypeDef::DeadTime, TIM_HandleTypeDef::Instance, IS_TIM_AUTOMATIC_OUTPUT_STATE, IS_TIM_BREAK2_POLARITY, IS_TIM_BREAK2_STATE, IS_TIM_BREAK_FILTER, IS_TIM_BREAK_POLARITY, IS_TIM_BREAK_STATE, IS_TIM_DEADTIME, IS_TIM_LOCK_LEVEL, IS_TIM_OSSI_STATE, IS_TIM_OSSR_STATE, TIM_BreakDeadTimeConfigTypeDef::LockLevel, TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode, and TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode.

HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BreakInput,
 |  | TIMEx_BreakInputConfigTypeDef * | sBreakInputConfig
 | ) |  |

Configures the break input source.

Parameters:
htim,: TIM handle.
BreakInput,: Break input to configure. This parameter can be one of the following values:
  • TIM_BREAKINPUT_BRK: Timer break input
  • TIM_BREAKINPUT_BRK2: Timer break 2 input
sBreakInputConfig,: Break input source configuration
Return values:
HAL status

Definition at line 1650 of file stm32h7xx_hal_tim_ex.c.

References assert_param, TIMEx_BreakInputConfigTypeDef::Enable, TIM_HandleTypeDef::Instance, IS_TIM_BREAKINPUT, IS_TIM_BREAKINPUTSOURCE, IS_TIM_BREAKINPUTSOURCE_POLARITY, IS_TIM_BREAKINPUTSOURCE_STATE, TIMEx_BreakInputConfigTypeDef::Polarity, TIMEx_BreakInputConfigTypeDef::Source, TIM_BREAKINPUT_BRK, TIM_BREAKINPUT_BRK2, TIM_BREAKINPUTSOURCE_BKIN, TIM_BREAKINPUTSOURCE_COMP1, TIM_BREAKINPUTSOURCE_COMP2, and TIM_BREAKINPUTSOURCE_DFSDM1.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence.

Note:
: this function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
Parameters:
htim,: TIM handle
InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_NONE: No trigger is needed
CommutationSource : the Commutation Event source. This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1381 of file stm32h7xx_hal_tim_ex.c.

References assert_param, TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, and TIM_TS_ITR3.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence with DMA.

Note:
: this function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
: The user should configure the DMA in his own software, in This function only the COMDE bit is set.
Parameters:
htim,: TIM handle
InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_NONE: No trigger is needed
CommutationSource : the Commutation Event source. This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1483 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE_DMA, assert_param, HAL_TIM_DMAError(), HAL_TIMEx_DMACommutationCplt(), TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_DMA_COM, TIM_DMA_ID_COMMUTATION, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, TIM_TS_ITR3, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence with interrupt.

Note:
: this function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
Parameters:
htim,: TIM handle
InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_NONE: No trigger is needed
CommutationSource : the Commutation Event source. This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1430 of file stm32h7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_IT_COM, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, and TIM_TS_ITR3.

HAL_StatusTypeDef HAL_TIMEx_GroupChannel5 | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channels
 | ) |  |

Group channel 5 and channel 1, 2 or 3.

Parameters:
htim,: TIM handle.
Channels,: specifies the reference signal(s) the OC5REF is combined with. This parameter can be any combination of the following values: TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
Return values:
HAL status

Definition at line 1930 of file stm32h7xx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_GROUPCH5, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_MasterConfigTypeDef * | sMasterConfig
 | ) |  |

Configures the TIM in master mode.

Parameters:
htim,: TIM handle.
sMasterConfig,: pointer to a TIM_MasterConfigTypeDef structure that contains the selected trigger output (TRGO) and the Master/Slave mode.
Return values:
HAL status

Definition at line 1527 of file stm32h7xx_hal_tim_ex.c.

References assert_param, TIM_HandleTypeDef::Instance, IS_TIM_MSM_STATE, IS_TIM_TRGO2_SOURCE, IS_TIM_TRGO_SOURCE, TIM_MasterConfigTypeDef::MasterOutputTrigger, TIM_MasterConfigTypeDef::MasterOutputTrigger2, and TIM_MasterConfigTypeDef::MasterSlaveMode.

HAL_StatusTypeDef HAL_TIMEx_RemapConfig | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Remap
 | ) |  |

Configures the TIMx Remapping input capabilities.

Parameters:
htim,: TIM handle.
Remap,: specifies the TIM remapping source. For TIM1, the parameter is one of the following values:
  • TIM_TIM1_ETR_GPIO: TIM1_ETR is connected to GPIO
  • TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output
  • TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output
  • TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
  • TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
  • TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
  • TIM_TIM1_ETR_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1
  • TIM_TIM1_ETR_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2
  • TIM_TIM1_ETR_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3:
For TIM2, the parameter is one of the following values:
  • TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO
  • TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output
  • TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output
  • TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE
  • TIM_TIM2_ETR_SAI1_FSA: TIM2_ETR is connected to SAI1 FS_A
  • TIM_TIM2_ETR_SAI1_FSB: TIM2_ETR is connected to SAI1 FS_B
For TIM3, the parameter is one of the following values:
  • TIM_TIM3_ETR_GPIO: TIM3_ETR is connected to GPIO
  • TIM_TIM3_ETR_COMP1: TIM3_ETR is connected to COMP1 output
For TIM5, the parameter is one of the following values:
  • TIM_TIM5_ETR_GPIO: TIM5_ETR is connected to GPIO
  • TIM_TIM5_ETR_SAI2_FSA: TIM5_ETR is connected to SAI2 FS_A
  • TIM_TIM5_ETR_SAI2_FSB: TIM5_ETR is connected to SAI2 FS_B
For TIM8, the parameter is one of the following values:
  • TIM_TIM8_ETR_GPIO: TIM8_ETR is connected to GPIO
  • TIM_TIM8_ETR_COMP1: TIM8_ETR is connected to COMP1 output
  • TIM_TIM8_ETR_COMP2: TIM8_ETR is connected to COMP2 output
  • TIM_TIM8_ETR_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
  • TIM_TIM8_ETR_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
  • TIM_TIM8_ETR_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
  • TIM_TIM8_ETR_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
  • TIM_TIM8_ETR_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
  • TIM_TIM8_ETR_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
Return values:
HAL status

Definition at line 1808 of file stm32h7xx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_ETRREMAP, TIM_HandleTypeDef::State, and TIMx_ETRSEL_MASK.

HAL_StatusTypeDef HAL_TIMEx_TISelection | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | TISelection,
 |  | uint32_t | Channel
 | ) |  |

Configures the TIMx input Selection capabilities.

Parameters:
htim,: TIM handle.
TISelection : parameter of the TIM_TISelectionStruct structure.
Channel,: specifies the channels that will be selected for configuration:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
  • TIM_CHANNEL_4: TIM Channel 4
TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows: For TIM1, the parameter is one of the following values:
  • TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
  • TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
For TIM2, the parameter is one of the following values:
  • TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
  • TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
  • TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output
  • TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
For TIM3, the parameter is one of the following values:
  • TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO
  • TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output
  • TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output
  • TIM_TIM3_TI1_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
For TIM5, the parameter is one of the following values:
  • TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to GPIO
  • TIM_TIM5_TI1_CAN_TMP: TIM5 TI1 is connected to CAN TMP
  • TIM_TIM5_TI1_CAN_RTP: TIM5 TI1 is connected to CAN RTP
For TIM8, the parameter is one of the following values:
  • TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
  • TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output
For TIM15, the parameter is one of the following values:
  • TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
  • TIM_TIM15_TI1_TIM2: TIM15 TI1 is connected to TIM2 CH1
  • TIM_TIM15_TI1_TIM3: TIM15 TI1 is connected to TIM3 CH1
  • TIM_TIM15_TI1_TIM4: TIM15 TI1 is connected to TIM4 CH1
  • TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE
  • TIM_TIM15_TI1_CSI: TIM15 TI1 is connected to CSI
  • TIM_TIM15_TI1_MCO2: TIM15 TI1 is connected to MCO2
  • TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO
  • TIM_TIM15_TI2_TIM2: TIM15 TI2 is connected to TIM2 CH2
  • TIM_TIM15_TI2_TIM3: TIM15 TI2 is connected to TIM3 CH2
  • TIM_TIM15_TI2_TIM4: TIM15 TI2 is connected to TIM4 CH2
For TIM16, the parameter can have the following values:
  • TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
  • TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
  • TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
  • TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt
For TIM17, the parameter can have the following values:
  • TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
  • TIM_TIM17_TI1_SPDIFFS: TIM17 TI1 is connected to SPDIF FS
  • TIM_TIM17_TI1_HSE_1MHZ: TIM17 TI1 is connected to HSE 1MHz
  • TIM_TIM17_TI1_MCO1: TIM17 TI1 is connected to MCO1
Return values:
HAL status

Definition at line 1895 of file stm32h7xx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_TISEL, TIM_HandleTypeDef::State, and TIMx_TIxSEL_MASK.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Extended Callbacks functions

Functions
Extended Callbacks functions
TIM Extended Exported Functions

Extended Callbacks functions. More...

Functions

__weak void | HAL_TIMEx_CommutationCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non blocking mode.

Detailed Description

Extended Callbacks functions.

  ==============================================================================
                    ##### Extended Callbacks functions #####
  ==============================================================================
  [..]
    This section provides Extended TIM callback functions:
    (+) TIM Commutation callback
    (+) TIM Break callback

Function Documentation

void HAL_TIMEx_BreakCallback ( TIM_HandleTypeDef * htim )

Hall Break detection callback in non blocking mode.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 1995 of file stm32h7xx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler().

void HAL_TIMEx_CommutationCallback ( TIM_HandleTypeDef * htim )

Hall commutation changed callback in non blocking mode.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 1980 of file stm32h7xx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler(), and HAL_TIMEx_DMACommutationCplt().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Extended Peripheral State functions

Functions
Extended Peripheral State functions
TIM Extended Exported Functions

Extended Peripheral State functions. More...

Functions

HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface state.

Detailed Description

Extended Peripheral State functions.

  ==============================================================================
                ##### Extended Peripheral State functions #####
  ==============================================================================
  [..]
    This subsection permit to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Hall Sensor interface state.

Parameters:
htim,: TIM Hall Sensor handle
Return values:
HAL state

Definition at line 2029 of file stm32h7xx_hal_tim_ex.c.

References TIM_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Extended Exported Functions

Modules | Functions
TIM Extended Exported Functions
TIMEx | TIM Extended Exported Macros

Modules

Extended Timer Hall Sensor functions

TIM Hall Sensor functions.

Extended Timer Complementary Output Compare functions

TIM Complementary Output Compare functions.

Extended Timer Complementary PWM functions

TIM Complementary PWM functions.

Extended Timer Complementary One Pulse functions

TIM Complementary One Pulse functions.

Extended Peripheral Control functions

Peripheral Control functions.

Extended Callbacks functions

Extended Callbacks functions.

Extended Peripheral State functions

Extended Peripheral State functions.

Functions

void | HAL_TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.
static void | TIM_CCxNChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
Enables or disables the TIM Capture Compare Channel xN.

Function Documentation

void HAL_TIMEx_DMACommutationCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Commutation callback.

Parameters:
hdma : pointer to DMA handle.
Return values:
None

Definition at line 2043 of file stm32h7xx_hal_tim_ex.c.

References HAL_TIM_STATE_READY, HAL_TIMEx_CommutationCallback(), and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIMEx_ConfigCommutationEvent_DMA().

static void TIM_CCxNChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelNState
 | ) |  | [static]

Enables or disables the TIM Capture Compare Channel xN.

Parameters:
TIMx to select the TIM peripheral
Channel,: specifies the TIM Channel This parameter can be one of the following values:
  • TIM_Channel_1: TIM Channel 1
  • TIM_Channel_2: TIM Channel 2
  • TIM_Channel_3: TIM Channel 3
ChannelNState,: specifies the TIM Channel CCxNE bit new state. This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
Return values:
None

Definition at line 2064 of file stm32h7xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM_HallSensor_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_HallSensor_InitTypeDef Struct Reference
TIM Extended Exported Types

TIM Hall sensor Configuration Structure definition. More...

#include <stm32h7xx_hal_tim_ex.h>

Data Fields

uint32_t | IC1Polarity
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | Commutation_Delay

Detailed Description

TIM Hall sensor Configuration Structure definition.

Definition at line 66 of file stm32h7xx_hal_tim_ex.h.

Field Documentation

uint32_t TIM_HallSensor_InitTypeDef::Commutation_Delay

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 77 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 75 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 69 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 72 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim_ex.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIMEx_BreakInputConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIMEx_BreakInputConfigTypeDef Struct Reference
TIM Extended Exported Types

TIM Break/Break2 input configuration. More...

#include <stm32h7xx_hal_tim_ex.h>

Data Fields

uint32_t | Source
uint32_t | Enable
uint32_t | Polarity

Detailed Description

TIM Break/Break2 input configuration.

Definition at line 84 of file stm32h7xx_hal_tim_ex.h.

Field Documentation

uint32_t TIMEx_BreakInputConfigTypeDef::Enable

Specifies whether or not the break input source is enabled. This parameter can be a value of TIM Extended Break input source enabling

Definition at line 87 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

uint32_t TIMEx_BreakInputConfigTypeDef::Polarity

Specifies the break input source polarity. This parameter can be a value of TIM Extended Break input polarity Not relevant when analog watchdog output of the DFSDM1 used as break input source

Definition at line 89 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

uint32_t TIMEx_BreakInputConfigTypeDef::Source

Specifies the source of the timer break input. This parameter can be a value of TIM Extended Break input source

Definition at line 85 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_tim_ex.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Extended Channel

Defines
TIM Extended Channel
TIM Extended Exported Constants

Defines

#define | TIM_CHANNEL_1 ((uint32_t)0x0000U)
#define | TIM_CHANNEL_2 ((uint32_t)0x0004U)
#define | TIM_CHANNEL_3 ((uint32_t)0x0008U)
#define | TIM_CHANNEL_4 ((uint32_t)0x000CU)
#define | TIM_CHANNEL_5 ((uint32_t)0x0010U)
#define | TIM_CHANNEL_6 ((uint32_t)0x0014U)
#define | TIM_CHANNEL_ALL ((uint32_t)0x003CU)

Define Documentation

#define TIM_CHANNEL_1 ((uint32_t)0x0000U)

TIM Channel 1

Definition at line 106 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), and TIM_OC1_SetConfig().

#define TIM_CHANNEL_2 ((uint32_t)0x0004U)

TIM Channel 2

Definition at line 107 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), and TIM_OC2_SetConfig().

#define TIM_CHANNEL_3 ((uint32_t)0x0008U)

TIM Channel 3

Definition at line 108 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), and TIM_OC3_SetConfig().

#define TIM_CHANNEL_4 ((uint32_t)0x000CU)

TIM Channel 4

Definition at line 109 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), and HAL_TIM_ReadCapturedValue().

#define TIM_CHANNEL_5 ((uint32_t)0x0010U)

TIM Channel 5

Definition at line 110 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define TIM_CHANNEL_6 ((uint32_t)0x0014U)

TIM Channel 6

Definition at line 111 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define TIM_CHANNEL_ALL ((uint32_t)0x003CU)

TIM all Channels

Definition at line 112 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIM_Encoder_Start_DMA().

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STM32H753xx HAL User Manual: TIM Output Compare and PWM Modes

Defines
TIM Output Compare and PWM Modes
TIM Extended Exported Constants

Defines

#define | TIM_OCMODE_TIMING ((uint32_t)0x0000U)
#define | TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
#define | TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)

Define Documentation

#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)

TIM Output Active mode

Definition at line 122 of file stm32h7xx_hal_tim_ex.h.

#define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)

TIM Asymetruc PWM mode 1

Definition at line 134 of file stm32h7xx_hal_tim_ex.h.

#define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)

TIM Asymetruc PWM mode 2

Definition at line 135 of file stm32h7xx_hal_tim_ex.h.

#define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)

TIM Combined PWM mode 1

Definition at line 132 of file stm32h7xx_hal_tim_ex.h.

#define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)

TIM Combined PWM mode 2

Definition at line 133 of file stm32h7xx_hal_tim_ex.h.

#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)

TIM Forced Active mode

Definition at line 127 of file stm32h7xx_hal_tim_ex.h.

#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)

TIM Forced Inactive mode

Definition at line 128 of file stm32h7xx_hal_tim_ex.h.

#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)

TIM Output Inactive mode

Definition at line 123 of file stm32h7xx_hal_tim_ex.h.

#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)

TIM PWM mode 1

Definition at line 125 of file stm32h7xx_hal_tim_ex.h.

#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

TIM PWM mode 2

Definition at line 126 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)

TIM Rettrigerrable OPM mode 1

Definition at line 130 of file stm32h7xx_hal_tim_ex.h.

#define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)

TIM Rettrigerrable OPM mode 2

Definition at line 131 of file stm32h7xx_hal_tim_ex.h.

#define TIM_OCMODE_TIMING ((uint32_t)0x0000U)

TIM Output timing mode

Definition at line 121 of file stm32h7xx_hal_tim_ex.h.

#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

TIM Output Toggle mode

Definition at line 124 of file stm32h7xx_hal_tim_ex.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Extended Clear Input Source

Defines
TIM Extended Clear Input Source
TIM Extended Exported Constants

Defines

#define | TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U)
#define | TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002U)
#define | TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U)

Define Documentation

#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U)

TIM Clear input source connected to ETR

Definition at line 143 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U)

TIM Clear input source None

Definition at line 145 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002U)

TIM Clear input source connected to OCREFClear

Definition at line 144 of file stm32h7xx_hal_tim_ex.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIMEX Break input 2 Enable

Defines
TIMEX Break input 2 Enable
TIM Extended Exported Constants

Defines

#define | TIM_BREAK2_DISABLE ((uint32_t)0x00000000U)
#define | TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)

Define Documentation

#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000U)

TIM Break2 disabled

Definition at line 154 of file stm32h7xx_hal_tim_ex.h.

#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)

TIM Break2 enabled

Definition at line 155 of file stm32h7xx_hal_tim_ex.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Extended Break Input 2 Polarity

Defines
TIM Extended Break Input 2 Polarity
TIM Extended Exported Constants

Defines

#define | TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000U)
#define | TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)

Define Documentation

#define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)

TIM Break2 polarity high

Definition at line 164 of file stm32h7xx_hal_tim_ex.h.

#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000U)

TIM Break2 polarity low

Definition at line 163 of file stm32h7xx_hal_tim_ex.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Trigger Selection

Defines
TIM Trigger Selection
TIM Extended Exported Constants

Defines

#define | TIM_TS_ITR4 ((uint32_t)0x0100000)
#define | TIM_TS_ITR5 ((uint32_t)0x0100010)
#define | TIM_TS_ITR6 ((uint32_t)0x0100020)
#define | TIM_TS_ITR7 ((uint32_t)0x0100030)
#define | TIM_TS_ITR8 ((uint32_t)0x0100040)

Define Documentation

#define TIM_TS_ITR4 ((uint32_t)0x0100000)

TIM Internal trigger 4

Definition at line 173 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TS_ITR5 ((uint32_t)0x0100010)

TIM Internal trigger 5

Definition at line 174 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TS_ITR6 ((uint32_t)0x0100020)

TIM Internal trigger 6

Definition at line 175 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TS_ITR7 ((uint32_t)0x0100030)

TIM Internal trigger 7

Definition at line 176 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TS_ITR8 ((uint32_t)0x0100040)

TIM Internal trigger 8

Definition at line 177 of file stm32h7xx_hal_tim_ex.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM DMA Base Address

Defines
TIM DMA Base Address
TIM Extended Exported Constants

Defines

#define | TIM_DMABASE_CR1 (0x00000000U)
#define | TIM_DMABASE_CR2 (0x00000001U)
#define | TIM_DMABASE_SMCR (0x00000002U)
#define | TIM_DMABASE_DIER (0x00000003U)
#define | TIM_DMABASE_SR (0x00000004U)
#define | TIM_DMABASE_EGR (0x00000005U)
#define | TIM_DMABASE_CCMR1 (0x00000006U)
#define | TIM_DMABASE_CCMR2 (0x00000007U)
#define | TIM_DMABASE_CCER (0x00000008U)
#define | TIM_DMABASE_CNT (0x00000009U)
#define | TIM_DMABASE_PSC (0x0000000AU)
#define | TIM_DMABASE_ARR (0x0000000BU)
#define | TIM_DMABASE_RCR (0x0000000CU)
#define | TIM_DMABASE_CCR1 (0x0000000DU)
#define | TIM_DMABASE_CCR2 (0x0000000EU)
#define | TIM_DMABASE_CCR3 (0x0000000FU)
#define | TIM_DMABASE_CCR4 (0x00000010U)
#define | TIM_DMABASE_BDTR (0x00000011U)
#define | TIM_DMABASE_DCR (0x00000012U)
#define | TIM_DMABASE_DMAR (0x00000013U)
#define | TIM_DMABASE_AF1 (0x00000014U)
#define | TIM_DMABASE_CCMR3 (0x00000015U)
#define | TIM_DMABASE_CCR5 (0x00000016U)
#define | TIM_DMABASE_CCR6 (0x00000017U)
#define | TIM_DMABASE_AF2 (0x00000018U)
#define | TIM_DMABASE_AF3 (0x00000019U)
#define | TIM_DMABASE_TISEL (0x0000001AU)

Define Documentation

#define TIM_DMABASE_AF1 (0x00000014U)

TIM DMA Base Address is AF1

Definition at line 225 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_AF2 (0x00000018U)

TIM DMA Base Address is AF2

Definition at line 229 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_AF3 (0x00000019U)

TIM DMA Base Address is AF3

Definition at line 230 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_ARR (0x0000000BU)

TIM DMA Base Address is ARR

Definition at line 216 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_BDTR (0x00000011U)

TIM DMA Base Address is BDTR

Definition at line 222 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_CCER (0x00000008U)

TIM DMA Base Address is CCER

Definition at line 213 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_CCMR1 (0x00000006U)

TIM DMA Base Address is CCMR1

Definition at line 211 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_CCMR2 (0x00000007U)

TIM DMA Base Address is CCMR2

Definition at line 212 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_CCMR3 (0x00000015U)

TIM DMA Base Address is CCMR3

Definition at line 226 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_CCR1 (0x0000000DU)

TIM DMA Base Address is CCR1

Definition at line 218 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_CCR2 (0x0000000EU)

TIM DMA Base Address is CCR2

Definition at line 219 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_CCR3 (0x0000000FU)

TIM DMA Base Address is CCR3

Definition at line 220 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_CCR4 (0x00000010U)

TIM DMA Base Address is CCR3

Definition at line 221 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_CCR5 (0x00000016U)

TIM DMA Base Address is CCR5

Definition at line 227 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_CCR6 (0x00000017U)

TIM DMA Base Address is CCR6

Definition at line 228 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_CNT (0x00000009U)

TIM DMA Base Address is CNT

Definition at line 214 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_CR1 (0x00000000U)

TIM DMA Base Address is CR1

Definition at line 205 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_CR2 (0x00000001U)

TIM DMA Base Address is CR2

Definition at line 206 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_DCR (0x00000012U)

TIM DMA Base Address is DCR

Definition at line 223 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_DIER (0x00000003U)

TIM DMA Base Address is DIER

Definition at line 208 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_DMAR (0x00000013U)

TIM DMA Base Address is DMAR

Definition at line 224 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_EGR (0x00000005U)

TIM DMA Base Address is EGR

Definition at line 210 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_PSC (0x0000000AU)

TIM DMA Base Address is PSC

Definition at line 215 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_RCR (0x0000000CU)

TIM DMA Base Address is RCR

Definition at line 217 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_SMCR (0x00000002U)

TIM DMA Base Address is SMCR

Definition at line 207 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_SR (0x00000004U)

TIM DMA Base Address is SR

Definition at line 209 of file stm32h7xx_hal_tim_ex.h.

#define TIM_DMABASE_TISEL (0x0000001AU)

TIM DMA Base Address is TISEL

Definition at line 231 of file stm32h7xx_hal_tim_ex.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Extended Remapping

Defines
TIM Extended Remapping
TIM Extended Exported Constants

Defines

#define | TIM_TIM1_ETR_GPIO (0x00000000) /* !< TIM1_ETR is connected to GPIO */
#define | TIM_TIM1_ETR_ADC1_AWD1 (0x0000C000) /* !< TIM1_ETR is connected to ADC1 AWD1 */
#define | TIM_TIM1_ETR_ADC1_AWD2 (0x00010000) /* !< TIM1_ETR is connected to ADC1 AWD2 */
#define | TIM_TIM1_ETR_ADC1_AWD3 (0x00014000) /* !< TIM1_ETR is connected to ADC1 AWD3 */
#define | TIM_TIM1_ETR_ADC3_AWD1 (0x00018000) /* !< TIM1_ETR is connected to ADC3 AWD1 */
#define | TIM_TIM1_ETR_ADC3_AWD2 (0x0001C000) /* !< TIM1_ETR is connected to ADC3 AWD2 */
#define | TIM_TIM1_ETR_ADC3_AWD3 (0x00020000) /* !< TIM1_ETR is connected to ADC3 AWD3 */
#define | TIM_TIM1_ETR_COMP1_OUT (0x00004000) /* !< TIM1_ETR is connected to COMP1 OUT */
#define | TIM_TIM1_ETR_COMP2_OUT (0x00008000) /* !< TIM1_ETR is connected to COMP2 OUT */
#define | TIM_TIM8_ETR_GPIO (0x00000000) /* !< TIM8_ETR is connected to GPIO */
#define | TIM_TIM8_ETR_ADC2_AWD1 (0x0000C000) /* !< TIM8_ETR is connected to ADC2 AWD1 */
#define | TIM_TIM8_ETR_ADC2_AWD2 (0x00010000) /* !< TIM8_ETR is connected to ADC2 AWD2 */
#define | TIM_TIM8_ETR_ADC2_AWD3 (0x00014000) /* !< TIM8_ETR is connected to ADC2 AWD3 */
#define | TIM_TIM8_ETR_ADC3_AWD1 (0x00018000) /* !< TIM8_ETR is connected to ADC3 AWD1 */
#define | TIM_TIM8_ETR_ADC3_AWD2 (0x0001C000) /* !< TIM8_ETR is connected to ADC3 AWD2 */
#define | TIM_TIM8_ETR_ADC3_AWD3 (0x00020000) /* !< TIM8_ETR is connected to ADC3 AWD3 */
#define | TIM_TIM8_ETR_COMP1_OUT (0x00004000) /* !< TIM8_ETR is connected to COMP1 OUT */
#define | TIM_TIM8_ETR_COMP2_OUT (0x00008000) /* !< TIM8_ETR is connected to COMP2 OUT */
#define | TIM_TIM2_ETR_GPIO (0x00000000) /* !< TIM2_ETR is connected to GPIO */
#define | TIM_TIM2_ETR_COMP1_OUT (0x0000C000) /* !< TIM2_ETR is connected to COMP1 OUT */
#define | TIM_TIM2_ETR_COMP2_OUT (0x00010000) /* !< TIM2_ETR is connected to COMP2 OUT */
#define | TIM_TIM2_ETR_RCC_LSE (0x00014000) /* !< TIM2_ETR is connected to RCC LSE */
#define | TIM_TIM2_ETR_SAI1_FSA (0x00018000) /* !< TIM2_ETR is connected to SAI1 FS_A */
#define | TIM_TIM2_ETR_SAI1_FSB (0x0001C000) /* !< TIM2_ETR is connected to SAI1 FS_B */
#define | TIM_TIM3_ETR_GPIO (0x00000000) /* !< TIM3_ETR is connected to GPIO */
#define | TIM_TIM3_ETR_COMP1_OUT (0x00000000) /* !< TIM3_ETR is connected to COMP1 OUT */
#define | TIM_TIM5_ETR_GPIO (0x00000000) /* !< TIM5_ETR is connected to GPIO */
#define | TIM_TIM5_ETR_SAI2_FSA (0x00000000) /* !< TIM5_ETR is connected to SAI2 FS_A */
#define | TIM_TIM5_ETR_SAI2_FSB (0x00000000) /* !< TIM5_ETR is connected to SAI2 FS_B */
#define | TIM_TIM1_BKR_GPIO (0x00000000) /* !< TIM1_BKR is connected to GPIO */
#define | TIM_TIM1_BKR_COMP1_OUT (0x00000002) /* !< TIM1_BKR is connected to COMP1 OUT */
#define | TIM_TIM1_BKR_COMP2_OUT (0x00000004) /* !< TIM1_BKR is connected to COMP2 OUT */
#define | TIM_TIM1_BKR_DFSDM_BRK0 (0x00000000) /* !< TIM1_BKR is connected to DFSDM BRK0 */
#define | TIM_TIM8_BKR_GPIO (0x00000000) /* !< TIM8_BKR is connected to GPIO */
#define | TIM_TIM8_BKR_COMP1_OUT (0x00000002) /* !< TIM8_BKR is connected to COMP1 OUT */
#define | TIM_TIM8_BKR_COMP2_OUT (0x00000004) /* !< TIM8_BKR is connected to COMP2 OUT */
#define | TIM_TIM8_BKR_DFSDM_BRK2 (0x00000000) /* !< TIM8_BKR is connected to DFSDM BRK2 */
#define | TIM_TIM15_BKR_GPIO (0x00000000) /* !< TIM15_BKR is connected to GPIO */
#define | TIM_TIM15_BKR_COMP1_OUT (0x00000002) /* !< TIM15_BKR is connected to COMP1 OUT */
#define | TIM_TIM15_BKR_COMP2_OUT (0x00000004) /* !< TIM15_BKR is connected to COMP2 OUT */
#define | TIM_TIM15_BKR_DFSDM_BRK0 (0x00000000) /* !< TIM15_BKR is connected to DFSDM BRK0 */
#define | TIM_TIM16_BKR_GPIO (0x00000000) /* !< TIM16_BKR is connected to GPIO */
#define | TIM_TIM16_BKR_COMP1_OUT (0x00000002) /* !< TIM16_BKR is connected to COMP1 OUT */
#define | TIM_TIM16_BKR_COMP2_OUT (0x00000004) /* !< TIM16_BKR is connected to COMP2 OUT */
#define | TIM_TIM16_BKR_DFSDM_BRK1 (0x00000000) /* !< TIM16_BKR is connected to DFSDM BRK1 */
#define | TIM_TIM17_BKR_GPIO (0x00000000) /* !< TIM17_BKR is connected to GPIO */
#define | TIM_TIM17_BKR_COMP1_OUT (0x00000002) /* !< TIM17_BKR is connected to COMP1 OUT */
#define | TIM_TIM17_BKR_COMP2_OUT (0x00000004) /* !< TIM17_BKR is connected to COMP2 OUT */
#define | TIM_TIM17_BKR_DFSDM_BRK2 (0x00000000) /* !< TIM17_BKR is connected to DFSDM BRK2 */
#define | TIM_TIM1_BKR2_GPIO (0x00000000) /* !< TIM1_BKR2 is connected to GPIO */
#define | TIM_TIM1_BKR2_COMP1_OUT (0x00000002) /* !< TIM1_BKR2 is connected to COMP1 OUT */
#define | TIM_TIM1_BKR2_COMP2_OUT (0x00000004) /* !< TIM1_BKR2 is connected to COMP2 OUT */
#define | TIM_TIM1_BKR2_DFSDM_BRK1 (0x00000000) /* !< TIM1_BKR2 is connected to DFSDM BRK0 */
#define | TIM_TIM8_BKR2_GPIO (0x00000000) /* !< TIM8_BKR2 is connected to GPIO */
#define | TIM_TIM8_BKR2_COMP1_OUT (0x00000002) /* !< TIM8_BKR2 is connected to COMP1 OUT */
#define | TIM_TIM8_BKR2_COMP2_OUT (0x00000004) /* !< TIM8_BKR2 is connected to COMP2 OUT */
#define | TIM_TIM8_BKR2_DFSDM_BRK3 (0x00000000) /* !< TIM8_BKR2 is connected to DFSDM BRK3 */
#define | TIM_TIM1_TI1_GPIO (0x00000000) /* !< TIM1_TI1 is connected to GPIO */
#define | TIM_TIM1_TI1_COMP1_OUT (0x00000001) /* !< TIM1_TI1 is connected to COMP1 OUT */
#define | TIM_TIM8_TI1_GPIO (0x00000000) /* !< TIM8_TI1 is connected to GPIO */
#define | TIM_TIM8_TI1_COMP2_OUT (0x00000001) /* !< TIM8_TI1 is connected to COMP2 OUT */
#define | TIM_TIM2_TI4_GPIO (0x00000000) /* !< TIM2_TI4 is connected to GPIO */
#define | TIM_TIM2_TI4_COMP1_OUT (0x01000000) /* !< TIM2_TI4 is connected to COMP1 OUT */
#define | TIM_TIM2_TI4_COMP2_OUT (0x02000000) /* !< TIM2_TI4 is connected to COMP2 OUT */
#define | TIM_TIM2_TI4_COMP1COMP2_OUT (0x03000000) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */
#define | TIM_TIM3_TI1_GPIO (0x00000000) /* !< TIM3_TI1 is connected to GPIO */
#define | TIM_TIM3_TI1_COMP1_OUT (0x00000001) /* !< TIM3_TI1 is connected to COMP1 OUT */
#define | TIM_TIM3_TI1_COMP2_OUT (0x00000002) /* !< TIM3_TI1 is connected to COMP2 OUT */
#define | TIM_TIM3_TI1_COMP1COMP2_OUT (0x00000003) /* !< TIM3_TI1 is connected to COMP2 OUT OR COMP2 OUT */
#define | TIM_TIM5_TI1_GPIO (0x00000000) /* !< TIM5_TI1 is connected to GPIO */
#define | TIM_TIM5_TI1_CAN_TMP (0x00000001) /* !< TIM5_TI1 is connected to CAN TMP */
#define | TIM_TIM5_TI1_CAN_RTP (0x00000002) /* !< TIM5_TI1 is connected to CAN RTP */
#define | TIM_TIM15_TI1_GPIO (0x00000000) /* !< TIM15_TI1 is connected to GPIO */
#define | TIM_TIM15_TI1_TIM2_CH1 (0x00000001) /* !< TIM15_TI1 is connected to TIM2 CH1 */
#define | TIM_TIM15_TI1_TIM3_CH1 (0x00000002) /* !< TIM15_TI1 is connected to TIM3 CH1 */
#define | TIM_TIM15_TI1_TIM4_CH1 (0x00000003) /* !< TIM15_TI1 is connected to TIM4 CH1 */
#define | TIM_TIM15_TI1_RCC_LSE (0x00000004) /* !< TIM15_TI1 is connected to RCC LSE */
#define | TIM_TIM15_TI1_RCC_CSI (0x00000005) /* !< TIM15_TI1 is connected to RCC CSI */
#define | TIM_TIM15_TI1_RCC_MCO2 (0x00000006) /* !< TIM15_TI1 is connected to RCC MCO2 */
#define | TIM_TIM15_TI2_GPIO (0x00000000) /* !< TIM15_TI2 is connected to GPIO */
#define | TIM_TIM15_TI2_TIM2_CH2 (0x00000100) /* !< TIM15_TI2 is connected to TIM2 CH2 */
#define | TIM_TIM15_TI2_TIM3_CH2 (0x00000200) /* !< TIM15_TI2 is connected to TIM3 CH2 */
#define | TIM_TIM15_TI2_TIM4_CH2 (0x00000300) /* !< TIM15_TI2 is connected to TIM4 CH2 */
#define | TIM_TIM16_TI1_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */
#define | TIM_TIM16_TI1_RCC_LSI (0x00000001) /* !< TIM16 TI1 is connected to RCC LSI */
#define | TIM_TIM16_TI1_RCC_LSE (0x00000002) /* !< TIM16 TI1 is connected to RCC LSE */
#define | TIM_TIM16_TI1_WKUP_IT (0x00000003) /* !< TIM16 TI1 is connected to WKUP_IT */
#define | TIM_TIM17_TI1_GPIO (0x00000000) /* !< TIM17 TI1 is connected to GPIO */
#define | TIM_TIM17_TI1_SPDIF_FS (0x00000001) /* !< TIM17 TI1 is connected to RCC LSI */
#define | TIM_TIM17_TI1_RCC_HSE1MHZ (0x00000002) /* !< TIM17 TI1 is connected to RCC LSE */
#define | TIM_TIM17_TI1_RCC_MCO1 (0x00000003) /* !< TIM17 TI1 is connected to RCC MCO1 */

Define Documentation

#define TIM_TIM15_BKR_COMP1_OUT (0x00000002) /* !< TIM15_BKR is connected to COMP1 OUT */

Definition at line 284 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_BKR_COMP2_OUT (0x00000004) /* !< TIM15_BKR is connected to COMP2 OUT */

Definition at line 285 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_BKR_DFSDM_BRK0 (0x00000000) /* !< TIM15_BKR is connected to DFSDM BRK0 */

Definition at line 286 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_BKR_GPIO (0x00000000) /* !< TIM15_BKR is connected to GPIO */

Definition at line 283 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_GPIO (0x00000000) /* !< TIM15_TI1 is connected to GPIO */

Definition at line 328 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_RCC_CSI (0x00000005) /* !< TIM15_TI1 is connected to RCC CSI */

Definition at line 333 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_RCC_LSE (0x00000004) /* !< TIM15_TI1 is connected to RCC LSE */

Definition at line 332 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_RCC_MCO2 (0x00000006) /* !< TIM15_TI1 is connected to RCC MCO2 */

Definition at line 334 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_TIM2_CH1 (0x00000001) /* !< TIM15_TI1 is connected to TIM2 CH1 */

Definition at line 329 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_TIM3_CH1 (0x00000002) /* !< TIM15_TI1 is connected to TIM3 CH1 */

Definition at line 330 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_TIM4_CH1 (0x00000003) /* !< TIM15_TI1 is connected to TIM4 CH1 */

Definition at line 331 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI2_GPIO (0x00000000) /* !< TIM15_TI2 is connected to GPIO */

Definition at line 336 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI2_TIM2_CH2 (0x00000100) /* !< TIM15_TI2 is connected to TIM2 CH2 */

Definition at line 337 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI2_TIM3_CH2 (0x00000200) /* !< TIM15_TI2 is connected to TIM3 CH2 */

Definition at line 338 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM15_TI2_TIM4_CH2 (0x00000300) /* !< TIM15_TI2 is connected to TIM4 CH2 */

Definition at line 339 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM16_BKR_COMP1_OUT (0x00000002) /* !< TIM16_BKR is connected to COMP1 OUT */

Definition at line 289 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM16_BKR_COMP2_OUT (0x00000004) /* !< TIM16_BKR is connected to COMP2 OUT */

Definition at line 290 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM16_BKR_DFSDM_BRK1 (0x00000000) /* !< TIM16_BKR is connected to DFSDM BRK1 */

Definition at line 291 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM16_BKR_GPIO (0x00000000) /* !< TIM16_BKR is connected to GPIO */

Definition at line 288 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */

Definition at line 341 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_RCC_LSE (0x00000002) /* !< TIM16 TI1 is connected to RCC LSE */

Definition at line 343 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_RCC_LSI (0x00000001) /* !< TIM16 TI1 is connected to RCC LSI */

Definition at line 342 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_WKUP_IT (0x00000003) /* !< TIM16 TI1 is connected to WKUP_IT */

Definition at line 344 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM17_BKR_COMP1_OUT (0x00000002) /* !< TIM17_BKR is connected to COMP1 OUT */

Definition at line 294 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM17_BKR_COMP2_OUT (0x00000004) /* !< TIM17_BKR is connected to COMP2 OUT */

Definition at line 295 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM17_BKR_DFSDM_BRK2 (0x00000000) /* !< TIM17_BKR is connected to DFSDM BRK2 */

Definition at line 296 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM17_BKR_GPIO (0x00000000) /* !< TIM17_BKR is connected to GPIO */

Definition at line 293 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_GPIO (0x00000000) /* !< TIM17 TI1 is connected to GPIO */

Definition at line 346 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_RCC_HSE1MHZ (0x00000002) /* !< TIM17 TI1 is connected to RCC LSE */

Definition at line 348 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_RCC_MCO1 (0x00000003) /* !< TIM17 TI1 is connected to RCC MCO1 */

Definition at line 349 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_SPDIF_FS (0x00000001) /* !< TIM17 TI1 is connected to RCC LSI */

Definition at line 347 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_BKR2_COMP1_OUT (0x00000002) /* !< TIM1_BKR2 is connected to COMP1 OUT */

Definition at line 299 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_BKR2_COMP2_OUT (0x00000004) /* !< TIM1_BKR2 is connected to COMP2 OUT */

Definition at line 300 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_BKR2_DFSDM_BRK1 (0x00000000) /* !< TIM1_BKR2 is connected to DFSDM BRK0 */

Definition at line 301 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_BKR2_GPIO (0x00000000) /* !< TIM1_BKR2 is connected to GPIO */

Definition at line 298 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_BKR_COMP1_OUT (0x00000002) /* !< TIM1_BKR is connected to COMP1 OUT */

Definition at line 274 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_BKR_COMP2_OUT (0x00000004) /* !< TIM1_BKR is connected to COMP2 OUT */

Definition at line 275 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_BKR_DFSDM_BRK0 (0x00000000) /* !< TIM1_BKR is connected to DFSDM BRK0 */

Definition at line 276 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_BKR_GPIO (0x00000000) /* !< TIM1_BKR is connected to GPIO */

Definition at line 273 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC1_AWD1 (0x0000C000) /* !< TIM1_ETR is connected to ADC1 AWD1 */

Definition at line 240 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC1_AWD2 (0x00010000) /* !< TIM1_ETR is connected to ADC1 AWD2 */

Definition at line 241 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC1_AWD3 (0x00014000) /* !< TIM1_ETR is connected to ADC1 AWD3 */

Definition at line 242 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC3_AWD1 (0x00018000) /* !< TIM1_ETR is connected to ADC3 AWD1 */

Definition at line 243 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC3_AWD2 (0x0001C000) /* !< TIM1_ETR is connected to ADC3 AWD2 */

Definition at line 244 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC3_AWD3 (0x00020000) /* !< TIM1_ETR is connected to ADC3 AWD3 */

Definition at line 245 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_COMP1_OUT (0x00004000) /* !< TIM1_ETR is connected to COMP1 OUT */

Definition at line 246 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_COMP2_OUT (0x00008000) /* !< TIM1_ETR is connected to COMP2 OUT */

Definition at line 247 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_GPIO (0x00000000) /* !< TIM1_ETR is connected to GPIO */

Definition at line 239 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_TI1_COMP1_OUT (0x00000001) /* !< TIM1_TI1 is connected to COMP1 OUT */

Definition at line 309 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM1_TI1_GPIO (0x00000000) /* !< TIM1_TI1 is connected to GPIO */

Definition at line 308 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_COMP1_OUT (0x0000C000) /* !< TIM2_ETR is connected to COMP1 OUT */

Definition at line 260 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_COMP2_OUT (0x00010000) /* !< TIM2_ETR is connected to COMP2 OUT */

Definition at line 261 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_GPIO (0x00000000) /* !< TIM2_ETR is connected to GPIO */

Definition at line 259 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_RCC_LSE (0x00014000) /* !< TIM2_ETR is connected to RCC LSE */

Definition at line 262 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_SAI1_FSA (0x00018000) /* !< TIM2_ETR is connected to SAI1 FS_A */

Definition at line 263 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_SAI1_FSB (0x0001C000) /* !< TIM2_ETR is connected to SAI1 FS_B */

Definition at line 264 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM2_TI4_COMP1_OUT (0x01000000) /* !< TIM2_TI4 is connected to COMP1 OUT */

Definition at line 315 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM2_TI4_COMP1COMP2_OUT (0x03000000) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */

Definition at line 317 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM2_TI4_COMP2_OUT (0x02000000) /* !< TIM2_TI4 is connected to COMP2 OUT */

Definition at line 316 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM2_TI4_GPIO (0x00000000) /* !< TIM2_TI4 is connected to GPIO */

Definition at line 314 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM3_ETR_COMP1_OUT (0x00000000) /* !< TIM3_ETR is connected to COMP1 OUT */

Definition at line 267 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM3_ETR_GPIO (0x00000000) /* !< TIM3_ETR is connected to GPIO */

Definition at line 266 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM3_TI1_COMP1_OUT (0x00000001) /* !< TIM3_TI1 is connected to COMP1 OUT */

Definition at line 320 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM3_TI1_COMP1COMP2_OUT (0x00000003) /* !< TIM3_TI1 is connected to COMP2 OUT OR COMP2 OUT */

Definition at line 322 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM3_TI1_COMP2_OUT (0x00000002) /* !< TIM3_TI1 is connected to COMP2 OUT */

Definition at line 321 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM3_TI1_GPIO (0x00000000) /* !< TIM3_TI1 is connected to GPIO */

Definition at line 319 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM5_ETR_GPIO (0x00000000) /* !< TIM5_ETR is connected to GPIO */

Definition at line 269 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM5_ETR_SAI2_FSA (0x00000000) /* !< TIM5_ETR is connected to SAI2 FS_A */

Definition at line 270 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM5_ETR_SAI2_FSB (0x00000000) /* !< TIM5_ETR is connected to SAI2 FS_B */

Definition at line 271 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM5_TI1_CAN_RTP (0x00000002) /* !< TIM5_TI1 is connected to CAN RTP */

Definition at line 326 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM5_TI1_CAN_TMP (0x00000001) /* !< TIM5_TI1 is connected to CAN TMP */

Definition at line 325 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM5_TI1_GPIO (0x00000000) /* !< TIM5_TI1 is connected to GPIO */

Definition at line 324 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_BKR2_COMP1_OUT (0x00000002) /* !< TIM8_BKR2 is connected to COMP1 OUT */

Definition at line 304 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_BKR2_COMP2_OUT (0x00000004) /* !< TIM8_BKR2 is connected to COMP2 OUT */

Definition at line 305 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_BKR2_DFSDM_BRK3 (0x00000000) /* !< TIM8_BKR2 is connected to DFSDM BRK3 */

Definition at line 306 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_BKR2_GPIO (0x00000000) /* !< TIM8_BKR2 is connected to GPIO */

Definition at line 303 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_BKR_COMP1_OUT (0x00000002) /* !< TIM8_BKR is connected to COMP1 OUT */

Definition at line 279 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_BKR_COMP2_OUT (0x00000004) /* !< TIM8_BKR is connected to COMP2 OUT */

Definition at line 280 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_BKR_DFSDM_BRK2 (0x00000000) /* !< TIM8_BKR is connected to DFSDM BRK2 */

Definition at line 281 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_BKR_GPIO (0x00000000) /* !< TIM8_BKR is connected to GPIO */

Definition at line 278 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC2_AWD1 (0x0000C000) /* !< TIM8_ETR is connected to ADC2 AWD1 */

Definition at line 250 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC2_AWD2 (0x00010000) /* !< TIM8_ETR is connected to ADC2 AWD2 */

Definition at line 251 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC2_AWD3 (0x00014000) /* !< TIM8_ETR is connected to ADC2 AWD3 */

Definition at line 252 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC3_AWD1 (0x00018000) /* !< TIM8_ETR is connected to ADC3 AWD1 */

Definition at line 253 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC3_AWD2 (0x0001C000) /* !< TIM8_ETR is connected to ADC3 AWD2 */

Definition at line 254 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC3_AWD3 (0x00020000) /* !< TIM8_ETR is connected to ADC3 AWD3 */

Definition at line 255 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_COMP1_OUT (0x00004000) /* !< TIM8_ETR is connected to COMP1 OUT */

Definition at line 256 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_COMP2_OUT (0x00008000) /* !< TIM8_ETR is connected to COMP2 OUT */

Definition at line 257 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_GPIO (0x00000000) /* !< TIM8_ETR is connected to GPIO */

Definition at line 249 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_TI1_COMP2_OUT (0x00000001) /* !< TIM8_TI1 is connected to COMP2 OUT */

Definition at line 312 of file stm32h7xx_hal_tim_ex.h.

#define TIM_TIM8_TI1_GPIO (0x00000000) /* !< TIM8_TI1 is connected to GPIO */

Definition at line 311 of file stm32h7xx_hal_tim_ex.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Extended Break input

Defines
TIM Extended Break input
Group Channel 5 and Channel 1, 2 or 3

Defines

#define | TIM_BREAKINPUT_BRK ((uint32_t)(0x00000001)) /* !< Timer break input */
#define | TIM_BREAKINPUT_BRK2 ((uint32_t)(0x00000002)) /* !< Timer break2 input */

Define Documentation

#define TIM_BREAKINPUT_BRK ((uint32_t)(0x00000001)) /* !< Timer break input */

Definition at line 367 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUT_BRK2 ((uint32_t)(0x00000002)) /* !< Timer break2 input */

Definition at line 368 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Extended Break input source

Defines
TIM Extended Break input source
Group Channel 5 and Channel 1, 2 or 3

Defines

#define | TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin */
#define | TIM_BREAKINPUTSOURCE_COMP1 ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_COMP2 ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */

Define Documentation

#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin */

Definition at line 376 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUTSOURCE_COMP1 ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */

Definition at line 377 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUTSOURCE_COMP2 ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */

Definition at line 378 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */

Definition at line 379 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Extended Break input source enabling

Defines
TIM Extended Break input source enabling
Group Channel 5 and Channel 1, 2 or 3

Defines

#define | TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)(0x00000000)) /* !< Break input source is disabled */
#define | TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)(0x00000001)) /* !< Break input source is enabled */

Define Documentation

#define TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)(0x00000000)) /* !< Break input source is disabled */

Definition at line 387 of file stm32h7xx_hal_tim_ex.h.

#define TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)(0x00000001)) /* !< Break input source is enabled */

Definition at line 388 of file stm32h7xx_hal_tim_ex.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Extended Break input polarity

Defines
TIM Extended Break input polarity
Group Channel 5 and Channel 1, 2 or 3

Defines

#define | TIM_BREAKINPUTSOURCE_POLARITY_LOW ((uint32_t)(0x00000001)) /* !< Break input source is active low */
#define | TIM_BREAKINPUTSOURCE_POLARITY_HIGH ((uint32_t)(0x00000000)) /* !< Break input source is active_high */

Define Documentation

#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH ((uint32_t)(0x00000000)) /* !< Break input source is active_high */

Definition at line 397 of file stm32h7xx_hal_tim_ex.h.

#define TIM_BREAKINPUTSOURCE_POLARITY_LOW ((uint32_t)(0x00000001)) /* !< Break input source is active low */

Definition at line 396 of file stm32h7xx_hal_tim_ex.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Group Channel 5 and Channel 1, 2 or 3

Modules | Defines
Group Channel 5 and Channel 1, 2 or 3
TIM Extended Exported Constants

Modules

TIM Extended Break input
TIM Extended Break input source
TIM Extended Break input source enabling
TIM Extended Break input polarity

Defines

#define | TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
#define | TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
#define | TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
#define | TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */

Define Documentation

#define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */

Definition at line 358 of file stm32h7xx_hal_tim_ex.h.

#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */

Definition at line 359 of file stm32h7xx_hal_tim_ex.h.

#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */

Definition at line 360 of file stm32h7xx_hal_tim_ex.h.

#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */

Definition at line 361 of file stm32h7xx_hal_tim_ex.h.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Extended Private Macros

Defines
TIM Extended Private Macros
TIM Extended Exported Macros

Defines

#define | IS_TIM_REMAP(__REMAP__) (((__REMAP__) <= (uint32_t)0x0001C01F))
#define | IS_TIM_BREAKINPUT(__BREAKINPUT__)
#define | IS_TIM_BREAKINPUTSOURCE(__SOURCE__)
#define | IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)
#define | IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)
#define | IS_TIM_TISEL(TISEL)
#define | IS_TIM_BKR2REMAP(BK2RREMAP)
#define | IS_TIM_BKRREMAP(BKRREMAP)
#define | IS_TIM_ETRREMAP(ETRREMAP)

Define Documentation

#define IS_TIM_BKR2REMAP ( BK2RREMAP )
Value:
(((BKR2REMAP) == TIM_TIM1_BKR_GPIO)      ||\
                                        ((BKR2REMAP) == TIM_TIM1_BKR_GPIO)      ||\
                                        ((BKR2REMAP) == TIM_TIM1_BKR_GPIO)      ||\
                                        ((BKR2REMAP) == TIM_TIM1_BKR_GPIO)      ||\
                                        ((BKR2REMAP) == TIM_TIM1_BKR_GPIO)      ||\
                                        ((BKR2REMAP) == TIM_TIM1_BKR_GPIO)      ||\
                                        ((BKR2REMAP) == TIM_TIM1_BKR_GPIO)      ||\
                                        ((BKR2REMAP) == TIM_TIM1_BKR_GPIO))

Definition at line 469 of file stm32h7xx_hal_tim_ex.h.

#define IS_TIM_BKRREMAP ( BKRREMAP )
Value:
(((BKRREMAP) == TIM_TIM1_BKR_GPIO)      ||\
                                      ((BKRREMAP) == TIM_TIM1_BKR_COMP1_OUT)      ||\
                                      ((BKRREMAP) == TIM_TIM1_BKR_COMP2_OUT)      ||\
                                      ((BKRREMAP) == TIM_TIM1_BKR_DFSDM_BRK0)      ||\
                                      ((BKRREMAP) == TIM_TIM8_BKR_GPIO)      ||\
                                      ((BKRREMAP) == TIM_TIM8_BKR_COMP1_OUT)      ||\
                                      ((BKRREMAP) == TIM_TIM8_BKR_COMP2_OUT)      ||\
                                      ((BKRREMAP) == TIM_TIM8_BKR_DFSDM_BRK2)      ||\
                                      ((BKRREMAP) == TIM_TIM15_BKR_GPIO)      ||\
                                      ((BKRREMAP) == TIM_TIM15_BKR_COMP1_OUT)      ||\
                                      ((BKRREMAP) == TIM_TIM15_BKR_COMP2_OUT)      ||\
                                      ((BKRREMAP) == TIM_TIM15_BKR_DFSDM_BRK0)      ||\
                                      ((BKRREMAP) == TIM_TIM16_BKR_GPIO)      ||\
                                      ((BKRREMAP) == TIM_TIM16_BKR_COMP1_OUT)      ||\
                                      ((BKRREMAP) == TIM_TIM16_BKR_COMP2_OUT)      ||\
                                      ((BKRREMAP) == TIM_TIM16_BKR_DFSDM_BRK1)      ||\
                                      ((BKRREMAP) == TIM_TIM17_BKR_GPIO)      ||\
                                      ((BKRREMAP) == TIM_TIM17_BKR_COMP1_OUT)      ||\
                                      ((BKRREMAP) == TIM_TIM17_BKR_COMP2_OUT)      ||\
                                      ((BKRREMAP) == TIM_TIM17_BKR_DFSDM_BRK2))

Definition at line 478 of file stm32h7xx_hal_tim_ex.h.

#define IS_TIM_BREAKINPUT ( __BREAKINPUT__ )
Value:
(((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))

Definition at line 420 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_BREAKINPUTSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))

Definition at line 423 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_BREAKINPUTSOURCE_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
                                                         ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))

Definition at line 431 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_BREAKINPUTSOURCE_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))

Definition at line 428 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_ETRREMAP ( ETRREMAP )
Value:
(((ETRREMAP) == TIM_TIM1_ETR_GPIO)      ||\
                                      ((ETRREMAP) == TIM_TIM1_ETR_ADC1_AWD1) ||\
                                      ((ETRREMAP) == TIM_TIM1_ETR_ADC1_AWD2) ||\
                                      ((ETRREMAP) == TIM_TIM1_ETR_ADC1_AWD3) ||\
                                      ((ETRREMAP) == TIM_TIM1_ETR_ADC3_AWD1) ||\
                                      ((ETRREMAP) == TIM_TIM1_ETR_ADC3_AWD2) ||\
                                      ((ETRREMAP) == TIM_TIM1_ETR_ADC3_AWD3) ||\
                                      ((ETRREMAP) == TIM_TIM1_ETR_COMP1_OUT) ||\
                                      ((ETRREMAP) == TIM_TIM1_ETR_COMP2_OUT) ||\
                                      ((ETRREMAP) == TIM_TIM8_ETR_GPIO)      ||\
                                      ((ETRREMAP) == TIM_TIM8_ETR_ADC2_AWD1) ||\
                                      ((ETRREMAP) == TIM_TIM8_ETR_ADC2_AWD2) ||\
                                      ((ETRREMAP) == TIM_TIM8_ETR_ADC2_AWD3) ||\
                                      ((ETRREMAP) == TIM_TIM8_ETR_ADC3_AWD1) ||\
                                      ((ETRREMAP) == TIM_TIM8_ETR_ADC3_AWD2) ||\
                                      ((ETRREMAP) == TIM_TIM8_ETR_ADC3_AWD3) ||\
                                      ((ETRREMAP) == TIM_TIM8_ETR_COMP1_OUT) ||\
                                      ((ETRREMAP) == TIM_TIM8_ETR_COMP2_OUT) ||\
                                      ((ETRREMAP) == TIM_TIM2_ETR_GPIO)      ||\
                                      ((ETRREMAP) == TIM_TIM2_ETR_COMP1_OUT) ||\
                                      ((ETRREMAP) == TIM_TIM2_ETR_COMP2_OUT) ||\
                                      ((ETRREMAP) == TIM_TIM2_ETR_RCC_LSE)   ||\
                                      ((ETRREMAP) == TIM_TIM2_ETR_SAI1_FSA)  ||\
                                      ((ETRREMAP) == TIM_TIM2_ETR_SAI1_FSB)  ||\
                                      ((ETRREMAP) == TIM_TIM3_ETR_GPIO)      ||\
                                      ((ETRREMAP) == TIM_TIM3_ETR_COMP1_OUT) ||\
                                      ((ETRREMAP) == TIM_TIM5_ETR_GPIO)      ||\
                                      ((ETRREMAP) == TIM_TIM5_ETR_SAI2_FSA)  |\
                                      ((ETRREMAP) == TIM_TIM5_ETR_SAI2_FSB))

Definition at line 499 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_RemapConfig().

#define IS_TIM_REMAP ( __REMAP__ ) (((__REMAP__) <= (uint32_t)0x0001C01F))

Definition at line 418 of file stm32h7xx_hal_tim_ex.h.

#define IS_TIM_TISEL ( TISEL )

Definition at line 434 of file stm32h7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_TISelection().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIMEx Private Functions

Functions
TIMEx Private Functions
TIM Extended Exported Macros

Functions

void HAL_TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.

Function Documentation

void HAL_TIMEx_DMACommutationCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Commutation callback.

Parameters:
hdma : pointer to DMA handle.
Return values:
None

Definition at line 2043 of file stm32h7xx_hal_tim_ex.c.

References HAL_TIM_STATE_READY, HAL_TIMEx_CommutationCallback(), and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIMEx_ConfigCommutationEvent_DMA().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIMEx

Modules | Defines
TIMEx
STM32H7xx_HAL_Driver

TIM Extended HAL module driver. More...

Modules

TIM Extended Exported Functions
TIM Extended Exported Types
TIM Extended Exported Constants
TIM Extended Exported Macros

Defines

#define | BDTR_BKF_SHIFT (16)
#define | BDTR_BK2F_SHIFT (20)
#define | TIMx_ETRSEL_MASK ((uint32_t)0x003C000)
#define | TIMx_TIxSEL_MASK ((uint32_t)0x000000F)

Detailed Description

TIM Extended HAL module driver.

Define Documentation

#define BDTR_BK2F_SHIFT (20)

Definition at line 118 of file stm32h7xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define BDTR_BKF_SHIFT (16)

Definition at line 117 of file stm32h7xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define TIMx_ETRSEL_MASK ((uint32_t)0x003C000)

Definition at line 119 of file stm32h7xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_RemapConfig().

#define TIMx_TIxSEL_MASK ((uint32_t)0x000000F)

Definition at line 120 of file stm32h7xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_TISelection().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Private Constants

Defines
UART Private Constants
UART

Defines

#define | UART_CR1_FIELDS
#define | USART_CR3_FIELDS
#define | UART_LPUART_BRR_MIN ((uint32_t)0x00000300) /* LPUART BRR minimum authorized value */
#define | UART_LPUART_BRR_MAX ((uint32_t)0x000FFFFF) /* LPUART BRR maximum authorized value */

Define Documentation

#define UART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
                                     USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
                                     USART_CR1_FIFOEN ))

UART or USART CR1 fields of parameters set by UART_SetConfig API

Definition at line 121 of file stm32h7xx_hal_uart.c.

Referenced by UART_SetConfig().

#define UART_LPUART_BRR_MAX ((uint32_t)0x000FFFFF) /* LPUART BRR maximum authorized value */

Definition at line 129 of file stm32h7xx_hal_uart.c.

Referenced by UART_SetConfig().

#define UART_LPUART_BRR_MIN ((uint32_t)0x00000300) /* LPUART BRR minimum authorized value */

Definition at line 128 of file stm32h7xx_hal_uart.c.

Referenced by UART_SetConfig().

#define USART_CR3_FIELDS
Value:
((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \
                                    USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))

UART or USART CR3 fields of parameters set by UART_SetConfig API

Definition at line 125 of file stm32h7xx_hal_uart.c.

Referenced by UART_SetConfig().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
UART Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitialize the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
Initialize the UART MSP.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
DeInitialize the UART MSP.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
    in asynchronous mode.
      (+) For the asynchronous mode the parameters below can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
        (++) Hardware flow control
        (++) Receiver/transmitter modes
        (++) Over Sampling Method
        (++) One-Bit Sampling Method
      (+) For the asynchronous mode, the following advanced features can be configured as well:
        (++) TX and/or RX pin level inversion
        (++) data logical level inversion
        (++) RX and TX pins swap
        (++) RX overrun detection disabling
        (++) DMA disabling on RX error
        (++) MSB first on communication line
        (++) auto Baud rate detection
    [..]
    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
    follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
    and UART multiprocessor mode configuration procedures (details for the procedures
    are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible UART formats are listed in the following table.

Table 1. UART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | UART frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_HalfDuplex_Init ( UART_HandleTypeDef * huart )

Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 294 of file stm32h7xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Instance, UART_HandleTypeDef::Lock, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), and UART_SetConfig().

HAL_StatusTypeDef HAL_LIN_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | BreakDetectLength
 | ) |  |

Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .

Parameters:
huart,: UART handle.
BreakDetectLength,: specifies the LIN break detection length. This parameter can be one of the following values:
  • UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
  • UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
Return values:
HAL status

Definition at line 357 of file stm32h7xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, IS_UART_LIN_BREAK_DETECT_LENGTH, UART_HandleTypeDef::Lock, UART_InitTypeDef::OverSampling, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_OVERSAMPLING_8, UART_SetConfig(), UART_WORDLENGTH_8B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_MultiProcessor_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t | Address,
 |  | uint32_t | WakeUpMethod
 | ) |  |

Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.

Parameters:
huart,: UART handle.
Address,: UART node address (4-, 6-, 7- or 8-bit long).
WakeUpMethod,: specifies the UART wakeup method. This parameter can be one of the following values:
  • UART_WAKEUPMETHOD_IDLELINE: WakeUp by an idle line detection
  • UART_WAKEUPMETHOD_ADDRESSMARK: WakeUp by an address mark
Note:
If the user resorts to idle line detection wake up, the Address parameter is useless and ignored by the initialization function.
If the user resorts to address mark wake up, the address length detection is configured by default to 4 bits only. For the UART to be able to manage 6-, 7- or 8-bit long addresses detection, the API HAL_MultiProcessorEx_AddressLength_Set() must be called after HAL_MultiProcessor_Init().
Return values:
HAL status

Definition at line 444 of file stm32h7xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Instance, IS_UART_WAKEUPMETHOD, UART_HandleTypeDef::Lock, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_CR2_ADDRESS_LSB_POS, UART_SetConfig(), and UART_WAKEUPMETHOD_ADDRESSMARK.

HAL_StatusTypeDef HAL_UART_DeInit ( UART_HandleTypeDef * huart )

DeInitialize the UART peripheral.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 508 of file stm32h7xx_hal_uart.c.

References __HAL_UART_DISABLE, assert_param, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_MspDeInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_UART_Init ( UART_HandleTypeDef * huart )

Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 231 of file stm32h7xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_InitTypeDef::HwFlowCtl, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_HandleTypeDef::Lock, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_HWCONTROL_NONE, and UART_SetConfig().

void HAL_UART_MspDeInit ( UART_HandleTypeDef * huart )

DeInitialize the UART MSP.

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 561 of file stm32h7xx_hal_uart.c.

Referenced by HAL_UART_DeInit().

void HAL_UART_MspInit ( UART_HandleTypeDef * huart )

Initialize the UART MSP.

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 546 of file stm32h7xx_hal_uart.c.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
UART Exported Functions

UART Transmit/Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_Abort (UART_HandleTypeDef *huart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_Abort_IT (UART_HandleTypeDef *huart)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit_IT (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive_IT (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
Handle UART interrupt request.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callback.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callback.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callback.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callback.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callback.
__weak void | HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
UART Abort Receive Complete callback.

Detailed Description

UART Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the UART asynchronous
    and Half duplex data transfers.

    (#) There are two mode of transfer:
       (+) Blocking mode: The communication is performed in polling mode.
           The HAL status of all data processing is returned by the same function
           after finishing transfer.
       (+) Non-Blocking mode: The communication is performed using Interrupts
           or DMA, These API's return the HAL status.
           The end of the data processing will be indicated through the
           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.
           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or Receive process
           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected

    (#) Blocking mode API's are :
        (+) HAL_UART_Transmit()
        (+) HAL_UART_Receive()

    (#) Non-Blocking mode API's with Interrupt are :
        (+) HAL_UART_Transmit_IT()
        (+) HAL_UART_Receive_IT()
        (+) HAL_UART_IRQHandler()

    (#) Non-Blocking mode API's with DMA are :
        (+) HAL_UART_Transmit_DMA()
        (+) HAL_UART_Receive_DMA()
        (+) HAL_UART_DMAPause()
        (+) HAL_UART_DMAResume()
        (+) HAL_UART_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
        (+) HAL_UART_TxHalfCpltCallback()
        (+) HAL_UART_TxCpltCallback()
        (+) HAL_UART_RxHalfCpltCallback()
        (+) HAL_UART_RxCpltCallback()
        (+) HAL_UART_ErrorCallback()

    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (+) HAL_UART_Abort()
        (+) HAL_UART_AbortTransmit()
        (+) HAL_UART_AbortReceive()
        (+) HAL_UART_Abort_IT()
        (+) HAL_UART_AbortTransmit_IT()
        (+) HAL_UART_AbortReceive_IT()

    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
        (+) HAL_UART_AbortCpltCallback()
        (+) HAL_UART_AbortTransmitCpltCallback()
        (+) HAL_UART_AbortReceiveCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
           and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
           If user wants to abort it, Abort services should be called by user.
       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.

    -@- In the Half duplex communication, it is forbidden to run the transmit
        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.

Function Documentation

HAL_StatusTypeDef HAL_UART_Abort ( UART_HandleTypeDef * huart )

Abort ongoing transfers (blocking mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1151 of file stm32h7xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_Abort_IT ( UART_HandleTypeDef * huart )

Abort ongoing transfers (Interrupt mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1309 of file stm32h7xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_UART_AbortCpltCallback(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_UART_AbortCpltCallback ( UART_HandleTypeDef * huart )

UART Abort Complete callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 1802 of file stm32h7xx_hal_uart.c.

Referenced by HAL_UART_Abort_IT(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

HAL_StatusTypeDef HAL_UART_AbortReceive ( UART_HandleTypeDef * huart )

Abort ongoing Receive transfer (blocking mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1261 of file stm32h7xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, HAL_DMA_Abort(), HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_AbortReceive_IT ( UART_HandleTypeDef * huart )

Abort ongoing Receive transfer (Interrupt mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1500 of file stm32h7xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, HAL_DMA_Abort_IT(), HAL_UART_AbortReceiveCpltCallback(), HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_DMARxOnlyAbortCallback(), and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_UART_AbortReceiveCpltCallback ( UART_HandleTypeDef * huart )

UART Abort Receive Complete callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 1832 of file stm32h7xx_hal_uart.c.

Referenced by HAL_UART_AbortReceive_IT(), and UART_DMARxOnlyAbortCallback().

HAL_StatusTypeDef HAL_UART_AbortTransmit ( UART_HandleTypeDef * huart )

Abort ongoing Transmit transfer (blocking mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1218 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_UART_STATE_READY, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_AbortTransmit_IT ( UART_HandleTypeDef * huart )

Abort ongoing Transmit transfer (Interrupt mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1434 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_UART_AbortTransmitCpltCallback(), HAL_UART_STATE_READY, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::TxXferCount, UART_DMATxOnlyAbortCallback(), and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_UART_AbortTransmitCpltCallback ( UART_HandleTypeDef * huart )

UART Abort Complete callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 1817 of file stm32h7xx_hal_uart.c.

Referenced by HAL_UART_AbortTransmit_IT(), and UART_DMATxOnlyAbortCallback().

HAL_StatusTypeDef HAL_UART_DMAPause ( UART_HandleTypeDef * huart )

Pause the DMA Transfer.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 1030 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_UART_DMAResume ( UART_HandleTypeDef * huart )

Resume the DMA Transfer.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 1063 of file stm32h7xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, and UART_CLEAR_OREF.

HAL_StatusTypeDef HAL_UART_DMAStop ( UART_HandleTypeDef * huart )

Stop the DMA Transfer.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 1097 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, UART_EndRxTransfer(), and UART_EndTxTransfer().

void HAL_UART_ErrorCallback ( UART_HandleTypeDef * huart )

UART error callback.

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 1787 of file stm32h7xx_hal_uart.c.

Referenced by HAL_UART_IRQHandler(), UART_DMAAbortOnError(), and UART_DMAError().

void HAL_UART_IRQHandler ( UART_HandleTypeDef * huart )

Handle UART interrupt request.

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 1563 of file stm32h7xx_hal_uart.c.

References __HAL_UART_CLEAR_IT, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_UART_ERROR_FE, HAL_UART_ERROR_NE, HAL_UART_ERROR_NONE, HAL_UART_ERROR_ORE, HAL_UART_ERROR_PE, HAL_UART_ErrorCallback(), HAL_UART_STATE_READY, HAL_UARTEx_WakeupCallback(), UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_CLEAR_WUF, UART_DMAAbortOnError(), UART_EndRxTransfer(), UART_EndTransmit_IT(), UART_Receive_IT(), UART_Transmit_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_Receive | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
huart,: UART handle.
pData,: pointer to data buffer.
Size,: amount of data to be received.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 729 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_HandleTypeDef::Mask, UART_InitTypeDef::Parity, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::RxXferSize, UART_FLAG_RXNE, UART_MASK_COMPUTATION, UART_PARITY_NONE, UART_WaitOnFlagUntilTimeout(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_Receive_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Parameters:
huart,: UART handle.
pData,: pointer to data buffer.
Size,: amount of data to be received.
Note:
When the UART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
Return values:
HAL status

Definition at line 970 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::pRxBuffPtr, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferSize, UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxHalfCplt(), __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_UART_Receive_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Parameters:
huart,: UART handle.
pData,: pointer to data buffer.
Size,: amount of data to be received.
Return values:
HAL status

Definition at line 850 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, UART_HandleTypeDef::pRxBuffPtr, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::RxXferSize, and UART_MASK_COMPUTATION.

void HAL_UART_RxCpltCallback ( UART_HandleTypeDef * huart )

Rx Transfer completed callback.

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 1757 of file stm32h7xx_hal_uart.c.

Referenced by UART_DMAReceiveCplt(), and UART_Receive_IT().

void HAL_UART_RxHalfCpltCallback ( UART_HandleTypeDef * huart )

Rx Half Transfer completed callback.

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 1772 of file stm32h7xx_hal_uart.c.

Referenced by UART_DMARxHalfCplt().

HAL_StatusTypeDef HAL_UART_Transmit | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Parameters:
huart,: UART handle.
pData,: Pointer to data buffer.
Size,: Amount of data to be sent.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 660 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, UART_HandleTypeDef::TxXferCount, UART_HandleTypeDef::TxXferSize, UART_FLAG_TC, UART_FLAG_TXE, UART_PARITY_NONE, UART_WaitOnFlagUntilTimeout(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_Transmit_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Parameters:
huart,: UART handle.
pData,: pointer to data buffer.
Size,: amount of data to be sent.
Return values:
HAL status

Definition at line 908 of file stm32h7xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::pTxBuffPtr, UART_HandleTypeDef::TxXferCount, UART_HandleTypeDef::TxXferSize, UART_CLEAR_TCF, UART_DMAError(), UART_DMATransmitCplt(), UART_DMATxHalfCplt(), __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_UART_Transmit_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Parameters:
huart,: UART handle.
pData,: pointer to data buffer.
Size,: amount of data to be sent.
Return values:
HAL status

Definition at line 800 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, UART_HandleTypeDef::pTxBuffPtr, UART_HandleTypeDef::TxXferCount, and UART_HandleTypeDef::TxXferSize.

void HAL_UART_TxCpltCallback ( UART_HandleTypeDef * huart )

Tx Transfer completed callback.

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 1727 of file stm32h7xx_hal_uart.c.

Referenced by UART_DMATransmitCplt(), and UART_EndTransmit_IT().

void HAL_UART_TxHalfCpltCallback ( UART_HandleTypeDef * huart )

Tx Half Transfer completed callback.

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 1742 of file stm32h7xx_hal_uart.c.

Referenced by UART_DMATxHalfCplt().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
UART Exported Functions

UART control functions. More...

Functions

HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enable the UART transmitter and disable the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enable the UART receiver and disable the UART transmitter.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmit break characters.

Detailed Description

UART control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the UART.
     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
     (+) UART_SetConfig() API configures the UART peripheral
     (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
     (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
     (+) HAL_LIN_SendBreak() API transmits the break characters

Function Documentation

HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver ( UART_HandleTypeDef * huart )

Enable the UART receiver and disable the UART transmitter.

Parameters:
huart,: UART handle.
Return values:
HAL status.

Definition at line 1950 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter ( UART_HandleTypeDef * huart )

Enable the UART transmitter and disable the UART receiver.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 1926 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_LIN_SendBreak ( UART_HandleTypeDef * huart )

Transmit break characters.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 1974 of file stm32h7xx_hal_uart.c.

References assert_param, UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, and UART_SENDBREAK_REQUEST.

HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode ( UART_HandleTypeDef * huart )

Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 1895 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, and UART_CheckIdleState().

HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode ( UART_HandleTypeDef * huart )

Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 1874 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, and UART_CheckIdleState().

void HAL_MultiProcessor_EnterMuteMode ( UART_HandleTypeDef * huart )

Enter UART mute mode (means UART actually enters mute mode).

Note:
To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
Parameters:
huart,: UART handle.
Return values:
None

Definition at line 1916 of file stm32h7xx_hal_uart.c.

References __HAL_UART_SEND_REQ, and UART_MUTE_MODE_REQUEST.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
UART Exported Functions

UART Peripheral State functions. More...

Functions

HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
Return the UART handle state.
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART handle error code.

Detailed Description

UART Peripheral State functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) Return the UART handle state.
      (+) Return the UART handle error code

Function Documentation

uint32_t HAL_UART_GetError ( UART_HandleTypeDef * huart )

Return the UART handle error code.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART.
Return values:
UART Error Code

Definition at line 2037 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode.

HAL_UART_StateTypeDef HAL_UART_GetState ( UART_HandleTypeDef * huart )

Return the UART handle state.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART.
Return values:
HAL state

Definition at line 2022 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::gState, and UART_HandleTypeDef::RxState.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Private Functions

Functions
UART Private Functions
UART

Functions

static void | UART_EndTxTransfer (UART_HandleTypeDef *huart)
End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
static void | UART_EndRxTransfer (UART_HandleTypeDef *huart)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | UART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process complete callback.
static void | UART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process complete callback.
static void | UART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process half complete callback.
static void | UART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process half complete callback.
static void | UART_DMAError (DMA_HandleTypeDef *hdma)
DMA UART communication error callback.
static void | UART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA UART communication abort callback (To be called at end of DMA Abort procedure).
static void | UART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | UART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | UART_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user by a call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | UART_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user by a call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static HAL_StatusTypeDef | UART_Transmit_IT (UART_HandleTypeDef *huart)
Send an amount of data in interrupt mode.
static HAL_StatusTypeDef | UART_EndTransmit_IT (UART_HandleTypeDef *huart)
Wrap up transmission in non-blocking mode.
static HAL_StatusTypeDef | UART_Receive_IT (UART_HandleTypeDef *huart)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle UART Communication Timeout.

Function Documentation

void UART_AdvFeatureConfig ( UART_HandleTypeDef * huart )

Configure the UART peripheral advanced features.

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 2330 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_AdvFeatureInitTypeDef::AutoBaudRateEnable, UART_AdvFeatureInitTypeDef::AutoBaudRateMode, UART_AdvFeatureInitTypeDef::DataInvert, UART_AdvFeatureInitTypeDef::DMADisableonRxError, UART_HandleTypeDef::Instance, IS_UART_ADVFEATURE_AUTOBAUDRATE, IS_UART_ADVFEATURE_AUTOBAUDRATEMODE, IS_UART_ADVFEATURE_DATAINV, IS_UART_ADVFEATURE_DMAONRXERROR, IS_UART_ADVFEATURE_INIT, IS_UART_ADVFEATURE_MSBFIRST, IS_UART_ADVFEATURE_RXINV, IS_UART_ADVFEATURE_SWAP, IS_UART_ADVFEATURE_TXINV, IS_UART_OVERRUN, UART_AdvFeatureInitTypeDef::MSBFirst, UART_AdvFeatureInitTypeDef::OverrunDisable, UART_AdvFeatureInitTypeDef::RxPinLevelInvert, UART_AdvFeatureInitTypeDef::Swap, UART_AdvFeatureInitTypeDef::TxPinLevelInvert, UART_ADVFEATURE_AUTOBAUDRATE_ENABLE, UART_ADVFEATURE_AUTOBAUDRATE_INIT, UART_ADVFEATURE_DATAINVERT_INIT, UART_ADVFEATURE_DMADISABLEONERROR_INIT, UART_ADVFEATURE_MSBFIRST_INIT, UART_ADVFEATURE_RXINVERT_INIT, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT, UART_ADVFEATURE_SWAP_INIT, and UART_ADVFEATURE_TXINVERT_INIT.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

HAL_StatusTypeDef UART_CheckIdleState ( UART_HandleTypeDef * huart )

Check the UART Idle State.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 2404 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, HAL_UART_TIMEOUT_VALUE, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, and UART_WaitOnFlagUntilTimeout().

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), and HAL_UART_Init().

static void UART_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA UART communication abort callback (To be called at end of DMA Abort procedure).

Parameters:
hdma,: DMA handle.
Return values:
None

Definition at line 2634 of file stm32h7xx_hal_uart.c.

References HAL_UART_ErrorCallback(), __DMA_HandleTypeDef::Parent, UART_HandleTypeDef::RxXferCount, and UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_IRQHandler().

static void UART_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA UART communication error callback.

Parameters:
hdma,: DMA handle.
Return values:
None

Definition at line 2600 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_DMA_ERROR_FE, HAL_DMA_GetError(), HAL_UART_ERROR_DMA, HAL_UART_ErrorCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::TxXferCount, UART_EndRxTransfer(), and UART_EndTxTransfer().

Referenced by HAL_UART_Receive_DMA(), and HAL_UART_Transmit_DMA().

static void UART_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART receive process complete callback.

Parameters:
hdma,: DMA handle.
Return values:
None

Definition at line 2559 of file stm32h7xx_hal_uart.c.

References DMA_CIRCULAR, HAL_UART_RxCpltCallback(), HAL_UART_STATE_READY, __DMA_HandleTypeDef::Init, UART_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __DMA_HandleTypeDef::Parent, UART_HandleTypeDef::RxState, and UART_HandleTypeDef::RxXferCount.

Referenced by HAL_UART_Receive_DMA().

static void UART_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2693 of file stm32h7xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_AbortCpltCallback(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_UART_Abort_IT().

static void UART_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART receive process half complete callback.

Parameters:
hdma : DMA handle.
Return values:
None

Definition at line 2588 of file stm32h7xx_hal_uart.c.

References HAL_UART_RxHalfCpltCallback(), and __DMA_HandleTypeDef::Parent.

Referenced by HAL_UART_Receive_DMA().

static void UART_DMARxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Rx communication abort callback, when initiated by user by a call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2756 of file stm32h7xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, HAL_UART_AbortReceiveCpltCallback(), HAL_UART_STATE_READY, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, and UART_CLEAR_PEF.

Referenced by HAL_UART_AbortReceive_IT().

static void UART_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART transmit process complete callback.

Parameters:
hdma,: DMA handle.
Return values:
None

Definition at line 2518 of file stm32h7xx_hal_uart.c.

References DMA_CIRCULAR, HAL_UART_TxCpltCallback(), __DMA_HandleTypeDef::Init, UART_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __DMA_HandleTypeDef::Parent, and UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_DMA().

static void UART_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2651 of file stm32h7xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_AbortCpltCallback(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_UART_Abort_IT().

static void UART_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART transmit process half complete callback.

Parameters:
hdma : DMA handle.
Return values:
None

Definition at line 2547 of file stm32h7xx_hal_uart.c.

References HAL_UART_TxHalfCpltCallback(), and __DMA_HandleTypeDef::Parent.

Referenced by HAL_UART_Transmit_DMA().

static void UART_DMATxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Tx communication abort callback, when initiated by user by a call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2735 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_AbortTransmitCpltCallback(), HAL_UART_STATE_READY, __DMA_HandleTypeDef::Parent, and UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_AbortTransmit_IT().

static void UART_EndRxTransfer ( UART_HandleTypeDef * huart ) [static]

End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 2502 of file stm32h7xx_hal_uart.c.

References HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::RxState.

Referenced by HAL_UART_DMAStop(), HAL_UART_IRQHandler(), and UART_DMAError().

static HAL_StatusTypeDef UART_EndTransmit_IT ( UART_HandleTypeDef * huart ) [static]

Wrap up transmission in non-blocking mode.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 2834 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_READY, HAL_UART_TxCpltCallback(), and UART_HandleTypeDef::Instance.

Referenced by HAL_UART_IRQHandler().

static void UART_EndTxTransfer ( UART_HandleTypeDef * huart ) [static]

End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 2487 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

Referenced by HAL_UART_DMAStop(), and UART_DMAError().

static HAL_StatusTypeDef UART_Receive_IT ( UART_HandleTypeDef * huart ) [static]

Receive an amount of data in interrupt mode.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Receive_IT()
Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 2855 of file stm32h7xx_hal_uart.c.

References __HAL_UART_SEND_REQ, HAL_UART_RxCpltCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_HandleTypeDef::Mask, UART_InitTypeDef::Parity, UART_HandleTypeDef::pRxBuffPtr, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_PARITY_NONE, UART_RXDATA_FLUSH_REQUEST, UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

Referenced by HAL_UART_IRQHandler().

HAL_StatusTypeDef UART_SetConfig ( UART_HandleTypeDef * huart )

Configure the UART peripheral.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 2058 of file stm32h7xx_hal_uart.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_HSI_DIVIDER, assert_param, UART_InitTypeDef::BaudRate, CSI_VALUE, UART_InitTypeDef::FIFOMode, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCCEx_GetD3PCLK1Freq(), HAL_RCCEx_GetPLL2ClockFreq(), HAL_RCCEx_GetPLL3ClockFreq(), HSI_VALUE, UART_InitTypeDef::HwFlowCtl, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, IS_LPUART_STOPBITS, IS_UART_BAUDRATE, IS_UART_FIFO_MODE_STATE, IS_UART_HARDWARE_FLOW_CONTROL, IS_UART_MODE, IS_UART_ONE_BIT_SAMPLE, IS_UART_OVERSAMPLING, IS_UART_PARITY, IS_UART_PRESCALER, IS_UART_RXFIFO_THRESHOLD, IS_UART_STOPBITS, IS_UART_TXFIFO_THRESHOLD, IS_UART_WORD_LENGTH, LSE_VALUE, UART_InitTypeDef::Mode, UART_InitTypeDef::OneBitSampling, UART_InitTypeDef::OverSampling, UART_InitTypeDef::Parity, PLL2_ClocksTypeDef::PLL2_Q_Frequency, PLL3_ClocksTypeDef::PLL3_Q_Frequency, UART_InitTypeDef::Prescaler, RCC_FLAG_HSIDIV, UART_InitTypeDef::RXFIFOThreshold, UART_InitTypeDef::StopBits, UART_InitTypeDef::TXFIFOThreshold, UART_CLOCKSOURCE_CSI, UART_CLOCKSOURCE_D2PCLK1, UART_CLOCKSOURCE_D2PCLK2, UART_CLOCKSOURCE_D3PCLK1, UART_CLOCKSOURCE_HSI, UART_CLOCKSOURCE_LSE, UART_CLOCKSOURCE_PLL2, UART_CLOCKSOURCE_PLL3, UART_CLOCKSOURCE_UNDEFINED, UART_CR1_FIELDS, UART_DIV_LPUART, UART_DIV_SAMPLING16, UART_DIV_SAMPLING8, UART_FIFOMODE_ENABLE, UART_GETCLOCKSOURCE, UART_INSTANCE_LOWPOWER, UART_LPUART_BRR_MAX, UART_LPUART_BRR_MIN, UART_OVERSAMPLING_8, USART_CR3_FIELDS, and UART_InitTypeDef::WordLength.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

static HAL_StatusTypeDef UART_Transmit_IT ( UART_HandleTypeDef * huart ) [static]

Send an amount of data in interrupt mode.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT().
Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 2779 of file stm32h7xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, UART_HandleTypeDef::pTxBuffPtr, UART_HandleTypeDef::TxXferCount, UART_PARITY_NONE, UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

Referenced by HAL_UART_IRQHandler().

HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  |

Handle UART Communication Timeout.

Parameters:
huart,: UART handle.
Flag | Specifies the UART flag to check
Status | Flag status (SET or RESET)
Tickstart | Tick start value
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2454 of file stm32h7xx_hal_uart.c.

References __HAL_UART_GET_FLAG, UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::RxState.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UARTEx_StopModeWakeUpSourceConfig(), and UART_CheckIdleState().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Exported Types

Data Structures | Enumerations
UART Exported Types
UART

Data Structures

struct | UART_InitTypeDef
UART Init Structure definition. More...
struct | UART_AdvFeatureInitTypeDef
UART Advanced Features initalization structure definition. More...
struct | UART_HandleTypeDef
UART handle Structure definition. More...

Enumerations

enum HAL_UART_StateTypeDef {
HAL_UART_STATE_RESET = 0x00U, HAL_UART_STATE_READY = 0x20U, HAL_UART_STATE_BUSY = 0x24U, HAL_UART_STATE_BUSY_TX = 0x21U,
HAL_UART_STATE_BUSY_RX = 0x22U, HAL_UART_STATE_BUSY_TX_RX = 0x23U, HAL_UART_STATE_TIMEOUT = 0xA0U, HAL_UART_STATE_ERROR = 0xE0U
}
HAL UART State structures definition. More...
enum HAL_UART_ErrorTypeDef {
HAL_UART_ERROR_NONE = 0x00U, HAL_UART_ERROR_PE = 0x01U, HAL_UART_ERROR_NE = 0x02U, HAL_UART_ERROR_FE = 0x04U,
HAL_UART_ERROR_ORE = 0x08U, HAL_UART_ERROR_DMA = 0x10U
}
HAL UART Error Code structure definition. More...
enum UART_ClockSourceTypeDef {
UART_CLOCKSOURCE_D2PCLK1 = 0x00U, UART_CLOCKSOURCE_D2PCLK2 = 0x01U, UART_CLOCKSOURCE_D3PCLK1 = 0x02U, UART_CLOCKSOURCE_PLL2 = 0x04U,
UART_CLOCKSOURCE_HSI = 0x08U, UART_CLOCKSOURCE_CSI = 0x10U, UART_CLOCKSOURCE_LSE = 0x20U, UART_CLOCKSOURCE_PLL3 = 0x40U,
UART_CLOCKSOURCE_UNDEFINED = 0x80U
}
UART clock sources definition. More...

Enumeration Type Documentation

enum HAL_UART_ErrorTypeDef

HAL UART Error Code structure definition.

Enumerator:
HAL_UART_ERROR_NONE

No error

HAL_UART_ERROR_PE

Parity error

HAL_UART_ERROR_NE

Noise error

HAL_UART_ERROR_FE

frame error

HAL_UART_ERROR_ORE

Overrun error

HAL_UART_ERROR_DMA

DMA transfer error

Definition at line 221 of file stm32h7xx_hal_uart.h.

enum HAL_UART_StateTypeDef

HAL UART State structures definition.

Note:
HAL UART State value is a combination of 2 different substates: gState and RxState.
  • gState contains UART state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized. HAL UART Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (IP busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.
Enumerator:
HAL_UART_STATE_RESET

Peripheral is not initialized Value is allowed for gState and RxState

HAL_UART_STATE_READY

Peripheral Initialized and ready for use Value is allowed for gState and RxState

HAL_UART_STATE_BUSY

an internal process is ongoing Value is allowed for gState only

HAL_UART_STATE_BUSY_TX

Data Transmission process is ongoing Value is allowed for gState only

HAL_UART_STATE_BUSY_RX

Data Reception process is ongoing Value is allowed for RxState only

HAL_UART_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

HAL_UART_STATE_TIMEOUT

Timeout state Value is allowed for gState only

HAL_UART_STATE_ERROR

Error Value is allowed for gState only

Definition at line 197 of file stm32h7xx_hal_uart.h.

enum UART_ClockSourceTypeDef

UART clock sources definition.

Enumerator:
UART_CLOCKSOURCE_D2PCLK1

Domain2 PCLK1 clock source

UART_CLOCKSOURCE_D2PCLK2

Domain2 PCLK2 clock source

UART_CLOCKSOURCE_D3PCLK1

Domain3 PCLK1 clock source

UART_CLOCKSOURCE_PLL2

PLL2Q clock source

UART_CLOCKSOURCE_HSI

HSI clock source

UART_CLOCKSOURCE_CSI

CSI clock source

UART_CLOCKSOURCE_LSE

LSE clock source

UART_CLOCKSOURCE_PLL3

PLL3Q clock source

UART_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 234 of file stm32h7xx_hal_uart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_InitTypeDef Struct Reference
UART Exported Types

UART Init Structure definition. More...

#include <stm32h7xx_hal_uart.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | HwFlowCtl
uint32_t | OverSampling
uint32_t | OneBitSampling
uint32_t | Prescaler
uint32_t | FIFOMode
uint32_t | TXFIFOThreshold
uint32_t | RXFIFOThreshold

Detailed Description

UART Init Structure definition.

Definition at line 65 of file stm32h7xx_hal_uart.h.

Field Documentation

uint32_t UART_InitTypeDef::BaudRate

This member configures the UART communication baud rate. The baud rate register is computed using the following formula:

  • If oversampling is 16 or in LIN mode, Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
  • If oversampling is 8, Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1

Definition at line 67 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::FIFOMode

Specifies if the FIFO mode will be used. This parameter can be a value of UART FIFO mode.

Definition at line 106 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::HwFlowCtl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of UART Hardware Flow Control.

Definition at line 92 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Init(), and UART_SetConfig().

uint32_t UART_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of UART Transfer Mode.

Definition at line 89 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::OneBitSampling

Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of UART One Bit Sampling Method.

Definition at line 99 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::OverSampling

Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8). This parameter can be a value of UART Over Sampling.

Definition at line 96 of file stm32h7xx_hal_uart.h.

Referenced by HAL_LIN_Init(), and UART_SetConfig().

uint32_t UART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of UART Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 82 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), UART_SetConfig(), and UART_Transmit_IT().

uint32_t UART_InitTypeDef::Prescaler

Specifies the prescaler value used to divide the UART clock source. This parameter can be a value of UART Prescaler.

Definition at line 103 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::RXFIFOThreshold

Specifies the RXFIFO threshold level. This parameter can be a value of UART RXFIFO threshold level.

Definition at line 112 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of UART Number of Stop Bits.

Definition at line 79 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::TXFIFOThreshold

Specifies the TXFIFO threshold level. This parameter can be a value of UART TXFIFO threshold level.

Definition at line 109 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of UART Word Length.

Definition at line 76 of file stm32h7xx_hal_uart.h.

Referenced by HAL_LIN_Init(), HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), UART_SetConfig(), and UART_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_uart.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART_AdvFeatureInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_AdvFeatureInitTypeDef Struct Reference
UART Exported Types

UART Advanced Features initalization structure definition. More...

#include <stm32h7xx_hal_uart.h>

Data Fields

uint32_t | AdvFeatureInit
uint32_t | TxPinLevelInvert
uint32_t | RxPinLevelInvert
uint32_t | DataInvert
uint32_t | Swap
uint32_t | OverrunDisable
uint32_t | DMADisableonRxError
uint32_t | AutoBaudRateEnable
uint32_t | AutoBaudRateMode
uint32_t | MSBFirst

Detailed Description

UART Advanced Features initalization structure definition.

Definition at line 120 of file stm32h7xx_hal_uart.h.

Field Documentation

uint32_t UART_AdvFeatureInitTypeDef::AdvFeatureInit

Specifies which advanced UART features is initialized. Several Advanced Features may be initialized at the same time . This parameter can be a value of UART Advanced Feature Initialization Type.

Definition at line 122 of file stm32h7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), and UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::AutoBaudRateEnable

Specifies whether auto Baud rate detection is enabled. This parameter can be a value of UART Advanced Feature Auto BaudRate Enable

Definition at line 145 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::AutoBaudRateMode

If auto Baud rate detection is enabled, specifies how the rate detection is carried out. This parameter can be a value of UART Advanced Feature AutoBaud Rate Mode.

Definition at line 148 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::DataInvert

Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). This parameter can be a value of UART Advanced Feature Binary Data Inversion.

Definition at line 132 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::DMADisableonRxError

Specifies whether the DMA is disabled in case of reception error. This parameter can be a value of UART Advanced Feature DMA Disable On Rx Error.

Definition at line 142 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::MSBFirst

Specifies whether MSB is sent first on UART line. This parameter can be a value of UART Advanced Feature MSB First.

Definition at line 152 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::OverrunDisable

Specifies whether the reception overrun detection is disabled. This parameter can be a value of UART Advanced Feature Overrun Disable.

Definition at line 139 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::RxPinLevelInvert

Specifies whether the RX pin active level is inverted. This parameter can be a value of UART Advanced Feature RX Pin Active Level Inversion.

Definition at line 129 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::Swap

Specifies whether TX and RX pins are swapped. This parameter can be a value of UART Advanced Feature RX TX Pins Swap.

Definition at line 136 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::TxPinLevelInvert

Specifies whether the TX pin active level is inverted. This parameter can be a value of UART Advanced Feature TX Pin Active Level Inversion.

Definition at line 126 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_uart.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_HandleTypeDef Struct Reference
UART Exported Types

UART handle Structure definition. More...

#include <stm32h7xx_hal_uart.h>

Data Fields

USART_TypeDef * | Instance
UART_InitTypeDef Init
UART_AdvFeatureInitTypeDef AdvancedInit
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | Mask
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_UART_StateTypeDef | gState
__IO HAL_UART_StateTypeDef | RxState
__IO uint32_t | ErrorCode

Detailed Description

UART handle Structure definition.

Definition at line 250 of file stm32h7xx_hal_uart.h.

Field Documentation

UART_AdvFeatureInitTypeDef UART_HandleTypeDef::AdvancedInit

UART Advanced Features initialization parameters

Definition at line 256 of file stm32h7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), and UART_AdvFeatureConfig().

__IO uint32_t UART_HandleTypeDef::ErrorCode

UART Error code

Definition at line 285 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_DeInit(), HAL_UART_GetError(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_CheckIdleState(), UART_DMAError(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

__IO HAL_UART_StateTypeDef UART_HandleTypeDef::gState

UART state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_UART_StateTypeDef

Definition at line 278 of file stm32h7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DeInit(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_GetState(), HAL_UART_Init(), HAL_UART_IRQHandler(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UARTEx_DisableStopMode(), HAL_UARTEx_EnableStopMode(), HAL_UARTEx_StopModeWakeUpSourceConfig(), UART_CheckIdleState(), UART_DMAError(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_EndTransmit_IT(), UART_EndTxTransfer(), UART_Transmit_IT(), and UART_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* UART_HandleTypeDef::hdmarx

UART Rx DMA Handle parameters

Definition at line 274 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DMAStop(), HAL_UART_IRQHandler(), HAL_UART_Receive_DMA(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

DMA_HandleTypeDef* UART_HandleTypeDef::hdmatx

UART Tx DMA Handle parameters

Definition at line 272 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DMAStop(), HAL_UART_Transmit_DMA(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

UART_InitTypeDef UART_HandleTypeDef::Init

UART communication parameters

Definition at line 254 of file stm32h7xx_hal_uart.h.

Referenced by HAL_LIN_Init(), HAL_UART_Init(), HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), UART_SetConfig(), and UART_Transmit_IT().

USART_TypeDef* UART_HandleTypeDef::Instance

UART registers base address

Definition at line 252 of file stm32h7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DeInit(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_Init(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UARTEx_DisableStopMode(), HAL_UARTEx_EnableStopMode(), HAL_UARTEx_StopModeWakeUpSourceConfig(), UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), UART_EndRxTransfer(), UART_EndTransmit_IT(), UART_EndTxTransfer(), UART_Receive_IT(), UART_SetConfig(), UART_Transmit_IT(), UART_WaitOnFlagUntilTimeout(), and UARTEx_Wakeup_AddressConfig().

HAL_LockTypeDef UART_HandleTypeDef::Lock

Locking object

Definition at line 276 of file stm32h7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

uint16_t UART_HandleTypeDef::Mask

UART Rx RDR register mask

Definition at line 270 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Receive(), and UART_Receive_IT().

uint8_t* UART_HandleTypeDef::pRxBuffPtr

Pointer to UART Rx transfer Buffer

Definition at line 264 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), and UART_Receive_IT().

uint8_t* UART_HandleTypeDef::pTxBuffPtr

Pointer to UART Tx transfer Buffer

Definition at line 258 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), and UART_Transmit_IT().

__IO HAL_UART_StateTypeDef UART_HandleTypeDef::RxState

UART state information related to Rx operations. This parameter can be a value of HAL_UART_StateTypeDef

Definition at line 282 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DeInit(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_GetState(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), UART_CheckIdleState(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_EndRxTransfer(), UART_Receive_IT(), and UART_WaitOnFlagUntilTimeout().

__IO uint16_t UART_HandleTypeDef::RxXferCount

UART Rx Transfer Counter

Definition at line 268 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_Receive(), HAL_UART_Receive_IT(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), and UART_Receive_IT().

uint16_t UART_HandleTypeDef::RxXferSize

UART Rx Transfer size

Definition at line 266 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Receive_DMA(), and HAL_UART_Receive_IT().

__IO uint16_t UART_HandleTypeDef::TxXferCount

UART Tx Transfer Counter

Definition at line 262 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMARxAbortCallback(), UART_DMATransmitCplt(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), and UART_Transmit_IT().

uint16_t UART_HandleTypeDef::TxXferSize

UART Tx Transfer size

Definition at line 260 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), and HAL_UART_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_uart.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Number of Stop Bits

Defines
UART Number of Stop Bits
UART Exported Constants

Defines

#define | UART_STOPBITS_0_5 USART_CR2_STOP_0
#define | UART_STOPBITS_1 ((uint32_t)0x00000000U)
#define | UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | UART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define UART_STOPBITS_0_5 USART_CR2_STOP_0

UART frame with 0.5 stop bit

Definition at line 301 of file stm32h7xx_hal_uart.h.

#define UART_STOPBITS_1 ((uint32_t)0x00000000U)

UART frame with 1 stop bit

Definition at line 302 of file stm32h7xx_hal_uart.h.

#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)

UART frame with 1.5 stop bits

Definition at line 303 of file stm32h7xx_hal_uart.h.

#define UART_STOPBITS_2 USART_CR2_STOP_1

UART frame with 2 stop bits

Definition at line 304 of file stm32h7xx_hal_uart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Parity

Defines
UART Parity
UART Exported Constants

Defines

#define | UART_PARITY_NONE ((uint32_t)0x00000000U)
#define | UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

Even parity

Definition at line 313 of file stm32h7xx_hal_uart.h.

#define UART_PARITY_NONE ((uint32_t)0x00000000U)

No parity

Definition at line 312 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), and UART_Transmit_IT().

#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Odd parity

Definition at line 314 of file stm32h7xx_hal_uart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Hardware Flow Control

Defines
UART Hardware Flow Control
UART Exported Constants

Defines

#define | UART_HWCONTROL_NONE ((uint32_t)0x00000000U)
#define | UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
#define | UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
#define | UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))

Define Documentation

#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)

Clear To Send

Definition at line 324 of file stm32h7xx_hal_uart.h.

#define UART_HWCONTROL_NONE ((uint32_t)0x00000000U)

No hardware control

Definition at line 322 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Init().

#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)

Request To Send

Definition at line 323 of file stm32h7xx_hal_uart.h.

#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))

Request and Clear To Send

Definition at line 325 of file stm32h7xx_hal_uart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Transfer Mode

Defines
UART Transfer Mode
UART Exported Constants

Defines

#define | UART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | UART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define UART_MODE_RX ((uint32_t)USART_CR1_RE)

RX mode

Definition at line 333 of file stm32h7xx_hal_uart.h.

#define UART_MODE_TX ((uint32_t)USART_CR1_TE)

TX mode

Definition at line 334 of file stm32h7xx_hal_uart.h.

#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

RX and TX mode

Definition at line 335 of file stm32h7xx_hal_uart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART State

Defines
UART State
UART Exported Constants

Defines

#define | UART_STATE_DISABLE ((uint32_t)0x00000000U)
#define | UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)

Define Documentation

#define UART_STATE_DISABLE ((uint32_t)0x00000000U)

UART disabled

Definition at line 343 of file stm32h7xx_hal_uart.h.

#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)

UART enabled

Definition at line 344 of file stm32h7xx_hal_uart.h.

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STM32H753xx HAL User Manual: UART Over Sampling

Defines
UART Over Sampling
UART Exported Constants

Defines

#define | UART_OVERSAMPLING_16 ((uint32_t)0x00000000U)
#define | UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)

Define Documentation

#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000U)

Oversampling by 16

Definition at line 352 of file stm32h7xx_hal_uart.h.

#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)

Oversampling by 8

Definition at line 353 of file stm32h7xx_hal_uart.h.

Referenced by HAL_LIN_Init(), and UART_SetConfig().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART One Bit Sampling Method

Defines
UART One Bit Sampling Method
UART Exported Constants

Defines

#define | UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000U)
#define | UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

Define Documentation

#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000U)

One-bit sampling disable

Definition at line 361 of file stm32h7xx_hal_uart.h.

#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

One-bit sampling enable

Definition at line 362 of file stm32h7xx_hal_uart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Prescaler

Defines
UART Prescaler
UART Exported Constants

Defines

#define | UART_PRESCALER_DIV1 ((uint32_t)0x00000000U)
#define | UART_PRESCALER_DIV2 ((uint32_t)0x00000001U)
#define | UART_PRESCALER_DIV4 ((uint32_t)0x00000002U)
#define | UART_PRESCALER_DIV6 ((uint32_t)0x00000003U)
#define | UART_PRESCALER_DIV8 ((uint32_t)0x00000004U)
#define | UART_PRESCALER_DIV10 ((uint32_t)0x00000005U)
#define | UART_PRESCALER_DIV12 ((uint32_t)0x00000006U)
#define | UART_PRESCALER_DIV16 ((uint32_t)0x00000007U)
#define | UART_PRESCALER_DIV32 ((uint32_t)0x00000008U)
#define | UART_PRESCALER_DIV64 ((uint32_t)0x00000009U)
#define | UART_PRESCALER_DIV128 ((uint32_t)0x0000000AU)
#define | UART_PRESCALER_DIV256 ((uint32_t)0x0000000BU)

Define Documentation

#define UART_PRESCALER_DIV1 ((uint32_t)0x00000000U)

UART clock /1

Definition at line 370 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV10 ((uint32_t)0x00000005U)

UART clock /10

Definition at line 375 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV12 ((uint32_t)0x00000006U)

UART clock /12

Definition at line 376 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV128 ((uint32_t)0x0000000AU)

UART clock /128

Definition at line 380 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV16 ((uint32_t)0x00000007U)

UART clock /16

Definition at line 377 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV2 ((uint32_t)0x00000001U)

UART clock /2

Definition at line 371 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV256 ((uint32_t)0x0000000BU)

UART clock /256

Definition at line 381 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV32 ((uint32_t)0x00000008U)

UART clock /32

Definition at line 378 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV4 ((uint32_t)0x00000002U)

UART clock /4

Definition at line 372 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV6 ((uint32_t)0x00000003U)

UART clock /6

Definition at line 373 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV64 ((uint32_t)0x00000009U)

UART clock /64

Definition at line 379 of file stm32h7xx_hal_uart.h.

#define UART_PRESCALER_DIV8 ((uint32_t)0x00000004U)

UART clock /8

Definition at line 374 of file stm32h7xx_hal_uart.h.

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STM32H753xx HAL User Manual: UART FIFO mode

Defines
UART FIFO mode
UART Exported Constants

UART FIFO mode. More...

Defines

#define | UART_FIFOMODE_DISABLE ((uint32_t)0x00000000U)
#define | UART_FIFOMODE_ENABLE ((uint32_t)USART_CR1_FIFOEN)

Detailed Description

UART FIFO mode.

Define Documentation

#define UART_FIFOMODE_DISABLE ((uint32_t)0x00000000U)

FIFO mode disable

Definition at line 391 of file stm32h7xx_hal_uart.h.

#define UART_FIFOMODE_ENABLE ((uint32_t)USART_CR1_FIFOEN)

FIFO mode enable

Definition at line 392 of file stm32h7xx_hal_uart.h.

Referenced by SMARTCARD_SetConfig(), and UART_SetConfig().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART TXFIFO threshold level

Defines
UART TXFIFO threshold level
UART Exported Constants

UART TXFIFO level. More...

Defines

#define | UART_TXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000U)
#define | UART_TXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_TXFTCFG_0)
#define | UART_TXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_TXFTCFG_1)
#define | UART_TXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1))
#define | UART_TXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_TXFTCFG_2)
#define | UART_TXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0))

Detailed Description

UART TXFIFO level.

Define Documentation

#define UART_TXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_TXFTCFG_1)

TXFIFO reaches 1/2 of its depth

Definition at line 403 of file stm32h7xx_hal_uart.h.

#define UART_TXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_TXFTCFG_0)

TXFIFO reaches 1/4 of its depth

Definition at line 402 of file stm32h7xx_hal_uart.h.

#define UART_TXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000U)

TXFIFO reaches 1/8 of its depth

Definition at line 401 of file stm32h7xx_hal_uart.h.

#define UART_TXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1))

TXFIFO reaches 3/4 of its depth

Definition at line 404 of file stm32h7xx_hal_uart.h.

#define UART_TXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_TXFTCFG_2)

TXFIFO reaches 7/8 of its depth

Definition at line 405 of file stm32h7xx_hal_uart.h.

#define UART_TXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0))

TXFIFO becomes empty

Definition at line 406 of file stm32h7xx_hal_uart.h.

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STM32H753xx HAL User Manual: UART RXFIFO threshold level

Defines
UART RXFIFO threshold level
UART Exported Constants

UART RXFIFO level. More...

Defines

#define | UART_RXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000U)
#define | UART_RXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_RXFTCFG_0)
#define | UART_RXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_RXFTCFG_1)
#define | UART_RXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1))
#define | UART_RXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_RXFTCFG_2)
#define | UART_RXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0))

Detailed Description

UART RXFIFO level.

Define Documentation

#define UART_RXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_RXFTCFG_1)

RXFIFO reaches 1/2 of its depth

Definition at line 417 of file stm32h7xx_hal_uart.h.

#define UART_RXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_RXFTCFG_0)

RXFIFO reaches 1/4 of its depth

Definition at line 416 of file stm32h7xx_hal_uart.h.

#define UART_RXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000U)

RXFIFO reaches 1/8 of its depth

Definition at line 415 of file stm32h7xx_hal_uart.h.

#define UART_RXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1))

RXFIFO reaches 3/4 of its depth

Definition at line 418 of file stm32h7xx_hal_uart.h.

#define UART_RXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_RXFTCFG_2)

RXFIFO reaches 7/8 of its depth

Definition at line 419 of file stm32h7xx_hal_uart.h.

#define UART_RXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0))

RXFIFO becomes full

Definition at line 420 of file stm32h7xx_hal_uart.h.

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STM32H753xx HAL User Manual: UART Advanced Feature AutoBaud Rate Mode

Defines
UART Advanced Feature AutoBaud Rate Mode
UART Exported Constants

Defines

#define | UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE)

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE)

Auto Baud rate detection on 0x55 frame detection

Definition at line 431 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1)

Auto Baud rate detection on 0x7F frame detection

Definition at line 430 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)

Auto Baud rate detection on falling edge

Definition at line 429 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x00000000U)

Auto Baud rate detection on start bit

Definition at line 428 of file stm32h7xx_hal_uart.h.

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STM32H753xx HAL User Manual: UART Receiver TimeOut

Defines
UART Receiver TimeOut
UART Exported Constants

Defines

#define | UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000U)
#define | UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)

Define Documentation

#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000U)

UART receiver timeout disable

Definition at line 439 of file stm32h7xx_hal_uart.h.

#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)

UART receiver timeout enable

Definition at line 440 of file stm32h7xx_hal_uart.h.

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STM32H753xx HAL User Manual: UART Local Interconnection Network mode

Defines
UART Local Interconnection Network mode
UART Exported Constants

Defines

#define | UART_LIN_DISABLE ((uint32_t)0x00000000U)
#define | UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN)

Define Documentation

#define UART_LIN_DISABLE ((uint32_t)0x00000000U)

Local Interconnect Network disable

Definition at line 448 of file stm32h7xx_hal_uart.h.

#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN)

Local Interconnect Network enable

Definition at line 449 of file stm32h7xx_hal_uart.h.

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STM32H753xx HAL User Manual: UART LIN Break Detection

Defines
UART LIN Break Detection
UART Exported Constants

Defines

#define | UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000U)
#define | UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)

Define Documentation

#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000U)

LIN 10-bit break detection length

Definition at line 457 of file stm32h7xx_hal_uart.h.

#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)

LIN 11-bit break detection length

Definition at line 458 of file stm32h7xx_hal_uart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART DMA Tx

Defines
UART DMA Tx
UART Exported Constants

Defines

#define | UART_DMA_TX_DISABLE ((uint32_t)0x00000000U)
#define | UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)

Define Documentation

#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000U)

UART DMA TX disabled

Definition at line 466 of file stm32h7xx_hal_uart.h.

#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)

UART DMA TX enabled

Definition at line 467 of file stm32h7xx_hal_uart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART DMA Rx

Defines
UART DMA Rx
UART Exported Constants

Defines

#define | UART_DMA_RX_DISABLE ((uint32_t)0x00000000U)
#define | UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)

Define Documentation

#define UART_DMA_RX_DISABLE ((uint32_t)0x00000000U)

UART DMA RX disabled

Definition at line 475 of file stm32h7xx_hal_uart.h.

#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)

UART DMA RX enabled

Definition at line 476 of file stm32h7xx_hal_uart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Half Duplex Selection

Defines
UART Half Duplex Selection
UART Exported Constants

Defines

#define | UART_HALF_DUPLEX_DISABLE ((uint32_t)0x00000000U)
#define | UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL)

Define Documentation

#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x00000000U)

UART half-duplex disabled

Definition at line 484 of file stm32h7xx_hal_uart.h.

#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL)

UART half-duplex enabled

Definition at line 485 of file stm32h7xx_hal_uart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART WakeUp Methods

Defines
UART WakeUp Methods
UART Exported Constants

Defines

#define | UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000U)
#define | UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)

Define Documentation

#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)

UART wake-up on address mark

Definition at line 494 of file stm32h7xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init().

#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000U)

UART wake-up on idle line

Definition at line 493 of file stm32h7xx_hal_uart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Request Parameters

Defines
UART Request Parameters
UART Exported Constants

Defines

#define | UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ)
#define | UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ)
#define | UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ)
#define | UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Define Documentation

#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ)

Auto-Baud Rate Request

Definition at line 502 of file stm32h7xx_hal_uart.h.

#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ)

Mute Mode Request

Definition at line 504 of file stm32h7xx_hal_uart.h.

Referenced by HAL_MultiProcessor_EnterMuteMode().

#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)

Receive Data flush Request

Definition at line 505 of file stm32h7xx_hal_uart.h.

Referenced by UART_Receive_IT().

#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ)

Send Break Request

Definition at line 503 of file stm32h7xx_hal_uart.h.

Referenced by HAL_LIN_SendBreak().

#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Transmit data flush Request

Definition at line 506 of file stm32h7xx_hal_uart.h.

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STM32H753xx HAL User Manual: UART Advanced Feature Initialization Type

Defines
UART Advanced Feature Initialization Type
UART Exported Constants

Defines

#define | UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001U)
#define | UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002U)
#define | UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004U)
#define | UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008U)
#define | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010U)
#define | UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020U)
#define | UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040U)
#define | UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080U)

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040U)

Auto Baud rate detection initialization

Definition at line 521 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004U)

Binary data inversion

Definition at line 517 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020U)

DMA disable on Reception Error

Definition at line 520 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080U)

Most significant bit sent/received first

Definition at line 522 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000U)

No advanced feature initialization

Definition at line 514 of file stm32h7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002U)

RX pin active level inversion

Definition at line 516 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010U)

RX overrun disable

Definition at line 519 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008U)

TX/RX pins swap

Definition at line 518 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001U)

TX pin active level inversion

Definition at line 515 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Advanced Feature TX Pin Active Level Inversion

Defines
UART Advanced Feature TX Pin Active Level Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)

Define Documentation

#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000U)

TX pin active level inversion disable

Definition at line 530 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)

TX pin active level inversion enable

Definition at line 531 of file stm32h7xx_hal_uart.h.

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STM32H753xx HAL User Manual: UART Advanced Feature RX Pin Active Level Inversion

Defines
UART Advanced Feature RX Pin Active Level Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)

Define Documentation

#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000U)

RX pin active level inversion disable

Definition at line 539 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)

RX pin active level inversion enable

Definition at line 540 of file stm32h7xx_hal_uart.h.

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STM32H753xx HAL User Manual: UART Advanced Feature Binary Data Inversion

Defines
UART Advanced Feature Binary Data Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)

Define Documentation

#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000U)

Binary data inversion disable

Definition at line 548 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)

Binary data inversion enable

Definition at line 549 of file stm32h7xx_hal_uart.h.

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STM32H753xx HAL User Manual: UART Advanced Feature RX TX Pins Swap

Defines
UART Advanced Feature RX TX Pins Swap
UART Exported Constants

Defines

#define | UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)

Define Documentation

#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000U)

TX/RX pins swap disable

Definition at line 557 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)

TX/RX pins swap enable

Definition at line 558 of file stm32h7xx_hal_uart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Advanced Feature Overrun Disable

Defines
UART Advanced Feature Overrun Disable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)

Define Documentation

#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)

RX overrun disable

Definition at line 567 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000U)

RX overrun enable

Definition at line 566 of file stm32h7xx_hal_uart.h.

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STM32H753xx HAL User Manual: UART Advanced Feature Auto BaudRate Enable

Defines
UART Advanced Feature Auto BaudRate Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN)

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000U)

RX Auto Baud rate detection enable

Definition at line 575 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN)

RX Auto Baud rate detection disable

Definition at line 576 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

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STM32H753xx HAL User Manual: UART Advanced Feature DMA Disable On Rx Error

Defines
UART Advanced Feature DMA Disable On Rx Error
UART Exported Constants

Defines

#define | UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)

Define Documentation

#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)

DMA disable on Reception Error

Definition at line 585 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000U)

DMA enable on Reception Error

Definition at line 584 of file stm32h7xx_hal_uart.h.

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STM32H753xx HAL User Manual: UART Advanced Feature MSB First

Defines
UART Advanced Feature MSB First
UART Exported Constants

Defines

#define | UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)

Define Documentation

#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000U)

Most significant bit sent/received first disable

Definition at line 593 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)

Most significant bit sent/received first enable

Definition at line 594 of file stm32h7xx_hal_uart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Advanced Feature Stop Mode Enable

Defines
UART Advanced Feature Stop Mode Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM)

Define Documentation

#define UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000U)

UART stop mode disable

Definition at line 602 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM)

UART stop mode enable

Definition at line 603 of file stm32h7xx_hal_uart.h.

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STM32H753xx HAL User Manual: UART Advanced Feature Mute Mode Enable

Defines
UART Advanced Feature Mute Mode Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME)

Define Documentation

#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000U)

UART mute mode disable

Definition at line 611 of file stm32h7xx_hal_uart.h.

#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME)

UART mute mode enable

Definition at line 612 of file stm32h7xx_hal_uart.h.

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STM32H753xx HAL User Manual: UART Address-matching LSB Position In CR2 Register

Defines
UART Address-matching LSB Position In CR2 Register
UART Exported Constants

Defines

#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24U)

Define Documentation

#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24U)

UART address-matching LSB position in CR2 register

Definition at line 620 of file stm32h7xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init(), and UARTEx_Wakeup_AddressConfig().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART WakeUp From Stop Selection

Defines
UART WakeUp From Stop Selection
UART Exported Constants

Defines

#define | UART_WAKEUP_ON_ADDRESS ((uint32_t)0x00000000U)
#define | UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1)
#define | UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS)
#define | UART_WAKEUP_ON_RXFIFO_THRESHOLD ((uint32_t)USART_CR3_RXFTIE)
#define | UART_WAKEUP_ON_RXFIFO_FULL ((uint32_t)USART_CR1_RXFFIE)
#define | UART_WAKEUP_ON_TXFIFO_THRESHOLD ((uint32_t)USART_CR3_TXFTIE)
#define | UART_WAKEUP_ON_TXFIFO_EMPTY ((uint32_t)USART_CR1_TXFEIE)

Define Documentation

#define UART_WAKEUP_ON_ADDRESS ((uint32_t)0x00000000U)

UART wake-up on address

Definition at line 628 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS)

UART wake-up on receive data register not empty

Definition at line 630 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

#define UART_WAKEUP_ON_RXFIFO_FULL ((uint32_t)USART_CR1_RXFFIE)

UART wake-up when the RXFIFO is full

Definition at line 632 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

#define UART_WAKEUP_ON_RXFIFO_THRESHOLD ((uint32_t)USART_CR3_RXFTIE)

UART wake-up when the RXFIFO reaches threshold

Definition at line 631 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1)

UART wake-up on start bit

Definition at line 629 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

#define UART_WAKEUP_ON_TXFIFO_EMPTY ((uint32_t)USART_CR1_TXFEIE)

UART wake-up when the TXFIFO is empty

Definition at line 634 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

#define UART_WAKEUP_ON_TXFIFO_THRESHOLD ((uint32_t)USART_CR3_TXFTIE)

UART wake-up when the TXFIFO reaches threshold

Definition at line 633 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART DriverEnable Polarity

Defines
UART DriverEnable Polarity
UART Exported Constants

Defines

#define | UART_DE_POLARITY_HIGH ((uint32_t)0x00000000U)
#define | UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP)

Define Documentation

#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000U)

Driver enable signal is active high

Definition at line 642 of file stm32h7xx_hal_uart.h.

#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP)

Driver enable signal is active low

Definition at line 643 of file stm32h7xx_hal_uart.h.

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STM32H753xx HAL User Manual: UART Driver Enable Assertion Time LSB Position In CR1 Register

Defines
UART Driver Enable Assertion Time LSB Position In CR1 Register
UART Exported Constants

Defines

#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21U)

Define Documentation

#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21U)

UART Driver Enable assertion time LSB position in CR1 register

Definition at line 651 of file stm32h7xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Driver Enable DeAssertion Time LSB Position In CR1 Register

Defines
UART Driver Enable DeAssertion Time LSB Position In CR1 Register
UART Exported Constants

Defines

#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16U)

Define Documentation

#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16U)

UART Driver Enable de-assertion time LSB position in CR1 register

Definition at line 659 of file stm32h7xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

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STM32H753xx HAL User Manual: UART Interruptions Flag Mask

Defines
UART Interruptions Flag Mask
UART Exported Constants

Defines

#define UART_IT_MASK ((uint32_t)0x001FU)

Define Documentation

#define UART_IT_MASK ((uint32_t)0x001FU)

UART interruptions flags mask

Definition at line 667 of file stm32h7xx_hal_uart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART polling-based communications time-out value

Defines
UART polling-based communications time-out value
UART Exported Constants

Defines

#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU

Define Documentation

#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU

UART polling-based communications time-out value

Definition at line 675 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig(), and UART_CheckIdleState().

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STM32H753xx HAL User Manual: UART Status Flags

Defines
UART Status Flags
UART Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | UART_FLAG_TXFT USART_ISR_TXFT
#define | UART_FLAG_RXFT USART_ISR_RXFT
#define | UART_FLAG_RXFF USART_ISR_RXFF
#define | UART_FLAG_TXFE USART_ISR_TXFE
#define | UART_FLAG_REACK USART_ISR_REACK
#define | UART_FLAG_TEACK USART_ISR_TEACK
#define | UART_FLAG_WUF USART_ISR_WUF
#define | UART_FLAG_RWU USART_ISR_RWU
#define | UART_FLAG_SBKF USART_ISR_SBKF
#define | UART_FLAG_CMF USART_ISR_CMF
#define | UART_FLAG_BUSY USART_ISR_BUSY
#define | UART_FLAG_ABRF USART_ISR_ABRF
#define | UART_FLAG_ABRE USART_ISR_ABRE
#define | UART_FLAG_RTOF USART_ISR_RTOF
#define | UART_FLAG_CTS USART_ISR_CTS
#define | UART_FLAG_CTSIF USART_ISR_CTSIF
#define | UART_FLAG_LBDF USART_ISR_LBDF
#define | UART_FLAG_TXE USART_ISR_TXE
#define | UART_FLAG_TXFNF USART_ISR_TXE
#define | UART_FLAG_TC USART_ISR_TC
#define | UART_FLAG_RXNE USART_ISR_RXNE
#define | UART_FLAG_RXFNE USART_ISR_RXNE
#define | UART_FLAG_IDLE USART_ISR_IDLE
#define | UART_FLAG_ORE USART_ISR_ORE
#define | UART_FLAG_NE USART_ISR_NE
#define | UART_FLAG_FE USART_ISR_FE
#define | UART_FLAG_PE USART_ISR_PE

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define UART_FLAG_ABRE USART_ISR_ABRE

UART uto Baud rate error

Definition at line 697 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_ABRF USART_ISR_ABRF

UART auto Baud rate flag

Definition at line 696 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_BUSY USART_ISR_BUSY

UART busy flag

Definition at line 695 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_CMF USART_ISR_CMF

UART character match flag

Definition at line 694 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_CTS USART_ISR_CTS

UART clear to send flag

Definition at line 699 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_CTSIF USART_ISR_CTSIF

UART clear to send interrupt flag

Definition at line 700 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_FE USART_ISR_FE

UART frame error

Definition at line 710 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_IDLE USART_ISR_IDLE

UART idle flag

Definition at line 707 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_LBDF USART_ISR_LBDF

UART LIN break detection flag

Definition at line 701 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_NE USART_ISR_NE

UART noise error

Definition at line 709 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_ORE USART_ISR_ORE

UART overrun error

Definition at line 708 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_PE USART_ISR_PE

UART parity error

Definition at line 711 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_REACK USART_ISR_REACK

UART receive enable acknowledge flag

Definition at line 689 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_RTOF USART_ISR_RTOF

UART receiver timeout flag

Definition at line 698 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_RWU USART_ISR_RWU

UART receiver wake-up from mute mode flag

Definition at line 692 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_RXFF USART_ISR_RXFF

UART RXFIFO Full flag

Definition at line 687 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_RXFNE USART_ISR_RXNE

UART RXFIFO not empty

Definition at line 706 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_RXFT USART_ISR_RXFT

UART RXFIFO threshold flag

Definition at line 686 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_RXNE USART_ISR_RXNE

UART read data register not empty

Definition at line 705 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Receive().

#define UART_FLAG_SBKF USART_ISR_SBKF

UART send break flag

Definition at line 693 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_TC USART_ISR_TC

UART transmission complete

Definition at line 704 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Transmit().

#define UART_FLAG_TEACK USART_ISR_TEACK

UART transmit enable acknowledge flag

Definition at line 690 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_TXE USART_ISR_TXE

UART transmit data register empty

Definition at line 702 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Transmit().

#define UART_FLAG_TXFE USART_ISR_TXFE

UART TXFIFO Empty flag

Definition at line 688 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_TXFNF USART_ISR_TXE

UART TXFIFO not full

Definition at line 703 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_TXFT USART_ISR_TXFT

UART TXFIFO threshold flag

Definition at line 685 of file stm32h7xx_hal_uart.h.

#define UART_FLAG_WUF USART_ISR_WUF

UART wake-up from stop mode flag

Definition at line 691 of file stm32h7xx_hal_uart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Interrupts Definition

Defines
UART Interrupts Definition
UART Exported Constants

Elements values convention: 000ZZZZZ0XXYYYYYb. More...

Defines

#define | UART_IT_PE ((uint32_t)0x0028U)
#define | UART_IT_TXE ((uint32_t)0x0727U)
#define | UART_IT_TC ((uint32_t)0x0626U)
#define | UART_IT_RXNE ((uint32_t)0x0525U)
#define | UART_IT_IDLE ((uint32_t)0x0424U)
#define | UART_IT_LBD ((uint32_t)0x0846U)
#define | UART_IT_CTS ((uint32_t)0x096AU)
#define | UART_IT_CM ((uint32_t)0x112EU)
#define | UART_IT_WUF ((uint32_t)0x1476U)
#define | UART_IT_RXFF ((uint16_t)0x183FU)
#define | UART_IT_TXFE ((uint16_t)0x173EU)
#define | UART_IT_RXFT ((uint16_t)0x1A7CU)
#define | UART_IT_TXFT ((uint16_t)0x1B77U)
#define | UART_IT_ERR ((uint32_t)0x0060U)
Elements values convention: 000000000XXYYYYYb.
#define | UART_IT_ORE ((uint32_t)0x0300U)
Elements values convention: 0000ZZZZ00000000b.
#define | UART_IT_NE ((uint32_t)0x0200U)
#define | UART_IT_FE ((uint32_t)0x0100U)

Detailed Description

Elements values convention: 000ZZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZZ : Flag position in the ISR register(5bits)

Define Documentation

#define UART_IT_CM ((uint32_t)0x112EU)

UART character match interruption

Definition at line 733 of file stm32h7xx_hal_uart.h.

#define UART_IT_CTS ((uint32_t)0x096AU)

UART CTS interruption

Definition at line 732 of file stm32h7xx_hal_uart.h.

#define UART_IT_ERR ((uint32_t)0x0060U)

Elements values convention: 000000000XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register UART error interruption

Definition at line 748 of file stm32h7xx_hal_uart.h.

#define UART_IT_FE ((uint32_t)0x0100U)

UART frame error interruption

Definition at line 755 of file stm32h7xx_hal_uart.h.

#define UART_IT_IDLE ((uint32_t)0x0424U)

UART idle interruption

Definition at line 730 of file stm32h7xx_hal_uart.h.

#define UART_IT_LBD ((uint32_t)0x0846U)

UART LIN break detection interruption

Definition at line 731 of file stm32h7xx_hal_uart.h.

#define UART_IT_NE ((uint32_t)0x0200U)

UART noise error interruption

Definition at line 754 of file stm32h7xx_hal_uart.h.

#define UART_IT_ORE ((uint32_t)0x0300U)

Elements values convention: 0000ZZZZ00000000b.

  • ZZZZ : Flag position in the ISR register(4bits) UART overrun error interruption

Definition at line 753 of file stm32h7xx_hal_uart.h.

#define UART_IT_PE ((uint32_t)0x0028U)

UART parity error interruption

Definition at line 726 of file stm32h7xx_hal_uart.h.

#define UART_IT_RXFF ((uint16_t)0x183FU)

Definition at line 735 of file stm32h7xx_hal_uart.h.

#define UART_IT_RXFT ((uint16_t)0x1A7CU)

Definition at line 737 of file stm32h7xx_hal_uart.h.

#define UART_IT_RXNE ((uint32_t)0x0525U)

UART read data register not empty interruption

Definition at line 729 of file stm32h7xx_hal_uart.h.

#define UART_IT_TC ((uint32_t)0x0626U)

UART transmission complete interruption

Definition at line 728 of file stm32h7xx_hal_uart.h.

#define UART_IT_TXE ((uint32_t)0x0727U)

UART transmit data register empty interruption

Definition at line 727 of file stm32h7xx_hal_uart.h.

#define UART_IT_TXFE ((uint16_t)0x173EU)

Definition at line 736 of file stm32h7xx_hal_uart.h.

#define UART_IT_TXFT ((uint16_t)0x1B77U)

Definition at line 738 of file stm32h7xx_hal_uart.h.

#define UART_IT_WUF ((uint32_t)0x1476U)

UART wake-up from stop mode interruption

Definition at line 734 of file stm32h7xx_hal_uart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Interruption Clear Flags

Defines
UART Interruption Clear Flags
UART Exported Constants

Defines

#define | UART_CLEAR_PEF USART_ICR_PECF
#define | UART_CLEAR_FEF USART_ICR_FECF
#define | UART_CLEAR_NEF USART_ICR_NCF
#define | UART_CLEAR_OREF USART_ICR_ORECF
#define | UART_CLEAR_IDLEF USART_ICR_IDLECF
#define | UART_CLEAR_TXFECF USART_ICR_TXFECF
#define | UART_CLEAR_TCF USART_ICR_TCCF
#define | UART_CLEAR_LBDF USART_ICR_LBDCF
#define | UART_CLEAR_CTSF USART_ICR_CTSCF
#define | UART_CLEAR_RTOF USART_ICR_RTOCF
#define | UART_CLEAR_CMF USART_ICR_CMCF
#define | UART_CLEAR_WUF USART_ICR_WUCF

Define Documentation

#define UART_CLEAR_CMF USART_ICR_CMCF

Character Match Clear Flag

Definition at line 773 of file stm32h7xx_hal_uart.h.

#define UART_CLEAR_CTSF USART_ICR_CTSCF

CTS Interrupt Clear Flag

Definition at line 771 of file stm32h7xx_hal_uart.h.

#define UART_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 764 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), and UART_DMATxAbortCallback().

#define UART_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 767 of file stm32h7xx_hal_uart.h.

#define UART_CLEAR_LBDF USART_ICR_LBDCF

LIN Break Detection Clear Flag

Definition at line 770 of file stm32h7xx_hal_uart.h.

#define UART_CLEAR_NEF USART_ICR_NCF

Noise detected Clear Flag

Definition at line 765 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), and UART_DMATxAbortCallback().

#define UART_CLEAR_OREF USART_ICR_ORECF

OverRun Error Clear Flag

Definition at line 766 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DMAResume(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), and UART_DMATxAbortCallback().

#define UART_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 763 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), and UART_DMATxAbortCallback().

#define UART_CLEAR_RTOF USART_ICR_RTOCF

Receiver Time Out Clear Flag

Definition at line 772 of file stm32h7xx_hal_uart.h.

#define UART_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 769 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Transmit_DMA().

#define UART_CLEAR_TXFECF USART_ICR_TXFECF

TXFIFO empty clear flag

Definition at line 768 of file stm32h7xx_hal_uart.h.

#define UART_CLEAR_WUF USART_ICR_WUCF

Wake Up from stop mode Clear Flag

Definition at line 774 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Exported Macros

Defines
UART Exported Macros
UART

Defines

#define | __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)
Reset UART handle states.
#define | __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)
Flush the UART Data registers.
#define | __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified UART pending flag.
#define | __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
Clear the UART PE pending flag.
#define | __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
Clear the UART FE pending flag.
#define | __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
Clear the UART NE pending flag.
#define | __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
Clear the UART ORE pending flag.
#define | __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
Clear the UART IDLE pending flag.
#define | __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
Clear the UART TX FIFO empty clear flag.
#define | __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified UART flag is set or not.
#define | __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified UART interrupt.
#define | __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified UART interrupt.
#define | __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
Check whether the specified UART interrupt has occurred or not.
#define | __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified UART interrupt source is enabled or not.
#define | __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified UART ISR flag, in setting the proper ICR register flag.
#define | __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
Set a specific UART request flag.
#define | __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the UART one bit sample method.
#define | __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the UART one bit sample method.
#define | __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART.
#define | __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART.
#define | __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)
Enable CTS flow control.
#define | __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)
Disable CTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)
Enable RTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)
Disable RTS flow control.

Define Documentation

#define __HAL_UART_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)

Clear the UART FE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 837 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified UART pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
__FLAG__,: specifies the flag to check. This parameter can be any combination of the following values:
  • UART_FLAG_WUF: Wake up from stop mode flag
  • UART_FLAG_CMF: Character match flag
  • UART_FLAG_RTOF: Receiver timeout flag
  • UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
  • UART_FLAG_LBD: LIN Break detection flag
  • UART_FLAG_TC: Transmission Complete flag
  • UART_FLAG_TXFE: TXFIFO Empty flag
  • UART_FLAG_IDLE: Idle Line detection flag
  • UART_FLAG_ORE: OverRun Error flag
  • UART_FLAG_NE: Noise Error flag
  • UART_FLAG_FE: Framing Error flag
  • UART_FLAG_PE: Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 825 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DMAResume(), HAL_UART_Transmit_DMA(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), and UART_DMATxAbortCallback().

#define __HAL_UART_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)

Clear the UART IDLE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 855 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified UART ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
__IT_CLEAR__,: specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt This parameter can be one of the following values:
  • UART_CLEAR_PEF: Parity Error Clear Flag
  • UART_CLEAR_FEF: Framing Error Clear Flag
  • UART_CLEAR_NEF: Noise detected Clear Flag
  • UART_CLEAR_OREF: OverRun Error Clear Flag
  • UART_CLEAR_IDLEF: IDLE line detected Clear Flag
  • UART_CLEAR_TCF: Transmission Complete Clear Flag
  • UART_CLEAR_LBDF: LIN Break Detection Clear Flag
  • UART_CLEAR_CTSF: CTS Interrupt Clear Flag
  • UART_CLEAR_RTOF: Receiver Time Out Clear Flag
  • UART_CLEAR_CMF: Character Match Clear Flag
  • .UART_CLEAR_WUF: Wake Up from stop mode Clear Flag
  • UART_CLEAR_TXFECF: TXFIFO empty Clear Flag
Return values:
None

Definition at line 1010 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define __HAL_UART_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)

Clear the UART NE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 843 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)

Clear the UART ORE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 849 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)

Clear the UART PE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 831 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_CLEAR_TXFECF ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)

Clear the UART TX FIFO empty clear flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 861 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable UART.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 1047 of file stm32h7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_DeInit(), HAL_UART_Init(), and HAL_UARTEx_StopModeWakeUpSourceConfig().

#define __HAL_UART_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))

Disable the specified UART interrupt.

Parameters:
__HANDLE__,: specifies the UART Handle.
__INTERRUPT__,: specifies the UART interrupt source to disable. This parameter can be one of the following values:
  • .UART_IT_RXFF : RXFIFO Full interrupt
  • UART_IT_TXFE : TXFIFO Empty interrupt
  • UART_IT_RXFT : RXFIFO threshold interrupt
  • UART_IT_TXFT : TXFIFO threshold interrupt
  • UART_IT_WUF: Wakeup from stop mode interrupt
  • UART_IT_CM: Character match interrupt
  • UART_IT_CTS: CTS change interrupt
  • UART_IT_LBD: LIN Break detection interrupt
  • UART_IT_TXE: Transmit Data Register empty interrupt
  • UART_IT_TC: Transmission complete interrupt
  • UART_IT_RXNE: Receive Data register not empty interrupt
  • UART_IT_IDLE: Idle line detection interrupt
  • UART_IT_PE: Parity Error interrupt
  • UART_IT_ERR: Error interrupt (Frame error, noise error, overrun error)
Return values:
None

Definition at line 940 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable UART.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 1041 of file stm32h7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_Init(), and HAL_UARTEx_StopModeWakeUpSourceConfig().

#define __HAL_UART_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))

Enable the specified UART interrupt.

Parameters:
__HANDLE__,: specifies the UART Handle.
__INTERRUPT__,: specifies the UART interrupt source to enable. This parameter can be one of the following values:
  • UART_IT_RXFF : RXFIFO Full interrupt
  • UART_IT_TXFE : TXFIFO Empty interrupt
  • .UART_IT_RXFT : RXFIFO threshold interrupt
  • UART_IT_TXFT : TXFIFO threshold interrupt
  • UART_IT_WUF: Wakeup from stop mode interrupt
  • UART_IT_CM: Character match interrupt
  • UART_IT_CTS: CTS change interrupt
  • UART_IT_LBD: LIN Break detection interrupt
  • UART_IT_TXE: Transmit Data Register empty interrupt
  • UART_IT_TC: Transmission complete interrupt
  • UART_IT_RXNE: Receive Data register not empty interrupt
  • UART_IT_IDLE: Idle line detection interrupt
  • .UART_IT_PE: Parity Error interrupt
  • UART_IT_ERR: Error interrupt (Frame error, noise error, overrun error)
Return values:
None

Definition at line 915 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                \
      SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
      SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
    }  while(0)

Flush the UART Data registers.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 801 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified UART flag is set or not.

Parameters:
__HANDLE__,: specifies the UART Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • UART_FLAG_TXFT: TXFIFO threshold flag
  • UART_FLAG_RXFT: RXFIFO threshold flag
  • UART_FLAG_RXFF: RXFIFO Full flag
  • UART_FLAG_TXFE: TXFIFO Empty flag
  • UART_FLAG_REACK: Receive enable acknowledge flag
  • UART_FLAG_TEACK: Transmit enable acknowledge flag
  • UART_FLAG_WUF: Wake up from stop mode flag
  • UART_FLAG_RWU: Receiver wake up flag (if the UART in mute mode)
  • UART_FLAG_SBKF: Send Break flag
  • UART_FLAG_CMF: Character match flag
  • UART_FLAG_BUSY: Busy flag
  • UART_FLAG_ABRF: Auto Baud rate detection flag
  • UART_FLAG_ABRE: Auto Baud rate detection error flag
  • UART_FLAG_RTOF: Receiver timeout flag
  • UART_FLAG_CTS: CTS Change flag
  • UART_FLAG_LBD: LIN Break detection flag
  • UART_FLAG_TXE: Transmit data register empty flag
  • UART_FLAG_TC: Transmission Complete flag
  • UART_FLAG_RXNE: Receive data register not empty flag
  • UART_FLAG_IDLE: Idle Line detection flag
  • UART_FLAG_ORE: OverRun Error flag
  • .UART_FLAG_NE: Noise Error flag
  • UART_FLAG_FE: Framing Error flag
  • UART_FLAG_PE: Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 893 of file stm32h7xx_hal_uart.h.

Referenced by UART_WaitOnFlagUntilTimeout().

#define __HAL_UART_GET_IT | ( | __HANDLE__,
 |  | __IT__
 | ) | ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))

Check whether the specified UART interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the UART Handle.
__IT__,: specifies the UART interrupt to check. This parameter can be one of the following values:
  • UART_IT_RXFF : RXFIFO Full interrupt
  • UART_IT_TXFE : TXFIFO Empty interrupt
  • UART_IT_RXFT : RXFIFO threshold interrupt
  • UART_IT_TXFT : TXFIFO threshold interrupt
  • UART_IT_WUF: Wakeup from stop mode interrupt
  • UART_IT_CM: Character match interrupt
  • UART_IT_CTS: CTS change interrupt
  • UART_IT_LBD: LIN Break detection interrupt
  • UART_IT_TXE: Transmit Data Register empty interrupt
  • UART_IT_TC: Transmission complete interrupt
  • UART_IT_RXNE: Receive Data register not empty interrupt
  • UART_IT_IDLE: Idle line detection interrupt
  • UART_IT_ORE: OverRun Error interrupt
  • UART_IT_NE: Noise Error interrupt
  • UART_IT_FE: Framing Error interrupt
  • UART_IT_PE: Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 966 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))

Check whether the specified UART interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the UART Handle.
__IT__,: specifies the UART interrupt source to check. This parameter can be one of the following values:
  • UART_IT_RXFF : RXFIFO Full interrupt
  • UART_IT_TXFE : TXFIFO Empty interrupt
  • UART_IT_RXFT : RXFIFO threshold interrupt
  • UART_IT_TXFT : TXFIFO threshold interrupt
  • UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
  • UART_IT_LBD: LIN Break detection interrupt
  • UART_IT_TXE: Transmit Data Register empty interrupt
  • UART_IT_TC: Transmission complete interrupt
  • UART_IT_RXNE: Receive Data register not empty interrupt
  • UART_IT_IDLE: Idle line detection interrupt
  • UART_IT_ORE: OverRun Error interrupt
  • UART_IT_NE: Noise Error interrupt
  • UART_IT_FE: Framing Error interrupt
  • UART_IT_PE: Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 988 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_CTS_DISABLE ( __HANDLE__ )
Value:
do{                                                       \
    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
  } while(0)

Disable CTS flow control.

Note:
This macro allows to disable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying CTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 1079 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_CTS_ENABLE ( __HANDLE__ )
Value:
do{                                                      \
    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
  } while(0)

Enable CTS flow control.

Note:
This macro allows to enable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying CTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 1061 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_RTS_DISABLE ( __HANDLE__ )
Value:
do{                                                      \
    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
  } while(0)

Disable RTS flow control.

Note:
This macro allows to disable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying RTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 1115 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_RTS_ENABLE ( __HANDLE__ )
Value:
do{                                                     \
    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
  } while(0)

Enable RTS flow control.

Note:
This macro allows to enable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying RTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 1097 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

Disable the UART one bit sample method.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 1035 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the UART one bit sample method.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 1029 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
                                                     } while(0)

Reset UART handle states.

Parameters:
__HANDLE__,: UART handle.
Return values:
None

Definition at line 793 of file stm32h7xx_hal_uart.h.

#define __HAL_UART_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))

Set a specific UART request flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
__REQ__,: specifies the request flag to set This parameter can be one of the following values:
  • UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request
  • UART_SENDBREAK_REQUEST: Send Break Request
  • UART_MUTE_MODE_REQUEST: Mute Mode Request
  • UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
  • UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
Return values:
None

Definition at line 1023 of file stm32h7xx_hal_uart.h.

Referenced by HAL_MultiProcessor_EnterMuteMode(), and UART_Receive_IT().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Private Variables

Variables
UART Private Variables
UART

Variables

static const uint16_t UARTPrescTable [12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}

Variable Documentation

const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256} [static]

Definition at line 1129 of file stm32h7xx_hal_uart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Private Macros

Defines
UART Private Macros
UART

Defines

#define | UART_DIV_LPUART(__PCLK__, __BAUD__, __PRESCALER__) ((((((uint64_t)(__PCLK__)/UARTPrescTable[(__PRESCALER__)])*256)) + ((__BAUD__)/2)) / (__BAUD__))
BRR division operation to set BRR register with LPUART.
#define | UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __PRESCALER__) (((((__PCLK__)/UARTPrescTable[(__PRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__))
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/UARTPrescTable[(__PRESCALER__)]) + ((__BAUD__)/2)) / (__BAUD__))
BRR division operation to set BRR register in 16-bit oversampling mode.
#define | UART_INSTANCE_LOWPOWER(__HANDLE__) (((__HANDLE__)->Instance == LPUART1) ? SET : RESET )
Check whether or not UART instance is Low Power UART.
#define | IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
Check UART Baud rate.
#define | IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART assertion time.
#define | IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART deassertion time.
#define | IS_UART_STOPBITS(__STOPBITS__)
Ensure that UART frame number of stop bits is valid.
#define | IS_LPUART_STOPBITS(__STOPBITS__)
Ensure that LPUART frame number of stop bits is valid.
#define | IS_LPUART_STOPBITS(__STOPBITS__)
Ensure that LPUART frame number of stop bits is valid.
#define | IS_UART_PARITY(__PARITY__)
Ensure that UART frame parity is valid.
#define | IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)
Ensure that UART hardware flow control is valid.
#define | IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
Ensure that UART communication mode is valid.
#define | IS_UART_STATE(__STATE__)
Ensure that UART state is valid.
#define | IS_UART_OVERSAMPLING(__SAMPLING__)
Ensure that UART oversampling is valid.
#define | IS_UART_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that UART frame sampling is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)
Ensure that UART auto Baud rate detection mode is valid.
#define | IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)
Ensure that UART receiver timeout setting is valid.
#define | IS_UART_LIN(__LIN__)
Ensure that UART LIN state is valid.
#define | IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__)
Ensure that UART LIN break detection length is valid.
#define | IS_UART_DMA_TX(__DMATX__)
Ensure that UART DMA TX state is valid.
#define | IS_UART_DMA_RX(__DMARX__)
Ensure that UART DMA RX state is valid.
#define | IS_UART_HALF_DUPLEX(__HDSEL__)
Ensure that UART half-duplex state is valid.
#define | IS_UART_WAKEUPMETHOD(__WAKEUP__)
Ensure that UART wake-up method is valid.
#define | IS_UART_REQUEST_PARAMETER(__PARAM__)
Ensure that UART request parameter is valid.
#define | IS_UART_ADVFEATURE_INIT(__INIT__)
Ensure that UART advanced features initialization is valid.
#define | IS_UART_ADVFEATURE_TXINV(__TXINV__)
Ensure that UART frame TX inversion setting is valid.
#define | IS_UART_ADVFEATURE_RXINV(__RXINV__)
Ensure that UART frame RX inversion setting is valid.
#define | IS_UART_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that UART frame data inversion setting is valid.
#define | IS_UART_ADVFEATURE_SWAP(__SWAP__)
Ensure that UART frame RX/TX pins swap setting is valid.
#define | IS_UART_OVERRUN(__OVERRUN__)
Ensure that UART frame overrun setting is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)
Ensure that UART auto Baud rate state is valid.
#define | IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that UART DMA enabling or disabling on error setting is valid.
#define | IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that UART frame MSB first setting is valid.
#define | IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__)
Ensure that UART stop mode state is valid.
#define | IS_UART_MUTE_MODE(__MUTE__)
Ensure that UART mute mode state is valid.
#define | IS_UART_WAKEUP_SELECTION(__WAKE__)
Ensure that UART wake-up selection is valid.
#define | IS_UART_DE_POLARITY(__POLARITY__)
Ensure that UART driver enable polarity is valid.
#define | IS_UART_PRESCALER(__PRESCALER__)
Ensure that UART Prescaler is valid.
#define | IS_UART_FIFO_MODE_STATE(__STATE__)
Ensure that UART FIFO mode is valid.
#define | IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that UART TXFIFO threshold level is valid.
#define | IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that UART RXFIFO threshold level is valid.

Define Documentation

#define IS_LPUART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == UART_STOPBITS_1) || \
                                          ((__STOPBITS__) == UART_STOPBITS_2))

Ensure that LPUART frame number of stop bits is valid.

Parameters:
__STOPBITS__,: LPUART frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 1455 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_LPUART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == UART_STOPBITS_1) || \
                                          ((__STOPBITS__) == UART_STOPBITS_2))

Ensure that LPUART frame number of stop bits is valid.

Parameters:
__STOPBITS__,: LPUART frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 1455 of file stm32h7xx_hal_uart.h.

#define IS_UART_ADVFEATURE_AUTOBAUDRATE ( __AUTOBAUDRATE__ )
Value:
(((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
                                                            ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))

Ensure that UART auto Baud rate state is valid.

Parameters:
__AUTOBAUDRATE__,: UART auto Baud rate state.
Return values:
SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)

Definition at line 1394 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE ( __MODE__ )
Value:
(((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))

Ensure that UART auto Baud rate detection mode is valid.

Parameters:
__MODE__,: UART auto Baud rate detection mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1262 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_DATAINV ( __DATAINV__ )
Value:
(((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
                                                 ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))

Ensure that UART frame data inversion setting is valid.

Parameters:
__DATAINV__,: UART frame data inversion setting.
Return values:
SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)

Definition at line 1370 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_DMAONRXERROR ( __DMA__ )
Value:
(((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
                                                   ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))

Ensure that UART DMA enabling or disabling on error setting is valid.

Parameters:
__DMA__,: UART DMA enabling or disabling on error setting.
Return values:
SET (__DMA__ is valid) or RESET (__DMA__ is invalid)

Definition at line 1402 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_INIT ( __INIT__ )
Value:
((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
                                                            UART_ADVFEATURE_TXINVERT_INIT          | \
                                                            UART_ADVFEATURE_RXINVERT_INIT          | \
                                                            UART_ADVFEATURE_DATAINVERT_INIT        | \
                                                            UART_ADVFEATURE_SWAP_INIT              | \
                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
                                                            UART_ADVFEATURE_MSBFIRST_INIT))

Ensure that UART advanced features initialization is valid.

Parameters:
__INIT__,: UART advanced features initialization.
Return values:
SET (__INIT__ is valid) or RESET (__INIT__ is invalid)

Definition at line 1339 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_MSBFIRST ( __MSBFIRST__ )
Value:
(((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
                                                   ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))

Ensure that UART frame MSB first setting is valid.

Parameters:
__MSBFIRST__,: UART frame MSB first setting.
Return values:
SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)

Definition at line 1410 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_RXINV ( __RXINV__ )
Value:
(((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
                                             ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))

Ensure that UART frame RX inversion setting is valid.

Parameters:
__RXINV__,: UART frame RX inversion setting.
Return values:
SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)

Definition at line 1362 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_STOPMODE ( __STOPMODE__ )
Value:
(((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
                                                   ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))

Ensure that UART stop mode state is valid.

Parameters:
__STOPMODE__,: UART stop mode state.
Return values:
SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)

Definition at line 1418 of file stm32h7xx_hal_uart.h.

#define IS_UART_ADVFEATURE_SWAP ( __SWAP__ )
Value:
(((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
                                           ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))

Ensure that UART frame RX/TX pins swap setting is valid.

Parameters:
__SWAP__,: UART frame RX/TX pins swap setting.
Return values:
SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)

Definition at line 1378 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_TXINV ( __TXINV__ )
Value:
(((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
                                             ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))

Ensure that UART frame TX inversion setting is valid.

Parameters:
__TXINV__,: UART frame TX inversion setting.
Return values:
SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)

Definition at line 1354 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ASSERTIONTIME ( __TIME__ ) ((__TIME__) <= 0x1FU)

Check UART assertion time.

Parameters:
__TIME__,: 5-bit value assertion time.
Return values:
Test result (TRUE or FALSE).

Definition at line 1180 of file stm32h7xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

#define IS_UART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 12500001U)

Check UART Baud rate.

Parameters:
__BAUDRATE__,: Baudrate specified by the user. The maximum Baud Rate is derived from the maximum clock on H7 (i.e. 100 MHz) divided by the smallest oversampling used on the USART (i.e. 8)
Return values:
SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)

Definition at line 1174 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_DE_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
                                              ((__POLARITY__) == UART_DE_POLARITY_LOW))

Ensure that UART driver enable polarity is valid.

Parameters:
__POLARITY__,: UART driver enable polarity.
Return values:
SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)

Definition at line 1447 of file stm32h7xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

#define IS_UART_DEASSERTIONTIME ( __TIME__ ) ((__TIME__) <= 0x1FU)

Check UART deassertion time.

Parameters:
__TIME__,: 5-bit value deassertion time.
Return values:
Test result (TRUE or FALSE).

Definition at line 1186 of file stm32h7xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

#define IS_UART_DMA_RX ( __DMARX__ )
Value:
(((__DMARX__) == UART_DMA_RX_DISABLE) || \
                                       ((__DMARX__) == UART_DMA_RX_ENABLE))

Ensure that UART DMA RX state is valid.

Parameters:
__DMARX__,: UART DMA RX state.
Return values:
SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)

Definition at line 1304 of file stm32h7xx_hal_uart.h.

#define IS_UART_DMA_TX ( __DMATX__ )
Value:
(((__DMATX__) == UART_DMA_TX_DISABLE) || \
                                       ((__DMATX__) == UART_DMA_TX_ENABLE))

Ensure that UART DMA TX state is valid.

Parameters:
__DMATX__,: UART DMA TX state.
Return values:
SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)

Definition at line 1296 of file stm32h7xx_hal_uart.h.

#define IS_UART_FIFO_MODE_STATE ( __STATE__ )
Value:
(((__STATE__) == UART_FIFOMODE_DISABLE ) || \
                                                ((__STATE__) == UART_FIFOMODE_ENABLE))

Ensure that UART FIFO mode is valid.

Parameters:
__STATE__,: UART FIFO mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 1481 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_HALF_DUPLEX ( __HDSEL__ )
Value:
(((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
                                            ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))

Ensure that UART half-duplex state is valid.

Parameters:
__HDSEL__,: UART half-duplex state.
Return values:
SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)

Definition at line 1312 of file stm32h7xx_hal_uart.h.

#define IS_UART_HARDWARE_FLOW_CONTROL ( __CONTROL__ )
Value:
(((__CONTROL__) == UART_HWCONTROL_NONE) || \
                                    ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
                                    ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
                                    ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))

Ensure that UART hardware flow control is valid.

Parameters:
__CONTROL__,: UART hardware flow control.
Return values:
SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)

Definition at line 1220 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_LIN ( __LIN__ )
Value:
(((__LIN__) == UART_LIN_DISABLE) || \
                                     ((__LIN__) == UART_LIN_ENABLE))

Ensure that UART LIN state is valid.

Parameters:
__LIN__,: UART LIN state.
Return values:
SET (__LIN__ is valid) or RESET (__LIN__ is invalid)

Definition at line 1280 of file stm32h7xx_hal_uart.h.

#define IS_UART_LIN_BREAK_DETECT_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
                                                     ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))

Ensure that UART LIN break detection length is valid.

Parameters:
__LENGTH__,: UART LIN break detection length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 1288 of file stm32h7xx_hal_uart.h.

Referenced by HAL_LIN_Init().

#define IS_UART_MODE ( __MODE__ ) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))

Ensure that UART communication mode is valid.

Parameters:
__MODE__,: UART communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1231 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_MUTE_MODE ( __MUTE__ )
Value:
(((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
                                           ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))

Ensure that UART mute mode state is valid.

Parameters:
__MUTE__,: UART mute mode state.
Return values:
SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)

Definition at line 1426 of file stm32h7xx_hal_uart.h.

#define IS_UART_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
                                            ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))

Ensure that UART frame sampling is valid.

Parameters:
__ONEBIT__,: UART frame sampling.
Return values:
SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

Definition at line 1254 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_OVERRUN ( __OVERRUN__ )
Value:
(((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
                                          ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))

Ensure that UART frame overrun setting is valid.

Parameters:
__OVERRUN__,: UART frame overrun setting.
Return values:
SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)

Definition at line 1386 of file stm32h7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_OVERSAMPLING ( __SAMPLING__ )
Value:
(((__SAMPLING__) == UART_OVERSAMPLING_16) || \
                                            ((__SAMPLING__) == UART_OVERSAMPLING_8))

Ensure that UART oversampling is valid.

Parameters:
__SAMPLING__,: UART oversampling.
Return values:
SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)

Definition at line 1246 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == UART_PARITY_NONE) || \
                                    ((__PARITY__) == UART_PARITY_EVEN) || \
                                    ((__PARITY__) == UART_PARITY_ODD))

Ensure that UART frame parity is valid.

Parameters:
__PARITY__,: UART frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 1211 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == UART_PRESCALER_DIV1) || \
                                          ((__PRESCALER__) == UART_PRESCALER_DIV2) || \
                                          ((__PRESCALER__) == UART_PRESCALER_DIV4) || \
                                          ((__PRESCALER__) == UART_PRESCALER_DIV6) || \
                                          ((__PRESCALER__) == UART_PRESCALER_DIV8) || \
                                          ((__PRESCALER__) == UART_PRESCALER_DIV10) || \
                                          ((__PRESCALER__) == UART_PRESCALER_DIV12) || \
                                          ((__PRESCALER__) == UART_PRESCALER_DIV16) || \
                                          ((__PRESCALER__) == UART_PRESCALER_DIV32) || \
                                          ((__PRESCALER__) == UART_PRESCALER_DIV64) || \
                                          ((__PRESCALER__) == UART_PRESCALER_DIV128) || \
                                          ((__PRESCALER__) == UART_PRESCALER_DIV256))

Ensure that UART Prescaler is valid.

Parameters:
__PRESCALER__,: UART Prescaler value.
Return values:
SET (__PRESCALER__ is valid) or RESET (__PRESCALER__ is invalid)

Definition at line 1463 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_RECEIVER_TIMEOUT ( __TIMEOUT__ )
Value:
(((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
                                               ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))

Ensure that UART receiver timeout setting is valid.

Parameters:
__TIMEOUT__,: UART receiver timeout setting.
Return values:
SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)

Definition at line 1272 of file stm32h7xx_hal_uart.h.

#define IS_UART_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
                                              ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
                                              ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
                                              ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
                                              ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))

Ensure that UART request parameter is valid.

Parameters:
__PARAM__,: UART request parameter.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 1328 of file stm32h7xx_hal_uart.h.

#define IS_UART_RXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
((((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8 ) || \
                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4 ) || \
                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2)  || \
                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4)  || \
                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8)) || \
                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))

Ensure that UART RXFIFO threshold level is valid.

Parameters:
__THRESHOLD__,: UART RXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 1501 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_STATE ( __STATE__ )
Value:
(((__STATE__) == UART_STATE_DISABLE) || \
                                  ((__STATE__) == UART_STATE_ENABLE))

Ensure that UART state is valid.

Parameters:
__STATE__,: UART state.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 1238 of file stm32h7xx_hal_uart.h.

#define IS_UART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == UART_STOPBITS_0_5) || \
                                        ((__STOPBITS__) == UART_STOPBITS_1)   || \
                                        ((__STOPBITS__) == UART_STOPBITS_1_5) || \
                                        ((__STOPBITS__) == UART_STOPBITS_2))

Ensure that UART frame number of stop bits is valid.

Parameters:
__STOPBITS__,: UART frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 1193 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_TXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
((((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8 ) || \
                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4 ) || \
                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2)  || \
                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4)  || \
                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8)) || \
                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))

Ensure that UART TXFIFO threshold level is valid.

Parameters:
__THRESHOLD__,: UART TXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 1489 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_WAKEUP_SELECTION ( __WAKE__ )
Value:
(((__WAKE__) == UART_WAKEUP_ON_ADDRESS           ) || \
                                            ((__WAKE__) == UART_WAKEUP_ON_STARTBIT          ) || \
                                            ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY ) || \
                                            ((__WAKE__) == UART_WAKEUP_ON_RXFIFO_THRESHOLD  ) || \
                                            ((__WAKE__) == UART_WAKEUP_ON_RXFIFO_FULL       ) || \
                                            ((__WAKE__) == UART_WAKEUP_ON_TXFIFO_THRESHOLD  ) || \
                                            ((__WAKE__) == UART_WAKEUP_ON_TXFIFO_EMPTY      ))

Ensure that UART wake-up selection is valid.

Parameters:
__WAKE__,: UART wake-up selection.
Return values:
SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)

Definition at line 1434 of file stm32h7xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

#define IS_UART_WAKEUPMETHOD ( __WAKEUP__ )
Value:
(((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
                                          ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))

Ensure that UART wake-up method is valid.

Parameters:
__WAKEUP__,: UART wake-up method .
Return values:
SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)

Definition at line 1320 of file stm32h7xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init().

#define UART_DIV_LPUART | ( | __PCLK__,
 |  | __BAUD__,
 |  | __PRESCALER__
 | ) | ((((((uint64_t)(__PCLK__)/UARTPrescTable[(__PRESCALER__)])*256)) + ((__BAUD__)/2)) / (__BAUD__))

BRR division operation to set BRR register with LPUART.

Parameters:
__PCLK__,: LPUART clock.
__BAUD__,: Baud rate set by the user.
__PRESCALER__,: UART prescaler value.
Return values:
Division result

Definition at line 1144 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_DIV_SAMPLING16 | ( | __PCLK__,
 |  | __BAUD__,
 |  | __PRESCALER__
 | ) | ((((__PCLK__)/UARTPrescTable[(__PRESCALER__)]) + ((__BAUD__)/2)) / (__BAUD__))

BRR division operation to set BRR register in 16-bit oversampling mode.

Parameters:
__PCLK__,: UART clock.
__BAUD__,: Baud rate set by the user.
__PRESCALER__,: UART prescaler value.
Return values:
Division result

Definition at line 1160 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_DIV_SAMPLING8 | ( | __PCLK__,
 |  | __BAUD__,
 |  | __PRESCALER__
 | ) | (((((__PCLK__)/UARTPrescTable[(__PRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__))

BRR division operation to set BRR register in 8-bit oversampling mode.

Parameters:
__PCLK__,: UART clock.
__BAUD__,: Baud rate set by the user.
__PRESCALER__,: UART prescaler value.
Return values:
Division result

Definition at line 1152 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_INSTANCE_LOWPOWER ( __HANDLE__ ) (((__HANDLE__)->Instance == LPUART1) ? SET : RESET )

Check whether or not UART instance is Low Power UART.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
SET (instance is LPUART) or RESET (instance isn't LPUART)

Definition at line 1166 of file stm32h7xx_hal_uart.h.

Referenced by UART_SetConfig().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UARTEx Private Functions

Functions
UARTEx Private Functions
UARTEx

Functions

static void UARTEx_Wakeup_AddressConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Initialize the UART wake-up from stop mode parameters when triggered by address detection.

Function Documentation

static void UARTEx_Wakeup_AddressConfig | ( | UART_HandleTypeDef * | huart,
 |  | UART_WakeUpTypeDef | WakeUpSelection
 | ) |  | [static]

Initialize the UART wake-up from stop mode parameters when triggered by address detection.

Parameters:
huart,: UART handle.
WakeUpSelection,: UART wake up from stop mode parameters.
Return values:
None

Definition at line 481 of file stm32h7xx_hal_uart_ex.c.

References UART_WakeUpTypeDef::Address, UART_WakeUpTypeDef::AddressLength, assert_param, UART_HandleTypeDef::Instance, IS_UART_ADDRESSLENGTH_DETECT, and UART_CR2_ADDRESS_LSB_POS.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
UARTEx Exported Functions

Extended Initialization and Configuration Functions. More...

Functions

HAL_StatusTypeDef HAL_RS485Ex_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Detailed Description

Extended Initialization and Configuration Functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
    in asynchronous mode.
      (+) For the asynchronous mode the parameters below can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
        (++) Hardware flow control
        (++) Receiver/transmitter modes
        (++) Over Sampling Method
        (++) One-Bit Sampling Method
      (+) For the asynchronous mode, the following advanced features can be configured as well:
        (++) TX and/or RX pin level inversion
        (++) data logical level inversion
        (++) RX and TX pins swap
        (++) RX overrun detection disabling
        (++) DMA disabling on RX error
        (++) MSB first on communication line
        (++) auto Baud rate detection
    [..]
    The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
     procedures (details for the procedures are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible UART formats are listed in the following table.

Table 1. UART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | UART frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_RS485Ex_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Polarity,
 |  | uint32_t | AssertionTime,
 |  | uint32_t | DeassertionTime
 | ) |  |

Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Parameters:
huart,: UART handle.
Polarity,: select the driver enable polarity. This parameter can be one of the following values:
  • UART_DE_POLARITY_HIGH: DE signal is active high
  • UART_DE_POLARITY_LOW: DE signal is active low
AssertionTime,: Driver Enable assertion time: 5-bit value defining the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate)
DeassertionTime,: Driver Enable deassertion time: 5-bit value defining the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate).
Return values:
HAL status

Definition at line 166 of file stm32h7xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Instance, IS_UART_ASSERTIONTIME, IS_UART_DE_POLARITY, IS_UART_DEASSERTIONTIME, UART_HandleTypeDef::Lock, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_CR1_DEAT_ADDRESS_LSB_POS, UART_CR1_DEDT_ADDRESS_LSB_POS, and UART_SetConfig().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
UARTEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_MultiProcessorEx_AddressLength_Set (UART_HandleTypeDef *huart, uint32_t AddressLength)
By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).
HAL_StatusTypeDef | HAL_UARTEx_StopModeWakeUpSourceConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Set Wakeup from Stop mode interrupt flag selection.
HAL_StatusTypeDef | HAL_UARTEx_EnableStopMode (UART_HandleTypeDef *huart)
Enable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableStopMode (UART_HandleTypeDef *huart)
Disable UART Stop Mode.
__weak void | HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..] This section provides the following functions:
     (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode
     (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality
     (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
         detection length to more than 4 bits for multiprocessor address mark wake up.
     (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
         trigger: address match, Start Bit detection or RXNE bit status.
     (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
     (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
     (+) HAL_UARTEx_WakeupCallback() called upon UART wakeup interrupt

Function Documentation

HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | AddressLength
 | ) |  |

By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).

Note:
Addresses detection lengths are: 6-bit address detection in 7-bit data mode, 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
Parameters:
huart,: UART handle.
AddressLength,: this parameter can be one of the following values:
  • UART_ADDRESS_DETECT_4B: 4-bit long address
  • UART_ADDRESS_DETECT_7B: 6-, 7- or 8-bit long address
Return values:
HAL status

Definition at line 274 of file stm32h7xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, UART_HandleTypeDef::Instance, IS_UART_ADDRESSLENGTH_DETECT, and UART_CheckIdleState().

HAL_StatusTypeDef HAL_UARTEx_DisableStopMode ( UART_HandleTypeDef * huart )

Disable UART Stop Mode.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 430 of file stm32h7xx_hal_uart_ex.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_UARTEx_EnableStopMode ( UART_HandleTypeDef * huart )

Enable UART Stop Mode.

Note:
The UART is able to wake up the MCU from Stop mode as long as UART clock is HSI or LSE.
Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 407 of file stm32h7xx_hal_uart_ex.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig | ( | UART_HandleTypeDef * | huart,
 |  | UART_WakeUpTypeDef | WakeUpSelection
 | ) |  |

Set Wakeup from Stop mode interrupt flag selection.

Parameters:
huart,: UART handle.
WakeUpSelection,: address match, Start Bit detection, RXNE bit status or RX/TX FIFO related event. This parameter can be one of the following values:
  • UART_WAKEUP_ON_ADDRESS
  • UART_WAKEUP_ON_STARTBIT
  • UART_WAKEUP_ON_READDATA_NONEMPTY
  • UART_WAKEUP_ON_RXFIFO_THRESHOLD
  • UART_WAKEUP_ON_RXFIFO_FULL
  • UART_WAKEUP_ON_TXFIFO_THRESHOLD
  • UART_WAKEUP_ON_TXFIFO_EMPTY
Return values:
HAL status

Definition at line 316 of file stm32h7xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, HAL_UART_TIMEOUT_VALUE, UART_HandleTypeDef::Instance, IS_UART_WAKEUP_SELECTION, UART_WaitOnFlagUntilTimeout(), UART_WAKEUP_ON_ADDRESS, UART_WAKEUP_ON_READDATA_NONEMPTY, UART_WAKEUP_ON_RXFIFO_FULL, UART_WAKEUP_ON_RXFIFO_THRESHOLD, UART_WAKEUP_ON_STARTBIT, UART_WAKEUP_ON_TXFIFO_EMPTY, UART_WAKEUP_ON_TXFIFO_THRESHOLD, UARTEx_Wakeup_AddressConfig(), and UART_WakeUpTypeDef::WakeUpEvent.

void HAL_UARTEx_WakeupCallback ( UART_HandleTypeDef * huart )

UART wakeup from Stop mode callback.

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 453 of file stm32h7xx_hal_uart_ex.c.

Referenced by HAL_UART_IRQHandler().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART_WakeUpTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_WakeUpTypeDef Struct Reference
UARTEx Exported Types

UART wake up from stop mode parameters. More...

#include <stm32h7xx_hal_uart_ex.h>

Data Fields

uint32_t | WakeUpEvent
uint16_t | AddressLength
uint8_t | Address

Detailed Description

UART wake up from stop mode parameters.

Definition at line 65 of file stm32h7xx_hal_uart_ex.h.

Field Documentation

uint8_t UART_WakeUpTypeDef::Address

UART/USART node address (7-bit long max).

Definition at line 75 of file stm32h7xx_hal_uart_ex.h.

Referenced by UARTEx_Wakeup_AddressConfig().

uint16_t UART_WakeUpTypeDef::AddressLength

Specifies whether the address is 4 or 7-bit long. This parameter can be a value of UART Extended WakeUp Address Length.

Definition at line 72 of file stm32h7xx_hal_uart_ex.h.

Referenced by UARTEx_Wakeup_AddressConfig().

uint32_t UART_WakeUpTypeDef::WakeUpEvent

Specifies which event will activat the Wakeup from Stop mode flag (WUF). This parameter can be a value of UART WakeUp From Stop Selection. If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must be filled up.

Definition at line 67 of file stm32h7xx_hal_uart_ex.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_uart_ex.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Word Length

Defines
UART Word Length
UARTEx Exported Constants

Defines

#define | UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define | UART_WORDLENGTH_8B ((uint32_t)0x00000000U)
#define | UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

Define Documentation

#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)

7-bit long UART frame

Definition at line 90 of file stm32h7xx_hal_uart_ex.h.

#define UART_WORDLENGTH_8B ((uint32_t)0x00000000U)

8-bit long UART frame

Definition at line 91 of file stm32h7xx_hal_uart_ex.h.

Referenced by HAL_LIN_Init().

#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

9-bit long UART frame

Definition at line 92 of file stm32h7xx_hal_uart_ex.h.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), and UART_Transmit_IT().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Extended WakeUp Address Length

Defines
UART Extended WakeUp Address Length
UARTEx Exported Constants

Defines

#define | UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000U)
#define | UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7)

Define Documentation

#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000U)

4-bit long wake-up address

Definition at line 100 of file stm32h7xx_hal_uart_ex.h.

#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7)

7-bit long wake-up address

Definition at line 101 of file stm32h7xx_hal_uart_ex.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UARTEx Private Macros

Defines
UARTEx Private Macros
UARTEx

Defines

#define | UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the UART clock source.
#define | UART_MASK_COMPUTATION(__HANDLE__)
Report the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_UART_WORD_LENGTH(__LENGTH__)
Ensure that UART frame length is valid.
#define | IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__)
Ensure that UART wake-up address length is valid.

Define Documentation

#define IS_UART_ADDRESSLENGTH_DETECT ( __ADDRESS__ )
Value:
(((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))

Ensure that UART wake-up address length is valid.

Parameters:
__ADDRESS__,: UART wake-up address length.
Return values:
SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)

Definition at line 439 of file stm32h7xx_hal_uart_ex.h.

Referenced by HAL_MultiProcessorEx_AddressLength_Set(), and UARTEx_Wakeup_AddressConfig().

#define IS_UART_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == UART_WORDLENGTH_7B) || \
                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \
                                         ((__LENGTH__) == UART_WORDLENGTH_9B))

Ensure that UART frame length is valid.

Parameters:
__LENGTH__,: UART frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 430 of file stm32h7xx_hal_uart_ex.h.

Referenced by UART_SetConfig().

#define UART_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the UART clock source.

Parameters:
__HANDLE__,: specifies the UART Handle.
__CLOCKSOURCE__,: output variable.
Return values:
UART clocking source, written in __CLOCKSOURCE__.

Definition at line 158 of file stm32h7xx_hal_uart_ex.h.

Referenced by UART_SetConfig().

#define UART_MASK_COMPUTATION ( __HANDLE__ )

Report the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Note:
If PCE = 1, the parity bit is not included in the data extracted by the reception API(). This masking operation is not carried out in the case of DMA transfers.
Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None,the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.

Definition at line 387 of file stm32h7xx_hal_uart_ex.h.

Referenced by HAL_UART_Receive(), and HAL_UART_Receive_IT().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART Private Constants

Defines
USART Private Constants
USART

Defines

#define | USART_DUMMY_DATA ((uint16_t) 0xFFFF)
#define | USART_TEACK_REACK_TIMEOUT ((uint32_t) 1000)
#define | USART_CR1_FIELDS
#define | USART_CR2_FIELDS
#define | USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))

Define Documentation

#define USART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
                                              USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8|\
                                              USART_CR1_FIFOEN ))

USART CR1 fields of parameters set by USART_SetConfig API

Definition at line 110 of file stm32h7xx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_CR2_FIELDS
Value:
((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL |USART_CR2_DIS_NSS|\
                                              USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP|\
                                              USART_CR2_SLVEN))

USART CR2 fields of parameters set by USART_SetConfig API

Definition at line 113 of file stm32h7xx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))

USART CR3 fields of parameters set by USART_SetConfig API

Definition at line 116 of file stm32h7xx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_DUMMY_DATA ((uint16_t) 0xFFFF)

USART transmitted dummy data

Definition at line 108 of file stm32h7xx_hal_usart.c.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), and USART_Receive_IT().

#define USART_TEACK_REACK_TIMEOUT ((uint32_t) 1000)

USART TX or RX enable acknowledge time-out value

Definition at line 109 of file stm32h7xx_hal_usart.c.

Referenced by USART_CheckIdleState().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
USART Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitialize the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
Initialize the USART MSP.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
DeInitialize the USART MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USART
    in asynchronous and in synchronous modes.
      (+) For the asynchronous mode only these parameters can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
        (++) USART polarity
        (++) USART phase
        (++) USART LastBit
        (++) Receiver/transmitter modes

    [..]
    The HAL_USART_Init() function follows the USART  synchronous configuration
    procedure (details for the procedure are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible USART formats are listed in the following table.

Table 1. USART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | USART frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_USART_DeInit ( USART_HandleTypeDef * husart )

DeInitialize the USART peripheral.

Parameters:
husart,: USART handle.
Return values:
HAL status

Definition at line 267 of file stm32h7xx_hal_usart.c.

References assert_param, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_MspDeInit(), HAL_USART_STATE_BUSY, HAL_USART_STATE_RESET, USART_HandleTypeDef::Instance, and USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USART_Init ( USART_HandleTypeDef * husart )

Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.

Parameters:
husart,: USART handle.
Return values:
HAL status

Definition at line 211 of file stm32h7xx_hal_usart.c.

References __HAL_USART_DISABLE, __HAL_USART_ENABLE, assert_param, HAL_USART_MspInit(), HAL_USART_STATE_BUSY, HAL_USART_STATE_RESET, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Lock, USART_InitTypeDef::SlaveMode, USART_HandleTypeDef::State, USART_CheckIdleState(), and USART_SetConfig().

void HAL_USART_MspDeInit ( USART_HandleTypeDef * husart )

DeInitialize the USART MSP.

Parameters:
husart,: USART handle.
Return values:
None

Definition at line 316 of file stm32h7xx_hal_usart.c.

Referenced by HAL_USART_DeInit().

void HAL_USART_MspInit ( USART_HandleTypeDef * husart )

Initialize the USART MSP.

Parameters:
husart,: USART handle.
Return values:
None

Definition at line 301 of file stm32h7xx_hal_usart.c.

Referenced by HAL_USART_Init().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
USART Exported Functions

USART Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_Abort (USART_HandleTypeDef *husart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_USART_Abort_IT (USART_HandleTypeDef *husart)
Abort ongoing transfers (Interrupt mode).
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
Handle USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callback.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callback.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callback.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callback.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callback.
__weak void | HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
USART Abort Complete callback.

Detailed Description

USART Transmit and Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..] This subsection provides a set of functions allowing to manage the USART synchronous
    data transfers.

    [..] The USART supports master mode only: it cannot receive or send data related to an input
         clock (SCLK is always an output).

    (#) There are two modes of transfer:
       (++) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode: The communication is performed using Interrupts
           or DMA, These API's return the HAL status.
           The end of the data processing will be indicated through the
           dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.
           The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or Receive process
           The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected

    (#) Blocking mode API's are :
        (++) HAL_USART_Transmit()in simplex mode
        (++) HAL_USART_Receive() in full duplex receive only
        (++) HAL_USART_TransmitReceive() in full duplex mode

    (#) Non-Blocking mode API's with Interrupt are :
        (++) HAL_USART_Transmit_IT()in simplex mode
        (++) HAL_USART_Receive_IT() in full duplex receive only
        (++) HAL_USART_TransmitReceive_IT()in full duplex mode
        (++) HAL_USART_IRQHandler()

    (#) No-Blocking mode API's  with DMA are :
        (++) HAL_USART_Transmit_DMA()in simplex mode
        (++) HAL_USART_Receive_DMA() in full duplex receive only
        (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
        (++) HAL_USART_DMAPause()
        (++) HAL_USART_DMAResume()
        (++) HAL_USART_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
        (++) HAL_USART_TxCpltCallback()
        (++) HAL_USART_RxCpltCallback()
        (++) HAL_USART_TxHalfCpltCallback()
        (++) HAL_USART_RxHalfCpltCallback()
        (++) HAL_USART_ErrorCallback()
        (++) HAL_USART_TxRxCpltCallback()

    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (+) HAL_USART_Abort()
        (+) HAL_USART_Abort_IT()

    (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
        (+) HAL_USART_AbortCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
           and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
           If user wants to abort it, Abort services should be called by user.
       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
           Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.

Function Documentation

HAL_StatusTypeDef HAL_USART_Abort ( USART_HandleTypeDef * husart )

Abort ongoing transfers (blocking mode).

Parameters:
husart USART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable USART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1241 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_USART_Abort_IT ( USART_HandleTypeDef * husart )

Abort ongoing transfers (Interrupt mode).

Parameters:
husart USART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable USART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1309 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_USART_AbortCpltCallback ( USART_HandleTypeDef * husart )

USART Abort Complete callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 1706 of file stm32h7xx_hal_usart.c.

Referenced by HAL_USART_Abort_IT(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

HAL_StatusTypeDef HAL_USART_DMAPause ( USART_HandleTypeDef * husart )

Pause the DMA Transfer.

Parameters:
husart,: USART handle.
Return values:
HAL status

Definition at line 1120 of file stm32h7xx_hal_usart.c.

References HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, USART_HandleTypeDef::Instance, and USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USART_DMAResume ( USART_HandleTypeDef * husart )

Resume the DMA Transfer.

Parameters:
husart,: USART handle.
Return values:
HAL status

Definition at line 1161 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, USART_HandleTypeDef::Instance, USART_HandleTypeDef::State, and USART_CLEAR_OREF.

HAL_StatusTypeDef HAL_USART_DMAStop ( USART_HandleTypeDef * husart )

Stop the DMA Transfer.

Parameters:
husart,: USART handle.
Return values:
HAL status

Definition at line 1199 of file stm32h7xx_hal_usart.c.

References HAL_DMA_Abort(), HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::State, and USART_EndTransfer().

void HAL_USART_ErrorCallback ( USART_HandleTypeDef * husart )

USART error callback.

Parameters:
husart,: USART handle.
Return values:
None

Definition at line 1691 of file stm32h7xx_hal_usart.c.

Referenced by HAL_USART_IRQHandler(), USART_DMAAbortOnError(), and USART_DMAError().

void HAL_USART_IRQHandler ( USART_HandleTypeDef * husart )

Handle USART interrupt request.

Parameters:
husart USART handle.
Return values:
None

Definition at line 1424 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_IT, USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_USART_ERROR_FE, HAL_USART_ERROR_NE, HAL_USART_ERROR_NONE, HAL_USART_ERROR_ORE, HAL_USART_ERROR_PE, HAL_USART_ERROR_UDR, HAL_USART_ErrorCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::State, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, USART_CLEAR_UDRCF, USART_DMAAbortOnError(), USART_EndTransfer(), USART_EndTransmit_IT(), USART_Receive_IT(), USART_Transmit_IT(), USART_TransmitReceive_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_USART_Receive | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Note:
To receive synchronous data, dummy data are simultaneously transmitted.
Parameters:
husart,: USART handle.
pRxData,: Pointer to data buffer.
Size,: Amount of data to be received.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 485 of file stm32h7xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_InitTypeDef::SlaveMode, USART_HandleTypeDef::State, USART_DUMMY_DATA, USART_FLAG_RXNE, USART_FLAG_TC, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_SLAVEMODE_DISABLE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_Receive_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Parameters:
husart,: USART handle.
pRxData,: pointer to data buffer.
Size,: amount of data to be received.
Note:
When the USART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
The USART DMA transmit channel must be configured in order to generate the clock for the slave.
Return values:
HAL status

Definition at line 955 of file stm32h7xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferSize, USART_InitTypeDef::SlaveMode, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferSize, USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxHalfCplt(), USART_SLAVEMODE_DISABLE, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_Receive_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Note:
To receive synchronous data, dummy data are simultaneously transmitted.
Parameters:
husart,: USART handle.
pRxData,: pointer to data buffer.
Size,: amount of data to be received.
Return values:
HAL status

Definition at line 763 of file stm32h7xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_InitTypeDef::SlaveMode, USART_HandleTypeDef::State, USART_DUMMY_DATA, USART_MASK_COMPUTATION, USART_SLAVEMODE_DISABLE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

void HAL_USART_RxCpltCallback ( USART_HandleTypeDef * husart )

Rx Transfer completed callback.

Parameters:
husart,: USART handle.
Return values:
None

Definition at line 1646 of file stm32h7xx_hal_usart.c.

Referenced by USART_DMAReceiveCplt(), and USART_Receive_IT().

void HAL_USART_RxHalfCpltCallback ( USART_HandleTypeDef * husart )

Rx Half Transfer completed callback.

Parameters:
husart,: USART handle.
Return values:
None

Definition at line 1661 of file stm32h7xx_hal_usart.c.

Referenced by USART_DMARxHalfCplt().

HAL_StatusTypeDef HAL_USART_Transmit | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Simplex send an amount of data in blocking mode.

Parameters:
husart,: USART handle.
pTxData,: Pointer to data buffer.
Size,: Amount of data to be sent.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 413 of file stm32h7xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, USART_FLAG_TC, USART_FLAG_TXE, USART_PARITY_NONE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_Transmit_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Parameters:
husart,: USART handle.
pTxData,: pointer to data buffer.
Size,: amount of data to be sent.
Return values:
HAL status

Definition at line 894 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, USART_CLEAR_TCF, USART_DMAError(), USART_DMATransmitCplt(), USART_DMATxHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_Transmit_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Parameters:
husart,: USART handle.
pTxData,: pointer to data buffer.
Size,: amount of data to be sent.
Return values:
HAL status

Definition at line 707 of file stm32h7xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, and USART_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_USART_TransmitReceive | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Full-Duplex Send and Receive an amount of data in blocking mode.

Parameters:
husart,: USART handle.
pTxData,: pointer to TX data buffer.
pRxData,: pointer to RX data buffer.
Size,: amount of data to be sent (same amount to be received).
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 572 of file stm32h7xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_InitTypeDef::SlaveMode, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, USART_FLAG_RXNE, USART_FLAG_TXE, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_SLAVEMODE_ENABLE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Transmit Receive an amount of data in non-blocking mode.

Parameters:
husart,: USART handle.
pTxData,: pointer to TX data buffer.
pRxData,: pointer to RX data buffer.
Size,: amount of data to be received/sent.
Note:
When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
Return values:
HAL status

Definition at line 1040 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferSize, USART_CLEAR_TCF, USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxHalfCplt(), USART_DMATransmitCplt(), USART_DMATxHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_TransmitReceive_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Send and Receive an amount of data in interrupt mode.

Parameters:
husart,: USART handle.
pTxData,: pointer to TX data buffer.
pRxData,: pointer to RX data buffer.
Size,: amount of data to be sent (same amount to be received).
Return values:
HAL status

Definition at line 833 of file stm32h7xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, and USART_MASK_COMPUTATION.

void HAL_USART_TxCpltCallback ( USART_HandleTypeDef * husart )

Tx Transfer completed callback.

Parameters:
husart,: USART handle.
Return values:
None

Definition at line 1616 of file stm32h7xx_hal_usart.c.

Referenced by USART_DMATransmitCplt(), and USART_EndTransmit_IT().

void HAL_USART_TxHalfCpltCallback ( USART_HandleTypeDef * husart )

Tx Half Transfer completed callback.

Parameters:
husart,: USART handle.
Return values:
None

Definition at line 1631 of file stm32h7xx_hal_usart.c.

Referenced by USART_DMATxHalfCplt().

void HAL_USART_TxRxCpltCallback ( USART_HandleTypeDef * husart )

Tx/Rx Transfers completed callback for the non-blocking process.

Parameters:
husart,: USART handle.
Return values:
None

Definition at line 1676 of file stm32h7xx_hal_usart.c.

Referenced by USART_DMAReceiveCplt(), and USART_TransmitReceive_IT().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
USART Exported Functions

USART Peripheral State and Error functions. More...

Functions

HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
Return the USART handle state.
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

USART Peripheral State and Error functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) Return the USART handle state
      (+) Return the USART handle error code

Function Documentation

uint32_t HAL_USART_GetError ( USART_HandleTypeDef * husart )

Return the USART error code.

Parameters:
husart : pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART.
Return values:
USART handle Error Code

Definition at line 1754 of file stm32h7xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode.

HAL_USART_StateTypeDef HAL_USART_GetState ( USART_HandleTypeDef * husart )

Return the USART handle state.

Parameters:
husart : pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART.
Return values:
USART handle state

Definition at line 1743 of file stm32h7xx_hal_usart.c.

References USART_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART Private Functions

Functions
USART Private Functions
USART

Functions

static void | USART_EndTransfer (USART_HandleTypeDef *husart)
End ongoing transfer on USART peripheral (following error detection or Transfer completion).
static void | USART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process complete callback.
static void | USART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process complete callback.
static void | USART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process half complete callback.
static void | USART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process half complete callback.
static void | USART_DMAError (DMA_HandleTypeDef *hdma)
DMA USART communication error callback.
static void | USART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | USART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | USART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | USART_WaitOnFlagUntilTimeout (USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle USART Communication Timeout.
static HAL_StatusTypeDef | USART_SetConfig (USART_HandleTypeDef *husart)
Configure the USART peripheral.
static HAL_StatusTypeDef | USART_CheckIdleState (USART_HandleTypeDef *husart)
Check the USART Idle State.
static HAL_StatusTypeDef | USART_Transmit_IT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_EndTransmit_IT (USART_HandleTypeDef *husart)
Wraps up transmission in non-blocking mode.
static HAL_StatusTypeDef | USART_Receive_IT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_TransmitReceive_IT (USART_HandleTypeDef *husart)
Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).

Function Documentation

static HAL_StatusTypeDef USART_CheckIdleState ( USART_HandleTypeDef * husart ) [static]

Check the USART Idle State.

Parameters:
husart,: USART handle.
Return values:
HAL status

Definition at line 2174 of file stm32h7xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, USART_HandleTypeDef::Instance, USART_HandleTypeDef::State, USART_TEACK_REACK_TIMEOUT, and USART_WaitOnFlagUntilTimeout().

Referenced by HAL_USART_Init().

static void USART_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma,: DMA handle.
Return values:
None

Definition at line 1921 of file stm32h7xx_hal_usart.c.

References HAL_USART_ErrorCallback(), __DMA_HandleTypeDef::Parent, USART_HandleTypeDef::RxXferCount, and USART_HandleTypeDef::TxXferCount.

Referenced by HAL_USART_IRQHandler().

static void USART_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA USART communication error callback.

Parameters:
hdma,: DMA handle.
Return values:
None

Definition at line 1901 of file stm32h7xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_DMA, HAL_USART_ErrorCallback(), HAL_USART_STATE_READY, __DMA_HandleTypeDef::Parent, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, and USART_EndTransfer().

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART receive process complete callback.

Parameters:
hdma,: DMA handle.
Return values:
None

Definition at line 1837 of file stm32h7xx_hal_usart.c.

References DMA_CIRCULAR, HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __DMA_HandleTypeDef::Init, USART_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __DMA_HandleTypeDef::Parent, USART_HandleTypeDef::RxXferCount, and USART_HandleTypeDef::State.

Referenced by HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA USART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1979 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, USART_HandleTypeDef::ErrorCode, HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_USART_Abort_IT().

static void USART_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART receive process half complete callback.

Parameters:
hdma : DMA handle.
Return values:
None

Definition at line 1889 of file stm32h7xx_hal_usart.c.

References HAL_USART_RxHalfCpltCallback(), and __DMA_HandleTypeDef::Parent.

Referenced by HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART transmit process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1791 of file stm32h7xx_hal_usart.c.

References DMA_CIRCULAR, HAL_USART_STATE_BUSY_TX, HAL_USART_TxCpltCallback(), __DMA_HandleTypeDef::Init, USART_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __DMA_HandleTypeDef::Parent, USART_HandleTypeDef::State, and USART_HandleTypeDef::TxXferCount.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA USART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1938 of file stm32h7xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, USART_HandleTypeDef::ErrorCode, HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_USART_Abort_IT().

static void USART_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART transmit process half complete callback.

Parameters:
hdma : DMA handle.
Return values:
None

Definition at line 1825 of file stm32h7xx_hal_usart.c.

References HAL_USART_TxHalfCpltCallback(), and __DMA_HandleTypeDef::Parent.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_EndTransfer ( USART_HandleTypeDef * husart ) [static]

End ongoing transfer on USART peripheral (following error detection or Transfer completion).

Parameters:
husart USART handle.
Return values:
None

Definition at line 1776 of file stm32h7xx_hal_usart.c.

References HAL_USART_STATE_READY, USART_HandleTypeDef::Instance, and USART_HandleTypeDef::State.

Referenced by HAL_USART_DMAStop(), HAL_USART_IRQHandler(), and USART_DMAError().

static HAL_StatusTypeDef USART_EndTransmit_IT ( USART_HandleTypeDef * husart ) [static]

Wraps up transmission in non-blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status

Definition at line 2271 of file stm32h7xx_hal_usart.c.

References HAL_USART_STATE_READY, HAL_USART_TxCpltCallback(), USART_HandleTypeDef::Instance, and USART_HandleTypeDef::State.

Referenced by HAL_USART_IRQHandler().

static HAL_StatusTypeDef USART_Receive_IT ( USART_HandleTypeDef * husart ) [static]

Simplex receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Receive_IT().
Parameters:
husart,: USART handle
Return values:
HAL status

Definition at line 2295 of file stm32h7xx_hal_usart.c.

References HAL_USART_RxCpltCallback(), HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_InitTypeDef::SlaveMode, USART_HandleTypeDef::State, USART_DUMMY_DATA, USART_PARITY_NONE, USART_SLAVEMODE_DISABLE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_IRQHandler().

static HAL_StatusTypeDef USART_SetConfig ( USART_HandleTypeDef * husart ) [static]

Configure the USART peripheral.

Parameters:
husart,: USART handle.
Return values:
HAL status

Definition at line 2053 of file stm32h7xx_hal_usart.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_HSI_DIVIDER, assert_param, USART_InitTypeDef::BaudRate, USART_InitTypeDef::CLKLastBit, USART_InitTypeDef::CLKPhase, USART_InitTypeDef::CLKPolarity, CSI_VALUE, USART_InitTypeDef::FIFOMode, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCCEx_GetPLL2ClockFreq(), HAL_RCCEx_GetPLL3ClockFreq(), HSI_VALUE, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, IS_USART_BAUDRATE, IS_USART_FIFO_MODE_STATE, IS_USART_LASTBIT, IS_USART_MODE, IS_USART_NSS, IS_USART_PARITY, IS_USART_PHASE, IS_USART_POLARITY, IS_USART_PRESCALER, IS_USART_RXFIFO_THRESHOLD, IS_USART_SLAVEMODE, IS_USART_STOPBITS, IS_USART_TXFIFO_THRESHOLD, IS_USART_WORD_LENGTH, LSE_VALUE, USART_InitTypeDef::Mode, USART_InitTypeDef::NSS, USART_InitTypeDef::Parity, PLL2_ClocksTypeDef::PLL2_Q_Frequency, PLL3_ClocksTypeDef::PLL3_Q_Frequency, USART_InitTypeDef::Prescaler, RCC_FLAG_HSIDIV, USART_InitTypeDef::RXFIFOThreshold, USART_InitTypeDef::SlaveMode, USART_InitTypeDef::StopBits, USART_InitTypeDef::TXFIFOThreshold, USART_CLOCK_ENABLE, USART_CLOCKSOURCE_CSI, USART_CLOCKSOURCE_D2PCLK1, USART_CLOCKSOURCE_D2PCLK2, USART_CLOCKSOURCE_HSI, USART_CLOCKSOURCE_LSE, USART_CLOCKSOURCE_PLL2, USART_CLOCKSOURCE_PLL3, USART_CLOCKSOURCE_UNDEFINED, USART_CR1_FIELDS, USART_CR2_FIELDS, USART_CR3_FIELDS, USART_DIV_SAMPLING8, USART_FIFOMODE_ENABLE, USART_GETCLOCKSOURCE, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_Init().

static HAL_StatusTypeDef USART_Transmit_IT ( USART_HandleTypeDef * husart ) [static]

Simplex send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Transmit_IT().
The USART errors are not managed to avoid the overrun error.
Parameters:
husart,: USART handle.
Return values:
HAL status

Definition at line 2222 of file stm32h7xx_hal_usart.c.

References USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::TxXferCount, USART_PARITY_NONE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_IRQHandler().

static HAL_StatusTypeDef USART_TransmitReceive_IT ( USART_HandleTypeDef * husart ) [static]

Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_TransmitReceive_IT().
Parameters:
husart,: USART handle.
Return values:
HAL status

Definition at line 2343 of file stm32h7xx_hal_usart.c.

References __HAL_USART_GET_FLAG, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_FLAG_RXNE, USART_FLAG_TXE, USART_PARITY_NONE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_IRQHandler().

static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle USART Communication Timeout.

Parameters:
husart,: USART handle.
Flag,: specifies the USART flag to check.
Status,: the Flag status (SET or RESET).
Tickstart,: tick start value.
Timeout,: timeout duration.
Return values:
HAL status

Definition at line 2021 of file stm32h7xx_hal_usart.c.

References __HAL_USART_GET_FLAG, HAL_GetTick(), HAL_USART_STATE_READY, USART_HandleTypeDef::Instance, and USART_HandleTypeDef::State.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), and USART_CheckIdleState().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART Exported Types

Data Structures | Enumerations
USART Exported Types
USART

Data Structures

struct | USART_InitTypeDef
USART Init Structure definition. More...
struct | USART_HandleTypeDef
USART handle Structure definition. More...

Enumerations

enum HAL_USART_StateTypeDef {
HAL_USART_STATE_RESET = 0x00U, HAL_USART_STATE_READY = 0x01U, HAL_USART_STATE_BUSY = 0x02U, HAL_USART_STATE_BUSY_TX = 0x12U,
HAL_USART_STATE_BUSY_RX = 0x22U, HAL_USART_STATE_BUSY_TX_RX = 0x32U, HAL_USART_STATE_TIMEOUT = 0x03U, HAL_USART_STATE_ERROR = 0x04U
}
HAL USART State structures definition. More...
enum HAL_USART_ErrorTypeDef {
HAL_USART_ERROR_NONE = 0x00U, HAL_USART_ERROR_PE = 0x01U, HAL_USART_ERROR_NE = 0x02U, HAL_USART_ERROR_FE = 0x04U,
HAL_USART_ERROR_ORE = 0x08U, HAL_USART_ERROR_DMA = 0x10U, HAL_USART_ERROR_UDR = 0x11U
}
HAL USART Error Code structure definition. More...
enum USART_ClockSourceTypeDef {
USART_CLOCKSOURCE_D2PCLK1 = 0x00U, USART_CLOCKSOURCE_D2PCLK2 = 0x01U, USART_CLOCKSOURCE_D3PCLK1 = 0x02U, USART_CLOCKSOURCE_PLL2 = 0x04U,
USART_CLOCKSOURCE_HSI = 0x08U, USART_CLOCKSOURCE_CSI = 0x10U, USART_CLOCKSOURCE_LSE = 0x20U, USART_CLOCKSOURCE_PLL3 = 0x40U,
USART_CLOCKSOURCE_UNDEFINED = 0x80U
}
USART clock sources definitions. More...

Enumeration Type Documentation

enum HAL_USART_ErrorTypeDef

HAL USART Error Code structure definition.

Enumerator:
HAL_USART_ERROR_NONE

No error

HAL_USART_ERROR_PE

Parity error

HAL_USART_ERROR_NE

Noise error

HAL_USART_ERROR_FE

frame error

HAL_USART_ERROR_ORE

Overrun error

HAL_USART_ERROR_DMA

DMA transfer error

HAL_USART_ERROR_UDR

SPI UnderRun error

Definition at line 136 of file stm32h7xx_hal_usart.h.

enum HAL_USART_StateTypeDef

HAL USART State structures definition.

Enumerator:
HAL_USART_STATE_RESET

Peripheral is not initialized

HAL_USART_STATE_READY

Peripheral Initialized and ready for use

HAL_USART_STATE_BUSY

an internal process is ongoing

HAL_USART_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_USART_STATE_BUSY_RX

Data Reception process is ongoing

HAL_USART_STATE_BUSY_TX_RX

Data Transmission Reception process is ongoing

HAL_USART_STATE_TIMEOUT

Timeout state

HAL_USART_STATE_ERROR

Error

Definition at line 121 of file stm32h7xx_hal_usart.h.

enum USART_ClockSourceTypeDef

USART clock sources definitions.

Enumerator:
USART_CLOCKSOURCE_D2PCLK1

Domain2 PCLK1 clock source

USART_CLOCKSOURCE_D2PCLK2

Domain2 PCLK2 clock source

USART_CLOCKSOURCE_D3PCLK1

Domain3 PCLK1 clock source

USART_CLOCKSOURCE_PLL2

PLL2Q clock source

USART_CLOCKSOURCE_HSI

HSI clock source

USART_CLOCKSOURCE_CSI

CSI clock source

USART_CLOCKSOURCE_LSE

LSE clock source

USART_CLOCKSOURCE_PLL3

PLL3Q clock source

USART_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 150 of file stm32h7xx_hal_usart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
USART_InitTypeDef Struct Reference
USART Exported Types

USART Init Structure definition. More...

#include <stm32h7xx_hal_usart.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | CLKLastBit
uint32_t | Prescaler
uint32_t | NSS
uint32_t | SlaveMode
uint32_t | FIFOMode
uint32_t | TXFIFOThreshold
uint32_t | RXFIFOThreshold

Detailed Description

USART Init Structure definition.

Definition at line 65 of file stm32h7xx_hal_usart.h.

Field Documentation

uint32_t USART_InitTypeDef::BaudRate

This member configures the Usart communication baud rate. The baud rate is computed using the following formula: Baud Rate Register = ((PCLKx) / ((husart->Init.BaudRate)))

Definition at line 67 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKLastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of USART Last Bit

Definition at line 93 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of USART Clock Phase

Definition at line 90 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKPolarity

Specifies the steady state of the serial clock. This parameter can be a value of USART Clock Polarity

Definition at line 87 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::FIFOMode

Specifies if the FIFO mode will be used. This parameter can be a value of USART FIFO mode

Definition at line 107 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of USART Mode

Definition at line 84 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::NSS

Specifies whether the NSS signal is managed by hardware (DIS_NSS pin) or by software . This parameter can be a value of USART Slave Select Management

Definition at line 100 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of USART Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 77 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

uint32_t USART_InitTypeDef::Prescaler

Specifies the prescaler value used to divide the USART clock source. This parameter can be a value of USART Prescaler

Definition at line 97 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::RXFIFOThreshold

Specifies the RXFIFO threshold level. This parameter can be a value of USART RXFIFO threshold level

Definition at line 113 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::SlaveMode

Enable/Disable UART SPI Slave Mode. This parameter can be a value of USART Synchronous Slave mode enable

Definition at line 104 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Init(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), USART_Receive_IT(), and USART_SetConfig().

uint32_t USART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of USART Number of Stop Bits

Definition at line 74 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::TXFIFOThreshold

Specifies the TXFIFO threshold level. This parameter can be a value of USART TXFIFO threshold level

Definition at line 110 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of USARTEx Word Length

Definition at line 71 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_usart.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
USART_HandleTypeDef Struct Reference
USART Exported Types

USART handle Structure definition. More...

#include <stm32h7xx_hal_usart.h>

Data Fields

USART_TypeDef * | Instance
USART_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | Mask
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_USART_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

USART handle Structure definition.

Definition at line 167 of file stm32h7xx_hal_usart.h.

Field Documentation

__IO uint32_t USART_HandleTypeDef::ErrorCode

USART Error code

Definition at line 195 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_GetError(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_CheckIdleState(), USART_DMAError(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

DMA_HandleTypeDef* USART_HandleTypeDef::hdmarx

USART Rx DMA Handle parameters

Definition at line 189 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAStop(), HAL_USART_IRQHandler(), HAL_USART_Receive_DMA(), HAL_USART_TransmitReceive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

DMA_HandleTypeDef* USART_HandleTypeDef::hdmatx

USART Tx DMA Handle parameters

Definition at line 187 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAStop(), HAL_USART_IRQHandler(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

USART_InitTypeDef USART_HandleTypeDef::Init

USART communication parameters

Definition at line 171 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Init(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

USART_TypeDef* USART_HandleTypeDef::Instance

USART registers base address

Definition at line 169 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_DMAPause(), HAL_USART_DMAResume(), HAL_USART_DMAStop(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_CheckIdleState(), USART_DMAReceiveCplt(), USART_DMATransmitCplt(), USART_EndTransfer(), USART_EndTransmit_IT(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

HAL_LockTypeDef USART_HandleTypeDef::Lock

Locking object

Definition at line 191 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Init().

uint16_t USART_HandleTypeDef::Mask

USART Rx RDR register mask

Definition at line 185 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_TransmitReceive(), USART_Receive_IT(), and USART_TransmitReceive_IT().

uint8_t* USART_HandleTypeDef::pRxBuffPtr

Pointer to USART Rx transfer Buffer

Definition at line 179 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_Receive_IT(), and USART_TransmitReceive_IT().

uint8_t* USART_HandleTypeDef::pTxBuffPtr

Pointer to USART Tx transfer Buffer

Definition at line 173 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

__IO uint16_t USART_HandleTypeDef::RxXferCount

USART Rx Transfer Counter

Definition at line 183 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), USART_Receive_IT(), and USART_TransmitReceive_IT().

uint16_t USART_HandleTypeDef::RxXferSize

USART Rx Transfer size

Definition at line 181 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

__IO HAL_USART_StateTypeDef USART_HandleTypeDef::State

USART communication state

Definition at line 193 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_DMAPause(), HAL_USART_DMAResume(), HAL_USART_DMAStop(), HAL_USART_GetState(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_CheckIdleState(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxAbortCallback(), USART_DMATransmitCplt(), USART_DMATxAbortCallback(), USART_EndTransfer(), USART_EndTransmit_IT(), USART_Receive_IT(), USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

__IO uint16_t USART_HandleTypeDef::TxXferCount

USART Tx Transfer Counter

Definition at line 177 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMARxAbortCallback(), USART_DMATransmitCplt(), USART_DMATxAbortCallback(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

uint16_t USART_HandleTypeDef::TxXferSize

USART Tx Transfer size

Definition at line 175 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_usart.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART Number of Stop Bits

Defines
USART Number of Stop Bits
USART Exported Constants

Defines

#define | USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define | USART_STOPBITS_1 ((uint32_t)0x00000000U)
#define | USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
#define | USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)

Define Documentation

#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)

USART frame with 0.5 stop bit

Definition at line 211 of file stm32h7xx_hal_usart.h.

#define USART_STOPBITS_1 ((uint32_t)0x00000000U)

USART frame with 1 stop bit

Definition at line 212 of file stm32h7xx_hal_usart.h.

#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))

USART frame with 1.5 stop bits

Definition at line 213 of file stm32h7xx_hal_usart.h.

#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)

USART frame with 2 stop bits

Definition at line 214 of file stm32h7xx_hal_usart.h.

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STM32H753xx HAL User Manual: USART Parity

Defines
USART Parity
USART Exported Constants

Defines

#define | USART_PARITY_NONE ((uint32_t)0x00000000U)
#define | USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

Even parity

Definition at line 223 of file stm32h7xx_hal_usart.h.

#define USART_PARITY_NONE ((uint32_t)0x00000000U)

No parity

Definition at line 222 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Odd parity

Definition at line 224 of file stm32h7xx_hal_usart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART Mode

Defines
USART Mode
USART Exported Constants

Defines

#define | USART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | USART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define USART_MODE_RX ((uint32_t)USART_CR1_RE)

RX mode

Definition at line 232 of file stm32h7xx_hal_usart.h.

#define USART_MODE_TX ((uint32_t)USART_CR1_TE)

TX mode

Definition at line 233 of file stm32h7xx_hal_usart.h.

#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

RX and TX mode

Definition at line 234 of file stm32h7xx_hal_usart.h.

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STM32H753xx HAL User Manual: USART Over Sampling

Defines
USART Over Sampling
USART Exported Constants

Defines

#define | USART_OVERSAMPLING_16 ((uint32_t)0x00000000U)
#define | USART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)

Define Documentation

#define USART_OVERSAMPLING_16 ((uint32_t)0x00000000U)

Oversampling by 16

Definition at line 242 of file stm32h7xx_hal_usart.h.

#define USART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)

Oversampling by 8

Definition at line 243 of file stm32h7xx_hal_usart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART Clock

Defines
USART Clock
USART Exported Constants

Defines

#define | USART_CLOCK_DISABLE ((uint32_t)0x00000000U)
#define | USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)

Define Documentation

#define USART_CLOCK_DISABLE ((uint32_t)0x00000000U)

USART clock disable

Definition at line 251 of file stm32h7xx_hal_usart.h.

#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)

USART clock enable

Definition at line 252 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART Clock Polarity

Defines
USART Clock Polarity
USART Exported Constants

Defines

#define | USART_POLARITY_LOW ((uint32_t)0x00000000U)
#define | USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

Define Documentation

#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

USART Clock signal is steady High

Definition at line 261 of file stm32h7xx_hal_usart.h.

#define USART_POLARITY_LOW ((uint32_t)0x00000000U)

USART Clock signal is steady Low

Definition at line 260 of file stm32h7xx_hal_usart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART Clock Phase

Defines
USART Clock Phase
USART Exported Constants

Defines

#define | USART_PHASE_1EDGE ((uint32_t)0x00000000U)
#define | USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

Define Documentation

#define USART_PHASE_1EDGE ((uint32_t)0x00000000U)

USART frame phase on first clock transition

Definition at line 269 of file stm32h7xx_hal_usart.h.

#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

USART frame phase on second clock transition

Definition at line 270 of file stm32h7xx_hal_usart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART Last Bit

Defines
USART Last Bit
USART Exported Constants

Defines

#define | USART_LASTBIT_DISABLE ((uint32_t)0x00000000U)
#define | USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

Define Documentation

#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000U)

USART frame last data bit clock pulse not output to SCLK pin

Definition at line 278 of file stm32h7xx_hal_usart.h.

#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

USART frame last data bit clock pulse output to SCLK pin

Definition at line 279 of file stm32h7xx_hal_usart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART Prescaler

Defines
USART Prescaler
USART Exported Constants

Defines

#define | USART_PRESCALER_DIV1 ((uint32_t)0x00000000U)
#define | USART_PRESCALER_DIV2 ((uint32_t)0x00000001U)
#define | USART_PRESCALER_DIV4 ((uint32_t)0x00000002U)
#define | USART_PRESCALER_DIV6 ((uint32_t)0x00000003U)
#define | USART_PRESCALER_DIV8 ((uint32_t)0x00000004U)
#define | USART_PRESCALER_DIV10 ((uint32_t)0x00000005U)
#define | USART_PRESCALER_DIV12 ((uint32_t)0x00000006U)
#define | USART_PRESCALER_DIV16 ((uint32_t)0x00000007U)
#define | USART_PRESCALER_DIV32 ((uint32_t)0x00000008U)
#define | USART_PRESCALER_DIV64 ((uint32_t)0x00000009U)
#define | USART_PRESCALER_DIV128 ((uint32_t)0x0000000AU)
#define | USART_PRESCALER_DIV256 ((uint32_t)0x0000000BU)

Define Documentation

#define USART_PRESCALER_DIV1 ((uint32_t)0x00000000U)

USART clock /1

Definition at line 287 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV10 ((uint32_t)0x00000005U)

USART clock /10

Definition at line 292 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV12 ((uint32_t)0x00000006U)

USART clock /12

Definition at line 293 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV128 ((uint32_t)0x0000000AU)

USART clock /128

Definition at line 297 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV16 ((uint32_t)0x00000007U)

USART clock /16

Definition at line 294 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV2 ((uint32_t)0x00000001U)

USART clock /2

Definition at line 288 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV256 ((uint32_t)0x0000000BU)

USART clock /256

Definition at line 298 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV32 ((uint32_t)0x00000008U)

USART clock /32

Definition at line 295 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV4 ((uint32_t)0x00000002U)

USART clock /4

Definition at line 289 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV6 ((uint32_t)0x00000003U)

USART clock /6

Definition at line 290 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV64 ((uint32_t)0x00000009U)

USART clock /64

Definition at line 296 of file stm32h7xx_hal_usart.h.

#define USART_PRESCALER_DIV8 ((uint32_t)0x00000004U)

USART clock /8

Definition at line 291 of file stm32h7xx_hal_usart.h.

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STM32H753xx HAL User Manual: USART Slave Select Management

Defines
USART Slave Select Management
USART Exported Constants

Defines

#define | USART_NSS_HW ((uint32_t)0x00000000U)
#define | USART_NSS_SW ((uint32_t)USART_CR2_DIS_NSS)

Define Documentation

#define USART_NSS_HW ((uint32_t)0x00000000U)

USART Hardware NSS management

Definition at line 307 of file stm32h7xx_hal_usart.h.

#define USART_NSS_SW ((uint32_t)USART_CR2_DIS_NSS)

USART Software NSS management

Definition at line 308 of file stm32h7xx_hal_usart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART Synchronous Slave mode enable

Defines
USART Synchronous Slave mode enable
USART Exported Constants

Defines

#define | USART_SLAVEMODE_DISABLE ((uint32_t)0x00000000U)
#define | USART_SLAVEMODE_ENABLE ((uint32_t)USART_CR2_SLVEN)

Define Documentation

#define USART_SLAVEMODE_DISABLE ((uint32_t)0x00000000U)

USART SPI Slave Mode Enable

Definition at line 316 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), and USART_Receive_IT().

#define USART_SLAVEMODE_ENABLE ((uint32_t)USART_CR2_SLVEN)

USART SPI Slave Mode Disable

Definition at line 317 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_TransmitReceive().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART FIFO mode

Defines
USART FIFO mode
USART Exported Constants

USART FIFO mode. More...

Defines

#define | USART_FIFOMODE_DISABLE ((uint32_t)0x00000000U)
#define | USART_FIFOMODE_ENABLE ((uint32_t)USART_CR1_FIFOEN)

Detailed Description

USART FIFO mode.

Define Documentation

#define USART_FIFOMODE_DISABLE ((uint32_t)0x00000000U)

FIFO mode disable

Definition at line 327 of file stm32h7xx_hal_usart.h.

#define USART_FIFOMODE_ENABLE ((uint32_t)USART_CR1_FIFOEN)

FIFO mode enable

Definition at line 328 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART TXFIFO threshold level

Defines
USART TXFIFO threshold level
USART Exported Constants

USART TXFIFO level. More...

Defines

#define | USART_TXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000U)
#define | USART_TXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_TXFTCFG_0)
#define | USART_TXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_TXFTCFG_1)
#define | USART_TXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1))
#define | USART_TXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_TXFTCFG_2)
#define | USART_TXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0))

Detailed Description

USART TXFIFO level.

Define Documentation

#define USART_TXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_TXFTCFG_1)

TXFIFO reaches 1/2 of its depth

Definition at line 339 of file stm32h7xx_hal_usart.h.

#define USART_TXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_TXFTCFG_0)

TXFIFO reaches 1/4 of its depth

Definition at line 338 of file stm32h7xx_hal_usart.h.

#define USART_TXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000U)

TXFIFO reaches 1/8 of its depth

Definition at line 337 of file stm32h7xx_hal_usart.h.

#define USART_TXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1))

TXFIFO reaches 3/4 of its depth

Definition at line 340 of file stm32h7xx_hal_usart.h.

#define USART_TXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_TXFTCFG_2)

TXFIFO reaches 7/8 of its depth

Definition at line 341 of file stm32h7xx_hal_usart.h.

#define USART_TXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0))

TXFIFO becomes empty

Definition at line 342 of file stm32h7xx_hal_usart.h.

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STM32H753xx HAL User Manual: USART RXFIFO threshold level

Defines
USART RXFIFO threshold level
USART Exported Constants

USART RXFIFO level. More...

Defines

#define | USART_RXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000U)
#define | USART_RXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_RXFTCFG_0)
#define | USART_RXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_RXFTCFG_1)
#define | USART_RXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1))
#define | USART_RXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_RXFTCFG_2)
#define | USART_RXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0))

Detailed Description

USART RXFIFO level.

Define Documentation

#define USART_RXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_RXFTCFG_1)

RXFIFO reaches 1/2 of its depth

Definition at line 353 of file stm32h7xx_hal_usart.h.

#define USART_RXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_RXFTCFG_0)

RXFIFO reaches 1/4 of its depth

Definition at line 352 of file stm32h7xx_hal_usart.h.

#define USART_RXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000U)

RXFIFO reaches 1/8 of its depth

Definition at line 351 of file stm32h7xx_hal_usart.h.

#define USART_RXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1))

RXFIFO reaches 3/4 of its depth

Definition at line 354 of file stm32h7xx_hal_usart.h.

#define USART_RXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_RXFTCFG_2)

RXFIFO reaches 7/8 of its depth

Definition at line 355 of file stm32h7xx_hal_usart.h.

#define USART_RXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0))

RXFIFO becomes full

Definition at line 356 of file stm32h7xx_hal_usart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART Request Parameters

Defines
USART Request Parameters
USART Exported Constants

Defines

#define | USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Define Documentation

#define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)

Receive Data flush Request

Definition at line 364 of file stm32h7xx_hal_usart.h.

#define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Transmit data flush Request

Definition at line 365 of file stm32h7xx_hal_usart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART Flags

Defines
USART Flags
USART Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | USART_FLAG_TXFT USART_ISR_TXFT
#define | USART_FLAG_RXFT USART_ISR_RXFT
#define | USART_FLAG_RXFF USART_ISR_RXFF
#define | USART_FLAG_TXFE USART_ISR_TXFE
#define | USART_FLAG_REACK USART_ISR_REACK
#define | USART_FLAG_TEACK USART_ISR_TEACK
#define | USART_FLAG_BUSY USART_ISR_BUSY
#define | USART_FLAG_UDR USART_ISR_UDR
#define | USART_FLAG_LBDF USART_ISR_LBDF
#define | USART_FLAG_TXE USART_ISR_TXE
#define | USART_FLAG_TXFNF USART_ISR_TXE
#define | USART_FLAG_TC USART_ISR_TC
#define | USART_FLAG_RXNE USART_ISR_RXNE
#define | USART_FLAG_RXFNE USART_ISR_RXNE
#define | USART_FLAG_IDLE USART_ISR_IDLE
#define | USART_FLAG_ORE USART_ISR_ORE
#define | USART_FLAG_NE USART_ISR_NE
#define | USART_FLAG_FE USART_ISR_FE
#define | USART_FLAG_PE USART_ISR_PE

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define USART_FLAG_BUSY USART_ISR_BUSY

USART busy flag

Definition at line 381 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_FE USART_ISR_FE

USART frame error

Definition at line 392 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_IDLE USART_ISR_IDLE

USART idle flag

Definition at line 389 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_LBDF USART_ISR_LBDF

USART LIN break detection flag

Definition at line 383 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_NE USART_ISR_NE

USART noise error

Definition at line 391 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_ORE USART_ISR_ORE

USART overrun error

Definition at line 390 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_PE USART_ISR_PE

USART parity error

Definition at line 393 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_REACK USART_ISR_REACK

USART receive enable acknowledge flag

Definition at line 379 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_RXFF USART_ISR_RXFF

USART RXFIFO Fullflag

Definition at line 377 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_RXFNE USART_ISR_RXNE

USART RXFIFO not empty

Definition at line 388 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_RXFT USART_ISR_RXFT

USART RXFIFO threshold flag

Definition at line 376 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_RXNE USART_ISR_RXNE

USART read data register not empty

Definition at line 387 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_TransmitReceive(), and USART_TransmitReceive_IT().

#define USART_FLAG_TC USART_ISR_TC

USART transmission complete

Definition at line 386 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), and HAL_USART_Transmit().

#define USART_FLAG_TEACK USART_ISR_TEACK

USART transmit enable acknowledge flag

Definition at line 380 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_TXE USART_ISR_TXE

USART transmit data register empty

Definition at line 384 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Transmit(), HAL_USART_TransmitReceive(), and USART_TransmitReceive_IT().

#define USART_FLAG_TXFE USART_ISR_TXFE

USART TXFIFO Empty flag

Definition at line 378 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_TXFNF USART_ISR_TXE

USART TXFIFO not full

Definition at line 385 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_TXFT USART_ISR_TXFT

USART TXFIFO threshold flag

Definition at line 375 of file stm32h7xx_hal_usart.h.

#define USART_FLAG_UDR USART_ISR_UDR

USART SPI slave underrun error

Definition at line 382 of file stm32h7xx_hal_usart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART Interrupts Definition

Defines
USART Interrupts Definition
USART Exported Constants

Elements values convention: 0000ZZZZ0XXYYYYYb. More...

Defines

#define | USART_IT_PE ((uint16_t)0x0028U)
#define | USART_IT_TXE ((uint16_t)0x0727U)
#define | USART_IT_TC ((uint16_t)0x0626U)
#define | USART_IT_RXNE ((uint16_t)0x0525U)
#define | USART_IT_IDLE ((uint16_t)0x0424U)
#define | USART_IT_ERR ((uint16_t)0x0060U)
#define | USART_IT_RXFF ((uint16_t)0x183FU)
#define | USART_IT_TXFE ((uint16_t)0x173EU)
#define | USART_IT_RXFT ((uint16_t)0x1A7CU)
#define | USART_IT_TXFT ((uint16_t)0x1B77U)
#define | USART_IT_UDR ((uint16_t)0x0D00U)
#define | USART_IT_ORE ((uint16_t)0x0300U)
#define | USART_IT_NE ((uint16_t)0x0200U)
#define | USART_IT_FE ((uint16_t)0x0100U)

Detailed Description

Elements values convention: 0000ZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZ : Flag position in the ISR register(5bits instead of 4bits)

Define Documentation

#define USART_IT_ERR ((uint16_t)0x0060U)

Definition at line 414 of file stm32h7xx_hal_usart.h.

#define USART_IT_FE ((uint16_t)0x0100U)

Definition at line 423 of file stm32h7xx_hal_usart.h.

#define USART_IT_IDLE ((uint16_t)0x0424U)

Definition at line 413 of file stm32h7xx_hal_usart.h.

#define USART_IT_NE ((uint16_t)0x0200U)

Definition at line 422 of file stm32h7xx_hal_usart.h.

#define USART_IT_ORE ((uint16_t)0x0300U)

Definition at line 421 of file stm32h7xx_hal_usart.h.

#define USART_IT_PE ((uint16_t)0x0028U)

Definition at line 409 of file stm32h7xx_hal_usart.h.

#define USART_IT_RXFF ((uint16_t)0x183FU)

Definition at line 415 of file stm32h7xx_hal_usart.h.

#define USART_IT_RXFT ((uint16_t)0x1A7CU)

Definition at line 417 of file stm32h7xx_hal_usart.h.

#define USART_IT_RXNE ((uint16_t)0x0525U)

Definition at line 412 of file stm32h7xx_hal_usart.h.

#define USART_IT_TC ((uint16_t)0x0626U)

Definition at line 411 of file stm32h7xx_hal_usart.h.

#define USART_IT_TXE ((uint16_t)0x0727U)

Definition at line 410 of file stm32h7xx_hal_usart.h.

#define USART_IT_TXFE ((uint16_t)0x173EU)

Definition at line 416 of file stm32h7xx_hal_usart.h.

#define USART_IT_TXFT ((uint16_t)0x1B77U)

Definition at line 418 of file stm32h7xx_hal_usart.h.

#define USART_IT_UDR ((uint16_t)0x0D00U)

Definition at line 420 of file stm32h7xx_hal_usart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART Interruption Clear Flags

Defines
USART Interruption Clear Flags
USART Exported Constants

Defines

#define | USART_CLEAR_PEF USART_ICR_PECF
#define | USART_CLEAR_FEF USART_ICR_FECF
#define | USART_CLEAR_NEF USART_ICR_NCF
#define | USART_CLEAR_OREF USART_ICR_ORECF
#define | USART_CLEAR_IDLEF USART_ICR_IDLECF
#define | USART_CLEAR_TCF USART_ICR_TCCF
#define | USART_CLEAR_UDRCF USART_ICR_UDRCF
#define | USART_CLEAR_TXFECF USART_ICR_TXFECF

Define Documentation

#define USART_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 432 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 435 of file stm32h7xx_hal_usart.h.

#define USART_CLEAR_NEF USART_ICR_NCF

Noise detected Clear Flag

Definition at line 433 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_OREF USART_ICR_ORECF

OverRun Error Clear Flag

Definition at line 434 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAResume(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 431 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 436 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

#define USART_CLEAR_TXFECF USART_ICR_TXFECF

TXFIFO empty clear flag

Definition at line 438 of file stm32h7xx_hal_usart.h.

#define USART_CLEAR_UDRCF USART_ICR_UDRCF

UnderRun Error Clear Flag

Definition at line 437 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART Interruption Flags Mask

Defines
USART Interruption Flags Mask
USART Exported Constants

Defines

#define USART_IT_MASK ((uint16_t)0x001FU)

Define Documentation

#define USART_IT_MASK ((uint16_t)0x001FU)

USART interruptions flags mask

Definition at line 446 of file stm32h7xx_hal_usart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART Exported Macros

Defines
USART Exported Macros
USART

Defines

#define | __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
Reset USART handle state.
#define | __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified USART flag is set or not.
#define | __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified USART pending flag.
#define | __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified USART interrupt.
#define | __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified USART interrupt.
#define | __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
Check whether the specified USART interrupt has occurred or not.
#define | __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified USART interrupt source is enabled or not.
#define | __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified USART ISR flag, in setting the proper ICR register flag.
#define | __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_PEF)
Clear the USART PE pending flag.
#define | __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_FEF)
Clear the USART FE pending flag.
#define | __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_NEF)
Clear the USART NE pending flag.
#define | __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_OREF)
Clear the USART ORE pending flag.
#define | __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_IDLEF)
Clear the USART IDLE pending flag.
#define | __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_UDRCF)
Clear the USART UDR pending flag.
#define | __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_TXFECF)
Clear the USART TX FIFO empty clear flag.
#define | __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__))
Set a specific USART request flag.
#define | __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the USART one bit sample method.
#define | __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the USART one bit sample method.
#define | __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable USART.
#define | __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable USART.

Define Documentation

#define __HAL_USART_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_FEF)

Clear the USART FE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 634 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified USART pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle.
__FLAG__,: specifies the flag to check. This parameter can be any combination of the following values:
  • USART_FLAG_TXFT: TXFIFO threshold flag
  • USART_FLAG_RXFT: RXFIFO threshold flag
  • USART_FLAG_RXFF: RXFIFO Full flag
  • USART_FLAG_TXFE: TXFIFO Empty flag
  • USART_FLAG_REACK: Receive enable ackowledge flag
  • USART_FLAG_TEACK: Transmit enable ackowledge flag
  • USART_FLAG_WUF: Wake up from stop mode flag
  • USART_FLAG_RWU: Receiver wake up flag (is the USART in mute mode)
  • USART_FLAG_SBKF: Send Break flag
  • USART_FLAG_CMF: Character match flag
  • USART_FLAG_BUSY: Busy flag
  • USART_FLAG_ABRF: Auto Baud rate detection flag
  • USART_FLAG_ABRE: Auto Baud rate detection error flag
  • USART_FLAG_RTOF: Receiver timeout flag
  • USART_FLAG_LBD: LIN Break detection flag
  • USART_FLAG_TXE: Transmit data register empty flag
  • USART_FLAG_TC: Transmission Complete flag
  • USART_FLAG_RXNE: Receive data register not empty flag
  • USART_FLAG_IDLE: Idle Line detection flag
  • USART_FLAG_ORE: OverRun Error flag
  • USART_FLAG_NE: Noise Error flag
  • USART_FLAG_FE: Framing Error flag
  • USART_FLAG_PE: Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 519 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAResume(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define __HAL_USART_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_IDLEF)

Clear the USART IDLE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 652 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified USART ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__,: specifies the USART Handle.
__IT_CLEAR__,: specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt. This parameter can be one of the following values:
  • USART_CLEAR_PEF: Parity Error Clear Flag
  • USART_CLEAR_FEF: Framing Error Clear Flag
  • USART_CLEAR_NEF: Noise detected Clear Flag
  • USART_CLEAR_OREF: OverRun Error Clear Flag
  • USART_CLEAR_IDLEF: IDLE line detected Clear Flag
  • USART_CLEAR_TCF: Transmission Complete Clear Flag
  • USART_CLEAR_UDRCF: UnderRun Error Clear Flag
  • USART_CLEAR_TXFECF: TXFIFO empty Clear Flag
Return values:
None

Definition at line 622 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define __HAL_USART_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_NEF)

Clear the USART NE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 640 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_OREF)

Clear the USART ORE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 646 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_PEF)

Clear the USART PE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 628 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_CLEAR_TXFECF ( __HANDLE__ ) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_TXFECF)

Clear the USART TX FIFO empty clear flag.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 664 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_CLEAR_UDRFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_UDRCF)

Clear the USART UDR pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 658 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable USART.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 701 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Init().

#define __HAL_USART_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))

Disable the specified USART interrupt.

Parameters:
__HANDLE__,: specifies the USART Handle.
__INTERRUPT__,: specifies the USART interrupt source to disable. This parameter can be one of the following values:
  • USART_IT_RXFF: RXFIFO Full interrupt
  • USART_IT_TXFE: TXFIFO Empty interrupt
  • USART_IT_RXFT: RXFIFO threshold interrupt
  • USART_IT_TXFT: TXFIFO threshold interrupt
  • USART_IT_TXE : Transmit Data Register empty interrupt
  • USART_IT_TC : Transmission complete interrupt
  • USART_IT_RXNE: Receive Data register not empty interrupt
  • USART_IT_IDLE: Idle line detection interrupt
  • USART_IT_PE : Parity Error interrupt
  • USART_IT_ERR : Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 558 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable USART.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 695 of file stm32h7xx_hal_usart.h.

Referenced by HAL_USART_Init().

#define __HAL_USART_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))

Enable the specified USART interrupt.

Parameters:
__HANDLE__,: specifies the USART Handle.
__INTERRUPT__,: specifies the USART interrupt source to enable. This parameter can be one of the following values:
  • USART_IT_RXFF: RXFIFO Full interrupt
  • USART_IT_TXFE: TXFIFO Empty interrupt
  • USART_IT_RXFT: RXFIFO threshold interrupt
  • USART_IT_TXFT: TXFIFO threshold interrupt
  • USART_IT_TXE : Transmit Data Register empty interrupt
  • USART_IT_TC : Transmission complete interrupt
  • USART_IT_RXNE: Receive Data register not empty interrupt
  • USART_IT_IDLE: Idle line detection interrupt
  • USART_IT_PE : Parity Error interrupt
  • USART_IT_ERR : Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 538 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified USART flag is set or not.

Parameters:
__HANDLE__,: specifies the USART Handle
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • USART_FLAG_TXFT: TXFIFO threshold flag
  • USART_FLAG_RXFT: RXFIFO threshold flag
  • USART_FLAG_RXFF: RXFIFO Full flag
  • USART_FLAG_TXFE: TXFIFO Empty flag
  • USART_FLAG_REACK: Receive enable ackowledge flag
  • USART_FLAG_TEACK: Transmit enable ackowledge flag
  • USART_FLAG_BUSY: Busy flag
  • USART_FLAG_TXE: Transmit data register empty flag
  • USART_FLAG_TC: Transmission Complete flag
  • USART_FLAG_RXNE: Receive data register not empty flag
  • USART_FLAG_IDLE: Idle Line detection flag
  • USART_FLAG_ORE: OverRun Error flag
  • USART_FLAG_UDR: UnderRun Error flag
  • USART_FLAG_NE: Noise Error flag
  • USART_FLAG_FE: Framing Error flag
  • USART_FLAG_PE: Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 488 of file stm32h7xx_hal_usart.h.

Referenced by USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

#define __HAL_USART_GET_IT | ( | __HANDLE__,
 |  | __IT__
 | ) | ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))

Check whether the specified USART interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the USART Handle.
__IT__,: specifies the USART interrupt source to check. This parameter can be one of the following values:
  • USART_IT_RXFF: RXFIFO Full interrupt
  • USART_IT_TXFE: TXFIFO Empty interrupt
  • USART_IT_RXFT: RXFIFO threshold interrupt
  • USART_IT_TXFT: TXFIFO threshold interrupt
  • USART_IT_TXE : Transmit Data Register empty interrupt
  • USART_IT_TC : Transmission complete interrupt
  • USART_IT_RXNE: Receive Data register not empty interrupt
  • USART_IT_IDLE: Idle line detection interrupt
  • USART_IT_ORE : OverRun Error interrupt
  • USART_IT_UDR : UnderRun Error interrupt
  • USART_IT_NE : Noise Error interrupt
  • USART_IT_FE : Framing Error interrupt
  • USART_IT_PE : Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 582 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
                                                   (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \
                                                   (((uint16_t)(__IT__)) & USART_IT_MASK)))

Check whether the specified USART interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the USART Handle.
__IT__,: specifies the USART interrupt source to check. This parameter can be one of the following values:
  • USART_IT_RXFF: RXFIFO Full interrupt
  • USART_IT_TXFE: TXFIFO Empty interrupt
  • USART_IT_RXFT: RXFIFO threshold interrupt
  • USART_IT_TXFT: TXFIFO threshold interrupt
  • USART_IT_TXE : Transmit Data Register empty interrupt
  • USART_IT_TC : Transmission complete interrupt
  • USART_IT_RXNE: Receive Data register not empty interrupt
  • USART_IT_IDLE: Idle line detection interrupt
  • USART_IT_ORE : OverRun Error interrupt
  • USART_IT_NE : Noise Error interrupt
  • USART_IT_FE : Framing Error interrupt
  • USART_IT_PE : Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 602 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

Disable the USART one bit sample method.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 689 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the USART one bit sample method.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 683 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_USART_STATE_RESET)

Reset USART handle state.

Parameters:
__HANDLE__,: USART handle.
Return values:
None

Definition at line 464 of file stm32h7xx_hal_usart.h.

#define __HAL_USART_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (__REQ__))

Set a specific USART request flag.

Parameters:
__HANDLE__,: specifies the USART Handle.
__REQ__,: specifies the request flag to set. This parameter can be one of the following values:
  • USART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
  • USART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
Return values:
None

Definition at line 677 of file stm32h7xx_hal_usart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART Private Variables

Variables
USART Private Variables
USART

Variables

static const uint16_t USARTPrescTable [12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}

Variable Documentation

const uint16_t USARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256} [static]

Definition at line 711 of file stm32h7xx_hal_usart.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART Private Macros

Defines
USART Private Macros
USART

Defines

#define | USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the USART clock source.
#define | USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __PRESCALER__) (((((__PCLK__)/USARTPrescTable[(__PRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__))
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
Check USART Baud rate.
#define | IS_USART_STOPBITS(__STOPBITS__)
Ensure that USART frame number of stop bits is valid.
#define | IS_USART_PARITY(__PARITY__)
Ensure that USART frame parity is valid.
#define | IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3U) == 0x00U) && ((__MODE__) != (uint32_t)0x00U))
Ensure that USART communication mode is valid.
#define | IS_USART_OVERSAMPLING(__SAMPLING__)
Ensure that USART oversampling is valid.
#define | IS_USART_CLOCK(__CLOCK__)
Ensure that USART clock state is valid.
#define | IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
Ensure that USART frame polarity is valid.
#define | IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
Ensure that USART frame phase is valid.
#define | IS_USART_LASTBIT(__LASTBIT__)
Ensure that USART frame last bit clock pulse setting is valid.
#define | IS_USART_REQUEST_PARAMETER(__PARAM__)
Ensure that USART request parameter is valid.
#define | IS_USART_PRESCALER(__PRESCALER__)
Ensure that USART Prescaler is valid.
#define | IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HW) || ((__NSS__) == USART_NSS_SW))
Ensure that USART NSS is valid.
#define | IS_USART_FIFO_MODE_STATE(__STATE__)
Ensure that USART FIFO mode is valid.
#define | IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that USART TXFIFO threshold level is valid.
#define | IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that USART RXFIFO threshold level is valid.
#define | IS_USART_SLAVEMODE(__STATE__)
Ensure that USART Slave Mode is valid.

Define Documentation

#define IS_USART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 12500001U)

Check USART Baud rate.

Parameters:
__BAUDRATE__,: Baudrate specified by the user. The maximum Baud Rate is derived from the maximum clock on H7 (i.e. 100 MHz) divided by the smallest oversampling used on the USART (i.e. 8).
Return values:
Test result (TRUE or FALSE).

Definition at line 840 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_CLOCK ( __CLOCK__ )
Value:
(((__CLOCK__) == USART_CLOCK_DISABLE) || \
                                   ((__CLOCK__) == USART_CLOCK_ENABLE))

Ensure that USART clock state is valid.

Parameters:
__CLOCK__,: USART clock state.
Return values:
SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)

Definition at line 881 of file stm32h7xx_hal_usart.h.

#define IS_USART_FIFO_MODE_STATE ( __STATE__ )
Value:
(((__STATE__) == USART_FIFOMODE_DISABLE ) || \
                                             ((__STATE__) == USART_FIFOMODE_ENABLE))

Ensure that USART FIFO mode is valid.

Parameters:
__STATE__,: USART FIFO mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 944 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_LASTBIT ( __LASTBIT__ )
Value:
(((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
                                       ((__LASTBIT__) == USART_LASTBIT_ENABLE))

Ensure that USART frame last bit clock pulse setting is valid.

Parameters:
__LASTBIT__,: USART frame last bit clock pulse setting.
Return values:
SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)

Definition at line 903 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_MODE ( __MODE__ ) ((((__MODE__) & (uint32_t)0xFFFFFFF3U) == 0x00U) && ((__MODE__) != (uint32_t)0x00U))

Ensure that USART communication mode is valid.

Parameters:
__MODE__,: USART communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 866 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_NSS ( __NSS__ ) (((__NSS__) == USART_NSS_HW) || ((__NSS__) == USART_NSS_SW))

Ensure that USART NSS is valid.

Parameters:
__NSS__,: USART Negative Slave Select pin management.
Return values:
SET (__NSS__ is valid) or RESET (__NSS__ is invalid)

Definition at line 937 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_OVERSAMPLING ( __SAMPLING__ )
Value:
(((__SAMPLING__) == USART_OVERSAMPLING_16) || \
                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))

Ensure that USART oversampling is valid.

Parameters:
__SAMPLING__,: USART oversampling.
Return values:
SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)

Definition at line 873 of file stm32h7xx_hal_usart.h.

#define IS_USART_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == USART_PARITY_NONE) || \
                                     ((__PARITY__) == USART_PARITY_EVEN) || \
                                     ((__PARITY__) == USART_PARITY_ODD))

Ensure that USART frame parity is valid.

Parameters:
__PARITY__,: USART frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 857 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_PHASE ( __CPHA__ ) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))

Ensure that USART frame phase is valid.

Parameters:
__CPHA__,: USART frame phase.
Return values:
SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)

Definition at line 896 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_POLARITY ( __CPOL__ ) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))

Ensure that USART frame polarity is valid.

Parameters:
__CPOL__,: USART frame polarity.
Return values:
SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)

Definition at line 889 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == USART_PRESCALER_DIV1) || \
                                           ((__PRESCALER__) == USART_PRESCALER_DIV2) || \
                                           ((__PRESCALER__) == USART_PRESCALER_DIV4) || \
                                           ((__PRESCALER__) == USART_PRESCALER_DIV6) || \
                                           ((__PRESCALER__) == USART_PRESCALER_DIV8) || \
                                           ((__PRESCALER__) == USART_PRESCALER_DIV10) || \
                                           ((__PRESCALER__) == USART_PRESCALER_DIV12) || \
                                           ((__PRESCALER__) == USART_PRESCALER_DIV16) || \
                                           ((__PRESCALER__) == USART_PRESCALER_DIV32) || \
                                           ((__PRESCALER__) == USART_PRESCALER_DIV64) || \
                                           ((__PRESCALER__) == USART_PRESCALER_DIV128) || \
                                           ((__PRESCALER__) == USART_PRESCALER_DIV256))

Ensure that USART Prescaler is valid.

Parameters:
__PRESCALER__,: USART Prescaler value.
Return values:
SET (__PRESCALER__ is valid) or RESET (__PRESCALER__ is invalid)

Definition at line 919 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
                                               ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))

Ensure that USART request parameter is valid.

Parameters:
__PARAM__,: USART request parameter.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 911 of file stm32h7xx_hal_usart.h.

#define IS_USART_RXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8) || \
                                                  ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4) || \
                                                  ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2) || \
                                                  ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4) || \
                                                  ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8) || \
                                                  ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8))

Ensure that USART RXFIFO threshold level is valid.

Parameters:
__THRESHOLD__,: USART RXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 964 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_SLAVEMODE ( __STATE__ )
Value:
(((__STATE__) == USART_SLAVEMODE_DISABLE ) || \
                                         ((__STATE__) == USART_SLAVEMODE_ENABLE))

Ensure that USART Slave Mode is valid.

Parameters:
__STATE__,: USART Slave Mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 976 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == USART_STOPBITS_0_5) || \
                                         ((__STOPBITS__) == USART_STOPBITS_1)   || \
                                         ((__STOPBITS__) == USART_STOPBITS_1_5) || \
                                         ((__STOPBITS__) == USART_STOPBITS_2))

Ensure that USART frame number of stop bits is valid.

Parameters:
__STOPBITS__,: USART frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 847 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_TXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8) || \
                                                  ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4) || \
                                                  ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2) || \
                                                  ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4) || \
                                                  ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8) || \
                                                  ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8))

Ensure that USART TXFIFO threshold level is valid.

Parameters:
__THRESHOLD__,: USART TXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 952 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define USART_DIV_SAMPLING8 | ( | __PCLK__,
 |  | __BAUD__,
 |  | __PRESCALER__
 | ) | (((((__PCLK__)/USARTPrescTable[(__PRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__))

BRR division operation to set BRR register in 8-bit oversampling mode.

Parameters:
__PCLK__,: USART clock.
__BAUD__,: Baud rate set by the user.
__PRESCALER__,: UART prescaler value.
Return values:
Division result

Definition at line 832 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define USART_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the USART clock source.

Parameters:
__HANDLE__,: specifies the USART Handle.
__CLOCKSOURCE__,: output variable.
Return values:
the USART clocking source, written in __CLOCKSOURCE__.

Definition at line 726 of file stm32h7xx_hal_usart.h.

Referenced by USART_SetConfig().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and Configuration functions

Functions
Initialization and Configuration functions
WWDG Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
          ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
      (+) Initialize and start the WWDG according to the specified parameters
          in the WWDG_InitTypeDef of associated handle.
      (+) Initialize the WWDG MSP.

Function Documentation

HAL_StatusTypeDef HAL_WWDG_Init ( WWDG_HandleTypeDef * hwwdg )

Initialize the WWDG according to the specified.

parameters in the WWDG_InitTypeDef of associated handle.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 174 of file stm32h7xx_hal_wwdg.c.

References assert_param, WWDG_InitTypeDef::Counter, WWDG_InitTypeDef::EWIMode, HAL_WWDG_MspInit(), WWDG_HandleTypeDef::Init, WWDG_HandleTypeDef::Instance, IS_WWDG_COUNTER, IS_WWDG_EWI_MODE, IS_WWDG_PRESCALER, IS_WWDG_WINDOW, WWDG_InitTypeDef::Prescaler, and WWDG_InitTypeDef::Window.

void HAL_WWDG_MspInit ( WWDG_HandleTypeDef * hwwdg )

Initialize the WWDG MSP.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Note:
When rewriting this function in user file, mechanism may be added to avoid multiple initialize when HAL_WWDG_Init function is called again to change parameters.
Return values:
None

Definition at line 212 of file stm32h7xx_hal_wwdg.c.

Referenced by HAL_WWDG_Init().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
WWDG Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

IO operation functions.

  ==============================================================================
                      ##### IO operation functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Refresh the WWDG.
    (+) Handle WWDG interrupt request and associated function callback.

Function Documentation

void HAL_WWDG_EarlyWakeupCallback ( WWDG_HandleTypeDef * hwwdg )

WWDG Early Wakeup callback.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 295 of file stm32h7xx_hal_wwdg.c.

Referenced by HAL_WWDG_IRQHandler().

void HAL_WWDG_IRQHandler ( WWDG_HandleTypeDef * hwwdg )

Handle WWDG interrupt request.

Note:
The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be performed before the actual reset is generated. The EWI interrupt is enabled by calling HAL_WWDG_Init function with EWIMode set to WWDG_EWI_ENABLE. When the downcounter reaches the value 0x40, and EWI interrupt is generated and the corresponding Interrupt Service Routine (ISR) can be used to trigger specific actions (such as communications or data logging), before resetting the device.
Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 271 of file stm32h7xx_hal_wwdg.c.

References __HAL_WWDG_CLEAR_FLAG, __HAL_WWDG_GET_FLAG, __HAL_WWDG_GET_IT_SOURCE, HAL_WWDG_EarlyWakeupCallback(), WWDG_FLAG_EWIF, and WWDG_IT_EWI.

HAL_StatusTypeDef HAL_WWDG_Refresh ( WWDG_HandleTypeDef * hwwdg )

Refresh the WWDG.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 248 of file stm32h7xx_hal_wwdg.c.

References WWDG_InitTypeDef::Counter, WWDG_HandleTypeDef::Init, and WWDG_HandleTypeDef::Instance.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: WWDG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
WWDG_InitTypeDef Struct Reference
WWDG Exported Types

WWDG Init structure definition. More...

#include <stm32h7xx_hal_wwdg.h>

Data Fields

uint32_t | Prescaler
uint32_t | Window
uint32_t | Counter
uint32_t | EWIMode

Detailed Description

WWDG Init structure definition.

Definition at line 66 of file stm32h7xx_hal_wwdg.h.

Field Documentation

uint32_t WWDG_InitTypeDef::Counter

Specifies the WWDG free-running downcounter value. This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F

Definition at line 74 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

uint32_t WWDG_InitTypeDef::EWIMode

Specifies if WWDG Early Wakeup Interupt is enable or not. This parameter can be a value of WWDG Early Wakeup Interrupt Mode

Definition at line 77 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

uint32_t WWDG_InitTypeDef::Prescaler

Specifies the prescaler value of the WWDG. This parameter can be a value of WWDG Prescaler

Definition at line 68 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

uint32_t WWDG_InitTypeDef::Window

Specifies the WWDG window value to be compared to the downcounter. This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F

Definition at line 71 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_wwdg.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: WWDG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
WWDG_HandleTypeDef Struct Reference
WWDG Exported Types

WWDG handle Structure definition. More...

#include <stm32h7xx_hal_wwdg.h>

Data Fields

WWDG_TypeDef * Instance
WWDG_InitTypeDef Init

Detailed Description

WWDG handle Structure definition.

Definition at line 85 of file stm32h7xx_hal_wwdg.h.

Field Documentation

WWDG_InitTypeDef WWDG_HandleTypeDef::Init

WWDG required parameters

Definition at line 89 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

WWDG_TypeDef* WWDG_HandleTypeDef::Instance

Register base address

Definition at line 87 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_wwdg.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: WWDG Interrupt definition

Defines
WWDG Interrupt definition
WWDG Exported Constants

Defines

#define WWDG_IT_EWI WWDG_CFR_EWI

Define Documentation

#define WWDG_IT_EWI WWDG_CFR_EWI

Early wakeup interrupt

Definition at line 105 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: WWDG Flag definition

Defines
WWDG Flag definition
WWDG Exported Constants

WWDG Flag definition. More...

Defines

#define WWDG_FLAG_EWIF WWDG_SR_EWIF

Detailed Description

WWDG Flag definition.

Define Documentation

#define WWDG_FLAG_EWIF WWDG_SR_EWIF

Early wakeup interrupt flag

Definition at line 114 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: WWDG Prescaler

Defines
WWDG Prescaler
WWDG Exported Constants

Defines

#define | WWDG_PRESCALER_1 ((uint32_t)(0x00000000U))
#define | WWDG_PRESCALER_2 ((uint32_t)(WWDG_CFR_WDGTB0))
#define | WWDG_PRESCALER_4 ((uint32_t)(WWDG_CFR_WDGTB1))
#define | WWDG_PRESCALER_8 ((uint32_t)(WWDG_CFR_WDGTB1|WWDG_CFR_WDGTB0))
#define | WWDG_PRESCALER_16 ((uint32_t)(WWDG_CFR_WDGTB2))
#define | WWDG_PRESCALER_32 ((uint32_t)(WWDG_CFR_WDGTB2|WWDG_CFR_WDGTB0))
#define | WWDG_PRESCALER_64 ((uint32_t)(WWDG_CFR_WDGTB2|WWDG_CFR_WDGTB1))
#define | WWDG_PRESCALER_128 ((uint32_t)(WWDG_CFR_WDGTB2|WWDG_CFR_WDGTB1|WWDG_CFR_WDGTB0))

Define Documentation

#define WWDG_PRESCALER_1 ((uint32_t)(0x00000000U))

WWDG counter clock = (PCLK1/4096)/1

Definition at line 122 of file stm32h7xx_hal_wwdg.h.

#define WWDG_PRESCALER_128 ((uint32_t)(WWDG_CFR_WDGTB2|WWDG_CFR_WDGTB1|WWDG_CFR_WDGTB0))

WWDG counter clock = (PCLK1/4096)/128

Definition at line 129 of file stm32h7xx_hal_wwdg.h.

#define WWDG_PRESCALER_16 ((uint32_t)(WWDG_CFR_WDGTB2))

WWDG counter clock = (PCLK1/4096)/16

Definition at line 126 of file stm32h7xx_hal_wwdg.h.

#define WWDG_PRESCALER_2 ((uint32_t)(WWDG_CFR_WDGTB0))

WWDG counter clock = (PCLK1/4096)/2

Definition at line 123 of file stm32h7xx_hal_wwdg.h.

#define WWDG_PRESCALER_32 ((uint32_t)(WWDG_CFR_WDGTB2|WWDG_CFR_WDGTB0))

WWDG counter clock = (PCLK1/4096)/32

Definition at line 127 of file stm32h7xx_hal_wwdg.h.

#define WWDG_PRESCALER_4 ((uint32_t)(WWDG_CFR_WDGTB1))

WWDG counter clock = (PCLK1/4096)/4

Definition at line 124 of file stm32h7xx_hal_wwdg.h.

#define WWDG_PRESCALER_64 ((uint32_t)(WWDG_CFR_WDGTB2|WWDG_CFR_WDGTB1))

WWDG counter clock = (PCLK1/4096)/64

Definition at line 128 of file stm32h7xx_hal_wwdg.h.

#define WWDG_PRESCALER_8 ((uint32_t)(WWDG_CFR_WDGTB1|WWDG_CFR_WDGTB0))

WWDG counter clock = (PCLK1/4096)/8

Definition at line 125 of file stm32h7xx_hal_wwdg.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: WWDG Early Wakeup Interrupt Mode

Defines
WWDG Early Wakeup Interrupt Mode
WWDG Exported Constants

Defines

#define | WWDG_EWI_DISABLE 0x00000000u
#define | WWDG_EWI_ENABLE WWDG_CFR_EWI

Define Documentation

#define WWDG_EWI_DISABLE 0x00000000u

EWI Disable

Definition at line 138 of file stm32h7xx_hal_wwdg.h.

#define WWDG_EWI_ENABLE WWDG_CFR_EWI

EWI Enable

Definition at line 139 of file stm32h7xx_hal_wwdg.h.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: WWDG Private Macros

Defines
WWDG Private Macros
WWDG

Defines

#define | IS_WWDG_PRESCALER(__PRESCALER__)
#define | IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W6) && ((__WINDOW__) <= WWDG_CFR_W))
#define | IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T6) && ((__COUNTER__) <= WWDG_CR_T))
#define | IS_WWDG_EWI_MODE(__MODE__)

Define Documentation

#define IS_WWDG_COUNTER ( __COUNTER__ ) (((__COUNTER__) >= WWDG_CR_T6) && ((__COUNTER__) <= WWDG_CR_T))

Definition at line 164 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_EWI_MODE ( __MODE__ )
Value:
(((__MODE__) == WWDG_EWI_ENABLE) || \
                                             ((__MODE__) == WWDG_EWI_DISABLE))

Definition at line 166 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == WWDG_PRESCALER_1)  || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_2)  || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_4)  || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_8)  || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_16) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_32) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_64) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_128))

Definition at line 153 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_WINDOW ( __WINDOW__ ) (((__WINDOW__) >= WWDG_CFR_W6) && ((__WINDOW__) <= WWDG_CFR_W))

Definition at line 162 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: WWDG Exported Macros

Defines
WWDG Exported Macros
WWDG

Defines

#define | __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
Enable the WWDG peripheral.
#define | __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
Enable the WWDG early wakeup interrupt.
#define | __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
Check whether the selected WWDG interrupt has occurred or not.
#define | __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
Clear the WWDG interrupt pending bits.
#define | __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified WWDG flag is set or not.
#define | __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(uint32_t)(__FLAG__))
Clear the WWDG's pending flags.
#define | __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified WWDG interrupt source is enabled or not.

Define Documentation

#define __HAL_WWDG_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(uint32_t)(__FLAG__))

Clear the WWDG's pending flags.

Parameters:
__HANDLE__ WWDG handle
__FLAG__ specifies the flag to clear. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag
Return values:
None

Definition at line 234 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))

Clear the WWDG interrupt pending bits.

bits to clear the selected interrupt pending bits.

Parameters:
__HANDLE__ WWDG handle
__INTERRUPT__ specifies the interrupt pending bit to clear. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag

Definition at line 214 of file stm32h7xx_hal_wwdg.h.

#define __HAL_WWDG_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)

Enable the WWDG peripheral.

Parameters:
__HANDLE__ WWDG handle
Return values:
None

Definition at line 184 of file stm32h7xx_hal_wwdg.h.

#define __HAL_WWDG_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))

Enable the WWDG early wakeup interrupt.

Parameters:
__HANDLE__,: WWDG handle
__INTERRUPT__ specifies the interrupt to enable. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early wakeup interrupt
Note:
Once enabled this interrupt cannot be disabled except by a system reset.
Return values:
None

Definition at line 195 of file stm32h7xx_hal_wwdg.h.

#define __HAL_WWDG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Check whether the specified WWDG flag is set or not.

Parameters:
__HANDLE__ WWDG handle
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag
Return values:
The new state of WWDG_FLAG (SET or RESET).

Definition at line 224 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))

Check whether the selected WWDG interrupt has occurred or not.

Parameters:
__HANDLE__ WWDG handle
__INTERRUPT__ specifies the it to check. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt IT
Return values:
The new state of WWDG_FLAG (SET or RESET).

Definition at line 205 of file stm32h7xx_hal_wwdg.h.

#define __HAL_WWDG_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified WWDG interrupt source is enabled or not.

Parameters:
__HANDLE__ WWDG Handle.
__INTERRUPT__ specifies the WWDG interrupt source to check. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early Wakeup Interrupt
Return values:
state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 243 of file stm32h7xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRC Extended input data inversion modes

Defines
CRC Extended input data inversion modes
CRC Extended exported constants

Defines

#define | CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000U)
#define | CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)
#define | CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)
#define | CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)
#define | IS_CRC_INPUTDATA_INVERSION_MODE(__MODE__)

Define Documentation

#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)

Definition at line 68 of file stm32h7xx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)

Definition at line 69 of file stm32h7xx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000U)

Definition at line 67 of file stm32h7xx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)

Definition at line 70 of file stm32h7xx_hal_crc_ex.h.

#define IS_CRC_INPUTDATA_INVERSION_MODE ( __MODE__ )
Value:
(((__MODE__) == CRC_INPUTDATA_INVERSION_NONE) || \
                                                       ((__MODE__) == CRC_INPUTDATA_INVERSION_BYTE) || \
                                                       ((__MODE__) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
                                                       ((__MODE__) == CRC_INPUTDATA_INVERSION_WORD))

Definition at line 72 of file stm32h7xx_hal_crc_ex.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Input_Data_Reverse().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRC Extended output data inversion modes

Defines
CRC Extended output data inversion modes
CRC Extended exported constants

Defines

#define | CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000U)
#define | CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)
#define | IS_CRC_OUTPUTDATA_INVERSION_MODE(__MODE__)

Define Documentation

#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000U)

Definition at line 83 of file stm32h7xx_hal_crc_ex.h.

#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)

Definition at line 84 of file stm32h7xx_hal_crc_ex.h.

#define IS_CRC_OUTPUTDATA_INVERSION_MODE ( __MODE__ )
Value:
(((__MODE__) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
                                                       ((__MODE__) == CRC_OUTPUTDATA_INVERSION_ENABLE))

Definition at line 86 of file stm32h7xx_hal_crc_ex.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Output_Data_Reverse().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: CRC Extended exported macros

Defines
CRC Extended exported macros
CRCEx

Defines

#define | __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
Set CRC output reversal.
#define | __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
Unset CRC output reversal.
#define | __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
Set CRC non-default polynomial.

Define Documentation

#define __HAL_CRC_OUTPUTREVERSAL_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))

Unset CRC output reversal.

Parameters:
__HANDLE__ : CRC handle
Return values:
None.

Definition at line 114 of file stm32h7xx_hal_crc_ex.h.

#define __HAL_CRC_OUTPUTREVERSAL_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)

Set CRC output reversal.

Parameters:
__HANDLE__ : CRC handle
Return values:
None.

Definition at line 107 of file stm32h7xx_hal_crc_ex.h.

#define __HAL_CRC_POLYNOMIAL_CONFIG | ( | __HANDLE__,
 |  | __POLYNOMIAL__
 | ) | ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))

Set CRC non-default polynomial.

Parameters:
__HANDLE__ : CRC handle
__POLYNOMIAL__,: 7, 8, 16 or 32-bit polynomial
Return values:
None.

Definition at line 122 of file stm32h7xx_hal_crc_ex.h.

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Extended CRC features functions

Functions
Extended CRC features functions
CRC Extended Exported Functions

Extended CRC features functions. More...

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initializes the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Extended CRC features functions.

 ===============================================================================
            ##### CRC Extended features functions #####
 ===============================================================================
    [..]
This subsection provides function allowing to:
      (+) Set CRC polynomial if different from default one.

Function Documentation

HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | InputReverseMode
 | ) |  |

Set the Reverse Input data mode.

Parameters:
hcrc,: CRC handle
InputReverseMode,: Input Data inversion mode This parameter can be one of the following values:
  • CRC_INPUTDATA_INVERSION_NONE: no change in bit order (default value)
  • CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal
  • CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal
  • CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal
Return values:
HAL status

Definition at line 174 of file stm32h7xx_hal_crc_ex.c.

References assert_param, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::Instance, IS_CRC_INPUTDATA_INVERSION_MODE, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | OutputReverseMode
 | ) |  |

Set the Reverse Output data mode.

Parameters:
hcrc,: CRC handle
OutputReverseMode,: Output Data inversion mode This parameter can be one of the following values:
  • CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)
  • CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD)
Return values:
HAL status

Definition at line 200 of file stm32h7xx_hal_crc_ex.c.

References assert_param, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::Instance, IS_CRC_OUTPUTDATA_INVERSION_MODE, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | Pol,
 |  | uint32_t | PolyLength
 | ) |  |

Initializes the CRC polynomial if different from default one.

Parameters:
hcrc,: CRC handle
Pol,: CRC generating polynomial (7, 8, 16 or 32-bit long) This parameter is written in normal representation, e.g. for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
PolyLength,: CRC polynomial length This parameter can be one of the following values:
  • CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)
  • CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)
  • CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16)
  • CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32)
Return values:
HAL status

Definition at line 108 of file stm32h7xx_hal_crc_ex.c.

References assert_param, CRC_POLYLENGTH_16B, CRC_POLYLENGTH_32B, CRC_POLYLENGTH_7B, CRC_POLYLENGTH_8B, HAL_CRC_LENGTH_16B, HAL_CRC_LENGTH_7B, HAL_CRC_LENGTH_8B, CRC_HandleTypeDef::Instance, and IS_CRC_POL_LENGTH.

Referenced by HAL_CRC_Init().

Generated on Fri Apr 28 2017 15:42:44 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: GPIO Alternate Function Selection

Defines
GPIO Alternate Function Selection
GPIO Exported Constants

Defines

#define | GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
AF 0 selection.
#define | GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define | GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define | GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
#define | GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
#define | GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
AF 1 selection.
#define | GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#define | GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
#define | GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
#define | GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
#define | GPIO_AF1_HRTIM1 ((uint8_t)0x01) /* HRTIM1 Alternate Function mapping */
#define | GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
AF 2 selection.
#define | GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define | GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
#define | GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */
#define | GPIO_AF2_HRTIM1 ((uint8_t)0x02) /* HRTIM2 Alternate Function mapping */
#define | GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */
#define | GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
AF 3 selection.
#define | GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */
#define | GPIO_AF3_DFSDM1 ((uint8_t)0x03) /* DFSDM Alternate Function mapping */
#define | GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM3 Alternate Function mapping */
#define | GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */
#define | GPIO_AF3_LPTIM4 ((uint8_t)0x03) /* LPTIM4 Alternate Function mapping */
#define | GPIO_AF3_LPTIM5 ((uint8_t)0x03) /* LPTIM5 Alternate Function mapping */
#define | GPIO_AF3_LPUART ((uint8_t)0x03) /* LPUART Alternate Function mapping */
#define | GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
AF 4 selection.
#define | GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define | GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#define | GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
#define | GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */
#define | GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
#define | GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */
#define | GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
#define | GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM Alternate Function mapping */
#define | GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
AF 5 selection.
#define | GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#define | GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */
#define | GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
#define | GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
#define | GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
#define | GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */
#define | GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
AF 6 selection.
#define | GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
#define | GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
#define | GPIO_AF6_SAI3 ((uint8_t)0x06) /* SAI3 Alternate Function mapping */
#define | GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */
#define | GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */
#define | GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */
#define | GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */
AF 7 selection.
#define | GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */
#define | GPIO_AF7_SPI6 ((uint8_t)0x07) /* SPI6 Alternate Function mapping */
#define | GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
#define | GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define | GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#define | GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */
#define | GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */
#define | GPIO_AF7_DFSDM1 ((uint8_t)0x07) /* DFSDM Alternate Function mapping */
#define | GPIO_AF7_SDIO1 ((uint8_t)0x07) /* SDIO1 Alternate Function mapping */
#define | GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */
AF 8 selection.
#define | GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
#define | GPIO_AF8_SAI4 ((uint8_t)0x08) /* SAI4 Alternate Function mapping */
#define | GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define | GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define | GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
#define | GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */
#define | GPIO_AF8_LPUART ((uint8_t)0x08) /* LPUART Alternate Function mapping */
#define | GPIO_AF8_SDIO1 ((uint8_t)0x08) /* SDIO1 Alternate Function mapping */
#define | GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
AF 9 selection.
#define | GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */
#define | GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
#define | GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
#define | GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */
#define | GPIO_AF9_SDIO2 ((uint8_t)0x09) /* SDIO2 Alternate Function mapping */
#define | GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */
#define | GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */
#define | GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */
#define | GPIO_AF9_SAI4 ((uint8_t)0x09) /* SAI4 Alternate Function mapping */
#define | GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */
AF 10 selection.
#define | GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */
#define | GPIO_AF10_SAI4 ((uint8_t)0xA) /* SAI4 Alternate Function mapping */
#define | GPIO_AF10_SDIO2 ((uint8_t)0xA) /* SDIO2 Alternate Function mapping */
#define | GPIO_AF10_OTG2_HS ((uint8_t)0xA) /* OTG2_HS Alternate Function mapping */
#define | GPIO_AF10_OTG1_FS ((uint8_t)0xA) /* OTG1_FS Alternate Function mapping */
#define | GPIO_AF10_COMP1 ((uint8_t)0xA) /* COMP1 Alternate Function mapping */
#define | GPIO_AF10_COMP2 ((uint8_t)0xA) /* COMP2 Alternate Function mapping */
#define | GPIO_AF10_LTDC ((uint8_t)0xA) /* LTDC Alternate Function mapping */
#define | GPIO_AF11_SWP ((uint8_t)0x0B) /* SWP Alternate Function mapping */
AF 11 selection.
#define | GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */
#define | GPIO_AF11_MDIOS ((uint8_t)0x0B) /* MDIOS Alternate Function mapping */
#define | GPIO_AF11_OTG1_HS ((uint8_t)0x0B) /* OTG1_HS Alternate Function mapping */
#define | GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */
#define | GPIO_AF11_SDIO2 ((uint8_t)0x0B) /* SDIO2 Alternate Function mapping */
#define | GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM Alternate Function mapping */
#define | GPIO_AF11_COMP1 ((uint8_t)0x0B) /* COMP1 Alternate Function mapping */
#define | GPIO_AF11_COMP2 ((uint8_t)0x0B) /* COMP2 Alternate Function mapping */
#define | GPIO_AF11_I2C4 ((uint8_t)0x0B) /* I2C4 Alternate Function mapping */
#define | GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
AF 12 selection.
#define | GPIO_AF12_SDIO1 ((uint8_t)0xC) /* SDIO1 Alternate Function mapping */
#define | GPIO_AF12_MDIOS ((uint8_t)0xC) /* MDIOS Alternate Function mapping */
#define | GPIO_AF12_OTG2_FS ((uint8_t)0xC) /* OTG2_FS Alternate Function mapping */
#define | GPIO_AF12_COMP1 ((uint8_t)0xC) /* COMP1 Alternate Function mapping */
#define | GPIO_AF12_COMP2 ((uint8_t)0xC) /* COMP2 Alternate Function mapping */
#define | GPIO_AF12_LTDC ((uint8_t)0xC) /* LTDC Alternate Function mapping */
#define | GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
AF 13 selection.
#define | GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */
#define | GPIO_AF13_COMP1 ((uint8_t)0x0D) /* COMP1 Alternate Function mapping */
#define | GPIO_AF13_COMP2 ((uint8_t)0x0D) /* COMP2 Alternate Function mapping */
#define | GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */
#define | GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */
AF 14 selection.
#define | GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */
#define | GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
AF 15 selection.
#define | IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)

Define Documentation

#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */

Definition at line 73 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */

Definition at line 71 of file stm32h7xx_hal_gpio_ex.h.

Referenced by HAL_RCC_MCOConfig().

#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */

AF 0 selection.

Definition at line 70 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */

Definition at line 72 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */

Definition at line 74 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF10_COMP1 ((uint8_t)0xA) /* COMP1 Alternate Function mapping */

Definition at line 194 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF10_COMP2 ((uint8_t)0xA) /* COMP2 Alternate Function mapping */

Definition at line 195 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF10_LTDC ((uint8_t)0xA) /* LTDC Alternate Function mapping */

Definition at line 196 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF10_OTG1_FS ((uint8_t)0xA) /* OTG1_FS Alternate Function mapping */

Definition at line 193 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF10_OTG2_HS ((uint8_t)0xA) /* OTG2_HS Alternate Function mapping */

Definition at line 192 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */

AF 10 selection.

Definition at line 188 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */

Definition at line 189 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF10_SAI4 ((uint8_t)0xA) /* SAI4 Alternate Function mapping */

Definition at line 190 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF10_SDIO2 ((uint8_t)0xA) /* SDIO2 Alternate Function mapping */

Definition at line 191 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_COMP1 ((uint8_t)0x0B) /* COMP1 Alternate Function mapping */

Definition at line 208 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_COMP2 ((uint8_t)0x0B) /* COMP2 Alternate Function mapping */

Definition at line 209 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM Alternate Function mapping */

Definition at line 207 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */

Definition at line 202 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_I2C4 ((uint8_t)0x0B) /* I2C4 Alternate Function mapping */

Definition at line 210 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_MDIOS ((uint8_t)0x0B) /* MDIOS Alternate Function mapping */

Definition at line 203 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_OTG1_HS ((uint8_t)0x0B) /* OTG1_HS Alternate Function mapping */

Definition at line 204 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_SDIO2 ((uint8_t)0x0B) /* SDIO2 Alternate Function mapping */

Definition at line 206 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_SWP ((uint8_t)0x0B) /* SWP Alternate Function mapping */

AF 11 selection.

Definition at line 201 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */

Definition at line 205 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF12_COMP1 ((uint8_t)0xC) /* COMP1 Alternate Function mapping */

Definition at line 219 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF12_COMP2 ((uint8_t)0xC) /* COMP2 Alternate Function mapping */

Definition at line 220 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */

AF 12 selection.

Definition at line 215 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF12_LTDC ((uint8_t)0xC) /* LTDC Alternate Function mapping */

Definition at line 221 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF12_MDIOS ((uint8_t)0xC) /* MDIOS Alternate Function mapping */

Definition at line 217 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF12_OTG2_FS ((uint8_t)0xC) /* OTG2_FS Alternate Function mapping */

Definition at line 218 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF12_SDIO1 ((uint8_t)0xC) /* SDIO1 Alternate Function mapping */

Definition at line 216 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF13_COMP1 ((uint8_t)0x0D) /* COMP1 Alternate Function mapping */

Definition at line 228 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF13_COMP2 ((uint8_t)0x0D) /* COMP2 Alternate Function mapping */

Definition at line 229 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */

AF 13 selection.

Definition at line 226 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */

Definition at line 227 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */

Definition at line 230 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */

AF 14 selection.

Definition at line 235 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */

Definition at line 236 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */

AF 15 selection.

Definition at line 241 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF1_HRTIM1 ((uint8_t)0x01) /* HRTIM1 Alternate Function mapping */

Definition at line 84 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */

Definition at line 83 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */

AF 1 selection.

Definition at line 79 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */

Definition at line 81 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */

Definition at line 82 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */

Definition at line 80 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF2_HRTIM1 ((uint8_t)0x02) /* HRTIM2 Alternate Function mapping */

Definition at line 93 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */

Definition at line 94 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */

Definition at line 92 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */

AF 2 selection.

Definition at line 89 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */

Definition at line 90 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */

Definition at line 91 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF3_DFSDM1 ((uint8_t)0x03) /* DFSDM Alternate Function mapping */

Definition at line 101 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM3 Alternate Function mapping */

Definition at line 102 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */

Definition at line 100 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */

Definition at line 103 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF3_LPTIM4 ((uint8_t)0x03) /* LPTIM4 Alternate Function mapping */

Definition at line 104 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF3_LPTIM5 ((uint8_t)0x03) /* LPTIM5 Alternate Function mapping */

Definition at line 105 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF3_LPUART ((uint8_t)0x03) /* LPUART Alternate Function mapping */

Definition at line 106 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */

AF 3 selection.

Definition at line 99 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */

Definition at line 116 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM Alternate Function mapping */

Definition at line 119 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */

AF 4 selection.

Definition at line 111 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */

Definition at line 112 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */

Definition at line 113 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */

Definition at line 114 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */

Definition at line 117 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */

Definition at line 115 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */

Definition at line 118 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */

Definition at line 130 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */

AF 5 selection.

Definition at line 124 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */

Definition at line 125 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */

Definition at line 126 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */

Definition at line 127 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */

Definition at line 128 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */

Definition at line 129 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */

Definition at line 141 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */

Definition at line 140 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */

Definition at line 138 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF6_SAI3 ((uint8_t)0x06) /* SAI3 Alternate Function mapping */

Definition at line 139 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */

AF 6 selection.

Definition at line 136 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */

Definition at line 137 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */

Definition at line 142 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF7_DFSDM1 ((uint8_t)0x07) /* DFSDM Alternate Function mapping */

Definition at line 155 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF7_SDIO1 ((uint8_t)0x07) /* SDIO1 Alternate Function mapping */

Definition at line 156 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */

AF 7 selection.

Definition at line 147 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */

Definition at line 148 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF7_SPI6 ((uint8_t)0x07) /* SPI6 Alternate Function mapping */

Definition at line 149 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */

Definition at line 154 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */

Definition at line 150 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */

Definition at line 151 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */

Definition at line 152 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */

Definition at line 153 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF8_LPUART ((uint8_t)0x08) /* LPUART Alternate Function mapping */

Definition at line 168 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */

Definition at line 162 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF8_SAI4 ((uint8_t)0x08) /* SAI4 Alternate Function mapping */

Definition at line 163 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF8_SDIO1 ((uint8_t)0x08) /* SDIO1 Alternate Function mapping */

Definition at line 169 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */

Definition at line 167 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */

AF 8 selection.

Definition at line 161 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */

Definition at line 164 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */

Definition at line 165 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */

Definition at line 166 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */

AF 9 selection.

Definition at line 174 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */

Definition at line 175 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */

Definition at line 182 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */

Definition at line 180 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */

Definition at line 178 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF9_SAI4 ((uint8_t)0x09) /* SAI4 Alternate Function mapping */

Definition at line 183 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF9_SDIO2 ((uint8_t)0x09) /* SDIO2 Alternate Function mapping */

Definition at line 179 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */

Definition at line 181 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */

Definition at line 176 of file stm32h7xx_hal_gpio_ex.h.

#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */

Definition at line 177 of file stm32h7xx_hal_gpio_ex.h.

#define IS_GPIO_AF ( AF ) ((AF) <= (uint8_t)0x0F)

Definition at line 243 of file stm32h7xx_hal_gpio_ex.h.

Referenced by HAL_GPIO_Init().

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STM32H753xx HAL User Manual: GPIO Exported Macros

GPIO Exported Macros
GPIOEx
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STM32H753xx HAL User Manual: GPIO Exported Functions

GPIO Exported Functions
GPIOEx
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STM32H753xx HAL User Manual: GPIO Private Constants

Defines
GPIO Private Constants
GPIOEx

Defines

#define | GPIOA_PIN_AVAILABLE GPIO_PIN_All
GPIO pin available on the platform.
#define | GPIOB_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOC_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOD_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOE_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOF_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOG_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOI_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOJ_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOH_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOK_PIN_AVAILABLE

Define Documentation

#define GPIOA_PIN_AVAILABLE GPIO_PIN_All

GPIO pin available on the platform.

Definition at line 281 of file stm32h7xx_hal_gpio_ex.h.

#define GPIOB_PIN_AVAILABLE GPIO_PIN_All

Definition at line 282 of file stm32h7xx_hal_gpio_ex.h.

#define GPIOC_PIN_AVAILABLE GPIO_PIN_All

Definition at line 283 of file stm32h7xx_hal_gpio_ex.h.

#define GPIOD_PIN_AVAILABLE GPIO_PIN_All

Definition at line 284 of file stm32h7xx_hal_gpio_ex.h.

#define GPIOE_PIN_AVAILABLE GPIO_PIN_All

Definition at line 285 of file stm32h7xx_hal_gpio_ex.h.

#define GPIOF_PIN_AVAILABLE GPIO_PIN_All

Definition at line 286 of file stm32h7xx_hal_gpio_ex.h.

#define GPIOG_PIN_AVAILABLE GPIO_PIN_All

Definition at line 287 of file stm32h7xx_hal_gpio_ex.h.

#define GPIOH_PIN_AVAILABLE GPIO_PIN_All

Definition at line 290 of file stm32h7xx_hal_gpio_ex.h.

#define GPIOI_PIN_AVAILABLE GPIO_PIN_All

Definition at line 288 of file stm32h7xx_hal_gpio_ex.h.

#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All

Definition at line 289 of file stm32h7xx_hal_gpio_ex.h.

#define GPIOK_PIN_AVAILABLE
Value:
(GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \
                              GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)

Definition at line 291 of file stm32h7xx_hal_gpio_ex.h.

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STM32H753xx HAL User Manual: GPIO Get Port Index

Defines
GPIO Get Port Index
GPIO Private Macros

Defines

#define GPIO_GET_INDEX(__GPIOx__)

Define Documentation

#define GPIO_GET_INDEX ( __GPIOx__ )
Value:
(uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
                                              ((__GPIOx__) == (GPIOB))? 1U :\
                                              ((__GPIOx__) == (GPIOC))? 2U :\
                                              ((__GPIOx__) == (GPIOD))? 3U :\
                                              ((__GPIOx__) == (GPIOE))? 4U :\
                                              ((__GPIOx__) == (GPIOF))? 5U :\
                                              ((__GPIOx__) == (GPIOG))? 6U :\
                                              ((__GPIOx__) == (GPIOH))? 7U :\
                                              ((__GPIOx__) == (GPIOI))? 8U :\
                                              ((__GPIOx__) == (GPIOJ))? 9U : 10U)

Definition at line 305 of file stm32h7xx_hal_gpio_ex.h.

Referenced by HAL_GPIO_DeInit(), and HAL_GPIO_Init().

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STM32H753xx HAL User Manual: GPIO Check Alternate Function

GPIO Check Alternate Function
GPIO Private Macros
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STM32H753xx HAL User Manual: GPIO Private Macros

Modules | Defines
GPIO Private Macros
GPIOEx

Modules

GPIO Get Port Index
GPIO Check Alternate Function

Defines

#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__, __PIN__)

Define Documentation

#define IS_GPIO_PIN_AVAILABLE | ( | __INSTANCE__,
 |  | __PIN__
 | ) |
Value:
((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
            (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \
            (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \
            (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \
            (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \
            (((__INSTANCE__) == GPIOF) && (((__PIN__) & (GPIOF_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOF_PIN_AVAILABLE)) == (GPIOF_PIN_AVAILABLE))) || \
            (((__INSTANCE__) == GPIOG) && (((__PIN__) & (GPIOG_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOG_PIN_AVAILABLE)) == (GPIOG_PIN_AVAILABLE))) || \
            (((__INSTANCE__) == GPIOI) && (((__PIN__) & (GPIOI_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOI_PIN_AVAILABLE)) == (GPIOI_PIN_AVAILABLE))) || \
            (((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || \
            (((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || \
            (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))

Definition at line 319 of file stm32h7xx_hal_gpio_ex.h.

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STM32H753xx HAL User Manual: GPIO Private Functions

GPIO Private Functions
GPIOEx
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STM32H753xx HAL User Manual: HCD State Structure definition

Typedefs | Enumerations
HCD State Structure definition
HCD Exported Types

Typedefs

typedef USB_OTG_GlobalTypeDef | HCD_TypeDef
typedef USB_OTG_CfgTypeDef | HCD_InitTypeDef
typedef USB_OTG_HCTypeDef | HCD_HCTypeDef
typedef USB_OTG_URBStateTypeDef | HCD_URBStateTypeDef
typedef USB_OTG_HCStateTypeDef | HCD_HCStateTypeDef

Enumerations

enum HCD_StateTypeDef {
HAL_HCD_STATE_RESET = 0x00, HAL_HCD_STATE_READY = 0x01, HAL_HCD_STATE_ERROR = 0x02, HAL_HCD_STATE_BUSY = 0x03,
HAL_HCD_STATE_TIMEOUT = 0x04
}

Typedef Documentation

typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef

Definition at line 79 of file stm32h7xx_hal_hcd.h.

typedef USB_OTG_HCTypeDef HCD_HCTypeDef

Definition at line 77 of file stm32h7xx_hal_hcd.h.

typedef USB_OTG_CfgTypeDef HCD_InitTypeDef

Definition at line 76 of file stm32h7xx_hal_hcd.h.

typedef USB_OTG_GlobalTypeDef HCD_TypeDef

Definition at line 75 of file stm32h7xx_hal_hcd.h.

typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef

Definition at line 78 of file stm32h7xx_hal_hcd.h.

Enumeration Type Documentation

enum HCD_StateTypeDef
Enumerator:
HAL_HCD_STATE_RESET
HAL_HCD_STATE_READY
HAL_HCD_STATE_ERROR
HAL_HCD_STATE_BUSY
HAL_HCD_STATE_TIMEOUT

Definition at line 66 of file stm32h7xx_hal_hcd.h.

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STM32H753xx HAL User Manual: HCD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HCD_HandleTypeDef Struct Reference
HCD Handle Structure definition

#include <stm32h7xx_hal_hcd.h>

Data Fields

HCD_TypeDef * Instance
HCD_InitTypeDef Init
HCD_HCTypeDef | hc [15]
HAL_LockTypeDef | Lock
__IO HCD_StateTypeDef | State
void * | pData

Detailed Description

Definition at line 87 of file stm32h7xx_hal_hcd.h.

Field Documentation

HCD_HCTypeDef HCD_HandleTypeDef::hc[15]

Host channels parameters

Definition at line 91 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_HC_GetState(), HAL_HCD_HC_GetURBState(), HAL_HCD_HC_GetXferCount(), HAL_HCD_HC_Init(), HAL_HCD_HC_SubmitRequest(), HCD_HC_IN_IRQHandler(), HCD_HC_OUT_IRQHandler(), and HCD_RXQLVL_IRQHandler().

HCD_InitTypeDef HCD_HandleTypeDef::Init

HCD required parameters

Definition at line 90 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_HC_SubmitRequest(), HAL_HCD_Init(), HAL_HCD_IRQHandler(), HCD_HC_IN_IRQHandler(), and HCD_Port_IRQHandler().

HCD_TypeDef* HCD_HandleTypeDef::Instance

Register base address

Definition at line 89 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_GetCurrentFrame(), HAL_HCD_GetCurrentSpeed(), HAL_HCD_HC_Halt(), HAL_HCD_HC_Init(), HAL_HCD_HC_SubmitRequest(), HAL_HCD_Init(), HAL_HCD_IRQHandler(), HAL_HCD_ResetPort(), HAL_HCD_Start(), HAL_HCD_Stop(), HCD_HC_IN_IRQHandler(), HCD_HC_OUT_IRQHandler(), HCD_Port_IRQHandler(), and HCD_RXQLVL_IRQHandler().

HAL_LockTypeDef HCD_HandleTypeDef::Lock

HCD peripheral status

Definition at line 92 of file stm32h7xx_hal_hcd.h.

void* HCD_HandleTypeDef::pData

Pointer Stack Handler

Definition at line 94 of file stm32h7xx_hal_hcd.h.

__IO HCD_StateTypeDef HCD_HandleTypeDef::State

HCD communication state

Definition at line 93 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_DeInit(), HAL_HCD_GetState(), and HAL_HCD_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_hcd.h
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STM32H753xx HAL User Manual: HCD Speed

Defines
HCD Speed
HCD Exported Constants

Defines

#define | HCD_SPEED_HIGH 0
#define | HCD_SPEED_LOW 2
#define | HCD_SPEED_FULL 3

Define Documentation

#define HCD_SPEED_FULL 3

Definition at line 113 of file stm32h7xx_hal_hcd.h.

Referenced by HCD_Port_IRQHandler().

#define HCD_SPEED_HIGH 0

Definition at line 111 of file stm32h7xx_hal_hcd.h.

Referenced by HCD_Port_IRQHandler().

#define HCD_SPEED_LOW 2

Definition at line 112 of file stm32h7xx_hal_hcd.h.

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STM32H753xx HAL User Manual: HCD PHY Module

Defines
HCD PHY Module
HCD Exported Constants

Defines

#define | HCD_PHY_ULPI 1
#define | HCD_PHY_EMBEDDED 2

Define Documentation

#define HCD_PHY_EMBEDDED 2

Definition at line 122 of file stm32h7xx_hal_hcd.h.

#define HCD_PHY_ULPI 1

Definition at line 121 of file stm32h7xx_hal_hcd.h.

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STM32H753xx HAL User Manual: HCD Exported Macros

Defines
HCD Exported Macros
HCD

macros to handle interrupts and specific clock configurations More...

Defines

#define | __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define | __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
#define | __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
#define | __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
#define | __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
#define | __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
#define | __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)

Detailed Description

macros to handle interrupts and specific clock configurations

Define Documentation

#define __HAL_HCD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))

Definition at line 140 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_IRQHandler().

#define __HAL_HCD_CLEAR_HC_INT | ( | chnum,
 |  | __INTERRUPT__
 | ) | (USBx_HC(chnum)->HCINT = (__INTERRUPT__))

Definition at line 143 of file stm32h7xx_hal_hcd.h.

Referenced by HCD_HC_IN_IRQHandler(), and HCD_HC_OUT_IRQHandler().

#define __HAL_HCD_DISABLE ( __HANDLE__ ) USB_DisableGlobalInt ((__HANDLE__)->Instance)

Definition at line 137 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_DeInit(), and HAL_HCD_Init().

#define __HAL_HCD_ENABLE ( __HANDLE__ ) USB_EnableGlobalInt ((__HANDLE__)->Instance)

Definition at line 136 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_Start().

#define __HAL_HCD_GET_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))

Definition at line 139 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_IRQHandler().

#define __HAL_HCD_IS_INVALID_INTERRUPT ( __HANDLE__ ) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)

Definition at line 141 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_IRQHandler().

#define __HAL_HCD_MASK_ACK_HC_INT ( chnum ) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)

Definition at line 146 of file stm32h7xx_hal_hcd.h.

#define __HAL_HCD_MASK_HALT_HC_INT ( chnum ) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)

Definition at line 144 of file stm32h7xx_hal_hcd.h.

Referenced by HCD_HC_IN_IRQHandler(), and HCD_HC_OUT_IRQHandler().

#define __HAL_HCD_UNMASK_ACK_HC_INT ( chnum ) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)

Definition at line 147 of file stm32h7xx_hal_hcd.h.

#define __HAL_HCD_UNMASK_HALT_HC_INT ( chnum ) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)

Definition at line 145 of file stm32h7xx_hal_hcd.h.

Referenced by HCD_HC_IN_IRQHandler(), and HCD_HC_OUT_IRQHandler().

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STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
HCD Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_HCD_Init (HCD_HandleTypeDef *hhcd)
Initialize the host driver.
HAL_StatusTypeDef | HAL_HCD_HC_Init (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
Initialize a host channel.
HAL_StatusTypeDef | HAL_HCD_HC_Halt (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
Halt a host channel.
HAL_StatusTypeDef | HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the host driver.
__weak void | HAL_HCD_MspInit (HCD_HandleTypeDef *hhcd)
Initializes the HCD MSP.
__weak void | HAL_HCD_MspDeInit (HCD_HandleTypeDef *hhcd)
DeInitializes HCD MSP.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
          ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:

Function Documentation

HAL_StatusTypeDef HAL_HCD_DeInit ( HCD_HandleTypeDef * hhcd )

DeInitialize the host driver.

Parameters:
hhcd,: HCD handle
Return values:
HAL status

Definition at line 237 of file stm32h7xx_hal_hcd.c.

References __HAL_HCD_DISABLE, HAL_HCD_MspDeInit(), HAL_HCD_STATE_BUSY, HAL_HCD_STATE_RESET, and HCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HCD_HC_Halt | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num
 | ) |  |

Halt a host channel.

Parameters:
hhcd,: HCD handle
ch_num,: Channel number. This parameter can be a value from 1 to 15
Return values:
HAL status

Definition at line 221 of file stm32h7xx_hal_hcd.c.

References HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_HC_Init | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num,
 |  | uint8_t | epnum,
 |  | uint8_t | dev_address,
 |  | uint8_t | speed,
 |  | uint8_t | ep_type,
 |  | uint16_t | mps
 | ) |  |

Initialize a host channel.

Parameters:
hhcd,: HCD handle
ch_num,: Channel number. This parameter can be a value from 1 to 15
epnum,: Endpoint number. This parameter can be a value from 1 to 15
dev_address : Current device address This parameter can be a value from 0 to 255
speed,: Current device speed. This parameter can be one of these values: HCD_SPEED_HIGH: High speed mode, HCD_SPEED_FULL: Full speed mode, HCD_SPEED_LOW: Low speed mode
ep_type,: Endpoint Type. This parameter can be one of these values: EP_TYPE_CTRL: Control type, EP_TYPE_ISOC: Isochronous type, EP_TYPE_BULK: Bulk type, EP_TYPE_INTR: Interrupt type
mps,: Max Packet Size. This parameter can be a value from 0 to32K
Return values:
HAL status

Definition at line 182 of file stm32h7xx_hal_hcd.c.

References HCD_HandleTypeDef::hc, and HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_Init ( HCD_HandleTypeDef * hhcd )

Initialize the host driver.

Parameters:
hhcd,: HCD handle
Return values:
HAL status

Definition at line 125 of file stm32h7xx_hal_hcd.c.

References __HAL_HCD_DISABLE, assert_param, HAL_HCD_MspInit(), HAL_HCD_STATE_BUSY, HAL_HCD_STATE_READY, HCD_HandleTypeDef::Init, HCD_HandleTypeDef::Instance, IS_HCD_ALL_INSTANCE, and HCD_HandleTypeDef::State.

void HAL_HCD_MspDeInit ( HCD_HandleTypeDef * hhcd )

DeInitializes HCD MSP.

Parameters:
hhcd,: HCD handle
Return values:
None

Definition at line 274 of file stm32h7xx_hal_hcd.c.

Referenced by HAL_HCD_DeInit().

void HAL_HCD_MspInit ( HCD_HandleTypeDef * hhcd )

Initializes the HCD MSP.

Parameters:
hhcd,: HCD handle
Return values:
None

Definition at line 262 of file stm32h7xx_hal_hcd.c.

Referenced by HAL_HCD_Init().

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STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
HCD Exported Functions

HCD IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_HCD_HC_SubmitRequest (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t direction, uint8_t ep_type, uint8_t token, uint8_t *pbuff, uint16_t length, uint8_t do_ping)
Submit a new URB for processing.
void | HAL_HCD_IRQHandler (HCD_HandleTypeDef *hhcd)
This function handles HCD interrupt request.
__weak void | HAL_HCD_SOF_Callback (HCD_HandleTypeDef *hhcd)
SOF callback.
__weak void | HAL_HCD_Connect_Callback (HCD_HandleTypeDef *hhcd)
Connexion Event callback.
__weak void | HAL_HCD_Disconnect_Callback (HCD_HandleTypeDef *hhcd)
Disconnexion Event callback.
__weak void | HAL_HCD_HC_NotifyURBChange_Callback (HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
Notify URB state change callback.

Detailed Description

HCD IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the USB Host Data
    Transfer

Function Documentation

void HAL_HCD_Connect_Callback ( HCD_HandleTypeDef * hhcd )

Connexion Event callback.

Parameters:
hhcd,: HCD handle
Return values:
None

Definition at line 562 of file stm32h7xx_hal_hcd.c.

Referenced by HCD_Port_IRQHandler().

void HAL_HCD_Disconnect_Callback ( HCD_HandleTypeDef * hhcd )

Disconnexion Event callback.

Parameters:
hhcd,: HCD handle
Return values:
None

Definition at line 574 of file stm32h7xx_hal_hcd.c.

Referenced by HAL_HCD_IRQHandler().

void HAL_HCD_HC_NotifyURBChange_Callback | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum,
 |  | HCD_URBStateTypeDef | urb_state
 | ) |  |

Notify URB state change callback.

Parameters:
hhcd,: HCD handle
chnum,: Channel number. This parameter can be a value from 1 to 15
urb_state,: This parameter can be one of these values: URB_IDLE/ URB_DONE/ URB_NOTREADY/ URB_NYET/ URB_ERROR/ URB_STALL/
Return values:
None

Definition at line 596 of file stm32h7xx_hal_hcd.c.

Referenced by HCD_HC_IN_IRQHandler(), and HCD_HC_OUT_IRQHandler().

HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num,
 |  | uint8_t | direction,
 |  | uint8_t | ep_type,
 |  | uint8_t | token,
 |  | uint8_t * | pbuff,
 |  | uint16_t | length,
 |  | uint8_t | do_ping
 | ) |  |

Submit a new URB for processing.

Parameters:
hhcd,: HCD handle
ch_num,: Channel number. This parameter can be a value from 1 to 15
direction,: Channel number. This parameter can be one of these values: 0 : Output / 1 : Input
ep_type,: Endpoint Type. This parameter can be one of these values: EP_TYPE_CTRL: Control type/ EP_TYPE_ISOC: Isochronous type/ EP_TYPE_BULK: Bulk type/ EP_TYPE_INTR: Interrupt type/
token,: Endpoint Type. This parameter can be one of these values: 0: HC_PID_SETUP / 1: HC_PID_DATA1
pbuff,: pointer to URB data
length,: Length of URB data
do_ping,: activate do ping protocol (for high speed only). This parameter can be one of these values: 0 : do ping inactive / 1 : do ping active
Return values:
HAL status

Definition at line 323 of file stm32h7xx_hal_hcd.c.

References HCD_HandleTypeDef::hc, HCD_HandleTypeDef::Init, and HCD_HandleTypeDef::Instance.

void HAL_HCD_IRQHandler ( HCD_HandleTypeDef * hhcd )

This function handles HCD interrupt request.

Parameters:
hhcd,: HCD handle
Return values:
None

Definition at line 447 of file stm32h7xx_hal_hcd.c.

References __HAL_HCD_CLEAR_FLAG, __HAL_HCD_GET_FLAG, __HAL_HCD_IS_INVALID_INTERRUPT, HAL_HCD_Disconnect_Callback(), HAL_HCD_SOF_Callback(), HCD_HC_IN_IRQHandler(), HCD_HC_OUT_IRQHandler(), HCD_Port_IRQHandler(), HCD_RXQLVL_IRQHandler(), HCD_HandleTypeDef::Init, and HCD_HandleTypeDef::Instance.

void HAL_HCD_SOF_Callback ( HCD_HandleTypeDef * hhcd )

SOF callback.

Parameters:
hhcd,: HCD handle
Return values:
None

Definition at line 550 of file stm32h7xx_hal_hcd.c.

Referenced by HAL_HCD_IRQHandler().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
HCD Exported Functions

Peripheral management functions. More...

Functions

HAL_StatusTypeDef | HAL_HCD_Start (HCD_HandleTypeDef *hhcd)
Start the host driver.
HAL_StatusTypeDef | HAL_HCD_Stop (HCD_HandleTypeDef *hhcd)
Stop the host driver.
HAL_StatusTypeDef | HAL_HCD_ResetPort (HCD_HandleTypeDef *hhcd)
Reset the host port.

Detailed Description

Peripheral management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the HCD data
    transfers.

Function Documentation

HAL_StatusTypeDef HAL_HCD_ResetPort ( HCD_HandleTypeDef * hhcd )

Reset the host port.

Parameters:
hhcd,: HCD handle
Return values:
HAL status

Definition at line 655 of file stm32h7xx_hal_hcd.c.

References HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_Start ( HCD_HandleTypeDef * hhcd )

Start the host driver.

Parameters:
hhcd,: HCD handle
Return values:
HAL status

Definition at line 627 of file stm32h7xx_hal_hcd.c.

References __HAL_HCD_ENABLE, and HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_Stop ( HCD_HandleTypeDef * hhcd )

Stop the host driver.

Parameters:
hhcd,: HCD handle
Return values:
HAL status

Definition at line 642 of file stm32h7xx_hal_hcd.c.

References HCD_HandleTypeDef::Instance.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
HCD Exported Functions

Peripheral State functions. More...

Functions

HCD_StateTypeDef | HAL_HCD_GetState (HCD_HandleTypeDef *hhcd)
Return the HCD state.
HCD_URBStateTypeDef | HAL_HCD_HC_GetURBState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return URB state for a channel.
uint32_t | HAL_HCD_HC_GetXferCount (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the last host transfer size.
HCD_HCStateTypeDef | HAL_HCD_HC_GetState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the Host Channel state.
uint32_t | HAL_HCD_GetCurrentFrame (HCD_HandleTypeDef *hhcd)
Return the current Host frame number.
uint32_t | HAL_HCD_GetCurrentSpeed (HCD_HandleTypeDef *hhcd)
Return the Host enumeration speed.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_HCD_GetCurrentFrame ( HCD_HandleTypeDef * hhcd )

Return the current Host frame number.

Parameters:
hhcd,: HCD handle
Return values:
Current Host frame number

Definition at line 748 of file stm32h7xx_hal_hcd.c.

References HCD_HandleTypeDef::Instance.

uint32_t HAL_HCD_GetCurrentSpeed ( HCD_HandleTypeDef * hhcd )

Return the Host enumeration speed.

Parameters:
hhcd,: HCD handle
Return values:
Enumeration speed

Definition at line 758 of file stm32h7xx_hal_hcd.c.

References HCD_HandleTypeDef::Instance.

HCD_StateTypeDef HAL_HCD_GetState ( HCD_HandleTypeDef * hhcd )

Return the HCD state.

Parameters:
hhcd,: HCD handle
Return values:
HAL state

Definition at line 684 of file stm32h7xx_hal_hcd.c.

References HCD_HandleTypeDef::State.

HCD_HCStateTypeDef HAL_HCD_HC_GetState | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  |

Return the Host Channel state.

Parameters:
hhcd,: HCD handle
chnum,: Channel number. This parameter can be a value from 1 to 15
Return values:
Host channel state This parameter can be one of the these values: HC_IDLE/ HC_XFRC/ HC_HALTED/ HC_NYET/ HC_NAK/ HC_STALL/ HC_XACTERR/ HC_BBLERR/ HC_DATATGLERR/

Definition at line 738 of file stm32h7xx_hal_hcd.c.

References HCD_HandleTypeDef::hc.

HCD_URBStateTypeDef HAL_HCD_HC_GetURBState | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  |

Return URB state for a channel.

Parameters:
hhcd,: HCD handle
chnum,: Channel number. This parameter can be a value from 1 to 15
Return values:
URB state. This parameter can be one of these values: URB_IDLE/ URB_DONE/ URB_NOTREADY/ URB_NYET/ URB_ERROR/ URB_STALL/

Definition at line 703 of file stm32h7xx_hal_hcd.c.

References HCD_HandleTypeDef::hc.

uint32_t HAL_HCD_HC_GetXferCount | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  |

Return the last host transfer size.

Parameters:
hhcd,: HCD handle
chnum,: Channel number. This parameter can be a value from 1 to 15
Return values:
last transfer size in byte

Definition at line 716 of file stm32h7xx_hal_hcd.c.

References HCD_HandleTypeDef::hc.

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HCD Instance definition

Defines
HCD Instance definition
HCD Private Macros

Defines

#define IS_HCD_ALL_INSTANCE(INSTANCE)

Define Documentation

#define IS_HCD_ALL_INSTANCE ( INSTANCE )
Value:
(((INSTANCE) == USB2_OTG_FS) || \
                                       ((INSTANCE) == USB1_OTG_HS))

Definition at line 235 of file stm32h7xx_hal_hcd.h.

Referenced by HAL_HCD_Init().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HCD Private Functions Prototypes

HCD Private Functions Prototypes
HCD
Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HCD Private Functions

Functions
HCD Private Functions
HCD

Functions

static void | HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
This function handles Host Channel IN interrupt requests.
static void | HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
This function handles Host Channel OUT interrupt requests.
static void | HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
This function handles Rx Queue Level interrupt requests.
static void | HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
This function handles Host Port interrupt requests.

Function Documentation

static void HCD_HC_IN_IRQHandler | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  | [static]

This function handles Host Channel IN interrupt requests.

Parameters:
hhcd,: HCD handle
chnum,: Channel number. This parameter can be a value from 1 to 15
Return values:
none

Definition at line 780 of file stm32h7xx_hal_hcd.c.

References __HAL_HCD_CLEAR_HC_INT, __HAL_HCD_MASK_HALT_HC_INT, __HAL_HCD_UNMASK_HALT_HC_INT, HAL_HCD_HC_NotifyURBChange_Callback(), HCD_HandleTypeDef::hc, HCD_HandleTypeDef::Init, and HCD_HandleTypeDef::Instance.

Referenced by HAL_HCD_IRQHandler().

static void HCD_HC_OUT_IRQHandler | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  | [static]

This function handles Host Channel OUT interrupt requests.

Parameters:
hhcd,: HCD handle
chnum,: Channel number. This parameter can be a value from 1 to 15
Return values:
none

Definition at line 920 of file stm32h7xx_hal_hcd.c.

References __HAL_HCD_CLEAR_HC_INT, __HAL_HCD_MASK_HALT_HC_INT, __HAL_HCD_UNMASK_HALT_HC_INT, HAL_HCD_HC_NotifyURBChange_Callback(), HCD_HandleTypeDef::hc, and HCD_HandleTypeDef::Instance.

Referenced by HAL_HCD_IRQHandler().

static void HCD_Port_IRQHandler ( HCD_HandleTypeDef * hhcd ) [static]

This function handles Host Port interrupt requests.

Parameters:
hhcd,: HCD handle
Return values:
None

Definition at line 1110 of file stm32h7xx_hal_hcd.c.

References HAL_HCD_Connect_Callback(), HCD_SPEED_FULL, HCD_SPEED_HIGH, HCD_HandleTypeDef::Init, and HCD_HandleTypeDef::Instance.

Referenced by HAL_HCD_IRQHandler().

static void HCD_RXQLVL_IRQHandler ( HCD_HandleTypeDef * hhcd ) [static]

This function handles Rx Queue Level interrupt requests.

Parameters:
hhcd,: HCD handle
Return values:
none

Definition at line 1060 of file stm32h7xx_hal_hcd.c.

References HCD_HandleTypeDef::hc, and HCD_HandleTypeDef::Instance.

Referenced by HAL_HCD_IRQHandler().

Generated on Fri Apr 28 2017 15:42:47 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2S Exported Types

Data Structures | Typedefs | Enumerations
I2S Exported Types
I2S

Data Structures

struct | I2S_InitTypeDef
I2S Init structure definition. More...
struct | __I2S_HandleTypeDef
I2S handle Structure definition. More...

Typedefs

typedef struct __I2S_HandleTypeDef | I2S_HandleTypeDef
I2S handle Structure definition.

Enumerations

enum HAL_I2S_StateTypeDef {
HAL_I2S_STATE_RESET = 0x00U, HAL_I2S_STATE_READY = 0x01U, HAL_I2S_STATE_BUSY = 0x02U, HAL_I2S_STATE_BUSY_TX = 0x03U,
HAL_I2S_STATE_BUSY_RX = 0x04U, HAL_I2S_STATE_BUSY_TX_RX = 0x05U, HAL_I2S_STATE_TIMEOUT = 0x06U, HAL_I2S_STATE_ERROR = 0x07U
}
HAL State structures definition. More...

Typedef Documentation

typedef struct __I2S_HandleTypeDef I2S_HandleTypeDef

I2S handle Structure definition.

Enumeration Type Documentation

enum HAL_I2S_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_I2S_STATE_RESET

I2S not yet initialized or disabled

HAL_I2S_STATE_READY

I2S initialized and ready for use

HAL_I2S_STATE_BUSY

I2S internal process is ongoing

HAL_I2S_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_I2S_STATE_BUSY_RX

Data Reception process is ongoing

HAL_I2S_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing

HAL_I2S_STATE_TIMEOUT

I2S timeout state

HAL_I2S_STATE_ERROR

I2S error state

Definition at line 112 of file stm32h7xx_hal_i2s.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2S_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2S_InitTypeDef Struct Reference
I2S Exported Types

I2S Init structure definition. More...

#include <stm32h7xx_hal_i2s.h>

Data Fields

uint32_t | Mode
uint32_t | Standard
uint32_t | DataFormat
uint32_t | MCLKOutput
uint32_t | AudioFreq
uint32_t | CPOL
uint32_t | FirstBit
uint32_t | WSInversion
uint32_t | IOSwap
uint32_t | Data24BitAlignment
uint32_t | FifoThreshold
uint32_t | MasterKeepIOState
uint32_t | SlaveExtendFREDetection

Detailed Description

I2S Init structure definition.

Definition at line 65 of file stm32h7xx_hal_i2s.h.

Field Documentation

uint32_t I2S_InitTypeDef::AudioFreq

Specifies the frequency selected for the I2S communication. This parameter can be a value of I2S Audio Frequency

Definition at line 79 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::CPOL

Specifies the idle state of the I2S clock. This parameter can be a value of I2S Clock Polarity

Definition at line 82 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::Data24BitAlignment

Specifies the Data Padding for 24 bits data lenght This parameter can be a value of Data Padding 24Bit

Definition at line 94 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::DataFormat

Specifies the data format for the I2S communication. This parameter can be a value of I2S Data Format

Definition at line 73 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit_IT(), and HAL_I2SEx_TransmitReceive_IT().

uint32_t I2S_InitTypeDef::FifoThreshold

Specifies the FIFO threshold level. This parameter can be a value of I2S Fifo Threshold

Definition at line 97 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_Transmit(), and HAL_I2SEx_TransmitReceive().

uint32_t I2S_InitTypeDef::FirstBit

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of I2S MSB LSB Transmission

Definition at line 85 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::IOSwap

Invert MISO/MOSI alternate functions This parameter can be a value of Control I2S IO Swap

Definition at line 91 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::MasterKeepIOState

Control of Alternate function GPIOs state This parameter can be a value of Keep IO State

Definition at line 100 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::MCLKOutput

Specifies whether the I2S MCLK output is enabled or not. This parameter can be a value of I2S MCLK Output

Definition at line 76 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::Mode

Specifies the I2S operating mode. This parameter can be a value of I2S Mode

Definition at line 67 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), HAL_I2SEx_TransmitReceive(), HAL_I2SEx_TransmitReceive_DMA(), HAL_I2SEx_TransmitReceive_IT(), I2S_CloseRx_ISR(), and I2S_CloseTx_ISR().

uint32_t I2S_InitTypeDef::SlaveExtendFREDetection

Control the channel length in SLAVE. This parameter can be a value of Slave Extend FRE Detection

Definition at line 103 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::Standard

Specifies the standard used for the I2S communication. This parameter can be a value of I2S Standard

Definition at line 70 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::WSInversion

Control the Word Select Inversion. This parameter can be a value of I2S Word Select Inversion

Definition at line 88 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_i2s.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: __I2S_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__I2S_HandleTypeDef Struct Reference
I2S Exported Types

I2S handle Structure definition. More...

#include <stm32h7xx_hal_i2s.h>

Data Fields

SPI_TypeDef * | Instance
I2S_InitTypeDef Init
uint16_t * | pTxBuffPtr
__IO uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint16_t * | pRxBuffPtr
__IO uint16_t | RxXferSize
__IO uint16_t | RxXferCount
void(* | RxISR )(struct __I2S_HandleTypeDef *hi2s)
void(* | TxISR )(struct __I2S_HandleTypeDef *hi2s)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
__IO HAL_LockTypeDef | Lock
__IO HAL_I2S_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

I2S handle Structure definition.

Definition at line 127 of file stm32h7xx_hal_i2s.h.

Field Documentation

__IO uint32_t __I2S_HandleTypeDef::ErrorCode

I2S Error code

Definition at line 157 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_GetError(), HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), HAL_I2SEx_TransmitReceive(), HAL_I2SEx_TransmitReceive_DMA(), HAL_I2SEx_TransmitReceive_IT(), I2S_CloseRx_ISR(), I2S_CloseTx_ISR(), I2S_DMAError(), I2SEx_CloseRxTx_ISR(), I2SEx_DMATxRxCplt(), and I2SEx_TxRxDMAError().

DMA_HandleTypeDef* __I2S_HandleTypeDef::hdmarx

I2S Rx DMA handle parameters

Definition at line 151 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), HAL_I2S_Receive_DMA(), and HAL_I2SEx_TransmitReceive_DMA().

DMA_HandleTypeDef* __I2S_HandleTypeDef::hdmatx

I2S Tx DMA handle parameters

Definition at line 149 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), HAL_I2S_Transmit_DMA(), and HAL_I2SEx_TransmitReceive_DMA().

I2S_InitTypeDef __I2S_HandleTypeDef::Init

I2S communication parameters

Definition at line 131 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), HAL_I2SEx_TransmitReceive(), HAL_I2SEx_TransmitReceive_DMA(), HAL_I2SEx_TransmitReceive_IT(), I2S_CloseRx_ISR(), and I2S_CloseTx_ISR().

SPI_TypeDef* __I2S_HandleTypeDef::Instance

I2S registers base address

Definition at line 129 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_DMAPause(), HAL_I2S_DMAResume(), HAL_I2S_DMAStop(), HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), HAL_I2SEx_TransmitReceive(), HAL_I2SEx_TransmitReceive_DMA(), HAL_I2SEx_TransmitReceive_IT(), I2S_CloseRx_ISR(), I2S_DMAError(), I2S_DMARxCplt(), I2S_DMATxCplt(), I2S_RxISR_16BIT(), I2S_RxISR_32BIT(), I2S_TxISR_16BIT(), I2S_TxISR_32BIT(), I2SEx_2linesRxISR_16BIT(), I2SEx_2linesRxISR_32BIT(), I2SEx_2linesTxISR_16BIT(), I2SEx_2linesTxISR_32BIT(), I2SEx_DMATxRxCplt(), and I2SEx_TxRxDMAError().

__IO HAL_LockTypeDef __I2S_HandleTypeDef::Lock

I2S locking object

Definition at line 153 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint16_t* __I2S_HandleTypeDef::pRxBuffPtr

Pointer to I2S Rx transfer buffer

Definition at line 139 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit_IT(), HAL_I2SEx_TransmitReceive(), HAL_I2SEx_TransmitReceive_DMA(), HAL_I2SEx_TransmitReceive_IT(), I2S_RxISR_16BIT(), I2S_RxISR_32BIT(), I2SEx_2linesRxISR_16BIT(), and I2SEx_2linesRxISR_32BIT().

uint16_t* __I2S_HandleTypeDef::pTxBuffPtr

Pointer to I2S Tx transfer buffer

Definition at line 133 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), HAL_I2SEx_TransmitReceive(), HAL_I2SEx_TransmitReceive_DMA(), HAL_I2SEx_TransmitReceive_IT(), I2S_TxISR_16BIT(), I2S_TxISR_32BIT(), I2SEx_2linesTxISR_16BIT(), and I2SEx_2linesTxISR_32BIT().

void(* __I2S_HandleTypeDef::RxISR)(struct __I2S_HandleTypeDef *hi2s)

function pointer on Rx ISR

Definition at line 145 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit_IT(), and HAL_I2SEx_TransmitReceive_IT().

__IO uint16_t __I2S_HandleTypeDef::RxXferCount

I2S Rx transfer counter

Definition at line 143 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit_IT(), HAL_I2SEx_TransmitReceive(), HAL_I2SEx_TransmitReceive_DMA(), HAL_I2SEx_TransmitReceive_IT(), I2S_DMAError(), I2S_DMARxCplt(), I2S_DMATxCplt(), I2S_RxISR_16BIT(), I2S_RxISR_32BIT(), I2SEx_2linesRxISR_16BIT(), I2SEx_2linesRxISR_32BIT(), I2SEx_2linesTxISR_16BIT(), I2SEx_2linesTxISR_32BIT(), I2SEx_DMATxRxCplt(), and I2SEx_TxRxDMAError().

__IO uint16_t __I2S_HandleTypeDef::RxXferSize

I2S Rx transfer size

Definition at line 141 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit_IT(), HAL_I2SEx_TransmitReceive(), HAL_I2SEx_TransmitReceive_DMA(), and HAL_I2SEx_TransmitReceive_IT().

__IO HAL_I2S_StateTypeDef __I2S_HandleTypeDef::State

I2S communication state

Definition at line 155 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_DMAStop(), HAL_I2S_GetState(), HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), HAL_I2SEx_TransmitReceive(), HAL_I2SEx_TransmitReceive_DMA(), HAL_I2SEx_TransmitReceive_IT(), I2S_CloseRx_ISR(), I2S_CloseTx_ISR(), I2S_DMAError(), I2S_DMARxCplt(), I2S_DMATxCplt(), I2S_WaitFlagStateUntilTimeout(), I2SEx_CloseRxTx_ISR(), I2SEx_DMATxRxCplt(), I2SEx_TxRxDMAError(), and I2SEx_WaitFlagStateUntilTimeout().

void(* __I2S_HandleTypeDef::TxISR)(struct __I2S_HandleTypeDef *hi2s)

function pointer on Tx ISR

Definition at line 147 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit_IT(), and HAL_I2SEx_TransmitReceive_IT().

__IO uint16_t __I2S_HandleTypeDef::TxXferCount

I2S Tx transfer Counter

Definition at line 137 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), HAL_I2SEx_TransmitReceive(), HAL_I2SEx_TransmitReceive_DMA(), HAL_I2SEx_TransmitReceive_IT(), I2S_DMAError(), I2S_DMARxCplt(), I2S_DMATxCplt(), I2S_TxISR_16BIT(), I2S_TxISR_32BIT(), I2SEx_2linesRxISR_16BIT(), I2SEx_2linesRxISR_32BIT(), I2SEx_2linesTxISR_16BIT(), I2SEx_2linesTxISR_32BIT(), I2SEx_DMATxRxCplt(), and I2SEx_TxRxDMAError().

__IO uint16_t __I2S_HandleTypeDef::TxXferSize

I2S Tx transfer size

Definition at line 135 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), HAL_I2SEx_TransmitReceive(), HAL_I2SEx_TransmitReceive_DMA(), and HAL_I2SEx_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_i2s.h
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STM32H753xx HAL User Manual: I2S Error Defintion

Defines
I2S Error Defintion
I2S Exported Constants

I2S Error Code. More...

Defines

#define | HAL_I2S_ERROR_NONE (0x00000000U)
#define | HAL_I2S_ERROR_UDR (0x00000001U)
#define | HAL_I2S_ERROR_OVR (0x00000002U)
#define | HAL_I2S_ERROR_FRE (0x00000004U)
#define | HAL_I2S_ERROR_DMA (0x00000008U)
#define | HAL_I2S_ERROR_DMA (0x00000008U)
#define | HAL_I2S_ERROR_TIMEOUT (0x00000010U)
#define | HAL_I2S_ERROR_PRESCALER (0x00000020U)

Detailed Description

I2S Error Code.

Define Documentation

#define HAL_I2S_ERROR_DMA (0x00000008U)

DMA transfer error

Definition at line 179 of file stm32h7xx_hal_i2s.h.

Referenced by I2S_DMAError(), and I2SEx_TxRxDMAError().

#define HAL_I2S_ERROR_DMA (0x00000008U)

DMA transfer error

Definition at line 179 of file stm32h7xx_hal_i2s.h.

#define HAL_I2S_ERROR_FRE (0x00000004U)

I2S Frame format error

Definition at line 177 of file stm32h7xx_hal_i2s.h.

#define HAL_I2S_ERROR_NONE (0x00000000U)

No error

Definition at line 174 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_Init(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), HAL_I2SEx_TransmitReceive(), HAL_I2SEx_TransmitReceive_DMA(), HAL_I2SEx_TransmitReceive_IT(), I2S_CloseRx_ISR(), I2SEx_CloseRxTx_ISR(), and I2SEx_DMATxRxCplt().

#define HAL_I2S_ERROR_OVR (0x00000002U)

I2S Overrun error

Definition at line 176 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler().

#define HAL_I2S_ERROR_PRESCALER (0x00000020U)

Prescaler error

Definition at line 181 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define HAL_I2S_ERROR_TIMEOUT (0x00000010U)

Timeout error

Definition at line 180 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Transmit(), and HAL_I2SEx_TransmitReceive().

#define HAL_I2S_ERROR_UDR (0x00000001U)

I2S Underrun error

Definition at line 175 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler().

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STM32H753xx HAL User Manual: I2S Mode

Defines
I2S Mode
I2S Exported Constants

Defines

#define | I2S_MODE_SLAVE_TX (0x00000000U)
#define | I2S_MODE_SLAVE_RX (0x00000002U)
#define | I2S_MODE_MASTER_TX (0x00000004U)
#define | I2S_MODE_MASTER_RX (0x00000006U)
#define | I2S_MODE_SLAVE_FD (0x00000008U)
#define | I2S_MODE_MASTER_FD (0x0000000AU)

Define Documentation

#define I2S_MODE_MASTER_FD (0x0000000AU)

Definition at line 194 of file stm32h7xx_hal_i2s.h.

#define I2S_MODE_MASTER_RX (0x00000006U)

Definition at line 192 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), and HAL_I2S_Receive_DMA().

#define I2S_MODE_MASTER_TX (0x00000004U)

Definition at line 191 of file stm32h7xx_hal_i2s.h.

#define I2S_MODE_SLAVE_FD (0x00000008U)

Definition at line 193 of file stm32h7xx_hal_i2s.h.

#define I2S_MODE_SLAVE_RX (0x00000002U)

Definition at line 190 of file stm32h7xx_hal_i2s.h.

#define I2S_MODE_SLAVE_TX (0x00000000U)

Definition at line 189 of file stm32h7xx_hal_i2s.h.

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STM32H753xx HAL User Manual: I2S Standard

Defines
I2S Standard
I2S Exported Constants

Defines

#define | I2S_STANDARD_PHILIPS (0x00000000U)
#define | I2S_STANDARD_MSB (0x00000010U)
#define | I2S_STANDARD_LSB (0x00000020U)
#define | I2S_STANDARD_PCM_SHORT (0x00000030U)
#define | I2S_STANDARD_PCM_LONG (0x000000B0U)

Define Documentation

#define I2S_STANDARD_LSB (0x00000020U)

Definition at line 204 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define I2S_STANDARD_MSB (0x00000010U)

Definition at line 203 of file stm32h7xx_hal_i2s.h.

#define I2S_STANDARD_PCM_LONG (0x000000B0U)

Definition at line 206 of file stm32h7xx_hal_i2s.h.

#define I2S_STANDARD_PCM_SHORT (0x00000030U)

Definition at line 205 of file stm32h7xx_hal_i2s.h.

#define I2S_STANDARD_PHILIPS (0x00000000U)

Definition at line 202 of file stm32h7xx_hal_i2s.h.

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STM32H753xx HAL User Manual: I2S Data Format

Defines
I2S Data Format
I2S Exported Constants

Defines

#define | I2S_DATAFORMAT_16B (0x00000000U)
#define | I2S_DATAFORMAT_16B_EXTENDED (0x00000400U)
#define | I2S_DATAFORMAT_24B (0x00000500U)
#define | I2S_DATAFORMAT_32B (0x00000600U)

Define Documentation

#define I2S_DATAFORMAT_16B (0x00000000U)

Definition at line 214 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit_IT(), and HAL_I2SEx_TransmitReceive_IT().

#define I2S_DATAFORMAT_16B_EXTENDED (0x00000400U)

Definition at line 215 of file stm32h7xx_hal_i2s.h.

#define I2S_DATAFORMAT_24B (0x00000500U)

Definition at line 216 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2SEx_TransmitReceive(), and HAL_I2SEx_TransmitReceive_DMA().

#define I2S_DATAFORMAT_32B (0x00000600U)

Definition at line 217 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2SEx_TransmitReceive(), and HAL_I2SEx_TransmitReceive_DMA().

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STM32H753xx HAL User Manual: I2S MCLK Output

Defines
I2S MCLK Output
I2S Exported Constants

Defines

#define | I2S_MCLKOUTPUT_ENABLE SPI_I2SCFGR_MCKOE
#define | I2S_MCLKOUTPUT_DISABLE (0x00000000U)

Define Documentation

#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)

Definition at line 226 of file stm32h7xx_hal_i2s.h.

#define I2S_MCLKOUTPUT_ENABLE SPI_I2SCFGR_MCKOE

Definition at line 225 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

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STM32H753xx HAL User Manual: I2S Audio Frequency

Defines
I2S Audio Frequency
I2S Exported Constants

Defines

#define | I2S_AUDIOFREQ_192K (192000U)
#define | I2S_AUDIOFREQ_96K (96000U)
#define | I2S_AUDIOFREQ_48K (48000U)
#define | I2S_AUDIOFREQ_44K (44100U)
#define | I2S_AUDIOFREQ_32K (32000U)
#define | I2S_AUDIOFREQ_22K (22050U)
#define | I2S_AUDIOFREQ_16K (16000U)
#define | I2S_AUDIOFREQ_11K (11025U)
#define | I2S_AUDIOFREQ_8K (8000U)
#define | I2S_AUDIOFREQ_DEFAULT (2U)

Define Documentation

#define I2S_AUDIOFREQ_11K (11025U)

Definition at line 241 of file stm32h7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_16K (16000U)

Definition at line 240 of file stm32h7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_192K (192000U)

Definition at line 234 of file stm32h7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_22K (22050U)

Definition at line 239 of file stm32h7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_32K (32000U)

Definition at line 238 of file stm32h7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_44K (44100U)

Definition at line 237 of file stm32h7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_48K (48000U)

Definition at line 236 of file stm32h7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_8K (8000U)

Definition at line 242 of file stm32h7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_96K (96000U)

Definition at line 235 of file stm32h7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_DEFAULT (2U)

Definition at line 243 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

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STM32H753xx HAL User Manual: I2S Clock Polarity

Defines
I2S Clock Polarity
I2S Exported Constants

Defines

#define | I2S_CPOL_LOW (0x00000000U)
#define | I2S_CPOL_HIGH SPI_I2SCFGR_CKPOL

Define Documentation

#define I2S_CPOL_HIGH SPI_I2SCFGR_CKPOL

Definition at line 252 of file stm32h7xx_hal_i2s.h.

#define I2S_CPOL_LOW (0x00000000U)

Definition at line 251 of file stm32h7xx_hal_i2s.h.

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STM32H753xx HAL User Manual: I2S MSB LSB Transmission

Defines
I2S MSB LSB Transmission
I2S Exported Constants

Defines

#define | I2S_FIRSTBIT_MSB (0x00000000U)
#define | I2S_FIRSTBIT_LSB SPI_CFG2_LSBFRST

Define Documentation

#define I2S_FIRSTBIT_LSB SPI_CFG2_LSBFRST

Definition at line 261 of file stm32h7xx_hal_i2s.h.

#define I2S_FIRSTBIT_MSB (0x00000000U)

Definition at line 260 of file stm32h7xx_hal_i2s.h.

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STM32H753xx HAL User Manual: I2S Word Select Inversion

Defines
I2S Word Select Inversion
I2S Exported Constants

Defines

#define | I2S_WS_INVERSION_DISABLE (0x00000000U)
#define | I2S_WS_INVERSION_ENABLE SPI_I2SCFGR_WSINV

Define Documentation

#define I2S_WS_INVERSION_DISABLE (0x00000000U)

Definition at line 269 of file stm32h7xx_hal_i2s.h.

#define I2S_WS_INVERSION_ENABLE SPI_I2SCFGR_WSINV

Definition at line 270 of file stm32h7xx_hal_i2s.h.

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STM32H753xx HAL User Manual: Control I2S IO Swap

Defines
Control I2S IO Swap
I2S Exported Constants

Defines

#define | I2S_IO_SWAP_DISABLE (0x00000000U)
#define | I2S_IO_SWAP_ENABLE SPI_CFG2_IOSWP

Define Documentation

#define I2S_IO_SWAP_DISABLE (0x00000000U)

Definition at line 278 of file stm32h7xx_hal_i2s.h.

#define I2S_IO_SWAP_ENABLE SPI_CFG2_IOSWP

Definition at line 279 of file stm32h7xx_hal_i2s.h.

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STM32H753xx HAL User Manual: Data Padding 24Bit

Defines
Data Padding 24Bit
I2S Exported Constants

Defines

#define | I2S_DATA_24BIT_ALIGNMENT_RIGHT (0x00000000U)
#define | I2S_DATA_24BIT_ALIGNMENT_LEFT SPI_I2SCFGR_DATFMT

Define Documentation

#define I2S_DATA_24BIT_ALIGNMENT_LEFT SPI_I2SCFGR_DATFMT

Definition at line 288 of file stm32h7xx_hal_i2s.h.

#define I2S_DATA_24BIT_ALIGNMENT_RIGHT (0x00000000U)

Definition at line 287 of file stm32h7xx_hal_i2s.h.

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STM32H753xx HAL User Manual: I2S Fifo Threshold

Defines
I2S Fifo Threshold
I2S Exported Constants

Defines

#define | I2S_FIFO_THRESHOLD_01DATA (0x00000000U)
#define | I2S_FIFO_THRESHOLD_02DATA (0x00000020U)
#define | I2S_FIFO_THRESHOLD_03DATA (0x00000040U)
#define | I2S_FIFO_THRESHOLD_04DATA (0x00000060U)
#define | I2S_FIFO_THRESHOLD_05DATA (0x00000080U)
#define | I2S_FIFO_THRESHOLD_06DATA (0x000000A0U)
#define | I2S_FIFO_THRESHOLD_07DATA (0x000000C0U)
#define | I2S_FIFO_THRESHOLD_08DATA (0x000000E0U)

Define Documentation

#define I2S_FIFO_THRESHOLD_01DATA (0x00000000U)

Definition at line 296 of file stm32h7xx_hal_i2s.h.

#define I2S_FIFO_THRESHOLD_02DATA (0x00000020U)

Definition at line 297 of file stm32h7xx_hal_i2s.h.

#define I2S_FIFO_THRESHOLD_03DATA (0x00000040U)

Definition at line 298 of file stm32h7xx_hal_i2s.h.

#define I2S_FIFO_THRESHOLD_04DATA (0x00000060U)

Definition at line 299 of file stm32h7xx_hal_i2s.h.

#define I2S_FIFO_THRESHOLD_05DATA (0x00000080U)

Definition at line 300 of file stm32h7xx_hal_i2s.h.

#define I2S_FIFO_THRESHOLD_06DATA (0x000000A0U)

Definition at line 301 of file stm32h7xx_hal_i2s.h.

#define I2S_FIFO_THRESHOLD_07DATA (0x000000C0U)

Definition at line 302 of file stm32h7xx_hal_i2s.h.

#define I2S_FIFO_THRESHOLD_08DATA (0x000000E0U)

Definition at line 303 of file stm32h7xx_hal_i2s.h.

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STM32H753xx HAL User Manual: Keep IO State

Defines
Keep IO State
I2S Exported Constants

Defines

#define | I2S_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)
#define | I2S_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR

Define Documentation

#define I2S_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)

Definition at line 311 of file stm32h7xx_hal_i2s.h.

#define I2S_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR

Definition at line 312 of file stm32h7xx_hal_i2s.h.

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STM32H753xx HAL User Manual: Slave Extend FRE Detection

Defines
Slave Extend FRE Detection
I2S Exported Constants

Defines

#define | I2S_SLAVE_EXTEND_FRE_DETECTION_DISABLE (0x00000000U)
#define | I2S_SLAVE_EXTEND_FRE_DETECTION_ENABLE SPI_I2SCFGR_FIXCH

Define Documentation

#define I2S_SLAVE_EXTEND_FRE_DETECTION_DISABLE (0x00000000U)

Definition at line 320 of file stm32h7xx_hal_i2s.h.

#define I2S_SLAVE_EXTEND_FRE_DETECTION_ENABLE SPI_I2SCFGR_FIXCH

Definition at line 321 of file stm32h7xx_hal_i2s.h.

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STM32H753xx HAL User Manual: I2S Interrupt definition

Defines
I2S Interrupt definition
I2S Exported Constants

Defines

#define | I2S_IT_TXE SPI_IER_TXPIE
#define | I2S_IT_RXNE SPI_IER_RXPIE
#define | I2S_IT_ERR (SPI_IER_OVRIE | SPI_IER_UDRIE | SPI_IER_TIFREIE)

Define Documentation

#define I2S_IT_ERR (SPI_IER_OVRIE | SPI_IER_UDRIE | SPI_IER_TIFREIE)

Definition at line 331 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit_IT(), HAL_I2SEx_TransmitReceive_IT(), I2S_CloseRx_ISR(), I2S_CloseTx_ISR(), and I2SEx_CloseRxTx_ISR().

#define I2S_IT_RXNE SPI_IER_RXPIE

Definition at line 330 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Receive_IT(), HAL_I2SEx_TransmitReceive_IT(), I2S_CloseRx_ISR(), I2SEx_2linesRxISR_16BIT(), I2SEx_2linesRxISR_32BIT(), and I2SEx_CloseRxTx_ISR().

#define I2S_IT_TXE SPI_IER_TXPIE

Definition at line 329 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Transmit_IT(), HAL_I2SEx_TransmitReceive_IT(), I2S_CloseTx_ISR(), I2SEx_2linesTxISR_16BIT(), I2SEx_2linesTxISR_32BIT(), and I2SEx_CloseRxTx_ISR().

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STM32H753xx HAL User Manual: I2S Flag definition

Defines
I2S Flag definition
I2S Exported Constants

Defines

#define | I2S_FLAG_TXE SPI_SR_TXP /* I2S status flag: Tx buffer empty flag */
#define | I2S_FLAG_RXNE SPI_SR_RXP /* I2S status flag: Rx buffer not empty flag */
#define | I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag: Underrun flag */
#define | I2S_FLAG_RXWNE SPI_SR_RXWNE /* I2S RxFIFO Word Not Empty */
#define | I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag: Overrun flag */
#define | I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag: TI mode frame format error flag */

Define Documentation

#define I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag: TI mode frame format error flag */

Definition at line 345 of file stm32h7xx_hal_i2s.h.

#define I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag: Overrun flag */

Definition at line 344 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler().

#define I2S_FLAG_RXNE SPI_SR_RXP /* I2S status flag: Rx buffer not empty flag */

Definition at line 341 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Receive(), and HAL_I2SEx_TransmitReceive().

#define I2S_FLAG_RXWNE SPI_SR_RXWNE /* I2S RxFIFO Word Not Empty */

Definition at line 343 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), and HAL_I2SEx_TransmitReceive().

#define I2S_FLAG_TXE SPI_SR_TXP /* I2S status flag: Tx buffer empty flag */

Definition at line 340 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Transmit(), and HAL_I2SEx_TransmitReceive().

#define I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag: Underrun flag */

Definition at line 342 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler().

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STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
I2S Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_I2S_Transmit (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Receive (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Transmit_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Receive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Transmit_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_Receive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Stops the audio stream playing from the Media.
void | HAL_I2S_IRQHandler (I2S_HandleTypeDef *hi2s)
This function handles I2S interrupt request.
__weak void | HAL_I2S_TxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer Half completed callbacks.
__weak void | HAL_I2S_TxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
__weak void | HAL_I2S_RxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer half completed callbacks.
__weak void | HAL_I2S_RxCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
__weak void | HAL_I2S_ErrorCallback (I2S_HandleTypeDef *hi2s)
I2S error callbacks.
static HAL_StatusTypeDef | I2S_WaitFlagStateUntilTimeout (I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
This function handles I2S Communication Timeout.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the I2S data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_I2S_Transmit()
        (++) HAL_I2S_Receive()

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_I2S_Transmit_IT()
        (++) HAL_I2S_Receive_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_I2S_Transmit_DMA()
        (++) HAL_I2S_Receive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_I2S_TxCpltCallback()
        (++) HAL_I2S_TxHalfCpltCallback()
        (++) HAL_I2S_RxCpltCallback()
        (++) HAL_I2S_RxHalfCpltCallback()
        (++) HAL_I2S_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_I2S_DMAPause ( I2S_HandleTypeDef * hi2s )

Pauses the audio stream playing from the Media.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 1193 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_DISABLE, __HAL_I2S_ENABLE, and __I2S_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_I2S_DMAResume ( I2S_HandleTypeDef * hi2s )

Resumes the audio stream playing from the Media.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 1228 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_DISABLE, __HAL_I2S_ENABLE, and __I2S_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_I2S_DMAStop ( I2S_HandleTypeDef * hi2s )

Stops the audio stream playing from the Media.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 1263 of file stm32h7xx_hal_i2s.c.

References __HAL_DMA_DISABLE, __HAL_I2S_DISABLE, __HAL_I2S_ENABLE, HAL_DMA_Abort(), HAL_I2S_STATE_READY, __I2S_HandleTypeDef::hdmarx, __I2S_HandleTypeDef::hdmatx, __I2S_HandleTypeDef::Instance, and __I2S_HandleTypeDef::State.

void HAL_I2S_ErrorCallback ( I2S_HandleTypeDef * hi2s )

I2S error callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1478 of file stm32h7xx_hal_i2s.c.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Transmit(), HAL_I2SEx_TransmitReceive(), I2S_CloseRx_ISR(), I2S_CloseTx_ISR(), I2S_DMAError(), I2SEx_CloseRxTx_ISR(), I2SEx_DMATxRxCplt(), and I2SEx_TxRxDMAError().

void HAL_I2S_IRQHandler ( I2S_HandleTypeDef * hi2s )

This function handles I2S interrupt request.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1320 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_DISABLE_IT, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_OVR, HAL_I2S_ERROR_UDR, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_READY, I2S_FLAG_OVR, I2S_FLAG_RXNE, I2S_FLAG_TXE, I2S_FLAG_UDR, I2S_IT_ERR, I2S_IT_RXNE, I2S_IT_TXE, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::RxISR, __I2S_HandleTypeDef::State, and __I2S_HandleTypeDef::TxISR.

HAL_StatusTypeDef HAL_I2S_Receive | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData,: a 16-bit pointer to data buffer.
Size,: number of frames to be sent.
Timeout,: Timeout duration
Note:
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate in continuous way and as the I2S is not disabled at the end of the I2S transaction.
This function can use an Audio Frequency up to 44KHz when I2S Clock Source is 32MHz
Return values:
HAL status

Definition at line 689 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_CLEAR_OVRFLAG, __HAL_I2S_ENABLE, __HAL_I2S_GET_FLAG, assert_param, __I2S_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2S_ERROR_NONE, HAL_I2S_ERROR_TIMEOUT, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_FLAG_RXNE, I2S_FLAG_RXWNE, I2S_MODE_MASTER_RX, __I2S_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, IS_I2S_MASTER, IS_I2S_RX_MODE, I2S_InitTypeDef::Mode, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::RxXferSize, and __I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_Receive_DMA | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData,: a 16-bit pointer to the Receive data buffer.
Size,: number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 1101 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_CLEAR_OVRFLAG, __HAL_I2S_DISABLE, __HAL_I2S_ENABLE, assert_param, __I2S_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, __I2S_HandleTypeDef::hdmarx, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_DMAError(), I2S_DMARxCplt(), I2S_DMARxHalfCplt(), I2S_MODE_MASTER_RX, __I2S_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, IS_I2S_RX_MODE, I2S_InitTypeDef::Mode, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::RxXferSize, __I2S_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_I2S_Receive_IT | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData,: a 16-bit pointer to the Receive data buffer.
Size,: number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
It is recommended to use DMA for the I2S receiver to avoid de-synchronisation between Master and Slave otherwise the I2S interrupt should be optimized.
This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
Return values:
HAL status

Definition at line 942 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __HAL_I2S_ENABLE_IT, assert_param, I2S_InitTypeDef::DataFormat, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_TX, I2S_DATAFORMAT_16B, I2S_IT_ERR, I2S_IT_RXNE, I2S_RxISR_16BIT(), I2S_RxISR_32BIT(), __I2S_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, IS_I2S_MASTER, IS_I2S_RX_MODE, I2S_InitTypeDef::Mode, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::RxISR, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::RxXferSize, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxISR, __I2S_HandleTypeDef::TxXferCount, and __I2S_HandleTypeDef::TxXferSize.

void HAL_I2S_RxCpltCallback ( I2S_HandleTypeDef * hi2s )

Rx Transfer completed callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1462 of file stm32h7xx_hal_i2s.c.

Referenced by I2S_CloseRx_ISR(), I2S_DMARxCplt(), and I2SEx_CloseRxTx_ISR().

void HAL_I2S_RxHalfCpltCallback ( I2S_HandleTypeDef * hi2s )

Rx Transfer half completed callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1446 of file stm32h7xx_hal_i2s.c.

Referenced by I2S_DMARxHalfCplt().

HAL_StatusTypeDef HAL_I2S_Transmit | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData,: a 16-bit pointer to data buffer.
Size,: number of frames to be sent.
Timeout,: Timeout duration
Note:
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
Return values:
HAL status

Definition at line 515 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __HAL_I2S_GET_FLAG, assert_param, __I2S_HandleTypeDef::ErrorCode, I2S_InitTypeDef::FifoThreshold, HAL_GetTick(), HAL_I2S_ERROR_NONE, HAL_I2S_ERROR_TIMEOUT, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_FLAG_TXE, I2S_WaitFlagStateUntilTimeout(), __I2S_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, IS_I2S_MASTER, IS_I2S_TX_MODE, I2S_InitTypeDef::Mode, __I2S_HandleTypeDef::pTxBuffPtr, SPI_FIFO_THRESHOLD_01DATA, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxXferCount, and __I2S_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_I2S_Transmit_DMA | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData,: a 16-bit pointer to the Transmit data buffer.
Size,: number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 1009 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_DISABLE, __HAL_I2S_ENABLE, assert_param, __I2S_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, __I2S_HandleTypeDef::hdmatx, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_DMAError(), I2S_DMATxCplt(), I2S_DMATxHalfCplt(), __I2S_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, IS_I2S_TX_MODE, I2S_InitTypeDef::Mode, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxXferCount, __I2S_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_I2S_Transmit_IT | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData,: a 16-bit pointer to data buffer.
Size,: number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
Return values:
HAL status

Definition at line 860 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __HAL_I2S_ENABLE_IT, assert_param, I2S_InitTypeDef::DataFormat, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_16B, I2S_IT_ERR, I2S_IT_TXE, I2S_TxISR_16BIT(), I2S_TxISR_32BIT(), __I2S_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, IS_I2S_MASTER, IS_I2S_TX_MODE, I2S_InitTypeDef::Mode, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::RxISR, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::RxXferSize, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxISR, __I2S_HandleTypeDef::TxXferCount, and __I2S_HandleTypeDef::TxXferSize.

void HAL_I2S_TxCpltCallback ( I2S_HandleTypeDef * hi2s )

Tx Transfer completed callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1430 of file stm32h7xx_hal_i2s.c.

Referenced by I2S_CloseTx_ISR(), and I2S_DMATxCplt().

void HAL_I2S_TxHalfCpltCallback ( I2S_HandleTypeDef * hi2s )

Tx Transfer Half completed callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1414 of file stm32h7xx_hal_i2s.c.

Referenced by I2S_DMATxHalfCplt().

static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint32_t | Flag,
 |  | uint32_t | State,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles I2S Communication Timeout.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Flag,: Flag checked
State,: Value of the flag expected
Timeout,: Duration of the timeout
Return values:
HAL status

Definition at line 1380 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_GET_FLAG, HAL_GetTick(), HAL_I2S_STATE_READY, and __I2S_HandleTypeDef::State.

Referenced by HAL_I2S_Transmit().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
I2S Exported Functions

Peripheral State functions. More...

Functions

HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_I2S_GetError ( I2S_HandleTypeDef * hi2s )

Return the I2S error code.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
I2S Error Code

Definition at line 1524 of file stm32h7xx_hal_i2s.c.

References __I2S_HandleTypeDef::ErrorCode.

HAL_I2S_StateTypeDef HAL_I2S_GetState ( I2S_HandleTypeDef * hi2s )

Return the I2S state.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL state

Definition at line 1513 of file stm32h7xx_hal_i2s.c.

References __I2S_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2S Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s)
DeInitializes the I2S peripheral.
__weak void | HAL_I2S_MspInit (I2S_HandleTypeDef *hi2s)
I2S MSP Init.
__weak void | HAL_I2S_MspDeInit (I2S_HandleTypeDef *hi2s)
I2S MSP DeInit.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialiaze the I2Sx peripheral in simplex mode:

      (+) User must Implement HAL_I2S_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_I2S_Init() to configure the selected device with
          the selected configuration:
        (++) Mode
        (++) Standard
        (++) Data Format
        (++) MCLK Output
        (++) Audio frequency
        (++) Polarity
        (++) First Bit
        (++) WS Inversion
        (++) IO Swap
        (++) Data 24Bit Alignment
        (++) Fifo Threshold
        (++) Alternate function GPIOs state
        (++) Channel length in SLAVE

     (+) Call the function HAL_I2S_DeInit() to restore the default configuration
         of the selected I2Sx periperal.

Function Documentation

HAL_StatusTypeDef HAL_I2S_DeInit ( I2S_HandleTypeDef * hi2s )

DeInitializes the I2S peripheral.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 395 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_DISABLE, assert_param, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_MspDeInit(), HAL_I2S_STATE_BUSY, HAL_I2S_STATE_RESET, __I2S_HandleTypeDef::Instance, and __I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_Init ( I2S_HandleTypeDef * hi2s )

Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 228 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_DISABLE, assert_param, I2S_InitTypeDef::AudioFreq, I2S_InitTypeDef::CPOL, I2S_InitTypeDef::Data24BitAlignment, I2S_InitTypeDef::DataFormat, __I2S_HandleTypeDef::ErrorCode, I2S_InitTypeDef::FifoThreshold, I2S_InitTypeDef::FirstBit, HAL_I2S_ERROR_NONE, HAL_I2S_ERROR_PRESCALER, HAL_I2S_MspInit(), HAL_I2S_STATE_BUSY, HAL_I2S_STATE_READY, HAL_I2S_STATE_RESET, HAL_RCCEx_GetPeriphCLKFreq(), I2S_AUDIOFREQ_DEFAULT, I2S_DATAFORMAT_16B, I2S_MCLKOUTPUT_ENABLE, I2S_STANDARD_LSB, __I2S_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, I2S_InitTypeDef::IOSwap, IS_I2S_AUDIO_FREQ, IS_I2S_CPOL, IS_I2S_DATA_24BIT_ALIGNMENT, IS_I2S_DATA_FORMAT, IS_I2S_FIFO_THRESHOLD, IS_I2S_FIRST_BIT, IS_I2S_IO_SWAP, IS_I2S_MASTER, IS_I2S_MASTER_KEEP_IO_STATE, IS_I2S_MCLK_OUTPUT, IS_I2S_MODE, IS_I2S_SLAVE_EXTEND_FRE_DETECTION, IS_I2S_STANDARD, IS_I2S_WS_INVERSION, __I2S_HandleTypeDef::Lock, I2S_InitTypeDef::MasterKeepIOState, I2S_InitTypeDef::MCLKOutput, I2S_InitTypeDef::Mode, RCC_PERIPHCLK_SPI1, I2S_InitTypeDef::SlaveExtendFREDetection, I2S_InitTypeDef::Standard, __I2S_HandleTypeDef::State, and I2S_InitTypeDef::WSInversion.

void HAL_I2S_MspDeInit ( I2S_HandleTypeDef * hi2s )

I2S MSP DeInit.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 445 of file stm32h7xx_hal_i2s.c.

Referenced by HAL_I2S_DeInit().

void HAL_I2S_MspInit ( I2S_HandleTypeDef * hi2s )

I2S MSP Init.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 429 of file stm32h7xx_hal_i2s.c.

Referenced by HAL_I2S_Init().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2S Private

Defines | Functions
I2S Private
I2S Exported Functions | I2S

Defines

#define | IS_I2S_MODE(MODE)
#define | IS_I2S_FD_MODE(MODE)
#define | IS_I2S_MASTER(MODE)
#define | IS_I2S_TX_MODE(MODE)
#define | IS_I2S_RX_MODE(MODE)
#define | IS_I2S_STANDARD(STANDARD)
#define | IS_I2S_DATA_FORMAT(FORMAT)
#define | IS_I2S_MCLK_OUTPUT(OUTPUT)
#define | IS_I2S_AUDIO_FREQ(FREQ)
#define | IS_I2S_CPOL(CPOL)
#define | IS_I2S_FIRST_BIT(FIRSTBIT)
#define | IS_I2S_WS_INVERSION(WSINV)
#define | IS_I2S_IO_SWAP(IOSWAP)
#define | IS_I2S_DATA_24BIT_ALIGNMENT(ALIGNMENT)
#define | IS_I2S_FIFO_THRESHOLD(FTHLV)
#define | IS_I2S_MASTER_KEEP_IO_STATE(AFCNTR)
#define | IS_I2S_SLAVE_EXTEND_FRE_DETECTION(FIXCH)

Functions

static void | I2S_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process complete callback.
static void | I2S_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process half complete callback.
static void | I2S_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process complete callback.
static void | I2S_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process half complete callback.
static void | I2S_DMAError (DMA_HandleTypeDef *hdma)
DMA I2S communication error callback.
static void | I2S_TxISR_16BIT (struct __I2S_HandleTypeDef *hi2s)
Handle the data 16-bit transmit in Interrupt mode.
static void | I2S_TxISR_32BIT (struct __I2S_HandleTypeDef *hi2s)
Handle the data 32-bit transmit in Interrupt mode.
static void | I2S_RxISR_16BIT (struct __I2S_HandleTypeDef *hi2s)
Manage the 16-bit receive in Interrupt context.
static void | I2S_RxISR_32BIT (struct __I2S_HandleTypeDef *hi2s)
Manage the 32-bit receive in Interrupt context.
static void | I2S_CloseRx_ISR (I2S_HandleTypeDef *hi2s)
Handle the end of the RX transaction.
static void | I2S_CloseTx_ISR (I2S_HandleTypeDef *hi2s)
Handle the end of the TX transaction.

Define Documentation

#define IS_I2S_AUDIO_FREQ ( FREQ )
Value:
((((FREQ) >= I2S_AUDIOFREQ_8K)    && \
                                    ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
                                    ((FREQ) == I2S_AUDIOFREQ_DEFAULT))

Definition at line 545 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_CPOL ( CPOL )
Value:
(((CPOL) == I2S_CPOL_LOW) || \
                                    ((CPOL) == I2S_CPOL_HIGH))

Definition at line 549 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_DATA_24BIT_ALIGNMENT ( ALIGNMENT )
Value:
(((ALIGNMENT) == I2S_DATA_24BIT_ALIGNMENT_RIGHT) || \
                                                 ((ALIGNMENT) == I2S_DATA_24BIT_ALIGNMENT_LEFT))

Definition at line 561 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_DATA_FORMAT ( FORMAT )
Value:
(((FORMAT) == I2S_DATAFORMAT_16B)          || \
                                    ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
                                    ((FORMAT) == I2S_DATAFORMAT_24B)          || \
                                    ((FORMAT) == I2S_DATAFORMAT_32B))

Definition at line 537 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_FD_MODE ( MODE )
Value:
(((MODE) == I2S_MODE_SLAVE_FD)  || \
                                   ((MODE) == I2S_MODE_MASTER_FD))

Definition at line 514 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2SEx_TransmitReceive(), HAL_I2SEx_TransmitReceive_DMA(), HAL_I2SEx_TransmitReceive_IT(), I2S_CloseRx_ISR(), and I2S_CloseTx_ISR().

#define IS_I2S_FIFO_THRESHOLD ( FTHLV )
Value:
(((FTHLV) == I2S_FIFO_THRESHOLD_01DATA) || \
                                      ((FTHLV) == I2S_FIFO_THRESHOLD_02DATA) || \
                                      ((FTHLV) == I2S_FIFO_THRESHOLD_03DATA) || \
                                      ((FTHLV) == I2S_FIFO_THRESHOLD_04DATA) || \
                                      ((FTHLV) == I2S_FIFO_THRESHOLD_05DATA) || \
                                      ((FTHLV) == I2S_FIFO_THRESHOLD_06DATA) || \
                                      ((FTHLV) == I2S_FIFO_THRESHOLD_07DATA) || \
                                      ((FTHLV) == I2S_FIFO_THRESHOLD_08DATA))

Definition at line 564 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_FIRST_BIT ( FIRSTBIT )
Value:
(((FIRSTBIT) == I2S_FIRSTBIT_MSB) || \
                                    ((FIRSTBIT) == I2S_FIRSTBIT_LSB))

Definition at line 552 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_IO_SWAP ( IOSWAP )
Value:
(((IOSWAP) == I2S_IO_SWAP_DISABLE) || \
                                    ((IOSWAP) == I2S_IO_SWAP_ENABLE))

Definition at line 558 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_MASTER ( MODE )
Value:
(((MODE) == I2S_MODE_MASTER_TX)  || \
                                   ((MODE) == I2S_MODE_MASTER_RX) || \
                                   ((MODE) == I2S_MODE_MASTER_FD))

Definition at line 517 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_Receive(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_IT(), HAL_I2SEx_TransmitReceive(), and HAL_I2SEx_TransmitReceive_IT().

#define IS_I2S_MASTER_KEEP_IO_STATE ( AFCNTR )
Value:
(((AFCNTR) == I2S_MASTER_KEEP_IO_STATE_DISABLE) || \
                                                  ((AFCNTR) == I2S_MASTER_KEEP_IO_STATE_ENABLE))

Definition at line 573 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_MCLK_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
                                    ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))

Definition at line 542 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_MODE ( MODE )
Value:
(((MODE) == I2S_MODE_SLAVE_TX)  || \
                                   ((MODE) == I2S_MODE_SLAVE_RX)  || \
                                   ((MODE) == I2S_MODE_MASTER_TX) || \
                                   ((MODE) == I2S_MODE_MASTER_RX) || \
                                   ((MODE) == I2S_MODE_SLAVE_FD)  || \
                                   ((MODE) == I2S_MODE_MASTER_FD))

Definition at line 507 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_RX_MODE ( MODE )
Value:
(((MODE) == I2S_MODE_SLAVE_RX)  || \
                                   ((MODE) == I2S_MODE_MASTER_RX) || \
                                   ((MODE) == I2S_MODE_SLAVE_FD)  || \
                                   ((MODE) == I2S_MODE_MASTER_FD))

Definition at line 526 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), and HAL_I2S_Receive_IT().

#define IS_I2S_SLAVE_EXTEND_FRE_DETECTION ( FIXCH )
Value:
(((FIXCH) == I2S_SLAVE_EXTEND_FRE_DETECTION_DISABLE) || \
                                                  ((FIXCH) == I2S_SLAVE_EXTEND_FRE_DETECTION_ENABLE))

Definition at line 576 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_STANDARD ( STANDARD )
Value:
(((STANDARD) == I2S_STANDARD_PHILIPS)   || \
                                   ((STANDARD) == I2S_STANDARD_MSB)       || \
                                   ((STANDARD) == I2S_STANDARD_LSB)       || \
                                   ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
                                   ((STANDARD) == I2S_STANDARD_PCM_LONG))

Definition at line 531 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_TX_MODE ( MODE )
Value:
(((MODE) == I2S_MODE_SLAVE_TX)  || \
                                   ((MODE) == I2S_MODE_MASTER_TX) || \
                                   ((MODE) == I2S_MODE_SLAVE_FD)  || \
                                   ((MODE) == I2S_MODE_MASTER_FD))

Definition at line 521 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

#define IS_I2S_WS_INVERSION ( WSINV )
Value:
(((WSINV) == I2S_WS_INVERSION_DISABLE) || \
                                    ((WSINV) == I2S_WS_INVERSION_ENABLE))

Definition at line 555 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

Function Documentation

static void I2S_CloseRx_ISR ( I2S_HandleTypeDef * hi2s ) [static]

Handle the end of the RX transaction.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1777 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_CLEAR_UDRFLAG, __HAL_I2S_DISABLE_IT, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_ErrorCallback(), HAL_I2S_RxCpltCallback(), HAL_I2S_STATE_READY, I2S_IT_ERR, I2S_IT_RXNE, __I2S_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, IS_I2S_FD_MODE, I2S_InitTypeDef::Mode, and __I2S_HandleTypeDef::State.

Referenced by I2S_RxISR_16BIT(), and I2S_RxISR_32BIT().

static void I2S_CloseTx_ISR ( I2S_HandleTypeDef * hi2s ) [static]

Handle the end of the TX transaction.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1807 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_CLEAR_OVRFLAG, __HAL_I2S_DISABLE_IT, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_READY, HAL_I2S_TxCpltCallback(), HAL_SPI_ERROR_NONE, I2S_IT_ERR, I2S_IT_TXE, __I2S_HandleTypeDef::Init, IS_I2S_FD_MODE, I2S_InitTypeDef::Mode, and __I2S_HandleTypeDef::State.

Referenced by I2S_TxISR_16BIT(), and I2S_TxISR_32BIT().

static void I2S_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S communication error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1665 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_DISABLE, __HAL_I2S_ENABLE, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_DMA, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_READY, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::State, and __I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Receive_DMA(), and HAL_I2S_Transmit_DMA().

static void I2S_DMARxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1606 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_DISABLE, __HAL_I2S_ENABLE, HAL_I2S_RxCpltCallback(), HAL_I2S_STATE_BUSY_TX_RX, HAL_I2S_STATE_READY, __I2S_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::State, and __I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Receive_DMA().

static void I2S_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S receive process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1652 of file stm32h7xx_hal_i2s.c.

References HAL_I2S_RxHalfCpltCallback().

Referenced by HAL_I2S_Receive_DMA().

static void I2S_DMATxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S transmit process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1546 of file stm32h7xx_hal_i2s.c.

References __HAL_I2S_DISABLE, __HAL_I2S_ENABLE, HAL_I2S_STATE_BUSY_TX_RX, HAL_I2S_STATE_READY, HAL_I2S_TxCpltCallback(), __I2S_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::State, and __I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Transmit_DMA().

static void I2S_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S transmit process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1593 of file stm32h7xx_hal_i2s.c.

References HAL_I2S_TxHalfCpltCallback().

Referenced by HAL_I2S_Transmit_DMA().

static void I2S_RxISR_16BIT ( struct __I2S_HandleTypeDef * hi2s ) [static]

Manage the 16-bit receive in Interrupt context.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1703 of file stm32h7xx_hal_i2s.c.

References I2S_CloseRx_ISR(), __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pRxBuffPtr, and __I2S_HandleTypeDef::RxXferCount.

Referenced by HAL_I2S_Receive_IT().

static void I2S_RxISR_32BIT ( struct __I2S_HandleTypeDef * hi2s ) [static]

Manage the 32-bit receive in Interrupt context.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1721 of file stm32h7xx_hal_i2s.c.

References I2S_CloseRx_ISR(), __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pRxBuffPtr, and __I2S_HandleTypeDef::RxXferCount.

Referenced by HAL_I2S_Receive_IT().

static void I2S_TxISR_16BIT ( struct __I2S_HandleTypeDef * hi2s ) [static]

Handle the data 16-bit transmit in Interrupt mode.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1739 of file stm32h7xx_hal_i2s.c.

References I2S_CloseTx_ISR(), __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pTxBuffPtr, and __I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Transmit_IT().

static void I2S_TxISR_32BIT ( struct __I2S_HandleTypeDef * hi2s ) [static]

Handle the data 32-bit transmit in Interrupt mode.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1758 of file stm32h7xx_hal_i2s.c.

References I2S_CloseTx_ISR(), __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pTxBuffPtr, and __I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Transmit_IT().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: I2S Exported Macros

Modules | Defines
I2S Exported Macros
I2S

Modules

I2S Exported Functions

Defines

#define | __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
Reset I2S handle state.
#define | __HAL_I2S_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Enable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Disable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->IER,(__INTERRUPT__)))
Enable the specified I2S interrupts.
#define | __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->IER,(__INTERRUPT__)))
Disable the specified I2S interrupts.
#define | __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified I2S interrupt source is enabled or disabled.
#define | __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Checks whether the specified I2S flag is set or not.
#define | __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
Clears the I2S UDR pending flag.
#define | __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
Clears the I2S OVR pending flag.
#define | __HAL_I2S_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
Clear the I2S FRE pending flag.

Define Documentation

#define __HAL_I2S_CLEAR_FREFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)

Clear the I2S FRE pending flag.

Parameters:
__HANDLE__,: specifies the I2S Handle.
Return values:
None

Definition at line 439 of file stm32h7xx_hal_i2s.h.

#define __HAL_I2S_CLEAR_OVRFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)

Clears the I2S OVR pending flag.

Parameters:
__HANDLE__,: specifies the I2S Handle.
Return values:
None

Definition at line 433 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), and I2S_CloseTx_ISR().

#define __HAL_I2S_CLEAR_UDRFLAG ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)

Clears the I2S UDR pending flag.

Parameters:
__HANDLE__,: specifies the I2S Handle.
Return values:
None

Definition at line 427 of file stm32h7xx_hal_i2s.h.

Referenced by I2S_CloseRx_ISR().

#define __HAL_I2S_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)

Disable the specified SPI peripheral (in I2S mode).

Parameters:
__HANDLE__,: specifies the I2S Handle.
Return values:
None

Definition at line 374 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_DMAPause(), HAL_I2S_DMAResume(), HAL_I2S_DMAStop(), HAL_I2S_Init(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_I2SEx_TransmitReceive_DMA(), I2S_DMAError(), I2S_DMARxCplt(), I2S_DMATxCplt(), I2SEx_DMATxRxCplt(), and I2SEx_TxRxDMAError().

#define __HAL_I2S_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (CLEAR_BIT((__HANDLE__)->Instance->IER,(__INTERRUPT__)))

Disable the specified I2S interrupts.

Parameters:
__HANDLE__,: specifies the I2S Handle.
__INTERRUPT__,: specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • I2S_IT_TXE: Tx buffer empty interrupt enable
  • I2S_IT_RXNE: RX buffer not empty interrupt enable
  • I2S_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 396 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), I2S_CloseRx_ISR(), I2S_CloseTx_ISR(), I2SEx_2linesRxISR_16BIT(), I2SEx_2linesRxISR_32BIT(), I2SEx_2linesTxISR_16BIT(), I2SEx_2linesTxISR_32BIT(), and I2SEx_CloseRxTx_ISR().

#define __HAL_I2S_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)

Enable the specified SPI peripheral (in I2S mode).

Parameters:
__HANDLE__,: specifies the I2S Handle.
Return values:
None

Definition at line 368 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_DMAPause(), HAL_I2S_DMAResume(), HAL_I2S_DMAStop(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), HAL_I2SEx_TransmitReceive(), HAL_I2SEx_TransmitReceive_DMA(), HAL_I2SEx_TransmitReceive_IT(), I2S_DMAError(), I2S_DMARxCplt(), I2S_DMATxCplt(), I2SEx_DMATxRxCplt(), and I2SEx_TxRxDMAError().

#define __HAL_I2S_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (SET_BIT((__HANDLE__)->Instance->IER,(__INTERRUPT__)))

Enable the specified I2S interrupts.

Parameters:
__HANDLE__,: specifies the I2S Handle.
__INTERRUPT__,: specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • I2S_IT_TXE: Tx buffer empty interrupt enable
  • I2S_IT_RXNE: RX buffer not empty interrupt enable
  • I2S_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 385 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive_IT(), HAL_I2S_Transmit_IT(), and HAL_I2SEx_TransmitReceive_IT().

#define __HAL_I2S_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Checks whether the specified I2S flag is set or not.

Parameters:
__HANDLE__,: specifies the I2S Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • I2S_FLAG_TXE : Tx buffer empty flag
  • I2S_FLAG_RXNE : Rx buffer not empty flag
  • I2S_FLAG_UDR : Underrun flag
  • I2S_FLAG_OVR : Overrun flag
  • I2S_FLAG_FRE : TI mode frame format error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 421 of file stm32h7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Transmit(), HAL_I2SEx_TransmitReceive(), I2S_WaitFlagStateUntilTimeout(), and I2SEx_WaitFlagStateUntilTimeout().

#define __HAL_I2S_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks if the specified I2S interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: specifies the I2S Handle. This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
__INTERRUPT__,: specifies the I2S interrupt source to check. This parameter can be one of the following values:
  • I2S_IT_TXE: Tx buffer empty interrupt enable
  • I2S_IT_RXNE: RX buffer not empty interrupt enable
  • I2S_IT_ERR: Error interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 408 of file stm32h7xx_hal_i2s.h.

#define __HAL_I2S_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)

Reset I2S handle state.

Parameters:
__HANDLE__,: specifies the I2S Handle.
Return values:
None

Definition at line 362 of file stm32h7xx_hal_i2s.h.

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IRDAEx Private Macros

Defines
IRDAEx Private Macros
IRDAEx

Defines

#define IRDA_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the IRDA clock source.

Define Documentation

#define IRDA_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the IRDA clock source.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
__CLOCKSOURCE__,: output variable.
Return values:
IRDA clocking source, written in __CLOCKSOURCE__.

Definition at line 73 of file stm32h7xx_hal_irda_ex.h.

Referenced by IRDA_SetConfig().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IWDG Private Defines

Defines
IWDG Private Defines
IWDG

Defines

#define HAL_IWDG_DEFAULT_TIMEOUT 48u

Define Documentation

#define HAL_IWDG_DEFAULT_TIMEOUT 48u

Definition at line 132 of file stm32h7xx_hal_iwdg.c.

Referenced by HAL_IWDG_Init().

Generated on Fri Apr 28 2017 15:42:48 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IWDG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IWDG_InitTypeDef Struct Reference
IWDG Exported Types

IWDG Init structure definition. More...

#include <stm32h7xx_hal_iwdg.h>

Data Fields

uint32_t | Prescaler
uint32_t | Reload
uint32_t | Window

Detailed Description

IWDG Init structure definition.

Definition at line 65 of file stm32h7xx_hal_iwdg.h.

Field Documentation

uint32_t IWDG_InitTypeDef::Prescaler

Select the prescaler of the IWDG. This parameter can be a value of IWDG Prescaler

Definition at line 67 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

uint32_t IWDG_InitTypeDef::Reload

Specifies the IWDG down-counter reload value. This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF

Definition at line 70 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

uint32_t IWDG_InitTypeDef::Window

Specifies the window value to be compared to the down-counter. This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF

Definition at line 73 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_iwdg.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IWDG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IWDG_HandleTypeDef Struct Reference
IWDG Exported Types

IWDG Handle Structure definition. More...

#include <stm32h7xx_hal_iwdg.h>

Data Fields

IWDG_TypeDef * Instance
IWDG_InitTypeDef Init

Detailed Description

IWDG Handle Structure definition.

Definition at line 81 of file stm32h7xx_hal_iwdg.h.

Field Documentation

IWDG_InitTypeDef IWDG_HandleTypeDef::Init

IWDG required parameters

Definition at line 85 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

IWDG_TypeDef* IWDG_HandleTypeDef::Instance

Register base address

Definition at line 83 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_iwdg.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: IWDG Prescaler

Defines
IWDG Prescaler
IWDG Exported Constants

Defines

#define | IWDG_PRESCALER_4 0x00000000u
#define | IWDG_PRESCALER_8 IWDG_PR_PR_0
#define | IWDG_PRESCALER_16 IWDG_PR_PR_1
#define | IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_64 IWDG_PR_PR_2
#define | IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Define Documentation

#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)

IWDG prescaler set to 128

Definition at line 106 of file stm32h7xx_hal_iwdg.h.

#define IWDG_PRESCALER_16 IWDG_PR_PR_1

IWDG prescaler set to 16

Definition at line 103 of file stm32h7xx_hal_iwdg.h.

#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

IWDG prescaler set to 256

Definition at line 107 of file stm32h7xx_hal_iwdg.h.

#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)

IWDG prescaler set to 32

Definition at line 104 of file stm32h7xx_hal_iwdg.h.

#define IWDG_PRESCALER_4 0x00000000u

IWDG prescaler set to 4

Definition at line 101 of file stm32h7xx_hal_iwdg.h.

#define IWDG_PRESCALER_64 IWDG_PR_PR_2

IWDG prescaler set to 64

Definition at line 105 of file stm32h7xx_hal_iwdg.h.

#define IWDG_PRESCALER_8 IWDG_PR_PR_0

IWDG prescaler set to 8

Definition at line 102 of file stm32h7xx_hal_iwdg.h.

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STM32H753xx HAL User Manual: IWDG Window option

Defines
IWDG Window option
IWDG Exported Constants

Defines

#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN

Define Documentation

#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN

Definition at line 115 of file stm32h7xx_hal_iwdg.h.

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STM32H753xx HAL User Manual: IWDG Exported Macros

Defines
IWDG Exported Macros
IWDG

Defines

#define | __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
Enable the IWDG peripheral.
#define | __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
Reload IWDG counter with value defined in the reload register (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).

Define Documentation

#define __HAL_IWDG_RELOAD_COUNTER ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)

Reload IWDG counter with value defined in the reload register (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).

Parameters:
__HANDLE__,: IWDG handle
Return values:
None

Definition at line 142 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init(), and HAL_IWDG_Refresh().

#define __HAL_IWDG_START ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)

Enable the IWDG peripheral.

Parameters:
__HANDLE__,: IWDG handle
Return values:
None

Definition at line 134 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

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STM32H753xx HAL User Manual: Initialization and Start functions

Functions
Initialization and Start functions
IWDG Exported Functions

Initialization and Start functions. More...

Functions

HAL_StatusTypeDef HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.

Detailed Description

Initialization and Start functions.

 ===============================================================================
          ##### Initialization and Start functions #####
 ===============================================================================
 [..]  This section provides functions allowing to:
      (+) Initialize the IWDG according to the specified parameters in the
          IWDG_InitTypeDef of associated handle.
      (+) Manage Window option.
      (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
          is reloaded in order to exit function with correct time base.

Function Documentation

HAL_StatusTypeDef HAL_IWDG_Init ( IWDG_HandleTypeDef * hiwdg )

Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.

Before exiting function, watchdog is refreshed in order to have correct time base.

Parameters:
hiwdg pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 172 of file stm32h7xx_hal_iwdg.c.

References __HAL_IWDG_RELOAD_COUNTER, __HAL_IWDG_START, assert_param, HAL_GetTick(), HAL_IWDG_DEFAULT_TIMEOUT, IWDG_HandleTypeDef::Init, IWDG_HandleTypeDef::Instance, IS_IWDG_PRESCALER, IS_IWDG_RELOAD, IS_IWDG_WINDOW, IWDG_ENABLE_WRITE_ACCESS, IWDG_InitTypeDef::Prescaler, IWDG_InitTypeDef::Reload, and IWDG_InitTypeDef::Window.

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STM32H753xx HAL User Manual: IO operation functions

Functions
IO operation functions
IWDG Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]  This section provides functions allowing to:
      (+) Refresh the IWDG.

Function Documentation

HAL_StatusTypeDef HAL_IWDG_Refresh ( IWDG_HandleTypeDef * hiwdg )

Refresh the IWDG.

Parameters:
hiwdg pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 256 of file stm32h7xx_hal_iwdg.c.

References __HAL_IWDG_RELOAD_COUNTER.

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STM32H753xx HAL User Manual: IWDG Private Constants

Defines
IWDG Private Constants
IWDG

Defines

#define | IWDG_KEY_RELOAD 0x0000AAAAu
IWDG Key Register BitMask.
#define | IWDG_KEY_ENABLE 0x0000CCCCu
#define | IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u
#define | IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u

Define Documentation

#define IWDG_KEY_ENABLE 0x0000CCCCu

IWDG Peripheral Enable

Definition at line 184 of file stm32h7xx_hal_iwdg.h.

#define IWDG_KEY_RELOAD 0x0000AAAAu

IWDG Key Register BitMask.

IWDG Reload Counter Enable

Definition at line 183 of file stm32h7xx_hal_iwdg.h.

#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u

IWDG KR Write Access Disable

Definition at line 186 of file stm32h7xx_hal_iwdg.h.

#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u

IWDG KR Write Access Enable

Definition at line 185 of file stm32h7xx_hal_iwdg.h.

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STM32H753xx HAL User Manual: IWDG Private Macros

Defines
IWDG Private Macros
IWDG

Defines

#define | IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IS_IWDG_PRESCALER(__PRESCALER__)
Check IWDG prescaler value.
#define | IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
Check IWDG reload value.
#define | IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
Check IWDG window value.

Define Documentation

#define IS_IWDG_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == IWDG_PRESCALER_4)  || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
                                               ((__PRESCALER__) == IWDG_PRESCALER_256))

Check IWDG prescaler value.

Parameters:
__PRESCALER__,: IWDG prescaler value
Return values:
None

Definition at line 216 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IS_IWDG_RELOAD ( __RELOAD__ ) ((__RELOAD__) <= IWDG_RLR_RL)

Check IWDG reload value.

Parameters:
__RELOAD__,: IWDG reload value
Return values:
None

Definition at line 229 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IS_IWDG_WINDOW ( __WINDOW__ ) ((__WINDOW__) <= IWDG_WINR_WIN)

Check IWDG window value.

Parameters:
__WINDOW__,: IWDG window value
Return values:
None

Definition at line 236 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IWDG_DISABLE_WRITE_ACCESS ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)

Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Parameters:
__HANDLE__,: IWDG handle
Return values:
None

Definition at line 209 of file stm32h7xx_hal_iwdg.h.

#define IWDG_ENABLE_WRITE_ACCESS ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)

Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Parameters:
__HANDLE__,: IWDG handle
Return values:
None

Definition at line 202 of file stm32h7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

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STM32H753xx HAL User Manual: OPAMPEx_Exported_Functions_Group1

Functions
OPAMPEx_Exported_Functions_Group1
OPAMPEx Exported Functions

Functions

HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll (OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
Run the self calibration of 2 OPAMPs in parallel.

Function Documentation

HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll | ( | OPAMP_HandleTypeDef * | hopamp1,
 |  | OPAMP_HandleTypeDef * | hopamp2
 | ) |  |

Run the self calibration of 2 OPAMPs in parallel.

Note:
Trimming values (PMOS & NMOS) are updated and user trimming is enabled is calibration is successful.
Calibration is performed in the mode specified in OPAMP init structure (mode normal or low power). To perform calibration for both modes, repeat this function twice after OPAMP init structure accordingly updated.
Parameters:
hopamp1 | handle
hopamp2 | handle
Return values:
HAL status

Definition at line 97 of file stm32h7xx_hal_opamp_ex.c.

References assert_param, HAL_Delay(), HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_READY, OPAMP_HandleTypeDef::Init, OPAMP_HandleTypeDef::Instance, IS_OPAMP_POWERMODE, OPAMP_INPUT_NONINVERTING, OPAMP_POWERMODE_HIGHSPEED, OPAMP_POWERMODE_NORMAL, OPAMP_STANDALONE_MODE, OPAMP_TRIMMING_DELAY, OPAMP_TRIMMING_USER, OPAMP_VREF_10VDDA, OPAMP_VREF_90VDDA, OPAMP_InitTypeDef::PowerMode, OPAMP_HandleTypeDef::State, OPAMP_InitTypeDef::TrimmingValueN, OPAMP_InitTypeDef::TrimmingValueNHighSpeed, OPAMP_InitTypeDef::TrimmingValueP, OPAMP_InitTypeDef::TrimmingValuePHighSpeed, and OPAMP_InitTypeDef::UserTrimming.

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STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
OPAMPEx Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef HAL_OPAMPEx_Unlock (OPAMP_HandleTypeDef *hopamp)
Unlock the selected OPAMP configuration.

Detailed Description

Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]
      (+) OPAMP unlock.

Function Documentation

HAL_StatusTypeDef HAL_OPAMPEx_Unlock ( OPAMP_HandleTypeDef * hopamp )

Unlock the selected OPAMP configuration.

Note:
This function must be called only when OPAMP is in state "locked".
Parameters:
hopamp,: OPAMP handle
Return values:
HAL status

Definition at line 408 of file stm32h7xx_hal_opamp_ex.c.

References assert_param, HAL_OPAMP_STATE_BUSY, HAL_OPAMP_STATE_CALIBBUSY, HAL_OPAMP_STATE_READY, HAL_OPAMP_STATE_RESET, OPAMP_HandleTypeDef::Instance, and OPAMP_HandleTypeDef::State.

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STM32H753xx HAL User Manual: RNG State Structure definition

Enumerations
RNG State Structure definition
RNG Init Structure definition

Enumerations

enum HAL_RNG_StateTypeDef {
HAL_RNG_STATE_RESET = 0x00U, HAL_RNG_STATE_READY = 0x01U, HAL_RNG_STATE_BUSY = 0x02U, HAL_RNG_STATE_TIMEOUT = 0x03U,
HAL_RNG_STATE_ERROR = 0x04U
}

Enumeration Type Documentation

enum HAL_RNG_StateTypeDef
Enumerator:
HAL_RNG_STATE_RESET

RNG not yet initialized or disabled

HAL_RNG_STATE_READY

RNG initialized and ready for use

HAL_RNG_STATE_BUSY

RNG internal process is ongoing

HAL_RNG_STATE_TIMEOUT

RNG timeout state

HAL_RNG_STATE_ERROR

RNG error state

Definition at line 76 of file stm32h7xx_hal_rng.h.

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STM32H753xx HAL User Manual: RNG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RNG_HandleTypeDef Struct Reference
RNG Handle Structure definition

#include <stm32h7xx_hal_rng.h>

Data Fields

RNG_TypeDef * | Instance
RNG_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_RNG_StateTypeDef | State
uint32_t | RandomNumber

Detailed Description

Definition at line 93 of file stm32h7xx_hal_rng.h.

Field Documentation

RNG_InitTypeDef RNG_HandleTypeDef::Init

RNG parameters

Definition at line 97 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_Init().

RNG_TypeDef* RNG_HandleTypeDef::Instance

Register base address

Definition at line 95 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_Init(), and HAL_RNG_IRQHandler().

HAL_LockTypeDef RNG_HandleTypeDef::Lock

RNG locking object

Definition at line 99 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_Init().

uint32_t RNG_HandleTypeDef::RandomNumber

Last Generated RNG Data

Definition at line 103 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber(), HAL_RNG_IRQHandler(), and HAL_RNG_ReadLastRandomNumber().

__IO HAL_RNG_StateTypeDef RNG_HandleTypeDef::State

RNG communication state

Definition at line 101 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_GenerateRandomNumber_IT(), HAL_RNG_GetState(), HAL_RNG_Init(), and HAL_RNG_IRQHandler().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rng.h
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STM32H753xx HAL User Manual: RNG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RNG_InitTypeDef Struct Reference
RNG Init Structure definition

#include <stm32h7xx_hal_rng.h>

Data Fields

uint32_t ClockErrorDetection

Detailed Description

Definition at line 67 of file stm32h7xx_hal_rng.h.

Field Documentation

uint32_t RNG_InitTypeDef::ClockErrorDetection

CED Clock error detection

Definition at line 69 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_Init().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_rng.h
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STM32H753xx HAL User Manual: RNG Interrupt definition

Defines
RNG Interrupt definition
RNG Exported Constants

Defines

#define | RNG_IT_DRDY RNG_SR_DRDY
#define | RNG_IT_CEI RNG_SR_CEIS
#define | RNG_IT_SEI RNG_SR_SEIS

Define Documentation

#define RNG_IT_CEI RNG_SR_CEIS

Clock error interrupt

Definition at line 125 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define RNG_IT_DRDY RNG_SR_DRDY

Data Ready interrupt

Definition at line 124 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define RNG_IT_SEI RNG_SR_SEIS

Seed error interrupt

Definition at line 126 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

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STM32H753xx HAL User Manual: RNG Flag definition

Defines
RNG Flag definition
RNG Exported Constants

Defines

#define | RNG_FLAG_DRDY RNG_SR_DRDY
#define | RNG_FLAG_CECS RNG_SR_CECS
#define | RNG_FLAG_SECS RNG_SR_SECS

Define Documentation

#define RNG_FLAG_CECS RNG_SR_CECS

Clock error current status

Definition at line 135 of file stm32h7xx_hal_rng.h.

#define RNG_FLAG_DRDY RNG_SR_DRDY

Data ready

Definition at line 134 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber().

#define RNG_FLAG_SECS RNG_SR_SECS

Seed error current status

Definition at line 136 of file stm32h7xx_hal_rng.h.

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STM32H753xx HAL User Manual: RNG Clock Error Detection

Defines
RNG Clock Error Detection
RNG Exported Constants

Defines

#define | RNG_CED_ENABLE ((uint32_t)0x00000000)
#define | RNG_CED_DISABLE RNG_CR_CED

Define Documentation

#define RNG_CED_DISABLE RNG_CR_CED

Clock error detection Disabled

Definition at line 146 of file stm32h7xx_hal_rng.h.

#define RNG_CED_ENABLE ((uint32_t)0x00000000)

Clock error detection Enabled

Definition at line 145 of file stm32h7xx_hal_rng.h.

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STM32H753xx HAL User Manual: RNG Exported Macros

Defines
RNG Exported Macros
RNG Exported Types

Defines

#define | __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
Reset RNG handle state.
#define | __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
Enables the RNG peripheral.
#define | __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
Disables the RNG peripheral.
#define | __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check the selected RNG flag status.
#define | __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
Clears the selected RNG flag status.
#define | __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
Enables the RNG interrupts.
#define | __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
Disables the RNG interrupts.
#define | __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks whether the specified RNG interrupt has occurred or not.
#define | __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
Clear the RNG interrupt status flags.

Define Documentation

#define __HAL_RNG_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | /* dummy macro */

Clears the selected RNG flag status.

Parameters:
__HANDLE__,: RNG handle
__FLAG__,: RNG flag to clear
Note:
WARNING: This is a dummy macro for HAL code alignment, flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
Return values:
None

Definition at line 202 of file stm32h7xx_hal_rng.h.

#define __HAL_RNG_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))

Clear the RNG interrupt status flags.

Parameters:
__HANDLE__,: RNG Handle
__INTERRUPT__,: specifies the RNG interrupt status flag to clear. This parameter can be one of the following values:
  • RNG_IT_CEI: Clock error interrupt
  • RNG_IT_SEI: Seed error interrupt
Note:
RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
Return values:
None

Definition at line 242 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)

Disables the RNG peripheral.

Parameters:
__HANDLE__,: RNG Handle
Return values:
None

Definition at line 180 of file stm32h7xx_hal_rng.h.

#define __HAL_RNG_DISABLE_IT ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)

Disables the RNG interrupts.

Parameters:
__HANDLE__,: RNG Handle
Return values:
None

Definition at line 218 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)

Enables the RNG peripheral.

Parameters:
__HANDLE__,: RNG Handle
Return values:
None

Definition at line 173 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_Init().

#define __HAL_RNG_ENABLE_IT ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)

Enables the RNG interrupts.

Parameters:
__HANDLE__,: RNG Handle
Return values:
None

Definition at line 211 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber_IT().

#define __HAL_RNG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Check the selected RNG flag status.

Parameters:
__HANDLE__,: RNG Handle
__FLAG__,: RNG flag This parameter can be one of the following values:
  • RNG_FLAG_DRDY: Data ready
  • RNG_FLAG_CECS: Clock error current status
  • RNG_FLAG_SECS: Seed error current status
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 192 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber().

#define __HAL_RNG_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))

Checks whether the specified RNG interrupt has occurred or not.

Parameters:
__HANDLE__,: RNG Handle
__INTERRUPT__,: specifies the RNG interrupt status flag to check. This parameter can be one of the following values:
  • RNG_IT_DRDY: Data ready interrupt
  • RNG_IT_CEI: Clock error interrupt
  • RNG_IT_SEI: Seed error interrupt
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 230 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)

Reset RNG handle state.

Parameters:
__HANDLE__,: RNG Handle
Return values:
None

Definition at line 166 of file stm32h7xx_hal_rng.h.

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STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RNG Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initializes the RNG peripheral and creates the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initializes the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG MSP.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
          ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the RNG according to the specified parameters
          in the RNG_InitTypeDef and create the associated handle
      (+) DeInitialize the RNG peripheral
      (+) Initialize the RNG MSP
      (+) DeInitialize RNG MSP

Function Documentation

HAL_StatusTypeDef HAL_RNG_DeInit ( RNG_HandleTypeDef * hrng )

DeInitializes the RNG peripheral.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

Definition at line 162 of file stm32h7xx_hal_rng.c.

References HAL_RNG_MspDeInit(), HAL_RNG_STATE_RESET, RNG_HandleTypeDef::Instance, and RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_Init ( RNG_HandleTypeDef * hrng )

Initializes the RNG peripheral and creates the associated handle.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

Definition at line 117 of file stm32h7xx_hal_rng.c.

References __HAL_RNG_ENABLE, assert_param, RNG_InitTypeDef::ClockErrorDetection, HAL_RNG_MspInit(), HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, HAL_RNG_STATE_RESET, RNG_HandleTypeDef::Init, RNG_HandleTypeDef::Instance, IS_RNG_CED, RNG_HandleTypeDef::Lock, and RNG_HandleTypeDef::State.

void HAL_RNG_MspDeInit ( RNG_HandleTypeDef * hrng )

DeInitializes the RNG MSP.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 209 of file stm32h7xx_hal_rng.c.

Referenced by HAL_RNG_DeInit().

void HAL_RNG_MspInit ( RNG_HandleTypeDef * hrng )

Initializes the RNG MSP.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 194 of file stm32h7xx_hal_rng.c.

Referenced by HAL_RNG_Init().

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STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RNG Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generates a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generates a 32-bit random number in interrupt mode.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handles RNG interrupt request.
uint32_t | HAL_RNG_ReadLastRandomNumber (RNG_HandleTypeDef *hrng)
Read latest generated random number.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callbacks.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Get the 32 bit Random number
      (+) Get the 32 bit Random number with interrupt enabled
      (+) Handle RNG interrupt request

Function Documentation

void HAL_RNG_ErrorCallback ( RNG_HandleTypeDef * hrng )

RNG error callbacks.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 422 of file stm32h7xx_hal_rng.c.

Referenced by HAL_RNG_IRQHandler().

HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber | ( | RNG_HandleTypeDef * | hrng,
 |  | uint32_t * | random32bit
 | ) |  |

Generates a 32-bit random number.

Note:
Each time the random number data is read the RNG_FLAG_DRDY flag is automatically cleared.
Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
random32bit,: pointer to generated random number variable if successful.
Return values:
HAL status

Definition at line 248 of file stm32h7xx_hal_rng.c.

References __HAL_RNG_GET_FLAG, HAL_GetTick(), HAL_RNG_STATE_BUSY, HAL_RNG_STATE_ERROR, HAL_RNG_STATE_READY, RNG_HandleTypeDef::Instance, RNG_HandleTypeDef::RandomNumber, RNG_FLAG_DRDY, RNG_TIMEOUT_VALUE, and RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT ( RNG_HandleTypeDef * hrng )

Generates a 32-bit random number in interrupt mode.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

Definition at line 302 of file stm32h7xx_hal_rng.c.

References __HAL_RNG_ENABLE_IT, HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, and RNG_HandleTypeDef::State.

void HAL_RNG_IRQHandler ( RNG_HandleTypeDef * hrng )

Handles RNG interrupt request.

Note:
In the case of a clock error, the RNG is no more able to generate random numbers because the PLL48CLK clock is not correct. User has to check that the clock controller is correctly configured to provide the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). The clock error has no impact on the previously generated random numbers, and the RNG_DR register contents can be used.
In the case of a seed error, the generation of random numbers is interrupted as long as the SECS bit is '1'. If a number is available in the RNG_DR register, it must not be used because it may not have enough entropy. In this case, it is recommended to clear the SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable the RNG peripheral to reinitialize and restart the RNG.
User-written HAL_RNG_ErrorCallback() API is called once whether SEIS or CEIS are set.
Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 353 of file stm32h7xx_hal_rng.c.

References __HAL_RNG_CLEAR_IT, __HAL_RNG_DISABLE_IT, __HAL_RNG_GET_IT, HAL_RNG_ErrorCallback(), HAL_RNG_ReadyDataCallback(), HAL_RNG_STATE_ERROR, HAL_RNG_STATE_READY, RNG_HandleTypeDef::Instance, RNG_HandleTypeDef::RandomNumber, RNG_IT_CEI, RNG_IT_DRDY, RNG_IT_SEI, and RNG_HandleTypeDef::State.

uint32_t HAL_RNG_ReadLastRandomNumber ( RNG_HandleTypeDef * hrng )

Read latest generated random number.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
random value

Definition at line 394 of file stm32h7xx_hal_rng.c.

References RNG_HandleTypeDef::RandomNumber.

void HAL_RNG_ReadyDataCallback | ( | RNG_HandleTypeDef * | hrng,
 |  | uint32_t | random32bit
 | ) |  |

Data Ready callback in non-blocking mode.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
random32bit,: generated random number.
Return values:
None

Definition at line 406 of file stm32h7xx_hal_rng.c.

Referenced by HAL_RNG_IRQHandler().

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STM32H753xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
RNG Exported Functions

Peripheral State functions. More...

Functions

HAL_RNG_StateTypeDef HAL_RNG_GetState (RNG_HandleTypeDef *hrng)
Returns the RNG state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_RNG_StateTypeDef HAL_RNG_GetState ( RNG_HandleTypeDef * hrng )

Returns the RNG state.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL state

Definition at line 456 of file stm32h7xx_hal_rng.c.

References RNG_HandleTypeDef::State.

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STM32H753xx HAL User Manual: RNG Private Types

RNG Private Types
RNG Exported Types
Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RNG Private Defines

RNG Private Defines
RNG Exported Types
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STM32H753xx HAL User Manual: RNG Private Variables

RNG Private Variables
RNG Exported Types
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STM32H753xx HAL User Manual: RNG Private Constants

Defines
RNG Private Constants
RNG Exported Types | RNG

Defines

#define RNG_TIMEOUT_VALUE 2U

Define Documentation

#define RNG_TIMEOUT_VALUE 2U

Definition at line 80 of file stm32h7xx_hal_rng.c.

Referenced by HAL_RNG_GenerateRandomNumber().

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STM32H753xx HAL User Manual: RNG Private Macros

Defines
RNG Private Macros
RNG Exported Types

Defines

#define | IS_RNG_IT(IT)
#define | IS_RNG_FLAG(FLAG)
#define | IS_RNG_CED(CED)

Define Documentation

#define IS_RNG_CED ( CED )
Value:
(((CED) == RNG_CED_ENABLE) || \
                           ((CED) == RNG_CED_DISABLE))

Definition at line 341 of file stm32h7xx_hal_rng.h.

Referenced by HAL_RNG_Init().

#define IS_RNG_FLAG ( FLAG )
Value:
(((FLAG) == RNG_FLAG_DRDY) || \
                           ((FLAG) == RNG_FLAG_CECS) || \
                           ((FLAG) == RNG_FLAG_SECS))

Definition at line 337 of file stm32h7xx_hal_rng.h.

#define IS_RNG_IT ( IT )
Value:
(((IT) == RNG_IT_CEI) || \
                       ((IT) == RNG_IT_SEI))

Definition at line 334 of file stm32h7xx_hal_rng.h.

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STM32H753xx HAL User Manual: RNG Private Functions Prototypes

RNG Private Functions Prototypes
RNG Exported Types
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STM32H753xx HAL User Manual: RNG Private Functions

RNG Private Functions
RNG Exported Types
Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SD Private Functions

Functions
SD Private Functions
SD | SD Exported Functions

Functions

static uint32_t | SD_InitCard (SD_HandleTypeDef *hsd)
Initializes the sd card.
static uint32_t | SD_PowerON (SD_HandleTypeDef *hsd)
Enquires cards about their operating voltage and configures clock controls and stores SD information that will be needed in future in the SD handle.
static uint32_t | SD_SendSDStatus (SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
Send Status info command.
static uint32_t | SD_SendStatus (SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
Returns the current card's status.
static uint32_t | SD_WideBus_Enable (SD_HandleTypeDef *hsd)
Enables the SDMMC wide bus mode.
static uint32_t | SD_WideBus_Disable (SD_HandleTypeDef *hsd)
Disables the SDMMC wide bus mode.
static uint32_t | SD_FindSCR (SD_HandleTypeDef *hsd, uint32_t *pSCR)
Finds the SD card SCR register value.
static HAL_StatusTypeDef | SD_PowerOFF (SD_HandleTypeDef *hsd)
Turns the SDMMC output signals off.
static HAL_StatusTypeDef | SD_Write_IT (SD_HandleTypeDef *hsd)
Wrap up writing in non-blocking mode.
static HAL_StatusTypeDef | SD_Read_IT (SD_HandleTypeDef *hsd)
Wrap up writing in non-blocking mode.
static uint32_t | SD_HighSpeed (SD_HandleTypeDef *hsd)
Switches the SD card to High Speed mode.
__weak void | HAL_SDEx_Read_DMADoubleBuffer0CpltCallback (SD_HandleTypeDef *hsd)
Read DMA Buffer 0 Transfer completed callbacks.
__weak void | HAL_SDEx_Read_DMADoubleBuffer1CpltCallback (SD_HandleTypeDef *hsd)
Read DMA Buffer 1 Transfer completed callbacks.
__weak void | HAL_SDEx_Write_DMADoubleBuffer0CpltCallback (SD_HandleTypeDef *hsd)
Write DMA Buffer 0 Transfer completed callbacks.
__weak void | HAL_SDEx_Write_DMADoubleBuffer1CpltCallback (SD_HandleTypeDef *hsd)
Write DMA Buffer 1 Transfer completed callbacks.

Function Documentation

__weak void HAL_SDEx_Read_DMADoubleBuffer0CpltCallback ( SD_HandleTypeDef * hsd )

Read DMA Buffer 0 Transfer completed callbacks.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 2879 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_IRQHandler().

__weak void HAL_SDEx_Read_DMADoubleBuffer1CpltCallback ( SD_HandleTypeDef * hsd )

Read DMA Buffer 1 Transfer completed callbacks.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 2894 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_IRQHandler().

__weak void HAL_SDEx_Write_DMADoubleBuffer0CpltCallback ( SD_HandleTypeDef * hsd )

Write DMA Buffer 0 Transfer completed callbacks.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 2909 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_IRQHandler().

__weak void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback ( SD_HandleTypeDef * hsd )

Write DMA Buffer 1 Transfer completed callbacks.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 2924 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_IRQHandler().

static uint32_t SD_FindSCR | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pSCR
 | ) |  | [static]

Finds the SD card SCR register value.

Parameters:
hsd,: Pointer to SD handle
pSCR,: pointer to the buffer that will contain the SCR value
Return values:
error state

Definition at line 2619 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_GET_FLAG, HAL_GetTick(), HAL_SD_ERROR_DATA_CRC_FAIL, HAL_SD_ERROR_DATA_TIMEOUT, HAL_SD_ERROR_NONE, HAL_SD_ERROR_RX_OVERRUN, HAL_SD_ERROR_TIMEOUT, SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::RelCardAdd, and SD_HandleTypeDef::SdCard.

Referenced by SD_WideBus_Disable(), and SD_WideBus_Enable().

static uint32_t SD_HighSpeed ( SD_HandleTypeDef * hsd ) [static]

Switches the SD card to High Speed mode.

This API must be used after "Transfer State"

Note:
This operation should be followed by the configuration of PLL to have SDMMCCK clock between 50 and 120 MHz
Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 2762 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_GET_FLAG, CARD_NORMAL_SPEED, CARD_ULTRA_HIGH_SPEED, HAL_SD_CardInfoTypeDef::CardSpeed, SD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SD_ERROR_REQUEST_NOT_APPLICABLE, HAL_SD_ERROR_TIMEOUT, HAL_SD_STATE_READY, SD_HandleTypeDef::Instance, SD_HandleTypeDef::SdCard, and SD_HandleTypeDef::State.

Referenced by HAL_SD_Init().

static uint32_t SD_InitCard ( SD_HandleTypeDef * hsd ) [static]

Initializes the sd card.

Parameters:
hsd,: Pointer to SD handle
Return values:
SD Card error state

Definition at line 2148 of file stm32h7xx_hal_sd.c.

References CARD_SECURED, HAL_SD_CardInfoTypeDef::CardType, SD_HandleTypeDef::CID, HAL_SD_CardInfoTypeDef::Class, SD_HandleTypeDef::CSD, HAL_SD_ERROR_NONE, HAL_SD_ERROR_REQUEST_NOT_APPLICABLE, HAL_SD_GetCardCSD(), SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::RelCardAdd, and SD_HandleTypeDef::SdCard.

Referenced by HAL_SD_InitCard().

static HAL_StatusTypeDef SD_PowerOFF ( SD_HandleTypeDef * hsd ) [static]

Turns the SDMMC output signals off.

Parameters:
hsd,: Pointer to SD handle
Return values:
HAL status

Definition at line 2381 of file stm32h7xx_hal_sd.c.

References SD_HandleTypeDef::Instance.

Referenced by HAL_SD_DeInit().

static uint32_t SD_PowerON ( SD_HandleTypeDef * hsd ) [static]

Enquires cards about their operating voltage and configures clock controls and stores SD information that will be needed in future in the SD handle.

Parameters:
hsd,: Pointer to SD handle
Return values:
error state

Definition at line 2235 of file stm32h7xx_hal_sd.c.

References CARD_SDHC_SDXC, CARD_ULTRA_HIGH_SPEED, CARD_V1_X, CARD_V2_X, HAL_SD_CardInfoTypeDef::CardSpeed, HAL_SD_CardInfoTypeDef::CardType, HAL_SD_CardInfoTypeDef::CardVersion, HAL_GetTick(), HAL_SD_DriveTransciver_1_8V_Callback(), HAL_SD_ERROR_INVALID_VOLTRANGE, HAL_SD_ERROR_NONE, HAL_SD_ERROR_TIMEOUT, HAL_SD_ERROR_UNSUPPORTED_FEATURE, SD_HandleTypeDef::Instance, and SD_HandleTypeDef::SdCard.

Referenced by HAL_SD_InitCard().

static HAL_StatusTypeDef SD_Read_IT ( SD_HandleTypeDef * hsd ) [static]

Wrap up writing in non-blocking mode.

Parameters:
hsd,: pointer to a SD_HandleTypeDef structure that contains the configuration information.
Return values:
HAL status

Definition at line 2710 of file stm32h7xx_hal_sd.c.

References SD_HandleTypeDef::Instance, and SD_HandleTypeDef::pRxBuffPtr.

Referenced by HAL_SD_IRQHandler().

static uint32_t SD_SendSDStatus | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pSDstatus
 | ) |  | [static]

Send Status info command.

Parameters:
hsd,: pointer to SD handle
pSDstatus,: Pointer to the buffer that will contain the SD card status SD Status register)
Return values:
error state

Definition at line 2397 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_GET_FLAG, SD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SD_ERROR_DATA_CRC_FAIL, HAL_SD_ERROR_DATA_TIMEOUT, HAL_SD_ERROR_LOCK_UNLOCK_FAILED, HAL_SD_ERROR_NONE, HAL_SD_ERROR_RX_OVERRUN, HAL_SD_ERROR_TIMEOUT, SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::RelCardAdd, and SD_HandleTypeDef::SdCard.

Referenced by HAL_SD_GetCardStatus().

static uint32_t SD_SendStatus | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pCardStatus
 | ) |  | [static]

Returns the current card's status.

Parameters:
hsd,: Pointer to SD handle
pCardStatus,: pointer to the buffer that will contain the SD card status (Card Status register)
Return values:
error state

Definition at line 2499 of file stm32h7xx_hal_sd.c.

References HAL_SD_ERROR_NONE, HAL_SD_ERROR_PARAM, SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::RelCardAdd, and SD_HandleTypeDef::SdCard.

Referenced by HAL_SD_GetCardState().

static uint32_t SD_WideBus_Disable ( SD_HandleTypeDef * hsd ) [static]

Disables the SDMMC wide bus mode.

Parameters:
hsd,: Pointer to SD handle
Return values:
error state

Definition at line 2573 of file stm32h7xx_hal_sd.c.

References HAL_SD_ERROR_LOCK_UNLOCK_FAILED, HAL_SD_ERROR_NONE, SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::RelCardAdd, SD_FindSCR(), and SD_HandleTypeDef::SdCard.

Referenced by HAL_SD_ConfigWideBusOperation().

static uint32_t SD_WideBus_Enable ( SD_HandleTypeDef * hsd ) [static]

Enables the SDMMC wide bus mode.

Parameters:
hsd,: pointer to SD handle
Return values:
error state

Definition at line 2526 of file stm32h7xx_hal_sd.c.

References HAL_SD_ERROR_LOCK_UNLOCK_FAILED, HAL_SD_ERROR_NONE, HAL_SD_ERROR_REQUEST_NOT_APPLICABLE, SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::RelCardAdd, SD_FindSCR(), and SD_HandleTypeDef::SdCard.

Referenced by HAL_SD_ConfigWideBusOperation().

static HAL_StatusTypeDef SD_Write_IT ( SD_HandleTypeDef * hsd ) [static]

Wrap up writing in non-blocking mode.

Parameters:
hsd,: pointer to a SD_HandleTypeDef structure that contains the configuration information.
Return values:
HAL status

Definition at line 2735 of file stm32h7xx_hal_sd.c.

References SD_HandleTypeDef::Instance, and SD_HandleTypeDef::pTxBuffPtr.

Referenced by HAL_SD_IRQHandler().

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STM32H753xx HAL User Manual: SD State enumeration structure

Enumerations
SD State enumeration structure
SD Exported Types

Enumerations

enum HAL_SD_StateTypeDef {
HAL_SD_STATE_RESET = ((uint32_t)0x00000000U), HAL_SD_STATE_READY = ((uint32_t)0x00000001U), HAL_SD_STATE_TIMEOUT = ((uint32_t)0x00000002U), HAL_SD_STATE_BUSY = ((uint32_t)0x00000003U),
HAL_SD_STATE_PROGRAMMING = ((uint32_t)0x00000004U), HAL_SD_STATE_RECEIVING = ((uint32_t)0x00000005U), HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU)
}

Enumeration Type Documentation

enum HAL_SD_StateTypeDef
Enumerator:
HAL_SD_STATE_RESET

SD not yet initialized or disabled

HAL_SD_STATE_READY

SD initialized and ready for use

HAL_SD_STATE_TIMEOUT

SD Timeout state

HAL_SD_STATE_BUSY

SD process ongoing

HAL_SD_STATE_PROGRAMMING

SD Programming State

HAL_SD_STATE_RECEIVING

SD Receinving State

HAL_SD_STATE_TRANSFER

SD Transfert State

HAL_SD_STATE_ERROR

SD is in error state

Definition at line 69 of file stm32h7xx_hal_sd.h.

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STM32H753xx HAL User Manual: SD Card State enumeration structure

Enumerations
SD Card State enumeration structure
SD Exported Types

Enumerations

enum HAL_SD_CardStateTypedef {
HAL_SD_CARD_READY = ((uint32_t)0x00000001U), HAL_SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), HAL_SD_CARD_STANDBY = ((uint32_t)0x00000003U), HAL_SD_CARD_TRANSFER = ((uint32_t)0x00000004U),
HAL_SD_CARD_SENDING = ((uint32_t)0x00000005U), HAL_SD_CARD_RECEIVING = ((uint32_t)0x00000006U), HAL_SD_CARD_PROGRAMMING = ((uint32_t)0x00000007U), HAL_SD_CARD_DISCONNECTED = ((uint32_t)0x00000008U),
HAL_SD_CARD_ERROR = ((uint32_t)0x000000FFU)
}

Enumeration Type Documentation

enum HAL_SD_CardStateTypedef
Enumerator:
HAL_SD_CARD_READY

Card state is ready

HAL_SD_CARD_IDENTIFICATION

Card is in identification state

HAL_SD_CARD_STANDBY

Card is in standby state

HAL_SD_CARD_TRANSFER

Card is in transfer state

HAL_SD_CARD_SENDING

Card is sending an operation

HAL_SD_CARD_RECEIVING

Card is receiving operation information

HAL_SD_CARD_PROGRAMMING

Card is in programming state

HAL_SD_CARD_DISCONNECTED

Card is disconnected

HAL_SD_CARD_ERROR

Card response Error

Definition at line 87 of file stm32h7xx_hal_sd.h.

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STM32H753xx HAL User Manual: SD Handle Structure definition

Data Structures | Defines
SD Handle Structure definition
SD Exported Types

Data Structures

struct | HAL_SD_CardInfoTypeDef
SD Card Information Structure definition. More...
struct | SD_HandleTypeDef
SD handle Structure definition. More...

Defines

#define | SD_InitTypeDef SDMMC_InitTypeDef
#define | SD_TypeDef SDMMC_TypeDef

Define Documentation

#define SD_InitTypeDef SDMMC_InitTypeDef

Definition at line 106 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_InitCard().

#define SD_TypeDef SDMMC_TypeDef

Definition at line 107 of file stm32h7xx_hal_sd.h.

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STM32H753xx HAL User Manual: HAL_SD_CardInfoTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_SD_CardInfoTypeDef Struct Reference
SD Handle Structure definition

SD Card Information Structure definition. More...

#include <stm32h7xx_hal_sd.h>

Data Fields

uint32_t | CardType
uint32_t | CardVersion
uint32_t | Class
uint32_t | RelCardAdd
uint32_t | BlockNbr
uint32_t | BlockSize
uint32_t | LogBlockNbr
uint32_t | LogBlockSize
uint32_t | CardSpeed

Detailed Description

SD Card Information Structure definition.

Definition at line 112 of file stm32h7xx_hal_sd.h.

Field Documentation

uint32_t HAL_SD_CardInfoTypeDef::BlockNbr

Specifies the Card Capacity in blocks

Definition at line 122 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD(), and HAL_SD_GetCardInfo().

uint32_t HAL_SD_CardInfoTypeDef::BlockSize

Specifies one block size in bytes

Definition at line 124 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD(), and HAL_SD_GetCardInfo().

uint32_t HAL_SD_CardInfoTypeDef::CardSpeed

Specifies the card Speed

Definition at line 130 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ConfigWideBusOperation(), HAL_SD_Init(), SD_HighSpeed(), and SD_PowerON().

uint32_t HAL_SD_CardInfoTypeDef::CardType

Specifies the card Type

Definition at line 114 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ConfigWideBusOperation(), HAL_SD_Erase(), HAL_SD_GetCardCSD(), HAL_SD_GetCardInfo(), HAL_SD_Init(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), HAL_SDEx_WriteBlocksDMAMultiBuffer(), SD_InitCard(), and SD_PowerON().

uint32_t HAL_SD_CardInfoTypeDef::CardVersion

Specifies the card version

Definition at line 116 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardInfo(), and SD_PowerON().

uint32_t HAL_SD_CardInfoTypeDef::Class

Specifies the class of the card class

Definition at line 118 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Erase(), HAL_SD_GetCardInfo(), and SD_InitCard().

uint32_t HAL_SD_CardInfoTypeDef::LogBlockNbr

Specifies the Card logical Capacity in blocks

Definition at line 126 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Erase(), HAL_SD_GetCardCSD(), HAL_SD_GetCardInfo(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), and HAL_SDEx_WriteBlocksDMAMultiBuffer().

uint32_t HAL_SD_CardInfoTypeDef::LogBlockSize

Specifies logical block size in bytes

Definition at line 128 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD(), and HAL_SD_GetCardInfo().

uint32_t HAL_SD_CardInfoTypeDef::RelCardAdd

Specifies the Relative Card Address

Definition at line 120 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardInfo(), SD_FindSCR(), SD_InitCard(), SD_SendSDStatus(), SD_SendStatus(), SD_WideBus_Disable(), and SD_WideBus_Enable().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sd.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SD_HandleTypeDef Struct Reference
SD Handle Structure definition

SD handle Structure definition. More...

#include <stm32h7xx_hal_sd.h>

Data Fields

SD_TypeDef * Instance
SD_InitTypeDef Init
HAL_LockTypeDef | Lock
uint32_t * | pTxBuffPtr
uint32_t | TxXferSize
uint32_t * | pRxBuffPtr
uint32_t | RxXferSize
__IO uint32_t | Context
__IO HAL_SD_StateTypeDef | State
__IO uint32_t | ErrorCode
HAL_SD_CardInfoTypeDef SdCard
uint32_t | CSD [4]
uint32_t | CID [4]

Detailed Description

SD handle Structure definition.

Definition at line 138 of file stm32h7xx_hal_sd.h.

Field Documentation

uint32_t SD_HandleTypeDef::CID[4]

SD card identification number table

Definition at line 164 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID(), and SD_InitCard().

__IO uint32_t SD_HandleTypeDef::Context

SD transfer context

Definition at line 154 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Init(), HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), and HAL_SDEx_WriteBlocksDMAMultiBuffer().

uint32_t SD_HandleTypeDef::CSD[4]

SD card specific data table

Definition at line 162 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD(), and SD_InitCard().

__IO uint32_t SD_HandleTypeDef::ErrorCode

SD Card Error codes

Definition at line 158 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Abort(), HAL_SD_Abort_IT(), HAL_SD_ConfigWideBusOperation(), HAL_SD_DeInit(), HAL_SD_Erase(), HAL_SD_GetCardCSD(), HAL_SD_GetCardState(), HAL_SD_GetCardStatus(), HAL_SD_GetError(), HAL_SD_Init(), HAL_SD_InitCard(), HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), HAL_SDEx_WriteBlocksDMAMultiBuffer(), SD_HighSpeed(), and SD_SendSDStatus().

SD_InitTypeDef SD_HandleTypeDef::Init

SD required parameters

Definition at line 142 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ConfigWideBusOperation(), and HAL_SD_Init().

SD_TypeDef* SD_HandleTypeDef::Instance

SD registers base address

Definition at line 140 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Abort(), HAL_SD_Abort_IT(), HAL_SD_ConfigWideBusOperation(), HAL_SD_DeInit(), HAL_SD_Erase(), HAL_SD_GetCardState(), HAL_SD_Init(), HAL_SD_InitCard(), HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ChangeDMABuffer(), HAL_SDEx_ConfigDMAMultiBuffer(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), HAL_SDEx_WriteBlocksDMAMultiBuffer(), SD_FindSCR(), SD_HighSpeed(), SD_InitCard(), SD_PowerOFF(), SD_PowerON(), SD_Read_IT(), SD_SendSDStatus(), SD_SendStatus(), SD_WideBus_Disable(), SD_WideBus_Enable(), and SD_Write_IT().

HAL_LockTypeDef SD_HandleTypeDef::Lock

SD locking object

Definition at line 144 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Init().

uint32_t* SD_HandleTypeDef::pRxBuffPtr

Pointer to SD Rx transfer Buffer

Definition at line 150 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), and SD_Read_IT().

uint32_t* SD_HandleTypeDef::pTxBuffPtr

Pointer to SD Tx transfer Buffer

Definition at line 146 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), and SD_Write_IT().

uint32_t SD_HandleTypeDef::RxXferSize

SD Rx Transfer size

Definition at line 152 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ReadBlocks_DMA(), and HAL_SD_ReadBlocks_IT().

HAL_SD_CardInfoTypeDef SD_HandleTypeDef::SdCard

SD Card information

Definition at line 160 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ConfigWideBusOperation(), HAL_SD_Erase(), HAL_SD_GetCardCSD(), HAL_SD_GetCardInfo(), HAL_SD_Init(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), HAL_SDEx_WriteBlocksDMAMultiBuffer(), SD_FindSCR(), SD_HighSpeed(), SD_InitCard(), SD_PowerON(), SD_SendSDStatus(), SD_SendStatus(), SD_WideBus_Disable(), and SD_WideBus_Enable().

__IO HAL_SD_StateTypeDef SD_HandleTypeDef::State

SD card State

Definition at line 156 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Abort(), HAL_SD_Abort_IT(), HAL_SD_ConfigWideBusOperation(), HAL_SD_DeInit(), HAL_SD_Erase(), HAL_SD_GetCardCSD(), HAL_SD_GetCardStatus(), HAL_SD_GetState(), HAL_SD_Init(), HAL_SD_InitCard(), HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ConfigDMAMultiBuffer(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), HAL_SDEx_WriteBlocksDMAMultiBuffer(), and SD_HighSpeed().

uint32_t SD_HandleTypeDef::TxXferSize

SD Tx Transfer size

Definition at line 148 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_WriteBlocks_DMA(), and HAL_SD_WriteBlocks_IT().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sd.h
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HAL_SD_CardCSDTypedef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_SD_CardCSDTypedef Struct Reference
Card Specific Data: CSD Register

#include <stm32h7xx_hal_sd.h>

Data Fields

__IO uint8_t | CSDStruct
__IO uint8_t | SysSpecVersion
__IO uint8_t | Reserved1
__IO uint8_t | TAAC
__IO uint8_t | NSAC
__IO uint8_t | MaxBusClkFrec
__IO uint16_t | CardComdClasses
__IO uint8_t | RdBlockLen
__IO uint8_t | PartBlockRead
__IO uint8_t | WrBlockMisalign
__IO uint8_t | RdBlockMisalign
__IO uint8_t | DSRImpl
__IO uint8_t | Reserved2
__IO uint32_t | DeviceSize
__IO uint8_t | MaxRdCurrentVDDMin
__IO uint8_t | MaxRdCurrentVDDMax
__IO uint8_t | MaxWrCurrentVDDMin
__IO uint8_t | MaxWrCurrentVDDMax
__IO uint8_t | DeviceSizeMul
__IO uint8_t | EraseGrSize
__IO uint8_t | EraseGrMul
__IO uint8_t | WrProtectGrSize
__IO uint8_t | WrProtectGrEnable
__IO uint8_t | ManDeflECC
__IO uint8_t | WrSpeedFact
__IO uint8_t | MaxWrBlockLen
__IO uint8_t | WriteBlockPaPartial
__IO uint8_t | Reserved3
__IO uint8_t | ContentProtectAppli
__IO uint8_t | FileFormatGrouop
__IO uint8_t | CopyFlag
__IO uint8_t | PermWrProtect
__IO uint8_t | TempWrProtect
__IO uint8_t | FileFormat
__IO uint8_t | ECC
__IO uint8_t | CSD_CRC
__IO uint8_t | Reserved4

Detailed Description

Definition at line 176 of file stm32h7xx_hal_sd.h.

Field Documentation

__IO uint16_t HAL_SD_CardCSDTypedef::CardComdClasses

Card command classes

Definition at line 184 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::ContentProtectAppli

Content protection application

Definition at line 206 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::CopyFlag

Copy flag (OTP)

Definition at line 208 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::CSD_CRC

CSD CRC

Definition at line 213 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::CSDStruct

CSD structure

Definition at line 178 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint32_t HAL_SD_CardCSDTypedef::DeviceSize

Device Size

Definition at line 191 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::DeviceSizeMul

Device size multiplier

Definition at line 196 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::DSRImpl

DSR implemented

Definition at line 189 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::ECC

ECC code

Definition at line 212 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::EraseGrMul

Erase group size multiplier

Definition at line 198 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::EraseGrSize

Erase group size

Definition at line 197 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::FileFormat

File format

Definition at line 211 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::FileFormatGrouop

File format group

Definition at line 207 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::ManDeflECC

Manufacturer default ECC

Definition at line 201 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::MaxBusClkFrec

Max. bus clock frequency

Definition at line 183 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::MaxRdCurrentVDDMax

Max. read current @ VDD max

Definition at line 193 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::MaxRdCurrentVDDMin

Max. read current @ VDD min

Definition at line 192 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::MaxWrBlockLen

Max. write data block length

Definition at line 203 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::MaxWrCurrentVDDMax

Max. write current @ VDD max

Definition at line 195 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::MaxWrCurrentVDDMin

Max. write current @ VDD min

Definition at line 194 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::NSAC

Data read access time 2 in CLK cycles

Definition at line 182 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::PartBlockRead

Partial blocks for read allowed

Definition at line 186 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::PermWrProtect

Permanent write protection

Definition at line 209 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::RdBlockLen

Max. read data block length

Definition at line 185 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::RdBlockMisalign

Read block misalignment

Definition at line 188 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::Reserved1

Reserved

Definition at line 180 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::Reserved2

Reserved

Definition at line 190 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::Reserved3

Reserved

Definition at line 205 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::Reserved4

Always 1

Definition at line 214 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::SysSpecVersion

System specification version

Definition at line 179 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::TAAC

Data read access time 1

Definition at line 181 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::TempWrProtect

Temporary write protection

Definition at line 210 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::WrBlockMisalign

Write block misalignment

Definition at line 187 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::WriteBlockPaPartial

Partial blocks for write allowed

Definition at line 204 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::WrProtectGrEnable

Write protect group enable

Definition at line 200 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::WrProtectGrSize

Write protect group size

Definition at line 199 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

__IO uint8_t HAL_SD_CardCSDTypedef::WrSpeedFact

Write speed factor

Definition at line 202 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sd.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HAL_SD_CardCIDTypedef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_SD_CardCIDTypedef Struct Reference
Card Identification Data: CID Register

#include <stm32h7xx_hal_sd.h>

Data Fields

__IO uint8_t | ManufacturerID
__IO uint16_t | OEM_AppliID
__IO uint32_t | ProdName1
__IO uint8_t | ProdName2
__IO uint8_t | ProdRev
__IO uint32_t | ProdSN
__IO uint8_t | Reserved1
__IO uint16_t | ManufactDate
__IO uint8_t | CID_CRC
__IO uint8_t | Reserved2

Detailed Description

Definition at line 223 of file stm32h7xx_hal_sd.h.

Field Documentation

__IO uint8_t HAL_SD_CardCIDTypedef::CID_CRC

CID CRC

Definition at line 233 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID().

__IO uint16_t HAL_SD_CardCIDTypedef::ManufactDate

Manufacturing Date

Definition at line 232 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID().

__IO uint8_t HAL_SD_CardCIDTypedef::ManufacturerID

Manufacturer ID

Definition at line 225 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID().

__IO uint16_t HAL_SD_CardCIDTypedef::OEM_AppliID

OEM/Application ID

Definition at line 226 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID().

__IO uint32_t HAL_SD_CardCIDTypedef::ProdName1

Product Name part1

Definition at line 227 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID().

__IO uint8_t HAL_SD_CardCIDTypedef::ProdName2

Product Name part2

Definition at line 228 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID().

__IO uint8_t HAL_SD_CardCIDTypedef::ProdRev

Product Revision

Definition at line 229 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID().

__IO uint32_t HAL_SD_CardCIDTypedef::ProdSN

Product Serial Number

Definition at line 230 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID().

__IO uint8_t HAL_SD_CardCIDTypedef::Reserved1

Reserved1

Definition at line 231 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID().

__IO uint8_t HAL_SD_CardCIDTypedef::Reserved2

Always 1

Definition at line 234 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCID().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sd.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HAL_SD_CardStatusTypedef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_SD_CardStatusTypedef Struct Reference
SD Card Status returned by ACMD13

#include <stm32h7xx_hal_sd.h>

Data Fields

__IO uint8_t | DataBusWidth
__IO uint8_t | SecuredMode
__IO uint16_t | CardType
__IO uint32_t | ProtectedAreaSize
__IO uint8_t | SpeedClass
__IO uint8_t | PerformanceMove
__IO uint8_t | AllocationUnitSize
__IO uint16_t | EraseSize
__IO uint8_t | EraseTimeout
__IO uint8_t | EraseOffset

Detailed Description

Definition at line 244 of file stm32h7xx_hal_sd.h.

Field Documentation

__IO uint8_t HAL_SD_CardStatusTypedef::AllocationUnitSize

Carries information about the card's allocation unit size

Definition at line 252 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint16_t HAL_SD_CardStatusTypedef::CardType

Carries information about card type

Definition at line 248 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint8_t HAL_SD_CardStatusTypedef::DataBusWidth

Shows the currently defined data bus width

Definition at line 246 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint8_t HAL_SD_CardStatusTypedef::EraseOffset

Carries information about the erase offset

Definition at line 255 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint16_t HAL_SD_CardStatusTypedef::EraseSize

Determines the number of AUs to be erased in one operation

Definition at line 253 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint8_t HAL_SD_CardStatusTypedef::EraseTimeout

Determines the timeout for any number of AU erase

Definition at line 254 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint8_t HAL_SD_CardStatusTypedef::PerformanceMove

Carries information about the card's performance move

Definition at line 251 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint32_t HAL_SD_CardStatusTypedef::ProtectedAreaSize

Carries information about the capacity of protected area

Definition at line 249 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint8_t HAL_SD_CardStatusTypedef::SecuredMode

Card is in secured mode of operation

Definition at line 247 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint8_t HAL_SD_CardStatusTypedef::SpeedClass

Carries information about the speed class of the card

Definition at line 250 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

The documentation for this struct was generated from the following file:
  • stm32h7xx_hal_sd.h
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SD Error status enumeration Structure definition

Defines
SD Error status enumeration Structure definition
Exported Constants

Defines

#define | HAL_SD_ERROR_NONE SDMMC_ERROR_NONE
#define | HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL
#define | HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL
#define | HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT
#define | HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT
#define | HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN
#define | HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN
#define | HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED
#define | HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR
#define | HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR
#define | HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM
#define | HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION
#define | HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED
#define | HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED
#define | HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD
#define | HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED
#define | HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR
#define | HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR
#define | HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN
#define | HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN
#define | HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE
#define | HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP
#define | HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED
#define | HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET
#define | HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR
#define | HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE
#define | HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE
#define | HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE
#define | HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER
#define | HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE
#define | HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY
#define | HAL_SD_ERROR_DMA SDMMC_ERROR_DMA
#define | HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT

Define Documentation

#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED

Misaligned address

Definition at line 283 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE

Error when addressed block is out of range

Definition at line 305 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Erase(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), and HAL_SDEx_WriteBlocksDMAMultiBuffer().

#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR

Error in sequence of authentication

Definition at line 303 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM

An invalid selection for erase groups

Definition at line 287 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR

Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length

Definition at line 284 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY

Error when transfer process is busy

Definition at line 309 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ReadBlocks(), and HAL_SD_WriteBlocks().

#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED

Command has been executed without using internal ECC

Definition at line 300 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED

Card internal ECC was applied but failed to correct the data

Definition at line 293 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR

Internal card controller error

Definition at line 294 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE

CID/CSD overwrite error

Definition at line 298 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL

Command response received (but CRC check failed)

Definition at line 277 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT

Command response timeout

Definition at line 279 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED

CRC check of the previous command failed

Definition at line 291 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL

Data block sent/received (CRC check failed)

Definition at line 278 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ReadBlocks(), HAL_SD_WriteBlocks(), SD_FindSCR(), and SD_SendSDStatus().

#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT

Data timeout

Definition at line 280 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ReadBlocks(), HAL_SD_WriteBlocks(), SD_FindSCR(), and SD_SendSDStatus().

#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA

Error while DMA transfer

Definition at line 310 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET

Erase sequence was cleared before executing because an out of erase sequence command was received

Definition at line 301 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR

An error in the sequence of erase command occurs

Definition at line 286 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR

General or unknown error

Definition at line 295 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD

Command is not legal for the card state

Definition at line 292 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE

Error in case of invalid voltage range

Definition at line 304 of file stm32h7xx_hal_sd.h.

Referenced by SD_PowerON().

#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED

Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card

Definition at line 289 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Erase(), SD_SendSDStatus(), SD_WideBus_Disable(), and SD_WideBus_Enable().

#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE

No error

Definition at line 276 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Abort(), HAL_SD_Abort_IT(), HAL_SD_ConfigWideBusOperation(), HAL_SD_DeInit(), HAL_SD_Erase(), HAL_SD_GetCardState(), HAL_SD_GetCardStatus(), HAL_SD_InitCard(), HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), HAL_SDEx_WriteBlocksDMAMultiBuffer(), SD_FindSCR(), SD_InitCard(), SD_PowerON(), SD_SendSDStatus(), SD_SendStatus(), SD_WideBus_Disable(), and SD_WideBus_Enable().

#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER

the used parameter is not valid

Definition at line 307 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ConfigWideBusOperation(), HAL_SD_Erase(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), and SD_SendStatus().

#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE

Error when command request is not applicable

Definition at line 306 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Erase(), SD_HighSpeed(), SD_InitCard(), and SD_WideBus_Enable().

#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN

Receive FIFO overrun

Definition at line 282 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ReadBlocks(), SD_FindSCR(), and SD_SendSDStatus().

#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN

The card could not sustain data reading in stream rmode

Definition at line 296 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN

The card could not sustain data programming in stream mode

Definition at line 297 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT

Timeout Error

Definition at line 311 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ReadBlocks(), SD_FindSCR(), SD_HighSpeed(), SD_PowerON(), and SD_SendSDStatus().

#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN

Transmit FIFO underrun

Definition at line 281 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_WriteBlocks().

#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE

Error when feature is not insupported

Definition at line 308 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ConfigWideBusOperation(), HAL_SD_GetCardCSD(), and SD_PowerON().

#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP

Only partial address space was erased

Definition at line 299 of file stm32h7xx_hal_sd.h.

#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION

Attempt to program a write protect block

Definition at line 288 of file stm32h7xx_hal_sd.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SD context enumeration

Defines
SD context enumeration
Exported Constants

Defines

#define | SD_CONTEXT_NONE ((uint32_t)0x00000000U)
#define | SD_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U)
#define | SD_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U)
#define | SD_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U)
#define | SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)
#define | SD_CONTEXT_IT ((uint32_t)0x00000008U)
#define | SD_CONTEXT_DMA ((uint32_t)0x00000080U)

Define Documentation

#define SD_CONTEXT_DMA ((uint32_t)0x00000080U)

Process in DMA mode

Definition at line 326 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_IRQHandler(), HAL_SD_ReadBlocks_DMA(), HAL_SD_WriteBlocks_DMA(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), and HAL_SDEx_WriteBlocksDMAMultiBuffer().

#define SD_CONTEXT_IT ((uint32_t)0x00000008U)

Process in Interrupt mode

Definition at line 325 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_IRQHandler(), HAL_SD_ReadBlocks_IT(), and HAL_SD_WriteBlocks_IT().

#define SD_CONTEXT_NONE ((uint32_t)0x00000000U)

None

Definition at line 320 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Init().

#define SD_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U)

Read multiple blocks operation

Definition at line 322 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), and HAL_SDEx_ReadBlocksDMAMultiBuffer().

#define SD_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U)

Read single block operation

Definition at line 321 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), and HAL_SD_ReadBlocks_IT().

#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)

Write multiple blocks operation

Definition at line 324 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_IRQHandler(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), and HAL_SDEx_WriteBlocksDMAMultiBuffer().

#define SD_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U)

Write single block operation

Definition at line 323 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_IRQHandler(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), and HAL_SD_WriteBlocks_IT().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SD Supported Memory Cards

Defines
SD Supported Memory Cards
Exported Constants

Defines

#define | CARD_NORMAL_SPEED ((uint32_t)0x00000000U)
#define | CARD_HIGH_SPEED ((uint32_t)0x00000100U)
#define | CARD_ULTRA_HIGH_SPEED ((uint32_t)0x00000200U)
#define | CARD_SDSC ((uint32_t)0x00000000U)
#define | CARD_SDHC_SDXC ((uint32_t)0x00000001U)
#define | CARD_SECURED ((uint32_t)0x00000003U)

Define Documentation

#define CARD_HIGH_SPEED ((uint32_t)0x00000100U)

High Speed Card <25Mo/s , Spec version 2.00

Definition at line 336 of file stm32h7xx_hal_sd.h.

#define CARD_NORMAL_SPEED ((uint32_t)0x00000000U)

Normal Speed Card <12.5Mo/s , Spec Version 1.01

Definition at line 335 of file stm32h7xx_hal_sd.h.

Referenced by SD_HighSpeed().

#define CARD_SDHC_SDXC ((uint32_t)0x00000001U)

SD High Capacity <32Go, SD Extended Capacity <2To

Definition at line 341 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Erase(), HAL_SD_GetCardCSD(), HAL_SD_Init(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), HAL_SDEx_WriteBlocksDMAMultiBuffer(), and SD_PowerON().

#define CARD_SDSC ((uint32_t)0x00000000U)

SD Standard Capacity <2Go

Definition at line 340 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_GetCardCSD().

#define CARD_SECURED ((uint32_t)0x00000003U)

Definition at line 342 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ConfigWideBusOperation(), HAL_SD_Erase(), HAL_SD_ReadBlocks(), HAL_SD_WriteBlocks(), and SD_InitCard().

#define CARD_ULTRA_HIGH_SPEED ((uint32_t)0x00000200U)

UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards and <104Mo/s for SDR104, Spec version 3.01

Definition at line 337 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ConfigWideBusOperation(), HAL_SD_Init(), SD_HighSpeed(), and SD_PowerON().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SD Supported Version

Defines
SD Supported Version
Exported Constants

Defines

#define | CARD_V1_X ((uint32_t)0x00000000U)
#define | CARD_V2_X ((uint32_t)0x00000001U)

Define Documentation

#define CARD_V1_X ((uint32_t)0x00000000U)

Definition at line 351 of file stm32h7xx_hal_sd.h.

Referenced by SD_PowerON().

#define CARD_V2_X ((uint32_t)0x00000001U)

Definition at line 352 of file stm32h7xx_hal_sd.h.

Referenced by SD_PowerON().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Exported Constants

Modules | Defines
Exported Constants
SD

Modules

SD Error status enumeration Structure definition
SD context enumeration
SD Supported Memory Cards
SD Supported Version

Defines

#define BLOCKSIZE ((uint32_t)512U)

Define Documentation

#define BLOCKSIZE ((uint32_t)512U)

Block size is 512 bytes

Definition at line 271 of file stm32h7xx_hal_sd.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SD Exported Macros

Defines
SD Exported Macros
SD

macros to handle interrupts and specific clock configurations More...

Defines

#define | __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Enable the SD device interrupt.
#define | __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Disable the SD device interrupt.
#define | __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
Check whether the specified SD flag is set or not.
#define | __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
Clear the SD's pending flags.
#define | __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Check whether the specified SD interrupt has occurred or not.
#define | __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Clear the SD's interrupt pending bits.

Detailed Description

macros to handle interrupts and specific clock configurations

Define Documentation

#define __HAL_SD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))

Clear the SD's pending flags.

Parameters:
__HANDLE__,: SD Handle
__FLAG__,: specifies the flag to clear. This parameter can be one or a combination of the following values:
  • SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
  • SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
  • SDMMC_FLAG_CTIMEOUT: Command response timeout
  • SDMMC_FLAG_DTIMEOUT: Data timeout
  • SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
  • SDMMC_FLAG_RXOVERR: Received FIFO overrun error
  • SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
  • SDMMC_FLAG_CMDSENT: Command sent (no response required)
  • SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
  • SDMMC_FLAG_DHOLD: Data transfer Hold
  • SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
  • SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
  • SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
  • SDMMC_FLAG_SDIOIT: SDIO interrupt received
  • SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
  • SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
  • SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
  • SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
  • SDMMC_FLAG_IDMATE: IDMA transfer error
  • SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
Return values:
None

Definition at line 496 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Abort(), HAL_SD_Abort_IT(), HAL_SD_ConfigWideBusOperation(), HAL_SD_Erase(), HAL_SD_GetCardCSD(), HAL_SD_GetCardStatus(), HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), SD_FindSCR(), SD_HighSpeed(), and SD_SendSDStatus().

#define __HAL_SD_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))

Clear the SD's interrupt pending bits.

Parameters:
__HANDLE__,: SD Handle
__INTERRUPT__,: specifies the interrupt pending bit to clear. This parameter can be one or a combination of the following values:
  • SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDMMC_IT_CTIMEOUT: Command response timeout interrupt
  • SDMMC_IT_DTIMEOUT: Data timeout interrupt
  • SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
  • SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
  • SDMMC_IT_DHOLD: Data transfer Hold interrupt
  • SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
  • SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
  • SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
  • SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
  • SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
  • SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
  • SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
  • SDMMC_IT_IDMATE: IDMA transfer error interrupt
  • SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
Return values:
None

Definition at line 563 of file stm32h7xx_hal_sd.h.

#define __HAL_SD_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))

Disable the SD device interrupt.

Parameters:
__HANDLE__,: SD Handle
__INTERRUPT__,: specifies the SDMMC interrupt sources to be disabled. This parameter can be one or a combination of the following values:
  • SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDMMC_IT_CTIMEOUT: Command response timeout interrupt
  • SDMMC_IT_DTIMEOUT: Data timeout interrupt
  • SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
  • SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
  • SDMMC_IT_DHOLD: Data transfer Hold interrupt
  • SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
  • SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  • SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  • SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
  • SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
  • SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
  • SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
  • SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
  • SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
  • SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
  • SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
  • SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
Return values:
None

Definition at line 429 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_Abort(), HAL_SD_Abort_IT(), HAL_SD_IRQHandler(), HAL_SD_ReadBlocks_DMA(), and HAL_SD_WriteBlocks_DMA().

#define __HAL_SD_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))

Enable the SD device interrupt.

Parameters:
__HANDLE__,: SD Handle
__INTERRUPT__,: specifies the SDMMC interrupt sources to be enabled. This parameter can be one or a combination of the following values:
  • SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDMMC_IT_CTIMEOUT: Command response timeout interrupt
  • SDMMC_IT_DTIMEOUT: Data timeout interrupt
  • SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
  • SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
  • SDMMC_IT_DHOLD: Data transfer Hold interrupt
  • SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
  • SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  • SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  • SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
  • SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
  • SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
  • SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
  • SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
  • SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
  • SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
  • SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
  • SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
Return values:
None

Definition at line 397 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_ReadBlocks_DMA(), HAL_SD_ReadBlocks_IT(), HAL_SD_WriteBlocks_DMA(), HAL_SD_WriteBlocks_IT(), HAL_SDEx_ReadBlocksDMAMultiBuffer(), and HAL_SDEx_WriteBlocksDMAMultiBuffer().

#define __HAL_SD_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))

Check whether the specified SD flag is set or not.

Parameters:
__HANDLE__,: SD Handle
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
  • SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
  • SDMMC_FLAG_CTIMEOUT: Command response timeout
  • SDMMC_FLAG_DTIMEOUT: Data timeout
  • SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
  • SDMMC_FLAG_RXOVERR: Received FIFO overrun error
  • SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
  • SDMMC_FLAG_CMDSENT: Command sent (no response required)
  • SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
  • SDMMC_FLAG_DHOLD: Data transfer Hold
  • SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
  • SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
  • SDMMC_FLAG_CPSMACT: Command path state machine active
  • SDMMC_FLAG_DPSMACT: Data path state machine active
  • SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
  • SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
  • SDMMC_FLAG_TXFIFOF: Transmit FIFO full
  • SDMMC_FLAG_RXFIFOF: Receive FIFO full
  • SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
  • SDMMC_FLAG_RXFIFOE: Receive FIFO empty
  • SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
  • SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
  • SDMMC_FLAG_SDIOIT: SDIO interrupt received
  • SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
  • SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
  • SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
  • SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
  • SDMMC_FLAG_IDMATE: IDMA transfer error
  • SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
Return values:
The new state of SD FLAG (SET or RESET).

Definition at line 467 of file stm32h7xx_hal_sd.h.

Referenced by HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_WriteBlocks(), SD_FindSCR(), SD_HighSpeed(), and SD_SendSDStatus().

#define __HAL_SD_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))

Check whether the specified SD interrupt has occurred or not.

Parameters:
__HANDLE__,: SD Handle
__INTERRUPT__,: specifies the SDMMC interrupt source to check. This parameter can be one of the following values:
  • SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDMMC_IT_CTIMEOUT: Command response timeout interrupt
  • SDMMC_IT_DTIMEOUT: Data timeout interrupt
  • SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
  • SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
  • SDMMC_IT_DHOLD: Data transfer Hold interrupt
  • SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
  • SDMMC_IT_DPSMACT: Data path state machine active interrupt
  • SDMMC_IT_CPSMACT: Command path state machine active interrupt
  • SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  • SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  • SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
  • SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
  • SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
  • SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
  • SDMMC_IT_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
  • SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
  • SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
  • SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
  • SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
  • SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
  • SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
  • SDMMC_IT_IDMATE: IDMA transfer error interrupt
  • SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
Return values:
The new state of SD IT (SET or RESET).

Definition at line 534 of file stm32h7xx_hal_sd.h.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SD Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_SD_Init (SD_HandleTypeDef *hsd)
Initializes the SD according to the specified parameters in the SD_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SD_InitCard (SD_HandleTypeDef *hsd)
Initializes the SD Card according to the specified parameters in the.
HAL_StatusTypeDef | HAL_SD_DeInit (SD_HandleTypeDef *hsd)
De-Initializes the SD card.
__weak void | HAL_SD_MspInit (SD_HandleTypeDef *hsd)
Initializes the SD MSP.
__weak void | HAL_SD_MspDeInit (SD_HandleTypeDef *hsd)
De-Initialize SD MSP.

Detailed Description

Initialization and de-initialization functions.

  ==============================================================================
          ##### Initialization and de-initialization functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to initialize/de-initialize the SD
    card device to be ready for use.

Function Documentation

HAL_StatusTypeDef HAL_SD_DeInit ( SD_HandleTypeDef * hsd )

De-Initializes the SD card.

Parameters:
hsd,: Pointer to SD handle
Return values:
HAL status

Definition at line 356 of file stm32h7xx_hal_sd.c.

References assert_param, SD_HandleTypeDef::ErrorCode, HAL_SD_DriveTransciver_1_8V_Callback(), HAL_SD_ERROR_NONE, HAL_SD_MspDeInit(), HAL_SD_STATE_BUSY, HAL_SD_STATE_RESET, SD_HandleTypeDef::Instance, SD_PowerOFF(), and SD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SD_Init ( SD_HandleTypeDef * hsd )

Initializes the SD according to the specified parameters in the SD_HandleTypeDef and create the associated handle.

Parameters:
hsd,: Pointer to the SD handle
Return values:
HAL status

Definition at line 236 of file stm32h7xx_hal_sd.c.

References assert_param, CARD_SDHC_SDXC, CARD_ULTRA_HIGH_SPEED, HAL_SD_CardInfoTypeDef::CardSpeed, HAL_SD_CardInfoTypeDef::CardType, SD_HandleTypeDef::Context, SD_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_SD_ConfigWideBusOperation(), HAL_SD_InitCard(), HAL_SD_MspInit(), HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, HAL_SD_STATE_RESET, SD_HandleTypeDef::Init, SD_HandleTypeDef::Instance, SD_HandleTypeDef::Lock, SD_CONTEXT_NONE, SD_HighSpeed(), SD_HandleTypeDef::SdCard, and SD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SD_InitCard ( SD_HandleTypeDef * hsd )

Initializes the SD Card according to the specified parameters in the.

Initializes the SD Card.

Parameters:
hsd,: Pointer to SD handle
Note:
This function initializes the SD card. It could be used when a card re-initialization is needed.
Return values:
HAL status

Definition at line 306 of file stm32h7xx_hal_sd.c.

References SD_HandleTypeDef::ErrorCode, HAL_SD_ERROR_NONE, HAL_SD_STATE_READY, __SAI_HandleTypeDef::Init, SD_HandleTypeDef::Instance, SD_InitCard(), SD_InitTypeDef, SD_PowerON(), and SD_HandleTypeDef::State.

Referenced by HAL_SD_Init().

void HAL_SD_MspDeInit ( SD_HandleTypeDef * hsd )

De-Initialize SD MSP.

Parameters:
hsd,: Pointer to SD handle
Return values:
None

Definition at line 407 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_DeInit().

void HAL_SD_MspInit ( SD_HandleTypeDef * hsd )

Initializes the SD MSP.

Parameters:
hsd,: Pointer to SD handle
Return values:
None

Definition at line 392 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_Init().

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
SD Exported Functions | Input and Output operation functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_SD_GetCardCID (SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef *pCID)
Returns information the information of the card which are stored on the CID register.
HAL_StatusTypeDef | HAL_SD_GetCardCSD (SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef *pCSD)
Returns information the information of the card which are stored on the CSD register.
HAL_StatusTypeDef | HAL_SD_GetCardStatus (SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pStatus)
Gets the SD status info.
HAL_StatusTypeDef | HAL_SD_GetCardInfo (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
Gets the SD card info.
HAL_StatusTypeDef | HAL_SD_ConfigWideBusOperation (SD_HandleTypeDef *hsd, uint32_t WideMode)
Enables wide bus operation for the requested card if supported by card.
HAL_SD_CardStateTypedef | HAL_SD_GetCardState (SD_HandleTypeDef *hsd)
Gets the current sd card data state.
HAL_StatusTypeDef | HAL_SD_Abort (SD_HandleTypeDef *hsd)
Abort the current transfer and disable the SD.
HAL_StatusTypeDef | HAL_SD_Abort_IT (SD_HandleTypeDef *hsd)
Abort the current transfer and disable the SD (IT mode).

Detailed Description

management functions

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control the SD card
    operations and get the related information

Function Documentation

HAL_StatusTypeDef HAL_SD_Abort ( SD_HandleTypeDef * hsd )

Abort the current transfer and disable the SD.

Parameters:
hsd,: pointer to a SD_HandleTypeDef structure that contains the configuration information for SD module.
Return values:
HAL status

Definition at line 2065 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_DISABLE_IT, SD_HandleTypeDef::ErrorCode, HAL_SD_CARD_RECEIVING, HAL_SD_CARD_SENDING, HAL_SD_ERROR_NONE, HAL_SD_GetCardState(), HAL_SD_STATE_READY, SD_HandleTypeDef::Instance, and SD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SD_Abort_IT ( SD_HandleTypeDef * hsd )

Abort the current transfer and disable the SD (IT mode).

Parameters:
hsd,: pointer to a SD_HandleTypeDef structure that contains the configuration information for SD module.
Return values:
HAL status

Definition at line 2099 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_DISABLE_IT, SD_HandleTypeDef::ErrorCode, HAL_SD_AbortCallback(), HAL_SD_CARD_RECEIVING, HAL_SD_CARD_SENDING, HAL_SD_ERROR_NONE, HAL_SD_GetCardState(), HAL_SD_STATE_READY, SD_HandleTypeDef::Instance, and SD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t | WideMode
 | ) |  |

Enables wide bus operation for the requested card if supported by card.

Parameters:
hsd,: Pointer to SD handle
WideMode,: Specifies the SD card wide bus mode This parameter can be one of the following values:
  • SDMMC_BUS_WIDE_8B: 8-bit data transfer
  • SDMMC_BUS_WIDE_4B: 4-bit data transfer
  • SDMMC_BUS_WIDE_1B: 1-bit data transfer
Return values:
HAL status

Definition at line 1953 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, assert_param, CARD_SECURED, CARD_ULTRA_HIGH_SPEED, HAL_SD_CardInfoTypeDef::CardSpeed, HAL_SD_CardInfoTypeDef::CardType, SD_HandleTypeDef::ErrorCode, HAL_SD_ERROR_NONE, HAL_SD_ERROR_PARAM, HAL_SD_ERROR_UNSUPPORTED_FEATURE, HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, SD_HandleTypeDef::Init, __SAI_HandleTypeDef::Init, SD_HandleTypeDef::Instance, SD_WideBus_Disable(), SD_WideBus_Enable(), SD_HandleTypeDef::SdCard, and SD_HandleTypeDef::State.

Referenced by HAL_SD_Init().

HAL_StatusTypeDef HAL_SD_GetCardCID | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardCIDTypedef * | pCID
 | ) |  |

Returns information the information of the card which are stored on the CID register.

Parameters:
hsd,: Pointer to SD handle
pCID,: Pointer to a HAL_SD_CIDTypedef structure that contains all CID register parameters
Return values:
HAL status

Definition at line 1610 of file stm32h7xx_hal_sd.c.

References SD_HandleTypeDef::CID, HAL_SD_CardCIDTypedef::CID_CRC, HAL_SD_CardCIDTypedef::ManufactDate, HAL_SD_CardCIDTypedef::ManufacturerID, HAL_SD_CardCIDTypedef::OEM_AppliID, HAL_SD_CardCIDTypedef::ProdName1, HAL_SD_CardCIDTypedef::ProdName2, HAL_SD_CardCIDTypedef::ProdRev, HAL_SD_CardCIDTypedef::ProdSN, HAL_SD_CardCIDTypedef::Reserved1, and HAL_SD_CardCIDTypedef::Reserved2.

HAL_StatusTypeDef HAL_SD_GetCardCSD | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardCSDTypedef * | pCSD
 | ) |  |

Returns information the information of the card which are stored on the CSD register.

Parameters:
hsd,: Pointer to SD handle
pCSD,: Pointer to a HAL_SD_CardInfoTypedef structure that contains all CSD register parameters
Return values:
HAL status

< Reserved

Definition at line 1691 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, HAL_SD_CardInfoTypeDef::BlockNbr, HAL_SD_CardInfoTypeDef::BlockSize, CARD_SDHC_SDXC, CARD_SDSC, HAL_SD_CardCSDTypedef::CardComdClasses, HAL_SD_CardInfoTypeDef::CardType, HAL_SD_CardCSDTypedef::ContentProtectAppli, HAL_SD_CardCSDTypedef::CopyFlag, SD_HandleTypeDef::CSD, HAL_SD_CardCSDTypedef::CSD_CRC, HAL_SD_CardCSDTypedef::CSDStruct, HAL_SD_CardCSDTypedef::DeviceSize, HAL_SD_CardCSDTypedef::DeviceSizeMul, HAL_SD_CardCSDTypedef::DSRImpl, HAL_SD_CardCSDTypedef::ECC, HAL_SD_CardCSDTypedef::EraseGrMul, HAL_SD_CardCSDTypedef::EraseGrSize, SD_HandleTypeDef::ErrorCode, HAL_SD_CardCSDTypedef::FileFormat, HAL_SD_CardCSDTypedef::FileFormatGrouop, HAL_SD_ERROR_UNSUPPORTED_FEATURE, HAL_SD_STATE_READY, HAL_SD_CardInfoTypeDef::LogBlockNbr, HAL_SD_CardInfoTypeDef::LogBlockSize, HAL_SD_CardCSDTypedef::ManDeflECC, HAL_SD_CardCSDTypedef::MaxBusClkFrec, HAL_SD_CardCSDTypedef::MaxRdCurrentVDDMax, HAL_SD_CardCSDTypedef::MaxRdCurrentVDDMin, HAL_SD_CardCSDTypedef::MaxWrBlockLen, HAL_SD_CardCSDTypedef::MaxWrCurrentVDDMax, HAL_SD_CardCSDTypedef::MaxWrCurrentVDDMin, HAL_SD_CardCSDTypedef::NSAC, HAL_SD_CardCSDTypedef::PartBlockRead, HAL_SD_CardCSDTypedef::PermWrProtect, HAL_SD_CardCSDTypedef::RdBlockLen, HAL_SD_CardCSDTypedef::RdBlockMisalign, HAL_SD_CardCSDTypedef::Reserved1, HAL_SD_CardCSDTypedef::Reserved2, HAL_SD_CardCSDTypedef::Reserved3, HAL_SD_CardCSDTypedef::Reserved4, SD_HandleTypeDef::SdCard, SD_HandleTypeDef::State, HAL_SD_CardCSDTypedef::SysSpecVersion, HAL_SD_CardCSDTypedef::TAAC, HAL_SD_CardCSDTypedef::TempWrProtect, HAL_SD_CardCSDTypedef::WrBlockMisalign, HAL_SD_CardCSDTypedef::WriteBlockPaPartial, HAL_SD_CardCSDTypedef::WrProtectGrEnable, HAL_SD_CardCSDTypedef::WrProtectGrSize, and HAL_SD_CardCSDTypedef::WrSpeedFact.

Referenced by SD_InitCard().

HAL_StatusTypeDef HAL_SD_GetCardInfo | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardInfoTypeDef * | pCardInfo
 | ) |  |

Gets the SD card info.

Parameters:
hsd,: Pointer to SD handle
pCardInfo,: Pointer to the HAL_SD_CardInfoTypeDef structure that will contain the SD card status information
Return values:
HAL status

Definition at line 1928 of file stm32h7xx_hal_sd.c.

References HAL_SD_CardInfoTypeDef::BlockNbr, HAL_SD_CardInfoTypeDef::BlockSize, HAL_SD_CardInfoTypeDef::CardType, HAL_SD_CardInfoTypeDef::CardVersion, HAL_SD_CardInfoTypeDef::Class, HAL_SD_CardInfoTypeDef::LogBlockNbr, HAL_SD_CardInfoTypeDef::LogBlockSize, HAL_SD_CardInfoTypeDef::RelCardAdd, and SD_HandleTypeDef::SdCard.

HAL_SD_CardStateTypedef HAL_SD_GetCardState ( SD_HandleTypeDef * hsd )

Gets the current sd card data state.

Parameters:
hsd,: pointer to SD handle
Return values:
Card state

Definition at line 2039 of file stm32h7xx_hal_sd.c.

References SD_HandleTypeDef::ErrorCode, HAL_SD_CARD_TRANSFER, HAL_SD_ERROR_NONE, SD_HandleTypeDef::Instance, and SD_SendStatus().

Referenced by HAL_SD_Abort(), HAL_SD_Abort_IT(), and HAL_SD_IRQHandler().

HAL_StatusTypeDef HAL_SD_GetCardStatus | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardStatusTypedef * | pStatus
 | ) |  |

Gets the SD status info.

Parameters:
hsd,: Pointer to SD handle
pStatus,: Pointer to the HAL_SD_CardStatusTypedef structure that will contain the SD card status information
Return values:
HAL status

Definition at line 1839 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, HAL_SD_CardStatusTypedef::AllocationUnitSize, HAL_SD_CardStatusTypedef::CardType, HAL_SD_CardStatusTypedef::DataBusWidth, HAL_SD_CardStatusTypedef::EraseOffset, HAL_SD_CardStatusTypedef::EraseSize, HAL_SD_CardStatusTypedef::EraseTimeout, SD_HandleTypeDef::ErrorCode, HAL_SD_ERROR_NONE, HAL_SD_STATE_READY, HAL_SD_CardStatusTypedef::PerformanceMove, HAL_SD_CardStatusTypedef::ProtectedAreaSize, SD_SendSDStatus(), HAL_SD_CardStatusTypedef::SecuredMode, HAL_SD_CardStatusTypedef::SpeedClass, and SD_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Input and Output operation functions

Modules | Functions
Input and Output operation functions
SD Exported Functions

Data transfer functions. More...

Modules

Peripheral Control functions

management functions

Functions

HAL_StatusTypeDef | HAL_SD_ReadBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SD_WriteBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Allows to write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SD_ReadBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SD_WriteBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SD_ReadBlocks_DMA (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SD_WriteBlocks_DMA (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SD_Erase (SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
Erases the specified memory area of the given SD card.
void | HAL_SD_IRQHandler (SD_HandleTypeDef *hsd)
This function handles SD card interrupt request.
HAL_SD_StateTypeDef | HAL_SD_GetState (SD_HandleTypeDef *hsd)
return the SD state
uint32_t | HAL_SD_GetError (SD_HandleTypeDef *hsd)
Return the SD error code.
__weak void | HAL_SD_TxCpltCallback (SD_HandleTypeDef *hsd)
Tx Transfer completed callbacks.
__weak void | HAL_SD_RxCpltCallback (SD_HandleTypeDef *hsd)
Rx Transfer completed callbacks.
__weak void | HAL_SD_ErrorCallback (SD_HandleTypeDef *hsd)
SD error callbacks.
__weak void | HAL_SD_AbortCallback (SD_HandleTypeDef *hsd)
SD Abort callbacks.
__weak void | HAL_SD_DriveTransciver_1_8V_Callback (FlagStatus status)
Enable/Disable the SD Transciver 1.8V Mode Callback.

Detailed Description

Data transfer functions.

  ==============================================================================
                        ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the data
    transfer from/to SD card.

Function Documentation

void HAL_SD_AbortCallback ( SD_HandleTypeDef * hsd )

SD Abort callbacks.

Parameters:
hsd,: Pointer SD handle
Return values:
None

Definition at line 1562 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_Abort_IT().

void HAL_SD_DriveTransciver_1_8V_Callback ( FlagStatus status )

Enable/Disable the SD Transciver 1.8V Mode Callback.

Parameters:
status,: Voltage Switch State
Return values:
None

Definition at line 1578 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_DeInit(), and SD_PowerON().

HAL_StatusTypeDef HAL_SD_Erase | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t | BlockStartAdd,
 |  | uint32_t | BlockEndAdd
 | ) |  |

Erases the specified memory area of the given SD card.

Note:
This API should be followed by a check on the card state through HAL_SD_GetCardState().
Parameters:
hsd,: Pointer to SD handle
BlockStartAdd,: Start Block address
BlockEndAdd,: End Block address
Return values:
HAL status

Definition at line 1209 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, CARD_SDHC_SDXC, CARD_SECURED, HAL_SD_CardInfoTypeDef::CardType, HAL_SD_CardInfoTypeDef::Class, SD_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_SD_ERROR_ADDR_OUT_OF_RANGE, HAL_SD_ERROR_LOCK_UNLOCK_FAILED, HAL_SD_ERROR_NONE, HAL_SD_ERROR_PARAM, HAL_SD_ERROR_REQUEST_NOT_APPLICABLE, HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::LogBlockNbr, SD_HandleTypeDef::SdCard, and SD_HandleTypeDef::State.

void HAL_SD_ErrorCallback ( SD_HandleTypeDef * hsd )

SD error callbacks.

Parameters:
hsd,: Pointer SD handle
Return values:
None

Definition at line 1547 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_IRQHandler().

uint32_t HAL_SD_GetError ( SD_HandleTypeDef * hsd )

Return the SD error code.

Parameters:
hsd : pointer to a SD_HandleTypeDef structure that contains the configuration information.
Return values:
SD Error Code

Definition at line 1507 of file stm32h7xx_hal_sd.c.

References SD_HandleTypeDef::ErrorCode.

HAL_SD_StateTypeDef HAL_SD_GetState ( SD_HandleTypeDef * hsd )

return the SD state

Parameters:
hsd,: Pointer to sd handle
Return values:
HAL state

Definition at line 1496 of file stm32h7xx_hal_sd.c.

References SD_HandleTypeDef::State.

void HAL_SD_IRQHandler ( SD_HandleTypeDef * hsd )

This function handles SD card interrupt request.

Parameters:
hsd,: Pointer to SD handle
Return values:
None

Definition at line 1309 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_DISABLE_IT, __HAL_SD_GET_FLAG, SD_HandleTypeDef::Context, SD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SD_CARD_TRANSFER, HAL_SD_ERROR_NONE, HAL_SD_ErrorCallback(), HAL_SD_GetCardState(), HAL_SD_RxCpltCallback(), HAL_SD_STATE_READY, HAL_SD_TxCpltCallback(), HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(), HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(), HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(), HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(), SD_HandleTypeDef::Instance, SD_CONTEXT_DMA, SD_CONTEXT_IT, SD_CONTEXT_READ_MULTIPLE_BLOCK, SD_CONTEXT_READ_SINGLE_BLOCK, SD_CONTEXT_WRITE_MULTIPLE_BLOCK, SD_CONTEXT_WRITE_SINGLE_BLOCK, SD_DMA_BUFFER0, SD_Read_IT(), SD_Write_IT(), and SD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SD_ReadBlocks | ( | SD_HandleTypeDef * | hsd,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks,
 |  | uint32_t | Timeout
 | ) |  |

Reads block(s) from a specified address in a card.

The Data transfer is managed by polling mode.

Note:
This API should be followed by a check on the card state through HAL_SD_GetCardState().
Parameters:
hsd,: Pointer to SD handle
pData,: pointer to the buffer that will contain the received data
BlockAdd,: Block Address from where data is to be read
NumberOfBlocks,: Number of SD blocks to read
Timeout
Return values:
HAL status

Definition at line 448 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_GET_FLAG, BLOCKSIZE, CARD_SDHC_SDXC, CARD_SECURED, HAL_SD_CardInfoTypeDef::CardType, SD_HandleTypeDef::Context, SD_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_GetTick(), HAL_SD_ERROR_ADDR_OUT_OF_RANGE, HAL_SD_ERROR_BUSY, HAL_SD_ERROR_DATA_CRC_FAIL, HAL_SD_ERROR_DATA_TIMEOUT, HAL_SD_ERROR_NONE, HAL_SD_ERROR_PARAM, HAL_SD_ERROR_RX_OVERRUN, HAL_SD_ERROR_TIMEOUT, HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::LogBlockNbr, SD_CONTEXT_READ_MULTIPLE_BLOCK, SD_CONTEXT_READ_SINGLE_BLOCK, SD_HandleTypeDef::SdCard, and SD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA | ( | SD_HandleTypeDef * | hsd,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Reads block(s) from a specified address in a card.

The Data transfer is managed by DMA mode.

Note:
This API should be followed by a check on the card state through HAL_SD_GetCardState().
You could also check the DMA transfer process through the SD Rx interrupt event.
Parameters:
hsd,: Pointer SD handle
pData,: Pointer to the buffer that will contain the received data
BlockAdd,: Block Address from where data is to be read
NumberOfBlocks,: Number of blocks to read.
Return values:
HAL status

Definition at line 996 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_DISABLE_IT, __HAL_SD_ENABLE_IT, BLOCKSIZE, CARD_SDHC_SDXC, HAL_SD_CardInfoTypeDef::CardType, SD_HandleTypeDef::Context, SD_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_SD_ERROR_ADDR_OUT_OF_RANGE, HAL_SD_ERROR_NONE, HAL_SD_ERROR_PARAM, HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::LogBlockNbr, SD_HandleTypeDef::pRxBuffPtr, SD_HandleTypeDef::RxXferSize, SD_CONTEXT_DMA, SD_CONTEXT_READ_MULTIPLE_BLOCK, SD_CONTEXT_READ_SINGLE_BLOCK, SD_HandleTypeDef::SdCard, and SD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SD_ReadBlocks_IT | ( | SD_HandleTypeDef * | hsd,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Reads block(s) from a specified address in a card.

The Data transfer is managed in interrupt mode.

Note:
This API should be followed by a check on the card state through HAL_SD_GetCardState().
You could also check the IT transfer process through the SD Rx interrupt event.
Parameters:
hsd,: Pointer to SD handle
pData,: Pointer to the buffer that will contain the received data
BlockAdd,: Block Address from where data is to be read
NumberOfBlocks,: Number of blocks to read.
Return values:
HAL status

Definition at line 791 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_ENABLE_IT, BLOCKSIZE, CARD_SDHC_SDXC, HAL_SD_CardInfoTypeDef::CardType, SD_HandleTypeDef::Context, SD_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_SD_ERROR_ADDR_OUT_OF_RANGE, HAL_SD_ERROR_NONE, HAL_SD_ERROR_PARAM, HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::LogBlockNbr, SD_HandleTypeDef::pRxBuffPtr, SD_HandleTypeDef::RxXferSize, SD_CONTEXT_IT, SD_CONTEXT_READ_MULTIPLE_BLOCK, SD_CONTEXT_READ_SINGLE_BLOCK, SD_HandleTypeDef::SdCard, and SD_HandleTypeDef::State.

void HAL_SD_RxCpltCallback ( SD_HandleTypeDef * hsd )

Rx Transfer completed callbacks.

Parameters:
hsd,: Pointer SD handle
Return values:
None

Definition at line 1532 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_IRQHandler().

void HAL_SD_TxCpltCallback ( SD_HandleTypeDef * hsd )

Tx Transfer completed callbacks.

Parameters:
hsd,: Pointer to SD handle
Return values:
None

Definition at line 1517 of file stm32h7xx_hal_sd.c.

Referenced by HAL_SD_IRQHandler().

HAL_StatusTypeDef HAL_SD_WriteBlocks | ( | SD_HandleTypeDef * | hsd,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks,
 |  | uint32_t | Timeout
 | ) |  |

Allows to write block(s) to a specified address in a card.

The Data transfer is managed by polling mode.

Note:
This API should be followed by a check on the card state through HAL_SD_GetCardState().
Parameters:
hsd,: Pointer to SD handle
pData,: pointer to the buffer that will contain the data to transmit
BlockAdd,: Block Address where data will be written
NumberOfBlocks,: Number of SD blocks to write
Timeout
Return values:
HAL status

Definition at line 618 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_GET_FLAG, BLOCKSIZE, CARD_SDHC_SDXC, CARD_SECURED, HAL_SD_CardInfoTypeDef::CardType, SD_HandleTypeDef::Context, SD_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_GetTick(), HAL_SD_ERROR_ADDR_OUT_OF_RANGE, HAL_SD_ERROR_BUSY, HAL_SD_ERROR_DATA_CRC_FAIL, HAL_SD_ERROR_DATA_TIMEOUT, HAL_SD_ERROR_NONE, HAL_SD_ERROR_PARAM, HAL_SD_ERROR_TX_UNDERRUN, HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::LogBlockNbr, SD_CONTEXT_WRITE_MULTIPLE_BLOCK, SD_CONTEXT_WRITE_SINGLE_BLOCK, SD_HandleTypeDef::SdCard, and SD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA | ( | SD_HandleTypeDef * | hsd,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Writes block(s) to a specified address in a card.

The Data transfer is managed by DMA mode.

Note:
This API should be followed by a check on the card state through HAL_SD_GetCardState().
You could also check the DMA transfer process through the SD Tx interrupt event.
Parameters:
hsd,: Pointer to SD handle
pData,: pointer to the buffer that will contain the data to transmit
BlockAdd,: Block Address where data will be written
NumberOfBlocks,: Number of blocks to write
Return values:
HAL status

Definition at line 1105 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_DISABLE_IT, __HAL_SD_ENABLE_IT, BLOCKSIZE, CARD_SDHC_SDXC, HAL_SD_CardInfoTypeDef::CardType, SD_HandleTypeDef::Context, SD_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_SD_ERROR_ADDR_OUT_OF_RANGE, HAL_SD_ERROR_NONE, HAL_SD_ERROR_PARAM, HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::LogBlockNbr, SD_HandleTypeDef::pTxBuffPtr, SD_CONTEXT_DMA, SD_CONTEXT_WRITE_MULTIPLE_BLOCK, SD_CONTEXT_WRITE_SINGLE_BLOCK, SD_HandleTypeDef::SdCard, SD_HandleTypeDef::State, and SD_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SD_WriteBlocks_IT | ( | SD_HandleTypeDef * | hsd,
 |  | uint8_t * | pData,
 |  | uint32_t | BlockAdd,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Writes block(s) to a specified address in a card.

The Data transfer is managed in interrupt mode.

Note:
This API should be followed by a check on the card state through HAL_SD_GetCardState().
You could also check the IT transfer process through the SD Tx interrupt event.
Parameters:
hsd,: Pointer to SD handle
pData,: Pointer to the buffer that will contain the data to transmit
BlockAdd,: Block Address where data will be written
NumberOfBlocks,: Number of blocks to write
Return values:
HAL status

Definition at line 894 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_ENABLE_IT, BLOCKSIZE, CARD_SDHC_SDXC, HAL_SD_CardInfoTypeDef::CardType, SD_HandleTypeDef::Context, SD_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_SD_ERROR_ADDR_OUT_OF_RANGE, HAL_SD_ERROR_NONE, HAL_SD_ERROR_PARAM, HAL_SD_STATE_BUSY, HAL_SD_STATE_READY, SD_HandleTypeDef::Instance, HAL_SD_CardInfoTypeDef::LogBlockNbr, SD_HandleTypeDef::pTxBuffPtr, SD_CONTEXT_IT, SD_CONTEXT_WRITE_MULTIPLE_BLOCK, SD_CONTEXT_WRITE_SINGLE_BLOCK, SD_HandleTypeDef::SdCard, SD_HandleTypeDef::State, and SD_HandleTypeDef::TxXferSize.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SD card related functions

Functions
SD card related functions
SD Exported Functions

Functions

HAL_StatusTypeDef | HAL_SD_SendSDStatus (SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
HAL_SD_CardStateTypedef | HAL_SD_GetCardState (SD_HandleTypeDef *hsd)
Gets the current sd card data state.
HAL_StatusTypeDef | HAL_SD_GetCardCID (SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef *pCID)
Returns information the information of the card which are stored on the CID register.
HAL_StatusTypeDef | HAL_SD_GetCardCSD (SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef *pCSD)
Returns information the information of the card which are stored on the CSD register.
HAL_StatusTypeDef | HAL_SD_GetCardStatus (SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pStatus)
Gets the SD status info.
HAL_StatusTypeDef | HAL_SD_GetCardInfo (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
Gets the SD card info.

Function Documentation

HAL_StatusTypeDef HAL_SD_GetCardCID | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardCIDTypedef * | pCID
 | ) |  |

Returns information the information of the card which are stored on the CID register.

Parameters:
hsd,: Pointer to SD handle
pCID,: Pointer to a HAL_SD_CIDTypedef structure that contains all CID register parameters
Return values:
HAL status

Definition at line 1610 of file stm32h7xx_hal_sd.c.

References SD_HandleTypeDef::CID, HAL_SD_CardCIDTypedef::CID_CRC, HAL_SD_CardCIDTypedef::ManufactDate, HAL_SD_CardCIDTypedef::ManufacturerID, HAL_SD_CardCIDTypedef::OEM_AppliID, HAL_SD_CardCIDTypedef::ProdName1, HAL_SD_CardCIDTypedef::ProdName2, HAL_SD_CardCIDTypedef::ProdRev, HAL_SD_CardCIDTypedef::ProdSN, HAL_SD_CardCIDTypedef::Reserved1, and HAL_SD_CardCIDTypedef::Reserved2.

HAL_StatusTypeDef HAL_SD_GetCardCSD | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardCSDTypedef * | pCSD
 | ) |  |

Returns information the information of the card which are stored on the CSD register.

Parameters:
hsd,: Pointer to SD handle
pCSD,: Pointer to a HAL_SD_CardInfoTypedef structure that contains all CSD register parameters
Return values:
HAL status

< Reserved

Definition at line 1691 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, HAL_SD_CardInfoTypeDef::BlockNbr, HAL_SD_CardInfoTypeDef::BlockSize, CARD_SDHC_SDXC, CARD_SDSC, HAL_SD_CardCSDTypedef::CardComdClasses, HAL_SD_CardInfoTypeDef::CardType, HAL_SD_CardCSDTypedef::ContentProtectAppli, HAL_SD_CardCSDTypedef::CopyFlag, SD_HandleTypeDef::CSD, HAL_SD_CardCSDTypedef::CSD_CRC, HAL_SD_CardCSDTypedef::CSDStruct, HAL_SD_CardCSDTypedef::DeviceSize, HAL_SD_CardCSDTypedef::DeviceSizeMul, HAL_SD_CardCSDTypedef::DSRImpl, HAL_SD_CardCSDTypedef::ECC, HAL_SD_CardCSDTypedef::EraseGrMul, HAL_SD_CardCSDTypedef::EraseGrSize, SD_HandleTypeDef::ErrorCode, HAL_SD_CardCSDTypedef::FileFormat, HAL_SD_CardCSDTypedef::FileFormatGrouop, HAL_SD_ERROR_UNSUPPORTED_FEATURE, HAL_SD_STATE_READY, HAL_SD_CardInfoTypeDef::LogBlockNbr, HAL_SD_CardInfoTypeDef::LogBlockSize, HAL_SD_CardCSDTypedef::ManDeflECC, HAL_SD_CardCSDTypedef::MaxBusClkFrec, HAL_SD_CardCSDTypedef::MaxRdCurrentVDDMax, HAL_SD_CardCSDTypedef::MaxRdCurrentVDDMin, HAL_SD_CardCSDTypedef::MaxWrBlockLen, HAL_SD_CardCSDTypedef::MaxWrCurrentVDDMax, HAL_SD_CardCSDTypedef::MaxWrCurrentVDDMin, HAL_SD_CardCSDTypedef::NSAC, HAL_SD_CardCSDTypedef::PartBlockRead, HAL_SD_CardCSDTypedef::PermWrProtect, HAL_SD_CardCSDTypedef::RdBlockLen, HAL_SD_CardCSDTypedef::RdBlockMisalign, HAL_SD_CardCSDTypedef::Reserved1, HAL_SD_CardCSDTypedef::Reserved2, HAL_SD_CardCSDTypedef::Reserved3, HAL_SD_CardCSDTypedef::Reserved4, SD_HandleTypeDef::SdCard, SD_HandleTypeDef::State, HAL_SD_CardCSDTypedef::SysSpecVersion, HAL_SD_CardCSDTypedef::TAAC, HAL_SD_CardCSDTypedef::TempWrProtect, HAL_SD_CardCSDTypedef::WrBlockMisalign, HAL_SD_CardCSDTypedef::WriteBlockPaPartial, HAL_SD_CardCSDTypedef::WrProtectGrEnable, HAL_SD_CardCSDTypedef::WrProtectGrSize, and HAL_SD_CardCSDTypedef::WrSpeedFact.

Referenced by SD_InitCard().

HAL_StatusTypeDef HAL_SD_GetCardInfo | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardInfoTypeDef * | pCardInfo
 | ) |  |

Gets the SD card info.

Parameters:
hsd,: Pointer to SD handle
pCardInfo,: Pointer to the HAL_SD_CardInfoTypeDef structure that will contain the SD card status information
Return values:
HAL status

Definition at line 1928 of file stm32h7xx_hal_sd.c.

References HAL_SD_CardInfoTypeDef::BlockNbr, HAL_SD_CardInfoTypeDef::BlockSize, HAL_SD_CardInfoTypeDef::CardType, HAL_SD_CardInfoTypeDef::CardVersion, HAL_SD_CardInfoTypeDef::Class, HAL_SD_CardInfoTypeDef::LogBlockNbr, HAL_SD_CardInfoTypeDef::LogBlockSize, HAL_SD_CardInfoTypeDef::RelCardAdd, and SD_HandleTypeDef::SdCard.

HAL_SD_CardStateTypedef HAL_SD_GetCardState ( SD_HandleTypeDef * hsd )

Gets the current sd card data state.

Parameters:
hsd,: pointer to SD handle
Return values:
Card state

Definition at line 2039 of file stm32h7xx_hal_sd.c.

References SD_HandleTypeDef::ErrorCode, HAL_SD_CARD_TRANSFER, HAL_SD_ERROR_NONE, SD_HandleTypeDef::Instance, and SD_SendStatus().

Referenced by HAL_SD_Abort(), HAL_SD_Abort_IT(), and HAL_SD_IRQHandler().

HAL_StatusTypeDef HAL_SD_GetCardStatus | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardStatusTypedef * | pStatus
 | ) |  |

Gets the SD status info.

Parameters:
hsd,: Pointer to SD handle
pStatus,: Pointer to the HAL_SD_CardStatusTypedef structure that will contain the SD card status information
Return values:
HAL status

Definition at line 1839 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, HAL_SD_CardStatusTypedef::AllocationUnitSize, HAL_SD_CardStatusTypedef::CardType, HAL_SD_CardStatusTypedef::DataBusWidth, HAL_SD_CardStatusTypedef::EraseOffset, HAL_SD_CardStatusTypedef::EraseSize, HAL_SD_CardStatusTypedef::EraseTimeout, SD_HandleTypeDef::ErrorCode, HAL_SD_ERROR_NONE, HAL_SD_STATE_READY, HAL_SD_CardStatusTypedef::PerformanceMove, HAL_SD_CardStatusTypedef::ProtectedAreaSize, SD_SendSDStatus(), HAL_SD_CardStatusTypedef::SecuredMode, HAL_SD_CardStatusTypedef::SpeedClass, and SD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SD_SendSDStatus | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pSDstatus
 | ) |  |
Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SD Exported Functions

Functions

HAL_SD_StateTypeDef | HAL_SD_GetState (SD_HandleTypeDef *hsd)
return the SD state
uint32_t | HAL_SD_GetError (SD_HandleTypeDef *hsd)
Return the SD error code.

Function Documentation

uint32_t HAL_SD_GetError ( SD_HandleTypeDef * hsd )

Return the SD error code.

Parameters:
hsd : pointer to a SD_HandleTypeDef structure that contains the configuration information.
Return values:
SD Error Code

Definition at line 1507 of file stm32h7xx_hal_sd.c.

References SD_HandleTypeDef::ErrorCode.

HAL_SD_StateTypeDef HAL_SD_GetState ( SD_HandleTypeDef * hsd )

return the SD state

Parameters:
hsd,: Pointer to sd handle
Return values:
HAL state

Definition at line 1496 of file stm32h7xx_hal_sd.c.

References SD_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Perioheral Abort management

Functions
Perioheral Abort management
SD Exported Functions

Functions

HAL_StatusTypeDef | HAL_SD_Abort (SD_HandleTypeDef *hsd)
Abort the current transfer and disable the SD.
HAL_StatusTypeDef | HAL_SD_Abort_IT (SD_HandleTypeDef *hsd)
Abort the current transfer and disable the SD (IT mode).

Function Documentation

HAL_StatusTypeDef HAL_SD_Abort ( SD_HandleTypeDef * hsd )

Abort the current transfer and disable the SD.

Parameters:
hsd,: pointer to a SD_HandleTypeDef structure that contains the configuration information for SD module.
Return values:
HAL status

Definition at line 2065 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_DISABLE_IT, SD_HandleTypeDef::ErrorCode, HAL_SD_CARD_RECEIVING, HAL_SD_CARD_SENDING, HAL_SD_ERROR_NONE, HAL_SD_GetCardState(), HAL_SD_STATE_READY, SD_HandleTypeDef::Instance, and SD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SD_Abort_IT ( SD_HandleTypeDef * hsd )

Abort the current transfer and disable the SD (IT mode).

Parameters:
hsd,: pointer to a SD_HandleTypeDef structure that contains the configuration information for SD module.
Return values:
HAL status

Definition at line 2099 of file stm32h7xx_hal_sd.c.

References __HAL_SD_CLEAR_FLAG, __HAL_SD_DISABLE_IT, SD_HandleTypeDef::ErrorCode, HAL_SD_AbortCallback(), HAL_SD_CARD_RECEIVING, HAL_SD_CARD_SENDING, HAL_SD_ERROR_NONE, HAL_SD_GetCardState(), HAL_SD_STATE_READY, SD_HandleTypeDef::Instance, and SD_HandleTypeDef::State.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SD Private Types

SD Private Types
SD Exported Functions
Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SD Private Defines

SD Private Defines
SD Exported Functions | SD
Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SD Private Variables

SD Private Variables
SD Exported Functions
Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SD Private Constants

SD Private Constants
SD Exported Functions
Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SD Private Macros

SD Private Macros
SD Exported Functions
Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SD Private Functions Prototypes

SD Private Functions Prototypes
SD Exported Functions
Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USARTEx Word Length

Defines
USARTEx Word Length
USARTEx Exported Constants

Defines

#define | USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define | USART_WORDLENGTH_8B ((uint32_t)0x00000000U)
#define | USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

Define Documentation

#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)

7-bit long USART frame

Definition at line 66 of file stm32h7xx_hal_usart_ex.h.

#define USART_WORDLENGTH_8B ((uint32_t)0x00000000U)

8-bit long USART frame

Definition at line 67 of file stm32h7xx_hal_usart_ex.h.

#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

9-bit long USART frame

Definition at line 68 of file stm32h7xx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USARTEx Private Macros

Defines
USARTEx Private Macros
USARTEx

Defines

#define | USART_MASK_COMPUTATION(__HANDLE__)
Compute the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_USART_WORD_LENGTH(__LENGTH__)
Ensure that USART frame length is valid.

Define Documentation

#define IS_USART_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == USART_WORDLENGTH_7B) || \
                                          ((__LENGTH__) == USART_WORDLENGTH_8B) || \
                                          ((__LENGTH__) == USART_WORDLENGTH_9B))

Ensure that USART frame length is valid.

Parameters:
__LENGTH__,: USART frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 135 of file stm32h7xx_hal_usart_ex.h.

Referenced by USART_SetConfig().

#define USART_MASK_COMPUTATION ( __HANDLE__ )

Compute the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Note:
If PCE = 1, the parity bit is not included in the data extracted by the reception API(). This masking operation is not carried out in the case of DMA transfers.
Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None,the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.

Definition at line 93 of file stm32h7xx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), and HAL_USART_TransmitReceive_IT().

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • k
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- a -

  • AccessPermission : MPU_Region_InitTypeDef
  • AccumulatedActiveH : LTDC_InitTypeDef
  • AccumulatedActiveW : LTDC_InitTypeDef
  • AccumulatedHBP : LTDC_InitTypeDef
  • AccumulatedVBP : LTDC_InitTypeDef
  • Activation : DFSDM_Channel_OutputClockTypeDef , SAI_PdmInitTypeDef
  • ActiveEdge : LPTIM_TriggerConfigTypeDef
  • ActiveFrameLength : SAI_FrameInitTypeDef
  • Activity : FDCAN_ProtocolStatusTypeDef
  • AdcClockSelection : RCC_PeriphCLKInitTypeDef
  • Address : FLASH_ProcessTypeDef , QSPI_CommandTypeDef , UART_WakeUpTypeDef
  • AddressAlignedBeats : ETH_DMAConfigTypeDef
  • AddressingMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • AddressLength : UART_WakeUpTypeDef
  • AddressMode : QSPI_CommandTypeDef
  • AddressSize : QSPI_CommandTypeDef
  • AddrEventCount : __I2C_HandleTypeDef
  • AdvancedInit : SMARTCARD_HandleTypeDef , UART_HandleTypeDef
  • AdvFeatureInit : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • AHBCLKDivider : RCC_ClkInitTypeDef
  • Alarm : RTC_AlarmTypeDef
  • AlarmDateWeekDay : RTC_AlarmTypeDef
  • AlarmDateWeekDaySel : RTC_AlarmTypeDef
  • AlarmMask : RTC_AlarmTypeDef
  • AlarmSubSecondMask : RTC_AlarmTypeDef
  • AlarmTime : RTC_AlarmTypeDef
  • Algorithm : CRYP_ConfigTypeDef
  • AllocationUnitSize : HAL_SD_CardStatusTypedef
  • Alpha : LTDC_LayerCfgTypeDef
  • Alpha0 : LTDC_LayerCfgTypeDef
  • AlphaInverted : DMA2D_InitTypeDef , DMA2D_LayerCfgTypeDef
  • AlphaMode : DMA2D_LayerCfgTypeDef
  • Alternate : GPIO_InitTypeDef
  • AlternateByteMode : QSPI_CommandTypeDef
  • AlternateBytes : QSPI_CommandTypeDef
  • AlternateBytesSize : QSPI_CommandTypeDef
  • AnalogFilter : SMBUS_InitTypeDef
  • APB1CLKDivider : RCC_ClkInitTypeDef
  • APB2CLKDivider : RCC_ClkInitTypeDef
  • APB3CLKDivider : RCC_ClkInitTypeDef
  • APB4CLKDivider : RCC_ClkInitTypeDef
  • AppContextDesc : ETH_RxDescListTypeDef
  • AppDescNbr : ETH_RxDescListTypeDef
  • AppWdgEvt : FDCAN_TTOperationStatusTypeDef
  • AppWdgLimit : FDCAN_TT_ConfigTypeDef
  • AsynchPrediv : RTC_InitTypeDef
  • Attributes : ETH_TxPacketConfig
  • AudioFreq : I2S_InitTypeDef
  • AudioFrequency : SAI_InitTypeDef
  • AudioMode : SAI_InitTypeDef
  • AutoBaudRateEnable : UART_AdvFeatureInitTypeDef
  • AutoBaudRateMode : UART_AdvFeatureInitTypeDef
  • AutoDelayedMode : HRTIM_CompareCfgTypeDef
  • AutoDelayedTimeout : HRTIM_CompareCfgTypeDef
  • AutoInjectedConv : ADC_InjectionConfTypeDef
  • AutomaticOutput : TIM_BreakDeadTimeConfigTypeDef
  • AutomaticPadCRCStrip : ETH_MACConfigTypeDef
  • AutomaticStop : QSPI_AutoPollingTypeDef
  • AutoReloadPreload : TIM_Base_InitTypeDef
  • AutoRetransmission : FDCAN_InitTypeDef
  • AutoRetryCount : SMARTCARD_InitTypeDef
  • AVDLevel : PWREx_AVDTypeDef
  • Awd : DFSDM_Channel_InitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
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  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- b -

  • B0 : CRYP_ConfigTypeDef
  • Backcolor : LTDC_InitTypeDef , LTDC_LayerCfgTypeDef
  • BackOffLimit : ETH_MACConfigTypeDef
  • Banks : FLASH_EraseInitTypeDef , FLASH_OBProgramInitTypeDef
  • BaseAddress : MPU_Region_InitTypeDef
  • BasicCyclesNbr : FDCAN_TT_ConfigTypeDef
  • battery_charging_active : PCD_HandleTypeDef
  • BaudRate : IRDA_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • BaudRatePrescaler : SPI_InitTypeDef
  • BESL : PCD_HandleTypeDef
  • BitRate : SWPMI_InitTypeDef
  • BitRateSwitch : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • Bits : JPEG_ACHuffTableTypeDef , JPEG_DCHuffTableTypeDef
  • BlankingSrce : COMP_InitTypeDef
  • BlendingFactor1 : LTDC_LayerCfgTypeDef
  • BlendingFactor2 : LTDC_LayerCfgTypeDef
  • Block : NAND_AddressTypeDef
  • BlockCount : MDMA_LinkNodeConfTypeDef
  • BlockDataLength : MDMA_LinkNodeConfTypeDef
  • BlockLength : SMARTCARD_InitTypeDef
  • BlockNbr : HAL_MMC_CardInfoTypeDef , NAND_DeviceConfigTypeDef , HAL_SD_CardInfoTypeDef
  • BlockSize : HAL_MMC_CardInfoTypeDef , NAND_DeviceConfigTypeDef , HAL_SD_CardInfoTypeDef
  • Blue : DMA2D_ColorTypeDef , LTDC_ColorTypeDef
  • BoostMode : ADC_InitTypeDef
  • BootAddr0 : FLASH_OBProgramInitTypeDef
  • BootAddr1 : FLASH_OBProgramInitTypeDef
  • BootConfig : FLASH_OBProgramInitTypeDef
  • BORLevel : FLASH_OBProgramInitTypeDef
  • Break2Filter : TIM_BreakDeadTimeConfigTypeDef
  • Break2Polarity : TIM_BreakDeadTimeConfigTypeDef
  • Break2State : TIM_BreakDeadTimeConfigTypeDef
  • BreakFilter : TIM_BreakDeadTimeConfigTypeDef
  • BreakPolarity : TIM_BreakDeadTimeConfigTypeDef
  • BreakState : TIM_BreakDeadTimeConfigTypeDef
  • BREErrorBitGen : CEC_InitTypeDef
  • BRERxStop : CEC_InitTypeDef
  • BroadcastFilter : ETH_MACFilterConfigTypeDef
  • BroadcastMsgNoErrorBitGen : CEC_InitTypeDef
  • buffer : __ETH_BufferTypeDef
  • BufferTransferLength : MDMA_InitTypeDef
  • BurstMode : HRTIM_TimerCfgTypeDef , ETH_DMAConfigTypeDef
  • BurstModeEntryDelayed : HRTIM_OutputCfgTypeDef
  • BusOff : FDCAN_ProtocolStatusTypeDef
  • ByteSelectMode : DCMI_InitTypeDef
  • ByteSelectStart : DCMI_InitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
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  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- c -

  • CalFieldLength : FDCAN_ClkCalUnitTypeDef
  • CaptureRate : DCMI_InitTypeDef
  • CaptureTrigger1 : HRTIM_TimerParamTypeDef
  • CaptureTrigger2 : HRTIM_TimerParamTypeDef
  • CardComdClasses : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • CardSpeed : HAL_SD_CardInfoTypeDef
  • CardType : HAL_MMC_CardInfoTypeDef , HAL_SD_CardInfoTypeDef , HAL_SD_CardStatusTypedef
  • CardVersion : HAL_SD_CardInfoTypeDef
  • CarrierFreq : HRTIM_ChopperModeCfgTypeDef
  • CarrierSenseBeforeTransmit : ETH_MACConfigTypeDef
  • CarrierSenseDuringTransmit : ETH_MACConfigTypeDef
  • CBNDTR : MDMA_LinkNodeTypeDef
  • CBRUR : MDMA_LinkNodeTypeDef
  • CDAR : MDMA_LinkNodeTypeDef
  • CecClockSelection : RCC_PeriphCLKInitTypeDef
  • CFI_1 : NOR_CFITypeDef
  • CFI_2 : NOR_CFITypeDef
  • CFI_3 : NOR_CFITypeDef
  • CFI_4 : NOR_CFITypeDef
  • Channel : ADC_AnalogWDGConfTypeDef , ADC_ChannelConfTypeDef , DFSDM_Filter_AwdParamTypeDef , TIM_HandleTypeDef
  • ChannelCount : ADC_InjectionConfigTypeDef
  • ChannelSelection : SPDIFRX_InitTypeDef
  • ChannelStatusMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • Checksum : ETH_RxPacketInfo
  • ChecksumCtrl : ETH_TxPacketConfig
  • ChecksumOffload : ETH_MACConfigTypeDef
  • ChipSelectHighTime : QSPI_InitTypeDef
  • ChopperModeEnable : HRTIM_OutputCfgTypeDef
  • ChromaSubsampling : JPEG_ConfTypeDef
  • ChromaSubSampling : DMA2D_LayerCfgTypeDef
  • CID : MMC_HandleTypeDef , SD_HandleTypeDef
  • CID_CRC : HAL_MMC_CardCIDTypedef , HAL_SD_CardCIDTypedef
  • CkperClockSelection : RCC_PeriphCLKInitTypeDef
  • CLAR : MDMA_LinkNodeTypeDef
  • Class : HAL_MMC_CardInfoTypeDef , HAL_SD_CardInfoTypeDef
  • ClearInputFilter : TIM_ClearInputConfigTypeDef
  • ClearInputPolarity : TIM_ClearInputConfigTypeDef
  • ClearInputPrescaler : TIM_ClearInputConfigTypeDef
  • ClearInputSource : TIM_ClearInputConfigTypeDef
  • ClearInputState : TIM_ClearInputConfigTypeDef
  • CLKLastBit : SMARTCARD_InitTypeDef , USART_InitTypeDef
  • CLKPhase : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • CLKPolarity : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • Clock : LPTIM_InitTypeDef
  • ClockCalibration : FDCAN_ClkCalUnitTypeDef , FDCAN_TT_ConfigTypeDef
  • ClockDivider : FDCAN_ClkCalUnitTypeDef
  • ClockDivision : TIM_Base_InitTypeDef
  • ClockEnable : SAI_PdmInitTypeDef
  • ClockErrorDetection : RNG_InitTypeDef
  • ClockFilter : TIM_ClockConfigTypeDef
  • ClockMode : QSPI_InitTypeDef
  • ClockPolarity : TIM_ClockConfigTypeDef
  • ClockPrescaler : ADC_InitTypeDef , QSPI_InitTypeDef , TIM_ClockConfigTypeDef
  • ClockQuality : FDCAN_TTOperationStatusTypeDef
  • ClockSource : HRTIM_BurstModeCfgTypeDef , TIM_ClockConfigTypeDef
  • ClockStrobing : SAI_InitTypeDef
  • ClockType : RCC_ClkInitTypeDef
  • CLUTColorMode : DMA2D_CLUTCfgTypeDef
  • CMAR : MDMA_LinkNodeTypeDef
  • CMDR : MDMA_LinkNodeTypeDef
  • CodeLength : JPEG_AC_HuffCodeTableTypeDef , JPEG_DC_HuffCodeTableTypeDef
  • ColorMode : DMA2D_InitTypeDef
  • ColorSpace : JPEG_ConfTypeDef
  • Commutation_Delay : TIM_HallSensor_InitTypeDef
  • CompandingMode : SAI_InitTypeDef
  • CompareValue : HRTIM_CompareCfgTypeDef
  • Conf : JPEG_HandleTypeDef
  • Config : NAND_HandleTypeDef
  • ContentProtectAppli : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • Context : JPEG_HandleTypeDef , MMC_HandleTypeDef , SD_HandleTypeDef
  • ContextQueue : ADC_InjectionConfigTypeDef
  • ContinuousConvMode : ADC_InitTypeDef
  • ControlPacketsFilter : ETH_MACFilterConfigTypeDef
  • ConversionDataManagement : ADC_InitTypeDef
  • CopyFlag : HAL_SD_CardCSDTypedef , HAL_MMC_CardCSDTypeDef
  • Counter : WWDG_InitTypeDef
  • CounterMode : TIM_Base_InitTypeDef
  • CounterSource : LPTIM_InitTypeDef
  • CPOL : I2S_InitTypeDef
  • CRCCalculation : SPI_InitTypeDef
  • CRCCheckingRxPackets : ETH_MACConfigTypeDef
  • CRCLength : CRC_InitTypeDef , SPI_InitTypeDef
  • CRCPadCtrl : ETH_TxPacketConfig
  • CRCPolynomial : SPI_InitTypeDef
  • CRCSize : __SPI_HandleTypeDef
  • CRCStripTypePacket : ETH_MACConfigTypeDef
  • CrypHeaderCount : CRYP_HandleTypeDef
  • CrypInCount : CRYP_HandleTypeDef
  • CrypOutCount : CRYP_HandleTypeDef
  • CSAR : MDMA_LinkNodeTypeDef
  • CSD : SD_HandleTypeDef , MMC_HandleTypeDef
  • CSD_CRC : HAL_SD_CardCSDTypedef , HAL_MMC_CardCSDTypeDef
  • CSDStruct : HAL_SD_CardCSDTypedef , HAL_MMC_CardCSDTypeDef
  • CSICalibrationValue : RCC_OscInitTypeDef
  • CSIState : RCC_OscInitTypeDef
  • CsXferCount : SPDIFRX_HandleTypeDef
  • CsXferSize : SPDIFRX_HandleTypeDef
  • CTBR : MDMA_LinkNodeTypeDef
  • CTCR : MDMA_LinkNodeTypeDef
  • CurRxDesc : ETH_RxDescListTypeDef
  • CurTxDesc : ETH_TxDescListTypeDef
  • CustomQuanTable : JPEG_HandleTypeDef
  • CycleStartSync : FDCAN_TT_ConfigTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
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  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- d -

  • DAC_ConnectOnChipPeripheral : DAC_ChannelConfTypeDef
  • DAC_HoldTime : DAC_SampleAndHoldConfTypeDef
  • DAC_OutputBuffer : DAC_ChannelConfTypeDef
  • DAC_RefreshTime : DAC_SampleAndHoldConfTypeDef
  • DAC_SampleAndHold : DAC_ChannelConfTypeDef
  • DAC_SampleAndHoldConfig : DAC_ChannelConfTypeDef
  • DAC_SampleTime : DAC_SampleAndHoldConfTypeDef
  • DAC_Trigger : DAC_ChannelConfTypeDef
  • DAC_TrimmingValue : DAC_ChannelConfTypeDef
  • DAC_UserTrimming : DAC_ChannelConfTypeDef
  • DACSynchro : HRTIM_TimerCfgTypeDef
  • Data24BitAlignment : I2S_InitTypeDef
  • DataAlignment : MDMA_InitTypeDef
  • DataBusWidth : HAL_SD_CardStatusTypedef
  • DataFormat : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef , I2S_InitTypeDef
  • DataInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • DataLastErrorCode : FDCAN_ProtocolStatusTypeDef
  • DataLength : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • DataMode : QSPI_CommandTypeDef
  • DataPacking : DFSDM_Channel_InputTypeDef
  • DataPrescaler : FDCAN_InitTypeDef
  • DataSize : SAI_InitTypeDef , SPI_InitTypeDef
  • DataSource : DFSDM_Filter_AwdParamTypeDef
  • DataSyncJumpWidth : FDCAN_InitTypeDef
  • DataTimeSeg1 : FDCAN_InitTypeDef
  • DataTimeSeg2 : FDCAN_InitTypeDef
  • DataType : CRYP_ConfigTypeDef , HASH_InitTypeDef
  • Date : RTC_DateTypeDef
  • DayLightSaving : RTC_TimeTypeDef
  • DdrHoldHalfCycle : QSPI_CommandTypeDef
  • DdrMode : QSPI_CommandTypeDef
  • DeadTime : TIM_BreakDeadTimeConfigTypeDef
  • DeadTimeInsertion : HRTIM_TimerCfgTypeDef
  • DefaultInitValueUse : CRC_InitTypeDef
  • DefaultPolynomialUse : CRC_InitTypeDef
  • DeferralCheck : ETH_MACConfigTypeDef
  • DelayedProtectionMode : HRTIM_TimerCfgTypeDef
  • DEPolarity : LTDC_InitTypeDef
  • DestAddrFilterMatch : ETH_L3FilterConfigTypeDef
  • DestAddrHigherBitsMatch : ETH_L3FilterConfigTypeDef
  • DestAddrInverseFiltering : ETH_MACFilterConfigTypeDef
  • DestBlockAddressOffset : MDMA_InitTypeDef
  • DestBurst : MDMA_InitTypeDef
  • DestDataSize : MDMA_InitTypeDef
  • DestinationInc : MDMA_InitTypeDef
  • DestinationPort : ETH_L4FilterConfigTypeDef
  • DestPortFilterMatch : ETH_L4FilterConfigTypeDef
  • Device_Code1 : NOR_IDTypeDef
  • Device_Code2 : NOR_IDTypeDef
  • Device_Code3 : NOR_IDTypeDef
  • Device_Id : NAND_IDTypeDef
  • DeviceSize : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • DeviceSizeMul : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • Dfsdm1ClockSelection : RCC_PeriphCLKInitTypeDef
  • DigestCalculationDisable : HASH_HandleTypeDef
  • Direction : DMA_InitTypeDef , SPI_InitTypeDef
  • DisableExec : MPU_Region_InitTypeDef
  • DiscontinuousConvMode : ADC_InitTypeDef
  • Divider : DFSDM_Channel_OutputClockTypeDef
  • DMA_Handle : ADC_HandleTypeDef , DCMI_HandleTypeDef
  • DMA_Handle1 : DAC_HandleTypeDef
  • DMA_Handle2 : DAC_HandleTypeDef
  • DMAArbitration : ETH_DMAConfigTypeDef
  • DMADisableonRxError : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • DMADstAddress : HRTIM_TimerCfgTypeDef , HRTIM_TimerParamTypeDef
  • DMAErrorCode : ETH_HandleTypeDef
  • DmaMode : DFSDM_Filter_RegularParamTypeDef , DFSDM_Filter_InjectedParamTypeDef
  • DMAmuxChannel : __DMA_HandleTypeDef
  • DMAmuxChannelStatus : __DMA_HandleTypeDef
  • DMAmuxChannelStatusMask : __DMA_HandleTypeDef
  • DMAmuxRequestGen : __DMA_HandleTypeDef
  • DMAmuxRequestGenStatus : __DMA_HandleTypeDef
  • DMAmuxRequestGenStatusMask : __DMA_HandleTypeDef
  • DMARequests : HRTIM_TimerParamTypeDef , HRTIM_TimerCfgTypeDef
  • DMASize : HRTIM_TimerParamTypeDef , HRTIM_TimerCfgTypeDef
  • DMASrcAddress : HRTIM_TimerParamTypeDef , HRTIM_TimerCfgTypeDef
  • DoubleVLANProcessing : ETH_RxVLANConfigTypeDef
  • DropTCPIPChecksumErrorPacket : ETH_MACConfigTypeDef
  • DSRImpl : HAL_SD_CardCSDTypedef , HAL_MMC_CardCSDTypeDef
  • DstAddress : MDMA_LinkNodeConfTypeDef
  • DualAddressMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • DualFlash : QSPI_InitTypeDef
  • DualModeData : ADC_MultiModeTypeDef
  • DummyCycles : QSPI_CommandTypeDef
  • DuplexMode : ETH_MACConfigTypeDef
  • DutyCycle : HRTIM_ChopperModeCfgTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
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  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- e -

  • ECC : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • ECSPending : FDCAN_TTOperationStatusTypeDef
  • Enable : MPU_Region_InitTypeDef , TIMEx_BreakInputConfigTypeDef
  • EncoderMode : TIM_Encoder_InitTypeDef
  • EndAddress : FDCAN_MsgRamAddressTypeDef
  • Endianness : MDMA_InitTypeDef
  • EOCSelection : ADC_InitTypeDef
  • EraseGrMul : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • EraseGrSize : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • EraseOffset : HAL_SD_CardStatusTypedef
  • EraseSize : HAL_SD_CardStatusTypedef
  • EraseTimeout : HAL_SD_CardStatusTypedef
  • ErrorCode : JPEG_HandleTypeDef , LTDC_HandleTypeDef , ADC_HandleTypeDef , __MDMA_HandleTypeDef , MMC_HandleTypeDef , CEC_HandleTypeDef , QSPI_HandleTypeDef , __SAI_HandleTypeDef , CRYP_HandleTypeDef , SD_HandleTypeDef , SMARTCARD_HandleTypeDef , DAC_HandleTypeDef , SMBUS_HandleTypeDef , SPDIFRX_HandleTypeDef , DCMI_HandleTypeDef , __SPI_HandleTypeDef , SWPMI_HandleTypeDef , DFSDM_Filter_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , __DMA_HandleTypeDef , __DMA2D_HandleTypeDef , ETH_RxPacketInfo , ETH_HandleTypeDef , FDCAN_HandleTypeDef , FLASH_ProcessTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , IRDA_HandleTypeDef
  • ErrorLevel : FDCAN_TTOperationStatusTypeDef
  • ErrorLimitValue : RCC_CRSInitTypeDef
  • ErrorLogging : FDCAN_ErrorCountersTypeDef
  • ErrorPassive : FDCAN_ProtocolStatusTypeDef
  • ErrorStateIndicator : FDCAN_RxHeaderTypeDef , FDCAN_TxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • Event : HRTIM_SimpleCaptureChannelCfgTypeDef , HRTIM_SimpleOnePulseChannelCfgTypeDef
  • EventEnable : HAL_DMA_MuxSyncConfigTypeDef
  • EventFilter : HRTIM_SimpleOnePulseChannelCfgTypeDef , HRTIM_SimpleCaptureChannelCfgTypeDef
  • EventPolarity : HRTIM_SimpleOnePulseChannelCfgTypeDef , HRTIM_SimpleCaptureChannelCfgTypeDef
  • EventSensitivity : HRTIM_SimpleOnePulseChannelCfgTypeDef , HRTIM_SimpleCaptureChannelCfgTypeDef
  • EventTrigSel : FDCAN_TT_ConfigTypeDef
  • EventType : FDCAN_TxEventFifoTypeDef
  • EvtTrigPolarity : FDCAN_TT_ConfigTypeDef
  • EWIMode : WWDG_InitTypeDef
  • ExpTxTrigNbr : FDCAN_TT_ConfigTypeDef
  • Extended : SRAM_HandleTypeDef , NOR_HandleTypeDef
  • ExtendedDataMode : DCMI_InitTypeDef
  • ExtendedFilterSA : FDCAN_MsgRamAddressTypeDef
  • ExtendedInterPacketGap : ETH_MACConfigTypeDef
  • ExtendedInterPacketGapVal : ETH_MACConfigTypeDef
  • ExternalClkSync : FDCAN_TT_ConfigTypeDef
  • ExternalTrigConv : ADC_InitTypeDef
  • ExternalTrigConvEdge : ADC_InitTypeDef
  • ExternalTrigInjecConv : ADC_InjectionConfTypeDef
  • ExternalTrigInjecConvEdge : ADC_InjectionConfTypeDef
  • ExtFiltersNbr : FDCAN_InitTypeDef
  • ExtraCommandEnable : NAND_DeviceConfigTypeDef
  • ExtTrigger : DFSDM_Filter_InjectedParamTypeDef
  • ExtTriggerEdge : DFSDM_Filter_HandleTypeDef , DFSDM_Filter_InjectedParamTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • k
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- f -

  • FallingLock : HRTIM_DeadTimeCfgTypeDef
  • FallingSign : HRTIM_DeadTimeCfgTypeDef
  • FallingSignLock : HRTIM_DeadTimeCfgTypeDef
  • FallingValue : HRTIM_DeadTimeCfgTypeDef
  • FastMode : DFSDM_Filter_RegularParamTypeDef , HRTIM_EventCfgTypeDef
  • FaultEnable : HRTIM_TimerCfgTypeDef
  • FaultLevel : HRTIM_OutputCfgTypeDef
  • FaultLock : HRTIM_TimerCfgTypeDef
  • FBStartAdress : LTDC_LayerCfgTypeDef
  • FdcanClockSelection : RCC_PeriphCLKInitTypeDef
  • FDFormat : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • FIFOMode : SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , DMA_InitTypeDef
  • FifoThreshold : I2S_InitTypeDef , QSPI_InitTypeDef , SPI_InitTypeDef
  • FIFOThreshold : DMA_InitTypeDef , SAI_InitTypeDef
  • FileFormat : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • FileFormatGrouop : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • Filter : HRTIM_TimerEventFilteringCfgTypeDef , HRTIM_EventCfgTypeDef , HRTIM_FaultCfgTypeDef , RTC_TamperTypeDef
  • FilterConfig : FDCAN_FilterTypeDef
  • FilterID1 : FDCAN_FilterTypeDef
  • FilterID2 : FDCAN_FilterTypeDef
  • FilterIndex : FDCAN_FilterTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_HpMsgStatusTypeDef , FDCAN_TriggerTypeDef
  • FilterList : FDCAN_HpMsgStatusTypeDef
  • FilterOrder : DFSDM_Channel_AwdTypeDef
  • FilterParam : DFSDM_Filter_InitTypeDef
  • FilterType : FDCAN_FilterTypeDef , FDCAN_TriggerTypeDef
  • FirstAppDesc : ETH_RxDescListTypeDef
  • FirstBit : I2S_InitTypeDef , SPI_InitTypeDef , SAI_InitTypeDef
  • FirstBitOffset : SAI_SlotInitTypeDef
  • FirstLinkedListNodeAddress : __MDMA_HandleTypeDef
  • FlashID : QSPI_InitTypeDef
  • FlashSize : QSPI_InitTypeDef
  • FlushRxPacket : ETH_DMAConfigTypeDef
  • FmcClockSelection : RCC_PeriphCLKInitTypeDef
  • ForwardRxErrorPacket : ETH_MACConfigTypeDef
  • ForwardRxUndersizedGoodPacket : ETH_MACConfigTypeDef
  • Fourth_Id : NAND_IDTypeDef
  • FrameEndCode : DCMI_CodesInitTypeDef
  • FrameFormat : FDCAN_InitTypeDef
  • FrameInit : __SAI_HandleTypeDef
  • FrameLength : SAI_FrameInitTypeDef
  • FrameStartCode : DCMI_CodesInitTypeDef
  • FreqErrorCapture : RCC_CRSSynchroInfoTypeDef
  • FreqErrorDirection : RCC_CRSSynchroInfoTypeDef
  • FSDefinition : SAI_FrameInitTypeDef
  • FSOffset : SAI_FrameInitTypeDef
  • FSPolarity : SAI_FrameInitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • k
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- g -

  • GapEnable : FDCAN_TT_ConfigTypeDef
  • GapFinished : FDCAN_TTOperationStatusTypeDef
  • GapStarted : FDCAN_TTOperationStatusTypeDef
  • GeneralCallMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • GeneratingPolynomial : CRC_InitTypeDef
  • GiantPacketSizeLimit : ETH_MACConfigTypeDef
  • GiantPacketSizeLimitControl : ETH_MACConfigTypeDef
  • GlobalTimeFilter : FDCAN_TT_ConfigTypeDef
  • GlobalUnicast : ETH_PowerDownConfigTypeDef
  • Green : DMA2D_ColorTypeDef , LTDC_ColorTypeDef
  • gState : SMARTCARD_HandleTypeDef , UART_HandleTypeDef , ETH_HandleTypeDef , CEC_HandleTypeDef , IRDA_HandleTypeDef
  • GTimeDiscPending : FDCAN_TTOperationStatusTypeDef
  • GTimeQuality : FDCAN_TTOperationStatusTypeDef
  • GuardTime : SMARTCARD_InitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • k
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- h -

  • HachOrPerfectFilter : ETH_MACFilterConfigTypeDef
  • HalfModeEnable : HRTIM_TimerCfgTypeDef
  • HashBuffSize : HASH_HandleTypeDef
  • HashInCount : HASH_HandleTypeDef
  • HashITCounter : HASH_HandleTypeDef
  • HashKeyCount : HASH_HandleTypeDef
  • HashMulticast : ETH_MACFilterConfigTypeDef
  • HashUnicast : ETH_MACFilterConfigTypeDef
  • hc : HCD_HandleTypeDef
  • hdma : TIM_HandleTypeDef
  • hdmaCsRx : SPDIFRX_HandleTypeDef
  • hdmaDrRx : SPDIFRX_HandleTypeDef
  • hdmain : CRYP_HandleTypeDef , HASH_HandleTypeDef , JPEG_HandleTypeDef
  • hdmaInj : DFSDM_Filter_HandleTypeDef
  • hdmaMaster : __HRTIM_HandleTypeDef
  • hdmaout : CRYP_HandleTypeDef , JPEG_HandleTypeDef
  • hdmaReg : DFSDM_Filter_HandleTypeDef
  • hdmarx : __I2C_HandleTypeDef , __I2S_HandleTypeDef , IRDA_HandleTypeDef , __SAI_HandleTypeDef , SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , SWPMI_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef
  • hdmaTimerA : __HRTIM_HandleTypeDef
  • hdmaTimerB : __HRTIM_HandleTypeDef
  • hdmaTimerC : __HRTIM_HandleTypeDef
  • hdmaTimerD : __HRTIM_HandleTypeDef
  • hdmaTimerE : __HRTIM_HandleTypeDef
  • hdmatx : SMARTCARD_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , IRDA_HandleTypeDef , __SAI_HandleTypeDef , __SPI_HandleTypeDef , SWPMI_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef
  • Header : CRYP_ConfigTypeDef
  • HeaderSize : CRYP_ConfigTypeDef
  • HeaderType : ETH_RxPacketInfo
  • HighBreakSignal : DFSDM_Filter_AwdParamTypeDef
  • HighThreshold : ADC_AnalogWDGConfTypeDef , DFSDM_Filter_AwdParamTypeDef
  • hmdma : SDRAM_HandleTypeDef , QSPI_HandleTypeDef , SRAM_HandleTypeDef
  • HorizontalSync : LTDC_InitTypeDef
  • HourFormat : RTC_InitTypeDef
  • Hours : RTC_TimeTypeDef
  • Hrtim1ClockSelection : RCC_PeriphCLKInitTypeDef
  • HRTIMInterruptResquests : HRTIM_InitTypeDef
  • HSEState : RCC_OscInitTypeDef
  • HSI48CalibrationValue : RCC_CRSInitTypeDef , RCC_CRSSynchroInfoTypeDef
  • HSI48State : RCC_OscInitTypeDef
  • HSICalibrationValue : RCC_OscInitTypeDef
  • HSIState : RCC_OscInitTypeDef
  • HSPolarity : DCMI_InitTypeDef , LTDC_InitTypeDef
  • HuffmanCode : JPEG_AC_HuffCodeTableTypeDef , JPEG_DC_HuffCodeTableTypeDef
  • HuffVal : JPEG_ACHuffTableTypeDef , JPEG_DCHuffTableTypeDef
  • HwFlowCtl : UART_InitTypeDef
  • Hysteresis : COMP_InitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • x
  • y
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- i -

  • I2c1ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c2ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c3ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c4ClockSelection : RCC_PeriphCLKInitTypeDef
  • IC1Filter : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Polarity : TIM_HallSensor_InitTypeDef , TIM_Encoder_InitTypeDef
  • IC1Prescaler : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Selection : TIM_Encoder_InitTypeDef
  • IC2Filter : TIM_Encoder_InitTypeDef
  • IC2Polarity : TIM_Encoder_InitTypeDef
  • IC2Prescaler : TIM_Encoder_InitTypeDef
  • IC2Selection : TIM_Encoder_InitTypeDef
  • ICFilter : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • ICPolarity : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • ICPrescaler : TIM_IC_InitTypeDef
  • ICSelection : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • Identifier : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • IdleDuration : HRTIM_BurstModeCfgTypeDef
  • IdleLevel : HRTIM_SimpleOCChannelCfgTypeDef , HRTIM_SimplePWMChannelCfgTypeDef , HRTIM_OutputCfgTypeDef
  • IdleMode : HRTIM_OutputCfgTypeDef
  • IdType : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef , FDCAN_FilterTypeDef
  • IFCR : DMA_Base_Registers
  • ImageHeight : JPEG_ConfTypeDef , LTDC_LayerCfgTypeDef
  • ImageQuality : JPEG_ConfTypeDef
  • ImageWidth : JPEG_ConfTypeDef , LTDC_LayerCfgTypeDef
  • IN_ep : PCD_HandleTypeDef
  • InDataLength : JPEG_HandleTypeDef
  • Init : MDIOS_HandleTypeDef , MDMA_LinkNodeConfTypeDef , __MDMA_HandleTypeDef , MMC_HandleTypeDef , NAND_HandleTypeDef , NOR_HandleTypeDef , OPAMP_HandleTypeDef , PCD_HandleTypeDef , QSPI_HandleTypeDef , RNG_HandleTypeDef , RTC_HandleTypeDef , __SAI_HandleTypeDef , SD_HandleTypeDef , SDRAM_HandleTypeDef , SMARTCARD_HandleTypeDef , SMBUS_HandleTypeDef , SPDIFRX_HandleTypeDef , __SPI_HandleTypeDef , SRAM_HandleTypeDef , SWPMI_HandleTypeDef , TIM_HandleTypeDef , UART_HandleTypeDef , ADC_HandleTypeDef , USART_HandleTypeDef , WWDG_HandleTypeDef , CEC_HandleTypeDef , COMP_HandleTypeDef , CRC_HandleTypeDef , CRYP_HandleTypeDef , DCMI_HandleTypeDef , DFSDM_Channel_HandleTypeDef , DFSDM_Filter_HandleTypeDef , __DMA_HandleTypeDef , __DMA2D_HandleTypeDef , ETH_HandleTypeDef , FDCAN_HandleTypeDef , HASH_HandleTypeDef , HCD_HandleTypeDef , __HRTIM_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , IRDA_HandleTypeDef , IWDG_HandleTypeDef , LPTIM_HandleTypeDef , LTDC_HandleTypeDef
  • InitRefTrigOffset : FDCAN_TT_ConfigTypeDef
  • InitValue : CRC_InitTypeDef
  • InjConvRemaining : DFSDM_Filter_HandleTypeDef
  • InjecOversampling : ADC_InjectionConfTypeDef
  • InjecOversamplingMode : ADC_InjectionConfTypeDef
  • InjectedChannel : ADC_InjectionConfTypeDef
  • InjectedChannelsNbr : DFSDM_Filter_HandleTypeDef
  • InjectedDiscontinuousConvMode : ADC_InjectionConfTypeDef
  • InjectedLeftBitShift : ADC_InjectionConfTypeDef
  • InjectedNbrOfConversion : ADC_InjectionConfTypeDef
  • InjectedOffset : ADC_InjectionConfTypeDef
  • InjectedOffsetNumber : ADC_InjectionConfTypeDef
  • InjectedOffsetRightShift : ADC_InjectionConfTypeDef
  • InjectedOffsetSignedSaturation : ADC_InjectionConfTypeDef
  • InjectedParam : DFSDM_Filter_InitTypeDef
  • InjectedRank : ADC_InjectionConfTypeDef
  • InjectedSamplingTime : ADC_InjectionConfTypeDef
  • InjectedScanMode : DFSDM_Filter_HandleTypeDef
  • InjectedSingleDiff : ADC_InjectionConfTypeDef
  • InjectedTrigger : DFSDM_Filter_HandleTypeDef
  • InjectionConfig : ADC_HandleTypeDef
  • InnerVlanCtrl : ETH_TxPacketConfig
  • InnerVlanTag : ETH_TxPacketConfig
  • InnerVLANTag : ETH_RxVLANConfigTypeDef
  • InnerVlanTag : ETH_RxPacketInfo
  • InnerVLANTagInStatus : ETH_RxVLANConfigTypeDef
  • Input : DFSDM_Channel_InitTypeDef
  • Input1Source : LPTIM_InitTypeDef
  • Input2Source : LPTIM_InitTypeDef
  • InputAlpha : DMA2D_LayerCfgTypeDef
  • InputColorMode : DMA2D_LayerCfgTypeDef
  • InputDataFormat : CRC_HandleTypeDef
  • InputDataInversionMode : CRC_InitTypeDef
  • InputOffset : DMA2D_LayerCfgTypeDef
  • InputSelection : SPDIFRX_InitTypeDef
  • InputTrigger : TIM_SlaveConfigTypeDef
  • Instance : IRDA_HandleTypeDef , SRAM_HandleTypeDef , FDCAN_HandleTypeDef , __SAI_HandleTypeDef , __DMA_HandleTypeDef , DCMI_HandleTypeDef , DAC_HandleTypeDef , NAND_HandleTypeDef , HCD_HandleTypeDef , SDRAM_HandleTypeDef , MDIOS_HandleTypeDef , OPAMP_HandleTypeDef , CRYP_HandleTypeDef , DFSDM_Filter_HandleTypeDef , __MDMA_HandleTypeDef , NOR_HandleTypeDef , __I2S_HandleTypeDef , __HRTIM_HandleTypeDef , JPEG_HandleTypeDef , SD_HandleTypeDef , MMC_HandleTypeDef , __I2C_HandleTypeDef , IWDG_HandleTypeDef , CRC_HandleTypeDef , COMP_HandleTypeDef , SMARTCARD_HandleTypeDef , ETH_HandleTypeDef , DFSDM_Channel_HandleTypeDef , WWDG_HandleTypeDef , RNG_HandleTypeDef , SMBUS_HandleTypeDef , __SPI_HandleTypeDef , SWPMI_HandleTypeDef , __DMA2D_HandleTypeDef , CEC_HandleTypeDef , ADC_HandleTypeDef , TIM_HandleTypeDef , LPTIM_HandleTypeDef , RTC_HandleTypeDef , UART_HandleTypeDef , PCD_HandleTypeDef , SPDIFRX_HandleTypeDef , QSPI_HandleTypeDef , USART_HandleTypeDef , LTDC_HandleTypeDef
  • Instruction : QSPI_CommandTypeDef
  • InstructionMode : QSPI_CommandTypeDef
  • InterPacketGapVal : ETH_MACConfigTypeDef
  • Interrupt : RTC_TamperTypeDef
  • InterruptRequests : HRTIM_TimerCfgTypeDef , HRTIM_TimerParamTypeDef
  • InterruptServiceRoutine : __SAI_HandleTypeDef
  • Interval : QSPI_AutoPollingTypeDef
  • IntOversampling : DFSDM_Filter_FilterParamTypeDef
  • InvertingInput : OPAMP_InitTypeDef , COMP_InitTypeDef
  • IOSwap : I2S_InitTypeDef , SPI_InitTypeDef
  • Ip4DestAddr : ETH_L3FilterConfigTypeDef
  • Ip4SrcAddr : ETH_L3FilterConfigTypeDef
  • Ip6Addr : ETH_L3FilterConfigTypeDef
  • IsBufferable : MPU_Region_InitTypeDef
  • IsCacheable : MPU_Region_InitTypeDef
  • IsCalibrationMsg : FDCAN_FilterTypeDef
  • IsFilterMatchingFrame : FDCAN_RxHeaderTypeDef
  • ISR : DMA_Base_Registers
  • IsShareable : MPU_Region_InitTypeDef
  • ItMode : ETH_RxDescListTypeDef
  • ITMode : ADC_AnalogWDGConfTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • a
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  • x
  • y
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- j -

  • Jabber : ETH_MACConfigTypeDef
  • JpegInCount : JPEG_HandleTypeDef
  • JPEGMode : DCMI_InitTypeDef
  • JpegOutCount : JPEG_HandleTypeDef
  • JumboPacket : ETH_MACConfigTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • Variables
  • a
  • b
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- k -

  • KeySize : CRYP_ConfigTypeDef , HASH_InitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- l -

  • L3FilterStatus : ETH_RxPacketInfo
  • L4FilterStatus : ETH_RxPacketInfo
  • LastErrorCode : FDCAN_ProtocolStatusTypeDef
  • LastLinkedListNodeAddress : __MDMA_HandleTypeDef
  • Latch : HRTIM_TimerEventFilteringCfgTypeDef
  • LayerCfg : __DMA2D_HandleTypeDef , LTDC_HandleTypeDef
  • LBPEErrorBitGen : CEC_InitTypeDef
  • LeftBitShift : ADC_InitTypeDef
  • LeftDelay : SAIEx_PdmMicDelayParamTypeDef
  • len : __ETH_BufferTypeDef
  • Length : ETH_TxPacketConfig
  • LineEndCode : DCMI_CodesInitTypeDef
  • LineSelectMode : DCMI_InitTypeDef
  • LineSelectStart : DCMI_InitTypeDef
  • LineStartCode : DCMI_CodesInitTypeDef
  • LinkedListNodeCounter : __MDMA_HandleTypeDef
  • ListenMode : CEC_InitTypeDef
  • Lock : HCD_HandleTypeDef , __HRTIM_HandleTypeDef , HRTIM_FaultCfgTypeDef , USART_HandleTypeDef , UART_HandleTypeDef , __I2C_HandleTypeDef , SWPMI_HandleTypeDef , SRAM_HandleTypeDef , __I2S_HandleTypeDef , IRDA_HandleTypeDef , SMBUS_HandleTypeDef , SMARTCARD_HandleTypeDef , SDRAM_HandleTypeDef , ADC_HandleTypeDef , __SAI_HandleTypeDef , RTC_HandleTypeDef , JPEG_HandleTypeDef , LPTIM_HandleTypeDef , PCD_HandleTypeDef , OPAMP_HandleTypeDef , NOR_HandleTypeDef , CEC_HandleTypeDef , MMC_HandleTypeDef , LTDC_HandleTypeDef , MDIOS_HandleTypeDef , COMP_HandleTypeDef , __MDMA_HandleTypeDef , CRC_HandleTypeDef , NAND_HandleTypeDef , CRYP_HandleTypeDef , DAC_HandleTypeDef , QSPI_HandleTypeDef , RNG_HandleTypeDef , DCMI_HandleTypeDef , HASH_HandleTypeDef , TIM_HandleTypeDef , FDCAN_HandleTypeDef , __SPI_HandleTypeDef , __DMA_HandleTypeDef , SD_HandleTypeDef , __DMA2D_HandleTypeDef , ETH_HandleTypeDef , SPDIFRX_HandleTypeDef , FLASH_ProcessTypeDef
  • LockLevel : TIM_BreakDeadTimeConfigTypeDef
  • LogBlockNbr : HAL_MMC_CardInfoTypeDef , HAL_SD_CardInfoTypeDef
  • LogBlockSize : HAL_MMC_CardInfoTypeDef , HAL_SD_CardInfoTypeDef
  • LoopbackMode : ETH_MACConfigTypeDef
  • LowBreakSignal : DFSDM_Filter_AwdParamTypeDef
  • LowPowerAutoWait : ADC_InitTypeDef
  • LowThreshold : ADC_AnalogWDGConfTypeDef , DFSDM_Filter_AwdParamTypeDef
  • lpm_active : PCD_HandleTypeDef
  • LPM_State : PCD_HandleTypeDef
  • Lptim1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lptim2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lptim3ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lptim4ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lptim5ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lpuart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • LSEState : RCC_OscInitTypeDef
  • LSIState : RCC_OscInitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • a
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  • y
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- m -

  • MACAddr : ETH_InitTypeDef
  • MACErrorCode : ETH_HandleTypeDef
  • MacFilterStatus : ETH_RxPacketInfo
  • MACLPIEvent : ETH_HandleTypeDef
  • MACWakeUpEvent : ETH_HandleTypeDef
  • MagicPacket : ETH_PowerDownConfigTypeDef
  • Maker_Id : NAND_IDTypeDef
  • ManDeflECC : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • ManufactDate : HAL_MMC_CardCIDTypedef , HAL_SD_CardCIDTypedef
  • Manufacturer_Code : NOR_IDTypeDef
  • ManufacturerID : HAL_MMC_CardCIDTypedef , HAL_SD_CardCIDTypedef
  • Mask : QSPI_AutoPollingTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , IRDA_HandleTypeDef
  • MaskFlag : RTC_TamperTypeDef
  • MasterInterDataIdleness : SPI_InitTypeDef
  • MasterKeepIOState : I2S_InitTypeDef , SPI_InitTypeDef
  • MasterOutputTrigger : TIM_MasterConfigTypeDef
  • MasterOutputTrigger2 : TIM_MasterConfigTypeDef
  • MasterPriority : FDCAN_TTOperationStatusTypeDef
  • MasterReceiverAutoSusp : SPI_InitTypeDef
  • MasterSlaveMode : TIM_MasterConfigTypeDef
  • MasterSSIdleness : SPI_InitTypeDef
  • MasterState : FDCAN_TTOperationStatusTypeDef
  • Match : QSPI_AutoPollingTypeDef
  • MatchMode : QSPI_AutoPollingTypeDef
  • MaxBusClkFrec : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • MaximumSegmentSize : ETH_DMAConfigTypeDef
  • MaxRdCurrentVDDMax : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • MaxRdCurrentVDDMin : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • MaxSegmentSize : ETH_TxPacketConfig
  • MaxWrBlockLen : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • MaxWrCurrentVDDMax : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • MaxWrCurrentVDDMin : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • Mckdiv : SAI_InitTypeDef
  • MckOverSampling : SAI_InitTypeDef
  • MCLKOutput : I2S_InitTypeDef
  • MediaInterface : ETH_InitTypeDef
  • MemBurst : DMA_InitTypeDef
  • MemDataAlignment : DMA_InitTypeDef
  • MemInc : DMA_InitTypeDef
  • MessageIndex : FDCAN_HpMsgStatusTypeDef
  • MessageMarker : FDCAN_TxEventFifoTypeDef , FDCAN_TxHeaderTypeDef
  • MessageRAMOffset : FDCAN_InitTypeDef
  • MessageStorage : FDCAN_HpMsgStatusTypeDef
  • MicPair : SAIEx_PdmMicDelayParamTypeDef
  • MicPairsNbr : SAI_PdmInitTypeDef
  • MinOscClkPeriods : FDCAN_ClkCalUnitTypeDef
  • Minutes : RTC_TimeTypeDef
  • MmcCard : MMC_HandleTypeDef
  • Mode : ADC_MultiModeTypeDef , I2S_InitTypeDef , COMP_InitTypeDef , PWR_PVDTypeDef , HRTIM_SimpleOCChannelCfgTypeDef , USART_InitTypeDef , SMARTCARD_InitTypeDef , __I2C_HandleTypeDef , IRDA_InitTypeDef , DMA_InitTypeDef , UART_InitTypeDef , HRTIM_BurstModeCfgTypeDef , SPI_InitTypeDef , GPIO_InitTypeDef , DMA2D_InitTypeDef , HRTIM_TimeBaseCfgTypeDef , PWREx_AVDTypeDef , OPAMP_InitTypeDef , FDCAN_InitTypeDef
  • MonoStereoMode : SAI_InitTypeDef
  • Month : RTC_DateTypeDef
  • MSBFirst : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • msgRam : FDCAN_HandleTypeDef
  • Multiplexer : DFSDM_Channel_InputTypeDef
  • mutecallback : __SAI_HandleTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • Variables
  • a
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- n -

  • NACKEnable : SMARTCARD_InitTypeDef
  • NbData : QSPI_CommandTypeDef
  • NbrOfConversion : ADC_InitTypeDef
  • NbrOfDiscConversion : ADC_InitTypeDef
  • NbSectors : FLASH_EraseInitTypeDef
  • NbSectorsToErase : FLASH_ProcessTypeDef
  • next : __ETH_BufferTypeDef
  • NoDivider : SAI_InitTypeDef
  • NoErase : RTC_TamperTypeDef
  • NominalPrescaler : FDCAN_InitTypeDef
  • NominalSyncJumpWidth : FDCAN_InitTypeDef
  • NominalTimeSeg1 : FDCAN_InitTypeDef
  • NominalTimeSeg2 : FDCAN_InitTypeDef
  • NonInvertingInput : OPAMP_InitTypeDef , COMP_InitTypeDef
  • NoStretchMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • NSAC : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • NSS : SPI_InitTypeDef , USART_InitTypeDef
  • NSSPMode : SPI_InitTypeDef
  • NSSPolarity : SPI_InitTypeDef
  • Number : MPU_Region_InitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • Variables
  • a
  • b
  • c
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  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- o -

  • OCFastMode : TIM_OC_InitTypeDef
  • OCIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCMode : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCNIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCNPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OEM_AppliID : HAL_MMC_CardCIDTypedef , HAL_SD_CardCIDTypedef
  • Offset : ADC_ChannelConfTypeDef , DFSDM_Channel_InitTypeDef
  • OffsetNumber : ADC_ChannelConfTypeDef
  • OffsetRightShift : ADC_ChannelConfTypeDef
  • OffsetSignedSaturation : ADC_ChannelConfTypeDef
  • OffStateIDLEMode : TIM_BreakDeadTimeConfigTypeDef
  • OffStateRunMode : TIM_BreakDeadTimeConfigTypeDef
  • OneBitSampling : SMARTCARD_InitTypeDef , UART_InitTypeDef
  • OperationMode : FDCAN_TT_ConfigTypeDef
  • OptionType : FLASH_OBProgramInitTypeDef
  • OscillatorType : RCC_OscInitTypeDef
  • OUT_ep : PCD_HandleTypeDef
  • OutDataLength : JPEG_HandleTypeDef
  • OutPut : RTC_InitTypeDef
  • OutputClock : DFSDM_Channel_InitTypeDef
  • OutputDataInversionMode : CRC_InitTypeDef
  • OutputDrive : SAI_InitTypeDef
  • OutputIdleLevel : HRTIM_SimpleOnePulseChannelCfgTypeDef
  • OutputOffset : DMA2D_InitTypeDef
  • OutputPol : COMP_InitTypeDef
  • OutputPolarity : LPTIM_InitTypeDef
  • OutPutPolarity : RTC_InitTypeDef
  • OutputPolarity : HRTIM_SimpleOnePulseChannelCfgTypeDef
  • OutPutRemap : RTC_InitTypeDef
  • OutPutType : RTC_InitTypeDef
  • Overrun : ADC_InitTypeDef
  • OverrunDisable : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • Oversampling : DFSDM_Channel_AwdTypeDef , DFSDM_Filter_FilterParamTypeDef
  • OverSampling : UART_InitTypeDef
  • Oversampling : ADC_InitTypeDef
  • OversamplingMode : ADC_InitTypeDef
  • OversamplingStopReset : ADC_OversamplingTypeDef
  • OwnAddress : CEC_InitTypeDef
  • OwnAddress1 : SMBUS_InitTypeDef , I2C_InitTypeDef
  • OwnAddress2 : I2C_InitTypeDef , SMBUS_InitTypeDef
  • OwnAddress2Masks : SMBUS_InitTypeDef , I2C_InitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
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  • u
  • v
  • w
  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- p -

  • PacketErrorCheckMode : SMBUS_InitTypeDef
  • Page : NAND_AddressTypeDef
  • PageSize : NAND_DeviceConfigTypeDef
  • Parent : __DMA_HandleTypeDef , __MDMA_HandleTypeDef
  • Parity : UART_InitTypeDef , USART_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef
  • ParityErrorMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • PartBlockRead : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • PassAllMulticast : ETH_MACFilterConfigTypeDef
  • PauseLowThreshold : ETH_MACConfigTypeDef
  • PauseTime : ETH_MACConfigTypeDef
  • PayloadLen : ETH_TxPacketConfig
  • PayloadType : ETH_RxPacketInfo
  • PBLx8Mode : ETH_DMAConfigTypeDef
  • pBuffPtr : DCMI_HandleTypeDef , __I2C_HandleTypeDef , __SAI_HandleTypeDef , SMBUS_HandleTypeDef
  • PCKPolarity : DCMI_InitTypeDef
  • pCLUT : DMA2D_CLUTCfgTypeDef
  • PCPolarity : LTDC_InitTypeDef
  • PCROPConfig : FLASH_OBProgramInitTypeDef
  • PCROPEndAddr : FLASH_OBProgramInitTypeDef
  • PCROPStartAddr : FLASH_OBProgramInitTypeDef
  • pCrypInBuffPtr : CRYP_HandleTypeDef
  • pCrypOutBuffPtr : CRYP_HandleTypeDef
  • pCsBuffPtr : SPDIFRX_HandleTypeDef
  • pData : HCD_HandleTypeDef , PCD_HandleTypeDef
  • PdmInit : SAI_InitTypeDef
  • PerformanceMove : HAL_SD_CardStatusTypedef
  • Period : HRTIM_TimeBaseCfgTypeDef , HRTIM_BurstModeCfgTypeDef , TIM_Base_InitTypeDef
  • PeriphBurst : DMA_InitTypeDef
  • PeriphClockSelection : RCC_PeriphCLKInitTypeDef
  • PeriphDataAlignment : DMA_InitTypeDef
  • PeripheralMode : SMBUS_InitTypeDef
  • PeriphInc : DMA_InitTypeDef
  • PermWrProtect : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • PgaConnect : OPAMP_InitTypeDef
  • PgaGain : OPAMP_InitTypeDef
  • Phase : CRYP_HandleTypeDef , HASH_HandleTypeDef
  • PhaseLock : FDCAN_TTOperationStatusTypeDef
  • pHashInBuffPtr : HASH_HandleTypeDef
  • pHashKeyBuffPtr : HASH_HandleTypeDef
  • pHashMsgBuffPtr : HASH_HandleTypeDef
  • pHashOutBuffPtr : HASH_HandleTypeDef
  • Pin : GPIO_InitTypeDef
  • pInitVect : CRYP_ConfigTypeDef
  • PinPolarity : PWREx_WakeupPinTypeDef
  • PinPull : PWREx_WakeupPinTypeDef
  • Pins : DFSDM_Channel_InputTypeDef
  • PixelFormat : LTDC_LayerCfgTypeDef
  • pJpegInBuffPtr : JPEG_HandleTypeDef
  • pJpegOutBuffPtr : JPEG_HandleTypeDef
  • pKey : CRYP_ConfigTypeDef , HASH_InitTypeDef
  • Plane : NAND_AddressTypeDef
  • PlaneNbr : NAND_DeviceConfigTypeDef
  • PlaneSize : NAND_DeviceConfigTypeDef
  • PLL : RCC_OscInitTypeDef
  • PLL1_P_Frequency : PLL1_ClocksTypeDef
  • PLL1_Q_Frequency : PLL1_ClocksTypeDef
  • PLL1_R_Frequency : PLL1_ClocksTypeDef
  • PLL2 : RCC_PeriphCLKInitTypeDef
  • PLL2_P_Frequency : PLL2_ClocksTypeDef
  • PLL2_Q_Frequency : PLL2_ClocksTypeDef
  • PLL2_R_Frequency : PLL2_ClocksTypeDef
  • PLL2FRACN : RCC_PLL2InitTypeDef
  • PLL2M : RCC_PLL2InitTypeDef
  • PLL2N : RCC_PLL2InitTypeDef
  • PLL2P : RCC_PLL2InitTypeDef
  • PLL2Q : RCC_PLL2InitTypeDef
  • PLL2R : RCC_PLL2InitTypeDef
  • PLL2RGE : RCC_PLL2InitTypeDef
  • PLL2VCOSEL : RCC_PLL2InitTypeDef
  • PLL3 : RCC_PeriphCLKInitTypeDef
  • PLL3_P_Frequency : PLL3_ClocksTypeDef
  • PLL3_Q_Frequency : PLL3_ClocksTypeDef
  • PLL3_R_Frequency : PLL3_ClocksTypeDef
  • PLL3FRACN : RCC_PLL3InitTypeDef
  • PLL3M : RCC_PLL3InitTypeDef
  • PLL3N : RCC_PLL3InitTypeDef
  • PLL3P : RCC_PLL3InitTypeDef
  • PLL3Q : RCC_PLL3InitTypeDef
  • PLL3R : RCC_PLL3InitTypeDef
  • PLL3RGE : RCC_PLL3InitTypeDef
  • PLL3VCOSEL : RCC_PLL3InitTypeDef
  • PLLFRACN : RCC_PLLInitTypeDef
  • PLLM : RCC_PLLInitTypeDef
  • PLLN : RCC_PLLInitTypeDef
  • PLLP : RCC_PLLInitTypeDef
  • PLLQ : RCC_PLLInitTypeDef
  • PLLR : RCC_PLLInitTypeDef
  • PLLRGE : RCC_PLLInitTypeDef
  • PLLSource : RCC_PLLInitTypeDef
  • PLLState : RCC_PLLInitTypeDef
  • PLLVCOSEL : RCC_PLLInitTypeDef
  • Polarity : HAL_DMA_MuxRequestGeneratorConfigTypeDef , HRTIM_EventCfgTypeDef , HRTIM_SimpleOCChannelCfgTypeDef , HRTIM_SimplePWMChannelCfgTypeDef , HRTIM_OutputCfgTypeDef , HRTIM_FaultCfgTypeDef , LPTIM_ULPClockConfigTypeDef , RCC_CRSInitTypeDef , TIMEx_BreakInputConfigTypeDef
  • PortAddress : MDIOS_InitTypeDef
  • PostRequestMaskAddress : MDMA_LinkNodeConfTypeDef
  • PostRequestMaskData : MDMA_LinkNodeConfTypeDef
  • PowerMode : IRDA_InitTypeDef , OPAMP_InitTypeDef
  • PreambleCheck : MDIOS_InitTypeDef
  • PreambleLength : ETH_MACConfigTypeDef
  • PreambleTypeMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • PrechargeDuration : RTC_TamperTypeDef
  • PreloadEnable : HRTIM_BurstModeCfgTypeDef , HRTIM_TimerCfgTypeDef
  • Prescaler : RCC_CRSInitTypeDef , HRTIM_DeadTimeCfgTypeDef , HRTIM_BurstModeCfgTypeDef , IRDA_InitTypeDef , LPTIM_ClockConfigTypeDef , UART_InitTypeDef , WWDG_InitTypeDef , USART_InitTypeDef , SMARTCARD_InitTypeDef , TIM_Base_InitTypeDef , IWDG_InitTypeDef
  • PrescalerRatio : HRTIM_TimeBaseCfgTypeDef
  • PreviousState : __I2C_HandleTypeDef , SMBUS_HandleTypeDef
  • Priority : DMA_InitTypeDef , MDMA_InitTypeDef
  • ProcedureOnGoing : FLASH_ProcessTypeDef
  • ProdName1 : HAL_SD_CardCIDTypedef , HAL_MMC_CardCIDTypedef
  • ProdName2 : HAL_SD_CardCIDTypedef , HAL_MMC_CardCIDTypedef
  • ProdRev : HAL_SD_CardCIDTypedef , HAL_MMC_CardCIDTypedef
  • ProdSN : HAL_SD_CardCIDTypedef , HAL_MMC_CardCIDTypedef
  • ProgrammableWatchdog : ETH_MACConfigTypeDef
  • PromiscuousMode : ETH_MACFilterConfigTypeDef
  • ProtectedAreaSize : HAL_SD_CardStatusTypedef
  • Protocol : ETH_L4FilterConfigTypeDef , SAI_InitTypeDef , ETH_L3FilterConfigTypeDef
  • ProtocolException : FDCAN_ProtocolStatusTypeDef , FDCAN_InitTypeDef
  • pRxBuffPtr : MMC_HandleTypeDef , __SPI_HandleTypeDef , __I2S_HandleTypeDef , QSPI_HandleTypeDef , SMARTCARD_HandleTypeDef , USART_HandleTypeDef , IRDA_HandleTypeDef , SPDIFRX_HandleTypeDef , SWPMI_HandleTypeDef , UART_HandleTypeDef , SD_HandleTypeDef
  • pTxBuffPtr : SWPMI_HandleTypeDef , UART_HandleTypeDef , __SPI_HandleTypeDef , IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , __I2S_HandleTypeDef , USART_HandleTypeDef , MMC_HandleTypeDef , CEC_HandleTypeDef , QSPI_HandleTypeDef , SD_HandleTypeDef
  • Pull : GPIO_InitTypeDef
  • Pulse : TIM_OnePulse_InitTypeDef , HRTIM_SimpleOCChannelCfgTypeDef , HRTIM_SimplePWMChannelCfgTypeDef , TIM_OC_InitTypeDef , HRTIM_SimpleOnePulseChannelCfgTypeDef
  • PushPull : HRTIM_TimerCfgTypeDef
  • PVDLevel : PWR_PVDTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- q -

  • QspiClockSelection : RCC_PeriphCLKInitTypeDef
  • QuantTable0 : JPEG_HandleTypeDef
  • QuantTable1 : JPEG_HandleTypeDef
  • QuantTable2 : JPEG_HandleTypeDef
  • QuantTable3 : JPEG_HandleTypeDef
  • QueueInjectedContext : ADC_InjectionConfTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- r -

  • RandomNumber : RNG_HandleTypeDef
  • Rank : ADC_ChannelConfTypeDef
  • Ratio : ADC_InjOversamplingTypeDef , ADC_OversamplingTypeDef
  • RdBlockLen : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • RdBlockMisalign : HAL_SD_CardCSDTypedef , HAL_MMC_CardCSDTypeDef
  • RDPLevel : FLASH_OBProgramInitTypeDef
  • RebuildINCRxBurst : ETH_DMAConfigTypeDef
  • ReceiveAllMode : ETH_MACFilterConfigTypeDef
  • ReceiveFlowControl : ETH_MACConfigTypeDef
  • ReceiveOwn : ETH_MACConfigTypeDef
  • ReceiveQueueMode : ETH_MACConfigTypeDef
  • Red : LTDC_ColorTypeDef , DMA2D_ColorTypeDef
  • RedBlueSwap : DMA2D_InitTypeDef , DMA2D_LayerCfgTypeDef
  • RefTrigOffset : FDCAN_TTOperationStatusTypeDef
  • RegularContMode : DFSDM_Filter_HandleTypeDef
  • RegularParam : DFSDM_Filter_InitTypeDef
  • RegularTrigger : DFSDM_Filter_HandleTypeDef
  • RelCardAdd : HAL_MMC_CardInfoTypeDef , HAL_SD_CardInfoTypeDef
  • Reload : IWDG_InitTypeDef
  • ReloadValue : RCC_CRSInitTypeDef , RCC_CRSSynchroInfoTypeDef
  • RepeatFactor : FDCAN_TriggerTypeDef
  • RepetitionCounter : HRTIM_TimeBaseCfgTypeDef , TIM_Base_InitTypeDef
  • RepetitionUpdate : HRTIM_TimerCfgTypeDef
  • Request : DMA_InitTypeDef , MDMA_InitTypeDef
  • RequestNumber : HAL_DMA_MuxSyncConfigTypeDef , HAL_DMA_MuxRequestGeneratorConfigTypeDef
  • Reserved : LTDC_ColorTypeDef , MDMA_LinkNodeTypeDef
  • Reserved0 : DMA_Base_Registers
  • Reserved1 : HAL_MMC_CardCSDTypeDef , HAL_MMC_CardCIDTypedef , HAL_SD_CardCSDTypedef , HAL_SD_CardCIDTypedef
  • Reserved2 : HAL_MMC_CardCSDTypeDef , HAL_MMC_CardCIDTypedef , HAL_SD_CardCSDTypedef , HAL_SD_CardCIDTypedef
  • Reserved3 : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • Reserved4 : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • ResetOnSync : HRTIM_TimerCfgTypeDef
  • ResetSource : HRTIM_OutputCfgTypeDef
  • ResetTrigger : HRTIM_TimerCfgTypeDef
  • ResetUpdate : HRTIM_TimerCfgTypeDef
  • Resolution : ADC_InitTypeDef
  • Retries : SPDIFRX_InitTypeDef
  • RetryTransmission : ETH_MACConfigTypeDef
  • RightBitShift : ADC_OversamplingTypeDef , ADC_InjOversamplingTypeDef , DFSDM_Channel_InitTypeDef
  • RightDelay : SAIEx_PdmMicDelayParamTypeDef
  • RisingLock : HRTIM_DeadTimeCfgTypeDef
  • RisingSign : HRTIM_DeadTimeCfgTypeDef
  • RisingSignLock : HRTIM_DeadTimeCfgTypeDef
  • RisingValue : HRTIM_DeadTimeCfgTypeDef
  • RngClockSelection : RCC_PeriphCLKInitTypeDef
  • RTCClockSelection : RCC_PeriphCLKInitTypeDef
  • RxBRSflag : FDCAN_ProtocolStatusTypeDef
  • RxBuffer : CEC_InitTypeDef
  • RxBufferIndex : FDCAN_FilterTypeDef
  • RxBufferingMode : SWPMI_InitTypeDef
  • RxBufferSA : FDCAN_MsgRamAddressTypeDef
  • RxBufferSize : FDCAN_InitTypeDef
  • RxBuffersNbr : FDCAN_InitTypeDef
  • RxBuffLen : ETH_InitTypeDef
  • RxCRCInitializationPattern : SPI_InitTypeDef
  • RxDesc : ETH_RxDescListTypeDef , ETH_InitTypeDef
  • RxDescList : ETH_HandleTypeDef
  • RxDMABurstLength : ETH_DMAConfigTypeDef
  • RxErrorCnt : FDCAN_ErrorCountersTypeDef
  • RxErrorPassive : FDCAN_ErrorCountersTypeDef
  • RxESIflag : FDCAN_ProtocolStatusTypeDef
  • RxFDFflag : FDCAN_ProtocolStatusTypeDef
  • RxFifo0ElmtSize : FDCAN_InitTypeDef
  • RxFifo0ElmtsNbr : FDCAN_InitTypeDef
  • RxFIFO0SA : FDCAN_MsgRamAddressTypeDef
  • RxFifo1ElmtSize : FDCAN_InitTypeDef
  • RxFifo1ElmtsNbr : FDCAN_InitTypeDef
  • RxFIFO1SA : FDCAN_MsgRamAddressTypeDef
  • RXFIFOThreshold : USART_InitTypeDef , UART_InitTypeDef , SMARTCARD_InitTypeDef
  • RxFrameType : FDCAN_RxHeaderTypeDef
  • RxISR : __SPI_HandleTypeDef , __I2S_HandleTypeDef
  • RxPinLevelInvert : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • RxState : ETH_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef , IRDA_HandleTypeDef , CEC_HandleTypeDef
  • RxTimestamp : FDCAN_RxHeaderTypeDef
  • RxXferCount : SWPMI_HandleTypeDef , QSPI_HandleTypeDef , __SPI_HandleTypeDef , IRDA_HandleTypeDef , __I2S_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , SPDIFRX_HandleTypeDef
  • RxXferSize : QSPI_HandleTypeDef , USART_HandleTypeDef , SPDIFRX_HandleTypeDef , MMC_HandleTypeDef , SMARTCARD_HandleTypeDef , IRDA_HandleTypeDef , __SPI_HandleTypeDef , SD_HandleTypeDef , SWPMI_HandleTypeDef , __I2S_HandleTypeDef , UART_HandleTypeDef , CEC_HandleTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
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  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- s -

  • Sai1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Sai2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Sai3ClockSelection : RCC_PeriphCLKInitTypeDef
  • Sai4AClockSelection : RCC_PeriphCLKInitTypeDef
  • Sai4BClockSelection : RCC_PeriphCLKInitTypeDef
  • SampleShifting : QSPI_InitTypeDef
  • SampleTime : LPTIM_TriggerConfigTypeDef , LPTIM_ULPClockConfigTypeDef
  • SamplingFrequency : RTC_TamperTypeDef
  • SamplingTime : ADC_ChannelConfTypeDef
  • ScanConvMode : ADC_InitTypeDef
  • ScanMode : DFSDM_Filter_InjectedParamTypeDef
  • SdCard : SD_HandleTypeDef
  • SdmmcClockSelection : RCC_PeriphCLKInitTypeDef
  • SecondFraction : RTC_TimeTypeDef
  • SecondPacketOperate : ETH_DMAConfigTypeDef
  • Seconds : RTC_TimeTypeDef
  • Sector : FLASH_ProcessTypeDef , FLASH_EraseInitTypeDef
  • SecureAreaConfig : FLASH_OBProgramInitTypeDef
  • SecureAreaEndAddr : FLASH_OBProgramInitTypeDef
  • SecureAreaStartAddr : FLASH_OBProgramInitTypeDef
  • SecuredMode : HAL_SD_CardStatusTypedef
  • SegmentCnt : ETH_RxPacketInfo
  • Selection : DFSDM_Channel_OutputClockTypeDef
  • Sensitivity : HRTIM_EventCfgTypeDef
  • SerialInterface : DFSDM_Channel_InitTypeDef
  • SetSource : HRTIM_OutputCfgTypeDef
  • Setup : PCD_HandleTypeDef
  • SignalFreeTime : CEC_InitTypeDef
  • SignalFreeTimeOption : CEC_InitTypeDef
  • SignalID : HAL_DMA_MuxRequestGeneratorConfigTypeDef
  • SincOrder : DFSDM_Filter_FilterParamTypeDef
  • SingleDiff : ADC_ChannelConfTypeDef
  • SIOOMode : QSPI_CommandTypeDef
  • Size : MPU_Region_InitTypeDef , CRYP_HandleTypeDef , DMA2D_CLUTCfgTypeDef
  • SlaveExtendFREDetection : I2S_InitTypeDef
  • SlaveMode : TIM_SlaveConfigTypeDef , USART_InitTypeDef
  • SlotActive : SAI_SlotInitTypeDef
  • SlotInit : __SAI_HandleTypeDef
  • SlotNumber : SAI_SlotInitTypeDef
  • SlotSize : SAI_SlotInitTypeDef
  • SlowProtocolDetect : ETH_MACConfigTypeDef
  • SMBusTimeout : SMBUS_InitTypeDef
  • Source : HRTIM_EventCfgTypeDef , HRTIM_FaultCfgTypeDef , LPTIM_ClockConfigTypeDef , LPTIM_TriggerConfigTypeDef , RCC_CRSInitTypeDef , TIMEx_BreakInputConfigTypeDef
  • SourceAddrControl : ETH_MACConfigTypeDef
  • SourceBlockAddressOffset : MDMA_InitTypeDef
  • SourceBurst : MDMA_InitTypeDef
  • SourceDataSize : MDMA_InitTypeDef
  • SourceInc : MDMA_InitTypeDef
  • SourcePort : ETH_L4FilterConfigTypeDef
  • SourceTxDesc : ETH_TxVLANConfigTypeDef
  • SpareAreaSize : NAND_DeviceConfigTypeDef
  • SpdifrxClockSelection : RCC_PeriphCLKInitTypeDef
  • Speed : GPIO_InitTypeDef , ETH_MACConfigTypeDef
  • SpeedClass : HAL_SD_CardStatusTypedef
  • Spi1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Spi2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Spi3ClockSelection : RCC_PeriphCLKInitTypeDef
  • Spi4ClockSelection : RCC_PeriphCLKInitTypeDef
  • Spi5ClockSelection : RCC_PeriphCLKInitTypeDef
  • Spi6ClockSelection : RCC_PeriphCLKInitTypeDef
  • SpiClock : DFSDM_Channel_SerialInterfaceTypeDef
  • SrcAddrCtrl : ETH_TxPacketConfig
  • SrcAddress : MDMA_LinkNodeConfTypeDef
  • SrcAddrFiltering : ETH_MACFilterConfigTypeDef
  • SrcAddrFilterMatch : ETH_L3FilterConfigTypeDef
  • SrcAddrHigherBitsMatch : ETH_L3FilterConfigTypeDef
  • SrcAddrInverseFiltering : ETH_MACFilterConfigTypeDef
  • SrcPortFilterMatch : ETH_L4FilterConfigTypeDef
  • Standard : I2S_InitTypeDef
  • StandardFilterSA : FDCAN_MsgRamAddressTypeDef
  • StartCycle : FDCAN_TriggerTypeDef
  • StartOnSync : HRTIM_TimerCfgTypeDef
  • StartPulse : HRTIM_ChopperModeCfgTypeDef
  • State : __I2C_HandleTypeDef , JPEG_HandleTypeDef , FDCAN_HandleTypeDef , DFSDM_Channel_HandleTypeDef , __DMA_HandleTypeDef , CRC_HandleTypeDef , SWPMI_HandleTypeDef , ADC_HandleTypeDef , COMP_HandleTypeDef , CRYP_HandleTypeDef , DAC_HandleTypeDef , DCMI_HandleTypeDef , USART_HandleTypeDef , DFSDM_Filter_HandleTypeDef , __DMA2D_HandleTypeDef , LTDC_HandleTypeDef , SPDIFRX_HandleTypeDef , HASH_HandleTypeDef , HCD_HandleTypeDef , __HRTIM_HandleTypeDef , __SPI_HandleTypeDef , TIM_HandleTypeDef , __I2S_HandleTypeDef , LPTIM_HandleTypeDef , SDRAM_HandleTypeDef , SMBUS_HandleTypeDef , MDIOS_HandleTypeDef , PCD_HandleTypeDef , __MDMA_HandleTypeDef , MMC_HandleTypeDef , SD_HandleTypeDef , NOR_HandleTypeDef , RNG_HandleTypeDef , RTC_HandleTypeDef , __SAI_HandleTypeDef , QSPI_HandleTypeDef , OPAMP_HandleTypeDef , SRAM_HandleTypeDef , NAND_HandleTypeDef
  • Status : OPAMP_HandleTypeDef , LPTIM_HandleTypeDef , HASH_HandleTypeDef
  • StatusBytesSize : QSPI_AutoPollingTypeDef
  • StdFiltersNbr : FDCAN_InitTypeDef
  • StereoMode : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • StopBits : UART_InitTypeDef , USART_InitTypeDef , SMARTCARD_InitTypeDef
  • StopWatchTrigSel : FDCAN_TT_ConfigTypeDef
  • StoreOperation : RTC_TimeTypeDef
  • StreamBaseAddress : __DMA_HandleTypeDef
  • StreamIndex : __DMA_HandleTypeDef
  • StripInnerVLANTag : ETH_RxVLANConfigTypeDef
  • StripVLANTag : ETH_RxVLANConfigTypeDef
  • SubRegionDisable : MPU_Region_InitTypeDef
  • SubSeconds : RTC_TimeTypeDef
  • Support2KPacket : ETH_MACConfigTypeDef
  • SuspendRequest : HASH_HandleTypeDef
  • SVLANType : ETH_TxVLANConfigTypeDef
  • Swap : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • Swpmi1ClockSelection : RCC_PeriphCLKInitTypeDef
  • SyncDevLimit : FDCAN_TT_ConfigTypeDef
  • SyncEnable : HAL_DMA_MuxSyncConfigTypeDef
  • SynchPrediv : RTC_InitTypeDef
  • Synchro : SAI_InitTypeDef
  • SynchroExt : SAI_InitTypeDef
  • SynchroMode : DCMI_InitTypeDef
  • SyncInputSource : HRTIM_InitTypeDef
  • SyncOptions : HRTIM_InitTypeDef
  • SyncOutputPolarity : HRTIM_InitTypeDef
  • SyncOutputSource : HRTIM_InitTypeDef
  • SyncPolarity : HAL_DMA_MuxSyncConfigTypeDef
  • SyncroCode : DCMI_InitTypeDef
  • SyncSignalID : HAL_DMA_MuxSyncConfigTypeDef
  • SyncState : FDCAN_TTOperationStatusTypeDef
  • SYSCLKDivider : RCC_ClkInitTypeDef
  • SYSCLKSource : RCC_ClkInitTypeDef
  • SysSpecVersion : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • x
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- t -

  • TAAC : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • Tamper : RTC_TamperTypeDef
  • TamperPullUp : RTC_TamperTypeDef
  • TCPHeaderLen : ETH_TxPacketConfig
  • TCPSegmentation : ETH_DMAConfigTypeDef
  • TDCvalue : FDCAN_ProtocolStatusTypeDef
  • TempWrProtect : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • Third_Id : NAND_IDTypeDef
  • TimeFormat : RTC_TimeTypeDef
  • TimeMark : FDCAN_TriggerTypeDef
  • TimeMaster : FDCAN_TT_ConfigTypeDef
  • Timeout : QSPI_HandleTypeDef
  • TimeOutActivation : QSPI_MemoryMappedTypeDef
  • TimeOutEnable : SMARTCARD_InitTypeDef
  • TimeOutPeriod : QSPI_MemoryMappedTypeDef
  • TimeOutValue : SMARTCARD_InitTypeDef
  • TimeQuantaPerBitTime : FDCAN_ClkCalUnitTypeDef
  • TimerParam : __HRTIM_HandleTypeDef
  • TimeStampOnTamperDetection : RTC_TamperTypeDef
  • Timing : I2C_InitTypeDef , SMBUS_InitTypeDef
  • TIMode : SPI_InitTypeDef
  • TIMPresSelection : RCC_PeriphCLKInitTypeDef
  • TmEventExt : FDCAN_TriggerTypeDef
  • TmEventInt : FDCAN_TriggerTypeDef
  • Tolerance : CEC_InitTypeDef
  • TotalHeigh : LTDC_InitTypeDef
  • TotalWidth : LTDC_InitTypeDef
  • TransferTriggerMode : MDMA_InitTypeDef
  • TransmitFlowControl : ETH_MACConfigTypeDef
  • TransmitPause : FDCAN_InitTypeDef
  • TransmitQueueMode : ETH_MACConfigTypeDef
  • Trigger : DFSDM_Filter_RegularParamTypeDef , DFSDM_Filter_InjectedParamTypeDef , HRTIM_CaptureCfgTypeDef , HRTIM_BurstModeCfgTypeDef , HRTIM_ADCTriggerCfgTypeDef , LPTIM_InitTypeDef , RTC_TamperTypeDef
  • TriggeredMode : ADC_OversamplingTypeDef
  • TriggerFilter : TIM_SlaveConfigTypeDef
  • TriggerIndex : FDCAN_TriggerTypeDef
  • TriggerMemoryNbr : FDCAN_TT_ConfigTypeDef
  • TriggerMode : COMP_InitTypeDef
  • TriggerPolarity : TIM_SlaveConfigTypeDef
  • TriggerPrescaler : TIM_SlaveConfigTypeDef
  • TriggerType : FDCAN_TriggerTypeDef
  • TrimmingValueN : OPAMP_InitTypeDef
  • TrimmingValueNHighSpeed : OPAMP_InitTypeDef
  • TrimmingValueP : OPAMP_InitTypeDef
  • TrimmingValuePHighSpeed : OPAMP_InitTypeDef
  • TriState : SAI_InitTypeDef
  • ttcan : FDCAN_HandleTypeDef
  • TTMemorySA : FDCAN_MsgRamAddressTypeDef
  • TURDenominator : FDCAN_TT_ConfigTypeDef
  • TURNumerator : FDCAN_TT_ConfigTypeDef
  • TwoSamplingDelay : ADC_MultiModeTypeDef
  • TxBuffer : ETH_TxPacketConfig
  • TxBufferIndex : FDCAN_TriggerTypeDef
  • TxBufferingMode : SWPMI_InitTypeDef
  • TxBufferSA : FDCAN_MsgRamAddressTypeDef
  • TxBuffersNbr : FDCAN_InitTypeDef
  • TxCompletionIndication : SMARTCARD_AdvFeatureInitTypeDef
  • TxCRCInitializationPattern : SPI_InitTypeDef
  • TxDesc : ETH_TxDescListTypeDef , ETH_InitTypeDef
  • TxDescList : ETH_HandleTypeDef
  • TxDMABurstLength : ETH_DMAConfigTypeDef
  • TxElmtSize : FDCAN_InitTypeDef
  • TxEnableWindow : FDCAN_TT_ConfigTypeDef
  • TxErrorCnt : FDCAN_ErrorCountersTypeDef
  • TxEventFifoControl : FDCAN_TxHeaderTypeDef
  • TxEventFIFOSA : FDCAN_MsgRamAddressTypeDef
  • TxEventsNbr : FDCAN_InitTypeDef
  • TxFIFOQSA : FDCAN_MsgRamAddressTypeDef
  • TxFifoQueueElmtsNbr : FDCAN_InitTypeDef
  • TxFifoQueueMode : FDCAN_InitTypeDef
  • TXFIFOThreshold : USART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef
  • TxFrameType : FDCAN_TxEventFifoTypeDef , FDCAN_TxHeaderTypeDef
  • TxISR : __I2S_HandleTypeDef , __SPI_HandleTypeDef
  • TxPinLevelInvert : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • TxTimestamp : FDCAN_TxEventFifoTypeDef
  • TxXferCount : IRDA_HandleTypeDef , USART_HandleTypeDef , __SPI_HandleTypeDef , QSPI_HandleTypeDef , CEC_HandleTypeDef , UART_HandleTypeDef , __I2S_HandleTypeDef , SMARTCARD_HandleTypeDef , SWPMI_HandleTypeDef
  • TxXferSize : MMC_HandleTypeDef , IRDA_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef , SD_HandleTypeDef , QSPI_HandleTypeDef , USART_HandleTypeDef , SWPMI_HandleTypeDef , __I2S_HandleTypeDef , SMARTCARD_HandleTypeDef
  • Type : DFSDM_Channel_SerialInterfaceTypeDef
  • TypeErase : FLASH_EraseInitTypeDef
  • TypeExtField : MPU_Region_InitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • u
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  • w
  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- u -

  • Uart4ClockSelection : RCC_PeriphCLKInitTypeDef
  • Uart5ClockSelection : RCC_PeriphCLKInitTypeDef
  • UART7ClockSelection : RCC_PeriphCLKInitTypeDef
  • UART8ClockSelection : RCC_PeriphCLKInitTypeDef
  • UltraLowPowerClock : LPTIM_InitTypeDef
  • UnicastPausePacketDetect : ETH_MACConfigTypeDef
  • UnicastSlowProtocolPacketDetect : ETH_MACConfigTypeDef
  • UpdateGating : HRTIM_TimerCfgTypeDef
  • UpdateMode : LPTIM_InitTypeDef
  • UpdateSource : HRTIM_ADCTriggerCfgTypeDef
  • UpdateTrigger : HRTIM_TimerCfgTypeDef
  • Usart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart3ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart6ClockSelection : RCC_PeriphCLKInitTypeDef
  • UsbClockSelection : RCC_PeriphCLKInitTypeDef
  • USERConfig : FLASH_OBProgramInitTypeDef
  • UserTrimming : OPAMP_InitTypeDef
  • USERType : FLASH_OBProgramInitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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  • q
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  • t
  • u
  • v
  • w
  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- v -

  • ValidityBitMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • VerticalSync : LTDC_InitTypeDef
  • VlanCtrl : ETH_TxPacketConfig
  • VlanTag : ETH_TxPacketConfig , ETH_RxPacketInfo
  • VLANTagControl : ETH_TxVLANConfigTypeDef
  • VLANTagHashTableMatch : ETH_RxVLANConfigTypeDef
  • VLANTagInStatus : ETH_RxVLANConfigTypeDef
  • VLANTagInverceMatch : ETH_RxVLANConfigTypeDef
  • VLANTypeCheck : ETH_RxVLANConfigTypeDef
  • VoltageClass : SWPMI_InitTypeDef
  • VoltageForErase : FLASH_ProcessTypeDef
  • VoltageRange : FLASH_EraseInitTypeDef
  • VSPolarity : DCMI_InitTypeDef , LTDC_InitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- w -

  • WaitForActivity : SPDIFRX_InitTypeDef
  • WaitForEvt : FDCAN_TTOperationStatusTypeDef
  • WakeUpEvent : UART_WakeUpTypeDef
  • WakeUpForward : ETH_PowerDownConfigTypeDef
  • WakeUpPacket : ETH_PowerDownConfigTypeDef
  • WakeUpPin : PWREx_WakeupPinTypeDef
  • Warning : FDCAN_ProtocolStatusTypeDef
  • Watchdog : ETH_MACConfigTypeDef
  • WatchdogMode : ADC_AnalogWDGConfTypeDef
  • WatchdogNumber : ADC_AnalogWDGConfTypeDef
  • WatchdogStartValue : FDCAN_ClkCalUnitTypeDef
  • WatchdogTimeout : ETH_MACConfigTypeDef
  • WeekDay : RTC_DateTypeDef
  • Window : IWDG_InitTypeDef , WWDG_InitTypeDef
  • WindowMode : COMP_InitTypeDef
  • WindowX0 : LTDC_LayerCfgTypeDef
  • WindowX1 : LTDC_LayerCfgTypeDef
  • WindowY0 : LTDC_LayerCfgTypeDef
  • WindowY1 : LTDC_LayerCfgTypeDef
  • WordLength : UART_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef , USART_InitTypeDef
  • WrBlockMisalign : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • WriteBlockPaPartial : HAL_SD_CardCSDTypedef , HAL_MMC_CardCSDTypeDef
  • WrProtectGrEnable : HAL_SD_CardCSDTypedef , HAL_MMC_CardCSDTypeDef
  • WrProtectGrSize : HAL_SD_CardCSDTypedef , HAL_MMC_CardCSDTypeDef
  • WRPSector : FLASH_OBProgramInitTypeDef
  • WRPState : FLASH_OBProgramInitTypeDef
  • WrSpeedFact : HAL_SD_CardCSDTypedef , HAL_MMC_CardCSDTypeDef
  • WSInversion : I2S_InitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- x -

  • XferAbortCallback : __DMA_HandleTypeDef , __MDMA_HandleTypeDef
  • XferBlockCpltCallback : __MDMA_HandleTypeDef
  • XferBufferCpltCallback : __MDMA_HandleTypeDef
  • XferCount : SMBUS_HandleTypeDef , DCMI_HandleTypeDef , __I2C_HandleTypeDef , __SAI_HandleTypeDef
  • XferCpltCallback : __DMA_HandleTypeDef , __DMA2D_HandleTypeDef , __MDMA_HandleTypeDef
  • XferErrorCallback : __DMA_HandleTypeDef , __DMA2D_HandleTypeDef , __MDMA_HandleTypeDef
  • XferHalfCpltCallback : __DMA_HandleTypeDef
  • XferISR : __I2C_HandleTypeDef
  • XferM1CpltCallback : __DMA_HandleTypeDef
  • XferM1HalfCpltCallback : __DMA_HandleTypeDef
  • XferOptions : __I2C_HandleTypeDef , SMBUS_HandleTypeDef
  • XferRepeatBlockCpltCallback : __MDMA_HandleTypeDef
  • XferSize : SMBUS_HandleTypeDef , DCMI_HandleTypeDef , __SAI_HandleTypeDef , __I2C_HandleTypeDef
  • XferTransferNumber : DCMI_HandleTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- y -

  • Year : RTC_DateTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- z -

  • ZeroQuantaPause : ETH_MACConfigTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- a -

  • AccessPermission : MPU_Region_InitTypeDef
  • AccumulatedActiveH : LTDC_InitTypeDef
  • AccumulatedActiveW : LTDC_InitTypeDef
  • AccumulatedHBP : LTDC_InitTypeDef
  • AccumulatedVBP : LTDC_InitTypeDef
  • Activation : DFSDM_Channel_OutputClockTypeDef , SAI_PdmInitTypeDef
  • ActiveEdge : LPTIM_TriggerConfigTypeDef
  • ActiveFrameLength : SAI_FrameInitTypeDef
  • Activity : FDCAN_ProtocolStatusTypeDef
  • AdcClockSelection : RCC_PeriphCLKInitTypeDef
  • Address : FLASH_ProcessTypeDef , QSPI_CommandTypeDef , UART_WakeUpTypeDef
  • AddressAlignedBeats : ETH_DMAConfigTypeDef
  • AddressingMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • AddressLength : UART_WakeUpTypeDef
  • AddressMode : QSPI_CommandTypeDef
  • AddressSize : QSPI_CommandTypeDef
  • AddrEventCount : __I2C_HandleTypeDef
  • AdvancedInit : SMARTCARD_HandleTypeDef , UART_HandleTypeDef
  • AdvFeatureInit : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • AHBCLKDivider : RCC_ClkInitTypeDef
  • Alarm : RTC_AlarmTypeDef
  • AlarmDateWeekDay : RTC_AlarmTypeDef
  • AlarmDateWeekDaySel : RTC_AlarmTypeDef
  • AlarmMask : RTC_AlarmTypeDef
  • AlarmSubSecondMask : RTC_AlarmTypeDef
  • AlarmTime : RTC_AlarmTypeDef
  • Algorithm : CRYP_ConfigTypeDef
  • AllocationUnitSize : HAL_SD_CardStatusTypedef
  • Alpha : LTDC_LayerCfgTypeDef
  • Alpha0 : LTDC_LayerCfgTypeDef
  • AlphaInverted : DMA2D_InitTypeDef , DMA2D_LayerCfgTypeDef
  • AlphaMode : DMA2D_LayerCfgTypeDef
  • Alternate : GPIO_InitTypeDef
  • AlternateByteMode : QSPI_CommandTypeDef
  • AlternateBytes : QSPI_CommandTypeDef
  • AlternateBytesSize : QSPI_CommandTypeDef
  • AnalogFilter : SMBUS_InitTypeDef
  • APB1CLKDivider : RCC_ClkInitTypeDef
  • APB2CLKDivider : RCC_ClkInitTypeDef
  • APB3CLKDivider : RCC_ClkInitTypeDef
  • APB4CLKDivider : RCC_ClkInitTypeDef
  • AppContextDesc : ETH_RxDescListTypeDef
  • AppDescNbr : ETH_RxDescListTypeDef
  • AppWdgEvt : FDCAN_TTOperationStatusTypeDef
  • AppWdgLimit : FDCAN_TT_ConfigTypeDef
  • AsynchPrediv : RTC_InitTypeDef
  • Attributes : ETH_TxPacketConfig
  • AudioFreq : I2S_InitTypeDef
  • AudioFrequency : SAI_InitTypeDef
  • AudioMode : SAI_InitTypeDef
  • AutoBaudRateEnable : UART_AdvFeatureInitTypeDef
  • AutoBaudRateMode : UART_AdvFeatureInitTypeDef
  • AutoDelayedMode : HRTIM_CompareCfgTypeDef
  • AutoDelayedTimeout : HRTIM_CompareCfgTypeDef
  • AutoInjectedConv : ADC_InjectionConfTypeDef
  • AutomaticOutput : TIM_BreakDeadTimeConfigTypeDef
  • AutomaticPadCRCStrip : ETH_MACConfigTypeDef
  • AutomaticStop : QSPI_AutoPollingTypeDef
  • AutoReloadPreload : TIM_Base_InitTypeDef
  • AutoRetransmission : FDCAN_InitTypeDef
  • AutoRetryCount : SMARTCARD_InitTypeDef
  • AVDLevel : PWREx_AVDTypeDef
  • Awd : DFSDM_Channel_InitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- b -

  • B0 : CRYP_ConfigTypeDef
  • Backcolor : LTDC_InitTypeDef , LTDC_LayerCfgTypeDef
  • BackOffLimit : ETH_MACConfigTypeDef
  • Banks : FLASH_EraseInitTypeDef , FLASH_OBProgramInitTypeDef
  • BaseAddress : MPU_Region_InitTypeDef
  • BasicCyclesNbr : FDCAN_TT_ConfigTypeDef
  • battery_charging_active : PCD_HandleTypeDef
  • BaudRate : IRDA_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • BaudRatePrescaler : SPI_InitTypeDef
  • BESL : PCD_HandleTypeDef
  • BitRate : SWPMI_InitTypeDef
  • BitRateSwitch : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • Bits : JPEG_ACHuffTableTypeDef , JPEG_DCHuffTableTypeDef
  • BlankingSrce : COMP_InitTypeDef
  • BlendingFactor1 : LTDC_LayerCfgTypeDef
  • BlendingFactor2 : LTDC_LayerCfgTypeDef
  • Block : NAND_AddressTypeDef
  • BlockCount : MDMA_LinkNodeConfTypeDef
  • BlockDataLength : MDMA_LinkNodeConfTypeDef
  • BlockLength : SMARTCARD_InitTypeDef
  • BlockNbr : HAL_MMC_CardInfoTypeDef , NAND_DeviceConfigTypeDef , HAL_SD_CardInfoTypeDef
  • BlockSize : HAL_MMC_CardInfoTypeDef , NAND_DeviceConfigTypeDef , HAL_SD_CardInfoTypeDef
  • Blue : DMA2D_ColorTypeDef , LTDC_ColorTypeDef
  • BoostMode : ADC_InitTypeDef
  • BootAddr0 : FLASH_OBProgramInitTypeDef
  • BootAddr1 : FLASH_OBProgramInitTypeDef
  • BootConfig : FLASH_OBProgramInitTypeDef
  • BORLevel : FLASH_OBProgramInitTypeDef
  • Break2Filter : TIM_BreakDeadTimeConfigTypeDef
  • Break2Polarity : TIM_BreakDeadTimeConfigTypeDef
  • Break2State : TIM_BreakDeadTimeConfigTypeDef
  • BreakFilter : TIM_BreakDeadTimeConfigTypeDef
  • BreakPolarity : TIM_BreakDeadTimeConfigTypeDef
  • BreakState : TIM_BreakDeadTimeConfigTypeDef
  • BREErrorBitGen : CEC_InitTypeDef
  • BRERxStop : CEC_InitTypeDef
  • BroadcastFilter : ETH_MACFilterConfigTypeDef
  • BroadcastMsgNoErrorBitGen : CEC_InitTypeDef
  • buffer : __ETH_BufferTypeDef
  • BufferTransferLength : MDMA_InitTypeDef
  • BurstMode : HRTIM_TimerCfgTypeDef , ETH_DMAConfigTypeDef
  • BurstModeEntryDelayed : HRTIM_OutputCfgTypeDef
  • BusOff : FDCAN_ProtocolStatusTypeDef
  • ByteSelectMode : DCMI_InitTypeDef
  • ByteSelectStart : DCMI_InitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- c -

  • CalFieldLength : FDCAN_ClkCalUnitTypeDef
  • CaptureRate : DCMI_InitTypeDef
  • CaptureTrigger1 : HRTIM_TimerParamTypeDef
  • CaptureTrigger2 : HRTIM_TimerParamTypeDef
  • CardComdClasses : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • CardSpeed : HAL_SD_CardInfoTypeDef
  • CardType : HAL_MMC_CardInfoTypeDef , HAL_SD_CardInfoTypeDef , HAL_SD_CardStatusTypedef
  • CardVersion : HAL_SD_CardInfoTypeDef
  • CarrierFreq : HRTIM_ChopperModeCfgTypeDef
  • CarrierSenseBeforeTransmit : ETH_MACConfigTypeDef
  • CarrierSenseDuringTransmit : ETH_MACConfigTypeDef
  • CBNDTR : MDMA_LinkNodeTypeDef
  • CBRUR : MDMA_LinkNodeTypeDef
  • CDAR : MDMA_LinkNodeTypeDef
  • CecClockSelection : RCC_PeriphCLKInitTypeDef
  • CFI_1 : NOR_CFITypeDef
  • CFI_2 : NOR_CFITypeDef
  • CFI_3 : NOR_CFITypeDef
  • CFI_4 : NOR_CFITypeDef
  • Channel : ADC_AnalogWDGConfTypeDef , ADC_ChannelConfTypeDef , DFSDM_Filter_AwdParamTypeDef , TIM_HandleTypeDef
  • ChannelCount : ADC_InjectionConfigTypeDef
  • ChannelSelection : SPDIFRX_InitTypeDef
  • ChannelStatusMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • Checksum : ETH_RxPacketInfo
  • ChecksumCtrl : ETH_TxPacketConfig
  • ChecksumOffload : ETH_MACConfigTypeDef
  • ChipSelectHighTime : QSPI_InitTypeDef
  • ChopperModeEnable : HRTIM_OutputCfgTypeDef
  • ChromaSubsampling : JPEG_ConfTypeDef
  • ChromaSubSampling : DMA2D_LayerCfgTypeDef
  • CID : MMC_HandleTypeDef , SD_HandleTypeDef
  • CID_CRC : HAL_MMC_CardCIDTypedef , HAL_SD_CardCIDTypedef
  • CkperClockSelection : RCC_PeriphCLKInitTypeDef
  • CLAR : MDMA_LinkNodeTypeDef
  • Class : HAL_MMC_CardInfoTypeDef , HAL_SD_CardInfoTypeDef
  • ClearInputFilter : TIM_ClearInputConfigTypeDef
  • ClearInputPolarity : TIM_ClearInputConfigTypeDef
  • ClearInputPrescaler : TIM_ClearInputConfigTypeDef
  • ClearInputSource : TIM_ClearInputConfigTypeDef
  • ClearInputState : TIM_ClearInputConfigTypeDef
  • CLKLastBit : SMARTCARD_InitTypeDef , USART_InitTypeDef
  • CLKPhase : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • CLKPolarity : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • Clock : LPTIM_InitTypeDef
  • ClockCalibration : FDCAN_ClkCalUnitTypeDef , FDCAN_TT_ConfigTypeDef
  • ClockDivider : FDCAN_ClkCalUnitTypeDef
  • ClockDivision : TIM_Base_InitTypeDef
  • ClockEnable : SAI_PdmInitTypeDef
  • ClockErrorDetection : RNG_InitTypeDef
  • ClockFilter : TIM_ClockConfigTypeDef
  • ClockMode : QSPI_InitTypeDef
  • ClockPolarity : TIM_ClockConfigTypeDef
  • ClockPrescaler : ADC_InitTypeDef , QSPI_InitTypeDef , TIM_ClockConfigTypeDef
  • ClockQuality : FDCAN_TTOperationStatusTypeDef
  • ClockSource : HRTIM_BurstModeCfgTypeDef , TIM_ClockConfigTypeDef
  • ClockStrobing : SAI_InitTypeDef
  • ClockType : RCC_ClkInitTypeDef
  • CLUTColorMode : DMA2D_CLUTCfgTypeDef
  • CMAR : MDMA_LinkNodeTypeDef
  • CMDR : MDMA_LinkNodeTypeDef
  • CodeLength : JPEG_AC_HuffCodeTableTypeDef , JPEG_DC_HuffCodeTableTypeDef
  • ColorMode : DMA2D_InitTypeDef
  • ColorSpace : JPEG_ConfTypeDef
  • Commutation_Delay : TIM_HallSensor_InitTypeDef
  • CompandingMode : SAI_InitTypeDef
  • CompareValue : HRTIM_CompareCfgTypeDef
  • Conf : JPEG_HandleTypeDef
  • Config : NAND_HandleTypeDef
  • ContentProtectAppli : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • Context : JPEG_HandleTypeDef , MMC_HandleTypeDef , SD_HandleTypeDef
  • ContextQueue : ADC_InjectionConfigTypeDef
  • ContinuousConvMode : ADC_InitTypeDef
  • ControlPacketsFilter : ETH_MACFilterConfigTypeDef
  • ConversionDataManagement : ADC_InitTypeDef
  • CopyFlag : HAL_SD_CardCSDTypedef , HAL_MMC_CardCSDTypeDef
  • Counter : WWDG_InitTypeDef
  • CounterMode : TIM_Base_InitTypeDef
  • CounterSource : LPTIM_InitTypeDef
  • CPOL : I2S_InitTypeDef
  • CRCCalculation : SPI_InitTypeDef
  • CRCCheckingRxPackets : ETH_MACConfigTypeDef
  • CRCLength : CRC_InitTypeDef , SPI_InitTypeDef
  • CRCPadCtrl : ETH_TxPacketConfig
  • CRCPolynomial : SPI_InitTypeDef
  • CRCSize : __SPI_HandleTypeDef
  • CRCStripTypePacket : ETH_MACConfigTypeDef
  • CrypHeaderCount : CRYP_HandleTypeDef
  • CrypInCount : CRYP_HandleTypeDef
  • CrypOutCount : CRYP_HandleTypeDef
  • CSAR : MDMA_LinkNodeTypeDef
  • CSD : SD_HandleTypeDef , MMC_HandleTypeDef
  • CSD_CRC : HAL_SD_CardCSDTypedef , HAL_MMC_CardCSDTypeDef
  • CSDStruct : HAL_SD_CardCSDTypedef , HAL_MMC_CardCSDTypeDef
  • CSICalibrationValue : RCC_OscInitTypeDef
  • CSIState : RCC_OscInitTypeDef
  • CsXferCount : SPDIFRX_HandleTypeDef
  • CsXferSize : SPDIFRX_HandleTypeDef
  • CTBR : MDMA_LinkNodeTypeDef
  • CTCR : MDMA_LinkNodeTypeDef
  • CurRxDesc : ETH_RxDescListTypeDef
  • CurTxDesc : ETH_TxDescListTypeDef
  • CustomQuanTable : JPEG_HandleTypeDef
  • CycleStartSync : FDCAN_TT_ConfigTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
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- d -

  • DAC_ConnectOnChipPeripheral : DAC_ChannelConfTypeDef
  • DAC_HoldTime : DAC_SampleAndHoldConfTypeDef
  • DAC_OutputBuffer : DAC_ChannelConfTypeDef
  • DAC_RefreshTime : DAC_SampleAndHoldConfTypeDef
  • DAC_SampleAndHold : DAC_ChannelConfTypeDef
  • DAC_SampleAndHoldConfig : DAC_ChannelConfTypeDef
  • DAC_SampleTime : DAC_SampleAndHoldConfTypeDef
  • DAC_Trigger : DAC_ChannelConfTypeDef
  • DAC_TrimmingValue : DAC_ChannelConfTypeDef
  • DAC_UserTrimming : DAC_ChannelConfTypeDef
  • DACSynchro : HRTIM_TimerCfgTypeDef
  • Data24BitAlignment : I2S_InitTypeDef
  • DataAlignment : MDMA_InitTypeDef
  • DataBusWidth : HAL_SD_CardStatusTypedef
  • DataFormat : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef , I2S_InitTypeDef
  • DataInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • DataLastErrorCode : FDCAN_ProtocolStatusTypeDef
  • DataLength : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • DataMode : QSPI_CommandTypeDef
  • DataPacking : DFSDM_Channel_InputTypeDef
  • DataPrescaler : FDCAN_InitTypeDef
  • DataSize : SAI_InitTypeDef , SPI_InitTypeDef
  • DataSource : DFSDM_Filter_AwdParamTypeDef
  • DataSyncJumpWidth : FDCAN_InitTypeDef
  • DataTimeSeg1 : FDCAN_InitTypeDef
  • DataTimeSeg2 : FDCAN_InitTypeDef
  • DataType : CRYP_ConfigTypeDef , HASH_InitTypeDef
  • Date : RTC_DateTypeDef
  • DayLightSaving : RTC_TimeTypeDef
  • DdrHoldHalfCycle : QSPI_CommandTypeDef
  • DdrMode : QSPI_CommandTypeDef
  • DeadTime : TIM_BreakDeadTimeConfigTypeDef
  • DeadTimeInsertion : HRTIM_TimerCfgTypeDef
  • DefaultInitValueUse : CRC_InitTypeDef
  • DefaultPolynomialUse : CRC_InitTypeDef
  • DeferralCheck : ETH_MACConfigTypeDef
  • DelayedProtectionMode : HRTIM_TimerCfgTypeDef
  • DEPolarity : LTDC_InitTypeDef
  • DestAddrFilterMatch : ETH_L3FilterConfigTypeDef
  • DestAddrHigherBitsMatch : ETH_L3FilterConfigTypeDef
  • DestAddrInverseFiltering : ETH_MACFilterConfigTypeDef
  • DestBlockAddressOffset : MDMA_InitTypeDef
  • DestBurst : MDMA_InitTypeDef
  • DestDataSize : MDMA_InitTypeDef
  • DestinationInc : MDMA_InitTypeDef
  • DestinationPort : ETH_L4FilterConfigTypeDef
  • DestPortFilterMatch : ETH_L4FilterConfigTypeDef
  • Device_Code1 : NOR_IDTypeDef
  • Device_Code2 : NOR_IDTypeDef
  • Device_Code3 : NOR_IDTypeDef
  • Device_Id : NAND_IDTypeDef
  • DeviceSize : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • DeviceSizeMul : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • Dfsdm1ClockSelection : RCC_PeriphCLKInitTypeDef
  • DigestCalculationDisable : HASH_HandleTypeDef
  • Direction : DMA_InitTypeDef , SPI_InitTypeDef
  • DisableExec : MPU_Region_InitTypeDef
  • DiscontinuousConvMode : ADC_InitTypeDef
  • Divider : DFSDM_Channel_OutputClockTypeDef
  • DMA_Handle : ADC_HandleTypeDef , DCMI_HandleTypeDef
  • DMA_Handle1 : DAC_HandleTypeDef
  • DMA_Handle2 : DAC_HandleTypeDef
  • DMAArbitration : ETH_DMAConfigTypeDef
  • DMADisableonRxError : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • DMADstAddress : HRTIM_TimerCfgTypeDef , HRTIM_TimerParamTypeDef
  • DMAErrorCode : ETH_HandleTypeDef
  • DmaMode : DFSDM_Filter_RegularParamTypeDef , DFSDM_Filter_InjectedParamTypeDef
  • DMAmuxChannel : __DMA_HandleTypeDef
  • DMAmuxChannelStatus : __DMA_HandleTypeDef
  • DMAmuxChannelStatusMask : __DMA_HandleTypeDef
  • DMAmuxRequestGen : __DMA_HandleTypeDef
  • DMAmuxRequestGenStatus : __DMA_HandleTypeDef
  • DMAmuxRequestGenStatusMask : __DMA_HandleTypeDef
  • DMARequests : HRTIM_TimerParamTypeDef , HRTIM_TimerCfgTypeDef
  • DMASize : HRTIM_TimerParamTypeDef , HRTIM_TimerCfgTypeDef
  • DMASrcAddress : HRTIM_TimerParamTypeDef , HRTIM_TimerCfgTypeDef
  • DoubleVLANProcessing : ETH_RxVLANConfigTypeDef
  • DropTCPIPChecksumErrorPacket : ETH_MACConfigTypeDef
  • DSRImpl : HAL_SD_CardCSDTypedef , HAL_MMC_CardCSDTypeDef
  • DstAddress : MDMA_LinkNodeConfTypeDef
  • DualAddressMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • DualFlash : QSPI_InitTypeDef
  • DualModeData : ADC_MultiModeTypeDef
  • DummyCycles : QSPI_CommandTypeDef
  • DuplexMode : ETH_MACConfigTypeDef
  • DutyCycle : HRTIM_ChopperModeCfgTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- e -

  • ECC : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • ECSPending : FDCAN_TTOperationStatusTypeDef
  • Enable : MPU_Region_InitTypeDef , TIMEx_BreakInputConfigTypeDef
  • EncoderMode : TIM_Encoder_InitTypeDef
  • EndAddress : FDCAN_MsgRamAddressTypeDef
  • Endianness : MDMA_InitTypeDef
  • EOCSelection : ADC_InitTypeDef
  • EraseGrMul : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • EraseGrSize : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • EraseOffset : HAL_SD_CardStatusTypedef
  • EraseSize : HAL_SD_CardStatusTypedef
  • EraseTimeout : HAL_SD_CardStatusTypedef
  • ErrorCode : JPEG_HandleTypeDef , LTDC_HandleTypeDef , ADC_HandleTypeDef , __MDMA_HandleTypeDef , MMC_HandleTypeDef , CEC_HandleTypeDef , QSPI_HandleTypeDef , __SAI_HandleTypeDef , CRYP_HandleTypeDef , SD_HandleTypeDef , SMARTCARD_HandleTypeDef , DAC_HandleTypeDef , SMBUS_HandleTypeDef , SPDIFRX_HandleTypeDef , DCMI_HandleTypeDef , __SPI_HandleTypeDef , SWPMI_HandleTypeDef , DFSDM_Filter_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , __DMA_HandleTypeDef , __DMA2D_HandleTypeDef , ETH_RxPacketInfo , ETH_HandleTypeDef , FDCAN_HandleTypeDef , FLASH_ProcessTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , IRDA_HandleTypeDef
  • ErrorLevel : FDCAN_TTOperationStatusTypeDef
  • ErrorLimitValue : RCC_CRSInitTypeDef
  • ErrorLogging : FDCAN_ErrorCountersTypeDef
  • ErrorPassive : FDCAN_ProtocolStatusTypeDef
  • ErrorStateIndicator : FDCAN_RxHeaderTypeDef , FDCAN_TxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • Event : HRTIM_SimpleCaptureChannelCfgTypeDef , HRTIM_SimpleOnePulseChannelCfgTypeDef
  • EventEnable : HAL_DMA_MuxSyncConfigTypeDef
  • EventFilter : HRTIM_SimpleOnePulseChannelCfgTypeDef , HRTIM_SimpleCaptureChannelCfgTypeDef
  • EventPolarity : HRTIM_SimpleOnePulseChannelCfgTypeDef , HRTIM_SimpleCaptureChannelCfgTypeDef
  • EventSensitivity : HRTIM_SimpleOnePulseChannelCfgTypeDef , HRTIM_SimpleCaptureChannelCfgTypeDef
  • EventTrigSel : FDCAN_TT_ConfigTypeDef
  • EventType : FDCAN_TxEventFifoTypeDef
  • EvtTrigPolarity : FDCAN_TT_ConfigTypeDef
  • EWIMode : WWDG_InitTypeDef
  • ExpTxTrigNbr : FDCAN_TT_ConfigTypeDef
  • Extended : SRAM_HandleTypeDef , NOR_HandleTypeDef
  • ExtendedDataMode : DCMI_InitTypeDef
  • ExtendedFilterSA : FDCAN_MsgRamAddressTypeDef
  • ExtendedInterPacketGap : ETH_MACConfigTypeDef
  • ExtendedInterPacketGapVal : ETH_MACConfigTypeDef
  • ExternalClkSync : FDCAN_TT_ConfigTypeDef
  • ExternalTrigConv : ADC_InitTypeDef
  • ExternalTrigConvEdge : ADC_InitTypeDef
  • ExternalTrigInjecConv : ADC_InjectionConfTypeDef
  • ExternalTrigInjecConvEdge : ADC_InjectionConfTypeDef
  • ExtFiltersNbr : FDCAN_InitTypeDef
  • ExtraCommandEnable : NAND_DeviceConfigTypeDef
  • ExtTrigger : DFSDM_Filter_InjectedParamTypeDef
  • ExtTriggerEdge : DFSDM_Filter_HandleTypeDef , DFSDM_Filter_InjectedParamTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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- f -

  • FallingLock : HRTIM_DeadTimeCfgTypeDef
  • FallingSign : HRTIM_DeadTimeCfgTypeDef
  • FallingSignLock : HRTIM_DeadTimeCfgTypeDef
  • FallingValue : HRTIM_DeadTimeCfgTypeDef
  • FastMode : DFSDM_Filter_RegularParamTypeDef , HRTIM_EventCfgTypeDef
  • FaultEnable : HRTIM_TimerCfgTypeDef
  • FaultLevel : HRTIM_OutputCfgTypeDef
  • FaultLock : HRTIM_TimerCfgTypeDef
  • FBStartAdress : LTDC_LayerCfgTypeDef
  • FdcanClockSelection : RCC_PeriphCLKInitTypeDef
  • FDFormat : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • FIFOMode : SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , DMA_InitTypeDef
  • FifoThreshold : I2S_InitTypeDef , QSPI_InitTypeDef , SPI_InitTypeDef
  • FIFOThreshold : DMA_InitTypeDef , SAI_InitTypeDef
  • FileFormat : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • FileFormatGrouop : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • Filter : HRTIM_TimerEventFilteringCfgTypeDef , HRTIM_EventCfgTypeDef , HRTIM_FaultCfgTypeDef , RTC_TamperTypeDef
  • FilterConfig : FDCAN_FilterTypeDef
  • FilterID1 : FDCAN_FilterTypeDef
  • FilterID2 : FDCAN_FilterTypeDef
  • FilterIndex : FDCAN_FilterTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_HpMsgStatusTypeDef , FDCAN_TriggerTypeDef
  • FilterList : FDCAN_HpMsgStatusTypeDef
  • FilterOrder : DFSDM_Channel_AwdTypeDef
  • FilterParam : DFSDM_Filter_InitTypeDef
  • FilterType : FDCAN_FilterTypeDef , FDCAN_TriggerTypeDef
  • FirstAppDesc : ETH_RxDescListTypeDef
  • FirstBit : I2S_InitTypeDef , SPI_InitTypeDef , SAI_InitTypeDef
  • FirstBitOffset : SAI_SlotInitTypeDef
  • FirstLinkedListNodeAddress : __MDMA_HandleTypeDef
  • FlashID : QSPI_InitTypeDef
  • FlashSize : QSPI_InitTypeDef
  • FlushRxPacket : ETH_DMAConfigTypeDef
  • FmcClockSelection : RCC_PeriphCLKInitTypeDef
  • ForwardRxErrorPacket : ETH_MACConfigTypeDef
  • ForwardRxUndersizedGoodPacket : ETH_MACConfigTypeDef
  • Fourth_Id : NAND_IDTypeDef
  • FrameEndCode : DCMI_CodesInitTypeDef
  • FrameFormat : FDCAN_InitTypeDef
  • FrameInit : __SAI_HandleTypeDef
  • FrameLength : SAI_FrameInitTypeDef
  • FrameStartCode : DCMI_CodesInitTypeDef
  • FreqErrorCapture : RCC_CRSSynchroInfoTypeDef
  • FreqErrorDirection : RCC_CRSSynchroInfoTypeDef
  • FSDefinition : SAI_FrameInitTypeDef
  • FSOffset : SAI_FrameInitTypeDef
  • FSPolarity : SAI_FrameInitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • Variables
  • a
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- g -

  • GapEnable : FDCAN_TT_ConfigTypeDef
  • GapFinished : FDCAN_TTOperationStatusTypeDef
  • GapStarted : FDCAN_TTOperationStatusTypeDef
  • GeneralCallMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • GeneratingPolynomial : CRC_InitTypeDef
  • GiantPacketSizeLimit : ETH_MACConfigTypeDef
  • GiantPacketSizeLimitControl : ETH_MACConfigTypeDef
  • GlobalTimeFilter : FDCAN_TT_ConfigTypeDef
  • GlobalUnicast : ETH_PowerDownConfigTypeDef
  • Green : DMA2D_ColorTypeDef , LTDC_ColorTypeDef
  • gState : SMARTCARD_HandleTypeDef , UART_HandleTypeDef , ETH_HandleTypeDef , CEC_HandleTypeDef , IRDA_HandleTypeDef
  • GTimeDiscPending : FDCAN_TTOperationStatusTypeDef
  • GTimeQuality : FDCAN_TTOperationStatusTypeDef
  • GuardTime : SMARTCARD_InitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
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- h -

  • HachOrPerfectFilter : ETH_MACFilterConfigTypeDef
  • HalfModeEnable : HRTIM_TimerCfgTypeDef
  • HashBuffSize : HASH_HandleTypeDef
  • HashInCount : HASH_HandleTypeDef
  • HashITCounter : HASH_HandleTypeDef
  • HashKeyCount : HASH_HandleTypeDef
  • HashMulticast : ETH_MACFilterConfigTypeDef
  • HashUnicast : ETH_MACFilterConfigTypeDef
  • hc : HCD_HandleTypeDef
  • hdma : TIM_HandleTypeDef
  • hdmaCsRx : SPDIFRX_HandleTypeDef
  • hdmaDrRx : SPDIFRX_HandleTypeDef
  • hdmain : CRYP_HandleTypeDef , HASH_HandleTypeDef , JPEG_HandleTypeDef
  • hdmaInj : DFSDM_Filter_HandleTypeDef
  • hdmaMaster : __HRTIM_HandleTypeDef
  • hdmaout : CRYP_HandleTypeDef , JPEG_HandleTypeDef
  • hdmaReg : DFSDM_Filter_HandleTypeDef
  • hdmarx : __I2C_HandleTypeDef , __I2S_HandleTypeDef , IRDA_HandleTypeDef , __SAI_HandleTypeDef , SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , SWPMI_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef
  • hdmaTimerA : __HRTIM_HandleTypeDef
  • hdmaTimerB : __HRTIM_HandleTypeDef
  • hdmaTimerC : __HRTIM_HandleTypeDef
  • hdmaTimerD : __HRTIM_HandleTypeDef
  • hdmaTimerE : __HRTIM_HandleTypeDef
  • hdmatx : SMARTCARD_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , IRDA_HandleTypeDef , __SAI_HandleTypeDef , __SPI_HandleTypeDef , SWPMI_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef
  • Header : CRYP_ConfigTypeDef
  • HeaderSize : CRYP_ConfigTypeDef
  • HeaderType : ETH_RxPacketInfo
  • HighBreakSignal : DFSDM_Filter_AwdParamTypeDef
  • HighThreshold : ADC_AnalogWDGConfTypeDef , DFSDM_Filter_AwdParamTypeDef
  • hmdma : SDRAM_HandleTypeDef , QSPI_HandleTypeDef , SRAM_HandleTypeDef
  • HorizontalSync : LTDC_InitTypeDef
  • HourFormat : RTC_InitTypeDef
  • Hours : RTC_TimeTypeDef
  • Hrtim1ClockSelection : RCC_PeriphCLKInitTypeDef
  • HRTIMInterruptResquests : HRTIM_InitTypeDef
  • HSEState : RCC_OscInitTypeDef
  • HSI48CalibrationValue : RCC_CRSInitTypeDef , RCC_CRSSynchroInfoTypeDef
  • HSI48State : RCC_OscInitTypeDef
  • HSICalibrationValue : RCC_OscInitTypeDef
  • HSIState : RCC_OscInitTypeDef
  • HSPolarity : DCMI_InitTypeDef , LTDC_InitTypeDef
  • HuffmanCode : JPEG_AC_HuffCodeTableTypeDef , JPEG_DC_HuffCodeTableTypeDef
  • HuffVal : JPEG_ACHuffTableTypeDef , JPEG_DCHuffTableTypeDef
  • HwFlowCtl : UART_InitTypeDef
  • Hysteresis : COMP_InitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
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- i -

  • I2c1ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c2ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c3ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c4ClockSelection : RCC_PeriphCLKInitTypeDef
  • IC1Filter : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Polarity : TIM_HallSensor_InitTypeDef , TIM_Encoder_InitTypeDef
  • IC1Prescaler : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Selection : TIM_Encoder_InitTypeDef
  • IC2Filter : TIM_Encoder_InitTypeDef
  • IC2Polarity : TIM_Encoder_InitTypeDef
  • IC2Prescaler : TIM_Encoder_InitTypeDef
  • IC2Selection : TIM_Encoder_InitTypeDef
  • ICFilter : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • ICPolarity : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • ICPrescaler : TIM_IC_InitTypeDef
  • ICSelection : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • Identifier : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • IdleDuration : HRTIM_BurstModeCfgTypeDef
  • IdleLevel : HRTIM_SimpleOCChannelCfgTypeDef , HRTIM_SimplePWMChannelCfgTypeDef , HRTIM_OutputCfgTypeDef
  • IdleMode : HRTIM_OutputCfgTypeDef
  • IdType : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef , FDCAN_FilterTypeDef
  • IFCR : DMA_Base_Registers
  • ImageHeight : JPEG_ConfTypeDef , LTDC_LayerCfgTypeDef
  • ImageQuality : JPEG_ConfTypeDef
  • ImageWidth : JPEG_ConfTypeDef , LTDC_LayerCfgTypeDef
  • IN_ep : PCD_HandleTypeDef
  • InDataLength : JPEG_HandleTypeDef
  • Init : MDIOS_HandleTypeDef , MDMA_LinkNodeConfTypeDef , __MDMA_HandleTypeDef , MMC_HandleTypeDef , NAND_HandleTypeDef , NOR_HandleTypeDef , OPAMP_HandleTypeDef , PCD_HandleTypeDef , QSPI_HandleTypeDef , RNG_HandleTypeDef , RTC_HandleTypeDef , __SAI_HandleTypeDef , SD_HandleTypeDef , SDRAM_HandleTypeDef , SMARTCARD_HandleTypeDef , SMBUS_HandleTypeDef , SPDIFRX_HandleTypeDef , __SPI_HandleTypeDef , SRAM_HandleTypeDef , SWPMI_HandleTypeDef , TIM_HandleTypeDef , UART_HandleTypeDef , ADC_HandleTypeDef , USART_HandleTypeDef , WWDG_HandleTypeDef , CEC_HandleTypeDef , COMP_HandleTypeDef , CRC_HandleTypeDef , CRYP_HandleTypeDef , DCMI_HandleTypeDef , DFSDM_Channel_HandleTypeDef , DFSDM_Filter_HandleTypeDef , __DMA_HandleTypeDef , __DMA2D_HandleTypeDef , ETH_HandleTypeDef , FDCAN_HandleTypeDef , HASH_HandleTypeDef , HCD_HandleTypeDef , __HRTIM_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , IRDA_HandleTypeDef , IWDG_HandleTypeDef , LPTIM_HandleTypeDef , LTDC_HandleTypeDef
  • InitRefTrigOffset : FDCAN_TT_ConfigTypeDef
  • InitValue : CRC_InitTypeDef
  • InjConvRemaining : DFSDM_Filter_HandleTypeDef
  • InjecOversampling : ADC_InjectionConfTypeDef
  • InjecOversamplingMode : ADC_InjectionConfTypeDef
  • InjectedChannel : ADC_InjectionConfTypeDef
  • InjectedChannelsNbr : DFSDM_Filter_HandleTypeDef
  • InjectedDiscontinuousConvMode : ADC_InjectionConfTypeDef
  • InjectedLeftBitShift : ADC_InjectionConfTypeDef
  • InjectedNbrOfConversion : ADC_InjectionConfTypeDef
  • InjectedOffset : ADC_InjectionConfTypeDef
  • InjectedOffsetNumber : ADC_InjectionConfTypeDef
  • InjectedOffsetRightShift : ADC_InjectionConfTypeDef
  • InjectedOffsetSignedSaturation : ADC_InjectionConfTypeDef
  • InjectedParam : DFSDM_Filter_InitTypeDef
  • InjectedRank : ADC_InjectionConfTypeDef
  • InjectedSamplingTime : ADC_InjectionConfTypeDef
  • InjectedScanMode : DFSDM_Filter_HandleTypeDef
  • InjectedSingleDiff : ADC_InjectionConfTypeDef
  • InjectedTrigger : DFSDM_Filter_HandleTypeDef
  • InjectionConfig : ADC_HandleTypeDef
  • InnerVlanCtrl : ETH_TxPacketConfig
  • InnerVlanTag : ETH_TxPacketConfig
  • InnerVLANTag : ETH_RxVLANConfigTypeDef
  • InnerVlanTag : ETH_RxPacketInfo
  • InnerVLANTagInStatus : ETH_RxVLANConfigTypeDef
  • Input : DFSDM_Channel_InitTypeDef
  • Input1Source : LPTIM_InitTypeDef
  • Input2Source : LPTIM_InitTypeDef
  • InputAlpha : DMA2D_LayerCfgTypeDef
  • InputColorMode : DMA2D_LayerCfgTypeDef
  • InputDataFormat : CRC_HandleTypeDef
  • InputDataInversionMode : CRC_InitTypeDef
  • InputOffset : DMA2D_LayerCfgTypeDef
  • InputSelection : SPDIFRX_InitTypeDef
  • InputTrigger : TIM_SlaveConfigTypeDef
  • Instance : IRDA_HandleTypeDef , SRAM_HandleTypeDef , FDCAN_HandleTypeDef , __SAI_HandleTypeDef , __DMA_HandleTypeDef , DCMI_HandleTypeDef , DAC_HandleTypeDef , NAND_HandleTypeDef , HCD_HandleTypeDef , SDRAM_HandleTypeDef , MDIOS_HandleTypeDef , OPAMP_HandleTypeDef , CRYP_HandleTypeDef , DFSDM_Filter_HandleTypeDef , __MDMA_HandleTypeDef , NOR_HandleTypeDef , __I2S_HandleTypeDef , __HRTIM_HandleTypeDef , JPEG_HandleTypeDef , SD_HandleTypeDef , MMC_HandleTypeDef , __I2C_HandleTypeDef , IWDG_HandleTypeDef , CRC_HandleTypeDef , COMP_HandleTypeDef , SMARTCARD_HandleTypeDef , ETH_HandleTypeDef , DFSDM_Channel_HandleTypeDef , WWDG_HandleTypeDef , RNG_HandleTypeDef , SMBUS_HandleTypeDef , __SPI_HandleTypeDef , SWPMI_HandleTypeDef , __DMA2D_HandleTypeDef , CEC_HandleTypeDef , ADC_HandleTypeDef , TIM_HandleTypeDef , LPTIM_HandleTypeDef , RTC_HandleTypeDef , UART_HandleTypeDef , PCD_HandleTypeDef , SPDIFRX_HandleTypeDef , QSPI_HandleTypeDef , USART_HandleTypeDef , LTDC_HandleTypeDef
  • Instruction : QSPI_CommandTypeDef
  • InstructionMode : QSPI_CommandTypeDef
  • InterPacketGapVal : ETH_MACConfigTypeDef
  • Interrupt : RTC_TamperTypeDef
  • InterruptRequests : HRTIM_TimerCfgTypeDef , HRTIM_TimerParamTypeDef
  • InterruptServiceRoutine : __SAI_HandleTypeDef
  • Interval : QSPI_AutoPollingTypeDef
  • IntOversampling : DFSDM_Filter_FilterParamTypeDef
  • InvertingInput : OPAMP_InitTypeDef , COMP_InitTypeDef
  • IOSwap : I2S_InitTypeDef , SPI_InitTypeDef
  • Ip4DestAddr : ETH_L3FilterConfigTypeDef
  • Ip4SrcAddr : ETH_L3FilterConfigTypeDef
  • Ip6Addr : ETH_L3FilterConfigTypeDef
  • IsBufferable : MPU_Region_InitTypeDef
  • IsCacheable : MPU_Region_InitTypeDef
  • IsCalibrationMsg : FDCAN_FilterTypeDef
  • IsFilterMatchingFrame : FDCAN_RxHeaderTypeDef
  • ISR : DMA_Base_Registers
  • IsShareable : MPU_Region_InitTypeDef
  • ItMode : ETH_RxDescListTypeDef
  • ITMode : ADC_AnalogWDGConfTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- j -

  • Jabber : ETH_MACConfigTypeDef
  • JpegInCount : JPEG_HandleTypeDef
  • JPEGMode : DCMI_InitTypeDef
  • JpegOutCount : JPEG_HandleTypeDef
  • JumboPacket : ETH_MACConfigTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- k -

  • KeySize : CRYP_ConfigTypeDef , HASH_InitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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- l -

  • L3FilterStatus : ETH_RxPacketInfo
  • L4FilterStatus : ETH_RxPacketInfo
  • LastErrorCode : FDCAN_ProtocolStatusTypeDef
  • LastLinkedListNodeAddress : __MDMA_HandleTypeDef
  • Latch : HRTIM_TimerEventFilteringCfgTypeDef
  • LayerCfg : __DMA2D_HandleTypeDef , LTDC_HandleTypeDef
  • LBPEErrorBitGen : CEC_InitTypeDef
  • LeftBitShift : ADC_InitTypeDef
  • LeftDelay : SAIEx_PdmMicDelayParamTypeDef
  • len : __ETH_BufferTypeDef
  • Length : ETH_TxPacketConfig
  • LineEndCode : DCMI_CodesInitTypeDef
  • LineSelectMode : DCMI_InitTypeDef
  • LineSelectStart : DCMI_InitTypeDef
  • LineStartCode : DCMI_CodesInitTypeDef
  • LinkedListNodeCounter : __MDMA_HandleTypeDef
  • ListenMode : CEC_InitTypeDef
  • Lock : HCD_HandleTypeDef , __HRTIM_HandleTypeDef , HRTIM_FaultCfgTypeDef , USART_HandleTypeDef , UART_HandleTypeDef , __I2C_HandleTypeDef , SWPMI_HandleTypeDef , SRAM_HandleTypeDef , __I2S_HandleTypeDef , IRDA_HandleTypeDef , SMBUS_HandleTypeDef , SMARTCARD_HandleTypeDef , SDRAM_HandleTypeDef , ADC_HandleTypeDef , __SAI_HandleTypeDef , RTC_HandleTypeDef , JPEG_HandleTypeDef , LPTIM_HandleTypeDef , PCD_HandleTypeDef , OPAMP_HandleTypeDef , NOR_HandleTypeDef , CEC_HandleTypeDef , MMC_HandleTypeDef , LTDC_HandleTypeDef , MDIOS_HandleTypeDef , COMP_HandleTypeDef , __MDMA_HandleTypeDef , CRC_HandleTypeDef , NAND_HandleTypeDef , CRYP_HandleTypeDef , DAC_HandleTypeDef , QSPI_HandleTypeDef , RNG_HandleTypeDef , DCMI_HandleTypeDef , HASH_HandleTypeDef , TIM_HandleTypeDef , FDCAN_HandleTypeDef , __SPI_HandleTypeDef , __DMA_HandleTypeDef , SD_HandleTypeDef , __DMA2D_HandleTypeDef , ETH_HandleTypeDef , SPDIFRX_HandleTypeDef , FLASH_ProcessTypeDef
  • LockLevel : TIM_BreakDeadTimeConfigTypeDef
  • LogBlockNbr : HAL_MMC_CardInfoTypeDef , HAL_SD_CardInfoTypeDef
  • LogBlockSize : HAL_MMC_CardInfoTypeDef , HAL_SD_CardInfoTypeDef
  • LoopbackMode : ETH_MACConfigTypeDef
  • LowBreakSignal : DFSDM_Filter_AwdParamTypeDef
  • LowPowerAutoWait : ADC_InitTypeDef
  • LowThreshold : ADC_AnalogWDGConfTypeDef , DFSDM_Filter_AwdParamTypeDef
  • lpm_active : PCD_HandleTypeDef
  • LPM_State : PCD_HandleTypeDef
  • Lptim1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lptim2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lptim3ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lptim4ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lptim5ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lpuart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • LSEState : RCC_OscInitTypeDef
  • LSIState : RCC_OscInitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- m -

  • MACAddr : ETH_InitTypeDef
  • MACErrorCode : ETH_HandleTypeDef
  • MacFilterStatus : ETH_RxPacketInfo
  • MACLPIEvent : ETH_HandleTypeDef
  • MACWakeUpEvent : ETH_HandleTypeDef
  • MagicPacket : ETH_PowerDownConfigTypeDef
  • Maker_Id : NAND_IDTypeDef
  • ManDeflECC : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • ManufactDate : HAL_MMC_CardCIDTypedef , HAL_SD_CardCIDTypedef
  • Manufacturer_Code : NOR_IDTypeDef
  • ManufacturerID : HAL_MMC_CardCIDTypedef , HAL_SD_CardCIDTypedef
  • Mask : QSPI_AutoPollingTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , IRDA_HandleTypeDef
  • MaskFlag : RTC_TamperTypeDef
  • MasterInterDataIdleness : SPI_InitTypeDef
  • MasterKeepIOState : I2S_InitTypeDef , SPI_InitTypeDef
  • MasterOutputTrigger : TIM_MasterConfigTypeDef
  • MasterOutputTrigger2 : TIM_MasterConfigTypeDef
  • MasterPriority : FDCAN_TTOperationStatusTypeDef
  • MasterReceiverAutoSusp : SPI_InitTypeDef
  • MasterSlaveMode : TIM_MasterConfigTypeDef
  • MasterSSIdleness : SPI_InitTypeDef
  • MasterState : FDCAN_TTOperationStatusTypeDef
  • Match : QSPI_AutoPollingTypeDef
  • MatchMode : QSPI_AutoPollingTypeDef
  • MaxBusClkFrec : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • MaximumSegmentSize : ETH_DMAConfigTypeDef
  • MaxRdCurrentVDDMax : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • MaxRdCurrentVDDMin : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • MaxSegmentSize : ETH_TxPacketConfig
  • MaxWrBlockLen : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • MaxWrCurrentVDDMax : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • MaxWrCurrentVDDMin : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • Mckdiv : SAI_InitTypeDef
  • MckOverSampling : SAI_InitTypeDef
  • MCLKOutput : I2S_InitTypeDef
  • MediaInterface : ETH_InitTypeDef
  • MemBurst : DMA_InitTypeDef
  • MemDataAlignment : DMA_InitTypeDef
  • MemInc : DMA_InitTypeDef
  • MessageIndex : FDCAN_HpMsgStatusTypeDef
  • MessageMarker : FDCAN_TxEventFifoTypeDef , FDCAN_TxHeaderTypeDef
  • MessageRAMOffset : FDCAN_InitTypeDef
  • MessageStorage : FDCAN_HpMsgStatusTypeDef
  • MicPair : SAIEx_PdmMicDelayParamTypeDef
  • MicPairsNbr : SAI_PdmInitTypeDef
  • MinOscClkPeriods : FDCAN_ClkCalUnitTypeDef
  • Minutes : RTC_TimeTypeDef
  • MmcCard : MMC_HandleTypeDef
  • Mode : ADC_MultiModeTypeDef , I2S_InitTypeDef , COMP_InitTypeDef , PWR_PVDTypeDef , HRTIM_SimpleOCChannelCfgTypeDef , USART_InitTypeDef , SMARTCARD_InitTypeDef , __I2C_HandleTypeDef , IRDA_InitTypeDef , DMA_InitTypeDef , UART_InitTypeDef , HRTIM_BurstModeCfgTypeDef , SPI_InitTypeDef , GPIO_InitTypeDef , DMA2D_InitTypeDef , HRTIM_TimeBaseCfgTypeDef , PWREx_AVDTypeDef , OPAMP_InitTypeDef , FDCAN_InitTypeDef
  • MonoStereoMode : SAI_InitTypeDef
  • Month : RTC_DateTypeDef
  • MSBFirst : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • msgRam : FDCAN_HandleTypeDef
  • Multiplexer : DFSDM_Channel_InputTypeDef
  • mutecallback : __SAI_HandleTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- n -

  • NACKEnable : SMARTCARD_InitTypeDef
  • NbData : QSPI_CommandTypeDef
  • NbrOfConversion : ADC_InitTypeDef
  • NbrOfDiscConversion : ADC_InitTypeDef
  • NbSectors : FLASH_EraseInitTypeDef
  • NbSectorsToErase : FLASH_ProcessTypeDef
  • next : __ETH_BufferTypeDef
  • NoDivider : SAI_InitTypeDef
  • NoErase : RTC_TamperTypeDef
  • NominalPrescaler : FDCAN_InitTypeDef
  • NominalSyncJumpWidth : FDCAN_InitTypeDef
  • NominalTimeSeg1 : FDCAN_InitTypeDef
  • NominalTimeSeg2 : FDCAN_InitTypeDef
  • NonInvertingInput : OPAMP_InitTypeDef , COMP_InitTypeDef
  • NoStretchMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • NSAC : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • NSS : SPI_InitTypeDef , USART_InitTypeDef
  • NSSPMode : SPI_InitTypeDef
  • NSSPolarity : SPI_InitTypeDef
  • Number : MPU_Region_InitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- o -

  • OCFastMode : TIM_OC_InitTypeDef
  • OCIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCMode : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCNIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCNPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OEM_AppliID : HAL_MMC_CardCIDTypedef , HAL_SD_CardCIDTypedef
  • Offset : ADC_ChannelConfTypeDef , DFSDM_Channel_InitTypeDef
  • OffsetNumber : ADC_ChannelConfTypeDef
  • OffsetRightShift : ADC_ChannelConfTypeDef
  • OffsetSignedSaturation : ADC_ChannelConfTypeDef
  • OffStateIDLEMode : TIM_BreakDeadTimeConfigTypeDef
  • OffStateRunMode : TIM_BreakDeadTimeConfigTypeDef
  • OneBitSampling : SMARTCARD_InitTypeDef , UART_InitTypeDef
  • OperationMode : FDCAN_TT_ConfigTypeDef
  • OptionType : FLASH_OBProgramInitTypeDef
  • OscillatorType : RCC_OscInitTypeDef
  • OUT_ep : PCD_HandleTypeDef
  • OutDataLength : JPEG_HandleTypeDef
  • OutPut : RTC_InitTypeDef
  • OutputClock : DFSDM_Channel_InitTypeDef
  • OutputDataInversionMode : CRC_InitTypeDef
  • OutputDrive : SAI_InitTypeDef
  • OutputIdleLevel : HRTIM_SimpleOnePulseChannelCfgTypeDef
  • OutputOffset : DMA2D_InitTypeDef
  • OutputPol : COMP_InitTypeDef
  • OutputPolarity : LPTIM_InitTypeDef
  • OutPutPolarity : RTC_InitTypeDef
  • OutputPolarity : HRTIM_SimpleOnePulseChannelCfgTypeDef
  • OutPutRemap : RTC_InitTypeDef
  • OutPutType : RTC_InitTypeDef
  • Overrun : ADC_InitTypeDef
  • OverrunDisable : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • Oversampling : DFSDM_Channel_AwdTypeDef , DFSDM_Filter_FilterParamTypeDef
  • OverSampling : UART_InitTypeDef
  • Oversampling : ADC_InitTypeDef
  • OversamplingMode : ADC_InitTypeDef
  • OversamplingStopReset : ADC_OversamplingTypeDef
  • OwnAddress : CEC_InitTypeDef
  • OwnAddress1 : SMBUS_InitTypeDef , I2C_InitTypeDef
  • OwnAddress2 : I2C_InitTypeDef , SMBUS_InitTypeDef
  • OwnAddress2Masks : SMBUS_InitTypeDef , I2C_InitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- p -

  • PacketErrorCheckMode : SMBUS_InitTypeDef
  • Page : NAND_AddressTypeDef
  • PageSize : NAND_DeviceConfigTypeDef
  • Parent : __DMA_HandleTypeDef , __MDMA_HandleTypeDef
  • Parity : UART_InitTypeDef , USART_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef
  • ParityErrorMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • PartBlockRead : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • PassAllMulticast : ETH_MACFilterConfigTypeDef
  • PauseLowThreshold : ETH_MACConfigTypeDef
  • PauseTime : ETH_MACConfigTypeDef
  • PayloadLen : ETH_TxPacketConfig
  • PayloadType : ETH_RxPacketInfo
  • PBLx8Mode : ETH_DMAConfigTypeDef
  • pBuffPtr : DCMI_HandleTypeDef , __I2C_HandleTypeDef , __SAI_HandleTypeDef , SMBUS_HandleTypeDef
  • PCKPolarity : DCMI_InitTypeDef
  • pCLUT : DMA2D_CLUTCfgTypeDef
  • PCPolarity : LTDC_InitTypeDef
  • PCROPConfig : FLASH_OBProgramInitTypeDef
  • PCROPEndAddr : FLASH_OBProgramInitTypeDef
  • PCROPStartAddr : FLASH_OBProgramInitTypeDef
  • pCrypInBuffPtr : CRYP_HandleTypeDef
  • pCrypOutBuffPtr : CRYP_HandleTypeDef
  • pCsBuffPtr : SPDIFRX_HandleTypeDef
  • pData : HCD_HandleTypeDef , PCD_HandleTypeDef
  • PdmInit : SAI_InitTypeDef
  • PerformanceMove : HAL_SD_CardStatusTypedef
  • Period : HRTIM_TimeBaseCfgTypeDef , HRTIM_BurstModeCfgTypeDef , TIM_Base_InitTypeDef
  • PeriphBurst : DMA_InitTypeDef
  • PeriphClockSelection : RCC_PeriphCLKInitTypeDef
  • PeriphDataAlignment : DMA_InitTypeDef
  • PeripheralMode : SMBUS_InitTypeDef
  • PeriphInc : DMA_InitTypeDef
  • PermWrProtect : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • PgaConnect : OPAMP_InitTypeDef
  • PgaGain : OPAMP_InitTypeDef
  • Phase : CRYP_HandleTypeDef , HASH_HandleTypeDef
  • PhaseLock : FDCAN_TTOperationStatusTypeDef
  • pHashInBuffPtr : HASH_HandleTypeDef
  • pHashKeyBuffPtr : HASH_HandleTypeDef
  • pHashMsgBuffPtr : HASH_HandleTypeDef
  • pHashOutBuffPtr : HASH_HandleTypeDef
  • Pin : GPIO_InitTypeDef
  • pInitVect : CRYP_ConfigTypeDef
  • PinPolarity : PWREx_WakeupPinTypeDef
  • PinPull : PWREx_WakeupPinTypeDef
  • Pins : DFSDM_Channel_InputTypeDef
  • PixelFormat : LTDC_LayerCfgTypeDef
  • pJpegInBuffPtr : JPEG_HandleTypeDef
  • pJpegOutBuffPtr : JPEG_HandleTypeDef
  • pKey : CRYP_ConfigTypeDef , HASH_InitTypeDef
  • Plane : NAND_AddressTypeDef
  • PlaneNbr : NAND_DeviceConfigTypeDef
  • PlaneSize : NAND_DeviceConfigTypeDef
  • PLL : RCC_OscInitTypeDef
  • PLL1_P_Frequency : PLL1_ClocksTypeDef
  • PLL1_Q_Frequency : PLL1_ClocksTypeDef
  • PLL1_R_Frequency : PLL1_ClocksTypeDef
  • PLL2 : RCC_PeriphCLKInitTypeDef
  • PLL2_P_Frequency : PLL2_ClocksTypeDef
  • PLL2_Q_Frequency : PLL2_ClocksTypeDef
  • PLL2_R_Frequency : PLL2_ClocksTypeDef
  • PLL2FRACN : RCC_PLL2InitTypeDef
  • PLL2M : RCC_PLL2InitTypeDef
  • PLL2N : RCC_PLL2InitTypeDef
  • PLL2P : RCC_PLL2InitTypeDef
  • PLL2Q : RCC_PLL2InitTypeDef
  • PLL2R : RCC_PLL2InitTypeDef
  • PLL2RGE : RCC_PLL2InitTypeDef
  • PLL2VCOSEL : RCC_PLL2InitTypeDef
  • PLL3 : RCC_PeriphCLKInitTypeDef
  • PLL3_P_Frequency : PLL3_ClocksTypeDef
  • PLL3_Q_Frequency : PLL3_ClocksTypeDef
  • PLL3_R_Frequency : PLL3_ClocksTypeDef
  • PLL3FRACN : RCC_PLL3InitTypeDef
  • PLL3M : RCC_PLL3InitTypeDef
  • PLL3N : RCC_PLL3InitTypeDef
  • PLL3P : RCC_PLL3InitTypeDef
  • PLL3Q : RCC_PLL3InitTypeDef
  • PLL3R : RCC_PLL3InitTypeDef
  • PLL3RGE : RCC_PLL3InitTypeDef
  • PLL3VCOSEL : RCC_PLL3InitTypeDef
  • PLLFRACN : RCC_PLLInitTypeDef
  • PLLM : RCC_PLLInitTypeDef
  • PLLN : RCC_PLLInitTypeDef
  • PLLP : RCC_PLLInitTypeDef
  • PLLQ : RCC_PLLInitTypeDef
  • PLLR : RCC_PLLInitTypeDef
  • PLLRGE : RCC_PLLInitTypeDef
  • PLLSource : RCC_PLLInitTypeDef
  • PLLState : RCC_PLLInitTypeDef
  • PLLVCOSEL : RCC_PLLInitTypeDef
  • Polarity : HAL_DMA_MuxRequestGeneratorConfigTypeDef , HRTIM_EventCfgTypeDef , HRTIM_SimpleOCChannelCfgTypeDef , HRTIM_SimplePWMChannelCfgTypeDef , HRTIM_OutputCfgTypeDef , HRTIM_FaultCfgTypeDef , LPTIM_ULPClockConfigTypeDef , RCC_CRSInitTypeDef , TIMEx_BreakInputConfigTypeDef
  • PortAddress : MDIOS_InitTypeDef
  • PostRequestMaskAddress : MDMA_LinkNodeConfTypeDef
  • PostRequestMaskData : MDMA_LinkNodeConfTypeDef
  • PowerMode : IRDA_InitTypeDef , OPAMP_InitTypeDef
  • PreambleCheck : MDIOS_InitTypeDef
  • PreambleLength : ETH_MACConfigTypeDef
  • PreambleTypeMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • PrechargeDuration : RTC_TamperTypeDef
  • PreloadEnable : HRTIM_BurstModeCfgTypeDef , HRTIM_TimerCfgTypeDef
  • Prescaler : RCC_CRSInitTypeDef , HRTIM_DeadTimeCfgTypeDef , HRTIM_BurstModeCfgTypeDef , IRDA_InitTypeDef , LPTIM_ClockConfigTypeDef , UART_InitTypeDef , WWDG_InitTypeDef , USART_InitTypeDef , SMARTCARD_InitTypeDef , TIM_Base_InitTypeDef , IWDG_InitTypeDef
  • PrescalerRatio : HRTIM_TimeBaseCfgTypeDef
  • PreviousState : __I2C_HandleTypeDef , SMBUS_HandleTypeDef
  • Priority : DMA_InitTypeDef , MDMA_InitTypeDef
  • ProcedureOnGoing : FLASH_ProcessTypeDef
  • ProdName1 : HAL_SD_CardCIDTypedef , HAL_MMC_CardCIDTypedef
  • ProdName2 : HAL_SD_CardCIDTypedef , HAL_MMC_CardCIDTypedef
  • ProdRev : HAL_SD_CardCIDTypedef , HAL_MMC_CardCIDTypedef
  • ProdSN : HAL_SD_CardCIDTypedef , HAL_MMC_CardCIDTypedef
  • ProgrammableWatchdog : ETH_MACConfigTypeDef
  • PromiscuousMode : ETH_MACFilterConfigTypeDef
  • ProtectedAreaSize : HAL_SD_CardStatusTypedef
  • Protocol : ETH_L4FilterConfigTypeDef , SAI_InitTypeDef , ETH_L3FilterConfigTypeDef
  • ProtocolException : FDCAN_ProtocolStatusTypeDef , FDCAN_InitTypeDef
  • pRxBuffPtr : MMC_HandleTypeDef , __SPI_HandleTypeDef , __I2S_HandleTypeDef , QSPI_HandleTypeDef , SMARTCARD_HandleTypeDef , USART_HandleTypeDef , IRDA_HandleTypeDef , SPDIFRX_HandleTypeDef , SWPMI_HandleTypeDef , UART_HandleTypeDef , SD_HandleTypeDef
  • pTxBuffPtr : SWPMI_HandleTypeDef , UART_HandleTypeDef , __SPI_HandleTypeDef , IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , __I2S_HandleTypeDef , USART_HandleTypeDef , MMC_HandleTypeDef , CEC_HandleTypeDef , QSPI_HandleTypeDef , SD_HandleTypeDef
  • Pull : GPIO_InitTypeDef
  • Pulse : TIM_OnePulse_InitTypeDef , HRTIM_SimpleOCChannelCfgTypeDef , HRTIM_SimplePWMChannelCfgTypeDef , TIM_OC_InitTypeDef , HRTIM_SimpleOnePulseChannelCfgTypeDef
  • PushPull : HRTIM_TimerCfgTypeDef
  • PVDLevel : PWR_PVDTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- q -

  • QspiClockSelection : RCC_PeriphCLKInitTypeDef
  • QuantTable0 : JPEG_HandleTypeDef
  • QuantTable1 : JPEG_HandleTypeDef
  • QuantTable2 : JPEG_HandleTypeDef
  • QuantTable3 : JPEG_HandleTypeDef
  • QueueInjectedContext : ADC_InjectionConfTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- r -

  • RandomNumber : RNG_HandleTypeDef
  • Rank : ADC_ChannelConfTypeDef
  • Ratio : ADC_InjOversamplingTypeDef , ADC_OversamplingTypeDef
  • RdBlockLen : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • RdBlockMisalign : HAL_SD_CardCSDTypedef , HAL_MMC_CardCSDTypeDef
  • RDPLevel : FLASH_OBProgramInitTypeDef
  • RebuildINCRxBurst : ETH_DMAConfigTypeDef
  • ReceiveAllMode : ETH_MACFilterConfigTypeDef
  • ReceiveFlowControl : ETH_MACConfigTypeDef
  • ReceiveOwn : ETH_MACConfigTypeDef
  • ReceiveQueueMode : ETH_MACConfigTypeDef
  • Red : LTDC_ColorTypeDef , DMA2D_ColorTypeDef
  • RedBlueSwap : DMA2D_InitTypeDef , DMA2D_LayerCfgTypeDef
  • RefTrigOffset : FDCAN_TTOperationStatusTypeDef
  • RegularContMode : DFSDM_Filter_HandleTypeDef
  • RegularParam : DFSDM_Filter_InitTypeDef
  • RegularTrigger : DFSDM_Filter_HandleTypeDef
  • RelCardAdd : HAL_MMC_CardInfoTypeDef , HAL_SD_CardInfoTypeDef
  • Reload : IWDG_InitTypeDef
  • ReloadValue : RCC_CRSInitTypeDef , RCC_CRSSynchroInfoTypeDef
  • RepeatFactor : FDCAN_TriggerTypeDef
  • RepetitionCounter : HRTIM_TimeBaseCfgTypeDef , TIM_Base_InitTypeDef
  • RepetitionUpdate : HRTIM_TimerCfgTypeDef
  • Request : DMA_InitTypeDef , MDMA_InitTypeDef
  • RequestNumber : HAL_DMA_MuxSyncConfigTypeDef , HAL_DMA_MuxRequestGeneratorConfigTypeDef
  • Reserved : LTDC_ColorTypeDef , MDMA_LinkNodeTypeDef
  • Reserved0 : DMA_Base_Registers
  • Reserved1 : HAL_MMC_CardCSDTypeDef , HAL_MMC_CardCIDTypedef , HAL_SD_CardCSDTypedef , HAL_SD_CardCIDTypedef
  • Reserved2 : HAL_MMC_CardCSDTypeDef , HAL_MMC_CardCIDTypedef , HAL_SD_CardCSDTypedef , HAL_SD_CardCIDTypedef
  • Reserved3 : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • Reserved4 : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • ResetOnSync : HRTIM_TimerCfgTypeDef
  • ResetSource : HRTIM_OutputCfgTypeDef
  • ResetTrigger : HRTIM_TimerCfgTypeDef
  • ResetUpdate : HRTIM_TimerCfgTypeDef
  • Resolution : ADC_InitTypeDef
  • Retries : SPDIFRX_InitTypeDef
  • RetryTransmission : ETH_MACConfigTypeDef
  • RightBitShift : ADC_OversamplingTypeDef , ADC_InjOversamplingTypeDef , DFSDM_Channel_InitTypeDef
  • RightDelay : SAIEx_PdmMicDelayParamTypeDef
  • RisingLock : HRTIM_DeadTimeCfgTypeDef
  • RisingSign : HRTIM_DeadTimeCfgTypeDef
  • RisingSignLock : HRTIM_DeadTimeCfgTypeDef
  • RisingValue : HRTIM_DeadTimeCfgTypeDef
  • RngClockSelection : RCC_PeriphCLKInitTypeDef
  • RTCClockSelection : RCC_PeriphCLKInitTypeDef
  • RxBRSflag : FDCAN_ProtocolStatusTypeDef
  • RxBuffer : CEC_InitTypeDef
  • RxBufferIndex : FDCAN_FilterTypeDef
  • RxBufferingMode : SWPMI_InitTypeDef
  • RxBufferSA : FDCAN_MsgRamAddressTypeDef
  • RxBufferSize : FDCAN_InitTypeDef
  • RxBuffersNbr : FDCAN_InitTypeDef
  • RxBuffLen : ETH_InitTypeDef
  • RxCRCInitializationPattern : SPI_InitTypeDef
  • RxDesc : ETH_RxDescListTypeDef , ETH_InitTypeDef
  • RxDescList : ETH_HandleTypeDef
  • RxDMABurstLength : ETH_DMAConfigTypeDef
  • RxErrorCnt : FDCAN_ErrorCountersTypeDef
  • RxErrorPassive : FDCAN_ErrorCountersTypeDef
  • RxESIflag : FDCAN_ProtocolStatusTypeDef
  • RxFDFflag : FDCAN_ProtocolStatusTypeDef
  • RxFifo0ElmtSize : FDCAN_InitTypeDef
  • RxFifo0ElmtsNbr : FDCAN_InitTypeDef
  • RxFIFO0SA : FDCAN_MsgRamAddressTypeDef
  • RxFifo1ElmtSize : FDCAN_InitTypeDef
  • RxFifo1ElmtsNbr : FDCAN_InitTypeDef
  • RxFIFO1SA : FDCAN_MsgRamAddressTypeDef
  • RXFIFOThreshold : USART_InitTypeDef , UART_InitTypeDef , SMARTCARD_InitTypeDef
  • RxFrameType : FDCAN_RxHeaderTypeDef
  • RxISR : __SPI_HandleTypeDef , __I2S_HandleTypeDef
  • RxPinLevelInvert : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • RxState : ETH_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef , IRDA_HandleTypeDef , CEC_HandleTypeDef
  • RxTimestamp : FDCAN_RxHeaderTypeDef
  • RxXferCount : SWPMI_HandleTypeDef , QSPI_HandleTypeDef , __SPI_HandleTypeDef , IRDA_HandleTypeDef , __I2S_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , SPDIFRX_HandleTypeDef
  • RxXferSize : QSPI_HandleTypeDef , USART_HandleTypeDef , SPDIFRX_HandleTypeDef , MMC_HandleTypeDef , SMARTCARD_HandleTypeDef , IRDA_HandleTypeDef , __SPI_HandleTypeDef , SD_HandleTypeDef , SWPMI_HandleTypeDef , __I2S_HandleTypeDef , UART_HandleTypeDef , CEC_HandleTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- s -

  • Sai1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Sai2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Sai3ClockSelection : RCC_PeriphCLKInitTypeDef
  • Sai4AClockSelection : RCC_PeriphCLKInitTypeDef
  • Sai4BClockSelection : RCC_PeriphCLKInitTypeDef
  • SampleShifting : QSPI_InitTypeDef
  • SampleTime : LPTIM_TriggerConfigTypeDef , LPTIM_ULPClockConfigTypeDef
  • SamplingFrequency : RTC_TamperTypeDef
  • SamplingTime : ADC_ChannelConfTypeDef
  • ScanConvMode : ADC_InitTypeDef
  • ScanMode : DFSDM_Filter_InjectedParamTypeDef
  • SdCard : SD_HandleTypeDef
  • SdmmcClockSelection : RCC_PeriphCLKInitTypeDef
  • SecondFraction : RTC_TimeTypeDef
  • SecondPacketOperate : ETH_DMAConfigTypeDef
  • Seconds : RTC_TimeTypeDef
  • Sector : FLASH_ProcessTypeDef , FLASH_EraseInitTypeDef
  • SecureAreaConfig : FLASH_OBProgramInitTypeDef
  • SecureAreaEndAddr : FLASH_OBProgramInitTypeDef
  • SecureAreaStartAddr : FLASH_OBProgramInitTypeDef
  • SecuredMode : HAL_SD_CardStatusTypedef
  • SegmentCnt : ETH_RxPacketInfo
  • Selection : DFSDM_Channel_OutputClockTypeDef
  • Sensitivity : HRTIM_EventCfgTypeDef
  • SerialInterface : DFSDM_Channel_InitTypeDef
  • SetSource : HRTIM_OutputCfgTypeDef
  • Setup : PCD_HandleTypeDef
  • SignalFreeTime : CEC_InitTypeDef
  • SignalFreeTimeOption : CEC_InitTypeDef
  • SignalID : HAL_DMA_MuxRequestGeneratorConfigTypeDef
  • SincOrder : DFSDM_Filter_FilterParamTypeDef
  • SingleDiff : ADC_ChannelConfTypeDef
  • SIOOMode : QSPI_CommandTypeDef
  • Size : MPU_Region_InitTypeDef , CRYP_HandleTypeDef , DMA2D_CLUTCfgTypeDef
  • SlaveExtendFREDetection : I2S_InitTypeDef
  • SlaveMode : TIM_SlaveConfigTypeDef , USART_InitTypeDef
  • SlotActive : SAI_SlotInitTypeDef
  • SlotInit : __SAI_HandleTypeDef
  • SlotNumber : SAI_SlotInitTypeDef
  • SlotSize : SAI_SlotInitTypeDef
  • SlowProtocolDetect : ETH_MACConfigTypeDef
  • SMBusTimeout : SMBUS_InitTypeDef
  • Source : HRTIM_EventCfgTypeDef , HRTIM_FaultCfgTypeDef , LPTIM_ClockConfigTypeDef , LPTIM_TriggerConfigTypeDef , RCC_CRSInitTypeDef , TIMEx_BreakInputConfigTypeDef
  • SourceAddrControl : ETH_MACConfigTypeDef
  • SourceBlockAddressOffset : MDMA_InitTypeDef
  • SourceBurst : MDMA_InitTypeDef
  • SourceDataSize : MDMA_InitTypeDef
  • SourceInc : MDMA_InitTypeDef
  • SourcePort : ETH_L4FilterConfigTypeDef
  • SourceTxDesc : ETH_TxVLANConfigTypeDef
  • SpareAreaSize : NAND_DeviceConfigTypeDef
  • SpdifrxClockSelection : RCC_PeriphCLKInitTypeDef
  • Speed : GPIO_InitTypeDef , ETH_MACConfigTypeDef
  • SpeedClass : HAL_SD_CardStatusTypedef
  • Spi1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Spi2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Spi3ClockSelection : RCC_PeriphCLKInitTypeDef
  • Spi4ClockSelection : RCC_PeriphCLKInitTypeDef
  • Spi5ClockSelection : RCC_PeriphCLKInitTypeDef
  • Spi6ClockSelection : RCC_PeriphCLKInitTypeDef
  • SpiClock : DFSDM_Channel_SerialInterfaceTypeDef
  • SrcAddrCtrl : ETH_TxPacketConfig
  • SrcAddress : MDMA_LinkNodeConfTypeDef
  • SrcAddrFiltering : ETH_MACFilterConfigTypeDef
  • SrcAddrFilterMatch : ETH_L3FilterConfigTypeDef
  • SrcAddrHigherBitsMatch : ETH_L3FilterConfigTypeDef
  • SrcAddrInverseFiltering : ETH_MACFilterConfigTypeDef
  • SrcPortFilterMatch : ETH_L4FilterConfigTypeDef
  • Standard : I2S_InitTypeDef
  • StandardFilterSA : FDCAN_MsgRamAddressTypeDef
  • StartCycle : FDCAN_TriggerTypeDef
  • StartOnSync : HRTIM_TimerCfgTypeDef
  • StartPulse : HRTIM_ChopperModeCfgTypeDef
  • State : __I2C_HandleTypeDef , JPEG_HandleTypeDef , FDCAN_HandleTypeDef , DFSDM_Channel_HandleTypeDef , __DMA_HandleTypeDef , CRC_HandleTypeDef , SWPMI_HandleTypeDef , ADC_HandleTypeDef , COMP_HandleTypeDef , CRYP_HandleTypeDef , DAC_HandleTypeDef , DCMI_HandleTypeDef , USART_HandleTypeDef , DFSDM_Filter_HandleTypeDef , __DMA2D_HandleTypeDef , LTDC_HandleTypeDef , SPDIFRX_HandleTypeDef , HASH_HandleTypeDef , HCD_HandleTypeDef , __HRTIM_HandleTypeDef , __SPI_HandleTypeDef , TIM_HandleTypeDef , __I2S_HandleTypeDef , LPTIM_HandleTypeDef , SDRAM_HandleTypeDef , SMBUS_HandleTypeDef , MDIOS_HandleTypeDef , PCD_HandleTypeDef , __MDMA_HandleTypeDef , MMC_HandleTypeDef , SD_HandleTypeDef , NOR_HandleTypeDef , RNG_HandleTypeDef , RTC_HandleTypeDef , __SAI_HandleTypeDef , QSPI_HandleTypeDef , OPAMP_HandleTypeDef , SRAM_HandleTypeDef , NAND_HandleTypeDef
  • Status : OPAMP_HandleTypeDef , LPTIM_HandleTypeDef , HASH_HandleTypeDef
  • StatusBytesSize : QSPI_AutoPollingTypeDef
  • StdFiltersNbr : FDCAN_InitTypeDef
  • StereoMode : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • StopBits : UART_InitTypeDef , USART_InitTypeDef , SMARTCARD_InitTypeDef
  • StopWatchTrigSel : FDCAN_TT_ConfigTypeDef
  • StoreOperation : RTC_TimeTypeDef
  • StreamBaseAddress : __DMA_HandleTypeDef
  • StreamIndex : __DMA_HandleTypeDef
  • StripInnerVLANTag : ETH_RxVLANConfigTypeDef
  • StripVLANTag : ETH_RxVLANConfigTypeDef
  • SubRegionDisable : MPU_Region_InitTypeDef
  • SubSeconds : RTC_TimeTypeDef
  • Support2KPacket : ETH_MACConfigTypeDef
  • SuspendRequest : HASH_HandleTypeDef
  • SVLANType : ETH_TxVLANConfigTypeDef
  • Swap : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • Swpmi1ClockSelection : RCC_PeriphCLKInitTypeDef
  • SyncDevLimit : FDCAN_TT_ConfigTypeDef
  • SyncEnable : HAL_DMA_MuxSyncConfigTypeDef
  • SynchPrediv : RTC_InitTypeDef
  • Synchro : SAI_InitTypeDef
  • SynchroExt : SAI_InitTypeDef
  • SynchroMode : DCMI_InitTypeDef
  • SyncInputSource : HRTIM_InitTypeDef
  • SyncOptions : HRTIM_InitTypeDef
  • SyncOutputPolarity : HRTIM_InitTypeDef
  • SyncOutputSource : HRTIM_InitTypeDef
  • SyncPolarity : HAL_DMA_MuxSyncConfigTypeDef
  • SyncroCode : DCMI_InitTypeDef
  • SyncSignalID : HAL_DMA_MuxSyncConfigTypeDef
  • SyncState : FDCAN_TTOperationStatusTypeDef
  • SYSCLKDivider : RCC_ClkInitTypeDef
  • SYSCLKSource : RCC_ClkInitTypeDef
  • SysSpecVersion : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- t -

  • TAAC : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • Tamper : RTC_TamperTypeDef
  • TamperPullUp : RTC_TamperTypeDef
  • TCPHeaderLen : ETH_TxPacketConfig
  • TCPSegmentation : ETH_DMAConfigTypeDef
  • TDCvalue : FDCAN_ProtocolStatusTypeDef
  • TempWrProtect : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • Third_Id : NAND_IDTypeDef
  • TimeFormat : RTC_TimeTypeDef
  • TimeMark : FDCAN_TriggerTypeDef
  • TimeMaster : FDCAN_TT_ConfigTypeDef
  • Timeout : QSPI_HandleTypeDef
  • TimeOutActivation : QSPI_MemoryMappedTypeDef
  • TimeOutEnable : SMARTCARD_InitTypeDef
  • TimeOutPeriod : QSPI_MemoryMappedTypeDef
  • TimeOutValue : SMARTCARD_InitTypeDef
  • TimeQuantaPerBitTime : FDCAN_ClkCalUnitTypeDef
  • TimerParam : __HRTIM_HandleTypeDef
  • TimeStampOnTamperDetection : RTC_TamperTypeDef
  • Timing : I2C_InitTypeDef , SMBUS_InitTypeDef
  • TIMode : SPI_InitTypeDef
  • TIMPresSelection : RCC_PeriphCLKInitTypeDef
  • TmEventExt : FDCAN_TriggerTypeDef
  • TmEventInt : FDCAN_TriggerTypeDef
  • Tolerance : CEC_InitTypeDef
  • TotalHeigh : LTDC_InitTypeDef
  • TotalWidth : LTDC_InitTypeDef
  • TransferTriggerMode : MDMA_InitTypeDef
  • TransmitFlowControl : ETH_MACConfigTypeDef
  • TransmitPause : FDCAN_InitTypeDef
  • TransmitQueueMode : ETH_MACConfigTypeDef
  • Trigger : DFSDM_Filter_RegularParamTypeDef , DFSDM_Filter_InjectedParamTypeDef , HRTIM_CaptureCfgTypeDef , HRTIM_BurstModeCfgTypeDef , HRTIM_ADCTriggerCfgTypeDef , LPTIM_InitTypeDef , RTC_TamperTypeDef
  • TriggeredMode : ADC_OversamplingTypeDef
  • TriggerFilter : TIM_SlaveConfigTypeDef
  • TriggerIndex : FDCAN_TriggerTypeDef
  • TriggerMemoryNbr : FDCAN_TT_ConfigTypeDef
  • TriggerMode : COMP_InitTypeDef
  • TriggerPolarity : TIM_SlaveConfigTypeDef
  • TriggerPrescaler : TIM_SlaveConfigTypeDef
  • TriggerType : FDCAN_TriggerTypeDef
  • TrimmingValueN : OPAMP_InitTypeDef
  • TrimmingValueNHighSpeed : OPAMP_InitTypeDef
  • TrimmingValueP : OPAMP_InitTypeDef
  • TrimmingValuePHighSpeed : OPAMP_InitTypeDef
  • TriState : SAI_InitTypeDef
  • ttcan : FDCAN_HandleTypeDef
  • TTMemorySA : FDCAN_MsgRamAddressTypeDef
  • TURDenominator : FDCAN_TT_ConfigTypeDef
  • TURNumerator : FDCAN_TT_ConfigTypeDef
  • TwoSamplingDelay : ADC_MultiModeTypeDef
  • TxBuffer : ETH_TxPacketConfig
  • TxBufferIndex : FDCAN_TriggerTypeDef
  • TxBufferingMode : SWPMI_InitTypeDef
  • TxBufferSA : FDCAN_MsgRamAddressTypeDef
  • TxBuffersNbr : FDCAN_InitTypeDef
  • TxCompletionIndication : SMARTCARD_AdvFeatureInitTypeDef
  • TxCRCInitializationPattern : SPI_InitTypeDef
  • TxDesc : ETH_TxDescListTypeDef , ETH_InitTypeDef
  • TxDescList : ETH_HandleTypeDef
  • TxDMABurstLength : ETH_DMAConfigTypeDef
  • TxElmtSize : FDCAN_InitTypeDef
  • TxEnableWindow : FDCAN_TT_ConfigTypeDef
  • TxErrorCnt : FDCAN_ErrorCountersTypeDef
  • TxEventFifoControl : FDCAN_TxHeaderTypeDef
  • TxEventFIFOSA : FDCAN_MsgRamAddressTypeDef
  • TxEventsNbr : FDCAN_InitTypeDef
  • TxFIFOQSA : FDCAN_MsgRamAddressTypeDef
  • TxFifoQueueElmtsNbr : FDCAN_InitTypeDef
  • TxFifoQueueMode : FDCAN_InitTypeDef
  • TXFIFOThreshold : USART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef
  • TxFrameType : FDCAN_TxEventFifoTypeDef , FDCAN_TxHeaderTypeDef
  • TxISR : __I2S_HandleTypeDef , __SPI_HandleTypeDef
  • TxPinLevelInvert : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • TxTimestamp : FDCAN_TxEventFifoTypeDef
  • TxXferCount : IRDA_HandleTypeDef , USART_HandleTypeDef , __SPI_HandleTypeDef , QSPI_HandleTypeDef , CEC_HandleTypeDef , UART_HandleTypeDef , __I2S_HandleTypeDef , SMARTCARD_HandleTypeDef , SWPMI_HandleTypeDef
  • TxXferSize : MMC_HandleTypeDef , IRDA_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef , SD_HandleTypeDef , QSPI_HandleTypeDef , USART_HandleTypeDef , SWPMI_HandleTypeDef , __I2S_HandleTypeDef , SMARTCARD_HandleTypeDef
  • Type : DFSDM_Channel_SerialInterfaceTypeDef
  • TypeErase : FLASH_EraseInitTypeDef
  • TypeExtField : MPU_Region_InitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • Uart4ClockSelection : RCC_PeriphCLKInitTypeDef
  • Uart5ClockSelection : RCC_PeriphCLKInitTypeDef
  • UART7ClockSelection : RCC_PeriphCLKInitTypeDef
  • UART8ClockSelection : RCC_PeriphCLKInitTypeDef
  • UltraLowPowerClock : LPTIM_InitTypeDef
  • UnicastPausePacketDetect : ETH_MACConfigTypeDef
  • UnicastSlowProtocolPacketDetect : ETH_MACConfigTypeDef
  • UpdateGating : HRTIM_TimerCfgTypeDef
  • UpdateMode : LPTIM_InitTypeDef
  • UpdateSource : HRTIM_ADCTriggerCfgTypeDef
  • UpdateTrigger : HRTIM_TimerCfgTypeDef
  • Usart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart3ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart6ClockSelection : RCC_PeriphCLKInitTypeDef
  • UsbClockSelection : RCC_PeriphCLKInitTypeDef
  • USERConfig : FLASH_OBProgramInitTypeDef
  • UserTrimming : OPAMP_InitTypeDef
  • USERType : FLASH_OBProgramInitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- v -

  • ValidityBitMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • VerticalSync : LTDC_InitTypeDef
  • VlanCtrl : ETH_TxPacketConfig
  • VlanTag : ETH_TxPacketConfig , ETH_RxPacketInfo
  • VLANTagControl : ETH_TxVLANConfigTypeDef
  • VLANTagHashTableMatch : ETH_RxVLANConfigTypeDef
  • VLANTagInStatus : ETH_RxVLANConfigTypeDef
  • VLANTagInverceMatch : ETH_RxVLANConfigTypeDef
  • VLANTypeCheck : ETH_RxVLANConfigTypeDef
  • VoltageClass : SWPMI_InitTypeDef
  • VoltageForErase : FLASH_ProcessTypeDef
  • VoltageRange : FLASH_EraseInitTypeDef
  • VSPolarity : DCMI_InitTypeDef , LTDC_InitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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  • WaitForActivity : SPDIFRX_InitTypeDef
  • WaitForEvt : FDCAN_TTOperationStatusTypeDef
  • WakeUpEvent : UART_WakeUpTypeDef
  • WakeUpForward : ETH_PowerDownConfigTypeDef
  • WakeUpPacket : ETH_PowerDownConfigTypeDef
  • WakeUpPin : PWREx_WakeupPinTypeDef
  • Warning : FDCAN_ProtocolStatusTypeDef
  • Watchdog : ETH_MACConfigTypeDef
  • WatchdogMode : ADC_AnalogWDGConfTypeDef
  • WatchdogNumber : ADC_AnalogWDGConfTypeDef
  • WatchdogStartValue : FDCAN_ClkCalUnitTypeDef
  • WatchdogTimeout : ETH_MACConfigTypeDef
  • WeekDay : RTC_DateTypeDef
  • Window : IWDG_InitTypeDef , WWDG_InitTypeDef
  • WindowMode : COMP_InitTypeDef
  • WindowX0 : LTDC_LayerCfgTypeDef
  • WindowX1 : LTDC_LayerCfgTypeDef
  • WindowY0 : LTDC_LayerCfgTypeDef
  • WindowY1 : LTDC_LayerCfgTypeDef
  • WordLength : UART_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef , USART_InitTypeDef
  • WrBlockMisalign : HAL_MMC_CardCSDTypeDef , HAL_SD_CardCSDTypedef
  • WriteBlockPaPartial : HAL_SD_CardCSDTypedef , HAL_MMC_CardCSDTypeDef
  • WrProtectGrEnable : HAL_SD_CardCSDTypedef , HAL_MMC_CardCSDTypeDef
  • WrProtectGrSize : HAL_SD_CardCSDTypedef , HAL_MMC_CardCSDTypeDef
  • WRPSector : FLASH_OBProgramInitTypeDef
  • WRPState : FLASH_OBProgramInitTypeDef
  • WrSpeedFact : HAL_SD_CardCSDTypedef , HAL_MMC_CardCSDTypeDef
  • WSInversion : I2S_InitTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

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  • Data Fields
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  • XferAbortCallback : __DMA_HandleTypeDef , __MDMA_HandleTypeDef
  • XferBlockCpltCallback : __MDMA_HandleTypeDef
  • XferBufferCpltCallback : __MDMA_HandleTypeDef
  • XferCount : SMBUS_HandleTypeDef , DCMI_HandleTypeDef , __I2C_HandleTypeDef , __SAI_HandleTypeDef
  • XferCpltCallback : __DMA_HandleTypeDef , __DMA2D_HandleTypeDef , __MDMA_HandleTypeDef
  • XferErrorCallback : __DMA_HandleTypeDef , __DMA2D_HandleTypeDef , __MDMA_HandleTypeDef
  • XferHalfCpltCallback : __DMA_HandleTypeDef
  • XferISR : __I2C_HandleTypeDef
  • XferM1CpltCallback : __DMA_HandleTypeDef
  • XferM1HalfCpltCallback : __DMA_HandleTypeDef
  • XferOptions : __I2C_HandleTypeDef , SMBUS_HandleTypeDef
  • XferRepeatBlockCpltCallback : __MDMA_HandleTypeDef
  • XferSize : SMBUS_HandleTypeDef , DCMI_HandleTypeDef , __SAI_HandleTypeDef , __I2C_HandleTypeDef
  • XferTransferNumber : DCMI_HandleTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

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  • Year : RTC_DateTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Fields - Variables

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- z -

  • ZeroQuantaPause : ETH_MACConfigTypeDef
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_conf.h File Reference

  • File List
  • Globals
Defines
stm32h7xx_hal_conf.h File Reference
#include "stm32h7xx_hal_rcc.h"
#include "stm32h7xx_hal_gpio.h"
#include "stm32h7xx_hal_dma.h"
#include "stm32h7xx_hal_hash.h"
#include "stm32h7xx_hal_dcmi.h"
#include "stm32h7xx_hal_dma2d.h"
#include "stm32h7xx_hal_dfsdm.h"
#include "stm32h7xx_hal_eth.h"
#include "stm32h7xx_hal_cortex.h"
#include "stm32h7xx_hal_adc.h"
#include "stm32h7xx_hal_fdcan.h"
#include "stm32h7xx_hal_cec.h"
#include "stm32h7xx_hal_comp.h"
#include "stm32h7xx_hal_crc.h"
#include "stm32h7xx_hal_cryp.h"
#include "stm32h7xx_hal_dac.h"
#include "stm32h7xx_hal_flash.h"
#include "stm32h7xx_hal_hrtim.h"
#include "stm32h7xx_hal_hsem.h"
#include "stm32h7xx_hal_sram.h"
#include "stm32h7xx_hal_nor.h"
#include "stm32h7xx_hal_nand.h"
#include "stm32h7xx_hal_i2c.h"
#include "stm32h7xx_hal_i2s.h"
#include "stm32h7xx_hal_iwdg.h"
#include "stm32h7xx_hal_jpeg.h"
#include "stm32h7xx_hal_mdios.h"
#include "stm32h7xx_hal_mdma.h"
#include "stm32h7xx_hal_mmc.h"
#include "stm32h7xx_hal_lptim.h"
#include "stm32h7xx_hal_ltdc.h"
#include "stm32h7xx_hal_opamp.h"
#include "stm32h7xx_hal_pwr.h"
#include "stm32h7xx_hal_qspi.h"
#include "stm32h7xx_hal_rng.h"
#include "stm32h7xx_hal_rtc.h"
#include "stm32h7xx_hal_sai.h"
#include "stm32h7xx_hal_sd.h"
#include "stm32h7xx_hal_sdram.h"
#include "stm32h7xx_hal_spi.h"
#include "stm32h7xx_hal_spdifrx.h"
#include "stm32h7xx_hal_swpmi.h"
#include "stm32h7xx_hal_tim.h"
#include "stm32h7xx_hal_uart.h"
#include "stm32h7xx_hal_usart.h"
#include "stm32h7xx_hal_irda.h"
#include "stm32h7xx_hal_smartcard.h"
#include "stm32h7xx_hal_smbus.h"
#include "stm32h7xx_hal_wwdg.h"
#include "stm32h7xx_hal_pcd.h"
#include "stm32h7xx_hal_hcd.h"

Go to the source code of this file.

Defines

#define | HAL_MODULE_ENABLED
This is the list of modules to be used in the HAL driver.
#define | HAL_ADC_MODULE_ENABLED
#define | HAL_CEC_MODULE_ENABLED
#define | HAL_COMP_MODULE_ENABLED
#define | HAL_CORTEX_MODULE_ENABLED
#define | HAL_CRC_MODULE_ENABLED
#define | HAL_CRYP_MODULE_ENABLED
#define | HAL_DAC_MODULE_ENABLED
#define | HAL_DCMI_MODULE_ENABLED
#define | HAL_DFSDM_MODULE_ENABLED
#define | HAL_DMA_MODULE_ENABLED
#define | HAL_DMA2D_MODULE_ENABLED
#define | HAL_ETH_MODULE_ENABLED
#define | HAL_FDCAN_MODULE_ENABLED
#define | HAL_FLASH_MODULE_ENABLED
#define | HAL_GPIO_MODULE_ENABLED
#define | HAL_HASH_MODULE_ENABLED
#define | HAL_HCD_MODULE_ENABLED
#define | HAL_HRTIM_MODULE_ENABLED
#define | HAL_HSEM_MODULE_ENABLED
#define | HAL_I2C_MODULE_ENABLED
#define | HAL_I2S_MODULE_ENABLED
#define | HAL_IRDA_MODULE_ENABLED
#define | HAL_IWDG_MODULE_ENABLED
#define | HAL_JPEG_MODULE_ENABLED
#define | HAL_LPTIM_MODULE_ENABLED
#define | HAL_LTDC_MODULE_ENABLED
#define | HAL_MDIOS_MODULE_ENABLED
#define | HAL_MDMA_MODULE_ENABLED
#define | HAL_MMC_MODULE_ENABLED
#define | HAL_NAND_MODULE_ENABLED
#define | HAL_NOR_MODULE_ENABLED
#define | HAL_OPAMP_MODULE_ENABLED
#define | HAL_PCD_MODULE_ENABLED
#define | HAL_PWR_MODULE_ENABLED
#define | HAL_QSPI_MODULE_ENABLED
#define | HAL_RCC_MODULE_ENABLED
#define | HAL_RNG_MODULE_ENABLED
#define | HAL_RTC_MODULE_ENABLED
#define | HAL_SAI_MODULE_ENABLED
#define | HAL_SD_MODULE_ENABLED
#define | HAL_SDRAM_MODULE_ENABLED
#define | HAL_SMARTCARD_MODULE_ENABLED
#define | HAL_SMBUS_MODULE_ENABLED
#define | HAL_SPDIFRX_MODULE_ENABLED
#define | HAL_SPI_MODULE_ENABLED
#define | HAL_SRAM_MODULE_ENABLED
#define | HAL_SWPMI_MODULE_ENABLED
#define | HAL_TIM_MODULE_ENABLED
#define | HAL_UART_MODULE_ENABLED
#define | HAL_USART_MODULE_ENABLED
#define | HAL_WWDG_MODULE_ENABLED
#define | HSE_VALUE ((uint32_t)25000000)
Adjust the value of External High Speed oscillator (HSE) used in your application.
#define | HSE_STARTUP_TIMEOUT ((uint32_t)5000)
#define | CSI_VALUE ((uint32_t)4000000)
Internal oscillator (CSI) default value.
#define | HSI_VALUE ((uint32_t)64000000)
Internal High Speed oscillator (HSI) value.
#define | LSE_VALUE ((uint32_t)32768)
External Low Speed oscillator (LSE) value.
#define | LSE_STARTUP_TIMEOUT ((uint32_t)5000)
#define | EXTERNAL_CLOCK_VALUE 12288000U
External clock source for I2S peripheral This value is used by the I2S HAL module to compute the I2S clock source frequency, this source is inserted directly through I2S_CKIN pad.
#define | VDD_VALUE ((uint32_t)3300)
This is the HAL system configuration section.
#define | TICK_INT_PRIORITY ((uint32_t)0x0F)
#define | USE_RTOS 0
#define | USE_SD_TRANSCEIVER 1U
#define | ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */
#define | ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */
#define | ETH_MAC_ADDR0 ((uint8_t)0x02)
#define | ETH_MAC_ADDR1 ((uint8_t)0x00)
#define | ETH_MAC_ADDR2 ((uint8_t)0x00)
#define | ETH_MAC_ADDR3 ((uint8_t)0x00)
#define | ETH_MAC_ADDR4 ((uint8_t)0x00)
#define | ETH_MAC_ADDR5 ((uint8_t)0x00)
#define | assert_param(expr) ((void)0)
Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.

Define Documentation

#define assert_param ( expr ) ((void)0)

Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.

Include module's header file

Definition at line 415 of file stm32h7xx_hal_conf.h.

Referenced by ADC_ConversionStop(), FLASH_Erase_Sector(), FLASH_MassErase(), FLASH_OB_BootAddConfig(), FLASH_OB_BOR_LevelConfig(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_GetPCROP(), FLASH_OB_GetSecureArea(), FLASH_OB_GetWRP(), FLASH_OB_PCROPConfig(), FLASH_OB_RDPConfig(), FLASH_OB_SecureAreaConfig(), FLASH_OB_UserConfig(), FLASH_WaitForLastOperation(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetError(), HAL_ADC_GetState(), HAL_ADC_GetValue(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_GetValue(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_LinearCalibration_GetValue(), HAL_ADCEx_LinearCalibration_SetValue(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeGetValue(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), HAL_ADCEx_RegularStop_IT(), HAL_CEC_DeInit(), HAL_CEC_Init(), HAL_CEC_SetDeviceAddress(), HAL_CEC_Transmit_IT(), HAL_COMP_DeInit(), HAL_COMP_GetOutputLevel(), HAL_COMP_GetState(), HAL_COMP_Init(), HAL_COMP_Lock(), HAL_COMP_Start(), HAL_COMP_Start_IT(), HAL_COMP_Stop(), HAL_CRC_DeInit(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), HAL_CRCEx_Output_Data_Reverse(), HAL_CRCEx_Polynomial_Set(), HAL_CRYP_Init(), HAL_CRYP_SetConfig(), HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetValue(), HAL_DAC_Init(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualSetValue(), HAL_DACEx_GetTrimOffset(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_SelfCalibrate(), HAL_DACEx_SetUserTrimming(), HAL_DACEx_TriangleWaveGenerate(), HAL_DCMI_ConfigCrop(), HAL_DCMI_Init(), HAL_DCMI_Start_DMA(), HAL_DFSDM_ChannelCkabStart(), HAL_DFSDM_ChannelCkabStart_IT(), HAL_DFSDM_ChannelCkabStop(), HAL_DFSDM_ChannelCkabStop_IT(), HAL_DFSDM_ChannelDeInit(), HAL_DFSDM_ChannelInit(), HAL_DFSDM_ChannelModifyOffset(), HAL_DFSDM_ChannelPollForCkab(), HAL_DFSDM_ChannelPollForScd(), HAL_DFSDM_ChannelScdStart(), HAL_DFSDM_ChannelScdStart_IT(), HAL_DFSDM_ChannelScdStop(), HAL_DFSDM_ChannelScdStop_IT(), HAL_DFSDM_FilterAwdStart_IT(), HAL_DFSDM_FilterAwdStop_IT(), HAL_DFSDM_FilterConfigInjChannel(), HAL_DFSDM_FilterConfigRegChannel(), HAL_DFSDM_FilterDeInit(), HAL_DFSDM_FilterExdStart(), HAL_DFSDM_FilterExdStop(), HAL_DFSDM_FilterGetConvTimeValue(), HAL_DFSDM_FilterGetExdMaxValue(), HAL_DFSDM_FilterGetExdMinValue(), HAL_DFSDM_FilterGetInjectedValue(), HAL_DFSDM_FilterGetRegularValue(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStop(), HAL_DFSDM_FilterInjectedStop_DMA(), HAL_DFSDM_FilterInjectedStop_IT(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStop(), HAL_DFSDM_FilterRegularStop_DMA(), HAL_DFSDM_FilterRegularStop_IT(), HAL_DMA2D_BlendingStart(), HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_CLUTLoad(), HAL_DMA2D_CLUTLoad_IT(), HAL_DMA2D_ConfigCLUT(), HAL_DMA2D_ConfigLayer(), HAL_DMA2D_EnableCLUT(), HAL_DMA2D_Init(), HAL_DMA2D_ProgramLineEvent(), HAL_DMA2D_Start(), HAL_DMA2D_Start_IT(), HAL_DMA_Init(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_ConfigMuxSync(), HAL_DMAEx_DisableMuxRequestGenerator(), HAL_DMAEx_EnableMuxRequestGenerator(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), HAL_EXTI_D1_ClearFlag(), HAL_EXTI_D1_EventInputConfig(), HAL_EXTI_D3_EventInputConfig(), HAL_EXTI_EdgeConfig(), HAL_EXTI_GenerateSWInterrupt(), HAL_FDCAN_ActivateNotification(), HAL_FDCAN_AddMessageToTxBuffer(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigClockCalibration(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigFifoWatermark(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_ConfigGlobalFilter(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTimestampCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_DeactivateNotification(), HAL_FDCAN_DeInit(), HAL_FDCAN_EnableTimestampCounter(), HAL_FDCAN_GetRxFifoFillLevel(), HAL_FDCAN_GetTxEvent(), HAL_FDCAN_Init(), HAL_FDCAN_IsRxBufferMessageAvailable(), HAL_FDCAN_IsTxBufferMessagePending(), HAL_FDCAN_TT_ActivateNotification(), HAL_FDCAN_TT_ConfigExternalSyncPhase(), HAL_FDCAN_TT_ConfigInterruptLines(), HAL_FDCAN_TT_ConfigOperation(), HAL_FDCAN_TT_ConfigReferenceMessage(), HAL_FDCAN_TT_ConfigRegisterTimeMark(), HAL_FDCAN_TT_ConfigStopWatch(), HAL_FDCAN_TT_ConfigTrigger(), HAL_FDCAN_TT_DeactivateNotification(), HAL_FDCAN_TT_DisableExternalSynchronization(), HAL_FDCAN_TT_DisableHardwareGapControl(), HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(), HAL_FDCAN_TT_DisableTimeMarkGapControl(), HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(), HAL_FDCAN_TT_EnableExternalSynchronization(), HAL_FDCAN_TT_EnableHardwareGapControl(), HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(), HAL_FDCAN_TT_EnableTimeMarkGapControl(), HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(), HAL_FDCAN_TT_GetOperationStatus(), HAL_FDCAN_TT_SetClockSynchronization(), HAL_FDCAN_TT_SetEndOfGap(), HAL_FDCAN_TT_SetGlobalTime(), HAL_FDCAN_TT_SetNextIsGap(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), HAL_FLASHEx_OBGetConfig(), HAL_FLASHEx_OBProgram(), HAL_GPIO_DeInit(), HAL_GPIO_Init(), HAL_GPIO_LockPin(), HAL_GPIO_ReadPin(), HAL_GPIO_TogglePin(), HAL_GPIO_WritePin(), HAL_HalfDuplex_Init(), HAL_HASH_Init(), HAL_HCD_Init(), HAL_HRTIM_ADCTriggerConfig(), HAL_HRTIM_BurstDMAConfig(), HAL_HRTIM_BurstDMATransfer(), HAL_HRTIM_BurstModeConfig(), HAL_HRTIM_BurstModeCtl(), HAL_HRTIM_ChopperModeConfig(), HAL_HRTIM_DeadTimeConfig(), HAL_HRTIM_DeInit(), HAL_HRTIM_EventConfig(), HAL_HRTIM_EventPrescalerConfig(), HAL_HRTIM_FaultConfig(), HAL_HRTIM_FaultModeCtl(), HAL_HRTIM_FaultPrescalerConfig(), HAL_HRTIM_GetCapturedValue(), HAL_HRTIM_GetCurrentPushPullStatus(), HAL_HRTIM_GetDelayedProtectionStatus(), HAL_HRTIM_GetIdlePushPullStatus(), HAL_HRTIM_Init(), HAL_HRTIM_SimpleBaseStart(), HAL_HRTIM_SimpleBaseStart_DMA(), HAL_HRTIM_SimpleBaseStart_IT(), HAL_HRTIM_SimpleBaseStop(), HAL_HRTIM_SimpleBaseStop_DMA(), HAL_HRTIM_SimpleBaseStop_IT(), HAL_HRTIM_SimpleCaptureChannelConfig(), HAL_HRTIM_SimpleCaptureStart(), HAL_HRTIM_SimpleCaptureStart_DMA(), HAL_HRTIM_SimpleCaptureStart_IT(), HAL_HRTIM_SimpleCaptureStop(), HAL_HRTIM_SimpleCaptureStop_DMA(), HAL_HRTIM_SimpleCaptureStop_IT(), HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOCStart(), HAL_HRTIM_SimpleOCStart_DMA(), HAL_HRTIM_SimpleOCStart_IT(), HAL_HRTIM_SimpleOCStop(), HAL_HRTIM_SimpleOCStop_DMA(), HAL_HRTIM_SimpleOCStop_IT(), HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimpleOnePulseStart(), HAL_HRTIM_SimpleOnePulseStart_IT(), HAL_HRTIM_SimpleOnePulseStop(), HAL_HRTIM_SimpleOnePulseStop_IT(), HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_SimplePWMStart(), HAL_HRTIM_SimplePWMStart_DMA(), HAL_HRTIM_SimplePWMStart_IT(), HAL_HRTIM_SimplePWMStop(), HAL_HRTIM_SimplePWMStop_DMA(), HAL_HRTIM_SimplePWMStop_IT(), HAL_HRTIM_SoftwareCapture(), HAL_HRTIM_SoftwareReset(), HAL_HRTIM_SoftwareUpdate(), HAL_HRTIM_TimeBaseConfig(), HAL_HRTIM_TimerEventFilteringConfig(), HAL_HRTIM_UpdateDisable(), HAL_HRTIM_UpdateEnable(), HAL_HRTIM_WaveformCaptureConfig(), HAL_HRTIM_WaveformCompareConfig(), HAL_HRTIM_WaveformCounterStart(), HAL_HRTIM_WaveformCounterStart_DMA(), HAL_HRTIM_WaveformCounterStart_IT(), HAL_HRTIM_WaveformCounterStop(), HAL_HRTIM_WaveformCounterStop_DMA(), HAL_HRTIM_WaveformCounterStop_IT(), HAL_HRTIM_WaveformGetOutputLevel(), HAL_HRTIM_WaveformGetOutputState(), HAL_HRTIM_WaveformOutputConfig(), HAL_HRTIM_WaveformOutputStart(), HAL_HRTIM_WaveformOutputStop(), HAL_HRTIM_WaveformSetOutputLevel(), HAL_HRTIM_WaveformTimerConfig(), HAL_HSEM_FastTake(), HAL_HSEM_Release(), HAL_HSEM_ReleaseAll(), HAL_HSEM_SetClearKey(), HAL_HSEM_Take(), HAL_I2C_DeInit(), HAL_I2C_Init(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableFastModePlus(), HAL_I2CEx_DisableWakeUp(), HAL_I2CEx_EnableFastModePlus(), HAL_I2CEx_EnableWakeUp(), HAL_I2S_DeInit(), HAL_I2S_Init(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), HAL_I2SEx_TransmitReceive(), HAL_I2SEx_TransmitReceive_DMA(), HAL_I2SEx_TransmitReceive_IT(), HAL_IRDA_DeInit(), HAL_IRDA_Init(), HAL_IWDG_Init(), HAL_JPEG_ConfigEncoding(), HAL_JPEG_Decode(), HAL_JPEG_Decode_DMA(), HAL_JPEG_Decode_IT(), HAL_JPEG_Encode(), HAL_JPEG_Encode_DMA(), HAL_JPEG_Encode_IT(), HAL_JPEG_Pause(), HAL_JPEG_Resume(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_ReadAutoReload(), HAL_LPTIM_ReadCompare(), HAL_LPTIM_ReadCounter(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), HAL_LPTIM_TimeOut_Stop_IT(), HAL_LTDC_ConfigCLUT(), HAL_LTDC_ConfigColorKeying(), HAL_LTDC_ConfigColorKeying_NoReload(), HAL_LTDC_ConfigLayer(), HAL_LTDC_ConfigLayer_NoReload(), HAL_LTDC_DisableCLUT(), HAL_LTDC_DisableCLUT_NoReload(), HAL_LTDC_DisableColorKeying(), HAL_LTDC_DisableColorKeying_NoReload(), HAL_LTDC_EnableCLUT(), HAL_LTDC_EnableCLUT_NoReload(), HAL_LTDC_EnableColorKeying(), HAL_LTDC_EnableColorKeying_NoReload(), HAL_LTDC_Init(), HAL_LTDC_ProgramLineEvent(), HAL_LTDC_Reload(), HAL_LTDC_SetAddress(), HAL_LTDC_SetAddress_NoReload(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetAlpha_NoReload(), HAL_LTDC_SetPitch(), HAL_LTDC_SetPitch_NoReload(), HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetPixelFormat_NoReload(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetWindowPosition_NoReload(), HAL_LTDC_SetWindowSize(), HAL_LTDC_SetWindowSize_NoReload(), HAL_MDIOS_ClearReadRegAddress(), HAL_MDIOS_ClearWriteRegAddress(), HAL_MDIOS_DeInit(), HAL_MDIOS_Init(), HAL_MDIOS_ReadReg(), HAL_MDIOS_WriteReg(), HAL_MDMA_Init(), HAL_MDMA_LinkedList_CreateNode(), HAL_MDMA_PollForTransfer(), HAL_MDMA_Start(), HAL_MDMA_Start_IT(), HAL_MMC_ConfigWideBusOperation(), HAL_MMC_DeInit(), HAL_MMC_Init(), HAL_MPU_ConfigRegion(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_NVIC_ClearPendingIRQ(), HAL_NVIC_DisableIRQ(), HAL_NVIC_EnableIRQ(), HAL_NVIC_GetActive(), HAL_NVIC_GetPendingIRQ(), HAL_NVIC_GetPriority(), HAL_NVIC_SetPendingIRQ(), HAL_NVIC_SetPriority(), HAL_NVIC_SetPriorityGrouping(), HAL_OPAMP_DeInit(), HAL_OPAMP_GetState(), HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_Lock(), HAL_OPAMP_SelfCalibrate(), HAL_OPAMP_Start(), HAL_OPAMP_Stop(), HAL_OPAMPEx_SelfCalibrateAll(), HAL_OPAMPEx_Unlock(), HAL_PCD_Init(), HAL_PWR_ConfigPVD(), HAL_PWR_DisableWakeUpPin(), HAL_PWR_EnableWakeUpPin(), HAL_PWR_EnterSLEEPMode(), HAL_PWR_EnterSTOPMode(), HAL_PWREx_ClearWakeupFlag(), HAL_PWREx_ConfigAVD(), HAL_PWREx_ConfigD3Domain(), HAL_PWREx_ConfigSupply(), HAL_PWREx_ControlStopModeVoltageScaling(), HAL_PWREx_ControlVoltageScaling(), HAL_PWREx_DisableWakeUpPin(), HAL_PWREx_EnableBatteryCharging(), HAL_PWREx_EnableWakeUpPin(), HAL_PWREx_EnterSTANDBYMode(), HAL_PWREx_EnterSTOPMode(), HAL_PWREx_GetWakeupFlag(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_Init(), HAL_QSPI_MemoryMapped(), HAL_RCC_ClockConfig(), HAL_RCC_MCOConfig(), HAL_RCC_OscConfig(), HAL_RCCEx_CRSConfig(), HAL_RCCEx_CRSGetSynchronizationInfo(), HAL_RCCEx_KerWakeUpStopCLKConfig(), HAL_RCCEx_PeriphCLKConfig(), HAL_RCCEx_WakeUpStopCLKConfig(), HAL_RCCEx_WWDGxSysResetConfig(), HAL_RNG_Init(), HAL_RS485Ex_Init(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_BKUPRead(), HAL_RTCEx_BKUPWrite(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_SAI_EnableRxMuteMode(), HAL_SAI_EnableTxMuteMode(), HAL_SAI_Init(), HAL_SAI_InitProtocol(), HAL_SAIEx_ConfigPdmMicDelay(), HAL_SD_ConfigWideBusOperation(), HAL_SD_DeInit(), HAL_SD_Init(), HAL_SetFMCMemorySwappingConfig(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARDEx_TimeOut_Config(), HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), HAL_SPDIFRX_DeInit(), HAL_SPDIFRX_Init(), HAL_SPDIFRX_SetDataFormat(), HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPIEx_ConfigureUnderrun(), HAL_SWPMI_DeInit(), HAL_SWPMI_Init(), HAL_SYSCFG_AnalogSwitchConfig(), HAL_SYSCFG_CM7BootAddConfig(), HAL_SYSCFG_CompensationCodeConfig(), HAL_SYSCFG_CompensationCodeSelect(), HAL_SYSCFG_ETHInterfaceSelect(), HAL_SYSCFG_VREFBUF_HighImpedanceConfig(), HAL_SYSCFG_VREFBUF_TrimmingConfig(), HAL_SYSCFG_VREFBUF_VoltageScalingConfig(), HAL_SYSTICK_CLKSourceConfig(), HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_ConfigTI1Input(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_ConfigBreakInput(), HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), HAL_TIMEx_GroupChannel5(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_RemapConfig(), HAL_TIMEx_TISelection(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_USART_DeInit(), HAL_USART_Init(), HAL_WWDG_Init(), HASH_Accumulate(), HASH_Start_DMA(), HMAC_Start_DMA(), I2C_TransferConfig(), IRDA_SetConfig(), QSPI_Config(), RCCEx_PLL2_Config(), RCCEx_PLL3_Config(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_SetConfig(), SMBUS_TransferConfig(), TIM_CCxChannelCmd(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_SlaveTimer_SetConfig(), UART_AdvFeatureConfig(), UART_SetConfig(), UARTEx_Wakeup_AddressConfig(), and USART_SetConfig().

#define CSI_VALUE ((uint32_t)4000000)

Internal oscillator (CSI) default value.

This value is the default CSI value after Reset. Value of the Internal oscillator in Hz

Definition at line 127 of file stm32h7xx_hal_conf.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_GetPLL1ClockFreq(), HAL_RCCEx_GetPLL2ClockFreq(), HAL_RCCEx_GetPLL3ClockFreq(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define ETH_MAC_ADDR0 ((uint8_t)0x02)

Definition at line 177 of file stm32h7xx_hal_conf.h.

#define ETH_MAC_ADDR1 ((uint8_t)0x00)

Definition at line 178 of file stm32h7xx_hal_conf.h.

#define ETH_MAC_ADDR2 ((uint8_t)0x00)

Definition at line 179 of file stm32h7xx_hal_conf.h.

#define ETH_MAC_ADDR3 ((uint8_t)0x00)

Definition at line 180 of file stm32h7xx_hal_conf.h.

#define ETH_MAC_ADDR4 ((uint8_t)0x00)

Definition at line 181 of file stm32h7xx_hal_conf.h.

#define ETH_MAC_ADDR5 ((uint8_t)0x00)

Definition at line 182 of file stm32h7xx_hal_conf.h.

#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */

Definition at line 175 of file stm32h7xx_hal_conf.h.

Referenced by ETH_DMARxDescListInit(), HAL_ETH_DescAssignMemory(), HAL_ETH_IsRxDataAvailable(), HAL_ETH_Start_IT(), and HAL_ETH_Stop_IT().

#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */

Definition at line 174 of file stm32h7xx_hal_conf.h.

Referenced by ETH_DMATxDescListInit().

#define EXTERNAL_CLOCK_VALUE 12288000U

External clock source for I2S peripheral This value is used by the I2S HAL module to compute the I2S clock source frequency, this source is inserted directly through I2S_CKIN pad.

Value of the External clock in Hz

Definition at line 158 of file stm32h7xx_hal_conf.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define HAL_ADC_MODULE_ENABLED

Definition at line 56 of file stm32h7xx_hal_conf.h.

#define HAL_CEC_MODULE_ENABLED

Definition at line 57 of file stm32h7xx_hal_conf.h.

#define HAL_COMP_MODULE_ENABLED

Definition at line 58 of file stm32h7xx_hal_conf.h.

#define HAL_CORTEX_MODULE_ENABLED

Definition at line 59 of file stm32h7xx_hal_conf.h.

#define HAL_CRC_MODULE_ENABLED

Definition at line 60 of file stm32h7xx_hal_conf.h.

#define HAL_CRYP_MODULE_ENABLED

Definition at line 61 of file stm32h7xx_hal_conf.h.

#define HAL_DAC_MODULE_ENABLED

Definition at line 62 of file stm32h7xx_hal_conf.h.

#define HAL_DCMI_MODULE_ENABLED

Definition at line 63 of file stm32h7xx_hal_conf.h.

#define HAL_DFSDM_MODULE_ENABLED

Definition at line 64 of file stm32h7xx_hal_conf.h.

#define HAL_DMA2D_MODULE_ENABLED

Definition at line 66 of file stm32h7xx_hal_conf.h.

#define HAL_DMA_MODULE_ENABLED

Definition at line 65 of file stm32h7xx_hal_conf.h.

#define HAL_ETH_MODULE_ENABLED

Definition at line 67 of file stm32h7xx_hal_conf.h.

#define HAL_FDCAN_MODULE_ENABLED

Definition at line 68 of file stm32h7xx_hal_conf.h.

#define HAL_FLASH_MODULE_ENABLED

Definition at line 69 of file stm32h7xx_hal_conf.h.

#define HAL_GPIO_MODULE_ENABLED

Definition at line 70 of file stm32h7xx_hal_conf.h.

#define HAL_HASH_MODULE_ENABLED

Definition at line 71 of file stm32h7xx_hal_conf.h.

#define HAL_HCD_MODULE_ENABLED

Definition at line 72 of file stm32h7xx_hal_conf.h.

#define HAL_HRTIM_MODULE_ENABLED

Definition at line 73 of file stm32h7xx_hal_conf.h.

#define HAL_HSEM_MODULE_ENABLED

Definition at line 74 of file stm32h7xx_hal_conf.h.

#define HAL_I2C_MODULE_ENABLED

Definition at line 75 of file stm32h7xx_hal_conf.h.

#define HAL_I2S_MODULE_ENABLED

Definition at line 76 of file stm32h7xx_hal_conf.h.

#define HAL_IRDA_MODULE_ENABLED

Definition at line 77 of file stm32h7xx_hal_conf.h.

#define HAL_IWDG_MODULE_ENABLED

Definition at line 78 of file stm32h7xx_hal_conf.h.

#define HAL_JPEG_MODULE_ENABLED

Definition at line 79 of file stm32h7xx_hal_conf.h.

#define HAL_LPTIM_MODULE_ENABLED

Definition at line 80 of file stm32h7xx_hal_conf.h.

#define HAL_LTDC_MODULE_ENABLED

Definition at line 81 of file stm32h7xx_hal_conf.h.

#define HAL_MDIOS_MODULE_ENABLED

Definition at line 82 of file stm32h7xx_hal_conf.h.

#define HAL_MDMA_MODULE_ENABLED

Definition at line 83 of file stm32h7xx_hal_conf.h.

#define HAL_MMC_MODULE_ENABLED

Definition at line 84 of file stm32h7xx_hal_conf.h.

#define HAL_MODULE_ENABLED

This is the list of modules to be used in the HAL driver.

Definition at line 55 of file stm32h7xx_hal_conf.h.

#define HAL_NAND_MODULE_ENABLED

Definition at line 85 of file stm32h7xx_hal_conf.h.

#define HAL_NOR_MODULE_ENABLED

Definition at line 86 of file stm32h7xx_hal_conf.h.

#define HAL_OPAMP_MODULE_ENABLED

Definition at line 87 of file stm32h7xx_hal_conf.h.

#define HAL_PCD_MODULE_ENABLED

Definition at line 88 of file stm32h7xx_hal_conf.h.

#define HAL_PWR_MODULE_ENABLED

Definition at line 89 of file stm32h7xx_hal_conf.h.

#define HAL_QSPI_MODULE_ENABLED

Definition at line 90 of file stm32h7xx_hal_conf.h.

#define HAL_RCC_MODULE_ENABLED

Definition at line 91 of file stm32h7xx_hal_conf.h.

#define HAL_RNG_MODULE_ENABLED

Definition at line 92 of file stm32h7xx_hal_conf.h.

#define HAL_RTC_MODULE_ENABLED

Definition at line 93 of file stm32h7xx_hal_conf.h.

#define HAL_SAI_MODULE_ENABLED

Definition at line 94 of file stm32h7xx_hal_conf.h.

#define HAL_SD_MODULE_ENABLED

Definition at line 95 of file stm32h7xx_hal_conf.h.

#define HAL_SDRAM_MODULE_ENABLED

Definition at line 96 of file stm32h7xx_hal_conf.h.

#define HAL_SMARTCARD_MODULE_ENABLED

Definition at line 97 of file stm32h7xx_hal_conf.h.

#define HAL_SMBUS_MODULE_ENABLED

Definition at line 98 of file stm32h7xx_hal_conf.h.

#define HAL_SPDIFRX_MODULE_ENABLED

Definition at line 99 of file stm32h7xx_hal_conf.h.

#define HAL_SPI_MODULE_ENABLED

Definition at line 100 of file stm32h7xx_hal_conf.h.

#define HAL_SRAM_MODULE_ENABLED

Definition at line 101 of file stm32h7xx_hal_conf.h.

#define HAL_SWPMI_MODULE_ENABLED

Definition at line 102 of file stm32h7xx_hal_conf.h.

#define HAL_TIM_MODULE_ENABLED

Definition at line 103 of file stm32h7xx_hal_conf.h.

#define HAL_UART_MODULE_ENABLED

Definition at line 104 of file stm32h7xx_hal_conf.h.

#define HAL_USART_MODULE_ENABLED

Definition at line 105 of file stm32h7xx_hal_conf.h.

#define HAL_WWDG_MODULE_ENABLED

Definition at line 106 of file stm32h7xx_hal_conf.h.

#define HSE_STARTUP_TIMEOUT ((uint32_t)5000)

Time out for HSE start up, in ms

Definition at line 119 of file stm32h7xx_hal_conf.h.

#define HSE_VALUE ((uint32_t)25000000)

Adjust the value of External High Speed oscillator (HSE) used in your application.

This value is used by the RCC HAL module to compute the system frequency (when HSE is used as system clock source, directly or through the PLL). Value of the External oscillator in Hz

Definition at line 115 of file stm32h7xx_hal_conf.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_GetPLL1ClockFreq(), HAL_RCCEx_GetPLL2ClockFreq(), and HAL_RCCEx_GetPLL3ClockFreq().

#define HSI_VALUE ((uint32_t)64000000)

Internal High Speed oscillator (HSI) value.

This value is used by the RCC HAL module to compute the system frequency (when HSI is used as system clock source, directly or through the PLL). Value of the Internal oscillator in Hz

Definition at line 136 of file stm32h7xx_hal_conf.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_GetPLL1ClockFreq(), HAL_RCCEx_GetPLL2ClockFreq(), HAL_RCCEx_GetPLL3ClockFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define LSE_STARTUP_TIMEOUT ((uint32_t)5000)

Time out for LSE start up, in ms

Definition at line 149 of file stm32h7xx_hal_conf.h.

#define LSE_VALUE ((uint32_t)32768)

External Low Speed oscillator (LSE) value.

This value is used by the UART, RTC HAL module to compute the system frequency Value of the External oscillator in Hz

Definition at line 144 of file stm32h7xx_hal_conf.h.

Referenced by IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define TICK_INT_PRIORITY ((uint32_t)0x0F)

tick interrupt priority

Definition at line 169 of file stm32h7xx_hal_conf.h.

Referenced by HAL_Init(), and HAL_RCC_ClockConfig().

#define USE_RTOS 0

Definition at line 170 of file stm32h7xx_hal_conf.h.

#define USE_SD_TRANSCEIVER 1U

use uSD Transceiver

Definition at line 171 of file stm32h7xx_hal_conf.h.

#define VDD_VALUE ((uint32_t)3300)

This is the HAL system configuration section.

Value of VDD in mv

Definition at line 168 of file stm32h7xx_hal_conf.h.

Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_eth.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_eth.h File Reference

Header file of ETH HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_eth_ex.h"

Go to the source code of this file.

Data Structures

struct | __ETH_BufferTypeDef
ETH Buffers List structure definition. More...
struct | ETH_TxDescListTypeDef
DMA Transmit Descriptors Wrapper structure definition. More...
struct | ETH_TxPacketConfig
Transmit Packet Configuration structure definition. More...
struct | ETH_RxDescListTypeDef
DMA Receive Descriptors Wrapper structure definition. More...
struct | ETH_RxPacketInfo
Received Packet Information structure definition. More...
struct | ETH_MACConfigTypeDef
ETH MAC Configuration Structure definition. More...
struct | ETH_DMAConfigTypeDef
ETH DMA Configuration Structure definition. More...
struct | ETH_InitTypeDef
ETH Init Structure definition. More...
struct | ETH_HandleTypeDef
ETH Handle Structure definition. More...
struct | ETH_MACFilterConfigTypeDef
ETH MAC filter structure definition. More...
struct | ETH_PowerDownConfigTypeDef
ETH Power Down structure definition. More...

Defines

#define | ETH_TX_DESC_CNT 4
#define | ETH_RX_DESC_CNT 4
#define | ETH_DMATXNDESCRF_B1AP ((uint32_t)0xFFFFFFFF)
Bit definition of TDES0 RF register.
#define | ETH_DMATXNDESCRF_B2AP ((uint32_t)0xFFFFFFFF)
Bit definition of TDES1 RF register.
#define | ETH_DMATXNDESCRF_IOC ((uint32_t)0x80000000)
Bit definition of TDES2 RF register.
#define | ETH_DMATXNDESCRF_TTSE ((uint32_t)0x40000000)
#define | ETH_DMATXNDESCRF_B2L ((uint32_t)0x3FFF0000)
#define | ETH_DMATXNDESCRF_VTIR ((uint32_t)0x0000C000)
#define | ETH_DMATXNDESCRF_VTIR_DISABLE ((uint32_t)0x00000000)
#define | ETH_DMATXNDESCRF_VTIR_REMOVE ((uint32_t)0x00004000)
#define | ETH_DMATXNDESCRF_VTIR_INSERT ((uint32_t)0x00008000)
#define | ETH_DMATXNDESCRF_VTIR_REPLACE ((uint32_t)0x0000C000)
#define | ETH_DMATXNDESCRF_B1L ((uint32_t)0x00003FFF)
#define | ETH_DMATXNDESCRF_HL ((uint32_t)0x000003FF)
#define | ETH_DMATXNDESCRF_OWN ((uint32_t)0x80000000)
Bit definition of TDES3 RF register.
#define | ETH_DMATXNDESCRF_CTXT ((uint32_t)0x40000000)
#define | ETH_DMATXNDESCRF_FD ((uint32_t)0x20000000)
#define | ETH_DMATXNDESCRF_LD ((uint32_t)0x10000000)
#define | ETH_DMATXNDESCRF_CPC ((uint32_t)0x0C000000)
#define | ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT ((uint32_t)0x00000000)
#define | ETH_DMATXNDESCRF_CPC_CRC_INSERT ((uint32_t)0x04000000)
#define | ETH_DMATXNDESCRF_CPC_DISABLE ((uint32_t)0x08000000)
#define | ETH_DMATXNDESCRF_CPC_CRC_REPLACE ((uint32_t)0x0C000000)
#define | ETH_DMATXNDESCRF_SAIC ((uint32_t)0x03800000)
#define | ETH_DMATXNDESCRF_SAIC_DISABLE ((uint32_t)0x00000000)
#define | ETH_DMATXNDESCRF_SAIC_INSERT ((uint32_t)0x00800000)
#define | ETH_DMATXNDESCRF_SAIC_REPLACE ((uint32_t)0x01000000)
#define | ETH_DMATXNDESCRF_THL ((uint32_t)0x00780000)
#define | ETH_DMATXNDESCRF_TSE ((uint32_t)0x00040000)
#define | ETH_DMATXNDESCRF_CIC ((uint32_t)0x00030000)
#define | ETH_DMATXNDESCRF_CIC_DISABLE ((uint32_t)0x00000000)
#define | ETH_DMATXNDESCRF_CIC_IPHDR_INSERT ((uint32_t)0x00010000)
#define | ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT ((uint32_t)0x00020000)
#define | ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC ((uint32_t)0x00030000)
#define | ETH_DMATXNDESCRF_TPL ((uint32_t)0x0003FFFF)
#define | ETH_DMATXNDESCRF_FL ((uint32_t)0x00007FFF)
#define | ETH_DMATXNDESCWBF_TTSL ((uint32_t)0xFFFFFFFF)
Bit definition of TDES0 WBF register.
#define | ETH_DMATXNDESCWBF_TTSH ((uint32_t)0xFFFFFFFF)
Bit definition of TDES1 WBF register.
#define | ETH_DMATXNDESCWBF_OWN ((uint32_t)0x80000000)
Bit definition of TDES3 WBF register.
#define | ETH_DMATXNDESCWBF_CTXT ((uint32_t)0x40000000)
#define | ETH_DMATXNDESCWBF_FD ((uint32_t)0x20000000)
#define | ETH_DMATXNDESCWBF_LD ((uint32_t)0x10000000)
#define | ETH_DMATXNDESCWBF_TTSS ((uint32_t)0x00020000)
#define | ETH_DMATXNDESCWBF_DP ((uint32_t)0x04000000)
#define | ETH_DMATXNDESCWBF_TTSE ((uint32_t)0x02000000)
#define | ETH_DMATXNDESCWBF_ES ((uint32_t)0x00008000)
#define | ETH_DMATXNDESCWBF_JT ((uint32_t)0x00004000)
#define | ETH_DMATXNDESCWBF_FF ((uint32_t)0x00002000)
#define | ETH_DMATXNDESCWBF_PCE ((uint32_t)0x00001000)
#define | ETH_DMATXNDESCWBF_LCA ((uint32_t)0x00000800)
#define | ETH_DMATXNDESCWBF_NC ((uint32_t)0x00000400)
#define | ETH_DMATXNDESCWBF_LCO ((uint32_t)0x00000200)
#define | ETH_DMATXNDESCWBF_EC ((uint32_t)0x00000100)
#define | ETH_DMATXNDESCWBF_CC ((uint32_t)0x000000F0)
#define | ETH_DMATXNDESCWBF_ED ((uint32_t)0x00000008)
#define | ETH_DMATXNDESCWBF_UF ((uint32_t)0x00000004)
#define | ETH_DMATXNDESCWBF_DB ((uint32_t)0x00000002)
#define | ETH_DMATXNDESCWBF_IHE ((uint32_t)0x00000004)
#define | ETH_DMATXCDESC_TTSL ((uint32_t)0xFFFFFFFF)
Bit definition of Tx context descriptor register 0.
#define | ETH_DMATXCDESC_TTSH ((uint32_t)0xFFFFFFFF)
Bit definition of Tx context descriptor register 1.
#define | ETH_DMATXCDESC_IVT ((uint32_t)0xFFFF0000)
Bit definition of Tx context descriptor register 2.
#define | ETH_DMATXCDESC_MSS ((uint32_t)0x00003FFF)
#define | ETH_DMATXCDESC_OWN ((uint32_t)0x80000000)
Bit definition of Tx context descriptor register 3.
#define | ETH_DMATXCDESC_CTXT ((uint32_t)0x40000000)
#define | ETH_DMATXCDESC_OSTC ((uint32_t)0x08000000)
#define | ETH_DMATXCDESC_TCMSSV ((uint32_t)0x04000000)
#define | ETH_DMATXCDESC_CDE ((uint32_t)0x00800000)
#define | ETH_DMATXCDESC_IVTIR ((uint32_t)0x000C0000)
#define | ETH_DMATXCDESC_IVTIR_DISABLE ((uint32_t)0x00000000)
#define | ETH_DMATXCDESC_IVTIR_REMOVE ((uint32_t)0x00040000)
#define | ETH_DMATXCDESC_IVTIR_INSERT ((uint32_t)0x00080000)
#define | ETH_DMATXCDESC_IVTIR_REPLACE ((uint32_t)0x000C0000)
#define | ETH_DMATXCDESC_IVLTV ((uint32_t)0x00020000)
#define | ETH_DMATXCDESC_VLTV ((uint32_t)0x00010000)
#define | ETH_DMATXCDESC_VT ((uint32_t)0x0000FFFF)
#define | ETH_DMARXNDESCRF_BUF1AP ((uint32_t)0xFFFFFFFF)
Bit definition of Rx normal descriptor register 0 read format.
#define | ETH_DMARXNDESCRF_BUF2AP ((uint32_t)0xFFFFFFFF)
Bit definition of Rx normal descriptor register 2 read format.
#define | ETH_DMARXNDESCRF_OWN ((uint32_t)0x80000000)
Bit definition of Rx normal descriptor register 3 read format.
#define | ETH_DMARXNDESCRF_IOC ((uint32_t)0x40000000)
#define | ETH_DMARXNDESCRF_BUF2V ((uint32_t)0x02000000)
#define | ETH_DMARXNDESCRF_BUF1V ((uint32_t)0x01000000)
#define | ETH_DMARXNDESCWBF_IVT ((uint32_t)0xFFFF0000)
Bit definition of Rx normal descriptor register 0 write back format.
#define | ETH_DMARXNDESCWBF_OVT ((uint32_t)0x0000FFFF)
#define | ETH_DMARXNDESCWBF_OPC ((uint32_t)0xFFFF0000)
Bit definition of Rx normal descriptor register 1 write back format.
#define | ETH_DMARXNDESCWBF_TD ((uint32_t)0x00008000)
#define | ETH_DMARXNDESCWBF_TSA ((uint32_t)0x00004000)
#define | ETH_DMARXNDESCWBF_PV ((uint32_t)0x00002000)
#define | ETH_DMARXNDESCWBF_PFT ((uint32_t)0x00001000)
#define | ETH_DMARXNDESCWBF_PMT_NO ((uint32_t)0x00000000)
#define | ETH_DMARXNDESCWBF_PMT_SYNC ((uint32_t)0x00000100)
#define | ETH_DMARXNDESCWBF_PMT_FUP ((uint32_t)0x00000200)
#define | ETH_DMARXNDESCWBF_PMT_DREQ ((uint32_t)0x00000300)
#define | ETH_DMARXNDESCWBF_PMT_DRESP ((uint32_t)0x00000400)
#define | ETH_DMARXNDESCWBF_PMT_PDREQ ((uint32_t)0x00000500)
#define | ETH_DMARXNDESCWBF_PMT_PDRESP ((uint32_t)0x00000600)
#define | ETH_DMARXNDESCWBF_PMT_PDRESPFUP ((uint32_t)0x00000700)
#define | ETH_DMARXNDESCWBF_PMT_ANNOUNCE ((uint32_t)0x00000800)
#define | ETH_DMARXNDESCWBF_PMT_MANAG ((uint32_t)0x00000900)
#define | ETH_DMARXNDESCWBF_PMT_SIGN ((uint32_t)0x00000A00)
#define | ETH_DMARXNDESCWBF_PMT_RESERVED ((uint32_t)0x00000F00)
#define | ETH_DMARXNDESCWBF_IPCE ((uint32_t)0x00000080)
#define | ETH_DMARXNDESCWBF_IPCB ((uint32_t)0x00000040)
#define | ETH_DMARXNDESCWBF_IPV6 ((uint32_t)0x00000020)
#define | ETH_DMARXNDESCWBF_IPV4 ((uint32_t)0x00000010)
#define | ETH_DMARXNDESCWBF_IPHE ((uint32_t)0x00000008)
#define | ETH_DMARXNDESCWBF_PT ((uint32_t)0x00000003)
#define | ETH_DMARXNDESCWBF_PT_UNKNOWN ((uint32_t)0x00000000)
#define | ETH_DMARXNDESCWBF_PT_UDP ((uint32_t)0x00000001)
#define | ETH_DMARXNDESCWBF_PT_TCP ((uint32_t)0x00000002)
#define | ETH_DMARXNDESCWBF_PT_ICMP ((uint32_t)0x00000003)
#define | ETH_DMARXNDESCWBF_L3L4FM ((uint32_t)0x20000000)
Bit definition of Rx normal descriptor register 2 write back format.
#define | ETH_DMARXNDESCWBF_L4FM ((uint32_t)0x10000000)
#define | ETH_DMARXNDESCWBF_L3FM ((uint32_t)0x08000000)
#define | ETH_DMARXNDESCWBF_MADRM ((uint32_t)0x07F80000)
#define | ETH_DMARXNDESCWBF_HF ((uint32_t)0x00040000)
#define | ETH_DMARXNDESCWBF_DAF ((uint32_t)0x00020000)
#define | ETH_DMARXNDESCWBF_SAF ((uint32_t)0x00010000)
#define | ETH_DMARXNDESCWBF_VF ((uint32_t)0x00008000)
#define | ETH_DMARXNDESCWBF_ARPNR ((uint32_t)0x00000400)
#define | ETH_DMARXNDESCWBF_OWN ((uint32_t)0x80000000)
Bit definition of Rx normal descriptor register 3 write back format.
#define | ETH_DMARXNDESCWBF_CTXT ((uint32_t)0x40000000)
#define | ETH_DMARXNDESCWBF_FD ((uint32_t)0x20000000)
#define | ETH_DMARXNDESCWBF_LD ((uint32_t)0x10000000)
#define | ETH_DMARXNDESCWBF_RS2V ((uint32_t)0x08000000)
#define | ETH_DMARXNDESCWBF_RS1V ((uint32_t)0x04000000)
#define | ETH_DMARXNDESCWBF_RS0V ((uint32_t)0x02000000)
#define | ETH_DMARXNDESCWBF_CE ((uint32_t)0x01000000)
#define | ETH_DMARXNDESCWBF_GP ((uint32_t)0x00800000)
#define | ETH_DMARXNDESCWBF_RWT ((uint32_t)0x00400000)
#define | ETH_DMARXNDESCWBF_OE ((uint32_t)0x00200000)
#define | ETH_DMARXNDESCWBF_RE ((uint32_t)0x00100000)
#define | ETH_DMARXNDESCWBF_DE ((uint32_t)0x00080000)
#define | ETH_DMARXNDESCWBF_LT ((uint32_t)0x00070000)
#define | ETH_DMARXNDESCWBF_LT_LP ((uint32_t)0x00000000)
#define | ETH_DMARXNDESCWBF_LT_TP ((uint32_t)0x00010000)
#define | ETH_DMARXNDESCWBF_LT_ARP ((uint32_t)0x00030000)
#define | ETH_DMARXNDESCWBF_LT_VLAN ((uint32_t)0x00040000)
#define | ETH_DMARXNDESCWBF_LT_DVLAN ((uint32_t)0x00050000)
#define | ETH_DMARXNDESCWBF_LT_MAC ((uint32_t)0x00060000)
#define | ETH_DMARXNDESCWBF_LT_OAM ((uint32_t)0x00070000)
#define | ETH_DMARXNDESCWBF_ES ((uint32_t)0x00008000)
#define | ETH_DMARXNDESCWBF_PL ((uint32_t)0x00007FFF)
#define | ETH_DMARXCDESC_RTSL ((uint32_t)0xFFFFFFFF)
Bit definition of Rx context descriptor register 0.
#define | ETH_DMARXCDESC_RTSH ((uint32_t)0xFFFFFFFF)
Bit definition of Rx context descriptor register 1.
#define | ETH_DMARXCDESC_OWN ((uint32_t)0x80000000)
Bit definition of Rx context descriptor register 3.
#define | ETH_DMARXCDESC_CTXT ((uint32_t)0x40000000)
#define | ETH_MAX_PACKET_SIZE ((uint32_t)1528)
#define | ETH_HEADER ((uint32_t)14)
#define | ETH_CRC ((uint32_t)4)
#define | ETH_VLAN_TAG ((uint32_t)4)
#define | ETH_MIN_PAYLOAD ((uint32_t)46)
#define | ETH_MAX_PAYLOAD ((uint32_t)1500)
#define | ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000)
#define | HAL_ETH_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_ETH_ERROR_PARAM ((uint32_t)0x00000001U)
#define | HAL_ETH_ERROR_BUSY ((uint32_t)0x00000002U)
#define | HAL_ETH_ERROR_TIMEOUT ((uint32_t)0x00000004U)
#define | HAL_ETH_ERROR_DMA ((uint32_t)0x00000008U)
#define | HAL_ETH_ERROR_MAC ((uint32_t)0x00000010U)
#define | ETH_TX_PACKETS_FEATURES_CSUM ((uint32_t)0x00000001)
#define | ETH_TX_PACKETS_FEATURES_SAIC ((uint32_t)0x00000002)
#define | ETH_TX_PACKETS_FEATURES_VLANTAG ((uint32_t)0x00000004)
#define | ETH_TX_PACKETS_FEATURES_INNERVLANTAG ((uint32_t)0x00000008)
#define | ETH_TX_PACKETS_FEATURES_TSO ((uint32_t)0x00000010)
#define | ETH_TX_PACKETS_FEATURES_CRCPAD ((uint32_t)0x00000020)
#define | ETH_SRC_ADDR_CONTROL_DISABLE ETH_DMATXNDESCRF_SAIC_DISABLE
#define | ETH_SRC_ADDR_INSERT ETH_DMATXNDESCRF_SAIC_INSERT
#define | ETH_SRC_ADDR_REPLACE ETH_DMATXNDESCRF_SAIC_REPLACE
#define | ETH_CRC_PAD_DISABLE ETH_DMATXNDESCRF_CPC_DISABLE
#define | ETH_CRC_PAD_INSERT ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT
#define | ETH_CRC_INSERT ETH_DMATXNDESCRF_CPC_CRC_INSERT
#define | ETH_CRC_REPLACE ETH_DMATXNDESCRF_CPC_CRC_REPLACE
#define | ETH_CHECKSUM_DISABLE ETH_DMATXNDESCRF_CIC_DISABLE
#define | ETH_CHECKSUM_IPHDR_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_INSERT
#define | ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT
#define | ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC
#define | ETH_VLAN_DISABLE ETH_DMATXNDESCRF_VTIR_DISABLE
#define | ETH_VLAN_REMOVE ETH_DMATXNDESCRF_VTIR_REMOVE
#define | ETH_VLAN_INSERT ETH_DMATXNDESCRF_VTIR_INSERT
#define | ETH_VLAN_REPLACE ETH_DMATXNDESCRF_VTIR_REPLACE
#define | ETH_INNER_VLAN_DISABLE ETH_DMATXCDESC_IVTIR_DISABLE
#define | ETH_INNER_VLAN_REMOVE ETH_DMATXCDESC_IVTIR_REMOVE
#define | ETH_INNER_VLAN_INSERT ETH_DMATXCDESC_IVTIR_INSERT
#define | ETH_INNER_VLAN_REPLACE ETH_DMATXCDESC_IVTIR_REPLACE
#define | ETH_CHECKSUM_BYPASSED ETH_DMARXNDESCWBF_IPCB
#define | ETH_CHECKSUM_IP_HEADER_ERROR ETH_DMARXNDESCWBF_IPHE
#define | ETH_CHECKSUM_IP_PAYLOAD_ERROR ETH_DMARXNDESCWBF_IPCE
#define | ETH_IP_HEADER_IPV4 ETH_DMARXNDESCWBF_IPV4
#define | ETH_IP_HEADER_IPV6 ETH_DMARXNDESCWBF_IPV6
#define | ETH_IP_PAYLOAD_UNKNOWN ETH_DMARXNDESCWBF_PT_UNKNOWN
#define | ETH_IP_PAYLOAD_UDP ETH_DMARXNDESCWBF_PT_UDP
#define | ETH_IP_PAYLOAD_TCP ETH_DMARXNDESCWBF_PT_TCP
#define | ETH_IP_PAYLOAD_ICMPN ETH_DMARXNDESCWBF_PT_ICMP
#define | ETH_HASH_FILTER_PASS ETH_DMARXNDESCWBF_HF
#define | ETH_VLAN_FILTER_PASS ETH_DMARXNDESCWBF_VF
#define | ETH_DEST_ADDRESS_FAIL ETH_DMARXNDESCWBF_DAF
#define | ETH_SOURCE_ADDRESS_FAIL ETH_DMARXNDESCWBF_SAF
#define | ETH_L3_FILTER0_MATCH ETH_DMARXNDESCWBF_L3FM
#define | ETH_L3_FILTER1_MATCH (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM)
#define | ETH_L4_FILTER0_MATCH ETH_DMARXNDESCWBF_L4FM
#define | ETH_L4_FILTER1_MATCH (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM)
#define | ETH_DRIBBLE_BIT_ERROR ETH_DMARXNDESCWBF_DE
#define | ETH_RECEIVE_ERROR ETH_DMARXNDESCWBF_RE
#define | ETH_RECEIVE_OVERFLOW ETH_DMARXNDESCWBF_OE
#define | ETH_WATCHDOG_TIMEOUT ETH_DMARXNDESCWBF_RWT
#define | ETH_GIANT_PACKET ETH_DMARXNDESCWBF_GP
#define | ETH_CRC_ERROR ETH_DMARXNDESCWBF_CE
#define | ETH_DMAARBITRATION_RX ETH_DMAMR_DA
#define | ETH_DMAARBITRATION_RX1_TX1 ((uint32_t)0x00000000)
#define | ETH_DMAARBITRATION_RX2_TX1 ETH_DMAMR_PR_2_1
#define | ETH_DMAARBITRATION_RX3_TX1 ETH_DMAMR_PR_3_1
#define | ETH_DMAARBITRATION_RX4_TX1 ETH_DMAMR_PR_4_1
#define | ETH_DMAARBITRATION_RX5_TX1 ETH_DMAMR_PR_5_1
#define | ETH_DMAARBITRATION_RX6_TX1 ETH_DMAMR_PR_6_1
#define | ETH_DMAARBITRATION_RX7_TX1 ETH_DMAMR_PR_7_1
#define | ETH_DMAARBITRATION_RX8_TX1 ETH_DMAMR_PR_8_1
#define | ETH_DMAARBITRATION_TX (ETH_DMAMR_TXPR | ETH_DMAMR_DA)
#define | ETH_DMAARBITRATION_TX1_RX1 ((uint32_t)0x00000000)
#define | ETH_DMAARBITRATION_TX2_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)
#define | ETH_DMAARBITRATION_TX3_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1)
#define | ETH_DMAARBITRATION_TX4_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1)
#define | ETH_DMAARBITRATION_TX5_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1)
#define | ETH_DMAARBITRATION_TX6_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1)
#define | ETH_DMAARBITRATION_TX7_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1)
#define | ETH_DMAARBITRATION_TX8_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1)
#define | ETH_BURSTLENGTH_FIXED ETH_DMASBMR_FB
#define | ETH_BURSTLENGTH_MIXED ETH_DMASBMR_MB
#define | ETH_BURSTLENGTH_UNSPECIFIED ((uint32_t)0x00000000)
#define | ETH_TXDMABURSTLENGTH_1BEAT ETH_DMACTCR_TPBL_1PBL
#define | ETH_TXDMABURSTLENGTH_2BEAT ETH_DMACTCR_TPBL_2PBL
#define | ETH_TXDMABURSTLENGTH_4BEAT ETH_DMACTCR_TPBL_4PBL
#define | ETH_TXDMABURSTLENGTH_8BEAT ETH_DMACTCR_TPBL_8PBL
#define | ETH_TXDMABURSTLENGTH_16BEAT ETH_DMACTCR_TPBL_16PBL
#define | ETH_TXDMABURSTLENGTH_32BEAT ETH_DMACTCR_TPBL_32PBL
#define | ETH_RXDMABURSTLENGTH_1BEAT ETH_DMACRCR_RPBL_1PBL
#define | ETH_RXDMABURSTLENGTH_2BEAT ETH_DMACRCR_RPBL_2PBL
#define | ETH_RXDMABURSTLENGTH_4BEAT ETH_DMACRCR_RPBL_4PBL
#define | ETH_RXDMABURSTLENGTH_8BEAT ETH_DMACRCR_RPBL_8PBL
#define | ETH_RXDMABURSTLENGTH_16BEAT ETH_DMACRCR_RPBL_16PBL
#define | ETH_RXDMABURSTLENGTH_32BEAT ETH_DMACRCR_RPBL_32PBL
#define | ETH_DMA_NORMAL_IT ETH_DMACIER_NIE
#define | ETH_DMA_ABNORMAL_IT ETH_DMACIER_AIE
#define | ETH_DMA_CONTEXT_DESC_ERROR_IT ETH_DMACIER_CDEE
#define | ETH_DMA_FATAL_BUS_ERROR_IT ETH_DMACIER_FBEE
#define | ETH_DMA_EARLY_RX_IT ETH_DMACIER_ERIE
#define | ETH_DMA_EARLY_TX_IT ETH_DMACIER_ETIE
#define | ETH_DMA_RX_WATCHDOG_TIMEOUT_IT ETH_DMACIER_RWTE
#define | ETH_DMA_RX_PROCESS_STOPPED_IT ETH_DMACIER_RSE
#define | ETH_DMA_RX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_RBUE
#define | ETH_DMA_RX_IT ETH_DMACIER_RIE
#define | ETH_DMA_TX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_TBUE
#define | ETH_DMA_TX_PROCESS_STOPPED_IT ETH_DMACIER_TXSE
#define | ETH_DMA_TX_IT ETH_DMACIER_TIE
#define | ETH_DMA_RX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
#define | ETH_DMA_RX_DESC_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0)
#define | ETH_DMA_RX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1)
#define | ETH_DMA_RX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0)
#define | ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_REB_BIT_2
#define | ETH_DMA_TX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
#define | ETH_DMA_TX_DESC_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0)
#define | ETH_DMA_TX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1)
#define | ETH_DMA_TX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0)
#define | ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_TEB_BIT_2
#define | ETH_DMA_CONTEXT_DESC_ERROR_FLAG ETH_DMACSR_CDE
#define | ETH_DMA_FATAL_BUS_ERROR_FLAG ETH_DMACSR_FBE
#define | ETH_DMA_EARLY_TX_IT_FLAG ETH_DMACSR_ERI
#define | ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG ETH_DMACSR_RWT
#define | ETH_DMA_RX_PROCESS_STOPPED_FLAG ETH_DMACSR_RPS
#define | ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG ETH_DMACSR_RBU
#define | ETH_DMA_TX_PROCESS_STOPPED_FLAG ETH_DMACSR_TPS
#define | ETH_TRANSMITSTOREFORWARD ETH_MTLTQOMR_TSF
#define | ETH_TRANSMITTHRESHOLD_32 ETH_MTLTQOMR_TTC_32BITS
#define | ETH_TRANSMITTHRESHOLD_64 ETH_MTLTQOMR_TTC_64BITS
#define | ETH_TRANSMITTHRESHOLD_96 ETH_MTLTQOMR_TTC_96BITS
#define | ETH_TRANSMITTHRESHOLD_128 ETH_MTLTQOMR_TTC_128BITS
#define | ETH_TRANSMITTHRESHOLD_192 ETH_MTLTQOMR_TTC_192BITS
#define | ETH_TRANSMITTHRESHOLD_256 ETH_MTLTQOMR_TTC_256BITS
#define | ETH_TRANSMITTHRESHOLD_384 ETH_MTLTQOMR_TTC_384BITS
#define | ETH_TRANSMITTHRESHOLD_512 ETH_MTLTQOMR_TTC_512BITS
#define | ETH_RECEIVESTOREFORWARD ETH_MTLRQOMR_RSF
#define | ETH_RECEIVETHRESHOLD8_64 ETH_MTLRQOMR_RTC_64BITS
#define | ETH_RECEIVETHRESHOLD8_32 ETH_MTLRQOMR_RTC_32BITS
#define | ETH_RECEIVETHRESHOLD8_96 ETH_MTLRQOMR_RTC_96BITS
#define | ETH_RECEIVETHRESHOLD8_128 ETH_MTLRQOMR_RTC_128BITS
#define | ETH_PAUSELOWTHRESHOLD_MINUS_4 ETH_MACTFCR_PLT_MINUS4
#define | ETH_PAUSELOWTHRESHOLD_MINUS_28 ETH_MACTFCR_PLT_MINUS28
#define | ETH_PAUSELOWTHRESHOLD_MINUS_36 ETH_MACTFCR_PLT_MINUS36
#define | ETH_PAUSELOWTHRESHOLD_MINUS_144 ETH_MACTFCR_PLT_MINUS144
#define | ETH_PAUSELOWTHRESHOLD_MINUS_256 ETH_MACTFCR_PLT_MINUS256
#define | ETH_PAUSELOWTHRESHOLD_MINUS_512 ETH_MACTFCR_PLT_MINUS512
#define | ETH_WATCHDOGTIMEOUT_2KB ETH_MACWTR_WTO_2KB
#define | ETH_WATCHDOGTIMEOUT_3KB ETH_MACWTR_WTO_3KB
#define | ETH_WATCHDOGTIMEOUT_4KB ETH_MACWTR_WTO_4KB
#define | ETH_WATCHDOGTIMEOUT_5KB ETH_MACWTR_WTO_5KB
#define | ETH_WATCHDOGTIMEOUT_6KB ETH_MACWTR_WTO_6KB
#define | ETH_WATCHDOGTIMEOUT_7KB ETH_MACWTR_WTO_7KB
#define | ETH_WATCHDOGTIMEOUT_8KB ETH_MACWTR_WTO_8KB
#define | ETH_WATCHDOGTIMEOUT_9KB ETH_MACWTR_WTO_9KB
#define | ETH_WATCHDOGTIMEOUT_10KB ETH_MACWTR_WTO_10KB
#define | ETH_WATCHDOGTIMEOUT_11KB ETH_MACWTR_WTO_12KB
#define | ETH_WATCHDOGTIMEOUT_12KB ETH_MACWTR_WTO_12KB
#define | ETH_WATCHDOGTIMEOUT_13KB ETH_MACWTR_WTO_13KB
#define | ETH_WATCHDOGTIMEOUT_14KB ETH_MACWTR_WTO_14KB
#define | ETH_WATCHDOGTIMEOUT_15KB ETH_MACWTR_WTO_15KB
#define | ETH_WATCHDOGTIMEOUT_16KB ETH_MACWTR_WTO_16KB
#define | ETH_INTERPACKETGAP_96BIT ETH_MACCR_IPG_96BIT
#define | ETH_INTERPACKETGAP_88BIT ETH_MACCR_IPG_88BIT
#define | ETH_INTERPACKETGAP_80BIT ETH_MACCR_IPG_80BIT
#define | ETH_INTERPACKETGAP_72BIT ETH_MACCR_IPG_72BIT
#define | ETH_INTERPACKETGAP_64BIT ETH_MACCR_IPG_64BIT
#define | ETH_INTERPACKETGAP_56BIT ETH_MACCR_IPG_56BIT
#define | ETH_INTERPACKETGAP_48BIT ETH_MACCR_IPG_48BIT
#define | ETH_INTERPACKETGAP_40BIT ETH_MACCR_IPG_40BIT
#define | ETH_SPEED_10M ((uint32_t)0x00000000)
#define | ETH_SPEED_100M ETH_MACCR_FES
#define | ETH_FULLDUPLEX_MODE ETH_MACCR_DM
#define | ETH_HALFDUPLEX_MODE ((uint32_t)0x00000000)
#define | ETH_BACKOFFLIMIT_10 ETH_MACCR_BL_10
#define | ETH_BACKOFFLIMIT_8 ETH_MACCR_BL_8
#define | ETH_BACKOFFLIMIT_4 ETH_MACCR_BL_4
#define | ETH_BACKOFFLIMIT_1 ETH_MACCR_BL_1
#define | ETH_PREAMBLELENGTH_7 ETH_MACCR_PRELEN_7
#define | ETH_PREAMBLELENGTH_5 ETH_MACCR_PRELEN_5
#define | ETH_PREAMBLELENGTH_3 ETH_MACCR_PRELEN_3
#define | ETH_SOURCEADDRESS_DISABLE ((uint32_t)0x00000000)
#define | ETH_SOURCEADDRESS_INSERT_ADDR0 ETH_MACCR_SARC_INSADDR0
#define | ETH_SOURCEADDRESS_INSERT_ADDR1 ETH_MACCR_SARC_INSADDR1
#define | ETH_SOURCEADDRESS_REPLACE_ADDR0 ETH_MACCR_SARC_REPADDR0
#define | ETH_SOURCEADDRESS_REPLACE_ADDR1 ETH_MACCR_SARC_REPADDR1
#define | ETH_CTRLPACKETS_BLOCK_ALL ETH_MACPFR_PCF_BLOCKALL
#define | ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA
#define | ETH_CTRLPACKETS_FORWARD_ALL ETH_MACPFR_PCF_FORWARDALL
#define | ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER
#define | ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U)
#define | ETH_VLANTAGCOMPARISON_12BIT ETH_MACVTR_ETV
#define | ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U)
#define | ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U)
#define | ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U)
#define | ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U)
#define | ETH_MAC_RX_STATUS_IT ETH_MACIER_RXSTSIE
#define | ETH_MAC_TX_STATUS_IT ETH_MACIER_TXSTSIE
#define | ETH_MAC_TIMESTAMP_IT ETH_MACIER_TSIE
#define | ETH_MAC_LPI_IT ETH_MACIER_LPIIE
#define | ETH_MAC_PMT_IT ETH_MACIER_PMTIE
#define | ETH_MAC_PHY_IT ETH_MACIER_PHYIE
#define | ETH_WAKEUP_PACKET_RECIEVED ETH_MACPCSR_RWKPRCVD
#define | ETH_MAGIC_PACKET_RECIEVED ETH_MACPCSR_MGKPRCVD
#define | ETH_RECEIVE_WATCHDOG_TIMEOUT ETH_MACRXTXSR_RWT
#define | ETH_EXECESSIVE_COLLISIONS ETH_MACRXTXSR_EXCOL
#define | ETH_LATE_COLLISIONS ETH_MACRXTXSR_LCOL
#define | ETH_EXECESSIVE_DEFERRAL ETH_MACRXTXSR_EXDEF
#define | ETH_LOSS_OF_CARRIER ETH_MACRXTXSR_LCARR
#define | ETH_NO_CARRIER ETH_MACRXTXSR_NCARR
#define | ETH_TRANSMIT_JABBR_TIMEOUT ETH_MACRXTXSR_TJT
#define | __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
Reset ETH handle state.
#define | __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__))
Enables the specified ETHERNET DMA interrupts.
#define | __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))
Disables the specified ETHERNET DMA interrupts.
#define | __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACIER & (__INTERRUPT__)) == (__INTERRUPT__))
Gets the ETHERNET DMA IT source enabled or disabled.
#define | __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACSR & (__INTERRUPT__)) == (__INTERRUPT__))
Gets the ETHERNET DMA IT pending bit.
#define | __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))
Clears the ETHERNET DMA IT pending bit.
#define | __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))
Checks whether the specified ETHERNET DMA flag is set or not.
#define | __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))
Clears the specified ETHERNET DMA flag.
#define | __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))
Enables the specified ETHERNET MAC interrupts.
#define | __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))
Disables the specified ETHERNET MAC interrupts.
#define | __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__))
Checks whether the specified ETHERNET MAC flag is set or not.
#define | ETH_WAKEUP_EXTI_LINE ((uint32_t)0x00400000) /* !< 86 - 64 = 22 */
#define | __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI_D1->IMR3 |= (__EXTI_LINE__))
Enable the ETH WAKEUP Exti Line.
#define | __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 & (__EXTI_LINE__))
checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
#define | __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__))
Clear the ETH WAKEUP Exti flag.
#define | __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__)
enable rising edge interrupt on selected EXTI line.
#define | __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__)
enable falling edge interrupt on selected EXTI line.
#define | __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__)
enable falling edge interrupt on selected EXTI line.
#define | __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__))
Generates a Software interrupt on selected EXTI line.

Typedefs

struct {
uint32_t DESC0
uint32_t DESC1
uint32_t DESC2
uint32_t DESC3
uint32_t BackupAddr0
uint32_t BackupAddr1
} ETH_DMADescTypeDef
ETH DMA Descriptor structure definition.
typedef struct __ETH_BufferTypeDef | ETH_BufferTypeDef
ETH Buffers List structure definition.

Enumerations

enum | ETH_MediaInterfaceTypeDef { HAL_ETH_MII_MODE = 0x00, HAL_ETH_RMII_MODE = 0x01 }
HAL ETH Media Interfaces enum definition. More...
enum HAL_ETH_StateTypeDef {
HAL_ETH_STATE_RESET = 0x00, HAL_ETH_STATE_READY = 0x10, HAL_ETH_STATE_BUSY = 0x23, HAL_ETH_STATE_BUSY_TX = 0x21,
HAL_ETH_STATE_BUSY_RX = 0x22, HAL_ETH_STATE_ERROR = 0xE0
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_ETH_Init (ETH_HandleTypeDef *heth)
Initialize the Ethernet peripheral registers.
HAL_StatusTypeDef | HAL_ETH_DeInit (ETH_HandleTypeDef *heth)
DeInitializes the ETH peripheral.
__weak void | HAL_ETH_MspInit (ETH_HandleTypeDef *heth)
Initializes the ETH MSP.
__weak void | HAL_ETH_MspDeInit (ETH_HandleTypeDef *heth)
DeInitializes ETH MSP.
HAL_StatusTypeDef | HAL_ETH_DescAssignMemory (ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1, uint8_t *pBuffer2)
Assign memory buffers to a DMA Rx descriptor.
HAL_StatusTypeDef | HAL_ETH_Start (ETH_HandleTypeDef *heth)
Enables Ethernet MAC and DMA reception and transmission.
HAL_StatusTypeDef | HAL_ETH_Start_IT (ETH_HandleTypeDef *heth)
Enables Ethernet MAC and DMA reception/transmission in Interrupt mode.
HAL_StatusTypeDef | HAL_ETH_Stop (ETH_HandleTypeDef *heth)
Stop Ethernet MAC and DMA reception/transmission.
HAL_StatusTypeDef | HAL_ETH_Stop_IT (ETH_HandleTypeDef *heth)
Stop Ethernet MAC and DMA reception/transmission in Interrupt mode.
uint8_t | HAL_ETH_IsRxDataAvailable (ETH_HandleTypeDef *heth)
Checks for received Packets.
HAL_StatusTypeDef | HAL_ETH_GetRxDataBuffer (ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer)
This function gets the buffer address of last received Packet.
HAL_StatusTypeDef | HAL_ETH_GetRxDataLength (ETH_HandleTypeDef *heth, uint32_t *Length)
This function gets the length of last received Packet.
HAL_StatusTypeDef | HAL_ETH_GetRxDataInfo (ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo)
Get the Rx data info (Packet type, VLAN tag, Filters status, ...)
HAL_StatusTypeDef | HAL_ETH_BuildRxDescriptors (ETH_HandleTypeDef *heth)
This function gives back Rx Desc of the last received Packet to the DMA, so ETH DMA will be able to use these descriptors to receive next Packets.
HAL_StatusTypeDef | HAL_ETH_Transmit (ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout)
Sends an Ethernet Packet in polling mode.
HAL_StatusTypeDef | HAL_ETH_Transmit_IT (ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig)
Sends an Ethernet Packet in interrupt mode.
HAL_StatusTypeDef | HAL_ETH_WritePHYRegister (ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue)
Writes to a PHY register.
HAL_StatusTypeDef | HAL_ETH_ReadPHYRegister (ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue)
Read a PHY register.
void | HAL_ETH_IRQHandler (ETH_HandleTypeDef *heth)
This function handles ETH interrupt request.
__weak void | HAL_ETH_TxCpltCallback (ETH_HandleTypeDef *heth)
Tx Transfer completed callbacks.
__weak void | HAL_ETH_RxCpltCallback (ETH_HandleTypeDef *heth)
Rx Transfer completed callbacks.
__weak void | HAL_ETH_DMAErrorCallback (ETH_HandleTypeDef *heth)
Ethernet DMA transfer error callbacks.
__weak void | HAL_ETH_MACErrorCallback (ETH_HandleTypeDef *heth)
Ethernet MAC transfer error callbacks.
__weak void | HAL_ETH_PMTCallback (ETH_HandleTypeDef *heth)
Ethernet Power Management module IT callback.
__weak void | HAL_ETH_EEECallback (ETH_HandleTypeDef *heth)
Energy Efficient Etherent IT callback.
__weak void | HAL_ETH_WakeUpCallback (ETH_HandleTypeDef *heth)
ETH WAKEUP interrupt callback.
HAL_StatusTypeDef | HAL_ETH_GetMACConfig (ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
Get the configuration of the MAC and MTL subsystems.
HAL_StatusTypeDef | HAL_ETH_GetDMAConfig (ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
Get the configuration of the DMA.
HAL_StatusTypeDef | HAL_ETH_SetMACConfig (ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
Set the MAC configuration.
HAL_StatusTypeDef | HAL_ETH_SetDMAConfig (ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
Set the ETH DMA configuration.
void | HAL_ETH_SetMDIOClockRange (ETH_HandleTypeDef *heth)
Configures the Clock range of ETH MDIO interface.
void | HAL_ETH_SetRxVLANIdentifier (ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier)
Set the VLAN Identifier for Rx packets.
HAL_StatusTypeDef | HAL_ETH_GetMACFilterConfig (ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
Get the ETH MAC (L2) Filters configuration.
HAL_StatusTypeDef | HAL_ETH_SetMACFilterConfig (ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
Set the ETH MAC (L2) Filters configuration.
HAL_StatusTypeDef | HAL_ETH_SetHashTable (ETH_HandleTypeDef *heth, uint32_t *pHashTable)
Set the ETH Hash Table Value.
HAL_StatusTypeDef | HAL_ETH_SetSourceMACAddrMatch (ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr)
Set the source MAC Address to be matched.
void | HAL_ETH_EnterPowerDownMode (ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig)
Enters the Power down mode.
void | HAL_ETH_ExitPowerDownMode (ETH_HandleTypeDef *heth)
Exits from the Power down mode.
HAL_StatusTypeDef | HAL_ETH_SetWakeUpFilter (ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count)
Set the WakeUp filter.
HAL_ETH_StateTypeDef | HAL_ETH_GetState (ETH_HandleTypeDef *heth)
Returns the ETH state.
uint32_t | HAL_ETH_GetError (ETH_HandleTypeDef *heth)
Returns the ETH error code.
uint32_t | HAL_ETH_GetDMAError (ETH_HandleTypeDef *heth)
Returns the ETH DMA error code.
uint32_t | HAL_ETH_GetMACError (ETH_HandleTypeDef *heth)
Returns the ETH MAC error code.
uint32_t | HAL_ETH_GetMACWakeUpSource (ETH_HandleTypeDef *heth)
Returns the ETH MAC WakeUp event source.

Detailed Description

Header file of ETH HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_eth.h.

Variable Documentation

uint32_t BackupAddr0

Definition at line 84 of file stm32h7xx_hal_eth.h.

uint32_t BackupAddr1

Definition at line 85 of file stm32h7xx_hal_eth.h.

uint32_t DESC0

Definition at line 80 of file stm32h7xx_hal_eth.h.

uint32_t DESC1

Definition at line 81 of file stm32h7xx_hal_eth.h.

uint32_t DESC2

Definition at line 82 of file stm32h7xx_hal_eth.h.

uint32_t DESC3

Definition at line 83 of file stm32h7xx_hal_eth.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_usart.h File Reference

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Data Structures | Defines | Enumerations | Functions | Variables
stm32h7xx_hal_usart.h File Reference

Header file of USART HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_usart_ex.h"

Go to the source code of this file.

Data Structures

struct | USART_InitTypeDef
USART Init Structure definition. More...
struct | USART_HandleTypeDef
USART handle Structure definition. More...

Defines

#define | __STM3H7xx_HAL_USART_H
#define | USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define | USART_STOPBITS_1 ((uint32_t)0x00000000U)
#define | USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
#define | USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define | USART_PARITY_NONE ((uint32_t)0x00000000U)
#define | USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | USART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | USART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | USART_OVERSAMPLING_16 ((uint32_t)0x00000000U)
#define | USART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
#define | USART_CLOCK_DISABLE ((uint32_t)0x00000000U)
#define | USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
#define | USART_POLARITY_LOW ((uint32_t)0x00000000U)
#define | USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
#define | USART_PHASE_1EDGE ((uint32_t)0x00000000U)
#define | USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
#define | USART_LASTBIT_DISABLE ((uint32_t)0x00000000U)
#define | USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
#define | USART_PRESCALER_DIV1 ((uint32_t)0x00000000U)
#define | USART_PRESCALER_DIV2 ((uint32_t)0x00000001U)
#define | USART_PRESCALER_DIV4 ((uint32_t)0x00000002U)
#define | USART_PRESCALER_DIV6 ((uint32_t)0x00000003U)
#define | USART_PRESCALER_DIV8 ((uint32_t)0x00000004U)
#define | USART_PRESCALER_DIV10 ((uint32_t)0x00000005U)
#define | USART_PRESCALER_DIV12 ((uint32_t)0x00000006U)
#define | USART_PRESCALER_DIV16 ((uint32_t)0x00000007U)
#define | USART_PRESCALER_DIV32 ((uint32_t)0x00000008U)
#define | USART_PRESCALER_DIV64 ((uint32_t)0x00000009U)
#define | USART_PRESCALER_DIV128 ((uint32_t)0x0000000AU)
#define | USART_PRESCALER_DIV256 ((uint32_t)0x0000000BU)
#define | USART_NSS_HW ((uint32_t)0x00000000U)
#define | USART_NSS_SW ((uint32_t)USART_CR2_DIS_NSS)
#define | USART_SLAVEMODE_DISABLE ((uint32_t)0x00000000U)
#define | USART_SLAVEMODE_ENABLE ((uint32_t)USART_CR2_SLVEN)
#define | USART_FIFOMODE_DISABLE ((uint32_t)0x00000000U)
#define | USART_FIFOMODE_ENABLE ((uint32_t)USART_CR1_FIFOEN)
#define | USART_TXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000U)
#define | USART_TXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_TXFTCFG_0)
#define | USART_TXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_TXFTCFG_1)
#define | USART_TXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1))
#define | USART_TXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_TXFTCFG_2)
#define | USART_TXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0))
#define | USART_RXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000U)
#define | USART_RXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_RXFTCFG_0)
#define | USART_RXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_RXFTCFG_1)
#define | USART_RXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1))
#define | USART_RXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_RXFTCFG_2)
#define | USART_RXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0))
#define | USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)
#define | USART_FLAG_TXFT USART_ISR_TXFT
#define | USART_FLAG_RXFT USART_ISR_RXFT
#define | USART_FLAG_RXFF USART_ISR_RXFF
#define | USART_FLAG_TXFE USART_ISR_TXFE
#define | USART_FLAG_REACK USART_ISR_REACK
#define | USART_FLAG_TEACK USART_ISR_TEACK
#define | USART_FLAG_BUSY USART_ISR_BUSY
#define | USART_FLAG_UDR USART_ISR_UDR
#define | USART_FLAG_LBDF USART_ISR_LBDF
#define | USART_FLAG_TXE USART_ISR_TXE
#define | USART_FLAG_TXFNF USART_ISR_TXE
#define | USART_FLAG_TC USART_ISR_TC
#define | USART_FLAG_RXNE USART_ISR_RXNE
#define | USART_FLAG_RXFNE USART_ISR_RXNE
#define | USART_FLAG_IDLE USART_ISR_IDLE
#define | USART_FLAG_ORE USART_ISR_ORE
#define | USART_FLAG_NE USART_ISR_NE
#define | USART_FLAG_FE USART_ISR_FE
#define | USART_FLAG_PE USART_ISR_PE
#define | USART_IT_PE ((uint16_t)0x0028U)
#define | USART_IT_TXE ((uint16_t)0x0727U)
#define | USART_IT_TC ((uint16_t)0x0626U)
#define | USART_IT_RXNE ((uint16_t)0x0525U)
#define | USART_IT_IDLE ((uint16_t)0x0424U)
#define | USART_IT_ERR ((uint16_t)0x0060U)
#define | USART_IT_RXFF ((uint16_t)0x183FU)
#define | USART_IT_TXFE ((uint16_t)0x173EU)
#define | USART_IT_RXFT ((uint16_t)0x1A7CU)
#define | USART_IT_TXFT ((uint16_t)0x1B77U)
#define | USART_IT_UDR ((uint16_t)0x0D00U)
#define | USART_IT_ORE ((uint16_t)0x0300U)
#define | USART_IT_NE ((uint16_t)0x0200U)
#define | USART_IT_FE ((uint16_t)0x0100U)
#define | USART_CLEAR_PEF USART_ICR_PECF
#define | USART_CLEAR_FEF USART_ICR_FECF
#define | USART_CLEAR_NEF USART_ICR_NCF
#define | USART_CLEAR_OREF USART_ICR_ORECF
#define | USART_CLEAR_IDLEF USART_ICR_IDLECF
#define | USART_CLEAR_TCF USART_ICR_TCCF
#define | USART_CLEAR_UDRCF USART_ICR_UDRCF
#define | USART_CLEAR_TXFECF USART_ICR_TXFECF
#define | USART_IT_MASK ((uint16_t)0x001FU)
#define | __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
Reset USART handle state.
#define | __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified USART flag is set or not.
#define | __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified USART pending flag.
#define | __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified USART interrupt.
#define | __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified USART interrupt.
#define | __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
Check whether the specified USART interrupt has occurred or not.
#define | __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified USART interrupt source is enabled or not.
#define | __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified USART ISR flag, in setting the proper ICR register flag.
#define | __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_PEF)
Clear the USART PE pending flag.
#define | __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_FEF)
Clear the USART FE pending flag.
#define | __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_NEF)
Clear the USART NE pending flag.
#define | __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_OREF)
Clear the USART ORE pending flag.
#define | __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_IDLEF)
Clear the USART IDLE pending flag.
#define | __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_UDRCF)
Clear the USART UDR pending flag.
#define | __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_TXFECF)
Clear the USART TX FIFO empty clear flag.
#define | __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__))
Set a specific USART request flag.
#define | __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the USART one bit sample method.
#define | __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the USART one bit sample method.
#define | __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable USART.
#define | __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable USART.
#define | USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the USART clock source.
#define | USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __PRESCALER__) (((((__PCLK__)/USARTPrescTable[(__PRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__))
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
Check USART Baud rate.
#define | IS_USART_STOPBITS(__STOPBITS__)
Ensure that USART frame number of stop bits is valid.
#define | IS_USART_PARITY(__PARITY__)
Ensure that USART frame parity is valid.
#define | IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3U) == 0x00U) && ((__MODE__) != (uint32_t)0x00U))
Ensure that USART communication mode is valid.
#define | IS_USART_OVERSAMPLING(__SAMPLING__)
Ensure that USART oversampling is valid.
#define | IS_USART_CLOCK(__CLOCK__)
Ensure that USART clock state is valid.
#define | IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
Ensure that USART frame polarity is valid.
#define | IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
Ensure that USART frame phase is valid.
#define | IS_USART_LASTBIT(__LASTBIT__)
Ensure that USART frame last bit clock pulse setting is valid.
#define | IS_USART_REQUEST_PARAMETER(__PARAM__)
Ensure that USART request parameter is valid.
#define | IS_USART_PRESCALER(__PRESCALER__)
Ensure that USART Prescaler is valid.
#define | IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HW) || ((__NSS__) == USART_NSS_SW))
Ensure that USART NSS is valid.
#define | IS_USART_FIFO_MODE_STATE(__STATE__)
Ensure that USART FIFO mode is valid.
#define | IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that USART TXFIFO threshold level is valid.
#define | IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that USART RXFIFO threshold level is valid.
#define | IS_USART_SLAVEMODE(__STATE__)
Ensure that USART Slave Mode is valid.

Enumerations

enum HAL_USART_StateTypeDef {
HAL_USART_STATE_RESET = 0x00U, HAL_USART_STATE_READY = 0x01U, HAL_USART_STATE_BUSY = 0x02U, HAL_USART_STATE_BUSY_TX = 0x12U,
HAL_USART_STATE_BUSY_RX = 0x22U, HAL_USART_STATE_BUSY_TX_RX = 0x32U, HAL_USART_STATE_TIMEOUT = 0x03U, HAL_USART_STATE_ERROR = 0x04U
}
HAL USART State structures definition. More...
enum HAL_USART_ErrorTypeDef {
HAL_USART_ERROR_NONE = 0x00U, HAL_USART_ERROR_PE = 0x01U, HAL_USART_ERROR_NE = 0x02U, HAL_USART_ERROR_FE = 0x04U,
HAL_USART_ERROR_ORE = 0x08U, HAL_USART_ERROR_DMA = 0x10U, HAL_USART_ERROR_UDR = 0x11U
}
HAL USART Error Code structure definition. More...
enum USART_ClockSourceTypeDef {
USART_CLOCKSOURCE_D2PCLK1 = 0x00U, USART_CLOCKSOURCE_D2PCLK2 = 0x01U, USART_CLOCKSOURCE_D3PCLK1 = 0x02U, USART_CLOCKSOURCE_PLL2 = 0x04U,
USART_CLOCKSOURCE_HSI = 0x08U, USART_CLOCKSOURCE_CSI = 0x10U, USART_CLOCKSOURCE_LSE = 0x20U, USART_CLOCKSOURCE_PLL3 = 0x40U,
USART_CLOCKSOURCE_UNDEFINED = 0x80U
}
USART clock sources definitions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitialize the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
Initialize the USART MSP.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
DeInitialize the USART MSP.
HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_Abort (USART_HandleTypeDef *husart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_USART_Abort_IT (USART_HandleTypeDef *husart)
Abort ongoing transfers (Interrupt mode).
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
Handle USART interrupt request.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callback.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callback.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callback.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callback.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callback.
__weak void | HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
USART Abort Complete callback.
HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
Return the USART handle state.
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Variables

static const uint16_t | USARTPrescTable [12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}

Detailed Description

Header file of USART HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_usart.h.

Define Documentation

#define __STM3H7xx_HAL_USART_H

Definition at line 40 of file stm32h7xx_hal_usart.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- _ -

  • __HAL_ADC_CLEAR_FLAG : stm32h7xx_hal_adc.h
  • __HAL_ADC_DISABLE_IT : stm32h7xx_hal_adc.h
  • __HAL_ADC_ENABLE_IT : stm32h7xx_hal_adc.h
  • __HAL_ADC_GET_FLAG : stm32h7xx_hal_adc.h
  • __HAL_ADC_GET_IT_SOURCE : stm32h7xx_hal_adc.h
  • __HAL_ADC_RESET_HANDLE_STATE : stm32h7xx_hal_adc.h
  • __HAL_BDMA_GET_GI_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_CEC_CLEAR_FLAG : stm32h7xx_hal_cec.h
  • __HAL_CEC_CLEAR_OAR : stm32h7xx_hal_cec.h
  • __HAL_CEC_DISABLE : stm32h7xx_hal_cec.h
  • __HAL_CEC_DISABLE_IT : stm32h7xx_hal_cec.h
  • __HAL_CEC_ENABLE : stm32h7xx_hal_cec.h
  • __HAL_CEC_ENABLE_IT : stm32h7xx_hal_cec.h
  • __HAL_CEC_FIRST_BYTE_TX_SET : stm32h7xx_hal_cec.h
  • __HAL_CEC_GET_FLAG : stm32h7xx_hal_cec.h
  • __HAL_CEC_GET_IT_SOURCE : stm32h7xx_hal_cec.h
  • __HAL_CEC_GET_TRANSMISSION_END_FLAG : stm32h7xx_hal_cec.h
  • __HAL_CEC_GET_TRANSMISSION_START_FLAG : stm32h7xx_hal_cec.h
  • __HAL_CEC_LAST_BYTE_TX_SET : stm32h7xx_hal_cec.h
  • __HAL_CEC_RESET_HANDLE_STATE : stm32h7xx_hal_cec.h
  • __HAL_CEC_SET_OAR : stm32h7xx_hal_cec.h
  • __HAL_COMP_CLEAR_C1IFLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_CLEAR_C2IFLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_CLEAR_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_CLEAR_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GENERATE_SWIT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GET_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTID3_DISABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTID3_ENABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_CLEAR_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GENERATE_SWIT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GET_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTID3_DISABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTID3_ENABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_DISABLE : stm32h7xx_hal_comp.h
  • __HAL_COMP_DISABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_DISABLE_OR : stm32h7xx_hal_comp.h
  • __HAL_COMP_ENABLE : stm32h7xx_hal_comp.h
  • __HAL_COMP_ENABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_ENABLE_OR : stm32h7xx_hal_comp.h
  • __HAL_COMP_GET_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_GET_IT_SOURCE : stm32h7xx_hal_comp.h
  • __HAL_COMP_IS_LOCKED : stm32h7xx_hal_comp.h
  • __HAL_COMP_LOCK : stm32h7xx_hal_comp.h
  • __HAL_COMP_RESET_HANDLE_STATE : stm32h7xx_hal_comp.h
  • __HAL_CRC_DR_RESET : stm32h7xx_hal_crc.h
  • __HAL_CRC_GET_IDR : stm32h7xx_hal_crc.h
  • __HAL_CRC_INITIALCRCVALUE_CONFIG : stm32h7xx_hal_crc.h
  • __HAL_CRC_OUTPUTREVERSAL_DISABLE : stm32h7xx_hal_crc_ex.h
  • __HAL_CRC_OUTPUTREVERSAL_ENABLE : stm32h7xx_hal_crc_ex.h
  • __HAL_CRC_POLYNOMIAL_CONFIG : stm32h7xx_hal_crc_ex.h
  • __HAL_CRC_RESET_HANDLE_STATE : stm32h7xx_hal_crc.h
  • __HAL_CRC_SET_IDR : stm32h7xx_hal_crc.h
  • __HAL_CRYP_DISABLE : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_DISABLE_IT : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_ENABLE : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_ENABLE_IT : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_GET_FLAG : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_GET_IT : stm32h7xx_hal_cryp.h
  • __HAL_DAC_CLEAR_FLAG : stm32h7xx_hal_dac.h
  • __HAL_DAC_DISABLE : stm32h7xx_hal_dac.h
  • __HAL_DAC_DISABLE_IT : stm32h7xx_hal_dac.h
  • __HAL_DAC_ENABLE : stm32h7xx_hal_dac.h
  • __HAL_DAC_ENABLE_IT : stm32h7xx_hal_dac.h
  • __HAL_DAC_GET_FLAG : stm32h7xx_hal_dac.h
  • __HAL_DAC_GET_IT_SOURCE : stm32h7xx_hal_dac.h
  • __HAL_DAC_RESET_HANDLE_STATE : stm32h7xx_hal_dac.h
  • __HAL_DBGMCU_FREEZE_FDCAN : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_HRTIM : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_IWDG1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM5 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_RTC : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM12 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM13 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM14 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM15 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM16 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM17 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM5 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM6 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM7 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM8 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_WWDG1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_FDCAN : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_HRTIM : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_I2C1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_I2C2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_I2C3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_I2C4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_IWDG1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_LPTIM1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_LPTIM2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_LPTIM3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_LPTIM4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_LPTIM5 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_RTC : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM12 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM13 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM14 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM15 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM16 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM17 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM5 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM6 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM7 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM8 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_WWDG1 : stm32h7xx_hal.h
  • __HAL_DCMI_CLEAR_FLAG : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_DISABLE : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_DISABLE_IT : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_ENABLE : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_ENABLE_IT : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_GET_FLAG : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_GET_IT_SOURCE : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_RESET_HANDLE_STATE : stm32h7xx_hal_dcmi.h
  • __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE : stm32h7xx_hal_dfsdm.h
  • __HAL_DFSDM_FILTER_RESET_HANDLE_STATE : stm32h7xx_hal_dfsdm.h
  • __HAL_DMA2D_CLEAR_FLAG : stm32h7xx_hal_dma2d.h
  • __HAL_DMA2D_DISABLE_IT : stm32h7xx_hal_dma2d.h
  • __HAL_DMA2D_ENABLE : stm32h7xx_hal_dma2d.h
  • __HAL_DMA2D_ENABLE_IT : stm32h7xx_hal_dma2d.h
  • __HAL_DMA2D_GET_FLAG : stm32h7xx_hal_dma2d.h
  • __HAL_DMA2D_GET_IT_SOURCE : stm32h7xx_hal_dma2d.h
  • __HAL_DMA2D_RESET_HANDLE_STATE : stm32h7xx_hal_dma2d.h
  • __HAL_DMA_CLEAR_FLAG : stm32h7xx_hal_dma.h
  • __HAL_DMA_D2_DISABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_DMA_D2_ENABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_DMA_D2_GET_IT_SOURCE : stm32h7xx_hal_dma.h
  • __HAL_DMA_D3_DISABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_DMA_D3_ENABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_DMA_D3_GET_IT_SOURCE : stm32h7xx_hal_dma.h
  • __HAL_DMA_DISABLE : stm32h7xx_hal_dma.h
  • __HAL_DMA_DISABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_DMA_ENABLE : stm32h7xx_hal_dma.h
  • __HAL_DMA_ENABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_COUNTER : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_DME_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_FE_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_FLAG : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_FS : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_HT_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_IT_SOURCE : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_TC_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_TE_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_DMA_RESET_HANDLE_STATE : stm32h7xx_hal_dma.h
  • __HAL_DMA_SET_COUNTER : stm32h7xx_hal_dma.h
  • __HAL_ETH_DMA_CLEAR_FLAG : stm32h7xx_hal_eth.h
  • __HAL_ETH_DMA_CLEAR_IT : stm32h7xx_hal_eth.h
  • __HAL_ETH_DMA_DISABLE_IT : stm32h7xx_hal_eth.h
  • __HAL_ETH_DMA_ENABLE_IT : stm32h7xx_hal_eth.h
  • __HAL_ETH_DMA_GET_FLAG : stm32h7xx_hal_eth.h
  • __HAL_ETH_DMA_GET_IT : stm32h7xx_hal_eth.h
  • __HAL_ETH_DMA_GET_IT_SOURCE : stm32h7xx_hal_eth.h
  • __HAL_ETH_MAC_DISABLE_IT : stm32h7xx_hal_eth.h
  • __HAL_ETH_MAC_ENABLE_IT : stm32h7xx_hal_eth.h
  • __HAL_ETH_MAC_GET_IT : stm32h7xx_hal_eth.h
  • __HAL_ETH_RESET_HANDLE_STATE : stm32h7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG : stm32h7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_ENABLE_IT : stm32h7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT : stm32h7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_GET_FLAG : stm32h7xx_hal_eth.h
  • __HAL_FDCAN_CLEAR_FLAG : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_CLEAR_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_DISABLE_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_ENABLE_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_GET_FLAG : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_GET_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_GET_IT_SOURCE : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_RESET_HANDLE_STATE : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_CLEAR_FLAG : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_CLEAR_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_DISABLE_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_ENABLE_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_GET_FLAG : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_GET_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_GET_IT_SOURCE : stm32h7xx_hal_fdcan.h
  • __HAL_FLASH_CALC_BOOT_BASE_ADR : stm32h7xx_hal_flash_ex.h
  • __HAL_FLASH_CLEAR_FLAG : stm32h7xx_hal_flash.h
  • __HAL_FLASH_CLEAR_FLAG_BANK1 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_CLEAR_FLAG_BANK2 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT : stm32h7xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT_BANK1 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT_BANK2 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT : stm32h7xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT_BANK1 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT_BANK2 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG : stm32h7xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG_BANK1 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG_BANK2 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_GET_LATENCY : stm32h7xx_hal_flash.h
  • __HAL_FLASH_SET_LATENCY : stm32h7xx_hal_flash.h
  • __HAL_GPIO_EXTI_CLEAR_FLAG : stm32h7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_IT : stm32h7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GENERATE_SWIT : stm32h7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FLAG : stm32h7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_IT : stm32h7xx_hal_gpio.h
  • __HAL_HASH_CLEAR_FLAG : stm32h7xx_hal_hash.h
  • __HAL_HASH_DISABLE_IT : stm32h7xx_hal_hash.h
  • __HAL_HASH_ENABLE_IT : stm32h7xx_hal_hash.h
  • __HAL_HASH_GET_FLAG : stm32h7xx_hal_hash.h
  • __HAL_HASH_INIT : stm32h7xx_hal_hash.h
  • __HAL_HASH_RESET_HANDLE_STATE : stm32h7xx_hal_hash.h
  • __HAL_HASH_RESET_HANDLE_STATUS : stm32h7xx_hal_hash.h
  • __HAL_HASH_RESET_MDMAT : stm32h7xx_hal_hash.h
  • __HAL_HASH_SET_MDMAT : stm32h7xx_hal_hash.h
  • __HAL_HASH_SET_NBVALIDBITS : stm32h7xx_hal_hash.h
  • __HAL_HASH_START_DIGEST : stm32h7xx_hal_hash.h
  • __HAL_HCD_CLEAR_FLAG : stm32h7xx_hal_hcd.h
  • __HAL_HCD_CLEAR_HC_INT : stm32h7xx_hal_hcd.h
  • __HAL_HCD_DISABLE : stm32h7xx_hal_hcd.h
  • __HAL_HCD_ENABLE : stm32h7xx_hal_hcd.h
  • __HAL_HCD_GET_FLAG : stm32h7xx_hal_hcd.h
  • __HAL_HCD_IS_INVALID_INTERRUPT : stm32h7xx_hal_hcd.h
  • __HAL_HCD_MASK_ACK_HC_INT : stm32h7xx_hal_hcd.h
  • __HAL_HCD_MASK_HALT_HC_INT : stm32h7xx_hal_hcd.h
  • __HAL_HCD_UNMASK_ACK_HC_INT : stm32h7xx_hal_hcd.h
  • __HAL_HCD_UNMASK_HALT_HC_INT : stm32h7xx_hal_hcd.h
  • __HAL_HRTIM_CLEAR_FLAG : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_CLEAR_IT : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_DISABLE : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_DISABLE_IT : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_ENABLE : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_ENABLE_IT : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_GET_FLAG : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_GET_ITSTATUS : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_GETCLOCKPRESCALER : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_GETCOMPARE : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_GETCOUNTER : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_GETPERIOD : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_MASTER_CLEAR_FLAG : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_MASTER_CLEAR_IT : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_MASTER_DISABLE_DMA : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_MASTER_DISABLE_IT : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_MASTER_ENABLE_DMA : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_MASTER_ENABLE_IT : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_MASTER_GET_FLAG : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_MASTER_GET_ITSTATUS : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_RESET_HANDLE_STATE : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_SETCLOCKPRESCALER : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_SETCOMPARE : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_SETCOUNTER : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_SETPERIOD : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_TIMER_CLEAR_FLAG : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_TIMER_CLEAR_IT : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_TIMER_DISABLE_DMA : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_TIMER_DISABLE_IT : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_TIMER_ENABLE_DMA : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_TIMER_ENABLE_IT : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_TIMER_GET_FLAG : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_TIMER_GET_ITSTATUS : stm32h7xx_hal_hrtim.h
  • __HAL_HSEM_CLEAR_FLAG : stm32h7xx_hal_hsem.h
  • __HAL_HSEM_DISABLE_IT : stm32h7xx_hal_hsem.h
  • __HAL_HSEM_ENABLE_IT : stm32h7xx_hal_hsem.h
  • __HAL_HSEM_GET_FLAG : stm32h7xx_hal_hsem.h
  • __HAL_HSEM_GET_IT : stm32h7xx_hal_hsem.h
  • __HAL_HSEM_SEMID_TO_MASK : stm32h7xx_hal_hsem.h
  • __HAL_I2C_CLEAR_FLAG : stm32h7xx_hal_i2c.h
  • __HAL_I2C_DISABLE : stm32h7xx_hal_i2c.h
  • __HAL_I2C_DISABLE_IT : stm32h7xx_hal_i2c.h
  • __HAL_I2C_ENABLE : stm32h7xx_hal_i2c.h
  • __HAL_I2C_ENABLE_IT : stm32h7xx_hal_i2c.h
  • __HAL_I2C_GENERATE_NACK : stm32h7xx_hal_i2c.h
  • __HAL_I2C_GET_FLAG : stm32h7xx_hal_i2c.h
  • __HAL_I2C_GET_IT_SOURCE : stm32h7xx_hal_i2c.h
  • __HAL_I2C_RESET_HANDLE_STATE : stm32h7xx_hal_i2c.h
  • __HAL_I2S_CLEAR_FREFLAG : stm32h7xx_hal_i2s.h
  • __HAL_I2S_CLEAR_OVRFLAG : stm32h7xx_hal_i2s.h
  • __HAL_I2S_CLEAR_UDRFLAG : stm32h7xx_hal_i2s.h
  • __HAL_I2S_DISABLE : stm32h7xx_hal_i2s.h
  • __HAL_I2S_DISABLE_IT : stm32h7xx_hal_i2s.h
  • __HAL_I2S_ENABLE : stm32h7xx_hal_i2s.h
  • __HAL_I2S_ENABLE_IT : stm32h7xx_hal_i2s.h
  • __HAL_I2S_GET_FLAG : stm32h7xx_hal_i2s.h
  • __HAL_I2S_GET_IT_SOURCE : stm32h7xx_hal_i2s.h
  • __HAL_I2S_RESET_HANDLE_STATE : stm32h7xx_hal_i2s.h
  • __HAL_IRDA_CLEAR_FEFLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_FLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IDLEFLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IT : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_NEFLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_OREFLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_PEFLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_DISABLE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_DISABLE_IT : stm32h7xx_hal_irda.h
  • __HAL_IRDA_ENABLE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_ENABLE_IT : stm32h7xx_hal_irda.h
  • __HAL_IRDA_FLUSH_DRREGISTER : stm32h7xx_hal_irda.h
  • __HAL_IRDA_GET_FLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_GET_IT : stm32h7xx_hal_irda.h
  • __HAL_IRDA_GET_IT_SOURCE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_RESET_HANDLE_STATE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_SEND_REQ : stm32h7xx_hal_irda.h
  • __HAL_IWDG_RELOAD_COUNTER : stm32h7xx_hal_iwdg.h
  • __HAL_IWDG_START : stm32h7xx_hal_iwdg.h
  • __HAL_JPEG_CLEAR_FLAG : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_DISABLE : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_DISABLE_IT : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_ENABLE : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_ENABLE_IT : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_GET_FLAG : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_GET_IT_SOURCE : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_RESET_HANDLE_STATE : stm32h7xx_hal_jpeg.h
  • __HAL_LPTIM_AUTORELOAD_SET : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_CLEAR_FLAG : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_COMPARE_SET : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE_IT : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE_IT : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_GET_FLAG : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_GET_IT_SOURCE : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_RESET_COUNTER : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_RESET_COUNTER_AFTERREAD : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_RESET_HANDLE_STATE : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_START_CONTINUOUS : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_START_SINGLE : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_StateTypeDef : stm32h7xx_hal_lptim.h
  • __HAL_LTDC_CLEAR_FLAG : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_DISABLE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_DISABLE_IT : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_ENABLE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_ENABLE_IT : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_GET_FLAG : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_GET_IT_SOURCE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_LAYER_DISABLE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_LAYER_ENABLE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_RESET_HANDLE_STATE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG : stm32h7xx_hal_ltdc.h
  • __HAL_MDIOS_CLEAR_ERROR_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_DISABLE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_DISABLE_IT : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_ENABLE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_ENABLE_IT : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_GET_ERROR_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_GET_IT_SOURCE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_GET_READ_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_GET_WRITE_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_RESET_HANDLE_STATE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDMA_CLEAR_FLAG : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_DISABLE : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_DISABLE_IT : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_ENABLE : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_ENABLE_IT : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_GET_FLAG : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_GET_IT_SOURCE : stm32h7xx_hal_mdma.h
  • __HAL_MMC_CLEAR_FLAG : stm32h7xx_hal_mmc.h
  • __HAL_MMC_CLEAR_IT : stm32h7xx_hal_mmc.h
  • __HAL_MMC_DISABLE_IT : stm32h7xx_hal_mmc.h
  • __HAL_MMC_ENABLE_IT : stm32h7xx_hal_mmc.h
  • __HAL_MMC_GET_FLAG : stm32h7xx_hal_mmc.h
  • __HAL_MMC_GET_IT : stm32h7xx_hal_mmc.h
  • __HAL_NAND_RESET_HANDLE_STATE : stm32h7xx_hal_nand.h
  • __HAL_NOR_RESET_HANDLE_STATE : stm32h7xx_hal_nor.h
  • __HAL_OPAMP_RESET_HANDLE_STATE : stm32h7xx_hal_opamp.h
  • __HAL_PCD_CLEAR_FLAG : stm32h7xx_hal_pcd.h
  • __HAL_PCD_DISABLE : stm32h7xx_hal_pcd.h
  • __HAL_PCD_ENABLE : stm32h7xx_hal_pcd.h
  • __HAL_PCD_GATE_PHYCLOCK : stm32h7xx_hal_pcd.h
  • __HAL_PCD_GET_FLAG : stm32h7xx_hal_pcd.h
  • __HAL_PCD_IS_INVALID_INTERRUPT : stm32h7xx_hal_pcd.h
  • __HAL_PCD_IS_PHY_SUSPENDED : stm32h7xx_hal_pcd.h
  • __HAL_PCD_UNGATE_PHYCLOCK : stm32h7xx_hal_pcd.h
  • __HAL_PWR_AVD_EXTI_CLEAR_FLAG : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_DISABLE_EVENT : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_DISABLE_IT : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_ENABLE_EVENT : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_ENABLE_IT : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_GET_FLAG : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_CLEAR_FLAG : stm32h7xx_hal_pwr.h
  • __HAL_PWR_GET_FLAG : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_CLEAR_FLAG : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_EVENT : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_IT : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_EVENT : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_IT : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GENERATE_SWIT : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GET_FLAG : stm32h7xx_hal_pwr.h
  • __HAL_PWR_VOLTAGESCALING_CONFIG : stm32h7xx_hal_pwr.h
  • __HAL_QSPI_CLEAR_FLAG : stm32h7xx_hal_qspi.h
  • __HAL_QSPI_DISABLE : stm32h7xx_hal_qspi.h
  • __HAL_QSPI_DISABLE_IT : stm32h7xx_hal_qspi.h
  • __HAL_QSPI_ENABLE : stm32h7xx_hal_qspi.h
  • __HAL_QSPI_ENABLE_IT : stm32h7xx_hal_qspi.h
  • __HAL_QSPI_GET_FLAG : stm32h7xx_hal_qspi.h
  • __HAL_QSPI_GET_IT_SOURCE : stm32h7xx_hal_qspi.h
  • __HAL_QSPI_RESET_HANDLE_STATE : stm32h7xx_hal_qspi.h
  • __HAL_RCC_ADC12_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC3_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC3_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_AHB1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB1H_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB1H_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB1L_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB1L_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_FORCE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_RELEASE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CLEAR_IT : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CLEAR_RESET_FLAGS : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CLKP_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_COMP12_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CPU_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CPU_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLEAR_FLAG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLEAR_IT : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_DISABLE_IT : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_ENABLE_IT : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_GET_FLAG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_GET_IT_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_RELOADVALUE_CALCULATE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRYP_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CSI_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CSI_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CSISTOP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CSISTOP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D3SRAM1_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D3SRAM1_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_DFSDM1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DISABLE_IT : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ENABLE_IT : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1MAC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1MAC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1MAC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1MAC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1PTP_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1PTP_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1RX_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1RX_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1TX_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1TX_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_FDCAN_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_ADC_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_CEC_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_CLKP_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_DFSDM1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FDCAN_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FLAG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_FMC_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_HRTIM1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_HSI_DIVIDER : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_I2C1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C2_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C3_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C4_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_IT : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_LPTIM1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPTIM2_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPTIM3_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPTIM4_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPTIM5_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPUART1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_PLL_OSCSOURCE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_QSPI_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_RNG_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_RTC_SOURCE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_SAI1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SAI2_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SAI3_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SAI4A_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SAI4B_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SDMMC_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPDIFRX_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI2_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI3_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI4_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI5_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI6_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SWPMI1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SYSCLK_SOURCE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_UART4_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART5_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART7_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART8_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART2_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART3_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART6_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USB_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HRTIM1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HRTIM1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HRTIM1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_HRTIM1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HRTIM1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSE_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSEM_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSEM_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSEM_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSEM_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI48_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI48_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSISTOP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSISTOP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ITCM_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ITCM_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDECEN_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDECEN_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDECRST_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDECRST_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM4_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM4_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM4_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM4_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM4_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM5_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM5_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM5_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM5_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM5_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM5_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM5_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPUART1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LSE_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LSEDRIVE_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LSI_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LSI_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2_VCIRANGE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2_VCORANGE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2CLKOUT_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2CLKOUT_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2FRACN_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2FRACN_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2FRACN_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3_VCIRANGE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3_VCORANGE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3CLKOUT_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3CLKOUT_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3FRACN_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3FRACN_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3FRACN_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLSOURCE_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL_VCIRANGE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL_VCORANGE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLLFRACN_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLLFRACN_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLLFRACN_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PWR_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PWR_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_QSPI_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_QSPI_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_QSPI_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_QSPI_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_QSPI_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_QSPI_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_QSPI_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLKPRESCALER : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI4_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI4_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI4_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI4_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI4_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI4_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI4A_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI4B_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SWPMI1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCLK_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIMCLKPRESCALER : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB2_OTG_FS_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB2_OTG_FS_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB2_OTG_FS_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB2_OTG_FS_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_VREF_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WAKEUPSTOP_CLK_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RNG_CLEAR_FLAG : stm32h7xx_hal_rng.h
  • __HAL_RNG_CLEAR_IT : stm32h7xx_hal_rng.h
  • __HAL_RNG_DISABLE : stm32h7xx_hal_rng.h
  • __HAL_RNG_DISABLE_IT : stm32h7xx_hal_rng.h
  • __HAL_RNG_ENABLE : stm32h7xx_hal_rng.h
  • __HAL_RNG_ENABLE_IT : stm32h7xx_hal_rng.h
  • __HAL_RNG_GET_FLAG : stm32h7xx_hal_rng.h
  • __HAL_RNG_GET_IT : stm32h7xx_hal_rng.h
  • __HAL_RNG_RESET_HANDLE_STATE : stm32h7xx_hal_rng.h
  • __HAL_RTC_ALARM_CLEAR_FLAG : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_DISABLE_IT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_ENABLE_IT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_CLEAR_FLAG : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_EVENT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_IT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_EVENT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_IT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GENERATE_SWIT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GET_FLAG : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_FLAG : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT_SOURCE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARMA_DISABLE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARMA_ENABLE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARMB_DISABLE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARMB_ENABLE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_CALIBRATION_OUTPUT_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_CALIBRATION_OUTPUT_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_RESET_HANDLE_STATE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_SHIFT_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_DISABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_ENABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT_SOURCE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT_SOURCE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTID3_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTID3_DISABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTID3_ENABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTID3_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WRITEPROTECTION_DISABLE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_WRITEPROTECTION_ENABLE : stm32h7xx_hal_rtc.h
  • __HAL_SAI_CLEAR_FLAG : stm32h7xx_hal_sai.h
  • __HAL_SAI_DISABLE : stm32h7xx_hal_sai.h
  • __HAL_SAI_DISABLE_IT : stm32h7xx_hal_sai.h
  • __HAL_SAI_ENABLE : stm32h7xx_hal_sai.h
  • __HAL_SAI_ENABLE_IT : stm32h7xx_hal_sai.h
  • __HAL_SAI_GET_FLAG : stm32h7xx_hal_sai.h
  • __HAL_SAI_GET_IT_SOURCE : stm32h7xx_hal_sai.h
  • __HAL_SAI_RESET_HANDLE_STATE : stm32h7xx_hal_sai.h
  • __HAL_SD_CLEAR_FLAG : stm32h7xx_hal_sd.h
  • __HAL_SD_CLEAR_IT : stm32h7xx_hal_sd.h
  • __HAL_SD_DISABLE_IT : stm32h7xx_hal_sd.h
  • __HAL_SD_ENABLE_IT : stm32h7xx_hal_sd.h
  • __HAL_SD_GET_FLAG : stm32h7xx_hal_sd.h
  • __HAL_SD_GET_IT : stm32h7xx_hal_sd.h
  • __HAL_SDRAM_RESET_HANDLE_STATE : stm32h7xx_hal_sdram.h
  • __HAL_SMARTCARD_CLEAR_FEFLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_FLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IDLEFLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IT : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_NEFLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_OREFLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_PEFLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_TXFECF : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE_IT : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE_IT : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_FLUSH_DRREGISTER : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_FLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT_SOURCE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_RESET_HANDLE_STATE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_SEND_REQ : stm32h7xx_hal_smartcard.h
  • __HAL_SMBUS_CLEAR_FLAG : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE_IT : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE_IT : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_GENERATE_NACK : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_GET_FLAG : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_GET_IT_SOURCE : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_RESET_HANDLE_STATE : stm32h7xx_hal_smbus.h
  • __HAL_SPDIFRX_CLEAR_IT : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_DISABLE_IT : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_ENABLE_IT : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_GET_FLAG : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_GET_IT_SOURCE : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_IDLE : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_RCV : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_RESET_HANDLE_STATE : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_SYNC : stm32h7xx_hal_spdifrx.h
  • __HAL_SPI_CLEAR_CRCERRFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_EOTFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_FREFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_MODFFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_OVRFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_TXTFFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_UDRFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_DISABLE : stm32h7xx_hal_spi.h
  • __HAL_SPI_DISABLE_IT : stm32h7xx_hal_spi.h
  • __HAL_SPI_ENABLE : stm32h7xx_hal_spi.h
  • __HAL_SPI_ENABLE_IT : stm32h7xx_hal_spi.h
  • __HAL_SPI_GET_FLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_GET_IT_SOURCE : stm32h7xx_hal_spi.h
  • __HAL_SPI_RESET_HANDLE_STATE : stm32h7xx_hal_spi.h
  • __HAL_SRAM_RESET_HANDLE_STATE : stm32h7xx_hal_sram.h
  • __HAL_SWPMI_CLEAR_FLAG : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_DISABLE : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_DISABLE_IT : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_ENABLE : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_ENABLE_IT : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_GET_FLAG : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_GET_IT : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_GET_IT_SOURCE : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_RESET_HANDLE_STATE : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_TRANSCEIVER_DISABLE : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_TRANSCEIVER_ENABLE : stm32h7xx_hal_swpmi.h
  • __HAL_TIM_CLEAR_FLAG : stm32h7xx_hal_tim.h
  • __HAL_TIM_CLEAR_IT : stm32h7xx_hal_tim.h
  • __HAL_TIM_DISABLE : stm32h7xx_hal_tim.h
  • __HAL_TIM_DISABLE_DMA : stm32h7xx_hal_tim.h
  • __HAL_TIM_DISABLE_IT : stm32h7xx_hal_tim.h
  • __HAL_TIM_ENABLE : stm32h7xx_hal_tim.h
  • __HAL_TIM_ENABLE_DMA : stm32h7xx_hal_tim.h
  • __HAL_TIM_ENABLE_IT : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_AUTORELOAD : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_CLOCKDIVISION : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_COMPARE : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_COUNTER : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_FLAG : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_ICPRESCALER : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_IT_SOURCE : stm32h7xx_hal_tim.h
  • __HAL_TIM_IS_TIM_COUNTING_DOWN : stm32h7xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE : stm32h7xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY : stm32h7xx_hal_tim.h
  • __HAL_TIM_MOE_ENABLE : stm32h7xx_hal_tim.h
  • __HAL_TIM_RESET_HANDLE_STATE : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_AUTORELOAD : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_CAPTUREPOLARITY : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_CLOCKDIVISION : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_COMPARE : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_COUNTER : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_ICPRESCALER : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_PRESCALER : stm32h7xx_hal_tim.h
  • __HAL_TIM_URS_DISABLE : stm32h7xx_hal_tim.h
  • __HAL_TIM_URS_ENABLE : stm32h7xx_hal_tim.h
  • __HAL_UART_CLEAR_FEFLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_FLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_IDLEFLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_IT : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_NEFLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_OREFLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_PEFLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_TXFECF : stm32h7xx_hal_uart.h
  • __HAL_UART_DISABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_DISABLE_IT : stm32h7xx_hal_uart.h
  • __HAL_UART_ENABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_ENABLE_IT : stm32h7xx_hal_uart.h
  • __HAL_UART_FLUSH_DRREGISTER : stm32h7xx_hal_uart.h
  • __HAL_UART_GET_FLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_GET_IT : stm32h7xx_hal_uart.h
  • __HAL_UART_GET_IT_SOURCE : stm32h7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_DISABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_ENABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_DISABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_ENABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_RESET_HANDLE_STATE : stm32h7xx_hal_uart.h
  • __HAL_UART_SEND_REQ : stm32h7xx_hal_uart.h
  • __HAL_USART_CLEAR_FEFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_FLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_IDLEFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_IT : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_NEFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_OREFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_PEFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_TXFECF : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_UDRFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_DISABLE : stm32h7xx_hal_usart.h
  • __HAL_USART_DISABLE_IT : stm32h7xx_hal_usart.h
  • __HAL_USART_ENABLE : stm32h7xx_hal_usart.h
  • __HAL_USART_ENABLE_IT : stm32h7xx_hal_usart.h
  • __HAL_USART_GET_FLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_GET_IT : stm32h7xx_hal_usart.h
  • __HAL_USART_GET_IT_SOURCE : stm32h7xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_usart.h
  • __HAL_USART_RESET_HANDLE_STATE : stm32h7xx_hal_usart.h
  • __HAL_USART_SEND_REQ : stm32h7xx_hal_usart.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG : stm32h7xx_hal_pcd.h
  • __HAL_WWDG_CLEAR_FLAG : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_CLEAR_IT : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE_IT : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_GET_FLAG : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT_SOURCE : stm32h7xx_hal_wwdg.h
  • __MCO1_CLK_ENABLE : stm32h7xx_hal_rcc.c
  • __MCO2_CLK_ENABLE : stm32h7xx_hal_rcc.c
  • __STM32H7xx_HAL_VERSION : stm32h7xx_hal.c
  • __STM32H7xx_HAL_VERSION_MAIN : stm32h7xx_hal.c
  • __STM32H7xx_HAL_VERSION_RC : stm32h7xx_hal.c
  • __STM32H7xx_HAL_VERSION_SUB1 : stm32h7xx_hal.c
  • __STM32H7xx_HAL_VERSION_SUB2 : stm32h7xx_hal.c
  • __STM3H7xx_HAL_USART_H : stm32h7xx_hal_usart.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- a -

  • a_dfsdm1ChannelHandle : stm32h7xx_hal_dfsdm.c
  • ADC12_COMMON_REGISTER : stm32h7xx_hal_adc_ex.h
  • ADC12_NONMULTIMODE_OR_MULTIMODEMASTER : stm32h7xx_hal_adc_ex.h
  • ADC3_COMMON_REGISTER : stm32h7xx_hal_adc_ex.h
  • ADC3_NONMULTIMODE_OR_MULTIMODEMASTER : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_1 : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_2 : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_3 : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_ALL_INJEC : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_ALL_REG : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_ALL_REGINJEC : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_NONE : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_SINGLE_INJEC : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_SINGLE_REG : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_SINGLE_REGINJEC : stm32h7xx_hal_adc_ex.h
  • ADC_ANY_OTHER_ENABLED : stm32h7xx_hal_adc_ex.h
  • ADC_AWD1_EVENT : stm32h7xx_hal_adc_ex.h
  • ADC_AWD1THRESHOLD_SHIFT_RESOLUTION : stm32h7xx_hal_adc_ex.h
  • ADC_AWD23THRESHOLD_SHIFT_RESOLUTION : stm32h7xx_hal_adc_ex.h
  • ADC_AWD2_EVENT : stm32h7xx_hal_adc_ex.h
  • ADC_AWD3_EVENT : stm32h7xx_hal_adc_ex.h
  • ADC_AWD_EVENT : stm32h7xx_hal_adc_ex.h
  • ADC_CALFACT_DIFF_GET : stm32h7xx_hal_adc_ex.h
  • ADC_CALFACT_DIFF_SET : stm32h7xx_hal_adc_ex.h
  • ADC_CALIB_OFFSET : stm32h7xx_hal_adc_ex.h
  • ADC_CALIB_OFFSET_LINEARITY : stm32h7xx_hal_adc_ex.h
  • ADC_CALIBRATION_TIMEOUT : stm32h7xx_hal_adc_ex.c
  • ADC_CCR_MULTI_DMACONTREQ : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR2_FIELDS : stm32h7xx_hal_adc.c
  • ADC_CFGR2_INJ_FIELDS : stm32h7xx_hal_adc_ex.c
  • ADC_CFGR_AUTOWAIT : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_CONTINUOUS : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_DISCONTINUOUS_NUM : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_DMACONTREQ : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_FIELDS_1 : stm32h7xx_hal_adc.c
  • ADC_CFGR_FIELDS_2 : stm32h7xx_hal_adc.c
  • ADC_CFGR_INJECT_CONTEXT_QUEUE : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_INJECT_DISCCONTINUOUS : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_REG_DISCONTINUOUS : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_SET_AWD1CH : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_SET_AWD23CR : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_WD_FIELDS : stm32h7xx_hal_adc.c
  • ADC_CHANNEL_0 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_1 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_10 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_11 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_12 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_13 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_14 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_15 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_16 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_17 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_18 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_19 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_2 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_3 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_4 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_5 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_6 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_7 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_8 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_9 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_DAC1CH1_ADC2 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_DAC1CH2_ADC2 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_TEMPSENSOR : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_VBAT_DIV4 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_VREFINT : stm32h7xx_hal_adc.h
  • ADC_CLEAR_ERRORCODE : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV1 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV10 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV12 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV128 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV16 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV2 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV256 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV32 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV4 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV6 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV64 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV8 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV1 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV2 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV4 : stm32h7xx_hal_adc.h
  • ADC_CLOCKPRESCALER_PCLK_DIV1 : stm32h7xx_hal_adc.h
  • ADC_CLOCKPRESCALER_PCLK_DIV2 : stm32h7xx_hal_adc.h
  • ADC_CLOCKPRESCALER_PCLK_DIV4 : stm32h7xx_hal_adc.h
  • ADC_CONVERSION_TIME_MAX_CPU_CYCLES : stm32h7xx_hal_adc.c
  • ADC_CONVERSIONDATA_DFSDM : stm32h7xx_hal_adc.h
  • ADC_CONVERSIONDATA_DMA_CIRCULAR : stm32h7xx_hal_adc.h
  • ADC_CONVERSIONDATA_DMA_ONESHOT : stm32h7xx_hal_adc.h
  • ADC_CONVERSIONDATA_DR : stm32h7xx_hal_adc.h
  • ADC_ConversionStop() : stm32h7xx_hal_adc.c
  • ADC_DIFFERENTIAL_ENDED : stm32h7xx_hal_adc_ex.h
  • ADC_DIFSEL_CHANNEL : stm32h7xx_hal_adc_ex.h
  • ADC_Disable() : stm32h7xx_hal_adc.c
  • ADC_DISABLE : stm32h7xx_hal_adc_ex.h
  • ADC_DISABLE_TIMEOUT : stm32h7xx_hal_adc.c
  • ADC_DISABLING_CONDITIONS : stm32h7xx_hal_adc_ex.h
  • ADC_DMAConvCplt() : stm32h7xx_hal_adc.c
  • ADC_DMAError() : stm32h7xx_hal_adc.c
  • ADC_DMAHalfConvCplt() : stm32h7xx_hal_adc.c
  • ADC_DUALMODE_ALTERTRIG : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_INJECSIMULT : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_INTERL : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGINTERL_INJECSIMULT : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_ALTERTRIG : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_INJECSIMULT : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODEDATAFORMAT_32_10_BITS : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODEDATAFORMAT_8_BITS : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODEDATAFORMAT_DISABLED : stm32h7xx_hal_adc_ex.h
  • ADC_Enable() : stm32h7xx_hal_adc.c
  • ADC_ENABLE : stm32h7xx_hal_adc_ex.h
  • ADC_ENABLE_TIMEOUT : stm32h7xx_hal_adc.c
  • ADC_ENABLING_CONDITIONS : stm32h7xx_hal_adc_ex.h
  • ADC_EOC_SEQ_CONV : stm32h7xx_hal_adc.h
  • ADC_EOC_SINGLE_CONV : stm32h7xx_hal_adc.h
  • ADC_EOSMP_EVENT : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIG_EXT_IT11 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_HR1_ADCTRG1 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_HR1_ADCTRG3 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_LPTIM1_OUT : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_LPTIM2_OUT : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_LPTIM3_OUT : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T15_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC1 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC2 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC3 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO2 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_CC2 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T3_CC4 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T3_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T4_CC4 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T4_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T6_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T8_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T8_TRGO2 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_FALLING : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_NONE : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISING : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIGINJEC_EXT_IT15 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_LPTIM1_OUT : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_LPTIM2_OUT : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_LPTIM3_OUT : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T15_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_CC4 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_TRGO2 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_CC1 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC1 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC3 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC4 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T4_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T6_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_CC4 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_TRGO2 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_NONE : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISING : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_ALL : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_AWD : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_AWD1 : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_AWD2 : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_AWD3 : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_EOC : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_EOS : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_EOSMP : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_JEOC : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_JEOS : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_JQOVF : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_OVR : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_POSTCONV_ALL : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_RDY : stm32h7xx_hal_adc_ex.h
  • ADC_GET_RESOLUTION : stm32h7xx_hal_adc.h
  • ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE : stm32h7xx_hal_adc_ex.h
  • ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_GROUP : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_1 : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_2 : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_3 : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_4 : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_SOFTWARE_START : stm32h7xx_hal_adc_ex.h
  • ADC_INSTANCE_IS_ENABLED : stm32h7xx_hal_adc_ex.h
  • ADC_IS_CONVERSION_ONGOING_INJECTED : stm32h7xx_hal_adc_ex.h
  • ADC_IS_CONVERSION_ONGOING_REGULAR : stm32h7xx_hal_adc.h
  • ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED : stm32h7xx_hal_adc_ex.h
  • ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE : stm32h7xx_hal_adc_ex.h
  • ADC_IS_ENABLE : stm32h7xx_hal_adc.h
  • ADC_IS_INDEPENDENT : stm32h7xx_hal_adc_ex.h
  • ADC_IS_SOFTWARE_START_INJECTED : stm32h7xx_hal_adc_ex.h
  • ADC_IS_SOFTWARE_START_REGULAR : stm32h7xx_hal_adc.h
  • ADC_IT_AWD : stm32h7xx_hal_adc_ex.h
  • ADC_IT_AWD1 : stm32h7xx_hal_adc_ex.h
  • ADC_IT_AWD2 : stm32h7xx_hal_adc_ex.h
  • ADC_IT_AWD3 : stm32h7xx_hal_adc_ex.h
  • ADC_IT_EOC : stm32h7xx_hal_adc_ex.h
  • ADC_IT_EOS : stm32h7xx_hal_adc_ex.h
  • ADC_IT_EOSMP : stm32h7xx_hal_adc_ex.h
  • ADC_IT_JEOC : stm32h7xx_hal_adc_ex.h
  • ADC_IT_JEOS : stm32h7xx_hal_adc_ex.h
  • ADC_IT_JQOVF : stm32h7xx_hal_adc_ex.h
  • ADC_IT_OVR : stm32h7xx_hal_adc_ex.h
  • ADC_IT_RDY : stm32h7xx_hal_adc_ex.h
  • ADC_JQOVF_EVENT : stm32h7xx_hal_adc_ex.h
  • ADC_JSQR_FIELDS : stm32h7xx_hal_adc_ex.c
  • ADC_JSQR_RK : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_1 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_10 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_11 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_12 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_13 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_14 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_15 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_2 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_3 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_4 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_5 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_6 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_7 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_8 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_9 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_NONE : stm32h7xx_hal_adc_ex.h
  • ADC_MASTER_REGISTER : stm32h7xx_hal_adc_ex.h
  • ADC_MODE_INDEPENDENT : stm32h7xx_hal_adc_ex.h
  • ADC_MULTI_SLAVE : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_1 : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_2 : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_3 : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_4 : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_NONE : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_SHIFT_RESOLUTION : stm32h7xx_hal_adc_ex.h
  • ADC_OFR_CHANNEL : stm32h7xx_hal_adc_ex.h
  • ADC_OFR_FIELDS : stm32h7xx_hal_adc.c
  • ADC_OVR_DATA_OVERWRITTEN : stm32h7xx_hal_adc.h
  • ADC_OVR_DATA_PRESERVED : stm32h7xx_hal_adc.h
  • ADC_OVR_EVENT : stm32h7xx_hal_adc_ex.h
  • ADC_REGOVERSAMPLING_CONTINUED_MODE : stm32h7xx_hal_adc_ex.h
  • ADC_REGOVERSAMPLING_RESUMED_MODE : stm32h7xx_hal_adc_ex.h
  • ADC_REGULAR_GROUP : stm32h7xx_hal_adc_ex.h
  • ADC_REGULAR_INJECTED_GROUP : stm32h7xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_1 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_10 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_11 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_12 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_13 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_14 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_15 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_16 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_2 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_3 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_4 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_5 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_6 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_7 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_8 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_9 : stm32h7xx_hal_adc.h
  • ADC_RESOLUTION_10B : stm32h7xx_hal_adc.h
  • ADC_RESOLUTION_12B : stm32h7xx_hal_adc.h
  • ADC_RESOLUTION_14B : stm32h7xx_hal_adc.h
  • ADC_RESOLUTION_16B : stm32h7xx_hal_adc.h
  • ADC_RESOLUTION_8B : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_1 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_10 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_11 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_2 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_3 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_4 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_5 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_6 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_7 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_8 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_9 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_NONE : stm32h7xx_hal_adc_ex.h
  • ADC_SAMPLETIME_16CYCLES_5 : stm32h7xx_hal_adc_ex.h
  • ADC_SAMPLETIME_1CYCLE_5 : stm32h7xx_hal_adc_ex.h
  • ADC_SAMPLETIME_2CYCLES_5 : stm32h7xx_hal_adc_ex.h
  • ADC_SAMPLETIME_32CYCLES_5 : stm32h7xx_hal_adc_ex.h
  • ADC_SAMPLETIME_387CYCLES_5 : stm32h7xx_hal_adc_ex.h
  • ADC_SAMPLETIME_64CYCLES_5 : stm32h7xx_hal_adc_ex.h
  • ADC_SAMPLETIME_810CYCLES_5 : stm32h7xx_hal_adc_ex.h
  • ADC_SAMPLETIME_8CYCLES_5 : stm32h7xx_hal_adc_ex.h
  • ADC_SCAN_DISABLE : stm32h7xx_hal_adc.h
  • ADC_SCAN_ENABLE : stm32h7xx_hal_adc.h
  • ADC_SINGLE_ENDED : stm32h7xx_hal_adc_ex.h
  • ADC_SMPR1 : stm32h7xx_hal_adc_ex.h
  • ADC_SMPR2 : stm32h7xx_hal_adc_ex.h
  • ADC_SOFTWARE_START : stm32h7xx_hal_adc.h
  • ADC_SQR1_RK : stm32h7xx_hal_adc_ex.h
  • ADC_SQR2_RK : stm32h7xx_hal_adc_ex.h
  • ADC_SQR3_RK : stm32h7xx_hal_adc_ex.h
  • ADC_SQR4_RK : stm32h7xx_hal_adc_ex.h
  • ADC_STAB_DELAY_US : stm32h7xx_hal_adc.h
  • ADC_STATE_CLR_SET : stm32h7xx_hal_adc.h
  • ADC_STOP_CONVERSION_TIMEOUT : stm32h7xx_hal_adc.h
  • ADC_TEMPSENSOR_DELAY_US : stm32h7xx_hal_adc.h
  • ADC_TRIGGEREDMODE_MULTI_TRIGGER : stm32h7xx_hal_adc_ex.h
  • ADC_TRIGGEREDMODE_SINGLE_TRIGGER : stm32h7xx_hal_adc_ex.h
  • ADC_TRX_HIGHTHRESHOLD : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_1CYCLE : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_2CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_3CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_4CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_5CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_6CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_7CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_8CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_9CYCLES : stm32h7xx_hal_adc_ex.h
  • ADDR_1ST_CYCLE : stm32h7xx_hal_nand.h
  • ADDR_2ND_CYCLE : stm32h7xx_hal_nand.h
  • ADDR_3RD_CYCLE : stm32h7xx_hal_nand.h
  • ADDR_4TH_CYCLE : stm32h7xx_hal_nand.h
  • ADDR_AREA : stm32h7xx_hal_nand.h
  • ANALOG_MODE : stm32h7xx_hal_gpio.c
  • ARRAY_ADDRESS : stm32h7xx_hal_nand.h
  • assert_param : stm32h7xx_hal_conf.h
  • AVD_FALLING_EDGE : stm32h7xx_hal_pwr_ex.c
  • AVD_MODE_EVT : stm32h7xx_hal_pwr_ex.c
  • AVD_MODE_IT : stm32h7xx_hal_pwr_ex.c
  • AVD_RISING_EDGE : stm32h7xx_hal_pwr_ex.c
  • AVD_RISING_FALLING_EDGE : stm32h7xx_hal_pwr_ex.c
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- b -

  • BackupAddr0 : stm32h7xx_hal_eth.h
  • BackupAddr1 : stm32h7xx_hal_eth.h
  • BDMA_CH6_CLEAR : stm32h7xx_hal.h
  • BDMA_CH7_CLEAR : stm32h7xx_hal.h
  • BDMA_FLAG_GL0 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL1 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL2 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL3 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL4 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL5 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL6 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL7 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT0 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT1 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT2 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT3 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT4 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT5 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT6 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT7 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC0 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC1 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC2 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC3 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC4 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC5 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC6 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC7 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE0 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE1 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE2 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE3 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE4 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE5 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE6 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE7 : stm32h7xx_hal_dma.h
  • BDMA_MEMORY_TO_MEMORY : stm32h7xx_hal_dma.c
  • BDMA_MEMORY_TO_PERIPH : stm32h7xx_hal_dma.c
  • BDMA_PERIPH_TO_MEMORY : stm32h7xx_hal_dma.c
  • BDMA_REQUEST_ADC3 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR0 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR1 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR2 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR3 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR4 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR5 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR6 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR7 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_I2C4_RX : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_I2C4_TX : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_LP_UART1_RX : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_LP_UART1_TX : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_MEM2MEM : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_SAI4_A : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_SAI4_B : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_SPI6_RX : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_SPI6_TX : stm32h7xx_hal_dma.h
  • BDTR_BK2F_SHIFT : stm32h7xx_hal_tim_ex.c
  • BDTR_BKF_SHIFT : stm32h7xx_hal_tim_ex.c
  • BLOCKSIZE : stm32h7xx_hal_mmc.h , stm32h7xx_hal_sd.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- c -

  • CARD_HIGH_SPEED : stm32h7xx_hal_sd.h
  • CARD_NORMAL_SPEED : stm32h7xx_hal_sd.h
  • CARD_SDHC_SDXC : stm32h7xx_hal_sd.h
  • CARD_SDSC : stm32h7xx_hal_sd.h
  • CARD_SECURED : stm32h7xx_hal_sd.h
  • CARD_ULTRA_HIGH_SPEED : stm32h7xx_hal_sd.h
  • CARD_V1_X : stm32h7xx_hal_sd.h
  • CARD_V2_X : stm32h7xx_hal_sd.h
  • CCU_IR_MASK : stm32h7xx_hal_fdcan.h
  • CEC_0_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_1_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_2_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_3_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_4_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_5_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_6_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_BRE_ERRORBIT_GENERATION : stm32h7xx_hal_cec.h
  • CEC_BRE_ERRORBIT_NO_GENERATION : stm32h7xx_hal_cec.h
  • CEC_BROADCASTERROR_ERRORBIT_GENERATION : stm32h7xx_hal_cec.h
  • CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION : stm32h7xx_hal_cec.h
  • CEC_CFGR_OAR_LSB_POS : stm32h7xx_hal_cec.h
  • CEC_DEFAULT_SFT : stm32h7xx_hal_cec.h
  • CEC_EXTENDED_TOLERANCE : stm32h7xx_hal_cec.h
  • CEC_FLAG_ARBLST : stm32h7xx_hal_cec.h
  • CEC_FLAG_BRE : stm32h7xx_hal_cec.h
  • CEC_FLAG_LBPE : stm32h7xx_hal_cec.h
  • CEC_FLAG_RXACKE : stm32h7xx_hal_cec.h
  • CEC_FLAG_RXBR : stm32h7xx_hal_cec.h
  • CEC_FLAG_RXEND : stm32h7xx_hal_cec.h
  • CEC_FLAG_RXOVR : stm32h7xx_hal_cec.h
  • CEC_FLAG_SBPE : stm32h7xx_hal_cec.h
  • CEC_FLAG_TXACKE : stm32h7xx_hal_cec.h
  • CEC_FLAG_TXBR : stm32h7xx_hal_cec.h
  • CEC_FLAG_TXEND : stm32h7xx_hal_cec.h
  • CEC_FLAG_TXERR : stm32h7xx_hal_cec.h
  • CEC_FLAG_TXUDR : stm32h7xx_hal_cec.h
  • CEC_FULL_LISTENING_MODE : stm32h7xx_hal_cec.h
  • CEC_IER_RX_ALL_ERR : stm32h7xx_hal_cec.h
  • CEC_IER_TX_ALL_ERR : stm32h7xx_hal_cec.h
  • CEC_INITIATOR_LSB_POS : stm32h7xx_hal_cec.h
  • CEC_ISR_ALL_ERROR : stm32h7xx_hal_cec.h
  • CEC_IT_ARBLST : stm32h7xx_hal_cec.h
  • CEC_IT_BRE : stm32h7xx_hal_cec.h
  • CEC_IT_LBPE : stm32h7xx_hal_cec.h
  • CEC_IT_RXACKE : stm32h7xx_hal_cec.h
  • CEC_IT_RXBR : stm32h7xx_hal_cec.h
  • CEC_IT_RXEND : stm32h7xx_hal_cec.h
  • CEC_IT_RXOVR : stm32h7xx_hal_cec.h
  • CEC_IT_SBPE : stm32h7xx_hal_cec.h
  • CEC_IT_TXACKE : stm32h7xx_hal_cec.h
  • CEC_IT_TXBR : stm32h7xx_hal_cec.h
  • CEC_IT_TXEND : stm32h7xx_hal_cec.h
  • CEC_IT_TXERR : stm32h7xx_hal_cec.h
  • CEC_IT_TXUDR : stm32h7xx_hal_cec.h
  • CEC_LBPE_ERRORBIT_GENERATION : stm32h7xx_hal_cec.h
  • CEC_LBPE_ERRORBIT_NO_GENERATION : stm32h7xx_hal_cec.h
  • CEC_NO_RX_STOP_ON_BRE : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_0 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_1 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_10 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_11 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_12 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_13 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_14 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_2 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_3 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_4 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_5 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_6 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_7 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_8 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_9 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_NONE : stm32h7xx_hal_cec.h
  • CEC_REDUCED_LISTENING_MODE : stm32h7xx_hal_cec.h
  • CEC_RX_STOP_ON_BRE : stm32h7xx_hal_cec.h
  • CEC_SFT_START_ON_TX_RX_END : stm32h7xx_hal_cec.h
  • CEC_SFT_START_ON_TXSOM : stm32h7xx_hal_cec.h
  • CEC_STANDARD_TOLERANCE : stm32h7xx_hal_cec.h
  • CFI1_ADDRESS : stm32h7xx_hal_nor.h
  • CFI2_ADDRESS : stm32h7xx_hal_nor.h
  • CFI3_ADDRESS : stm32h7xx_hal_nor.h
  • CFI4_ADDRESS : stm32h7xx_hal_nor.h
  • CLOCKSWITCH_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • CM7_CPUID : stm32h7xx_hal_cortex.h
  • CMD_AREA : stm32h7xx_hal_nand.h
  • COLUMN_1ST_CYCLE : stm32h7xx_hal_nand.h
  • COLUMN_2ND_CYCLE : stm32h7xx_hal_nand.h
  • COLUMN_ADDRESS : stm32h7xx_hal_nand.h
  • COMP_BLANKINGSRC_NONE : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM15_OC1 : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5 : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM2_OC3 : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC3 : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC4 : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM8_OC5 : stm32h7xx_hal_comp.h
  • COMP_CLEAR_C1IF : stm32h7xx_hal_comp.h
  • COMP_CLEAR_C2IF : stm32h7xx_hal_comp.h
  • COMP_DELAY_STARTUP_US : stm32h7xx_hal_comp.c
  • COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32h7xx_hal_comp.c
  • COMP_EXTI_EVENT : stm32h7xx_hal_comp.h
  • COMP_EXTI_FALLING : stm32h7xx_hal_comp.h
  • COMP_EXTI_IT : stm32h7xx_hal_comp.h
  • COMP_EXTI_LINE_COMP1 : stm32h7xx_hal_comp.h
  • COMP_EXTI_LINE_COMP2 : stm32h7xx_hal_comp.h
  • COMP_EXTI_RISING : stm32h7xx_hal_comp.h
  • COMP_FLAG_C1I : stm32h7xx_hal_comp.h
  • COMP_FLAG_C2I : stm32h7xx_hal_comp.h
  • COMP_FLAG_LOCK : stm32h7xx_hal_comp.h
  • COMP_GET_EXTI_LINE : stm32h7xx_hal_comp.h
  • COMP_HYSTERESIS_HIGH : stm32h7xx_hal_comp.h
  • COMP_HYSTERESIS_LOW : stm32h7xx_hal_comp.h
  • COMP_HYSTERESIS_MEDIUM : stm32h7xx_hal_comp.h
  • COMP_HYSTERESIS_NONE : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_1_2VREFINT : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_1_4VREFINT : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_3_4VREFINT : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC1_CH1 : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC1_CH2 : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_IO1 : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_IO2 : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_VREFINT : stm32h7xx_hal_comp.h
  • COMP_INPUT_PLUS_IO1 : stm32h7xx_hal_comp.h
  • COMP_INPUT_PLUS_IO2 : stm32h7xx_hal_comp.h
  • COMP_IT_EN : stm32h7xx_hal_comp.h
  • COMP_OUTPUT_LEVEL_HIGH : stm32h7xx_hal_comp.h
  • COMP_OUTPUT_LEVEL_LOW : stm32h7xx_hal_comp.h
  • COMP_OUTPUTPOL_INVERTED : stm32h7xx_hal_comp.h
  • COMP_OUTPUTPOL_NONINVERTED : stm32h7xx_hal_comp.h
  • COMP_POWERMODE_HIGHSPEED : stm32h7xx_hal_comp.h
  • COMP_POWERMODE_MEDIUMSPEED : stm32h7xx_hal_comp.h
  • COMP_POWERMODE_ULTRALOWPOWER : stm32h7xx_hal_comp.h
  • COMP_STATE_BITFIELD_LOCK : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_FALLING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING_FALLING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_FALLING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING_FALLING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_NONE : stm32h7xx_hal_comp.h
  • COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON : stm32h7xx_hal_comp.h
  • COMP_WINDOWMODE_DISABLE : stm32h7xx_hal_comp.h
  • CR_PSIZE_MASK : stm32h7xx_hal_flash.h
  • CRC_Handle_16() : stm32h7xx_hal_crc.c
  • CRC_Handle_8() : stm32h7xx_hal_crc.c
  • CRC_INPUTDATA_FORMAT_BYTES : stm32h7xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_HALFWORDS : stm32h7xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_UNDEFINED : stm32h7xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_WORDS : stm32h7xx_hal_crc.h
  • CRC_INPUTDATA_INVERSION_BYTE : stm32h7xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_HALFWORD : stm32h7xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_NONE : stm32h7xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_WORD : stm32h7xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_DISABLE : stm32h7xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_ENABLE : stm32h7xx_hal_crc_ex.h
  • CRC_POLYLENGTH_16B : stm32h7xx_hal_crc.h
  • CRC_POLYLENGTH_32B : stm32h7xx_hal_crc.h
  • CRC_POLYLENGTH_7B : stm32h7xx_hal_crc.h
  • CRC_POLYLENGTH_8B : stm32h7xx_hal_crc.h
  • CRYP_AES_CBC : stm32h7xx_hal_cryp.h
  • CRYP_AES_CCM : stm32h7xx_hal_cryp.h
  • CRYP_AES_CTR : stm32h7xx_hal_cryp.h
  • CRYP_AES_Decrypt() : stm32h7xx_hal_cryp.c
  • CRYP_AES_Decrypt_DMA() : stm32h7xx_hal_cryp.c
  • CRYP_AES_Decrypt_IT() : stm32h7xx_hal_cryp.c
  • CRYP_AES_ECB : stm32h7xx_hal_cryp.h
  • CRYP_AES_Encrypt() : stm32h7xx_hal_cryp.c
  • CRYP_AES_Encrypt_IT() : stm32h7xx_hal_cryp.c
  • CRYP_AES_GCM : stm32h7xx_hal_cryp.h
  • CRYP_AES_IT() : stm32h7xx_hal_cryp.c
  • CRYP_AES_ProcessData() : stm32h7xx_hal_cryp.c
  • CRYP_AESCCM_Process() : stm32h7xx_hal_cryp.c
  • CRYP_AESCCM_Process_DMA() : stm32h7xx_hal_cryp.c
  • CRYP_AESCCM_Process_IT() : stm32h7xx_hal_cryp.c
  • CRYP_AESGCM_Process() : stm32h7xx_hal_cryp.c
  • CRYP_AESGCM_Process_DMA() : stm32h7xx_hal_cryp.c
  • CRYP_AESGCM_Process_IT() : stm32h7xx_hal_cryp.c
  • CRYP_CCM_CTR0_0 : stm32h7xx_hal_cryp_ex.c
  • CRYP_CCM_CTR0_3 : stm32h7xx_hal_cryp_ex.c
  • CRYP_CCM_CTR1_0 : stm32h7xx_hal_cryp.c
  • CRYP_CCM_CTR1_1 : stm32h7xx_hal_cryp.c
  • CRYP_CCM_CTR1_2 : stm32h7xx_hal_cryp.c
  • CRYP_DATATYPE_16B : stm32h7xx_hal_cryp.h
  • CRYP_DATATYPE_1B : stm32h7xx_hal_cryp.h
  • CRYP_DATATYPE_32B : stm32h7xx_hal_cryp.h
  • CRYP_DATATYPE_8B : stm32h7xx_hal_cryp.h
  • CRYP_DES_CBC : stm32h7xx_hal_cryp.h
  • CRYP_DES_ECB : stm32h7xx_hal_cryp.h
  • CRYP_DMAError() : stm32h7xx_hal_cryp.c
  • CRYP_DMAInCplt() : stm32h7xx_hal_cryp.c
  • CRYP_DMAOutCplt() : stm32h7xx_hal_cryp.c
  • CRYP_FLAG_BUSY : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_IFEM : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_IFNF : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_INRIS : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_MASK : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_OFFU : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_OFNE : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_OUTRIS : stm32h7xx_hal_cryp.h
  • CRYP_GCMCCM_SetHeaderPhase() : stm32h7xx_hal_cryp.c
  • CRYP_GCMCCM_SetHeaderPhase_DMA() : stm32h7xx_hal_cryp.c
  • CRYP_GCMCCM_SetHeaderPhase_IT() : stm32h7xx_hal_cryp.c
  • CRYP_GCMCCM_SetPayloadPhase_IT() : stm32h7xx_hal_cryp.c
  • CRYP_IT_INI : stm32h7xx_hal_cryp.h
  • CRYP_IT_OUTI : stm32h7xx_hal_cryp.h
  • CRYP_KEYSIZE_128B : stm32h7xx_hal_cryp.h
  • CRYP_KEYSIZE_192B : stm32h7xx_hal_cryp.h
  • CRYP_KEYSIZE_256B : stm32h7xx_hal_cryp.h
  • CRYP_OPERATINGMODE_DECRYPT : stm32h7xx_hal_cryp_ex.c , stm32h7xx_hal_cryp.c
  • CRYP_OPERATINGMODE_ENCRYPT : stm32h7xx_hal_cryp_ex.c , stm32h7xx_hal_cryp.c
  • CRYP_PHASE_FINAL : stm32h7xx_hal_cryp.c , stm32h7xx_hal_cryp_ex.c
  • CRYP_PHASE_HEADER : stm32h7xx_hal_cryp_ex.c , stm32h7xx_hal_cryp.c
  • CRYP_PHASE_INIT : stm32h7xx_hal_cryp.c , stm32h7xx_hal_cryp_ex.c
  • CRYP_PHASE_PAYLOAD : stm32h7xx_hal_cryp.c , stm32h7xx_hal_cryp_ex.c
  • CRYP_PHASE_PROCESS : stm32h7xx_hal_cryp.c
  • CRYP_PHASE_READY : stm32h7xx_hal_cryp.c
  • CRYP_SET_PHASE : stm32h7xx_hal_cryp.c
  • CRYP_SetDMAConfig() : stm32h7xx_hal_cryp.c
  • CRYP_SetKey() : stm32h7xx_hal_cryp.c
  • CRYP_TDES_CBC : stm32h7xx_hal_cryp.h
  • CRYP_TDES_ECB : stm32h7xx_hal_cryp.h
  • CRYP_TDES_IT() : stm32h7xx_hal_cryp.c
  • CRYP_TDES_Process() : stm32h7xx_hal_cryp.c
  • CRYP_TIMEOUT_GCMCCMHEADERPHASE : stm32h7xx_hal_cryp.c
  • CRYP_TIMEOUT_GCMCCMINITPHASE : stm32h7xx_hal_cryp.c
  • CRYP_TIMEOUT_KEYPREPARATION : stm32h7xx_hal_cryp.c
  • CRYP_WaitOnBUSYFlag() : stm32h7xx_hal_cryp.c
  • CRYP_WaitOnIFEMFlag() : stm32h7xx_hal_cryp.c
  • CRYP_WaitOnOFNEFlag() : stm32h7xx_hal_cryp.c
  • CRYP_Workaround() : stm32h7xx_hal_cryp.c
  • CRYPEx_PHASE_FINAL : stm32h7xx_hal_cryp_ex.c
  • CRYPEx_PHASE_PROCESS : stm32h7xx_hal_cryp_ex.c
  • CSI_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • CSI_VALUE : stm32h7xx_hal_conf.h
  • CvtEltSize : stm32h7xx_hal_fdcan.c
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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  • Variables
  • Typedefs
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- d -

  • D2_TO_D3_DMA_DIRECTION : stm32h7xx_hal_dma.c
  • D2_TO_D3_DMA_IT : stm32h7xx_hal_dma.h
  • D2_TO_D3_DMA_MDATA_SIZE : stm32h7xx_hal_dma.c
  • D2_TO_D3_DMA_MEMORY_INC : stm32h7xx_hal_dma.c
  • D2_TO_D3_DMA_MODE : stm32h7xx_hal_dma.c
  • D2_TO_D3_DMA_PDATA_SIZE : stm32h7xx_hal_dma.c
  • D2_TO_D3_DMA_PERIPHERAL_INC : stm32h7xx_hal_dma.c
  • D2_TO_D3_DMA_PRIORITY : stm32h7xx_hal_dma.c
  • DAC_ALIGN_12B_L : stm32h7xx_hal_dac.h
  • DAC_ALIGN_12B_R : stm32h7xx_hal_dac.h
  • DAC_ALIGN_8B_R : stm32h7xx_hal_dac.h
  • DAC_CHANNEL_1 : stm32h7xx_hal_dac.h
  • DAC_CHANNEL_2 : stm32h7xx_hal_dac.h
  • DAC_CHIPCONNECT_DISABLE : stm32h7xx_hal_dac.h
  • DAC_CHIPCONNECT_ENABLE : stm32h7xx_hal_dac.h
  • DAC_DHR12R1_ALIGNMENT : stm32h7xx_hal_dac.h
  • DAC_DHR12R2_ALIGNMENT : stm32h7xx_hal_dac.h
  • DAC_DHR12RD_ALIGNMENT : stm32h7xx_hal_dac.h
  • DAC_DMAConvCpltCh1() : stm32h7xx_hal_dac.c
  • DAC_DMAConvCpltCh2() : stm32h7xx_hal_dac_ex.c
  • DAC_DMAErrorCh1() : stm32h7xx_hal_dac.c
  • DAC_DMAErrorCh2() : stm32h7xx_hal_dac_ex.c
  • DAC_DMAHalfConvCpltCh1() : stm32h7xx_hal_dac.c
  • DAC_DMAHalfConvCpltCh2() : stm32h7xx_hal_dac_ex.c
  • DAC_FLAG_DMAUDR1 : stm32h7xx_hal_dac.h
  • DAC_FLAG_DMAUDR2 : stm32h7xx_hal_dac.h
  • DAC_IT_DMAUDR1 : stm32h7xx_hal_dac.h
  • DAC_IT_DMAUDR2 : stm32h7xx_hal_dac.h
  • DAC_LFSRUNMASK_BIT0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS10_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS11_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS1_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS2_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS3_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS4_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS5_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS6_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS7_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS8_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS9_0 : stm32h7xx_hal_dac_ex.h
  • DAC_OUTPUTBUFFER_DISABLE : stm32h7xx_hal_dac.h
  • DAC_OUTPUTBUFFER_ENABLE : stm32h7xx_hal_dac.h
  • DAC_SAMPLEANDHOLD_DISABLE : stm32h7xx_hal_dac.h
  • DAC_SAMPLEANDHOLD_ENABLE : stm32h7xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_1 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_1023 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_127 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_15 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_2047 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_255 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_3 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_31 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_4095 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_511 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_63 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_7 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIGGER_EXT_IT9 : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_HR1_TRGO1 : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_HR1_TRGO2 : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_LP1_OUT : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_LP2_OUT : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_NONE : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_SOFTWARE : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T15_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T1_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T2_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T4_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T5_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T6_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T7_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T8_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIMMING_FACTORY : stm32h7xx_hal_dac.h
  • DAC_TRIMMING_USER : stm32h7xx_hal_dac.h
  • DCMI_BSM_ALL : stm32h7xx_hal_dcmi.h
  • DCMI_BSM_ALTERNATE_2 : stm32h7xx_hal_dcmi.h
  • DCMI_BSM_ALTERNATE_4 : stm32h7xx_hal_dcmi.h
  • DCMI_BSM_OTHER : stm32h7xx_hal_dcmi.h
  • DCMI_CR_ALL_FRAME : stm32h7xx_hal_dcmi.h
  • DCMI_CR_ALTERNATE_2_FRAME : stm32h7xx_hal_dcmi.h
  • DCMI_CR_ALTERNATE_4_FRAME : stm32h7xx_hal_dcmi.h
  • DCMI_DMAError() : stm32h7xx_hal_dcmi.c
  • DCMI_DMAXferCplt() : stm32h7xx_hal_dcmi.c
  • DCMI_EXTEND_DATA_10B : stm32h7xx_hal_dcmi.h
  • DCMI_EXTEND_DATA_12B : stm32h7xx_hal_dcmi.h
  • DCMI_EXTEND_DATA_14B : stm32h7xx_hal_dcmi.h
  • DCMI_EXTEND_DATA_8B : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_ERRMI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_ERRRI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_FNE : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_FRAMEMI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_FRAMERI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_HSYNC : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_LINEMI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_LINERI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_OVRMI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_OVRRI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_VSYNC : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_VSYNCMI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_VSYNCRI : stm32h7xx_hal_dcmi.h
  • DCMI_HSPOLARITY_HIGH : stm32h7xx_hal_dcmi.h
  • DCMI_HSPOLARITY_LOW : stm32h7xx_hal_dcmi.h
  • DCMI_IT_ERR : stm32h7xx_hal_dcmi.h
  • DCMI_IT_FRAME : stm32h7xx_hal_dcmi.h
  • DCMI_IT_LINE : stm32h7xx_hal_dcmi.h
  • DCMI_IT_OVR : stm32h7xx_hal_dcmi.h
  • DCMI_IT_VSYNC : stm32h7xx_hal_dcmi.h
  • DCMI_JPEG_DISABLE : stm32h7xx_hal_dcmi.h
  • DCMI_JPEG_ENABLE : stm32h7xx_hal_dcmi.h
  • DCMI_LSM_ALL : stm32h7xx_hal_dcmi.h
  • DCMI_LSM_ALTERNATE_2 : stm32h7xx_hal_dcmi.h
  • DCMI_MIS_INDEX : stm32h7xx_hal_dcmi.h
  • DCMI_MODE_CONTINUOUS : stm32h7xx_hal_dcmi.h
  • DCMI_MODE_SNAPSHOT : stm32h7xx_hal_dcmi.h
  • DCMI_OEBS_EVEN : stm32h7xx_hal_dcmi.h
  • DCMI_OEBS_ODD : stm32h7xx_hal_dcmi.h
  • DCMI_OELS_EVEN : stm32h7xx_hal_dcmi.h
  • DCMI_OELS_ODD : stm32h7xx_hal_dcmi.h
  • DCMI_PCKPOLARITY_FALLING : stm32h7xx_hal_dcmi.h
  • DCMI_PCKPOLARITY_RISING : stm32h7xx_hal_dcmi.h
  • DCMI_POSITION_CWSIZE_VLINE : stm32h7xx_hal_dcmi.c
  • DCMI_POSITION_CWSTRT_VST : stm32h7xx_hal_dcmi.c
  • DCMI_POSITION_ESCR_FEC : stm32h7xx_hal_dcmi.c
  • DCMI_POSITION_ESCR_LEC : stm32h7xx_hal_dcmi.c
  • DCMI_POSITION_ESCR_LSC : stm32h7xx_hal_dcmi.c
  • DCMI_SR_INDEX : stm32h7xx_hal_dcmi.h
  • DCMI_SYNCHRO_EMBEDDED : stm32h7xx_hal_dcmi.h
  • DCMI_SYNCHRO_HARDWARE : stm32h7xx_hal_dcmi.h
  • DCMI_VSPOLARITY_HIGH : stm32h7xx_hal_dcmi.h
  • DCMI_VSPOLARITY_LOW : stm32h7xx_hal_dcmi.h
  • DCMI_WINDOW_COORDINATE : stm32h7xx_hal_dcmi.h
  • DCMI_WINDOW_HEIGHT : stm32h7xx_hal_dcmi.h
  • DEFAULT_CRC32_POLY : stm32h7xx_hal_crc.h
  • DEFAULT_CRC_INITVALUE : stm32h7xx_hal_crc.h
  • DEFAULT_INIT_VALUE_DISABLE : stm32h7xx_hal_crc.h
  • DEFAULT_INIT_VALUE_ENABLE : stm32h7xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_DISABLE : stm32h7xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_ENABLE : stm32h7xx_hal_crc.h
  • DESC0 : stm32h7xx_hal_eth.h
  • DESC1 : stm32h7xx_hal_eth.h
  • DESC2 : stm32h7xx_hal_eth.h
  • DESC3 : stm32h7xx_hal_eth.h
  • DEVICE_CODE1_ADDR : stm32h7xx_hal_nor.h
  • DEVICE_CODE2_ADDR : stm32h7xx_hal_nor.h
  • DEVICE_CODE3_ADDR : stm32h7xx_hal_nor.h
  • DFSDM1_CHANNEL_NUMBER : stm32h7xx_hal_dfsdm.c
  • DFSDM_AWD_HIGH_THRESHOLD : stm32h7xx_hal_dfsdm.h
  • DFSDM_AWD_LOW_THRESHOLD : stm32h7xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_0 : stm32h7xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_1 : stm32h7xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_2 : stm32h7xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_3 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_0 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_1 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_2 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_3 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_4 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_5 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_6 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_7 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_ADC_OUTPUT : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_DUAL_MODE : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_EXTERNAL_INPUTS : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_FASTSINC_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_INTERLEAVED_MODE : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_INTERNAL_REGISTER : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_MANCHESTER_FALLING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_MANCHESTER_RISING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SAME_CHANNEL_PINS : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SINC1_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SINC2_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SINC3_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_INTERNAL : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_FALLING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_RISING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_STANDARD_MODE : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHAWSCDR_BKSCD_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_CHAWSCDR_FOSR_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_CHCFGR1_CLK_DIV_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_CHCFGR2_DTRBS_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_CHCFGR2_OFFSET_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_CKAB_TIMEOUT : stm32h7xx_hal_dfsdm.c
  • DFSDM_CONTINUOUS_CONV_OFF : stm32h7xx_hal_dfsdm.h
  • DFSDM_CONTINUOUS_CONV_ON : stm32h7xx_hal_dfsdm.h
  • DFSDM_DMAError() : stm32h7xx_hal_dfsdm.c
  • DFSDM_DMAInjectedConvCplt() : stm32h7xx_hal_dfsdm.c
  • DFSDM_DMAInjectedHalfConvCplt() : stm32h7xx_hal_dfsdm.c
  • DFSDM_DMARegularConvCplt() : stm32h7xx_hal_dfsdm.c
  • DFSDM_DMARegularHalfConvCplt() : stm32h7xx_hal_dfsdm.c
  • DFSDM_FILTER_AWD_CHANNEL_DATA : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_AWD_FILTER_DATA : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_DMA : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_INJECTED_OVERRUN : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_NONE : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_REGULAR_OVERRUN : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_BOTH_EDGES : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_EXTI11 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_EXTI15 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_FALLING_EDGE : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_LPTIM1 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_LPTIM2 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_LPTIM3 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_RISING_EDGE : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM16_OC1 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM1_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM3_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM4_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM6_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM7_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM8_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIGGER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_FASTSINC_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC1_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC2_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC3_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC4_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC5_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SW_TRIGGER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SYNC_TRIGGER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FLTAWHTR_THRESHOLD_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTAWLTR_THRESHOLD_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTAWSR_HIGH_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTCNVTIMR_DATA_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTCR1_MSB_RCH_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTCR2_AWDCH_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTCR2_EXCH_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTEXMAX_DATA_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTEXMIN_DATA_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTFCR_FOSR_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTICR_CLRCKABF_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTICR_CLRSCDF_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTISR_CKABF_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTISR_SCDF_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTJDATAR_DATA_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTRDATAR_DATA_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_GetChannelFromInstance() : stm32h7xx_hal_dfsdm.c
  • DFSDM_GetInjChannelsNbr() : stm32h7xx_hal_dfsdm.c
  • DFSDM_InjConvStart() : stm32h7xx_hal_dfsdm.c
  • DFSDM_InjConvStop() : stm32h7xx_hal_dfsdm.c
  • DFSDM_LSB_MASK : stm32h7xx_hal_dfsdm.c
  • DFSDM_MSB_MASK : stm32h7xx_hal_dfsdm.c
  • DFSDM_NO_BREAK_SIGNAL : stm32h7xx_hal_dfsdm.h
  • DFSDM_RegConvStart() : stm32h7xx_hal_dfsdm.c
  • DFSDM_RegConvStop() : stm32h7xx_hal_dfsdm.c
  • DLCtoBytes : stm32h7xx_hal_fdcan.c
  • DMA2D_CCM_ARGB8888 : stm32h7xx_hal_dma2d.h
  • DMA2D_CCM_RGB888 : stm32h7xx_hal_dma2d.h
  • DMA2D_CLUT_SIZE : stm32h7xx_hal_dma2d.h
  • DMA2D_COLOR_VALUE : stm32h7xx_hal_dma2d.h
  • DMA2D_COMBINE_ALPHA : stm32h7xx_hal_dma2d.h
  • DMA2D_CSS_420 : stm32h7xx_hal_dma2d.h
  • DMA2D_CSS_422 : stm32h7xx_hal_dma2d.h
  • DMA2D_FLAG_CAE : stm32h7xx_hal_dma2d.h
  • DMA2D_FLAG_CE : stm32h7xx_hal_dma2d.h
  • DMA2D_FLAG_CTC : stm32h7xx_hal_dma2d.h
  • DMA2D_FLAG_TC : stm32h7xx_hal_dma2d.h
  • DMA2D_FLAG_TE : stm32h7xx_hal_dma2d.h
  • DMA2D_FLAG_TW : stm32h7xx_hal_dma2d.h
  • DMA2D_HandleTypeDef : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_A4 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_A8 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_AL44 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_AL88 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_ARGB1555 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_ARGB4444 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_ARGB8888 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_L4 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_L8 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_RGB565 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_RGB888 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_YCBCR : stm32h7xx_hal_dma2d.h
  • DMA2D_INVERTED_ALPHA : stm32h7xx_hal_dma2d.h
  • DMA2D_IT_CAE : stm32h7xx_hal_dma2d.h
  • DMA2D_IT_CE : stm32h7xx_hal_dma2d.h
  • DMA2D_IT_CTC : stm32h7xx_hal_dma2d.h
  • DMA2D_IT_TC : stm32h7xx_hal_dma2d.h
  • DMA2D_IT_TE : stm32h7xx_hal_dma2d.h
  • DMA2D_IT_TW : stm32h7xx_hal_dma2d.h
  • DMA2D_LINE : stm32h7xx_hal_dma2d.h
  • DMA2D_LINE_WATERMARK_MAX : stm32h7xx_hal_dma2d.h
  • DMA2D_M2M : stm32h7xx_hal_dma2d.h
  • DMA2D_M2M_BLEND : stm32h7xx_hal_dma2d.h
  • DMA2D_M2M_PFC : stm32h7xx_hal_dma2d.h
  • DMA2D_NO_CSS : stm32h7xx_hal_dma2d.h
  • DMA2D_NO_MODIF_ALPHA : stm32h7xx_hal_dma2d.h
  • DMA2D_OFFSET : stm32h7xx_hal_dma2d.h
  • DMA2D_OUTPUT_ARGB1555 : stm32h7xx_hal_dma2d.h
  • DMA2D_OUTPUT_ARGB4444 : stm32h7xx_hal_dma2d.h
  • DMA2D_OUTPUT_ARGB8888 : stm32h7xx_hal_dma2d.h
  • DMA2D_OUTPUT_RGB565 : stm32h7xx_hal_dma2d.h
  • DMA2D_OUTPUT_RGB888 : stm32h7xx_hal_dma2d.h
  • DMA2D_PIXEL : stm32h7xx_hal_dma2d.h
  • DMA2D_POSITION_AMTCR_DT : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_BGPFCCR_AI : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_BGPFCCR_ALPHA : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_BGPFCCR_AM : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_BGPFCCR_CCM : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_BGPFCCR_CS : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_BGPFCCR_RBS : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_FGPFCCR_AI : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_FGPFCCR_ALPHA : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_FGPFCCR_AM : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_FGPFCCR_CCM : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_FGPFCCR_CS : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_FGPFCCR_CSS : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_FGPFCCR_RBS : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_NLR_PL : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_OPFCCR_AI : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_OPFCCR_RBS : stm32h7xx_hal_dma2d.c
  • DMA2D_R2M : stm32h7xx_hal_dma2d.h
  • DMA2D_RB_REGULAR : stm32h7xx_hal_dma2d.h
  • DMA2D_RB_SWAP : stm32h7xx_hal_dma2d.h
  • DMA2D_REGULAR_ALPHA : stm32h7xx_hal_dma2d.h
  • DMA2D_REPLACE_ALPHA : stm32h7xx_hal_dma2d.h
  • DMA2D_SetConfig() : stm32h7xx_hal_dma2d.c
  • DMA2D_TIMEOUT_ABORT : stm32h7xx_hal_dma2d.c
  • DMA2D_TIMEOUT_SUSPEND : stm32h7xx_hal_dma2d.c
  • DMA_CalcBaseAndBitshift() : stm32h7xx_hal_dma.c
  • DMA_CalcDMAMUXChannelBaseAndMask() : stm32h7xx_hal_dma.c
  • DMA_CalcDMAMUXRequestGenBaseAndMask() : stm32h7xx_hal_dma.c
  • DMA_CheckFifoParam() : stm32h7xx_hal_dma.c
  • DMA_CIRCULAR : stm32h7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_1QUARTERFULL : stm32h7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_3QUARTERSFULL : stm32h7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_FULL : stm32h7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_HALFFULL : stm32h7xx_hal_dma.h
  • DMA_FIFOMODE_DISABLE : stm32h7xx_hal_dma.h
  • DMA_FIFOMODE_ENABLE : stm32h7xx_hal_dma.h
  • DMA_FLAG_DMEIF0_4 : stm32h7xx_hal_dma.h
  • DMA_FLAG_DMEIF1_5 : stm32h7xx_hal_dma.h
  • DMA_FLAG_DMEIF2_6 : stm32h7xx_hal_dma.h
  • DMA_FLAG_DMEIF3_7 : stm32h7xx_hal_dma.h
  • DMA_FLAG_FEIF0_4 : stm32h7xx_hal_dma.h
  • DMA_FLAG_FEIF1_5 : stm32h7xx_hal_dma.h
  • DMA_FLAG_FEIF2_6 : stm32h7xx_hal_dma.h
  • DMA_FLAG_FEIF3_7 : stm32h7xx_hal_dma.h
  • DMA_FLAG_HTIF0_4 : stm32h7xx_hal_dma.h
  • DMA_FLAG_HTIF1_5 : stm32h7xx_hal_dma.h
  • DMA_FLAG_HTIF2_6 : stm32h7xx_hal_dma.h
  • DMA_FLAG_HTIF3_7 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TCIF0_4 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TCIF1_5 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TCIF2_6 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TCIF3_7 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TEIF0_4 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TEIF1_5 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TEIF2_6 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TEIF3_7 : stm32h7xx_hal_dma.h
  • DMA_HandleTypeDef : stm32h7xx_hal_dma.h
  • DMA_IT_DME : stm32h7xx_hal_dma.h
  • DMA_IT_FE : stm32h7xx_hal_dma.h
  • DMA_IT_HT : stm32h7xx_hal_dma.h
  • DMA_IT_TC : stm32h7xx_hal_dma.h
  • DMA_IT_TE : stm32h7xx_hal_dma.h
  • DMA_MBURST_INC16 : stm32h7xx_hal_dma.h
  • DMA_MBURST_INC4 : stm32h7xx_hal_dma.h
  • DMA_MBURST_INC8 : stm32h7xx_hal_dma.h
  • DMA_MBURST_SINGLE : stm32h7xx_hal_dma.h
  • DMA_MDATAALIGN_BYTE : stm32h7xx_hal_dma.h
  • DMA_MDATAALIGN_HALFWORD : stm32h7xx_hal_dma.h
  • DMA_MDATAALIGN_WORD : stm32h7xx_hal_dma.h
  • DMA_MEMORY_TO_MEMORY : stm32h7xx_hal_dma.h
  • DMA_MEMORY_TO_PERIPH : stm32h7xx_hal_dma.h
  • DMA_MINC_DISABLE : stm32h7xx_hal_dma.h
  • DMA_MINC_ENABLE : stm32h7xx_hal_dma.h
  • DMA_MultiBufferSetConfig() : stm32h7xx_hal_dma_ex.c
  • DMA_NORMAL : stm32h7xx_hal_dma.h
  • DMA_PBURST_INC16 : stm32h7xx_hal_dma.h
  • DMA_PBURST_INC4 : stm32h7xx_hal_dma.h
  • DMA_PBURST_INC8 : stm32h7xx_hal_dma.h
  • DMA_PBURST_SINGLE : stm32h7xx_hal_dma.h
  • DMA_PDATAALIGN_BYTE : stm32h7xx_hal_dma.h
  • DMA_PDATAALIGN_HALFWORD : stm32h7xx_hal_dma.h
  • DMA_PDATAALIGN_WORD : stm32h7xx_hal_dma.h
  • DMA_PERIPH_TO_MEMORY : stm32h7xx_hal_dma.h
  • DMA_PFCTRL : stm32h7xx_hal_dma.h
  • DMA_PINC_DISABLE : stm32h7xx_hal_dma.h
  • DMA_PINC_ENABLE : stm32h7xx_hal_dma.h
  • DMA_PRIORITY_HIGH : stm32h7xx_hal_dma.h
  • DMA_PRIORITY_LOW : stm32h7xx_hal_dma.h
  • DMA_PRIORITY_MEDIUM : stm32h7xx_hal_dma.h
  • DMA_PRIORITY_VERY_HIGH : stm32h7xx_hal_dma.h
  • DMA_REQUEST_ADC1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_ADC2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_ADC3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_CRYP_IN : stm32h7xx_hal_dma.h
  • DMA_REQUEST_CRYP_OUT : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DAC1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DAC2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DCMI : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DFSDM1_FLT0 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DFSDM1_FLT1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DFSDM1_FLT2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DFSDM1_FLT3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR0 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR5 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR6 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR7 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_HASH_IN : stm32h7xx_hal_dma.h
  • DMA_REQUEST_HRTIM_MASTER : stm32h7xx_hal_dma.h
  • DMA_REQUEST_HRTIM_TIMER_A : stm32h7xx_hal_dma.h
  • DMA_REQUEST_HRTIM_TIMER_B : stm32h7xx_hal_dma.h
  • DMA_REQUEST_HRTIM_TIMER_C : stm32h7xx_hal_dma.h
  • DMA_REQUEST_HRTIM_TIMER_D : stm32h7xx_hal_dma.h
  • DMA_REQUEST_HRTIM_TIMER_E : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C1_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C1_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C2_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C2_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C3_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C3_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_MEM2MEM : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SAI1_A : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SAI1_B : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SAI2_A : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SAI2_B : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SAI3_A : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SAI3_B : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPDIF_RX_CS : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPDIF_RX_DT : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI1_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI1_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI2_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI2_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI3_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI3_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI4_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI4_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI5_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI5_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SWPMI_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SWPMI_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM15_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM15_COM : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM15_TRIG : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM15_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM16_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM16_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM17_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM17_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_COM : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_TRIG : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM2_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_TRIG : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM4_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_CH4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_TRIG : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM6_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM7_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_COM : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_TRIG : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART4_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART4_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART5_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART5_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART7_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART7_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART8_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART8_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART1_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART1_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART2_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART2_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART3_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART3_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART6_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART6_TX : stm32h7xx_hal_dma.h
  • DMA_SetConfig() : stm32h7xx_hal_dma.c
  • DMAMUX_POSITION_CxCR_EGE : stm32h7xx_hal_dma_ex.c
  • DMAMUX_POSITION_CxCR_SE : stm32h7xx_hal_dma_ex.c
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- e -

  • eMMC_DUAL_VOLTAGE_RANGE : stm32h7xx_hal_mmc.h
  • eMMC_HIGH_VOLTAGE_RANGE : stm32h7xx_hal_mmc.h
  • ETH_BACKOFFLIMIT_1 : stm32h7xx_hal_eth.h
  • ETH_BACKOFFLIMIT_10 : stm32h7xx_hal_eth.h
  • ETH_BACKOFFLIMIT_4 : stm32h7xx_hal_eth.h
  • ETH_BACKOFFLIMIT_8 : stm32h7xx_hal_eth.h
  • ETH_BufferTypeDef : stm32h7xx_hal_eth.h
  • ETH_BURSTLENGTH_FIXED : stm32h7xx_hal_eth.h
  • ETH_BURSTLENGTH_MIXED : stm32h7xx_hal_eth.h
  • ETH_BURSTLENGTH_UNSPECIFIED : stm32h7xx_hal_eth.h
  • ETH_CHECKSUM_BYPASSED : stm32h7xx_hal_eth.h
  • ETH_CHECKSUM_DISABLE : stm32h7xx_hal_eth.h
  • ETH_CHECKSUM_IP_HEADER_ERROR : stm32h7xx_hal_eth.h
  • ETH_CHECKSUM_IP_PAYLOAD_ERROR : stm32h7xx_hal_eth.h
  • ETH_CHECKSUM_IPHDR_INSERT : stm32h7xx_hal_eth.h
  • ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT : stm32h7xx_hal_eth.h
  • ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC : stm32h7xx_hal_eth.h
  • ETH_CRC : stm32h7xx_hal_eth.h
  • ETH_CRC_ERROR : stm32h7xx_hal_eth.h
  • ETH_CRC_INSERT : stm32h7xx_hal_eth.h
  • ETH_CRC_PAD_DISABLE : stm32h7xx_hal_eth.h
  • ETH_CRC_PAD_INSERT : stm32h7xx_hal_eth.h
  • ETH_CRC_REPLACE : stm32h7xx_hal_eth.h
  • ETH_CTRLPACKETS_BLOCK_ALL : stm32h7xx_hal_eth.h
  • ETH_CTRLPACKETS_FORWARD_ALL : stm32h7xx_hal_eth.h
  • ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA : stm32h7xx_hal_eth.h
  • ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER : stm32h7xx_hal_eth.h
  • ETH_DEST_ADDRESS_FAIL : stm32h7xx_hal_eth.h
  • ETH_DMA_ABNORMAL_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_CONTEXT_DESC_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_CONTEXT_DESC_ERROR_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_EARLY_RX_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_EARLY_TX_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_EARLY_TX_IT_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_FATAL_BUS_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_FATAL_BUS_ERROR_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_NORMAL_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_BUFFER_READ_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_BUFFER_UNAVAILABLE_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_DESC_READ_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_DESC_WRITE_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_NO_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_PROCESS_STOPPED_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_PROCESS_STOPPED_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_WATCHDOG_TIMEOUT_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_TX_BUFFER_READ_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_TX_BUFFER_UNAVAILABLE_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_TX_DESC_READ_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_TX_DESC_WRITE_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_TX_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_TX_NO_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_TX_PROCESS_STOPPED_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_TX_PROCESS_STOPPED_IT : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_RX : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_RX1_TX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_RX2_TX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_RX3_TX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_RX4_TX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_RX5_TX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_RX6_TX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_RX7_TX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_RX8_TX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_TX : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_TX1_RX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_TX2_RX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_TX3_RX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_TX4_RX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_TX5_RX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_TX6_RX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_TX7_RX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_TX8_RX1 : stm32h7xx_hal_eth.h
  • ETH_DMACCR_MASK : stm32h7xx_hal_eth.c
  • ETH_DMACRCR_MASK : stm32h7xx_hal_eth.c
  • ETH_DMACTCR_MASK : stm32h7xx_hal_eth.c
  • ETH_DMADescTypeDef : stm32h7xx_hal_eth.h
  • ETH_DMAMR_MASK : stm32h7xx_hal_eth.c
  • ETH_DMARXCDESC_CTXT : stm32h7xx_hal_eth.h
  • ETH_DMARXCDESC_OWN : stm32h7xx_hal_eth.h
  • ETH_DMARXCDESC_RTSH : stm32h7xx_hal_eth.h
  • ETH_DMARXCDESC_RTSL : stm32h7xx_hal_eth.h
  • ETH_DMARxDescListInit() : stm32h7xx_hal_eth.c
  • ETH_DMARXNDESCRF_BUF1AP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCRF_BUF1V : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCRF_BUF2AP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCRF_BUF2V : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCRF_IOC : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCRF_OWN : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_ARPNR : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_CE : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_CTXT : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_DAF : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_DE : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_ERRORS_MASK : stm32h7xx_hal_eth.c
  • ETH_DMARXNDESCWBF_ES : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_FD : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_GP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_HF : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_IPCB : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_IPCE : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_IPHE : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_IPV4 : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_IPV6 : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_IVT : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_L3FM : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_L3L4FM : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_L4FM : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_LD : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_LT : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_LT_ARP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_LT_DVLAN : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_LT_LP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_LT_MAC : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_LT_OAM : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_LT_TP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_LT_VLAN : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_MADRM : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_OE : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_OPC : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_OVT : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_OWN : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PFT : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PL : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_ANNOUNCE : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_DREQ : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_DRESP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_FUP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_MANAG : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_NO : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_PDREQ : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_PDRESP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_PDRESPFUP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_RESERVED : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_SIGN : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_SYNC : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PT : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PT_ICMP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PT_TCP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PT_UDP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PT_UNKNOWN : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PV : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_RE : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_RS0V : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_RS1V : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_RS2V : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_RWT : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_SAF : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_TD : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_TSA : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_VF : stm32h7xx_hal_eth.h
  • ETH_DMASBMR_MASK : stm32h7xx_hal_eth.c
  • ETH_DMATXCDESC_CDE : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_CTXT : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_IVLTV : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_IVT : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_IVTIR : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_IVTIR_DISABLE : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_IVTIR_INSERT : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_IVTIR_REMOVE : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_IVTIR_REPLACE : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_MSS : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_OSTC : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_OWN : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_TCMSSV : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_TTSH : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_TTSL : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_VLTV : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_VT : stm32h7xx_hal_eth.h
  • ETH_DMATxDescListInit() : stm32h7xx_hal_eth.c
  • ETH_DMATXNDESCRF_B1AP : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_B1L : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_B2AP : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_B2L : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CIC : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CIC_DISABLE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CIC_IPHDR_INSERT : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CPC : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CPC_CRC_INSERT : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CPC_CRC_REPLACE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CPC_DISABLE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CTXT : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_FD : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_FL : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_HL : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_IOC : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_LD : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_OWN : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_SAIC : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_SAIC_DISABLE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_SAIC_INSERT : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_SAIC_REPLACE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_THL : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_TPL : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_TSE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_TTSE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_VTIR : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_VTIR_DISABLE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_VTIR_INSERT : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_VTIR_REMOVE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_VTIR_REPLACE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_CC : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_CTXT : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_DB : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_DP : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_EC : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_ED : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_ES : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_FD : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_FF : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_IHE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_JT : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_LCA : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_LCO : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_LD : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_NC : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_OWN : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_PCE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_TTSE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_TTSH : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_TTSL : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_TTSS : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_UF : stm32h7xx_hal_eth.h
  • ETH_DRIBBLE_BIT_ERROR : stm32h7xx_hal_eth.h
  • ETH_EXECESSIVE_COLLISIONS : stm32h7xx_hal_eth.h
  • ETH_EXECESSIVE_DEFERRAL : stm32h7xx_hal_eth.h
  • ETH_FULLDUPLEX_MODE : stm32h7xx_hal_eth.h
  • ETH_GIANT_PACKET : stm32h7xx_hal_eth.h
  • ETH_HALFDUPLEX_MODE : stm32h7xx_hal_eth.h
  • ETH_HASH_FILTER_PASS : stm32h7xx_hal_eth.h
  • ETH_HEADER : stm32h7xx_hal_eth.h
  • ETH_INNER_TX_VLANTAG : stm32h7xx_hal_eth_ex.h
  • ETH_INNER_VLAN_DISABLE : stm32h7xx_hal_eth.h
  • ETH_INNER_VLAN_INSERT : stm32h7xx_hal_eth.h
  • ETH_INNER_VLAN_REMOVE : stm32h7xx_hal_eth.h
  • ETH_INNER_VLAN_REPLACE : stm32h7xx_hal_eth.h
  • ETH_INNERVLANTAGRXSTRIPPING_ALWAYS : stm32h7xx_hal_eth_ex.h
  • ETH_INNERVLANTAGRXSTRIPPING_IFFAILS : stm32h7xx_hal_eth_ex.h
  • ETH_INNERVLANTAGRXSTRIPPING_IFPASS : stm32h7xx_hal_eth_ex.h
  • ETH_INNERVLANTAGRXSTRIPPING_NONE : stm32h7xx_hal_eth_ex.h
  • ETH_INTERPACKETGAP_40BIT : stm32h7xx_hal_eth.h
  • ETH_INTERPACKETGAP_48BIT : stm32h7xx_hal_eth.h
  • ETH_INTERPACKETGAP_56BIT : stm32h7xx_hal_eth.h
  • ETH_INTERPACKETGAP_64BIT : stm32h7xx_hal_eth.h
  • ETH_INTERPACKETGAP_72BIT : stm32h7xx_hal_eth.h
  • ETH_INTERPACKETGAP_80BIT : stm32h7xx_hal_eth.h
  • ETH_INTERPACKETGAP_88BIT : stm32h7xx_hal_eth.h
  • ETH_INTERPACKETGAP_96BIT : stm32h7xx_hal_eth.h
  • ETH_IP_HEADER_IPV4 : stm32h7xx_hal_eth.h
  • ETH_IP_HEADER_IPV6 : stm32h7xx_hal_eth.h
  • ETH_IP_PAYLOAD_ICMPN : stm32h7xx_hal_eth.h
  • ETH_IP_PAYLOAD_TCP : stm32h7xx_hal_eth.h
  • ETH_IP_PAYLOAD_UDP : stm32h7xx_hal_eth.h
  • ETH_IP_PAYLOAD_UNKNOWN : stm32h7xx_hal_eth.h
  • ETH_JUMBO_FRAME_PAYLOAD : stm32h7xx_hal_eth.h
  • ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L3_DEST_ADDR_MATCH_DISABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L3_FILTER0_MATCH : stm32h7xx_hal_eth.h
  • ETH_L3_FILTER1_MATCH : stm32h7xx_hal_eth.h
  • ETH_L3_FILTER_0 : stm32h7xx_hal_eth_ex.h
  • ETH_L3_FILTER_1 : stm32h7xx_hal_eth_ex.h
  • ETH_L3_IPV4_MATCH : stm32h7xx_hal_eth_ex.h
  • ETH_L3_IPV6_MATCH : stm32h7xx_hal_eth_ex.h
  • ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L3_SRC_ADDR_MATCH_DISABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L4_DEST_PORT_MATCH_DISABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L4_FILTER0_MATCH : stm32h7xx_hal_eth.h
  • ETH_L4_FILTER1_MATCH : stm32h7xx_hal_eth.h
  • ETH_L4_FILTER_0 : stm32h7xx_hal_eth_ex.h
  • ETH_L4_FILTER_1 : stm32h7xx_hal_eth_ex.h
  • ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L4_SRC_PORT_MATCH_DISABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L4_TCP_MATCH : stm32h7xx_hal_eth_ex.h
  • ETH_L4_UDP_MATCH : stm32h7xx_hal_eth_ex.h
  • ETH_LATE_COLLISIONS : stm32h7xx_hal_eth.h
  • ETH_LOSS_OF_CARRIER : stm32h7xx_hal_eth.h
  • ETH_MAC_ADDR0 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDR1 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDR2 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDR3 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDR4 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDR5 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDRESS0 : stm32h7xx_hal_eth.h
  • ETH_MAC_ADDRESS1 : stm32h7xx_hal_eth.h
  • ETH_MAC_ADDRESS2 : stm32h7xx_hal_eth.h
  • ETH_MAC_ADDRESS3 : stm32h7xx_hal_eth.h
  • ETH_MAC_LPI_IT : stm32h7xx_hal_eth.h
  • ETH_MAC_MDIO_ClkConfig() : stm32h7xx_hal_eth.c
  • ETH_MAC_PHY_IT : stm32h7xx_hal_eth.h
  • ETH_MAC_PMT_IT : stm32h7xx_hal_eth.h
  • ETH_MAC_RX_STATUS_IT : stm32h7xx_hal_eth.h
  • ETH_MAC_TIMESTAMP_IT : stm32h7xx_hal_eth.h
  • ETH_MAC_TX_STATUS_IT : stm32h7xx_hal_eth.h
  • ETH_MAC_US_TICK : stm32h7xx_hal_eth.c
  • ETH_MACCR_MASK : stm32h7xx_hal_eth.c
  • ETH_MACDMAConfig() : stm32h7xx_hal_eth.c
  • ETH_MACECR_MASK : stm32h7xx_hal_eth.c
  • ETH_MACL3CR_MASK : stm32h7xx_hal_eth_ex.c
  • ETH_MACL4CR_MASK : stm32h7xx_hal_eth_ex.c
  • ETH_MACPCSR_MASK : stm32h7xx_hal_eth.c
  • ETH_MACPFR_MASK : stm32h7xx_hal_eth.c
  • ETH_MACRFCR_MASK : stm32h7xx_hal_eth.c
  • ETH_MACRXVLAN_MASK : stm32h7xx_hal_eth_ex.c
  • ETH_MACTFCR_MASK : stm32h7xx_hal_eth.c
  • ETH_MACTXVLAN_MASK : stm32h7xx_hal_eth_ex.c
  • ETH_MACWTR_MASK : stm32h7xx_hal_eth.c
  • ETH_MAGIC_PACKET_RECIEVED : stm32h7xx_hal_eth.h
  • ETH_MAX_PACKET_SIZE : stm32h7xx_hal_eth.h
  • ETH_MAX_PAYLOAD : stm32h7xx_hal_eth.h
  • ETH_MDIO_BUS_TIMEOUT : stm32h7xx_hal_eth.c
  • ETH_MediaInterfaceTypeDef : stm32h7xx_hal_eth.h
  • ETH_MIN_PAYLOAD : stm32h7xx_hal_eth.h
  • ETH_MTLRQOMR_MASK : stm32h7xx_hal_eth.c
  • ETH_MTLTQOMR_MASK : stm32h7xx_hal_eth.c
  • ETH_NO_CARRIER : stm32h7xx_hal_eth.h
  • ETH_OUTER_TX_VLANTAG : stm32h7xx_hal_eth_ex.h
  • ETH_PAUSELOWTHRESHOLD_MINUS_144 : stm32h7xx_hal_eth.h
  • ETH_PAUSELOWTHRESHOLD_MINUS_256 : stm32h7xx_hal_eth.h
  • ETH_PAUSELOWTHRESHOLD_MINUS_28 : stm32h7xx_hal_eth.h
  • ETH_PAUSELOWTHRESHOLD_MINUS_36 : stm32h7xx_hal_eth.h
  • ETH_PAUSELOWTHRESHOLD_MINUS_4 : stm32h7xx_hal_eth.h
  • ETH_PAUSELOWTHRESHOLD_MINUS_512 : stm32h7xx_hal_eth.h
  • ETH_PREAMBLELENGTH_3 : stm32h7xx_hal_eth.h
  • ETH_PREAMBLELENGTH_5 : stm32h7xx_hal_eth.h
  • ETH_PREAMBLELENGTH_7 : stm32h7xx_hal_eth.h
  • ETH_Prepare_Tx_Descriptors() : stm32h7xx_hal_eth.c
  • ETH_RECEIVE_ERROR : stm32h7xx_hal_eth.h
  • ETH_RECEIVE_OVERFLOW : stm32h7xx_hal_eth.h
  • ETH_RECEIVE_WATCHDOG_TIMEOUT : stm32h7xx_hal_eth.h
  • ETH_RECEIVESTOREFORWARD : stm32h7xx_hal_eth.h
  • ETH_RECEIVETHRESHOLD8_128 : stm32h7xx_hal_eth.h
  • ETH_RECEIVETHRESHOLD8_32 : stm32h7xx_hal_eth.h
  • ETH_RECEIVETHRESHOLD8_64 : stm32h7xx_hal_eth.h
  • ETH_RECEIVETHRESHOLD8_96 : stm32h7xx_hal_eth.h
  • ETH_RX_DESC_CNT : stm32h7xx_hal_eth.h , stm32h7xx_hal_conf.h
  • ETH_RX_LPI_ENTRY : stm32h7xx_hal_eth_ex.h
  • ETH_RX_LPI_EXIT : stm32h7xx_hal_eth_ex.h
  • ETH_RXDMABURSTLENGTH_16BEAT : stm32h7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_1BEAT : stm32h7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_2BEAT : stm32h7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_32BEAT : stm32h7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_4BEAT : stm32h7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_8BEAT : stm32h7xx_hal_eth.h
  • ETH_SetDMAConfig() : stm32h7xx_hal_eth.c
  • ETH_SetMACConfig() : stm32h7xx_hal_eth.c
  • ETH_SOURCE_ADDRESS_FAIL : stm32h7xx_hal_eth.h
  • ETH_SOURCEADDRESS_DISABLE : stm32h7xx_hal_eth.h
  • ETH_SOURCEADDRESS_INSERT_ADDR0 : stm32h7xx_hal_eth.h
  • ETH_SOURCEADDRESS_INSERT_ADDR1 : stm32h7xx_hal_eth.h
  • ETH_SOURCEADDRESS_REPLACE_ADDR0 : stm32h7xx_hal_eth.h
  • ETH_SOURCEADDRESS_REPLACE_ADDR1 : stm32h7xx_hal_eth.h
  • ETH_SPEED_100M : stm32h7xx_hal_eth.h
  • ETH_SPEED_10M : stm32h7xx_hal_eth.h
  • ETH_SRC_ADDR_CONTROL_DISABLE : stm32h7xx_hal_eth.h
  • ETH_SRC_ADDR_INSERT : stm32h7xx_hal_eth.h
  • ETH_SRC_ADDR_REPLACE : stm32h7xx_hal_eth.h
  • ETH_SWRESET_TIMEOUT : stm32h7xx_hal_eth.c
  • ETH_TRANSMIT_JABBR_TIMEOUT : stm32h7xx_hal_eth.h
  • ETH_TRANSMITSTOREFORWARD : stm32h7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLD_128 : stm32h7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLD_192 : stm32h7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLD_256 : stm32h7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLD_32 : stm32h7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLD_384 : stm32h7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLD_512 : stm32h7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLD_64 : stm32h7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLD_96 : stm32h7xx_hal_eth.h
  • ETH_TX_DESC_CNT : stm32h7xx_hal_conf.h , stm32h7xx_hal_eth.h
  • ETH_TX_LPI_ENTRY : stm32h7xx_hal_eth_ex.h
  • ETH_TX_LPI_EXIT : stm32h7xx_hal_eth_ex.h
  • ETH_TX_PACKETS_FEATURES_CRCPAD : stm32h7xx_hal_eth.h
  • ETH_TX_PACKETS_FEATURES_CSUM : stm32h7xx_hal_eth.h
  • ETH_TX_PACKETS_FEATURES_INNERVLANTAG : stm32h7xx_hal_eth.h
  • ETH_TX_PACKETS_FEATURES_SAIC : stm32h7xx_hal_eth.h
  • ETH_TX_PACKETS_FEATURES_TSO : stm32h7xx_hal_eth.h
  • ETH_TX_PACKETS_FEATURES_VLANTAG : stm32h7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_16BEAT : stm32h7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_1BEAT : stm32h7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_2BEAT : stm32h7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_32BEAT : stm32h7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_4BEAT : stm32h7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_8BEAT : stm32h7xx_hal_eth.h
  • ETH_VLAN_DISABLE : stm32h7xx_hal_eth.h
  • ETH_VLAN_FILTER_PASS : stm32h7xx_hal_eth.h
  • ETH_VLAN_INSERT : stm32h7xx_hal_eth.h
  • ETH_VLAN_REMOVE : stm32h7xx_hal_eth.h
  • ETH_VLAN_REPLACE : stm32h7xx_hal_eth.h
  • ETH_VLAN_TAG : stm32h7xx_hal_eth.h
  • ETH_VLANTAGCOMPARISON_12BIT : stm32h7xx_hal_eth.h
  • ETH_VLANTAGCOMPARISON_16BIT : stm32h7xx_hal_eth.h
  • ETH_VLANTAGCONTROL_DELETE : stm32h7xx_hal_eth_ex.h
  • ETH_VLANTAGCONTROL_INSERT : stm32h7xx_hal_eth_ex.h
  • ETH_VLANTAGCONTROL_NONE : stm32h7xx_hal_eth_ex.h
  • ETH_VLANTAGCONTROL_REPLACE : stm32h7xx_hal_eth_ex.h
  • ETH_VLANTAGRXSTRIPPING_ALWAYS : stm32h7xx_hal_eth_ex.h
  • ETH_VLANTAGRXSTRIPPING_IFFAILS : stm32h7xx_hal_eth_ex.h
  • ETH_VLANTAGRXSTRIPPING_IFPASS : stm32h7xx_hal_eth_ex.h
  • ETH_VLANTAGRXSTRIPPING_NONE : stm32h7xx_hal_eth_ex.h
  • ETH_VLANTYPECHECK_CVLAN : stm32h7xx_hal_eth_ex.h
  • ETH_VLANTYPECHECK_DISABLE : stm32h7xx_hal_eth_ex.h
  • ETH_VLANTYPECHECK_SVLAN : stm32h7xx_hal_eth_ex.h
  • ETH_WAKEUP_EXTI_LINE : stm32h7xx_hal_eth.h
  • ETH_WAKEUP_PACKET_RECIEVED : stm32h7xx_hal_eth.h
  • ETH_WATCHDOG_TIMEOUT : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_10KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_11KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_12KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_13KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_14KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_15KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_16KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_2KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_3KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_4KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_5KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_6KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_7KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_8KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_9KB : stm32h7xx_hal_eth.h
  • EXTERNAL_CLOCK_VALUE : stm32h7xx_hal_conf.h
  • EXTI_FALLING_EDGE : stm32h7xx_hal.h
  • EXTI_LINE0 : stm32h7xx_hal.h
  • EXTI_LINE1 : stm32h7xx_hal.h
  • EXTI_LINE10 : stm32h7xx_hal.h
  • EXTI_LINE11 : stm32h7xx_hal.h
  • EXTI_LINE12 : stm32h7xx_hal.h
  • EXTI_LINE13 : stm32h7xx_hal.h
  • EXTI_LINE14 : stm32h7xx_hal.h
  • EXTI_LINE15 : stm32h7xx_hal.h
  • EXTI_LINE16 : stm32h7xx_hal.h
  • EXTI_LINE17 : stm32h7xx_hal.h
  • EXTI_LINE18 : stm32h7xx_hal.h
  • EXTI_LINE19 : stm32h7xx_hal.h
  • EXTI_LINE2 : stm32h7xx_hal.h
  • EXTI_LINE20 : stm32h7xx_hal.h
  • EXTI_LINE21 : stm32h7xx_hal.h
  • EXTI_LINE22 : stm32h7xx_hal.h
  • EXTI_LINE23 : stm32h7xx_hal.h
  • EXTI_LINE24 : stm32h7xx_hal.h
  • EXTI_LINE25 : stm32h7xx_hal.h
  • EXTI_LINE26 : stm32h7xx_hal.h
  • EXTI_LINE27 : stm32h7xx_hal.h
  • EXTI_LINE28 : stm32h7xx_hal.h
  • EXTI_LINE29 : stm32h7xx_hal.h
  • EXTI_LINE3 : stm32h7xx_hal.h
  • EXTI_LINE30 : stm32h7xx_hal.h
  • EXTI_LINE31 : stm32h7xx_hal.h
  • EXTI_LINE32 : stm32h7xx_hal.h
  • EXTI_LINE33 : stm32h7xx_hal.h
  • EXTI_LINE34 : stm32h7xx_hal.h
  • EXTI_LINE35 : stm32h7xx_hal.h
  • EXTI_LINE36 : stm32h7xx_hal.h
  • EXTI_LINE37 : stm32h7xx_hal.h
  • EXTI_LINE38 : stm32h7xx_hal.h
  • EXTI_LINE39 : stm32h7xx_hal.h
  • EXTI_LINE4 : stm32h7xx_hal.h
  • EXTI_LINE40 : stm32h7xx_hal.h
  • EXTI_LINE41 : stm32h7xx_hal.h
  • EXTI_LINE42 : stm32h7xx_hal.h
  • EXTI_LINE43 : stm32h7xx_hal.h
  • EXTI_LINE44 : stm32h7xx_hal.h
  • EXTI_LINE47 : stm32h7xx_hal.h
  • EXTI_LINE48 : stm32h7xx_hal.h
  • EXTI_LINE49 : stm32h7xx_hal.h
  • EXTI_LINE5 : stm32h7xx_hal.h
  • EXTI_LINE50 : stm32h7xx_hal.h
  • EXTI_LINE51 : stm32h7xx_hal.h
  • EXTI_LINE52 : stm32h7xx_hal.h
  • EXTI_LINE53 : stm32h7xx_hal.h
  • EXTI_LINE54 : stm32h7xx_hal.h
  • EXTI_LINE55 : stm32h7xx_hal.h
  • EXTI_LINE56 : stm32h7xx_hal.h
  • EXTI_LINE57 : stm32h7xx_hal.h
  • EXTI_LINE58 : stm32h7xx_hal.h
  • EXTI_LINE59 : stm32h7xx_hal.h
  • EXTI_LINE6 : stm32h7xx_hal.h
  • EXTI_LINE60 : stm32h7xx_hal.h
  • EXTI_LINE61 : stm32h7xx_hal.h
  • EXTI_LINE62 : stm32h7xx_hal.h
  • EXTI_LINE63 : stm32h7xx_hal.h
  • EXTI_LINE64 : stm32h7xx_hal.h
  • EXTI_LINE65 : stm32h7xx_hal.h
  • EXTI_LINE66 : stm32h7xx_hal.h
  • EXTI_LINE67 : stm32h7xx_hal.h
  • EXTI_LINE68 : stm32h7xx_hal.h
  • EXTI_LINE69 : stm32h7xx_hal.h
  • EXTI_LINE7 : stm32h7xx_hal.h
  • EXTI_LINE70 : stm32h7xx_hal.h
  • EXTI_LINE71 : stm32h7xx_hal.h
  • EXTI_LINE72 : stm32h7xx_hal.h
  • EXTI_LINE73 : stm32h7xx_hal.h
  • EXTI_LINE74 : stm32h7xx_hal.h
  • EXTI_LINE75 : stm32h7xx_hal.h
  • EXTI_LINE76 : stm32h7xx_hal.h
  • EXTI_LINE8 : stm32h7xx_hal.h
  • EXTI_LINE85 : stm32h7xx_hal.h
  • EXTI_LINE86 : stm32h7xx_hal.h
  • EXTI_LINE87 : stm32h7xx_hal.h
  • EXTI_LINE9 : stm32h7xx_hal.h
  • EXTI_MODE : stm32h7xx_hal_gpio.c
  • EXTI_MODE_EVT : stm32h7xx_hal.h
  • EXTI_MODE_IT : stm32h7xx_hal.h
  • EXTI_RISING_EDGE : stm32h7xx_hal.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- f -

  • FALLING_EDGE : stm32h7xx_hal_gpio.c
  • FDCAN_ACCEPT_IN_RX_FIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_ACCEPT_IN_RX_FIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_BRS_OFF : stm32h7xx_hal_fdcan.h
  • FDCAN_BRS_ON : stm32h7xx_hal_fdcan.h
  • FDCAN_CalcultateRamBlockAddresses() : stm32h7xx_hal_fdcan.c
  • FDCAN_CALIB_CLOCK_PERIOD_COUNTER : stm32h7xx_hal_fdcan.h
  • FDCAN_CALIB_FIELD_LENGTH_32 : stm32h7xx_hal_fdcan.h
  • FDCAN_CALIB_FIELD_LENGTH_64 : stm32h7xx_hal_fdcan.h
  • FDCAN_CALIB_TIME_QUANTA_COUNTER : stm32h7xx_hal_fdcan.h
  • FDCAN_CALIB_WATCHDOG_COUNTER : stm32h7xx_hal_fdcan.h
  • FDCAN_CFG_RX_FIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_CFG_RX_FIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_CFG_TX_EVENT_FIFO : stm32h7xx_hal_fdcan.h
  • FDCAN_CLASSIC_CAN : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_BASIC_CALIBRATED : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV1 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV10 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV12 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV14 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV16 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV18 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV2 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV20 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV22 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV24 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV26 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV28 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV30 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV4 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV6 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV8 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_NOT_CALIBRATED : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_PRECISION_CALIBRATED : stm32h7xx_hal_fdcan.h
  • FDCAN_COM_STATE_IDLE : stm32h7xx_hal_fdcan.h
  • FDCAN_COM_STATE_RX : stm32h7xx_hal_fdcan.h
  • FDCAN_COM_STATE_SYNC : stm32h7xx_hal_fdcan.h
  • FDCAN_COM_STATE_TX : stm32h7xx_hal_fdcan.h
  • FDCAN_CopyMessageToRAM() : stm32h7xx_hal_fdcan.c
  • FDCAN_DATA_BYTES_12 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_16 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_20 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_24 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_32 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_48 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_64 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_8 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_FRAME : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_0 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_12 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_16 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_20 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_24 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_3 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_32 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_4 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_48 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_5 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_6 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_64 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_7 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_8 : stm32h7xx_hal_fdcan.h
  • FDCAN_ELEMENT_MASK_ANMF : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_BRS : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_DLC : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_EFC : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_ESI : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_ET : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_EXTID : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_FDF : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_FIDX : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_MM : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_RTR : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_STDID : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_TS : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_XTD : stm32h7xx_hal_fdcan.c
  • FDCAN_ERROR_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_ESI_ACTIVE : stm32h7xx_hal_fdcan.h
  • FDCAN_ESI_PASSIVE : stm32h7xx_hal_fdcan.h
  • FDCAN_EXT_EVT_SYNC_TT_OPERATION : stm32h7xx_hal_fdcan.h
  • FDCAN_EXTENDED_ID : stm32h7xx_hal_fdcan.h
  • FDCAN_FD_CAN : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_DISABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_DUAL : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_HP : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_MASK : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_RANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_RANGE_NO_EIDM : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_REJECT : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXBUFFER : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO0_HP : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO1_HP : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_ARB_PROTOCOL_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_BUS_OFF : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_CALIB_STATE_CHANGED : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_CALIB_WATCHDOG_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_DATA_PROTOCOL_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_LOGGING_OVERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_PASSIVE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_WARNING : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RAM_ACCESS_FAILURE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RAM_WATCHDOG : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RESERVED_ADDRESS_ACCESS : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_HIGH_PRIORITY_MSG : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TIMEOUT_OCCURRED : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TIMESTAMP_WRAPAROUND : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_ABORT_COMPLETE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_COMPLETE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_FIFO_EMPTY : stm32h7xx_hal_fdcan.h
  • FDCAN_FRAME_CLASSIC : stm32h7xx_hal_fdcan.h
  • FDCAN_FRAME_FD_BRS : stm32h7xx_hal_fdcan.h
  • FDCAN_FRAME_FD_NO_BRS : stm32h7xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_MSG_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_NO_FIFO : stm32h7xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_RXFIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_RXFIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_INTERRUPT_LINE0 : stm32h7xx_hal_fdcan.h
  • FDCAN_INTERRUPT_LINE1 : stm32h7xx_hal_fdcan.h
  • FDCAN_IR_MASK : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_ARB_PROTOCOL_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_BUS_OFF : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_CALIB_STATE_CHANGED : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_CALIB_WATCHDOG_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_DATA_PROTOCOL_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_ERROR_LOGGING_OVERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_ERROR_PASSIVE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_ERROR_WARNING : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RAM_ACCESS_FAILURE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RAM_WATCHDOG : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RESERVED_ADDRESS_ACCESS : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_BUFFER_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_MESSAGE_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_MESSAGE_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_HIGH_PRIORITY_MSG : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TIMEOUT_OCCURRED : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TIMESTAMP_WRAPAROUND : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_ABORT_COMPLETE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_COMPLETE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_ELT_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_NEW_DATA : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_FIFO_EMPTY : stm32h7xx_hal_fdcan.h
  • FDCAN_MODE_BUS_MONITORING : stm32h7xx_hal_fdcan.h
  • FDCAN_MODE_EXTERNAL_LOOPBACK : stm32h7xx_hal_fdcan.h
  • FDCAN_MODE_INTERNAL_LOOPBACK : stm32h7xx_hal_fdcan.h
  • FDCAN_MODE_NORMAL : stm32h7xx_hal_fdcan.h
  • FDCAN_MODE_RESTRICTED_OPERATION : stm32h7xx_hal_fdcan.h
  • FDCAN_NO_TX_EVENTS : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_ACK : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_BIT0 : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_BIT1 : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_CRC : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_FORM : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_NO_CHANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_NONE : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_STUFF : stm32h7xx_hal_fdcan.h
  • FDCAN_REJECT : stm32h7xx_hal_fdcan.h
  • FDCAN_REMOTE_FRAME : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER0 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER1 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER10 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER11 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER12 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER13 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER14 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER15 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER16 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER17 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER18 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER19 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER2 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER20 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER21 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER22 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER23 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER24 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER25 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER26 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER27 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER28 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER29 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER3 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER30 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER31 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER32 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER33 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER34 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER35 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER36 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER37 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER38 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER39 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER4 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER40 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER41 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER42 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER43 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER44 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER45 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER46 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER47 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER48 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER49 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER5 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER50 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER51 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER52 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER53 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER54 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER55 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER56 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER57 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER58 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER59 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER6 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER60 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER61 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER62 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER63 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER7 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER8 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER9 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_FIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_FIFO0_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_RX_FIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_FIFO1_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_RX_FIFO_BLOCKING : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_FIFO_OVERWRITE : stm32h7xx_hal_fdcan.h
  • FDCAN_STANDARD_ID : stm32h7xx_hal_fdcan.h
  • FDCAN_STORE_TX_EVENTS : stm32h7xx_hal_fdcan.h
  • FDCAN_STRICTLY_TT_OPERATION : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMEOUT_CONTINUOUS : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMEOUT_RX_FIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMEOUT_RX_FIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMEOUT_TX_EVENT_FIFO : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMEOUT_VALUE : stm32h7xx_hal_fdcan.c
  • FDCAN_TIMESTAMP_EXTERNAL : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_INTERNAL : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_10 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_11 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_12 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_13 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_14 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_15 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_16 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_3 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_4 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_5 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_6 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_7 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_8 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_9 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_AUTO_CLK_CALIB_DISABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_AUTO_CLK_CALIB_ENABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_BACKUP_TIME_MASTER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_COMMUNICATION_LEVEL0 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_COMMUNICATION_LEVEL1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_COMMUNICATION_LEVEL2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CURRENT_TIME_MASTER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_16 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_32 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_4 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_64 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_8 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_DISTURBING_ERROR_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TT_END_OF_LIST : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVENT_TRIGGER_0 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVENT_TRIGGER_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVENT_TRIGGER_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVENT_TRIGGER_3 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVT_TRIG_POL_FALLING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVT_TRIG_POL_RISING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EXT_CLK_SYNC_DISABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EXT_CLK_SYNC_ENABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FATAL_ERROR_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TT_FLAG_APPLICATION_WATCHDOG : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_BASIC_CYCLE_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_CONFIG_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_GLOBAL_TIME_DISC : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_GLOBAL_TIME_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_GLOBAL_TIME_WRAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_INIT_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_MATRIX_CYCLE_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_REG_TIME_MARK : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_SCHEDULING_ERROR_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_SCHEDULING_ERROR_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_START_OF_GAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_STOP_WATCH : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_SYNC_MODE_CHANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_TRIG_TIME_MARK : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_TX_COUNT_OVERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_GLOB_TIME_FILT_DISABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_GLOB_TIME_FILT_ENABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_GLOBAL_TIME_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TT_IN_GAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IN_SCHEDULE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_APPLICATION_WATCHDOG : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_BASIC_CYCLE_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_CONFIG_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_ERROR_LEVEL_CHANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_GLOBAL_TIME_DISC : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_GLOBAL_TIME_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_GLOBAL_TIME_WRAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_INIT_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_MATRIX_CYCLE_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_REG_TIME_MARK : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_SCHEDULING_ERROR_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_SCHEDULING_ERROR_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_START_OF_GAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_STOP_WATCH : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_SYNC_MODE_CHANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_TRIG_TIME_MARK : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_TX_COUNT_OVERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_TX_COUNT_UNDERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_MASTER_OFF : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_NO_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_NO_SYNC_PULSE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_OUT_OF_SYNC : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_POTENTIAL_MASTER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REF_MESSAGE_NO_PAYLOAD : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REG_TIMEMARK_CYC_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REG_TIMEMARK_DIABLED : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REG_TIMEMARK_GLO_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REG_TIMEMARK_LOC_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_16TH_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_2ND_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_32ND_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_4TH_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_64TH_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_8TH_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_RX_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_SCHEDULE_SYNC_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TT_SEVERE_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_SLAVE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_CYCLE_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_DISABLED : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_FALLING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_GLOBAL_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_LOCAL_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_RISING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_TRIGGER_0 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_TRIGGER_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_TRIGGER_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_TRIGGER_3 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_SYNC_BASIC_CYCLE_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_SYNC_MATRIX_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_SYNCHRONIZING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TIME_BASE_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TIME_MARK_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TT_TIME_SLAVE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TM_GEN_EXTERNAL_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TM_GEN_INTERNAL_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TM_NO_EXTERNAL_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TM_NO_INTERNAL_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_REF_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_REF_TRIGGER_GAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_TRIGGER_ARBITRATION : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_TRIGGER_CONTINUOUS : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_TRIGGER_MERGED : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_TRIGGER_SINGLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_WARNING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_WATCH_TRIGGER_GAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER0 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER10 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER11 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER12 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER13 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER14 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER15 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER16 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER17 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER18 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER19 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER20 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER21 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER22 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER23 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER24 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER25 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER26 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER27 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER28 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER29 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER3 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER30 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER31 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER4 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER5 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER6 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER7 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER8 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER9 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_EVENT_FIFO_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TX_FIFO_OPERATION : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_IN_SPITE_OF_ABORT : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_QUEUE_OPERATION : stm32h7xx_hal_fdcan.h
  • FLASH_BANK_1 : stm32h7xx_hal_flash_ex.h
  • FLASH_BANK_2 : stm32h7xx_hal_flash_ex.h
  • FLASH_BANK_BOTH : stm32h7xx_hal_flash_ex.h
  • FLASH_Erase_Sector() : stm32h7xx_hal_flash_ex.c , stm32h7xx_hal_flash_ex.h
  • FLASH_FLAG_ALL_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_ALL_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_ALL_ERRORS_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_ALL_ERRORS_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_BSY : stm32h7xx_hal_flash.h
  • FLASH_FLAG_BSY_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_BSY_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRC_BUSY : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRC_BUSY_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRC_BUSY_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRCEND : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRCEND_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRCEND_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_DBECCE_BANK1RR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_DBECCE_BANK2RR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_DBECCERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_EOP : stm32h7xx_hal_flash.h
  • FLASH_FLAG_EOP_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_EOP_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_INCERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_INCERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_INCERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_OPERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_OPERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_OPERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_PGSERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_PGSERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_PGSERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_QW : stm32h7xx_hal_flash.h
  • FLASH_FLAG_QW_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_QW_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDPERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDPERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDPERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDSERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDSERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDSERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_SNECCE_BANK1RR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_SNECCE_BANK2RR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_SNECCERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_STRBER_BANK1R : stm32h7xx_hal_flash.h
  • FLASH_FLAG_STRBER_BANK2R : stm32h7xx_hal_flash.h
  • FLASH_FLAG_STRBERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WBNE_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WBNE_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WDW : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WRPERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WRPERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WRPERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_ALL_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_ALL_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_CRCEND_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_CRCEND_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_DBECCERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_DBECCERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_EOP_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_EOP_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_INCERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_INCERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_OPERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_OPERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_PGSERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_PGSERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_RDPERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_RDPERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_RDSERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_RDSERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_SNECCERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_SNECCERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_STRBERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_STRBERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_WRPERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_WRPERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_KEY1 : stm32h7xx_hal_flash.h
  • FLASH_KEY2 : stm32h7xx_hal_flash.h
  • FLASH_LATENCY_0 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_1 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_2 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_3 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_4 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_5 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_6 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_7 : stm32h7xx_hal_flash_ex.h
  • FLASH_MassErase() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_BootAddConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_BOR_LevelConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_DisableWRP() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_EnableWRP() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetBootAdd() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetBOR() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetPCROP() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetRDP() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetSecureArea() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetUser() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetWRP() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_PCROPConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_RDPConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_SecureAreaConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_UserConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_WaitForLastOperation() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • FLASH_OPT_KEY1 : stm32h7xx_hal_flash.h
  • FLASH_OPT_KEY2 : stm32h7xx_hal_flash.h
  • FLASH_PROC_ALLBANK_MASSERASE : stm32h7xx_hal_flash.h
  • FLASH_PROC_MASSERASE_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_PROC_MASSERASE_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_PROC_NONE : stm32h7xx_hal_flash.h
  • FLASH_PROC_PROGRAM_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_PROC_PROGRAM_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_PROC_SECTERASE_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_PROC_SECTERASE_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_ProcedureTypeDef : stm32h7xx_hal_flash.h
  • FLASH_PSIZE_BYTE : stm32h7xx_hal_flash.h
  • FLASH_PSIZE_DOUBLE_WORD : stm32h7xx_hal_flash.h
  • FLASH_PSIZE_HALF_WORD : stm32h7xx_hal_flash.h
  • FLASH_PSIZE_WORD : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_0 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_1 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_2 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_3 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_4 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_5 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_6 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_7 : stm32h7xx_hal_flash.h
  • FLASH_SetErrorCode() : stm32h7xx_hal_flash.c
  • FLASH_TIMEOUT_VALUE : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash_ex.c
  • FLASH_TYPEERASE_MASSERASE : stm32h7xx_hal_flash_ex.h
  • FLASH_TYPEERASE_SECTORS : stm32h7xx_hal_flash_ex.h
  • FLASH_TYPEPROGRAM_FLASHWORD : stm32h7xx_hal_flash.h
  • FLASH_VOLTAGE_RANGE_1 : stm32h7xx_hal_flash_ex.h
  • FLASH_VOLTAGE_RANGE_2 : stm32h7xx_hal_flash_ex.h
  • FLASH_VOLTAGE_RANGE_3 : stm32h7xx_hal_flash_ex.h
  • FLASH_VOLTAGE_RANGE_4 : stm32h7xx_hal_flash_ex.h
  • FLASH_WaitForLastOperation() : stm32h7xx_hal_flash.h , stm32h7xx_hal_flash.c
  • FMC_SWAPBMAP_DISABLE : stm32h7xx_hal.h
  • FMC_SWAPBMAP_SDRAM_SRAM : stm32h7xx_hal.h
  • FMC_SWAPBMAP_SDRAMB2 : stm32h7xx_hal.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- g -

  • GetTimerIdxFromDMAHandle() : stm32h7xx_hal_hrtim.c
  • GPIO_AF0_LCDBIAS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF0_MCO : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF0_RTC_50Hz : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF0_SWJ : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF0_TRACE : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_COMP1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_COMP2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_OTG1_FS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_OTG2_HS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_QUADSPI : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_SAI2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_SAI4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_SDIO2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_COMP1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_COMP2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_DFSDM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_ETH : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_I2C4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_MDIOS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_OTG1_HS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_SDIO2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_SWP : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_UART7 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_COMP1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_COMP2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_FMC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_MDIOS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_OTG2_FS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_SDIO1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_COMP1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_COMP2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_DCMI : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_DSI : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF14_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF14_UART5 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF15_EVENTOUT : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_HRTIM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_LPTIM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_TIM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_TIM16 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_TIM17 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_TIM2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_HRTIM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_SAI1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM12 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM5 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_DFSDM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_HRTIM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_LPTIM2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_LPTIM3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_LPTIM4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_LPTIM5 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_LPUART : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_TIM8 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_CEC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_DFSDM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_LPTIM2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_TIM15 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_USART1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_CEC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI5 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI6 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_DFSDM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_I2C4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_SAI1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_SAI3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_SPI2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_SPI3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_UART4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_DFSDM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_SDIO1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_SPI2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_SPI3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_SPI6 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_UART7 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_USART1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_USART2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_USART3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_USART6 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_LPUART : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_SAI2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_SAI4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_SDIO1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_SPDIF : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_SPI6 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_UART4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_UART5 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_UART8 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_FDCAN1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_FDCAN2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_FMC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_QUADSPI : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_SAI4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_SDIO2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_SPDIF : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_TIM13 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_TIM14 : stm32h7xx_hal_gpio_ex.h
  • GPIO_GET_INDEX : stm32h7xx_hal_gpio_ex.h
  • GPIO_MODE : stm32h7xx_hal_gpio.c
  • GPIO_MODE_AF_OD : stm32h7xx_hal_gpio.h
  • GPIO_MODE_AF_PP : stm32h7xx_hal_gpio.h
  • GPIO_MODE_ANALOG : stm32h7xx_hal_gpio.h
  • GPIO_MODE_EVT : stm32h7xx_hal_gpio.c
  • GPIO_MODE_EVT_FALLING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING_FALLING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_INPUT : stm32h7xx_hal_gpio.h
  • GPIO_MODE_IT : stm32h7xx_hal_gpio.c
  • GPIO_MODE_IT_FALLING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_IT_RISING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_IT_RISING_FALLING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_OD : stm32h7xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_PP : stm32h7xx_hal_gpio.h
  • GPIO_NOPULL : stm32h7xx_hal_gpio.h
  • GPIO_NUMBER : stm32h7xx_hal_gpio.c
  • GPIO_OUTPUT_TYPE : stm32h7xx_hal_gpio.c
  • GPIO_PIN_0 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_1 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_10 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_11 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_12 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_13 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_14 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_15 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_2 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_3 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_4 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_5 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_6 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_7 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_8 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_9 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_All : stm32h7xx_hal_gpio.h
  • GPIO_PIN_MASK : stm32h7xx_hal_gpio.h
  • GPIO_PIN_RESET : stm32h7xx_hal_gpio.h
  • GPIO_PIN_SET : stm32h7xx_hal_gpio.h
  • GPIO_PinState : stm32h7xx_hal_gpio.h
  • GPIO_PULLDOWN : stm32h7xx_hal_gpio.h
  • GPIO_PULLUP : stm32h7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_HIGH : stm32h7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_LOW : stm32h7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_MEDIUM : stm32h7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_VERY_HIGH : stm32h7xx_hal_gpio.h
  • GPIOA_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOB_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOC_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOD_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOE_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOF_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOG_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOH_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOI_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOJ_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOK_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- h -

  • HAL_ADC_AnalogWDGConfig() : stm32h7xx_hal_adc.c
  • HAL_ADC_ConfigChannel() : stm32h7xx_hal_adc.c
  • HAL_ADC_ConvCpltCallback() : stm32h7xx_hal_adc.c
  • HAL_ADC_ConvHalfCpltCallback() : stm32h7xx_hal_adc.c
  • HAL_ADC_DeInit() : stm32h7xx_hal_adc.c
  • HAL_ADC_ERROR_DMA : stm32h7xx_hal_adc.h
  • HAL_ADC_ERROR_INTERNAL : stm32h7xx_hal_adc.h
  • HAL_ADC_ERROR_JQOVF : stm32h7xx_hal_adc.h
  • HAL_ADC_ERROR_NONE : stm32h7xx_hal_adc.h
  • HAL_ADC_ERROR_OVR : stm32h7xx_hal_adc.h
  • HAL_ADC_ErrorCallback() : stm32h7xx_hal_adc.c
  • HAL_ADC_GetError() : stm32h7xx_hal_adc.c
  • HAL_ADC_GetState() : stm32h7xx_hal_adc.c
  • HAL_ADC_GetValue() : stm32h7xx_hal_adc.c
  • HAL_ADC_Init() : stm32h7xx_hal_adc.c
  • HAL_ADC_IRQHandler() : stm32h7xx_hal_adc.c
  • HAL_ADC_LevelOutOfWindowCallback() : stm32h7xx_hal_adc.c
  • HAL_ADC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_ADC_MspDeInit() : stm32h7xx_hal_adc.c
  • HAL_ADC_MspInit() : stm32h7xx_hal_adc.c
  • HAL_ADC_PollForConversion() : stm32h7xx_hal_adc.c
  • HAL_ADC_PollForEvent() : stm32h7xx_hal_adc.c
  • HAL_ADC_Start() : stm32h7xx_hal_adc.c
  • HAL_ADC_Start_DMA() : stm32h7xx_hal_adc.c
  • HAL_ADC_Start_IT() : stm32h7xx_hal_adc.c
  • HAL_ADC_STATE_AWD1 : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_AWD2 : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_AWD3 : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_BUSY_INTERNAL : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_CONFIG : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_DMA : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_INTERNAL : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_INJ_BUSY : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_INJ_EOC : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_INJ_JQOVF : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_MULTIMODE_SLAVE : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_READY : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_REG_BUSY : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOC : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOSMP : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_REG_OVR : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_RESET : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_TIMEOUT : stm32h7xx_hal_adc.h
  • HAL_ADC_Stop() : stm32h7xx_hal_adc.c
  • HAL_ADC_Stop_DMA() : stm32h7xx_hal_adc.c
  • HAL_ADC_Stop_IT() : stm32h7xx_hal_adc.c
  • HAL_ADCEx_Calibration_GetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_SetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_Start() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_DisableInjectedQueue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_DisableVoltageRegulator() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_EnableInjectedQueue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_EndOfSamplingCallback() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_EnterADCDeepPowerDownMode() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConfigChannel() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConvCpltCallback() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedGetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedPollForConversion() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedQueueOverflowCallback() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart_IT() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop_IT() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow2Callback() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow3Callback() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_LinearCalibration_GetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_LinearCalibration_SetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeConfigChannel() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeGetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStart_DMA() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStop_DMA() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_RegularMultiModeStop_DMA() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop_DMA() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop_IT() : stm32h7xx_hal_adc_ex.c
  • HAL_CEC_ChangeRxBuffer() : stm32h7xx_hal_cec.c
  • HAL_CEC_DeInit() : stm32h7xx_hal_cec.c
  • HAL_CEC_ERROR_ARBLST : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_BRE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_LBPE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_NONE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_RXACKE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_RXOVR : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_SBPE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_TXACKE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_TXERR : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_TXUDR : stm32h7xx_hal_cec.h
  • HAL_CEC_ErrorCallback() : stm32h7xx_hal_cec.c
  • HAL_CEC_GetError() : stm32h7xx_hal_cec.c
  • HAL_CEC_GetLastReceivedFrameSize() : stm32h7xx_hal_cec.c
  • HAL_CEC_GetState() : stm32h7xx_hal_cec.c
  • HAL_CEC_Init() : stm32h7xx_hal_cec.c
  • HAL_CEC_IRQHandler() : stm32h7xx_hal_cec.c
  • HAL_CEC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_CEC_MspDeInit() : stm32h7xx_hal_cec.c
  • HAL_CEC_MspInit() : stm32h7xx_hal_cec.c
  • HAL_CEC_RxCpltCallback() : stm32h7xx_hal_cec.c
  • HAL_CEC_SetDeviceAddress() : stm32h7xx_hal_cec.c
  • HAL_CEC_STATE_BUSY : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_RX : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_RX_TX : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_TX : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_ERROR : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_READY : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_RESET : stm32h7xx_hal_cec.h
  • HAL_CEC_StateTypeDef : stm32h7xx_hal_cec.h
  • HAL_CEC_Transmit_IT() : stm32h7xx_hal_cec.c
  • HAL_CEC_TxCpltCallback() : stm32h7xx_hal_cec.c
  • HAL_COMP_DeInit() : stm32h7xx_hal_comp.c
  • HAL_COMP_GetOutputLevel() : stm32h7xx_hal_comp.c
  • HAL_COMP_GetState() : stm32h7xx_hal_comp.c
  • HAL_COMP_Init() : stm32h7xx_hal_comp.c
  • HAL_COMP_IRQHandler() : stm32h7xx_hal_comp.c
  • HAL_COMP_Lock() : stm32h7xx_hal_comp.c
  • HAL_COMP_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_COMP_MspDeInit() : stm32h7xx_hal_comp.c
  • HAL_COMP_MspInit() : stm32h7xx_hal_comp.c
  • HAL_COMP_Start() : stm32h7xx_hal_comp.c
  • HAL_COMP_Start_IT() : stm32h7xx_hal_comp.c
  • HAL_COMP_STATE_BUSY : stm32h7xx_hal_comp.h
  • HAL_COMP_STATE_BUSY_LOCKED : stm32h7xx_hal_comp.h
  • HAL_COMP_STATE_READY : stm32h7xx_hal_comp.h
  • HAL_COMP_STATE_READY_LOCKED : stm32h7xx_hal_comp.h
  • HAL_COMP_STATE_RESET : stm32h7xx_hal_comp.h
  • HAL_COMP_STATE_RESET_LOCKED : stm32h7xx_hal_comp.h
  • HAL_COMP_StateTypeDef : stm32h7xx_hal_comp.h
  • HAL_COMP_Stop() : stm32h7xx_hal_comp.c
  • HAL_COMP_Stop_IT() : stm32h7xx_hal_comp.c
  • HAL_COMP_TriggerCallback() : stm32h7xx_hal_comp.c
  • HAL_CORTEX_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_CRC_Accumulate() : stm32h7xx_hal_crc.c , stm32h7xx_hal_crc.h
  • HAL_CRC_Calculate() : stm32h7xx_hal_crc.c , stm32h7xx_hal_crc.h
  • HAL_CRC_DeInit() : stm32h7xx_hal_crc.c , stm32h7xx_hal_crc.h
  • HAL_CRC_GetState() : stm32h7xx_hal_crc.c , stm32h7xx_hal_crc.h
  • HAL_CRC_Init() : stm32h7xx_hal_crc.c , stm32h7xx_hal_crc.h
  • HAL_CRC_Input_Data_Reverse : stm32h7xx_hal_crc.h
  • HAL_CRC_LENGTH_16B : stm32h7xx_hal_crc.h
  • HAL_CRC_LENGTH_32B : stm32h7xx_hal_crc.h
  • HAL_CRC_LENGTH_7B : stm32h7xx_hal_crc.h
  • HAL_CRC_LENGTH_8B : stm32h7xx_hal_crc.h
  • HAL_CRC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_CRC_MspDeInit() : stm32h7xx_hal_crc.c , stm32h7xx_hal_crc.h
  • HAL_CRC_MspInit() : stm32h7xx_hal_crc.c , stm32h7xx_hal_crc.h
  • HAL_CRC_Output_Data_Reverse : stm32h7xx_hal_crc.h
  • HAL_CRC_STATE_BUSY : stm32h7xx_hal_crc.h
  • HAL_CRC_STATE_ERROR : stm32h7xx_hal_crc.h
  • HAL_CRC_STATE_READY : stm32h7xx_hal_crc.h
  • HAL_CRC_STATE_RESET : stm32h7xx_hal_crc.h
  • HAL_CRC_STATE_TIMEOUT : stm32h7xx_hal_crc.h
  • HAL_CRC_StateTypeDef : stm32h7xx_hal_crc.h
  • HAL_CRCEx_Input_Data_Reverse() : stm32h7xx_hal_crc_ex.c
  • HAL_CRCEx_Output_Data_Reverse() : stm32h7xx_hal_crc_ex.c
  • HAL_CRCEx_Polynomial_Set() : stm32h7xx_hal_crc_ex.c
  • HAL_CRYP_Decrypt() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Decrypt_DMA() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Decrypt_IT() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_DeInit() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Encrypt() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Encrypt_DMA() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Encrypt_IT() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_BUSY : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_DMA : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_NONE : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_NOT_SUPPORTED : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_READ : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_TIMEOUT : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_WRITE : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ErrorCallback() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_FIFO_FLUSH : stm32h7xx_hal_cryp.c
  • HAL_CRYP_GetConfig() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_GetError() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_GetState() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_InCpltCallback() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Init() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_IRQHandler() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_CRYP_MspDeInit() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_MspInit() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_OutCpltCallback() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_SetConfig() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_STATE_BUSY : stm32h7xx_hal_cryp.h
  • HAL_CRYP_STATE_READY : stm32h7xx_hal_cryp.h
  • HAL_CRYP_STATE_RESET : stm32h7xx_hal_cryp.h
  • HAL_CRYP_STATETypeDef : stm32h7xx_hal_cryp.h
  • HAL_CRYPEx_AESCCM_GenerateAuthTAG() : stm32h7xx_hal_cryp_ex.c
  • HAL_CRYPEx_AESGCM_GenerateAuthTAG() : stm32h7xx_hal_cryp_ex.c
  • HAL_DAC_ConfigChannel() : stm32h7xx_hal_dac.c
  • HAL_DAC_ConvCpltCallbackCh1() : stm32h7xx_hal_dac.c
  • HAL_DAC_ConvHalfCpltCallbackCh1() : stm32h7xx_hal_dac.c
  • HAL_DAC_DeInit() : stm32h7xx_hal_dac.c
  • HAL_DAC_DMAUnderrunCallbackCh1() : stm32h7xx_hal_dac.c
  • HAL_DAC_ERROR_DMA : stm32h7xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH1 : stm32h7xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH2 : stm32h7xx_hal_dac.h
  • HAL_DAC_ERROR_NONE : stm32h7xx_hal_dac.h
  • HAL_DAC_ERROR_TIMEOUT : stm32h7xx_hal_dac.h
  • HAL_DAC_ErrorCallbackCh1() : stm32h7xx_hal_dac.c
  • HAL_DAC_GetError() : stm32h7xx_hal_dac.c
  • HAL_DAC_GetState() : stm32h7xx_hal_dac.c
  • HAL_DAC_GetValue() : stm32h7xx_hal_dac.c
  • HAL_DAC_Init() : stm32h7xx_hal_dac.c
  • HAL_DAC_IRQHandler() : stm32h7xx_hal_dac.c
  • HAL_DAC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DAC_MspDeInit() : stm32h7xx_hal_dac.c
  • HAL_DAC_MspInit() : stm32h7xx_hal_dac.c
  • HAL_DAC_SetValue() : stm32h7xx_hal_dac.c
  • HAL_DAC_Start() : stm32h7xx_hal_dac.c
  • HAL_DAC_Start_DMA() : stm32h7xx_hal_dac.c
  • HAL_DAC_STATE_BUSY : stm32h7xx_hal_dac.h
  • HAL_DAC_STATE_ERROR : stm32h7xx_hal_dac.h
  • HAL_DAC_STATE_READY : stm32h7xx_hal_dac.h
  • HAL_DAC_STATE_RESET : stm32h7xx_hal_dac.h
  • HAL_DAC_STATE_TIMEOUT : stm32h7xx_hal_dac.h
  • HAL_DAC_StateTypeDef : stm32h7xx_hal_dac.h
  • HAL_DAC_Stop() : stm32h7xx_hal_dac.c
  • HAL_DAC_Stop_DMA() : stm32h7xx_hal_dac.c
  • HAL_DACEx_ConvCpltCallbackCh2() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_ConvHalfCpltCallbackCh2() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_DMAUnderrunCallbackCh2() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_DualGetValue() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_DualSetValue() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_ErrorCallbackCh2() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_GetTrimOffset() : stm32h7xx_hal_dac_ex.c , stm32h7xx_hal_dac_ex.h
  • HAL_DACEx_NoiseWaveGenerate() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_SelfCalibrate() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_SetUserTrimming() : stm32h7xx_hal_dac_ex.c , stm32h7xx_hal_dac_ex.h
  • HAL_DACEx_TriangleWaveGenerate() : stm32h7xx_hal_dac_ex.c
  • HAL_DCMI_ConfigCrop() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_DeInit() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_DisableCrop() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_EnableCrop() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_ERROR_DMA : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_NONE : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_OVR : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_SYNC : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_TIMEOUT : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ErrorCallback() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_FrameEventCallback() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_GetError() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_GetState() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_Init() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_IRQHandler() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_LineEventCallback() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DCMI_MspDeInit() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_MspInit() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_Resume() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_Start_DMA() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_STATE_BUSY : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_STATE_ERROR : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_STATE_READY : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_STATE_RESET : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_STATE_SUSPENDED : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_STATE_TIMEOUT : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_StateTypeDef : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_Stop() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_Suspend() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_VsyncEventCallback() : stm32h7xx_hal_dcmi.c
  • HAL_DeInit() : stm32h7xx_hal.c
  • HAL_Delay() : stm32h7xx_hal.c
  • HAL_DFSDM_CHANNEL_STATE_ERROR : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_CHANNEL_STATE_READY : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_CHANNEL_STATE_RESET : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_Channel_StateTypeDef : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_ChannelCkabCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStart() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStart_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStop() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStop_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelDeInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelGetAwdValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelGetState() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelModifyOffset() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelMspDeInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelMspInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelPollForCkab() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelPollForScd() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStart() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStart_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStop() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStop_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FILTER_STATE_ERROR : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_INJ : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_READY : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_REG : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_REG_INJ : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_RESET : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_Filter_StateTypeDef : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FilterAwdCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterAwdStart_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterAwdStop_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterConfigInjChannel() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterConfigRegChannel() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterDeInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterErrorCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterExdStart() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterExdStop() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetConvTimeValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetError() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetExdMaxValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetExdMinValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetInjectedValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetRegularValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetState() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjConvCpltCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjConvHalfCpltCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedMsbStart_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStart() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStart_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStart_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStop() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStop_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStop_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterMspDeInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterMspInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterPollForInjConversion() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterPollForRegConversion() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegConvCpltCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegConvHalfCpltCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularMsbStart_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStart() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStart_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStart_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStop() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStop_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStop_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_IRQHandler() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DisableCompensationCell() : stm32h7xx_hal.c
  • HAL_DisableDBGSleepMode() : stm32h7xx_hal.c
  • HAL_DisableDBGStandbyMode() : stm32h7xx_hal.c
  • HAL_DisableDBGStopMode() : stm32h7xx_hal.c
  • HAL_DisableDomain3DBGStandbyMode() : stm32h7xx_hal.c
  • HAL_DisableDomain3DBGStopMode() : stm32h7xx_hal.c
  • HAL_DMA2D_Abort() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_BlendingStart() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_BlendingStart_IT() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoad() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoad_IT() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoading_Abort() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoading_Resume() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoading_Suspend() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoadingCpltCallback() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_ConfigCLUT() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_ConfigDeadTime() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_ConfigLayer() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_DeInit() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_DisableCLUT : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_DisableDeadTime() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_EnableCLUT() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_EnableDeadTime() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_ERROR_CAE : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_ERROR_CE : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_ERROR_NONE : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_ERROR_TE : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_ERROR_TIMEOUT : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_GetError() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_GetState() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_Init() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_IRQHandler() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_LineEventCallback() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DMA2D_MspDeInit() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_MspInit() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_PollForTransfer() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_ProgramLineEvent() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_Resume() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_Start() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_Start_IT() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_STATE_BUSY : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_STATE_ERROR : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_STATE_READY : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_STATE_RESET : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_STATE_SUSPEND : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_STATE_TIMEOUT : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_StateTypeDef : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_Suspend() : stm32h7xx_hal_dma2d.c
  • HAL_DMA_Abort() : stm32h7xx_hal_dma.c
  • HAL_DMA_Abort_IT() : stm32h7xx_hal_dma.c
  • HAL_DMA_CallbackIDTypeDef : stm32h7xx_hal_dma.h
  • HAL_DMA_DeInit() : stm32h7xx_hal_dma.c
  • HAL_DMA_ERROR_DME : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_FE : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_NO_XFER : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_NONE : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_NOT_SUPPORTED : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_PARAM : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_REQGEN : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_SYNC : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_TE : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_TIMEOUT : stm32h7xx_hal_dma.h
  • HAL_DMA_FULL_TRANSFER : stm32h7xx_hal_dma.h
  • HAL_DMA_GetError() : stm32h7xx_hal_dma.c
  • HAL_DMA_GetState() : stm32h7xx_hal_dma.c
  • HAL_DMA_HALF_TRANSFER : stm32h7xx_hal_dma.h
  • HAL_DMA_Init() : stm32h7xx_hal_dma.c
  • HAL_DMA_IRQHandler() : stm32h7xx_hal_dma.c
  • HAL_DMA_LevelCompleteTypeDef : stm32h7xx_hal_dma.h
  • HAL_DMA_MemoryTypeDef : stm32h7xx_hal_dma_ex.h
  • HAL_DMA_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DMA_PollForTransfer() : stm32h7xx_hal_dma.c
  • HAL_DMA_RegisterCallback() : stm32h7xx_hal_dma.c
  • HAL_DMA_Start() : stm32h7xx_hal_dma.c
  • HAL_DMA_Start_IT() : stm32h7xx_hal_dma.c
  • HAL_DMA_STATE_ABORT : stm32h7xx_hal_dma.h
  • HAL_DMA_STATE_BUSY : stm32h7xx_hal_dma.h
  • HAL_DMA_STATE_ERROR : stm32h7xx_hal_dma.h
  • HAL_DMA_STATE_READY : stm32h7xx_hal_dma.h
  • HAL_DMA_STATE_RESET : stm32h7xx_hal_dma.h
  • HAL_DMA_StateTypeDef : stm32h7xx_hal_dma.h
  • HAL_DMA_UnRegisterCallback() : stm32h7xx_hal_dma.c
  • HAL_DMA_XFER_ABORT_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_ALL_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_CPLT_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_ERROR_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_HALFCPLT_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_M1CPLT_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_M1HALFCPLT_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMAEx_ChangeMemory() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_ConfigMuxRequestGenerator() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_ConfigMuxSync() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_DisableMuxRequestGenerator() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_EnableMuxRequestGenerator() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_MultiBufferStart() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_MultiBufferStart_IT() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_MUX_IRQHandler() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQUEST_GEN_EXTI0 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI0 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM1_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM2_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM3_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_TIM12_TRGO : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_ADC3_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_EXTI0 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_EXTI2 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_SPI6_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_COMP1_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_EXTI0 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_EXTI2 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_I2C4_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_LPTIM2_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_LPTIM3_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_RTC_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_SPI6_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_REQUEST_GEN_FALLING : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_REQUEST_GEN_NO_EVENT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_REQUEST_GEN_RISING : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_REQUEST_GEN_RISING_FALLING : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_FALLING : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_NO_EVENT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_RISING : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_RISING_FALLING : stm32h7xx_hal_dma_ex.h
  • HAL_EnableCompensationCell() : stm32h7xx_hal.c
  • HAL_EnableDBGSleepMode() : stm32h7xx_hal.c
  • HAL_EnableDBGStandbyMode() : stm32h7xx_hal.c
  • HAL_EnableDBGStopMode() : stm32h7xx_hal.c
  • HAL_EnableDomain3DBGStandbyMode() : stm32h7xx_hal.c
  • HAL_EnableDomain3DBGStopMode() : stm32h7xx_hal.c
  • HAL_ETH_BuildRxDescriptors() : stm32h7xx_hal_eth.c
  • HAL_ETH_DeInit() : stm32h7xx_hal_eth.c
  • HAL_ETH_DescAssignMemory() : stm32h7xx_hal_eth.c
  • HAL_ETH_DMAErrorCallback() : stm32h7xx_hal_eth.c
  • HAL_ETH_EEECallback() : stm32h7xx_hal_eth.c
  • HAL_ETH_EnterPowerDownMode() : stm32h7xx_hal_eth.c
  • HAL_ETH_ERROR_BUSY : stm32h7xx_hal_eth.h
  • HAL_ETH_ERROR_DMA : stm32h7xx_hal_eth.h
  • HAL_ETH_ERROR_MAC : stm32h7xx_hal_eth.h
  • HAL_ETH_ERROR_NONE : stm32h7xx_hal_eth.h
  • HAL_ETH_ERROR_PARAM : stm32h7xx_hal_eth.h
  • HAL_ETH_ERROR_TIMEOUT : stm32h7xx_hal_eth.h
  • HAL_ETH_ExitPowerDownMode() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetDMAConfig() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetDMAError() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetError() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetMACConfig() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetMACError() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetMACFilterConfig() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetMACWakeUpSource() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetRxDataBuffer() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetRxDataInfo() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetRxDataLength() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetState() : stm32h7xx_hal_eth.c
  • HAL_ETH_Init() : stm32h7xx_hal_eth.c
  • HAL_ETH_IRQHandler() : stm32h7xx_hal_eth.c
  • HAL_ETH_IsRxDataAvailable() : stm32h7xx_hal_eth.c
  • HAL_ETH_MACErrorCallback() : stm32h7xx_hal_eth.c
  • HAL_ETH_MII_MODE : stm32h7xx_hal_eth.h
  • HAL_ETH_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_ETH_MspDeInit() : stm32h7xx_hal_eth.c
  • HAL_ETH_MspInit() : stm32h7xx_hal_eth.c
  • HAL_ETH_PMTCallback() : stm32h7xx_hal_eth.c
  • HAL_ETH_ReadPHYRegister() : stm32h7xx_hal_eth.c
  • HAL_ETH_RMII_MODE : stm32h7xx_hal_eth.h
  • HAL_ETH_RxCpltCallback() : stm32h7xx_hal_eth.c
  • HAL_ETH_SetDMAConfig() : stm32h7xx_hal_eth.c
  • HAL_ETH_SetHashTable() : stm32h7xx_hal_eth.c
  • HAL_ETH_SetMACConfig() : stm32h7xx_hal_eth.c
  • HAL_ETH_SetMACFilterConfig() : stm32h7xx_hal_eth.c
  • HAL_ETH_SetMDIOClockRange() : stm32h7xx_hal_eth.c
  • HAL_ETH_SetRxVLANIdentifier() : stm32h7xx_hal_eth.c
  • HAL_ETH_SetSourceMACAddrMatch() : stm32h7xx_hal_eth.c
  • HAL_ETH_SetWakeUpFilter() : stm32h7xx_hal_eth.c
  • HAL_ETH_Start() : stm32h7xx_hal_eth.c
  • HAL_ETH_Start_IT() : stm32h7xx_hal_eth.c
  • HAL_ETH_STATE_BUSY : stm32h7xx_hal_eth.h
  • HAL_ETH_STATE_BUSY_RX : stm32h7xx_hal_eth.h
  • HAL_ETH_STATE_BUSY_TX : stm32h7xx_hal_eth.h
  • HAL_ETH_STATE_ERROR : stm32h7xx_hal_eth.h
  • HAL_ETH_STATE_READY : stm32h7xx_hal_eth.h
  • HAL_ETH_STATE_RESET : stm32h7xx_hal_eth.h
  • HAL_ETH_StateTypeDef : stm32h7xx_hal_eth.h
  • HAL_ETH_Stop() : stm32h7xx_hal_eth.c
  • HAL_ETH_Stop_IT() : stm32h7xx_hal_eth.c
  • HAL_ETH_Transmit() : stm32h7xx_hal_eth.c
  • HAL_ETH_Transmit_IT() : stm32h7xx_hal_eth.c
  • HAL_ETH_TxCpltCallback() : stm32h7xx_hal_eth.c
  • HAL_ETH_WakeUpCallback() : stm32h7xx_hal_eth.c
  • HAL_ETH_WritePHYRegister() : stm32h7xx_hal_eth.c
  • HAL_ETHEx_DisableARPOffload() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_DisableL3L4Filtering() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_DisableVLANProcessing() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_EnableARPOffload() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_EnableL3L4Filtering() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_EnableVLANProcessing() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_EnterLPIMode() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_ExitLPIMode() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_GetL3FilterConfig() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_GetL4FilterConfig() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_GetMACLPIEvent() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_GetRxVLANConfig() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_GetTxVLANConfig() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_SetARPAddressMatch() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_SetL3FilterConfig() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_SetL4FilterConfig() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_SetRxVLANConfig() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_SetTxVLANConfig() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_SetTxVLANIdentifier() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_SetVLANHashTable() : stm32h7xx_hal_eth_ex.c
  • HAL_EXTI_D1_ClearFlag() : stm32h7xx_hal.c
  • HAL_EXTI_D1_EventInputConfig() : stm32h7xx_hal.c
  • HAL_EXTI_D3_EventInputConfig() : stm32h7xx_hal.c
  • HAL_EXTI_EdgeConfig() : stm32h7xx_hal.c
  • HAL_EXTI_GenerateSWInterrupt() : stm32h7xx_hal.c
  • HAL_FDCAN_AbortTxRequest() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ActivateNotification() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_AddMessageToTxBuffer() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_AddMessageToTxFifoQ() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ClockCalibrationCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigClockCalibration() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigExtendedIdMask() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigFifoWatermark() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigFilter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigGlobalFilter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigInterruptLines() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigRamWatchdog() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigRxFifoOverwrite() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTimeoutCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTimestampCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTxDelayCompensation() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DeactivateNotification() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DeInit() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DisableTimeoutCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DisableTimestampCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DisableTxDelayCompensation() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnableTimeoutCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnableTimestampCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnableTxBufferRequest() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnableTxDelayCompensation() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnterPowerDownMode() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ERROR_LOG_OVERFLOW : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NONE : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_INITIALIZED : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_READY : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_STARTED : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_SUPPORTED : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PARAM : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PENDING : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PROTOCOL_ARBT : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PROTOCOL_DATA : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RAM_ACCESS : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RAM_WDG : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RESEVED_AREA : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TIMEOUT : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_APPL_WDG : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_CONFIG : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_GLOBAL_TIME : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_NO_INIT_REF : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_NO_REF : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_SCHEDULE1 : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_SCHEDULE2 : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_TX_OVERFLOW : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_TX_UNDERFLOW : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ErrorCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ExitPowerDownMode() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ExitRestrictedOperationMode() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetClockCalibrationCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetClockCalibrationState() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetError() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetErrorCounters() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetHighPriorityMessageStatus() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetProtocolStatus() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetRxFifoFillLevel() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetRxMessage() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetState() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetTimeoutCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetTimestampCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetTxEvent() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetTxFifoFreeLevel() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_HighPriorityMessageCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_Init() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_IRQHandler() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_IsRestrictedOperationMode() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_IsRxBufferMessageAvailable() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_IsTxBufferMessagePending() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_FDCAN_MspDeInit() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_MspInit() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ResetClockCalibrationState() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ResetTimeoutCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ResetTimestampCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RxBufferNewMessageCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RxFifo0Callback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RxFifo1Callback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_Start() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_STATE_BUSY : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_STATE_ERROR : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_STATE_READY : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_STATE_RESET : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_StateTypeDef : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_Stop() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TimeoutOccurredCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TimestampWraparoundCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ActivateNotification() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigExternalSyncPhase() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigInterruptLines() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigOperation() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigReferenceMessage() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigRegisterTimeMark() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigStopWatch() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigTrigger() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DeactivateNotification() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DisableExternalSynchronization() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DisableHardwareGapControl() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DisableRegisterTimeMarkPulse() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DisableTimeMarkGapControl() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DisableTriggerTimeMarkPulse() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_EnableExternalSynchronization() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_EnableHardwareGapControl() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_EnableRegisterTimeMarkPulse() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_EnableTimeMarkGapControl() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_EnableTriggerTimeMarkPulse() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_GetOperationStatus() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_GlobalTimeCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ScheduleSyncCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_SetClockSynchronization() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_SetEndOfGap() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_SetGlobalTime() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_SetNextIsGap() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_StopWatchCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_TimeMarkCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TxBufferAbortCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TxBufferCompleteCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TxEventFifoCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TxFifoEmptyCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FLASH_EndOfOperationCallback() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_DBECC : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_DBECC_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_DBECC_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_INC : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_INC_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_INC_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_NONE : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_OB_CHANGE : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_OPE : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_OPE_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_OPE_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_PGS : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_PGS_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_PGS_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDP : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDP_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDP_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDS : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDS_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDS_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_SNECC : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_SNECC_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_SNECC_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_STRB : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_STRB_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_STRB_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_GetError() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASH_IRQHandler() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASH_Lock() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASH_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_FLASH_OB_Launch() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASH_OB_Lock() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASH_OB_Unlock() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASH_OperationErrorCallback() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASH_Program() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASH_Program_IT() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASH_Unlock() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASHEx_Erase() : stm32h7xx_hal_flash_ex.c , stm32h7xx_hal_flash_ex.h
  • HAL_FLASHEx_Erase_IT() : stm32h7xx_hal_flash_ex.c , stm32h7xx_hal_flash_ex.h
  • HAL_FLASHEx_Lock_Bank1() : stm32h7xx_hal_flash_ex.c , stm32h7xx_hal_flash_ex.h
  • HAL_FLASHEx_Lock_Bank2() : stm32h7xx_hal_flash_ex.c , stm32h7xx_hal_flash_ex.h
  • HAL_FLASHEx_OBGetConfig() : stm32h7xx_hal_flash_ex.c , stm32h7xx_hal_flash_ex.h
  • HAL_FLASHEx_OBProgram() : stm32h7xx_hal_flash_ex.c , stm32h7xx_hal_flash_ex.h
  • HAL_FLASHEx_Unlock_Bank1() : stm32h7xx_hal_flash_ex.c , stm32h7xx_hal_flash_ex.h
  • HAL_FLASHEx_Unlock_Bank2() : stm32h7xx_hal_flash_ex.c , stm32h7xx_hal_flash_ex.h
  • HAL_GetCurrentCPUID() : stm32h7xx_hal_cortex.c
  • HAL_GetDEVID() : stm32h7xx_hal.c
  • HAL_GetFMCMemorySwappingConfig() : stm32h7xx_hal.c
  • HAL_GetHalVersion() : stm32h7xx_hal.c
  • HAL_GetREVID() : stm32h7xx_hal.c
  • HAL_GetTick() : stm32h7xx_hal.c
  • HAL_GPIO_DeInit() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_EXTI_Callback() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_EXTI_IRQHandler() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_Init() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_LockPin() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_GPIO_ReadPin() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_TogglePin() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_WritePin() : stm32h7xx_hal_gpio.c
  • HAL_HalfDuplex_EnableReceiver() : stm32h7xx_hal_uart.c
  • HAL_HalfDuplex_EnableTransmitter() : stm32h7xx_hal_uart.c
  • HAL_HalfDuplex_Init() : stm32h7xx_hal_uart.c
  • HAL_HASH_ContextRestoring() : stm32h7xx_hal_hash.c
  • HAL_HASH_ContextSaving() : stm32h7xx_hal_hash.c
  • HAL_HASH_DeInit() : stm32h7xx_hal_hash.c
  • HAL_HASH_DgstCpltCallback() : stm32h7xx_hal_hash.c
  • HAL_HASH_DMAFeed_ProcessSuspend() : stm32h7xx_hal_hash.c
  • HAL_HASH_ErrorCallback() : stm32h7xx_hal_hash.c
  • HAL_HASH_GetState() : stm32h7xx_hal_hash.c
  • HAL_HASH_GetStatus() : stm32h7xx_hal_hash.c
  • HAL_HASH_InCpltCallback() : stm32h7xx_hal_hash.c
  • HAL_HASH_Init() : stm32h7xx_hal_hash.c
  • HAL_HASH_IRQHandler() : stm32h7xx_hal_hash.c
  • HAL_HASH_MD5_Accumulate() : stm32h7xx_hal_hash.c
  • HAL_HASH_MD5_Finish() : stm32h7xx_hal_hash.c
  • HAL_HASH_MD5_Start() : stm32h7xx_hal_hash.c
  • HAL_HASH_MD5_Start_DMA() : stm32h7xx_hal_hash.c
  • HAL_HASH_MD5_Start_IT() : stm32h7xx_hal_hash.c
  • HAL_HASH_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_HASH_MspDeInit() : stm32h7xx_hal_hash.c
  • HAL_HASH_MspInit() : stm32h7xx_hal_hash.c
  • HAL_HASH_PHASE_HMAC_STEP_1 : stm32h7xx_hal_hash.h
  • HAL_HASH_PHASE_HMAC_STEP_2 : stm32h7xx_hal_hash.h
  • HAL_HASH_PHASE_HMAC_STEP_3 : stm32h7xx_hal_hash.h
  • HAL_HASH_PHASE_PROCESS : stm32h7xx_hal_hash.h
  • HAL_HASH_PHASE_READY : stm32h7xx_hal_hash.h
  • HAL_HASH_PhaseTypeDef : stm32h7xx_hal_hash.h
  • HAL_HASH_SHA1_Accumulate() : stm32h7xx_hal_hash.c
  • HAL_HASH_SHA1_Finish() : stm32h7xx_hal_hash.c
  • HAL_HASH_SHA1_Start() : stm32h7xx_hal_hash.c
  • HAL_HASH_SHA1_Start_DMA() : stm32h7xx_hal_hash.c
  • HAL_HASH_SHA1_Start_IT() : stm32h7xx_hal_hash.c
  • HAL_HASH_STATE_BUSY : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_ERROR : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_READY : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_RESET : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_SUSPENDED : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_TIMEOUT : stm32h7xx_hal_hash.h
  • HAL_HASH_StateTypeDef : stm32h7xx_hal_hash.h
  • HAL_HASH_SUSPEND : stm32h7xx_hal_hash.h
  • HAL_HASH_SUSPEND_NONE : stm32h7xx_hal_hash.h
  • HAL_HASH_SuspendTypeDef : stm32h7xx_hal_hash.h
  • HAL_HASH_SwFeed_ProcessSuspend() : stm32h7xx_hal_hash.c
  • HAL_HASHEx_IRQHandler : stm32h7xx_hal_hash.h
  • HAL_HASHEx_SHA224_Accumulate() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA224_Finish() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA224_Start() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA224_Start_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA224_Start_IT() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA256_Accumulate() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA256_Finish() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA256_Start() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA256_Start_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA256_Start_IT() : stm32h7xx_hal_hash_ex.c
  • HAL_HCD_Connect_Callback() : stm32h7xx_hal_hcd.c
  • HAL_HCD_DeInit() : stm32h7xx_hal_hcd.c
  • HAL_HCD_Disconnect_Callback() : stm32h7xx_hal_hcd.c
  • HAL_HCD_GetCurrentFrame() : stm32h7xx_hal_hcd.c
  • HAL_HCD_GetCurrentSpeed() : stm32h7xx_hal_hcd.c
  • HAL_HCD_GetState() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_GetState() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_GetURBState() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_GetXferCount() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_Halt() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_Init() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_NotifyURBChange_Callback() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_SubmitRequest() : stm32h7xx_hal_hcd.c
  • HAL_HCD_Init() : stm32h7xx_hal_hcd.c
  • HAL_HCD_IRQHandler() : stm32h7xx_hal_hcd.c
  • HAL_HCD_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_HCD_MspDeInit() : stm32h7xx_hal_hcd.c
  • HAL_HCD_MspInit() : stm32h7xx_hal_hcd.c
  • HAL_HCD_ResetPort() : stm32h7xx_hal_hcd.c
  • HAL_HCD_SOF_Callback() : stm32h7xx_hal_hcd.c
  • HAL_HCD_Start() : stm32h7xx_hal_hcd.c
  • HAL_HCD_STATE_BUSY : stm32h7xx_hal_hcd.h
  • HAL_HCD_STATE_ERROR : stm32h7xx_hal_hcd.h
  • HAL_HCD_STATE_READY : stm32h7xx_hal_hcd.h
  • HAL_HCD_STATE_RESET : stm32h7xx_hal_hcd.h
  • HAL_HCD_STATE_TIMEOUT : stm32h7xx_hal_hcd.h
  • HAL_HCD_Stop() : stm32h7xx_hal_hcd.c
  • HAL_HMAC_MD5_Start() : stm32h7xx_hal_hash.c
  • HAL_HMAC_MD5_Start_DMA() : stm32h7xx_hal_hash.c
  • HAL_HMAC_MD5_Start_IT() : stm32h7xx_hal_hash.c
  • HAL_HMAC_SHA1_Start() : stm32h7xx_hal_hash.c
  • HAL_HMAC_SHA1_Start_DMA() : stm32h7xx_hal_hash.c
  • HAL_HMAC_SHA1_Start_IT() : stm32h7xx_hal_hash.c
  • HAL_HMACEx_MD5_Step1_2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_MD5_Step2_3_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_MD5_Step2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA1_Step1_2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA1_Step2_3_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA1_Step2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Start() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Start_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Start_IT() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Step1_2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Step2_3_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Step2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Start() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Start_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Start_IT() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Step1_2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Step2_3_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Step2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HRTIM_ADCTriggerConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_BurstDMAConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_BurstDMATransfer() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_BurstDMATransferCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_BurstModeConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_BurstModeCtl() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_BurstModePeriodCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_BurstModeSoftwareTrigger() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Capture1EventCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Capture2EventCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_ChopperModeConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Compare1EventCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Compare2EventCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Compare3EventCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Compare4EventCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_CounterResetCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_DeadTimeConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_DeInit() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_DelayedProtectionCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_ErrorCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_EventConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_EventPrescalerConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Fault1Callback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Fault2Callback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Fault3Callback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Fault4Callback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Fault5Callback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_FaultConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_FaultModeCtl() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_FaultPrescalerConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_GetBurstStatus() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_GetCapturedValue() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_GetCurrentPushPullStatus() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_GetDelayedProtectionStatus() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_GetIdlePushPullStatus() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_GetState() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Init() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_IRQHandler() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_HRTIM_MspDeInit() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_MspInit() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Output1ResetCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Output1SetCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Output2ResetCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Output2SetCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_RegistersUpdateCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_RepetitionEventCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleBaseStart() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleBaseStart_DMA() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleBaseStart_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleBaseStop() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleBaseStop_DMA() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleBaseStop_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleCaptureChannelConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleCaptureStart() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleCaptureStart_DMA() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleCaptureStart_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleCaptureStop() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleCaptureStop_DMA() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleCaptureStop_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOCChannelConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOCStart() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOCStart_DMA() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOCStart_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOCStop() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOCStop_DMA() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOCStop_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOnePulseChannelConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOnePulseStart() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOnePulseStart_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOnePulseStop() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOnePulseStop_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimplePWMChannelConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimplePWMStart() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimplePWMStart_DMA() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimplePWMStart_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimplePWMStop() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimplePWMStop_DMA() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimplePWMStop_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SoftwareCapture() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SoftwareReset() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SoftwareUpdate() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_STATE_BUSY : stm32h7xx_hal_hrtim.h
  • HAL_HRTIM_STATE_ERROR : stm32h7xx_hal_hrtim.h
  • HAL_HRTIM_STATE_READY : stm32h7xx_hal_hrtim.h
  • HAL_HRTIM_STATE_TIMEOUT : stm32h7xx_hal_hrtim.h
  • HAL_HRTIM_StateTypeDef : stm32h7xx_hal_hrtim.h
  • HAL_HRTIM_SynchronizationEventCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SystemFaultCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_TimeBaseConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_TimerEventFilteringConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_UpdateDisable() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_UpdateEnable() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformCaptureConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformCompareConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformCounterStart() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformCounterStart_DMA() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformCounterStart_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformCounterStop() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformCounterStop_DMA() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformCounterStop_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformGetOutputLevel() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformGetOutputState() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformOutputConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformOutputStart() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformOutputStop() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformSetOutputLevel() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformTimerConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HSEM_ActivateNotification() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_DeactivateNotification() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_FastTake() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_FreeCallback() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_GetClearKey() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_IRQHandler() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_IsSemTaken() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_HSEM_Release() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_ReleaseAll() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_SetClearKey() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_Take() : stm32h7xx_hal_hsem.c
  • HAL_I2C_AbortCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_AddrCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_DeInit() : stm32h7xx_hal_i2c.c
  • HAL_I2C_DisableListen_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_EnableListen_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_ER_IRQHandler() : stm32h7xx_hal_i2c.c
  • HAL_I2C_ERROR_AF : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_ARLO : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_BERR : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_NONE : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_OVR : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_SIZE : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_TIMEOUT : stm32h7xx_hal_i2c.h
  • HAL_I2C_ErrorCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_EV_IRQHandler() : stm32h7xx_hal_i2c.c
  • HAL_I2C_GetError() : stm32h7xx_hal_i2c.c
  • HAL_I2C_GetMode() : stm32h7xx_hal_i2c.c
  • HAL_I2C_GetState() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Init() : stm32h7xx_hal_i2c.c
  • HAL_I2C_IsDeviceReady() : stm32h7xx_hal_i2c.c
  • HAL_I2C_ListenCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Abort_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Receive() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Receive_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Receive_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Sequential_Receive_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Sequential_Transmit_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Transmit() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MasterRxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MasterTxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Read() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Read_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Read_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Write() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Write_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Write_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MemRxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MemTxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MODE_MASTER : stm32h7xx_hal_i2c.h
  • HAL_I2C_MODE_MEM : stm32h7xx_hal_i2c.h
  • HAL_I2C_MODE_NONE : stm32h7xx_hal_i2c.h
  • HAL_I2C_MODE_SLAVE : stm32h7xx_hal_i2c.h
  • HAL_I2C_ModeTypeDef : stm32h7xx_hal_i2c.h
  • HAL_I2C_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_I2C_MspDeInit() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MspInit() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Receive() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Sequential_Receive_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Sequential_Transmit_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_SlaveRxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_SlaveTxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_STATE_ABORT : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX_LISTEN : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX_LISTEN : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_ERROR : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_LISTEN : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_READY : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_RESET : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_TIMEOUT : stm32h7xx_hal_i2c.h
  • HAL_I2C_StateTypeDef : stm32h7xx_hal_i2c.h
  • HAL_I2CEx_ConfigAnalogFilter() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2CEx_ConfigDigitalFilter() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableFastModePlus() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableWakeUp() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableFastModePlus() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableWakeUp() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2S_DeInit() : stm32h7xx_hal_i2s.c
  • HAL_I2S_DMAPause() : stm32h7xx_hal_i2s.c
  • HAL_I2S_DMAResume() : stm32h7xx_hal_i2s.c
  • HAL_I2S_DMAStop() : stm32h7xx_hal_i2s.c
  • HAL_I2S_ERROR_DMA : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_FRE : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_NONE : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_OVR : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_PRESCALER : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_TIMEOUT : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_UDR : stm32h7xx_hal_i2s.h
  • HAL_I2S_ErrorCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2S_GetError() : stm32h7xx_hal_i2s.c
  • HAL_I2S_GetState() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Init() : stm32h7xx_hal_i2s.c
  • HAL_I2S_IRQHandler() : stm32h7xx_hal_i2s.c
  • HAL_I2S_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_I2S_MspDeInit() : stm32h7xx_hal_i2s.c
  • HAL_I2S_MspInit() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Receive() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Receive_DMA() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Receive_IT() : stm32h7xx_hal_i2s.c
  • HAL_I2S_RxCpltCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2S_RxHalfCpltCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2S_STATE_BUSY : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_RX : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX_RX : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_ERROR : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_READY : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_RESET : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_TIMEOUT : stm32h7xx_hal_i2s.h
  • HAL_I2S_StateTypeDef : stm32h7xx_hal_i2s.h
  • HAL_I2S_Transmit() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Transmit_DMA() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Transmit_IT() : stm32h7xx_hal_i2s.c
  • HAL_I2S_TxCpltCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2S_TxHalfCpltCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2SEx_TransmitReceive() : stm32h7xx_hal_i2s_ex.c
  • HAL_I2SEx_TransmitReceive_DMA() : stm32h7xx_hal_i2s_ex.c
  • HAL_I2SEx_TransmitReceive_IT() : stm32h7xx_hal_i2s_ex.c
  • HAL_I2SEx_TxRxCpltCallback() : stm32h7xx_hal_i2s_ex.c
  • HAL_I2SEx_TxRxHalfCpltCallback() : stm32h7xx_hal_i2s_ex.c
  • HAL_IncTick() : stm32h7xx_hal.c
  • HAL_Init() : stm32h7xx_hal.c
  • HAL_InitTick() : stm32h7xx_hal.c
  • HAL_IRDA_Abort() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Abort_IT() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortReceive() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortReceive_IT() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortReceiveCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortTransmit() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortTransmit_IT() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortTransmitCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_DeInit() : stm32h7xx_hal_irda.c
  • HAL_IRDA_DMAPause() : stm32h7xx_hal_irda.c
  • HAL_IRDA_DMAResume() : stm32h7xx_hal_irda.c
  • HAL_IRDA_DMAStop() : stm32h7xx_hal_irda.c
  • HAL_IRDA_ERROR_BUSY : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_DMA : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_FE : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_NE : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_NONE : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_ORE : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_PE : stm32h7xx_hal_irda.h
  • HAL_IRDA_ErrorCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_ErrorTypeDef : stm32h7xx_hal_irda.h
  • HAL_IRDA_GetError() : stm32h7xx_hal_irda.c
  • HAL_IRDA_GetState() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Init() : stm32h7xx_hal_irda.c
  • HAL_IRDA_IRQHandler() : stm32h7xx_hal_irda.c
  • HAL_IRDA_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_IRDA_MspDeInit() : stm32h7xx_hal_irda.c
  • HAL_IRDA_MspInit() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Receive() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Receive_DMA() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Receive_IT() : stm32h7xx_hal_irda.c
  • HAL_IRDA_RxCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_RxHalfCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_STATE_BUSY : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_RX : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX_RX : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_ERROR : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_READY : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_RESET : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_TIMEOUT : stm32h7xx_hal_irda.h
  • HAL_IRDA_StateTypeDef : stm32h7xx_hal_irda.h
  • HAL_IRDA_Transmit() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Transmit_DMA() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Transmit_IT() : stm32h7xx_hal_irda.c
  • HAL_IRDA_TxCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_TxHalfCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IWDG_DEFAULT_TIMEOUT : stm32h7xx_hal_iwdg.c
  • HAL_IWDG_Init() : stm32h7xx_hal_iwdg.c
  • HAL_IWDG_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_IWDG_Refresh() : stm32h7xx_hal_iwdg.c
  • HAL_JPEG_Abort() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_ConfigEncoding() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_ConfigInputBuffer() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_ConfigOutputBuffer() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_DataReadyCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Decode() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Decode_DMA() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Decode_IT() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_DecodeCpltCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_DeInit() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_DisableHeaderParsing() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_EnableHeaderParsing() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Encode() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Encode_DMA() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Encode_IT() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_EncodeCpltCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_ERROR_DMA : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ERROR_HUFF_TABLE : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ERROR_NONE : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ERROR_QUANT_TABLE : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ERROR_TIMEOUT : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ErrorCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_GetDataCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_GetError() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_GetInfo() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_GetState() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_InfoReadyCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Init() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_IRQHandler() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_JPEG_MspDeInit() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_MspInit() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Pause() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Resume() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_SetUserQuantTables() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_STATE_BUSY : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_BUSY_DECODING : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_BUSY_ENCODING : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_ERROR : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_READY : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_RESET : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_TIMEOUT : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATETypeDef : stm32h7xx_hal_jpeg.h
  • HAL_LIN_Init() : stm32h7xx_hal_uart.c
  • HAL_LIN_SendBreak() : stm32h7xx_hal_uart.c
  • HAL_LPTIM_AutoReloadMatchCallback() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_AutoReloadWriteCallback() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_CompareMatchCallback() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_CompareWriteCallback() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_Counter_Start() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_Counter_Start_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_Counter_Stop() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_Counter_Stop_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_DeInit() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_DirectionDownCallback() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_DirectionUpCallback() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Start() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Start_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Stop() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Stop_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_GetState() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_Init() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_IRQHandler() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_LPTIM_MspDeInit() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_MspInit() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Stop() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Stop_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_PWM_Start() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_PWM_Start_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_PWM_Stop() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_PWM_Stop_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_ReadAutoReload() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_ReadCompare() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_ReadCounter() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Start() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Start_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Stop() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Stop_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_STATE_BUSY : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_STATE_ERROR : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_STATE_READY : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_STATE_RESET : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_STATE_TIMEOUT : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_StateTypeDef : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Stop() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Stop_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_TriggerCallback() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LTDC_ConfigCLUT() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ConfigColorKeying() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ConfigColorKeying_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ConfigLayer() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ConfigLayer_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DeInit() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DisableCLUT() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DisableCLUT_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DisableColorKeying() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DisableColorKeying_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DisableDither() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_EnableCLUT() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_EnableCLUT_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_EnableColorKeying() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_EnableColorKeying_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_EnableDither() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ERROR_FU : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_ERROR_NONE : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_ERROR_TE : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_ERROR_TIMEOUT : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_ErrorCallback() : stm32h7xx_hal_ltdc.c , stm32h7xx_hal_ltdc.h
  • HAL_LTDC_GetError() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_GetState() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_Init() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_IRQHandler() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_LineEventCallback() : stm32h7xx_hal_ltdc.c , stm32h7xx_hal_ltdc.h
  • HAL_LTDC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_LTDC_MspDeInit() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_MspInit() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ProgramLineEvent() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_Reload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ReloadEventCallback() : stm32h7xx_hal_ltdc.c , stm32h7xx_hal_ltdc.h
  • HAL_LTDC_SetAddress() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetAddress_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetAlpha() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetAlpha_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetPitch() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetPitch_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetPixelFormat() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetPixelFormat_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetWindowPosition() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetWindowPosition_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetWindowSize() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetWindowSize_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_STATE_BUSY : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_STATE_ERROR : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_STATE_READY : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_STATE_RESET : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_STATE_TIMEOUT : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_StateTypeDef : stm32h7xx_hal_ltdc.h
  • HAL_MDIOS_ClearReadRegAddress() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_ClearWriteRegAddress() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_DeInit() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_EnableEvents() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_ErrorCallback() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_GetError() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_GetReadRegAddress() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_GetState() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_GetWrittenRegAddress() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_Init() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_IRQHandler() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_MDIOS_MspDeInit() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_MspInit() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_ReadCpltCallback() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_ReadReg() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_STATE_BUSY : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_STATE_ERROR : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_STATE_READY : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_STATE_RESET : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_StateTypeDef : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_WakeUpCallback() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_WriteCpltCallback() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_WriteReg() : stm32h7xx_hal_mdios.c
  • HAL_MDMA_Abort() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_Abort_IT() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_BLOCK_TRANSFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_BUFFER_TRANSFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_CallbackIDTypeDef : stm32h7xx_hal_mdma.h
  • HAL_MDMA_CHANNEL_SIZE : stm32h7xx_hal_mdma.c
  • HAL_MDMA_ConfigPostRequestMask() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_DeInit() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_ERROR_ALIGNMENT : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_BLOCK_SIZE : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_BUSY : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_LINKED_LIST : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_MASK_DATA : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_NO_XFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_NONE : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_READ_XFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_TIMEOUT : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_WRITE_XFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_FULL_TRANSFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_GenerateSWRequest() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_GetError() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_GetState() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_Init() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_IRQHandler() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_LevelCompleteTypeDef : stm32h7xx_hal_mdma.h
  • HAL_MDMA_LinkedList_AddNode() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_LinkedList_CreateNode() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_LinkedList_DisableCircularMode() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_LinkedList_EnableCircularMode() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_LinkedList_RemoveNode() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_MDMA_PollForTransfer() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_RegisterCallback() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_REPEAT_BLOCK_TRANSFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_Start() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_Start_IT() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_STATE_ABORT : stm32h7xx_hal_mdma.h
  • HAL_MDMA_STATE_BUSY : stm32h7xx_hal_mdma.h
  • HAL_MDMA_STATE_ERROR : stm32h7xx_hal_mdma.h
  • HAL_MDMA_STATE_READY : stm32h7xx_hal_mdma.h
  • HAL_MDMA_STATE_RESET : stm32h7xx_hal_mdma.h
  • HAL_MDMA_StateTypeDef : stm32h7xx_hal_mdma.h
  • HAL_MDMA_UnRegisterCallback() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_XFER_ABORT_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_ALL_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_BLOCKCPLT_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_BUFFERCPLT_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_CPLT_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_ERROR_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MMC_Abort() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_Abort_IT() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_AbortCallback() : stm32h7xx_hal_mmc.c
  • HAL_MMC_CARD_DISCONNECTED : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_ERROR : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_IDENTIFICATION : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_PROGRAMMING : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_READY : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_RECEIVING : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_SENDING : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_STANDBY : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_TRANSFER : stm32h7xx_hal_mmc.h
  • HAL_MMC_CardStateTypedef : stm32h7xx_hal_mmc.h
  • HAL_MMC_ConfigWideBusOperation() : stm32h7xx_hal_mmc.c
  • HAL_MMC_DeInit() : stm32h7xx_hal_mmc.c
  • HAL_MMC_Erase() : stm32h7xx_hal_mmc.c
  • HAL_MMC_ERROR_ADDR_MISALIGNED : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_ADDR_OUT_OF_RANGE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_AKE_SEQ_ERR : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_BAD_ERASE_PARAM : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_BLOCK_LEN_ERR : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_BUSY : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CARD_ECC_DISABLED : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CARD_ECC_FAILED : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CC_ERR : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CID_CSD_OVERWRITE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CMD_CRC_FAIL : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CMD_RSP_TIMEOUT : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_COM_CRC_FAILED : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_DATA_CRC_FAIL : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_DATA_TIMEOUT : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_DMA : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_ERASE_RESET : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_ERASE_SEQ_ERR : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_ILLEGAL_CMD : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_INVALID_VOLTRANGE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_LOCK_UNLOCK_FAILED : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_NONE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_PARAM : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_RX_OVERRUN : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_STREAM_READ_UNDERRUN : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_STREAM_WRITE_OVERRUN : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_TIMEOUT : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_TX_UNDERRUN : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_UNSUPPORTED_FEATURE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_WP_ERASE_SKIP : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_WRITE_PROT_VIOLATION : stm32h7xx_hal_mmc.h
  • HAL_MMC_ErrorCallback() : stm32h7xx_hal_mmc.c
  • HAL_MMC_GetCardCID() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_GetCardCSD() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_GetCardInfo() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_GetCardState() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_GetError() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_GetState() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_Init() : stm32h7xx_hal_mmc.c
  • HAL_MMC_InitCard() : stm32h7xx_hal_mmc.c
  • HAL_MMC_IRQHandler() : stm32h7xx_hal_mmc.c
  • HAL_MMC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_MMC_MspDeInit() : stm32h7xx_hal_mmc.c
  • HAL_MMC_MspInit() : stm32h7xx_hal_mmc.c
  • HAL_MMC_ReadBlocks() : stm32h7xx_hal_mmc.c
  • HAL_MMC_ReadBlocks_DMA() : stm32h7xx_hal_mmc.c
  • HAL_MMC_ReadBlocks_IT() : stm32h7xx_hal_mmc.c
  • HAL_MMC_RxCpltCallback() : stm32h7xx_hal_mmc.c
  • HAL_MMC_STATE_BUSY : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_ERROR : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_PROGRAMMING : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_READY : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_RECEIVING : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_RESET : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_TIMEOUT : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_TRANSFER : stm32h7xx_hal_mmc.h
  • HAL_MMC_StateTypeDef : stm32h7xx_hal_mmc.h
  • HAL_MMC_TxCpltCallback() : stm32h7xx_hal_mmc.c
  • HAL_MMC_WriteBlocks() : stm32h7xx_hal_mmc.c
  • HAL_MMC_WriteBlocks_DMA() : stm32h7xx_hal_mmc.c
  • HAL_MMC_WriteBlocks_IT() : stm32h7xx_hal_mmc.c
  • HAL_MMCEx_ChangeDMABuffer() : stm32h7xx_hal_mmc_ex.c
  • HAL_MMCEx_ConfigDMAMultiBuffer() : stm32h7xx_hal_mmc_ex.c
  • HAL_MMCEx_DMABuffer_MemoryTypeDef : stm32h7xx_hal_mmc_ex.h
  • HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc_ex.h
  • HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc_ex.h
  • HAL_MMCEx_ReadBlocksDMAMultiBuffer() : stm32h7xx_hal_mmc_ex.c
  • HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc_ex.h
  • HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc_ex.h
  • HAL_MMCEx_WriteBlocksDMAMultiBuffer() : stm32h7xx_hal_mmc_ex.c
  • HAL_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_MPU_ConfigRegion() : stm32h7xx_hal_cortex.c
  • HAL_MPU_Disable() : stm32h7xx_hal_cortex.h
  • HAL_MPU_Enable() : stm32h7xx_hal_cortex.h
  • HAL_MspDeInit() : stm32h7xx_hal.c
  • HAL_MspInit() : stm32h7xx_hal.c
  • HAL_MultiProcessor_DisableMuteMode() : stm32h7xx_hal_uart.c
  • HAL_MultiProcessor_EnableMuteMode() : stm32h7xx_hal_uart.c
  • HAL_MultiProcessor_EnterMuteMode() : stm32h7xx_hal_uart.c
  • HAL_MultiProcessor_Init() : stm32h7xx_hal_uart.c
  • HAL_MultiProcessorEx_AddressLength_Set() : stm32h7xx_hal_uart_ex.c
  • HAL_NAND_Address_Inc() : stm32h7xx_hal_nand.c
  • HAL_NAND_ConfigDevice() : stm32h7xx_hal_nand.c
  • HAL_NAND_DeInit() : stm32h7xx_hal_nand.c
  • HAL_NAND_ECC_Disable() : stm32h7xx_hal_nand.c
  • HAL_NAND_ECC_Enable() : stm32h7xx_hal_nand.c
  • HAL_NAND_Erase_Block() : stm32h7xx_hal_nand.c
  • HAL_NAND_GetECC() : stm32h7xx_hal_nand.c
  • HAL_NAND_GetState() : stm32h7xx_hal_nand.c
  • HAL_NAND_Init() : stm32h7xx_hal_nand.c
  • HAL_NAND_IRQHandler() : stm32h7xx_hal_nand.c
  • HAL_NAND_ITCallback() : stm32h7xx_hal_nand.c
  • HAL_NAND_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_NAND_MspDeInit() : stm32h7xx_hal_nand.c
  • HAL_NAND_MspInit() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_ID() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_Page_16b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_Page_8b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_SpareArea_16b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_SpareArea_8b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_Status() : stm32h7xx_hal_nand.c
  • HAL_NAND_Reset() : stm32h7xx_hal_nand.c
  • HAL_NAND_STATE_BUSY : stm32h7xx_hal_nand.h
  • HAL_NAND_STATE_ERROR : stm32h7xx_hal_nand.h
  • HAL_NAND_STATE_READY : stm32h7xx_hal_nand.h
  • HAL_NAND_STATE_RESET : stm32h7xx_hal_nand.h
  • HAL_NAND_StateTypeDef : stm32h7xx_hal_nand.h
  • HAL_NAND_Write_Page_16b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Write_Page_8b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Write_SpareArea_16b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Write_SpareArea_8b() : stm32h7xx_hal_nand.c
  • HAL_NOR_DeInit() : stm32h7xx_hal_nor.c
  • HAL_NOR_Erase_Block() : stm32h7xx_hal_nor.c
  • HAL_NOR_Erase_Chip() : stm32h7xx_hal_nor.c
  • HAL_NOR_GetState() : stm32h7xx_hal_nor.c
  • HAL_NOR_GetStatus() : stm32h7xx_hal_nor.c
  • HAL_NOR_Init() : stm32h7xx_hal_nor.c
  • HAL_NOR_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_NOR_MspDeInit() : stm32h7xx_hal_nor.c
  • HAL_NOR_MspInit() : stm32h7xx_hal_nor.c
  • HAL_NOR_MspWait() : stm32h7xx_hal_nor.c
  • HAL_NOR_Program() : stm32h7xx_hal_nor.c
  • HAL_NOR_ProgramBuffer() : stm32h7xx_hal_nor.c
  • HAL_NOR_Read() : stm32h7xx_hal_nor.c
  • HAL_NOR_Read_CFI() : stm32h7xx_hal_nor.c
  • HAL_NOR_Read_ID() : stm32h7xx_hal_nor.c
  • HAL_NOR_ReadBuffer() : stm32h7xx_hal_nor.c
  • HAL_NOR_ReturnToReadMode() : stm32h7xx_hal_nor.c
  • HAL_NOR_STATE_BUSY : stm32h7xx_hal_nor.h
  • HAL_NOR_STATE_ERROR : stm32h7xx_hal_nor.h
  • HAL_NOR_STATE_PROTECTED : stm32h7xx_hal_nor.h
  • HAL_NOR_STATE_READY : stm32h7xx_hal_nor.h
  • HAL_NOR_STATE_RESET : stm32h7xx_hal_nor.h
  • HAL_NOR_StateTypeDef : stm32h7xx_hal_nor.h
  • HAL_NOR_STATUS_ERROR : stm32h7xx_hal_nor.h
  • HAL_NOR_STATUS_ONGOING : stm32h7xx_hal_nor.h
  • HAL_NOR_STATUS_SUCCESS : stm32h7xx_hal_nor.h
  • HAL_NOR_STATUS_TIMEOUT : stm32h7xx_hal_nor.h
  • HAL_NOR_StatusTypeDef : stm32h7xx_hal_nor.h
  • HAL_NOR_WriteOperation_Disable() : stm32h7xx_hal_nor.c
  • HAL_NOR_WriteOperation_Enable() : stm32h7xx_hal_nor.c
  • HAL_NVIC_ClearPendingIRQ() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_DisableIRQ() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_EnableIRQ() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_GetActive() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_GetPendingIRQ() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_GetPriority() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_GetPriorityGrouping() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_SetPendingIRQ() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_SetPriority() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_SetPriorityGrouping() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_SystemReset() : stm32h7xx_hal_cortex.c
  • HAL_OPAMP_DeInit() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_GetState() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_GetTrimOffset() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_Init() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_Lock() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_OPAMP_MspDeInit() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_MspInit() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_SelfCalibrate() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_Start() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_STATE_BUSY : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_STATE_BUSYLOCKED : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_STATE_CALIBBUSY : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_STATE_READY : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_STATE_RESET : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_StateTypeDef : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_Stop() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_TrimmingValueTypeDef : stm32h7xx_hal_opamp.h
  • HAL_OPAMPEx_SelfCalibrateAll() : stm32h7xx_hal_opamp_ex.c , stm32h7xx_hal_opamp_ex.h
  • HAL_OPAMPEx_Unlock() : stm32h7xx_hal_opamp_ex.c
  • HAL_PCD_ActivateRemoteWakeup() : stm32h7xx_hal_pcd.c
  • HAL_PCD_ConnectCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DataInStageCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DataOutStageCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DeActivateRemoteWakeup() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DeInit() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DevConnect() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DevDisconnect() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DisconnectCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_Close() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_ClrStall() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_Flush() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_GetRxCount() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_Open() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_Receive() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_SetStall() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_Transmit() : stm32h7xx_hal_pcd.c
  • HAL_PCD_GetState() : stm32h7xx_hal_pcd.c
  • HAL_PCD_Init() : stm32h7xx_hal_pcd.c
  • HAL_PCD_IRQHandler() : stm32h7xx_hal_pcd.c
  • HAL_PCD_ISOINIncompleteCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_ISOOUTIncompleteCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_PCD_MspDeInit() : stm32h7xx_hal_pcd.c
  • HAL_PCD_MspInit() : stm32h7xx_hal_pcd.c
  • HAL_PCD_ResetCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_ResumeCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_SetAddress() : stm32h7xx_hal_pcd.c
  • HAL_PCD_SetupStageCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_SOFCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_Start() : stm32h7xx_hal_pcd.c
  • HAL_PCD_STATE_BUSY : stm32h7xx_hal_pcd.h
  • HAL_PCD_STATE_ERROR : stm32h7xx_hal_pcd.h
  • HAL_PCD_STATE_READY : stm32h7xx_hal_pcd.h
  • HAL_PCD_STATE_RESET : stm32h7xx_hal_pcd.h
  • HAL_PCD_STATE_TIMEOUT : stm32h7xx_hal_pcd.h
  • HAL_PCD_Stop() : stm32h7xx_hal_pcd.c
  • HAL_PCD_SuspendCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCDEx_ActivateBCD() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_ActivateLPM() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_Callback() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_VBUSDetect() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateBCD() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateLPM() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_LPM_Callback() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_SetRxFiFo() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_SetTxFiFo() : stm32h7xx_hal_pcd_ex.c
  • HAL_PWR_ConfigPVD() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DeInit() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DisableBkUpAccess() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DisablePVD() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DisableSEVOnPend() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DisableSleepOnExit() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DisableWakeUpPin() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnableBkUpAccess() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnablePVD() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnableSEVOnPend() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnableSleepOnExit() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnableWakeUpPin() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnterSLEEPMode() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnterSTANDBYMode() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnterSTOPMode() : stm32h7xx_hal_pwr.c
  • HAL_PWR_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_PWR_PVD_IRQHandler() : stm32h7xx_hal_pwr.c
  • HAL_PWR_PVDCallback() : stm32h7xx_hal_pwr.c
  • HAL_PWREx_AVDCallback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ClearWakeupFlag() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ConfigAVD() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ConfigD3Domain() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ConfigSupply() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ControlStopModeVoltageScaling() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ControlVoltageScaling() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableAVD() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableBatteryCharging() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableBkUpReg() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableFlashPowerDown() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableMonitoring() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableUSBReg() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableUSBVoltageDetector() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableWakeUpPin() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableAVD() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableBatteryCharging() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableBkUpReg() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableFlashPowerDown() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableMonitoring() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableUSBReg() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableUSBVoltageDetector() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableWakeUpPin() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTANDBYMode() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOPMode() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetStopModeVoltageRange() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetSupplyConfig() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetTemperatureLevel() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetVBATLevel() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetVoltageRange() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetWakeupFlag() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_PVD_AVD_IRQHandler() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WAKEUP_PIN_IRQHandler() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP1_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP2_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP3_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP4_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP5_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP6_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_QPSI_TIMEOUT_DEFAULT_VALUE : stm32h7xx_hal_qspi.h
  • HAL_QSPI_Abort() : stm32h7xx_hal_qspi.h , stm32h7xx_hal_qspi.c
  • HAL_QSPI_Abort_IT() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_AbortCpltCallback() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_AutoPolling() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_AutoPolling_IT() : stm32h7xx_hal_qspi.h , stm32h7xx_hal_qspi.c
  • HAL_QSPI_CmdCpltCallback() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_Command() : stm32h7xx_hal_qspi.h , stm32h7xx_hal_qspi.c
  • HAL_QSPI_Command_IT() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_DeInit() : stm32h7xx_hal_qspi.h , stm32h7xx_hal_qspi.c
  • HAL_QSPI_ERROR_DMA : stm32h7xx_hal_qspi.h
  • HAL_QSPI_ERROR_INVALID_PARAM : stm32h7xx_hal_qspi.h
  • HAL_QSPI_ERROR_NONE : stm32h7xx_hal_qspi.h
  • HAL_QSPI_ERROR_TIMEOUT : stm32h7xx_hal_qspi.h
  • HAL_QSPI_ERROR_TRANSFER : stm32h7xx_hal_qspi.h
  • HAL_QSPI_ErrorCallback() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_FifoThresholdCallback() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_GetError() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_GetFifoThreshold() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_GetState() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_Init() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_IRQHandler() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_MemoryMapped() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_QSPI_MspDeInit() : stm32h7xx_hal_qspi.h , stm32h7xx_hal_qspi.c
  • HAL_QSPI_MspInit() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_Receive() : stm32h7xx_hal_qspi.h , stm32h7xx_hal_qspi.c
  • HAL_QSPI_Receive_DMA() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_Receive_IT() : stm32h7xx_hal_qspi.h , stm32h7xx_hal_qspi.c
  • HAL_QSPI_RxCpltCallback() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_RxHalfCpltCallback() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_SetFifoThreshold() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_SetTimeout() : stm32h7xx_hal_qspi.h , stm32h7xx_hal_qspi.c
  • HAL_QSPI_STATE_ABORT : stm32h7xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY : stm32h7xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_AUTO_POLLING : stm32h7xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_INDIRECT_RX : stm32h7xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_INDIRECT_TX : stm32h7xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_MEM_MAPPED : stm32h7xx_hal_qspi.h
  • HAL_QSPI_STATE_ERROR : stm32h7xx_hal_qspi.h
  • HAL_QSPI_STATE_READY : stm32h7xx_hal_qspi.h
  • HAL_QSPI_STATE_RESET : stm32h7xx_hal_qspi.h
  • HAL_QSPI_StateTypeDef : stm32h7xx_hal_qspi.h
  • HAL_QSPI_StatusMatchCallback() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_TimeOutCallback() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_Transmit() : stm32h7xx_hal_qspi.h , stm32h7xx_hal_qspi.c
  • HAL_QSPI_Transmit_DMA() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_Transmit_IT() : stm32h7xx_hal_qspi.h , stm32h7xx_hal_qspi.c
  • HAL_QSPI_TxCpltCallback() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_TxHalfCpltCallback() : stm32h7xx_hal_qspi.h , stm32h7xx_hal_qspi.c
  • HAL_RCC_CCSCallback() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_ClockConfig() : stm32h7xx_hal_rcc.c
  • HAL_RCC_DeInit() : stm32h7xx_hal_rcc.c
  • HAL_RCC_DisableCSS() : stm32h7xx_hal_rcc.h
  • HAL_RCC_EnableCSS() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_GetClockConfig() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_GetHCLKFreq() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_GetOscConfig() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_GetPCLK1Freq() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_GetPCLK2Freq() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_GetSysClockFreq() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_MCOConfig() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_RCC_NMI_IRQHandler() : stm32h7xx_hal_rcc.h , stm32h7xx_hal_rcc.c
  • HAL_RCC_OscConfig() : stm32h7xx_hal_rcc.c
  • HAL_RCCEx_CRS_ErrorCallback() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_ExpectedSyncCallback() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_IRQHandler() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_SyncOkCallback() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_SyncWarnCallback() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSConfig() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSGetSynchronizationInfo() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSSoftwareSynchronizationGenerate() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSWaitSynchronization() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_DisableLSECSS() : stm32h7xx_hal_rcc_ex.c , stm32h7xx_hal_rcc_ex.h
  • HAL_RCCEx_EnableLSECSS() : stm32h7xx_hal_rcc_ex.c , stm32h7xx_hal_rcc_ex.h
  • HAL_RCCEx_GetD1PCLK1Freq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetD1SysClockFreq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetD3PCLK1Freq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKConfig() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKFreq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPLL1ClockFreq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPLL2ClockFreq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPLL3ClockFreq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_KerWakeUpStopCLKConfig() : stm32h7xx_hal_rcc_ex.h , stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_PeriphCLKConfig() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_WakeUpStopCLKConfig() : stm32h7xx_hal_rcc_ex.c , stm32h7xx_hal_rcc_ex.h
  • HAL_RCCEx_WWDGxSysResetConfig() : stm32h7xx_hal_rcc_ex.c , stm32h7xx_hal_rcc_ex.h
  • HAL_ResumeTick() : stm32h7xx_hal.c
  • HAL_RNG_DeInit() : stm32h7xx_hal_rng.c
  • HAL_RNG_ErrorCallback() : stm32h7xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber() : stm32h7xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber_IT() : stm32h7xx_hal_rng.c
  • HAL_RNG_GetState() : stm32h7xx_hal_rng.c
  • HAL_RNG_Init() : stm32h7xx_hal_rng.c
  • HAL_RNG_IRQHandler() : stm32h7xx_hal_rng.c
  • HAL_RNG_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_RNG_MspDeInit() : stm32h7xx_hal_rng.c
  • HAL_RNG_MspInit() : stm32h7xx_hal_rng.c
  • HAL_RNG_ReadLastRandomNumber() : stm32h7xx_hal_rng.c
  • HAL_RNG_ReadyDataCallback() : stm32h7xx_hal_rng.c
  • HAL_RNG_STATE_BUSY : stm32h7xx_hal_rng.h
  • HAL_RNG_STATE_ERROR : stm32h7xx_hal_rng.h
  • HAL_RNG_STATE_READY : stm32h7xx_hal_rng.h
  • HAL_RNG_STATE_RESET : stm32h7xx_hal_rng.h
  • HAL_RNG_STATE_TIMEOUT : stm32h7xx_hal_rng.h
  • HAL_RNG_StateTypeDef : stm32h7xx_hal_rng.h
  • HAL_RS485Ex_Init() : stm32h7xx_hal_uart_ex.c
  • HAL_RTC_AlarmAEventCallback() : stm32h7xx_hal_rtc.c
  • HAL_RTC_AlarmIRQHandler() : stm32h7xx_hal_rtc.c
  • HAL_RTC_DeactivateAlarm() : stm32h7xx_hal_rtc.c
  • HAL_RTC_DeInit() : stm32h7xx_hal_rtc.c
  • HAL_RTC_GetAlarm() : stm32h7xx_hal_rtc.c
  • HAL_RTC_GetDate() : stm32h7xx_hal_rtc.c
  • HAL_RTC_GetState() : stm32h7xx_hal_rtc.c
  • HAL_RTC_GetTime() : stm32h7xx_hal_rtc.c
  • HAL_RTC_Init() : stm32h7xx_hal_rtc.c
  • HAL_RTC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_RTC_MspDeInit() : stm32h7xx_hal_rtc.c
  • HAL_RTC_MspInit() : stm32h7xx_hal_rtc.c
  • HAL_RTC_PollForAlarmAEvent() : stm32h7xx_hal_rtc.c
  • HAL_RTC_SetAlarm() : stm32h7xx_hal_rtc.c
  • HAL_RTC_SetAlarm_IT() : stm32h7xx_hal_rtc.c
  • HAL_RTC_SetDate() : stm32h7xx_hal_rtc.c
  • HAL_RTC_SetTime() : stm32h7xx_hal_rtc.c
  • HAL_RTC_STATE_BUSY : stm32h7xx_hal_rtc.h
  • HAL_RTC_STATE_ERROR : stm32h7xx_hal_rtc.h
  • HAL_RTC_STATE_READY : stm32h7xx_hal_rtc.h
  • HAL_RTC_STATE_RESET : stm32h7xx_hal_rtc.h
  • HAL_RTC_STATE_TIMEOUT : stm32h7xx_hal_rtc.h
  • HAL_RTC_WaitForSynchro() : stm32h7xx_hal_rtc.c
  • HAL_RTCEx_AlarmBEventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPRead() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPWrite() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateCalibrationOutPut() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateInternalTimeStamp() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateRefClock() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTamper() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTimeStamp() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateWakeUpTimer() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DisableBypassShadow() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_EnableBypassShadow() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_GetTimeStamp() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_GetWakeUpTimer() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForAlarmBEvent() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper1Event() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper2Event() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper3Event() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTimeStampEvent() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForWakeUpTimerEvent() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetCalibrationOutPut() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTimeStamp() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetRefClock() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSmoothCalib() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSynchroShift() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper_IT() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp_IT() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer_IT() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper1EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper2EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper3EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_TamperTimeStampIRQHandler() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_TimeStampEventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerEventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerIRQHandler() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCStateTypeDef : stm32h7xx_hal_rtc.h
  • HAL_SAI_Abort() : stm32h7xx_hal_sai.c
  • HAL_SAI_DeInit() : stm32h7xx_hal_sai.c
  • HAL_SAI_DisableRxMuteMode() : stm32h7xx_hal_sai.c
  • HAL_SAI_DisableTxMuteMode() : stm32h7xx_hal_sai.c
  • HAL_SAI_DMAPause() : stm32h7xx_hal_sai.c
  • HAL_SAI_DMAResume() : stm32h7xx_hal_sai.c
  • HAL_SAI_DMAStop() : stm32h7xx_hal_sai.c
  • HAL_SAI_EnableRxMuteMode() : stm32h7xx_hal_sai.c
  • HAL_SAI_EnableTxMuteMode() : stm32h7xx_hal_sai.c
  • HAL_SAI_ERROR_AFSDET : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_CNREADY : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_DMA : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_LFSDET : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_NONE : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_OVR : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_TIMEOUT : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_UDR : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_WCKCFG : stm32h7xx_hal_sai.h
  • HAL_SAI_ErrorCallback() : stm32h7xx_hal_sai.c
  • HAL_SAI_GetError() : stm32h7xx_hal_sai.c
  • HAL_SAI_GetState() : stm32h7xx_hal_sai.c
  • HAL_SAI_Init() : stm32h7xx_hal_sai.c
  • HAL_SAI_InitProtocol() : stm32h7xx_hal_sai.c
  • HAL_SAI_IRQHandler() : stm32h7xx_hal_sai.c
  • HAL_SAI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SAI_MspDeInit() : stm32h7xx_hal_sai.c
  • HAL_SAI_MspInit() : stm32h7xx_hal_sai.c
  • HAL_SAI_Receive() : stm32h7xx_hal_sai.c
  • HAL_SAI_Receive_DMA() : stm32h7xx_hal_sai.c
  • HAL_SAI_Receive_IT() : stm32h7xx_hal_sai.c
  • HAL_SAI_RxCpltCallback() : stm32h7xx_hal_sai.c
  • HAL_SAI_RxHalfCpltCallback() : stm32h7xx_hal_sai.c
  • HAL_SAI_STATE_BUSY : stm32h7xx_hal_sai.h
  • HAL_SAI_STATE_BUSY_RX : stm32h7xx_hal_sai.h
  • HAL_SAI_STATE_BUSY_TX : stm32h7xx_hal_sai.h
  • HAL_SAI_STATE_READY : stm32h7xx_hal_sai.h
  • HAL_SAI_STATE_RESET : stm32h7xx_hal_sai.h
  • HAL_SAI_StateTypeDef : stm32h7xx_hal_sai.h
  • HAL_SAI_Transmit() : stm32h7xx_hal_sai.c
  • HAL_SAI_Transmit_DMA() : stm32h7xx_hal_sai.c
  • HAL_SAI_Transmit_IT() : stm32h7xx_hal_sai.c
  • HAL_SAI_TxCpltCallback() : stm32h7xx_hal_sai.c
  • HAL_SAI_TxHalfCpltCallback() : stm32h7xx_hal_sai.c
  • HAL_SAIEx_ConfigPdmMicDelay() : stm32h7xx_hal_sai_ex.c
  • HAL_SD_Abort() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd.h
  • HAL_SD_Abort_IT() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd.h
  • HAL_SD_AbortCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_CARD_DISCONNECTED : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_ERROR : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_IDENTIFICATION : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_PROGRAMMING : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_READY : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_RECEIVING : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_SENDING : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_STANDBY : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_TRANSFER : stm32h7xx_hal_sd.h
  • HAL_SD_CardStateTypedef : stm32h7xx_hal_sd.h
  • HAL_SD_ConfigWideBusOperation() : stm32h7xx_hal_sd.c
  • HAL_SD_DeInit() : stm32h7xx_hal_sd.c
  • HAL_SD_DriveTransciver_1_8V_Callback() : stm32h7xx_hal_sd.c
  • HAL_SD_Erase() : stm32h7xx_hal_sd.c
  • HAL_SD_ERROR_ADDR_MISALIGNED : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_ADDR_OUT_OF_RANGE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_AKE_SEQ_ERR : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_BAD_ERASE_PARAM : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_BLOCK_LEN_ERR : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_BUSY : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CARD_ECC_DISABLED : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CARD_ECC_FAILED : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CC_ERR : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CID_CSD_OVERWRITE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CMD_CRC_FAIL : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CMD_RSP_TIMEOUT : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_COM_CRC_FAILED : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_DATA_CRC_FAIL : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_DATA_TIMEOUT : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_DMA : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_ERASE_RESET : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_ERASE_SEQ_ERR : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_GENERAL_UNKNOWN_ERR : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_ILLEGAL_CMD : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_INVALID_VOLTRANGE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_LOCK_UNLOCK_FAILED : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_NONE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_PARAM : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_REQUEST_NOT_APPLICABLE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_RX_OVERRUN : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_STREAM_READ_UNDERRUN : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_STREAM_WRITE_OVERRUN : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_TIMEOUT : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_TX_UNDERRUN : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_UNSUPPORTED_FEATURE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_WP_ERASE_SKIP : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_WRITE_PROT_VIOLATION : stm32h7xx_hal_sd.h
  • HAL_SD_ErrorCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_GetCardCID() : stm32h7xx_hal_sd.h , stm32h7xx_hal_sd.c
  • HAL_SD_GetCardCSD() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd.h
  • HAL_SD_GetCardInfo() : stm32h7xx_hal_sd.h , stm32h7xx_hal_sd.c
  • HAL_SD_GetCardState() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd.h
  • HAL_SD_GetCardStatus() : stm32h7xx_hal_sd.h , stm32h7xx_hal_sd.c
  • HAL_SD_GetError() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd.h
  • HAL_SD_GetState() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd.h
  • HAL_SD_Init() : stm32h7xx_hal_sd.c
  • HAL_SD_InitCard() : stm32h7xx_hal_sd.c
  • HAL_SD_IRQHandler() : stm32h7xx_hal_sd.c
  • HAL_SD_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SD_MspDeInit() : stm32h7xx_hal_sd.c
  • HAL_SD_MspInit() : stm32h7xx_hal_sd.c
  • HAL_SD_ReadBlocks() : stm32h7xx_hal_sd.c
  • HAL_SD_ReadBlocks_DMA() : stm32h7xx_hal_sd.c
  • HAL_SD_ReadBlocks_IT() : stm32h7xx_hal_sd.c
  • HAL_SD_RxCpltCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_SendSDStatus() : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_BUSY : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_ERROR : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_PROGRAMMING : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_READY : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_RECEIVING : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_RESET : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_TIMEOUT : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_TRANSFER : stm32h7xx_hal_sd.h
  • HAL_SD_StateTypeDef : stm32h7xx_hal_sd.h
  • HAL_SD_TxCpltCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_WriteBlocks() : stm32h7xx_hal_sd.c
  • HAL_SD_WriteBlocks_DMA() : stm32h7xx_hal_sd.c
  • HAL_SD_WriteBlocks_IT() : stm32h7xx_hal_sd.c
  • HAL_SDEx_ChangeDMABuffer() : stm32h7xx_hal_sd_ex.c
  • HAL_SDEx_ConfigDMAMultiBuffer() : stm32h7xx_hal_sd_ex.c
  • HAL_SDEx_DMABuffer_MemoryTypeDef : stm32h7xx_hal_sd_ex.h
  • HAL_SDEx_Read_DMADoubleBuffer0CpltCallback() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd_ex.h
  • HAL_SDEx_Read_DMADoubleBuffer1CpltCallback() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd_ex.h
  • HAL_SDEx_ReadBlocksDMAMultiBuffer() : stm32h7xx_hal_sd_ex.c
  • HAL_SDEx_Write_DMADoubleBuffer0CpltCallback() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd_ex.h
  • HAL_SDEx_Write_DMADoubleBuffer1CpltCallback() : stm32h7xx_hal_sd_ex.h , stm32h7xx_hal_sd.c
  • HAL_SDEx_WriteBlocksDMAMultiBuffer() : stm32h7xx_hal_sd_ex.c
  • HAL_SDRAM_DeInit() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_DMA_XferCpltCallback() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_DMA_XferErrorCallback() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_GetModeStatus() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_GetState() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Init() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_IRQHandler() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SDRAM_MspDeInit() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_MspInit() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_ProgramRefreshRate() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Read_16b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Read_32b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Read_8b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Read_DMA() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_RefreshErrorCallback() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_SendCommand() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_SetAutoRefreshNumber() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_STATE_BUSY : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_STATE_ERROR : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_STATE_PRECHARGED : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_STATE_READY : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_STATE_RESET : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_STATE_WRITE_PROTECTED : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_StateTypeDef : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_Write_16b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Write_32b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Write_8b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Write_DMA() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_WriteProtection_Disable() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_WriteProtection_Enable() : stm32h7xx_hal_sdram.c
  • HAL_SetFMCMemorySwappingConfig() : stm32h7xx_hal.c
  • HAL_SMARTCARD_Abort() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Abort_IT() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortCpltCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive_IT() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceiveCpltCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit_IT() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmitCpltCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_DeInit() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_ERROR_DMA : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_FE : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NE : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NONE : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_ORE : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_PE : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_RTO : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_UDR : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ErrorCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_ErrorTypeDef : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_GetError() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_GetState() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Init() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_IRQHandler() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SMARTCARD_MspDeInit() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_MspInit() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_DMA() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_IT() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_RxCpltCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_STATE_BUSY : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_RX : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX_RX : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_ERROR : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_READY : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_RESET : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_TIMEOUT : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_StateTypeDef : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_Transmit() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_DMA() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_IT() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_TxCpltCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARDEx_BlockLength_Config() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableReceiverTimeOut() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableReceiverTimeOut() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TimeOut_Config() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMBUS_AddrCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_DeInit() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_DisableAlert_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_DisableListen_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_EnableAlert_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_EnableListen_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ER_IRQHandler() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_ERROR_ACKF : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ALERT : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ARLO : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BERR : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BUSTIMEOUT : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_HALTIMEOUT : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_NONE : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_OVR : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_PECERR : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ErrorCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_EV_IRQHandler() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_GetError() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_GetState() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_Init() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_IsDeviceReady() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ListenCpltCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_Master_Abort_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_Master_Receive_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_Master_Transmit_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_MasterRxCpltCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_MasterTxCpltCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SMBUS_MspDeInit() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_MspInit() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_Slave_Receive_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_Slave_Transmit_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_SlaveRxCpltCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_SlaveTxCpltCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_STATE_BUSY : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_ERROR : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_LISTEN : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_RX : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_TX : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_READY : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_RESET : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_RX : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_TX : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_TIMEOUT : stm32h7xx_hal_smbus.h
  • HAL_SPDIFRX_CxCpltCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_CxHalfCpltCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_DeInit() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_DMAStop() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ERROR_DMA : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_NONE : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_OVR : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_PE : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_TIMEOUT : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_UNKNOWN : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ErrorCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_GetError() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_GetState() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_Init() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_IRQHandler() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SPDIFRX_MspDeInit() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_MspInit() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveControlFlow() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveControlFlow_DMA() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveControlFlow_IT() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveDataFlow() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveDataFlow_DMA() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveDataFlow_IT() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_RxCpltCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_RxHalfCpltCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_SetDataFormat() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_STATE_BUSY : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_BUSY_CX : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_BUSY_RX : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_ERROR : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_READY : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_RESET : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_StateTypeDef : stm32h7xx_hal_spdifrx.h
  • HAL_SPI_Abort() : stm32h7xx_hal_spi.c
  • HAL_SPI_Abort_IT() : stm32h7xx_hal_spi.c
  • HAL_SPI_AbortCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_DeInit() : stm32h7xx_hal_spi.c
  • HAL_SPI_DMAPause() : stm32h7xx_hal_spi.c
  • HAL_SPI_DMAResume() : stm32h7xx_hal_spi.c
  • HAL_SPI_DMAStop() : stm32h7xx_hal_spi.c
  • HAL_SPI_ERROR_ABORT : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_CRC : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_DMA : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_FLAG : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_FRE : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_MODF : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_NONE : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_OVR : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_TIMEOUT : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_UDR : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_UNKNOW : stm32h7xx_hal_spi.h
  • HAL_SPI_ErrorCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_GetError() : stm32h7xx_hal_spi.c
  • HAL_SPI_GetState() : stm32h7xx_hal_spi.c
  • HAL_SPI_Init() : stm32h7xx_hal_spi.c
  • HAL_SPI_IRQHandler() : stm32h7xx_hal_spi.c
  • HAL_SPI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SPI_MspDeInit() : stm32h7xx_hal_spi.c
  • HAL_SPI_MspInit() : stm32h7xx_hal_spi.c
  • HAL_SPI_Receive() : stm32h7xx_hal_spi.c
  • HAL_SPI_Receive_DMA() : stm32h7xx_hal_spi.c
  • HAL_SPI_Receive_IT() : stm32h7xx_hal_spi.c
  • HAL_SPI_RxCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_RxHalfCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_STATE_ABORT : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_RX : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX_RX : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_ERROR : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_READY : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_RESET : stm32h7xx_hal_spi.h
  • HAL_SPI_StateTypeDef : stm32h7xx_hal_spi.h
  • HAL_SPI_Transmit() : stm32h7xx_hal_spi.c
  • HAL_SPI_Transmit_DMA() : stm32h7xx_hal_spi.c
  • HAL_SPI_Transmit_IT() : stm32h7xx_hal_spi.c
  • HAL_SPI_TransmitReceive() : stm32h7xx_hal_spi.c
  • HAL_SPI_TransmitReceive_DMA() : stm32h7xx_hal_spi.c
  • HAL_SPI_TransmitReceive_IT() : stm32h7xx_hal_spi.c
  • HAL_SPI_TxCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_TxHalfCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_TxRxCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_TxRxHalfCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPIEx_ConfigureUnderrun() : stm32h7xx_hal_spi_ex.c
  • HAL_SPIEx_DisableLockConfiguration() : stm32h7xx_hal_spi_ex.c
  • HAL_SPIEx_EnableLockConfiguration() : stm32h7xx_hal_spi_ex.c
  • HAL_SPIEx_FlushRxFifo() : stm32h7xx_hal_spi_ex.c
  • HAL_SRAM_DeInit() : stm32h7xx_hal_sram.c
  • HAL_SRAM_DMA_XferCpltCallback() : stm32h7xx_hal_sram.c , stm32h7xx_hal_sram.h
  • HAL_SRAM_DMA_XferErrorCallback() : stm32h7xx_hal_sram.h , stm32h7xx_hal_sram.c
  • HAL_SRAM_GetState() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Init() : stm32h7xx_hal_sram.c
  • HAL_SRAM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SRAM_MspDeInit() : stm32h7xx_hal_sram.c
  • HAL_SRAM_MspInit() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Read_16b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Read_32b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Read_8b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Read_DMA() : stm32h7xx_hal_sram.c
  • HAL_SRAM_STATE_BUSY : stm32h7xx_hal_sram.h
  • HAL_SRAM_STATE_ERROR : stm32h7xx_hal_sram.h
  • HAL_SRAM_STATE_PROTECTED : stm32h7xx_hal_sram.h
  • HAL_SRAM_STATE_READY : stm32h7xx_hal_sram.h
  • HAL_SRAM_STATE_RESET : stm32h7xx_hal_sram.h
  • HAL_SRAM_StateTypeDef : stm32h7xx_hal_sram.h
  • HAL_SRAM_Write_16b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Write_32b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Write_8b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Write_DMA() : stm32h7xx_hal_sram.c
  • HAL_SRAM_WriteOperation_Disable() : stm32h7xx_hal_sram.c
  • HAL_SRAM_WriteOperation_Enable() : stm32h7xx_hal_sram.c
  • HAL_SuspendTick() : stm32h7xx_hal.c
  • HAL_SWPMI_DeInit() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_DisableLoopback() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_DMAStop() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_EnableLoopback() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_CRC : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_DMA : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_NONE : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_OVR : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_UDR : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ErrorCallback() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_GetError() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_GetState() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_Init() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_IRQHandler() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SWPMI_MspDeInit() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_MspInit() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_Receive() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_Receive_DMA() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_Receive_IT() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_RxCpltCallback() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_RxHalfCpltCallback() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_BUSY : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_BUSY_RX : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_BUSY_TX : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_BUSY_TX_RX : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_ERROR : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_READY : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_RESET : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_TIMEOUT : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_StateTypeDef : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_Transmit() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_Transmit_DMA() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_Transmit_IT() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_TxCpltCallback() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_TxHalfCpltCallback() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SYSCFG_AnalogSwitchConfig() : stm32h7xx_hal.c
  • HAL_SYSCFG_CM7BootAddConfig() : stm32h7xx_hal.c
  • HAL_SYSCFG_CompensationCodeConfig() : stm32h7xx_hal.c
  • HAL_SYSCFG_CompensationCodeSelect() : stm32h7xx_hal.c
  • HAL_SYSCFG_DisableBOOST() : stm32h7xx_hal.c
  • HAL_SYSCFG_DisableIOSpeedOptimize() : stm32h7xx_hal.c
  • HAL_SYSCFG_DisableVREFBUF() : stm32h7xx_hal.c
  • HAL_SYSCFG_EnableBOOST() : stm32h7xx_hal.c
  • HAL_SYSCFG_EnableIOSpeedOptimize() : stm32h7xx_hal.c
  • HAL_SYSCFG_EnableVREFBUF() : stm32h7xx_hal.c
  • HAL_SYSCFG_ETHInterfaceSelect() : stm32h7xx_hal.c
  • HAL_SYSCFG_VREFBUF_HighImpedanceConfig() : stm32h7xx_hal.c
  • HAL_SYSCFG_VREFBUF_TrimmingConfig() : stm32h7xx_hal.c
  • HAL_SYSCFG_VREFBUF_VoltageScalingConfig() : stm32h7xx_hal.c
  • HAL_SYSTICK_Callback() : stm32h7xx_hal_cortex.c
  • HAL_SYSTICK_CLKSourceConfig() : stm32h7xx_hal_cortex.c
  • HAL_SYSTICK_Config() : stm32h7xx_hal_cortex.c
  • HAL_SYSTICK_IRQHandler() : stm32h7xx_hal_cortex.c
  • HAL_TIM_ACTIVE_CHANNEL_1 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_2 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_3 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_4 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_5 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_6 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_CLEARED : stm32h7xx_hal_tim.h
  • HAL_TIM_ActiveChannel : stm32h7xx_hal_tim.h
  • HAL_TIM_Base_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Start_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Stop_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_ConfigClockSource() : stm32h7xx_hal_tim.c
  • HAL_TIM_ConfigOCrefClear() : stm32h7xx_hal_tim.c
  • HAL_TIM_ConfigTI1Input() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStart() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStop() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStart() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStop() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMACaptureCplt() : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim.c
  • HAL_TIM_DMADelayPulseCplt() : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim.c
  • HAL_TIM_DMAError() : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Start_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_ErrorCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_GenerateEvent() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_CaptureCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_ConfigChannel() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Start_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Stop_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_IRQHandler() : stm32h7xx_hal_tim.c
  • HAL_TIM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_TIM_OC_ConfigChannel() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_DelayElapsedCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Start_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Stop_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_ConfigChannel() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_PeriodElapsedCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_ConfigChannel() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Start_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Stop_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_ReadCapturedValue() : stm32h7xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization() : stm32h7xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_STATE_BUSY : stm32h7xx_hal_tim.h
  • HAL_TIM_STATE_ERROR : stm32h7xx_hal_tim.h
  • HAL_TIM_STATE_READY : stm32h7xx_hal_tim.h
  • HAL_TIM_STATE_RESET : stm32h7xx_hal_tim.h
  • HAL_TIM_STATE_TIMEOUT : stm32h7xx_hal_tim.h
  • HAL_TIM_StateTypeDef : stm32h7xx_hal_tim.h
  • HAL_TIM_TriggerCallback() : stm32h7xx_hal_tim.c
  • HAL_TIMEOUT_ADDR : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_BUSY : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_DCMI_STOP : stm32h7xx_hal_dcmi.c
  • HAL_TIMEOUT_DIR : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_DMA_ABORT : stm32h7xx_hal_dma.c
  • HAL_TIMEOUT_MDMA_ABORT : stm32h7xx_hal_mdma.c
  • HAL_TIMEOUT_RXNE : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_STOPF : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_TC : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_TCR : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_TXIS : stm32h7xx_hal_smbus.c
  • HAL_TIMEx_BreakCallback() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_CommutationCallback() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakDeadTime() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakInput() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_DMACommutationCplt() : stm32h7xx_hal_tim_ex.c , stm32h7xx_hal_tim_ex.h
  • HAL_TIMEx_GroupChannel5() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_DeInit() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_GetState() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Init() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspDeInit() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspInit() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_MasterConfigSynchronization() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_RemapConfig() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_TISelection() : stm32h7xx_hal_tim_ex.c
  • HAL_UART_Abort() : stm32h7xx_hal_uart.c
  • HAL_UART_Abort_IT() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortReceive() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortReceive_IT() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortReceiveCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortTransmit() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortTransmit_IT() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortTransmitCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_DeInit() : stm32h7xx_hal_uart.c
  • HAL_UART_DMAPause() : stm32h7xx_hal_uart.c
  • HAL_UART_DMAResume() : stm32h7xx_hal_uart.c
  • HAL_UART_DMAStop() : stm32h7xx_hal_uart.c
  • HAL_UART_ERROR_DMA : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_FE : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_NE : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_NONE : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_ORE : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_PE : stm32h7xx_hal_uart.h
  • HAL_UART_ErrorCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_ErrorTypeDef : stm32h7xx_hal_uart.h
  • HAL_UART_GetError() : stm32h7xx_hal_uart.c
  • HAL_UART_GetState() : stm32h7xx_hal_uart.c
  • HAL_UART_Init() : stm32h7xx_hal_uart.c
  • HAL_UART_IRQHandler() : stm32h7xx_hal_uart.c
  • HAL_UART_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_UART_MspDeInit() : stm32h7xx_hal_uart.c
  • HAL_UART_MspInit() : stm32h7xx_hal_uart.c
  • HAL_UART_Receive() : stm32h7xx_hal_uart.c
  • HAL_UART_Receive_DMA() : stm32h7xx_hal_uart.c
  • HAL_UART_Receive_IT() : stm32h7xx_hal_uart.c
  • HAL_UART_RxCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_RxHalfCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_STATE_BUSY : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_BUSY_RX : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX_RX : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_ERROR : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_READY : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_RESET : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_TIMEOUT : stm32h7xx_hal_uart.h
  • HAL_UART_StateTypeDef : stm32h7xx_hal_uart.h
  • HAL_UART_TIMEOUT_VALUE : stm32h7xx_hal_uart.h
  • HAL_UART_Transmit() : stm32h7xx_hal_uart.c
  • HAL_UART_Transmit_DMA() : stm32h7xx_hal_uart.c
  • HAL_UART_Transmit_IT() : stm32h7xx_hal_uart.c
  • HAL_UART_TxCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_TxHalfCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UARTEx_DisableStopMode() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_EnableStopMode() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_StopModeWakeUpSourceConfig() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_WakeupCallback() : stm32h7xx_hal_uart_ex.c
  • HAL_USART_Abort() : stm32h7xx_hal_usart.c
  • HAL_USART_Abort_IT() : stm32h7xx_hal_usart.c
  • HAL_USART_AbortCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_DeInit() : stm32h7xx_hal_usart.c
  • HAL_USART_DMAPause() : stm32h7xx_hal_usart.c
  • HAL_USART_DMAResume() : stm32h7xx_hal_usart.c
  • HAL_USART_DMAStop() : stm32h7xx_hal_usart.c
  • HAL_USART_ERROR_DMA : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_FE : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_NE : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_NONE : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_ORE : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_PE : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_UDR : stm32h7xx_hal_usart.h
  • HAL_USART_ErrorCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_ErrorTypeDef : stm32h7xx_hal_usart.h
  • HAL_USART_GetError() : stm32h7xx_hal_usart.c
  • HAL_USART_GetState() : stm32h7xx_hal_usart.c
  • HAL_USART_Init() : stm32h7xx_hal_usart.c
  • HAL_USART_IRQHandler() : stm32h7xx_hal_usart.c
  • HAL_USART_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_USART_MspDeInit() : stm32h7xx_hal_usart.c
  • HAL_USART_MspInit() : stm32h7xx_hal_usart.c
  • HAL_USART_Receive() : stm32h7xx_hal_usart.c
  • HAL_USART_Receive_DMA() : stm32h7xx_hal_usart.c
  • HAL_USART_Receive_IT() : stm32h7xx_hal_usart.c
  • HAL_USART_RxCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_RxHalfCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_STATE_BUSY : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_BUSY_RX : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX_RX : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_ERROR : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_READY : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_RESET : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_TIMEOUT : stm32h7xx_hal_usart.h
  • HAL_USART_StateTypeDef : stm32h7xx_hal_usart.h
  • HAL_USART_Transmit() : stm32h7xx_hal_usart.c
  • HAL_USART_Transmit_DMA() : stm32h7xx_hal_usart.c
  • HAL_USART_Transmit_IT() : stm32h7xx_hal_usart.c
  • HAL_USART_TransmitReceive() : stm32h7xx_hal_usart.c
  • HAL_USART_TransmitReceive_DMA() : stm32h7xx_hal_usart.c
  • HAL_USART_TransmitReceive_IT() : stm32h7xx_hal_usart.c
  • HAL_USART_TxCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_TxHalfCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_TxRxCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_WWDG_EarlyWakeupCallback() : stm32h7xx_hal_wwdg.c
  • HAL_WWDG_Init() : stm32h7xx_hal_wwdg.c
  • HAL_WWDG_IRQHandler() : stm32h7xx_hal_wwdg.c
  • HAL_WWDG_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_WWDG_MspInit() : stm32h7xx_hal_wwdg.c
  • HAL_WWDG_Refresh() : stm32h7xx_hal_wwdg.c
  • HASH_Accumulate() : stm32h7xx_hal_hash.c
  • HASH_ALGOMODE_HASH : stm32h7xx_hal_hash.h
  • HASH_ALGOMODE_HMAC : stm32h7xx_hal_hash.h
  • HASH_ALGOSELECTION_MD5 : stm32h7xx_hal_hash.h
  • HASH_ALGOSELECTION_SHA1 : stm32h7xx_hal_hash.h
  • HASH_ALGOSELECTION_SHA224 : stm32h7xx_hal_hash.h
  • HASH_ALGOSELECTION_SHA256 : stm32h7xx_hal_hash.h
  • HASH_DATATYPE_16B : stm32h7xx_hal_hash.h
  • HASH_DATATYPE_1B : stm32h7xx_hal_hash.h
  • HASH_DATATYPE_32B : stm32h7xx_hal_hash.h
  • HASH_DATATYPE_8B : stm32h7xx_hal_hash.h
  • HASH_DIGEST_CALCULATION_NOT_STARTED : stm32h7xx_hal_hash.c
  • HASH_DIGEST_CALCULATION_STARTED : stm32h7xx_hal_hash.c
  • HASH_DIGEST_LENGTH : stm32h7xx_hal_hash.h
  • HASH_DMAError() : stm32h7xx_hal_hash.c
  • HASH_DMAXferCplt() : stm32h7xx_hal_hash.c
  • HASH_Finish() : stm32h7xx_hal_hash.c
  • HASH_FLAG_BUSY : stm32h7xx_hal_hash.h
  • HASH_FLAG_DCIS : stm32h7xx_hal_hash.h
  • HASH_FLAG_DINIS : stm32h7xx_hal_hash.h
  • HASH_FLAG_DINNE : stm32h7xx_hal_hash.h
  • HASH_FLAG_DMAS : stm32h7xx_hal_hash.h
  • HASH_GetDigest() : stm32h7xx_hal_hash.c
  • HASH_HMAC_KEYTYPE_LONGKEY : stm32h7xx_hal_hash.h
  • HASH_HMAC_KEYTYPE_SHORTKEY : stm32h7xx_hal_hash.h
  • HASH_IT() : stm32h7xx_hal_hash.c
  • HASH_IT_DCI : stm32h7xx_hal_hash.h
  • HASH_IT_DINI : stm32h7xx_hal_hash.h
  • HASH_NBW_PUSHED : stm32h7xx_hal_hash.h
  • HASH_NUMBER_OF_CSR_REGISTERS : stm32h7xx_hal_hash.c
  • HASH_Start() : stm32h7xx_hal_hash.c
  • HASH_Start_DMA() : stm32h7xx_hal_hash.c
  • HASH_Start_IT() : stm32h7xx_hal_hash.c
  • HASH_TIMEOUTVALUE : stm32h7xx_hal_hash.c
  • HASH_WaitOnFlagUntilTimeout() : stm32h7xx_hal_hash.c
  • HASH_Write_Block_Data() : stm32h7xx_hal_hash.c
  • HASH_WriteData() : stm32h7xx_hal_hash.c
  • HCD_HC_IN_IRQHandler() : stm32h7xx_hal_hcd.c
  • HCD_HC_OUT_IRQHandler() : stm32h7xx_hal_hcd.c
  • HCD_HCStateTypeDef : stm32h7xx_hal_hcd.h
  • HCD_HCTypeDef : stm32h7xx_hal_hcd.h
  • HCD_InitTypeDef : stm32h7xx_hal_hcd.h
  • HCD_PHY_EMBEDDED : stm32h7xx_hal_hcd.h
  • HCD_PHY_ULPI : stm32h7xx_hal_hcd.h
  • HCD_Port_IRQHandler() : stm32h7xx_hal_hcd.c
  • HCD_RXQLVL_IRQHandler() : stm32h7xx_hal_hcd.c
  • HCD_SPEED_FULL : stm32h7xx_hal_hcd.h
  • HCD_SPEED_HIGH : stm32h7xx_hal_hcd.h
  • HCD_SPEED_LOW : stm32h7xx_hal_hcd.h
  • HCD_StateTypeDef : stm32h7xx_hal_hcd.h
  • HCD_TypeDef : stm32h7xx_hal_hcd.h
  • HCD_URBStateTypeDef : stm32h7xx_hal_hcd.h
  • HMAC_Processing() : stm32h7xx_hal_hash.c
  • HMAC_Start() : stm32h7xx_hal_hash.c
  • HMAC_Start_DMA() : stm32h7xx_hal_hash.c
  • HMAC_Start_IT() : stm32h7xx_hal_hash.c
  • HRIM_BURSTMODEPRELOAD_DISABLED : stm32h7xx_hal_hrtim.h
  • HRIM_BURSTMODEPRELOAD_ENABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGER_1 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGER_2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGER_3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGER_4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_EVENT_1 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_EVENT_2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_EVENT_3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_EVENT_4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_EVENT_5 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_EVENT_10 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_EVENT_6 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_EVENT_7 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_EVENT_8 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_EVENT_9 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGERUPDATE_MASTER : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGERUPDATE_TIMER_A : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGERUPDATE_TIMER_B : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGERUPDATE_TIMER_C : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGERUPDATE_TIMER_D : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGERUPDATE_TIMER_E : stm32h7xx_hal_hrtim.h
  • HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT : stm32h7xx_hal_hrtim.h
  • HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_AUTODELAYEDMODE_REGULAR : stm32h7xx_hal_hrtim.h
  • HRTIM_BASICOCMODE_ACTIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_BASICOCMODE_INACTIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_BASICOCMODE_TOGGLE : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_CHPR : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_CNT : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_CR : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_DIER : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_DTR : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_EEFR1 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_EEFR2 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_FLTR : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_ICR : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_OUTR : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_PER : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_REP : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_RST1R : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_RST2R : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_RSTR : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_SET1R : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_SET2R : stm32h7xx_hal_hrtim.h
  • HRTIM_BurstDMACplt() : stm32h7xx_hal_hrtim.c
  • HRTIM_BURSTMODE_CONTINOUS : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODE_SINGLESHOT : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECLOCKSOURCE_FHRTIM : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECLOCKSOURCE_MASTER : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECLOCKSOURCE_TIMER_A : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECLOCKSOURCE_TIMER_B : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECLOCKSOURCE_TIMER_C : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECLOCKSOURCE_TIMER_D : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECLOCKSOURCE_TIMER_E : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECTL_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECTL_ENABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV1 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV1024 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV128 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV16 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV16384 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV2 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV2048 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV256 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV32 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV32768 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV4 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV4096 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV512 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV64 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV8 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV8192 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODESTATUS_NORMAL : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODESTATUS_ONGOING : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_EVENT_7 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_EVENT_8 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_MASTER_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_MASTER_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_MASTER_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_MASTER_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_MASTER_REPETITION : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_MASTER_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERA_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERB_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERC_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERD_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERE_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_EEV_1 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_EEV_10 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_EEV_2 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_EEV_3 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_EEV_4 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_EEV_5 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_EEV_6 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_EEV_7 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_EEV_8 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_EEV_9 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TA1_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TA1_SET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TB1_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TB1_SET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TC1_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TC1_SET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TD1_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TD1_SET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TE1_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TE1_SET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TIMERA_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TIMERA_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TIMERB_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TIMERB_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TIMERC_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TIMERC_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TIMERD_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TIMERD_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TIMERE_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TIMERE_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_UPDATE : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTUREUNIT_1 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTUREUNIT_2 : stm32h7xx_hal_hrtim.h
  • HRTIM_CaptureUnitConfig() : stm32h7xx_hal_hrtim.c
  • HRTIM_CHOPPER_DUTYCYCLE_0 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_DUTYCYCLE_125 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_DUTYCYCLE_250 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_DUTYCYCLE_375 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_DUTYCYCLE_500 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_DUTYCYCLE_625 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_DUTYCYCLE_750 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_DUTYCYCLE_875 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PRESCALERRATIO_DIV112 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PRESCALERRATIO_DIV128 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PRESCALERRATIO_DIV144 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PRESCALERRATIO_DIV16 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PRESCALERRATIO_DIV160 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PRESCALERRATIO_DIV176 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PRESCALERRATIO_DIV192 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PRESCALERRATIO_DIV208 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PRESCALERRATIO_DIV224 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PRESCALERRATIO_DIV240 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PRESCALERRATIO_DIV256 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PRESCALERRATIO_DIV32 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PRESCALERRATIO_DIV48 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PRESCALERRATIO_DIV64 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PRESCALERRATIO_DIV80 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PRESCALERRATIO_DIV96 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PULSEWIDTH_112 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PULSEWIDTH_128 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PULSEWIDTH_144 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PULSEWIDTH_16 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PULSEWIDTH_160 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PULSEWIDTH_176 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PULSEWIDTH_192 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PULSEWIDTH_208 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PULSEWIDTH_224 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PULSEWIDTH_240 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PULSEWIDTH_256 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PULSEWIDTH_32 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PULSEWIDTH_48 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PULSEWIDTH_64 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PULSEWIDTH_80 : stm32h7xx_hal_hrtim.h
  • HRTIM_CHOPPER_PULSEWIDTH_96 : stm32h7xx_hal_hrtim.h
  • HRTIM_COMPAREUNIT_1 : stm32h7xx_hal_hrtim.h
  • HRTIM_COMPAREUNIT_2 : stm32h7xx_hal_hrtim.h
  • HRTIM_COMPAREUNIT_3 : stm32h7xx_hal_hrtim.h
  • HRTIM_COMPAREUNIT_4 : stm32h7xx_hal_hrtim.h
  • HRTIM_CompareUnitConfig() : stm32h7xx_hal_hrtim.c
  • HRTIM_DACSYNC_DACTRIGOUT_1 : stm32h7xx_hal_hrtim.h
  • HRTIM_DACSYNC_DACTRIGOUT_2 : stm32h7xx_hal_hrtim.h
  • HRTIM_DACSYNC_DACTRIGOUT_3 : stm32h7xx_hal_hrtim.h
  • HRTIM_DACSYNC_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_DMAError() : stm32h7xx_hal_hrtim.c
  • HRTIM_DMAMasterCplt() : stm32h7xx_hal_hrtim.c
  • HRTIM_DMATimerxCplt() : stm32h7xx_hal_hrtim.c
  • HRTIM_EVENT_1 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENT_10 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENT_2 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENT_3 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENT_4 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENT_5 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENT_6 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENT_7 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENT_8 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENT_9 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENT_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_EventConfig() : stm32h7xx_hal_hrtim.c
  • HRTIM_EVENTFASTMODE_DISABLE : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTFASTMODE_ENABLE : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTFILTER_1 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTFILTER_10 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTFILTER_11 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTFILTER_12 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTFILTER_13 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTFILTER_14 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTFILTER_15 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTFILTER_2 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTFILTER_3 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTFILTER_4 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTFILTER_5 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTFILTER_6 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTFILTER_7 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTFILTER_8 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTFILTER_9 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTFILTER_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTPOLARITY_HIGH : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTPOLARITY_LOW : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTPRESCALER_DIV1 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTPRESCALER_DIV2 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTPRESCALER_DIV4 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTPRESCALER_DIV8 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTSENSITIVITY_BOTHEDGES : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTSENSITIVITY_FALLINGEDGE : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTSENSITIVITY_LEVEL : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTSENSITIVITY_RISINGEDGE : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTSRC_1 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTSRC_2 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTSRC_3 : stm32h7xx_hal_hrtim.h
  • HRTIM_EVENTSRC_4 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULT_1 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULT_2 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULT_3 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULT_4 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULT_5 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTFILTER_1 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTFILTER_10 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTFILTER_11 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTFILTER_12 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTFILTER_13 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTFILTER_14 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTFILTER_15 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTFILTER_2 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTFILTER_3 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTFILTER_4 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTFILTER_5 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTFILTER_6 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTFILTER_7 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTFILTER_8 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTFILTER_9 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTFILTER_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTLOCK_READONLY : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTLOCK_READWRITE : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTMODECTL_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTMODECTL_ENABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTPOLARITY_HIGH : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTPOLARITY_LOW : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTPRESCALER_DIV1 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTPRESCALER_DIV2 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTPRESCALER_DIV4 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTPRESCALER_DIV8 : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTSOURCE_DIGITALINPUT : stm32h7xx_hal_hrtim.h
  • HRTIM_FAULTSOURCE_INTERNAL : stm32h7xx_hal_hrtim.h
  • HRTIM_FLAG_BMPER : stm32h7xx_hal_hrtim.h
  • HRTIM_FLAG_FLT1 : stm32h7xx_hal_hrtim.h
  • HRTIM_FLAG_FLT2 : stm32h7xx_hal_hrtim.h
  • HRTIM_FLAG_FLT3 : stm32h7xx_hal_hrtim.h
  • HRTIM_FLAG_FLT4 : stm32h7xx_hal_hrtim.h
  • HRTIM_FLAG_FLT5 : stm32h7xx_hal_hrtim.h
  • HRTIM_FLAG_SYSFLT : stm32h7xx_hal_hrtim.h
  • HRTIM_FLTR_FLTxEN : stm32h7xx_hal_hrtim.c
  • HRTIM_ForceRegistersUpdate() : stm32h7xx_hal_hrtim.c
  • HRTIM_GetDMAFromOCMode() : stm32h7xx_hal_hrtim.c
  • HRTIM_GetDMAHandleFromTimerIdx() : stm32h7xx_hal_hrtim.c
  • HRTIM_GetITFromOCMode() : stm32h7xx_hal_hrtim.c
  • HRTIM_HALFMODE_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_HALFMODE_ENABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_HandleTypeDef : stm32h7xx_hal_hrtim.h
  • HRTIM_HRTIM_ISR() : stm32h7xx_hal_hrtim.c
  • HRTIM_IT_BMPER : stm32h7xx_hal_hrtim.h
  • HRTIM_IT_FLT1 : stm32h7xx_hal_hrtim.h
  • HRTIM_IT_FLT2 : stm32h7xx_hal_hrtim.h
  • HRTIM_IT_FLT3 : stm32h7xx_hal_hrtim.h
  • HRTIM_IT_FLT4 : stm32h7xx_hal_hrtim.h
  • HRTIM_IT_FLT5 : stm32h7xx_hal_hrtim.h
  • HRTIM_IT_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_IT_SYSFLT : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_DMA_MCMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_DMA_MCMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_DMA_MCMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_DMA_MCMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_DMA_MREP : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_DMA_MUPD : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_DMA_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_DMA_SYNC : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_FLAG_MCMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_FLAG_MCMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_FLAG_MCMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_FLAG_MCMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_FLAG_MREP : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_FLAG_MUPD : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_FLAG_SYNC : stm32h7xx_hal_hrtim.h
  • HRTIM_Master_ISR() : stm32h7xx_hal_hrtim.c
  • HRTIM_MASTER_IT_MCMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_IT_MCMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_IT_MCMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_IT_MCMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_IT_MREP : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_IT_MUPD : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_IT_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_MASTER_IT_SYNC : stm32h7xx_hal_hrtim.h
  • HRTIM_MasterBase_Config() : stm32h7xx_hal_hrtim.c
  • HRTIM_MasterWaveform_Config() : stm32h7xx_hal_hrtim.c
  • HRTIM_MODE_CONTINUOUS : stm32h7xx_hal_hrtim.h
  • HRTIM_MODE_SINGLESHOT : stm32h7xx_hal_hrtim.h
  • HRTIM_MODE_SINGLESHOT_RETRIGGERABLE : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUT_TA1 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUT_TA2 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUT_TB1 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUT_TB2 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUT_TC1 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUT_TC2 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUT_TD1 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUT_TD2 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUT_TE1 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUT_TE2 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTBURSTMODEENTRY_DELAYED : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTBURSTMODEENTRY_REGULAR : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTCHOPPERMODE_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTCHOPPERMODE_ENABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_OutputConfig() : stm32h7xx_hal_hrtim.c
  • HRTIM_OUTPUTFAULTLEVEL_ACTIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTFAULTLEVEL_HIGHZ : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTFAULTLEVEL_INACTIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTFAULTLEVEL_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTIDLELEVEL_ACTIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTIDLELEVEL_INACTIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTIDLEMODE_IDLE : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTIDLEMODE_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTLEVEL_ACTIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTLEVEL_INACTIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTPOLARITY_HIGH : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTPOLARITY_LOW : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_EEV_1 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_EEV_10 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_EEV_2 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_EEV_3 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_EEV_4 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_EEV_5 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_EEV_6 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_EEV_7 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_EEV_8 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_EEV_9 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_MASTERCMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_MASTERCMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_MASTERCMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_MASTERCMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_MASTERPER : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_RESYNC : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_TIMCMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_TIMCMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_TIMCMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_TIMCMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_TIMEV_1 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_TIMEV_2 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_TIMEV_3 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_TIMEV_4 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_TIMEV_5 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_TIMEV_6 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_TIMEV_7 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_TIMEV_8 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_TIMEV_9 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_TIMPER : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTRESET_UPDATE : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_EEV_1 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_EEV_10 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_EEV_2 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_EEV_3 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_EEV_4 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_EEV_5 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_EEV_6 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_EEV_7 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_EEV_8 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_EEV_9 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_MASTERCMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_MASTERCMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_MASTERCMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_MASTERCMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_MASTERPER : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_RESYNC : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_TIMCMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_TIMCMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_TIMCMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_TIMCMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_TIMEV_1 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_TIMEV_2 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_TIMEV_3 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_TIMEV_4 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_TIMEV_5 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_TIMEV_6 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_TIMEV_7 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_TIMEV_8 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_TIMEV_9 : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_TIMPER : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSET_UPDATE : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSTATE_FAULT : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSTATE_IDLE : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSTATE_RUN : stm32h7xx_hal_hrtim.h
  • HRTIM_PRELOAD_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_PRELOAD_ENABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_PRESCALERRATIO_DIV1 : stm32h7xx_hal_hrtim.h
  • HRTIM_PRESCALERRATIO_DIV2 : stm32h7xx_hal_hrtim.h
  • HRTIM_PRESCALERRATIO_DIV4 : stm32h7xx_hal_hrtim.h
  • HRTIM_PRESCALERRATIO_MUL16 : stm32h7xx_hal_hrtim.h
  • HRTIM_PRESCALERRATIO_MUL2 : stm32h7xx_hal_hrtim.h
  • HRTIM_PRESCALERRATIO_MUL32 : stm32h7xx_hal_hrtim.h
  • HRTIM_PRESCALERRATIO_MUL4 : stm32h7xx_hal_hrtim.h
  • HRTIM_PRESCALERRATIO_MUL8 : stm32h7xx_hal_hrtim.h
  • HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 : stm32h7xx_hal_hrtim.h
  • HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 : stm32h7xx_hal_hrtim.h
  • HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 : stm32h7xx_hal_hrtim.h
  • HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCINPUTSOURCE_INTERNALEVENT : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCINPUTSOURCE_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCOPTION_MASTER : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCOPTION_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCOPTION_SLAVE : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCOUTPUTPOLARITY_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCOUTPUTPOLARITY_POSITIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCOUTPUTSOURCE_MASTER_START : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCOUTPUTSOURCE_TIMA_START : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCRESET_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCRESET_ENABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCSTART_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCSTART_ENABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_TAOEN_MASK : stm32h7xx_hal_hrtim.h
  • HRTIM_TBOEN_MASK : stm32h7xx_hal_hrtim.h
  • HRTIM_TCOEN_MASK : stm32h7xx_hal_hrtim.h
  • HRTIM_TDOEN_MASK : stm32h7xx_hal_hrtim.h
  • HRTIM_TEOEN_MASK : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_CPT1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_CPT2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_DLYPRT : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_REP : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_RST : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_RST1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_RST2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_SET1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_SET2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_UPD : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_CPT1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_CPT2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_DLYPRT : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_REP : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_RST : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_RST1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_RST2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_SET1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_SET2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_UPD : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_CPT1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_CPT2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_DLYPRT : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_REP : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_RST : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_RST1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_RST2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_SET1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_SET2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_UPD : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_ResetConfig() : stm32h7xx_hal_hrtim.c
  • HRTIM_TIMCR_TIMUPDATETRIGGER : stm32h7xx_hal_hrtim.c
  • HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_RISINGLOCK_READONLY : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_RISINGLOCK_WRITE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIMEINSERTION_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIMEINSERTION_ENABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_Timer_ISR() : stm32h7xx_hal_hrtim.c
  • HRTIM_TIMERBURSTMODE_MAINTAINCLOCK : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERBURSTMODE_RESETCOUNTER : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERID_MASTER : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERID_TIMER_A : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERID_TIMER_B : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERID_TIMER_C : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERID_TIMER_D : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERID_TIMER_E : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERINDEX_COMMON : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERINDEX_MASTER : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERINDEX_TIMER_A : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERINDEX_TIMER_B : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERINDEX_TIMER_C : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERINDEX_TIMER_D : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERINDEX_TIMER_E : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERRESET_MASTER : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERRESET_TIMER_A : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERRESET_TIMER_B : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERRESET_TIMER_C : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERRESET_TIMER_D : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERRESET_TIMER_E : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERUPDATE_A : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERUPDATE_B : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERUPDATE_C : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERUPDATE_D : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERUPDATE_E : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERUPDATE_MASTER : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGCMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGCMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGCMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGCMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_WINDOWINGTIM : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTLATCH_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTLATCH_ENABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMFAULTENABLE_FAULT1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMFAULTENABLE_FAULT2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMFAULTENABLE_FAULT3 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMFAULTENABLE_FAULT4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMFAULTENABLE_FAULT5 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMFAULTENABLE_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMFAULTLOCK_READONLY : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMFAULTLOCK_READWRITE : stm32h7xx_hal_hrtim.h
  • HRTIM_TimingUnitBase_Config() : stm32h7xx_hal_hrtim.c
  • HRTIM_TimingUnitWaveform_Config() : stm32h7xx_hal_hrtim.c
  • HRTIM_TIMPUSHPULLMODE_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMPUSHPULLMODE_ENABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_EEV_1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_EEV_10 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_EEV_2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_EEV_3 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_EEV_4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_EEV_5 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_EEV_6 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_EEV_7 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_EEV_8 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_EEV_9 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_MASTER_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_MASTER_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_MASTER_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_MASTER_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_MASTER_PER : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_UPDATE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMUPDATEONRESET_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMUPDATEONRESET_ENABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMUPDATETRIGGER_MASTER : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMUPDATETRIGGER_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMUPDATETRIGGER_TIMER_A : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMUPDATETRIGGER_TIMER_B : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMUPDATETRIGGER_TIMER_C : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMUPDATETRIGGER_TIMER_D : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMUPDATETRIGGER_TIMER_E : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEGATING_DMABURST : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEGATING_DMABURST_UPDATE : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEGATING_INDEPENDENT : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEGATING_UPDEN1 : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEGATING_UPDEN1_UPDATE : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEGATING_UPDEN2 : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEGATING_UPDEN2_UPDATE : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEGATING_UPDEN3 : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEGATING_UPDEN3_UPDATE : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEONREPETITION_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEONREPETITION_ENABLED : stm32h7xx_hal_hrtim.h
  • HSE_STARTUP_TIMEOUT : stm32h7xx_hal_conf.h
  • HSE_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • HSE_VALUE : stm32h7xx_hal_conf.h
  • HSI48_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • HSI_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • HSI_VALUE : stm32h7xx_hal_conf.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- i -

  • I2C_ADDRESSINGMODE_10BIT : stm32h7xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_7BIT : stm32h7xx_hal_i2c.h
  • I2C_ANALOGFILTER_DISABLE : stm32h7xx_hal_i2c_ex.h
  • I2C_ANALOGFILTER_ENABLE : stm32h7xx_hal_i2c_ex.h
  • I2C_AUTOEND_MODE : stm32h7xx_hal_i2c.h
  • I2C_DIRECTION_RECEIVE : stm32h7xx_hal_i2c.h
  • I2C_DIRECTION_TRANSMIT : stm32h7xx_hal_i2c.h
  • I2C_Disable_IRQ() : stm32h7xx_hal_i2c.c
  • I2C_DMAAbort() : stm32h7xx_hal_i2c.c
  • I2C_DMAError() : stm32h7xx_hal_i2c.c
  • I2C_DMAMasterReceiveCplt() : stm32h7xx_hal_i2c.c
  • I2C_DMAMasterTransmitCplt() : stm32h7xx_hal_i2c.c
  • I2C_DMASlaveReceiveCplt() : stm32h7xx_hal_i2c.c
  • I2C_DMASlaveTransmitCplt() : stm32h7xx_hal_i2c.c
  • I2C_DUALADDRESS_DISABLE : stm32h7xx_hal_i2c.h
  • I2C_DUALADDRESS_ENABLE : stm32h7xx_hal_i2c.h
  • I2C_Enable_IRQ() : stm32h7xx_hal_i2c.c
  • I2C_FASTMODEPLUS_I2C1 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C2 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C3 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C4 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB6 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB7 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB8 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB9 : stm32h7xx_hal_i2c_ex.h
  • I2C_FIRST_AND_LAST_FRAME : stm32h7xx_hal_i2c.h
  • I2C_FIRST_AND_NEXT_FRAME : stm32h7xx_hal_i2c.h
  • I2C_FIRST_FRAME : stm32h7xx_hal_i2c.h
  • I2C_FLAG_ADDR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_AF : stm32h7xx_hal_i2c.h
  • I2C_FLAG_ALERT : stm32h7xx_hal_i2c.h
  • I2C_FLAG_ARLO : stm32h7xx_hal_i2c.h
  • I2C_FLAG_BERR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_BUSY : stm32h7xx_hal_i2c.h
  • I2C_FLAG_DIR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_OVR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_PECERR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_RXNE : stm32h7xx_hal_i2c.h
  • I2C_FLAG_STOPF : stm32h7xx_hal_i2c.h
  • I2C_FLAG_TC : stm32h7xx_hal_i2c.h
  • I2C_FLAG_TCR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_TIMEOUT : stm32h7xx_hal_i2c.h
  • I2C_FLAG_TXE : stm32h7xx_hal_i2c.h
  • I2C_FLAG_TXIS : stm32h7xx_hal_i2c.h
  • I2C_Flush_TXDR() : stm32h7xx_hal_i2c.c
  • I2C_GENERALCALL_DISABLE : stm32h7xx_hal_i2c.h
  • I2C_GENERALCALL_ENABLE : stm32h7xx_hal_i2c.h
  • I2C_GENERATE_START : stm32h7xx_hal_i2c.h
  • I2C_GENERATE_START_READ : stm32h7xx_hal_i2c.h
  • I2C_GENERATE_START_WRITE : stm32h7xx_hal_i2c.h
  • I2C_GENERATE_STOP : stm32h7xx_hal_i2c.h
  • I2C_GET_ADDR_MATCH : stm32h7xx_hal_i2c.h
  • I2C_GET_DIR : stm32h7xx_hal_i2c.h
  • I2C_GET_DMA_REMAIN_DATA : stm32h7xx_hal_i2c.c
  • I2C_GET_OWN_ADDRESS1 : stm32h7xx_hal_i2c.h
  • I2C_GET_OWN_ADDRESS2 : stm32h7xx_hal_i2c.h
  • I2C_GET_STOP_MODE : stm32h7xx_hal_i2c.h
  • I2C_HandleTypeDef : stm32h7xx_hal_i2c.h
  • I2C_IsAcknowledgeFailed() : stm32h7xx_hal_i2c.c
  • I2C_IT_ADDRI : stm32h7xx_hal_i2c.h
  • I2C_IT_ERRI : stm32h7xx_hal_i2c.h
  • I2C_IT_NACKI : stm32h7xx_hal_i2c.h
  • I2C_IT_RXI : stm32h7xx_hal_i2c.h
  • I2C_IT_STOPI : stm32h7xx_hal_i2c.h
  • I2C_IT_TCI : stm32h7xx_hal_i2c.h
  • I2C_IT_TXI : stm32h7xx_hal_i2c.h
  • I2C_ITAddrCplt() : stm32h7xx_hal_i2c.c
  • I2C_ITError() : stm32h7xx_hal_i2c.c
  • I2C_ITListenCplt() : stm32h7xx_hal_i2c.c
  • I2C_ITMasterCplt() : stm32h7xx_hal_i2c.c
  • I2C_ITMasterSequentialCplt() : stm32h7xx_hal_i2c.c
  • I2C_ITSlaveCplt() : stm32h7xx_hal_i2c.c
  • I2C_ITSlaveSequentialCplt() : stm32h7xx_hal_i2c.c
  • I2C_LAST_FRAME : stm32h7xx_hal_i2c.h
  • I2C_Master_ISR_DMA() : stm32h7xx_hal_i2c.c
  • I2C_Master_ISR_IT() : stm32h7xx_hal_i2c.c
  • I2C_MEM_ADD_LSB : stm32h7xx_hal_i2c.h
  • I2C_MEM_ADD_MSB : stm32h7xx_hal_i2c.h
  • I2C_MEMADD_SIZE_16BIT : stm32h7xx_hal_i2c.h
  • I2C_MEMADD_SIZE_8BIT : stm32h7xx_hal_i2c.h
  • I2C_NEXT_FRAME : stm32h7xx_hal_i2c.h
  • I2C_NO_OPTION_FRAME : stm32h7xx_hal_i2c.h
  • I2C_NO_STARTSTOP : stm32h7xx_hal_i2c.h
  • I2C_NOSTRETCH_DISABLE : stm32h7xx_hal_i2c.h
  • I2C_NOSTRETCH_ENABLE : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK01 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK02 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK03 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK04 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK05 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK06 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK07 : stm32h7xx_hal_i2c.h
  • I2C_OA2_NOMASK : stm32h7xx_hal_i2c.h
  • I2C_RELOAD_MODE : stm32h7xx_hal_i2c.h
  • I2C_RequestMemoryRead() : stm32h7xx_hal_i2c.c
  • I2C_RequestMemoryWrite() : stm32h7xx_hal_i2c.c
  • I2C_RESET_CR2 : stm32h7xx_hal_i2c.h
  • I2C_Slave_ISR_DMA() : stm32h7xx_hal_i2c.c
  • I2C_Slave_ISR_IT() : stm32h7xx_hal_i2c.c
  • I2C_SOFTEND_MODE : stm32h7xx_hal_i2c.h
  • I2C_STATE_MASTER_BUSY_RX : stm32h7xx_hal_i2c.c
  • I2C_STATE_MASTER_BUSY_TX : stm32h7xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_RX : stm32h7xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_TX : stm32h7xx_hal_i2c.c
  • I2C_STATE_MSK : stm32h7xx_hal_i2c.c
  • I2C_STATE_NONE : stm32h7xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_RX : stm32h7xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_TX : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_ADDR : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_BUSY : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_DIR : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_FLAG : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_RXNE : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_STOPF : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_TC : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_TCR : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_TXIS : stm32h7xx_hal_i2c.c
  • I2C_TransferConfig() : stm32h7xx_hal_i2c.c
  • I2C_WaitOnFlagUntilTimeout() : stm32h7xx_hal_i2c.c
  • I2C_WaitOnRXNEFlagUntilTimeout() : stm32h7xx_hal_i2c.c
  • I2C_WaitOnSTOPFlagUntilTimeout() : stm32h7xx_hal_i2c.c
  • I2C_WaitOnTXISFlagUntilTimeout() : stm32h7xx_hal_i2c.c
  • I2C_XFER_CPLT_IT : stm32h7xx_hal_i2c.c
  • I2C_XFER_ERROR_IT : stm32h7xx_hal_i2c.c
  • I2C_XFER_LISTEN_IT : stm32h7xx_hal_i2c.c
  • I2C_XFER_RELOAD_IT : stm32h7xx_hal_i2c.c
  • I2C_XFER_RX_IT : stm32h7xx_hal_i2c.c
  • I2C_XFER_TX_IT : stm32h7xx_hal_i2c.c
  • I2S_AUDIOFREQ_11K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_16K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_192K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_22K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_32K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_44K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_48K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_8K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_96K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_DEFAULT : stm32h7xx_hal_i2s.h
  • I2S_CloseRx_ISR() : stm32h7xx_hal_i2s.c
  • I2S_CloseTx_ISR() : stm32h7xx_hal_i2s.c
  • I2S_CPOL_HIGH : stm32h7xx_hal_i2s.h
  • I2S_CPOL_LOW : stm32h7xx_hal_i2s.h
  • I2S_DATA_24BIT_ALIGNMENT_LEFT : stm32h7xx_hal_i2s.h
  • I2S_DATA_24BIT_ALIGNMENT_RIGHT : stm32h7xx_hal_i2s.h
  • I2S_DATAFORMAT_16B : stm32h7xx_hal_i2s.h
  • I2S_DATAFORMAT_16B_EXTENDED : stm32h7xx_hal_i2s.h
  • I2S_DATAFORMAT_24B : stm32h7xx_hal_i2s.h
  • I2S_DATAFORMAT_32B : stm32h7xx_hal_i2s.h
  • I2S_DMAError() : stm32h7xx_hal_i2s.c
  • I2S_DMARxCplt() : stm32h7xx_hal_i2s.c
  • I2S_DMARxHalfCplt() : stm32h7xx_hal_i2s.c
  • I2S_DMATxCplt() : stm32h7xx_hal_i2s.c
  • I2S_DMATxHalfCplt() : stm32h7xx_hal_i2s.c
  • I2S_FIFO_THRESHOLD_01DATA : stm32h7xx_hal_i2s.h
  • I2S_FIFO_THRESHOLD_02DATA : stm32h7xx_hal_i2s.h
  • I2S_FIFO_THRESHOLD_03DATA : stm32h7xx_hal_i2s.h
  • I2S_FIFO_THRESHOLD_04DATA : stm32h7xx_hal_i2s.h
  • I2S_FIFO_THRESHOLD_05DATA : stm32h7xx_hal_i2s.h
  • I2S_FIFO_THRESHOLD_06DATA : stm32h7xx_hal_i2s.h
  • I2S_FIFO_THRESHOLD_07DATA : stm32h7xx_hal_i2s.h
  • I2S_FIFO_THRESHOLD_08DATA : stm32h7xx_hal_i2s.h
  • I2S_FIRSTBIT_LSB : stm32h7xx_hal_i2s.h
  • I2S_FIRSTBIT_MSB : stm32h7xx_hal_i2s.h
  • I2S_FLAG_FRE : stm32h7xx_hal_i2s.h
  • I2S_FLAG_OVR : stm32h7xx_hal_i2s.h
  • I2S_FLAG_RXNE : stm32h7xx_hal_i2s.h
  • I2S_FLAG_RXWNE : stm32h7xx_hal_i2s.h
  • I2S_FLAG_TXE : stm32h7xx_hal_i2s.h
  • I2S_FLAG_UDR : stm32h7xx_hal_i2s.h
  • I2S_HandleTypeDef : stm32h7xx_hal_i2s.h
  • I2S_IO_SWAP_DISABLE : stm32h7xx_hal_i2s.h
  • I2S_IO_SWAP_ENABLE : stm32h7xx_hal_i2s.h
  • I2S_IT_ERR : stm32h7xx_hal_i2s.h
  • I2S_IT_RXNE : stm32h7xx_hal_i2s.h
  • I2S_IT_TXE : stm32h7xx_hal_i2s.h
  • I2S_MASTER_KEEP_IO_STATE_DISABLE : stm32h7xx_hal_i2s.h
  • I2S_MASTER_KEEP_IO_STATE_ENABLE : stm32h7xx_hal_i2s.h
  • I2S_MCLKOUTPUT_DISABLE : stm32h7xx_hal_i2s.h
  • I2S_MCLKOUTPUT_ENABLE : stm32h7xx_hal_i2s.h
  • I2S_MODE_MASTER_FD : stm32h7xx_hal_i2s.h
  • I2S_MODE_MASTER_RX : stm32h7xx_hal_i2s.h
  • I2S_MODE_MASTER_TX : stm32h7xx_hal_i2s.h
  • I2S_MODE_SLAVE_FD : stm32h7xx_hal_i2s.h
  • I2S_MODE_SLAVE_RX : stm32h7xx_hal_i2s.h
  • I2S_MODE_SLAVE_TX : stm32h7xx_hal_i2s.h
  • I2S_RxISR_16BIT() : stm32h7xx_hal_i2s.c
  • I2S_RxISR_32BIT() : stm32h7xx_hal_i2s.c
  • I2S_SLAVE_EXTEND_FRE_DETECTION_DISABLE : stm32h7xx_hal_i2s.h
  • I2S_SLAVE_EXTEND_FRE_DETECTION_ENABLE : stm32h7xx_hal_i2s.h
  • I2S_STANDARD_LSB : stm32h7xx_hal_i2s.h
  • I2S_STANDARD_MSB : stm32h7xx_hal_i2s.h
  • I2S_STANDARD_PCM_LONG : stm32h7xx_hal_i2s.h
  • I2S_STANDARD_PCM_SHORT : stm32h7xx_hal_i2s.h
  • I2S_STANDARD_PHILIPS : stm32h7xx_hal_i2s.h
  • I2S_TxISR_16BIT() : stm32h7xx_hal_i2s.c
  • I2S_TxISR_32BIT() : stm32h7xx_hal_i2s.c
  • I2S_USE_I2S : stm32h7xx_hal_i2s_ex.c
  • I2S_USE_I2SEXT : stm32h7xx_hal_i2s_ex.c
  • I2S_UseTypeDef : stm32h7xx_hal_i2s_ex.c
  • I2S_WaitFlagStateUntilTimeout() : stm32h7xx_hal_i2s.c
  • I2S_WS_INVERSION_DISABLE : stm32h7xx_hal_i2s.h
  • I2S_WS_INVERSION_ENABLE : stm32h7xx_hal_i2s.h
  • I2SEx_2linesRxISR_16BIT() : stm32h7xx_hal_i2s_ex.c
  • I2SEx_2linesRxISR_32BIT() : stm32h7xx_hal_i2s_ex.c
  • I2SEx_2linesTxISR_16BIT() : stm32h7xx_hal_i2s_ex.c
  • I2SEx_2linesTxISR_32BIT() : stm32h7xx_hal_i2s_ex.c
  • I2SEx_CloseRxTx_ISR() : stm32h7xx_hal_i2s_ex.c
  • I2SEx_DMATxRxCplt() : stm32h7xx_hal_i2s_ex.c
  • I2SEx_DMATxRxHalfCplt() : stm32h7xx_hal_i2s_ex.c
  • I2SEx_TxRxDMAError() : stm32h7xx_hal_i2s_ex.c
  • I2SEx_WaitFlagStateUntilTimeout() : stm32h7xx_hal_i2s_ex.c
  • IDCODE_DEVID_MASK : stm32h7xx_hal.c
  • INCR_RX_DESC_INDEX : stm32h7xx_hal_eth.c
  • INCR_TX_DESC_INDEX : stm32h7xx_hal_eth.c
  • IRDA_AUTOBAUD_REQUEST : stm32h7xx_hal_irda.h
  • IRDA_BAUDRATE : stm32h7xx_hal_irda.h
  • IRDA_CheckIdleState() : stm32h7xx_hal_irda.c
  • IRDA_CLEAR_FEF : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_IDLEF : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_NEF : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_OREF : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_PEF : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_TCF : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_CSI : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_D2PCLK1 : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_D2PCLK2 : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_D3PCLK1 : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_HSI : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_LSE : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PLL2Q : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PLL3Q : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_UNDEFINED : stm32h7xx_hal_irda.h
  • IRDA_ClockSourceTypeDef : stm32h7xx_hal_irda.h
  • IRDA_ControlTypeDef : stm32h7xx_hal_irda.h
  • IRDA_CR1_FIELDS : stm32h7xx_hal_irda.c
  • IRDA_DMA_RX_DISABLE : stm32h7xx_hal_irda.h
  • IRDA_DMA_RX_ENABLE : stm32h7xx_hal_irda.h
  • IRDA_DMA_TX_DISABLE : stm32h7xx_hal_irda.h
  • IRDA_DMA_TX_ENABLE : stm32h7xx_hal_irda.h
  • IRDA_DMAAbortOnError() : stm32h7xx_hal_irda.c
  • IRDA_DMAError() : stm32h7xx_hal_irda.c
  • IRDA_DMAReceiveCplt() : stm32h7xx_hal_irda.c
  • IRDA_DMAReceiveHalfCplt() : stm32h7xx_hal_irda.c
  • IRDA_DMARxAbortCallback() : stm32h7xx_hal_irda.c
  • IRDA_DMARxOnlyAbortCallback() : stm32h7xx_hal_irda.c
  • IRDA_DMATransmitCplt() : stm32h7xx_hal_irda.c
  • IRDA_DMATransmitHalfCplt() : stm32h7xx_hal_irda.c
  • IRDA_DMATxAbortCallback() : stm32h7xx_hal_irda.c
  • IRDA_DMATxOnlyAbortCallback() : stm32h7xx_hal_irda.c
  • IRDA_EndRxTransfer() : stm32h7xx_hal_irda.c
  • IRDA_EndTransmit_IT() : stm32h7xx_hal_irda.c
  • IRDA_EndTxTransfer() : stm32h7xx_hal_irda.c
  • IRDA_FLAG_ABRE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_ABRF : stm32h7xx_hal_irda.h
  • IRDA_FLAG_BUSY : stm32h7xx_hal_irda.h
  • IRDA_FLAG_FE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_NE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_ORE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_PE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_REACK : stm32h7xx_hal_irda.h
  • IRDA_FLAG_RXNE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_TC : stm32h7xx_hal_irda.h
  • IRDA_FLAG_TEACK : stm32h7xx_hal_irda.h
  • IRDA_FLAG_TXE : stm32h7xx_hal_irda.h
  • IRDA_GETCLOCKSOURCE : stm32h7xx_hal_irda_ex.h
  • IRDA_IT_ERR : stm32h7xx_hal_irda.h
  • IRDA_IT_FE : stm32h7xx_hal_irda.h
  • IRDA_IT_IDLE : stm32h7xx_hal_irda.h
  • IRDA_IT_MASK : stm32h7xx_hal_irda.h
  • IRDA_IT_NE : stm32h7xx_hal_irda.h
  • IRDA_IT_ORE : stm32h7xx_hal_irda.h
  • IRDA_IT_PE : stm32h7xx_hal_irda.h
  • IRDA_IT_RXNE : stm32h7xx_hal_irda.h
  • IRDA_IT_TC : stm32h7xx_hal_irda.h
  • IRDA_IT_TXE : stm32h7xx_hal_irda.h
  • IRDA_MASK_COMPUTATION : stm32h7xx_hal_irda.h
  • IRDA_MODE : stm32h7xx_hal_irda.h
  • IRDA_MODE_DISABLE : stm32h7xx_hal_irda.h
  • IRDA_MODE_ENABLE : stm32h7xx_hal_irda.h
  • IRDA_MODE_RX : stm32h7xx_hal_irda.h
  • IRDA_MODE_TX : stm32h7xx_hal_irda.h
  • IRDA_MODE_TX_RX : stm32h7xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_irda.h
  • IRDA_PARITY : stm32h7xx_hal_irda.h
  • IRDA_PARITY_EVEN : stm32h7xx_hal_irda.h
  • IRDA_PARITY_NONE : stm32h7xx_hal_irda.h
  • IRDA_PARITY_ODD : stm32h7xx_hal_irda.h
  • IRDA_POWERMODE : stm32h7xx_hal_irda.h
  • IRDA_POWERMODE_LOWPOWER : stm32h7xx_hal_irda.h
  • IRDA_POWERMODE_NORMAL : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER : stm32h7xx_hal_irda.h
  • IRDA_Receive_IT() : stm32h7xx_hal_irda.c
  • IRDA_RXDATA_FLUSH_REQUEST : stm32h7xx_hal_irda.h
  • IRDA_SetConfig() : stm32h7xx_hal_irda.c
  • IRDA_STATE_DISABLE : stm32h7xx_hal_irda.h
  • IRDA_STATE_ENABLE : stm32h7xx_hal_irda.h
  • IRDA_TEACK_REACK_TIMEOUT : stm32h7xx_hal_irda.c
  • IRDA_Transmit_IT() : stm32h7xx_hal_irda.c
  • IRDA_TXDATA_FLUSH_REQUEST : stm32h7xx_hal_irda.h
  • IRDA_WaitOnFlagUntilTimeout() : stm32h7xx_hal_irda.c
  • IRDA_WORDLENGTH : stm32h7xx_hal_irda.h
  • IRDA_WORDLENGTH_7B : stm32h7xx_hal_irda.h
  • IRDA_WORDLENGTH_8B : stm32h7xx_hal_irda.h
  • IRDA_WORDLENGTH_9B : stm32h7xx_hal_irda.h
  • IS_ADC1_DIFF_CHANNEL : stm32h7xx_hal_adc_ex.h
  • IS_ADC2_DIFF_CHANNEL : stm32h7xx_hal_adc_ex.h
  • IS_ADC3_DIFF_CHANNEL : stm32h7xx_hal_adc_ex.h
  • IS_ADC_ANALOG_WATCHDOG_MODE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_ANALOG_WATCHDOG_NUMBER : stm32h7xx_hal_adc_ex.h
  • IS_ADC_CALFACT : stm32h7xx_hal_adc_ex.h
  • IS_ADC_CHANNEL : stm32h7xx_hal_adc_ex.h
  • IS_ADC_CLOCKPRESCALER : stm32h7xx_hal_adc.h
  • IS_ADC_CONVERSION_GROUP : stm32h7xx_hal_adc_ex.h
  • IS_ADC_CONVERSIONDATAMGT : stm32h7xx_hal_adc.h
  • IS_ADC_DUAL_DATA_MODE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_EOC_SELECTION : stm32h7xx_hal_adc.h
  • IS_ADC_EVENT_TYPE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_EXTTRIG : stm32h7xx_hal_adc.h
  • IS_ADC_EXTTRIG_EDGE : stm32h7xx_hal_adc.h
  • IS_ADC_EXTTRIGINJEC : stm32h7xx_hal_adc_ex.h
  • IS_ADC_EXTTRIGINJEC_EDGE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_INJECTED_NB_CONV : stm32h7xx_hal_adc_ex.h
  • IS_ADC_INJECTED_RANK : stm32h7xx_hal_adc_ex.h
  • IS_ADC_LEFT_BIT_SHIFT : stm32h7xx_hal_adc_ex.h
  • IS_ADC_MODE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_OFFSET_NUMBER : stm32h7xx_hal_adc_ex.h
  • IS_ADC_OVERRUN : stm32h7xx_hal_adc.h
  • IS_ADC_OVERSAMPLING_RATIO : stm32h7xx_hal_adc_ex.h
  • IS_ADC_RANGE : stm32h7xx_hal_adc.h
  • IS_ADC_REGOVERSAMPLING_MODE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_REGULAR_DISCONT_NUMBER : stm32h7xx_hal_adc.h
  • IS_ADC_REGULAR_NB_CONV : stm32h7xx_hal_adc.h
  • IS_ADC_REGULAR_RANK : stm32h7xx_hal_adc.h
  • IS_ADC_RESOLUTION : stm32h7xx_hal_adc.h
  • IS_ADC_RESOLUTION_8_BITS : stm32h7xx_hal_adc.h
  • IS_ADC_RIGHT_BIT_SHIFT : stm32h7xx_hal_adc_ex.h
  • IS_ADC_SAMPLE_TIME : stm32h7xx_hal_adc.h
  • IS_ADC_SAMPLING_DELAY : stm32h7xx_hal_adc_ex.h
  • IS_ADC_SCAN_MODE : stm32h7xx_hal_adc.h , stm32h7xx_hal_adc_ex.h
  • IS_ADC_SINGLE_DIFFERENTIAL : stm32h7xx_hal_adc_ex.h
  • IS_ADC_TRIGGERED_OVERSAMPLING_MODE : stm32h7xx_hal_adc_ex.h
  • IS_BDMA_D3_REQUEST : stm32h7xx_hal_dma.h
  • IS_BOOT_ADDRESS : stm32h7xx_hal_flash.h
  • IS_CEC_ADDRESS : stm32h7xx_hal_cec.h
  • IS_CEC_BREERRORBITGEN : stm32h7xx_hal_cec.h
  • IS_CEC_BRERXSTOP : stm32h7xx_hal_cec.h
  • IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION : stm32h7xx_hal_cec.h
  • IS_CEC_LBPEERRORBITGEN : stm32h7xx_hal_cec.h
  • IS_CEC_LISTENING_MODE : stm32h7xx_hal_cec.h
  • IS_CEC_MSGSIZE : stm32h7xx_hal_cec.h
  • IS_CEC_OWN_ADDRESS : stm32h7xx_hal_cec.h
  • IS_CEC_SFTOP : stm32h7xx_hal_cec.h
  • IS_CEC_SIGNALFREETIME : stm32h7xx_hal_cec.h
  • IS_CEC_TOLERANCE : stm32h7xx_hal_cec.h
  • IS_CHANNEL_STATUS_MASK : stm32h7xx_hal_spdifrx.h
  • IS_COMP_BLANKINGSRCE : stm32h7xx_hal_comp.h
  • IS_COMP_HYSTERESIS : stm32h7xx_hal_comp.h
  • IS_COMP_INPUT_MINUS : stm32h7xx_hal_comp.h
  • IS_COMP_INPUT_PLUS : stm32h7xx_hal_comp.h
  • IS_COMP_OUTPUT_LEVEL : stm32h7xx_hal_comp.h
  • IS_COMP_OUTPUTPOL : stm32h7xx_hal_comp.h
  • IS_COMP_POWERMODE : stm32h7xx_hal_comp.h
  • IS_COMP_TRIGGERMODE : stm32h7xx_hal_comp.h
  • IS_COMP_WINDOWMODE : stm32h7xx_hal_comp.h
  • IS_CRC_INPUTDATA_FORMAT : stm32h7xx_hal_crc.h
  • IS_CRC_INPUTDATA_INVERSION_MODE : stm32h7xx_hal_crc_ex.h
  • IS_CRC_OUTPUTDATA_INVERSION_MODE : stm32h7xx_hal_crc_ex.h
  • IS_CRC_POL_LENGTH : stm32h7xx_hal_crc.h
  • IS_CRYP_ALGORITHM : stm32h7xx_hal_cryp.h
  • IS_CRYP_DATATYPE : stm32h7xx_hal_cryp.h
  • IS_CRYP_KEYSIZE : stm32h7xx_hal_cryp.h
  • IS_D2_DMA_INSTANCE : stm32h7xx_hal_dma.h
  • IS_D2_DMAMUX_REQUEST_GEN_SIGNAL_ID : stm32h7xx_hal_dma_ex.h
  • IS_D2_DMAMUX_SYNC_SIGNAL_ID : stm32h7xx_hal_dma_ex.h
  • IS_D3_DMA_INSTANCE : stm32h7xx_hal_dma.h
  • IS_D3_DMAMUX_REQUEST_GEN_SIGNAL_ID : stm32h7xx_hal_dma_ex.h
  • IS_D3_DMAMUX_SYNC_SIGNAL_ID : stm32h7xx_hal_dma_ex.h
  • IS_D3_STATE : stm32h7xx_hal_pwr_ex.h
  • IS_DAC_ALIGN : stm32h7xx_hal_dac.h
  • IS_DAC_CHANNEL : stm32h7xx_hal_dac.h
  • IS_DAC_CHIP_CONNECTION : stm32h7xx_hal_dac_ex.h
  • IS_DAC_DATA : stm32h7xx_hal_dac.h
  • IS_DAC_HOLDTIME : stm32h7xx_hal_dac_ex.h
  • IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE : stm32h7xx_hal_dac_ex.h
  • IS_DAC_NEWTRIMMINGVALUE : stm32h7xx_hal_dac_ex.h
  • IS_DAC_OUTPUT_BUFFER_STATE : stm32h7xx_hal_dac.h
  • IS_DAC_REFRESHTIME : stm32h7xx_hal_dac.h
  • IS_DAC_SAMPLEANDHOLD : stm32h7xx_hal_dac_ex.h
  • IS_DAC_SAMPLETIME : stm32h7xx_hal_dac_ex.h
  • IS_DAC_TRIGGER : stm32h7xx_hal_dac_ex.h
  • IS_DAC_TRIMMING : stm32h7xx_hal_dac_ex.h
  • IS_DAC_TRIMMINGVALUE : stm32h7xx_hal_dac_ex.h
  • IS_DCMI_BYTE_SELECT_MODE : stm32h7xx_hal_dcmi.h
  • IS_DCMI_BYTE_SELECT_START : stm32h7xx_hal_dcmi.h
  • IS_DCMI_CAPTURE_MODE : stm32h7xx_hal_dcmi.h
  • IS_DCMI_CAPTURE_RATE : stm32h7xx_hal_dcmi.h
  • IS_DCMI_EXTENDED_DATA : stm32h7xx_hal_dcmi.h
  • IS_DCMI_HSPOLARITY : stm32h7xx_hal_dcmi.h
  • IS_DCMI_LINE_SELECT_MODE : stm32h7xx_hal_dcmi.h
  • IS_DCMI_LINE_SELECT_START : stm32h7xx_hal_dcmi.h
  • IS_DCMI_MODE_JPEG : stm32h7xx_hal_dcmi.h
  • IS_DCMI_PCKPOLARITY : stm32h7xx_hal_dcmi.h
  • IS_DCMI_SYNCHRO : stm32h7xx_hal_dcmi.h
  • IS_DCMI_VSPOLARITY : stm32h7xx_hal_dcmi.h
  • IS_DCMI_WINDOW_COORDINATE : stm32h7xx_hal_dcmi.h
  • IS_DCMI_WINDOW_HEIGHT : stm32h7xx_hal_dcmi.h
  • IS_DEFAULT_INIT_VALUE : stm32h7xx_hal_crc.h
  • IS_DEFAULT_POLYNOMIAL : stm32h7xx_hal_crc.h
  • IS_DFSDM_BREAK_SIGNALS : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_DATA_PACKING : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_FILTER_ORDER : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_FILTER_OVS_RATIO : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_INPUT : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_INPUT_PINS : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_OFFSET : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_OUTPUT_CLOCK : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_SCD_THRESHOLD : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_SPI_CLOCK : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CONTINUOUS_MODE : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_AWD_DATA_SOURCE : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_AWD_THRESHOLD : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_EXT_TRIG : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_EXT_TRIG_EDGE : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_INJ_TRIGGER : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_OVS_RATIO : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_REG_TRIGGER : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_SINC_ORDER : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_INJECTED_CHANNEL : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_REGULAR_CHANNEL : stm32h7xx_hal_dfsdm.h
  • IS_DMA2D_ALPHA_INVERTED : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_ALPHA_MODE : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_CHROMA_SUB_SAMPLING : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_CLUT_CM : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_CLUT_SIZE : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_CMODE : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_COLOR : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_GET_FLAG : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_INPUT_COLOR_MODE : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_IT : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_LAYER : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_LINE : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_LINEWATERMARK : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_MODE : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_OFFSET : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_PIXEL : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_RB_SWAP : stm32h7xx_hal_dma2d.h
  • IS_DMA_BUFFER_SIZE : stm32h7xx_hal_dma.h
  • IS_DMA_D2_REQUEST : stm32h7xx_hal_dma.h
  • IS_DMA_DIRECTION : stm32h7xx_hal_dma.h
  • IS_DMA_FIFO_MODE_STATE : stm32h7xx_hal_dma.h
  • IS_DMA_FIFO_THRESHOLD : stm32h7xx_hal_dma.h
  • IS_DMA_MEMORY_BURST : stm32h7xx_hal_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32h7xx_hal_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32h7xx_hal_dma.h
  • IS_DMA_MODE : stm32h7xx_hal_dma.h
  • IS_DMA_PERIPHERAL_BURST : stm32h7xx_hal_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32h7xx_hal_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32h7xx_hal_dma.h
  • IS_DMA_PRIORITY : stm32h7xx_hal_dma.h
  • IS_DMAMUX_REQUEST_GEN_POLARITY : stm32h7xx_hal_dma_ex.h
  • IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER : stm32h7xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_EVENT : stm32h7xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_POLARITY : stm32h7xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_REQUEST_NUMBER : stm32h7xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_STATE : stm32h7xx_hal_dma_ex.h
  • IS_EXTI_ALL_LINE : stm32h7xx_hal.h
  • IS_EXTI_CONFIG_LINE : stm32h7xx_hal.h
  • IS_EXTI_D1_LINE : stm32h7xx_hal.h
  • IS_EXTI_D3_CLEAR : stm32h7xx_hal.h
  • IS_EXTI_D3_LINE : stm32h7xx_hal.h
  • IS_EXTI_EDGE_LINE : stm32h7xx_hal.h
  • IS_EXTI_MODE_LINE : stm32h7xx_hal.h
  • IS_FDCAN_BRS : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_CALIBRATION_FIELD_LENGTH : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_CKDIV : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DATA_PRESCALER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DATA_SIZE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DATA_SJW : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DATA_TSEG1 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DATA_TSEG2 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DLC : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_EFC : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_ESI : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_EXT_FILTER_TYPE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_FDF : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_FIFO_WATERMARK : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_FILTER_CFG : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_FRAME_FORMAT : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_FRAME_TYPE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_ID_TYPE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_IT : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_IT_LINE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_MAX_VALUE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_MIN_VALUE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_MODE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_PRESCALER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_SJW : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_TSEG1 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_TSEG2 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_NON_MATCHING : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_OPERATION_MODE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_RX_FIFO : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_RX_FIFO_MODE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_STD_FILTER_TYPE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TIMEOUT : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TIMESTAMP : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TIMESTAMP_PRESCALER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_AUTO_CLK_CALIBRATION : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_BASIC_CYCLES_NUMBER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_CYCLE_START_SYNC : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_EVENT_TRIGGER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_EVENT_TRIGGER_POLARITY : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_EXTERNAL_CLK_SYNC : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_GLOBAL_TIME_FILTERING : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_IT : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_OPERATION : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_REPEAT_FACTOR : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_STOP_WATCH_POLARITY : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_STOP_WATCH_SOURCE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_STOP_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TIME_MASTER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TIME_PRESET : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TM_EVENT_EXTERNAL : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TM_EVENT_INTERNAL : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TRIGGER_TYPE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TUR_DENOMINATOR : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TUR_LEVEL_0_2 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TUR_LEVEL_1 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TUR_NUMERATOR : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TX_ENABLE_WINDOW : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TX_FIFO_QUEUE_MODE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TX_LOCATION : stm32h7xx_hal_fdcan.h
  • IS_FLASH_ADDRESS : stm32h7xx_hal_flash_ex.h
  • IS_FLASH_BANK : stm32h7xx_hal_flash.h , stm32h7xx_hal_flash_ex.h
  • IS_FLASH_BANK_EXCLUSIVE : stm32h7xx_hal_flash.h
  • IS_FLASH_FLAG_BANK1 : stm32h7xx_hal_flash.h
  • IS_FLASH_FLAG_BANK2 : stm32h7xx_hal_flash.h
  • IS_FLASH_IT_BANK1 : stm32h7xx_hal_flash.h
  • IS_FLASH_IT_BANK2 : stm32h7xx_hal_flash.h
  • IS_FLASH_LATENCY : stm32h7xx_hal_flash_ex.h
  • IS_FLASH_NBSECTORS : stm32h7xx_hal_flash_ex.h
  • IS_FLASH_PROGRAM_ADDRESS : stm32h7xx_hal_flash.h
  • IS_FLASH_PROGRAM_ADDRESS_BANK1 : stm32h7xx_hal_flash.h
  • IS_FLASH_PROGRAM_ADDRESS_BANK2 : stm32h7xx_hal_flash.h
  • IS_FLASH_SECTOR : stm32h7xx_hal_flash_ex.h
  • IS_FLASH_TYPEERASE : stm32h7xx_hal_flash_ex.h
  • IS_FLASH_TYPEPROGRAM : stm32h7xx_hal_flash.h
  • IS_FMC_SWAPBMAP_MODE : stm32h7xx_hal.h
  • IS_GPIO_AF : stm32h7xx_hal_gpio_ex.h
  • IS_GPIO_MODE : stm32h7xx_hal_gpio.h
  • IS_GPIO_PIN : stm32h7xx_hal_gpio.h
  • IS_GPIO_PIN_ACTION : stm32h7xx_hal_gpio.h
  • IS_GPIO_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • IS_GPIO_PULL : stm32h7xx_hal_gpio.h
  • IS_GPIO_SPEED : stm32h7xx_hal_gpio.h
  • IS_HASH_DATATYPE : stm32h7xx_hal_hash.h
  • IS_HASH_DMA_MULTIBUFFER_SIZE : stm32h7xx_hal_hash.h
  • IS_HASH_POLLING_MULTIBUFFER_SIZE : stm32h7xx_hal_hash.h
  • IS_HASH_PROCESSING : stm32h7xx_hal_hash.h
  • IS_HCD_ALL_INSTANCE : stm32h7xx_hal_hcd.h
  • IS_HHRTIM_DACSYNC : stm32h7xx_hal_hrtim.h
  • IS_HMAC_DMA_MULTIBUFFER_SIZE : stm32h7xx_hal_hash.h
  • IS_HMAC_PROCESSING : stm32h7xx_hal_hash.h
  • IS_HRTIM_ADCTRIGGER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_ADCTRIGGERUPDATE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_AUTODELAYEDMODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_BASICOCMODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_BURSTMODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_BURSTMODECLOCKSOURCE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_BURSTMODECTL : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_BURSTMODEPRELOAD : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_BURSTMODETRIGGER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_CAPTUREUNIT : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_CHOPPER_DUTYCYCLE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_CHOPPER_PRESCALERRATIO : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_CHOPPER_PULSEWIDTH : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_COMPAREUNIT : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_EVENT : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_EVENTFASTMODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_EVENTFILTER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_EVENTPOLARITY : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_EVENTPRESCALER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_EVENTSENSITIVITY : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_EVENTSRC : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_FAULT : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_FAULTFILTER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_FAULTLOCK : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_FAULTMODECTL : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_FAULTPOLARITY : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_FAULTPRESCALER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_FAULTSOURCE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_HALFMODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_HRTIM_BURSTMODEPRESCALER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_IT : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_MASTER_DMA : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_MASTER_IT : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_MODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_MODE_ONEPULSE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_OUTPUT : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_OUTPUTBURSTMODEENTRY : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_OUTPUTCHOPPERMODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_OUTPUTFAULTLEVEL : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_OUTPUTIDLELEVEL : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_OUTPUTIDLEMODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_OUTPUTLEVEL : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_OUTPUTPOLARITY : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_OUTPUTRESET : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_OUTPUTSET : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_PRELOAD : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_PRESCALERRATIO : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_SYNCINPUTSOURCE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_SYNCOUTPUTPOLARITY : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_SYNCOUTPUTSOURCE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_SYNCRESET : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_SYNCSTART : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIM_DMA : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIM_IT : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMDEADTIME_FALLINGLOCK : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMDEADTIME_FALLINGSIGN : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMDEADTIME_PRESCALERRATIO : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMDEADTIME_RISINGLOCK : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMDEADTIME_RISINGSIGN : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMDEADTIMEINSERTION : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMDELAYEDPROTECTION : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMER_BURSTDMA : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMER_CAPTURETRIGGER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMER_OUTPUT : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMERBURSTMODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMERID : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMERINDEX : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMERRESET : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMERUPDATE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMEVENTFILTER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMEVENTLATCH : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMFAULTENABLE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMFAULTLOCK : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMING_UNIT : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMPUSHPULLMODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMRESETTRIGGER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMUPDATEONRESET : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMUPDATETRIGGER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_UPDATEGATING_MASTER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_UPDATEGATING_TIM : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_UPDATEONREPETITION : stm32h7xx_hal_hrtim.h
  • IS_HSEM_KEY : stm32h7xx_hal_hsem.h
  • IS_HSEM_MASTERID : stm32h7xx_hal_hsem.h
  • IS_HSEM_PROCESSID : stm32h7xx_hal_hsem.h
  • IS_HSEM_SEMID : stm32h7xx_hal_hsem.h
  • IS_I2C_ADDRESSING_MODE : stm32h7xx_hal_i2c.h
  • IS_I2C_ANALOG_FILTER : stm32h7xx_hal_i2c_ex.h
  • IS_I2C_DIGITAL_FILTER : stm32h7xx_hal_i2c_ex.h
  • IS_I2C_DUAL_ADDRESS : stm32h7xx_hal_i2c.h
  • IS_I2C_FASTMODEPLUS : stm32h7xx_hal_i2c_ex.h
  • IS_I2C_GENERAL_CALL : stm32h7xx_hal_i2c.h
  • IS_I2C_MEMADD_SIZE : stm32h7xx_hal_i2c.h
  • IS_I2C_NO_STRETCH : stm32h7xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32h7xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2 : stm32h7xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2_MASK : stm32h7xx_hal_i2c.h
  • IS_I2C_TRANSFER_OPTIONS_REQUEST : stm32h7xx_hal_i2c.h
  • IS_I2S_AUDIO_FREQ : stm32h7xx_hal_i2s.h
  • IS_I2S_CPOL : stm32h7xx_hal_i2s.h
  • IS_I2S_DATA_24BIT_ALIGNMENT : stm32h7xx_hal_i2s.h
  • IS_I2S_DATA_FORMAT : stm32h7xx_hal_i2s.h
  • IS_I2S_FD_MODE : stm32h7xx_hal_i2s.h
  • IS_I2S_FIFO_THRESHOLD : stm32h7xx_hal_i2s.h
  • IS_I2S_FIRST_BIT : stm32h7xx_hal_i2s.h
  • IS_I2S_IO_SWAP : stm32h7xx_hal_i2s.h
  • IS_I2S_MASTER : stm32h7xx_hal_i2s.h
  • IS_I2S_MASTER_KEEP_IO_STATE : stm32h7xx_hal_i2s.h
  • IS_I2S_MCLK_OUTPUT : stm32h7xx_hal_i2s.h
  • IS_I2S_MODE : stm32h7xx_hal_i2s.h
  • IS_I2S_RX_MODE : stm32h7xx_hal_i2s.h
  • IS_I2S_SLAVE_EXTEND_FRE_DETECTION : stm32h7xx_hal_i2s.h
  • IS_I2S_STANDARD : stm32h7xx_hal_i2s.h
  • IS_I2S_TX_MODE : stm32h7xx_hal_i2s.h
  • IS_I2S_WS_INVERSION : stm32h7xx_hal_i2s.h
  • IS_IRDA_BAUDRATE : stm32h7xx_hal_irda.h
  • IS_IRDA_DMA_RX : stm32h7xx_hal_irda.h
  • IS_IRDA_DMA_TX : stm32h7xx_hal_irda.h
  • IS_IRDA_MODE : stm32h7xx_hal_irda.h
  • IS_IRDA_ONE_BIT_SAMPLE : stm32h7xx_hal_irda.h
  • IS_IRDA_PARITY : stm32h7xx_hal_irda.h
  • IS_IRDA_POWERMODE : stm32h7xx_hal_irda.h
  • IS_IRDA_PRESCALER : stm32h7xx_hal_irda.h
  • IS_IRDA_REQUEST_PARAMETER : stm32h7xx_hal_irda.h
  • IS_IRDA_STATE : stm32h7xx_hal_irda.h
  • IS_IRDA_TX_RX_MODE : stm32h7xx_hal_irda.h
  • IS_IRDA_WORD_LENGTH : stm32h7xx_hal_irda.h
  • IS_IWDG_PRESCALER : stm32h7xx_hal_iwdg.h
  • IS_IWDG_RELOAD : stm32h7xx_hal_iwdg.h
  • IS_IWDG_WINDOW : stm32h7xx_hal_iwdg.h
  • IS_JPEG_CHROMASUBSAMPLING : stm32h7xx_hal_jpeg.h
  • IS_JPEG_COLORSPACE : stm32h7xx_hal_jpeg.h
  • IS_JPEG_IMAGE_QUALITY : stm32h7xx_hal_jpeg.h
  • IS_JPEG_PAUSE_RESUME_STATE : stm32h7xx_hal_jpeg.h
  • IS_LPTIM_AUTORELOAD : stm32h7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_POLARITY : stm32h7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALER : stm32h7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALERDIV1 : stm32h7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SAMPLE_TIME : stm32h7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SOURCE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_COMPARE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_COUNTER_SOURCE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_EXT_TRG_POLARITY : stm32h7xx_hal_lptim.h
  • IS_LPTIM_INPUT1_SOURCE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_INPUT2_SOURCE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_OUTPUT_POLARITY : stm32h7xx_hal_lptim.h
  • IS_LPTIM_PERIOD : stm32h7xx_hal_lptim.h
  • IS_LPTIM_PULSE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_TRG_SOURCE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_TRIG_SAMPLE_TIME : stm32h7xx_hal_lptim.h
  • IS_LPTIM_UPDATE_MODE : stm32h7xx_hal_lptim.h
  • IS_LPUART_STOPBITS : stm32h7xx_hal_uart.h
  • IS_LTDC_AAH : stm32h7xx_hal_ltdc.h
  • IS_LTDC_AAW : stm32h7xx_hal_ltdc.h
  • IS_LTDC_AHBP : stm32h7xx_hal_ltdc.h
  • IS_LTDC_ALPHA : stm32h7xx_hal_ltdc.h
  • IS_LTDC_AVBP : stm32h7xx_hal_ltdc.h
  • IS_LTDC_BLENDING_FACTOR1 : stm32h7xx_hal_ltdc.h
  • IS_LTDC_BLENDING_FACTOR2 : stm32h7xx_hal_ltdc.h
  • IS_LTDC_BLUEVALUE : stm32h7xx_hal_ltdc.h
  • IS_LTDC_CFBLL : stm32h7xx_hal_ltdc.h
  • IS_LTDC_CFBLNBR : stm32h7xx_hal_ltdc.h
  • IS_LTDC_CFBP : stm32h7xx_hal_ltdc.h
  • IS_LTDC_DEPOL : stm32h7xx_hal_ltdc.h
  • IS_LTDC_GREENVALUE : stm32h7xx_hal_ltdc.h
  • IS_LTDC_HCONFIGSP : stm32h7xx_hal_ltdc.h
  • IS_LTDC_HCONFIGST : stm32h7xx_hal_ltdc.h
  • IS_LTDC_HSPOL : stm32h7xx_hal_ltdc.h
  • IS_LTDC_HSYNC : stm32h7xx_hal_ltdc.h
  • IS_LTDC_LAYER : stm32h7xx_hal_ltdc.h
  • IS_LTDC_LIPOS : stm32h7xx_hal_ltdc.h
  • IS_LTDC_PCPOL : stm32h7xx_hal_ltdc.h
  • IS_LTDC_PIXEL_FORMAT : stm32h7xx_hal_ltdc.h
  • IS_LTDC_REDVALUE : stm32h7xx_hal_ltdc.h
  • IS_LTDC_RELOAD : stm32h7xx_hal_ltdc.h
  • IS_LTDC_TOTALH : stm32h7xx_hal_ltdc.h
  • IS_LTDC_TOTALW : stm32h7xx_hal_ltdc.h
  • IS_LTDC_VCONFIGSP : stm32h7xx_hal_ltdc.h
  • IS_LTDC_VCONFIGST : stm32h7xx_hal_ltdc.h
  • IS_LTDC_VSPOL : stm32h7xx_hal_ltdc.h
  • IS_LTDC_VSYNC : stm32h7xx_hal_ltdc.h
  • IS_MDIOS_PORTADDRESS : stm32h7xx_hal_mdios.h
  • IS_MDIOS_PREAMBLECHECK : stm32h7xx_hal_mdios.h
  • IS_MDIOS_REGISTER : stm32h7xx_hal_mdios.h
  • IS_MDMA_BLOCK_ADDR_OFFSET : stm32h7xx_hal_mdma.h
  • IS_MDMA_BLOCK_COUNT : stm32h7xx_hal_mdma.h
  • IS_MDMA_BUFFER_TRANSFER_LENGTH : stm32h7xx_hal_mdma.h
  • IS_MDMA_DATA_ALIGNMENT : stm32h7xx_hal_mdma.h
  • IS_MDMA_DESTINATION_BURST : stm32h7xx_hal_mdma.h
  • IS_MDMA_DESTINATION_DATASIZE : stm32h7xx_hal_mdma.h
  • IS_MDMA_DESTINATION_INC : stm32h7xx_hal_mdma.h
  • IS_MDMA_ENDIANNESS_MODE : stm32h7xx_hal_mdma.h
  • IS_MDMA_LEVEL_COMPLETE : stm32h7xx_hal_mdma.h
  • IS_MDMA_PRIORITY : stm32h7xx_hal_mdma.h
  • IS_MDMA_REQUEST : stm32h7xx_hal_mdma.h
  • IS_MDMA_SOURCE_BURST : stm32h7xx_hal_mdma.h
  • IS_MDMA_SOURCE_DATASIZE : stm32h7xx_hal_mdma.h
  • IS_MDMA_SOURCE_INC : stm32h7xx_hal_mdma.h
  • IS_MDMA_TRANSFER_LENGTH : stm32h7xx_hal_mdma.h
  • IS_MDMA_TRANSFER_TRIGGER_MODE : stm32h7xx_hal_mdma.h
  • IS_MPU_ACCESS_BUFFERABLE : stm32h7xx_hal_cortex.h
  • IS_MPU_ACCESS_CACHEABLE : stm32h7xx_hal_cortex.h
  • IS_MPU_ACCESS_SHAREABLE : stm32h7xx_hal_cortex.h
  • IS_MPU_INSTRUCTION_ACCESS : stm32h7xx_hal_cortex.h
  • IS_MPU_REGION_ENABLE : stm32h7xx_hal_cortex.h
  • IS_MPU_REGION_NUMBER : stm32h7xx_hal_cortex.h
  • IS_MPU_REGION_PERMISSION_ATTRIBUTE : stm32h7xx_hal_cortex.h
  • IS_MPU_REGION_SIZE : stm32h7xx_hal_cortex.h
  • IS_MPU_SUB_REGION_DISABLE : stm32h7xx_hal_cortex.h
  • IS_MPU_TEX_LEVEL : stm32h7xx_hal_cortex.h
  • IS_NVIC_DEVICE_IRQ : stm32h7xx_hal_cortex.h
  • IS_NVIC_PREEMPTION_PRIORITY : stm32h7xx_hal_cortex.h
  • IS_NVIC_PRIORITY_GROUP : stm32h7xx_hal_cortex.h
  • IS_NVIC_SUB_PRIORITY : stm32h7xx_hal_cortex.h
  • IS_OB_BOOT_ADD_OPTION : stm32h7xx_hal_flash_ex.h
  • IS_OB_BOOT_ADDRESS : stm32h7xx_hal_flash_ex.h
  • IS_OB_BOR_LEVEL : stm32h7xx_hal_flash_ex.h
  • IS_OB_IWDG1_SOURCE : stm32h7xx_hal_flash_ex.h
  • IS_OB_IWDG_SOURCE : stm32h7xx_hal_flash_ex.h
  • IS_OB_IWDG_STDBY_FREEZE : stm32h7xx_hal_flash_ex.h
  • IS_OB_IWDG_STOP_FREEZE : stm32h7xx_hal_flash_ex.h
  • IS_OB_PCROP_RDP : stm32h7xx_hal_flash_ex.h
  • IS_OB_RDP_LEVEL : stm32h7xx_hal_flash_ex.h
  • IS_OB_SECURE_RDP : stm32h7xx_hal_flash_ex.h
  • IS_OB_STDBY_D1_RESET : stm32h7xx_hal_flash_ex.h
  • IS_OB_STDBY_SOURCE : stm32h7xx_hal_flash_ex.h
  • IS_OB_STOP_D1_RESET : stm32h7xx_hal_flash_ex.h
  • IS_OB_STOP_SOURCE : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_IOHSLV : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_IWDG_STDBY : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_IWDG_STOP : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_SECURITY : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_SWAP_BANK : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_TYPE : stm32h7xx_hal_flash_ex.h
  • IS_OB_WRP_SECTOR : stm32h7xx_hal_flash_ex.h
  • IS_OB_WWDG_SOURCE : stm32h7xx_hal_flash_ex.h
  • IS_OPAMP_FACTORYTRIMMING : stm32h7xx_hal_opamp.h
  • IS_OPAMP_FUNCTIONAL_NORMALMODE : stm32h7xx_hal_opamp.h
  • IS_OPAMP_INVERTING_INPUT_STANDALONE : stm32h7xx_hal_opamp.h
  • IS_OPAMP_NONINVERTING_INPUT : stm32h7xx_hal_opamp.h
  • IS_OPAMP_PGA_GAIN : stm32h7xx_hal_opamp.h
  • IS_OPAMP_PGACONNECT : stm32h7xx_hal_opamp.h
  • IS_OPAMP_POWERMODE : stm32h7xx_hal_opamp.h
  • IS_OPAMP_TRIMMING : stm32h7xx_hal_opamp.h
  • IS_OPAMP_TRIMMINGVALUE : stm32h7xx_hal_opamp.h
  • IS_OPAMP_VREF : stm32h7xx_hal_opamp.h
  • IS_OPTIONBYTE : stm32h7xx_hal_flash_ex.h
  • IS_PARITY_ERROR_MASK : stm32h7xx_hal_spdifrx.h
  • IS_PCD_ALL_INSTANCE : stm32h7xx_hal_pcd.h
  • IS_PREAMBLE_TYPE_MASK : stm32h7xx_hal_spdifrx.h
  • IS_PWR_AVD_LEVEL : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_AVD_MODE : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_BATTERY_RESISTOR_SELECT : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_DOMAIN : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_PVD_LEVEL : stm32h7xx_hal_pwr.h
  • IS_PWR_PVD_MODE : stm32h7xx_hal_pwr.h
  • IS_PWR_REGULATOR : stm32h7xx_hal_pwr.h
  • IS_PWR_REGULATOR_VOLTAGE : stm32h7xx_hal_pwr.h
  • IS_PWR_SLEEP_ENTRY : stm32h7xx_hal_pwr.h
  • IS_PWR_STOP_ENTRY : stm32h7xx_hal_pwr.h
  • IS_PWR_STOP_MODE_REGULATOR_VOLTAGE : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_SUPPLY : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_FLAG : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN_POLARITY : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN_PULL : stm32h7xx_hal_pwr_ex.h
  • IS_QSPI_ADDRESS_MODE : stm32h7xx_hal_qspi.h
  • IS_QSPI_ADDRESS_SIZE : stm32h7xx_hal_qspi.h
  • IS_QSPI_ALTERNATE_BYTES_MODE : stm32h7xx_hal_qspi.h
  • IS_QSPI_ALTERNATE_BYTES_SIZE : stm32h7xx_hal_qspi.h
  • IS_QSPI_AUTOMATIC_STOP : stm32h7xx_hal_qspi.h
  • IS_QSPI_CLOCK_MODE : stm32h7xx_hal_qspi.h
  • IS_QSPI_CLOCK_PRESCALER : stm32h7xx_hal_qspi.h
  • IS_QSPI_CS_HIGH_TIME : stm32h7xx_hal_qspi.h
  • IS_QSPI_DATA_MODE : stm32h7xx_hal_qspi.h
  • IS_QSPI_DDR_HHC : stm32h7xx_hal_qspi.h
  • IS_QSPI_DDR_MODE : stm32h7xx_hal_qspi.h
  • IS_QSPI_DUAL_FLASH_MODE : stm32h7xx_hal_qspi.h
  • IS_QSPI_DUMMY_CYCLES : stm32h7xx_hal_qspi.h
  • IS_QSPI_FIFO_THRESHOLD : stm32h7xx_hal_qspi.h
  • IS_QSPI_FLASH_ID : stm32h7xx_hal_qspi.h
  • IS_QSPI_FLASH_SIZE : stm32h7xx_hal_qspi.h
  • IS_QSPI_FUNCTIONAL_MODE : stm32h7xx_hal_qspi.c
  • IS_QSPI_INSTRUCTION : stm32h7xx_hal_qspi.h
  • IS_QSPI_INSTRUCTION_MODE : stm32h7xx_hal_qspi.h
  • IS_QSPI_INTERVAL : stm32h7xx_hal_qspi.h
  • IS_QSPI_MATCH_MODE : stm32h7xx_hal_qspi.h
  • IS_QSPI_SIOO_MODE : stm32h7xx_hal_qspi.h
  • IS_QSPI_SSHIFT : stm32h7xx_hal_qspi.h
  • IS_QSPI_STATUS_BYTES_SIZE : stm32h7xx_hal_qspi.h
  • IS_QSPI_TIMEOUT_ACTIVATION : stm32h7xx_hal_qspi.h
  • IS_QSPI_TIMEOUT_PERIOD : stm32h7xx_hal_qspi.h
  • IS_RCC_ADCCLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CALIBRATION_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_CECCLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CLKPSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CLOCKTYPE : stm32h7xx_hal_rcc.h
  • IS_RCC_CRS_ERRORLIMIT : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_FREQERRORDIR : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_HSI48CALIBRATION : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_RELOADVALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_DIV : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_POLARITY : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_SOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CSI : stm32h7xx_hal_rcc.h
  • IS_RCC_CSICALIBRATION_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_D1PCLK1 : stm32h7xx_hal_rcc.h
  • IS_RCC_D3PCLK1 : stm32h7xx_hal_rcc.h
  • IS_RCC_DFSDM1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_FDCANCLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_FLAG : stm32h7xx_hal_rcc.h
  • IS_RCC_FMCCLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_HCLK : stm32h7xx_hal_rcc.h
  • IS_RCC_HRTIM1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_HSE : stm32h7xx_hal_rcc.h
  • IS_RCC_HSI : stm32h7xx_hal_rcc.h
  • IS_RCC_HSI48 : stm32h7xx_hal_rcc.h
  • IS_RCC_I2C1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_I2C2CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_I2C3CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_I2C4CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPTIM1CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPTIM2CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPTIM3CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPTIM4CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPTIM5CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPUART1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LSE : stm32h7xx_hal_rcc.h
  • IS_RCC_LSI : stm32h7xx_hal_rcc.h
  • IS_RCC_MCO : stm32h7xx_hal_rcc.h
  • IS_RCC_MCO1SOURCE : stm32h7xx_hal_rcc.h
  • IS_RCC_MCO2SOURCE : stm32h7xx_hal_rcc.h
  • IS_RCC_MCODIV : stm32h7xx_hal_rcc.h
  • IS_RCC_OSCILLATORTYPE : stm32h7xx_hal_rcc.h
  • IS_RCC_PCLK1 : stm32h7xx_hal_rcc.h
  • IS_RCC_PCLK2 : stm32h7xx_hal_rcc.h
  • IS_RCC_PERIPHCLOCK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL : stm32h7xx_hal_rcc.h
  • IS_RCC_PLL2CLOCKOUT_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2M_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2N_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2P_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2Q_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2R_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3CLOCKOUT_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3M_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3N_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3P_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3Q_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3R_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLLCLOCKOUT_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLM_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLN_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLP_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLQ_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLR_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLSOURCE : stm32h7xx_hal_rcc.h
  • IS_RCC_QSPICLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_RNGCLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_RTCCLKSOURCE : stm32h7xx_hal_rcc.h
  • IS_RCC_SAI1CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SAI2CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SAI3CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SAI4ACLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SAI4BCLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SCOPE_WWDG : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SDMMC : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPDIFRXCLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI1CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI2CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI3CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI4CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI5CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI6CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_STOP_KERWAKEUPCLOCK : stm32h7xx_hal_rcc.h
  • IS_RCC_STOP_WAKEUPCLOCK : stm32h7xx_hal_rcc.h
  • IS_RCC_SWPMI1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SYSCLK : stm32h7xx_hal_rcc.h
  • IS_RCC_SYSCLKSOURCE : stm32h7xx_hal_rcc.h
  • IS_RCC_TIMPRES : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_UART4CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_UART5CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_UART7CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_UART8CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART2CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART3CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART6CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USBCLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RNG_CED : stm32h7xx_hal_rng.h
  • IS_RNG_FLAG : stm32h7xx_hal_rng.h
  • IS_RNG_IT : stm32h7xx_hal_rng.h
  • IS_RTC_ALARM : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_DATE : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_SEL : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_MASK : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_MASK : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_VALUE : stm32h7xx_hal_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32h7xx_hal_rtc.h
  • IS_RTC_BKP : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_CALIB_OUTPUT : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_DATE : stm32h7xx_hal_rtc.h
  • IS_RTC_DAYLIGHT_SAVING : stm32h7xx_hal_rtc.h
  • IS_RTC_FORMAT : stm32h7xx_hal_rtc.h
  • IS_RTC_HOUR12 : stm32h7xx_hal_rtc.h
  • IS_RTC_HOUR24 : stm32h7xx_hal_rtc.h
  • IS_RTC_HOUR_FORMAT : stm32h7xx_hal_rtc.h
  • IS_RTC_HOURFORMAT12 : stm32h7xx_hal_rtc.h
  • IS_RTC_MINUTES : stm32h7xx_hal_rtc.h
  • IS_RTC_MONTH : stm32h7xx_hal_rtc.h
  • IS_RTC_OUTPUT : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_OUTPUT_POL : stm32h7xx_hal_rtc.h
  • IS_RTC_OUTPUT_REMAP : stm32h7xx_hal_rtc.h
  • IS_RTC_OUTPUT_TYPE : stm32h7xx_hal_rtc.h
  • IS_RTC_SECONDS : stm32h7xx_hal_rtc.h
  • IS_RTC_SHIFT_ADD1S : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_SHIFT_SUBFS : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PERIOD : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PLUS : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_STORE_OPERATION : stm32h7xx_hal_rtc.h
  • IS_RTC_SYNCH_PREDIV : stm32h7xx_hal_rtc.h
  • IS_RTC_TAMPER : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_ERASE_MODE : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_FILTER : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_MASKFLAG_STATE : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PRECHARGE_DURATION : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PULLUP_STATE : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TRIGGER : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMP_PIN : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_CLOCK : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_COUNTER : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_WEEKDAY : stm32h7xx_hal_rtc.h
  • IS_RTC_YEAR : stm32h7xx_hal_rtc.h
  • IS_SAI_AUDIO_FREQUENCY : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_ACTIVE_FRAME : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_CLOCK_STROBING : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_COMPANDING_MODE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_DATASIZE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FIFO_THRESHOLD : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FIRST_BIT : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FIRSTBIT_OFFSET : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FRAME_LENGTH : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FS_DEFINITION : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FS_OFFSET : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FS_POLARITY : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MASTER_DIVIDER : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MCK_OVERSAMPLING : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MODE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_COUNTER : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_VALUE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_NODIVIDER : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_OUTPUT_DRIVE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_PROTOCOL : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_NUMBER : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_SIZE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_SYNCEXT : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_SYNCHRO : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_TRISTATE_MANAGEMENT : stm32h7xx_hal_sai.h
  • IS_SAI_MONO_STEREO_MODE : stm32h7xx_hal_sai.h
  • IS_SAI_PDM_CLOCK_ENABLE : stm32h7xx_hal_sai.h
  • IS_SAI_PDM_MIC_DELAY : stm32h7xx_hal_sai_ex.h
  • IS_SAI_PDM_MIC_PAIRS_NUMBER : stm32h7xx_hal_sai.h
  • IS_SAI_PROTOCOL_DATASIZE : stm32h7xx_hal_sai.h
  • IS_SAI_SLOT_ACTIVE : stm32h7xx_hal_sai.h
  • IS_SAI_SUPPORTED_PROTOCOL : stm32h7xx_hal_sai.h
  • IS_SMARTCARD_ADVFEATURE_DATAINV : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_DMAONRXERROR : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_INIT : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_MSBFIRST : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_RXINV : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_SWAP : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_TXINV : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_AUTORETRY_COUNT : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_BAUDRATE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_BLOCKLENGTH : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_FIFO_MODE_STATE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_LASTBIT : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_MODE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_NACK : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ONE_BIT_SAMPLE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_OVERRUN : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_PARITY : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_PHASE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_POLARITY : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_REQUEST_PARAMETER : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_RXFIFO_THRESHOLD : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_STOPBITS : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT_VALUE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_TRANSMISSION_COMPLETION : stm32h7xx_hal_smartcard_ex.h
  • IS_SMARTCARD_TXFIFO_THRESHOLD : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_WORD_LENGTH : stm32h7xx_hal_smartcard.h
  • IS_SMBUS_ADDRESSING_MODE : stm32h7xx_hal_smbus.h
  • IS_SMBUS_ANALOG_FILTER : stm32h7xx_hal_smbus.h
  • IS_SMBUS_DUAL_ADDRESS : stm32h7xx_hal_smbus.h
  • IS_SMBUS_GENERAL_CALL : stm32h7xx_hal_smbus.h
  • IS_SMBUS_NO_STRETCH : stm32h7xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS1 : stm32h7xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2 : stm32h7xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2_MASK : stm32h7xx_hal_smbus.h
  • IS_SMBUS_PEC : stm32h7xx_hal_smbus.h
  • IS_SMBUS_PERIPHERAL_MODE : stm32h7xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_MODE : stm32h7xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OPTIONS_REQUEST : stm32h7xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST : stm32h7xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_REQUEST : stm32h7xx_hal_smbus.h
  • IS_SPDIFRX_CHANNEL : stm32h7xx_hal_spdifrx.h
  • IS_SPDIFRX_DATA_FORMAT : stm32h7xx_hal_spdifrx.h
  • IS_SPDIFRX_INPUT_SELECT : stm32h7xx_hal_spdifrx.h
  • IS_SPDIFRX_MAX_RETRIES : stm32h7xx_hal_spdifrx.h
  • IS_SPDIFRX_WAIT_FOR_ACTIVITY : stm32h7xx_hal_spdifrx.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32h7xx_hal_spi.h
  • IS_SPI_CPHA : stm32h7xx_hal_spi.h
  • IS_SPI_CPOL : stm32h7xx_hal_spi.h
  • IS_SPI_CRC_CALCULATION : stm32h7xx_hal_spi.h
  • IS_SPI_CRC_INITIALIZATION_PATTERN : stm32h7xx_hal_spi.h
  • IS_SPI_CRC_LENGTH : stm32h7xx_hal_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32h7xx_hal_spi.h
  • IS_SPI_DATASIZE : stm32h7xx_hal_spi.h
  • IS_SPI_DIRECTION : stm32h7xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES : stm32h7xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY : stm32h7xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY : stm32h7xx_hal_spi.h
  • IS_SPI_FIFOTHRESHOLD : stm32h7xx_hal_spi.h
  • IS_SPI_FIRST_BIT : stm32h7xx_hal_spi.h
  • IS_SPI_MODE : stm32h7xx_hal_spi.h
  • IS_SPI_NSS : stm32h7xx_hal_spi.h
  • IS_SPI_NSSP : stm32h7xx_hal_spi.h
  • IS_SPI_TIMODE : stm32h7xx_hal_spi.h
  • IS_SPI_UNDERRUN_BEHAVIOUR : stm32h7xx_hal_spi.h
  • IS_SPI_UNDERRUN_DETECTION : stm32h7xx_hal_spi.h
  • IS_STEREO_MODE : stm32h7xx_hal_spdifrx.h
  • IS_SWPMI_BITRATE_VALUE : stm32h7xx_hal_swpmi.h
  • IS_SWPMI_RX_BUFFERING_MODE : stm32h7xx_hal_swpmi.h
  • IS_SWPMI_TX_BUFFERING_MODE : stm32h7xx_hal_swpmi.h
  • IS_SWPMI_VOLTAGE_CLASS : stm32h7xx_hal_swpmi.h
  • IS_SYSCFG_ANALOG_SWITCH : stm32h7xx_hal.h
  • IS_SYSCFG_BOOT_ADDRESS : stm32h7xx_hal.h
  • IS_SYSCFG_BOOT_REGISTER : stm32h7xx_hal.h
  • IS_SYSCFG_CODE_CONFIG : stm32h7xx_hal.h
  • IS_SYSCFG_CODE_SELECT : stm32h7xx_hal.h
  • IS_SYSCFG_ETHERNET_CONFIG : stm32h7xx_hal.h
  • IS_SYSCFG_SWITCH_STATE : stm32h7xx_hal.h
  • IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE : stm32h7xx_hal.h
  • IS_SYSCFG_VREFBUF_TRIMMING : stm32h7xx_hal.h
  • IS_SYSCFG_VREFBUF_VOLTAGE_SCALE : stm32h7xx_hal.h
  • IS_SYSTICK_CLK_SOURCE : stm32h7xx_hal_cortex.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_AUTORELOAD_PRELOAD : stm32h7xx_hal_tim.h
  • IS_TIM_BKR2REMAP : stm32h7xx_hal_tim_ex.h
  • IS_TIM_BKRREMAP : stm32h7xx_hal_tim_ex.h
  • IS_TIM_BREAK2_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK2_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK_FILTER : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK_SYSTEM : stm32h7xx_hal_tim.h
  • IS_TIM_BREAKINPUT : stm32h7xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE : stm32h7xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_POLARITY : stm32h7xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_STATE : stm32h7xx_hal_tim_ex.h
  • IS_TIM_CHANNELS : stm32h7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_FILTER : stm32h7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_PRESCALER : stm32h7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_SOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_CLOCKDIVISION_DIV : stm32h7xx_hal_tim.h
  • IS_TIM_CLOCKFILTER : stm32h7xx_hal_tim.h
  • IS_TIM_CLOCKPOLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_CLOCKPRESCALER : stm32h7xx_hal_tim.h
  • IS_TIM_CLOCKSOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_COMPLEMENTARY_CHANNELS : stm32h7xx_hal_tim.h
  • IS_TIM_COUNTER_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_DEADTIME : stm32h7xx_hal_tim.h
  • IS_TIM_DMA_BASE : stm32h7xx_hal_tim.h
  • IS_TIM_DMA_LENGTH : stm32h7xx_hal_tim.h
  • IS_TIM_DMA_SOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_ENCODER_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_ETRREMAP : stm32h7xx_hal_tim_ex.h
  • IS_TIM_EVENT_SOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_FAST_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_GROUPCH5 : stm32h7xx_hal_tim.h
  • IS_TIM_IC_FILTER : stm32h7xx_hal_tim.h
  • IS_TIM_IC_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_IC_PRESCALER : stm32h7xx_hal_tim.h
  • IS_TIM_IC_SELECTION : stm32h7xx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION : stm32h7xx_hal_tim.h
  • IS_TIM_LOCK_LEVEL : stm32h7xx_hal_tim.h
  • IS_TIM_MSM_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_OC_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_OC_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_OCIDLE_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_OCN_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_OPM_CHANNELS : stm32h7xx_hal_tim.h
  • IS_TIM_OPM_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_OSSI_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_OSSR_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_PWM_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_REMAP : stm32h7xx_hal_tim_ex.h
  • IS_TIM_SLAVE_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_TI1SELECTION : stm32h7xx_hal_tim.h
  • IS_TIM_TISEL : stm32h7xx_hal_tim_ex.h
  • IS_TIM_TRGO2_SOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_TRGO_SOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32h7xx_hal_tim.h
  • IS_TIM_TRIGGERFILTER : stm32h7xx_hal_tim.h
  • IS_TIM_TRIGGERPOLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_TRIGGERPRESCALER : stm32h7xx_hal_tim.h
  • IS_TIMESTAMP_EDGE : stm32h7xx_hal_rtc_ex.h
  • IS_TRANSFER_MODE : stm32h7xx_hal_i2c.h
  • IS_TRANSFER_REQUEST : stm32h7xx_hal_i2c.h
  • IS_UART_ADDRESSLENGTH_DETECT : stm32h7xx_hal_uart_ex.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATE : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATEMODE : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_DATAINV : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_DMAONRXERROR : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_INIT : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_MSBFIRST : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_RXINV : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_STOPMODE : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_SWAP : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_TXINV : stm32h7xx_hal_uart.h
  • IS_UART_ASSERTIONTIME : stm32h7xx_hal_uart.h
  • IS_UART_BAUDRATE : stm32h7xx_hal_uart.h
  • IS_UART_DE_POLARITY : stm32h7xx_hal_uart.h
  • IS_UART_DEASSERTIONTIME : stm32h7xx_hal_uart.h
  • IS_UART_DMA_RX : stm32h7xx_hal_uart.h
  • IS_UART_DMA_TX : stm32h7xx_hal_uart.h
  • IS_UART_FIFO_MODE_STATE : stm32h7xx_hal_uart.h
  • IS_UART_HALF_DUPLEX : stm32h7xx_hal_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : stm32h7xx_hal_uart.h
  • IS_UART_LIN : stm32h7xx_hal_uart.h
  • IS_UART_LIN_BREAK_DETECT_LENGTH : stm32h7xx_hal_uart.h
  • IS_UART_MODE : stm32h7xx_hal_uart.h
  • IS_UART_MUTE_MODE : stm32h7xx_hal_uart.h
  • IS_UART_ONE_BIT_SAMPLE : stm32h7xx_hal_uart.h
  • IS_UART_OVERRUN : stm32h7xx_hal_uart.h
  • IS_UART_OVERSAMPLING : stm32h7xx_hal_uart.h
  • IS_UART_PARITY : stm32h7xx_hal_uart.h
  • IS_UART_PRESCALER : stm32h7xx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT : stm32h7xx_hal_uart.h
  • IS_UART_REQUEST_PARAMETER : stm32h7xx_hal_uart.h
  • IS_UART_RXFIFO_THRESHOLD : stm32h7xx_hal_uart.h
  • IS_UART_STATE : stm32h7xx_hal_uart.h
  • IS_UART_STOPBITS : stm32h7xx_hal_uart.h
  • IS_UART_TXFIFO_THRESHOLD : stm32h7xx_hal_uart.h
  • IS_UART_WAKEUP_SELECTION : stm32h7xx_hal_uart.h
  • IS_UART_WAKEUPMETHOD : stm32h7xx_hal_uart.h
  • IS_UART_WORD_LENGTH : stm32h7xx_hal_uart_ex.h
  • IS_USART_BAUDRATE : stm32h7xx_hal_usart.h
  • IS_USART_CLOCK : stm32h7xx_hal_usart.h
  • IS_USART_FIFO_MODE_STATE : stm32h7xx_hal_usart.h
  • IS_USART_LASTBIT : stm32h7xx_hal_usart.h
  • IS_USART_MODE : stm32h7xx_hal_usart.h
  • IS_USART_NSS : stm32h7xx_hal_usart.h
  • IS_USART_OVERSAMPLING : stm32h7xx_hal_usart.h
  • IS_USART_PARITY : stm32h7xx_hal_usart.h
  • IS_USART_PHASE : stm32h7xx_hal_usart.h
  • IS_USART_POLARITY : stm32h7xx_hal_usart.h
  • IS_USART_PRESCALER : stm32h7xx_hal_usart.h
  • IS_USART_REQUEST_PARAMETER : stm32h7xx_hal_usart.h
  • IS_USART_RXFIFO_THRESHOLD : stm32h7xx_hal_usart.h
  • IS_USART_SLAVEMODE : stm32h7xx_hal_usart.h
  • IS_USART_STOPBITS : stm32h7xx_hal_usart.h
  • IS_USART_TXFIFO_THRESHOLD : stm32h7xx_hal_usart.h
  • IS_USART_WORD_LENGTH : stm32h7xx_hal_usart_ex.h
  • IS_VALIDITY_MASK : stm32h7xx_hal_spdifrx.h
  • IS_VOLTAGERANGE : stm32h7xx_hal_flash_ex.h
  • IS_WRPSTATE : stm32h7xx_hal_flash_ex.h
  • IS_WWDG_COUNTER : stm32h7xx_hal_wwdg.h
  • IS_WWDG_EWI_MODE : stm32h7xx_hal_wwdg.h
  • IS_WWDG_PRESCALER : stm32h7xx_hal_wwdg.h
  • IS_WWDG_WINDOW : stm32h7xx_hal_wwdg.h
  • IWDG_DISABLE_WRITE_ACCESS : stm32h7xx_hal_iwdg.h
  • IWDG_ENABLE_WRITE_ACCESS : stm32h7xx_hal_iwdg.h
  • IWDG_KEY_ENABLE : stm32h7xx_hal_iwdg.h
  • IWDG_KEY_RELOAD : stm32h7xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_DISABLE : stm32h7xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_ENABLE : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_128 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_16 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_256 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_32 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_4 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_64 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_8 : stm32h7xx_hal_iwdg.h
  • IWDG_WINDOW_DISABLE : stm32h7xx_hal_iwdg.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
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  • r
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  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- j -

  • JPEG_420_SUBSAMPLING : stm32h7xx_hal_jpeg.h
  • JPEG_422_SUBSAMPLING : stm32h7xx_hal_jpeg.h
  • JPEG_444_SUBSAMPLING : stm32h7xx_hal_jpeg.h
  • JPEG_AC_HUFF_TABLE_SIZE : stm32h7xx_hal_jpeg.c
  • JPEG_ACCHROM_HuffTable : stm32h7xx_hal_jpeg.c
  • JPEG_ACHuff_BitsVals_To_SizeCodes() : stm32h7xx_hal_jpeg.c
  • JPEG_ACLUM_HuffTable : stm32h7xx_hal_jpeg.c
  • JPEG_Bits_To_SizeCodes() : stm32h7xx_hal_jpeg.c
  • JPEG_CHROM_QuantTable : stm32h7xx_hal_jpeg.c
  • JPEG_CMYK_COLORSPACE : stm32h7xx_hal_jpeg.h
  • JPEG_CONTEXT_CONF_ENCODING : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_CUSTOM_TABLES : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_DECODE : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_DMA : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_ENCODE : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_ENDING_DMA : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_IT : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_METHOD_MASK : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_OPERATION_MASK : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_PAUSE_INPUT : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_PAUSE_OUTPUT : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_POLLING : stm32h7xx_hal_jpeg.c
  • JPEG_DC_HUFF_TABLE_SIZE : stm32h7xx_hal_jpeg.c
  • JPEG_DCCHROM_HuffTable : stm32h7xx_hal_jpeg.c
  • JPEG_DCHuff_BitsVals_To_SizeCodes() : stm32h7xx_hal_jpeg.c
  • JPEG_DCLUM_HuffTable : stm32h7xx_hal_jpeg.c
  • JPEG_DMA_ContinueProcess() : stm32h7xx_hal_jpeg.c
  • JPEG_DMA_EndProcess() : stm32h7xx_hal_jpeg.c
  • JPEG_DMA_PollResidualData() : stm32h7xx_hal_jpeg.c
  • JPEG_DMA_StartProcess() : stm32h7xx_hal_jpeg.c
  • JPEG_FIFO_SIZE : stm32h7xx_hal_jpeg.c
  • JPEG_FIFO_TH_SIZE : stm32h7xx_hal_jpeg.c
  • JPEG_FLAG_ALL : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_COF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_EOCF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_HPDF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_IFNFF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_IFTF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_OFNEF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_OFTF : stm32h7xx_hal_jpeg.h
  • JPEG_GetQuality() : stm32h7xx_hal_jpeg.c
  • JPEG_GRAYSCALE_COLORSPACE : stm32h7xx_hal_jpeg.h
  • JPEG_IMAGE_QUALITY_MAX : stm32h7xx_hal_jpeg.h
  • JPEG_IMAGE_QUALITY_MIN : stm32h7xx_hal_jpeg.h
  • JPEG_Init_Process() : stm32h7xx_hal_jpeg.c
  • JPEG_INTERRUPT_MASK : stm32h7xx_hal_jpeg.c
  • JPEG_IT_EOC : stm32h7xx_hal_jpeg.h
  • JPEG_IT_HPD : stm32h7xx_hal_jpeg.h
  • JPEG_IT_IFNF : stm32h7xx_hal_jpeg.h
  • JPEG_IT_IFT : stm32h7xx_hal_jpeg.h
  • JPEG_IT_OFNE : stm32h7xx_hal_jpeg.h
  • JPEG_IT_OFT : stm32h7xx_hal_jpeg.h
  • JPEG_LUM_QuantTable : stm32h7xx_hal_jpeg.c
  • JPEG_MDMAErrorCallback() : stm32h7xx_hal_jpeg.c
  • JPEG_MDMAInCpltCallback() : stm32h7xx_hal_jpeg.c
  • JPEG_MDMAOutAbortCallback() : stm32h7xx_hal_jpeg.c
  • JPEG_MDMAOutCpltCallback() : stm32h7xx_hal_jpeg.c
  • JPEG_PAUSE_RESUME_INPUT : stm32h7xx_hal_jpeg.h
  • JPEG_PAUSE_RESUME_INPUT_OUTPUT : stm32h7xx_hal_jpeg.h
  • JPEG_PAUSE_RESUME_OUTPUT : stm32h7xx_hal_jpeg.h
  • JPEG_Process() : stm32h7xx_hal_jpeg.c
  • JPEG_PROCESS_DONE : stm32h7xx_hal_jpeg.c
  • JPEG_PROCESS_ONGOING : stm32h7xx_hal_jpeg.c
  • JPEG_QUANT_TABLE_SIZE : stm32h7xx_hal_jpeg.h
  • JPEG_ReadInputData() : stm32h7xx_hal_jpeg.c
  • JPEG_Set_Huff_DHTMem() : stm32h7xx_hal_jpeg.c
  • JPEG_Set_HuffAC_Mem() : stm32h7xx_hal_jpeg.c
  • JPEG_Set_HuffDC_Mem() : stm32h7xx_hal_jpeg.c
  • JPEG_Set_HuffEnc_Mem() : stm32h7xx_hal_jpeg.c
  • JPEG_Set_Quantization_Mem() : stm32h7xx_hal_jpeg.c
  • JPEG_SetColorCMYK() : stm32h7xx_hal_jpeg.c
  • JPEG_SetColorGrayScale() : stm32h7xx_hal_jpeg.c
  • JPEG_SetColorYCBCR() : stm32h7xx_hal_jpeg.c
  • JPEG_StoreOutputData() : stm32h7xx_hal_jpeg.c
  • JPEG_TIMEOUT_VALUE : stm32h7xx_hal_jpeg.c
  • JPEG_YCBCR_COLORSPACE : stm32h7xx_hal_jpeg.h
  • JPEG_ZIGZAG_ORDER : stm32h7xx_hal_jpeg.c
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- l -

  • LPM_L0 : stm32h7xx_hal_pcd.h
  • LPM_L1 : stm32h7xx_hal_pcd.h
  • LPM_L2 : stm32h7xx_hal_pcd.h
  • LPM_L3 : stm32h7xx_hal_pcd.h
  • LPTIM4_OUT_CLEAR : stm32h7xx_hal.h
  • LPTIM5_OUT_CLEAR : stm32h7xx_hal.h
  • LPTIM_ACTIVEEDGE_FALLING : stm32h7xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING : stm32h7xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING_FALLING : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_FALLING : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING_FALLING : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_2TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_4TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_8TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_ULPTIM : stm32h7xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_EXTERNAL : stm32h7xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_INTERNAL : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_ARRM : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_ARROK : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_CMPM : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_CMPOK : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_DOWN : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_EXTTRIG : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_UP : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1 : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1_COMP2 : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP2 : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_GPIO : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_SAI1_FSA : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_SAI1_FSB : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_COMP2 : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_GPIO : stm32h7xx_hal_lptim.h
  • LPTIM_IT_ARRM : stm32h7xx_hal_lptim.h
  • LPTIM_IT_ARROK : stm32h7xx_hal_lptim.h
  • LPTIM_IT_CMPM : stm32h7xx_hal_lptim.h
  • LPTIM_IT_CMPOK : stm32h7xx_hal_lptim.h
  • LPTIM_IT_DOWN : stm32h7xx_hal_lptim.h
  • LPTIM_IT_EXTTRIG : stm32h7xx_hal_lptim.h
  • LPTIM_IT_UP : stm32h7xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_HIGH : stm32h7xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_LOW : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV1 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV128 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV16 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV2 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV32 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV4 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV64 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV8 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_2TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_4TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_8TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_0 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_1 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_2 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_3 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_4 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_5 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_6 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_7 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_SOFTWARE : stm32h7xx_hal_lptim.h
  • LPTIM_UPDATE_ENDOFPERIOD : stm32h7xx_hal_lptim.h
  • LPTIM_UPDATE_IMMEDIATE : stm32h7xx_hal_lptim.h
  • LSE_STARTUP_TIMEOUT : stm32h7xx_hal_conf.h
  • LSE_VALUE : stm32h7xx_hal_conf.h
  • LSI_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • LTDC_ALPHA : stm32h7xx_hal_ltdc.h
  • LTDC_BLENDING_FACTOR1_CA : stm32h7xx_hal_ltdc.h
  • LTDC_BLENDING_FACTOR1_PAxCA : stm32h7xx_hal_ltdc.h
  • LTDC_BLENDING_FACTOR2_CA : stm32h7xx_hal_ltdc.h
  • LTDC_BLENDING_FACTOR2_PAxCA : stm32h7xx_hal_ltdc.h
  • LTDC_COLOR : stm32h7xx_hal_ltdc.h
  • LTDC_COLOR_FRAME_BUFFER : stm32h7xx_hal_ltdc.h
  • LTDC_DEPOLARITY_AH : stm32h7xx_hal_ltdc.h
  • LTDC_DEPOLARITY_AL : stm32h7xx_hal_ltdc.h
  • LTDC_FLAG_FU : stm32h7xx_hal_ltdc.h
  • LTDC_FLAG_LI : stm32h7xx_hal_ltdc.h
  • LTDC_FLAG_RR : stm32h7xx_hal_ltdc.h
  • LTDC_FLAG_TE : stm32h7xx_hal_ltdc.h
  • LTDC_HORIZONTALSYNC : stm32h7xx_hal_ltdc.h
  • LTDC_HSPOLARITY_AH : stm32h7xx_hal_ltdc.h
  • LTDC_HSPOLARITY_AL : stm32h7xx_hal_ltdc.h
  • LTDC_IT_FU : stm32h7xx_hal_ltdc.h
  • LTDC_IT_LI : stm32h7xx_hal_ltdc.h
  • LTDC_IT_RR : stm32h7xx_hal_ltdc.h
  • LTDC_IT_TE : stm32h7xx_hal_ltdc.h
  • LTDC_LAYER : stm32h7xx_hal_ltdc.h
  • LTDC_LAYER_1 : stm32h7xx_hal_ltdc.h
  • LTDC_LAYER_2 : stm32h7xx_hal_ltdc.h
  • LTDC_LINE_NUMBER : stm32h7xx_hal_ltdc.h
  • LTDC_PCPOLARITY_IIPC : stm32h7xx_hal_ltdc.h
  • LTDC_PCPOLARITY_IPC : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_AL44 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_AL88 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_ARGB1555 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_ARGB4444 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_ARGB8888 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_L8 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_RGB565 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_RGB888 : stm32h7xx_hal_ltdc.h
  • LTDC_RELOAD_IMMEDIATE : stm32h7xx_hal_ltdc.h
  • LTDC_RELOAD_VERTICAL_BLANKING : stm32h7xx_hal_ltdc.h
  • LTDC_SetConfig() : stm32h7xx_hal_ltdc.c
  • LTDC_STARTPOSITION : stm32h7xx_hal_ltdc.h
  • LTDC_STOPPOSITION : stm32h7xx_hal_ltdc.h
  • LTDC_VERTICALSYNC : stm32h7xx_hal_ltdc.h
  • LTDC_VSPOLARITY_AH : stm32h7xx_hal_ltdc.h
  • LTDC_VSPOLARITY_AL : stm32h7xx_hal_ltdc.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
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  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- m -

  • MAX_DMA2D_LAYER : stm32h7xx_hal_dma2d.h
  • MAX_HRTIM_TIMER : stm32h7xx_hal_hrtim.h
  • MAX_LAYER : stm32h7xx_hal_ltdc.h
  • MAX_NBYTE_SIZE : stm32h7xx_hal_i2c.c , stm32h7xx_hal_smbus.c
  • MC_ADDRESS : stm32h7xx_hal_nor.h
  • MCO1_GPIO_PORT : stm32h7xx_hal_rcc.c
  • MCO1_PIN : stm32h7xx_hal_rcc.c
  • MCO2_GPIO_PORT : stm32h7xx_hal_rcc.c
  • MCO2_PIN : stm32h7xx_hal_rcc.c
  • MDIOS_ALL_ERRORS_FLAG : stm32h7xx_hal_mdios.c
  • MDIOS_ALL_REG_FLAG : stm32h7xx_hal_mdios.c
  • MDIOS_ALLREG_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_DIN_BASE_ADDR : stm32h7xx_hal_mdios.c
  • MDIOS_DOUT_BASE_ADDR : stm32h7xx_hal_mdios.c
  • MDIOS_IT_ERROR : stm32h7xx_hal_mdios.h
  • MDIOS_IT_READ : stm32h7xx_hal_mdios.h
  • MDIOS_IT_WRITE : stm32h7xx_hal_mdios.h
  • MDIOS_PORT_ADDRESS_SHIFT : stm32h7xx_hal_mdios.c
  • MDIOS_PREAMBLE_CHECK_DISABLE : stm32h7xx_hal_mdios.h
  • MDIOS_PREAMBLE_CHECK_ENABLE : stm32h7xx_hal_mdios.h
  • MDIOS_PREAMBLE_ERROR_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG0 : stm32h7xx_hal_mdios.h
  • MDIOS_REG0_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG1 : stm32h7xx_hal_mdios.h
  • MDIOS_REG10 : stm32h7xx_hal_mdios.h
  • MDIOS_REG10_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG11 : stm32h7xx_hal_mdios.h
  • MDIOS_REG11_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG12 : stm32h7xx_hal_mdios.h
  • MDIOS_REG12_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG13 : stm32h7xx_hal_mdios.h
  • MDIOS_REG13_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG14 : stm32h7xx_hal_mdios.h
  • MDIOS_REG14_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG15 : stm32h7xx_hal_mdios.h
  • MDIOS_REG15_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG16 : stm32h7xx_hal_mdios.h
  • MDIOS_REG16_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG17 : stm32h7xx_hal_mdios.h
  • MDIOS_REG17_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG18 : stm32h7xx_hal_mdios.h
  • MDIOS_REG18_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG19 : stm32h7xx_hal_mdios.h
  • MDIOS_REG19_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG1_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG2 : stm32h7xx_hal_mdios.h
  • MDIOS_REG20 : stm32h7xx_hal_mdios.h
  • MDIOS_REG20_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG21 : stm32h7xx_hal_mdios.h
  • MDIOS_REG21_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG22 : stm32h7xx_hal_mdios.h
  • MDIOS_REG22_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG23 : stm32h7xx_hal_mdios.h
  • MDIOS_REG23_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG24 : stm32h7xx_hal_mdios.h
  • MDIOS_REG24_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG25 : stm32h7xx_hal_mdios.h
  • MDIOS_REG25_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG26 : stm32h7xx_hal_mdios.h
  • MDIOS_REG26_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG27 : stm32h7xx_hal_mdios.h
  • MDIOS_REG27_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG28 : stm32h7xx_hal_mdios.h
  • MDIOS_REG28_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG29 : stm32h7xx_hal_mdios.h
  • MDIOS_REG29_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG2_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG3 : stm32h7xx_hal_mdios.h
  • MDIOS_REG30 : stm32h7xx_hal_mdios.h
  • MDIOS_REG30_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG31 : stm32h7xx_hal_mdios.h
  • MDIOS_REG31_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG3_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG4 : stm32h7xx_hal_mdios.h
  • MDIOS_REG4_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG5 : stm32h7xx_hal_mdios.h
  • MDIOS_REG5_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG6 : stm32h7xx_hal_mdios.h
  • MDIOS_REG6_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG7 : stm32h7xx_hal_mdios.h
  • MDIOS_REG7_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG8 : stm32h7xx_hal_mdios.h
  • MDIOS_REG8_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG9 : stm32h7xx_hal_mdios.h
  • MDIOS_REG9_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_START_ERROR_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_TURNAROUND_ERROR_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_WAKEUP_EXTI_LINE : stm32h7xx_hal_mdios.h
  • MDMA_BLOCK_TRANSFER : stm32h7xx_hal_mdma.h
  • MDMA_BUFFER_TRANSFER : stm32h7xx_hal_mdma.h
  • MDMA_DATAALIGN_LEFT : stm32h7xx_hal_mdma.h
  • MDMA_DATAALIGN_PACKENABLE : stm32h7xx_hal_mdma.h
  • MDMA_DATAALIGN_RIGHT : stm32h7xx_hal_mdma.h
  • MDMA_DATAALIGN_RIGHT_SIGNED : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_128BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_16BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_2BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_32BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_4BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_64BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_8BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_SINGLE : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DATASIZE_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DATASIZE_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DATASIZE_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DATASIZE_WORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DEC_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DEC_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DEC_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DEC_WORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_INC_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_DEST_INC_DISABLE : stm32h7xx_hal_mdma.h
  • MDMA_DEST_INC_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_INC_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_INC_WORD : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_BFTC : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_BRT : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_BT : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_CRQA : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_CTC : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_TE : stm32h7xx_hal_mdma.h
  • MDMA_FULL_TRANSFER : stm32h7xx_hal_mdma.h
  • MDMA_HandleTypeDef : stm32h7xx_hal_mdma.h
  • MDMA_Init() : stm32h7xx_hal_mdma.c
  • MDMA_IT_BFTC : stm32h7xx_hal_mdma.h
  • MDMA_IT_BRT : stm32h7xx_hal_mdma.h
  • MDMA_IT_BT : stm32h7xx_hal_mdma.h
  • MDMA_IT_CTC : stm32h7xx_hal_mdma.h
  • MDMA_IT_TE : stm32h7xx_hal_mdma.h
  • MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE : stm32h7xx_hal_mdma.h
  • MDMA_LITTLE_ENDIANNESS_PRESERVE : stm32h7xx_hal_mdma.h
  • MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE : stm32h7xx_hal_mdma.h
  • MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE : stm32h7xx_hal_mdma.h
  • MDMA_PRIORITY_HIGH : stm32h7xx_hal_mdma.h
  • MDMA_PRIORITY_LOW : stm32h7xx_hal_mdma.h
  • MDMA_PRIORITY_MEDIUM : stm32h7xx_hal_mdma.h
  • MDMA_PRIORITY_VERY_HIGH : stm32h7xx_hal_mdma.h
  • MDMA_REPEAT_BLOCK_TRANSFER : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream0_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream1_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream2_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream3_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream4_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream5_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream6_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream7_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream0_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream1_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream2_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream3_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream4_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream5_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream6_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream7_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2D_CLUT_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2D_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2D_TW : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_JPEG_END_CONVERSION : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_JPEG_INFIFO_NF : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_JPEG_INFIFO_TH : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_JPEG_OUTFIFO_NE : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_JPEG_OUTFIFO_TH : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_LTDC_LINE_IT : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_QUADSPI_FIFO_TH : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_QUADSPI_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_SDMMC1_END_DATA : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_SW : stm32h7xx_hal_mdma.h
  • MDMA_SetConfig() : stm32h7xx_hal_mdma.c
  • MDMA_SOURCE_BURST_128BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_16BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_2BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_32BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_4BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_64BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_8BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_SINGLE : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DATASIZE_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DATASIZE_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DATASIZE_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DATASIZE_WORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DEC_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DEC_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DEC_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DEC_WORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_INC_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_SRC_INC_DISABLE : stm32h7xx_hal_mdma.h
  • MDMA_SRC_INC_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_INC_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_INC_WORD : stm32h7xx_hal_mdma.h
  • MEMORY0 : stm32h7xx_hal_dma_ex.h
  • MEMORY1 : stm32h7xx_hal_dma_ex.h
  • MMC_CONTEXT_DMA : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_IT : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_NONE : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_READ_MULTIPLE_BLOCK : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_READ_SINGLE_BLOCK : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_WRITE_MULTIPLE_BLOCK : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_WRITE_SINGLE_BLOCK : stm32h7xx_hal_mmc.h
  • MMC_DMA_BUFFER0 : stm32h7xx_hal_mmc_ex.h
  • MMC_DMA_BUFFER1 : stm32h7xx_hal_mmc_ex.h
  • MMC_DUAL_VOLTAGE_RANGE : stm32h7xx_hal_mmc.h
  • MMC_HIGH_CAPACITY_CARD : stm32h7xx_hal_mmc.h
  • MMC_HIGH_VOLTAGE_RANGE : stm32h7xx_hal_mmc.h
  • MMC_InitCard() : stm32h7xx_hal_mmc.c
  • MMC_InitTypeDef : stm32h7xx_hal_mmc.h
  • MMC_INVALID_VOLTAGE_RANGE : stm32h7xx_hal_mmc.h
  • MMC_LOW_CAPACITY_CARD : stm32h7xx_hal_mmc.h
  • MMC_PowerOFF() : stm32h7xx_hal_mmc.c
  • MMC_PowerON() : stm32h7xx_hal_mmc.c
  • MMC_Read_IT() : stm32h7xx_hal_mmc.c
  • MMC_ReadExtCSD() : stm32h7xx_hal_mmc.c
  • MMC_SendStatus() : stm32h7xx_hal_mmc.c
  • MMC_TypeDef : stm32h7xx_hal_mmc.h
  • MMC_Write_IT() : stm32h7xx_hal_mmc.c
  • MPU_ACCESS_BUFFERABLE : stm32h7xx_hal_cortex.h
  • MPU_ACCESS_CACHEABLE : stm32h7xx_hal_cortex.h
  • MPU_ACCESS_NOT_BUFFERABLE : stm32h7xx_hal_cortex.h
  • MPU_ACCESS_NOT_CACHEABLE : stm32h7xx_hal_cortex.h
  • MPU_ACCESS_NOT_SHAREABLE : stm32h7xx_hal_cortex.h
  • MPU_ACCESS_SHAREABLE : stm32h7xx_hal_cortex.h
  • MPU_HARDFAULT_NMI : stm32h7xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF : stm32h7xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF_NONE : stm32h7xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_DISABLE : stm32h7xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_ENABLE : stm32h7xx_hal_cortex.h
  • MPU_PRIVILEGED_DEFAULT : stm32h7xx_hal_cortex.h
  • MPU_REGION_DISABLE : stm32h7xx_hal_cortex.h
  • MPU_REGION_ENABLE : stm32h7xx_hal_cortex.h
  • MPU_REGION_FULL_ACCESS : stm32h7xx_hal_cortex.h
  • MPU_REGION_NO_ACCESS : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER0 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER1 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER2 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER3 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER4 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER5 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER6 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER7 : stm32h7xx_hal_cortex.h
  • MPU_REGION_PRIV_RO : stm32h7xx_hal_cortex.h
  • MPU_REGION_PRIV_RO_URO : stm32h7xx_hal_cortex.h
  • MPU_REGION_PRIV_RW : stm32h7xx_hal_cortex.h
  • MPU_REGION_PRIV_RW_URO : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_128B : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_128KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_128MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_16KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_16MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_1GB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_1KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_1MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_256B : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_256KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_256MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_2GB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_2KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_2MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_32B : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_32KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_32MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_4GB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_4KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_4MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_512B : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_512KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_512MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_64B : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_64KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_64MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_8KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_8MB : stm32h7xx_hal_cortex.h
  • MPU_TEX_LEVEL0 : stm32h7xx_hal_cortex.h
  • MPU_TEX_LEVEL1 : stm32h7xx_hal_cortex.h
  • MPU_TEX_LEVEL2 : stm32h7xx_hal_cortex.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- n -

  • NAND_BUSY : stm32h7xx_hal_nand.h
  • NAND_CMD_AREA_A : stm32h7xx_hal_nand.h
  • NAND_CMD_AREA_B : stm32h7xx_hal_nand.h
  • NAND_CMD_AREA_C : stm32h7xx_hal_nand.h
  • NAND_CMD_AREA_TRUE1 : stm32h7xx_hal_nand.h
  • NAND_CMD_ERASE0 : stm32h7xx_hal_nand.h
  • NAND_CMD_ERASE1 : stm32h7xx_hal_nand.h
  • NAND_CMD_LOCK_STATUS : stm32h7xx_hal_nand.h
  • NAND_CMD_READID : stm32h7xx_hal_nand.h
  • NAND_CMD_RESET : stm32h7xx_hal_nand.h
  • NAND_CMD_STATUS : stm32h7xx_hal_nand.h
  • NAND_CMD_WRITE0 : stm32h7xx_hal_nand.h
  • NAND_CMD_WRITE_TRUE1 : stm32h7xx_hal_nand.h
  • NAND_DEVICE : stm32h7xx_hal_nand.h
  • NAND_ERROR : stm32h7xx_hal_nand.h
  • NAND_INVALID_ADDRESS : stm32h7xx_hal_nand.h
  • NAND_READY : stm32h7xx_hal_nand.h
  • NAND_TIMEOUT_ERROR : stm32h7xx_hal_nand.h
  • NAND_VALID_ADDRESS : stm32h7xx_hal_nand.h
  • NAND_WRITE_TIMEOUT : stm32h7xx_hal_nand.h
  • NOR_ADDR_SHIFT : stm32h7xx_hal_nor.h
  • NOR_CMD_ADDRESS_FIFTH : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_FIRST : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_FIRST_CFI : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_FOURTH : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_SECOND : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_SIXTH : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_THIRD : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_AUTO_SELECT : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_BLOCK_ERASE : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_BUFFER_AND_PROG : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_CFI : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_ERASE : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_FIRST : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_PROGRAM : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_READ_RESET : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_SECOND : stm32h7xx_hal_nor.c
  • NOR_MASK_STATUS_DQ5 : stm32h7xx_hal_nor.c
  • NOR_MASK_STATUS_DQ6 : stm32h7xx_hal_nor.c
  • NOR_MEMORY_16B : stm32h7xx_hal_nor.h
  • NOR_MEMORY_8B : stm32h7xx_hal_nor.h
  • NOR_MEMORY_ADRESS1 : stm32h7xx_hal_nor.h
  • NOR_MEMORY_ADRESS2 : stm32h7xx_hal_nor.h
  • NOR_MEMORY_ADRESS3 : stm32h7xx_hal_nor.h
  • NOR_MEMORY_ADRESS4 : stm32h7xx_hal_nor.h
  • NOR_TMEOUT : stm32h7xx_hal_nor.h
  • NOR_WRITE : stm32h7xx_hal_nor.h
  • NVIC_PRIORITYGROUP_0 : stm32h7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_1 : stm32h7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_2 : stm32h7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_3 : stm32h7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_4 : stm32h7xx_hal_cortex.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- o -

  • OB_BOOT_ADD0 : stm32h7xx_hal_flash_ex.h
  • OB_BOOT_ADD1 : stm32h7xx_hal_flash_ex.h
  • OB_BOOT_ADD_BOTH : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_AXIM_FLASH : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_DTCM_RAM : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_ITCM_FLASH : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_ITCM_RAM : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_SRAM1 : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_SRAM2 : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_SYSTEM : stm32h7xx_hal_flash_ex.h
  • OB_BOR_LEVEL1 : stm32h7xx_hal_flash_ex.h
  • OB_BOR_LEVEL2 : stm32h7xx_hal_flash_ex.h
  • OB_BOR_LEVEL3 : stm32h7xx_hal_flash_ex.h
  • OB_BOR_OFF : stm32h7xx_hal_flash_ex.h
  • OB_IOHSLV_DISABLE : stm32h7xx_hal_flash_ex.h
  • OB_IOHSLV_ENABLE : stm32h7xx_hal_flash_ex.h
  • OB_IWDG1_HW : stm32h7xx_hal_flash_ex.h
  • OB_IWDG1_SW : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_HW : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_STDBY_ACTIVE : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_STDBY_FREEZE : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_STOP_ACTIVE : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_STOP_FREEZE : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_SW : stm32h7xx_hal_flash_ex.h
  • OB_PCROP_RDP_ERASE : stm32h7xx_hal_flash_ex.h
  • OB_PCROP_RDP_NOT_ERASE : stm32h7xx_hal_flash_ex.h
  • OB_RDP_LEVEL_0 : stm32h7xx_hal_flash_ex.h
  • OB_RDP_LEVEL_1 : stm32h7xx_hal_flash_ex.h
  • OB_RDP_LEVEL_2 : stm32h7xx_hal_flash_ex.h
  • OB_SECURE_RDP_ERASE : stm32h7xx_hal_flash_ex.h
  • OB_SECURE_RDP_NOT_ERASE : stm32h7xx_hal_flash_ex.h
  • OB_SECURITY_DISABLE : stm32h7xx_hal_flash_ex.h
  • OB_SECURITY_ENABLE : stm32h7xx_hal_flash_ex.h
  • OB_STDBY_NO_RST : stm32h7xx_hal_flash_ex.h
  • OB_STDBY_NO_RST_D1 : stm32h7xx_hal_flash_ex.h
  • OB_STDBY_RST : stm32h7xx_hal_flash_ex.h
  • OB_STDBY_RST_D1 : stm32h7xx_hal_flash_ex.h
  • OB_STOP_NO_RST : stm32h7xx_hal_flash_ex.h
  • OB_STOP_NO_RST_D1 : stm32h7xx_hal_flash_ex.h
  • OB_STOP_RST : stm32h7xx_hal_flash_ex.h
  • OB_STOP_RST_D1 : stm32h7xx_hal_flash_ex.h
  • OB_SWAP_BANK_DISABLE : stm32h7xx_hal_flash_ex.h
  • OB_SWAP_BANK_ENABLE : stm32h7xx_hal_flash_ex.h
  • OB_USER_IOHSLV : stm32h7xx_hal_flash_ex.h
  • OB_USER_IWDG1_SW : stm32h7xx_hal_flash_ex.h
  • OB_USER_IWDG_STDBY : stm32h7xx_hal_flash_ex.h
  • OB_USER_IWDG_STOP : stm32h7xx_hal_flash_ex.h
  • OB_USER_NRST_STDBY_D1 : stm32h7xx_hal_flash_ex.h
  • OB_USER_NRST_STOP_D1 : stm32h7xx_hal_flash_ex.h
  • OB_USER_SECURITY : stm32h7xx_hal_flash_ex.h
  • OB_USER_ST_RAM_SIZE : stm32h7xx_hal_flash_ex.h
  • OB_USER_SWAP_BANK : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_0 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_1 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_2 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_3 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_4 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_5 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_6 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_7 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_All : stm32h7xx_hal_flash_ex.h
  • OB_WRPSTATE_DISABLE : stm32h7xx_hal_flash_ex.h
  • OB_WRPSTATE_ENABLE : stm32h7xx_hal_flash_ex.h
  • OB_WWDG_HW : stm32h7xx_hal_flash_ex.h
  • OB_WWDG_SW : stm32h7xx_hal_flash_ex.h
  • OPAMP_CSR_INIT_MASK_FOLLOWER : stm32h7xx_hal_opamp.c
  • OPAMP_CSR_INIT_MASK_PGA : stm32h7xx_hal_opamp.c
  • OPAMP_CSR_INIT_MASK_STANDALONE : stm32h7xx_hal_opamp.c
  • OPAMP_CSR_RESET_BITS : stm32h7xx_hal_opamp.c
  • OPAMP_CSR_RESET_VALUE : stm32h7xx_hal_opamp.c
  • OPAMP_FACTORYTRIMMING_DUMMY : stm32h7xx_hal_opamp.h
  • OPAMP_FACTORYTRIMMING_N : stm32h7xx_hal_opamp.h
  • OPAMP_FACTORYTRIMMING_P : stm32h7xx_hal_opamp.h
  • OPAMP_FOLLOWER_MODE : stm32h7xx_hal_opamp.h
  • OPAMP_INPUT_NONINVERTING : stm32h7xx_hal_opamp.h
  • OPAMP_INVERTINGINPUT_IO0 : stm32h7xx_hal_opamp.h
  • OPAMP_INVERTINGINPUT_IO1 : stm32h7xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_DAC_CH : stm32h7xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_IO0 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_NO : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_GAIN_16_OR_MINUS_15 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_GAIN_2_OR_MINUS_1 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_GAIN_4_OR_MINUS_3 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_GAIN_8_OR_MINUS_7 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_MODE : stm32h7xx_hal_opamp.h
  • OPAMP_POWERMODE_HIGHSPEED : stm32h7xx_hal_opamp.h
  • OPAMP_POWERMODE_NORMAL : stm32h7xx_hal_opamp.h
  • OPAMP_STANDALONE_MODE : stm32h7xx_hal_opamp.h
  • OPAMP_TRIMMING_DELAY : stm32h7xx_hal_opamp.h
  • OPAMP_TRIMMING_FACTORY : stm32h7xx_hal_opamp.h
  • OPAMP_TRIMMING_USER : stm32h7xx_hal_opamp.h
  • OPAMP_VREF_10VDDA : stm32h7xx_hal_opamp.h
  • OPAMP_VREF_3VDDA : stm32h7xx_hal_opamp.h
  • OPAMP_VREF_50VDDA : stm32h7xx_hal_opamp.h
  • OPAMP_VREF_90VDDA : stm32h7xx_hal_opamp.h
  • OPTIONBYTE_BOOTADD : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_BOR : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_PCROP : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_RDP : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_SECURE_AREA : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_USER : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_WRP : stm32h7xx_hal_flash_ex.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- p -

  • PCD_BCD_CHARGING_DOWNSTREAM_PORT : stm32h7xx_hal_pcd_ex.h
  • PCD_BCD_CONTACT_DETECTION : stm32h7xx_hal_pcd_ex.h
  • PCD_BCD_DEDICATED_CHARGING_PORT : stm32h7xx_hal_pcd_ex.h
  • PCD_BCD_DISCOVERY_COMPLETED : stm32h7xx_hal_pcd_ex.h
  • PCD_BCD_ERROR : stm32h7xx_hal_pcd_ex.h
  • PCD_BCD_MsgTypeDef : stm32h7xx_hal_pcd_ex.h
  • PCD_BCD_STD_DOWNSTREAM_PORT : stm32h7xx_hal_pcd_ex.h
  • PCD_EPTypeDef : stm32h7xx_hal_pcd.h
  • PCD_InitTypeDef : stm32h7xx_hal_pcd.h
  • PCD_LPM_L0_ACTIVE : stm32h7xx_hal_pcd_ex.h
  • PCD_LPM_L1_ACTIVE : stm32h7xx_hal_pcd_ex.h
  • PCD_LPM_MsgTypeDef : stm32h7xx_hal_pcd_ex.h
  • PCD_LPM_StateTypeDef : stm32h7xx_hal_pcd.h
  • PCD_MAX : stm32h7xx_hal_pcd.c
  • PCD_MIN : stm32h7xx_hal_pcd.c
  • PCD_PHY_EMBEDDED : stm32h7xx_hal_pcd.h
  • PCD_PHY_ULPI : stm32h7xx_hal_pcd.h
  • PCD_SPEED_FULL : stm32h7xx_hal_pcd.h
  • PCD_SPEED_HIGH : stm32h7xx_hal_pcd.h
  • PCD_SPEED_HIGH_IN_FULL : stm32h7xx_hal_pcd.h
  • PCD_StateTypeDef : stm32h7xx_hal_pcd.h
  • PCD_TypeDef : stm32h7xx_hal_pcd.h
  • PCD_WriteEmptyTxFifo() : stm32h7xx_hal_pcd.c
  • pFlash : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash_ex.c
  • PLL2_TIMEOUT_VALUE : stm32h7xx_hal_rcc_ex.c
  • PLL3_TIMEOUT_VALUE : stm32h7xx_hal_rcc_ex.c
  • PLL_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h , stm32h7xx_hal_rcc_ex.c
  • PVD_FALLING_EDGE : stm32h7xx_hal_pwr.c
  • PVD_MODE_EVT : stm32h7xx_hal_pwr.c
  • PVD_MODE_IT : stm32h7xx_hal_pwr.c
  • PVD_RISING_EDGE : stm32h7xx_hal_pwr.c
  • PVD_RISING_FALLING_EDGE : stm32h7xx_hal_pwr.c
  • PWR_AVD_MODE_EVENT_FALLING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_EVENT_RISING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_EVENT_RISING_FALLING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_IT_FALLING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_IT_RISING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_IT_RISING_FALLING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_NORMAL : stm32h7xx_hal_pwr_ex.h
  • PWR_AVDLEVEL_0 : stm32h7xx_hal_pwr_ex.h
  • PWR_AVDLEVEL_1 : stm32h7xx_hal_pwr_ex.h
  • PWR_AVDLEVEL_2 : stm32h7xx_hal_pwr_ex.h
  • PWR_AVDLEVEL_3 : stm32h7xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_1_5 : stm32h7xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_5 : stm32h7xx_hal_pwr_ex.h
  • PWR_CPU_FLAGS : stm32h7xx_hal_pwr_ex.h
  • PWR_D1_DOMAIN : stm32h7xx_hal_pwr_ex.h
  • PWR_D2_DOMAIN : stm32h7xx_hal_pwr_ex.h
  • PWR_D3_DOMAIN : stm32h7xx_hal_pwr_ex.h
  • PWR_D3_DOMAIN_RUN : stm32h7xx_hal_pwr_ex.h
  • PWR_D3_DOMAIN_STOP : stm32h7xx_hal_pwr_ex.h
  • PWR_EWUP_MASK : stm32h7xx_hal_pwr.h
  • PWR_EXTERNAL_SOURCE_SUPPLY : stm32h7xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_AVD : stm32h7xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVD : stm32h7xx_hal_pwr.h
  • PWR_EXTI_WAKEUP_PINS_MASK : stm32h7xx_hal_pwr_ex.h
  • PWR_FLAG_ACTVOS : stm32h7xx_hal_pwr.h
  • PWR_FLAG_ACTVOSRDY : stm32h7xx_hal_pwr.h
  • PWR_FLAG_AVDO : stm32h7xx_hal_pwr.h
  • PWR_FLAG_BRR : stm32h7xx_hal_pwr.h
  • PWR_FLAG_PVDO : stm32h7xx_hal_pwr.h
  • PWR_FLAG_SB : stm32h7xx_hal_pwr.h
  • PWR_FLAG_SB_D1 : stm32h7xx_hal_pwr.h
  • PWR_FLAG_SB_D2 : stm32h7xx_hal_pwr.h
  • PWR_FLAG_SCUEN : stm32h7xx_hal_pwr.h
  • PWR_FLAG_SETTING_DELAY_US : stm32h7xx_hal_pwr_ex.c
  • PWR_FLAG_STOP : stm32h7xx_hal_pwr.h
  • PWR_FLAG_VOSRDY : stm32h7xx_hal_pwr.h
  • PWR_LDO_SUPPLY : stm32h7xx_hal_pwr_ex.h
  • PWR_LOWPOWERREGULATOR_ON : stm32h7xx_hal_pwr.h
  • PWR_MAINREGULATOR_ON : stm32h7xx_hal_pwr.h
  • PWR_PIN_NO_PULL : stm32h7xx_hal_pwr_ex.h
  • PWR_PIN_POLARITY_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_PIN_POLARITY_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_PIN_PULL_DOWN : stm32h7xx_hal_pwr_ex.h
  • PWR_PIN_PULL_UP : stm32h7xx_hal_pwr_ex.h
  • PWR_PVD_MODE_EVENT_FALLING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING_FALLING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_IT_FALLING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING_FALLING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_NORMAL : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_0 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_1 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_2 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_3 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_4 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_5 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_6 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_7 : stm32h7xx_hal_pwr.h
  • PWR_REGULATOR_SVOS_SCALE3 : stm32h7xx_hal_pwr_ex.h
  • PWR_REGULATOR_SVOS_SCALE4 : stm32h7xx_hal_pwr_ex.h
  • PWR_REGULATOR_SVOS_SCALE5 : stm32h7xx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE1 : stm32h7xx_hal_pwr.h
  • PWR_REGULATOR_VOLTAGE_SCALE2 : stm32h7xx_hal_pwr.h
  • PWR_REGULATOR_VOLTAGE_SCALE3 : stm32h7xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFE : stm32h7xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFI : stm32h7xx_hal_pwr.h
  • PWR_STOPENTRY_WFE : stm32h7xx_hal_pwr.h
  • PWR_STOPENTRY_WFI : stm32h7xx_hal_pwr.h
  • PWR_SUPPLY_CONFIG_MASK : stm32h7xx_hal_pwr_ex.h
  • PWR_TEMP_ABOVE_HIGH_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_TEMP_BELOW_LOW_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_VBAT_ABOVE_HIGH_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_VBAT_BELOW_LOW_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG1 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG2 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG3 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG4 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG5 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG6 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN6 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN6_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN6_LOW : stm32h7xx_hal_pwr_ex.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
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  • q
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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- q -

  • QSPI_ADDRESS_16_BITS : stm32h7xx_hal_qspi.h
  • QSPI_ADDRESS_1_LINE : stm32h7xx_hal_qspi.h
  • QSPI_ADDRESS_24_BITS : stm32h7xx_hal_qspi.h
  • QSPI_ADDRESS_2_LINES : stm32h7xx_hal_qspi.h
  • QSPI_ADDRESS_32_BITS : stm32h7xx_hal_qspi.h
  • QSPI_ADDRESS_4_LINES : stm32h7xx_hal_qspi.h
  • QSPI_ADDRESS_8_BITS : stm32h7xx_hal_qspi.h
  • QSPI_ADDRESS_NONE : stm32h7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_16_BITS : stm32h7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_1_LINE : stm32h7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_24_BITS : stm32h7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_2_LINES : stm32h7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_32_BITS : stm32h7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_4_LINES : stm32h7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_8_BITS : stm32h7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_NONE : stm32h7xx_hal_qspi.h
  • QSPI_AUTOMATIC_STOP_DISABLE : stm32h7xx_hal_qspi.h
  • QSPI_AUTOMATIC_STOP_ENABLE : stm32h7xx_hal_qspi.h
  • QSPI_CLOCK_MODE_0 : stm32h7xx_hal_qspi.h
  • QSPI_CLOCK_MODE_3 : stm32h7xx_hal_qspi.h
  • QSPI_Config() : stm32h7xx_hal_qspi.c
  • QSPI_CS_HIGH_TIME_1_CYCLE : stm32h7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_2_CYCLE : stm32h7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_3_CYCLE : stm32h7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_4_CYCLE : stm32h7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_5_CYCLE : stm32h7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_6_CYCLE : stm32h7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_7_CYCLE : stm32h7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_8_CYCLE : stm32h7xx_hal_qspi.h
  • QSPI_DATA_1_LINE : stm32h7xx_hal_qspi.h
  • QSPI_DATA_2_LINES : stm32h7xx_hal_qspi.h
  • QSPI_DATA_4_LINES : stm32h7xx_hal_qspi.h
  • QSPI_DATA_NONE : stm32h7xx_hal_qspi.h
  • QSPI_DDR_HHC_ANALOG_DELAY : stm32h7xx_hal_qspi.h
  • QSPI_DDR_HHC_HALF_CLK_DELAY : stm32h7xx_hal_qspi.h
  • QSPI_DDR_MODE_DISABLE : stm32h7xx_hal_qspi.h
  • QSPI_DDR_MODE_ENABLE : stm32h7xx_hal_qspi.h
  • QSPI_DMAAbortCplt() : stm32h7xx_hal_qspi.c
  • QSPI_DMAError() : stm32h7xx_hal_qspi.c
  • QSPI_DMARxCplt() : stm32h7xx_hal_qspi.c
  • QSPI_DMATxCplt() : stm32h7xx_hal_qspi.c
  • QSPI_DUALFLASH_DISABLE : stm32h7xx_hal_qspi.h
  • QSPI_DUALFLASH_ENABLE : stm32h7xx_hal_qspi.h
  • QSPI_FLAG_BUSY : stm32h7xx_hal_qspi.h
  • QSPI_FLAG_FT : stm32h7xx_hal_qspi.h
  • QSPI_FLAG_SM : stm32h7xx_hal_qspi.h
  • QSPI_FLAG_TC : stm32h7xx_hal_qspi.h
  • QSPI_FLAG_TE : stm32h7xx_hal_qspi.h
  • QSPI_FLAG_TO : stm32h7xx_hal_qspi.h
  • QSPI_FLASH_ID_1 : stm32h7xx_hal_qspi.h
  • QSPI_FLASH_ID_2 : stm32h7xx_hal_qspi.h
  • QSPI_FUNCTIONAL_MODE_AUTO_POLLING : stm32h7xx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_INDIRECT_READ : stm32h7xx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE : stm32h7xx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED : stm32h7xx_hal_qspi.c
  • QSPI_INSTRUCTION_1_LINE : stm32h7xx_hal_qspi.h
  • QSPI_INSTRUCTION_2_LINES : stm32h7xx_hal_qspi.h
  • QSPI_INSTRUCTION_4_LINES : stm32h7xx_hal_qspi.h
  • QSPI_INSTRUCTION_NONE : stm32h7xx_hal_qspi.h
  • QSPI_IT_FT : stm32h7xx_hal_qspi.h
  • QSPI_IT_SM : stm32h7xx_hal_qspi.h
  • QSPI_IT_TC : stm32h7xx_hal_qspi.h
  • QSPI_IT_TE : stm32h7xx_hal_qspi.h
  • QSPI_IT_TO : stm32h7xx_hal_qspi.h
  • QSPI_MATCH_MODE_AND : stm32h7xx_hal_qspi.h
  • QSPI_MATCH_MODE_OR : stm32h7xx_hal_qspi.h
  • QSPI_SAMPLE_SHIFTING_HALFCYCLE : stm32h7xx_hal_qspi.h
  • QSPI_SAMPLE_SHIFTING_NONE : stm32h7xx_hal_qspi.h
  • QSPI_SIOO_INST_EVERY_CMD : stm32h7xx_hal_qspi.h
  • QSPI_SIOO_INST_ONLY_FIRST_CMD : stm32h7xx_hal_qspi.h
  • QSPI_TIMEOUT_COUNTER_DISABLE : stm32h7xx_hal_qspi.h
  • QSPI_TIMEOUT_COUNTER_ENABLE : stm32h7xx_hal_qspi.h
  • QSPI_WaitFlagStateUntilTimeout() : stm32h7xx_hal_qspi.c
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- r -

  • RCC_ADCCLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_APB1_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_APB1_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_APB1_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_APB1_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_APB1_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_APB2_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_APB2_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_APB2_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_APB2_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_APB2_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_APB3_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_APB3_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_APB3_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_APB3_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_APB3_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_APB4_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_APB4_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_APB4_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_APB4_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_APB4_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_CECCLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_CECCLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_CECCLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_CLKPSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_CLKPSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_CLKPSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_CLOCKTYPE_D1PCLK1 : stm32h7xx_hal_rcc.h
  • RCC_CLOCKTYPE_D3PCLK1 : stm32h7xx_hal_rcc.h
  • RCC_CLOCKTYPE_HCLK : stm32h7xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK1 : stm32h7xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK2 : stm32h7xx_hal_rcc.h
  • RCC_CLOCKTYPE_SYSCLK : stm32h7xx_hal_rcc.h
  • RCC_CRS_ERRORLIMIT_DEFAULT : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ERR : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ERROR_MASK : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ESYNC : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCERR : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCMISS : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCOK : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCWARN : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_TRIMOVF : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FREQERRORDIR_DOWN : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FREQERRORDIR_UP : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_HSI48CALIBRATION_DEFAULT : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_ERR : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_ERROR_MASK : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_ESYNC : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCERR : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCMISS : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCOK : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCWARN : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_TRIMOVF : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_NONE : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_RELOADVALUE_DEFAULT : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV1 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV128 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV16 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV2 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV32 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV4 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV64 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV8 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_POLARITY_FALLING : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_POLARITY_RISING : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_USB1 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_USB2 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNCERR : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNCMISS : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNCOK : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNCWARN : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_TIMEOUT : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_TRIMOVF : stm32h7xx_hal_rcc_ex.h
  • RCC_CSI_OFF : stm32h7xx_hal_rcc.h
  • RCC_CSI_ON : stm32h7xx_hal_rcc.h
  • RCC_CSICALIBRATION_DEFAULT : stm32h7xx_hal_rcc.h
  • RCC_DBP_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • RCC_DFSDM1CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_DFSDM1CLKSOURCE_SYS : stm32h7xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_FLAG_BORRST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_CPURST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_CSIRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_D1CKRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_D1RST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_D2CKRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_D2RST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_HSERDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_HSI48RDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_HSIDIV : stm32h7xx_hal_rcc.h
  • RCC_FLAG_HSIRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_IWDG1RST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_LPWR1RST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_LPWR2RST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_LSERDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_LSIRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_MASK : stm32h7xx_hal_rcc.h
  • RCC_FLAG_PINRST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_PLL2RDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_PLL3RDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_PLLRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_PORRST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_RMVF : stm32h7xx_hal_rcc.h
  • RCC_FLAG_SFTRST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_WWDG1RST : stm32h7xx_hal_rcc.h
  • RCC_FMCCLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_FMCCLKSOURCE_D1HCLK : stm32h7xx_hal_rcc_ex.h
  • RCC_FMCCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_FMCCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_GET_PLL_OSCSOURCE : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV128 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV256 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV512 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV64 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_HRTIM1CLK_CPUCLK : stm32h7xx_hal_rcc_ex.h
  • RCC_HRTIM1CLK_TIMCLK : stm32h7xx_hal_rcc_ex.h
  • RCC_HSE_BYPASS : stm32h7xx_hal_rcc.h
  • RCC_HSE_OFF : stm32h7xx_hal_rcc.h
  • RCC_HSE_ON : stm32h7xx_hal_rcc.h
  • RCC_HSI48_OFF : stm32h7xx_hal_rcc.h
  • RCC_HSI48_ON : stm32h7xx_hal_rcc.h
  • RCC_HSI_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_HSI_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_HSI_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_HSI_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_HSI_OFF : stm32h7xx_hal_rcc.h
  • RCC_HSI_ON : stm32h7xx_hal_rcc.h
  • RCC_HSICALIBRATION_DEFAULT : stm32h7xx_hal_rcc.h
  • RCC_I2C1CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_IT_CSIRDY : stm32h7xx_hal_rcc.h
  • RCC_IT_CSS : stm32h7xx_hal_rcc.h
  • RCC_IT_HSERDY : stm32h7xx_hal_rcc.h
  • RCC_IT_HSI48RDY : stm32h7xx_hal_rcc.h
  • RCC_IT_HSIRDY : stm32h7xx_hal_rcc.h
  • RCC_IT_LSECSS : stm32h7xx_hal_rcc.h
  • RCC_IT_LSERDY : stm32h7xx_hal_rcc.h
  • RCC_IT_LSIRDY : stm32h7xx_hal_rcc.h
  • RCC_IT_PLL2RDY : stm32h7xx_hal_rcc.h
  • RCC_IT_PLL3RDY : stm32h7xx_hal_rcc.h
  • RCC_IT_PLLRDY : stm32h7xx_hal_rcc.h
  • RCC_LPTIM1CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM4CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM4CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM4CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM4CLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM4CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM4CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM5CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM5CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM5CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM5CLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM5CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM5CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LSE_BYPASS : stm32h7xx_hal_rcc.h
  • RCC_LSE_OFF : stm32h7xx_hal_rcc.h
  • RCC_LSE_ON : stm32h7xx_hal_rcc.h
  • RCC_LSE_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • RCC_LSEDRIVE_HIGH : stm32h7xx_hal_rcc.h
  • RCC_LSEDRIVE_LOW : stm32h7xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMHIGH : stm32h7xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMLOW : stm32h7xx_hal_rcc.h
  • RCC_LSI_OFF : stm32h7xx_hal_rcc.h
  • RCC_LSI_ON : stm32h7xx_hal_rcc.h
  • RCC_MCO1 : stm32h7xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSE : stm32h7xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI : stm32h7xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI48 : stm32h7xx_hal_rcc.h
  • RCC_MCO1SOURCE_LSE : stm32h7xx_hal_rcc.h
  • RCC_MCO1SOURCE_PLL1QCLK : stm32h7xx_hal_rcc.h
  • RCC_MCO2 : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_CSICLK : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_HSE : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_LSICLK : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_PLL2PCLK : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_PLLCLK : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_SYSCLK : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_1 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_10 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_11 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_12 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_13 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_14 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_15 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_2 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_3 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_4 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_5 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_6 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_7 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_8 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_9 : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_CSI : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSE : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI48 : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSE : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_NONE : stm32h7xx_hal_rcc.h
  • RCC_PERIPHCLK_ADC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_CEC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_CKPER : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_DFSDM1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_DSI : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_FDCAN : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_FMC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_HRTIM1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C4 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM4 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM5 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPUART1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LTDC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_QSPI : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RNG : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RTC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI4A : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI4B : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SDMMC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPDIFRX : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI4 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI5 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI6 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SWPMI1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_TIM : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART4 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART5 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART7 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART8 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART6 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USB : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL1_DIVP : stm32h7xx_hal_rcc.h
  • RCC_PLL1_DIVQ : stm32h7xx_hal_rcc.h
  • RCC_PLL1_DIVR : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCIRANGE_0 : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCIRANGE_1 : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCIRANGE_2 : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCIRANGE_3 : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCOMEDIUM : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCOWIDE : stm32h7xx_hal_rcc.h
  • RCC_PLL2_DIVP : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2_DIVQ : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2_DIVR : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCIRANGE_0 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCIRANGE_1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCIRANGE_2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCIRANGE_3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCOMEDIUM : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCOWIDE : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3_DIVP : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3_DIVQ : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3_DIVR : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCIRANGE_0 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCIRANGE_1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCIRANGE_2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCIRANGE_3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCOMEDIUM : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCOWIDE : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL_NONE : stm32h7xx_hal_rcc.h
  • RCC_PLL_OFF : stm32h7xx_hal_rcc.h
  • RCC_PLL_ON : stm32h7xx_hal_rcc.h
  • RCC_PLLSOURCE_CSI : stm32h7xx_hal_rcc.h
  • RCC_PLLSOURCE_HSE : stm32h7xx_hal_rcc.h
  • RCC_PLLSOURCE_HSI : stm32h7xx_hal_rcc.h
  • RCC_PLLSOURCE_NONE : stm32h7xx_hal_rcc.h
  • RCC_QSPICLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_QSPICLKSOURCE_D1HCLK : stm32h7xx_hal_rcc_ex.h
  • RCC_QSPICLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_QSPICLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_HSI48 : stm32h7xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_RTCCLKSOURCE_HSE_DIV10 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV11 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV12 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV13 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV14 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV15 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV17 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV18 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV19 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV20 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV21 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV22 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV23 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV24 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV25 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV26 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV27 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV28 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV29 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV3 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV30 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV31 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV32 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV33 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV34 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV35 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV36 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV37 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV38 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV39 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV40 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV41 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV42 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV43 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV44 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV45 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV46 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV47 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV48 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV49 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV5 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV50 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV51 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV52 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV53 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV54 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV55 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV56 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV57 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV58 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV59 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV6 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV60 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV61 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV62 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV63 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV7 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV9 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSE : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSI : stm32h7xx_hal_rcc.h
  • RCC_SAI1CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI3CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI3CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI3CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI3CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI3CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI4ACLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI4ACLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI4ACLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI4ACLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI4ACLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI4BCLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI4BCLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI4BCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI4BCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI4BCLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SDMMCCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SDMMCCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPDIFRXCLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPDIFRXCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SPDIFRXCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPDIFRXCLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI1CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI1CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI1CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI1CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI2CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI2CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI2CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI2CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI2CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI3CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI3CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI3CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI3CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI3CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_STOP_KERWAKEUPCLOCK_CSI : stm32h7xx_hal_rcc.h
  • RCC_STOP_KERWAKEUPCLOCK_HSI : stm32h7xx_hal_rcc.h
  • RCC_STOP_WAKEUPCLOCK_CSI : stm32h7xx_hal_rcc.h
  • RCC_STOP_WAKEUPCLOCK_HSI : stm32h7xx_hal_rcc.h
  • RCC_SWPMI1CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SWPMI1CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SYSCLK_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV128 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV256 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV512 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV64 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_CSI : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSE : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSI : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLCLK : stm32h7xx_hal_rcc.h
  • RCC_TIMPRES_ACTIVATED : stm32h7xx_hal_rcc_ex.h
  • RCC_TIMPRES_DESACTIVATED : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_D2PCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_D2PCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_HSI48 : stm32h7xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_WWDG1 : stm32h7xx_hal_rcc_ex.h
  • RCCEx_PLL2_Config() : stm32h7xx_hal_rcc_ex.c
  • RCCEx_PLL3_Config() : stm32h7xx_hal_rcc_ex.c
  • RISING_EDGE : stm32h7xx_hal_gpio.c
  • RNG_CED_DISABLE : stm32h7xx_hal_rng.h
  • RNG_CED_ENABLE : stm32h7xx_hal_rng.h
  • RNG_FLAG_CECS : stm32h7xx_hal_rng.h
  • RNG_FLAG_DRDY : stm32h7xx_hal_rng.h
  • RNG_FLAG_SECS : stm32h7xx_hal_rng.h
  • RNG_IT_CEI : stm32h7xx_hal_rng.h
  • RNG_IT_DRDY : stm32h7xx_hal_rng.h
  • RNG_IT_SEI : stm32h7xx_hal_rng.h
  • RNG_TIMEOUT_VALUE : stm32h7xx_hal_rng.c
  • RTC_ALARM_A : stm32h7xx_hal_rtc.h
  • RTC_ALARM_B : stm32h7xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_DATE : stm32h7xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_WEEKDAY : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_ALL : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_DATEWEEKDAY : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_HOURS : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_MINUTES : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_NONE : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_SECONDS : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_ALL : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_NONE : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_1 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_10 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_11 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_12 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_13 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_2 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_3 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_4 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_5 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_6 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_7 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_8 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_9 : stm32h7xx_hal_rtc.h
  • RTC_ALL_TAMPER_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_Bcd2ToByte() : stm32h7xx_hal_rtc.c
  • RTC_BKP_DR0 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR1 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR10 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR11 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR12 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR13 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR14 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR15 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR16 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR17 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR18 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR19 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR2 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR20 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR21 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR22 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR23 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR24 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR25 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR26 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR27 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR28 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR29 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR3 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR30 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR31 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR4 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR5 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR6 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR7 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR8 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR9 : stm32h7xx_hal_rtc_ex.h
  • RTC_ByteToBcd2() : stm32h7xx_hal_rtc.c
  • RTC_CALIBOUTPUT_1HZ : stm32h7xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_512HZ : stm32h7xx_hal_rtc_ex.h
  • RTC_DAYLIGHTSAVING_ADD1H : stm32h7xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_NONE : stm32h7xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_SUB1H : stm32h7xx_hal_rtc.h
  • RTC_DR_RESERVED_MASK : stm32h7xx_hal_rtc.h
  • RTC_EnterInitMode() : stm32h7xx_hal_rtc.c
  • RTC_EXTI_LINE_ALARM_EVENT : stm32h7xx_hal_rtc.h
  • RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT : stm32h7xx_hal_rtc_ex.h
  • RTC_EXTI_LINE_WAKEUPTIMER_EVENT : stm32h7xx_hal_rtc_ex.h
  • RTC_FLAG_ALRAF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_ALRAWF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_ALRBF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_ALRBWF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_INITF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_INITS : stm32h7xx_hal_rtc.h
  • RTC_FLAG_ITSF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_RECALPF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_RSF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_SHPF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_TAMP1F : stm32h7xx_hal_rtc.h
  • RTC_FLAG_TAMP2F : stm32h7xx_hal_rtc.h
  • RTC_FLAG_TAMP3F : stm32h7xx_hal_rtc.h
  • RTC_FLAG_TSF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_TSOVF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_WUTF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_WUTWF : stm32h7xx_hal_rtc.h
  • RTC_FORMAT_BCD : stm32h7xx_hal_rtc.h
  • RTC_FORMAT_BIN : stm32h7xx_hal_rtc.h
  • RTC_HOURFORMAT12_AM : stm32h7xx_hal_rtc.h
  • RTC_HOURFORMAT12_PM : stm32h7xx_hal_rtc.h
  • RTC_HOURFORMAT_12 : stm32h7xx_hal_rtc.h
  • RTC_HOURFORMAT_24 : stm32h7xx_hal_rtc.h
  • RTC_INIT_MASK : stm32h7xx_hal_rtc.h
  • RTC_IT_ALRA : stm32h7xx_hal_rtc.h
  • RTC_IT_ALRB : stm32h7xx_hal_rtc.h
  • RTC_IT_TAMP : stm32h7xx_hal_rtc.h
  • RTC_IT_TAMP1 : stm32h7xx_hal_rtc.h
  • RTC_IT_TAMP2 : stm32h7xx_hal_rtc.h
  • RTC_IT_TAMP3 : stm32h7xx_hal_rtc.h
  • RTC_IT_TS : stm32h7xx_hal_rtc.h
  • RTC_IT_WUT : stm32h7xx_hal_rtc.h
  • RTC_MONTH_APRIL : stm32h7xx_hal_rtc.h
  • RTC_MONTH_AUGUST : stm32h7xx_hal_rtc.h
  • RTC_MONTH_DECEMBER : stm32h7xx_hal_rtc.h
  • RTC_MONTH_FEBRUARY : stm32h7xx_hal_rtc.h
  • RTC_MONTH_JANUARY : stm32h7xx_hal_rtc.h
  • RTC_MONTH_JULY : stm32h7xx_hal_rtc.h
  • RTC_MONTH_JUNE : stm32h7xx_hal_rtc.h
  • RTC_MONTH_MARCH : stm32h7xx_hal_rtc.h
  • RTC_MONTH_MAY : stm32h7xx_hal_rtc.h
  • RTC_MONTH_NOVEMBER : stm32h7xx_hal_rtc.h
  • RTC_MONTH_OCTOBER : stm32h7xx_hal_rtc.h
  • RTC_MONTH_SEPTEMBER : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_ALARMA : stm32h7xx_hal_rtc_ex.h
  • RTC_OUTPUT_ALARMB : stm32h7xx_hal_rtc_ex.h
  • RTC_OUTPUT_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_OUTPUT_POLARITY_HIGH : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_LOW : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_REMAP_NONE : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_REMAP_POS1 : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_OPENDRAIN : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_PUSHPULL : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_WAKEUP : stm32h7xx_hal_rtc_ex.h
  • RTC_RSF_MASK : stm32h7xx_hal_rtc.h
  • RTC_SHIFTADD1S_RESET : stm32h7xx_hal_rtc_ex.h
  • RTC_SHIFTADD1S_SET : stm32h7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_16SEC : stm32h7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_32SEC : stm32h7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_8SEC : stm32h7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET : stm32h7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_SET : stm32h7xx_hal_rtc_ex.h
  • RTC_STOREOPERATION_RESET : stm32h7xx_hal_rtc.h
  • RTC_STOREOPERATION_SET : stm32h7xx_hal_rtc.h
  • RTC_TAMPCR_TAMPXE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPCR_TAMPXIE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER1_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER2_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER3_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_1 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_2 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_3 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_2SAMPLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_4SAMPLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_8SAMPLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_1RTCCLK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_2RTCCLK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_4RTCCLK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_8RTCCLK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_FALLINGEDGE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_HIGHLEVEL : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_LOWLEVEL : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_RISINGEDGE : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMEOUT_VALUE : stm32h7xx_hal_rtc.h
  • RTC_TIMESTAMPEDGE_FALLING : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPEDGE_RISING : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_DEFAULT : stm32h7xx_hal_rtc_ex.h
  • RTC_TR_RESERVED_MASK : stm32h7xx_hal_rtc.h
  • RTC_WAKEUPCLOCK_CK_SPRE_16BITS : stm32h7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_CK_SPRE_17BITS : stm32h7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV16 : stm32h7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV2 : stm32h7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV4 : stm32h7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV8 : stm32h7xx_hal_rtc_ex.h
  • RTC_WEEKDAY_FRIDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_MONDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_SATURDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_SUNDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_THURSDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_TUESDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_WEDNESDAY : stm32h7xx_hal_rtc.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- s -

  • SAI_AC97_PROTOCOL : stm32h7xx_hal_sai.h
  • SAI_ALAW_1CPL_COMPANDING : stm32h7xx_hal_sai.h
  • SAI_ALAW_2CPL_COMPANDING : stm32h7xx_hal_sai.h
  • SAI_ASYNCHRONOUS : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_11K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_16K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_192K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_22K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_32K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_44K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_48K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_8K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_96K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_MCKDIV : stm32h7xx_hal_sai.h
  • SAI_CLOCKSTROBING_FALLINGEDGE : stm32h7xx_hal_sai.h
  • SAI_CLOCKSTROBING_RISINGEDGE : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_10 : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_16 : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_20 : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_24 : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_32 : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_8 : stm32h7xx_hal_sai.h
  • SAI_DEFAULT_TIMEOUT : stm32h7xx_hal_sai.c
  • SAI_Disable() : stm32h7xx_hal_sai.c
  • SAI_DMAAbort() : stm32h7xx_hal_sai.c
  • SAI_DMAError() : stm32h7xx_hal_sai.c
  • SAI_DMARxCplt() : stm32h7xx_hal_sai.c
  • SAI_DMARxHalfCplt() : stm32h7xx_hal_sai.c
  • SAI_DMATxCplt() : stm32h7xx_hal_sai.c
  • SAI_DMATxHalfCplt() : stm32h7xx_hal_sai.c
  • SAI_FIFO_SIZE : stm32h7xx_hal_sai.c
  • SAI_FIFOSTATUS_1QUARTERFULL : stm32h7xx_hal_sai.h
  • SAI_FIFOSTATUS_3QUARTERFULL : stm32h7xx_hal_sai.h
  • SAI_FIFOSTATUS_EMPTY : stm32h7xx_hal_sai.h
  • SAI_FIFOSTATUS_FULL : stm32h7xx_hal_sai.h
  • SAI_FIFOSTATUS_HALFFULL : stm32h7xx_hal_sai.h
  • SAI_FIFOSTATUS_LESS1QUARTERFULL : stm32h7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_1QF : stm32h7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_3QF : stm32h7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_EMPTY : stm32h7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_FULL : stm32h7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_HF : stm32h7xx_hal_sai.h
  • SAI_FillFifo() : stm32h7xx_hal_sai.c
  • SAI_FIRSTBIT_LSB : stm32h7xx_hal_sai.h
  • SAI_FIRSTBIT_MSB : stm32h7xx_hal_sai.h
  • SAI_FLAG_AFSDET : stm32h7xx_hal_sai.h
  • SAI_FLAG_CNRDY : stm32h7xx_hal_sai.h
  • SAI_FLAG_FREQ : stm32h7xx_hal_sai.h
  • SAI_FLAG_LFSDET : stm32h7xx_hal_sai.h
  • SAI_FLAG_MUTEDET : stm32h7xx_hal_sai.h
  • SAI_FLAG_OVRUDR : stm32h7xx_hal_sai.h
  • SAI_FLAG_WCKCFG : stm32h7xx_hal_sai.h
  • SAI_FREE_PROTOCOL : stm32h7xx_hal_sai.h
  • SAI_FS_ACTIVE_HIGH : stm32h7xx_hal_sai.h
  • SAI_FS_ACTIVE_LOW : stm32h7xx_hal_sai.h
  • SAI_FS_BEFOREFIRSTBIT : stm32h7xx_hal_sai.h
  • SAI_FS_CHANNEL_IDENTIFICATION : stm32h7xx_hal_sai.h
  • SAI_FS_FIRSTBIT : stm32h7xx_hal_sai.h
  • SAI_FS_STARTFRAME : stm32h7xx_hal_sai.h
  • SAI_HandleTypeDef : stm32h7xx_hal_sai.h
  • SAI_I2S_LSBJUSTIFIED : stm32h7xx_hal_sai.h
  • SAI_I2S_MSBJUSTIFIED : stm32h7xx_hal_sai.h
  • SAI_I2S_STANDARD : stm32h7xx_hal_sai.h
  • SAI_InitI2S() : stm32h7xx_hal_sai.c
  • SAI_InitPCM() : stm32h7xx_hal_sai.c
  • SAI_InterruptFlag() : stm32h7xx_hal_sai.c
  • SAI_IT_AFSDET : stm32h7xx_hal_sai.h
  • SAI_IT_CNRDY : stm32h7xx_hal_sai.h
  • SAI_IT_FREQ : stm32h7xx_hal_sai.h
  • SAI_IT_LFSDET : stm32h7xx_hal_sai.h
  • SAI_IT_MUTEDET : stm32h7xx_hal_sai.h
  • SAI_IT_OVRUDR : stm32h7xx_hal_sai.h
  • SAI_IT_WCKCFG : stm32h7xx_hal_sai.h
  • SAI_LAST_SENT_VALUE : stm32h7xx_hal_sai.h
  • SAI_LONG_TIMEOUT : stm32h7xx_hal_sai.c
  • SAI_MASTERDIVIDER_DISABLE : stm32h7xx_hal_sai.h
  • SAI_MASTERDIVIDER_ENABLE : stm32h7xx_hal_sai.h
  • SAI_MCK_OVERSAMPLING_DISABLE : stm32h7xx_hal_sai.h
  • SAI_MCK_OVERSAMPLING_ENABLE : stm32h7xx_hal_sai.h
  • SAI_MODE_DMA : stm32h7xx_hal_sai.c
  • SAI_MODE_IT : stm32h7xx_hal_sai.c
  • SAI_MODEMASTER_RX : stm32h7xx_hal_sai.h
  • SAI_MODEMASTER_TX : stm32h7xx_hal_sai.h
  • SAI_MODESLAVE_RX : stm32h7xx_hal_sai.h
  • SAI_MODESLAVE_TX : stm32h7xx_hal_sai.h
  • SAI_ModeTypedef : stm32h7xx_hal_sai.c
  • SAI_MONOMODE : stm32h7xx_hal_sai.h
  • SAI_NOCOMPANDING : stm32h7xx_hal_sai.h
  • SAI_OUTPUT_NOTRELEASED : stm32h7xx_hal_sai.h
  • SAI_OUTPUT_RELEASED : stm32h7xx_hal_sai.h
  • SAI_OUTPUTDRIVE_DISABLE : stm32h7xx_hal_sai.h
  • SAI_OUTPUTDRIVE_ENABLE : stm32h7xx_hal_sai.h
  • SAI_PCM_LONG : stm32h7xx_hal_sai.h
  • SAI_PCM_SHORT : stm32h7xx_hal_sai.h
  • SAI_PDM_CLOCK1_ENABLE : stm32h7xx_hal_sai.h
  • SAI_PDM_CLOCK2_ENABLE : stm32h7xx_hal_sai.h
  • SAI_PDM_CLOCK3_ENABLE : stm32h7xx_hal_sai.h
  • SAI_PDM_CLOCK4_ENABLE : stm32h7xx_hal_sai.h
  • SAI_PDM_DELAY_MASK : stm32h7xx_hal_sai_ex.c
  • SAI_PDM_DELAY_OFFSET : stm32h7xx_hal_sai_ex.c
  • SAI_PDM_RIGHT_DELAY_OFFSET : stm32h7xx_hal_sai_ex.c
  • SAI_PDMCR_MICNBR_OFFSET : stm32h7xx_hal_sai.c
  • SAI_PROTOCOL_DATASIZE_16BIT : stm32h7xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_16BITEXTENDED : stm32h7xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_24BIT : stm32h7xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_32BIT : stm32h7xx_hal_sai.h
  • SAI_Receive_IT16Bit() : stm32h7xx_hal_sai.c
  • SAI_Receive_IT32Bit() : stm32h7xx_hal_sai.c
  • SAI_Receive_IT8Bit() : stm32h7xx_hal_sai.c
  • SAI_SLOT_NOTACTIVE : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_0 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_1 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_10 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_11 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_12 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_13 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_14 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_15 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_2 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_3 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_4 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_5 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_6 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_7 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_8 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_9 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_ALL : stm32h7xx_hal_sai.h
  • SAI_SLOTSIZE_16B : stm32h7xx_hal_sai.h
  • SAI_SLOTSIZE_32B : stm32h7xx_hal_sai.h
  • SAI_SLOTSIZE_DATASIZE : stm32h7xx_hal_sai.h
  • SAI_SPDIF_PROTOCOL : stm32h7xx_hal_sai.h
  • SAI_STEREOMODE : stm32h7xx_hal_sai.h
  • SAI_SYNCEXT_DISABLE : stm32h7xx_hal_sai.h
  • SAI_SYNCEXT_OUTBLOCKA_ENABLE : stm32h7xx_hal_sai.h
  • SAI_SYNCEXT_OUTBLOCKB_ENABLE : stm32h7xx_hal_sai.h
  • SAI_SYNCHRONOUS : stm32h7xx_hal_sai.h
  • SAI_SYNCHRONOUS_EXT_SAI1 : stm32h7xx_hal_sai.h
  • SAI_SYNCHRONOUS_EXT_SAI2 : stm32h7xx_hal_sai.h
  • SAI_Transmit_IT16Bit() : stm32h7xx_hal_sai.c
  • SAI_Transmit_IT32Bit() : stm32h7xx_hal_sai.c
  • SAI_Transmit_IT8Bit() : stm32h7xx_hal_sai.c
  • SAI_ULAW_1CPL_COMPANDING : stm32h7xx_hal_sai.h
  • SAI_ULAW_2CPL_COMPANDING : stm32h7xx_hal_sai.h
  • SAI_xCR2_MUTECNT_OFFSET : stm32h7xx_hal_sai.c
  • SAI_ZERO_VALUE : stm32h7xx_hal_sai.h
  • SAIcallback : stm32h7xx_hal_sai.h
  • SD_CONTEXT_DMA : stm32h7xx_hal_sd.h
  • SD_CONTEXT_IT : stm32h7xx_hal_sd.h
  • SD_CONTEXT_NONE : stm32h7xx_hal_sd.h
  • SD_CONTEXT_READ_MULTIPLE_BLOCK : stm32h7xx_hal_sd.h
  • SD_CONTEXT_READ_SINGLE_BLOCK : stm32h7xx_hal_sd.h
  • SD_CONTEXT_WRITE_MULTIPLE_BLOCK : stm32h7xx_hal_sd.h
  • SD_CONTEXT_WRITE_SINGLE_BLOCK : stm32h7xx_hal_sd.h
  • SD_DMA_BUFFER0 : stm32h7xx_hal_sd_ex.h
  • SD_DMA_BUFFER1 : stm32h7xx_hal_sd_ex.h
  • SD_FindSCR() : stm32h7xx_hal_sd.c
  • SD_HighSpeed() : stm32h7xx_hal_sd.c
  • SD_InitCard() : stm32h7xx_hal_sd.c
  • SD_InitTypeDef : stm32h7xx_hal_sd.h
  • SD_PowerOFF() : stm32h7xx_hal_sd.c
  • SD_PowerON() : stm32h7xx_hal_sd.c
  • SD_Read_IT() : stm32h7xx_hal_sd.c
  • SD_SendSDStatus() : stm32h7xx_hal_sd.c
  • SD_SendStatus() : stm32h7xx_hal_sd.c
  • SD_TypeDef : stm32h7xx_hal_sd.h
  • SD_WideBus_Disable() : stm32h7xx_hal_sd.c
  • SD_WideBus_Enable() : stm32h7xx_hal_sd.c
  • SD_Write_IT() : stm32h7xx_hal_sd.c
  • SlaveAddr_MSK : stm32h7xx_hal_i2c.c
  • SlaveAddr_SHIFT : stm32h7xx_hal_i2c.c
  • SMARTCARD_ADVFEATURE_DATAINV_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINV_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINVERT_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_NO_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_OVERRUN_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_OVERRUN_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINVERT_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_SWAP_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXCOMPLETION : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXINV_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINV_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINVERT_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_AdvFeatureConfig() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_CheckIdleState() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_CLEAR_EOBF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_FEF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_IDLEF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_NEF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_OREF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_PEF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_RTOF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCBGTF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TXFECF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_UDRCF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLOCKSOURCE_CSI : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_D2PCLK1 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_D2PCLK2 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_D3PCLK1 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_HSI : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_LSE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PLL2Q : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PLL3Q : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_UNDEFINED : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ClockSourceTypeDef : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CR3_SCARCNT_LSB_POS : stm32h7xx_hal_smartcard.h
  • SMARTCARD_DMAAbortOnError() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMAError() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMAReceiveCplt() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMARxAbortCallback() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMARxOnlyAbortCallback() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMATransmitCplt() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMATxAbortCallback() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMATxOnlyAbortCallback() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_EndRxTransfer() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_EndTransmit_IT() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_EndTxTransfer() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_FIFOMODE_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_FIFOMODE_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_FLAG_BUSY : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_EOBF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_FE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_IDLE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_NE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_ORE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_PE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_REACK : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RTOF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXNE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TC : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TCBGT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TEACK : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_GETCLOCKSOURCE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_GTPR_GT_LSB_POS : stm32h7xx_hal_smartcard.h
  • SMARTCARD_IT_EOB : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_ERR : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_FE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_IDLE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_MASK : stm32h7xx_hal_smartcard.h
  • SMARTCARD_IT_NE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_ORE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_PE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RTO : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXNE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TC : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TCBGT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_LASTBIT_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_MODE_RX : stm32h7xx_hal_smartcard.h
  • SMARTCARD_MODE_TX : stm32h7xx_hal_smartcard.h
  • SMARTCARD_MODE_TX_RX : stm32h7xx_hal_smartcard.h
  • SMARTCARD_NACK_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_NACK_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PARITY_EVEN : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PARITY_ODD : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PHASE_1EDGE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PHASE_2EDGE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_POLARITY_HIGH : stm32h7xx_hal_smartcard.h
  • SMARTCARD_POLARITY_LOW : stm32h7xx_hal_smartcard.h
  • SMARTCARD_Receive_IT() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_RTOR_BLEN_LSB_POS : stm32h7xx_hal_smartcard.h
  • SMARTCARD_RXDATA_FLUSH_REQUEST : stm32h7xx_hal_smartcard.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_RXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_RXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_RXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_SetConfig() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_STOPBITS_0_5 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_1_5 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TC : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TCBGT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TEACK_REACK_TIMEOUT : stm32h7xx_hal_smartcard.c
  • SMARTCARD_TIMEOUT_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TIMEOUT_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TRANSMISSION_COMPLETION_FLAG : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TRANSMISSION_COMPLETION_SETTING : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_Transmit_IT() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_TXDATA_FLUSH_REQUEST : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_WaitOnFlagUntilTimeout() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_WORDLENGTH_9B : stm32h7xx_hal_smartcard.h
  • SMBUS_ADDRESSINGMODE_10BIT : stm32h7xx_hal_smbus.h
  • SMBUS_ADDRESSINGMODE_7BIT : stm32h7xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_DISABLE : stm32h7xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_ENABLE : stm32h7xx_hal_smbus.h
  • SMBUS_AUTOEND_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_CHECK_FLAG : stm32h7xx_hal_smbus.h
  • SMBUS_ConvertOtherXferOptions() : stm32h7xx_hal_smbus.c
  • SMBUS_Disable_IRQ() : stm32h7xx_hal_smbus.c
  • SMBUS_DUALADDRESS_DISABLE : stm32h7xx_hal_smbus.h
  • SMBUS_DUALADDRESS_ENABLE : stm32h7xx_hal_smbus.h
  • SMBUS_Enable_IRQ() : stm32h7xx_hal_smbus.c
  • SMBUS_FIRST_AND_LAST_FRAME_NO_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_FIRST_FRAME : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_ADDR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_AF : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_ALERT : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_ARLO : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_BERR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_BUSY : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_DIR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_MASK : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_OVR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_PECERR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_RXNE : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_STOPF : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_TC : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_TCR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_TIMEOUT : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_TXE : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_TXIS : stm32h7xx_hal_smbus.h
  • SMBUS_GENERALCALL_DISABLE : stm32h7xx_hal_smbus.h
  • SMBUS_GENERALCALL_ENABLE : stm32h7xx_hal_smbus.h
  • SMBUS_GENERATE_START : stm32h7xx_hal_smbus.h
  • SMBUS_GENERATE_START_READ : stm32h7xx_hal_smbus.h
  • SMBUS_GENERATE_START_WRITE : stm32h7xx_hal_smbus.h
  • SMBUS_GENERATE_STOP : stm32h7xx_hal_smbus.h
  • SMBUS_GET_ADDR_MATCH : stm32h7xx_hal_smbus.h
  • SMBUS_GET_ALERT_ENABLED : stm32h7xx_hal_smbus.h
  • SMBUS_GET_DIR : stm32h7xx_hal_smbus.h
  • SMBUS_GET_ISR_REG : stm32h7xx_hal_smbus.h
  • SMBUS_GET_PEC_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_GET_STOP_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_IT_ADDR : stm32h7xx_hal_smbus.h
  • SMBUS_IT_ADDRI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_ALERT : stm32h7xx_hal_smbus.h
  • SMBUS_IT_ERRI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_NACKI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_RX : stm32h7xx_hal_smbus.h
  • SMBUS_IT_RXI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_STOPI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_TCI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_TX : stm32h7xx_hal_smbus.h
  • SMBUS_IT_TXI : stm32h7xx_hal_smbus.h
  • SMBUS_LAST_FRAME_NO_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_LAST_FRAME_WITH_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_Master_ISR() : stm32h7xx_hal_smbus.c
  • SMBUS_NEXT_FRAME : stm32h7xx_hal_smbus.h
  • SMBUS_NO_STARTSTOP : stm32h7xx_hal_smbus.h
  • SMBUS_NOSTRETCH_DISABLE : stm32h7xx_hal_smbus.h
  • SMBUS_NOSTRETCH_ENABLE : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK01 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK02 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK03 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK04 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK05 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK06 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK07 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_NOMASK : stm32h7xx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_NO_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_OTHER_FRAME_NO_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_OTHER_FRAME_WITH_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_PEC_DISABLE : stm32h7xx_hal_smbus.h
  • SMBUS_PEC_ENABLE : stm32h7xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_HOST : stm32h7xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE : stm32h7xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP : stm32h7xx_hal_smbus.h
  • SMBUS_RELOAD_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_RESET_CR1 : stm32h7xx_hal_smbus.h
  • SMBUS_RESET_CR2 : stm32h7xx_hal_smbus.h
  • SMBUS_SENDPEC_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_Slave_ISR() : stm32h7xx_hal_smbus.c
  • SMBUS_SOFTEND_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_TransferConfig() : stm32h7xx_hal_smbus.c
  • SMBUS_WaitOnFlagUntilTimeout() : stm32h7xx_hal_smbus.c
  • SPDIFRX_CHANNEL_A : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_CHANNEL_B : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_CHANNELSTATUS_OFF : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_CHANNELSTATUS_ON : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_DATAFORMAT_32BITS : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_DATAFORMAT_LSB : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_DATAFORMAT_MSB : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_DMACxCplt() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_DMACxHalfCplt() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_DMAError() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_DMARxCplt() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_DMARxHalfCplt() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_FLAG_CSRNE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_FERR : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_OVR : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_PERR : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_RXNE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_SBD : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_SERR : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_SYNCD : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_TERR : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN0 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN1 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN2 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN3 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_CSRNE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_IFEIE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_OVRIE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_PERRIE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_RXNE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_SBLKIE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_SYNCDIE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_15 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_3 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_63 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_NONE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_PARITYERRORMASK_OFF : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_PARITYERRORMASK_ON : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_PREAMBLETYPEMASK_OFF : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_PREAMBLETYPEMASK_ON : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_ReceiveControlFlow_IT() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_ReceiveDataFlow_IT() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_STATE_IDLE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_STATE_RCV : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_STATE_SYNC : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_STEREOMODE_DISABLE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_STEREOMODE_ENABLE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_TIMEOUT_VALUE : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_VALIDITYMASK_OFF : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_VALIDITYMASK_ON : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_WAITFORACTIVITY_OFF : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_WAITFORACTIVITY_ON : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_WaitOnFlagUntilTimeout() : stm32h7xx_hal_spdifrx.c
  • SPI_1LINE_RX : stm32h7xx_hal_spi.h
  • SPI_1LINE_TX : stm32h7xx_hal_spi.h
  • SPI_2linesRxISR_16BIT() : stm32h7xx_hal_spi.c
  • SPI_2linesRxISR_32BIT() : stm32h7xx_hal_spi.c
  • SPI_2linesRxISR_8BIT() : stm32h7xx_hal_spi.c
  • SPI_2linesTxISR_16BIT() : stm32h7xx_hal_spi.c
  • SPI_2linesTxISR_32BIT() : stm32h7xx_hal_spi.c
  • SPI_2linesTxISR_8BIT() : stm32h7xx_hal_spi.c
  • SPI_AbortRx_ISR() : stm32h7xx_hal_spi.c
  • SPI_AbortTx_ISR() : stm32h7xx_hal_spi.c
  • SPI_BAUDRATEPRESCALER_128 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm32h7xx_hal_spi.h
  • SPI_CloseRx_ISR() : stm32h7xx_hal_spi.c
  • SPI_CloseRxTx_ISR() : stm32h7xx_hal_spi.c
  • SPI_CloseTx_ISR() : stm32h7xx_hal_spi.c
  • SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN : stm32h7xx_hal_spi.h
  • SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_10BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_11BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_12BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_13BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_14BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_15BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_16BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_17BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_18BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_19BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_20BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_21BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_22BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_23BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_24BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_25BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_26BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_27BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_28BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_29BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_30BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_31BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_32BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_4BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_5BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_6BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_7BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_8BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_9BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_DATASIZE : stm32h7xx_hal_spi.h
  • SPI_CRCCALCULATION_DISABLE : stm32h7xx_hal_spi.h
  • SPI_CRCCALCULATION_ENABLE : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_10BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_11BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_12BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_13BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_14BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_15BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_16BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_17BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_18BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_19BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_20BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_21BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_22BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_23BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_24BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_25BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_26BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_27BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_28BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_29BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_30BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_31BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_32BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_4BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_5BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_6BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_7BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_8BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_9BIT : stm32h7xx_hal_spi.h
  • SPI_DEFAULT_TIMEOUT : stm32h7xx_hal_spi.c
  • SPI_DIRECTION_1LINE : stm32h7xx_hal_spi.h
  • SPI_DIRECTION_2LINES : stm32h7xx_hal_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : stm32h7xx_hal_spi.h
  • SPI_DIRECTION_2LINES_TXONLY : stm32h7xx_hal_spi.h
  • SPI_DMAAbortOnError() : stm32h7xx_hal_spi.c
  • SPI_DMAError() : stm32h7xx_hal_spi.c
  • SPI_DMAHalfReceiveCplt() : stm32h7xx_hal_spi.c
  • SPI_DMAHalfTransmitCplt() : stm32h7xx_hal_spi.c
  • SPI_DMAHalfTransmitReceiveCplt() : stm32h7xx_hal_spi.c
  • SPI_DMAReceiveCplt() : stm32h7xx_hal_spi.c
  • SPI_DMARxAbortCallback() : stm32h7xx_hal_spi.c
  • SPI_DMATransmitCplt() : stm32h7xx_hal_spi.c
  • SPI_DMATransmitReceiveCplt() : stm32h7xx_hal_spi.c
  • SPI_DMATxAbortCallback() : stm32h7xx_hal_spi.c
  • SPI_EndRxTransaction() : stm32h7xx_hal_spi.c
  • SPI_EndRxTxTransaction() : stm32h7xx_hal_spi.c
  • SPI_FIFO_THRESHOLD_01DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_02DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_03DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_04DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_05DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_06DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_07DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_08DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_09DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_10DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_11DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_12DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_13DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_14DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_15DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_16DATA : stm32h7xx_hal_spi.h
  • SPI_FIRSTBIT_LSB : stm32h7xx_hal_spi.h
  • SPI_FIRSTBIT_MSB : stm32h7xx_hal_spi.h
  • SPI_FLAG_CRCERR : stm32h7xx_hal_spi.h
  • SPI_FLAG_EOT : stm32h7xx_hal_spi.h
  • SPI_FLAG_FRE : stm32h7xx_hal_spi.h
  • SPI_FLAG_FRLVL : stm32h7xx_hal_spi.h
  • SPI_FLAG_MODF : stm32h7xx_hal_spi.h
  • SPI_FLAG_OVR : stm32h7xx_hal_spi.h
  • SPI_FLAG_RXNE : stm32h7xx_hal_spi.h
  • SPI_FLAG_RXWNE : stm32h7xx_hal_spi.h
  • SPI_FLAG_TXE : stm32h7xx_hal_spi.h
  • SPI_FLAG_TXTF : stm32h7xx_hal_spi.h
  • SPI_FLAG_UDR : stm32h7xx_hal_spi.h
  • SPI_FRLVL_EMPTY : stm32h7xx_hal_spi.h
  • SPI_FRLVL_FULL : stm32h7xx_hal_spi.h
  • SPI_FRLVL_HALF_FULL : stm32h7xx_hal_spi.h
  • SPI_FRLVL_QUARTER_FULL : stm32h7xx_hal_spi.h
  • SPI_HandleTypeDef : stm32h7xx_hal_spi.h
  • SPI_HIGHEND_FIFO_SIZE : stm32h7xx_hal_spi.h
  • SPI_IO_SWAP_DISABLE : stm32h7xx_hal_spi.h
  • SPI_IO_SWAP_ENABLE : stm32h7xx_hal_spi.h
  • SPI_IT_EOT : stm32h7xx_hal_spi.h
  • SPI_IT_ERR : stm32h7xx_hal_spi.h
  • SPI_IT_RXNE : stm32h7xx_hal_spi.h
  • SPI_IT_TXE : stm32h7xx_hal_spi.h
  • SPI_IT_TXTF : stm32h7xx_hal_spi.h
  • SPI_LOWEND_FIFO_SIZE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_00CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_01CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_02CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_03CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_04CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_05CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_06CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_07CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_08CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_09CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_10CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_11CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_12CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_13CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_14CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_15CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_KEEP_IO_STATE_DISABLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_KEEP_IO_STATE_ENABLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_RX_AUTOSUSP_DISABLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_RX_AUTOSUSP_ENABLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_00CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_01CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_02CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_03CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_04CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_05CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_06CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_07CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_08CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_09CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_10CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_11CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_12CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_13CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_14CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_15CYCLE : stm32h7xx_hal_spi.h
  • SPI_MODE_MASTER : stm32h7xx_hal_spi.h
  • SPI_MODE_SLAVE : stm32h7xx_hal_spi.h
  • SPI_NSS_HARD_INPUT : stm32h7xx_hal_spi.h
  • SPI_NSS_HARD_OUTPUT : stm32h7xx_hal_spi.h
  • SPI_NSS_POLARITY_HIGH : stm32h7xx_hal_spi.h
  • SPI_NSS_POLARITY_LOW : stm32h7xx_hal_spi.h
  • SPI_NSS_PULSE_DISABLE : stm32h7xx_hal_spi.h
  • SPI_NSS_PULSE_ENABLE : stm32h7xx_hal_spi.h
  • SPI_NSS_SOFT : stm32h7xx_hal_spi.h
  • SPI_PHASE_1EDGE : stm32h7xx_hal_spi.h
  • SPI_PHASE_2EDGE : stm32h7xx_hal_spi.h
  • SPI_POLARITY_HIGH : stm32h7xx_hal_spi.h
  • SPI_POLARITY_LOW : stm32h7xx_hal_spi.h
  • SPI_RxISR_16BIT() : stm32h7xx_hal_spi.c
  • SPI_RxISR_32BIT() : stm32h7xx_hal_spi.c
  • SPI_RxISR_8BIT() : stm32h7xx_hal_spi.c
  • SPI_TIMODE_DISABLE : stm32h7xx_hal_spi.h
  • SPI_TIMODE_ENABLE : stm32h7xx_hal_spi.h
  • SPI_TxISR_16BIT() : stm32h7xx_hal_spi.c
  • SPI_TxISR_32BIT() : stm32h7xx_hal_spi.c
  • SPI_TxISR_8BIT() : stm32h7xx_hal_spi.c
  • SPI_UNDERRUN_BEHAV_LAST_RECEIVED : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_BEHAV_REGISTER_PATTERN : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_DETECT_END_DATA_FRAME : stm32h7xx_hal_spi.h
  • SPI_WaitFifoStateUntilTimeout() : stm32h7xx_hal_spi.c
  • SPI_WaitFlagStateUntilTimeout() : stm32h7xx_hal_spi.c
  • SWPMI_DMAAbortOnError() : stm32h7xx_hal_swpmi.c
  • SWPMI_DMAError() : stm32h7xx_hal_swpmi.c
  • SWPMI_DMAReceiveCplt() : stm32h7xx_hal_swpmi.c
  • SWPMI_DMARxHalfCplt() : stm32h7xx_hal_swpmi.c
  • SWPMI_DMATransmitCplt() : stm32h7xx_hal_swpmi.c
  • SWPMI_DMATxHalfCplt() : stm32h7xx_hal_swpmi.c
  • SWPMI_EndReceive_IT() : stm32h7xx_hal_swpmi.c
  • SWPMI_EndTransmit_IT() : stm32h7xx_hal_swpmi.c
  • SWPMI_EndTransmitReceive_IT() : stm32h7xx_hal_swpmi.c
  • SWPMI_FLAG_DEACTF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_RDYF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_RXBERF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_RXBFF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_RXNE : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_RXOVRF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_SRF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_SUSP : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_TCF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_TXBEF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_TXE : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_TXUNRF : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_RDYIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_RIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_RXBERIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_RXBFIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_RXOVRIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_SRIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_TCIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_TIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_TXBEIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_TXUNRIE : stm32h7xx_hal_swpmi.h
  • SWPMI_Receive_IT() : stm32h7xx_hal_swpmi.c
  • SWPMI_RX_MULTI_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_RX_NO_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_RX_SINGLE_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_TIMEOUT_VALUE : stm32h7xx_hal_swpmi.c
  • SWPMI_Transmit_IT() : stm32h7xx_hal_swpmi.c
  • SWPMI_TX_MULTI_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_TX_NO_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_TX_SINGLE_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_VOLTAGE_CLASS_B : stm32h7xx_hal_swpmi.h
  • SWPMI_VOLTAGE_CLASS_C : stm32h7xx_hal_swpmi.h
  • SWPMI_WaitOnFlagSetUntilTimeout() : stm32h7xx_hal_swpmi.c
  • SYSCFG_BOOT_ADDR0 : stm32h7xx_hal.h
  • SYSCFG_BOOT_ADDR1 : stm32h7xx_hal.h
  • SYSCFG_CELL_CODE : stm32h7xx_hal.h
  • SYSCFG_ETH_MII : stm32h7xx_hal.h
  • SYSCFG_ETH_RMII : stm32h7xx_hal.h
  • SYSCFG_REGISTER_CODE : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA0 : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA0_CLOSE : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA0_OPEN : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA1 : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA1_CLOSE : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA1_OPEN : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC2 : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC2_CLOSE : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC2_OPEN : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC3 : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC3_CLOSE : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC3_OPEN : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE0 : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE1 : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE2 : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE3 : stm32h7xx_hal.h
  • SYSTICK_CLKSOURCE_HCLK : stm32h7xx_hal_cortex.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32h7xx_hal_cortex.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- t -

  • TICK_INT_PRIORITY : stm32h7xx_hal_conf.h
  • TIM_AUTOMATICOUTPUT_DISABLE : stm32h7xx_hal_tim.h
  • TIM_AUTOMATICOUTPUT_ENABLE : stm32h7xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_DISABLE : stm32h7xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_ENABLE : stm32h7xx_hal_tim.h
  • TIM_Base_SetConfig() : stm32h7xx_hal_tim.c , stm32h7xx_hal_tim.h
  • TIM_BREAK2_DISABLE : stm32h7xx_hal_tim_ex.h
  • TIM_BREAK2_ENABLE : stm32h7xx_hal_tim_ex.h
  • TIM_BREAK2POLARITY_HIGH : stm32h7xx_hal_tim_ex.h
  • TIM_BREAK2POLARITY_LOW : stm32h7xx_hal_tim_ex.h
  • TIM_BREAK_DISABLE : stm32h7xx_hal_tim.h
  • TIM_BREAK_ENABLE : stm32h7xx_hal_tim.h
  • TIM_BREAKINPUT_BRK : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUT_BRK2 : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_BKIN : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_DFSDM1 : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_DISABLE : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_ENABLE : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_HIGH : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_LOW : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKPOLARITY_HIGH : stm32h7xx_hal_tim.h
  • TIM_BREAKPOLARITY_LOW : stm32h7xx_hal_tim.h
  • TIM_CCER_CCxE_MASK : stm32h7xx_hal_tim.h
  • TIM_CCER_CCxNE_MASK : stm32h7xx_hal_tim.h
  • TIM_CCx_DISABLE : stm32h7xx_hal_tim.h
  • TIM_CCx_ENABLE : stm32h7xx_hal_tim.h
  • TIM_CCxChannelCmd() : stm32h7xx_hal_tim.c , stm32h7xx_hal_tim.h
  • TIM_CCxN_DISABLE : stm32h7xx_hal_tim.h
  • TIM_CCxN_ENABLE : stm32h7xx_hal_tim.h
  • TIM_CCxNChannelCmd() : stm32h7xx_hal_tim_ex.c
  • TIM_CHANNEL_1 : stm32h7xx_hal_tim_ex.h
  • TIM_CHANNEL_2 : stm32h7xx_hal_tim_ex.h
  • TIM_CHANNEL_3 : stm32h7xx_hal_tim_ex.h
  • TIM_CHANNEL_4 : stm32h7xx_hal_tim_ex.h
  • TIM_CHANNEL_5 : stm32h7xx_hal_tim_ex.h
  • TIM_CHANNEL_6 : stm32h7xx_hal_tim_ex.h
  • TIM_CHANNEL_ALL : stm32h7xx_hal_tim_ex.h
  • TIM_CLEARINPUTPOLARITY_INVERTED : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_NONINVERTED : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV1 : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV2 : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV4 : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV8 : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_ETR : stm32h7xx_hal_tim_ex.h
  • TIM_CLEARINPUTSOURCE_NONE : stm32h7xx_hal_tim_ex.h
  • TIM_CLEARINPUTSOURCE_OCREFCLR : stm32h7xx_hal_tim_ex.h
  • TIM_CLOCKDIVISION_DIV1 : stm32h7xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV2 : stm32h7xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV4 : stm32h7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_BOTHEDGE : stm32h7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_FALLING : stm32h7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_INVERTED : stm32h7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_NONINVERTED : stm32h7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_RISING : stm32h7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV1 : stm32h7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV2 : stm32h7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV4 : stm32h7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV8 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE1 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE2 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_INTERNAL : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR0 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR1 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR2 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR3 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1ED : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI2 : stm32h7xx_hal_tim.h
  • TIM_COMMUTATION_SOFTWARE : stm32h7xx_hal_tim.h
  • TIM_COMMUTATION_TRGI : stm32h7xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED1 : stm32h7xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED2 : stm32h7xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED3 : stm32h7xx_hal_tim.h
  • TIM_COUNTERMODE_DOWN : stm32h7xx_hal_tim.h
  • TIM_COUNTERMODE_UP : stm32h7xx_hal_tim.h
  • TIM_DMA_CC1 : stm32h7xx_hal_tim.h
  • TIM_DMA_CC2 : stm32h7xx_hal_tim.h
  • TIM_DMA_CC3 : stm32h7xx_hal_tim.h
  • TIM_DMA_CC4 : stm32h7xx_hal_tim.h
  • TIM_DMA_COM : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_CC1 : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_CC2 : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_CC3 : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_CC4 : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_COMMUTATION : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_UPDATE : stm32h7xx_hal_tim.h
  • TIM_DMA_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_DMA_UPDATE : stm32h7xx_hal_tim.h
  • TIM_DMABASE_AF1 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_AF2 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_AF3 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_ARR : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_BDTR : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CCER : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CCMR1 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CCMR2 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CCMR3 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CCR1 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CCR2 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CCR3 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CCR4 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CCR5 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CCR6 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CNT : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CR1 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CR2 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_DCR : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_DIER : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_DMAR : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_EGR : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_PSC : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_RCR : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_SMCR : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_SR : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_TISEL : stm32h7xx_hal_tim_ex.h
  • TIM_DMABURSTLENGTH_10TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_11TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_12TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_13TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_14TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_15TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_16TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_17TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_18TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_1TRANSFER : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_2TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_3TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_4TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_5TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_6TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_7TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_8TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_9TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMAPeriodElapsedCplt() : stm32h7xx_hal_tim.c
  • TIM_DMATriggerCplt() : stm32h7xx_hal_tim.c
  • TIM_ENCODERMODE_TI1 : stm32h7xx_hal_tim.h
  • TIM_ENCODERMODE_TI12 : stm32h7xx_hal_tim.h
  • TIM_ENCODERMODE_TI2 : stm32h7xx_hal_tim.h
  • TIM_ETR_SetConfig() : stm32h7xx_hal_tim.c , stm32h7xx_hal_tim.h
  • TIM_ETRPOLARITY_INVERTED : stm32h7xx_hal_tim.h
  • TIM_ETRPOLARITY_NONINVERTED : stm32h7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV1 : stm32h7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV2 : stm32h7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV4 : stm32h7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV8 : stm32h7xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_BREAK2 : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_CC1 : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_CC2 : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_CC3 : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_CC4 : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_COM : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_TRIGGER : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_UPDATE : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim_ex.h
  • TIM_FLAG_BREAK : stm32h7xx_hal_tim.h
  • TIM_FLAG_BREAK2 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC1 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC1OF : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC2 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC2OF : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC3 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC3OF : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC4 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC4OF : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC5 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC6 : stm32h7xx_hal_tim.h
  • TIM_FLAG_COM : stm32h7xx_hal_tim.h
  • TIM_FLAG_SYSTEM_BREAK : stm32h7xx_hal_tim.h
  • TIM_FLAG_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_FLAG_UPDATE : stm32h7xx_hal_tim.h
  • TIM_GROUPCH5_NONE : stm32h7xx_hal_tim_ex.h
  • TIM_GROUPCH5_OC1REFC : stm32h7xx_hal_tim_ex.h
  • TIM_GROUPCH5_OC2REFC : stm32h7xx_hal_tim_ex.h
  • TIM_GROUPCH5_OC3REFC : stm32h7xx_hal_tim_ex.h
  • TIM_ICPOLARITY_BOTHEDGE : stm32h7xx_hal_tim.h
  • TIM_ICPOLARITY_FALLING : stm32h7xx_hal_tim.h
  • TIM_ICPOLARITY_RISING : stm32h7xx_hal_tim.h
  • TIM_ICPSC_DIV1 : stm32h7xx_hal_tim.h
  • TIM_ICPSC_DIV2 : stm32h7xx_hal_tim.h
  • TIM_ICPSC_DIV4 : stm32h7xx_hal_tim.h
  • TIM_ICPSC_DIV8 : stm32h7xx_hal_tim.h
  • TIM_ICSELECTION_DIRECTTI : stm32h7xx_hal_tim.h
  • TIM_ICSELECTION_INDIRECTTI : stm32h7xx_hal_tim.h
  • TIM_ICSELECTION_TRC : stm32h7xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE : stm32h7xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_FALLING : stm32h7xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_RISING : stm32h7xx_hal_tim.h
  • TIM_IT_BREAK : stm32h7xx_hal_tim.h
  • TIM_IT_CC1 : stm32h7xx_hal_tim.h
  • TIM_IT_CC2 : stm32h7xx_hal_tim.h
  • TIM_IT_CC3 : stm32h7xx_hal_tim.h
  • TIM_IT_CC4 : stm32h7xx_hal_tim.h
  • TIM_IT_COM : stm32h7xx_hal_tim.h
  • TIM_IT_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_IT_UPDATE : stm32h7xx_hal_tim.h
  • TIM_ITRx_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_LOCKLEVEL_1 : stm32h7xx_hal_tim.h
  • TIM_LOCKLEVEL_2 : stm32h7xx_hal_tim.h
  • TIM_LOCKLEVEL_3 : stm32h7xx_hal_tim.h
  • TIM_LOCKLEVEL_OFF : stm32h7xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_DISABLE : stm32h7xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_ENABLE : stm32h7xx_hal_tim.h
  • TIM_OC1_SetConfig() : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim.c
  • TIM_OC2_SetConfig() : stm32h7xx_hal_tim.c , stm32h7xx_hal_tim.h
  • TIM_OC3_SetConfig() : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim.c
  • TIM_OC4_SetConfig() : stm32h7xx_hal_tim.c , stm32h7xx_hal_tim.h
  • TIM_OC5_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_OC6_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_OCFAST_DISABLE : stm32h7xx_hal_tim.h
  • TIM_OCFAST_ENABLE : stm32h7xx_hal_tim.h
  • TIM_OCIDLESTATE_RESET : stm32h7xx_hal_tim.h
  • TIM_OCIDLESTATE_SET : stm32h7xx_hal_tim.h
  • TIM_OCMODE_ACTIVE : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_ASSYMETRIC_PWM1 : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_ASSYMETRIC_PWM2 : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_COMBINED_PWM1 : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_COMBINED_PWM2 : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_FORCED_ACTIVE : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_FORCED_INACTIVE : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_INACTIVE : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_PWM1 : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_PWM2 : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_RETRIGERRABLE_OPM1 : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_RETRIGERRABLE_OPM2 : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_TIMING : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_TOGGLE : stm32h7xx_hal_tim_ex.h
  • TIM_OCNIDLESTATE_RESET : stm32h7xx_hal_tim.h
  • TIM_OCNIDLESTATE_SET : stm32h7xx_hal_tim.h
  • TIM_OCNPOLARITY_HIGH : stm32h7xx_hal_tim.h
  • TIM_OCNPOLARITY_LOW : stm32h7xx_hal_tim.h
  • TIM_OCPOLARITY_HIGH : stm32h7xx_hal_tim.h
  • TIM_OCPOLARITY_LOW : stm32h7xx_hal_tim.h
  • TIM_OPMODE_REPETITIVE : stm32h7xx_hal_tim.h
  • TIM_OPMODE_SINGLE : stm32h7xx_hal_tim.h
  • TIM_OSSI_DISABLE : stm32h7xx_hal_tim.h
  • TIM_OSSI_ENABLE : stm32h7xx_hal_tim.h
  • TIM_OSSR_DISABLE : stm32h7xx_hal_tim.h
  • TIM_OSSR_ENABLE : stm32h7xx_hal_tim.h
  • TIM_OUTPUTSTATE_DISABLE : stm32h7xx_hal_tim.h
  • TIM_OUTPUTSTATE_ENABLE : stm32h7xx_hal_tim.h
  • TIM_RESET_CAPTUREPOLARITY : stm32h7xx_hal_tim.h
  • TIM_RESET_ICPRESCALERVALUE : stm32h7xx_hal_tim.h
  • TIM_SET_CAPTUREPOLARITY : stm32h7xx_hal_tim.h
  • TIM_SET_ICPRESCALERVALUE : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_DISABLE : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_EXTERNAL1 : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_GATED : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_RESET : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_SlaveTimer_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_TI1_ConfigInputStage() : stm32h7xx_hal_tim.c
  • TIM_TI1_SetConfig() : stm32h7xx_hal_tim.c , stm32h7xx_hal_tim.h
  • TIM_TI1SELECTION_CH1 : stm32h7xx_hal_tim.h
  • TIM_TI1SELECTION_XORCOMBINATION : stm32h7xx_hal_tim.h
  • TIM_TI2_ConfigInputStage() : stm32h7xx_hal_tim.c
  • TIM_TI2_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_TI3_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_TI4_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_TIM15_BKR_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_BKR_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_BKR_DFSDM_BRK0 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_BKR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_RCC_CSI : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_RCC_LSE : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_RCC_MCO2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_TIM2_CH1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_TIM3_CH1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_TIM4_CH1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI2_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI2_TIM2_CH2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI2_TIM3_CH2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI2_TIM4_CH2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_BKR_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_BKR_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_BKR_DFSDM_BRK1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_BKR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_TI1_RCC_LSE : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_TI1_RCC_LSI : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_TI1_WKUP_IT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_BKR_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_BKR_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_BKR_DFSDM_BRK2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_BKR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_TI1_RCC_HSE1MHZ : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_TI1_RCC_MCO1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_TI1_SPDIF_FS : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_BKR2_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_BKR2_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_BKR2_DFSDM_BRK1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_BKR2_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_BKR_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_BKR_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_BKR_DFSDM_BRK0 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_BKR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD3 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC3_AWD1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC3_AWD2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC3_AWD3 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_TI1_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_RCC_LSE : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_SAI1_FSA : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_SAI1_FSB : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP1COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_TI4_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_ETR_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP1COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_ETR_SAI2_FSA : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_ETR_SAI2_FSB : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_TI1_CAN_RTP : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_TI1_CAN_TMP : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_BKR2_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_BKR2_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_BKR2_DFSDM_BRK3 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_BKR2_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_BKR_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_BKR_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_BKR_DFSDM_BRK2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_BKR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD3 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC3_AWD1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC3_AWD2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC3_AWD3 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_TI1_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TRGO2_ENABLE : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC1 : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC1REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC2REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC3REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC4REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_RISING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISINGFALLING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC5REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_RISING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC6REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC6REF_RISINGFALLING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_RESET : stm32h7xx_hal_tim.h
  • TIM_TRGO2_UPDATE : stm32h7xx_hal_tim.h
  • TIM_TRGO_ENABLE : stm32h7xx_hal_tim.h
  • TIM_TRGO_OC1 : stm32h7xx_hal_tim.h
  • TIM_TRGO_OC1REF : stm32h7xx_hal_tim.h
  • TIM_TRGO_OC2REF : stm32h7xx_hal_tim.h
  • TIM_TRGO_OC3REF : stm32h7xx_hal_tim.h
  • TIM_TRGO_OC4REF : stm32h7xx_hal_tim.h
  • TIM_TRGO_RESET : stm32h7xx_hal_tim.h
  • TIM_TRGO_UPDATE : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_BOTHEDGE : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_FALLING : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_INVERTED : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_NONINVERTED : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_RISING : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV1 : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV2 : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV4 : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV8 : stm32h7xx_hal_tim.h
  • TIM_TS_ETRF : stm32h7xx_hal_tim.h
  • TIM_TS_ITR0 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR1 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR2 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR3 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR4 : stm32h7xx_hal_tim_ex.h
  • TIM_TS_ITR5 : stm32h7xx_hal_tim_ex.h
  • TIM_TS_ITR6 : stm32h7xx_hal_tim_ex.h
  • TIM_TS_ITR7 : stm32h7xx_hal_tim_ex.h
  • TIM_TS_ITR8 : stm32h7xx_hal_tim_ex.h
  • TIM_TS_NONE : stm32h7xx_hal_tim.h
  • TIM_TS_TI1F_ED : stm32h7xx_hal_tim.h
  • TIM_TS_TI1FP1 : stm32h7xx_hal_tim.h
  • TIM_TS_TI2FP2 : stm32h7xx_hal_tim.h
  • TIMEOUT_DAC_CALIBCONFIG : stm32h7xx_hal_dac.c
  • TimerIdxToTimerId : stm32h7xx_hal_hrtim.c
  • TIMING_CLEAR_MASK : stm32h7xx_hal_smbus.c , stm32h7xx_hal_i2c.c
  • TIMx_ETRSEL_MASK : stm32h7xx_hal_tim_ex.c
  • TIMx_TIxSEL_MASK : stm32h7xx_hal_tim_ex.c
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- u -

  • UART_ADDRESS_DETECT_4B : stm32h7xx_hal_uart_ex.h
  • UART_ADDRESS_DETECT_7B : stm32h7xx_hal_uart_ex.h
  • UART_ADVFEATURE_AUTOBAUDRATE_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DATAINVERT_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DMA_DISABLEONRXERROR : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DMA_ENABLEONRXERROR : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DMADISABLEONERROR_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_NO_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_RXINVERT_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_TXINVERT_INIT : stm32h7xx_hal_uart.h
  • UART_AdvFeatureConfig() : stm32h7xx_hal_uart.c
  • UART_AUTOBAUD_REQUEST : stm32h7xx_hal_uart.h
  • UART_CheckIdleState() : stm32h7xx_hal_uart.c
  • UART_CLEAR_CMF : stm32h7xx_hal_uart.h
  • UART_CLEAR_CTSF : stm32h7xx_hal_uart.h
  • UART_CLEAR_FEF : stm32h7xx_hal_uart.h
  • UART_CLEAR_IDLEF : stm32h7xx_hal_uart.h
  • UART_CLEAR_LBDF : stm32h7xx_hal_uart.h
  • UART_CLEAR_NEF : stm32h7xx_hal_uart.h
  • UART_CLEAR_OREF : stm32h7xx_hal_uart.h
  • UART_CLEAR_PEF : stm32h7xx_hal_uart.h
  • UART_CLEAR_RTOF : stm32h7xx_hal_uart.h
  • UART_CLEAR_TCF : stm32h7xx_hal_uart.h
  • UART_CLEAR_TXFECF : stm32h7xx_hal_uart.h
  • UART_CLEAR_WUF : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_CSI : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_D2PCLK1 : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_D2PCLK2 : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_D3PCLK1 : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_HSI : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_LSE : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_PLL2 : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_PLL3 : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_UNDEFINED : stm32h7xx_hal_uart.h
  • UART_ClockSourceTypeDef : stm32h7xx_hal_uart.h
  • UART_CR1_DEAT_ADDRESS_LSB_POS : stm32h7xx_hal_uart.h
  • UART_CR1_DEDT_ADDRESS_LSB_POS : stm32h7xx_hal_uart.h
  • UART_CR1_FIELDS : stm32h7xx_hal_uart.c
  • UART_CR2_ADDRESS_LSB_POS : stm32h7xx_hal_uart.h
  • UART_DE_POLARITY_HIGH : stm32h7xx_hal_uart.h
  • UART_DE_POLARITY_LOW : stm32h7xx_hal_uart.h
  • UART_DIV_LPUART : stm32h7xx_hal_uart.h
  • UART_DIV_SAMPLING16 : stm32h7xx_hal_uart.h
  • UART_DIV_SAMPLING8 : stm32h7xx_hal_uart.h
  • UART_DMA_RX_DISABLE : stm32h7xx_hal_uart.h
  • UART_DMA_RX_ENABLE : stm32h7xx_hal_uart.h
  • UART_DMA_TX_DISABLE : stm32h7xx_hal_uart.h
  • UART_DMA_TX_ENABLE : stm32h7xx_hal_uart.h
  • UART_DMAAbortOnError() : stm32h7xx_hal_uart.c
  • UART_DMAError() : stm32h7xx_hal_uart.c
  • UART_DMAReceiveCplt() : stm32h7xx_hal_uart.c
  • UART_DMARxAbortCallback() : stm32h7xx_hal_uart.c
  • UART_DMARxHalfCplt() : stm32h7xx_hal_uart.c
  • UART_DMARxOnlyAbortCallback() : stm32h7xx_hal_uart.c
  • UART_DMATransmitCplt() : stm32h7xx_hal_uart.c
  • UART_DMATxAbortCallback() : stm32h7xx_hal_uart.c
  • UART_DMATxHalfCplt() : stm32h7xx_hal_uart.c
  • UART_DMATxOnlyAbortCallback() : stm32h7xx_hal_uart.c
  • UART_EndRxTransfer() : stm32h7xx_hal_uart.c
  • UART_EndTransmit_IT() : stm32h7xx_hal_uart.c
  • UART_EndTxTransfer() : stm32h7xx_hal_uart.c
  • UART_FIFOMODE_DISABLE : stm32h7xx_hal_uart.h
  • UART_FIFOMODE_ENABLE : stm32h7xx_hal_uart.h
  • UART_FLAG_ABRE : stm32h7xx_hal_uart.h
  • UART_FLAG_ABRF : stm32h7xx_hal_uart.h
  • UART_FLAG_BUSY : stm32h7xx_hal_uart.h
  • UART_FLAG_CMF : stm32h7xx_hal_uart.h
  • UART_FLAG_CTS : stm32h7xx_hal_uart.h
  • UART_FLAG_CTSIF : stm32h7xx_hal_uart.h
  • UART_FLAG_FE : stm32h7xx_hal_uart.h
  • UART_FLAG_IDLE : stm32h7xx_hal_uart.h
  • UART_FLAG_LBDF : stm32h7xx_hal_uart.h
  • UART_FLAG_NE : stm32h7xx_hal_uart.h
  • UART_FLAG_ORE : stm32h7xx_hal_uart.h
  • UART_FLAG_PE : stm32h7xx_hal_uart.h
  • UART_FLAG_REACK : stm32h7xx_hal_uart.h
  • UART_FLAG_RTOF : stm32h7xx_hal_uart.h
  • UART_FLAG_RWU : stm32h7xx_hal_uart.h
  • UART_FLAG_RXFF : stm32h7xx_hal_uart.h
  • UART_FLAG_RXFNE : stm32h7xx_hal_uart.h
  • UART_FLAG_RXFT : stm32h7xx_hal_uart.h
  • UART_FLAG_RXNE : stm32h7xx_hal_uart.h
  • UART_FLAG_SBKF : stm32h7xx_hal_uart.h
  • UART_FLAG_TC : stm32h7xx_hal_uart.h
  • UART_FLAG_TEACK : stm32h7xx_hal_uart.h
  • UART_FLAG_TXE : stm32h7xx_hal_uart.h
  • UART_FLAG_TXFE : stm32h7xx_hal_uart.h
  • UART_FLAG_TXFNF : stm32h7xx_hal_uart.h
  • UART_FLAG_TXFT : stm32h7xx_hal_uart.h
  • UART_FLAG_WUF : stm32h7xx_hal_uart.h
  • UART_GETCLOCKSOURCE : stm32h7xx_hal_uart_ex.h
  • UART_HALF_DUPLEX_DISABLE : stm32h7xx_hal_uart.h
  • UART_HALF_DUPLEX_ENABLE : stm32h7xx_hal_uart.h
  • UART_HWCONTROL_CTS : stm32h7xx_hal_uart.h
  • UART_HWCONTROL_NONE : stm32h7xx_hal_uart.h
  • UART_HWCONTROL_RTS : stm32h7xx_hal_uart.h
  • UART_HWCONTROL_RTS_CTS : stm32h7xx_hal_uart.h
  • UART_INSTANCE_LOWPOWER : stm32h7xx_hal_uart.h
  • UART_IT_CM : stm32h7xx_hal_uart.h
  • UART_IT_CTS : stm32h7xx_hal_uart.h
  • UART_IT_ERR : stm32h7xx_hal_uart.h
  • UART_IT_FE : stm32h7xx_hal_uart.h
  • UART_IT_IDLE : stm32h7xx_hal_uart.h
  • UART_IT_LBD : stm32h7xx_hal_uart.h
  • UART_IT_MASK : stm32h7xx_hal_uart.h
  • UART_IT_NE : stm32h7xx_hal_uart.h
  • UART_IT_ORE : stm32h7xx_hal_uart.h
  • UART_IT_PE : stm32h7xx_hal_uart.h
  • UART_IT_RXFF : stm32h7xx_hal_uart.h
  • UART_IT_RXFT : stm32h7xx_hal_uart.h
  • UART_IT_RXNE : stm32h7xx_hal_uart.h
  • UART_IT_TC : stm32h7xx_hal_uart.h
  • UART_IT_TXE : stm32h7xx_hal_uart.h
  • UART_IT_TXFE : stm32h7xx_hal_uart.h
  • UART_IT_TXFT : stm32h7xx_hal_uart.h
  • UART_IT_WUF : stm32h7xx_hal_uart.h
  • UART_LIN_DISABLE : stm32h7xx_hal_uart.h
  • UART_LIN_ENABLE : stm32h7xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_10B : stm32h7xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_11B : stm32h7xx_hal_uart.h
  • UART_LPUART_BRR_MAX : stm32h7xx_hal_uart.c
  • UART_LPUART_BRR_MIN : stm32h7xx_hal_uart.c
  • UART_MASK_COMPUTATION : stm32h7xx_hal_uart_ex.h
  • UART_MODE_RX : stm32h7xx_hal_uart.h
  • UART_MODE_TX : stm32h7xx_hal_uart.h
  • UART_MODE_TX_RX : stm32h7xx_hal_uart.h
  • UART_MUTE_MODE_REQUEST : stm32h7xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_uart.h
  • UART_OVERSAMPLING_16 : stm32h7xx_hal_uart.h
  • UART_OVERSAMPLING_8 : stm32h7xx_hal_uart.h
  • UART_PARITY_EVEN : stm32h7xx_hal_uart.h
  • UART_PARITY_NONE : stm32h7xx_hal_uart.h
  • UART_PARITY_ODD : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV1 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV10 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV12 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV128 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV16 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV2 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV256 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV32 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV4 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV6 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV64 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV8 : stm32h7xx_hal_uart.h
  • UART_Receive_IT() : stm32h7xx_hal_uart.c
  • UART_RECEIVER_TIMEOUT_DISABLE : stm32h7xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_ENABLE : stm32h7xx_hal_uart.h
  • UART_RXDATA_FLUSH_REQUEST : stm32h7xx_hal_uart.h
  • UART_RXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_uart.h
  • UART_RXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_uart.h
  • UART_RXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_uart.h
  • UART_RXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_uart.h
  • UART_RXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_uart.h
  • UART_RXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_uart.h
  • UART_SENDBREAK_REQUEST : stm32h7xx_hal_uart.h
  • UART_SetConfig() : stm32h7xx_hal_uart.c
  • UART_STATE_DISABLE : stm32h7xx_hal_uart.h
  • UART_STATE_ENABLE : stm32h7xx_hal_uart.h
  • UART_STOPBITS_0_5 : stm32h7xx_hal_uart.h
  • UART_STOPBITS_1 : stm32h7xx_hal_uart.h
  • UART_STOPBITS_1_5 : stm32h7xx_hal_uart.h
  • UART_STOPBITS_2 : stm32h7xx_hal_uart.h
  • UART_Transmit_IT() : stm32h7xx_hal_uart.c
  • UART_TXDATA_FLUSH_REQUEST : stm32h7xx_hal_uart.h
  • UART_TXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_uart.h
  • UART_TXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_uart.h
  • UART_TXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_uart.h
  • UART_TXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_uart.h
  • UART_TXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_uart.h
  • UART_TXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_uart.h
  • UART_WaitOnFlagUntilTimeout() : stm32h7xx_hal_uart.c
  • UART_WAKEUP_ON_ADDRESS : stm32h7xx_hal_uart.h
  • UART_WAKEUP_ON_READDATA_NONEMPTY : stm32h7xx_hal_uart.h
  • UART_WAKEUP_ON_RXFIFO_FULL : stm32h7xx_hal_uart.h
  • UART_WAKEUP_ON_RXFIFO_THRESHOLD : stm32h7xx_hal_uart.h
  • UART_WAKEUP_ON_STARTBIT : stm32h7xx_hal_uart.h
  • UART_WAKEUP_ON_TXFIFO_EMPTY : stm32h7xx_hal_uart.h
  • UART_WAKEUP_ON_TXFIFO_THRESHOLD : stm32h7xx_hal_uart.h
  • UART_WAKEUPMETHOD_ADDRESSMARK : stm32h7xx_hal_uart.h
  • UART_WAKEUPMETHOD_IDLELINE : stm32h7xx_hal_uart.h
  • UART_WORDLENGTH_7B : stm32h7xx_hal_uart_ex.h
  • UART_WORDLENGTH_8B : stm32h7xx_hal_uart_ex.h
  • UART_WORDLENGTH_9B : stm32h7xx_hal_uart_ex.h
  • UARTEx_Wakeup_AddressConfig() : stm32h7xx_hal_uart_ex.c
  • UARTPrescTable : stm32h7xx_hal_uart.h
  • USART_CheckIdleState() : stm32h7xx_hal_usart.c
  • USART_CLEAR_FEF : stm32h7xx_hal_usart.h
  • USART_CLEAR_IDLEF : stm32h7xx_hal_usart.h
  • USART_CLEAR_NEF : stm32h7xx_hal_usart.h
  • USART_CLEAR_OREF : stm32h7xx_hal_usart.h
  • USART_CLEAR_PEF : stm32h7xx_hal_usart.h
  • USART_CLEAR_TCF : stm32h7xx_hal_usart.h
  • USART_CLEAR_TXFECF : stm32h7xx_hal_usart.h
  • USART_CLEAR_UDRCF : stm32h7xx_hal_usart.h
  • USART_CLOCK_DISABLE : stm32h7xx_hal_usart.h
  • USART_CLOCK_ENABLE : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_CSI : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_D2PCLK1 : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_D2PCLK2 : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_D3PCLK1 : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_HSI : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_LSE : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_PLL2 : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_PLL3 : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_UNDEFINED : stm32h7xx_hal_usart.h
  • USART_ClockSourceTypeDef : stm32h7xx_hal_usart.h
  • USART_CR1_FIELDS : stm32h7xx_hal_usart.c , stm32h7xx_hal_smartcard.c
  • USART_CR2_CLK_FIELDS : stm32h7xx_hal_smartcard.c
  • USART_CR2_FIELDS : stm32h7xx_hal_smartcard.c , stm32h7xx_hal_usart.c
  • USART_CR3_FIELDS : stm32h7xx_hal_smartcard.c , stm32h7xx_hal_uart.c , stm32h7xx_hal_usart.c
  • USART_DIV_SAMPLING8 : stm32h7xx_hal_usart.h
  • USART_DMAAbortOnError() : stm32h7xx_hal_usart.c
  • USART_DMAError() : stm32h7xx_hal_usart.c
  • USART_DMAReceiveCplt() : stm32h7xx_hal_usart.c
  • USART_DMARxAbortCallback() : stm32h7xx_hal_usart.c
  • USART_DMARxHalfCplt() : stm32h7xx_hal_usart.c
  • USART_DMATransmitCplt() : stm32h7xx_hal_usart.c
  • USART_DMATxAbortCallback() : stm32h7xx_hal_usart.c
  • USART_DMATxHalfCplt() : stm32h7xx_hal_usart.c
  • USART_DUMMY_DATA : stm32h7xx_hal_usart.c
  • USART_EndTransfer() : stm32h7xx_hal_usart.c
  • USART_EndTransmit_IT() : stm32h7xx_hal_usart.c
  • USART_FIFOMODE_DISABLE : stm32h7xx_hal_usart.h
  • USART_FIFOMODE_ENABLE : stm32h7xx_hal_usart.h
  • USART_FLAG_BUSY : stm32h7xx_hal_usart.h
  • USART_FLAG_FE : stm32h7xx_hal_usart.h
  • USART_FLAG_IDLE : stm32h7xx_hal_usart.h
  • USART_FLAG_LBDF : stm32h7xx_hal_usart.h
  • USART_FLAG_NE : stm32h7xx_hal_usart.h
  • USART_FLAG_ORE : stm32h7xx_hal_usart.h
  • USART_FLAG_PE : stm32h7xx_hal_usart.h
  • USART_FLAG_REACK : stm32h7xx_hal_usart.h
  • USART_FLAG_RXFF : stm32h7xx_hal_usart.h
  • USART_FLAG_RXFNE : stm32h7xx_hal_usart.h
  • USART_FLAG_RXFT : stm32h7xx_hal_usart.h
  • USART_FLAG_RXNE : stm32h7xx_hal_usart.h
  • USART_FLAG_TC : stm32h7xx_hal_usart.h
  • USART_FLAG_TEACK : stm32h7xx_hal_usart.h
  • USART_FLAG_TXE : stm32h7xx_hal_usart.h
  • USART_FLAG_TXFE : stm32h7xx_hal_usart.h
  • USART_FLAG_TXFNF : stm32h7xx_hal_usart.h
  • USART_FLAG_TXFT : stm32h7xx_hal_usart.h
  • USART_FLAG_UDR : stm32h7xx_hal_usart.h
  • USART_GETCLOCKSOURCE : stm32h7xx_hal_usart.h
  • USART_IT_ERR : stm32h7xx_hal_usart.h
  • USART_IT_FE : stm32h7xx_hal_usart.h
  • USART_IT_IDLE : stm32h7xx_hal_usart.h
  • USART_IT_MASK : stm32h7xx_hal_usart.h
  • USART_IT_NE : stm32h7xx_hal_usart.h
  • USART_IT_ORE : stm32h7xx_hal_usart.h
  • USART_IT_PE : stm32h7xx_hal_usart.h
  • USART_IT_RXFF : stm32h7xx_hal_usart.h
  • USART_IT_RXFT : stm32h7xx_hal_usart.h
  • USART_IT_RXNE : stm32h7xx_hal_usart.h
  • USART_IT_TC : stm32h7xx_hal_usart.h
  • USART_IT_TXE : stm32h7xx_hal_usart.h
  • USART_IT_TXFE : stm32h7xx_hal_usart.h
  • USART_IT_TXFT : stm32h7xx_hal_usart.h
  • USART_IT_UDR : stm32h7xx_hal_usart.h
  • USART_LASTBIT_DISABLE : stm32h7xx_hal_usart.h
  • USART_LASTBIT_ENABLE : stm32h7xx_hal_usart.h
  • USART_MASK_COMPUTATION : stm32h7xx_hal_usart_ex.h
  • USART_MODE_RX : stm32h7xx_hal_usart.h
  • USART_MODE_TX : stm32h7xx_hal_usart.h
  • USART_MODE_TX_RX : stm32h7xx_hal_usart.h
  • USART_NSS_HW : stm32h7xx_hal_usart.h
  • USART_NSS_SW : stm32h7xx_hal_usart.h
  • USART_OVERSAMPLING_16 : stm32h7xx_hal_usart.h
  • USART_OVERSAMPLING_8 : stm32h7xx_hal_usart.h
  • USART_PARITY_EVEN : stm32h7xx_hal_usart.h
  • USART_PARITY_NONE : stm32h7xx_hal_usart.h
  • USART_PARITY_ODD : stm32h7xx_hal_usart.h
  • USART_PHASE_1EDGE : stm32h7xx_hal_usart.h
  • USART_PHASE_2EDGE : stm32h7xx_hal_usart.h
  • USART_POLARITY_HIGH : stm32h7xx_hal_usart.h
  • USART_POLARITY_LOW : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV1 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV10 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV12 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV128 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV16 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV2 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV256 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV32 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV4 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV6 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV64 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV8 : stm32h7xx_hal_usart.h
  • USART_Receive_IT() : stm32h7xx_hal_usart.c
  • USART_RXDATA_FLUSH_REQUEST : stm32h7xx_hal_usart.h
  • USART_RXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_usart.h
  • USART_RXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_usart.h
  • USART_RXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_usart.h
  • USART_RXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_usart.h
  • USART_RXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_usart.h
  • USART_RXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_usart.h
  • USART_SetConfig() : stm32h7xx_hal_usart.c
  • USART_SLAVEMODE_DISABLE : stm32h7xx_hal_usart.h
  • USART_SLAVEMODE_ENABLE : stm32h7xx_hal_usart.h
  • USART_STOPBITS_0_5 : stm32h7xx_hal_usart.h
  • USART_STOPBITS_1 : stm32h7xx_hal_usart.h
  • USART_STOPBITS_1_5 : stm32h7xx_hal_usart.h
  • USART_STOPBITS_2 : stm32h7xx_hal_usart.h
  • USART_TEACK_REACK_TIMEOUT : stm32h7xx_hal_usart.c
  • USART_Transmit_IT() : stm32h7xx_hal_usart.c
  • USART_TransmitReceive_IT() : stm32h7xx_hal_usart.c
  • USART_TXDATA_FLUSH_REQUEST : stm32h7xx_hal_usart.h
  • USART_TXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_usart.h
  • USART_TXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_usart.h
  • USART_TXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_usart.h
  • USART_TXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_usart.h
  • USART_TXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_usart.h
  • USART_TXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_usart.h
  • USART_WaitOnFlagUntilTimeout() : stm32h7xx_hal_usart.c
  • USART_WORDLENGTH_7B : stm32h7xx_hal_usart_ex.h
  • USART_WORDLENGTH_8B : stm32h7xx_hal_usart_ex.h
  • USART_WORDLENGTH_9B : stm32h7xx_hal_usart_ex.h
  • USARTPrescTable : stm32h7xx_hal_usart.h
  • USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_LINE : stm32h7xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE : stm32h7xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_LINE : stm32h7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE : stm32h7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • USBD_FS_TRDT_VALUE : stm32h7xx_hal_pcd.h
  • USBD_HS_TRDT_VALUE : stm32h7xx_hal_pcd.h
  • USE_RTOS : stm32h7xx_hal_conf.h
  • USE_SD_TRANSCEIVER : stm32h7xx_hal_conf.h
  • uwNORMemoryDataWidth : stm32h7xx_hal_nor.c
  • uwTick : stm32h7xx_hal.c
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- v -

  • v_dfsdm1ChannelCounter : stm32h7xx_hal_dfsdm.c
  • VDD_VALUE : stm32h7xx_hal_conf.h
  • VREFBUF_TIMEOUT_VALUE : stm32h7xx_hal.c
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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  • Typedefs
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- w -

  • WWDG_EWI_DISABLE : stm32h7xx_hal_wwdg.h
  • WWDG_EWI_ENABLE : stm32h7xx_hal_wwdg.h
  • WWDG_FLAG_EWIF : stm32h7xx_hal_wwdg.h
  • WWDG_IT_EWI : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_1 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_128 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_16 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_2 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_32 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_4 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_64 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_8 : stm32h7xx_hal_wwdg.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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  • Globals
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  • Functions
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  • Typedefs
  • Enumerations
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  • i
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  • s
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  • u

- a -

  • ADC_ConversionStop() : stm32h7xx_hal_adc.c
  • ADC_Disable() : stm32h7xx_hal_adc.c
  • ADC_DMAConvCplt() : stm32h7xx_hal_adc.c
  • ADC_DMAError() : stm32h7xx_hal_adc.c
  • ADC_DMAHalfConvCplt() : stm32h7xx_hal_adc.c
  • ADC_Enable() : stm32h7xx_hal_adc.c
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
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- c -

  • CRC_Handle_16() : stm32h7xx_hal_crc.c
  • CRC_Handle_8() : stm32h7xx_hal_crc.c
  • CRYP_AES_Decrypt() : stm32h7xx_hal_cryp.c
  • CRYP_AES_Decrypt_DMA() : stm32h7xx_hal_cryp.c
  • CRYP_AES_Decrypt_IT() : stm32h7xx_hal_cryp.c
  • CRYP_AES_Encrypt() : stm32h7xx_hal_cryp.c
  • CRYP_AES_Encrypt_IT() : stm32h7xx_hal_cryp.c
  • CRYP_AES_IT() : stm32h7xx_hal_cryp.c
  • CRYP_AES_ProcessData() : stm32h7xx_hal_cryp.c
  • CRYP_AESCCM_Process() : stm32h7xx_hal_cryp.c
  • CRYP_AESCCM_Process_DMA() : stm32h7xx_hal_cryp.c
  • CRYP_AESCCM_Process_IT() : stm32h7xx_hal_cryp.c
  • CRYP_AESGCM_Process() : stm32h7xx_hal_cryp.c
  • CRYP_AESGCM_Process_DMA() : stm32h7xx_hal_cryp.c
  • CRYP_AESGCM_Process_IT() : stm32h7xx_hal_cryp.c
  • CRYP_DMAError() : stm32h7xx_hal_cryp.c
  • CRYP_DMAInCplt() : stm32h7xx_hal_cryp.c
  • CRYP_DMAOutCplt() : stm32h7xx_hal_cryp.c
  • CRYP_GCMCCM_SetHeaderPhase() : stm32h7xx_hal_cryp.c
  • CRYP_GCMCCM_SetHeaderPhase_DMA() : stm32h7xx_hal_cryp.c
  • CRYP_GCMCCM_SetHeaderPhase_IT() : stm32h7xx_hal_cryp.c
  • CRYP_GCMCCM_SetPayloadPhase_IT() : stm32h7xx_hal_cryp.c
  • CRYP_SetDMAConfig() : stm32h7xx_hal_cryp.c
  • CRYP_SetKey() : stm32h7xx_hal_cryp.c
  • CRYP_TDES_IT() : stm32h7xx_hal_cryp.c
  • CRYP_TDES_Process() : stm32h7xx_hal_cryp.c
  • CRYP_WaitOnBUSYFlag() : stm32h7xx_hal_cryp.c
  • CRYP_WaitOnIFEMFlag() : stm32h7xx_hal_cryp.c
  • CRYP_WaitOnOFNEFlag() : stm32h7xx_hal_cryp.c
  • CRYP_Workaround() : stm32h7xx_hal_cryp.c
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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  • Typedefs
  • Enumerations
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  • u

- d -

  • DAC_DMAConvCpltCh1() : stm32h7xx_hal_dac.c
  • DAC_DMAConvCpltCh2() : stm32h7xx_hal_dac_ex.c
  • DAC_DMAErrorCh1() : stm32h7xx_hal_dac.c
  • DAC_DMAErrorCh2() : stm32h7xx_hal_dac_ex.c
  • DAC_DMAHalfConvCpltCh1() : stm32h7xx_hal_dac.c
  • DAC_DMAHalfConvCpltCh2() : stm32h7xx_hal_dac_ex.c
  • DCMI_DMAError() : stm32h7xx_hal_dcmi.c
  • DCMI_DMAXferCplt() : stm32h7xx_hal_dcmi.c
  • DFSDM_DMAError() : stm32h7xx_hal_dfsdm.c
  • DFSDM_DMAInjectedConvCplt() : stm32h7xx_hal_dfsdm.c
  • DFSDM_DMAInjectedHalfConvCplt() : stm32h7xx_hal_dfsdm.c
  • DFSDM_DMARegularConvCplt() : stm32h7xx_hal_dfsdm.c
  • DFSDM_DMARegularHalfConvCplt() : stm32h7xx_hal_dfsdm.c
  • DFSDM_GetChannelFromInstance() : stm32h7xx_hal_dfsdm.c
  • DFSDM_GetInjChannelsNbr() : stm32h7xx_hal_dfsdm.c
  • DFSDM_InjConvStart() : stm32h7xx_hal_dfsdm.c
  • DFSDM_InjConvStop() : stm32h7xx_hal_dfsdm.c
  • DFSDM_RegConvStart() : stm32h7xx_hal_dfsdm.c
  • DFSDM_RegConvStop() : stm32h7xx_hal_dfsdm.c
  • DMA2D_SetConfig() : stm32h7xx_hal_dma2d.c
  • DMA_CalcBaseAndBitshift() : stm32h7xx_hal_dma.c
  • DMA_CalcDMAMUXChannelBaseAndMask() : stm32h7xx_hal_dma.c
  • DMA_CalcDMAMUXRequestGenBaseAndMask() : stm32h7xx_hal_dma.c
  • DMA_CheckFifoParam() : stm32h7xx_hal_dma.c
  • DMA_MultiBufferSetConfig() : stm32h7xx_hal_dma_ex.c
  • DMA_SetConfig() : stm32h7xx_hal_dma.c
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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  • u

- e -

  • ETH_DMARxDescListInit() : stm32h7xx_hal_eth.c
  • ETH_DMATxDescListInit() : stm32h7xx_hal_eth.c
  • ETH_MAC_MDIO_ClkConfig() : stm32h7xx_hal_eth.c
  • ETH_MACDMAConfig() : stm32h7xx_hal_eth.c
  • ETH_Prepare_Tx_Descriptors() : stm32h7xx_hal_eth.c
  • ETH_SetDMAConfig() : stm32h7xx_hal_eth.c
  • ETH_SetMACConfig() : stm32h7xx_hal_eth.c
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
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  • Functions
  • Variables
  • Typedefs
  • Enumerations
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- f -

  • FDCAN_CalcultateRamBlockAddresses() : stm32h7xx_hal_fdcan.c
  • FDCAN_CopyMessageToRAM() : stm32h7xx_hal_fdcan.c
  • FLASH_Erase_Sector() : stm32h7xx_hal_flash_ex.h , stm32h7xx_hal_flash_ex.c
  • FLASH_MassErase() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_BootAddConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_BOR_LevelConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_DisableWRP() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_EnableWRP() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetBootAdd() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetBOR() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetPCROP() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetRDP() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetSecureArea() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetUser() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_GetWRP() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_PCROPConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_RDPConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_SecureAreaConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_UserConfig() : stm32h7xx_hal_flash_ex.c
  • FLASH_OB_WaitForLastOperation() : stm32h7xx_hal_flash.h , stm32h7xx_hal_flash.c
  • FLASH_SetErrorCode() : stm32h7xx_hal_flash.c
  • FLASH_WaitForLastOperation() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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  • GetTimerIdxFromDMAHandle() : stm32h7xx_hal_hrtim.c
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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- h -

  • HAL_ADC_AnalogWDGConfig() : stm32h7xx_hal_adc.c
  • HAL_ADC_ConfigChannel() : stm32h7xx_hal_adc.c
  • HAL_ADC_ConvCpltCallback() : stm32h7xx_hal_adc.c
  • HAL_ADC_ConvHalfCpltCallback() : stm32h7xx_hal_adc.c
  • HAL_ADC_DeInit() : stm32h7xx_hal_adc.c
  • HAL_ADC_ErrorCallback() : stm32h7xx_hal_adc.c
  • HAL_ADC_GetError() : stm32h7xx_hal_adc.c
  • HAL_ADC_GetState() : stm32h7xx_hal_adc.c
  • HAL_ADC_GetValue() : stm32h7xx_hal_adc.c
  • HAL_ADC_Init() : stm32h7xx_hal_adc.c
  • HAL_ADC_IRQHandler() : stm32h7xx_hal_adc.c
  • HAL_ADC_LevelOutOfWindowCallback() : stm32h7xx_hal_adc.c
  • HAL_ADC_MspDeInit() : stm32h7xx_hal_adc.c
  • HAL_ADC_MspInit() : stm32h7xx_hal_adc.c
  • HAL_ADC_PollForConversion() : stm32h7xx_hal_adc.c
  • HAL_ADC_PollForEvent() : stm32h7xx_hal_adc.c
  • HAL_ADC_Start() : stm32h7xx_hal_adc.c
  • HAL_ADC_Start_DMA() : stm32h7xx_hal_adc.c
  • HAL_ADC_Start_IT() : stm32h7xx_hal_adc.c
  • HAL_ADC_Stop() : stm32h7xx_hal_adc.c
  • HAL_ADC_Stop_DMA() : stm32h7xx_hal_adc.c
  • HAL_ADC_Stop_IT() : stm32h7xx_hal_adc.c
  • HAL_ADCEx_Calibration_GetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_SetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_Start() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_DisableInjectedQueue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_DisableVoltageRegulator() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_EnableInjectedQueue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_EndOfSamplingCallback() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_EnterADCDeepPowerDownMode() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConfigChannel() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConvCpltCallback() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedGetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedPollForConversion() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedQueueOverflowCallback() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart_IT() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop_IT() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow2Callback() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow3Callback() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_LinearCalibration_GetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_LinearCalibration_SetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeConfigChannel() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeGetValue() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStart_DMA() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStop_DMA() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_RegularMultiModeStop_DMA() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop_DMA() : stm32h7xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop_IT() : stm32h7xx_hal_adc_ex.c
  • HAL_CEC_ChangeRxBuffer() : stm32h7xx_hal_cec.c
  • HAL_CEC_DeInit() : stm32h7xx_hal_cec.c
  • HAL_CEC_ErrorCallback() : stm32h7xx_hal_cec.c
  • HAL_CEC_GetError() : stm32h7xx_hal_cec.c
  • HAL_CEC_GetLastReceivedFrameSize() : stm32h7xx_hal_cec.c
  • HAL_CEC_GetState() : stm32h7xx_hal_cec.c
  • HAL_CEC_Init() : stm32h7xx_hal_cec.c
  • HAL_CEC_IRQHandler() : stm32h7xx_hal_cec.c
  • HAL_CEC_MspDeInit() : stm32h7xx_hal_cec.c
  • HAL_CEC_MspInit() : stm32h7xx_hal_cec.c
  • HAL_CEC_RxCpltCallback() : stm32h7xx_hal_cec.c
  • HAL_CEC_SetDeviceAddress() : stm32h7xx_hal_cec.c
  • HAL_CEC_Transmit_IT() : stm32h7xx_hal_cec.c
  • HAL_CEC_TxCpltCallback() : stm32h7xx_hal_cec.c
  • HAL_COMP_DeInit() : stm32h7xx_hal_comp.c
  • HAL_COMP_GetOutputLevel() : stm32h7xx_hal_comp.c
  • HAL_COMP_GetState() : stm32h7xx_hal_comp.c
  • HAL_COMP_Init() : stm32h7xx_hal_comp.c
  • HAL_COMP_IRQHandler() : stm32h7xx_hal_comp.c
  • HAL_COMP_Lock() : stm32h7xx_hal_comp.c
  • HAL_COMP_MspDeInit() : stm32h7xx_hal_comp.c
  • HAL_COMP_MspInit() : stm32h7xx_hal_comp.c
  • HAL_COMP_Start() : stm32h7xx_hal_comp.c
  • HAL_COMP_Start_IT() : stm32h7xx_hal_comp.c
  • HAL_COMP_Stop() : stm32h7xx_hal_comp.c
  • HAL_COMP_Stop_IT() : stm32h7xx_hal_comp.c
  • HAL_COMP_TriggerCallback() : stm32h7xx_hal_comp.c
  • HAL_CRC_Accumulate() : stm32h7xx_hal_crc.c , stm32h7xx_hal_crc.h
  • HAL_CRC_Calculate() : stm32h7xx_hal_crc.c , stm32h7xx_hal_crc.h
  • HAL_CRC_DeInit() : stm32h7xx_hal_crc.c , stm32h7xx_hal_crc.h
  • HAL_CRC_GetState() : stm32h7xx_hal_crc.c , stm32h7xx_hal_crc.h
  • HAL_CRC_Init() : stm32h7xx_hal_crc.c , stm32h7xx_hal_crc.h
  • HAL_CRC_MspDeInit() : stm32h7xx_hal_crc.c , stm32h7xx_hal_crc.h
  • HAL_CRC_MspInit() : stm32h7xx_hal_crc.c , stm32h7xx_hal_crc.h
  • HAL_CRCEx_Input_Data_Reverse() : stm32h7xx_hal_crc_ex.c
  • HAL_CRCEx_Output_Data_Reverse() : stm32h7xx_hal_crc_ex.c
  • HAL_CRCEx_Polynomial_Set() : stm32h7xx_hal_crc_ex.c
  • HAL_CRYP_Decrypt() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Decrypt_DMA() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Decrypt_IT() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_DeInit() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Encrypt() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Encrypt_DMA() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Encrypt_IT() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_ErrorCallback() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_GetConfig() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_GetError() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_GetState() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_InCpltCallback() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_Init() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_IRQHandler() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_MspDeInit() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_MspInit() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_OutCpltCallback() : stm32h7xx_hal_cryp.c
  • HAL_CRYP_SetConfig() : stm32h7xx_hal_cryp.c
  • HAL_CRYPEx_AESCCM_GenerateAuthTAG() : stm32h7xx_hal_cryp_ex.c
  • HAL_CRYPEx_AESGCM_GenerateAuthTAG() : stm32h7xx_hal_cryp_ex.c
  • HAL_DAC_ConfigChannel() : stm32h7xx_hal_dac.c
  • HAL_DAC_ConvCpltCallbackCh1() : stm32h7xx_hal_dac.c
  • HAL_DAC_ConvHalfCpltCallbackCh1() : stm32h7xx_hal_dac.c
  • HAL_DAC_DeInit() : stm32h7xx_hal_dac.c
  • HAL_DAC_DMAUnderrunCallbackCh1() : stm32h7xx_hal_dac.c
  • HAL_DAC_ErrorCallbackCh1() : stm32h7xx_hal_dac.c
  • HAL_DAC_GetError() : stm32h7xx_hal_dac.c
  • HAL_DAC_GetState() : stm32h7xx_hal_dac.c
  • HAL_DAC_GetValue() : stm32h7xx_hal_dac.c
  • HAL_DAC_Init() : stm32h7xx_hal_dac.c
  • HAL_DAC_IRQHandler() : stm32h7xx_hal_dac.c
  • HAL_DAC_MspDeInit() : stm32h7xx_hal_dac.c
  • HAL_DAC_MspInit() : stm32h7xx_hal_dac.c
  • HAL_DAC_SetValue() : stm32h7xx_hal_dac.c
  • HAL_DAC_Start() : stm32h7xx_hal_dac.c
  • HAL_DAC_Start_DMA() : stm32h7xx_hal_dac.c
  • HAL_DAC_Stop() : stm32h7xx_hal_dac.c
  • HAL_DAC_Stop_DMA() : stm32h7xx_hal_dac.c
  • HAL_DACEx_ConvCpltCallbackCh2() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_ConvHalfCpltCallbackCh2() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_DMAUnderrunCallbackCh2() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_DualGetValue() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_DualSetValue() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_ErrorCallbackCh2() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_GetTrimOffset() : stm32h7xx_hal_dac_ex.c , stm32h7xx_hal_dac_ex.h
  • HAL_DACEx_NoiseWaveGenerate() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_SelfCalibrate() : stm32h7xx_hal_dac_ex.c
  • HAL_DACEx_SetUserTrimming() : stm32h7xx_hal_dac_ex.c , stm32h7xx_hal_dac_ex.h
  • HAL_DACEx_TriangleWaveGenerate() : stm32h7xx_hal_dac_ex.c
  • HAL_DCMI_ConfigCrop() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_DeInit() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_DisableCrop() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_EnableCrop() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_ErrorCallback() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_FrameEventCallback() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_GetError() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_GetState() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_Init() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_IRQHandler() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_LineEventCallback() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_MspDeInit() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_MspInit() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_Resume() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_Start_DMA() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_Stop() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_Suspend() : stm32h7xx_hal_dcmi.c
  • HAL_DCMI_VsyncEventCallback() : stm32h7xx_hal_dcmi.c
  • HAL_DeInit() : stm32h7xx_hal.c
  • HAL_Delay() : stm32h7xx_hal.c
  • HAL_DFSDM_ChannelCkabCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStart() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStart_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStop() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStop_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelDeInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelGetAwdValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelGetState() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelModifyOffset() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelMspDeInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelMspInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelPollForCkab() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelPollForScd() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStart() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStart_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStop() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStop_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterAwdCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterAwdStart_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterAwdStop_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterConfigInjChannel() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterConfigRegChannel() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterDeInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterErrorCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterExdStart() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterExdStop() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetConvTimeValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetError() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetExdMaxValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetExdMinValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetInjectedValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetRegularValue() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetState() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjConvCpltCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjConvHalfCpltCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedMsbStart_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStart() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStart_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStart_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStop() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStop_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStop_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterMspDeInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterMspInit() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterPollForInjConversion() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterPollForRegConversion() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegConvCpltCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegConvHalfCpltCallback() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularMsbStart_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStart() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStart_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStart_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStop() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStop_DMA() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStop_IT() : stm32h7xx_hal_dfsdm.c
  • HAL_DFSDM_IRQHandler() : stm32h7xx_hal_dfsdm.c
  • HAL_DisableCompensationCell() : stm32h7xx_hal.c
  • HAL_DisableDBGSleepMode() : stm32h7xx_hal.c
  • HAL_DisableDBGStandbyMode() : stm32h7xx_hal.c
  • HAL_DisableDBGStopMode() : stm32h7xx_hal.c
  • HAL_DisableDomain3DBGStandbyMode() : stm32h7xx_hal.c
  • HAL_DisableDomain3DBGStopMode() : stm32h7xx_hal.c
  • HAL_DMA2D_Abort() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_BlendingStart() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_BlendingStart_IT() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoad() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoad_IT() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoading_Abort() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoading_Resume() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoading_Suspend() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_CLUTLoadingCpltCallback() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_ConfigCLUT() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_ConfigDeadTime() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_ConfigLayer() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_DeInit() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_DisableDeadTime() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_EnableCLUT() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_EnableDeadTime() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_GetError() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_GetState() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_Init() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_IRQHandler() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_LineEventCallback() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_MspDeInit() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_MspInit() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_PollForTransfer() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_ProgramLineEvent() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_Resume() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_Start() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_Start_IT() : stm32h7xx_hal_dma2d.c
  • HAL_DMA2D_Suspend() : stm32h7xx_hal_dma2d.c
  • HAL_DMA_Abort() : stm32h7xx_hal_dma.c
  • HAL_DMA_Abort_IT() : stm32h7xx_hal_dma.c
  • HAL_DMA_DeInit() : stm32h7xx_hal_dma.c
  • HAL_DMA_GetError() : stm32h7xx_hal_dma.c
  • HAL_DMA_GetState() : stm32h7xx_hal_dma.c
  • HAL_DMA_Init() : stm32h7xx_hal_dma.c
  • HAL_DMA_IRQHandler() : stm32h7xx_hal_dma.c
  • HAL_DMA_PollForTransfer() : stm32h7xx_hal_dma.c
  • HAL_DMA_RegisterCallback() : stm32h7xx_hal_dma.c
  • HAL_DMA_Start() : stm32h7xx_hal_dma.c
  • HAL_DMA_Start_IT() : stm32h7xx_hal_dma.c
  • HAL_DMA_UnRegisterCallback() : stm32h7xx_hal_dma.c
  • HAL_DMAEx_ChangeMemory() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_ConfigMuxRequestGenerator() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_ConfigMuxSync() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_DisableMuxRequestGenerator() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_EnableMuxRequestGenerator() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_MultiBufferStart() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_MultiBufferStart_IT() : stm32h7xx_hal_dma_ex.c
  • HAL_DMAEx_MUX_IRQHandler() : stm32h7xx_hal_dma_ex.c
  • HAL_EnableCompensationCell() : stm32h7xx_hal.c
  • HAL_EnableDBGSleepMode() : stm32h7xx_hal.c
  • HAL_EnableDBGStandbyMode() : stm32h7xx_hal.c
  • HAL_EnableDBGStopMode() : stm32h7xx_hal.c
  • HAL_EnableDomain3DBGStandbyMode() : stm32h7xx_hal.c
  • HAL_EnableDomain3DBGStopMode() : stm32h7xx_hal.c
  • HAL_ETH_BuildRxDescriptors() : stm32h7xx_hal_eth.c
  • HAL_ETH_DeInit() : stm32h7xx_hal_eth.c
  • HAL_ETH_DescAssignMemory() : stm32h7xx_hal_eth.c
  • HAL_ETH_DMAErrorCallback() : stm32h7xx_hal_eth.c
  • HAL_ETH_EEECallback() : stm32h7xx_hal_eth.c
  • HAL_ETH_EnterPowerDownMode() : stm32h7xx_hal_eth.c
  • HAL_ETH_ExitPowerDownMode() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetDMAConfig() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetDMAError() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetError() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetMACConfig() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetMACError() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetMACFilterConfig() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetMACWakeUpSource() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetRxDataBuffer() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetRxDataInfo() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetRxDataLength() : stm32h7xx_hal_eth.c
  • HAL_ETH_GetState() : stm32h7xx_hal_eth.c
  • HAL_ETH_Init() : stm32h7xx_hal_eth.c
  • HAL_ETH_IRQHandler() : stm32h7xx_hal_eth.c
  • HAL_ETH_IsRxDataAvailable() : stm32h7xx_hal_eth.c
  • HAL_ETH_MACErrorCallback() : stm32h7xx_hal_eth.c
  • HAL_ETH_MspDeInit() : stm32h7xx_hal_eth.c
  • HAL_ETH_MspInit() : stm32h7xx_hal_eth.c
  • HAL_ETH_PMTCallback() : stm32h7xx_hal_eth.c
  • HAL_ETH_ReadPHYRegister() : stm32h7xx_hal_eth.c
  • HAL_ETH_RxCpltCallback() : stm32h7xx_hal_eth.c
  • HAL_ETH_SetDMAConfig() : stm32h7xx_hal_eth.c
  • HAL_ETH_SetHashTable() : stm32h7xx_hal_eth.c
  • HAL_ETH_SetMACConfig() : stm32h7xx_hal_eth.c
  • HAL_ETH_SetMACFilterConfig() : stm32h7xx_hal_eth.c
  • HAL_ETH_SetMDIOClockRange() : stm32h7xx_hal_eth.c
  • HAL_ETH_SetRxVLANIdentifier() : stm32h7xx_hal_eth.c
  • HAL_ETH_SetSourceMACAddrMatch() : stm32h7xx_hal_eth.c
  • HAL_ETH_SetWakeUpFilter() : stm32h7xx_hal_eth.c
  • HAL_ETH_Start() : stm32h7xx_hal_eth.c
  • HAL_ETH_Start_IT() : stm32h7xx_hal_eth.c
  • HAL_ETH_Stop() : stm32h7xx_hal_eth.c
  • HAL_ETH_Stop_IT() : stm32h7xx_hal_eth.c
  • HAL_ETH_Transmit() : stm32h7xx_hal_eth.c
  • HAL_ETH_Transmit_IT() : stm32h7xx_hal_eth.c
  • HAL_ETH_TxCpltCallback() : stm32h7xx_hal_eth.c
  • HAL_ETH_WakeUpCallback() : stm32h7xx_hal_eth.c
  • HAL_ETH_WritePHYRegister() : stm32h7xx_hal_eth.c
  • HAL_ETHEx_DisableARPOffload() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_DisableL3L4Filtering() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_DisableVLANProcessing() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_EnableARPOffload() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_EnableL3L4Filtering() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_EnableVLANProcessing() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_EnterLPIMode() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_ExitLPIMode() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_GetL3FilterConfig() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_GetL4FilterConfig() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_GetMACLPIEvent() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_GetRxVLANConfig() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_GetTxVLANConfig() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_SetARPAddressMatch() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_SetL3FilterConfig() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_SetL4FilterConfig() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_SetRxVLANConfig() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_SetTxVLANConfig() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_SetTxVLANIdentifier() : stm32h7xx_hal_eth_ex.c
  • HAL_ETHEx_SetVLANHashTable() : stm32h7xx_hal_eth_ex.c
  • HAL_EXTI_D1_ClearFlag() : stm32h7xx_hal.c
  • HAL_EXTI_D1_EventInputConfig() : stm32h7xx_hal.c
  • HAL_EXTI_D3_EventInputConfig() : stm32h7xx_hal.c
  • HAL_EXTI_EdgeConfig() : stm32h7xx_hal.c
  • HAL_EXTI_GenerateSWInterrupt() : stm32h7xx_hal.c
  • HAL_FDCAN_AbortTxRequest() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ActivateNotification() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_AddMessageToTxBuffer() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_AddMessageToTxFifoQ() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ClockCalibrationCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigClockCalibration() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigExtendedIdMask() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigFifoWatermark() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigFilter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigGlobalFilter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigInterruptLines() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigRamWatchdog() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigRxFifoOverwrite() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTimeoutCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTimestampCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTxDelayCompensation() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DeactivateNotification() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DeInit() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DisableTimeoutCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DisableTimestampCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_DisableTxDelayCompensation() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnableTimeoutCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnableTimestampCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnableTxBufferRequest() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnableTxDelayCompensation() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_EnterPowerDownMode() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ErrorCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ExitPowerDownMode() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ExitRestrictedOperationMode() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetClockCalibrationCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetClockCalibrationState() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetError() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetErrorCounters() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetHighPriorityMessageStatus() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetProtocolStatus() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetRxFifoFillLevel() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetRxMessage() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetState() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetTimeoutCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetTimestampCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetTxEvent() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_GetTxFifoFreeLevel() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_HighPriorityMessageCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_Init() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_IRQHandler() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_IsRestrictedOperationMode() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_IsRxBufferMessageAvailable() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_IsTxBufferMessagePending() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_MspDeInit() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_MspInit() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ResetClockCalibrationState() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ResetTimeoutCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_ResetTimestampCounter() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RxBufferNewMessageCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RxFifo0Callback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_RxFifo1Callback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_Start() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_Stop() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TimeoutOccurredCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TimestampWraparoundCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ActivateNotification() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigExternalSyncPhase() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigInterruptLines() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigOperation() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigReferenceMessage() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigRegisterTimeMark() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigStopWatch() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ConfigTrigger() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DeactivateNotification() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DisableExternalSynchronization() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DisableHardwareGapControl() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DisableRegisterTimeMarkPulse() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DisableTimeMarkGapControl() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_DisableTriggerTimeMarkPulse() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_EnableExternalSynchronization() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_EnableHardwareGapControl() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_EnableRegisterTimeMarkPulse() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_EnableTimeMarkGapControl() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_EnableTriggerTimeMarkPulse() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_GetOperationStatus() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_GlobalTimeCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_ScheduleSyncCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_SetClockSynchronization() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_SetEndOfGap() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_SetGlobalTime() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_SetNextIsGap() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_StopWatchCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TT_TimeMarkCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TxBufferAbortCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TxBufferCompleteCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TxEventFifoCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FDCAN_TxFifoEmptyCallback() : stm32h7xx_hal_fdcan.c
  • HAL_FLASH_EndOfOperationCallback() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASH_GetError() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASH_IRQHandler() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASH_Lock() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASH_OB_Launch() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASH_OB_Lock() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASH_OB_Unlock() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASH_OperationErrorCallback() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASH_Program() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASH_Program_IT() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASH_Unlock() : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash.h
  • HAL_FLASHEx_Erase() : stm32h7xx_hal_flash_ex.c , stm32h7xx_hal_flash_ex.h
  • HAL_FLASHEx_Erase_IT() : stm32h7xx_hal_flash_ex.c , stm32h7xx_hal_flash_ex.h
  • HAL_FLASHEx_Lock_Bank1() : stm32h7xx_hal_flash_ex.c , stm32h7xx_hal_flash_ex.h
  • HAL_FLASHEx_Lock_Bank2() : stm32h7xx_hal_flash_ex.c , stm32h7xx_hal_flash_ex.h
  • HAL_FLASHEx_OBGetConfig() : stm32h7xx_hal_flash_ex.c , stm32h7xx_hal_flash_ex.h
  • HAL_FLASHEx_OBProgram() : stm32h7xx_hal_flash_ex.c , stm32h7xx_hal_flash_ex.h
  • HAL_FLASHEx_Unlock_Bank1() : stm32h7xx_hal_flash_ex.c , stm32h7xx_hal_flash_ex.h
  • HAL_FLASHEx_Unlock_Bank2() : stm32h7xx_hal_flash_ex.c , stm32h7xx_hal_flash_ex.h
  • HAL_GetCurrentCPUID() : stm32h7xx_hal_cortex.c
  • HAL_GetDEVID() : stm32h7xx_hal.c
  • HAL_GetFMCMemorySwappingConfig() : stm32h7xx_hal.c
  • HAL_GetHalVersion() : stm32h7xx_hal.c
  • HAL_GetREVID() : stm32h7xx_hal.c
  • HAL_GetTick() : stm32h7xx_hal.c
  • HAL_GPIO_DeInit() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_EXTI_Callback() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_EXTI_IRQHandler() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_Init() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_LockPin() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_ReadPin() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_TogglePin() : stm32h7xx_hal_gpio.c
  • HAL_GPIO_WritePin() : stm32h7xx_hal_gpio.c
  • HAL_HalfDuplex_EnableReceiver() : stm32h7xx_hal_uart.c
  • HAL_HalfDuplex_EnableTransmitter() : stm32h7xx_hal_uart.c
  • HAL_HalfDuplex_Init() : stm32h7xx_hal_uart.c
  • HAL_HASH_ContextRestoring() : stm32h7xx_hal_hash.c
  • HAL_HASH_ContextSaving() : stm32h7xx_hal_hash.c
  • HAL_HASH_DeInit() : stm32h7xx_hal_hash.c
  • HAL_HASH_DgstCpltCallback() : stm32h7xx_hal_hash.c
  • HAL_HASH_DMAFeed_ProcessSuspend() : stm32h7xx_hal_hash.c
  • HAL_HASH_ErrorCallback() : stm32h7xx_hal_hash.c
  • HAL_HASH_GetState() : stm32h7xx_hal_hash.c
  • HAL_HASH_GetStatus() : stm32h7xx_hal_hash.c
  • HAL_HASH_InCpltCallback() : stm32h7xx_hal_hash.c
  • HAL_HASH_Init() : stm32h7xx_hal_hash.c
  • HAL_HASH_IRQHandler() : stm32h7xx_hal_hash.c
  • HAL_HASH_MD5_Accumulate() : stm32h7xx_hal_hash.c
  • HAL_HASH_MD5_Finish() : stm32h7xx_hal_hash.c
  • HAL_HASH_MD5_Start() : stm32h7xx_hal_hash.c
  • HAL_HASH_MD5_Start_DMA() : stm32h7xx_hal_hash.c
  • HAL_HASH_MD5_Start_IT() : stm32h7xx_hal_hash.c
  • HAL_HASH_MspDeInit() : stm32h7xx_hal_hash.c
  • HAL_HASH_MspInit() : stm32h7xx_hal_hash.c
  • HAL_HASH_SHA1_Accumulate() : stm32h7xx_hal_hash.c
  • HAL_HASH_SHA1_Finish() : stm32h7xx_hal_hash.c
  • HAL_HASH_SHA1_Start() : stm32h7xx_hal_hash.c
  • HAL_HASH_SHA1_Start_DMA() : stm32h7xx_hal_hash.c
  • HAL_HASH_SHA1_Start_IT() : stm32h7xx_hal_hash.c
  • HAL_HASH_SwFeed_ProcessSuspend() : stm32h7xx_hal_hash.c
  • HAL_HASHEx_SHA224_Accumulate() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA224_Finish() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA224_Start() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA224_Start_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA224_Start_IT() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA256_Accumulate() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA256_Finish() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA256_Start() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA256_Start_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HASHEx_SHA256_Start_IT() : stm32h7xx_hal_hash_ex.c
  • HAL_HCD_Connect_Callback() : stm32h7xx_hal_hcd.c
  • HAL_HCD_DeInit() : stm32h7xx_hal_hcd.c
  • HAL_HCD_Disconnect_Callback() : stm32h7xx_hal_hcd.c
  • HAL_HCD_GetCurrentFrame() : stm32h7xx_hal_hcd.c
  • HAL_HCD_GetCurrentSpeed() : stm32h7xx_hal_hcd.c
  • HAL_HCD_GetState() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_GetState() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_GetURBState() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_GetXferCount() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_Halt() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_Init() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_NotifyURBChange_Callback() : stm32h7xx_hal_hcd.c
  • HAL_HCD_HC_SubmitRequest() : stm32h7xx_hal_hcd.c
  • HAL_HCD_Init() : stm32h7xx_hal_hcd.c
  • HAL_HCD_IRQHandler() : stm32h7xx_hal_hcd.c
  • HAL_HCD_MspDeInit() : stm32h7xx_hal_hcd.c
  • HAL_HCD_MspInit() : stm32h7xx_hal_hcd.c
  • HAL_HCD_ResetPort() : stm32h7xx_hal_hcd.c
  • HAL_HCD_SOF_Callback() : stm32h7xx_hal_hcd.c
  • HAL_HCD_Start() : stm32h7xx_hal_hcd.c
  • HAL_HCD_Stop() : stm32h7xx_hal_hcd.c
  • HAL_HMAC_MD5_Start() : stm32h7xx_hal_hash.c
  • HAL_HMAC_MD5_Start_DMA() : stm32h7xx_hal_hash.c
  • HAL_HMAC_MD5_Start_IT() : stm32h7xx_hal_hash.c
  • HAL_HMAC_SHA1_Start() : stm32h7xx_hal_hash.c
  • HAL_HMAC_SHA1_Start_DMA() : stm32h7xx_hal_hash.c
  • HAL_HMAC_SHA1_Start_IT() : stm32h7xx_hal_hash.c
  • HAL_HMACEx_MD5_Step1_2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_MD5_Step2_3_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_MD5_Step2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA1_Step1_2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA1_Step2_3_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA1_Step2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Start() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Start_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Start_IT() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Step1_2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Step2_3_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA224_Step2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Start() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Start_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Start_IT() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Step1_2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Step2_3_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HMACEx_SHA256_Step2_DMA() : stm32h7xx_hal_hash_ex.c
  • HAL_HRTIM_ADCTriggerConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_BurstDMAConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_BurstDMATransfer() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_BurstDMATransferCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_BurstModeConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_BurstModeCtl() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_BurstModePeriodCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_BurstModeSoftwareTrigger() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Capture1EventCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Capture2EventCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_ChopperModeConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Compare1EventCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Compare2EventCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Compare3EventCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Compare4EventCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_CounterResetCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_DeadTimeConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_DeInit() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_DelayedProtectionCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_ErrorCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_EventConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_EventPrescalerConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Fault1Callback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Fault2Callback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Fault3Callback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Fault4Callback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Fault5Callback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_FaultConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_FaultModeCtl() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_FaultPrescalerConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_GetBurstStatus() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_GetCapturedValue() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_GetCurrentPushPullStatus() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_GetDelayedProtectionStatus() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_GetIdlePushPullStatus() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_GetState() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Init() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_IRQHandler() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_MspDeInit() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_MspInit() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Output1ResetCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Output1SetCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Output2ResetCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_Output2SetCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_RegistersUpdateCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_RepetitionEventCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleBaseStart() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleBaseStart_DMA() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleBaseStart_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleBaseStop() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleBaseStop_DMA() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleBaseStop_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleCaptureChannelConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleCaptureStart() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleCaptureStart_DMA() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleCaptureStart_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleCaptureStop() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleCaptureStop_DMA() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleCaptureStop_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOCChannelConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOCStart() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOCStart_DMA() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOCStart_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOCStop() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOCStop_DMA() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOCStop_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOnePulseChannelConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOnePulseStart() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOnePulseStart_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOnePulseStop() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimpleOnePulseStop_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimplePWMChannelConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimplePWMStart() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimplePWMStart_DMA() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimplePWMStart_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimplePWMStop() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimplePWMStop_DMA() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SimplePWMStop_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SoftwareCapture() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SoftwareReset() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SoftwareUpdate() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SynchronizationEventCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_SystemFaultCallback() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_TimeBaseConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_TimerEventFilteringConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_UpdateDisable() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_UpdateEnable() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformCaptureConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformCompareConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformCounterStart() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformCounterStart_DMA() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformCounterStart_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformCounterStop() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformCounterStop_DMA() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformCounterStop_IT() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformGetOutputLevel() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformGetOutputState() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformOutputConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformOutputStart() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformOutputStop() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformSetOutputLevel() : stm32h7xx_hal_hrtim.c
  • HAL_HRTIM_WaveformTimerConfig() : stm32h7xx_hal_hrtim.c
  • HAL_HSEM_ActivateNotification() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_DeactivateNotification() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_FastTake() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_FreeCallback() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_GetClearKey() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_IRQHandler() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_IsSemTaken() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_Release() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_ReleaseAll() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_SetClearKey() : stm32h7xx_hal_hsem.c
  • HAL_HSEM_Take() : stm32h7xx_hal_hsem.c
  • HAL_I2C_AbortCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_AddrCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_DeInit() : stm32h7xx_hal_i2c.c
  • HAL_I2C_DisableListen_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_EnableListen_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_ER_IRQHandler() : stm32h7xx_hal_i2c.c
  • HAL_I2C_ErrorCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_EV_IRQHandler() : stm32h7xx_hal_i2c.c
  • HAL_I2C_GetError() : stm32h7xx_hal_i2c.c
  • HAL_I2C_GetMode() : stm32h7xx_hal_i2c.c
  • HAL_I2C_GetState() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Init() : stm32h7xx_hal_i2c.c
  • HAL_I2C_IsDeviceReady() : stm32h7xx_hal_i2c.c
  • HAL_I2C_ListenCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Abort_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Receive() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Receive_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Receive_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Sequential_Receive_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Sequential_Transmit_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Transmit() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MasterRxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MasterTxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Read() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Read_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Read_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Write() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Write_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Mem_Write_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MemRxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MemTxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MspDeInit() : stm32h7xx_hal_i2c.c
  • HAL_I2C_MspInit() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Receive() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Sequential_Receive_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Sequential_Transmit_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_DMA() : stm32h7xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_IT() : stm32h7xx_hal_i2c.c
  • HAL_I2C_SlaveRxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2C_SlaveTxCpltCallback() : stm32h7xx_hal_i2c.c
  • HAL_I2CEx_ConfigAnalogFilter() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2CEx_ConfigDigitalFilter() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableFastModePlus() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableWakeUp() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableFastModePlus() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableWakeUp() : stm32h7xx_hal_i2c_ex.c
  • HAL_I2S_DeInit() : stm32h7xx_hal_i2s.c
  • HAL_I2S_DMAPause() : stm32h7xx_hal_i2s.c
  • HAL_I2S_DMAResume() : stm32h7xx_hal_i2s.c
  • HAL_I2S_DMAStop() : stm32h7xx_hal_i2s.c
  • HAL_I2S_ErrorCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2S_GetError() : stm32h7xx_hal_i2s.c
  • HAL_I2S_GetState() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Init() : stm32h7xx_hal_i2s.c
  • HAL_I2S_IRQHandler() : stm32h7xx_hal_i2s.c
  • HAL_I2S_MspDeInit() : stm32h7xx_hal_i2s.c
  • HAL_I2S_MspInit() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Receive() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Receive_DMA() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Receive_IT() : stm32h7xx_hal_i2s.c
  • HAL_I2S_RxCpltCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2S_RxHalfCpltCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Transmit() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Transmit_DMA() : stm32h7xx_hal_i2s.c
  • HAL_I2S_Transmit_IT() : stm32h7xx_hal_i2s.c
  • HAL_I2S_TxCpltCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2S_TxHalfCpltCallback() : stm32h7xx_hal_i2s.c
  • HAL_I2SEx_TransmitReceive() : stm32h7xx_hal_i2s_ex.c
  • HAL_I2SEx_TransmitReceive_DMA() : stm32h7xx_hal_i2s_ex.c
  • HAL_I2SEx_TransmitReceive_IT() : stm32h7xx_hal_i2s_ex.c
  • HAL_I2SEx_TxRxCpltCallback() : stm32h7xx_hal_i2s_ex.c
  • HAL_I2SEx_TxRxHalfCpltCallback() : stm32h7xx_hal_i2s_ex.c
  • HAL_IncTick() : stm32h7xx_hal.c
  • HAL_Init() : stm32h7xx_hal.c
  • HAL_InitTick() : stm32h7xx_hal.c
  • HAL_IRDA_Abort() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Abort_IT() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortReceive() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortReceive_IT() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortReceiveCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortTransmit() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortTransmit_IT() : stm32h7xx_hal_irda.c
  • HAL_IRDA_AbortTransmitCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_DeInit() : stm32h7xx_hal_irda.c
  • HAL_IRDA_DMAPause() : stm32h7xx_hal_irda.c
  • HAL_IRDA_DMAResume() : stm32h7xx_hal_irda.c
  • HAL_IRDA_DMAStop() : stm32h7xx_hal_irda.c
  • HAL_IRDA_ErrorCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_GetError() : stm32h7xx_hal_irda.c
  • HAL_IRDA_GetState() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Init() : stm32h7xx_hal_irda.c
  • HAL_IRDA_IRQHandler() : stm32h7xx_hal_irda.c
  • HAL_IRDA_MspDeInit() : stm32h7xx_hal_irda.c
  • HAL_IRDA_MspInit() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Receive() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Receive_DMA() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Receive_IT() : stm32h7xx_hal_irda.c
  • HAL_IRDA_RxCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_RxHalfCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Transmit() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Transmit_DMA() : stm32h7xx_hal_irda.c
  • HAL_IRDA_Transmit_IT() : stm32h7xx_hal_irda.c
  • HAL_IRDA_TxCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IRDA_TxHalfCpltCallback() : stm32h7xx_hal_irda.c
  • HAL_IWDG_Init() : stm32h7xx_hal_iwdg.c
  • HAL_IWDG_Refresh() : stm32h7xx_hal_iwdg.c
  • HAL_JPEG_Abort() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_ConfigEncoding() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_ConfigInputBuffer() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_ConfigOutputBuffer() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_DataReadyCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Decode() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Decode_DMA() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Decode_IT() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_DecodeCpltCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_DeInit() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_DisableHeaderParsing() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_EnableHeaderParsing() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Encode() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Encode_DMA() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Encode_IT() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_EncodeCpltCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_ErrorCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_GetDataCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_GetError() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_GetInfo() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_GetState() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_InfoReadyCallback() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Init() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_IRQHandler() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_MspDeInit() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_MspInit() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Pause() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_Resume() : stm32h7xx_hal_jpeg.c
  • HAL_JPEG_SetUserQuantTables() : stm32h7xx_hal_jpeg.c
  • HAL_LIN_Init() : stm32h7xx_hal_uart.c
  • HAL_LIN_SendBreak() : stm32h7xx_hal_uart.c
  • HAL_LPTIM_AutoReloadMatchCallback() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_AutoReloadWriteCallback() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_CompareMatchCallback() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_CompareWriteCallback() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_Counter_Start() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_Counter_Start_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_Counter_Stop() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_Counter_Stop_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_DeInit() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_DirectionDownCallback() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_DirectionUpCallback() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Start() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Start_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Stop() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Stop_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_GetState() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_Init() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_IRQHandler() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_MspDeInit() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_MspInit() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Stop() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Stop_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_PWM_Start() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_PWM_Start_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_PWM_Stop() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_PWM_Stop_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_ReadAutoReload() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_ReadCompare() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_ReadCounter() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Start() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Start_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Stop() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Stop_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Stop() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Stop_IT() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LPTIM_TriggerCallback() : stm32h7xx_hal_lptim.c , stm32h7xx_hal_lptim.h
  • HAL_LTDC_ConfigCLUT() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ConfigColorKeying() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ConfigColorKeying_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ConfigLayer() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ConfigLayer_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DeInit() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DisableCLUT() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DisableCLUT_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DisableColorKeying() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DisableColorKeying_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_DisableDither() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_EnableCLUT() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_EnableCLUT_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_EnableColorKeying() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_EnableColorKeying_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_EnableDither() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ErrorCallback() : stm32h7xx_hal_ltdc.c , stm32h7xx_hal_ltdc.h
  • HAL_LTDC_GetError() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_GetState() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_Init() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_IRQHandler() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_LineEventCallback() : stm32h7xx_hal_ltdc.c , stm32h7xx_hal_ltdc.h
  • HAL_LTDC_MspDeInit() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_MspInit() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ProgramLineEvent() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_Reload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_ReloadEventCallback() : stm32h7xx_hal_ltdc.c , stm32h7xx_hal_ltdc.h
  • HAL_LTDC_SetAddress() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetAddress_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetAlpha() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetAlpha_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetPitch() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetPitch_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetPixelFormat() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetPixelFormat_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetWindowPosition() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetWindowPosition_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetWindowSize() : stm32h7xx_hal_ltdc.c
  • HAL_LTDC_SetWindowSize_NoReload() : stm32h7xx_hal_ltdc.c
  • HAL_MDIOS_ClearReadRegAddress() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_ClearWriteRegAddress() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_DeInit() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_EnableEvents() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_ErrorCallback() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_GetError() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_GetReadRegAddress() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_GetState() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_GetWrittenRegAddress() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_Init() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_IRQHandler() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_MspDeInit() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_MspInit() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_ReadCpltCallback() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_ReadReg() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_WakeUpCallback() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_WriteCpltCallback() : stm32h7xx_hal_mdios.c
  • HAL_MDIOS_WriteReg() : stm32h7xx_hal_mdios.c
  • HAL_MDMA_Abort() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_Abort_IT() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_ConfigPostRequestMask() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_DeInit() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_GenerateSWRequest() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_GetError() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_GetState() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_Init() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_IRQHandler() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_LinkedList_AddNode() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_LinkedList_CreateNode() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_LinkedList_DisableCircularMode() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_LinkedList_EnableCircularMode() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_LinkedList_RemoveNode() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_PollForTransfer() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_RegisterCallback() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_Start() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_Start_IT() : stm32h7xx_hal_mdma.c
  • HAL_MDMA_UnRegisterCallback() : stm32h7xx_hal_mdma.c
  • HAL_MMC_Abort() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_Abort_IT() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_AbortCallback() : stm32h7xx_hal_mmc.c
  • HAL_MMC_ConfigWideBusOperation() : stm32h7xx_hal_mmc.c
  • HAL_MMC_DeInit() : stm32h7xx_hal_mmc.c
  • HAL_MMC_Erase() : stm32h7xx_hal_mmc.c
  • HAL_MMC_ErrorCallback() : stm32h7xx_hal_mmc.c
  • HAL_MMC_GetCardCID() : stm32h7xx_hal_mmc.h , stm32h7xx_hal_mmc.c
  • HAL_MMC_GetCardCSD() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_GetCardInfo() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_GetCardState() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_GetError() : stm32h7xx_hal_mmc.h , stm32h7xx_hal_mmc.c
  • HAL_MMC_GetState() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc.h
  • HAL_MMC_Init() : stm32h7xx_hal_mmc.c
  • HAL_MMC_InitCard() : stm32h7xx_hal_mmc.c
  • HAL_MMC_IRQHandler() : stm32h7xx_hal_mmc.c
  • HAL_MMC_MspDeInit() : stm32h7xx_hal_mmc.c
  • HAL_MMC_MspInit() : stm32h7xx_hal_mmc.c
  • HAL_MMC_ReadBlocks() : stm32h7xx_hal_mmc.c
  • HAL_MMC_ReadBlocks_DMA() : stm32h7xx_hal_mmc.c
  • HAL_MMC_ReadBlocks_IT() : stm32h7xx_hal_mmc.c
  • HAL_MMC_RxCpltCallback() : stm32h7xx_hal_mmc.c
  • HAL_MMC_TxCpltCallback() : stm32h7xx_hal_mmc.c
  • HAL_MMC_WriteBlocks() : stm32h7xx_hal_mmc.c
  • HAL_MMC_WriteBlocks_DMA() : stm32h7xx_hal_mmc.c
  • HAL_MMC_WriteBlocks_IT() : stm32h7xx_hal_mmc.c
  • HAL_MMCEx_ChangeDMABuffer() : stm32h7xx_hal_mmc_ex.c
  • HAL_MMCEx_ConfigDMAMultiBuffer() : stm32h7xx_hal_mmc_ex.c
  • HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc_ex.h
  • HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback() : stm32h7xx_hal_mmc_ex.h , stm32h7xx_hal_mmc.c
  • HAL_MMCEx_ReadBlocksDMAMultiBuffer() : stm32h7xx_hal_mmc_ex.c
  • HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc_ex.h
  • HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback() : stm32h7xx_hal_mmc.c , stm32h7xx_hal_mmc_ex.h
  • HAL_MMCEx_WriteBlocksDMAMultiBuffer() : stm32h7xx_hal_mmc_ex.c
  • HAL_MPU_ConfigRegion() : stm32h7xx_hal_cortex.c
  • HAL_MPU_Disable() : stm32h7xx_hal_cortex.h
  • HAL_MPU_Enable() : stm32h7xx_hal_cortex.h
  • HAL_MspDeInit() : stm32h7xx_hal.c
  • HAL_MspInit() : stm32h7xx_hal.c
  • HAL_MultiProcessor_DisableMuteMode() : stm32h7xx_hal_uart.c
  • HAL_MultiProcessor_EnableMuteMode() : stm32h7xx_hal_uart.c
  • HAL_MultiProcessor_EnterMuteMode() : stm32h7xx_hal_uart.c
  • HAL_MultiProcessor_Init() : stm32h7xx_hal_uart.c
  • HAL_MultiProcessorEx_AddressLength_Set() : stm32h7xx_hal_uart_ex.c
  • HAL_NAND_Address_Inc() : stm32h7xx_hal_nand.c
  • HAL_NAND_ConfigDevice() : stm32h7xx_hal_nand.c
  • HAL_NAND_DeInit() : stm32h7xx_hal_nand.c
  • HAL_NAND_ECC_Disable() : stm32h7xx_hal_nand.c
  • HAL_NAND_ECC_Enable() : stm32h7xx_hal_nand.c
  • HAL_NAND_Erase_Block() : stm32h7xx_hal_nand.c
  • HAL_NAND_GetECC() : stm32h7xx_hal_nand.c
  • HAL_NAND_GetState() : stm32h7xx_hal_nand.c
  • HAL_NAND_Init() : stm32h7xx_hal_nand.c
  • HAL_NAND_IRQHandler() : stm32h7xx_hal_nand.c
  • HAL_NAND_ITCallback() : stm32h7xx_hal_nand.c
  • HAL_NAND_MspDeInit() : stm32h7xx_hal_nand.c
  • HAL_NAND_MspInit() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_ID() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_Page_16b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_Page_8b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_SpareArea_16b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_SpareArea_8b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Read_Status() : stm32h7xx_hal_nand.c
  • HAL_NAND_Reset() : stm32h7xx_hal_nand.c
  • HAL_NAND_Write_Page_16b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Write_Page_8b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Write_SpareArea_16b() : stm32h7xx_hal_nand.c
  • HAL_NAND_Write_SpareArea_8b() : stm32h7xx_hal_nand.c
  • HAL_NOR_DeInit() : stm32h7xx_hal_nor.c
  • HAL_NOR_Erase_Block() : stm32h7xx_hal_nor.c
  • HAL_NOR_Erase_Chip() : stm32h7xx_hal_nor.c
  • HAL_NOR_GetState() : stm32h7xx_hal_nor.c
  • HAL_NOR_GetStatus() : stm32h7xx_hal_nor.c
  • HAL_NOR_Init() : stm32h7xx_hal_nor.c
  • HAL_NOR_MspDeInit() : stm32h7xx_hal_nor.c
  • HAL_NOR_MspInit() : stm32h7xx_hal_nor.c
  • HAL_NOR_MspWait() : stm32h7xx_hal_nor.c
  • HAL_NOR_Program() : stm32h7xx_hal_nor.c
  • HAL_NOR_ProgramBuffer() : stm32h7xx_hal_nor.c
  • HAL_NOR_Read() : stm32h7xx_hal_nor.c
  • HAL_NOR_Read_CFI() : stm32h7xx_hal_nor.c
  • HAL_NOR_Read_ID() : stm32h7xx_hal_nor.c
  • HAL_NOR_ReadBuffer() : stm32h7xx_hal_nor.c
  • HAL_NOR_ReturnToReadMode() : stm32h7xx_hal_nor.c
  • HAL_NOR_WriteOperation_Disable() : stm32h7xx_hal_nor.c
  • HAL_NOR_WriteOperation_Enable() : stm32h7xx_hal_nor.c
  • HAL_NVIC_ClearPendingIRQ() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_DisableIRQ() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_EnableIRQ() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_GetActive() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_GetPendingIRQ() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_GetPriority() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_GetPriorityGrouping() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_SetPendingIRQ() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_SetPriority() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_SetPriorityGrouping() : stm32h7xx_hal_cortex.c
  • HAL_NVIC_SystemReset() : stm32h7xx_hal_cortex.c
  • HAL_OPAMP_DeInit() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_GetState() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_GetTrimOffset() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_Init() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_Lock() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_MspDeInit() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_MspInit() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_SelfCalibrate() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_Start() : stm32h7xx_hal_opamp.c
  • HAL_OPAMP_Stop() : stm32h7xx_hal_opamp.c
  • HAL_OPAMPEx_SelfCalibrateAll() : stm32h7xx_hal_opamp_ex.c , stm32h7xx_hal_opamp_ex.h
  • HAL_OPAMPEx_Unlock() : stm32h7xx_hal_opamp_ex.c
  • HAL_PCD_ActivateRemoteWakeup() : stm32h7xx_hal_pcd.c
  • HAL_PCD_ConnectCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DataInStageCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DataOutStageCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DeActivateRemoteWakeup() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DeInit() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DevConnect() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DevDisconnect() : stm32h7xx_hal_pcd.c
  • HAL_PCD_DisconnectCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_Close() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_ClrStall() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_Flush() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_GetRxCount() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_Open() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_Receive() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_SetStall() : stm32h7xx_hal_pcd.c
  • HAL_PCD_EP_Transmit() : stm32h7xx_hal_pcd.c
  • HAL_PCD_GetState() : stm32h7xx_hal_pcd.c
  • HAL_PCD_Init() : stm32h7xx_hal_pcd.c
  • HAL_PCD_IRQHandler() : stm32h7xx_hal_pcd.c
  • HAL_PCD_ISOINIncompleteCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_ISOOUTIncompleteCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_MspDeInit() : stm32h7xx_hal_pcd.c
  • HAL_PCD_MspInit() : stm32h7xx_hal_pcd.c
  • HAL_PCD_ResetCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_ResumeCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_SetAddress() : stm32h7xx_hal_pcd.c
  • HAL_PCD_SetupStageCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_SOFCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCD_Start() : stm32h7xx_hal_pcd.c
  • HAL_PCD_Stop() : stm32h7xx_hal_pcd.c
  • HAL_PCD_SuspendCallback() : stm32h7xx_hal_pcd.c
  • HAL_PCDEx_ActivateBCD() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_ActivateLPM() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_Callback() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_VBUSDetect() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateBCD() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateLPM() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_LPM_Callback() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_SetRxFiFo() : stm32h7xx_hal_pcd_ex.c
  • HAL_PCDEx_SetTxFiFo() : stm32h7xx_hal_pcd_ex.c
  • HAL_PWR_ConfigPVD() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DeInit() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DisableBkUpAccess() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DisablePVD() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DisableSEVOnPend() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DisableSleepOnExit() : stm32h7xx_hal_pwr.c
  • HAL_PWR_DisableWakeUpPin() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnableBkUpAccess() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnablePVD() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnableSEVOnPend() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnableSleepOnExit() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnableWakeUpPin() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnterSLEEPMode() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnterSTANDBYMode() : stm32h7xx_hal_pwr.c
  • HAL_PWR_EnterSTOPMode() : stm32h7xx_hal_pwr.c
  • HAL_PWR_PVD_IRQHandler() : stm32h7xx_hal_pwr.c
  • HAL_PWR_PVDCallback() : stm32h7xx_hal_pwr.c
  • HAL_PWREx_AVDCallback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ClearWakeupFlag() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ConfigAVD() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ConfigD3Domain() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ConfigSupply() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ControlStopModeVoltageScaling() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_ControlVoltageScaling() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableAVD() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableBatteryCharging() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableBkUpReg() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableFlashPowerDown() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableMonitoring() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableUSBReg() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableUSBVoltageDetector() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableWakeUpPin() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableAVD() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableBatteryCharging() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableBkUpReg() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableFlashPowerDown() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableMonitoring() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableUSBReg() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableUSBVoltageDetector() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableWakeUpPin() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTANDBYMode() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOPMode() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetStopModeVoltageRange() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetSupplyConfig() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetTemperatureLevel() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetVBATLevel() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetVoltageRange() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_GetWakeupFlag() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_PVD_AVD_IRQHandler() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WAKEUP_PIN_IRQHandler() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP1_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP2_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP3_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP4_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP5_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_PWREx_WKUP6_Callback() : stm32h7xx_hal_pwr_ex.c
  • HAL_QSPI_Abort() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_Abort_IT() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_AbortCpltCallback() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_AutoPolling() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_AutoPolling_IT() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_CmdCpltCallback() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_Command() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_Command_IT() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_DeInit() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_ErrorCallback() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_FifoThresholdCallback() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_GetError() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_GetFifoThreshold() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_GetState() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_Init() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_IRQHandler() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_MemoryMapped() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_MspDeInit() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_MspInit() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_Receive() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_Receive_DMA() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_Receive_IT() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_RxCpltCallback() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_RxHalfCpltCallback() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_SetFifoThreshold() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_SetTimeout() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_StatusMatchCallback() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_TimeOutCallback() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_Transmit() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_Transmit_DMA() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_Transmit_IT() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_TxCpltCallback() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_QSPI_TxHalfCpltCallback() : stm32h7xx_hal_qspi.c , stm32h7xx_hal_qspi.h
  • HAL_RCC_CCSCallback() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_ClockConfig() : stm32h7xx_hal_rcc.c
  • HAL_RCC_DeInit() : stm32h7xx_hal_rcc.c
  • HAL_RCC_DisableCSS() : stm32h7xx_hal_rcc.h
  • HAL_RCC_EnableCSS() : stm32h7xx_hal_rcc.h , stm32h7xx_hal_rcc.c
  • HAL_RCC_GetClockConfig() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_GetHCLKFreq() : stm32h7xx_hal_rcc.h , stm32h7xx_hal_rcc.c
  • HAL_RCC_GetOscConfig() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_GetPCLK1Freq() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_GetPCLK2Freq() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_GetSysClockFreq() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_MCOConfig() : stm32h7xx_hal_rcc.h , stm32h7xx_hal_rcc.c
  • HAL_RCC_NMI_IRQHandler() : stm32h7xx_hal_rcc.c , stm32h7xx_hal_rcc.h
  • HAL_RCC_OscConfig() : stm32h7xx_hal_rcc.c
  • HAL_RCCEx_CRS_ErrorCallback() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_ExpectedSyncCallback() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_IRQHandler() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_SyncOkCallback() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_SyncWarnCallback() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSConfig() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSGetSynchronizationInfo() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSSoftwareSynchronizationGenerate() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSWaitSynchronization() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_DisableLSECSS() : stm32h7xx_hal_rcc_ex.c , stm32h7xx_hal_rcc_ex.h
  • HAL_RCCEx_EnableLSECSS() : stm32h7xx_hal_rcc_ex.h , stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetD1PCLK1Freq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetD1SysClockFreq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetD3PCLK1Freq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKConfig() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKFreq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPLL1ClockFreq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPLL2ClockFreq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPLL3ClockFreq() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_KerWakeUpStopCLKConfig() : stm32h7xx_hal_rcc_ex.c , stm32h7xx_hal_rcc_ex.h
  • HAL_RCCEx_PeriphCLKConfig() : stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_WakeUpStopCLKConfig() : stm32h7xx_hal_rcc_ex.h , stm32h7xx_hal_rcc_ex.c
  • HAL_RCCEx_WWDGxSysResetConfig() : stm32h7xx_hal_rcc_ex.c , stm32h7xx_hal_rcc_ex.h
  • HAL_ResumeTick() : stm32h7xx_hal.c
  • HAL_RNG_DeInit() : stm32h7xx_hal_rng.c
  • HAL_RNG_ErrorCallback() : stm32h7xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber() : stm32h7xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber_IT() : stm32h7xx_hal_rng.c
  • HAL_RNG_GetState() : stm32h7xx_hal_rng.c
  • HAL_RNG_Init() : stm32h7xx_hal_rng.c
  • HAL_RNG_IRQHandler() : stm32h7xx_hal_rng.c
  • HAL_RNG_MspDeInit() : stm32h7xx_hal_rng.c
  • HAL_RNG_MspInit() : stm32h7xx_hal_rng.c
  • HAL_RNG_ReadLastRandomNumber() : stm32h7xx_hal_rng.c
  • HAL_RNG_ReadyDataCallback() : stm32h7xx_hal_rng.c
  • HAL_RS485Ex_Init() : stm32h7xx_hal_uart_ex.c
  • HAL_RTC_AlarmAEventCallback() : stm32h7xx_hal_rtc.c
  • HAL_RTC_AlarmIRQHandler() : stm32h7xx_hal_rtc.c
  • HAL_RTC_DeactivateAlarm() : stm32h7xx_hal_rtc.c
  • HAL_RTC_DeInit() : stm32h7xx_hal_rtc.c
  • HAL_RTC_GetAlarm() : stm32h7xx_hal_rtc.c
  • HAL_RTC_GetDate() : stm32h7xx_hal_rtc.c
  • HAL_RTC_GetState() : stm32h7xx_hal_rtc.c
  • HAL_RTC_GetTime() : stm32h7xx_hal_rtc.c
  • HAL_RTC_Init() : stm32h7xx_hal_rtc.c
  • HAL_RTC_MspDeInit() : stm32h7xx_hal_rtc.c
  • HAL_RTC_MspInit() : stm32h7xx_hal_rtc.c
  • HAL_RTC_PollForAlarmAEvent() : stm32h7xx_hal_rtc.c
  • HAL_RTC_SetAlarm() : stm32h7xx_hal_rtc.c
  • HAL_RTC_SetAlarm_IT() : stm32h7xx_hal_rtc.c
  • HAL_RTC_SetDate() : stm32h7xx_hal_rtc.c
  • HAL_RTC_SetTime() : stm32h7xx_hal_rtc.c
  • HAL_RTC_WaitForSynchro() : stm32h7xx_hal_rtc.c
  • HAL_RTCEx_AlarmBEventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPRead() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPWrite() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateCalibrationOutPut() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateInternalTimeStamp() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateRefClock() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTamper() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTimeStamp() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateWakeUpTimer() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_DisableBypassShadow() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_EnableBypassShadow() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_GetTimeStamp() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_GetWakeUpTimer() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForAlarmBEvent() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper1Event() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper2Event() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper3Event() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTimeStampEvent() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForWakeUpTimerEvent() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetCalibrationOutPut() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTimeStamp() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetRefClock() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSmoothCalib() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSynchroShift() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper_IT() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp_IT() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer_IT() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper1EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper2EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper3EventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_TamperTimeStampIRQHandler() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_TimeStampEventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerEventCallback() : stm32h7xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerIRQHandler() : stm32h7xx_hal_rtc_ex.c
  • HAL_SAI_Abort() : stm32h7xx_hal_sai.c
  • HAL_SAI_DeInit() : stm32h7xx_hal_sai.c
  • HAL_SAI_DisableRxMuteMode() : stm32h7xx_hal_sai.c
  • HAL_SAI_DisableTxMuteMode() : stm32h7xx_hal_sai.c
  • HAL_SAI_DMAPause() : stm32h7xx_hal_sai.c
  • HAL_SAI_DMAResume() : stm32h7xx_hal_sai.c
  • HAL_SAI_DMAStop() : stm32h7xx_hal_sai.c
  • HAL_SAI_EnableRxMuteMode() : stm32h7xx_hal_sai.c
  • HAL_SAI_EnableTxMuteMode() : stm32h7xx_hal_sai.c
  • HAL_SAI_ErrorCallback() : stm32h7xx_hal_sai.c
  • HAL_SAI_GetError() : stm32h7xx_hal_sai.c
  • HAL_SAI_GetState() : stm32h7xx_hal_sai.c
  • HAL_SAI_Init() : stm32h7xx_hal_sai.c
  • HAL_SAI_InitProtocol() : stm32h7xx_hal_sai.c
  • HAL_SAI_IRQHandler() : stm32h7xx_hal_sai.c
  • HAL_SAI_MspDeInit() : stm32h7xx_hal_sai.c
  • HAL_SAI_MspInit() : stm32h7xx_hal_sai.c
  • HAL_SAI_Receive() : stm32h7xx_hal_sai.c
  • HAL_SAI_Receive_DMA() : stm32h7xx_hal_sai.c
  • HAL_SAI_Receive_IT() : stm32h7xx_hal_sai.c
  • HAL_SAI_RxCpltCallback() : stm32h7xx_hal_sai.c
  • HAL_SAI_RxHalfCpltCallback() : stm32h7xx_hal_sai.c
  • HAL_SAI_Transmit() : stm32h7xx_hal_sai.c
  • HAL_SAI_Transmit_DMA() : stm32h7xx_hal_sai.c
  • HAL_SAI_Transmit_IT() : stm32h7xx_hal_sai.c
  • HAL_SAI_TxCpltCallback() : stm32h7xx_hal_sai.c
  • HAL_SAI_TxHalfCpltCallback() : stm32h7xx_hal_sai.c
  • HAL_SAIEx_ConfigPdmMicDelay() : stm32h7xx_hal_sai_ex.c
  • HAL_SD_Abort() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd.h
  • HAL_SD_Abort_IT() : stm32h7xx_hal_sd.h , stm32h7xx_hal_sd.c
  • HAL_SD_AbortCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_ConfigWideBusOperation() : stm32h7xx_hal_sd.c
  • HAL_SD_DeInit() : stm32h7xx_hal_sd.c
  • HAL_SD_DriveTransciver_1_8V_Callback() : stm32h7xx_hal_sd.c
  • HAL_SD_Erase() : stm32h7xx_hal_sd.c
  • HAL_SD_ErrorCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_GetCardCID() : stm32h7xx_hal_sd.h , stm32h7xx_hal_sd.c
  • HAL_SD_GetCardCSD() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd.h
  • HAL_SD_GetCardInfo() : stm32h7xx_hal_sd.h , stm32h7xx_hal_sd.c
  • HAL_SD_GetCardState() : stm32h7xx_hal_sd.h , stm32h7xx_hal_sd.c
  • HAL_SD_GetCardStatus() : stm32h7xx_hal_sd.h , stm32h7xx_hal_sd.c
  • HAL_SD_GetError() : stm32h7xx_hal_sd.h , stm32h7xx_hal_sd.c
  • HAL_SD_GetState() : stm32h7xx_hal_sd.h , stm32h7xx_hal_sd.c
  • HAL_SD_Init() : stm32h7xx_hal_sd.c
  • HAL_SD_InitCard() : stm32h7xx_hal_sd.c
  • HAL_SD_IRQHandler() : stm32h7xx_hal_sd.c
  • HAL_SD_MspDeInit() : stm32h7xx_hal_sd.c
  • HAL_SD_MspInit() : stm32h7xx_hal_sd.c
  • HAL_SD_ReadBlocks() : stm32h7xx_hal_sd.c
  • HAL_SD_ReadBlocks_DMA() : stm32h7xx_hal_sd.c
  • HAL_SD_ReadBlocks_IT() : stm32h7xx_hal_sd.c
  • HAL_SD_RxCpltCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_SendSDStatus() : stm32h7xx_hal_sd.h
  • HAL_SD_TxCpltCallback() : stm32h7xx_hal_sd.c
  • HAL_SD_WriteBlocks() : stm32h7xx_hal_sd.c
  • HAL_SD_WriteBlocks_DMA() : stm32h7xx_hal_sd.c
  • HAL_SD_WriteBlocks_IT() : stm32h7xx_hal_sd.c
  • HAL_SDEx_ChangeDMABuffer() : stm32h7xx_hal_sd_ex.c
  • HAL_SDEx_ConfigDMAMultiBuffer() : stm32h7xx_hal_sd_ex.c
  • HAL_SDEx_Read_DMADoubleBuffer0CpltCallback() : stm32h7xx_hal_sd_ex.h , stm32h7xx_hal_sd.c
  • HAL_SDEx_Read_DMADoubleBuffer1CpltCallback() : stm32h7xx_hal_sd_ex.h , stm32h7xx_hal_sd.c
  • HAL_SDEx_ReadBlocksDMAMultiBuffer() : stm32h7xx_hal_sd_ex.c
  • HAL_SDEx_Write_DMADoubleBuffer0CpltCallback() : stm32h7xx_hal_sd.c , stm32h7xx_hal_sd_ex.h
  • HAL_SDEx_Write_DMADoubleBuffer1CpltCallback() : stm32h7xx_hal_sd_ex.h , stm32h7xx_hal_sd.c
  • HAL_SDEx_WriteBlocksDMAMultiBuffer() : stm32h7xx_hal_sd_ex.c
  • HAL_SDRAM_DeInit() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_DMA_XferCpltCallback() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_DMA_XferErrorCallback() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_GetModeStatus() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_GetState() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Init() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_IRQHandler() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_MspDeInit() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_MspInit() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_ProgramRefreshRate() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Read_16b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Read_32b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Read_8b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Read_DMA() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_RefreshErrorCallback() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_SendCommand() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_SetAutoRefreshNumber() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Write_16b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Write_32b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Write_8b() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_Write_DMA() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_WriteProtection_Disable() : stm32h7xx_hal_sdram.c
  • HAL_SDRAM_WriteProtection_Enable() : stm32h7xx_hal_sdram.c
  • HAL_SetFMCMemorySwappingConfig() : stm32h7xx_hal.c
  • HAL_SMARTCARD_Abort() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Abort_IT() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortCpltCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive_IT() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceiveCpltCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit_IT() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmitCpltCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_DeInit() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_ErrorCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_GetError() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_GetState() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Init() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_IRQHandler() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_MspDeInit() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_MspInit() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_DMA() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_IT() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_RxCpltCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_DMA() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_IT() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARD_TxCpltCallback() : stm32h7xx_hal_smartcard.c
  • HAL_SMARTCARDEx_BlockLength_Config() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableReceiverTimeOut() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableReceiverTimeOut() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TimeOut_Config() : stm32h7xx_hal_smartcard_ex.c
  • HAL_SMBUS_AddrCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_DeInit() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_DisableAlert_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_DisableListen_IT() : stm32h7xx_hal_smbus.h , stm32h7xx_hal_smbus.c
  • HAL_SMBUS_EnableAlert_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_EnableListen_IT() : stm32h7xx_hal_smbus.h , stm32h7xx_hal_smbus.c
  • HAL_SMBUS_ER_IRQHandler() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_ErrorCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_EV_IRQHandler() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_GetError() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_GetState() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_Init() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_IsDeviceReady() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ListenCpltCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_Master_Abort_IT() : stm32h7xx_hal_smbus.h , stm32h7xx_hal_smbus.c
  • HAL_SMBUS_Master_Receive_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_Master_Transmit_IT() : stm32h7xx_hal_smbus.h , stm32h7xx_hal_smbus.c
  • HAL_SMBUS_MasterRxCpltCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_MasterTxCpltCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_MspDeInit() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_MspInit() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_Slave_Receive_IT() : stm32h7xx_hal_smbus.h , stm32h7xx_hal_smbus.c
  • HAL_SMBUS_Slave_Transmit_IT() : stm32h7xx_hal_smbus.c , stm32h7xx_hal_smbus.h
  • HAL_SMBUS_SlaveRxCpltCallback() : stm32h7xx_hal_smbus.c
  • HAL_SMBUS_SlaveTxCpltCallback() : stm32h7xx_hal_smbus.c
  • HAL_SPDIFRX_CxCpltCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_CxHalfCpltCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_DeInit() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_DMAStop() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ErrorCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_GetError() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_GetState() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_Init() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_IRQHandler() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_MspDeInit() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_MspInit() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveControlFlow() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveControlFlow_DMA() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveControlFlow_IT() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveDataFlow() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveDataFlow_DMA() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveDataFlow_IT() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_RxCpltCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_RxHalfCpltCallback() : stm32h7xx_hal_spdifrx.c
  • HAL_SPDIFRX_SetDataFormat() : stm32h7xx_hal_spdifrx.c
  • HAL_SPI_Abort() : stm32h7xx_hal_spi.c
  • HAL_SPI_Abort_IT() : stm32h7xx_hal_spi.c
  • HAL_SPI_AbortCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_DeInit() : stm32h7xx_hal_spi.c
  • HAL_SPI_DMAPause() : stm32h7xx_hal_spi.c
  • HAL_SPI_DMAResume() : stm32h7xx_hal_spi.c
  • HAL_SPI_DMAStop() : stm32h7xx_hal_spi.c
  • HAL_SPI_ErrorCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_GetError() : stm32h7xx_hal_spi.c
  • HAL_SPI_GetState() : stm32h7xx_hal_spi.c
  • HAL_SPI_Init() : stm32h7xx_hal_spi.c
  • HAL_SPI_IRQHandler() : stm32h7xx_hal_spi.c
  • HAL_SPI_MspDeInit() : stm32h7xx_hal_spi.c
  • HAL_SPI_MspInit() : stm32h7xx_hal_spi.c
  • HAL_SPI_Receive() : stm32h7xx_hal_spi.c
  • HAL_SPI_Receive_DMA() : stm32h7xx_hal_spi.c
  • HAL_SPI_Receive_IT() : stm32h7xx_hal_spi.c
  • HAL_SPI_RxCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_RxHalfCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_Transmit() : stm32h7xx_hal_spi.c
  • HAL_SPI_Transmit_DMA() : stm32h7xx_hal_spi.c
  • HAL_SPI_Transmit_IT() : stm32h7xx_hal_spi.c
  • HAL_SPI_TransmitReceive() : stm32h7xx_hal_spi.c
  • HAL_SPI_TransmitReceive_DMA() : stm32h7xx_hal_spi.c
  • HAL_SPI_TransmitReceive_IT() : stm32h7xx_hal_spi.c
  • HAL_SPI_TxCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_TxHalfCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_TxRxCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPI_TxRxHalfCpltCallback() : stm32h7xx_hal_spi.c
  • HAL_SPIEx_ConfigureUnderrun() : stm32h7xx_hal_spi_ex.c
  • HAL_SPIEx_DisableLockConfiguration() : stm32h7xx_hal_spi_ex.c
  • HAL_SPIEx_EnableLockConfiguration() : stm32h7xx_hal_spi_ex.c
  • HAL_SPIEx_FlushRxFifo() : stm32h7xx_hal_spi_ex.c
  • HAL_SRAM_DeInit() : stm32h7xx_hal_sram.c
  • HAL_SRAM_DMA_XferCpltCallback() : stm32h7xx_hal_sram.h , stm32h7xx_hal_sram.c
  • HAL_SRAM_DMA_XferErrorCallback() : stm32h7xx_hal_sram.c , stm32h7xx_hal_sram.h
  • HAL_SRAM_GetState() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Init() : stm32h7xx_hal_sram.c
  • HAL_SRAM_MspDeInit() : stm32h7xx_hal_sram.c
  • HAL_SRAM_MspInit() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Read_16b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Read_32b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Read_8b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Read_DMA() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Write_16b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Write_32b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Write_8b() : stm32h7xx_hal_sram.c
  • HAL_SRAM_Write_DMA() : stm32h7xx_hal_sram.c
  • HAL_SRAM_WriteOperation_Disable() : stm32h7xx_hal_sram.c
  • HAL_SRAM_WriteOperation_Enable() : stm32h7xx_hal_sram.c
  • HAL_SuspendTick() : stm32h7xx_hal.c
  • HAL_SWPMI_DeInit() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_DisableLoopback() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_DMAStop() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_EnableLoopback() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ErrorCallback() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_GetError() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_GetState() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_Init() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_IRQHandler() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_MspDeInit() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_MspInit() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_Receive() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_Receive_DMA() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_Receive_IT() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_RxCpltCallback() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_RxHalfCpltCallback() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_Transmit() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_Transmit_DMA() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_Transmit_IT() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_TxCpltCallback() : stm32h7xx_hal_swpmi.h , stm32h7xx_hal_swpmi.c
  • HAL_SWPMI_TxHalfCpltCallback() : stm32h7xx_hal_swpmi.c , stm32h7xx_hal_swpmi.h
  • HAL_SYSCFG_AnalogSwitchConfig() : stm32h7xx_hal.c
  • HAL_SYSCFG_CM7BootAddConfig() : stm32h7xx_hal.c
  • HAL_SYSCFG_CompensationCodeConfig() : stm32h7xx_hal.c
  • HAL_SYSCFG_CompensationCodeSelect() : stm32h7xx_hal.c
  • HAL_SYSCFG_DisableBOOST() : stm32h7xx_hal.c
  • HAL_SYSCFG_DisableIOSpeedOptimize() : stm32h7xx_hal.c
  • HAL_SYSCFG_DisableVREFBUF() : stm32h7xx_hal.c
  • HAL_SYSCFG_EnableBOOST() : stm32h7xx_hal.c
  • HAL_SYSCFG_EnableIOSpeedOptimize() : stm32h7xx_hal.c
  • HAL_SYSCFG_EnableVREFBUF() : stm32h7xx_hal.c
  • HAL_SYSCFG_ETHInterfaceSelect() : stm32h7xx_hal.c
  • HAL_SYSCFG_VREFBUF_HighImpedanceConfig() : stm32h7xx_hal.c
  • HAL_SYSCFG_VREFBUF_TrimmingConfig() : stm32h7xx_hal.c
  • HAL_SYSCFG_VREFBUF_VoltageScalingConfig() : stm32h7xx_hal.c
  • HAL_SYSTICK_Callback() : stm32h7xx_hal_cortex.c
  • HAL_SYSTICK_CLKSourceConfig() : stm32h7xx_hal_cortex.c
  • HAL_SYSTICK_Config() : stm32h7xx_hal_cortex.c
  • HAL_SYSTICK_IRQHandler() : stm32h7xx_hal_cortex.c
  • HAL_TIM_Base_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Start_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Stop_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_Base_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_ConfigClockSource() : stm32h7xx_hal_tim.c
  • HAL_TIM_ConfigOCrefClear() : stm32h7xx_hal_tim.c
  • HAL_TIM_ConfigTI1Input() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStart() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStop() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStart() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStop() : stm32h7xx_hal_tim.c
  • HAL_TIM_DMACaptureCplt() : stm32h7xx_hal_tim.c , stm32h7xx_hal_tim.h
  • HAL_TIM_DMADelayPulseCplt() : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim.c
  • HAL_TIM_DMAError() : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Start_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_ErrorCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_GenerateEvent() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_CaptureCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_ConfigChannel() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Start_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Stop_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_IC_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_IRQHandler() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_ConfigChannel() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_DelayElapsedCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Start_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Stop_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_OC_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_ConfigChannel() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_PeriodElapsedCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_ConfigChannel() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_DeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_GetState() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Init() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_MspDeInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_MspInit() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedCallback() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Start() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Start_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Start_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Stop() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Stop_DMA() : stm32h7xx_hal_tim.c
  • HAL_TIM_PWM_Stop_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_ReadCapturedValue() : stm32h7xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization() : stm32h7xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization_IT() : stm32h7xx_hal_tim.c
  • HAL_TIM_TriggerCallback() : stm32h7xx_hal_tim.c
  • HAL_TIMEx_BreakCallback() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_CommutationCallback() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakDeadTime() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakInput() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_DMACommutationCplt() : stm32h7xx_hal_tim_ex.c , stm32h7xx_hal_tim_ex.h
  • HAL_TIMEx_GroupChannel5() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_DeInit() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_GetState() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Init() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspDeInit() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspInit() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_MasterConfigSynchronization() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_DMA() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_IT() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_RemapConfig() : stm32h7xx_hal_tim_ex.c
  • HAL_TIMEx_TISelection() : stm32h7xx_hal_tim_ex.c
  • HAL_UART_Abort() : stm32h7xx_hal_uart.c
  • HAL_UART_Abort_IT() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortReceive() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortReceive_IT() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortReceiveCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortTransmit() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortTransmit_IT() : stm32h7xx_hal_uart.c
  • HAL_UART_AbortTransmitCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_DeInit() : stm32h7xx_hal_uart.c
  • HAL_UART_DMAPause() : stm32h7xx_hal_uart.c
  • HAL_UART_DMAResume() : stm32h7xx_hal_uart.c
  • HAL_UART_DMAStop() : stm32h7xx_hal_uart.c
  • HAL_UART_ErrorCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_GetError() : stm32h7xx_hal_uart.c
  • HAL_UART_GetState() : stm32h7xx_hal_uart.c
  • HAL_UART_Init() : stm32h7xx_hal_uart.c
  • HAL_UART_IRQHandler() : stm32h7xx_hal_uart.c
  • HAL_UART_MspDeInit() : stm32h7xx_hal_uart.c
  • HAL_UART_MspInit() : stm32h7xx_hal_uart.c
  • HAL_UART_Receive() : stm32h7xx_hal_uart.c
  • HAL_UART_Receive_DMA() : stm32h7xx_hal_uart.c
  • HAL_UART_Receive_IT() : stm32h7xx_hal_uart.c
  • HAL_UART_RxCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_RxHalfCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_Transmit() : stm32h7xx_hal_uart.c
  • HAL_UART_Transmit_DMA() : stm32h7xx_hal_uart.c
  • HAL_UART_Transmit_IT() : stm32h7xx_hal_uart.c
  • HAL_UART_TxCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UART_TxHalfCpltCallback() : stm32h7xx_hal_uart.c
  • HAL_UARTEx_DisableStopMode() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_EnableStopMode() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_StopModeWakeUpSourceConfig() : stm32h7xx_hal_uart_ex.c
  • HAL_UARTEx_WakeupCallback() : stm32h7xx_hal_uart_ex.c
  • HAL_USART_Abort() : stm32h7xx_hal_usart.c
  • HAL_USART_Abort_IT() : stm32h7xx_hal_usart.c
  • HAL_USART_AbortCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_DeInit() : stm32h7xx_hal_usart.c
  • HAL_USART_DMAPause() : stm32h7xx_hal_usart.c
  • HAL_USART_DMAResume() : stm32h7xx_hal_usart.c
  • HAL_USART_DMAStop() : stm32h7xx_hal_usart.c
  • HAL_USART_ErrorCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_GetError() : stm32h7xx_hal_usart.c
  • HAL_USART_GetState() : stm32h7xx_hal_usart.c
  • HAL_USART_Init() : stm32h7xx_hal_usart.c
  • HAL_USART_IRQHandler() : stm32h7xx_hal_usart.c
  • HAL_USART_MspDeInit() : stm32h7xx_hal_usart.c
  • HAL_USART_MspInit() : stm32h7xx_hal_usart.c
  • HAL_USART_Receive() : stm32h7xx_hal_usart.c
  • HAL_USART_Receive_DMA() : stm32h7xx_hal_usart.c
  • HAL_USART_Receive_IT() : stm32h7xx_hal_usart.c
  • HAL_USART_RxCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_RxHalfCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_Transmit() : stm32h7xx_hal_usart.c
  • HAL_USART_Transmit_DMA() : stm32h7xx_hal_usart.c
  • HAL_USART_Transmit_IT() : stm32h7xx_hal_usart.c
  • HAL_USART_TransmitReceive() : stm32h7xx_hal_usart.c
  • HAL_USART_TransmitReceive_DMA() : stm32h7xx_hal_usart.c
  • HAL_USART_TransmitReceive_IT() : stm32h7xx_hal_usart.c
  • HAL_USART_TxCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_TxHalfCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_USART_TxRxCpltCallback() : stm32h7xx_hal_usart.c
  • HAL_WWDG_EarlyWakeupCallback() : stm32h7xx_hal_wwdg.c
  • HAL_WWDG_Init() : stm32h7xx_hal_wwdg.c
  • HAL_WWDG_IRQHandler() : stm32h7xx_hal_wwdg.c
  • HAL_WWDG_MspInit() : stm32h7xx_hal_wwdg.c
  • HAL_WWDG_Refresh() : stm32h7xx_hal_wwdg.c
  • HASH_Accumulate() : stm32h7xx_hal_hash.c
  • HASH_DMAError() : stm32h7xx_hal_hash.c
  • HASH_DMAXferCplt() : stm32h7xx_hal_hash.c
  • HASH_Finish() : stm32h7xx_hal_hash.c
  • HASH_GetDigest() : stm32h7xx_hal_hash.c
  • HASH_IT() : stm32h7xx_hal_hash.c
  • HASH_Start() : stm32h7xx_hal_hash.c
  • HASH_Start_DMA() : stm32h7xx_hal_hash.c
  • HASH_Start_IT() : stm32h7xx_hal_hash.c
  • HASH_WaitOnFlagUntilTimeout() : stm32h7xx_hal_hash.c
  • HASH_Write_Block_Data() : stm32h7xx_hal_hash.c
  • HASH_WriteData() : stm32h7xx_hal_hash.c
  • HCD_HC_IN_IRQHandler() : stm32h7xx_hal_hcd.c
  • HCD_HC_OUT_IRQHandler() : stm32h7xx_hal_hcd.c
  • HCD_Port_IRQHandler() : stm32h7xx_hal_hcd.c
  • HCD_RXQLVL_IRQHandler() : stm32h7xx_hal_hcd.c
  • HMAC_Processing() : stm32h7xx_hal_hash.c
  • HMAC_Start() : stm32h7xx_hal_hash.c
  • HMAC_Start_DMA() : stm32h7xx_hal_hash.c
  • HMAC_Start_IT() : stm32h7xx_hal_hash.c
  • HRTIM_BurstDMACplt() : stm32h7xx_hal_hrtim.c
  • HRTIM_CaptureUnitConfig() : stm32h7xx_hal_hrtim.c
  • HRTIM_CompareUnitConfig() : stm32h7xx_hal_hrtim.c
  • HRTIM_DMAError() : stm32h7xx_hal_hrtim.c
  • HRTIM_DMAMasterCplt() : stm32h7xx_hal_hrtim.c
  • HRTIM_DMATimerxCplt() : stm32h7xx_hal_hrtim.c
  • HRTIM_EventConfig() : stm32h7xx_hal_hrtim.c
  • HRTIM_ForceRegistersUpdate() : stm32h7xx_hal_hrtim.c
  • HRTIM_GetDMAFromOCMode() : stm32h7xx_hal_hrtim.c
  • HRTIM_GetDMAHandleFromTimerIdx() : stm32h7xx_hal_hrtim.c
  • HRTIM_GetITFromOCMode() : stm32h7xx_hal_hrtim.c
  • HRTIM_HRTIM_ISR() : stm32h7xx_hal_hrtim.c
  • HRTIM_Master_ISR() : stm32h7xx_hal_hrtim.c
  • HRTIM_MasterBase_Config() : stm32h7xx_hal_hrtim.c
  • HRTIM_MasterWaveform_Config() : stm32h7xx_hal_hrtim.c
  • HRTIM_OutputConfig() : stm32h7xx_hal_hrtim.c
  • HRTIM_TIM_ResetConfig() : stm32h7xx_hal_hrtim.c
  • HRTIM_Timer_ISR() : stm32h7xx_hal_hrtim.c
  • HRTIM_TimingUnitBase_Config() : stm32h7xx_hal_hrtim.c
  • HRTIM_TimingUnitWaveform_Config() : stm32h7xx_hal_hrtim.c
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STM32H753xx HAL User Manual: Globals

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- i -

  • I2C_Disable_IRQ() : stm32h7xx_hal_i2c.c
  • I2C_DMAAbort() : stm32h7xx_hal_i2c.c
  • I2C_DMAError() : stm32h7xx_hal_i2c.c
  • I2C_DMAMasterReceiveCplt() : stm32h7xx_hal_i2c.c
  • I2C_DMAMasterTransmitCplt() : stm32h7xx_hal_i2c.c
  • I2C_DMASlaveReceiveCplt() : stm32h7xx_hal_i2c.c
  • I2C_DMASlaveTransmitCplt() : stm32h7xx_hal_i2c.c
  • I2C_Enable_IRQ() : stm32h7xx_hal_i2c.c
  • I2C_Flush_TXDR() : stm32h7xx_hal_i2c.c
  • I2C_IsAcknowledgeFailed() : stm32h7xx_hal_i2c.c
  • I2C_ITAddrCplt() : stm32h7xx_hal_i2c.c
  • I2C_ITError() : stm32h7xx_hal_i2c.c
  • I2C_ITListenCplt() : stm32h7xx_hal_i2c.c
  • I2C_ITMasterCplt() : stm32h7xx_hal_i2c.c
  • I2C_ITMasterSequentialCplt() : stm32h7xx_hal_i2c.c
  • I2C_ITSlaveCplt() : stm32h7xx_hal_i2c.c
  • I2C_ITSlaveSequentialCplt() : stm32h7xx_hal_i2c.c
  • I2C_Master_ISR_DMA() : stm32h7xx_hal_i2c.c
  • I2C_Master_ISR_IT() : stm32h7xx_hal_i2c.c
  • I2C_RequestMemoryRead() : stm32h7xx_hal_i2c.c
  • I2C_RequestMemoryWrite() : stm32h7xx_hal_i2c.c
  • I2C_Slave_ISR_DMA() : stm32h7xx_hal_i2c.c
  • I2C_Slave_ISR_IT() : stm32h7xx_hal_i2c.c
  • I2C_TransferConfig() : stm32h7xx_hal_i2c.c
  • I2C_WaitOnFlagUntilTimeout() : stm32h7xx_hal_i2c.c
  • I2C_WaitOnRXNEFlagUntilTimeout() : stm32h7xx_hal_i2c.c
  • I2C_WaitOnSTOPFlagUntilTimeout() : stm32h7xx_hal_i2c.c
  • I2C_WaitOnTXISFlagUntilTimeout() : stm32h7xx_hal_i2c.c
  • I2S_CloseRx_ISR() : stm32h7xx_hal_i2s.c
  • I2S_CloseTx_ISR() : stm32h7xx_hal_i2s.c
  • I2S_DMAError() : stm32h7xx_hal_i2s.c
  • I2S_DMARxCplt() : stm32h7xx_hal_i2s.c
  • I2S_DMARxHalfCplt() : stm32h7xx_hal_i2s.c
  • I2S_DMATxCplt() : stm32h7xx_hal_i2s.c
  • I2S_DMATxHalfCplt() : stm32h7xx_hal_i2s.c
  • I2S_RxISR_16BIT() : stm32h7xx_hal_i2s.c
  • I2S_RxISR_32BIT() : stm32h7xx_hal_i2s.c
  • I2S_TxISR_16BIT() : stm32h7xx_hal_i2s.c
  • I2S_TxISR_32BIT() : stm32h7xx_hal_i2s.c
  • I2S_WaitFlagStateUntilTimeout() : stm32h7xx_hal_i2s.c
  • I2SEx_2linesRxISR_16BIT() : stm32h7xx_hal_i2s_ex.c
  • I2SEx_2linesRxISR_32BIT() : stm32h7xx_hal_i2s_ex.c
  • I2SEx_2linesTxISR_16BIT() : stm32h7xx_hal_i2s_ex.c
  • I2SEx_2linesTxISR_32BIT() : stm32h7xx_hal_i2s_ex.c
  • I2SEx_CloseRxTx_ISR() : stm32h7xx_hal_i2s_ex.c
  • I2SEx_DMATxRxCplt() : stm32h7xx_hal_i2s_ex.c
  • I2SEx_DMATxRxHalfCplt() : stm32h7xx_hal_i2s_ex.c
  • I2SEx_TxRxDMAError() : stm32h7xx_hal_i2s_ex.c
  • I2SEx_WaitFlagStateUntilTimeout() : stm32h7xx_hal_i2s_ex.c
  • IRDA_CheckIdleState() : stm32h7xx_hal_irda.c
  • IRDA_DMAAbortOnError() : stm32h7xx_hal_irda.c
  • IRDA_DMAError() : stm32h7xx_hal_irda.c
  • IRDA_DMAReceiveCplt() : stm32h7xx_hal_irda.c
  • IRDA_DMAReceiveHalfCplt() : stm32h7xx_hal_irda.c
  • IRDA_DMARxAbortCallback() : stm32h7xx_hal_irda.c
  • IRDA_DMARxOnlyAbortCallback() : stm32h7xx_hal_irda.c
  • IRDA_DMATransmitCplt() : stm32h7xx_hal_irda.c
  • IRDA_DMATransmitHalfCplt() : stm32h7xx_hal_irda.c
  • IRDA_DMATxAbortCallback() : stm32h7xx_hal_irda.c
  • IRDA_DMATxOnlyAbortCallback() : stm32h7xx_hal_irda.c
  • IRDA_EndRxTransfer() : stm32h7xx_hal_irda.c
  • IRDA_EndTransmit_IT() : stm32h7xx_hal_irda.c
  • IRDA_EndTxTransfer() : stm32h7xx_hal_irda.c
  • IRDA_Receive_IT() : stm32h7xx_hal_irda.c
  • IRDA_SetConfig() : stm32h7xx_hal_irda.c
  • IRDA_Transmit_IT() : stm32h7xx_hal_irda.c
  • IRDA_WaitOnFlagUntilTimeout() : stm32h7xx_hal_irda.c
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STM32H753xx HAL User Manual: Globals

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- j -

  • JPEG_ACHuff_BitsVals_To_SizeCodes() : stm32h7xx_hal_jpeg.c
  • JPEG_Bits_To_SizeCodes() : stm32h7xx_hal_jpeg.c
  • JPEG_DCHuff_BitsVals_To_SizeCodes() : stm32h7xx_hal_jpeg.c
  • JPEG_DMA_ContinueProcess() : stm32h7xx_hal_jpeg.c
  • JPEG_DMA_EndProcess() : stm32h7xx_hal_jpeg.c
  • JPEG_DMA_PollResidualData() : stm32h7xx_hal_jpeg.c
  • JPEG_DMA_StartProcess() : stm32h7xx_hal_jpeg.c
  • JPEG_GetQuality() : stm32h7xx_hal_jpeg.c
  • JPEG_Init_Process() : stm32h7xx_hal_jpeg.c
  • JPEG_MDMAErrorCallback() : stm32h7xx_hal_jpeg.c
  • JPEG_MDMAInCpltCallback() : stm32h7xx_hal_jpeg.c
  • JPEG_MDMAOutAbortCallback() : stm32h7xx_hal_jpeg.c
  • JPEG_MDMAOutCpltCallback() : stm32h7xx_hal_jpeg.c
  • JPEG_Process() : stm32h7xx_hal_jpeg.c
  • JPEG_ReadInputData() : stm32h7xx_hal_jpeg.c
  • JPEG_Set_Huff_DHTMem() : stm32h7xx_hal_jpeg.c
  • JPEG_Set_HuffAC_Mem() : stm32h7xx_hal_jpeg.c
  • JPEG_Set_HuffDC_Mem() : stm32h7xx_hal_jpeg.c
  • JPEG_Set_HuffEnc_Mem() : stm32h7xx_hal_jpeg.c
  • JPEG_Set_Quantization_Mem() : stm32h7xx_hal_jpeg.c
  • JPEG_SetColorCMYK() : stm32h7xx_hal_jpeg.c
  • JPEG_SetColorGrayScale() : stm32h7xx_hal_jpeg.c
  • JPEG_SetColorYCBCR() : stm32h7xx_hal_jpeg.c
  • JPEG_StoreOutputData() : stm32h7xx_hal_jpeg.c
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STM32H753xx HAL User Manual: Globals

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- l -

  • LTDC_SetConfig() : stm32h7xx_hal_ltdc.c
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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- m -

  • MDMA_Init() : stm32h7xx_hal_mdma.c
  • MDMA_SetConfig() : stm32h7xx_hal_mdma.c
  • MMC_InitCard() : stm32h7xx_hal_mmc.c
  • MMC_PowerOFF() : stm32h7xx_hal_mmc.c
  • MMC_PowerON() : stm32h7xx_hal_mmc.c
  • MMC_Read_IT() : stm32h7xx_hal_mmc.c
  • MMC_ReadExtCSD() : stm32h7xx_hal_mmc.c
  • MMC_SendStatus() : stm32h7xx_hal_mmc.c
  • MMC_Write_IT() : stm32h7xx_hal_mmc.c
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STM32H753xx HAL User Manual: Globals

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- p -

  • PCD_WriteEmptyTxFifo() : stm32h7xx_hal_pcd.c
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STM32H753xx HAL User Manual: Globals

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- q -

  • QSPI_Config() : stm32h7xx_hal_qspi.c
  • QSPI_DMAAbortCplt() : stm32h7xx_hal_qspi.c
  • QSPI_DMAError() : stm32h7xx_hal_qspi.c
  • QSPI_DMARxCplt() : stm32h7xx_hal_qspi.c
  • QSPI_DMATxCplt() : stm32h7xx_hal_qspi.c
  • QSPI_WaitFlagStateUntilTimeout() : stm32h7xx_hal_qspi.c
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STM32H753xx HAL User Manual: Globals

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- r -

  • RCCEx_PLL2_Config() : stm32h7xx_hal_rcc_ex.c
  • RCCEx_PLL3_Config() : stm32h7xx_hal_rcc_ex.c
  • RTC_Bcd2ToByte() : stm32h7xx_hal_rtc.c
  • RTC_ByteToBcd2() : stm32h7xx_hal_rtc.c
  • RTC_EnterInitMode() : stm32h7xx_hal_rtc.c
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STM32H753xx HAL User Manual: Globals

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- s -

  • SAI_Disable() : stm32h7xx_hal_sai.c
  • SAI_DMAAbort() : stm32h7xx_hal_sai.c
  • SAI_DMAError() : stm32h7xx_hal_sai.c
  • SAI_DMARxCplt() : stm32h7xx_hal_sai.c
  • SAI_DMARxHalfCplt() : stm32h7xx_hal_sai.c
  • SAI_DMATxCplt() : stm32h7xx_hal_sai.c
  • SAI_DMATxHalfCplt() : stm32h7xx_hal_sai.c
  • SAI_FillFifo() : stm32h7xx_hal_sai.c
  • SAI_InitI2S() : stm32h7xx_hal_sai.c
  • SAI_InitPCM() : stm32h7xx_hal_sai.c
  • SAI_InterruptFlag() : stm32h7xx_hal_sai.c
  • SAI_Receive_IT16Bit() : stm32h7xx_hal_sai.c
  • SAI_Receive_IT32Bit() : stm32h7xx_hal_sai.c
  • SAI_Receive_IT8Bit() : stm32h7xx_hal_sai.c
  • SAI_Transmit_IT16Bit() : stm32h7xx_hal_sai.c
  • SAI_Transmit_IT32Bit() : stm32h7xx_hal_sai.c
  • SAI_Transmit_IT8Bit() : stm32h7xx_hal_sai.c
  • SD_FindSCR() : stm32h7xx_hal_sd.c
  • SD_HighSpeed() : stm32h7xx_hal_sd.c
  • SD_InitCard() : stm32h7xx_hal_sd.c
  • SD_PowerOFF() : stm32h7xx_hal_sd.c
  • SD_PowerON() : stm32h7xx_hal_sd.c
  • SD_Read_IT() : stm32h7xx_hal_sd.c
  • SD_SendSDStatus() : stm32h7xx_hal_sd.c
  • SD_SendStatus() : stm32h7xx_hal_sd.c
  • SD_WideBus_Disable() : stm32h7xx_hal_sd.c
  • SD_WideBus_Enable() : stm32h7xx_hal_sd.c
  • SD_Write_IT() : stm32h7xx_hal_sd.c
  • SMARTCARD_AdvFeatureConfig() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_CheckIdleState() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMAAbortOnError() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMAError() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMAReceiveCplt() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMARxAbortCallback() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMARxOnlyAbortCallback() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMATransmitCplt() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMATxAbortCallback() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_DMATxOnlyAbortCallback() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_EndRxTransfer() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_EndTransmit_IT() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_EndTxTransfer() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_Receive_IT() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_SetConfig() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_Transmit_IT() : stm32h7xx_hal_smartcard.c
  • SMARTCARD_WaitOnFlagUntilTimeout() : stm32h7xx_hal_smartcard.c
  • SMBUS_ConvertOtherXferOptions() : stm32h7xx_hal_smbus.c
  • SMBUS_Disable_IRQ() : stm32h7xx_hal_smbus.c
  • SMBUS_Enable_IRQ() : stm32h7xx_hal_smbus.c
  • SMBUS_Master_ISR() : stm32h7xx_hal_smbus.c
  • SMBUS_Slave_ISR() : stm32h7xx_hal_smbus.c
  • SMBUS_TransferConfig() : stm32h7xx_hal_smbus.c
  • SMBUS_WaitOnFlagUntilTimeout() : stm32h7xx_hal_smbus.c
  • SPDIFRX_DMACxCplt() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_DMACxHalfCplt() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_DMAError() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_DMARxCplt() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_DMARxHalfCplt() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_ReceiveControlFlow_IT() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_ReceiveDataFlow_IT() : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_WaitOnFlagUntilTimeout() : stm32h7xx_hal_spdifrx.c
  • SPI_2linesRxISR_16BIT() : stm32h7xx_hal_spi.c
  • SPI_2linesRxISR_32BIT() : stm32h7xx_hal_spi.c
  • SPI_2linesRxISR_8BIT() : stm32h7xx_hal_spi.c
  • SPI_2linesTxISR_16BIT() : stm32h7xx_hal_spi.c
  • SPI_2linesTxISR_32BIT() : stm32h7xx_hal_spi.c
  • SPI_2linesTxISR_8BIT() : stm32h7xx_hal_spi.c
  • SPI_AbortRx_ISR() : stm32h7xx_hal_spi.c
  • SPI_AbortTx_ISR() : stm32h7xx_hal_spi.c
  • SPI_CloseRx_ISR() : stm32h7xx_hal_spi.c
  • SPI_CloseRxTx_ISR() : stm32h7xx_hal_spi.c
  • SPI_CloseTx_ISR() : stm32h7xx_hal_spi.c
  • SPI_DMAAbortOnError() : stm32h7xx_hal_spi.c
  • SPI_DMAError() : stm32h7xx_hal_spi.c
  • SPI_DMAHalfReceiveCplt() : stm32h7xx_hal_spi.c
  • SPI_DMAHalfTransmitCplt() : stm32h7xx_hal_spi.c
  • SPI_DMAHalfTransmitReceiveCplt() : stm32h7xx_hal_spi.c
  • SPI_DMAReceiveCplt() : stm32h7xx_hal_spi.c
  • SPI_DMARxAbortCallback() : stm32h7xx_hal_spi.c
  • SPI_DMATransmitCplt() : stm32h7xx_hal_spi.c
  • SPI_DMATransmitReceiveCplt() : stm32h7xx_hal_spi.c
  • SPI_DMATxAbortCallback() : stm32h7xx_hal_spi.c
  • SPI_EndRxTransaction() : stm32h7xx_hal_spi.c
  • SPI_EndRxTxTransaction() : stm32h7xx_hal_spi.c
  • SPI_RxISR_16BIT() : stm32h7xx_hal_spi.c
  • SPI_RxISR_32BIT() : stm32h7xx_hal_spi.c
  • SPI_RxISR_8BIT() : stm32h7xx_hal_spi.c
  • SPI_TxISR_16BIT() : stm32h7xx_hal_spi.c
  • SPI_TxISR_32BIT() : stm32h7xx_hal_spi.c
  • SPI_TxISR_8BIT() : stm32h7xx_hal_spi.c
  • SPI_WaitFifoStateUntilTimeout() : stm32h7xx_hal_spi.c
  • SPI_WaitFlagStateUntilTimeout() : stm32h7xx_hal_spi.c
  • SWPMI_DMAAbortOnError() : stm32h7xx_hal_swpmi.c
  • SWPMI_DMAError() : stm32h7xx_hal_swpmi.c
  • SWPMI_DMAReceiveCplt() : stm32h7xx_hal_swpmi.c
  • SWPMI_DMARxHalfCplt() : stm32h7xx_hal_swpmi.c
  • SWPMI_DMATransmitCplt() : stm32h7xx_hal_swpmi.c
  • SWPMI_DMATxHalfCplt() : stm32h7xx_hal_swpmi.c
  • SWPMI_EndReceive_IT() : stm32h7xx_hal_swpmi.c
  • SWPMI_EndTransmit_IT() : stm32h7xx_hal_swpmi.c
  • SWPMI_EndTransmitReceive_IT() : stm32h7xx_hal_swpmi.c
  • SWPMI_Receive_IT() : stm32h7xx_hal_swpmi.c
  • SWPMI_Transmit_IT() : stm32h7xx_hal_swpmi.c
  • SWPMI_WaitOnFlagSetUntilTimeout() : stm32h7xx_hal_swpmi.c
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STM32H753xx HAL User Manual: Globals

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- t -

  • TIM_Base_SetConfig() : stm32h7xx_hal_tim.c , stm32h7xx_hal_tim.h
  • TIM_CCxChannelCmd() : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim.c
  • TIM_CCxNChannelCmd() : stm32h7xx_hal_tim_ex.c
  • TIM_DMAPeriodElapsedCplt() : stm32h7xx_hal_tim.c
  • TIM_DMATriggerCplt() : stm32h7xx_hal_tim.c
  • TIM_ETR_SetConfig() : stm32h7xx_hal_tim.c , stm32h7xx_hal_tim.h
  • TIM_ITRx_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_OC1_SetConfig() : stm32h7xx_hal_tim.c , stm32h7xx_hal_tim.h
  • TIM_OC2_SetConfig() : stm32h7xx_hal_tim.c , stm32h7xx_hal_tim.h
  • TIM_OC3_SetConfig() : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim.c
  • TIM_OC4_SetConfig() : stm32h7xx_hal_tim.c , stm32h7xx_hal_tim.h
  • TIM_OC5_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_OC6_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_SlaveTimer_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_TI1_ConfigInputStage() : stm32h7xx_hal_tim.c
  • TIM_TI1_SetConfig() : stm32h7xx_hal_tim.c , stm32h7xx_hal_tim.h
  • TIM_TI2_ConfigInputStage() : stm32h7xx_hal_tim.c
  • TIM_TI2_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_TI3_SetConfig() : stm32h7xx_hal_tim.c
  • TIM_TI4_SetConfig() : stm32h7xx_hal_tim.c
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STM32H753xx HAL User Manual: Globals

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  • u

- u -

  • UART_AdvFeatureConfig() : stm32h7xx_hal_uart.c
  • UART_CheckIdleState() : stm32h7xx_hal_uart.c
  • UART_DMAAbortOnError() : stm32h7xx_hal_uart.c
  • UART_DMAError() : stm32h7xx_hal_uart.c
  • UART_DMAReceiveCplt() : stm32h7xx_hal_uart.c
  • UART_DMARxAbortCallback() : stm32h7xx_hal_uart.c
  • UART_DMARxHalfCplt() : stm32h7xx_hal_uart.c
  • UART_DMARxOnlyAbortCallback() : stm32h7xx_hal_uart.c
  • UART_DMATransmitCplt() : stm32h7xx_hal_uart.c
  • UART_DMATxAbortCallback() : stm32h7xx_hal_uart.c
  • UART_DMATxHalfCplt() : stm32h7xx_hal_uart.c
  • UART_DMATxOnlyAbortCallback() : stm32h7xx_hal_uart.c
  • UART_EndRxTransfer() : stm32h7xx_hal_uart.c
  • UART_EndTransmit_IT() : stm32h7xx_hal_uart.c
  • UART_EndTxTransfer() : stm32h7xx_hal_uart.c
  • UART_Receive_IT() : stm32h7xx_hal_uart.c
  • UART_SetConfig() : stm32h7xx_hal_uart.c
  • UART_Transmit_IT() : stm32h7xx_hal_uart.c
  • UART_WaitOnFlagUntilTimeout() : stm32h7xx_hal_uart.c
  • UARTEx_Wakeup_AddressConfig() : stm32h7xx_hal_uart_ex.c
  • USART_CheckIdleState() : stm32h7xx_hal_usart.c
  • USART_DMAAbortOnError() : stm32h7xx_hal_usart.c
  • USART_DMAError() : stm32h7xx_hal_usart.c
  • USART_DMAReceiveCplt() : stm32h7xx_hal_usart.c
  • USART_DMARxAbortCallback() : stm32h7xx_hal_usart.c
  • USART_DMARxHalfCplt() : stm32h7xx_hal_usart.c
  • USART_DMATransmitCplt() : stm32h7xx_hal_usart.c
  • USART_DMATxAbortCallback() : stm32h7xx_hal_usart.c
  • USART_DMATxHalfCplt() : stm32h7xx_hal_usart.c
  • USART_EndTransfer() : stm32h7xx_hal_usart.c
  • USART_EndTransmit_IT() : stm32h7xx_hal_usart.c
  • USART_Receive_IT() : stm32h7xx_hal_usart.c
  • USART_SetConfig() : stm32h7xx_hal_usart.c
  • USART_Transmit_IT() : stm32h7xx_hal_usart.c
  • USART_TransmitReceive_IT() : stm32h7xx_hal_usart.c
  • USART_WaitOnFlagUntilTimeout() : stm32h7xx_hal_usart.c
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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  • a_dfsdm1ChannelHandle : stm32h7xx_hal_dfsdm.c
  • BackupAddr0 : stm32h7xx_hal_eth.h
  • BackupAddr1 : stm32h7xx_hal_eth.h
  • CvtEltSize : stm32h7xx_hal_fdcan.c
  • DESC0 : stm32h7xx_hal_eth.h
  • DESC1 : stm32h7xx_hal_eth.h
  • DESC2 : stm32h7xx_hal_eth.h
  • DESC3 : stm32h7xx_hal_eth.h
  • DLCtoBytes : stm32h7xx_hal_fdcan.c
  • JPEG_ACCHROM_HuffTable : stm32h7xx_hal_jpeg.c
  • JPEG_ACLUM_HuffTable : stm32h7xx_hal_jpeg.c
  • JPEG_CHROM_QuantTable : stm32h7xx_hal_jpeg.c
  • JPEG_DCCHROM_HuffTable : stm32h7xx_hal_jpeg.c
  • JPEG_DCLUM_HuffTable : stm32h7xx_hal_jpeg.c
  • JPEG_LUM_QuantTable : stm32h7xx_hal_jpeg.c
  • JPEG_ZIGZAG_ORDER : stm32h7xx_hal_jpeg.c
  • pFlash : stm32h7xx_hal_flash.c , stm32h7xx_hal_flash_ex.c
  • TimerIdxToTimerId : stm32h7xx_hal_hrtim.c
  • UARTPrescTable : stm32h7xx_hal_uart.h
  • USARTPrescTable : stm32h7xx_hal_usart.h
  • uwNORMemoryDataWidth : stm32h7xx_hal_nor.c
  • uwTick : stm32h7xx_hal.c
  • v_dfsdm1ChannelCounter : stm32h7xx_hal_dfsdm.c
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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  • DMA2D_HandleTypeDef : stm32h7xx_hal_dma2d.h
  • DMA_HandleTypeDef : stm32h7xx_hal_dma.h
  • ETH_BufferTypeDef : stm32h7xx_hal_eth.h
  • ETH_DMADescTypeDef : stm32h7xx_hal_eth.h
  • HAL_LPTIM_StateTypeDef : stm32h7xx_hal_lptim.h
  • HAL_OPAMP_TrimmingValueTypeDef : stm32h7xx_hal_opamp.h
  • HCD_HCStateTypeDef : stm32h7xx_hal_hcd.h
  • HCD_HCTypeDef : stm32h7xx_hal_hcd.h
  • HCD_InitTypeDef : stm32h7xx_hal_hcd.h
  • HCD_TypeDef : stm32h7xx_hal_hcd.h
  • HCD_URBStateTypeDef : stm32h7xx_hal_hcd.h
  • HRTIM_HandleTypeDef : stm32h7xx_hal_hrtim.h
  • I2C_HandleTypeDef : stm32h7xx_hal_i2c.h
  • I2S_HandleTypeDef : stm32h7xx_hal_i2s.h
  • MDMA_HandleTypeDef : stm32h7xx_hal_mdma.h
  • PCD_EPTypeDef : stm32h7xx_hal_pcd.h
  • PCD_InitTypeDef : stm32h7xx_hal_pcd.h
  • PCD_TypeDef : stm32h7xx_hal_pcd.h
  • SAI_HandleTypeDef : stm32h7xx_hal_sai.h
  • SAIcallback : stm32h7xx_hal_sai.h
  • SPI_HandleTypeDef : stm32h7xx_hal_spi.h
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STM32H753xx HAL User Manual: Globals

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  • _
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  • u

- _ -

  • __HAL_LPTIM_StateTypeDef : stm32h7xx_hal_lptim.h

- e -

  • ETH_MediaInterfaceTypeDef : stm32h7xx_hal_eth.h

- f -

  • FLASH_ProcedureTypeDef : stm32h7xx_hal_flash.h

- g -

  • GPIO_PinState : stm32h7xx_hal_gpio.h

- h -

  • HAL_CEC_StateTypeDef : stm32h7xx_hal_cec.h
  • HAL_COMP_StateTypeDef : stm32h7xx_hal_comp.h
  • HAL_CRC_StateTypeDef : stm32h7xx_hal_crc.h
  • HAL_CRYP_STATETypeDef : stm32h7xx_hal_cryp.h
  • HAL_DAC_StateTypeDef : stm32h7xx_hal_dac.h
  • HAL_DCMI_StateTypeDef : stm32h7xx_hal_dcmi.h
  • HAL_DFSDM_Channel_StateTypeDef : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_Filter_StateTypeDef : stm32h7xx_hal_dfsdm.h
  • HAL_DMA2D_StateTypeDef : stm32h7xx_hal_dma2d.h
  • HAL_DMA_CallbackIDTypeDef : stm32h7xx_hal_dma.h
  • HAL_DMA_LevelCompleteTypeDef : stm32h7xx_hal_dma.h
  • HAL_DMA_MemoryTypeDef : stm32h7xx_hal_dma_ex.h
  • HAL_DMA_StateTypeDef : stm32h7xx_hal_dma.h
  • HAL_ETH_StateTypeDef : stm32h7xx_hal_eth.h
  • HAL_FDCAN_StateTypeDef : stm32h7xx_hal_fdcan.h
  • HAL_HASH_PhaseTypeDef : stm32h7xx_hal_hash.h
  • HAL_HASH_StateTypeDef : stm32h7xx_hal_hash.h
  • HAL_HASH_SuspendTypeDef : stm32h7xx_hal_hash.h
  • HAL_HRTIM_StateTypeDef : stm32h7xx_hal_hrtim.h
  • HAL_I2C_ModeTypeDef : stm32h7xx_hal_i2c.h
  • HAL_I2C_StateTypeDef : stm32h7xx_hal_i2c.h
  • HAL_I2S_StateTypeDef : stm32h7xx_hal_i2s.h
  • HAL_IRDA_ErrorTypeDef : stm32h7xx_hal_irda.h
  • HAL_IRDA_StateTypeDef : stm32h7xx_hal_irda.h
  • HAL_JPEG_STATETypeDef : stm32h7xx_hal_jpeg.h
  • HAL_LTDC_StateTypeDef : stm32h7xx_hal_ltdc.h
  • HAL_MDIOS_StateTypeDef : stm32h7xx_hal_mdios.h
  • HAL_MDMA_CallbackIDTypeDef : stm32h7xx_hal_mdma.h
  • HAL_MDMA_LevelCompleteTypeDef : stm32h7xx_hal_mdma.h
  • HAL_MDMA_StateTypeDef : stm32h7xx_hal_mdma.h
  • HAL_MMC_CardStateTypedef : stm32h7xx_hal_mmc.h
  • HAL_MMC_StateTypeDef : stm32h7xx_hal_mmc.h
  • HAL_MMCEx_DMABuffer_MemoryTypeDef : stm32h7xx_hal_mmc_ex.h
  • HAL_NAND_StateTypeDef : stm32h7xx_hal_nand.h
  • HAL_NOR_StateTypeDef : stm32h7xx_hal_nor.h
  • HAL_NOR_StatusTypeDef : stm32h7xx_hal_nor.h
  • HAL_OPAMP_StateTypeDef : stm32h7xx_hal_opamp.h
  • HAL_QSPI_StateTypeDef : stm32h7xx_hal_qspi.h
  • HAL_RNG_StateTypeDef : stm32h7xx_hal_rng.h
  • HAL_RTCStateTypeDef : stm32h7xx_hal_rtc.h
  • HAL_SAI_StateTypeDef : stm32h7xx_hal_sai.h
  • HAL_SD_CardStateTypedef : stm32h7xx_hal_sd.h
  • HAL_SD_StateTypeDef : stm32h7xx_hal_sd.h
  • HAL_SDEx_DMABuffer_MemoryTypeDef : stm32h7xx_hal_sd_ex.h
  • HAL_SDRAM_StateTypeDef : stm32h7xx_hal_sdram.h
  • HAL_SMARTCARD_ErrorTypeDef : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_StateTypeDef : stm32h7xx_hal_smartcard.h
  • HAL_SPDIFRX_StateTypeDef : stm32h7xx_hal_spdifrx.h
  • HAL_SPI_StateTypeDef : stm32h7xx_hal_spi.h
  • HAL_SRAM_StateTypeDef : stm32h7xx_hal_sram.h
  • HAL_SWPMI_StateTypeDef : stm32h7xx_hal_swpmi.h
  • HAL_TIM_ActiveChannel : stm32h7xx_hal_tim.h
  • HAL_TIM_StateTypeDef : stm32h7xx_hal_tim.h
  • HAL_UART_ErrorTypeDef : stm32h7xx_hal_uart.h
  • HAL_UART_StateTypeDef : stm32h7xx_hal_uart.h
  • HAL_USART_ErrorTypeDef : stm32h7xx_hal_usart.h
  • HAL_USART_StateTypeDef : stm32h7xx_hal_usart.h
  • HCD_StateTypeDef : stm32h7xx_hal_hcd.h

- i -

  • I2S_UseTypeDef : stm32h7xx_hal_i2s_ex.c
  • IRDA_ClockSourceTypeDef : stm32h7xx_hal_irda.h
  • IRDA_ControlTypeDef : stm32h7xx_hal_irda.h

- p -

  • PCD_BCD_MsgTypeDef : stm32h7xx_hal_pcd_ex.h
  • PCD_LPM_MsgTypeDef : stm32h7xx_hal_pcd_ex.h
  • PCD_LPM_StateTypeDef : stm32h7xx_hal_pcd.h
  • PCD_StateTypeDef : stm32h7xx_hal_pcd.h

- s -

  • SAI_ModeTypedef : stm32h7xx_hal_sai.c
  • SMARTCARD_ClockSourceTypeDef : stm32h7xx_hal_smartcard.h

- u -

  • UART_ClockSourceTypeDef : stm32h7xx_hal_uart.h
  • USART_ClockSourceTypeDef : stm32h7xx_hal_usart.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
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  • Functions
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  • Enumerations
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  • Defines
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  • l
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  • p
  • s
  • u

- f -

  • FLASH_PROC_ALLBANK_MASSERASE : stm32h7xx_hal_flash.h
  • FLASH_PROC_MASSERASE_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_PROC_MASSERASE_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_PROC_NONE : stm32h7xx_hal_flash.h
  • FLASH_PROC_PROGRAM_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_PROC_PROGRAM_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_PROC_SECTERASE_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_PROC_SECTERASE_BANK2 : stm32h7xx_hal_flash.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
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  • g
  • h
  • i
  • l
  • m
  • p
  • s
  • u

- g -

  • GPIO_PIN_RESET : stm32h7xx_hal_gpio.h
  • GPIO_PIN_SET : stm32h7xx_hal_gpio.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • f
  • g
  • h
  • i
  • l
  • m
  • p
  • s
  • u

- h -

  • HAL_CEC_STATE_BUSY : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_RX : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_RX_TX : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_TX : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_ERROR : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_READY : stm32h7xx_hal_cec.h
  • HAL_CEC_STATE_RESET : stm32h7xx_hal_cec.h
  • HAL_COMP_STATE_BUSY : stm32h7xx_hal_comp.h
  • HAL_COMP_STATE_BUSY_LOCKED : stm32h7xx_hal_comp.h
  • HAL_COMP_STATE_READY : stm32h7xx_hal_comp.h
  • HAL_COMP_STATE_READY_LOCKED : stm32h7xx_hal_comp.h
  • HAL_COMP_STATE_RESET : stm32h7xx_hal_comp.h
  • HAL_COMP_STATE_RESET_LOCKED : stm32h7xx_hal_comp.h
  • HAL_CRC_STATE_BUSY : stm32h7xx_hal_crc.h
  • HAL_CRC_STATE_ERROR : stm32h7xx_hal_crc.h
  • HAL_CRC_STATE_READY : stm32h7xx_hal_crc.h
  • HAL_CRC_STATE_RESET : stm32h7xx_hal_crc.h
  • HAL_CRC_STATE_TIMEOUT : stm32h7xx_hal_crc.h
  • HAL_CRYP_STATE_BUSY : stm32h7xx_hal_cryp.h
  • HAL_CRYP_STATE_READY : stm32h7xx_hal_cryp.h
  • HAL_CRYP_STATE_RESET : stm32h7xx_hal_cryp.h
  • HAL_DAC_STATE_BUSY : stm32h7xx_hal_dac.h
  • HAL_DAC_STATE_ERROR : stm32h7xx_hal_dac.h
  • HAL_DAC_STATE_READY : stm32h7xx_hal_dac.h
  • HAL_DAC_STATE_RESET : stm32h7xx_hal_dac.h
  • HAL_DAC_STATE_TIMEOUT : stm32h7xx_hal_dac.h
  • HAL_DCMI_STATE_BUSY : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_STATE_ERROR : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_STATE_READY : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_STATE_RESET : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_STATE_SUSPENDED : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_STATE_TIMEOUT : stm32h7xx_hal_dcmi.h
  • HAL_DFSDM_CHANNEL_STATE_ERROR : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_CHANNEL_STATE_READY : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_CHANNEL_STATE_RESET : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_ERROR : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_INJ : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_READY : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_REG : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_REG_INJ : stm32h7xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_RESET : stm32h7xx_hal_dfsdm.h
  • HAL_DMA2D_STATE_BUSY : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_STATE_ERROR : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_STATE_READY : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_STATE_RESET : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_STATE_SUSPEND : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_STATE_TIMEOUT : stm32h7xx_hal_dma2d.h
  • HAL_DMA_FULL_TRANSFER : stm32h7xx_hal_dma.h
  • HAL_DMA_HALF_TRANSFER : stm32h7xx_hal_dma.h
  • HAL_DMA_STATE_ABORT : stm32h7xx_hal_dma.h
  • HAL_DMA_STATE_BUSY : stm32h7xx_hal_dma.h
  • HAL_DMA_STATE_ERROR : stm32h7xx_hal_dma.h
  • HAL_DMA_STATE_READY : stm32h7xx_hal_dma.h
  • HAL_DMA_STATE_RESET : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_ABORT_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_ALL_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_CPLT_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_ERROR_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_HALFCPLT_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_M1CPLT_CB_ID : stm32h7xx_hal_dma.h
  • HAL_DMA_XFER_M1HALFCPLT_CB_ID : stm32h7xx_hal_dma.h
  • HAL_ETH_MII_MODE : stm32h7xx_hal_eth.h
  • HAL_ETH_RMII_MODE : stm32h7xx_hal_eth.h
  • HAL_ETH_STATE_BUSY : stm32h7xx_hal_eth.h
  • HAL_ETH_STATE_BUSY_RX : stm32h7xx_hal_eth.h
  • HAL_ETH_STATE_BUSY_TX : stm32h7xx_hal_eth.h
  • HAL_ETH_STATE_ERROR : stm32h7xx_hal_eth.h
  • HAL_ETH_STATE_READY : stm32h7xx_hal_eth.h
  • HAL_ETH_STATE_RESET : stm32h7xx_hal_eth.h
  • HAL_FDCAN_STATE_BUSY : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_STATE_ERROR : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_STATE_READY : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_STATE_RESET : stm32h7xx_hal_fdcan.h
  • HAL_HASH_PHASE_HMAC_STEP_1 : stm32h7xx_hal_hash.h
  • HAL_HASH_PHASE_HMAC_STEP_2 : stm32h7xx_hal_hash.h
  • HAL_HASH_PHASE_HMAC_STEP_3 : stm32h7xx_hal_hash.h
  • HAL_HASH_PHASE_PROCESS : stm32h7xx_hal_hash.h
  • HAL_HASH_PHASE_READY : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_BUSY : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_ERROR : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_READY : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_RESET : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_SUSPENDED : stm32h7xx_hal_hash.h
  • HAL_HASH_STATE_TIMEOUT : stm32h7xx_hal_hash.h
  • HAL_HASH_SUSPEND : stm32h7xx_hal_hash.h
  • HAL_HASH_SUSPEND_NONE : stm32h7xx_hal_hash.h
  • HAL_HCD_STATE_BUSY : stm32h7xx_hal_hcd.h
  • HAL_HCD_STATE_ERROR : stm32h7xx_hal_hcd.h
  • HAL_HCD_STATE_READY : stm32h7xx_hal_hcd.h
  • HAL_HCD_STATE_RESET : stm32h7xx_hal_hcd.h
  • HAL_HCD_STATE_TIMEOUT : stm32h7xx_hal_hcd.h
  • HAL_HRTIM_STATE_BUSY : stm32h7xx_hal_hrtim.h
  • HAL_HRTIM_STATE_ERROR : stm32h7xx_hal_hrtim.h
  • HAL_HRTIM_STATE_READY : stm32h7xx_hal_hrtim.h
  • HAL_HRTIM_STATE_TIMEOUT : stm32h7xx_hal_hrtim.h
  • HAL_I2C_MODE_MASTER : stm32h7xx_hal_i2c.h
  • HAL_I2C_MODE_MEM : stm32h7xx_hal_i2c.h
  • HAL_I2C_MODE_NONE : stm32h7xx_hal_i2c.h
  • HAL_I2C_MODE_SLAVE : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_ABORT : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX_LISTEN : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX_LISTEN : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_ERROR : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_LISTEN : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_READY : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_RESET : stm32h7xx_hal_i2c.h
  • HAL_I2C_STATE_TIMEOUT : stm32h7xx_hal_i2c.h
  • HAL_I2S_STATE_BUSY : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_RX : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX_RX : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_ERROR : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_READY : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_RESET : stm32h7xx_hal_i2s.h
  • HAL_I2S_STATE_TIMEOUT : stm32h7xx_hal_i2s.h
  • HAL_IRDA_ERROR_BUSY : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_DMA : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_FE : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_NE : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_NONE : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_ORE : stm32h7xx_hal_irda.h
  • HAL_IRDA_ERROR_PE : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_RX : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX_RX : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_ERROR : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_READY : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_RESET : stm32h7xx_hal_irda.h
  • HAL_IRDA_STATE_TIMEOUT : stm32h7xx_hal_irda.h
  • HAL_JPEG_STATE_BUSY : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_BUSY_DECODING : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_BUSY_ENCODING : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_ERROR : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_READY : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_RESET : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_STATE_TIMEOUT : stm32h7xx_hal_jpeg.h
  • HAL_LPTIM_STATE_BUSY : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_STATE_ERROR : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_STATE_READY : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_STATE_RESET : stm32h7xx_hal_lptim.h
  • HAL_LPTIM_STATE_TIMEOUT : stm32h7xx_hal_lptim.h
  • HAL_LTDC_STATE_BUSY : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_STATE_ERROR : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_STATE_READY : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_STATE_RESET : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_STATE_TIMEOUT : stm32h7xx_hal_ltdc.h
  • HAL_MDIOS_STATE_BUSY : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_STATE_ERROR : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_STATE_READY : stm32h7xx_hal_mdios.h
  • HAL_MDIOS_STATE_RESET : stm32h7xx_hal_mdios.h
  • HAL_MDMA_BLOCK_TRANSFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_BUFFER_TRANSFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_FULL_TRANSFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_REPEAT_BLOCK_TRANSFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_STATE_ABORT : stm32h7xx_hal_mdma.h
  • HAL_MDMA_STATE_BUSY : stm32h7xx_hal_mdma.h
  • HAL_MDMA_STATE_ERROR : stm32h7xx_hal_mdma.h
  • HAL_MDMA_STATE_READY : stm32h7xx_hal_mdma.h
  • HAL_MDMA_STATE_RESET : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_ABORT_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_ALL_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_BLOCKCPLT_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_BUFFERCPLT_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_CPLT_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_ERROR_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID : stm32h7xx_hal_mdma.h
  • HAL_MMC_CARD_DISCONNECTED : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_ERROR : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_IDENTIFICATION : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_PROGRAMMING : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_READY : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_RECEIVING : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_SENDING : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_STANDBY : stm32h7xx_hal_mmc.h
  • HAL_MMC_CARD_TRANSFER : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_BUSY : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_ERROR : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_PROGRAMMING : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_READY : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_RECEIVING : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_RESET : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_TIMEOUT : stm32h7xx_hal_mmc.h
  • HAL_MMC_STATE_TRANSFER : stm32h7xx_hal_mmc.h
  • HAL_NAND_STATE_BUSY : stm32h7xx_hal_nand.h
  • HAL_NAND_STATE_ERROR : stm32h7xx_hal_nand.h
  • HAL_NAND_STATE_READY : stm32h7xx_hal_nand.h
  • HAL_NAND_STATE_RESET : stm32h7xx_hal_nand.h
  • HAL_NOR_STATE_BUSY : stm32h7xx_hal_nor.h
  • HAL_NOR_STATE_ERROR : stm32h7xx_hal_nor.h
  • HAL_NOR_STATE_PROTECTED : stm32h7xx_hal_nor.h
  • HAL_NOR_STATE_READY : stm32h7xx_hal_nor.h
  • HAL_NOR_STATE_RESET : stm32h7xx_hal_nor.h
  • HAL_NOR_STATUS_ERROR : stm32h7xx_hal_nor.h
  • HAL_NOR_STATUS_ONGOING : stm32h7xx_hal_nor.h
  • HAL_NOR_STATUS_SUCCESS : stm32h7xx_hal_nor.h
  • HAL_NOR_STATUS_TIMEOUT : stm32h7xx_hal_nor.h
  • HAL_OPAMP_STATE_BUSY : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_STATE_BUSYLOCKED : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_STATE_CALIBBUSY : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_STATE_READY : stm32h7xx_hal_opamp.h
  • HAL_OPAMP_STATE_RESET : stm32h7xx_hal_opamp.h
  • HAL_PCD_STATE_BUSY : stm32h7xx_hal_pcd.h
  • HAL_PCD_STATE_ERROR : stm32h7xx_hal_pcd.h
  • HAL_PCD_STATE_READY : stm32h7xx_hal_pcd.h
  • HAL_PCD_STATE_RESET : stm32h7xx_hal_pcd.h
  • HAL_PCD_STATE_TIMEOUT : stm32h7xx_hal_pcd.h
  • HAL_QSPI_STATE_ABORT : stm32h7xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY : stm32h7xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_AUTO_POLLING : stm32h7xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_INDIRECT_RX : stm32h7xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_INDIRECT_TX : stm32h7xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_MEM_MAPPED : stm32h7xx_hal_qspi.h
  • HAL_QSPI_STATE_ERROR : stm32h7xx_hal_qspi.h
  • HAL_QSPI_STATE_READY : stm32h7xx_hal_qspi.h
  • HAL_QSPI_STATE_RESET : stm32h7xx_hal_qspi.h
  • HAL_RNG_STATE_BUSY : stm32h7xx_hal_rng.h
  • HAL_RNG_STATE_ERROR : stm32h7xx_hal_rng.h
  • HAL_RNG_STATE_READY : stm32h7xx_hal_rng.h
  • HAL_RNG_STATE_RESET : stm32h7xx_hal_rng.h
  • HAL_RNG_STATE_TIMEOUT : stm32h7xx_hal_rng.h
  • HAL_RTC_STATE_BUSY : stm32h7xx_hal_rtc.h
  • HAL_RTC_STATE_ERROR : stm32h7xx_hal_rtc.h
  • HAL_RTC_STATE_READY : stm32h7xx_hal_rtc.h
  • HAL_RTC_STATE_RESET : stm32h7xx_hal_rtc.h
  • HAL_RTC_STATE_TIMEOUT : stm32h7xx_hal_rtc.h
  • HAL_SAI_STATE_BUSY : stm32h7xx_hal_sai.h
  • HAL_SAI_STATE_BUSY_RX : stm32h7xx_hal_sai.h
  • HAL_SAI_STATE_BUSY_TX : stm32h7xx_hal_sai.h
  • HAL_SAI_STATE_READY : stm32h7xx_hal_sai.h
  • HAL_SAI_STATE_RESET : stm32h7xx_hal_sai.h
  • HAL_SD_CARD_DISCONNECTED : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_ERROR : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_IDENTIFICATION : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_PROGRAMMING : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_READY : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_RECEIVING : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_SENDING : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_STANDBY : stm32h7xx_hal_sd.h
  • HAL_SD_CARD_TRANSFER : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_BUSY : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_ERROR : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_PROGRAMMING : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_READY : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_RECEIVING : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_RESET : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_TIMEOUT : stm32h7xx_hal_sd.h
  • HAL_SD_STATE_TRANSFER : stm32h7xx_hal_sd.h
  • HAL_SDRAM_STATE_BUSY : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_STATE_ERROR : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_STATE_PRECHARGED : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_STATE_READY : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_STATE_RESET : stm32h7xx_hal_sdram.h
  • HAL_SDRAM_STATE_WRITE_PROTECTED : stm32h7xx_hal_sdram.h
  • HAL_SMARTCARD_ERROR_DMA : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_FE : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NE : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NONE : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_ORE : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_PE : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_RTO : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_UDR : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_RX : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX_RX : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_ERROR : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_READY : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_RESET : stm32h7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_TIMEOUT : stm32h7xx_hal_smartcard.h
  • HAL_SPDIFRX_STATE_BUSY : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_BUSY_CX : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_BUSY_RX : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_ERROR : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_READY : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_RESET : stm32h7xx_hal_spdifrx.h
  • HAL_SPI_STATE_ABORT : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_RX : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX_RX : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_ERROR : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_READY : stm32h7xx_hal_spi.h
  • HAL_SPI_STATE_RESET : stm32h7xx_hal_spi.h
  • HAL_SRAM_STATE_BUSY : stm32h7xx_hal_sram.h
  • HAL_SRAM_STATE_ERROR : stm32h7xx_hal_sram.h
  • HAL_SRAM_STATE_PROTECTED : stm32h7xx_hal_sram.h
  • HAL_SRAM_STATE_READY : stm32h7xx_hal_sram.h
  • HAL_SRAM_STATE_RESET : stm32h7xx_hal_sram.h
  • HAL_SWPMI_STATE_BUSY : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_BUSY_RX : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_BUSY_TX : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_BUSY_TX_RX : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_ERROR : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_READY : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_RESET : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_STATE_TIMEOUT : stm32h7xx_hal_swpmi.h
  • HAL_TIM_ACTIVE_CHANNEL_1 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_2 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_3 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_4 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_5 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_6 : stm32h7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_CLEARED : stm32h7xx_hal_tim.h
  • HAL_TIM_STATE_BUSY : stm32h7xx_hal_tim.h
  • HAL_TIM_STATE_ERROR : stm32h7xx_hal_tim.h
  • HAL_TIM_STATE_READY : stm32h7xx_hal_tim.h
  • HAL_TIM_STATE_RESET : stm32h7xx_hal_tim.h
  • HAL_TIM_STATE_TIMEOUT : stm32h7xx_hal_tim.h
  • HAL_UART_ERROR_DMA : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_FE : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_NE : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_NONE : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_ORE : stm32h7xx_hal_uart.h
  • HAL_UART_ERROR_PE : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_BUSY : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_BUSY_RX : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX_RX : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_ERROR : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_READY : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_RESET : stm32h7xx_hal_uart.h
  • HAL_UART_STATE_TIMEOUT : stm32h7xx_hal_uart.h
  • HAL_USART_ERROR_DMA : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_FE : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_NE : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_NONE : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_ORE : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_PE : stm32h7xx_hal_usart.h
  • HAL_USART_ERROR_UDR : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_BUSY : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_BUSY_RX : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX_RX : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_ERROR : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_READY : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_RESET : stm32h7xx_hal_usart.h
  • HAL_USART_STATE_TIMEOUT : stm32h7xx_hal_usart.h
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STM32H753xx HAL User Manual: Globals

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- i -

  • I2S_USE_I2S : stm32h7xx_hal_i2s_ex.c
  • I2S_USE_I2SEXT : stm32h7xx_hal_i2s_ex.c
  • IRDA_BAUDRATE : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_CSI : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_D2PCLK1 : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_D2PCLK2 : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_D3PCLK1 : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_HSI : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_LSE : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PLL2Q : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PLL3Q : stm32h7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_UNDEFINED : stm32h7xx_hal_irda.h
  • IRDA_MODE : stm32h7xx_hal_irda.h
  • IRDA_PARITY : stm32h7xx_hal_irda.h
  • IRDA_POWERMODE : stm32h7xx_hal_irda.h
  • IRDA_PRESCALER : stm32h7xx_hal_irda.h
  • IRDA_WORDLENGTH : stm32h7xx_hal_irda.h
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STM32H753xx HAL User Manual: Globals

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- l -

  • LPM_L0 : stm32h7xx_hal_pcd.h
  • LPM_L1 : stm32h7xx_hal_pcd.h
  • LPM_L2 : stm32h7xx_hal_pcd.h
  • LPM_L3 : stm32h7xx_hal_pcd.h
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STM32H753xx HAL User Manual: Globals

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- m -

  • MEMORY0 : stm32h7xx_hal_dma_ex.h
  • MEMORY1 : stm32h7xx_hal_dma_ex.h
  • MMC_DMA_BUFFER0 : stm32h7xx_hal_mmc_ex.h
  • MMC_DMA_BUFFER1 : stm32h7xx_hal_mmc_ex.h
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STM32H753xx HAL User Manual: Globals

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- p -

  • PCD_BCD_CHARGING_DOWNSTREAM_PORT : stm32h7xx_hal_pcd_ex.h
  • PCD_BCD_CONTACT_DETECTION : stm32h7xx_hal_pcd_ex.h
  • PCD_BCD_DEDICATED_CHARGING_PORT : stm32h7xx_hal_pcd_ex.h
  • PCD_BCD_DISCOVERY_COMPLETED : stm32h7xx_hal_pcd_ex.h
  • PCD_BCD_ERROR : stm32h7xx_hal_pcd_ex.h
  • PCD_BCD_STD_DOWNSTREAM_PORT : stm32h7xx_hal_pcd_ex.h
  • PCD_LPM_L0_ACTIVE : stm32h7xx_hal_pcd_ex.h
  • PCD_LPM_L1_ACTIVE : stm32h7xx_hal_pcd_ex.h
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STM32H753xx HAL User Manual: Globals

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- s -

  • SAI_MODE_DMA : stm32h7xx_hal_sai.c
  • SAI_MODE_IT : stm32h7xx_hal_sai.c
  • SD_DMA_BUFFER0 : stm32h7xx_hal_sd_ex.h
  • SD_DMA_BUFFER1 : stm32h7xx_hal_sd_ex.h
  • SMARTCARD_CLOCKSOURCE_CSI : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_D2PCLK1 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_D2PCLK2 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_D3PCLK1 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_HSI : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_LSE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PLL2Q : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PLL3Q : stm32h7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_UNDEFINED : stm32h7xx_hal_smartcard.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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- u -

  • UART_CLOCKSOURCE_CSI : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_D2PCLK1 : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_D2PCLK2 : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_D3PCLK1 : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_HSI : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_LSE : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_PLL2 : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_PLL3 : stm32h7xx_hal_uart.h
  • UART_CLOCKSOURCE_UNDEFINED : stm32h7xx_hal_uart.h
  • USART_CLOCKSOURCE_CSI : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_D2PCLK1 : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_D2PCLK2 : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_D3PCLK1 : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_HSI : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_LSE : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_PLL2 : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_PLL3 : stm32h7xx_hal_usart.h
  • USART_CLOCKSOURCE_UNDEFINED : stm32h7xx_hal_usart.h
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STM32H753xx HAL User Manual: Globals

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- _ -

  • __HAL_ADC_CLEAR_FLAG : stm32h7xx_hal_adc.h
  • __HAL_ADC_DISABLE_IT : stm32h7xx_hal_adc.h
  • __HAL_ADC_ENABLE_IT : stm32h7xx_hal_adc.h
  • __HAL_ADC_GET_FLAG : stm32h7xx_hal_adc.h
  • __HAL_ADC_GET_IT_SOURCE : stm32h7xx_hal_adc.h
  • __HAL_ADC_RESET_HANDLE_STATE : stm32h7xx_hal_adc.h
  • __HAL_BDMA_GET_GI_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_CEC_CLEAR_FLAG : stm32h7xx_hal_cec.h
  • __HAL_CEC_CLEAR_OAR : stm32h7xx_hal_cec.h
  • __HAL_CEC_DISABLE : stm32h7xx_hal_cec.h
  • __HAL_CEC_DISABLE_IT : stm32h7xx_hal_cec.h
  • __HAL_CEC_ENABLE : stm32h7xx_hal_cec.h
  • __HAL_CEC_ENABLE_IT : stm32h7xx_hal_cec.h
  • __HAL_CEC_FIRST_BYTE_TX_SET : stm32h7xx_hal_cec.h
  • __HAL_CEC_GET_FLAG : stm32h7xx_hal_cec.h
  • __HAL_CEC_GET_IT_SOURCE : stm32h7xx_hal_cec.h
  • __HAL_CEC_GET_TRANSMISSION_END_FLAG : stm32h7xx_hal_cec.h
  • __HAL_CEC_GET_TRANSMISSION_START_FLAG : stm32h7xx_hal_cec.h
  • __HAL_CEC_LAST_BYTE_TX_SET : stm32h7xx_hal_cec.h
  • __HAL_CEC_RESET_HANDLE_STATE : stm32h7xx_hal_cec.h
  • __HAL_CEC_SET_OAR : stm32h7xx_hal_cec.h
  • __HAL_COMP_CLEAR_C1IFLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_CLEAR_C2IFLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_CLEAR_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_CLEAR_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GENERATE_SWIT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GET_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTID3_DISABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTID3_ENABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_CLEAR_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GENERATE_SWIT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GET_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTID3_DISABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTID3_ENABLE_EVENT : stm32h7xx_hal_comp.h
  • __HAL_COMP_DISABLE : stm32h7xx_hal_comp.h
  • __HAL_COMP_DISABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_DISABLE_OR : stm32h7xx_hal_comp.h
  • __HAL_COMP_ENABLE : stm32h7xx_hal_comp.h
  • __HAL_COMP_ENABLE_IT : stm32h7xx_hal_comp.h
  • __HAL_COMP_ENABLE_OR : stm32h7xx_hal_comp.h
  • __HAL_COMP_GET_FLAG : stm32h7xx_hal_comp.h
  • __HAL_COMP_GET_IT_SOURCE : stm32h7xx_hal_comp.h
  • __HAL_COMP_IS_LOCKED : stm32h7xx_hal_comp.h
  • __HAL_COMP_LOCK : stm32h7xx_hal_comp.h
  • __HAL_COMP_RESET_HANDLE_STATE : stm32h7xx_hal_comp.h
  • __HAL_CRC_DR_RESET : stm32h7xx_hal_crc.h
  • __HAL_CRC_GET_IDR : stm32h7xx_hal_crc.h
  • __HAL_CRC_INITIALCRCVALUE_CONFIG : stm32h7xx_hal_crc.h
  • __HAL_CRC_OUTPUTREVERSAL_DISABLE : stm32h7xx_hal_crc_ex.h
  • __HAL_CRC_OUTPUTREVERSAL_ENABLE : stm32h7xx_hal_crc_ex.h
  • __HAL_CRC_POLYNOMIAL_CONFIG : stm32h7xx_hal_crc_ex.h
  • __HAL_CRC_RESET_HANDLE_STATE : stm32h7xx_hal_crc.h
  • __HAL_CRC_SET_IDR : stm32h7xx_hal_crc.h
  • __HAL_CRYP_DISABLE : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_DISABLE_IT : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_ENABLE : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_ENABLE_IT : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_GET_FLAG : stm32h7xx_hal_cryp.h
  • __HAL_CRYP_GET_IT : stm32h7xx_hal_cryp.h
  • __HAL_DAC_CLEAR_FLAG : stm32h7xx_hal_dac.h
  • __HAL_DAC_DISABLE : stm32h7xx_hal_dac.h
  • __HAL_DAC_DISABLE_IT : stm32h7xx_hal_dac.h
  • __HAL_DAC_ENABLE : stm32h7xx_hal_dac.h
  • __HAL_DAC_ENABLE_IT : stm32h7xx_hal_dac.h
  • __HAL_DAC_GET_FLAG : stm32h7xx_hal_dac.h
  • __HAL_DAC_GET_IT_SOURCE : stm32h7xx_hal_dac.h
  • __HAL_DAC_RESET_HANDLE_STATE : stm32h7xx_hal_dac.h
  • __HAL_DBGMCU_FREEZE_FDCAN : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_HRTIM : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_IWDG1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM5 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_RTC : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM12 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM13 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM14 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM15 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM16 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM17 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM5 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM6 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM7 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM8 : stm32h7xx_hal.h
  • __HAL_DBGMCU_FREEZE_WWDG1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_FDCAN : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_HRTIM : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_I2C1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_I2C2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_I2C3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_I2C4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_IWDG1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_LPTIM1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_LPTIM2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_LPTIM3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_LPTIM4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_LPTIM5 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_RTC : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM1 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM12 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM13 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM14 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM15 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM16 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM17 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM2 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM3 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM4 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM5 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM6 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM7 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_TIM8 : stm32h7xx_hal.h
  • __HAL_DBGMCU_UnFreeze_WWDG1 : stm32h7xx_hal.h
  • __HAL_DCMI_CLEAR_FLAG : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_DISABLE : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_DISABLE_IT : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_ENABLE : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_ENABLE_IT : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_GET_FLAG : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_GET_IT_SOURCE : stm32h7xx_hal_dcmi.h
  • __HAL_DCMI_RESET_HANDLE_STATE : stm32h7xx_hal_dcmi.h
  • __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE : stm32h7xx_hal_dfsdm.h
  • __HAL_DFSDM_FILTER_RESET_HANDLE_STATE : stm32h7xx_hal_dfsdm.h
  • __HAL_DMA2D_CLEAR_FLAG : stm32h7xx_hal_dma2d.h
  • __HAL_DMA2D_DISABLE_IT : stm32h7xx_hal_dma2d.h
  • __HAL_DMA2D_ENABLE : stm32h7xx_hal_dma2d.h
  • __HAL_DMA2D_ENABLE_IT : stm32h7xx_hal_dma2d.h
  • __HAL_DMA2D_GET_FLAG : stm32h7xx_hal_dma2d.h
  • __HAL_DMA2D_GET_IT_SOURCE : stm32h7xx_hal_dma2d.h
  • __HAL_DMA2D_RESET_HANDLE_STATE : stm32h7xx_hal_dma2d.h
  • __HAL_DMA_CLEAR_FLAG : stm32h7xx_hal_dma.h
  • __HAL_DMA_D2_DISABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_DMA_D2_ENABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_DMA_D2_GET_IT_SOURCE : stm32h7xx_hal_dma.h
  • __HAL_DMA_D3_DISABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_DMA_D3_ENABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_DMA_D3_GET_IT_SOURCE : stm32h7xx_hal_dma.h
  • __HAL_DMA_DISABLE : stm32h7xx_hal_dma.h
  • __HAL_DMA_DISABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_DMA_ENABLE : stm32h7xx_hal_dma.h
  • __HAL_DMA_ENABLE_IT : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_COUNTER : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_DME_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_FE_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_FLAG : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_FS : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_HT_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_IT_SOURCE : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_TC_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_DMA_GET_TE_FLAG_INDEX : stm32h7xx_hal_dma.h
  • __HAL_DMA_RESET_HANDLE_STATE : stm32h7xx_hal_dma.h
  • __HAL_DMA_SET_COUNTER : stm32h7xx_hal_dma.h
  • __HAL_ETH_DMA_CLEAR_FLAG : stm32h7xx_hal_eth.h
  • __HAL_ETH_DMA_CLEAR_IT : stm32h7xx_hal_eth.h
  • __HAL_ETH_DMA_DISABLE_IT : stm32h7xx_hal_eth.h
  • __HAL_ETH_DMA_ENABLE_IT : stm32h7xx_hal_eth.h
  • __HAL_ETH_DMA_GET_FLAG : stm32h7xx_hal_eth.h
  • __HAL_ETH_DMA_GET_IT : stm32h7xx_hal_eth.h
  • __HAL_ETH_DMA_GET_IT_SOURCE : stm32h7xx_hal_eth.h
  • __HAL_ETH_MAC_DISABLE_IT : stm32h7xx_hal_eth.h
  • __HAL_ETH_MAC_ENABLE_IT : stm32h7xx_hal_eth.h
  • __HAL_ETH_MAC_GET_IT : stm32h7xx_hal_eth.h
  • __HAL_ETH_RESET_HANDLE_STATE : stm32h7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG : stm32h7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_ENABLE_IT : stm32h7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT : stm32h7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_GET_FLAG : stm32h7xx_hal_eth.h
  • __HAL_FDCAN_CLEAR_FLAG : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_CLEAR_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_DISABLE_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_ENABLE_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_GET_FLAG : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_GET_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_GET_IT_SOURCE : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_RESET_HANDLE_STATE : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_CLEAR_FLAG : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_CLEAR_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_DISABLE_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_ENABLE_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_GET_FLAG : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_GET_IT : stm32h7xx_hal_fdcan.h
  • __HAL_FDCAN_TT_GET_IT_SOURCE : stm32h7xx_hal_fdcan.h
  • __HAL_FLASH_CALC_BOOT_BASE_ADR : stm32h7xx_hal_flash_ex.h
  • __HAL_FLASH_CLEAR_FLAG : stm32h7xx_hal_flash.h
  • __HAL_FLASH_CLEAR_FLAG_BANK1 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_CLEAR_FLAG_BANK2 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT : stm32h7xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT_BANK1 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT_BANK2 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT : stm32h7xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT_BANK1 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT_BANK2 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG : stm32h7xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG_BANK1 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG_BANK2 : stm32h7xx_hal_flash.h
  • __HAL_FLASH_GET_LATENCY : stm32h7xx_hal_flash.h
  • __HAL_FLASH_SET_LATENCY : stm32h7xx_hal_flash.h
  • __HAL_GPIO_EXTI_CLEAR_FLAG : stm32h7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_IT : stm32h7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GENERATE_SWIT : stm32h7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FLAG : stm32h7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_IT : stm32h7xx_hal_gpio.h
  • __HAL_HASH_CLEAR_FLAG : stm32h7xx_hal_hash.h
  • __HAL_HASH_DISABLE_IT : stm32h7xx_hal_hash.h
  • __HAL_HASH_ENABLE_IT : stm32h7xx_hal_hash.h
  • __HAL_HASH_GET_FLAG : stm32h7xx_hal_hash.h
  • __HAL_HASH_INIT : stm32h7xx_hal_hash.h
  • __HAL_HASH_RESET_HANDLE_STATE : stm32h7xx_hal_hash.h
  • __HAL_HASH_RESET_HANDLE_STATUS : stm32h7xx_hal_hash.h
  • __HAL_HASH_RESET_MDMAT : stm32h7xx_hal_hash.h
  • __HAL_HASH_SET_MDMAT : stm32h7xx_hal_hash.h
  • __HAL_HASH_SET_NBVALIDBITS : stm32h7xx_hal_hash.h
  • __HAL_HASH_START_DIGEST : stm32h7xx_hal_hash.h
  • __HAL_HCD_CLEAR_FLAG : stm32h7xx_hal_hcd.h
  • __HAL_HCD_CLEAR_HC_INT : stm32h7xx_hal_hcd.h
  • __HAL_HCD_DISABLE : stm32h7xx_hal_hcd.h
  • __HAL_HCD_ENABLE : stm32h7xx_hal_hcd.h
  • __HAL_HCD_GET_FLAG : stm32h7xx_hal_hcd.h
  • __HAL_HCD_IS_INVALID_INTERRUPT : stm32h7xx_hal_hcd.h
  • __HAL_HCD_MASK_ACK_HC_INT : stm32h7xx_hal_hcd.h
  • __HAL_HCD_MASK_HALT_HC_INT : stm32h7xx_hal_hcd.h
  • __HAL_HCD_UNMASK_ACK_HC_INT : stm32h7xx_hal_hcd.h
  • __HAL_HCD_UNMASK_HALT_HC_INT : stm32h7xx_hal_hcd.h
  • __HAL_HRTIM_CLEAR_FLAG : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_CLEAR_IT : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_DISABLE : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_DISABLE_IT : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_ENABLE : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_ENABLE_IT : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_GET_FLAG : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_GET_ITSTATUS : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_GETCLOCKPRESCALER : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_GETCOMPARE : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_GETCOUNTER : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_GETPERIOD : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_MASTER_CLEAR_FLAG : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_MASTER_CLEAR_IT : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_MASTER_DISABLE_DMA : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_MASTER_DISABLE_IT : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_MASTER_ENABLE_DMA : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_MASTER_ENABLE_IT : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_MASTER_GET_FLAG : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_MASTER_GET_ITSTATUS : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_RESET_HANDLE_STATE : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_SETCLOCKPRESCALER : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_SETCOMPARE : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_SETCOUNTER : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_SETPERIOD : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_TIMER_CLEAR_FLAG : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_TIMER_CLEAR_IT : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_TIMER_DISABLE_DMA : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_TIMER_DISABLE_IT : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_TIMER_ENABLE_DMA : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_TIMER_ENABLE_IT : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_TIMER_GET_FLAG : stm32h7xx_hal_hrtim.h
  • __HAL_HRTIM_TIMER_GET_ITSTATUS : stm32h7xx_hal_hrtim.h
  • __HAL_HSEM_CLEAR_FLAG : stm32h7xx_hal_hsem.h
  • __HAL_HSEM_DISABLE_IT : stm32h7xx_hal_hsem.h
  • __HAL_HSEM_ENABLE_IT : stm32h7xx_hal_hsem.h
  • __HAL_HSEM_GET_FLAG : stm32h7xx_hal_hsem.h
  • __HAL_HSEM_GET_IT : stm32h7xx_hal_hsem.h
  • __HAL_HSEM_SEMID_TO_MASK : stm32h7xx_hal_hsem.h
  • __HAL_I2C_CLEAR_FLAG : stm32h7xx_hal_i2c.h
  • __HAL_I2C_DISABLE : stm32h7xx_hal_i2c.h
  • __HAL_I2C_DISABLE_IT : stm32h7xx_hal_i2c.h
  • __HAL_I2C_ENABLE : stm32h7xx_hal_i2c.h
  • __HAL_I2C_ENABLE_IT : stm32h7xx_hal_i2c.h
  • __HAL_I2C_GENERATE_NACK : stm32h7xx_hal_i2c.h
  • __HAL_I2C_GET_FLAG : stm32h7xx_hal_i2c.h
  • __HAL_I2C_GET_IT_SOURCE : stm32h7xx_hal_i2c.h
  • __HAL_I2C_RESET_HANDLE_STATE : stm32h7xx_hal_i2c.h
  • __HAL_I2S_CLEAR_FREFLAG : stm32h7xx_hal_i2s.h
  • __HAL_I2S_CLEAR_OVRFLAG : stm32h7xx_hal_i2s.h
  • __HAL_I2S_CLEAR_UDRFLAG : stm32h7xx_hal_i2s.h
  • __HAL_I2S_DISABLE : stm32h7xx_hal_i2s.h
  • __HAL_I2S_DISABLE_IT : stm32h7xx_hal_i2s.h
  • __HAL_I2S_ENABLE : stm32h7xx_hal_i2s.h
  • __HAL_I2S_ENABLE_IT : stm32h7xx_hal_i2s.h
  • __HAL_I2S_GET_FLAG : stm32h7xx_hal_i2s.h
  • __HAL_I2S_GET_IT_SOURCE : stm32h7xx_hal_i2s.h
  • __HAL_I2S_RESET_HANDLE_STATE : stm32h7xx_hal_i2s.h
  • __HAL_IRDA_CLEAR_FEFLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_FLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IDLEFLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IT : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_NEFLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_OREFLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_CLEAR_PEFLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_DISABLE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_DISABLE_IT : stm32h7xx_hal_irda.h
  • __HAL_IRDA_ENABLE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_ENABLE_IT : stm32h7xx_hal_irda.h
  • __HAL_IRDA_FLUSH_DRREGISTER : stm32h7xx_hal_irda.h
  • __HAL_IRDA_GET_FLAG : stm32h7xx_hal_irda.h
  • __HAL_IRDA_GET_IT : stm32h7xx_hal_irda.h
  • __HAL_IRDA_GET_IT_SOURCE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_RESET_HANDLE_STATE : stm32h7xx_hal_irda.h
  • __HAL_IRDA_SEND_REQ : stm32h7xx_hal_irda.h
  • __HAL_IWDG_RELOAD_COUNTER : stm32h7xx_hal_iwdg.h
  • __HAL_IWDG_START : stm32h7xx_hal_iwdg.h
  • __HAL_JPEG_CLEAR_FLAG : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_DISABLE : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_DISABLE_IT : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_ENABLE : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_ENABLE_IT : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_GET_FLAG : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_GET_IT_SOURCE : stm32h7xx_hal_jpeg.h
  • __HAL_JPEG_RESET_HANDLE_STATE : stm32h7xx_hal_jpeg.h
  • __HAL_LPTIM_AUTORELOAD_SET : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_CLEAR_FLAG : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_COMPARE_SET : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE_IT : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE_IT : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_GET_FLAG : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_GET_IT_SOURCE : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_RESET_COUNTER : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_RESET_COUNTER_AFTERREAD : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_RESET_HANDLE_STATE : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_START_CONTINUOUS : stm32h7xx_hal_lptim.h
  • __HAL_LPTIM_START_SINGLE : stm32h7xx_hal_lptim.h
  • __HAL_LTDC_CLEAR_FLAG : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_DISABLE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_DISABLE_IT : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_ENABLE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_ENABLE_IT : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_GET_FLAG : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_GET_IT_SOURCE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_LAYER_DISABLE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_LAYER_ENABLE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_RESET_HANDLE_STATE : stm32h7xx_hal_ltdc.h
  • __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG : stm32h7xx_hal_ltdc.h
  • __HAL_MDIOS_CLEAR_ERROR_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_DISABLE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_DISABLE_IT : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_ENABLE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_ENABLE_IT : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_GET_ERROR_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_GET_IT_SOURCE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_GET_READ_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_GET_WRITE_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_RESET_HANDLE_STATE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT : stm32h7xx_hal_mdios.h
  • __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG : stm32h7xx_hal_mdios.h
  • __HAL_MDMA_CLEAR_FLAG : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_DISABLE : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_DISABLE_IT : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_ENABLE : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_ENABLE_IT : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_GET_FLAG : stm32h7xx_hal_mdma.h
  • __HAL_MDMA_GET_IT_SOURCE : stm32h7xx_hal_mdma.h
  • __HAL_MMC_CLEAR_FLAG : stm32h7xx_hal_mmc.h
  • __HAL_MMC_CLEAR_IT : stm32h7xx_hal_mmc.h
  • __HAL_MMC_DISABLE_IT : stm32h7xx_hal_mmc.h
  • __HAL_MMC_ENABLE_IT : stm32h7xx_hal_mmc.h
  • __HAL_MMC_GET_FLAG : stm32h7xx_hal_mmc.h
  • __HAL_MMC_GET_IT : stm32h7xx_hal_mmc.h
  • __HAL_NAND_RESET_HANDLE_STATE : stm32h7xx_hal_nand.h
  • __HAL_NOR_RESET_HANDLE_STATE : stm32h7xx_hal_nor.h
  • __HAL_OPAMP_RESET_HANDLE_STATE : stm32h7xx_hal_opamp.h
  • __HAL_PCD_CLEAR_FLAG : stm32h7xx_hal_pcd.h
  • __HAL_PCD_DISABLE : stm32h7xx_hal_pcd.h
  • __HAL_PCD_ENABLE : stm32h7xx_hal_pcd.h
  • __HAL_PCD_GATE_PHYCLOCK : stm32h7xx_hal_pcd.h
  • __HAL_PCD_GET_FLAG : stm32h7xx_hal_pcd.h
  • __HAL_PCD_IS_INVALID_INTERRUPT : stm32h7xx_hal_pcd.h
  • __HAL_PCD_IS_PHY_SUSPENDED : stm32h7xx_hal_pcd.h
  • __HAL_PCD_UNGATE_PHYCLOCK : stm32h7xx_hal_pcd.h
  • __HAL_PWR_AVD_EXTI_CLEAR_FLAG : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_DISABLE_EVENT : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_DISABLE_IT : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_ENABLE_EVENT : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_ENABLE_IT : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_AVD_EXTI_GET_FLAG : stm32h7xx_hal_pwr_ex.h
  • __HAL_PWR_CLEAR_FLAG : stm32h7xx_hal_pwr.h
  • __HAL_PWR_GET_FLAG : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_CLEAR_FLAG : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_EVENT : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_IT : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_EVENT : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_IT : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GENERATE_SWIT : stm32h7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GET_FLAG : stm32h7xx_hal_pwr.h
  • __HAL_PWR_VOLTAGESCALING_CONFIG : stm32h7xx_hal_pwr.h
  • __HAL_QSPI_CLEAR_FLAG : stm32h7xx_hal_qspi.h
  • __HAL_QSPI_DISABLE : stm32h7xx_hal_qspi.h
  • __HAL_QSPI_DISABLE_IT : stm32h7xx_hal_qspi.h
  • __HAL_QSPI_ENABLE : stm32h7xx_hal_qspi.h
  • __HAL_QSPI_ENABLE_IT : stm32h7xx_hal_qspi.h
  • __HAL_QSPI_GET_FLAG : stm32h7xx_hal_qspi.h
  • __HAL_QSPI_GET_IT_SOURCE : stm32h7xx_hal_qspi.h
  • __HAL_QSPI_RESET_HANDLE_STATE : stm32h7xx_hal_qspi.h
  • __HAL_RCC_ADC12_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC12_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC3_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC3_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ADC_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_AHB1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_AHB4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB1H_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB1H_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB1L_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB1L_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_APB4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_FORCE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_RELEASE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BDMA_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_BKPRAM_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CEC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CLEAR_IT : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CLEAR_RESET_FLAGS : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CLKP_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_COMP12_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_COMP12_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CPU_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CPU_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLEAR_FLAG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLEAR_IT : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_DISABLE_IT : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_ENABLE_IT : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_GET_FLAG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_GET_IT_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRS_RELOADVALUE_CALCULATE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_CRYP_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CRYP_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CSI_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CSI_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CSISTOP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_CSISTOP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D3SRAM1_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_D3SRAM1_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DAC12_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DCMI_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_DFSDM1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DISABLE_IT : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DMA2D_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ENABLE_IT : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1MAC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1MAC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1MAC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1MAC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1PTP_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1PTP_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1RX_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1RX_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1TX_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1TX_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_FDCAN_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FDCAN_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_FMC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_ADC_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_CEC_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_CLKP_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_DFSDM1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FDCAN_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FLAG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_FMC_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_HRTIM1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_HSI_DIVIDER : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_I2C1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C2_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C3_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C4_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_IT : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_LPTIM1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPTIM2_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPTIM3_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPTIM4_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPTIM5_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPUART1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_PLL_OSCSOURCE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_QSPI_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_RNG_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_RTC_SOURCE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_SAI1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SAI2_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SAI3_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SAI4A_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SAI4B_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SDMMC_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPDIFRX_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI2_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI3_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI4_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI5_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SPI6_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SWPMI1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SYSCLK_SOURCE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GET_UART4_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART5_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART7_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART8_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART1_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART2_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART3_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART6_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USB_SOURCE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOA_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOB_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOD_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOE_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOF_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOG_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOH_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOI_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOJ_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_GPIOK_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HASH_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HRTIM1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HRTIM1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HRTIM1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_HRTIM1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HRTIM1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSE_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSEM_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSEM_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSEM_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSEM_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI48_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI48_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSI_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSISTOP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_HSISTOP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_I2C4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ITCM_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_ITCM_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDECEN_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDECEN_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDECRST_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_JPGDECRST_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM4_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM4_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM4_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM4_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM4_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM5_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM5_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM5_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM5_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM5_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM5_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPTIM5_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_LPUART1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LPUART1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LSE_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LSEDRIVE_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LSI_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LSI_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_LTDC_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDIOS_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_MDMA_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_OPAMP_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2_VCIRANGE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2_VCORANGE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2CLKOUT_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2CLKOUT_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2FRACN_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2FRACN_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL2FRACN_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3_VCIRANGE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3_VCORANGE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3CLKOUT_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3CLKOUT_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3FRACN_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3FRACN_DISABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL3FRACN_ENABLE : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_PLL_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLSOURCE_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL_VCIRANGE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLL_VCORANGE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLLFRACN_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLLFRACN_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PLLFRACN_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PWR_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_PWR_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_QSPI_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_QSPI_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_QSPI_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_QSPI_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_QSPI_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_QSPI_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_QSPI_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RNG_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CLKPRESCALER : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_RTC_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI4_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI4_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI4_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI4_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI4_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI4_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SAI4A_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI4B_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SDMMC_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPDIFRX_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI5_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SPI6_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_SWPMI1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_SYSCLK_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM12_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM13_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM14_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM15_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM16_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM17_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM5_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM6_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM7_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIM8_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_TIMCLKPRESCALER : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART4_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART5_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART7_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_UART8_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART1_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART2_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART3_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USART6_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB2_OTG_FS_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB2_OTG_FS_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB2_OTG_FS_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB2_OTG_FS_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_USB_CONFIG : stm32h7xx_hal_rcc_ex.h
  • __HAL_RCC_VREF_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_CLKAM_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_CLKAM_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_FORCE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_VREF_RELEASE_RESET : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WAKEUPSTOP_CLK_CONFIG : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_CLK_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_CLK_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE : stm32h7xx_hal_rcc.h
  • __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE : stm32h7xx_hal_rcc.h
  • __HAL_RNG_CLEAR_FLAG : stm32h7xx_hal_rng.h
  • __HAL_RNG_CLEAR_IT : stm32h7xx_hal_rng.h
  • __HAL_RNG_DISABLE : stm32h7xx_hal_rng.h
  • __HAL_RNG_DISABLE_IT : stm32h7xx_hal_rng.h
  • __HAL_RNG_ENABLE : stm32h7xx_hal_rng.h
  • __HAL_RNG_ENABLE_IT : stm32h7xx_hal_rng.h
  • __HAL_RNG_GET_FLAG : stm32h7xx_hal_rng.h
  • __HAL_RNG_GET_IT : stm32h7xx_hal_rng.h
  • __HAL_RNG_RESET_HANDLE_STATE : stm32h7xx_hal_rng.h
  • __HAL_RTC_ALARM_CLEAR_FLAG : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_DISABLE_IT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_ENABLE_IT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_CLEAR_FLAG : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_EVENT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_IT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_EVENT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_IT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GENERATE_SWIT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GET_FLAG : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_FLAG : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT_SOURCE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARMA_DISABLE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARMA_ENABLE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARMB_DISABLE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_ALARMB_ENABLE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_CALIBRATION_OUTPUT_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_CALIBRATION_OUTPUT_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_RESET_HANDLE_STATE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_SHIFT_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_DISABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_ENABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT_SOURCE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT_SOURCE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTID3_CLEAR_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTID3_DISABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTID3_ENABLE_EVENT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTID3_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_FLAG : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE : stm32h7xx_hal_rtc_ex.h
  • __HAL_RTC_WRITEPROTECTION_DISABLE : stm32h7xx_hal_rtc.h
  • __HAL_RTC_WRITEPROTECTION_ENABLE : stm32h7xx_hal_rtc.h
  • __HAL_SAI_CLEAR_FLAG : stm32h7xx_hal_sai.h
  • __HAL_SAI_DISABLE : stm32h7xx_hal_sai.h
  • __HAL_SAI_DISABLE_IT : stm32h7xx_hal_sai.h
  • __HAL_SAI_ENABLE : stm32h7xx_hal_sai.h
  • __HAL_SAI_ENABLE_IT : stm32h7xx_hal_sai.h
  • __HAL_SAI_GET_FLAG : stm32h7xx_hal_sai.h
  • __HAL_SAI_GET_IT_SOURCE : stm32h7xx_hal_sai.h
  • __HAL_SAI_RESET_HANDLE_STATE : stm32h7xx_hal_sai.h
  • __HAL_SD_CLEAR_FLAG : stm32h7xx_hal_sd.h
  • __HAL_SD_CLEAR_IT : stm32h7xx_hal_sd.h
  • __HAL_SD_DISABLE_IT : stm32h7xx_hal_sd.h
  • __HAL_SD_ENABLE_IT : stm32h7xx_hal_sd.h
  • __HAL_SD_GET_FLAG : stm32h7xx_hal_sd.h
  • __HAL_SD_GET_IT : stm32h7xx_hal_sd.h
  • __HAL_SDRAM_RESET_HANDLE_STATE : stm32h7xx_hal_sdram.h
  • __HAL_SMARTCARD_CLEAR_FEFLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_FLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IDLEFLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IT : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_NEFLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_OREFLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_PEFLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_TXFECF : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE_IT : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE_IT : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_FLUSH_DRREGISTER : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_FLAG : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT_SOURCE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_RESET_HANDLE_STATE : stm32h7xx_hal_smartcard.h
  • __HAL_SMARTCARD_SEND_REQ : stm32h7xx_hal_smartcard.h
  • __HAL_SMBUS_CLEAR_FLAG : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE_IT : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE_IT : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_GENERATE_NACK : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_GET_FLAG : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_GET_IT_SOURCE : stm32h7xx_hal_smbus.h
  • __HAL_SMBUS_RESET_HANDLE_STATE : stm32h7xx_hal_smbus.h
  • __HAL_SPDIFRX_CLEAR_IT : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_DISABLE_IT : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_ENABLE_IT : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_GET_FLAG : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_GET_IT_SOURCE : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_IDLE : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_RCV : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_RESET_HANDLE_STATE : stm32h7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_SYNC : stm32h7xx_hal_spdifrx.h
  • __HAL_SPI_CLEAR_CRCERRFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_EOTFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_FREFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_MODFFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_OVRFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_TXTFFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_CLEAR_UDRFLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_DISABLE : stm32h7xx_hal_spi.h
  • __HAL_SPI_DISABLE_IT : stm32h7xx_hal_spi.h
  • __HAL_SPI_ENABLE : stm32h7xx_hal_spi.h
  • __HAL_SPI_ENABLE_IT : stm32h7xx_hal_spi.h
  • __HAL_SPI_GET_FLAG : stm32h7xx_hal_spi.h
  • __HAL_SPI_GET_IT_SOURCE : stm32h7xx_hal_spi.h
  • __HAL_SPI_RESET_HANDLE_STATE : stm32h7xx_hal_spi.h
  • __HAL_SRAM_RESET_HANDLE_STATE : stm32h7xx_hal_sram.h
  • __HAL_SWPMI_CLEAR_FLAG : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_DISABLE : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_DISABLE_IT : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_ENABLE : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_ENABLE_IT : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_GET_FLAG : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_GET_IT : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_GET_IT_SOURCE : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_RESET_HANDLE_STATE : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_TRANSCEIVER_DISABLE : stm32h7xx_hal_swpmi.h
  • __HAL_SWPMI_TRANSCEIVER_ENABLE : stm32h7xx_hal_swpmi.h
  • __HAL_TIM_CLEAR_FLAG : stm32h7xx_hal_tim.h
  • __HAL_TIM_CLEAR_IT : stm32h7xx_hal_tim.h
  • __HAL_TIM_DISABLE : stm32h7xx_hal_tim.h
  • __HAL_TIM_DISABLE_DMA : stm32h7xx_hal_tim.h
  • __HAL_TIM_DISABLE_IT : stm32h7xx_hal_tim.h
  • __HAL_TIM_ENABLE : stm32h7xx_hal_tim.h
  • __HAL_TIM_ENABLE_DMA : stm32h7xx_hal_tim.h
  • __HAL_TIM_ENABLE_IT : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_AUTORELOAD : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_CLOCKDIVISION : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_COMPARE : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_COUNTER : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_FLAG : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_ICPRESCALER : stm32h7xx_hal_tim.h
  • __HAL_TIM_GET_IT_SOURCE : stm32h7xx_hal_tim.h
  • __HAL_TIM_IS_TIM_COUNTING_DOWN : stm32h7xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE : stm32h7xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY : stm32h7xx_hal_tim.h
  • __HAL_TIM_MOE_ENABLE : stm32h7xx_hal_tim.h
  • __HAL_TIM_RESET_HANDLE_STATE : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_AUTORELOAD : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_CAPTUREPOLARITY : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_CLOCKDIVISION : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_COMPARE : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_COUNTER : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_ICPRESCALER : stm32h7xx_hal_tim.h
  • __HAL_TIM_SET_PRESCALER : stm32h7xx_hal_tim.h
  • __HAL_TIM_URS_DISABLE : stm32h7xx_hal_tim.h
  • __HAL_TIM_URS_ENABLE : stm32h7xx_hal_tim.h
  • __HAL_UART_CLEAR_FEFLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_FLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_IDLEFLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_IT : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_NEFLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_OREFLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_PEFLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_CLEAR_TXFECF : stm32h7xx_hal_uart.h
  • __HAL_UART_DISABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_DISABLE_IT : stm32h7xx_hal_uart.h
  • __HAL_UART_ENABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_ENABLE_IT : stm32h7xx_hal_uart.h
  • __HAL_UART_FLUSH_DRREGISTER : stm32h7xx_hal_uart.h
  • __HAL_UART_GET_FLAG : stm32h7xx_hal_uart.h
  • __HAL_UART_GET_IT : stm32h7xx_hal_uart.h
  • __HAL_UART_GET_IT_SOURCE : stm32h7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_DISABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_ENABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_DISABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_ENABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_uart.h
  • __HAL_UART_RESET_HANDLE_STATE : stm32h7xx_hal_uart.h
  • __HAL_UART_SEND_REQ : stm32h7xx_hal_uart.h
  • __HAL_USART_CLEAR_FEFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_FLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_IDLEFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_IT : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_NEFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_OREFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_PEFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_TXFECF : stm32h7xx_hal_usart.h
  • __HAL_USART_CLEAR_UDRFLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_DISABLE : stm32h7xx_hal_usart.h
  • __HAL_USART_DISABLE_IT : stm32h7xx_hal_usart.h
  • __HAL_USART_ENABLE : stm32h7xx_hal_usart.h
  • __HAL_USART_ENABLE_IT : stm32h7xx_hal_usart.h
  • __HAL_USART_GET_FLAG : stm32h7xx_hal_usart.h
  • __HAL_USART_GET_IT : stm32h7xx_hal_usart.h
  • __HAL_USART_GET_IT_SOURCE : stm32h7xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_usart.h
  • __HAL_USART_RESET_HANDLE_STATE : stm32h7xx_hal_usart.h
  • __HAL_USART_SEND_REQ : stm32h7xx_hal_usart.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT : stm32h7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG : stm32h7xx_hal_pcd.h
  • __HAL_WWDG_CLEAR_FLAG : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_CLEAR_IT : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE_IT : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_GET_FLAG : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT : stm32h7xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT_SOURCE : stm32h7xx_hal_wwdg.h
  • __MCO1_CLK_ENABLE : stm32h7xx_hal_rcc.c
  • __MCO2_CLK_ENABLE : stm32h7xx_hal_rcc.c
  • __STM32H7xx_HAL_VERSION : stm32h7xx_hal.c
  • __STM32H7xx_HAL_VERSION_MAIN : stm32h7xx_hal.c
  • __STM32H7xx_HAL_VERSION_RC : stm32h7xx_hal.c
  • __STM32H7xx_HAL_VERSION_SUB1 : stm32h7xx_hal.c
  • __STM32H7xx_HAL_VERSION_SUB2 : stm32h7xx_hal.c
  • __STM3H7xx_HAL_USART_H : stm32h7xx_hal_usart.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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- a -

  • ADC12_COMMON_REGISTER : stm32h7xx_hal_adc_ex.h
  • ADC12_NONMULTIMODE_OR_MULTIMODEMASTER : stm32h7xx_hal_adc_ex.h
  • ADC3_COMMON_REGISTER : stm32h7xx_hal_adc_ex.h
  • ADC3_NONMULTIMODE_OR_MULTIMODEMASTER : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_1 : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_2 : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_3 : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_ALL_INJEC : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_ALL_REG : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_ALL_REGINJEC : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_NONE : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_SINGLE_INJEC : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_SINGLE_REG : stm32h7xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_SINGLE_REGINJEC : stm32h7xx_hal_adc_ex.h
  • ADC_ANY_OTHER_ENABLED : stm32h7xx_hal_adc_ex.h
  • ADC_AWD1_EVENT : stm32h7xx_hal_adc_ex.h
  • ADC_AWD1THRESHOLD_SHIFT_RESOLUTION : stm32h7xx_hal_adc_ex.h
  • ADC_AWD23THRESHOLD_SHIFT_RESOLUTION : stm32h7xx_hal_adc_ex.h
  • ADC_AWD2_EVENT : stm32h7xx_hal_adc_ex.h
  • ADC_AWD3_EVENT : stm32h7xx_hal_adc_ex.h
  • ADC_AWD_EVENT : stm32h7xx_hal_adc_ex.h
  • ADC_CALFACT_DIFF_GET : stm32h7xx_hal_adc_ex.h
  • ADC_CALFACT_DIFF_SET : stm32h7xx_hal_adc_ex.h
  • ADC_CALIB_OFFSET : stm32h7xx_hal_adc_ex.h
  • ADC_CALIB_OFFSET_LINEARITY : stm32h7xx_hal_adc_ex.h
  • ADC_CALIBRATION_TIMEOUT : stm32h7xx_hal_adc_ex.c
  • ADC_CCR_MULTI_DMACONTREQ : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR2_FIELDS : stm32h7xx_hal_adc.c
  • ADC_CFGR2_INJ_FIELDS : stm32h7xx_hal_adc_ex.c
  • ADC_CFGR_AUTOWAIT : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_CONTINUOUS : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_DISCONTINUOUS_NUM : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_DMACONTREQ : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_FIELDS_1 : stm32h7xx_hal_adc.c
  • ADC_CFGR_FIELDS_2 : stm32h7xx_hal_adc.c
  • ADC_CFGR_INJECT_CONTEXT_QUEUE : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_INJECT_DISCCONTINUOUS : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_REG_DISCONTINUOUS : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_SET_AWD1CH : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_SET_AWD23CR : stm32h7xx_hal_adc_ex.h
  • ADC_CFGR_WD_FIELDS : stm32h7xx_hal_adc.c
  • ADC_CHANNEL_0 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_1 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_10 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_11 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_12 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_13 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_14 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_15 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_16 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_17 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_18 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_19 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_2 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_3 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_4 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_5 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_6 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_7 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_8 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_9 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_DAC1CH1_ADC2 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_DAC1CH2_ADC2 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_TEMPSENSOR : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_VBAT_DIV4 : stm32h7xx_hal_adc.h
  • ADC_CHANNEL_VREFINT : stm32h7xx_hal_adc.h
  • ADC_CLEAR_ERRORCODE : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV1 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV10 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV12 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV128 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV16 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV2 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV256 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV32 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV4 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV6 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV64 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV8 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV1 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV2 : stm32h7xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV4 : stm32h7xx_hal_adc.h
  • ADC_CLOCKPRESCALER_PCLK_DIV1 : stm32h7xx_hal_adc.h
  • ADC_CLOCKPRESCALER_PCLK_DIV2 : stm32h7xx_hal_adc.h
  • ADC_CLOCKPRESCALER_PCLK_DIV4 : stm32h7xx_hal_adc.h
  • ADC_CONVERSION_TIME_MAX_CPU_CYCLES : stm32h7xx_hal_adc.c
  • ADC_CONVERSIONDATA_DFSDM : stm32h7xx_hal_adc.h
  • ADC_CONVERSIONDATA_DMA_CIRCULAR : stm32h7xx_hal_adc.h
  • ADC_CONVERSIONDATA_DMA_ONESHOT : stm32h7xx_hal_adc.h
  • ADC_CONVERSIONDATA_DR : stm32h7xx_hal_adc.h
  • ADC_DIFFERENTIAL_ENDED : stm32h7xx_hal_adc_ex.h
  • ADC_DIFSEL_CHANNEL : stm32h7xx_hal_adc_ex.h
  • ADC_DISABLE : stm32h7xx_hal_adc_ex.h
  • ADC_DISABLE_TIMEOUT : stm32h7xx_hal_adc.c
  • ADC_DISABLING_CONDITIONS : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_ALTERTRIG : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_INJECSIMULT : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_INTERL : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGINTERL_INJECSIMULT : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_ALTERTRIG : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_INJECSIMULT : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODEDATAFORMAT_32_10_BITS : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODEDATAFORMAT_8_BITS : stm32h7xx_hal_adc_ex.h
  • ADC_DUALMODEDATAFORMAT_DISABLED : stm32h7xx_hal_adc_ex.h
  • ADC_ENABLE : stm32h7xx_hal_adc_ex.h
  • ADC_ENABLE_TIMEOUT : stm32h7xx_hal_adc.c
  • ADC_ENABLING_CONDITIONS : stm32h7xx_hal_adc_ex.h
  • ADC_EOC_SEQ_CONV : stm32h7xx_hal_adc.h
  • ADC_EOC_SINGLE_CONV : stm32h7xx_hal_adc.h
  • ADC_EOSMP_EVENT : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIG_EXT_IT11 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_HR1_ADCTRG1 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_HR1_ADCTRG3 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_LPTIM1_OUT : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_LPTIM2_OUT : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_LPTIM3_OUT : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T15_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC1 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC2 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC3 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO2 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_CC2 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T3_CC4 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T3_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T4_CC4 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T4_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T6_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T8_TRGO : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIG_T8_TRGO2 : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_FALLING : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_NONE : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISING : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING : stm32h7xx_hal_adc.h
  • ADC_EXTERNALTRIGINJEC_EXT_IT15 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_LPTIM1_OUT : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_LPTIM2_OUT : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_LPTIM3_OUT : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T15_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_CC4 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_TRGO2 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_CC1 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC1 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC3 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC4 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T4_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T6_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_CC4 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_TRGO : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_TRGO2 : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_NONE : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISING : stm32h7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_ALL : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_AWD : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_AWD1 : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_AWD2 : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_AWD3 : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_EOC : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_EOS : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_EOSMP : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_JEOC : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_JEOS : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_JQOVF : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_OVR : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_POSTCONV_ALL : stm32h7xx_hal_adc_ex.h
  • ADC_FLAG_RDY : stm32h7xx_hal_adc_ex.h
  • ADC_GET_RESOLUTION : stm32h7xx_hal_adc.h
  • ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE : stm32h7xx_hal_adc_ex.h
  • ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_GROUP : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_1 : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_2 : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_3 : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_4 : stm32h7xx_hal_adc_ex.h
  • ADC_INJECTED_SOFTWARE_START : stm32h7xx_hal_adc_ex.h
  • ADC_INSTANCE_IS_ENABLED : stm32h7xx_hal_adc_ex.h
  • ADC_IS_CONVERSION_ONGOING_INJECTED : stm32h7xx_hal_adc_ex.h
  • ADC_IS_CONVERSION_ONGOING_REGULAR : stm32h7xx_hal_adc.h
  • ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED : stm32h7xx_hal_adc_ex.h
  • ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE : stm32h7xx_hal_adc_ex.h
  • ADC_IS_ENABLE : stm32h7xx_hal_adc.h
  • ADC_IS_INDEPENDENT : stm32h7xx_hal_adc_ex.h
  • ADC_IS_SOFTWARE_START_INJECTED : stm32h7xx_hal_adc_ex.h
  • ADC_IS_SOFTWARE_START_REGULAR : stm32h7xx_hal_adc.h
  • ADC_IT_AWD : stm32h7xx_hal_adc_ex.h
  • ADC_IT_AWD1 : stm32h7xx_hal_adc_ex.h
  • ADC_IT_AWD2 : stm32h7xx_hal_adc_ex.h
  • ADC_IT_AWD3 : stm32h7xx_hal_adc_ex.h
  • ADC_IT_EOC : stm32h7xx_hal_adc_ex.h
  • ADC_IT_EOS : stm32h7xx_hal_adc_ex.h
  • ADC_IT_EOSMP : stm32h7xx_hal_adc_ex.h
  • ADC_IT_JEOC : stm32h7xx_hal_adc_ex.h
  • ADC_IT_JEOS : stm32h7xx_hal_adc_ex.h
  • ADC_IT_JQOVF : stm32h7xx_hal_adc_ex.h
  • ADC_IT_OVR : stm32h7xx_hal_adc_ex.h
  • ADC_IT_RDY : stm32h7xx_hal_adc_ex.h
  • ADC_JQOVF_EVENT : stm32h7xx_hal_adc_ex.h
  • ADC_JSQR_FIELDS : stm32h7xx_hal_adc_ex.c
  • ADC_JSQR_RK : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_1 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_10 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_11 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_12 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_13 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_14 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_15 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_2 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_3 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_4 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_5 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_6 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_7 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_8 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_9 : stm32h7xx_hal_adc_ex.h
  • ADC_LEFTBITSHIFT_NONE : stm32h7xx_hal_adc_ex.h
  • ADC_MASTER_REGISTER : stm32h7xx_hal_adc_ex.h
  • ADC_MODE_INDEPENDENT : stm32h7xx_hal_adc_ex.h
  • ADC_MULTI_SLAVE : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_1 : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_2 : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_3 : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_4 : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_NONE : stm32h7xx_hal_adc_ex.h
  • ADC_OFFSET_SHIFT_RESOLUTION : stm32h7xx_hal_adc_ex.h
  • ADC_OFR_CHANNEL : stm32h7xx_hal_adc_ex.h
  • ADC_OFR_FIELDS : stm32h7xx_hal_adc.c
  • ADC_OVR_DATA_OVERWRITTEN : stm32h7xx_hal_adc.h
  • ADC_OVR_DATA_PRESERVED : stm32h7xx_hal_adc.h
  • ADC_OVR_EVENT : stm32h7xx_hal_adc_ex.h
  • ADC_REGOVERSAMPLING_CONTINUED_MODE : stm32h7xx_hal_adc_ex.h
  • ADC_REGOVERSAMPLING_RESUMED_MODE : stm32h7xx_hal_adc_ex.h
  • ADC_REGULAR_GROUP : stm32h7xx_hal_adc_ex.h
  • ADC_REGULAR_INJECTED_GROUP : stm32h7xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_1 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_10 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_11 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_12 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_13 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_14 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_15 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_16 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_2 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_3 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_4 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_5 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_6 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_7 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_8 : stm32h7xx_hal_adc.h
  • ADC_REGULAR_RANK_9 : stm32h7xx_hal_adc.h
  • ADC_RESOLUTION_10B : stm32h7xx_hal_adc.h
  • ADC_RESOLUTION_12B : stm32h7xx_hal_adc.h
  • ADC_RESOLUTION_14B : stm32h7xx_hal_adc.h
  • ADC_RESOLUTION_16B : stm32h7xx_hal_adc.h
  • ADC_RESOLUTION_8B : stm32h7xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_1 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_10 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_11 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_2 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_3 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_4 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_5 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_6 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_7 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_8 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_9 : stm32h7xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_NONE : stm32h7xx_hal_adc_ex.h
  • ADC_SAMPLETIME_16CYCLES_5 : stm32h7xx_hal_adc_ex.h
  • ADC_SAMPLETIME_1CYCLE_5 : stm32h7xx_hal_adc_ex.h
  • ADC_SAMPLETIME_2CYCLES_5 : stm32h7xx_hal_adc_ex.h
  • ADC_SAMPLETIME_32CYCLES_5 : stm32h7xx_hal_adc_ex.h
  • ADC_SAMPLETIME_387CYCLES_5 : stm32h7xx_hal_adc_ex.h
  • ADC_SAMPLETIME_64CYCLES_5 : stm32h7xx_hal_adc_ex.h
  • ADC_SAMPLETIME_810CYCLES_5 : stm32h7xx_hal_adc_ex.h
  • ADC_SAMPLETIME_8CYCLES_5 : stm32h7xx_hal_adc_ex.h
  • ADC_SCAN_DISABLE : stm32h7xx_hal_adc.h
  • ADC_SCAN_ENABLE : stm32h7xx_hal_adc.h
  • ADC_SINGLE_ENDED : stm32h7xx_hal_adc_ex.h
  • ADC_SMPR1 : stm32h7xx_hal_adc_ex.h
  • ADC_SMPR2 : stm32h7xx_hal_adc_ex.h
  • ADC_SOFTWARE_START : stm32h7xx_hal_adc.h
  • ADC_SQR1_RK : stm32h7xx_hal_adc_ex.h
  • ADC_SQR2_RK : stm32h7xx_hal_adc_ex.h
  • ADC_SQR3_RK : stm32h7xx_hal_adc_ex.h
  • ADC_SQR4_RK : stm32h7xx_hal_adc_ex.h
  • ADC_STAB_DELAY_US : stm32h7xx_hal_adc.h
  • ADC_STATE_CLR_SET : stm32h7xx_hal_adc.h
  • ADC_STOP_CONVERSION_TIMEOUT : stm32h7xx_hal_adc.h
  • ADC_TEMPSENSOR_DELAY_US : stm32h7xx_hal_adc.h
  • ADC_TRIGGEREDMODE_MULTI_TRIGGER : stm32h7xx_hal_adc_ex.h
  • ADC_TRIGGEREDMODE_SINGLE_TRIGGER : stm32h7xx_hal_adc_ex.h
  • ADC_TRX_HIGHTHRESHOLD : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_1CYCLE : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_2CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_3CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_4CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_5CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_6CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_7CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_8CYCLES : stm32h7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_9CYCLES : stm32h7xx_hal_adc_ex.h
  • ADDR_1ST_CYCLE : stm32h7xx_hal_nand.h
  • ADDR_2ND_CYCLE : stm32h7xx_hal_nand.h
  • ADDR_3RD_CYCLE : stm32h7xx_hal_nand.h
  • ADDR_4TH_CYCLE : stm32h7xx_hal_nand.h
  • ADDR_AREA : stm32h7xx_hal_nand.h
  • ANALOG_MODE : stm32h7xx_hal_gpio.c
  • ARRAY_ADDRESS : stm32h7xx_hal_nand.h
  • assert_param : stm32h7xx_hal_conf.h
  • AVD_FALLING_EDGE : stm32h7xx_hal_pwr_ex.c
  • AVD_MODE_EVT : stm32h7xx_hal_pwr_ex.c
  • AVD_MODE_IT : stm32h7xx_hal_pwr_ex.c
  • AVD_RISING_EDGE : stm32h7xx_hal_pwr_ex.c
  • AVD_RISING_FALLING_EDGE : stm32h7xx_hal_pwr_ex.c
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
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  • Variables
  • Typedefs
  • Enumerations
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- b -

  • BDMA_CH6_CLEAR : stm32h7xx_hal.h
  • BDMA_CH7_CLEAR : stm32h7xx_hal.h
  • BDMA_FLAG_GL0 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL1 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL2 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL3 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL4 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL5 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL6 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_GL7 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT0 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT1 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT2 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT3 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT4 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT5 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT6 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_HT7 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC0 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC1 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC2 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC3 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC4 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC5 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC6 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TC7 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE0 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE1 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE2 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE3 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE4 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE5 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE6 : stm32h7xx_hal_dma.h
  • BDMA_FLAG_TE7 : stm32h7xx_hal_dma.h
  • BDMA_MEMORY_TO_MEMORY : stm32h7xx_hal_dma.c
  • BDMA_MEMORY_TO_PERIPH : stm32h7xx_hal_dma.c
  • BDMA_PERIPH_TO_MEMORY : stm32h7xx_hal_dma.c
  • BDMA_REQUEST_ADC3 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR0 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR1 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR2 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR3 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR4 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR5 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR6 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_GENERATOR7 : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_I2C4_RX : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_I2C4_TX : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_LP_UART1_RX : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_LP_UART1_TX : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_MEM2MEM : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_SAI4_A : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_SAI4_B : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_SPI6_RX : stm32h7xx_hal_dma.h
  • BDMA_REQUEST_SPI6_TX : stm32h7xx_hal_dma.h
  • BDTR_BK2F_SHIFT : stm32h7xx_hal_tim_ex.c
  • BDTR_BKF_SHIFT : stm32h7xx_hal_tim_ex.c
  • BLOCKSIZE : stm32h7xx_hal_sd.h , stm32h7xx_hal_mmc.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
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  • g
  • h
  • i
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- c -

  • CARD_HIGH_SPEED : stm32h7xx_hal_sd.h
  • CARD_NORMAL_SPEED : stm32h7xx_hal_sd.h
  • CARD_SDHC_SDXC : stm32h7xx_hal_sd.h
  • CARD_SDSC : stm32h7xx_hal_sd.h
  • CARD_SECURED : stm32h7xx_hal_sd.h
  • CARD_ULTRA_HIGH_SPEED : stm32h7xx_hal_sd.h
  • CARD_V1_X : stm32h7xx_hal_sd.h
  • CARD_V2_X : stm32h7xx_hal_sd.h
  • CCU_IR_MASK : stm32h7xx_hal_fdcan.h
  • CEC_0_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_1_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_2_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_3_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_4_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_5_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_6_5_BITPERIOD_SFT : stm32h7xx_hal_cec.h
  • CEC_BRE_ERRORBIT_GENERATION : stm32h7xx_hal_cec.h
  • CEC_BRE_ERRORBIT_NO_GENERATION : stm32h7xx_hal_cec.h
  • CEC_BROADCASTERROR_ERRORBIT_GENERATION : stm32h7xx_hal_cec.h
  • CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION : stm32h7xx_hal_cec.h
  • CEC_CFGR_OAR_LSB_POS : stm32h7xx_hal_cec.h
  • CEC_DEFAULT_SFT : stm32h7xx_hal_cec.h
  • CEC_EXTENDED_TOLERANCE : stm32h7xx_hal_cec.h
  • CEC_FLAG_ARBLST : stm32h7xx_hal_cec.h
  • CEC_FLAG_BRE : stm32h7xx_hal_cec.h
  • CEC_FLAG_LBPE : stm32h7xx_hal_cec.h
  • CEC_FLAG_RXACKE : stm32h7xx_hal_cec.h
  • CEC_FLAG_RXBR : stm32h7xx_hal_cec.h
  • CEC_FLAG_RXEND : stm32h7xx_hal_cec.h
  • CEC_FLAG_RXOVR : stm32h7xx_hal_cec.h
  • CEC_FLAG_SBPE : stm32h7xx_hal_cec.h
  • CEC_FLAG_TXACKE : stm32h7xx_hal_cec.h
  • CEC_FLAG_TXBR : stm32h7xx_hal_cec.h
  • CEC_FLAG_TXEND : stm32h7xx_hal_cec.h
  • CEC_FLAG_TXERR : stm32h7xx_hal_cec.h
  • CEC_FLAG_TXUDR : stm32h7xx_hal_cec.h
  • CEC_FULL_LISTENING_MODE : stm32h7xx_hal_cec.h
  • CEC_IER_RX_ALL_ERR : stm32h7xx_hal_cec.h
  • CEC_IER_TX_ALL_ERR : stm32h7xx_hal_cec.h
  • CEC_INITIATOR_LSB_POS : stm32h7xx_hal_cec.h
  • CEC_ISR_ALL_ERROR : stm32h7xx_hal_cec.h
  • CEC_IT_ARBLST : stm32h7xx_hal_cec.h
  • CEC_IT_BRE : stm32h7xx_hal_cec.h
  • CEC_IT_LBPE : stm32h7xx_hal_cec.h
  • CEC_IT_RXACKE : stm32h7xx_hal_cec.h
  • CEC_IT_RXBR : stm32h7xx_hal_cec.h
  • CEC_IT_RXEND : stm32h7xx_hal_cec.h
  • CEC_IT_RXOVR : stm32h7xx_hal_cec.h
  • CEC_IT_SBPE : stm32h7xx_hal_cec.h
  • CEC_IT_TXACKE : stm32h7xx_hal_cec.h
  • CEC_IT_TXBR : stm32h7xx_hal_cec.h
  • CEC_IT_TXEND : stm32h7xx_hal_cec.h
  • CEC_IT_TXERR : stm32h7xx_hal_cec.h
  • CEC_IT_TXUDR : stm32h7xx_hal_cec.h
  • CEC_LBPE_ERRORBIT_GENERATION : stm32h7xx_hal_cec.h
  • CEC_LBPE_ERRORBIT_NO_GENERATION : stm32h7xx_hal_cec.h
  • CEC_NO_RX_STOP_ON_BRE : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_0 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_1 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_10 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_11 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_12 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_13 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_14 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_2 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_3 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_4 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_5 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_6 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_7 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_8 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_9 : stm32h7xx_hal_cec.h
  • CEC_OWN_ADDRESS_NONE : stm32h7xx_hal_cec.h
  • CEC_REDUCED_LISTENING_MODE : stm32h7xx_hal_cec.h
  • CEC_RX_STOP_ON_BRE : stm32h7xx_hal_cec.h
  • CEC_SFT_START_ON_TX_RX_END : stm32h7xx_hal_cec.h
  • CEC_SFT_START_ON_TXSOM : stm32h7xx_hal_cec.h
  • CEC_STANDARD_TOLERANCE : stm32h7xx_hal_cec.h
  • CFI1_ADDRESS : stm32h7xx_hal_nor.h
  • CFI2_ADDRESS : stm32h7xx_hal_nor.h
  • CFI3_ADDRESS : stm32h7xx_hal_nor.h
  • CFI4_ADDRESS : stm32h7xx_hal_nor.h
  • CLOCKSWITCH_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • CM7_CPUID : stm32h7xx_hal_cortex.h
  • CMD_AREA : stm32h7xx_hal_nand.h
  • COLUMN_1ST_CYCLE : stm32h7xx_hal_nand.h
  • COLUMN_2ND_CYCLE : stm32h7xx_hal_nand.h
  • COLUMN_ADDRESS : stm32h7xx_hal_nand.h
  • COMP_BLANKINGSRC_NONE : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM15_OC1 : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5 : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM2_OC3 : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC3 : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC4 : stm32h7xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM8_OC5 : stm32h7xx_hal_comp.h
  • COMP_CLEAR_C1IF : stm32h7xx_hal_comp.h
  • COMP_CLEAR_C2IF : stm32h7xx_hal_comp.h
  • COMP_DELAY_STARTUP_US : stm32h7xx_hal_comp.c
  • COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32h7xx_hal_comp.c
  • COMP_EXTI_EVENT : stm32h7xx_hal_comp.h
  • COMP_EXTI_FALLING : stm32h7xx_hal_comp.h
  • COMP_EXTI_IT : stm32h7xx_hal_comp.h
  • COMP_EXTI_LINE_COMP1 : stm32h7xx_hal_comp.h
  • COMP_EXTI_LINE_COMP2 : stm32h7xx_hal_comp.h
  • COMP_EXTI_RISING : stm32h7xx_hal_comp.h
  • COMP_FLAG_C1I : stm32h7xx_hal_comp.h
  • COMP_FLAG_C2I : stm32h7xx_hal_comp.h
  • COMP_FLAG_LOCK : stm32h7xx_hal_comp.h
  • COMP_GET_EXTI_LINE : stm32h7xx_hal_comp.h
  • COMP_HYSTERESIS_HIGH : stm32h7xx_hal_comp.h
  • COMP_HYSTERESIS_LOW : stm32h7xx_hal_comp.h
  • COMP_HYSTERESIS_MEDIUM : stm32h7xx_hal_comp.h
  • COMP_HYSTERESIS_NONE : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_1_2VREFINT : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_1_4VREFINT : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_3_4VREFINT : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC1_CH1 : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC1_CH2 : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_IO1 : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_IO2 : stm32h7xx_hal_comp.h
  • COMP_INPUT_MINUS_VREFINT : stm32h7xx_hal_comp.h
  • COMP_INPUT_PLUS_IO1 : stm32h7xx_hal_comp.h
  • COMP_INPUT_PLUS_IO2 : stm32h7xx_hal_comp.h
  • COMP_IT_EN : stm32h7xx_hal_comp.h
  • COMP_OUTPUT_LEVEL_HIGH : stm32h7xx_hal_comp.h
  • COMP_OUTPUT_LEVEL_LOW : stm32h7xx_hal_comp.h
  • COMP_OUTPUTPOL_INVERTED : stm32h7xx_hal_comp.h
  • COMP_OUTPUTPOL_NONINVERTED : stm32h7xx_hal_comp.h
  • COMP_POWERMODE_HIGHSPEED : stm32h7xx_hal_comp.h
  • COMP_POWERMODE_MEDIUMSPEED : stm32h7xx_hal_comp.h
  • COMP_POWERMODE_ULTRALOWPOWER : stm32h7xx_hal_comp.h
  • COMP_STATE_BITFIELD_LOCK : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_FALLING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING_FALLING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_FALLING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING_FALLING : stm32h7xx_hal_comp.h
  • COMP_TRIGGERMODE_NONE : stm32h7xx_hal_comp.h
  • COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON : stm32h7xx_hal_comp.h
  • COMP_WINDOWMODE_DISABLE : stm32h7xx_hal_comp.h
  • CR_PSIZE_MASK : stm32h7xx_hal_flash.h
  • CRC_INPUTDATA_FORMAT_BYTES : stm32h7xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_HALFWORDS : stm32h7xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_UNDEFINED : stm32h7xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_WORDS : stm32h7xx_hal_crc.h
  • CRC_INPUTDATA_INVERSION_BYTE : stm32h7xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_HALFWORD : stm32h7xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_NONE : stm32h7xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_WORD : stm32h7xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_DISABLE : stm32h7xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_ENABLE : stm32h7xx_hal_crc_ex.h
  • CRC_POLYLENGTH_16B : stm32h7xx_hal_crc.h
  • CRC_POLYLENGTH_32B : stm32h7xx_hal_crc.h
  • CRC_POLYLENGTH_7B : stm32h7xx_hal_crc.h
  • CRC_POLYLENGTH_8B : stm32h7xx_hal_crc.h
  • CRYP_AES_CBC : stm32h7xx_hal_cryp.h
  • CRYP_AES_CCM : stm32h7xx_hal_cryp.h
  • CRYP_AES_CTR : stm32h7xx_hal_cryp.h
  • CRYP_AES_ECB : stm32h7xx_hal_cryp.h
  • CRYP_AES_GCM : stm32h7xx_hal_cryp.h
  • CRYP_CCM_CTR0_0 : stm32h7xx_hal_cryp_ex.c
  • CRYP_CCM_CTR0_3 : stm32h7xx_hal_cryp_ex.c
  • CRYP_CCM_CTR1_0 : stm32h7xx_hal_cryp.c
  • CRYP_CCM_CTR1_1 : stm32h7xx_hal_cryp.c
  • CRYP_CCM_CTR1_2 : stm32h7xx_hal_cryp.c
  • CRYP_DATATYPE_16B : stm32h7xx_hal_cryp.h
  • CRYP_DATATYPE_1B : stm32h7xx_hal_cryp.h
  • CRYP_DATATYPE_32B : stm32h7xx_hal_cryp.h
  • CRYP_DATATYPE_8B : stm32h7xx_hal_cryp.h
  • CRYP_DES_CBC : stm32h7xx_hal_cryp.h
  • CRYP_DES_ECB : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_BUSY : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_IFEM : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_IFNF : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_INRIS : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_MASK : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_OFFU : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_OFNE : stm32h7xx_hal_cryp.h
  • CRYP_FLAG_OUTRIS : stm32h7xx_hal_cryp.h
  • CRYP_IT_INI : stm32h7xx_hal_cryp.h
  • CRYP_IT_OUTI : stm32h7xx_hal_cryp.h
  • CRYP_KEYSIZE_128B : stm32h7xx_hal_cryp.h
  • CRYP_KEYSIZE_192B : stm32h7xx_hal_cryp.h
  • CRYP_KEYSIZE_256B : stm32h7xx_hal_cryp.h
  • CRYP_OPERATINGMODE_DECRYPT : stm32h7xx_hal_cryp_ex.c , stm32h7xx_hal_cryp.c
  • CRYP_OPERATINGMODE_ENCRYPT : stm32h7xx_hal_cryp.c , stm32h7xx_hal_cryp_ex.c
  • CRYP_PHASE_FINAL : stm32h7xx_hal_cryp.c , stm32h7xx_hal_cryp_ex.c
  • CRYP_PHASE_HEADER : stm32h7xx_hal_cryp_ex.c , stm32h7xx_hal_cryp.c
  • CRYP_PHASE_INIT : stm32h7xx_hal_cryp_ex.c , stm32h7xx_hal_cryp.c
  • CRYP_PHASE_PAYLOAD : stm32h7xx_hal_cryp.c , stm32h7xx_hal_cryp_ex.c
  • CRYP_PHASE_PROCESS : stm32h7xx_hal_cryp.c
  • CRYP_PHASE_READY : stm32h7xx_hal_cryp.c
  • CRYP_SET_PHASE : stm32h7xx_hal_cryp.c
  • CRYP_TDES_CBC : stm32h7xx_hal_cryp.h
  • CRYP_TDES_ECB : stm32h7xx_hal_cryp.h
  • CRYP_TIMEOUT_GCMCCMHEADERPHASE : stm32h7xx_hal_cryp.c
  • CRYP_TIMEOUT_GCMCCMINITPHASE : stm32h7xx_hal_cryp.c
  • CRYP_TIMEOUT_KEYPREPARATION : stm32h7xx_hal_cryp.c
  • CRYPEx_PHASE_FINAL : stm32h7xx_hal_cryp_ex.c
  • CRYPEx_PHASE_PROCESS : stm32h7xx_hal_cryp_ex.c
  • CSI_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • CSI_VALUE : stm32h7xx_hal_conf.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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- d -

  • D2_TO_D3_DMA_DIRECTION : stm32h7xx_hal_dma.c
  • D2_TO_D3_DMA_IT : stm32h7xx_hal_dma.h
  • D2_TO_D3_DMA_MDATA_SIZE : stm32h7xx_hal_dma.c
  • D2_TO_D3_DMA_MEMORY_INC : stm32h7xx_hal_dma.c
  • D2_TO_D3_DMA_MODE : stm32h7xx_hal_dma.c
  • D2_TO_D3_DMA_PDATA_SIZE : stm32h7xx_hal_dma.c
  • D2_TO_D3_DMA_PERIPHERAL_INC : stm32h7xx_hal_dma.c
  • D2_TO_D3_DMA_PRIORITY : stm32h7xx_hal_dma.c
  • DAC_ALIGN_12B_L : stm32h7xx_hal_dac.h
  • DAC_ALIGN_12B_R : stm32h7xx_hal_dac.h
  • DAC_ALIGN_8B_R : stm32h7xx_hal_dac.h
  • DAC_CHANNEL_1 : stm32h7xx_hal_dac.h
  • DAC_CHANNEL_2 : stm32h7xx_hal_dac.h
  • DAC_CHIPCONNECT_DISABLE : stm32h7xx_hal_dac.h
  • DAC_CHIPCONNECT_ENABLE : stm32h7xx_hal_dac.h
  • DAC_DHR12R1_ALIGNMENT : stm32h7xx_hal_dac.h
  • DAC_DHR12R2_ALIGNMENT : stm32h7xx_hal_dac.h
  • DAC_DHR12RD_ALIGNMENT : stm32h7xx_hal_dac.h
  • DAC_FLAG_DMAUDR1 : stm32h7xx_hal_dac.h
  • DAC_FLAG_DMAUDR2 : stm32h7xx_hal_dac.h
  • DAC_IT_DMAUDR1 : stm32h7xx_hal_dac.h
  • DAC_IT_DMAUDR2 : stm32h7xx_hal_dac.h
  • DAC_LFSRUNMASK_BIT0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS10_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS11_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS1_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS2_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS3_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS4_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS5_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS6_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS7_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS8_0 : stm32h7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS9_0 : stm32h7xx_hal_dac_ex.h
  • DAC_OUTPUTBUFFER_DISABLE : stm32h7xx_hal_dac.h
  • DAC_OUTPUTBUFFER_ENABLE : stm32h7xx_hal_dac.h
  • DAC_SAMPLEANDHOLD_DISABLE : stm32h7xx_hal_dac.h
  • DAC_SAMPLEANDHOLD_ENABLE : stm32h7xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_1 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_1023 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_127 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_15 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_2047 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_255 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_3 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_31 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_4095 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_511 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_63 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_7 : stm32h7xx_hal_dac_ex.h
  • DAC_TRIGGER_EXT_IT9 : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_HR1_TRGO1 : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_HR1_TRGO2 : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_LP1_OUT : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_LP2_OUT : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_NONE : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_SOFTWARE : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T15_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T1_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T2_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T4_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T5_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T6_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T7_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIGGER_T8_TRGO : stm32h7xx_hal_dac.h
  • DAC_TRIMMING_FACTORY : stm32h7xx_hal_dac.h
  • DAC_TRIMMING_USER : stm32h7xx_hal_dac.h
  • DCMI_BSM_ALL : stm32h7xx_hal_dcmi.h
  • DCMI_BSM_ALTERNATE_2 : stm32h7xx_hal_dcmi.h
  • DCMI_BSM_ALTERNATE_4 : stm32h7xx_hal_dcmi.h
  • DCMI_BSM_OTHER : stm32h7xx_hal_dcmi.h
  • DCMI_CR_ALL_FRAME : stm32h7xx_hal_dcmi.h
  • DCMI_CR_ALTERNATE_2_FRAME : stm32h7xx_hal_dcmi.h
  • DCMI_CR_ALTERNATE_4_FRAME : stm32h7xx_hal_dcmi.h
  • DCMI_EXTEND_DATA_10B : stm32h7xx_hal_dcmi.h
  • DCMI_EXTEND_DATA_12B : stm32h7xx_hal_dcmi.h
  • DCMI_EXTEND_DATA_14B : stm32h7xx_hal_dcmi.h
  • DCMI_EXTEND_DATA_8B : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_ERRMI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_ERRRI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_FNE : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_FRAMEMI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_FRAMERI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_HSYNC : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_LINEMI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_LINERI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_OVRMI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_OVRRI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_VSYNC : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_VSYNCMI : stm32h7xx_hal_dcmi.h
  • DCMI_FLAG_VSYNCRI : stm32h7xx_hal_dcmi.h
  • DCMI_HSPOLARITY_HIGH : stm32h7xx_hal_dcmi.h
  • DCMI_HSPOLARITY_LOW : stm32h7xx_hal_dcmi.h
  • DCMI_IT_ERR : stm32h7xx_hal_dcmi.h
  • DCMI_IT_FRAME : stm32h7xx_hal_dcmi.h
  • DCMI_IT_LINE : stm32h7xx_hal_dcmi.h
  • DCMI_IT_OVR : stm32h7xx_hal_dcmi.h
  • DCMI_IT_VSYNC : stm32h7xx_hal_dcmi.h
  • DCMI_JPEG_DISABLE : stm32h7xx_hal_dcmi.h
  • DCMI_JPEG_ENABLE : stm32h7xx_hal_dcmi.h
  • DCMI_LSM_ALL : stm32h7xx_hal_dcmi.h
  • DCMI_LSM_ALTERNATE_2 : stm32h7xx_hal_dcmi.h
  • DCMI_MIS_INDEX : stm32h7xx_hal_dcmi.h
  • DCMI_MODE_CONTINUOUS : stm32h7xx_hal_dcmi.h
  • DCMI_MODE_SNAPSHOT : stm32h7xx_hal_dcmi.h
  • DCMI_OEBS_EVEN : stm32h7xx_hal_dcmi.h
  • DCMI_OEBS_ODD : stm32h7xx_hal_dcmi.h
  • DCMI_OELS_EVEN : stm32h7xx_hal_dcmi.h
  • DCMI_OELS_ODD : stm32h7xx_hal_dcmi.h
  • DCMI_PCKPOLARITY_FALLING : stm32h7xx_hal_dcmi.h
  • DCMI_PCKPOLARITY_RISING : stm32h7xx_hal_dcmi.h
  • DCMI_POSITION_CWSIZE_VLINE : stm32h7xx_hal_dcmi.c
  • DCMI_POSITION_CWSTRT_VST : stm32h7xx_hal_dcmi.c
  • DCMI_POSITION_ESCR_FEC : stm32h7xx_hal_dcmi.c
  • DCMI_POSITION_ESCR_LEC : stm32h7xx_hal_dcmi.c
  • DCMI_POSITION_ESCR_LSC : stm32h7xx_hal_dcmi.c
  • DCMI_SR_INDEX : stm32h7xx_hal_dcmi.h
  • DCMI_SYNCHRO_EMBEDDED : stm32h7xx_hal_dcmi.h
  • DCMI_SYNCHRO_HARDWARE : stm32h7xx_hal_dcmi.h
  • DCMI_VSPOLARITY_HIGH : stm32h7xx_hal_dcmi.h
  • DCMI_VSPOLARITY_LOW : stm32h7xx_hal_dcmi.h
  • DCMI_WINDOW_COORDINATE : stm32h7xx_hal_dcmi.h
  • DCMI_WINDOW_HEIGHT : stm32h7xx_hal_dcmi.h
  • DEFAULT_CRC32_POLY : stm32h7xx_hal_crc.h
  • DEFAULT_CRC_INITVALUE : stm32h7xx_hal_crc.h
  • DEFAULT_INIT_VALUE_DISABLE : stm32h7xx_hal_crc.h
  • DEFAULT_INIT_VALUE_ENABLE : stm32h7xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_DISABLE : stm32h7xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_ENABLE : stm32h7xx_hal_crc.h
  • DEVICE_CODE1_ADDR : stm32h7xx_hal_nor.h
  • DEVICE_CODE2_ADDR : stm32h7xx_hal_nor.h
  • DEVICE_CODE3_ADDR : stm32h7xx_hal_nor.h
  • DFSDM1_CHANNEL_NUMBER : stm32h7xx_hal_dfsdm.c
  • DFSDM_AWD_HIGH_THRESHOLD : stm32h7xx_hal_dfsdm.h
  • DFSDM_AWD_LOW_THRESHOLD : stm32h7xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_0 : stm32h7xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_1 : stm32h7xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_2 : stm32h7xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_3 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_0 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_1 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_2 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_3 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_4 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_5 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_6 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_7 : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_ADC_OUTPUT : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_DUAL_MODE : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_EXTERNAL_INPUTS : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_FASTSINC_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_INTERLEAVED_MODE : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_INTERNAL_REGISTER : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_MANCHESTER_FALLING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_MANCHESTER_RISING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SAME_CHANNEL_PINS : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SINC1_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SINC2_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SINC3_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_INTERNAL : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_FALLING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_RISING : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHANNEL_STANDARD_MODE : stm32h7xx_hal_dfsdm.h
  • DFSDM_CHAWSCDR_BKSCD_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_CHAWSCDR_FOSR_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_CHCFGR1_CLK_DIV_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_CHCFGR2_DTRBS_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_CHCFGR2_OFFSET_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_CKAB_TIMEOUT : stm32h7xx_hal_dfsdm.c
  • DFSDM_CONTINUOUS_CONV_OFF : stm32h7xx_hal_dfsdm.h
  • DFSDM_CONTINUOUS_CONV_ON : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_AWD_CHANNEL_DATA : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_AWD_FILTER_DATA : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_DMA : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_INJECTED_OVERRUN : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_NONE : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_REGULAR_OVERRUN : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_BOTH_EDGES : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_EXTI11 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_EXTI15 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_FALLING_EDGE : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_LPTIM1 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_LPTIM2 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_LPTIM3 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_RISING_EDGE : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM16_OC1 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM1_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM3_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM4_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM6_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM7_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM8_TRGO : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIGGER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_FASTSINC_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC1_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC2_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC3_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC4_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC5_ORDER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SW_TRIGGER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FILTER_SYNC_TRIGGER : stm32h7xx_hal_dfsdm.h
  • DFSDM_FLTAWHTR_THRESHOLD_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTAWLTR_THRESHOLD_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTAWSR_HIGH_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTCNVTIMR_DATA_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTCR1_MSB_RCH_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTCR2_AWDCH_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTCR2_EXCH_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTEXMAX_DATA_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTEXMIN_DATA_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTFCR_FOSR_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTICR_CLRCKABF_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTICR_CLRSCDF_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTISR_CKABF_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTISR_SCDF_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTJDATAR_DATA_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_FLTRDATAR_DATA_OFFSET : stm32h7xx_hal_dfsdm.c
  • DFSDM_LSB_MASK : stm32h7xx_hal_dfsdm.c
  • DFSDM_MSB_MASK : stm32h7xx_hal_dfsdm.c
  • DFSDM_NO_BREAK_SIGNAL : stm32h7xx_hal_dfsdm.h
  • DMA2D_CCM_ARGB8888 : stm32h7xx_hal_dma2d.h
  • DMA2D_CCM_RGB888 : stm32h7xx_hal_dma2d.h
  • DMA2D_CLUT_SIZE : stm32h7xx_hal_dma2d.h
  • DMA2D_COLOR_VALUE : stm32h7xx_hal_dma2d.h
  • DMA2D_COMBINE_ALPHA : stm32h7xx_hal_dma2d.h
  • DMA2D_CSS_420 : stm32h7xx_hal_dma2d.h
  • DMA2D_CSS_422 : stm32h7xx_hal_dma2d.h
  • DMA2D_FLAG_CAE : stm32h7xx_hal_dma2d.h
  • DMA2D_FLAG_CE : stm32h7xx_hal_dma2d.h
  • DMA2D_FLAG_CTC : stm32h7xx_hal_dma2d.h
  • DMA2D_FLAG_TC : stm32h7xx_hal_dma2d.h
  • DMA2D_FLAG_TE : stm32h7xx_hal_dma2d.h
  • DMA2D_FLAG_TW : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_A4 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_A8 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_AL44 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_AL88 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_ARGB1555 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_ARGB4444 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_ARGB8888 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_L4 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_L8 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_RGB565 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_RGB888 : stm32h7xx_hal_dma2d.h
  • DMA2D_INPUT_YCBCR : stm32h7xx_hal_dma2d.h
  • DMA2D_INVERTED_ALPHA : stm32h7xx_hal_dma2d.h
  • DMA2D_IT_CAE : stm32h7xx_hal_dma2d.h
  • DMA2D_IT_CE : stm32h7xx_hal_dma2d.h
  • DMA2D_IT_CTC : stm32h7xx_hal_dma2d.h
  • DMA2D_IT_TC : stm32h7xx_hal_dma2d.h
  • DMA2D_IT_TE : stm32h7xx_hal_dma2d.h
  • DMA2D_IT_TW : stm32h7xx_hal_dma2d.h
  • DMA2D_LINE : stm32h7xx_hal_dma2d.h
  • DMA2D_LINE_WATERMARK_MAX : stm32h7xx_hal_dma2d.h
  • DMA2D_M2M : stm32h7xx_hal_dma2d.h
  • DMA2D_M2M_BLEND : stm32h7xx_hal_dma2d.h
  • DMA2D_M2M_PFC : stm32h7xx_hal_dma2d.h
  • DMA2D_NO_CSS : stm32h7xx_hal_dma2d.h
  • DMA2D_NO_MODIF_ALPHA : stm32h7xx_hal_dma2d.h
  • DMA2D_OFFSET : stm32h7xx_hal_dma2d.h
  • DMA2D_OUTPUT_ARGB1555 : stm32h7xx_hal_dma2d.h
  • DMA2D_OUTPUT_ARGB4444 : stm32h7xx_hal_dma2d.h
  • DMA2D_OUTPUT_ARGB8888 : stm32h7xx_hal_dma2d.h
  • DMA2D_OUTPUT_RGB565 : stm32h7xx_hal_dma2d.h
  • DMA2D_OUTPUT_RGB888 : stm32h7xx_hal_dma2d.h
  • DMA2D_PIXEL : stm32h7xx_hal_dma2d.h
  • DMA2D_POSITION_AMTCR_DT : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_BGPFCCR_AI : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_BGPFCCR_ALPHA : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_BGPFCCR_AM : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_BGPFCCR_CCM : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_BGPFCCR_CS : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_BGPFCCR_RBS : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_FGPFCCR_AI : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_FGPFCCR_ALPHA : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_FGPFCCR_AM : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_FGPFCCR_CCM : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_FGPFCCR_CS : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_FGPFCCR_CSS : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_FGPFCCR_RBS : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_NLR_PL : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_OPFCCR_AI : stm32h7xx_hal_dma2d.c
  • DMA2D_POSITION_OPFCCR_RBS : stm32h7xx_hal_dma2d.c
  • DMA2D_R2M : stm32h7xx_hal_dma2d.h
  • DMA2D_RB_REGULAR : stm32h7xx_hal_dma2d.h
  • DMA2D_RB_SWAP : stm32h7xx_hal_dma2d.h
  • DMA2D_REGULAR_ALPHA : stm32h7xx_hal_dma2d.h
  • DMA2D_REPLACE_ALPHA : stm32h7xx_hal_dma2d.h
  • DMA2D_TIMEOUT_ABORT : stm32h7xx_hal_dma2d.c
  • DMA2D_TIMEOUT_SUSPEND : stm32h7xx_hal_dma2d.c
  • DMA_CIRCULAR : stm32h7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_1QUARTERFULL : stm32h7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_3QUARTERSFULL : stm32h7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_FULL : stm32h7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_HALFFULL : stm32h7xx_hal_dma.h
  • DMA_FIFOMODE_DISABLE : stm32h7xx_hal_dma.h
  • DMA_FIFOMODE_ENABLE : stm32h7xx_hal_dma.h
  • DMA_FLAG_DMEIF0_4 : stm32h7xx_hal_dma.h
  • DMA_FLAG_DMEIF1_5 : stm32h7xx_hal_dma.h
  • DMA_FLAG_DMEIF2_6 : stm32h7xx_hal_dma.h
  • DMA_FLAG_DMEIF3_7 : stm32h7xx_hal_dma.h
  • DMA_FLAG_FEIF0_4 : stm32h7xx_hal_dma.h
  • DMA_FLAG_FEIF1_5 : stm32h7xx_hal_dma.h
  • DMA_FLAG_FEIF2_6 : stm32h7xx_hal_dma.h
  • DMA_FLAG_FEIF3_7 : stm32h7xx_hal_dma.h
  • DMA_FLAG_HTIF0_4 : stm32h7xx_hal_dma.h
  • DMA_FLAG_HTIF1_5 : stm32h7xx_hal_dma.h
  • DMA_FLAG_HTIF2_6 : stm32h7xx_hal_dma.h
  • DMA_FLAG_HTIF3_7 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TCIF0_4 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TCIF1_5 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TCIF2_6 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TCIF3_7 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TEIF0_4 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TEIF1_5 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TEIF2_6 : stm32h7xx_hal_dma.h
  • DMA_FLAG_TEIF3_7 : stm32h7xx_hal_dma.h
  • DMA_IT_DME : stm32h7xx_hal_dma.h
  • DMA_IT_FE : stm32h7xx_hal_dma.h
  • DMA_IT_HT : stm32h7xx_hal_dma.h
  • DMA_IT_TC : stm32h7xx_hal_dma.h
  • DMA_IT_TE : stm32h7xx_hal_dma.h
  • DMA_MBURST_INC16 : stm32h7xx_hal_dma.h
  • DMA_MBURST_INC4 : stm32h7xx_hal_dma.h
  • DMA_MBURST_INC8 : stm32h7xx_hal_dma.h
  • DMA_MBURST_SINGLE : stm32h7xx_hal_dma.h
  • DMA_MDATAALIGN_BYTE : stm32h7xx_hal_dma.h
  • DMA_MDATAALIGN_HALFWORD : stm32h7xx_hal_dma.h
  • DMA_MDATAALIGN_WORD : stm32h7xx_hal_dma.h
  • DMA_MEMORY_TO_MEMORY : stm32h7xx_hal_dma.h
  • DMA_MEMORY_TO_PERIPH : stm32h7xx_hal_dma.h
  • DMA_MINC_DISABLE : stm32h7xx_hal_dma.h
  • DMA_MINC_ENABLE : stm32h7xx_hal_dma.h
  • DMA_NORMAL : stm32h7xx_hal_dma.h
  • DMA_PBURST_INC16 : stm32h7xx_hal_dma.h
  • DMA_PBURST_INC4 : stm32h7xx_hal_dma.h
  • DMA_PBURST_INC8 : stm32h7xx_hal_dma.h
  • DMA_PBURST_SINGLE : stm32h7xx_hal_dma.h
  • DMA_PDATAALIGN_BYTE : stm32h7xx_hal_dma.h
  • DMA_PDATAALIGN_HALFWORD : stm32h7xx_hal_dma.h
  • DMA_PDATAALIGN_WORD : stm32h7xx_hal_dma.h
  • DMA_PERIPH_TO_MEMORY : stm32h7xx_hal_dma.h
  • DMA_PFCTRL : stm32h7xx_hal_dma.h
  • DMA_PINC_DISABLE : stm32h7xx_hal_dma.h
  • DMA_PINC_ENABLE : stm32h7xx_hal_dma.h
  • DMA_PRIORITY_HIGH : stm32h7xx_hal_dma.h
  • DMA_PRIORITY_LOW : stm32h7xx_hal_dma.h
  • DMA_PRIORITY_MEDIUM : stm32h7xx_hal_dma.h
  • DMA_PRIORITY_VERY_HIGH : stm32h7xx_hal_dma.h
  • DMA_REQUEST_ADC1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_ADC2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_ADC3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_CRYP_IN : stm32h7xx_hal_dma.h
  • DMA_REQUEST_CRYP_OUT : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DAC1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DAC2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DCMI : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DFSDM1_FLT0 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DFSDM1_FLT1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DFSDM1_FLT2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_DFSDM1_FLT3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR0 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR5 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR6 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_GENERATOR7 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_HASH_IN : stm32h7xx_hal_dma.h
  • DMA_REQUEST_HRTIM_MASTER : stm32h7xx_hal_dma.h
  • DMA_REQUEST_HRTIM_TIMER_A : stm32h7xx_hal_dma.h
  • DMA_REQUEST_HRTIM_TIMER_B : stm32h7xx_hal_dma.h
  • DMA_REQUEST_HRTIM_TIMER_C : stm32h7xx_hal_dma.h
  • DMA_REQUEST_HRTIM_TIMER_D : stm32h7xx_hal_dma.h
  • DMA_REQUEST_HRTIM_TIMER_E : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C1_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C1_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C2_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C2_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C3_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_I2C3_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_MEM2MEM : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SAI1_A : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SAI1_B : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SAI2_A : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SAI2_B : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SAI3_A : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SAI3_B : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPDIF_RX_CS : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPDIF_RX_DT : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI1_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI1_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI2_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI2_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI3_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI3_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI4_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI4_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI5_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SPI5_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SWPMI_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_SWPMI_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM15_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM15_COM : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM15_TRIG : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM15_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM16_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM16_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM17_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM17_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_COM : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_TRIG : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM1_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM2_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_TRIG : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM3_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM4_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_CH4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_TRIG : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM5_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM6_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM7_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH1 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH2 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH3 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH4 : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_COM : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_TRIG : stm32h7xx_hal_dma.h
  • DMA_REQUEST_TIM8_UP : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART4_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART4_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART5_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART5_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART7_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART7_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART8_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_UART8_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART1_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART1_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART2_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART2_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART3_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART3_TX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART6_RX : stm32h7xx_hal_dma.h
  • DMA_REQUEST_USART6_TX : stm32h7xx_hal_dma.h
  • DMAMUX_POSITION_CxCR_EGE : stm32h7xx_hal_dma_ex.c
  • DMAMUX_POSITION_CxCR_SE : stm32h7xx_hal_dma_ex.c
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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- e -

  • eMMC_DUAL_VOLTAGE_RANGE : stm32h7xx_hal_mmc.h
  • eMMC_HIGH_VOLTAGE_RANGE : stm32h7xx_hal_mmc.h
  • ETH_BACKOFFLIMIT_1 : stm32h7xx_hal_eth.h
  • ETH_BACKOFFLIMIT_10 : stm32h7xx_hal_eth.h
  • ETH_BACKOFFLIMIT_4 : stm32h7xx_hal_eth.h
  • ETH_BACKOFFLIMIT_8 : stm32h7xx_hal_eth.h
  • ETH_BURSTLENGTH_FIXED : stm32h7xx_hal_eth.h
  • ETH_BURSTLENGTH_MIXED : stm32h7xx_hal_eth.h
  • ETH_BURSTLENGTH_UNSPECIFIED : stm32h7xx_hal_eth.h
  • ETH_CHECKSUM_BYPASSED : stm32h7xx_hal_eth.h
  • ETH_CHECKSUM_DISABLE : stm32h7xx_hal_eth.h
  • ETH_CHECKSUM_IP_HEADER_ERROR : stm32h7xx_hal_eth.h
  • ETH_CHECKSUM_IP_PAYLOAD_ERROR : stm32h7xx_hal_eth.h
  • ETH_CHECKSUM_IPHDR_INSERT : stm32h7xx_hal_eth.h
  • ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT : stm32h7xx_hal_eth.h
  • ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC : stm32h7xx_hal_eth.h
  • ETH_CRC : stm32h7xx_hal_eth.h
  • ETH_CRC_ERROR : stm32h7xx_hal_eth.h
  • ETH_CRC_INSERT : stm32h7xx_hal_eth.h
  • ETH_CRC_PAD_DISABLE : stm32h7xx_hal_eth.h
  • ETH_CRC_PAD_INSERT : stm32h7xx_hal_eth.h
  • ETH_CRC_REPLACE : stm32h7xx_hal_eth.h
  • ETH_CTRLPACKETS_BLOCK_ALL : stm32h7xx_hal_eth.h
  • ETH_CTRLPACKETS_FORWARD_ALL : stm32h7xx_hal_eth.h
  • ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA : stm32h7xx_hal_eth.h
  • ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER : stm32h7xx_hal_eth.h
  • ETH_DEST_ADDRESS_FAIL : stm32h7xx_hal_eth.h
  • ETH_DMA_ABNORMAL_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_CONTEXT_DESC_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_CONTEXT_DESC_ERROR_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_EARLY_RX_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_EARLY_TX_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_EARLY_TX_IT_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_FATAL_BUS_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_FATAL_BUS_ERROR_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_NORMAL_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_BUFFER_READ_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_BUFFER_UNAVAILABLE_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_DESC_READ_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_DESC_WRITE_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_NO_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_PROCESS_STOPPED_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_PROCESS_STOPPED_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_RX_WATCHDOG_TIMEOUT_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_TX_BUFFER_READ_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_TX_BUFFER_UNAVAILABLE_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_TX_DESC_READ_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_TX_DESC_WRITE_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_TX_IT : stm32h7xx_hal_eth.h
  • ETH_DMA_TX_NO_ERROR_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_TX_PROCESS_STOPPED_FLAG : stm32h7xx_hal_eth.h
  • ETH_DMA_TX_PROCESS_STOPPED_IT : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_RX : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_RX1_TX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_RX2_TX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_RX3_TX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_RX4_TX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_RX5_TX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_RX6_TX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_RX7_TX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_RX8_TX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_TX : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_TX1_RX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_TX2_RX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_TX3_RX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_TX4_RX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_TX5_RX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_TX6_RX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_TX7_RX1 : stm32h7xx_hal_eth.h
  • ETH_DMAARBITRATION_TX8_RX1 : stm32h7xx_hal_eth.h
  • ETH_DMACCR_MASK : stm32h7xx_hal_eth.c
  • ETH_DMACRCR_MASK : stm32h7xx_hal_eth.c
  • ETH_DMACTCR_MASK : stm32h7xx_hal_eth.c
  • ETH_DMAMR_MASK : stm32h7xx_hal_eth.c
  • ETH_DMARXCDESC_CTXT : stm32h7xx_hal_eth.h
  • ETH_DMARXCDESC_OWN : stm32h7xx_hal_eth.h
  • ETH_DMARXCDESC_RTSH : stm32h7xx_hal_eth.h
  • ETH_DMARXCDESC_RTSL : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCRF_BUF1AP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCRF_BUF1V : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCRF_BUF2AP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCRF_BUF2V : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCRF_IOC : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCRF_OWN : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_ARPNR : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_CE : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_CTXT : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_DAF : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_DE : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_ERRORS_MASK : stm32h7xx_hal_eth.c
  • ETH_DMARXNDESCWBF_ES : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_FD : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_GP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_HF : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_IPCB : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_IPCE : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_IPHE : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_IPV4 : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_IPV6 : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_IVT : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_L3FM : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_L3L4FM : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_L4FM : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_LD : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_LT : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_LT_ARP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_LT_DVLAN : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_LT_LP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_LT_MAC : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_LT_OAM : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_LT_TP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_LT_VLAN : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_MADRM : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_OE : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_OPC : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_OVT : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_OWN : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PFT : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PL : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_ANNOUNCE : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_DREQ : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_DRESP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_FUP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_MANAG : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_NO : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_PDREQ : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_PDRESP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_PDRESPFUP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_RESERVED : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_SIGN : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PMT_SYNC : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PT : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PT_ICMP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PT_TCP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PT_UDP : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PT_UNKNOWN : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_PV : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_RE : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_RS0V : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_RS1V : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_RS2V : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_RWT : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_SAF : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_TD : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_TSA : stm32h7xx_hal_eth.h
  • ETH_DMARXNDESCWBF_VF : stm32h7xx_hal_eth.h
  • ETH_DMASBMR_MASK : stm32h7xx_hal_eth.c
  • ETH_DMATXCDESC_CDE : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_CTXT : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_IVLTV : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_IVT : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_IVTIR : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_IVTIR_DISABLE : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_IVTIR_INSERT : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_IVTIR_REMOVE : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_IVTIR_REPLACE : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_MSS : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_OSTC : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_OWN : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_TCMSSV : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_TTSH : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_TTSL : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_VLTV : stm32h7xx_hal_eth.h
  • ETH_DMATXCDESC_VT : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_B1AP : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_B1L : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_B2AP : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_B2L : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CIC : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CIC_DISABLE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CIC_IPHDR_INSERT : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CPC : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CPC_CRC_INSERT : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CPC_CRC_REPLACE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CPC_DISABLE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_CTXT : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_FD : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_FL : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_HL : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_IOC : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_LD : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_OWN : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_SAIC : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_SAIC_DISABLE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_SAIC_INSERT : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_SAIC_REPLACE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_THL : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_TPL : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_TSE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_TTSE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_VTIR : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_VTIR_DISABLE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_VTIR_INSERT : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_VTIR_REMOVE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCRF_VTIR_REPLACE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_CC : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_CTXT : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_DB : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_DP : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_EC : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_ED : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_ES : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_FD : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_FF : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_IHE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_JT : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_LCA : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_LCO : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_LD : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_NC : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_OWN : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_PCE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_TTSE : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_TTSH : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_TTSL : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_TTSS : stm32h7xx_hal_eth.h
  • ETH_DMATXNDESCWBF_UF : stm32h7xx_hal_eth.h
  • ETH_DRIBBLE_BIT_ERROR : stm32h7xx_hal_eth.h
  • ETH_EXECESSIVE_COLLISIONS : stm32h7xx_hal_eth.h
  • ETH_EXECESSIVE_DEFERRAL : stm32h7xx_hal_eth.h
  • ETH_FULLDUPLEX_MODE : stm32h7xx_hal_eth.h
  • ETH_GIANT_PACKET : stm32h7xx_hal_eth.h
  • ETH_HALFDUPLEX_MODE : stm32h7xx_hal_eth.h
  • ETH_HASH_FILTER_PASS : stm32h7xx_hal_eth.h
  • ETH_HEADER : stm32h7xx_hal_eth.h
  • ETH_INNER_TX_VLANTAG : stm32h7xx_hal_eth_ex.h
  • ETH_INNER_VLAN_DISABLE : stm32h7xx_hal_eth.h
  • ETH_INNER_VLAN_INSERT : stm32h7xx_hal_eth.h
  • ETH_INNER_VLAN_REMOVE : stm32h7xx_hal_eth.h
  • ETH_INNER_VLAN_REPLACE : stm32h7xx_hal_eth.h
  • ETH_INNERVLANTAGRXSTRIPPING_ALWAYS : stm32h7xx_hal_eth_ex.h
  • ETH_INNERVLANTAGRXSTRIPPING_IFFAILS : stm32h7xx_hal_eth_ex.h
  • ETH_INNERVLANTAGRXSTRIPPING_IFPASS : stm32h7xx_hal_eth_ex.h
  • ETH_INNERVLANTAGRXSTRIPPING_NONE : stm32h7xx_hal_eth_ex.h
  • ETH_INTERPACKETGAP_40BIT : stm32h7xx_hal_eth.h
  • ETH_INTERPACKETGAP_48BIT : stm32h7xx_hal_eth.h
  • ETH_INTERPACKETGAP_56BIT : stm32h7xx_hal_eth.h
  • ETH_INTERPACKETGAP_64BIT : stm32h7xx_hal_eth.h
  • ETH_INTERPACKETGAP_72BIT : stm32h7xx_hal_eth.h
  • ETH_INTERPACKETGAP_80BIT : stm32h7xx_hal_eth.h
  • ETH_INTERPACKETGAP_88BIT : stm32h7xx_hal_eth.h
  • ETH_INTERPACKETGAP_96BIT : stm32h7xx_hal_eth.h
  • ETH_IP_HEADER_IPV4 : stm32h7xx_hal_eth.h
  • ETH_IP_HEADER_IPV6 : stm32h7xx_hal_eth.h
  • ETH_IP_PAYLOAD_ICMPN : stm32h7xx_hal_eth.h
  • ETH_IP_PAYLOAD_TCP : stm32h7xx_hal_eth.h
  • ETH_IP_PAYLOAD_UDP : stm32h7xx_hal_eth.h
  • ETH_IP_PAYLOAD_UNKNOWN : stm32h7xx_hal_eth.h
  • ETH_JUMBO_FRAME_PAYLOAD : stm32h7xx_hal_eth.h
  • ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L3_DEST_ADDR_MATCH_DISABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L3_FILTER0_MATCH : stm32h7xx_hal_eth.h
  • ETH_L3_FILTER1_MATCH : stm32h7xx_hal_eth.h
  • ETH_L3_FILTER_0 : stm32h7xx_hal_eth_ex.h
  • ETH_L3_FILTER_1 : stm32h7xx_hal_eth_ex.h
  • ETH_L3_IPV4_MATCH : stm32h7xx_hal_eth_ex.h
  • ETH_L3_IPV6_MATCH : stm32h7xx_hal_eth_ex.h
  • ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L3_SRC_ADDR_MATCH_DISABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L4_DEST_PORT_MATCH_DISABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L4_FILTER0_MATCH : stm32h7xx_hal_eth.h
  • ETH_L4_FILTER1_MATCH : stm32h7xx_hal_eth.h
  • ETH_L4_FILTER_0 : stm32h7xx_hal_eth_ex.h
  • ETH_L4_FILTER_1 : stm32h7xx_hal_eth_ex.h
  • ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L4_SRC_PORT_MATCH_DISABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE : stm32h7xx_hal_eth_ex.h
  • ETH_L4_TCP_MATCH : stm32h7xx_hal_eth_ex.h
  • ETH_L4_UDP_MATCH : stm32h7xx_hal_eth_ex.h
  • ETH_LATE_COLLISIONS : stm32h7xx_hal_eth.h
  • ETH_LOSS_OF_CARRIER : stm32h7xx_hal_eth.h
  • ETH_MAC_ADDR0 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDR1 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDR2 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDR3 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDR4 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDR5 : stm32h7xx_hal_conf.h
  • ETH_MAC_ADDRESS0 : stm32h7xx_hal_eth.h
  • ETH_MAC_ADDRESS1 : stm32h7xx_hal_eth.h
  • ETH_MAC_ADDRESS2 : stm32h7xx_hal_eth.h
  • ETH_MAC_ADDRESS3 : stm32h7xx_hal_eth.h
  • ETH_MAC_LPI_IT : stm32h7xx_hal_eth.h
  • ETH_MAC_PHY_IT : stm32h7xx_hal_eth.h
  • ETH_MAC_PMT_IT : stm32h7xx_hal_eth.h
  • ETH_MAC_RX_STATUS_IT : stm32h7xx_hal_eth.h
  • ETH_MAC_TIMESTAMP_IT : stm32h7xx_hal_eth.h
  • ETH_MAC_TX_STATUS_IT : stm32h7xx_hal_eth.h
  • ETH_MAC_US_TICK : stm32h7xx_hal_eth.c
  • ETH_MACCR_MASK : stm32h7xx_hal_eth.c
  • ETH_MACECR_MASK : stm32h7xx_hal_eth.c
  • ETH_MACL3CR_MASK : stm32h7xx_hal_eth_ex.c
  • ETH_MACL4CR_MASK : stm32h7xx_hal_eth_ex.c
  • ETH_MACPCSR_MASK : stm32h7xx_hal_eth.c
  • ETH_MACPFR_MASK : stm32h7xx_hal_eth.c
  • ETH_MACRFCR_MASK : stm32h7xx_hal_eth.c
  • ETH_MACRXVLAN_MASK : stm32h7xx_hal_eth_ex.c
  • ETH_MACTFCR_MASK : stm32h7xx_hal_eth.c
  • ETH_MACTXVLAN_MASK : stm32h7xx_hal_eth_ex.c
  • ETH_MACWTR_MASK : stm32h7xx_hal_eth.c
  • ETH_MAGIC_PACKET_RECIEVED : stm32h7xx_hal_eth.h
  • ETH_MAX_PACKET_SIZE : stm32h7xx_hal_eth.h
  • ETH_MAX_PAYLOAD : stm32h7xx_hal_eth.h
  • ETH_MDIO_BUS_TIMEOUT : stm32h7xx_hal_eth.c
  • ETH_MIN_PAYLOAD : stm32h7xx_hal_eth.h
  • ETH_MTLRQOMR_MASK : stm32h7xx_hal_eth.c
  • ETH_MTLTQOMR_MASK : stm32h7xx_hal_eth.c
  • ETH_NO_CARRIER : stm32h7xx_hal_eth.h
  • ETH_OUTER_TX_VLANTAG : stm32h7xx_hal_eth_ex.h
  • ETH_PAUSELOWTHRESHOLD_MINUS_144 : stm32h7xx_hal_eth.h
  • ETH_PAUSELOWTHRESHOLD_MINUS_256 : stm32h7xx_hal_eth.h
  • ETH_PAUSELOWTHRESHOLD_MINUS_28 : stm32h7xx_hal_eth.h
  • ETH_PAUSELOWTHRESHOLD_MINUS_36 : stm32h7xx_hal_eth.h
  • ETH_PAUSELOWTHRESHOLD_MINUS_4 : stm32h7xx_hal_eth.h
  • ETH_PAUSELOWTHRESHOLD_MINUS_512 : stm32h7xx_hal_eth.h
  • ETH_PREAMBLELENGTH_3 : stm32h7xx_hal_eth.h
  • ETH_PREAMBLELENGTH_5 : stm32h7xx_hal_eth.h
  • ETH_PREAMBLELENGTH_7 : stm32h7xx_hal_eth.h
  • ETH_RECEIVE_ERROR : stm32h7xx_hal_eth.h
  • ETH_RECEIVE_OVERFLOW : stm32h7xx_hal_eth.h
  • ETH_RECEIVE_WATCHDOG_TIMEOUT : stm32h7xx_hal_eth.h
  • ETH_RECEIVESTOREFORWARD : stm32h7xx_hal_eth.h
  • ETH_RECEIVETHRESHOLD8_128 : stm32h7xx_hal_eth.h
  • ETH_RECEIVETHRESHOLD8_32 : stm32h7xx_hal_eth.h
  • ETH_RECEIVETHRESHOLD8_64 : stm32h7xx_hal_eth.h
  • ETH_RECEIVETHRESHOLD8_96 : stm32h7xx_hal_eth.h
  • ETH_RX_DESC_CNT : stm32h7xx_hal_conf.h , stm32h7xx_hal_eth.h
  • ETH_RX_LPI_ENTRY : stm32h7xx_hal_eth_ex.h
  • ETH_RX_LPI_EXIT : stm32h7xx_hal_eth_ex.h
  • ETH_RXDMABURSTLENGTH_16BEAT : stm32h7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_1BEAT : stm32h7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_2BEAT : stm32h7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_32BEAT : stm32h7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_4BEAT : stm32h7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_8BEAT : stm32h7xx_hal_eth.h
  • ETH_SOURCE_ADDRESS_FAIL : stm32h7xx_hal_eth.h
  • ETH_SOURCEADDRESS_DISABLE : stm32h7xx_hal_eth.h
  • ETH_SOURCEADDRESS_INSERT_ADDR0 : stm32h7xx_hal_eth.h
  • ETH_SOURCEADDRESS_INSERT_ADDR1 : stm32h7xx_hal_eth.h
  • ETH_SOURCEADDRESS_REPLACE_ADDR0 : stm32h7xx_hal_eth.h
  • ETH_SOURCEADDRESS_REPLACE_ADDR1 : stm32h7xx_hal_eth.h
  • ETH_SPEED_100M : stm32h7xx_hal_eth.h
  • ETH_SPEED_10M : stm32h7xx_hal_eth.h
  • ETH_SRC_ADDR_CONTROL_DISABLE : stm32h7xx_hal_eth.h
  • ETH_SRC_ADDR_INSERT : stm32h7xx_hal_eth.h
  • ETH_SRC_ADDR_REPLACE : stm32h7xx_hal_eth.h
  • ETH_SWRESET_TIMEOUT : stm32h7xx_hal_eth.c
  • ETH_TRANSMIT_JABBR_TIMEOUT : stm32h7xx_hal_eth.h
  • ETH_TRANSMITSTOREFORWARD : stm32h7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLD_128 : stm32h7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLD_192 : stm32h7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLD_256 : stm32h7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLD_32 : stm32h7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLD_384 : stm32h7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLD_512 : stm32h7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLD_64 : stm32h7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLD_96 : stm32h7xx_hal_eth.h
  • ETH_TX_DESC_CNT : stm32h7xx_hal_conf.h , stm32h7xx_hal_eth.h
  • ETH_TX_LPI_ENTRY : stm32h7xx_hal_eth_ex.h
  • ETH_TX_LPI_EXIT : stm32h7xx_hal_eth_ex.h
  • ETH_TX_PACKETS_FEATURES_CRCPAD : stm32h7xx_hal_eth.h
  • ETH_TX_PACKETS_FEATURES_CSUM : stm32h7xx_hal_eth.h
  • ETH_TX_PACKETS_FEATURES_INNERVLANTAG : stm32h7xx_hal_eth.h
  • ETH_TX_PACKETS_FEATURES_SAIC : stm32h7xx_hal_eth.h
  • ETH_TX_PACKETS_FEATURES_TSO : stm32h7xx_hal_eth.h
  • ETH_TX_PACKETS_FEATURES_VLANTAG : stm32h7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_16BEAT : stm32h7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_1BEAT : stm32h7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_2BEAT : stm32h7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_32BEAT : stm32h7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_4BEAT : stm32h7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_8BEAT : stm32h7xx_hal_eth.h
  • ETH_VLAN_DISABLE : stm32h7xx_hal_eth.h
  • ETH_VLAN_FILTER_PASS : stm32h7xx_hal_eth.h
  • ETH_VLAN_INSERT : stm32h7xx_hal_eth.h
  • ETH_VLAN_REMOVE : stm32h7xx_hal_eth.h
  • ETH_VLAN_REPLACE : stm32h7xx_hal_eth.h
  • ETH_VLAN_TAG : stm32h7xx_hal_eth.h
  • ETH_VLANTAGCOMPARISON_12BIT : stm32h7xx_hal_eth.h
  • ETH_VLANTAGCOMPARISON_16BIT : stm32h7xx_hal_eth.h
  • ETH_VLANTAGCONTROL_DELETE : stm32h7xx_hal_eth_ex.h
  • ETH_VLANTAGCONTROL_INSERT : stm32h7xx_hal_eth_ex.h
  • ETH_VLANTAGCONTROL_NONE : stm32h7xx_hal_eth_ex.h
  • ETH_VLANTAGCONTROL_REPLACE : stm32h7xx_hal_eth_ex.h
  • ETH_VLANTAGRXSTRIPPING_ALWAYS : stm32h7xx_hal_eth_ex.h
  • ETH_VLANTAGRXSTRIPPING_IFFAILS : stm32h7xx_hal_eth_ex.h
  • ETH_VLANTAGRXSTRIPPING_IFPASS : stm32h7xx_hal_eth_ex.h
  • ETH_VLANTAGRXSTRIPPING_NONE : stm32h7xx_hal_eth_ex.h
  • ETH_VLANTYPECHECK_CVLAN : stm32h7xx_hal_eth_ex.h
  • ETH_VLANTYPECHECK_DISABLE : stm32h7xx_hal_eth_ex.h
  • ETH_VLANTYPECHECK_SVLAN : stm32h7xx_hal_eth_ex.h
  • ETH_WAKEUP_EXTI_LINE : stm32h7xx_hal_eth.h
  • ETH_WAKEUP_PACKET_RECIEVED : stm32h7xx_hal_eth.h
  • ETH_WATCHDOG_TIMEOUT : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_10KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_11KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_12KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_13KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_14KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_15KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_16KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_2KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_3KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_4KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_5KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_6KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_7KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_8KB : stm32h7xx_hal_eth.h
  • ETH_WATCHDOGTIMEOUT_9KB : stm32h7xx_hal_eth.h
  • EXTERNAL_CLOCK_VALUE : stm32h7xx_hal_conf.h
  • EXTI_FALLING_EDGE : stm32h7xx_hal.h
  • EXTI_LINE0 : stm32h7xx_hal.h
  • EXTI_LINE1 : stm32h7xx_hal.h
  • EXTI_LINE10 : stm32h7xx_hal.h
  • EXTI_LINE11 : stm32h7xx_hal.h
  • EXTI_LINE12 : stm32h7xx_hal.h
  • EXTI_LINE13 : stm32h7xx_hal.h
  • EXTI_LINE14 : stm32h7xx_hal.h
  • EXTI_LINE15 : stm32h7xx_hal.h
  • EXTI_LINE16 : stm32h7xx_hal.h
  • EXTI_LINE17 : stm32h7xx_hal.h
  • EXTI_LINE18 : stm32h7xx_hal.h
  • EXTI_LINE19 : stm32h7xx_hal.h
  • EXTI_LINE2 : stm32h7xx_hal.h
  • EXTI_LINE20 : stm32h7xx_hal.h
  • EXTI_LINE21 : stm32h7xx_hal.h
  • EXTI_LINE22 : stm32h7xx_hal.h
  • EXTI_LINE23 : stm32h7xx_hal.h
  • EXTI_LINE24 : stm32h7xx_hal.h
  • EXTI_LINE25 : stm32h7xx_hal.h
  • EXTI_LINE26 : stm32h7xx_hal.h
  • EXTI_LINE27 : stm32h7xx_hal.h
  • EXTI_LINE28 : stm32h7xx_hal.h
  • EXTI_LINE29 : stm32h7xx_hal.h
  • EXTI_LINE3 : stm32h7xx_hal.h
  • EXTI_LINE30 : stm32h7xx_hal.h
  • EXTI_LINE31 : stm32h7xx_hal.h
  • EXTI_LINE32 : stm32h7xx_hal.h
  • EXTI_LINE33 : stm32h7xx_hal.h
  • EXTI_LINE34 : stm32h7xx_hal.h
  • EXTI_LINE35 : stm32h7xx_hal.h
  • EXTI_LINE36 : stm32h7xx_hal.h
  • EXTI_LINE37 : stm32h7xx_hal.h
  • EXTI_LINE38 : stm32h7xx_hal.h
  • EXTI_LINE39 : stm32h7xx_hal.h
  • EXTI_LINE4 : stm32h7xx_hal.h
  • EXTI_LINE40 : stm32h7xx_hal.h
  • EXTI_LINE41 : stm32h7xx_hal.h
  • EXTI_LINE42 : stm32h7xx_hal.h
  • EXTI_LINE43 : stm32h7xx_hal.h
  • EXTI_LINE44 : stm32h7xx_hal.h
  • EXTI_LINE47 : stm32h7xx_hal.h
  • EXTI_LINE48 : stm32h7xx_hal.h
  • EXTI_LINE49 : stm32h7xx_hal.h
  • EXTI_LINE5 : stm32h7xx_hal.h
  • EXTI_LINE50 : stm32h7xx_hal.h
  • EXTI_LINE51 : stm32h7xx_hal.h
  • EXTI_LINE52 : stm32h7xx_hal.h
  • EXTI_LINE53 : stm32h7xx_hal.h
  • EXTI_LINE54 : stm32h7xx_hal.h
  • EXTI_LINE55 : stm32h7xx_hal.h
  • EXTI_LINE56 : stm32h7xx_hal.h
  • EXTI_LINE57 : stm32h7xx_hal.h
  • EXTI_LINE58 : stm32h7xx_hal.h
  • EXTI_LINE59 : stm32h7xx_hal.h
  • EXTI_LINE6 : stm32h7xx_hal.h
  • EXTI_LINE60 : stm32h7xx_hal.h
  • EXTI_LINE61 : stm32h7xx_hal.h
  • EXTI_LINE62 : stm32h7xx_hal.h
  • EXTI_LINE63 : stm32h7xx_hal.h
  • EXTI_LINE64 : stm32h7xx_hal.h
  • EXTI_LINE65 : stm32h7xx_hal.h
  • EXTI_LINE66 : stm32h7xx_hal.h
  • EXTI_LINE67 : stm32h7xx_hal.h
  • EXTI_LINE68 : stm32h7xx_hal.h
  • EXTI_LINE69 : stm32h7xx_hal.h
  • EXTI_LINE7 : stm32h7xx_hal.h
  • EXTI_LINE70 : stm32h7xx_hal.h
  • EXTI_LINE71 : stm32h7xx_hal.h
  • EXTI_LINE72 : stm32h7xx_hal.h
  • EXTI_LINE73 : stm32h7xx_hal.h
  • EXTI_LINE74 : stm32h7xx_hal.h
  • EXTI_LINE75 : stm32h7xx_hal.h
  • EXTI_LINE76 : stm32h7xx_hal.h
  • EXTI_LINE8 : stm32h7xx_hal.h
  • EXTI_LINE85 : stm32h7xx_hal.h
  • EXTI_LINE86 : stm32h7xx_hal.h
  • EXTI_LINE87 : stm32h7xx_hal.h
  • EXTI_LINE9 : stm32h7xx_hal.h
  • EXTI_MODE : stm32h7xx_hal_gpio.c
  • EXTI_MODE_EVT : stm32h7xx_hal.h
  • EXTI_MODE_IT : stm32h7xx_hal.h
  • EXTI_RISING_EDGE : stm32h7xx_hal.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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- f -

  • FALLING_EDGE : stm32h7xx_hal_gpio.c
  • FDCAN_ACCEPT_IN_RX_FIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_ACCEPT_IN_RX_FIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_BRS_OFF : stm32h7xx_hal_fdcan.h
  • FDCAN_BRS_ON : stm32h7xx_hal_fdcan.h
  • FDCAN_CALIB_CLOCK_PERIOD_COUNTER : stm32h7xx_hal_fdcan.h
  • FDCAN_CALIB_FIELD_LENGTH_32 : stm32h7xx_hal_fdcan.h
  • FDCAN_CALIB_FIELD_LENGTH_64 : stm32h7xx_hal_fdcan.h
  • FDCAN_CALIB_TIME_QUANTA_COUNTER : stm32h7xx_hal_fdcan.h
  • FDCAN_CALIB_WATCHDOG_COUNTER : stm32h7xx_hal_fdcan.h
  • FDCAN_CFG_RX_FIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_CFG_RX_FIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_CFG_TX_EVENT_FIFO : stm32h7xx_hal_fdcan.h
  • FDCAN_CLASSIC_CAN : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_BASIC_CALIBRATED : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV1 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV10 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV12 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV14 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV16 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV18 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV2 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV20 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV22 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV24 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV26 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV28 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV30 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV4 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV6 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV8 : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_NOT_CALIBRATED : stm32h7xx_hal_fdcan.h
  • FDCAN_CLOCK_PRECISION_CALIBRATED : stm32h7xx_hal_fdcan.h
  • FDCAN_COM_STATE_IDLE : stm32h7xx_hal_fdcan.h
  • FDCAN_COM_STATE_RX : stm32h7xx_hal_fdcan.h
  • FDCAN_COM_STATE_SYNC : stm32h7xx_hal_fdcan.h
  • FDCAN_COM_STATE_TX : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_12 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_16 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_20 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_24 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_32 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_48 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_64 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_BYTES_8 : stm32h7xx_hal_fdcan.h
  • FDCAN_DATA_FRAME : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_0 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_12 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_16 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_20 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_24 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_3 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_32 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_4 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_48 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_5 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_6 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_64 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_7 : stm32h7xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_8 : stm32h7xx_hal_fdcan.h
  • FDCAN_ELEMENT_MASK_ANMF : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_BRS : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_DLC : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_EFC : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_ESI : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_ET : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_EXTID : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_FDF : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_FIDX : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_MM : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_RTR : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_STDID : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_TS : stm32h7xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_XTD : stm32h7xx_hal_fdcan.c
  • FDCAN_ERROR_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_ESI_ACTIVE : stm32h7xx_hal_fdcan.h
  • FDCAN_ESI_PASSIVE : stm32h7xx_hal_fdcan.h
  • FDCAN_EXT_EVT_SYNC_TT_OPERATION : stm32h7xx_hal_fdcan.h
  • FDCAN_EXTENDED_ID : stm32h7xx_hal_fdcan.h
  • FDCAN_FD_CAN : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_DISABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_DUAL : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_HP : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_MASK : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_RANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_RANGE_NO_EIDM : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_REJECT : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXBUFFER : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO0_HP : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO1_HP : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_ARB_PROTOCOL_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_BUS_OFF : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_CALIB_STATE_CHANGED : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_CALIB_WATCHDOG_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_DATA_PROTOCOL_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_LOGGING_OVERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_PASSIVE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_WARNING : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RAM_ACCESS_FAILURE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RAM_WATCHDOG : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RESERVED_ADDRESS_ACCESS : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_RX_HIGH_PRIORITY_MSG : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TIMEOUT_OCCURRED : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TIMESTAMP_WRAPAROUND : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_ABORT_COMPLETE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_COMPLETE : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_FLAG_TX_FIFO_EMPTY : stm32h7xx_hal_fdcan.h
  • FDCAN_FRAME_CLASSIC : stm32h7xx_hal_fdcan.h
  • FDCAN_FRAME_FD_BRS : stm32h7xx_hal_fdcan.h
  • FDCAN_FRAME_FD_NO_BRS : stm32h7xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_MSG_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_NO_FIFO : stm32h7xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_RXFIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_RXFIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_INTERRUPT_LINE0 : stm32h7xx_hal_fdcan.h
  • FDCAN_INTERRUPT_LINE1 : stm32h7xx_hal_fdcan.h
  • FDCAN_IR_MASK : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_ARB_PROTOCOL_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_BUS_OFF : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_CALIB_STATE_CHANGED : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_CALIB_WATCHDOG_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_DATA_PROTOCOL_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_ERROR_LOGGING_OVERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_ERROR_PASSIVE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_ERROR_WARNING : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RAM_ACCESS_FAILURE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RAM_WATCHDOG : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RESERVED_ADDRESS_ACCESS : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_BUFFER_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_MESSAGE_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_MESSAGE_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_NEW_MESSAGE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_RX_HIGH_PRIORITY_MSG : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TIMEOUT_OCCURRED : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TIMESTAMP_WRAPAROUND : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_ABORT_COMPLETE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_COMPLETE : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_ELT_LOST : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_FULL : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_NEW_DATA : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_WATERMARK : stm32h7xx_hal_fdcan.h
  • FDCAN_IT_TX_FIFO_EMPTY : stm32h7xx_hal_fdcan.h
  • FDCAN_MODE_BUS_MONITORING : stm32h7xx_hal_fdcan.h
  • FDCAN_MODE_EXTERNAL_LOOPBACK : stm32h7xx_hal_fdcan.h
  • FDCAN_MODE_INTERNAL_LOOPBACK : stm32h7xx_hal_fdcan.h
  • FDCAN_MODE_NORMAL : stm32h7xx_hal_fdcan.h
  • FDCAN_MODE_RESTRICTED_OPERATION : stm32h7xx_hal_fdcan.h
  • FDCAN_NO_TX_EVENTS : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_ACK : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_BIT0 : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_BIT1 : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_CRC : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_FORM : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_NO_CHANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_NONE : stm32h7xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_STUFF : stm32h7xx_hal_fdcan.h
  • FDCAN_REJECT : stm32h7xx_hal_fdcan.h
  • FDCAN_REMOTE_FRAME : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER0 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER1 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER10 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER11 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER12 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER13 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER14 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER15 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER16 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER17 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER18 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER19 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER2 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER20 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER21 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER22 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER23 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER24 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER25 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER26 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER27 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER28 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER29 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER3 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER30 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER31 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER32 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER33 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER34 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER35 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER36 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER37 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER38 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER39 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER4 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER40 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER41 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER42 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER43 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER44 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER45 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER46 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER47 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER48 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER49 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER5 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER50 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER51 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER52 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER53 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER54 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER55 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER56 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER57 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER58 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER59 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER6 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER60 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER61 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER62 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER63 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER7 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER8 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_BUFFER9 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_FIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_FIFO0_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_RX_FIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_FIFO1_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_RX_FIFO_BLOCKING : stm32h7xx_hal_fdcan.h
  • FDCAN_RX_FIFO_OVERWRITE : stm32h7xx_hal_fdcan.h
  • FDCAN_STANDARD_ID : stm32h7xx_hal_fdcan.h
  • FDCAN_STORE_TX_EVENTS : stm32h7xx_hal_fdcan.h
  • FDCAN_STRICTLY_TT_OPERATION : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMEOUT_CONTINUOUS : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMEOUT_RX_FIFO0 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMEOUT_RX_FIFO1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMEOUT_TX_EVENT_FIFO : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMEOUT_VALUE : stm32h7xx_hal_fdcan.c
  • FDCAN_TIMESTAMP_EXTERNAL : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_INTERNAL : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_10 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_11 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_12 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_13 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_14 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_15 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_16 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_3 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_4 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_5 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_6 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_7 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_8 : stm32h7xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_9 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_AUTO_CLK_CALIB_DISABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_AUTO_CLK_CALIB_ENABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_BACKUP_TIME_MASTER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_COMMUNICATION_LEVEL0 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_COMMUNICATION_LEVEL1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_COMMUNICATION_LEVEL2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CURRENT_TIME_MASTER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_16 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_32 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_4 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_64 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_CYCLES_PER_MATRIX_8 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_DISTURBING_ERROR_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TT_END_OF_LIST : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVENT_TRIGGER_0 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVENT_TRIGGER_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVENT_TRIGGER_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVENT_TRIGGER_3 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVT_TRIG_POL_FALLING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EVT_TRIG_POL_RISING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EXT_CLK_SYNC_DISABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_EXT_CLK_SYNC_ENABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FATAL_ERROR_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TT_FLAG_APPLICATION_WATCHDOG : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_BASIC_CYCLE_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_CONFIG_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_GLOBAL_TIME_DISC : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_GLOBAL_TIME_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_GLOBAL_TIME_WRAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_INIT_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_MATRIX_CYCLE_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_REG_TIME_MARK : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_SCHEDULING_ERROR_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_SCHEDULING_ERROR_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_START_OF_GAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_STOP_WATCH : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_SYNC_MODE_CHANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_TRIG_TIME_MARK : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_TX_COUNT_OVERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_FLAG_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_GLOB_TIME_FILT_DISABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_GLOB_TIME_FILT_ENABLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_GLOBAL_TIME_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TT_IN_GAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IN_SCHEDULE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_APPLICATION_WATCHDOG : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_BASIC_CYCLE_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_CONFIG_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_ERROR_LEVEL_CHANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_GLOBAL_TIME_DISC : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_GLOBAL_TIME_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_GLOBAL_TIME_WRAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_INIT_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_MATRIX_CYCLE_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_REG_TIME_MARK : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_SCHEDULING_ERROR_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_SCHEDULING_ERROR_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_START_OF_GAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_STOP_WATCH : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_SYNC_MODE_CHANGE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_TRIG_TIME_MARK : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_TX_COUNT_OVERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_TX_COUNT_UNDERFLOW : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_IT_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_MASTER_OFF : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_NO_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_NO_SYNC_PULSE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_OUT_OF_SYNC : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_POTENTIAL_MASTER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REF_MESSAGE_NO_PAYLOAD : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REG_TIMEMARK_CYC_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REG_TIMEMARK_DIABLED : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REG_TIMEMARK_GLO_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REG_TIMEMARK_LOC_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_16TH_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_2ND_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_32ND_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_4TH_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_64TH_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_8TH_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_REPEAT_EVERY_CYCLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_RX_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_SCHEDULE_SYNC_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TT_SEVERE_ERROR : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_SLAVE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_CYCLE_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_DISABLED : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_FALLING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_GLOBAL_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_LOCAL_TIME : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_RISING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_TRIGGER_0 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_TRIGGER_1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_TRIGGER_2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_STOP_WATCH_TRIGGER_3 : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_SYNC_BASIC_CYCLE_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_SYNC_MATRIX_START : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_SYNCHRONIZING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TIME_BASE_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TIME_MARK_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TT_TIME_SLAVE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TM_GEN_EXTERNAL_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TM_GEN_INTERNAL_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TM_NO_EXTERNAL_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TM_NO_INTERNAL_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_REF_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_REF_TRIGGER_GAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_TRIGGER_ARBITRATION : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_TRIGGER_CONTINUOUS : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_TRIGGER_MERGED : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_TX_TRIGGER_SINGLE : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_WARNING : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • FDCAN_TT_WATCH_TRIGGER_GAP : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER0 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER1 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER10 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER11 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER12 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER13 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER14 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER15 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER16 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER17 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER18 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER19 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER2 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER20 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER21 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER22 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER23 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER24 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER25 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER26 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER27 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER28 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER29 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER3 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER30 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER31 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER4 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER5 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER6 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER7 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER8 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_BUFFER9 : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_EVENT : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_EVENT_FIFO_MASK : stm32h7xx_hal_fdcan.c
  • FDCAN_TX_FIFO_OPERATION : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_IN_SPITE_OF_ABORT : stm32h7xx_hal_fdcan.h
  • FDCAN_TX_QUEUE_OPERATION : stm32h7xx_hal_fdcan.h
  • FLASH_BANK_1 : stm32h7xx_hal_flash_ex.h
  • FLASH_BANK_2 : stm32h7xx_hal_flash_ex.h
  • FLASH_BANK_BOTH : stm32h7xx_hal_flash_ex.h
  • FLASH_FLAG_ALL_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_ALL_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_ALL_ERRORS_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_ALL_ERRORS_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_BSY : stm32h7xx_hal_flash.h
  • FLASH_FLAG_BSY_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_BSY_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRC_BUSY : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRC_BUSY_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRC_BUSY_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRCEND : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRCEND_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_CRCEND_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_DBECCE_BANK1RR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_DBECCE_BANK2RR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_DBECCERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_EOP : stm32h7xx_hal_flash.h
  • FLASH_FLAG_EOP_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_EOP_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_INCERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_INCERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_INCERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_OPERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_OPERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_OPERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_PGSERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_PGSERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_PGSERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_QW : stm32h7xx_hal_flash.h
  • FLASH_FLAG_QW_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_QW_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDPERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDPERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDPERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDSERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDSERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_RDSERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_SNECCE_BANK1RR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_SNECCE_BANK2RR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_SNECCERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_STRBER_BANK1R : stm32h7xx_hal_flash.h
  • FLASH_FLAG_STRBER_BANK2R : stm32h7xx_hal_flash.h
  • FLASH_FLAG_STRBERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WBNE_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WBNE_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WDW : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WRPERR : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WRPERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_FLAG_WRPERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_ALL_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_ALL_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_CRCEND_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_CRCEND_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_DBECCERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_DBECCERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_EOP_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_EOP_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_INCERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_INCERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_OPERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_OPERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_PGSERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_PGSERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_RDPERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_RDPERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_RDSERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_RDSERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_SNECCERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_SNECCERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_STRBERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_STRBERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_IT_WRPERR_BANK1 : stm32h7xx_hal_flash.h
  • FLASH_IT_WRPERR_BANK2 : stm32h7xx_hal_flash.h
  • FLASH_KEY1 : stm32h7xx_hal_flash.h
  • FLASH_KEY2 : stm32h7xx_hal_flash.h
  • FLASH_LATENCY_0 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_1 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_2 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_3 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_4 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_5 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_6 : stm32h7xx_hal_flash_ex.h
  • FLASH_LATENCY_7 : stm32h7xx_hal_flash_ex.h
  • FLASH_OPT_KEY1 : stm32h7xx_hal_flash.h
  • FLASH_OPT_KEY2 : stm32h7xx_hal_flash.h
  • FLASH_PSIZE_BYTE : stm32h7xx_hal_flash.h
  • FLASH_PSIZE_DOUBLE_WORD : stm32h7xx_hal_flash.h
  • FLASH_PSIZE_HALF_WORD : stm32h7xx_hal_flash.h
  • FLASH_PSIZE_WORD : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_0 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_1 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_2 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_3 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_4 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_5 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_6 : stm32h7xx_hal_flash.h
  • FLASH_SECTOR_7 : stm32h7xx_hal_flash.h
  • FLASH_TIMEOUT_VALUE : stm32h7xx_hal_flash_ex.c , stm32h7xx_hal_flash.c
  • FLASH_TYPEERASE_MASSERASE : stm32h7xx_hal_flash_ex.h
  • FLASH_TYPEERASE_SECTORS : stm32h7xx_hal_flash_ex.h
  • FLASH_TYPEPROGRAM_FLASHWORD : stm32h7xx_hal_flash.h
  • FLASH_VOLTAGE_RANGE_1 : stm32h7xx_hal_flash_ex.h
  • FLASH_VOLTAGE_RANGE_2 : stm32h7xx_hal_flash_ex.h
  • FLASH_VOLTAGE_RANGE_3 : stm32h7xx_hal_flash_ex.h
  • FLASH_VOLTAGE_RANGE_4 : stm32h7xx_hal_flash_ex.h
  • FMC_SWAPBMAP_DISABLE : stm32h7xx_hal.h
  • FMC_SWAPBMAP_SDRAM_SRAM : stm32h7xx_hal.h
  • FMC_SWAPBMAP_SDRAMB2 : stm32h7xx_hal.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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- g -

  • GPIO_AF0_LCDBIAS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF0_MCO : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF0_RTC_50Hz : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF0_SWJ : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF0_TRACE : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_COMP1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_COMP2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_OTG1_FS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_OTG2_HS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_QUADSPI : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_SAI2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_SAI4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF10_SDIO2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_COMP1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_COMP2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_DFSDM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_ETH : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_I2C4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_MDIOS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_OTG1_HS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_SDIO2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_SWP : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF11_UART7 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_COMP1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_COMP2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_FMC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_MDIOS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_OTG2_FS : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF12_SDIO1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_COMP1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_COMP2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_DCMI : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_DSI : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF13_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF14_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF14_UART5 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF15_EVENTOUT : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_HRTIM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_LPTIM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_TIM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_TIM16 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_TIM17 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF1_TIM2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_HRTIM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_SAI1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM12 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM5 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_DFSDM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_HRTIM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_LPTIM2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_LPTIM3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_LPTIM4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_LPTIM5 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_LPUART : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF3_TIM8 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_CEC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_DFSDM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_LPTIM2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_TIM15 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF4_USART1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_CEC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI5 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI6 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_DFSDM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_I2C4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_SAI1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_SAI3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_SPI2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_SPI3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF6_UART4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_DFSDM1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_SDIO1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_SPI2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_SPI3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_SPI6 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_UART7 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_USART1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_USART2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_USART3 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF7_USART6 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_LPUART : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_SAI2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_SAI4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_SDIO1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_SPDIF : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_SPI6 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_UART4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_UART5 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF8_UART8 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_FDCAN1 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_FDCAN2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_FMC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_LTDC : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_QUADSPI : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_SAI4 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_SDIO2 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_SPDIF : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_TIM13 : stm32h7xx_hal_gpio_ex.h
  • GPIO_AF9_TIM14 : stm32h7xx_hal_gpio_ex.h
  • GPIO_GET_INDEX : stm32h7xx_hal_gpio_ex.h
  • GPIO_MODE : stm32h7xx_hal_gpio.c
  • GPIO_MODE_AF_OD : stm32h7xx_hal_gpio.h
  • GPIO_MODE_AF_PP : stm32h7xx_hal_gpio.h
  • GPIO_MODE_ANALOG : stm32h7xx_hal_gpio.h
  • GPIO_MODE_EVT : stm32h7xx_hal_gpio.c
  • GPIO_MODE_EVT_FALLING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING_FALLING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_INPUT : stm32h7xx_hal_gpio.h
  • GPIO_MODE_IT : stm32h7xx_hal_gpio.c
  • GPIO_MODE_IT_FALLING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_IT_RISING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_IT_RISING_FALLING : stm32h7xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_OD : stm32h7xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_PP : stm32h7xx_hal_gpio.h
  • GPIO_NOPULL : stm32h7xx_hal_gpio.h
  • GPIO_NUMBER : stm32h7xx_hal_gpio.c
  • GPIO_OUTPUT_TYPE : stm32h7xx_hal_gpio.c
  • GPIO_PIN_0 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_1 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_10 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_11 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_12 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_13 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_14 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_15 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_2 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_3 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_4 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_5 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_6 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_7 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_8 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_9 : stm32h7xx_hal_gpio.h
  • GPIO_PIN_All : stm32h7xx_hal_gpio.h
  • GPIO_PIN_MASK : stm32h7xx_hal_gpio.h
  • GPIO_PULLDOWN : stm32h7xx_hal_gpio.h
  • GPIO_PULLUP : stm32h7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_HIGH : stm32h7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_LOW : stm32h7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_MEDIUM : stm32h7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_VERY_HIGH : stm32h7xx_hal_gpio.h
  • GPIOA_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOB_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOC_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOD_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOE_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOF_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOG_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOH_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOI_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOJ_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • GPIOK_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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- h -

  • HAL_ADC_ERROR_DMA : stm32h7xx_hal_adc.h
  • HAL_ADC_ERROR_INTERNAL : stm32h7xx_hal_adc.h
  • HAL_ADC_ERROR_JQOVF : stm32h7xx_hal_adc.h
  • HAL_ADC_ERROR_NONE : stm32h7xx_hal_adc.h
  • HAL_ADC_ERROR_OVR : stm32h7xx_hal_adc.h
  • HAL_ADC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_ADC_STATE_AWD1 : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_AWD2 : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_AWD3 : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_BUSY_INTERNAL : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_CONFIG : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_DMA : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_INTERNAL : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_INJ_BUSY : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_INJ_EOC : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_INJ_JQOVF : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_MULTIMODE_SLAVE : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_READY : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_REG_BUSY : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOC : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOSMP : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_REG_OVR : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_RESET : stm32h7xx_hal_adc.h
  • HAL_ADC_STATE_TIMEOUT : stm32h7xx_hal_adc.h
  • HAL_CEC_ERROR_ARBLST : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_BRE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_LBPE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_NONE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_RXACKE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_RXOVR : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_SBPE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_TXACKE : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_TXERR : stm32h7xx_hal_cec.h
  • HAL_CEC_ERROR_TXUDR : stm32h7xx_hal_cec.h
  • HAL_CEC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_COMP_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_CORTEX_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_CRC_Input_Data_Reverse : stm32h7xx_hal_crc.h
  • HAL_CRC_LENGTH_16B : stm32h7xx_hal_crc.h
  • HAL_CRC_LENGTH_32B : stm32h7xx_hal_crc.h
  • HAL_CRC_LENGTH_7B : stm32h7xx_hal_crc.h
  • HAL_CRC_LENGTH_8B : stm32h7xx_hal_crc.h
  • HAL_CRC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_CRC_Output_Data_Reverse : stm32h7xx_hal_crc.h
  • HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_BUSY : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_DMA : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_NONE : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_NOT_SUPPORTED : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_READ : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_TIMEOUT : stm32h7xx_hal_cryp.h
  • HAL_CRYP_ERROR_WRITE : stm32h7xx_hal_cryp.h
  • HAL_CRYP_FIFO_FLUSH : stm32h7xx_hal_cryp.c
  • HAL_CRYP_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DAC_ERROR_DMA : stm32h7xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH1 : stm32h7xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH2 : stm32h7xx_hal_dac.h
  • HAL_DAC_ERROR_NONE : stm32h7xx_hal_dac.h
  • HAL_DAC_ERROR_TIMEOUT : stm32h7xx_hal_dac.h
  • HAL_DAC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DCMI_ERROR_DMA : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_NONE : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_OVR : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_SYNC : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_TIMEOUT : stm32h7xx_hal_dcmi.h
  • HAL_DCMI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DFSDM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DMA2D_DisableCLUT : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_ERROR_CAE : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_ERROR_CE : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_ERROR_NONE : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_ERROR_TE : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_ERROR_TIMEOUT : stm32h7xx_hal_dma2d.h
  • HAL_DMA2D_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DMA_ERROR_DME : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_FE : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_NO_XFER : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_NONE : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_NOT_SUPPORTED : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_PARAM : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_REQGEN : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_SYNC : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_TE : stm32h7xx_hal_dma.h
  • HAL_DMA_ERROR_TIMEOUT : stm32h7xx_hal_dma.h
  • HAL_DMA_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQUEST_GEN_EXTI0 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI0 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM1_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM2_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM3_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_TIM12_TRGO : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_ADC3_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_EXTI0 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_EXTI2 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_SPI6_IT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_COMP1_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_EXTI0 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_EXTI2 : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_I2C4_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_LPTIM2_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_LPTIM3_OUT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_RTC_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX2_SYNC_SPI6_WKUP : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_REQUEST_GEN_FALLING : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_REQUEST_GEN_NO_EVENT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_REQUEST_GEN_RISING : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_REQUEST_GEN_RISING_FALLING : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_FALLING : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_NO_EVENT : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_RISING : stm32h7xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_RISING_FALLING : stm32h7xx_hal_dma_ex.h
  • HAL_ETH_ERROR_BUSY : stm32h7xx_hal_eth.h
  • HAL_ETH_ERROR_DMA : stm32h7xx_hal_eth.h
  • HAL_ETH_ERROR_MAC : stm32h7xx_hal_eth.h
  • HAL_ETH_ERROR_NONE : stm32h7xx_hal_eth.h
  • HAL_ETH_ERROR_PARAM : stm32h7xx_hal_eth.h
  • HAL_ETH_ERROR_TIMEOUT : stm32h7xx_hal_eth.h
  • HAL_ETH_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_FDCAN_ERROR_LOG_OVERFLOW : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NONE : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_INITIALIZED : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_READY : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_STARTED : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_SUPPORTED : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PARAM : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PENDING : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PROTOCOL_ARBT : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PROTOCOL_DATA : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RAM_ACCESS : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RAM_WDG : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RESEVED_AREA : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TIMEOUT : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_APPL_WDG : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_CONFIG : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_GLOBAL_TIME : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_NO_INIT_REF : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_NO_REF : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_SCHEDULE1 : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_SCHEDULE2 : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_TX_OVERFLOW : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TT_TX_UNDERFLOW : stm32h7xx_hal_fdcan.h
  • HAL_FDCAN_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_FLASH_ERROR_DBECC : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_DBECC_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_DBECC_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_INC : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_INC_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_INC_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_NONE : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_OB_CHANGE : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_OPE : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_OPE_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_OPE_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_PGS : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_PGS_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_PGS_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDP : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDP_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDP_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDS : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDS_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_RDS_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_SNECC : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_SNECC_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_SNECC_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_STRB : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_STRB_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_STRB_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP_BANK1 : stm32h7xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP_BANK2 : stm32h7xx_hal_flash.h
  • HAL_FLASH_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_GPIO_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_HASH_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_HASHEx_IRQHandler : stm32h7xx_hal_hash.h
  • HAL_HCD_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_HRTIM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_HSEM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_I2C_ERROR_AF : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_ARLO : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_BERR : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_NONE : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_OVR : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_SIZE : stm32h7xx_hal_i2c.h
  • HAL_I2C_ERROR_TIMEOUT : stm32h7xx_hal_i2c.h
  • HAL_I2C_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_I2S_ERROR_DMA : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_FRE : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_NONE : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_OVR : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_PRESCALER : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_TIMEOUT : stm32h7xx_hal_i2s.h
  • HAL_I2S_ERROR_UDR : stm32h7xx_hal_i2s.h
  • HAL_I2S_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_IRDA_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_IWDG_DEFAULT_TIMEOUT : stm32h7xx_hal_iwdg.c
  • HAL_IWDG_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_JPEG_ERROR_DMA : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ERROR_HUFF_TABLE : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ERROR_NONE : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ERROR_QUANT_TABLE : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_ERROR_TIMEOUT : stm32h7xx_hal_jpeg.h
  • HAL_JPEG_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_LPTIM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_LTDC_ERROR_FU : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_ERROR_NONE : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_ERROR_TE : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_ERROR_TIMEOUT : stm32h7xx_hal_ltdc.h
  • HAL_LTDC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_MDIOS_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_MDMA_CHANNEL_SIZE : stm32h7xx_hal_mdma.c
  • HAL_MDMA_ERROR_ALIGNMENT : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_BLOCK_SIZE : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_BUSY : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_LINKED_LIST : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_MASK_DATA : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_NO_XFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_NONE : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_READ_XFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_TIMEOUT : stm32h7xx_hal_mdma.h
  • HAL_MDMA_ERROR_WRITE_XFER : stm32h7xx_hal_mdma.h
  • HAL_MDMA_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_MMC_ERROR_ADDR_MISALIGNED : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_ADDR_OUT_OF_RANGE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_AKE_SEQ_ERR : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_BAD_ERASE_PARAM : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_BLOCK_LEN_ERR : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_BUSY : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CARD_ECC_DISABLED : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CARD_ECC_FAILED : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CC_ERR : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CID_CSD_OVERWRITE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CMD_CRC_FAIL : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_CMD_RSP_TIMEOUT : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_COM_CRC_FAILED : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_DATA_CRC_FAIL : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_DATA_TIMEOUT : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_DMA : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_ERASE_RESET : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_ERASE_SEQ_ERR : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_ILLEGAL_CMD : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_INVALID_VOLTRANGE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_LOCK_UNLOCK_FAILED : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_NONE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_PARAM : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_RX_OVERRUN : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_STREAM_READ_UNDERRUN : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_STREAM_WRITE_OVERRUN : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_TIMEOUT : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_TX_UNDERRUN : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_UNSUPPORTED_FEATURE : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_WP_ERASE_SKIP : stm32h7xx_hal_mmc.h
  • HAL_MMC_ERROR_WRITE_PROT_VIOLATION : stm32h7xx_hal_mmc.h
  • HAL_MMC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_NAND_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_NOR_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_OPAMP_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_PCD_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_PWR_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_QPSI_TIMEOUT_DEFAULT_VALUE : stm32h7xx_hal_qspi.h
  • HAL_QSPI_ERROR_DMA : stm32h7xx_hal_qspi.h
  • HAL_QSPI_ERROR_INVALID_PARAM : stm32h7xx_hal_qspi.h
  • HAL_QSPI_ERROR_NONE : stm32h7xx_hal_qspi.h
  • HAL_QSPI_ERROR_TIMEOUT : stm32h7xx_hal_qspi.h
  • HAL_QSPI_ERROR_TRANSFER : stm32h7xx_hal_qspi.h
  • HAL_QSPI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_RCC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_RNG_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_RTC_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SAI_ERROR_AFSDET : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_CNREADY : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_DMA : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_LFSDET : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_NONE : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_OVR : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_TIMEOUT : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_UDR : stm32h7xx_hal_sai.h
  • HAL_SAI_ERROR_WCKCFG : stm32h7xx_hal_sai.h
  • HAL_SAI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SD_ERROR_ADDR_MISALIGNED : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_ADDR_OUT_OF_RANGE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_AKE_SEQ_ERR : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_BAD_ERASE_PARAM : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_BLOCK_LEN_ERR : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_BUSY : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CARD_ECC_DISABLED : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CARD_ECC_FAILED : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CC_ERR : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CID_CSD_OVERWRITE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CMD_CRC_FAIL : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_CMD_RSP_TIMEOUT : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_COM_CRC_FAILED : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_DATA_CRC_FAIL : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_DATA_TIMEOUT : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_DMA : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_ERASE_RESET : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_ERASE_SEQ_ERR : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_GENERAL_UNKNOWN_ERR : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_ILLEGAL_CMD : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_INVALID_VOLTRANGE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_LOCK_UNLOCK_FAILED : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_NONE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_PARAM : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_REQUEST_NOT_APPLICABLE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_RX_OVERRUN : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_STREAM_READ_UNDERRUN : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_STREAM_WRITE_OVERRUN : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_TIMEOUT : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_TX_UNDERRUN : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_UNSUPPORTED_FEATURE : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_WP_ERASE_SKIP : stm32h7xx_hal_sd.h
  • HAL_SD_ERROR_WRITE_PROT_VIOLATION : stm32h7xx_hal_sd.h
  • HAL_SD_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SDRAM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SMARTCARD_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SMBUS_ERROR_ACKF : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ALERT : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ARLO : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BERR : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BUSTIMEOUT : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_HALTIMEOUT : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_NONE : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_OVR : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_ERROR_PECERR : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SMBUS_STATE_BUSY : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_ERROR : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_LISTEN : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_RX : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_TX : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_READY : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_RESET : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_RX : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_TX : stm32h7xx_hal_smbus.h
  • HAL_SMBUS_STATE_TIMEOUT : stm32h7xx_hal_smbus.h
  • HAL_SPDIFRX_ERROR_DMA : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_NONE : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_OVR : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_PE : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_TIMEOUT : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_UNKNOWN : stm32h7xx_hal_spdifrx.h
  • HAL_SPDIFRX_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SPI_ERROR_ABORT : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_CRC : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_DMA : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_FLAG : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_FRE : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_MODF : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_NONE : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_OVR : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_TIMEOUT : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_UDR : stm32h7xx_hal_spi.h
  • HAL_SPI_ERROR_UNKNOW : stm32h7xx_hal_spi.h
  • HAL_SPI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SRAM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_SWPMI_ERROR_CRC : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_DMA : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_NONE : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_OVR : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_UDR : stm32h7xx_hal_swpmi.h
  • HAL_SWPMI_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_TIM_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_TIMEOUT_ADDR : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_BUSY : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_DCMI_STOP : stm32h7xx_hal_dcmi.c
  • HAL_TIMEOUT_DIR : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_DMA_ABORT : stm32h7xx_hal_dma.c
  • HAL_TIMEOUT_MDMA_ABORT : stm32h7xx_hal_mdma.c
  • HAL_TIMEOUT_RXNE : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_STOPF : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_TC : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_TCR : stm32h7xx_hal_smbus.c
  • HAL_TIMEOUT_TXIS : stm32h7xx_hal_smbus.c
  • HAL_UART_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_UART_TIMEOUT_VALUE : stm32h7xx_hal_uart.h
  • HAL_USART_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HAL_WWDG_MODULE_ENABLED : stm32h7xx_hal_conf.h
  • HASH_ALGOMODE_HASH : stm32h7xx_hal_hash.h
  • HASH_ALGOMODE_HMAC : stm32h7xx_hal_hash.h
  • HASH_ALGOSELECTION_MD5 : stm32h7xx_hal_hash.h
  • HASH_ALGOSELECTION_SHA1 : stm32h7xx_hal_hash.h
  • HASH_ALGOSELECTION_SHA224 : stm32h7xx_hal_hash.h
  • HASH_ALGOSELECTION_SHA256 : stm32h7xx_hal_hash.h
  • HASH_DATATYPE_16B : stm32h7xx_hal_hash.h
  • HASH_DATATYPE_1B : stm32h7xx_hal_hash.h
  • HASH_DATATYPE_32B : stm32h7xx_hal_hash.h
  • HASH_DATATYPE_8B : stm32h7xx_hal_hash.h
  • HASH_DIGEST_CALCULATION_NOT_STARTED : stm32h7xx_hal_hash.c
  • HASH_DIGEST_CALCULATION_STARTED : stm32h7xx_hal_hash.c
  • HASH_DIGEST_LENGTH : stm32h7xx_hal_hash.h
  • HASH_FLAG_BUSY : stm32h7xx_hal_hash.h
  • HASH_FLAG_DCIS : stm32h7xx_hal_hash.h
  • HASH_FLAG_DINIS : stm32h7xx_hal_hash.h
  • HASH_FLAG_DINNE : stm32h7xx_hal_hash.h
  • HASH_FLAG_DMAS : stm32h7xx_hal_hash.h
  • HASH_HMAC_KEYTYPE_LONGKEY : stm32h7xx_hal_hash.h
  • HASH_HMAC_KEYTYPE_SHORTKEY : stm32h7xx_hal_hash.h
  • HASH_IT_DCI : stm32h7xx_hal_hash.h
  • HASH_IT_DINI : stm32h7xx_hal_hash.h
  • HASH_NBW_PUSHED : stm32h7xx_hal_hash.h
  • HASH_NUMBER_OF_CSR_REGISTERS : stm32h7xx_hal_hash.c
  • HASH_TIMEOUTVALUE : stm32h7xx_hal_hash.c
  • HCD_PHY_EMBEDDED : stm32h7xx_hal_hcd.h
  • HCD_PHY_ULPI : stm32h7xx_hal_hcd.h
  • HCD_SPEED_FULL : stm32h7xx_hal_hcd.h
  • HCD_SPEED_HIGH : stm32h7xx_hal_hcd.h
  • HCD_SPEED_LOW : stm32h7xx_hal_hcd.h
  • HRIM_BURSTMODEPRELOAD_DISABLED : stm32h7xx_hal_hrtim.h
  • HRIM_BURSTMODEPRELOAD_ENABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGER_1 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGER_2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGER_3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGER_4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_EVENT_1 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_EVENT_2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_EVENT_3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_EVENT_4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_EVENT_5 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_EVENT_10 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_EVENT_6 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_EVENT_7 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_EVENT_8 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_EVENT_9 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGERUPDATE_MASTER : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGERUPDATE_TIMER_A : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGERUPDATE_TIMER_B : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGERUPDATE_TIMER_C : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGERUPDATE_TIMER_D : stm32h7xx_hal_hrtim.h
  • HRTIM_ADCTRIGGERUPDATE_TIMER_E : stm32h7xx_hal_hrtim.h
  • HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT : stm32h7xx_hal_hrtim.h
  • HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_AUTODELAYEDMODE_REGULAR : stm32h7xx_hal_hrtim.h
  • HRTIM_BASICOCMODE_ACTIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_BASICOCMODE_INACTIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_BASICOCMODE_TOGGLE : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_CHPR : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_CNT : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_CR : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_DIER : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_DTR : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_EEFR1 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_EEFR2 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_FLTR : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_ICR : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_OUTR : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_PER : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_REP : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_RST1R : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_RST2R : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_RSTR : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_SET1R : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTDMA_SET2R : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODE_CONTINOUS : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODE_SINGLESHOT : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECLOCKSOURCE_FHRTIM : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECLOCKSOURCE_MASTER : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECLOCKSOURCE_TIMER_A : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECLOCKSOURCE_TIMER_B : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECLOCKSOURCE_TIMER_C : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECLOCKSOURCE_TIMER_D : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECLOCKSOURCE_TIMER_E : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECTL_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODECTL_ENABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV1 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV1024 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV128 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV16 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV16384 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV2 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV2048 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV256 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV32 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV32768 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV4 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV4096 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV512 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV64 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV8 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODEPRESCALER_DIV8192 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODESTATUS_NORMAL : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODESTATUS_ONGOING : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_EVENT_7 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_EVENT_8 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_MASTER_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_MASTER_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_MASTER_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_MASTER_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_MASTER_REPETITION : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_MASTER_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERA_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERB_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERC_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERD_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION : stm32h7xx_hal_hrtim.h
  • HRTIM_BURSTMODETRIGGER_TIMERE_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_EEV_1 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_EEV_10 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_EEV_2 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_EEV_3 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_EEV_4 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_EEV_5 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_EEV_6 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_EEV_7 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_EEV_8 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_EEV_9 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TA1_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TA1_SET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TB1_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TB1_SET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TC1_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TC1_SET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TD1_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TD1_SET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TE1_RESET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TE1_SET : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TIMERA_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TIMERA_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TIMERB_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TIMERB_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TIMERC_CMP1 : stm32h7xx_hal_hrtim.h
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  • HRTIM_CAPTURETRIGGER_TIMERE_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_CAPTURETRIGGER_TIMERE_CMP2 : stm32h7xx_hal_hrtim.h
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  • HRTIM_FAULTFILTER_7 : stm32h7xx_hal_hrtim.h
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  • HRTIM_OUTPUT_TB1 : stm32h7xx_hal_hrtim.h
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  • HRTIM_OUTPUTSTATE_FAULT : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSTATE_IDLE : stm32h7xx_hal_hrtim.h
  • HRTIM_OUTPUTSTATE_RUN : stm32h7xx_hal_hrtim.h
  • HRTIM_PRELOAD_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_PRELOAD_ENABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_PRESCALERRATIO_DIV1 : stm32h7xx_hal_hrtim.h
  • HRTIM_PRESCALERRATIO_DIV2 : stm32h7xx_hal_hrtim.h
  • HRTIM_PRESCALERRATIO_DIV4 : stm32h7xx_hal_hrtim.h
  • HRTIM_PRESCALERRATIO_MUL16 : stm32h7xx_hal_hrtim.h
  • HRTIM_PRESCALERRATIO_MUL2 : stm32h7xx_hal_hrtim.h
  • HRTIM_PRESCALERRATIO_MUL32 : stm32h7xx_hal_hrtim.h
  • HRTIM_PRESCALERRATIO_MUL4 : stm32h7xx_hal_hrtim.h
  • HRTIM_PRESCALERRATIO_MUL8 : stm32h7xx_hal_hrtim.h
  • HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 : stm32h7xx_hal_hrtim.h
  • HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 : stm32h7xx_hal_hrtim.h
  • HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 : stm32h7xx_hal_hrtim.h
  • HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCINPUTSOURCE_INTERNALEVENT : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCINPUTSOURCE_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCOPTION_MASTER : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCOPTION_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCOPTION_SLAVE : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCOUTPUTPOLARITY_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCOUTPUTPOLARITY_POSITIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCOUTPUTSOURCE_MASTER_START : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCOUTPUTSOURCE_TIMA_START : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCRESET_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCRESET_ENABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCSTART_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_SYNCSTART_ENABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_TAOEN_MASK : stm32h7xx_hal_hrtim.h
  • HRTIM_TBOEN_MASK : stm32h7xx_hal_hrtim.h
  • HRTIM_TCOEN_MASK : stm32h7xx_hal_hrtim.h
  • HRTIM_TDOEN_MASK : stm32h7xx_hal_hrtim.h
  • HRTIM_TEOEN_MASK : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_CPT1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_CPT2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_DLYPRT : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_REP : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_RST : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_RST1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_RST2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_SET1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_SET2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_DMA_UPD : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_CPT1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_CPT2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_DLYPRT : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_REP : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_RST : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_RST1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_RST2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_SET1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_SET2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_FLAG_UPD : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_CPT1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_CPT2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_DLYPRT : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_REP : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_RST : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_RST1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_RST2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_SET1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_SET2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIM_IT_UPD : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMCR_TIMUPDATETRIGGER : stm32h7xx_hal_hrtim.c
  • HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_RISINGLOCK_READONLY : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_RISINGLOCK_WRITE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIMEINSERTION_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMDEADTIMEINSERTION_ENABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERBURSTMODE_MAINTAINCLOCK : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERBURSTMODE_RESETCOUNTER : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERID_MASTER : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERID_TIMER_A : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERID_TIMER_B : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERID_TIMER_C : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERID_TIMER_D : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERID_TIMER_E : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERINDEX_COMMON : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERINDEX_MASTER : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERINDEX_TIMER_A : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERINDEX_TIMER_B : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERINDEX_TIMER_C : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERINDEX_TIMER_D : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERINDEX_TIMER_E : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERRESET_MASTER : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERRESET_TIMER_A : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERRESET_TIMER_B : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERRESET_TIMER_C : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERRESET_TIMER_D : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERRESET_TIMER_E : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERUPDATE_A : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERUPDATE_B : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERUPDATE_C : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERUPDATE_D : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERUPDATE_E : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMERUPDATE_MASTER : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGCMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGCMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGCMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGCMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTFILTER_WINDOWINGTIM : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTLATCH_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMEVENTLATCH_ENABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMFAULTENABLE_FAULT1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMFAULTENABLE_FAULT2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMFAULTENABLE_FAULT3 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMFAULTENABLE_FAULT4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMFAULTENABLE_FAULT5 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMFAULTENABLE_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMFAULTLOCK_READONLY : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMFAULTLOCK_READWRITE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMPUSHPULLMODE_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMPUSHPULLMODE_ENABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_EEV_1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_EEV_10 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_EEV_2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_EEV_3 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_EEV_4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_EEV_5 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_EEV_6 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_EEV_7 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_EEV_8 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_EEV_9 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_MASTER_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_MASTER_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_MASTER_CMP3 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_MASTER_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_MASTER_PER : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMRESETTRIGGER_UPDATE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMUPDATEONRESET_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMUPDATEONRESET_ENABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMUPDATETRIGGER_MASTER : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMUPDATETRIGGER_NONE : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMUPDATETRIGGER_TIMER_A : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMUPDATETRIGGER_TIMER_B : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMUPDATETRIGGER_TIMER_C : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMUPDATETRIGGER_TIMER_D : stm32h7xx_hal_hrtim.h
  • HRTIM_TIMUPDATETRIGGER_TIMER_E : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEGATING_DMABURST : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEGATING_DMABURST_UPDATE : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEGATING_INDEPENDENT : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEGATING_UPDEN1 : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEGATING_UPDEN1_UPDATE : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEGATING_UPDEN2 : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEGATING_UPDEN2_UPDATE : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEGATING_UPDEN3 : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEGATING_UPDEN3_UPDATE : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEONREPETITION_DISABLED : stm32h7xx_hal_hrtim.h
  • HRTIM_UPDATEONREPETITION_ENABLED : stm32h7xx_hal_hrtim.h
  • HSE_STARTUP_TIMEOUT : stm32h7xx_hal_conf.h
  • HSE_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • HSE_VALUE : stm32h7xx_hal_conf.h
  • HSI48_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • HSI_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • HSI_VALUE : stm32h7xx_hal_conf.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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- i -

  • I2C_ADDRESSINGMODE_10BIT : stm32h7xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_7BIT : stm32h7xx_hal_i2c.h
  • I2C_ANALOGFILTER_DISABLE : stm32h7xx_hal_i2c_ex.h
  • I2C_ANALOGFILTER_ENABLE : stm32h7xx_hal_i2c_ex.h
  • I2C_AUTOEND_MODE : stm32h7xx_hal_i2c.h
  • I2C_DIRECTION_RECEIVE : stm32h7xx_hal_i2c.h
  • I2C_DIRECTION_TRANSMIT : stm32h7xx_hal_i2c.h
  • I2C_DUALADDRESS_DISABLE : stm32h7xx_hal_i2c.h
  • I2C_DUALADDRESS_ENABLE : stm32h7xx_hal_i2c.h
  • I2C_FASTMODEPLUS_I2C1 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C2 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C3 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C4 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB6 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB7 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB8 : stm32h7xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB9 : stm32h7xx_hal_i2c_ex.h
  • I2C_FIRST_AND_LAST_FRAME : stm32h7xx_hal_i2c.h
  • I2C_FIRST_AND_NEXT_FRAME : stm32h7xx_hal_i2c.h
  • I2C_FIRST_FRAME : stm32h7xx_hal_i2c.h
  • I2C_FLAG_ADDR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_AF : stm32h7xx_hal_i2c.h
  • I2C_FLAG_ALERT : stm32h7xx_hal_i2c.h
  • I2C_FLAG_ARLO : stm32h7xx_hal_i2c.h
  • I2C_FLAG_BERR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_BUSY : stm32h7xx_hal_i2c.h
  • I2C_FLAG_DIR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_OVR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_PECERR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_RXNE : stm32h7xx_hal_i2c.h
  • I2C_FLAG_STOPF : stm32h7xx_hal_i2c.h
  • I2C_FLAG_TC : stm32h7xx_hal_i2c.h
  • I2C_FLAG_TCR : stm32h7xx_hal_i2c.h
  • I2C_FLAG_TIMEOUT : stm32h7xx_hal_i2c.h
  • I2C_FLAG_TXE : stm32h7xx_hal_i2c.h
  • I2C_FLAG_TXIS : stm32h7xx_hal_i2c.h
  • I2C_GENERALCALL_DISABLE : stm32h7xx_hal_i2c.h
  • I2C_GENERALCALL_ENABLE : stm32h7xx_hal_i2c.h
  • I2C_GENERATE_START : stm32h7xx_hal_i2c.h
  • I2C_GENERATE_START_READ : stm32h7xx_hal_i2c.h
  • I2C_GENERATE_START_WRITE : stm32h7xx_hal_i2c.h
  • I2C_GENERATE_STOP : stm32h7xx_hal_i2c.h
  • I2C_GET_ADDR_MATCH : stm32h7xx_hal_i2c.h
  • I2C_GET_DIR : stm32h7xx_hal_i2c.h
  • I2C_GET_DMA_REMAIN_DATA : stm32h7xx_hal_i2c.c
  • I2C_GET_OWN_ADDRESS1 : stm32h7xx_hal_i2c.h
  • I2C_GET_OWN_ADDRESS2 : stm32h7xx_hal_i2c.h
  • I2C_GET_STOP_MODE : stm32h7xx_hal_i2c.h
  • I2C_IT_ADDRI : stm32h7xx_hal_i2c.h
  • I2C_IT_ERRI : stm32h7xx_hal_i2c.h
  • I2C_IT_NACKI : stm32h7xx_hal_i2c.h
  • I2C_IT_RXI : stm32h7xx_hal_i2c.h
  • I2C_IT_STOPI : stm32h7xx_hal_i2c.h
  • I2C_IT_TCI : stm32h7xx_hal_i2c.h
  • I2C_IT_TXI : stm32h7xx_hal_i2c.h
  • I2C_LAST_FRAME : stm32h7xx_hal_i2c.h
  • I2C_MEM_ADD_LSB : stm32h7xx_hal_i2c.h
  • I2C_MEM_ADD_MSB : stm32h7xx_hal_i2c.h
  • I2C_MEMADD_SIZE_16BIT : stm32h7xx_hal_i2c.h
  • I2C_MEMADD_SIZE_8BIT : stm32h7xx_hal_i2c.h
  • I2C_NEXT_FRAME : stm32h7xx_hal_i2c.h
  • I2C_NO_OPTION_FRAME : stm32h7xx_hal_i2c.h
  • I2C_NO_STARTSTOP : stm32h7xx_hal_i2c.h
  • I2C_NOSTRETCH_DISABLE : stm32h7xx_hal_i2c.h
  • I2C_NOSTRETCH_ENABLE : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK01 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK02 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK03 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK04 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK05 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK06 : stm32h7xx_hal_i2c.h
  • I2C_OA2_MASK07 : stm32h7xx_hal_i2c.h
  • I2C_OA2_NOMASK : stm32h7xx_hal_i2c.h
  • I2C_RELOAD_MODE : stm32h7xx_hal_i2c.h
  • I2C_RESET_CR2 : stm32h7xx_hal_i2c.h
  • I2C_SOFTEND_MODE : stm32h7xx_hal_i2c.h
  • I2C_STATE_MASTER_BUSY_RX : stm32h7xx_hal_i2c.c
  • I2C_STATE_MASTER_BUSY_TX : stm32h7xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_RX : stm32h7xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_TX : stm32h7xx_hal_i2c.c
  • I2C_STATE_MSK : stm32h7xx_hal_i2c.c
  • I2C_STATE_NONE : stm32h7xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_RX : stm32h7xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_TX : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_ADDR : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_BUSY : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_DIR : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_FLAG : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_RXNE : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_STOPF : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_TC : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_TCR : stm32h7xx_hal_i2c.c
  • I2C_TIMEOUT_TXIS : stm32h7xx_hal_i2c.c
  • I2C_XFER_CPLT_IT : stm32h7xx_hal_i2c.c
  • I2C_XFER_ERROR_IT : stm32h7xx_hal_i2c.c
  • I2C_XFER_LISTEN_IT : stm32h7xx_hal_i2c.c
  • I2C_XFER_RELOAD_IT : stm32h7xx_hal_i2c.c
  • I2C_XFER_RX_IT : stm32h7xx_hal_i2c.c
  • I2C_XFER_TX_IT : stm32h7xx_hal_i2c.c
  • I2S_AUDIOFREQ_11K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_16K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_192K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_22K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_32K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_44K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_48K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_8K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_96K : stm32h7xx_hal_i2s.h
  • I2S_AUDIOFREQ_DEFAULT : stm32h7xx_hal_i2s.h
  • I2S_CPOL_HIGH : stm32h7xx_hal_i2s.h
  • I2S_CPOL_LOW : stm32h7xx_hal_i2s.h
  • I2S_DATA_24BIT_ALIGNMENT_LEFT : stm32h7xx_hal_i2s.h
  • I2S_DATA_24BIT_ALIGNMENT_RIGHT : stm32h7xx_hal_i2s.h
  • I2S_DATAFORMAT_16B : stm32h7xx_hal_i2s.h
  • I2S_DATAFORMAT_16B_EXTENDED : stm32h7xx_hal_i2s.h
  • I2S_DATAFORMAT_24B : stm32h7xx_hal_i2s.h
  • I2S_DATAFORMAT_32B : stm32h7xx_hal_i2s.h
  • I2S_FIFO_THRESHOLD_01DATA : stm32h7xx_hal_i2s.h
  • I2S_FIFO_THRESHOLD_02DATA : stm32h7xx_hal_i2s.h
  • I2S_FIFO_THRESHOLD_03DATA : stm32h7xx_hal_i2s.h
  • I2S_FIFO_THRESHOLD_04DATA : stm32h7xx_hal_i2s.h
  • I2S_FIFO_THRESHOLD_05DATA : stm32h7xx_hal_i2s.h
  • I2S_FIFO_THRESHOLD_06DATA : stm32h7xx_hal_i2s.h
  • I2S_FIFO_THRESHOLD_07DATA : stm32h7xx_hal_i2s.h
  • I2S_FIFO_THRESHOLD_08DATA : stm32h7xx_hal_i2s.h
  • I2S_FIRSTBIT_LSB : stm32h7xx_hal_i2s.h
  • I2S_FIRSTBIT_MSB : stm32h7xx_hal_i2s.h
  • I2S_FLAG_FRE : stm32h7xx_hal_i2s.h
  • I2S_FLAG_OVR : stm32h7xx_hal_i2s.h
  • I2S_FLAG_RXNE : stm32h7xx_hal_i2s.h
  • I2S_FLAG_RXWNE : stm32h7xx_hal_i2s.h
  • I2S_FLAG_TXE : stm32h7xx_hal_i2s.h
  • I2S_FLAG_UDR : stm32h7xx_hal_i2s.h
  • I2S_IO_SWAP_DISABLE : stm32h7xx_hal_i2s.h
  • I2S_IO_SWAP_ENABLE : stm32h7xx_hal_i2s.h
  • I2S_IT_ERR : stm32h7xx_hal_i2s.h
  • I2S_IT_RXNE : stm32h7xx_hal_i2s.h
  • I2S_IT_TXE : stm32h7xx_hal_i2s.h
  • I2S_MASTER_KEEP_IO_STATE_DISABLE : stm32h7xx_hal_i2s.h
  • I2S_MASTER_KEEP_IO_STATE_ENABLE : stm32h7xx_hal_i2s.h
  • I2S_MCLKOUTPUT_DISABLE : stm32h7xx_hal_i2s.h
  • I2S_MCLKOUTPUT_ENABLE : stm32h7xx_hal_i2s.h
  • I2S_MODE_MASTER_FD : stm32h7xx_hal_i2s.h
  • I2S_MODE_MASTER_RX : stm32h7xx_hal_i2s.h
  • I2S_MODE_MASTER_TX : stm32h7xx_hal_i2s.h
  • I2S_MODE_SLAVE_FD : stm32h7xx_hal_i2s.h
  • I2S_MODE_SLAVE_RX : stm32h7xx_hal_i2s.h
  • I2S_MODE_SLAVE_TX : stm32h7xx_hal_i2s.h
  • I2S_SLAVE_EXTEND_FRE_DETECTION_DISABLE : stm32h7xx_hal_i2s.h
  • I2S_SLAVE_EXTEND_FRE_DETECTION_ENABLE : stm32h7xx_hal_i2s.h
  • I2S_STANDARD_LSB : stm32h7xx_hal_i2s.h
  • I2S_STANDARD_MSB : stm32h7xx_hal_i2s.h
  • I2S_STANDARD_PCM_LONG : stm32h7xx_hal_i2s.h
  • I2S_STANDARD_PCM_SHORT : stm32h7xx_hal_i2s.h
  • I2S_STANDARD_PHILIPS : stm32h7xx_hal_i2s.h
  • I2S_WS_INVERSION_DISABLE : stm32h7xx_hal_i2s.h
  • I2S_WS_INVERSION_ENABLE : stm32h7xx_hal_i2s.h
  • IDCODE_DEVID_MASK : stm32h7xx_hal.c
  • INCR_RX_DESC_INDEX : stm32h7xx_hal_eth.c
  • INCR_TX_DESC_INDEX : stm32h7xx_hal_eth.c
  • IRDA_AUTOBAUD_REQUEST : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_FEF : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_IDLEF : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_NEF : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_OREF : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_PEF : stm32h7xx_hal_irda.h
  • IRDA_CLEAR_TCF : stm32h7xx_hal_irda.h
  • IRDA_CR1_FIELDS : stm32h7xx_hal_irda.c
  • IRDA_DMA_RX_DISABLE : stm32h7xx_hal_irda.h
  • IRDA_DMA_RX_ENABLE : stm32h7xx_hal_irda.h
  • IRDA_DMA_TX_DISABLE : stm32h7xx_hal_irda.h
  • IRDA_DMA_TX_ENABLE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_ABRE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_ABRF : stm32h7xx_hal_irda.h
  • IRDA_FLAG_BUSY : stm32h7xx_hal_irda.h
  • IRDA_FLAG_FE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_NE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_ORE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_PE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_REACK : stm32h7xx_hal_irda.h
  • IRDA_FLAG_RXNE : stm32h7xx_hal_irda.h
  • IRDA_FLAG_TC : stm32h7xx_hal_irda.h
  • IRDA_FLAG_TEACK : stm32h7xx_hal_irda.h
  • IRDA_FLAG_TXE : stm32h7xx_hal_irda.h
  • IRDA_GETCLOCKSOURCE : stm32h7xx_hal_irda_ex.h
  • IRDA_IT_ERR : stm32h7xx_hal_irda.h
  • IRDA_IT_FE : stm32h7xx_hal_irda.h
  • IRDA_IT_IDLE : stm32h7xx_hal_irda.h
  • IRDA_IT_MASK : stm32h7xx_hal_irda.h
  • IRDA_IT_NE : stm32h7xx_hal_irda.h
  • IRDA_IT_ORE : stm32h7xx_hal_irda.h
  • IRDA_IT_PE : stm32h7xx_hal_irda.h
  • IRDA_IT_RXNE : stm32h7xx_hal_irda.h
  • IRDA_IT_TC : stm32h7xx_hal_irda.h
  • IRDA_IT_TXE : stm32h7xx_hal_irda.h
  • IRDA_MASK_COMPUTATION : stm32h7xx_hal_irda.h
  • IRDA_MODE_DISABLE : stm32h7xx_hal_irda.h
  • IRDA_MODE_ENABLE : stm32h7xx_hal_irda.h
  • IRDA_MODE_RX : stm32h7xx_hal_irda.h
  • IRDA_MODE_TX : stm32h7xx_hal_irda.h
  • IRDA_MODE_TX_RX : stm32h7xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_irda.h
  • IRDA_PARITY_EVEN : stm32h7xx_hal_irda.h
  • IRDA_PARITY_NONE : stm32h7xx_hal_irda.h
  • IRDA_PARITY_ODD : stm32h7xx_hal_irda.h
  • IRDA_POWERMODE_LOWPOWER : stm32h7xx_hal_irda.h
  • IRDA_POWERMODE_NORMAL : stm32h7xx_hal_irda.h
  • IRDA_RXDATA_FLUSH_REQUEST : stm32h7xx_hal_irda.h
  • IRDA_STATE_DISABLE : stm32h7xx_hal_irda.h
  • IRDA_STATE_ENABLE : stm32h7xx_hal_irda.h
  • IRDA_TEACK_REACK_TIMEOUT : stm32h7xx_hal_irda.c
  • IRDA_TXDATA_FLUSH_REQUEST : stm32h7xx_hal_irda.h
  • IRDA_WORDLENGTH_7B : stm32h7xx_hal_irda.h
  • IRDA_WORDLENGTH_8B : stm32h7xx_hal_irda.h
  • IRDA_WORDLENGTH_9B : stm32h7xx_hal_irda.h
  • IS_ADC1_DIFF_CHANNEL : stm32h7xx_hal_adc_ex.h
  • IS_ADC2_DIFF_CHANNEL : stm32h7xx_hal_adc_ex.h
  • IS_ADC3_DIFF_CHANNEL : stm32h7xx_hal_adc_ex.h
  • IS_ADC_ANALOG_WATCHDOG_MODE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_ANALOG_WATCHDOG_NUMBER : stm32h7xx_hal_adc_ex.h
  • IS_ADC_CALFACT : stm32h7xx_hal_adc_ex.h
  • IS_ADC_CHANNEL : stm32h7xx_hal_adc_ex.h
  • IS_ADC_CLOCKPRESCALER : stm32h7xx_hal_adc.h
  • IS_ADC_CONVERSION_GROUP : stm32h7xx_hal_adc_ex.h
  • IS_ADC_CONVERSIONDATAMGT : stm32h7xx_hal_adc.h
  • IS_ADC_DUAL_DATA_MODE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_EOC_SELECTION : stm32h7xx_hal_adc.h
  • IS_ADC_EVENT_TYPE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_EXTTRIG : stm32h7xx_hal_adc.h
  • IS_ADC_EXTTRIG_EDGE : stm32h7xx_hal_adc.h
  • IS_ADC_EXTTRIGINJEC : stm32h7xx_hal_adc_ex.h
  • IS_ADC_EXTTRIGINJEC_EDGE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_INJECTED_NB_CONV : stm32h7xx_hal_adc_ex.h
  • IS_ADC_INJECTED_RANK : stm32h7xx_hal_adc_ex.h
  • IS_ADC_LEFT_BIT_SHIFT : stm32h7xx_hal_adc_ex.h
  • IS_ADC_MODE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_OFFSET_NUMBER : stm32h7xx_hal_adc_ex.h
  • IS_ADC_OVERRUN : stm32h7xx_hal_adc.h
  • IS_ADC_OVERSAMPLING_RATIO : stm32h7xx_hal_adc_ex.h
  • IS_ADC_RANGE : stm32h7xx_hal_adc.h
  • IS_ADC_REGOVERSAMPLING_MODE : stm32h7xx_hal_adc_ex.h
  • IS_ADC_REGULAR_DISCONT_NUMBER : stm32h7xx_hal_adc.h
  • IS_ADC_REGULAR_NB_CONV : stm32h7xx_hal_adc.h
  • IS_ADC_REGULAR_RANK : stm32h7xx_hal_adc.h
  • IS_ADC_RESOLUTION : stm32h7xx_hal_adc.h
  • IS_ADC_RESOLUTION_8_BITS : stm32h7xx_hal_adc.h
  • IS_ADC_RIGHT_BIT_SHIFT : stm32h7xx_hal_adc_ex.h
  • IS_ADC_SAMPLE_TIME : stm32h7xx_hal_adc.h
  • IS_ADC_SAMPLING_DELAY : stm32h7xx_hal_adc_ex.h
  • IS_ADC_SCAN_MODE : stm32h7xx_hal_adc.h , stm32h7xx_hal_adc_ex.h
  • IS_ADC_SINGLE_DIFFERENTIAL : stm32h7xx_hal_adc_ex.h
  • IS_ADC_TRIGGERED_OVERSAMPLING_MODE : stm32h7xx_hal_adc_ex.h
  • IS_BDMA_D3_REQUEST : stm32h7xx_hal_dma.h
  • IS_BOOT_ADDRESS : stm32h7xx_hal_flash.h
  • IS_CEC_ADDRESS : stm32h7xx_hal_cec.h
  • IS_CEC_BREERRORBITGEN : stm32h7xx_hal_cec.h
  • IS_CEC_BRERXSTOP : stm32h7xx_hal_cec.h
  • IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION : stm32h7xx_hal_cec.h
  • IS_CEC_LBPEERRORBITGEN : stm32h7xx_hal_cec.h
  • IS_CEC_LISTENING_MODE : stm32h7xx_hal_cec.h
  • IS_CEC_MSGSIZE : stm32h7xx_hal_cec.h
  • IS_CEC_OWN_ADDRESS : stm32h7xx_hal_cec.h
  • IS_CEC_SFTOP : stm32h7xx_hal_cec.h
  • IS_CEC_SIGNALFREETIME : stm32h7xx_hal_cec.h
  • IS_CEC_TOLERANCE : stm32h7xx_hal_cec.h
  • IS_CHANNEL_STATUS_MASK : stm32h7xx_hal_spdifrx.h
  • IS_COMP_BLANKINGSRCE : stm32h7xx_hal_comp.h
  • IS_COMP_HYSTERESIS : stm32h7xx_hal_comp.h
  • IS_COMP_INPUT_MINUS : stm32h7xx_hal_comp.h
  • IS_COMP_INPUT_PLUS : stm32h7xx_hal_comp.h
  • IS_COMP_OUTPUT_LEVEL : stm32h7xx_hal_comp.h
  • IS_COMP_OUTPUTPOL : stm32h7xx_hal_comp.h
  • IS_COMP_POWERMODE : stm32h7xx_hal_comp.h
  • IS_COMP_TRIGGERMODE : stm32h7xx_hal_comp.h
  • IS_COMP_WINDOWMODE : stm32h7xx_hal_comp.h
  • IS_CRC_INPUTDATA_FORMAT : stm32h7xx_hal_crc.h
  • IS_CRC_INPUTDATA_INVERSION_MODE : stm32h7xx_hal_crc_ex.h
  • IS_CRC_OUTPUTDATA_INVERSION_MODE : stm32h7xx_hal_crc_ex.h
  • IS_CRC_POL_LENGTH : stm32h7xx_hal_crc.h
  • IS_CRYP_ALGORITHM : stm32h7xx_hal_cryp.h
  • IS_CRYP_DATATYPE : stm32h7xx_hal_cryp.h
  • IS_CRYP_KEYSIZE : stm32h7xx_hal_cryp.h
  • IS_D2_DMA_INSTANCE : stm32h7xx_hal_dma.h
  • IS_D2_DMAMUX_REQUEST_GEN_SIGNAL_ID : stm32h7xx_hal_dma_ex.h
  • IS_D2_DMAMUX_SYNC_SIGNAL_ID : stm32h7xx_hal_dma_ex.h
  • IS_D3_DMA_INSTANCE : stm32h7xx_hal_dma.h
  • IS_D3_DMAMUX_REQUEST_GEN_SIGNAL_ID : stm32h7xx_hal_dma_ex.h
  • IS_D3_DMAMUX_SYNC_SIGNAL_ID : stm32h7xx_hal_dma_ex.h
  • IS_D3_STATE : stm32h7xx_hal_pwr_ex.h
  • IS_DAC_ALIGN : stm32h7xx_hal_dac.h
  • IS_DAC_CHANNEL : stm32h7xx_hal_dac.h
  • IS_DAC_CHIP_CONNECTION : stm32h7xx_hal_dac_ex.h
  • IS_DAC_DATA : stm32h7xx_hal_dac.h
  • IS_DAC_HOLDTIME : stm32h7xx_hal_dac_ex.h
  • IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE : stm32h7xx_hal_dac_ex.h
  • IS_DAC_NEWTRIMMINGVALUE : stm32h7xx_hal_dac_ex.h
  • IS_DAC_OUTPUT_BUFFER_STATE : stm32h7xx_hal_dac.h
  • IS_DAC_REFRESHTIME : stm32h7xx_hal_dac.h
  • IS_DAC_SAMPLEANDHOLD : stm32h7xx_hal_dac_ex.h
  • IS_DAC_SAMPLETIME : stm32h7xx_hal_dac_ex.h
  • IS_DAC_TRIGGER : stm32h7xx_hal_dac_ex.h
  • IS_DAC_TRIMMING : stm32h7xx_hal_dac_ex.h
  • IS_DAC_TRIMMINGVALUE : stm32h7xx_hal_dac_ex.h
  • IS_DCMI_BYTE_SELECT_MODE : stm32h7xx_hal_dcmi.h
  • IS_DCMI_BYTE_SELECT_START : stm32h7xx_hal_dcmi.h
  • IS_DCMI_CAPTURE_MODE : stm32h7xx_hal_dcmi.h
  • IS_DCMI_CAPTURE_RATE : stm32h7xx_hal_dcmi.h
  • IS_DCMI_EXTENDED_DATA : stm32h7xx_hal_dcmi.h
  • IS_DCMI_HSPOLARITY : stm32h7xx_hal_dcmi.h
  • IS_DCMI_LINE_SELECT_MODE : stm32h7xx_hal_dcmi.h
  • IS_DCMI_LINE_SELECT_START : stm32h7xx_hal_dcmi.h
  • IS_DCMI_MODE_JPEG : stm32h7xx_hal_dcmi.h
  • IS_DCMI_PCKPOLARITY : stm32h7xx_hal_dcmi.h
  • IS_DCMI_SYNCHRO : stm32h7xx_hal_dcmi.h
  • IS_DCMI_VSPOLARITY : stm32h7xx_hal_dcmi.h
  • IS_DCMI_WINDOW_COORDINATE : stm32h7xx_hal_dcmi.h
  • IS_DCMI_WINDOW_HEIGHT : stm32h7xx_hal_dcmi.h
  • IS_DEFAULT_INIT_VALUE : stm32h7xx_hal_crc.h
  • IS_DEFAULT_POLYNOMIAL : stm32h7xx_hal_crc.h
  • IS_DFSDM_BREAK_SIGNALS : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_DATA_PACKING : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_FILTER_ORDER : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_FILTER_OVS_RATIO : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_INPUT : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_INPUT_PINS : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_OFFSET : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_OUTPUT_CLOCK : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_SCD_THRESHOLD : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_SPI_CLOCK : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_CONTINUOUS_MODE : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_AWD_DATA_SOURCE : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_AWD_THRESHOLD : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_EXT_TRIG : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_EXT_TRIG_EDGE : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_INJ_TRIGGER : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_OVS_RATIO : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_REG_TRIGGER : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_SINC_ORDER : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_INJECTED_CHANNEL : stm32h7xx_hal_dfsdm.h
  • IS_DFSDM_REGULAR_CHANNEL : stm32h7xx_hal_dfsdm.h
  • IS_DMA2D_ALPHA_INVERTED : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_ALPHA_MODE : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_CHROMA_SUB_SAMPLING : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_CLUT_CM : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_CLUT_SIZE : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_CMODE : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_COLOR : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_GET_FLAG : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_INPUT_COLOR_MODE : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_IT : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_LAYER : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_LINE : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_LINEWATERMARK : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_MODE : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_OFFSET : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_PIXEL : stm32h7xx_hal_dma2d.h
  • IS_DMA2D_RB_SWAP : stm32h7xx_hal_dma2d.h
  • IS_DMA_BUFFER_SIZE : stm32h7xx_hal_dma.h
  • IS_DMA_D2_REQUEST : stm32h7xx_hal_dma.h
  • IS_DMA_DIRECTION : stm32h7xx_hal_dma.h
  • IS_DMA_FIFO_MODE_STATE : stm32h7xx_hal_dma.h
  • IS_DMA_FIFO_THRESHOLD : stm32h7xx_hal_dma.h
  • IS_DMA_MEMORY_BURST : stm32h7xx_hal_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32h7xx_hal_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32h7xx_hal_dma.h
  • IS_DMA_MODE : stm32h7xx_hal_dma.h
  • IS_DMA_PERIPHERAL_BURST : stm32h7xx_hal_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32h7xx_hal_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32h7xx_hal_dma.h
  • IS_DMA_PRIORITY : stm32h7xx_hal_dma.h
  • IS_DMAMUX_REQUEST_GEN_POLARITY : stm32h7xx_hal_dma_ex.h
  • IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER : stm32h7xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_EVENT : stm32h7xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_POLARITY : stm32h7xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_REQUEST_NUMBER : stm32h7xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_STATE : stm32h7xx_hal_dma_ex.h
  • IS_EXTI_ALL_LINE : stm32h7xx_hal.h
  • IS_EXTI_CONFIG_LINE : stm32h7xx_hal.h
  • IS_EXTI_D1_LINE : stm32h7xx_hal.h
  • IS_EXTI_D3_CLEAR : stm32h7xx_hal.h
  • IS_EXTI_D3_LINE : stm32h7xx_hal.h
  • IS_EXTI_EDGE_LINE : stm32h7xx_hal.h
  • IS_EXTI_MODE_LINE : stm32h7xx_hal.h
  • IS_FDCAN_BRS : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_CALIBRATION_FIELD_LENGTH : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_CKDIV : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DATA_PRESCALER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DATA_SIZE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DATA_SJW : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DATA_TSEG1 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DATA_TSEG2 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_DLC : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_EFC : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_ESI : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_EXT_FILTER_TYPE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_FDF : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_FIFO_WATERMARK : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_FILTER_CFG : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_FRAME_FORMAT : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_FRAME_TYPE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_ID_TYPE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_IT : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_IT_LINE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_MAX_VALUE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_MIN_VALUE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_MODE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_PRESCALER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_SJW : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_TSEG1 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_TSEG2 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_NON_MATCHING : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_OPERATION_MODE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_RX_FIFO : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_RX_FIFO_MODE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_STD_FILTER_TYPE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TIMEOUT : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TIMESTAMP : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TIMESTAMP_PRESCALER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_AUTO_CLK_CALIBRATION : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_BASIC_CYCLES_NUMBER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_CYCLE_START_SYNC : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_EVENT_TRIGGER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_EVENT_TRIGGER_POLARITY : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_EXTERNAL_CLK_SYNC : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_GLOBAL_TIME_FILTERING : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_IT : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_OPERATION : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_REPEAT_FACTOR : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_STOP_WATCH_POLARITY : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_STOP_WATCH_SOURCE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_STOP_WATCH_TRIGGER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TIME_MASTER : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TIME_PRESET : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TM_EVENT_EXTERNAL : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TM_EVENT_INTERNAL : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TRIGGER_TYPE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TUR_DENOMINATOR : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TUR_LEVEL_0_2 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TUR_LEVEL_1 : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TUR_NUMERATOR : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TT_TX_ENABLE_WINDOW : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TX_FIFO_QUEUE_MODE : stm32h7xx_hal_fdcan.h
  • IS_FDCAN_TX_LOCATION : stm32h7xx_hal_fdcan.h
  • IS_FLASH_ADDRESS : stm32h7xx_hal_flash_ex.h
  • IS_FLASH_BANK : stm32h7xx_hal_flash.h , stm32h7xx_hal_flash_ex.h
  • IS_FLASH_BANK_EXCLUSIVE : stm32h7xx_hal_flash.h
  • IS_FLASH_FLAG_BANK1 : stm32h7xx_hal_flash.h
  • IS_FLASH_FLAG_BANK2 : stm32h7xx_hal_flash.h
  • IS_FLASH_IT_BANK1 : stm32h7xx_hal_flash.h
  • IS_FLASH_IT_BANK2 : stm32h7xx_hal_flash.h
  • IS_FLASH_LATENCY : stm32h7xx_hal_flash_ex.h
  • IS_FLASH_NBSECTORS : stm32h7xx_hal_flash_ex.h
  • IS_FLASH_PROGRAM_ADDRESS : stm32h7xx_hal_flash.h
  • IS_FLASH_PROGRAM_ADDRESS_BANK1 : stm32h7xx_hal_flash.h
  • IS_FLASH_PROGRAM_ADDRESS_BANK2 : stm32h7xx_hal_flash.h
  • IS_FLASH_SECTOR : stm32h7xx_hal_flash_ex.h
  • IS_FLASH_TYPEERASE : stm32h7xx_hal_flash_ex.h
  • IS_FLASH_TYPEPROGRAM : stm32h7xx_hal_flash.h
  • IS_FMC_SWAPBMAP_MODE : stm32h7xx_hal.h
  • IS_GPIO_AF : stm32h7xx_hal_gpio_ex.h
  • IS_GPIO_MODE : stm32h7xx_hal_gpio.h
  • IS_GPIO_PIN : stm32h7xx_hal_gpio.h
  • IS_GPIO_PIN_ACTION : stm32h7xx_hal_gpio.h
  • IS_GPIO_PIN_AVAILABLE : stm32h7xx_hal_gpio_ex.h
  • IS_GPIO_PULL : stm32h7xx_hal_gpio.h
  • IS_GPIO_SPEED : stm32h7xx_hal_gpio.h
  • IS_HASH_DATATYPE : stm32h7xx_hal_hash.h
  • IS_HASH_DMA_MULTIBUFFER_SIZE : stm32h7xx_hal_hash.h
  • IS_HASH_POLLING_MULTIBUFFER_SIZE : stm32h7xx_hal_hash.h
  • IS_HASH_PROCESSING : stm32h7xx_hal_hash.h
  • IS_HCD_ALL_INSTANCE : stm32h7xx_hal_hcd.h
  • IS_HHRTIM_DACSYNC : stm32h7xx_hal_hrtim.h
  • IS_HMAC_DMA_MULTIBUFFER_SIZE : stm32h7xx_hal_hash.h
  • IS_HMAC_PROCESSING : stm32h7xx_hal_hash.h
  • IS_HRTIM_ADCTRIGGER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_ADCTRIGGERUPDATE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_AUTODELAYEDMODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_BASICOCMODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_BURSTMODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_BURSTMODECLOCKSOURCE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_BURSTMODECTL : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_BURSTMODEPRELOAD : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_BURSTMODETRIGGER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_CAPTUREUNIT : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_CHOPPER_DUTYCYCLE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_CHOPPER_PRESCALERRATIO : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_CHOPPER_PULSEWIDTH : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_COMPAREUNIT : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_EVENT : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_EVENTFASTMODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_EVENTFILTER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_EVENTPOLARITY : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_EVENTPRESCALER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_EVENTSENSITIVITY : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_EVENTSRC : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_FAULT : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_FAULTFILTER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_FAULTLOCK : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_FAULTMODECTL : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_FAULTPOLARITY : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_FAULTPRESCALER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_FAULTSOURCE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_HALFMODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_HRTIM_BURSTMODEPRESCALER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_IT : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_MASTER_DMA : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_MASTER_IT : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_MODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_MODE_ONEPULSE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_OUTPUT : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_OUTPUTBURSTMODEENTRY : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_OUTPUTCHOPPERMODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_OUTPUTFAULTLEVEL : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_OUTPUTIDLELEVEL : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_OUTPUTIDLEMODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_OUTPUTLEVEL : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_OUTPUTPOLARITY : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_OUTPUTRESET : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_OUTPUTSET : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_PRELOAD : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_PRESCALERRATIO : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_SYNCINPUTSOURCE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_SYNCOUTPUTPOLARITY : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_SYNCOUTPUTSOURCE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_SYNCRESET : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_SYNCSTART : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIM_DMA : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIM_IT : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMDEADTIME_FALLINGLOCK : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMDEADTIME_FALLINGSIGN : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMDEADTIME_PRESCALERRATIO : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMDEADTIME_RISINGLOCK : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMDEADTIME_RISINGSIGN : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMDEADTIMEINSERTION : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMDELAYEDPROTECTION : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMER_BURSTDMA : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMER_CAPTURETRIGGER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMER_OUTPUT : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMERBURSTMODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMERID : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMERINDEX : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMERRESET : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMERUPDATE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMEVENTFILTER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMEVENTLATCH : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMFAULTENABLE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMFAULTLOCK : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMING_UNIT : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMPUSHPULLMODE : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMRESETTRIGGER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMUPDATEONRESET : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_TIMUPDATETRIGGER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_UPDATEGATING_MASTER : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_UPDATEGATING_TIM : stm32h7xx_hal_hrtim.h
  • IS_HRTIM_UPDATEONREPETITION : stm32h7xx_hal_hrtim.h
  • IS_HSEM_KEY : stm32h7xx_hal_hsem.h
  • IS_HSEM_MASTERID : stm32h7xx_hal_hsem.h
  • IS_HSEM_PROCESSID : stm32h7xx_hal_hsem.h
  • IS_HSEM_SEMID : stm32h7xx_hal_hsem.h
  • IS_I2C_ADDRESSING_MODE : stm32h7xx_hal_i2c.h
  • IS_I2C_ANALOG_FILTER : stm32h7xx_hal_i2c_ex.h
  • IS_I2C_DIGITAL_FILTER : stm32h7xx_hal_i2c_ex.h
  • IS_I2C_DUAL_ADDRESS : stm32h7xx_hal_i2c.h
  • IS_I2C_FASTMODEPLUS : stm32h7xx_hal_i2c_ex.h
  • IS_I2C_GENERAL_CALL : stm32h7xx_hal_i2c.h
  • IS_I2C_MEMADD_SIZE : stm32h7xx_hal_i2c.h
  • IS_I2C_NO_STRETCH : stm32h7xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32h7xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2 : stm32h7xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2_MASK : stm32h7xx_hal_i2c.h
  • IS_I2C_TRANSFER_OPTIONS_REQUEST : stm32h7xx_hal_i2c.h
  • IS_I2S_AUDIO_FREQ : stm32h7xx_hal_i2s.h
  • IS_I2S_CPOL : stm32h7xx_hal_i2s.h
  • IS_I2S_DATA_24BIT_ALIGNMENT : stm32h7xx_hal_i2s.h
  • IS_I2S_DATA_FORMAT : stm32h7xx_hal_i2s.h
  • IS_I2S_FD_MODE : stm32h7xx_hal_i2s.h
  • IS_I2S_FIFO_THRESHOLD : stm32h7xx_hal_i2s.h
  • IS_I2S_FIRST_BIT : stm32h7xx_hal_i2s.h
  • IS_I2S_IO_SWAP : stm32h7xx_hal_i2s.h
  • IS_I2S_MASTER : stm32h7xx_hal_i2s.h
  • IS_I2S_MASTER_KEEP_IO_STATE : stm32h7xx_hal_i2s.h
  • IS_I2S_MCLK_OUTPUT : stm32h7xx_hal_i2s.h
  • IS_I2S_MODE : stm32h7xx_hal_i2s.h
  • IS_I2S_RX_MODE : stm32h7xx_hal_i2s.h
  • IS_I2S_SLAVE_EXTEND_FRE_DETECTION : stm32h7xx_hal_i2s.h
  • IS_I2S_STANDARD : stm32h7xx_hal_i2s.h
  • IS_I2S_TX_MODE : stm32h7xx_hal_i2s.h
  • IS_I2S_WS_INVERSION : stm32h7xx_hal_i2s.h
  • IS_IRDA_BAUDRATE : stm32h7xx_hal_irda.h
  • IS_IRDA_DMA_RX : stm32h7xx_hal_irda.h
  • IS_IRDA_DMA_TX : stm32h7xx_hal_irda.h
  • IS_IRDA_MODE : stm32h7xx_hal_irda.h
  • IS_IRDA_ONE_BIT_SAMPLE : stm32h7xx_hal_irda.h
  • IS_IRDA_PARITY : stm32h7xx_hal_irda.h
  • IS_IRDA_POWERMODE : stm32h7xx_hal_irda.h
  • IS_IRDA_PRESCALER : stm32h7xx_hal_irda.h
  • IS_IRDA_REQUEST_PARAMETER : stm32h7xx_hal_irda.h
  • IS_IRDA_STATE : stm32h7xx_hal_irda.h
  • IS_IRDA_TX_RX_MODE : stm32h7xx_hal_irda.h
  • IS_IRDA_WORD_LENGTH : stm32h7xx_hal_irda.h
  • IS_IWDG_PRESCALER : stm32h7xx_hal_iwdg.h
  • IS_IWDG_RELOAD : stm32h7xx_hal_iwdg.h
  • IS_IWDG_WINDOW : stm32h7xx_hal_iwdg.h
  • IS_JPEG_CHROMASUBSAMPLING : stm32h7xx_hal_jpeg.h
  • IS_JPEG_COLORSPACE : stm32h7xx_hal_jpeg.h
  • IS_JPEG_IMAGE_QUALITY : stm32h7xx_hal_jpeg.h
  • IS_JPEG_PAUSE_RESUME_STATE : stm32h7xx_hal_jpeg.h
  • IS_LPTIM_AUTORELOAD : stm32h7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_POLARITY : stm32h7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALER : stm32h7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALERDIV1 : stm32h7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SAMPLE_TIME : stm32h7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SOURCE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_COMPARE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_COUNTER_SOURCE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_EXT_TRG_POLARITY : stm32h7xx_hal_lptim.h
  • IS_LPTIM_INPUT1_SOURCE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_INPUT2_SOURCE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_OUTPUT_POLARITY : stm32h7xx_hal_lptim.h
  • IS_LPTIM_PERIOD : stm32h7xx_hal_lptim.h
  • IS_LPTIM_PULSE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_TRG_SOURCE : stm32h7xx_hal_lptim.h
  • IS_LPTIM_TRIG_SAMPLE_TIME : stm32h7xx_hal_lptim.h
  • IS_LPTIM_UPDATE_MODE : stm32h7xx_hal_lptim.h
  • IS_LPUART_STOPBITS : stm32h7xx_hal_uart.h
  • IS_LTDC_AAH : stm32h7xx_hal_ltdc.h
  • IS_LTDC_AAW : stm32h7xx_hal_ltdc.h
  • IS_LTDC_AHBP : stm32h7xx_hal_ltdc.h
  • IS_LTDC_ALPHA : stm32h7xx_hal_ltdc.h
  • IS_LTDC_AVBP : stm32h7xx_hal_ltdc.h
  • IS_LTDC_BLENDING_FACTOR1 : stm32h7xx_hal_ltdc.h
  • IS_LTDC_BLENDING_FACTOR2 : stm32h7xx_hal_ltdc.h
  • IS_LTDC_BLUEVALUE : stm32h7xx_hal_ltdc.h
  • IS_LTDC_CFBLL : stm32h7xx_hal_ltdc.h
  • IS_LTDC_CFBLNBR : stm32h7xx_hal_ltdc.h
  • IS_LTDC_CFBP : stm32h7xx_hal_ltdc.h
  • IS_LTDC_DEPOL : stm32h7xx_hal_ltdc.h
  • IS_LTDC_GREENVALUE : stm32h7xx_hal_ltdc.h
  • IS_LTDC_HCONFIGSP : stm32h7xx_hal_ltdc.h
  • IS_LTDC_HCONFIGST : stm32h7xx_hal_ltdc.h
  • IS_LTDC_HSPOL : stm32h7xx_hal_ltdc.h
  • IS_LTDC_HSYNC : stm32h7xx_hal_ltdc.h
  • IS_LTDC_LAYER : stm32h7xx_hal_ltdc.h
  • IS_LTDC_LIPOS : stm32h7xx_hal_ltdc.h
  • IS_LTDC_PCPOL : stm32h7xx_hal_ltdc.h
  • IS_LTDC_PIXEL_FORMAT : stm32h7xx_hal_ltdc.h
  • IS_LTDC_REDVALUE : stm32h7xx_hal_ltdc.h
  • IS_LTDC_RELOAD : stm32h7xx_hal_ltdc.h
  • IS_LTDC_TOTALH : stm32h7xx_hal_ltdc.h
  • IS_LTDC_TOTALW : stm32h7xx_hal_ltdc.h
  • IS_LTDC_VCONFIGSP : stm32h7xx_hal_ltdc.h
  • IS_LTDC_VCONFIGST : stm32h7xx_hal_ltdc.h
  • IS_LTDC_VSPOL : stm32h7xx_hal_ltdc.h
  • IS_LTDC_VSYNC : stm32h7xx_hal_ltdc.h
  • IS_MDIOS_PORTADDRESS : stm32h7xx_hal_mdios.h
  • IS_MDIOS_PREAMBLECHECK : stm32h7xx_hal_mdios.h
  • IS_MDIOS_REGISTER : stm32h7xx_hal_mdios.h
  • IS_MDMA_BLOCK_ADDR_OFFSET : stm32h7xx_hal_mdma.h
  • IS_MDMA_BLOCK_COUNT : stm32h7xx_hal_mdma.h
  • IS_MDMA_BUFFER_TRANSFER_LENGTH : stm32h7xx_hal_mdma.h
  • IS_MDMA_DATA_ALIGNMENT : stm32h7xx_hal_mdma.h
  • IS_MDMA_DESTINATION_BURST : stm32h7xx_hal_mdma.h
  • IS_MDMA_DESTINATION_DATASIZE : stm32h7xx_hal_mdma.h
  • IS_MDMA_DESTINATION_INC : stm32h7xx_hal_mdma.h
  • IS_MDMA_ENDIANNESS_MODE : stm32h7xx_hal_mdma.h
  • IS_MDMA_LEVEL_COMPLETE : stm32h7xx_hal_mdma.h
  • IS_MDMA_PRIORITY : stm32h7xx_hal_mdma.h
  • IS_MDMA_REQUEST : stm32h7xx_hal_mdma.h
  • IS_MDMA_SOURCE_BURST : stm32h7xx_hal_mdma.h
  • IS_MDMA_SOURCE_DATASIZE : stm32h7xx_hal_mdma.h
  • IS_MDMA_SOURCE_INC : stm32h7xx_hal_mdma.h
  • IS_MDMA_TRANSFER_LENGTH : stm32h7xx_hal_mdma.h
  • IS_MDMA_TRANSFER_TRIGGER_MODE : stm32h7xx_hal_mdma.h
  • IS_MPU_ACCESS_BUFFERABLE : stm32h7xx_hal_cortex.h
  • IS_MPU_ACCESS_CACHEABLE : stm32h7xx_hal_cortex.h
  • IS_MPU_ACCESS_SHAREABLE : stm32h7xx_hal_cortex.h
  • IS_MPU_INSTRUCTION_ACCESS : stm32h7xx_hal_cortex.h
  • IS_MPU_REGION_ENABLE : stm32h7xx_hal_cortex.h
  • IS_MPU_REGION_NUMBER : stm32h7xx_hal_cortex.h
  • IS_MPU_REGION_PERMISSION_ATTRIBUTE : stm32h7xx_hal_cortex.h
  • IS_MPU_REGION_SIZE : stm32h7xx_hal_cortex.h
  • IS_MPU_SUB_REGION_DISABLE : stm32h7xx_hal_cortex.h
  • IS_MPU_TEX_LEVEL : stm32h7xx_hal_cortex.h
  • IS_NVIC_DEVICE_IRQ : stm32h7xx_hal_cortex.h
  • IS_NVIC_PREEMPTION_PRIORITY : stm32h7xx_hal_cortex.h
  • IS_NVIC_PRIORITY_GROUP : stm32h7xx_hal_cortex.h
  • IS_NVIC_SUB_PRIORITY : stm32h7xx_hal_cortex.h
  • IS_OB_BOOT_ADD_OPTION : stm32h7xx_hal_flash_ex.h
  • IS_OB_BOOT_ADDRESS : stm32h7xx_hal_flash_ex.h
  • IS_OB_BOR_LEVEL : stm32h7xx_hal_flash_ex.h
  • IS_OB_IWDG1_SOURCE : stm32h7xx_hal_flash_ex.h
  • IS_OB_IWDG_SOURCE : stm32h7xx_hal_flash_ex.h
  • IS_OB_IWDG_STDBY_FREEZE : stm32h7xx_hal_flash_ex.h
  • IS_OB_IWDG_STOP_FREEZE : stm32h7xx_hal_flash_ex.h
  • IS_OB_PCROP_RDP : stm32h7xx_hal_flash_ex.h
  • IS_OB_RDP_LEVEL : stm32h7xx_hal_flash_ex.h
  • IS_OB_SECURE_RDP : stm32h7xx_hal_flash_ex.h
  • IS_OB_STDBY_D1_RESET : stm32h7xx_hal_flash_ex.h
  • IS_OB_STDBY_SOURCE : stm32h7xx_hal_flash_ex.h
  • IS_OB_STOP_D1_RESET : stm32h7xx_hal_flash_ex.h
  • IS_OB_STOP_SOURCE : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_IOHSLV : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_IWDG_STDBY : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_IWDG_STOP : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_SECURITY : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_SWAP_BANK : stm32h7xx_hal_flash_ex.h
  • IS_OB_USER_TYPE : stm32h7xx_hal_flash_ex.h
  • IS_OB_WRP_SECTOR : stm32h7xx_hal_flash_ex.h
  • IS_OB_WWDG_SOURCE : stm32h7xx_hal_flash_ex.h
  • IS_OPAMP_FACTORYTRIMMING : stm32h7xx_hal_opamp.h
  • IS_OPAMP_FUNCTIONAL_NORMALMODE : stm32h7xx_hal_opamp.h
  • IS_OPAMP_INVERTING_INPUT_STANDALONE : stm32h7xx_hal_opamp.h
  • IS_OPAMP_NONINVERTING_INPUT : stm32h7xx_hal_opamp.h
  • IS_OPAMP_PGA_GAIN : stm32h7xx_hal_opamp.h
  • IS_OPAMP_PGACONNECT : stm32h7xx_hal_opamp.h
  • IS_OPAMP_POWERMODE : stm32h7xx_hal_opamp.h
  • IS_OPAMP_TRIMMING : stm32h7xx_hal_opamp.h
  • IS_OPAMP_TRIMMINGVALUE : stm32h7xx_hal_opamp.h
  • IS_OPAMP_VREF : stm32h7xx_hal_opamp.h
  • IS_OPTIONBYTE : stm32h7xx_hal_flash_ex.h
  • IS_PARITY_ERROR_MASK : stm32h7xx_hal_spdifrx.h
  • IS_PCD_ALL_INSTANCE : stm32h7xx_hal_pcd.h
  • IS_PREAMBLE_TYPE_MASK : stm32h7xx_hal_spdifrx.h
  • IS_PWR_AVD_LEVEL : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_AVD_MODE : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_BATTERY_RESISTOR_SELECT : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_DOMAIN : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_PVD_LEVEL : stm32h7xx_hal_pwr.h
  • IS_PWR_PVD_MODE : stm32h7xx_hal_pwr.h
  • IS_PWR_REGULATOR : stm32h7xx_hal_pwr.h
  • IS_PWR_REGULATOR_VOLTAGE : stm32h7xx_hal_pwr.h
  • IS_PWR_SLEEP_ENTRY : stm32h7xx_hal_pwr.h
  • IS_PWR_STOP_ENTRY : stm32h7xx_hal_pwr.h
  • IS_PWR_STOP_MODE_REGULATOR_VOLTAGE : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_SUPPLY : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_FLAG : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN_POLARITY : stm32h7xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN_PULL : stm32h7xx_hal_pwr_ex.h
  • IS_QSPI_ADDRESS_MODE : stm32h7xx_hal_qspi.h
  • IS_QSPI_ADDRESS_SIZE : stm32h7xx_hal_qspi.h
  • IS_QSPI_ALTERNATE_BYTES_MODE : stm32h7xx_hal_qspi.h
  • IS_QSPI_ALTERNATE_BYTES_SIZE : stm32h7xx_hal_qspi.h
  • IS_QSPI_AUTOMATIC_STOP : stm32h7xx_hal_qspi.h
  • IS_QSPI_CLOCK_MODE : stm32h7xx_hal_qspi.h
  • IS_QSPI_CLOCK_PRESCALER : stm32h7xx_hal_qspi.h
  • IS_QSPI_CS_HIGH_TIME : stm32h7xx_hal_qspi.h
  • IS_QSPI_DATA_MODE : stm32h7xx_hal_qspi.h
  • IS_QSPI_DDR_HHC : stm32h7xx_hal_qspi.h
  • IS_QSPI_DDR_MODE : stm32h7xx_hal_qspi.h
  • IS_QSPI_DUAL_FLASH_MODE : stm32h7xx_hal_qspi.h
  • IS_QSPI_DUMMY_CYCLES : stm32h7xx_hal_qspi.h
  • IS_QSPI_FIFO_THRESHOLD : stm32h7xx_hal_qspi.h
  • IS_QSPI_FLASH_ID : stm32h7xx_hal_qspi.h
  • IS_QSPI_FLASH_SIZE : stm32h7xx_hal_qspi.h
  • IS_QSPI_FUNCTIONAL_MODE : stm32h7xx_hal_qspi.c
  • IS_QSPI_INSTRUCTION : stm32h7xx_hal_qspi.h
  • IS_QSPI_INSTRUCTION_MODE : stm32h7xx_hal_qspi.h
  • IS_QSPI_INTERVAL : stm32h7xx_hal_qspi.h
  • IS_QSPI_MATCH_MODE : stm32h7xx_hal_qspi.h
  • IS_QSPI_SIOO_MODE : stm32h7xx_hal_qspi.h
  • IS_QSPI_SSHIFT : stm32h7xx_hal_qspi.h
  • IS_QSPI_STATUS_BYTES_SIZE : stm32h7xx_hal_qspi.h
  • IS_QSPI_TIMEOUT_ACTIVATION : stm32h7xx_hal_qspi.h
  • IS_QSPI_TIMEOUT_PERIOD : stm32h7xx_hal_qspi.h
  • IS_RCC_ADCCLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CALIBRATION_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_CECCLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CLKPSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CLOCKTYPE : stm32h7xx_hal_rcc.h
  • IS_RCC_CRS_ERRORLIMIT : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_FREQERRORDIR : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_HSI48CALIBRATION : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_RELOADVALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_DIV : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_POLARITY : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_SOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_CSI : stm32h7xx_hal_rcc.h
  • IS_RCC_CSICALIBRATION_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_D1PCLK1 : stm32h7xx_hal_rcc.h
  • IS_RCC_D3PCLK1 : stm32h7xx_hal_rcc.h
  • IS_RCC_DFSDM1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_FDCANCLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_FLAG : stm32h7xx_hal_rcc.h
  • IS_RCC_FMCCLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_HCLK : stm32h7xx_hal_rcc.h
  • IS_RCC_HRTIM1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_HSE : stm32h7xx_hal_rcc.h
  • IS_RCC_HSI : stm32h7xx_hal_rcc.h
  • IS_RCC_HSI48 : stm32h7xx_hal_rcc.h
  • IS_RCC_I2C1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_I2C2CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_I2C3CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_I2C4CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPTIM1CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPTIM2CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPTIM3CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPTIM4CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPTIM5CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LPUART1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_LSE : stm32h7xx_hal_rcc.h
  • IS_RCC_LSI : stm32h7xx_hal_rcc.h
  • IS_RCC_MCO : stm32h7xx_hal_rcc.h
  • IS_RCC_MCO1SOURCE : stm32h7xx_hal_rcc.h
  • IS_RCC_MCO2SOURCE : stm32h7xx_hal_rcc.h
  • IS_RCC_MCODIV : stm32h7xx_hal_rcc.h
  • IS_RCC_OSCILLATORTYPE : stm32h7xx_hal_rcc.h
  • IS_RCC_PCLK1 : stm32h7xx_hal_rcc.h
  • IS_RCC_PCLK2 : stm32h7xx_hal_rcc.h
  • IS_RCC_PERIPHCLOCK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL : stm32h7xx_hal_rcc.h
  • IS_RCC_PLL2CLOCKOUT_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2M_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2N_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2P_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2Q_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL2R_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3CLOCKOUT_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3M_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3N_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3P_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3Q_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLL3R_VALUE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_PLLCLOCKOUT_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLM_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLN_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLP_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLQ_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLR_VALUE : stm32h7xx_hal_rcc.h
  • IS_RCC_PLLSOURCE : stm32h7xx_hal_rcc.h
  • IS_RCC_QSPICLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_RNGCLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_RTCCLKSOURCE : stm32h7xx_hal_rcc.h
  • IS_RCC_SAI1CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SAI2CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SAI3CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SAI4ACLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SAI4BCLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SCOPE_WWDG : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SDMMC : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPDIFRXCLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI1CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI2CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI3CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI4CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI5CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SPI6CLK : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_STOP_KERWAKEUPCLOCK : stm32h7xx_hal_rcc.h
  • IS_RCC_STOP_WAKEUPCLOCK : stm32h7xx_hal_rcc.h
  • IS_RCC_SWPMI1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_SYSCLK : stm32h7xx_hal_rcc.h
  • IS_RCC_SYSCLKSOURCE : stm32h7xx_hal_rcc.h
  • IS_RCC_TIMPRES : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_UART4CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_UART5CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_UART7CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_UART8CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART1CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART2CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART3CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USART6CLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RCC_USBCLKSOURCE : stm32h7xx_hal_rcc_ex.h
  • IS_RNG_CED : stm32h7xx_hal_rng.h
  • IS_RNG_FLAG : stm32h7xx_hal_rng.h
  • IS_RNG_IT : stm32h7xx_hal_rng.h
  • IS_RTC_ALARM : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_DATE : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_SEL : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_MASK : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_MASK : stm32h7xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_VALUE : stm32h7xx_hal_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32h7xx_hal_rtc.h
  • IS_RTC_BKP : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_CALIB_OUTPUT : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_DATE : stm32h7xx_hal_rtc.h
  • IS_RTC_DAYLIGHT_SAVING : stm32h7xx_hal_rtc.h
  • IS_RTC_FORMAT : stm32h7xx_hal_rtc.h
  • IS_RTC_HOUR12 : stm32h7xx_hal_rtc.h
  • IS_RTC_HOUR24 : stm32h7xx_hal_rtc.h
  • IS_RTC_HOUR_FORMAT : stm32h7xx_hal_rtc.h
  • IS_RTC_HOURFORMAT12 : stm32h7xx_hal_rtc.h
  • IS_RTC_MINUTES : stm32h7xx_hal_rtc.h
  • IS_RTC_MONTH : stm32h7xx_hal_rtc.h
  • IS_RTC_OUTPUT : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_OUTPUT_POL : stm32h7xx_hal_rtc.h
  • IS_RTC_OUTPUT_REMAP : stm32h7xx_hal_rtc.h
  • IS_RTC_OUTPUT_TYPE : stm32h7xx_hal_rtc.h
  • IS_RTC_SECONDS : stm32h7xx_hal_rtc.h
  • IS_RTC_SHIFT_ADD1S : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_SHIFT_SUBFS : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PERIOD : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PLUS : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_STORE_OPERATION : stm32h7xx_hal_rtc.h
  • IS_RTC_SYNCH_PREDIV : stm32h7xx_hal_rtc.h
  • IS_RTC_TAMPER : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_ERASE_MODE : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_FILTER : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_MASKFLAG_STATE : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PRECHARGE_DURATION : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PULLUP_STATE : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TRIGGER : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMP_PIN : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_CLOCK : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_COUNTER : stm32h7xx_hal_rtc_ex.h
  • IS_RTC_WEEKDAY : stm32h7xx_hal_rtc.h
  • IS_RTC_YEAR : stm32h7xx_hal_rtc.h
  • IS_SAI_AUDIO_FREQUENCY : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_ACTIVE_FRAME : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_CLOCK_STROBING : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_COMPANDING_MODE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_DATASIZE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FIFO_THRESHOLD : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FIRST_BIT : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FIRSTBIT_OFFSET : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FRAME_LENGTH : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FS_DEFINITION : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FS_OFFSET : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_FS_POLARITY : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MASTER_DIVIDER : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MCK_OVERSAMPLING : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MODE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_COUNTER : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_VALUE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_NODIVIDER : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_OUTPUT_DRIVE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_PROTOCOL : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_NUMBER : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_SIZE : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_SYNCEXT : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_SYNCHRO : stm32h7xx_hal_sai.h
  • IS_SAI_BLOCK_TRISTATE_MANAGEMENT : stm32h7xx_hal_sai.h
  • IS_SAI_MONO_STEREO_MODE : stm32h7xx_hal_sai.h
  • IS_SAI_PDM_CLOCK_ENABLE : stm32h7xx_hal_sai.h
  • IS_SAI_PDM_MIC_DELAY : stm32h7xx_hal_sai_ex.h
  • IS_SAI_PDM_MIC_PAIRS_NUMBER : stm32h7xx_hal_sai.h
  • IS_SAI_PROTOCOL_DATASIZE : stm32h7xx_hal_sai.h
  • IS_SAI_SLOT_ACTIVE : stm32h7xx_hal_sai.h
  • IS_SAI_SUPPORTED_PROTOCOL : stm32h7xx_hal_sai.h
  • IS_SMARTCARD_ADVFEATURE_DATAINV : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_DMAONRXERROR : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_INIT : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_MSBFIRST : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_RXINV : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_SWAP : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_TXINV : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_AUTORETRY_COUNT : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_BAUDRATE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_BLOCKLENGTH : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_FIFO_MODE_STATE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_LASTBIT : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_MODE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_NACK : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_ONE_BIT_SAMPLE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_OVERRUN : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_PARITY : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_PHASE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_POLARITY : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_REQUEST_PARAMETER : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_RXFIFO_THRESHOLD : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_STOPBITS : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT_VALUE : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_TRANSMISSION_COMPLETION : stm32h7xx_hal_smartcard_ex.h
  • IS_SMARTCARD_TXFIFO_THRESHOLD : stm32h7xx_hal_smartcard.h
  • IS_SMARTCARD_WORD_LENGTH : stm32h7xx_hal_smartcard.h
  • IS_SMBUS_ADDRESSING_MODE : stm32h7xx_hal_smbus.h
  • IS_SMBUS_ANALOG_FILTER : stm32h7xx_hal_smbus.h
  • IS_SMBUS_DUAL_ADDRESS : stm32h7xx_hal_smbus.h
  • IS_SMBUS_GENERAL_CALL : stm32h7xx_hal_smbus.h
  • IS_SMBUS_NO_STRETCH : stm32h7xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS1 : stm32h7xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2 : stm32h7xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2_MASK : stm32h7xx_hal_smbus.h
  • IS_SMBUS_PEC : stm32h7xx_hal_smbus.h
  • IS_SMBUS_PERIPHERAL_MODE : stm32h7xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_MODE : stm32h7xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OPTIONS_REQUEST : stm32h7xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST : stm32h7xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_REQUEST : stm32h7xx_hal_smbus.h
  • IS_SPDIFRX_CHANNEL : stm32h7xx_hal_spdifrx.h
  • IS_SPDIFRX_DATA_FORMAT : stm32h7xx_hal_spdifrx.h
  • IS_SPDIFRX_INPUT_SELECT : stm32h7xx_hal_spdifrx.h
  • IS_SPDIFRX_MAX_RETRIES : stm32h7xx_hal_spdifrx.h
  • IS_SPDIFRX_WAIT_FOR_ACTIVITY : stm32h7xx_hal_spdifrx.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32h7xx_hal_spi.h
  • IS_SPI_CPHA : stm32h7xx_hal_spi.h
  • IS_SPI_CPOL : stm32h7xx_hal_spi.h
  • IS_SPI_CRC_CALCULATION : stm32h7xx_hal_spi.h
  • IS_SPI_CRC_INITIALIZATION_PATTERN : stm32h7xx_hal_spi.h
  • IS_SPI_CRC_LENGTH : stm32h7xx_hal_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32h7xx_hal_spi.h
  • IS_SPI_DATASIZE : stm32h7xx_hal_spi.h
  • IS_SPI_DIRECTION : stm32h7xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES : stm32h7xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY : stm32h7xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY : stm32h7xx_hal_spi.h
  • IS_SPI_FIFOTHRESHOLD : stm32h7xx_hal_spi.h
  • IS_SPI_FIRST_BIT : stm32h7xx_hal_spi.h
  • IS_SPI_MODE : stm32h7xx_hal_spi.h
  • IS_SPI_NSS : stm32h7xx_hal_spi.h
  • IS_SPI_NSSP : stm32h7xx_hal_spi.h
  • IS_SPI_TIMODE : stm32h7xx_hal_spi.h
  • IS_SPI_UNDERRUN_BEHAVIOUR : stm32h7xx_hal_spi.h
  • IS_SPI_UNDERRUN_DETECTION : stm32h7xx_hal_spi.h
  • IS_STEREO_MODE : stm32h7xx_hal_spdifrx.h
  • IS_SWPMI_BITRATE_VALUE : stm32h7xx_hal_swpmi.h
  • IS_SWPMI_RX_BUFFERING_MODE : stm32h7xx_hal_swpmi.h
  • IS_SWPMI_TX_BUFFERING_MODE : stm32h7xx_hal_swpmi.h
  • IS_SWPMI_VOLTAGE_CLASS : stm32h7xx_hal_swpmi.h
  • IS_SYSCFG_ANALOG_SWITCH : stm32h7xx_hal.h
  • IS_SYSCFG_BOOT_ADDRESS : stm32h7xx_hal.h
  • IS_SYSCFG_BOOT_REGISTER : stm32h7xx_hal.h
  • IS_SYSCFG_CODE_CONFIG : stm32h7xx_hal.h
  • IS_SYSCFG_CODE_SELECT : stm32h7xx_hal.h
  • IS_SYSCFG_ETHERNET_CONFIG : stm32h7xx_hal.h
  • IS_SYSCFG_SWITCH_STATE : stm32h7xx_hal.h
  • IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE : stm32h7xx_hal.h
  • IS_SYSCFG_VREFBUF_TRIMMING : stm32h7xx_hal.h
  • IS_SYSCFG_VREFBUF_VOLTAGE_SCALE : stm32h7xx_hal.h
  • IS_SYSTICK_CLK_SOURCE : stm32h7xx_hal_cortex.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_AUTORELOAD_PRELOAD : stm32h7xx_hal_tim.h
  • IS_TIM_BKR2REMAP : stm32h7xx_hal_tim_ex.h
  • IS_TIM_BKRREMAP : stm32h7xx_hal_tim_ex.h
  • IS_TIM_BREAK2_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK2_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK_FILTER : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_BREAK_SYSTEM : stm32h7xx_hal_tim.h
  • IS_TIM_BREAKINPUT : stm32h7xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE : stm32h7xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_POLARITY : stm32h7xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_STATE : stm32h7xx_hal_tim_ex.h
  • IS_TIM_CHANNELS : stm32h7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_FILTER : stm32h7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_PRESCALER : stm32h7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_SOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_CLOCKDIVISION_DIV : stm32h7xx_hal_tim.h
  • IS_TIM_CLOCKFILTER : stm32h7xx_hal_tim.h
  • IS_TIM_CLOCKPOLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_CLOCKPRESCALER : stm32h7xx_hal_tim.h
  • IS_TIM_CLOCKSOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_COMPLEMENTARY_CHANNELS : stm32h7xx_hal_tim.h
  • IS_TIM_COUNTER_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_DEADTIME : stm32h7xx_hal_tim.h
  • IS_TIM_DMA_BASE : stm32h7xx_hal_tim.h
  • IS_TIM_DMA_LENGTH : stm32h7xx_hal_tim.h
  • IS_TIM_DMA_SOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_ENCODER_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_ETRREMAP : stm32h7xx_hal_tim_ex.h
  • IS_TIM_EVENT_SOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_FAST_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_GROUPCH5 : stm32h7xx_hal_tim.h
  • IS_TIM_IC_FILTER : stm32h7xx_hal_tim.h
  • IS_TIM_IC_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_IC_PRESCALER : stm32h7xx_hal_tim.h
  • IS_TIM_IC_SELECTION : stm32h7xx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION : stm32h7xx_hal_tim.h
  • IS_TIM_LOCK_LEVEL : stm32h7xx_hal_tim.h
  • IS_TIM_MSM_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_OC_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_OC_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_OCIDLE_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_OCN_POLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_OPM_CHANNELS : stm32h7xx_hal_tim.h
  • IS_TIM_OPM_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_OSSI_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_OSSR_STATE : stm32h7xx_hal_tim.h
  • IS_TIM_PWM_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_REMAP : stm32h7xx_hal_tim_ex.h
  • IS_TIM_SLAVE_MODE : stm32h7xx_hal_tim.h
  • IS_TIM_TI1SELECTION : stm32h7xx_hal_tim.h
  • IS_TIM_TISEL : stm32h7xx_hal_tim_ex.h
  • IS_TIM_TRGO2_SOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_TRGO_SOURCE : stm32h7xx_hal_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32h7xx_hal_tim.h
  • IS_TIM_TRIGGERFILTER : stm32h7xx_hal_tim.h
  • IS_TIM_TRIGGERPOLARITY : stm32h7xx_hal_tim.h
  • IS_TIM_TRIGGERPRESCALER : stm32h7xx_hal_tim.h
  • IS_TIMESTAMP_EDGE : stm32h7xx_hal_rtc_ex.h
  • IS_TRANSFER_MODE : stm32h7xx_hal_i2c.h
  • IS_TRANSFER_REQUEST : stm32h7xx_hal_i2c.h
  • IS_UART_ADDRESSLENGTH_DETECT : stm32h7xx_hal_uart_ex.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATE : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATEMODE : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_DATAINV : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_DMAONRXERROR : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_INIT : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_MSBFIRST : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_RXINV : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_STOPMODE : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_SWAP : stm32h7xx_hal_uart.h
  • IS_UART_ADVFEATURE_TXINV : stm32h7xx_hal_uart.h
  • IS_UART_ASSERTIONTIME : stm32h7xx_hal_uart.h
  • IS_UART_BAUDRATE : stm32h7xx_hal_uart.h
  • IS_UART_DE_POLARITY : stm32h7xx_hal_uart.h
  • IS_UART_DEASSERTIONTIME : stm32h7xx_hal_uart.h
  • IS_UART_DMA_RX : stm32h7xx_hal_uart.h
  • IS_UART_DMA_TX : stm32h7xx_hal_uart.h
  • IS_UART_FIFO_MODE_STATE : stm32h7xx_hal_uart.h
  • IS_UART_HALF_DUPLEX : stm32h7xx_hal_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : stm32h7xx_hal_uart.h
  • IS_UART_LIN : stm32h7xx_hal_uart.h
  • IS_UART_LIN_BREAK_DETECT_LENGTH : stm32h7xx_hal_uart.h
  • IS_UART_MODE : stm32h7xx_hal_uart.h
  • IS_UART_MUTE_MODE : stm32h7xx_hal_uart.h
  • IS_UART_ONE_BIT_SAMPLE : stm32h7xx_hal_uart.h
  • IS_UART_OVERRUN : stm32h7xx_hal_uart.h
  • IS_UART_OVERSAMPLING : stm32h7xx_hal_uart.h
  • IS_UART_PARITY : stm32h7xx_hal_uart.h
  • IS_UART_PRESCALER : stm32h7xx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT : stm32h7xx_hal_uart.h
  • IS_UART_REQUEST_PARAMETER : stm32h7xx_hal_uart.h
  • IS_UART_RXFIFO_THRESHOLD : stm32h7xx_hal_uart.h
  • IS_UART_STATE : stm32h7xx_hal_uart.h
  • IS_UART_STOPBITS : stm32h7xx_hal_uart.h
  • IS_UART_TXFIFO_THRESHOLD : stm32h7xx_hal_uart.h
  • IS_UART_WAKEUP_SELECTION : stm32h7xx_hal_uart.h
  • IS_UART_WAKEUPMETHOD : stm32h7xx_hal_uart.h
  • IS_UART_WORD_LENGTH : stm32h7xx_hal_uart_ex.h
  • IS_USART_BAUDRATE : stm32h7xx_hal_usart.h
  • IS_USART_CLOCK : stm32h7xx_hal_usart.h
  • IS_USART_FIFO_MODE_STATE : stm32h7xx_hal_usart.h
  • IS_USART_LASTBIT : stm32h7xx_hal_usart.h
  • IS_USART_MODE : stm32h7xx_hal_usart.h
  • IS_USART_NSS : stm32h7xx_hal_usart.h
  • IS_USART_OVERSAMPLING : stm32h7xx_hal_usart.h
  • IS_USART_PARITY : stm32h7xx_hal_usart.h
  • IS_USART_PHASE : stm32h7xx_hal_usart.h
  • IS_USART_POLARITY : stm32h7xx_hal_usart.h
  • IS_USART_PRESCALER : stm32h7xx_hal_usart.h
  • IS_USART_REQUEST_PARAMETER : stm32h7xx_hal_usart.h
  • IS_USART_RXFIFO_THRESHOLD : stm32h7xx_hal_usart.h
  • IS_USART_SLAVEMODE : stm32h7xx_hal_usart.h
  • IS_USART_STOPBITS : stm32h7xx_hal_usart.h
  • IS_USART_TXFIFO_THRESHOLD : stm32h7xx_hal_usart.h
  • IS_USART_WORD_LENGTH : stm32h7xx_hal_usart_ex.h
  • IS_VALIDITY_MASK : stm32h7xx_hal_spdifrx.h
  • IS_VOLTAGERANGE : stm32h7xx_hal_flash_ex.h
  • IS_WRPSTATE : stm32h7xx_hal_flash_ex.h
  • IS_WWDG_COUNTER : stm32h7xx_hal_wwdg.h
  • IS_WWDG_EWI_MODE : stm32h7xx_hal_wwdg.h
  • IS_WWDG_PRESCALER : stm32h7xx_hal_wwdg.h
  • IS_WWDG_WINDOW : stm32h7xx_hal_wwdg.h
  • IWDG_DISABLE_WRITE_ACCESS : stm32h7xx_hal_iwdg.h
  • IWDG_ENABLE_WRITE_ACCESS : stm32h7xx_hal_iwdg.h
  • IWDG_KEY_ENABLE : stm32h7xx_hal_iwdg.h
  • IWDG_KEY_RELOAD : stm32h7xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_DISABLE : stm32h7xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_ENABLE : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_128 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_16 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_256 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_32 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_4 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_64 : stm32h7xx_hal_iwdg.h
  • IWDG_PRESCALER_8 : stm32h7xx_hal_iwdg.h
  • IWDG_WINDOW_DISABLE : stm32h7xx_hal_iwdg.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • a
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- j -

  • JPEG_420_SUBSAMPLING : stm32h7xx_hal_jpeg.h
  • JPEG_422_SUBSAMPLING : stm32h7xx_hal_jpeg.h
  • JPEG_444_SUBSAMPLING : stm32h7xx_hal_jpeg.h
  • JPEG_AC_HUFF_TABLE_SIZE : stm32h7xx_hal_jpeg.c
  • JPEG_CMYK_COLORSPACE : stm32h7xx_hal_jpeg.h
  • JPEG_CONTEXT_CONF_ENCODING : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_CUSTOM_TABLES : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_DECODE : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_DMA : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_ENCODE : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_ENDING_DMA : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_IT : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_METHOD_MASK : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_OPERATION_MASK : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_PAUSE_INPUT : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_PAUSE_OUTPUT : stm32h7xx_hal_jpeg.c
  • JPEG_CONTEXT_POLLING : stm32h7xx_hal_jpeg.c
  • JPEG_DC_HUFF_TABLE_SIZE : stm32h7xx_hal_jpeg.c
  • JPEG_FIFO_SIZE : stm32h7xx_hal_jpeg.c
  • JPEG_FIFO_TH_SIZE : stm32h7xx_hal_jpeg.c
  • JPEG_FLAG_ALL : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_COF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_EOCF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_HPDF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_IFNFF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_IFTF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_OFNEF : stm32h7xx_hal_jpeg.h
  • JPEG_FLAG_OFTF : stm32h7xx_hal_jpeg.h
  • JPEG_GRAYSCALE_COLORSPACE : stm32h7xx_hal_jpeg.h
  • JPEG_IMAGE_QUALITY_MAX : stm32h7xx_hal_jpeg.h
  • JPEG_IMAGE_QUALITY_MIN : stm32h7xx_hal_jpeg.h
  • JPEG_INTERRUPT_MASK : stm32h7xx_hal_jpeg.c
  • JPEG_IT_EOC : stm32h7xx_hal_jpeg.h
  • JPEG_IT_HPD : stm32h7xx_hal_jpeg.h
  • JPEG_IT_IFNF : stm32h7xx_hal_jpeg.h
  • JPEG_IT_IFT : stm32h7xx_hal_jpeg.h
  • JPEG_IT_OFNE : stm32h7xx_hal_jpeg.h
  • JPEG_IT_OFT : stm32h7xx_hal_jpeg.h
  • JPEG_PAUSE_RESUME_INPUT : stm32h7xx_hal_jpeg.h
  • JPEG_PAUSE_RESUME_INPUT_OUTPUT : stm32h7xx_hal_jpeg.h
  • JPEG_PAUSE_RESUME_OUTPUT : stm32h7xx_hal_jpeg.h
  • JPEG_PROCESS_DONE : stm32h7xx_hal_jpeg.c
  • JPEG_PROCESS_ONGOING : stm32h7xx_hal_jpeg.c
  • JPEG_QUANT_TABLE_SIZE : stm32h7xx_hal_jpeg.h
  • JPEG_TIMEOUT_VALUE : stm32h7xx_hal_jpeg.c
  • JPEG_YCBCR_COLORSPACE : stm32h7xx_hal_jpeg.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • _
  • a
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- l -

  • LPTIM4_OUT_CLEAR : stm32h7xx_hal.h
  • LPTIM5_OUT_CLEAR : stm32h7xx_hal.h
  • LPTIM_ACTIVEEDGE_FALLING : stm32h7xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING : stm32h7xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING_FALLING : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_FALLING : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING_FALLING : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_2TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_4TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_8TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC : stm32h7xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_ULPTIM : stm32h7xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_EXTERNAL : stm32h7xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_INTERNAL : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_ARRM : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_ARROK : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_CMPM : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_CMPOK : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_DOWN : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_EXTTRIG : stm32h7xx_hal_lptim.h
  • LPTIM_FLAG_UP : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1 : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1_COMP2 : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP2 : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_GPIO : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_SAI1_FSA : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_SAI1_FSB : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_COMP2 : stm32h7xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_GPIO : stm32h7xx_hal_lptim.h
  • LPTIM_IT_ARRM : stm32h7xx_hal_lptim.h
  • LPTIM_IT_ARROK : stm32h7xx_hal_lptim.h
  • LPTIM_IT_CMPM : stm32h7xx_hal_lptim.h
  • LPTIM_IT_CMPOK : stm32h7xx_hal_lptim.h
  • LPTIM_IT_DOWN : stm32h7xx_hal_lptim.h
  • LPTIM_IT_EXTTRIG : stm32h7xx_hal_lptim.h
  • LPTIM_IT_UP : stm32h7xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_HIGH : stm32h7xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_LOW : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV1 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV128 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV16 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV2 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV32 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV4 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV64 : stm32h7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV8 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_2TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_4TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_8TRANSITIONS : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_0 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_1 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_2 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_3 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_4 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_5 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_6 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_7 : stm32h7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_SOFTWARE : stm32h7xx_hal_lptim.h
  • LPTIM_UPDATE_ENDOFPERIOD : stm32h7xx_hal_lptim.h
  • LPTIM_UPDATE_IMMEDIATE : stm32h7xx_hal_lptim.h
  • LSE_STARTUP_TIMEOUT : stm32h7xx_hal_conf.h
  • LSE_VALUE : stm32h7xx_hal_conf.h
  • LSI_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • LTDC_ALPHA : stm32h7xx_hal_ltdc.h
  • LTDC_BLENDING_FACTOR1_CA : stm32h7xx_hal_ltdc.h
  • LTDC_BLENDING_FACTOR1_PAxCA : stm32h7xx_hal_ltdc.h
  • LTDC_BLENDING_FACTOR2_CA : stm32h7xx_hal_ltdc.h
  • LTDC_BLENDING_FACTOR2_PAxCA : stm32h7xx_hal_ltdc.h
  • LTDC_COLOR : stm32h7xx_hal_ltdc.h
  • LTDC_COLOR_FRAME_BUFFER : stm32h7xx_hal_ltdc.h
  • LTDC_DEPOLARITY_AH : stm32h7xx_hal_ltdc.h
  • LTDC_DEPOLARITY_AL : stm32h7xx_hal_ltdc.h
  • LTDC_FLAG_FU : stm32h7xx_hal_ltdc.h
  • LTDC_FLAG_LI : stm32h7xx_hal_ltdc.h
  • LTDC_FLAG_RR : stm32h7xx_hal_ltdc.h
  • LTDC_FLAG_TE : stm32h7xx_hal_ltdc.h
  • LTDC_HORIZONTALSYNC : stm32h7xx_hal_ltdc.h
  • LTDC_HSPOLARITY_AH : stm32h7xx_hal_ltdc.h
  • LTDC_HSPOLARITY_AL : stm32h7xx_hal_ltdc.h
  • LTDC_IT_FU : stm32h7xx_hal_ltdc.h
  • LTDC_IT_LI : stm32h7xx_hal_ltdc.h
  • LTDC_IT_RR : stm32h7xx_hal_ltdc.h
  • LTDC_IT_TE : stm32h7xx_hal_ltdc.h
  • LTDC_LAYER : stm32h7xx_hal_ltdc.h
  • LTDC_LAYER_1 : stm32h7xx_hal_ltdc.h
  • LTDC_LAYER_2 : stm32h7xx_hal_ltdc.h
  • LTDC_LINE_NUMBER : stm32h7xx_hal_ltdc.h
  • LTDC_PCPOLARITY_IIPC : stm32h7xx_hal_ltdc.h
  • LTDC_PCPOLARITY_IPC : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_AL44 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_AL88 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_ARGB1555 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_ARGB4444 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_ARGB8888 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_L8 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_RGB565 : stm32h7xx_hal_ltdc.h
  • LTDC_PIXEL_FORMAT_RGB888 : stm32h7xx_hal_ltdc.h
  • LTDC_RELOAD_IMMEDIATE : stm32h7xx_hal_ltdc.h
  • LTDC_RELOAD_VERTICAL_BLANKING : stm32h7xx_hal_ltdc.h
  • LTDC_STARTPOSITION : stm32h7xx_hal_ltdc.h
  • LTDC_STOPPOSITION : stm32h7xx_hal_ltdc.h
  • LTDC_VERTICALSYNC : stm32h7xx_hal_ltdc.h
  • LTDC_VSPOLARITY_AH : stm32h7xx_hal_ltdc.h
  • LTDC_VSPOLARITY_AL : stm32h7xx_hal_ltdc.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
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- m -

  • MAX_DMA2D_LAYER : stm32h7xx_hal_dma2d.h
  • MAX_HRTIM_TIMER : stm32h7xx_hal_hrtim.h
  • MAX_LAYER : stm32h7xx_hal_ltdc.h
  • MAX_NBYTE_SIZE : stm32h7xx_hal_i2c.c , stm32h7xx_hal_smbus.c
  • MC_ADDRESS : stm32h7xx_hal_nor.h
  • MCO1_GPIO_PORT : stm32h7xx_hal_rcc.c
  • MCO1_PIN : stm32h7xx_hal_rcc.c
  • MCO2_GPIO_PORT : stm32h7xx_hal_rcc.c
  • MCO2_PIN : stm32h7xx_hal_rcc.c
  • MDIOS_ALL_ERRORS_FLAG : stm32h7xx_hal_mdios.c
  • MDIOS_ALL_REG_FLAG : stm32h7xx_hal_mdios.c
  • MDIOS_ALLREG_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_DIN_BASE_ADDR : stm32h7xx_hal_mdios.c
  • MDIOS_DOUT_BASE_ADDR : stm32h7xx_hal_mdios.c
  • MDIOS_IT_ERROR : stm32h7xx_hal_mdios.h
  • MDIOS_IT_READ : stm32h7xx_hal_mdios.h
  • MDIOS_IT_WRITE : stm32h7xx_hal_mdios.h
  • MDIOS_PORT_ADDRESS_SHIFT : stm32h7xx_hal_mdios.c
  • MDIOS_PREAMBLE_CHECK_DISABLE : stm32h7xx_hal_mdios.h
  • MDIOS_PREAMBLE_CHECK_ENABLE : stm32h7xx_hal_mdios.h
  • MDIOS_PREAMBLE_ERROR_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG0 : stm32h7xx_hal_mdios.h
  • MDIOS_REG0_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG1 : stm32h7xx_hal_mdios.h
  • MDIOS_REG10 : stm32h7xx_hal_mdios.h
  • MDIOS_REG10_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG11 : stm32h7xx_hal_mdios.h
  • MDIOS_REG11_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG12 : stm32h7xx_hal_mdios.h
  • MDIOS_REG12_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG13 : stm32h7xx_hal_mdios.h
  • MDIOS_REG13_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG14 : stm32h7xx_hal_mdios.h
  • MDIOS_REG14_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG15 : stm32h7xx_hal_mdios.h
  • MDIOS_REG15_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG16 : stm32h7xx_hal_mdios.h
  • MDIOS_REG16_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG17 : stm32h7xx_hal_mdios.h
  • MDIOS_REG17_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG18 : stm32h7xx_hal_mdios.h
  • MDIOS_REG18_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG19 : stm32h7xx_hal_mdios.h
  • MDIOS_REG19_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG1_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG2 : stm32h7xx_hal_mdios.h
  • MDIOS_REG20 : stm32h7xx_hal_mdios.h
  • MDIOS_REG20_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG21 : stm32h7xx_hal_mdios.h
  • MDIOS_REG21_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG22 : stm32h7xx_hal_mdios.h
  • MDIOS_REG22_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG23 : stm32h7xx_hal_mdios.h
  • MDIOS_REG23_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG24 : stm32h7xx_hal_mdios.h
  • MDIOS_REG24_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG25 : stm32h7xx_hal_mdios.h
  • MDIOS_REG25_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG26 : stm32h7xx_hal_mdios.h
  • MDIOS_REG26_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG27 : stm32h7xx_hal_mdios.h
  • MDIOS_REG27_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG28 : stm32h7xx_hal_mdios.h
  • MDIOS_REG28_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG29 : stm32h7xx_hal_mdios.h
  • MDIOS_REG29_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG2_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG3 : stm32h7xx_hal_mdios.h
  • MDIOS_REG30 : stm32h7xx_hal_mdios.h
  • MDIOS_REG30_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG31 : stm32h7xx_hal_mdios.h
  • MDIOS_REG31_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG3_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG4 : stm32h7xx_hal_mdios.h
  • MDIOS_REG4_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG5 : stm32h7xx_hal_mdios.h
  • MDIOS_REG5_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG6 : stm32h7xx_hal_mdios.h
  • MDIOS_REG6_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG7 : stm32h7xx_hal_mdios.h
  • MDIOS_REG7_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG8 : stm32h7xx_hal_mdios.h
  • MDIOS_REG8_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_REG9 : stm32h7xx_hal_mdios.h
  • MDIOS_REG9_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_START_ERROR_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_TURNAROUND_ERROR_FLAG : stm32h7xx_hal_mdios.h
  • MDIOS_WAKEUP_EXTI_LINE : stm32h7xx_hal_mdios.h
  • MDMA_BLOCK_TRANSFER : stm32h7xx_hal_mdma.h
  • MDMA_BUFFER_TRANSFER : stm32h7xx_hal_mdma.h
  • MDMA_DATAALIGN_LEFT : stm32h7xx_hal_mdma.h
  • MDMA_DATAALIGN_PACKENABLE : stm32h7xx_hal_mdma.h
  • MDMA_DATAALIGN_RIGHT : stm32h7xx_hal_mdma.h
  • MDMA_DATAALIGN_RIGHT_SIGNED : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_128BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_16BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_2BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_32BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_4BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_64BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_8BEATS : stm32h7xx_hal_mdma.h
  • MDMA_DEST_BURST_SINGLE : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DATASIZE_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DATASIZE_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DATASIZE_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DATASIZE_WORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DEC_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DEC_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DEC_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_DEC_WORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_INC_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_DEST_INC_DISABLE : stm32h7xx_hal_mdma.h
  • MDMA_DEST_INC_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_INC_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_DEST_INC_WORD : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_BFTC : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_BRT : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_BT : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_CRQA : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_CTC : stm32h7xx_hal_mdma.h
  • MDMA_FLAG_TE : stm32h7xx_hal_mdma.h
  • MDMA_FULL_TRANSFER : stm32h7xx_hal_mdma.h
  • MDMA_IT_BFTC : stm32h7xx_hal_mdma.h
  • MDMA_IT_BRT : stm32h7xx_hal_mdma.h
  • MDMA_IT_BT : stm32h7xx_hal_mdma.h
  • MDMA_IT_CTC : stm32h7xx_hal_mdma.h
  • MDMA_IT_TE : stm32h7xx_hal_mdma.h
  • MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE : stm32h7xx_hal_mdma.h
  • MDMA_LITTLE_ENDIANNESS_PRESERVE : stm32h7xx_hal_mdma.h
  • MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE : stm32h7xx_hal_mdma.h
  • MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE : stm32h7xx_hal_mdma.h
  • MDMA_PRIORITY_HIGH : stm32h7xx_hal_mdma.h
  • MDMA_PRIORITY_LOW : stm32h7xx_hal_mdma.h
  • MDMA_PRIORITY_MEDIUM : stm32h7xx_hal_mdma.h
  • MDMA_PRIORITY_VERY_HIGH : stm32h7xx_hal_mdma.h
  • MDMA_REPEAT_BLOCK_TRANSFER : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream0_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream1_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream2_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream3_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream4_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream5_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream6_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA1_Stream7_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream0_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream1_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream2_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream3_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream4_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream5_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream6_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2_Stream7_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2D_CLUT_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2D_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_DMA2D_TW : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_JPEG_END_CONVERSION : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_JPEG_INFIFO_NF : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_JPEG_INFIFO_TH : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_JPEG_OUTFIFO_NE : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_JPEG_OUTFIFO_TH : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_LTDC_LINE_IT : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_QUADSPI_FIFO_TH : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_QUADSPI_TC : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_SDMMC1_END_DATA : stm32h7xx_hal_mdma.h
  • MDMA_REQUEST_SW : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_128BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_16BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_2BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_32BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_4BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_64BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_8BEATS : stm32h7xx_hal_mdma.h
  • MDMA_SOURCE_BURST_SINGLE : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DATASIZE_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DATASIZE_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DATASIZE_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DATASIZE_WORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DEC_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DEC_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DEC_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_DEC_WORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_INC_BYTE : stm32h7xx_hal_mdma.h
  • MDMA_SRC_INC_DISABLE : stm32h7xx_hal_mdma.h
  • MDMA_SRC_INC_DOUBLEWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_INC_HALFWORD : stm32h7xx_hal_mdma.h
  • MDMA_SRC_INC_WORD : stm32h7xx_hal_mdma.h
  • MMC_CONTEXT_DMA : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_IT : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_NONE : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_READ_MULTIPLE_BLOCK : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_READ_SINGLE_BLOCK : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_WRITE_MULTIPLE_BLOCK : stm32h7xx_hal_mmc.h
  • MMC_CONTEXT_WRITE_SINGLE_BLOCK : stm32h7xx_hal_mmc.h
  • MMC_DUAL_VOLTAGE_RANGE : stm32h7xx_hal_mmc.h
  • MMC_HIGH_CAPACITY_CARD : stm32h7xx_hal_mmc.h
  • MMC_HIGH_VOLTAGE_RANGE : stm32h7xx_hal_mmc.h
  • MMC_InitTypeDef : stm32h7xx_hal_mmc.h
  • MMC_INVALID_VOLTAGE_RANGE : stm32h7xx_hal_mmc.h
  • MMC_LOW_CAPACITY_CARD : stm32h7xx_hal_mmc.h
  • MMC_TypeDef : stm32h7xx_hal_mmc.h
  • MPU_ACCESS_BUFFERABLE : stm32h7xx_hal_cortex.h
  • MPU_ACCESS_CACHEABLE : stm32h7xx_hal_cortex.h
  • MPU_ACCESS_NOT_BUFFERABLE : stm32h7xx_hal_cortex.h
  • MPU_ACCESS_NOT_CACHEABLE : stm32h7xx_hal_cortex.h
  • MPU_ACCESS_NOT_SHAREABLE : stm32h7xx_hal_cortex.h
  • MPU_ACCESS_SHAREABLE : stm32h7xx_hal_cortex.h
  • MPU_HARDFAULT_NMI : stm32h7xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF : stm32h7xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF_NONE : stm32h7xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_DISABLE : stm32h7xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_ENABLE : stm32h7xx_hal_cortex.h
  • MPU_PRIVILEGED_DEFAULT : stm32h7xx_hal_cortex.h
  • MPU_REGION_DISABLE : stm32h7xx_hal_cortex.h
  • MPU_REGION_ENABLE : stm32h7xx_hal_cortex.h
  • MPU_REGION_FULL_ACCESS : stm32h7xx_hal_cortex.h
  • MPU_REGION_NO_ACCESS : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER0 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER1 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER2 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER3 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER4 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER5 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER6 : stm32h7xx_hal_cortex.h
  • MPU_REGION_NUMBER7 : stm32h7xx_hal_cortex.h
  • MPU_REGION_PRIV_RO : stm32h7xx_hal_cortex.h
  • MPU_REGION_PRIV_RO_URO : stm32h7xx_hal_cortex.h
  • MPU_REGION_PRIV_RW : stm32h7xx_hal_cortex.h
  • MPU_REGION_PRIV_RW_URO : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_128B : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_128KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_128MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_16KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_16MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_1GB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_1KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_1MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_256B : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_256KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_256MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_2GB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_2KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_2MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_32B : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_32KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_32MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_4GB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_4KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_4MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_512B : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_512KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_512MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_64B : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_64KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_64MB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_8KB : stm32h7xx_hal_cortex.h
  • MPU_REGION_SIZE_8MB : stm32h7xx_hal_cortex.h
  • MPU_TEX_LEVEL0 : stm32h7xx_hal_cortex.h
  • MPU_TEX_LEVEL1 : stm32h7xx_hal_cortex.h
  • MPU_TEX_LEVEL2 : stm32h7xx_hal_cortex.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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- n -

  • NAND_BUSY : stm32h7xx_hal_nand.h
  • NAND_CMD_AREA_A : stm32h7xx_hal_nand.h
  • NAND_CMD_AREA_B : stm32h7xx_hal_nand.h
  • NAND_CMD_AREA_C : stm32h7xx_hal_nand.h
  • NAND_CMD_AREA_TRUE1 : stm32h7xx_hal_nand.h
  • NAND_CMD_ERASE0 : stm32h7xx_hal_nand.h
  • NAND_CMD_ERASE1 : stm32h7xx_hal_nand.h
  • NAND_CMD_LOCK_STATUS : stm32h7xx_hal_nand.h
  • NAND_CMD_READID : stm32h7xx_hal_nand.h
  • NAND_CMD_RESET : stm32h7xx_hal_nand.h
  • NAND_CMD_STATUS : stm32h7xx_hal_nand.h
  • NAND_CMD_WRITE0 : stm32h7xx_hal_nand.h
  • NAND_CMD_WRITE_TRUE1 : stm32h7xx_hal_nand.h
  • NAND_DEVICE : stm32h7xx_hal_nand.h
  • NAND_ERROR : stm32h7xx_hal_nand.h
  • NAND_INVALID_ADDRESS : stm32h7xx_hal_nand.h
  • NAND_READY : stm32h7xx_hal_nand.h
  • NAND_TIMEOUT_ERROR : stm32h7xx_hal_nand.h
  • NAND_VALID_ADDRESS : stm32h7xx_hal_nand.h
  • NAND_WRITE_TIMEOUT : stm32h7xx_hal_nand.h
  • NOR_ADDR_SHIFT : stm32h7xx_hal_nor.h
  • NOR_CMD_ADDRESS_FIFTH : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_FIRST : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_FIRST_CFI : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_FOURTH : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_SECOND : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_SIXTH : stm32h7xx_hal_nor.c
  • NOR_CMD_ADDRESS_THIRD : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_AUTO_SELECT : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_BLOCK_ERASE : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_BUFFER_AND_PROG : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_CFI : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_ERASE : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_FIRST : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_PROGRAM : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_READ_RESET : stm32h7xx_hal_nor.c
  • NOR_CMD_DATA_SECOND : stm32h7xx_hal_nor.c
  • NOR_MASK_STATUS_DQ5 : stm32h7xx_hal_nor.c
  • NOR_MASK_STATUS_DQ6 : stm32h7xx_hal_nor.c
  • NOR_MEMORY_16B : stm32h7xx_hal_nor.h
  • NOR_MEMORY_8B : stm32h7xx_hal_nor.h
  • NOR_MEMORY_ADRESS1 : stm32h7xx_hal_nor.h
  • NOR_MEMORY_ADRESS2 : stm32h7xx_hal_nor.h
  • NOR_MEMORY_ADRESS3 : stm32h7xx_hal_nor.h
  • NOR_MEMORY_ADRESS4 : stm32h7xx_hal_nor.h
  • NOR_TMEOUT : stm32h7xx_hal_nor.h
  • NOR_WRITE : stm32h7xx_hal_nor.h
  • NVIC_PRIORITYGROUP_0 : stm32h7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_1 : stm32h7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_2 : stm32h7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_3 : stm32h7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_4 : stm32h7xx_hal_cortex.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
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- o -

  • OB_BOOT_ADD0 : stm32h7xx_hal_flash_ex.h
  • OB_BOOT_ADD1 : stm32h7xx_hal_flash_ex.h
  • OB_BOOT_ADD_BOTH : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_AXIM_FLASH : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_DTCM_RAM : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_ITCM_FLASH : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_ITCM_RAM : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_SRAM1 : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_SRAM2 : stm32h7xx_hal_flash_ex.h
  • OB_BOOTADDR_SYSTEM : stm32h7xx_hal_flash_ex.h
  • OB_BOR_LEVEL1 : stm32h7xx_hal_flash_ex.h
  • OB_BOR_LEVEL2 : stm32h7xx_hal_flash_ex.h
  • OB_BOR_LEVEL3 : stm32h7xx_hal_flash_ex.h
  • OB_BOR_OFF : stm32h7xx_hal_flash_ex.h
  • OB_IOHSLV_DISABLE : stm32h7xx_hal_flash_ex.h
  • OB_IOHSLV_ENABLE : stm32h7xx_hal_flash_ex.h
  • OB_IWDG1_HW : stm32h7xx_hal_flash_ex.h
  • OB_IWDG1_SW : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_HW : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_STDBY_ACTIVE : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_STDBY_FREEZE : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_STOP_ACTIVE : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_STOP_FREEZE : stm32h7xx_hal_flash_ex.h
  • OB_IWDG_SW : stm32h7xx_hal_flash_ex.h
  • OB_PCROP_RDP_ERASE : stm32h7xx_hal_flash_ex.h
  • OB_PCROP_RDP_NOT_ERASE : stm32h7xx_hal_flash_ex.h
  • OB_RDP_LEVEL_0 : stm32h7xx_hal_flash_ex.h
  • OB_RDP_LEVEL_1 : stm32h7xx_hal_flash_ex.h
  • OB_RDP_LEVEL_2 : stm32h7xx_hal_flash_ex.h
  • OB_SECURE_RDP_ERASE : stm32h7xx_hal_flash_ex.h
  • OB_SECURE_RDP_NOT_ERASE : stm32h7xx_hal_flash_ex.h
  • OB_SECURITY_DISABLE : stm32h7xx_hal_flash_ex.h
  • OB_SECURITY_ENABLE : stm32h7xx_hal_flash_ex.h
  • OB_STDBY_NO_RST : stm32h7xx_hal_flash_ex.h
  • OB_STDBY_NO_RST_D1 : stm32h7xx_hal_flash_ex.h
  • OB_STDBY_RST : stm32h7xx_hal_flash_ex.h
  • OB_STDBY_RST_D1 : stm32h7xx_hal_flash_ex.h
  • OB_STOP_NO_RST : stm32h7xx_hal_flash_ex.h
  • OB_STOP_NO_RST_D1 : stm32h7xx_hal_flash_ex.h
  • OB_STOP_RST : stm32h7xx_hal_flash_ex.h
  • OB_STOP_RST_D1 : stm32h7xx_hal_flash_ex.h
  • OB_SWAP_BANK_DISABLE : stm32h7xx_hal_flash_ex.h
  • OB_SWAP_BANK_ENABLE : stm32h7xx_hal_flash_ex.h
  • OB_USER_IOHSLV : stm32h7xx_hal_flash_ex.h
  • OB_USER_IWDG1_SW : stm32h7xx_hal_flash_ex.h
  • OB_USER_IWDG_STDBY : stm32h7xx_hal_flash_ex.h
  • OB_USER_IWDG_STOP : stm32h7xx_hal_flash_ex.h
  • OB_USER_NRST_STDBY_D1 : stm32h7xx_hal_flash_ex.h
  • OB_USER_NRST_STOP_D1 : stm32h7xx_hal_flash_ex.h
  • OB_USER_SECURITY : stm32h7xx_hal_flash_ex.h
  • OB_USER_ST_RAM_SIZE : stm32h7xx_hal_flash_ex.h
  • OB_USER_SWAP_BANK : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_0 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_1 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_2 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_3 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_4 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_5 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_6 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_7 : stm32h7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_All : stm32h7xx_hal_flash_ex.h
  • OB_WRPSTATE_DISABLE : stm32h7xx_hal_flash_ex.h
  • OB_WRPSTATE_ENABLE : stm32h7xx_hal_flash_ex.h
  • OB_WWDG_HW : stm32h7xx_hal_flash_ex.h
  • OB_WWDG_SW : stm32h7xx_hal_flash_ex.h
  • OPAMP_CSR_INIT_MASK_FOLLOWER : stm32h7xx_hal_opamp.c
  • OPAMP_CSR_INIT_MASK_PGA : stm32h7xx_hal_opamp.c
  • OPAMP_CSR_INIT_MASK_STANDALONE : stm32h7xx_hal_opamp.c
  • OPAMP_CSR_RESET_BITS : stm32h7xx_hal_opamp.c
  • OPAMP_CSR_RESET_VALUE : stm32h7xx_hal_opamp.c
  • OPAMP_FACTORYTRIMMING_DUMMY : stm32h7xx_hal_opamp.h
  • OPAMP_FACTORYTRIMMING_N : stm32h7xx_hal_opamp.h
  • OPAMP_FACTORYTRIMMING_P : stm32h7xx_hal_opamp.h
  • OPAMP_FOLLOWER_MODE : stm32h7xx_hal_opamp.h
  • OPAMP_INPUT_NONINVERTING : stm32h7xx_hal_opamp.h
  • OPAMP_INVERTINGINPUT_IO0 : stm32h7xx_hal_opamp.h
  • OPAMP_INVERTINGINPUT_IO1 : stm32h7xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_DAC_CH : stm32h7xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_IO0 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_NO : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_GAIN_16_OR_MINUS_15 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_GAIN_2_OR_MINUS_1 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_GAIN_4_OR_MINUS_3 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_GAIN_8_OR_MINUS_7 : stm32h7xx_hal_opamp.h
  • OPAMP_PGA_MODE : stm32h7xx_hal_opamp.h
  • OPAMP_POWERMODE_HIGHSPEED : stm32h7xx_hal_opamp.h
  • OPAMP_POWERMODE_NORMAL : stm32h7xx_hal_opamp.h
  • OPAMP_STANDALONE_MODE : stm32h7xx_hal_opamp.h
  • OPAMP_TRIMMING_DELAY : stm32h7xx_hal_opamp.h
  • OPAMP_TRIMMING_FACTORY : stm32h7xx_hal_opamp.h
  • OPAMP_TRIMMING_USER : stm32h7xx_hal_opamp.h
  • OPAMP_VREF_10VDDA : stm32h7xx_hal_opamp.h
  • OPAMP_VREF_3VDDA : stm32h7xx_hal_opamp.h
  • OPAMP_VREF_50VDDA : stm32h7xx_hal_opamp.h
  • OPAMP_VREF_90VDDA : stm32h7xx_hal_opamp.h
  • OPTIONBYTE_BOOTADD : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_BOR : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_PCROP : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_RDP : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_SECURE_AREA : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_USER : stm32h7xx_hal_flash_ex.h
  • OPTIONBYTE_WRP : stm32h7xx_hal_flash_ex.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
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- p -

  • PCD_MAX : stm32h7xx_hal_pcd.c
  • PCD_MIN : stm32h7xx_hal_pcd.c
  • PCD_PHY_EMBEDDED : stm32h7xx_hal_pcd.h
  • PCD_PHY_ULPI : stm32h7xx_hal_pcd.h
  • PCD_SPEED_FULL : stm32h7xx_hal_pcd.h
  • PCD_SPEED_HIGH : stm32h7xx_hal_pcd.h
  • PCD_SPEED_HIGH_IN_FULL : stm32h7xx_hal_pcd.h
  • PLL2_TIMEOUT_VALUE : stm32h7xx_hal_rcc_ex.c
  • PLL3_TIMEOUT_VALUE : stm32h7xx_hal_rcc_ex.c
  • PLL_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h , stm32h7xx_hal_rcc_ex.c
  • PVD_FALLING_EDGE : stm32h7xx_hal_pwr.c
  • PVD_MODE_EVT : stm32h7xx_hal_pwr.c
  • PVD_MODE_IT : stm32h7xx_hal_pwr.c
  • PVD_RISING_EDGE : stm32h7xx_hal_pwr.c
  • PVD_RISING_FALLING_EDGE : stm32h7xx_hal_pwr.c
  • PWR_AVD_MODE_EVENT_FALLING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_EVENT_RISING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_EVENT_RISING_FALLING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_IT_FALLING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_IT_RISING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_IT_RISING_FALLING : stm32h7xx_hal_pwr_ex.h
  • PWR_AVD_MODE_NORMAL : stm32h7xx_hal_pwr_ex.h
  • PWR_AVDLEVEL_0 : stm32h7xx_hal_pwr_ex.h
  • PWR_AVDLEVEL_1 : stm32h7xx_hal_pwr_ex.h
  • PWR_AVDLEVEL_2 : stm32h7xx_hal_pwr_ex.h
  • PWR_AVDLEVEL_3 : stm32h7xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_1_5 : stm32h7xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_5 : stm32h7xx_hal_pwr_ex.h
  • PWR_CPU_FLAGS : stm32h7xx_hal_pwr_ex.h
  • PWR_D1_DOMAIN : stm32h7xx_hal_pwr_ex.h
  • PWR_D2_DOMAIN : stm32h7xx_hal_pwr_ex.h
  • PWR_D3_DOMAIN : stm32h7xx_hal_pwr_ex.h
  • PWR_D3_DOMAIN_RUN : stm32h7xx_hal_pwr_ex.h
  • PWR_D3_DOMAIN_STOP : stm32h7xx_hal_pwr_ex.h
  • PWR_EWUP_MASK : stm32h7xx_hal_pwr.h
  • PWR_EXTERNAL_SOURCE_SUPPLY : stm32h7xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_AVD : stm32h7xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVD : stm32h7xx_hal_pwr.h
  • PWR_EXTI_WAKEUP_PINS_MASK : stm32h7xx_hal_pwr_ex.h
  • PWR_FLAG_ACTVOS : stm32h7xx_hal_pwr.h
  • PWR_FLAG_ACTVOSRDY : stm32h7xx_hal_pwr.h
  • PWR_FLAG_AVDO : stm32h7xx_hal_pwr.h
  • PWR_FLAG_BRR : stm32h7xx_hal_pwr.h
  • PWR_FLAG_PVDO : stm32h7xx_hal_pwr.h
  • PWR_FLAG_SB : stm32h7xx_hal_pwr.h
  • PWR_FLAG_SB_D1 : stm32h7xx_hal_pwr.h
  • PWR_FLAG_SB_D2 : stm32h7xx_hal_pwr.h
  • PWR_FLAG_SCUEN : stm32h7xx_hal_pwr.h
  • PWR_FLAG_SETTING_DELAY_US : stm32h7xx_hal_pwr_ex.c
  • PWR_FLAG_STOP : stm32h7xx_hal_pwr.h
  • PWR_FLAG_VOSRDY : stm32h7xx_hal_pwr.h
  • PWR_LDO_SUPPLY : stm32h7xx_hal_pwr_ex.h
  • PWR_LOWPOWERREGULATOR_ON : stm32h7xx_hal_pwr.h
  • PWR_MAINREGULATOR_ON : stm32h7xx_hal_pwr.h
  • PWR_PIN_NO_PULL : stm32h7xx_hal_pwr_ex.h
  • PWR_PIN_POLARITY_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_PIN_POLARITY_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_PIN_PULL_DOWN : stm32h7xx_hal_pwr_ex.h
  • PWR_PIN_PULL_UP : stm32h7xx_hal_pwr_ex.h
  • PWR_PVD_MODE_EVENT_FALLING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING_FALLING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_IT_FALLING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING_FALLING : stm32h7xx_hal_pwr.h
  • PWR_PVD_MODE_NORMAL : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_0 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_1 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_2 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_3 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_4 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_5 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_6 : stm32h7xx_hal_pwr.h
  • PWR_PVDLEVEL_7 : stm32h7xx_hal_pwr.h
  • PWR_REGULATOR_SVOS_SCALE3 : stm32h7xx_hal_pwr_ex.h
  • PWR_REGULATOR_SVOS_SCALE4 : stm32h7xx_hal_pwr_ex.h
  • PWR_REGULATOR_SVOS_SCALE5 : stm32h7xx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE1 : stm32h7xx_hal_pwr.h
  • PWR_REGULATOR_VOLTAGE_SCALE2 : stm32h7xx_hal_pwr.h
  • PWR_REGULATOR_VOLTAGE_SCALE3 : stm32h7xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFE : stm32h7xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFI : stm32h7xx_hal_pwr.h
  • PWR_STOPENTRY_WFE : stm32h7xx_hal_pwr.h
  • PWR_STOPENTRY_WFI : stm32h7xx_hal_pwr.h
  • PWR_SUPPLY_CONFIG_MASK : stm32h7xx_hal_pwr_ex.h
  • PWR_TEMP_ABOVE_HIGH_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_TEMP_BELOW_LOW_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_VBAT_ABOVE_HIGH_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_VBAT_BELOW_LOW_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG1 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG2 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG3 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG4 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG5 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_FLAG6 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_LOW : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN6 : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN6_HIGH : stm32h7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN6_LOW : stm32h7xx_hal_pwr_ex.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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- q -

  • QSPI_ADDRESS_16_BITS : stm32h7xx_hal_qspi.h
  • QSPI_ADDRESS_1_LINE : stm32h7xx_hal_qspi.h
  • QSPI_ADDRESS_24_BITS : stm32h7xx_hal_qspi.h
  • QSPI_ADDRESS_2_LINES : stm32h7xx_hal_qspi.h
  • QSPI_ADDRESS_32_BITS : stm32h7xx_hal_qspi.h
  • QSPI_ADDRESS_4_LINES : stm32h7xx_hal_qspi.h
  • QSPI_ADDRESS_8_BITS : stm32h7xx_hal_qspi.h
  • QSPI_ADDRESS_NONE : stm32h7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_16_BITS : stm32h7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_1_LINE : stm32h7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_24_BITS : stm32h7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_2_LINES : stm32h7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_32_BITS : stm32h7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_4_LINES : stm32h7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_8_BITS : stm32h7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_NONE : stm32h7xx_hal_qspi.h
  • QSPI_AUTOMATIC_STOP_DISABLE : stm32h7xx_hal_qspi.h
  • QSPI_AUTOMATIC_STOP_ENABLE : stm32h7xx_hal_qspi.h
  • QSPI_CLOCK_MODE_0 : stm32h7xx_hal_qspi.h
  • QSPI_CLOCK_MODE_3 : stm32h7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_1_CYCLE : stm32h7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_2_CYCLE : stm32h7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_3_CYCLE : stm32h7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_4_CYCLE : stm32h7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_5_CYCLE : stm32h7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_6_CYCLE : stm32h7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_7_CYCLE : stm32h7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_8_CYCLE : stm32h7xx_hal_qspi.h
  • QSPI_DATA_1_LINE : stm32h7xx_hal_qspi.h
  • QSPI_DATA_2_LINES : stm32h7xx_hal_qspi.h
  • QSPI_DATA_4_LINES : stm32h7xx_hal_qspi.h
  • QSPI_DATA_NONE : stm32h7xx_hal_qspi.h
  • QSPI_DDR_HHC_ANALOG_DELAY : stm32h7xx_hal_qspi.h
  • QSPI_DDR_HHC_HALF_CLK_DELAY : stm32h7xx_hal_qspi.h
  • QSPI_DDR_MODE_DISABLE : stm32h7xx_hal_qspi.h
  • QSPI_DDR_MODE_ENABLE : stm32h7xx_hal_qspi.h
  • QSPI_DUALFLASH_DISABLE : stm32h7xx_hal_qspi.h
  • QSPI_DUALFLASH_ENABLE : stm32h7xx_hal_qspi.h
  • QSPI_FLAG_BUSY : stm32h7xx_hal_qspi.h
  • QSPI_FLAG_FT : stm32h7xx_hal_qspi.h
  • QSPI_FLAG_SM : stm32h7xx_hal_qspi.h
  • QSPI_FLAG_TC : stm32h7xx_hal_qspi.h
  • QSPI_FLAG_TE : stm32h7xx_hal_qspi.h
  • QSPI_FLAG_TO : stm32h7xx_hal_qspi.h
  • QSPI_FLASH_ID_1 : stm32h7xx_hal_qspi.h
  • QSPI_FLASH_ID_2 : stm32h7xx_hal_qspi.h
  • QSPI_FUNCTIONAL_MODE_AUTO_POLLING : stm32h7xx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_INDIRECT_READ : stm32h7xx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE : stm32h7xx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED : stm32h7xx_hal_qspi.c
  • QSPI_INSTRUCTION_1_LINE : stm32h7xx_hal_qspi.h
  • QSPI_INSTRUCTION_2_LINES : stm32h7xx_hal_qspi.h
  • QSPI_INSTRUCTION_4_LINES : stm32h7xx_hal_qspi.h
  • QSPI_INSTRUCTION_NONE : stm32h7xx_hal_qspi.h
  • QSPI_IT_FT : stm32h7xx_hal_qspi.h
  • QSPI_IT_SM : stm32h7xx_hal_qspi.h
  • QSPI_IT_TC : stm32h7xx_hal_qspi.h
  • QSPI_IT_TE : stm32h7xx_hal_qspi.h
  • QSPI_IT_TO : stm32h7xx_hal_qspi.h
  • QSPI_MATCH_MODE_AND : stm32h7xx_hal_qspi.h
  • QSPI_MATCH_MODE_OR : stm32h7xx_hal_qspi.h
  • QSPI_SAMPLE_SHIFTING_HALFCYCLE : stm32h7xx_hal_qspi.h
  • QSPI_SAMPLE_SHIFTING_NONE : stm32h7xx_hal_qspi.h
  • QSPI_SIOO_INST_EVERY_CMD : stm32h7xx_hal_qspi.h
  • QSPI_SIOO_INST_ONLY_FIRST_CMD : stm32h7xx_hal_qspi.h
  • QSPI_TIMEOUT_COUNTER_DISABLE : stm32h7xx_hal_qspi.h
  • QSPI_TIMEOUT_COUNTER_ENABLE : stm32h7xx_hal_qspi.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

  • File List
  • Globals
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  • Functions
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- r -

  • RCC_ADCCLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_APB1_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_APB1_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_APB1_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_APB1_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_APB1_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_APB2_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_APB2_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_APB2_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_APB2_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_APB2_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_APB3_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_APB3_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_APB3_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_APB3_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_APB3_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_APB4_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_APB4_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_APB4_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_APB4_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_APB4_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_CECCLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_CECCLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_CECCLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_CLKPSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_CLKPSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_CLKPSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_CLOCKTYPE_D1PCLK1 : stm32h7xx_hal_rcc.h
  • RCC_CLOCKTYPE_D3PCLK1 : stm32h7xx_hal_rcc.h
  • RCC_CLOCKTYPE_HCLK : stm32h7xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK1 : stm32h7xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK2 : stm32h7xx_hal_rcc.h
  • RCC_CLOCKTYPE_SYSCLK : stm32h7xx_hal_rcc.h
  • RCC_CRS_ERRORLIMIT_DEFAULT : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ERR : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ERROR_MASK : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ESYNC : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCERR : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCMISS : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCOK : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCWARN : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_TRIMOVF : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FREQERRORDIR_DOWN : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_FREQERRORDIR_UP : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_HSI48CALIBRATION_DEFAULT : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_ERR : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_ERROR_MASK : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_ESYNC : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCERR : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCMISS : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCOK : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCWARN : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_IT_TRIMOVF : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_NONE : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_RELOADVALUE_DEFAULT : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV1 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV128 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV16 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV2 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV32 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV4 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV64 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV8 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_POLARITY_FALLING : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_POLARITY_RISING : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_USB1 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_USB2 : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNCERR : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNCMISS : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNCOK : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_SYNCWARN : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_TIMEOUT : stm32h7xx_hal_rcc_ex.h
  • RCC_CRS_TRIMOVF : stm32h7xx_hal_rcc_ex.h
  • RCC_CSI_OFF : stm32h7xx_hal_rcc.h
  • RCC_CSI_ON : stm32h7xx_hal_rcc.h
  • RCC_CSICALIBRATION_DEFAULT : stm32h7xx_hal_rcc.h
  • RCC_DBP_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • RCC_DFSDM1CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_DFSDM1CLKSOURCE_SYS : stm32h7xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_FLAG_BORRST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_CPURST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_CSIRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_D1CKRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_D1RST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_D2CKRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_D2RST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_HSERDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_HSI48RDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_HSIDIV : stm32h7xx_hal_rcc.h
  • RCC_FLAG_HSIRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_IWDG1RST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_LPWR1RST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_LPWR2RST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_LSERDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_LSIRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_MASK : stm32h7xx_hal_rcc.h
  • RCC_FLAG_PINRST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_PLL2RDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_PLL3RDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_PLLRDY : stm32h7xx_hal_rcc.h
  • RCC_FLAG_PORRST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_RMVF : stm32h7xx_hal_rcc.h
  • RCC_FLAG_SFTRST : stm32h7xx_hal_rcc.h
  • RCC_FLAG_WWDG1RST : stm32h7xx_hal_rcc.h
  • RCC_FMCCLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_FMCCLKSOURCE_D1HCLK : stm32h7xx_hal_rcc_ex.h
  • RCC_FMCCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_FMCCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_GET_PLL_OSCSOURCE : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV128 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV256 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV512 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV64 : stm32h7xx_hal_rcc.h
  • RCC_HCLK_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_HRTIM1CLK_CPUCLK : stm32h7xx_hal_rcc_ex.h
  • RCC_HRTIM1CLK_TIMCLK : stm32h7xx_hal_rcc_ex.h
  • RCC_HSE_BYPASS : stm32h7xx_hal_rcc.h
  • RCC_HSE_OFF : stm32h7xx_hal_rcc.h
  • RCC_HSE_ON : stm32h7xx_hal_rcc.h
  • RCC_HSI48_OFF : stm32h7xx_hal_rcc.h
  • RCC_HSI48_ON : stm32h7xx_hal_rcc.h
  • RCC_HSI_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_HSI_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_HSI_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_HSI_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_HSI_OFF : stm32h7xx_hal_rcc.h
  • RCC_HSI_ON : stm32h7xx_hal_rcc.h
  • RCC_HSICALIBRATION_DEFAULT : stm32h7xx_hal_rcc.h
  • RCC_I2C1CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_IT_CSIRDY : stm32h7xx_hal_rcc.h
  • RCC_IT_CSS : stm32h7xx_hal_rcc.h
  • RCC_IT_HSERDY : stm32h7xx_hal_rcc.h
  • RCC_IT_HSI48RDY : stm32h7xx_hal_rcc.h
  • RCC_IT_HSIRDY : stm32h7xx_hal_rcc.h
  • RCC_IT_LSECSS : stm32h7xx_hal_rcc.h
  • RCC_IT_LSERDY : stm32h7xx_hal_rcc.h
  • RCC_IT_LSIRDY : stm32h7xx_hal_rcc.h
  • RCC_IT_PLL2RDY : stm32h7xx_hal_rcc.h
  • RCC_IT_PLL3RDY : stm32h7xx_hal_rcc.h
  • RCC_IT_PLLRDY : stm32h7xx_hal_rcc.h
  • RCC_LPTIM1CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM3CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM4CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM4CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM4CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM4CLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM4CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM4CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM5CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM5CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM5CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM5CLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM5CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPTIM5CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_LSE_BYPASS : stm32h7xx_hal_rcc.h
  • RCC_LSE_OFF : stm32h7xx_hal_rcc.h
  • RCC_LSE_ON : stm32h7xx_hal_rcc.h
  • RCC_LSE_TIMEOUT_VALUE : stm32h7xx_hal_rcc.h
  • RCC_LSEDRIVE_HIGH : stm32h7xx_hal_rcc.h
  • RCC_LSEDRIVE_LOW : stm32h7xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMHIGH : stm32h7xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMLOW : stm32h7xx_hal_rcc.h
  • RCC_LSI_OFF : stm32h7xx_hal_rcc.h
  • RCC_LSI_ON : stm32h7xx_hal_rcc.h
  • RCC_MCO1 : stm32h7xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSE : stm32h7xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI : stm32h7xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI48 : stm32h7xx_hal_rcc.h
  • RCC_MCO1SOURCE_LSE : stm32h7xx_hal_rcc.h
  • RCC_MCO1SOURCE_PLL1QCLK : stm32h7xx_hal_rcc.h
  • RCC_MCO2 : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_CSICLK : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_HSE : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_LSICLK : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_PLL2PCLK : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_PLLCLK : stm32h7xx_hal_rcc.h
  • RCC_MCO2SOURCE_SYSCLK : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_1 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_10 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_11 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_12 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_13 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_14 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_15 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_2 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_3 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_4 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_5 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_6 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_7 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_8 : stm32h7xx_hal_rcc.h
  • RCC_MCODIV_9 : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_CSI : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSE : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI48 : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSE : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI : stm32h7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_NONE : stm32h7xx_hal_rcc.h
  • RCC_PERIPHCLK_ADC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_CEC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_CKPER : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_DFSDM1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_DSI : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_FDCAN : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_FMC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_HRTIM1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C4 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM4 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM5 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPUART1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LTDC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_QSPI : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RNG : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RTC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI4A : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI4B : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SDMMC : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPDIFRX : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI4 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI5 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPI6 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SWPMI1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_TIM : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART4 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART5 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART7 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART8 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART6 : stm32h7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USB : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL1_DIVP : stm32h7xx_hal_rcc.h
  • RCC_PLL1_DIVQ : stm32h7xx_hal_rcc.h
  • RCC_PLL1_DIVR : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCIRANGE_0 : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCIRANGE_1 : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCIRANGE_2 : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCIRANGE_3 : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCOMEDIUM : stm32h7xx_hal_rcc.h
  • RCC_PLL1VCOWIDE : stm32h7xx_hal_rcc.h
  • RCC_PLL2_DIVP : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2_DIVQ : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2_DIVR : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCIRANGE_0 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCIRANGE_1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCIRANGE_2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCIRANGE_3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCOMEDIUM : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL2VCOWIDE : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3_DIVP : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3_DIVQ : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3_DIVR : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCIRANGE_0 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCIRANGE_1 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCIRANGE_2 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCIRANGE_3 : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCOMEDIUM : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL3VCOWIDE : stm32h7xx_hal_rcc_ex.h
  • RCC_PLL_NONE : stm32h7xx_hal_rcc.h
  • RCC_PLL_OFF : stm32h7xx_hal_rcc.h
  • RCC_PLL_ON : stm32h7xx_hal_rcc.h
  • RCC_PLLSOURCE_CSI : stm32h7xx_hal_rcc.h
  • RCC_PLLSOURCE_HSE : stm32h7xx_hal_rcc.h
  • RCC_PLLSOURCE_HSI : stm32h7xx_hal_rcc.h
  • RCC_PLLSOURCE_NONE : stm32h7xx_hal_rcc.h
  • RCC_QSPICLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_QSPICLKSOURCE_D1HCLK : stm32h7xx_hal_rcc_ex.h
  • RCC_QSPICLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_QSPICLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_HSI48 : stm32h7xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_LSI : stm32h7xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_RTCCLKSOURCE_HSE_DIV10 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV11 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV12 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV13 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV14 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV15 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV17 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV18 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV19 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV20 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV21 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV22 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV23 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV24 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV25 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV26 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV27 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV28 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV29 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV3 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV30 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV31 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV32 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV33 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV34 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV35 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV36 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV37 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV38 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV39 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV40 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV41 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV42 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV43 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV44 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV45 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV46 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV47 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV48 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV49 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV5 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV50 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV51 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV52 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV53 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV54 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV55 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV56 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV57 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV58 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV59 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV6 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV60 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV61 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV62 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV63 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV7 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV9 : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSE : stm32h7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSI : stm32h7xx_hal_rcc.h
  • RCC_SAI1CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI3CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI3CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI3CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI3CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI3CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI4ACLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI4ACLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI4ACLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI4ACLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI4ACLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI4BCLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI4BCLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI4BCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI4BCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SAI4BCLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SDMMCCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SDMMCCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPDIFRXCLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPDIFRXCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SPDIFRXCLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPDIFRXCLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI1CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI1CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI1CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI1CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI2CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI2CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI2CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI2CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI2CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI3CLKSOURCE_CLKP : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI3CLKSOURCE_PIN : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI3CLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI3CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI3CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI4CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI5CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_D3PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_HSE : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_SPI6CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_STOP_KERWAKEUPCLOCK_CSI : stm32h7xx_hal_rcc.h
  • RCC_STOP_KERWAKEUPCLOCK_HSI : stm32h7xx_hal_rcc.h
  • RCC_STOP_WAKEUPCLOCK_CSI : stm32h7xx_hal_rcc.h
  • RCC_STOP_WAKEUPCLOCK_HSI : stm32h7xx_hal_rcc.h
  • RCC_SWPMI1CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_SWPMI1CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_SYSCLK_DIV1 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV128 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV16 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV2 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV256 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV4 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV512 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV64 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLK_DIV8 : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_CSI : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSE : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSI : stm32h7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLCLK : stm32h7xx_hal_rcc.h
  • RCC_TIMPRES_ACTIVATED : stm32h7xx_hal_rcc_ex.h
  • RCC_TIMPRES_DESACTIVATED : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_D2PCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_D2PCLK1 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_CSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_D2PCLK2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_HSI : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_LSE : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_PLL2 : stm32h7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_HSI48 : stm32h7xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLL : stm32h7xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLL3 : stm32h7xx_hal_rcc_ex.h
  • RCC_WWDG1 : stm32h7xx_hal_rcc_ex.h
  • RISING_EDGE : stm32h7xx_hal_gpio.c
  • RNG_CED_DISABLE : stm32h7xx_hal_rng.h
  • RNG_CED_ENABLE : stm32h7xx_hal_rng.h
  • RNG_FLAG_CECS : stm32h7xx_hal_rng.h
  • RNG_FLAG_DRDY : stm32h7xx_hal_rng.h
  • RNG_FLAG_SECS : stm32h7xx_hal_rng.h
  • RNG_IT_CEI : stm32h7xx_hal_rng.h
  • RNG_IT_DRDY : stm32h7xx_hal_rng.h
  • RNG_IT_SEI : stm32h7xx_hal_rng.h
  • RNG_TIMEOUT_VALUE : stm32h7xx_hal_rng.c
  • RTC_ALARM_A : stm32h7xx_hal_rtc.h
  • RTC_ALARM_B : stm32h7xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_DATE : stm32h7xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_WEEKDAY : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_ALL : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_DATEWEEKDAY : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_HOURS : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_MINUTES : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_NONE : stm32h7xx_hal_rtc.h
  • RTC_ALARMMASK_SECONDS : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_ALL : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_NONE : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_1 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_10 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_11 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_12 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_13 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_2 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_3 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_4 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_5 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_6 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_7 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_8 : stm32h7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_9 : stm32h7xx_hal_rtc.h
  • RTC_ALL_TAMPER_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR0 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR1 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR10 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR11 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR12 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR13 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR14 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR15 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR16 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR17 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR18 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR19 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR2 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR20 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR21 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR22 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR23 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR24 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR25 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR26 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR27 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR28 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR29 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR3 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR30 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR31 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR4 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR5 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR6 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR7 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR8 : stm32h7xx_hal_rtc_ex.h
  • RTC_BKP_DR9 : stm32h7xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_1HZ : stm32h7xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_512HZ : stm32h7xx_hal_rtc_ex.h
  • RTC_DAYLIGHTSAVING_ADD1H : stm32h7xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_NONE : stm32h7xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_SUB1H : stm32h7xx_hal_rtc.h
  • RTC_DR_RESERVED_MASK : stm32h7xx_hal_rtc.h
  • RTC_EXTI_LINE_ALARM_EVENT : stm32h7xx_hal_rtc.h
  • RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT : stm32h7xx_hal_rtc_ex.h
  • RTC_EXTI_LINE_WAKEUPTIMER_EVENT : stm32h7xx_hal_rtc_ex.h
  • RTC_FLAG_ALRAF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_ALRAWF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_ALRBF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_ALRBWF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_INITF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_INITS : stm32h7xx_hal_rtc.h
  • RTC_FLAG_ITSF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_RECALPF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_RSF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_SHPF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_TAMP1F : stm32h7xx_hal_rtc.h
  • RTC_FLAG_TAMP2F : stm32h7xx_hal_rtc.h
  • RTC_FLAG_TAMP3F : stm32h7xx_hal_rtc.h
  • RTC_FLAG_TSF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_TSOVF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_WUTF : stm32h7xx_hal_rtc.h
  • RTC_FLAG_WUTWF : stm32h7xx_hal_rtc.h
  • RTC_FORMAT_BCD : stm32h7xx_hal_rtc.h
  • RTC_FORMAT_BIN : stm32h7xx_hal_rtc.h
  • RTC_HOURFORMAT12_AM : stm32h7xx_hal_rtc.h
  • RTC_HOURFORMAT12_PM : stm32h7xx_hal_rtc.h
  • RTC_HOURFORMAT_12 : stm32h7xx_hal_rtc.h
  • RTC_HOURFORMAT_24 : stm32h7xx_hal_rtc.h
  • RTC_INIT_MASK : stm32h7xx_hal_rtc.h
  • RTC_IT_ALRA : stm32h7xx_hal_rtc.h
  • RTC_IT_ALRB : stm32h7xx_hal_rtc.h
  • RTC_IT_TAMP : stm32h7xx_hal_rtc.h
  • RTC_IT_TAMP1 : stm32h7xx_hal_rtc.h
  • RTC_IT_TAMP2 : stm32h7xx_hal_rtc.h
  • RTC_IT_TAMP3 : stm32h7xx_hal_rtc.h
  • RTC_IT_TS : stm32h7xx_hal_rtc.h
  • RTC_IT_WUT : stm32h7xx_hal_rtc.h
  • RTC_MONTH_APRIL : stm32h7xx_hal_rtc.h
  • RTC_MONTH_AUGUST : stm32h7xx_hal_rtc.h
  • RTC_MONTH_DECEMBER : stm32h7xx_hal_rtc.h
  • RTC_MONTH_FEBRUARY : stm32h7xx_hal_rtc.h
  • RTC_MONTH_JANUARY : stm32h7xx_hal_rtc.h
  • RTC_MONTH_JULY : stm32h7xx_hal_rtc.h
  • RTC_MONTH_JUNE : stm32h7xx_hal_rtc.h
  • RTC_MONTH_MARCH : stm32h7xx_hal_rtc.h
  • RTC_MONTH_MAY : stm32h7xx_hal_rtc.h
  • RTC_MONTH_NOVEMBER : stm32h7xx_hal_rtc.h
  • RTC_MONTH_OCTOBER : stm32h7xx_hal_rtc.h
  • RTC_MONTH_SEPTEMBER : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_ALARMA : stm32h7xx_hal_rtc_ex.h
  • RTC_OUTPUT_ALARMB : stm32h7xx_hal_rtc_ex.h
  • RTC_OUTPUT_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_OUTPUT_POLARITY_HIGH : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_LOW : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_REMAP_NONE : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_REMAP_POS1 : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_OPENDRAIN : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_PUSHPULL : stm32h7xx_hal_rtc.h
  • RTC_OUTPUT_WAKEUP : stm32h7xx_hal_rtc_ex.h
  • RTC_RSF_MASK : stm32h7xx_hal_rtc.h
  • RTC_SHIFTADD1S_RESET : stm32h7xx_hal_rtc_ex.h
  • RTC_SHIFTADD1S_SET : stm32h7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_16SEC : stm32h7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_32SEC : stm32h7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_8SEC : stm32h7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET : stm32h7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_SET : stm32h7xx_hal_rtc_ex.h
  • RTC_STOREOPERATION_RESET : stm32h7xx_hal_rtc.h
  • RTC_STOREOPERATION_SET : stm32h7xx_hal_rtc.h
  • RTC_TAMPCR_TAMPXE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPCR_TAMPXIE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER1_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER2_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER3_INTERRUPT : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_1 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_2 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_3 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_2SAMPLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_4SAMPLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_8SAMPLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_1RTCCLK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_2RTCCLK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_4RTCCLK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_8RTCCLK : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_FALLINGEDGE : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_HIGHLEVEL : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_LOWLEVEL : stm32h7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_RISINGEDGE : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMEOUT_VALUE : stm32h7xx_hal_rtc.h
  • RTC_TIMESTAMPEDGE_FALLING : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPEDGE_RISING : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_DISABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_ENABLE : stm32h7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_DEFAULT : stm32h7xx_hal_rtc_ex.h
  • RTC_TR_RESERVED_MASK : stm32h7xx_hal_rtc.h
  • RTC_WAKEUPCLOCK_CK_SPRE_16BITS : stm32h7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_CK_SPRE_17BITS : stm32h7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV16 : stm32h7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV2 : stm32h7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV4 : stm32h7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV8 : stm32h7xx_hal_rtc_ex.h
  • RTC_WEEKDAY_FRIDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_MONDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_SATURDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_SUNDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_THURSDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_TUESDAY : stm32h7xx_hal_rtc.h
  • RTC_WEEKDAY_WEDNESDAY : stm32h7xx_hal_rtc.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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- s -

  • SAI_AC97_PROTOCOL : stm32h7xx_hal_sai.h
  • SAI_ALAW_1CPL_COMPANDING : stm32h7xx_hal_sai.h
  • SAI_ALAW_2CPL_COMPANDING : stm32h7xx_hal_sai.h
  • SAI_ASYNCHRONOUS : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_11K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_16K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_192K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_22K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_32K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_44K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_48K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_8K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_96K : stm32h7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_MCKDIV : stm32h7xx_hal_sai.h
  • SAI_CLOCKSTROBING_FALLINGEDGE : stm32h7xx_hal_sai.h
  • SAI_CLOCKSTROBING_RISINGEDGE : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_10 : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_16 : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_20 : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_24 : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_32 : stm32h7xx_hal_sai.h
  • SAI_DATASIZE_8 : stm32h7xx_hal_sai.h
  • SAI_DEFAULT_TIMEOUT : stm32h7xx_hal_sai.c
  • SAI_FIFO_SIZE : stm32h7xx_hal_sai.c
  • SAI_FIFOSTATUS_1QUARTERFULL : stm32h7xx_hal_sai.h
  • SAI_FIFOSTATUS_3QUARTERFULL : stm32h7xx_hal_sai.h
  • SAI_FIFOSTATUS_EMPTY : stm32h7xx_hal_sai.h
  • SAI_FIFOSTATUS_FULL : stm32h7xx_hal_sai.h
  • SAI_FIFOSTATUS_HALFFULL : stm32h7xx_hal_sai.h
  • SAI_FIFOSTATUS_LESS1QUARTERFULL : stm32h7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_1QF : stm32h7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_3QF : stm32h7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_EMPTY : stm32h7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_FULL : stm32h7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_HF : stm32h7xx_hal_sai.h
  • SAI_FIRSTBIT_LSB : stm32h7xx_hal_sai.h
  • SAI_FIRSTBIT_MSB : stm32h7xx_hal_sai.h
  • SAI_FLAG_AFSDET : stm32h7xx_hal_sai.h
  • SAI_FLAG_CNRDY : stm32h7xx_hal_sai.h
  • SAI_FLAG_FREQ : stm32h7xx_hal_sai.h
  • SAI_FLAG_LFSDET : stm32h7xx_hal_sai.h
  • SAI_FLAG_MUTEDET : stm32h7xx_hal_sai.h
  • SAI_FLAG_OVRUDR : stm32h7xx_hal_sai.h
  • SAI_FLAG_WCKCFG : stm32h7xx_hal_sai.h
  • SAI_FREE_PROTOCOL : stm32h7xx_hal_sai.h
  • SAI_FS_ACTIVE_HIGH : stm32h7xx_hal_sai.h
  • SAI_FS_ACTIVE_LOW : stm32h7xx_hal_sai.h
  • SAI_FS_BEFOREFIRSTBIT : stm32h7xx_hal_sai.h
  • SAI_FS_CHANNEL_IDENTIFICATION : stm32h7xx_hal_sai.h
  • SAI_FS_FIRSTBIT : stm32h7xx_hal_sai.h
  • SAI_FS_STARTFRAME : stm32h7xx_hal_sai.h
  • SAI_I2S_LSBJUSTIFIED : stm32h7xx_hal_sai.h
  • SAI_I2S_MSBJUSTIFIED : stm32h7xx_hal_sai.h
  • SAI_I2S_STANDARD : stm32h7xx_hal_sai.h
  • SAI_IT_AFSDET : stm32h7xx_hal_sai.h
  • SAI_IT_CNRDY : stm32h7xx_hal_sai.h
  • SAI_IT_FREQ : stm32h7xx_hal_sai.h
  • SAI_IT_LFSDET : stm32h7xx_hal_sai.h
  • SAI_IT_MUTEDET : stm32h7xx_hal_sai.h
  • SAI_IT_OVRUDR : stm32h7xx_hal_sai.h
  • SAI_IT_WCKCFG : stm32h7xx_hal_sai.h
  • SAI_LAST_SENT_VALUE : stm32h7xx_hal_sai.h
  • SAI_LONG_TIMEOUT : stm32h7xx_hal_sai.c
  • SAI_MASTERDIVIDER_DISABLE : stm32h7xx_hal_sai.h
  • SAI_MASTERDIVIDER_ENABLE : stm32h7xx_hal_sai.h
  • SAI_MCK_OVERSAMPLING_DISABLE : stm32h7xx_hal_sai.h
  • SAI_MCK_OVERSAMPLING_ENABLE : stm32h7xx_hal_sai.h
  • SAI_MODEMASTER_RX : stm32h7xx_hal_sai.h
  • SAI_MODEMASTER_TX : stm32h7xx_hal_sai.h
  • SAI_MODESLAVE_RX : stm32h7xx_hal_sai.h
  • SAI_MODESLAVE_TX : stm32h7xx_hal_sai.h
  • SAI_MONOMODE : stm32h7xx_hal_sai.h
  • SAI_NOCOMPANDING : stm32h7xx_hal_sai.h
  • SAI_OUTPUT_NOTRELEASED : stm32h7xx_hal_sai.h
  • SAI_OUTPUT_RELEASED : stm32h7xx_hal_sai.h
  • SAI_OUTPUTDRIVE_DISABLE : stm32h7xx_hal_sai.h
  • SAI_OUTPUTDRIVE_ENABLE : stm32h7xx_hal_sai.h
  • SAI_PCM_LONG : stm32h7xx_hal_sai.h
  • SAI_PCM_SHORT : stm32h7xx_hal_sai.h
  • SAI_PDM_CLOCK1_ENABLE : stm32h7xx_hal_sai.h
  • SAI_PDM_CLOCK2_ENABLE : stm32h7xx_hal_sai.h
  • SAI_PDM_CLOCK3_ENABLE : stm32h7xx_hal_sai.h
  • SAI_PDM_CLOCK4_ENABLE : stm32h7xx_hal_sai.h
  • SAI_PDM_DELAY_MASK : stm32h7xx_hal_sai_ex.c
  • SAI_PDM_DELAY_OFFSET : stm32h7xx_hal_sai_ex.c
  • SAI_PDM_RIGHT_DELAY_OFFSET : stm32h7xx_hal_sai_ex.c
  • SAI_PDMCR_MICNBR_OFFSET : stm32h7xx_hal_sai.c
  • SAI_PROTOCOL_DATASIZE_16BIT : stm32h7xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_16BITEXTENDED : stm32h7xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_24BIT : stm32h7xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_32BIT : stm32h7xx_hal_sai.h
  • SAI_SLOT_NOTACTIVE : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_0 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_1 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_10 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_11 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_12 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_13 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_14 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_15 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_2 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_3 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_4 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_5 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_6 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_7 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_8 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_9 : stm32h7xx_hal_sai.h
  • SAI_SLOTACTIVE_ALL : stm32h7xx_hal_sai.h
  • SAI_SLOTSIZE_16B : stm32h7xx_hal_sai.h
  • SAI_SLOTSIZE_32B : stm32h7xx_hal_sai.h
  • SAI_SLOTSIZE_DATASIZE : stm32h7xx_hal_sai.h
  • SAI_SPDIF_PROTOCOL : stm32h7xx_hal_sai.h
  • SAI_STEREOMODE : stm32h7xx_hal_sai.h
  • SAI_SYNCEXT_DISABLE : stm32h7xx_hal_sai.h
  • SAI_SYNCEXT_OUTBLOCKA_ENABLE : stm32h7xx_hal_sai.h
  • SAI_SYNCEXT_OUTBLOCKB_ENABLE : stm32h7xx_hal_sai.h
  • SAI_SYNCHRONOUS : stm32h7xx_hal_sai.h
  • SAI_SYNCHRONOUS_EXT_SAI1 : stm32h7xx_hal_sai.h
  • SAI_SYNCHRONOUS_EXT_SAI2 : stm32h7xx_hal_sai.h
  • SAI_ULAW_1CPL_COMPANDING : stm32h7xx_hal_sai.h
  • SAI_ULAW_2CPL_COMPANDING : stm32h7xx_hal_sai.h
  • SAI_xCR2_MUTECNT_OFFSET : stm32h7xx_hal_sai.c
  • SAI_ZERO_VALUE : stm32h7xx_hal_sai.h
  • SD_CONTEXT_DMA : stm32h7xx_hal_sd.h
  • SD_CONTEXT_IT : stm32h7xx_hal_sd.h
  • SD_CONTEXT_NONE : stm32h7xx_hal_sd.h
  • SD_CONTEXT_READ_MULTIPLE_BLOCK : stm32h7xx_hal_sd.h
  • SD_CONTEXT_READ_SINGLE_BLOCK : stm32h7xx_hal_sd.h
  • SD_CONTEXT_WRITE_MULTIPLE_BLOCK : stm32h7xx_hal_sd.h
  • SD_CONTEXT_WRITE_SINGLE_BLOCK : stm32h7xx_hal_sd.h
  • SD_InitTypeDef : stm32h7xx_hal_sd.h
  • SD_TypeDef : stm32h7xx_hal_sd.h
  • SlaveAddr_MSK : stm32h7xx_hal_i2c.c
  • SlaveAddr_SHIFT : stm32h7xx_hal_i2c.c
  • SMARTCARD_ADVFEATURE_DATAINV_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINV_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINVERT_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_NO_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_OVERRUN_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_OVERRUN_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINVERT_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_SWAP_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXCOMPLETION : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXINV_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINV_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINVERT_INIT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_EOBF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_FEF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_IDLEF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_NEF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_OREF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_PEF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_RTOF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCBGTF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TXFECF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_UDRCF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_CR3_SCARCNT_LSB_POS : stm32h7xx_hal_smartcard.h
  • SMARTCARD_FIFOMODE_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_FIFOMODE_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_FLAG_BUSY : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_EOBF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_FE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_IDLE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_NE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_ORE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_PE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_REACK : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RTOF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXNE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TC : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TCBGT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TEACK : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_GETCLOCKSOURCE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_GTPR_GT_LSB_POS : stm32h7xx_hal_smartcard.h
  • SMARTCARD_IT_EOB : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_ERR : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_FE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_IDLE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_MASK : stm32h7xx_hal_smartcard.h
  • SMARTCARD_IT_NE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_ORE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_PE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RTO : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFF : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXNE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TC : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TCBGT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFE : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_LASTBIT_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_MODE_RX : stm32h7xx_hal_smartcard.h
  • SMARTCARD_MODE_TX : stm32h7xx_hal_smartcard.h
  • SMARTCARD_MODE_TX_RX : stm32h7xx_hal_smartcard.h
  • SMARTCARD_NACK_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_NACK_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PARITY_EVEN : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PARITY_ODD : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PHASE_1EDGE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_PHASE_2EDGE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_POLARITY_HIGH : stm32h7xx_hal_smartcard.h
  • SMARTCARD_POLARITY_LOW : stm32h7xx_hal_smartcard.h
  • SMARTCARD_RTOR_BLEN_LSB_POS : stm32h7xx_hal_smartcard.h
  • SMARTCARD_RXDATA_FLUSH_REQUEST : stm32h7xx_hal_smartcard.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_RXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_RXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_RXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_0_5 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_1_5 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TC : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TCBGT : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TEACK_REACK_TIMEOUT : stm32h7xx_hal_smartcard.c
  • SMARTCARD_TIMEOUT_DISABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TIMEOUT_ENABLE : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TRANSMISSION_COMPLETION_FLAG : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TRANSMISSION_COMPLETION_SETTING : stm32h7xx_hal_smartcard_ex.h
  • SMARTCARD_TXDATA_FLUSH_REQUEST : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_TXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_smartcard.h
  • SMARTCARD_WORDLENGTH_9B : stm32h7xx_hal_smartcard.h
  • SMBUS_ADDRESSINGMODE_10BIT : stm32h7xx_hal_smbus.h
  • SMBUS_ADDRESSINGMODE_7BIT : stm32h7xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_DISABLE : stm32h7xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_ENABLE : stm32h7xx_hal_smbus.h
  • SMBUS_AUTOEND_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_CHECK_FLAG : stm32h7xx_hal_smbus.h
  • SMBUS_DUALADDRESS_DISABLE : stm32h7xx_hal_smbus.h
  • SMBUS_DUALADDRESS_ENABLE : stm32h7xx_hal_smbus.h
  • SMBUS_FIRST_AND_LAST_FRAME_NO_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_FIRST_FRAME : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_ADDR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_AF : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_ALERT : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_ARLO : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_BERR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_BUSY : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_DIR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_MASK : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_OVR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_PECERR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_RXNE : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_STOPF : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_TC : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_TCR : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_TIMEOUT : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_TXE : stm32h7xx_hal_smbus.h
  • SMBUS_FLAG_TXIS : stm32h7xx_hal_smbus.h
  • SMBUS_GENERALCALL_DISABLE : stm32h7xx_hal_smbus.h
  • SMBUS_GENERALCALL_ENABLE : stm32h7xx_hal_smbus.h
  • SMBUS_GENERATE_START : stm32h7xx_hal_smbus.h
  • SMBUS_GENERATE_START_READ : stm32h7xx_hal_smbus.h
  • SMBUS_GENERATE_START_WRITE : stm32h7xx_hal_smbus.h
  • SMBUS_GENERATE_STOP : stm32h7xx_hal_smbus.h
  • SMBUS_GET_ADDR_MATCH : stm32h7xx_hal_smbus.h
  • SMBUS_GET_ALERT_ENABLED : stm32h7xx_hal_smbus.h
  • SMBUS_GET_DIR : stm32h7xx_hal_smbus.h
  • SMBUS_GET_ISR_REG : stm32h7xx_hal_smbus.h
  • SMBUS_GET_PEC_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_GET_STOP_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_IT_ADDR : stm32h7xx_hal_smbus.h
  • SMBUS_IT_ADDRI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_ALERT : stm32h7xx_hal_smbus.h
  • SMBUS_IT_ERRI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_NACKI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_RX : stm32h7xx_hal_smbus.h
  • SMBUS_IT_RXI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_STOPI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_TCI : stm32h7xx_hal_smbus.h
  • SMBUS_IT_TX : stm32h7xx_hal_smbus.h
  • SMBUS_IT_TXI : stm32h7xx_hal_smbus.h
  • SMBUS_LAST_FRAME_NO_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_LAST_FRAME_WITH_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_NEXT_FRAME : stm32h7xx_hal_smbus.h
  • SMBUS_NO_STARTSTOP : stm32h7xx_hal_smbus.h
  • SMBUS_NOSTRETCH_DISABLE : stm32h7xx_hal_smbus.h
  • SMBUS_NOSTRETCH_ENABLE : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK01 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK02 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK03 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK04 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK05 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK06 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_MASK07 : stm32h7xx_hal_smbus.h
  • SMBUS_OA2_NOMASK : stm32h7xx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_NO_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_OTHER_FRAME_NO_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_OTHER_FRAME_WITH_PEC : stm32h7xx_hal_smbus.h
  • SMBUS_PEC_DISABLE : stm32h7xx_hal_smbus.h
  • SMBUS_PEC_ENABLE : stm32h7xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_HOST : stm32h7xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE : stm32h7xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP : stm32h7xx_hal_smbus.h
  • SMBUS_RELOAD_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_RESET_CR1 : stm32h7xx_hal_smbus.h
  • SMBUS_RESET_CR2 : stm32h7xx_hal_smbus.h
  • SMBUS_SENDPEC_MODE : stm32h7xx_hal_smbus.h
  • SMBUS_SOFTEND_MODE : stm32h7xx_hal_smbus.h
  • SPDIFRX_CHANNEL_A : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_CHANNEL_B : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_CHANNELSTATUS_OFF : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_CHANNELSTATUS_ON : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_DATAFORMAT_32BITS : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_DATAFORMAT_LSB : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_DATAFORMAT_MSB : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_CSRNE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_FERR : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_OVR : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_PERR : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_RXNE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_SBD : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_SERR : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_SYNCD : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_TERR : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN0 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN1 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN2 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN3 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_CSRNE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_IFEIE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_OVRIE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_PERRIE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_RXNE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_SBLKIE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_IT_SYNCDIE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_15 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_3 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_63 : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_NONE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_PARITYERRORMASK_OFF : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_PARITYERRORMASK_ON : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_PREAMBLETYPEMASK_OFF : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_PREAMBLETYPEMASK_ON : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_STATE_IDLE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_STATE_RCV : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_STATE_SYNC : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_STEREOMODE_DISABLE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_STEREOMODE_ENABLE : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_TIMEOUT_VALUE : stm32h7xx_hal_spdifrx.c
  • SPDIFRX_VALIDITYMASK_OFF : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_VALIDITYMASK_ON : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_WAITFORACTIVITY_OFF : stm32h7xx_hal_spdifrx.h
  • SPDIFRX_WAITFORACTIVITY_ON : stm32h7xx_hal_spdifrx.h
  • SPI_1LINE_RX : stm32h7xx_hal_spi.h
  • SPI_1LINE_TX : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_128 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm32h7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm32h7xx_hal_spi.h
  • SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN : stm32h7xx_hal_spi.h
  • SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_10BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_11BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_12BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_13BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_14BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_15BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_16BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_17BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_18BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_19BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_20BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_21BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_22BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_23BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_24BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_25BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_26BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_27BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_28BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_29BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_30BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_31BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_32BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_4BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_5BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_6BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_7BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_8BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_9BIT : stm32h7xx_hal_spi.h
  • SPI_CRC_LENGTH_DATASIZE : stm32h7xx_hal_spi.h
  • SPI_CRCCALCULATION_DISABLE : stm32h7xx_hal_spi.h
  • SPI_CRCCALCULATION_ENABLE : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_10BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_11BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_12BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_13BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_14BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_15BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_16BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_17BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_18BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_19BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_20BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_21BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_22BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_23BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_24BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_25BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_26BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_27BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_28BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_29BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_30BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_31BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_32BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_4BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_5BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_6BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_7BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_8BIT : stm32h7xx_hal_spi.h
  • SPI_DATASIZE_9BIT : stm32h7xx_hal_spi.h
  • SPI_DEFAULT_TIMEOUT : stm32h7xx_hal_spi.c
  • SPI_DIRECTION_1LINE : stm32h7xx_hal_spi.h
  • SPI_DIRECTION_2LINES : stm32h7xx_hal_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : stm32h7xx_hal_spi.h
  • SPI_DIRECTION_2LINES_TXONLY : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_01DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_02DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_03DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_04DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_05DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_06DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_07DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_08DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_09DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_10DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_11DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_12DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_13DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_14DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_15DATA : stm32h7xx_hal_spi.h
  • SPI_FIFO_THRESHOLD_16DATA : stm32h7xx_hal_spi.h
  • SPI_FIRSTBIT_LSB : stm32h7xx_hal_spi.h
  • SPI_FIRSTBIT_MSB : stm32h7xx_hal_spi.h
  • SPI_FLAG_CRCERR : stm32h7xx_hal_spi.h
  • SPI_FLAG_EOT : stm32h7xx_hal_spi.h
  • SPI_FLAG_FRE : stm32h7xx_hal_spi.h
  • SPI_FLAG_FRLVL : stm32h7xx_hal_spi.h
  • SPI_FLAG_MODF : stm32h7xx_hal_spi.h
  • SPI_FLAG_OVR : stm32h7xx_hal_spi.h
  • SPI_FLAG_RXNE : stm32h7xx_hal_spi.h
  • SPI_FLAG_RXWNE : stm32h7xx_hal_spi.h
  • SPI_FLAG_TXE : stm32h7xx_hal_spi.h
  • SPI_FLAG_TXTF : stm32h7xx_hal_spi.h
  • SPI_FLAG_UDR : stm32h7xx_hal_spi.h
  • SPI_FRLVL_EMPTY : stm32h7xx_hal_spi.h
  • SPI_FRLVL_FULL : stm32h7xx_hal_spi.h
  • SPI_FRLVL_HALF_FULL : stm32h7xx_hal_spi.h
  • SPI_FRLVL_QUARTER_FULL : stm32h7xx_hal_spi.h
  • SPI_HIGHEND_FIFO_SIZE : stm32h7xx_hal_spi.h
  • SPI_IO_SWAP_DISABLE : stm32h7xx_hal_spi.h
  • SPI_IO_SWAP_ENABLE : stm32h7xx_hal_spi.h
  • SPI_IT_EOT : stm32h7xx_hal_spi.h
  • SPI_IT_ERR : stm32h7xx_hal_spi.h
  • SPI_IT_RXNE : stm32h7xx_hal_spi.h
  • SPI_IT_TXE : stm32h7xx_hal_spi.h
  • SPI_IT_TXTF : stm32h7xx_hal_spi.h
  • SPI_LOWEND_FIFO_SIZE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_00CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_01CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_02CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_03CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_04CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_05CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_06CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_07CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_08CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_09CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_10CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_11CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_12CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_13CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_14CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_INTERDATA_IDLENESS_15CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_KEEP_IO_STATE_DISABLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_KEEP_IO_STATE_ENABLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_RX_AUTOSUSP_DISABLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_RX_AUTOSUSP_ENABLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_00CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_01CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_02CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_03CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_04CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_05CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_06CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_07CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_08CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_09CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_10CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_11CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_12CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_13CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_14CYCLE : stm32h7xx_hal_spi.h
  • SPI_MASTER_SS_IDLENESS_15CYCLE : stm32h7xx_hal_spi.h
  • SPI_MODE_MASTER : stm32h7xx_hal_spi.h
  • SPI_MODE_SLAVE : stm32h7xx_hal_spi.h
  • SPI_NSS_HARD_INPUT : stm32h7xx_hal_spi.h
  • SPI_NSS_HARD_OUTPUT : stm32h7xx_hal_spi.h
  • SPI_NSS_POLARITY_HIGH : stm32h7xx_hal_spi.h
  • SPI_NSS_POLARITY_LOW : stm32h7xx_hal_spi.h
  • SPI_NSS_PULSE_DISABLE : stm32h7xx_hal_spi.h
  • SPI_NSS_PULSE_ENABLE : stm32h7xx_hal_spi.h
  • SPI_NSS_SOFT : stm32h7xx_hal_spi.h
  • SPI_PHASE_1EDGE : stm32h7xx_hal_spi.h
  • SPI_PHASE_2EDGE : stm32h7xx_hal_spi.h
  • SPI_POLARITY_HIGH : stm32h7xx_hal_spi.h
  • SPI_POLARITY_LOW : stm32h7xx_hal_spi.h
  • SPI_TIMODE_DISABLE : stm32h7xx_hal_spi.h
  • SPI_TIMODE_ENABLE : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_BEHAV_LAST_RECEIVED : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_BEHAV_REGISTER_PATTERN : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME : stm32h7xx_hal_spi.h
  • SPI_UNDERRUN_DETECT_END_DATA_FRAME : stm32h7xx_hal_spi.h
  • SWPMI_FLAG_DEACTF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_RDYF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_RXBERF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_RXBFF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_RXNE : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_RXOVRF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_SRF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_SUSP : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_TCF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_TXBEF : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_TXE : stm32h7xx_hal_swpmi.h
  • SWPMI_FLAG_TXUNRF : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_RDYIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_RIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_RXBERIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_RXBFIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_RXOVRIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_SRIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_TCIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_TIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_TXBEIE : stm32h7xx_hal_swpmi.h
  • SWPMI_IT_TXUNRIE : stm32h7xx_hal_swpmi.h
  • SWPMI_RX_MULTI_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_RX_NO_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_RX_SINGLE_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_TIMEOUT_VALUE : stm32h7xx_hal_swpmi.c
  • SWPMI_TX_MULTI_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_TX_NO_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_TX_SINGLE_SOFTWAREBUFFER : stm32h7xx_hal_swpmi.h
  • SWPMI_VOLTAGE_CLASS_B : stm32h7xx_hal_swpmi.h
  • SWPMI_VOLTAGE_CLASS_C : stm32h7xx_hal_swpmi.h
  • SYSCFG_BOOT_ADDR0 : stm32h7xx_hal.h
  • SYSCFG_BOOT_ADDR1 : stm32h7xx_hal.h
  • SYSCFG_CELL_CODE : stm32h7xx_hal.h
  • SYSCFG_ETH_MII : stm32h7xx_hal.h
  • SYSCFG_ETH_RMII : stm32h7xx_hal.h
  • SYSCFG_REGISTER_CODE : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA0 : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA0_CLOSE : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA0_OPEN : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA1 : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA1_CLOSE : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PA1_OPEN : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC2 : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC2_CLOSE : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC2_OPEN : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC3 : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC3_CLOSE : stm32h7xx_hal.h
  • SYSCFG_SWITCH_PC3_OPEN : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE0 : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE1 : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE2 : stm32h7xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE3 : stm32h7xx_hal.h
  • SYSTICK_CLKSOURCE_HCLK : stm32h7xx_hal_cortex.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32h7xx_hal_cortex.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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- t -

  • TICK_INT_PRIORITY : stm32h7xx_hal_conf.h
  • TIM_AUTOMATICOUTPUT_DISABLE : stm32h7xx_hal_tim.h
  • TIM_AUTOMATICOUTPUT_ENABLE : stm32h7xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_DISABLE : stm32h7xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_ENABLE : stm32h7xx_hal_tim.h
  • TIM_BREAK2_DISABLE : stm32h7xx_hal_tim_ex.h
  • TIM_BREAK2_ENABLE : stm32h7xx_hal_tim_ex.h
  • TIM_BREAK2POLARITY_HIGH : stm32h7xx_hal_tim_ex.h
  • TIM_BREAK2POLARITY_LOW : stm32h7xx_hal_tim_ex.h
  • TIM_BREAK_DISABLE : stm32h7xx_hal_tim.h
  • TIM_BREAK_ENABLE : stm32h7xx_hal_tim.h
  • TIM_BREAKINPUT_BRK : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUT_BRK2 : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_BKIN : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP1 : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP2 : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_DFSDM1 : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_DISABLE : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_ENABLE : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_HIGH : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_LOW : stm32h7xx_hal_tim_ex.h
  • TIM_BREAKPOLARITY_HIGH : stm32h7xx_hal_tim.h
  • TIM_BREAKPOLARITY_LOW : stm32h7xx_hal_tim.h
  • TIM_CCER_CCxE_MASK : stm32h7xx_hal_tim.h
  • TIM_CCER_CCxNE_MASK : stm32h7xx_hal_tim.h
  • TIM_CCx_DISABLE : stm32h7xx_hal_tim.h
  • TIM_CCx_ENABLE : stm32h7xx_hal_tim.h
  • TIM_CCxN_DISABLE : stm32h7xx_hal_tim.h
  • TIM_CCxN_ENABLE : stm32h7xx_hal_tim.h
  • TIM_CHANNEL_1 : stm32h7xx_hal_tim_ex.h
  • TIM_CHANNEL_2 : stm32h7xx_hal_tim_ex.h
  • TIM_CHANNEL_3 : stm32h7xx_hal_tim_ex.h
  • TIM_CHANNEL_4 : stm32h7xx_hal_tim_ex.h
  • TIM_CHANNEL_5 : stm32h7xx_hal_tim_ex.h
  • TIM_CHANNEL_6 : stm32h7xx_hal_tim_ex.h
  • TIM_CHANNEL_ALL : stm32h7xx_hal_tim_ex.h
  • TIM_CLEARINPUTPOLARITY_INVERTED : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_NONINVERTED : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV1 : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV2 : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV4 : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV8 : stm32h7xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_ETR : stm32h7xx_hal_tim_ex.h
  • TIM_CLEARINPUTSOURCE_NONE : stm32h7xx_hal_tim_ex.h
  • TIM_CLEARINPUTSOURCE_OCREFCLR : stm32h7xx_hal_tim_ex.h
  • TIM_CLOCKDIVISION_DIV1 : stm32h7xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV2 : stm32h7xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV4 : stm32h7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_BOTHEDGE : stm32h7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_FALLING : stm32h7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_INVERTED : stm32h7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_NONINVERTED : stm32h7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_RISING : stm32h7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV1 : stm32h7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV2 : stm32h7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV4 : stm32h7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV8 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE1 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE2 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_INTERNAL : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR0 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR1 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR2 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR3 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1 : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1ED : stm32h7xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI2 : stm32h7xx_hal_tim.h
  • TIM_COMMUTATION_SOFTWARE : stm32h7xx_hal_tim.h
  • TIM_COMMUTATION_TRGI : stm32h7xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED1 : stm32h7xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED2 : stm32h7xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED3 : stm32h7xx_hal_tim.h
  • TIM_COUNTERMODE_DOWN : stm32h7xx_hal_tim.h
  • TIM_COUNTERMODE_UP : stm32h7xx_hal_tim.h
  • TIM_DMA_CC1 : stm32h7xx_hal_tim.h
  • TIM_DMA_CC2 : stm32h7xx_hal_tim.h
  • TIM_DMA_CC3 : stm32h7xx_hal_tim.h
  • TIM_DMA_CC4 : stm32h7xx_hal_tim.h
  • TIM_DMA_COM : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_CC1 : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_CC2 : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_CC3 : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_CC4 : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_COMMUTATION : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_DMA_ID_UPDATE : stm32h7xx_hal_tim.h
  • TIM_DMA_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_DMA_UPDATE : stm32h7xx_hal_tim.h
  • TIM_DMABASE_AF1 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_AF2 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_AF3 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_ARR : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_BDTR : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CCER : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CCMR1 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CCMR2 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CCMR3 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CCR1 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CCR2 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CCR3 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CCR4 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CCR5 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CCR6 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CNT : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CR1 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_CR2 : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_DCR : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_DIER : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_DMAR : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_EGR : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_PSC : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_RCR : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_SMCR : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_SR : stm32h7xx_hal_tim_ex.h
  • TIM_DMABASE_TISEL : stm32h7xx_hal_tim_ex.h
  • TIM_DMABURSTLENGTH_10TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_11TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_12TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_13TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_14TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_15TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_16TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_17TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_18TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_1TRANSFER : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_2TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_3TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_4TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_5TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_6TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_7TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_8TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_9TRANSFERS : stm32h7xx_hal_tim.h
  • TIM_ENCODERMODE_TI1 : stm32h7xx_hal_tim.h
  • TIM_ENCODERMODE_TI12 : stm32h7xx_hal_tim.h
  • TIM_ENCODERMODE_TI2 : stm32h7xx_hal_tim.h
  • TIM_ETRPOLARITY_INVERTED : stm32h7xx_hal_tim.h
  • TIM_ETRPOLARITY_NONINVERTED : stm32h7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV1 : stm32h7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV2 : stm32h7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV4 : stm32h7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV8 : stm32h7xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_BREAK2 : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_CC1 : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_CC2 : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_CC3 : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_CC4 : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_COM : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_TRIGGER : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim_ex.h
  • TIM_EVENTSOURCE_UPDATE : stm32h7xx_hal_tim.h , stm32h7xx_hal_tim_ex.h
  • TIM_FLAG_BREAK : stm32h7xx_hal_tim.h
  • TIM_FLAG_BREAK2 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC1 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC1OF : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC2 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC2OF : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC3 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC3OF : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC4 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC4OF : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC5 : stm32h7xx_hal_tim.h
  • TIM_FLAG_CC6 : stm32h7xx_hal_tim.h
  • TIM_FLAG_COM : stm32h7xx_hal_tim.h
  • TIM_FLAG_SYSTEM_BREAK : stm32h7xx_hal_tim.h
  • TIM_FLAG_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_FLAG_UPDATE : stm32h7xx_hal_tim.h
  • TIM_GROUPCH5_NONE : stm32h7xx_hal_tim_ex.h
  • TIM_GROUPCH5_OC1REFC : stm32h7xx_hal_tim_ex.h
  • TIM_GROUPCH5_OC2REFC : stm32h7xx_hal_tim_ex.h
  • TIM_GROUPCH5_OC3REFC : stm32h7xx_hal_tim_ex.h
  • TIM_ICPOLARITY_BOTHEDGE : stm32h7xx_hal_tim.h
  • TIM_ICPOLARITY_FALLING : stm32h7xx_hal_tim.h
  • TIM_ICPOLARITY_RISING : stm32h7xx_hal_tim.h
  • TIM_ICPSC_DIV1 : stm32h7xx_hal_tim.h
  • TIM_ICPSC_DIV2 : stm32h7xx_hal_tim.h
  • TIM_ICPSC_DIV4 : stm32h7xx_hal_tim.h
  • TIM_ICPSC_DIV8 : stm32h7xx_hal_tim.h
  • TIM_ICSELECTION_DIRECTTI : stm32h7xx_hal_tim.h
  • TIM_ICSELECTION_INDIRECTTI : stm32h7xx_hal_tim.h
  • TIM_ICSELECTION_TRC : stm32h7xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE : stm32h7xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_FALLING : stm32h7xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_RISING : stm32h7xx_hal_tim.h
  • TIM_IT_BREAK : stm32h7xx_hal_tim.h
  • TIM_IT_CC1 : stm32h7xx_hal_tim.h
  • TIM_IT_CC2 : stm32h7xx_hal_tim.h
  • TIM_IT_CC3 : stm32h7xx_hal_tim.h
  • TIM_IT_CC4 : stm32h7xx_hal_tim.h
  • TIM_IT_COM : stm32h7xx_hal_tim.h
  • TIM_IT_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_IT_UPDATE : stm32h7xx_hal_tim.h
  • TIM_LOCKLEVEL_1 : stm32h7xx_hal_tim.h
  • TIM_LOCKLEVEL_2 : stm32h7xx_hal_tim.h
  • TIM_LOCKLEVEL_3 : stm32h7xx_hal_tim.h
  • TIM_LOCKLEVEL_OFF : stm32h7xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_DISABLE : stm32h7xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_ENABLE : stm32h7xx_hal_tim.h
  • TIM_OCFAST_DISABLE : stm32h7xx_hal_tim.h
  • TIM_OCFAST_ENABLE : stm32h7xx_hal_tim.h
  • TIM_OCIDLESTATE_RESET : stm32h7xx_hal_tim.h
  • TIM_OCIDLESTATE_SET : stm32h7xx_hal_tim.h
  • TIM_OCMODE_ACTIVE : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_ASSYMETRIC_PWM1 : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_ASSYMETRIC_PWM2 : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_COMBINED_PWM1 : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_COMBINED_PWM2 : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_FORCED_ACTIVE : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_FORCED_INACTIVE : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_INACTIVE : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_PWM1 : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_PWM2 : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_RETRIGERRABLE_OPM1 : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_RETRIGERRABLE_OPM2 : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_TIMING : stm32h7xx_hal_tim_ex.h
  • TIM_OCMODE_TOGGLE : stm32h7xx_hal_tim_ex.h
  • TIM_OCNIDLESTATE_RESET : stm32h7xx_hal_tim.h
  • TIM_OCNIDLESTATE_SET : stm32h7xx_hal_tim.h
  • TIM_OCNPOLARITY_HIGH : stm32h7xx_hal_tim.h
  • TIM_OCNPOLARITY_LOW : stm32h7xx_hal_tim.h
  • TIM_OCPOLARITY_HIGH : stm32h7xx_hal_tim.h
  • TIM_OCPOLARITY_LOW : stm32h7xx_hal_tim.h
  • TIM_OPMODE_REPETITIVE : stm32h7xx_hal_tim.h
  • TIM_OPMODE_SINGLE : stm32h7xx_hal_tim.h
  • TIM_OSSI_DISABLE : stm32h7xx_hal_tim.h
  • TIM_OSSI_ENABLE : stm32h7xx_hal_tim.h
  • TIM_OSSR_DISABLE : stm32h7xx_hal_tim.h
  • TIM_OSSR_ENABLE : stm32h7xx_hal_tim.h
  • TIM_OUTPUTSTATE_DISABLE : stm32h7xx_hal_tim.h
  • TIM_OUTPUTSTATE_ENABLE : stm32h7xx_hal_tim.h
  • TIM_RESET_CAPTUREPOLARITY : stm32h7xx_hal_tim.h
  • TIM_RESET_ICPRESCALERVALUE : stm32h7xx_hal_tim.h
  • TIM_SET_CAPTUREPOLARITY : stm32h7xx_hal_tim.h
  • TIM_SET_ICPRESCALERVALUE : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_DISABLE : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_EXTERNAL1 : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_GATED : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_RESET : stm32h7xx_hal_tim.h
  • TIM_SLAVEMODE_TRIGGER : stm32h7xx_hal_tim.h
  • TIM_TI1SELECTION_CH1 : stm32h7xx_hal_tim.h
  • TIM_TI1SELECTION_XORCOMBINATION : stm32h7xx_hal_tim.h
  • TIM_TIM15_BKR_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_BKR_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_BKR_DFSDM_BRK0 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_BKR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_RCC_CSI : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_RCC_LSE : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_RCC_MCO2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_TIM2_CH1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_TIM3_CH1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI1_TIM4_CH1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI2_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI2_TIM2_CH2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI2_TIM3_CH2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM15_TI2_TIM4_CH2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_BKR_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_BKR_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_BKR_DFSDM_BRK1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_BKR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_TI1_RCC_LSE : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_TI1_RCC_LSI : stm32h7xx_hal_tim_ex.h
  • TIM_TIM16_TI1_WKUP_IT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_BKR_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_BKR_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_BKR_DFSDM_BRK2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_BKR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_TI1_RCC_HSE1MHZ : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_TI1_RCC_MCO1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM17_TI1_SPDIF_FS : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_BKR2_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_BKR2_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_BKR2_DFSDM_BRK1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_BKR2_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_BKR_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_BKR_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_BKR_DFSDM_BRK0 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_BKR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD3 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC3_AWD1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC3_AWD2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC3_AWD3 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_TI1_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM1_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_RCC_LSE : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_SAI1_FSA : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_ETR_SAI1_FSB : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP1COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM2_TI4_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_ETR_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP1COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM3_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_ETR_SAI2_FSA : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_ETR_SAI2_FSB : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_TI1_CAN_RTP : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_TI1_CAN_TMP : stm32h7xx_hal_tim_ex.h
  • TIM_TIM5_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_BKR2_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_BKR2_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_BKR2_DFSDM_BRK3 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_BKR2_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_BKR_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_BKR_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_BKR_DFSDM_BRK2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_BKR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD3 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC3_AWD1 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC3_AWD2 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC3_AWD3 : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_COMP1_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_ETR_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_TI1_COMP2_OUT : stm32h7xx_hal_tim_ex.h
  • TIM_TIM8_TI1_GPIO : stm32h7xx_hal_tim_ex.h
  • TIM_TRGO2_ENABLE : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC1 : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC1REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC2REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC3REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC4REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_RISING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISINGFALLING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC5REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_RISING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC6REF : stm32h7xx_hal_tim.h
  • TIM_TRGO2_OC6REF_RISINGFALLING : stm32h7xx_hal_tim.h
  • TIM_TRGO2_RESET : stm32h7xx_hal_tim.h
  • TIM_TRGO2_UPDATE : stm32h7xx_hal_tim.h
  • TIM_TRGO_ENABLE : stm32h7xx_hal_tim.h
  • TIM_TRGO_OC1 : stm32h7xx_hal_tim.h
  • TIM_TRGO_OC1REF : stm32h7xx_hal_tim.h
  • TIM_TRGO_OC2REF : stm32h7xx_hal_tim.h
  • TIM_TRGO_OC3REF : stm32h7xx_hal_tim.h
  • TIM_TRGO_OC4REF : stm32h7xx_hal_tim.h
  • TIM_TRGO_RESET : stm32h7xx_hal_tim.h
  • TIM_TRGO_UPDATE : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_BOTHEDGE : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_FALLING : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_INVERTED : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_NONINVERTED : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_RISING : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV1 : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV2 : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV4 : stm32h7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV8 : stm32h7xx_hal_tim.h
  • TIM_TS_ETRF : stm32h7xx_hal_tim.h
  • TIM_TS_ITR0 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR1 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR2 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR3 : stm32h7xx_hal_tim.h
  • TIM_TS_ITR4 : stm32h7xx_hal_tim_ex.h
  • TIM_TS_ITR5 : stm32h7xx_hal_tim_ex.h
  • TIM_TS_ITR6 : stm32h7xx_hal_tim_ex.h
  • TIM_TS_ITR7 : stm32h7xx_hal_tim_ex.h
  • TIM_TS_ITR8 : stm32h7xx_hal_tim_ex.h
  • TIM_TS_NONE : stm32h7xx_hal_tim.h
  • TIM_TS_TI1F_ED : stm32h7xx_hal_tim.h
  • TIM_TS_TI1FP1 : stm32h7xx_hal_tim.h
  • TIM_TS_TI2FP2 : stm32h7xx_hal_tim.h
  • TIMEOUT_DAC_CALIBCONFIG : stm32h7xx_hal_dac.c
  • TIMING_CLEAR_MASK : stm32h7xx_hal_smbus.c , stm32h7xx_hal_i2c.c
  • TIMx_ETRSEL_MASK : stm32h7xx_hal_tim_ex.c
  • TIMx_TIxSEL_MASK : stm32h7xx_hal_tim_ex.c
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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- u -

  • UART_ADDRESS_DETECT_4B : stm32h7xx_hal_uart_ex.h
  • UART_ADDRESS_DETECT_7B : stm32h7xx_hal_uart_ex.h
  • UART_ADVFEATURE_AUTOBAUDRATE_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DATAINVERT_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DMA_DISABLEONRXERROR : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DMA_ENABLEONRXERROR : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_DMADISABLEONERROR_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_NO_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_RXINVERT_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_INIT : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_DISABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_ENABLE : stm32h7xx_hal_uart.h
  • UART_ADVFEATURE_TXINVERT_INIT : stm32h7xx_hal_uart.h
  • UART_AUTOBAUD_REQUEST : stm32h7xx_hal_uart.h
  • UART_CLEAR_CMF : stm32h7xx_hal_uart.h
  • UART_CLEAR_CTSF : stm32h7xx_hal_uart.h
  • UART_CLEAR_FEF : stm32h7xx_hal_uart.h
  • UART_CLEAR_IDLEF : stm32h7xx_hal_uart.h
  • UART_CLEAR_LBDF : stm32h7xx_hal_uart.h
  • UART_CLEAR_NEF : stm32h7xx_hal_uart.h
  • UART_CLEAR_OREF : stm32h7xx_hal_uart.h
  • UART_CLEAR_PEF : stm32h7xx_hal_uart.h
  • UART_CLEAR_RTOF : stm32h7xx_hal_uart.h
  • UART_CLEAR_TCF : stm32h7xx_hal_uart.h
  • UART_CLEAR_TXFECF : stm32h7xx_hal_uart.h
  • UART_CLEAR_WUF : stm32h7xx_hal_uart.h
  • UART_CR1_DEAT_ADDRESS_LSB_POS : stm32h7xx_hal_uart.h
  • UART_CR1_DEDT_ADDRESS_LSB_POS : stm32h7xx_hal_uart.h
  • UART_CR1_FIELDS : stm32h7xx_hal_uart.c
  • UART_CR2_ADDRESS_LSB_POS : stm32h7xx_hal_uart.h
  • UART_DE_POLARITY_HIGH : stm32h7xx_hal_uart.h
  • UART_DE_POLARITY_LOW : stm32h7xx_hal_uart.h
  • UART_DIV_LPUART : stm32h7xx_hal_uart.h
  • UART_DIV_SAMPLING16 : stm32h7xx_hal_uart.h
  • UART_DIV_SAMPLING8 : stm32h7xx_hal_uart.h
  • UART_DMA_RX_DISABLE : stm32h7xx_hal_uart.h
  • UART_DMA_RX_ENABLE : stm32h7xx_hal_uart.h
  • UART_DMA_TX_DISABLE : stm32h7xx_hal_uart.h
  • UART_DMA_TX_ENABLE : stm32h7xx_hal_uart.h
  • UART_FIFOMODE_DISABLE : stm32h7xx_hal_uart.h
  • UART_FIFOMODE_ENABLE : stm32h7xx_hal_uart.h
  • UART_FLAG_ABRE : stm32h7xx_hal_uart.h
  • UART_FLAG_ABRF : stm32h7xx_hal_uart.h
  • UART_FLAG_BUSY : stm32h7xx_hal_uart.h
  • UART_FLAG_CMF : stm32h7xx_hal_uart.h
  • UART_FLAG_CTS : stm32h7xx_hal_uart.h
  • UART_FLAG_CTSIF : stm32h7xx_hal_uart.h
  • UART_FLAG_FE : stm32h7xx_hal_uart.h
  • UART_FLAG_IDLE : stm32h7xx_hal_uart.h
  • UART_FLAG_LBDF : stm32h7xx_hal_uart.h
  • UART_FLAG_NE : stm32h7xx_hal_uart.h
  • UART_FLAG_ORE : stm32h7xx_hal_uart.h
  • UART_FLAG_PE : stm32h7xx_hal_uart.h
  • UART_FLAG_REACK : stm32h7xx_hal_uart.h
  • UART_FLAG_RTOF : stm32h7xx_hal_uart.h
  • UART_FLAG_RWU : stm32h7xx_hal_uart.h
  • UART_FLAG_RXFF : stm32h7xx_hal_uart.h
  • UART_FLAG_RXFNE : stm32h7xx_hal_uart.h
  • UART_FLAG_RXFT : stm32h7xx_hal_uart.h
  • UART_FLAG_RXNE : stm32h7xx_hal_uart.h
  • UART_FLAG_SBKF : stm32h7xx_hal_uart.h
  • UART_FLAG_TC : stm32h7xx_hal_uart.h
  • UART_FLAG_TEACK : stm32h7xx_hal_uart.h
  • UART_FLAG_TXE : stm32h7xx_hal_uart.h
  • UART_FLAG_TXFE : stm32h7xx_hal_uart.h
  • UART_FLAG_TXFNF : stm32h7xx_hal_uart.h
  • UART_FLAG_TXFT : stm32h7xx_hal_uart.h
  • UART_FLAG_WUF : stm32h7xx_hal_uart.h
  • UART_GETCLOCKSOURCE : stm32h7xx_hal_uart_ex.h
  • UART_HALF_DUPLEX_DISABLE : stm32h7xx_hal_uart.h
  • UART_HALF_DUPLEX_ENABLE : stm32h7xx_hal_uart.h
  • UART_HWCONTROL_CTS : stm32h7xx_hal_uart.h
  • UART_HWCONTROL_NONE : stm32h7xx_hal_uart.h
  • UART_HWCONTROL_RTS : stm32h7xx_hal_uart.h
  • UART_HWCONTROL_RTS_CTS : stm32h7xx_hal_uart.h
  • UART_INSTANCE_LOWPOWER : stm32h7xx_hal_uart.h
  • UART_IT_CM : stm32h7xx_hal_uart.h
  • UART_IT_CTS : stm32h7xx_hal_uart.h
  • UART_IT_ERR : stm32h7xx_hal_uart.h
  • UART_IT_FE : stm32h7xx_hal_uart.h
  • UART_IT_IDLE : stm32h7xx_hal_uart.h
  • UART_IT_LBD : stm32h7xx_hal_uart.h
  • UART_IT_MASK : stm32h7xx_hal_uart.h
  • UART_IT_NE : stm32h7xx_hal_uart.h
  • UART_IT_ORE : stm32h7xx_hal_uart.h
  • UART_IT_PE : stm32h7xx_hal_uart.h
  • UART_IT_RXFF : stm32h7xx_hal_uart.h
  • UART_IT_RXFT : stm32h7xx_hal_uart.h
  • UART_IT_RXNE : stm32h7xx_hal_uart.h
  • UART_IT_TC : stm32h7xx_hal_uart.h
  • UART_IT_TXE : stm32h7xx_hal_uart.h
  • UART_IT_TXFE : stm32h7xx_hal_uart.h
  • UART_IT_TXFT : stm32h7xx_hal_uart.h
  • UART_IT_WUF : stm32h7xx_hal_uart.h
  • UART_LIN_DISABLE : stm32h7xx_hal_uart.h
  • UART_LIN_ENABLE : stm32h7xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_10B : stm32h7xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_11B : stm32h7xx_hal_uart.h
  • UART_LPUART_BRR_MAX : stm32h7xx_hal_uart.c
  • UART_LPUART_BRR_MIN : stm32h7xx_hal_uart.c
  • UART_MASK_COMPUTATION : stm32h7xx_hal_uart_ex.h
  • UART_MODE_RX : stm32h7xx_hal_uart.h
  • UART_MODE_TX : stm32h7xx_hal_uart.h
  • UART_MODE_TX_RX : stm32h7xx_hal_uart.h
  • UART_MUTE_MODE_REQUEST : stm32h7xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_DISABLE : stm32h7xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_ENABLE : stm32h7xx_hal_uart.h
  • UART_OVERSAMPLING_16 : stm32h7xx_hal_uart.h
  • UART_OVERSAMPLING_8 : stm32h7xx_hal_uart.h
  • UART_PARITY_EVEN : stm32h7xx_hal_uart.h
  • UART_PARITY_NONE : stm32h7xx_hal_uart.h
  • UART_PARITY_ODD : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV1 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV10 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV12 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV128 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV16 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV2 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV256 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV32 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV4 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV6 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV64 : stm32h7xx_hal_uart.h
  • UART_PRESCALER_DIV8 : stm32h7xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_DISABLE : stm32h7xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_ENABLE : stm32h7xx_hal_uart.h
  • UART_RXDATA_FLUSH_REQUEST : stm32h7xx_hal_uart.h
  • UART_RXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_uart.h
  • UART_RXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_uart.h
  • UART_RXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_uart.h
  • UART_RXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_uart.h
  • UART_RXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_uart.h
  • UART_RXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_uart.h
  • UART_SENDBREAK_REQUEST : stm32h7xx_hal_uart.h
  • UART_STATE_DISABLE : stm32h7xx_hal_uart.h
  • UART_STATE_ENABLE : stm32h7xx_hal_uart.h
  • UART_STOPBITS_0_5 : stm32h7xx_hal_uart.h
  • UART_STOPBITS_1 : stm32h7xx_hal_uart.h
  • UART_STOPBITS_1_5 : stm32h7xx_hal_uart.h
  • UART_STOPBITS_2 : stm32h7xx_hal_uart.h
  • UART_TXDATA_FLUSH_REQUEST : stm32h7xx_hal_uart.h
  • UART_TXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_uart.h
  • UART_TXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_uart.h
  • UART_TXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_uart.h
  • UART_TXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_uart.h
  • UART_TXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_uart.h
  • UART_TXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_uart.h
  • UART_WAKEUP_ON_ADDRESS : stm32h7xx_hal_uart.h
  • UART_WAKEUP_ON_READDATA_NONEMPTY : stm32h7xx_hal_uart.h
  • UART_WAKEUP_ON_RXFIFO_FULL : stm32h7xx_hal_uart.h
  • UART_WAKEUP_ON_RXFIFO_THRESHOLD : stm32h7xx_hal_uart.h
  • UART_WAKEUP_ON_STARTBIT : stm32h7xx_hal_uart.h
  • UART_WAKEUP_ON_TXFIFO_EMPTY : stm32h7xx_hal_uart.h
  • UART_WAKEUP_ON_TXFIFO_THRESHOLD : stm32h7xx_hal_uart.h
  • UART_WAKEUPMETHOD_ADDRESSMARK : stm32h7xx_hal_uart.h
  • UART_WAKEUPMETHOD_IDLELINE : stm32h7xx_hal_uart.h
  • UART_WORDLENGTH_7B : stm32h7xx_hal_uart_ex.h
  • UART_WORDLENGTH_8B : stm32h7xx_hal_uart_ex.h
  • UART_WORDLENGTH_9B : stm32h7xx_hal_uart_ex.h
  • USART_CLEAR_FEF : stm32h7xx_hal_usart.h
  • USART_CLEAR_IDLEF : stm32h7xx_hal_usart.h
  • USART_CLEAR_NEF : stm32h7xx_hal_usart.h
  • USART_CLEAR_OREF : stm32h7xx_hal_usart.h
  • USART_CLEAR_PEF : stm32h7xx_hal_usart.h
  • USART_CLEAR_TCF : stm32h7xx_hal_usart.h
  • USART_CLEAR_TXFECF : stm32h7xx_hal_usart.h
  • USART_CLEAR_UDRCF : stm32h7xx_hal_usart.h
  • USART_CLOCK_DISABLE : stm32h7xx_hal_usart.h
  • USART_CLOCK_ENABLE : stm32h7xx_hal_usart.h
  • USART_CR1_FIELDS : stm32h7xx_hal_smartcard.c , stm32h7xx_hal_usart.c
  • USART_CR2_CLK_FIELDS : stm32h7xx_hal_smartcard.c
  • USART_CR2_FIELDS : stm32h7xx_hal_smartcard.c , stm32h7xx_hal_usart.c
  • USART_CR3_FIELDS : stm32h7xx_hal_smartcard.c , stm32h7xx_hal_uart.c , stm32h7xx_hal_usart.c
  • USART_DIV_SAMPLING8 : stm32h7xx_hal_usart.h
  • USART_DUMMY_DATA : stm32h7xx_hal_usart.c
  • USART_FIFOMODE_DISABLE : stm32h7xx_hal_usart.h
  • USART_FIFOMODE_ENABLE : stm32h7xx_hal_usart.h
  • USART_FLAG_BUSY : stm32h7xx_hal_usart.h
  • USART_FLAG_FE : stm32h7xx_hal_usart.h
  • USART_FLAG_IDLE : stm32h7xx_hal_usart.h
  • USART_FLAG_LBDF : stm32h7xx_hal_usart.h
  • USART_FLAG_NE : stm32h7xx_hal_usart.h
  • USART_FLAG_ORE : stm32h7xx_hal_usart.h
  • USART_FLAG_PE : stm32h7xx_hal_usart.h
  • USART_FLAG_REACK : stm32h7xx_hal_usart.h
  • USART_FLAG_RXFF : stm32h7xx_hal_usart.h
  • USART_FLAG_RXFNE : stm32h7xx_hal_usart.h
  • USART_FLAG_RXFT : stm32h7xx_hal_usart.h
  • USART_FLAG_RXNE : stm32h7xx_hal_usart.h
  • USART_FLAG_TC : stm32h7xx_hal_usart.h
  • USART_FLAG_TEACK : stm32h7xx_hal_usart.h
  • USART_FLAG_TXE : stm32h7xx_hal_usart.h
  • USART_FLAG_TXFE : stm32h7xx_hal_usart.h
  • USART_FLAG_TXFNF : stm32h7xx_hal_usart.h
  • USART_FLAG_TXFT : stm32h7xx_hal_usart.h
  • USART_FLAG_UDR : stm32h7xx_hal_usart.h
  • USART_GETCLOCKSOURCE : stm32h7xx_hal_usart.h
  • USART_IT_ERR : stm32h7xx_hal_usart.h
  • USART_IT_FE : stm32h7xx_hal_usart.h
  • USART_IT_IDLE : stm32h7xx_hal_usart.h
  • USART_IT_MASK : stm32h7xx_hal_usart.h
  • USART_IT_NE : stm32h7xx_hal_usart.h
  • USART_IT_ORE : stm32h7xx_hal_usart.h
  • USART_IT_PE : stm32h7xx_hal_usart.h
  • USART_IT_RXFF : stm32h7xx_hal_usart.h
  • USART_IT_RXFT : stm32h7xx_hal_usart.h
  • USART_IT_RXNE : stm32h7xx_hal_usart.h
  • USART_IT_TC : stm32h7xx_hal_usart.h
  • USART_IT_TXE : stm32h7xx_hal_usart.h
  • USART_IT_TXFE : stm32h7xx_hal_usart.h
  • USART_IT_TXFT : stm32h7xx_hal_usart.h
  • USART_IT_UDR : stm32h7xx_hal_usart.h
  • USART_LASTBIT_DISABLE : stm32h7xx_hal_usart.h
  • USART_LASTBIT_ENABLE : stm32h7xx_hal_usart.h
  • USART_MASK_COMPUTATION : stm32h7xx_hal_usart_ex.h
  • USART_MODE_RX : stm32h7xx_hal_usart.h
  • USART_MODE_TX : stm32h7xx_hal_usart.h
  • USART_MODE_TX_RX : stm32h7xx_hal_usart.h
  • USART_NSS_HW : stm32h7xx_hal_usart.h
  • USART_NSS_SW : stm32h7xx_hal_usart.h
  • USART_OVERSAMPLING_16 : stm32h7xx_hal_usart.h
  • USART_OVERSAMPLING_8 : stm32h7xx_hal_usart.h
  • USART_PARITY_EVEN : stm32h7xx_hal_usart.h
  • USART_PARITY_NONE : stm32h7xx_hal_usart.h
  • USART_PARITY_ODD : stm32h7xx_hal_usart.h
  • USART_PHASE_1EDGE : stm32h7xx_hal_usart.h
  • USART_PHASE_2EDGE : stm32h7xx_hal_usart.h
  • USART_POLARITY_HIGH : stm32h7xx_hal_usart.h
  • USART_POLARITY_LOW : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV1 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV10 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV12 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV128 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV16 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV2 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV256 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV32 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV4 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV6 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV64 : stm32h7xx_hal_usart.h
  • USART_PRESCALER_DIV8 : stm32h7xx_hal_usart.h
  • USART_RXDATA_FLUSH_REQUEST : stm32h7xx_hal_usart.h
  • USART_RXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_usart.h
  • USART_RXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_usart.h
  • USART_RXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_usart.h
  • USART_RXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_usart.h
  • USART_RXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_usart.h
  • USART_RXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_usart.h
  • USART_SLAVEMODE_DISABLE : stm32h7xx_hal_usart.h
  • USART_SLAVEMODE_ENABLE : stm32h7xx_hal_usart.h
  • USART_STOPBITS_0_5 : stm32h7xx_hal_usart.h
  • USART_STOPBITS_1 : stm32h7xx_hal_usart.h
  • USART_STOPBITS_1_5 : stm32h7xx_hal_usart.h
  • USART_STOPBITS_2 : stm32h7xx_hal_usart.h
  • USART_TEACK_REACK_TIMEOUT : stm32h7xx_hal_usart.c
  • USART_TXDATA_FLUSH_REQUEST : stm32h7xx_hal_usart.h
  • USART_TXFIFO_THRESHOLD_1_2 : stm32h7xx_hal_usart.h
  • USART_TXFIFO_THRESHOLD_1_4 : stm32h7xx_hal_usart.h
  • USART_TXFIFO_THRESHOLD_1_8 : stm32h7xx_hal_usart.h
  • USART_TXFIFO_THRESHOLD_3_4 : stm32h7xx_hal_usart.h
  • USART_TXFIFO_THRESHOLD_7_8 : stm32h7xx_hal_usart.h
  • USART_TXFIFO_THRESHOLD_8_8 : stm32h7xx_hal_usart.h
  • USART_WORDLENGTH_7B : stm32h7xx_hal_usart_ex.h
  • USART_WORDLENGTH_8B : stm32h7xx_hal_usart_ex.h
  • USART_WORDLENGTH_9B : stm32h7xx_hal_usart_ex.h
  • USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_LINE : stm32h7xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE : stm32h7xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_LINE : stm32h7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE : stm32h7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE : stm32h7xx_hal_pcd.h
  • USBD_FS_TRDT_VALUE : stm32h7xx_hal_pcd.h
  • USBD_HS_TRDT_VALUE : stm32h7xx_hal_pcd.h
  • USE_RTOS : stm32h7xx_hal_conf.h
  • USE_SD_TRANSCEIVER : stm32h7xx_hal_conf.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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- v -

  • VDD_VALUE : stm32h7xx_hal_conf.h
  • VREFBUF_TIMEOUT_VALUE : stm32h7xx_hal.c
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Globals

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- w -

  • WWDG_EWI_DISABLE : stm32h7xx_hal_wwdg.h
  • WWDG_EWI_ENABLE : stm32h7xx_hal_wwdg.h
  • WWDG_FLAG_EWIF : stm32h7xx_hal_wwdg.h
  • WWDG_IT_EWI : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_1 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_128 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_16 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_2 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_32 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_4 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_64 : stm32h7xx_hal_wwdg.h
  • WWDG_PRESCALER_8 : stm32h7xx_hal_wwdg.h
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal.h File Reference

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Defines | Functions
stm32h7xx_hal.h File Reference

This file contains all the functions prototypes for the HAL module driver. More...

#include "stm32h7xx_hal_conf.h"

Go to the source code of this file.

Defines

#define | SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT2
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT1
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT4
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT3
#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000)
#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ
#define | SYSCFG_ETH_MII ((uint32_t)0x00000000)
#define | SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2
#define | SYSCFG_SWITCH_PA0 SYSCFG_PMCR_PA0SO
#define | SYSCFG_SWITCH_PA1 SYSCFG_PMCR_PA1SO
#define | SYSCFG_SWITCH_PC2 SYSCFG_PMCR_PC2SO
#define | SYSCFG_SWITCH_PC3 SYSCFG_PMCR_PC3SO
#define | SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCR_PA0SO
#define | SYSCFG_SWITCH_PA0_CLOSE ((uint32_t)0x00000000)
#define | SYSCFG_SWITCH_PA1_OPEN SYSCFG_PMCR_PA1SO
#define | SYSCFG_SWITCH_PA1_CLOSE ((uint32_t)0x00000000)
#define | SYSCFG_SWITCH_PC2_OPEN SYSCFG_PMCR_PC2SO
#define | SYSCFG_SWITCH_PC2_CLOSE ((uint32_t)0x00000000)
#define | SYSCFG_SWITCH_PC3_OPEN SYSCFG_PMCR_PC3SO
#define | SYSCFG_SWITCH_PC3_CLOSE ((uint32_t)0x00000000)
#define | SYSCFG_BOOT_ADDR0 ((uint32_t)0x00000000)
#define | SYSCFG_BOOT_ADDR1 ((uint32_t)0x00000001)
#define | SYSCFG_CELL_CODE ((uint32_t)0x00000000)
#define | SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS
#define | EXTI_MODE_IT ((uint32_t)0x00010000)
#define | EXTI_MODE_EVT ((uint32_t)0x00020000)
#define | EXTI_RISING_EDGE ((uint32_t)0x00100000)
#define | EXTI_FALLING_EDGE ((uint32_t)0x00200000)
#define | EXTI_LINE0 ((uint32_t)0x00)
#define | EXTI_LINE1 ((uint32_t)0x01)
#define | EXTI_LINE2 ((uint32_t)0x02)
#define | EXTI_LINE3 ((uint32_t)0x03)
#define | EXTI_LINE4 ((uint32_t)0x04)
#define | EXTI_LINE5 ((uint32_t)0x05)
#define | EXTI_LINE6 ((uint32_t)0x06)
#define | EXTI_LINE7 ((uint32_t)0x07)
#define | EXTI_LINE8 ((uint32_t)0x08)
#define | EXTI_LINE9 ((uint32_t)0x09)
#define | EXTI_LINE10 ((uint32_t)0x0A)
#define | EXTI_LINE11 ((uint32_t)0x0B)
#define | EXTI_LINE12 ((uint32_t)0x0C)
#define | EXTI_LINE13 ((uint32_t)0x0D)
#define | EXTI_LINE14 ((uint32_t)0x0E)
#define | EXTI_LINE15 ((uint32_t)0x0F)
#define | EXTI_LINE16 ((uint32_t)0x10)
#define | EXTI_LINE17 ((uint32_t)0x11)
#define | EXTI_LINE18 ((uint32_t)0x12)
#define | EXTI_LINE19 ((uint32_t)0x13)
#define | EXTI_LINE20 ((uint32_t)0x14)
#define | EXTI_LINE21 ((uint32_t)0x15)
#define | EXTI_LINE22 ((uint32_t)0x16)
#define | EXTI_LINE23 ((uint32_t)0x17)
#define | EXTI_LINE24 ((uint32_t)0x18)
#define | EXTI_LINE25 ((uint32_t)0x19)
#define | EXTI_LINE26 ((uint32_t)0x1A)
#define | EXTI_LINE27 ((uint32_t)0x1B)
#define | EXTI_LINE28 ((uint32_t)0x1C)
#define | EXTI_LINE29 ((uint32_t)0x1D)
#define | EXTI_LINE30 ((uint32_t)0x1E)
#define | EXTI_LINE31 ((uint32_t)0x1F)
#define | EXTI_LINE32 ((uint32_t)0x20)
#define | EXTI_LINE33 ((uint32_t)0x21)
#define | EXTI_LINE34 ((uint32_t)0x22)
#define | EXTI_LINE35 ((uint32_t)0x23)
#define | EXTI_LINE36 ((uint32_t)0x24)
#define | EXTI_LINE37 ((uint32_t)0x25)
#define | EXTI_LINE38 ((uint32_t)0x26)
#define | EXTI_LINE39 ((uint32_t)0x27)
#define | EXTI_LINE40 ((uint32_t)0x28)
#define | EXTI_LINE41 ((uint32_t)0x29)
#define | EXTI_LINE42 ((uint32_t)0x2A)
#define | EXTI_LINE43 ((uint32_t)0x2B)
#define | EXTI_LINE44 ((uint32_t)0x2C)
#define | EXTI_LINE47 ((uint32_t)0x2F)
#define | EXTI_LINE48 ((uint32_t)0x30)
#define | EXTI_LINE49 ((uint32_t)0x31)
#define | EXTI_LINE50 ((uint32_t)0x32)
#define | EXTI_LINE51 ((uint32_t)0x33)
#define | EXTI_LINE52 ((uint32_t)0x34)
#define | EXTI_LINE53 ((uint32_t)0x35)
#define | EXTI_LINE54 ((uint32_t)0x36)
#define | EXTI_LINE55 ((uint32_t)0x37)
#define | EXTI_LINE56 ((uint32_t)0x38)
#define | EXTI_LINE57 ((uint32_t)0x39)
#define | EXTI_LINE58 ((uint32_t)0x3A)
#define | EXTI_LINE59 ((uint32_t)0x3B)
#define | EXTI_LINE60 ((uint32_t)0x3C)
#define | EXTI_LINE61 ((uint32_t)0x3D)
#define | EXTI_LINE62 ((uint32_t)0x3E)
#define | EXTI_LINE63 ((uint32_t)0x3F)
#define | EXTI_LINE64 ((uint32_t)0x40)
#define | EXTI_LINE65 ((uint32_t)0x41)
#define | EXTI_LINE66 ((uint32_t)0x42)
#define | EXTI_LINE67 ((uint32_t)0x43)
#define | EXTI_LINE68 ((uint32_t)0x44)
#define | EXTI_LINE69 ((uint32_t)0x45)
#define | EXTI_LINE70 ((uint32_t)0x46)
#define | EXTI_LINE71 ((uint32_t)0x47)
#define | EXTI_LINE72 ((uint32_t)0x48)
#define | EXTI_LINE73 ((uint32_t)0x49)
#define | EXTI_LINE74 ((uint32_t)0x4A)
#define | EXTI_LINE75 ((uint32_t)0x4B)
#define | EXTI_LINE76 ((uint32_t)0x4C)
#define | EXTI_LINE85 ((uint32_t)0x55)
#define | EXTI_LINE86 ((uint32_t)0x56)
#define | EXTI_LINE87 ((uint32_t)0x57)
#define | BDMA_CH6_CLEAR ((uint32_t)0x00000000)
#define | BDMA_CH7_CLEAR ((uint32_t)0x00000001)
#define | LPTIM4_OUT_CLEAR ((uint32_t)0x00000002)
#define | LPTIM5_OUT_CLEAR ((uint32_t)0x00000003)
#define | FMC_SWAPBMAP_DISABLE (0x00000000U)
#define | FMC_SWAPBMAP_SDRAM_SRAM FMC_BCR1_BMAP_0
#define | FMC_SWAPBMAP_SDRAMB2 FMC_BCR1_BMAP_1
#define | IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)
#define | IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)
#define | IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
#define | IS_SYSCFG_ETHERNET_CONFIG(CONFIG)
#define | IS_SYSCFG_ANALOG_SWITCH(SWITCH)
#define | IS_SYSCFG_SWITCH_STATE(STATE)
#define | IS_SYSCFG_BOOT_REGISTER(REGISTER)
#define | IS_SYSCFG_BOOT_ADDRESS(ADDRESS) ((ADDRESS) < PERIPH_BASE)
#define | IS_SYSCFG_CODE_SELECT(SELECT)
#define | IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10))
#define | IS_EXTI_EDGE_LINE(EDGE) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE))
#define | IS_EXTI_MODE_LINE(MODE) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT))
#define | IS_EXTI_CONFIG_LINE(LINE)
#define | IS_EXTI_ALL_LINE(LINE)
#define | IS_EXTI_D1_LINE(LINE)
#define | IS_EXTI_D3_LINE(LINE)
#define | IS_EXTI_D3_CLEAR(SOURCE)
#define | IS_FMC_SWAPBMAP_MODE(__MODE__)
#define | __HAL_DBGMCU_FREEZE_WWDG1() (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1))
Freeze/Unfreeze Peripherals in Debug mode.
#define | __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2))
#define | __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3))
#define | __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4))
#define | __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5))
#define | __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6))
#define | __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7))
#define | __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12))
#define | __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13))
#define | __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14))
#define | __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1))
#define | __HAL_DBGMCU_FREEZE_I2C1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1))
#define | __HAL_DBGMCU_FREEZE_I2C2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2))
#define | __HAL_DBGMCU_FREEZE_I2C3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3))
#define | __HAL_DBGMCU_FREEZE_FDCAN() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN))
#define | __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1))
#define | __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8))
#define | __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15))
#define | __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16))
#define | __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17))
#define | __HAL_DBGMCU_FREEZE_HRTIM() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM))
#define | __HAL_DBGMCU_FREEZE_I2C4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4))
#define | __HAL_DBGMCU_FREEZE_LPTIM2() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2))
#define | __HAL_DBGMCU_FREEZE_LPTIM3() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3))
#define | __HAL_DBGMCU_FREEZE_LPTIM4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4))
#define | __HAL_DBGMCU_FREEZE_LPTIM5() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5))
#define | __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC))
#define | __HAL_DBGMCU_FREEZE_IWDG1() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1))
#define | __HAL_DBGMCU_UnFreeze_WWDG1() (DBGMCU->APB3FZ1 &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1))
#define | __HAL_DBGMCU_UnFreeze_TIM2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2))
#define | __HAL_DBGMCU_UnFreeze_TIM3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3))
#define | __HAL_DBGMCU_UnFreeze_TIM4() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4))
#define | __HAL_DBGMCU_UnFreeze_TIM5() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5))
#define | __HAL_DBGMCU_UnFreeze_TIM6() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6))
#define | __HAL_DBGMCU_UnFreeze_TIM7() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7))
#define | __HAL_DBGMCU_UnFreeze_TIM12() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12))
#define | __HAL_DBGMCU_UnFreeze_TIM13() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13))
#define | __HAL_DBGMCU_UnFreeze_TIM14() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14))
#define | __HAL_DBGMCU_UnFreeze_LPTIM1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1))
#define | __HAL_DBGMCU_UnFreeze_I2C1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1))
#define | __HAL_DBGMCU_UnFreeze_I2C2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2))
#define | __HAL_DBGMCU_UnFreeze_I2C3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3))
#define | __HAL_DBGMCU_UnFreeze_FDCAN() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN))
#define | __HAL_DBGMCU_UnFreeze_TIM1() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM1))
#define | __HAL_DBGMCU_UnFreeze_TIM8() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM8))
#define | __HAL_DBGMCU_UnFreeze_TIM15() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM15))
#define | __HAL_DBGMCU_UnFreeze_TIM16() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM16))
#define | __HAL_DBGMCU_UnFreeze_TIM17() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM17))
#define | __HAL_DBGMCU_UnFreeze_HRTIM() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM))
#define | __HAL_DBGMCU_UnFreeze_I2C4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_I2C4))
#define | __HAL_DBGMCU_UnFreeze_LPTIM2() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2))
#define | __HAL_DBGMCU_UnFreeze_LPTIM3() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3))
#define | __HAL_DBGMCU_UnFreeze_LPTIM4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4))
#define | __HAL_DBGMCU_UnFreeze_LPTIM5() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5))
#define | __HAL_DBGMCU_UnFreeze_RTC() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_RTC))
#define | __HAL_DBGMCU_UnFreeze_IWDG1() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1))

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configures the SysTick to generate an interrupt each 1 millisecond, which is clocked by the HSI (at this stage, the clock is not yet configured and thus the system is running from the internal HSI at 16 MHz).
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the systick.
__weak void | HAL_MspInit (void)
Initializes the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base.
__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak void | HAL_Delay (__IO uint32_t Delay)
This function provides accurate delay (in milliseconds) based on variable incremented.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
void | HAL_SYSCFG_ETHInterfaceSelect (uint32_t SYSCFG_ETHInterface)
Ethernet PHY Interface Selection either MII or RMII.
void | HAL_SYSCFG_AnalogSwitchConfig (uint32_t SYSCFG_AnalogSwitch, uint32_t SYSCFG_SwitchState)
Analog Switch control for dual analog pads.
void | HAL_SYSCFG_EnableBOOST (void)
Enables the booster to reduce the total harmonic distortion of the analog switch when the supply voltage is lower than 2.7 V.
void | HAL_SYSCFG_DisableBOOST (void)
Disables the booster.
void | HAL_SYSCFG_CM7BootAddConfig (uint32_t BootRegister, uint32_t BootAddress)
BootCM7 address 0 configuration.
void | HAL_EnableCompensationCell (void)
Enables the I/O Compensation Cell.
void | HAL_DisableCompensationCell (void)
Power-down the I/O Compensation Cell.
void | HAL_SYSCFG_EnableIOSpeedOptimize (void)
To Enable optimize the I/O speed when the product voltage is low.
void | HAL_SYSCFG_DisableIOSpeedOptimize (void)
To Disable optimize the I/O speed when the product voltage is low.
void | HAL_SYSCFG_CompensationCodeSelect (uint32_t SYSCFG_CompCode)
Code selection for the I/O Compensation cell.
void | HAL_SYSCFG_CompensationCodeConfig (uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode)
Code selection for the I/O Compensation cell.
void | HAL_EnableDBGSleepMode (void)
Enable the Debug Module during Domain1 SLEEP mode.
void | HAL_DisableDBGSleepMode (void)
Disable the Debug Module during Domain1 SLEEP mode.
void | HAL_EnableDBGStopMode (void)
Enable the Debug Module during Domain1 STOP mode.
void | HAL_DisableDBGStopMode (void)
Disable the Debug Module during Domain1 STOP mode.
void | HAL_EnableDBGStandbyMode (void)
Enable the Debug Module during Domain1 STANDBY mode.
void | HAL_DisableDBGStandbyMode (void)
Disable the Debug Module during Domain1 STANDBY mode.
void | HAL_EnableDomain3DBGStopMode (void)
Enable the Debug Module during Domain3 STOP mode.
void | HAL_DisableDomain3DBGStopMode (void)
Disable the Debug Module during Domain3 STOP mode.
void | HAL_EnableDomain3DBGStandbyMode (void)
Enable the Debug Module during Domain3 STANDBY mode.
void | HAL_DisableDomain3DBGStandbyMode (void)
Disable the Debug Module during Domain3 STANDBY mode.
void | HAL_EXTI_EdgeConfig (uint32_t EXTI_Line, uint32_t EXTI_Edge)
Configure the EXTI input event line edge.
void | HAL_EXTI_GenerateSWInterrupt (uint32_t EXTI_Line)
Generates a Software interrupt on selected EXTI line.
void | HAL_EXTI_D1_ClearFlag (uint32_t EXTI_Line)
Clears the EXTI's line pending flags for Domain D1.
void | HAL_EXTI_D1_EventInputConfig (uint32_t EXTI_Line, uint32_t EXTI_Mode, uint32_t EXTI_LineCmd)
Configure the EXTI input event line for Domain D1.
void | HAL_EXTI_D3_EventInputConfig (uint32_t EXTI_Line, uint32_t EXTI_LineCmd, uint32_t EXTI_ClearSrc)
Configure the EXTI input event line for Domain D3.
void | HAL_SetFMCMemorySwappingConfig (uint32_t BankMapConfig)
Set the FMC Memory Mapping Swapping config.
uint32_t | HAL_GetFMCMemorySwappingConfig (void)
Get FMC Bank mapping mode.
void | HAL_SYSCFG_VREFBUF_VoltageScalingConfig (uint32_t VoltageScaling)
Configure the internal voltage reference buffer voltage scale.
void | HAL_SYSCFG_VREFBUF_HighImpedanceConfig (uint32_t Mode)
Configure the internal voltage reference buffer high impedance mode.
void | HAL_SYSCFG_VREFBUF_TrimmingConfig (uint32_t TrimmingValue)
Tune the Internal Voltage Reference buffer (VREFBUF).
HAL_StatusTypeDef | HAL_SYSCFG_EnableVREFBUF (void)
Enable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_DisableVREFBUF (void)
Disable the Internal Voltage Reference buffer (VREFBUF).

Detailed Description

This file contains all the functions prototypes for the HAL module driver.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal.h.

Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_adc.h File Reference

  • File List
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Data Structures | Defines | Functions
stm32h7xx_hal_adc.h File Reference

Header file of ADC HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_adc_ex.h"

Go to the source code of this file.

Data Structures

struct | ADC_OversamplingTypeDef
ADC Regular Conversion Oversampling structure definition. More...
struct | ADC_InitTypeDef
Structure definition of ADC instance and ADC group regular. More...
struct | ADC_AnalogWDGConfTypeDef
Structure definition of ADC analog watchdog. More...

Defines

#define | HAL_ADC_STATE_RESET ((uint32_t)0x00000000)
HAL ADC state machine: ADC states definition (bitfields)
#define | HAL_ADC_STATE_READY ((uint32_t)0x00000001)
#define | HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002)
#define | HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004)
#define | HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010)
#define | HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020)
#define | HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040)
#define | HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100)
#define | HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200)
#define | HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400)
#define | HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800)
#define | HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000)
#define | HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000)
#define | HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000)
#define | HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000)
#define | HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000)
#define | HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000)
#define | HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000)
#define | HAL_ADC_ERROR_NONE ((uint32_t)0x00)
#define | HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01)
#define | HAL_ADC_ERROR_OVR ((uint32_t)0x02)
#define | HAL_ADC_ERROR_DMA ((uint32_t)0x04)
#define | HAL_ADC_ERROR_JQOVF ((uint32_t)0x08)
#define | ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CCR_CKMODE_0)
#define | ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CCR_CKMODE_1)
#define | ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_CKMODE)
#define | ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
#define | ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
#define | ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
#define | ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000)
#define | ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_PRESC_0)
#define | ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_PRESC_1)
#define | ADC_CLOCK_ASYNC_DIV6 ((uint32_t)(ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))
#define | ADC_CLOCK_ASYNC_DIV8 ((uint32_t)(ADC_CCR_PRESC_2))
#define | ADC_CLOCK_ASYNC_DIV10 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_0))
#define | ADC_CLOCK_ASYNC_DIV12 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1))
#define | ADC_CLOCK_ASYNC_DIV16 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))
#define | ADC_CLOCK_ASYNC_DIV32 ((uint32_t)(ADC_CCR_PRESC_3))
#define | ADC_CLOCK_ASYNC_DIV64 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_0))
#define | ADC_CLOCK_ASYNC_DIV128 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1))
#define | ADC_CLOCK_ASYNC_DIV256 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))
#define | ADC_RESOLUTION_16B ((uint32_t)0x00000000)
#define | ADC_RESOLUTION_14B ((uint32_t)ADC_CFGR_RES_0)
#define | ADC_RESOLUTION_12B ((uint32_t)ADC_CFGR_RES_1)
#define | ADC_RESOLUTION_10B ((uint32_t)(ADC_CFGR_RES_1 | ADC_CFGR_RES_0))
#define | ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_2)
#define | ADC_SCAN_DISABLE ((uint32_t)0x00000000)
#define | ADC_SCAN_ENABLE ((uint32_t)0x00000001)
#define | ADC_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
#define | ADC_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
#define | ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
#define | ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
#define | ADC_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3)
#define | ADC_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
#define | ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
#define | ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
#define | ADC_EXTERNALTRIG_T3_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_HR1_ADCTRG1 ((uint32_t) ADC_CFGR_EXTSEL_4)
#define | ADC_EXTERNALTRIG_HR1_ADCTRG3 ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_LPTIM1_OUT ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1))
#define | ADC_EXTERNALTRIG_LPTIM2_OUT ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1| ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_LPTIM3_OUT ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2))
#define | ADC_SOFTWARE_START ((uint32_t)0x00000001)
#define | ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0)
#define | ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1)
#define | ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN)
#define | ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
#define | ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
#define | ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000)
#define | ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR_OVRMOD)
#define | ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
#define | ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
#define | ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
#define | ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
#define | ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
#define | ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
#define | ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
#define | ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
#define | ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
#define | ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
#define | ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
#define | ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
#define | ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
#define | ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
#define | ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
#define | ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)
#define | ADC_CHANNEL_0 ((uint32_t)(0x00000000))
#define | ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ10_1))
#define | ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ10_2))
#define | ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
#define | ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ10_3))
#define | ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1))
#define | ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2))
#define | ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
#define | ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ10_4))
#define | ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1))
#define | ADC_CHANNEL_19 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1| ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_17
#define | ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_18
#define | ADC_CHANNEL_VREFINT ADC_CHANNEL_19
#define | ADC_CHANNEL_DAC1CH1_ADC2 (ADC_CHANNEL_16)
#define | ADC_CHANNEL_DAC1CH2_ADC2 (ADC_CHANNEL_17)
#define | ADC_CONVERSIONDATA_DR ((uint32_t)0x00000000)
#define | ADC_CONVERSIONDATA_DFSDM ((uint32_t)ADC_CFGR_DMNGT_1)
#define | ADC_CONVERSIONDATA_DMA_ONESHOT ((uint32_t)ADC_CFGR_DMNGT_0)
#define | ADC_CONVERSIONDATA_DMA_CIRCULAR ((uint32_t)(ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1))
#define | IS_ADC_CONVERSIONDATAMGT(DATA)
Verify the ADC data conversion setting.
#define | ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)
Test if conversion trigger of regular group is software start or external trigger.
#define | ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)
Returns resolution bits in CFGR register: RES[1:0].
#define | ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
Clear ADC error code (set it to error code: "no error")
#define | ADC_IS_ENABLE(__HANDLE__)
Verification of ADC state: enabled or disabled.
#define | ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__)
Check if no conversion on going on regular group.
#define | ADC_STATE_CLR_SET MODIFY_REG
Simultaneously clears and sets specific bits of the handle State.
#define | IS_ADC_RANGE(RESOLUTION, ADC_VALUE)
Verify that a given value is aligned with the ADC resolution range.
#define | IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
Verify the length of the scheduled regular conversions group.
#define | IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
Verify the number of scheduled regular conversions in discontinuous mode.
#define | IS_ADC_CLOCKPRESCALER(ADC_CLOCK)
Verify the ADC clock setting.
#define | IS_ADC_RESOLUTION(RESOLUTION)
Verify the ADC resolution setting.
#define | IS_ADC_RESOLUTION_8_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B))
Verify the ADC resolution setting when limited to 8 bits.
#define | IS_ADC_SCAN_MODE(SCAN_MODE)
Verify the ADC scan mode.
#define | IS_ADC_EXTTRIG_EDGE(EDGE)
Verify the ADC edge trigger setting for regular group.
#define | IS_ADC_EXTTRIG(REGTRIG)
Verify the ADC regular conversions external trigger.
#define | IS_ADC_EOC_SELECTION(EOC_SELECTION)
Verify the ADC regular conversions check for converted data availability.
#define | IS_ADC_OVERRUN(OVR)
Verify the ADC regular conversions overrun handling.
#define | IS_ADC_SAMPLE_TIME(TIME)
Verify the ADC conversions sampling time.
#define | IS_ADC_REGULAR_RANK(__CHANNEL__)
Verify the ADC regular channel setting.
#define | ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 5)
#define | ADC_TEMPSENSOR_DELAY_US ((uint32_t) 120)
#define | ADC_STAB_DELAY_US ((uint32_t) 10)
#define | __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
Reset ADC handle state.
#define | __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Checks if the specified ADC interrupt source is enabled or disabled.
#define | __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Enable an ADC interrupt.
#define | __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Disable an ADC interrupt.
#define | __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
Checks whether the specified ADC flag is set or not.
#define | __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
Clear a specified ADC flag.

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initialize the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitialize the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enable ADC, starts conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for ADC event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start conversion of regular group and transfer result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handle ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non-blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non-blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog 1 callback in non-blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).
HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configure a channel to be assigned to ADC group regular.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configure the analog watchdog.
uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
Return the ADC handle state.
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.
HAL_StatusTypeDef | ADC_ConversionStop (ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
Stop ADC conversion.
HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_Disable (ADC_HandleTypeDef *hadc)
Disable the selected ADC.
void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

Header file of ADC HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_adc.h.

Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_adc_ex.h File Reference

  • File List
  • Globals
  • Drivers
  • STM32H7xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32h7xx_hal_adc_ex.h File Reference

Header file of ADC HAL extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | ADC_InjectionConfigTypeDef
ADC group injected contexts queue configuration. More...
struct | ADC_HandleTypeDef
ADC handle Structure definition. More...
struct | ADC_InjOversamplingTypeDef
ADC Injected Conversion Oversampling structure definition. More...
struct | ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group. More...
struct | ADC_InjectionConfTypeDef
Structure definition of ADC group injected and ADC channel affected to ADC group injected. More...
struct | ADC_MultiModeTypeDef
Structure definition of ADC MultiMode. More...

Defines

#define | ADC_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
#define | ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
#define | ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
#define | ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
#define | ADC_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
#define | ADC_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2 ((uint32_t)ADC_JSQR_JEXTSEL_4)
#define | ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4 ((uint32_t)(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_LPTIM1_OUT ((uint32_t)(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJEC_LPTIM2_OUT ((uint32_t)(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_LPTIM3_OUT ((uint32_t)(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2))
#define | ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN)
#define | ADC_SINGLE_ENDED ((uint32_t)0x00000000)
#define | ADC_DIFFERENTIAL_ENDED ((uint32_t)ADC_CR_ADCALDIF)
#define | ADC_OFFSET_NONE ((uint32_t)0x00)
#define | ADC_OFFSET_1 ((uint32_t)0x01)
#define | ADC_OFFSET_2 ((uint32_t)0x02)
#define | ADC_OFFSET_3 ((uint32_t)0x03)
#define | ADC_OFFSET_4 ((uint32_t)0x04)
#define | ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
#define | ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
#define | ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
#define | ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
#define | ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000))
#define | ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_0))
#define | ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_1))
#define | ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0))
#define | ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0))
#define | ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1))
#define | ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0))
#define | ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0))
#define | ADC_DUALMODEDATAFORMAT_DISABLED ((uint32_t)0x00000000)
#define | ADC_DUALMODEDATAFORMAT_32_10_BITS ((uint32_t)ADC_CCR_DAMDF_1)
#define | ADC_DUALMODEDATAFORMAT_8_BITS ((uint32_t)(ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1))
#define | ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000))
#define | ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)(ADC_CCR_DELAY_2))
#define | ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)(ADC_CCR_DELAY_3))
#define | ADC_ANALOGWATCHDOG_1 ((uint32_t)0x00000001)
#define | ADC_ANALOGWATCHDOG_2 ((uint32_t)0x00000002)
#define | ADC_ANALOGWATCHDOG_3 ((uint32_t)0x00000003)
#define | ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000)
#define | ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN))
#define | ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN))
#define | ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))
#define | ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR_AWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CFGR_JAWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))
#define | ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))
#define | ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS))
#define | ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS))
#define | ADC_EOSMP_EVENT ((uint32_t)ADC_FLAG_EOSMP)
#define | ADC_AWD1_EVENT ((uint32_t)ADC_FLAG_AWD1)
#define | ADC_AWD2_EVENT ((uint32_t)ADC_FLAG_AWD2)
#define | ADC_AWD3_EVENT ((uint32_t)ADC_FLAG_AWD3)
#define | ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
#define | ADC_JQOVF_EVENT ((uint32_t)ADC_FLAG_JQOVF)
#define | ADC_AWD_EVENT ADC_AWD1_EVENT
#define | ADC_IT_RDY ADC_IER_RDY
#define | ADC_IT_EOSMP ADC_IER_EOSMP
#define | ADC_IT_EOC ADC_IER_EOC
#define | ADC_IT_EOS ADC_IER_EOS
#define | ADC_IT_OVR ADC_IER_OVR
#define | ADC_IT_JEOC ADC_IER_JEOC
#define | ADC_IT_JEOS ADC_IER_JEOS
#define | ADC_IT_AWD1 ADC_IER_AWD1
#define | ADC_IT_AWD2 ADC_IER_AWD2
#define | ADC_IT_AWD3 ADC_IER_AWD3
#define | ADC_IT_JQOVF ADC_IER_JQOVF
#define | ADC_IT_AWD ADC_IT_AWD1
#define | ADC_FLAG_RDY ADC_ISR_ADRD
#define | ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | ADC_FLAG_EOC ADC_ISR_EOC
#define | ADC_FLAG_EOS ADC_ISR_EOS
#define | ADC_FLAG_OVR ADC_ISR_OVR
#define | ADC_FLAG_JEOC ADC_ISR_JEOC
#define | ADC_FLAG_JEOS ADC_ISR_JEOS
#define | ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | ADC_FLAG_AWD3 ADC_ISR_AWD3
#define | ADC_FLAG_JQOVF ADC_ISR_JQOVF
#define | ADC_FLAG_AWD ADC_FLAG_AWD1
#define | ADC_FLAG_ALL
#define | ADC_FLAG_POSTCONV_ALL
#define | ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000)
#define | ADC_RIGHTBITSHIFT_1 ((uint32_t)ADC_CFGR2_OVSS_0)
#define | ADC_RIGHTBITSHIFT_2 ((uint32_t)ADC_CFGR2_OVSS_1)
#define | ADC_RIGHTBITSHIFT_3 ((uint32_t)(ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0))
#define | ADC_RIGHTBITSHIFT_4 ((uint32_t)ADC_CFGR2_OVSS_2)
#define | ADC_RIGHTBITSHIFT_5 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0))
#define | ADC_RIGHTBITSHIFT_6 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1))
#define | ADC_RIGHTBITSHIFT_7 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0))
#define | ADC_RIGHTBITSHIFT_8 ((uint32_t)ADC_CFGR2_OVSS_3)
#define | ADC_RIGHTBITSHIFT_9 ((uint32_t)(ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0))
#define | ADC_RIGHTBITSHIFT_10 ((uint32_t)(ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1))
#define | ADC_RIGHTBITSHIFT_11 ((uint32_t)(ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0))
#define | ADC_LEFTBITSHIFT_NONE ((uint32_t)0x00000000)
#define | ADC_LEFTBITSHIFT_1 ((uint32_t)ADC_CFGR2_LSHIFT_0)
#define | ADC_LEFTBITSHIFT_2 ((uint32_t)ADC_CFGR2_LSHIFT_1)
#define | ADC_LEFTBITSHIFT_3 ((uint32_t)(ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0))
#define | ADC_LEFTBITSHIFT_4 ((uint32_t)ADC_CFGR2_LSHIFT_2)
#define | ADC_LEFTBITSHIFT_5 ((uint32_t)(ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0))
#define | ADC_LEFTBITSHIFT_6 ((uint32_t)(ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1))
#define | ADC_LEFTBITSHIFT_7 ((uint32_t)(ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0))
#define | ADC_LEFTBITSHIFT_8 ((uint32_t)ADC_CFGR2_LSHIFT_3)
#define | ADC_LEFTBITSHIFT_9 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0))
#define | ADC_LEFTBITSHIFT_10 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1))
#define | ADC_LEFTBITSHIFT_11 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0))
#define | ADC_LEFTBITSHIFT_12 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2))
#define | ADC_LEFTBITSHIFT_13 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0))
#define | ADC_LEFTBITSHIFT_14 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1))
#define | ADC_LEFTBITSHIFT_15 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0))
#define | ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000)
#define | ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)ADC_CFGR2_TROVS)
#define | ADC_REGOVERSAMPLING_CONTINUED_MODE ((uint32_t)0x00000000)
#define | ADC_REGOVERSAMPLING_RESUMED_MODE ((uint32_t)ADC_CFGR2_ROVSM)
#define | ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000)
#define | ADC_SAMPLETIME_2CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_0)
#define | ADC_SAMPLETIME_8CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_1)
#define | ADC_SAMPLETIME_16CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0))
#define | ADC_SAMPLETIME_32CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_2)
#define | ADC_SAMPLETIME_64CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0))
#define | ADC_SAMPLETIME_387CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1))
#define | ADC_SAMPLETIME_810CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10)
#define | ADC_CALIB_OFFSET ((uint32_t)0x00000000)
#define | ADC_CALIB_OFFSET_LINEARITY (ADC_CR_ADCALLIN)
#define | IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
Verify the length of scheduled injected conversions group.
#define | IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= ((uint32_t)0x7F))
Calibration factor length verification (7 bits maximum)
#define | IS_ADC_CHANNEL(__CHANNEL__)
Verify the ADC channel setting.
#define | IS_ADC1_DIFF_CHANNEL(__CHANNEL__)
Verify the ADC channel setting in differential mode for ADC1.
#define | IS_ADC2_DIFF_CHANNEL(__CHANNEL__)
Verify the ADC channel setting in differential mode for ADC2.
#define | IS_ADC3_DIFF_CHANNEL(__CHANNEL__)
Verify the ADC channel setting in differential mode for ADC3.
#define | ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
Test if conversion trigger of injected group is software start or external trigger.
#define | ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__)
Check if no conversion on going on regular or injected groups.
#define | ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__)
Check if no conversion on going on injected group.
#define | ADC_IS_INDEPENDENT(__HANDLE__)
Check whether or not ADC is independent.
#define | ADC_SMPR1(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << (POSITION_VAL(ADC_SMPR1_SMP1) * (__CHANNELNB__)))
Set the ADC's sample time for Channels numbers between 0 and 9.
#define | ADC_SMPR2(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << ((POSITION_VAL(ADC_SMPR2_SMP11) * ((__CHANNELNB__) - 10))))
Set the ADC's sample time for Channels numbers between 10 and 18.
#define | ADC_SQR1_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR1_SQ1) * (__RANKNB__)))
Set the selected regular Channel rank for rank between 1 and 4.
#define | ADC_SQR2_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR2_SQ6) * ((__RANKNB__) - 5)))
Set the selected regular Channel rank for rank between 5 and 9.
#define | ADC_SQR3_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR3_SQ11) * ((__RANKNB__) - 10)))
Set the selected regular Channel rank for rank between 10 and 14.
#define | ADC_SQR4_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR4_SQ16) * ((__RANKNB__) - 15)))
Set the selected regular Channel rank for rank between 15 and 16.
#define | ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << ((POSITION_VAL(ADC_JSQR_JSQ1)-3) * (__RANKNB__) +3))
Set the selected injected Channel rank.
#define | ADC_CFGR_SET_AWD1CH(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_CFGR_AWD1CH))
Set the Analog Watchdog 1 channel.
#define | ADC_CFGR_SET_AWD23CR(__CHANNEL__) (1U << (__CHANNEL__))
Configure the channel number into Analog Watchdog 2 or 3.
#define | ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((uint32_t)(__INJECT_CONTEXT_QUEUE_MODE__) << POSITION_VAL(ADC_CFGR_JQM))
Enable ADC injected context queue.
#define | ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_JDISCEN))
Enable ADC discontinuous conversion mode for injected group.
#define | ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_DISCEN))
Enable ADC discontinuous conversion mode for regular group.
#define | ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << POSITION_VAL(ADC_CFGR_DISCNUM))
Configures the number of discontinuous conversions for regular group.
#define | ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << POSITION_VAL(ADC_CFGR_AUTDLY))
Enable the ADC auto delay mode.
#define | ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_CONT))
Enable ADC continuous conversion mode.
#define | ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__))
Enable the ADC DMA continuous request.
#define | ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_OFR1_OFFSET1_CH))
Configure the channel number into offset OFRx register.
#define | ADC_DIFSEL_CHANNEL(__CHANNEL__) (1U << (__CHANNEL__))
Configure the channel number into differential mode selection register.
#define | ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D >> POSITION_VAL(ADC_CALFACT_CALFACT_D)) ) << POSITION_VAL(ADC_CALFACT_CALFACT_D))
Calibration factor in differential mode to be set into calibration register.
#define | ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> POSITION_VAL(ADC_CALFACT_CALFACT_D))
Calibration factor in differential mode to be retrieved from calibration register.
#define | ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16)
Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
#define | ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CCR_DMACFG))
Enable the ADC DMA continuous request for ADC multimode.
#define | ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
Enable the ADC peripheral.
#define | ADC_ENABLING_CONDITIONS(__HANDLE__)
Verification of hardware constraints before ADC can be enabled.
#define | ADC_DISABLE(__HANDLE__)
Disable the ADC peripheral.
#define | ADC_DISABLING_CONDITIONS(__HANDLE__)
Verification of hardware constraints before ADC can be disabled.
#define | ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 2)*2))
Shift the offset in function of the selected ADC resolution.
#define | ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 2)*2))
Shift the AWD1 threshold in function of the selected ADC resolution.
#define | ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 2)*2))
Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.
#define | ADC12_COMMON_REGISTER(__HANDLE__) (ADC12_COMMON)
Report common register to ADC1 and ADC2.
#define | ADC3_COMMON_REGISTER(__HANDLE__) (ADC3_COMMON)
Report common register to ADC1 and ADC2.
#define | ADC_MASTER_REGISTER(__HANDLE__)
Report Master Instance.
#define | ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__)
Check whether or not dual regular conversions are enabled.
#define | ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)
Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master.
#define | ADC3_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)
Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master.
#define | ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__)
Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled.
#define | ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__)
Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled.
#define | ADC_INSTANCE_IS_ENABLED(__INSTANCE__)
Verification of ADC state: enabled or disabled, directly checked on instance as input parameter.
#define | ADC_ANY_OTHER_ENABLED(__HANDLE__)
Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle.
#define | ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
Set handle instance of the ADC slave associated to the ADC master.
#define | IS_ADC_SINGLE_DIFFERENTIAL(SING_DIFF)
Verify the ADC single-ended input or differential mode setting.
#define | IS_ADC_OFFSET_NUMBER(OFFSET_NUMBER)
Verify the ADC offset management setting.
#define | IS_ADC_INJECTED_RANK(CHANNEL)
Verify the ADC injected channel setting.
#define | IS_ADC_EXTTRIGINJEC(INJTRIG)
Verify the ADC injected conversions external trigger.
#define | IS_ADC_EXTTRIGINJEC_EDGE(EDGE)
Verify the ADC edge trigger setting for injected group.
#define | IS_ADC_MODE(MODE)
Verify the ADC multimode setting.
#define | IS_ADC_DUAL_DATA_MODE(MODE)
Verify the ADC dual data mode setting.
#define | IS_ADC_SAMPLING_DELAY(DELAY)
Verify the ADC multimode delay setting.
#define | IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG)
Verify the ADC analog watchdog setting.
#define | IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG)
Verify the ADC analog watchdog mode setting.
#define | IS_ADC_CONVERSION_GROUP(CONVERSION)
Verify the ADC conversion (regular or injected or both).
#define | IS_ADC_EVENT_TYPE(EVENT)
Verify the ADC event type.
#define | IS_ADC_SCAN_MODE(SCAN_MODE)
Verify the ADC scan mode.
#define | IS_ADC_OVERSAMPLING_RATIO(RATIO) ((RATIO) < 1024)
Verify the ADC oversampling ratio.
#define | IS_ADC_RIGHT_BIT_SHIFT(SHIFT)
Verify the ADC oversampling right shift.
#define | IS_ADC_LEFT_BIT_SHIFT(SHIFT)
Verify the ADC oversampling left shift.
#define | IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE)
Verify the ADC oversampling triggered mode.
#define | IS_ADC_REGOVERSAMPLING_MODE(MODE)
Verify the ADC oversampling regular conversion resumed or continued mode.

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
uint32_t | HAL_ADCEx_Calibration_GetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Get the calibration factor from automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_LinearCalibration_GetValue (ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer)
Get the calibration factor from automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_Calibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set the calibration factor to overwrite automatic conversion result, ADC must be enabled and no conversion on going.
HAL_StatusTypeDef | HAL_ADCEx_LinearCalibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer)
Set the linear calibration factor.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels and disable ADC peripheral if no regular conversion is on going.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group with interruption.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion, disable ADC peripheral if no regular conversion is on going.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStart_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start MultiMode conversion and transfer regular results through DMA.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADCEx_MultiModeGetValue (ADC_HandleTypeDef *hadc)
Return the last ADC Master and Slave regular conversions results when in multimode configuration.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non-blocking mode.
__weak void | HAL_ADCEx_InjectedQueueOverflowCallback (ADC_HandleTypeDef *hadc)
Injected context queue overflow callback.
__weak void | HAL_ADCEx_LevelOutOfWindow2Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 2 callback in non-blocking mode.
__weak void | HAL_ADCEx_LevelOutOfWindow3Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 3 callback in non-blocking mode.
__weak void | HAL_ADCEx_EndOfSamplingCallback (ADC_HandleTypeDef *hadc)
End Of Sampling callback in non-blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of ADC groups regular and injected, disable interrution of end-of-conversion, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularMultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop DMA-based MultiMode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configure a channel to be assigned to ADC group injected.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeConfigChannel (ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
Enable ADC multimode and configure multimode parameters.
HAL_StatusTypeDef | HAL_ADCEx_EnableInjectedQueue (ADC_HandleTypeDef *hadc)
Enable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableInjectedQueue (ADC_HandleTypeDef *hadc)
Disable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableVoltageRegulator (ADC_HandleTypeDef *hadc)
Disable ADC voltage regulator.
HAL_StatusTypeDef | HAL_ADCEx_EnterADCDeepPowerDownMode (ADC_HandleTypeDef *hadc)
Enter ADC deep-power-down mode.

Detailed Description

Header file of ADC HAL extended module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_adc_ex.h.

Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_cec.h File Reference

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stm32h7xx_hal_cec.h File Reference

Header file of CEC HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | CEC_InitTypeDef
CEC Init Structure definition. More...
struct | CEC_HandleTypeDef
CEC handle Structure definition. More...

Defines

#define | HAL_CEC_ERROR_NONE (uint32_t) 0x0000U
#define | HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR
#define | HAL_CEC_ERROR_BRE CEC_ISR_BRE
#define | HAL_CEC_ERROR_SBPE CEC_ISR_SBPE
#define | HAL_CEC_ERROR_LBPE CEC_ISR_LBPE
#define | HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE
#define | HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST
#define | HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR
#define | HAL_CEC_ERROR_TXERR CEC_ISR_TXERR
#define | HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE
#define | CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
#define | CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
#define | CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
#define | CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
#define | CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
#define | CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
#define | CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
#define | CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)
#define | CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
#define | CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
#define | CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
#define | CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
#define | CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define | CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
#define | CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define | CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
#define | CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
#define | CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
#define | CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
#define | CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
#define | CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
#define | CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
#define | CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)
#define | CEC_INITIATOR_LSB_POS ((uint32_t) 4U)
#define | CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
#define | CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
#define | CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
#define | CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
#define | CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
#define | CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
#define | CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
#define | CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
#define | CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
#define | CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
#define | CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
#define | CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
#define | CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
#define | CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
#define | CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
#define | CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */
#define | CEC_IT_TXACKE CEC_IER_TXACKEIE
#define | CEC_IT_TXERR CEC_IER_TXERRIE
#define | CEC_IT_TXUDR CEC_IER_TXUDRIE
#define | CEC_IT_TXEND CEC_IER_TXENDIE
#define | CEC_IT_TXBR CEC_IER_TXBRIE
#define | CEC_IT_ARBLST CEC_IER_ARBLSTIE
#define | CEC_IT_RXACKE CEC_IER_RXACKEIE
#define | CEC_IT_LBPE CEC_IER_LBPEIE
#define | CEC_IT_SBPE CEC_IER_SBPEIE
#define | CEC_IT_BRE CEC_IER_BREIE
#define | CEC_IT_RXOVR CEC_IER_RXOVRIE
#define | CEC_IT_RXEND CEC_IER_RXENDIE
#define | CEC_IT_RXBR CEC_IER_RXBRIE
#define | CEC_FLAG_TXACKE CEC_ISR_TXACKE
#define | CEC_FLAG_TXERR CEC_ISR_TXERR
#define | CEC_FLAG_TXUDR CEC_ISR_TXUDR
#define | CEC_FLAG_TXEND CEC_ISR_TXEND
#define | CEC_FLAG_TXBR CEC_ISR_TXBR
#define | CEC_FLAG_ARBLST CEC_ISR_ARBLST
#define | CEC_FLAG_RXACKE CEC_ISR_RXACKE
#define | CEC_FLAG_LBPE CEC_ISR_LBPE
#define | CEC_FLAG_SBPE CEC_ISR_SBPE
#define | CEC_FLAG_BRE CEC_ISR_BRE
#define | CEC_FLAG_RXOVR CEC_ISR_RXOVR
#define | CEC_FLAG_RXEND CEC_ISR_RXEND
#define | CEC_FLAG_RXBR CEC_ISR_RXBR
#define | CEC_ISR_ALL_ERROR
#define | CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
#define | CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
#define | __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__)
Reset CEC handle gstate & RxState.
#define | __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
Checks whether or not the specified CEC interrupt flag is set.
#define | __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
Clears the interrupt or status flag when raised (write at 1)
#define | __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enables the specified CEC interrupt.
#define | __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disables the specified CEC interrupt.
#define | __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
Checks whether or not the specified CEC interrupt is enabled.
#define | __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
Enables the CEC device.
#define | __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
Disables the CEC device.
#define | __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
Set Transmission Start flag.
#define | __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
Set Transmission End flag.
#define | __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
Get Transmission Start flag.
#define | __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
Get Transmission End flag.
#define | __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
Clear OAR register.
#define | __HAL_CEC_SET_OAR(__HANDLE__, __ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
Set OAR register (without resetting previously set address in case of multi-address mode) To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand.
#define | IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
#define | IS_CEC_TOLERANCE(__RXTOL__)
#define | IS_CEC_BRERXSTOP(__BRERXSTOP__)
#define | IS_CEC_BREERRORBITGEN(__ERRORBITGEN__)
#define | IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__)
#define | IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__)
#define | IS_CEC_SFTOP(__SFTOP__)
#define | IS_CEC_LISTENING_MODE(__MODE__)
#define | IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10)
Check CEC message size.
#define | IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFF)
Check CEC device Own Address Register (OAR) setting.
#define | IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
Check CEC initiator or destination logical address setting.

Enumerations

enum HAL_CEC_StateTypeDef {
HAL_CEC_STATE_RESET = 0x00U, HAL_CEC_STATE_READY = 0x20U, HAL_CEC_STATE_BUSY = 0x24U, HAL_CEC_STATE_BUSY_RX = 0x22U,
HAL_CEC_STATE_BUSY_TX = 0x21U, HAL_CEC_STATE_BUSY_RX_TX = 0x23U, HAL_CEC_STATE_ERROR = 0x60U
}
HAL CEC State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_CEC_Init (CEC_HandleTypeDef *hcec)
Initializes the CEC mode according to the specified parameters in the CEC_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_CEC_DeInit (CEC_HandleTypeDef *hcec)
DeInitializes the CEC peripheral.
HAL_StatusTypeDef | HAL_CEC_SetDeviceAddress (CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
Initializes the Own Address of the CEC device.
__weak void | HAL_CEC_MspInit (CEC_HandleTypeDef *hcec)
CEC MSP Init.
__weak void | HAL_CEC_MspDeInit (CEC_HandleTypeDef *hcec)
CEC MSP DeInit.
HAL_StatusTypeDef | HAL_CEC_Transmit_IT (CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
Send data in interrupt mode.
uint32_t | HAL_CEC_GetLastReceivedFrameSize (CEC_HandleTypeDef *hcec)
Get size of the received frame.
void | HAL_CEC_ChangeRxBuffer (CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
Change Rx Buffer.
void | HAL_CEC_IRQHandler (CEC_HandleTypeDef *hcec)
This function handles CEC interrupt requests.
__weak void | HAL_CEC_TxCpltCallback (CEC_HandleTypeDef *hcec)
Tx Transfer completed callback.
__weak void | HAL_CEC_RxCpltCallback (CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
Rx Transfer completed callback.
__weak void | HAL_CEC_ErrorCallback (CEC_HandleTypeDef *hcec)
CEC error callbacks.
HAL_CEC_StateTypeDef | HAL_CEC_GetState (CEC_HandleTypeDef *hcec)
return the CEC state
uint32_t | HAL_CEC_GetError (CEC_HandleTypeDef *hcec)
Return the CEC error code.

Detailed Description

Header file of CEC HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_cec.h.

Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_comp.h File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Data Structures | Defines | Enumerations | Functions
stm32h7xx_hal_comp.h File Reference

Header file of COMP HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | COMP_InitTypeDef
COMP Init structure definition. More...
struct | COMP_HandleTypeDef
COMP Handle Structure definition. More...

Defines

#define | COMP_STATE_BITFIELD_LOCK ((uint32_t)0x10)
HAL COMP state machine: HAL COMP states definition.
#define | COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000)
#define | COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CFGRx_WINMODE)
#define | COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000)
#define | COMP_POWERMODE_MEDIUMSPEED (COMP_CFGRx_PWRMODE_0)
#define | COMP_POWERMODE_ULTRALOWPOWER (COMP_CFGRx_PWRMODE)
#define | COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000)
#define | COMP_INPUT_PLUS_IO2 (COMP_CFGRx_INPSEL)
#define | COMP_INPUT_MINUS_1_4VREFINT ( COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)
#define | COMP_INPUT_MINUS_1_2VREFINT ( COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)
#define | COMP_INPUT_MINUS_3_4VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)
#define | COMP_INPUT_MINUS_VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN )
#define | COMP_INPUT_MINUS_DAC1_CH1 (COMP_CFGRx_INMSEL_2 )
#define | COMP_INPUT_MINUS_DAC1_CH2 (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_0)
#define | COMP_INPUT_MINUS_IO1 (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 )
#define | COMP_INPUT_MINUS_IO2 (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0)
#define | COMP_HYSTERESIS_NONE ((uint32_t)0x00000000)
#define | COMP_HYSTERESIS_LOW (COMP_CFGRx_HYST_0)
#define | COMP_HYSTERESIS_MEDIUM (COMP_CFGRx_HYST_1)
#define | COMP_HYSTERESIS_HIGH (COMP_CFGRx_HYST)
#define | COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000)
#define | COMP_OUTPUTPOL_INVERTED (COMP_CFGRx_POLARITY)
#define | COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000)
#define | COMP_BLANKINGSRC_TIM1_OC5 (COMP_CFGRx_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM2_OC3 (COMP_CFGRx_BLANKING_1)
#define | COMP_BLANKINGSRC_TIM3_OC3 (COMP_CFGRx_BLANKING_0 |COMP_CFGRx_BLANKING_1)
#define | COMP_BLANKINGSRC_TIM3_OC4 (COMP_CFGRx_BLANKING_2)
#define | COMP_BLANKINGSRC_TIM8_OC5 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM15_OC1 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_1)
#define | COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000)
#define | COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001)
#define | COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000)
#define | COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)
#define | COMP_FLAG_C1I COMP_SR_C1IF
#define | COMP_FLAG_C2I COMP_SR_C2IF
#define | COMP_FLAG_LOCK COMP_CFGRx_LOCK
#define | COMP_CLEAR_C1IF COMP_ICFR_C1IF
#define | COMP_CLEAR_C2IF COMP_ICFR_C2IF
#define | COMP_IT_EN COMP_CFGRx_ITEN
#define | __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
Reset COMP handle state.
#define | __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)
Enable the specified comparator.
#define | __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)
Disable the specified comparator.
#define | __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK)
Lock the specified comparator configuration.
#define | __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK) == COMP_CFGRx_LOCK)
Check whether the specified comparator is locked.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI Line in event mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI Line in event mode.
#define | __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)
Check whether the COMP1 EXTI line flag is set or not.
#define | __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)
Clear the COMP1 EXTI flag.
#define | __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1)
Generate a software interrupt on the COMP1 EXTI line.
#define | __HAL_COMP_COMP1_EXTID3_ENABLE_EVENT() SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 D3 EXTI Line in event mode.
#define | __HAL_COMP_COMP1_EXTID3_DISABLE_EVENT() CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 D3 EXTI Line in event mode.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI Line in event mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI Line in event mode.
#define | __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)
Check whether the COMP2 EXTI line flag is set or not.
#define | __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)
Clear the the COMP2 EXTI flag.
#define | __HAL_COMP_COMP2_EXTID3_ENABLE_EVENT() SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 D3 EXTI Line in event mode.
#define | __HAL_COMP_COMP2_EXTID3_DISABLE_EVENT() CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 D3 EXTI Line in event mode.
#define | __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2)
Generate a software interrupt on the COMP2 EXTI line.
#define | __HAL_COMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CFGR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified COMP interrupt source is enabled or disabled.
#define | __HAL_COMP_GET_FLAG(__FLAG__) ((COMP12->SR & (__FLAG__)) == (__FLAG__))
Checks whether the specified COMP flag is set or not.
#define | __HAL_COMP_CLEAR_FLAG(__FLAG__) (COMP12->ICFR = (__FLAG__))
Clears the specified COMP pending flag.
#define | __HAL_COMP_CLEAR_C1IFLAG() __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C1IF)
Clear the COMP C1I flag.
#define | __HAL_COMP_CLEAR_C2IFLAG() __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C2IF)
Clear the COMP C2I flag.
#define | __HAL_COMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ( ((__HANDLE__)->Instance->CFGR) |= (__INTERRUPT__) )
Enable the specified COMP interrupt.
#define | __HAL_COMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFGR) &= ~(__INTERRUPT__))
Disable the specified COMP interrupt.
#define | __HAL_COMP_ENABLE_OR(__AF__) SET_BIT(COMP12->OR, (__AF__))
Enable the specified bit in the Option register.
#define | __HAL_COMP_DISABLE_OR(__AF__) CLEAR_BIT(COMP12->OR, (__AF__))
Disable the specified bit in the Option register.
#define | COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM20)
#define | COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM21)
#define | COMP_EXTI_IT ((uint32_t) 0x01)
#define | COMP_EXTI_EVENT ((uint32_t) 0x02)
#define | COMP_EXTI_RISING ((uint32_t) 0x10)
#define | COMP_EXTI_FALLING ((uint32_t) 0x20)
#define | COMP_GET_EXTI_LINE(__INSTANCE__)
Get the specified EXTI line for a comparator instance.
#define | IS_COMP_WINDOWMODE(__WINDOWMODE__)
#define | IS_COMP_POWERMODE(__POWERMODE__)
#define | IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_COMP_HYSTERESIS(__HYSTERESIS__)
#define | IS_COMP_OUTPUTPOL(__POL__)
#define | IS_COMP_BLANKINGSRCE(__SOURCE__)
#define | IS_COMP_TRIGGERMODE(__MODE__)
#define | IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__)

Enumerations

enum HAL_COMP_StateTypeDef {
HAL_COMP_STATE_RESET = 0x00, HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), HAL_COMP_STATE_READY = 0x01, HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK),
HAL_COMP_STATE_BUSY = 0x02, HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)
}

Functions

HAL_StatusTypeDef | HAL_COMP_Init (COMP_HandleTypeDef *hcomp)
Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP peripheral.
__weak void | HAL_COMP_MspInit (COMP_HandleTypeDef *hcomp)
Initialize the COMP MSP.
__weak void | HAL_COMP_MspDeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP MSP.
HAL_StatusTypeDef | HAL_COMP_Start (COMP_HandleTypeDef *hcomp)
Start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop (COMP_HandleTypeDef *hcomp)
Stop the comparator.
HAL_StatusTypeDef | HAL_COMP_Start_IT (COMP_HandleTypeDef *hcomp)
Enable the interrupt and start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop_IT (COMP_HandleTypeDef *hcomp)
Disable the interrupt and Stop the comparator.
void | HAL_COMP_IRQHandler (COMP_HandleTypeDef *hcomp)
Comparator IRQ Handler.
HAL_StatusTypeDef | HAL_COMP_Lock (COMP_HandleTypeDef *hcomp)
Lock the selected comparator configuration.
uint32_t | HAL_COMP_GetOutputLevel (COMP_HandleTypeDef *hcomp)
Return the output level (high or low) of the selected comparator.
__weak void | HAL_COMP_TriggerCallback (COMP_HandleTypeDef *hcomp)
Comparator callback.
HAL_COMP_StateTypeDef | HAL_COMP_GetState (COMP_HandleTypeDef *hcomp)
Return the COMP handle state.

Detailed Description

Header file of COMP HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_comp.h.

Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_cortex.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_hal_cortex.h File Reference

Header file of CORTEX HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | MPU_Region_InitTypeDef

Defines

#define | NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007)
#define | NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006)
#define | NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005)
#define | NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004)
#define | NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003)
#define | SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
#define | SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
#define | MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
#define | MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
#define | MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
#define | MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
#define | MPU_REGION_ENABLE ((uint8_t)0x01)
#define | MPU_REGION_DISABLE ((uint8_t)0x00)
#define | MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define | MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
#define | MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
#define | MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
#define | MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
#define | MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define | MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define | MPU_TEX_LEVEL2 ((uint8_t)0x02)
#define | MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define | MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define | MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define | MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define | MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define | MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define | MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define | MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define | MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define | MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define | MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define | MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define | MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define | MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define | MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define | MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define | MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define | MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define | MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define | MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define | MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define | MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define | MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define | MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define | MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define | MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define | MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define | MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
#define | MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define | MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define | MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define | MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define | MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define | MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
#define | MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define | MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define | MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define | MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define | MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define | MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define | MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define | MPU_REGION_NUMBER7 ((uint8_t)0x07)
#define | CM7_CPUID (uint32_t)0x00000003
#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define | IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
#define | IS_SYSTICK_CLK_SOURCE(SOURCE)
#define | IS_MPU_REGION_ENABLE(STATE)
#define | IS_MPU_INSTRUCTION_ACCESS(STATE)
#define | IS_MPU_ACCESS_SHAREABLE(STATE)
#define | IS_MPU_ACCESS_CACHEABLE(STATE)
#define | IS_MPU_ACCESS_BUFFERABLE(STATE)
#define | IS_MPU_TEX_LEVEL(TYPE)
#define | IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)
#define | IS_MPU_REGION_NUMBER(NUMBER)
#define | IS_MPU_REGION_SIZE(SIZE)
#define | IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Sets the priority grouping field (preemption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Sets the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiates a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initializes the System Timer and its interrupt, and starts the System Tick Timer.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initializes and configures the Region and the memory to be protected.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Gets the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Gets the priority of an interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Sets Pending bit of an external interrupt.
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clears the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Gets active interrupt ( reads the active register in NVIC and returns the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configures the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
This function handles SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.
uint32_t | HAL_GetCurrentCPUID (void)
Returns the current CPU ID.
__STATIC_INLINE void | HAL_MPU_Disable (void)
Disables the MPU.
__STATIC_INLINE void | HAL_MPU_Enable (uint32_t MPU_Control)
Enables the MPU.

Detailed Description

Header file of CORTEX HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_cortex.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_crc.h File Reference

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stm32h7xx_hal_crc.h File Reference

Header file of CRC HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_crc_ex.h"

Go to the source code of this file.

Data Structures

struct | CRC_InitTypeDef
struct | CRC_HandleTypeDef

Defines

#define | DEFAULT_CRC32_POLY 0x04C11DB7U
#define | DEFAULT_CRC_INITVALUE 0xFFFFFFFFU
#define | DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)
#define | DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)
#define | CRC_POLYLENGTH_32B ((uint32_t)0x00000000U)
#define | CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)
#define | CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)
#define | CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)
#define | HAL_CRC_LENGTH_32B 32U
#define | HAL_CRC_LENGTH_16B 16U
#define | HAL_CRC_LENGTH_8B 8U
#define | HAL_CRC_LENGTH_7B 7U
#define | CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000U)
#define | CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001U)
#define | CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002U)
#define | CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003U)
#define | __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
Reset CRC handle state.
#define | __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
Reset CRC Data Register.
#define | __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
Set CRC INIT non-default value.
#define | __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
Stores a 32-bit data in the Independent Data(ID) register.
#define | __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
Returns the 32-bit data stored in the Independent Data(ID) register.
#define | HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
#define | HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
#define | IS_DEFAULT_POLYNOMIAL(__DEFAULT__)
#define | IS_DEFAULT_INIT_VALUE(__VALUE__)
#define | IS_CRC_POL_LENGTH(__LENGTH__)
#define | IS_CRC_INPUTDATA_FORMAT(__FORMAT__)

Enumerations

enum HAL_CRC_StateTypeDef {
HAL_CRC_STATE_RESET = 0x00U, HAL_CRC_STATE_READY = 0x01U, HAL_CRC_STATE_BUSY = 0x02U, HAL_CRC_STATE_TIMEOUT = 0x03U,
HAL_CRC_STATE_ERROR = 0x04U
}

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initialize the CRC MSP.
void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.
uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.
HAL_CRC_StateTypeDef | HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC state.

Detailed Description

Header file of CRC HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_crc.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_crc_ex.h File Reference

  • File List
  • Globals
  • Drivers
  • STM32H7xx_HAL_Driver
  • Inc
Defines | Functions
stm32h7xx_hal_crc_ex.h File Reference

Header file of CRC HAL extension module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000U)
#define | CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)
#define | CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)
#define | CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)
#define | IS_CRC_INPUTDATA_INVERSION_MODE(__MODE__)
#define | CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000U)
#define | CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)
#define | IS_CRC_OUTPUTDATA_INVERSION_MODE(__MODE__)
#define | __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
Set CRC output reversal.
#define | __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
Unset CRC output reversal.
#define | __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
Set CRC non-default polynomial.

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initializes the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Header file of CRC HAL extension module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_crc_ex.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_cryp.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32h7xx_hal_cryp.h File Reference

Header file of CRYP HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_cryp_ex.h"

Go to the source code of this file.

Data Structures

struct | CRYP_ConfigTypeDef
CRYP Init Structure definition. More...
struct | CRYP_HandleTypeDef
CRYP handle Structure definition. More...

Defines

#define | HAL_CRYP_ERROR_NONE 0x00000000U
#define | HAL_CRYP_ERROR_WRITE 0x00000001U
#define | HAL_CRYP_ERROR_READ 0x00000002U
#define | HAL_CRYP_ERROR_DMA 0x00000004U
#define | HAL_CRYP_ERROR_BUSY 0x00000008U
#define | HAL_CRYP_ERROR_TIMEOUT 0x00000010U
#define | HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U
#define | HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U
#define | CRYP_DES_ECB CRYP_CR_ALGOMODE_DES_ECB
#define | CRYP_DES_CBC CRYP_CR_ALGOMODE_DES_CBC
#define | CRYP_TDES_ECB CRYP_CR_ALGOMODE_TDES_ECB
#define | CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC
#define | CRYP_AES_ECB CRYP_CR_ALGOMODE_AES_ECB
#define | CRYP_AES_CBC CRYP_CR_ALGOMODE_AES_CBC
#define | CRYP_AES_CTR CRYP_CR_ALGOMODE_AES_CTR
#define | CRYP_AES_GCM CRYP_CR_ALGOMODE_AES_GCM
#define | CRYP_AES_CCM CRYP_CR_ALGOMODE_AES_CCM
#define | CRYP_KEYSIZE_128B 0x00000000U
#define | CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
#define | CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
#define | CRYP_DATATYPE_32B 0x00000000U
#define | CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
#define | CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
#define | CRYP_DATATYPE_1B CRYP_CR_DATATYPE
#define | CRYP_IT_INI CRYP_IMSCR_INIM
#define | CRYP_IT_OUTI CRYP_IMSCR_OUTIM
#define | CRYP_FLAG_IFEM CRYP_SR_IFEM
#define | CRYP_FLAG_IFNF CRYP_SR_IFNF
#define | CRYP_FLAG_OFNE CRYP_SR_OFNE
#define | CRYP_FLAG_OFFU CRYP_SR_OFFU
#define | CRYP_FLAG_BUSY CRYP_SR_BUSY
#define | CRYP_FLAG_OUTRIS 0x01000002U
#define | CRYP_FLAG_INRIS 0x01000001U
#define | __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
Enable/Disable the CRYP peripheral.
#define | __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)
#define | CRYP_FLAG_MASK 0x0000001FU
Check whether the specified CRYP status flag is set or not.
#define | __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__)
#define | __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified CRYP interrupt is set or not.
#define | __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
Enable the CRYP interrupt.
#define | __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
Disable the CRYP interrupt.
#define | IS_CRYP_ALGORITHM(ALGORITHM)
#define | IS_CRYP_KEYSIZE(KEYSIZE)
#define | IS_CRYP_DATATYPE(DATATYPE)

Enumerations

enum | HAL_CRYP_STATETypeDef { HAL_CRYP_STATE_RESET = 0x00U, HAL_CRYP_STATE_READY = 0x01U, HAL_CRYP_STATE_BUSY = 0x02U }
CRYP State Structure definition. More...

Functions

HAL_StatusTypeDef | HAL_CRYP_Init (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP according to the specified parameters in the CRYP_ConfigTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_CRYP_DeInit (CRYP_HandleTypeDef *hcryp)
De-Initializes the CRYP peripheral.
__weak void | HAL_CRYP_MspInit (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP MSP.
__weak void | HAL_CRYP_MspDeInit (CRYP_HandleTypeDef *hcryp)
DeInitializes CRYP MSP.
HAL_StatusTypeDef | HAL_CRYP_SetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Configure the CRYP according to the specified parameters in the CRYP_ConfigTypeDef.
HAL_StatusTypeDef | HAL_CRYP_GetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Get CRYP Configuration parameters in associated handle.
HAL_StatusTypeDef | HAL_CRYP_Encrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Encryption mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Decryption mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in interrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in itnterrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in DMA mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in DMA mode.
void | HAL_CRYP_IRQHandler (CRYP_HandleTypeDef *hcryp)
This function handles cryptographic interrupt request.
HAL_CRYP_STATETypeDef | HAL_CRYP_GetState (CRYP_HandleTypeDef *hcryp)
Returns the CRYP state.
__weak void | HAL_CRYP_InCpltCallback (CRYP_HandleTypeDef *hcryp)
Input FIFO transfer completed callback.
__weak void | HAL_CRYP_OutCpltCallback (CRYP_HandleTypeDef *hcryp)
Output FIFO transfer completed callback.
__weak void | HAL_CRYP_ErrorCallback (CRYP_HandleTypeDef *hcryp)
CRYP error callback.
uint32_t | HAL_CRYP_GetError (CRYP_HandleTypeDef *hcryp)
Return the CRYP error code.

Detailed Description

Header file of CRYP HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_cryp.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_cryp_ex.h File Reference

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Functions
stm32h7xx_hal_cryp_ex.h File Reference

Header file of CRYP HAL Extension module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_CRYPEx_AESGCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
generate the GCM authentication TAG.
HAL_StatusTypeDef | HAL_CRYPEx_AESCCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
AES CCM Authentication TAG generation.

Detailed Description

Header file of CRYP HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_cryp_ex.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dac.h File Reference

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stm32h7xx_hal_dac.h File Reference

Header file of DAC HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_dac_ex.h"

Go to the source code of this file.

Data Structures

struct | DAC_HandleTypeDef
DAC handle Structure definition. More...
struct | DAC_SampleAndHoldConfTypeDef
DAC Configuration sample and hold Channel structure definition. More...
struct | DAC_ChannelConfTypeDef
DAC Configuration regular Channel structure definition. More...

Defines

#define | HAL_DAC_ERROR_NONE 0x00
#define | HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01
#define | HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02
#define | HAL_DAC_ERROR_DMA 0x04
#define | HAL_DAC_ERROR_TIMEOUT 0x08
#define | DAC_TRIGGER_NONE ((uint32_t)0x00000000)
#define | DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TEN1))
#define | DAC_TRIGGER_T1_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_2 |DAC_CR_TEN1))
#define | DAC_TRIGGER_T6_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TEN1))
#define | DAC_TRIGGER_HR1_TRGO1 ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_HR1_TRGO2 ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_LP1_OUT ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_LP2_OUT ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1))
#define | DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
#define | DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_MCR_MODE1_1)
#define | DAC_CHIPCONNECT_DISABLE ((uint32_t)0x00000000)
#define | DAC_CHIPCONNECT_ENABLE ((uint32_t)DAC_MCR_MODE1_0)
#define | DAC_TRIMMING_FACTORY ((uint32_t)0x00000000)
#define | DAC_TRIMMING_USER ((uint32_t)0x00000001)
#define | DAC_SAMPLEANDHOLD_DISABLE ((uint32_t)0x00000000)
#define | DAC_SAMPLEANDHOLD_ENABLE ((uint32_t)DAC_MCR_MODE1_2)
#define | DAC_CHANNEL_1 ((uint32_t)0x00000000)
#define | DAC_CHANNEL_2 ((uint32_t)0x00000010)
#define | DAC_ALIGN_12B_R ((uint32_t)0x00000000)
#define | DAC_ALIGN_12B_L ((uint32_t)0x00000004)
#define | DAC_ALIGN_8B_R ((uint32_t)0x00000008)
#define | DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define | DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
#define | DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define | DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
#define | __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
Reset DAC handle state.
#define | __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
Enable the DAC channel.
#define | __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
Disable the DAC channel.
#define | DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
Set DHR12R1 alignment.
#define | DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
Set DHR12R2 alignment.
#define | DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
Set DHR12RD alignment.
#define | __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the DAC interrupt.
#define | __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the DAC interrupt.
#define | __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified DAC interrupt source is enabled or not.
#define | __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected DAC's flag status.
#define | __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
Clear the DAC's flag.
#define | IS_DAC_OUTPUT_BUFFER_STATE(STATE)
#define | IS_DAC_CHANNEL(CHANNEL)
#define | IS_DAC_ALIGN(ALIGN)
#define | IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
#define | IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x0000000FF)

Enumerations

enum HAL_DAC_StateTypeDef {
HAL_DAC_STATE_RESET = 0x00, HAL_DAC_STATE_READY = 0x01, HAL_DAC_STATE_BUSY = 0x02, HAL_DAC_STATE_TIMEOUT = 0x03,
HAL_DAC_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitialize the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initialize the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitialize the DAC MSP.
HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enable DAC and start conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disable DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enable DAC and start conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disable DAC and stop conversion of channel.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handle DAC interrupt request This function uses the interruption of DMA underrun.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configure the selected DAC channel.
uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the last data output value of the selected DAC channel.
HAL_DAC_StateTypeDef | HAL_DAC_GetState (DAC_HandleTypeDef *hdac)
return the DAC handle state
uint32_t | HAL_DAC_GetError (DAC_HandleTypeDef *hdac)
Return the DAC error code.

Detailed Description

Header file of DAC HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_dac.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dac_ex.h File Reference

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Defines | Functions
stm32h7xx_hal_dac_ex.h File Reference

Header file of DAC HAL Extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000)
#define | DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2)
#define | DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3)
#define | DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000)
#define | DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2)
#define | DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3)
#define | DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | IS_DAC_TRIGGER(TRIGGER)
#define | IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x0000003FF)
#define | IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x0000003FF)
#define | IS_DAC_SAMPLEANDHOLD(MODE)
#define | IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
#define | IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
#define | IS_DAC_CHIP_CONNECTION(CONNECT)
#define | IS_DAC_TRIMMING(TRIMMING)
#define | IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)

Functions

HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel2.
HAL_StatusTypeDef | HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Run the self calibration of one DAC channel.
HAL_StatusTypeDef | HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
Set the trimming mode and trimming value (user trimming mode applied).
uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Return the last data output value of the selected DAC channel.
uint32_t | HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the DAC trimming value.
void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.

Detailed Description

Header file of DAC HAL Extended module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_dac_ex.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dcmi.h File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Data Structures | Defines | Enumerations | Functions
stm32h7xx_hal_dcmi.h File Reference

Header file of DCMI HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | DCMI_CodesInitTypeDef
DCMI Embedded Synchronisation CODE Init structure definition. More...
struct | DCMI_InitTypeDef
DCMI Init structure definition. More...
struct | DCMI_HandleTypeDef
DCMI handle Structure definition. More...

Defines

#define | HAL_DCMI_ERROR_NONE (0x00000000U)
#define | HAL_DCMI_ERROR_OVR (0x00000001U)
#define | HAL_DCMI_ERROR_SYNC (0x00000002U)
#define | HAL_DCMI_ERROR_TIMEOUT (0x00000020U)
#define | HAL_DCMI_ERROR_DMA (0x00000040U)
#define | DCMI_MODE_CONTINUOUS (0x00000000U)
#define | DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM)
#define | DCMI_SYNCHRO_HARDWARE (0x00000000U)
#define | DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS)
#define | DCMI_PCKPOLARITY_FALLING (0x00000000U)
#define | DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL)
#define | DCMI_VSPOLARITY_LOW (0x00000000U)
#define | DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL)
#define | DCMI_HSPOLARITY_LOW (0x00000000U)
#define | DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL)
#define | DCMI_JPEG_DISABLE (0x00000000U)
#define | DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG)
#define | DCMI_CR_ALL_FRAME (0x00000000U)
#define | DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0)
#define | DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1)
#define | DCMI_EXTEND_DATA_8B (0x00000000U)
#define | DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0)
#define | DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1)
#define | DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))
#define | DCMI_WINDOW_COORDINATE (0x3FFFU)
#define | DCMI_WINDOW_HEIGHT (0x1FFFU)
#define | DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE)
#define | DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE)
#define | DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE)
#define | DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE)
#define | DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE)
#define | DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC)
DCMI SR register.
#define | DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC)
#define | DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE)
#define | DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS)
DCMI RIS register.
#define | DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS)
#define | DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS)
#define | DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS)
#define | DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS)
#define | DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS)
DCMI MIS register.
#define | DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS )
#define | DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS )
#define | DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS)
#define | DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS )
#define | DCMI_BSM_ALL (0x00000000U)
#define | DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0)
#define | DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1)
#define | DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1))
#define | DCMI_OEBS_ODD (0x00000000U)
#define | DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS)
#define | DCMI_LSM_ALL (0x00000000U)
#define | DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM)
#define | DCMI_OELS_ODD (0x00000000U)
#define | DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS)
#define | __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
Reset DCMI handle state.
#define | __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
Enable the DCMI.
#define | __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
Disable the DCMI.
#define | __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)
Get the DCMI pending flag.
#define | __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the DCMI pending flags.
#define | __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified DCMI interrupts.
#define | __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
Disable the specified DCMI interrupts.
#define | __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
Check whether the specified DCMI interrupt has occurred or not.
#define | DCMI_MIS_INDEX (0x1000)
#define | DCMI_SR_INDEX (0x2000)
#define | IS_DCMI_CAPTURE_MODE(MODE)
#define | IS_DCMI_SYNCHRO(MODE)
#define | IS_DCMI_PCKPOLARITY(POLARITY)
#define | IS_DCMI_VSPOLARITY(POLARITY)
#define | IS_DCMI_HSPOLARITY(POLARITY)
#define | IS_DCMI_MODE_JPEG(JPEG_MODE)
#define | IS_DCMI_CAPTURE_RATE(RATE)
#define | IS_DCMI_EXTENDED_DATA(DATA)
#define | IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
#define | IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
#define | IS_DCMI_BYTE_SELECT_MODE(MODE)
#define | IS_DCMI_BYTE_SELECT_START(POLARITY)
#define | IS_DCMI_LINE_SELECT_MODE(MODE)
#define | IS_DCMI_LINE_SELECT_START(POLARITY)

Enumerations

enum HAL_DCMI_StateTypeDef {
HAL_DCMI_STATE_RESET = 0x00U, HAL_DCMI_STATE_READY = 0x01U, HAL_DCMI_STATE_BUSY = 0x02U, HAL_DCMI_STATE_TIMEOUT = 0x03U,
HAL_DCMI_STATE_ERROR = 0x04U, HAL_DCMI_STATE_SUSPENDED = 0x05U
}
HAL DCMI State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_DCMI_Init (DCMI_HandleTypeDef *hdcmi)
Initializes the DCMI according to the specified parameters in the DCMI_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DCMI_DeInit (DCMI_HandleTypeDef *hdcmi)
Deinitializes the DCMI peripheral registers to their default reset values.
__weak void | HAL_DCMI_MspInit (DCMI_HandleTypeDef *hdcmi)
Initializes the DCMI MSP.
__weak void | HAL_DCMI_MspDeInit (DCMI_HandleTypeDef *hdcmi)
DeInitializes the DCMI MSP.
HAL_StatusTypeDef | HAL_DCMI_Start_DMA (DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
Enables DCMI DMA request and enables DCMI capture.
HAL_StatusTypeDef | HAL_DCMI_Stop (DCMI_HandleTypeDef *hdcmi)
Disable DCMI DMA request and Disable DCMI capture.
HAL_StatusTypeDef | HAL_DCMI_Suspend (DCMI_HandleTypeDef *hdcmi)
Suspend DCMI capture.
HAL_StatusTypeDef | HAL_DCMI_Resume (DCMI_HandleTypeDef *hdcmi)
Resume DCMI capture.
__weak void | HAL_DCMI_ErrorCallback (DCMI_HandleTypeDef *hdcmi)
Error DCMI callback.
__weak void | HAL_DCMI_LineEventCallback (DCMI_HandleTypeDef *hdcmi)
Line Event callback.
__weak void | HAL_DCMI_FrameEventCallback (DCMI_HandleTypeDef *hdcmi)
Frame Event callback.
__weak void | HAL_DCMI_VsyncEventCallback (DCMI_HandleTypeDef *hdcmi)
VSYNC Event callback.
void | HAL_DCMI_IRQHandler (DCMI_HandleTypeDef *hdcmi)
Handles DCMI interrupt request.
HAL_StatusTypeDef | HAL_DCMI_ConfigCrop (DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
Configure the DCMI CROP coordinate.
HAL_StatusTypeDef | HAL_DCMI_EnableCrop (DCMI_HandleTypeDef *hdcmi)
Enable the Crop feature.
HAL_StatusTypeDef | HAL_DCMI_DisableCrop (DCMI_HandleTypeDef *hdcmi)
Disable the Crop feature.
HAL_DCMI_StateTypeDef | HAL_DCMI_GetState (DCMI_HandleTypeDef *hdcmi)
Return the DCMI state.
uint32_t | HAL_DCMI_GetError (DCMI_HandleTypeDef *hdcmi)
Return the DCMI error code.

Detailed Description

Header file of DCMI HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_dcmi.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dfsdm.h File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Data Structures | Defines | Enumerations | Functions
stm32h7xx_hal_dfsdm.h File Reference

Header file of DFSDM HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | DFSDM_Channel_OutputClockTypeDef
DFSDM channel output clock structure definition. More...
struct | DFSDM_Channel_InputTypeDef
DFSDM channel input structure definition. More...
struct | DFSDM_Channel_SerialInterfaceTypeDef
DFSDM channel serial interface structure definition. More...
struct | DFSDM_Channel_AwdTypeDef
DFSDM channel analog watchdog structure definition. More...
struct | DFSDM_Channel_InitTypeDef
DFSDM channel init structure definition. More...
struct | DFSDM_Channel_HandleTypeDef
DFSDM channel handle structure definition. More...
struct | DFSDM_Filter_RegularParamTypeDef
DFSDM filter regular conversion parameters structure definition. More...
struct | DFSDM_Filter_InjectedParamTypeDef
DFSDM filter injected conversion parameters structure definition. More...
struct | DFSDM_Filter_FilterParamTypeDef
DFSDM filter parameters structure definition. More...
struct | DFSDM_Filter_InitTypeDef
DFSDM filter init structure definition. More...
struct | DFSDM_Filter_HandleTypeDef
DFSDM filter handle structure definition. More...
struct | DFSDM_Filter_AwdParamTypeDef
DFSDM filter analog watchdog parameters structure definition. More...

Defines

#define | DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000)
#define | DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC
#define | DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000)
#define | DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0
#define | DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1
#define | DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000)
#define | DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0
#define | DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1
#define | DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000)
#define | DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL
#define | DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000)
#define | DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0
#define | DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1
#define | DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP
#define | DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000)
#define | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0
#define | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1
#define | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL
#define | DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000)
#define | DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0
#define | DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1
#define | DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD
#define | DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000)
#define | DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001)
#define | DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002)
#define | DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000)
#define | DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0
#define | DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1
#define | DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2
#define | DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)
#define | DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3
#define | DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)
#define | DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3)
#define | DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)
#define | DFSDM_FILTER_EXT_TRIG_LPTIM1 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_LPTIM2 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_0)
#define | DFSDM_FILTER_EXT_TRIG_LPTIM3 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2)
#define | DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0
#define | DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1
#define | DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN
#define | DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000)
#define | DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0
#define | DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1
#define | DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1)
#define | DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2
#define | DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2)
#define | DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000)
#define | DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL
#define | DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000)
#define | DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001)
#define | DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002)
#define | DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003)
#define | DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000)
#define | DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001)
#define | DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002)
#define | DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004)
#define | DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008)
#define | DFSDM_CHANNEL_0 ((uint32_t)0x00000001)
#define | DFSDM_CHANNEL_1 ((uint32_t)0x00010002)
#define | DFSDM_CHANNEL_2 ((uint32_t)0x00020004)
#define | DFSDM_CHANNEL_3 ((uint32_t)0x00030008)
#define | DFSDM_CHANNEL_4 ((uint32_t)0x00040010)
#define | DFSDM_CHANNEL_5 ((uint32_t)0x00050020)
#define | DFSDM_CHANNEL_6 ((uint32_t)0x00060040)
#define | DFSDM_CHANNEL_7 ((uint32_t)0x00070080)
#define | DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000)
#define | DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001)
#define | DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000)
#define | DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001)
#define | __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
Reset DFSDM channel handle state.
#define | __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
Reset DFSDM filter handle state.
#define | IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK)
#define | IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))
#define | IS_DFSDM_CHANNEL_INPUT(INPUT)
#define | IS_DFSDM_CHANNEL_DATA_PACKING(MODE)
#define | IS_DFSDM_CHANNEL_INPUT_PINS(PINS)
#define | IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE)
#define | IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE)
#define | IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER)
#define | IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32))
#define | IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
#define | IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F)
#define | IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF)
#define | IS_DFSDM_FILTER_REG_TRIGGER(TRIG)
#define | IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)
#define | IS_DFSDM_FILTER_EXT_TRIG(TRIG)
#define | IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)
#define | IS_DFSDM_FILTER_SINC_ORDER(ORDER)
#define | IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024))
#define | IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256))
#define | IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA)
#define | IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
#define | IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xF)
#define | IS_DFSDM_REGULAR_CHANNEL(CHANNEL)
#define | IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FF))
#define | IS_DFSDM_CONTINUOUS_MODE(MODE)

Enumerations

enum | HAL_DFSDM_Channel_StateTypeDef { HAL_DFSDM_CHANNEL_STATE_RESET = 0x00, HAL_DFSDM_CHANNEL_STATE_READY = 0x01, HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFF }
HAL DFSDM Channel states definition. More...
enum HAL_DFSDM_Filter_StateTypeDef {
HAL_DFSDM_FILTER_STATE_RESET = 0x00, HAL_DFSDM_FILTER_STATE_READY = 0x01, HAL_DFSDM_FILTER_STATE_REG = 0x02, HAL_DFSDM_FILTER_STATE_INJ = 0x03,
HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04, HAL_DFSDM_FILTER_STATE_ERROR = 0xFF
}
HAL DFSDM Filter states definition. More...

Functions

HAL_StatusTypeDef | HAL_DFSDM_ChannelInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel according to the specified parameters in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_DFSDM_ChannelDeInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel.
__weak void | HAL_DFSDM_ChannelMspInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel MSP.
__weak void | HAL_DFSDM_ChannelMspDeInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel MSP.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStart (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStart_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStop (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStop_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStart (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStart_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStop (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStop_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in interrupt mode.
int16_t | HAL_DFSDM_ChannelGetAwdValue (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get channel analog watchdog value.
HAL_StatusTypeDef | HAL_DFSDM_ChannelModifyOffset (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset)
This function allows to modify channel offset value.
HAL_StatusTypeDef | HAL_DFSDM_ChannelPollForCkab (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the clock absence detection.
HAL_StatusTypeDef | HAL_DFSDM_ChannelPollForScd (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the short circuit detection.
__weak void | HAL_DFSDM_ChannelCkabCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Clock absence detection callback.
__weak void | HAL_DFSDM_ChannelScdCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Short circuit detection callback.
HAL_DFSDM_Channel_StateTypeDef | HAL_DFSDM_ChannelGetState (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get the current DFSDM channel handle state.
HAL_StatusTypeDef | HAL_DFSDM_FilterInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initialize the DFSDM filter according to the specified parameters in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_DFSDM_FilterDeInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter.
__weak void | HAL_DFSDM_FilterMspInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initializes the DFSDM filter MSP.
__weak void | HAL_DFSDM_FilterMspDeInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter MSP.
HAL_StatusTypeDef | HAL_DFSDM_FilterConfigRegChannel (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t ContinuousMode)
This function allows to select channel and to enable/disable continuous mode for regular conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterConfigInjChannel (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to select channels for injected conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularMsbStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode and to get only the 16 most significant bits of conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedMsbStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode and to get only the 16 most significant bits of conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterAwdStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, DFSDM_Filter_AwdParamTypeDef *awdParam)
This function allows to start filter analog watchdog in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterAwdStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop filter analog watchdog in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterExdStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to start extreme detector feature.
HAL_StatusTypeDef | HAL_DFSDM_FilterExdStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop extreme detector feature.
int32_t | HAL_DFSDM_FilterGetRegularValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get regular conversion value.
int32_t | HAL_DFSDM_FilterGetInjectedValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get injected conversion value.
int32_t | HAL_DFSDM_FilterGetExdMaxValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector maximum value.
int32_t | HAL_DFSDM_FilterGetExdMinValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector minimum value.
uint32_t | HAL_DFSDM_FilterGetConvTimeValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get conversion time value.
void | HAL_DFSDM_IRQHandler (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function handles the DFSDM interrupts.
HAL_StatusTypeDef | HAL_DFSDM_FilterPollForRegConversion (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of regular conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterPollForInjConversion (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of injected conversion.
__weak void | HAL_DFSDM_FilterRegConvCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Regular conversion complete callback.
__weak void | HAL_DFSDM_FilterRegConvHalfCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half regular conversion complete callback.
__weak void | HAL_DFSDM_FilterInjConvCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Injected conversion complete callback.
__weak void | HAL_DFSDM_FilterInjConvHalfCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half injected conversion complete callback.
__weak void | HAL_DFSDM_FilterAwdCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold)
Filter analog watchdog callback.
__weak void | HAL_DFSDM_FilterErrorCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Error callback.
HAL_DFSDM_Filter_StateTypeDef | HAL_DFSDM_FilterGetState (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter handle state.
uint32_t | HAL_DFSDM_FilterGetError (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter error.

Detailed Description

Header file of DFSDM HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_dfsdm.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dma.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_dma.h File Reference

Header file of DMA HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_dma_ex.h"

Go to the source code of this file.

Data Structures

struct | DMA_InitTypeDef
DMA Configuration Structure definition. More...
struct | __DMA_HandleTypeDef
DMA handle Structure definition. More...

Defines

#define | HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_DMA_ERROR_TE ((uint32_t)0x00000001U)
#define | HAL_DMA_ERROR_FE ((uint32_t)0x00000002U)
#define | HAL_DMA_ERROR_DME ((uint32_t)0x00000004U)
#define | HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U)
#define | HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U)
#define | HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U)
#define | HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U)
#define | HAL_DMA_ERROR_SYNC ((uint32_t)0x00000200U)
#define | HAL_DMA_ERROR_REQGEN ((uint32_t)0x00000400U)
#define | DMA_REQUEST_MEM2MEM ((uint32_t)0x00000000)
#define | DMA_REQUEST_GENERATOR0 ((uint32_t)0x00000001)
#define | DMA_REQUEST_GENERATOR1 ((uint32_t)0x00000002)
#define | DMA_REQUEST_GENERATOR2 ((uint32_t)0x00000003)
#define | DMA_REQUEST_GENERATOR3 ((uint32_t)0x00000004)
#define | DMA_REQUEST_GENERATOR4 ((uint32_t)0x00000005)
#define | DMA_REQUEST_GENERATOR5 ((uint32_t)0x00000006)
#define | DMA_REQUEST_GENERATOR6 ((uint32_t)0x00000007)
#define | DMA_REQUEST_GENERATOR7 ((uint32_t)0x00000008)
#define | DMA_REQUEST_ADC1 ((uint32_t)0x00000009)
#define | DMA_REQUEST_ADC2 ((uint32_t)0x0000000A)
#define | DMA_REQUEST_TIM1_CH1 ((uint32_t)0x0000000B)
#define | DMA_REQUEST_TIM1_CH2 ((uint32_t)0x0000000C)
#define | DMA_REQUEST_TIM1_CH3 ((uint32_t)0x0000000D)
#define | DMA_REQUEST_TIM1_CH4 ((uint32_t)0x0000000E)
#define | DMA_REQUEST_TIM1_UP ((uint32_t)0x0000000F)
#define | DMA_REQUEST_TIM1_TRIG ((uint32_t)0x00000010)
#define | DMA_REQUEST_TIM1_COM ((uint32_t)0x00000011)
#define | DMA_REQUEST_TIM2_CH1 ((uint32_t)0x00000012)
#define | DMA_REQUEST_TIM2_CH2 ((uint32_t)0x00000013)
#define | DMA_REQUEST_TIM2_CH3 ((uint32_t)0x00000014)
#define | DMA_REQUEST_TIM2_CH4 ((uint32_t)0x00000015)
#define | DMA_REQUEST_TIM2_UP ((uint32_t)0x00000016)
#define | DMA_REQUEST_TIM3_CH1 ((uint32_t)0x00000017)
#define | DMA_REQUEST_TIM3_CH2 ((uint32_t)0x00000018)
#define | DMA_REQUEST_TIM3_CH3 ((uint32_t)0x00000019)
#define | DMA_REQUEST_TIM3_CH4 ((uint32_t)0x0000001A)
#define | DMA_REQUEST_TIM3_UP ((uint32_t)0x0000001B)
#define | DMA_REQUEST_TIM3_TRIG ((uint32_t)0x0000001C)
#define | DMA_REQUEST_TIM4_CH1 ((uint32_t)0x0000001D)
#define | DMA_REQUEST_TIM4_CH2 ((uint32_t)0x0000001E)
#define | DMA_REQUEST_TIM4_CH3 ((uint32_t)0x0000001F)
#define | DMA_REQUEST_TIM4_UP ((uint32_t)0x00000020)
#define | DMA_REQUEST_I2C1_RX ((uint32_t)0x00000021)
#define | DMA_REQUEST_I2C1_TX ((uint32_t)0x00000022)
#define | DMA_REQUEST_I2C2_RX ((uint32_t)0x00000023)
#define | DMA_REQUEST_I2C2_TX ((uint32_t)0x00000024)
#define | DMA_REQUEST_SPI1_RX ((uint32_t)0x00000025)
#define | DMA_REQUEST_SPI1_TX ((uint32_t)0x00000026)
#define | DMA_REQUEST_SPI2_RX ((uint32_t)0x00000027)
#define | DMA_REQUEST_SPI2_TX ((uint32_t)0x00000028)
#define | DMA_REQUEST_USART1_RX ((uint32_t)0x00000029)
#define | DMA_REQUEST_USART1_TX ((uint32_t)0x0000002A)
#define | DMA_REQUEST_USART2_RX ((uint32_t)0x0000002B)
#define | DMA_REQUEST_USART2_TX ((uint32_t)0x0000002C)
#define | DMA_REQUEST_USART3_RX ((uint32_t)0x0000002D)
#define | DMA_REQUEST_USART3_TX ((uint32_t)0x0000002E)
#define | DMA_REQUEST_TIM8_CH1 ((uint32_t)0x0000002F)
#define | DMA_REQUEST_TIM8_CH2 ((uint32_t)0x00000030)
#define | DMA_REQUEST_TIM8_CH3 ((uint32_t)0x00000031)
#define | DMA_REQUEST_TIM8_CH4 ((uint32_t)0x00000032)
#define | DMA_REQUEST_TIM8_UP ((uint32_t)0x00000033)
#define | DMA_REQUEST_TIM8_TRIG ((uint32_t)0x00000034)
#define | DMA_REQUEST_TIM8_COM ((uint32_t)0x00000035)
#define | DMA_REQUEST_TIM5_CH1 ((uint32_t)0x00000037)
#define | DMA_REQUEST_TIM5_CH2 ((uint32_t)0x00000038)
#define | DMA_REQUEST_TIM5_CH3 ((uint32_t)0x00000039)
#define | DMA_REQUEST_TIM5_CH4 ((uint32_t)0x0000003A)
#define | DMA_REQUEST_TIM5_UP ((uint32_t)0x0000003B)
#define | DMA_REQUEST_TIM5_TRIG ((uint32_t)0x0000003C)
#define | DMA_REQUEST_SPI3_RX ((uint32_t)0x0000003D)
#define | DMA_REQUEST_SPI3_TX ((uint32_t)0x0000003E)
#define | DMA_REQUEST_UART4_RX ((uint32_t)0x0000003F)
#define | DMA_REQUEST_UART4_TX ((uint32_t)0x00000040)
#define | DMA_REQUEST_UART5_RX ((uint32_t)0x00000041)
#define | DMA_REQUEST_UART5_TX ((uint32_t)0x00000042)
#define | DMA_REQUEST_DAC1 ((uint32_t)0x00000043)
#define | DMA_REQUEST_DAC2 ((uint32_t)0x00000044)
#define | DMA_REQUEST_TIM6_UP ((uint32_t)0x00000045)
#define | DMA_REQUEST_TIM7_UP ((uint32_t)0x00000046)
#define | DMA_REQUEST_USART6_RX ((uint32_t)0x00000047)
#define | DMA_REQUEST_USART6_TX ((uint32_t)0x00000048)
#define | DMA_REQUEST_I2C3_RX ((uint32_t)0x00000049)
#define | DMA_REQUEST_I2C3_TX ((uint32_t)0x0000004A)
#define | DMA_REQUEST_DCMI ((uint32_t)0x0000004B)
#define | DMA_REQUEST_CRYP_IN ((uint32_t)0x0000004C)
#define | DMA_REQUEST_CRYP_OUT ((uint32_t)0x0000004D)
#define | DMA_REQUEST_HASH_IN ((uint32_t)0x0000004E)
#define | DMA_REQUEST_UART7_RX ((uint32_t)0x0000004F)
#define | DMA_REQUEST_UART7_TX ((uint32_t)0x00000050)
#define | DMA_REQUEST_UART8_RX ((uint32_t)0x00000051)
#define | DMA_REQUEST_UART8_TX ((uint32_t)0x00000052)
#define | DMA_REQUEST_SPI4_RX ((uint32_t)0x00000053)
#define | DMA_REQUEST_SPI4_TX ((uint32_t)0x00000054)
#define | DMA_REQUEST_SPI5_RX ((uint32_t)0x00000055)
#define | DMA_REQUEST_SPI5_TX ((uint32_t)0x00000056)
#define | DMA_REQUEST_SAI1_A ((uint32_t)0x00000057)
#define | DMA_REQUEST_SAI1_B ((uint32_t)0x00000058)
#define | DMA_REQUEST_SAI2_A ((uint32_t)0x00000059)
#define | DMA_REQUEST_SAI2_B ((uint32_t)0x0000005A)
#define | DMA_REQUEST_SWPMI_RX ((uint32_t)0x0000005B)
#define | DMA_REQUEST_SWPMI_TX ((uint32_t)0x0000005C)
#define | DMA_REQUEST_SPDIF_RX_DT ((uint32_t)0x0000005D)
#define | DMA_REQUEST_SPDIF_RX_CS ((uint32_t)0x0000005E)
#define | DMA_REQUEST_HRTIM_MASTER ((uint32_t)0x0000005F)
#define | DMA_REQUEST_HRTIM_TIMER_A ((uint32_t)0x00000060)
#define | DMA_REQUEST_HRTIM_TIMER_B ((uint32_t)0x00000061)
#define | DMA_REQUEST_HRTIM_TIMER_C ((uint32_t)0x00000062)
#define | DMA_REQUEST_HRTIM_TIMER_D ((uint32_t)0x00000063)
#define | DMA_REQUEST_HRTIM_TIMER_E ((uint32_t)0x00000064)
#define | DMA_REQUEST_DFSDM1_FLT0 ((uint32_t)0x00000065)
#define | DMA_REQUEST_DFSDM1_FLT1 ((uint32_t)0x00000066)
#define | DMA_REQUEST_DFSDM1_FLT2 ((uint32_t)0x00000067)
#define | DMA_REQUEST_DFSDM1_FLT3 ((uint32_t)0x00000068)
#define | DMA_REQUEST_TIM15_CH1 ((uint32_t)0x00000069)
#define | DMA_REQUEST_TIM15_UP ((uint32_t)0x0000006A)
#define | DMA_REQUEST_TIM15_TRIG ((uint32_t)0x0000006B)
#define | DMA_REQUEST_TIM15_COM ((uint32_t)0x0000006C)
#define | DMA_REQUEST_TIM16_CH1 ((uint32_t)0x0000006D)
#define | DMA_REQUEST_TIM16_UP ((uint32_t)0x0000006E)
#define | DMA_REQUEST_TIM17_CH1 ((uint32_t)0x0000006F)
#define | DMA_REQUEST_TIM17_UP ((uint32_t)0x00000070)
#define | DMA_REQUEST_SAI3_A ((uint32_t)0x00000071)
#define | DMA_REQUEST_SAI3_B ((uint32_t)0x00000072)
#define | DMA_REQUEST_ADC3 ((uint32_t)0x00000073)
#define | BDMA_REQUEST_MEM2MEM ((uint32_t)0x00000000)
#define | BDMA_REQUEST_GENERATOR0 ((uint32_t)0x10000001)
#define | BDMA_REQUEST_GENERATOR1 ((uint32_t)0x10000002)
#define | BDMA_REQUEST_GENERATOR2 ((uint32_t)0x10000003)
#define | BDMA_REQUEST_GENERATOR3 ((uint32_t)0x10000004)
#define | BDMA_REQUEST_GENERATOR4 ((uint32_t)0x10000005)
#define | BDMA_REQUEST_GENERATOR5 ((uint32_t)0x10000006)
#define | BDMA_REQUEST_GENERATOR6 ((uint32_t)0x10000007)
#define | BDMA_REQUEST_GENERATOR7 ((uint32_t)0x10000008)
#define | BDMA_REQUEST_LP_UART1_RX ((uint32_t)0x10000009)
#define | BDMA_REQUEST_LP_UART1_TX ((uint32_t)0x1000000A)
#define | BDMA_REQUEST_SPI6_RX ((uint32_t)0x1000000B)
#define | BDMA_REQUEST_SPI6_TX ((uint32_t)0x1000000C)
#define | BDMA_REQUEST_I2C4_RX ((uint32_t)0x1000000D)
#define | BDMA_REQUEST_I2C4_TX ((uint32_t)0x1000000E)
#define | BDMA_REQUEST_SAI4_A ((uint32_t)0x1000000F)
#define | BDMA_REQUEST_SAI4_B ((uint32_t)0x10000010)
#define | BDMA_REQUEST_ADC3 ((uint32_t)0x10000011)
#define | DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U)
#define | DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0)
#define | DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1)
#define | DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC)
#define | DMA_PINC_DISABLE ((uint32_t)0x00000000U)
#define | DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC)
#define | DMA_MINC_DISABLE ((uint32_t)0x00000000U)
#define | DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U)
#define | DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0)
#define | DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1)
#define | DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U)
#define | DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0)
#define | DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1)
#define | DMA_NORMAL ((uint32_t)0x00000000U)
#define | DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC)
#define | DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)
#define | DMA_PRIORITY_LOW ((uint32_t)0x00000000U)
#define | DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0)
#define | DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1)
#define | DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL)
#define | DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U)
#define | DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS)
#define | DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U)
#define | DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0)
#define | DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1)
#define | DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH)
#define | DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
#define | DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
#define | DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
#define | DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
#define | DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
#define | DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
#define | DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
#define | DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
#define | DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
#define | DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
#define | DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
#define | DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
#define | DMA_IT_FE ((uint32_t)0x00000080U)
#define | DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U)
#define | DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U)
#define | DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
#define | DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
#define | DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
#define | DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
#define | DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
#define | DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
#define | DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
#define | DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
#define | DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
#define | DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
#define | DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
#define | DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
#define | DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
#define | DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
#define | DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
#define | DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
#define | DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
#define | DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
#define | BDMA_FLAG_GL0 ((uint32_t)0x00000001)
#define | BDMA_FLAG_TC0 ((uint32_t)0x00000002)
#define | BDMA_FLAG_HT0 ((uint32_t)0x00000004)
#define | BDMA_FLAG_TE0 ((uint32_t)0x00000008)
#define | BDMA_FLAG_GL1 ((uint32_t)0x00000010)
#define | BDMA_FLAG_TC1 ((uint32_t)0x00000020)
#define | BDMA_FLAG_HT1 ((uint32_t)0x00000040)
#define | BDMA_FLAG_TE1 ((uint32_t)0x00000080)
#define | BDMA_FLAG_GL2 ((uint32_t)0x00000100)
#define | BDMA_FLAG_TC2 ((uint32_t)0x00000200)
#define | BDMA_FLAG_HT2 ((uint32_t)0x00000400)
#define | BDMA_FLAG_TE2 ((uint32_t)0x00000800)
#define | BDMA_FLAG_GL3 ((uint32_t)0x00001000)
#define | BDMA_FLAG_TC3 ((uint32_t)0x00002000)
#define | BDMA_FLAG_HT3 ((uint32_t)0x00004000)
#define | BDMA_FLAG_TE3 ((uint32_t)0x00008000)
#define | BDMA_FLAG_GL4 ((uint32_t)0x00010000)
#define | BDMA_FLAG_TC4 ((uint32_t)0x00020000)
#define | BDMA_FLAG_HT4 ((uint32_t)0x00040000)
#define | BDMA_FLAG_TE4 ((uint32_t)0x00080000)
#define | BDMA_FLAG_GL5 ((uint32_t)0x00100000)
#define | BDMA_FLAG_TC5 ((uint32_t)0x00200000)
#define | BDMA_FLAG_HT5 ((uint32_t)0x00400000)
#define | BDMA_FLAG_TE5 ((uint32_t)0x00800000)
#define | BDMA_FLAG_GL6 ((uint32_t)0x01000000)
#define | BDMA_FLAG_TC6 ((uint32_t)0x02000000)
#define | BDMA_FLAG_HT6 ((uint32_t)0x04000000)
#define | BDMA_FLAG_TE6 ((uint32_t)0x08000000)
#define | BDMA_FLAG_GL7 ((uint32_t)0x10000000)
#define | BDMA_FLAG_TC7 ((uint32_t)0x20000000)
#define | BDMA_FLAG_HT7 ((uint32_t)0x40000000)
#define | BDMA_FLAG_TE7 ((uint32_t)0x80000000)
#define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Reset DMA handle state.
#define | __HAL_DMA_GET_FS(__HANDLE__) ((IS_D2_DMA_INSTANCE(__HANDLE__))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0)
Return the current DMA Stream FIFO filled level.
#define | __HAL_DMA_ENABLE(__HANDLE__)
Enable the specified DMA Stream.
#define | __HAL_DMA_DISABLE(__HANDLE__)
Disable the specified DMA Stream.
#define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream transfer complete flag.
#define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream half transfer complete flag.
#define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream transfer error flag.
#define | __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream FIFO error flag.
#define | __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream direct mode error flag.
#define | __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)
Returns the current BDMA Channel Global interrupt flag.
#define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)
Get the DMA Stream pending flags.
#define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the DMA Stream pending flags.
#define | D2_TO_D3_DMA_IT(__DMA_IT__)
#define | __HAL_DMA_D3_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (D2_TO_D3_DMA_IT(__INTERRUPT__)))
#define | __HAL_DMA_D2_ENABLE_IT(__HANDLE__, __INTERRUPT__)
#define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified DMA Stream interrupts.
#define | __HAL_DMA_D3_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(D2_TO_D3_DMA_IT(__INTERRUPT__)))
#define | __HAL_DMA_D2_DISABLE_IT(__HANDLE__, __INTERRUPT__)
#define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified DMA Stream interrupts.
#define | __HAL_DMA_D3_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (D2_TO_D3_DMA_IT(__INTERRUPT__))))
#define | __HAL_DMA_D2_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
#define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified DMA Stream interrupt is enabled or not.
#define | __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__)
Writes the number of data units to be transferred on the DMA Stream.
#define | __HAL_DMA_GET_COUNTER(__HANDLE__)
Returns the number of remaining data units in the current DMAy Streamx transfer.
#define | IS_DMA_D2_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3))
#define | IS_BDMA_D3_REQUEST(REQUEST)
#define | IS_D2_DMA_INSTANCE(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) >= ((uint32_t)DMA1_Stream0)) && ((uint32_t)((__HANDLE__)->Instance) <= ((uint32_t)DMA2_Stream7)))
#define | IS_D3_DMA_INSTANCE(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) >= ((uint32_t)BDMA_Channel0)) && ((uint32_t)((__HANDLE__)->Instance) <= ((uint32_t)BDMA_Channel7)))
#define | IS_DMA_DIRECTION(DIRECTION)
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MODE(MODE)
#define | IS_DMA_PRIORITY(PRIORITY)
#define | IS_DMA_FIFO_MODE_STATE(STATE)
#define | IS_DMA_FIFO_THRESHOLD(THRESHOLD)
#define | IS_DMA_MEMORY_BURST(BURST)
#define | IS_DMA_PERIPHERAL_BURST(BURST)

Typedefs

typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef
DMA handle Structure definition.

Enumerations

enum HAL_DMA_StateTypeDef {
HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_ERROR = 0x03U,
HAL_DMA_STATE_ABORT = 0x04U
}
HAL DMA State structures definition. More...
enum | HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01U }
HAL DMA Transfer complete level structure definition. More...
enum HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U, HAL_DMA_XFER_ABORT_CB_ID = 0x05U, HAL_DMA_XFER_ALL_CB_ID = 0x06U
}
HAL DMA Callbacks IDs structure definition. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitializes the DMA peripheral.
HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Starts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Returns the DMA state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

Header file of DMA HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_dma.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dma2d.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_dma2d.h File Reference

Header file of DMA2D HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | DMA2D_ColorTypeDef
DMA2D color Structure definition. More...
struct | DMA2D_CLUTCfgTypeDef
DMA2D CLUT Structure definition. More...
struct | DMA2D_InitTypeDef
DMA2D Init structure definition. More...
struct | DMA2D_LayerCfgTypeDef
DMA2D Layer structure definition. More...
struct | __DMA2D_HandleTypeDef
DMA2D handle Structure definition. More...

Defines

#define | MAX_DMA2D_LAYER 2U
#define | HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001U)
#define | HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002U)
#define | HAL_DMA2D_ERROR_CAE ((uint32_t)0x00000004U)
#define | HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020U)
#define | DMA2D_M2M ((uint32_t)0x00000000U)
#define | DMA2D_M2M_PFC DMA2D_CR_MODE_0
#define | DMA2D_M2M_BLEND DMA2D_CR_MODE_1
#define | DMA2D_R2M DMA2D_CR_MODE
#define | DMA2D_OUTPUT_ARGB8888 ((uint32_t)0x00000000U)
#define | DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0
#define | DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1
#define | DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1)
#define | DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2
#define | DMA2D_INPUT_ARGB8888 ((uint32_t)0x00000000U)
#define | DMA2D_INPUT_RGB888 ((uint32_t)0x00000001U)
#define | DMA2D_INPUT_RGB565 ((uint32_t)0x00000002U)
#define | DMA2D_INPUT_ARGB1555 ((uint32_t)0x00000003U)
#define | DMA2D_INPUT_ARGB4444 ((uint32_t)0x00000004U)
#define | DMA2D_INPUT_L8 ((uint32_t)0x00000005U)
#define | DMA2D_INPUT_AL44 ((uint32_t)0x00000006U)
#define | DMA2D_INPUT_AL88 ((uint32_t)0x00000007U)
#define | DMA2D_INPUT_L4 ((uint32_t)0x00000008U)
#define | DMA2D_INPUT_A8 ((uint32_t)0x00000009U)
#define | DMA2D_INPUT_A4 ((uint32_t)0x0000000AU)
#define | DMA2D_INPUT_YCBCR ((uint32_t)0x0000000BU)
#define | DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000U)
#define | DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001U)
#define | DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002U)
#define | DMA2D_REGULAR_ALPHA ((uint32_t)0x00000000U)
#define | DMA2D_INVERTED_ALPHA ((uint32_t)0x00000001U)
#define | DMA2D_RB_REGULAR ((uint32_t)0x00000000U)
#define | DMA2D_RB_SWAP ((uint32_t)0x00000001U)
#define | DMA2D_NO_CSS ((uint32_t)0x00000000)
#define | DMA2D_CSS_422 ((uint32_t)0x00000001)
#define | DMA2D_CSS_420 ((uint32_t)0x00000002)
#define | DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000U)
#define | DMA2D_CCM_RGB888 ((uint32_t)0x00000001U)
#define | DMA2D_IT_CE DMA2D_CR_CEIE
#define | DMA2D_IT_CTC DMA2D_CR_CTCIE
#define | DMA2D_IT_CAE DMA2D_CR_CAEIE
#define | DMA2D_IT_TW DMA2D_CR_TWIE
#define | DMA2D_IT_TC DMA2D_CR_TCIE
#define | DMA2D_IT_TE DMA2D_CR_TEIE
#define | DMA2D_FLAG_CE DMA2D_ISR_CEIF
#define | DMA2D_FLAG_CTC DMA2D_ISR_CTCIF
#define | DMA2D_FLAG_CAE DMA2D_ISR_CAEIF
#define | DMA2D_FLAG_TW DMA2D_ISR_TWIF
#define | DMA2D_FLAG_TC DMA2D_ISR_TCIF
#define | DMA2D_FLAG_TE DMA2D_ISR_TEIF
#define | HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort
#define | __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
Reset DMA2D handle state.
#define | __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
Enable the DMA2D.
#define | __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
Get the DMA2D pending flags.
#define | __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
Clear the DMA2D pending flags.
#define | __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the specified DMA2D interrupts.
#define | __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the specified DMA2D interrupts.
#define | __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
Check whether the specified DMA2D interrupt source is enabled or not.
#define | DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW
#define | DMA2D_COLOR_VALUE ((uint32_t)0x000000FFU)
#define | DMA2D_OFFSET DMA2D_FGOR_LO
#define | DMA2D_PIXEL (DMA2D_NLR_PL >> 16U)
#define | DMA2D_LINE DMA2D_NLR_NL
#define | DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8)
#define | IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
#define | IS_DMA2D_MODE(MODE)
#define | IS_DMA2D_CMODE(MODE_ARGB)
#define | IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
#define | IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
#define | IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
#define | IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
#define | IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM)
#define | IS_DMA2D_ALPHA_MODE(AlphaMode)
#define | IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted)
#define | IS_DMA2D_RB_SWAP(RB_Swap)
#define | IS_DMA2D_CHROMA_SUB_SAMPLING
#define | IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
#define | IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
#define | IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
#define | IS_DMA2D_IT(IT)
#define | IS_DMA2D_GET_FLAG(FLAG)

Typedefs

typedef struct
__DMA2D_HandleTypeDef 		DMA2D_HandleTypeDef
DMA2D handle Structure definition.

Enumerations

enum HAL_DMA2D_StateTypeDef {
HAL_DMA2D_STATE_RESET = 0x00U, HAL_DMA2D_STATE_READY = 0x01U, HAL_DMA2D_STATE_BUSY = 0x02U, HAL_DMA2D_STATE_TIMEOUT = 0x03U,
HAL_DMA2D_STATE_ERROR = 0x04U, HAL_DMA2D_STATE_SUSPEND = 0x05U
}
HAL DMA2D State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_DMA2D_Init (DMA2D_HandleTypeDef *hdma2d)
Initialize the DMA2D according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d)
Deinitializes the DMA2D peripheral registers to their default reset values.
__weak void | HAL_DMA2D_MspInit (DMA2D_HandleTypeDef *hdma2d)
Initializes the DMA2D MSP.
__weak void | HAL_DMA2D_MspDeInit (DMA2D_HandleTypeDef *hdma2d)
DeInitializes the DMA2D MSP.
HAL_StatusTypeDef | HAL_DMA2D_Start (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_BlendingStart (DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the multi-source DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Start_IT (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the DMA2D Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_BlendingStart_IT (DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the multi-source DMA2D Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_Suspend (DMA2D_HandleTypeDef *hdma2d)
Suspend the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Resume (DMA2D_HandleTypeDef *hdma2d)
Resume the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Abort (DMA2D_HandleTypeDef *hdma2d)
Abort the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_EnableCLUT (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Enable the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoad (DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Start DMA2D CLUT Loading.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoad_IT (DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Start DMA2D CLUT Loading with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoading_Abort (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Abort the DMA2D CLUT loading.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoading_Suspend (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Suspend the DMA2D CLUT loading.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoading_Resume (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Resume the DMA2D CLUT loading.
HAL_StatusTypeDef | HAL_DMA2D_PollForTransfer (DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
Polling for transfer complete or CLUT loading.
void | HAL_DMA2D_IRQHandler (DMA2D_HandleTypeDef *hdma2d)
Handle DMA2D interrupt request.
__weak void | HAL_DMA2D_LineEventCallback (DMA2D_HandleTypeDef *hdma2d)
Transfer watermark callback.
__weak void | HAL_DMA2D_CLUTLoadingCpltCallback (DMA2D_HandleTypeDef *hdma2d)
CLUT Transfer Complete callback.
HAL_StatusTypeDef | HAL_DMA2D_ConfigLayer (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Configure the DMA2D Layer according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA2D_ConfigCLUT (DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Configure the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_ProgramLineEvent (DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
Configure the line watermark.
HAL_StatusTypeDef | HAL_DMA2D_EnableDeadTime (DMA2D_HandleTypeDef *hdma2d)
Enable DMA2D dead time feature.
HAL_StatusTypeDef | HAL_DMA2D_DisableDeadTime (DMA2D_HandleTypeDef *hdma2d)
Disable DMA2D dead time feature.
HAL_StatusTypeDef | HAL_DMA2D_ConfigDeadTime (DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
Configure dead time.
HAL_DMA2D_StateTypeDef | HAL_DMA2D_GetState (DMA2D_HandleTypeDef *hdma2d)
Return the DMA2D state.
uint32_t | HAL_DMA2D_GetError (DMA2D_HandleTypeDef *hdma2d)
Return the DMA2D error code.

Detailed Description

Header file of DMA2D HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_dma2d.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dma_ex.h File Reference

  • File List
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  • Drivers
  • STM32H7xx_HAL_Driver
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Data Structures | Defines | Enumerations | Functions
stm32h7xx_hal_dma_ex.h File Reference

Header file of DMA HAL extension module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | HAL_DMA_MuxSyncConfigTypeDef
HAL DMAMUX Synchronization configuration structure definition. More...
struct | HAL_DMA_MuxRequestGeneratorConfigTypeDef
HAL DMAMUX request generator parameters structure definition. More...

Defines

#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT ((uint32_t)0x00000000)
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT ((uint32_t)0x01000000)
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT ((uint32_t)0x02000000)
#define | HAL_DMAMUX1_SYNC_LPTIM1_OUT ((uint32_t)0x03000000)
#define | HAL_DMAMUX1_SYNC_LPTIM2_OUT ((uint32_t)0x04000000)
#define | HAL_DMAMUX1_SYNC_LPTIM3_OUT ((uint32_t)0x05000000)
#define | HAL_DMAMUX1_SYNC_EXTI0 ((uint32_t)0x06000000)
#define | HAL_DMAMUX1_SYNC_TIM12_TRGO ((uint32_t)0x07000000)
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT ((uint32_t)0x00000000)
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT ((uint32_t)0x01000000)
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT ((uint32_t)0x02000000)
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT ((uint32_t)0x03000000)
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT ((uint32_t)0x04000000)
#define | HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT ((uint32_t)0x05000000)
#define | HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP ((uint32_t)0x06000000)
#define | HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP ((uint32_t)0x07000000)
#define | HAL_DMAMUX2_SYNC_LPTIM2_OUT ((uint32_t)0x08000000)
#define | HAL_DMAMUX2_SYNC_LPTIM3_OUT ((uint32_t)0x09000000)
#define | HAL_DMAMUX2_SYNC_I2C4_WKUP ((uint32_t)0x0A000000)
#define | HAL_DMAMUX2_SYNC_SPI6_WKUP ((uint32_t)0x0B000000)
#define | HAL_DMAMUX2_SYNC_COMP1_OUT ((uint32_t)0x0C000000)
#define | HAL_DMAMUX2_SYNC_RTC_WKUP ((uint32_t)0x0D000000)
#define | HAL_DMAMUX2_SYNC_EXTI0 ((uint32_t)0x0E000000)
#define | HAL_DMAMUX2_SYNC_EXTI2 ((uint32_t)0x0F000000)
#define | HAL_DMAMUX_SYNC_NO_EVENT ((uint32_t)0x00000000)
#define | HAL_DMAMUX_SYNC_RISING ((uint32_t)DMAMUX_CxCR_SPOL_0)
#define | HAL_DMAMUX_SYNC_FALLING ((uint32_t)DMAMUX_CxCR_SPOL_1)
#define | HAL_DMAMUX_SYNC_RISING_FALLING ((uint32_t)DMAMUX_CxCR_SPOL)
#define | HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT ((uint32_t)0x00000000)
#define | HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT ((uint32_t)0x00000001)
#define | HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT ((uint32_t)0x00000002)
#define | HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT ((uint32_t)0x00000003)
#define | HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT ((uint32_t)0x00000004)
#define | HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT ((uint32_t)0x00000005)
#define | HAL_DMAMUX1_REQUEST_GEN_EXTI0 ((uint32_t)0x00000006)
#define | HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO ((uint32_t)0x00000007)
#define | HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT ((uint32_t)0x00000000)
#define | HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT ((uint32_t)0x00000001)
#define | HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT ((uint32_t)0x00000002)
#define | HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT ((uint32_t)0x00000003)
#define | HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT ((uint32_t)0x00000004)
#define | HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT ((uint32_t)0x00000005)
#define | HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT ((uint32_t)0x00000006)
#define | HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP ((uint32_t)0x00000007)
#define | HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP ((uint32_t)0x00000008)
#define | HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP ((uint32_t)0x00000009)
#define | HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT ((uint32_t)0x0000000A)
#define | HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP ((uint32_t)0x0000000B)
#define | HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT ((uint32_t)0x0000000C)
#define | HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP ((uint32_t)0x0000000D)
#define | HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP ((uint32_t)0x0000000E)
#define | HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP ((uint32_t)0x0000000F)
#define | HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP ((uint32_t)0x00000010)
#define | HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT ((uint32_t)0x00000011)
#define | HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT ((uint32_t)0x00000012)
#define | HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP ((uint32_t)0x00000013)
#define | HAL_DMAMUX2_REQUEST_GEN_EXTI0 ((uint32_t)0x00000014)
#define | HAL_DMAMUX2_REQUEST_GEN_EXTI2 ((uint32_t)0x00000015)
#define | HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT ((uint32_t)0x00000016)
#define | HAL_DMAMUX2_REQUEST_GEN_SPI6_IT ((uint32_t)0x00000017)
#define | HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT ((uint32_t)0x00000018)
#define | HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT ((uint32_t)0x00000019)
#define | HAL_DMAMUX2_REQUEST_GEN_ADC3_IT ((uint32_t)0x0000001A)
#define | HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT ((uint32_t)0x0000001B)
#define | HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT ((uint32_t)0x0000001C)
#define | HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT ((uint32_t)0x0000001D)
#define | HAL_DMAMUX_REQUEST_GEN_NO_EVENT ((uint32_t)0x00000000)
#define | HAL_DMAMUX_REQUEST_GEN_RISING ((uint32_t)DMAMUX_RGxCR_GPOL_0)
#define | HAL_DMAMUX_REQUEST_GEN_FALLING ((uint32_t)DMAMUX_RGxCR_GPOL_1)
#define | HAL_DMAMUX_REQUEST_GEN_RISING_FALLING ((uint32_t)DMAMUX_RGxCR_GPOL)
#define | IS_D2_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO)
#define | IS_D3_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2)
#define | IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32))
#define | IS_DMAMUX_SYNC_POLARITY(POLARITY)
#define | IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
#define | IS_DMAMUX_SYNC_EVENT(EVENT)
#define | IS_D2_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO)
#define | IS_D3_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT)
#define | IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32))
#define | IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY)

Enumerations

enum | HAL_DMA_MemoryTypeDef { MEMORY0 = 0x00U, MEMORY1 = 0x01U }
HAL DMA Memory definition. More...

Functions

HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer.
HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMAEx_ChangeMemory (DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
Change the memory0 or memory1 address on the fly.
HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxSync (DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
Configure the DMAMUX synchronization parameters for a given DMA stream (instance).
HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
Configure the DMAMUX request generator block used by the given DMA stream (instance).
HAL_StatusTypeDef | HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Enable the DMAMUX request generator block used by the given DMA stream (instance).
HAL_StatusTypeDef | HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Disable the DMAMUX request generator block used by the given DMA stream (instance).
void | HAL_DMAEx_MUX_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMAMUX interrupt request.

Detailed Description

Header file of DMA HAL extension module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_dma_ex.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_eth_ex.h File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Data Structures | Defines | Functions
stm32h7xx_hal_eth_ex.h File Reference

Header file of ETH HAL Extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | ETH_RxVLANConfigTypeDef
ETH RX VLAN structure definition. More...
struct | ETH_TxVLANConfigTypeDef
ETH TX VLAN structure definition. More...
struct | ETH_L3FilterConfigTypeDef
ETH L3 filter structure definition. More...
struct | ETH_L4FilterConfigTypeDef
ETH L4 filter structure definition. More...

Defines

#define | ETH_TX_LPI_ENTRY ETH_MACLCSR_TLPIEN
#define | ETH_TX_LPI_EXIT ETH_MACLCSR_TLPIEX
#define | ETH_RX_LPI_ENTRY ETH_MACLCSR_RLPIEN
#define | ETH_RX_LPI_EXIT ETH_MACLCSR_RLPIEX
#define | ETH_L3_FILTER_0 ((uint32_t)0x00000000)
#define | ETH_L3_FILTER_1 ((uint32_t)0x0000000C)
#define | ETH_L4_FILTER_0 ((uint32_t)0x00000000)
#define | ETH_L4_FILTER_1 ((uint32_t)0x0000000C)
#define | ETH_L3_IPV6_MATCH ETH_MACL3L4CR_L3PEN
#define | ETH_L3_IPV4_MATCH ((uint32_t)0x00000000)
#define | ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3SAM
#define | ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM)
#define | ETH_L3_SRC_ADDR_MATCH_DISABLE ((uint32_t)0x00000000)
#define | ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3DAM
#define | ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM)
#define | ETH_L3_DEST_ADDR_MATCH_DISABLE ((uint32_t)0x00000000)
#define | ETH_L4_UDP_MATCH ETH_MACL3L4CR_L4PEN
#define | ETH_L4_TCP_MATCH ((uint32_t)0x00000000)
#define | ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4SPM
#define | ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM)
#define | ETH_L4_SRC_PORT_MATCH_DISABLE ((uint32_t)0x00000000)
#define | ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4DPM
#define | ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)
#define | ETH_L4_DEST_PORT_MATCH_DISABLE ((uint32_t)0x00000000)
#define | ETH_INNERVLANTAGRXSTRIPPING_NONE ETH_MACVTR_EIVLS_DONOTSTRIP
#define | ETH_INNERVLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EIVLS_STRIPIFPASS
#define | ETH_INNERVLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS
#define | ETH_INNERVLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EIVLS_ALWAYSSTRIP
#define | ETH_VLANTAGRXSTRIPPING_NONE ETH_MACVTR_EVLS_DONOTSTRIP
#define | ETH_VLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EVLS_STRIPIFPASS
#define | ETH_VLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS
#define | ETH_VLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EVLS_ALWAYSSTRIP
#define | ETH_VLANTYPECHECK_DISABLE ETH_MACVTR_DOVLTC
#define | ETH_VLANTYPECHECK_SVLAN (ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL)
#define | ETH_VLANTYPECHECK_CVLAN ((uint32_t)0x00000000)
#define | ETH_VLANTAGCONTROL_NONE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_NOVLANTAG)
#define | ETH_VLANTAGCONTROL_DELETE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGDELETE)
#define | ETH_VLANTAGCONTROL_INSERT (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGINSERT)
#define | ETH_VLANTAGCONTROL_REPLACE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGREPLACE)
#define | ETH_INNER_TX_VLANTAG ((uint32_t)0x00000001U)
#define | ETH_OUTER_TX_VLANTAG ((uint32_t)0x00000000U)

Functions

void | HAL_ETHEx_EnableARPOffload (ETH_HandleTypeDef *heth)
Enables ARP Offload.
void | HAL_ETHEx_DisableARPOffload (ETH_HandleTypeDef *heth)
Disables ARP Offload.
void | HAL_ETHEx_SetARPAddressMatch (ETH_HandleTypeDef *heth, uint32_t IpAddress)
Set the ARP Match IP address.
void | HAL_ETHEx_EnableL3L4Filtering (ETH_HandleTypeDef *heth)
Enables L3 and L4 filtering process.
void | HAL_ETHEx_DisableL3L4Filtering (ETH_HandleTypeDef *heth)
Disables L3 and L4 filtering process.
HAL_StatusTypeDef | HAL_ETHEx_GetL3FilterConfig (ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
Configures the L3 Filter, this function allow to: set the layer 3 protocol to be matched (IPv4 or IPv6) enable/disable L3 source/destination port perfect/inverse match.
HAL_StatusTypeDef | HAL_ETHEx_GetL4FilterConfig (ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig)
Configures the L4 Filter, this function allow to: set the layer 4 protocol to be matched (TCP or UDP) enable/disable L4 source/destination port perfect/inverse match.
HAL_StatusTypeDef | HAL_ETHEx_SetL3FilterConfig (ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
Configures the L3 Filter, this function allow to: set the layer 3 protocol to be matched (IPv4 or IPv6) enable/disable L3 source/destination port perfect/inverse match.
HAL_StatusTypeDef | HAL_ETHEx_SetL4FilterConfig (ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig)
Configures the L4 Filter, this function allow to: set the layer 4 protocol to be matched (TCP or UDP) enable/disable L4 source/destination port perfect/inverse match.
void | HAL_ETHEx_EnableVLANProcessing (ETH_HandleTypeDef *heth)
Enables the VLAN Tag Filtering process.
void | HAL_ETHEx_DisableVLANProcessing (ETH_HandleTypeDef *heth)
Disables the VLAN Tag Filtering process.
HAL_StatusTypeDef | HAL_ETHEx_GetRxVLANConfig (ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
Get the VLAN Configuration for Receive Packets.
HAL_StatusTypeDef | HAL_ETHEx_SetRxVLANConfig (ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
Set the VLAN Configuration for Receive Packets.
void | HAL_ETHEx_SetVLANHashTable (ETH_HandleTypeDef *heth, uint32_t VLANHashTable)
Set the VLAN Hash Table.
HAL_StatusTypeDef | HAL_ETHEx_GetTxVLANConfig (ETH_HandleTypeDef *heth, uint32_t VLANTag, ETH_TxVLANConfigTypeDef *pVlanConfig)
Get the VLAN Configuration for Transmit Packets.
HAL_StatusTypeDef | HAL_ETHEx_SetTxVLANConfig (ETH_HandleTypeDef *heth, uint32_t VLANTag, ETH_TxVLANConfigTypeDef *pVlanConfig)
Set the VLAN Configuration for Transmit Packets.
void | HAL_ETHEx_SetTxVLANIdentifier (ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier)
Set the VLAN Tag Identifier for Transmit Packets.
void | HAL_ETHEx_EnterLPIMode (ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop)
Enters the Low Power Idle (LPI) mode.
void | HAL_ETHEx_ExitLPIMode (ETH_HandleTypeDef *heth)
Exits the Low Power Idle (LPI) mode.
uint32_t | HAL_ETHEx_GetMACLPIEvent (ETH_HandleTypeDef *heth)
Returns the ETH MAC LPI event.

Detailed Description

Header file of ETH HAL Extended module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_eth_ex.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_fdcan.h File Reference

  • File List
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Data Structures | Defines | Enumerations | Functions
stm32h7xx_hal_fdcan.h File Reference

Header file of FDCAN HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | FDCAN_InitTypeDef
FDCAN Init structure definition. More...
struct | FDCAN_ClkCalUnitTypeDef
FDCAN clock calibration unit structure definition. More...
struct | FDCAN_FilterTypeDef
FDCAN filter structure definition. More...
struct | FDCAN_TxHeaderTypeDef
FDCAN Tx header structure definition. More...
struct | FDCAN_RxHeaderTypeDef
FDCAN Rx header structure definition. More...
struct | FDCAN_TxEventFifoTypeDef
FDCAN Tx event FIFO structure definition. More...
struct | FDCAN_HpMsgStatusTypeDef
FDCAN High Priority Message Status structure definition. More...
struct | FDCAN_ProtocolStatusTypeDef
FDCAN Protocol Status structure definition. More...
struct | FDCAN_ErrorCountersTypeDef
FDCAN Error Counters structure definition. More...
struct | FDCAN_TT_ConfigTypeDef
FDCAN TT Init structure definition. More...
struct | FDCAN_TriggerTypeDef
FDCAN Trigger structure definition. More...
struct | FDCAN_TTOperationStatusTypeDef
FDCAN TT Operation Status structure definition. More...
struct | FDCAN_MsgRamAddressTypeDef
FDCAN Message RAM blocks. More...
struct | FDCAN_HandleTypeDef
FDCAN handle structure definition. More...

Defines

#define | HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U)
#define | HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U)
#define | HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U)
#define | HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U)
#define | HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U)
#define | HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U)
#define | HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U)
#define | HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U)
#define | HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO
#define | HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI
#define | HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA
#define | HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED
#define | HAL_FDCAN_ERROR_RESEVED_AREA FDCAN_IR_ARA
#define | HAL_FDCAN_ERROR_TT_GLOBAL_TIME FDCAN_TTIR_GTE
#define | HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU
#define | HAL_FDCAN_ERROR_TT_TX_OVERFLOW FDCAN_TTIR_TXO
#define | HAL_FDCAN_ERROR_TT_SCHEDULE1 FDCAN_TTIR_SE1
#define | HAL_FDCAN_ERROR_TT_SCHEDULE2 FDCAN_TTIR_SE2
#define | HAL_FDCAN_ERROR_TT_NO_INIT_REF FDCAN_TTIR_IWT
#define | HAL_FDCAN_ERROR_TT_NO_REF FDCAN_TTIR_WT
#define | HAL_FDCAN_ERROR_TT_APPL_WDG FDCAN_TTIR_AW
#define | HAL_FDCAN_ERROR_TT_CONFIG FDCAN_TTIR_CER
#define | FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U)
#define | FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)
#define | FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE))
#define | FDCAN_MODE_NORMAL ((uint32_t)0x00000000U)
#define | FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U)
#define | FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U)
#define | FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U)
#define | FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U)
#define | FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U)
#define | FDCAN_CLOCK_DIV2 ((uint32_t)0x00010000U)
#define | FDCAN_CLOCK_DIV4 ((uint32_t)0x00020000U)
#define | FDCAN_CLOCK_DIV6 ((uint32_t)0x00030000U)
#define | FDCAN_CLOCK_DIV8 ((uint32_t)0x00040000U)
#define | FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U)
#define | FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U)
#define | FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U)
#define | FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U)
#define | FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U)
#define | FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U)
#define | FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U)
#define | FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U)
#define | FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U)
#define | FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U)
#define | FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U)
#define | FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U)
#define | FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL)
#define | FDCAN_CLOCK_NOT_CALIBRATED ((uint32_t)0x00000000U)
#define | FDCAN_CLOCK_BASIC_CALIBRATED ((uint32_t)0x40000000U)
#define | FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U)
#define | FDCAN_CALIB_TIME_QUANTA_COUNTER ((uint32_t)0x00000000U)
#define | FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U)
#define | FDCAN_CALIB_WATCHDOG_COUNTER ((uint32_t)0x00000002U)
#define | FDCAN_DATA_BYTES_8 ((uint32_t)0x00000004U)
#define | FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U)
#define | FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U)
#define | FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U)
#define | FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U)
#define | FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU)
#define | FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU)
#define | FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U)
#define | FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U)
#define | FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM)
#define | FDCAN_STANDARD_ID ((uint32_t)0x00000000U)
#define | FDCAN_EXTENDED_ID ((uint32_t)0x40000000U)
#define | FDCAN_DATA_FRAME ((uint32_t)0x00000000U)
#define | FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)
#define | FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U)
#define | FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U)
#define | FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U)
#define | FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U)
#define | FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U)
#define | FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U)
#define | FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U)
#define | FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U)
#define | FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U)
#define | FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U)
#define | FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U)
#define | FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U)
#define | FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U)
#define | FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U)
#define | FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U)
#define | FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U)
#define | FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U)
#define | FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U)
#define | FDCAN_BRS_OFF ((uint32_t)0x00000000U)
#define | FDCAN_BRS_ON ((uint32_t)0x00100000U)
#define | FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U)
#define | FDCAN_FD_CAN ((uint32_t)0x00200000U)
#define | FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U)
#define | FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U)
#define | FDCAN_FILTER_RANGE ((uint32_t)0x00000000U)
#define | FDCAN_FILTER_DUAL ((uint32_t)0x00000001U)
#define | FDCAN_FILTER_MASK ((uint32_t)0x00000002U)
#define | FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U)
#define | FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U)
#define | FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U)
#define | FDCAN_FILTER_REJECT ((uint32_t)0x00000003U)
#define | FDCAN_FILTER_HP ((uint32_t)0x00000004U)
#define | FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U)
#define | FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U)
#define | FDCAN_FILTER_TO_RXBUFFER ((uint32_t)0x00000007U)
#define | FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U)
#define | FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U)
#define | FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U)
#define | FDCAN_TX_BUFFER3 ((uint32_t)0x00000008U)
#define | FDCAN_TX_BUFFER4 ((uint32_t)0x00000010U)
#define | FDCAN_TX_BUFFER5 ((uint32_t)0x00000020U)
#define | FDCAN_TX_BUFFER6 ((uint32_t)0x00000040U)
#define | FDCAN_TX_BUFFER7 ((uint32_t)0x00000080U)
#define | FDCAN_TX_BUFFER8 ((uint32_t)0x00000100U)
#define | FDCAN_TX_BUFFER9 ((uint32_t)0x00000200U)
#define | FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U)
#define | FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U)
#define | FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U)
#define | FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U)
#define | FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U)
#define | FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U)
#define | FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U)
#define | FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U)
#define | FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U)
#define | FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U)
#define | FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U)
#define | FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U)
#define | FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U)
#define | FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U)
#define | FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U)
#define | FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U)
#define | FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U)
#define | FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U)
#define | FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U)
#define | FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U)
#define | FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U)
#define | FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U)
#define | FDCAN_RX_FIFO0 ((uint32_t)0x00000040U)
#define | FDCAN_RX_FIFO1 ((uint32_t)0x00000041U)
#define | FDCAN_RX_BUFFER0 ((uint32_t)0x00000000U)
#define | FDCAN_RX_BUFFER1 ((uint32_t)0x00000001U)
#define | FDCAN_RX_BUFFER2 ((uint32_t)0x00000002U)
#define | FDCAN_RX_BUFFER3 ((uint32_t)0x00000003U)
#define | FDCAN_RX_BUFFER4 ((uint32_t)0x00000004U)
#define | FDCAN_RX_BUFFER5 ((uint32_t)0x00000005U)
#define | FDCAN_RX_BUFFER6 ((uint32_t)0x00000006U)
#define | FDCAN_RX_BUFFER7 ((uint32_t)0x00000007U)
#define | FDCAN_RX_BUFFER8 ((uint32_t)0x00000008U)
#define | FDCAN_RX_BUFFER9 ((uint32_t)0x00000009U)
#define | FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU)
#define | FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU)
#define | FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU)
#define | FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU)
#define | FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU)
#define | FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU)
#define | FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U)
#define | FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U)
#define | FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U)
#define | FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U)
#define | FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U)
#define | FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U)
#define | FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U)
#define | FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U)
#define | FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U)
#define | FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U)
#define | FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU)
#define | FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU)
#define | FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU)
#define | FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU)
#define | FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU)
#define | FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU)
#define | FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U)
#define | FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U)
#define | FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U)
#define | FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U)
#define | FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U)
#define | FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U)
#define | FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U)
#define | FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U)
#define | FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U)
#define | FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U)
#define | FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU)
#define | FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU)
#define | FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU)
#define | FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU)
#define | FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU)
#define | FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU)
#define | FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U)
#define | FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U)
#define | FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U)
#define | FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U)
#define | FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U)
#define | FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U)
#define | FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U)
#define | FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U)
#define | FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U)
#define | FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U)
#define | FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU)
#define | FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU)
#define | FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU)
#define | FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU)
#define | FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU)
#define | FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU)
#define | FDCAN_TX_EVENT ((uint32_t)0x00400000U)
#define | FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U)
#define | FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U)
#define | FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U)
#define | FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U)
#define | FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U)
#define | FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U)
#define | FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U)
#define | FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U)
#define | FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U)
#define | FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U)
#define | FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U)
#define | FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U)
#define | FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U)
#define | FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U)
#define | FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U)
#define | FDCAN_COM_STATE_RX ((uint32_t)0x00000016U)
#define | FDCAN_COM_STATE_TX ((uint32_t)0x00000024U)
#define | FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U)
#define | FDCAN_CFG_RX_FIFO0 ((uint32_t)0x00000001U)
#define | FDCAN_CFG_RX_FIFO1 ((uint32_t)0x00000002U)
#define | FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U)
#define | FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U)
#define | FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U)
#define | FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U)
#define | FDCAN_REJECT ((uint32_t)0x00000002U)
#define | FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U)
#define | FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U)
#define | FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U)
#define | FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U)
#define | FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U)
#define | FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U)
#define | FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U)
#define | FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U)
#define | FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U)
#define | FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U)
#define | FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U)
#define | FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U)
#define | FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U)
#define | FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U)
#define | FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U)
#define | FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U)
#define | FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U)
#define | FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U)
#define | FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U)
#define | FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U)
#define | FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U)
#define | FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U)
#define | FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U)
#define | FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U)
#define | FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ((uint32_t)0x00000000U)
#define | FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS)
#define | FDCAN_TT_REPEAT_EVERY_CYCLE ((uint32_t)0x00000000U)
#define | FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ((uint32_t)0x00000002U)
#define | FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ((uint32_t)0x00000004U)
#define | FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ((uint32_t)0x00000008U)
#define | FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U)
#define | FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U)
#define | FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U)
#define | FDCAN_TT_TX_REF_TRIGGER ((uint32_t)0x00000000U)
#define | FDCAN_TT_TX_REF_TRIGGER_GAP ((uint32_t)0x00000001U)
#define | FDCAN_TT_TX_TRIGGER_SINGLE ((uint32_t)0x00000002U)
#define | FDCAN_TT_TX_TRIGGER_CONTINUOUS ((uint32_t)0x00000003U)
#define | FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U)
#define | FDCAN_TT_TX_TRIGGER_MERGED ((uint32_t)0x00000005U)
#define | FDCAN_TT_WATCH_TRIGGER ((uint32_t)0x00000006U)
#define | FDCAN_TT_WATCH_TRIGGER_GAP ((uint32_t)0x00000007U)
#define | FDCAN_TT_RX_TRIGGER ((uint32_t)0x00000008U)
#define | FDCAN_TT_TIME_BASE_TRIGGER ((uint32_t)0x00000009U)
#define | FDCAN_TT_END_OF_LIST ((uint32_t)0x0000000AU)
#define | FDCAN_TT_TM_NO_INTERNAL_EVENT ((uint32_t)0x00000000U)
#define | FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U)
#define | FDCAN_TT_TM_NO_EXTERNAL_EVENT ((uint32_t)0x00000000U)
#define | FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U)
#define | FDCAN_TT_COMMUNICATION_LEVEL1 ((uint32_t)0x00000001U)
#define | FDCAN_TT_COMMUNICATION_LEVEL2 ((uint32_t)0x00000002U)
#define | FDCAN_TT_COMMUNICATION_LEVEL0 ((uint32_t)0x00000003U)
#define | FDCAN_STRICTLY_TT_OPERATION ((uint32_t)0x00000000U)
#define | FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN)
#define | FDCAN_TT_SLAVE ((uint32_t)0x00000000U)
#define | FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM)
#define | FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_TT_EXT_CLK_SYNC_ENABLE ((uint32_t)FDCAN_TTOCF_EECS)
#define | FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_TT_GLOB_TIME_FILT_ENABLE ((uint32_t)FDCAN_TTOCF_EGTF)
#define | FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_TT_AUTO_CLK_CALIB_ENABLE ((uint32_t)FDCAN_TTOCF_ECC)
#define | FDCAN_TT_EVT_TRIG_POL_RISING ((uint32_t)0x00000000U)
#define | FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP)
#define | FDCAN_TT_CYCLES_PER_MATRIX_1 ((uint32_t)0x00000000U)
#define | FDCAN_TT_CYCLES_PER_MATRIX_2 ((uint32_t)0x00000001U)
#define | FDCAN_TT_CYCLES_PER_MATRIX_4 ((uint32_t)0x00000003U)
#define | FDCAN_TT_CYCLES_PER_MATRIX_8 ((uint32_t)0x00000007U)
#define | FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU)
#define | FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU)
#define | FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU)
#define | FDCAN_TT_NO_SYNC_PULSE ((uint32_t)0x00000000U)
#define | FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U)
#define | FDCAN_TT_SYNC_MATRIX_START ((uint32_t)0x00000080U)
#define | FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U)
#define | FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U)
#define | FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U)
#define | FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U)
#define | FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U)
#define | FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U)
#define | FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U)
#define | FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U)
#define | FDCAN_TT_STOP_WATCH_DISABLED ((uint32_t)0x00000000U)
#define | FDCAN_TT_STOP_WATCH_CYCLE_TIME ((uint32_t)0x00000008U)
#define | FDCAN_TT_STOP_WATCH_LOCAL_TIME ((uint32_t)0x00000010U)
#define | FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U)
#define | FDCAN_TT_STOP_WATCH_RISING ((uint32_t)0x00000000U)
#define | FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U)
#define | FDCAN_TT_REG_TIMEMARK_DIABLED ((uint32_t)0x00000000U)
#define | FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U)
#define | FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U)
#define | FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U)
#define | FDCAN_TT_NO_ERROR ((uint32_t)0x00000000U)
#define | FDCAN_TT_WARNING ((uint32_t)0x00000001U)
#define | FDCAN_TT_ERROR ((uint32_t)0x00000002U)
#define | FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U)
#define | FDCAN_TT_MASTER_OFF ((uint32_t)0x00000000U)
#define | FDCAN_TT_TIME_SLAVE ((uint32_t)0x00000004U)
#define | FDCAN_TT_BACKUP_TIME_MASTER ((uint32_t)0x00000008U)
#define | FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU)
#define | FDCAN_TT_OUT_OF_SYNC ((uint32_t)0x00000000U)
#define | FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U)
#define | FDCAN_TT_IN_GAP ((uint32_t)0x00000020U)
#define | FDCAN_TT_IN_SCHEDULE ((uint32_t)0x00000030U)
#define | FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU)
#define | CCU_IR_MASK ((uint32_t)0xC0000000U)
#define | FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC
#define | FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF
#define | FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE
#define | FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM
#define | FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE FDCAN_IR_DRX
#define | FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL
#define | FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF
#define | FDCAN_FLAG_TX_EVT_FIFO_WATERMARK FDCAN_IR_TEFW
#define | FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN
#define | FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L
#define | FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F
#define | FDCAN_FLAG_RX_FIFO0_WATERMARK FDCAN_IR_RF0W
#define | FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N
#define | FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L
#define | FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F
#define | FDCAN_FLAG_RX_FIFO1_WATERMARK FDCAN_IR_RF1W
#define | FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N
#define | FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF
#define | FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO
#define | FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP
#define | FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW
#define | FDCAN_FLAG_BUS_OFF FDCAN_IR_BO
#define | FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI
#define | FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA
#define | FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED
#define | FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA
#define | FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW
#define | FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO
#define | FDCAN_FLAG_CALIB_STATE_CHANGED (FDCANCCU_IR_CSC << 30)
#define | FDCAN_FLAG_CALIB_WATCHDOG_EVENT (FDCANCCU_IR_CWE << 30)
#define | FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE
#define | FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE
#define | FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE
#define | FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME
#define | FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE
#define | FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE
#define | FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE
#define | FDCAN_IT_CALIB_STATE_CHANGED (FDCANCCU_IE_CSCE << 30)
#define | FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30)
#define | FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE
#define | FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE
#define | FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE
#define | FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE
#define | FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE
#define | FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE
#define | FDCAN_IT_RX_FIFO0_WATERMARK FDCAN_IE_RF0WE
#define | FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE
#define | FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE
#define | FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE
#define | FDCAN_IT_RX_FIFO1_WATERMARK FDCAN_IE_RF1WE
#define | FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE
#define | FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE
#define | FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE
#define | FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE
#define | FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE
#define | FDCAN_IT_BUS_OFF FDCAN_IE_BOE
#define | FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE
#define | FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE
#define | FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE
#define | FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE
#define | FDCAN_TT_FLAG_BASIC_CYCLE_START FDCAN_TTIR_SBC
#define | FDCAN_TT_FLAG_MATRIX_CYCLE_START FDCAN_TTIR_SMC
#define | FDCAN_TT_FLAG_SYNC_MODE_CHANGE FDCAN_TTIR_CSM
#define | FDCAN_TT_FLAG_START_OF_GAP FDCAN_TTIR_SOG
#define | FDCAN_TT_FLAG_REG_TIME_MARK FDCAN_TTIR_RTMI
#define | FDCAN_TT_FLAG_TRIG_TIME_MARK FDCAN_TTIR_TTMI
#define | FDCAN_TT_FLAG_STOP_WATCH FDCAN_TTIR_SWE
#define | FDCAN_TT_FLAG_GLOBAL_TIME_WRAP FDCAN_TTIR_GTW
#define | FDCAN_TT_FLAG_GLOBAL_TIME_DISC FDCAN_TTIR_GTD
#define | FDCAN_TT_FLAG_GLOBAL_TIME_ERROR FDCAN_TTIR_GTE
#define | FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW FDCAN_TTIR_TXU
#define | FDCAN_TT_FLAG_TX_COUNT_OVERFLOW FDCAN_TTIR_TXO
#define | FDCAN_TT_FLAG_SCHEDULING_ERROR_1 FDCAN_TTIR_SE1
#define | FDCAN_TT_FLAG_SCHEDULING_ERROR_2 FDCAN_TTIR_SE2
#define | FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE FDCAN_TTIR_ELC
#define | FDCAN_TT_FLAG_INIT_WATCH_TRIGGER FDCAN_TTIR_IWT
#define | FDCAN_TT_FLAG_WATCH_TRIGGER FDCAN_TTIR_WT
#define | FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW
#define | FDCAN_TT_FLAG_CONFIG_ERROR FDCAN_TTIR_CER
#define | FDCAN_TT_IT_BASIC_CYCLE_START FDCAN_TTIE_SBCE
#define | FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE
#define | FDCAN_TT_IT_SYNC_MODE_CHANGE FDCAN_TTIE_CSME
#define | FDCAN_TT_IT_START_OF_GAP FDCAN_TTIE_SOGE
#define | FDCAN_TT_IT_REG_TIME_MARK FDCAN_TTIE_RTMIE
#define | FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE
#define | FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE
#define | FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE
#define | FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE
#define | FDCAN_TT_IT_GLOBAL_TIME_ERROR FDCAN_TTIE_GTEE
#define | FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE
#define | FDCAN_TT_IT_TX_COUNT_OVERFLOW FDCAN_TTIE_TXOE
#define | FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E
#define | FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E
#define | FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE
#define | FDCAN_TT_IT_INIT_WATCH_TRIGGER FDCAN_TTIE_IWTE
#define | FDCAN_TT_IT_WATCH_TRIGGER FDCAN_TTIE_WTE
#define | FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE
#define | FDCAN_TT_IT_CONFIG_ERROR FDCAN_TTIE_CERE
#define | __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
Reset FDCAN handle state.
#define | __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified FDCAN interrupts.
#define | __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified FDCAN interrupts.
#define | __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
Check whether the specified FDCAN interrupt is set or not.
#define | __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__)
Clear the specified FDCAN interrupts.
#define | __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
Check whether the specified FDCAN flag is set or not.
#define | __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the specified FDCAN flags.
#define | __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__)))
Check if the specified FDCAN interrupt source is enabled or disabled.
#define | __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__))
Enable the specified FDCAN TT interrupts.
#define | __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__))
Disable the specified FDCAN TT interrupts.
#define | __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__))
Check whether the specified FDCAN TT interrupt is set or not.
#define | __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__))
Clear the specified FDCAN TT interrupts.
#define | __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__))
Check whether the specified FDCAN TT flag is set or not.
#define | __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__))
Clear the specified FDCAN TT flags.
#define | __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__))
Check if the specified FDCAN TT interrupt source is enabled or disabled.
#define | IS_FDCAN_FRAME_FORMAT(FORMAT)
#define | IS_FDCAN_MODE(MODE)
#define | IS_FDCAN_CKDIV(CKDIV)
#define | IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 512))
#define | IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1) && ((SJW) <= 128))
#define | IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 2) && ((TSEG1) <= 256))
#define | IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 2) && ((TSEG2) <= 128))
#define | IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 32))
#define | IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1) && ((SJW) <= 16))
#define | IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1) && ((TSEG1) <= 32))
#define | IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1) && ((TSEG2) <= 16))
#define | IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX))
#define | IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN))
#define | IS_FDCAN_DATA_SIZE(SIZE)
#define | IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE)
#define | IS_FDCAN_ID_TYPE(ID_TYPE)
#define | IS_FDCAN_FILTER_CFG(CONFIG)
#define | IS_FDCAN_TX_LOCATION(LOCATION)
#define | IS_FDCAN_RX_FIFO(FIFO)
#define | IS_FDCAN_RX_FIFO_MODE(MODE)
#define | IS_FDCAN_STD_FILTER_TYPE(TYPE)
#define | IS_FDCAN_EXT_FILTER_TYPE(TYPE)
#define | IS_FDCAN_FRAME_TYPE(TYPE)
#define | IS_FDCAN_DLC(DLC)
#define | IS_FDCAN_ESI(ESI)
#define | IS_FDCAN_BRS(BRS)
#define | IS_FDCAN_FDF(FDF)
#define | IS_FDCAN_EFC(EFC)
#define | IS_FDCAN_IT(IT) (((IT) & 0xC0300000U) == RESET)
#define | IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == RESET)
#define | IS_FDCAN_FIFO_WATERMARK(FIFO)
#define | IS_FDCAN_NON_MATCHING(DESTINATION)
#define | IS_FDCAN_IT_LINE(IT_LINE)
#define | IS_FDCAN_TIMESTAMP(OPERATION)
#define | IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER)
#define | IS_FDCAN_TIMEOUT(OPERATION)
#define | IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH)
#define | IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD)
#define | IS_FDCAN_TT_REPEAT_FACTOR(FACTOR)
#define | IS_FDCAN_TT_TRIGGER_TYPE(TYPE)
#define | IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT)
#define | IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT)
#define | IS_FDCAN_OPERATION_MODE(MODE)
#define | IS_FDCAN_TT_OPERATION(OPERATION)
#define | IS_FDCAN_TT_TIME_MASTER(FUNCTION)
#define | IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC)
#define | IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING)
#define | IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION)
#define | IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY)
#define | IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER)
#define | IS_FDCAN_TT_CYCLE_START_SYNC(SYNC)
#define | IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1) && ((NTU) <= 16))
#define | IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000) && ((NUMERATOR) <= 0x1FFFF))
#define | IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001) && ((DENOMINATOR) <= 0x3FFF))
#define | IS_FDCAN_TT_TUR_LEVEL_1(NC, DC) ((NC) >= (4 * (DC)))
#define | IS_FDCAN_TT_TUR_LEVEL_0_2(NC, DC) ((NC) >= (8 * (DC)))
#define | IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER)
#define | IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER)
#define | IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFF) && ((TIME) != 0x8000))
#define | IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE)
#define | IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY)
#define | IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE)

Enumerations

enum | HAL_FDCAN_StateTypeDef { HAL_FDCAN_STATE_RESET = 0x00U, HAL_FDCAN_STATE_READY = 0x01U, HAL_FDCAN_STATE_BUSY = 0x02U, HAL_FDCAN_STATE_ERROR = 0x03U }
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_Init (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN peripheral according to the specified parameters in the FDCAN_InitTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_DeInit (FDCAN_HandleTypeDef *hfdcan)
Deinitializes the FDCAN peripheral registers to their default reset values.
__weak void | HAL_FDCAN_MspInit (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN MSP.
__weak void | HAL_FDCAN_MspDeInit (FDCAN_HandleTypeDef *hfdcan)
DeInitializes the FDCAN MSP.
HAL_StatusTypeDef | HAL_FDCAN_EnterPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Enter FDCAN peripheral in sleep mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Exit power down mode.
HAL_StatusTypeDef | HAL_FDCAN_ConfigClockCalibration (FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig)
Configure the FDCAN clock calibration unit according to the specified parameters in the FDCAN_ClkCalUnitTypeDef structure.
uint32_t | HAL_FDCAN_GetClockCalibrationState (FDCAN_HandleTypeDef *hfdcan)
Get the clock calibration state.
HAL_StatusTypeDef | HAL_FDCAN_ResetClockCalibrationState (FDCAN_HandleTypeDef *hfdcan)
Reset the clock calibration state.
uint32_t | HAL_FDCAN_GetClockCalibrationCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t Counter)
Get the clock calibration counter value.
HAL_StatusTypeDef | HAL_FDCAN_ConfigFilter (FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
Configure the FDCAN reception filter according to the specified parameters in the FDCAN_FilterTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_ConfigGlobalFilter (FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt)
Configure the FDCAN global filter.
HAL_StatusTypeDef | HAL_FDCAN_ConfigExtendedIdMask (FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
Configure the extended ID mask.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRxFifoOverwrite (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
Configure the Rx FIFO operation mode.
HAL_StatusTypeDef | HAL_FDCAN_ConfigFifoWatermark (FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark)
Configure the FIFO watermark.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRamWatchdog (FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
Configure the RAM watchdog.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
Configure the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
Enable the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timestamp counter.
uint16_t | HAL_FDCAN_GetTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Get the timestamp counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timestamp counter to zero.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimeoutCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
Configure the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Enable the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timeout counter.
uint16_t | HAL_FDCAN_GetTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Get the timeout counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timeout counter to its start value.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
Configure the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_EnableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Enable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_DisableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Disable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_Start (FDCAN_HandleTypeDef *hfdcan)
Start the FDCAN module.
HAL_StatusTypeDef | HAL_FDCAN_Stop (FDCAN_HandleTypeDef *hfdcan)
Stop the FDCAN module and enable access to configuration registers.
HAL_StatusTypeDef | HAL_FDCAN_AddMessageToTxFifoQ (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData)
Add a message to the Tx FIFO/Queue and activate the corresponding transmission request.
HAL_StatusTypeDef | HAL_FDCAN_AddMessageToTxBuffer (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
Add a message to a dedicated Tx buffer.
HAL_StatusTypeDef | HAL_FDCAN_EnableTxBufferRequest (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
Enable transmission request.
HAL_StatusTypeDef | HAL_FDCAN_AbortTxRequest (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
Abort transmission request.
HAL_StatusTypeDef | HAL_FDCAN_GetRxMessage (FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetTxEvent (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetHighPriorityMessageStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
Get high priority message status.
HAL_StatusTypeDef | HAL_FDCAN_GetProtocolStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
Get protocol status.
HAL_StatusTypeDef | HAL_FDCAN_GetErrorCounters (FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
Get error counter values.
uint32_t | HAL_FDCAN_IsRxBufferMessageAvailable (FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex)
Check if a new message is received in the selected Rx buffer.
uint32_t | HAL_FDCAN_IsTxBufferMessagePending (FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
Check if a transmission request is pending on the selected Tx buffer.
uint32_t | HAL_FDCAN_GetRxFifoFillLevel (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
Return Rx FIFO fill level.
uint32_t | HAL_FDCAN_GetTxFifoFreeLevel (FDCAN_HandleTypeDef *hfdcan)
Return Tx FIFO free level: number of consecutive free Tx FIFO elements starting from Tx FIFO GetIndex.
uint32_t | HAL_FDCAN_IsRestrictedOperationMode (FDCAN_HandleTypeDef *hfdcan)
Check if the FDCAN peripheral entered Restricted Operation Mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitRestrictedOperationMode (FDCAN_HandleTypeDef *hfdcan)
Exit Restricted Operation Mode.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigOperation (FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams)
Initialize TT operation parameters.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigReferenceMessage (FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload)
Configure the reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigTrigger (FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig)
Configure the FDCAN trigger according to the specified parameters in the FDCAN_TriggerTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_TT_SetGlobalTime (FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset)
Schedule global time adjustment for the next reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_SetClockSynchronization (FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator)
Schedule TUR numerator update for the next reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigStopWatch (FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity)
Configure stop watch source and polarity.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigRegisterTimeMark (FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle)
Configure register time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableRegisterTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Enable register time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableRegisterTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Disable register time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableTriggerTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Enable trigger time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableTriggerTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Disable trigger time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableHardwareGapControl (FDCAN_HandleTypeDef *hfdcan)
Enable gap control by input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableHardwareGapControl (FDCAN_HandleTypeDef *hfdcan)
Disable gap control by input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableTimeMarkGapControl (FDCAN_HandleTypeDef *hfdcan)
Enable gap control (finish only) by register time mark interrupt.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableTimeMarkGapControl (FDCAN_HandleTypeDef *hfdcan)
Disable gap control by register time mark interrupt.
HAL_StatusTypeDef | HAL_FDCAN_TT_SetNextIsGap (FDCAN_HandleTypeDef *hfdcan)
Transmit next reference message with Next_is_Gap = "1".
HAL_StatusTypeDef | HAL_FDCAN_TT_SetEndOfGap (FDCAN_HandleTypeDef *hfdcan)
Finish a Gap by requesting start of reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigExternalSyncPhase (FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase)
Configure target phase used for external synchronization by event trigger input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableExternalSynchronization (FDCAN_HandleTypeDef *hfdcan)
Synchronize the phase of the FDCAN schedule to an external schedule using event trigger input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableExternalSynchronization (FDCAN_HandleTypeDef *hfdcan)
Disable external schedule synchronization.
HAL_StatusTypeDef | HAL_FDCAN_TT_GetOperationStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus)
Get TT operation status.
HAL_StatusTypeDef | HAL_FDCAN_ConfigInterruptLines (FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
Assign interrupts to either Interrupt line 0 or 1.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigInterruptLines (FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine)
Assign TT interrupts to either Interrupt line 0 or 1.
HAL_StatusTypeDef | HAL_FDCAN_ActivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
Enable interrupts.
HAL_StatusTypeDef | HAL_FDCAN_DeactivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
Disable interrupts.
HAL_StatusTypeDef | HAL_FDCAN_TT_ActivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs)
Enable TT interrupts.
HAL_StatusTypeDef | HAL_FDCAN_TT_DeactivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs)
Disable TT interrupts.
void | HAL_FDCAN_IRQHandler (FDCAN_HandleTypeDef *hfdcan)
Handles FDCAN interrupt request.
__weak void | HAL_FDCAN_ClockCalibrationCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)
Clock Calibration callback.
__weak void | HAL_FDCAN_TxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
Tx Event callback.
__weak void | HAL_FDCAN_RxFifo0Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
Rx FIFO 0 callback.
__weak void | HAL_FDCAN_RxFifo1Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
Rx FIFO 1 callback.
__weak void | HAL_FDCAN_TxFifoEmptyCallback (FDCAN_HandleTypeDef *hfdcan)
Tx FIFO Empty callback.
__weak void | HAL_FDCAN_TxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Complete callback.
__weak void | HAL_FDCAN_TxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Cancellation callback.
__weak void | HAL_FDCAN_RxBufferNewMessageCallback (FDCAN_HandleTypeDef *hfdcan)
Rx Buffer New Message callback.
__weak void | HAL_FDCAN_HighPriorityMessageCallback (FDCAN_HandleTypeDef *hfdcan)
High Priority Message callback.
__weak void | HAL_FDCAN_TimestampWraparoundCallback (FDCAN_HandleTypeDef *hfdcan)
Timestamp Wraparound callback.
__weak void | HAL_FDCAN_TimeoutOccurredCallback (FDCAN_HandleTypeDef *hfdcan)
Timeout Occurred callback.
__weak void | HAL_FDCAN_ErrorCallback (FDCAN_HandleTypeDef *hfdcan)
Error callback.
__weak void | HAL_FDCAN_TT_ScheduleSyncCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)
TT Schedule Synchronization callback.
__weak void | HAL_FDCAN_TT_TimeMarkCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)
TT Time Mark callback.
__weak void | HAL_FDCAN_TT_StopWatchCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)
TT Stop Watch callback.
__weak void | HAL_FDCAN_TT_GlobalTimeCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)
TT Global Time callback.
uint32_t | HAL_FDCAN_GetError (FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN error code.
HAL_FDCAN_StateTypeDef | HAL_FDCAN_GetState (FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN state.

Detailed Description

Header file of FDCAN HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_fdcan.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_flash.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32h7xx_hal_flash.h File Reference

Header file of FLASH HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_flash_ex.h"

Go to the source code of this file.

Data Structures

struct | FLASH_ProcessTypeDef
FLASH handle Structure definition. More...

Defines

#define | HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_FLASH_ERROR_WRP ((uint32_t)0x00000001U)
#define | HAL_FLASH_ERROR_PGS ((uint32_t)0x00000002U)
#define | HAL_FLASH_ERROR_STRB ((uint32_t)0x00000004U)
#define | HAL_FLASH_ERROR_INC ((uint32_t)0x00000008U)
#define | HAL_FLASH_ERROR_OPE ((uint32_t)0x00000010U)
#define | HAL_FLASH_ERROR_RDP ((uint32_t)0x00000020U)
#define | HAL_FLASH_ERROR_RDS ((uint32_t)0x00000040U)
#define | HAL_FLASH_ERROR_SNECC ((uint32_t)0x00000080U)
#define | HAL_FLASH_ERROR_DBECC ((uint32_t)0x00000100U)
#define | HAL_FLASH_ERROR_WRP_BANK1 ((uint32_t)0x00000001U)
#define | HAL_FLASH_ERROR_PGS_BANK1 ((uint32_t)0x00000002U)
#define | HAL_FLASH_ERROR_STRB_BANK1 ((uint32_t)0x00000004U)
#define | HAL_FLASH_ERROR_INC_BANK1 ((uint32_t)0x00000008U)
#define | HAL_FLASH_ERROR_OPE_BANK1 ((uint32_t)0x00000010U)
#define | HAL_FLASH_ERROR_RDP_BANK1 ((uint32_t)0x00000020U)
#define | HAL_FLASH_ERROR_RDS_BANK1 ((uint32_t)0x00000040U)
#define | HAL_FLASH_ERROR_SNECC_BANK1 ((uint32_t)0x00000080U)
#define | HAL_FLASH_ERROR_DBECC_BANK1 ((uint32_t)0x00000100U)
#define | HAL_FLASH_ERROR_WRP_BANK2 ((uint32_t)0x00001000U)
#define | HAL_FLASH_ERROR_PGS_BANK2 ((uint32_t)0x00002000U)
#define | HAL_FLASH_ERROR_STRB_BANK2 ((uint32_t)0x00004000U)
#define | HAL_FLASH_ERROR_INC_BANK2 ((uint32_t)0x00008000U)
#define | HAL_FLASH_ERROR_OPE_BANK2 ((uint32_t)0x00010000U)
#define | HAL_FLASH_ERROR_RDP_BANK2 ((uint32_t)0x00020000U)
#define | HAL_FLASH_ERROR_RDS_BANK2 ((uint32_t)0x00040000U)
#define | HAL_FLASH_ERROR_SNECC_BANK2 ((uint32_t)0x00080000U)
#define | HAL_FLASH_ERROR_DBECC_BANK2 ((uint32_t)0x00100000U)
#define | HAL_FLASH_ERROR_OB_CHANGE ((uint32_t)0x01000000U)
#define | FLASH_TYPEPROGRAM_FLASHWORD ((uint32_t)0x03U)
#define | FLASH_FLAG_BSY FLASH_SR_BSY
#define | FLASH_FLAG_WDW FLASH_SR_WDW
#define | FLASH_FLAG_QW FLASH_SR_QW
#define | FLASH_FLAG_CRC_BUSY FLASH_SR_CRC_BUSY
#define | FLASH_FLAG_EOP FLASH_SR_EOP
#define | FLASH_FLAG_WRPERR FLASH_SR_WRPERR
#define | FLASH_FLAG_PGSERR FLASH_SR_PGSERR
#define | FLASH_FLAG_STRBERR FLASH_SR_STRBERR
#define | FLASH_FLAG_INCERR FLASH_SR_INCERR
#define | FLASH_FLAG_OPERR FLASH_SR_OPERR
#define | FLASH_FLAG_RDPERR FLASH_SR_RDPERR
#define | FLASH_FLAG_RDSERR FLASH_SR_RDSERR
#define | FLASH_FLAG_SNECCERR FLASH_SR_SNECCERR
#define | FLASH_FLAG_DBECCERR FLASH_SR_DBECCERR
#define | FLASH_FLAG_CRCEND FLASH_SR_CRCEND
#define | FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY
#define | FLASH_FLAG_WBNE_BANK1 FLASH_SR_WBNE
#define | FLASH_FLAG_QW_BANK1 FLASH_SR_QW
#define | FLASH_FLAG_CRC_BUSY_BANK1 FLASH_SR_CRC_BUSY
#define | FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP
#define | FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPERR
#define | FLASH_FLAG_PGSERR_BANK1 FLASH_SR_PGSERR
#define | FLASH_FLAG_STRBER_BANK1R FLASH_SR_STRBERR
#define | FLASH_FLAG_INCERR_BANK1 FLASH_SR_INCERR
#define | FLASH_FLAG_OPERR_BANK1 FLASH_SR_OPERR
#define | FLASH_FLAG_RDPERR_BANK1 FLASH_SR_RDPERR
#define | FLASH_FLAG_RDSERR_BANK1 FLASH_SR_RDSERR
#define | FLASH_FLAG_SNECCE_BANK1RR FLASH_SR_SNECCERR
#define | FLASH_FLAG_DBECCE_BANK1RR FLASH_SR_DBECCERR
#define | FLASH_FLAG_CRCEND_BANK1 FLASH_SR_CRCEND
#define | FLASH_FLAG_ALL_ERRORS_BANK1
#define | FLASH_FLAG_ALL_BANK1
#define | FLASH_FLAG_BSY_BANK2 (FLASH_SR_BSY | 0x80000000U)
#define | FLASH_FLAG_WBNE_BANK2 (FLASH_SR_WBNE | 0x80000000U)
#define | FLASH_FLAG_QW_BANK2 (FLASH_SR_QW | 0x80000000U)
#define | FLASH_FLAG_CRC_BUSY_BANK2 (FLASH_SR_CRC_BUSY | 0x80000000U)
#define | FLASH_FLAG_EOP_BANK2 (FLASH_SR_EOP | 0x80000000U)
#define | FLASH_FLAG_WRPERR_BANK2 (FLASH_SR_WRPERR | 0x80000000U)
#define | FLASH_FLAG_PGSERR_BANK2 (FLASH_SR_PGSERR | 0x80000000U)
#define | FLASH_FLAG_STRBER_BANK2R (FLASH_SR_STRBERR | 0x80000000U)
#define | FLASH_FLAG_INCERR_BANK2 (FLASH_SR_INCERR | 0x80000000U)
#define | FLASH_FLAG_OPERR_BANK2 (FLASH_SR_OPERR | 0x80000000U)
#define | FLASH_FLAG_RDPERR_BANK2 (FLASH_SR_RDPERR | 0x80000000U)
#define | FLASH_FLAG_RDSERR_BANK2 (FLASH_SR_RDSERR | 0x80000000U)
#define | FLASH_FLAG_SNECCE_BANK2RR (FLASH_SR_SNECCERR | 0x80000000U)
#define | FLASH_FLAG_DBECCE_BANK2RR (FLASH_SR_DBECCERR | 0x80000000U)
#define | FLASH_FLAG_CRCEND_BANK2 (FLASH_SR_CRCEND | 0x80000000U)
#define | FLASH_FLAG_ALL_ERRORS_BANK2
#define | FLASH_FLAG_ALL_BANK2
#define | FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE
#define | FLASH_IT_WRPERR_BANK1 FLASH_CR_WRPERRIE
#define | FLASH_IT_PGSERR_BANK1 FLASH_CR_PGSERRIE
#define | FLASH_IT_STRBERR_BANK1 FLASH_CR_STRBERRIE
#define | FLASH_IT_INCERR_BANK1 FLASH_CR_INCERRIE
#define | FLASH_IT_OPERR_BANK1 FLASH_CR_OPERRIE
#define | FLASH_IT_RDPERR_BANK1 FLASH_CR_RDPERRIE
#define | FLASH_IT_RDSERR_BANK1 FLASH_CR_RDSERRIE
#define | FLASH_IT_SNECCERR_BANK1 FLASH_CR_SNECCERRIE
#define | FLASH_IT_DBECCERR_BANK1 FLASH_CR_DBECCERRIE
#define | FLASH_IT_CRCEND_BANK1 FLASH_CR_CRCENDIE
#define | FLASH_IT_ALL_BANK1
#define | FLASH_IT_EOP_BANK2 (FLASH_CR_EOPIE | 0x80000000U)
#define | FLASH_IT_WRPERR_BANK2 (FLASH_CR_WRPERRIE | 0x80000000U)
#define | FLASH_IT_PGSERR_BANK2 (FLASH_CR_PGSERRIE | 0x80000000U)
#define | FLASH_IT_STRBERR_BANK2 (FLASH_CR_STRBERRIE | 0x80000000U)
#define | FLASH_IT_INCERR_BANK2 (FLASH_CR_INCERRIE | 0x80000000U)
#define | FLASH_IT_OPERR_BANK2 (FLASH_CR_OPERRIE | 0x80000000U)
#define | FLASH_IT_RDPERR_BANK2 (FLASH_CR_RDPERRIE | 0x80000000U)
#define | FLASH_IT_RDSERR_BANK2 (FLASH_CR_RDSERRIE | 0x80000000U)
#define | FLASH_IT_SNECCERR_BANK2 (FLASH_CR_SNECCERRIE | 0x80000000U)
#define | FLASH_IT_DBECCERR_BANK2 (FLASH_CR_DBECCERRIE | 0x80000000U)
#define | FLASH_IT_CRCEND_BANK2 (FLASH_CR_CRCENDIE | 0x80000000U)
#define | FLASH_IT_ALL_BANK2
#define | FLASH_PSIZE_BYTE ((uint32_t)0x00000000U)
#define | FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0)
#define | FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1)
#define | FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE)
#define | CR_PSIZE_MASK ((uint32_t)0xFFFFFFCFU)
#define | FLASH_KEY1 ((uint32_t)0x45670123U)
#define | FLASH_KEY2 ((uint32_t)0xCDEF89ABU)
#define | FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU)
#define | FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU)
#define | FLASH_SECTOR_0 ((uint32_t)0U)
#define | FLASH_SECTOR_1 ((uint32_t)1U)
#define | FLASH_SECTOR_2 ((uint32_t)2U)
#define | FLASH_SECTOR_3 ((uint32_t)3U)
#define | FLASH_SECTOR_4 ((uint32_t)4U)
#define | FLASH_SECTOR_5 ((uint32_t)5U)
#define | FLASH_SECTOR_6 ((uint32_t)6U)
#define | FLASH_SECTOR_7 ((uint32_t)7U)
#define | __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
Set the FLASH Latency.
#define | __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
Get the FLASH Latency.
#define | __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 |= (__INTERRUPT__))
Enable the specified FLASH interrupt.
#define | __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFF))
#define | __HAL_FLASH_ENABLE_IT(__INTERRUPT__)
#define | __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 &= ~(uint32_t)(__INTERRUPT__))
Disable the specified FLASH interrupt.
#define | __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFF))
#define | __HAL_FLASH_DISABLE_IT(__INTERRUPT__)
#define | __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) (READ_BIT(FLASH->SR1, (__FLAG__)) == (__FLAG__))
Checks whether the specified FLASH flag is set or not.
#define | __HAL_FLASH_GET_FLAG_BANK2(__FLAG__) (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFF)) == (((__FLAG__) & 0x7FFFFFFF)))
#define | __HAL_FLASH_GET_FLAG(__FLAG__)
#define | __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) WRITE_REG(FLASH->CCR1, (__FLAG__))
Clear the specified FLASH flag.
#define | __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__) WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFF))
#define | __HAL_FLASH_CLEAR_FLAG(__FLAG__)
#define | IS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD)
#define | IS_FLASH_IT_BANK1(IT) (((IT) & FLASH_IT_ALL_BANK1) == (IT))
#define | IS_FLASH_IT_BANK2(IT) (((IT) & FLASH_IT_ALL_BANK2) == (IT))
#define | IS_FLASH_FLAG_BANK1(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))
#define | IS_FLASH_FLAG_BANK2(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))
#define | IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < (FLASH_BANK1_BASE + FLASH_BANK_SIZE) ))
#define | IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) < (FLASH_BANK2_BASE + FLASH_BANK_SIZE) ))
#define | IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS))
#define | IS_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= (0x3FFF0000U))
#define | IS_FLASH_BANK(BANK)
#define | IS_FLASH_BANK_EXCLUSIVE(BANK)

Enumerations

enum FLASH_ProcedureTypeDef {
FLASH_PROC_NONE = 0U, FLASH_PROC_SECTERASE_BANK1, FLASH_PROC_MASSERASE_BANK1, FLASH_PROC_PROGRAM_BANK1,
FLASH_PROC_SECTERASE_BANK2, FLASH_PROC_MASSERASE_BANK2, FLASH_PROC_PROGRAM_BANK2, FLASH_PROC_ALLBANK_MASSERASE
}
FLASH Procedure structure definition. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t DataAddress)
Program flash word of 256 bits at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t DataAddress)
Program flash words of 256 bits at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
This function handles FLASH interrupt request.
void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.
HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control registers access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Locks the FLASH control registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.
uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout, uint32_t Bank)
Wait for a FLASH operation to complete.
HAL_StatusTypeDef | FLASH_OB_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH Option Bytes change operation to complete.

Detailed Description

Header file of FLASH HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_flash.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_flash_ex.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_hal_flash_ex.h File Reference

Header file of FLASH HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | FLASH_EraseInitTypeDef
FLASH Erase structure definition. More...
struct | FLASH_OBProgramInitTypeDef
FLASH Option Bytes Program structure definition. More...

Defines

#define | FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U)
#define | FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U)
#define | FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U)
#define | FLASH_VOLTAGE_RANGE_2 ((uint32_t)FLASH_CR_PSIZE_0)
#define | FLASH_VOLTAGE_RANGE_3 ((uint32_t)FLASH_CR_PSIZE_1)
#define | FLASH_VOLTAGE_RANGE_4 ((uint32_t)FLASH_CR_PSIZE)
#define | OB_WRPSTATE_DISABLE ((uint32_t)0x00U)
#define | OB_WRPSTATE_ENABLE ((uint32_t)0x01U)
#define | OPTIONBYTE_WRP ((uint32_t)0x01U)
#define | OPTIONBYTE_RDP ((uint32_t)0x02U)
#define | OPTIONBYTE_USER ((uint32_t)0x04U)
#define | OPTIONBYTE_PCROP ((uint32_t)0x08U)
#define | OPTIONBYTE_BOR ((uint32_t)0x10U)
#define | OPTIONBYTE_SECURE_AREA ((uint32_t)0x20U)
#define | OPTIONBYTE_BOOTADD ((uint32_t)0x40U)
#define | OB_RDP_LEVEL_0 ((uint32_t)0xAA00U)
#define | OB_RDP_LEVEL_1 ((uint32_t)0x5500U)
#define | OB_RDP_LEVEL_2 ((uint32_t)0xCC00U)
#define | OB_WWDG_SW ((uint32_t)0x10U)
#define | OB_WWDG_HW ((uint32_t)0x00U)
#define | OB_IWDG_SW ((uint32_t)0x20U)
#define | OB_IWDG_HW ((uint32_t)0x00U)
#define | OB_STOP_NO_RST ((uint32_t)0x40U)
#define | OB_STOP_RST ((uint32_t)0x00U)
#define | OB_STDBY_NO_RST ((uint32_t)0x80U)
#define | OB_STDBY_RST ((uint32_t)0x00U)
#define | OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000U)
#define | OB_IWDG_STOP_ACTIVE ((uint32_t)FLASH_OPTSR_FZ_IWDG_STOP)
#define | OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000U)
#define | OB_IWDG_STDBY_ACTIVE ((uint32_t)FLASH_OPTSR_FZ_IWDG_SDBY)
#define | OB_BOR_LEVEL3 ((uint32_t)0x00U)
#define | OB_BOR_LEVEL2 ((uint32_t)0x04U)
#define | OB_BOR_LEVEL1 ((uint32_t)0x08U)
#define | OB_BOR_OFF ((uint32_t)0x0CU)
#define | OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000U)
#define | OB_BOOTADDR_SYSTEM ((uint32_t)0x0040U)
#define | OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080U)
#define | OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U)
#define | OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U)
#define | OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U)
#define | OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U)
#define | FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
#define | FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
#define | FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
#define | FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
#define | FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
#define | FLASH_BANK_1 ((uint32_t)0x01U)
#define | FLASH_BANK_2 ((uint32_t)0x02U)
#define | FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2))
#define | OB_PCROP_RDP_NOT_ERASE ((uint32_t)0x00000000U)
#define | OB_PCROP_RDP_ERASE ((uint32_t)FLASH_PRAR_DMEP)
#define | OB_WRP_SECTOR_0 ((uint32_t)0x00000001U)
#define | OB_WRP_SECTOR_1 ((uint32_t)0x00000002U)
#define | OB_WRP_SECTOR_2 ((uint32_t)0x00000004U)
#define | OB_WRP_SECTOR_3 ((uint32_t)0x00000008U)
#define | OB_WRP_SECTOR_4 ((uint32_t)0x00000010U)
#define | OB_WRP_SECTOR_5 ((uint32_t)0x00000020U)
#define | OB_WRP_SECTOR_6 ((uint32_t)0x00000040U)
#define | OB_WRP_SECTOR_7 ((uint32_t)0x00000080U)
#define | OB_WRP_SECTOR_All ((uint32_t)0x000000FFU)
#define | OB_SECURITY_DISABLE ((uint32_t)0x00000U)
#define | OB_SECURITY_ENABLE ((uint32_t)FLASH_OPTSR_SECURITY)
#define | OB_IWDG1_HW ((uint32_t)FLASH_OPTSR_IWDG1_SW)
#define | OB_IWDG1_SW ((uint32_t)0x00000U)
#define | OB_STOP_RST_D1 ((uint32_t)0x0000U)
#define | OB_STOP_NO_RST_D1 ((uint32_t)FLASH_OPTSR_NRST_STOP_D1)
#define | OB_STDBY_RST_D1 ((uint32_t)0x0000U)
#define | OB_STDBY_NO_RST_D1 ((uint32_t)FLASH_OPTSR_NRST_STBY_D1)
#define | OB_SWAP_BANK_DISABLE ((uint32_t)0x00000U)
#define | OB_SWAP_BANK_ENABLE ((uint32_t)FLASH_OPTSR_SWAP_BANK_OPT)
#define | OB_IOHSLV_DISABLE ((uint32_t)0x00000000U)
#define | OB_IOHSLV_ENABLE ((uint32_t)FLASH_OPTSR_IO_HSLV)
#define | OB_BOOT_ADD0 ((uint32_t)0x01U)
#define | OB_BOOT_ADD1 ((uint32_t)0x02U)
#define | OB_BOOT_ADD_BOTH ((uint32_t)0x03U)
#define | OB_USER_NRST_STOP_D1 ((uint32_t)0x0001U)
#define | OB_USER_NRST_STDBY_D1 ((uint32_t)0x0002U)
#define | OB_USER_IWDG_STOP ((uint32_t)0x0004U)
#define | OB_USER_IWDG_STDBY ((uint32_t)0x0008U)
#define | OB_USER_ST_RAM_SIZE ((uint32_t)0x0010U)
#define | OB_USER_SECURITY ((uint32_t)0x0020U)
#define | OB_USER_SWAP_BANK ((uint32_t)0x0100U)
#define | OB_USER_IOHSLV ((uint32_t)0x0200U)
#define | OB_USER_IWDG1_SW ((uint32_t)0x0400U)
#define | OB_SECURE_RDP_NOT_ERASE ((uint32_t)0x00000000U)
#define | OB_SECURE_RDP_ERASE ((uint32_t)FLASH_SCAR_DMES)
#define | __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14)
Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)
#define | IS_FLASH_TYPEERASE(VALUE)
#define | IS_VOLTAGERANGE(RANGE)
#define | IS_WRPSTATE(VALUE)
#define | IS_OPTIONBYTE(VALUE)
#define | IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U)
#define | IS_OB_RDP_LEVEL(LEVEL)
#define | IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
#define | IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define | IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
#define | IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
#define | IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
#define | IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
#define | IS_OB_BOR_LEVEL(LEVEL)
#define | IS_FLASH_LATENCY(LATENCY)
#define | IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
#define | IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
#define | IS_FLASH_SECTOR(SECTOR)
#define | IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xFFFFFF00) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#define | IS_FLASH_BANK(BANK)
#define | IS_OB_PCROP_RDP(CONFIG)
#define | IS_OB_SECURE_RDP(CONFIG)
#define | IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))
#define | IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
#define | IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
#define | IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
#define | IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
#define | IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))
#define | IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))
#define | IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE)) /*User can only move the security bit from 0 to 1*/
#define | IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x400U) && ((TYPE) != 0))
#define | IS_OB_BOOT_ADD_OPTION(VALUE)

Functions

HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
Perform a mass erase or erase the specified FLASH memory sectors.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option byte configuration.
HAL_StatusTypeDef | HAL_FLASHEx_Unlock_Bank1 (void)
Unlock the FLASH Bank1 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_Lock_Bank1 (void)
Locks the FLASH Bank1 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_Unlock_Bank2 (void)
Unlock the FLASH Bank2 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_Lock_Bank2 (void)
Locks the FLASH Bank2 control registers access.
void | FLASH_Erase_Sector (uint32_t Sector, uint32_t Bank, uint32_t VoltageRange)
Erase the specified FLASH memory sector.

Detailed Description

Header file of FLASH HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_flash_ex.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_gpio.h File Reference

  • File List
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  • Drivers
  • STM32H7xx_HAL_Driver
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Data Structures | Defines | Enumerations | Functions
stm32h7xx_hal_gpio.h File Reference

Header file of GPIO HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_gpio_ex.h"

Go to the source code of this file.

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Defines

#define | GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
#define | GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
#define | GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
#define | GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
#define | GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
#define | GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
#define | GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
#define | GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
#define | GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
#define | GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
#define | GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
#define | GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
#define | GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
#define | GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
#define | GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
#define | GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
#define | GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
#define | GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */
#define | GPIO_MODE_INPUT ((uint32_t)0x00000000U)
#define | GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U)
#define | GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U)
#define | GPIO_MODE_AF_PP ((uint32_t)0x00000002U)
#define | GPIO_MODE_AF_OD ((uint32_t)0x00000012U)
#define | GPIO_MODE_ANALOG ((uint32_t)0x00000003U)
#define | GPIO_MODE_IT_RISING ((uint32_t)0x11110000U)
#define | GPIO_MODE_IT_FALLING ((uint32_t)0x11210000U)
#define | GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x11310000U)
#define | GPIO_MODE_EVT_RISING ((uint32_t)0x11120000U)
#define | GPIO_MODE_EVT_FALLING ((uint32_t)0x11220000U)
#define | GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x11320000U)
#define | GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U)
#define | GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U)
#define | GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U)
#define | GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U)
#define | GPIO_NOPULL ((uint32_t)0x00000000U)
#define | GPIO_PULLUP ((uint32_t)0x00000001U)
#define | GPIO_PULLDOWN ((uint32_t)0x00000002U)
#define | __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__))
Checks whether the specified EXTI line flag is set or not.
#define | __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__))
Clears the EXTI's line pending flags.
#define | __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__))
Checks whether the specified EXTI line is asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__))
Clears the EXTI's line pending bits.
#define | __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
Generates a Software interrupt on selected EXTI line.
#define | IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define | IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK ) != (uint32_t)0x00))
#define | IS_GPIO_MODE(MODE)
#define | IS_GPIO_SPEED(SPEED)
#define | IS_GPIO_PULL(PULL)

Enumerations

enum | GPIO_PinState { GPIO_PIN_RESET = 0, GPIO_PIN_SET }
GPIO Bit SET and Bit RESET enumeration. More...

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initializes the GPIOx peripheral registers to their default reset values.
GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Sets or clears the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggles the specified GPIO pins.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
Handle EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.

Detailed Description

Header file of GPIO HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_gpio.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_gpio_ex.h File Reference

  • File List
  • Globals
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  • STM32H7xx_HAL_Driver
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Defines
stm32h7xx_hal_gpio_ex.h File Reference

Header file of GPIO HAL Extension module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
AF 0 selection.
#define | GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define | GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define | GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
#define | GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
#define | GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
AF 1 selection.
#define | GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#define | GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
#define | GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
#define | GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
#define | GPIO_AF1_HRTIM1 ((uint8_t)0x01) /* HRTIM1 Alternate Function mapping */
#define | GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
AF 2 selection.
#define | GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define | GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
#define | GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */
#define | GPIO_AF2_HRTIM1 ((uint8_t)0x02) /* HRTIM2 Alternate Function mapping */
#define | GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */
#define | GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
AF 3 selection.
#define | GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */
#define | GPIO_AF3_DFSDM1 ((uint8_t)0x03) /* DFSDM Alternate Function mapping */
#define | GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM3 Alternate Function mapping */
#define | GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */
#define | GPIO_AF3_LPTIM4 ((uint8_t)0x03) /* LPTIM4 Alternate Function mapping */
#define | GPIO_AF3_LPTIM5 ((uint8_t)0x03) /* LPTIM5 Alternate Function mapping */
#define | GPIO_AF3_LPUART ((uint8_t)0x03) /* LPUART Alternate Function mapping */
#define | GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
AF 4 selection.
#define | GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define | GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#define | GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
#define | GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */
#define | GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
#define | GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */
#define | GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
#define | GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM Alternate Function mapping */
#define | GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
AF 5 selection.
#define | GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#define | GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */
#define | GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
#define | GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
#define | GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
#define | GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */
#define | GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
AF 6 selection.
#define | GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
#define | GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
#define | GPIO_AF6_SAI3 ((uint8_t)0x06) /* SAI3 Alternate Function mapping */
#define | GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */
#define | GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */
#define | GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */
#define | GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */
AF 7 selection.
#define | GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */
#define | GPIO_AF7_SPI6 ((uint8_t)0x07) /* SPI6 Alternate Function mapping */
#define | GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
#define | GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define | GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#define | GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */
#define | GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */
#define | GPIO_AF7_DFSDM1 ((uint8_t)0x07) /* DFSDM Alternate Function mapping */
#define | GPIO_AF7_SDIO1 ((uint8_t)0x07) /* SDIO1 Alternate Function mapping */
#define | GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */
AF 8 selection.
#define | GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
#define | GPIO_AF8_SAI4 ((uint8_t)0x08) /* SAI4 Alternate Function mapping */
#define | GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define | GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define | GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
#define | GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */
#define | GPIO_AF8_LPUART ((uint8_t)0x08) /* LPUART Alternate Function mapping */
#define | GPIO_AF8_SDIO1 ((uint8_t)0x08) /* SDIO1 Alternate Function mapping */
#define | GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
AF 9 selection.
#define | GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */
#define | GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
#define | GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
#define | GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */
#define | GPIO_AF9_SDIO2 ((uint8_t)0x09) /* SDIO2 Alternate Function mapping */
#define | GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */
#define | GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */
#define | GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */
#define | GPIO_AF9_SAI4 ((uint8_t)0x09) /* SAI4 Alternate Function mapping */
#define | GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */
AF 10 selection.
#define | GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */
#define | GPIO_AF10_SAI4 ((uint8_t)0xA) /* SAI4 Alternate Function mapping */
#define | GPIO_AF10_SDIO2 ((uint8_t)0xA) /* SDIO2 Alternate Function mapping */
#define | GPIO_AF10_OTG2_HS ((uint8_t)0xA) /* OTG2_HS Alternate Function mapping */
#define | GPIO_AF10_OTG1_FS ((uint8_t)0xA) /* OTG1_FS Alternate Function mapping */
#define | GPIO_AF10_COMP1 ((uint8_t)0xA) /* COMP1 Alternate Function mapping */
#define | GPIO_AF10_COMP2 ((uint8_t)0xA) /* COMP2 Alternate Function mapping */
#define | GPIO_AF10_LTDC ((uint8_t)0xA) /* LTDC Alternate Function mapping */
#define | GPIO_AF11_SWP ((uint8_t)0x0B) /* SWP Alternate Function mapping */
AF 11 selection.
#define | GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */
#define | GPIO_AF11_MDIOS ((uint8_t)0x0B) /* MDIOS Alternate Function mapping */
#define | GPIO_AF11_OTG1_HS ((uint8_t)0x0B) /* OTG1_HS Alternate Function mapping */
#define | GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */
#define | GPIO_AF11_SDIO2 ((uint8_t)0x0B) /* SDIO2 Alternate Function mapping */
#define | GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM Alternate Function mapping */
#define | GPIO_AF11_COMP1 ((uint8_t)0x0B) /* COMP1 Alternate Function mapping */
#define | GPIO_AF11_COMP2 ((uint8_t)0x0B) /* COMP2 Alternate Function mapping */
#define | GPIO_AF11_I2C4 ((uint8_t)0x0B) /* I2C4 Alternate Function mapping */
#define | GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
AF 12 selection.
#define | GPIO_AF12_SDIO1 ((uint8_t)0xC) /* SDIO1 Alternate Function mapping */
#define | GPIO_AF12_MDIOS ((uint8_t)0xC) /* MDIOS Alternate Function mapping */
#define | GPIO_AF12_OTG2_FS ((uint8_t)0xC) /* OTG2_FS Alternate Function mapping */
#define | GPIO_AF12_COMP1 ((uint8_t)0xC) /* COMP1 Alternate Function mapping */
#define | GPIO_AF12_COMP2 ((uint8_t)0xC) /* COMP2 Alternate Function mapping */
#define | GPIO_AF12_LTDC ((uint8_t)0xC) /* LTDC Alternate Function mapping */
#define | GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
AF 13 selection.
#define | GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */
#define | GPIO_AF13_COMP1 ((uint8_t)0x0D) /* COMP1 Alternate Function mapping */
#define | GPIO_AF13_COMP2 ((uint8_t)0x0D) /* COMP2 Alternate Function mapping */
#define | GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */
#define | GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */
AF 14 selection.
#define | GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */
#define | GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
AF 15 selection.
#define | IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
#define | GPIOA_PIN_AVAILABLE GPIO_PIN_All
GPIO pin available on the platform.
#define | GPIOB_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOC_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOD_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOE_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOF_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOG_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOI_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOJ_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOH_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOK_PIN_AVAILABLE
#define | GPIO_GET_INDEX(__GPIOx__)
#define | IS_GPIO_PIN_AVAILABLE(__INSTANCE__, __PIN__)

Detailed Description

Header file of GPIO HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_gpio_ex.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_hash.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32h7xx_hal_hash.h File Reference

Header file of HASH HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_hash_ex.h"

Go to the source code of this file.

Data Structures

struct | HASH_InitTypeDef
HASH Configuration Structure definition. More...
struct | HASH_HandleTypeDef
HASH Handle Structure definition. More...

Defines

#define | HASH_ALGOSELECTION_SHA1 ((uint32_t)0x0000)
#define | HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1
#define | HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO
#define | HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0
#define | HASH_ALGOMODE_HASH ((uint32_t)0x00000000)
#define | HASH_ALGOMODE_HMAC HASH_CR_MODE
#define | HASH_DATATYPE_32B ((uint32_t)0x0000)
#define | HASH_DATATYPE_16B HASH_CR_DATATYPE_0
#define | HASH_DATATYPE_8B HASH_CR_DATATYPE_1
#define | HASH_DATATYPE_1B HASH_CR_DATATYPE
#define | HASH_HMAC_KEYTYPE_SHORTKEY ((uint32_t)0x00000000)
#define | HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY
#define | HASH_FLAG_DINIS HASH_SR_DINIS
#define | HASH_FLAG_DCIS HASH_SR_DCIS
#define | HASH_FLAG_DMAS HASH_SR_DMAS
#define | HASH_FLAG_BUSY HASH_SR_BUSY
#define | HASH_FLAG_DINNE HASH_CR_DINNE
#define | HASH_IT_DINI HASH_IMR_DINIE
#define | HASH_IT_DCI HASH_IMR_DCIE
#define | HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler
#define | __HAL_HASH_GET_FLAG(__FLAG__)
Check whether or not the specified HASH flag is set.
#define | __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__))
Clear the specified HASH flag.
#define | __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__))
Enable the specified HASH interrupt.
#define | __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
Disable the specified HASH interrupt.
#define | __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
Reset HASH handle state.
#define | __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
Reset HASH handle status.
#define | __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT)
Enable the multi-buffer DMA transfer mode.
#define | __HAL_HASH_RESET_MDMAT() CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)
Disable the multi-buffer DMA transfer mode.
#define | __HAL_HASH_START_DIGEST() SET_BIT(HASH->STR, HASH_STR_DCAL)
Start the digest computation.
#define | __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * ((__SIZE__) % 4))
Set the number of valid bits in the last word written in data register DIN.
#define | __HAL_HASH_INIT() SET_BIT(HASH->CR, HASH_CR_INIT)
Reset the HASH core.
#define | HASH_DIGEST_LENGTH()
Return digest length in bytes.
#define | HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8)
Return number of words already pushed in the FIFO.
#define | IS_HASH_DATATYPE(__DATATYPE__)
Ensure that HASH input data type is valid.
#define | IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4) == 0)
Ensure that input data buffer size is valid for multi-buffer HASH processing in polling mode.
#define | IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == RESET) || (((__SIZE__) % 4) == 0))
Ensure that input data buffer size is valid for multi-buffer HASH processing in DMA mode.
#define | IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__, __SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4) == 0))
Ensure that input data buffer size is valid for multi-buffer HMAC processing in DMA mode.
#define | IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
Ensure that handle phase is set to HASH processing.
#define | IS_HMAC_PROCESSING(__HANDLE__)
Ensure that handle phase is set to HMAC processing.

Enumerations

enum HAL_HASH_StateTypeDef {
HAL_HASH_STATE_RESET = 0x00, HAL_HASH_STATE_READY = 0x01, HAL_HASH_STATE_BUSY = 0x02, HAL_HASH_STATE_TIMEOUT = 0x06,
HAL_HASH_STATE_ERROR = 0x07, HAL_HASH_STATE_SUSPENDED = 0x08
}
HAL State structures definition. More...
enum HAL_HASH_PhaseTypeDef {
HAL_HASH_PHASE_READY = 0x01, HAL_HASH_PHASE_PROCESS = 0x02, HAL_HASH_PHASE_HMAC_STEP_1 = 0x03, HAL_HASH_PHASE_HMAC_STEP_2 = 0x04,
HAL_HASH_PHASE_HMAC_STEP_3 = 0x05
}
HAL phase structures definition. More...
enum | HAL_HASH_SuspendTypeDef { HAL_HASH_SUSPEND_NONE = 0x00, HAL_HASH_SUSPEND = 0x01 }
HAL HASH mode suspend definitions. More...

Functions

HAL_StatusTypeDef | HAL_HASH_Init (HASH_HandleTypeDef *hhash)
Initialize the HASH according to the specified parameters in the HASH_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_HASH_DeInit (HASH_HandleTypeDef *hhash)
DeInitialize the HASH peripheral.
__weak void | HAL_HASH_MspInit (HASH_HandleTypeDef *hhash)
Initialize the HASH MSP.
__weak void | HAL_HASH_MspDeInit (HASH_HandleTypeDef *hhash)
DeInitialize the HASH MSP.
__weak void | HAL_HASH_InCpltCallback (HASH_HandleTypeDef *hhash)
Input data transfer complete call back.
__weak void | HAL_HASH_DgstCpltCallback (HASH_HandleTypeDef *hhash)
Digest computation complete call back.
__weak void | HAL_HASH_ErrorCallback (HASH_HandleTypeDef *hhash)
Error callback.
HAL_StatusTypeDef | HAL_HASH_SHA1_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASH_MD5_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in MD5 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASH_MD5_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in MD5 mode then processes pInBuffer.
HAL_StatusTypeDef | HAL_HASH_SHA1_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in SHA1 mode then processes pInBuffer.
HAL_StatusTypeDef | HAL_HASH_SHA1_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HAL_HASH_MD5_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in MD5 mode, next process pInBuffer then read the computed digest in interruption mode.
void | HAL_HASH_IRQHandler (HASH_HandleTypeDef *hhash)
Handle HASH interrupt request.
HAL_StatusTypeDef | HAL_HASH_SHA1_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASH_SHA1_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in SHA1 mode.
HAL_StatusTypeDef | HAL_HASH_MD5_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASH_MD5_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in MD5 mode.
HAL_StatusTypeDef | HAL_HMAC_SHA1_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HMAC_MD5_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HMAC_MD5_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then read the computed digest in interrupt mode.
HAL_StatusTypeDef | HAL_HMAC_SHA1_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then read the computed digest in interrupt mode.
HAL_StatusTypeDef | HAL_HMAC_SHA1_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.
HAL_StatusTypeDef | HAL_HMAC_MD5_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC MD5 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.
HAL_HASH_StateTypeDef | HAL_HASH_GetState (HASH_HandleTypeDef *hhash)
Return the HASH handle state.
HAL_StatusTypeDef | HAL_HASH_GetStatus (HASH_HandleTypeDef *hhash)
Return the HASH HAL status.
void | HAL_HASH_ContextSaving (HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
Save the HASH context in case of processing suspension.
void | HAL_HASH_ContextRestoring (HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
Restore the HASH context in case of processing resumption.
void | HAL_HASH_SwFeed_ProcessSuspend (HASH_HandleTypeDef *hhash)
Initiate HASH processing suspension when in polling or interruption mode.
HAL_StatusTypeDef | HAL_HASH_DMAFeed_ProcessSuspend (HASH_HandleTypeDef *hhash)
Suspend the HASH processing when in DMA mode.
HAL_StatusTypeDef | HASH_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
Initialize the HASH peripheral, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HASH_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
If not already done, initialize the HASH peripheral then processes pInBuffer.
HAL_StatusTypeDef | HASH_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm)
Initialize the HASH peripheral, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HASH_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
Initialize the HASH peripheral then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HASH_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest.
HAL_StatusTypeDef | HMAC_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
Initialize the HASH peripheral in HMAC mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HMAC_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm)
Initialize the HASH peripheral in HMAC mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HMAC_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
Initialize the HASH peripheral in HMAC mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.

Detailed Description

Header file of HASH HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_hash.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_hash_ex.h File Reference

  • File List
  • Globals
  • Drivers
  • STM32H7xx_HAL_Driver
  • Inc
Functions
stm32h7xx_hal_hash_ex.h File Reference

Header file of HASH HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_HASHEx_SHA224_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASHEx_SHA224_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in SHA224 mode then processes pInBuffer.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in SHA256 mode then processes pInBuffer.
HAL_StatusTypeDef | HAL_HASHEx_SHA224_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HAL_HASHEx_SHA224_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASHEx_SHA224_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in SHA224 mode.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in SHA256 mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then read the computed digest in interrupt mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then read the computed digest in interrupt mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.
HAL_StatusTypeDef | HAL_HMACEx_MD5_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_MD5_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
MD5 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_MD5_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA1_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA1_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA1 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA1_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA224 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA256 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.

Detailed Description

Header file of HASH HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_hash_ex.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_hcd.h File Reference

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stm32h7xx_hal_hcd.h File Reference

Header file of HCD HAL module. More...

#include "stm32h7xx_ll_usb.h"

Go to the source code of this file.

Data Structures

struct | HCD_HandleTypeDef

Defines

#define | HCD_SPEED_HIGH 0
#define | HCD_SPEED_LOW 2
#define | HCD_SPEED_FULL 3
#define | HCD_PHY_ULPI 1
#define | HCD_PHY_EMBEDDED 2
#define | __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define | __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
#define | __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
#define | __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
#define | __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
#define | __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
#define | __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
#define | IS_HCD_ALL_INSTANCE(INSTANCE)

Typedefs

typedef USB_OTG_GlobalTypeDef | HCD_TypeDef
typedef USB_OTG_CfgTypeDef | HCD_InitTypeDef
typedef USB_OTG_HCTypeDef | HCD_HCTypeDef
typedef USB_OTG_URBStateTypeDef | HCD_URBStateTypeDef
typedef USB_OTG_HCStateTypeDef | HCD_HCStateTypeDef

Enumerations

enum HCD_StateTypeDef {
HAL_HCD_STATE_RESET = 0x00, HAL_HCD_STATE_READY = 0x01, HAL_HCD_STATE_ERROR = 0x02, HAL_HCD_STATE_BUSY = 0x03,
HAL_HCD_STATE_TIMEOUT = 0x04
}

Functions

HAL_StatusTypeDef | HAL_HCD_Init (HCD_HandleTypeDef *hhcd)
Initialize the host driver.
HAL_StatusTypeDef | HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the host driver.
HAL_StatusTypeDef | HAL_HCD_HC_Init (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
Initialize a host channel.
HAL_StatusTypeDef | HAL_HCD_HC_Halt (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
Halt a host channel.
__weak void | HAL_HCD_MspInit (HCD_HandleTypeDef *hhcd)
Initializes the HCD MSP.
__weak void | HAL_HCD_MspDeInit (HCD_HandleTypeDef *hhcd)
DeInitializes HCD MSP.
HAL_StatusTypeDef | HAL_HCD_HC_SubmitRequest (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t direction, uint8_t ep_type, uint8_t token, uint8_t *pbuff, uint16_t length, uint8_t do_ping)
Submit a new URB for processing.
void | HAL_HCD_IRQHandler (HCD_HandleTypeDef *hhcd)
This function handles HCD interrupt request.
__weak void | HAL_HCD_SOF_Callback (HCD_HandleTypeDef *hhcd)
SOF callback.
__weak void | HAL_HCD_Connect_Callback (HCD_HandleTypeDef *hhcd)
Connexion Event callback.
__weak void | HAL_HCD_Disconnect_Callback (HCD_HandleTypeDef *hhcd)
Disconnexion Event callback.
__weak void | HAL_HCD_HC_NotifyURBChange_Callback (HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
Notify URB state change callback.
HAL_StatusTypeDef | HAL_HCD_ResetPort (HCD_HandleTypeDef *hhcd)
Reset the host port.
HAL_StatusTypeDef | HAL_HCD_Start (HCD_HandleTypeDef *hhcd)
Start the host driver.
HAL_StatusTypeDef | HAL_HCD_Stop (HCD_HandleTypeDef *hhcd)
Stop the host driver.
HCD_StateTypeDef | HAL_HCD_GetState (HCD_HandleTypeDef *hhcd)
Return the HCD state.
HCD_URBStateTypeDef | HAL_HCD_HC_GetURBState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return URB state for a channel.
uint32_t | HAL_HCD_HC_GetXferCount (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the last host transfer size.
HCD_HCStateTypeDef | HAL_HCD_HC_GetState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the Host Channel state.
uint32_t | HAL_HCD_GetCurrentFrame (HCD_HandleTypeDef *hhcd)
Return the current Host frame number.
uint32_t | HAL_HCD_GetCurrentSpeed (HCD_HandleTypeDef *hhcd)
Return the Host enumeration speed.

Detailed Description

Header file of HCD HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_hcd.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_hrtim.h File Reference

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stm32h7xx_hal_hrtim.h File Reference

Header file of HRTIM HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | HRTIM_InitTypeDef
HRTIM Configuration Structure definition - Time base related parameters. More...
struct | HRTIM_TimerParamTypeDef
HRTIM Timer Structure definition. More...
struct | __HRTIM_HandleTypeDef
HRTIM Handle Structure definition. More...
struct | HRTIM_TimeBaseCfgTypeDef
Simple output compare mode configuration definition. More...
struct | HRTIM_SimpleOCChannelCfgTypeDef
Simple output compare mode configuration definition. More...
struct | HRTIM_SimplePWMChannelCfgTypeDef
Simple PWM output mode configuration definition. More...
struct | HRTIM_SimpleCaptureChannelCfgTypeDef
Simple capture mode configuration definition. More...
struct | HRTIM_SimpleOnePulseChannelCfgTypeDef
Simple One Pulse mode configuration definition. More...
struct | HRTIM_TimerCfgTypeDef
Timer configuration definition. More...
struct | HRTIM_CompareCfgTypeDef
Compare unit configuration definition. More...
struct | HRTIM_CaptureCfgTypeDef
Capture unit configuration definition. More...
struct | HRTIM_OutputCfgTypeDef
Output configuration definition. More...
struct | HRTIM_TimerEventFilteringCfgTypeDef
External event filtering in timing units configuration definition. More...
struct | HRTIM_DeadTimeCfgTypeDef
Dead time feature configuration definition. More...
struct | HRTIM_ChopperModeCfgTypeDef
Chopper mode configuration definition. More...
struct | HRTIM_EventCfgTypeDef
External event channel configuration definition. More...
struct | HRTIM_FaultCfgTypeDef
Fault channel configuration definition. More...
struct | HRTIM_BurstModeCfgTypeDef
Burst mode configuration definition. More...
struct | HRTIM_ADCTriggerCfgTypeDef
ADC trigger configuration definition. More...

Defines

#define | MAX_HRTIM_TIMER 6U
#define | HRTIM_TIMERINDEX_TIMER_A (uint32_t)0x0U
#define | HRTIM_TIMERINDEX_TIMER_B (uint32_t)0x1U
#define | HRTIM_TIMERINDEX_TIMER_C (uint32_t)0x2U
#define | HRTIM_TIMERINDEX_TIMER_D (uint32_t)0x3U
#define | HRTIM_TIMERINDEX_TIMER_E (uint32_t)0x4U
#define | HRTIM_TIMERINDEX_MASTER (uint32_t)0x5U
#define | HRTIM_TIMERINDEX_COMMON (uint32_t)0xFFU
#define | HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN)
#define | HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN)
#define | HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN)
#define | HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN)
#define | HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN)
#define | HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN)
#define | IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U)
#define | HRTIM_COMPAREUNIT_1 (uint32_t)0x00000001U
#define | HRTIM_COMPAREUNIT_2 (uint32_t)0x00000002U
#define | HRTIM_COMPAREUNIT_3 (uint32_t)0x00000004U
#define | HRTIM_COMPAREUNIT_4 (uint32_t)0x00000008U
#define | HRTIM_CAPTUREUNIT_1 (uint32_t)0x00000001U
#define | HRTIM_CAPTUREUNIT_2 (uint32_t)0x00000002U
#define | HRTIM_OUTPUT_TA1 (uint32_t)0x00000001U
#define | HRTIM_OUTPUT_TA2 (uint32_t)0x00000002U
#define | HRTIM_OUTPUT_TB1 (uint32_t)0x00000004U
#define | HRTIM_OUTPUT_TB2 (uint32_t)0x00000008U
#define | HRTIM_OUTPUT_TC1 (uint32_t)0x00000010U
#define | HRTIM_OUTPUT_TC2 (uint32_t)0x00000020U
#define | HRTIM_OUTPUT_TD1 (uint32_t)0x00000040U
#define | HRTIM_OUTPUT_TD2 (uint32_t)0x00000080U
#define | HRTIM_OUTPUT_TE1 (uint32_t)0x00000100U
#define | HRTIM_OUTPUT_TE2 (uint32_t)0x00000200U
#define | HRTIM_ADCTRIGGER_1 (uint32_t)0x00000001U
#define | HRTIM_ADCTRIGGER_2 (uint32_t)0x00000002U
#define | HRTIM_ADCTRIGGER_3 (uint32_t)0x00000004U
#define | HRTIM_ADCTRIGGER_4 (uint32_t)0x00000008U
#define | HRTIM_EVENT_NONE ((uint32_t)0x00000000U)
#define | HRTIM_EVENT_1 ((uint32_t)0x00000001U)
#define | HRTIM_EVENT_2 ((uint32_t)0x00000002U)
#define | HRTIM_EVENT_3 ((uint32_t)0x00000004U)
#define | HRTIM_EVENT_4 ((uint32_t)0x00000008U)
#define | HRTIM_EVENT_5 ((uint32_t)0x00000010U)
#define | HRTIM_EVENT_6 ((uint32_t)0x00000020U)
#define | HRTIM_EVENT_7 ((uint32_t)0x00000040U)
#define | HRTIM_EVENT_8 ((uint32_t)0x00000080U)
#define | HRTIM_EVENT_9 ((uint32_t)0x00000100U)
#define | HRTIM_EVENT_10 ((uint32_t)0x00000200U)
#define | HRTIM_FAULT_1 ((uint32_t)0x01U)
#define | HRTIM_FAULT_2 ((uint32_t)0x02U)
#define | HRTIM_FAULT_3 ((uint32_t)0x04U)
#define | HRTIM_FAULT_4 ((uint32_t)0x08U)
#define | HRTIM_FAULT_5 ((uint32_t)0x10U)
#define | HRTIM_PRESCALERRATIO_MUL32 ((uint32_t)0x00000000U)
#define | HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001U)
#define | HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002U)
#define | HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003U)
#define | HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004U)
#define | HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005U)
#define | HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006U)
#define | HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007U)
#define | HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008U)
#define | HRTIM_MODE_SINGLESHOT ((uint32_t)0x00000000U)
#define | HRTIM_MODE_SINGLESHOT_RETRIGGERABLE ((uint32_t)0x00000010U)
#define | HRTIM_HALFMODE_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_HALFMODE_ENABLED ((uint32_t)0x00000020U)
#define | HRTIM_SYNCSTART_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM)
#define | HRTIM_SYNCRESET_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM)
#define | HRTIM_DACSYNC_NONE ((uint32_t)0x00000000U)
#define | HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0)
#define | HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1)
#define | HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0)
#define | HRTIM_PRELOAD_DISABLED 0x00000000U
#define | HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN)
#define | HRTIM_UPDATEGATING_INDEPENDENT ((uint32_t)0x00000000U)
#define | HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0)
#define | HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1)
#define | HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)
#define | HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2)
#define | HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0)
#define | HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1)
#define | HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)
#define | HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3)
#define | HRTIM_TIMERBURSTMODE_MAINTAINCLOCK ((uint32_t)0x000000U)
#define | HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM)
#define | HRTIM_UPDATEONREPETITION_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU)
#define | HRTIM_TIMPUSHPULLMODE_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_TIMPUSHPULLMODE_ENABLED ((uint32_t)HRTIM_TIMCR_PSHPLL)
#define | HRTIM_TIMFAULTENABLE_NONE ((uint32_t)0x00000000U)
#define | HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN)
#define | HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN)
#define | HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN)
#define | HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN)
#define | HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN)
#define | HRTIM_TIMFAULTLOCK_READWRITE ((uint32_t)0x00000000U)
#define | HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTLCK)
#define | HRTIM_TIMDEADTIMEINSERTION_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN
#define | HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 (HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)
#define | HRTIM_TIMUPDATETRIGGER_NONE ((uint32_t)0x00000000U)
#define | HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU)
#define | HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU)
#define | HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU)
#define | HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU)
#define | HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU)
#define | HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU)
#define | HRTIM_TIMRESETTRIGGER_NONE ((uint32_t)0x00000000U)
#define | HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE)
#define | HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2)
#define | HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4)
#define | HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER)
#define | HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1)
#define | HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2)
#define | HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3)
#define | HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4)
#define | HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1)
#define | HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2)
#define | HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3)
#define | HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4)
#define | HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5)
#define | HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6)
#define | HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7)
#define | HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8)
#define | HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9)
#define | HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10)
#define | HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1)
#define | HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2)
#define | HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4)
#define | HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1)
#define | HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2)
#define | HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4)
#define | HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1)
#define | HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2)
#define | HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4)
#define | HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1)
#define | HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2)
#define | HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4)
#define | HRTIM_TIMUPDATEONRESET_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU)
#define | HRTIM_AUTODELAYEDMODE_REGULAR ((uint32_t)0x00000000U)
#define | HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0)
#define | HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1)
#define | HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0)
#define | HRTIM_BASICOCMODE_TOGGLE (0x00000001U)
#define | HRTIM_BASICOCMODE_INACTIVE (0x00000002U)
#define | HRTIM_BASICOCMODE_ACTIVE (0x00000003U)
#define | HRTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U)
#define | HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1)
#define | HRTIM_OUTPUTSET_NONE ((uint32_t)0x00000000U)
#define | HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC)
#define | HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER)
#define | HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1)
#define | HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2)
#define | HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3)
#define | HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4)
#define | HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER)
#define | HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1)
#define | HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2)
#define | HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3)
#define | HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4)
#define | HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
#define | HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
#define | HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
#define | HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
#define | HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
#define | HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
#define | HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
#define | HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
#define | HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
#define | HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1)
#define | HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2)
#define | HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3)
#define | HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4)
#define | HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5)
#define | HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6)
#define | HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7)
#define | HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8)
#define | HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9)
#define | HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10)
#define | HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE)
#define | HRTIM_OUTPUTRESET_NONE ((uint32_t)0x00000000U)
#define | HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC)
#define | HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER)
#define | HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1)
#define | HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2)
#define | HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3)
#define | HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4)
#define | HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER)
#define | HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1)
#define | HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2)
#define | HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3)
#define | HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4)
#define | HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
#define | HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
#define | HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
#define | HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
#define | HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
#define | HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
#define | HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
#define | HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
#define | HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
#define | HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1)
#define | HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2)
#define | HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3)
#define | HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4)
#define | HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5)
#define | HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6)
#define | HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7)
#define | HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8)
#define | HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9)
#define | HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10)
#define | HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE)
#define | HRTIM_OUTPUTIDLEMODE_NONE ((uint32_t)0x00000000U)
#define | HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1)
#define | HRTIM_OUTPUTIDLELEVEL_INACTIVE ((uint32_t)0x00000000U)
#define | HRTIM_OUTPUTIDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1)
#define | HRTIM_OUTPUTFAULTLEVEL_NONE ((uint32_t)0x00000000U)
#define | HRTIM_OUTPUTFAULTLEVEL_ACTIVE (HRTIM_OUTR_FAULT1_0)
#define | HRTIM_OUTPUTFAULTLEVEL_INACTIVE (HRTIM_OUTR_FAULT1_1)
#define | HRTIM_OUTPUTFAULTLEVEL_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0)
#define | HRTIM_OUTPUTCHOPPERMODE_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1)
#define | HRTIM_OUTPUTBURSTMODEENTRY_REGULAR ((uint32_t)0x00000000U)
#define | HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1)
#define | HRTIM_CAPTURETRIGGER_NONE ((uint32_t)0x00000000U)
#define | HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT)
#define | HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT)
#define | HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT)
#define | HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT)
#define | HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT)
#define | HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT)
#define | HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT)
#define | HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT)
#define | HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT)
#define | HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT)
#define | HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT)
#define | HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET)
#define | HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST)
#define | HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TIMACMP1)
#define | HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TIMACMP2)
#define | HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET)
#define | HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST)
#define | HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TIMBCMP1)
#define | HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TIMBCMP2)
#define | HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET)
#define | HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST)
#define | HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TIMCCMP1)
#define | HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TIMCCMP2)
#define | HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET)
#define | HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST)
#define | HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TIMDCMP1)
#define | HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TIMDCMP2)
#define | HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET)
#define | HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST)
#define | HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TIMECMP1)
#define | HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TIMECMP2)
#define | HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
#define | HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
#define | HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
#define | HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define | HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
#define | HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define | HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define | HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define | HRTIM_TIMEVENTLATCH_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH
#define | HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 ((uint32_t)0x00000000U)
#define | HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0)
#define | HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1)
#define | HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)
#define | HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2)
#define | HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0)
#define | HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1)
#define | HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)
#define | HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE ((uint32_t)0x00000000U)
#define | HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR)
#define | HRTIM_TIMDEADTIME_RISINGLOCK_WRITE ((uint32_t)0x00000000U)
#define | HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK)
#define | HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE ((uint32_t)0x00000000U)
#define | HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK)
#define | HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE ((uint32_t)0x00000000U)
#define | HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF)
#define | HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE ((uint32_t)0x00000000U)
#define | HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK)
#define | HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE ((uint32_t)0x00000000U)
#define | HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV16 ((uint32_t)0x000000U)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV32 (HRTIM_CHPR_CARFRQ_0)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV48 (HRTIM_CHPR_CARFRQ_1)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV80 (HRTIM_CHPR_CARFRQ_2)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)
#define | HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)
#define | HRTIM_CHOPPER_DUTYCYCLE_0 ((uint32_t)0x000000U)
#define | HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0)
#define | HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1)
#define | HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0)
#define | HRTIM_CHOPPER_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2)
#define | HRTIM_CHOPPER_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0)
#define | HRTIM_CHOPPER_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1)
#define | HRTIM_CHOPPER_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0)
#define | HRTIM_CHOPPER_PULSEWIDTH_16 ((uint32_t)0x000000U)
#define | HRTIM_CHOPPER_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0)
#define | HRTIM_CHOPPER_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1)
#define | HRTIM_CHOPPER_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)
#define | HRTIM_CHOPPER_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2)
#define | HRTIM_CHOPPER_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)
#define | HRTIM_CHOPPER_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)
#define | HRTIM_CHOPPER_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)
#define | HRTIM_CHOPPER_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3)
#define | HRTIM_CHOPPER_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0)
#define | HRTIM_CHOPPER_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1)
#define | HRTIM_CHOPPER_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)
#define | HRTIM_CHOPPER_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2)
#define | HRTIM_CHOPPER_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)
#define | HRTIM_CHOPPER_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)
#define | HRTIM_CHOPPER_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)
#define | HRTIM_SYNCOPTION_NONE ((uint32_t)0x00000000U)
#define | HRTIM_SYNCOPTION_MASTER ((uint32_t)0x00000001U)
#define | HRTIM_SYNCOPTION_SLAVE ((uint32_t)0x00000002U)
#define | HRTIM_SYNCINPUTSOURCE_NONE ((uint32_t)0x00000000U)
#define | HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1
#define | HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0)
#define | HRTIM_SYNCOUTPUTSOURCE_MASTER_START ((uint32_t)0x00000000U)
#define | HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0)
#define | HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1)
#define | HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0)
#define | HRTIM_SYNCOUTPUTPOLARITY_NONE ((uint32_t)0x00000000U)
#define | HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_1)
#define | HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0)
#define | HRTIM_EVENTSRC_1 ((uint32_t)0x00000000U)
#define | HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
#define | HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
#define | HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
#define | HRTIM_EVENTPOLARITY_HIGH ((uint32_t)0x00000000U)
#define | HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL)
#define | HRTIM_EVENTSENSITIVITY_LEVEL ((uint32_t)0x00000000U)
#define | HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0)
#define | HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1)
#define | HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0)
#define | HRTIM_EVENTFASTMODE_DISABLE ((uint32_t)0x00000000U)
#define | HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST)
#define | HRTIM_EVENTFILTER_NONE ((uint32_t)0x00000000U)
#define | HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0)
#define | HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1)
#define | HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)
#define | HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2)
#define | HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0)
#define | HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1)
#define | HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)
#define | HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3)
#define | HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0)
#define | HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1)
#define | HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)
#define | HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2)
#define | HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0)
#define | HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1)
#define | HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)
#define | HRTIM_EVENTPRESCALER_DIV1 ((uint32_t)0x00000000U)
#define | HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0)
#define | HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1)
#define | HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0)
#define | HRTIM_FAULTSOURCE_DIGITALINPUT ((uint32_t)0x00000000U)
#define | HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC)
#define | HRTIM_FAULTPOLARITY_LOW ((uint32_t)0x00000000U)
#define | HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P)
#define | HRTIM_FAULTFILTER_NONE ((uint32_t)0x00000000U)
#define | HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0)
#define | HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1)
#define | HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)
#define | HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2)
#define | HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)
#define | HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)
#define | HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)
#define | HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3)
#define | HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0)
#define | HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1)
#define | HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)
#define | HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2)
#define | HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)
#define | HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)
#define | HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)
#define | HRTIM_FAULTLOCK_READWRITE ((uint32_t)0x00000000U)
#define | HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK)
#define | HRTIM_FAULTPRESCALER_DIV1 ((uint32_t)0x00000000U)
#define | HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0)
#define | HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1)
#define | HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0)
#define | HRTIM_BURSTMODE_SINGLESHOT ((uint32_t)0x00000000U)
#define | HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM)
#define | HRTIM_BURSTMODECLOCKSOURCE_MASTER ((uint32_t)0x00000000U)
#define | HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0)
#define | HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1)
#define | HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)
#define | HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2)
#define | HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0)
#define | HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1)
#define | HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)
#define | HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO (HRTIM_BMCR_BMCLK_3)
#define | HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1)
#define | HRTIM_BURSTMODEPRESCALER_DIV1 ((uint32_t)0x00000000U)
#define | HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0)
#define | HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1)
#define | HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)
#define | HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2)
#define | HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)
#define | HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)
#define | HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)
#define | HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3)
#define | HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0)
#define | HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1)
#define | HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)
#define | HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2)
#define | HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)
#define | HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)
#define | HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)
#define | HRIM_BURSTMODEPRELOAD_DISABLED ((uint32_t)0x00000000U)
#define | HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN)
#define | HRTIM_BURSTMODETRIGGER_NONE ((uint32_t)0x00000000U)
#define | HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST)
#define | HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP)
#define | HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1)
#define | HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2)
#define | HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3)
#define | HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4)
#define | HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST)
#define | HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP)
#define | HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1)
#define | HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2)
#define | HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST)
#define | HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP)
#define | HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1)
#define | HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2)
#define | HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST)
#define | HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP)
#define | HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1)
#define | HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2)
#define | HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST)
#define | HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP)
#define | HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1)
#define | HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2)
#define | HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST)
#define | HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP)
#define | HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1)
#define | HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2)
#define | HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7)
#define | HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8)
#define | HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7)
#define | HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8)
#define | HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV)
#define | HRTIM_ADCTRIGGERUPDATE_MASTER ((uint32_t)0x00000000U)
#define | HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0)
#define | HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1)
#define | HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0)
#define | HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2)
#define | HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0)
#define | HRTIM_ADCTRIGGEREVENT13_NONE ((uint32_t)0x00000000U)
#define | HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1)
#define | HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2)
#define | HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3)
#define | HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4)
#define | HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER)
#define | HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1)
#define | HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2)
#define | HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3)
#define | HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4)
#define | HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4)
#define | HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER)
#define | HRTIM_ADCTRIGGEREVENT24_NONE ((uint32_t)0x00000000U)
#define | HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1)
#define | HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2)
#define | HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3)
#define | HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4)
#define | HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER)
#define | HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6)
#define | HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7)
#define | HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8)
#define | HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9)
#define | HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4)
#define | HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST)
#define | HRTIM_BURSTDMA_NONE ((uint32_t)0x00000000U)
#define | HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR)
#define | HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR)
#define | HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER)
#define | HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT)
#define | HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER)
#define | HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP)
#define | HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1)
#define | HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2)
#define | HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3)
#define | HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4)
#define | HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR)
#define | HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R)
#define | HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R)
#define | HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R)
#define | HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R)
#define | HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1)
#define | HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2)
#define | HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR)
#define | HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR)
#define | HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR)
#define | HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR)
#define | HRTIM_BURSTMODECTL_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME)
#define | HRTIM_FAULTMODECTL_DISABLED ((uint32_t)0x00000000U)
#define | HRTIM_FAULTMODECTL_ENABLED ((uint32_t)0x00000001U)
#define | HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU)
#define | HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU)
#define | HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU)
#define | HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU)
#define | HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU)
#define | HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU)
#define | HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST)
#define | HRTIM_TIMERRESET_TIMER_A (HRTIM_CR2_TARST)
#define | HRTIM_TIMERRESET_TIMER_B (HRTIM_CR2_TBRST)
#define | HRTIM_TIMERRESET_TIMER_C (HRTIM_CR2_TCRST)
#define | HRTIM_TIMERRESET_TIMER_D (HRTIM_CR2_TDRST)
#define | HRTIM_TIMERRESET_TIMER_E (HRTIM_CR2_TERST)
#define | HRTIM_OUTPUTLEVEL_ACTIVE ((uint32_t)0x00000001U)
#define | HRTIM_OUTPUTLEVEL_INACTIVE ((uint32_t)0x00000002U)
#define | HRTIM_OUTPUTSTATE_IDLE ((uint32_t)0x00000001U)
#define | HRTIM_OUTPUTSTATE_RUN ((uint32_t)0x00000002U)
#define | HRTIM_OUTPUTSTATE_FAULT ((uint32_t)0x00000003U)
#define | HRTIM_BURSTMODESTATUS_NORMAL ((uint32_t) 0x00000000U)
#define | HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT)
#define | HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 ((uint32_t) 0x00000000U)
#define | HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT)
#define | HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 ((uint32_t) 0x00000000U)
#define | HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT)
#define | HRTIM_IT_NONE ((uint32_t)0x00000000U)
#define | HRTIM_IT_FLT1 HRTIM_IER_FLT1
#define | HRTIM_IT_FLT2 HRTIM_IER_FLT2
#define | HRTIM_IT_FLT3 HRTIM_IER_FLT3
#define | HRTIM_IT_FLT4 HRTIM_IER_FLT4
#define | HRTIM_IT_FLT5 HRTIM_IER_FLT5
#define | HRTIM_IT_SYSFLT HRTIM_IER_SYSFLT
#define | HRTIM_IT_BMPER HRTIM_IER_BMPER
#define | HRTIM_MASTER_IT_NONE ((uint32_t)0x00000000U)
#define | HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE
#define | HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE
#define | HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE
#define | HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE
#define | HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE
#define | HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE
#define | HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE
#define | HRTIM_TIM_IT_NONE ((uint32_t)0x00000000U)
#define | HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE
#define | HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE
#define | HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE
#define | HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE
#define | HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE
#define | HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE
#define | HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE
#define | HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE
#define | HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE
#define | HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE
#define | HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE
#define | HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE
#define | HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE
#define | HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE
#define | HRTIM_FLAG_FLT1 HRTIM_ISR_FLT1
#define | HRTIM_FLAG_FLT2 HRTIM_ISR_FLT2
#define | HRTIM_FLAG_FLT3 HRTIM_ISR_FLT3
#define | HRTIM_FLAG_FLT4 HRTIM_ISR_FLT4
#define | HRTIM_FLAG_FLT5 HRTIM_ISR_FLT5
#define | HRTIM_FLAG_SYSFLT HRTIM_ISR_SYSFLT
#define | HRTIM_FLAG_BMPER HRTIM_ISR_BMPER
#define | HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1
#define | HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2
#define | HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3
#define | HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4
#define | HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP
#define | HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC
#define | HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD
#define | HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1
#define | HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2
#define | HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3
#define | HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4
#define | HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP
#define | HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD
#define | HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1
#define | HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2
#define | HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1
#define | HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1
#define | HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2
#define | HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2
#define | HRTIM_TIM_FLAG_RST HRTIM_TIMISR_RST
#define | HRTIM_TIM_FLAG_DLYPRT HRTIM_TIMISR_DLYPRT
#define | HRTIM_MASTER_DMA_NONE ((uint32_t)0x00000000U)
#define | HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE
#define | HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE
#define | HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE
#define | HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE
#define | HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE
#define | HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE
#define | HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE
#define | HRTIM_TIM_DMA_NONE ((uint32_t)0x00000000U)
#define | HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE
#define | HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE
#define | HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE
#define | HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE
#define | HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE
#define | HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE
#define | HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE
#define | HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE
#define | HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE
#define | HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE
#define | HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE
#define | HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE
#define | HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE
#define | HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE
#define | IS_HRTIM_TIMERINDEX(TIMERINDEX)
#define | IS_HRTIM_TIMING_UNIT(TIMERINDEX)
#define | IS_HRTIM_COMPAREUNIT(COMPAREUNIT)
#define | IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)
#define | IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U)
#define | IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)
#define | IS_HRTIM_ADCTRIGGER(ADCTRIGGER)
#define | IS_HRTIM_EVENT(EVENT)
#define | IS_HRTIM_FAULT(FAULT)
#define | IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)
#define | IS_HRTIM_MODE(MODE)
#define | IS_HRTIM_MODE_ONEPULSE(MODE)
#define | IS_HRTIM_HALFMODE(HALFMODE)
#define | IS_HRTIM_SYNCSTART(SYNCSTART)
#define | IS_HRTIM_SYNCRESET(SYNCRESET)
#define | IS_HHRTIM_DACSYNC(DACSYNC)
#define | IS_HRTIM_PRELOAD(PRELOAD)
#define | IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)
#define | IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)
#define | IS_HRTIM_TIMERBURSTMODE(TIMERBURSTMODE)
#define | IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION)
#define | IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)
#define | IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U)
#define | IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)
#define | IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)
#define | IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)
#define | IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U)
#define | IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U)
#define | IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001U) == 0x00000000U)
#define | IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET)
#define | IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)
#define | IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE)
#define | IS_HRTIM_BASICOCMODE(BASICOCMODE)
#define | IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)
#define | IS_HRTIM_OUTPUTSET(OUTPUTSET)
#define | IS_HRTIM_OUTPUTRESET(OUTPUTRESET)
#define | IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)
#define | IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)
#define | IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)
#define | IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)
#define | IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)
#define | IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER)
#define | IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)
#define | IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)
#define | IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)
#define | IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)
#define | IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)
#define | IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)
#define | IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)
#define | IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)
#define | IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)
#define | IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)
#define | IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)
#define | IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)
#define | IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)
#define | IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)
#define | IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)
#define | IS_HRTIM_EVENTSRC(EVENTSRC)
#define | IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)
#define | IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)
#define | IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)
#define | IS_HRTIM_EVENTFILTER(EVENT, FILTER)
#define | IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)
#define | IS_HRTIM_FAULTSOURCE(FAULTSOURCE)
#define | IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)
#define | IS_HRTIM_FAULTFILTER(FAULTFILTER)
#define | IS_HRTIM_FAULTLOCK(FAULTLOCK)
#define | IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)
#define | IS_HRTIM_BURSTMODE(BURSTMODE)
#define | IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)
#define | IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)
#define | IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)
#define | IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)
#define | IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)
#define | IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA)
#define | IS_HRTIM_BURSTMODECTL(BURSTMODECTL)
#define | IS_HRTIM_FAULTMODECTL(FAULTMODECTL)
#define | IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U)
#define | IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FFU) == 0x00000000U)
#define | IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)
#define | IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0U) == 0x00000000U)
#define | IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U)
#define | IS_HRTIM_TIM_IT(IS_HRTIM_TIM_IT) (((IS_HRTIM_TIM_IT) & 0xFFFF8020U) == 0x00000000U)
#define | IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U)
#define | IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U)
#define | __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)
Reset HRTIM handle state.
#define | __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__))
Enables or disables the timer counter(s)
#define | HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
#define | HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
#define | HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
#define | HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
#define | HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
#define | __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)
#define | __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
Enables or disables the specified HRTIM common interrupts.
#define | __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
#define | __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__))
Enables or disables the specified HRTIM Master timer interrupts.
#define | __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))
#define | __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__))
Enables or disables the specified HRTIM Timerx interrupts.
#define | __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))
#define | __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified HRTIM common interrupt source is enabled or disabled.
#define | __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified HRTIM Master interrupt source is enabled or disabled.
#define | __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified HRTIM Timerx interrupt source is enabled or disabled.
#define | __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))
Clears the specified HRTIM common pending flag.
#define | __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__))
Clears the specified HRTIM Master pending flag.
#define | __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__))
Clears the specified HRTIM Timerx pending flag.
#define | __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
Enables or disables the specified HRTIM common interrupts.
#define | __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
#define | __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))
Enables or disables the specified HRTIM Master timer DMA requets.
#define | __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
#define | __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__))
Enables or disables the specified HRTIM Timerx DMA requests.
#define | __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))
#define | __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__))
#define | __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))
#define | __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__))
#define | __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))
#define | __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__,__TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__))
#define | __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__,__TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))
#define | __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__)
Sets the HRTIM timer Counter Register value on runtime.
#define | __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__)
Gets the HRTIM timer Counter Register value on runtime.
#define | __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__)
Sets the HRTIM timer Period value on runtime.
#define | __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__)
Gets the HRTIM timer Period Register value on runtime.
#define | __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__)
Sets the HRTIM timer clock prescaler value on runtime.
#define | __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__)
Gets the HRTIM timer clock prescaler value on runtime.
#define | __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__)
Sets the HRTIM timer Compare Register value on runtime.
#define | __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__)
Gets the HRTIM timer Compare Register value on runtime.

Typedefs

typedef struct
__HRTIM_HandleTypeDef 		HRTIM_HandleTypeDef
HRTIM Handle Structure definition.

Enumerations

enum | HAL_HRTIM_StateTypeDef { HAL_HRTIM_STATE_READY = 0x01U, HAL_HRTIM_STATE_BUSY = 0x02U, HAL_HRTIM_STATE_TIMEOUT = 0x06U, HAL_HRTIM_STATE_ERROR = 0x07U }
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_HRTIM_Init (HRTIM_HandleTypeDef *hhrtim)
Initializes a HRTIM instance.
HAL_StatusTypeDef | HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim)
De-initializes a HRTIM instance.
__weak void | HAL_HRTIM_MspInit (HRTIM_HandleTypeDef *hhrtim)
MSP initialization for a HRTIM instance.
__weak void | HAL_HRTIM_MspDeInit (HRTIM_HandleTypeDef *hhrtim)
MSP initialization for a for a HRTIM instance.
HAL_StatusTypeDef | HAL_HRTIM_TimeBaseConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg)
Configures the time base unit of a timer.
HAL_StatusTypeDef | HAL_HRTIM_SimpleBaseStart (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Starts the counter of a timer operating in basic time base mode.
HAL_StatusTypeDef | HAL_HRTIM_SimpleBaseStop (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Stops the counter of a timer operating in basic time base mode.
HAL_StatusTypeDef | HAL_HRTIM_SimpleBaseStart_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Starts the counter of a timer operating in simple time base mode (Timer repetition interrupt is enabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleBaseStop_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Stops the counter of a timer operating in simple time base mode (Timer repetition interrupt is disabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleBaseStart_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t SrcAddr, uint32_t DestAddr, uint32_t Length)
Starts the counter of a timer operating in simple time base mode (Timer repetition DMA request is enabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleBaseStop_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Stops the counter of a timer operating in simple time base mode (Timer repetition DMA request is disabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleOCChannelConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel, HRTIM_SimpleOCChannelCfgTypeDef *pSimpleOCChannelCfg)
Configures an output in simple output compare mode.
HAL_StatusTypeDef | HAL_HRTIM_SimpleOCStart (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel)
Starts the output compare signal generation on the designed timer output.
HAL_StatusTypeDef | HAL_HRTIM_SimpleOCStop (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel)
Stops the output compare signal generation on the designed timer output.
HAL_StatusTypeDef | HAL_HRTIM_SimpleOCStart_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel)
Starts the output compare signal generation on the designed timer output (Interrupt is enabled (see note note below)).
HAL_StatusTypeDef | HAL_HRTIM_SimpleOCStop_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel)
Stops the output compare signal generation on the designed timer output (Interrupt is disabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleOCStart_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel, uint32_t SrcAddr, uint32_t DestAddr, uint32_t Length)
Starts the output compare signal generation on the designed timer output (DMA request is enabled (see note below)).
HAL_StatusTypeDef | HAL_HRTIM_SimpleOCStop_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel)
Stops the output compare signal generation on the designed timer output (DMA request is disabled).
HAL_StatusTypeDef | HAL_HRTIM_SimplePWMChannelConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel, HRTIM_SimplePWMChannelCfgTypeDef *pSimplePWMChannelCfg)
Configures an output in simple PWM mode.
HAL_StatusTypeDef | HAL_HRTIM_SimplePWMStart (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel)
Starts the PWM output signal generation on the designed timer output.
HAL_StatusTypeDef | HAL_HRTIM_SimplePWMStop (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel)
Stops the PWM output signal generation on the designed timer output.
HAL_StatusTypeDef | HAL_HRTIM_SimplePWMStart_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel)
Starts the PWM output signal generation on the designed timer output (The compare interrupt is enabled).
HAL_StatusTypeDef | HAL_HRTIM_SimplePWMStop_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel)
Stops the PWM output signal generation on the designed timer output (The compare interrupt is disabled).
HAL_StatusTypeDef | HAL_HRTIM_SimplePWMStart_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel, uint32_t SrcAddr, uint32_t DestAddr, uint32_t Length)
Starts the PWM output signal generation on the designed timer output (The compare DMA request is enabled).
HAL_StatusTypeDef | HAL_HRTIM_SimplePWMStop_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel)
Stops the PWM output signal generation on the designed timer output (The compare DMA request is disabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleCaptureChannelConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel, HRTIM_SimpleCaptureChannelCfgTypeDef *pSimpleCaptureChannelCfg)
Configures a simple capture.
HAL_StatusTypeDef | HAL_HRTIM_SimpleCaptureStart (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel)
Enables a simple capture on the designed capture unit.
HAL_StatusTypeDef | HAL_HRTIM_SimpleCaptureStop (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel)
Disables a simple capture on the designed capture unit.
HAL_StatusTypeDef | HAL_HRTIM_SimpleCaptureStart_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel)
Enables a basic capture on the designed capture unit (Capture interrupt is enabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleCaptureStop_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel)
Disables a basic capture on the designed capture unit (Capture interrupt is disabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleCaptureStart_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel, uint32_t SrcAddr, uint32_t DestAddr, uint32_t Length)
Enables a basic capture on the designed capture unit (Capture DMA request is enabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleCaptureStop_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel)
Disables a basic capture on the designed capture unit (Capture DMA request is disabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleOnePulseChannelConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel, HRTIM_SimpleOnePulseChannelCfgTypeDef *pSimpleOnePulseChannelCfg)
Configures an output simple one pulse mode.
HAL_StatusTypeDef | HAL_HRTIM_SimpleOnePulseStart (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel)
Enables the simple one pulse signal generation on the designed output.
HAL_StatusTypeDef | HAL_HRTIM_SimpleOnePulseStop (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel)
Disables the simple one pulse signal generation on the designed output.
HAL_StatusTypeDef | HAL_HRTIM_SimpleOnePulseStart_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel)
Enables the simple one pulse signal generation on the designed output (The compare interrupt is enabled (pulse start)).
HAL_StatusTypeDef | HAL_HRTIM_SimpleOnePulseStop_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel)
Disables the simple one pulse signal generation on the designed output (The compare interrupt is disabled).
HAL_StatusTypeDef | HAL_HRTIM_BurstModeConfig (HRTIM_HandleTypeDef *hhrtim, HRTIM_BurstModeCfgTypeDef *pBurstModeCfg)
Configures the burst mode feature of the HRTIM.
HAL_StatusTypeDef | HAL_HRTIM_EventConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t Event, HRTIM_EventCfgTypeDef *pEventCfg)
Configures the conditioning of an external event.
HAL_StatusTypeDef | HAL_HRTIM_EventPrescalerConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler)
Configures the external event conditioning block prescaler.
HAL_StatusTypeDef | HAL_HRTIM_FaultConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t Fault, HRTIM_FaultCfgTypeDef *pFaultCfg)
Configures the conditioning of fault input.
HAL_StatusTypeDef | HAL_HRTIM_FaultPrescalerConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler)
Configures the fault conditioning block prescaler.
void | HAL_HRTIM_FaultModeCtl (HRTIM_HandleTypeDef *hhrtim, uint32_t Faults, uint32_t Enable)
Enables or disables the HRTIMx Fault mode.
HAL_StatusTypeDef | HAL_HRTIM_ADCTriggerConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t ADCTrigger, HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg)
Configures both the ADC trigger register update source and the ADC trigger source.
HAL_StatusTypeDef | HAL_HRTIM_WaveformTimerConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, HRTIM_TimerCfgTypeDef *pTimerCfg)
Configures the general behavior of a timer operating in waveform mode.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCompareConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CompareUnit, HRTIM_CompareCfgTypeDef *pCompareCfg)
Configures the compare unit of a timer operating in waveform mode.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCaptureConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, HRTIM_CaptureCfgTypeDef *pCaptureCfg)
Configures the capture unit of a timer operating in waveform mode.
HAL_StatusTypeDef | HAL_HRTIM_WaveformOutputConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, HRTIM_OutputCfgTypeDef *pOutputCfg)
Configures the output of a timer operating in waveform mode.
HAL_StatusTypeDef | HAL_HRTIM_WaveformSetOutputLevel (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, uint32_t OutputLevel)
Forces the timer output to its active or inactive state.
HAL_StatusTypeDef | HAL_HRTIM_TimerEventFilteringConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event, HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg)
Configures the event filtering capabilities of a timer (blanking, windowing)
HAL_StatusTypeDef | HAL_HRTIM_DeadTimeConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg)
Configures the deadtime insertion feature for a timer.
HAL_StatusTypeDef | HAL_HRTIM_ChopperModeConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg)
Configures the chopper mode feature for a timer.
HAL_StatusTypeDef | HAL_HRTIM_BurstDMAConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t RegistersToUpdate)
Configures the burst DMA controller for a timer.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCounterStart (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Starts the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter start.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCounterStop (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Stops the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter stop.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCounterStart_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Starts the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter start.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCounterStop_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Stops the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter stop.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCounterStart_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Starts the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter start.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCounterStop_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Stops the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter stop.
HAL_StatusTypeDef | HAL_HRTIM_WaveformOutputStart (HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStart)
Enables the generation of the waveform signal on the designated output(s) Outputs can be combined (ORed) to allow for simultaneous output enabling.
HAL_StatusTypeDef | HAL_HRTIM_WaveformOutputStop (HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStop)
Disables the generation of the waveform signal on the designated output(s) Outputs can be combined (ORed) to allow for simultaneous output disabling.
HAL_StatusTypeDef | HAL_HRTIM_BurstModeCtl (HRTIM_HandleTypeDef *hhrtim, uint32_t Enable)
Enables or disables the HRTIM burst mode controller.
HAL_StatusTypeDef | HAL_HRTIM_BurstModeSoftwareTrigger (HRTIM_HandleTypeDef *hhrtim)
Triggers the burst mode operation.
HAL_StatusTypeDef | HAL_HRTIM_SoftwareCapture (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit)
Triggers a software capture on the designed capture unit.
HAL_StatusTypeDef | HAL_HRTIM_SoftwareUpdate (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Triggers the update of the registers of one or several timers.
HAL_StatusTypeDef | HAL_HRTIM_SoftwareReset (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Triggers the reset of one or several timers.
HAL_StatusTypeDef | HAL_HRTIM_BurstDMATransfer (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t BurstBufferAddress, uint32_t BurstBufferLength)
Starts a burst DMA operation to update HRTIM control registers content.
HAL_StatusTypeDef | HAL_HRTIM_UpdateEnable (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Enables the transfer from preload to active registers for one or several timing units (including master timer).
HAL_StatusTypeDef | HAL_HRTIM_UpdateDisable (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Disables the transfer from preload to active registers for one or several timing units (including master timer).
HAL_HRTIM_StateTypeDef | HAL_HRTIM_GetState (HRTIM_HandleTypeDef *hhrtim)
return the HRTIM HAL state
uint32_t | HAL_HRTIM_GetCapturedValue (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit)
Returns actual value of the capture register of the designated capture unit.
uint32_t | HAL_HRTIM_WaveformGetOutputLevel (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output)
Returns actual level (active or inactive) of the designated output.
uint32_t | HAL_HRTIM_WaveformGetOutputState (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output)
Returns actual state (RUN, IDLE, FAULT) of the designated output.
uint32_t | HAL_HRTIM_GetDelayedProtectionStatus (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output)
Returns the level (active or inactive) of the designated output when the delayed protection was triggered.
uint32_t | HAL_HRTIM_GetBurstStatus (HRTIM_HandleTypeDef *hhrtim)
Returns the actual status (active or inactive) of the burst mode controller.
uint32_t | HAL_HRTIM_GetCurrentPushPullStatus (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Indicates on which output the signal is currently active (when the push pull mode is enabled).
uint32_t | HAL_HRTIM_GetIdlePushPullStatus (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Indicates on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered.
void | HAL_HRTIM_IRQHandler (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
This function handles HRTIM interrupt request.
__weak void | HAL_HRTIM_Fault1Callback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a fault 1 interrupt occured.
__weak void | HAL_HRTIM_Fault2Callback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a fault 2 interrupt occured.
__weak void | HAL_HRTIM_Fault3Callback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a fault 3 interrupt occured.
__weak void | HAL_HRTIM_Fault4Callback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a fault 4 interrupt occured.
__weak void | HAL_HRTIM_Fault5Callback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a fault 5 interrupt occured.
__weak void | HAL_HRTIM_SystemFaultCallback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a system fault interrupt occured.
__weak void | HAL_HRTIM_BurstModePeriodCallback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when the end of the burst mode period is reached.
__weak void | HAL_HRTIM_SynchronizationEventCallback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a synchronization input event is received.
__weak void | HAL_HRTIM_RegistersUpdateCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when timer registers are updated.
__weak void | HAL_HRTIM_RepetitionEventCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when timer repetition period has elapsed.
__weak void | HAL_HRTIM_Compare1EventCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer counter matches the value programmed in the compare 1 register.
__weak void | HAL_HRTIM_Compare2EventCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer counter matches the value programmed in the compare 2 register.
__weak void | HAL_HRTIM_Compare3EventCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer counter matches the value programmed in the compare 3 register.
__weak void | HAL_HRTIM_Compare4EventCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer counter matches the value programmed in the compare 4 register.
__weak void | HAL_HRTIM_Capture1EventCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer x capture 1 event occurs.
__weak void | HAL_HRTIM_Capture2EventCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer x capture 2 event occurs.
__weak void | HAL_HRTIM_DelayedProtectionCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the delayed idle or balanced idle mode is entered.
__weak void | HAL_HRTIM_CounterResetCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer x counter reset/roll-over event occurs.
__weak void | HAL_HRTIM_Output1SetCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer x output 1 is set.
__weak void | HAL_HRTIM_Output1ResetCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer x output 1 is reset.
__weak void | HAL_HRTIM_Output2SetCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer x output 2 is set.
__weak void | HAL_HRTIM_Output2ResetCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer x output 2 is reset.
__weak void | HAL_HRTIM_BurstDMATransferCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when a DMA burst transfer is completed.
__weak void | HAL_HRTIM_ErrorCallback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a DMA error occurs.

Detailed Description

Header file of HRTIM HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_hrtim.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_hsem.h File Reference

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Defines | Functions
stm32h7xx_hal_hsem.h File Reference

Header file of HSEM HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))
SemID to mask helper Macro.
#define | __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER0 |= (__SEM_MASK__))
Enables the specified HSEM interrupts.
#define | __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER0 &= ~(__SEM_MASK__))
Disables the specified HSEM interrupts.
#define | __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR0)
Checks whether interrupt has occurred or not for semaphores specified by a mask.
#define | __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR0)
Get the semaphores release status flags.
#define | __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR0 |= (__SEM_MASK__))
Clears the HSEM Interrupt flags.
#define | IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )
#define | IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )
#define | IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
#define | IS_HSEM_MASTERID(__MASTERID__) (((__MASTERID__) == HSEM_CM7_MASTERID))

Functions

HAL_StatusTypeDef | HAL_HSEM_Take (uint32_t SemID, uint32_t ProcessID)
Take a semaphore in 2 Step mode.
HAL_StatusTypeDef | HAL_HSEM_FastTake (uint32_t SemID)
Fast Take a semaphore with 1 Step mode.
uint32_t | HAL_HSEM_IsSemTaken (uint32_t SemID)
Check semaphore state Taken or not.
void | HAL_HSEM_Release (uint32_t SemID, uint32_t ProcessID)
Release a semaphore.
void | HAL_HSEM_ReleaseAll (uint32_t Key, uint32_t MasterID)
Release All semaphore used by a given Master .
void | HAL_HSEM_SetClearKey (uint32_t Key)
Set semaphore Key .
uint32_t | HAL_HSEM_GetClearKey (void)
Get semaphore Key .
void | HAL_HSEM_ActivateNotification (uint32_t SemMask)
Activate Semaphore release Notification for a given Semaphores Mask .
void | HAL_HSEM_DeactivateNotification (uint32_t SemMask)
Deactivate Semaphore release Notification for a given Semaphores Mask .
__weak void | HAL_HSEM_FreeCallback (uint32_t SemMask)
Semaphore Released Callback.
void | HAL_HSEM_IRQHandler (void)
This function handles HSEM interrupt request.

Detailed Description

Header file of HSEM HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_hsem.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_i2c.h File Reference

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stm32h7xx_hal_i2c.h File Reference

Header file of I2C HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_i2c_ex.h"

Go to the source code of this file.

Data Structures

struct | I2C_InitTypeDef
struct | __I2C_HandleTypeDef

Defines

#define | HAL_I2C_ERROR_NONE (0x00000000U)
#define | HAL_I2C_ERROR_BERR (0x00000001U)
#define | HAL_I2C_ERROR_ARLO (0x00000002U)
#define | HAL_I2C_ERROR_AF (0x00000004U)
#define | HAL_I2C_ERROR_OVR (0x00000008U)
#define | HAL_I2C_ERROR_DMA (0x00000010U)
#define | HAL_I2C_ERROR_TIMEOUT (0x00000020U)
#define | HAL_I2C_ERROR_SIZE (0x00000040U)
#define | I2C_NO_OPTION_FRAME (0xFFFF0000U)
#define | I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define | I2C_ADDRESSINGMODE_10BIT (0x00000002U)
#define | I2C_DUALADDRESS_DISABLE (0x00000000U)
#define | I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
#define | I2C_OA2_NOMASK ((uint8_t)0x00U)
#define | I2C_OA2_MASK01 ((uint8_t)0x01U)
#define | I2C_OA2_MASK02 ((uint8_t)0x02U)
#define | I2C_OA2_MASK03 ((uint8_t)0x03U)
#define | I2C_OA2_MASK04 ((uint8_t)0x04U)
#define | I2C_OA2_MASK05 ((uint8_t)0x05U)
#define | I2C_OA2_MASK06 ((uint8_t)0x06U)
#define | I2C_OA2_MASK07 ((uint8_t)0x07U)
#define | I2C_GENERALCALL_DISABLE (0x00000000U)
#define | I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
#define | I2C_NOSTRETCH_DISABLE (0x00000000U)
#define | I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
#define | I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define | I2C_MEMADD_SIZE_16BIT (0x00000002U)
#define | I2C_DIRECTION_TRANSMIT (0x00000000U)
#define | I2C_DIRECTION_RECEIVE (0x00000001U)
#define | I2C_RELOAD_MODE I2C_CR2_RELOAD
#define | I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define | I2C_SOFTEND_MODE (0x00000000U)
#define | I2C_NO_STARTSTOP (0x00000000U)
#define | I2C_GENERATE_STOP I2C_CR2_STOP
#define | I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | I2C_GENERATE_START_WRITE I2C_CR2_START
#define | I2C_IT_ERRI I2C_CR1_ERRIE
#define | I2C_IT_TCI I2C_CR1_TCIE
#define | I2C_IT_STOPI I2C_CR1_STOPIE
#define | I2C_IT_NACKI I2C_CR1_NACKIE
#define | I2C_IT_ADDRI I2C_CR1_ADDRIE
#define | I2C_IT_RXI I2C_CR1_RXIE
#define | I2C_IT_TXI I2C_CR1_TXIE
#define | I2C_FLAG_TXE I2C_ISR_TXE
#define | I2C_FLAG_TXIS I2C_ISR_TXIS
#define | I2C_FLAG_RXNE I2C_ISR_RXNE
#define | I2C_FLAG_ADDR I2C_ISR_ADDR
#define | I2C_FLAG_AF I2C_ISR_NACKF
#define | I2C_FLAG_STOPF I2C_ISR_STOPF
#define | I2C_FLAG_TC I2C_ISR_TC
#define | I2C_FLAG_TCR I2C_ISR_TCR
#define | I2C_FLAG_BERR I2C_ISR_BERR
#define | I2C_FLAG_ARLO I2C_ISR_ARLO
#define | I2C_FLAG_OVR I2C_ISR_OVR
#define | I2C_FLAG_PECERR I2C_ISR_PECERR
#define | I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | I2C_FLAG_ALERT I2C_ISR_ALERT
#define | I2C_FLAG_BUSY I2C_ISR_BUSY
#define | I2C_FLAG_DIR I2C_ISR_DIR
#define | __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
Reset I2C handle state.
#define | __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified I2C interrupt.
#define | __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified I2C interrupt.
#define | __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified I2C interrupt source is enabled or not.
#define | __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
Check whether the specified I2C flag is set or not.
#define | __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified I2C peripheral.
#define | __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified I2C peripheral.
#define | __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge I2C peripheral in Slave mode.
#define | IS_I2C_ADDRESSING_MODE(MODE)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_OWN_ADDRESS2_MASK(MASK)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_MEMADD_SIZE(SIZE)
#define | IS_TRANSFER_MODE(MODE)
#define | IS_TRANSFER_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
#define | I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define | I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
#define | I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define | I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | I2C_GENERATE_START(__ADDMODE__, __ADDRESS__)

Typedefs

typedef struct __I2C_HandleTypeDef | I2C_HandleTypeDef

Enumerations

enum HAL_I2C_StateTypeDef {
HAL_I2C_STATE_RESET = 0x00U, HAL_I2C_STATE_READY = 0x20U, HAL_I2C_STATE_BUSY = 0x24U, HAL_I2C_STATE_BUSY_TX = 0x21U,
HAL_I2C_STATE_BUSY_RX = 0x22U, HAL_I2C_STATE_LISTEN = 0x28U, HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU,
HAL_I2C_STATE_ABORT = 0x60U, HAL_I2C_STATE_TIMEOUT = 0xA0U, HAL_I2C_STATE_ERROR = 0xE0U
}
enum | HAL_I2C_ModeTypeDef { HAL_I2C_MODE_NONE = 0x00U, HAL_I2C_MODE_MASTER = 0x10U, HAL_I2C_MODE_SLAVE = 0x20U, HAL_I2C_MODE_MEM = 0x40U }

Functions

HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master/host I2C process communication with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.
HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

Header file of I2C HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_i2c.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_i2c_ex.h File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_i2c_ex.h File Reference

Header file of I2C HAL Extension module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U)
#define | I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
#define | I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP
#define | I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP
#define | I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP
#define | I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP
#define | I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP
#define | I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP
#define | I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP
#define | I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP
#define | IS_I2C_ANALOG_FILTER(FILTER)
#define | IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_I2C_FASTMODEPLUS(__CONFIG__)

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configure I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configure I2C Digital noise filter.
HAL_StatusTypeDef | HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
Enable I2C wakeup from stop mode.
HAL_StatusTypeDef | HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
Disable I2C wakeup from stop mode.
void | HAL_I2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
void | HAL_I2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.

Detailed Description

Header file of I2C HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_i2c_ex.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_i2s.h File Reference

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  • STM32H7xx_HAL_Driver
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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_i2s.h File Reference

Header file of I2S HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_i2s_ex.h"

Go to the source code of this file.

Data Structures

struct | I2S_InitTypeDef
I2S Init structure definition. More...
struct | __I2S_HandleTypeDef
I2S handle Structure definition. More...

Defines

#define | HAL_I2S_ERROR_NONE (0x00000000U)
#define | HAL_I2S_ERROR_UDR (0x00000001U)
#define | HAL_I2S_ERROR_OVR (0x00000002U)
#define | HAL_I2S_ERROR_FRE (0x00000004U)
#define | HAL_I2S_ERROR_DMA (0x00000008U)
#define | HAL_I2S_ERROR_DMA (0x00000008U)
#define | HAL_I2S_ERROR_TIMEOUT (0x00000010U)
#define | HAL_I2S_ERROR_PRESCALER (0x00000020U)
#define | I2S_MODE_SLAVE_TX (0x00000000U)
#define | I2S_MODE_SLAVE_RX (0x00000002U)
#define | I2S_MODE_MASTER_TX (0x00000004U)
#define | I2S_MODE_MASTER_RX (0x00000006U)
#define | I2S_MODE_SLAVE_FD (0x00000008U)
#define | I2S_MODE_MASTER_FD (0x0000000AU)
#define | I2S_STANDARD_PHILIPS (0x00000000U)
#define | I2S_STANDARD_MSB (0x00000010U)
#define | I2S_STANDARD_LSB (0x00000020U)
#define | I2S_STANDARD_PCM_SHORT (0x00000030U)
#define | I2S_STANDARD_PCM_LONG (0x000000B0U)
#define | I2S_DATAFORMAT_16B (0x00000000U)
#define | I2S_DATAFORMAT_16B_EXTENDED (0x00000400U)
#define | I2S_DATAFORMAT_24B (0x00000500U)
#define | I2S_DATAFORMAT_32B (0x00000600U)
#define | I2S_MCLKOUTPUT_ENABLE SPI_I2SCFGR_MCKOE
#define | I2S_MCLKOUTPUT_DISABLE (0x00000000U)
#define | I2S_AUDIOFREQ_192K (192000U)
#define | I2S_AUDIOFREQ_96K (96000U)
#define | I2S_AUDIOFREQ_48K (48000U)
#define | I2S_AUDIOFREQ_44K (44100U)
#define | I2S_AUDIOFREQ_32K (32000U)
#define | I2S_AUDIOFREQ_22K (22050U)
#define | I2S_AUDIOFREQ_16K (16000U)
#define | I2S_AUDIOFREQ_11K (11025U)
#define | I2S_AUDIOFREQ_8K (8000U)
#define | I2S_AUDIOFREQ_DEFAULT (2U)
#define | I2S_CPOL_LOW (0x00000000U)
#define | I2S_CPOL_HIGH SPI_I2SCFGR_CKPOL
#define | I2S_FIRSTBIT_MSB (0x00000000U)
#define | I2S_FIRSTBIT_LSB SPI_CFG2_LSBFRST
#define | I2S_WS_INVERSION_DISABLE (0x00000000U)
#define | I2S_WS_INVERSION_ENABLE SPI_I2SCFGR_WSINV
#define | I2S_IO_SWAP_DISABLE (0x00000000U)
#define | I2S_IO_SWAP_ENABLE SPI_CFG2_IOSWP
#define | I2S_DATA_24BIT_ALIGNMENT_RIGHT (0x00000000U)
#define | I2S_DATA_24BIT_ALIGNMENT_LEFT SPI_I2SCFGR_DATFMT
#define | I2S_FIFO_THRESHOLD_01DATA (0x00000000U)
#define | I2S_FIFO_THRESHOLD_02DATA (0x00000020U)
#define | I2S_FIFO_THRESHOLD_03DATA (0x00000040U)
#define | I2S_FIFO_THRESHOLD_04DATA (0x00000060U)
#define | I2S_FIFO_THRESHOLD_05DATA (0x00000080U)
#define | I2S_FIFO_THRESHOLD_06DATA (0x000000A0U)
#define | I2S_FIFO_THRESHOLD_07DATA (0x000000C0U)
#define | I2S_FIFO_THRESHOLD_08DATA (0x000000E0U)
#define | I2S_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)
#define | I2S_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
#define | I2S_SLAVE_EXTEND_FRE_DETECTION_DISABLE (0x00000000U)
#define | I2S_SLAVE_EXTEND_FRE_DETECTION_ENABLE SPI_I2SCFGR_FIXCH
#define | I2S_IT_TXE SPI_IER_TXPIE
#define | I2S_IT_RXNE SPI_IER_RXPIE
#define | I2S_IT_ERR (SPI_IER_OVRIE | SPI_IER_UDRIE | SPI_IER_TIFREIE)
#define | I2S_FLAG_TXE SPI_SR_TXP /* I2S status flag: Tx buffer empty flag */
#define | I2S_FLAG_RXNE SPI_SR_RXP /* I2S status flag: Rx buffer not empty flag */
#define | I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag: Underrun flag */
#define | I2S_FLAG_RXWNE SPI_SR_RXWNE /* I2S RxFIFO Word Not Empty */
#define | I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag: Overrun flag */
#define | I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag: TI mode frame format error flag */
#define | __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
Reset I2S handle state.
#define | __HAL_I2S_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Enable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Disable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->IER,(__INTERRUPT__)))
Enable the specified I2S interrupts.
#define | __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->IER,(__INTERRUPT__)))
Disable the specified I2S interrupts.
#define | __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified I2S interrupt source is enabled or disabled.
#define | __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Checks whether the specified I2S flag is set or not.
#define | __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
Clears the I2S UDR pending flag.
#define | __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
Clears the I2S OVR pending flag.
#define | __HAL_I2S_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
Clear the I2S FRE pending flag.
#define | IS_I2S_MODE(MODE)
#define | IS_I2S_FD_MODE(MODE)
#define | IS_I2S_MASTER(MODE)
#define | IS_I2S_TX_MODE(MODE)
#define | IS_I2S_RX_MODE(MODE)
#define | IS_I2S_STANDARD(STANDARD)
#define | IS_I2S_DATA_FORMAT(FORMAT)
#define | IS_I2S_MCLK_OUTPUT(OUTPUT)
#define | IS_I2S_AUDIO_FREQ(FREQ)
#define | IS_I2S_CPOL(CPOL)
#define | IS_I2S_FIRST_BIT(FIRSTBIT)
#define | IS_I2S_WS_INVERSION(WSINV)
#define | IS_I2S_IO_SWAP(IOSWAP)
#define | IS_I2S_DATA_24BIT_ALIGNMENT(ALIGNMENT)
#define | IS_I2S_FIFO_THRESHOLD(FTHLV)
#define | IS_I2S_MASTER_KEEP_IO_STATE(AFCNTR)
#define | IS_I2S_SLAVE_EXTEND_FRE_DETECTION(FIXCH)

Typedefs

typedef struct __I2S_HandleTypeDef | I2S_HandleTypeDef
I2S handle Structure definition.

Enumerations

enum HAL_I2S_StateTypeDef {
HAL_I2S_STATE_RESET = 0x00U, HAL_I2S_STATE_READY = 0x01U, HAL_I2S_STATE_BUSY = 0x02U, HAL_I2S_STATE_BUSY_TX = 0x03U,
HAL_I2S_STATE_BUSY_RX = 0x04U, HAL_I2S_STATE_BUSY_TX_RX = 0x05U, HAL_I2S_STATE_TIMEOUT = 0x06U, HAL_I2S_STATE_ERROR = 0x07U
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s)
DeInitializes the I2S peripheral.
__weak void | HAL_I2S_MspInit (I2S_HandleTypeDef *hi2s)
I2S MSP Init.
__weak void | HAL_I2S_MspDeInit (I2S_HandleTypeDef *hi2s)
I2S MSP DeInit.
HAL_StatusTypeDef | HAL_I2S_Transmit (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Receive (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Transmit_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Receive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
void | HAL_I2S_IRQHandler (I2S_HandleTypeDef *hi2s)
This function handles I2S interrupt request.
HAL_StatusTypeDef | HAL_I2S_Transmit_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_Receive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Stops the audio stream playing from the Media.
__weak void | HAL_I2S_TxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer Half completed callbacks.
__weak void | HAL_I2S_TxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
__weak void | HAL_I2S_RxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer half completed callbacks.
__weak void | HAL_I2S_RxCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
__weak void | HAL_I2S_ErrorCallback (I2S_HandleTypeDef *hi2s)
I2S error callbacks.
HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.

Detailed Description

Header file of I2S HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_i2s.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_i2s_ex.h File Reference

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stm32h7xx_hal_i2s_ex.h File Reference

Header file of I2S HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_I2SEx_TransmitReceive (I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2SEx_TransmitReceive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2SEx_TransmitReceive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
__weak void | HAL_I2SEx_TxRxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx/Rx Transfer half completed callbacks.
__weak void | HAL_I2SEx_TxRxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx/Rx Transfer completed callbacks.

Detailed Description

Header file of I2S HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_i2s_ex.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_irda.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32h7xx_hal_irda.h File Reference

Header file of IRDA HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_irda_ex.h"

Go to the source code of this file.

Data Structures

struct | IRDA_InitTypeDef
IRDA Init Structure definition. More...
struct | IRDA_HandleTypeDef
IRDA handle Structure definition. More...

Defines

#define | IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define | IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
#define | IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
#define | IRDA_PARITY_NONE ((uint32_t)0x00000000)
#define | IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
#define | IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
#define | IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000)
#define | IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
#define | IRDA_STATE_DISABLE ((uint32_t)0x00000000)
#define | IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE)
#define | IRDA_MODE_DISABLE ((uint32_t)0x00000000)
#define | IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN)
#define | IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)
#define | IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
#define | IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000)
#define | IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)
#define | IRDA_DMA_RX_DISABLE ((uint32_t)0x00000000)
#define | IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)
#define | IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ)
#define | IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ)
#define | IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ)
#define | IRDA_FLAG_REACK ((uint32_t)0x00400000)
#define | IRDA_FLAG_TEACK ((uint32_t)0x00200000)
#define | IRDA_FLAG_BUSY ((uint32_t)0x00010000)
#define | IRDA_FLAG_ABRF ((uint32_t)0x00008000)
#define | IRDA_FLAG_ABRE ((uint32_t)0x00004000)
#define | IRDA_FLAG_TXE ((uint32_t)0x00000080)
#define | IRDA_FLAG_TC ((uint32_t)0x00000040)
#define | IRDA_FLAG_RXNE ((uint32_t)0x00000020)
#define | IRDA_FLAG_ORE ((uint32_t)0x00000008)
#define | IRDA_FLAG_NE ((uint32_t)0x00000004)
#define | IRDA_FLAG_FE ((uint32_t)0x00000002)
#define | IRDA_FLAG_PE ((uint32_t)0x00000001)
#define | IRDA_IT_PE ((uint16_t)0x0028)
#define | IRDA_IT_TXE ((uint16_t)0x0727)
#define | IRDA_IT_TC ((uint16_t)0x0626)
#define | IRDA_IT_RXNE ((uint16_t)0x0525)
#define | IRDA_IT_IDLE ((uint16_t)0x0424)
#define | IRDA_IT_ERR ((uint16_t)0x0060)
#define | IRDA_IT_ORE ((uint16_t)0x0300)
#define | IRDA_IT_NE ((uint16_t)0x0200)
#define | IRDA_IT_FE ((uint16_t)0x0100)
#define | IRDA_CLEAR_PEF USART_ICR_PECF
#define | IRDA_CLEAR_FEF USART_ICR_FECF
#define | IRDA_CLEAR_NEF USART_ICR_NCF
#define | IRDA_CLEAR_OREF USART_ICR_ORECF
#define | IRDA_CLEAR_IDLEF USART_ICR_IDLECF
#define | IRDA_CLEAR_TCF USART_ICR_TCCF
#define | IRDA_IT_MASK ((uint16_t)0x001F)
#define | __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)
Reset IRDA handle state.
#define | __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)
Flush the IRDA DR register.
#define | __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified IRDA pending flag.
#define | __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
Clear the IRDA PE pending flag.
#define | __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
Clear the IRDA FE pending flag.
#define | __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
Clear the IRDA NE pending flag.
#define | __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
Clear the IRDA ORE pending flag.
#define | __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
Clear the IRDA IDLE pending flag.
#define | __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified IRDA flag is set or not.
#define | __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified IRDA interrupt.
#define | __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified IRDA interrupt.
#define | __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08)))
Check whether the specified IRDA interrupt has occurred or not.
#define | __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified IRDA interrupt source is enabled or not.
#define | __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
#define | __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific IRDA request flag.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the IRDA one bit sample method.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the IRDA one bit sample method.
#define | __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART/USART associated to IRDA Handle.
#define | __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART/USART associated to IRDA Handle.
#define | IRDA_MASK_COMPUTATION(__HANDLE__)
Compute the mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
Ensure that IRDA Baud rate is less or equal to maximum value.
#define | IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
Ensure that IRDA prescaler value is strictly larger than 0.
#define | IS_IRDA_WORD_LENGTH(__LENGTH__)
Ensure that IRDA frame length is valid.
#define | IS_IRDA_PARITY(__PARITY__)
Ensure that IRDA frame parity is valid.
#define | IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
Ensure that IRDA communication mode is valid.
#define | IS_IRDA_POWERMODE(__MODE__)
Ensure that IRDA power mode is valid.
#define | IS_IRDA_STATE(__STATE__)
Ensure that IRDA state is valid.
#define | IS_IRDA_MODE(__MODE__)
Ensure that IRDA associated UART/USART mode is valid.
#define | IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that IRDA sampling rate is valid.
#define | IS_IRDA_DMA_TX(__DMATX__)
Ensure that IRDA DMA TX mode is valid.
#define | IS_IRDA_DMA_RX(__DMARX__)
Ensure that IRDA DMA RX mode is valid.
#define | IS_IRDA_REQUEST_PARAMETER(__PARAM__)
Ensure that IRDA request is valid.

Enumerations

enum HAL_IRDA_StateTypeDef {
HAL_IRDA_STATE_RESET = 0x00U, HAL_IRDA_STATE_READY = 0x20U, HAL_IRDA_STATE_BUSY = 0x24U, HAL_IRDA_STATE_BUSY_TX = 0x21U,
HAL_IRDA_STATE_BUSY_RX = 0x22U, HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, HAL_IRDA_STATE_TIMEOUT = 0xA0U, HAL_IRDA_STATE_ERROR = 0xE0U
}
HAL IRDA State structures definition. More...
enum HAL_IRDA_ErrorTypeDef {
HAL_IRDA_ERROR_NONE = 0x00, HAL_IRDA_ERROR_PE = 0x01, HAL_IRDA_ERROR_NE = 0x02, HAL_IRDA_ERROR_FE = 0x04,
HAL_IRDA_ERROR_ORE = 0x08, HAL_IRDA_ERROR_DMA = 0x10, HAL_IRDA_ERROR_BUSY = 0x20
}
HAL IRDA Error Code structure definition. More...
enum IRDA_ClockSourceTypeDef {
IRDA_CLOCKSOURCE_D2PCLK1 = 0x00, IRDA_CLOCKSOURCE_D2PCLK2 = 0x01, IRDA_CLOCKSOURCE_D3PCLK1 = 0x02, IRDA_CLOCKSOURCE_PLL2Q = 0x04,
IRDA_CLOCKSOURCE_HSI = 0x08, IRDA_CLOCKSOURCE_CSI = 0x10, IRDA_CLOCKSOURCE_LSE = 0x20, IRDA_CLOCKSOURCE_PLL3Q = 0x40,
IRDA_CLOCKSOURCE_UNDEFINED = 0x80
}
IRDA clock sources definition. More...
enum IRDA_ControlTypeDef {
IRDA_BAUDRATE = 0x00, IRDA_PARITY = 0x01, IRDA_WORDLENGTH = 0x02, IRDA_MODE = 0x03,
IRDA_PRESCALER = 0x04, IRDA_POWERMODE = 0x05
}
IRDA Configuration enumeration values definition. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
Initialize the IRDA MSP.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA MSP.
HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_Abort (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_Abort_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
Handle IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer completed callback.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer completed callback.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callback.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callback.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callback.
__weak void | HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Receive Complete callback.
HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Return the IRDA handle state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IRDA handle error code.

Detailed Description

Header file of IRDA HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_irda.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_irda_ex.h File Reference

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Defines
stm32h7xx_hal_irda_ex.h File Reference

Header file of IRDA HAL Extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Defines

#define IRDA_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the IRDA clock source.

Detailed Description

Header file of IRDA HAL Extended module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_irda_ex.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_iwdg.h File Reference

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stm32h7xx_hal_iwdg.h File Reference

Header file of IWDG HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | IWDG_InitTypeDef
IWDG Init structure definition. More...
struct | IWDG_HandleTypeDef
IWDG Handle Structure definition. More...

Defines

#define | IWDG_PRESCALER_4 0x00000000u
#define | IWDG_PRESCALER_8 IWDG_PR_PR_0
#define | IWDG_PRESCALER_16 IWDG_PR_PR_1
#define | IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_64 IWDG_PR_PR_2
#define | IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)
#define | IWDG_WINDOW_DISABLE IWDG_WINR_WIN
#define | __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
Enable the IWDG peripheral.
#define | __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
Reload IWDG counter with value defined in the reload register (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
#define | IWDG_KEY_RELOAD 0x0000AAAAu
IWDG Key Register BitMask.
#define | IWDG_KEY_ENABLE 0x0000CCCCu
#define | IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u
#define | IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u
#define | IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IS_IWDG_PRESCALER(__PRESCALER__)
Check IWDG prescaler value.
#define | IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
Check IWDG reload value.
#define | IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
Check IWDG window value.

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

Header file of IWDG HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_iwdg.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_jpeg.h File Reference

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stm32h7xx_hal_jpeg.h File Reference

Header file of JPEG HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_mdma.h"

Go to the source code of this file.

Data Structures

struct | JPEG_ConfTypeDef
struct | JPEG_HandleTypeDef

Defines

#define | HAL_JPEG_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_JPEG_ERROR_HUFF_TABLE ((uint32_t)0x00000001U)
#define | HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U)
#define | HAL_JPEG_ERROR_DMA ((uint32_t)0x00000004U)
#define | HAL_JPEG_ERROR_TIMEOUT ((uint32_t)0x00000008U)
#define | JPEG_QUANT_TABLE_SIZE ((uint32_t)64U)
#define | JPEG_GRAYSCALE_COLORSPACE ((uint32_t)0x00000000U)
#define | JPEG_YCBCR_COLORSPACE JPEG_CONFR1_COLORSPACE_0
#define | JPEG_CMYK_COLORSPACE JPEG_CONFR1_COLORSPACE
#define | JPEG_444_SUBSAMPLING ((uint32_t)0x00000000U)
#define | JPEG_420_SUBSAMPLING ((uint32_t)0x00000001U)
#define | JPEG_422_SUBSAMPLING ((uint32_t)0x00000002U)
#define | JPEG_IMAGE_QUALITY_MIN ((uint32_t)1U)
#define | JPEG_IMAGE_QUALITY_MAX ((uint32_t)100U)
#define | JPEG_IT_IFT ((uint32_t)JPEG_CR_IFTIE)
#define | JPEG_IT_IFNF ((uint32_t)JPEG_CR_IFNFIE)
#define | JPEG_IT_OFT ((uint32_t)JPEG_CR_OFTIE)
#define | JPEG_IT_OFNE ((uint32_t)JPEG_CR_OFTIE)
#define | JPEG_IT_EOC ((uint32_t)JPEG_CR_EOCIE)
#define | JPEG_IT_HPD ((uint32_t)JPEG_CR_HPDIE)
#define | JPEG_FLAG_IFTF ((uint32_t)JPEG_SR_IFTF)
#define | JPEG_FLAG_IFNFF ((uint32_t)JPEG_SR_IFNFF)
#define | JPEG_FLAG_OFTF ((uint32_t)JPEG_SR_OFTF)
#define | JPEG_FLAG_OFNEF ((uint32_t)JPEG_SR_OFNEF)
#define | JPEG_FLAG_EOCF ((uint32_t)JPEG_SR_EOCF)
#define | JPEG_FLAG_HPDF ((uint32_t)JPEG_SR_HPDF)
#define | JPEG_FLAG_COF ((uint32_t)JPEG_SR_COF)
#define | JPEG_FLAG_ALL ((uint32_t)0x000000FEU)
#define | JPEG_PAUSE_RESUME_INPUT ((uint32_t)0x00000001U)
#define | JPEG_PAUSE_RESUME_OUTPUT ((uint32_t)0x00000002U)
#define | JPEG_PAUSE_RESUME_INPUT_OUTPUT ((uint32_t)0x00000003U)
#define | __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_JPEG_STATE_RESET)
Reset JPEG handle state.
#define | __HAL_JPEG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= JPEG_CR_JCEN)
Enable the JPEG peripheral.
#define | __HAL_JPEG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~JPEG_CR_JCEN)
Disable the JPEG peripheral.
#define | __HAL_JPEG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)))
Check the specified JPEG status flag.
#define | __HAL_JPEG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->CFR |= ((__FLAG__) & (JPEG_FLAG_EOCF | JPEG_FLAG_HPDF))))
Clear the specified JPEG status flag.
#define | __HAL_JPEG_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) )
Enable Interrupt.
#define | __HAL_JPEG_DISABLE_IT(__HANDLE__, __INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0)
Disable Interrupt.
#define | __HAL_JPEG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
Get Interrupt state.
#define | IS_JPEG_CHROMASUBSAMPLING(SUBSAMPLING)
#define | IS_JPEG_IMAGE_QUALITY(NUMBER) (((NUMBER) >= JPEG_IMAGE_QUALITY_MIN) && ((NUMBER) <= JPEG_IMAGE_QUALITY_MAX))
#define | IS_JPEG_COLORSPACE(COLORSPACE)
#define | IS_JPEG_PAUSE_RESUME_STATE(VALUE)

Enumerations

enum HAL_JPEG_STATETypeDef {
HAL_JPEG_STATE_RESET = 0x00U, HAL_JPEG_STATE_READY = 0x01U, HAL_JPEG_STATE_BUSY = 0x02U, HAL_JPEG_STATE_BUSY_ENCODING = 0x03U,
HAL_JPEG_STATE_BUSY_DECODING = 0x04U, HAL_JPEG_STATE_TIMEOUT = 0x05U, HAL_JPEG_STATE_ERROR = 0x06U
}

Functions

HAL_StatusTypeDef | HAL_JPEG_Init (JPEG_HandleTypeDef *hjpeg)
Initializes the JPEG according to the specified parameters in the JPEG_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_JPEG_DeInit (JPEG_HandleTypeDef *hjpeg)
DeInitializes the JPEG peripheral.
__weak void | HAL_JPEG_MspInit (JPEG_HandleTypeDef *hjpeg)
Initializes the JPEG MSP.
__weak void | HAL_JPEG_MspDeInit (JPEG_HandleTypeDef *hjpeg)
DeInitializes JPEG MSP.
HAL_StatusTypeDef | HAL_JPEG_ConfigEncoding (JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf)
Set the JPEG encoding configuration.
HAL_StatusTypeDef | HAL_JPEG_GetInfo (JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
Extract the image configuration from the JPEG header during the decoding.
HAL_StatusTypeDef | HAL_JPEG_EnableHeaderParsing (JPEG_HandleTypeDef *hjpeg)
Enable JPEG Header parsing for decoding.
HAL_StatusTypeDef | HAL_JPEG_DisableHeaderParsing (JPEG_HandleTypeDef *hjpeg)
Disable JPEG Header parsing for decoding.
HAL_StatusTypeDef | HAL_JPEG_SetUserQuantTables (JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, uint8_t *QTable2, uint8_t *QTable3)
Modify the default Quantization tables used for JPEG encoding.
HAL_StatusTypeDef | HAL_JPEG_Encode (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout)
Starts JPEG encoding with polling processing.
HAL_StatusTypeDef | HAL_JPEG_Decode (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, uint8_t *pDataOutMCU, uint32_t OutDataLength, uint32_t Timeout)
Starts JPEG decoding with polling processing.
HAL_StatusTypeDef | HAL_JPEG_Encode_IT (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)
Starts JPEG encoding with interrupt processing.
HAL_StatusTypeDef | HAL_JPEG_Decode_IT (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, uint8_t *pDataOutMCU, uint32_t OutDataLength)
Starts JPEG decoding with interrupt processing.
HAL_StatusTypeDef | HAL_JPEG_Encode_DMA (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)
Starts JPEG encoding with DMA processing.
HAL_StatusTypeDef | HAL_JPEG_Decode_DMA (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, uint8_t *pDataOutMCU, uint32_t OutDataLength)
Starts JPEG decoding with DMA processing.
HAL_StatusTypeDef | HAL_JPEG_Pause (JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)
Pause the JPEG Input/Output processing.
HAL_StatusTypeDef | HAL_JPEG_Resume (JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)
Resume the JPEG Input/Output processing.
void | HAL_JPEG_ConfigInputBuffer (JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength)
Config Encoding/Decoding Input Buffer.
void | HAL_JPEG_ConfigOutputBuffer (JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength)
Config Encoding/Decoding Output Buffer.
HAL_StatusTypeDef | HAL_JPEG_Abort (JPEG_HandleTypeDef *hjpeg)
Aborts the JPEG Encoding/Decoding.
__weak void | HAL_JPEG_InfoReadyCallback (JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
Decoding JPEG Info ready callback.
__weak void | HAL_JPEG_EncodeCpltCallback (JPEG_HandleTypeDef *hjpeg)
Encoding complete callback.
__weak void | HAL_JPEG_DecodeCpltCallback (JPEG_HandleTypeDef *hjpeg)
Decoding complete callback.
__weak void | HAL_JPEG_ErrorCallback (JPEG_HandleTypeDef *hjpeg)
JPEG error callback.
__weak void | HAL_JPEG_GetDataCallback (JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData)
Get New Data chunk callback.
__weak void | HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength)
Decoded/Encoded Data ready callback.
void | HAL_JPEG_IRQHandler (JPEG_HandleTypeDef *hjpeg)
This function handles JPEG interrupt request.
HAL_JPEG_STATETypeDef | HAL_JPEG_GetState (JPEG_HandleTypeDef *hjpeg)
Returns the JPEG state.
uint32_t | HAL_JPEG_GetError (JPEG_HandleTypeDef *hjpeg)
Return the JPEG error code.

Detailed Description

Header file of JPEG HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_jpeg.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_lptim.h File Reference

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stm32h7xx_hal_lptim.h File Reference

Header file of LPTIM HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | LPTIM_ClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_ULPClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_TriggerConfigTypeDef
LPTIM Trigger configuration definition. More...
struct | LPTIM_InitTypeDef
LPTIM Initialization Structure definition. More...
struct | LPTIM_HandleTypeDef
LPTIM handle Structure definition. More...

Defines

#define | LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00U)
#define | LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
#define | LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000U)
#define | LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
#define | LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
#define | LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
#define | LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC)
#define | LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U)
#define | LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)
#define | LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
#define | LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define | LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define | LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
#define | LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000U)
#define | LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
#define | LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFFU)
#define | LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000U)
#define | LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
#define | LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define | LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define | LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
#define | LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_6 ((uint32_t)LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL
#define | LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
#define | LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
#define | LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
#define | LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
#define | LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define | LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define | LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
#define | LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000U)
#define | LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
#define | LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000U)
#define | LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
#define | LPTIM_INPUT1SOURCE_GPIO ((uint32_t)0x00000000U)
#define | LPTIM_INPUT1SOURCE_COMP1 LPTIM_CFGR2_IN1_SEL0
#define | LPTIM_INPUT1SOURCE_COMP2 LPTIM_CFGR2_IN1_SEL1
#define | LPTIM_INPUT1SOURCE_COMP1_COMP2 (LPTIM_CFGR2_IN1_SEL0|LPTIM_CFGR2_IN1_SEL1)
#define | LPTIM_INPUT1SOURCE_SAI1_FSA LPTIM_CFGR2_IN1_SEL0
#define | LPTIM_INPUT1SOURCE_SAI1_FSB LPTIM_CFGR2_IN1_SEL1
#define | LPTIM_INPUT2SOURCE_GPIO ((uint32_t)0x00000000U)
#define | LPTIM_INPUT2SOURCE_COMP2 LPTIM_CFGR2_IN2_SEL0
#define | LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
#define | LPTIM_FLAG_UP LPTIM_ISR_UP
#define | LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
#define | LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
#define | LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
#define | LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
#define | LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define | LPTIM_IT_UP LPTIM_IER_UPIE
#define | LPTIM_IT_ARROK LPTIM_IER_ARROKIE
#define | LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
#define | LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
#define | LPTIM_IT_ARRM LPTIM_IER_ARRMIE
#define | LPTIM_IT_CMPM LPTIM_IER_CMPMIE
#define | __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
Reset LPTIM handle state.
#define | __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
Enable the LPTIM peripheral.
#define | __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))
Disable the LPTIM peripheral.
#define | __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
Start the LPTIM peripheral in Continuous mode.
#define | __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
Start the LPTIM peripheral in single mode.
#define | __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)
Reset the LPTIM Counter register in synchronous mode.
#define | __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)
Reset after read of the LPTIM Counter register in asynchronous mode.
#define | __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
Write the passed parameter in the Autoreload register.
#define | __HAL_LPTIM_COMPARE_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
Write the passed parameter in the Compare register.
#define | __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
Check whether the specified LPTIM flag is set or not.
#define | __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified LPTIM flag.
#define | __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified LPTIM interrupt.
#define | __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified LPTIM interrupt.
#define | __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified LPTIM interrupt is set or not.
#define | IS_LPTIM_CLOCK_SOURCE(__SOURCE__)
#define | IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__)
#define | IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
#define | IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_CLOCK_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRG_SOURCE(__TRIG__)
#define | IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_UPDATE_MODE(__MODE__)
#define | IS_LPTIM_COUNTER_SOURCE(__SOURCE__)
#define | IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFF)
#define | IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFF)
#define | IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFF)
#define | IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFF)
#define | IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)
#define | IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)

Typedefs

typedef enum
__HAL_LPTIM_StateTypeDef 		HAL_LPTIM_StateTypeDef
HAL LPTIM State structure definition.

Enumerations

enum __HAL_LPTIM_StateTypeDef {
HAL_LPTIM_STATE_RESET = 0x00U, HAL_LPTIM_STATE_READY = 0x01U, HAL_LPTIM_STATE_BUSY = 0x02U, HAL_LPTIM_STATE_TIMEOUT = 0x03U,
HAL_LPTIM_STATE_ERROR = 0x04U
}
HAL LPTIM State structure definition. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize the LPTIM peripheral.
void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM MSP.
void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize LPTIM MSP.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface in nterrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode in interrupt mode.
uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
Return the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
Return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
Return the current Compare (Pulse) value.
void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
Handle LPTIM interrupt request.
void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non-blocking mode.
void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non-blocking mode.
void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non-blocking mode.
void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non-blocking mode.
void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non-blocking mode.
void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non-blocking mode.
void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non-blocking mode.
HAL_LPTIM_StateTypeDef | HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Returns the LPTIM state.

Detailed Description

Header file of LPTIM HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_lptim.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_ltdc.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32h7xx_hal_ltdc.h File Reference

Header file of LTDC HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | LTDC_ColorTypeDef
LTDC color structure definition. More...
struct | LTDC_InitTypeDef
LTDC Init structure definition. More...
struct | LTDC_LayerCfgTypeDef
LTDC Layer structure definition. More...
struct | LTDC_HandleTypeDef
LTDC handle Structure definition. More...

Defines

#define | MAX_LAYER 2U
#define | HAL_LTDC_ERROR_NONE (0x00000000U)
#define | HAL_LTDC_ERROR_TE (0x00000001U)
#define | HAL_LTDC_ERROR_FU (0x00000002U)
#define | HAL_LTDC_ERROR_TIMEOUT (0x00000020U)
#define | LTDC_LAYER_1 (0x00000000U)
#define | LTDC_LAYER_2 (0x00000001U)
#define | LTDC_HSPOLARITY_AL (0x00000000U)
#define | LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL
#define | LTDC_VSPOLARITY_AL (0x00000000U)
#define | LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL
#define | LTDC_DEPOLARITY_AL (0x00000000U)
#define | LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL
#define | LTDC_PCPOLARITY_IPC (0x00000000U)
#define | LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL
#define | LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16)
#define | LTDC_VERTICALSYNC LTDC_SSCR_VSH
#define | LTDC_COLOR (0x000000FFU)
#define | LTDC_BLENDING_FACTOR1_CA (0x00000400U)
#define | LTDC_BLENDING_FACTOR1_PAxCA (0x00000600U)
#define | LTDC_BLENDING_FACTOR2_CA (0x00000005U)
#define | LTDC_BLENDING_FACTOR2_PAxCA (0x00000007U)
#define | LTDC_PIXEL_FORMAT_ARGB8888 (0x00000000U)
#define | LTDC_PIXEL_FORMAT_RGB888 (0x00000001U)
#define | LTDC_PIXEL_FORMAT_RGB565 (0x00000002U)
#define | LTDC_PIXEL_FORMAT_ARGB1555 (0x00000003U)
#define | LTDC_PIXEL_FORMAT_ARGB4444 (0x00000004U)
#define | LTDC_PIXEL_FORMAT_L8 (0x00000005U)
#define | LTDC_PIXEL_FORMAT_AL44 (0x00000006U)
#define | LTDC_PIXEL_FORMAT_AL88 (0x00000007U)
#define | LTDC_ALPHA LTDC_LxCACR_CONSTA
#define | LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16)
#define | LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS
#define | LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL
#define | LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR
#define | LTDC_IT_LI LTDC_IER_LIE
#define | LTDC_IT_FU LTDC_IER_FUIE
#define | LTDC_IT_TE LTDC_IER_TERRIE
#define | LTDC_IT_RR LTDC_IER_RRIE
#define | LTDC_FLAG_LI LTDC_ISR_LIF
#define | LTDC_FLAG_FU LTDC_ISR_FUIF
#define | LTDC_FLAG_TE LTDC_ISR_TERRIF
#define | LTDC_FLAG_RR LTDC_ISR_RRIF
#define | LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR
#define | LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR
#define | __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
Reset LTDC handle state.
#define | __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
Enable the LTDC.
#define | __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
Disable the LTDC.
#define | __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
Enable the LTDC Layer.
#define | __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
Disable the LTDC Layer.
#define | __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
Reload immediately all LTDC Layers.
#define | __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR)
Reload during vertical blanking period all LTDC Layers.
#define | __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
Get the LTDC pending flags.
#define | __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clears the LTDC pending flags.
#define | __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enables the specified LTDC interrupts.
#define | __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
Disables the specified LTDC interrupts.
#define | __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
Checks whether the specified LTDC interrupt has occurred or not.
#define | LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__)))))
#define | IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER)
#define | IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
#define | IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
#define | IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH))
#define | IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC))
#define | IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC)
#define | IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC)
#define | IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC)
#define | IS_LTDC_AVBP(__AVBP__) ((__AVBP__) <= LTDC_VERTICALSYNC)
#define | IS_LTDC_AAW(__AAW__) ((__AAW__) <= LTDC_HORIZONTALSYNC)
#define | IS_LTDC_AAH(__AAH__) ((__AAH__) <= LTDC_VERTICALSYNC)
#define | IS_LTDC_TOTALW(__TOTALW__) ((__TOTALW__) <= LTDC_HORIZONTALSYNC)
#define | IS_LTDC_TOTALH(__TOTALH__) ((__TOTALH__) <= LTDC_VERTICALSYNC)
#define | IS_LTDC_BLUEVALUE(__BBLUE__) ((__BBLUE__) <= LTDC_COLOR)
#define | IS_LTDC_GREENVALUE(__BGREEN__) ((__BGREEN__) <= LTDC_COLOR)
#define | IS_LTDC_REDVALUE(__BRED__) ((__BRED__) <= LTDC_COLOR)
#define | IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__)
#define | IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR2__)
#define | IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__)
#define | IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA)
#define | IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION)
#define | IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION)
#define | IS_LTDC_VCONFIGST(__VCONFIGST__) ((__VCONFIGST__) <= LTDC_STARTPOSITION)
#define | IS_LTDC_VCONFIGSP(__VCONFIGSP__) ((__VCONFIGSP__) <= LTDC_STOPPOSITION)
#define | IS_LTDC_CFBP(__CFBP__) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER)
#define | IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)
#define | IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER)
#define | IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU)
#define | IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))

Enumerations

enum HAL_LTDC_StateTypeDef {
HAL_LTDC_STATE_RESET = 0x00U, HAL_LTDC_STATE_READY = 0x01U, HAL_LTDC_STATE_BUSY = 0x02U, HAL_LTDC_STATE_TIMEOUT = 0x03U,
HAL_LTDC_STATE_ERROR = 0x04U
}
HAL LTDC State enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_LTDC_Init (LTDC_HandleTypeDef *hltdc)
Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef.
HAL_StatusTypeDef | HAL_LTDC_DeInit (LTDC_HandleTypeDef *hltdc)
De-initialize the LTDC peripheral.
__weak void | HAL_LTDC_MspInit (LTDC_HandleTypeDef *hltdc)
Initialize the LTDC MSP.
__weak void | HAL_LTDC_MspDeInit (LTDC_HandleTypeDef *hltdc)
De-initialize the LTDC MSP.
void | HAL_LTDC_ErrorCallback (LTDC_HandleTypeDef *hltdc)
Error LTDC callback.
void | HAL_LTDC_LineEventCallback (LTDC_HandleTypeDef *hltdc)
Line Event callback.
void | HAL_LTDC_ReloadEventCallback (LTDC_HandleTypeDef *hltdc)
Reload Event callback.
void | HAL_LTDC_IRQHandler (LTDC_HandleTypeDef *hltdc)
Handle LTDC interrupt request.
HAL_StatusTypeDef | HAL_LTDC_ConfigLayer (LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
Configure the LTDC Layer according to the specified parameters in the LTDC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_LTDC_SetWindowSize (LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
Set the LTDC window size.
HAL_StatusTypeDef | HAL_LTDC_SetWindowPosition (LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
Set the LTDC window position.
HAL_StatusTypeDef | HAL_LTDC_SetPixelFormat (LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
Reconfigure the pixel format.
HAL_StatusTypeDef | HAL_LTDC_SetAlpha (LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
Reconfigure the layer alpha value.
HAL_StatusTypeDef | HAL_LTDC_SetAddress (LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
Reconfigure the frame buffer Address.
HAL_StatusTypeDef | HAL_LTDC_SetPitch (LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is larger than the one intended to be displayed on screen.
HAL_StatusTypeDef | HAL_LTDC_ConfigColorKeying (LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
Configure the color keying.
HAL_StatusTypeDef | HAL_LTDC_ConfigCLUT (LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)
Load the color lookup table.
HAL_StatusTypeDef | HAL_LTDC_EnableColorKeying (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color keying.
HAL_StatusTypeDef | HAL_LTDC_DisableColorKeying (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color keying.
HAL_StatusTypeDef | HAL_LTDC_EnableCLUT (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color lookup table.
HAL_StatusTypeDef | HAL_LTDC_DisableCLUT (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color lookup table.
HAL_StatusTypeDef | HAL_LTDC_ProgramLineEvent (LTDC_HandleTypeDef *hltdc, uint32_t Line)
Define the position of the line interrupt.
HAL_StatusTypeDef | HAL_LTDC_EnableDither (LTDC_HandleTypeDef *hltdc)
Enable Dither.
HAL_StatusTypeDef | HAL_LTDC_DisableDither (LTDC_HandleTypeDef *hltdc)
Disable Dither.
HAL_StatusTypeDef | HAL_LTDC_Reload (LTDC_HandleTypeDef *hltdc, uint32_t ReloadType)
Reload LTDC Layers configuration.
HAL_StatusTypeDef | HAL_LTDC_ConfigLayer_NoReload (LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
Configure the LTDC Layer according to the specified without reloading parameters in the LTDC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_LTDC_SetWindowSize_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
Set the LTDC window size without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetWindowPosition_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
Set the LTDC window position without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetPixelFormat_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
Reconfigure the pixel format without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetAlpha_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
Reconfigure the layer alpha value without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetAddress_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
Reconfigure the frame buffer Address without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetPitch_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is larger than the one intended to be displayed on screen.
HAL_StatusTypeDef | HAL_LTDC_ConfigColorKeying_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
Configure the color keying without reloading.
HAL_StatusTypeDef | HAL_LTDC_EnableColorKeying_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color keying without reloading.
HAL_StatusTypeDef | HAL_LTDC_DisableColorKeying_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color keying without reloading.
HAL_StatusTypeDef | HAL_LTDC_EnableCLUT_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color lookup table without reloading.
HAL_StatusTypeDef | HAL_LTDC_DisableCLUT_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color lookup table without reloading.
HAL_LTDC_StateTypeDef | HAL_LTDC_GetState (LTDC_HandleTypeDef *hltdc)
Return the LTDC handle state.
uint32_t | HAL_LTDC_GetError (LTDC_HandleTypeDef *hltdc)
Return the LTDC handle error code.

Detailed Description

Header file of LTDC HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_ltdc.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_mdios.h File Reference

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stm32h7xx_hal_mdios.h File Reference

Header file of MDIOS HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | MDIOS_InitTypeDef
struct | MDIOS_HandleTypeDef

Defines

#define | MDIOS_PREAMBLE_CHECK_ENABLE ((uint32_t)0x00000000U)
#define | MDIOS_PREAMBLE_CHECK_DISABLE MDIOS_CR_DPC
#define | MDIOS_REG0 ((uint32_t)0x00000000U)
#define | MDIOS_REG1 ((uint32_t)0x00000001U)
#define | MDIOS_REG2 ((uint32_t)0x00000002U)
#define | MDIOS_REG3 ((uint32_t)0x00000003U)
#define | MDIOS_REG4 ((uint32_t)0x00000004U)
#define | MDIOS_REG5 ((uint32_t)0x00000005U)
#define | MDIOS_REG6 ((uint32_t)0x00000006U)
#define | MDIOS_REG7 ((uint32_t)0x00000007U)
#define | MDIOS_REG8 ((uint32_t)0x00000008U)
#define | MDIOS_REG9 ((uint32_t)0x00000009U)
#define | MDIOS_REG10 ((uint32_t)0x0000000AU)
#define | MDIOS_REG11 ((uint32_t)0x0000000BU)
#define | MDIOS_REG12 ((uint32_t)0x0000000CU)
#define | MDIOS_REG13 ((uint32_t)0x0000000DU)
#define | MDIOS_REG14 ((uint32_t)0x0000000EU)
#define | MDIOS_REG15 ((uint32_t)0x0000000FU)
#define | MDIOS_REG16 ((uint32_t)0x00000010U)
#define | MDIOS_REG17 ((uint32_t)0x00000011U)
#define | MDIOS_REG18 ((uint32_t)0x00000012U)
#define | MDIOS_REG19 ((uint32_t)0x00000013U)
#define | MDIOS_REG20 ((uint32_t)0x00000014U)
#define | MDIOS_REG21 ((uint32_t)0x00000015U)
#define | MDIOS_REG22 ((uint32_t)0x00000016U)
#define | MDIOS_REG23 ((uint32_t)0x00000017U)
#define | MDIOS_REG24 ((uint32_t)0x00000018U)
#define | MDIOS_REG25 ((uint32_t)0x00000019U)
#define | MDIOS_REG26 ((uint32_t)0x0000001AU)
#define | MDIOS_REG27 ((uint32_t)0x0000001BU)
#define | MDIOS_REG28 ((uint32_t)0x0000001CU)
#define | MDIOS_REG29 ((uint32_t)0x0000001DU)
#define | MDIOS_REG30 ((uint32_t)0x0000001EU)
#define | MDIOS_REG31 ((uint32_t)0x0000001FU)
#define | MDIOS_REG0_FLAG ((uint32_t)0x00000001U)
#define | MDIOS_REG1_FLAG ((uint32_t)0x00000002U)
#define | MDIOS_REG2_FLAG ((uint32_t)0x00000004U)
#define | MDIOS_REG3_FLAG ((uint32_t)0x00000008U)
#define | MDIOS_REG4_FLAG ((uint32_t)0x00000010U)
#define | MDIOS_REG5_FLAG ((uint32_t)0x00000020U)
#define | MDIOS_REG6_FLAG ((uint32_t)0x00000040U)
#define | MDIOS_REG7_FLAG ((uint32_t)0x00000080U)
#define | MDIOS_REG8_FLAG ((uint32_t)0x00000100U)
#define | MDIOS_REG9_FLAG ((uint32_t)0x00000200U)
#define | MDIOS_REG10_FLAG ((uint32_t)0x00000400U)
#define | MDIOS_REG11_FLAG ((uint32_t)0x00000800U)
#define | MDIOS_REG12_FLAG ((uint32_t)0x00001000U)
#define | MDIOS_REG13_FLAG ((uint32_t)0x00002000U)
#define | MDIOS_REG14_FLAG ((uint32_t)0x00004000U)
#define | MDIOS_REG15_FLAG ((uint32_t)0x00008000U)
#define | MDIOS_REG16_FLAG ((uint32_t)0x00010000U)
#define | MDIOS_REG17_FLAG ((uint32_t)0x00020000U)
#define | MDIOS_REG18_FLAG ((uint32_t)0x00040000U)
#define | MDIOS_REG19_FLAG ((uint32_t)0x00080000U)
#define | MDIOS_REG20_FLAG ((uint32_t)0x00100000U)
#define | MDIOS_REG21_FLAG ((uint32_t)0x00200000U)
#define | MDIOS_REG22_FLAG ((uint32_t)0x00400000U)
#define | MDIOS_REG23_FLAG ((uint32_t)0x00800000U)
#define | MDIOS_REG24_FLAG ((uint32_t)0x01000000U)
#define | MDIOS_REG25_FLAG ((uint32_t)0x02000000U)
#define | MDIOS_REG26_FLAG ((uint32_t)0x04000000U)
#define | MDIOS_REG27_FLAG ((uint32_t)0x08000000U)
#define | MDIOS_REG28_FLAG ((uint32_t)0x10000000U)
#define | MDIOS_REG29_FLAG ((uint32_t)0x20000000U)
#define | MDIOS_REG30_FLAG ((uint32_t)0x40000000U)
#define | MDIOS_REG31_FLAG ((uint32_t)0x80000000U)
#define | MDIOS_ALLREG_FLAG ((uint32_t)0xFFFFFFFFU)
#define | MDIOS_IT_WRITE MDIOS_CR_WRIE
#define | MDIOS_IT_READ MDIOS_CR_RDIE
#define | MDIOS_IT_ERROR MDIOS_CR_EIE
#define | MDIOS_TURNAROUND_ERROR_FLAG MDIOS_SR_TERF
#define | MDIOS_START_ERROR_FLAG MDIOS_SR_SERF
#define | MDIOS_PREAMBLE_ERROR_FLAG MDIOS_SR_PERF
#define | MDIOS_WAKEUP_EXTI_LINE ((uint32_t)0x00000400) /* !< 42 - 32 = 10 */
#define | __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDIOS_STATE_RESET)
Reset MDIOS handle state.
#define | __HAL_MDIOS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN)
Enable/Disable the MDIOS peripheral.
#define | __HAL_MDIOS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~MDIOS_CR_EN)
#define | __HAL_MDIOS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the MDIOS device interrupt.
#define | __HAL_MDIOS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the MDIOS device interrupt.
#define | __HAL_MDIOS_GET_WRITE_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WRFR & (__FLAG__))
Set MDIOS slave get write register flag.
#define | __HAL_MDIOS_GET_READ_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RDFR & (__FLAG__))
MDIOS slave get read register flag.
#define | __HAL_MDIOS_GET_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__))
MDIOS slave get interrupt.
#define | __HAL_MDIOS_CLEAR_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR) |= (__FLAG__)
MDIOS slave clear interrupt.
#define | __HAL_MDIOS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
Checks whether the specified MDIOS interrupt is set or not.
#define | __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI_D1->IMR2 |= (__EXTI_LINE__))
Enable the MDIOS WAKEUP Exti Line.
#define | __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR2 & (__EXTI_LINE__))
checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not.
#define | __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR2 = (__EXTI_LINE__))
Clear the MDIOS WAKEUP Exti flag.
#define | __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__)
enable rising edge interrupt on selected EXTI line.
#define | __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__)
enable falling edge interrupt on selected EXTI line.
#define | __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__)
enable falling edge interrupt on selected EXTI line.
#define | __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER2 |= (__EXTI_LINE__))
Generates a Software interrupt on selected EXTI line.
#define | IS_MDIOS_PORTADDRESS(__ADDR__) ((__ADDR__) < 32)
#define | IS_MDIOS_REGISTER(__REGISTER__) ((__REGISTER__) < 32)
#define | IS_MDIOS_PREAMBLECHECK(__PREAMBLECHECK__)

Enumerations

enum | HAL_MDIOS_StateTypeDef { HAL_MDIOS_STATE_RESET = 0x00U, HAL_MDIOS_STATE_READY = 0x01U, HAL_MDIOS_STATE_BUSY = 0x02U, HAL_MDIOS_STATE_ERROR = 0x04U }

Functions

HAL_StatusTypeDef | HAL_MDIOS_Init (MDIOS_HandleTypeDef *hmdios)
Initializes the MDIOS according to the specified parameters in the MDIOS_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_MDIOS_DeInit (MDIOS_HandleTypeDef *hmdios)
DeInitializes the MDIOS peripheral.
__weak void | HAL_MDIOS_MspInit (MDIOS_HandleTypeDef *hmdios)
MDIOS MSP Init.
__weak void | HAL_MDIOS_MspDeInit (MDIOS_HandleTypeDef *hmdios)
MDIOS MSP DeInit.
HAL_StatusTypeDef | HAL_MDIOS_WriteReg (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data)
Writes to an MDIOS output register.
HAL_StatusTypeDef | HAL_MDIOS_ReadReg (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData)
Reads an MDIOS input register.
uint32_t | HAL_MDIOS_GetWrittenRegAddress (MDIOS_HandleTypeDef *hmdios)
Gets Written registers by MDIO master.
uint32_t | HAL_MDIOS_GetReadRegAddress (MDIOS_HandleTypeDef *hmdios)
Gets Read registers by MDIO master.
HAL_StatusTypeDef | HAL_MDIOS_ClearWriteRegAddress (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
Clears Write registers flag.
HAL_StatusTypeDef | HAL_MDIOS_ClearReadRegAddress (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
Clears Read register flag.
HAL_StatusTypeDef | HAL_MDIOS_EnableEvents (MDIOS_HandleTypeDef *hmdios)
Enables Events for MDIOS peripheral.
void | HAL_MDIOS_IRQHandler (MDIOS_HandleTypeDef *hmdios)
This function handles MDIOS interrupt request.
__weak void | HAL_MDIOS_WriteCpltCallback (MDIOS_HandleTypeDef *hmdios)
Write Complete Callback.
__weak void | HAL_MDIOS_ReadCpltCallback (MDIOS_HandleTypeDef *hmdios)
Read Complete Callback.
__weak void | HAL_MDIOS_ErrorCallback (MDIOS_HandleTypeDef *hmdios)
Error Callback.
__weak void | HAL_MDIOS_WakeUpCallback (MDIOS_HandleTypeDef *hmdios)
MDIOS WAKEUP interrupt callback.
uint32_t | HAL_MDIOS_GetError (MDIOS_HandleTypeDef *hmdios)
Gets MDIOS error flags.
HAL_MDIOS_StateTypeDef | HAL_MDIOS_GetState (MDIOS_HandleTypeDef *hmdios)
Return the MDIOS HAL state.

Detailed Description

Header file of MDIOS HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_mdios.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_mdma.h File Reference

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stm32h7xx_hal_mdma.h File Reference

Header file of DMA HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | MDMA_InitTypeDef
MDMA Configuration Structure definition. More...
struct | MDMA_LinkNodeTypeDef
HAL MDMA linked list node structure definition. More...
struct | MDMA_LinkNodeConfTypeDef
HAL MDMA linked list node configuration structure definition. More...
struct | __MDMA_HandleTypeDef
MDMA handle Structure definition. More...

Defines

#define | HAL_MDMA_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_MDMA_ERROR_READ_XFER ((uint32_t)0x00000001U)
#define | HAL_MDMA_ERROR_WRITE_XFER ((uint32_t)0x00000002U)
#define | HAL_MDMA_ERROR_MASK_DATA ((uint32_t)0x00000004U)
#define | HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U)
#define | HAL_MDMA_ERROR_ALIGNMENT ((uint32_t)0x00000010U)
#define | HAL_MDMA_ERROR_BLOCK_SIZE ((uint32_t)0x00000020U)
#define | HAL_MDMA_ERROR_TIMEOUT ((uint32_t)0x00000040U)
#define | HAL_MDMA_ERROR_NO_XFER ((uint32_t)0x00000080U)
#define | HAL_MDMA_ERROR_BUSY ((uint32_t)0x00000100U)
#define | MDMA_REQUEST_DMA1_Stream0_TC ((uint32_t)0x00000000U)
#define | MDMA_REQUEST_DMA1_Stream1_TC ((uint32_t)0x00000001U)
#define | MDMA_REQUEST_DMA1_Stream2_TC ((uint32_t)0x00000002U)
#define | MDMA_REQUEST_DMA1_Stream3_TC ((uint32_t)0x00000003U)
#define | MDMA_REQUEST_DMA1_Stream4_TC ((uint32_t)0x00000004U)
#define | MDMA_REQUEST_DMA1_Stream5_TC ((uint32_t)0x00000005U)
#define | MDMA_REQUEST_DMA1_Stream6_TC ((uint32_t)0x00000006U)
#define | MDMA_REQUEST_DMA1_Stream7_TC ((uint32_t)0x00000007U)
#define | MDMA_REQUEST_DMA2_Stream0_TC ((uint32_t)0x00000008U)
#define | MDMA_REQUEST_DMA2_Stream1_TC ((uint32_t)0x00000009U)
#define | MDMA_REQUEST_DMA2_Stream2_TC ((uint32_t)0x0000000AU)
#define | MDMA_REQUEST_DMA2_Stream3_TC ((uint32_t)0x0000000BU)
#define | MDMA_REQUEST_DMA2_Stream4_TC ((uint32_t)0x0000000CU)
#define | MDMA_REQUEST_DMA2_Stream5_TC ((uint32_t)0x0000000DU)
#define | MDMA_REQUEST_DMA2_Stream6_TC ((uint32_t)0x0000000EU)
#define | MDMA_REQUEST_DMA2_Stream7_TC ((uint32_t)0x0000000FU)
#define | MDMA_REQUEST_LTDC_LINE_IT ((uint32_t)0x00000010U)
#define | MDMA_REQUEST_JPEG_INFIFO_TH ((uint32_t)0x00000011U)
#define | MDMA_REQUEST_JPEG_INFIFO_NF ((uint32_t)0x00000012U)
#define | MDMA_REQUEST_JPEG_OUTFIFO_TH ((uint32_t)0x00000013U)
#define | MDMA_REQUEST_JPEG_OUTFIFO_NE ((uint32_t)0x00000014U)
#define | MDMA_REQUEST_JPEG_END_CONVERSION ((uint32_t)0x00000015U)
#define | MDMA_REQUEST_QUADSPI_FIFO_TH ((uint32_t)0x00000016U)
#define | MDMA_REQUEST_QUADSPI_TC ((uint32_t)0x00000017U)
#define | MDMA_REQUEST_DMA2D_CLUT_TC ((uint32_t)0x00000018U)
#define | MDMA_REQUEST_DMA2D_TC ((uint32_t)0x00000019U)
#define | MDMA_REQUEST_DMA2D_TW ((uint32_t)0x0000001AU)
#define | MDMA_REQUEST_SDMMC1_END_DATA ((uint32_t)0x0000001DU)
#define | MDMA_REQUEST_SW ((uint32_t)0x40000000U)
#define | MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U)
#define | MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0)
#define | MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1)
#define | MDMA_FULL_TRANSFER ((uint32_t)MDMA_CTCR_TRGM)
#define | MDMA_PRIORITY_LOW ((uint32_t)0x00000000U)
#define | MDMA_PRIORITY_MEDIUM ((uint32_t)MDMA_CCR_PL_0)
#define | MDMA_PRIORITY_HIGH ((uint32_t)MDMA_CCR_PL_1)
#define | MDMA_PRIORITY_VERY_HIGH ((uint32_t)MDMA_CCR_PL)
#define | MDMA_LITTLE_ENDIANNESS_PRESERVE ((uint32_t)0x00000000U)
#define | MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX)
#define | MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX)
#define | MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX)
#define | MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U)
#define | MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1)
#define | MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0)
#define | MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1)
#define | MDMA_SRC_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS)
#define | MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC)
#define | MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0)
#define | MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1)
#define | MDMA_SRC_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS)
#define | MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U)
#define | MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1)
#define | MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0)
#define | MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1)
#define | MDMA_DEST_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS)
#define | MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC)
#define | MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0)
#define | MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1)
#define | MDMA_DEST_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS)
#define | MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U)
#define | MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0)
#define | MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1)
#define | MDMA_SRC_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_SSIZE)
#define | MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U)
#define | MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0)
#define | MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1)
#define | MDMA_DEST_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_DSIZE)
#define | MDMA_DATAALIGN_PACKENABLE ((uint32_t)MDMA_CTCR_PKE)
#define | MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
#define | MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0)
#define | MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1)
#define | MDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U)
#define | MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0)
#define | MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1)
#define | MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1)
#define | MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2)
#define | MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2)
#define | MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2)
#define | MDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST)
#define | MDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U)
#define | MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0)
#define | MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1)
#define | MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1)
#define | MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2)
#define | MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2)
#define | MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2)
#define | MDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST)
#define | MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE)
#define | MDMA_IT_CTC ((uint32_t)MDMA_CCR_CTCIE)
#define | MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE)
#define | MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE)
#define | MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE)
#define | MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF)
#define | MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF)
#define | MDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF)
#define | MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF)
#define | MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF)
#define | MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA)
#define | __HAL_MDMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= MDMA_CCR_EN)
Enable the specified MDMA Channel.
#define | __HAL_MDMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~MDMA_CCR_EN)
Disable the specified DMA Channel.
#define | __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CISR & (__FLAG__))
Get the MDMA Channel pending flags.
#define | __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__))
Clear the MDMA Stream pending flags.
#define | __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
Enables the specified DMA Channel interrupts.
#define | __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
Disables the specified MDMA Channel interrupts.
#define | __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
Checks whether the specified MDMA Channel interrupt is enabled or not.
#define | IS_MDMA_LEVEL_COMPLETE(__LEVEL__)
#define | IS_MDMA_PRIORITY(__PRIORITY__)
#define | IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__)
#define | IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_END_DATA))
#define | IS_MDMA_SOURCE_INC(__INC__)
#define | IS_MDMA_DESTINATION_INC(__INC__)
#define | IS_MDMA_SOURCE_DATASIZE(__SIZE__)
#define | IS_MDMA_DESTINATION_DATASIZE(__SIZE__)
#define | IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__)
#define | IS_MDMA_SOURCE_BURST(__BURST__)
#define | IS_MDMA_DESTINATION_BURST(__BURST__)
#define | IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__)
#define | IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001) && ((__LENGTH__) < 0x000000FF))
#define | IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0 ) && ((__COUNT__) <= 4096))
#define | IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0) && ((SIZE) <= 65536))
#define | IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536))

Typedefs

typedef struct __MDMA_HandleTypeDef | MDMA_HandleTypeDef
MDMA handle Structure definition.

Enumerations

enum HAL_MDMA_StateTypeDef {
HAL_MDMA_STATE_RESET = 0x00U, HAL_MDMA_STATE_READY = 0x01U, HAL_MDMA_STATE_BUSY = 0x02U, HAL_MDMA_STATE_ERROR = 0x03U,
HAL_MDMA_STATE_ABORT = 0x04U
}
HAL MDMA State structure definition. More...
enum | HAL_MDMA_LevelCompleteTypeDef { HAL_MDMA_FULL_TRANSFER = 0x00U, HAL_MDMA_BUFFER_TRANSFER = 0x01U, HAL_MDMA_BLOCK_TRANSFER = 0x02U, HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U }
HAL MDMA Level Complete structure definition. More...
enum HAL_MDMA_CallbackIDTypeDef {
HAL_MDMA_XFER_CPLT_CB_ID = 0x00U, HAL_MDMA_XFER_BUFFERCPLT_CB_ID = 0x01U, HAL_MDMA_XFER_BLOCKCPLT_CB_ID = 0x02U, HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID = 0x03U,
HAL_MDMA_XFER_ERROR_CB_ID = 0x04U, HAL_MDMA_XFER_ABORT_CB_ID = 0x05U, HAL_MDMA_XFER_ALL_CB_ID = 0x06U
}
HAL MDMA Callbacks IDs structure definition. More...

Functions

HAL_StatusTypeDef | HAL_MDMA_Init (MDMA_HandleTypeDef *hmdma)
Initializes the MDMA according to the specified parameters in the MDMA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma)
DeInitializes the MDMA peripheral.
HAL_StatusTypeDef | HAL_MDMA_ConfigPostRequestMask (MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData)
Config the Post request Mask address and Mask data.
HAL_StatusTypeDef | HAL_MDMA_RegisterCallback (MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void(*pCallback)(MDMA_HandleTypeDef *_hmdma))
Register callbacks.
HAL_StatusTypeDef | HAL_MDMA_UnRegisterCallback (MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_CreateNode (MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig)
Initializes an MDMA Link Node according to the specified parameters in the pMDMA_LinkedListNodeConfig .
HAL_StatusTypeDef | HAL_MDMA_LinkedList_AddNode (MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode)
Connect a node to the linked list.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_RemoveNode (MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode)
Disconnect/Remove a node from the transfer linked list.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_EnableCircularMode (MDMA_HandleTypeDef *hmdma)
Make the linked list circular by connecting the last node to the first.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_DisableCircularMode (MDMA_HandleTypeDef *hmdma)
Disable the linked list circular mode by setting the last node connection to null.
HAL_StatusTypeDef | HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
Starts the MDMA Transfer.
HAL_StatusTypeDef | HAL_MDMA_Start_IT (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
Starts the MDMA Transfer with interrupts enabled.
HAL_StatusTypeDef | HAL_MDMA_Abort (MDMA_HandleTypeDef *hmdma)
Aborts the MDMA Transfer.
HAL_StatusTypeDef | HAL_MDMA_Abort_IT (MDMA_HandleTypeDef *hmdma)
Aborts the MDMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_MDMA_PollForTransfer (MDMA_HandleTypeDef *hmdma, uint32_t CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
HAL_StatusTypeDef | HAL_MDMA_GenerateSWRequest (MDMA_HandleTypeDef *hmdma)
Generate an MDMA SW request trigger to activate the request on the given Channel.
void | HAL_MDMA_IRQHandler (MDMA_HandleTypeDef *hmdma)
Handles MDMA interrupt request.
HAL_MDMA_StateTypeDef | HAL_MDMA_GetState (MDMA_HandleTypeDef *hmdma)
Returns the MDMA state.
uint32_t | HAL_MDMA_GetError (MDMA_HandleTypeDef *hmdma)
Return the MDMA error code.

Detailed Description

Header file of DMA HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_mdma.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_mmc.h File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Data Structures | Defines | Enumerations | Functions
stm32h7xx_hal_mmc.h File Reference

Header file of MMC HAL module. More...

#include "stm32h7xx_ll_sdmmc.h"
#include "stm32h7xx_hal_mmc_ex.h"

Go to the source code of this file.

Data Structures

struct | HAL_MMC_CardInfoTypeDef
MMC Card Information Structure definition. More...
struct | MMC_HandleTypeDef
MMC handle Structure definition. More...
struct | HAL_MMC_CardCSDTypeDef
struct | HAL_MMC_CardCIDTypedef

Defines

#define | MMC_InitTypeDef SDMMC_InitTypeDef
#define | MMC_TypeDef SDMMC_TypeDef
#define | BLOCKSIZE ((uint32_t)512U)
#define | HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE
#define | HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL
#define | HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL
#define | HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT
#define | HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT
#define | HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN
#define | HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN
#define | HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED
#define | HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR
#define | HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR
#define | HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM
#define | HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION
#define | HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED
#define | HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED
#define | HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD
#define | HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED
#define | HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR
#define | HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR
#define | HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN
#define | HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN
#define | HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE
#define | HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP
#define | HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED
#define | HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET
#define | HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR
#define | HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE
#define | HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE
#define | HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE
#define | HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER
#define | HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE
#define | HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY
#define | HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA
#define | HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT
#define | MMC_CONTEXT_NONE ((uint32_t)0x00000000U)
#define | MMC_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U)
#define | MMC_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U)
#define | MMC_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U)
#define | MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)
#define | MMC_CONTEXT_IT ((uint32_t)0x00000008U)
#define | MMC_CONTEXT_DMA ((uint32_t)0x00000080U)
#define | MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U
#define | MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U
#define | eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U
#define | eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U
#define | MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
#define | MMC_LOW_CAPACITY_CARD ((uint32_t)0x00000000U)
#define | MMC_HIGH_CAPACITY_CARD ((uint32_t)0x00000001U)
#define | __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Enable the MMC device interrupt.
#define | __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Disable the MMC device interrupt.
#define | __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
Check whether the specified MMC flag is set or not.
#define | __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
Clear the MMC's pending flags.
#define | __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Check whether the specified MMC interrupt has occurred or not.
#define | __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Clear the MMC's interrupt pending bits.

Enumerations

enum HAL_MMC_StateTypeDef {
HAL_MMC_STATE_RESET = ((uint32_t)0x00000000U), HAL_MMC_STATE_READY = ((uint32_t)0x00000001U), HAL_MMC_STATE_TIMEOUT = ((uint32_t)0x00000002U), HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U),
HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU)
}
enum HAL_MMC_CardStateTypedef {
HAL_MMC_CARD_READY = ((uint32_t)0x00000001U), HAL_MMC_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), HAL_MMC_CARD_STANDBY = ((uint32_t)0x00000003U), HAL_MMC_CARD_TRANSFER = ((uint32_t)0x00000004U),
HAL_MMC_CARD_SENDING = ((uint32_t)0x00000005U), HAL_MMC_CARD_RECEIVING = ((uint32_t)0x00000006U), HAL_MMC_CARD_PROGRAMMING = ((uint32_t)0x00000007U), HAL_MMC_CARD_DISCONNECTED = ((uint32_t)0x00000008U),
HAL_MMC_CARD_ERROR = ((uint32_t)0x000000FFU)
}

Functions

HAL_StatusTypeDef | HAL_MMC_Init (MMC_HandleTypeDef *hmmc)
Initializes the MMC according to the specified parameters in the MMC_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_MMC_InitCard (MMC_HandleTypeDef *hmmc)
Initializes the MMC Card.
HAL_StatusTypeDef | HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc)
De-Initializes the MMC card.
__weak void | HAL_MMC_MspInit (MMC_HandleTypeDef *hmmc)
Initializes the MMC MSP.
__weak void | HAL_MMC_MspDeInit (MMC_HandleTypeDef *hmmc)
De-Initialize MMC MSP.
HAL_StatusTypeDef | HAL_MMC_ReadBlocks (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_WriteBlocks (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Allows to write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_Erase (MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
Erases the specified memory area of the given MMC card.
HAL_StatusTypeDef | HAL_MMC_ReadBlocks_IT (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_WriteBlocks_IT (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_ReadBlocks_DMA (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_WriteBlocks_DMA (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
void | HAL_MMC_IRQHandler (MMC_HandleTypeDef *hmmc)
This function handles MMC card interrupt request.
__weak void | HAL_MMC_TxCpltCallback (MMC_HandleTypeDef *hmmc)
Tx Transfer completed callbacks.
__weak void | HAL_MMC_RxCpltCallback (MMC_HandleTypeDef *hmmc)
Rx Transfer completed callbacks.
__weak void | HAL_MMC_ErrorCallback (MMC_HandleTypeDef *hmmc)
MMC error callbacks.
__weak void | HAL_MMC_AbortCallback (MMC_HandleTypeDef *hmmc)
MMC Abort callbacks.
HAL_StatusTypeDef | HAL_MMC_ConfigWideBusOperation (MMC_HandleTypeDef *hmmc, uint32_t WideMode)
Enables wide bus operation for the requested card if supported by card.
HAL_MMC_CardStateTypedef | HAL_MMC_GetCardState (MMC_HandleTypeDef *hmmc)
Gets the current mmc card data state.
HAL_StatusTypeDef | HAL_MMC_GetCardCID (MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypedef *pCID)
Returns information the information of the card which are stored on the CID register.
HAL_StatusTypeDef | HAL_MMC_GetCardCSD (MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
Returns information the information of the card which are stored on the CSD register.
HAL_StatusTypeDef | HAL_MMC_GetCardInfo (MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
Gets the MMC card info.
HAL_MMC_StateTypeDef | HAL_MMC_GetState (MMC_HandleTypeDef *hmmc)
return the MMC state
uint32_t | HAL_MMC_GetError (MMC_HandleTypeDef *hmmc)
Return the MMC error code.
HAL_StatusTypeDef | HAL_MMC_Abort (MMC_HandleTypeDef *hmmc)
Abort the current transfer and disable the MMC.
HAL_StatusTypeDef | HAL_MMC_Abort_IT (MMC_HandleTypeDef *hmmc)
Abort the current transfer and disable the MMC (IT mode).

Detailed Description

Header file of MMC HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_mmc.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_mmc_ex.h File Reference

  • File List
  • Globals
  • Drivers
  • STM32H7xx_HAL_Driver
  • Inc
Enumerations | Functions
stm32h7xx_hal_mmc_ex.h File Reference

Header file of MMC HAL extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Enumerations

enum | HAL_MMCEx_DMABuffer_MemoryTypeDef { MMC_DMA_BUFFER0 = 0x00U, MMC_DMA_BUFFER1 = 0x01U }

Functions

HAL_StatusTypeDef | HAL_MMCEx_ConfigDMAMultiBuffer (MMC_HandleTypeDef *hmmc, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, uint32_t BufferSize)
Configure DMA Dual Buffer mode.
HAL_StatusTypeDef | HAL_MMCEx_ReadBlocksDMAMultiBuffer (MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMCEx_WriteBlocksDMAMultiBuffer (MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMCEx_ChangeDMABuffer (MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
Change the DMA Buffer0 or Buffer1 address on the fly.
void | HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback (MMC_HandleTypeDef *hmmc)
Read DMA Buffer 0 Transfer completed callbacks.
void | HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback (MMC_HandleTypeDef *hmmc)
Read DMA Buffer 1 Transfer completed callbacks.
void | HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback (MMC_HandleTypeDef *hmmc)
Write DMA Buffer 0 Transfer completed callbacks.
void | HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback (MMC_HandleTypeDef *hmmc)
Write DMA Buffer 1 Transfer completed callbacks.

Detailed Description

Header file of MMC HAL extended module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_mmc_ex.h.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_nand.h File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Data Structures | Defines | Enumerations | Functions
stm32h7xx_hal_nand.h File Reference

Header file of NAND HAL module. More...

#include "stm32h7xx_ll_fmc.h"

Go to the source code of this file.

Data Structures

struct | NAND_IDTypeDef
NAND Memory electronic signature Structure definition. More...
struct | NAND_AddressTypeDef
NAND Memory address Structure definition. More...
struct | NAND_DeviceConfigTypeDef
NAND Memory info Structure definition. More...
struct | NAND_HandleTypeDef
NAND handle Structure definition. More...

Defines

#define | __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
Reset NAND handle state.
#define | NAND_DEVICE ((uint32_t)0x80000000U)
#define | NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)
#define | CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
#define | ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
#define | NAND_CMD_AREA_A ((uint8_t)0x00U)
#define | NAND_CMD_AREA_B ((uint8_t)0x01U)
#define | NAND_CMD_AREA_C ((uint8_t)0x50U)
#define | NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
#define | NAND_CMD_WRITE0 ((uint8_t)0x80U)
#define | NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
#define | NAND_CMD_ERASE0 ((uint8_t)0x60U)
#define | NAND_CMD_ERASE1 ((uint8_t)0xD0U)
#define | NAND_CMD_READID ((uint8_t)0x90U)
#define | NAND_CMD_STATUS ((uint8_t)0x70U)
#define | NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
#define | NAND_CMD_RESET ((uint8_t)0xFFU)
#define | NAND_VALID_ADDRESS ((uint32_t)0x00000100U)
#define | NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)
#define | NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)
#define | NAND_BUSY ((uint32_t)0x00000000U)
#define | NAND_ERROR ((uint32_t)0x00000001U)
#define | NAND_READY ((uint32_t)0x00000040U)
#define | ARRAY_ADDRESS(__ADDRESS__, __HANDLE__)
NAND memory address computation.
#define | COLUMN_ADDRESS(__HANDLE__) ((__HANDLE__)->Config.PageSize)
#define | ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
NAND memory address cycling.
#define | ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
#define | ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
#define | ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
#define | COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
NAND memory Columns cycling.
#define | COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */

Enumerations

enum | HAL_NAND_StateTypeDef { HAL_NAND_STATE_RESET = 0x00U, HAL_NAND_STATE_READY = 0x01U, HAL_NAND_STATE_BUSY = 0x02U, HAL_NAND_STATE_ERROR = 0x03U }
HAL NAND State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_NAND_Init (NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
Perform NAND memory Initialization sequence.
HAL_StatusTypeDef | HAL_NAND_DeInit (NAND_HandleTypeDef *hnand)
Perform NAND memory De-Initialization sequence.
__weak void | HAL_NAND_MspInit (NAND_HandleTypeDef *hnand)
NAND MSP Init.
__weak void | HAL_NAND_MspDeInit (NAND_HandleTypeDef *hnand)
NAND MSP DeInit.
void | HAL_NAND_IRQHandler (NAND_HandleTypeDef *hnand)
This function handles NAND device interrupt request.
__weak void | HAL_NAND_ITCallback (NAND_HandleTypeDef *hnand)
NAND interrupt feature callback.
HAL_StatusTypeDef | HAL_NAND_Read_ID (NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
Read the NAND memory electronic signature.
HAL_StatusTypeDef | HAL_NAND_ConfigDevice (NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
Configure the device: Enter the physical parameters of the device.
HAL_StatusTypeDef | HAL_NAND_Reset (NAND_HandleTypeDef *hnand)
NAND memory reset.
HAL_StatusTypeDef | HAL_NAND_Read_Page_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
Read Page(s) from NAND memory block (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_Page_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
Write Page(s) to NAND memory block (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Read_SpareArea_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
Read Spare area(s) from NAND memory (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_SpareArea_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
Write Spare area(s) to NAND memory (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Read_Page_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
Read Page(s) from NAND memory block (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_Page_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
Write Page(s) to NAND memory block (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Read_SpareArea_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
Read Spare area(s) from NAND memory (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_SpareArea_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
Write Spare area(s) to NAND memory (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Erase_Block (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
NAND memory Block erase.
uint32_t | HAL_NAND_Address_Inc (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
Increment the NAND memory address.
HAL_StatusTypeDef | HAL_NAND_ECC_Enable (NAND_HandleTypeDef *hnand)
Enables dynamically NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_ECC_Disable (NAND_HandleTypeDef *hnand)
Disables dynamically FMC_NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_GetECC (NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
Disables dynamically NAND ECC feature.
HAL_NAND_StateTypeDef | HAL_NAND_GetState (NAND_HandleTypeDef *hnand)
return the NAND state
uint32_t | HAL_NAND_Read_Status (NAND_HandleTypeDef *hnand)
NAND memory read status.

Detailed Description

Header file of NAND HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_nand.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_nor.h File Reference

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stm32h7xx_hal_nor.h File Reference

Header file of NOR HAL module. More...

#include "stm32h7xx_ll_fmc.h"

Go to the source code of this file.

Data Structures

struct | NOR_IDTypeDef
FMC NOR ID typedef. More...
struct | NOR_CFITypeDef
FMC NOR CFI typedef. More...
struct | NOR_HandleTypeDef
NOR handle Structure definition. More...

Defines

#define | __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
Reset NOR handle state.
#define | MC_ADDRESS ((uint16_t)0x0000U)
#define | DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
#define | DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
#define | DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
#define | CFI1_ADDRESS ((uint16_t)0x61U)
#define | CFI2_ADDRESS ((uint16_t)0x62U)
#define | CFI3_ADDRESS ((uint16_t)0x63U)
#define | CFI4_ADDRESS ((uint16_t)0x64U)
#define | NOR_TMEOUT ((uint16_t)0xFFFFU)
#define | NOR_MEMORY_8B ((uint8_t)0x0U)
#define | NOR_MEMORY_16B ((uint8_t)0x1U)
#define | NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)
#define | NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)
#define | NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)
#define | NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)
#define | NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)
NOR memory address shifting.
#define | NOR_WRITE(__ADDRESS__, __DATA__)
NOR memory write data to specified address.

Enumerations

enum HAL_NOR_StateTypeDef {
HAL_NOR_STATE_RESET = 0x00U, HAL_NOR_STATE_READY = 0x01U, HAL_NOR_STATE_BUSY = 0x02U, HAL_NOR_STATE_ERROR = 0x03U,
HAL_NOR_STATE_PROTECTED = 0x04U
}
HAL SRAM State structures definition. More...
enum | HAL_NOR_StatusTypeDef { HAL_NOR_STATUS_SUCCESS = 0U, HAL_NOR_STATUS_ONGOING, HAL_NOR_STATUS_ERROR, HAL_NOR_STATUS_TIMEOUT }
FMC NOR Status typedef. More...

Functions

HAL_StatusTypeDef | HAL_NOR_Init (NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Perform the NOR memory Initialization sequence.
HAL_StatusTypeDef | HAL_NOR_DeInit (NOR_HandleTypeDef *hnor)
Perform NOR memory De-Initialization sequence.
__weak void | HAL_NOR_MspInit (NOR_HandleTypeDef *hnor)
NOR MSP Init.
__weak void | HAL_NOR_MspDeInit (NOR_HandleTypeDef *hnor)
NOR MSP DeInit.
__weak void | HAL_NOR_MspWait (NOR_HandleTypeDef *hnor, uint32_t Timeout)
NOR MSP Wait for Ready/Busy signal.
HAL_StatusTypeDef | HAL_NOR_Read_ID (NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
Read NOR flash IDs.
HAL_StatusTypeDef | HAL_NOR_ReturnToReadMode (NOR_HandleTypeDef *hnor)
Returns the NOR memory to Read mode.
HAL_StatusTypeDef | HAL_NOR_Read (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Read data from NOR memory.
HAL_StatusTypeDef | HAL_NOR_Program (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Program data to NOR memory.
HAL_StatusTypeDef | HAL_NOR_ReadBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Reads a half-word buffer from the NOR memory.
HAL_StatusTypeDef | HAL_NOR_ProgramBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Writes a half-word buffer to the NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Block (NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
Erase the specified block of the NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Chip (NOR_HandleTypeDef *hnor, uint32_t Address)
Erase the entire NOR chip.
HAL_StatusTypeDef | HAL_NOR_Read_CFI (NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
Read NOR flash CFI IDs.
HAL_StatusTypeDef | HAL_NOR_WriteOperation_Enable (NOR_HandleTypeDef *hnor)
Enables dynamically NOR write operation.
HAL_StatusTypeDef | HAL_NOR_WriteOperation_Disable (NOR_HandleTypeDef *hnor)
Disables dynamically NOR write operation.
HAL_NOR_StateTypeDef | HAL_NOR_GetState (NOR_HandleTypeDef *hnor)
return the NOR controller state
HAL_NOR_StatusTypeDef | HAL_NOR_GetStatus (NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
Returns the NOR operation status.

Detailed Description

Header file of NOR HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_nor.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_opamp.h File Reference

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stm32h7xx_hal_opamp.h File Reference

Header file of OPAMP HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_opamp_ex.h"

Go to the source code of this file.

Data Structures

struct | OPAMP_InitTypeDef
OPAMP Init structure definition. More...
struct | OPAMP_HandleTypeDef
OPAMP Handle Structure definition. More...

Defines

#define | OPAMP_STANDALONE_MODE ((uint32_t)0x00000000)
#define | OPAMP_PGA_MODE OPAMP_CSR_VMSEL_1
#define | OPAMP_FOLLOWER_MODE (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0)
#define | OPAMP_NONINVERTINGINPUT_IO0 ((uint32_t)0x00000000)
#define | OPAMP_NONINVERTINGINPUT_DAC_CH OPAMP_CSR_VPSEL_0
#define | OPAMP_INVERTINGINPUT_IO0 ((uint32_t)0x00000000)
#define | OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0
#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_NO ((uint32_t)0x00000000)
#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_CSR_PGGAIN_2
#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS OPAMP_CSR_PGGAIN_3
#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_3)
#define | OPAMP_PGA_GAIN_2_OR_MINUS_1 ((uint32_t)0x00000000)
#define | OPAMP_PGA_GAIN_4_OR_MINUS_3 OPAMP_CSR_PGGAIN_0
#define | OPAMP_PGA_GAIN_8_OR_MINUS_7 OPAMP_CSR_PGGAIN_1
#define | OPAMP_PGA_GAIN_16_OR_MINUS_15 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1)
#define | OPAMP_POWERMODE_NORMAL ((uint32_t)0x00000000)
#define | OPAMP_POWERMODE_HIGHSPEED OPAMP_CSR_OPAHSM
#define | OPAMP_VREF_3VDDA ((uint32_t)0x00000000)
#define | OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0
#define | OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1
#define | OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL
#define | OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000)
#define | OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM
#define | OPAMP_FACTORYTRIMMING_DUMMY ((uint32_t)0xFFFFFFFF)
#define | OPAMP_FACTORYTRIMMING_N ((uint32_t)0x00000000)
#define | OPAMP_FACTORYTRIMMING_P ((uint32_t)0x00000001)
#define | OPAMP_INPUT_NONINVERTING ((uint32_t) 8)
#define | OPAMP_TRIMMING_DELAY ((uint32_t) 2)
#define | __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
Reset OPAMP handle state.
#define | IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT)
#define | IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT)
#define | IS_OPAMP_NONINVERTING_INPUT(INPUT)
#define | IS_OPAMP_PGACONNECT(CONNECT)
#define | IS_OPAMP_PGA_GAIN(GAIN)
#define | IS_OPAMP_VREF(VREF)
#define | IS_OPAMP_POWERMODE(TRIMMING)
#define | IS_OPAMP_TRIMMING(TRIMMING)
#define | IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
#define | IS_OPAMP_FACTORYTRIMMING(TRIMMING)

Typedefs

typedef uint32_t | HAL_OPAMP_TrimmingValueTypeDef
HAl_OPAMP_TrimmingValueTypeDef definition.

Enumerations

enum HAL_OPAMP_StateTypeDef {
HAL_OPAMP_STATE_RESET = 0x00000000, HAL_OPAMP_STATE_READY = 0x00000001, HAL_OPAMP_STATE_CALIBBUSY = 0x00000002, HAL_OPAMP_STATE_BUSY = 0x00000004,
HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_OPAMP_Init (OPAMP_HandleTypeDef *hopamp)
Initialize the OPAMP according to the specified parameters in the OPAMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp)
DeInitialize the OPAMP peripheral.
__weak void | HAL_OPAMP_MspInit (OPAMP_HandleTypeDef *hopamp)
Initialize the OPAMP MSP.
__weak void | HAL_OPAMP_MspDeInit (OPAMP_HandleTypeDef *hopamp)
DeInitialize OPAMP MSP.
HAL_StatusTypeDef | HAL_OPAMP_Start (OPAMP_HandleTypeDef *hopamp)
Start the OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_Stop (OPAMP_HandleTypeDef *hopamp)
Stop the OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_SelfCalibrate (OPAMP_HandleTypeDef *hopamp)
Run the self calibration of one OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_Lock (OPAMP_HandleTypeDef *hopamp)
Lock the selected OPAMP configuration.
HAL_OPAMP_TrimmingValueTypeDef | HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
Return the OPAMP factory trimming value.
HAL_OPAMP_StateTypeDef | HAL_OPAMP_GetState (OPAMP_HandleTypeDef *hopamp)
Return the OPAMP handle state.

Detailed Description

Header file of OPAMP HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_opamp.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_opamp_ex.h File Reference

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Functions
stm32h7xx_hal_opamp_ex.h File Reference

Header file of OPAMP HAL Extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_OPAMPEx_SelfCalibrateAll (OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
Run the self calibration of 2 OPAMPs in parallel.
HAL_StatusTypeDef | HAL_OPAMPEx_Unlock (OPAMP_HandleTypeDef *hopamp)
Unlock the selected OPAMP configuration.

Detailed Description

Header file of OPAMP HAL Extended module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_opamp_ex.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_pcd.h File Reference

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stm32h7xx_hal_pcd.h File Reference

Header file of PCD HAL module. More...

#include "stm32h7xx_ll_usb.h"
#include "stm32h7xx_hal_pcd_ex.h"

Go to the source code of this file.

Data Structures

struct | PCD_HandleTypeDef
PCD Handle Structure definition. More...

Defines

#define | PCD_SPEED_HIGH 0
#define | PCD_SPEED_HIGH_IN_FULL 1
#define | PCD_SPEED_FULL 2
#define | PCD_PHY_ULPI 1
#define | PCD_PHY_EMBEDDED 2
#define | USBD_HS_TRDT_VALUE 9
#define | USBD_FS_TRDT_VALUE 5
#define | __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define | __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
#define | __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)
#define | __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
#define | __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
#define | USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)
#define | USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)
#define | USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)
#define | USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)
#define | USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)
#define | USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)
#define | USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR2_IM43)
#define | USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR2_IM44)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI_D1->IMR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI_D1->IMR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI_D1->PR2 & (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI_D1->PR2 = (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE()
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER2 |= USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI_D1->IMR2 |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI_D1->IMR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI_D1->PR2 & (USB_OTG_FS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI_D1->PR2 = USB_OTG_FS_WAKEUP_EXTI_LINE
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE()
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER2 |= USB_OTG_FS_WAKEUP_EXTI_LINE)
#define | IS_PCD_ALL_INSTANCE(INSTANCE)

Typedefs

typedef USB_OTG_GlobalTypeDef | PCD_TypeDef
typedef USB_OTG_CfgTypeDef | PCD_InitTypeDef
typedef USB_OTG_EPTypeDef | PCD_EPTypeDef

Enumerations

enum PCD_StateTypeDef {
HAL_PCD_STATE_RESET = 0x00, HAL_PCD_STATE_READY = 0x01, HAL_PCD_STATE_ERROR = 0x02, HAL_PCD_STATE_BUSY = 0x03,
HAL_PCD_STATE_TIMEOUT = 0x04
}
PCD State structure definition. More...
enum | PCD_LPM_StateTypeDef { LPM_L0 = 0x00, LPM_L1 = 0x01, LPM_L2 = 0x02, LPM_L3 = 0x03 }

Functions

HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start The USB OTG Device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop The USB OTG Device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
This function handles PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data out stage callbacks.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callbacks.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callbacks.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callbacks.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callbacks.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callbacks.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callbacks.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callbacks.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callbacks.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callbacks.
HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
uint16_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
HAL_PCD_ActivateRemoteWakeup : Active remote wake-up signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
HAL_PCD_DeActivateRemoteWakeup : de-active remote wake-up signalling.
PCD_StateTypeDef | HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD state.

Detailed Description

Header file of PCD HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_pcd.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_pcd_ex.h File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Enumerations | Functions
stm32h7xx_hal_pcd_ex.h File Reference

Header file of PCD HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Enumerations

enum | PCD_LPM_MsgTypeDef { PCD_LPM_L0_ACTIVE = 0x00, PCD_LPM_L1_ACTIVE = 0x01 }
enum PCD_BCD_MsgTypeDef {
PCD_BCD_ERROR = 0xFF, PCD_BCD_CONTACT_DETECTION = 0xFE, PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, PCD_BCD_DISCOVERY_COMPLETED = 0x00
}

Functions

HAL_StatusTypeDef | HAL_PCDEx_SetTxFiFo (PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
Set Tx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_SetRxFiFo (PCD_HandleTypeDef *hpcd, uint16_t size)
Set Rx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_ActivateLPM (PCD_HandleTypeDef *hpcd)
HAL_PCDEx_ActivateLPM : active LPM Feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateLPM (PCD_HandleTypeDef *hpcd)
HAL_PCDEx_DeActivateLPM : de-active LPM feature.
HAL_StatusTypeDef | HAL_PCDEx_ActivateBCD (PCD_HandleTypeDef *hpcd)
Activate BatteryCharging feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateBCD (PCD_HandleTypeDef *hpcd)
Deactivate BatteryCharging feature.
void | HAL_PCDEx_BCD_VBUSDetect (PCD_HandleTypeDef *hpcd)
Handle BatteryCharging Process.
__weak void | HAL_PCDEx_LPM_Callback (PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
Send LPM message to user layer callback.
__weak void | HAL_PCDEx_BCD_Callback (PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
Send BatteryCharging message to user layer callback.

Detailed Description

Header file of PCD HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_pcd_ex.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_pwr.h File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Data Structures | Defines | Functions
stm32h7xx_hal_pwr.h File Reference

Header file of PWR HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_pwr_ex.h"

Go to the source code of this file.

Data Structures

struct | PWR_PVDTypeDef
PWR PVD configuration structure definition. More...

Defines

#define | PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0
#define | PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1
#define | PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2
#define | PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3
#define | PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4
#define | PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5
#define | PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6
#define | PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7/* External input analog voltage (Compare internally to VREFINT) */
#define | PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U)
#define | PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U)
#define | PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U)
#define | PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U)
#define | PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U)
#define | PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U)
#define | PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U)
#define | PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)
#define | PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS
#define | PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)
#define | PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)
#define | PWR_STOPENTRY_WFI ((uint8_t)0x01U)
#define | PWR_STOPENTRY_WFE ((uint8_t)0x02U)
#define | PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
#define | PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1)
#define | PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0)
#define | PWR_FLAG_STOP ((uint8_t)0x01U)
#define | PWR_FLAG_SB_D1 ((uint8_t)0x02U)
#define | PWR_FLAG_SB_D2 ((uint8_t)0x03U)
#define | PWR_FLAG_SB ((uint8_t)0x04U)
#define | PWR_FLAG_PVDO ((uint8_t)0x07U)
#define | PWR_FLAG_AVDO ((uint8_t)0x08U)
#define | PWR_FLAG_ACTVOSRDY ((uint8_t)0x09U)
#define | PWR_FLAG_ACTVOS ((uint8_t)0x0AU)
#define | PWR_FLAG_BRR ((uint8_t)0x0BU)
#define | PWR_FLAG_VOSRDY ((uint8_t)0x0CU)
#define | PWR_FLAG_SCUEN ((uint8_t)0x0DU)
#define | PWR_EWUP_MASK ((uint32_t)0x0FFF3F3FU)
#define | __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)
macros configure the main internal regulator output voltage.
#define | __HAL_PWR_GET_FLAG(__FLAG__)
Check PWR PVD/AVD and VOSflags are set or not.
#define | __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
Clear the PWR's flags.
#define | __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_PVD)
Enable the PVD EXTI Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_PVD)
Disable the PVD EXTI Line 16.
#define | __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_PVD)
Enable event on PVD EXTI Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_PVD)
Disable event on PVD EXTI Line 16.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
PVD EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_GET_FLAG() READ_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_PVD)
Check whether the specified PVD EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_PVD)
Clear the PVD EXTI flag.
#define | __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
Generates a Software interrupt on PVD EXTI line.
#define | PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR1_IM16)
#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | IS_PWR_PVD_MODE(MODE)
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define | IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
#define | IS_PWR_REGULATOR_VOLTAGE(VOLTAGE)

Functions

void | HAL_PWR_DeInit (void)
Deinitialize the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configure the voltage threshold detected by the Power Voltage Detector(PVD).
void | HAL_PWR_EnablePVD (void)
Enable the Power Voltage Detector(PVD).
void | HAL_PWR_DisablePVD (void)
Disable the Power Voltage Detector(PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
Enable the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disable the WakeUp PINx functionality.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enter the system to STOP mode.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enter CM7 core to Sleep mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enter the system to STANDBY mode.
void | HAL_PWR_PVD_IRQHandler (void)
This function handles the PWR PVD interrupt request.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.
void | HAL_PWR_EnableSleepOnExit (void)
Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enable CORTEX SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disable CORTEX SEVONPEND bit.

Detailed Description

Header file of PWR HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_pwr.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_pwr_ex.h File Reference

  • File List
  • Globals
  • Drivers
  • STM32H7xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32h7xx_hal_pwr_ex.h File Reference

Header file of PWR HAL Extension module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | PWREx_AVDTypeDef
PWREx AVD configuration structure definition. More...
struct | PWREx_WakeupPinTypeDef
PWREx Wakeup pin configuration structure definition. More...

Defines

#define | PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN_6
#define | PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN_5
#define | PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN_4
#define | PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN_3
#define | PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN_2
#define | PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN_1
#define | PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN_6
#define | PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN_5
#define | PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN_4
#define | PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN_3
#define | PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN_2
#define | PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN_1
#define | PWR_WAKEUP_PIN6_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_6 | PWR_WKUPEPR_WKUPEN_6)
#define | PWR_WAKEUP_PIN5_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_5 | PWR_WKUPEPR_WKUPEN_5)
#define | PWR_WAKEUP_PIN4_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_4 | PWR_WKUPEPR_WKUPEN_4)
#define | PWR_WAKEUP_PIN3_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_3 | PWR_WKUPEPR_WKUPEN_3)
#define | PWR_WAKEUP_PIN2_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_2 | PWR_WKUPEPR_WKUPEN_2)
#define | PWR_WAKEUP_PIN1_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_1 | PWR_WKUPEPR_WKUPEN_1)
#define | PWR_EXTI_WAKEUP_PINS_MASK
#define | PWR_PIN_POLARITY_HIGH ((uint32_t)0x00000000U)
#define | PWR_PIN_POLARITY_LOW ((uint32_t)0x00000001U)
#define | PWR_PIN_NO_PULL ((uint32_t)0x00000000U)
#define | PWR_PIN_PULL_UP ((uint32_t)0x00000001U)
#define | PWR_PIN_PULL_DOWN ((uint32_t)0x00000002U)
#define | PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1
#define | PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2
#define | PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3
#define | PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4
#define | PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5
#define | PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6
#define | PWR_D1_DOMAIN ((uint32_t)0x00000000U)
#define | PWR_D2_DOMAIN ((uint32_t)0x00000001U)
#define | PWR_D3_DOMAIN ((uint32_t)0x00000002U)
#define | PWR_CPU_FLAGS ((uint32_t)0x00000000U)
#define | PWR_D3_DOMAIN_STOP ((uint32_t)0x00000000U)
#define | PWR_D3_DOMAIN_RUN ((uint32_t)0x00000800U)
#define | PWR_LDO_SUPPLY PWR_CR3_LDOEN /* Core domains are suppplied from the LDO */
#define | PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /* The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source */
#define | PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
#define | PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0
#define | PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1
#define | PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2
#define | PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3
#define | PWR_AVD_MODE_NORMAL ((uint32_t)0x00000000U)
#define | PWR_AVD_MODE_IT_RISING ((uint32_t)0x00010001U)
#define | PWR_AVD_MODE_IT_FALLING ((uint32_t)0x00010002U)
#define | PWR_AVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U)
#define | PWR_AVD_MODE_EVENT_RISING ((uint32_t)0x00020001U)
#define | PWR_AVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U)
#define | PWR_AVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U)
#define | PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0)
#define | PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1)
#define | PWR_REGULATOR_SVOS_SCALE3 (uint32_t)(PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)
#define | PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000U)
#define | PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS
#define | PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U)
#define | PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL
#define | PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH
#define | PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U)
#define | PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL
#define | PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH
#define | PWR_EXTI_LINE_AVD ((uint32_t)EXTI_IMR1_IM16)
#define | __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_AVD)
Enable the AVD EXTI Line 16.
#define | __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_AVD)
Disable the AVD EXTI Line 16.
#define | __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_AVD)
Enable event on AVD EXTI Line 16.
#define | __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_AVD)
Disable event on AVD EXTI Line 16.
#define | __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
Enable the AVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
Disable the AVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
Enable the AVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
Disable the AVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE()
AVD EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the AVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_AVD_EXTI_GET_FLAG() READ_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_AVD)
Check whether the specified AVD EXTI interrupt flag is set or not.
#define | __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_AVD)
Clear the AVD EXTI flag.
#define | IS_PWR_SUPPLY(PWR_SOURCE)
#define | IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE)
#define | IS_PWR_DOMAIN(DOMAIN)
#define | IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) || ((STATE) == PWR_D3_DOMAIN_RUN))
#define | IS_PWR_WAKEUP_PIN(PIN)
#define | IS_PWR_WAKEUP_PIN_POLARITY(POLARITY)
#define | IS_PWR_WAKEUP_PIN_PULL(PULL)
#define | IS_PWR_WAKEUP_FLAG(FLAG)
#define | IS_PWR_AVD_LEVEL(LEVEL)
#define | IS_PWR_AVD_MODE(MODE)
#define | IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR)

Functions

HAL_StatusTypeDef | HAL_PWREx_ConfigSupply (uint32_t SupplySource)
Configure the system Power Supply.
uint32_t | HAL_PWREx_GetSupplyConfig (void)
Get the power supply configuration.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configure the main internal regulator output voltage.
uint32_t | HAL_PWREx_GetVoltageRange (void)
Get the main internal regulator output voltage.
HAL_StatusTypeDef | HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling)
Configure the main internal regulator output voltage in STOP mode.
uint32_t | HAL_PWREx_GetStopModeVoltageRange (void)
Get the main internal regulator output voltage in STOP mode.
void | HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain)
Enter a Domain to DSTOP mode.
void | HAL_PWREx_EnterSTANDBYMode (uint32_t Domain)
Enter a Domain to DSTANDBY mode.
void | HAL_PWREx_ConfigD3Domain (uint32_t D3State)
Configure the D3 Domain state when the CPU is in low power mode.
void | HAL_PWREx_EnableFlashPowerDown (void)
Enable the Flash Power Down in Stop mode.
void | HAL_PWREx_DisableFlashPowerDown (void)
Disable the Flash Power Down in Stop mode.
void | HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams)
Enable the Wake-up PINx functionality.
void | HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the Wake-up PINx functionality.
uint32_t | HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag)
Get the Wake-Up Pin flag.
HAL_StatusTypeDef | HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag)
Clear the Wake-Up pin flag.
void | HAL_PWREx_WAKEUP_PIN_IRQHandler (void)
This function handles the PWR WAKEUP PIN interrupt request.
__weak void | HAL_PWREx_WKUP1_Callback (void)
PWR WKUP1 interrupt callback.
__weak void | HAL_PWREx_WKUP2_Callback (void)
PWR WKUP2 interrupt callback.
__weak void | HAL_PWREx_WKUP3_Callback (void)
PWR WKUP3 interrupt callback.
__weak void | HAL_PWREx_WKUP4_Callback (void)
PWR WKUP4 interrupt callback.
__weak void | HAL_PWREx_WKUP5_Callback (void)
PWR WKUP5 interrupt callback.
__weak void | HAL_PWREx_WKUP6_Callback (void)
PWR WKUP6 interrupt callback.
HAL_StatusTypeDef | HAL_PWREx_EnableBkUpReg (void)
Enable the Backup Regulator.
HAL_StatusTypeDef | HAL_PWREx_DisableBkUpReg (void)
Disable the Backup Regulator.
HAL_StatusTypeDef | HAL_PWREx_EnableUSBReg (void)
Enable the USB Regulator.
HAL_StatusTypeDef | HAL_PWREx_DisableUSBReg (void)
Disable the USB Regulator.
void | HAL_PWREx_EnableUSBVoltageDetector (void)
Enable the USB voltage level detector.
void | HAL_PWREx_DisableUSBVoltageDetector (void)
Disable the USB voltage level detector.
void | HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue)
Enable the Battery charging.
void | HAL_PWREx_DisableBatteryCharging (void)
Disable the Battery charging.
void | HAL_PWREx_EnableMonitoring (void)
Enable the VBAT and temperature monitoring.
void | HAL_PWREx_DisableMonitoring (void)
Disable the VBAT and temperature monitoring.
uint32_t | HAL_PWREx_GetTemperatureLevel (void)
Indicate whether the junction temperature is between, above or below the threshold.
uint32_t | HAL_PWREx_GetVBATLevel (void)
Indicate whether the Battery voltage level is between, above or below the threshold.
void | HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD)
Configure the analog voltage threshold detected by the Analog Voltage Detector(AVD).
void | HAL_PWREx_EnableAVD (void)
Enable the Analog Voltage Detector(AVD).
void | HAL_PWREx_DisableAVD (void)
Disable the Analog Voltage Detector(AVD).
void | HAL_PWREx_PVD_AVD_IRQHandler (void)
This function handles the PWR PVD/AVD interrupt request.
__weak void | HAL_PWREx_AVDCallback (void)
PWR AVD interrupt callback.

Detailed Description

Header file of PWR HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_pwr_ex.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_qspi.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32h7xx_hal_qspi.h File Reference

Header file of QSPI HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_mdma.h"

Go to the source code of this file.

Data Structures

struct | QSPI_InitTypeDef
QSPI Init structure definition. More...
struct | QSPI_HandleTypeDef
QSPI Handle Structure definition. More...
struct | QSPI_CommandTypeDef
QSPI Command structure definition. More...
struct | QSPI_AutoPollingTypeDef
QSPI Auto Polling mode configuration structure definition. More...
struct | QSPI_MemoryMappedTypeDef
QSPI Memory Mapped mode configuration structure definition. More...

Defines

#define | HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U)
#define | HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U)
#define | HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U)
#define | HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U)
#define | QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U)
#define | QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT)
#define | QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000U)
#define | QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0)
#define | QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2)
#define | QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0)
#define | QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT)
#define | QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000)
#define | QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE)
#define | QSPI_FLASH_ID_1 ((uint32_t)0x00000000)
#define | QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
#define | QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
#define | QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000)
#define | QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000)
#define | QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0)
#define | QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1)
#define | QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE)
#define | QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000)
#define | QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0)
#define | QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1)
#define | QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE)
#define | QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000)
#define | QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0)
#define | QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1)
#define | QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE)
#define | QSPI_ADDRESS_NONE ((uint32_t)0x00000000)
#define | QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0)
#define | QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1)
#define | QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE)
#define | QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000)
#define | QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0)
#define | QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1)
#define | QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE)
#define | QSPI_DATA_NONE ((uint32_t)0X00000000)
#define | QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0)
#define | QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1)
#define | QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE)
#define | QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000)
#define | QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM)
#define | QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000)
#define | QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC)
#define | QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000)
#define | QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO)
#define | QSPI_MATCH_MODE_AND ((uint32_t)0x00000000)
#define | QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM)
#define | QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000)
#define | QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS)
#define | QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000)
#define | QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN)
#define | QSPI_FLAG_BUSY QUADSPI_SR_BUSY
#define | QSPI_FLAG_TO QUADSPI_SR_TOF
#define | QSPI_FLAG_SM QUADSPI_SR_SMF
#define | QSPI_FLAG_FT QUADSPI_SR_FTF
#define | QSPI_FLAG_TC QUADSPI_SR_TCF
#define | QSPI_FLAG_TE QUADSPI_SR_TEF
#define | QSPI_IT_TO QUADSPI_CR_TOIE
#define | QSPI_IT_SM QUADSPI_CR_SMIE
#define | QSPI_IT_FT QUADSPI_CR_FTIE
#define | QSPI_IT_TC QUADSPI_CR_TCIE
#define | QSPI_IT_TE QUADSPI_CR_TEIE
#define | HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
#define | __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
Reset QSPI handle state.
#define | __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
Enable the QSPI peripheral.
#define | __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
Disable the QSPI peripheral.
#define | __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Enable the specified QSPI interrupt.
#define | __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Disable the specified QSPI interrupt.
#define | __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified QSPI interrupt source is enabled or not.
#define | __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
Check whether the selected QSPI flag is set or not.
#define | __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
Clears the specified QSPI's flag status.
#define | IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
#define | IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 32))
#define | IS_QSPI_SSHIFT(SSHIFT)
#define | IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))
#define | IS_QSPI_CS_HIGH_TIME(CSHTIME)
#define | IS_QSPI_CLOCK_MODE(CLKMODE)
#define | IS_QSPI_FLASH_ID(FLASH)
#define | IS_QSPI_DUAL_FLASH_MODE(MODE)
#define | IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
#define | IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)
#define | IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE)
#define | IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31)
#define | IS_QSPI_INSTRUCTION_MODE(MODE)
#define | IS_QSPI_ADDRESS_MODE(MODE)
#define | IS_QSPI_ALTERNATE_BYTES_MODE(MODE)
#define | IS_QSPI_DATA_MODE(MODE)
#define | IS_QSPI_DDR_MODE(DDR_MODE)
#define | IS_QSPI_DDR_HHC(DDR_HHC)
#define | IS_QSPI_SIOO_MODE(SIOO_MODE)
#define | IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
#define | IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))
#define | IS_QSPI_MATCH_MODE(MODE)
#define | IS_QSPI_AUTOMATIC_STOP(APMS)
#define | IS_QSPI_TIMEOUT_ACTIVATION(TCEN)
#define | IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)

Enumerations

enum HAL_QSPI_StateTypeDef {
HAL_QSPI_STATE_RESET = 0x00U, HAL_QSPI_STATE_READY = 0x01U, HAL_QSPI_STATE_BUSY = 0x02U, HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U,
HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, HAL_QSPI_STATE_ABORT = 0x08U,
HAL_QSPI_STATE_ERROR = 0x04U
}
HAL QSPI State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI mode according to the specified parameters in the QSPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi)
De-Initialize the QSPI peripheral.
void | HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI MSP.
void | HAL_QSPI_MspDeInit (QSPI_HandleTypeDef *hqspi)
DeInitialize the QSPI MSP.
void | HAL_QSPI_IRQHandler (QSPI_HandleTypeDef *hqspi)
Handle QSPI interrupt request.
HAL_StatusTypeDef | HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
Set the command configuration.
HAL_StatusTypeDef | HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
Set the command configuration in interrupt mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
Configure the QSPI Automatic Polling Mode in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
Configure the QSPI Automatic Polling Mode in non-blocking mode.
HAL_StatusTypeDef | HAL_QSPI_MemoryMapped (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
Configure the Memory Mapped mode.
void | HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi)
Transfer Error callback.
void | HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi)
Abort completed callback.
void | HAL_QSPI_FifoThresholdCallback (QSPI_HandleTypeDef *hqspi)
FIFO Threshold callback.
void | HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi)
Command completed callback.
void | HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Transfer completed callback.
void | HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Transfer completed callback.
void | HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Half Transfer completed callback.
void | HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Half Transfer completed callback.
void | HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi)
Status Match callback.
void | HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi)
Timeout callback.
HAL_QSPI_StateTypeDef | HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi)
Return the QSPI handle state.
uint32_t | HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi)
Return the QSPI error code.
HAL_StatusTypeDef | HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi)
Abort the current transmission.
HAL_StatusTypeDef | HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi)
Abort the current transmission (non-blocking function)
void | HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
Set QSPI timeout.
HAL_StatusTypeDef | HAL_QSPI_SetFifoThreshold (QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
Set QSPI Fifo threshold.
uint32_t | HAL_QSPI_GetFifoThreshold (QSPI_HandleTypeDef *hqspi)
Get QSPI Fifo threshold.

Detailed Description

Header file of QSPI HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_qspi.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_rcc.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_hal_rcc.h File Reference

Header file of RCC HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_rcc_ex.h"

Go to the source code of this file.

Data Structures

struct | RCC_PLLInitTypeDef
RCC PLL configuration structure definition. More...
struct | RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition. More...
struct | RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition. More...

Defines

#define | RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
#define | RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
#define | RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
#define | RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
#define | RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
#define | RCC_OSCILLATORTYPE_CSI ((uint32_t)0x00000010)
#define | RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
#define | RCC_HSE_OFF ((uint32_t)0x00000000)
#define | RCC_HSE_ON RCC_CR_HSEON
#define | RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
#define | RCC_LSE_OFF ((uint32_t)0x00000000)
#define | RCC_LSE_ON RCC_BDCR_LSEON
#define | RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
#define | RCC_HSI_OFF ((uint32_t)0x00000000)
#define | RCC_HSI_ON RCC_CR_HSION
#define | RCC_HSI_DIV1 (RCC_CR_HSIDIV_1 | RCC_CR_HSION)
#define | RCC_HSI_DIV2 (RCC_CR_HSIDIV_2 | RCC_CR_HSION)
#define | RCC_HSI_DIV4 (RCC_CR_HSIDIV_4 | RCC_CR_HSION)
#define | RCC_HSI_DIV8 (RCC_CR_HSIDIV | RCC_CR_HSION)
#define | RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x20U) /* Default HSI calibration trimming value */
#define | RCC_HSI48_OFF ((uint8_t)0x00)
#define | RCC_HSI48_ON ((uint8_t)0x01)
#define | RCC_LSI_OFF ((uint32_t)0x00000000)
#define | RCC_LSI_ON RCC_CSR_LSION
#define | RCC_CSI_OFF ((uint32_t)0x00000000)
#define | RCC_CSI_ON RCC_CR_CSION
#define | RCC_CSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default CSI calibration trimming value */
#define | RCC_PLL_NONE ((uint32_t)0x00000000)
#define | RCC_PLL_OFF ((uint32_t)0x00000001)
#define | RCC_PLL_ON ((uint32_t)0x00000002)
#define | RCC_PLLSOURCE_HSI ((uint32_t)0x00000000)
#define | RCC_PLLSOURCE_CSI ((uint32_t)0x00000001)
#define | RCC_PLLSOURCE_HSE ((uint32_t)0x00000002)
#define | RCC_PLLSOURCE_NONE ((uint32_t)0x00000003)
#define | RCC_PLL1_DIVP RCC_PLLCFGR_DIVP1EN
#define | RCC_PLL1_DIVQ RCC_PLLCFGR_DIVQ1EN
#define | RCC_PLL1_DIVR RCC_PLLCFGR_DIVR1EN
#define | RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0
#define | RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1
#define | RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2
#define | RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3
#define | RCC_PLL1VCOWIDE ((uint32_t)0x00000000)
#define | RCC_PLL1VCOMEDIUM RCC_PLLCFGR_PLL1VCOSEL
#define | RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
#define | RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
#define | RCC_CLOCKTYPE_D1PCLK1 ((uint32_t)0x00000004)
#define | RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000008)
#define | RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000010)
#define | RCC_CLOCKTYPE_D3PCLK1 ((uint32_t)0x00000020)
#define | RCC_SYSCLKSOURCE_CSI RCC_CFGR_SW_CSI
#define | RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL1
#define | RCC_SYSCLK_DIV1 RCC_D1CFGR_D1CPRE_DIV1
#define | RCC_SYSCLK_DIV2 RCC_D1CFGR_D1CPRE_DIV2
#define | RCC_SYSCLK_DIV4 RCC_D1CFGR_D1CPRE_DIV4
#define | RCC_SYSCLK_DIV8 RCC_D1CFGR_D1CPRE_DIV8
#define | RCC_SYSCLK_DIV16 RCC_D1CFGR_D1CPRE_DIV16
#define | RCC_SYSCLK_DIV64 RCC_D1CFGR_D1CPRE_DIV64
#define | RCC_SYSCLK_DIV128 RCC_D1CFGR_D1CPRE_DIV128
#define | RCC_SYSCLK_DIV256 RCC_D1CFGR_D1CPRE_DIV256
#define | RCC_SYSCLK_DIV512 RCC_D1CFGR_D1CPRE_DIV512
#define | RCC_HCLK_DIV1 RCC_D1CFGR_HPRE_DIV1
#define | RCC_HCLK_DIV2 RCC_D1CFGR_HPRE_DIV2
#define | RCC_HCLK_DIV4 RCC_D1CFGR_HPRE_DIV4
#define | RCC_HCLK_DIV8 RCC_D1CFGR_HPRE_DIV8
#define | RCC_HCLK_DIV16 RCC_D1CFGR_HPRE_DIV16
#define | RCC_HCLK_DIV64 RCC_D1CFGR_HPRE_DIV64
#define | RCC_HCLK_DIV128 RCC_D1CFGR_HPRE_DIV128
#define | RCC_HCLK_DIV256 RCC_D1CFGR_HPRE_DIV256
#define | RCC_HCLK_DIV512 RCC_D1CFGR_HPRE_DIV512
#define | RCC_APB3_DIV1 RCC_D1CFGR_D1PPRE_DIV1
#define | RCC_APB3_DIV2 RCC_D1CFGR_D1PPRE_DIV2
#define | RCC_APB3_DIV4 RCC_D1CFGR_D1PPRE_DIV4
#define | RCC_APB3_DIV8 RCC_D1CFGR_D1PPRE_DIV8
#define | RCC_APB3_DIV16 RCC_D1CFGR_D1PPRE_DIV16
#define | RCC_APB1_DIV1 RCC_D2CFGR_D2PPRE1_DIV1
#define | RCC_APB1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2
#define | RCC_APB1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4
#define | RCC_APB1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8
#define | RCC_APB1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16
#define | RCC_APB2_DIV1 RCC_D2CFGR_D2PPRE2_DIV1
#define | RCC_APB2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2
#define | RCC_APB2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4
#define | RCC_APB2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8
#define | RCC_APB2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16
#define | RCC_APB4_DIV1 RCC_D3CFGR_D3PPRE_DIV1
#define | RCC_APB4_DIV2 RCC_D3CFGR_D3PPRE_DIV2
#define | RCC_APB4_DIV4 RCC_D3CFGR_D3PPRE_DIV4
#define | RCC_APB4_DIV8 RCC_D3CFGR_D3PPRE_DIV8
#define | RCC_APB4_DIV16 RCC_D3CFGR_D3PPRE_DIV16
#define | RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)
#define | RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)
#define | RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00002300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00003300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00004300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00005300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00006300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00007300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00008300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00009300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x0000A300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x0000B300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x0000C300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x0000D300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x0000E300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x0000F300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00010300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00011300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00012300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00013300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00014300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00015300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00016300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00017300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00018300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00019300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x0001A300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x0001B300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x0001C300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x0001D300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x0001E300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x0001F300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV32 ((uint32_t)0x00020300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV33 ((uint32_t)0x00021300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV34 ((uint32_t)0x00022300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV35 ((uint32_t)0x00023300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV36 ((uint32_t)0x00024300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV37 ((uint32_t)0x00025300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV38 ((uint32_t)0x00026300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV39 ((uint32_t)0x00027300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV40 ((uint32_t)0x00028300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV41 ((uint32_t)0x00029300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV42 ((uint32_t)0x0002A300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV43 ((uint32_t)0x0002B300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV44 ((uint32_t)0x0002C300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV45 ((uint32_t)0x0002D300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV46 ((uint32_t)0x0002E300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV47 ((uint32_t)0x0002F300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV48 ((uint32_t)0x00030300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV49 ((uint32_t)0x00031300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV50 ((uint32_t)0x00032300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV51 ((uint32_t)0x00033300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV52 ((uint32_t)0x00034300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV53 ((uint32_t)0x00035300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV54 ((uint32_t)0x00036300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV55 ((uint32_t)0x00037300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV56 ((uint32_t)0x00038300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV57 ((uint32_t)0x00039300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV58 ((uint32_t)0x0003A300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV59 ((uint32_t)0x0003B300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV60 ((uint32_t)0x0003C300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV61 ((uint32_t)0x0003D300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV62 ((uint32_t)0x0003E300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV63 ((uint32_t)0x0003F300U)
#define | RCC_MCO1 ((uint32_t)0x00000000)
#define | RCC_MCO2 ((uint32_t)0x00000001)
#define | RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
#define | RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
#define | RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
#define | RCC_MCO1SOURCE_PLL1QCLK ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1)
#define | RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO1_2
#define | RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
#define | RCC_MCO2SOURCE_PLL2PCLK RCC_CFGR_MCO2_0
#define | RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
#define | RCC_MCO2SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1)
#define | RCC_MCO2SOURCE_CSICLK RCC_CFGR_MCO2_2
#define | RCC_MCO2SOURCE_LSICLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2)
#define | RCC_MCODIV_1 RCC_CFGR_MCO1PRE_0
#define | RCC_MCODIV_2 RCC_CFGR_MCO1PRE_1
#define | RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
#define | RCC_MCODIV_4 RCC_CFGR_MCO1PRE_2
#define | RCC_MCODIV_5 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
#define | RCC_MCODIV_6 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
#define | RCC_MCODIV_7 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
#define | RCC_MCODIV_8 RCC_CFGR_MCO1PRE_3
#define | RCC_MCODIV_9 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_10 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_11 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_12 ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_13 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_14 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
#define | RCC_MCODIV_15 RCC_CFGR_MCO1PRE
#define | RCC_IT_LSIRDY ((uint32_t)0x00000001)
#define | RCC_IT_LSERDY ((uint32_t)0x00000002)
#define | RCC_IT_HSIRDY ((uint32_t)0x00000004)
#define | RCC_IT_HSERDY ((uint32_t)0x00000008)
#define | RCC_IT_CSIRDY ((uint32_t)0x00000010)
#define | RCC_IT_HSI48RDY ((uint32_t)0x00000020)
#define | RCC_IT_PLLRDY ((uint32_t)0x00000040)
#define | RCC_IT_PLL2RDY ((uint32_t)0x00000080)
#define | RCC_IT_PLL3RDY ((uint32_t)0x00000100)
#define | RCC_IT_LSECSS ((uint32_t)0x00000200)
#define | RCC_IT_CSS ((uint32_t)0x00000400)
#define | RCC_FLAG_HSIRDY ((uint8_t)0x22)
#define | RCC_FLAG_HSIDIV ((uint8_t)0x25)
#define | RCC_FLAG_CSIRDY ((uint8_t)0x28)
#define | RCC_FLAG_HSI48RDY ((uint8_t)0x2D)
#define | RCC_FLAG_D1CKRDY ((uint8_t)0x2E)
#define | RCC_FLAG_D2CKRDY ((uint8_t)0x2F)
#define | RCC_FLAG_HSERDY ((uint8_t)0x31)
#define | RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define | RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
#define | RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
#define | RCC_FLAG_LSERDY ((uint8_t)0x41)
#define | RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define | RCC_FLAG_RMVF ((uint8_t)0x90)
#define | RCC_FLAG_CPURST ((uint8_t)0x91)
#define | RCC_FLAG_D1RST ((uint8_t)0x93)
#define | RCC_FLAG_D2RST ((uint8_t)0x94)
#define | RCC_FLAG_BORRST ((uint8_t)0x95)
#define | RCC_FLAG_PINRST ((uint8_t)0x96)
#define | RCC_FLAG_PORRST ((uint8_t)0x97)
#define | RCC_FLAG_SFTRST ((uint8_t)0x98)
#define | RCC_FLAG_IWDG1RST ((uint8_t)0x9A)
#define | RCC_FLAG_WWDG1RST ((uint8_t)0x9C)
#define | RCC_FLAG_LPWR1RST ((uint8_t)0x9E)
#define | RCC_FLAG_LPWR2RST ((uint8_t)0x9F)
#define | RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)
#define | RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
#define | RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
#define | RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
#define | RCC_STOP_WAKEUPCLOCK_HSI ((uint32_t)0x00000000)
#define | RCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR_STOPWUCK
#define | RCC_STOP_KERWAKEUPCLOCK_HSI ((uint32_t)0x00000000)
#define | RCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR_STOPKERWUCK
#define | __HAL_RCC_MDMA_CLK_ENABLE()
Enable or disable the AHB3 peripheral clock.
#define | __HAL_RCC_DMA2D_CLK_ENABLE()
#define | __HAL_RCC_JPGDECEN_CLK_ENABLE()
#define | __HAL_RCC_FLASH_CLK_ENABLE()
#define | __HAL_RCC_FMC_CLK_ENABLE()
#define | __HAL_RCC_QSPI_CLK_ENABLE()
#define | __HAL_RCC_SDMMC1_CLK_ENABLE()
#define | __HAL_RCC_MDMA_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
#define | __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
#define | __HAL_RCC_JPGDECEN_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
#define | __HAL_RCC_FLASH_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FLASHEN))
#define | __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
#define | __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
#define | __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
#define | __HAL_RCC_DMA1_CLK_ENABLE()
Enable or disable the AHB1 peripheral clock.
#define | __HAL_RCC_DMA2_CLK_ENABLE()
#define | __HAL_RCC_ADC12_CLK_ENABLE()
#define | __HAL_RCC_ETH1MAC_CLK_ENABLE()
#define | __HAL_RCC_ETH1TX_CLK_ENABLE()
#define | __HAL_RCC_ETH1RX_CLK_ENABLE()
#define | __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
#define | __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
#define | __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
#define | __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
#define | __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
#define | __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
#define | __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
#define | __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
#define | __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
#define | __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
#define | __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
#define | __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
#define | __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
#define | __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
#define | __HAL_RCC_DCMI_CLK_ENABLE()
Enable or disable the AHB2 peripheral clock.
#define | __HAL_RCC_CRYP_CLK_ENABLE()
#define | __HAL_RCC_HASH_CLK_ENABLE()
#define | __HAL_RCC_RNG_CLK_ENABLE()
#define | __HAL_RCC_SDMMC2_CLK_ENABLE()
#define | __HAL_RCC_D2SRAM1_CLK_ENABLE()
#define | __HAL_RCC_D2SRAM2_CLK_ENABLE()
#define | __HAL_RCC_D2SRAM3_CLK_ENABLE()
#define | __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
#define | __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
#define | __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
#define | __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
#define | __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
#define | __HAL_RCC_D2SRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
#define | __HAL_RCC_D2SRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
#define | __HAL_RCC_D2SRAM3_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
#define | __HAL_RCC_GPIOA_CLK_ENABLE()
Enable or disable the AHB4 peripheral clock.
#define | __HAL_RCC_GPIOB_CLK_ENABLE()
#define | __HAL_RCC_GPIOC_CLK_ENABLE()
#define | __HAL_RCC_GPIOD_CLK_ENABLE()
#define | __HAL_RCC_GPIOE_CLK_ENABLE()
#define | __HAL_RCC_GPIOF_CLK_ENABLE()
#define | __HAL_RCC_GPIOG_CLK_ENABLE()
#define | __HAL_RCC_GPIOH_CLK_ENABLE()
#define | __HAL_RCC_GPIOI_CLK_ENABLE()
#define | __HAL_RCC_GPIOJ_CLK_ENABLE()
#define | __HAL_RCC_GPIOK_CLK_ENABLE()
#define | __HAL_RCC_CRC_CLK_ENABLE()
#define | __HAL_RCC_BDMA_CLK_ENABLE()
#define | __HAL_RCC_ADC3_CLK_ENABLE()
#define | __HAL_RCC_HSEM_CLK_ENABLE()
#define | __HAL_RCC_BKPRAM_CLK_ENABLE()
#define | __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
#define | __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
#define | __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
#define | __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
#define | __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
#define | __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
#define | __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
#define | __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
#define | __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
#define | __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
#define | __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
#define | __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
#define | __HAL_RCC_BDMA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
#define | __HAL_RCC_ADC3_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
#define | __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
#define | __HAL_RCC_BKPRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
#define | __HAL_RCC_LTDC_CLK_ENABLE()
Enable or disable the APB3 peripheral clock.
#define | __HAL_RCC_WWDG1_CLK_ENABLE()
#define | __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
#define | __HAL_RCC_WWDG1_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
#define | __HAL_RCC_TIM2_CLK_ENABLE()
Enable or disable the APB1 peripheral clock.
#define | __HAL_RCC_TIM3_CLK_ENABLE()
#define | __HAL_RCC_TIM4_CLK_ENABLE()
#define | __HAL_RCC_TIM5_CLK_ENABLE()
#define | __HAL_RCC_TIM6_CLK_ENABLE()
#define | __HAL_RCC_TIM7_CLK_ENABLE()
#define | __HAL_RCC_TIM12_CLK_ENABLE()
#define | __HAL_RCC_TIM13_CLK_ENABLE()
#define | __HAL_RCC_TIM14_CLK_ENABLE()
#define | __HAL_RCC_LPTIM1_CLK_ENABLE()
#define | __HAL_RCC_SPI2_CLK_ENABLE()
#define | __HAL_RCC_SPI3_CLK_ENABLE()
#define | __HAL_RCC_SPDIFRX_CLK_ENABLE()
#define | __HAL_RCC_USART2_CLK_ENABLE()
#define | __HAL_RCC_USART3_CLK_ENABLE()
#define | __HAL_RCC_UART4_CLK_ENABLE()
#define | __HAL_RCC_UART5_CLK_ENABLE()
#define | __HAL_RCC_I2C1_CLK_ENABLE()
#define | __HAL_RCC_I2C2_CLK_ENABLE()
#define | __HAL_RCC_I2C3_CLK_ENABLE()
#define | __HAL_RCC_CEC_CLK_ENABLE()
#define | __HAL_RCC_DAC12_CLK_ENABLE()
#define | __HAL_RCC_UART7_CLK_ENABLE()
#define | __HAL_RCC_UART8_CLK_ENABLE()
#define | __HAL_RCC_CRS_CLK_ENABLE()
#define | __HAL_RCC_SWPMI1_CLK_ENABLE()
#define | __HAL_RCC_OPAMP_CLK_ENABLE()
#define | __HAL_RCC_MDIOS_CLK_ENABLE()
#define | __HAL_RCC_FDCAN_CLK_ENABLE()
#define | __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
#define | __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
#define | __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
#define | __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
#define | __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
#define | __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
#define | __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
#define | __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
#define | __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
#define | __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
#define | __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
#define | __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
#define | __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
#define | __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
#define | __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
#define | __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
#define | __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
#define | __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
#define | __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
#define | __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
#define | __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
#define | __HAL_RCC_DAC12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
#define | __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
#define | __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
#define | __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
#define | __HAL_RCC_SWPMI1_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
#define | __HAL_RCC_OPAMP_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
#define | __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
#define | __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
#define | __HAL_RCC_TIM1_CLK_ENABLE()
Enable or disable the APB2 peripheral clock.
#define | __HAL_RCC_TIM8_CLK_ENABLE()
#define | __HAL_RCC_USART1_CLK_ENABLE()
#define | __HAL_RCC_USART6_CLK_ENABLE()
#define | __HAL_RCC_SPI1_CLK_ENABLE()
#define | __HAL_RCC_SPI4_CLK_ENABLE()
#define | __HAL_RCC_TIM15_CLK_ENABLE()
#define | __HAL_RCC_TIM16_CLK_ENABLE()
#define | __HAL_RCC_TIM17_CLK_ENABLE()
#define | __HAL_RCC_SPI5_CLK_ENABLE()
#define | __HAL_RCC_SAI1_CLK_ENABLE()
#define | __HAL_RCC_SAI2_CLK_ENABLE()
#define | __HAL_RCC_SAI3_CLK_ENABLE()
#define | __HAL_RCC_DFSDM1_CLK_ENABLE()
#define | __HAL_RCC_HRTIM1_CLK_ENABLE()
#define | __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
#define | __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
#define | __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
#define | __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
#define | __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
#define | __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
#define | __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
#define | __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
#define | __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
#define | __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
#define | __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
#define | __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
#define | __HAL_RCC_SAI3_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
#define | __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
#define | __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
#define | __HAL_RCC_SYSCFG_CLK_ENABLE()
Enable or disable the APB4 peripheral clock.
#define | __HAL_RCC_LPUART1_CLK_ENABLE()
#define | __HAL_RCC_SPI6_CLK_ENABLE()
#define | __HAL_RCC_I2C4_CLK_ENABLE()
#define | __HAL_RCC_LPTIM2_CLK_ENABLE()
#define | __HAL_RCC_LPTIM3_CLK_ENABLE()
#define | __HAL_RCC_LPTIM4_CLK_ENABLE()
#define | __HAL_RCC_LPTIM5_CLK_ENABLE()
#define | __HAL_RCC_COMP12_CLK_ENABLE()
#define | __HAL_RCC_VREF_CLK_ENABLE()
#define | __HAL_RCC_SAI4_CLK_ENABLE()
#define | __HAL_RCC_RTC_CLK_ENABLE()
#define | __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
#define | __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
#define | __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
#define | __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
#define | __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
#define | __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
#define | __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
#define | __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
#define | __HAL_RCC_COMP12_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
#define | __HAL_RCC_VREF_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
#define | __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
#define | __HAL_RCC_SAI4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
#define | __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
Enable or disable the AHB3 peripheral reset.
#define | __HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))
#define | __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))
#define | __HAL_RCC_JPGDECRST_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST))
#define | __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
#define | __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
#define | __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST))
#define | __HAL_RCC_CPU_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_CPURST))
#define | __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
#define | __HAL_RCC_MDMA_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))
#define | __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))
#define | __HAL_RCC_JPGDECRST_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST))
#define | __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))
#define | __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST))
#define | __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))
#define | __HAL_RCC_CPU_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_CPURST))
#define | __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
Force or release the AHB1 peripheral reset.
#define | __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
#define | __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
#define | __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST))
#define | __HAL_RCC_ETH1MAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST))
#define | __HAL_RCC_USB1_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST))
#define | __HAL_RCC_USB2_OTG_FS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST))
#define | __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
#define | __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST))
#define | __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST))
#define | __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST))
#define | __HAL_RCC_ETH1MAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST))
#define | __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST))
#define | __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST))
#define | __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
Force or release the AHB2 peripheral reset.
#define | __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
#define | __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
#define | __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
#define | __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
#define | __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))
#define | __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
#define | __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST))
#define | __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST))
#define | __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST))
#define | __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))
#define | __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))
#define | __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0xFFFFFFFF)
Force or release the AHB4 peripheral reset.
#define | __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST)
#define | __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST)
#define | __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST)
#define | __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST)
#define | __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST)
#define | __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST)
#define | __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST)
#define | __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST)
#define | __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST)
#define | __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST)
#define | __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST)
#define | __HAL_RCC_PWR_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_PWRRST)
#define | __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST)
#define | __HAL_RCC_BDMA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST)
#define | __HAL_RCC_ADC3_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST)
#define | __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST)
#define | __HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTR = 0x00)
#define | __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST)
#define | __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST)
#define | __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST)
#define | __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST)
#define | __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST)
#define | __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)
#define | __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)
#define | __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)
#define | __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST)
#define | __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)
#define | __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)
#define | __HAL_RCC_PWR_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_PWRRST)
#define | __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST)
#define | __HAL_RCC_BDMA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST)
#define | __HAL_RCC_ADC3_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST)
#define | __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST)
#define | __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0xFFFFFFFF)
Force or release the APB3 peripheral reset.
#define | __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST)
#define | __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTR = 0x00)
#define | __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST)
#define | __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xFFFFFFFF)
Force or release the APB1 peripheral reset.
#define | __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0xFFFFFFFF)
#define | __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST)
#define | __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST)
#define | __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST)
#define | __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST)
#define | __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST)
#define | __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST)
#define | __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST)
#define | __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST)
#define | __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST)
#define | __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST)
#define | __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST)
#define | __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST)
#define | __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST)
#define | __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST)
#define | __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST)
#define | __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST)
#define | __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST)
#define | __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST)
#define | __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST)
#define | __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST)
#define | __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST)
#define | __HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST)
#define | __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST)
#define | __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST)
#define | __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST)
#define | __HAL_RCC_SWPMI1_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST)
#define | __HAL_RCC_OPAMP_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST)
#define | __HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST)
#define | __HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST)
#define | __HAL_RCC_APB1L_RELEASE_RESET() (RCC->APB1LRSTR = 0x00)
#define | __HAL_RCC_APB1H_RELEASE_RESET() (RCC->APB1HRSTR = 0x00)
#define | __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST)
#define | __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST)
#define | __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST)
#define | __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST)
#define | __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST)
#define | __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST)
#define | __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST)
#define | __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST)
#define | __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST)
#define | __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST)
#define | __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST)
#define | __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST)
#define | __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST)
#define | __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)
#define | __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST)
#define | __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST)
#define | __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST)
#define | __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)
#define | __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)
#define | __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)
#define | __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)
#define | __HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)
#define | __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)
#define | __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST)
#define | __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST)
#define | __HAL_RCC_SWPMI1_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST)
#define | __HAL_RCC_OPAMP_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)
#define | __HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)
#define | __HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)
#define | __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Force or release the APB2 peripheral reset.
#define | __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST)
#define | __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST)
#define | __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST)
#define | __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST)
#define | __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST)
#define | __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST)
#define | __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST)
#define | __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST)
#define | __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST)
#define | __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST)
#define | __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST)
#define | __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST)
#define | __HAL_RCC_SAI3_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST)
#define | __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST)
#define | __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST)
#define | __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
#define | __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST)
#define | __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST)
#define | __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST)
#define | __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST)
#define | __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST)
#define | __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST)
#define | __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST)
#define | __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST)
#define | __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)
#define | __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)
#define | __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)
#define | __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST)
#define | __HAL_RCC_SAI3_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST)
#define | __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST)
#define | __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST)
#define | __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0xFFFFFFFF)
Force or release the APB4 peripheral reset.
#define | __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST)
#define | __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST)
#define | __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST)
#define | __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST)
#define | __HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST)
#define | __HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST)
#define | __HAL_RCC_LPTIM4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST)
#define | __HAL_RCC_LPTIM5_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST)
#define | __HAL_RCC_COMP12_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST)
#define | __HAL_RCC_VREF_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST)
#define | __HAL_RCC_SAI4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST)
#define | __HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTR = 0x00)
#define | __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST)
#define | __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST)
#define | __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST)
#define | __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST)
#define | __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST)
#define | __HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST)
#define | __HAL_RCC_LPTIM4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST)
#define | __HAL_RCC_LPTIM5_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST)
#define | __HAL_RCC_COMP12_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST)
#define | __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST)
#define | __HAL_RCC_SAI4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST)
#define | __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
#define | __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
#define | __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
#define | __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
#define | __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
#define | __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
#define | __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
#define | __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
#define | __HAL_RCC_ITCM_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
#define | __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
#define | __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
#define | __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
#define | __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
#define | __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
#define | __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
#define | __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
#define | __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
#define | __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
#define | __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
#define | __HAL_RCC_ITCM_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
#define | __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
#define | __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
#define | __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
#define | __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
#define | __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
#define | __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
#define | __HAL_RCC_ETH1PTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1PTPLPEN))
#define | __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
#define | __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
#define | __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
#define | __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
#define | __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
#define | __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
#define | __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
#define | __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
#define | __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
#define | __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
#define | __HAL_RCC_ETH1PTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1PTPLPEN))
#define | __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
#define | __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
#define | __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
#define | __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
#define | __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
#define | __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
#define | __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
#define | __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
#define | __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
#define | __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
#define | __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
#define | __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
#define | __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
#define | __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
#define | __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
#define | __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
#define | __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
#define | __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
#define | __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
#define | __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
#define | __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
#define | __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
#define | __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
#define | __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
#define | __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
#define | __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
#define | __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_PWRLPEN)
#define | __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
#define | __HAL_RCC_BDMA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
#define | __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
#define | __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
#define | __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN))
#define | __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
#define | __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
#define | __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
#define | __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
#define | __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
#define | __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
#define | __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
#define | __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
#define | __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_PWRLPEN)
#define | __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
#define | __HAL_RCC_BDMA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
#define | __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
#define | __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
#define | __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
#define | __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
#define | __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
#define | __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
#define | __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
#define | __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
#define | __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
#define | __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
#define | __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
#define | __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
#define | __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
#define | __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
#define | __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
#define | __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
#define | __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
#define | __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
#define | __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
#define | __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
#define | __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
#define | __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
#define | __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
#define | __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
#define | __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
#define | __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
#define | __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
#define | __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
#define | __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
#define | __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
#define | __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
#define | __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
#define | __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
#define | __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
#define | __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
#define | __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
#define | __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
#define | __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
#define | __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
#define | __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
#define | __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
#define | __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
#define | __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
#define | __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
#define | __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
#define | __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
#define | __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
#define | __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
#define | __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
#define | __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
#define | __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
#define | __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
#define | __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
#define | __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
#define | __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
#define | __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
#define | __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
#define | __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
#define | __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
#define | __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
#define | __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
#define | __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
#define | __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
#define | __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
#define | __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
#define | __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
#define | __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
#define | __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
#define | __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
#define | __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
#define | __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
#define | __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
#define | __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
#define | __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
#define | __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
#define | __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
#define | __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
#define | __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
#define | __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
#define | __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
#define | __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
#define | __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
#define | __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
#define | __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
#define | __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
#define | __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
#define | __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
#define | __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
#define | __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
#define | __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
#define | __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
#define | __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
#define | __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
#define | __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
#define | __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
#define | __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
#define | __HAL_RCC_COMP12_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
#define | __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
#define | __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
#define | __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
#define | __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
#define | __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
#define | __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
#define | __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
#define | __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
#define | __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
#define | __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
#define | __HAL_RCC_COMP12_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
#define | __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
#define | __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
#define | __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
#define | __HAL_RCC_BDMA_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN)
Enable or disable peripheral bus clock when D3 domain is in DRUN.
#define | __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN)
#define | __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN)
#define | __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN)
#define | __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN)
#define | __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN)
#define | __HAL_RCC_LPTIM4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN)
#define | __HAL_RCC_LPTIM5_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN)
#define | __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN)
#define | __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN)
#define | __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN)
#define | __HAL_RCC_CRC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN)
#define | __HAL_RCC_SAI4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN)
#define | __HAL_RCC_ADC3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN)
#define | __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN)
#define | __HAL_RCC_D3SRAM1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN)
#define | __HAL_RCC_BDMA_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN)
#define | __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN)
#define | __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN)
#define | __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN)
#define | __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN)
#define | __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN)
#define | __HAL_RCC_LPTIM4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN)
#define | __HAL_RCC_LPTIM5_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN)
#define | __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN)
#define | __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN)
#define | __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_RTCAMEN)
#define | __HAL_RCC_CRC_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_CRCAMEN)
#define | __HAL_RCC_SAI4_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_SAI4AMEN)
#define | __HAL_RCC_ADC3_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_ADC3AMEN)
#define | __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN)
#define | __HAL_RCC_D3SRAM1_CLKAM_DISABLE() (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN)
#define | __HAL_RCC_HSI_CONFIG(__STATE__) MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__))
Macro to enable or disable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))
Macro to get the HSI divider.
#define | __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
Macros to enable or disable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
#define | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_ICSCR_HSITRIM))
Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
#define | __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for some peripherals.
#define | __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
#define | __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON);
Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
#define | __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
#define | __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION)
Macros to enable or disable the Internal oscillator (CSI).
#define | __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION)
#define | __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) MODIFY_REG(RCC->ICSCR, RCC_ICSCR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << POSITION_VAL(RCC_ICSCR_CSITRIM))
Macro Adjusts the Internal oscillator (CSI) calibration value.
#define | __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON)
Macros to enable or disable the force of the Low-power Internal oscillator (CSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
#define | __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)
#define | __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
Macros to enable or disable the Internal Low Speed oscillator (LSI).
#define | __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
#define | __HAL_RCC_HSE_CONFIG(__STATE__)
Macro to configure the External High Speed oscillator (__HSE__).
#define | __HAL_RCC_LSE_CONFIG(__STATE__)
Macro to configure the External Low Speed oscillator (LSE).
#define | __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Macros to enable or disable the the RTC clock.
#define | __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
#define | __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__)
Macros to configure the RTC clock (RTCCLK).
#define | __HAL_RCC_RTC_CONFIG(__RTCCLKSource__)
#define | __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
#define | __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Macros to force or release the Backup domain reset.
#define | __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
#define | __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON)
Macros to enable or disable the main PLL.
#define | __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)
#define | __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)
#define | __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
#define | __HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO.
#define | __HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
#define | __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__, __PLLR1__)
Macro to configures the main PLL clock source, multiplication and division factors.
#define | __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))
Macro to configure the PLLs clock source.
#define | __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << POSITION_VAL(RCC_PLL1FRACR_FRACN1))
Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor.
#define | __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))
Macro to select the PLL1 reference frequency range.
#define | __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))
Macro to select the PLL1 reference frequency range.
#define | __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Macro to get the clock source used as system clock.
#define | __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
Macro to configure the system clock source.
#define | __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))
Macro to get the oscillator used as PLL clock source.
#define | __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
Macro to configure the External Low Speed oscillator (LSE) drive capability.
#define | __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))
Macro to configure the wake up from stop clock.
#define | __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))
Macro to configure the Kernel wake up from stop clock.
#define | __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
Enable RCC interrupt.
#define | __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
Disable RCC interrupt.
#define | __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
Clear the RCC's interrupt pending bits.
#define | __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
Check the RCC's interrupt has occurred or not.
#define | __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF)
Set RMVF bit to clear the reset flags.
#define | RCC_FLAG_MASK ((uint8_t)0x1F)
Check RCC flag is set or not.
#define | __HAL_RCC_GET_FLAG(__FLAG__)
#define | RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> POSITION_VAL(RCC_PLLCKSELR_PLLSRC))
#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define | HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define | HSI48_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define | CSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define | LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define | PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define | CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
#define | RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
#define | RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
#define | IS_RCC_OSCILLATORTYPE(OSCILLATOR)
#define | IS_RCC_HSE(HSE)
#define | IS_RCC_LSE(LSE)
#define | IS_RCC_HSI(HSI)
#define | IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
#define | IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
#define | IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON))
#define | IS_RCC_PLL(PLL)
#define | IS_RCC_PLLSOURCE(SOURCE)
#define | IS_RCC_PLLM_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 63))
#define | IS_RCC_PLLN_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512))
#define | IS_RCC_PLLP_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
#define | IS_RCC_PLLQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
#define | IS_RCC_PLLR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
#define | IS_RCC_PLLCLOCKOUT_VALUE(VALUE)
#define | IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 0x3F))
#define | IS_RCC_SYSCLKSOURCE(SOURCE)
#define | IS_RCC_SYSCLK(SYSCLK)
#define | IS_RCC_HCLK(HCLK)
#define | IS_RCC_D1PCLK1(D1PCLK1)
#define | IS_RCC_PCLK1(PCLK1)
#define | IS_RCC_PCLK2(PCLK2)
#define | IS_RCC_D3PCLK1(D3PCLK1)
#define | IS_RCC_RTCCLKSOURCE(SOURCE)
#define | IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
#define | IS_RCC_MCO1SOURCE(SOURCE)
#define | IS_RCC_MCO2SOURCE(SOURCE)
#define | IS_RCC_MCODIV(DIV)
#define | IS_RCC_FLAG(FLAG)
#define | IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0xFFF)
#define | IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
#define | IS_RCC_STOP_WAKEUPCLOCK(SOURCE)
#define | IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE)

Functions

void | HAL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
__weak HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initializes the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.
void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
void | HAL_RCC_EnableCSS (void)
Enables the Clock Security System.
void | HAL_RCC_DisableCSS (void)
uint32_t | HAL_RCC_GetSysClockFreq (void)
Returns the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Returns the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Returns the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Returns the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
This function handles the RCC CSS interrupt request.
void | HAL_RCC_CCSCallback (void)
RCC Clock Security System interrupt callback.

Detailed Description

Header file of RCC HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_rcc.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_rcc_ex.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_hal_rcc_ex.h File Reference

Header file of RCC HAL Extension module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RCC_PLL2InitTypeDef
PLL2 Clock structure definition. More...
struct | RCC_PLL3InitTypeDef
PLL3 Clock structure definition. More...
struct | PLL1_ClocksTypeDef
RCC PLL1 Clocks structure definition. More...
struct | PLL2_ClocksTypeDef
RCC PLL2 Clocks structure definition. More...
struct | PLL3_ClocksTypeDef
RCC PLL3 Clocks structure definition. More...
struct | RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition. More...
struct | RCC_CRSInitTypeDef
RCC_CRS Init structure definition. More...
struct | RCC_CRSSynchroInfoTypeDef
RCC_CRS Synchronization structure definition. More...

Defines

#define | RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
#define | RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
#define | RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
#define | RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
#define | RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
#define | RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000020)
#define | RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000040)
#define | RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000080)
#define | RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
#define | RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000200)
#define | RCC_PERIPHCLK_LPTIM2 ((uint32_t)0x00000400)
#define | RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000800)
#define | RCC_PERIPHCLK_SAI2 ((uint32_t)0x00001000)
#define | RCC_PERIPHCLK_USB ((uint32_t)0x00002000)
#define | RCC_PERIPHCLK_ADC ((uint32_t)0x00004000)
#define | RCC_PERIPHCLK_SWPMI1 ((uint32_t)0x00008000)
#define | RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x00010000)
#define | RCC_PERIPHCLK_RTC ((uint32_t)0x00020000)
#define | RCC_PERIPHCLK_CEC ((uint32_t)0x00040000)
#define | RCC_PERIPHCLK_USART6 ((uint32_t)0x00080000)
#define | RCC_PERIPHCLK_UART7 ((uint32_t)0x00100000)
#define | RCC_PERIPHCLK_UART8 ((uint32_t)0x00200000)
#define | RCC_PERIPHCLK_I2C4 ((uint32_t)0x00400000)
#define | RCC_PERIPHCLK_LPTIM3 ((uint32_t)0x00800000)
#define | RCC_PERIPHCLK_LPTIM4 ((uint32_t)0x01000000)
#define | RCC_PERIPHCLK_LPTIM5 ((uint32_t)0x02000000)
#define | RCC_PERIPHCLK_SAI3 ((uint32_t)0x04000000)
#define | RCC_PERIPHCLK_SAI4A ((uint32_t)0x08000000)
#define | RCC_PERIPHCLK_SAI4B ((uint32_t)0x10000000)
#define | RCC_PERIPHCLK_FMC ((uint32_t)0x20000000)
#define | RCC_PERIPHCLK_QSPI ((uint32_t)0x40000000)
#define | RCC_PERIPHCLK_DSI ((uint32_t)0x80000000)
#define | RCC_PERIPHCLK_CKPER ((uint32_t)0x80000001)
#define | RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x80000002)
#define | RCC_PERIPHCLK_FDCAN ((uint32_t)0x80000004)
#define | RCC_PERIPHCLK_SPI1 ((uint32_t)0x80000008)
#define | RCC_PERIPHCLK_SPI2 ((uint32_t)0x80000010)
#define | RCC_PERIPHCLK_SPI3 ((uint32_t)0x80000020)
#define | RCC_PERIPHCLK_SPI4 ((uint32_t)0x80000040)
#define | RCC_PERIPHCLK_SPI5 ((uint32_t)0x80000080)
#define | RCC_PERIPHCLK_SPI6 ((uint32_t)0x80000100)
#define | RCC_PERIPHCLK_SDMMC ((uint32_t)0x80000200)
#define | RCC_PERIPHCLK_LTDC ((uint32_t)0x80000400)
#define | RCC_PERIPHCLK_RNG ((uint32_t)0x80000800)
#define | RCC_PERIPHCLK_HRTIM1 ((uint32_t)0x80001000)
#define | RCC_PERIPHCLK_TIM ((uint32_t)0x80002000)
#define | RCC_PLL2_DIVP RCC_PLLCFGR_DIVP2EN
#define | RCC_PLL2_DIVQ RCC_PLLCFGR_DIVQ2EN
#define | RCC_PLL2_DIVR RCC_PLLCFGR_DIVR2EN
#define | RCC_PLL3_DIVP RCC_PLLCFGR_DIVP3EN
#define | RCC_PLL3_DIVQ RCC_PLLCFGR_DIVQ3EN
#define | RCC_PLL3_DIVR RCC_PLLCFGR_DIVR3EN
#define | RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0
#define | RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1
#define | RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2
#define | RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3
#define | RCC_PLL2VCOWIDE ((uint32_t)0x00000000)
#define | RCC_PLL2VCOMEDIUM RCC_PLLCFGR_PLL2VCOSEL
#define | RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0
#define | RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1
#define | RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2
#define | RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3
#define | RCC_PLL3VCOWIDE ((uint32_t)0x00000000)
#define | RCC_PLL3VCOMEDIUM RCC_PLLCFGR_PLL3VCOSEL
#define | RCC_USART1CLKSOURCE_D2PCLK2 ((uint32_t)0x00000000)
#define | RCC_USART1CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16SEL_0
#define | RCC_USART1CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16SEL_1
#define | RCC_USART1CLKSOURCE_HSI (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
#define | RCC_USART1CLKSOURCE_CSI RCC_D2CCIP2R_USART16SEL_2
#define | RCC_USART1CLKSOURCE_LSE (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
#define | RCC_USART2CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_USART2CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0
#define | RCC_USART2CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1
#define | RCC_USART2CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
#define | RCC_USART2CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2
#define | RCC_USART2CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
#define | RCC_USART3CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_USART3CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0
#define | RCC_USART3CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1
#define | RCC_USART3CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
#define | RCC_USART3CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2
#define | RCC_USART3CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
#define | RCC_UART4CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_UART4CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0
#define | RCC_UART4CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1
#define | RCC_UART4CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
#define | RCC_UART4CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2
#define | RCC_UART4CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
#define | RCC_UART5CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_UART5CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0
#define | RCC_UART5CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1
#define | RCC_UART5CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
#define | RCC_UART5CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2
#define | RCC_UART5CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
#define | RCC_USART6CLKSOURCE_D2PCLK2 ((uint32_t)0x00000000)
#define | RCC_USART6CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16SEL_0
#define | RCC_USART6CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16SEL_1
#define | RCC_USART6CLKSOURCE_HSI (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
#define | RCC_USART6CLKSOURCE_CSI RCC_D2CCIP2R_USART16SEL_2
#define | RCC_USART6CLKSOURCE_LSE (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
#define | RCC_UART7CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_UART7CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0
#define | RCC_UART7CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1
#define | RCC_UART7CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
#define | RCC_UART7CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2
#define | RCC_UART7CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
#define | RCC_UART8CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_UART8CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0
#define | RCC_UART8CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1
#define | RCC_UART8CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
#define | RCC_UART8CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2
#define | RCC_UART8CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
#define | RCC_LPUART1CLKSOURCE_D3PCLK1 ((uint32_t)0x00000000)
#define | RCC_LPUART1CLKSOURCE_PLL2 RCC_D3CCIPR_LPUART1SEL_0
#define | RCC_LPUART1CLKSOURCE_PLL3 RCC_D3CCIPR_LPUART1SEL_1
#define | RCC_LPUART1CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)
#define | RCC_LPUART1CLKSOURCE_CSI RCC_D3CCIPR_LPUART1SEL_2
#define | RCC_LPUART1CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0)
#define | RCC_I2C1CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_I2C1CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0
#define | RCC_I2C1CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1
#define | RCC_I2C1CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
#define | RCC_I2C2CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_I2C2CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0
#define | RCC_I2C2CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1
#define | RCC_I2C2CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
#define | RCC_I2C3CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_I2C3CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0
#define | RCC_I2C3CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1
#define | RCC_I2C3CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
#define | RCC_I2C4CLKSOURCE_D3PCLK1 ((uint32_t)0x00000000)
#define | RCC_I2C4CLKSOURCE_PLL3 RCC_D3CCIPR_I2C4SEL_0
#define | RCC_I2C4CLKSOURCE_HSI RCC_D3CCIPR_I2C4SEL_1
#define | RCC_I2C4CLKSOURCE_CSI (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)
#define | RCC_RNGCLKSOURCE_HSI48 ((uint32_t)0x00000000)
#define | RCC_RNGCLKSOURCE_PLL RCC_D2CCIP2R_RNGSEL_0
#define | RCC_RNGCLKSOURCE_LSE RCC_D2CCIP2R_RNGSEL_1
#define | RCC_RNGCLKSOURCE_LSI RCC_D2CCIP2R_RNGSEL
#define | RCC_HRTIM1CLK_TIMCLK ((uint32_t)0x00000000)
#define | RCC_HRTIM1CLK_CPUCLK RCC_CFGR_HRTIMSEL
#define | RCC_USBCLKSOURCE_PLL RCC_D2CCIP2R_USBSEL_0
#define | RCC_USBCLKSOURCE_PLL3 RCC_D2CCIP2R_USBSEL_1
#define | RCC_USBCLKSOURCE_HSI48 RCC_D2CCIP2R_USBSEL
#define | RCC_SAI1CLKSOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_SAI1CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI1SEL_0
#define | RCC_SAI1CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI1SEL_1
#define | RCC_SAI1CLKSOURCE_PIN (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)
#define | RCC_SAI1CLKSOURCE_CLKP RCC_D2CCIP1R_SAI1SEL_2
#define | RCC_SAI2CLKSOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_SAI2CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI23SEL_0
#define | RCC_SAI2CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI23SEL_1
#define | RCC_SAI2CLKSOURCE_PIN (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
#define | RCC_SAI2CLKSOURCE_CLKP RCC_D2CCIP1R_SAI23SEL_2
#define | RCC_SPI1CLKSOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_SPI1CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI123SEL_0
#define | RCC_SPI1CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI123SEL_1
#define | RCC_SPI1CLKSOURCE_PIN (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
#define | RCC_SPI1CLKSOURCE_CLKP RCC_D2CCIP1R_SPI123SEL_2
#define | RCC_SPI2CLKSOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_SPI2CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI123SEL
#define | RCC_SPI2CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI123SEL_1
#define | RCC_SPI2CLKSOURCE_PIN (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
#define | RCC_SPI2CLKSOURCE_CLKP RCC_D2CCIP1R_SPI123SEL_2
#define | RCC_SPI3CLKSOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_SPI3CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI123SEL
#define | RCC_SPI3CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI123SEL_1
#define | RCC_SPI3CLKSOURCE_PIN (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
#define | RCC_SPI3CLKSOURCE_CLKP RCC_D2CCIP1R_SPI123SEL_2
#define | RCC_SPI4CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_SPI4CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI45SEL_0
#define | RCC_SPI4CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI45SEL_1
#define | RCC_SPI4CLKSOURCE_HSI (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
#define | RCC_SPI4CLKSOURCE_CSI RCC_D2CCIP1R_SPI45SEL_2
#define | RCC_SPI4CLKSOURCE_HSE (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
#define | RCC_SPI5CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_SPI5CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI45SEL_0
#define | RCC_SPI5CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI45SEL_1
#define | RCC_SPI5CLKSOURCE_HSI (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
#define | RCC_SPI5CLKSOURCE_CSI RCC_D2CCIP1R_SPI45SEL_2
#define | RCC_SPI5CLKSOURCE_HSE (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
#define | RCC_SPI6CLKSOURCE_D3PCLK1 ((uint32_t)0x00000000)
#define | RCC_SPI6CLKSOURCE_PLL2 RCC_D3CCIPR_SPI6SEL_0
#define | RCC_SPI6CLKSOURCE_PLL3 RCC_D3CCIPR_SPI6SEL_1
#define | RCC_SPI6CLKSOURCE_HSI (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)
#define | RCC_SPI6CLKSOURCE_CSI RCC_D3CCIPR_SPI6SEL_2
#define | RCC_SPI6CLKSOURCE_HSE (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)
#define | RCC_SAI3CLKSOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_SAI3CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI23SEL_0
#define | RCC_SAI3CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI23SEL_1
#define | RCC_SAI3CLKSOURCE_PIN (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
#define | RCC_SAI3CLKSOURCE_CLKP RCC_D2CCIP1R_SAI23SEL_2
#define | RCC_SAI4ACLKSOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_SAI4ACLKSOURCE_PLL2 RCC_D3CCIPR_SAI4ASEL_0
#define | RCC_SAI4ACLKSOURCE_PLL3 RCC_D3CCIPR_SAI4ASEL_1
#define | RCC_SAI4ACLKSOURCE_PIN (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
#define | RCC_SAI4ACLKSOURCE_CLKP RCC_D3CCIPR_SAI4ASEL_2
#define | RCC_SAI4BCLKSOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_SAI4BCLKSOURCE_PLL2 RCC_D3CCIPR_SAI4BSEL_0
#define | RCC_SAI4BCLKSOURCE_PLL3 RCC_D3CCIPR_SAI4BSEL_1
#define | RCC_SAI4BCLKSOURCE_PIN (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
#define | RCC_SAI4BCLKSOURCE_CLKP RCC_D3CCIPR_SAI4BSEL_2
#define | RCC_LPTIM1CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_LPTIM1CLKSOURCE_PLL2 RCC_D2CCIP2R_LPTIM1SEL_0
#define | RCC_LPTIM1CLKSOURCE_PLL3 RCC_D2CCIP2R_LPTIM1SEL_1
#define | RCC_LPTIM1CLKSOURCE_LSE (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)
#define | RCC_LPTIM1CLKSOURCE_LSI RCC_D2CCIP2R_LPTIM1SEL_2
#define | RCC_LPTIM1CLKSOURCE_CLKP (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)
#define | RCC_LPTIM2CLKSOURCE_D3PCLK1 ((uint32_t)0x00000000)
#define | RCC_LPTIM2CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM2SEL_0
#define | RCC_LPTIM2CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM2SEL_1
#define | RCC_LPTIM2CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)
#define | RCC_LPTIM2CLKSOURCE_LSI RCC_D3CCIPR_LPTIM2SEL_2
#define | RCC_LPTIM2CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)
#define | RCC_LPTIM3CLKSOURCE_D3PCLK1 ((uint32_t)0x00000000)
#define | RCC_LPTIM3CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM345SEL_0
#define | RCC_LPTIM3CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM345SEL_1
#define | RCC_LPTIM3CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
#define | RCC_LPTIM3CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2
#define | RCC_LPTIM3CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
#define | RCC_LPTIM4CLKSOURCE_D3PCLK1 ((uint32_t)0x00000000)
#define | RCC_LPTIM4CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM345SEL_0
#define | RCC_LPTIM4CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM345SEL_1
#define | RCC_LPTIM4CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
#define | RCC_LPTIM4CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2
#define | RCC_LPTIM4CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
#define | RCC_LPTIM5CLKSOURCE_D3PCLK1 ((uint32_t)0x00000000)
#define | RCC_LPTIM5CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM345SEL_0
#define | RCC_LPTIM5CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM345SEL_1
#define | RCC_LPTIM5CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
#define | RCC_LPTIM5CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2
#define | RCC_LPTIM5CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
#define | RCC_QSPICLKSOURCE_D1HCLK ((uint32_t)0x00000000)
#define | RCC_QSPICLKSOURCE_PLL RCC_D1CCIPR_QSPISEL_0
#define | RCC_QSPICLKSOURCE_PLL2 RCC_D1CCIPR_QSPISEL_1
#define | RCC_QSPICLKSOURCE_CLKP RCC_D1CCIPR_QSPISEL
#define | RCC_FMCCLKSOURCE_D1HCLK ((uint32_t)0x00000000)
#define | RCC_FMCCLKSOURCE_PLL RCC_D1CCIPR_FMCSEL_0
#define | RCC_FMCCLKSOURCE_PLL2 RCC_D1CCIPR_FMCSEL_1
#define | RCC_FMCCLKSOURCE_CLKP RCC_D1CCIPR_FMCSEL
#define | RCC_FDCANCLKSOURCE_HSE ((uint32_t)0x00000000)
#define | RCC_FDCANCLKSOURCE_PLL RCC_D2CCIP1R_FDCANSEL_0
#define | RCC_FDCANCLKSOURCE_PLL2 RCC_D2CCIP1R_FDCANSEL_1
#define | RCC_SDMMCCLKSOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_SDMMCCLKSOURCE_PLL2 RCC_D1CCIPR_SDMMCSEL
#define | RCC_USBCLKSOURCE_PLL RCC_D2CCIP2R_USBSEL_0
#define | RCC_USBCLKSOURCE_PLL3 RCC_D2CCIP2R_USBSEL_1
#define | RCC_USBCLKSOURCE_HSI48 RCC_D2CCIP2R_USBSEL
#define | RCC_ADCCLKSOURCE_PLL2 ((uint32_t)0x00000000)
#define | RCC_ADCCLKSOURCE_PLL3 RCC_D3CCIPR_ADCSEL_0
#define | RCC_ADCCLKSOURCE_CLKP RCC_D3CCIPR_ADCSEL_1
#define | RCC_SWPMI1CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_SWPMI1CLKSOURCE_HSI RCC_D2CCIP1R_SWPSEL
#define | RCC_DFSDM1CLKSOURCE_D2PCLK1 ((uint32_t)0x00000000)
#define | RCC_DFSDM1CLKSOURCE_SYS RCC_D2CCIP1R_DFSDM1SEL
#define | RCC_SPDIFRXCLKSOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_SPDIFRXCLKSOURCE_PLL2 RCC_D2CCIP1R_SPDIFSEL_0
#define | RCC_SPDIFRXCLKSOURCE_PLL3 RCC_D2CCIP1R_SPDIFSEL_1
#define | RCC_SPDIFRXCLKSOURCE_HSI RCC_D2CCIP1R_SPDIFSEL
#define | RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000)
#define | RCC_CECCLKSOURCE_LSI RCC_D2CCIP2R_CECSEL_0
#define | RCC_CECCLKSOURCE_CSI RCC_D2CCIP2R_CECSEL_1
#define | RCC_CLKPSOURCE_HSI ((uint32_t)0x00000000)
#define | RCC_CLKPSOURCE_CSI RCC_D1CCIPR_CKPERSEL_0
#define | RCC_CLKPSOURCE_HSE RCC_D1CCIPR_CKPERSEL_1
#define | RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U)
#define | RCC_TIMPRES_ACTIVATED RCC_CFGR_TIMPRE
#define | RCC_WWDG1 RCC_GCR_WW1RSC
#define | RCC_CRS_NONE ((uint32_t)0x00000000U)
#define | RCC_CRS_TIMEOUT ((uint32_t)0x00000001U)
#define | RCC_CRS_SYNCOK ((uint32_t)0x00000002U)
#define | RCC_CRS_SYNCWARN ((uint32_t)0x00000004U)
#define | RCC_CRS_SYNCERR ((uint32_t)0x00000008U)
#define | RCC_CRS_SYNCMISS ((uint32_t)0x00000010U)
#define | RCC_CRS_TRIMOVF ((uint32_t)0x00000020U)
#define | RCC_CRS_SYNC_SOURCE_USB2 ((uint32_t)0x00000000U)
#define | RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0
#define | RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1
#define | RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U)
#define | RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0
#define | RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1
#define | RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)
#define | RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2
#define | RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)
#define | RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)
#define | RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV
#define | RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U)
#define | RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL
#define | RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU)
#define | RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U)
#define | RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U)
#define | RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U)
#define | RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR)
#define | RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE
#define | RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE
#define | RCC_CRS_IT_ERR CRS_CR_ERRIE
#define | RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE
#define | RCC_CRS_IT_SYNCERR CRS_CR_ERRIE
#define | RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE
#define | RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE
#define | RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF
#define | RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF
#define | RCC_CRS_FLAG_ERR CRS_ISR_ERRF
#define | RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF
#define | RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR
#define | RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS
#define | RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF
#define | __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON)
Macros to enable or disable PLL2.
#define | __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)
#define | __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)
#define | __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
#define | __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO.
#define | __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
#define | __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__)
Macro to configures the PLL2 multiplication and division factors.
#define | __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,(uint32_t)(__RCC_PLL2FRACN__) << POSITION_VAL(RCC_PLL2FRACR_FRACN2))
Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor.
#define | __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))
Macro to select the PLL2 reference frequency range.
#define | __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))
Macro to select the PLL2 reference frequency range.
#define | __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON)
Macros to enable or disable the main PLL3.
#define | __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)
#define | __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO.
#define | __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
#define | __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)
#define | __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
#define | __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__)
Macro to configures the PLL3 multiplication and division factors.
#define | __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << POSITION_VAL(RCC_PLL3FRACR_FRACN3))
Macro to configures PLL3 clock Fractional Part of The Multiplication Factor.
#define | __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))
Macro to select the PLL3 reference frequency range.
#define | __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))
Macro to select the PLL3 reference frequency range.
#define | __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
Macro to Configure the SAI1 clock source.
#define | __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL)))
Macro to get the SAI1 clock source.
#define | __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
Macro to Configure the SPDIFRX clock source.
#define | __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)))
Macro to get the SPDIFRX clock source.
#define | __HAL_RCC_SAI2_CONFIG(__RCC_SAI2CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI2CLKSource__))
Macro to Configure the SAI2 clock source.
#define | __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
Macro to get the SAI2 clock source.
#define | __HAL_RCC_SAI3_CONFIG(__RCC_SAI3CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI3CLKSource__))
Macro to Configure the SAI3 clock source.
#define | __HAL_RCC_GET_SAI3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
Macro to get the SAI3 clock source.
#define | __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))
Macro to Configure the SAI4A clock source.
#define | __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL)))
Macro to get the SAI4A clock source.
#define | __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))
Macro to Configure the SAI4B clock source.
#define | __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))
Macro to get the SAI4B clock source.
#define | __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1CLKSource__))
macro to configure the I2C1 clock (I2C1CLK).
#define | __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
macro to get the I2C1 clock source.
#define | __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C2CLKSource__))
macro to configure the I2C2 clock (I2C2CLK).
#define | __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
macro to get the I2C2 clock source.
#define | __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C3CLKSource__))
macro to configure the I2C3 clock (I2C3CLK).
#define | __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
macro to get the I2C3 clock source.
#define | __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
macro to configure the I2C4 clock (I2C4CLK).
#define | __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))
macro to get the I2C4 clock source.
#define | __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART1CLKSource__))
macro to configure the USART1 clock (USART1CLK).
#define | __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
macro to get the USART1 clock source.
#define | __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART2CLKSource__))
macro to configure the USART2 clock (USART2CLK).
#define | __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
macro to get the USART2 clock source.
#define | __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART3CLKSource__))
macro to configure the USART3 clock (USART3CLK).
#define | __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
macro to get the USART3 clock source.
#define | __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART4CLKSource__))
macro to configure the UART4 clock (UART4CLK).
#define | __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
macro to get the UART4 clock source.
#define | __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART5CLKSource__))
macro to configure the UART5 clock (UART5CLK).
#define | __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
macro to get the UART5 clock source.
#define | __HAL_RCC_USART6_CONFIG(__USART6CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART6CLKSource__))
macro to configure the USART6 clock (USART6CLK).
#define | __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
macro to get the USART6 clock source.
#define | __HAL_RCC_UART7_CONFIG(__UART7CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART7CLKSource__))
macro to configure the UART5 clock (UART7CLK).
#define | __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
macro to get the UART7 clock source.
#define | __HAL_RCC_UART8_CONFIG(__UART8CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART8CLKSource__))
macro to configure the UART8 clock (UART8CLK).
#define | __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
macro to get the UART8 clock source.
#define | __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
macro to configure the LPUART1 clock (LPUART1CLK).
#define | __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))
macro to get the LPUART1 clock source.
#define | __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
macro to get the LPTIM1 clock source.
#define | __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))
macro to get the LPTIM1 clock source.
#define | __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
macro to get the LPTIM2 clock source.
#define | __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))
macro to get the LPTIM2 clock source.
#define | __HAL_RCC_LPTIM3_CONFIG(__LPTIM3CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM3CLKSource__))
macro to get the LPTIM3 clock source.
#define | __HAL_RCC_GET_LPTIM3_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
macro to get the LPTIM3 clock source.
#define | __HAL_RCC_LPTIM4_CONFIG(__LPTIM4CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM4CLKSource__))
macro to get the LPTIM4 clock source.
#define | __HAL_RCC_GET_LPTIM4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
macro to get the LPTIM4 clock source.
#define | __HAL_RCC_LPTIM5_CONFIG(__LPTIM5CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM5CLKSource__))
macro to configure the LPTIM5 clock source.
#define | __HAL_RCC_GET_LPTIM5_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
macro to get the LPTIM5 clock source.
#define | __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__))
macro to configure the QSPI clock source.
#define | __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)))
macro to get the QSPI clock source.
#define | __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
macro to configure the FMC clock source.
#define | __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))
macro to get the FMC clock source.
#define | __HAL_RCC_USB_CONFIG(__USBCLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
Macro to configure the USB clock (USBCLK).
#define | __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)))
Macro to get the USB clock source.
#define | __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
Macro to configure the ADC clock.
#define | __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))
Macro to get the ADC clock source.
#define | __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
Macro to configure the SWPMI1 clock.
#define | __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))
Macro to get the SWPMI1 clock source.
#define | __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
Macro to configure the DFSDM1 clock.
#define | __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)))
Macro to get the DFSDM1 clock source.
#define | __HAL_RCC_CEC_CONFIG(__CECCLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
macro to configure the CEC clock (CECCLK).
#define | __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)))
macro to get the CEC clock source.
#define | __HAL_RCC_CLKP_CONFIG(__CLKPSource__) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
Macro to configure the CLKP : Oscillator clock for peripheral.
#define | __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)))
Macro to get the Oscillator clock for peripheral source.
#define | __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
Macro to configure the FDCAN clock.
#define | __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)))
Macro to get the FDCAN clock.
#define | __HAL_RCC_SPI1_CONFIG(__RCC_SPI1CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI1CLKSource__))
Macro to Configure the SPI1 clock source.
#define | __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
Macro to get the SPI1 clock source.
#define | __HAL_RCC_SPI2_CONFIG(__RCC_SPI2CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI2CLKSource__))
Macro to Configure the SPI2 clock source.
#define | __HAL_RCC_GET_SPI2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
Macro to get the SPI2 clock source.
#define | __HAL_RCC_SPI3_CONFIG(__RCC_SPI3CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI3CLKSource__))
Macro to Configure the SPI3 clock source.
#define | __HAL_RCC_GET_SPI3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
Macro to get the SPI3 clock source.
#define | __HAL_RCC_SPI4_CONFIG(__RCC_SPI4CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI4CLKSource__))
Macro to Configure the SPI4 clock source.
#define | __HAL_RCC_GET_SPI4_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
Macro to get the SPI4 clock source.
#define | __HAL_RCC_SPI5_CONFIG(__RCC_SPI5CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI5CLKSource__))
Macro to Configure the SPI5 clock source.
#define | __HAL_RCC_GET_SPI5_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
Macro to get the SPI5 clock source.
#define | __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
Macro to Configure the SPI6 clock source.
#define | __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))
Macro to get the SPI6 clock source.
#define | __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
Macro to configure the SDMMC clock.
#define | __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)))
Macro to get the SDMMC clock.
#define | __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
macro to configure the RNG clock (RNGCLK).
#define | __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)))
macro to get the RNG clock source.
#define | __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__))
Macro to configure the HRTIM1 prescaler clock source.
#define | __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)))
Macro to get the HRTIM1 clock source.
#define | __HAL_RCC_TIMCLKPRESCALER(__PRESC__)
Macro to configure the Timers clocks prescalers.
#define | __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
Enable the specified CRS interrupts.
#define | __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
Disable the specified CRS interrupts.
#define | __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the CRS interrupt has occurred or not.
#define | RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
Clear the CRS interrupt pending bits.
#define | __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)
#define | __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
Check whether the specified CRS flag is set or not.
#define | RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
Clear the CRS specified FLAG.
#define | __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)
#define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
Enable the oscillator clock for frequency error counter.
#define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
Disable the oscillator clock for frequency error counter.
#define | __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
Enable the automatic hardware adjustment of TRIM bits.
#define | __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
Enable or disable the automatic hardware adjustment of TRIM bits.
#define | __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
Macro to calculate reload value to be set in CRS register according to target and sync frequencies.
#define | IS_RCC_PERIPHCLOCK(SELECTION)
#define | IS_RCC_PLL2CLOCKOUT_VALUE(VALUE)
#define | IS_RCC_PLL3CLOCKOUT_VALUE(VALUE)
#define | IS_RCC_USART1CLKSOURCE(SOURCE)
#define | IS_RCC_USART2CLKSOURCE(SOURCE)
#define | IS_RCC_USART3CLKSOURCE(SOURCE)
#define | IS_RCC_UART4CLKSOURCE(SOURCE)
#define | IS_RCC_UART5CLKSOURCE(SOURCE)
#define | IS_RCC_USART6CLKSOURCE(SOURCE)
#define | IS_RCC_UART7CLKSOURCE(SOURCE)
#define | IS_RCC_UART8CLKSOURCE(SOURCE)
#define | IS_RCC_LPUART1CLKSOURCE(SOURCE)
#define | IS_RCC_I2C1CLKSOURCE(SOURCE)
#define | IS_RCC_I2C2CLKSOURCE(SOURCE)
#define | IS_RCC_I2C3CLKSOURCE(SOURCE)
#define | IS_RCC_I2C4CLKSOURCE(SOURCE)
#define | IS_RCC_RNGCLKSOURCE(SOURCE)
#define | IS_RCC_HRTIM1CLKSOURCE(SOURCE)
#define | IS_RCC_USBCLKSOURCE(SOURCE)
#define | IS_RCC_SAI1CLK(__SOURCE__)
#define | IS_RCC_SAI2CLK(__SOURCE__)
#define | IS_RCC_SPI1CLK(__SOURCE__)
#define | IS_RCC_SPI2CLK(__SOURCE__)
#define | IS_RCC_SPI3CLK(__SOURCE__)
#define | IS_RCC_SPI4CLK(__SOURCE__)
#define | IS_RCC_SPI5CLK(__SOURCE__)
#define | IS_RCC_SPI6CLK(__SOURCE__)
#define | IS_RCC_SAI3CLK(__SOURCE__)
#define | IS_RCC_SAI4ACLK(__SOURCE__)
#define | IS_RCC_SAI4BCLK(__SOURCE__)
#define | IS_RCC_PLL3M_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 63))
#define | IS_RCC_PLL3N_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512))
#define | IS_RCC_PLL3P_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
#define | IS_RCC_PLL3Q_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
#define | IS_RCC_PLL3R_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
#define | IS_RCC_PLL2M_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 63))
#define | IS_RCC_PLL2N_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512))
#define | IS_RCC_PLL2P_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
#define | IS_RCC_PLL2Q_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
#define | IS_RCC_PLL2R_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
#define | IS_RCC_LPTIM1CLK(SOURCE)
#define | IS_RCC_LPTIM2CLK(SOURCE)
#define | IS_RCC_LPTIM3CLK(SOURCE)
#define | IS_RCC_LPTIM4CLK(SOURCE)
#define | IS_RCC_LPTIM5CLK(SOURCE)
#define | IS_RCC_QSPICLK(__SOURCE__)
#define | IS_RCC_FMCCLK(__SOURCE__)
#define | IS_RCC_FDCANCLK(__SOURCE__)
#define | IS_RCC_SDMMC(__SOURCE__)
#define | IS_RCC_USBCLKSOURCE(SOURCE)
#define | IS_RCC_ADCCLKSOURCE(SOURCE)
#define | IS_RCC_SWPMI1CLKSOURCE(SOURCE)
#define | IS_RCC_DFSDM1CLKSOURCE(SOURCE)
#define | IS_RCC_SPDIFRXCLKSOURCE(SOURCE)
#define | IS_RCC_CECCLKSOURCE(SOURCE)
#define | IS_RCC_CLKPSOURCE(SOURCE)
#define | IS_RCC_TIMPRES(VALUE)
#define | IS_RCC_SCOPE_WWDG(WWDG) ((WWDG) == RCC_WWDG1)
#define | IS_RCC_CRS_SYNC_SOURCE(__SOURCE__)
#define | IS_RCC_CRS_SYNC_DIV(__DIV__)
#define | IS_RCC_CRS_SYNC_POLARITY(__POLARITY__)
#define | IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
#define | IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
#define | IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
#define | IS_RCC_CRS_FREQERRORDIR(__DIR__)

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Return the peripheral clock frequency for a given peripheral(SAI..)
uint32_t | HAL_RCCEx_GetD1PCLK1Freq (void)
Returns the D1PCLK1 frequency.
uint32_t | HAL_RCCEx_GetD3PCLK1Freq (void)
Returns the D3PCLK1 frequency.
uint32_t | HAL_RCCEx_GetD1SysClockFreq (void)
Returns the main Core frequency.
void | HAL_RCCEx_GetPLL1ClockFreq (PLL1_ClocksTypeDef *PLL1_Clocks)
Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency.
void | HAL_RCCEx_GetPLL2ClockFreq (PLL2_ClocksTypeDef *PLL2_Clocks)
Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency.
void | HAL_RCCEx_GetPLL3ClockFreq (PLL3_ClocksTypeDef *PLL3_Clocks)
Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency.
void | HAL_RCCEx_WakeUpStopCLKConfig (uint32_t WakeUpClk)
Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
void | HAL_RCCEx_KerWakeUpStopCLKConfig (uint32_t WakeUpClk)
Configure the oscillator Kernel clock source for wakeup from Stop.
void | HAL_RCCEx_EnableLSECSS (void)
Enables the LSE Clock Security System.
void | HAL_RCCEx_DisableLSECSS (void)
Disables the LSE Clock Security System.
void | HAL_RCCEx_WWDGxSysResetConfig (uint32_t RCC_WWDGx)
Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs.
void | HAL_RCCEx_CRSConfig (RCC_CRSInitTypeDef *pInit)
Start automatic synchronization for polling mode.
void | HAL_RCCEx_CRSSoftwareSynchronizationGenerate (void)
Generate the software synchronization event.
void | HAL_RCCEx_CRSGetSynchronizationInfo (RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
Return synchronization info.
uint32_t | HAL_RCCEx_CRSWaitSynchronization (uint32_t Timeout)
Wait for CRS Synchronization status.
void | HAL_RCCEx_CRS_IRQHandler (void)
Handle the Clock Recovery System interrupt request.
__weak void | HAL_RCCEx_CRS_SyncOkCallback (void)
RCCEx Clock Recovery System SYNCOK interrupt callback.
__weak void | HAL_RCCEx_CRS_SyncWarnCallback (void)
RCCEx Clock Recovery System SYNCWARN interrupt callback.
__weak void | HAL_RCCEx_CRS_ExpectedSyncCallback (void)
RCCEx Clock Recovery System Expected SYNC interrupt callback.
__weak void | HAL_RCCEx_CRS_ErrorCallback (uint32_t Error)
RCCEx Clock Recovery System Error interrupt callback.

Detailed Description

Header file of RCC HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_rcc_ex.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_rng.h File Reference

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stm32h7xx_hal_rng.h File Reference

Header file of RNG HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RNG_InitTypeDef
struct | RNG_HandleTypeDef

Defines

#define | RNG_IT_DRDY RNG_SR_DRDY
#define | RNG_IT_CEI RNG_SR_CEIS
#define | RNG_IT_SEI RNG_SR_SEIS
#define | RNG_FLAG_DRDY RNG_SR_DRDY
#define | RNG_FLAG_CECS RNG_SR_CECS
#define | RNG_FLAG_SECS RNG_SR_SECS
#define | RNG_CED_ENABLE ((uint32_t)0x00000000)
#define | RNG_CED_DISABLE RNG_CR_CED
#define | __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
Reset RNG handle state.
#define | __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
Enables the RNG peripheral.
#define | __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
Disables the RNG peripheral.
#define | __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check the selected RNG flag status.
#define | __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
Clears the selected RNG flag status.
#define | __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
Enables the RNG interrupts.
#define | __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
Disables the RNG interrupts.
#define | __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks whether the specified RNG interrupt has occurred or not.
#define | __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
Clear the RNG interrupt status flags.
#define | IS_RNG_IT(IT)
#define | IS_RNG_FLAG(FLAG)
#define | IS_RNG_CED(CED)

Enumerations

enum HAL_RNG_StateTypeDef {
HAL_RNG_STATE_RESET = 0x00U, HAL_RNG_STATE_READY = 0x01U, HAL_RNG_STATE_BUSY = 0x02U, HAL_RNG_STATE_TIMEOUT = 0x03U,
HAL_RNG_STATE_ERROR = 0x04U
}

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initializes the RNG peripheral and creates the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initializes the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG MSP.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generates a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generates a 32-bit random number in interrupt mode.
uint32_t | HAL_RNG_ReadLastRandomNumber (RNG_HandleTypeDef *hrng)
Read latest generated random number.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handles RNG interrupt request.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callbacks.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
HAL_RNG_StateTypeDef | HAL_RNG_GetState (RNG_HandleTypeDef *hrng)
Returns the RNG state.

Detailed Description

Header file of RNG HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_rng.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_rtc.h File Reference

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stm32h7xx_hal_rtc.h File Reference

Header file of RTC HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_rtc_ex.h"

Go to the source code of this file.

Data Structures

struct | RTC_InitTypeDef
RTC Configuration Structure definition. More...
struct | RTC_TimeTypeDef
RTC Time structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | RTC_HandleTypeDef
Time Handle Structure definition. More...

Defines

#define | RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
#define | RTC_HOURFORMAT_12 ((uint32_t)0x00000040)
#define | RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
#define | RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)
#define | RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
#define | RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE)
#define | RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000)
#define | RTC_OUTPUT_REMAP_POS1 ((uint32_t)RTC_OR_OUT_RMP)
#define | RTC_HOURFORMAT12_AM ((uint8_t)0x00)
#define | RTC_HOURFORMAT12_PM ((uint8_t)0x40)
#define | RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)
#define | RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)
#define | RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)
#define | RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
#define | RTC_STOREOPERATION_SET ((uint32_t)0x00040000)
#define | RTC_FORMAT_BIN ((uint32_t)0x000000000)
#define | RTC_FORMAT_BCD ((uint32_t)0x000000001)
#define | RTC_MONTH_JANUARY ((uint8_t)0x01)
#define | RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define | RTC_MONTH_MARCH ((uint8_t)0x03)
#define | RTC_MONTH_APRIL ((uint8_t)0x04)
#define | RTC_MONTH_MAY ((uint8_t)0x05)
#define | RTC_MONTH_JUNE ((uint8_t)0x06)
#define | RTC_MONTH_JULY ((uint8_t)0x07)
#define | RTC_MONTH_AUGUST ((uint8_t)0x08)
#define | RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
#define | RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define | RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define | RTC_MONTH_DECEMBER ((uint8_t)0x12)
#define | RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define | RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define | RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
#define | RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
#define | RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define | RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define | RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
#define | RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
#define | RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)
#define | RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
#define | RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define | RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define | RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define | RTC_ALARMMASK_ALL ((uint32_t)0x80808080)
#define | RTC_ALARM_A RTC_CR_ALRAE
#define | RTC_ALARM_B RTC_CR_ALRBE
#define | RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000)
#define | RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000)
#define | RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000)
#define | RTC_IT_TS ((uint32_t)RTC_CR_TSIE)
#define | RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE)
#define | RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE)
#define | RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE)
#define | RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE)
#define | RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE)
#define | RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE)
#define | RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE)
#define | RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF)
#define | RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F)
#define | RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F)
#define | RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F)
#define | RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF)
#define | RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF)
#define | RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF)
#define | RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF)
#define | RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF)
#define | RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF)
#define | RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF)
#define | RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF)
#define | RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS)
#define | RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF)
#define | RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF)
#define | RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF)
#define | RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF)
#define | __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
Reset RTC handle state.
#define | __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)
Disable the write protection for RTC registers.
#define | __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)
Enable the write protection for RTC registers.
#define | __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
Enable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
Disable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
Enable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
Disable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
Check whether the specified RTC Alarm interrupt has occurred or not.
#define | __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC Alarm's flag status.
#define | __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Alarm's pending flags.
#define | __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Alarm interrupt is enabled or not.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI_D1->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI_D1->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI_D1->PR1 & RTC_EXTI_LINE_ALARM_EVENT)
Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI_D1->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))
Clear the RTC Alarm associated Exti line flag.
#define | __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)
Generate a Software interrupt on RTC Alarm associated Exti line.
#define | RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
#define | RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
#define | RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)
#define | RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU)
#define | RTC_TIMEOUT_VALUE 1000
#define | RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000)
#define | IS_RTC_HOUR_FORMAT(FORMAT)
#define | IS_RTC_OUTPUT_POL(POL)
#define | IS_RTC_OUTPUT_TYPE(TYPE)
#define | IS_RTC_OUTPUT_REMAP(REMAP)
#define | IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
#define | IS_RTC_DAYLIGHT_SAVING(SAVE)
#define | IS_RTC_STORE_OPERATION(OPERATION)
#define | IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
#define | IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
#define | IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
#define | IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
#define | IS_RTC_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
#define | IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL)
#define | IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
#define | IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
#define | IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
#define | IS_RTC_ALARM_SUB_SECOND_MASK(MASK)
#define | IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
#define | IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF)
#define | IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
#define | IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
#define | IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
#define | IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)

Enumerations

enum HAL_RTCStateTypeDef {
HAL_RTC_STATE_RESET = 0x00, HAL_RTC_STATE_READY = 0x01, HAL_RTC_STATE_BUSY = 0x02, HAL_RTC_STATE_TIMEOUT = 0x03,
HAL_RTC_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initialize the RTC according to the specified parameters in the RTC_InitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC peripheral.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initialize the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC MSP.
HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Set RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Get RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Set RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Get RTC current date.
HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Get the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Alarm interrupt request.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle AlarmA Polling request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.
HAL_RTCStateTypeDef | HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Return the RTC handle state.
HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enter the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.

Detailed Description

Header file of RTC HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_rtc.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_rtc_ex.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_hal_rtc_ex.h File Reference

Header file of RTC HAL Extension module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RTC_TamperTypeDef
RTC Tamper structure definition. More...

Defines

#define | RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)
#define | RTC_OUTPUT_ALARMA ((uint32_t)0x00200000)
#define | RTC_OUTPUT_ALARMB ((uint32_t)0x00400000)
#define | RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000)
#define | RTC_BKP_DR0 ((uint32_t)0x00000000)
#define | RTC_BKP_DR1 ((uint32_t)0x00000001)
#define | RTC_BKP_DR2 ((uint32_t)0x00000002)
#define | RTC_BKP_DR3 ((uint32_t)0x00000003)
#define | RTC_BKP_DR4 ((uint32_t)0x00000004)
#define | RTC_BKP_DR5 ((uint32_t)0x00000005)
#define | RTC_BKP_DR6 ((uint32_t)0x00000006)
#define | RTC_BKP_DR7 ((uint32_t)0x00000007)
#define | RTC_BKP_DR8 ((uint32_t)0x00000008)
#define | RTC_BKP_DR9 ((uint32_t)0x00000009)
#define | RTC_BKP_DR10 ((uint32_t)0x0000000A)
#define | RTC_BKP_DR11 ((uint32_t)0x0000000B)
#define | RTC_BKP_DR12 ((uint32_t)0x0000000C)
#define | RTC_BKP_DR13 ((uint32_t)0x0000000D)
#define | RTC_BKP_DR14 ((uint32_t)0x0000000E)
#define | RTC_BKP_DR15 ((uint32_t)0x0000000F)
#define | RTC_BKP_DR16 ((uint32_t)0x00000010)
#define | RTC_BKP_DR17 ((uint32_t)0x00000011)
#define | RTC_BKP_DR18 ((uint32_t)0x00000012)
#define | RTC_BKP_DR19 ((uint32_t)0x00000013)
#define | RTC_BKP_DR20 ((uint32_t)0x00000014)
#define | RTC_BKP_DR21 ((uint32_t)0x00000015)
#define | RTC_BKP_DR22 ((uint32_t)0x00000016)
#define | RTC_BKP_DR23 ((uint32_t)0x00000017)
#define | RTC_BKP_DR24 ((uint32_t)0x00000018)
#define | RTC_BKP_DR25 ((uint32_t)0x00000019)
#define | RTC_BKP_DR26 ((uint32_t)0x0000001A)
#define | RTC_BKP_DR27 ((uint32_t)0x0000001B)
#define | RTC_BKP_DR28 ((uint32_t)0x0000001C)
#define | RTC_BKP_DR29 ((uint32_t)0x0000001D)
#define | RTC_BKP_DR30 ((uint32_t)0x0000001E)
#define | RTC_BKP_DR31 ((uint32_t)0x0000001F)
#define | RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)
#define | RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008)
#define | RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)
#define | RTC_TAMPER_1 RTC_TAMPCR_TAMP1E
#define | RTC_TAMPER_2 RTC_TAMPCR_TAMP2E
#define | RTC_TAMPER_3 RTC_TAMPCR_TAMP3E
#define | RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE
#define | RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE
#define | RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE
#define | RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE
#define | RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)
#define | RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002)
#define | RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define | RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
#define | RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000)
#define | RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000)
#define | RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000)
#define | RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000)
#define | RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000)
#define | RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800)
#define | RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000)
#define | RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700)
#define | RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000)
#define | RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000)
#define | RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000)
#define | RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000)
#define | RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAMPCR_TAMPTS)
#define | RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000)
#define | RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000)
#define | RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003)
#define | RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004)
#define | RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006)
#define | RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000)
#define | RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000)
#define | RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000)
#define | RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000)
#define | RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000)
#define | RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)
#define | RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000)
#define | RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)
#define | RTC_SHIFTADD1S_SET ((uint32_t)0x80000000)
#define | __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
Enable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
Disable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Wake Up timer interrupt is enabled or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC WakeUpTimer's flag status.
#define | __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Wake Up timer's pending flags.
#define | __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))
Enable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
Disable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))
Enable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
Disable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))
Enable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
Disable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
Enable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
Disable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified RTC Tamper interrupt has occurred or not.
#define | __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Tamper interrupt is enabled or not.
#define | __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC Tamper's flag status.
#define | __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Tamper's pending flags.
#define | __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
Enable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
Disable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
Check whether the specified RTC TimeStamp interrupt has occurred or not.
#define | __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Time Stamp interrupt is enabled or not.
#define | __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC TimeStamp's flag status.
#define | __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Time Stamp's pending flags.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
Enable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
Disable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC Internal Time Stamp's flag status.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Internal Time Stamp's pending flags.
#define | __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
Enable the RTC calibration output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
Disable the calibration output.
#define | __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
Enable the clock reference detection.
#define | __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
Disable the clock reference detection.
#define | __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC shift operation's flag status.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI_D1->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI_D1->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTID3_ENABLE_EVENT() (EXTI->D3PMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated D3 Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTID3_DISABLE_EVENT() (EXTI->D3PMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated D3 Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI_D1->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI_D1->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the RTC WakeUp Timer associated Exti line flag.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI_D1->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI_D1->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTID3_GET_FLAG() (EXTI_D3->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the RTC WakeUp Timer associated D3 Exti line interrupt flag is set or not.
#define | __HAL_RTC_WAKEUPTIMER_EXTID3_CLEAR_FLAG() (EXTI_D3->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the RTC WakeUp Timer associated D3 Exti line flag.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI_D1->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI_D1->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Clear the RTC Tamper and Timestamp associated Exti line flag.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00040000)
#define | RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00080000)
#define | RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))
#define | RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))
#define | IS_RTC_OUTPUT(OUTPUT)
#define | IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
#define | IS_TIMESTAMP_EDGE(EDGE)
#define | IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXE))) == 0x00U) && ((__TAMPER__) != (uint32_t)RESET))
#define | IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & (uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXIE)) == 0x00U) && ((__INTERRUPT__) != (uint32_t)RESET))
#define | IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
#define | IS_RTC_TAMPER_TRIGGER(TRIGGER)
#define | IS_RTC_TAMPER_ERASE_MODE(MODE)
#define | IS_RTC_TAMPER_MASKFLAG_STATE(STATE)
#define | IS_RTC_TAMPER_FILTER(FILTER)
#define | IS_RTC_TAMPER_SAMPLING_FREQ(FREQ)
#define | IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION)
#define | IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION)
#define | IS_RTC_TAMPER_PULLUP_STATE(STATE)
#define | IS_RTC_WAKEUP_CLOCK(CLOCK)
#define | IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
#define | IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD)
#define | IS_RTC_SMOOTH_CALIB_PLUS(PLUS)
#define | IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
#define | IS_RTC_SHIFT_ADD1S(SEL)
#define | IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
#define | IS_RTC_CALIB_OUTPUT(OUTPUT)

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Set Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Get the RTC TimeStamp value.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivate Tamper.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
Handle TimeStamp interrupt request.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper2 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper3Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper3 Polling.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer with interrupt.
uint32_t | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivate wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Get wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Wake Up Timer Polling.
void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Write a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Read data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
Set the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configure the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disable the Bypass Shadow feature.
__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Alarm B Polling request.

Detailed Description

Header file of RTC HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_rtc_ex.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sai.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_sai.h File Reference

Header file of SAI HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_sai_ex.h"

Go to the source code of this file.

Data Structures

struct | SAI_PdmInitTypeDef
struct | SAI_InitTypeDef
struct | SAI_FrameInitTypeDef
struct | SAI_SlotInitTypeDef
struct | __SAI_HandleTypeDef

Defines

#define | HAL_SAI_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_SAI_ERROR_OVR ((uint32_t)0x00000001U)
#define | HAL_SAI_ERROR_UDR ((uint32_t)0x00000002U)
#define | HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004U)
#define | HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008U)
#define | HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U)
#define | HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020U)
#define | HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U)
#define | HAL_SAI_ERROR_DMA ((uint32_t)0x00000080U)
#define | SAI_SYNCEXT_DISABLE 0
#define | SAI_SYNCEXT_OUTBLOCKA_ENABLE 1
#define | SAI_SYNCEXT_OUTBLOCKB_ENABLE 2
#define | SAI_I2S_STANDARD 0
#define | SAI_I2S_MSBJUSTIFIED 1
#define | SAI_I2S_LSBJUSTIFIED 2
#define | SAI_PCM_LONG 3
#define | SAI_PCM_SHORT 4
#define | SAI_PROTOCOL_DATASIZE_16BIT 0
#define | SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1
#define | SAI_PROTOCOL_DATASIZE_24BIT 2
#define | SAI_PROTOCOL_DATASIZE_32BIT 3
#define | SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000U)
#define | SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000U)
#define | SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000U)
#define | SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100U)
#define | SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000U)
#define | SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050U)
#define | SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000U)
#define | SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025U)
#define | SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000U)
#define | SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0U)
#define | SAI_MCK_OVERSAMPLING_DISABLE ((uint32_t)0x00000000U)
#define | SAI_MCK_OVERSAMPLING_ENABLE ((uint32_t)SAI_xCR1_OSR)
#define | SAI_PDM_CLOCK1_ENABLE ((uint32_t)SAI_PDMCR_CKEN1)
#define | SAI_PDM_CLOCK2_ENABLE ((uint32_t)SAI_PDMCR_CKEN2)
#define | SAI_PDM_CLOCK3_ENABLE ((uint32_t)SAI_PDMCR_CKEN3)
#define | SAI_PDM_CLOCK4_ENABLE ((uint32_t)SAI_PDMCR_CKEN4)
#define | SAI_MODEMASTER_TX ((uint32_t)0x00000000U)
#define | SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0)
#define | SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1)
#define | SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))
#define | SAI_FREE_PROTOCOL ((uint32_t)0x00000000U)
#define | SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0)
#define | SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1)
#define | SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1)
#define | SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
#define | SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2)
#define | SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
#define | SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
#define | SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
#define | SAI_FIRSTBIT_MSB ((uint32_t)0x00000000U)
#define | SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST)
#define | SAI_CLOCKSTROBING_FALLINGEDGE 0
#define | SAI_CLOCKSTROBING_RISINGEDGE 1
#define | SAI_ASYNCHRONOUS 0
#define | SAI_SYNCHRONOUS 1
#define | SAI_SYNCHRONOUS_EXT_SAI1 2
#define | SAI_SYNCHRONOUS_EXT_SAI2 3
#define | SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000U)
#define | SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV)
#define | SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000U)
#define | SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NOMCK)
#define | SAI_FS_STARTFRAME ((uint32_t)0x00000000U)
#define | SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF)
#define | SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000U)
#define | SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPOL)
#define | SAI_FS_FIRSTBIT ((uint32_t)0x00000000U)
#define | SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF)
#define | SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000U)
#define | SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
#define | SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
#define | SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000U)
#define | SAI_SLOTACTIVE_0 ((uint32_t)0x00000001U)
#define | SAI_SLOTACTIVE_1 ((uint32_t)0x00000002U)
#define | SAI_SLOTACTIVE_2 ((uint32_t)0x00000004U)
#define | SAI_SLOTACTIVE_3 ((uint32_t)0x00000008U)
#define | SAI_SLOTACTIVE_4 ((uint32_t)0x00000010U)
#define | SAI_SLOTACTIVE_5 ((uint32_t)0x00000020U)
#define | SAI_SLOTACTIVE_6 ((uint32_t)0x00000040U)
#define | SAI_SLOTACTIVE_7 ((uint32_t)0x00000080U)
#define | SAI_SLOTACTIVE_8 ((uint32_t)0x00000100U)
#define | SAI_SLOTACTIVE_9 ((uint32_t)0x00000200U)
#define | SAI_SLOTACTIVE_10 ((uint32_t)0x00000400U)
#define | SAI_SLOTACTIVE_11 ((uint32_t)0x00000800U)
#define | SAI_SLOTACTIVE_12 ((uint32_t)0x00001000U)
#define | SAI_SLOTACTIVE_13 ((uint32_t)0x00002000U)
#define | SAI_SLOTACTIVE_14 ((uint32_t)0x00004000U)
#define | SAI_SLOTACTIVE_15 ((uint32_t)0x00008000U)
#define | SAI_SLOTACTIVE_ALL ((uint32_t)0x0000FFFFU)
#define | SAI_STEREOMODE ((uint32_t)0x00000000U)
#define | SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)
#define | SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000U)
#define | SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS)
#define | SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000U)
#define | SAI_FIFOTHRESHOLD_1QF ((uint32_t)(SAI_xCR2_FTH_0))
#define | SAI_FIFOTHRESHOLD_HF ((uint32_t)(SAI_xCR2_FTH_1))
#define | SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
#define | SAI_FIFOTHRESHOLD_FULL ((uint32_t)(SAI_xCR2_FTH_2))
#define | SAI_NOCOMPANDING ((uint32_t)0x00000000U)
#define | SAI_ULAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1))
#define | SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
#define | SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
#define | SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))
#define | SAI_ZERO_VALUE ((uint32_t)0x00000000U)
#define | SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL)
#define | SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)
#define | SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)
#define | SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)
#define | SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)
#define | SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)
#define | SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)
#define | SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)
#define | SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)
#define | SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)
#define | SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)
#define | SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)
#define | SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)
#define | SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)
#define | SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)
#define | SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000U)
#define | SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000U)
#define | SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000U)
#define | SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000U)
#define | SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000U)
#define | SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000U)
#define | __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
Reset SAI handle state.
#define | __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
Enable or disable the specified SAI interrupts.
#define | __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
#define | __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SAI interrupt source is enabled or not.
#define | __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SAI flag is set or not.
#define | __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
Clear the specified SAI pending flag.
#define | __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
#define | __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
#define | IS_SAI_BLOCK_SYNCEXT(STATE)
#define | IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)
#define | IS_SAI_PROTOCOL_DATASIZE(DATASIZE)
#define | IS_SAI_AUDIO_FREQUENCY(AUDIO)
#define | IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE)
#define | IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 4U))
#define | IS_SAI_PDM_CLOCK_ENABLE(CLOCK)
#define | IS_SAI_BLOCK_MODE(MODE)
#define | IS_SAI_BLOCK_PROTOCOL(PROTOCOL)
#define | IS_SAI_BLOCK_DATASIZE(DATASIZE)
#define | IS_SAI_BLOCK_FIRST_BIT(BIT)
#define | IS_SAI_BLOCK_CLOCK_STROBING(CLOCK)
#define | IS_SAI_BLOCK_SYNCHRO(SYNCHRO)
#define | IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE)
#define | IS_SAI_BLOCK_NODIVIDER(NODIVIDER)
#define | IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
#define | IS_SAI_BLOCK_MUTE_VALUE(VALUE)
#define | IS_SAI_BLOCK_COMPANDING_MODE(MODE)
#define | IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD)
#define | IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE)
#define | IS_SAI_MONO_STEREO_MODE(MODE)
#define | IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
#define | IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
#define | IS_SAI_BLOCK_SLOT_SIZE(SIZE)
#define | IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
#define | IS_SAI_BLOCK_FS_OFFSET(OFFSET)
#define | IS_SAI_BLOCK_FS_POLARITY(POLARITY)
#define | IS_SAI_BLOCK_FS_DEFINITION(DEFINITION)
#define | IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
#define | IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
#define | IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))

Typedefs

typedef void(* | SAIcallback )(void)
SAI Callback prototype.
typedef struct __SAI_HandleTypeDef | SAI_HandleTypeDef

Enumerations

enum HAL_SAI_StateTypeDef {
HAL_SAI_STATE_RESET = 0x00U, HAL_SAI_STATE_READY = 0x01U, HAL_SAI_STATE_BUSY = 0x02U, HAL_SAI_STATE_BUSY_TX = 0x12U,
HAL_SAI_STATE_BUSY_RX = 0x22U
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_SAI_InitProtocol (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.
HAL_StatusTypeDef | HAL_SAI_Init (SAI_HandleTypeDef *hsai)
Initialize the SAI according to the specified parameters.
HAL_StatusTypeDef | HAL_SAI_DeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI peripheral.
__weak void | HAL_SAI_MspInit (SAI_HandleTypeDef *hsai)
Initialize the SAI MSP.
__weak void | HAL_SAI_MspDeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI MSP.
HAL_StatusTypeDef | HAL_SAI_Transmit (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Receive (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Transmit_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Receive_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Transmit_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_Receive_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_DMAPause (SAI_HandleTypeDef *hsai)
Pause the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAResume (SAI_HandleTypeDef *hsai)
Resume the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAStop (SAI_HandleTypeDef *hsai)
Stop the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_Abort (SAI_HandleTypeDef *hsai)
Abort the current transfer and disable the SAI.
HAL_StatusTypeDef | HAL_SAI_EnableTxMuteMode (SAI_HandleTypeDef *hsai, uint16_t val)
Enable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_DisableTxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_EnableRxMuteMode (SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
Enable the Rx mute detection.
HAL_StatusTypeDef | HAL_SAI_DisableRxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Rx mute detection.
void | HAL_SAI_IRQHandler (SAI_HandleTypeDef *hsai)
Handle SAI interrupt request.
__weak void | HAL_SAI_TxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer Half completed callback.
__weak void | HAL_SAI_TxCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer completed callback.
__weak void | HAL_SAI_RxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer half completed callback.
__weak void | HAL_SAI_RxCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer completed callback.
__weak void | HAL_SAI_ErrorCallback (SAI_HandleTypeDef *hsai)
SAI error callback.
HAL_SAI_StateTypeDef | HAL_SAI_GetState (SAI_HandleTypeDef *hsai)
Return the SAI handle state.
uint32_t | HAL_SAI_GetError (SAI_HandleTypeDef *hsai)
Return the SAI error code.

Detailed Description

Header file of SAI HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_sai.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sai_ex.h File Reference

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stm32h7xx_hal_sai_ex.h File Reference

Header file of SAI HAL extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SAIEx_PdmMicDelayParamTypeDef
PDM microphone delay structure definition. More...

Defines

#define | IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U)

Functions

HAL_StatusTypeDef | HAL_SAIEx_ConfigPdmMicDelay (SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
Configure PDM microphone delays.

Detailed Description

Header file of SAI HAL extended module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_sai_ex.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sd.h File Reference

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stm32h7xx_hal_sd.h File Reference

Header file of SD HAL module. More...

#include "stm32h7xx_ll_sdmmc.h"
#include "stm32h7xx_hal_sd_ex.h"

Go to the source code of this file.

Data Structures

struct | HAL_SD_CardInfoTypeDef
SD Card Information Structure definition. More...
struct | SD_HandleTypeDef
SD handle Structure definition. More...
struct | HAL_SD_CardCSDTypedef
struct | HAL_SD_CardCIDTypedef
struct | HAL_SD_CardStatusTypedef

Defines

#define | SD_InitTypeDef SDMMC_InitTypeDef
#define | SD_TypeDef SDMMC_TypeDef
#define | BLOCKSIZE ((uint32_t)512U)
#define | HAL_SD_ERROR_NONE SDMMC_ERROR_NONE
#define | HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL
#define | HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL
#define | HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT
#define | HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT
#define | HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN
#define | HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN
#define | HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED
#define | HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR
#define | HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR
#define | HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM
#define | HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION
#define | HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED
#define | HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED
#define | HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD
#define | HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED
#define | HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR
#define | HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR
#define | HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN
#define | HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN
#define | HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE
#define | HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP
#define | HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED
#define | HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET
#define | HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR
#define | HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE
#define | HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE
#define | HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE
#define | HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER
#define | HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE
#define | HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY
#define | HAL_SD_ERROR_DMA SDMMC_ERROR_DMA
#define | HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT
#define | SD_CONTEXT_NONE ((uint32_t)0x00000000U)
#define | SD_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U)
#define | SD_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U)
#define | SD_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U)
#define | SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)
#define | SD_CONTEXT_IT ((uint32_t)0x00000008U)
#define | SD_CONTEXT_DMA ((uint32_t)0x00000080U)
#define | CARD_NORMAL_SPEED ((uint32_t)0x00000000U)
#define | CARD_HIGH_SPEED ((uint32_t)0x00000100U)
#define | CARD_ULTRA_HIGH_SPEED ((uint32_t)0x00000200U)
#define | CARD_SDSC ((uint32_t)0x00000000U)
#define | CARD_SDHC_SDXC ((uint32_t)0x00000001U)
#define | CARD_SECURED ((uint32_t)0x00000003U)
#define | CARD_V1_X ((uint32_t)0x00000000U)
#define | CARD_V2_X ((uint32_t)0x00000001U)
#define | __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Enable the SD device interrupt.
#define | __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Disable the SD device interrupt.
#define | __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
Check whether the specified SD flag is set or not.
#define | __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
Clear the SD's pending flags.
#define | __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Check whether the specified SD interrupt has occurred or not.
#define | __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Clear the SD's interrupt pending bits.

Enumerations

enum HAL_SD_StateTypeDef {
HAL_SD_STATE_RESET = ((uint32_t)0x00000000U), HAL_SD_STATE_READY = ((uint32_t)0x00000001U), HAL_SD_STATE_TIMEOUT = ((uint32_t)0x00000002U), HAL_SD_STATE_BUSY = ((uint32_t)0x00000003U),
HAL_SD_STATE_PROGRAMMING = ((uint32_t)0x00000004U), HAL_SD_STATE_RECEIVING = ((uint32_t)0x00000005U), HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU)
}
enum HAL_SD_CardStateTypedef {
HAL_SD_CARD_READY = ((uint32_t)0x00000001U), HAL_SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), HAL_SD_CARD_STANDBY = ((uint32_t)0x00000003U), HAL_SD_CARD_TRANSFER = ((uint32_t)0x00000004U),
HAL_SD_CARD_SENDING = ((uint32_t)0x00000005U), HAL_SD_CARD_RECEIVING = ((uint32_t)0x00000006U), HAL_SD_CARD_PROGRAMMING = ((uint32_t)0x00000007U), HAL_SD_CARD_DISCONNECTED = ((uint32_t)0x00000008U),
HAL_SD_CARD_ERROR = ((uint32_t)0x000000FFU)
}

Functions

HAL_StatusTypeDef | HAL_SD_Init (SD_HandleTypeDef *hsd)
Initializes the SD according to the specified parameters in the SD_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SD_InitCard (SD_HandleTypeDef *hsd)
Initializes the SD Card according to the specified parameters in the.
HAL_StatusTypeDef | HAL_SD_DeInit (SD_HandleTypeDef *hsd)
De-Initializes the SD card.
__weak void | HAL_SD_MspInit (SD_HandleTypeDef *hsd)
Initializes the SD MSP.
__weak void | HAL_SD_MspDeInit (SD_HandleTypeDef *hsd)
De-Initialize SD MSP.
HAL_StatusTypeDef | HAL_SD_ReadBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SD_WriteBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Allows to write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SD_Erase (SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
Erases the specified memory area of the given SD card.
HAL_StatusTypeDef | HAL_SD_ReadBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SD_WriteBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SD_ReadBlocks_DMA (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SD_WriteBlocks_DMA (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
void | HAL_SD_IRQHandler (SD_HandleTypeDef *hsd)
This function handles SD card interrupt request.
__weak void | HAL_SD_TxCpltCallback (SD_HandleTypeDef *hsd)
Tx Transfer completed callbacks.
__weak void | HAL_SD_RxCpltCallback (SD_HandleTypeDef *hsd)
Rx Transfer completed callbacks.
__weak void | HAL_SD_ErrorCallback (SD_HandleTypeDef *hsd)
SD error callbacks.
__weak void | HAL_SD_AbortCallback (SD_HandleTypeDef *hsd)
SD Abort callbacks.
__weak void | HAL_SD_DriveTransciver_1_8V_Callback (FlagStatus status)
Enable/Disable the SD Transciver 1.8V Mode Callback.
HAL_StatusTypeDef | HAL_SD_ConfigWideBusOperation (SD_HandleTypeDef *hsd, uint32_t WideMode)
Enables wide bus operation for the requested card if supported by card.
HAL_StatusTypeDef | HAL_SD_SendSDStatus (SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
HAL_SD_CardStateTypedef | HAL_SD_GetCardState (SD_HandleTypeDef *hsd)
Gets the current sd card data state.
HAL_StatusTypeDef | HAL_SD_GetCardCID (SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef *pCID)
Returns information the information of the card which are stored on the CID register.
HAL_StatusTypeDef | HAL_SD_GetCardCSD (SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef *pCSD)
Returns information the information of the card which are stored on the CSD register.
HAL_StatusTypeDef | HAL_SD_GetCardStatus (SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pStatus)
Gets the SD status info.
HAL_StatusTypeDef | HAL_SD_GetCardInfo (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
Gets the SD card info.
HAL_SD_StateTypeDef | HAL_SD_GetState (SD_HandleTypeDef *hsd)
return the SD state
uint32_t | HAL_SD_GetError (SD_HandleTypeDef *hsd)
Return the SD error code.
HAL_StatusTypeDef | HAL_SD_Abort (SD_HandleTypeDef *hsd)
Abort the current transfer and disable the SD.
HAL_StatusTypeDef | HAL_SD_Abort_IT (SD_HandleTypeDef *hsd)
Abort the current transfer and disable the SD (IT mode).

Detailed Description

Header file of SD HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_sd.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sd_ex.h File Reference

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stm32h7xx_hal_sd_ex.h File Reference

Header file of SD HAL extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Enumerations

enum | HAL_SDEx_DMABuffer_MemoryTypeDef { SD_DMA_BUFFER0 = 0x00U, SD_DMA_BUFFER1 = 0x01U }

Functions

HAL_StatusTypeDef | HAL_SDEx_ConfigDMAMultiBuffer (SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, uint32_t BufferSize)
Configure DMA Dual Buffer mode.
HAL_StatusTypeDef | HAL_SDEx_ReadBlocksDMAMultiBuffer (SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SDEx_WriteBlocksDMAMultiBuffer (SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SDEx_ChangeDMABuffer (SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
Change the DMA Buffer0 or Buffer1 address on the fly.
void | HAL_SDEx_Read_DMADoubleBuffer0CpltCallback (SD_HandleTypeDef *hsd)
Read DMA Buffer 0 Transfer completed callbacks.
void | HAL_SDEx_Read_DMADoubleBuffer1CpltCallback (SD_HandleTypeDef *hsd)
Read DMA Buffer 1 Transfer completed callbacks.
void | HAL_SDEx_Write_DMADoubleBuffer0CpltCallback (SD_HandleTypeDef *hsd)
Write DMA Buffer 0 Transfer completed callbacks.
void | HAL_SDEx_Write_DMADoubleBuffer1CpltCallback (SD_HandleTypeDef *hsd)
Write DMA Buffer 1 Transfer completed callbacks.

Detailed Description

Header file of SD HAL extended module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_sd_ex.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sdram.h File Reference

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stm32h7xx_hal_sdram.h File Reference

Header file of SDRAM HAL module. More...

#include "stm32h7xx_ll_fmc.h"
#include "stm32h7xx_hal_mdma.h"

Go to the source code of this file.

Data Structures

struct | SDRAM_HandleTypeDef
SDRAM handle Structure definition. More...

Defines

#define | __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
Reset SDRAM handle state.

Enumerations

enum HAL_SDRAM_StateTypeDef {
HAL_SDRAM_STATE_RESET = 0x00U, HAL_SDRAM_STATE_READY = 0x01U, HAL_SDRAM_STATE_BUSY = 0x02U, HAL_SDRAM_STATE_ERROR = 0x03U,
HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U, HAL_SDRAM_STATE_PRECHARGED = 0x05U
}
HAL SDRAM State structure definition. More...

Functions

HAL_StatusTypeDef | HAL_SDRAM_Init (SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
Performs the SDRAM device initialization sequence.
HAL_StatusTypeDef | HAL_SDRAM_DeInit (SDRAM_HandleTypeDef *hsdram)
Perform the SDRAM device initialization sequence.
__weak void | HAL_SDRAM_MspInit (SDRAM_HandleTypeDef *hsdram)
SDRAM MSP Init.
__weak void | HAL_SDRAM_MspDeInit (SDRAM_HandleTypeDef *hsdram)
SDRAM MSP DeInit.
void | HAL_SDRAM_IRQHandler (SDRAM_HandleTypeDef *hsdram)
This function handles SDRAM refresh error interrupt request.
__weak void | HAL_SDRAM_RefreshErrorCallback (SDRAM_HandleTypeDef *hsdram)
SDRAM Refresh error callback.
__weak void | HAL_SDRAM_DMA_XferCpltCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete callback.
__weak void | HAL_SDRAM_DMA_XferErrorCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete error callback.
HAL_StatusTypeDef | HAL_SDRAM_Read_8b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
Reads 8-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_8b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
Writes 8-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_16b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
Reads 16-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_16b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
Writes 16-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_32b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads 32-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_32b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes 32-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_DMA (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads a Words data from the SDRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SDRAM_Write_DMA (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes a Words data buffer to SDRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SDRAM_WriteProtection_Enable (SDRAM_HandleTypeDef *hsdram)
Enables dynamically SDRAM write protection.
HAL_StatusTypeDef | HAL_SDRAM_WriteProtection_Disable (SDRAM_HandleTypeDef *hsdram)
Disables dynamically SDRAM write protection.
HAL_StatusTypeDef | HAL_SDRAM_SendCommand (SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
Sends Command to the SDRAM bank.
HAL_StatusTypeDef | HAL_SDRAM_ProgramRefreshRate (SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
Programs the SDRAM Memory Refresh rate.
HAL_StatusTypeDef | HAL_SDRAM_SetAutoRefreshNumber (SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
Sets the Number of consecutive SDRAM Memory auto Refresh commands.
uint32_t | HAL_SDRAM_GetModeStatus (SDRAM_HandleTypeDef *hsdram)
Returns the SDRAM memory current mode.
HAL_SDRAM_StateTypeDef | HAL_SDRAM_GetState (SDRAM_HandleTypeDef *hsdram)
Returns the SDRAM state.

Detailed Description

Header file of SDRAM HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_sdram.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_smartcard.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32h7xx_hal_smartcard.h File Reference

Header file of SMARTCARD HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_smartcard_ex.h"

Go to the source code of this file.

Data Structures

struct | SMARTCARD_InitTypeDef
SMARTCARD Init Structure definition. More...
struct | SMARTCARD_AdvFeatureInitTypeDef
SMARTCARD advanced features initalization structure definition. More...
struct | SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition. More...

Defines

#define | SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
#define | SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define | SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
#define | SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
#define | SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
#define | SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000)
#define | SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
#define | SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000)
#define | SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
#define | SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
#define | SMARTCARD_FIFOMODE_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_FIFOMODE_ENABLE ((uint32_t)USART_CR1_FIFOEN)
#define | SMARTCARD_TXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000)
#define | SMARTCARD_TXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_TXFTCFG_0)
#define | SMARTCARD_TXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_TXFTCFG_1)
#define | SMARTCARD_TXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1))
#define | SMARTCARD_TXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_TXFTCFG_2)
#define | SMARTCARD_TXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0))
#define | SMARTCARD_RXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000)
#define | SMARTCARD_RXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_RXFTCFG_0)
#define | SMARTCARD_RXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_RXFTCFG_1)
#define | SMARTCARD_RXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1))
#define | SMARTCARD_RXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_RXFTCFG_2)
#define | SMARTCARD_RXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0))
#define | SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
#define | SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define | SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)
#define | SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)
#define | SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)
#define | SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)
#define | SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)
#define | SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)
#define | SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)
#define | SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)
#define | SMARTCARD_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ)
#define | SMARTCARD_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ)
#define | SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17)
#define | SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8)
#define | SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24)
#define | SMARTCARD_IT_MASK ((uint16_t)0x001F)
#define | __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)
Reset SMARTCARD handle state.
#define | __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)
Flush the Smartcard Data registers.
#define | __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified SMARTCARD pending flag.
#define | __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
Clear the SMARTCARD PE pending flag.
#define | __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
Clear the SMARTCARD FE pending flag.
#define | __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
Clear the SMARTCARD NE pending flag.
#define | __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
Clear the SMARTCARD ORE pending flag.
#define | __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
Clear the SMARTCARD IDLE pending flag.
#define | __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified Smartcard flag is set or not.
#define | __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
Check whether the specified SmartCard interrupt has occurred or not.
#define | __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified SmartCard interrupt source is enabled or not.
#define | __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
#define | __HAL_SMARTCARD_CLEAR_TXFECF(__HANDLE__) __HAL_SMARTCARD_CLEAR_IT((__HANDLE__), SMARTCARD_CLEAR_TXFECF)
Clear the SMARTCARD TX FIFO empty clear flag.
#define | __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific SMARTCARD request flag.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable the USART associated to the SMARTCARD Handle.
#define | IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
Check the Baud rate range.
#define | IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)
Check the block length range.
#define | IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF)
Check the receiver timeout value.
#define | IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7)
Check the SMARTCARD autoretry counter value.
#define | IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
Ensure that SMARTCARD frame length is valid.
#define | IS_SMARTCARD_STOPBITS(__STOPBITS__)
Ensure that SMARTCARD frame number of stop bits is valid.
#define | IS_SMARTCARD_PARITY(__PARITY__)
Ensure that SMARTCARD frame parity is valid.
#define | IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3) == 0x00) && ((__MODE__) != (uint16_t)0x00))
Ensure that SMARTCARD communication mode is valid.
#define | IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
Ensure that SMARTCARD frame polarity is valid.
#define | IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
Ensure that SMARTCARD frame phase is valid.
#define | IS_SMARTCARD_LASTBIT(__LASTBIT__)
Ensure that SMARTCARD frame last bit clock pulse setting is valid.
#define | IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that SMARTCARD frame sampling is valid.
#define | IS_SMARTCARD_NACK(__NACK__)
Ensure that SMARTCARD NACK transmission setting is valid.
#define | IS_SMARTCARD_TIMEOUT(__TIMEOUT__)
Ensure that SMARTCARD receiver timeout setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_INIT(__INIT__)
Ensure that SMARTCARD advanced features initialization is valid.
#define | IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__)
Ensure that SMARTCARD frame TX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__)
Ensure that SMARTCARD frame RX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that SMARTCARD frame data inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__)
Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
#define | IS_SMARTCARD_OVERRUN(__OVERRUN__)
Ensure that SMARTCARD frame overrun setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that SMARTCARD frame MSB first setting is valid.
#define | IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__)
Ensure that SMARTCARD request parameter is valid.
#define | IS_SMARTCARD_FIFO_MODE_STATE(__STATE__)
Ensure that SMARTCARD FIFO mode is valid.
#define | IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that SMARTCARD TXFIFO threshold level is valid.
#define | IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that SMARTCARD RXFIFO threshold level is valid.

Enumerations

enum HAL_SMARTCARD_StateTypeDef {
HAL_SMARTCARD_STATE_RESET = 0x00U, HAL_SMARTCARD_STATE_READY = 0x20U, HAL_SMARTCARD_STATE_BUSY = 0x24U, HAL_SMARTCARD_STATE_BUSY_TX = 0x21U,
HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, HAL_SMARTCARD_STATE_ERROR = 0xE0U
}
HAL SMARTCARD State structures definition. More...
enum HAL_SMARTCARD_ErrorTypeDef {
HAL_SMARTCARD_ERROR_NONE = 0x00, HAL_SMARTCARD_ERROR_PE = 0x01, HAL_SMARTCARD_ERROR_NE = 0x02, HAL_SMARTCARD_ERROR_FE = 0x04,
HAL_SMARTCARD_ERROR_ORE = 0x08, HAL_SMARTCARD_ERROR_DMA = 0x10, HAL_SMARTCARD_ERROR_UDR = 0x11, HAL_SMARTCARD_ERROR_RTO = 0x20
}
HAL SMARTCARD Error Code structure definition. More...
enum SMARTCARD_ClockSourceTypeDef {
SMARTCARD_CLOCKSOURCE_D2PCLK1 = 0x00, SMARTCARD_CLOCKSOURCE_D2PCLK2 = 0x01, SMARTCARD_CLOCKSOURCE_D3PCLK1 = 0x02, SMARTCARD_CLOCKSOURCE_PLL2Q = 0x04,
SMARTCARD_CLOCKSOURCE_HSI = 0x08, SMARTCARD_CLOCKSOURCE_CSI = 0x10, SMARTCARD_CLOCKSOURCE_LSE = 0x20, SMARTCARD_CLOCKSOURCE_PLL3Q = 0x40,
SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x80
}
SMARTCARD clock sources. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD MSP.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD MSP.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Abort (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_Abort_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsmartcard)
Handle SMARTCARD interrupt requests.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Tx Transfer completed callback.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Rx Transfer completed callback.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD error callback.
__weak void | HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Receive Complete callback.
HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle state.
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle error code.

Detailed Description

Header file of SMARTCARD HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_smartcard.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_smartcard_ex.h File Reference

  • File List
  • Globals
  • Drivers
  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_smartcard_ex.h File Reference

Header file of SMARTCARD HAL Extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | SMARTCARD_TCBGT SMARTCARD_IT_TCBGT
#define | SMARTCARD_TC SMARTCARD_IT_TC
#define | SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)
#define | SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)
#define | SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)
#define | SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)
#define | SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)
#define | SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)
#define | SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)
#define | SMARTCARD_ADVFEATURE_TXCOMPLETION ((uint32_t)0x00000100)
#define | SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT
#define | SMARTCARD_FLAG_REACK USART_ISR_REACK
#define | SMARTCARD_FLAG_TEACK USART_ISR_TEACK
#define | SMARTCARD_FLAG_BUSY USART_ISR_BUSY
#define | SMARTCARD_FLAG_EOBF USART_ISR_EOBF
#define | SMARTCARD_FLAG_RTOF USART_ISR_RTOF
#define | SMARTCARD_FLAG_TXE USART_ISR_TXE
#define | SMARTCARD_FLAG_TC USART_ISR_TC
#define | SMARTCARD_FLAG_RXNE USART_ISR_RXNE
#define | SMARTCARD_FLAG_IDLE USART_ISR_IDLE
#define | SMARTCARD_FLAG_ORE USART_ISR_ORE
#define | SMARTCARD_FLAG_NE USART_ISR_NE
#define | SMARTCARD_FLAG_FE USART_ISR_FE
#define | SMARTCARD_FLAG_PE USART_ISR_PE
#define | SMARTCARD_FLAG_TXFT USART_ISR_TXFT
#define | SMARTCARD_FLAG_RXFT USART_ISR_RXFT
#define | SMARTCARD_FLAG_RXFF USART_ISR_RXFF
#define | SMARTCARD_FLAG_TXFE USART_ISR_TXFE
#define | SMARTCARD_IT_PE ((uint16_t)0x0028)
#define | SMARTCARD_IT_TXE ((uint16_t)0x0727)
#define | SMARTCARD_IT_TC ((uint16_t)0x0626)
#define | SMARTCARD_IT_RXNE ((uint16_t)0x0525)
#define | SMARTCARD_IT_IDLE ((uint16_t)0x0424)
#define | SMARTCARD_IT_ERR ((uint16_t)0x0060)
#define | SMARTCARD_IT_ORE ((uint16_t)0x0300)
#define | SMARTCARD_IT_NE ((uint16_t)0x0200)
#define | SMARTCARD_IT_FE ((uint16_t)0x0100)
#define | SMARTCARD_IT_EOB ((uint16_t)0x0C3B)
#define | SMARTCARD_IT_RTO ((uint16_t)0x0B3A)
#define | SMARTCARD_IT_RXFF ((uint16_t)0x183F)
#define | SMARTCARD_IT_TXFE ((uint16_t)0x173E)
#define | SMARTCARD_IT_RXFT ((uint16_t)0x187C)
#define | SMARTCARD_IT_TXFT ((uint16_t)0x1B77)
#define | SMARTCARD_IT_TCBGT ((uint16_t)0x1978)
#define | SMARTCARD_CLEAR_PEF USART_ICR_PECF
#define | SMARTCARD_CLEAR_FEF USART_ICR_FECF
#define | SMARTCARD_CLEAR_NEF USART_ICR_NCF
#define | SMARTCARD_CLEAR_OREF USART_ICR_ORECF
#define | SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF
#define | SMARTCARD_CLEAR_TCF USART_ICR_TCCF
#define | SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF
#define | SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF
#define | SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF
#define | SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF
#define | SMARTCARD_CLEAR_UDRCF USART_ICR_UDRCF
#define | SMARTCARD_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the SMARTCARD clock source.
#define | SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)
Set the Transmission Completion flag.
#define | SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
Return the transmission completion flag.
#define | IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__)
Ensure that SMARTCARD frame transmission completion used flag is valid.

Functions

void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the SMARTCARD receiver timeout feature.

Detailed Description

Header file of SMARTCARD HAL Extended module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_smartcard_ex.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_smbus.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_hal_smbus.h File Reference

Header file of SMBUS HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SMBUS_InitTypeDef
struct | SMBUS_HandleTypeDef

Defines

#define | HAL_SMBUS_STATE_RESET (0x00000000U)
#define | HAL_SMBUS_STATE_READY (0x00000001U)
#define | HAL_SMBUS_STATE_BUSY (0x00000002U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U)
#define | HAL_SMBUS_STATE_TIMEOUT (0x00000003U)
#define | HAL_SMBUS_STATE_ERROR (0x00000004U)
#define | HAL_SMBUS_STATE_LISTEN (0x00000008U)
#define | HAL_SMBUS_ERROR_NONE (0x00000000U)
#define | HAL_SMBUS_ERROR_BERR (0x00000001U)
#define | HAL_SMBUS_ERROR_ARLO (0x00000002U)
#define | HAL_SMBUS_ERROR_ACKF (0x00000004U)
#define | HAL_SMBUS_ERROR_OVR (0x00000008U)
#define | HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U)
#define | HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U)
#define | HAL_SMBUS_ERROR_ALERT (0x00000040U)
#define | HAL_SMBUS_ERROR_PECERR (0x00000080U)
#define | SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
#define | SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
#define | SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
#define | SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
#define | SMBUS_DUALADDRESS_DISABLE (0x00000000U)
#define | SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
#define | SMBUS_OA2_NOMASK ((uint8_t)0x00U)
#define | SMBUS_OA2_MASK01 ((uint8_t)0x01U)
#define | SMBUS_OA2_MASK02 ((uint8_t)0x02U)
#define | SMBUS_OA2_MASK03 ((uint8_t)0x03U)
#define | SMBUS_OA2_MASK04 ((uint8_t)0x04U)
#define | SMBUS_OA2_MASK05 ((uint8_t)0x05U)
#define | SMBUS_OA2_MASK06 ((uint8_t)0x06U)
#define | SMBUS_OA2_MASK07 ((uint8_t)0x07U)
#define | SMBUS_GENERALCALL_DISABLE (0x00000000U)
#define | SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
#define | SMBUS_NOSTRETCH_DISABLE (0x00000000U)
#define | SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
#define | SMBUS_PEC_DISABLE (0x00000000U)
#define | SMBUS_PEC_ENABLE I2C_CR1_PECEN
#define | SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
#define | SMBUS_SOFTEND_MODE (0x00000000U)
#define | SMBUS_RELOAD_MODE I2C_CR2_RELOAD
#define | SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
#define | SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
#define | SMBUS_NO_STARTSTOP (0x00000000U)
#define | SMBUS_GENERATE_STOP I2C_CR2_STOP
#define | SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | SMBUS_GENERATE_START_WRITE I2C_CR2_START
#define | SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
#define | SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define | SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
#define | SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
#define | SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
#define | SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
#define | SMBUS_IT_ERRI I2C_CR1_ERRIE
#define | SMBUS_IT_TCI I2C_CR1_TCIE
#define | SMBUS_IT_STOPI I2C_CR1_STOPIE
#define | SMBUS_IT_NACKI I2C_CR1_NACKIE
#define | SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define | SMBUS_IT_RXI I2C_CR1_RXIE
#define | SMBUS_IT_TXI I2C_CR1_TXIE
#define | SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
#define | SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
#define | SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define | SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
#define | SMBUS_FLAG_TXE I2C_ISR_TXE
#define | SMBUS_FLAG_TXIS I2C_ISR_TXIS
#define | SMBUS_FLAG_RXNE I2C_ISR_RXNE
#define | SMBUS_FLAG_ADDR I2C_ISR_ADDR
#define | SMBUS_FLAG_AF I2C_ISR_NACKF
#define | SMBUS_FLAG_STOPF I2C_ISR_STOPF
#define | SMBUS_FLAG_TC I2C_ISR_TC
#define | SMBUS_FLAG_TCR I2C_ISR_TCR
#define | SMBUS_FLAG_BERR I2C_ISR_BERR
#define | SMBUS_FLAG_ARLO I2C_ISR_ARLO
#define | SMBUS_FLAG_OVR I2C_ISR_OVR
#define | SMBUS_FLAG_PECERR I2C_ISR_PECERR
#define | SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | SMBUS_FLAG_ALERT I2C_ISR_ALERT
#define | SMBUS_FLAG_BUSY I2C_ISR_BUSY
#define | SMBUS_FLAG_DIR I2C_ISR_DIR
#define | __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
Reset SMBUS handle state.
#define | __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified SMBUS interrupts.
#define | __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified SMBUS interrupts.
#define | __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SMBUS interrupt source is enabled or not.
#define | SMBUS_FLAG_MASK (0x0001FFFFU)
Check whether the specified SMBUS flag is set or not.
#define | __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
#define | __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified SMBUS peripheral.
#define | __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified SMBUS peripheral.
#define | __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
#define | IS_SMBUS_ANALOG_FILTER(FILTER)
#define | IS_SMBUS_ADDRESSING_MODE(MODE)
#define | IS_SMBUS_DUAL_ADDRESS(ADDRESS)
#define | IS_SMBUS_OWN_ADDRESS2_MASK(MASK)
#define | IS_SMBUS_GENERAL_CALL(CALL)
#define | IS_SMBUS_NO_STRETCH(STRETCH)
#define | IS_SMBUS_PEC(PEC)
#define | IS_SMBUS_PERIPHERAL_MODE(MODE)
#define | IS_SMBUS_TRANSFER_MODE(MODE)
#define | IS_SMBUS_TRANSFER_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)
#define | SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
#define | SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | SMBUS_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)
#define | SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
#define | SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define | SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
#define | SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
#define | SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
#define | IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)

Functions

HAL_StatusTypeDef | HAL_SMBUS_Init (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS peripheral.
__weak void | HAL_SMBUS_MspInit (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS MSP.
__weak void | HAL_SMBUS_MspDeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS MSP.
HAL_StatusTypeDef | HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.
HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.
void | HAL_SMBUS_EV_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS event interrupt request.
void | HAL_SMBUS_ER_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS error interrupt request.
__weak void | HAL_SMBUS_MasterTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Tx Transfer completed callback.
__weak void | HAL_SMBUS_MasterRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Rx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Tx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Rx Transfer completed callback.
__weak void | HAL_SMBUS_AddrCallback (SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_SMBUS_ListenCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Listen Complete callback.
__weak void | HAL_SMBUS_ErrorCallback (SMBUS_HandleTypeDef *hsmbus)
SMBUS error callback.
uint32_t | HAL_SMBUS_GetState (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS handle state.
uint32_t | HAL_SMBUS_GetError (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS error code.

Detailed Description

Header file of SMBUS HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_smbus.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_spdifrx.h File Reference

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  • STM32H7xx_HAL_Driver
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Data Structures | Defines | Enumerations | Functions
stm32h7xx_hal_spdifrx.h File Reference

Header file of SPDIFRX HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SPDIFRX_InitTypeDef
SPDIFRX Init structure definition. More...
struct | SPDIFRX_SetDataFormatTypeDef
SPDIFRX SetDataFormat structure definition. More...
struct | SPDIFRX_HandleTypeDef
SPDIFRX handle Structure definition. More...

Defines

#define | HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001U)
#define | HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002U)
#define | HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004U)
#define | HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008U)
#define | HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010U)
#define | SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000U)
#define | SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000U)
#define | SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000U)
#define | SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000U)
#define | SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000U)
#define | SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000U)
#define | SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000U)
#define | SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000U)
#define | SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000U)
#define | SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)
#define | SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000U)
#define | SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)
#define | SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied into the SPDIF_DR */
#define | SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
#define | SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U)
#define | SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)
#define | SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000U)
#define | SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)
#define | SPDIFRX_CHANNEL_A ((uint32_t)0x00000000U)
#define | SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)
#define | SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000U)
#define | SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010U)
#define | SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020U)
#define | SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000U)
#define | SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)
#define | SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFCU)
#define | SPDIFRX_STATE_SYNC ((uint32_t)0x00000001U)
#define | SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN)
#define | SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)
#define | SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)
#define | SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)
#define | SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)
#define | SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)
#define | SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)
#define | SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )
#define | SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)
#define | SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)
#define | SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)
#define | SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)
#define | SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)
#define | SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)
#define | SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)
#define | SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)
#define | SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)
#define | __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN)
Reset SPDIFRX handle state.
#define | __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)
Disable the specified SPDIFRX peripheral (IDLE State).
#define | __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)
Enable the specified SPDIFRX peripheral (SYNC State).
#define | __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)
Enable the specified SPDIFRX peripheral (RCV State).
#define | __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
Enable or disable the specified SPDIFRX interrupts.
#define | __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
#define | __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified SPDIFRX interrupt source is enabled or disabled.
#define | __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Checks whether the specified SPDIFRX flag is set or not.
#define | __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))
Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.
#define | IS_SPDIFRX_INPUT_SELECT(INPUT)
#define | IS_SPDIFRX_MAX_RETRIES(RET)
#define | IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL)
#define | IS_PREAMBLE_TYPE_MASK(VAL)
#define | IS_VALIDITY_MASK(VAL)
#define | IS_PARITY_ERROR_MASK(VAL)
#define | IS_SPDIFRX_CHANNEL(CHANNEL)
#define | IS_SPDIFRX_DATA_FORMAT(FORMAT)
#define | IS_STEREO_MODE(MODE)
#define | IS_CHANNEL_STATUS_MASK(VAL)

Enumerations

enum HAL_SPDIFRX_StateTypeDef {
HAL_SPDIFRX_STATE_RESET = 0x00U, HAL_SPDIFRX_STATE_READY = 0x01U, HAL_SPDIFRX_STATE_BUSY = 0x02U, HAL_SPDIFRX_STATE_BUSY_RX = 0x03U,
HAL_SPDIFRX_STATE_BUSY_CX = 0x04U, HAL_SPDIFRX_STATE_ERROR = 0x07U
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_SPDIFRX_Init (SPDIFRX_HandleTypeDef *hspdif)
Initializes the SPDIFRX according to the specified parameters in the SPDIFRX_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif)
DeInitializes the SPDIFRX peripheral.
__weak void | HAL_SPDIFRX_MspInit (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX MSP Init.
__weak void | HAL_SPDIFRX_MspDeInit (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX MSP DeInit.
HAL_StatusTypeDef | HAL_SPDIFRX_SetDataFormat (SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)
Sets the SPDIFRX dtat format according to the specified parameters in the SPDIFRX_InitTypeDef.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data (Data Flow) in blocking mode.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveControlFlow (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data (Control Flow) in blocking mode.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveControlFlow_IT (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Control Flow) with Interrupt.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow_IT (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Data Flow) in non-blocking mode with Interrupt.
void | HAL_SPDIFRX_IRQHandler (SPDIFRX_HandleTypeDef *hspdif)
This function handles SPDIFRX interrupt request.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveControlFlow_DMA (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Control Flow) with DMA.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow_DMA (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Data Flow) mode with DMA.
HAL_StatusTypeDef | HAL_SPDIFRX_DMAStop (SPDIFRX_HandleTypeDef *hspdif)
stop the audio stream receive from the Media.
__weak void | HAL_SPDIFRX_RxHalfCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Data flow) half completed callbacks.
__weak void | HAL_SPDIFRX_RxCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Data flow) completed callbacks.
__weak void | HAL_SPDIFRX_ErrorCallback (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX error callbacks.
__weak void | HAL_SPDIFRX_CxHalfCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx (Control flow) Transfer half completed callbacks.
__weak void | HAL_SPDIFRX_CxCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Control flow) completed callbacks.
HAL_SPDIFRX_StateTypeDef | HAL_SPDIFRX_GetState (SPDIFRX_HandleTypeDef *hspdif)
Return the SPDIFRX state.
uint32_t | HAL_SPDIFRX_GetError (SPDIFRX_HandleTypeDef *hspdif)
Return the SPDIFRX error code.

Detailed Description

Header file of SPDIFRX HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_spdifrx.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_spi.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32h7xx_hal_spi.h File Reference

Header file of SPI HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_spi_ex.h"

Go to the source code of this file.

Data Structures

struct | SPI_InitTypeDef
SPI Configuration Structure definition. More...
struct | __SPI_HandleTypeDef
SPI handle Structure definition. More...

Defines

#define | SPI_LOWEND_FIFO_SIZE 8U
#define | SPI_HIGHEND_FIFO_SIZE 16U
#define | HAL_SPI_ERROR_NONE (0x00000000U)
#define | HAL_SPI_ERROR_MODF (0x00000001U)
#define | HAL_SPI_ERROR_CRC (0x00000002U)
#define | HAL_SPI_ERROR_OVR (0x00000004U)
#define | HAL_SPI_ERROR_FRE (0x00000008U)
#define | HAL_SPI_ERROR_DMA (0x00000010U)
#define | HAL_SPI_ERROR_FLAG (0x00000020U)
#define | HAL_SPI_ERROR_ABORT (0x00000040U)
#define | HAL_SPI_ERROR_UDR (0x00000080U)
#define | HAL_SPI_ERROR_TIMEOUT (0x00000100U)
#define | HAL_SPI_ERROR_UNKNOW (0x00000200U)
#define | SPI_MODE_SLAVE (0x00000000U)
#define | SPI_MODE_MASTER SPI_CFG2_MASTER
#define | SPI_DIRECTION_2LINES (0x00000000U)
#define | SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0
#define | SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1
#define | SPI_DIRECTION_1LINE SPI_CFG2_COMM
#define | SPI_DATASIZE_4BIT (0x00000003U)
#define | SPI_DATASIZE_5BIT (0x00000004U)
#define | SPI_DATASIZE_6BIT (0x00000005U)
#define | SPI_DATASIZE_7BIT (0x00000006U)
#define | SPI_DATASIZE_8BIT (0x00000007U)
#define | SPI_DATASIZE_9BIT (0x00000008U)
#define | SPI_DATASIZE_10BIT (0x00000009U)
#define | SPI_DATASIZE_11BIT (0x0000000AU)
#define | SPI_DATASIZE_12BIT (0x0000000BU)
#define | SPI_DATASIZE_13BIT (0x0000000CU)
#define | SPI_DATASIZE_14BIT (0x0000000DU)
#define | SPI_DATASIZE_15BIT (0x0000000EU)
#define | SPI_DATASIZE_16BIT (0x0000000FU)
#define | SPI_DATASIZE_17BIT (0x00000010U)
#define | SPI_DATASIZE_18BIT (0x00000011U)
#define | SPI_DATASIZE_19BIT (0x00000012U)
#define | SPI_DATASIZE_20BIT (0x00000013U)
#define | SPI_DATASIZE_21BIT (0x00000014U)
#define | SPI_DATASIZE_22BIT (0x00000015U)
#define | SPI_DATASIZE_23BIT (0x00000016U)
#define | SPI_DATASIZE_24BIT (0x00000017U)
#define | SPI_DATASIZE_25BIT (0x00000018U)
#define | SPI_DATASIZE_26BIT (0x00000019U)
#define | SPI_DATASIZE_27BIT (0x0000001AU)
#define | SPI_DATASIZE_28BIT (0x0000001BU)
#define | SPI_DATASIZE_29BIT (0x0000001CU)
#define | SPI_DATASIZE_30BIT (0x0000001DU)
#define | SPI_DATASIZE_31BIT (0x0000001EU)
#define | SPI_DATASIZE_32BIT (0x0000001FU)
#define | SPI_POLARITY_LOW (0x00000000U)
#define | SPI_POLARITY_HIGH SPI_CFG2_CPOL
#define | SPI_PHASE_1EDGE (0x00000000U)
#define | SPI_PHASE_2EDGE SPI_CFG2_CPHA
#define | SPI_NSS_SOFT SPI_CFG2_SSM
#define | SPI_NSS_HARD_INPUT (0x00000000U)
#define | SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE
#define | SPI_NSS_PULSE_DISABLE (0x00000000U)
#define | SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM
#define | SPI_BAUDRATEPRESCALER_2 (0x00000000U)
#define | SPI_BAUDRATEPRESCALER_4 (0x10000000U)
#define | SPI_BAUDRATEPRESCALER_8 (0x20000000U)
#define | SPI_BAUDRATEPRESCALER_16 (0x30000000U)
#define | SPI_BAUDRATEPRESCALER_32 (0x40000000U)
#define | SPI_BAUDRATEPRESCALER_64 (0x50000000U)
#define | SPI_BAUDRATEPRESCALER_128 (0x60000000U)
#define | SPI_BAUDRATEPRESCALER_256 (0x70000000U)
#define | SPI_FIRSTBIT_MSB (0x00000000U)
#define | SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST
#define | SPI_TIMODE_DISABLE (0x00000000U)
#define | SPI_TIMODE_ENABLE SPI_CFG2_SP_0
#define | SPI_CRCCALCULATION_DISABLE (0x00000000U)
#define | SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN
#define | SPI_CRC_LENGTH_DATASIZE (0x00000000U)
#define | SPI_CRC_LENGTH_4BIT (0x00030000U)
#define | SPI_CRC_LENGTH_5BIT (0x00040000U)
#define | SPI_CRC_LENGTH_6BIT (0x00050000U)
#define | SPI_CRC_LENGTH_7BIT (0x00060000U)
#define | SPI_CRC_LENGTH_8BIT (0x00070000U)
#define | SPI_CRC_LENGTH_9BIT (0x00080000U)
#define | SPI_CRC_LENGTH_10BIT (0x00090000U)
#define | SPI_CRC_LENGTH_11BIT (0x000A0000U)
#define | SPI_CRC_LENGTH_12BIT (0x000B0000U)
#define | SPI_CRC_LENGTH_13BIT (0x000C0000U)
#define | SPI_CRC_LENGTH_14BIT (0x000D0000U)
#define | SPI_CRC_LENGTH_15BIT (0x000E0000U)
#define | SPI_CRC_LENGTH_16BIT (0x000F0000U)
#define | SPI_CRC_LENGTH_17BIT (0x00100000U)
#define | SPI_CRC_LENGTH_18BIT (0x00110000U)
#define | SPI_CRC_LENGTH_19BIT (0x00120000U)
#define | SPI_CRC_LENGTH_20BIT (0x00130000U)
#define | SPI_CRC_LENGTH_21BIT (0x00140000U)
#define | SPI_CRC_LENGTH_22BIT (0x00150000U)
#define | SPI_CRC_LENGTH_23BIT (0x00160000U)
#define | SPI_CRC_LENGTH_24BIT (0x00170000U)
#define | SPI_CRC_LENGTH_25BIT (0x00180000U)
#define | SPI_CRC_LENGTH_26BIT (0x00190000U)
#define | SPI_CRC_LENGTH_27BIT (0x001A0000U)
#define | SPI_CRC_LENGTH_28BIT (0x001B0000U)
#define | SPI_CRC_LENGTH_29BIT (0x001C0000U)
#define | SPI_CRC_LENGTH_30BIT (0x001D0000U)
#define | SPI_CRC_LENGTH_31BIT (0x001E0000U)
#define | SPI_CRC_LENGTH_32BIT (0x001F0000U)
#define | SPI_FIFO_THRESHOLD_01DATA (0x00000000U)
#define | SPI_FIFO_THRESHOLD_02DATA (0x00000020U)
#define | SPI_FIFO_THRESHOLD_03DATA (0x00000040U)
#define | SPI_FIFO_THRESHOLD_04DATA (0x00000060U)
#define | SPI_FIFO_THRESHOLD_05DATA (0x00000080U)
#define | SPI_FIFO_THRESHOLD_06DATA (0x000000A0U)
#define | SPI_FIFO_THRESHOLD_07DATA (0x000000C0U)
#define | SPI_FIFO_THRESHOLD_08DATA (0x000000E0U)
#define | SPI_FIFO_THRESHOLD_09DATA (0x00000100U)
#define | SPI_FIFO_THRESHOLD_10DATA (0x00000120U)
#define | SPI_FIFO_THRESHOLD_11DATA (0x00000140U)
#define | SPI_FIFO_THRESHOLD_12DATA (0x00000160U)
#define | SPI_FIFO_THRESHOLD_13DATA (0x00000180U)
#define | SPI_FIFO_THRESHOLD_14DATA (0x000001A0U)
#define | SPI_FIFO_THRESHOLD_15DATA (0x000001C0U)
#define | SPI_FIFO_THRESHOLD_16DATA (0x000001E0U)
#define | SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000U)
#define | SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001U)
#define | SPI_NSS_POLARITY_LOW (0x00000000U)
#define | SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP
#define | SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)
#define | SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
#define | SPI_IO_SWAP_DISABLE (0x00000000U)
#define | SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP
#define | SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000U)
#define | SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001U)
#define | SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002U)
#define | SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003U)
#define | SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004U)
#define | SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005U)
#define | SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006U)
#define | SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007U)
#define | SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008U)
#define | SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009U)
#define | SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AU)
#define | SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BU)
#define | SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CU)
#define | SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DU)
#define | SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EU)
#define | SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FU)
#define | SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000U)
#define | SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000001U)
#define | SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000002U)
#define | SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000003U)
#define | SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000004U)
#define | SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000005U)
#define | SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000006U)
#define | SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000007U)
#define | SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000008U)
#define | SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000009U)
#define | SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x0000000AU)
#define | SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x0000000BU)
#define | SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x0000000CU)
#define | SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x0000000DU)
#define | SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x0000000EU)
#define | SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x0000000FU)
#define | SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000U)
#define | SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX
#define | SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000U)
#define | SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0
#define | SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1
#define | SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000U)
#define | SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG_0
#define | SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED SPI_CFG1_UDRCFG_1
#define | SPI_IT_TXE SPI_IER_TXPIE
#define | SPI_IT_RXNE SPI_IER_RXPIE
#define | SPI_IT_EOT SPI_IER_EOTIE
#define | SPI_IT_TXTF SPI_IER_TXTFIE
#define | SPI_IT_ERR (SPI_IER_UDRIE | SPI_IER_OVRIE | SPI_IER_TIFREIE | SPI_IER_MODFIE)
#define | SPI_FLAG_TXE SPI_SR_TXP /* SPI status flag: Tx buffer empty flag */
#define | SPI_FLAG_RXNE SPI_SR_RXP /* SPI status flag: Rx buffer not empty flag */
#define | SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag: Underrun flag */
#define | SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define | SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag: TI mode frame format error flag */
#define | SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag: CRC error flag */
#define | SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define | SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI fifo reception level */
#define | SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI RxFIFO Word Not Empty */
#define | SPI_FLAG_TXTF SPI_SR_TXTF /* SPI Transmission Transfer Filled flag */
#define | SPI_FLAG_EOT SPI_SR_EOT /* SPI fifo transmision complete */
#define | SPI_FRLVL_EMPTY (0x00000000U)
#define | SPI_FRLVL_QUARTER_FULL (0x00002000U)
#define | SPI_FRLVL_HALF_FULL (0x00004000U)
#define | SPI_FRLVL_FULL (0x00006000U)
#define | __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
Reset SPI handle state.
#define | __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified SPI interrupts.
#define | __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified SPI interrupts.
#define | __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SPI interrupt source is enabled or not.
#define | __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SPI flag is set or not.
#define | __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC)
Clear the SPI CRCERR pending flag.
#define | __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC));
Clear the SPI MODF pending flag.
#define | __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
Clear the SPI OVR pending flag.
#define | __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
Clear the SPI FRE pending flag.
#define | __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
Clear the SPI UDR pending flag.
#define | __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC)
Clear the SPI EOT pending flag.
#define | __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC)
Clear the SPI UDR pending flag.
#define | __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
Enable the SPI peripheral.
#define | __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
Disable the SPI peripheral.
#define | SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR)
Set the SPI transmit-only mode.
#define | SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR)
Set the SPI receive-only mode.
#define | IS_SPI_MODE(MODE)
#define | IS_SPI_DIRECTION(MODE)
#define | IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE)
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE)
#define | IS_SPI_DATASIZE(DATASIZE)
#define | IS_SPI_FIFOTHRESHOLD(THRESHOLD)
#define | IS_SPI_CPOL(CPOL)
#define | IS_SPI_CPHA(CPHA)
#define | IS_SPI_NSS(NSS)
#define | IS_SPI_NSSP(NSSP)
#define | IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
#define | IS_SPI_FIRST_BIT(BIT)
#define | IS_SPI_TIMODE(MODE)
#define | IS_SPI_CRC_CALCULATION(CALCULATION)
#define | IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN)
#define | IS_SPI_CRC_LENGTH(LENGTH)
#define | IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFFFFFF))
#define | IS_SPI_UNDERRUN_DETECTION(MODE)
#define | IS_SPI_UNDERRUN_BEHAVIOUR(MODE)

Typedefs

typedef struct __SPI_HandleTypeDef | SPI_HandleTypeDef
SPI handle Structure definition.

Enumerations

enum HAL_SPI_StateTypeDef {
HAL_SPI_STATE_RESET = 0x00U, HAL_SPI_STATE_READY = 0x01U, HAL_SPI_STATE_BUSY = 0x02U, HAL_SPI_STATE_BUSY_TX = 0x03U,
HAL_SPI_STATE_BUSY_RX = 0x04U, HAL_SPI_STATE_BUSY_TX_RX = 0x05U, HAL_SPI_STATE_ERROR = 0x06U, HAL_SPI_STATE_ABORT = 0x07U
}
HAL SPI State structure definition. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_Abort (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_SPI_Abort_IT (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
__weak void | HAL_SPI_AbortCpltCallback (SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.
HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

Header file of SPI HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_spi.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_spi_ex.h File Reference

  • File List
  • Globals
  • Drivers
  • STM32H7xx_HAL_Driver
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Functions
stm32h7xx_hal_spi_ex.h File Reference

Header file of SPI HAL Extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_SPIEx_FlushRxFifo (SPI_HandleTypeDef *hspi)
Flush the RX fifo.
HAL_StatusTypeDef | HAL_SPIEx_EnableLockConfiguration (SPI_HandleTypeDef *hspi)
Enable the Lock for the AF configuration of associated IOs and write protect the Content of Configuartion register 2 when SPI is enabled.
HAL_StatusTypeDef | HAL_SPIEx_DisableLockConfiguration (SPI_HandleTypeDef *hspi)
Disable the Lock for the AF configuration of associated IOs.
HAL_StatusTypeDef | HAL_SPIEx_ConfigureUnderrun (SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour)
Configure the UNDERRUN condition and behavior of slave transmitter.

Detailed Description

Header file of SPI HAL Extended module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_spi_ex.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sram.h File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Data Structures | Defines | Enumerations | Functions
stm32h7xx_hal_sram.h File Reference

Header file of SRAM HAL module. More...

#include "stm32h7xx_ll_fmc.h"
#include "stm32h7xx_hal_mdma.h"

Go to the source code of this file.

Data Structures

struct | SRAM_HandleTypeDef
SRAM handle Structure definition. More...

Defines

#define | __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
Reset SRAM handle state.

Enumerations

enum HAL_SRAM_StateTypeDef {
HAL_SRAM_STATE_RESET = 0x00U, HAL_SRAM_STATE_READY = 0x01U, HAL_SRAM_STATE_BUSY = 0x02U, HAL_SRAM_STATE_ERROR = 0x03U,
HAL_SRAM_STATE_PROTECTED = 0x04U
}
HAL SRAM State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_SRAM_Init (SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Performs the SRAM device initialization sequence.
HAL_StatusTypeDef | HAL_SRAM_DeInit (SRAM_HandleTypeDef *hsram)
Performs the SRAM device De-initialization sequence.
__weak void | HAL_SRAM_MspInit (SRAM_HandleTypeDef *hsram)
SRAM MSP Init.
__weak void | HAL_SRAM_MspDeInit (SRAM_HandleTypeDef *hsram)
SRAM MSP DeInit.
HAL_StatusTypeDef | HAL_SRAM_Read_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
Reads 8-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
Writes 8-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
Reads 16-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
Writes 16-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads 32-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes 32-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads a Words data from the SRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SRAM_Write_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes a Words data buffer to SRAM memory using DMA transfer.
void | HAL_SRAM_DMA_XferCpltCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete callback.
void | HAL_SRAM_DMA_XferErrorCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete error callback.
HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Enable (SRAM_HandleTypeDef *hsram)
Enables dynamically SRAM write operation.
HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Disable (SRAM_HandleTypeDef *hsram)
Disables dynamically SRAM write operation.
HAL_SRAM_StateTypeDef | HAL_SRAM_GetState (SRAM_HandleTypeDef *hsram)
Returns the SRAM controller state.

Detailed Description

Header file of SRAM HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_sram.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_swpmi.h File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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stm32h7xx_hal_swpmi.h File Reference

Header file of SWPMI HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SWPMI_InitTypeDef
SWPMI Init Structure definition. More...
struct | SWPMI_HandleTypeDef
SWPMI handle Structure definition. More...

Defines

#define | HAL_SWPMI_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_SWPMI_ERROR_CRC ((uint32_t)0x00000004)
#define | HAL_SWPMI_ERROR_OVR ((uint32_t)0x00000008)
#define | HAL_SWPMI_ERROR_UDR ((uint32_t)0x0000000C)
#define | HAL_SWPMI_ERROR_DMA ((uint32_t)0x00000010)
#define | SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000)
#define | SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS
#define | SWPMI_TX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_TX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_TX_MULTI_SOFTWAREBUFFER SWPMI_CR_TXMODE
#define | SWPMI_RX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_RX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_RX_MULTI_SOFTWAREBUFFER SWPMI_CR_RXMODE
#define | SWPMI_FLAG_RXBFF SWPMI_ISR_RXBFF
#define | SWPMI_FLAG_TXBEF SWPMI_ISR_TXBEF
#define | SWPMI_FLAG_RXBERF SWPMI_ISR_RXBERF
#define | SWPMI_FLAG_RXOVRF SWPMI_ISR_RXOVRF
#define | SWPMI_FLAG_TXUNRF SWPMI_ISR_TXUNRF
#define | SWPMI_FLAG_RXNE SWPMI_ISR_RXNE
#define | SWPMI_FLAG_TXE SWPMI_ISR_TXE
#define | SWPMI_FLAG_TCF SWPMI_ISR_TCF
#define | SWPMI_FLAG_SRF SWPMI_ISR_SRF
#define | SWPMI_FLAG_SUSP SWPMI_ISR_SUSP
#define | SWPMI_FLAG_DEACTF SWPMI_ISR_DEACTF
#define | SWPMI_FLAG_RDYF SWPMI_ISR_RDYF
#define | SWPMI_IT_RDYIE SWPMI_IER_RDYIE
#define | SWPMI_IT_SRIE SWPMI_IER_SRIE
#define | SWPMI_IT_TCIE SWPMI_IER_TCIE
#define | SWPMI_IT_TIE SWPMI_IER_TIE
#define | SWPMI_IT_RIE SWPMI_IER_RIE
#define | SWPMI_IT_TXUNRIE SWPMI_IER_TXUNRIE
#define | SWPMI_IT_RXOVRIE SWPMI_IER_RXOVRIE
#define | SWPMI_IT_RXBERIE SWPMI_IER_RXBERIE
#define | SWPMI_IT_TXBEIE SWPMI_IER_TXBEIE
#define | SWPMI_IT_RXBFIE SWPMI_IER_RXBFIE
#define | __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET)
Reset SWPMI handle state.
#define | __HAL_SWPMI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
Enable the SWPMI peripheral.
#define | __HAL_SWPMI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
Disable the SWPMI peripheral.
#define | __HAL_SWPMI_TRANSCEIVER_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)
Enable/Disable the SWPMI transceiver.
#define | __HAL_SWPMI_TRANSCEIVER_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)
#define | __HAL_SWPMI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__))
Check whether the specified SWPMI flag is set or not.
#define | __HAL_SWPMI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__))
Clear the specified SWPMI ISR flag.
#define | __HAL_SWPMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
Enable the specified SWPMI interrupt.
#define | __HAL_SWPMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
Disable the specified SWPMI interrupt.
#define | __HAL_SWPMI_GET_IT(__HANDLE__, __IT__) (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__))
Check whether the specified SWPMI interrupt has occurred or not.
#define | __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET)
Check whether the specified SWPMI interrupt source is enabled or not.
#define | IS_SWPMI_VOLTAGE_CLASS(__CLASS__)
#define | IS_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 63))
#define | IS_SWPMI_TX_BUFFERING_MODE(__MODE__)
#define | IS_SWPMI_RX_BUFFERING_MODE(__MODE__)

Enumerations

enum HAL_SWPMI_StateTypeDef {
HAL_SWPMI_STATE_RESET = 0x00, HAL_SWPMI_STATE_READY = 0x01, HAL_SWPMI_STATE_BUSY = 0x02, HAL_SWPMI_STATE_BUSY_TX = 0x12,
HAL_SWPMI_STATE_BUSY_RX = 0x22, HAL_SWPMI_STATE_BUSY_TX_RX = 0x32, HAL_SWPMI_STATE_TIMEOUT = 0x03, HAL_SWPMI_STATE_ERROR = 0x04
}
HAL SWPMI State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_SWPMI_Init (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.
HAL_StatusTypeDef | HAL_SWPMI_DeInit (SWPMI_HandleTypeDef *hswpmi)
De-initialize the SWPMI peripheral.
void | HAL_SWPMI_MspInit (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI MSP.
void | HAL_SWPMI_MspDeInit (SWPMI_HandleTypeDef *hswpmi)
DeInitialize the SWPMI MSP.
HAL_StatusTypeDef | HAL_SWPMI_Transmit (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Receive (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_DMAStop (SWPMI_HandleTypeDef *hswpmi)
Stop all DMA transfers.
HAL_StatusTypeDef | HAL_SWPMI_EnableLoopback (SWPMI_HandleTypeDef *hswpmi)
Enable the Loopback mode.
HAL_StatusTypeDef | HAL_SWPMI_DisableLoopback (SWPMI_HandleTypeDef *hswpmi)
Disable the Loopback mode.
void | HAL_SWPMI_IRQHandler (SWPMI_HandleTypeDef *hswpmi)
Handle SWPMI interrupt request.
void | HAL_SWPMI_TxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Transfer completed callback.
void | HAL_SWPMI_TxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Half Transfer completed callback.
void | HAL_SWPMI_RxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Transfer completed callback.
void | HAL_SWPMI_RxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Half Transfer completed callback.
void | HAL_SWPMI_ErrorCallback (SWPMI_HandleTypeDef *hswpmi)
SWPMI error callback.
HAL_SWPMI_StateTypeDef | HAL_SWPMI_GetState (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI handle state.
uint32_t | HAL_SWPMI_GetError (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI error code.

Detailed Description

Header file of SWPMI HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_swpmi.h.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_tim.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32h7xx_hal_tim.h File Reference

Header file of TIM HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_tim_ex.h"

Go to the source code of this file.

Data Structures

struct | TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition. More...
struct | TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition. More...
struct | TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition. More...
struct | TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition. More...
struct | TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition. More...
struct | TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition. More...
struct | TIM_ClearInputConfigTypeDef
Clear Input Configuration Handle Structure definition. More...
struct | TIM_MasterConfigTypeDef
TIM Master configuration Structure definition. More...
struct | TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition. More...
struct | TIM_BreakDeadTimeConfigTypeDef
TIM Break input(s) and Dead time configuration Structure definition. More...
struct | TIM_HandleTypeDef
TIM Time Base Handle Structure definition. More...

Defines

#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG
#define | TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G
#define | TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U)
#define | TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P)
#define | TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
#define | TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP)
#define | TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000U)
#define | TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000U)
#define | TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0)
#define | TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1)
#define | TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS)
#define | TIM_COUNTERMODE_UP ((uint32_t)0x0000U)
#define | TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define | TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define | TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
#define | TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000U)
#define | TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
#define | TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
#define | TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000U)
#define | TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
#define | TIM_AUTORELOAD_PRELOAD_DISABLE ((uint32_t)0x0000U)
#define | TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE)
#define | TIM_OCFAST_DISABLE ((uint32_t)0x0000U)
#define | TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
#define | TIM_OCPOLARITY_HIGH ((uint32_t)0x0000U)
#define | TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
#define | TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000U)
#define | TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
#define | TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
#define | TIM_OCIDLESTATE_RESET ((uint32_t)0x0000U)
#define | TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
#define | TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000U)
#define | TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0)
#define | TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1)
#define | TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S)
#define | TIM_ICPSC_DIV1 ((uint32_t)0x0000U)
#define | TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0)
#define | TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1)
#define | TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC)
#define | TIM_OPMODE_SINGLE (TIM_CR1_OPM)
#define | TIM_OPMODE_REPETITIVE ((uint32_t)0x0000U)
#define | TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
#define | TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
#define | TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_IT_UPDATE (TIM_DIER_UIE)
#define | TIM_IT_CC1 (TIM_DIER_CC1IE)
#define | TIM_IT_CC2 (TIM_DIER_CC2IE)
#define | TIM_IT_CC3 (TIM_DIER_CC3IE)
#define | TIM_IT_CC4 (TIM_DIER_CC4IE)
#define | TIM_IT_COM (TIM_DIER_COMIE)
#define | TIM_IT_TRIGGER (TIM_DIER_TIE)
#define | TIM_IT_BREAK (TIM_DIER_BIE)
#define | TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
#define | TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000U)
#define | TIM_DMA_UPDATE (TIM_DIER_UDE)
#define | TIM_DMA_CC1 (TIM_DIER_CC1DE)
#define | TIM_DMA_CC2 (TIM_DIER_CC2DE)
#define | TIM_DMA_CC3 (TIM_DIER_CC3DE)
#define | TIM_DMA_CC4 (TIM_DIER_CC4DE)
#define | TIM_DMA_COM (TIM_DIER_COMDE)
#define | TIM_DMA_TRIGGER (TIM_DIER_TDE)
#define | TIM_FLAG_UPDATE (TIM_SR_UIF)
#define | TIM_FLAG_CC1 (TIM_SR_CC1IF)
#define | TIM_FLAG_CC2 (TIM_SR_CC2IF)
#define | TIM_FLAG_CC3 (TIM_SR_CC3IF)
#define | TIM_FLAG_CC4 (TIM_SR_CC4IF)
#define | TIM_FLAG_CC5 (TIM_SR_CC5IF)
#define | TIM_FLAG_CC6 (TIM_SR_CC6IF)
#define | TIM_FLAG_COM (TIM_SR_COMIF)
#define | TIM_FLAG_TRIGGER (TIM_SR_TIF)
#define | TIM_FLAG_BREAK (TIM_SR_BIF)
#define | TIM_FLAG_BREAK2 (TIM_SR_B2IF)
#define | TIM_FLAG_SYSTEM_BREAK (TIM_SR_SBIF)
#define | TIM_FLAG_CC1OF (TIM_SR_CC1OF)
#define | TIM_FLAG_CC2OF (TIM_SR_CC2OF)
#define | TIM_FLAG_CC3OF (TIM_SR_CC3OF)
#define | TIM_FLAG_CC4OF (TIM_SR_CC4OF)
#define | TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
#define | TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
#define | TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000U)
#define | TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
#define | TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
#define | TIM_OSSR_DISABLE ((uint32_t)0x0000U)
#define | TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
#define | TIM_OSSI_DISABLE ((uint32_t)0x0000U)
#define | TIM_LOCKLEVEL_OFF ((uint32_t)0x0000U)
#define | TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
#define | TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
#define | TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
#define | TIM_BREAK_ENABLE (TIM_BDTR_BKE)
#define | TIM_BREAK_DISABLE ((uint32_t)0x0000U)
#define | TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000U)
#define | TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
#define | TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
#define | TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000U)
#define | TIM_TRGO_RESET ((uint32_t)0x0000U)
#define | TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
#define | TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
#define | TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
#define | TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
#define | TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define | TIM_TRGO2_RESET ((uint32_t)0x00000000U)
#define | TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
#define | TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
#define | TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
#define | TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
#define | TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080U)
#define | TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000U)
#define | TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000U)
#define | TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
#define | TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
#define | TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
#define | TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
#define | TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
#define | TIM_TS_ITR0 ((uint32_t)0x0000U)
#define | TIM_TS_ITR1 ((uint32_t)0x0010U)
#define | TIM_TS_ITR2 ((uint32_t)0x0020U)
#define | TIM_TS_ITR3 ((uint32_t)0x0030U)
#define | TIM_TS_TI1F_ED ((uint32_t)0x0040U)
#define | TIM_TS_TI1FP1 ((uint32_t)0x0050U)
#define | TIM_TS_TI2FP2 ((uint32_t)0x0060U)
#define | TIM_TS_ETRF ((uint32_t)0x0070U)
#define | TIM_TS_NONE ((uint32_t)0xFFFFU)
#define | TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_TI1SELECTION_CH1 ((uint32_t)0x0000U)
#define | TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
#define | TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
#define | TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
#define | TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
#define | TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
#define | TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
#define | TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
#define | TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
#define | TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
#define | TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
#define | TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
#define | TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
#define | TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
#define | TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
#define | TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
#define | TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
#define | TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
#define | TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
#define | TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)
#define | TIM_DMA_ID_UPDATE ((uint16_t) 0x0U)
#define | TIM_DMA_ID_CC1 ((uint16_t) 0x1U)
#define | TIM_DMA_ID_CC2 ((uint16_t) 0x2U)
#define | TIM_DMA_ID_CC3 ((uint16_t) 0x3U)
#define | TIM_DMA_ID_CC4 ((uint16_t) 0x4U)
#define | TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U)
#define | TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U)
#define | TIM_CCx_ENABLE ((uint32_t)0x0001U)
#define | TIM_CCx_DISABLE ((uint32_t)0x0000U)
#define | TIM_CCxN_ENABLE ((uint32_t)0x0004U)
#define | TIM_CCxN_DISABLE ((uint32_t)0x0000U)
#define | __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
Reset TIM handle state.
#define | __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
Enable the TIM peripheral.
#define | __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
Set the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
Enable the TIM main Output.
#define | TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define | TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
#define | __HAL_TIM_DISABLE(__HANDLE__)
Disable the TIM peripheral.
#define | __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_MOE_DISABLE(__HANDLE__)
Disable the TIM main Output.
#define | __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) ((__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE))
Disable the TIM main Output.
#define | __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
Enable the specified TIM interrupt.
#define | __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
Disable the specified TIM interrupt.
#define | __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
Enable the specified DMA request.
#define | __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
Disable the specified DMA request.
#define | __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
Check whether the specified TIM interrupt flag is set or not.
#define | __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the specified TIM interrupt flag.
#define | __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified TIM interrupt source is enabled or not.
#define | __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(uint32_t)(__INTERRUPT__))
Clear the TIM interrupt pending bits.
#define | __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
Indicates whether or not the TIM Counter is used as downcounter.
#define | __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
Set the TIM Prescaler on runtime.
#define | TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
#define | TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
#define | TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
#define | TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)
#define | __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
Set the TIM Counter Register value on runtime.
#define | __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
Get the TIM Counter Register value on runtime.
#define | __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)
Set the TIM Autoreload Register value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
Get the TIM Autoreload Register value on runtime.
#define | __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__)
Set the TIM Clock Division value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
Get the TIM Clock Division value on runtime.
#define | __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)
Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
#define | __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)
Get the TIM Input Capture prescaler on runtime.
#define | __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Set the TIM Capture x input polarity on runtime.
#define | __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__)
Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
#define | __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__)
Get the TIM Capture Compare Register value on runtime.
#define | IS_TIM_CLEARINPUT_SOURCE(__MODE__)
#define | IS_TIM_DMA_BASE(__BASE__)
#define | IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define | IS_TIM_COUNTER_MODE(__MODE__)
#define | IS_TIM_CLOCKDIVISION_DIV(__DIV__)
#define | IS_TIM_AUTORELOAD_PRELOAD(PRELOAD)
#define | IS_TIM_FAST_STATE(__STATE__)
#define | IS_TIM_OC_POLARITY(__POLARITY__)
#define | IS_TIM_OCN_POLARITY(__POLARITY__)
#define | IS_TIM_OCIDLE_STATE(__STATE__)
#define | IS_TIM_OCNIDLE_STATE(__STATE__)
#define | IS_TIM_IC_POLARITY(__POLARITY__)
#define | IS_TIM_IC_SELECTION(__SELECTION__)
#define | IS_TIM_IC_PRESCALER(__PRESCALER__)
#define | IS_TIM_OPM_MODE(__MODE__)
#define | IS_TIM_ENCODER_MODE(__MODE__)
#define | IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define | IS_TIM_CHANNELS(__CHANNEL__)
#define | IS_TIM_OPM_CHANNELS(__CHANNEL__)
#define | IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__)
#define | IS_TIM_CLOCKSOURCE(__CLOCK__)
#define | IS_TIM_CLOCKPOLARITY(__POLARITY__)
#define | IS_TIM_CLOCKPRESCALER(__PRESCALER__)
#define | IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
#define | IS_TIM_CLEARINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__)
#define | IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_OSSR_STATE(__STATE__)
#define | IS_TIM_OSSI_STATE(__STATE__)
#define | IS_TIM_LOCK_LEVEL(__LEVEL__)
#define | IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xF)
#define | IS_TIM_BREAK_STATE(__STATE__)
#define | IS_TIM_BREAK_POLARITY(__POLARITY__)
#define | IS_TIM_BREAK2_STATE(__STATE__)
#define | IS_TIM_BREAK2_POLARITY(__POLARITY__)
#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__)
#define | IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
#define | IS_TIM_TRGO_SOURCE(__SOURCE__)
#define | IS_TIM_TRGO2_SOURCE(__SOURCE__)
#define | IS_TIM_MSM_STATE(__STATE__)
#define | IS_TIM_SLAVE_MODE(__MODE__)
#define | IS_TIM_PWM_MODE(__MODE__)
#define | IS_TIM_OC_MODE(__MODE__)
#define | IS_TIM_TRIGGER_SELECTION(__SELECTION__)
#define | IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__)
#define | IS_TIM_TRIGGERPOLARITY(__POLARITY__)
#define | IS_TIM_TRIGGERPRESCALER(__PRESCALER__)
#define | IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_TI1SELECTION(__TI1SELECTION__)
#define | IS_TIM_DMA_LENGTH(__LENGTH__)
#define | IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
#define | IS_TIM_BREAK_SYSTEM(__CONFIG__)

Enumerations

enum HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
}
HAL Active channel structures definition. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initialize the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initialize the TIM Time Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Time Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Time Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Time Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Time Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Time Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Time Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Time Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initialize the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initialize the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initialize the TIM PWM mode according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initialize the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initialize the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initialize the TIM Input Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement on in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement on in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initialize the TIM One Pulse mode according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM One Pulse mode.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initialize the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initialize the TIM Encoder Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initialize the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.
void | HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.
HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initialize the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initialize the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initialize the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initialize the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.
__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
TIM error callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Output Compare handle state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM handle state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode handle state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode state.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM Output Compare 1 configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM Output Compare 2 configuration.
void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM Output Compare 3 configuration.
void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM Output Compare 4 configuration.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | HAL_TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | HAL_TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | HAL_TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.

Detailed Description

Header file of TIM HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_tim.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_tim_ex.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_hal_tim_ex.h File Reference

Header file of TIM HAL Extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | TIM_HallSensor_InitTypeDef
TIM Hall sensor Configuration Structure definition. More...
struct | TIMEx_BreakInputConfigTypeDef
TIM Break/Break2 input configuration. More...

Defines

#define | TIM_CHANNEL_1 ((uint32_t)0x0000U)
#define | TIM_CHANNEL_2 ((uint32_t)0x0004U)
#define | TIM_CHANNEL_3 ((uint32_t)0x0008U)
#define | TIM_CHANNEL_4 ((uint32_t)0x000CU)
#define | TIM_CHANNEL_5 ((uint32_t)0x0010U)
#define | TIM_CHANNEL_6 ((uint32_t)0x0014U)
#define | TIM_CHANNEL_ALL ((uint32_t)0x003CU)
#define | TIM_OCMODE_TIMING ((uint32_t)0x0000U)
#define | TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
#define | TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
#define | TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U)
#define | TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002U)
#define | TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U)
#define | TIM_BREAK2_DISABLE ((uint32_t)0x00000000U)
#define | TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
#define | TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000U)
#define | TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)
#define | TIM_TS_ITR4 ((uint32_t)0x0100000)
#define | TIM_TS_ITR5 ((uint32_t)0x0100010)
#define | TIM_TS_ITR6 ((uint32_t)0x0100020)
#define | TIM_TS_ITR7 ((uint32_t)0x0100030)
#define | TIM_TS_ITR8 ((uint32_t)0x0100040)
#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG
#define | TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G
#define | TIM_DMABASE_CR1 (0x00000000U)
#define | TIM_DMABASE_CR2 (0x00000001U)
#define | TIM_DMABASE_SMCR (0x00000002U)
#define | TIM_DMABASE_DIER (0x00000003U)
#define | TIM_DMABASE_SR (0x00000004U)
#define | TIM_DMABASE_EGR (0x00000005U)
#define | TIM_DMABASE_CCMR1 (0x00000006U)
#define | TIM_DMABASE_CCMR2 (0x00000007U)
#define | TIM_DMABASE_CCER (0x00000008U)
#define | TIM_DMABASE_CNT (0x00000009U)
#define | TIM_DMABASE_PSC (0x0000000AU)
#define | TIM_DMABASE_ARR (0x0000000BU)
#define | TIM_DMABASE_RCR (0x0000000CU)
#define | TIM_DMABASE_CCR1 (0x0000000DU)
#define | TIM_DMABASE_CCR2 (0x0000000EU)
#define | TIM_DMABASE_CCR3 (0x0000000FU)
#define | TIM_DMABASE_CCR4 (0x00000010U)
#define | TIM_DMABASE_BDTR (0x00000011U)
#define | TIM_DMABASE_DCR (0x00000012U)
#define | TIM_DMABASE_DMAR (0x00000013U)
#define | TIM_DMABASE_AF1 (0x00000014U)
#define | TIM_DMABASE_CCMR3 (0x00000015U)
#define | TIM_DMABASE_CCR5 (0x00000016U)
#define | TIM_DMABASE_CCR6 (0x00000017U)
#define | TIM_DMABASE_AF2 (0x00000018U)
#define | TIM_DMABASE_AF3 (0x00000019U)
#define | TIM_DMABASE_TISEL (0x0000001AU)
#define | TIM_TIM1_ETR_GPIO (0x00000000) /* !< TIM1_ETR is connected to GPIO */
#define | TIM_TIM1_ETR_ADC1_AWD1 (0x0000C000) /* !< TIM1_ETR is connected to ADC1 AWD1 */
#define | TIM_TIM1_ETR_ADC1_AWD2 (0x00010000) /* !< TIM1_ETR is connected to ADC1 AWD2 */
#define | TIM_TIM1_ETR_ADC1_AWD3 (0x00014000) /* !< TIM1_ETR is connected to ADC1 AWD3 */
#define | TIM_TIM1_ETR_ADC3_AWD1 (0x00018000) /* !< TIM1_ETR is connected to ADC3 AWD1 */
#define | TIM_TIM1_ETR_ADC3_AWD2 (0x0001C000) /* !< TIM1_ETR is connected to ADC3 AWD2 */
#define | TIM_TIM1_ETR_ADC3_AWD3 (0x00020000) /* !< TIM1_ETR is connected to ADC3 AWD3 */
#define | TIM_TIM1_ETR_COMP1_OUT (0x00004000) /* !< TIM1_ETR is connected to COMP1 OUT */
#define | TIM_TIM1_ETR_COMP2_OUT (0x00008000) /* !< TIM1_ETR is connected to COMP2 OUT */
#define | TIM_TIM8_ETR_GPIO (0x00000000) /* !< TIM8_ETR is connected to GPIO */
#define | TIM_TIM8_ETR_ADC2_AWD1 (0x0000C000) /* !< TIM8_ETR is connected to ADC2 AWD1 */
#define | TIM_TIM8_ETR_ADC2_AWD2 (0x00010000) /* !< TIM8_ETR is connected to ADC2 AWD2 */
#define | TIM_TIM8_ETR_ADC2_AWD3 (0x00014000) /* !< TIM8_ETR is connected to ADC2 AWD3 */
#define | TIM_TIM8_ETR_ADC3_AWD1 (0x00018000) /* !< TIM8_ETR is connected to ADC3 AWD1 */
#define | TIM_TIM8_ETR_ADC3_AWD2 (0x0001C000) /* !< TIM8_ETR is connected to ADC3 AWD2 */
#define | TIM_TIM8_ETR_ADC3_AWD3 (0x00020000) /* !< TIM8_ETR is connected to ADC3 AWD3 */
#define | TIM_TIM8_ETR_COMP1_OUT (0x00004000) /* !< TIM8_ETR is connected to COMP1 OUT */
#define | TIM_TIM8_ETR_COMP2_OUT (0x00008000) /* !< TIM8_ETR is connected to COMP2 OUT */
#define | TIM_TIM2_ETR_GPIO (0x00000000) /* !< TIM2_ETR is connected to GPIO */
#define | TIM_TIM2_ETR_COMP1_OUT (0x0000C000) /* !< TIM2_ETR is connected to COMP1 OUT */
#define | TIM_TIM2_ETR_COMP2_OUT (0x00010000) /* !< TIM2_ETR is connected to COMP2 OUT */
#define | TIM_TIM2_ETR_RCC_LSE (0x00014000) /* !< TIM2_ETR is connected to RCC LSE */
#define | TIM_TIM2_ETR_SAI1_FSA (0x00018000) /* !< TIM2_ETR is connected to SAI1 FS_A */
#define | TIM_TIM2_ETR_SAI1_FSB (0x0001C000) /* !< TIM2_ETR is connected to SAI1 FS_B */
#define | TIM_TIM3_ETR_GPIO (0x00000000) /* !< TIM3_ETR is connected to GPIO */
#define | TIM_TIM3_ETR_COMP1_OUT (0x00000000) /* !< TIM3_ETR is connected to COMP1 OUT */
#define | TIM_TIM5_ETR_GPIO (0x00000000) /* !< TIM5_ETR is connected to GPIO */
#define | TIM_TIM5_ETR_SAI2_FSA (0x00000000) /* !< TIM5_ETR is connected to SAI2 FS_A */
#define | TIM_TIM5_ETR_SAI2_FSB (0x00000000) /* !< TIM5_ETR is connected to SAI2 FS_B */
#define | TIM_TIM1_BKR_GPIO (0x00000000) /* !< TIM1_BKR is connected to GPIO */
#define | TIM_TIM1_BKR_COMP1_OUT (0x00000002) /* !< TIM1_BKR is connected to COMP1 OUT */
#define | TIM_TIM1_BKR_COMP2_OUT (0x00000004) /* !< TIM1_BKR is connected to COMP2 OUT */
#define | TIM_TIM1_BKR_DFSDM_BRK0 (0x00000000) /* !< TIM1_BKR is connected to DFSDM BRK0 */
#define | TIM_TIM8_BKR_GPIO (0x00000000) /* !< TIM8_BKR is connected to GPIO */
#define | TIM_TIM8_BKR_COMP1_OUT (0x00000002) /* !< TIM8_BKR is connected to COMP1 OUT */
#define | TIM_TIM8_BKR_COMP2_OUT (0x00000004) /* !< TIM8_BKR is connected to COMP2 OUT */
#define | TIM_TIM8_BKR_DFSDM_BRK2 (0x00000000) /* !< TIM8_BKR is connected to DFSDM BRK2 */
#define | TIM_TIM15_BKR_GPIO (0x00000000) /* !< TIM15_BKR is connected to GPIO */
#define | TIM_TIM15_BKR_COMP1_OUT (0x00000002) /* !< TIM15_BKR is connected to COMP1 OUT */
#define | TIM_TIM15_BKR_COMP2_OUT (0x00000004) /* !< TIM15_BKR is connected to COMP2 OUT */
#define | TIM_TIM15_BKR_DFSDM_BRK0 (0x00000000) /* !< TIM15_BKR is connected to DFSDM BRK0 */
#define | TIM_TIM16_BKR_GPIO (0x00000000) /* !< TIM16_BKR is connected to GPIO */
#define | TIM_TIM16_BKR_COMP1_OUT (0x00000002) /* !< TIM16_BKR is connected to COMP1 OUT */
#define | TIM_TIM16_BKR_COMP2_OUT (0x00000004) /* !< TIM16_BKR is connected to COMP2 OUT */
#define | TIM_TIM16_BKR_DFSDM_BRK1 (0x00000000) /* !< TIM16_BKR is connected to DFSDM BRK1 */
#define | TIM_TIM17_BKR_GPIO (0x00000000) /* !< TIM17_BKR is connected to GPIO */
#define | TIM_TIM17_BKR_COMP1_OUT (0x00000002) /* !< TIM17_BKR is connected to COMP1 OUT */
#define | TIM_TIM17_BKR_COMP2_OUT (0x00000004) /* !< TIM17_BKR is connected to COMP2 OUT */
#define | TIM_TIM17_BKR_DFSDM_BRK2 (0x00000000) /* !< TIM17_BKR is connected to DFSDM BRK2 */
#define | TIM_TIM1_BKR2_GPIO (0x00000000) /* !< TIM1_BKR2 is connected to GPIO */
#define | TIM_TIM1_BKR2_COMP1_OUT (0x00000002) /* !< TIM1_BKR2 is connected to COMP1 OUT */
#define | TIM_TIM1_BKR2_COMP2_OUT (0x00000004) /* !< TIM1_BKR2 is connected to COMP2 OUT */
#define | TIM_TIM1_BKR2_DFSDM_BRK1 (0x00000000) /* !< TIM1_BKR2 is connected to DFSDM BRK0 */
#define | TIM_TIM8_BKR2_GPIO (0x00000000) /* !< TIM8_BKR2 is connected to GPIO */
#define | TIM_TIM8_BKR2_COMP1_OUT (0x00000002) /* !< TIM8_BKR2 is connected to COMP1 OUT */
#define | TIM_TIM8_BKR2_COMP2_OUT (0x00000004) /* !< TIM8_BKR2 is connected to COMP2 OUT */
#define | TIM_TIM8_BKR2_DFSDM_BRK3 (0x00000000) /* !< TIM8_BKR2 is connected to DFSDM BRK3 */
#define | TIM_TIM1_TI1_GPIO (0x00000000) /* !< TIM1_TI1 is connected to GPIO */
#define | TIM_TIM1_TI1_COMP1_OUT (0x00000001) /* !< TIM1_TI1 is connected to COMP1 OUT */
#define | TIM_TIM8_TI1_GPIO (0x00000000) /* !< TIM8_TI1 is connected to GPIO */
#define | TIM_TIM8_TI1_COMP2_OUT (0x00000001) /* !< TIM8_TI1 is connected to COMP2 OUT */
#define | TIM_TIM2_TI4_GPIO (0x00000000) /* !< TIM2_TI4 is connected to GPIO */
#define | TIM_TIM2_TI4_COMP1_OUT (0x01000000) /* !< TIM2_TI4 is connected to COMP1 OUT */
#define | TIM_TIM2_TI4_COMP2_OUT (0x02000000) /* !< TIM2_TI4 is connected to COMP2 OUT */
#define | TIM_TIM2_TI4_COMP1COMP2_OUT (0x03000000) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */
#define | TIM_TIM3_TI1_GPIO (0x00000000) /* !< TIM3_TI1 is connected to GPIO */
#define | TIM_TIM3_TI1_COMP1_OUT (0x00000001) /* !< TIM3_TI1 is connected to COMP1 OUT */
#define | TIM_TIM3_TI1_COMP2_OUT (0x00000002) /* !< TIM3_TI1 is connected to COMP2 OUT */
#define | TIM_TIM3_TI1_COMP1COMP2_OUT (0x00000003) /* !< TIM3_TI1 is connected to COMP2 OUT OR COMP2 OUT */
#define | TIM_TIM5_TI1_GPIO (0x00000000) /* !< TIM5_TI1 is connected to GPIO */
#define | TIM_TIM5_TI1_CAN_TMP (0x00000001) /* !< TIM5_TI1 is connected to CAN TMP */
#define | TIM_TIM5_TI1_CAN_RTP (0x00000002) /* !< TIM5_TI1 is connected to CAN RTP */
#define | TIM_TIM15_TI1_GPIO (0x00000000) /* !< TIM15_TI1 is connected to GPIO */
#define | TIM_TIM15_TI1_TIM2_CH1 (0x00000001) /* !< TIM15_TI1 is connected to TIM2 CH1 */
#define | TIM_TIM15_TI1_TIM3_CH1 (0x00000002) /* !< TIM15_TI1 is connected to TIM3 CH1 */
#define | TIM_TIM15_TI1_TIM4_CH1 (0x00000003) /* !< TIM15_TI1 is connected to TIM4 CH1 */
#define | TIM_TIM15_TI1_RCC_LSE (0x00000004) /* !< TIM15_TI1 is connected to RCC LSE */
#define | TIM_TIM15_TI1_RCC_CSI (0x00000005) /* !< TIM15_TI1 is connected to RCC CSI */
#define | TIM_TIM15_TI1_RCC_MCO2 (0x00000006) /* !< TIM15_TI1 is connected to RCC MCO2 */
#define | TIM_TIM15_TI2_GPIO (0x00000000) /* !< TIM15_TI2 is connected to GPIO */
#define | TIM_TIM15_TI2_TIM2_CH2 (0x00000100) /* !< TIM15_TI2 is connected to TIM2 CH2 */
#define | TIM_TIM15_TI2_TIM3_CH2 (0x00000200) /* !< TIM15_TI2 is connected to TIM3 CH2 */
#define | TIM_TIM15_TI2_TIM4_CH2 (0x00000300) /* !< TIM15_TI2 is connected to TIM4 CH2 */
#define | TIM_TIM16_TI1_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */
#define | TIM_TIM16_TI1_RCC_LSI (0x00000001) /* !< TIM16 TI1 is connected to RCC LSI */
#define | TIM_TIM16_TI1_RCC_LSE (0x00000002) /* !< TIM16 TI1 is connected to RCC LSE */
#define | TIM_TIM16_TI1_WKUP_IT (0x00000003) /* !< TIM16 TI1 is connected to WKUP_IT */
#define | TIM_TIM17_TI1_GPIO (0x00000000) /* !< TIM17 TI1 is connected to GPIO */
#define | TIM_TIM17_TI1_SPDIF_FS (0x00000001) /* !< TIM17 TI1 is connected to RCC LSI */
#define | TIM_TIM17_TI1_RCC_HSE1MHZ (0x00000002) /* !< TIM17 TI1 is connected to RCC LSE */
#define | TIM_TIM17_TI1_RCC_MCO1 (0x00000003) /* !< TIM17 TI1 is connected to RCC MCO1 */
#define | TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
#define | TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
#define | TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
#define | TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
#define | TIM_BREAKINPUT_BRK ((uint32_t)(0x00000001)) /* !< Timer break input */
#define | TIM_BREAKINPUT_BRK2 ((uint32_t)(0x00000002)) /* !< Timer break2 input */
#define | TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin */
#define | TIM_BREAKINPUTSOURCE_COMP1 ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_COMP2 ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)(0x00000000)) /* !< Break input source is disabled */
#define | TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)(0x00000001)) /* !< Break input source is enabled */
#define | TIM_BREAKINPUTSOURCE_POLARITY_LOW ((uint32_t)(0x00000001)) /* !< Break input source is active low */
#define | TIM_BREAKINPUTSOURCE_POLARITY_HIGH ((uint32_t)(0x00000000)) /* !< Break input source is active_high */
#define | IS_TIM_REMAP(__REMAP__) (((__REMAP__) <= (uint32_t)0x0001C01F))
#define | IS_TIM_BREAKINPUT(__BREAKINPUT__)
#define | IS_TIM_BREAKINPUTSOURCE(__SOURCE__)
#define | IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)
#define | IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)
#define | IS_TIM_TISEL(TISEL)
#define | IS_TIM_BKR2REMAP(BK2RREMAP)
#define | IS_TIM_BKRREMAP(BKRREMAP)
#define | IS_TIM_ETRREMAP(ETRREMAP)

Functions

HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Start the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complemetary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
Configures the break input source.
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIMx Remapping input capabilities.
HAL_StatusTypeDef | HAL_TIMEx_TISelection (TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
Configures the TIMx input Selection capabilities.
HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t Channels)
Group channel 5 and channel 1, 2 or 3.
__weak void | HAL_TIMEx_CommutationCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface state.
void | HAL_TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.

Detailed Description

Header file of TIM HAL Extended module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_tim_ex.h.

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STM32H753xx HAL User Manual: stm32h7xx_hal_uart.h File Reference

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stm32h7xx_hal_uart.h File Reference

Header file of UART HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_uart_ex.h"

Go to the source code of this file.

Data Structures

struct | UART_InitTypeDef
UART Init Structure definition. More...
struct | UART_AdvFeatureInitTypeDef
UART Advanced Features initalization structure definition. More...
struct | UART_HandleTypeDef
UART handle Structure definition. More...

Defines

#define | UART_STOPBITS_0_5 USART_CR2_STOP_0
#define | UART_STOPBITS_1 ((uint32_t)0x00000000U)
#define | UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | UART_STOPBITS_2 USART_CR2_STOP_1
#define | UART_PARITY_NONE ((uint32_t)0x00000000U)
#define | UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | UART_HWCONTROL_NONE ((uint32_t)0x00000000U)
#define | UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
#define | UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
#define | UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
#define | UART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | UART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | UART_STATE_DISABLE ((uint32_t)0x00000000U)
#define | UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
#define | UART_OVERSAMPLING_16 ((uint32_t)0x00000000U)
#define | UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
#define | UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000U)
#define | UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
#define | UART_PRESCALER_DIV1 ((uint32_t)0x00000000U)
#define | UART_PRESCALER_DIV2 ((uint32_t)0x00000001U)
#define | UART_PRESCALER_DIV4 ((uint32_t)0x00000002U)
#define | UART_PRESCALER_DIV6 ((uint32_t)0x00000003U)
#define | UART_PRESCALER_DIV8 ((uint32_t)0x00000004U)
#define | UART_PRESCALER_DIV10 ((uint32_t)0x00000005U)
#define | UART_PRESCALER_DIV12 ((uint32_t)0x00000006U)
#define | UART_PRESCALER_DIV16 ((uint32_t)0x00000007U)
#define | UART_PRESCALER_DIV32 ((uint32_t)0x00000008U)
#define | UART_PRESCALER_DIV64 ((uint32_t)0x00000009U)
#define | UART_PRESCALER_DIV128 ((uint32_t)0x0000000AU)
#define | UART_PRESCALER_DIV256 ((uint32_t)0x0000000BU)
#define | UART_FIFOMODE_DISABLE ((uint32_t)0x00000000U)
#define | UART_FIFOMODE_ENABLE ((uint32_t)USART_CR1_FIFOEN)
#define | UART_TXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000U)
#define | UART_TXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_TXFTCFG_0)
#define | UART_TXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_TXFTCFG_1)
#define | UART_TXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1))
#define | UART_TXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_TXFTCFG_2)
#define | UART_TXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0))
#define | UART_RXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000U)
#define | UART_RXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_RXFTCFG_0)
#define | UART_RXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_RXFTCFG_1)
#define | UART_RXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1))
#define | UART_RXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_RXFTCFG_2)
#define | UART_RXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0))
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE)
#define | UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000U)
#define | UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)
#define | UART_LIN_DISABLE ((uint32_t)0x00000000U)
#define | UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN)
#define | UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000U)
#define | UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)
#define | UART_DMA_TX_DISABLE ((uint32_t)0x00000000U)
#define | UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)
#define | UART_DMA_RX_DISABLE ((uint32_t)0x00000000U)
#define | UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)
#define | UART_HALF_DUPLEX_DISABLE ((uint32_t)0x00000000U)
#define | UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL)
#define | UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000U)
#define | UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)
#define | UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ)
#define | UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ)
#define | UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ)
#define | UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)
#define | UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001U)
#define | UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002U)
#define | UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004U)
#define | UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008U)
#define | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010U)
#define | UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020U)
#define | UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040U)
#define | UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080U)
#define | UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)
#define | UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)
#define | UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)
#define | UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)
#define | UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)
#define | UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN)
#define | UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)
#define | UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)
#define | UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM)
#define | UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000U)
#define | UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME)
#define | UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24U)
#define | UART_WAKEUP_ON_ADDRESS ((uint32_t)0x00000000U)
#define | UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1)
#define | UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS)
#define | UART_WAKEUP_ON_RXFIFO_THRESHOLD ((uint32_t)USART_CR3_RXFTIE)
#define | UART_WAKEUP_ON_RXFIFO_FULL ((uint32_t)USART_CR1_RXFFIE)
#define | UART_WAKEUP_ON_TXFIFO_THRESHOLD ((uint32_t)USART_CR3_TXFTIE)
#define | UART_WAKEUP_ON_TXFIFO_EMPTY ((uint32_t)USART_CR1_TXFEIE)
#define | UART_DE_POLARITY_HIGH ((uint32_t)0x00000000U)
#define | UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP)
#define | UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21U)
#define | UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16U)
#define | UART_IT_MASK ((uint32_t)0x001FU)
#define | HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU
#define | UART_FLAG_TXFT USART_ISR_TXFT
#define | UART_FLAG_RXFT USART_ISR_RXFT
#define | UART_FLAG_RXFF USART_ISR_RXFF
#define | UART_FLAG_TXFE USART_ISR_TXFE
#define | UART_FLAG_REACK USART_ISR_REACK
#define | UART_FLAG_TEACK USART_ISR_TEACK
#define | UART_FLAG_WUF USART_ISR_WUF
#define | UART_FLAG_RWU USART_ISR_RWU
#define | UART_FLAG_SBKF USART_ISR_SBKF
#define | UART_FLAG_CMF USART_ISR_CMF
#define | UART_FLAG_BUSY USART_ISR_BUSY
#define | UART_FLAG_ABRF USART_ISR_ABRF
#define | UART_FLAG_ABRE USART_ISR_ABRE
#define | UART_FLAG_RTOF USART_ISR_RTOF
#define | UART_FLAG_CTS USART_ISR_CTS
#define | UART_FLAG_CTSIF USART_ISR_CTSIF
#define | UART_FLAG_LBDF USART_ISR_LBDF
#define | UART_FLAG_TXE USART_ISR_TXE
#define | UART_FLAG_TXFNF USART_ISR_TXE
#define | UART_FLAG_TC USART_ISR_TC
#define | UART_FLAG_RXNE USART_ISR_RXNE
#define | UART_FLAG_RXFNE USART_ISR_RXNE
#define | UART_FLAG_IDLE USART_ISR_IDLE
#define | UART_FLAG_ORE USART_ISR_ORE
#define | UART_FLAG_NE USART_ISR_NE
#define | UART_FLAG_FE USART_ISR_FE
#define | UART_FLAG_PE USART_ISR_PE
#define | UART_IT_PE ((uint32_t)0x0028U)
#define | UART_IT_TXE ((uint32_t)0x0727U)
#define | UART_IT_TC ((uint32_t)0x0626U)
#define | UART_IT_RXNE ((uint32_t)0x0525U)
#define | UART_IT_IDLE ((uint32_t)0x0424U)
#define | UART_IT_LBD ((uint32_t)0x0846U)
#define | UART_IT_CTS ((uint32_t)0x096AU)
#define | UART_IT_CM ((uint32_t)0x112EU)
#define | UART_IT_WUF ((uint32_t)0x1476U)
#define | UART_IT_RXFF ((uint16_t)0x183FU)
#define | UART_IT_TXFE ((uint16_t)0x173EU)
#define | UART_IT_RXFT ((uint16_t)0x1A7CU)
#define | UART_IT_TXFT ((uint16_t)0x1B77U)
#define | UART_IT_ERR ((uint32_t)0x0060U)
Elements values convention: 000000000XXYYYYYb.
#define | UART_IT_ORE ((uint32_t)0x0300U)
Elements values convention: 0000ZZZZ00000000b.
#define | UART_IT_NE ((uint32_t)0x0200U)
#define | UART_IT_FE ((uint32_t)0x0100U)
#define | UART_CLEAR_PEF USART_ICR_PECF
#define | UART_CLEAR_FEF USART_ICR_FECF
#define | UART_CLEAR_NEF USART_ICR_NCF
#define | UART_CLEAR_OREF USART_ICR_ORECF
#define | UART_CLEAR_IDLEF USART_ICR_IDLECF
#define | UART_CLEAR_TXFECF USART_ICR_TXFECF
#define | UART_CLEAR_TCF USART_ICR_TCCF
#define | UART_CLEAR_LBDF USART_ICR_LBDCF
#define | UART_CLEAR_CTSF USART_ICR_CTSCF
#define | UART_CLEAR_RTOF USART_ICR_RTOCF
#define | UART_CLEAR_CMF USART_ICR_CMCF
#define | UART_CLEAR_WUF USART_ICR_WUCF
#define | __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)
Reset UART handle states.
#define | __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)
Flush the UART Data registers.
#define | __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified UART pending flag.
#define | __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
Clear the UART PE pending flag.
#define | __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
Clear the UART FE pending flag.
#define | __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
Clear the UART NE pending flag.
#define | __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
Clear the UART ORE pending flag.
#define | __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
Clear the UART IDLE pending flag.
#define | __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
Clear the UART TX FIFO empty clear flag.
#define | __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified UART flag is set or not.
#define | __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified UART interrupt.
#define | __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified UART interrupt.
#define | __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
Check whether the specified UART interrupt has occurred or not.
#define | __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified UART interrupt source is enabled or not.
#define | __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified UART ISR flag, in setting the proper ICR register flag.
#define | __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
Set a specific UART request flag.
#define | __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the UART one bit sample method.
#define | __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the UART one bit sample method.
#define | __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART.
#define | __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART.
#define | __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)
Enable CTS flow control.
#define | __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)
Disable CTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)
Enable RTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)
Disable RTS flow control.
#define | UART_DIV_LPUART(__PCLK__, __BAUD__, __PRESCALER__) ((((((uint64_t)(__PCLK__)/UARTPrescTable[(__PRESCALER__)])*256)) + ((__BAUD__)/2)) / (__BAUD__))
BRR division operation to set BRR register with LPUART.
#define | UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __PRESCALER__) (((((__PCLK__)/UARTPrescTable[(__PRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__))
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/UARTPrescTable[(__PRESCALER__)]) + ((__BAUD__)/2)) / (__BAUD__))
BRR division operation to set BRR register in 16-bit oversampling mode.
#define | UART_INSTANCE_LOWPOWER(__HANDLE__) (((__HANDLE__)->Instance == LPUART1) ? SET : RESET )
Check whether or not UART instance is Low Power UART.
#define | IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
Check UART Baud rate.
#define | IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART assertion time.
#define | IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART deassertion time.
#define | IS_UART_STOPBITS(__STOPBITS__)
Ensure that UART frame number of stop bits is valid.
#define | IS_LPUART_STOPBITS(__STOPBITS__)
Ensure that LPUART frame number of stop bits is valid.
#define | IS_UART_PARITY(__PARITY__)
Ensure that UART frame parity is valid.
#define | IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)
Ensure that UART hardware flow control is valid.
#define | IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
Ensure that UART communication mode is valid.
#define | IS_UART_STATE(__STATE__)
Ensure that UART state is valid.
#define | IS_UART_OVERSAMPLING(__SAMPLING__)
Ensure that UART oversampling is valid.
#define | IS_UART_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that UART frame sampling is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)
Ensure that UART auto Baud rate detection mode is valid.
#define | IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)
Ensure that UART receiver timeout setting is valid.
#define | IS_UART_LIN(__LIN__)
Ensure that UART LIN state is valid.
#define | IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__)
Ensure that UART LIN break detection length is valid.
#define | IS_UART_DMA_TX(__DMATX__)
Ensure that UART DMA TX state is valid.
#define | IS_UART_DMA_RX(__DMARX__)
Ensure that UART DMA RX state is valid.
#define | IS_UART_HALF_DUPLEX(__HDSEL__)
Ensure that UART half-duplex state is valid.
#define | IS_UART_WAKEUPMETHOD(__WAKEUP__)
Ensure that UART wake-up method is valid.
#define | IS_UART_REQUEST_PARAMETER(__PARAM__)
Ensure that UART request parameter is valid.
#define | IS_UART_ADVFEATURE_INIT(__INIT__)
Ensure that UART advanced features initialization is valid.
#define | IS_UART_ADVFEATURE_TXINV(__TXINV__)
Ensure that UART frame TX inversion setting is valid.
#define | IS_UART_ADVFEATURE_RXINV(__RXINV__)
Ensure that UART frame RX inversion setting is valid.
#define | IS_UART_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that UART frame data inversion setting is valid.
#define | IS_UART_ADVFEATURE_SWAP(__SWAP__)
Ensure that UART frame RX/TX pins swap setting is valid.
#define | IS_UART_OVERRUN(__OVERRUN__)
Ensure that UART frame overrun setting is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)
Ensure that UART auto Baud rate state is valid.
#define | IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that UART DMA enabling or disabling on error setting is valid.
#define | IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that UART frame MSB first setting is valid.
#define | IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__)
Ensure that UART stop mode state is valid.
#define | IS_UART_MUTE_MODE(__MUTE__)
Ensure that UART mute mode state is valid.
#define | IS_UART_WAKEUP_SELECTION(__WAKE__)
Ensure that UART wake-up selection is valid.
#define | IS_UART_DE_POLARITY(__POLARITY__)
Ensure that UART driver enable polarity is valid.
#define | IS_LPUART_STOPBITS(__STOPBITS__)
Ensure that LPUART frame number of stop bits is valid.
#define | IS_UART_PRESCALER(__PRESCALER__)
Ensure that UART Prescaler is valid.
#define | IS_UART_FIFO_MODE_STATE(__STATE__)
Ensure that UART FIFO mode is valid.
#define | IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that UART TXFIFO threshold level is valid.
#define | IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that UART RXFIFO threshold level is valid.

Enumerations

enum HAL_UART_StateTypeDef {
HAL_UART_STATE_RESET = 0x00U, HAL_UART_STATE_READY = 0x20U, HAL_UART_STATE_BUSY = 0x24U, HAL_UART_STATE_BUSY_TX = 0x21U,
HAL_UART_STATE_BUSY_RX = 0x22U, HAL_UART_STATE_BUSY_TX_RX = 0x23U, HAL_UART_STATE_TIMEOUT = 0xA0U, HAL_UART_STATE_ERROR = 0xE0U
}
HAL UART State structures definition. More...
enum HAL_UART_ErrorTypeDef {
HAL_UART_ERROR_NONE = 0x00U, HAL_UART_ERROR_PE = 0x01U, HAL_UART_ERROR_NE = 0x02U, HAL_UART_ERROR_FE = 0x04U,
HAL_UART_ERROR_ORE = 0x08U, HAL_UART_ERROR_DMA = 0x10U
}
HAL UART Error Code structure definition. More...
enum UART_ClockSourceTypeDef {
UART_CLOCKSOURCE_D2PCLK1 = 0x00U, UART_CLOCKSOURCE_D2PCLK2 = 0x01U, UART_CLOCKSOURCE_D3PCLK1 = 0x02U, UART_CLOCKSOURCE_PLL2 = 0x04U,
UART_CLOCKSOURCE_HSI = 0x08U, UART_CLOCKSOURCE_CSI = 0x10U, UART_CLOCKSOURCE_LSE = 0x20U, UART_CLOCKSOURCE_PLL3 = 0x40U,
UART_CLOCKSOURCE_UNDEFINED = 0x80U
}
UART clock sources definition. More...

Functions

HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitialize the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
Initialize the UART MSP.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
DeInitialize the UART MSP.
HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_Abort (UART_HandleTypeDef *huart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_Abort_IT (UART_HandleTypeDef *huart)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit_IT (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive_IT (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
Handle UART interrupt request.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callback.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callback.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callback.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callback.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callback.
__weak void | HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
UART Abort Receive Complete callback.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmit break characters.
HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enable the UART transmitter and disable the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enable the UART receiver and disable the UART transmitter.
HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
Return the UART handle state.
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART handle error code.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle UART Communication Timeout.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.

Variables

static const uint16_t | UARTPrescTable [12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}

Detailed Description

Header file of UART HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_uart.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_uart_ex.h File Reference

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Data Structures | Defines | Functions
stm32h7xx_hal_uart_ex.h File Reference

Header file of UART HAL Extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | UART_WakeUpTypeDef
UART wake up from stop mode parameters. More...

Defines

#define | UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define | UART_WORDLENGTH_8B ((uint32_t)0x00000000U)
#define | UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
#define | UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000U)
#define | UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7)
#define | UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the UART clock source.
#define | UART_MASK_COMPUTATION(__HANDLE__)
Report the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_UART_WORD_LENGTH(__LENGTH__)
Ensure that UART frame length is valid.
#define | IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__)
Ensure that UART wake-up address length is valid.

Functions

HAL_StatusTypeDef | HAL_RS485Ex_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_UARTEx_StopModeWakeUpSourceConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Set Wakeup from Stop mode interrupt flag selection.
HAL_StatusTypeDef | HAL_UARTEx_EnableStopMode (UART_HandleTypeDef *huart)
Enable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableStopMode (UART_HandleTypeDef *huart)
Disable UART Stop Mode.
HAL_StatusTypeDef | HAL_MultiProcessorEx_AddressLength_Set (UART_HandleTypeDef *huart, uint32_t AddressLength)
By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).
__weak void | HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.

Detailed Description

Header file of UART HAL Extended module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_uart_ex.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_usart_ex.h File Reference

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Defines
stm32h7xx_hal_usart_ex.h File Reference

Header file of USART HAL Extended module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define | USART_WORDLENGTH_8B ((uint32_t)0x00000000U)
#define | USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
#define | USART_MASK_COMPUTATION(__HANDLE__)
Compute the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_USART_WORD_LENGTH(__LENGTH__)
Ensure that USART frame length is valid.

Detailed Description

Header file of USART HAL Extended module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_usart_ex.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_wwdg.h File Reference

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stm32h7xx_hal_wwdg.h File Reference

Header file of WWDG HAL module. More...

#include "stm32h7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | WWDG_InitTypeDef
WWDG Init structure definition. More...
struct | WWDG_HandleTypeDef
WWDG handle Structure definition. More...

Defines

#define | WWDG_IT_EWI WWDG_CFR_EWI
#define | WWDG_FLAG_EWIF WWDG_SR_EWIF
#define | WWDG_PRESCALER_1 ((uint32_t)(0x00000000U))
#define | WWDG_PRESCALER_2 ((uint32_t)(WWDG_CFR_WDGTB0))
#define | WWDG_PRESCALER_4 ((uint32_t)(WWDG_CFR_WDGTB1))
#define | WWDG_PRESCALER_8 ((uint32_t)(WWDG_CFR_WDGTB1|WWDG_CFR_WDGTB0))
#define | WWDG_PRESCALER_16 ((uint32_t)(WWDG_CFR_WDGTB2))
#define | WWDG_PRESCALER_32 ((uint32_t)(WWDG_CFR_WDGTB2|WWDG_CFR_WDGTB0))
#define | WWDG_PRESCALER_64 ((uint32_t)(WWDG_CFR_WDGTB2|WWDG_CFR_WDGTB1))
#define | WWDG_PRESCALER_128 ((uint32_t)(WWDG_CFR_WDGTB2|WWDG_CFR_WDGTB1|WWDG_CFR_WDGTB0))
#define | WWDG_EWI_DISABLE 0x00000000u
#define | WWDG_EWI_ENABLE WWDG_CFR_EWI
#define | IS_WWDG_PRESCALER(__PRESCALER__)
#define | IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W6) && ((__WINDOW__) <= WWDG_CFR_W))
#define | IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T6) && ((__COUNTER__) <= WWDG_CR_T))
#define | IS_WWDG_EWI_MODE(__MODE__)
#define | __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
Enable the WWDG peripheral.
#define | __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
Enable the WWDG early wakeup interrupt.
#define | __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
Check whether the selected WWDG interrupt has occurred or not.
#define | __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
Clear the WWDG interrupt pending bits.
#define | __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified WWDG flag is set or not.
#define | __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(uint32_t)(__FLAG__))
Clear the WWDG's pending flags.
#define | __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified WWDG interrupt source is enabled or not.

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

Header file of WWDG HAL module.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_wwdg.h.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32H7xx_HAL_Driver
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Defines | Functions | Variables
stm32h7xx_hal.c File Reference

HAL module driver. This is the common part of the HAL initialization. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | __STM32H7xx_HAL_VERSION_MAIN (0x01)
STM32H7xx HAL Driver version number V1.0.0.
#define | __STM32H7xx_HAL_VERSION_SUB1 (0x00)
#define | __STM32H7xx_HAL_VERSION_SUB2 (0x00)
#define | __STM32H7xx_HAL_VERSION_RC (0x00)
#define | __STM32H7xx_HAL_VERSION
#define | IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
#define | VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms */

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configures the SysTick to generate an interrupt each 1 millisecond, which is clocked by the HSI (at this stage, the clock is not yet configured and thus the system is running from the internal HSI at 16 MHz).
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the systick.
__weak void | HAL_MspInit (void)
Initializes the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base.
__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
__weak void | HAL_Delay (__IO uint32_t Delay)
This function provides accurate delay (in milliseconds) based on variable incremented.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
void | HAL_SYSCFG_VREFBUF_VoltageScalingConfig (uint32_t VoltageScaling)
Configure the internal voltage reference buffer voltage scale.
void | HAL_SYSCFG_VREFBUF_HighImpedanceConfig (uint32_t Mode)
Configure the internal voltage reference buffer high impedance mode.
void | HAL_SYSCFG_VREFBUF_TrimmingConfig (uint32_t TrimmingValue)
Tune the Internal Voltage Reference buffer (VREFBUF).
HAL_StatusTypeDef | HAL_SYSCFG_EnableVREFBUF (void)
Enable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_DisableVREFBUF (void)
Disable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_ETHInterfaceSelect (uint32_t SYSCFG_ETHInterface)
Ethernet PHY Interface Selection either MII or RMII.
void | HAL_SYSCFG_AnalogSwitchConfig (uint32_t SYSCFG_AnalogSwitch, uint32_t SYSCFG_SwitchState)
Analog Switch control for dual analog pads.
void | HAL_SYSCFG_EnableBOOST (void)
Enables the booster to reduce the total harmonic distortion of the analog switch when the supply voltage is lower than 2.7 V.
void | HAL_SYSCFG_DisableBOOST (void)
Disables the booster.
void | HAL_SYSCFG_CM7BootAddConfig (uint32_t BootRegister, uint32_t BootAddress)
BootCM7 address 0 configuration.
void | HAL_EnableCompensationCell (void)
Enables the I/O Compensation Cell.
void | HAL_DisableCompensationCell (void)
Power-down the I/O Compensation Cell.
void | HAL_SYSCFG_EnableIOSpeedOptimize (void)
To Enable optimize the I/O speed when the product voltage is low.
void | HAL_SYSCFG_DisableIOSpeedOptimize (void)
To Disable optimize the I/O speed when the product voltage is low.
void | HAL_SYSCFG_CompensationCodeSelect (uint32_t SYSCFG_CompCode)
Code selection for the I/O Compensation cell.
void | HAL_SYSCFG_CompensationCodeConfig (uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode)
Code selection for the I/O Compensation cell.
void | HAL_EnableDBGSleepMode (void)
Enable the Debug Module during Domain1 SLEEP mode.
void | HAL_DisableDBGSleepMode (void)
Disable the Debug Module during Domain1 SLEEP mode.
void | HAL_EnableDBGStopMode (void)
Enable the Debug Module during Domain1 STOP mode.
void | HAL_DisableDBGStopMode (void)
Disable the Debug Module during Domain1 STOP mode.
void | HAL_EnableDBGStandbyMode (void)
Enable the Debug Module during Domain1 STANDBY mode.
void | HAL_DisableDBGStandbyMode (void)
Disable the Debug Module during Domain1 STANDBY mode.
void | HAL_EnableDomain3DBGStopMode (void)
Enable the Debug Module during Domain3 STOP mode.
void | HAL_DisableDomain3DBGStopMode (void)
Disable the Debug Module during Domain3 STOP mode.
void | HAL_EnableDomain3DBGStandbyMode (void)
Enable the Debug Module during Domain3 STANDBY mode.
void | HAL_DisableDomain3DBGStandbyMode (void)
Disable the Debug Module during Domain3 STANDBY mode.
void | HAL_SetFMCMemorySwappingConfig (uint32_t BankMapConfig)
Set the FMC Memory Mapping Swapping config.
uint32_t | HAL_GetFMCMemorySwappingConfig (void)
Get FMC Bank mapping mode.
void | HAL_EXTI_EdgeConfig (uint32_t EXTI_Line, uint32_t EXTI_Edge)
Configure the EXTI input event line edge.
void | HAL_EXTI_GenerateSWInterrupt (uint32_t EXTI_Line)
Generates a Software interrupt on selected EXTI line.
void | HAL_EXTI_D1_ClearFlag (uint32_t EXTI_Line)
Clears the EXTI's line pending flags for Domain D1.
void | HAL_EXTI_D1_EventInputConfig (uint32_t EXTI_Line, uint32_t EXTI_Mode, uint32_t EXTI_LineCmd)
Configure the EXTI input event line for Domain D1.
void | HAL_EXTI_D3_EventInputConfig (uint32_t EXTI_Line, uint32_t EXTI_LineCmd, uint32_t EXTI_ClearSrc)
Configure the EXTI input event line for Domain D3.

Variables

__IO uint32_t | uwTick

Detailed Description

HAL module driver. This is the common part of the HAL initialization.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The common HAL driver contains a set of generic and common APIs that can be
    used by the PPP peripheral drivers and the user to start using the HAL.
    [..]
    The HAL contains two APIs' categories:
         (+) Common HAL APIs
         (+) Services HAL APIs
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal.c.

Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_adc.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_adc.c File Reference

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and deinitialization functions ++ Initialization and Configuration of ADC + Operation functions ++ Start, stop, get result of regular conversions of regular using 3 possible modes: polling, interruption or DMA. + Control functions ++ Channels configuration on regular group ++ Analog Watchdog configuration + State functions ++ ADC state machine management ++ Interrupts and flags management Other functions (extended functions) are available in file "stm32h7xx_hal_adc_ex.c". More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | ADC_CFGR_FIELDS_1
#define | ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMNGT | ADC_CFGR_AUTDLY))
#define | ADC_CFGR2_FIELDS
#define | ADC_CFGR_WD_FIELDS
#define | ADC_OFR_FIELDS ((uint32_t)(ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH))
#define | ADC_ENABLE_TIMEOUT ((uint32_t) 2)
#define | ADC_DISABLE_TIMEOUT ((uint32_t) 2)
#define | ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 210688)

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initialize the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitialize the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enable ADC, starts conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for ADC event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start conversion of regular group and transfer result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handle ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non-blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non-blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog 1 callback in non-blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).
HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configure a channel to be assigned to ADC group regular.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configure the analog watchdog.
uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
Return the ADC handle state.
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.
HAL_StatusTypeDef | ADC_ConversionStop (ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
Stop ADC conversion.
HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_Disable (ADC_HandleTypeDef *hadc)
Disable the selected ADC.
void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and deinitialization functions ++ Initialization and Configuration of ADC + Operation functions ++ Start, stop, get result of regular conversions of regular using 3 possible modes: polling, interruption or DMA. + Control functions ++ Channels configuration on regular group ++ Analog Watchdog configuration + State functions ++ ADC state machine management ++ Interrupts and flags management Other functions (extended functions) are available in file "stm32h7xx_hal_adc_ex.c".

Author:
MCD Application conversion
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                    ##### ADC specific features #####
  ==============================================================================
  [..]
  (+) 16-bit, 14-bit, 12-bit, 10-bit or 8-bit configurable resolution.

  (+) Interrupt generation at the end of regular conversion and in case of
      analog watchdog or overrun events.

  (+) Single and continuous conversion modes.

  (+) Scan mode for conversion of several channels sequentially.

  (+) Data alignment with in-built data coherency.

  (+) Programmable sampling time (channel wise)

  (+) External trigger (timer or EXTI) with configurable polarity

  (+) DMA request generation for transfer of conversions data of regular group.

  (+) Configurable delay between conversions in Dual interleaved mode.

  (+) ADC channels selectable single/differential input.

  (+) ADC offset on regular groups.

  (+) ADC calibration

  (+) ADC conversion of regular group.

  (+) ADC supply requirements: 1.62 V to 3.6 V.

  (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
      Vdda or to an external voltage reference).

                     ##### How to use this driver #####
  ==============================================================================
    [..]

     *** Configuration of top level parameters related to ADC ***
     ============================================================
     [..]

    (#) Enable the ADC interface
        (++) As prerequisite, ADC clock must be configured at RCC top level.

        (++) Two clock settings are mandatory:
             (+++) ADC clock (core clock, also possibly conversion clock).

             (+++) ADC clock (conversions clock).
                   Two possible clock sources: synchronous clock derived from AHB clock
                   or asynchronous clock derived from system clock, the PLL2 or the PLL3 running up to 400MHz.

             (+++) Example:
                   Into HAL_ADC_MspInit() (recommended code location) or with
                   other device clock parameters configuration:
               (+++) __HAL_RCC_ADC_CLK_ENABLE();                  (mandatory)

               RCC_ADCCLKSOURCE_PLL2 enable:                   (optional: if asynchronous clock selected)
               (+++) RCC_PeriphClkInitTypeDef   RCC_PeriphClkInit;
               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
               (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_PLL2;
               (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);

        (++) ADC clock source and clock prescaler are configured at ADC level with
             parameter "ClockPrescaler" using function HAL_ADC_Init().

    (#) ADC pins configuration
         (++) Enable the clock for the ADC GPIOs
              using macro __HAL_RCC_GPIOx_CLK_ENABLE()
         (++) Configure these ADC pins in analog mode
              using function HAL_GPIO_Init()

    (#) Optionally, in case of usage of ADC with interruptions:
         (++) Configure the NVIC for ADC
              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
              into the function of corresponding ADC interruption vector
              ADCx_IRQHandler().

    (#) Optionally, in case of usage of DMA:
         (++) Configure the DMA (DMA channel, mode normal or circular, ...)
              using function HAL_DMA_Init().
         (++) Configure the NVIC for DMA
              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
              into the function of corresponding DMA interruption vector
              DMAx_Channelx_IRQHandler().

    *** Configuration of ADC, group regular, channels parameters ***
     ================================================================
     [..]

    (#) Configure the ADC parameters (resolution, data alignment, ...)
        and regular group parameters (conversion trigger, sequencer, ...)
        using function HAL_ADC_Init().

    (#) Configure the channels for regular group parameters (channel number,
        channel rank into sequencer, ..., into regular group)
        using function HAL_ADC_ConfigChannel().

    (#) Optionally, configure the analog watchdog parameters (channels
        monitored, thresholds, ...)
        using function HAL_ADC_AnalogWDGConfig().

     *** Execution of ADC conversions ***
     ====================================
     [..]

    (#) Optionally, perform an automatic ADC calibration to improve the
        conversion accuracy
        using function HAL_ADCEx_Calibration_Start().

    (#) ADC driver can be used among three modes: polling, interruption,
        transfer by DMA.

        (++) ADC conversion by polling:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start()
          (+++) Wait for ADC conversion completion
                using function HAL_ADC_PollForConversion()
          (+++) Retrieve conversion results
                using function HAL_ADC_GetValue()
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop()

        (++) ADC conversion by interruption:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start_IT()
          (+++) Wait for ADC conversion completion by call of function
                HAL_ADC_ConvCpltCallback()
                (this function must be implemented in user program)
          (+++) Retrieve conversion results
                using function HAL_ADC_GetValue()
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop_IT()

        (++) ADC conversion with transfer by DMA:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start_DMA()
          (+++) Wait for ADC conversion completion by call of function
                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
                (these functions must be implemented in user program)
          (+++) Conversion results are automatically transferred by DMA into
                destination variable address.
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop_DMA()

     [..]

    (@) Callback functions must be implemented in user program:
      (+@) HAL_ADC_ErrorCallback()
      (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
      (+@) HAL_ADC_ConvCpltCallback()
      (+@) HAL_ADC_ConvHalfCpltCallback

     *** Deinitialization of ADC ***
     ============================================================
     [..]

    (#) Disable the ADC interface
      (++) ADC clock can be hard reset and disabled at RCC top level.
        (++) Hard reset of ADC peripherals
             using macro __HAL_RCC_ADCx_FORCE_RESET(), __HAL_RCC_ADCx_RELEASE_RESET().
        (++) ADC clock disable
             using the equivalent macro/functions as configuration step.
             (+++) Example:
                   Into HAL_ADC_MspDeInit() (recommended code location) or with
                   other device clock parameters configuration:
               (+++) __HAL_RCC_ADC_CLK_DISABLE();                  (if not used anymore)
               RCC_ADCCLKSOURCE_CLKP restore:                      (optional)
               (+++) RCC_PeriphClkInitTypeDef   RCC_PeriphClkInit;
               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
               (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_CLKP;
               (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);

    (#) ADC pins configuration
         (++) Disable the clock for the ADC GPIOs
              using macro __HAL_RCC_GPIOx_CLK_DISABLE()

    (#) Optionally, in case of usage of ADC with interruptions:
         (++) Disable the NVIC for ADC
              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)

    (#) Optionally, in case of usage of DMA:
         (++) Deinitialize the DMA
              using function HAL_DMA_Init().
         (++) Disable the NVIC for DMA
              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)

    [..]
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_adc.c.

Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_adc_ex.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32H7xx_HAL_Driver
  • Src
Defines | Functions
stm32h7xx_hal_adc_ex.c File Reference

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Operation functions ++ Start, stop, get result of conversions of injected group, using 2 possible modes: polling, interruption. ++ Calibration +++ ADC automatic self-calibration +++ Calibration factors get or set ++ Multimode feature when available + Control functions ++ Channels configuration on injected group + State functions ++ Injected group queues management Other functions (generic functions) are available in file "stm32h7xx_hal_adc.c". More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | ADC_JSQR_FIELDS
#define | ADC_CFGR2_INJ_FIELDS
#define | ADC_CALIBRATION_TIMEOUT ((uint32_t) 64000)

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
uint32_t | HAL_ADCEx_Calibration_GetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Get the calibration factor from automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_LinearCalibration_GetValue (ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer)
Get the calibration factor from automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_Calibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set the calibration factor to overwrite automatic conversion result, ADC must be enabled and no conversion on going.
HAL_StatusTypeDef | HAL_ADCEx_LinearCalibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer)
Set the linear calibration factor.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels and disable ADC peripheral if no regular conversion is on going.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group with interruption.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion, disable ADC peripheral if no regular conversion is on going.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStart_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start MultiMode conversion and transfer regular results through DMA.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADCEx_MultiModeGetValue (ADC_HandleTypeDef *hadc)
Return the last ADC Master and Slave regular conversions results when in multimode configuration.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non-blocking mode.
__weak void | HAL_ADCEx_InjectedQueueOverflowCallback (ADC_HandleTypeDef *hadc)
Injected context queue overflow callback.
__weak void | HAL_ADCEx_LevelOutOfWindow2Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 2 callback in non-blocking mode.
__weak void | HAL_ADCEx_LevelOutOfWindow3Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 3 callback in non-blocking mode.
__weak void | HAL_ADCEx_EndOfSamplingCallback (ADC_HandleTypeDef *hadc)
End Of Sampling callback in non-blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of ADC groups regular and injected, disable interrution of end-of-conversion, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularMultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop DMA-based MultiMode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configure a channel to be assigned to ADC group injected.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeConfigChannel (ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
Enable ADC multimode and configure multimode parameters.
HAL_StatusTypeDef | HAL_ADCEx_EnableInjectedQueue (ADC_HandleTypeDef *hadc)
Enable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableInjectedQueue (ADC_HandleTypeDef *hadc)
Disable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableVoltageRegulator (ADC_HandleTypeDef *hadc)
Disable ADC voltage regulator.
HAL_StatusTypeDef | HAL_ADCEx_EnterADCDeepPowerDownMode (ADC_HandleTypeDef *hadc)
Enter ADC deep-power-down mode.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Operation functions ++ Start, stop, get result of conversions of injected group, using 2 possible modes: polling, interruption. ++ Calibration +++ ADC automatic self-calibration +++ Calibration factors get or set ++ Multimode feature when available + Control functions ++ Channels configuration on injected group + State functions ++ Injected group queues management Other functions (generic functions) are available in file "stm32h7xx_hal_adc.c".

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                    ##### ADC specific features #####
  ==============================================================================
  [..]
  (@) Sections "ADC peripheral features" and "How to use this driver" are
      available in file of generic functions "stm32h7xx_hal_adc.c".
  [..]
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_adc_ex.c.

Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_cec.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Functions
stm32h7xx_hal_cec.c File Reference

CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization function + IO operation function + Peripheral Control function. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_CEC_Init (CEC_HandleTypeDef *hcec)
Initializes the CEC mode according to the specified parameters in the CEC_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_CEC_DeInit (CEC_HandleTypeDef *hcec)
DeInitializes the CEC peripheral.
HAL_StatusTypeDef | HAL_CEC_SetDeviceAddress (CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
Initializes the Own Address of the CEC device.
__weak void | HAL_CEC_MspInit (CEC_HandleTypeDef *hcec)
CEC MSP Init.
__weak void | HAL_CEC_MspDeInit (CEC_HandleTypeDef *hcec)
CEC MSP DeInit.
HAL_StatusTypeDef | HAL_CEC_Transmit_IT (CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
Send data in interrupt mode.
uint32_t | HAL_CEC_GetLastReceivedFrameSize (CEC_HandleTypeDef *hcec)
Get size of the received frame.
void | HAL_CEC_ChangeRxBuffer (CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
Change Rx Buffer.
void | HAL_CEC_IRQHandler (CEC_HandleTypeDef *hcec)
This function handles CEC interrupt requests.
__weak void | HAL_CEC_TxCpltCallback (CEC_HandleTypeDef *hcec)
Tx Transfer completed callback.
__weak void | HAL_CEC_RxCpltCallback (CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
Rx Transfer completed callback.
__weak void | HAL_CEC_ErrorCallback (CEC_HandleTypeDef *hcec)
CEC error callbacks.
HAL_CEC_StateTypeDef | HAL_CEC_GetState (CEC_HandleTypeDef *hcec)
return the CEC state
uint32_t | HAL_CEC_GetError (CEC_HandleTypeDef *hcec)
Return the CEC error code.

Detailed Description

CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization function + IO operation function + Peripheral Control function.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
    [..]
    The CEC HAL driver can be used as follow:

    (#) Declare a CEC_HandleTypeDef handle structure.
    (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
        (##) Enable the CEC interface clock.
        (##) CEC pins configuration:
            (+++) Enable the clock for the CEC GPIOs.
            (+++) Configure these CEC pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
             and HAL_CEC_Receive_IT() APIs):
            (+++) Configure the CEC interrupt priority.
            (+++) Enable the NVIC CEC IRQ handle.
            (+++) The specific CEC interrupts (Transmission complete interrupt,
                  RXNE interrupt and Error Interrupts) will be managed using the macros
                  __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
                  and receive process.

    (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
        in case of Bit Rising Error, Error-Bit generation conditions, device logical
        address and Listen mode in the hcec Init structure.

    (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.

  [..]
    (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
        by calling the customed HAL_CEC_MspInit() API.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_cec.c.

Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_comp.c File Reference

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Defines | Functions
stm32h7xx_hal_comp.c File Reference

COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode + Start/Stop operation functions in interrupt mode + Peripheral control functions + Peripheral state functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | COMP_DELAY_STARTUP_US ((uint32_t) 80U)
#define | COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U)

Functions

HAL_StatusTypeDef | HAL_COMP_Init (COMP_HandleTypeDef *hcomp)
Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP peripheral.
__weak void | HAL_COMP_MspInit (COMP_HandleTypeDef *hcomp)
Initialize the COMP MSP.
__weak void | HAL_COMP_MspDeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP MSP.
HAL_StatusTypeDef | HAL_COMP_Start (COMP_HandleTypeDef *hcomp)
Start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop (COMP_HandleTypeDef *hcomp)
Stop the comparator.
HAL_StatusTypeDef | HAL_COMP_Start_IT (COMP_HandleTypeDef *hcomp)
Enable the interrupt and start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop_IT (COMP_HandleTypeDef *hcomp)
Disable the interrupt and Stop the comparator.
void | HAL_COMP_IRQHandler (COMP_HandleTypeDef *hcomp)
Comparator IRQ Handler.
HAL_StatusTypeDef | HAL_COMP_Lock (COMP_HandleTypeDef *hcomp)
Lock the selected comparator configuration.
uint32_t | HAL_COMP_GetOutputLevel (COMP_HandleTypeDef *hcomp)
Return the output level (high or low) of the selected comparator.
__weak void | HAL_COMP_TriggerCallback (COMP_HandleTypeDef *hcomp)
Comparator callback.
HAL_COMP_StateTypeDef | HAL_COMP_GetState (COMP_HandleTypeDef *hcomp)
Return the COMP handle state.

Detailed Description

COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode + Start/Stop operation functions in interrupt mode + Peripheral control functions + Peripheral state functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ================================================================================
                   ##### COMP Peripheral features #####
  ================================================================================

  [..]
      The STM32H7xx device family integrates two analog comparators instances
      COMP1 and COMP2:
      (#) The COMP input minus (inverting input) and input plus (non inverting input)
          can be set to internal references or to GPIO pins
          (refer to GPIO list in reference manual).

      (#) The COMP output level is available using HAL_COMP_GetOutputLevel()
          and can be redirected to other peripherals: GPIO pins (in mode
          alternate functions for comparator), timers.
          (refer to GPIO list in reference manual).

      (#) Pairs of comparators instances can be combined in window mode
          (2 consecutive instances odd and even COMP<x> and COMP<x+1>).

      (#) The comparators have interrupt capability through the EXTI controller
          with wake-up from sleep and stop modes:
          (++) COMP1 is internally connected to EXTI Line 20
          (++) COMP2 is internally connected to EXTI Line 21

  [..]
          From the corresponding IRQ handler, the right interrupt source can be retrieved
          using macro __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG().

            ##### How to use this driver #####
  ================================================================================
  [..]
      This driver provides functions to configure and program the comparator instances of
      STM32H7xx devices.

      To use the comparator, perform the following steps:

      (#)  Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
      (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
           using HAL_GPIO_Init().
      (++) If needed, configure the GPIO connected to comparator output in alternate function mode
           using HAL_GPIO_Init().
      (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
           selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
           interrupt vector using HAL_NVIC_EnableIRQ() function.

      (#) Configure the comparator using HAL_COMP_Init() function:
      (++) Select the input minus (inverting input)
      (++) Select the input plus (non-inverting input)
      (++) Select the hysteresis
      (++) Select the blanking source
      (++) Select the output polarity
      (++) Select the power mode
      (++) Select the window mode
      -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
          to enable internal control clock of the comparators.
          However, this is a legacy strategy.
          Therefore, for compatibility anticipation, it is recommended to
          implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".
          In STM32H7,COMP clock enable  __HAL_RCC_COMP12_CLK_ENABLE() must
          be implemented by user in "HAL_COMP_MspInit()".
      (#) Reconfiguration on-the-fly of comparator can be done by calling again
          function HAL_COMP_Init() with new input structure parameters values.

      (#) Enable the comparator using HAL_COMP_Start() or HAL_COMP_Start_IT()to be enabled
          with the interrupt through NVIC of the CPU.
      Note: HAL_COMP_Start_IT() must be called after each interrupt otherwise the interrupt
      mode will stay disabled.

      (#) Use HAL_COMP_GetOutputLevel() or HAL_COMP_TriggerCallback()
          functions to manage comparator outputs(output level or events)

      (#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT()
          to disable the interrupt too.

      (#) De-initialize the comparator using HAL_COMP_DeInit() function.

      (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
          The only way to unlock the comparator is a device hardware reset.

Table 1. COMP inputs and output for STM32H7xx devices +---------------------------------------------------------+ | | | COMP1 | COMP2 | |----------------|----------------|-----------|-----------| | | IO1 | PB0 | PE9 | | Input plus | IO2 | PB2 | PE11 | | | | | | |----------------|----------------|-----------------------| | | 1/4 VrefInt | Available | Available | | | 1/2 VrefInt | Available | Available | | | 3/4 VrefInt | Available | Available | | Input minus | VrefInt | Available | Available | | | DAC1 channel 1 | Available | Available | | | DAC1 channel 2 | Available | Available | | | IO1 | PB1 | PE10 | | | IO2 | PC4 | PE7 | | | | | | | | | | | | | | | | +---------------------------------------------------------+ | Output | | PC5 (1) | PE8 (1) | | | | PE12 (1) | PE13 (1) | | | | TIM (2) | TIM (2) | +---------------------------------------------------------+ (1) GPIO must be set to alternate function for comparator (2) Comparators output to timers is set in timers instances.

Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_comp.c.

Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_cortex.c File Reference

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Functions
stm32h7xx_hal_cortex.c File Reference

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Sets the priority grouping field (preemption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Sets the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiates a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initializes the System Timer and its interrupt, and starts the System Tick Timer.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initializes and configures the Region and the memory to be protected.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Gets the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Gets the priority of an interrupt.
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Sets Pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clears the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Gets active interrupt ( reads the active register in NVIC and returns the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configures the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
This function handles SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.
uint32_t | HAL_GetCurrentCPUID (void)
Returns the current CPU ID.

Detailed Description

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================

    [..]
    *** How to configure Interrupts using CORTEX HAL driver ***
    ===========================================================
    [..]
    This section provides functions allowing to configure the NVIC interrupts (IRQ).
    The Cortex-M exceptions are managed by CMSIS functions.

    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
        function according to the following table.
    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
    (#) please refer to programming manual for details in how to configure priority.

     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
         The pending IRQ priority will be managed only by the sub priority.

     -@- IRQ priority order (sorted by highest to lowest priority):
        (+@) Lowest preemption priority
        (+@) Lowest sub priority
        (+@) Lowest hardware priority (IRQ number)

    [..]
    *** How to configure Systick using CORTEX HAL driver ***
    ========================================================
    [..]
    Setup SysTick Timer for time base.

   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
       is a CMSIS function that:
        (++) Configures the SysTick Reload register with value passed as function parameter.
        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
        (++) Resets the SysTick Counter register.
        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
        (++) Enables the SysTick Interrupt.
        (++) Starts the SysTick Counter.

   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
       HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
       HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined
       inside the stm32h7xx_hal_cortex.h file.

   (+) You can change the SysTick IRQ priority by calling the
       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.

   (+) To adjust the SysTick time base, use the following formula:

       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
       (++) Reload Value should not exceed 0xFFFFFF
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_cortex.c.

Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_crc.c File Reference

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Functions
stm32h7xx_hal_crc.c File Reference

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

static uint32_t | CRC_Handle_8 (CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
Enter 8-bit input data to the CRC calculator.
static uint32_t | CRC_Handle_16 (CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
Enter 16-bit input data to the CRC calculator.
HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initialize the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.
uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.
HAL_CRC_StateTypeDef | HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC state.

Detailed Description

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
 ===============================================================================
                     ##### CRC How to use this driver #####
 ===============================================================================
    [..]

    (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();

    (#) Initialize CRC calculator
         (++) specify generating polynomial (IP default or non-default one)
         (++) specify initialization value (IP default or non-default one)
         (++) specify input data format
         (++) specify input or output data inversion mode if any

    (#) Use HAL_CRC_Accumulate() function to compute the CRC value of the
        input data buffer starting with the previously computed CRC as
        initialization value

    (#) Use HAL_CRC_Calculate() function to compute the CRC value of the
        input data buffer starting with the defined initialization value
        (default or non-default) to initiate CRC calculation
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_crc.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_crc_ex.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Functions
stm32h7xx_hal_crc_ex.c File Reference

Extended CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the CRC peripheral: + Initialization/de-initialization functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initializes the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Extended CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the CRC peripheral: + Initialization/de-initialization functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                    ##### CRC specific features #####
  ==============================================================================
  [..]
  (#) Polynomial configuration.
  (#) Input data reverse mode.
  (#) Output data reverse mode.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_crc_ex.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_cryp.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_cryp.c File Reference

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization and de-initialization functions + AES processing functions + DES processing functions + TDES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | CRYP_TIMEOUT_KEYPREPARATION 82U /*The latency of key preparation operation is 82 clock cycles.*/
#define | CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
#define | CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
#define | CRYP_PHASE_READY 0x00000001U
#define | CRYP_PHASE_PROCESS 0x00000002U
#define | CRYP_PHASE_INIT 0x00000000U
#define | CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
#define | CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
#define | CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
#define | CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
#define | CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR
#define | CRYP_CCM_CTR1_0 0x07FFFFFFU
#define | CRYP_CCM_CTR1_1 0xFFFFFF00U
#define | CRYP_CCM_CTR1_2 0x00000001U
#define | CRYP_SET_PHASE(__HANDLE__, __PHASE__)
#define | HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)

Functions

static void | CRYP_SetDMAConfig (CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
Set the DMA configuration and start the DMA transfer.
static void | CRYP_DMAInCplt (DMA_HandleTypeDef *hdma)
DMA CRYP input data process complete callback.
static void | CRYP_DMAOutCplt (DMA_HandleTypeDef *hdma)
DMA CRYP output data process complete callback.
static void | CRYP_DMAError (DMA_HandleTypeDef *hdma)
DMA CRYP communication error callback.
static void | CRYP_SetKey (CRYP_HandleTypeDef *hcryp, uint32_t *Key, uint32_t KeySize)
Writes Key in Key registers.
static HAL_StatusTypeDef | CRYP_AES_IT (CRYP_HandleTypeDef *hcryp)
Handle CRYP block input/output data handling under interruption.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetHeaderPhase (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Sets the header phase in polling mode.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetPayloadPhase_IT (CRYP_HandleTypeDef *hcryp)
Sets the payload phase in iterrupt mode.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetHeaderPhase_IT (CRYP_HandleTypeDef *hcryp)
Sets the header phase in interrupt mode.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetHeaderPhase_DMA (CRYP_HandleTypeDef *hcryp)
Sets the header phase when using DMA in process.
static void | CRYP_Workaround (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Workaround used for GCM/CCM mode.
static HAL_StatusTypeDef | CRYP_AESGCM_Process_DMA (CRYP_HandleTypeDef *hcryp)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA.
static HAL_StatusTypeDef | CRYP_AESGCM_Process_IT (CRYP_HandleTypeDef *hcryp)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode.
static HAL_StatusTypeDef | CRYP_AESGCM_Process (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG.
static HAL_StatusTypeDef | CRYP_AESCCM_Process (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
AES CCM encryption/decryption processing in polling mode.
static HAL_StatusTypeDef | CRYP_AESCCM_Process_IT (CRYP_HandleTypeDef *hcryp)
AES CCM encryption/decryption process in interrupt mode.
static HAL_StatusTypeDef | CRYP_AESCCM_Process_DMA (CRYP_HandleTypeDef *hcryp)
AES CCM encryption/decryption process in DMA mode.
static HAL_StatusTypeDef | CRYP_AES_ProcessData (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Process Data: Write Input data in polling mode and used in AES functions.
static HAL_StatusTypeDef | CRYP_AES_Encrypt (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption in ECB/CBC & CTR Algorithm with AES Standard.
static HAL_StatusTypeDef | CRYP_AES_Decrypt (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Decryption in ECB/CBC & CTR mode with AES Standard.
static HAL_StatusTypeDef | CRYP_AES_Decrypt_IT (CRYP_HandleTypeDef *hcryp)
Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.
static HAL_StatusTypeDef | CRYP_AES_Encrypt_IT (CRYP_HandleTypeDef *hcryp)
Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.
static HAL_StatusTypeDef | CRYP_AES_Decrypt_DMA (CRYP_HandleTypeDef *hcryp)
Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode.
static HAL_StatusTypeDef | CRYP_TDES_IT (CRYP_HandleTypeDef *hcryp)
CRYP block input/output data handling under interruption with DES/TDES standard.
static HAL_StatusTypeDef | CRYP_WaitOnIFEMFlag (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.
static HAL_StatusTypeDef | CRYP_WaitOnBUSYFlag (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.
static HAL_StatusTypeDef | CRYP_WaitOnOFNEFlag (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.
static HAL_StatusTypeDef | CRYP_TDES_Process (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption in ECB/CBC Algorithm with DES/TDES standard.
HAL_StatusTypeDef | HAL_CRYP_Init (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP according to the specified parameters in the CRYP_ConfigTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_CRYP_DeInit (CRYP_HandleTypeDef *hcryp)
De-Initializes the CRYP peripheral.
HAL_StatusTypeDef | HAL_CRYP_SetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Configure the CRYP according to the specified parameters in the CRYP_ConfigTypeDef.
HAL_StatusTypeDef | HAL_CRYP_GetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Get CRYP Configuration parameters in associated handle.
__weak void | HAL_CRYP_MspInit (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP MSP.
__weak void | HAL_CRYP_MspDeInit (CRYP_HandleTypeDef *hcryp)
DeInitializes CRYP MSP.
HAL_StatusTypeDef | HAL_CRYP_Encrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Encryption mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Decryption mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in interrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in itnterrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in DMA mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in DMA mode.
void | HAL_CRYP_IRQHandler (CRYP_HandleTypeDef *hcryp)
This function handles cryptographic interrupt request.
uint32_t | HAL_CRYP_GetError (CRYP_HandleTypeDef *hcryp)
Return the CRYP error code.
HAL_CRYP_STATETypeDef | HAL_CRYP_GetState (CRYP_HandleTypeDef *hcryp)
Returns the CRYP state.
__weak void | HAL_CRYP_InCpltCallback (CRYP_HandleTypeDef *hcryp)
Input FIFO transfer completed callback.
__weak void | HAL_CRYP_OutCpltCallback (CRYP_HandleTypeDef *hcryp)
Output FIFO transfer completed callback.
__weak void | HAL_CRYP_ErrorCallback (CRYP_HandleTypeDef *hcryp)
CRYP error callback.

Detailed Description

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization and de-initialization functions + AES processing functions + DES processing functions + TDES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      The CRYP HAL driver can be used in CRYP IP as follows:

      (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
         (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
         (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
             (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
             (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
             (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
         (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
             (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
             (+++) Configure and enable two DMA streams one for managing data transfer from
                 memory to peripheral (input stream) and another stream for managing data
                 transfer from peripheral to memory (output stream)
             (+++) Associate the initialized DMA handle to the CRYP DMA handle
                 using  __HAL_LINKDMA()
             (+++) Configure the priority and enable the NVIC for the transfer complete
                 interrupt on the two DMA Streams. The output stream should have higher
                 priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()

      (#)Initialize the CRYP according to the specified parameters :
         (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
         (##) The key size: 128, 192 or 256.
         (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM.
         (##) The initialization vector (counter). It is not used in ECB mode.
         (##) The key buffer used for encryption/decryption.
         (##) The Header used only in AES GCM and CCM Algorithm for authentication.
         (##) The HeaderSize The size of header buffer in word.
         (##) The B0 block is the first authentication block used only  in AES CCM mode.

      (#)Three processing (encryption/decryption) functions are available:
         (##) Polling mode: encryption and decryption APIs are blocking functions
              i.e. they process the data and wait till the processing is finished,
              e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
         (##) Interrupt mode: encryption and decryption APIs are not blocking functions
              i.e. they process the data under interrupt,
              e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
         (##) DMA mode: encryption and decryption APIs are not blocking functions
              i.e. the data transfer is ensured by DMA,
              e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA

      (#)When the processing function is called at first time after HAL_CRYP_Init()
         the CRYP peripheral is configured and processes the buffer in input.
         At second call, no need to Initialize the CRYP, user have to get current configuration via
         HAL_CRYP_GetConfig() API, then only  HAL_CRYP_SetConfig() is requested to set
         new parametres, finally user can  start encryption/decryption.

       (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.

    [..]
      The cryptographic processor supports following standards:
      (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP:
         (##)64-bit data block processing
         (##) chaining modes supported :
             (+++)  Electronic Code Book(ECB)
             (+++)  Cipher Block Chaining (CBC)
         (##) keys length supported :64-bit, 128-bit and 192-bit.
      (#) The advanced encryption standard (AES) supported  by CRYP1:
         (##)128-bit data block processing
         (##) chaining modes supported :
             (+++)  Electronic Code Book(ECB)
             (+++)  Cipher Block Chaining (CBC)
             (+++)  Counter mode (CTR)
             (+++)  Galois/counter mode (GCM/GMAC)
             (+++)  Counter with Cipher Block Chaining-Message(CCM)
         (##) keys length Supported :
             (+++) for CRYP1 IP: 128-bit, 192-bit and 256-bit.

    [..]  This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 IP:
      (#)  Algorithm supported :
         (##) Galois/counter mode (GCM)
         (##) Galois message authentication code (GMAC) :is exactly the same as
              GCM algorithm composed only by an header.
      (#)  Four phases are performed in GCM :
         (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
         (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
          computation only.
         (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
          encryption + data XORing. It works in a similar way for ciphertext (C).
         (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
      (#)  structure of message construction in GCM is defined as below  :
         (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
         (##) The authenticated header A (also knows as Additional Authentication Data AAD)
          this part of the message is only authenticated, not encrypted.
         (##) The plaintext message P is both authenticated and encrypted as ciphertext.
          GCM standard specifies that ciphertext has same bit length as the plaintext.
         (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
          (on 64 bits)

    [..]  This section describe The AES Counter with Cipher Block Chaining-Message
          Authentication Code (CCM) supported by both CRYP1 IP:
      (#)  Specific parameters for CCM  :

         (##) B0 block  : According to NIST Special Publication 800-38C,
            The first block B0 is formatted as follows, where l(m) is encoded in
            most-significant-byte first order(see below table 3)

              (+++)  Q: a bit string representation of the octet length of P (plaintext)
              (+++)  q The octet length of the binary representation of the octet length of the payload
              (+++)  A nonce (N), n The octet length of the where n+q=15.
              (+++)  Flags: most significant octet containing four flags for control information,
              (+++)  t The octet length of the MAC.
         (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
              the associated data length expressed in bytes (a) defined as below:
            (+++)  If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
            (+++)  If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
            (+++)  If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
         (##) CTRx block  : control blocks
            (+++) Generation of CTR1 from first block B0 information :
              equal to B0 with first 5 bits zeroed and most significant bits storing octet
              length of P also zeroed, then incremented by one ( see below Table 4)
            (+++) Generation of CTR0: same as CTR1 with bit[0] set to zero.

      (#)  Four phases are performed in CCM for CRYP1 IP:
         (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
         (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
          computation only.
         (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
          encryption + data XORing. It works in a similar way for ciphertext (C).
         (##) Final phase: IP generates the authenticated tag (T) using the last block of data.

Table 1. Initial Counter Block (ICB) +-------------------------------------------------------+ | Initialization vector (IV) | Counter | |----------------|----------------|-----------|---------| 127 95 63 31 0

Bit Number Register Contents ---------- --------------- ----------- 127 ...96 CRYP_IV1R[31:0] ICB[127:96] 95 ...64 CRYP_IV1L[31:0] B0[95:64] 63 ... 32 CRYP_IV0R[31:0] ICB[63:32] 31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2

Table 2. GCM last block definition

+-------------------------------------------------------------------+ | Bit[0] | Bit[32] | Bit[64] | Bit[96] | |-----------|--------------------|-----------|----------------------| | 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] | |-----------|--------------------|-----------|----------------------|

Table 3. B0 block Octet Number Contents ------------ --------- 0 Flags 1 ... 15-q Nonce N 16-q ... 15 Q

the Flags field is formatted as follows:

Bit Number Contents ---------- ---------------------- 7 Reserved (always zero) 6 Adata 5 ... 3 (t-2)/2 2 ... 0 [q-1]3

Table 4. CTRx block Bit Number Register Contents ---------- --------------- ----------- 127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for bit 0 that is set to 1 95 ...64 CRYP_IV1L[31:0] B0[95:64] 63 ... 32 CRYP_IV0R[31:0] B0[63:32] 31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0

Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_cryp.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_cryp_ex.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32H7xx_HAL_Driver
  • Src
Defines | Functions
stm32h7xx_hal_cryp_ex.c File Reference

Extended CRYP HAL module driver This file provides firmware functions to manage the following functionalities of CRYP extension peripheral: + Extended AES processing functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | CRYP_PHASE_INIT 0x00000000U
#define | CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
#define | CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
#define | CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
#define | CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
#define | CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR
#define | CRYPEx_PHASE_PROCESS 0x02U
#define | CRYPEx_PHASE_FINAL 0x03U
#define | CRYP_CCM_CTR0_0 0x07FFFFFFU
#define | CRYP_CCM_CTR0_3 0xFFFFFF00U

Functions

HAL_StatusTypeDef | HAL_CRYPEx_AESGCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
generate the GCM authentication TAG.
HAL_StatusTypeDef | HAL_CRYPEx_AESCCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
AES CCM Authentication TAG generation.

Detailed Description

Extended CRYP HAL module driver This file provides firmware functions to manage the following functionalities of CRYP extension peripheral: + Extended AES processing functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The CRYP extension HAL driver can be used after AES-GCM or AES-CCM
    Encryption/Decryption to get the authentication messages.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_cryp_ex.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dac.c File Reference

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Defines | Functions
stm32h7xx_hal_dac.c File Reference

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMEOUT_DAC_CALIBCONFIG ((uint32_t)1) /* 1ms */

Functions

static void | DAC_DMAConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
static void | DAC_DMAErrorCh1 (DMA_HandleTypeDef *hdma)
DMA error callback.
static void | DAC_DMAHalfConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitialize the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initialize the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitialize the DAC MSP.
HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enable DAC and start conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disable DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enable DAC and start conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disable DAC and stop conversion of channel.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handle DAC interrupt request This function uses the interruption of DMA underrun.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.
uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configure the selected DAC channel.
HAL_DAC_StateTypeDef | HAL_DAC_GetState (DAC_HandleTypeDef *hdac)
return the DAC handle state
uint32_t | HAL_DAC_GetError (DAC_HandleTypeDef *hdac)
Return the DAC error code.

Detailed Description

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                      ##### DAC Peripheral features #####
  ==============================================================================
    [..]
      *** DAC Channels ***
      ====================
    [..]
    STM32H7 devices integrate two 12-bit Digital Analog Converters.

    The 2 converters (i.e. channel1 & channel2) can be used independently or simultaneously (dual mode):
      (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip
          peripherals (ex. OPAMPs, comparators).
      (#) DAC channel2 with DAC_OUT2 (PA5) as output or connected to on-chip
          peripherals (ex. OPAMPs, comparators).

      *** DAC Triggers ***
      ====================
    [..]
    Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
    [..]
    Digital to Analog conversion can be triggered by:
      (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
          The used pin (GPIOx_PIN_9) must be configured in input mode.

      (#) Timers TRGO:TIM1,TIM2,TIM4, TIM5, TIM6, TIM7,TIM8 and TIM15
          (DAC_TRIGGER_T1_TRGO, DAC_TRIGGER_T2_TRGO...)

      (#) Timers TRGO: HRTIM1,LPTIM1,LPTIM2
      (DAC_TRIGGER_HR1_TRGO1,DAC_TRIGGER_HR1_TRGO2,DAC_TRIGGER_LP1_OUT,DAC_TRIGGER_LP2_OUT)
      (#) Software using DAC_TRIGGER_SOFTWARE

      *** DAC Buffer mode feature ***
      ===============================
      [..]
      Each DAC channel integrates an output buffer that can be used to
      reduce the output impedance, and to drive external loads directly
      without having to add an external operational amplifier.
      To enable, the output buffer use
      sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
      [..]
      (@) Refer to the device datasheet for more details about output
          impedance value with and without output buffer.

      *** DAC connect feature ***
      ===============================
      [..]
      Each DAC channel can be connected internally.
      To connect, use
      sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE;

      *** GPIO configurations guidelines ***
      ====================================
      [..]
      When a DAC channel is used (ex channel1 on PA4) and the other is not
      (ex channel2 on PA5 is configured in Analog and disabled).
      Channel1 may disturb channel2 as coupling effect.
      Note that there is no coupling on channel2 as soon as channel2 is turned on.
      Coupling on adjacent channel could be avoided as follows:
      when unused PA5 is configured as INPUT PULL-UP or DOWN.
      PA5 is configured in ANALOG just before it is turned on.

      *** DAC Sample and Hold feature ***
      ===================================
      [..]
      For each converter, 2 modes are supported: normal mode and
      "sample and hold" mode (i.e. low power mode).
      In the sample and hold mode, the DAC core converts data, then holds the
      converted voltage on a capacitor. When not converting, the DAC cores and
      buffer are completely turned off between samples and the DAC output is
      tri-stated, therefore  reducing the overall power consumption. A new
      stabilization period is needed before each new conversion.
      [..]
      The sample and hold allow setting internal or external voltage @
      low power consumption cost (output value can be at any given rate either
      by CPU or DMA).
      [..]
      The Sample and hold block and registers uses either LSI & run in
      several power modes: run mode, sleep mode & stop mode.

      To enable Sample and Hold mode ,enable LSI using HAL_RCC_OscConfig with
    RCC_OSCILLATORTYPE_LSI & RCC_LSI_ON parameters.

      Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE
         & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
           DAC_HoldTime & DAC_RefreshTime.

       *** DAC calibration feature ***
       ===================================
      [..]
       (#)  The 2 converters (channel1 & channel2) provide calibration capabilities.
       (++) Calibration aims at correcting some offset of output buffer.
       (++) The DAC uses either factory calibration settings OR user defined
           calibration (trimming) settings (i.e. trimming mode).
       (++) The user defined settings can be figured out using self calibration
           handled by HAL_DACEx_SelfCalibrate.
       (++) HAL_DACEx_SelfCalibrate:
       (+++) Runs automatically the calibration.
       (+++) Enables the user trimming mode
       (+++) Updates a structure with trimming values with fresh calibration
            results.
            The user may store the calibration results for larger
            (ex monitoring the trimming as a function of temperature
            for instance)

       *** DAC wave generation feature ***
       ===================================
       [..]
       Both DAC channels can be used to generate:
         (#) Noise wave
         (#) Triangle wave

       *** DAC data format ***
       =======================
       [..]
       The DAC data format can be:
         (#) 8-bit right alignment using DAC_ALIGN_8B_R
         (#) 12-bit left alignment using DAC_ALIGN_12B_L
         (#) 12-bit right alignment using DAC_ALIGN_12B_R

       *** DAC data value to voltage correspondence ***
       ================================================
       [..]
       The analog output voltage on each DAC channel pin is determined
       by the following equation:
       [..]
       DAC_OUTx = VREF+ * DOR / 4095
       (+) with  DOR is the Data Output Register
       [..]
          VREF+ is the input voltage reference (refer to the device datasheet)
       [..]
        e.g. To set DAC_OUT1 to 0.7V:
       (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V

       *** DMA requests  ***
       =====================
       [..]
       A DMA request can be generated when an external trigger (but not
       a software trigger) occurs if DMA requests are enabled using
       HAL_DAC_Start_DMA().
       DMA requests are mapped as following:
      (#) DAC channel1: mapped on DMA_REQUEST_DAC1
      (#) DAC channel2: mapped on DMA_REQUEST_DAC2
      [..]
    -@- For Dual mode and specific signal (Triangle and noise) generation please
        refer to Extended Features Driver description

                      ##### How to use this driver #####
  ==============================================================================
    [..]
      (+) DAC APB clock must be enabled to get write access to DAC
          registers using HAL_DAC_Init()
      (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
      (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.

     *** Calibration mode IO operation ***
     ======================================
     [..]
       (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset()
       (+) Run the calibration using HAL_DACEx_SelfCalibrate()
       (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming()

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Start the DAC peripheral using HAL_DAC_Start()
       (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
       (+) Stop the DAC peripheral using HAL_DAC_Stop()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
           of data to be transferred at each end of conversion.
       (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1()or HAL_DACEx_ConvHalfCpltCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2().
       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DACEx_ConvHalfCpltCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2().
       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1.
       (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
           HAL_DAC_DMAUnderrunCallbackCh1()or HAL_DACEx_DMAUnderrunCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()and
           add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1().
       (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()

     *** DAC HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DAC HAL driver.

      (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
      (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
      (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status

     [..]
      (@) You can refer to the DAC HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_dac.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dac_ex.c File Reference

  • File List
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Functions
stm32h7xx_hal_dac_ex.c File Reference

Extended DAC HAL module driver. This file provides firmware functions to manage the extended functionalities of DAC peripheral. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel2.
HAL_StatusTypeDef | HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Run the self calibration of one DAC channel.
HAL_StatusTypeDef | HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
Set the trimming mode and trimming value (user trimming mode applied).
uint32_t | HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the DAC trimming value.
uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Return the last data output value of the selected DAC channel.
void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

Extended DAC HAL module driver. This file provides firmware functions to manage the extended functionalities of DAC peripheral.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                      ##### How to use this driver #####
  ==============================================================================
    [..]
      (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.

      (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
      (+) HAL_DACEx_SetUserTrimming to set user trimming value.
      (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
          after reset, user setting if HAL_DACEx_SetUserTrimming have been used
          at least one time after reset).
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_dac_ex.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dcmi.c File Reference

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Defines | Functions
stm32h7xx_hal_dcmi.c File Reference

DCMI HAL module driver This file provides firmware functions to manage the following functionalities of the Digital Camera Interface (DCMI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* Set timeout to 1s */
#define | DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE)
#define | DCMI_POSITION_CWSTRT_VST (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST)
#define | DCMI_POSITION_ESCR_LSC (uint32_t)POSITION_VAL(DCMI_ESCR_LSC)
#define | DCMI_POSITION_ESCR_LEC (uint32_t)POSITION_VAL(DCMI_ESCR_LEC)
#define | DCMI_POSITION_ESCR_FEC (uint32_t)POSITION_VAL(DCMI_ESCR_FEC)

Functions

static void | DCMI_DMAXferCplt (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
static void | DCMI_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
HAL_StatusTypeDef | HAL_DCMI_Init (DCMI_HandleTypeDef *hdcmi)
Initializes the DCMI according to the specified parameters in the DCMI_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DCMI_DeInit (DCMI_HandleTypeDef *hdcmi)
Deinitializes the DCMI peripheral registers to their default reset values.
__weak void | HAL_DCMI_MspInit (DCMI_HandleTypeDef *hdcmi)
Initializes the DCMI MSP.
__weak void | HAL_DCMI_MspDeInit (DCMI_HandleTypeDef *hdcmi)
DeInitializes the DCMI MSP.
HAL_StatusTypeDef | HAL_DCMI_Start_DMA (DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
Enables DCMI DMA request and enables DCMI capture.
HAL_StatusTypeDef | HAL_DCMI_Stop (DCMI_HandleTypeDef *hdcmi)
Disable DCMI DMA request and Disable DCMI capture.
HAL_StatusTypeDef | HAL_DCMI_Suspend (DCMI_HandleTypeDef *hdcmi)
Suspend DCMI capture.
HAL_StatusTypeDef | HAL_DCMI_Resume (DCMI_HandleTypeDef *hdcmi)
Resume DCMI capture.
void | HAL_DCMI_IRQHandler (DCMI_HandleTypeDef *hdcmi)
Handles DCMI interrupt request.
__weak void | HAL_DCMI_ErrorCallback (DCMI_HandleTypeDef *hdcmi)
Error DCMI callback.
__weak void | HAL_DCMI_LineEventCallback (DCMI_HandleTypeDef *hdcmi)
Line Event callback.
__weak void | HAL_DCMI_VsyncEventCallback (DCMI_HandleTypeDef *hdcmi)
VSYNC Event callback.
__weak void | HAL_DCMI_FrameEventCallback (DCMI_HandleTypeDef *hdcmi)
Frame Event callback.
HAL_StatusTypeDef | HAL_DCMI_ConfigCrop (DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
Configure the DCMI CROP coordinate.
HAL_StatusTypeDef | HAL_DCMI_DisableCrop (DCMI_HandleTypeDef *hdcmi)
Disable the Crop feature.
HAL_StatusTypeDef | HAL_DCMI_EnableCrop (DCMI_HandleTypeDef *hdcmi)
Enable the Crop feature.
HAL_DCMI_StateTypeDef | HAL_DCMI_GetState (DCMI_HandleTypeDef *hdcmi)
Return the DCMI state.
uint32_t | HAL_DCMI_GetError (DCMI_HandleTypeDef *hdcmi)
Return the DCMI error code.

Detailed Description

DCMI HAL module driver This file provides firmware functions to manage the following functionalities of the Digital Camera Interface (DCMI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
      The sequence below describes how to use this driver to capture image
      from a camera module connected to the DCMI Interface.
      This sequence does not take into account the configuration of the
      camera module, which should be made before to configure and enable
      the DCMI to capture images.

    (#) Program the required configuration through following parameters:
        horizontal and vertical polarity, pixel clock polarity, Capture Rate,
        Synchronization Mode, code of the frame delimiter and data width
        using HAL_DCMI_Init() function.

    (#) Configure the selected DMA stream to transfer Data from DCMI DR
        register to the destination memory buffer.

    (#) Program the required configuration through following parameters:
        DCMI mode, destination memory Buffer address and the data length
        and enable capture using HAL_DCMI_Start_DMA() function.

    (#) Optionally, configure and Enable the CROP feature to select a rectangular
        window from the received image using HAL_DCMI_ConfigCrop()
        and HAL_DCMI_EnableCrop() functions

    (#) The capture can be stopped using HAL_DCMI_Stop() function.

    (#) To control DCMI state you can use the function HAL_DCMI_GetState().

     *** DCMI HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DCMI HAL driver.

      (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.
      (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.
      (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.
      (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.
      (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
      (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
      (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.

     [..]
       (@) You can refer to the DCMI HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_dcmi.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dfsdm.c File Reference

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Defines | Functions | Variables
stm32h7xx_hal_dfsdm.c File Reference

This file provides firmware functions to manage the following functionalities of the Digital Filter for Sigma-Delta Modulators (DFSDM) peripherals: + Initialization and configuration of channels and filters + Regular channels configuration + Injected channels configuration + Regular/Injected Channels DMA Configuration + Interrupts and flags management + Analog watchdog feature + Short-circuit detector feature + Extremes detector feature + Clock absence detector feature + Break generation on analog watchdog or short-circuit event. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | DFSDM_CHCFGR1_CLK_DIV_OFFSET POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV)
#define | DFSDM_CHAWSCDR_BKSCD_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_BKSCD)
#define | DFSDM_CHAWSCDR_FOSR_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR)
#define | DFSDM_CHCFGR2_OFFSET_OFFSET POSITION_VAL(DFSDM_CHCFGR2_OFFSET)
#define | DFSDM_CHCFGR2_DTRBS_OFFSET POSITION_VAL(DFSDM_CHCFGR2_DTRBS)
#define | DFSDM_FLTFCR_FOSR_OFFSET POSITION_VAL(DFSDM_FLTFCR_FOSR)
#define | DFSDM_FLTCR1_MSB_RCH_OFFSET 8
#define | DFSDM_FLTCR2_EXCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_EXCH)
#define | DFSDM_FLTCR2_AWDCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_AWDCH)
#define | DFSDM_FLTISR_CKABF_OFFSET POSITION_VAL(DFSDM_FLTISR_CKABF)
#define | DFSDM_FLTISR_SCDF_OFFSET POSITION_VAL(DFSDM_FLTISR_SCDF)
#define | DFSDM_FLTICR_CLRCKABF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRCKABF)
#define | DFSDM_FLTICR_CLRSCDF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRSCDF)
#define | DFSDM_FLTRDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTRDATAR_RDATA)
#define | DFSDM_FLTJDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTJDATAR_JDATA)
#define | DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT)
#define | DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT)
#define | DFSDM_FLTEXMAX_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMAX_EXMAX)
#define | DFSDM_FLTEXMIN_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMIN_EXMIN)
#define | DFSDM_FLTCNVTIMR_DATA_OFFSET POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT)
#define | DFSDM_FLTAWSR_HIGH_OFFSET POSITION_VAL(DFSDM_FLTAWSR_AWHTF)
#define | DFSDM_MSB_MASK 0xFFFF0000
#define | DFSDM_LSB_MASK 0x0000FFFF
#define | DFSDM_CKAB_TIMEOUT 5000
#define | DFSDM1_CHANNEL_NUMBER 8

Functions

static uint32_t | DFSDM_GetInjChannelsNbr (uint32_t Channels)
This function allows to get the number of injected channels.
static uint32_t | DFSDM_GetChannelFromInstance (DFSDM_Channel_TypeDef *Instance)
This function allows to get the channel number from channel instance.
static void | DFSDM_RegConvStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really start regular conversion.
static void | DFSDM_RegConvStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really stop regular conversion.
static void | DFSDM_InjConvStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really start injected conversion.
static void | DFSDM_InjConvStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really stop injected conversion.
static void | DFSDM_DMARegularHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback for regular conversion.
static void | DFSDM_DMARegularConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback for regular conversion.
static void | DFSDM_DMAInjectedHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback for injected conversion.
static void | DFSDM_DMAInjectedConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback for injected conversion.
static void | DFSDM_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
HAL_StatusTypeDef | HAL_DFSDM_ChannelInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel according to the specified parameters in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_DFSDM_ChannelDeInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel.
__weak void | HAL_DFSDM_ChannelMspInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel MSP.
__weak void | HAL_DFSDM_ChannelMspDeInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel MSP.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStart (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelPollForCkab (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the clock absence detection.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStop (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStart_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in interrupt mode.
__weak void | HAL_DFSDM_ChannelCkabCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Clock absence detection callback.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStop_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStart (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelPollForScd (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the short circuit detection.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStop (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStart_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in interrupt mode.
__weak void | HAL_DFSDM_ChannelScdCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Short circuit detection callback.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStop_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in interrupt mode.
int16_t | HAL_DFSDM_ChannelGetAwdValue (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get channel analog watchdog value.
HAL_StatusTypeDef | HAL_DFSDM_ChannelModifyOffset (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset)
This function allows to modify channel offset value.
HAL_DFSDM_Channel_StateTypeDef | HAL_DFSDM_ChannelGetState (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get the current DFSDM channel handle state.
HAL_StatusTypeDef | HAL_DFSDM_FilterInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initialize the DFSDM filter according to the specified parameters in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_DFSDM_FilterDeInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter.
__weak void | HAL_DFSDM_FilterMspInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initializes the DFSDM filter MSP.
__weak void | HAL_DFSDM_FilterMspDeInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter MSP.
HAL_StatusTypeDef | HAL_DFSDM_FilterConfigRegChannel (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t ContinuousMode)
This function allows to select channel and to enable/disable continuous mode for regular conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterConfigInjChannel (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to select channels for injected conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterPollForRegConversion (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of regular conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularMsbStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode and to get only the 16 most significant bits of conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in DMA mode.
int32_t | HAL_DFSDM_FilterGetRegularValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get regular conversion value.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterPollForInjConversion (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of injected conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedMsbStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode and to get only the 16 most significant bits of conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in DMA mode.
int32_t | HAL_DFSDM_FilterGetInjectedValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get injected conversion value.
HAL_StatusTypeDef | HAL_DFSDM_FilterAwdStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, DFSDM_Filter_AwdParamTypeDef *awdParam)
This function allows to start filter analog watchdog in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterAwdStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop filter analog watchdog in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterExdStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to start extreme detector feature.
HAL_StatusTypeDef | HAL_DFSDM_FilterExdStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop extreme detector feature.
int32_t | HAL_DFSDM_FilterGetExdMaxValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector maximum value.
int32_t | HAL_DFSDM_FilterGetExdMinValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector minimum value.
uint32_t | HAL_DFSDM_FilterGetConvTimeValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get conversion time value.
void | HAL_DFSDM_IRQHandler (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function handles the DFSDM interrupts.
__weak void | HAL_DFSDM_FilterRegConvCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Regular conversion complete callback.
__weak void | HAL_DFSDM_FilterRegConvHalfCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half regular conversion complete callback.
__weak void | HAL_DFSDM_FilterInjConvCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Injected conversion complete callback.
__weak void | HAL_DFSDM_FilterInjConvHalfCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half injected conversion complete callback.
__weak void | HAL_DFSDM_FilterAwdCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold)
Filter analog watchdog callback.
__weak void | HAL_DFSDM_FilterErrorCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Error callback.
HAL_DFSDM_Filter_StateTypeDef | HAL_DFSDM_FilterGetState (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter handle state.
uint32_t | HAL_DFSDM_FilterGetError (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter error.

Variables

__IO uint32_t | v_dfsdm1ChannelCounter = 0
DFSDM_Channel_HandleTypeDef * | a_dfsdm1ChannelHandle [DFSDM1_CHANNEL_NUMBER] = {NULL}

Detailed Description

This file provides firmware functions to manage the following functionalities of the Digital Filter for Sigma-Delta Modulators (DFSDM) peripherals: + Initialization and configuration of channels and filters + Regular channels configuration + Injected channels configuration + Regular/Injected Channels DMA Configuration + Interrupts and flags management + Analog watchdog feature + Short-circuit detector feature + Extremes detector feature + Clock absence detector feature + Break generation on analog watchdog or short-circuit event.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
  [..]
    *** Channel initialization ***
    ==============================
    [..]
      (#) User has first to initialize channels (before filters initialization).
      (#) As prerequisite, fill in the HAL_DFSDM_ChannelMspInit() :
        (++) Enable DFSDMz clock interface with __HAL_RCC_DFSDMz_CLK_ENABLE().
        (++) Enable the clocks for the DFSDMz GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
        (++) Configure these DFSDMz pins in alternate mode using HAL_GPIO_Init().
        (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global
            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
      (#) Configure the output clock, input, serial interface, analog watchdog,
          offset and data right bit shift parameters for this channel using the
          HAL_DFSDM_ChannelInit() function.

    *** Channel clock absence detector ***
    ======================================
    [..]
      (#) Start clock absence detector using HAL_DFSDM_ChannelCkabStart() or
          HAL_DFSDM_ChannelCkabStart_IT().
      (#) In polling mode, use HAL_DFSDM_ChannelPollForCkab() to detect the clock
          absence.
      (#) In interrupt mode, HAL_DFSDM_ChannelCkabCallback() will be called if
          clock absence is detected.
      (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or
          HAL_DFSDM_ChannelCkabStop_IT().
      (#) Please note that the same mode (polling or interrupt) has to be used
          for all channels because the channels are sharing the same interrupt.
      (#) Please note also that in interrupt mode, if clock absence detector is
          stopped for one channel, interrupt will be disabled for all channels.

    *** Channel short circuit detector ***
    ======================================
    [..]
      (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or
          or HAL_DFSDM_ChannelScdStart_IT().
      (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short
          circuit.
      (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if
          short circuit is detected.
      (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or
          or HAL_DFSDM_ChannelScdStop_IT().
      (#) Please note that the same mode (polling or interrupt) has to be used
          for all channels because the channels are sharing the same interrupt.
      (#) Please note also that in interrupt mode, if short circuit detector is
          stopped for one channel, interrupt will be disabled for all channels.

    *** Channel analog watchdog value ***
    =====================================
    [..]
      (#) Get analog watchdog filter value of a channel using
          HAL_DFSDM_ChannelGetAwdValue().

    *** Channel offset value ***
    =====================================
    [..]
      (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset().

    *** Filter initialization ***
    =============================
    [..]
      (#) After channel initialization, user has to init filters.
      (#) As prerequisite, fill in the HAL_DFSDM_FilterMspInit() :
        (++) If interrupt mode is used , enable and configure DFSDMz_FLTx global
            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
            Please note that DFSDMz_FLT0 global interrupt could be already
            enabled if interrupt is used for channel.
        (++) If DMA mode is used, configure DMA with HAL_DMA_Init() and link it
            with DFSDMz filter handle using __HAL_LINKDMA().
      (#) Configure the regular conversion, injected conversion and filter
          parameters for this filter using the HAL_DFSDM_FilterInit() function.

    *** Filter regular channel conversion ***
    =========================================
    [..]
      (#) Select regular channel and enable/disable continuous mode using
          HAL_DFSDM_FilterConfigRegChannel().
      (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(),
          HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or
          HAL_DFSDM_FilterRegularMsbStart_DMA().
      (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect
          the end of regular conversion.
      (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called
          at the end of regular conversion.
      (#) Get value of regular conversion and corresponding channel using
          HAL_DFSDM_FilterGetRegularValue().
      (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and
          HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the
          half transfer and at the transfer complete. Please note that
          HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA
          circular mode.
      (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(),
          HAL_DFSDM_FilterRegularStop_IT() or HAL_DFSDM_FilterRegularStop_DMA().

    *** Filter injected channels conversion ***
    ===========================================
    [..]
      (#) Select injected channels using HAL_DFSDM_FilterConfigInjChannel().
      (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(),
          HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or
          HAL_DFSDM_FilterInjectedMsbStart_DMA().
      (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect
          the end of injected conversion.
      (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called
          at the end of injected conversion.
      (#) Get value of injected conversion and corresponding channel using
          HAL_DFSDM_FilterGetInjectedValue().
      (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and
          HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the
          half transfer and at the transfer complete. Please note that
          HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA
          circular mode.
      (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(),
          HAL_DFSDM_FilterInjectedStop_IT() or HAL_DFSDM_FilterInjectedStop_DMA().

    *** Filter analog watchdog ***
    ==============================
    [..]
      (#) Start filter analog watchdog using HAL_DFSDM_FilterAwdStart_IT().
      (#) HAL_DFSDM_FilterAwdCallback() will be called if analog watchdog occurs.
      (#) Stop filter analog watchdog using HAL_DFSDM_FilterAwdStop_IT().

    *** Filter extreme detector ***
    ===============================
    [..]
      (#) Start filter extreme detector using HAL_DFSDM_FilterExdStart().
      (#) Get extreme detector maximum value using HAL_DFSDM_FilterGetExdMaxValue().
      (#) Get extreme detector minimum value using HAL_DFSDM_FilterGetExdMinValue().
      (#) Start filter extreme detector using HAL_DFSDM_FilterExdStop().

    *** Filter conversion time ***
    ==============================
    [..]
      (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue().
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_dfsdm.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dma.c File Reference

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Data Structures | Defines | Functions
stm32h7xx_hal_dma.c File Reference

DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Data Structures

struct | DMA_Base_Registers

Defines

#define | HAL_TIMEOUT_DMA_ABORT (5U) /* 5 ms */
#define | BDMA_PERIPH_TO_MEMORY (0x00000000U)
#define | BDMA_MEMORY_TO_PERIPH ((uint32_t)BDMA_CCR_DIR)
#define | BDMA_MEMORY_TO_MEMORY ((uint32_t)BDMA_CCR_MEM2MEM)
#define | D2_TO_D3_DMA_DIRECTION(__D2_DMA_DIRECTION__)
#define | D2_TO_D3_DMA_PERIPHERAL_INC(__D2_PERIPHERAL_INC__) ((__D2_PERIPHERAL_INC__) >> 3U)
#define | D2_TO_D3_DMA_MEMORY_INC(__D2_MEMORY_INC__) ((__D2_MEMORY_INC__) >> 3U)
#define | D2_TO_D3_DMA_PDATA_SIZE(__D2_PDATA_SIZE__) ((__D2_PDATA_SIZE__) >> 3U)
#define | D2_TO_D3_DMA_MDATA_SIZE(__D2_MDATA_SIZE__) ((__D2_MDATA_SIZE__) >> 3U)
#define | D2_TO_D3_DMA_MODE(__D2_MODE__) (((__D2_MODE__) >> 3U) & BDMA_CCR_CIRC)
#define | D2_TO_D3_DMA_PRIORITY(__D2_PRIORITY__) ((__D2_PRIORITY__) >> 4U)

Functions

static void | DMA_SetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Sets the DMA Transfer parameter.
static uint32_t | DMA_CalcBaseAndBitshift (DMA_HandleTypeDef *hdma)
Returns the DMA Stream base address depending on stream number.
static HAL_StatusTypeDef | DMA_CheckFifoParam (DMA_HandleTypeDef *hdma)
Check compatibility between FIFO threshold level and size of the memory burst.
static void | DMA_CalcDMAMUXChannelBaseAndMask (DMA_HandleTypeDef *hdma)
Updates the DMA handle with the DMAMUX channel and status mask depending on stream number.
static void | DMA_CalcDMAMUXRequestGenBaseAndMask (DMA_HandleTypeDef *hdma)
Updates the DMA handle with the DMAMUX request generator params.
HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitializes the DMA peripheral.
HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Starts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Returns the DMA state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
   (#) Enable and configure the peripheral to be connected to the DMA Stream
       (except for internal SRAM/FLASH memories: no initialization is
       necessary) please refer to Reference manual for connection between peripherals
       and DMA requests .

   (#) For a given Stream, program the required configuration through the following parameters:
       Transfer Direction, Source and Destination data formats,
       Circular, Normal or peripheral flow control mode, Stream Priority level,
       Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
       Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.

     *** Polling mode IO operation ***
     =================================
    [..]
          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
              address and destination address and the Length of data to be transferred
          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
              case a fixed Timeout can be configured by User depending from his application.

     *** Interrupt mode IO operation ***
     ===================================
    [..]
          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
              Source address and destination address and the Length of data to be transferred. In this
              case the DMA interrupt is configured
          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
              add his own function by customization of function pointer XferCpltCallback and
              XferErrorCallback (i.e a member of DMA handle structure).
    [..]
     (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
         detection.

     (#) Use HAL_DMA_Abort() function to abort the current transfer

     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.

     -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
           possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
           Half-Word data size for the peripheral to access its data register and set Word data size
           for the Memory to gain in access time. Each two half words will be packed and written in
           a single access to a Word in the Memory).

     -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
           and Destination. In this case the Peripheral Data Size will be applied to both Source
           and Destination.

     *** DMA HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DMA HAL driver.

      (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
      (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
      (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
      (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
      (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
      (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.

     [..]
      (@) You can refer to the DMA HAL driver header file for more useful macros.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_dma.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dma2d.c File Reference

  • File List
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Defines | Functions
stm32h7xx_hal_dma2d.c File Reference

DMA2D HAL module driver. This file provides firmware functions to manage the following functionalities of the DMA2D peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | DMA2D_TIMEOUT_ABORT ((uint32_t)1000)
#define | DMA2D_TIMEOUT_SUSPEND ((uint32_t)1000)
#define | DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS)
#define | DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS)
#define | DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM)
#define | DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM)
#define | DMA2D_POSITION_OPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_OPFCCR_AI)
#define | DMA2D_POSITION_FGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AI)
#define | DMA2D_POSITION_BGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AI)
#define | DMA2D_POSITION_OPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_OPFCCR_RBS)
#define | DMA2D_POSITION_FGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_RBS)
#define | DMA2D_POSITION_BGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_RBS)
#define | DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT)
#define | DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM)
#define | DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM)
#define | DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA)
#define | DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA)
#define | DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL)
#define | DMA2D_POSITION_FGPFCCR_CSS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CSS)

Functions

static void | DMA2D_SetConfig (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Set the DMA2D transfer parameters.
HAL_StatusTypeDef | HAL_DMA2D_Init (DMA2D_HandleTypeDef *hdma2d)
Initialize the DMA2D according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d)
Deinitializes the DMA2D peripheral registers to their default reset values.
__weak void | HAL_DMA2D_MspInit (DMA2D_HandleTypeDef *hdma2d)
Initializes the DMA2D MSP.
__weak void | HAL_DMA2D_MspDeInit (DMA2D_HandleTypeDef *hdma2d)
DeInitializes the DMA2D MSP.
HAL_StatusTypeDef | HAL_DMA2D_Start (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Start_IT (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the DMA2D Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_BlendingStart (DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the multi-source DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_BlendingStart_IT (DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the multi-source DMA2D Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_Abort (DMA2D_HandleTypeDef *hdma2d)
Abort the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Suspend (DMA2D_HandleTypeDef *hdma2d)
Suspend the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Resume (DMA2D_HandleTypeDef *hdma2d)
Resume the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_EnableCLUT (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Enable the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoad (DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Start DMA2D CLUT Loading.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoad_IT (DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Start DMA2D CLUT Loading with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoading_Abort (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Abort the DMA2D CLUT loading.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoading_Suspend (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Suspend the DMA2D CLUT loading.
HAL_StatusTypeDef | HAL_DMA2D_CLUTLoading_Resume (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Resume the DMA2D CLUT loading.
HAL_StatusTypeDef | HAL_DMA2D_PollForTransfer (DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
Polling for transfer complete or CLUT loading.
void | HAL_DMA2D_IRQHandler (DMA2D_HandleTypeDef *hdma2d)
Handle DMA2D interrupt request.
__weak void | HAL_DMA2D_LineEventCallback (DMA2D_HandleTypeDef *hdma2d)
Transfer watermark callback.
__weak void | HAL_DMA2D_CLUTLoadingCpltCallback (DMA2D_HandleTypeDef *hdma2d)
CLUT Transfer Complete callback.
HAL_StatusTypeDef | HAL_DMA2D_ConfigLayer (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Configure the DMA2D Layer according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA2D_ConfigCLUT (DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Configure the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_ProgramLineEvent (DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
Configure the line watermark.
HAL_StatusTypeDef | HAL_DMA2D_EnableDeadTime (DMA2D_HandleTypeDef *hdma2d)
Enable DMA2D dead time feature.
HAL_StatusTypeDef | HAL_DMA2D_DisableDeadTime (DMA2D_HandleTypeDef *hdma2d)
Disable DMA2D dead time feature.
HAL_StatusTypeDef | HAL_DMA2D_ConfigDeadTime (DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
Configure dead time.
HAL_DMA2D_StateTypeDef | HAL_DMA2D_GetState (DMA2D_HandleTypeDef *hdma2d)
Return the DMA2D state.
uint32_t | HAL_DMA2D_GetError (DMA2D_HandleTypeDef *hdma2d)
Return the DMA2D error code.

Detailed Description

DMA2D HAL module driver. This file provides firmware functions to manage the following functionalities of the DMA2D peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      (#) Program the required configuration through the following parameters:
          the transfer mode, the output color mode and the output offset using
          HAL_DMA2D_Init() function.

      (#) Program the required configuration through the following parameters:
          the input color mode, the input color, the input alpha value, the alpha mode,
          the red/blue swap mode, the inverted alpha mode and the input offset using
          HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.

     *** Polling mode IO operation ***
     =================================
    [..]
       (#) Configure pdata parameter (explained hereafter), destination and data length
           and enable the transfer using HAL_DMA2D_Start().
       (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
           user can specify the value of timeout according to his end application.

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (#) Configure pdata parameter, destination and data length and enable
           the transfer using HAL_DMA2D_Start_IT().
       (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
       (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
           add his own function by customization of function pointer XferCpltCallback (member
           of DMA2D handle structure).
       (#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback
           XferErrorCallback.

         -@-   In Register-to-Memory transfer mode, pdata parameter is the register
               color, in Memory-to-memory or Memory-to-Memory with pixel format
               conversion pdata is the source address.

         -@-   Configure the foreground source address, the background source address,
               the destination and data length then Enable the transfer using
               HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
               in interrupt mode.

         -@-   HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
               are used if the memory to memory with blending transfer mode is selected.

      (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
          mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.

      (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent()

      (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
          consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
          and enable/disable the functionality  with the APIs HAL_DMA2D_EnableDeadTime() or
          HAL_DMA2D_DisableDeadTime().

      (#) The transfer can be suspended, resumed and aborted using the following
          functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().

      (#) The CLUT loading can be suspended, resumed and aborted using the following
          functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
          HAL_DMA2D_CLUTLoading_Abort().

      (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().

      (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().

     *** DMA2D HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DMA2D HAL driver :

      (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
      (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
      (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
      (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
      (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
      (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.

     [..]
      (@) You can refer to the DMA2D HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_dma2d.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dma_ex.c File Reference

  • File List
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Defines | Functions
stm32h7xx_hal_dma_ex.c File Reference

DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | DMAMUX_POSITION_CxCR_SE (uint32_t)POSITION_VAL(DMAMUX_CxCR_SE)
#define | DMAMUX_POSITION_CxCR_EGE (uint32_t)POSITION_VAL(DMAMUX_CxCR_EGE)

Functions

static void | DMA_MultiBufferSetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Set the DMA Transfer parameter.
HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer.
HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMAEx_ChangeMemory (DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
Change the memory0 or memory1 address on the fly.
HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxSync (DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
Configure the DMAMUX synchronization parameters for a given DMA stream (instance).
HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
Configure the DMAMUX request generator block used by the given DMA stream (instance).
HAL_StatusTypeDef | HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Enable the DMAMUX request generator block used by the given DMA stream (instance).
HAL_StatusTypeDef | HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Disable the DMAMUX request generator block used by the given DMA stream (instance).
void | HAL_DMAEx_MUX_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMAMUX interrupt request.

Detailed Description

DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
  The DMA Extension HAL driver can be used as follows:
   (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
       for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.

   (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
   (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
       Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
       to respectively enable/disable the request generator.

   (+) To handle the DMAMUX Interrupts, the function  HAL_DMA_MUX_IRQHandler should be called from
       the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler .
       As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMA_MUX_IRQHandler should be
       called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
      (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)

     -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
     -@-  When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
     -@-  In Multi (Double) buffer mode, it is possible to update the base address for
          the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
     -@-  Multi (Double) buffer mode is only possible with D2 DMAs i.e DMA1 or DMA2. not BDMA.
          Multi (Double) buffer mode is not possible with D3 BDMA.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_dma_ex.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_eth.c File Reference

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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_eth.c File Reference

ETH HAL module driver. This file provides firmware functions to manage the following functionalities of the Ethernet (ETH) peripheral: + Initialization and deinitialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | ETH_MACCR_MASK ((uint32_t)0xFFFB7F7CU)
#define | ETH_MACECR_MASK ((uint32_t)0x3F077FFFU)
#define | ETH_MACPFR_MASK ((uint32_t)0x800007FFF)
#define | ETH_MACWTR_MASK ((uint32_t)0x0000010FU)
#define | ETH_MACTFCR_MASK ((uint32_t)0xFFFF00F2U)
#define | ETH_MACRFCR_MASK ((uint32_t)0x00000003U)
#define | ETH_MTLTQOMR_MASK ((uint32_t)0x00000072U)
#define | ETH_MTLRQOMR_MASK ((uint32_t)0x0000007BU)
#define | ETH_DMAMR_MASK ((uint32_t)0x00007802U)
#define | ETH_DMASBMR_MASK ((uint32_t)0x0000D001U)
#define | ETH_DMACCR_MASK ((uint32_t)0x00013FFFU)
#define | ETH_DMACTCR_MASK ((uint32_t)0x003F1010U)
#define | ETH_DMACRCR_MASK ((uint32_t)0x803F0000U)
#define | ETH_MACPCSR_MASK
#define | ETH_SWRESET_TIMEOUT ((uint32_t)500U)
#define | ETH_MDIO_BUS_TIMEOUT ((uint32_t)1000U)
#define | ETH_DMARXNDESCWBF_ERRORS_MASK
#define | ETH_MAC_US_TICK ((uint32_t)1000000U)
#define | INCR_TX_DESC_INDEX(inx, offset)
#define | INCR_RX_DESC_INDEX(inx, offset)

Functions

static void | ETH_MAC_MDIO_ClkConfig (ETH_HandleTypeDef *heth)
Configures the Clock range of SMI interface.
static void | ETH_SetMACConfig (ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
static void | ETH_SetDMAConfig (ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
static void | ETH_MACDMAConfig (ETH_HandleTypeDef *heth)
Configures Ethernet MAC and DMA with default parameters.
static void | ETH_DMATxDescListInit (ETH_HandleTypeDef *heth)
Initializes the DMA Tx descriptors.
static void | ETH_DMARxDescListInit (ETH_HandleTypeDef *heth)
Initializes the DMA Rx descriptors in chain mode.
static uint32_t | ETH_Prepare_Tx_Descriptors (ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode)
Prepare Tx DMA descriptor before transmission.
HAL_StatusTypeDef | HAL_ETH_Init (ETH_HandleTypeDef *heth)
Initialize the Ethernet peripheral registers.
HAL_StatusTypeDef | HAL_ETH_DeInit (ETH_HandleTypeDef *heth)
DeInitializes the ETH peripheral.
__weak void | HAL_ETH_MspInit (ETH_HandleTypeDef *heth)
Initializes the ETH MSP.
__weak void | HAL_ETH_MspDeInit (ETH_HandleTypeDef *heth)
DeInitializes ETH MSP.
HAL_StatusTypeDef | HAL_ETH_DescAssignMemory (ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1, uint8_t *pBuffer2)
Assign memory buffers to a DMA Rx descriptor.
HAL_StatusTypeDef | HAL_ETH_Start (ETH_HandleTypeDef *heth)
Enables Ethernet MAC and DMA reception and transmission.
HAL_StatusTypeDef | HAL_ETH_Start_IT (ETH_HandleTypeDef *heth)
Enables Ethernet MAC and DMA reception/transmission in Interrupt mode.
HAL_StatusTypeDef | HAL_ETH_Stop (ETH_HandleTypeDef *heth)
Stop Ethernet MAC and DMA reception/transmission.
HAL_StatusTypeDef | HAL_ETH_Stop_IT (ETH_HandleTypeDef *heth)
Stop Ethernet MAC and DMA reception/transmission in Interrupt mode.
HAL_StatusTypeDef | HAL_ETH_Transmit (ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout)
Sends an Ethernet Packet in polling mode.
HAL_StatusTypeDef | HAL_ETH_Transmit_IT (ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig)
Sends an Ethernet Packet in interrupt mode.
uint8_t | HAL_ETH_IsRxDataAvailable (ETH_HandleTypeDef *heth)
Checks for received Packets.
HAL_StatusTypeDef | HAL_ETH_GetRxDataBuffer (ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer)
This function gets the buffer address of last received Packet.
HAL_StatusTypeDef | HAL_ETH_GetRxDataLength (ETH_HandleTypeDef *heth, uint32_t *Length)
This function gets the length of last received Packet.
HAL_StatusTypeDef | HAL_ETH_GetRxDataInfo (ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo)
Get the Rx data info (Packet type, VLAN tag, Filters status, ...)
HAL_StatusTypeDef | HAL_ETH_BuildRxDescriptors (ETH_HandleTypeDef *heth)
This function gives back Rx Desc of the last received Packet to the DMA, so ETH DMA will be able to use these descriptors to receive next Packets.
void | HAL_ETH_IRQHandler (ETH_HandleTypeDef *heth)
This function handles ETH interrupt request.
__weak void | HAL_ETH_TxCpltCallback (ETH_HandleTypeDef *heth)
Tx Transfer completed callbacks.
__weak void | HAL_ETH_RxCpltCallback (ETH_HandleTypeDef *heth)
Rx Transfer completed callbacks.
__weak void | HAL_ETH_DMAErrorCallback (ETH_HandleTypeDef *heth)
Ethernet DMA transfer error callbacks.
__weak void | HAL_ETH_MACErrorCallback (ETH_HandleTypeDef *heth)
Ethernet MAC transfer error callbacks.
__weak void | HAL_ETH_PMTCallback (ETH_HandleTypeDef *heth)
Ethernet Power Management module IT callback.
__weak void | HAL_ETH_EEECallback (ETH_HandleTypeDef *heth)
Energy Efficient Etherent IT callback.
__weak void | HAL_ETH_WakeUpCallback (ETH_HandleTypeDef *heth)
ETH WAKEUP interrupt callback.
HAL_StatusTypeDef | HAL_ETH_ReadPHYRegister (ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue)
Read a PHY register.
HAL_StatusTypeDef | HAL_ETH_WritePHYRegister (ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue)
Writes to a PHY register.
HAL_StatusTypeDef | HAL_ETH_GetMACConfig (ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
Get the configuration of the MAC and MTL subsystems.
HAL_StatusTypeDef | HAL_ETH_GetDMAConfig (ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
Get the configuration of the DMA.
HAL_StatusTypeDef | HAL_ETH_SetMACConfig (ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
Set the MAC configuration.
HAL_StatusTypeDef | HAL_ETH_SetDMAConfig (ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
Set the ETH DMA configuration.
void | HAL_ETH_SetMDIOClockRange (ETH_HandleTypeDef *heth)
Configures the Clock range of ETH MDIO interface.
HAL_StatusTypeDef | HAL_ETH_SetMACFilterConfig (ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
Set the ETH MAC (L2) Filters configuration.
HAL_StatusTypeDef | HAL_ETH_GetMACFilterConfig (ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
Get the ETH MAC (L2) Filters configuration.
HAL_StatusTypeDef | HAL_ETH_SetSourceMACAddrMatch (ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr)
Set the source MAC Address to be matched.
HAL_StatusTypeDef | HAL_ETH_SetHashTable (ETH_HandleTypeDef *heth, uint32_t *pHashTable)
Set the ETH Hash Table Value.
void | HAL_ETH_SetRxVLANIdentifier (ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier)
Set the VLAN Identifier for Rx packets.
void | HAL_ETH_EnterPowerDownMode (ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig)
Enters the Power down mode.
void | HAL_ETH_ExitPowerDownMode (ETH_HandleTypeDef *heth)
Exits from the Power down mode.
HAL_StatusTypeDef | HAL_ETH_SetWakeUpFilter (ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count)
Set the WakeUp filter.
HAL_ETH_StateTypeDef | HAL_ETH_GetState (ETH_HandleTypeDef *heth)
Returns the ETH state.
uint32_t | HAL_ETH_GetError (ETH_HandleTypeDef *heth)
Returns the ETH error code.
uint32_t | HAL_ETH_GetDMAError (ETH_HandleTypeDef *heth)
Returns the ETH DMA error code.
uint32_t | HAL_ETH_GetMACError (ETH_HandleTypeDef *heth)
Returns the ETH MAC error code.
uint32_t | HAL_ETH_GetMACWakeUpSource (ETH_HandleTypeDef *heth)
Returns the ETH MAC WakeUp event source.

Detailed Description

ETH HAL module driver. This file provides firmware functions to manage the following functionalities of the Ethernet (ETH) peripheral: + Initialization and deinitialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
     [..]
     The ETH HAL driver can be used as follows:

      (#)Declare a ETH_HandleTypeDef handle structure, for example:
         ETH_HandleTypeDef  heth;

      (#)Fill parameters of Init structure in heth handle

      (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)

      (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
          (##) Enable the Ethernet interface clock using
                (+++)  __HAL_RCC_ETH1MAC_CLK_ENABLE()
                (+++)  __HAL_RCC_ETH1TX_CLK_ENABLE()
                (+++)  __HAL_RCC_ETH1RX_CLK_ENABLE()

          (##) Initialize the related GPIO clocks
          (##) Configure Ethernet pinout
          (##) Configure Ethernet NVIC interrupt (in Interrupt mode)

      (#) Ethernet data reception is asynchronous, so call the following API
          to start the listening mode:
          (##) HAL_ETH_Start():
               This API starts the MAC and DMA transmission and reception process,
               without enabling end of transfer interrupts, in this mode user
               has to poll for data availability by calling HAL_ETH_IsRxDataAvailable()
          (##) HAL_ETH_Start_IT():
               This API starts the MAC and DMA transmission and reception process,
               end of transfer interrupts are enabled in this mode,
               HAL_ETH_RxCpltCallback() will be executed when an Ethernet packet is received

      (#) When data is received (HAL_ETH_IsRxDataAvailable() returns 1 or Rx interrupt
          occurred), user can call the following APIs to get received data:
          (##) HAL_ETH_GetRxDataBuffer(): Get buffer address of received frame
          (##) HAL_ETH_GetRxDataLength(): Get received frame length
          (##) HAL_ETH_GetRxDataInfo(): Get received frame additional info,
               please refer to ETH_RxPacketInfo typedef structure

      (#) For transmission path, two APIs are available:
         (##) HAL_ETH_Transmit(): Transmit an ETH frame in blocking mode
         (##) HAL_ETH_Transmit_IT(): Transmit an ETH frame in interrupt mode,
              HAL_ETH_TxCpltCallback() will be executed when end of transfer occur

      (#) Communication with an external PHY device:
         (##) HAL_ETH_ReadPHYRegister(): Read a register from an external PHY
         (##) HAL_ETH_WritePHYRegister(): Write data to an external RHY register

      (#) Configure the Ethernet MAC after ETH peripheral initialization
          (##) HAL_ETH_GetMACConfig(): Get MAC actual configuration into ETH_MACConfigTypeDef
          (##) HAL_ETH_SetMACConfig(): Set MAC configuration based on ETH_MACConfigTypeDef

      (#) Configure the Ethernet DMA after ETH peripheral initialization
          (##) HAL_ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef
          (##) HAL_ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef

      -@- The PTP protocol offload APIs are  not supported in this driver.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_eth.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_eth_ex.c File Reference

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Defines | Functions
stm32h7xx_hal_eth_ex.c File Reference

ETH HAL Extended module driver. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | ETH_MACL4CR_MASK
#define | ETH_MACL3CR_MASK
#define | ETH_MACRXVLAN_MASK
#define | ETH_MACTXVLAN_MASK

Functions

void | HAL_ETHEx_EnableARPOffload (ETH_HandleTypeDef *heth)
Enables ARP Offload.
void | HAL_ETHEx_DisableARPOffload (ETH_HandleTypeDef *heth)
Disables ARP Offload.
void | HAL_ETHEx_SetARPAddressMatch (ETH_HandleTypeDef *heth, uint32_t IpAddress)
Set the ARP Match IP address.
HAL_StatusTypeDef | HAL_ETHEx_SetL4FilterConfig (ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig)
Configures the L4 Filter, this function allow to: set the layer 4 protocol to be matched (TCP or UDP) enable/disable L4 source/destination port perfect/inverse match.
HAL_StatusTypeDef | HAL_ETHEx_GetL4FilterConfig (ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig)
Configures the L4 Filter, this function allow to: set the layer 4 protocol to be matched (TCP or UDP) enable/disable L4 source/destination port perfect/inverse match.
HAL_StatusTypeDef | HAL_ETHEx_SetL3FilterConfig (ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
Configures the L3 Filter, this function allow to: set the layer 3 protocol to be matched (IPv4 or IPv6) enable/disable L3 source/destination port perfect/inverse match.
HAL_StatusTypeDef | HAL_ETHEx_GetL3FilterConfig (ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
Configures the L3 Filter, this function allow to: set the layer 3 protocol to be matched (IPv4 or IPv6) enable/disable L3 source/destination port perfect/inverse match.
void | HAL_ETHEx_EnableL3L4Filtering (ETH_HandleTypeDef *heth)
Enables L3 and L4 filtering process.
void | HAL_ETHEx_DisableL3L4Filtering (ETH_HandleTypeDef *heth)
Disables L3 and L4 filtering process.
HAL_StatusTypeDef | HAL_ETHEx_GetRxVLANConfig (ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
Get the VLAN Configuration for Receive Packets.
HAL_StatusTypeDef | HAL_ETHEx_SetRxVLANConfig (ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
Set the VLAN Configuration for Receive Packets.
void | HAL_ETHEx_SetVLANHashTable (ETH_HandleTypeDef *heth, uint32_t VLANHashTable)
Set the VLAN Hash Table.
HAL_StatusTypeDef | HAL_ETHEx_GetTxVLANConfig (ETH_HandleTypeDef *heth, uint32_t VLANTag, ETH_TxVLANConfigTypeDef *pVlanConfig)
Get the VLAN Configuration for Transmit Packets.
HAL_StatusTypeDef | HAL_ETHEx_SetTxVLANConfig (ETH_HandleTypeDef *heth, uint32_t VLANTag, ETH_TxVLANConfigTypeDef *pVlanConfig)
Set the VLAN Configuration for Transmit Packets.
void | HAL_ETHEx_SetTxVLANIdentifier (ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier)
Set the VLAN Tag Identifier for Transmit Packets.
void | HAL_ETHEx_EnableVLANProcessing (ETH_HandleTypeDef *heth)
Enables the VLAN Tag Filtering process.
void | HAL_ETHEx_DisableVLANProcessing (ETH_HandleTypeDef *heth)
Disables the VLAN Tag Filtering process.
void | HAL_ETHEx_EnterLPIMode (ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop)
Enters the Low Power Idle (LPI) mode.
void | HAL_ETHEx_ExitLPIMode (ETH_HandleTypeDef *heth)
Exits the Low Power Idle (LPI) mode.
uint32_t | HAL_ETHEx_GetMACLPIEvent (ETH_HandleTypeDef *heth)
Returns the ETH MAC LPI event.

Detailed Description

ETH HAL Extended module driver.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_eth_ex.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_fdcan.c File Reference

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stm32h7xx_hal_fdcan.c File Reference

FDCAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Flexible DataRate Controller Area Network (FDCAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Configuration and Control functions + Peripheral State and Error functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | FDCAN_TIMEOUT_VALUE 10
#define | FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFW | FDCAN_IR_TEFN)
#define | FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0W | FDCAN_IR_RF0N)
#define | FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1W | FDCAN_IR_RF1N)
#define | FDCAN_ERROR_MASK
#define | FDCAN_TT_SCHEDULE_SYNC_MASK (FDCAN_TTIR_SBC | FDCAN_TTIR_SMC | FDCAN_TTIR_CSM | FDCAN_TTIR_SOG)
#define | FDCAN_TT_TIME_MARK_MASK (FDCAN_TTIR_RTMI | FDCAN_TTIR_TTMI)
#define | FDCAN_TT_GLOBAL_TIME_MASK (FDCAN_TTIR_GTW | FDCAN_TTIR_GTD)
#define | FDCAN_TT_DISTURBING_ERROR_MASK
#define | FDCAN_TT_FATAL_ERROR_MASK (FDCAN_TTIR_IWT | FDCAN_TTIR_WT | FDCAN_TTIR_AW | FDCAN_TTIR_CER)
#define | FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */
#define | FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */
#define | FDCAN_ELEMENT_MASK_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */
#define | FDCAN_ELEMENT_MASK_XTD ((uint32_t)0x40000000U) /* Extended Identifier */
#define | FDCAN_ELEMENT_MASK_ESI ((uint32_t)0x80000000U) /* Error State Indicator */
#define | FDCAN_ELEMENT_MASK_TS ((uint32_t)0x0000FFFFU) /* Timestamp */
#define | FDCAN_ELEMENT_MASK_DLC ((uint32_t)0x000F0000U) /* Data Length Code */
#define | FDCAN_ELEMENT_MASK_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */
#define | FDCAN_ELEMENT_MASK_FDF ((uint32_t)0x00200000U) /* FD Format */
#define | FDCAN_ELEMENT_MASK_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */
#define | FDCAN_ELEMENT_MASK_MM ((uint32_t)0xFF000000U) /* Message Marker */
#define | FDCAN_ELEMENT_MASK_FIDX ((uint32_t)0x7F000000U) /* Filter Index */
#define | FDCAN_ELEMENT_MASK_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
#define | FDCAN_ELEMENT_MASK_ET ((uint32_t)0x00C00000U) /* Event type */

Functions

static HAL_StatusTypeDef | FDCAN_CalcultateRamBlockAddresses (FDCAN_HandleTypeDef *hfdcan)
Calculate each RAM block start address and size.
static HAL_StatusTypeDef | FDCAN_CopyMessageToRAM (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
Copy Tx message to the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_Init (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN peripheral according to the specified parameters in the FDCAN_InitTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_DeInit (FDCAN_HandleTypeDef *hfdcan)
Deinitializes the FDCAN peripheral registers to their default reset values.
__weak void | HAL_FDCAN_MspInit (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN MSP.
__weak void | HAL_FDCAN_MspDeInit (FDCAN_HandleTypeDef *hfdcan)
DeInitializes the FDCAN MSP.
HAL_StatusTypeDef | HAL_FDCAN_EnterPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Enter FDCAN peripheral in sleep mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Exit power down mode.
HAL_StatusTypeDef | HAL_FDCAN_ConfigClockCalibration (FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig)
Configure the FDCAN clock calibration unit according to the specified parameters in the FDCAN_ClkCalUnitTypeDef structure.
uint32_t | HAL_FDCAN_GetClockCalibrationState (FDCAN_HandleTypeDef *hfdcan)
Get the clock calibration state.
HAL_StatusTypeDef | HAL_FDCAN_ResetClockCalibrationState (FDCAN_HandleTypeDef *hfdcan)
Reset the clock calibration state.
uint32_t | HAL_FDCAN_GetClockCalibrationCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t Counter)
Get the clock calibration counter value.
HAL_StatusTypeDef | HAL_FDCAN_ConfigFilter (FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
Configure the FDCAN reception filter according to the specified parameters in the FDCAN_FilterTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_ConfigGlobalFilter (FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt)
Configure the FDCAN global filter.
HAL_StatusTypeDef | HAL_FDCAN_ConfigExtendedIdMask (FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
Configure the extended ID mask.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRxFifoOverwrite (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
Configure the Rx FIFO operation mode.
HAL_StatusTypeDef | HAL_FDCAN_ConfigFifoWatermark (FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark)
Configure the FIFO watermark.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRamWatchdog (FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
Configure the RAM watchdog.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
Configure the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
Enable the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timestamp counter.
uint16_t | HAL_FDCAN_GetTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Get the timestamp counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timestamp counter to zero.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimeoutCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
Configure the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Enable the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timeout counter.
uint16_t | HAL_FDCAN_GetTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Get the timeout counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timeout counter to its start value.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
Configure the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_EnableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Enable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_DisableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Disable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_Start (FDCAN_HandleTypeDef *hfdcan)
Start the FDCAN module.
HAL_StatusTypeDef | HAL_FDCAN_Stop (FDCAN_HandleTypeDef *hfdcan)
Stop the FDCAN module and enable access to configuration registers.
HAL_StatusTypeDef | HAL_FDCAN_AddMessageToTxFifoQ (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData)
Add a message to the Tx FIFO/Queue and activate the corresponding transmission request.
HAL_StatusTypeDef | HAL_FDCAN_AddMessageToTxBuffer (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
Add a message to a dedicated Tx buffer.
HAL_StatusTypeDef | HAL_FDCAN_EnableTxBufferRequest (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
Enable transmission request.
HAL_StatusTypeDef | HAL_FDCAN_AbortTxRequest (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
Abort transmission request.
HAL_StatusTypeDef | HAL_FDCAN_GetRxMessage (FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetTxEvent (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetHighPriorityMessageStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
Get high priority message status.
HAL_StatusTypeDef | HAL_FDCAN_GetProtocolStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
Get protocol status.
HAL_StatusTypeDef | HAL_FDCAN_GetErrorCounters (FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
Get error counter values.
uint32_t | HAL_FDCAN_IsRxBufferMessageAvailable (FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex)
Check if a new message is received in the selected Rx buffer.
uint32_t | HAL_FDCAN_IsTxBufferMessagePending (FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
Check if a transmission request is pending on the selected Tx buffer.
uint32_t | HAL_FDCAN_GetRxFifoFillLevel (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
Return Rx FIFO fill level.
uint32_t | HAL_FDCAN_GetTxFifoFreeLevel (FDCAN_HandleTypeDef *hfdcan)
Return Tx FIFO free level: number of consecutive free Tx FIFO elements starting from Tx FIFO GetIndex.
uint32_t | HAL_FDCAN_IsRestrictedOperationMode (FDCAN_HandleTypeDef *hfdcan)
Check if the FDCAN peripheral entered Restricted Operation Mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitRestrictedOperationMode (FDCAN_HandleTypeDef *hfdcan)
Exit Restricted Operation Mode.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigOperation (FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams)
Initialize TT operation parameters.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigReferenceMessage (FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload)
Configure the reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigTrigger (FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig)
Configure the FDCAN trigger according to the specified parameters in the FDCAN_TriggerTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_TT_SetGlobalTime (FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset)
Schedule global time adjustment for the next reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_SetClockSynchronization (FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator)
Schedule TUR numerator update for the next reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigStopWatch (FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity)
Configure stop watch source and polarity.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigRegisterTimeMark (FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle)
Configure register time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableRegisterTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Enable register time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableRegisterTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Disable register time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableTriggerTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Enable trigger time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableTriggerTimeMarkPulse (FDCAN_HandleTypeDef *hfdcan)
Disable trigger time mark pulse generation.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableHardwareGapControl (FDCAN_HandleTypeDef *hfdcan)
Enable gap control by input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableHardwareGapControl (FDCAN_HandleTypeDef *hfdcan)
Disable gap control by input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableTimeMarkGapControl (FDCAN_HandleTypeDef *hfdcan)
Enable gap control (finish only) by register time mark interrupt.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableTimeMarkGapControl (FDCAN_HandleTypeDef *hfdcan)
Disable gap control by register time mark interrupt.
HAL_StatusTypeDef | HAL_FDCAN_TT_SetNextIsGap (FDCAN_HandleTypeDef *hfdcan)
Transmit next reference message with Next_is_Gap = "1".
HAL_StatusTypeDef | HAL_FDCAN_TT_SetEndOfGap (FDCAN_HandleTypeDef *hfdcan)
Finish a Gap by requesting start of reference message.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigExternalSyncPhase (FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase)
Configure target phase used for external synchronization by event trigger input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_EnableExternalSynchronization (FDCAN_HandleTypeDef *hfdcan)
Synchronize the phase of the FDCAN schedule to an external schedule using event trigger input pin fdcan1_evt.
HAL_StatusTypeDef | HAL_FDCAN_TT_DisableExternalSynchronization (FDCAN_HandleTypeDef *hfdcan)
Disable external schedule synchronization.
HAL_StatusTypeDef | HAL_FDCAN_TT_GetOperationStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus)
Get TT operation status.
HAL_StatusTypeDef | HAL_FDCAN_ConfigInterruptLines (FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
Assign interrupts to either Interrupt line 0 or 1.
HAL_StatusTypeDef | HAL_FDCAN_TT_ConfigInterruptLines (FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine)
Assign TT interrupts to either Interrupt line 0 or 1.
HAL_StatusTypeDef | HAL_FDCAN_ActivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
Enable interrupts.
HAL_StatusTypeDef | HAL_FDCAN_DeactivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
Disable interrupts.
HAL_StatusTypeDef | HAL_FDCAN_TT_ActivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs)
Enable TT interrupts.
HAL_StatusTypeDef | HAL_FDCAN_TT_DeactivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs)
Disable TT interrupts.
void | HAL_FDCAN_IRQHandler (FDCAN_HandleTypeDef *hfdcan)
Handles FDCAN interrupt request.
__weak void | HAL_FDCAN_ClockCalibrationCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)
Clock Calibration callback.
__weak void | HAL_FDCAN_TxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
Tx Event callback.
__weak void | HAL_FDCAN_RxFifo0Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
Rx FIFO 0 callback.
__weak void | HAL_FDCAN_RxFifo1Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
Rx FIFO 1 callback.
__weak void | HAL_FDCAN_TxFifoEmptyCallback (FDCAN_HandleTypeDef *hfdcan)
Tx FIFO Empty callback.
__weak void | HAL_FDCAN_TxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Complete callback.
__weak void | HAL_FDCAN_TxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Cancellation callback.
__weak void | HAL_FDCAN_RxBufferNewMessageCallback (FDCAN_HandleTypeDef *hfdcan)
Rx Buffer New Message callback.
__weak void | HAL_FDCAN_TimestampWraparoundCallback (FDCAN_HandleTypeDef *hfdcan)
Timestamp Wraparound callback.
__weak void | HAL_FDCAN_TimeoutOccurredCallback (FDCAN_HandleTypeDef *hfdcan)
Timeout Occurred callback.
__weak void | HAL_FDCAN_HighPriorityMessageCallback (FDCAN_HandleTypeDef *hfdcan)
High Priority Message callback.
__weak void | HAL_FDCAN_ErrorCallback (FDCAN_HandleTypeDef *hfdcan)
Error callback.
__weak void | HAL_FDCAN_TT_ScheduleSyncCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)
TT Schedule Synchronization callback.
__weak void | HAL_FDCAN_TT_TimeMarkCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)
TT Time Mark callback.
__weak void | HAL_FDCAN_TT_StopWatchCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)
TT Stop Watch callback.
__weak void | HAL_FDCAN_TT_GlobalTimeCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)
TT Global Time callback.
HAL_FDCAN_StateTypeDef | HAL_FDCAN_GetState (FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN state.
uint32_t | HAL_FDCAN_GetError (FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN error code.

Variables

static const uint8_t | DLCtoBytes [] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}
static const uint8_t | CvtEltSize [] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7}

Detailed Description

FDCAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Flexible DataRate Controller Area Network (FDCAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Configuration and Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function.

      (#) If needed , configure the reception filters and optional features using
          the following configuration functions:
            (++) HAL_FDCAN_ConfigClockCalibration
            (++) HAL_FDCAN_ConfigFilter
            (++) HAL_FDCAN_ConfigGlobalFilter
            (++) HAL_FDCAN_ConfigExtendedIdMask
            (++) HAL_FDCAN_ConfigRxFifoOverwrite
            (++) HAL_FDCAN_ConfigFifoWatermark
            (++) HAL_FDCAN_ConfigRamWatchdog
            (++) HAL_FDCAN_ConfigTimestampCounter
            (++) HAL_FDCAN_EnableTimestampCounter
            (++) HAL_FDCAN_DisableTimestampCounter
            (++) HAL_FDCAN_ConfigTimeoutCounter
            (++) HAL_FDCAN_EnableTimeoutCounter
            (++) HAL_FDCAN_DisableTimeoutCounter
            (++) HAL_FDCAN_ConfigTxDelayCompensation
            (++) HAL_FDCAN_EnableTxDelayCompensation
            (++) HAL_FDCAN_DisableTxDelayCompensation
            (++) HAL_FDCAN_TT_ConfigOperation
            (++) HAL_FDCAN_TT_ConfigReferenceMessage
            (++) HAL_FDCAN_TT_ConfigTrigger

      (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level
          the node is active on the bus: it can send and receive messages.

      (#) The following Tx control functions can only be called when the FDCAN
          module is started:
            (++) HAL_FDCAN_AddMessageToTxFifoQ
            (++) HAL_FDCAN_EnableTxBufferRequest
            (++) HAL_FDCAN_AbortTxRequest

      (#) When a message is received into the FDCAN message RAM, it can be
          retrieved using the HAL_FDCAN_GetRxMessage function.

      (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering
          it to initialization mode and re-enabling access to configuration
          registers through the configuration functions listed here above.

      (#) All other control functions can be called any time after initialization
          phase, no matter if the FDCAN module is started or stoped.

      *** Polling mode operation ***
      ==============================

    [..]
        (#) Reception and transmission states can be monitored via the following
            functions:
              (++) HAL_FDCAN_IsRxBufferMessageAvailable
              (++) HAL_FDCAN_IsTxBufferMessagePending
              (++) HAL_FDCAN_GetRxFifoFillLevel
              (++) HAL_FDCAN_GetTxFifoFreeLevel

      *** Interrupt mode operation ***
      ================================
      [..]
        (#) There are two interrupt lines: line 0 and 1.
            By default, all interrupts are assigned to line 0. Interrupt lines
            can be configured using HAL_FDCAN_ConfigInterruptLines function.

        (#) Notifications are activated using HAL_FDCAN_ActivateNotification
            function. Then, the process can be controlled through one of the
            available user callbacks: HAL_FDCAN_xxxCallback.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_fdcan.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_flash.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Functions | Variables
stm32h7xx_hal_flash.c File Reference

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */

Functions

static void | FLASH_SetErrorCode (uint32_t Bank)
Set the specific FLASH error flag.
HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t FlashAddress, uint64_t DataAddress)
Program flash word of 256 bits at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t FlashAddress, uint64_t DataAddress)
Program flash words of 256 bits at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
This function handles FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.
HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control registers access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Locks the FLASH control registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.
uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout, uint32_t Bank)
Wait for a FLASH operation to complete.
HAL_StatusTypeDef | FLASH_OB_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH Option Bytes change operation to complete.

Variables

FLASH_ProcessTypeDef pFlash

Detailed Description

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                        ##### FLASH peripheral features #####
  ==============================================================================

  [..] The Flash memory interface manages CPU AXI I-Code and D-Code accesses
       to the Flash memory. It implements the erase and program Flash memory operations
       and the read and write protection mechanisms.

  [..] The FLASH main features are:
      (+) Flash memory read operations
      (+) Flash memory program/erase operations
      (+) Read / write protections
      (+) Option bytes programming
      (+) Error code correction (ECC) : Data in flash are 266-bits word
          (10 bits added per double word)

                        ##### How to use this driver #####
 ==============================================================================
    [..]
      This driver provides functions and macros to configure and program the FLASH
      memory of all STM32H7xx devices.

      (#) FLASH Memory IO Programming functions:
           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
                HAL_FLASH_Lock() functions
           (++) Program functions: double word only
           (++) There Two modes of programming :
            (+++) Polling mode using HAL_FLASH_Program() function
            (+++) Interrupt mode using HAL_FLASH_Program_IT() function

      (#) Interrupts and flags management functions :
           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
           (++) Callback functions are called when the flash operations are finished :
                HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
                HAL_FLASH_OperationErrorCallback()
           (++) Get error flag status by calling HAL_FLASH_GetError()

      (#) Option bytes management functions :
           (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
                HAL_FLASH_OB_Lock() functions
           (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function.
                In this case, a reset is generated
    [..]
      In addition to these functions, this driver includes a set of macros allowing
      to handle the following operations:
       (+) Set the latency
       (+) Enable/Disable the FLASH interrupts
       (+) Monitor the FLASH flags status
     [..]
    (@) For any Flash memory program operation (erase or program), the CPU clock frequency
        (HCLK) must be at least 1MHz.
    (@) The contents of the Flash memory are not guaranteed if a device reset occurs during
        a Flash memory operation.
    (@) Any attempt to read the Flash memory while it is being written or erased, causes the
        bus to stall. Read operations are processed correctly once the program operation has
        completed. This means that code or data fetches cannot be performed while a write/erase
        operation is ongoing
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_flash.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_flash_ex.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Functions | Variables
stm32h7xx_hal_flash_ex.c File Reference

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extension peripheral: + Extended programming operations functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | FLASH_TIMEOUT_VALUE 50000U/* 50 s */

Functions

static void | FLASH_MassErase (uint32_t VoltageRange, uint32_t Banks)
Full erase of FLASH memory sectors.
void | FLASH_Erase_Sector (uint32_t Sector, uint32_t Banks, uint32_t VoltageRange)
Erase the specified FLASH memory sector.
static HAL_StatusTypeDef | FLASH_OB_EnableWRP (uint32_t WRPSector, uint32_t Banks)
Enable the write protection of the desired bank1 or bank 2 sectors.
static HAL_StatusTypeDef | FLASH_OB_DisableWRP (uint32_t WRPSector, uint32_t Banks)
Disable the write protection of the desired bank1 or bank 2 sectors.
static void | FLASH_OB_GetWRP (uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank)
Get the write protection of the given bank1 or bank 2 sectors.
static HAL_StatusTypeDef | FLASH_OB_RDPConfig (uint32_t RDPLevel)
Set the read protection level.
static uint32_t | FLASH_OB_GetRDP (void)
Get the read protection level.
static HAL_StatusTypeDef | FLASH_OB_PCROPConfig (uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks)
Configure the Proprietary code readout protection of the desired addresses.
static void | FLASH_OB_GetPCROP (uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr, uint32_t Bank)
Get the Proprietary code readout protection configuration on a given Bank.
static HAL_StatusTypeDef | FLASH_OB_BOR_LevelConfig (uint8_t Level)
Set the BOR Level.
static uint32_t | FLASH_OB_GetBOR (void)
Get the BOR Level.
static HAL_StatusTypeDef | FLASH_OB_UserConfig (uint32_t UserType, uint32_t UserConfig)
Program the FLASH User Option Byte.
static uint32_t | FLASH_OB_GetUser (void)
Return the FLASH User Option Byte value.
static HAL_StatusTypeDef | FLASH_OB_BootAddConfig (uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1)
Set Boot address.
static void | FLASH_OB_GetBootAdd (uint32_t *BootAddress0, uint32_t *BootAddress1)
Get Boot address.
static HAL_StatusTypeDef | FLASH_OB_SecureAreaConfig (uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks)
Set secure area configuration.
static void | FLASH_OB_GetSecureArea (uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank)
Set secure area configuration.
HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
Perform a mass erase or erase the specified FLASH memory sectors.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option byte configuration.
HAL_StatusTypeDef | HAL_FLASHEx_Unlock_Bank1 (void)
Unlock the FLASH Bank1 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_Lock_Bank1 (void)
Locks the FLASH Bank1 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_Unlock_Bank2 (void)
Unlock the FLASH Bank2 control registers access.
HAL_StatusTypeDef | HAL_FLASHEx_Lock_Bank2 (void)
Locks the FLASH Bank2 control registers access.

Variables

FLASH_ProcessTypeDef pFlash

Detailed Description

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extension peripheral: + Extended programming operations functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
 ==============================================================================
                   ##### Flash Extension features #####
  ==============================================================================

  [..] Comparing to other previous devices, the FLASH interface for STM32H7xx
       devices contains the following additional features

       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
           capability (RWW)
       (+) Dual bank memory organization
       (+) PCROP protection for all banks

                        ##### How to use this driver #####
 ==============================================================================
  [..] This driver provides functions to configure and program the FLASH memory
       of all STM32H7xx devices. It includes
      (#) FLASH Memory Erase functions:
           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
                HAL_FLASH_Lock() functions
           (++) Erase function: Erase sector, erase all sectors
           (++) There are two modes of erase :
             (+++) Polling Mode using HAL_FLASHEx_Erase()
             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()

      (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
        (++) Set/Reset the write protection per bank
        (++) Set the Read protection Level
        (++) Set the BOR level
        (++) Program the user Option Bytes
        (++) PCROP protection configuration and control per bank
    (++) Secure area configuration and control per bank
    (++) Core Boot address configuration

   (#) FLASH Memory Lock and unlock per Bank: HAL_FLASHEx_Lock_Bank1 and HAL_FLASHEx_Unlock_Bank1 functions
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_flash_ex.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_gpio.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
  • Src
Defines | Functions
stm32h7xx_hal_gpio.c File Reference

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | GPIO_MODE ((uint32_t)0x00000003)
#define | ANALOG_MODE ((uint32_t)0x00000008)
#define | EXTI_MODE ((uint32_t)0x10000000)
#define | GPIO_MODE_IT ((uint32_t)0x00010000)
#define | GPIO_MODE_EVT ((uint32_t)0x00020000)
#define | RISING_EDGE ((uint32_t)0x00100000)
#define | FALLING_EDGE ((uint32_t)0x00200000)
#define | GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
#define | GPIO_NUMBER ((uint32_t)16)

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initializes the GPIOx peripheral registers to their default reset values.
GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Sets or clears the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggles the specified GPIO pins.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
Handle EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.

Detailed Description

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                    ##### GPIO Peripheral features #####
  ==============================================================================
  [..]
  Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
  port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
  in several modes:
  (+) Input mode
  (+) Analog mode
  (+) Output mode
  (+) Alternate function mode
  (+) External interrupt/event lines

  [..]
  During and just after reset, the alternate functions and external interrupt
        lines are not active and the I/O ports are configured in input floating mode.

  [..]
  All GPIO pins have weak internal pull-up and pull-down resistors, which can be
        activated or not.

  [..]
  In Output or Alternate mode, each IO can be configured on open-drain or push-pull
        type and the IO speed can be selected depending on the VDD value.

  [..]
  All ports have external interrupt/event capability. To use external interrupt
        lines, the port must be configured in input mode. All available GPIO pins are
        connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.

  [..]
  The external interrupt/event controller consists of up to 23 edge detectors
        (16 lines are connected to GPIO) for generating event/interrupt requests (each
        input line can be independently configured to select the type (interrupt or event)
        and the corresponding trigger event (rising or falling or both). Each line can
        also be masked independently.

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().

    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
             structure.
        (++) In case of Output or alternate function mode selection: the speed is
             configured through "Speed" member from GPIO_InitTypeDef structure.
        (++) In alternate mode is selection, the alternate function connected to the IO
             is configured through "Alternate" member from GPIO_InitTypeDef structure.
        (++) Analog mode is required when a pin is to be used as ADC channel
             or DAC output.
        (++) In case of external interrupt/event selection the "Mode" member from
             GPIO_InitTypeDef structure select the type (interrupt or event) and
             the corresponding trigger event (rising or falling or both).

    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
        HAL_NVIC_EnableIRQ().

    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().

    (#) To set/reset the level of a pin configured in output mode use
        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().

   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().

    (#) During and just after reset, the alternate functions are not
        active and the GPIO pins are configured in input floating mode (except JTAG
        pins).

    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
        priority over the GPIO function.

    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
        general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
        The HSE has priority over the GPIO function.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_gpio.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_hash.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_hash.c File Reference

HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral: + Initialization and de-initialization methods + HASH or HMAC processing in polling mode + HASH or HMAC processing in interrupt mode + HASH or HMAC processing in DMA mode + Peripheral State methods + HASH or HMAC processing suspension/resumption. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | HASH_DIGEST_CALCULATION_NOT_STARTED ((uint32_t)0x00000000)
#define | HASH_DIGEST_CALCULATION_STARTED ((uint32_t)0x00000001)
#define | HASH_NUMBER_OF_CSR_REGISTERS 54
#define | HASH_TIMEOUTVALUE 1000

Functions

static void | HASH_DMAXferCplt (DMA_HandleTypeDef *hdma)
DMA HASH Input Data transfer completion callback.
static void | HASH_DMAError (DMA_HandleTypeDef *hdma)
DMA HASH communication error callback.
static void | HASH_GetDigest (uint8_t *pMsgDigest, uint8_t Size)
Retrieve the message digest.
static HAL_StatusTypeDef | HASH_WaitOnFlagUntilTimeout (HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
Handle HASH processing Timeout.
static HAL_StatusTypeDef | HASH_WriteData (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Feed the input buffer to the HASH IP.
static HAL_StatusTypeDef | HASH_IT (HASH_HandleTypeDef *hhash)
HASH processing in interruption mode.
static uint32_t | HASH_Write_Block_Data (HASH_HandleTypeDef *hhash)
Write a block of data in HASH IP in interruption mode.
static HAL_StatusTypeDef | HMAC_Processing (HASH_HandleTypeDef *hhash, uint32_t Timeout)
HMAC processing in polling mode.
HAL_StatusTypeDef | HAL_HASH_Init (HASH_HandleTypeDef *hhash)
Initialize the HASH according to the specified parameters in the HASH_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_HASH_DeInit (HASH_HandleTypeDef *hhash)
DeInitialize the HASH peripheral.
__weak void | HAL_HASH_MspInit (HASH_HandleTypeDef *hhash)
Initialize the HASH MSP.
__weak void | HAL_HASH_MspDeInit (HASH_HandleTypeDef *hhash)
DeInitialize the HASH MSP.
__weak void | HAL_HASH_InCpltCallback (HASH_HandleTypeDef *hhash)
Input data transfer complete call back.
__weak void | HAL_HASH_DgstCpltCallback (HASH_HandleTypeDef *hhash)
Digest computation complete call back.
__weak void | HAL_HASH_ErrorCallback (HASH_HandleTypeDef *hhash)
Error callback.
HAL_StatusTypeDef | HAL_HASH_MD5_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in MD5 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASH_MD5_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in MD5 mode then processes pInBuffer.
HAL_StatusTypeDef | HAL_HASH_SHA1_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASH_SHA1_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in SHA1 mode then processes pInBuffer.
HAL_StatusTypeDef | HAL_HASH_MD5_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in MD5 mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HAL_HASH_SHA1_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then read the computed digest in interruption mode.
void | HAL_HASH_IRQHandler (HASH_HandleTypeDef *hhash)
Handle HASH interrupt request.
HAL_StatusTypeDef | HAL_HASH_MD5_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASH_MD5_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in MD5 mode.
HAL_StatusTypeDef | HAL_HASH_SHA1_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASH_SHA1_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in SHA1 mode.
HAL_StatusTypeDef | HAL_HMAC_MD5_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HMAC_SHA1_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HMAC_MD5_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then read the computed digest in interrupt mode.
HAL_StatusTypeDef | HAL_HMAC_SHA1_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then read the computed digest in interrupt mode.
HAL_StatusTypeDef | HAL_HMAC_MD5_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC MD5 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.
HAL_StatusTypeDef | HAL_HMAC_SHA1_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.
HAL_HASH_StateTypeDef | HAL_HASH_GetState (HASH_HandleTypeDef *hhash)
Return the HASH handle state.
HAL_StatusTypeDef | HAL_HASH_GetStatus (HASH_HandleTypeDef *hhash)
Return the HASH HAL status.
void | HAL_HASH_ContextSaving (HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
Save the HASH context in case of processing suspension.
void | HAL_HASH_ContextRestoring (HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
Restore the HASH context in case of processing resumption.
void | HAL_HASH_SwFeed_ProcessSuspend (HASH_HandleTypeDef *hhash)
Initiate HASH processing suspension when in polling or interruption mode.
HAL_StatusTypeDef | HAL_HASH_DMAFeed_ProcessSuspend (HASH_HandleTypeDef *hhash)
Suspend the HASH processing when in DMA mode.
HAL_StatusTypeDef | HASH_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
Initialize the HASH peripheral, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HASH_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
If not already done, initialize the HASH peripheral then processes pInBuffer.
HAL_StatusTypeDef | HASH_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm)
Initialize the HASH peripheral, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HASH_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
Initialize the HASH peripheral then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HASH_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest.
HAL_StatusTypeDef | HMAC_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
Initialize the HASH peripheral in HMAC mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HMAC_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm)
Initialize the HASH peripheral in HMAC mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HMAC_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
Initialize the HASH peripheral in HMAC mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.

Detailed Description

HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral: + Initialization and de-initialization methods + HASH or HMAC processing in polling mode + HASH or HMAC processing in interrupt mode + HASH or HMAC processing in DMA mode + Peripheral State methods + HASH or HMAC processing suspension/resumption.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
 ===============================================================================
                     ##### How to use this driver #####
 ===============================================================================
    [..]
    The HASH HAL driver can be used as follows:

    (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
        (##) Enable the HASH interface clock using __HASH_CLK_ENABLE()
        (##) When resorting to interrupt-based APIs (e.g. HAL_HASH_xxx_Start_IT())
            (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
            (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
            (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler() API
        (##) When resorting to DMA-based APIs  (e.g. HAL_HASH_xxx_Start_DMA())
            (+++) Enable the DMAx interface clock using
                   __DMAx_CLK_ENABLE()
            (+++) Configure and enable one DMA stream to manage data transfer from
                memory to peripheral (input stream). Managing data transfer from
                peripheral to memory can be performed only using CPU.
            (+++) Associate the initialized DMA handle to the HASH DMA handle
                using  __HAL_LINKDMA()
            (+++) Configure the priority and enable the NVIC for the transfer complete
                interrupt on the DMA Stream: use
                 HAL_NVIC_SetPriority() and
                 HAL_NVIC_EnableIRQ()

    (#)Initialize the HASH HAL using HAL_HASH_Init(). This function:
        (##) resorts to HAL_HASH_MspInit() for low-level initialization,
        (##) configures the data type: 1-bit, 8-bit, 16-bit or 32-bit.

    (#)Three processing schemes are available:
        (##) Polling mode: processing APIs are blocking functions
             i.e. they process the data and wait till the digest computation is finished,
             e.g. HAL_HASH_xxx_Start() for HASH or HAL_HMAC_xxx_Start() for HMAC
        (##) Interrupt mode: processing APIs are not blocking functions
                i.e. they process the data under interrupt,
                e.g. HAL_HASH_xxx_Start_IT() for HASH or HAL_HMAC_xxx_Start_IT() for HMAC
        (##) DMA mode: processing APIs are not blocking functions and the CPU is
             not used for data transfer i.e. the data transfer is ensured by DMA,
                e.g. HAL_HASH_xxx_Start_DMA() for HASH or HAL_HMAC_xxx_Start_DMA()
                for HMAC. Note that in DMA mode, a call to HAL_HASH_xxx_Finish()
                is then required to retrieve the digest.

    (#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is
       initialized and processes the buffer fed in input. When the input data have all been
       fed to the IP, the digest computation can start.

    (#)Multi-buffer processing is possible in polling and DMA mode.
        (##) In polling mode, only multi-buffer HASH processing is possible.
             API HAL_HASH_xxx_Accumulate() must be called for each input buffer, except for the last one.
             User must resort to HAL_HASH_xxx_Start() to enter the last one and retrieve as
             well the computed digest.

        (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.

              (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
             From that point, each buffer can be fed to the IP thru HAL_HASH_xxx_Start_DMA() API.
             Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
             macro then wrap-up the HASH processing in feeding the last input buffer thru the
             same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to
             API HAL_HASH_xxx_Finish().

             (+++) HMAC processing (requires to resort to extended functions):
             after initialization, the key and the first input buffer are entered
             in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
             starts step 2.
             The following buffers are next entered with the API  HAL_HMACEx_xxx_Step2_DMA(). At this
             point, the HMAC processing is still carrying out step 2.
             Then, step 2 for the last input buffer and step 3 are carried out by a single call
             to HAL_HMACEx_xxx_Step2_3_DMA().

             The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish().

    (#)Context swapping.
        (##) Two APIs are available to suspend HASH or HMAC processing:
             (+++) HAL_HASH_SwFeed_ProcessSuspend() when data are entered by software (polling or IT mode),
             (+++) HAL_HASH_DMAFeed_ProcessSuspend() when data are entered by DMA.

        (##) When HASH or HMAC processing is suspended, HAL_HASH_ContextSaving() allows
            to save in memory the IP context. This context can be restored afterwards
            to resume the HASH processing thanks to HAL_HASH_ContextRestoring().

        (##) Once the HASH IP has been restored to the same configuration as that at suspension
             time, processing can be restarted with the same API call (same API, same handle,
             same parameters) as done before the suspension. Relevant parameters to restart at
             the proper location are internally saved in the HASH handle.

    (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_hash.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_hash_ex.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32H7xx_HAL_Driver
  • Src
Functions
stm32h7xx_hal_hash_ex.c File Reference

Extended HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral for SHA-224 and SHA-256 alogrithms: + HASH or HMAC processing in polling mode + HASH or HMAC processing in interrupt mode + HASH or HMAC processing in DMA mode Additionally, this file provides functions to manage HMAC multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224 and SHA-256. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_HASHEx_SHA224_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASHEx_SHA224_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in SHA224 mode then processes pInBuffer.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Accumulate (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
If not already done, initialize the HASH peripheral in SHA256 mode then processes pInBuffer.
HAL_StatusTypeDef | HAL_HASHEx_SHA224_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then read the computed digest in interruption mode.
HAL_StatusTypeDef | HAL_HASHEx_SHA224_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASHEx_SHA224_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in SHA224 mode.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer to feed the input buffer to the IP.
HAL_StatusTypeDef | HAL_HASHEx_SHA256_Finish (HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
Return the computed digest in SHA256 mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Start (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout)
Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then read the computed digest.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then read the computed digest in interrupt mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Start_IT (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer)
Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then read the computed digest in interrupt mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Start_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required DMA transfers to feed the key and the input buffer to the IP.
HAL_StatusTypeDef | HAL_HMACEx_MD5_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_MD5_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
MD5 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_MD5_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA1_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA1_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA1 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA1_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA224 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA224_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Step1_2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Step2_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA256 HMAC step 2 in multi-buffer DMA mode.
HAL_StatusTypeDef | HAL_HMACEx_SHA256_Step2_3_DMA (HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.

Detailed Description

Extended HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral for SHA-224 and SHA-256 alogrithms: + HASH or HMAC processing in polling mode + HASH or HMAC processing in interrupt mode + HASH or HMAC processing in DMA mode Additionally, this file provides functions to manage HMAC multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224 and SHA-256.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
 ===============================================================================
                     ##### HASH peripheral extended features  #####
 ===============================================================================
    [..]
    The SHA-224 and SHA-256 HASH and HMAC processing can be carried out exactly
    the same way as for SHA-1 or MD-5 algorithms.
    (#) Three modes are available.
        (##) Polling mode: processing APIs are blocking functions
             i.e. they process the data and wait till the digest computation is finished,
             e.g. HAL_HASHEx_xxx_Start()
        (##) Interrupt mode: processing APIs are not blocking functions
                i.e. they process the data under interrupt,
                e.g. HAL_HASHEx_xxx_Start_IT()
        (##) DMA mode: processing APIs are not blocking functions and the CPU is
             not used for data transfer i.e. the data transfer is ensured by DMA,
                e.g. HAL_HASHEx_xxx_Start_DMA(). Note that in DMA mode, a call to
                HAL_HASHEx_xxx_Finish() is then required to retrieve the digest.

   (#)Multi-buffer processing is possible in polling and DMA mode.
        (##) In polling mode, only multi-buffer HASH processing is possible.
             API HAL_HASHEx_xxx_Accumulate() must be called for each input buffer, except for the last one.
             User must resort to HAL_HASHEx_xxx_Start() to enter the last one and retrieve as
             well the computed digest.

        (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.

              (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
             From that point, each buffer can be fed to the IP thru HAL_HASHEx_xxx_Start_DMA() API.
             Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
             macro then wrap-up the HASH processing in feeding the last input buffer thru the
             same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to
             API HAL_HASHEx_xxx_Finish().

             (+++) HMAC processing (MD-5, SHA-1, SHA-224 and SHA-256 must all resort to
             extended functions): after initialization, the key and the first input buffer are entered
             in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
             starts step 2.
             The following buffers are next entered with the API  HAL_HMACEx_xxx_Step2_DMA(). At this
             point, the HMAC processing is still carrying out step 2.
             Then, step 2 for the last input buffer and step 3 are carried out by a single call
             to HAL_HMACEx_xxx_Step2_3_DMA().

             The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish() for
             MD-5 and SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 and SHA-256.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_hash_ex.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_hcd.c File Reference

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Functions
stm32h7xx_hal_hcd.c File Reference

HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

static void | HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
This function handles Host Channel IN interrupt requests.
static void | HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
This function handles Host Channel OUT interrupt requests.
static void | HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
This function handles Rx Queue Level interrupt requests.
static void | HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
This function handles Host Port interrupt requests.
HAL_StatusTypeDef | HAL_HCD_Init (HCD_HandleTypeDef *hhcd)
Initialize the host driver.
HAL_StatusTypeDef | HAL_HCD_HC_Init (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
Initialize a host channel.
HAL_StatusTypeDef | HAL_HCD_HC_Halt (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
Halt a host channel.
HAL_StatusTypeDef | HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the host driver.
__weak void | HAL_HCD_MspInit (HCD_HandleTypeDef *hhcd)
Initializes the HCD MSP.
__weak void | HAL_HCD_MspDeInit (HCD_HandleTypeDef *hhcd)
DeInitializes HCD MSP.
HAL_StatusTypeDef | HAL_HCD_HC_SubmitRequest (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t direction, uint8_t ep_type, uint8_t token, uint8_t *pbuff, uint16_t length, uint8_t do_ping)
Submit a new URB for processing.
void | HAL_HCD_IRQHandler (HCD_HandleTypeDef *hhcd)
This function handles HCD interrupt request.
__weak void | HAL_HCD_SOF_Callback (HCD_HandleTypeDef *hhcd)
SOF callback.
__weak void | HAL_HCD_Connect_Callback (HCD_HandleTypeDef *hhcd)
Connexion Event callback.
__weak void | HAL_HCD_Disconnect_Callback (HCD_HandleTypeDef *hhcd)
Disconnexion Event callback.
__weak void | HAL_HCD_HC_NotifyURBChange_Callback (HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
Notify URB state change callback.
HAL_StatusTypeDef | HAL_HCD_Start (HCD_HandleTypeDef *hhcd)
Start the host driver.
HAL_StatusTypeDef | HAL_HCD_Stop (HCD_HandleTypeDef *hhcd)
Stop the host driver.
HAL_StatusTypeDef | HAL_HCD_ResetPort (HCD_HandleTypeDef *hhcd)
Reset the host port.
HCD_StateTypeDef | HAL_HCD_GetState (HCD_HandleTypeDef *hhcd)
Return the HCD state.
HCD_URBStateTypeDef | HAL_HCD_HC_GetURBState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return URB state for a channel.
uint32_t | HAL_HCD_HC_GetXferCount (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the last host transfer size.
HCD_HCStateTypeDef | HAL_HCD_HC_GetState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the Host Channel state.
uint32_t | HAL_HCD_GetCurrentFrame (HCD_HandleTypeDef *hhcd)
Return the current Host frame number.
uint32_t | HAL_HCD_GetCurrentSpeed (HCD_HandleTypeDef *hhcd)
Return the Host enumeration speed.

Detailed Description

HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
  [..]
    (#)Declare a HCD_HandleTypeDef handle structure, for example:
       HCD_HandleTypeDef  hhcd;

    (#)Fill parameters of Init structure in HCD handle

    (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)

    (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
        (##) Enable the HCD/USB Low Level interface clock using the following macros
             (+++) __OTGFS-OTG_CLK_ENABLE() or __OTGHS-OTG_CLK_ENABLE()
             (+++) __OTGHSULPI_CLK_ENABLE() For High Speed Mode

        (##) Initialize the related GPIO clocks
        (##) Configure HCD pin-out
        (##) Configure HCD NVIC interrupt

    (#)Associate the Upper USB Host stack to the HAL HCD Driver:
        (##) hhcd.pData = phost;

    (#)Enable HCD transmission and reception:
        (##) HAL_HCD_Start();
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_hcd.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_hrtim.c File Reference

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Defines | Functions | Variables
stm32h7xx_hal_hrtim.c File Reference

HRTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the High Resolution Timer (HRTIM) peripheral: + HRTIM Initialization + Timer Time Base Unit Configuration + Simple Time Base Start/Stop + Simple Time Base Start/Stop Interrupt + Simple Time Base Start/Stop DMA Request + Simple Output Compare/PWM Channel Configuration + Simple Output Compare/PWM Channel Start/Stop Interrupt + Simple Output Compare/PWM Channel Start/Stop DMA Request + Simple Input Capture Channel Configuration + Simple Input Capture Channel Start/Stop Interrupt + Simple Input Capture Channel Start/Stop DMA Request + Simple One Pulse Channel Configuration + Simple One Pulse Channel Start/Stop Interrupt + HRTIM External Synchronization Configuration + HRTIM Burst Mode Controller Configuration + HRTIM Burst Mode Controller Enabling + HRTIM External Events Conditioning Configuration + HRTIM Faults Conditioning Configuration + HRTIM Faults Enabling + HRTIM ADC trigger Configuration + Waveform Timer Configuration + Waveform Event Filtering Configuration + Waveform Dead Time Insertion Configuration + Waveform Chopper Mode Configuration + Waveform Compare Unit Configuration + Waveform Capture Unit Configuration + Waveform Output Configuration + Waveform Counter Start/Stop + Waveform Counter Start/Stop Interrupt + Waveform Counter Start/Stop DMA Request + Waveform Output Enabling + Waveform Output Level Set/Get + Waveform Output State Get + Waveform Burst DMA Operation Configuration + Waveform Burst DMA Operation Start + Waveform Timer Counter Software Reset + Waveform Capture Software Trigger + Waveform Burst Mode Controller Software Trigger + Waveform Timer Pre-loadable Registers Update Enabling + Waveform Timer Pre-loadable Registers Software Update + Waveform Timer Delayed Protection Status Get + Waveform Timer Burst Status Get + Waveform Timer Push-Pull Status Get + Peripheral State Get. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | HRTIM_FLTR_FLTxEN
#define | HRTIM_TIMCR_TIMUPDATETRIGGER

Functions

static void | HRTIM_MasterBase_Config (HRTIM_HandleTypeDef *hhrtim, HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg)
Configures the master timer time base.
static void | HRTIM_TimingUnitBase_Config (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg)
Configures timing unit (timer A to timer E) time base.
static void | HRTIM_MasterWaveform_Config (HRTIM_HandleTypeDef *hhrtim, HRTIM_TimerCfgTypeDef *pTimerCfg)
Configures the master timer in waveform mode.
static void | HRTIM_TimingUnitWaveform_Config (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, HRTIM_TimerCfgTypeDef *pTimerCfg)
Configures timing unit (timer A to timer E) in waveform mode.
static void | HRTIM_CompareUnitConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CompareUnit, HRTIM_CompareCfgTypeDef *pCompareCfg)
Configures a compare unit.
static void | HRTIM_CaptureUnitConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, uint32_t Event)
Configures a capture unit.
static void | HRTIM_OutputConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, HRTIM_OutputCfgTypeDef *pOutputCfg)
Configures the output of a timing unit.
static void | HRTIM_EventConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t Event, HRTIM_EventCfgTypeDef *pEventCfg)
Configures an external event channel.
static void | HRTIM_TIM_ResetConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event)
Configures the timer counter reset.
static uint32_t | HRTIM_GetITFromOCMode (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel)
Returns the interrupt to enable or disable according to the OC mode.
static uint32_t | HRTIM_GetDMAFromOCMode (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel)
Returns the DMA request to enable or disable according to the OC mode.
static DMA_HandleTypeDef * | HRTIM_GetDMAHandleFromTimerIdx (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
static uint32_t | GetTimerIdxFromDMAHandle (DMA_HandleTypeDef *hdma)
static void | HRTIM_ForceRegistersUpdate (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Forces an immediate transfer from the preload to the active registers.
static void | HRTIM_HRTIM_ISR (HRTIM_HandleTypeDef *hhrtim)
HRTIM interrupts service routine.
static void | HRTIM_Master_ISR (HRTIM_HandleTypeDef *hhrtim)
Master timer interrupts service routine.
static void | HRTIM_Timer_ISR (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Timer interrupts service routine.
static void | HRTIM_DMAMasterCplt (DMA_HandleTypeDef *hdma)
DMA callback invoked upon master timer related DMA request completion.
static void | HRTIM_DMATimerxCplt (DMA_HandleTypeDef *hdma)
DMA callback invoked upon timer A..E related DMA request completion.
static void | HRTIM_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
static void | HRTIM_BurstDMACplt (DMA_HandleTypeDef *hdma)
DMA callback invoked upon burst DMA transfer completion.
HAL_StatusTypeDef | HAL_HRTIM_Init (HRTIM_HandleTypeDef *hhrtim)
Initializes a HRTIM instance.
HAL_StatusTypeDef | HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim)
De-initializes a HRTIM instance.
__weak void | HAL_HRTIM_MspInit (HRTIM_HandleTypeDef *hhrtim)
MSP initialization for a HRTIM instance.
__weak void | HAL_HRTIM_MspDeInit (HRTIM_HandleTypeDef *hhrtim)
MSP initialization for a for a HRTIM instance.
HAL_StatusTypeDef | HAL_HRTIM_TimeBaseConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg)
Configures the time base unit of a timer.
HAL_StatusTypeDef | HAL_HRTIM_SimpleBaseStart (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Starts the counter of a timer operating in basic time base mode.
HAL_StatusTypeDef | HAL_HRTIM_SimpleBaseStop (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Stops the counter of a timer operating in basic time base mode.
HAL_StatusTypeDef | HAL_HRTIM_SimpleBaseStart_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Starts the counter of a timer operating in simple time base mode (Timer repetition interrupt is enabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleBaseStop_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Stops the counter of a timer operating in simple time base mode (Timer repetition interrupt is disabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleBaseStart_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t SrcAddr, uint32_t DestAddr, uint32_t Length)
Starts the counter of a timer operating in simple time base mode (Timer repetition DMA request is enabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleBaseStop_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Stops the counter of a timer operating in simple time base mode (Timer repetition DMA request is disabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleOCChannelConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel, HRTIM_SimpleOCChannelCfgTypeDef *pSimpleOCChannelCfg)
Configures an output in simple output compare mode.
HAL_StatusTypeDef | HAL_HRTIM_SimpleOCStart (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel)
Starts the output compare signal generation on the designed timer output.
HAL_StatusTypeDef | HAL_HRTIM_SimpleOCStop (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel)
Stops the output compare signal generation on the designed timer output.
HAL_StatusTypeDef | HAL_HRTIM_SimpleOCStart_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel)
Starts the output compare signal generation on the designed timer output (Interrupt is enabled (see note note below)).
HAL_StatusTypeDef | HAL_HRTIM_SimpleOCStop_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel)
Stops the output compare signal generation on the designed timer output (Interrupt is disabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleOCStart_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel, uint32_t SrcAddr, uint32_t DestAddr, uint32_t Length)
Starts the output compare signal generation on the designed timer output (DMA request is enabled (see note below)).
HAL_StatusTypeDef | HAL_HRTIM_SimpleOCStop_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel)
Stops the output compare signal generation on the designed timer output (DMA request is disabled).
HAL_StatusTypeDef | HAL_HRTIM_SimplePWMChannelConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel, HRTIM_SimplePWMChannelCfgTypeDef *pSimplePWMChannelCfg)
Configures an output in simple PWM mode.
HAL_StatusTypeDef | HAL_HRTIM_SimplePWMStart (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel)
Starts the PWM output signal generation on the designed timer output.
HAL_StatusTypeDef | HAL_HRTIM_SimplePWMStop (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel)
Stops the PWM output signal generation on the designed timer output.
HAL_StatusTypeDef | HAL_HRTIM_SimplePWMStart_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel)
Starts the PWM output signal generation on the designed timer output (The compare interrupt is enabled).
HAL_StatusTypeDef | HAL_HRTIM_SimplePWMStop_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel)
Stops the PWM output signal generation on the designed timer output (The compare interrupt is disabled).
HAL_StatusTypeDef | HAL_HRTIM_SimplePWMStart_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel, uint32_t SrcAddr, uint32_t DestAddr, uint32_t Length)
Starts the PWM output signal generation on the designed timer output (The compare DMA request is enabled).
HAL_StatusTypeDef | HAL_HRTIM_SimplePWMStop_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel)
Stops the PWM output signal generation on the designed timer output (The compare DMA request is disabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleCaptureChannelConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel, HRTIM_SimpleCaptureChannelCfgTypeDef *pSimpleCaptureChannelCfg)
Configures a simple capture.
HAL_StatusTypeDef | HAL_HRTIM_SimpleCaptureStart (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel)
Enables a simple capture on the designed capture unit.
HAL_StatusTypeDef | HAL_HRTIM_SimpleCaptureStop (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel)
Disables a simple capture on the designed capture unit.
HAL_StatusTypeDef | HAL_HRTIM_SimpleCaptureStart_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel)
Enables a basic capture on the designed capture unit (Capture interrupt is enabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleCaptureStop_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel)
Disables a basic capture on the designed capture unit (Capture interrupt is disabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleCaptureStart_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel, uint32_t SrcAddr, uint32_t DestAddr, uint32_t Length)
Enables a basic capture on the designed capture unit (Capture DMA request is enabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleCaptureStop_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel)
Disables a basic capture on the designed capture unit (Capture DMA request is disabled).
HAL_StatusTypeDef | HAL_HRTIM_SimpleOnePulseChannelConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel, HRTIM_SimpleOnePulseChannelCfgTypeDef *pSimpleOnePulseChannelCfg)
Configures an output simple one pulse mode.
HAL_StatusTypeDef | HAL_HRTIM_SimpleOnePulseStart (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel)
Enables the simple one pulse signal generation on the designed output.
HAL_StatusTypeDef | HAL_HRTIM_SimpleOnePulseStop (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel)
Disables the simple one pulse signal generation on the designed output.
HAL_StatusTypeDef | HAL_HRTIM_SimpleOnePulseStart_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel)
Enables the simple one pulse signal generation on the designed output (The compare interrupt is enabled (pulse start)).
HAL_StatusTypeDef | HAL_HRTIM_SimpleOnePulseStop_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel)
Disables the simple one pulse signal generation on the designed output (The compare interrupt is disabled).
HAL_StatusTypeDef | HAL_HRTIM_BurstModeConfig (HRTIM_HandleTypeDef *hhrtim, HRTIM_BurstModeCfgTypeDef *pBurstModeCfg)
Configures the burst mode feature of the HRTIM.
HAL_StatusTypeDef | HAL_HRTIM_EventConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t Event, HRTIM_EventCfgTypeDef *pEventCfg)
Configures the conditioning of an external event.
HAL_StatusTypeDef | HAL_HRTIM_EventPrescalerConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler)
Configures the external event conditioning block prescaler.
HAL_StatusTypeDef | HAL_HRTIM_FaultConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t Fault, HRTIM_FaultCfgTypeDef *pFaultCfg)
Configures the conditioning of fault input.
HAL_StatusTypeDef | HAL_HRTIM_FaultPrescalerConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler)
Configures the fault conditioning block prescaler.
void | HAL_HRTIM_FaultModeCtl (HRTIM_HandleTypeDef *hhrtim, uint32_t Faults, uint32_t Enable)
Enables or disables the HRTIMx Fault mode.
HAL_StatusTypeDef | HAL_HRTIM_ADCTriggerConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t ADCTrigger, HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg)
Configures both the ADC trigger register update source and the ADC trigger source.
HAL_StatusTypeDef | HAL_HRTIM_WaveformTimerConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, HRTIM_TimerCfgTypeDef *pTimerCfg)
Configures the general behavior of a timer operating in waveform mode.
HAL_StatusTypeDef | HAL_HRTIM_TimerEventFilteringConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event, HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg)
Configures the event filtering capabilities of a timer (blanking, windowing)
HAL_StatusTypeDef | HAL_HRTIM_DeadTimeConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg)
Configures the deadtime insertion feature for a timer.
HAL_StatusTypeDef | HAL_HRTIM_ChopperModeConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg)
Configures the chopper mode feature for a timer.
HAL_StatusTypeDef | HAL_HRTIM_BurstDMAConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t RegistersToUpdate)
Configures the burst DMA controller for a timer.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCompareConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CompareUnit, HRTIM_CompareCfgTypeDef *pCompareCfg)
Configures the compare unit of a timer operating in waveform mode.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCaptureConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, HRTIM_CaptureCfgTypeDef *pCaptureCfg)
Configures the capture unit of a timer operating in waveform mode.
HAL_StatusTypeDef | HAL_HRTIM_WaveformOutputConfig (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, HRTIM_OutputCfgTypeDef *pOutputCfg)
Configures the output of a timer operating in waveform mode.
HAL_StatusTypeDef | HAL_HRTIM_WaveformSetOutputLevel (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, uint32_t OutputLevel)
Forces the timer output to its active or inactive state.
HAL_StatusTypeDef | HAL_HRTIM_WaveformOutputStart (HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStart)
Enables the generation of the waveform signal on the designated output(s) Outputs can be combined (ORed) to allow for simultaneous output enabling.
HAL_StatusTypeDef | HAL_HRTIM_WaveformOutputStop (HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStop)
Disables the generation of the waveform signal on the designated output(s) Outputs can be combined (ORed) to allow for simultaneous output disabling.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCounterStart (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Starts the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter start.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCounterStop (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Stops the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter stop.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCounterStart_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Starts the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter start.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCounterStop_IT (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Stops the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter stop.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCounterStart_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Starts the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter start.
HAL_StatusTypeDef | HAL_HRTIM_WaveformCounterStop_DMA (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Stops the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter stop.
HAL_StatusTypeDef | HAL_HRTIM_BurstModeCtl (HRTIM_HandleTypeDef *hhrtim, uint32_t Enable)
Enables or disables the HRTIM burst mode controller.
HAL_StatusTypeDef | HAL_HRTIM_BurstModeSoftwareTrigger (HRTIM_HandleTypeDef *hhrtim)
Triggers the burst mode operation.
HAL_StatusTypeDef | HAL_HRTIM_SoftwareCapture (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit)
Triggers a software capture on the designed capture unit.
HAL_StatusTypeDef | HAL_HRTIM_SoftwareUpdate (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Triggers the update of the registers of one or several timers.
HAL_StatusTypeDef | HAL_HRTIM_SoftwareReset (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Triggers the reset of one or several timers.
HAL_StatusTypeDef | HAL_HRTIM_BurstDMATransfer (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t BurstBufferAddress, uint32_t BurstBufferLength)
Starts a burst DMA operation to update HRTIM control registers content.
HAL_StatusTypeDef | HAL_HRTIM_UpdateEnable (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Enables the transfer from preload to active registers for one or several timing units (including master timer).
HAL_StatusTypeDef | HAL_HRTIM_UpdateDisable (HRTIM_HandleTypeDef *hhrtim, uint32_t Timers)
Disables the transfer from preload to active registers for one or several timing units (including master timer).
HAL_HRTIM_StateTypeDef | HAL_HRTIM_GetState (HRTIM_HandleTypeDef *hhrtim)
return the HRTIM HAL state
uint32_t | HAL_HRTIM_GetCapturedValue (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit)
Returns actual value of the capture register of the designated capture unit.
uint32_t | HAL_HRTIM_WaveformGetOutputLevel (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output)
Returns actual level (active or inactive) of the designated output.
uint32_t | HAL_HRTIM_WaveformGetOutputState (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output)
Returns actual state (RUN, IDLE, FAULT) of the designated output.
uint32_t | HAL_HRTIM_GetDelayedProtectionStatus (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output)
Returns the level (active or inactive) of the designated output when the delayed protection was triggered.
uint32_t | HAL_HRTIM_GetBurstStatus (HRTIM_HandleTypeDef *hhrtim)
Returns the actual status (active or inactive) of the burst mode controller.
uint32_t | HAL_HRTIM_GetCurrentPushPullStatus (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Indicates on which output the signal is currently active (when the push pull mode is enabled).
uint32_t | HAL_HRTIM_GetIdlePushPullStatus (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Indicates on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered.
void | HAL_HRTIM_IRQHandler (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
This function handles HRTIM interrupt request.
__weak void | HAL_HRTIM_Fault1Callback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a fault 1 interrupt occured.
__weak void | HAL_HRTIM_Fault2Callback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a fault 2 interrupt occured.
__weak void | HAL_HRTIM_Fault3Callback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a fault 3 interrupt occured.
__weak void | HAL_HRTIM_Fault4Callback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a fault 4 interrupt occured.
__weak void | HAL_HRTIM_Fault5Callback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a fault 5 interrupt occured.
__weak void | HAL_HRTIM_SystemFaultCallback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a system fault interrupt occured.
__weak void | HAL_HRTIM_BurstModePeriodCallback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when the end of the burst mode period is reached.
__weak void | HAL_HRTIM_SynchronizationEventCallback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a synchronization input event is received.
__weak void | HAL_HRTIM_RegistersUpdateCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when timer registers are updated.
__weak void | HAL_HRTIM_RepetitionEventCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when timer repetition period has elapsed.
__weak void | HAL_HRTIM_Compare1EventCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer counter matches the value programmed in the compare 1 register.
__weak void | HAL_HRTIM_Compare2EventCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer counter matches the value programmed in the compare 2 register.
__weak void | HAL_HRTIM_Compare3EventCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer counter matches the value programmed in the compare 3 register.
__weak void | HAL_HRTIM_Compare4EventCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer counter matches the value programmed in the compare 4 register.
__weak void | HAL_HRTIM_Capture1EventCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer x capture 1 event occurs.
__weak void | HAL_HRTIM_Capture2EventCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer x capture 2 event occurs.
__weak void | HAL_HRTIM_DelayedProtectionCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the delayed idle or balanced idle mode is entered.
__weak void | HAL_HRTIM_CounterResetCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer x counter reset/roll-over event occurs.
__weak void | HAL_HRTIM_Output1SetCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer x output 1 is set.
__weak void | HAL_HRTIM_Output1ResetCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer x output 1 is reset.
__weak void | HAL_HRTIM_Output2SetCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer x output 2 is set.
__weak void | HAL_HRTIM_Output2ResetCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when the timer x output 2 is reset.
__weak void | HAL_HRTIM_BurstDMATransferCallback (HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx)
Callback function invoked when a DMA burst transfer is completed.
__weak void | HAL_HRTIM_ErrorCallback (HRTIM_HandleTypeDef *hhrtim)
Callback function invoked when a DMA error occurs.

Variables

static uint32_t | TimerIdxToTimerId []

Detailed Description

HRTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the High Resolution Timer (HRTIM) peripheral: + HRTIM Initialization + Timer Time Base Unit Configuration + Simple Time Base Start/Stop + Simple Time Base Start/Stop Interrupt + Simple Time Base Start/Stop DMA Request + Simple Output Compare/PWM Channel Configuration + Simple Output Compare/PWM Channel Start/Stop Interrupt + Simple Output Compare/PWM Channel Start/Stop DMA Request + Simple Input Capture Channel Configuration + Simple Input Capture Channel Start/Stop Interrupt + Simple Input Capture Channel Start/Stop DMA Request + Simple One Pulse Channel Configuration + Simple One Pulse Channel Start/Stop Interrupt + HRTIM External Synchronization Configuration + HRTIM Burst Mode Controller Configuration + HRTIM Burst Mode Controller Enabling + HRTIM External Events Conditioning Configuration + HRTIM Faults Conditioning Configuration + HRTIM Faults Enabling + HRTIM ADC trigger Configuration + Waveform Timer Configuration + Waveform Event Filtering Configuration + Waveform Dead Time Insertion Configuration + Waveform Chopper Mode Configuration + Waveform Compare Unit Configuration + Waveform Capture Unit Configuration + Waveform Output Configuration + Waveform Counter Start/Stop + Waveform Counter Start/Stop Interrupt + Waveform Counter Start/Stop DMA Request + Waveform Output Enabling + Waveform Output Level Set/Get + Waveform Output State Get + Waveform Burst DMA Operation Configuration + Waveform Burst DMA Operation Start + Waveform Timer Counter Software Reset + Waveform Capture Software Trigger + Waveform Burst Mode Controller Software Trigger + Waveform Timer Pre-loadable Registers Update Enabling + Waveform Timer Pre-loadable Registers Software Update + Waveform Timer Delayed Protection Status Get + Waveform Timer Burst Status Get + Waveform Timer Push-Pull Status Get + Peripheral State Get.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                      ##### Simple mode v.s. waveform mode #####
==============================================================================
  [..] The HRTIM HAL API is split into 2 categories:
    (#)Simple functions: these functions allow for using a HRTIM timer as a
        general purpose timer with high resolution capabilities.
       Following simple modes are proposed:
         (+)Output compare mode
         (+)PWM output mode
         (+)Input capture mode
         (+)One pulse mode
       HRTIM simple modes are managed through the set of functions named
       HAL_HRTIM_Simple<Function>. These functions are similar in name and usage
       to the one defined for the TIM peripheral. When a HRTIM timer operates in
       simple mode, only a very limited set of HRTIM features are used.
    (#)Waveform functions: These functions allow taking advantage of the HRTIM
       flexibility to produce numerous types of control signal. When a HRTIM timer
       operates in waveform mode, all the HRTIM features are accessible without
       any restriction.  HRTIM waveform modes are managed through the set of
       functions named HAL_HRTIM_Waveform<Function>

==============================================================================
                      ##### How to use this driver #####
==============================================================================
    [..]
     (#)Initialize the HRTIM low level resources by implementing the
        HAL_HRTIM_MspInit() function:
        (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
        (##)Connect HRTIM pins to MCU I/Os
            (+++) Enable the clock for the HRTIM GPIOs using the following
                  function: __GPIOx_CLK_ENABLE()
            (+++) Configure these GPIO pins in Alternate Function mode using
                  HAL_GPIO_Init()
        (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
            (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
            (+++)Initialize the DMA handle
            (+++)Associate the initialized DMA handle to the appropriate DMA
                 handle of the HRTIM handle using  __HAL_LINKDMA()
            (+++)Initialize the DMA channel using HAL_DMA_Init()
            (+++)Configure the priority and enable the NVIC for the transfer
                 complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
                 and HAL_NVIC_EnableIRQ()
        (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
            (+++)Configure the priority and enable the NVIC for the concerned
                 HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()

    (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
       structure (field of the HRTIM handle) specifies which global interrupt of
       whole HRTIM must be enabled (Burst mode period, System fault, Faults).
       It also contains the HRTIM external synchronization configuration. HRTIM
       can act as a master (generating a synchronization signal) or as a slave
       (waiting for a trigger to be synchronized).

     (#) Configure HRTIM resources shared by all HRTIM timers
        (##)Burst Mode Controller:
                (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
                     controller: operating mode (continuous or -shot mode), clock
                     (source, prescaler) , trigger(s), period, idle duration.
        (##)External Events Conditionning:
                (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
                     external event channel: source, polarity, edge-sensitivity.
                     External event can be used as triggers (timer reset, input
                     capture, burst mode, ADC triggers, delayed protection, …)
                     They can also be used to set or reset timer outputs. Up to
                     10 event channels are available.
                (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
                     event sampling clock (used for digital filtering).
        (##)Fault Conditionning:
                (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
                     fault channel: source, polarity, edge-sensitivity.  Fault
                     channels are used to disable the outputs in case of an
                     abnormal operation. Up to 5 fault channels are available.
                (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
                     sampling clock (used for digital filtering).
                (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
                     circuitry. By default all fault inputs are disabled.
        (##)ADC trigger:
                (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
                     the update of the ADC trigger register and the ADC trigger.
                     4 independent triggers are available to start both the regular
                     and the injected sequencers of the 2 ADCs

     (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
         function must be called whatever the HRTIM timer operating mode is
         (simple v.s. waveform). It  configures mainly:
        (##)The HRTIM  timer counter operating mode (continuous, one shot)
        (##)The HRTIM  timer clock prescaler
        (##)The HRTIM  timer period
        (##)The HRTIM  timer repetition counter

     (#) If the HRTIM timer operates in simple mode:
        (##)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
                  HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
                  HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
        (##)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
                  HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
                  HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
                  HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
        (##)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
                  HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
                  HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
                  HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
        (##)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
                  HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
                  HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
                  HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
        (##)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
                  HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
                  HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().

     (#) If the HRTIM timer operates in waveform mode:
        (##)Completes waveform timer configuration
                (+++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM
                     timer operating in wave form mode mainly consists in:
                        - Enabling the HRTIM timer interrupts and DMA requests,
                        - Enabling the half mode for the HRTIM timer,
                        - Defining how the HRTIM timer reacts to external
                          synchronization input,
                        - Enabling the push-pull mode for the HRTIM timer,
                        - Enabling the fault channels for the HRTIM timer,
                        - Enabling the deadtime insertion for the HRTIM timer,
                        - Setting the delayed protection mode for the HRTIM timer
                          (source and outputs on which the delayed protection are applied),
                        - Specifying the HRTIM timer update and reset triggers,
                        - Specifying the HRTIM timer registers update policy (preload enabling, …).
                (+++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
                     event blanking and windowingcircuitry of a HRTIM timer:
                        - Blanking:  to mask external events during a defined
                          time period
                        - Windowing:  to enable external events only during
                          a defined time period
                (+++)HAL_HRTIM_DeadTimeConfig(): configures the deadtime insertion
                     unit for a HRTIM timer. Allows to generate a couple of
                     complementary signals from a single reference waveform,
                     with programmable delays between active state.
                (+++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
                     the high-frequency carrier signal added on top of the timing
                     unit output. Chopper mode can be enabled or disabled for each
                     timer output separately (see  HAL_HRTIM_WaveformOutputConfig()).
                (+++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
                     controller. Allows having multiple HRTIM registers updated
                     with a single DMA request. The burst DMA operation is started
                     by calling HAL_HRTIM_BurstDMATransfer().
                (+++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
                     of a HRTIM timer. This operation consists in setting the
                     compare value and possibly specifying the auto delayed mode
                     for compare units 2 and 4 (allows to have compare events
                     generated relatively to capture events). Note that when auto
                     delayed mode is needed, the capture unit associated to the
                     compare unit must be configured separately.
                (+++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
                     of a HRTIM timer. This operation consists in specifying the
                     source(s)  triggering the capture (timer register update event,
                     external event, timer output set/reset event, other HRTIM
                     timer related events).
                (+++)HAL_HRTIM_WaveformOutputConfig(): configuration HRTIM timer
                     output manly consists in:
                        - Setting the output polarity (active high or active low),
                        - Defining the set/reset crossbar for the output,
                        - Specifying the fault level (active or inactive) in IDLE
                          and FAULT states.,
        (##)Set waveform timer output(s) level
                (+++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
                     active or inactive level. For example, when deadtime insertion
                     is enabled it is necessary to force the output level by software
                     to have the outputs in a complementary state as soon as the RUN mode is entered.
        (##)Enable/Disable waveform timer output(s)
                (+++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().
        (##)Start/Stop waveform HRTIM timer(s).
                (+++)HAL_HRTIM_WaveformCounterStart(),HAL_HRTIM_WaveformCounterStop(),
                (+++)HAL_HRTIM_WaveformCounterStart_IT(),HAL_HRTIM_WaveformCounterStop_IT(),
                (+++)HAL_HRTIM_WaveformCounterStart()_DMA,HAL_HRTIM_WaveformCounterStop_DMA(),

        (##)Burst mode controller enabling:
                (+++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
                     burst mode controller.

        (##)Some HRTIM operations can be triggered by software:
                (+++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
                     trigs the burst operation.
                (+++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
                     capture of the HRTIM timer counter.
                (+++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
                     update of the pre-loadable registers of the HRTIM timer ()
                (+++)HAL_HRTIM_SoftwareReset():calling this function resets the
                     HRTIM timer counter.

        (##)Some functions can be used anytime to retrieve HRTIM timer related
            information
                (+++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
                     capture register of the designated capture unit.
                (+++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
                     (ACTIVE/INACTIVE) of the designated timer output.
                (+++)HAL_HRTIM_WaveformGetOutputState():returns actual state
                     (IDLE/RUN/FAULT) of the designated timer output.
                (+++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
                     (ACTIVE/INACTIVE) of the designated output when the delayed
                      protection was triggered.
                (+++)HAL_HRTIM_GetBurstStatus(): returns the actual status
                     (ACTIVE/INACTIVE) of the burst mode controller.
                (+++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
                     is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
                     the push-pull indicates on which output the signal is currently
                     active (e.g signal applied on output 1 and output 2 forced
                     inactive or vice versa).
                (+++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
                     is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
                     the idle push-pull  status indicates during which period the
                     delayed protection request occurred (e.g. protection occurred
                     when the output 1 was active and output 2 forced inactive or
                     vice versa).

        (##)Some functions can be used anytime to retrieve actual HRTIM status
                (+++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_hrtim.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_hsem.c File Reference

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Functions
stm32h7xx_hal_hsem.c File Reference

HSEM HAL module driver. This file provides firmware functions to manage the following functionalities of the semaphore peripheral: + Semaphore Take function (2-Step Procedure) , non blocking + Semaphore FastTake function (1-Step Procedure) , non blocking + Semaphore Status check + Semaphore Clear Key Set and Get + Release and release all functions + Semaphore notification enabling and disabling and callnack functions + IRQ handler management. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_HSEM_Take (uint32_t SemID, uint32_t ProcessID)
Take a semaphore in 2 Step mode.
HAL_StatusTypeDef | HAL_HSEM_FastTake (uint32_t SemID)
Fast Take a semaphore with 1 Step mode.
uint32_t | HAL_HSEM_IsSemTaken (uint32_t SemID)
Check semaphore state Taken or not.
void | HAL_HSEM_Release (uint32_t SemID, uint32_t ProcessID)
Release a semaphore.
void | HAL_HSEM_ReleaseAll (uint32_t Key, uint32_t MasterID)
Release All semaphore used by a given Master .
void | HAL_HSEM_SetClearKey (uint32_t Key)
Set semaphore Key .
uint32_t | HAL_HSEM_GetClearKey (void)
Get semaphore Key .
void | HAL_HSEM_ActivateNotification (uint32_t SemMask)
Activate Semaphore release Notification for a given Semaphores Mask .
void | HAL_HSEM_DeactivateNotification (uint32_t SemMask)
Deactivate Semaphore release Notification for a given Semaphores Mask .
void | HAL_HSEM_IRQHandler (void)
This function handles HSEM interrupt request.
__weak void | HAL_HSEM_FreeCallback (uint32_t SemMask)
Semaphore Released Callback.

Detailed Description

HSEM HAL module driver. This file provides firmware functions to manage the following functionalities of the semaphore peripheral: + Semaphore Take function (2-Step Procedure) , non blocking + Semaphore FastTake function (1-Step Procedure) , non blocking + Semaphore Status check + Semaphore Clear Key Set and Get + Release and release all functions + Semaphore notification enabling and disabling and callnack functions + IRQ handler management.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
  [..]
      (#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters :
           (++) the semaphore ID from 0 to 31
           (++) the process ID from 0 to 255
      (#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter :
           (++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero
      (#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter :
          (++) the semaphore ID from 0_ID to 31
          (++) It returns 1 if the given semaphore is taken otherwise (Free) zero.
      (#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters :
           (++) the semaphore ID from 0 to 31
           (++) the process ID from 0 to 255:
           (++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt
         may be generated when enabled (notification activated). If ProcessID or MasterID does not match,
         semaphore remains taken (locked).

      (#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All
          This function takes as parameters :
           (++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by
              HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions
           (++) the Master ID:
           (++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds
           to MasterID  will be freed, and an interrupt may be generated when enabled (notification activated). If the
           Key or the MasterID doesn't match, semaphores remains taken (locked).

      (#)Semaphores Release all key functions:
         (++)  HAL_HSEM_SetClearKey() to set semaphore release all Key
         (++)  HAL_HSEM_GetClearKey() to get release all Key
      (#)Semaphores notification functions :
         (++)  HAL_HSEM_ActivateNotification to activate a notification callback on
               a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released
               the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released
               semaphores (bitfield).

         (++)  HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield).
         (++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask
                Used by the notification functions
     *** HSEM HAL driver macros list ***
     =============================================
     [..] Below the list of most used macros in HSEM HAL driver.

      (+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask.
      [..] Example of use :
      [..] mask = __HAL_HSEM_SEMID_TO_MASK(8)  |  __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25).
      [..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using  __HAL_HSEM_SEMID_TO_MASK as the above example.
      (+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts.
      (+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts.
      (+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not.
      (+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags.
      (+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

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Definition in file stm32h7xx_hal_hsem.c.

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STM32H753xx HAL User Manual: stm32h7xx_hal_i2c.c File Reference

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Defines | Functions
stm32h7xx_hal_i2c.c File Reference

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFFU)
#define | I2C_TIMEOUT_ADDR ((uint32_t)10000U)
#define | I2C_TIMEOUT_BUSY ((uint32_t)25U)
#define | I2C_TIMEOUT_DIR ((uint32_t)25U)
#define | I2C_TIMEOUT_RXNE ((uint32_t)25U)
#define | I2C_TIMEOUT_STOPF ((uint32_t)25U)
#define | I2C_TIMEOUT_TC ((uint32_t)25U)
#define | I2C_TIMEOUT_TCR ((uint32_t)25U)
#define | I2C_TIMEOUT_TXIS ((uint32_t)25U)
#define | I2C_TIMEOUT_FLAG ((uint32_t)25U)
#define | MAX_NBYTE_SIZE 255U
#define | SlaveAddr_SHIFT 7U
#define | SlaveAddr_MSK 0x06U
#define | I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~HAL_I2C_STATE_READY)))
#define | I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
#define | I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))
#define | I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))
#define | I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))
#define | I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))
#define | I2C_XFER_TX_IT ((uint32_t)0x00000001U)
#define | I2C_XFER_RX_IT ((uint32_t)0x00000002U)
#define | I2C_XFER_LISTEN_IT ((uint32_t)0x00000004U)
#define | I2C_XFER_ERROR_IT ((uint32_t)0x00000011U)
#define | I2C_XFER_CPLT_IT ((uint32_t)0x00000012U)
#define | I2C_XFER_RELOAD_IT ((uint32_t)0x00000012U)
#define | I2C_GET_DMA_REMAIN_DATA(__HANDLE__)

Functions

static void | I2C_DMAMasterTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C master transmit process complete callback.
static void | I2C_DMAMasterReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C master receive process complete callback.
static void | I2C_DMASlaveTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave transmit process complete callback.
static void | I2C_DMASlaveReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave receive process complete callback.
static void | I2C_DMAError (DMA_HandleTypeDef *hdma)
DMA I2C communication error callback.
static void | I2C_DMAAbort (DMA_HandleTypeDef *hdma)
DMA I2C communication abort callback (To be called at end of DMA Abort procedure).
static void | I2C_ITAddrCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Address complete process callback.
static void | I2C_ITMasterSequentialCplt (I2C_HandleTypeDef *hi2c)
I2C Master sequential complete process.
static void | I2C_ITSlaveSequentialCplt (I2C_HandleTypeDef *hi2c)
I2C Slave sequential complete process.
static void | I2C_ITMasterCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Master complete process.
static void | I2C_ITSlaveCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Slave complete process.
static void | I2C_ITListenCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Listen complete process.
static void | I2C_ITError (I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
I2C interrupts error process.
static HAL_StatusTypeDef | I2C_RequestMemoryWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | I2C_RequestMemoryRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for read request.
static HAL_StatusTypeDef | I2C_Master_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Slave_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Master_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
static HAL_StatusTypeDef | I2C_Slave_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
static HAL_StatusTypeDef | I2C_WaitOnFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout.
static HAL_StatusTypeDef | I2C_WaitOnTXISFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of TXIS flag.
static HAL_StatusTypeDef | I2C_WaitOnRXNEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | I2C_WaitOnSTOPFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | I2C_IsAcknowledgeFailed (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles Acknowledge failed detection during an I2C Communication.
static HAL_StatusTypeDef | I2C_Enable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static HAL_StatusTypeDef | I2C_Disable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static void | I2C_Flush_TXDR (I2C_HandleTypeDef *hi2c)
I2C Tx data register flush process.
static void | I2C_TransferConfig (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master/host I2C process communication with Interrupt.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.
HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
    The I2C HAL driver can be used as follows:

    (#) Declare a I2C_HandleTypeDef handle structure, for example:
        I2C_HandleTypeDef  hi2c;

    (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
        (##) Enable the I2Cx interface clock
        (##) I2C pins configuration
            (+++) Enable the clock for the I2C GPIOs
            (+++) Configure I2C pins as alternate function open-drain
        (##) NVIC configuration if you need to use interrupt process
            (+++) Configure the I2Cx interrupt priority
            (+++) Enable the NVIC I2C IRQ Channel
        (##) DMA Configuration if you need to use DMA process
            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
            (+++) Enable the DMAx interface clock using
            (+++) Configure the DMA handle parameters
            (+++) Configure the DMA Tx or Rx stream
            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
                  the DMA Tx or Rx stream

    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.

    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.

    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()

    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()

    *** Polling mode IO MEM operation ***
    =====================================
    [..]
      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
      (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
      (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
      (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
           This action will inform Master to generate a Stop condition to discard the communication.

    *** Interrupt mode IO sequential operation ***
    ===================================
    [..]
      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
          when a direction change during transfer
    [..]
      (+) A specific option field manage the different steps of a sequential transfer
      (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
                            and data to transfer without a final stop condition
      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
                            and data to transfer without a final stop condition, an then permit a call the same master sequential interface
                            several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT())
      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
                            and with new data to transfer if the direction change or manage only the new data to transfer
                            if no direction change and without a final stop condition in both cases
      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
                            and with new data to transfer if the direction change or manage only the new data to transfer
                            if no direction change and with a final stop condition in both cases

      (+) Differents sequential I2C interfaces are listed below:
      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
      (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
      (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
      (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
      (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
      (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
      (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
      (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
      (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
      (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
      (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
      (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
           This action will inform Master to generate a Stop condition to discard the communication.

    *** Interrupt mode IO MEM operation ***
    =======================================
    [..]
      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
          HAL_I2C_Mem_Write_IT()
      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
          HAL_I2C_Mem_Read_IT()
      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback()

    *** DMA mode IO operation ***
    ==============================
    [..]
      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
          HAL_I2C_Master_Transmit_DMA()
      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
          HAL_I2C_Master_Receive_DMA()
      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
          HAL_I2C_Slave_Transmit_DMA()
      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
          HAL_I2C_Slave_Receive_DMA()
      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
           This action will inform Master to generate a Stop condition to discard the communication.

    *** DMA mode IO MEM operation ***
    =================================
    [..]
      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
          HAL_I2C_Mem_Write_DMA()
      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
          HAL_I2C_Mem_Read_DMA()
      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback()

     *** I2C HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in I2C HAL driver.

      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
      (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
      (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
      (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt

     [..]
       (@) You can refer to the I2C HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_i2c.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_i2c_ex.c File Reference

  • File List
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  • Drivers
  • STM32H7xx_HAL_Driver
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Functions
stm32h7xx_hal_i2c_ex.c File Reference

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configure I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configure I2C Digital noise filter.
HAL_StatusTypeDef | HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
Enable I2C wakeup from stop mode.
HAL_StatusTypeDef | HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
Disable I2C wakeup from stop mode.
void | HAL_I2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
void | HAL_I2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.

Detailed Description

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
               ##### I2C peripheral Extended features  #####
  ==============================================================================

  [..] Comparing to other previous devices, the I2C interface for STM32H7XX
       devices contains the following additional features

       (+) Possibility to disable or enable Analog Noise Filter
       (+) Use of a configured Digital Noise Filter
       (+) Disable or enable wakeup from Stop modes
       (+) Disable or enable Fast Mode Plus

                     ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to configure Noise Filter and Wake Up Feature
    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
    (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
          (++) HAL_I2CEx_EnableWakeUp()
          (++) HAL_I2CEx_DisableWakeUp()
    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
          (++) HAL_I2CEx_EnableFastModePlus()
          (++) HAL_I2CEx_DisableFastModePlus()
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_i2c_ex.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_i2s.c File Reference

  • File List
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  • Drivers
  • STM32H7xx_HAL_Driver
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Functions
stm32h7xx_hal_i2s.c File Reference

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

static void | I2S_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process complete callback.
static void | I2S_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process half complete callback.
static void | I2S_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process complete callback.
static void | I2S_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process half complete callback.
static void | I2S_DMAError (DMA_HandleTypeDef *hdma)
DMA I2S communication error callback.
static void | I2S_TxISR_16BIT (struct __I2S_HandleTypeDef *hi2s)
Handle the data 16-bit transmit in Interrupt mode.
static void | I2S_TxISR_32BIT (struct __I2S_HandleTypeDef *hi2s)
Handle the data 32-bit transmit in Interrupt mode.
static void | I2S_RxISR_16BIT (struct __I2S_HandleTypeDef *hi2s)
Manage the 16-bit receive in Interrupt context.
static void | I2S_RxISR_32BIT (struct __I2S_HandleTypeDef *hi2s)
Manage the 32-bit receive in Interrupt context.
static void | I2S_CloseRx_ISR (I2S_HandleTypeDef *hi2s)
Handle the end of the RX transaction.
static void | I2S_CloseTx_ISR (I2S_HandleTypeDef *hi2s)
Handle the end of the TX transaction.
static HAL_StatusTypeDef | I2S_WaitFlagStateUntilTimeout (I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
This function handles I2S Communication Timeout.
HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s)
DeInitializes the I2S peripheral.
__weak void | HAL_I2S_MspInit (I2S_HandleTypeDef *hi2s)
I2S MSP Init.
__weak void | HAL_I2S_MspDeInit (I2S_HandleTypeDef *hi2s)
I2S MSP DeInit.
HAL_StatusTypeDef | HAL_I2S_Transmit (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Receive (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Transmit_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Receive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Transmit_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_Receive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Stops the audio stream playing from the Media.
void | HAL_I2S_IRQHandler (I2S_HandleTypeDef *hi2s)
This function handles I2S interrupt request.
__weak void | HAL_I2S_TxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer Half completed callbacks.
__weak void | HAL_I2S_TxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
__weak void | HAL_I2S_RxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer half completed callbacks.
__weak void | HAL_I2S_RxCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
__weak void | HAL_I2S_ErrorCallback (I2S_HandleTypeDef *hi2s)
I2S error callbacks.
HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.

Detailed Description

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
 ===============================================================================
                  ##### How to use this driver #####
 ===============================================================================
 [..]
    The I2S HAL driver can be used as follow:

    (#) Declare a I2S_HandleTypeDef handle structure.
    (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
        (##) Enable the SPIx interface clock.
        (##) I2S pins configuration:
            (+++) Enable the clock for the I2S GPIOs.
            (+++) Configure these I2S pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
             and HAL_I2S_Receive_IT() APIs).
            (+++) Configure the I2Sx interrupt priority.
            (+++) Enable the NVIC I2S IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
             and HAL_I2S_Receive_DMA() APIs:
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Channel.
            (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
                  DMA Tx/Rx Channel.

   (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
       using HAL_I2S_Init() function.

   -@- The specific I2S interrupts (Transmission complete interrupt,
       RXNE interrupt and Error Interrupts) will be managed using the macros
       __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
   -@- Make sure that either:
       (+@) External clock source is configured after setting correctly
            the define constant EXTERNAL_CLOCK_VALUE in the stm32h7xx_hal_conf.h file.

   Three mode of operations are available within this driver :

   *** Polling mode IO operation ***
   =================================
   [..]
     (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
     (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()

   *** Interrupt mode IO operation ***
   ===================================
   [..]
     (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
     (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback

   *** DMA mode IO operation ***
   ==============================
   [..]
     (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
     (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback
     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()

   *** I2S HAL driver macros list ***
   ===================================
   [..]
     Below the list of most used macros in I2S HAL driver.

      (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
      (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
      (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
      (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
      (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not

    [..]
      (@) You can refer to the I2S HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_i2s.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_i2s_ex.c File Reference

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Enumerations | Functions
stm32h7xx_hal_i2s_ex.c File Reference

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of I2S extension peripheral: + IO operation functions + Peripheral Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Enumerations

enum | I2S_UseTypeDef { I2S_USE_I2S = 0x00U, I2S_USE_I2SEXT = 0x01U }

Functions

static void | I2SEx_DMATxRxCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit receive process complete callback.
static void | I2SEx_DMATxRxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit receive process half complete callback.
static void | I2SEx_TxRxDMAError (DMA_HandleTypeDef *hdma)
DMA I2S communication error callback.
static void | I2SEx_2linesTxISR_16BIT (struct __I2S_HandleTypeDef *hi2s)
Tx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | I2SEx_2linesTxISR_32BIT (struct __I2S_HandleTypeDef *hi2s)
Tx 32-bit handler for Transmit and Receive in Interrupt mode.
static void | I2SEx_2linesRxISR_16BIT (struct __I2S_HandleTypeDef *hi2s)
Rx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | I2SEx_2linesRxISR_32BIT (struct __I2S_HandleTypeDef *hi2s)
Rx 32-bit handler for Transmit and Receive in Interrupt mode.
static void | I2SEx_CloseRxTx_ISR (I2S_HandleTypeDef *hi2s)
Handle the end of the RXTX transaction.
static HAL_StatusTypeDef | I2SEx_WaitFlagStateUntilTimeout (I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
This function handles I2S Communication Timeout.
HAL_StatusTypeDef | HAL_I2SEx_TransmitReceive (I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2SEx_TransmitReceive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2SEx_TransmitReceive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
__weak void | HAL_I2SEx_TxRxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx/Rx Transfer half completed callbacks.
__weak void | HAL_I2SEx_TxRxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx/Rx Transfer completed callbacks.

Detailed Description

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of I2S extension peripheral: + IO operation functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                  ##### I2S Extension features #####
  ==============================================================================
  [..]
     (+) In I2S full duplex mode, SPI2S peripheral is able to manage sending and receiving
         data simultaneously using two data lines.

 ===============================================================================
                  ##### How to use this driver #####
 ===============================================================================
 [..]
   Three operation modes are available within this driver :

   *** Polling mode IO operation ***
   =================================
   [..]
     (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2SEx_TransmitReceive()

   *** Interrupt mode IO operation ***
   ===================================
   [..]
     (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2SEx_TransmitReceive_IT()
     (+) At full duplex transfer end of half transfer HAL_I2SEx_TxRxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2SEx_TxRxHalfCpltCallback
     (+) At full duplex transfer end of transfer HAL_I2SEx_TxRxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2SEx_TxRxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback

   *** DMA mode IO operation ***
   ==============================
   [..]
     (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2SEx_TransmitReceive_DMA()
     (+) At the end of half transfer HAL_I2SEx_TxRxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
     (+) At the end of transfer HAL_I2S_TxRxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback
     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_i2s_ex.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_irda.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_irda.c File Reference

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | IRDA_TEACK_REACK_TIMEOUT 1000
#define | IRDA_CR1_FIELDS

Functions

static HAL_StatusTypeDef | IRDA_SetConfig (IRDA_HandleTypeDef *hirda)
Configure the IRDA peripheral.
static HAL_StatusTypeDef | IRDA_CheckIdleState (IRDA_HandleTypeDef *hirda)
Check the IRDA Idle State.
static HAL_StatusTypeDef | IRDA_WaitOnFlagUntilTimeout (IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle IRDA Communication Timeout.
static void | IRDA_EndTxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
static void | IRDA_EndRxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).
static void | IRDA_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process complete callback.
static void | IRDA_DMATransmitHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process complete callback.
static void | IRDA_DMAReceiveHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAError (DMA_HandleTypeDef *hdma)
DMA IRDA communication error callback.
static void | IRDA_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA IRDA communication abort callback (To be called at end of DMA Abort procedure).
static void | IRDA_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | IRDA_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | IRDA_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | IRDA_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static HAL_StatusTypeDef | IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda)
Send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | IRDA_EndTransmit_IT (IRDA_HandleTypeDef *hirda)
Wrap up transmission in non-blocking mode.
static HAL_StatusTypeDef | IRDA_Receive_IT (IRDA_HandleTypeDef *hirda)
Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
Initialize the IRDA MSP.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA MSP.
HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_Abort (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_Abort_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
Handle IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer completed callback.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callback.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer completed callback.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callback.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callback.
__weak void | HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Receive Complete callback.
HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Return the IRDA handle state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IRDA handle error code.

Detailed Description

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The IRDA HAL driver can be used as follows:

    (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
    (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
        in setting the associated USART or UART in IRDA mode:
        (++) Enable the USARTx/UARTx interface clock.
        (++) USARTx/UARTx pins configuration:
            (+++) Enable the clock for the USARTx/UARTx GPIOs.
            (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
        (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
             and HAL_IRDA_Receive_IT() APIs):
            (+++) Configure the USARTx/UARTx interrupt priority.
            (+++) Enable the NVIC USARTx/UARTx IRQ handle.
            (+++) The specific IRDA interrupts (Transmission complete interrupt,
                  RXNE interrupt and Error Interrupts) will be managed using the macros
                  __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.

        (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
             and HAL_IRDA_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.

    (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
        the normal or low power mode and the clock prescaler in the hirda handle Init structure.

    (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_IRDA_MspInit() API.

         -@@- The specific IRDA interrupts (Transmission complete interrupt,
             RXNE interrupt and Error Interrupts) will be managed using the macros
             __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.

    (#) Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
       (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
       (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()

     *** IRDA HAL driver macros list ***
     ====================================
     [..]
       Below the list of most used macros in IRDA HAL driver.

       (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
       (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
       (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
       (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
       (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
       (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
       (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled

     [..]
       (@) You can refer to the IRDA HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_irda.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_iwdg.c File Reference

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Defines | Functions
stm32h7xx_hal_iwdg.c File Reference

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | HAL_IWDG_DEFAULT_TIMEOUT 48u

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                    ##### IWDG Generic features #####
  ==============================================================================
  [..]
    (+) The IWDG can be started by either software or hardware (configurable
        through option byte).

    (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
        if the main clock fails.

    (+) Once the IWDG is started, the LSI is forced ON and both can not be
        disabled. The counter starts counting down from the reset value (0xFFF).
        When it reaches the end of count value (0x000) a reset signal is
        generated (IWDG reset).

    (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
        the IWDG_RLR value is reloaded in the counter and the watchdog reset is
        prevented.

    (+) The IWDG is implemented in the VDD voltage domain that is still functional
        in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
        IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
        reset occurs.

    (+) Debug mode : When the microcontroller enters debug mode (core halted),
        the IWDG counter either continues to work normally or stops, depending
        on DBG_IWDG_STOP configuration bit in DBG module, accessible through
        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros

    [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
         The IWDG timeout may vary due to LSI frequency dispersion. STM32H7xx
         devices provide the capability to measure the LSI frequency (LSI clock
         connected internally to TIM16 CH1 input capture). The measured value
         can be used to have an IWDG timeout with an acceptable accuracy.

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (#) Use IWDG using HAL_IWDG_Init() function to :
      (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
           clock is forced ON and IWDG counter starts downcounting.
      (++) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
           IWDG_WINR.
      (++) Configure the IWDG prescaler and counter reload value. This reload
           value will be loaded in the IWDG counter each time the watchdog is
           reloaded, then the IWDG will start counting down from this value.
      (++) Wait for status flags to be reset
      (++) Depending on window parameter:
         (+++) If Window Init parameter is same as Window register value,
               nothing more is done but reload counter value in order to exit
               function withy exact time base.
         (+++) Else modify Window register. This will automatically reload
               watchdog counter.

    (#) Then the application program must refresh the IWDG counter at regular
        intervals during normal operation to prevent an MCU reset, using
        HAL_IWDG_Refresh() function.

     *** IWDG HAL driver macros list ***
     ====================================
     [..]
       Below the list of most used macros in IWDG HAL driver:
      (+) __HAL_IWDG_START: Enable the IWDG peripheral
      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
          the reload register
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_iwdg.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_jpeg.c File Reference

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stm32h7xx_hal_jpeg.c File Reference

JPEG HAL module driver. This file provides firmware functions to manage the following functionalities of the JPEG encoder/decoder peripheral: + Initialization and de-initialization functions + JPEG processing functions encoding and decoding + JPEG decoding Getting Info and encoding configuration setting + JPEG enable/disable header parsing functions (for decoding) + JPEG Input/Output Buffer configuration. + JPEG callback functions + JPEG Abort/Pause/Resume functions + JPEG custom quantization tables setting functions + IRQ handler management + Peripheral State and Error functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Data Structures

struct | JPEG_ACHuffTableTypeDef
struct | JPEG_DCHuffTableTypeDef
struct | JPEG_AC_HuffCodeTableTypeDef
struct | JPEG_DC_HuffCodeTableTypeDef

Defines

#define | JPEG_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */
#define | JPEG_AC_HUFF_TABLE_SIZE ((uint32_t)162U) /* Huffman AC table size : 162 codes*/
#define | JPEG_DC_HUFF_TABLE_SIZE ((uint32_t)12U) /* Huffman AC table size : 12 codes*/
#define | JPEG_FIFO_SIZE ((uint32_t)16U) /* JPEG Input/Output HW FIFO size in words*/
#define | JPEG_FIFO_TH_SIZE ((uint32_t)8U) /* JPEG Input/Output HW FIFO Threshold in words*/
#define | JPEG_INTERRUPT_MASK ((uint32_t)0x0000007EU) /* JPEG Interrupt Mask*/
#define | JPEG_CONTEXT_ENCODE ((uint32_t)0x00000001U) /* JPEG context : operation is encoding*/
#define | JPEG_CONTEXT_DECODE ((uint32_t)0x00000002U) /* JPEG context : operation is decoding*/
#define | JPEG_CONTEXT_OPERATION_MASK ((uint32_t)0x00000003U) /* JPEG context : operation Mask */
#define | JPEG_CONTEXT_POLLING ((uint32_t)0x00000004U) /* JPEG context : Transfer use Polling */
#define | JPEG_CONTEXT_IT ((uint32_t)0x00000008U) /* JPEG context : Transfer use Interrupt */
#define | JPEG_CONTEXT_DMA ((uint32_t)0x0000000CU) /* JPEG context : Transfer use DMA */
#define | JPEG_CONTEXT_METHOD_MASK ((uint32_t)0x0000000CU) /* JPEG context : Transfer Mask */
#define | JPEG_CONTEXT_CONF_ENCODING ((uint32_t)0x00000100U) /* JPEG context : encoding config done */
#define | JPEG_CONTEXT_PAUSE_INPUT ((uint32_t)0x00001000U) /* JPEG context : Pause Input */
#define | JPEG_CONTEXT_PAUSE_OUTPUT ((uint32_t)0x00002000U) /* JPEG context : Pause Output */
#define | JPEG_CONTEXT_CUSTOM_TABLES ((uint32_t)0x00004000U) /* JPEG context : Use custom quantization tables */
#define | JPEG_CONTEXT_ENDING_DMA ((uint32_t)0x00008000U) /* JPEG context : ending with DMA in progress */
#define | JPEG_PROCESS_ONGOING ((uint32_t)0x00000000U) /* Process is on going */
#define | JPEG_PROCESS_DONE ((uint32_t)0x00000001U) /* Process is done (ends) */

Functions

static HAL_StatusTypeDef | JPEG_Bits_To_SizeCodes (uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK)
Generates Huffman sizes/Codes Table from Bits/vals Table.
static HAL_StatusTypeDef | JPEG_DCHuff_BitsVals_To_SizeCodes (JPEG_DCHuffTableTypeDef *DC_BitsValsTable, JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable)
Transform a Bits/Vals DC Huffman table to sizes/Codes huffman Table that can programmed to the JPEG encoder registers.
static HAL_StatusTypeDef | JPEG_ACHuff_BitsVals_To_SizeCodes (JPEG_ACHuffTableTypeDef *AC_BitsValsTable, JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable)
Transform a Bits/Vals AC Huffman table to sizes/Codes huffman Table that can programmed to the JPEG encoder registers.
static HAL_StatusTypeDef | JPEG_Set_HuffDC_Mem (JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, __IO uint32_t *DCTableAddress)
Set the JPEG register with an DC huffman table at the given DC table address.
static HAL_StatusTypeDef | JPEG_Set_HuffAC_Mem (JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, __IO uint32_t *ACTableAddress)
Set the JPEG register with an AC huffman table at the given AC table address.
static HAL_StatusTypeDef | JPEG_Set_HuffEnc_Mem (JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0, JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1)
Configure the JPEG encoder register huffman tables to used during the encdoing operation.
static void | JPEG_Set_Huff_DHTMem (JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0, JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1)
Configure the JPEG register huffman tables to be included in the JPEG file header (used for encoding only)
static HAL_StatusTypeDef | JPEG_Set_Quantization_Mem (JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, __IO uint32_t *QTableAddress)
Configure the JPEG registers with a given quantization table.
static void | JPEG_SetColorYCBCR (JPEG_HandleTypeDef *hjpeg)
Configure the JPEG registers for YCbCr color space.
static void | JPEG_SetColorGrayScale (JPEG_HandleTypeDef *hjpeg)
Configure the JPEG registers for GrayScale color space.
static void | JPEG_SetColorCMYK (JPEG_HandleTypeDef *hjpeg)
Configure the JPEG registers for CMYK color space.
static void | JPEG_Init_Process (JPEG_HandleTypeDef *hjpeg)
Init the JPEG encoding/decoding process in case of Polling or Interrupt and DMA.
static uint32_t | JPEG_Process (JPEG_HandleTypeDef *hjpeg)
JPEG encoding/decoding process in case of Polling or Interrupt.
static void | JPEG_ReadInputData (JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords)
Read some input Data from the input buffer.
static void | JPEG_StoreOutputData (JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords)
Store some output data from the JPEG peripheral to the output buffer.
static uint32_t | JPEG_GetQuality (JPEG_HandleTypeDef *hjpeg)
Calculate the decoded image quality (from 1 to 100)
static HAL_StatusTypeDef | JPEG_DMA_StartProcess (JPEG_HandleTypeDef *hjpeg)
Start the JPEG DMA process (encoding/decoding)
static uint32_t | JPEG_DMA_ContinueProcess (JPEG_HandleTypeDef *hjpeg)
Continue the current JPEG DMA process (encoding/decoding)
static uint32_t | JPEG_DMA_EndProcess (JPEG_HandleTypeDef *hjpeg)
Finalize the current JPEG DMA process (encoding/decoding)
static void | JPEG_DMA_PollResidualData (JPEG_HandleTypeDef *hjpeg)
Poll residual output data when DMA process (encoding/decoding)
static void | JPEG_MDMAOutCpltCallback (MDMA_HandleTypeDef *hmdma)
DMA output transfer complete callback.
static void | JPEG_MDMAInCpltCallback (MDMA_HandleTypeDef *hmdma)
DMA input transfer complete callback.
static void | JPEG_MDMAErrorCallback (MDMA_HandleTypeDef *hmdma)
DMA Transfer error callback.
static void | JPEG_MDMAOutAbortCallback (MDMA_HandleTypeDef *hmdma)
DMA output Abort callback.
HAL_StatusTypeDef | HAL_JPEG_Init (JPEG_HandleTypeDef *hjpeg)
Initializes the JPEG according to the specified parameters in the JPEG_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_JPEG_DeInit (JPEG_HandleTypeDef *hjpeg)
DeInitializes the JPEG peripheral.
__weak void | HAL_JPEG_MspInit (JPEG_HandleTypeDef *hjpeg)
Initializes the JPEG MSP.
__weak void | HAL_JPEG_MspDeInit (JPEG_HandleTypeDef *hjpeg)
DeInitializes JPEG MSP.
HAL_StatusTypeDef | HAL_JPEG_ConfigEncoding (JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf)
Set the JPEG encoding configuration.
HAL_StatusTypeDef | HAL_JPEG_GetInfo (JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
Extract the image configuration from the JPEG header during the decoding.
HAL_StatusTypeDef | HAL_JPEG_EnableHeaderParsing (JPEG_HandleTypeDef *hjpeg)
Enable JPEG Header parsing for decoding.
HAL_StatusTypeDef | HAL_JPEG_DisableHeaderParsing (JPEG_HandleTypeDef *hjpeg)
Disable JPEG Header parsing for decoding.
HAL_StatusTypeDef | HAL_JPEG_SetUserQuantTables (JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, uint8_t *QTable2, uint8_t *QTable3)
Modify the default Quantization tables used for JPEG encoding.
HAL_StatusTypeDef | HAL_JPEG_Encode (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout)
Starts JPEG encoding with polling processing.
HAL_StatusTypeDef | HAL_JPEG_Decode (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, uint8_t *pDataOutMCU, uint32_t OutDataLength, uint32_t Timeout)
Starts JPEG decoding with polling processing.
HAL_StatusTypeDef | HAL_JPEG_Encode_IT (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)
Starts JPEG encoding with interrupt processing.
HAL_StatusTypeDef | HAL_JPEG_Decode_IT (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, uint8_t *pDataOutMCU, uint32_t OutDataLength)
Starts JPEG decoding with interrupt processing.
HAL_StatusTypeDef | HAL_JPEG_Encode_DMA (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)
Starts JPEG encoding with DMA processing.
HAL_StatusTypeDef | HAL_JPEG_Decode_DMA (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, uint8_t *pDataOutMCU, uint32_t OutDataLength)
Starts JPEG decoding with DMA processing.
HAL_StatusTypeDef | HAL_JPEG_Pause (JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)
Pause the JPEG Input/Output processing.
HAL_StatusTypeDef | HAL_JPEG_Resume (JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)
Resume the JPEG Input/Output processing.
void | HAL_JPEG_ConfigInputBuffer (JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength)
Config Encoding/Decoding Input Buffer.
void | HAL_JPEG_ConfigOutputBuffer (JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength)
Config Encoding/Decoding Output Buffer.
HAL_StatusTypeDef | HAL_JPEG_Abort (JPEG_HandleTypeDef *hjpeg)
Aborts the JPEG Encoding/Decoding.
__weak void | HAL_JPEG_InfoReadyCallback (JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
Decoding JPEG Info ready callback.
__weak void | HAL_JPEG_EncodeCpltCallback (JPEG_HandleTypeDef *hjpeg)
Encoding complete callback.
__weak void | HAL_JPEG_DecodeCpltCallback (JPEG_HandleTypeDef *hjpeg)
Decoding complete callback.
__weak void | HAL_JPEG_ErrorCallback (JPEG_HandleTypeDef *hjpeg)
JPEG error callback.
__weak void | HAL_JPEG_GetDataCallback (JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData)
Get New Data chunk callback.
__weak void | HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength)
Decoded/Encoded Data ready callback.
void | HAL_JPEG_IRQHandler (JPEG_HandleTypeDef *hjpeg)
This function handles JPEG interrupt request.
HAL_JPEG_STATETypeDef | HAL_JPEG_GetState (JPEG_HandleTypeDef *hjpeg)
Returns the JPEG state.
uint32_t | HAL_JPEG_GetError (JPEG_HandleTypeDef *hjpeg)
Return the JPEG error code.

Variables

static const
JPEG_DCHuffTableTypeDef 		JPEG_DCLUM_HuffTable
static const
JPEG_DCHuffTableTypeDef 		JPEG_DCCHROM_HuffTable
static const
JPEG_ACHuffTableTypeDef 		JPEG_ACLUM_HuffTable
static const
JPEG_ACHuffTableTypeDef 		JPEG_ACCHROM_HuffTable
static const uint8_t | JPEG_LUM_QuantTable [JPEG_QUANT_TABLE_SIZE]
static const uint8_t | JPEG_CHROM_QuantTable [JPEG_QUANT_TABLE_SIZE]
static const uint8_t | JPEG_ZIGZAG_ORDER [JPEG_QUANT_TABLE_SIZE]

Detailed Description

JPEG HAL module driver. This file provides firmware functions to manage the following functionalities of the JPEG encoder/decoder peripheral: + Initialization and de-initialization functions + JPEG processing functions encoding and decoding + JPEG decoding Getting Info and encoding configuration setting + JPEG enable/disable header parsing functions (for decoding) + JPEG Input/Output Buffer configuration. + JPEG callback functions + JPEG Abort/Pause/Resume functions + JPEG custom quantization tables setting functions + IRQ handler management + Peripheral State and Error functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the JPEG peripheral using HAL_JPEG_Init : No initialization parameters are required.
         Only the call to HAL_JPEG_Init is necessary to initialize the JPEG peripheral.

     (#) If operation is JPEG encoding use function HAL_JPEG_ConfigEncoding to set
         the encoding parameters (mandatory before calling the encoding function).
         the application can change the encoding parameter "ImageQuality" from
         1 to 100 to obtain a more or less quality (visual quality vs the original row image),
         and inversely more or less jpg file size.

     (#) Note that for decoding operation the JPEG peripheral output data are organized in
         YCbCr blocks called MCU (Minimum Coded Unit) as defioned in the JPEG specification
         ISO/IEC 10918-1 standard.
         It is up to the application to transform these YCbCr blocks to RGB data that can be display.

         Respectively, for Encoding operation the JPEG peripheral input should be organized
         in YCbCr MCU blocks. It is up to the application to perform the necessary RGB to YCbCr
         MCU blocks transformation before feeding the JPEG peripheral with data.

     (#) Use functions HAL_JPEG_Encode and HAL_JPEG_Decode to start respectively
         a JPEG encoding/decoding operation in polling method (blocking).

     (#) Use functions HAL_JPEG_Encode_IT and HAL_JPEG_Decode_IT to start respectively
         a JPEG encoding/decoding operation with Interrupt method (not blocking).

     (#) Use functions HAL_JPEG_Encode_DMA and HAL_JPEG_Decode_DMA to start respectively
         a JPEG encoding/decoding operation with DMA method (not blocking).

     (#) Callback HAL_JPEG_InfoReadyCallback is asserted if the current operation
         is a JPEG decoding to provide the application with JPEG image  parameters.
         This callback is asserted when the JPEG peripheral successfully parse the
         JPEG header.

     (#) Callback HAL_JPEG_GetDataCallback is asserted for both encoding and decoding
         operations to inform the application that the input buffer has been
         consumed by the peripheral and to ask for a new data chunk if the operation
         (encoding/decoding) has not been complete yet.

        (++) This CallBack should be implemented in the application side. It should
             call the function HAL_JPEG_ConfigInputBuffer if new input data are available,
             or call HAL_JPEG_Pause with parameter XferSelection set to JPEG_PAUSE_RESUME_INPUT
             to inform the JPEG HAL driver that the ongoing operation shall pause waiting for the
             application to provide a new input data chunk.
             Once the application succeed getting new data and if the input has been paused,
             the application can call the function HAL_JPEG_ConfigInputBuffer to set the new
             input buffer and size, then resume the JPEG HAL input by calling new function HAL_JPEG_Resume.
             If the application has ended feeding the HAL JPEG with input data (no more input data), the application
             Should call the function HAL_JPEG_ConfigInputBuffer (within the callback HAL_JPEG_GetDataCallback)
             with the parameter InDataLength set to zero.

         (++) The mechanism of HAL_JPEG_ConfigInputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows
              to the application to provide the input data (for encoding or decoding) by chunks.
              If the new input data chunk is not available (because data should be read from an input file
              for example) the application can pause the JPEG input (using function HAL_JPEG_Pause)
              Once the new input data chunk is available ( read from a file for example), the application
              can call the function HAL_JPEG_ConfigInputBuffer to provide the HAL with the new chunk
              then resume the JPEG HAL input by calling function HAL_JPEG_Resume.

         (++) The application can call functions HAL_JPEG_ConfigInputBuffer then HAL_JPEG_Resume.
              any time (outside the HAL_JPEG_GetDataCallback)  Once the new input chunk data available.
              However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called
              (if necessary) within the callback HAL_JPEG_GetDataCallback, i.e when the HAL JPEG has ended
              Transferring the previous chunk buffer to the JPEG peripheral.

     (#) Callback HAL_JPEG_DataReadyCallback is asserted when the HAL JPEG driver
         has filled the given output buffer with the given size.

         (++) This CallBack should be implemented in the application side. It should
              call the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver
              with the new output buffer location and size to be used  to store next data chunk.
              if the application is not ready to provide the output chunk location then it can
              call the function HAL_JPEG_Pause with parameter XferSelection set to "JPEG_PAUSE_RESUME_OUTPUT"
              to inform the JPEG HAL driver that it shall pause output data. Once the application
              is ready to receive the new data chunk (output buffer location free or available) it should call
              the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver
              with the new output chunk buffer location and size, then call "HAL_JPEG_Resume"
              to inform the HAL that it shall resume outputting data in the given output buffer.

         (++) The mechanism of HAL_JPEG_ConfigOutputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows
              the application to receive data from the JPEG peripheral by chunks. when a chunk
              is received, the application can pause the HAL JPEG output data to be able to process
              these received data (YCbCr to RGB conversion in case of decoding or data storage in case
              of encoding).

         (++) The application can call  functions HAL_JPEG_ ConfigOutputBuffer then HAL_JPEG_Resume.
              any time (outside the HAL_JPEG_DataReadyCallback) Once the output data buffer is free to use.
              However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called
              (if necessary) within the callback HAL_JPEG_ DataReadyCallback, i.e when the HAL JPEG has ended
              Transferring the previous chunk buffer from the JPEG peripheral to the application.

     (#) Callback HAL_JPEG_EncodeCpltCallback is asserted when the HAL JPEG driver has
         ended the current JPEG encoding operation, and all output data has been transmitted
         to the application.

     (#) Callback HAL_JPEG_DecodeCpltCallback is asserted when the HAL JPEG driver has
         ended the current JPEG decoding operation. and all output data has been transmitted
         to the application.

     (#) Callback HAL_JPEG_ErrorCallback is asserted when an error occurred during
         the current operation. the application can call the function "HAL_JPEG_GetError"
         to retrieve the error codes.

     (#) By default the HAL JPEG driver uses the default quantization tables
         as provide in the JPEG specification (ISO/IEC 10918-1 standard) for encoding.
         User can change these default tables if necessary using the function HAL_JPEG_SetUserQuantTables
         Note that for decoding the quantization tables are automatically extracted from
         the JPEG header.

      (#) To control JPEG state you can use the following function: HAL_JPEG_GetState()

     *** JPEG HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in JPEG HAL driver.

      (+) __HAL_JPEG_RESET_HANDLE_STATE : Reset JPEG handle state.
      (+) __HAL_JPEG_ENABLE             : Enable the JPEG peripheral.
      (+) __HAL_JPEG_DISABLE            : Disable the JPEG peripheral.
      (+) __HAL_JPEG_GET_FLAG           : Check the specified JPEG status flag.
      (+) __HAL_JPEG_CLEAR_FLAG         : Clear the specified JPEG status flag.
      (+) __HAL_JPEG_ENABLE_IT          : Enable the specified JPEG Interrupt.
      (+) __HAL_JPEG_DISABLE_IT         : Disable the specified JPEG Interrupt.
      (+) __HAL_JPEG_GET_IT_SOURCE      : returns the state of the specified JPEG Interrupt (Enabled or disabled).
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_jpeg.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_lptim.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32H7xx_HAL_Driver
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Functions
stm32h7xx_hal_lptim.c File Reference

LPTIM HAL module driver. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize the LPTIM peripheral.
__weak void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM MSP.
__weak void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize LPTIM MSP.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface in nterrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode in interrupt mode.
uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
Return the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
Return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
Return the current Compare (Pulse) value.
void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
Handle LPTIM interrupt request.
__weak void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non-blocking mode.
__weak void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non-blocking mode.
__weak void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non-blocking mode.
HAL_LPTIM_StateTypeDef | HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Returns the LPTIM state.

Detailed Description

LPTIM HAL module driver.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017 This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions.
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      The LPTIM HAL driver can be used as follows:

      (#)Initialize the LPTIM low level resources by implementing the
        HAL_LPTIM_MspInit():
         (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
         (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
             (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
             (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
             (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().

      (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
         configures mainly:
         (++) The instance: LPTIM1 or LPTIM2.
         (++) Clock: the counter clock.
                 (+++) Source   : it can be either the ULPTIM input (IN1) or one of
                              the internal clock; (APB, LSE, LSI or MSI).
                 (+++) Prescaler: select the clock divider.
         (++)  UltraLowPowerClock : To be used only if the ULPTIM is selected
               as counter clock source.
                 (+++) Polarity:   polarity of the active edge for the counter unit
                               if the ULPTIM input is selected.
                 (+++) SampleTime: clock sampling time to configure the clock glitch
                               filter.
         (++) Trigger: How the counter start.
                 (+++) Source: trigger can be software or one of the hardware triggers.
                 (+++) ActiveEdge : only for hardware trigger.
                 (+++) SampleTime : trigger sampling time to configure the trigger
                                glitch filter.
         (++) OutputPolarity : 2 opposite polarities are possibles.
         (++) UpdateMode: specifies whether the update of the autoreload and
              the compare values is done immediately or after the end of current
              period.
         (++) Input1Source: Source selected for input1 (GPIO or comparator output).
         (++) Input2Source: Source selected for input2 (GPIO or comparator output).
              Input2 is used only for encoder feature so is used only for LPTIM1 instance.

      (#)Six modes are available:

         (++) PWM Mode: To generate a PWM signal with specified period and pulse,
         call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
         mode.

         (++) One Pulse Mode: To generate pulse with specified width in response
         to a stimulus, call HAL_LPTIM_OnePulse_Start() or
         HAL_LPTIM_OnePulse_Start_IT() for interruption mode.

         (++) Set once Mode: In this mode, the output changes the level (from
         low level to high level if the output polarity is configured high, else
         the opposite) when a compare match occurs. To start this mode, call
         HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
         interruption mode.

         (++) Encoder Mode: To use the encoder interface call
         HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
         interruption mode. Only available for LPTIM1 instance.

         (++) Time out Mode: an active edge on one selected trigger input rests
         the counter. The first trigger event will start the timer, any
         successive trigger event will reset the counter and the timer will
         restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
         HAL_LPTIM_TimeOut_Start_IT() for interruption mode.

         (++) Counter Mode: counter can be used to count external events on
         the LPTIM Input1 or it can be used to count internal clock cycles.
         To start this mode, call HAL_LPTIM_Counter_Start() or
         HAL_LPTIM_Counter_Start_IT() for interruption mode.

      (#) User can stop any process by calling the corresponding API:
          HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
          already started in interruption mode.

       (#)De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_lptim.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_ltdc.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32H7xx_HAL_Driver
  • Src
Functions
stm32h7xx_hal_ltdc.c File Reference

LTDC HAL module driver. This file provides firmware functions to manage the following functionalities of the LTDC peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

static void | LTDC_SetConfig (LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
Configures the LTDC peripheral.
HAL_StatusTypeDef | HAL_LTDC_Init (LTDC_HandleTypeDef *hltdc)
Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef.
HAL_StatusTypeDef | HAL_LTDC_DeInit (LTDC_HandleTypeDef *hltdc)
De-initialize the LTDC peripheral.
__weak void | HAL_LTDC_MspInit (LTDC_HandleTypeDef *hltdc)
Initialize the LTDC MSP.
__weak void | HAL_LTDC_MspDeInit (LTDC_HandleTypeDef *hltdc)
De-initialize the LTDC MSP.
void | HAL_LTDC_IRQHandler (LTDC_HandleTypeDef *hltdc)
Handle LTDC interrupt request.
__weak void | HAL_LTDC_ErrorCallback (LTDC_HandleTypeDef *hltdc)
Error LTDC callback.
__weak void | HAL_LTDC_LineEventCallback (LTDC_HandleTypeDef *hltdc)
Line Event callback.
__weak void | HAL_LTDC_ReloadEventCallback (LTDC_HandleTypeDef *hltdc)
Reload Event callback.
HAL_StatusTypeDef | HAL_LTDC_ConfigLayer (LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
Configure the LTDC Layer according to the specified parameters in the LTDC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_LTDC_ConfigColorKeying (LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
Configure the color keying.
HAL_StatusTypeDef | HAL_LTDC_ConfigCLUT (LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)
Load the color lookup table.
HAL_StatusTypeDef | HAL_LTDC_EnableColorKeying (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color keying.
HAL_StatusTypeDef | HAL_LTDC_DisableColorKeying (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color keying.
HAL_StatusTypeDef | HAL_LTDC_EnableCLUT (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color lookup table.
HAL_StatusTypeDef | HAL_LTDC_DisableCLUT (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color lookup table.
HAL_StatusTypeDef | HAL_LTDC_EnableDither (LTDC_HandleTypeDef *hltdc)
Enable Dither.
HAL_StatusTypeDef | HAL_LTDC_DisableDither (LTDC_HandleTypeDef *hltdc)
Disable Dither.
HAL_StatusTypeDef | HAL_LTDC_SetWindowSize (LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
Set the LTDC window size.
HAL_StatusTypeDef | HAL_LTDC_SetWindowPosition (LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
Set the LTDC window position.
HAL_StatusTypeDef | HAL_LTDC_SetPixelFormat (LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
Reconfigure the pixel format.
HAL_StatusTypeDef | HAL_LTDC_SetAlpha (LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
Reconfigure the layer alpha value.
HAL_StatusTypeDef | HAL_LTDC_SetAddress (LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
Reconfigure the frame buffer Address.
HAL_StatusTypeDef | HAL_LTDC_SetPitch (LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is larger than the one intended to be displayed on screen.
HAL_StatusTypeDef | HAL_LTDC_ProgramLineEvent (LTDC_HandleTypeDef *hltdc, uint32_t Line)
Define the position of the line interrupt.
HAL_StatusTypeDef | HAL_LTDC_Reload (LTDC_HandleTypeDef *hltdc, uint32_t ReloadType)
Reload LTDC Layers configuration.
HAL_StatusTypeDef | HAL_LTDC_ConfigLayer_NoReload (LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
Configure the LTDC Layer according to the specified without reloading parameters in the LTDC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_LTDC_SetWindowSize_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
Set the LTDC window size without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetWindowPosition_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
Set the LTDC window position without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetPixelFormat_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
Reconfigure the pixel format without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetAlpha_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
Reconfigure the layer alpha value without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetAddress_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
Reconfigure the frame buffer Address without reloading.
HAL_StatusTypeDef | HAL_LTDC_SetPitch_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is larger than the one intended to be displayed on screen.
HAL_StatusTypeDef | HAL_LTDC_ConfigColorKeying_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
Configure the color keying without reloading.
HAL_StatusTypeDef | HAL_LTDC_EnableColorKeying_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color keying without reloading.
HAL_StatusTypeDef | HAL_LTDC_DisableColorKeying_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color keying without reloading.
HAL_StatusTypeDef | HAL_LTDC_EnableCLUT_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Enable the color lookup table without reloading.
HAL_StatusTypeDef | HAL_LTDC_DisableCLUT_NoReload (LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
Disable the color lookup table without reloading.
HAL_LTDC_StateTypeDef | HAL_LTDC_GetState (LTDC_HandleTypeDef *hltdc)
Return the LTDC handle state.
uint32_t | HAL_LTDC_GetError (LTDC_HandleTypeDef *hltdc)
Return the LTDC handle error code.

Detailed Description

LTDC HAL module driver. This file provides firmware functions to manage the following functionalities of the LTDC peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Program the required configuration through the following parameters:
         the LTDC timing, the horizontal and vertical polarity,
         the pixel clock polarity, Data Enable polarity and the LTDC background color value
         using HAL_LTDC_Init() function

     (#) Program the required configuration through the following parameters:
         the pixel format, the blending factors, input alpha value, the window size
         and the image size using HAL_LTDC_ConfigLayer() function for foreground
         or/and background layer.

     (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and
         HAL_LTDC_EnableCLUT functions.

     (#) Optionally, enable the Dither using HAL_LTDC_EnableDither().

     (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying()
         and HAL_LTDC_EnableColorKeying functions.

     (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent()
         function

     (#) If needed, reconfigure and change the pixel format value, the alpha value
         value, the window size, the window position and the layer start address
         for foreground or/and background layer using respectively the following
         functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),
         HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetAddress.

     (#) Variant functions with _NoReload post fix allows to set the LTDC configuration/settings without immediate reload.
         This is useful in case when the program requires to modify serval LTDC settings (on one or both layers)
         then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload

         After calling the _NoReload functions to set different color/format/layer settings,
         the program can call the function  HAL_LTDC_Reload To apply(Reload) these settings.
         Function HAL_LTDC_Reload can be called with the parameter  ReloadType
         set to LTDC_RELOAD_IMMEDIATE if an immediate reload is required.
         Function HAL_LTDC_Reload can be called with the parameter  ReloadType
         set to LTDC_RELOAD_VERTICAL_BLANKING if the reload should be done in the next vertical blanking period,
         this option allows to avoid display flicker by applying the new settings during the vertical blanking period.

     (#) To control LTDC state you can use the following function: HAL_LTDC_GetState()

     *** LTDC HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in LTDC HAL driver.

      (+) __HAL_LTDC_ENABLE: Enable the LTDC.
      (+) __HAL_LTDC_DISABLE: Disable the LTDC.
      (+) __HAL_LTDC_LAYER_ENABLE: Enable an LTDC Layer.
      (+) __HAL_LTDC_LAYER_DISABLE: Disable an LTDC Layer.
      (+) __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG: Reload  Layer Configuration.
      (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags.
      (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags.
      (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts.
      (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.
      (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.

     [..]
       (@) You can refer to the LTDC HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_ltdc.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_mdios.c File Reference

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Defines | Functions
stm32h7xx_hal_mdios.c File Reference

MDIOS HAL module driver. This file provides firmware functions to manage the following functionalities of the MDIOS Peripheral. + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | MDIOS_PORT_ADDRESS_SHIFT ((uint32_t)8)
#define | MDIOS_ALL_REG_FLAG ((uint32_t)0xFFFFFFFFU)
#define | MDIOS_ALL_ERRORS_FLAG ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF))
#define | MDIOS_DIN_BASE_ADDR (MDIOS_BASE + 0x100)
#define | MDIOS_DOUT_BASE_ADDR (MDIOS_BASE + 0x180)

Functions

HAL_StatusTypeDef | HAL_MDIOS_Init (MDIOS_HandleTypeDef *hmdios)
Initializes the MDIOS according to the specified parameters in the MDIOS_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_MDIOS_DeInit (MDIOS_HandleTypeDef *hmdios)
DeInitializes the MDIOS peripheral.
__weak void | HAL_MDIOS_MspInit (MDIOS_HandleTypeDef *hmdios)
MDIOS MSP Init.
__weak void | HAL_MDIOS_MspDeInit (MDIOS_HandleTypeDef *hmdios)
MDIOS MSP DeInit.
HAL_StatusTypeDef | HAL_MDIOS_WriteReg (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data)
Writes to an MDIOS output register.
HAL_StatusTypeDef | HAL_MDIOS_ReadReg (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData)
Reads an MDIOS input register.
uint32_t | HAL_MDIOS_GetWrittenRegAddress (MDIOS_HandleTypeDef *hmdios)
Gets Written registers by MDIO master.
uint32_t | HAL_MDIOS_GetReadRegAddress (MDIOS_HandleTypeDef *hmdios)
Gets Read registers by MDIO master.
HAL_StatusTypeDef | HAL_MDIOS_ClearWriteRegAddress (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
Clears Write registers flag.
HAL_StatusTypeDef | HAL_MDIOS_ClearReadRegAddress (MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
Clears Read register flag.
HAL_StatusTypeDef | HAL_MDIOS_EnableEvents (MDIOS_HandleTypeDef *hmdios)
Enables Events for MDIOS peripheral.
void | HAL_MDIOS_IRQHandler (MDIOS_HandleTypeDef *hmdios)
This function handles MDIOS interrupt request.
__weak void | HAL_MDIOS_WriteCpltCallback (MDIOS_HandleTypeDef *hmdios)
Write Complete Callback.
__weak void | HAL_MDIOS_ReadCpltCallback (MDIOS_HandleTypeDef *hmdios)
Read Complete Callback.
__weak void | HAL_MDIOS_ErrorCallback (MDIOS_HandleTypeDef *hmdios)
Error Callback.
__weak void | HAL_MDIOS_WakeUpCallback (MDIOS_HandleTypeDef *hmdios)
MDIOS WAKEUP interrupt callback.
uint32_t | HAL_MDIOS_GetError (MDIOS_HandleTypeDef *hmdios)
Gets MDIOS error flags.
HAL_MDIOS_StateTypeDef | HAL_MDIOS_GetState (MDIOS_HandleTypeDef *hmdios)
Return the MDIOS HAL state.

Detailed Description

MDIOS HAL module driver. This file provides firmware functions to manage the following functionalities of the MDIOS Peripheral. + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
    [..]
    The MDIOS HAL driver can be used as follow:

    (#) Declare a MDIOS_HandleTypeDef handle structure.

    (#) Initialize the MDIOS low level resources by implementing the HAL_MDIOS_MspInit() API:
        (##) Enable the MDIOS interface clock.
        (##) MDIOS pins configuration:
            (+++) Enable clocks for the MDIOS GPIOs.
            (+++) Configure the MDIOS pins as alternate function.
        (##) NVIC configuration if you need to use interrupt process:
            (+++) Configure the MDIOS interrupt priority.
            (+++) Enable the NVIC MDIOS IRQ handle.

    (#) Program the Port Address and the Preamble Check in the Init structure.

    (#) Initialize the MDIOS registers by calling the HAL_MDIOS_Init() API.

    (#) Perform direct slave read/write operations using the following APIs:
        (##) Read the value of a DINn register: HAL_MDIOS_ReadReg()
        (##) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()

    (#) Get the Master read/write operations flags using the following APIs:
        (##) Bit map of DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()
        (##) Bit map of DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()

    (#) Clear the read/write flags using the following APIs:
        (##) Clear read flags of a set of registers: HAL_MDIOS_ClearReadRegAddress()
        (##) Clear write flags of a set of registers: HAL_MDIOS_ClearWriteRegAddress()

    (#) Enable interrupts on events using HAL_MDIOS_EnableEvents(), when called
        the MDIOS will generate an interrupt in the following cases:
        (##) a DINn register written by the Master
        (##) a DOUTn register read by the Master
        (##) an error occur

        (@) A callback is executed for each genereted interrupt, so the driver provide the following
            HAL_MDIOS_WriteCpltCallback(), HAL_MDIOS_ReadCpltCallback() and HAL_MDIOS_ErrorCallback()
        (@) HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt
            and execute the previous callbacks

    (#) Reset the MDIOS peripheral and all related ressources by calling the HAL_MDIOS_DeInit() API.
        (##) HAL_MDIOS_MspDeInit() must be implemented to reset low level ressources
            (GPIO, Clocks, NVIC configuration ...)
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_mdios.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_mdma.c File Reference

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Defines | Functions
stm32h7xx_hal_mdma.c File Reference

This file provides firmware functions to manage the following functionalities of the Master Direct Memory Access (MDMA) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral State and errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | HAL_TIMEOUT_MDMA_ABORT ((uint32_t)5U) /* 5 ms */
#define | HAL_MDMA_CHANNEL_SIZE ((uint32_t)0x40U) /* an MDMA instance channel size is 64 byte */

Functions

static void | MDMA_SetConfig (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
Sets the MDMA Transfer parameter.
static void | MDMA_Init (MDMA_HandleTypeDef *hmdma)
HAL_StatusTypeDef | HAL_MDMA_Init (MDMA_HandleTypeDef *hmdma)
Initializes the MDMA according to the specified parameters in the MDMA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma)
DeInitializes the MDMA peripheral.
HAL_StatusTypeDef | HAL_MDMA_ConfigPostRequestMask (MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData)
Config the Post request Mask address and Mask data.
HAL_StatusTypeDef | HAL_MDMA_RegisterCallback (MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void(*pCallback)(MDMA_HandleTypeDef *_hmdma))
Register callbacks.
HAL_StatusTypeDef | HAL_MDMA_UnRegisterCallback (MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_CreateNode (MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig)
Initializes an MDMA Link Node according to the specified parameters in the pMDMA_LinkedListNodeConfig .
HAL_StatusTypeDef | HAL_MDMA_LinkedList_AddNode (MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode)
Connect a node to the linked list.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_RemoveNode (MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode)
Disconnect/Remove a node from the transfer linked list.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_EnableCircularMode (MDMA_HandleTypeDef *hmdma)
Make the linked list circular by connecting the last node to the first.
HAL_StatusTypeDef | HAL_MDMA_LinkedList_DisableCircularMode (MDMA_HandleTypeDef *hmdma)
Disable the linked list circular mode by setting the last node connection to null.
HAL_StatusTypeDef | HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
Starts the MDMA Transfer.
HAL_StatusTypeDef | HAL_MDMA_Start_IT (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
Starts the MDMA Transfer with interrupts enabled.
HAL_StatusTypeDef | HAL_MDMA_Abort (MDMA_HandleTypeDef *hmdma)
Aborts the MDMA Transfer.
HAL_StatusTypeDef | HAL_MDMA_Abort_IT (MDMA_HandleTypeDef *hmdma)
Aborts the MDMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_MDMA_PollForTransfer (MDMA_HandleTypeDef *hmdma, uint32_t CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
HAL_StatusTypeDef | HAL_MDMA_GenerateSWRequest (MDMA_HandleTypeDef *hmdma)
Generate an MDMA SW request trigger to activate the request on the given Channel.
void | HAL_MDMA_IRQHandler (MDMA_HandleTypeDef *hmdma)
Handles MDMA interrupt request.
HAL_MDMA_StateTypeDef | HAL_MDMA_GetState (MDMA_HandleTypeDef *hmdma)
Returns the MDMA state.
uint32_t | HAL_MDMA_GetError (MDMA_HandleTypeDef *hmdma)
Return the MDMA error code.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Master Direct Memory Access (MDMA) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral State and errors functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
   (#) Enable and configure the peripheral to be connected to the MDMA Channel
       (except for internal SRAM/FLASH memories: no initialization is
       necessary) please refer to Reference manual for connection between peripherals
       and MDMA requests.

   (#)
       For a given Channel use HAL_MDMA_Init function to program the required configuration through the following parameters:
       transfer request , channel priority, data endianness, Source increment, destination increment ,
       source data size, destination data size, data alignment, source Burst, destination Burst ,
       buffer Transfer Length, Transfer Trigger Mode (buffer transfer, block transfer, repeated block transfer
       or full transfer) source and destination block address offset, mask address and data.

       If using the MDMA in linked list mode then use function HAL_MDMA_LinkedList_CreateNode to fill a transfer node.
       Note that parameters given to the function HAL_MDMA_Init corresponds always to the node zero.
       Use function HAL_MDMA_LinkedList_AddNode to connect the created node to the linked list at a given position.
       User can make a linked list circular using function HAL_MDMA_LinkedList_EnableCircularMode , this function will automatically connect the
       last node of the list to the first one in order to make the list circular.
       In this case the linked list will loop on node 1 : first node connected after the initial transfer defined by the HAL_MDMA_Init

      -@-   The initial transfer itself (node 0 corresponding to the Init).
            User can disable the circular mode using function HAL_MDMA_LinkedList_DisableCircularMode, this function will then remove
            the connection between last node and first one.

       Function HAL_MDMA_LinkedList_RemoveNode can be used to remove (disconnect) a node from the transfer linked list.
       When a linked list is circular (last node connected to first one), if removing node1  (node where the linked list loops),
       the linked list remains circular and node 2 becomes the first one.
       Note that if the linked list is made circular the transfer will loop infinitely (or until aborted by the user).

    [..]
       (+) User can select the transfer trigger mode (parameter TransferTriggerMode) to define the amount of data to be
           transfer upon a request :
             (++) MDMA_BUFFER_TRANSFER : each request triggers a transfer of BufferTransferLength data
               with BufferTransferLength defined within the HAL_MDMA_Init.
             (++) MDMA_BLOCK_TRANSFER : each request triggers a transfer of a block
               with block size defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT
               or within the current linked list node parameters.
             (++) MDMA_REPEAT_BLOCK_TRANSFER : each request triggers a transfer of a number of blocks
               with block size and number of blocks defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT
               or within the current linked list node parameters.
             (++) MDMA_FULL_TRANSFER : each request triggers a full transfer
              all blocks and all nodes(if a linked list has been created using HAL_MDMA_LinkedList_CreateNode \ HAL_MDMA_LinkedList_AddNode).

     *** Polling mode IO operation ***
     =================================
    [..]
          (+) Use HAL_MDMA_Start() to start MDMA transfer after the configuration of Source
              address and destination address and the Length of data to be transferred.
          (+) Use HAL_MDMA_PollForTransfer() to poll for the end of current transfer or a transfer level
             In this case a fixed Timeout can be configured by User depending from his application.
          (+) Use HAL_MDMA_Abort() function to abort the current transfer : blocking method this API returns
              when the abort ends or timeout (should not be called from an interrupt service routine).

     *** Interrupt mode IO operation ***
     ===================================
    [..]
          (+) Configure the MDMA interrupt priority using HAL_NVIC_SetPriority()
          (+) Enable the MDMA IRQ handler using HAL_NVIC_EnableIRQ()
          (+) Use HAL_MDMA_Start_IT() to start MDMA transfer after the configuration of
              Source address and destination address and the Length of data to be transferred. In this
              case the MDMA interrupt is configured.
          (+) Use HAL_MDMA_IRQHandler() called under MDMA_IRQHandler() Interrupt subroutine
          (+) At the end of data transfer HAL_MDMA_IRQHandler() function is executed and user can
              add his own function by customization of function pointer XferCpltCallback and
              XferErrorCallback (i.e a member of MDMA handle structure).

          (+) Use HAL_MDMA_Abort_IT() function to abort the current transfer : non-blocking method. This API returns immediately
              then the callback XferAbortCallback (if specified  by the user) is asserted once the MDMA channel hase effectively aborted.
              (could be called from an interrupt service routine).

          (+) Use functions HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback respectevely to register unregister user callbacks
              from the following list :
              (++) XferCpltCallback            : transfer complete callback.
              (++) XferBufferCpltCallback      : buffer transfer complete callback.
              (++) XferBlockCpltCallback       : block transfer complete callback.
              (++) XferRepeatBlockCpltCallback : repeated block transfer complete callback.
              (++) XferErrorCallback           : transfer error callback.
              (++) XferAbortCallback           : transfer abort complete callback.

    [..]
         (+)  If the transfer Request corresponds to SW request (MDMA_REQUEST_SW) User can use function HAL_MDMA_GenerateSWRequest to
              trigger requests manually. Function HAL_MDMA_GenerateSWRequest must be used with the following precautions:
              (++) This function returns an error if used while the Transfer hase ends or not started.
              (++) If used while the current request hase not been served yet (current request transfer on going)
                this function returns an error and the new request is ignored.

              Generally this function should be used in conjunctions with the MDMA callbacks:
              (++) example 1:
                 (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BUFFER_TRANSFER
                 (+++) Register a callback for buffer transfer complete (using callback ID set to HAL_MDMA_XFER_BUFFERCPLT_CB_ID)
                 (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first BufferTransferLength data.
                 (+++) When the buffer transfer complete callback is asserted first buffer hase been transferred and user can ask for a new buffer transfer
                   request using HAL_MDMA_GenerateSWRequest.

              (++) example 2:
                 (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BLOCK_TRANSFER
                 (+++) Register a callback for block transfer complete (using callback ID HAL_MDMA_XFER_BLOCKCPLT_CB_ID)
                 (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first block of data.
                 (+++) When the block transfer complete callback is asserted the fisrt block hase been transferred and user can ask
                   for a new block transfer request using HAL_MDMA_GenerateSWRequest.

    [..]  Use HAL_MDMA_GetState() function to return the MDMA state and HAL_MDMA_GetError() in case of error detection.

     *** MDMA HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in MDMA HAL driver.

      (+) __HAL_MDMA_ENABLE: Enable the specified MDMA Stream.
      (+) __HAL_MDMA_DISABLE: Disable the specified MDMA Stream.
      (+) __HAL_MDMA_GET_FLAG: Get the MDMA Stream pending flags.
      (+) __HAL_MDMA_CLEAR_FLAG: Clear the MDMA Stream pending flags.
      (+) __HAL_MDMA_ENABLE_IT: Enable the specified MDMA Stream interrupts.
      (+) __HAL_MDMA_DISABLE_IT: Disable the specified MDMA Stream interrupts.
      (+) __HAL_MDMA_GET_IT_SOURCE: Check whether the specified MDMA Stream interrupt has occurred or not.

     [..]
      (@) You can refer to the header file of the MDMA HAL driver for more useful macros.

    [..]
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_mdma.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_mmc.c File Reference

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  • STM32H7xx_HAL_Driver
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Functions
stm32h7xx_hal_mmc.c File Reference

MMC card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (MMC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + MMC card Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

static uint32_t | MMC_InitCard (MMC_HandleTypeDef *hmmc)
Initializes the mmc card.
static uint32_t | MMC_PowerON (MMC_HandleTypeDef *hmmc)
Enquires cards about their operating voltage and configures clock controls and stores MMC information that will be needed in future in the MMC handle.
static uint32_t | MMC_SendStatus (MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
Returns the current card's status.
static HAL_StatusTypeDef | MMC_PowerOFF (MMC_HandleTypeDef *hmmc)
Turns the SDMMC output signals off.
static HAL_StatusTypeDef | MMC_Write_IT (MMC_HandleTypeDef *hmmc)
Wrap up writing in non-blocking mode.
static HAL_StatusTypeDef | MMC_Read_IT (MMC_HandleTypeDef *hmmc)
Wrap up reading in non-blocking mode.
static HAL_StatusTypeDef | MMC_ReadExtCSD (MMC_HandleTypeDef *hmmc, uint32_t *pBlockNbr, uint32_t Timeout)
Reads extended CSD register to get the sectors number of the device.
HAL_StatusTypeDef | HAL_MMC_Init (MMC_HandleTypeDef *hmmc)
Initializes the MMC according to the specified parameters in the MMC_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_MMC_InitCard (MMC_HandleTypeDef *hmmc)
Initializes the MMC Card.
HAL_StatusTypeDef | HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc)
De-Initializes the MMC card.
__weak void | HAL_MMC_MspInit (MMC_HandleTypeDef *hmmc)
Initializes the MMC MSP.
__weak void | HAL_MMC_MspDeInit (MMC_HandleTypeDef *hmmc)
De-Initialize MMC MSP.
HAL_StatusTypeDef | HAL_MMC_ReadBlocks (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_WriteBlocks (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Allows to write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_ReadBlocks_IT (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_WriteBlocks_IT (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_ReadBlocks_DMA (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_WriteBlocks_DMA (MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMC_Erase (MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
Erases the specified memory area of the given MMC card.
void | HAL_MMC_IRQHandler (MMC_HandleTypeDef *hmmc)
This function handles MMC card interrupt request.
HAL_MMC_StateTypeDef | HAL_MMC_GetState (MMC_HandleTypeDef *hmmc)
return the MMC state
uint32_t | HAL_MMC_GetError (MMC_HandleTypeDef *hmmc)
Return the MMC error code.
__weak void | HAL_MMC_TxCpltCallback (MMC_HandleTypeDef *hmmc)
Tx Transfer completed callbacks.
__weak void | HAL_MMC_RxCpltCallback (MMC_HandleTypeDef *hmmc)
Rx Transfer completed callbacks.
__weak void | HAL_MMC_ErrorCallback (MMC_HandleTypeDef *hmmc)
MMC error callbacks.
__weak void | HAL_MMC_AbortCallback (MMC_HandleTypeDef *hmmc)
MMC Abort callbacks.
HAL_StatusTypeDef | HAL_MMC_GetCardCID (MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypedef *pCID)
Returns information the information of the card which are stored on the CID register.
HAL_StatusTypeDef | HAL_MMC_GetCardCSD (MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
Returns information the information of the card which are stored on the CSD register.
HAL_StatusTypeDef | HAL_MMC_GetCardInfo (MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
Gets the MMC card info.
HAL_StatusTypeDef | HAL_MMC_ConfigWideBusOperation (MMC_HandleTypeDef *hmmc, uint32_t WideMode)
Enables wide bus operation for the requested card if supported by card.
HAL_MMC_CardStateTypedef | HAL_MMC_GetCardState (MMC_HandleTypeDef *hmmc)
Gets the current mmc card data state.
HAL_StatusTypeDef | HAL_MMC_Abort (MMC_HandleTypeDef *hmmc)
Abort the current transfer and disable the MMC.
HAL_StatusTypeDef | HAL_MMC_Abort_IT (MMC_HandleTypeDef *hmmc)
Abort the current transfer and disable the MMC (IT mode).
__weak void | HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback (MMC_HandleTypeDef *hmmc)
Read DMA Buffer 0 Transfer completed callbacks.
__weak void | HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback (MMC_HandleTypeDef *hmmc)
Read DMA Buffer 1 Transfer completed callbacks.
__weak void | HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback (MMC_HandleTypeDef *hmmc)
Write DMA Buffer 0 Transfer completed callbacks.
__weak void | HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback (MMC_HandleTypeDef *hmmc)
Write DMA Buffer 1 Transfer completed callbacks.

Detailed Description

MMC card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (MMC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + MMC card Control functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    This driver implements a high level communication layer for read and write from/to
    this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
    the user in HAL_MMC_MspInit() function (MSP layer).
    Basically, the MSP layer configuration should be the same as we provide in the
    examples.
    You can easily tailor this configuration according to hardware resources.

  [..]
    This driver is a generic layered driver for SDMMC memories which uses the HAL
    SDMMC driver functions to interface with MMC and eMMC cards devices.
    It is used as follows:

    (#)Initialize the SDMMC low level resources by implement the HAL_MMC_MspInit() API:
        (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
        (##) SDMMC pins configuration for MMC card
            (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
                  and according to your pin assignment;
        (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
            (+++) Configure the SDMMC interrupt priorities using functions HAL_NVIC_SetPriority();
            (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
            (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
                  and __HAL_MMC_DISABLE_IT() inside the communication process.
            (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT()
                  and __HAL_MMC_CLEAR_IT()
        (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC IP are used.

    (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization

  *** MMC Card Initialization and configuration ***
  ================================================
  [..]
    To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes
    SDMMC IP (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer).
    This function provide the following operations:

    (#) Initialize the SDMMC peripheral interface with defaullt configuration.
        The initialization process is done at 400KHz. You can change or adapt
        this frequency by adjusting the "ClockDiv" field.
        The MMC Card frequency (SDMMC_CK) is computed as follows:

           SDMMC_CK = SDMMCCLK / (2 * ClockDiv)

        In initialization mode and according to the MMC Card standard,
        make sure that the SDMMC_CK frequency doesn't exceed 400KHz.

        This phase of initialization is done through SDMMC_Init() and
        SDMMC_PowerState_ON() SDMMC low level APIs.

    (#) Initialize the MMC card. The API used is HAL_MMC_InitCard().
        This phase allows the card initialization and identification
        and check the MMC Card type (Standard Capacity or High Capacity)
        The initialization flow is compatible with MMC standard.

        This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case
        of plug-off plug-in.

    (#) Configure the MMC Card Data transfer frequency. By Default, the card transfer
        frequency by adjusting the "ClockDiv" field.
        In transfer mode and according to the MMC Card standard, make sure that the
        SDMMC_CK frequency doesn't exceed 25MHz and 100MHz in High-speed mode switch.

    (#) Select the corresponding MMC Card according to the address read with the step 2.

    (#) Configure the MMC Card in wide bus mode: 4-bits data.

  *** MMC Card Read operation ***
  ==============================
  [..]
    (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to ensure that the transfer is done correctly. The check is done
        through HAL_MMC_GetCardState() function for MMC card state.

    (+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.

  *** MMC Card Write operation ***
  ===============================
  [..]
    (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.

    (+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 byte).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.

  *** MMC card CID register ***
  ============================
  [..]
    (+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register.
        Some of the CID parameters are useful for card initialization and identification.

  *** MMC HAL driver macros list ***
  ==================================
  [..]
    Below the list of most used macros in MMC HAL driver.

    (+) __HAL_MMC_ENABLE_IT: Enable the MMC device interrupt
    (+) __HAL_MMC_DISABLE_IT: Disable the MMC device interrupt
    (+) __HAL_MMC_GET_FLAG:Check whether the specified MMC flag is set or not
    (+) __HAL_MMC_CLEAR_FLAG: Clear the MMC's pending flags

  [..]
    (@) You can refer to the MMC HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_mmc.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_mmc_ex.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Functions
stm32h7xx_hal_mmc_ex.c File Reference

MMC card Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (MMC) peripheral: + Extended features functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_MMCEx_ConfigDMAMultiBuffer (MMC_HandleTypeDef *hmmc, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, uint32_t BufferSize)
Configure DMA Dual Buffer mode.
HAL_StatusTypeDef | HAL_MMCEx_ReadBlocksDMAMultiBuffer (MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_MMCEx_WriteBlocksDMAMultiBuffer (MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_MMCEx_ChangeDMABuffer (MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
Change the DMA Buffer0 or Buffer1 address on the fly.

Detailed Description

MMC card Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (MMC) peripheral: + Extended features functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
   The MMC Extension HAL driver can be used as follows:
   (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_MMCEx_ConfigDMAMultiBuffer() function.

   (+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_mmc_ex.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_nand.c File Reference

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Functions
stm32h7xx_hal_nand.c File Reference

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_NAND_Init (NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
Perform NAND memory Initialization sequence.
HAL_StatusTypeDef | HAL_NAND_DeInit (NAND_HandleTypeDef *hnand)
Perform NAND memory De-Initialization sequence.
__weak void | HAL_NAND_MspInit (NAND_HandleTypeDef *hnand)
NAND MSP Init.
__weak void | HAL_NAND_MspDeInit (NAND_HandleTypeDef *hnand)
NAND MSP DeInit.
void | HAL_NAND_IRQHandler (NAND_HandleTypeDef *hnand)
This function handles NAND device interrupt request.
__weak void | HAL_NAND_ITCallback (NAND_HandleTypeDef *hnand)
NAND interrupt feature callback.
HAL_StatusTypeDef | HAL_NAND_Read_ID (NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
Read the NAND memory electronic signature.
HAL_StatusTypeDef | HAL_NAND_Reset (NAND_HandleTypeDef *hnand)
NAND memory reset.
HAL_StatusTypeDef | HAL_NAND_ConfigDevice (NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
Configure the device: Enter the physical parameters of the device.
HAL_StatusTypeDef | HAL_NAND_Read_Page_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
Read Page(s) from NAND memory block (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Read_Page_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
Read Page(s) from NAND memory block (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_Page_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
Write Page(s) to NAND memory block (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_Page_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
Write Page(s) to NAND memory block (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Read_SpareArea_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
Read Spare area(s) from NAND memory (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Read_SpareArea_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
Read Spare area(s) from NAND memory (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_SpareArea_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
Write Spare area(s) to NAND memory (8-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Write_SpareArea_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
Write Spare area(s) to NAND memory (16-bits addressing)
HAL_StatusTypeDef | HAL_NAND_Erase_Block (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
NAND memory Block erase.
uint32_t | HAL_NAND_Address_Inc (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
Increment the NAND memory address.
HAL_StatusTypeDef | HAL_NAND_ECC_Enable (NAND_HandleTypeDef *hnand)
Enables dynamically NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_ECC_Disable (NAND_HandleTypeDef *hnand)
Disables dynamically FMC_NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_GetECC (NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
Disables dynamically NAND ECC feature.
HAL_NAND_StateTypeDef | HAL_NAND_GetState (NAND_HandleTypeDef *hnand)
return the NAND state
uint32_t | HAL_NAND_Read_Status (NAND_HandleTypeDef *hnand)
NAND memory read status.

Detailed Description

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                         ##### How to use this driver #####
  ==============================================================================
    [..]
      This driver is a generic layered driver which contains a set of APIs used to
      control NAND flash memories. It uses the FMC/FSMC layer functions to interface
      with NAND devices. This driver is used as follows:

      (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
          with control and timing parameters for both common and attribute spaces.

      (+) Read NAND flash memory maker and device IDs using the function
          HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
          structure declared by the function caller.

      (+) Access NAND flash memory by read/write operations using the functions
          HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
          HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
          HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
          HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
          to read/write page(s)/spare area(s). These functions use specific device
          information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
          structure. The read/write address information is contained by the Nand_Address_Typedef
          structure passed as parameter.

      (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().

      (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
          The erase block address information is contained in the Nand_Address_Typedef
          structure passed as parameter.

      (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().

      (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
          HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
          feature or the function HAL_NAND_GetECC() to get the ECC correction code.

      (+) You can monitor the NAND device HAL state by calling the function
          HAL_NAND_GetState()

    [..]
      (@) This driver is a set of generic APIs which handle standard NAND flash operations.
          If a NAND flash device contains different operations and/or implementations,
          it should be implemented separately.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_nand.c.

Generated on Fri Apr 28 2017 15:42:41 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_nor.c File Reference

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Defines | Functions | Variables
stm32h7xx_hal_nor.c File Reference

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
#define | NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
#define | NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
#define | NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
#define | NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
#define | NOR_CMD_DATA_FIRST (uint16_t)0x00AA
#define | NOR_CMD_DATA_SECOND (uint16_t)0x0055
#define | NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
#define | NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
#define | NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
#define | NOR_CMD_DATA_CFI (uint16_t)0x0098
#define | NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
#define | NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
#define | NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
#define | NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
#define | NOR_MASK_STATUS_DQ6 (uint16_t)0x0040

Functions

HAL_StatusTypeDef | HAL_NOR_Init (NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Perform the NOR memory Initialization sequence.
HAL_StatusTypeDef | HAL_NOR_DeInit (NOR_HandleTypeDef *hnor)
Perform NOR memory De-Initialization sequence.
__weak void | HAL_NOR_MspInit (NOR_HandleTypeDef *hnor)
NOR MSP Init.
__weak void | HAL_NOR_MspDeInit (NOR_HandleTypeDef *hnor)
NOR MSP DeInit.
__weak void | HAL_NOR_MspWait (NOR_HandleTypeDef *hnor, uint32_t Timeout)
NOR MSP Wait for Ready/Busy signal.
HAL_StatusTypeDef | HAL_NOR_Read_ID (NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
Read NOR flash IDs.
HAL_StatusTypeDef | HAL_NOR_ReturnToReadMode (NOR_HandleTypeDef *hnor)
Returns the NOR memory to Read mode.
HAL_StatusTypeDef | HAL_NOR_Read (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Read data from NOR memory.
HAL_StatusTypeDef | HAL_NOR_Program (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Program data to NOR memory.
HAL_StatusTypeDef | HAL_NOR_ReadBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Reads a half-word buffer from the NOR memory.
HAL_StatusTypeDef | HAL_NOR_ProgramBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Writes a half-word buffer to the NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Block (NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
Erase the specified block of the NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Chip (NOR_HandleTypeDef *hnor, uint32_t Address)
Erase the entire NOR chip.
HAL_StatusTypeDef | HAL_NOR_Read_CFI (NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
Read NOR flash CFI IDs.
HAL_StatusTypeDef | HAL_NOR_WriteOperation_Enable (NOR_HandleTypeDef *hnor)
Enables dynamically NOR write operation.
HAL_StatusTypeDef | HAL_NOR_WriteOperation_Disable (NOR_HandleTypeDef *hnor)
Disables dynamically NOR write operation.
HAL_NOR_StateTypeDef | HAL_NOR_GetState (NOR_HandleTypeDef *hnor)
return the NOR controller state
HAL_NOR_StatusTypeDef | HAL_NOR_GetStatus (NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
Returns the NOR operation status.

Variables

static uint32_t | uwNORMemoryDataWidth = NOR_MEMORY_8B

Detailed Description

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      This driver is a generic layered driver which contains a set of APIs used to
      control NOR flash memories. It uses the FMC layer functions to interface
      with NOR devices. This driver is used as follows:

      (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
          with control and timing parameters for both normal and extended mode.

      (+) Read NOR flash memory manufacturer code and device IDs using the function
          HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
          structure declared by the function caller.

      (+) Access NOR flash memory by read/write data unit operations using the functions
          HAL_NOR_Read(), HAL_NOR_Program().

      (+) Perform NOR flash erase block/chip operations using the functions
          HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().

      (+) Read the NOR flash CFI (common flash interface) IDs using the function
          HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
          structure declared by the function caller.

      (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
          HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation

      (+) You can monitor the NOR device HAL state by calling the function
          HAL_NOR_GetState()
    [..]
     (@) This driver is a set of generic APIs which handle standard NOR flash operations.
         If a NOR flash device contains different operations and/or implementations,
         it should be implemented separately.

     *** NOR HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in NOR HAL driver.

      (+) NOR_WRITE : NOR memory write data to specified address
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_nor.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_opamp.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_opamp.c File Reference

OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s) peripheral: + OPAMP configuration + OPAMP calibration Thanks to + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | OPAMP_CSR_RESET_VALUE ((uint32_t)0x00000000)
#define | OPAMP_CSR_RESET_BITS
#define | OPAMP_CSR_INIT_MASK_PGA
#define | OPAMP_CSR_INIT_MASK_FOLLOWER
#define | OPAMP_CSR_INIT_MASK_STANDALONE

Functions

HAL_StatusTypeDef | HAL_OPAMP_Init (OPAMP_HandleTypeDef *hopamp)
Initialize the OPAMP according to the specified parameters in the OPAMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp)
DeInitialize the OPAMP peripheral.
__weak void | HAL_OPAMP_MspInit (OPAMP_HandleTypeDef *hopamp)
Initialize the OPAMP MSP.
__weak void | HAL_OPAMP_MspDeInit (OPAMP_HandleTypeDef *hopamp)
DeInitialize OPAMP MSP.
HAL_StatusTypeDef | HAL_OPAMP_Start (OPAMP_HandleTypeDef *hopamp)
Start the OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_Stop (OPAMP_HandleTypeDef *hopamp)
Stop the OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_SelfCalibrate (OPAMP_HandleTypeDef *hopamp)
Run the self calibration of one OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_Lock (OPAMP_HandleTypeDef *hopamp)
Lock the selected OPAMP configuration.
HAL_OPAMP_TrimmingValueTypeDef | HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
Return the OPAMP factory trimming value.
HAL_OPAMP_StateTypeDef | HAL_OPAMP_GetState (OPAMP_HandleTypeDef *hopamp)
Return the OPAMP handle state.

Detailed Description

OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s) peripheral: + OPAMP configuration + OPAMP calibration Thanks to + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
================================================================================
          ##### OPAMP Peripheral Features #####
================================================================================

  [..] The device integrates 2 operational amplifiers OPAMP1 & OPAMP2

       (#) The OPAMP(s) provides several exclusive running modes.
       (++) Standalone mode
       (++) Programmable Gain Amplifier (PGA) modes
       (++) Follower mode

       (#) Each OPAMP(s) can be configured in normal and high speed mode.

       (#) The OPAMP(s) provide(s) calibration capabilities.
       (++) Calibration aims at correcting some offset for running mode.
       (++) The OPAMP uses either factory calibration settings OR user defined
           calibration (trimming) settings (i.e. trimming mode).
       (++) The user defined settings can be figured out using self calibration
           handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
       (++) HAL_OPAMP_SelfCalibrate:
       (+++) Runs automatically the calibration in 2 steps.
            (90% of VDDA for NMOS transistors, 10% of VDDA for PMOS transistors).
            (As OPAMP is Rail-to-rail input/output, these 2 steps calibration is
             appropriate and enough in most cases).
       (+++) Runs automatically the calibration.
       (+++) Enables the user trimming mode
       (+++) Updates the init structure with trimming values with fresh calibration
            results.
            The user may store the calibration results for larger
            (ex monitoring the trimming as a function of temperature
            for instance)
       (+++) HAL_OPAMPEx_SelfCalibrateAll
            runs calibration of all OPAMPs in parallel to save search time.

       (#) Running mode: Standalone mode
       (++) Gain is set externally (gain depends on external loads).
       (++) Follower mode also possible externally by connecting the inverting input to
           the output.

       (#) Running mode: Follower mode
       (++) No Inverting Input is connected.

       (#) Running mode: Programmable Gain Amplifier (PGA) mode
           (Resistor feedback output)
       (#) The OPAMP(s) output(s) can be internally connected to resistor feedback
           output.
       (#) OPAMP gain can be selected as :

      (##) Gain of x2, x4, x8 or x16 for non inverting mode with:
      (+++) VREF- referenced.
      (+++) Filtering on VINM0, VREF- referenced.
      (+++) VINM0 node for bias voltage and VINP0 for input signal.
      (+++) VINM0 node for bias voltage and VINP0 for input signal, VINM1 node for filtering.

      (##) Gain of x-1, x-3, x-7 or x-15 for inverting mode with:
      (+++) VINM0 node for input signal and VINP0 for bias.
      (+++) VINM0 node for input signal and VINP0 for bias voltage, VINM1 node for filtering.

       (#) The OPAMPs inverting input can be selected according to the Reference Manual
           "OPAMP functional description" chapter.

       (#) The OPAMPs non inverting input can be selected according to the Reference Manual
           "OPAMP functional description" chapter.

            ##### How to use this driver #####
================================================================================
  [..]

    *** High speed / normal power mode ***
    ============================================
    [..]  To run in high speed mode:

      (#) Configure the OPAMP using HAL_OPAMP_Init() function:
      (++) Select OPAMP_POWERMODE_HIGHSPEED
      (++) Otherwise select OPAMP_POWERMODE_NORMAL

    *** Calibration ***
    ============================================
    [..]  To run the OPAMP calibration self calibration:

      (#) Start calibration using HAL_OPAMP_SelfCalibrate.
           Store the calibration results.

    *** Running mode ***
    ============================================

    [..]  To use the OPAMP, perform the following steps:

      (#) Fill in the HAL_OPAMP_MspInit() to
      (++) Enable the OPAMP Peripheral clock using macro __HAL_RCC_OPAMP_CLK_ENABLE()
      (++) Configure the OPAMP input AND output in analog mode using
           HAL_GPIO_Init() to map the OPAMP output to the GPIO pin.

      (#) Configure the OPAMP using HAL_OPAMP_Init() function:
      (++) Select the mode
      (++) Select the inverting input
      (++) Select the non-inverting input
      (++) If PGA mode is enabled, Select if inverting input is connected.
      (++) Select either factory or user defined trimming mode.
      (++) If the user-defined trimming mode is enabled, select PMOS & NMOS trimming values
          (typically values set by HAL_OPAMP_SelfCalibrate function).

      (#) Enable the OPAMP using HAL_OPAMP_Start() function.

      (#) Disable the OPAMP using HAL_OPAMP_Stop() function.

      (#) Lock the OPAMP in running mode using HAL_OPAMP_Lock() function.
          Caution: On STM32H7, HAL OPAMP lock is software lock only (not
          hardware lock as on some other STM32 devices)

      (#) If needed, unlock the OPAMP using HAL_OPAMPEx_Unlock() function.

    *** Running mode: change of configuration while OPAMP ON  ***
    ============================================
    [..] To Re-configure OPAMP when OPAMP is ON (change on the fly)
      (#) If needed, fill in the HAL_OPAMP_MspInit()
      (++) This is the case for instance if you wish to use new OPAMP I/O

      (#) Configure the OPAMP using HAL_OPAMP_Init() function:
      (++) As in configure case, select first the parameters you wish to modify.

      (#) Change from high speed mode to normal power mode (& vice versa) requires
          first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init().
          In other words, of OPAMP is ON, HAL_OPAMP_Init can NOT change power mode
          alone.

Table 1. OPAMPs inverting/non-inverting inputs for the STM32H7 devices:

+------------------------------------------------------------------------| | | | OPAMP1 | OPAMP2 | |-----------------|---------|----------------------|---------------------| | Inverting Input | VM_SEL | VINM0-> PC5 | VINM0-> PE8 | | | | VINM1-> PA7 | VINM1-> PG1 | | | | Internal: | Internal: | | | | ADC1_IN9 | OPAMP2_OUT | | | | ADC2_IN9 | PGA mode | | | | OPAMP1_OUT | | | | | PGA mode | | |-----------------|---------|----------------------|---------------------| | Non Inverting | VP_SEL | | | | | | VP0 -> PB0 (GPIO) | VP0 -> PE9 (GPIO) | | | | Internal: | Internal: | | Input | | DAC1_int | DAC2_int | | | | ADC1_IN8 | COMP2_INP | | | | ADC2_IN8 | | | | | COMP1_INP | | +------------------------------------------------------------------------|

[..] Table 2. OPAMPs outputs for the STM32H7 devices:

+------------------------------------------------------------------------- | | | OPAMP1 | OPAMP2 | |-----------------|--------|-----------------------|---------------------| | Output | VOUT | PC4 | PE7 | | | | & ADC1_IN4| | & COMP2_INN7 if | | | | ADC2_IN4 |connected internally | | | | COMP1_INN7 if | | | | | connected internally | | |-----------------|--------|-----------------------|---------------------|

Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_opamp.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_opamp_ex.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32H7xx_HAL_Driver
  • Src
Functions
stm32h7xx_hal_opamp_ex.c File Reference

Extended OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions. More...

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_OPAMPEx_Unlock (OPAMP_HandleTypeDef *hopamp)
Unlock the selected OPAMP configuration.
HAL_StatusTypeDef | HAL_OPAMPEx_SelfCalibrateAll (OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
Run the self calibration of 2 OPAMPs in parallel.

Detailed Description

Extended OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"

/** @addtogroup STM32H7xx_HAL_Driver
  * @{
  */

/** @defgroup OPAMPEx OPAMPEx
  * @brief OPAMP Extended HAL module driver
  * @{
  */

#ifdef HAL_OPAMP_MODULE_ENABLED

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/

/** @defgroup OPAMPEx_Exported_Functions OPAMP Extended Exported Functions
  * @{
  */

/** @defgroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
  * @brief    Extended operation functions
  *
@verbatim
 ===============================================================================
              ##### Extended IO operation functions #####
 ===============================================================================
  [..]
      (+) OPAMP Self calibration.

Definition in file stm32h7xx_hal_opamp_ex.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_pcd.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_pcd.c File Reference

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define | PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))

Functions

static HAL_StatusTypeDef | PCD_WriteEmptyTxFifo (PCD_HandleTypeDef *hpcd, uint32_t epnum)
DCD_WriteEmptyTxFifo check FIFO for the next packet to be loaded.
HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start The USB OTG Device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop The USB OTG Device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
This function handles PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data out stage callbacks.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callbacks.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callbacks.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callbacks.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callbacks.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callbacks.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callbacks.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callbacks.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callbacks.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callbacks.
HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
uint16_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
HAL_PCD_ActivateRemoteWakeup : Active remote wake-up signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
HAL_PCD_DeActivateRemoteWakeup : de-active remote wake-up signalling.
PCD_StateTypeDef | HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD state.

Detailed Description

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
    [..]
      The PCD HAL driver can be used as follows:

     (#) Declare a PCD_HandleTypeDef handle structure, for example:
         PCD_HandleTypeDef  hpcd;

     (#) Fill parameters of Init structure in HCD handle

     (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...)

     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
         (##) Enable the PCD/USB Low Level interface clock using
              (+++) __OTGFS-OTG_CLK_ENABLE()/__OTGHS-OTG_CLK_ENABLE();
              (+++) __OTGHSULPI_CLK_ENABLE(); (For High Speed Mode)

         (##) Initialize the related GPIO clocks
         (##) Configure PCD pin-out
         (##) Configure PCD NVIC interrupt

     (#)Associate the Upper USB device stack to the HAL PCD Driver:
         (##) hpcd.pData = pdev;

     (#)Enable HCD transmission and reception:
         (##) HAL_PCD_Start();
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_pcd.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_pcd_ex.c File Reference

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Functions
stm32h7xx_hal_pcd_ex.c File Reference

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_PCDEx_SetTxFiFo (PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
Set Tx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_SetRxFiFo (PCD_HandleTypeDef *hpcd, uint16_t size)
Set Rx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_ActivateLPM (PCD_HandleTypeDef *hpcd)
HAL_PCDEx_ActivateLPM : active LPM Feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateLPM (PCD_HandleTypeDef *hpcd)
HAL_PCDEx_DeActivateLPM : de-active LPM feature.
void | HAL_PCDEx_BCD_VBUSDetect (PCD_HandleTypeDef *hpcd)
Handle BatteryCharging Process.
HAL_StatusTypeDef | HAL_PCDEx_ActivateBCD (PCD_HandleTypeDef *hpcd)
Activate BatteryCharging feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateBCD (PCD_HandleTypeDef *hpcd)
Deactivate BatteryCharging feature.
__weak void | HAL_PCDEx_LPM_Callback (PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
Send LPM message to user layer callback.
__weak void | HAL_PCDEx_BCD_Callback (PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
Send BatteryCharging message to user layer callback.

Detailed Description

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_pcd_ex.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_pwr.c File Reference

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Defines | Functions
stm32h7xx_hal_pwr.c File Reference

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | PVD_MODE_IT ((uint32_t)0x00010000U)
#define | PVD_MODE_EVT ((uint32_t)0x00020000U)
#define | PVD_RISING_EDGE ((uint32_t)0x00000001U)
#define | PVD_FALLING_EDGE ((uint32_t)0x00000002U)
#define | PVD_RISING_FALLING_EDGE ((uint32_t)0x00000003U)

Functions

void | HAL_PWR_DeInit (void)
Deinitialize the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configure the voltage threshold detected by the Power Voltage Detector(PVD).
void | HAL_PWR_EnablePVD (void)
Enable the Power Voltage Detector(PVD).
void | HAL_PWR_DisablePVD (void)
Disable the Power Voltage Detector(PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
Enable the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disable the WakeUp PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enter CM7 core to Sleep mode.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enter the system to STOP mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enter the system to STANDBY mode.
void | HAL_PWR_EnableSleepOnExit (void)
Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enable CORTEX SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disable CORTEX SEVONPEND bit.
void | HAL_PWR_PVD_IRQHandler (void)
This function handles the PWR PVD interrupt request.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.

Detailed Description

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_pwr.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_pwr_ex.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_pwr_ex.c File Reference

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of PWR extension peripheral: + Peripheral Extended features functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | AVD_MODE_IT ((uint32_t)0x00010000U)
#define | AVD_MODE_EVT ((uint32_t)0x00020000U)
#define | AVD_RISING_EDGE ((uint32_t)0x00000001U)
#define | AVD_FALLING_EDGE ((uint32_t)0x00000002U)
#define | AVD_RISING_FALLING_EDGE ((uint32_t)0x00000003U)
#define | PWR_FLAG_SETTING_DELAY_US ((uint32_t)1000U)

Functions

HAL_StatusTypeDef | HAL_PWREx_ConfigSupply (uint32_t SupplySource)
Configure the system Power Supply.
uint32_t | HAL_PWREx_GetSupplyConfig (void)
Get the power supply configuration.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configure the main internal regulator output voltage.
uint32_t | HAL_PWREx_GetVoltageRange (void)
Get the main internal regulator output voltage.
HAL_StatusTypeDef | HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling)
Configure the main internal regulator output voltage in STOP mode.
uint32_t | HAL_PWREx_GetStopModeVoltageRange (void)
Get the main internal regulator output voltage in STOP mode.
void | HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain)
Enter a Domain to DSTOP mode.
void | HAL_PWREx_EnterSTANDBYMode (uint32_t Domain)
Enter a Domain to DSTANDBY mode.
void | HAL_PWREx_ConfigD3Domain (uint32_t D3State)
Configure the D3 Domain state when the CPU is in low power mode.
void | HAL_PWREx_EnableFlashPowerDown (void)
Enable the Flash Power Down in Stop mode.
void | HAL_PWREx_DisableFlashPowerDown (void)
Disable the Flash Power Down in Stop mode.
void | HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams)
Enable the Wake-up PINx functionality.
void | HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the Wake-up PINx functionality.
uint32_t | HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag)
Get the Wake-Up Pin flag.
HAL_StatusTypeDef | HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag)
Clear the Wake-Up pin flag.
void | HAL_PWREx_WAKEUP_PIN_IRQHandler (void)
This function handles the PWR WAKEUP PIN interrupt request.
__weak void | HAL_PWREx_WKUP1_Callback (void)
PWR WKUP1 interrupt callback.
__weak void | HAL_PWREx_WKUP2_Callback (void)
PWR WKUP2 interrupt callback.
__weak void | HAL_PWREx_WKUP3_Callback (void)
PWR WKUP3 interrupt callback.
__weak void | HAL_PWREx_WKUP4_Callback (void)
PWR WKUP4 interrupt callback.
__weak void | HAL_PWREx_WKUP5_Callback (void)
PWR WKUP5 interrupt callback.
__weak void | HAL_PWREx_WKUP6_Callback (void)
PWR WKUP6 interrupt callback.
HAL_StatusTypeDef | HAL_PWREx_EnableBkUpReg (void)
Enable the Backup Regulator.
HAL_StatusTypeDef | HAL_PWREx_DisableBkUpReg (void)
Disable the Backup Regulator.
HAL_StatusTypeDef | HAL_PWREx_EnableUSBReg (void)
Enable the USB Regulator.
HAL_StatusTypeDef | HAL_PWREx_DisableUSBReg (void)
Disable the USB Regulator.
void | HAL_PWREx_EnableUSBVoltageDetector (void)
Enable the USB voltage level detector.
void | HAL_PWREx_DisableUSBVoltageDetector (void)
Disable the USB voltage level detector.
void | HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue)
Enable the Battery charging.
void | HAL_PWREx_DisableBatteryCharging (void)
Disable the Battery charging.
void | HAL_PWREx_EnableMonitoring (void)
Enable the VBAT and temperature monitoring.
void | HAL_PWREx_DisableMonitoring (void)
Disable the VBAT and temperature monitoring.
uint32_t | HAL_PWREx_GetTemperatureLevel (void)
Indicate whether the junction temperature is between, above or below the threshold.
uint32_t | HAL_PWREx_GetVBATLevel (void)
Indicate whether the Battery voltage level is between, above or below the threshold.
void | HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD)
Configure the analog voltage threshold detected by the Analog Voltage Detector(AVD).
void | HAL_PWREx_EnableAVD (void)
Enable the Analog Voltage Detector(AVD).
void | HAL_PWREx_DisableAVD (void)
Disable the Analog Voltage Detector(AVD).
void | HAL_PWREx_PVD_AVD_IRQHandler (void)
This function handles the PWR PVD/AVD interrupt request.
__weak void | HAL_PWREx_AVDCallback (void)
PWR AVD interrupt callback.

Detailed Description

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of PWR extension peripheral: + Peripheral Extended features functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_pwr_ex.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_qspi.c File Reference

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Defines | Functions
stm32h7xx_hal_qspi.c File Reference

QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + MDMA channel configuration for indirect functional mode + Errors management and abort functionality. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000)
#define | QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0)
#define | QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1)
#define | QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE)
#define | IS_QSPI_FUNCTIONAL_MODE(MODE)

Functions

static void | QSPI_DMARxCplt (MDMA_HandleTypeDef *hmdma)
DMA QSPI receive process complete callback.
static void | QSPI_DMATxCplt (MDMA_HandleTypeDef *hmdma)
DMA QSPI transmit process complete callback.
static void | QSPI_DMAError (MDMA_HandleTypeDef *hmdma)
DMA QSPI communication error callback.
static void | QSPI_DMAAbortCplt (MDMA_HandleTypeDef *hmdma)
MDMA QSPI abort complete callback.
static HAL_StatusTypeDef | QSPI_WaitFlagStateUntilTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t tickstart, uint32_t Timeout)
Wait for a flag state until timeout.
static void | QSPI_Config (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
Configure the communication registers.
HAL_StatusTypeDef | HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI mode according to the specified parameters in the QSPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi)
De-Initialize the QSPI peripheral.
__weak void | HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI MSP.
__weak void | HAL_QSPI_MspDeInit (QSPI_HandleTypeDef *hqspi)
DeInitialize the QSPI MSP.
void | HAL_QSPI_IRQHandler (QSPI_HandleTypeDef *hqspi)
Handle QSPI interrupt request.
HAL_StatusTypeDef | HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
Set the command configuration.
HAL_StatusTypeDef | HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
Set the command configuration in interrupt mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
Configure the QSPI Automatic Polling Mode in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
Configure the QSPI Automatic Polling Mode in non-blocking mode.
HAL_StatusTypeDef | HAL_QSPI_MemoryMapped (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
Configure the Memory Mapped mode.
__weak void | HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi)
Transfer Error callback.
__weak void | HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi)
Abort completed callback.
__weak void | HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi)
Command completed callback.
__weak void | HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Transfer completed callback.
__weak void | HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Transfer completed callback.
__weak void | HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Half Transfer completed callback.
__weak void | HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Half Transfer completed callback.
__weak void | HAL_QSPI_FifoThresholdCallback (QSPI_HandleTypeDef *hqspi)
FIFO Threshold callback.
__weak void | HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi)
Status Match callback.
__weak void | HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi)
Timeout callback.
HAL_QSPI_StateTypeDef | HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi)
Return the QSPI handle state.
uint32_t | HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi)
Return the QSPI error code.
HAL_StatusTypeDef | HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi)
Abort the current transmission.
HAL_StatusTypeDef | HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi)
Abort the current transmission (non-blocking function)
void | HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
Set QSPI timeout.
HAL_StatusTypeDef | HAL_QSPI_SetFifoThreshold (QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
Set QSPI Fifo threshold.
uint32_t | HAL_QSPI_GetFifoThreshold (QSPI_HandleTypeDef *hqspi)
Get QSPI Fifo threshold.

Detailed Description

QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + MDMA channel configuration for indirect functional mode + Errors management and abort functionality.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
  [..]
    *** Initialization ***
    ======================
    [..]
      (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
        (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
        (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
        (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
        (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
        (++) If interrupt mode is used, enable and configure QuadSPI global
            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
        (++) If DMA mode is used, enable the clocks for the QuadSPI MDMA
            with __HAL_RCC_MDMA_CLK_ENABLE(), configure MDMA with HAL_MDMA_Init(),
            link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
            MDMA global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
      (#) Configure the flash size, the clock prescaler, the fifo threshold, the
          clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.

    *** Indirect functional mode ***
    ================================
    [..]
      (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
          functions :
         (++) Instruction phase : the mode used and if present the instruction opcode.
         (++) Address phase : the mode used and if present the size and the address value.
         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
             bytes values.
         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (++) Data phase : the mode used and if present the number of bytes.
         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
             if activated.
         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
      (#) If no data is required for the command, it is sent directly to the memory :
         (++) In polling mode, the output of the function is done when the transfer is complete.
         (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
      (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
          HAL_QSPI_Transmit_IT() after the command configuration :
         (++) In polling mode, the output of the function is done when the transfer is complete.
         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
             is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
         (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
             HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
      (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
          HAL_QSPI_Receive_IT() after the command configuration :
         (++) In polling mode, the output of the function is done when the transfer is complete.
         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
             is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
         (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
             HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.

    *** Auto-polling functional mode ***
    ====================================
    [..]
      (#) Configure the command sequence and the auto-polling functional mode using the
          HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
         (++) Instruction phase : the mode used and if present the instruction opcode.
         (++) Address phase : the mode used and if present the size and the address value.
         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
             bytes values.
         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (++) Data phase : the mode used.
         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
             if activated.
         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
         (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
             the polling interval and the automatic stop activation.
      (#) After the configuration :
         (++) In polling mode, the output of the function is done when the status match is reached. The
             automatic stop is activated to avoid an infinite loop.
         (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.

    *** Memory-mapped functional mode ***
    =====================================
    [..]
      (#) Configure the command sequence and the memory-mapped functional mode using the
          HAL_QSPI_MemoryMapped() functions :
         (++) Instruction phase : the mode used and if present the instruction opcode.
         (++) Address phase : the mode used and the size.
         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
             bytes values.
         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (++) Data phase : the mode used.
         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
             if activated.
         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
         (++) The timeout activation and the timeout period.
      (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
          the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.

    *** Errors management and abort functionality ***
    =================================================
    [..]
      (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
      (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
          flushes the fifo :
         (++) In polling mode, the output of the function is done when the transfer
              complete bit is set and the busy bit cleared.
         (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
              the transfer complete bi is set.

    *** Control functions ***
    =========================
    [..]
      (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
      (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
      (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
      (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold

    *** Workarounds linked to Silicon Limitation ***
    ====================================================
    [..]
      (#) Workarounds Implemented inside HAL Driver
         (++) Extra data written in the FIFO at the end of a read transfer
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_qspi.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_rcc.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_rcc.c File Reference

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO1_GPIO_PORT GPIOA
#define | MCO1_PIN GPIO_PIN_8
#define | __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define | MCO2_GPIO_PORT GPIOC
#define | MCO2_PIN GPIO_PIN_9

Functions

void | HAL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
__weak HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initializes the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.
void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
void | HAL_RCC_EnableCSS (void)
Enables the Clock Security System.
uint32_t | HAL_RCC_GetSysClockFreq (void)
Returns the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Returns the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Returns the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Returns the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
This function handles the RCC CSS interrupt request.
__weak void | HAL_RCC_CCSCallback (void)
RCC Clock Security System interrupt callback.

Detailed Description

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                      ##### RCC specific features #####
  ==============================================================================
    [..]
      After reset the device is running from Internal High Speed oscillator
      (HSI 64MHz) with Flash 0 wait state,and all peripherals are off except
      internal SRAM, Flash, JTAG and PWR
      (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses;
          all peripherals mapped on these buses are running at HSI speed.
      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
      (+) All GPIOs are in analogue mode , except the JTAG pins which
          are assigned to be used for debug purpose.

    [..]
      Once the device started from reset, the user application has to:
      (+) Configure the clock source to be used to drive the System clock
          (if the application needs higher frequency/performance)
      (+) Configure the System clock frequency and Flash settings
      (+) Configure the AHB and APB buses pre-scalers
      (+) Enable the clock for the peripheral(s) to be used
      (+) Configure the clock kernel source(s) for peripherals which clocks are not
          derived from the System clock through :RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R
          and RCC_D3CCIPR registers

                      ##### RCC Limitations #####
  ==============================================================================
    [..]
      A delay between an RCC peripheral clock enable and the effective peripheral
      enabling should be taken into account in order to manage the peripheral read/write
      from/to registers.
      (+) This delay depends on the peripheral mapping.
      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
          after the clock enable bit is set on the hardware register
      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
          after the clock enable bit is set on the hardware register

    [..]
      Implemented Workaround:
      (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_rcc.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_rcc_ex.c File Reference

  • File List
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Defines | Functions
stm32h7xx_hal_rcc_ex.c File Reference

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | PLL2_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define | PLL3_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define | PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */

Functions

static HAL_StatusTypeDef | RCCEx_PLL2_Config (RCC_PLL2InitTypeDef *pll2)
Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it.
static HAL_StatusTypeDef | RCCEx_PLL3_Config (RCC_PLL3InitTypeDef *pll3)
Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it.
HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Return the peripheral clock frequency for a given peripheral(SAI..)
uint32_t | HAL_RCCEx_GetD1PCLK1Freq (void)
Returns the D1PCLK1 frequency.
uint32_t | HAL_RCCEx_GetD3PCLK1Freq (void)
Returns the D3PCLK1 frequency.
void | HAL_RCCEx_GetPLL2ClockFreq (PLL2_ClocksTypeDef *PLL2_Clocks)
Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency.
void | HAL_RCCEx_GetPLL3ClockFreq (PLL3_ClocksTypeDef *PLL3_Clocks)
Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency.
void | HAL_RCCEx_GetPLL1ClockFreq (PLL1_ClocksTypeDef *PLL1_Clocks)
Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency.
uint32_t | HAL_RCCEx_GetD1SysClockFreq (void)
Returns the main Core frequency.
void | HAL_RCCEx_EnableLSECSS (void)
Enables the LSE Clock Security System.
void | HAL_RCCEx_DisableLSECSS (void)
Disables the LSE Clock Security System.
void | HAL_RCCEx_WakeUpStopCLKConfig (uint32_t WakeUpClk)
Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
void | HAL_RCCEx_KerWakeUpStopCLKConfig (uint32_t WakeUpClk)
Configure the oscillator Kernel clock source for wakeup from Stop.
void | HAL_RCCEx_WWDGxSysResetConfig (uint32_t RCC_WWDGx)
Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs.
void | HAL_RCCEx_CRSConfig (RCC_CRSInitTypeDef *pInit)
Start automatic synchronization for polling mode.
void | HAL_RCCEx_CRSSoftwareSynchronizationGenerate (void)
Generate the software synchronization event.
void | HAL_RCCEx_CRSGetSynchronizationInfo (RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
Return synchronization info.
uint32_t | HAL_RCCEx_CRSWaitSynchronization (uint32_t Timeout)
Wait for CRS Synchronization status.
void | HAL_RCCEx_CRS_IRQHandler (void)
Handle the Clock Recovery System interrupt request.
__weak void | HAL_RCCEx_CRS_SyncOkCallback (void)
RCCEx Clock Recovery System SYNCOK interrupt callback.
__weak void | HAL_RCCEx_CRS_SyncWarnCallback (void)
RCCEx Clock Recovery System SYNCWARN interrupt callback.
__weak void | HAL_RCCEx_CRS_ExpectedSyncCallback (void)
RCCEx Clock Recovery System Expected SYNC interrupt callback.
__weak void | HAL_RCCEx_CRS_ErrorCallback (uint32_t Error)
RCCEx Clock Recovery System Error interrupt callback.

Detailed Description

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_rcc_ex.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_rng.c File Reference

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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_rng.c File Reference

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization/de-initialization functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | RNG_TIMEOUT_VALUE 2U

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initializes the RNG peripheral and creates the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initializes the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG MSP.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generates a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generates a 32-bit random number in interrupt mode.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handles RNG interrupt request.
uint32_t | HAL_RNG_ReadLastRandomNumber (RNG_HandleTypeDef *hrng)
Read latest generated random number.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callbacks.
HAL_RNG_StateTypeDef | HAL_RNG_GetState (RNG_HandleTypeDef *hrng)
Returns the RNG state.

Detailed Description

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization/de-initialization functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
  [..]
      The RNG HAL driver can be used as follows:

      (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
          in HAL_RNG_MspInit().
      (#) Activate the RNG peripheral using HAL_RNG_Init() function.
      (#) Wait until the 32 bit Random Number Generator contains a valid
          random data using (polling/interrupt) mode.
      (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_rng.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_rtc.c File Reference

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  • STM32H7xx_HAL_Driver
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Functions
stm32h7xx_hal_rtc.c File Reference

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initialize the RTC according to the specified parameters in the RTC_InitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC peripheral.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initialize the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC MSP.
HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Set RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Get RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Set RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Get RTC current date.
HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Get the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Alarm interrupt request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle AlarmA Polling request.
HAL_StatusTypeDef | HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.
HAL_RTCStateTypeDef | HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Return the RTC handle state.
HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enter the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.

Detailed Description

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
 ===============================================================================
                          ##### RTC Operating Condition #####
 ===============================================================================
  [..] The real-time clock (RTC) and the RTC backup registers can be powered
       from the VBAT voltage when the main VDD supply is powered off.
       To retain the content of the RTC backup registers and supply the RTC
       when VDD is turned off, VBAT pin can be connected to an optional
       standby voltage supplied by a battery or by another source.

                   ##### Backup Domain Reset #####
 ===============================================================================
  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
       to their reset values.
       A backup domain reset is generated when one of the following events occurs:
    (#) Software reset, triggered by setting the BDRST bit in the
        RCC Backup domain control register (RCC_BDCR).
    (#) VDD or VBAT power on, if both supplies have previously been powered off.
    (#) Tamper detection event resets all data backup registers.

                   ##### Backup Domain Access #####
 ===================================================================
  [..] After reset, the backup domain (RTC registers, RTC backup data
       registers and backup SRAM) is protected against possible unwanted write
       accesses.

  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
    (#) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for
        PeriphClockSelection and select RTCClockSelection (LSE, LSI or any HSE divider)
    (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro.

                  ##### How to use RTC Driver #####
 ===================================================================
  [..]
    (#) Enable the RTC domain access (see description in the section above).
    (#) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
        format using the HAL_RTC_Init() function.

  *** Time and Date configuration ***
  ===================================
  [..]
    (#) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
        and HAL_RTC_SetDate() functions.
    (#) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.

  *** Alarm configuration ***
  ===========================
  [..]
    (#) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
            You can also configure the RTC Alarm with interrupt mode using the
            HAL_RTC_SetAlarm_IT() function.
    (#) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.

                  ##### RTC and low power modes #####
 ===================================================================
  [..] The MCU can be woken up from a low power mode by an RTC alternate
       function.
  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
       RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
       These RTC alternate functions can wake up the system from the Stop and Standby low power
       modes.
  [..] The system can also wake up from low power modes without depending
       on an external interrupt (Auto-wakeup mode), by using the RTC alarm
       or the RTC wakeup events.
  [..] The RTC provides a programmable time base for waking up from the
       Stop or Standby mode at regular intervals.
       Wakeup from STOP and Standby modes is possible only when the RTC clock source
       is LSE or LSI.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_rtc.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_rtc_ex.c File Reference

  • File List
  • Globals
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  • STM32H7xx_HAL_Driver
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Functions
stm32h7xx_hal_rtc_ex.c File Reference

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Set Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Get the RTC TimeStamp value.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivate Tamper.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
Handle TimeStamp interrupt request.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper2 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper3Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper3 Polling.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer with interrupt.
uint32_t | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivate wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Get wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Wake Up Timer Polling.
void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Write a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Read data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
Set the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configure the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disable the Bypass Shadow feature.
__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Alarm B Polling request.

Detailed Description

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                  ##### How to use this driver #####
  ==============================================================================
  [..]
    (+) Enable the RTC domain access.
    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
        format using the HAL_RTC_Init() function.

  *** RTC Wakeup configuration ***
  ================================
  [..]
    (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
        function. You can also configure the RTC Wakeup timer with interrupt mode
        using the HAL_RTCEx_SetWakeUpTimer_IT() function.
    (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
        function.

  *** Outputs configuration ***
  =============================
  [..]  The RTC has 2 different outputs:
    (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B
        and WaKeUp signals.
        To output the selected RTC signal, use the HAL_RTC_Init() function.
    (+) RTC_CALIB: this output is 512Hz signal or 1Hz.
        To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
    (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on
        the RTC_OR register.
    (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
        automatically configured in output alternate function.

  *** Smooth digital Calibration configuration ***
  ================================================
  [..]
    (+) Configure the RTC Original Digital Calibration Value and the corresponding
        calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib()
        function.

  *** TimeStamp configuration ***
  ===============================
  [..]
    (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function.
        You can also configure the RTC TimeStamp with interrupt mode using the
        HAL_RTCEx_SetTimeStamp_IT() function.
    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
        function.

  *** Internal TimeStamp configuration ***
  ===============================
  [..]
    (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function.
        User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG.
    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
        function.

  *** Tamper configuration ***
  ============================
  [..]
    (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
        or Level according to the Tamper filter (if equal to 0 Edge else Level)
        value, sampling frequency, NoErase, MaskFlag,  precharge or discharge and
        Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper
        with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
    (+) The default configuration of the Tamper erases the backup registers. To avoid
        erase, enable the NoErase field on the RTC_TAMPCR register.

  *** Backup Data Registers configuration ***
  ===========================================
  [..]
    (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
        function.
    (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
        function.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_rtc_ex.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sai.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Enumerations | Functions
stm32h7xx_hal_sai.c File Reference

SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | SAI_FIFO_SIZE 8U
#define | SAI_DEFAULT_TIMEOUT 4U /* 4ms */
#define | SAI_LONG_TIMEOUT 1000U
#define | SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT)
#define | SAI_PDMCR_MICNBR_OFFSET POSITION_VAL(SAI_PDMCR_MICNBR)

Enumerations

enum | SAI_ModeTypedef { SAI_MODE_DMA, SAI_MODE_IT }

Functions

static void | SAI_FillFifo (SAI_HandleTypeDef *hsai)
Fill the fifo.
static uint32_t | SAI_InterruptFlag (SAI_HandleTypeDef *hsai, uint32_t mode)
Return the interrupt flag to set according the SAI setup.
static HAL_StatusTypeDef | SAI_InitI2S (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the SAI I2S protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_InitPCM (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the SAI PCM protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_Disable (SAI_HandleTypeDef *hsai)
Disable the SAI and wait for the disabling.
static void | SAI_Transmit_IT8Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
static void | SAI_Transmit_IT16Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
static void | SAI_Transmit_IT32Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
static void | SAI_Receive_IT8Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode 8-Bit transfer.
static void | SAI_Receive_IT16Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
static void | SAI_Receive_IT32Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
static void | SAI_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process complete callback.
static void | SAI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process half complete callback.
static void | SAI_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process complete callback.
static void | SAI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process half complete callback.
static void | SAI_DMAError (DMA_HandleTypeDef *hdma)
DMA SAI communication error callback.
static void | SAI_DMAAbort (DMA_HandleTypeDef *hdma)
DMA SAI Abort callback.
HAL_StatusTypeDef | HAL_SAI_InitProtocol (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.
HAL_StatusTypeDef | HAL_SAI_Init (SAI_HandleTypeDef *hsai)
Initialize the SAI according to the specified parameters.
HAL_StatusTypeDef | HAL_SAI_DeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI peripheral.
__weak void | HAL_SAI_MspInit (SAI_HandleTypeDef *hsai)
Initialize the SAI MSP.
__weak void | HAL_SAI_MspDeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI MSP.
HAL_StatusTypeDef | HAL_SAI_Transmit (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Receive (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Transmit_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Receive_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_DMAPause (SAI_HandleTypeDef *hsai)
Pause the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAResume (SAI_HandleTypeDef *hsai)
Resume the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAStop (SAI_HandleTypeDef *hsai)
Stop the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_Abort (SAI_HandleTypeDef *hsai)
Abort the current transfer and disable the SAI.
HAL_StatusTypeDef | HAL_SAI_Transmit_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_Receive_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_EnableTxMuteMode (SAI_HandleTypeDef *hsai, uint16_t val)
Enable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_DisableTxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_EnableRxMuteMode (SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
Enable the Rx mute detection.
HAL_StatusTypeDef | HAL_SAI_DisableRxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Rx mute detection.
void | HAL_SAI_IRQHandler (SAI_HandleTypeDef *hsai)
Handle SAI interrupt request.
__weak void | HAL_SAI_TxCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer completed callback.
__weak void | HAL_SAI_TxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer Half completed callback.
__weak void | HAL_SAI_RxCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer completed callback.
__weak void | HAL_SAI_RxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer half completed callback.
__weak void | HAL_SAI_ErrorCallback (SAI_HandleTypeDef *hsai)
SAI error callback.
HAL_SAI_StateTypeDef | HAL_SAI_GetState (SAI_HandleTypeDef *hsai)
Return the SAI handle state.
uint32_t | HAL_SAI_GetError (SAI_HandleTypeDef *hsai)
Return the SAI error code.

Detailed Description

SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                  ##### How to use this driver #####
  ==============================================================================

  [..]
    The SAI HAL driver can be used as follows:

    (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai).
    (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
        (##) Enable the SAI interface clock.
        (##) SAI pins configuration:
            (+++) Enable the clock for the SAI GPIOs.
            (+++) Configure these SAI pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()
             and HAL_SAI_Receive_IT() APIs):
            (+++) Configure the SAI interrupt priority.
            (+++) Enable the NVIC SAI IRQ handle.

        (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()
             and HAL_SAI_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx stream.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Stream.
            (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
                DMA Tx/Rx Stream.

    (#) The initialization can be done by two ways
        (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init().
        (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol().

  [..]
    (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
        will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT()
        inside the transmit and receive process.
  [..]
    (@) Make sure that either:
        (+@) PLLSAI1CLK output is configured or
        (+@) PLLSAI2CLK output is configured or
        (+@) PLLSAI3CLK output is configured or
    (+@) PLLSAI4ACLK output is configured or
    (+@) PLLSAI4BCLK output is configured or
    (+@) External clock source is configured after setting correctly
             the define constant EXTERNAL_CLOCK_VALUE in the stm32h7xx_hal_conf.h file.

  [..]
    (@) In master Tx mode: enabling the audio block immediately generates the bit clock
        for the external slaves even if there is no data in the FIFO, However FS signal
        generation is conditioned by the presence of data in the FIFO.

  [..]
    (@) In master Rx mode: enabling the audio block immediately generates the bit clock
        and FS signal for the external slaves.

  [..]
    (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
        (+@) First bit Offset <= (SLOT size - Data size)
        (+@) Data size <= SLOT size
        (+@) Number of SLOT x SLOT size = Frame length
        (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.

  [..]
    (@) PDM interface can be activated through HAL_SAI_Init function.
        Please note that PDM interface is only available for SAIx sub-block A.
        PDM microphone delays can be tuned with HAL_SAIEx_ConfigPdmMicDelay function.

  [..]
    Three operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()
      (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT()
      (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
      (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT()
      (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
      (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
          add his own code by customization of function pointer HAL_SAI_ErrorCallback()

    *** DMA mode IO operation ***
    =============================
    [..]
      (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA()
      (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
      (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA()
      (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
      (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
          add his own code by customization of function pointer HAL_SAI_ErrorCallback()
      (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
      (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
      (+) Stop the DMA Transfer using HAL_SAI_DMAStop()

    *** SAI HAL driver additional function list ***
    ===============================================
    [..]
      Below the list the others API available SAI HAL driver :

      (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode
      (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode
      (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode
      (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode
      (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo.
      (+) HAL_SAI_Abort(): Abort the current transfer

    *** SAI HAL driver macros list ***
    ==================================
    [..]
      Below the list of most used macros in SAI HAL driver :

      (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral
      (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral
      (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts
      (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts
      (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is
          enabled or disabled
      (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_sai.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sai_ex.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_sai_ex.c File Reference

SAI Extended HAL module driver. This file provides firmware functions to manage the following functionality of the SAI Peripheral Controller: + Modify PDM microphone delays. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | SAI_PDM_DELAY_MASK 0x77U
#define | SAI_PDM_DELAY_OFFSET 8U
#define | SAI_PDM_RIGHT_DELAY_OFFSET 4U

Functions

HAL_StatusTypeDef | HAL_SAIEx_ConfigPdmMicDelay (SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
Configure PDM microphone delays.

Detailed Description

SAI Extended HAL module driver. This file provides firmware functions to manage the following functionality of the SAI Peripheral Controller: + Modify PDM microphone delays.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_sai_ex.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sd.c File Reference

  • File List
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Functions
stm32h7xx_hal_sd.c File Reference

SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

static uint32_t | SD_InitCard (SD_HandleTypeDef *hsd)
Initializes the sd card.
static uint32_t | SD_PowerON (SD_HandleTypeDef *hsd)
Enquires cards about their operating voltage and configures clock controls and stores SD information that will be needed in future in the SD handle.
static uint32_t | SD_SendSDStatus (SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
Send Status info command.
static uint32_t | SD_SendStatus (SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
Returns the current card's status.
static uint32_t | SD_WideBus_Enable (SD_HandleTypeDef *hsd)
Enables the SDMMC wide bus mode.
static uint32_t | SD_WideBus_Disable (SD_HandleTypeDef *hsd)
Disables the SDMMC wide bus mode.
static uint32_t | SD_FindSCR (SD_HandleTypeDef *hsd, uint32_t *pSCR)
Finds the SD card SCR register value.
static HAL_StatusTypeDef | SD_PowerOFF (SD_HandleTypeDef *hsd)
Turns the SDMMC output signals off.
static HAL_StatusTypeDef | SD_Write_IT (SD_HandleTypeDef *hsd)
Wrap up writing in non-blocking mode.
static HAL_StatusTypeDef | SD_Read_IT (SD_HandleTypeDef *hsd)
Wrap up writing in non-blocking mode.
static uint32_t | SD_HighSpeed (SD_HandleTypeDef *hsd)
Switches the SD card to High Speed mode.
HAL_StatusTypeDef | HAL_SD_Init (SD_HandleTypeDef *hsd)
Initializes the SD according to the specified parameters in the SD_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SD_InitCard (SD_HandleTypeDef *hsd)
Initializes the SD Card according to the specified parameters in the.
HAL_StatusTypeDef | HAL_SD_DeInit (SD_HandleTypeDef *hsd)
De-Initializes the SD card.
__weak void | HAL_SD_MspInit (SD_HandleTypeDef *hsd)
Initializes the SD MSP.
__weak void | HAL_SD_MspDeInit (SD_HandleTypeDef *hsd)
De-Initialize SD MSP.
HAL_StatusTypeDef | HAL_SD_ReadBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SD_WriteBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
Allows to write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SD_ReadBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SD_WriteBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SD_ReadBlocks_DMA (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SD_WriteBlocks_DMA (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SD_Erase (SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
Erases the specified memory area of the given SD card.
void | HAL_SD_IRQHandler (SD_HandleTypeDef *hsd)
This function handles SD card interrupt request.
HAL_SD_StateTypeDef | HAL_SD_GetState (SD_HandleTypeDef *hsd)
return the SD state
uint32_t | HAL_SD_GetError (SD_HandleTypeDef *hsd)
Return the SD error code.
__weak void | HAL_SD_TxCpltCallback (SD_HandleTypeDef *hsd)
Tx Transfer completed callbacks.
__weak void | HAL_SD_RxCpltCallback (SD_HandleTypeDef *hsd)
Rx Transfer completed callbacks.
__weak void | HAL_SD_ErrorCallback (SD_HandleTypeDef *hsd)
SD error callbacks.
__weak void | HAL_SD_AbortCallback (SD_HandleTypeDef *hsd)
SD Abort callbacks.
__weak void | HAL_SD_DriveTransciver_1_8V_Callback (FlagStatus status)
Enable/Disable the SD Transciver 1.8V Mode Callback.
HAL_StatusTypeDef | HAL_SD_GetCardCID (SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef *pCID)
Returns information the information of the card which are stored on the CID register.
HAL_StatusTypeDef | HAL_SD_GetCardCSD (SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef *pCSD)
Returns information the information of the card which are stored on the CSD register.
HAL_StatusTypeDef | HAL_SD_GetCardStatus (SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pStatus)
Gets the SD status info.
HAL_StatusTypeDef | HAL_SD_GetCardInfo (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
Gets the SD card info.
HAL_StatusTypeDef | HAL_SD_ConfigWideBusOperation (SD_HandleTypeDef *hsd, uint32_t WideMode)
Enables wide bus operation for the requested card if supported by card.
HAL_SD_CardStateTypedef | HAL_SD_GetCardState (SD_HandleTypeDef *hsd)
Gets the current sd card data state.
HAL_StatusTypeDef | HAL_SD_Abort (SD_HandleTypeDef *hsd)
Abort the current transfer and disable the SD.
HAL_StatusTypeDef | HAL_SD_Abort_IT (SD_HandleTypeDef *hsd)
Abort the current transfer and disable the SD (IT mode).
__weak void | HAL_SDEx_Read_DMADoubleBuffer0CpltCallback (SD_HandleTypeDef *hsd)
Read DMA Buffer 0 Transfer completed callbacks.
__weak void | HAL_SDEx_Read_DMADoubleBuffer1CpltCallback (SD_HandleTypeDef *hsd)
Read DMA Buffer 1 Transfer completed callbacks.
__weak void | HAL_SDEx_Write_DMADoubleBuffer0CpltCallback (SD_HandleTypeDef *hsd)
Write DMA Buffer 0 Transfer completed callbacks.
__weak void | HAL_SDEx_Write_DMADoubleBuffer1CpltCallback (SD_HandleTypeDef *hsd)
Write DMA Buffer 1 Transfer completed callbacks.

Detailed Description

SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    This driver implements a high level communication layer for read and write from/to
    this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
    the user in HAL_SD_MspInit() function (MSP layer).
    Basically, the MSP layer configuration should be the same as we provide in the
    examples.
    You can easily tailor this configuration according to hardware resources.

  [..]
    This driver is a generic layered driver for SDMMC memories which uses the HAL
    SDMMC driver functions to interface with SD and uSD cards devices.
    It is used as follows:

    (#)Initialize the SDMMC low level resources by implement the HAL_SD_MspInit() API:
        (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
        (##) SDMMC pins configuration for SD card
            (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
                  and according to your pin assignment;
        (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
            (+++) Configure the SDMMC interrupt priorities using functions HAL_NVIC_SetPriority();
            (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
            (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT()
                  and __HAL_SD_DISABLE_IT() inside the communication process.
            (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
                  and __HAL_SD_CLEAR_IT()
        (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC IP are used.

    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization

  *** SD Card Initialization and configuration ***
  ================================================
  [..]
    To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
    the SD Card and put it into StandBy State (Ready for data transfer).
    This function provide the following operations:

    (#) Apply the SD Card initialization process at 400KHz and check the SD Card
        type (Standard Capacity or High Capacity). You can change or adapt this
        frequency by adjusting the "ClockDiv" field.
        The SD Card frequency (SDMMC_CK) is computed as follows:

           SDMMC_CK = SDMMCCLK / (2 * ClockDiv)

        In initialization mode and according to the SD Card standard,
        make sure that the SDMMC_CK frequency doesn't exceed 400KHz.

    (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo
        structure. This structure provide also ready computed SD Card capacity
        and Block size.

        -@- These information are stored in SD handle structure in case of future use.

    (#) Configure the SD Card Data transfer frequency. You can change or adapt this
        frequency by adjusting the "ClockDiv" field.
        In transfer mode and according to the SD Card standard, make sure that the
        SDMMC_CK frequency doesn't exceed 25MHz and 100MHz in High-speed mode switch.

    (#) Select the corresponding SD Card according to the address read with the step 2.

    (#) Configure the SD Card in wide bus mode: 4-bits data.

  *** SD Card Read operation ***
  ==============================
  [..]
    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.

    (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.

  *** SD Card Write operation ***
  ===============================
  [..]
    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.

    (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 byte).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.

  *** SD card status ***
  ======================
  [..]
    (+) At any time, you can check the SD Card status and get the SD card state
        by using the HAL_SD_GetStatusInfo() function. This function checks first if the
        SD card is still connected and then get the internal SD Card transfer state.

  *** SD HAL driver macros list ***
  ==================================
  [..]
    Below the list of most used macros in SD HAL driver.

    (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt
    (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt
    (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
    (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags

    (@) You can refer to the SD HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_sd.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sd_ex.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Functions
stm32h7xx_hal_sd_ex.c File Reference

SD card Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Extended features functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_SDEx_ConfigDMAMultiBuffer (SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, uint32_t BufferSize)
Configure DMA Dual Buffer mode.
HAL_StatusTypeDef | HAL_SDEx_ReadBlocksDMAMultiBuffer (SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_StatusTypeDef | HAL_SDEx_WriteBlocksDMAMultiBuffer (SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
Write block(s) to a specified address in a card.
HAL_StatusTypeDef | HAL_SDEx_ChangeDMABuffer (SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
Change the DMA Buffer0 or Buffer1 address on the fly.

Detailed Description

SD card Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Extended features functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
   The SD Extension HAL driver can be used as follows:
   (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_SDEx_ConfigDMAMultiBuffer() function.

   (+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer() and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_sd_ex.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sdram.c File Reference

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Functions
stm32h7xx_hal_sdram.c File Reference

SDRAM HAL module driver. This file provides a generic firmware to drive SDRAM memories mounted as external device. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_SDRAM_Init (SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
Performs the SDRAM device initialization sequence.
HAL_StatusTypeDef | HAL_SDRAM_DeInit (SDRAM_HandleTypeDef *hsdram)
Perform the SDRAM device initialization sequence.
__weak void | HAL_SDRAM_MspInit (SDRAM_HandleTypeDef *hsdram)
SDRAM MSP Init.
__weak void | HAL_SDRAM_MspDeInit (SDRAM_HandleTypeDef *hsdram)
SDRAM MSP DeInit.
void | HAL_SDRAM_IRQHandler (SDRAM_HandleTypeDef *hsdram)
This function handles SDRAM refresh error interrupt request.
__weak void | HAL_SDRAM_RefreshErrorCallback (SDRAM_HandleTypeDef *hsdram)
SDRAM Refresh error callback.
__weak void | HAL_SDRAM_DMA_XferCpltCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete callback.
__weak void | HAL_SDRAM_DMA_XferErrorCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete error callback.
HAL_StatusTypeDef | HAL_SDRAM_Read_8b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
Reads 8-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_8b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
Writes 8-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_16b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
Reads 16-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_16b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
Writes 16-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_32b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads 32-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_32b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes 32-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_DMA (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads a Words data from the SDRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SDRAM_Write_DMA (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes a Words data buffer to SDRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SDRAM_WriteProtection_Enable (SDRAM_HandleTypeDef *hsdram)
Enables dynamically SDRAM write protection.
HAL_StatusTypeDef | HAL_SDRAM_WriteProtection_Disable (SDRAM_HandleTypeDef *hsdram)
Disables dynamically SDRAM write protection.
HAL_StatusTypeDef | HAL_SDRAM_SendCommand (SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
Sends Command to the SDRAM bank.
HAL_StatusTypeDef | HAL_SDRAM_ProgramRefreshRate (SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
Programs the SDRAM Memory Refresh rate.
HAL_StatusTypeDef | HAL_SDRAM_SetAutoRefreshNumber (SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
Sets the Number of consecutive SDRAM Memory auto Refresh commands.
uint32_t | HAL_SDRAM_GetModeStatus (SDRAM_HandleTypeDef *hsdram)
Returns the SDRAM memory current mode.
HAL_SDRAM_StateTypeDef | HAL_SDRAM_GetState (SDRAM_HandleTypeDef *hsdram)
Returns the SDRAM state.

Detailed Description

SDRAM HAL module driver. This file provides a generic firmware to drive SDRAM memories mounted as external device.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                       ##### How to use this driver #####
  ==============================================================================
  [..]
    This driver is a generic layered driver which contains a set of APIs used to
    control SDRAM memories. It uses the FMC layer functions to interface
    with SDRAM devices.
    The following sequence should be followed to configure the FMC to interface
    with SDRAM memories:

   (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
          SDRAM_HandleTypeDef  hdsram

       (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
            values of the structure member.

       (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
            base register instance for NOR or SDRAM device

   (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
          FMC_SDRAM_TimingTypeDef  Timing;
      and fill its fields with the allowed values of the structure member.

   (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
       performs the following sequence:

       (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
       (##) Control register configuration using the FMC SDRAM interface function
            FMC_SDRAM_Init()
       (##) Timing register configuration using the FMC SDRAM interface function
            FMC_SDRAM_Timing_Init()
       (##) Program the SDRAM external device by applying its initialization sequence
            according to the device plugged in your hardware. This step is mandatory
            for accessing the SDRAM device.

   (#) At this stage you can perform read/write accesses from/to the memory connected
       to the SDRAM Bank. You can perform either polling or DMA transfer using the
       following APIs:
       (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
       (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer

   (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
       HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
       the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
       device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
       structure.

   (#) You can continuously monitor the SDRAM device HAL state by calling the function
       HAL_SDRAM_GetState()
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_sdram.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_smartcard.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
  • Src
Defines | Functions
stm32h7xx_hal_smartcard.c File Reference

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | SMARTCARD_TEACK_REACK_TIMEOUT 1000
#define | USART_CR1_FIELDS
#define | USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL))
#define | USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP))
#define | USART_CR3_FIELDS

Functions

static HAL_StatusTypeDef | SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral.
static void | SMARTCARD_AdvFeatureConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral advanced features.
static HAL_StatusTypeDef | SMARTCARD_CheckIdleState (SMARTCARD_HandleTypeDef *hsmartcard)
Check the SMARTCARD Idle State.
static HAL_StatusTypeDef | SMARTCARD_WaitOnFlagUntilTimeout (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle SMARTCARD Communication Timeout.
static void | SMARTCARD_EndTxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
static void | SMARTCARD_EndRxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | SMARTCARD_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD transmit process complete callback.
static void | SMARTCARD_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD receive process complete callback.
static void | SMARTCARD_DMAError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication error callback.
static void | SMARTCARD_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SMARTCARD_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SMARTCARD_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | SMARTCARD_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | SMARTCARD_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static HAL_StatusTypeDef | SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | SMARTCARD_EndTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Wrap up transmission in non-blocking mode.
static HAL_StatusTypeDef | SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD MSP.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD MSP.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Abort (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_Abort_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsmartcard)
Handle SMARTCARD interrupt requests.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Tx Transfer completed callback.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Rx Transfer completed callback.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD error callback.
__weak void | HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Receive Complete callback.
HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle state.
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle error code.

Detailed Description

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The SMARTCARD HAL driver can be used as follows:

    (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
    (#) Associate a USART to the SMARTCARD handle hsmartcard.
    (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
        (++) Enable the USARTx interface clock.
        (++) USART pins configuration:
            (+++) Enable the clock for the USART GPIOs.
            (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
        (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
             and HAL_SMARTCARD_Receive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
        (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
             and HAL_SMARTCARD_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.

    (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
        the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
        error enabling or disabling in the hsmartcard handle Init structure.

    (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
        in the hsmartcard handle AdvancedInit structure.

    (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_SMARTCARD_MspInit() API.
        [..]
        (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
             RXNE interrupt and Error Interrupts) will be managed using the macros
             __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.

    [..]
    [..] Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()

     *** SMARTCARD HAL driver macros list ***
     ========================================
     [..]
       Below the list of most used macros in SMARTCARD HAL driver.

       (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
       (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
       (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
       (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
       (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled

     [..]
       (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_smartcard.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_smartcard_ex.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
  • Src
Functions
stm32h7xx_hal_smartcard_ex.c File Reference

SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the SMARTCARD receiver timeout feature.

Detailed Description

SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  =============================================================================
               ##### SMARTCARD peripheral extended features  #####
  =============================================================================
  [..]
  The Extended SMARTCARD HAL driver can be used as follows:

    (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
        then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
        auto-retry counter,...) in the hsmartcard AdvancedInit structure.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_smartcard_ex.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_smbus.c File Reference

  • File List
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Defines | Functions
stm32h7xx_hal_smbus.c File Reference

SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! SMBUS TIMING clear register Mask */
#define | HAL_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */
#define | HAL_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_TC ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */
#define | MAX_NBYTE_SIZE 255

Functions

static HAL_StatusTypeDef | SMBUS_WaitOnFlagUntilTimeout (SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
Handle SMBUS Communication Timeout.
static HAL_StatusTypeDef | SMBUS_Enable_IRQ (SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static HAL_StatusTypeDef | SMBUS_Disable_IRQ (SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static HAL_StatusTypeDef | SMBUS_Master_ISR (SMBUS_HandleTypeDef *hsmbus)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
static HAL_StatusTypeDef | SMBUS_Slave_ISR (SMBUS_HandleTypeDef *hsmbus)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
static void | SMBUS_ConvertOtherXferOptions (SMBUS_HandleTypeDef *hsmbus)
Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
static void | SMBUS_TransferConfig (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
HAL_StatusTypeDef | HAL_SMBUS_Init (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS peripheral.
__weak void | HAL_SMBUS_MspInit (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS MSP.
__weak void | HAL_SMBUS_MspDeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS MSP.
HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.
void | HAL_SMBUS_EV_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS event interrupt request.
void | HAL_SMBUS_ER_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS error interrupt request.
__weak void | HAL_SMBUS_MasterTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Tx Transfer completed callback.
__weak void | HAL_SMBUS_MasterRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Rx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Tx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Rx Transfer completed callback.
__weak void | HAL_SMBUS_AddrCallback (SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_SMBUS_ListenCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Listen Complete callback.
__weak void | HAL_SMBUS_ErrorCallback (SMBUS_HandleTypeDef *hsmbus)
SMBUS error callback.
uint32_t | HAL_SMBUS_GetState (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS handle state.
uint32_t | HAL_SMBUS_GetError (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS error code.

Detailed Description

SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
    The SMBUS HAL driver can be used as follows:

    (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
        SMBUS_HandleTypeDef  hsmbus;

    (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
        (++) Enable the SMBUSx interface clock
        (++) SMBUS pins configuration
            (+++) Enable the clock for the SMBUS GPIOs
            (+++) Configure SMBUS pins as alternate function open-drain
        (++) NVIC configuration if you need to use interrupt process
            (+++) Configure the SMBUSx interrupt priority
            (+++) Enable the NVIC SMBUS IRQ Channel

    (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing Mode,
        Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
        Peripheral mode and Packet Error Check mode in the hsmbus Init structure.

    (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
        (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.

    (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()

    (#) For SMBUS IO operations, only one mode of operations is available within this driver

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT()
      (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
      (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT()
      (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
      (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
      (++) The associated previous transfer callback is called at the end of abort process
      (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
      (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
      (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
           using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
      (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can
           add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
      (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
      (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT()
      (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
      (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT()
      (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
      (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
      (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
           add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
           to check the Alert Error Code using function HAL_SMBUS_GetError()
      (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
      (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
           to check the Error Code using function HAL_SMBUS_GetError()

     *** SMBUS HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in SMBUS HAL driver.

      (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
      (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
      (+) __HAL_SMBUS_GET_FLAG : Checks whether the specified SMBUS flag is set or not
      (+) __HAL_SMBUS_CLEAR_FLAG : Clears the specified SMBUS pending flag
      (+) __HAL_SMBUS_ENABLE_IT: Enables the specified SMBUS interrupt
      (+) __HAL_SMBUS_DISABLE_IT: Disables the specified SMBUS interrupt

     [..]
       (@) You can refer to the SMBUS HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_smbus.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_spdifrx.c File Reference

  • File List
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Defines | Functions
stm32h7xx_hal_spdifrx.c File Reference

This file provides firmware functions to manage the following functionalities of the SPDIFRX audio interface: + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | SPDIFRX_TIMEOUT_VALUE 0xFFFFU

Functions

static void | SPDIFRX_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Data flow) complete callback.
static void | SPDIFRX_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Data flow) half complete callback.
static void | SPDIFRX_DMACxCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Control flow) complete callback.
static void | SPDIFRX_DMACxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Control flow) half complete callback.
static void | SPDIFRX_DMAError (DMA_HandleTypeDef *hdma)
DMA SPDIFRX communication error callback.
static void | SPDIFRX_ReceiveControlFlow_IT (SPDIFRX_HandleTypeDef *hspdif)
Receive an amount of data (Control Flow) with Interrupt.
static void | SPDIFRX_ReceiveDataFlow_IT (SPDIFRX_HandleTypeDef *hspdif)
Receive an amount of data (Data Flow) with Interrupt.
static HAL_StatusTypeDef | SPDIFRX_WaitOnFlagUntilTimeout (SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart)
This function handles SPDIFRX Communication Timeout.
HAL_StatusTypeDef | HAL_SPDIFRX_Init (SPDIFRX_HandleTypeDef *hspdif)
Initializes the SPDIFRX according to the specified parameters in the SPDIFRX_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif)
DeInitializes the SPDIFRX peripheral.
__weak void | HAL_SPDIFRX_MspInit (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX MSP Init.
__weak void | HAL_SPDIFRX_MspDeInit (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX MSP DeInit.
HAL_StatusTypeDef | HAL_SPDIFRX_SetDataFormat (SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)
Sets the SPDIFRX dtat format according to the specified parameters in the SPDIFRX_InitTypeDef.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data (Data Flow) in blocking mode.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveControlFlow (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data (Control Flow) in blocking mode.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow_IT (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Data Flow) in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveControlFlow_IT (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Control Flow) with Interrupt.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow_DMA (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Data Flow) mode with DMA.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveControlFlow_DMA (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Control Flow) with DMA.
HAL_StatusTypeDef | HAL_SPDIFRX_DMAStop (SPDIFRX_HandleTypeDef *hspdif)
stop the audio stream receive from the Media.
void | HAL_SPDIFRX_IRQHandler (SPDIFRX_HandleTypeDef *hspdif)
This function handles SPDIFRX interrupt request.
__weak void | HAL_SPDIFRX_RxHalfCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Data flow) half completed callbacks.
__weak void | HAL_SPDIFRX_RxCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Data flow) completed callbacks.
__weak void | HAL_SPDIFRX_CxHalfCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx (Control flow) Transfer half completed callbacks.
__weak void | HAL_SPDIFRX_CxCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Control flow) completed callbacks.
__weak void | HAL_SPDIFRX_ErrorCallback (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX error callbacks.
HAL_SPDIFRX_StateTypeDef | HAL_SPDIFRX_GetState (SPDIFRX_HandleTypeDef *hspdif)
Return the SPDIFRX state.
uint32_t | HAL_SPDIFRX_GetError (SPDIFRX_HandleTypeDef *hspdif)
Return the SPDIFRX error code.

Detailed Description

This file provides firmware functions to manage the following functionalities of the SPDIFRX audio interface: + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
 ===============================================================================
                  ##### How to use this driver #####
 ===============================================================================
 [..]
    The SPDIFRX HAL driver can be used as follow:

    (#) Declare SPDIFRX_HandleTypeDef handle structure.
    (#) Initialize the SPDIFRX low level resources by implement the HAL_SPDIFRX_MspInit() API:
        (##) Enable the SPDIFRX interface clock.
        (##) SPDIFRX pins configuration:
            (+++) Enable the clock for the SPDIFRX GPIOs.
            (+++) Configure these SPDIFRX pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveControlFlow_IT() and HAL_SPDIFRX_ReceiveDataFlow_IT() API's).
            (+++) Configure the SPDIFRX interrupt priority.
            (+++) Enable the NVIC SPDIFRX IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveControlFlow_DMA() API's).
            (+++) Declare a DMA handle structure for the reception of the Data Flow channel.
            (+++) Declare a DMA handle structure for the reception of the Control Flow channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters.
            (+++) Configure the DMA Channel.
            (+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
                DMA CtrlRx/DataRx channel.

   (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits
       using HAL_SPDIFRX_Init() function.

   -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros
       __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process.
   -@- Make sure that ck_spdif clock is configured.

   (#) Three operation modes are available within this driver :

   *** Polling mode for reception operation (for debug purpose) ***
   ================================================================
   [..]
     (+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow()
         (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveControlFlow()

   *** Interrupt mode for reception operation ***
   =========================================
   [..]
     (+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT()
         (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveControlFlow_IT()
     (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
     (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
     (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback

   *** DMA mode for reception operation ***
   ========================================
   [..]
     (+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA()
         (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveControlFlow_DMA()
     (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
     (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
     (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
     (+) Stop the DMA Transfer using HAL_SPDIFRX_DMAStop()

   *** SPDIFRX HAL driver macros list ***
   =============================================
   [..]
     Below the list of most used macros in USART HAL driver.
      (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State)
      (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State)
      (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State)
      (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts
      (+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts
      (+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not.

    [..]
      (@) You can refer to the SPDIFRX HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_spdifrx.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_spi.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_spi.c File Reference

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | SPI_DEFAULT_TIMEOUT 100U

Functions

static void | SPI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit process complete callback.
static void | SPI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI receive process complete callback.
static void | SPI_DMATransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit receive process complete callback.
static void | SPI_DMAHalfTransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit process complete callback.
static void | SPI_DMAHalfReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half receive process complete callback.
static void | SPI_DMAHalfTransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit receive process complete callback.
static void | SPI_DMAError (DMA_HandleTypeDef *hdma)
DMA SPI communication error callback.
static void | SPI_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SPI_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SPI_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | SPI_WaitFlagStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI Communication Timeout.
static HAL_StatusTypeDef | SPI_WaitFifoStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI FIFO Communication Timeout.
static void | SPI_TxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 8-bit transmit in Interrupt mode.
static void | SPI_TxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 16-bit transmit in Interrupt mode.
static void | SPI_TxISR_32BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 32-bit transmit in Interrupt mode.
static void | SPI_RxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Manage the receive 8-bit in Interrupt context.
static void | SPI_RxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Manage the 16-bit receive in Interrupt context.
static void | SPI_RxISR_32BIT (struct __SPI_HandleTypeDef *hspi)
Manage the 32-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Tx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Tx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_32BIT (struct __SPI_HandleTypeDef *hspi)
Tx 32-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Rx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_32BIT (struct __SPI_HandleTypeDef *hspi)
Rx 32-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_AbortRx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Rx transaction.
static void | SPI_AbortTx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Tx or Rx/Tx transaction.
static void | SPI_CloseRxTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.
static void | SPI_CloseRx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RX transaction.
static void | SPI_CloseTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the TX transaction.
static HAL_StatusTypeDef | SPI_EndRxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RX transaction complete.
static HAL_StatusTypeDef | SPI_EndRxTxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RXTX or TX transaction complete.
HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Abort (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_SPI_Abort_IT (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
__weak void | HAL_SPI_AbortCpltCallback (SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.
HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      The SPI HAL driver can be used as follows:

      (#) Declare a SPI_HandleTypeDef handle structure, for example:
          SPI_HandleTypeDef  hspi;

      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
          (##) Enable the SPIx interface clock
          (##) SPI pins configuration
              (+++) Enable the clock for the SPI GPIOs
              (+++) Configure these SPI pins as alternate function push-pull
          (##) NVIC configuration if you need to use interrupt process
              (+++) Configure the SPIx interrupt priority
              (+++) Enable the NVIC SPI IRQ handle
          (##) DMA Configuration if you need to use DMA process
              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
              (+++) Enable the DMAx clock
              (+++) Configure the DMA handle parameters
              (+++) Configure the DMA Tx or Rx Stream/Channel
              (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel

      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.

      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
              by calling the customized HAL_SPI_MspInit() API.

    [..]
      Circular mode restriction:
      (+) The DMA circular mode cannot be used when the SPI is configured in these modes:
          (++) Master 2Lines RxOnly
          (++) Master 1Line Rx
      (+) The CRC feature is not managed when the DMA circular mode is enabled
      (+) When the SPI DMA Pause/Stop features are used, we must use the following APIs
          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_spi.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_spi_ex.c File Reference

  • File List
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  • Drivers
  • STM32H7xx_HAL_Driver
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Functions
stm32h7xx_hal_spi_ex.c File Reference

Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions + Peripheral Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_SPIEx_FlushRxFifo (SPI_HandleTypeDef *hspi)
Flush the RX fifo.
HAL_StatusTypeDef | HAL_SPIEx_EnableLockConfiguration (SPI_HandleTypeDef *hspi)
Enable the Lock for the AF configuration of associated IOs and write protect the Content of Configuartion register 2 when SPI is enabled.
HAL_StatusTypeDef | HAL_SPIEx_DisableLockConfiguration (SPI_HandleTypeDef *hspi)
Disable the Lock for the AF configuration of associated IOs.
HAL_StatusTypeDef | HAL_SPIEx_ConfigureUnderrun (SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour)
Configure the UNDERRUN condition and behavior of slave transmitter.

Detailed Description

Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_spi_ex.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sram.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32H7xx_HAL_Driver
  • Src
Functions
stm32h7xx_hal_sram.c File Reference

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_SRAM_Init (SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Performs the SRAM device initialization sequence.
HAL_StatusTypeDef | HAL_SRAM_DeInit (SRAM_HandleTypeDef *hsram)
Performs the SRAM device De-initialization sequence.
__weak void | HAL_SRAM_MspInit (SRAM_HandleTypeDef *hsram)
SRAM MSP Init.
__weak void | HAL_SRAM_MspDeInit (SRAM_HandleTypeDef *hsram)
SRAM MSP DeInit.
__weak void | HAL_SRAM_DMA_XferCpltCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete callback.
__weak void | HAL_SRAM_DMA_XferErrorCallback (MDMA_HandleTypeDef *hmdma)
DMA transfer complete error callback.
HAL_StatusTypeDef | HAL_SRAM_Read_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
Reads 8-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
Writes 8-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
Reads 16-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
Writes 16-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads 32-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes 32-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads a Words data from the SRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SRAM_Write_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes a Words data buffer to SRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Enable (SRAM_HandleTypeDef *hsram)
Enables dynamically SRAM write operation.
HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Disable (SRAM_HandleTypeDef *hsram)
Disables dynamically SRAM write operation.
HAL_SRAM_StateTypeDef | HAL_SRAM_GetState (SRAM_HandleTypeDef *hsram)
Returns the SRAM controller state.

Detailed Description

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                          ##### How to use this driver #####
  ==============================================================================
  [..]
    This driver is a generic layered driver which contains a set of APIs used to
    control SRAM memories. It uses the FMC layer functions to interface
    with SRAM devices.
    The following sequence should be followed to configure the FMC to interface
    with SRAM/PSRAM memories:

   (#) Declare a SRAM_HandleTypeDef handle structure, for example:
          SRAM_HandleTypeDef  hsram; and:

       (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
            values of the structure member.

       (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
            base register instance for NOR or SRAM device

       (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
            base register instance for NOR or SRAM extended mode

   (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
       mode timings; for example:
          FMC_NORSRAM_TimingTypeDef  Timing and FMC_NORSRAM_TimingTypeDef  ExTiming;
      and fill its fields with the allowed values of the structure member.

   (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
       performs the following sequence:

       (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
       (##) Control register configuration using the FMC NORSRAM interface function
            FMC_NORSRAM_Init()
       (##) Timing register configuration using the FMC NORSRAM interface function
            FMC_NORSRAM_Timing_Init()
       (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
            FMC_NORSRAM_Extended_Timing_Init()
       (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()

   (#) At this stage you can perform read/write accesses from/to the memory connected
       to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
       following APIs:
       (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
       (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer

   (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
       HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation

   (#) You can continuously monitor the SRAM device HAL state by calling the function
       HAL_SRAM_GetState()
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_sram.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_swpmi.c File Reference

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Defines | Functions
stm32h7xx_hal_swpmi.c File Reference

SWPMI HAL module driver. This file provides firmware functions to manage the following functionalities of the Single Wire Protocol Master Interface (SWPMI). + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | SWPMI_TIMEOUT_VALUE ((uint32_t) 22000U)

Functions

static void | SWPMI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI transmit process complete callback.
static void | SWPMI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI transmit process half complete callback.
static void | SWPMI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI receive process complete callback.
static void | SWPMI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI receive process half complete callback.
static void | SWPMI_DMAError (DMA_HandleTypeDef *hdma)
DMA SWPMI communication error callback.
static void | SWPMI_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SWPMI communication abort callback.
static HAL_StatusTypeDef | SWPMI_Transmit_IT (SWPMI_HandleTypeDef *hswpmi)
Transmit an amount of data in interrupt mode.
static HAL_StatusTypeDef | SWPMI_EndTransmit_IT (SWPMI_HandleTypeDef *hswpmi)
Wraps up transmission in non-blocking mode.
static HAL_StatusTypeDef | SWPMI_Receive_IT (SWPMI_HandleTypeDef *hswpmi)
Receive an amount of data in interrupt mode.
static HAL_StatusTypeDef | SWPMI_EndReceive_IT (SWPMI_HandleTypeDef *hswpmi)
Wraps up reception in non-blocking mode.
static HAL_StatusTypeDef | SWPMI_EndTransmitReceive_IT (SWPMI_HandleTypeDef *hswpmi)
Wraps up transmission and reception in non-blocking mode.
static HAL_StatusTypeDef | SWPMI_WaitOnFlagSetUntilTimeout (SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout)
Handle SWPMI Communication Timeout.
HAL_StatusTypeDef | HAL_SWPMI_Init (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.
HAL_StatusTypeDef | HAL_SWPMI_DeInit (SWPMI_HandleTypeDef *hswpmi)
De-initialize the SWPMI peripheral.
__weak void | HAL_SWPMI_MspInit (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI MSP.
__weak void | HAL_SWPMI_MspDeInit (SWPMI_HandleTypeDef *hswpmi)
DeInitialize the SWPMI MSP.
HAL_StatusTypeDef | HAL_SWPMI_Transmit (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Receive (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_DMAStop (SWPMI_HandleTypeDef *hswpmi)
Stop all DMA transfers.
HAL_StatusTypeDef | HAL_SWPMI_EnableLoopback (SWPMI_HandleTypeDef *hswpmi)
Enable the Loopback mode.
HAL_StatusTypeDef | HAL_SWPMI_DisableLoopback (SWPMI_HandleTypeDef *hswpmi)
Disable the Loopback mode.
void | HAL_SWPMI_IRQHandler (SWPMI_HandleTypeDef *hswpmi)
Handle SWPMI interrupt request.
__weak void | HAL_SWPMI_TxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Transfer completed callback.
__weak void | HAL_SWPMI_TxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Half Transfer completed callback.
__weak void | HAL_SWPMI_RxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Transfer completed callback.
__weak void | HAL_SWPMI_RxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Half Transfer completed callback.
__weak void | HAL_SWPMI_ErrorCallback (SWPMI_HandleTypeDef *hswpmi)
SWPMI error callback.
HAL_SWPMI_StateTypeDef | HAL_SWPMI_GetState (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI handle state.
uint32_t | HAL_SWPMI_GetError (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI error code.

Detailed Description

SWPMI HAL module driver. This file provides firmware functions to manage the following functionalities of the Single Wire Protocol Master Interface (SWPMI). + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
  [..]
     The SWPMI HAL driver can be used as follows:

    (#) Declare a SWPMI_HandleTypeDef handle structure (eg. SWPMI_HandleTypeDef hswpmi).

    (#) Initialize the SWPMI low level resources by implementing the HAL_SWPMI_MspInit() API:
        (##) Enable the SWPMIx interface clock with __HAL_RCC_SWPMIx_CLK_ENABLE().
        (##) SWPMI IO configuration:
            (+++) Enable the clock for the SWPMI GPIO.
            (+++) Configure these SWPMI pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_SWPMI_Transmit_IT()
             and HAL_SWPMI_Receive_IT() APIs):
            (+++) Configure the SWPMIx interrupt priority with HAL_NVIC_SetPriority().
            (+++) Enable the NVIC SWPMI IRQ handle with HAL_NVIC_EnableIRQ().

        (##) DMA Configuration if you need to use DMA process (HAL_SWPMI_Transmit_DMA()
             and HAL_SWPMI_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channels.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required
                  Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channels and requests.
            (+++) Associate the initialized DMA handle to the SWPMI DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete
                  interrupt on the DMA Tx/Rx channels.

    (#) Program the Bite Rate, Tx Buffering mode, Rx Buffering mode in the Init structure.

    (#) Enable the SWPMI peripheral by calling the HAL_SWPMI_Init() function.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_swpmi.c.

Generated on Fri Apr 28 2017 15:42:42 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_tim.c File Reference

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Functions
stm32h7xx_hal_tim.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

static void | TIM_OC5_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM Output Compare 5 configuration.
static void | TIM_OC6_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM Output Compare 6 configuration.
static void | TIM_TI1_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI1.
static void | TIM_TI2_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TIM_TI2_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI2.
static void | TIM_TI3_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TIM_TI4_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI4 as Input.
static void | TIM_ITRx_SetConfig (TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
Selects the Input Trigger source.
static void | TIM_DMAPeriodElapsedCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse complete callback.
static void | TIM_DMATriggerCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger callback.
static void | TIM_SlaveTimer_SetConfig (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
TIM Slave mode configuration.
HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initialize the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initialize the TIM Time Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Time Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Time Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Time Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Time Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Time Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Time Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Time Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initialize the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initialize the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initialize the TIM PWM mode according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initialize the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initialize the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initialize the TIM Input Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement on in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement on in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initialize the TIM One Pulse mode according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM One Pulse mode.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initialize the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initialize the TIM Encoder Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initialize the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.
void | HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.
HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initialize the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initialize the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initialize the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initialize the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.
__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
TIM error callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Output Compare handle state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM handle state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode handle state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode state.
void | HAL_TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | HAL_TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | HAL_TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM Output Compare 1 configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM Output Compare 2 configuration.
void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM Output Compare 3 configuration.
void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM Output Compare 4 configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                      ##### TIM Generic features #####
  ==============================================================================
  [..] The Timer features include:
       (#) 16-bit (32-bit for TIM2/TIM5) up, down, up/down auto-reload counter.
       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
           counter clock frequency either by any factor between 1 and 65536.
       (#) Up to 4 independent channels for:
           (++) Input Capture
           (++) Output Compare
           (++) PWM generation (Edge and Center-aligned Mode)
           (++) One-pulse mode output

            ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending on the selected feature:
           (++) Time Base : HAL_TIM_Base_MspInit()
           (++) Input Capture : HAL_TIM_IC_MspInit()
           (++) Output Compare : HAL_TIM_OC_MspInit()
           (++) PWM generation : HAL_TIM_PWM_MspInit()
           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
             __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.
     (#) Configure the TIM in the desired functioning mode using one of the
       Initialization function of this driver:
       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base.
       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
            Output Compare signal.
       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
            PWM signal.
       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
            external signal.
       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
              in One Pulse Mode.
       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT().
           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT().
           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT().
           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT().
           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT().
           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
     (#) The DMA Burst is managed with the two following functions:
           (++)HAL_TIM_DMABurst_WriteStart().
           (++)HAL_TIM_DMABurst_ReadStart().
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_tim.c.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_tim_ex.c File Reference

  • File List
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  • Drivers
  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_tim_ex.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal bread and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | BDTR_BKF_SHIFT (16)
#define | BDTR_BK2F_SHIFT (20)
#define | TIMx_ETRSEL_MASK ((uint32_t)0x003C000)
#define | TIMx_TIxSEL_MASK ((uint32_t)0x000000F)

Functions

static void | TIM_CCxNChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
Enables or disables the TIM Capture Compare Channel xN.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Start the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complemetary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
Configures the break input source.
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIMx Remapping input capabilities.
HAL_StatusTypeDef | HAL_TIMEx_TISelection (TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
Configures the TIMx input Selection capabilities.
HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t Channels)
Group channel 5 and channel 1, 2 or 3.
__weak void | HAL_TIMEx_CommutationCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface state.
void | HAL_TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal bread and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                      ##### TIM Extended features #####
  ==============================================================================
  [..]
    The Timer Extended features include:
    (#) Complementary outputs with programmable dead-time for :
        (++) Output Compare
        (++) PWM generation (Edge and Center-aligned Mode)
        (++) One-pulse mode output
    (#) Synchronization circuit to control the timer with external signals and to
        interconnect several timers together.
    (#) Break input to put the timer output signals in reset state or in a known state.
    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
        positioning purposes

            ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending from feature used :
           (++) Complementary Output Compare : HAL_TIM_OC_MspInit().
           (++) Complementary PWM generation : HAL_TIM_PWM_MspInit().
           (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit().
           (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit().

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
              __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.

     (#) Configure the TIM in the desired functioning mode using one of the
         initialization function of this driver:
          (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
              Timer Hall Sensor Interface and the commutation event with the corresponding
              Interrupt and DMA request if needed (Note that One Timer is used to interface
             with the Hall sensor Interface and another Timer should be used to use
             the commutation event).

     (#) Activate the TIM peripheral using one of the start functions:
           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT().
           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT().
           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT().
           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_tim_ex.c.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_uart.c File Reference

  • File List
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  • STM32H7xx_HAL_Driver
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Defines | Functions
stm32h7xx_hal_uart.c File Reference

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | UART_CR1_FIELDS
#define | USART_CR3_FIELDS
#define | UART_LPUART_BRR_MIN ((uint32_t)0x00000300) /* LPUART BRR minimum authorized value */
#define | UART_LPUART_BRR_MAX ((uint32_t)0x000FFFFF) /* LPUART BRR maximum authorized value */

Functions

static void | UART_EndTxTransfer (UART_HandleTypeDef *huart)
End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
static void | UART_EndRxTransfer (UART_HandleTypeDef *huart)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | UART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process complete callback.
static void | UART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process complete callback.
static void | UART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process half complete callback.
static void | UART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process half complete callback.
static void | UART_DMAError (DMA_HandleTypeDef *hdma)
DMA UART communication error callback.
static void | UART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA UART communication abort callback (To be called at end of DMA Abort procedure).
static void | UART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | UART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | UART_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user by a call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | UART_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user by a call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static HAL_StatusTypeDef | UART_Transmit_IT (UART_HandleTypeDef *huart)
Send an amount of data in interrupt mode.
static HAL_StatusTypeDef | UART_EndTransmit_IT (UART_HandleTypeDef *huart)
Wrap up transmission in non-blocking mode.
static HAL_StatusTypeDef | UART_Receive_IT (UART_HandleTypeDef *huart)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitialize the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
Initialize the UART MSP.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
DeInitialize the UART MSP.
HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_Abort (UART_HandleTypeDef *huart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_Abort_IT (UART_HandleTypeDef *huart)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit_IT (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive_IT (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
Handle UART interrupt request.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callback.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callback.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callback.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callback.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callback.
__weak void | HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
UART Abort Receive Complete callback.
HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enable the UART transmitter and disable the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enable the UART receiver and disable the UART transmitter.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmit break characters.
HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
Return the UART handle state.
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART handle error code.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle UART Communication Timeout.

Detailed Description

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
  [..]
    The UART HAL driver can be used as follows:

    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
        (++) Enable the USARTx interface clock.
        (++) UART pins configuration:
            (+++) Enable the clock for the UART GPIOs.
            (+++) Configure these UART pins as alternate function pull-up.
        (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
             and HAL_UART_Receive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
        (++) UART interrupts handling:
              -@@-  The specific UART interrupts (Transmission complete interrupt,
                RXNE interrupt and Error Interrupts) are managed using the macros
                __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive processes.
        (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
             and HAL_UART_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.

    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
        flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.

    (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
        in the huart handle AdvancedInit structure.

    (#) For the UART asynchronous mode, initialize the UART registers by calling
        the HAL_UART_Init() API.

    (#) For the UART Half duplex mode, initialize the UART registers by calling
        the HAL_HalfDuplex_Init() API.

    (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
        by calling the HAL_LIN_Init() API.

    (#) For the UART Multiprocessor mode, initialize the UART registers
        by calling the HAL_MultiProcessor_Init() API.

    (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
        by calling the HAL_RS485Ex_Init() API.

    [..]
    (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
        also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
        calling the customized HAL_UART_MspInit() API.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_uart.c.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_uart_ex.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32H7xx_HAL_Driver
  • Src
Functions
stm32h7xx_hal_uart_ex.c File Reference

Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

static void | UARTEx_Wakeup_AddressConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Initialize the UART wake-up from stop mode parameters when triggered by address detection.
HAL_StatusTypeDef | HAL_RS485Ex_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_MultiProcessorEx_AddressLength_Set (UART_HandleTypeDef *huart, uint32_t AddressLength)
By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).
HAL_StatusTypeDef | HAL_UARTEx_StopModeWakeUpSourceConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Set Wakeup from Stop mode interrupt flag selection.
HAL_StatusTypeDef | HAL_UARTEx_EnableStopMode (UART_HandleTypeDef *huart)
Enable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableStopMode (UART_HandleTypeDef *huart)
Disable UART Stop Mode.
__weak void | HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.

Detailed Description

Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
               ##### UART peripheral extended features  #####
  ==============================================================================

    (#) Declare a UART_HandleTypeDef handle structure.

    (#) For the UART RS485 Driver Enable mode, initialize the UART registers
        by calling the HAL_RS485Ex_Init() API.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_uart_ex.c.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_usart.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32H7xx_HAL_Driver
  • Src
Defines | Functions
stm32h7xx_hal_usart.c File Reference

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Defines

#define | USART_DUMMY_DATA ((uint16_t) 0xFFFF)
#define | USART_TEACK_REACK_TIMEOUT ((uint32_t) 1000)
#define | USART_CR1_FIELDS
#define | USART_CR2_FIELDS
#define | USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))

Functions

static void | USART_EndTransfer (USART_HandleTypeDef *husart)
End ongoing transfer on USART peripheral (following error detection or Transfer completion).
static void | USART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process complete callback.
static void | USART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process complete callback.
static void | USART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process half complete callback.
static void | USART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process half complete callback.
static void | USART_DMAError (DMA_HandleTypeDef *hdma)
DMA USART communication error callback.
static void | USART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | USART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | USART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | USART_WaitOnFlagUntilTimeout (USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle USART Communication Timeout.
static HAL_StatusTypeDef | USART_SetConfig (USART_HandleTypeDef *husart)
Configure the USART peripheral.
static HAL_StatusTypeDef | USART_CheckIdleState (USART_HandleTypeDef *husart)
Check the USART Idle State.
static HAL_StatusTypeDef | USART_Transmit_IT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_EndTransmit_IT (USART_HandleTypeDef *husart)
Wraps up transmission in non-blocking mode.
static HAL_StatusTypeDef | USART_Receive_IT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_TransmitReceive_IT (USART_HandleTypeDef *husart)
Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitialize the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
Initialize the USART MSP.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
DeInitialize the USART MSP.
HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_Abort (USART_HandleTypeDef *husart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_USART_Abort_IT (USART_HandleTypeDef *husart)
Abort ongoing transfers (Interrupt mode).
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
Handle USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callback.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callback.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callback.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callback.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callback.
__weak void | HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
USART Abort Complete callback.
HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
Return the USART handle state.
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
    [..]
      The USART HAL driver can be used as follows:

      (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
      (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
          (++) Enable the USARTx interface clock.
          (++) USART pins configuration:
            (+++) Enable the clock for the USART GPIOs.
            (+++) Configure these USART pins as alternate function pull-up.
          (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
                HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
            (++) USART interrupts handling:
              -@@-   The specific USART interrupts (Transmission complete interrupt,
                  RXNE interrupt and Error Interrupts) will be managed using the macros
                  __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
          (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
               HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.

      (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
          flow control and Mode (Receiver/Transmitter) in the husart handle Init structure.

      (#) Initialize the USART registers by calling the HAL_USART_Init() API:
          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
               by calling the customized HAL_USART_MspInit(&husart) API.

    [..]
     (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
        HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
        HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_usart.c.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_wwdg.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32H7xx_HAL_Driver
  • Src
Functions
stm32h7xx_hal_wwdg.c File Reference

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration function + IO operation functions. More...

#include "stm32h7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration function + IO operation functions.

Author:
MCD Application Team
Version:
V1.0.0
Date:
21-April-2017
  ==============================================================================
                      ##### WWDG specific features #####
  ==============================================================================
  [..]
    Once enabled the WWDG generates a system reset on expiry of a programmed
    time period, unless the program refreshes the counter (T[6;0] downcounter)
    before reaching 0x3F value (i.e. a reset is generated when the counter
    value rolls over from 0x40 to 0x3F).

    (+) An MCU reset is also generated if the counter value is refreshed
        before the counter has reached the refresh window value. This
        implies that the counter must be refreshed in a limited window.

    (+) Once enabled the WWDG cannot be disabled except by a system reset.

    (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has
        occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)).

    (+) The WWDG downcounter input clock is derived from the APB clock divided
        by a programmable prescaler.

    (+) WWDG downcounter clock (Hz) = PCLK1 / (4096 * Prescaler)

    (+) WWDG timeout (ms) = (1000 * (T[5;0] + 1)) / (WWDG downcounter clock)
        where T[5;0] are the lowest 6 bits of downcounter.

    (+) WWDG Counter refresh is allowed between the following limits :
        (++) min time (ms) = (1000 * (T[5;0] - Window)) / (WWDG downcounter clock)
        (++) max time (ms) = (1000 * (T[5;0] - 0x40)) / (WWDG downcounter clock)

    (+) Min-max timeout value @80 MHz(PCLK1): ~51.2 us / ~26.22 ms

    (+) The Early Wakeup Interrupt (EWI) can be used if specific safety
        operations or data logging must be performed before the actual reset is
        generated. When the downcounter reaches the value 0x40, an EWI interrupt
        is generated and the corresponding interrupt service routine (ISR) can
        be used to trigger specific actions (such as communications or data
        logging), before resetting the device.
        In some applications, the EWI interrupt can be used to manage a software
        system check and/or system recovery/graceful degradation, without
        generating a WWDG reset. In this case, the corresponding interrupt
        service routine (ISR) should reload the WWDG counter to avoid the WWDG
        reset, then trigger the required actions.
        Note:When the EWI interrupt cannot be served, e.g. due to a system lock
        in a higher priority task, the WWDG reset will eventually be generated.

    (+) Debug mode : When the microcontroller enters debug mode (core halted),
        the WWDG counter either continues to work normally or stops, depending
        on DBG_WWDG_STOP configuration bit in DBG module, accessible through
        __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().

    (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup
        Interrupt mode using using HAL_WWDG_Init() function.
        This enables WWDG peripheral and the downcounter starts downcounting
        from given counter value.
        Init function can be called again to modify all watchdog parameters,
        however if EWI mode has been set once, it can't be clear until next
        reset.

    (+) The application program must refresh the WWDG counter at regular
        intervals during normal operation to prevent an MCU reset using
        HAL_WWDG_Refresh() function. This operation must occur only when
        the counter is lower than the window value already programmed.

    (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when
        the counter reaches 0x40. User can add his own code in weak function
        HAL_WWDG_EarlyWakeupCallback().

     *** WWDG HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in WWDG HAL driver.

      (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
      (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32h7xx_hal_wwdg.c.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Structures

  • Data Structure Index
  • Data Fields
Data Structures
Here are the data structures with brief descriptions:
__DMA2D_HandleTypeDef | DMA2D handle Structure definition
__DMA_HandleTypeDef | DMA handle Structure definition
__ETH_BufferTypeDef | ETH Buffers List structure definition
__HRTIM_HandleTypeDef | HRTIM Handle Structure definition
__I2C_HandleTypeDef |
__I2S_HandleTypeDef | I2S handle Structure definition
__MDMA_HandleTypeDef | MDMA handle Structure definition
__SAI_HandleTypeDef |
__SPI_HandleTypeDef | SPI handle Structure definition
ADC_AnalogWDGConfTypeDef | Structure definition of ADC analog watchdog
ADC_ChannelConfTypeDef | Structure definition of ADC channel for regular group
ADC_HandleTypeDef | ADC handle Structure definition
ADC_InitTypeDef | Structure definition of ADC instance and ADC group regular
ADC_InjectionConfigTypeDef | ADC group injected contexts queue configuration
ADC_InjectionConfTypeDef | Structure definition of ADC group injected and ADC channel affected to ADC group injected
ADC_InjOversamplingTypeDef | ADC Injected Conversion Oversampling structure definition
ADC_MultiModeTypeDef | Structure definition of ADC MultiMode
ADC_OversamplingTypeDef | ADC Regular Conversion Oversampling structure definition
CEC_HandleTypeDef | CEC handle Structure definition
CEC_InitTypeDef | CEC Init Structure definition
COMP_HandleTypeDef | COMP Handle Structure definition
COMP_InitTypeDef | COMP Init structure definition
CRC_HandleTypeDef |
CRC_InitTypeDef |
CRYP_ConfigTypeDef | CRYP Init Structure definition
CRYP_HandleTypeDef | CRYP handle Structure definition
DAC_ChannelConfTypeDef | DAC Configuration regular Channel structure definition
DAC_HandleTypeDef | DAC handle Structure definition
DAC_SampleAndHoldConfTypeDef | DAC Configuration sample and hold Channel structure definition
DCMI_CodesInitTypeDef | DCMI Embedded Synchronisation CODE Init structure definition
DCMI_HandleTypeDef | DCMI handle Structure definition
DCMI_InitTypeDef | DCMI Init structure definition
DFSDM_Channel_AwdTypeDef | DFSDM channel analog watchdog structure definition
DFSDM_Channel_HandleTypeDef | DFSDM channel handle structure definition
DFSDM_Channel_InitTypeDef | DFSDM channel init structure definition
DFSDM_Channel_InputTypeDef | DFSDM channel input structure definition
DFSDM_Channel_OutputClockTypeDef | DFSDM channel output clock structure definition
DFSDM_Channel_SerialInterfaceTypeDef | DFSDM channel serial interface structure definition
DFSDM_Filter_AwdParamTypeDef | DFSDM filter analog watchdog parameters structure definition
DFSDM_Filter_FilterParamTypeDef | DFSDM filter parameters structure definition
DFSDM_Filter_HandleTypeDef | DFSDM filter handle structure definition
DFSDM_Filter_InitTypeDef | DFSDM filter init structure definition
DFSDM_Filter_InjectedParamTypeDef | DFSDM filter injected conversion parameters structure definition
DFSDM_Filter_RegularParamTypeDef | DFSDM filter regular conversion parameters structure definition
DMA2D_CLUTCfgTypeDef | DMA2D CLUT Structure definition
DMA2D_ColorTypeDef | DMA2D color Structure definition
DMA2D_InitTypeDef | DMA2D Init structure definition
DMA2D_LayerCfgTypeDef | DMA2D Layer structure definition
DMA_Base_Registers |
DMA_InitTypeDef | DMA Configuration Structure definition
ETH_DMAConfigTypeDef | ETH DMA Configuration Structure definition
ETH_HandleTypeDef | ETH Handle Structure definition
ETH_InitTypeDef | ETH Init Structure definition
ETH_L3FilterConfigTypeDef | ETH L3 filter structure definition
ETH_L4FilterConfigTypeDef | ETH L4 filter structure definition
ETH_MACConfigTypeDef | ETH MAC Configuration Structure definition
ETH_MACFilterConfigTypeDef | ETH MAC filter structure definition
ETH_PowerDownConfigTypeDef | ETH Power Down structure definition
ETH_RxDescListTypeDef | DMA Receive Descriptors Wrapper structure definition
ETH_RxPacketInfo | Received Packet Information structure definition
ETH_RxVLANConfigTypeDef | ETH RX VLAN structure definition
ETH_TxDescListTypeDef | DMA Transmit Descriptors Wrapper structure definition
ETH_TxPacketConfig | Transmit Packet Configuration structure definition
ETH_TxVLANConfigTypeDef | ETH TX VLAN structure definition
FDCAN_ClkCalUnitTypeDef | FDCAN clock calibration unit structure definition
FDCAN_ErrorCountersTypeDef | FDCAN Error Counters structure definition
FDCAN_FilterTypeDef | FDCAN filter structure definition
FDCAN_HandleTypeDef | FDCAN handle structure definition
FDCAN_HpMsgStatusTypeDef | FDCAN High Priority Message Status structure definition
FDCAN_InitTypeDef | FDCAN Init structure definition
FDCAN_MsgRamAddressTypeDef | FDCAN Message RAM blocks
FDCAN_ProtocolStatusTypeDef | FDCAN Protocol Status structure definition
FDCAN_RxHeaderTypeDef | FDCAN Rx header structure definition
FDCAN_TriggerTypeDef | FDCAN Trigger structure definition
FDCAN_TT_ConfigTypeDef | FDCAN TT Init structure definition
FDCAN_TTOperationStatusTypeDef | FDCAN TT Operation Status structure definition
FDCAN_TxEventFifoTypeDef | FDCAN Tx event FIFO structure definition
FDCAN_TxHeaderTypeDef | FDCAN Tx header structure definition
FLASH_EraseInitTypeDef | FLASH Erase structure definition
FLASH_OBProgramInitTypeDef | FLASH Option Bytes Program structure definition
FLASH_ProcessTypeDef | FLASH handle Structure definition
GPIO_InitTypeDef | GPIO Init structure definition
HAL_DMA_MuxRequestGeneratorConfigTypeDef | HAL DMAMUX request generator parameters structure definition
HAL_DMA_MuxSyncConfigTypeDef | HAL DMAMUX Synchronization configuration structure definition
HAL_MMC_CardCIDTypedef |
HAL_MMC_CardCSDTypeDef |
HAL_MMC_CardInfoTypeDef | MMC Card Information Structure definition
HAL_SD_CardCIDTypedef |
HAL_SD_CardCSDTypedef |
HAL_SD_CardInfoTypeDef | SD Card Information Structure definition
HAL_SD_CardStatusTypedef |
HASH_HandleTypeDef | HASH Handle Structure definition
HASH_InitTypeDef | HASH Configuration Structure definition
HCD_HandleTypeDef |
HRTIM_ADCTriggerCfgTypeDef | ADC trigger configuration definition
HRTIM_BurstModeCfgTypeDef | Burst mode configuration definition
HRTIM_CaptureCfgTypeDef | Capture unit configuration definition
HRTIM_ChopperModeCfgTypeDef | Chopper mode configuration definition
HRTIM_CompareCfgTypeDef | Compare unit configuration definition
HRTIM_DeadTimeCfgTypeDef | Dead time feature configuration definition
HRTIM_EventCfgTypeDef | External event channel configuration definition
HRTIM_FaultCfgTypeDef | Fault channel configuration definition
HRTIM_InitTypeDef | HRTIM Configuration Structure definition - Time base related parameters
HRTIM_OutputCfgTypeDef | Output configuration definition
HRTIM_SimpleCaptureChannelCfgTypeDef | Simple capture mode configuration definition
HRTIM_SimpleOCChannelCfgTypeDef | Simple output compare mode configuration definition
HRTIM_SimpleOnePulseChannelCfgTypeDef | Simple One Pulse mode configuration definition
HRTIM_SimplePWMChannelCfgTypeDef | Simple PWM output mode configuration definition
HRTIM_TimeBaseCfgTypeDef | Simple output compare mode configuration definition
HRTIM_TimerCfgTypeDef | Timer configuration definition
HRTIM_TimerEventFilteringCfgTypeDef | External event filtering in timing units configuration definition
HRTIM_TimerParamTypeDef | HRTIM Timer Structure definition
I2C_InitTypeDef |
I2S_InitTypeDef | I2S Init structure definition
IRDA_HandleTypeDef | IRDA handle Structure definition
IRDA_InitTypeDef | IRDA Init Structure definition
IWDG_HandleTypeDef | IWDG Handle Structure definition
IWDG_InitTypeDef | IWDG Init structure definition
JPEG_AC_HuffCodeTableTypeDef |
JPEG_ACHuffTableTypeDef |
JPEG_ConfTypeDef |
JPEG_DC_HuffCodeTableTypeDef |
JPEG_DCHuffTableTypeDef |
JPEG_HandleTypeDef |
LPTIM_ClockConfigTypeDef | LPTIM Clock configuration definition
LPTIM_HandleTypeDef | LPTIM handle Structure definition
LPTIM_InitTypeDef | LPTIM Initialization Structure definition
LPTIM_TriggerConfigTypeDef | LPTIM Trigger configuration definition
LPTIM_ULPClockConfigTypeDef | LPTIM Clock configuration definition
LTDC_ColorTypeDef | LTDC color structure definition
LTDC_HandleTypeDef | LTDC handle Structure definition
LTDC_InitTypeDef | LTDC Init structure definition
LTDC_LayerCfgTypeDef | LTDC Layer structure definition
MDIOS_HandleTypeDef |
MDIOS_InitTypeDef |
MDMA_InitTypeDef | MDMA Configuration Structure definition
MDMA_LinkNodeConfTypeDef | HAL MDMA linked list node configuration structure definition
MDMA_LinkNodeTypeDef | HAL MDMA linked list node structure definition
MMC_HandleTypeDef | MMC handle Structure definition
MPU_Region_InitTypeDef |
NAND_AddressTypeDef | NAND Memory address Structure definition
NAND_DeviceConfigTypeDef | NAND Memory info Structure definition
NAND_HandleTypeDef | NAND handle Structure definition
NAND_IDTypeDef | NAND Memory electronic signature Structure definition
NOR_CFITypeDef | FMC NOR CFI typedef
NOR_HandleTypeDef | NOR handle Structure definition
NOR_IDTypeDef | FMC NOR ID typedef
OPAMP_HandleTypeDef | OPAMP Handle Structure definition
OPAMP_InitTypeDef | OPAMP Init structure definition
PCD_HandleTypeDef | PCD Handle Structure definition
PLL1_ClocksTypeDef | RCC PLL1 Clocks structure definition
PLL2_ClocksTypeDef | RCC PLL2 Clocks structure definition
PLL3_ClocksTypeDef | RCC PLL3 Clocks structure definition
PWR_PVDTypeDef | PWR PVD configuration structure definition
PWREx_AVDTypeDef | PWREx AVD configuration structure definition
PWREx_WakeupPinTypeDef | PWREx Wakeup pin configuration structure definition
QSPI_AutoPollingTypeDef | QSPI Auto Polling mode configuration structure definition
QSPI_CommandTypeDef | QSPI Command structure definition
QSPI_HandleTypeDef | QSPI Handle Structure definition
QSPI_InitTypeDef | QSPI Init structure definition
QSPI_MemoryMappedTypeDef | QSPI Memory Mapped mode configuration structure definition
RCC_ClkInitTypeDef | RCC System, AHB and APB busses clock configuration structure definition
RCC_CRSInitTypeDef | RCC_CRS Init structure definition
RCC_CRSSynchroInfoTypeDef | RCC_CRS Synchronization structure definition
RCC_OscInitTypeDef | RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition
RCC_PeriphCLKInitTypeDef | RCC extended clocks structure definition
RCC_PLL2InitTypeDef | PLL2 Clock structure definition
RCC_PLL3InitTypeDef | PLL3 Clock structure definition
RCC_PLLInitTypeDef | RCC PLL configuration structure definition
RNG_HandleTypeDef |
RNG_InitTypeDef |
RTC_AlarmTypeDef | RTC Alarm structure definition
RTC_DateTypeDef | RTC Date structure definition
RTC_HandleTypeDef | Time Handle Structure definition
RTC_InitTypeDef | RTC Configuration Structure definition
RTC_TamperTypeDef | RTC Tamper structure definition
RTC_TimeTypeDef | RTC Time structure definition
SAI_FrameInitTypeDef |
SAI_InitTypeDef |
SAI_PdmInitTypeDef |
SAI_SlotInitTypeDef |
SAIEx_PdmMicDelayParamTypeDef | PDM microphone delay structure definition
SD_HandleTypeDef | SD handle Structure definition
SDRAM_HandleTypeDef | SDRAM handle Structure definition
SMARTCARD_AdvFeatureInitTypeDef | SMARTCARD advanced features initalization structure definition
SMARTCARD_HandleTypeDef | SMARTCARD handle Structure definition
SMARTCARD_InitTypeDef | SMARTCARD Init Structure definition
SMBUS_HandleTypeDef |
SMBUS_InitTypeDef |
SPDIFRX_HandleTypeDef | SPDIFRX handle Structure definition
SPDIFRX_InitTypeDef | SPDIFRX Init structure definition
SPDIFRX_SetDataFormatTypeDef | SPDIFRX SetDataFormat structure definition
SPI_InitTypeDef | SPI Configuration Structure definition
SRAM_HandleTypeDef | SRAM handle Structure definition
SWPMI_HandleTypeDef | SWPMI handle Structure definition
SWPMI_InitTypeDef | SWPMI Init Structure definition
TIM_Base_InitTypeDef | TIM Time base Configuration Structure definition
TIM_BreakDeadTimeConfigTypeDef | TIM Break input(s) and Dead time configuration Structure definition
TIM_ClearInputConfigTypeDef | Clear Input Configuration Handle Structure definition
TIM_ClockConfigTypeDef | Clock Configuration Handle Structure definition
TIM_Encoder_InitTypeDef | TIM Encoder Configuration Structure definition
TIM_HallSensor_InitTypeDef | TIM Hall sensor Configuration Structure definition
TIM_HandleTypeDef | TIM Time Base Handle Structure definition
TIM_IC_InitTypeDef | TIM Input Capture Configuration Structure definition
TIM_MasterConfigTypeDef | TIM Master configuration Structure definition
TIM_OC_InitTypeDef | TIM Output Compare Configuration Structure definition
TIM_OnePulse_InitTypeDef | TIM One Pulse Mode Configuration Structure definition
TIM_SlaveConfigTypeDef | TIM Slave configuration Structure definition
TIMEx_BreakInputConfigTypeDef | TIM Break/Break2 input configuration
UART_AdvFeatureInitTypeDef | UART Advanced Features initalization structure definition
UART_HandleTypeDef | UART handle Structure definition
UART_InitTypeDef | UART Init Structure definition
UART_WakeUpTypeDef | UART wake up from stop mode parameters
USART_HandleTypeDef | USART handle Structure definition
USART_InitTypeDef | USART Init Structure definition
WWDG_HandleTypeDef | WWDG handle Structure definition
WWDG_InitTypeDef | WWDG Init structure definition
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Data Structure Index

  • Data Structure Index
  • Data Fields
Data Structure Index
A | C | D | E | F | G | H | I | J | L | M | N | O | P | Q | R | S | T | U | W | _
A
ETH_L3FilterConfigTypeDef HRTIM_DeadTimeCfgTypeDef NAND_DeviceConfigTypeDef SDRAM_HandleTypeDef
ETH_L4FilterConfigTypeDef HRTIM_EventCfgTypeDef NAND_HandleTypeDef SMARTCARD_AdvFeatureInitTypeDef
ADC_AnalogWDGConfTypeDef ETH_MACConfigTypeDef HRTIM_FaultCfgTypeDef NAND_IDTypeDef SMARTCARD_HandleTypeDef
ADC_ChannelConfTypeDef ETH_MACFilterConfigTypeDef HRTIM_InitTypeDef NOR_CFITypeDef SMARTCARD_InitTypeDef
ADC_HandleTypeDef ETH_PowerDownConfigTypeDef HRTIM_OutputCfgTypeDef NOR_HandleTypeDef SMBUS_HandleTypeDef
ADC_InitTypeDef ETH_RxDescListTypeDef HRTIM_SimpleCaptureChannelCfgTypeDef NOR_IDTypeDef SMBUS_InitTypeDef
ADC_InjectionConfigTypeDef ETH_RxPacketInfo HRTIM_SimpleOCChannelCfgTypeDef
O
SPDIFRX_HandleTypeDef
ADC_InjectionConfTypeDef ETH_RxVLANConfigTypeDef HRTIM_SimpleOnePulseChannelCfgTypeDef SPDIFRX_InitTypeDef
ADC_InjOversamplingTypeDef ETH_TxDescListTypeDef HRTIM_SimplePWMChannelCfgTypeDef OPAMP_HandleTypeDef SPDIFRX_SetDataFormatTypeDef
ADC_MultiModeTypeDef ETH_TxPacketConfig HRTIM_TimeBaseCfgTypeDef OPAMP_InitTypeDef SPI_InitTypeDef
ADC_OversamplingTypeDef ETH_TxVLANConfigTypeDef HRTIM_TimerCfgTypeDef
P
SRAM_HandleTypeDef
C
F
HRTIM_TimerEventFilteringCfgTypeDef SWPMI_HandleTypeDef
HRTIM_TimerParamTypeDef PCD_HandleTypeDef SWPMI_InitTypeDef
CEC_HandleTypeDef FDCAN_ClkCalUnitTypeDef
I
PLL1_ClocksTypeDef
T
CEC_InitTypeDef FDCAN_ErrorCountersTypeDef PLL2_ClocksTypeDef
COMP_HandleTypeDef FDCAN_FilterTypeDef I2C_InitTypeDef PLL3_ClocksTypeDef TIM_Base_InitTypeDef
COMP_InitTypeDef FDCAN_HandleTypeDef I2S_InitTypeDef PWR_PVDTypeDef TIM_BreakDeadTimeConfigTypeDef
CRC_HandleTypeDef FDCAN_HpMsgStatusTypeDef IRDA_HandleTypeDef PWREx_AVDTypeDef TIM_ClearInputConfigTypeDef
CRC_InitTypeDef FDCAN_InitTypeDef IRDA_InitTypeDef PWREx_WakeupPinTypeDef TIM_ClockConfigTypeDef
CRYP_ConfigTypeDef FDCAN_MsgRamAddressTypeDef IWDG_HandleTypeDef
Q
TIM_Encoder_InitTypeDef
CRYP_HandleTypeDef FDCAN_ProtocolStatusTypeDef IWDG_InitTypeDef TIM_HallSensor_InitTypeDef
D
FDCAN_RxHeaderTypeDef
J
QSPI_AutoPollingTypeDef TIM_HandleTypeDef
FDCAN_TriggerTypeDef QSPI_CommandTypeDef TIM_IC_InitTypeDef
DAC_ChannelConfTypeDef FDCAN_TT_ConfigTypeDef JPEG_AC_HuffCodeTableTypeDef QSPI_HandleTypeDef TIM_MasterConfigTypeDef
DAC_HandleTypeDef FDCAN_TTOperationStatusTypeDef JPEG_ACHuffTableTypeDef QSPI_InitTypeDef TIM_OC_InitTypeDef
DAC_SampleAndHoldConfTypeDef FDCAN_TxEventFifoTypeDef JPEG_ConfTypeDef QSPI_MemoryMappedTypeDef TIM_OnePulse_InitTypeDef
DCMI_CodesInitTypeDef FDCAN_TxHeaderTypeDef JPEG_DC_HuffCodeTableTypeDef
R
TIM_SlaveConfigTypeDef
DCMI_HandleTypeDef FLASH_EraseInitTypeDef JPEG_DCHuffTableTypeDef TIMEx_BreakInputConfigTypeDef
DCMI_InitTypeDef FLASH_OBProgramInitTypeDef JPEG_HandleTypeDef RCC_ClkInitTypeDef
U
DFSDM_Channel_AwdTypeDef FLASH_ProcessTypeDef
L
RCC_CRSInitTypeDef
DFSDM_Channel_HandleTypeDef
G
RCC_CRSSynchroInfoTypeDef UART_AdvFeatureInitTypeDef
DFSDM_Channel_InitTypeDef LPTIM_ClockConfigTypeDef RCC_OscInitTypeDef UART_HandleTypeDef
DFSDM_Channel_InputTypeDef GPIO_InitTypeDef LPTIM_HandleTypeDef RCC_PeriphCLKInitTypeDef UART_InitTypeDef
DFSDM_Channel_OutputClockTypeDef
H
LPTIM_InitTypeDef RCC_PLL2InitTypeDef UART_WakeUpTypeDef
DFSDM_Channel_SerialInterfaceTypeDef LPTIM_TriggerConfigTypeDef RCC_PLL3InitTypeDef USART_HandleTypeDef
DFSDM_Filter_AwdParamTypeDef HAL_DMA_MuxRequestGeneratorConfigTypeDef LPTIM_ULPClockConfigTypeDef RCC_PLLInitTypeDef USART_InitTypeDef
DFSDM_Filter_FilterParamTypeDef HAL_DMA_MuxSyncConfigTypeDef LTDC_ColorTypeDef RNG_HandleTypeDef
W
DFSDM_Filter_HandleTypeDef HAL_MMC_CardCIDTypedef LTDC_HandleTypeDef RNG_InitTypeDef
DFSDM_Filter_InitTypeDef HAL_MMC_CardCSDTypeDef LTDC_InitTypeDef RTC_AlarmTypeDef WWDG_HandleTypeDef
DFSDM_Filter_InjectedParamTypeDef HAL_MMC_CardInfoTypeDef LTDC_LayerCfgTypeDef RTC_DateTypeDef WWDG_InitTypeDef
DFSDM_Filter_RegularParamTypeDef HAL_SD_CardCIDTypedef
M
RTC_HandleTypeDef
_
DMA2D_CLUTCfgTypeDef HAL_SD_CardCSDTypedef RTC_InitTypeDef
DMA2D_ColorTypeDef HAL_SD_CardInfoTypeDef MDIOS_HandleTypeDef RTC_TamperTypeDef __DMA2D_HandleTypeDef
DMA2D_InitTypeDef HAL_SD_CardStatusTypedef MDIOS_InitTypeDef RTC_TimeTypeDef __DMA_HandleTypeDef
DMA2D_LayerCfgTypeDef HASH_HandleTypeDef MDMA_InitTypeDef
S
__ETH_BufferTypeDef
DMA_Base_Registers HASH_InitTypeDef MDMA_LinkNodeConfTypeDef __HRTIM_HandleTypeDef
DMA_InitTypeDef HCD_HandleTypeDef MDMA_LinkNodeTypeDef SAI_FrameInitTypeDef __I2C_HandleTypeDef
E
HRTIM_ADCTriggerCfgTypeDef MMC_HandleTypeDef SAI_InitTypeDef __I2S_HandleTypeDef
HRTIM_BurstModeCfgTypeDef MPU_Region_InitTypeDef SAI_PdmInitTypeDef __MDMA_HandleTypeDef
ETH_DMAConfigTypeDef HRTIM_CaptureCfgTypeDef
N
SAI_SlotInitTypeDef __SAI_HandleTypeDef
ETH_HandleTypeDef HRTIM_ChopperModeCfgTypeDef SAIEx_PdmMicDelayParamTypeDef __SPI_HandleTypeDef
ETH_InitTypeDef HRTIM_CompareCfgTypeDef NAND_AddressTypeDef SD_HandleTypeDef
A | C | D | E | F | G | H | I | J | L | M | N | O | P | Q | R | S | T | U | W | _
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: C:/Workspace/STM32_H7/STM32H7xx_HAL_Driver/Trunk/Drivers/STM32H7xx_HAL_Driver/Inc/ Directory Reference

  • Drivers
  • STM32H7xx_HAL_Driver
  • Inc
Inc Directory Reference

Files

file | stm32h7xx_hal.h [code]

This file contains all the functions prototypes for the HAL module driver.

file | stm32h7xx_hal_adc.h [code]

Header file of ADC HAL module.

file | stm32h7xx_hal_adc_ex.h [code]

Header file of ADC HAL extended module.

file | stm32h7xx_hal_cec.h [code]

Header file of CEC HAL module.

file | stm32h7xx_hal_comp.h [code]

Header file of COMP HAL module.

file | stm32h7xx_hal_cortex.h [code]

Header file of CORTEX HAL module.

file | stm32h7xx_hal_crc.h [code]

Header file of CRC HAL module.

file | stm32h7xx_hal_crc_ex.h [code]

Header file of CRC HAL extension module.

file | stm32h7xx_hal_cryp.h [code]

Header file of CRYP HAL module.

file | stm32h7xx_hal_cryp_ex.h [code]

Header file of CRYP HAL Extension module.

file | stm32h7xx_hal_dac.h [code]

Header file of DAC HAL module.

file | stm32h7xx_hal_dac_ex.h [code]

Header file of DAC HAL Extended module.

file | stm32h7xx_hal_dcmi.h [code]

Header file of DCMI HAL module.

file | stm32h7xx_hal_dfsdm.h [code]

Header file of DFSDM HAL module.

file | stm32h7xx_hal_dma.h [code]

Header file of DMA HAL module.

file | stm32h7xx_hal_dma2d.h [code]

Header file of DMA2D HAL module.

file | stm32h7xx_hal_dma_ex.h [code]

Header file of DMA HAL extension module.

file | stm32h7xx_hal_eth.h [code]

Header file of ETH HAL module.

file | stm32h7xx_hal_eth_ex.h [code]

Header file of ETH HAL Extended module.

file | stm32h7xx_hal_fdcan.h [code]

Header file of FDCAN HAL module.

file | stm32h7xx_hal_flash.h [code]

Header file of FLASH HAL module.

file | stm32h7xx_hal_flash_ex.h [code]

Header file of FLASH HAL module.

file | stm32h7xx_hal_gpio.h [code]

Header file of GPIO HAL module.

file | stm32h7xx_hal_gpio_ex.h [code]

Header file of GPIO HAL Extension module.

file | stm32h7xx_hal_hash.h [code]

Header file of HASH HAL module.

file | stm32h7xx_hal_hash_ex.h [code]

Header file of HASH HAL module.

file | stm32h7xx_hal_hcd.h [code]

Header file of HCD HAL module.

file | stm32h7xx_hal_hrtim.h [code]

Header file of HRTIM HAL module.

file | stm32h7xx_hal_hsem.h [code]

Header file of HSEM HAL module.

file | stm32h7xx_hal_i2c.h [code]

Header file of I2C HAL module.

file | stm32h7xx_hal_i2c_ex.h [code]

Header file of I2C HAL Extension module.

file | stm32h7xx_hal_i2s.h [code]

Header file of I2S HAL module.

file | stm32h7xx_hal_i2s_ex.h [code]

Header file of I2S HAL module.

file | stm32h7xx_hal_irda.h [code]

Header file of IRDA HAL module.

file | stm32h7xx_hal_irda_ex.h [code]

Header file of IRDA HAL Extended module.

file | stm32h7xx_hal_iwdg.h [code]

Header file of IWDG HAL module.

file | stm32h7xx_hal_jpeg.h [code]

Header file of JPEG HAL module.

file | stm32h7xx_hal_lptim.h [code]

Header file of LPTIM HAL module.

file | stm32h7xx_hal_ltdc.h [code]

Header file of LTDC HAL module.

file | stm32h7xx_hal_mdios.h [code]

Header file of MDIOS HAL module.

file | stm32h7xx_hal_mdma.h [code]

Header file of DMA HAL module.

file | stm32h7xx_hal_mmc.h [code]

Header file of MMC HAL module.

file | stm32h7xx_hal_mmc_ex.h [code]

Header file of MMC HAL extended module.

file | stm32h7xx_hal_nand.h [code]

Header file of NAND HAL module.

file | stm32h7xx_hal_nor.h [code]

Header file of NOR HAL module.

file | stm32h7xx_hal_opamp.h [code]

Header file of OPAMP HAL module.

file | stm32h7xx_hal_opamp_ex.h [code]

Header file of OPAMP HAL Extended module.

file | stm32h7xx_hal_pcd.h [code]

Header file of PCD HAL module.

file | stm32h7xx_hal_pcd_ex.h [code]

Header file of PCD HAL module.

file | stm32h7xx_hal_pwr.h [code]

Header file of PWR HAL module.

file | stm32h7xx_hal_pwr_ex.h [code]

Header file of PWR HAL Extension module.

file | stm32h7xx_hal_qspi.h [code]

Header file of QSPI HAL module.

file | stm32h7xx_hal_rcc.h [code]

Header file of RCC HAL module.

file | stm32h7xx_hal_rcc_ex.h [code]

Header file of RCC HAL Extension module.

file | stm32h7xx_hal_rng.h [code]

Header file of RNG HAL module.

file | stm32h7xx_hal_rtc.h [code]

Header file of RTC HAL module.

file | stm32h7xx_hal_rtc_ex.h [code]

Header file of RTC HAL Extension module.

file | stm32h7xx_hal_sai.h [code]

Header file of SAI HAL module.

file | stm32h7xx_hal_sai_ex.h [code]

Header file of SAI HAL extended module.

file | stm32h7xx_hal_sd.h [code]

Header file of SD HAL module.

file | stm32h7xx_hal_sd_ex.h [code]

Header file of SD HAL extended module.

file | stm32h7xx_hal_sdram.h [code]

Header file of SDRAM HAL module.

file | stm32h7xx_hal_smartcard.h [code]

Header file of SMARTCARD HAL module.

file | stm32h7xx_hal_smartcard_ex.h [code]

Header file of SMARTCARD HAL Extended module.

file | stm32h7xx_hal_smbus.h [code]

Header file of SMBUS HAL module.

file | stm32h7xx_hal_spdifrx.h [code]

Header file of SPDIFRX HAL module.

file | stm32h7xx_hal_spi.h [code]

Header file of SPI HAL module.

file | stm32h7xx_hal_spi_ex.h [code]

Header file of SPI HAL Extended module.

file | stm32h7xx_hal_sram.h [code]

Header file of SRAM HAL module.

file | stm32h7xx_hal_swpmi.h [code]

Header file of SWPMI HAL module.

file | stm32h7xx_hal_tim.h [code]

Header file of TIM HAL module.

file | stm32h7xx_hal_tim_ex.h [code]

Header file of TIM HAL Extended module.

file | stm32h7xx_hal_uart.h [code]

Header file of UART HAL module.

file | stm32h7xx_hal_uart_ex.h [code]

Header file of UART HAL Extended module.

file | stm32h7xx_hal_usart.h [code]

Header file of USART HAL module.

file | stm32h7xx_hal_usart_ex.h [code]

Header file of USART HAL Extended module.

file | stm32h7xx_hal_wwdg.h [code]

Header file of WWDG HAL module.

Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: C:/Workspace/STM32_H7/STM32H7xx_HAL_Driver/Trunk/Drivers/ Directory Reference

  • Drivers
Drivers Directory Reference

Directories

directory STM32H7xx_HAL_Driver
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: C:/Workspace/STM32_H7/STM32H7xx_HAL_Driver/Trunk/Drivers/STM32H7xx_HAL_Driver/Src/ Directory Reference

  • Drivers
  • STM32H7xx_HAL_Driver
  • Src
Src Directory Reference

Files

file | stm32h7xx_hal.c [code]

HAL module driver. This is the common part of the HAL initialization.

file | stm32h7xx_hal_adc.c [code]

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and deinitialization functions ++ Initialization and Configuration of ADC + Operation functions ++ Start, stop, get result of regular conversions of regular using 3 possible modes: polling, interruption or DMA. + Control functions ++ Channels configuration on regular group ++ Analog Watchdog configuration + State functions ++ ADC state machine management ++ Interrupts and flags management Other functions (extended functions) are available in file "stm32h7xx_hal_adc_ex.c".

file | stm32h7xx_hal_adc_ex.c [code]

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Operation functions ++ Start, stop, get result of conversions of injected group, using 2 possible modes: polling, interruption. ++ Calibration +++ ADC automatic self-calibration +++ Calibration factors get or set ++ Multimode feature when available + Control functions ++ Channels configuration on injected group + State functions ++ Injected group queues management Other functions (generic functions) are available in file "stm32h7xx_hal_adc.c".

file | stm32h7xx_hal_cec.c [code]

CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization function + IO operation function + Peripheral Control function.

file | stm32h7xx_hal_comp.c [code]

COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode + Start/Stop operation functions in interrupt mode + Peripheral control functions + Peripheral state functions.

file | stm32h7xx_hal_cortex.c [code]

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32h7xx_hal_crc.c [code]

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions.

file | stm32h7xx_hal_crc_ex.c [code]

Extended CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the CRC peripheral: + Initialization/de-initialization functions.

file | stm32h7xx_hal_cryp.c [code]

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization and de-initialization functions + AES processing functions + DES processing functions + TDES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions.

file | stm32h7xx_hal_cryp_ex.c [code]

Extended CRYP HAL module driver This file provides firmware functions to manage the following functionalities of CRYP extension peripheral: + Extended AES processing functions.

file | stm32h7xx_hal_dac.c [code]

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32h7xx_hal_dac_ex.c [code]

Extended DAC HAL module driver. This file provides firmware functions to manage the extended functionalities of DAC peripheral.

file | stm32h7xx_hal_dcmi.c [code]

DCMI HAL module driver This file provides firmware functions to manage the following functionalities of the Digital Camera Interface (DCMI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32h7xx_hal_dfsdm.c [code]

This file provides firmware functions to manage the following functionalities of the Digital Filter for Sigma-Delta Modulators (DFSDM) peripherals: + Initialization and configuration of channels and filters + Regular channels configuration + Injected channels configuration + Regular/Injected Channels DMA Configuration + Interrupts and flags management + Analog watchdog feature + Short-circuit detector feature + Extremes detector feature + Clock absence detector feature + Break generation on analog watchdog or short-circuit event.

file | stm32h7xx_hal_dma.c [code]

DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions.

file | stm32h7xx_hal_dma2d.c [code]

DMA2D HAL module driver. This file provides firmware functions to manage the following functionalities of the DMA2D peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32h7xx_hal_dma_ex.c [code]

DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions.

file | stm32h7xx_hal_eth.c [code]

ETH HAL module driver. This file provides firmware functions to manage the following functionalities of the Ethernet (ETH) peripheral: + Initialization and deinitialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32h7xx_hal_eth_ex.c [code]

ETH HAL Extended module driver.

file | stm32h7xx_hal_fdcan.c [code]

FDCAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Flexible DataRate Controller Area Network (FDCAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Configuration and Control functions + Peripheral State and Error functions.

file | stm32h7xx_hal_flash.c [code]

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions.

file | stm32h7xx_hal_flash_ex.c [code]

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extension peripheral: + Extended programming operations functions.

file | stm32h7xx_hal_gpio.c [code]

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions.

file | stm32h7xx_hal_hash.c [code]

HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral: + Initialization and de-initialization methods + HASH or HMAC processing in polling mode + HASH or HMAC processing in interrupt mode + HASH or HMAC processing in DMA mode + Peripheral State methods + HASH or HMAC processing suspension/resumption.

file | stm32h7xx_hal_hash_ex.c [code]

Extended HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral for SHA-224 and SHA-256 alogrithms: + HASH or HMAC processing in polling mode + HASH or HMAC processing in interrupt mode + HASH or HMAC processing in DMA mode Additionally, this file provides functions to manage HMAC multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224 and SHA-256.

file | stm32h7xx_hal_hcd.c [code]

HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32h7xx_hal_hrtim.c [code]

HRTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the High Resolution Timer (HRTIM) peripheral: + HRTIM Initialization + Timer Time Base Unit Configuration + Simple Time Base Start/Stop + Simple Time Base Start/Stop Interrupt + Simple Time Base Start/Stop DMA Request + Simple Output Compare/PWM Channel Configuration + Simple Output Compare/PWM Channel Start/Stop Interrupt + Simple Output Compare/PWM Channel Start/Stop DMA Request + Simple Input Capture Channel Configuration + Simple Input Capture Channel Start/Stop Interrupt + Simple Input Capture Channel Start/Stop DMA Request + Simple One Pulse Channel Configuration + Simple One Pulse Channel Start/Stop Interrupt + HRTIM External Synchronization Configuration + HRTIM Burst Mode Controller Configuration + HRTIM Burst Mode Controller Enabling + HRTIM External Events Conditioning Configuration + HRTIM Faults Conditioning Configuration + HRTIM Faults Enabling + HRTIM ADC trigger Configuration + Waveform Timer Configuration + Waveform Event Filtering Configuration + Waveform Dead Time Insertion Configuration + Waveform Chopper Mode Configuration + Waveform Compare Unit Configuration + Waveform Capture Unit Configuration + Waveform Output Configuration + Waveform Counter Start/Stop + Waveform Counter Start/Stop Interrupt + Waveform Counter Start/Stop DMA Request + Waveform Output Enabling + Waveform Output Level Set/Get + Waveform Output State Get + Waveform Burst DMA Operation Configuration + Waveform Burst DMA Operation Start + Waveform Timer Counter Software Reset + Waveform Capture Software Trigger + Waveform Burst Mode Controller Software Trigger + Waveform Timer Pre-loadable Registers Update Enabling + Waveform Timer Pre-loadable Registers Software Update + Waveform Timer Delayed Protection Status Get + Waveform Timer Burst Status Get + Waveform Timer Push-Pull Status Get + Peripheral State Get.

file | stm32h7xx_hal_hsem.c [code]

HSEM HAL module driver. This file provides firmware functions to manage the following functionalities of the semaphore peripheral: + Semaphore Take function (2-Step Procedure) , non blocking + Semaphore FastTake function (1-Step Procedure) , non blocking + Semaphore Status check + Semaphore Clear Key Set and Get + Release and release all functions + Semaphore notification enabling and disabling and callnack functions + IRQ handler management.

file | stm32h7xx_hal_i2c.c [code]

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32h7xx_hal_i2c_ex.c [code]

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions.

file | stm32h7xx_hal_i2s.c [code]

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32h7xx_hal_i2s_ex.c [code]

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of I2S extension peripheral: + IO operation functions + Peripheral Control functions.

file | stm32h7xx_hal_irda.c [code]

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions.

file | stm32h7xx_hal_iwdg.c [code]

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions.

file | stm32h7xx_hal_jpeg.c [code]

JPEG HAL module driver. This file provides firmware functions to manage the following functionalities of the JPEG encoder/decoder peripheral: + Initialization and de-initialization functions + JPEG processing functions encoding and decoding + JPEG decoding Getting Info and encoding configuration setting + JPEG enable/disable header parsing functions (for decoding) + JPEG Input/Output Buffer configuration. + JPEG callback functions + JPEG Abort/Pause/Resume functions + JPEG custom quantization tables setting functions + IRQ handler management + Peripheral State and Error functions.

file | stm32h7xx_hal_lptim.c [code]

LPTIM HAL module driver.

file | stm32h7xx_hal_ltdc.c [code]

LTDC HAL module driver. This file provides firmware functions to manage the following functionalities of the LTDC peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32h7xx_hal_mdios.c [code]

MDIOS HAL module driver. This file provides firmware functions to manage the following functionalities of the MDIOS Peripheral. + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

file | stm32h7xx_hal_mdma.c [code]

This file provides firmware functions to manage the following functionalities of the Master Direct Memory Access (MDMA) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral State and errors functions.

file | stm32h7xx_hal_mmc.c [code]

MMC card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (MMC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + MMC card Control functions.

file | stm32h7xx_hal_mmc_ex.c [code]

MMC card Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (MMC) peripheral: + Extended features functions.

file | stm32h7xx_hal_nand.c [code]

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device.

file | stm32h7xx_hal_nor.c [code]

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device.

file | stm32h7xx_hal_opamp.c [code]

OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s) peripheral: + OPAMP configuration + OPAMP calibration Thanks to + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32h7xx_hal_opamp_ex.c [code]

Extended OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions.

file | stm32h7xx_hal_pcd.c [code]

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32h7xx_hal_pcd_ex.c [code]

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions.

file | stm32h7xx_hal_pwr.c [code]

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32h7xx_hal_pwr_ex.c [code]

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of PWR extension peripheral: + Peripheral Extended features functions.

file | stm32h7xx_hal_qspi.c [code]

QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + MDMA channel configuration for indirect functional mode + Errors management and abort functionality.

file | stm32h7xx_hal_rcc.c [code]

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32h7xx_hal_rcc_ex.c [code]

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions.

file | stm32h7xx_hal_rng.c [code]

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization/de-initialization functions + Peripheral Control functions + Peripheral State functions.

file | stm32h7xx_hal_rtc.c [code]

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management.

file | stm32h7xx_hal_rtc_ex.c [code]

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions.

file | stm32h7xx_hal_sai.c [code]

SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32h7xx_hal_sai_ex.c [code]

SAI Extended HAL module driver. This file provides firmware functions to manage the following functionality of the SAI Peripheral Controller: + Modify PDM microphone delays.

file | stm32h7xx_hal_sd.c [code]

SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32h7xx_hal_sd_ex.c [code]

SD card Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Extended features functions.

file | stm32h7xx_hal_sdram.c [code]

SDRAM HAL module driver. This file provides a generic firmware to drive SDRAM memories mounted as external device.

file | stm32h7xx_hal_smartcard.c [code]

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32h7xx_hal_smartcard_ex.c [code]

SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32h7xx_hal_smbus.c [code]

SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32h7xx_hal_spdifrx.c [code]

This file provides firmware functions to manage the following functionalities of the SPDIFRX audio interface: + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management.

file | stm32h7xx_hal_spi.c [code]

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32h7xx_hal_spi_ex.c [code]

Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions + Peripheral Control functions.

file | stm32h7xx_hal_sram.c [code]

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device.

file | stm32h7xx_hal_swpmi.c [code]

SWPMI HAL module driver. This file provides firmware functions to manage the following functionalities of the Single Wire Protocol Master Interface (SWPMI). + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management.

file | stm32h7xx_hal_tim.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration.

file | stm32h7xx_hal_tim_ex.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal bread and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration.

file | stm32h7xx_hal_uart.c [code]

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

file | stm32h7xx_hal_uart_ex.c [code]

Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32h7xx_hal_usart.c [code]

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32h7xx_hal_wwdg.c [code]

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration function + IO operation functions.

Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: C:/Workspace/STM32_H7/STM32H7xx_HAL_Driver/Trunk/Drivers/STM32H7xx_HAL_Driver/ Directory Reference

  • Drivers
  • STM32H7xx_HAL_Driver
STM32H7xx_HAL_Driver Directory Reference

Directories

directory | Inc
directory | Src
Generated on Fri Apr 28 2017 15:42:56 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Directories

Directories
This directory hierarchy is sorted roughly, but not completely, alphabetically:
  • Drivers
    • STM32H7xx_HAL_Driver
      • Inc
      • Src
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: File List

  • File List
  • Globals
File List
Here is a list of all files with brief descriptions:
stm32h7xx_hal.c [code] | HAL module driver. This is the common part of the HAL initialization
stm32h7xx_hal.h [code] | This file contains all the functions prototypes for the HAL module driver
stm32h7xx_hal_adc.c [code] | This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and deinitialization functions ++ Initialization and Configuration of ADC + Operation functions ++ Start, stop, get result of regular conversions of regular using 3 possible modes: polling, interruption or DMA. + Control functions ++ Channels configuration on regular group ++ Analog Watchdog configuration + State functions ++ ADC state machine management ++ Interrupts and flags management Other functions (extended functions) are available in file "stm32h7xx_hal_adc_ex.c"
stm32h7xx_hal_adc.h [code] | Header file of ADC HAL module
stm32h7xx_hal_adc_ex.c [code] | This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Operation functions ++ Start, stop, get result of conversions of injected group, using 2 possible modes: polling, interruption. ++ Calibration +++ ADC automatic self-calibration +++ Calibration factors get or set ++ Multimode feature when available + Control functions ++ Channels configuration on injected group + State functions ++ Injected group queues management Other functions (generic functions) are available in file "stm32h7xx_hal_adc.c"
stm32h7xx_hal_adc_ex.h [code] | Header file of ADC HAL extended module
stm32h7xx_hal_cec.c [code] | CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization function + IO operation function + Peripheral Control function
stm32h7xx_hal_cec.h [code] | Header file of CEC HAL module
stm32h7xx_hal_comp.c [code] | COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode + Start/Stop operation functions in interrupt mode + Peripheral control functions + Peripheral state functions
stm32h7xx_hal_comp.h [code] | Header file of COMP HAL module
stm32h7xx_hal_conf.h [code]
stm32h7xx_hal_cortex.c [code] | CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions
stm32h7xx_hal_cortex.h [code] | Header file of CORTEX HAL module
stm32h7xx_hal_crc.c [code] | CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions
stm32h7xx_hal_crc.h [code] | Header file of CRC HAL module
stm32h7xx_hal_crc_ex.c [code] | Extended CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the CRC peripheral: + Initialization/de-initialization functions
stm32h7xx_hal_crc_ex.h [code] | Header file of CRC HAL extension module
stm32h7xx_hal_cryp.c [code] | CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization and de-initialization functions + AES processing functions + DES processing functions + TDES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions
stm32h7xx_hal_cryp.h [code] | Header file of CRYP HAL module
stm32h7xx_hal_cryp_ex.c [code] | Extended CRYP HAL module driver This file provides firmware functions to manage the following functionalities of CRYP extension peripheral: + Extended AES processing functions
stm32h7xx_hal_cryp_ex.h [code] | Header file of CRYP HAL Extension module
stm32h7xx_hal_dac.c [code] | DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32h7xx_hal_dac.h [code] | Header file of DAC HAL module
stm32h7xx_hal_dac_ex.c [code] | Extended DAC HAL module driver. This file provides firmware functions to manage the extended functionalities of DAC peripheral
stm32h7xx_hal_dac_ex.h [code] | Header file of DAC HAL Extended module
stm32h7xx_hal_dcmi.c [code] | DCMI HAL module driver This file provides firmware functions to manage the following functionalities of the Digital Camera Interface (DCMI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32h7xx_hal_dcmi.h [code] | Header file of DCMI HAL module
stm32h7xx_hal_dfsdm.c [code] | This file provides firmware functions to manage the following functionalities of the Digital Filter for Sigma-Delta Modulators (DFSDM) peripherals: + Initialization and configuration of channels and filters + Regular channels configuration + Injected channels configuration + Regular/Injected Channels DMA Configuration + Interrupts and flags management + Analog watchdog feature + Short-circuit detector feature + Extremes detector feature + Clock absence detector feature + Break generation on analog watchdog or short-circuit event
stm32h7xx_hal_dfsdm.h [code] | Header file of DFSDM HAL module
stm32h7xx_hal_dma.c [code] | DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions
stm32h7xx_hal_dma.h [code] | Header file of DMA HAL module
stm32h7xx_hal_dma2d.c [code] | DMA2D HAL module driver. This file provides firmware functions to manage the following functionalities of the DMA2D peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32h7xx_hal_dma2d.h [code] | Header file of DMA2D HAL module
stm32h7xx_hal_dma_ex.c [code] | DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions
stm32h7xx_hal_dma_ex.h [code] | Header file of DMA HAL extension module
stm32h7xx_hal_eth.c [code] | ETH HAL module driver. This file provides firmware functions to manage the following functionalities of the Ethernet (ETH) peripheral: + Initialization and deinitialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32h7xx_hal_eth.h [code] | Header file of ETH HAL module
stm32h7xx_hal_eth_ex.c [code] | ETH HAL Extended module driver
stm32h7xx_hal_eth_ex.h [code] | Header file of ETH HAL Extended module
stm32h7xx_hal_fdcan.c [code] | FDCAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Flexible DataRate Controller Area Network (FDCAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Configuration and Control functions + Peripheral State and Error functions
stm32h7xx_hal_fdcan.h [code] | Header file of FDCAN HAL module
stm32h7xx_hal_flash.c [code] | FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions
stm32h7xx_hal_flash.h [code] | Header file of FLASH HAL module
stm32h7xx_hal_flash_ex.c [code] | Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extension peripheral: + Extended programming operations functions
stm32h7xx_hal_flash_ex.h [code] | Header file of FLASH HAL module
stm32h7xx_hal_gpio.c [code] | GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions
stm32h7xx_hal_gpio.h [code] | Header file of GPIO HAL module
stm32h7xx_hal_gpio_ex.h [code] | Header file of GPIO HAL Extension module
stm32h7xx_hal_hash.c [code] | HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral: + Initialization and de-initialization methods + HASH or HMAC processing in polling mode + HASH or HMAC processing in interrupt mode + HASH or HMAC processing in DMA mode + Peripheral State methods + HASH or HMAC processing suspension/resumption
stm32h7xx_hal_hash.h [code] | Header file of HASH HAL module
stm32h7xx_hal_hash_ex.c [code] | Extended HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral for SHA-224 and SHA-256 alogrithms: + HASH or HMAC processing in polling mode + HASH or HMAC processing in interrupt mode + HASH or HMAC processing in DMA mode Additionally, this file provides functions to manage HMAC multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224 and SHA-256
stm32h7xx_hal_hash_ex.h [code] | Header file of HASH HAL module
stm32h7xx_hal_hcd.c [code] | HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32h7xx_hal_hcd.h [code] | Header file of HCD HAL module
stm32h7xx_hal_hrtim.c [code] | HRTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the High Resolution Timer (HRTIM) peripheral: + HRTIM Initialization + Timer Time Base Unit Configuration + Simple Time Base Start/Stop + Simple Time Base Start/Stop Interrupt + Simple Time Base Start/Stop DMA Request + Simple Output Compare/PWM Channel Configuration + Simple Output Compare/PWM Channel Start/Stop Interrupt + Simple Output Compare/PWM Channel Start/Stop DMA Request + Simple Input Capture Channel Configuration + Simple Input Capture Channel Start/Stop Interrupt + Simple Input Capture Channel Start/Stop DMA Request + Simple One Pulse Channel Configuration + Simple One Pulse Channel Start/Stop Interrupt + HRTIM External Synchronization Configuration + HRTIM Burst Mode Controller Configuration + HRTIM Burst Mode Controller Enabling + HRTIM External Events Conditioning Configuration + HRTIM Faults Conditioning Configuration + HRTIM Faults Enabling + HRTIM ADC trigger Configuration + Waveform Timer Configuration + Waveform Event Filtering Configuration + Waveform Dead Time Insertion Configuration + Waveform Chopper Mode Configuration + Waveform Compare Unit Configuration + Waveform Capture Unit Configuration + Waveform Output Configuration + Waveform Counter Start/Stop + Waveform Counter Start/Stop Interrupt + Waveform Counter Start/Stop DMA Request + Waveform Output Enabling + Waveform Output Level Set/Get + Waveform Output State Get + Waveform Burst DMA Operation Configuration + Waveform Burst DMA Operation Start + Waveform Timer Counter Software Reset + Waveform Capture Software Trigger + Waveform Burst Mode Controller Software Trigger + Waveform Timer Pre-loadable Registers Update Enabling + Waveform Timer Pre-loadable Registers Software Update + Waveform Timer Delayed Protection Status Get + Waveform Timer Burst Status Get + Waveform Timer Push-Pull Status Get + Peripheral State Get
stm32h7xx_hal_hrtim.h [code] | Header file of HRTIM HAL module
stm32h7xx_hal_hsem.c [code] | HSEM HAL module driver. This file provides firmware functions to manage the following functionalities of the semaphore peripheral: + Semaphore Take function (2-Step Procedure) , non blocking + Semaphore FastTake function (1-Step Procedure) , non blocking + Semaphore Status check + Semaphore Clear Key Set and Get + Release and release all functions + Semaphore notification enabling and disabling and callnack functions + IRQ handler management
stm32h7xx_hal_hsem.h [code] | Header file of HSEM HAL module
stm32h7xx_hal_i2c.c [code] | I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32h7xx_hal_i2c.h [code] | Header file of I2C HAL module
stm32h7xx_hal_i2c_ex.c [code] | I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions
stm32h7xx_hal_i2c_ex.h [code] | Header file of I2C HAL Extension module
stm32h7xx_hal_i2s.c [code] | I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32h7xx_hal_i2s.h [code] | Header file of I2S HAL module
stm32h7xx_hal_i2s_ex.c [code] | I2S HAL module driver. This file provides firmware functions to manage the following functionalities of I2S extension peripheral: + IO operation functions + Peripheral Control functions
stm32h7xx_hal_i2s_ex.h [code] | Header file of I2S HAL module
stm32h7xx_hal_irda.c [code] | IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions
stm32h7xx_hal_irda.h [code] | Header file of IRDA HAL module
stm32h7xx_hal_irda_ex.h [code] | Header file of IRDA HAL Extended module
stm32h7xx_hal_iwdg.c [code] | IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions
stm32h7xx_hal_iwdg.h [code] | Header file of IWDG HAL module
stm32h7xx_hal_jpeg.c [code] | JPEG HAL module driver. This file provides firmware functions to manage the following functionalities of the JPEG encoder/decoder peripheral: + Initialization and de-initialization functions + JPEG processing functions encoding and decoding + JPEG decoding Getting Info and encoding configuration setting + JPEG enable/disable header parsing functions (for decoding) + JPEG Input/Output Buffer configuration. + JPEG callback functions + JPEG Abort/Pause/Resume functions + JPEG custom quantization tables setting functions + IRQ handler management + Peripheral State and Error functions
stm32h7xx_hal_jpeg.h [code] | Header file of JPEG HAL module
stm32h7xx_hal_lptim.c [code] | LPTIM HAL module driver
stm32h7xx_hal_lptim.h [code] | Header file of LPTIM HAL module
stm32h7xx_hal_ltdc.c [code] | LTDC HAL module driver. This file provides firmware functions to manage the following functionalities of the LTDC peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32h7xx_hal_ltdc.h [code] | Header file of LTDC HAL module
stm32h7xx_hal_mdios.c [code] | MDIOS HAL module driver. This file provides firmware functions to manage the following functionalities of the MDIOS Peripheral. + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions
stm32h7xx_hal_mdios.h [code] | Header file of MDIOS HAL module
stm32h7xx_hal_mdma.c [code] | This file provides firmware functions to manage the following functionalities of the Master Direct Memory Access (MDMA) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral State and errors functions
stm32h7xx_hal_mdma.h [code] | Header file of DMA HAL module
stm32h7xx_hal_mmc.c [code] | MMC card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (MMC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + MMC card Control functions
stm32h7xx_hal_mmc.h [code] | Header file of MMC HAL module
stm32h7xx_hal_mmc_ex.c [code] | MMC card Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (MMC) peripheral: + Extended features functions
stm32h7xx_hal_mmc_ex.h [code] | Header file of MMC HAL extended module
stm32h7xx_hal_nand.c [code] | NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device
stm32h7xx_hal_nand.h [code] | Header file of NAND HAL module
stm32h7xx_hal_nor.c [code] | NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device
stm32h7xx_hal_nor.h [code] | Header file of NOR HAL module
stm32h7xx_hal_opamp.c [code] | OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s) peripheral: + OPAMP configuration + OPAMP calibration Thanks to + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32h7xx_hal_opamp.h [code] | Header file of OPAMP HAL module
stm32h7xx_hal_opamp_ex.c [code] | Extended OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions
stm32h7xx_hal_opamp_ex.h [code] | Header file of OPAMP HAL Extended module
stm32h7xx_hal_pcd.c [code] | PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32h7xx_hal_pcd.h [code] | Header file of PCD HAL module
stm32h7xx_hal_pcd_ex.c [code] | PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions
stm32h7xx_hal_pcd_ex.h [code] | Header file of PCD HAL module
stm32h7xx_hal_pwr.c [code] | PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization and de-initialization functions + Peripheral Control functions
stm32h7xx_hal_pwr.h [code] | Header file of PWR HAL module
stm32h7xx_hal_pwr_ex.c [code] | Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of PWR extension peripheral: + Peripheral Extended features functions
stm32h7xx_hal_pwr_ex.h [code] | Header file of PWR HAL Extension module
stm32h7xx_hal_qspi.c [code] | QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + MDMA channel configuration for indirect functional mode + Errors management and abort functionality
stm32h7xx_hal_qspi.h [code] | Header file of QSPI HAL module
stm32h7xx_hal_rcc.c [code] | RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions
stm32h7xx_hal_rcc.h [code] | Header file of RCC HAL module
stm32h7xx_hal_rcc_ex.c [code] | Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions
stm32h7xx_hal_rcc_ex.h [code] | Header file of RCC HAL Extension module
stm32h7xx_hal_rng.c [code] | RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization/de-initialization functions + Peripheral Control functions + Peripheral State functions
stm32h7xx_hal_rng.h [code] | Header file of RNG HAL module
stm32h7xx_hal_rtc.c [code] | RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management
stm32h7xx_hal_rtc.h [code] | Header file of RTC HAL module
stm32h7xx_hal_rtc_ex.c [code] | Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions
stm32h7xx_hal_rtc_ex.h [code] | Header file of RTC HAL Extension module
stm32h7xx_hal_sai.c [code] | SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions
stm32h7xx_hal_sai.h [code] | Header file of SAI HAL module
stm32h7xx_hal_sai_ex.c [code] | SAI Extended HAL module driver. This file provides firmware functions to manage the following functionality of the SAI Peripheral Controller: + Modify PDM microphone delays
stm32h7xx_hal_sai_ex.h [code] | Header file of SAI HAL extended module
stm32h7xx_hal_sd.c [code] | SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32h7xx_hal_sd.h [code] | Header file of SD HAL module
stm32h7xx_hal_sd_ex.c [code] | SD card Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Extended features functions
stm32h7xx_hal_sd_ex.h [code] | Header file of SD HAL extended module
stm32h7xx_hal_sdram.c [code] | SDRAM HAL module driver. This file provides a generic firmware to drive SDRAM memories mounted as external device
stm32h7xx_hal_sdram.h [code] | Header file of SDRAM HAL module
stm32h7xx_hal_smartcard.c [code] | SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32h7xx_hal_smartcard.h [code] | Header file of SMARTCARD HAL module
stm32h7xx_hal_smartcard_ex.c [code] | SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions
stm32h7xx_hal_smartcard_ex.h [code] | Header file of SMARTCARD HAL Extended module
stm32h7xx_hal_smbus.c [code] | SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32h7xx_hal_smbus.h [code] | Header file of SMBUS HAL module
stm32h7xx_hal_spdifrx.c [code] | This file provides firmware functions to manage the following functionalities of the SPDIFRX audio interface: + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management
stm32h7xx_hal_spdifrx.h [code] | Header file of SPDIFRX HAL module
stm32h7xx_hal_spi.c [code] | SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32h7xx_hal_spi.h [code] | Header file of SPI HAL module
stm32h7xx_hal_spi_ex.c [code] | Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions + Peripheral Control functions
stm32h7xx_hal_spi_ex.h [code] | Header file of SPI HAL Extended module
stm32h7xx_hal_sram.c [code] | SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device
stm32h7xx_hal_sram.h [code] | Header file of SRAM HAL module
stm32h7xx_hal_swpmi.c [code] | SWPMI HAL module driver. This file provides firmware functions to manage the following functionalities of the Single Wire Protocol Master Interface (SWPMI). + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management
stm32h7xx_hal_swpmi.h [code] | Header file of SWPMI HAL module
stm32h7xx_hal_tim.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration
stm32h7xx_hal_tim.h [code] | Header file of TIM HAL module
stm32h7xx_hal_tim_ex.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal bread and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration
stm32h7xx_hal_tim_ex.h [code] | Header file of TIM HAL Extended module
stm32h7xx_hal_uart.c [code] | UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions
stm32h7xx_hal_uart.h [code] | Header file of UART HAL module
stm32h7xx_hal_uart_ex.c [code] | Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions
stm32h7xx_hal_uart_ex.h [code] | Header file of UART HAL Extended module
stm32h7xx_hal_usart.c [code] | USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32h7xx_hal_usart.h [code] | Header file of USART HAL module
stm32h7xx_hal_usart_ex.h [code] | Header file of USART HAL Extended module
stm32h7xx_hal_wwdg.c [code] | WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration function + IO operation functions
stm32h7xx_hal_wwdg.h [code] | Header file of WWDG HAL module
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STM32H753xx HAL User Manual: ADC

Modules
ADC
STM32H7xx_HAL_Driver

ADC HAL module driver. More...

Modules

ADC Private Constants
ADC Exported Functions
ADC Private Functions
ADC Exported Types
ADC Exported Constants
ADC Private Macros
ADC Exported Macros

Detailed Description

ADC HAL module driver.

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STM32H753xx HAL User Manual: ADC Exported Constants

Modules
ADC Exported Constants
ADC

Modules

ADC Error Code
ADC clock source and clock prescaler
ADC Resolution
ADC sequencer scan mode
ADC group regular trigger source
ADC group regular trigger edge (when external trigger is selected)
ADC sequencer end of unitary conversion or sequence conversions
ADC overrun
ADC group regular sequencer rank
ADC Channels
ADC Conversion Data Management
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STM32H753xx HAL User Manual: ADC Exported Functions

Modules
ADC Exported Functions
ADC

Modules

Initialization and deinitialization functions

ADC Initialization and Configuration functions.

Input and Output operation functions

ADC IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

ADC Peripheral State functions.

ADC Private Functions
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STM32H753xx HAL User Manual: ADC Exported Types

Data Structures | Modules
ADC Exported Types
ADC

Data Structures

struct | ADC_OversamplingTypeDef
ADC Regular Conversion Oversampling structure definition. More...
struct | ADC_InitTypeDef
Structure definition of ADC instance and ADC group regular. More...
struct | ADC_AnalogWDGConfTypeDef
Structure definition of ADC analog watchdog. More...

Modules

ADC States
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STM32H753xx HAL User Manual: ADCEx

Modules
ADCEx
STM32H7xx_HAL_Driver

ADC Extended HAL module driver. More...

Modules

ADC Extended Private Constants
ADC Extended Exported Functions
ADC Extended Exported Types
ADC Extended Exported Constants
ADC Extended Private Macros

Detailed Description

ADC Extended HAL module driver.

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STM32H753xx HAL User Manual: ADC Extended Exported Functions

Modules
ADC Extended Exported Functions
ADCEx

Modules

Extended Input and Output operation functions

Extended IO operation functions.

ADC Extended Peripheral Control functions

ADC Extended Peripheral Control functions.

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STM32H753xx HAL User Manual: ADC Extended Exported Types

Data Structures
ADC Extended Exported Types
ADCEx

Data Structures

struct | ADC_InjectionConfigTypeDef
ADC group injected contexts queue configuration. More...
struct | ADC_HandleTypeDef
ADC handle Structure definition. More...
struct | ADC_InjOversamplingTypeDef
ADC Injected Conversion Oversampling structure definition. More...
struct | ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group. More...
struct | ADC_InjectionConfTypeDef
Structure definition of ADC group injected and ADC channel affected to ADC group injected. More...
struct | ADC_MultiModeTypeDef
Structure definition of ADC MultiMode. More...
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STM32H753xx HAL User Manual: CEC

Modules
CEC
STM32H7xx_HAL_Driver

HAL CEC module driver. More...

Modules

CEC Private Constants
CEC Private Functions
CEC Exported Functions
CEC Exported Types
CEC Exported Constants
CEC Exported Macros
CEC Private Types
CEC Private Variables
CEC Private Macros

Detailed Description

HAL CEC module driver.

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STM32H753xx HAL User Manual: CEC Exported Constants

Modules
CEC Exported Constants
CEC

Modules

CEC Error Code
CEC Signal Free Time setting parameter
CEC Receiver Tolerance
CEC Reception Stop on Error
CEC Error Bit Generation if Bit Rise Error reported
CEC Error Bit Generation if Long Bit Period Error reported
CEC Error Bit Generation on Broadcast message
CEC Signal Free Time start option
CEC Listening mode option
CEC Device Own Address position in CEC CFGR register
CEC Initiator logical address position in message header
CEC Own Address
CEC Interrupts definition
CEC Flags definition
CEC all RX or TX errors flags
CEC all RX errors interrupts enabling flag
CEC all TX errors interrupts enabling flag
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STM32H753xx HAL User Manual: CEC Exported Functions

Modules
CEC Exported Functions
CEC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

CEC Transmit/Receive functions.

Peripheral Control function

CEC control functions.

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STM32H753xx HAL User Manual: COMP

Modules
COMP
STM32H7xx_HAL_Driver

COMP HAL module driver. More...

Modules

COMP Exported Functions
COMP Exported Types
COMP Exported Constants
COMP Exported Macros
COMP Private Constants
COMP Private Macros

Detailed Description

COMP HAL module driver.

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STM32H753xx HAL User Manual: COMP Exported Constants

Modules
COMP Exported Constants
COMP

Modules

COMP Window Mode
COMP power mode
COMP input plus (non-inverting input)
COMP input minus (inverting input)
COMP hysteresis
COMP Output Polarity
COMP Blanking Source
COMP Output Level
COMP output to EXTI
COMP Flag
COMP Interruption Clear Flags
COMP Interrupts Definitions
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STM32H753xx HAL User Manual: COMP Exported Functions

Modules
COMP Exported Functions
COMP

Modules

Initialization/de-initialization functions

Initialization and de-initialization functions.

Start-Stop operation functions

Start-Stop operation functions.

Peripheral Control functions

Management functions.

Peripheral State functions

Peripheral State functions.

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STM32H753xx HAL User Manual: COMP Private Macros

Modules
COMP Private Macros
COMP

Modules

COMP Private macros to get EXTI line associated with Comparators
COMP private macros to check input parameters
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STM32H753xx HAL User Manual: CORTEX

Modules
CORTEX
STM32H7xx_HAL_Driver

CORTEX HAL module driver. More...

Modules

CORTEX Exported Functions
Cortex Exported Types
CORTEX Exported Constants
CORTEX Exported Macros
CORTEX_CPU_Identifier
CORTEX Private Macros
CORTEX Private Functions

CORTEX private functions.

Detailed Description

CORTEX HAL module driver.

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STM32H753xx HAL User Manual: CORTEX Exported Constants

Modules
CORTEX Exported Constants
CORTEX

Modules

CORTEX Preemption Priority Group
CORTEX _SysTick clock source
MPU HFNMI and PRIVILEGED Access control
CORTEX MPU Region Enable
CORTEX MPU Instruction Access
CORTEX MPU Instruction Access Shareable
CORTEX MPU Instruction Access Cacheable
CORTEX MPU Instruction Access Bufferable
MPU TEX Levels
CORTEX MPU Region Size
CORTEX MPU Region Permission Attributes
CORTEX MPU Region Number
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STM32H753xx HAL User Manual: CORTEX Exported Functions

Modules
CORTEX Exported Functions
CORTEX

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

Cortex control functions.

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STM32H753xx HAL User Manual: Cortex Exported Types

Modules
Cortex Exported Types
CORTEX

Modules

MPU Region Initialization Structure Definition

MPU Region initialization structure.

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STM32H753xx HAL User Manual: MPU Region Initialization Structure Definition

Data Structures
MPU Region Initialization Structure Definition
Cortex Exported Types

MPU Region initialization structure. More...

Data Structures

struct MPU_Region_InitTypeDef

Detailed Description

MPU Region initialization structure.

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STM32H753xx HAL User Manual: CRC

Modules
CRC
STM32H7xx_HAL_Driver

CRC HAL module driver. More...

Modules

CRC Exported Functions
CRC Exported Types
CRC exported constants
CRC exported macros
CRC Private Types
CRC Private Defines
CRC Private Variables
CRC Private Constants
CRC Private Macros
CRC Private Functions Prototypes
CRC Private Functions

Detailed Description

CRC HAL module driver.

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STM32H753xx HAL User Manual: CRC exported constants

Modules
CRC exported constants
CRC

Modules

Default CRC generating polynomial
Default CRC computation initialization value
Indicates whether or not default polynomial is used
Indicates whether or not default init value is used
Polynomial sizes to configure the IP
CRC polynomial possible sizes actual definitions
CRC input buffer format
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STM32H753xx HAL User Manual: CRC Exported Types

Modules
CRC Exported Types
CRC

Modules

CRC State Structure definition
CRC Init Structure definition
CRC Handle Structure definition
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STM32H753xx HAL User Manual: CRC Init Structure definition

Data Structures
CRC Init Structure definition
CRC Exported Types

Data Structures

struct CRC_InitTypeDef
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STM32H753xx HAL User Manual: CRC Handle Structure definition

Data Structures
CRC Handle Structure definition
CRC Exported Types

Data Structures

struct CRC_HandleTypeDef
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STM32H753xx HAL User Manual: CRCEx

Modules
CRCEx
STM32H7xx_HAL_Driver

CRC Extended HAL module driver. More...

Modules

CRC Extended exported constants
CRC Extended exported macros
CRC Extended Exported Functions

Detailed Description

CRC Extended HAL module driver.

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STM32H753xx HAL User Manual: CRC Extended exported constants

Modules
CRC Extended exported constants
CRCEx

Modules

CRC Extended input data inversion modes
CRC Extended output data inversion modes
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STM32H753xx HAL User Manual: CRC Extended Exported Functions

Modules
CRC Extended Exported Functions
CRCEx

Modules

Extended CRC features functions

Extended CRC features functions.

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STM32H753xx HAL User Manual: CRYP

Modules
CRYP
STM32H7xx_HAL_Driver

CRYP HAL module driver. More...

Modules

CRYP Exported Functions
CRYP Exported Types
CRYP Exported Constants
CRYP Exported Macros
CRYP Private Macros
CRYP Private Constants
CRYP Private Defines
CRYP Private Variables
CRYP Private Functions Prototypes
CRYP Private Functions
CRYP_Private_Functions_prototypes

Detailed Description

CRYP HAL module driver.

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STM32H753xx HAL User Manual: CRYP Exported Constants

Modules
CRYP Exported Constants
CRYP

Modules

CRYP Error Definition
CRYP Algorithm Mode
CRYP Key Size
CRYP Data Type
CRYP Interrupt
CRYP Flags
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STM32H753xx HAL User Manual: CRYP Exported Functions

Modules
CRYP Exported Functions
CRYP

Modules

Initialization and de-initialization functions

CRYP Initialization and Configuration functions.

Encrypt Decrypt functions

CRYP processing functions.

CRYP IRQ handler management

CRYP IRQ handler.

CRYP Private Functions
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STM32H753xx HAL User Manual: CRYPEx

Modules
CRYPEx
STM32H7xx_HAL_Driver

CRYP Extension HAL module driver. More...

Modules

CRYPEx Private Types
CRYPEx Private Variables
CRYPEx Private Constants
CRYPEx Private Macros
CRYPEx Private Functions
CRYPEx Exported Functions
CRYPEx_Private_Defines

Detailed Description

CRYP Extension HAL module driver.

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STM32H753xx HAL User Manual: CRYPEx Exported Functions

Modules
CRYPEx Exported Functions
CRYPEx

Modules

Extended AES processing functions

CRYPEx Extended processing functions.

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STM32H753xx HAL User Manual: DAC

Modules
DAC
STM32H7xx_HAL_Driver

DAC driver modules. More...

Modules

DAC Exported Types
DAC Exported Constants
DAC Exported Macros
DAC Private Macros
DAC Private Constants
DAC Exported Functions

Detailed Description

DAC driver modules.

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STM32H753xx HAL User Manual: DAC Exported Constants

Modules
DAC Exported Constants
DAC

Modules

DAC Error Code
DAC trigger selection
DAC output buffer
DAC ConnectOnChipPeripheral
DAC User Trimming
. Mode is Sample and hold (low power or normal)
DAC Channel selection
DAC data alignment
DAC flags definition
DAC IT definition
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STM32H753xx HAL User Manual: DAC Exported Functions

Modules
DAC Exported Functions
DAC Private Constants | DAC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State and Errors functions

Peripheral State and Errors functions.

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STM32H753xx HAL User Manual: DACEx

Modules
DACEx
STM32H7xx_HAL_Driver

DAC Extended HAL module driver. More...

Modules

DACEx Exported Functions
Peripheral Control functions

Extended Peripheral Control functions.

DACEx private functions

Extended private functions.

DACEx Exported Constants

HAL State structures definition.

DACEx Private Macros

Detailed Description

DAC Extended HAL module driver.

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STM32H753xx HAL User Manual: DACEx Exported Constants

Modules
DACEx Exported Constants
DACEx

HAL State structures definition. More...

Modules

DACEx lfsrunmask triangle amplitude

Detailed Description

HAL State structures definition.

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STM32H753xx HAL User Manual: DCMI Exported Constants

Modules
DCMI Exported Constants
DCMI

Modules

DCMI Error Code
DCMI Capture Mode
DCMI Synchronization Mode
DCMI PIXCK Polarity
DCMI VSYNC Polarity
DCMI HSYNC Polarity
DCMI MODE JPEG
DCMI Capture Rate
DCMI Extended Data Mode
DCMI Window Coordinate
DCMI Window Height
DCMI interrupt sources
DCMI Flags
DCMI Byte Select Mode
DCMI Byte Select Start
DCMI Line Select Mode
DCMI Line Select Start
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STM32H753xx HAL User Manual: DCMI Exported Functions

Modules
DCMI Exported Functions
DCMI

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

DCMI Private Functions
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STM32H753xx HAL User Manual: DFSDM

Modules
DFSDM
STM32H7xx_HAL_Driver

DFSDM HAL driver module. More...

Modules

DFSDM Private Define
DFSDM Private Variables
DFSDM Private Functions
DFSDM Exported Functions
DFSDM Exported Types
DFSDM Exported Constants
DFSDM Exported Macros
DFSDM Private Macros

Detailed Description

DFSDM HAL driver module.

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STM32H753xx HAL User Manual: DFSDM Exported Constants

Modules
DFSDM Exported Constants
DFSDM

Modules

DFSDM channel output clock selection
DFSDM channel input multiplexer
DFSDM channel input data packing
DFSDM channel input pins
DFSDM channel serial interface type
DFSDM channel SPI clock selection
DFSDM channel analog watchdog filter order
DFSDM filter conversion trigger
DFSDM filter external trigger
DFSDM filter external trigger edge
DFSDM filter sinc order
DFSDM filter analog watchdog data source
DFSDM filter error code
DFSDM break signals
DFSDM Channel Selection
DFSDM Continuous Mode
DFSDM analog watchdog threshold
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STM32H753xx HAL User Manual: DFSDM Exported Functions

Modules
DFSDM Exported Functions
DFSDM

Modules

Channel initialization and de-initialization functions

Channel initialization and de-initialization functions.

Channel operation functions

Channel operation functions.

Channel state function

Channel state function.

Filter initialization and de-initialization functions

Filter initialization and de-initialization functions.

Filter control functions

Filter control functions.

Filter operation functions

Filter operation functions.

Filter state functions

Filter state functions.

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STM32H753xx HAL User Manual: DMA

Data Structures | Modules
DMA
STM32H7xx_HAL_Driver

DMA HAL module driver. More...

Data Structures

struct DMA_Base_Registers

Modules

DMA Exported Types

DMA Exported Types.

DMA Exported Constants

DMA Exported constants.

DMA Exported Macros
DMA Exported Functions

DMA Exported functions.

DMA Private Constants

DMA private defines and constants.

DMA Private Macros

DMA private macros.

DMA Private Functions

DMA private functions.

Detailed Description

DMA HAL module driver.

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STM32H753xx HAL User Manual: DMA2D

Modules
DMA2D
STM32H7xx_HAL_Driver

DMA2D HAL module driver. More...

Modules

DMA2D Private Constants
DMA2D Exported Functions
DMA2D Private Functions
DMA2D Exported Types
DMA2D Exported Constants
DMA2D Exported Macros
DMA2D Private Macros
DMA2D_Private_Functions_Prototypes

Detailed Description

DMA2D HAL module driver.

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STM32H753xx HAL User Manual: DMA2D Exported Constants

Modules
DMA2D Exported Constants
DMA2D

Modules

DMA2D Error Code
DMA2D Mode
DMA2D Output Color Mode
DMA2D Input Color Mode
DMA2D Alpha Mode
DMA2D ALPHA Inversion
DMA2D Red and Blue Swap
DMA2D Chroma Sub Sampling
DMA2D CLUT Color Mode
DMA2D Interrupts
DMA2D Flags
DMA2D API Aliases
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STM32H753xx HAL User Manual: DMA2D Exported Functions

Modules
DMA2D Exported Functions
DMA2D

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State and Error functions

Peripheral State functions.

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STM32H753xx HAL User Manual: DMA2D Private Constants

Modules
DMA2D Private Constants
DMA2D

Modules

DMA2D Time Out
DMA2D Shifts
DMA2D Maximum Line Watermark
DMA2D Color Value
DMA2D Offset
DMA2D Size
DMA2D CLUT Size
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STM32H753xx HAL User Manual: DMA Exported Constants

Modules
DMA Exported Constants
DMA

DMA Exported constants. More...

Modules

DMA Error Code

DMA Error Code.

DMA Request selection

DMA Request selection.

DMA Data transfer direction

DMA data transfer direction.

DMA Peripheral incremented mode

DMA peripheral incremented mode.

DMA Memory incremented mode

DMA memory incremented mode.

DMA Peripheral data size

DMA peripheral data size.

DMA Memory data size

DMA memory data size.

DMA mode

DMA mode.

DMA Priority level

DMA priority levels.

DMA FIFO direct mode

DMA FIFO direct mode.

DMA FIFO threshold level

DMA FIFO level.

DMA Memory burst

DMA memory burst.

DMA Peripheral burst

DMA peripheral burst.

DMA interrupt enable definitions

DMA interrupts definition.

DMA flag definitions

DMA flag definitions.

BDMA flag definitions

BDMA flag definitions.

Detailed Description

DMA Exported constants.

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STM32H753xx HAL User Manual: DMA Exported Functions

Modules
DMA Exported Functions
DMA

DMA Exported functions. More...

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

I/O operation functions

I/O operation functions.

Peripheral State functions

Peripheral State functions.

Detailed Description

DMA Exported functions.

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STM32H753xx HAL User Manual: DMA Exported Constants

Modules
DMA Exported Constants
DMAEx

DMAEx Exported constants. More...

Modules

DMAEx MUX SyncSignalID selection

DMAEx MUX SyncSignalID selection.

DMAEx MUX SyncPolarity selection

DMAEx MUX SyncPolarity selection.

DMAEx MUX SignalGeneratorID selection

DMAEx MUX SignalGeneratorID selection.

DMAEx MUX RequestGeneneratorPolarity selection

DMAEx MUX RequestGeneneratorPolarity selection.

Detailed Description

DMAEx Exported constants.

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STM32H753xx HAL User Manual: DMAEx Exported Functions

Modules
DMAEx Exported Functions
DMAEx

DMAEx Exported functions. More...

Modules

Extended features functions

Extended features functions.

Detailed Description

DMAEx Exported functions.

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STM32H753xx HAL User Manual: ETH Exported Constants

Modules
ETH Exported Constants
ETH

Modules

ETH DMA Tx Descriptor Bit Definition
ETH DMA Rx Descriptor Bit Definition
ETH frame settings
ETH Error Code
ETH Tx Packet Attributes
ETH Tx Packet Source Addr Control
ETH Tx Packet CRC Pad Control
ETH Tx Packet Checksum Control
ETH Tx Packet VLAN Control
ETH Tx Packet Inner VLAN Control
ETH Rx Checksum Status
ETH Rx IP Header Type
ETH Rx Payload Type
ETH Rx MAC Filter Status
ETH Rx L3 Filter Status
ETH Rx L4 Filter Status
ETH Rx Error Code
ETH DMA Arbitration
ETH Burst Mode
ETH Tx DMA Burst Length
ETH Rx DMA Burst Length
ETH DMA Interrupts
ETH DMA Status Flags
ETH Transmit Mode
ETH Receive Mode
ETH Pause Low Threshold
ETH Watchdog Timeout
ETH Inter Packet Gap
ETH Speed
ETH Duplex Mode
ETH Back Off Limit
ETH Preamble Length
ETH Source Addr Control
ETH Control Packets Filter
ETH VLAN Tag Comparison
ETH MAC addresses
ETH MAC Interrupts
ETH MAC Wake Up Event
ETH MAC Rx Tx Status
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STM32H753xx HAL User Manual: ETH Exported Functions

Modules
ETH Exported Functions
ETH

Modules

Initialization and deinitialization functions

Initialization and Configuration functions.

IO operation functions

ETH Transmit and Receive functions.

Peripheral Control functions

ETH control functions.

Peripheral State and Errors functions

ETH State and Errors functions.

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STM32H753xx HAL User Manual: ETHEx

Modules
ETHEx
STM32H7xx_HAL_Driver

ETH HAL Extended module driver. More...

Modules

ETHEx Private Constants
ETH Extended Exported Functions
ETHEx Exported Types
ETHEx Exported Constants

Detailed Description

ETH HAL Extended module driver.

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STM32H753xx HAL User Manual: ETHEx Exported Constants

Modules
ETHEx Exported Constants
ETHEx

Modules

ETHEx LPI Event
ETHEx L3 Filter
ETHEx L4 Filter
ETHEx L3 Protocol
ETHEx L3 Source Match
ETHEx L3 Destination Match
ETHEx L4 Protocol
ETHEx L4 Source Match
ETHEx L4 Destination Match
ETHEx Rx Inner VLAN Tag Stripping
ETHEx Rx VLAN Tag Stripping
ETHEx VLAN Type Check
ETHEx_VLAN_Tag_Control
ETHEx Tx VLAN Tag
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STM32H753xx HAL User Manual: ETH Extended Exported Functions

Modules
ETH Extended Exported Functions
ETHEx

Modules

Extended features functions

Extended features functions.

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STM32H753xx HAL User Manual: ETHEx Exported Types

Data Structures
ETHEx Exported Types
ETHEx

Data Structures

struct | ETH_RxVLANConfigTypeDef
ETH RX VLAN structure definition. More...
struct | ETH_TxVLANConfigTypeDef
ETH TX VLAN structure definition. More...
struct | ETH_L3FilterConfigTypeDef
ETH L3 filter structure definition. More...
struct | ETH_L4FilterConfigTypeDef
ETH L4 filter structure definition. More...
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STM32H753xx HAL User Manual: FDCAN Exported Constants

Modules
FDCAN Exported Constants
FDCAN

Modules

HAL FDCAN Error Code
FDCAN Frame Format
FDCAN Operating Mode
FDCAN Clock Divider
FDCAN Calibration Field Length
FDCAN Calibration State
FDCAN Calibration Counter
FDCAN Data Field Size
FDCAN Tx FIFO/Queue Mode
FDCAN ID Type
FDCAN Frame Type
FDCAN Data Length Code
FDCAN Error State Indicator
FDCAN Bit Rate Switching
FDCAN format
FDCAN Event FIFO control
FDCAN Filter Type
FDCAN Filter Configuration
FDCAN Tx Location
FDCAN Rx Location
FDCAN Event Type
FDCAN High Priority Message Storage
FDCAN protocol error code
FDCAN communication state
FDCAN FIFO watermark
FDCAN FIFO operation mode
FDCAN non-matching frames
FDCAN interrupt line
FDCAN timestamp
FDCAN timestamp prescaler
FDCAN timeout operation
FDCAN TT reference message payload
FDCAN TT repeat factor
FDCAN TT trigger type
FDCAN TT time mark event internal
FDCAN TT time mark event external
FDCAN Operation Mode
FDCAN TT Operation
FDCAN TT Time Master
FDCAN TT External Clock Synchronization
FDCAN TT Global Time Filtering
FDCAN TT Automatic Clock Calibration
FDCAN TT Event Trigger Polarity
FDCAN TT Basic Cycle Number
FDCAN TT Cycle Start Sync
FDCAN TT Stop Watch Trigger Selection
FDCAN TT Event Trigger Selection
FDCAN TT Stop Watch Source
FDCAN TT Stop Watch Polarity
FDCAN TT Time Mark Source
FDCAN TT Error Level
FDCAN TT Master State
FDCAN TT Synchronization State
Interrupt masks
FDCAN Flags
FDCAN Interrupts
FDCAN TT Flags
FDCAN TT Interrupts
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STM32H753xx HAL User Manual: FDCAN Exported Functions

Modules
FDCAN Exported Functions
FDCAN

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Configuration functions

FDCAN Configuration functions.

Control functions

Control functions.

TT Configuration and control functions

TT Configuration and control functions.

Interrupts management

Interrupts management.

Callback functions

FDCAN Callback functions.

Peripheral State functions

FDCAN Peripheral State functions.

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STM32H753xx HAL User Manual: FDCAN Interrupts

Modules
FDCAN Interrupts
FDCAN Exported Constants

Modules

FDCAN Tx Interrupts
FDCAN Rx Interrupts
FDCAN Counter Interrupts
Clock Calibration Interrupts
FDCAN Tx Event FIFO Interrupts
FDCAN Rx FIFO 0 Interrupts
FDCAN Rx FIFO 1 Interrupts
FDCAN Error Interrupts
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STM32H753xx HAL User Manual: FDCAN TT Interrupts

Modules
FDCAN TT Interrupts
FDCAN Exported Constants

Modules

FDCAN TT Schedule Synchronization Interrupts
FDCAN TT Time Mark Interrupts
FDCAN TT Stop Watch Interrupt
FDCAN TT Global Time Interrupts
FDCAN TT Disturbing Error Interrupts
FDCAN TT Fatal Error Interrupts
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STM32H753xx HAL User Manual: FLASH Exported Constants

Modules
FLASH Exported Constants
FLASH

Modules

FLASH Error Code

FLASH Error Code.

FLASH Type Program
FLASH Flag definition

Flag definition.

FLASH Interrupt definition

FLASH Interrupt definition.

FLASH Program Parallelism
FLASH Keys
FLASH Sectors
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STM32H753xx HAL User Manual: FLASH_Exported_Functions

Modules
FLASH_Exported_Functions
FLASH

Modules

FLASH_Exported_Functions_Group1
FLASH_Exported_Functions_Group2
FLASH_Exported_Functions_Group3
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STM32H753xx HAL User Manual: FLASH Private functions

Modules
FLASH Private functions
FLASH

Modules

Programming operation functions

Programming operation functions.

Peripheral Control functions

management functions

Peripheral State and Errors functions

Peripheral Errors functions.

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STM32H753xx HAL User Manual: FLASH Exported Constants

Modules
FLASH Exported Constants
FLASHEx

Modules

FLASH Type Erase
FLASH Voltage Range
FLASH WRP State
FLASH Option Type
FLASH Option Bytes Read Protection
FLASH Option Bytes WWatchdog
FLASH Option Bytes IWatchdog
FLASH Option Bytes nRST_STOP
FLASH Option Bytes nRST_STDBY
FLASH IWDG Counter Freeze in STOP
FLASH IWDG Counter Freeze in STANDBY
FLASH BOR Reset Level
FLASH Boot Address
FLASH Latency
FLASH Banks
FLASHEx OB PCROP RDP
FLASH Option Bytes Write Protection
FLASHEx OB SECURITY
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STM32H753xx HAL User Manual: FLASHEx_Exported_Functions

Modules
FLASHEx_Exported_Functions
FLASHEx

Modules

FLASHEx_Exported_Functions_Group1
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STM32H753xx HAL User Manual: FLASH Exported Types

Data Structures
FLASH Exported Types
FLASHEx

Data Structures

struct | FLASH_EraseInitTypeDef
FLASH Erase structure definition. More...
struct | FLASH_OBProgramInitTypeDef
FLASH Option Bytes Program structure definition. More...
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STM32H753xx HAL User Manual: FLASHEx Private Macros

Modules
FLASHEx Private Macros
FLASHEx

Modules

FLASHEx Private macros to check input parameters
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STM32H753xx HAL User Manual: GPIO

Modules
GPIO
STM32H7xx_HAL_Driver

GPIO HAL module driver. More...

Modules

GPIO Exported Functions
GPIO Exported Types
GPIO Exported Constants
GPIO Exported Macros
GPIO Private Constants
GPIO Private Macros
GPIO Private Functions

Detailed Description

GPIO HAL module driver.

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STM32H753xx HAL User Manual: GPIO Exported Constants

Modules
GPIO Exported Constants
GPIO

Modules

GPIO pins define
GPIO mode define

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ.

GPIO speed define

GPIO Output Maximum frequency.

GPIO pull define

GPIO Pull-Up or Pull-Down Activation.

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STM32H753xx HAL User Manual: GPIO Exported Functions

Modules
GPIO Exported Functions
GPIO

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

GPIO Read, Write, Toggle, Lock and EXTI management functions.

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STM32H753xx HAL User Manual: GPIOEx

Modules
GPIOEx
STM32H7xx_HAL_Driver

Modules

GPIO Exported Constants
GPIO Exported Macros
GPIO Exported Functions
GPIO Private Constants
GPIO Private Macros
GPIO Private Functions
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STM32H753xx HAL User Manual: GPIO Exported Constants

Modules
GPIO Exported Constants
GPIOEx

Modules

GPIO Alternate Function Selection
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STM32H753xx HAL User Manual: HAL Exported Functions

Modules
HAL Exported Functions
HAL

Modules

Initialization and de-initialization Functions

Initialization and de-initialization functions.

HAL Control functions

HAL Control functions.

Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH

Modules
HASH
STM32H7xx_HAL_Driver

HASH HAL module driver. More...

Modules

HASH Private Constants
HASH Private Functions
HASH Exported Functions
HASH Exported Types
HASH Exported Constants
HASH Exported Macros
HASH Private Macros

Detailed Description

HASH HAL module driver.

Generated on Fri Apr 28 2017 15:42:46 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HASH Exported Constants

Modules
HASH Exported Constants
HASH

Modules

HASH algorithm selection
HASH algorithm mode
HASH input data type
HMAC key length type
HASH flags definitions
HASH interrupts definitions
HASH API alias
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STM32H753xx HAL User Manual: HASH Exported Functions

Modules
HASH Exported Functions
HASH

Modules

Initialization and de-initialization functions

HASH Initialization, configuration and call-back functions.

HASH processing functions in polling mode

HASH processing functions using polling mode.

HASH processing functions in interrupt mode

HASH processing functions using interrupt mode.

HASH processing functions in DMA mode

HASH processing functions using DMA mode.

HMAC processing functions in polling mode

HMAC processing functions using polling mode.

HMAC processing functions in interrupt mode

HMAC processing functions using interrupt mode.

HMAC processing functions in DMA mode

HMAC processing functions using DMA modes.

Peripheral states functions

Peripheral State functions.

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STM32H753xx HAL User Manual: HASH Private Constants

Modules
HASH Private Constants
HASH

Modules

HASH Digest Calculation Status
HASH Number of Context Swap Registers
HASH TimeOut Value
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STM32H753xx HAL User Manual: HASHEx

Modules
HASHEx
STM32H7xx_HAL_Driver

HASH HAL extended module driver. More...

Modules

HASH Extended Exported Functions

Detailed Description

HASH HAL extended module driver.

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STM32H753xx HAL User Manual: HASH Extended Exported Functions

Modules
HASH Extended Exported Functions
HASHEx

Modules

HASH extended processing functions in polling mode

HASH extended processing functions using polling mode.

HASH extended processing functions in interrupt mode

HASH extended processing functions using interrupt mode.

HASH extended processing functions in DMA mode

HASH extended processing functions using DMA mode.

HMAC extended processing functions in polling mode

HMAC extended processing functions using polling mode.

HMAC extended processing functions in interrupt mode

HMAC extended processing functions using interruption mode.

HMAC extended processing functions in DMA mode

HMAC extended processing functions using DMA mode.

Multi-buffer HMAC extended processing functions in DMA mode

HMAC extended processing functions in multi-buffer DMA mode.

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STM32H753xx HAL User Manual: HCD

Modules
HCD
STM32H7xx_HAL_Driver

HCD HAL module driver. More...

Modules

HCD Exported Types
HCD Exported Constants
HCD Exported Macros

macros to handle interrupts and specific clock configurations

HCD Exported Functions
HCD Private Macros
HCD Private Functions Prototypes
HCD Private Functions

Detailed Description

HCD HAL module driver.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: HCD Exported Constants

Modules
HCD Exported Constants
HCD

Modules

HCD Speed
HCD PHY Module
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STM32H753xx HAL User Manual: HCD Exported Functions

Modules
HCD Exported Functions
HCD

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

IO operation functions

HCD IO operation functions.

Peripheral Control functions

Peripheral management functions.

Peripheral State functions

Peripheral State functions.

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STM32H753xx HAL User Manual: HCD Exported Types

Modules
HCD Exported Types
HCD

Modules

HCD State Structure definition
HCD Handle Structure definition
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STM32H753xx HAL User Manual: HCD Handle Structure definition

Data Structures
HCD Handle Structure definition
HCD Exported Types

Data Structures

struct HCD_HandleTypeDef
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STM32H753xx HAL User Manual: HCD Private Macros

Modules
HCD Private Macros
HCD

Modules

HCD Instance definition
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STM32H753xx HAL User Manual: HRTIM

Modules
HRTIM
STM32H7xx_HAL_Driver

HRTIM HAL module driver. More...

Modules

HRTIM Private Define
HRTIM Private Variables
HRTIM Private Functions
HRTIM Exported Functions
HRTIM Exported Types
HRTIM Exported Constants
HRTIM Exported Macros
HRTIM Private Macros

Detailed Description

HRTIM HAL module driver.

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STM32H753xx HAL User Manual: HRTIM Exported Constants

Modules
HRTIM Exported Constants
HRTIM

Modules

HRTIM Max Timer
HRTIM Timer Index

Constants defining the timer indexes.

HRTIM Timer identifier

Constants defining timer identifiers.

HRTIM Compare Unit

Constants defining compare unit identifiers.

HRTIM Capture Unit

Constants defining capture unit identifiers.

HRTIM Timer Output

Constants defining timer output identifiers.

HRTIM ADC Trigger

Constants defining ADC triggers identifiers.

HRTIM External Event Channels

Constants defining external event channel identifiers.

HRTIM Fault Channel

Constants defining fault channel identifiers.

HRTIM Prescaler Ratio

Constants defining timer high-resolution clock prescaler ratio.

HRTIM Mode

Constants defining timer counter operating mode.

HRTIM Half Mode Enable

Constants defining half mode enabling status.

HRTIM Start On Sync Input Event

Constants defining the timer behavior following the synchronization event.

HRTIM Reset On Sync Input Event

Constants defining the timer behavior following the synchronization event.

HRTIM DAC Synchronization

Constants defining on which output the DAC synchronization event is sent.

HRTIM Register Preload Enable

Constants defining whether a write access into a preloadable register is done into the active or the preload register.

HRTIM Update Gating

Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3.

HRTIM Timer Burst Mode

Constants defining how the timer behaves during a burst mode operation.

HRTIM Timer Repetition Update

Constants defining whether registers are updated when the timer repetition period is completed (either due to roll-over or reset events)

HRTIM Timer Push Pull Mode

Constants defining whether or not the puhs-pull mode is enabled for a timer.

HRTIM Timer Fault Enabling

Constants defining whether a faut channel is enabled for a timer.

HRTIM Timer Fault Lock

Constants defining whether or not fault enabling bits are write protected for a timer.

HRTIM Timer Deadtime Insertion

Constants defining whether or not fault the dead time insertion feature is enabled for a timer.

HRTIM Timer Delayed Protection Mode

Constants defining all possible delayed protection modes for a timer.

HRTIM Timer Update Trigger

Constants defining whether the registers update is done synchronously with any other timer or master update.

HRTIM Timer Reset Trigger

Constants defining the events that can be selected to trigger the reset of the timer counter.

HRTIM Timer Reset Update

Constants defining whether the register are updated upon Timerx counter reset or roll-over to 0 after reaching the period value in continuous mode.

HRTIM Compare Unit Auto Delayed Mode

Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare), or in auto-delayed mode.

HRTIM Simple OC Mode

Constants defining the behavior of the output signal when the timer operates in basic output compare mode.

HRTIM Output Polarity

Constants defining the polarity of a timer output.

HRTIM Output Set Source

Constants defining the events that can be selected to configure the set crossbar of a timer output.

HRTIM Output Reset Source

Constants defining the events that can be selected to configure the set crossbar of a timer output.

HRTIM Output Idle Mode

Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered.

HRTIM Output IDLE Level

Constants defining the output level when output is in IDLE state.

HRTIM Output FAULT Level

Constants defining the output level when output is in FAULT state.

HRTIM Output Chopper Mode Enable

Constants defining whether or not chopper mode is enabled for a timer output.

HRTIM Output Burst Mode Entry Delayed

Constants defining the idle mode entry is delayed by forcing a deadtime insertion before switching the outputs to their idle state.

HRTIM Capture Unit Trigger

Constants defining the events that can be selected to trigger the capture of the timing unit counter.

HRTIM Timer External Event Filter

Constants defining the event filtering apploed to external events by a timer.

HRTIM Timer External Event Latch

Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends.

HRTIM Deadtime Prescaler Ratio

Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG)

HRTIM Deadtime Rising Sign

Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge.

HRTIM Deadtime Rising Lock

Constants defining whether or not the deadtime (rising sign and value) is write protected.

HRTIM Deadtime Rising Sign Lock

Constants defining whether or not the deadtime rising sign is write protected.

HRTIM Deadtime Falling Sign

Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge.

HRTIM Deadtime Falling Lock

Constants defining whether or not the deadtime (falling sign and value) is write protected.

HRTIM Deadtime Falling Sign Lock

Constants defining whether or not the deadtime falling sign is write protected.

HRTIM Chopper Frequency

Constants defining the frequency of the generated high frequency carrier.

HRTIM Chopper Duty Cycle

Constants defining the duty cycle of the generated high frequency carrier Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)

HRTIM Chopper Start Pulse Width

Constants defining the pulse width of the first pulse of the generated high frequency carrier.

HRTIM Synchronization Options

Constants defining the options for synchronizing multiple HRTIM instances, as a master unit (generating a synchronization signal) or as a slave (waiting for a trigger to be synchronized)

HRTIM Synchronization Input Source

Constants defining defining the synchronization input source.

HRTIM Synchronization Output Source

Constants defining the source and event to be sent on the synchronization outputs.

HRTIM Synchronization Output Polarity

Constants defining the routing and conditioning of the synchronization output event.

HRTIM External Event Sources

Constants defining available sources associated to external events.

HRTIM External Event Polarity

Constants defining the polarity of an external event.

HRTIM External Event Sensitivity

Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event.

HRTIM External Event Fast Mode

Constants defining whether or not an external event is programmed in fast mode.

HRTIM External Event Filter

Constants defining the frequency used to sample an external event 6 input and the length (N) of the digital filter applied.

HRTIM External Event Prescaler

Constants defining division ratio between the timer clock frequency fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters.

HRTIM Fault Sources

Constants defining whether a faults is be triggered by any external or internal fault source.

HRTIM Fault Polarity

Constants defining the polarity of a fault event.

HRTIM Fault Filter

@ brief Constants defining the frequency used to sample the fault input and the length (N) of the digital filter applied

HRTIM Fault Lock

Constants defining whether or not the fault programming bits are write protected.

HRTIM External Fault Prescaler

Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used by the digital filters.

HRTIM Burst Mode Operating Mode

Constants defining if the burst mode is entered once or if it is continuously operating.

HRTIM Burst Mode Clock Source

Constants defining the clock source for the burst mode counter.

HRTIM Burst Mode Prescaler

Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller.

HRTIM Burst Mode Register Preload Enable

Constants defining whether or not burst mode registers preload mechanism is enabled, i.e.

HRTIM Burst Mode Trigger

Constants defining the events that can be used tor trig the burst mode operation.

HRTIM ADC Trigger Update Source

constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register).

HRTIM ADC Trigger Event

constants defining the events triggering ADC conversion.

HRTIM Burst DMA Registers Update

Constants defining the registers that can be written during a burst DMA operation.

HRTIM Burst Mode Control

Constants used to enable or disable the burst mode controller.

HRTIM Fault Mode Control

Constants used to enable or disable a fault channel.

HRTIM Software Timer Update

Constants used to force timer registers update.

HRTIM Software Timer Reset

Constants used to force timer counter reset.

HRTIM Output Level

Constants defining the level of a timer output.

HRTIM Output State

Constants defining the state of a timer output.

HRTIM Burst Mode Status

Constants defining the operating state of the burst mode controller.

HRTIM Current Push Pull Status

Constants defining on which output the signal is currently applied in push-pull mode.

HRTIM Idle Push Pull Status

Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered.

HRTIM Common Interrupt Enable
HRTIM Master Interrupt Enable
HRTIM Timing Unit Interrupt Enable
HRTIM Common Interrupt Flag
HRTIM Master Interrupt Flag
HRTIM Timing Unit Interrupt Flag
HRTIM Master DMA Request Enable
HRTIM Timing Unit DMA Request Enable
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STM32H753xx HAL User Manual: HRTIM Exported Functions

Modules
HRTIM Exported Functions
HRTIM

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Simple time base mode functions

Simple time base mode functions.

Simple output compare mode functions

Simple output compare functions.

Simple PWM output mode functions

Simple PWM output functions.

Simple input capture functions

Simple input capture functions.

Simple one pulse functions

Simple one pulse functions.

Configuration functions

HRTIM configuration functions.

Timer waveform configuration and functions

HRTIM timer configuration and control functions.

Peripheral state functions

Peripheral State functions.

Interrupts handling

Functions called when HRTIM generates an interrupt 7 interrupts can be generated by the master timer:

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STM32H753xx HAL User Manual: HSEM

Modules
HSEM
STM32H7xx_HAL_Driver

HSEM HAL module driver. More...

Modules

HSEM Exported Functions
HSEM Exported Types
HSEM Exported Constants
HSEM Exported Macros
HSEM Private Types
HSEM Private Variables
HSEM Private Constants
HSEM Private Macros

Detailed Description

HSEM HAL module driver.

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STM32H753xx HAL User Manual: HSEM Exported Functions

Modules
HSEM Exported Functions
HSEM

Modules

Take and Release functions

HSEM Take and Release functions.

HSEM Set and Get Key functions

HSEM Set and Get Key functions.

HSEM IRQ handler management

HSEM Notification functions.

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STM32H753xx HAL User Manual: I2C Configuration Structure definition

Data Structures
I2C Configuration Structure definition
I2C Exported Types

I2C Configuration Structure definition. More...

Data Structures

struct I2C_InitTypeDef

Detailed Description

I2C Configuration Structure definition.

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STM32H753xx HAL User Manual: I2C Exported Constants

Modules
I2C Exported Constants
I2C

Modules

I2C Sequential Transfer Options
I2C Addressing Mode
I2C Dual Addressing Mode
I2C Own Address2 Masks
I2C General Call Addressing Mode
I2C No-Stretch Mode
I2C Memory Address Size
I2C Transfer Direction
I2C Reload End Mode
I2C Start or Stop Mode
I2C Interrupt configuration definition

I2C Interrupt definition Elements values convention: 0xXXXXXXXX.

I2C Flag definition
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STM32H753xx HAL User Manual: I2C Exported Functions

Modules
I2C Exported Functions
I2C

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

IRQ Handler and Callbacks
Peripheral State, Mode and Error functions

Peripheral State, Mode and Error functions.

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STM32H753xx HAL User Manual: I2C Exported Types

Modules
I2C Exported Types
I2C

Modules

I2C Configuration Structure definition

I2C Configuration Structure definition.

HAL state structure definition

HAL State structure definition.

HAL mode structure definition

HAL Mode structure definition.

I2C Error Code definition

I2C Error Code definition.

I2C handle Structure definition

I2C handle Structure definition.

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STM32H753xx HAL User Manual: I2CEx

Modules
I2CEx
STM32H7xx_HAL_Driver

I2C Extended HAL module driver. More...

Modules

I2C Extended Exported Functions
I2C Extended Exported Constants

Detailed Description

I2C Extended HAL module driver.

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STM32H753xx HAL User Manual: I2C Extended Exported Constants

Modules
I2C Extended Exported Constants
I2CEx

Modules

I2C Extended Analog Filter
I2C Extended Fast Mode Plus
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STM32H753xx HAL User Manual: I2C Extended Exported Functions

Modules
I2C Extended Exported Functions
I2CEx

Modules

Extended features functions

Extended features functions.

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STM32H753xx HAL User Manual: I2S

Modules
I2S
STM32H7xx_HAL_Driver

I2S HAL module driver. More...

Modules

I2S Exported Types
I2S Exported Constants
I2S Exported Macros
I2S Private
I2S Exported Functions

Detailed Description

I2S HAL module driver.

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STM32H753xx HAL User Manual: I2S Exported Constants

Modules
I2S Exported Constants
I2S

Modules

I2S Error Defintion

I2S Error Code.

I2S Mode
I2S Standard
I2S Data Format
I2S MCLK Output
I2S Audio Frequency
I2S Clock Polarity
I2S MSB LSB Transmission
I2S Word Select Inversion
Control I2S IO Swap
Data Padding 24Bit
I2S Fifo Threshold
Keep IO State
Slave Extend FRE Detection
I2S Interrupt definition
I2S Flag definition
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STM32H753xx HAL User Manual: I2S Exported Functions

Modules
I2S Exported Functions
I2S Exported Macros | I2S

Modules

IO operation functions

Data transfers functions.

Peripheral State and Errors functions

Peripheral State functions.

Initialization and de-initialization functions

Initialization and Configuration functions.

I2S Private
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STM32H753xx HAL User Manual: I2SEx

Modules
I2SEx
STM32H7xx_HAL_Driver

I2S Extended HAL module driver. More...

Modules

I2S Extended Private Typedef
I2S Extended Private Functions
I2S Extended Exported Functions

Detailed Description

I2S Extended HAL module driver.

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STM32H753xx HAL User Manual: I2S Extended Exported Functions

Modules
I2S Extended Exported Functions
I2SEx

Modules

I2S Extended IO operation functions

I2SEx IO operation functions.

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STM32H753xx HAL User Manual: IRDA

Modules
IRDA
STM32H7xx_HAL_Driver

HAL IRDA module driver. More...

Modules

IRDA Private Constants
IRDA Exported Functions
IRDA Private Functions
IRDA Exported Types
IRDA Exported Constants
IRDA Exported Macros
IRDA Private Macros

Detailed Description

HAL IRDA module driver.

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STM32H753xx HAL User Manual: IRDA Exported Constants

Modules
IRDA Exported Constants
IRDA

Modules

IRDA Word Length
IRDA Parity
IRDA Transfer Mode
IRDA Low Power
IRDA State
IRDA Mode
IRDA One Bit Sampling
IRDA DMA Tx
IRDA DMA Rx
IRDA Request Parameters
IRDA Flags

Elements values convention: 0xXXXX.

IRDA Interrupts Definition

Elements values convention: 0000ZZZZ0XXYYYYYb.

IRDA Interruption Clear Flags
IRDA interruptions flags mask
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STM32H753xx HAL User Manual: IRDA Exported Functions

Modules
IRDA Exported Functions
IRDA

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IRDA Transmit and Receive functions.

Peripheral State and Error functions

IRDA State and Errors functions.

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STM32H753xx HAL User Manual: IRDAEx

Modules
IRDAEx
STM32H7xx_HAL_Driver

Modules

IRDAEx Private Macros
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STM32H753xx HAL User Manual: IWDG

Modules
IWDG
STM32H7xx_HAL_Driver

IWDG HAL module driver. More...

Modules

IWDG Private Defines
IWDG Exported Types
IWDG Exported Constants
IWDG Exported Macros
IWDG Exported Functions
IWDG Private Constants
IWDG Private Macros

Detailed Description

IWDG HAL module driver.

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STM32H753xx HAL User Manual: IWDG Exported Constants

Modules
IWDG Exported Constants
IWDG

Modules

IWDG Prescaler
IWDG Window option
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STM32H753xx HAL User Manual: IWDG Exported Functions

Modules
IWDG Exported Functions
IWDG

Modules

Initialization and Start functions

Initialization and Start functions.

IO operation functions

IO operation functions.

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STM32H753xx HAL User Manual: IWDG Exported Types

Data Structures
IWDG Exported Types
IWDG

Data Structures

struct | IWDG_InitTypeDef
IWDG Init structure definition. More...
struct | IWDG_HandleTypeDef
IWDG Handle Structure definition. More...
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STM32H753xx HAL User Manual: JPEG

Modules
JPEG
STM32H7xx_HAL_Driver

JPEG HAL module driver. More...

Modules

JPEG Exported Functions
JPEG Exported Types
JPEG Exported Constants
JPEG Exported Macros
JPEG Private Types
JPEG Private Defines
JPEG Private Variables
JPEG Private Constants
JPEG Private Macros
JPEG Private Functions Prototypes
JPEG Private Functions

Detailed Description

JPEG HAL module driver.

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STM32H753xx HAL User Manual: JPEG Configuration for encoding Structure definition

Data Structures
JPEG Configuration for encoding Structure definition
JPEG Exported Types

JPEG encoding configuration Structure definition. More...

Data Structures

struct JPEG_ConfTypeDef

Detailed Description

JPEG encoding configuration Structure definition.

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STM32H753xx HAL User Manual: JPEG Exported Constants

Modules
JPEG Exported Constants
JPEG

Modules

JPEG Error Code definition

JPEG Error Code definition.

JPEG Quantization Table Size

JPEG Quantization Table Size.

JPEG ColorSpace

JPEG Color Space.

JPEG Chrominance Sampling

JPEG Chrominance Sampling.

JPEG Image Quality

JPEG Min and Max Image Quality.

JPEG Interrupt configuration definition

JPEG Interrupt definition.

JPEG Flag definition

JPEG Flags definition.

JPEG Process Pause Resume definition

JPEG process pause, resume definition.

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STM32H753xx HAL User Manual: JPEG Exported Functions

Modules
JPEG Exported Functions
JPEG

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Configuration functions

JPEG Configuration functions.

encoding/decoding processing functions

processing functions.

JPEG Decode/Encode callback functions

JPEG process callback functions.

JPEG IRQ handler management

JPEG IRQ handler.

Peripheral State functions

Peripheral State functions.

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STM32H753xx HAL User Manual: JPEG Exported Types

Modules
JPEG Exported Types
JPEG

Modules

JPEG Configuration for encoding Structure definition

JPEG encoding configuration Structure definition.

HAL JPEG state structure definition

HAL JPEG State structure definition.

JPEG handle Structure definition

JPEG handle Structure definition.

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STM32H753xx HAL User Manual: JPEG handle Structure definition

Data Structures
JPEG handle Structure definition
JPEG Exported Types

JPEG handle Structure definition. More...

Data Structures

struct JPEG_HandleTypeDef

Detailed Description

JPEG handle Structure definition.

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STM32H753xx HAL User Manual: JPEG Private Types

Data Structures
JPEG Private Types
JPEG

Data Structures

struct | JPEG_ACHuffTableTypeDef
struct | JPEG_DCHuffTableTypeDef
struct | JPEG_AC_HuffCodeTableTypeDef
struct | JPEG_DC_HuffCodeTableTypeDef
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STM32H753xx HAL User Manual: LPTIM

Modules
LPTIM
STM32H7xx_HAL_Driver

LPTIM HAL module driver. More...

Modules

LPTIM Exported Functions
LPTIM Exported Types
LPTIM Exported Constants
LPTIM Exported Macros
LPTIM Private Constants
LPTIM Private Macros
LPTIM Private Functions

Detailed Description

LPTIM HAL module driver.

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STM32H753xx HAL User Manual: LPTIM Exported Constants

Modules
LPTIM Exported Constants
LPTIM

Modules

LPTIM Clock Source
LPTIM Clock Prescaler
LPTIM Output Polarity
LPTIM Clock Sample Time
LPTIM Clock Polarity
LPTIM Trigger Source
LPTIM External Trigger Polarity
LPTIM Trigger Sample Time
LPTIM Updating Mode
LPTIM Counter Source
LPTIM Input1 Source
LPTIM Input2 Source
LPTIM Flags Definition
LPTIM Interrupts Definition
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STM32H753xx HAL User Manual: LTDC

Modules
LTDC
STM32H7xx_HAL_Driver

LTDC HAL module driver. More...

Modules

LTDC Exported Functions
LTDC Exported Types
LTDC Exported Constants
LTDC Exported Macros
LTDC Private Types
LTDC Private Variables
LTDC Private Constants
LTDC Private Macros
LTDC Private Functions

Detailed Description

LTDC HAL module driver.

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STM32H753xx HAL User Manual: LTDC Exported Constants

Modules
LTDC Exported Constants
LTDC

Modules

LTDC Error Code
LTDC Layer
LTDC HS POLARITY
LTDC VS POLARITY
LTDC DE POLARITY
LTDC PC POLARITY
LTDC SYNC
LTDC BACK COLOR
LTDC Blending Factor1
LTDC Blending Factor2
LTDC Pixel format
LTDC Alpha
LTDC LAYER Config
LTDC Interrupts
LTDC Flags
LTDC Reload Type
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STM32H753xx HAL User Manual: MDIOS Exported Constants

Modules
MDIOS Exported Constants
MDIOS

Modules

MDIOS Preamble Check
MDIOS Input Output Registers Definitions
MDIOS Registers Flags
Interrupt Sources
MDIOS Interrupt Flags
MDIOS Wakeup Line
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STM32H753xx HAL User Manual: MDIOS Exported Functions

Modules
MDIOS Exported Functions
MDIOS

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

IO operation functions

MDIOS Read/Write functions.

Peripheral Control functions

MDIOS control functions.

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STM32H753xx HAL User Manual: MDIOS Exported Types

Modules
MDIOS Exported Types
MDIOS

Modules

MDIOS State structures definition
MDIOS Init Structure definition
MDIOS handle Structure definition
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STM32H753xx HAL User Manual: MDIOS Init Structure definition

Data Structures
MDIOS Init Structure definition
MDIOS Exported Types

Data Structures

struct MDIOS_InitTypeDef
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STM32H753xx HAL User Manual: MDIOS handle Structure definition

Data Structures
MDIOS handle Structure definition
MDIOS Exported Types

Data Structures

struct MDIOS_HandleTypeDef
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STM32H753xx HAL User Manual: MDMA

Modules
MDMA
STM32H7xx_HAL_Driver

MDMA HAL module driver. More...

Modules

MDMA Exported Types

MDMA Exported Types.

MDMA Exported Constants

MDMA Exported constants.

MDMA Exported Macros
MDMA Exported Functions
MDMA Private Types
MDMA Private Defines
MDMA Private Variables
MDMA Private Constants
MDMA Private Macros
MDMA Private Functions Prototypes
MDMA Private Functions
JPEG Private Functions

Detailed Description

MDMA HAL module driver.

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STM32H753xx HAL User Manual: MDMA Exported Constants

Modules
MDMA Exported Constants
MDMA

MDMA Exported constants. More...

Modules

MDMA Error Codes

MDMA Error Codes.

MDMA Request selection

MDMA_Request_selection.

MDMA Transfer Trigger Mode

MDMA Transfer Trigger Mode.

MDMA Priority level

MDMA Priority level.

MDMA Endianness

MDMA Endianness.

MDMA Source increment mode

MDMA Source increment mode.

MDMA Destination increment mode

MDMA Destination increment mode.

MDMA Source data size

MDMA Source data size.

MDMA Destination data size

MDMA Destination data size.

MDMA data alignment

MDMA MDMA data alignment.

MDMA Source burst

MDMA Source burst.

MDMA Destination burst

MDMA Destination burst.

MDMA interrupt enable definitions

MDMA interrupt enable definitions.

MDMA flag definitions

MDMA flag definitions.

Detailed Description

MDMA Exported constants.

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STM32H753xx HAL User Manual: MDMA Exported Functions

Modules
MDMA Exported Functions
MDMA

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Linked List operation functions

Linked list operation functions.

I/O operation functions

I/O operation functions.

Peripheral State functions

Peripheral State functions.

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STM32H753xx HAL User Manual: MMC

Modules
MMC
STM32H7xx_HAL_Driver

MMC HAL module driver. More...

Modules

MMC Private Functions
MMC Exported Types
Exported Constants
MMC Exported Macros

macros to handle interrupts and specific clock configurations

MMC Exported Functions
MMC Private Defines

Detailed Description

MMC HAL module driver.

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STM32H753xx HAL User Manual: MMC Exported Functions

Modules
MMC Exported Functions
MMC

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Input and Output operation functions

Data transfer functions.

Peripheral Control functions

management functions

MMC card related functions
Peripheral State and Errors functions
Perioheral Abort management
MMC Private Types
MMC Private Defines
MMC Private Variables
MMC Private Constants
MMC Private Macros
MMC Private Functions Prototypes
MMC Private Functions
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STM32H753xx HAL User Manual: MMC Exported Types

Modules
MMC Exported Types
MMC

Modules

MMC State enumeration structure
MMC Card State enumeration structure
MMC Handle Structure definition
Card Specific Data: CSD Register
Card Identification Data: CID Register
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STM32H753xx HAL User Manual: Card Specific Data: CSD Register

Data Structures
Card Specific Data: CSD Register
MMC Exported Types

Data Structures

struct HAL_MMC_CardCSDTypeDef
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STM32H753xx HAL User Manual: Card Identification Data: CID Register

Data Structures
Card Identification Data: CID Register
MMC Exported Types

Data Structures

struct HAL_MMC_CardCIDTypedef
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STM32H753xx HAL User Manual: MMCEx

Modules
MMCEx
STM32H7xx_HAL_Driver

MMC Extended HAL module driver. More...

Modules

MMCEx Exported Types
MMCEx Exported Functions

Detailed Description

MMC Extended HAL module driver.

MMC HAL extended module driver.

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STM32H753xx HAL User Manual: MMCEx Exported Functions

Modules
MMCEx Exported Functions
MMCEx

Modules

MultiBuffer functions

Multibuffer functions.

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STM32H753xx HAL User Manual: MMCEx Exported Types

Modules
MMCEx Exported Types
MMCEx

Modules

MMC Internal DMA Buffer structure
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STM32H753xx HAL User Manual: NAND

Modules
NAND
STM32H7xx_HAL_Driver

NAND HAL module driver. More...

Modules

NAND Exported Functions
NAND Exported Types
NAND Exported Macros
NAND Private Constants
NAND Private Macros

Detailed Description

NAND HAL module driver.

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STM32H753xx HAL User Manual: NAND Exported Functions

Modules
NAND Exported Functions
NAND

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output functions

Input Output and memory control functions.

Peripheral Control functions

management functions

Peripheral State functions

Peripheral State functions.

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STM32H753xx HAL User Manual: NOR

Modules
NOR
STM32H7xx_HAL_Driver

NOR driver modules. More...

Modules

NOR Private Defines
NOR Private Variables
NOR Exported Functions
NOR Exported Types
NOR Exported Macros
NOR Private Constants
NOR Private Macros

Detailed Description

NOR driver modules.

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STM32H753xx HAL User Manual: NOR Exported Functions

Modules
NOR Exported Functions
NOR

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output functions

Input Output and memory control functions.

NOR Control functions

management functions

NOR State functions

Peripheral State functions.

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STM32H753xx HAL User Manual: OPAMP

Modules
OPAMP
STM32H7xx_HAL_Driver

OPAMP module driver. More...

Modules

OPAMP Exported Functions
OPAMP Exported Types
OPAMP Exported Constants
OPAMP Private Constants

OPAMP Private constants and defines.

OPAMP Exported Macros
OPAMP Private Macros

Detailed Description

OPAMP module driver.

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STM32H753xx HAL User Manual: OPAMP Exported Constants

Modules
OPAMP Exported Constants
OPAMP

Modules

OPAMP Mode
OPAMP Non Inverting Input
OPAMP Inverting Input
OPAMP Pga Connect
OPAMP Pga Gain
OPAMP PowerMode
OPAMP VREF
OPAMP User Trimming
OPAMP Factory Trimming
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STM32H753xx HAL User Manual: OPAMP Exported Functions

Modules
OPAMP Exported Functions
OPAMP

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

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STM32H753xx HAL User Manual: OPAMPEx

Modules
OPAMPEx
STM32H7xx_HAL_Driver

Modules

OPAMPEx Exported Functions
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STM32H753xx HAL User Manual: OPAMPEx Exported Functions

Modules
OPAMPEx Exported Functions
OPAMPEx

Modules

OPAMPEx_Exported_Functions_Group1
Peripheral Control functions

Peripheral Control functions.

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STM32H753xx HAL User Manual: PCD

Modules
PCD
STM32H7xx_HAL_Driver

PCD HAL module driver. More...

Modules

PCD Private Macros
PCD Private Functions
PCD Exported Functions
PCD Exported Types
PCD Exported Constants
PCD Exported Macros

macros to handle interrupts and specific clock configurations

Detailed Description

PCD HAL module driver.

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STM32H753xx HAL User Manual: PCD Exported Constants

Modules
PCD Exported Constants
PCD

Modules

PCD Speed
PCD PHY Module
Turnaround Timeout Value
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STM32H753xx HAL User Manual: PCD Exported Functions

Modules
PCD Exported Functions
PCD | PCD Exported Macros

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral Control functions

management functions

Peripheral State functions

Peripheral State functions.

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STM32H753xx HAL User Manual: PCDEx Exported Functions

Modules
PCDEx Exported Functions
PCDEx

Modules

Peripheral Control functions

PCDEx control functions.

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STM32H753xx HAL User Manual: PWR

Modules
PWR
STM32H7xx_HAL_Driver

PWR HAL module driver. More...

Modules

PWR Exported Functions
PWR Exported Types
PWR Exported Constants
PWR Exported Macro
PWR Private Constants
PWR Private Macros

Detailed Description

PWR HAL module driver.

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STM32H753xx HAL User Manual: PWR Exported Constants

Modules
PWR Exported Constants
PWR

Modules

PWR PVD detection level
PWR PVD Mode
PWR Regulator state in SLEEP/STOP mode
PWR SLEEP mode entry
PWR STOP mode entry
PWR Regulator Voltage Scale
PWR Flag
PWR Enable WUP Mask
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STM32H753xx HAL User Manual: PWR Exported Functions

Modules
PWR Exported Functions
PWR

Modules

Initialization and De-Initialization functions

Initialization and De-Initialization functions.

Peripheral Control functions

Low Power modes configuration functions.

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STM32H753xx HAL User Manual: PWR Exported Types

Data Structures
PWR Exported Types
PWR

Data Structures

struct PWR_PVDTypeDef
PWR PVD configuration structure definition. More...
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STM32H753xx HAL User Manual: PWR Private Constants

Modules
PWR Private Constants
PWR

Modules

PWR PVD Mode Mask
PWR PVD EXTI Line
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STM32H753xx HAL User Manual: PWR Private Macros

Modules
PWR Private Macros
PWR

Modules

PWR Private macros to check input parameters
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STM32H753xx HAL User Manual: PWREx

Modules
PWREx
STM32H7xx_HAL_Driver

PWR Extended HAL module driver. More...

Modules

PWREx Exported Functions
PWREx Exported Types
PWREx Exported Constants
PWREx Exported Macro
PWREx Private Macros
PWREx_Private_Constants

Detailed Description

PWR Extended HAL module driver.

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STM32H753xx HAL User Manual: PWREx Exported Constants

Modules
PWREx Exported Constants
PWREx

Modules

PWREx Wake-Up Pins
PWREx Pin Polarity configuration
PWREx Pin Pull configuration
PWREx Wakeup Pins Flags.
PWREx Domains definition
PWREx Domain Flags definition
PWREx D3 Domain State
PWREx Supply configuration
PWREx AVD detection level
PWREx AVD Mode
PWREx Regulator Voltage Scale
PWR battery charging resistor selection
PWREx VBAT Thresholds
PWREx Temperature Thresholds
PWREx AVD EXTI Line 16
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STM32H753xx HAL User Manual: PWREx Exported Functions

Modules
PWREx Exported Functions
PWREx

Modules

Power supply control functions

Power supply control functions.

Low power control functions

Low power control functions.

Peripherals control functions

Peripherals control functions.

Power Monitoring functions

Power Monitoring functions.

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STM32H753xx HAL User Manual: PWREx Exported Types

Data Structures
PWREx Exported Types
PWREx

Data Structures

struct | PWREx_AVDTypeDef
PWREx AVD configuration structure definition. More...
struct | PWREx_WakeupPinTypeDef
PWREx Wakeup pin configuration structure definition. More...
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STM32H753xx HAL User Manual: PWREx_Private_Constants

Modules
PWREx_Private_Constants
PWREx

Modules

PWR Extended AVD Mode Mask
PWR Extended Flag Setting Time Out Value
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STM32H753xx HAL User Manual: PWREx Private Macros

Modules
PWREx Private Macros
PWREx

Modules

PWREx Private macros to check input parameters
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STM32H753xx HAL User Manual: QSPI

Modules
QSPI
STM32H7xx_HAL_Driver

QSPI HAL module driver. More...

Modules

QSPI Private Constants
QSPI Private Macros
QSPI Exported Functions
QSPI Exported Types
QSPI Exported Constants
QSPI Exported Macros

Detailed Description

QSPI HAL module driver.

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STM32H753xx HAL User Manual: QSPI Exported Constants

Modules
QSPI Exported Constants
QSPI

Modules

QSPI Error Code
QSPI Sample Shifting
QSPI ChipSelect High Time
QSPI Clock Mode
QSPI Flash Select
QSPI Dual Flash Mode
QSPI Address Size
QSPI Alternate Bytes Size
QSPI Instruction Mode
QSPI Address Mode
QSPI Alternate Bytes Mode
QSPI Data Mode
QSPI DDR Mode
QSPI DDR Data Output Delay
QSPI Send Instruction Mode
QSPI Match Mode
QSPI Automatic Stop
QSPI Timeout Activation
QSPI Flags
QSPI Interrupts
QSPI Timeout definition

QSPI Timeout definition.

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STM32H753xx HAL User Manual: RCC

Modules
RCC
STM32H7xx_HAL_Driver

RCC HAL module driver. More...

Modules

RCC Private Macros
RCC Private Variables
RCC Exported Functions
RCC Exported Types
RCC Exported Constants
RCC Exported Macros
RCC Private Constants

Detailed Description

RCC HAL module driver.

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STM32H753xx HAL User Manual: RCC Exported Constants

Modules
RCC Exported Constants
RCC

Modules

RCC Oscillator Type
RCC HSE Config
RCC LSE Config
RCC HSI Config
RCC HSI48 Config
RCC LSI Config
RCC CSI Config
RCC PLL Config
RCC PLL Clock Source
RCC PLL Clock Output
RCC PLL1 VCI Range
RCC PLL1 VCO Range
RCC System Clock Type
RCC System Clock Source
RCC SYS Clock Source
RCC HCLK Clock Source
RCC APB3 Clock Source
RCC APB1 Clock Source
RCC APB2 Clock Source
RCC APB4 Clock Source
RCC RTC Clock Source
RCC MCO Index
RCC MCO1 Clock Source
RCC MCO2 Clock Source
RCC MCOx Clock Prescaler
RCC Interrupt
RCC Flag

Elements values convention: 0XXYYYYYb.

LSE Drive Config
RCC Stop WakeUpClock
RCC Stop KernelWakeUpClock
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STM32H753xx HAL User Manual: RCC Exported Functions

Modules
RCC Exported Functions
RCC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

RCC clocks control functions.

RCC_Exported_Functions_Group2
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STM32H753xx HAL User Manual: RCC Exported Types

Data Structures
RCC Exported Types
RCC

Data Structures

struct | RCC_PLLInitTypeDef
RCC PLL configuration structure definition. More...
struct | RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition. More...
struct | RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition. More...
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STM32H753xx HAL User Manual: RCCEx

Modules
RCCEx
STM32H7xx_HAL_Driver

RCC HAL module driver. More...

Modules

Private Defines
RCCEx Private Macros
Exported Functions
RCCEx Exported Types
RCCEx Exported Constants
RCCEx Exported Macros
Extended Peripheral Control functions

Extended Peripheral Control functions.

RCCEx_Exported_Functions_Group2
Extended Clock Recovery System Control functions

Extended Clock Recovery System Control functions.

Detailed Description

RCC HAL module driver.

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STM32H753xx HAL User Manual: Exported Functions

Modules
Exported Functions
RCCEx

Modules

Extended Peripheral Control functions

Extended Peripheral Control functions.

Private Functions
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STM32H753xx HAL User Manual: RCCEx Exported Types

Data Structures
RCCEx Exported Types
RCCEx

Data Structures

struct | RCC_PLL2InitTypeDef
PLL2 Clock structure definition. More...
struct | RCC_PLL3InitTypeDef
PLL3 Clock structure definition. More...
struct | PLL1_ClocksTypeDef
RCC PLL1 Clocks structure definition. More...
struct | PLL2_ClocksTypeDef
RCC PLL2 Clocks structure definition. More...
struct | PLL3_ClocksTypeDef
RCC PLL3 Clocks structure definition. More...
struct | RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition. More...
struct | RCC_CRSInitTypeDef
RCC_CRS Init structure definition. More...
struct | RCC_CRSSynchroInfoTypeDef
RCC_CRS Synchronization structure definition. More...
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STM32H753xx HAL User Manual: RCCEx Private Macros

Modules
RCCEx Private Macros
RCCEx

Modules

RCC Private macros to check input parameters
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STM32H753xx HAL User Manual: RNG

Modules
RNG
STM32H7xx_HAL_Driver

RNG HAL module driver. More...

Modules

RNG Exported Types
RNG Private Constants
RNG Exported Functions

Detailed Description

RNG HAL module driver.

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STM32H753xx HAL User Manual: RNG Exported Constants

Modules
RNG Exported Constants
RNG Exported Types

Modules

RNG Interrupt definition
RNG Flag definition
RNG Clock Error Detection
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STM32H753xx HAL User Manual: RNG Exported Functions

Modules
RNG Exported Functions
RNG Exported Types | RNG

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

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STM32H753xx HAL User Manual: RNG Exported Types

Modules
RNG Exported Types
RNG

Modules

RNG Init Structure definition
RNG Exported Constants
RNG Exported Macros
RNG Exported Functions
RNG Private Types
RNG Private Defines
RNG Private Variables
RNG Private Constants
RNG Private Macros
RNG Private Functions Prototypes
RNG Private Functions
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STM32H753xx HAL User Manual: RNG Init Structure definition

Data Structures | Modules
RNG Init Structure definition
RNG Exported Types

Data Structures

struct RNG_InitTypeDef

Modules

RNG State Structure definition
RNG Handle Structure definition
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STM32H753xx HAL User Manual: RNG Handle Structure definition

Data Structures
RNG Handle Structure definition
RNG Init Structure definition

Data Structures

struct RNG_HandleTypeDef
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STM32H753xx HAL User Manual: RTC

Modules
RTC
STM32H7xx_HAL_Driver

RTC HAL module driver. More...

Modules

RTC Exported Functions
RTC Private functions
RTC Exported Types
RTC Exported Constants
RTC Exported Macros
RTC Private Constants
RTC Private Macros

Detailed Description

RTC HAL module driver.

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STM32H753xx HAL User Manual: RTC Exported Constants

Modules
RTC Exported Constants
RTC

Modules

RTC Hour Formats
RTC Output Polarity Definitions
RTC Output Type ALARM OUT
RTC Output ALARM OUT Remap
RTC AM PM Definitions
RTC DayLight Saving Definitions
RTC Store Operation Definitions
RTC Input Parameter Format Definitions
RTC Month Date Definitions
RTC WeekDay Definitions
RTC Alarm Date WeekDay Definitions
RTC Alarm Mask Definitions
RTC Alarms Definitions
RTC Alarm Sub Seconds Masks Definitions
RTC Interrupts Definitions
RTC Flags Definitions
Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Exported Functions

Modules
RTC Exported Functions
RTC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

RTC Time and Date functions

RTC Time and Date functions.

RTC Alarm functions

RTC Alarm functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: RTC Private Macros

Modules
RTC Private Macros
RTC

Modules

RTC Private macros to check input parameters
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STM32H753xx HAL User Manual: RTCEx

Modules
RTCEx
STM32H7xx_HAL_Driver

RTC Extended HAL module driver. More...

Modules

RTCEx Exported Functions
RTCEx Exported Types
RTCEx Exported Constants
RTCEx Exported Macros
RTCEx Private Constants
RTCEx Private Macros

Detailed Description

RTC Extended HAL module driver.

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STM32H753xx HAL User Manual: RTCEx Exported Constants

Modules
RTCEx Exported Constants
RTCEx

Modules

RTC Output Selection Definitions
RTC Backup Registers Definitions
RTC TimeStamp Edges Definitions
RTC TimeStamp Pins Selection
RTC Tamper Pins Definitions
RTC Tamper Interrupts Definitions
RTC Tamper Triggers Definitions
RTC Tamper EraseBackUp Definitions
RTC Tamper Mask Flag Definitions
RTC Tamper Filter Definitions
RTC Tamper Sampling Frequencies Definitions
RTC Tamper Pin Precharge Duration Definitions
RTC Tamper TimeStamp On Tamper Detection Definitions
RTC Tamper Pull Up Definitions
RTC Wakeup Timer Definitions
RTC Smooth Calib Period Definitions
RTC Smooth Calib Plus Pulses Definitions
RTC Calib Output Selection Definitions
RTC Add 1 Second Parameter Definitions
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STM32H753xx HAL User Manual: RTCEx Exported Functions

Modules
RTCEx Exported Functions
RTCEx

Modules

RTC TimeStamp and Tamper functions

RTC TimeStamp and Tamper functions.

RTC Wake-up functions

RTC Wake-up functions.

Extended Peripheral Control functions

Extended Peripheral Control functions.

Extended features functions

Extended features functions.

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STM32H753xx HAL User Manual: RTCEx Exported Types

Data Structures
RTCEx Exported Types
RTCEx

Data Structures

struct RTC_TamperTypeDef
RTC Tamper structure definition. More...
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STM32H753xx HAL User Manual: RTCEx Private Macros

Modules
RTCEx Private Macros
RTCEx

Modules

Private macros to check input parameters
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STM32H753xx HAL User Manual: SAI

Modules
SAI
STM32H7xx_HAL_Driver

SAI HAL module driver. More...

Modules

SAI Private Typedefs
SAI Private Constants
SAI Private Functions

Private functions.

SAI Exported Functions
SAI Exported Types
SAI Exported Constants
SAI Exported Macros

macros to handle interrupts and specific configurations

SAI_Private_Macros

Detailed Description

SAI HAL module driver.

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STM32H753xx HAL User Manual: SAI Exported Constants

Modules
SAI Exported Constants
SAI

Modules

SAI Error Code
SAI External synchronisation
SAI Supported protocol
SAI protocol data size
SAI Audio Frequency
SAI Block Master Clock OverSampling
SAI PDM Clock Enable
SAI Block Mode
SAI Block Protocol
SAI Block Data Size
SAI Block MSB LSB transmission
SAI Block Clock Strobing
SAI Block Synchronization
SAI Block Output Drive
SAI Block NoDivider
SAI Block FS Definition
SAI Block FS Polarity
SAI Block FS Offset
SAI Block Slot Size
SAI Block Slot Active
SAI Mono Stereo Mode
SAI TRIState Management
SAI Block Fifo Threshold
SAI Block Companding Mode
SAI Block Mute Value
SAI Block Interrupts Definition
SAI Block Flags Definition
SAI Block Fifo Status Level
Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Exported Functions

Modules
SAI Exported Functions
SAI

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State functions

Peripheral State functions.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Frame Structure definition

Data Structures
SAI Frame Structure definition
SAI Exported Types

SAI Frame Init structure definition. More...

Data Structures

struct SAI_FrameInitTypeDef

Detailed Description

SAI Frame Init structure definition.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Init Structure definition

Data Structures
SAI Init Structure definition
SAI Exported Types

SAI Init Structure definition. More...

Data Structures

struct SAI_InitTypeDef

Detailed Description

SAI Init Structure definition.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI PDM Structure definition

Data Structures
SAI PDM Structure definition
SAI Exported Types

SAI PDM Init structure definition. More...

Data Structures

struct SAI_PdmInitTypeDef

Detailed Description

SAI PDM Init structure definition.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAI Slot Structure definition

Data Structures
SAI Slot Structure definition
SAI Exported Types

SAI Block Slot Init Structure definition. More...

Data Structures

struct SAI_SlotInitTypeDef

Detailed Description

SAI Block Slot Init Structure definition.

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STM32H753xx HAL User Manual: SAIEx Extended Exported Functions

Modules
SAIEx Extended Exported Functions
SAIEx

Modules

Peripheral Control functions

SAIEx control functions.

Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SAIEx Exported Types

Data Structures
SAIEx Exported Types
SAIEx

Data Structures

struct SAIEx_PdmMicDelayParamTypeDef
PDM microphone delay structure definition. More...
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STM32H753xx HAL User Manual: SD

Modules
SD
STM32H7xx_HAL_Driver

SD HAL module driver. More...

Modules

SD Private Functions
SD Exported Types
Exported Constants
SD Exported Macros

macros to handle interrupts and specific clock configurations

SD Exported Functions
SD Private Defines

Detailed Description

SD HAL module driver.

Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SD Exported Functions

Modules
SD Exported Functions
SD

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Input and Output operation functions

Data transfer functions.

Peripheral Control functions

management functions

SD card related functions
Peripheral State and Errors functions
Perioheral Abort management
SD Private Types
SD Private Defines
SD Private Variables
SD Private Constants
SD Private Macros
SD Private Functions Prototypes
SD Private Functions
Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SD Exported Types

Modules
SD Exported Types
SD

Modules

SD State enumeration structure
SD Card State enumeration structure
SD Handle Structure definition
Card Specific Data: CSD Register
Card Identification Data: CID Register
SD Card Status returned by ACMD13
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STM32H753xx HAL User Manual: Card Specific Data: CSD Register

Data Structures
Card Specific Data: CSD Register
SD Exported Types

Data Structures

struct HAL_SD_CardCSDTypedef
Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Card Identification Data: CID Register

Data Structures
Card Identification Data: CID Register
SD Exported Types

Data Structures

struct HAL_SD_CardCIDTypedef
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STM32H753xx HAL User Manual: SD Card Status returned by ACMD13

Data Structures
SD Card Status returned by ACMD13
SD Exported Types

Data Structures

struct HAL_SD_CardStatusTypedef
Generated on Fri Apr 28 2017 15:42:51 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SDEx

Modules
SDEx
STM32H7xx_HAL_Driver

SD Extended HAL module driver. More...

Modules

SDEx Exported Types
SDEx Exported Functions

Detailed Description

SD Extended HAL module driver.

SD HAL extended module driver.

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STM32H753xx HAL User Manual: SDEx Exported Functions

Modules
SDEx Exported Functions
SDEx

Modules

MultiBuffer functions

Multibuffer functions.

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STM32H753xx HAL User Manual: SDEx Exported Types

Modules
SDEx Exported Types
SDEx

Modules

SD Card Internal DMA Buffer structure
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STM32H753xx HAL User Manual: SDRAM

Modules
SDRAM
STM32H7xx_HAL_Driver

SDRAM driver modules. More...

Modules

SDRAM Exported Functions
SDRAM Exported Types
SDRAM Exported Macros

Detailed Description

SDRAM driver modules.

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STM32H753xx HAL User Manual: SDRAM Exported Functions

Modules
SDRAM Exported Functions
SDRAM

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output functions

Input Output and memory control functions.

Control functions

management functions

State functions

Peripheral State functions.

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STM32H753xx HAL User Manual: SMARTCARD

Modules
SMARTCARD
STM32H7xx_HAL_Driver

HAL SMARTCARD module driver. More...

Modules

SMARTCARD Private Constants
SMARTCARD Exported Functions
SMARTCARD Private Functions
SMARTCARD Exported Types
SMARTCARD Exported Constants
SMARTCARD Exported Macros
SMARTCARD Private Macros

Detailed Description

HAL SMARTCARD module driver.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMARTCARD Exported Constants

Modules
SMARTCARD Exported Constants
SMARTCARD

Modules

SMARTCARD Word Length
SMARTCARD Number of Stop Bits
SMARTCARD Parity
SMARTCARD Transfer Mode
SMARTCARD Clock Polarity
SMARTCARD Clock Phase
SMARTCARD Last Bit
SMARTCARD FIFO mode

SMARTCARD FIFO mode.

SMARTCARD TXFIFO threshold level

SMARTCARD TXFIFO level.

SMARTCARD RXFIFO threshold level

SMARTCARD RXFIFO level.

SMARTCARD One Bit Sampling Method
SMARTCARD NACK Enable
SMARTCARD Timeout Enable
SMARTCARD advanced feature TX pin active level inversion
SMARTCARD advanced feature RX pin active level inversion
SMARTCARD advanced feature Binary Data inversion
SMARTCARD advanced feature RX TX pins swap
SMARTCARD advanced feature Overrun Disable
SMARTCARD advanced feature DMA Disable on Rx Error
SMARTCARD advanced feature MSB first
SMARTCARD Request Parameters
SMARTCARD auto retry counter LSB position in CR3 register
SMARTCARD guard time value LSB position in GTPR register
SMARTCARD block length LSB position in RTOR register
SMARTCARD interruptions flags mask
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STM32H753xx HAL User Manual: SMARTCARD Exported Functions

Modules
SMARTCARD Exported Functions
SMARTCARD

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

SMARTCARD Transmit and Receive functions.

Peripheral State and Errors functions

SMARTCARD State and Errors functions.

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STM32H753xx HAL User Manual: SMARTCARDEx

Modules
SMARTCARDEx
STM32H7xx_HAL_Driver

SMARTCARD Extended HAL module driver. More...

Modules

SMARTCARD Extended Exported Functions
SMARTCARD Extended Private Macros
SMARTCARD Extended Exported Constants

Detailed Description

SMARTCARD Extended HAL module driver.

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STM32H753xx HAL User Manual: SMARTCARD Extended Exported Constants

Modules
SMARTCARD Extended Exported Constants
SMARTCARDEx

Modules

SMARTCARD Transmission Completion Indication
SMARTCARD advanced feature initialization type
SMARTCARD Flags

Elements values convention: 0xXXXX.

SMARTCARD Interrupts Definition

Elements values convention: 000ZZZZZ0XXYYYYYb.

SMARTCARD Interruption Clear Flags
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STM32H753xx HAL User Manual: SMARTCARD Extended Exported Functions

Modules
SMARTCARD Extended Exported Functions
SMARTCARDEx

Modules

Extended Peripheral Control functions

Extended control functions.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMBUS

Modules
SMBUS
STM32H7xx_HAL_Driver

SMBUS HAL module driver. More...

Modules

SMBUS Private Constants
SMBUS Exported Functions
SMBUS Exported Types
SMBUS Exported Constants
SMBUS Exported Macros
SMBUS Private Macros
SMBUS Private Functions

Data transfers Private functions.

Detailed Description

SMBUS HAL module driver.

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STM32H753xx HAL User Manual: SMBUS Configuration Structure definition

Data Structures
SMBUS Configuration Structure definition
SMBUS Exported Types

SMBUS Configuration Structure definition. More...

Data Structures

struct SMBUS_InitTypeDef

Detailed Description

SMBUS Configuration Structure definition.

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STM32H753xx HAL User Manual: SMBUS Exported Constants

Modules
SMBUS Exported Constants
SMBUS

Modules

SMBUS Analog Filter
SMBUS addressing mode
SMBUS dual addressing mode
SMBUS own address2 masks
SMBUS general call addressing mode
SMBUS nostretch mode
SMBUS packet error check mode
SMBUS peripheral mode
SMBUS ReloadEndMode definition
SMBUS StartStopMode definition
SMBUS XferOptions definition
SMBUS Interrupt configuration definition

SMBUS Interrupt definition Elements values convention: 0xXXXXXXXX.

SMBUS Flag definition

Flag definition Elements values convention: 0xXXXXYYYY.

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STM32H753xx HAL User Manual: SMBUS Exported Functions

Modules
SMBUS Exported Functions
SMBUS

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

IRQ Handler and Callbacks
Peripheral State and Errors functions

Peripheral State and Errors functions.

SMBUS Private Functions

Data transfers Private functions.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SMBUS Exported Types

Modules
SMBUS Exported Types
SMBUS

Modules

SMBUS Configuration Structure definition

SMBUS Configuration Structure definition.

HAL state definition

HAL State definition.

SMBUS Error Code definition

SMBUS Error Code definition.

SMBUS handle Structure definition

SMBUS handle Structure definition.

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STM32H753xx HAL User Manual: SMBUS handle Structure definition

Data Structures
SMBUS handle Structure definition
SMBUS Exported Types

SMBUS handle Structure definition. More...

Data Structures

struct SMBUS_HandleTypeDef

Detailed Description

SMBUS handle Structure definition.

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STM32H753xx HAL User Manual: SPDIFRX Exported Constants

Modules
SPDIFRX Exported Constants
SPDIFRX

Modules

SPDIFRX Error Code
SPDIFRX Input Selection
SPDIFRX Maximum Retries
SPDIFRX Wait For Activity
SPDIFRX Preamble Type Mask
SPDIFRX Channel Status Mask
SPDIFRX Validity Mask
SPDIFRX Parity Error Mask
SPDIFRX Channel Selection
SPDIFRX Data Format
SPDIFRX Stereo Mode
SPDIFRX State
SPDIFRX Interrupts Definition
SPDIFRX Flags Definition
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STM32H753xx HAL User Manual: SPI

Modules
SPI
STM32H7xx_HAL_Driver

SPI HAL module driver. More...

Modules

SPI Private Constants
SPI Private Functions

Private functions.

SPI Exported Functions
SPI Exported Types
SPI Exported Constants
SPI Exported Macros
SPI Private Macros

Detailed Description

SPI HAL module driver.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPI Exported Constants

Modules
SPI Exported Constants
SPI

Modules

SPI FIFO Type
SPI Error Codes
SPI Mode
SPI Direction Mode
SPI Data Size
SPI Clock Polarity
SPI Clock Phase
SPI Slave Select Management
SPI NSS Pulse Mode
SPI BaudRate Prescaler
SPI MSB LSB Transmission
SPI TI Mode
SPI CRC Calculation
SPI CRC Length
SPI Fifo Threshold
SPI CRC Calculation Initialization Pattern
SPI NSS Polarity
Keep IO State
Control SPI IO Swap
SPI Master SS Ideleness
SPI Master Inter-Data Ideleness
SPI Master Receiver AutoSuspend
SPI Underrun Detection
SPI Underrun Behaviour
SPI Interrupt Definition
SPI Flags Definition
SPI Reception FIFO Status Level
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STM32H753xx HAL User Manual: SPI Exported Functions

Modules
SPI Exported Functions
SPI

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State and Errors functions

SPI control functions.

Generated on Fri Apr 28 2017 15:42:52 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SPIEx

Modules
SPIEx
STM32H7xx_HAL_Driver

SPI Extended HAL module driver. More...

Modules

SPIEx Exported Functions

Detailed Description

SPI Extended HAL module driver.

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STM32H753xx HAL User Manual: SPIEx Exported Functions

Modules
SPIEx Exported Functions
SPIEx

Modules

IO operation functions

Data transfers functions.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SRAM

Modules
SRAM
STM32H7xx_HAL_Driver

SRAM driver modules. More...

Modules

SRAM Exported Functions
SRAM Exported Types
SRAM Exported Macros

Detailed Description

SRAM driver modules.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SRAM Exported Functions

Modules
SRAM Exported Functions
SRAM

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input Output and memory control functions

Input Output and memory control functions.

Control functions

Control functions.

Peripheral State functions

Peripheral State functions.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: STM32H7xx_HAL_Driver

Modules
STM32H7xx_HAL_Driver

Modules

HAL

HAL module driver.

ADC

ADC HAL module driver.

ADCEx

ADC Extended HAL module driver.

CEC

HAL CEC module driver.

COMP

COMP HAL module driver.

CORTEX

CORTEX HAL module driver.

CRC

CRC HAL module driver.

CRYP

CRYP HAL module driver.

CRYPEx

CRYP Extension HAL module driver.

DAC

DAC driver modules.

DACEx

DAC Extended HAL module driver.

DCMI

DCMI HAL module driver.

DFSDM

DFSDM HAL driver module.

DMA

DMA HAL module driver.

DMA2D

DMA2D HAL module driver.

DMAEx

DMA Extended HAL module driver.

ETH

ETH HAL module driver.

ETHEx

ETH HAL Extended module driver.

FDCAN

FDCAN HAL module driver.

FLASH

FLASH HAL module driver.

FLASHEx

FLASH HAL Extension module driver.

GPIO

GPIO HAL module driver.

HASH

HASH HAL module driver.

HASHEx

HASH HAL extended module driver.

HRTIM

HRTIM HAL module driver.

HSEM

HSEM HAL module driver.

I2C

I2C HAL module driver.

I2CEx

I2C Extended HAL module driver.

I2SEx

I2S Extended HAL module driver.

IRDA

HAL IRDA module driver.

JPEG

JPEG HAL module driver.

LPTIM

LPTIM HAL module driver.

LTDC

LTDC HAL module driver.

MDIOS

HAL MDIOS module driver.

MDMA

MDMA HAL module driver.

MMC

MMC HAL module driver.

MMCEx

MMC Extended HAL module driver.

NAND

NAND HAL module driver.

NOR

NOR driver modules.

OPAMP

OPAMP module driver.

PCD

PCD HAL module driver.

PCDEx

PCD Extended HAL module driver.

PWR

PWR HAL module driver.

PWREx

PWR Extended HAL module driver.

QSPI

QSPI HAL module driver.

RCC

RCC HAL module driver.

RCCEx

RCC HAL module driver.

RTC

RTC HAL module driver.

RTCEx

RTC Extended HAL module driver.

SAI

SAI HAL module driver.

SAIEx

SAI Extended HAL module driver.

SDEx

SD Extended HAL module driver.

SDRAM

SDRAM driver modules.

SMARTCARD

HAL SMARTCARD module driver.

SMARTCARDEx

SMARTCARD Extended HAL module driver.

SMBUS

SMBUS HAL module driver.

SPDIFRX

SPDIFRX HAL module driver.

SPI

SPI HAL module driver.

SPIEx

SPI Extended HAL module driver.

SRAM

SRAM driver modules.

SWPMI

HAL SWPMI module driver.

TIM

TIM HAL module driver.

TIMEx

TIM Extended HAL module driver.

UART

HAL UART module driver.

UARTEx

UART Extended HAL module driver.

USART

HAL USART Synchronous module driver.

WWDG

WWDG HAL module driver.

CRCEx

CRC Extended HAL module driver.

GPIOEx
HCD

HCD HAL module driver.

I2S

I2S HAL module driver.

IRDAEx
IWDG

IWDG HAL module driver.

OPAMPEx
RNG

RNG HAL module driver.

SD

SD HAL module driver.

USARTEx
Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SWPMI

Modules
SWPMI
STM32H7xx_HAL_Driver

HAL SWPMI module driver. More...

Modules

SWPMI Exported Functions
SWPMI Private Functions
SWPMI Exported Types
SWPMI Exported Constants
SWPMI Exported Macros
SWPMI Private Types
SWPMI Private Variables
SWPMI Private Constants
SWPMI Private Macros

Detailed Description

HAL SWPMI module driver.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: SWPMI Exported Constants

Modules
SWPMI Exported Constants
SWPMI

Modules

SWPMI Error Code Bitmap
SWPMI Voltage Class
SWPMI Tx Buffering Mode
SWPMI Rx Buffering Mode
SWPMI Status Flags

Elements values convention: 0xXXXXXXXX.

SWPMI Interrupts Definition

Elements values convention: 0xXXXX.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM

Modules
TIM
STM32H7xx_HAL_Driver

TIM HAL module driver. More...

Modules

TIM Exported Functions
TIM Exported Types
TIM Exported Constants
TIM Exported Macros
TIM Private Constants
TIM Private Macros
TIM Private Functions

Detailed Description

TIM HAL module driver.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Exported Constants

Modules
TIM Exported Constants
TIM

Modules

TIM Extended Event Source
TIM Input Channel polarity
TIM ETR Polarity
TIM ETR Prescaler
TIM Counter Mode
TIM Clock Division
TIM Output Compare State
TIM Auto-Reload Preload
TIM Output Fast State
TIM Output Compare Polarity
TIM Complementary Output Compare Polarity
TIM Output Compare Idle State
TIM Complementary Output Compare Idle State
TIM Input Capture Polarity
TIM Input Capture Selection
TIM Input Capture Prescaler
TIM One Pulse Mode
TIM Encoder Mode
TIM interrupt Definition
TIM Commutation Source
TIM DMA Sources
TIM Flag Definition
TIM Clock Source
TIM Clock Polarity
TIM Clock Prescaler
TIM Clear Input Polarity
TIM Clear Input Prescaler
TIM Off-state Selection for Run Mode
TIM Off-state Selection for Idle Mode
TIM Lock Configuration
TIM Break Input Enable
TIM Break Input Polarity
TIM Automatic Output Enable
TIM Master Mode Selection
TIM Master Mode Selection 2 (TRGO2)
TIM Master/Slave Mode
TIM Slave mode
TIM Trigger Selection
TIM Trigger Polarity
TIM Trigger Prescaler
TIM TI1 Input Selection
TIM DMA Burst Length
TIM DMA Handle Index
TIM Capture/Compare Channel State
Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Extended Exported Constants

Modules
TIM Extended Exported Constants
TIMEx

Modules

TIM Extended Channel
TIM Output Compare and PWM Modes
TIM Extended Clear Input Source
TIMEX Break input 2 Enable
TIM Extended Break Input 2 Polarity
TIM Trigger Selection
TIM Extended Event Source
TIM DMA Base Address
TIM Extended Remapping
Group Channel 5 and Channel 1, 2 or 3
Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Extended Exported Macros

Modules
TIM Extended Exported Macros
TIMEx

Modules

TIM Extended Private Macros
TIMEx Private Functions
TIM Extended Exported Functions
Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: TIM Extended Exported Types

Data Structures
TIM Extended Exported Types
TIMEx

Data Structures

struct | TIM_HallSensor_InitTypeDef
TIM Hall sensor Configuration Structure definition. More...
struct | TIMEx_BreakInputConfigTypeDef
TIM Break/Break2 input configuration. More...
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STM32H753xx HAL User Manual: UART

Modules
UART
STM32H7xx_HAL_Driver

HAL UART module driver. More...

Modules

UART Private Constants
UART Exported Functions
UART Private Functions
UART Exported Types
UART Exported Constants
UART Exported Macros
UART Private Variables
UART Private Macros

Detailed Description

HAL UART module driver.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UART Exported Constants

Modules
UART Exported Constants
UART

Modules

UART Number of Stop Bits
UART Parity
UART Hardware Flow Control
UART Transfer Mode
UART State
UART Over Sampling
UART One Bit Sampling Method
UART Prescaler
UART FIFO mode

UART FIFO mode.

UART TXFIFO threshold level

UART TXFIFO level.

UART RXFIFO threshold level

UART RXFIFO level.

UART Advanced Feature AutoBaud Rate Mode
UART Receiver TimeOut
UART Local Interconnection Network mode
UART LIN Break Detection
UART DMA Tx
UART DMA Rx
UART Half Duplex Selection
UART WakeUp Methods
UART Request Parameters
UART Advanced Feature Initialization Type
UART Advanced Feature TX Pin Active Level Inversion
UART Advanced Feature RX Pin Active Level Inversion
UART Advanced Feature Binary Data Inversion
UART Advanced Feature RX TX Pins Swap
UART Advanced Feature Overrun Disable
UART Advanced Feature Auto BaudRate Enable
UART Advanced Feature DMA Disable On Rx Error
UART Advanced Feature MSB First
UART Advanced Feature Stop Mode Enable
UART Advanced Feature Mute Mode Enable
UART Address-matching LSB Position In CR2 Register
UART WakeUp From Stop Selection
UART DriverEnable Polarity
UART Driver Enable Assertion Time LSB Position In CR1 Register
UART Driver Enable DeAssertion Time LSB Position In CR1 Register
UART Interruptions Flag Mask
UART polling-based communications time-out value
UART Status Flags

Elements values convention: 0xXXXX.

UART Interrupts Definition

Elements values convention: 000ZZZZZ0XXYYYYYb.

UART Interruption Clear Flags
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STM32H753xx HAL User Manual: UART Exported Functions

Modules
UART Exported Functions
UART

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

UART Transmit/Receive functions.

Peripheral Control functions

UART control functions.

Peripheral State and Error functions

UART Peripheral State functions.

Generated on Fri Apr 28 2017 15:42:53 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UARTEx

Modules
UARTEx
STM32H7xx_HAL_Driver

UART Extended HAL module driver. More...

Modules

UARTEx Private Functions
UARTEx Exported Functions
UARTEx Exported Types
UARTEx Exported Constants
UARTEx Private Macros

Detailed Description

UART Extended HAL module driver.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UARTEx Exported Constants

Modules
UARTEx Exported Constants
UARTEx

Modules

UART Word Length
UART Extended WakeUp Address Length
Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UARTEx Exported Functions

Modules
UARTEx Exported Functions
UARTEx

Modules

Initialization and de-initialization functions

Extended Initialization and Configuration Functions.

Peripheral Control functions

Extended Peripheral Control functions.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: UARTEx Exported Types

Data Structures
UARTEx Exported Types
UARTEx

Data Structures

struct UART_WakeUpTypeDef
UART wake up from stop mode parameters. More...
Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART

Modules
USART
STM32H7xx_HAL_Driver

HAL USART Synchronous module driver. More...

Modules

USART Private Constants
USART Exported Functions
USART Private Functions
USART Exported Types
USART Exported Constants
USART Exported Macros
USART Private Variables
USART Private Macros

Detailed Description

HAL USART Synchronous module driver.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART Exported Constants

Modules
USART Exported Constants
USART

Modules

USART Number of Stop Bits
USART Parity
USART Mode
USART Over Sampling
USART Clock
USART Clock Polarity
USART Clock Phase
USART Last Bit
USART Prescaler
USART Slave Select Management
USART Synchronous Slave mode enable
USART FIFO mode

USART FIFO mode.

USART TXFIFO threshold level

USART TXFIFO level.

USART RXFIFO threshold level

USART RXFIFO level.

USART Request Parameters
USART Flags

Elements values convention: 0xXXXX.

USART Interrupts Definition

Elements values convention: 0000ZZZZ0XXYYYYYb.

USART Interruption Clear Flags
USART Interruption Flags Mask
Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USART Exported Functions

Modules
USART Exported Functions
USART

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

USART Transmit and Receive functions.

Peripheral State and Error functions

USART Peripheral State and Error functions.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USARTEx

Modules
USARTEx
STM32H7xx_HAL_Driver

Modules

USARTEx Exported Constants
USARTEx Private Macros
Generated on Fri Apr 28 2017 15:42:55 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: USARTEx Exported Constants

Modules
USARTEx Exported Constants
USARTEx

Modules

USARTEx Word Length
Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: WWDG

Modules
WWDG
STM32H7xx_HAL_Driver

WWDG HAL module driver. More...

Modules

WWDG Exported Functions
WWDG Exported Types
WWDG Exported Constants
WWDG Private Macros
WWDG Exported Macros

Detailed Description

WWDG HAL module driver.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: WWDG Exported Constants

Modules
WWDG Exported Constants
WWDG

Modules

WWDG Interrupt definition
WWDG Flag definition

WWDG Flag definition.

WWDG Prescaler
WWDG Early Wakeup Interrupt Mode
Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: WWDG Exported Functions

Modules
WWDG Exported Functions
WWDG

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: WWDG Exported Types

Data Structures
WWDG Exported Types
WWDG

Data Structures

struct | WWDG_InitTypeDef
WWDG Init structure definition. More...
struct | WWDG_HandleTypeDef
WWDG handle Structure definition. More...
Generated on Fri Apr 28 2017 15:42:54 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: Modules

Modules
Here is a list of all modules:
  • Initialization/de-initialization functions
  • Peripheral Control functions
  • Peripheral State functions
  • STM32H7xx_HAL_Driver
    • HAL
      • HAL Exported Functions
        • Initialization and de-initialization Functions
        • HAL Control functions
      • HAL Exported Constants
        • VREFBUF Voltage Scale
        • VREFBUF High Impedance
        • Ethernet Config
        • Analog Switch Config
        • Boot Config
        • IOCompenstionCell Config
        • Event Input Config
        • SwapBankMapping Config
      • HAL Exported Macros
    • ADC
      • ADC Private Constants
      • ADC Exported Functions
        • Initialization and deinitialization functions
        • Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State functions
        • ADC Private Functions
      • ADC Private Functions
      • ADC Exported Types
        • ADC States
      • ADC Exported Constants
        • ADC Error Code
        • ADC clock source and clock prescaler
        • ADC Resolution
        • ADC sequencer scan mode
        • ADC group regular trigger source
        • ADC group regular trigger edge (when external trigger is selected)
        • ADC sequencer end of unitary conversion or sequence conversions
        • ADC overrun
        • ADC group regular sequencer rank
        • ADC Channels
        • ADC Conversion Data Management
      • ADC Private Macros
      • ADC Exported Macros
    • ADCEx
      • ADC Extended Private Constants
      • ADC Extended Exported Functions
        • Extended Input and Output operation functions
        • ADC Extended Peripheral Control functions
      • ADC Extended Exported Types
      • ADC Extended Exported Constants
        • ADC Extended External Trigger Source for Injected Group
        • ADC group injected trigger edge (when external trigger is selected)
        • ADC Extended Single-ended/Differential input mode
        • ADC Extended Offset Number
        • ADC Extended Injected Channel Rank
        • ADC Extended multimode dual mode
        • ADC Extended Dual Mode Data Formatting
        • ADC Extended delay between 2 sampling phases
        • ADC Extended Analog Watchdog Selection
        • ADC Extended Analog Watchdog Mode
        • ADC Extended Conversion Group
        • ADC Extended Event Type
        • ADC Extended Interrupts Definition
        • ADC Extended Flags Definition
        • ADC Extended Oversampling Right Shift
        • ADC Extended Oversampling left Shift
        • ADC Extended Triggered Regular Oversampling
        • ADC Extended Regular Oversampling Continued or Resumed Mode
        • ADC Sampling Times
        • ADC Extended Calibration mode offset mode or linear mode
      • ADC Extended Private Macros
    • CEC
      • CEC Private Constants
      • CEC Private Functions
      • CEC Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral Control function
      • CEC Exported Types
      • CEC Exported Constants
        • CEC Error Code
        • CEC Signal Free Time setting parameter
        • CEC Receiver Tolerance
        • CEC Reception Stop on Error
        • CEC Error Bit Generation if Bit Rise Error reported
        • CEC Error Bit Generation if Long Bit Period Error reported
        • CEC Error Bit Generation on Broadcast message
        • CEC Signal Free Time start option
        • CEC Listening mode option
        • CEC Device Own Address position in CEC CFGR register
        • CEC Initiator logical address position in message header
        • CEC Own Address
        • CEC Interrupts definition
        • CEC Flags definition
        • CEC all RX or TX errors flags
        • CEC all RX errors interrupts enabling flag
        • CEC all TX errors interrupts enabling flag
      • CEC Exported Macros
      • CEC Private Types
      • CEC Private Variables
      • CEC Private Macros
    • COMP
      • COMP Exported Functions
        • Initialization/de-initialization functions
        • Start-Stop operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • COMP Exported Types
      • COMP Exported Constants
        • COMP Window Mode
        • COMP power mode
        • COMP input plus (non-inverting input)
        • COMP input minus (inverting input)
        • COMP hysteresis
        • COMP Output Polarity
        • COMP Blanking Source
        • COMP Output Level
        • COMP output to EXTI
        • COMP Flag
        • COMP Interruption Clear Flags
        • COMP Interrupts Definitions
      • COMP Exported Macros
        • COMP Handle Management
        • COMP external interrupt line management
      • COMP Private Constants
        • COMP EXTI Lines
      • COMP Private Macros
        • COMP Private macros to get EXTI line associated with Comparators
        • COMP private macros to check input parameters
    • CORTEX
      • CORTEX Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
      • Cortex Exported Types
        • MPU Region Initialization Structure Definition
      • CORTEX Exported Constants
        • CORTEX Preemption Priority Group
        • CORTEX _SysTick clock source
        • MPU HFNMI and PRIVILEGED Access control
        • CORTEX MPU Region Enable
        • CORTEX MPU Instruction Access
        • CORTEX MPU Instruction Access Shareable
        • CORTEX MPU Instruction Access Cacheable
        • CORTEX MPU Instruction Access Bufferable
        • MPU TEX Levels
        • CORTEX MPU Region Size
        • CORTEX MPU Region Permission Attributes
        • CORTEX MPU Region Number
      • CORTEX Exported Macros
      • CORTEX_CPU_Identifier
      • CORTEX Private Macros
      • CORTEX Private Functions
    • CRC
      • CRC Exported Functions
        • Initialization/de-initialization functions
        • Peripheral Control functions
        • Peripheral State functions
      • CRC Exported Types
        • CRC State Structure definition
        • CRC Init Structure definition
        • CRC Handle Structure definition
      • CRC exported constants
        • Default CRC generating polynomial
        • Default CRC computation initialization value
        • Indicates whether or not default polynomial is used
        • Indicates whether or not default init value is used
        • Polynomial sizes to configure the IP
        • CRC polynomial possible sizes actual definitions
        • CRC input buffer format
      • CRC exported macros
      • CRC Private Types
      • CRC Private Defines
      • CRC Private Variables
      • CRC Private Constants
      • CRC Private Macros
      • CRC Private Functions Prototypes
      • CRC Private Functions
    • CRYP
      • CRYP Exported Functions
        • Initialization and de-initialization functions
        • Encrypt Decrypt functions
        • CRYP IRQ handler management
        • CRYP Private Functions
      • CRYP Exported Types
      • CRYP Exported Constants
        • CRYP Error Definition
        • CRYP Algorithm Mode
        • CRYP Key Size
        • CRYP Data Type
        • CRYP Interrupt
        • CRYP Flags
      • CRYP Exported Macros
      • CRYP Private Macros
        • CRYP Private macros to check input parameters
      • CRYP Private Constants
      • CRYP Private Defines
      • CRYP Private Variables
      • CRYP Private Functions Prototypes
      • CRYP Private Functions
      • CRYP_Private_Functions_prototypes
    • CRYPEx
      • CRYPEx Private Types
      • CRYPEx Private Variables
      • CRYPEx Private Constants
      • CRYPEx Private Macros
      • CRYPEx Private Functions
      • CRYPEx Exported Functions
        • Extended AES processing functions
      • CRYPEx_Private_Defines
    • DAC
      • DAC Exported Types
      • DAC Exported Constants
        • DAC Error Code
        • DAC trigger selection
        • DAC output buffer
        • DAC ConnectOnChipPeripheral
        • DAC User Trimming
        • . Mode is Sample and hold (low power or normal)
        • DAC Channel selection
        • DAC data alignment
        • DAC flags definition
        • DAC IT definition
      • DAC Exported Macros
      • DAC Private Macros
      • DAC Private Constants
        • DAC Private Functions
        • DAC Exported Functions
          • Initialization and de-initialization functions
          • IO operation functions
          • Peripheral Control functions
          • Peripheral State and Errors functions
      • DAC Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
    • DACEx
      • DACEx Exported Functions
        • IO operation functions
        • Peripheral Control functions
      • Peripheral Control functions
      • DACEx private functions
      • DACEx Exported Constants
        • DACEx lfsrunmask triangle amplitude
      • DACEx Private Macros
    • DCMI
      • DCMI Exported Functions
        • Initialization and Configuration functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State functions
        • DCMI Private Functions
      • DCMI Exported Types
      • DCMI Exported Constants
        • DCMI Error Code
        • DCMI Capture Mode
        • DCMI Synchronization Mode
        • DCMI PIXCK Polarity
        • DCMI VSYNC Polarity
        • DCMI HSYNC Polarity
        • DCMI MODE JPEG
        • DCMI Capture Rate
        • DCMI Extended Data Mode
        • DCMI Window Coordinate
        • DCMI Window Height
        • DCMI interrupt sources
        • DCMI Flags
        • DCMI Byte Select Mode
        • DCMI Byte Select Start
        • DCMI Line Select Mode
        • DCMI Line Select Start
      • DCMI Exported Macros
      • DCMI Private Constants
      • DCMI Private Macros
      • DCMI Private Functions
    • DFSDM
      • DFSDM Private Define
      • DFSDM Private Variables
      • DFSDM Private Functions
      • DFSDM Exported Functions
        • Channel initialization and de-initialization functions
        • Channel operation functions
        • Channel state function
        • Filter initialization and de-initialization functions
        • Filter control functions
        • Filter operation functions
        • Filter state functions
      • DFSDM Exported Types
      • DFSDM Exported Constants
        • DFSDM channel output clock selection
        • DFSDM channel input multiplexer
        • DFSDM channel input data packing
        • DFSDM channel input pins
        • DFSDM channel serial interface type
        • DFSDM channel SPI clock selection
        • DFSDM channel analog watchdog filter order
        • DFSDM filter conversion trigger
        • DFSDM filter external trigger
        • DFSDM filter external trigger edge
        • DFSDM filter sinc order
        • DFSDM filter analog watchdog data source
        • DFSDM filter error code
        • DFSDM break signals
        • DFSDM Channel Selection
        • DFSDM Continuous Mode
        • DFSDM analog watchdog threshold
      • DFSDM Exported Macros
      • DFSDM Private Macros
    • DMA
      • DMA Exported Types
      • DMA Exported Constants
        • DMA Error Code
        • DMA Request selection
        • DMA Data transfer direction
        • DMA Peripheral incremented mode
        • DMA Memory incremented mode
        • DMA Peripheral data size
        • DMA Memory data size
        • DMA mode
        • DMA Priority level
        • DMA FIFO direct mode
        • DMA FIFO threshold level
        • DMA Memory burst
        • DMA Peripheral burst
        • DMA interrupt enable definitions
        • DMA flag definitions
        • BDMA flag definitions
      • DMA Exported Macros
      • DMA Exported Functions
        • Initialization and de-initialization functions
        • I/O operation functions
        • Peripheral State functions
      • DMA Private Constants
      • DMA Private Macros
      • DMA Private Functions
    • DMA2D
      • DMA2D Private Constants
        • DMA2D Time Out
        • DMA2D Shifts
        • DMA2D Maximum Line Watermark
        • DMA2D Color Value
        • DMA2D Offset
        • DMA2D Size
        • DMA2D CLUT Size
      • DMA2D Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Error functions
      • DMA2D Private Functions
      • DMA2D Exported Types
      • DMA2D Exported Constants
        • DMA2D Error Code
        • DMA2D Mode
        • DMA2D Output Color Mode
        • DMA2D Input Color Mode
        • DMA2D Alpha Mode
        • DMA2D ALPHA Inversion
        • DMA2D Red and Blue Swap
        • DMA2D Chroma Sub Sampling
        • DMA2D CLUT Color Mode
        • DMA2D Interrupts
        • DMA2D Flags
        • DMA2D API Aliases
      • DMA2D Exported Macros
      • DMA2D Private Macros
      • DMA2D_Private_Functions_Prototypes
    • DMAEx
      • DMAEx Exported Types
      • DMA Exported Constants
        • DMAEx MUX SyncSignalID selection
        • DMAEx MUX SyncPolarity selection
        • DMAEx MUX SignalGeneratorID selection
        • DMAEx MUX RequestGeneneratorPolarity selection
      • DMAEx Exported Functions
        • Extended features functions
      • DMA Private Macros
      • DMAEx Private Functions
    • ETH
      • ETH Private Macros
      • ETH Private Functions
      • ETH Exported Functions
        • Initialization and deinitialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
      • ETH Exported Types
      • ETH Exported Constants
        • ETH DMA Tx Descriptor Bit Definition
        • ETH DMA Rx Descriptor Bit Definition
        • ETH frame settings
        • ETH Error Code
        • ETH Tx Packet Attributes
        • ETH Tx Packet Source Addr Control
        • ETH Tx Packet CRC Pad Control
        • ETH Tx Packet Checksum Control
        • ETH Tx Packet VLAN Control
        • ETH Tx Packet Inner VLAN Control
        • ETH Rx Checksum Status
        • ETH Rx IP Header Type
        • ETH Rx Payload Type
        • ETH Rx MAC Filter Status
        • ETH Rx L3 Filter Status
        • ETH Rx L4 Filter Status
        • ETH Rx Error Code
        • ETH DMA Arbitration
        • ETH Burst Mode
        • ETH Tx DMA Burst Length
        • ETH Rx DMA Burst Length
        • ETH DMA Interrupts
        • ETH DMA Status Flags
        • ETH Transmit Mode
        • ETH Receive Mode
        • ETH Pause Low Threshold
        • ETH Watchdog Timeout
        • ETH Inter Packet Gap
        • ETH Speed
        • ETH Duplex Mode
        • ETH Back Off Limit
        • ETH Preamble Length
        • ETH Source Addr Control
        • ETH Control Packets Filter
        • ETH VLAN Tag Comparison
        • ETH MAC addresses
        • ETH MAC Interrupts
        • ETH MAC Wake Up Event
        • ETH MAC Rx Tx Status
      • ETH Exported Macros
      • ETH Private Constants
    • ETHEx
      • ETHEx Private Constants
      • ETH Extended Exported Functions
        • Extended features functions
      • ETHEx Exported Types
      • ETHEx Exported Constants
        • ETHEx LPI Event
        • ETHEx L3 Filter
        • ETHEx L4 Filter
        • ETHEx L3 Protocol
        • ETHEx L3 Source Match
        • ETHEx L3 Destination Match
        • ETHEx L4 Protocol
        • ETHEx L4 Source Match
        • ETHEx L4 Destination Match
        • ETHEx Rx Inner VLAN Tag Stripping
        • ETHEx Rx VLAN Tag Stripping
        • ETHEx VLAN Type Check
        • ETHEx_VLAN_Tag_Control
        • ETHEx Tx VLAN Tag
    • FDCAN
      • FDCAN Exported Functions
        • Initialization and de-initialization functions
        • Configuration functions
        • Control functions
        • TT Configuration and control functions
        • Interrupts management
        • Callback functions
        • Peripheral State functions
      • FDCAN Exported Types
      • FDCAN Exported Constants
        • HAL FDCAN Error Code
        • FDCAN Frame Format
        • FDCAN Operating Mode
        • FDCAN Clock Divider
        • FDCAN Calibration Field Length
        • FDCAN Calibration State
        • FDCAN Calibration Counter
        • FDCAN Data Field Size
        • FDCAN Tx FIFO/Queue Mode
        • FDCAN ID Type
        • FDCAN Frame Type
        • FDCAN Data Length Code
        • FDCAN Error State Indicator
        • FDCAN Bit Rate Switching
        • FDCAN format
        • FDCAN Event FIFO control
        • FDCAN Filter Type
        • FDCAN Filter Configuration
        • FDCAN Tx Location
        • FDCAN Rx Location
        • FDCAN Event Type
        • FDCAN High Priority Message Storage
        • FDCAN protocol error code
        • FDCAN communication state
        • FDCAN FIFO watermark
        • FDCAN FIFO operation mode
        • FDCAN non-matching frames
        • FDCAN interrupt line
        • FDCAN timestamp
        • FDCAN timestamp prescaler
        • FDCAN timeout operation
        • FDCAN TT reference message payload
        • FDCAN TT repeat factor
        • FDCAN TT trigger type
        • FDCAN TT time mark event internal
        • FDCAN TT time mark event external
        • FDCAN Operation Mode
        • FDCAN TT Operation
        • FDCAN TT Time Master
        • FDCAN TT External Clock Synchronization
        • FDCAN TT Global Time Filtering
        • FDCAN TT Automatic Clock Calibration
        • FDCAN TT Event Trigger Polarity
        • FDCAN TT Basic Cycle Number
        • FDCAN TT Cycle Start Sync
        • FDCAN TT Stop Watch Trigger Selection
        • FDCAN TT Event Trigger Selection
        • FDCAN TT Stop Watch Source
        • FDCAN TT Stop Watch Polarity
        • FDCAN TT Time Mark Source
        • FDCAN TT Error Level
        • FDCAN TT Master State
        • FDCAN TT Synchronization State
        • Interrupt masks
        • FDCAN Flags
        • FDCAN Interrupts
          • FDCAN Tx Interrupts
          • FDCAN Rx Interrupts
          • FDCAN Counter Interrupts
          • Clock Calibration Interrupts
          • FDCAN Tx Event FIFO Interrupts
          • FDCAN Rx FIFO 0 Interrupts
          • FDCAN Rx FIFO 1 Interrupts
          • FDCAN Error Interrupts
        • FDCAN TT Flags
        • FDCAN TT Interrupts
          • FDCAN TT Schedule Synchronization Interrupts
          • FDCAN TT Time Mark Interrupts
          • FDCAN TT Stop Watch Interrupt
          • FDCAN TT Global Time Interrupts
          • FDCAN TT Disturbing Error Interrupts
          • FDCAN TT Fatal Error Interrupts
      • FDCAN Exported Macros
      • FDCAN Private Types
      • FDCAN Private Variables
      • FDCAN Private Constants
      • FDCAN Private Macros
      • FDCAN Private Functions Prototypes
      • FDCAN Private Functions
    • FLASH
      • FLASH Private functions
        • Programming operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
      • FLASH Exported Types
      • FLASH Exported Constants
        • FLASH Error Code
        • FLASH Type Program
        • FLASH Flag definition
        • FLASH Interrupt definition
        • FLASH Program Parallelism
        • FLASH Keys
        • FLASH Sectors
      • FLASH Exported Macros
      • FLASH Private Variables
      • FLASH Private Constants
      • FLASH Private Macros
        • FLASH Definitions
        • FLASH BANK IT Definitions
        • FLASH Address
      • FLASH_Exported_Functions
        • FLASH_Exported_Functions_Group1
        • FLASH_Exported_Functions_Group2
        • FLASH_Exported_Functions_Group3
    • FLASHEx
      • Extended FLASH Private functions
        • Extended IO operation functions
      • FLASH Exported Types
      • FLASH Exported Constants
        • FLASH Type Erase
        • FLASH Voltage Range
        • FLASH WRP State
        • FLASH Option Type
        • FLASH Option Bytes Read Protection
        • FLASH Option Bytes WWatchdog
        • FLASH Option Bytes IWatchdog
        • FLASH Option Bytes nRST_STOP
        • FLASH Option Bytes nRST_STDBY
        • FLASH IWDG Counter Freeze in STOP
        • FLASH IWDG Counter Freeze in STANDBY
        • FLASH BOR Reset Level
        • FLASH Boot Address
        • FLASH Latency
        • FLASH Banks
        • FLASHEx OB PCROP RDP
        • FLASH Option Bytes Write Protection
        • FLASHEx OB SECURITY
      • FLASHEx OB IWDG1 SW
      • FLASHEx OB NRST STOP D1
      • FLASHEx OB NRST STDBY D1
      • FLASHEx OB SWAP BANK
      • FLASHEx OB IOHSLV
      • FLASHEx OB BOOT OPTION
      • FLASHEx OB USER Type
      • FLASHEx OB SECURE RDP
      • FLASH Exported Macros
      • FLASHEx Private Macros
        • FLASHEx Private macros to check input parameters
      • FLASHEx_Private_Constants
      • FLASHEx_Exported_Functions
        • FLASHEx_Exported_Functions_Group1
    • GPIO
      • GPIO Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
      • GPIO Exported Types
      • GPIO Exported Constants
        • GPIO pins define
        • GPIO mode define
        • GPIO speed define
        • GPIO pull define
      • GPIO Exported Macros
      • GPIO Private Constants
      • GPIO Private Macros
      • GPIO Private Functions
    • HASH
      • HASH Private Constants
        • HASH Digest Calculation Status
        • HASH Number of Context Swap Registers
        • HASH TimeOut Value
      • HASH Private Functions
      • HASH Exported Functions
        • Initialization and de-initialization functions
        • HASH processing functions in polling mode
        • HASH processing functions in interrupt mode
        • HASH processing functions in DMA mode
        • HMAC processing functions in polling mode
        • HMAC processing functions in interrupt mode
        • HMAC processing functions in DMA mode
        • Peripheral states functions
      • HASH Exported Types
      • HASH Exported Constants
        • HASH algorithm selection
        • HASH algorithm mode
        • HASH input data type
        • HMAC key length type
        • HASH flags definitions
        • HASH interrupts definitions
        • HASH API alias
      • HASH Exported Macros
      • HASH Private Macros
    • HASHEx
      • HASH Extended Exported Functions
        • HASH extended processing functions in polling mode
        • HASH extended processing functions in interrupt mode
        • HASH extended processing functions in DMA mode
        • HMAC extended processing functions in polling mode
        • HMAC extended processing functions in interrupt mode
        • HMAC extended processing functions in DMA mode
        • Multi-buffer HMAC extended processing functions in DMA mode
    • HRTIM
      • HRTIM Private Define
      • HRTIM Private Variables
      • HRTIM Private Functions
      • HRTIM Exported Functions
        • Initialization and de-initialization functions
        • Simple time base mode functions
        • Simple output compare mode functions
        • Simple PWM output mode functions
        • Simple input capture functions
        • Simple one pulse functions
        • Configuration functions
        • Timer waveform configuration and functions
        • Peripheral state functions
        • Interrupts handling
      • HRTIM Exported Types
      • HRTIM Exported Constants
        • HRTIM Max Timer
        • HRTIM Timer Index
        • HRTIM Timer identifier
        • HRTIM Compare Unit
        • HRTIM Capture Unit
        • HRTIM Timer Output
        • HRTIM ADC Trigger
        • HRTIM External Event Channels
        • HRTIM Fault Channel
        • HRTIM Prescaler Ratio
        • HRTIM Mode
        • HRTIM Half Mode Enable
        • HRTIM Start On Sync Input Event
        • HRTIM Reset On Sync Input Event
        • HRTIM DAC Synchronization
        • HRTIM Register Preload Enable
        • HRTIM Update Gating
        • HRTIM Timer Burst Mode
        • HRTIM Timer Repetition Update
        • HRTIM Timer Push Pull Mode
        • HRTIM Timer Fault Enabling
        • HRTIM Timer Fault Lock
        • HRTIM Timer Deadtime Insertion
        • HRTIM Timer Delayed Protection Mode
        • HRTIM Timer Update Trigger
        • HRTIM Timer Reset Trigger
        • HRTIM Timer Reset Update
        • HRTIM Compare Unit Auto Delayed Mode
        • HRTIM Simple OC Mode
        • HRTIM Output Polarity
        • HRTIM Output Set Source
        • HRTIM Output Reset Source
        • HRTIM Output Idle Mode
        • HRTIM Output IDLE Level
        • HRTIM Output FAULT Level
        • HRTIM Output Chopper Mode Enable
        • HRTIM Output Burst Mode Entry Delayed
        • HRTIM Capture Unit Trigger
        • HRTIM Timer External Event Filter
        • HRTIM Timer External Event Latch
        • HRTIM Deadtime Prescaler Ratio
        • HRTIM Deadtime Rising Sign
        • HRTIM Deadtime Rising Lock
        • HRTIM Deadtime Rising Sign Lock
        • HRTIM Deadtime Falling Sign
        • HRTIM Deadtime Falling Lock
        • HRTIM Deadtime Falling Sign Lock
        • HRTIM Chopper Frequency
        • HRTIM Chopper Duty Cycle
        • HRTIM Chopper Start Pulse Width
        • HRTIM Synchronization Options
        • HRTIM Synchronization Input Source
        • HRTIM Synchronization Output Source
        • HRTIM Synchronization Output Polarity
        • HRTIM External Event Sources
        • HRTIM External Event Polarity
        • HRTIM External Event Sensitivity
        • HRTIM External Event Fast Mode
        • HRTIM External Event Filter
        • HRTIM External Event Prescaler
        • HRTIM Fault Sources
        • HRTIM Fault Polarity
        • HRTIM Fault Filter
        • HRTIM Fault Lock
        • HRTIM External Fault Prescaler
        • HRTIM Burst Mode Operating Mode
        • HRTIM Burst Mode Clock Source
        • HRTIM Burst Mode Prescaler
        • HRTIM Burst Mode Register Preload Enable
        • HRTIM Burst Mode Trigger
        • HRTIM ADC Trigger Update Source
        • HRTIM ADC Trigger Event
        • HRTIM Burst DMA Registers Update
        • HRTIM Burst Mode Control
        • HRTIM Fault Mode Control
        • HRTIM Software Timer Update
        • HRTIM Software Timer Reset
        • HRTIM Output Level
        • HRTIM Output State
        • HRTIM Burst Mode Status
        • HRTIM Current Push Pull Status
        • HRTIM Idle Push Pull Status
        • HRTIM Common Interrupt Enable
        • HRTIM Master Interrupt Enable
        • HRTIM Timing Unit Interrupt Enable
        • HRTIM Common Interrupt Flag
        • HRTIM Master Interrupt Flag
        • HRTIM Timing Unit Interrupt Flag
        • HRTIM Master DMA Request Enable
        • HRTIM Timing Unit DMA Request Enable
      • HRTIM Exported Macros
      • HRTIM Private Macros
    • HSEM
      • HSEM Exported Functions
        • Take and Release functions
        • HSEM Set and Get Key functions
        • HSEM IRQ handler management
      • HSEM Exported Types
      • HSEM Exported Constants
      • HSEM Exported Macros
      • HSEM Private Types
      • HSEM Private Variables
      • HSEM Private Constants
      • HSEM Private Macros
    • I2C
      • I2C Private Define
      • I2C Private Functions
      • I2C Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • IRQ Handler and Callbacks
        • Peripheral State, Mode and Error functions
      • I2C Exported Types
        • I2C Configuration Structure definition
        • HAL state structure definition
        • HAL mode structure definition
        • I2C Error Code definition
        • I2C handle Structure definition
      • I2C Exported Constants
        • I2C Sequential Transfer Options
        • I2C Addressing Mode
        • I2C Dual Addressing Mode
        • I2C Own Address2 Masks
        • I2C General Call Addressing Mode
        • I2C No-Stretch Mode
        • I2C Memory Address Size
        • I2C Transfer Direction
        • I2C Reload End Mode
        • I2C Start or Stop Mode
        • I2C Interrupt configuration definition
        • I2C Flag definition
      • I2C Exported Macros
      • I2C Private Constants
      • I2C Private Macros
    • I2CEx
      • I2C Extended Exported Functions
        • Extended features functions
          • I2C Extended Private Constants
          • I2C Extended Private Macros
          • I2C Extended Private Functions
      • I2C Extended Exported Constants
        • I2C Extended Analog Filter
        • I2C Extended Fast Mode Plus
    • I2SEx
      • I2S Extended Private Typedef
      • I2S Extended Private Functions
      • I2S Extended Exported Functions
        • I2S Extended IO operation functions
    • IRDA
      • IRDA Private Constants
      • IRDA Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Error functions
      • IRDA Private Functions
      • IRDA Exported Types
      • IRDA Exported Constants
        • IRDA Word Length
        • IRDA Parity
        • IRDA Transfer Mode
        • IRDA Low Power
        • IRDA State
        • IRDA Mode
        • IRDA One Bit Sampling
        • IRDA DMA Tx
        • IRDA DMA Rx
        • IRDA Request Parameters
        • IRDA Flags
        • IRDA Interrupts Definition
        • IRDA Interruption Clear Flags
        • IRDA interruptions flags mask
      • IRDA Exported Macros
      • IRDA Private Macros
    • JPEG
      • JPEG Exported Functions
        • Initialization and de-initialization functions
        • Configuration functions
        • encoding/decoding processing functions
        • JPEG Decode/Encode callback functions
        • JPEG IRQ handler management
        • Peripheral State functions
      • JPEG Exported Types
        • JPEG Configuration for encoding Structure definition
        • HAL JPEG state structure definition
        • JPEG handle Structure definition
      • JPEG Exported Constants
        • JPEG Error Code definition
        • JPEG Quantization Table Size
        • JPEG ColorSpace
        • JPEG Chrominance Sampling
        • JPEG Image Quality
        • JPEG Interrupt configuration definition
        • JPEG Flag definition
        • JPEG Process Pause Resume definition
      • JPEG Exported Macros
      • JPEG Private Types
      • JPEG Private Defines
      • JPEG Private Variables
      • JPEG Private Constants
      • JPEG Private Macros
      • JPEG Private Functions Prototypes
      • JPEG Private Functions
    • LPTIM
      • LPTIM Exported Functions
        • Initialization/de-initialization functions
        • LPTIM Start-Stop operation functions
        • LPTIM Read operation functions
        • LPTIM IRQ handler and callbacks
        • Peripheral State functions
      • LPTIM Exported Types
      • LPTIM Exported Constants
        • LPTIM Clock Source
        • LPTIM Clock Prescaler
        • LPTIM Output Polarity
        • LPTIM Clock Sample Time
        • LPTIM Clock Polarity
        • LPTIM Trigger Source
        • LPTIM External Trigger Polarity
        • LPTIM Trigger Sample Time
        • LPTIM Updating Mode
        • LPTIM Counter Source
        • LPTIM Input1 Source
        • LPTIM Input2 Source
        • LPTIM Flags Definition
        • LPTIM Interrupts Definition
      • LPTIM Exported Macros
      • LPTIM Private Constants
      • LPTIM Private Macros
      • LPTIM Private Functions
    • LTDC
      • LTDC Exported Functions
        • Initialization and Configuration functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
      • LTDC Exported Types
      • LTDC Exported Constants
        • LTDC Error Code
        • LTDC Layer
        • LTDC HS POLARITY
        • LTDC VS POLARITY
        • LTDC DE POLARITY
        • LTDC PC POLARITY
        • LTDC SYNC
        • LTDC BACK COLOR
        • LTDC Blending Factor1
        • LTDC Blending Factor2
        • LTDC Pixel format
        • LTDC Alpha
        • LTDC LAYER Config
        • LTDC Interrupts
        • LTDC Flags
        • LTDC Reload Type
      • LTDC Exported Macros
      • LTDC Private Types
      • LTDC Private Variables
      • LTDC Private Constants
      • LTDC Private Macros
      • LTDC Private Functions
    • MDIOS
      • MDIOS Exported Functions
        • Initialization/de-initialization functions
          • IO operation functions
          • Peripheral Control functions
        • IO operation functions
        • Peripheral Control functions
      • MDIOS Exported Types
        • MDIOS State structures definition
        • MDIOS Init Structure definition
        • MDIOS handle Structure definition
      • MDIOS Exported Constants
        • MDIOS Preamble Check
        • MDIOS Input Output Registers Definitions
        • MDIOS Registers Flags
        • Interrupt Sources
        • MDIOS Interrupt Flags
        • MDIOS Wakeup Line
      • MDIOS Exported Macros
      • MDIOS Private Types
      • MDIOS Private Variables
      • MDIOS Private Constants
      • MDIOS Private Macros
      • MDIOS Private Functions
    • MDMA
      • MDMA Exported Types
      • MDMA Exported Constants
        • MDMA Error Codes
        • MDMA Request selection
        • MDMA Transfer Trigger Mode
        • MDMA Priority level
        • MDMA Endianness
        • MDMA Source increment mode
        • MDMA Destination increment mode
        • MDMA Source data size
        • MDMA Destination data size
        • MDMA data alignment
        • MDMA Source burst
        • MDMA Destination burst
        • MDMA interrupt enable definitions
        • MDMA flag definitions
      • MDMA Exported Macros
      • MDMA Exported Functions
        • Initialization and de-initialization functions
        • Linked List operation functions
        • I/O operation functions
        • Peripheral State functions
      • MDMA Private Types
      • MDMA Private Defines
      • MDMA Private Variables
      • MDMA Private Constants
      • MDMA Private Macros
      • MDMA Private Functions Prototypes
      • MDMA Private Functions
      • JPEG Private Functions
    • MMC
      • MMC Private Functions
      • MMC Exported Types
        • MMC State enumeration structure
        • MMC Card State enumeration structure
        • MMC Handle Structure definition
        • Card Specific Data: CSD Register
        • Card Identification Data: CID Register
      • Exported Constants
        • MMC Error status enumeration Structure definition
        • MMC context enumeration
        • MMC Voltage mode
        • MMC Memory Cards
      • MMC Exported Macros
      • MMC Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral Control functions
        • MMC card related functions
        • Peripheral State and Errors functions
        • Perioheral Abort management
        • MMC Private Types
        • MMC Private Defines
        • MMC Private Variables
        • MMC Private Constants
        • MMC Private Macros
        • MMC Private Functions Prototypes
        • MMC Private Functions
      • MMC Private Defines
    • MMCEx
      • MMCEx Exported Types
        • MMC Internal DMA Buffer structure
      • MMCEx Exported Functions
        • MultiBuffer functions
    • NAND
      • NAND Exported Functions
        • Initialization and de-initialization functions
        • Input and Output functions
        • Peripheral Control functions
        • Peripheral State functions
      • NAND Exported Types
      • NAND Exported Macros
      • NAND Private Constants
      • NAND Private Macros
    • NOR
      • NOR Private Defines
      • NOR Private Variables
      • NOR Exported Functions
        • Initialization and de-initialization functions
        • Input and Output functions
        • NOR Control functions
        • NOR State functions
      • NOR Exported Types
      • NOR Exported Macros
      • NOR Private Constants
      • NOR Private Macros
    • OPAMP
      • OPAMP Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • OPAMP Exported Types
      • OPAMP Exported Constants
        • OPAMP Mode
        • OPAMP Non Inverting Input
        • OPAMP Inverting Input
        • OPAMP Pga Connect
        • OPAMP Pga Gain
        • OPAMP PowerMode
        • OPAMP VREF
        • OPAMP User Trimming
        • OPAMP Factory Trimming
      • OPAMP Private Constants
      • OPAMP Exported Macros
      • OPAMP Private Macros
    • PCD
      • PCD Private Macros
      • PCD Private Functions
      • PCD Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • PCD Exported Types
      • PCD Exported Constants
        • PCD Speed
        • PCD PHY Module
        • Turnaround Timeout Value
      • PCD Exported Macros
        • PCD Instance definition
        • PCD Exported Functions
          • Initialization and de-initialization functions
          • IO operation functions
          • Peripheral Control functions
          • Peripheral State functions
    • PCDEx
      • PCDEx Exported Functions
        • Peripheral Control functions
    • PWR
      • PWR Exported Functions
        • Initialization and De-Initialization functions
        • Peripheral Control functions
      • PWR Exported Types
      • PWR Exported Constants
        • PWR PVD detection level
        • PWR PVD Mode
        • PWR Regulator state in SLEEP/STOP mode
        • PWR SLEEP mode entry
        • PWR STOP mode entry
        • PWR Regulator Voltage Scale
        • PWR Flag
        • PWR Enable WUP Mask
      • PWR Exported Macro
      • PWR Private Constants
        • PWR PVD Mode Mask
        • PWR PVD EXTI Line
      • PWR Private Macros
        • PWR Private macros to check input parameters
    • PWREx
      • PWREx Exported Functions
        • Power supply control functions
        • Low power control functions
        • Peripherals control functions
        • Power Monitoring functions
      • PWREx Exported Types
      • PWREx Exported Constants
        • PWREx Wake-Up Pins
        • PWREx Pin Polarity configuration
        • PWREx Pin Pull configuration
        • PWREx Wakeup Pins Flags.
        • PWREx Domains definition
        • PWREx Domain Flags definition
        • PWREx D3 Domain State
        • PWREx Supply configuration
        • PWREx AVD detection level
        • PWREx AVD Mode
        • PWREx Regulator Voltage Scale
        • PWR battery charging resistor selection
        • PWREx VBAT Thresholds
        • PWREx Temperature Thresholds
        • PWREx AVD EXTI Line 16
      • PWREx Exported Macro
      • PWREx Private Macros
        • PWREx Private macros to check input parameters
      • PWREx_Private_Constants
        • PWR Extended AVD Mode Mask
        • PWR Extended Flag Setting Time Out Value
    • QSPI
      • QSPI Private Constants
      • QSPI Private Macros
      • QSPI Exported Functions
        • Initialization/de-initialization functions
        • Input and Output operation functions
        • Peripheral Control and State functions
      • QSPI Exported Types
      • QSPI Exported Constants
        • QSPI Error Code
        • QSPI Sample Shifting
        • QSPI ChipSelect High Time
        • QSPI Clock Mode
        • QSPI Flash Select
        • QSPI Dual Flash Mode
        • QSPI Address Size
        • QSPI Alternate Bytes Size
        • QSPI Instruction Mode
        • QSPI Address Mode
        • QSPI Alternate Bytes Mode
        • QSPI Data Mode
        • QSPI DDR Mode
        • QSPI DDR Data Output Delay
        • QSPI Send Instruction Mode
        • QSPI Match Mode
        • QSPI Automatic Stop
        • QSPI Timeout Activation
        • QSPI Flags
        • QSPI Interrupts
        • QSPI Timeout definition
      • QSPI Exported Macros
    • RCC
      • RCC Private Macros
        • RCC Private macros to check input parameters
      • RCC Private Variables
      • RCC Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
        • RCC_Exported_Functions_Group2
      • RCC Exported Types
      • RCC Exported Constants
        • RCC Oscillator Type
        • RCC HSE Config
        • RCC LSE Config
        • RCC HSI Config
        • RCC HSI48 Config
        • RCC LSI Config
        • RCC CSI Config
        • RCC PLL Config
        • RCC PLL Clock Source
        • RCC PLL Clock Output
        • RCC PLL1 VCI Range
        • RCC PLL1 VCO Range
        • RCC System Clock Type
        • RCC System Clock Source
        • RCC SYS Clock Source
        • RCC HCLK Clock Source
        • RCC APB3 Clock Source
        • RCC APB1 Clock Source
        • RCC APB2 Clock Source
        • RCC APB4 Clock Source
        • RCC RTC Clock Source
        • RCC MCO Index
        • RCC MCO1 Clock Source
        • RCC MCO2 Clock Source
        • RCC MCOx Clock Prescaler
        • RCC Interrupt
        • RCC Flag
        • LSE Drive Config
        • RCC Stop WakeUpClock
        • RCC Stop KernelWakeUpClock
      • RCC Exported Macros
        • LSE Configuration
        • Flags Interrupts Management
      • RCC Private Constants
    • RCCEx
      • Private Defines
      • RCCEx Private Macros
        • RCC Private macros to check input parameters
      • Exported Functions
        • Extended Peripheral Control functions
          • Extended Clock Recovery System Control functions
        • Private Functions
      • RCCEx Exported Types
      • RCCEx Exported Constants
        • RCCEx Periph Clock Selection
        • RCC PLL2 Clock Output
        • RCC PLL3 Clock Output
        • RCC PLL2 VCI Range
        • RCC PLL2 VCO Range
        • RCC PLL3 VCI Range
        • RCC PLL3 VCO Range
        • RCCEx USART1 Clock Source
        • RCCEx USART2 Clock Source
        • RCCEx USART3 Clock Source
        • RCCEx UART4 Clock Source
        • RCCEx UART5 Clock Source
        • RCCEx USART6 Clock Source
        • RCCEx UART7 Clock Source
        • RCCEx UART8 Clock Source
        • RCCEx LPUART1 Clock Source
        • RCCEx I2C1 Clock Source
        • RCCEx I2C2 Clock Source
        • RCCEx I2C3 Clock Source
        • RCCEx I2C4 Clock Source
        • RCCEx RNG Clock Source
        • RCC Extended HRTIM1 Clock Source
        • SAI1 Clock Source
        • SAI2 Clock Source
        • SPI1 Clock Source
        • SPI2 Clock Source
        • SPI3 Clock Source
        • SPI4 Clock Source
        • SPI5 Clock Source
        • SPI6 Clock Source
        • SAI3 Clock Source
        • SAI4A Clock Source
        • SAI4B Clock Source
        • RCCEx LPTIM1 Clock Source
        • RCCEx LPTIM2 Clock Source
        • RCCEx LPTIM3 Clock Source
        • RCCEx LPTIM4 Clock Source
        • RCCEx LPTIM5 Clock Source
        • RCCEx QSPI Clock Source
        • RCCEx FMC Clock Source
        • RCCEx FDCAN Clock Source
        • RCCEx SDMMC Clock Source
        • RCCEx USB Clock Source
        • RCCEx ADC Clock Source
        • RCCEx SWPMI1 Clock Source
        • RCCEx DFSDM1 Clock Source
        • RCCEx SPDIFRX Clock Source
        • RCCEx CEC Clock Source
        • RCCEx CLKP Clock Source
        • RCCEx TIM Prescaler Selection
        • RCCEx RCC WWDGx
        • RCCEx CRS Status
        • RCCEx CRS SynchroSource
        • RCCEx CRS SynchroDivider
        • RCCEx CRS SynchroPolarity
        • RCCEx CRS ReloadValueDefault
        • RCCEx CRS ErrorLimitDefault
        • RCCEx CRS HSI48CalibrationDefault
        • RCCEx CRS FreqErrorDirection
        • RCCEx CRS Interrupt Sources
        • RCCEx CRS Flags
      • RCCEx Exported Macros
        • RCC Extended HRTIMx Clock Config
        • RCCEx CRS Extended Features
      • Extended Peripheral Control functions
        • Extended Clock Recovery System Control functions
      • RCCEx_Exported_Functions_Group2
      • Extended Clock Recovery System Control functions
    • RTC
      • RTC Exported Functions
        • Initialization and de-initialization functions
        • RTC Time and Date functions
        • RTC Alarm functions
        • Peripheral Control functions
        • Peripheral State functions
      • RTC Private functions
      • RTC Exported Types
      • RTC Exported Constants
        • RTC Hour Formats
        • RTC Output Polarity Definitions
        • RTC Output Type ALARM OUT
        • RTC Output ALARM OUT Remap
        • RTC AM PM Definitions
        • RTC DayLight Saving Definitions
        • RTC Store Operation Definitions
        • RTC Input Parameter Format Definitions
        • RTC Month Date Definitions
        • RTC WeekDay Definitions
        • RTC Alarm Date WeekDay Definitions
        • RTC Alarm Mask Definitions
        • RTC Alarms Definitions
        • RTC Alarm Sub Seconds Masks Definitions
        • RTC Interrupts Definitions
        • RTC Flags Definitions
      • RTC Exported Macros
      • RTC Private Constants
      • RTC Private Macros
        • RTC Private macros to check input parameters
    • RTCEx
      • RTCEx Exported Functions
        • RTC TimeStamp and Tamper functions
        • RTC Wake-up functions
        • Extended Peripheral Control functions
        • Extended features functions
      • RTCEx Exported Types
      • RTCEx Exported Constants
        • RTC Output Selection Definitions
        • RTC Backup Registers Definitions
        • RTC TimeStamp Edges Definitions
        • RTC TimeStamp Pins Selection
        • RTC Tamper Pins Definitions
        • RTC Tamper Interrupts Definitions
        • RTC Tamper Triggers Definitions
        • RTC Tamper EraseBackUp Definitions
        • RTC Tamper Mask Flag Definitions
        • RTC Tamper Filter Definitions
        • RTC Tamper Sampling Frequencies Definitions
        • RTC Tamper Pin Precharge Duration Definitions
        • RTC Tamper TimeStamp On Tamper Detection Definitions
        • RTC Tamper Pull Up Definitions
        • RTC Wakeup Timer Definitions
        • RTC Smooth Calib Period Definitions
        • RTC Smooth Calib Plus Pulses Definitions
        • RTC Calib Output Selection Definitions
        • RTC Add 1 Second Parameter Definitions
      • RTCEx Exported Macros
      • RTCEx Private Constants
      • RTCEx Private Macros
        • Private macros to check input parameters
    • SAI
      • SAI Private Typedefs
      • SAI Private Constants
      • SAI Private Functions
      • SAI Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State functions
      • SAI Exported Types
        • SAI PDM Structure definition
        • SAI Init Structure definition
        • SAI Frame Structure definition
        • SAI Slot Structure definition
        • SAI Handle Structure definition
      • SAI Exported Constants
        • SAI Error Code
        • SAI External synchronisation
        • SAI Supported protocol
        • SAI protocol data size
        • SAI Audio Frequency
        • SAI Block Master Clock OverSampling
        • SAI PDM Clock Enable
        • SAI Block Mode
        • SAI Block Protocol
        • SAI Block Data Size
        • SAI Block MSB LSB transmission
        • SAI Block Clock Strobing
        • SAI Block Synchronization
        • SAI Block Output Drive
        • SAI Block NoDivider
        • SAI Block FS Definition
        • SAI Block FS Polarity
        • SAI Block FS Offset
        • SAI Block Slot Size
        • SAI Block Slot Active
        • SAI Mono Stereo Mode
        • SAI TRIState Management
        • SAI Block Fifo Threshold
        • SAI Block Companding Mode
        • SAI Block Mute Value
        • SAI Block Interrupts Definition
        • SAI Block Flags Definition
        • SAI Block Fifo Status Level
      • SAI Exported Macros
      • SAI_Private_Macros
    • SAIEx
      • SAIEx Extended Exported Functions
        • Peripheral Control functions
      • SAIEx Exported Types
      • SAIEx Extended Private Macros
    • SDEx
      • SDEx Exported Types
        • SD Card Internal DMA Buffer structure
      • SDEx Exported Functions
        • MultiBuffer functions
    • SDRAM
      • SDRAM Exported Functions
        • Initialization and de-initialization functions
        • Input and Output functions
        • Control functions
        • State functions
      • SDRAM Exported Types
      • SDRAM Exported Macros
    • SMARTCARD
      • SMARTCARD Private Constants
      • SMARTCARD Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • SMARTCARD Private Functions
      • SMARTCARD Exported Types
      • SMARTCARD Exported Constants
        • SMARTCARD Word Length
        • SMARTCARD Number of Stop Bits
        • SMARTCARD Parity
        • SMARTCARD Transfer Mode
        • SMARTCARD Clock Polarity
        • SMARTCARD Clock Phase
        • SMARTCARD Last Bit
        • SMARTCARD FIFO mode
        • SMARTCARD TXFIFO threshold level
        • SMARTCARD RXFIFO threshold level
        • SMARTCARD One Bit Sampling Method
        • SMARTCARD NACK Enable
        • SMARTCARD Timeout Enable
        • SMARTCARD advanced feature TX pin active level inversion
        • SMARTCARD advanced feature RX pin active level inversion
        • SMARTCARD advanced feature Binary Data inversion
        • SMARTCARD advanced feature RX TX pins swap
        • SMARTCARD advanced feature Overrun Disable
        • SMARTCARD advanced feature DMA Disable on Rx Error
        • SMARTCARD advanced feature MSB first
        • SMARTCARD Request Parameters
        • SMARTCARD auto retry counter LSB position in CR3 register
        • SMARTCARD guard time value LSB position in GTPR register
        • SMARTCARD block length LSB position in RTOR register
        • SMARTCARD interruptions flags mask
      • SMARTCARD Exported Macros
      • SMARTCARD Private Macros
    • SMARTCARDEx
      • SMARTCARD Extended Exported Functions
        • Extended Peripheral Control functions
      • SMARTCARD Extended Private Macros
      • SMARTCARD Extended Exported Constants
        • SMARTCARD Transmission Completion Indication
        • SMARTCARD advanced feature initialization type
        • SMARTCARD Flags
        • SMARTCARD Interrupts Definition
        • SMARTCARD Interruption Clear Flags
    • SMBUS
      • SMBUS Private Constants
      • SMBUS Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
          • Blocking mode Polling
          • Non-Blocking mode Interrupt
          • IRQ Handler and Callbacks
          • Peripheral State and Errors functions
        • IRQ Handler and Callbacks
        • Peripheral State and Errors functions
        • SMBUS Private Functions
      • SMBUS Exported Types
        • SMBUS Configuration Structure definition
        • HAL state definition
        • SMBUS Error Code definition
        • SMBUS handle Structure definition
      • SMBUS Exported Constants
        • SMBUS Analog Filter
        • SMBUS addressing mode
        • SMBUS dual addressing mode
        • SMBUS own address2 masks
        • SMBUS general call addressing mode
        • SMBUS nostretch mode
        • SMBUS packet error check mode
        • SMBUS peripheral mode
        • SMBUS ReloadEndMode definition
        • SMBUS StartStopMode definition
        • SMBUS XferOptions definition
        • SMBUS Interrupt configuration definition
        • SMBUS Flag definition
      • SMBUS Exported Macros
      • SMBUS Private Macros
      • SMBUS Private Functions
    • SPDIFRX
      • SPDIFRX Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • SPDIFRX Exported Types
      • SPDIFRX Exported Constants
        • SPDIFRX Error Code
        • SPDIFRX Input Selection
        • SPDIFRX Maximum Retries
        • SPDIFRX Wait For Activity
        • SPDIFRX Preamble Type Mask
        • SPDIFRX Channel Status Mask
        • SPDIFRX Validity Mask
        • SPDIFRX Parity Error Mask
        • SPDIFRX Channel Selection
        • SPDIFRX Data Format
        • SPDIFRX Stereo Mode
        • SPDIFRX State
        • SPDIFRX Interrupts Definition
        • SPDIFRX Flags Definition
      • SPDIFRX Exported Macros
      • SPDIFRX Private Macros
      • SPDIFRX Private Functions
    • SPI
      • SPI Private Constants
      • SPI Private Functions
      • SPI Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • SPI Exported Types
      • SPI Exported Constants
        • SPI FIFO Type
        • SPI Error Codes
        • SPI Mode
        • SPI Direction Mode
        • SPI Data Size
        • SPI Clock Polarity
        • SPI Clock Phase
        • SPI Slave Select Management
        • SPI NSS Pulse Mode
        • SPI BaudRate Prescaler
        • SPI MSB LSB Transmission
        • SPI TI Mode
        • SPI CRC Calculation
        • SPI CRC Length
        • SPI Fifo Threshold
        • SPI CRC Calculation Initialization Pattern
        • SPI NSS Polarity
        • Keep IO State
        • Control SPI IO Swap
        • SPI Master SS Ideleness
        • SPI Master Inter-Data Ideleness
        • SPI Master Receiver AutoSuspend
        • SPI Underrun Detection
        • SPI Underrun Behaviour
        • SPI Interrupt Definition
        • SPI Flags Definition
        • SPI Reception FIFO Status Level
      • SPI Exported Macros
      • SPI Private Macros
    • SPIEx
      • SPIEx Exported Functions
        • IO operation functions
    • SRAM
      • SRAM Exported Functions
        • Initialization and de-initialization functions
        • Input Output and memory control functions
        • Control functions
        • Peripheral State functions
      • SRAM Exported Types
      • SRAM Exported Macros
    • SWPMI
      • SWPMI Exported Functions
        • Initialization/de-initialization methods
        • IO operation methods
        • SWPMI IRQ handler and callbacks
        • Peripheral Control methods
      • SWPMI Private Functions
      • SWPMI Exported Types
      • SWPMI Exported Constants
        • SWPMI Error Code Bitmap
        • SWPMI Voltage Class
        • SWPMI Tx Buffering Mode
        • SWPMI Rx Buffering Mode
        • SWPMI Status Flags
        • SWPMI Interrupts Definition
      • SWPMI Exported Macros
      • SWPMI Private Types
      • SWPMI Private Variables
      • SWPMI Private Constants
      • SWPMI Private Macros
    • TIM
      • TIM Exported Functions
        • Time Base functions
        • Time Output Compare functions
        • Time PWM functions
        • Time Input Capture functions
        • Time One Pulse functions
        • Time Encoder functions
        • TIM IRQ handler management
        • Peripheral Control functions
        • TIM Callbacks functions
        • Peripheral State functions
      • TIM Exported Types
      • TIM Exported Constants
        • TIM Extended Event Source
        • TIM Input Channel polarity
        • TIM ETR Polarity
        • TIM ETR Prescaler
        • TIM Counter Mode
        • TIM Clock Division
        • TIM Output Compare State
        • TIM Auto-Reload Preload
        • TIM Output Fast State
        • TIM Output Compare Polarity
        • TIM Complementary Output Compare Polarity
        • TIM Output Compare Idle State
        • TIM Complementary Output Compare Idle State
        • TIM Input Capture Polarity
        • TIM Input Capture Selection
        • TIM Input Capture Prescaler
        • TIM One Pulse Mode
        • TIM Encoder Mode
        • TIM interrupt Definition
        • TIM Commutation Source
        • TIM DMA Sources
        • TIM Flag Definition
        • TIM Clock Source
        • TIM Clock Polarity
        • TIM Clock Prescaler
        • TIM Clear Input Polarity
        • TIM Clear Input Prescaler
        • TIM Off-state Selection for Run Mode
        • TIM Off-state Selection for Idle Mode
        • TIM Lock Configuration
        • TIM Break Input Enable
        • TIM Break Input Polarity
        • TIM Automatic Output Enable
        • TIM Master Mode Selection
        • TIM Master Mode Selection 2 (TRGO2)
        • TIM Master/Slave Mode
        • TIM Slave mode
        • TIM Trigger Selection
        • TIM Trigger Polarity
        • TIM Trigger Prescaler
        • TIM TI1 Input Selection
        • TIM DMA Burst Length
        • TIM DMA Handle Index
        • TIM Capture/Compare Channel State
      • TIM Exported Macros
      • TIM Private Constants
      • TIM Private Macros
      • TIM Private Functions
    • TIMEx
      • TIM Extended Exported Functions
        • Extended Timer Hall Sensor functions
        • Extended Timer Complementary Output Compare functions
        • Extended Timer Complementary PWM functions
        • Extended Timer Complementary One Pulse functions
        • Extended Peripheral Control functions
        • Extended Callbacks functions
        • Extended Peripheral State functions
      • TIM Extended Exported Types
      • TIM Extended Exported Constants
        • TIM Extended Channel
        • TIM Output Compare and PWM Modes
        • TIM Extended Clear Input Source
        • TIMEX Break input 2 Enable
        • TIM Extended Break Input 2 Polarity
        • TIM Trigger Selection
        • TIM Extended Event Source
        • TIM DMA Base Address
        • TIM Extended Remapping
        • Group Channel 5 and Channel 1, 2 or 3
          • TIM Extended Break input
          • TIM Extended Break input source
          • TIM Extended Break input source enabling
          • TIM Extended Break input polarity
      • TIM Extended Exported Macros
        • TIM Extended Private Macros
        • TIMEx Private Functions
        • TIM Extended Exported Functions
          • Extended Timer Hall Sensor functions
          • Extended Timer Complementary Output Compare functions
          • Extended Timer Complementary PWM functions
          • Extended Timer Complementary One Pulse functions
          • Extended Peripheral Control functions
          • Extended Callbacks functions
          • Extended Peripheral State functions
    • UART
      • UART Private Constants
      • UART Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Error functions
      • UART Private Functions
      • UART Exported Types
      • UART Exported Constants
        • UART Number of Stop Bits
        • UART Parity
        • UART Hardware Flow Control
        • UART Transfer Mode
        • UART State
        • UART Over Sampling
        • UART One Bit Sampling Method
        • UART Prescaler
        • UART FIFO mode
        • UART TXFIFO threshold level
        • UART RXFIFO threshold level
        • UART Advanced Feature AutoBaud Rate Mode
        • UART Receiver TimeOut
        • UART Local Interconnection Network mode
        • UART LIN Break Detection
        • UART DMA Tx
        • UART DMA Rx
        • UART Half Duplex Selection
        • UART WakeUp Methods
        • UART Request Parameters
        • UART Advanced Feature Initialization Type
        • UART Advanced Feature TX Pin Active Level Inversion
        • UART Advanced Feature RX Pin Active Level Inversion
        • UART Advanced Feature Binary Data Inversion
        • UART Advanced Feature RX TX Pins Swap
        • UART Advanced Feature Overrun Disable
        • UART Advanced Feature Auto BaudRate Enable
        • UART Advanced Feature DMA Disable On Rx Error
        • UART Advanced Feature MSB First
        • UART Advanced Feature Stop Mode Enable
        • UART Advanced Feature Mute Mode Enable
        • UART Address-matching LSB Position In CR2 Register
        • UART WakeUp From Stop Selection
        • UART DriverEnable Polarity
        • UART Driver Enable Assertion Time LSB Position In CR1 Register
        • UART Driver Enable DeAssertion Time LSB Position In CR1 Register
        • UART Interruptions Flag Mask
        • UART polling-based communications time-out value
        • UART Status Flags
        • UART Interrupts Definition
        • UART Interruption Clear Flags
      • UART Exported Macros
      • UART Private Variables
      • UART Private Macros
    • UARTEx
      • UARTEx Private Functions
      • UARTEx Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
      • UARTEx Exported Types
      • UARTEx Exported Constants
        • UART Word Length
        • UART Extended WakeUp Address Length
      • UARTEx Private Macros
    • USART
      • USART Private Constants
      • USART Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Error functions
      • USART Private Functions
      • USART Exported Types
      • USART Exported Constants
        • USART Number of Stop Bits
        • USART Parity
        • USART Mode
        • USART Over Sampling
        • USART Clock
        • USART Clock Polarity
        • USART Clock Phase
        • USART Last Bit
        • USART Prescaler
        • USART Slave Select Management
        • USART Synchronous Slave mode enable
        • USART FIFO mode
        • USART TXFIFO threshold level
        • USART RXFIFO threshold level
        • USART Request Parameters
        • USART Flags
        • USART Interrupts Definition
        • USART Interruption Clear Flags
        • USART Interruption Flags Mask
      • USART Exported Macros
      • USART Private Variables
      • USART Private Macros
    • WWDG
      • WWDG Exported Functions
        • Initialization and Configuration functions
        • IO operation functions
      • WWDG Exported Types
      • WWDG Exported Constants
        • WWDG Interrupt definition
        • WWDG Flag definition
        • WWDG Prescaler
        • WWDG Early Wakeup Interrupt Mode
      • WWDG Private Macros
      • WWDG Exported Macros
    • CRCEx
      • CRC Extended exported constants
        • CRC Extended input data inversion modes
        • CRC Extended output data inversion modes
      • CRC Extended exported macros
      • CRC Extended Exported Functions
        • Extended CRC features functions
    • GPIOEx
      • GPIO Exported Constants
        • GPIO Alternate Function Selection
      • GPIO Exported Macros
      • GPIO Exported Functions
      • GPIO Private Constants
      • GPIO Private Macros
        • GPIO Get Port Index
        • GPIO Check Alternate Function
      • GPIO Private Functions
    • HCD
      • HCD Exported Types
        • HCD State Structure definition
        • HCD Handle Structure definition
      • HCD Exported Constants
        • HCD Speed
        • HCD PHY Module
      • HCD Exported Macros
      • HCD Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • HCD Private Macros
        • HCD Instance definition
      • HCD Private Functions Prototypes
      • HCD Private Functions
    • I2S
      • I2S Exported Types
      • I2S Exported Constants
        • I2S Error Defintion
        • I2S Mode
        • I2S Standard
        • I2S Data Format
        • I2S MCLK Output
        • I2S Audio Frequency
        • I2S Clock Polarity
        • I2S MSB LSB Transmission
        • I2S Word Select Inversion
        • Control I2S IO Swap
        • Data Padding 24Bit
        • I2S Fifo Threshold
        • Keep IO State
        • Slave Extend FRE Detection
        • I2S Interrupt definition
        • I2S Flag definition
      • I2S Exported Macros
        • I2S Exported Functions
          • IO operation functions
          • Peripheral State and Errors functions
          • Initialization and de-initialization functions
          • I2S Private
      • I2S Private
      • I2S Exported Functions
        • IO operation functions
        • Peripheral State and Errors functions
        • Initialization and de-initialization functions
        • I2S Private
    • IRDAEx
      • IRDAEx Private Macros
    • IWDG
      • IWDG Private Defines
      • IWDG Exported Types
      • IWDG Exported Constants
        • IWDG Prescaler
        • IWDG Window option
      • IWDG Exported Macros
      • IWDG Exported Functions
        • Initialization and Start functions
        • IO operation functions
      • IWDG Private Constants
      • IWDG Private Macros
    • OPAMPEx
      • OPAMPEx Exported Functions
        • OPAMPEx_Exported_Functions_Group1
        • Peripheral Control functions
    • RNG
      • RNG Exported Types
        • RNG Init Structure definition
          • RNG State Structure definition
          • RNG Handle Structure definition
        • RNG Exported Constants
          • RNG Interrupt definition
          • RNG Flag definition
          • RNG Clock Error Detection
        • RNG Exported Macros
        • RNG Exported Functions
          • Initialization and de-initialization functions
          • Peripheral Control functions
          • Peripheral State functions
        • RNG Private Types
        • RNG Private Defines
        • RNG Private Variables
        • RNG Private Constants
        • RNG Private Macros
        • RNG Private Functions Prototypes
        • RNG Private Functions
      • RNG Private Constants
      • RNG Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
        • Peripheral State functions
    • SD
      • SD Private Functions
      • SD Exported Types
        • SD State enumeration structure
        • SD Card State enumeration structure
        • SD Handle Structure definition
        • Card Specific Data: CSD Register
        • Card Identification Data: CID Register
        • SD Card Status returned by ACMD13
      • Exported Constants
        • SD Error status enumeration Structure definition
        • SD context enumeration
        • SD Supported Memory Cards
        • SD Supported Version
      • SD Exported Macros
      • SD Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
          • Peripheral Control functions
        • Peripheral Control functions
        • SD card related functions
        • Peripheral State and Errors functions
        • Perioheral Abort management
        • SD Private Types
        • SD Private Defines
        • SD Private Variables
        • SD Private Constants
        • SD Private Macros
        • SD Private Functions Prototypes
        • SD Private Functions
      • SD Private Defines
    • USARTEx
      • USARTEx Exported Constants
        • USARTEx Word Length
      • USARTEx Private Macros
Generated on Fri Apr 28 2017 15:42:57 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal.c Source File

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stm32h7xx_hal.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   HAL module driver.
00008   *          This is the common part of the HAL initialization
00009   *
00010   @verbatim
00011   ==============================================================================
00012                      ##### How to use this driver #####
00013   ==============================================================================
00014     [..]
00015     The common HAL driver contains a set of generic and common APIs that can be
00016     used by the PPP peripheral drivers and the user to start using the HAL.
00017     [..]
00018     The HAL contains two APIs' categories:
00019          (+) Common HAL APIs
00020          (+) Services HAL APIs
00021
00022   @endverbatim
00023   ******************************************************************************
00024   * @attention
00025   *
00026   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00027   *
00028   * Redistribution and use in source and binary forms, with or without modification,
00029   * are permitted provided that the following conditions are met:
00030   *   1. Redistributions of source code must retain the above copyright notice,
00031   *      this list of conditions and the following disclaimer.
00032   *   2. Redistributions in binary form must reproduce the above copyright notice,
00033   *      this list of conditions and the following disclaimer in the documentation
00034   *      and/or other materials provided with the distribution.
00035   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00036   *      may be used to endorse or promote products derived from this software
00037   *      without specific prior written permission.
00038   *
00039   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00040   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00041   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00042   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00043   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00044   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00045   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00046   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00047   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00048   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00049   *
00050   ******************************************************************************
00051   */
00052
00053 /* Includes ------------------------------------------------------------------*/
00054 #include "stm32h7xx_hal.h"
00055
00056 /** @addtogroup STM32H7xx_HAL_Driver
00057   * @{
00058   */
00059
00060 /** @defgroup HAL  HAL
00061   * @brief HAL module driver.
00062   * @{
00063   */
00064
00065 /* Private typedef -----------------------------------------------------------*/
00066 /* Private define ------------------------------------------------------------*/
00067 /**
00068  * @brief STM32H7xx HAL Driver version number V1.0.0
00069    */
00070 #define __STM32H7xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
00071 #define __STM32H7xx_HAL_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
00072 #define __STM32H7xx_HAL_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
00073 #define __STM32H7xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
00074 #define __STM32H7xx_HAL_VERSION         ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
00075                                         |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\
00076                                         |(__STM32H7xx_HAL_VERSION_SUB2 << 8 )\
00077                                         |(__STM32H7xx_HAL_VERSION_RC))
00078
00079 #define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
00080 #define VREFBUF_TIMEOUT_VALUE     (uint32_t)10   /* 10 ms  */
00081
00082 /* Private macro -------------------------------------------------------------*/
00083 /* Private variables ---------------------------------------------------------*/
00084 __IO uint32_t uwTick;
00085
00086 /* Private function prototypes -----------------------------------------------*/
00087 /* Private functions ---------------------------------------------------------*/
00088
00089 /** @defgroup HAL_Exported_Functions HAL Exported Functions
00090   * @{
00091   */
00092
00093 /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
00094  *  @brief    Initialization and de-initialization functions
00095  *
00096 @verbatim
00097  ===============================================================================
00098               ##### Initialization and de-initialization functions #####
00099  ===============================================================================
00100     [..]  This section provides functions allowing to:
00101       (+) Initializes the Flash interface the NVIC allocation and initial clock
00102           configuration. It initializes the systick also when timeout is needed
00103           and the backup domain when enabled.
00104       (+) de-Initializes common part of the HAL
00105       (+) Configure The time base source to have 1ms time base with a dedicated
00106           Tick interrupt priority.
00107         (++) Systick timer is used by default as source of time base, but user
00108              can eventually implement his proper time base source (a general purpose
00109              timer for example or other time source), keeping in mind that Time base
00110              duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
00111              handled in milliseconds basis.
00112         (++) Time base configuration function (HAL_InitTick ()) is called automatically
00113              at the beginning of the program after reset by HAL_Init() or at any time
00114              when clock is configured, by HAL_RCC_ClockConfig().
00115         (++) Source of time base is configured  to generate interrupts at regular
00116              time intervals. Care must be taken if HAL_Delay() is called from a
00117              peripheral ISR process, the Tick interrupt line must have higher priority
00118             (numerically lower) than the peripheral interrupt. Otherwise the caller
00119             ISR process will be blocked.
00120        (++) functions affecting time base configurations are declared as __weak
00121              to make  override possible  in case of other  implementations in user file.
00122 @endverbatim
00123   * @{
00124   */
00125
00126 /**
00127   * @brief  This function is used to initialize the HAL Library; it must be the first
00128   *         instruction to be executed in the main program (before to call any other
00129   *         HAL function), it performs the following:
00130   *           Configures the SysTick to generate an interrupt each 1 millisecond,
00131   *           which is clocked by the HSI (at this stage, the clock is not yet
00132   *           configured and thus the system is running from the internal HSI at 16 MHz).
00133   *           Set NVIC Group Priority to 4.
00134   *           Calls the HAL_MspInit() callback function defined in user file
00135   *           "stm32h7xx_hal_msp.c" to do the global low level hardware initialization
00136   *
00137   * @note   SysTick is used as time base for the HAL_Delay() function, the application
00138   *         need to ensure that the SysTick time base is always set to 1 millisecond
00139   *         to have correct HAL operation.
00140   * @retval HAL status
00141   */
00142 HAL_StatusTypeDef HAL_Init(void)
00143 {
00144
00145   /* Set Interrupt Group Priority */
00146   HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
00147
00148   /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
00149    HAL_InitTick(TICK_INT_PRIORITY);
00150
00151   /* Init the low level hardware */
00152   HAL_MspInit();
00153
00154   /* Return function status */
00155   return HAL_OK;
00156 }
00157
00158 /**
00159   * @brief  This function de-Initializes common part of the HAL and stops the systick.
00160   *         This function is optional.
00161   * @retval HAL status
00162   */
00163 HAL_StatusTypeDef HAL_DeInit(void)
00164 {
00165   /* Reset of all peripherals */
00166   __HAL_RCC_AHB3_FORCE_RESET();
00167   __HAL_RCC_AHB3_RELEASE_RESET();
00168
00169   __HAL_RCC_AHB1_FORCE_RESET();
00170   __HAL_RCC_AHB1_RELEASE_RESET();
00171
00172   __HAL_RCC_AHB2_FORCE_RESET();
00173   __HAL_RCC_AHB2_RELEASE_RESET();
00174
00175   __HAL_RCC_AHB4_FORCE_RESET();
00176  __HAL_RCC_AHB4_RELEASE_RESET();
00177
00178   __HAL_RCC_APB3_FORCE_RESET();
00179   __HAL_RCC_APB3_RELEASE_RESET();
00180
00181   __HAL_RCC_APB1L_FORCE_RESET();
00182   __HAL_RCC_APB1L_RELEASE_RESET();
00183
00184   __HAL_RCC_APB1H_FORCE_RESET();
00185   __HAL_RCC_APB1H_RELEASE_RESET();
00186
00187    __HAL_RCC_APB2_FORCE_RESET();
00188    __HAL_RCC_APB2_RELEASE_RESET();
00189
00190   __HAL_RCC_APB4_FORCE_RESET();
00191   __HAL_RCC_APB4_RELEASE_RESET();
00192
00193   /* De-Init the low level hardware */
00194   HAL_MspDeInit();
00195
00196   /* Return function status */
00197   return HAL_OK;
00198 }
00199
00200 /**
00201   * @brief  Initializes the MSP.
00202   * @retval None
00203   */
00204 __weak void HAL_MspInit(void)
00205 {
00206   /* NOTE : This function Should not be modified, when the callback is needed,
00207             the HAL_MspInit could be implemented in the user file
00208    */
00209 }
00210
00211 /**
00212   * @brief  DeInitializes the MSP.
00213   * @retval None
00214   */
00215 __weak void HAL_MspDeInit(void)
00216 {
00217   /* NOTE : This function Should not be modified, when the callback is needed,
00218             the HAL_MspDeInit could be implemented in the user file
00219    */
00220 }
00221
00222 /**
00223   * @brief This function configures the source of the time base.
00224   *        The time source is configured  to have 1ms time base with a dedicated
00225   *        Tick interrupt priority.
00226   * @note This function is called  automatically at the beginning of program after
00227   *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
00228   * @note In the default implementation, SysTick timer is the source of time base.
00229   *       It is used to generate interrupts at regular time intervals.
00230   *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
00231   *       The the SysTick interrupt must have higher priority (numerically lower)
00232   *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
00233   *       The function is declared as __weak  to be overwritten  in case of other
00234   *       implementation  in user file.
00235   * @param TickPriority: Tick interrupt priority.
00236   * @retval HAL status
00237   */
00238 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
00239 {
00240   /*Configure the SysTick to have interrupt in 1ms time basis*/
00241   HAL_SYSTICK_Config(SystemCoreClock/1000);
00242
00243   /*Configure the SysTick IRQ priority */
00244   HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
00245
00246   /* Return function status */
00247   return HAL_OK;
00248 }
00249
00250 /**
00251   * @}
00252   */
00253
00254 /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
00255  *  @brief    HAL Control functions
00256  *
00257 @verbatim
00258  ===============================================================================
00259                       ##### HAL Control functions #####
00260  ===============================================================================
00261     [..]  This section provides functions allowing to:
00262       (+) Provide a tick value in millisecond
00263       (+) Provide a blocking delay in millisecond
00264       (+) Suspend the time base source interrupt
00265       (+) Resume the time base source interrupt
00266       (+) Get the HAL API driver version
00267       (+) Get the device identifier
00268       (+) Get the device revision identifier
00269       (+) Enable/Disable Debug module during SLEEP mode
00270       (+) Enable/Disable Debug module during STOP mode
00271       (+) Enable/Disable Debug module during STANDBY mode
00272
00273 @endverbatim
00274   * @{
00275   */
00276
00277 /**
00278   * @brief This function is called to increment  a global variable "uwTick"
00279   *        used as application time base.
00280   * @note In the default implementation, this variable is incremented each 1ms
00281   *       in Systick ISR.
00282  * @note This function is declared as __weak to be overwritten in case of other
00283   *      implementations in user file.
00284   * @retval None
00285   */
00286 __weak void HAL_IncTick(void)
00287 {
00288   uwTick++;
00289 }
00290
00291 /**
00292   * @brief Provides a tick value in millisecond.
00293   * @note This function is declared as __weak to be overwritten in case of other
00294   *       implementations in user file.
00295   * @retval tick value
00296   */
00297 __weak uint32_t HAL_GetTick(void)
00298 {
00299   return uwTick;
00300 }
00301
00302 /**
00303   * @brief This function provides accurate delay (in milliseconds) based
00304   *        on variable incremented.
00305   * @note In the default implementation , SysTick timer is the source of time base.
00306   *       It is used to generate interrupts at regular time intervals where uwTick
00307   *       is incremented.
00308   * @note ThiS function is declared as __weak to be overwritten in case of other
00309   *       implementations in user file.
00310   * @param Delay: specifies the delay time length, in milliseconds.
00311   * @retval None
00312   */
00313 __weak void HAL_Delay(__IO uint32_t Delay)
00314 {
00315   uint32_t tickstart = 0;
00316   tickstart = HAL_GetTick();
00317   while((HAL_GetTick() - tickstart) < Delay)
00318   {
00319   }
00320 }
00321
00322 /**
00323   * @brief Suspend Tick increment.
00324   * @note In the default implementation , SysTick timer is the source of time base. It is
00325   *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
00326   *       is called, the the SysTick interrupt will be disabled and so Tick increment
00327   *       is suspended.
00328   * @note This function is declared as __weak to be overwritten in case of other
00329   *       implementations in user file.
00330   * @retval None
00331   */
00332 __weak void HAL_SuspendTick(void)
00333 {
00334   /* Disable SysTick Interrupt */
00335   SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
00336 }
00337
00338 /**
00339   * @brief Resume Tick increment.
00340   * @note In the default implementation , SysTick timer is the source of time base. It is
00341   *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
00342   *       is called, the the SysTick interrupt will be enabled and so Tick increment
00343   *       is resumed.
00344   * @note This function is declared as __weak to be overwritten in case of other
00345   *       implementations in user file.
00346   * @retval None
00347   */
00348 __weak void HAL_ResumeTick(void)
00349 {
00350   /* Enable SysTick Interrupt */
00351   SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
00352 }
00353
00354 /**
00355   * @brief  Returns the HAL revision
00356   * @retval version : 0xXYZR (8bits for each decimal, R for RC)
00357   */
00358 uint32_t HAL_GetHalVersion(void)
00359 {
00360  return __STM32H7xx_HAL_VERSION;
00361 }
00362
00363 /**
00364   * @brief  Returns the device revision identifier.
00365   * @retval Device revision identifier
00366   */
00367 uint32_t HAL_GetREVID(void)
00368 {
00369    return((DBGMCU->IDCODE) >> 16);
00370 }
00371
00372 /**
00373   * @brief  Returns the device identifier.
00374   * @retval Device identifier
00375   */
00376 uint32_t HAL_GetDEVID(void)
00377 {
00378    return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
00379 }
00380
00381 /**
00382   * @brief Configure the internal voltage reference buffer voltage scale.
00383   * @param VoltageScaling  specifies the output voltage to achieve
00384   *          This parameter can be one of the following values:
00385   *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V.
00386   *                                                This requires VDDA equal to or higher than 2.4 V.
00387   *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V.
00388   *                                                This requires VDDA equal to or higher than 2.8 V.
00389   *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.5 V.
00390   *                                                This requires VDDA equal to or higher than 1.8 V.
00391   *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.8 V.
00392   *                                                This requires VDDA equal to or higher than 2.1 V.
00393   * @retval None
00394   */
00395 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
00396 {
00397   /* Check the parameters */
00398   assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
00399
00400   MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
00401 }
00402
00403 /**
00404   * @brief Configure the internal voltage reference buffer high impedance mode.
00405   * @param Mode  specifies the high impedance mode
00406   *          This parameter can be one of the following values:
00407   *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
00408   *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
00409   * @retval None
00410   */
00411 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
00412 {
00413   /* Check the parameters */
00414   assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
00415
00416   MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
00417 }
00418
00419 /**
00420   * @brief  Tune the Internal Voltage Reference buffer (VREFBUF).
00421   * @retval None
00422   */
00423 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
00424 {
00425   /* Check the parameters */
00426   assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
00427
00428   MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
00429 }
00430
00431 /**
00432   * @brief  Enable the Internal Voltage Reference buffer (VREFBUF).
00433   * @retval HAL_OK/HAL_TIMEOUT
00434   */
00435 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
00436 {
00437   uint32_t  tickstart = 0;
00438
00439   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
00440
00441   /* Get Start Tick*/
00442   tickstart = HAL_GetTick();
00443
00444   /* Wait for VRR bit  */
00445   while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == RESET)
00446   {
00447     if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
00448     {
00449       return HAL_TIMEOUT;
00450     }
00451   }
00452
00453   return HAL_OK;
00454 }
00455
00456 /**
00457   * @brief  Disable the Internal Voltage Reference buffer (VREFBUF).
00458   *
00459   * @retval None
00460   */
00461 void HAL_SYSCFG_DisableVREFBUF(void)
00462 {
00463   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
00464 }
00465
00466 /**
00467   * @brief  Ethernet PHY Interface Selection either MII or RMII
00468   * @param  SYSCFG_ETHInterface: Selects the Ethernet PHY interface
00469   *   This parameter can be one of the following values:
00470   *   @arg SYSCFG_ETH_MII : Select the Media Independent Interface
00471   *   @arg SYSCFG_ETH_RMII: Select the Reduced Media Independent Interface
00472   * @retval None
00473   */
00474 void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface)
00475 {
00476   /* Check the parameter */
00477   assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface));
00478
00479   MODIFY_REG(SYSCFG->PMCR, SYCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface));
00480 }
00481
00482
00483 /**
00484   * @brief  Analog Switch control for dual analog pads.
00485   * @param  SYSCFG_AnalogSwitch: Selects the analog pad
00486   *   This parameter can be one or a combination of the following values:
00487   *   @arg SYSCFG_SWITCH_PA0 : Select PA0 analog switch
00488   *   @arg SYSCFG_SWITCH_PA1:  Select PA1 analog switch
00489   *   @arg SYSCFG_SWITCH_PC2 : Select PC2 analog switch
00490   *   @arg SYSCFG_SWITCH_PC3:  Select PC3 analog switch
00491   * @param  SYSCFG_SwitchState: Open or Close the analog switch between dual pads (PXn and PXn_C)
00492   *   This parameter can be one or a combination of the following values:
00493   *   @arg SYSCFG_SWITCH_PA0_OPEN
00494   *   @arg SYSCFG_SWITCH_PA0_CLOSE
00495   *   @arg SYSCFG_SWITCH_PA1_OPEN
00496   *   @arg SYSCFG_SWITCH_PA1_CLOSE
00497   *   @arg SYSCFG_SWITCH_PC2_OPEN
00498   *   @arg SYSCFG_SWITCH_PC2_CLOSE
00499   *   @arg SYSCFG_SWITCH_PC3_OPEN
00500   *   @arg SYSCFG_SWITCH_PC3_CLOSE
00501   * @retval None
00502   */
00503
00504 void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState )
00505 {
00506   /* Check the parameter */
00507   assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch));
00508   assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState));
00509
00510   MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState));
00511 }
00512
00513
00514 /**
00515   * @brief  Enables the booster to reduce the total harmonic distortion of the analog
00516   *         switch when the supply voltage is lower than 2.7 V.
00517   * @note   Activating the booster allows to guaranty the analog switch AC performance
00518   *         when the supply voltage is below 2.7 V: in this case, the analog switch
00519   *         performance is the same on the full voltage range
00520   * @retval None
00521   */
00522 void HAL_SYSCFG_EnableBOOST(void)
00523 {
00524  SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
00525 }
00526
00527 /**
00528   * @brief  Disables the booster
00529   * @note   Activating the booster allows to guaranty the analog switch AC performance
00530   *         when the supply voltage is below 2.7 V: in this case, the analog switch
00531   *         performance is the same on the full voltage range
00532   * @retval None
00533   */
00534 void HAL_SYSCFG_DisableBOOST(void)
00535 {
00536  CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
00537 }
00538
00539
00540 /**
00541   * @brief  BootCM7 address 0 configuration
00542   * @param  BootRegister :Specifies the Boot Address register (Address0 or Address1)
00543   *   This parameter can be one of the following values:
00544   *   @arg SYSCFG_BOOT_ADDR0 : Select the boot address0
00545   *   @arg SYSCFG_BOOT_ADDR1:  Select the boot address1
00546   * @param  BootAddress :Specifies the CM7 Boot Address to be loaded in Address0 or Address1
00547   * @retval None
00548   */
00549 void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
00550 {
00551   /* Check the parameters */
00552   assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister));
00553   assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress));
00554   if ( BootRegister == SYSCFG_BOOT_ADDR0 )
00555   {
00556     /* Configure CM7 BOOT ADD0 */
00557     MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((BootAddress >> 16) << POSITION_VAL(SYSCFG_UR2_BOOT_ADD0)));
00558   }
00559   else
00560   {
00561     /* Configure CM7 BOOT ADD1 */
00562     MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, (BootAddress >> 16));
00563   }
00564
00565 }
00566
00567
00568 /**
00569   * @brief  Enables the I/O Compensation Cell.
00570   * @note   The I/O compensation cell can be used only when the device supply
00571   *         voltage ranges from 2.4 to 3.6 V.
00572   * @retval None
00573   */
00574 void HAL_EnableCompensationCell(void)
00575 {
00576   SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) ;
00577 }
00578
00579 /**
00580   * @brief  Power-down the I/O Compensation Cell.
00581   * @note   The I/O compensation cell can be used only when the device supply
00582   *         voltage ranges from 2.4 to 3.6 V.
00583   * @retval None
00584   */
00585 void HAL_DisableCompensationCell(void)
00586 {
00587   CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) ;
00588 }
00589
00590
00591 /**
00592   * @brief  To Enable optimize the I/O speed when the product voltage is low.
00593   * @note   This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
00594   *         used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
00595   *         higher than 2.5 V might be destructive.
00596   * @retval None
00597   */
00598 void HAL_SYSCFG_EnableIOSpeedOptimize(void)
00599 {
00600    SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) ;
00601 }
00602
00603 /**
00604   * @brief  To Disable optimize the I/O speed when the product voltage is low.
00605   * @note   This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
00606   *         used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
00607   *         higher than 2.5 V might be destructive.
00608   * @retval None
00609   */
00610 void HAL_SYSCFG_DisableIOSpeedOptimize(void)
00611 {
00612   CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) ;
00613 }
00614
00615 /**
00616   * @brief  Code selection for the I/O Compensation cell
00617   * @param  SYSCFG_CompCode: Selects the code to be applied for the I/O compensation cell
00618   *   This parameter can be one of the following values:
00619   *   @arg SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
00620   *   @arg SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
00621   * @retval None
00622   */
00623 void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode)
00624 {
00625   /* Check the parameter */
00626   assert_param(IS_SYSCFG_CODE_SELECT(SYSCFG_CompCode));
00627   MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS, (uint32_t)(SYSCFG_CompCode));
00628 }
00629
00630 /**
00631   * @brief  Code selection for the I/O Compensation cell
00632   * @param  SYSCFG_PMOSCode: PMOS compensation code
00633   *         This code is applied to the I/O compensation cell when the CS bit of the
00634   *          SYSCFG_CMPCR is set
00635   * @param  SYSCFG_NMOSCode: NMOS compensation code
00636   *         This code is applied to the I/O compensation cell when the CS bit of the
00637   *          SYSCFG_CMPCR is set
00638   * @retval None
00639   */
00640 void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
00641 {
00642   /* Check the parameter */
00643   assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
00644   assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
00645   MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC|SYSCFG_CCCR_PCC, (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
00646 }
00647
00648
00649 /**
00650   * @brief  Enable the Debug Module during Domain1 SLEEP mode
00651   * @retval None
00652   */
00653 void HAL_EnableDBGSleepMode(void)
00654 {
00655   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
00656 }
00657
00658 /**
00659   * @brief  Disable the Debug Module during Domain1 SLEEP mode
00660   * @retval None
00661   */
00662 void HAL_DisableDBGSleepMode(void)
00663 {
00664   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
00665 }
00666
00667 /**
00668   * @brief  Enable the Debug Module during Domain1 STOP mode
00669   * @retval None
00670   */
00671 void HAL_EnableDBGStopMode(void)
00672 {
00673   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
00674 }
00675
00676 /**
00677   * @brief  Disable the Debug Module during Domain1 STOP mode
00678   * @retval None
00679   */
00680 void HAL_DisableDBGStopMode(void)
00681 {
00682   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
00683 }
00684
00685 /**
00686   * @brief  Enable the Debug Module during Domain1 STANDBY mode
00687   * @retval None
00688   */
00689 void HAL_EnableDBGStandbyMode(void)
00690 {
00691   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
00692 }
00693
00694 /**
00695   * @brief  Disable the Debug Module during Domain1 STANDBY mode
00696   * @retval None
00697   */
00698 void HAL_DisableDBGStandbyMode(void)
00699 {
00700   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
00701 }
00702
00703 /**
00704   * @brief  Enable the Debug Module during Domain3 STOP mode
00705   * @retval None
00706   */
00707 void HAL_EnableDomain3DBGStopMode(void)
00708 {
00709   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
00710 }
00711
00712 /**
00713   * @brief  Disable the Debug Module during Domain3 STOP mode
00714   * @retval None
00715   */
00716 void HAL_DisableDomain3DBGStopMode(void)
00717 {
00718   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
00719 }
00720
00721 /**
00722   * @brief  Enable the Debug Module during Domain3 STANDBY mode
00723   * @retval None
00724   */
00725 void HAL_EnableDomain3DBGStandbyMode(void)
00726 {
00727   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
00728 }
00729
00730 /**
00731   * @brief  Disable the Debug Module during Domain3 STANDBY mode
00732   * @retval None
00733   */
00734 void HAL_DisableDomain3DBGStandbyMode(void)
00735 {
00736   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
00737 }
00738
00739 /**
00740   * @brief  Set the FMC Memory Mapping Swapping config.
00741   * @param  BankMapConfig: Defines the FMC Bank mapping configuration. This parameter can be
00742             FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
00743   * @retval HAL state
00744   */
00745 void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig)
00746 {
00747   /* Check the parameter */
00748   assert_param(IS_FMC_SWAPBMAP_MODE(BankMapConfig));
00749   MODIFY_REG(FMC_Bank1->BTCR[0], FMC_BCR1_BMAP, BankMapConfig);
00750 }
00751
00752 /**
00753   * @brief  Get FMC Bank mapping mode.
00754   * @retval The FMC Bank mapping mode. This parameter can be
00755             FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
00756 */
00757 uint32_t HAL_GetFMCMemorySwappingConfig(void)
00758 {
00759   return READ_BIT(FMC_Bank1->BTCR[0], FMC_BCR1_BMAP);
00760 }
00761
00762 /**
00763   * @brief  Configure the EXTI input event line edge
00764   * @note    No edge configuration for direct lines but for configurable lines:(EXTI_LINE0..EXTI_LINE21),
00765   *          EXTI_LINE49,EXTI_LINE51,EXTI_LINE85 and EXTI_LINE86.
00766   * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
00767   *         (EXTI_LINE0....EXTI_LINE87)excluding :line45,line46 and line77 to line84 which are reserved
00768   * @param   EXTI_Edge: Specifies  EXTI line Edge used.
00769   *          This parameter can be one of the following values :
00770   *   @arg EXTI_RISING_EDGE : Configurable line, with Rising edge trigger detection
00771   *   @arg EXTI_FALLING_EDGE: Configurable line, with Falling edge trigger detection
00772   * @retval None
00773   */
00774 void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge )
00775 {
00776   /* Check the parameter */
00777     assert_param(IS_EXTI_CONFIG_LINE(EXTI_Line));
00778     assert_param(IS_EXTI_EDGE_LINE(EXTI_Edge));
00779
00780     /* Clear Rising Falling edge configuration */
00781     CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20)), (uint32_t)(1 << (EXTI_Line & 0x1F)));
00782     CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20)), (uint32_t)(1 << (EXTI_Line & 0x1F)));
00783
00784      if( (EXTI_Edge & EXTI_RISING_EDGE) == EXTI_RISING_EDGE)
00785         {
00786          SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20)), (uint32_t)(1 << (EXTI_Line & 0x1F)));
00787         }
00788       if( (EXTI_Edge & EXTI_FALLING_EDGE) == EXTI_FALLING_EDGE)
00789         {
00790          SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20)), (uint32_t)(1 << (EXTI_Line & 0x1F)));
00791         }
00792 }
00793
00794 /**
00795   * @brief  Generates a Software interrupt on selected EXTI line.
00796   * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
00797   *          (EXTI_LINE0..EXTI_LINE21),EXTI_LINE49,EXTI_LINE51,EXTI_LINE85 and EXTI_LINE86.
00798   * @retval None
00799   */
00800 void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
00801 {
00802   /* Check the parameters */
00803   assert_param(IS_EXTI_CONFIG_LINE(EXTI_Line));
00804
00805   SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER1)) + ((EXTI_Line >> 5 ) * 0x20)), (uint32_t)(1 << (EXTI_Line & 0x1F)));
00806 }
00807
00808
00809 /**
00810   * @brief  Clears the EXTI's line pending flags for Domain D1
00811   * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
00812   *         (EXTI_LINE0....EXTI_LINE87)excluding :line45,line46 and line77 to line84 which are reserved
00813   * @retval None
00814   */
00815 void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line)
00816 {
00817   /* Check the parameters */
00818  assert_param(IS_EXTI_D1_LINE(EXTI_Line));
00819  SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->PR1)) + ((EXTI_Line >> 5 ) * 0x10)), (uint32_t)(1 << (EXTI_Line & 0x1F)));
00820
00821 }
00822
00823 /**
00824   * @brief  Configure the EXTI input event line for Domain D1
00825   * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
00826   *         (EXTI_LINE0 to EXTI_LINE87)excluding :line45,line46 and line77 to line84 which are reserved
00827   * @param   EXTI_Mode: Specifies which EXTI line is used as interrupt or an event.
00828   *          This parameter can be one or a combination of the following values :
00829   *   @arg EXTI_MODE_IT :  Interrupt Mode selected
00830   *   @arg EXTI_MODE_EVT : Event Mode selected
00831   * @param   EXTI_LineCmd controls (Enable/Disable) the EXTI line.
00832
00833   * @retval None
00834   */
00835 void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd )
00836 {
00837   /* Check the parameter */
00838     assert_param(IS_EXTI_D1_LINE(EXTI_Line));
00839     assert_param(IS_EXTI_MODE_LINE(EXTI_Mode));
00840
00841   if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT)
00842       {
00843          if( EXTI_LineCmd == DISABLE)
00844            {
00845            /* Clear EXTI line configuration */
00846             CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10)),(uint32_t)(1 << (EXTI_Line & 0x1F)) );
00847            }
00848          else
00849            {
00850             SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10)), (uint32_t)(1 << (EXTI_Line & 0x1F)));
00851            }
00852      }
00853  if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT)
00854       {
00855           if( EXTI_LineCmd == DISABLE)
00856            {
00857              /* Clear EXTI line configuration */
00858              CLEAR_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10)), (uint32_t)(1 << (EXTI_Line & 0x1F)));
00859            }
00860            else
00861            {
00862             SET_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10)), (uint32_t)(1 << (EXTI_Line & 0x1F)));
00863            }
00864       }
00865
00866 }
00867
00868
00869 /**
00870   * @brief  Configure the EXTI input event line for Domain D3
00871   * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
00872   *         (EXTI_LINE0 to EXTI_LINE15),(EXTI_LINE19 to EXTI_LINE21),EXTI_LINE25, EXTI_LINE34,
00873   *          EXTI_LINE35,EXTI_LINE41,(EXTI_LINE48 to EXTI_LINE53)
00874   * @param   EXTI_LineCmd controls (Enable/Disable) the EXTI line.
00875   * @param   EXTI_ClearSrc: Specifies the clear source of D3 pending event.
00876   *          This parameter can be one of the following values :
00877   *   @arg BDMA_CH6_CLEAR : BDMA ch6 event selected as D3 domain pendclear source
00878   *   @arg BDMA_CH7_CLEAR : BDMA ch7 event selected as D3 domain pendclear source
00879   *   @arg LPTIM4_OUT_CLEAR : LPTIM4 out selected as D3 domain pendclear source
00880   *   @arg LPTIM5_OUT_CLEAR : LPTIM5 out selected as D3 domain pendclear source
00881   * @retval None
00882   */
00883 void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc  )
00884 {
00885
00886  /* Check the parameter */
00887     assert_param(IS_EXTI_D3_LINE(EXTI_Line));
00888     assert_param(IS_EXTI_D3_CLEAR(EXTI_ClearSrc));
00889
00890     if( EXTI_LineCmd == DISABLE)
00891       {
00892       /* Clear EXTI line configuration */
00893        CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) + ((EXTI_Line >> 5 ) * 0x20)),(uint32_t)(1 << (EXTI_Line & 0x1F)) );
00894       }
00895    else
00896      {
00897        SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) +((EXTI_Line >> 5 ) * 0x20)), (uint32_t)(1 << (EXTI_Line & 0x1F)));
00898      }
00899
00900
00901     if ( (EXTI_Line>>4)%2 ==0)
00902     {
00903      MODIFY_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1L)) + ((EXTI_Line >> 5 ) * 0x20)), \
00904     (uint32_t)(3 << ((EXTI_Line*2) & 0x1F)), (uint32_t)(EXTI_ClearSrc << ((EXTI_Line*2) & 0x1F))) ;
00905     }
00906
00907     else
00908       {
00909       MODIFY_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1H)) + ((EXTI_Line >> 5 ) * 0x20)), \
00910      (uint32_t)(3 << ((EXTI_Line*2) & 0x1F)), (uint32_t)(EXTI_ClearSrc << ((EXTI_Line*2) & 0x1F))) ;
00911       }
00912
00913 }
00914
00915
00916
00917 /**
00918   * @}
00919   */
00920
00921 /**
00922   * @}
00923   */
00924
00925 /**
00926   * @}
00927   */
00928
00929 /**
00930   * @}
00931   */
00932
00933 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:37 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal.h Source File

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stm32h7xx_hal.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   This file contains all the functions prototypes for the HAL
00008   *          module driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00013   *
00014   * Redistribution and use in source and binary forms, with or without modification,
00015   * are permitted provided that the following conditions are met:
00016   *   1. Redistributions of source code must retain the above copyright notice,
00017   *      this list of conditions and the following disclaimer.
00018   *   2. Redistributions in binary form must reproduce the above copyright notice,
00019   *      this list of conditions and the following disclaimer in the documentation
00020   *      and/or other materials provided with the distribution.
00021   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00022   *      may be used to endorse or promote products derived from this software
00023   *      without specific prior written permission.
00024   *
00025   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00026   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00027   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00028   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00029   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00030   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00031   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00032   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00033   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00034   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00035   *
00036   ******************************************************************************
00037   */
00038
00039 /* Define to prevent recursive inclusion -------------------------------------*/
00040 #ifndef __STM32H7xx_HAL_H
00041 #define __STM32H7xx_HAL_H
00042
00043 #ifdef __cplusplus
00044  extern "C" {
00045 #endif
00046
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32h7xx_hal_conf.h"
00049
00050 /** @addtogroup STM32H7xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup HAL
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /* Exported constants --------------------------------------------------------*/
00060 /** @defgroup HAL_Exported_Constants HAL Exported Constants
00061   * @{
00062   */
00063
00064 /** @defgroup HAL_SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
00065   * @{
00066   */
00067 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0   VREFBUF_CSR_VRS_OUT2   /*!< Voltage reference scale 0 (VREF_OUT2) */
00068 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1   VREFBUF_CSR_VRS_OUT1   /*!< Voltage reference scale 1 (VREF_OUT1) */
00069 #define SYSCFG_VREFBUF_VOLTAGE_SCALE2   VREFBUF_CSR_VRS_OUT4   /*!< Voltage reference scale 2 (VREF_OUT4) */
00070 #define SYSCFG_VREFBUF_VOLTAGE_SCALE3   VREFBUF_CSR_VRS_OUT3   /*!< Voltage reference scale 3 (VREF_OUT3) */
00071
00072
00073 /**
00074   * @}
00075   */
00076
00077 /** @defgroup HAL_SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
00078   * @{
00079   */
00080 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
00081 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ        /*!< VREF_plus pin is high impedance */
00082
00083
00084
00085 /**
00086   * @}
00087   */
00088
00089 /** @defgroup HAL_SYSCFG_Ethernet_Config  Ethernet Config
00090   * @{
00091   */
00092 #define SYSCFG_ETH_MII                      ((uint32_t)0x00000000)  /*!< Select the Media Independent Interface */
00093 #define SYSCFG_ETH_RMII                     SYSCFG_PMCR_EPIS_SEL_2  /*!< Select the Reduced Media Independent Interface */
00094
00095
00096 /**
00097   * @}
00098   */
00099
00100
00101 /** @defgroup HAL_SYSCFG_Analog_Switch_Config  Analog Switch Config
00102   * @{
00103   */
00104 #define SYSCFG_SWITCH_PA0                       SYSCFG_PMCR_PA0SO  /*!< Select PA0 analog switch */
00105 #define SYSCFG_SWITCH_PA1                       SYSCFG_PMCR_PA1SO  /*!< Select PA1 analog switch */
00106 #define SYSCFG_SWITCH_PC2                       SYSCFG_PMCR_PC2SO  /*!< Select PC2 analog switch */
00107 #define SYSCFG_SWITCH_PC3                       SYSCFG_PMCR_PC3SO  /*!< Select PC3 analog switch */
00108
00109
00110
00111 #define SYSCFG_SWITCH_PA0_OPEN                       SYSCFG_PMCR_PA0SO       /*!< PA0 analog switch opened */
00112 #define SYSCFG_SWITCH_PA0_CLOSE                      ((uint32_t)0x00000000)  /*!< PA0 analog switch closed */
00113 #define SYSCFG_SWITCH_PA1_OPEN                       SYSCFG_PMCR_PA1SO       /*!< PA1 analog switch opened */
00114 #define SYSCFG_SWITCH_PA1_CLOSE                      ((uint32_t)0x00000000)  /*!< PA1 analog switch closed*/
00115 #define SYSCFG_SWITCH_PC2_OPEN                       SYSCFG_PMCR_PC2SO       /*!< PC2 analog switch opened */
00116 #define SYSCFG_SWITCH_PC2_CLOSE                      ((uint32_t)0x00000000)  /*!< PC2 analog switch closed */
00117 #define SYSCFG_SWITCH_PC3_OPEN                       SYSCFG_PMCR_PC3SO       /*!< PC3 analog switch opened */
00118 #define SYSCFG_SWITCH_PC3_CLOSE                      ((uint32_t)0x00000000)  /*!< PC3 analog switch closed */
00119
00120
00121 /**
00122   * @}
00123   */
00124
00125 /** @defgroup HAL_SYSCFG_Boot_Config  Boot Config
00126   * @{
00127   */
00128 #define SYSCFG_BOOT_ADDR0                    ((uint32_t)0x00000000)  /*!< Select Boot address0 */
00129 #define SYSCFG_BOOT_ADDR1                    ((uint32_t)0x00000001)  /*!< Select Boot address1 */
00130
00131
00132
00133 /**
00134   * @}
00135   */
00136
00137
00138 /** @defgroup HAL_SYSCFG_IOCompenstionCell_Config  IOCompenstionCell Config
00139   * @{
00140   */
00141 #define SYSCFG_CELL_CODE                    ((uint32_t)0x00000000)  /*!< Select Code from the cell */
00142 #define SYSCFG_REGISTER_CODE                 SYSCFG_CCCSR_CS        /*!< Code from the SYSCFG compensation cell code register */
00143
00144
00145 /**
00146   * @}
00147   */
00148
00149 /** @defgroup HAL_EXTI_Event_Input_Config  Event Input Config
00150   * @{
00151   */
00152
00153 #define EXTI_MODE_IT          ((uint32_t)0x00010000)
00154 #define EXTI_MODE_EVT         ((uint32_t)0x00020000)
00155 #define EXTI_RISING_EDGE      ((uint32_t)0x00100000)
00156 #define EXTI_FALLING_EDGE     ((uint32_t)0x00200000)
00157
00158
00159 #define EXTI_LINE0       ((uint32_t)0x00)  /*!< External interrupt LINE 0  */
00160 #define EXTI_LINE1       ((uint32_t)0x01)  /*!< External interrupt LINE 1  */
00161 #define EXTI_LINE2       ((uint32_t)0x02)  /*!< External interrupt LINE 2  */
00162 #define EXTI_LINE3       ((uint32_t)0x03)  /*!< External interrupt LINE 3  */
00163 #define EXTI_LINE4       ((uint32_t)0x04)  /*!< External interrupt LINE 4  */
00164 #define EXTI_LINE5       ((uint32_t)0x05)  /*!< External interrupt LINE 5  */
00165 #define EXTI_LINE6       ((uint32_t)0x06)  /*!< External interrupt LINE 6  */
00166 #define EXTI_LINE7       ((uint32_t)0x07)  /*!< External interrupt LINE 7  */
00167 #define EXTI_LINE8       ((uint32_t)0x08)  /*!< External interrupt LINE 8  */
00168 #define EXTI_LINE9       ((uint32_t)0x09)  /*!< External interrupt LINE 9  */
00169 #define EXTI_LINE10      ((uint32_t)0x0A)  /*!< External interrupt LINE 10 */
00170 #define EXTI_LINE11      ((uint32_t)0x0B)  /*!< External interrupt LINE 11 */
00171 #define EXTI_LINE12      ((uint32_t)0x0C)  /*!< External interrupt LINE 12 */
00172 #define EXTI_LINE13      ((uint32_t)0x0D)  /*!< External interrupt LINE 13 */
00173 #define EXTI_LINE14      ((uint32_t)0x0E)  /*!< External interrupt LINE 14 */
00174 #define EXTI_LINE15      ((uint32_t)0x0F)  /*!< External interrupt LINE 15 */
00175 #define EXTI_LINE16      ((uint32_t)0x10)
00176 #define EXTI_LINE17      ((uint32_t)0x11)
00177 #define EXTI_LINE18      ((uint32_t)0x12)
00178 #define EXTI_LINE19      ((uint32_t)0x13)
00179 #define EXTI_LINE20      ((uint32_t)0x14)
00180 #define EXTI_LINE21      ((uint32_t)0x15)
00181 #define EXTI_LINE22      ((uint32_t)0x16)
00182 #define EXTI_LINE23      ((uint32_t)0x17)
00183 #define EXTI_LINE24      ((uint32_t)0x18)
00184 #define EXTI_LINE25      ((uint32_t)0x19)
00185 #define EXTI_LINE26      ((uint32_t)0x1A)
00186 #define EXTI_LINE27      ((uint32_t)0x1B)
00187 #define EXTI_LINE28      ((uint32_t)0x1C)
00188 #define EXTI_LINE29      ((uint32_t)0x1D)
00189 #define EXTI_LINE30      ((uint32_t)0x1E)
00190 #define EXTI_LINE31      ((uint32_t)0x1F)
00191 #define EXTI_LINE32      ((uint32_t)0x20)
00192 #define EXTI_LINE33      ((uint32_t)0x21)
00193 #define EXTI_LINE34      ((uint32_t)0x22)
00194 #define EXTI_LINE35      ((uint32_t)0x23)
00195 #define EXTI_LINE36      ((uint32_t)0x24)
00196 #define EXTI_LINE37      ((uint32_t)0x25)
00197 #define EXTI_LINE38      ((uint32_t)0x26)
00198 #define EXTI_LINE39      ((uint32_t)0x27)
00199
00200 #define EXTI_LINE40      ((uint32_t)0x28)
00201 #define EXTI_LINE41      ((uint32_t)0x29)
00202 #define EXTI_LINE42      ((uint32_t)0x2A)
00203 #define EXTI_LINE43      ((uint32_t)0x2B)
00204 #define EXTI_LINE44      ((uint32_t)0x2C)
00205 /* EXTI_LINE45 Reserved */
00206 /* EXTI_LINE46 Reserved */
00207 #define EXTI_LINE47      ((uint32_t)0x2F)
00208 #define EXTI_LINE48      ((uint32_t)0x30)
00209 #define EXTI_LINE49      ((uint32_t)0x31)
00210
00211 #define EXTI_LINE50      ((uint32_t)0x32)
00212 #define EXTI_LINE51      ((uint32_t)0x33)
00213 #define EXTI_LINE52      ((uint32_t)0x34)
00214 #define EXTI_LINE53      ((uint32_t)0x35)
00215 #define EXTI_LINE54      ((uint32_t)0x36)
00216 #define EXTI_LINE55      ((uint32_t)0x37)
00217 #define EXTI_LINE56      ((uint32_t)0x38)
00218 #define EXTI_LINE57      ((uint32_t)0x39)
00219 #define EXTI_LINE58      ((uint32_t)0x3A)
00220 #define EXTI_LINE59      ((uint32_t)0x3B)
00221
00222 #define EXTI_LINE60      ((uint32_t)0x3C)
00223 #define EXTI_LINE61      ((uint32_t)0x3D)
00224 #define EXTI_LINE62      ((uint32_t)0x3E)
00225 #define EXTI_LINE63      ((uint32_t)0x3F)
00226 #define EXTI_LINE64      ((uint32_t)0x40)
00227 #define EXTI_LINE65      ((uint32_t)0x41)
00228 #define EXTI_LINE66      ((uint32_t)0x42)
00229 #define EXTI_LINE67      ((uint32_t)0x43)
00230 #define EXTI_LINE68      ((uint32_t)0x44)
00231 #define EXTI_LINE69      ((uint32_t)0x45)
00232
00233 #define EXTI_LINE70      ((uint32_t)0x46)
00234 #define EXTI_LINE71      ((uint32_t)0x47)
00235 #define EXTI_LINE72      ((uint32_t)0x48)
00236 #define EXTI_LINE73      ((uint32_t)0x49)
00237 #define EXTI_LINE74      ((uint32_t)0x4A)
00238 #define EXTI_LINE75      ((uint32_t)0x4B)
00239 #define EXTI_LINE76      ((uint32_t)0x4C)
00240
00241 /* EXTI_LINE77   Reserved */
00242 /* EXTI_LINE78   Reserved */
00243 /* EXTI_LINE79   Reserved */
00244 /* EXTI_LINE80   Reserved */
00245 /* EXTI_LINE81   Reserved */
00246 /* EXTI_LINE82   Reserved */
00247 /* EXTI_LINE83   Reserved */
00248 /* EXTI_LINE84   Reserved */
00249
00250 #define EXTI_LINE85      ((uint32_t)0x55)
00251 #define EXTI_LINE86      ((uint32_t)0x56)
00252 #define EXTI_LINE87      ((uint32_t)0x57)
00253
00254 /* EXTI_LINE88   Reserved */
00255
00256 /**
00257   * @}
00258   */
00259
00260 #define  BDMA_CH6_CLEAR             ((uint32_t)0x00000000)   /*!< BDMA ch6 event selected as D3 domain pendclear source*/
00261 #define  BDMA_CH7_CLEAR             ((uint32_t)0x00000001)   /*!< BDMA ch7 event selected as D3 domain pendclear source*/
00262 #define  LPTIM4_OUT_CLEAR           ((uint32_t)0x00000002)   /*!< LPTIM4 out selected as D3 domain pendclear source*/
00263 #define  LPTIM5_OUT_CLEAR           ((uint32_t)0x00000003)   /*!< LPTIM5 out selected as D3 domain pendclear source*/
00264
00265
00266
00267
00268
00269 /** @defgroup HAL_FMC_SwapBankMapping_Config  SwapBankMapping Config
00270   * @{
00271   */
00272 #define FMC_SWAPBMAP_DISABLE             (0x00000000U)
00273 #define FMC_SWAPBMAP_SDRAM_SRAM          FMC_BCR1_BMAP_0
00274 #define FMC_SWAPBMAP_SDRAMB2             FMC_BCR1_BMAP_1
00275
00276 /**
00277   * @}
00278   */
00279
00280 /**
00281   * @}
00282   */
00283  /* Exported macro ------------------------------------------------------------*/
00284 /** @defgroup HAL_Exported_Macros HAL Exported Macros
00285   * @{
00286   */
00287 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
00288                                                      ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
00289                                                      ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \
00290                                                      ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3))
00291
00292
00293 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
00294                                                       ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
00295
00296 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
00297
00298 #define IS_SYSCFG_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SYSCFG_ETH_MII)        || \
00299                                           ((CONFIG) == SYSCFG_ETH_RMII))
00300
00301 #define IS_SYSCFG_ANALOG_SWITCH(SWITCH)    ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \
00302                                            (((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || \
00303                                            (((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || \
00304                                            (((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3))
00305
00306 #define IS_SYSCFG_SWITCH_STATE(STATE)      ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN)    || \
00307                                            (((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE)   || \
00308                                            (((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN)     || \
00309                                            (((STATE) & SYSCFG_SWITCH_PA1_CLOSE) == SYSCFG_SWITCH_PA1_CLOSE)   || \
00310                                            (((STATE) & SYSCFG_SWITCH_PC2_OPEN) == SYSCFG_SWITCH_PC2_OPEN)     || \
00311                                            (((STATE) & SYSCFG_SWITCH_PC2_CLOSE) == SYSCFG_SWITCH_PC2_CLOSE)   || \
00312                                            (((STATE) & SYSCFG_SWITCH_PC3_OPEN) == SYSCFG_SWITCH_PC3_OPEN)     || \
00313                                            (((STATE) & SYSCFG_SWITCH_PC3_CLOSE) == SYSCFG_SWITCH_PC3_CLOSE))
00314
00315 #define IS_SYSCFG_BOOT_REGISTER(REGISTER) (((REGISTER) == SYSCFG_BOOT_ADDR0)|| \
00316                                           ((REGISTER) == SYSCFG_BOOT_ADDR1))
00317
00318 #define IS_SYSCFG_BOOT_ADDRESS(ADDRESS) ((ADDRESS) < PERIPH_BASE)
00319
00320 #define IS_SYSCFG_CODE_SELECT(SELECT) (((SELECT) == SYSCFG_CELL_CODE)|| \
00321                                         ((SELECT) == SYSCFG_REGISTER_CODE))
00322
00323 #define IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10))
00324
00325 #define IS_EXTI_EDGE_LINE(EDGE) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE))
00326 #define IS_EXTI_MODE_LINE(MODE) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT))
00327
00328 #define IS_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)|| \
00329                                 ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)   || \
00330                                 ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)   || \
00331                                 ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)   || \
00332                                 ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)   || \
00333                                 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
00334                                 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
00335                                 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
00336                                 ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
00337                                 ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
00338                                 ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
00339                                 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \
00340                                 ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))
00341
00342 #define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
00343                                 ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
00344                                 ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
00345                                 ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
00346                                 ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
00347                                 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
00348                                 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
00349                                 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
00350                                 ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
00351                                 ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
00352                                 ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
00353                                 ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
00354                                 ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
00355                                 ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
00356                                 ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
00357                                 ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
00358                                 ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
00359                                 ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
00360                                 ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
00361                                 ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
00362                                 ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
00363                                 ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
00364                                 ((LINE) == EXTI_LINE44) || \
00365                                 ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
00366                                 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
00367                                 ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
00368                                 ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
00369                                 ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
00370                                 ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
00371                                 ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
00372                                 ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
00373                                 ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
00374                                 ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
00375                                 ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
00376                                 ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
00377                                 ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
00378                                 ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
00379                                 ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
00380                                 ((LINE) == EXTI_LINE85) || \
00381                                 ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
00382
00383 #define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
00384                                 ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
00385                                 ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
00386                                 ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
00387                                 ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
00388                                 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
00389                                 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
00390                                 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
00391                                 ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
00392                                 ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
00393                                 ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
00394                                 ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
00395                                 ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
00396                                 ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
00397                                 ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
00398                                 ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
00399                                 ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
00400                                 ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
00401                                 ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
00402                                 ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
00403                                 ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
00404                                 ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
00405                                 ((LINE) == EXTI_LINE44) || \
00406                                 ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
00407                                 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
00408                                 ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
00409                                 ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
00410                                 ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
00411                                 ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
00412                                 ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
00413                                 ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
00414                                 ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
00415                                 ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
00416                                 ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
00417                                 ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
00418                                 ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
00419                                 ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
00420                                 ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
00421                                 ((LINE) == EXTI_LINE85) || \
00422                                 ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
00423
00424
00425 #define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \
00426                                 ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
00427                                 ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
00428                                 ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
00429                                 ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
00430                                 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
00431                                 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
00432                                 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
00433                                 ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
00434                                 ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
00435                                 ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
00436                                 ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
00437                                 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
00438                                 ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
00439                                 ((LINE) == EXTI_LINE53))
00440
00441 #define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR)    || \
00442                                  ((SOURCE) == LPTIM4_OUT_CLEAR) || ((SOURCE) == LPTIM5_OUT_CLEAR))
00443
00444 #define IS_FMC_SWAPBMAP_MODE(__MODE__) (((__MODE__) == FMC_SWAPBMAP_DISABLE)    || \
00445                                         ((__MODE__) == FMC_SWAPBMAP_SDRAM_SRAM) || \
00446                                         ((__MODE__) == FMC_SWAPBMAP_SDRAMB2))
00447
00448
00449 /** @brief  Freeze/Unfreeze Peripherals in Debug mode
00450   */
00451 #define __HAL_DBGMCU_FREEZE_WWDG1()          (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1))
00452
00453 #define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2))
00454 #define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3))
00455 #define __HAL_DBGMCU_FREEZE_TIM4()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4))
00456 #define __HAL_DBGMCU_FREEZE_TIM5()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5))
00457 #define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6))
00458 #define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7))
00459 #define __HAL_DBGMCU_FREEZE_TIM12()          (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12))
00460 #define __HAL_DBGMCU_FREEZE_TIM13()          (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13))
00461 #define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14))
00462 #define __HAL_DBGMCU_FREEZE_LPTIM1()         (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1))
00463 #define __HAL_DBGMCU_FREEZE_I2C1()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1))
00464 #define __HAL_DBGMCU_FREEZE_I2C2()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2))
00465 #define __HAL_DBGMCU_FREEZE_I2C3()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3))
00466 #define __HAL_DBGMCU_FREEZE_FDCAN()          (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN))
00467
00468
00469 #define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1))
00470 #define __HAL_DBGMCU_FREEZE_TIM8()           (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8))
00471 #define __HAL_DBGMCU_FREEZE_TIM15()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15))
00472 #define __HAL_DBGMCU_FREEZE_TIM16()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16))
00473 #define __HAL_DBGMCU_FREEZE_TIM17()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17))
00474 #define __HAL_DBGMCU_FREEZE_HRTIM()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM))
00475
00476 #define __HAL_DBGMCU_FREEZE_I2C4()           (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4))
00477 #define __HAL_DBGMCU_FREEZE_LPTIM2()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2))
00478 #define __HAL_DBGMCU_FREEZE_LPTIM3()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3))
00479 #define __HAL_DBGMCU_FREEZE_LPTIM4()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4))
00480 #define __HAL_DBGMCU_FREEZE_LPTIM5()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5))
00481 #define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC))
00482 #define __HAL_DBGMCU_FREEZE_IWDG1()          (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1))
00483
00484
00485 #define __HAL_DBGMCU_UnFreeze_WWDG1()          (DBGMCU->APB3FZ1  &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1))
00486
00487 #define __HAL_DBGMCU_UnFreeze_TIM2()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2))
00488 #define __HAL_DBGMCU_UnFreeze_TIM3()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3))
00489 #define __HAL_DBGMCU_UnFreeze_TIM4()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4))
00490 #define __HAL_DBGMCU_UnFreeze_TIM5()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5))
00491 #define __HAL_DBGMCU_UnFreeze_TIM6()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6))
00492 #define __HAL_DBGMCU_UnFreeze_TIM7()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7))
00493 #define __HAL_DBGMCU_UnFreeze_TIM12()          (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12))
00494 #define __HAL_DBGMCU_UnFreeze_TIM13()          (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13))
00495 #define __HAL_DBGMCU_UnFreeze_TIM14()          (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14))
00496 #define __HAL_DBGMCU_UnFreeze_LPTIM1()         (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1))
00497 #define __HAL_DBGMCU_UnFreeze_I2C1()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1))
00498 #define __HAL_DBGMCU_UnFreeze_I2C2()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2))
00499 #define __HAL_DBGMCU_UnFreeze_I2C3()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3))
00500 #define __HAL_DBGMCU_UnFreeze_FDCAN()          (DBGMCU->APB1HFZ1  &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN))
00501
00502
00503 #define __HAL_DBGMCU_UnFreeze_TIM1()           (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM1))
00504 #define __HAL_DBGMCU_UnFreeze_TIM8()           (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM8))
00505 #define __HAL_DBGMCU_UnFreeze_TIM15()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM15))
00506 #define __HAL_DBGMCU_UnFreeze_TIM16()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM16))
00507 #define __HAL_DBGMCU_UnFreeze_TIM17()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM17))
00508 #define __HAL_DBGMCU_UnFreeze_HRTIM()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM))
00509
00510 #define __HAL_DBGMCU_UnFreeze_I2C4()           (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_I2C4))
00511 #define __HAL_DBGMCU_UnFreeze_LPTIM2()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2))
00512 #define __HAL_DBGMCU_UnFreeze_LPTIM3()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3))
00513 #define __HAL_DBGMCU_UnFreeze_LPTIM4()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4))
00514 #define __HAL_DBGMCU_UnFreeze_LPTIM5()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5))
00515 #define __HAL_DBGMCU_UnFreeze_RTC()            (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_RTC))
00516 #define __HAL_DBGMCU_UnFreeze_IWDG1()          (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1))
00517
00518
00519 /**
00520   * @}
00521   */
00522
00523 /* Exported functions --------------------------------------------------------*/
00524 /** @addtogroup HAL_Exported_Functions
00525   * @{
00526   */
00527 /** @addtogroup HAL_Exported_Functions_Group1
00528   * @{
00529   */
00530
00531 /* Initialization and de-initialization functions  ******************************/
00532 HAL_StatusTypeDef HAL_Init(void);
00533 HAL_StatusTypeDef HAL_DeInit(void);
00534 void HAL_MspInit(void);
00535 void HAL_MspDeInit(void);
00536 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
00537 /**
00538   * @}
00539   */
00540
00541 /** @addtogroup HAL_Exported_Functions_Group2
00542   * @{
00543   */
00544 /* Peripheral Control functions  ************************************************/
00545 void HAL_IncTick(void);
00546 void HAL_Delay(__IO uint32_t Delay);
00547 uint32_t HAL_GetTick(void);
00548 void HAL_SuspendTick(void);
00549 void HAL_ResumeTick(void);
00550 uint32_t HAL_GetHalVersion(void);
00551 uint32_t HAL_GetREVID(void);
00552 uint32_t HAL_GetDEVID(void);
00553 void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface);
00554 void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState );
00555 void HAL_SYSCFG_EnableBOOST(void);
00556 void HAL_SYSCFG_DisableBOOST(void);
00557 void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
00558 void HAL_EnableCompensationCell(void);
00559 void HAL_DisableCompensationCell(void);
00560 void HAL_SYSCFG_EnableIOSpeedOptimize(void);
00561 void HAL_SYSCFG_DisableIOSpeedOptimize(void);
00562 void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode);
00563 void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
00564 void HAL_EnableDBGSleepMode(void);
00565 void HAL_DisableDBGSleepMode(void);
00566 void HAL_EnableDBGStopMode(void);
00567 void HAL_DisableDBGStopMode(void);
00568 void HAL_EnableDBGStandbyMode(void);
00569 void HAL_DisableDBGStandbyMode(void);
00570 void HAL_EnableDomain3DBGStopMode(void);
00571 void HAL_DisableDomain3DBGStopMode(void);
00572 void HAL_EnableDomain3DBGStandbyMode(void);
00573 void HAL_DisableDomain3DBGStandbyMode(void);
00574 void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge );
00575 void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
00576 void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line);
00577 void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd);
00578 void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc);
00579 void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig);
00580 uint32_t HAL_GetFMCMemorySwappingConfig(void);
00581 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
00582 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
00583 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
00584 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
00585 void HAL_SYSCFG_DisableVREFBUF(void);
00586 /**
00587   * @}
00588   */
00589
00590 /**
00591   * @}
00592   */
00593 /**
00594   * @}
00595   */
00596
00597 /**
00598   * @}
00599   */
00600
00601 #ifdef __cplusplus
00602 }
00603 #endif
00604
00605 #endif /* __STM32H7xx_HAL_H */
00606
00607 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:37 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_adc.c Source File

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stm32h7xx_hal_adc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_adc.c
00004   * @author  MCD Application conversion
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Analog to Digital Convertor (ADC)
00009   *          peripheral:
00010   *           + Initialization and deinitialization functions
00011   *             ++ Initialization and Configuration of ADC
00012   *           + Operation functions
00013   *             ++ Start, stop, get result of regular conversions of regular
00014   *                using 3 possible modes: polling, interruption or DMA.
00015   *           + Control functions
00016   *             ++ Channels configuration on regular group
00017   *             ++ Analog Watchdog configuration
00018   *           + State functions
00019   *             ++ ADC state machine management
00020   *             ++ Interrupts and flags management
00021   *          Other functions (extended functions) are available in file
00022   *          "stm32h7xx_hal_adc_ex.c".
00023    @verbatim
00024   ==============================================================================
00025                     ##### ADC specific features #####
00026   ==============================================================================
00027   [..]
00028   (+) 16-bit, 14-bit, 12-bit, 10-bit or 8-bit configurable resolution.
00029
00030   (+) Interrupt generation at the end of regular conversion and in case of
00031       analog watchdog or overrun events.
00032
00033   (+) Single and continuous conversion modes.
00034
00035   (+) Scan mode for conversion of several channels sequentially.
00036
00037   (+) Data alignment with in-built data coherency.
00038
00039   (+) Programmable sampling time (channel wise)
00040
00041   (+) External trigger (timer or EXTI) with configurable polarity
00042
00043   (+) DMA request generation for transfer of conversions data of regular group.
00044
00045   (+) Configurable delay between conversions in Dual interleaved mode.
00046
00047   (+) ADC channels selectable single/differential input.
00048
00049   (+) ADC offset on regular groups.
00050
00051   (+) ADC calibration
00052
00053   (+) ADC conversion of regular group.
00054
00055   (+) ADC supply requirements: 1.62 V to 3.6 V.
00056
00057   (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
00058       Vdda or to an external voltage reference).
00059
00060                      ##### How to use this driver #####
00061   ==============================================================================
00062     [..]
00063
00064      *** Configuration of top level parameters related to ADC ***
00065      ============================================================
00066      [..]
00067
00068     (#) Enable the ADC interface
00069         (++) As prerequisite, ADC clock must be configured at RCC top level.
00070
00071         (++) Two clock settings are mandatory:
00072              (+++) ADC clock (core clock, also possibly conversion clock).
00073
00074              (+++) ADC clock (conversions clock).
00075                    Two possible clock sources: synchronous clock derived from AHB clock
00076                    or asynchronous clock derived from system clock, the PLL2 or the PLL3 running up to 400MHz.
00077
00078              (+++) Example:
00079                    Into HAL_ADC_MspInit() (recommended code location) or with
00080                    other device clock parameters configuration:
00081                (+++) __HAL_RCC_ADC_CLK_ENABLE();                  (mandatory)
00082
00083                RCC_ADCCLKSOURCE_PLL2 enable:                   (optional: if asynchronous clock selected)
00084                (+++) RCC_PeriphClkInitTypeDef   RCC_PeriphClkInit;
00085                (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
00086                (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_PLL2;
00087                (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
00088
00089         (++) ADC clock source and clock prescaler are configured at ADC level with
00090              parameter "ClockPrescaler" using function HAL_ADC_Init().
00091
00092     (#) ADC pins configuration
00093          (++) Enable the clock for the ADC GPIOs
00094               using macro __HAL_RCC_GPIOx_CLK_ENABLE()
00095          (++) Configure these ADC pins in analog mode
00096               using function HAL_GPIO_Init()
00097
00098     (#) Optionally, in case of usage of ADC with interruptions:
00099          (++) Configure the NVIC for ADC
00100               using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
00101          (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
00102               into the function of corresponding ADC interruption vector
00103               ADCx_IRQHandler().
00104
00105     (#) Optionally, in case of usage of DMA:
00106          (++) Configure the DMA (DMA channel, mode normal or circular, ...)
00107               using function HAL_DMA_Init().
00108          (++) Configure the NVIC for DMA
00109               using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
00110          (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
00111               into the function of corresponding DMA interruption vector
00112               DMAx_Channelx_IRQHandler().
00113
00114     *** Configuration of ADC, group regular, channels parameters ***
00115      ================================================================
00116      [..]
00117
00118
00119     (#) Configure the ADC parameters (resolution, data alignment, ...)
00120         and regular group parameters (conversion trigger, sequencer, ...)
00121         using function HAL_ADC_Init().
00122
00123     (#) Configure the channels for regular group parameters (channel number,
00124         channel rank into sequencer, ..., into regular group)
00125         using function HAL_ADC_ConfigChannel().
00126
00127     (#) Optionally, configure the analog watchdog parameters (channels
00128         monitored, thresholds, ...)
00129         using function HAL_ADC_AnalogWDGConfig().
00130
00131      *** Execution of ADC conversions ***
00132      ====================================
00133      [..]
00134
00135
00136     (#) Optionally, perform an automatic ADC calibration to improve the
00137         conversion accuracy
00138         using function HAL_ADCEx_Calibration_Start().
00139
00140     (#) ADC driver can be used among three modes: polling, interruption,
00141         transfer by DMA.
00142
00143         (++) ADC conversion by polling:
00144           (+++) Activate the ADC peripheral and start conversions
00145                 using function HAL_ADC_Start()
00146           (+++) Wait for ADC conversion completion
00147                 using function HAL_ADC_PollForConversion()
00148           (+++) Retrieve conversion results
00149                 using function HAL_ADC_GetValue()
00150           (+++) Stop conversion and disable the ADC peripheral
00151                 using function HAL_ADC_Stop()
00152
00153         (++) ADC conversion by interruption:
00154           (+++) Activate the ADC peripheral and start conversions
00155                 using function HAL_ADC_Start_IT()
00156           (+++) Wait for ADC conversion completion by call of function
00157                 HAL_ADC_ConvCpltCallback()
00158                 (this function must be implemented in user program)
00159           (+++) Retrieve conversion results
00160                 using function HAL_ADC_GetValue()
00161           (+++) Stop conversion and disable the ADC peripheral
00162                 using function HAL_ADC_Stop_IT()
00163
00164         (++) ADC conversion with transfer by DMA:
00165           (+++) Activate the ADC peripheral and start conversions
00166                 using function HAL_ADC_Start_DMA()
00167           (+++) Wait for ADC conversion completion by call of function
00168                 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
00169                 (these functions must be implemented in user program)
00170           (+++) Conversion results are automatically transferred by DMA into
00171                 destination variable address.
00172           (+++) Stop conversion and disable the ADC peripheral
00173                 using function HAL_ADC_Stop_DMA()
00174
00175      [..]
00176
00177
00178     (@) Callback functions must be implemented in user program:
00179       (+@) HAL_ADC_ErrorCallback()
00180       (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
00181       (+@) HAL_ADC_ConvCpltCallback()
00182       (+@) HAL_ADC_ConvHalfCpltCallback
00183
00184      *** Deinitialization of ADC ***
00185      ============================================================
00186      [..]
00187
00188
00189     (#) Disable the ADC interface
00190       (++) ADC clock can be hard reset and disabled at RCC top level.
00191         (++) Hard reset of ADC peripherals
00192              using macro __HAL_RCC_ADCx_FORCE_RESET(), __HAL_RCC_ADCx_RELEASE_RESET().
00193         (++) ADC clock disable
00194              using the equivalent macro/functions as configuration step.
00195              (+++) Example:
00196                    Into HAL_ADC_MspDeInit() (recommended code location) or with
00197                    other device clock parameters configuration:
00198                (+++) __HAL_RCC_ADC_CLK_DISABLE();                  (if not used anymore)
00199                RCC_ADCCLKSOURCE_CLKP restore:                      (optional)
00200                (+++) RCC_PeriphClkInitTypeDef   RCC_PeriphClkInit;
00201                (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
00202                (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_CLKP;
00203                (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
00204
00205     (#) ADC pins configuration
00206          (++) Disable the clock for the ADC GPIOs
00207               using macro __HAL_RCC_GPIOx_CLK_DISABLE()
00208
00209     (#) Optionally, in case of usage of ADC with interruptions:
00210          (++) Disable the NVIC for ADC
00211               using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
00212
00213     (#) Optionally, in case of usage of DMA:
00214          (++) Deinitialize the DMA
00215               using function HAL_DMA_Init().
00216          (++) Disable the NVIC for DMA
00217               using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
00218
00219     [..]
00220
00221     @endverbatim
00222   ******************************************************************************
00223   * @attention
00224   *
00225   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00226   *
00227   * Redistribution and use in source and binary forms, with or without modification,
00228   * are permitted provided that the following conditions are met:
00229   *   1. Redistributions of source code must retain the above copyright notice,
00230   *      this list of conditions and the following disclaimer.
00231   *   2. Redistributions in binary form must reproduce the above copyright notice,
00232   *      this list of conditions and the following disclaimer in the documentation
00233   *      and/or other materials provided with the distribution.
00234   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00235   *      may be used to endorse or promote products derived from this software
00236   *      without specific prior written permission.
00237   *
00238   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00239   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00240   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00241   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00242   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00243   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00244   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00245   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00246   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00247   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00248   *
00249   ******************************************************************************
00250   */
00251
00252 /* Includes ------------------------------------------------------------------*/
00253 #include "stm32h7xx_hal.h"
00254
00255 /** @addtogroup STM32H7xx_HAL_Driver
00256   * @{
00257   */
00258
00259 /** @defgroup ADC ADC
00260   * @brief ADC HAL module driver
00261   * @{
00262   */
00263
00264 #ifdef HAL_ADC_MODULE_ENABLED
00265
00266 /* Private typedef -----------------------------------------------------------*/
00267 /* Private define ------------------------------------------------------------*/
00268
00269 /** @defgroup ADC_Private_Constants ADC Private Constants
00270   * @{
00271   */
00272
00273 #define ADC_CFGR_FIELDS_1  ((uint32_t)(ADC_CFGR_RES    |\
00274                                        ADC_CFGR_CONT   | ADC_CFGR_OVRMOD  |\
00275                                        ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
00276                                        ADC_CFGR_EXTEN  | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
00277                                                                                   when no regular conversion is on-going */
00278
00279 #define ADC_CFGR_FIELDS_2  ((uint32_t)(ADC_CFGR_DMNGT | ADC_CFGR_AUTDLY)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion
00280                                                                                  (neither regular nor injected) is on-going  */
00281
00282 #define ADC_CFGR2_FIELDS  ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OSR   |\
00283                                        ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
00284                                        ADC_CFGR2_ROVSM))
00285
00286 #define ADC_CFGR_WD_FIELDS  ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN | \
00287                                         ADC_CFGR_AWD1EN | ADC_CFGR_AWD1CH)) /*!< ADC_CFGR fields of Analog Watchdog parameters that can be updated when no
00288                                                                                   conversion (neither regular nor injected) is on-going  */
00289
00290 #define ADC_OFR_FIELDS  ((uint32_t)(ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH)) /*!< ADC_OFR fields of parameters that can be updated when no conversion
00291                                                                                                         (neither regular nor injected) is on-going */
00292
00293 /* Delay to wait before setting ADEN once ADCAL has been reset
00294    must be at least 4 ADC clock cycles.
00295    Assuming lowest ADC clock (350 KHz according to DS), this
00296    4 ADC clock cycles duration is equal to
00297    4 / 350,000 = 0.011 ms.
00298    ADC_ENABLE_TIMEOUT set to 2 is a margin large enough to ensure
00299    the 4 ADC clock cycles have elapsed while waiting for ADRDY
00300    to become 1 */
00301   #define ADC_ENABLE_TIMEOUT              ((uint32_t)  2)    /*!< ADC enable time-out value  */
00302   #define ADC_DISABLE_TIMEOUT             ((uint32_t)  2)    /*!< ADC disable time-out value */
00303
00304 /* Timeout to wait for current conversion on going to be completed.           */
00305 /* Timeout fixed to worst case, for 1 channel.                                */
00306 /*   - maximum sampling time (830.5 adc_clk)                                  */
00307 /*   - ADC resolution (Tsar 16 bits= 16.5 adc_clk)                            */
00308 /*   - ADC clock with prescaler 256                                           */
00309 /*     823 * 256 = 210688 clock cycles max                                    */
00310 /* Unit: cycles of CPU clock.                                                 */
00311 #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 210688)  /*!< ADC conversion completion time-out value */
00312
00313
00314
00315
00316 /**
00317   * @}
00318   */
00319
00320 /* Private macro -------------------------------------------------------------*/
00321 /* Private variables ---------------------------------------------------------*/
00322 /* Private function prototypes -----------------------------------------------*/
00323 /* Exported functions --------------------------------------------------------*/
00324
00325 /** @defgroup ADC_Exported_Functions ADC Exported Functions
00326   * @{
00327   */
00328
00329 /** @defgroup ADC_Exported_Functions_Group1 Initialization and deinitialization functions
00330   * @brief    ADC Initialization and Configuration functions
00331   *
00332 @verbatim
00333  ===============================================================================
00334               ##### Initialization and deinitialization functions #####
00335  ===============================================================================
00336     [..] This section provides functions allowing to:
00337       (+) Initialize and configure the ADC.
00338       (+) Deinitialize the ADC.
00339
00340 @endverbatim
00341   * @{
00342   */
00343 /**
00344   * @brief  Initialize the ADC peripheral and regular group according to
00345   *         parameters specified in structure "ADC_InitTypeDef".
00346   * @note   As prerequisite, ADC clock must be configured at RCC top level
00347   *         depending on possible clock sources: PLL2/PLL3 clocks or AHB clock.
00348   * @note   Possibility to update parameters on the fly:
00349   *         this function initializes the ADC MSP (HAL_ADC_MspInit()) only when
00350   *         coming from ADC state reset. Following calls to this function can
00351   *         be used to reconfigure some parameters of ADC_InitTypeDef
00352   *         structure on the fly, without modifying MSP configuration. If ADC
00353   *         MSP has to be modified again, HAL_ADC_DeInit() must be called
00354   *         before HAL_ADC_Init().
00355   *         The setting of these parameters is conditioned by ADC state.
00356   *         For parameters constraints, see comments of structure
00357   *         "ADC_InitTypeDef".
00358   * @note   This function configures the ADC within 2 scopes: scope of entire
00359   *         ADC and scope of regular group. For parameters details, see comments
00360   *         of structure "ADC_InitTypeDef".
00361   * @note   Parameters related to common ADC registers (ADC clock mode) are set
00362   *         only if all ADCs are disabled.
00363   *         If this is not the case, these common parameters setting are
00364   *         bypassed without error reporting: it can be the intended behaviour in
00365   *         case of update of a parameter of ADC_InitTypeDef on the fly,
00366   *         without  disabling the other ADCs.
00367   * @param  hadc: ADC handle
00368   * @retval HAL status
00369   */
00370 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
00371 {
00372   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00373
00374   ADC_Common_TypeDef *tmpADC_Common;
00375   uint32_t tmpCFGR = 0;
00376   __IO uint32_t wait_loop_index = 0;
00377
00378   /* Check ADC handle */
00379   if(hadc == NULL)
00380   {
00381     return HAL_ERROR;
00382   }
00383
00384   /* Check the parameters */
00385   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00386   assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
00387   assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
00388   assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
00389   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00390   assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
00391   assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
00392   assert_param(IS_ADC_CONVERSIONDATAMGT(hadc->Init.ConversionDataManagement));
00393   assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
00394   assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
00395   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
00396   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
00397   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.BoostMode));
00398
00399   if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
00400   {
00401     assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
00402     assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
00403
00404     if (hadc->Init.DiscontinuousConvMode == ENABLE)
00405     {
00406       assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
00407     }
00408   }
00409
00410
00411   /* DISCEN and CONT bits can not be set at the same time */
00412   assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
00413
00414
00415   /* Actions performed only if ADC is coming from state reset:                */
00416   /* - Initialization of ADC MSP                                              */
00417   if (hadc->State == HAL_ADC_STATE_RESET)
00418   {
00419     /* Init the low level hardware */
00420     HAL_ADC_MspInit(hadc);
00421
00422     /* Set ADC error code to none */
00423     ADC_CLEAR_ERRORCODE(hadc);
00424
00425     /* Initialize Lock */
00426     hadc->Lock = HAL_UNLOCKED;
00427   }
00428
00429
00430   /* - Exit from deep-power-down mode and ADC voltage regulator enable        */
00431   /*  Exit deep power down mode if still in that state                        */
00432   if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD))
00433   {
00434     /* Exit deep power down mode */
00435     CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
00436
00437     /* System was in deep power down mode, calibration must
00438        be relaunched or a previously saved calibration factor
00439        re-applied once the ADC voltage regulator is enabled   */
00440   }
00441
00442
00443   if  (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
00444   {
00445     /* Enable ADC internal voltage regulator */
00446     SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
00447     /* Delay for ADC stabilization time                                       */
00448     /* Wait loop initialization and execution                                 */
00449     /* Note: Variable divided by 2 to compensate partially                    */
00450     /*       CPU processing cycles.                                           */
00451     wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000 * 2)));
00452     while(wait_loop_index != 0)
00453     {
00454       wait_loop_index--;
00455     }
00456   }
00457
00458
00459   /* Verification that ADC voltage regulator is correctly enabled, whether    */
00460   /* or not ADC is coming from state reset (if any potential problem of       */
00461   /* clocking, voltage regulator would not be enabled).                       */
00462   if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
00463   {
00464     /* Update ADC state machine to error */
00465     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00466
00467     /* Set ADC error code to ADC IP internal error */
00468     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00469
00470     tmp_hal_status = HAL_ERROR;
00471   }
00472
00473
00474   /* Configuration of ADC parameters if previous preliminary actions are      */
00475   /* correctly completed and if there is no conversion on going on regular    */
00476   /* group (ADC may already be enabled at this point if HAL_ADC_Init() is     */
00477   /* called to update a parameter on the fly).                                */
00478   if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
00479       (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)  )
00480   {
00481
00482     /* Initialize the ADC state */
00483     SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
00484
00485     /* Configuration of common ADC parameters                                 */
00486
00487     if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
00488     {
00489       /* Pointer to the common control register                               */
00490       tmpADC_Common = ADC12_COMMON_REGISTER(hadc);
00491     }
00492     else
00493     {
00494       /* Pointer to the common control register                               */
00495       tmpADC_Common = ADC3_COMMON_REGISTER(hadc);
00496     }
00497
00498     /* Parameters update conditioned to ADC state:                            */
00499     /* Parameters that can be updated only when ADC is disabled:              */
00500     /*  - Multimode clock configuration                                       */
00501     if ((ADC_IS_ENABLE(hadc) == RESET)   &&
00502         (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
00503     {
00504       /* Reset configuration of ADC common register CCR:                      */
00505       /*                                                                      */
00506       /*   - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set  */
00507       /*     according to adc->Init.ClockPrescaler. It selects the clock      */
00508       /*    source and sets the clock division factor.                        */
00509       /*                                                                      */
00510       /* Some parameters of this register are not reset, since they are set   */
00511       /* by other functions and must be kept in case of usage of this         */
00512       /* function on the fly (update of a parameter of ADC_InitTypeDef        */
00513       /* without needing to reconfigure all other ADC groups/channels         */
00514       /* parameters):                                                         */
00515       /*   - when multimode feature is available, multimode-related           */
00516       /*     parameters:DELAY,DUAL(set by API                                 */
00517       /*     HAL_ADCEx_MultiModeConfigChannel())                              */
00518       /*   - internal measurement paths: Vbat, temperature sensor, Vref       */
00519       /*     (set into HAL_ADC_ConfigChannel() or                             */
00520       /*     HAL_ADCEx_InjectedConfigChannel() )                              */
00521
00522       MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_PRESC|ADC_CCR_CKMODE, hadc->Init.ClockPrescaler);
00523     }
00524
00525
00526     /* Configuration of ADC:                                                  */
00527     /*  - resolution                               Init.Resolution            */
00528     /*  - external trigger to start conversion     Init.ExternalTrigConv      */
00529     /*  - external trigger polarity                Init.ExternalTrigConvEdge  */
00530     /*  - continuous conversion mode               Init.ContinuousConvMode    */
00531     /*  - overrun                                  Init.Overrun               */
00532     /*  - discontinuous mode                       Init.DiscontinuousConvMode */
00533     /*  - discontinuous mode channel count         Init.NbrOfDiscConversion   */
00534     tmpCFGR  = ( ADC_CFGR_CONTINUOUS(hadc->Init.ContinuousConvMode)          |
00535                  hadc->Init.Overrun                                          |
00536                  hadc->Init.Resolution                                       |
00537                 ADC_CFGR_REG_DISCONTINUOUS(hadc->Init.DiscontinuousConvMode)  );
00538
00539     if (hadc->Init.DiscontinuousConvMode == ENABLE)
00540     {
00541       tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
00542     }
00543
00544     /* Enable external trigger if trigger selection is different of software  */
00545     /* start.                                                                 */
00546     /*  - external trigger to start conversion     Init.ExternalTrigConv      */
00547     /*  - external trigger polarity                Init.ExternalTrigConvEdge  */
00548     /* Note:  parameter ExternalTrigConvEdge set to "trigger edge none" is    */
00549     /*        equivalent to software start.                                   */
00550     if ((hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
00551         && (hadc->Init.ExternalTrigConvEdge != ADC_EXTERNALTRIGCONVEDGE_NONE))
00552     {
00553       tmpCFGR |= ( hadc->Init.ExternalTrigConv |  hadc->Init.ExternalTrigConvEdge);
00554     }
00555
00556     /* Update Configuration Register CFGR */
00557     MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
00558
00559
00560     /* Parameters update conditioned to ADC state:                            */
00561     /* Parameters that can be updated when ADC is disabled or enabled without */
00562     /* conversion on going on regular and injected groups:                    */
00563     /*  - Conversion data management      Init.ConversionDataManagement       */
00564     /*  - LowPowerAutoWait feature        Init.LowPowerAutoWait               */
00565     /*  - Oversampling parameters         Init.Oversampling                   */
00566     /*  - Boost Mode                      BoostMode                           */
00567     if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
00568     {
00569       tmpCFGR = ( ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait)       |
00570                   ADC_CFGR_DMACONTREQ(hadc->Init.ConversionDataManagement) );
00571
00572       MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
00573
00574
00575       if (hadc->Init.OversamplingMode == ENABLE)
00576       {
00577         assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
00578         assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
00579         assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
00580         assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
00581
00582         if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
00583             || (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
00584         {
00585           /* Multi trigger is not applicable to software-triggered conversions */
00586           assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER));
00587         }
00588
00589
00590        /* Configuration of Oversampler:                                       */
00591        /*  - Oversampling Ratio                                               */
00592        /*  - Right bit shift                                                  */
00593        /*  - Leftt bit shift                                                  */
00594        /*  - Triggered mode                                                   */
00595        /*  - Oversampling mode (continued/resumed)                            */
00596        MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
00597                                          ADC_CFGR2_ROVSE                       |
00598                                          (hadc->Init.Oversampling.Ratio << 16) |
00599                                          hadc->Init.Oversampling.RightBitShift |
00600                                          hadc->Init.Oversampling.TriggeredMode |
00601                                          hadc->Init.Oversampling.OversamplingStopReset);
00602       }
00603       else
00604       {
00605         /* Disable Regular OverSampling */
00606         CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
00607       }
00608
00609       /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */
00610       MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift);
00611
00612       /* Configure the BOOST Mode */
00613       if(hadc->Init.BoostMode == ENABLE)
00614       {
00615         SET_BIT(hadc->Instance->CR, ADC_CR_BOOST);
00616       }
00617       else
00618       {
00619         CLEAR_BIT(hadc->Instance->CR, ADC_CR_BOOST);
00620       }
00621
00622     }   /*  if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
00623
00624     /* Configuration of regular group sequencer:                              */
00625     /* - if scan mode is disabled, regular channels sequence length is set to */
00626     /*   0x00: 1 channel converted (channel on regular rank 1)                */
00627     /*   Parameter "NbrOfConversion" is discarded.                            */
00628     /*   Note: Scan mode is not present by hardware on this device, but       */
00629     /*   emulated by software for alignment over all STM32 devices.           */
00630     /* - if scan mode is enabled, regular channels sequence length is set to  */
00631     /*   parameter "NbrOfConversion"                                          */
00632
00633     if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
00634     {
00635       /* Set number of ranks in regular group sequencer */
00636       MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
00637     }
00638     else
00639     {
00640       CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
00641     }
00642
00643
00644     /* Initialize the ADC state */
00645     /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
00646     ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
00647   }
00648   else
00649   {
00650     /* Update ADC state machine to error */
00651     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00652
00653     tmp_hal_status = HAL_ERROR;
00654   }  /*  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)  && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)  ) */
00655
00656
00657   /* Return function status */
00658   return tmp_hal_status;
00659
00660 }
00661
00662 /**
00663   * @brief  Deinitialize the ADC peripheral registers to their default reset
00664   *         values, with deinitialization of the ADC MSP.
00665   * @note   Keep in mind that all ADCs use the same clock: disabling
00666   *         the clock will reset all ADCs.
00667   * @note   By default, HAL_ADC_DeInit() sets DEEPPWD: this saves more power by
00668   *         reducing the leakage currents and is particularly interesting before
00669   *         entering STOP 1 or STOP 2 modes.
00670   * @param  hadc: ADC handle
00671   * @retval HAL status
00672   */
00673 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
00674 {
00675   ADC_Common_TypeDef *tmpADC_Common;
00676
00677   /* Check ADC handle */
00678   if(hadc == NULL)
00679   {
00680      return HAL_ERROR;
00681   }
00682
00683   /* Check the parameters */
00684   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00685
00686   /* Set ADC state */
00687   SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
00688
00689   /* Stop potential conversion on going, on regular and injected groups */
00690   /* No check on ADC_ConversionStop() return status, if the conversion
00691     stop failed, it is up to HAL_ADC_MspDeInit() to reset the ADC IP */
00692   ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
00693
00694
00695   /* Disable ADC peripheral if conversions are effectively stopped            */
00696   /* Flush register JSQR: reset the queue sequencer when injected             */
00697   /* queue sequencer is enabled and ADC disabled.                             */
00698   /* The software and hardware triggers of the injected sequence are both     */
00699   /* internally disabled just after the completion of the last valid          */
00700   /* injected sequence.                                                       */
00701   SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
00702
00703   /* Disable the ADC peripheral                                               */
00704   /* No check on ADC_Disable() return status, if the ADC disabling process
00705      failed, it is up to HAL_ADC_MspDeInit() to reset the ADC IP              */
00706   ADC_Disable(hadc);
00707
00708
00709   /* ========== Reset ADC registers ========== */
00710   /* Reset register IER */
00711   __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3  | ADC_IT_AWD2 | ADC_IT_AWD1 |
00712                               ADC_IT_JQOVF | ADC_IT_OVR  |
00713                               ADC_IT_JEOS  | ADC_IT_JEOC |
00714                               ADC_IT_EOS   | ADC_IT_EOC  |
00715                               ADC_IT_EOSMP | ADC_IT_RDY                 ) );
00716
00717   /* Reset register ISR */
00718   __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3  | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
00719                               ADC_FLAG_JQOVF | ADC_FLAG_OVR  |
00720                               ADC_FLAG_JEOS  | ADC_FLAG_JEOC |
00721                               ADC_FLAG_EOS   | ADC_FLAG_EOC  |
00722                               ADC_FLAG_EOSMP | ADC_FLAG_RDY                   ) );
00723
00724   /* Reset register CR */
00725  /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
00726     ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
00727     no direct reset applicable.
00728     Update CR register to reset value where doable by software */
00729   CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
00730   SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
00731
00732   /* Reset register CFGR */
00733   CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN |
00734                                   ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM     |
00735                                   ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN  |
00736                                   ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD  |
00737                                   ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  |
00738                                   ADC_CFGR_RES     | ADC_CFGR_DMNGT);
00739   SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
00740
00741   /* Reset register CFGR2 */
00742   CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS |
00743                                    ADC_CFGR2_OSR   | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE );
00744
00745   /* Reset register SMPR1 */
00746   CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |
00747                                    ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |
00748                                    ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |
00749                                    ADC_SMPR1_SMP0 );
00750
00751   /* Reset register SMPR2 */
00752   CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
00753                                    ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
00754                                    ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10 );
00755
00756   /* Reset register LTR1 and HTR1 */
00757   CLEAR_BIT(hadc->Instance->LTR1, ADC_LTR1_LT1);
00758   CLEAR_BIT(hadc->Instance->HTR1, ADC_HTR1_HT1);
00759
00760   /* Reset register LTR2 and HTR2*/
00761   CLEAR_BIT(hadc->Instance->LTR2, ADC_LTR2_LT2);
00762   CLEAR_BIT(hadc->Instance->HTR2, ADC_HTR2_HT2);
00763
00764   /* Reset register LTR3 and HTR3 */
00765   CLEAR_BIT(hadc->Instance->LTR3, ADC_LTR3_LT3);
00766   CLEAR_BIT(hadc->Instance->HTR3, ADC_HTR3_HT3);
00767
00768   /* Reset register SQR1 */
00769   CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
00770                                   ADC_SQR1_SQ1 | ADC_SQR1_L);
00771
00772   /* Reset register SQR2 */
00773   CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
00774                                   ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
00775
00776   /* Reset register SQR3 */
00777   CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
00778                                   ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
00779
00780   /* Reset register SQR4 */
00781   CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
00782
00783   /* Register JSQR was reset when the ADC was disabled */
00784
00785   /* Reset register DR */
00786   /* bits in access mode read only, no direct reset applicable*/
00787
00788   /* Reset register OFR1 */
00789   CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
00790   /* Reset register OFR2 */
00791   CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
00792   /* Reset register OFR3 */
00793   CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
00794   /* Reset register OFR4 */
00795   CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
00796
00797   /* Reset registers JDR1, JDR2, JDR3, JDR4 */
00798   /* bits in access mode read only, no direct reset applicable*/
00799
00800   /* Reset register AWD2CR */
00801   CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
00802
00803   /* Reset register AWD3CR */
00804   CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
00805
00806   /* Reset register DIFSEL */
00807   CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
00808
00809   /* Reset register CALFACT */
00810   CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
00811
00812
00813   /* ========== Reset common ADC registers ========== */
00814
00815   /* Software is allowed to change common parameters only when all the other
00816      ADCs are disabled.   */
00817   if ((ADC_IS_ENABLE(hadc) == RESET)   &&
00818       (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
00819   {
00820     /* Reset configuration of ADC common register CCR:
00821       - clock mode: CKMODE, PRESCEN
00822       - multimode related parameters(when this feature is available): DELAY, DUAL
00823        (set into  HAL_ADCEx_MultiModeConfigChannel() )
00824       - internal measurement paths: Vbat, temperature sensor, Vref (set into
00825         HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
00826     */
00827     if((hadc->Instance == ADC1)||(hadc->Instance == ADC2))
00828     {
00829       tmpADC_Common = ADC12_COMMON_REGISTER(hadc);
00830     }
00831     else
00832     {
00833       tmpADC_Common = ADC3_COMMON_REGISTER(hadc);
00834     }
00835     CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_CKMODE |
00836                                   ADC_CCR_PRESC  |
00837                                   ADC_CCR_VBATEN |
00838                                   ADC_CCR_TSEN   |
00839                                   ADC_CCR_VREFEN |
00840                                   ADC_CCR_DAMDF  |
00841                                   ADC_CCR_DELAY  |
00842                                   ADC_CCR_DUAL  );
00843
00844   }
00845
00846   /* DeInit the low level hardware.
00847
00848      For example:
00849     __HAL_RCC_ADC_FORCE_RESET();
00850     __HAL_RCC_ADC_RELEASE_RESET();
00851     __HAL_RCC_ADC_CLK_DISABLE();
00852
00853     Keep in mind that all ADCs use the same clock: disabling
00854     the clock will reset all ADCs.
00855
00856   */
00857   HAL_ADC_MspDeInit(hadc);
00858
00859   /* Set ADC error code to none */
00860   ADC_CLEAR_ERRORCODE(hadc);
00861
00862   /* Reset injected channel configuration parameters */
00863   hadc->InjectionConfig.ContextQueue = 0;
00864   hadc->InjectionConfig.ChannelCount = 0;
00865
00866   /* Set ADC state */
00867   hadc->State = HAL_ADC_STATE_RESET;
00868
00869   /* Process unlocked */
00870   __HAL_UNLOCK(hadc);
00871
00872
00873   /* Return function status */
00874   return HAL_OK;
00875
00876 }
00877
00878 /**
00879   * @brief  Initialize the ADC MSP.
00880   * @param  hadc: ADC handle
00881   * @retval None
00882   */
00883 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
00884 {
00885   /* Prevent unused argument(s) compilation warning */
00886   UNUSED(hadc);
00887   /* NOTE : This function should not be modified. When the callback is needed,
00888             function HAL_ADC_MspInit must be implemented in the user file.
00889    */
00890 }
00891
00892 /**
00893   * @brief  DeInitialize the ADC MSP.
00894   * @param  hadc: ADC handle
00895   * @note   All ADCs use the same clock: disabling the clock will reset all ADCs.
00896   * @retval None
00897   */
00898 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
00899 {
00900   /* Prevent unused argument(s) compilation warning */
00901   UNUSED(hadc);
00902   /* NOTE : This function should not be modified. When the callback is needed,
00903             function HAL_ADC_MspDeInit must be implemented in the user file.
00904    */
00905 }
00906
00907 /**
00908   * @}
00909   */
00910
00911 /** @defgroup ADC_Exported_Functions_Group2 Input and Output operation functions
00912   * @brief    ADC IO operation functions
00913   *
00914 @verbatim
00915  ===============================================================================
00916              ##### IO operation functions #####
00917  ===============================================================================
00918     [..] This section provides functions allowing to:
00919       (+) Start conversion of regular group.
00920       (+) Stop conversion of regular group.
00921       (+) Poll for conversion complete on regular group.
00922       (+) Poll for conversion event.
00923       (+) Get result of regular channel conversion.
00924       (+) Start conversion of regular group and enable interruptions.
00925       (+) Stop conversion of regular group and disable interruptions.
00926       (+) Handle ADC interrupt request
00927       (+) Start conversion of regular group and enable DMA transfer.
00928       (+) Stop conversion of regular group and disable ADC DMA transfer.
00929
00930 @endverbatim
00931   * @{
00932   */
00933
00934 /**
00935   * @brief  Enable ADC, starts conversion of regular group.
00936   * @note   Interruptions enabled in this function: None.
00937   * @note   Case of multimode enabled(when multimode feature is available):
00938   *            if ADC is Slave, ADC is enabled but conversion is not started,
00939   *            if ADC is master, ADC is enabled and multimode conversion is started.
00940   * @param  hadc: ADC handle
00941   * @retval HAL status
00942   */
00943 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
00944 {
00945   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00946   ADC_TypeDef        *tmpADC_Master;
00947
00948   /* Check the parameters */
00949   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00950
00951   /* Perform ADC enable and conversion start if no conversion is on going */
00952   if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
00953   {
00954     /* Process locked */
00955     __HAL_LOCK(hadc);
00956
00957     /* Enable the ADC peripheral */
00958     tmp_hal_status = ADC_Enable(hadc);
00959
00960     /* Start conversion if ADC is effectively enabled */
00961     if (tmp_hal_status == HAL_OK)
00962     {
00963       /* State machine update: Check if an injected conversion is ongoing */
00964       if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
00965       {
00966         /* Reset ADC error code fields related to regular conversions only */
00967         CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA));
00968       }
00969       else
00970       {
00971         /* Set ADC error code to none */
00972         ADC_CLEAR_ERRORCODE(hadc);
00973       }
00974       /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
00975       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
00976
00977       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
00978         - by default if ADC is Master or Independent
00979         - if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */
00980       if (ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
00981       {
00982         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00983       }
00984
00985       /* Clear regular group conversion flag and overrun flag                   */
00986       /* (To ensure of no unknown state from potential previous ADC operations) */
00987       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
00988
00989       /* Enable conversion of regular group.                                  */
00990       /* If software start has been selected, conversion starts immediately.  */
00991       /* If external trigger has been selected, conversion starts at next     */
00992       /* trigger event.                                                       */
00993       /* Case of multimode enabled(when multimode feature is available):      */
00994       /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
00995       /*    enabled only (conversion is not started),                         */
00996       /*  - if ADC is master, ADC is enabled and conversion is started.       */
00997       if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
00998       {
00999         /* Multimode feature is not available or ADC Instance is Independent or Master,
01000              or is not Slave ADC with dual regular conversions enabled.
01001              Then, set HAL_ADC_STATE_INJ_BUSY bit and reset HAL_ADC_STATE_INJ_EOC bit if JAUTO is set. */
01002         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
01003         {
01004           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01005         }
01006         /* Process unlocked */
01007         __HAL_UNLOCK(hadc);
01008         /* Start ADC */
01009         SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
01010       }
01011       else
01012       {
01013         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01014         /* if Master ADC JAUTO bit is set, update Slave State in setting
01015            HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
01016         tmpADC_Master = ADC_MASTER_REGISTER(hadc);
01017         if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET)
01018         {
01019           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01020
01021         }  /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */
01022         /* Process unlocked */
01023         __HAL_UNLOCK(hadc);
01024       }    /* if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) */
01025     }
01026     else
01027     {
01028       /* Process unlocked */
01029       __HAL_UNLOCK(hadc);
01030     }
01031   }
01032   else
01033   {
01034     tmp_hal_status = HAL_BUSY;
01035   }
01036
01037   /* Return function status */
01038   return tmp_hal_status;
01039 }
01040
01041 /**
01042   * @brief  Stop ADC conversion of regular group (and injected channels in
01043   *         case of auto_injection mode), disable ADC peripheral.
01044   * @note   ADC peripheral disable is forcing stop of potential
01045   *         conversion on injected group. If injected group is under use, it
01046   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
01047   * @param  hadc: ADC handle
01048   * @retval HAL status.
01049   */
01050 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
01051 {
01052   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01053
01054   /* Check the parameters */
01055   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01056
01057   /* Process locked */
01058   __HAL_LOCK(hadc);
01059
01060   /* 1. Stop potential conversion on going, on ADC groups regular and injected */
01061   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
01062
01063   /* Disable ADC peripheral if conversions are effectively stopped */
01064   if (tmp_hal_status == HAL_OK)
01065   {
01066     /* 2. Disable the ADC peripheral */
01067     tmp_hal_status = ADC_Disable(hadc);
01068
01069     /* Check if ADC is effectively disabled */
01070     if (tmp_hal_status == HAL_OK)
01071     {
01072       /* Set ADC state */
01073       /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
01074       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
01075     }
01076   }
01077
01078   /* Process unlocked */
01079   __HAL_UNLOCK(hadc);
01080
01081   /* Return function status */
01082   return tmp_hal_status;
01083 }
01084
01085
01086
01087 /**
01088   * @brief  Wait for regular group conversion to be completed.
01089   * @param  hadc: ADC handle
01090   * @param  Timeout: Timeout value in millisecond.
01091   * @note   Depending on hadc->Init.EOCSelection, EOS or EOC is
01092   *         checked and cleared depending on AUTDLY bit status.
01093   * @note   HAL_ADC_PollForConversion() returns HAL_ERROR if EOC is polled in a
01094   *         DMA-managed conversions configuration: indeed, EOC is immediately
01095   *         reset by the DMA reading the DR register when the converted data is
01096   *         available. Therefore, EOC is set for a too short period to be
01097   *         reliably polled.
01098   * @retval HAL status
01099   */
01100 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
01101 {
01102   uint32_t           tickstart = 0;
01103   uint32_t           tmp_Flag_EOC   = 0x00;
01104   ADC_Common_TypeDef *tmpADC_Common;
01105   ADC_TypeDef        *tmpADC_Master;
01106   uint32_t           tmp_cfgr       = 0x00;
01107   uint32_t           tmp_eos_raised = 0x01; /* by default, assume that EOS is set,
01108                                                tmp_eos_raised will be corrected
01109                                                accordingly during API execution */
01110
01111   /* Check the parameters */
01112   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01113
01114    /* If end of conversion selected to end of sequence conversions */
01115   if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
01116   {
01117     tmp_Flag_EOC = ADC_FLAG_EOS;
01118   }
01119   /* If end of conversion selected to end of unitary conversion */
01120   else  /* ADC_EOC_SINGLE_CONV */
01121   {
01122     /* Check that the ADC is not in a DMA-based configuration. Otherwise,
01123        returns an error.  */
01124
01125     /* Check whether dual regular conversions are disabled or unavailable. */
01126     if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET)
01127     {
01128       /* Check DMNGT bit in handle ADC CFGR register */
01129       if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0) != RESET)
01130       {
01131         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01132         return HAL_ERROR;
01133       }
01134     }
01135     else
01136     {
01137       /* Else need to check Common register CCR DAMDF bit field. */
01138       /* Set pointer to the common control register */
01139
01140       /* Pointer to the common control register                                 */
01141       /* Dual ADC mode, could be only ADC1 or ADC2                              */
01142       tmpADC_Common = ADC12_COMMON_REGISTER(hadc);
01143
01144       if ((READ_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF) == ADC_DUALMODEDATAFORMAT_32_10_BITS)
01145           || (READ_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF) == ADC_DUALMODEDATAFORMAT_8_BITS))
01146       {
01147         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01148         return HAL_ERROR;
01149       }
01150     }
01151
01152     /* no DMA transfer detected, polling ADC_FLAG_EOC is possible */
01153     tmp_Flag_EOC = ADC_FLAG_EOC;
01154   }
01155
01156   /* Get tick count */
01157   tickstart = HAL_GetTick();
01158
01159   /* Wait until End of Conversion or Sequence flag is raised */
01160   while (HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
01161   {
01162     /* Check if timeout is disabled (set to infinite wait) */
01163     if(Timeout != HAL_MAX_DELAY)
01164     {
01165       if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
01166       {
01167         /* Update ADC state machine to timeout */
01168         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
01169
01170         /* Process unlocked */
01171         __HAL_UNLOCK(hadc);
01172
01173         return HAL_TIMEOUT;
01174       }
01175     }
01176   }
01177
01178   /* Next, to clear the polled flag as well as to update the handle State,
01179      EOS is checked and the relevant configuration register is retrieved. */
01180   /*   1. Check whether or not EOS is set */
01181   if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_EOS))
01182   {
01183     tmp_eos_raised = 0;
01184   }
01185   /*  2. Check whether or not hadc is the handle of a Slave ADC with dual
01186    regular conversions enabled. */
01187   if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
01188   {
01189     /* Retrieve handle ADC CFGR register */
01190     tmp_cfgr = READ_REG(hadc->Instance->CFGR);
01191   }
01192   else
01193   {
01194     /* Retrieve Master ADC CFGR register */
01195     tmpADC_Master = ADC_MASTER_REGISTER(hadc);
01196     tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
01197   }
01198
01199   /* Clear polled flag */
01200   if (tmp_Flag_EOC == ADC_FLAG_EOS)
01201   {
01202     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
01203   }
01204   else
01205   {
01206
01207     /* Clear end of conversion EOC flag of regular group if low power feature */
01208     /* "LowPowerAutoWait " is disabled, to not interfere with this feature    */
01209     /* until data register is read using function HAL_ADC_GetValue().         */
01210     /* For regular groups, no new conversion will start before EOC is cleared.*/
01211     /* Note that 1. reading DR clears EOC.                                    */
01212     /*           2. in multimode with dual regular conversions enabled (when  */
01213     /*              multimode feature is available), Master AUTDLY bit is     */
01214     /*              checked.                                                  */
01215     if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
01216     {
01217       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
01218     }
01219   }
01220
01221
01222   /* Update ADC state machine */
01223   SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
01224   /* If 1. EOS is set
01225         2. conversions are software-triggered
01226         3. CONT bit is reset (that of handle ADC or Master ADC if applicable)
01227      Then regular conversions are over and HAL_ADC_STATE_REG_BUSY can be reset.
01228         4. additionally, if no injected conversions are on-going, HAL_ADC_STATE_READY
01229           can be set */
01230   if ((tmp_eos_raised)
01231       && (ADC_IS_SOFTWARE_START_REGULAR(hadc))
01232       && (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET))
01233   {
01234     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01235     /* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */
01236     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01237     {
01238       SET_BIT(hadc->State, HAL_ADC_STATE_READY);
01239     }
01240   }
01241
01242
01243   /* Return function status */
01244   return HAL_OK;
01245 }
01246
01247 /**
01248   * @brief  Poll for ADC event.
01249   * @param  hadc: ADC handle
01250   * @param  EventType: the ADC event type.
01251   *          This parameter can be one of the following values:
01252   *            @arg @ref ADC_EOSMP_EVENT  ADC End of Sampling event
01253   *            @arg @ref ADC_AWD1_EVENT   ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
01254   *            @arg @ref ADC_AWD2_EVENT   ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
01255   *            @arg @ref ADC_AWD3_EVENT   ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
01256   *            @arg @ref ADC_OVR_EVENT    ADC Overrun event
01257   *            @arg @ref ADC_JQOVF_EVENT  ADC Injected context queue overflow event
01258   * @param  Timeout: Timeout value in millisecond.
01259   * @note   The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
01260   *         Indeed, the latter is reset only if hadc->Init.Overrun field is set
01261   *         to ADC_OVR_DATA_OVERWRITTEN. Otherwise, DR may be potentially overwritten
01262   *         by a new converted data as soon as OVR is cleared.
01263   *         To reset OVR flag once the preserved data is retrieved, the user can resort
01264   *         to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
01265   * @retval HAL status
01266   */
01267 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
01268 {
01269   uint32_t tickstart = 0;
01270
01271   /* Check the parameters */
01272   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01273   assert_param(IS_ADC_EVENT_TYPE(EventType));
01274
01275   /* Get tick count */
01276   tickstart = HAL_GetTick();
01277
01278   /* Check selected event flag */
01279   while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
01280   {
01281     /* Check if timeout is disabled (set to infinite wait) */
01282     if(Timeout != HAL_MAX_DELAY)
01283     {
01284       if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
01285       {
01286         /* Update ADC state machine to timeout */
01287         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
01288
01289         /* Process unlocked */
01290         __HAL_UNLOCK(hadc);
01291
01292         return HAL_TIMEOUT;
01293       }
01294     }
01295   }
01296
01297
01298   switch(EventType)
01299   {
01300     /* End Of Sampling event */
01301     case ADC_EOSMP_EVENT:
01302       /* Set ADC state */
01303       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
01304
01305       /* Clear the End Of Sampling flag */
01306       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
01307
01308       break;
01309
01310     /* Analog watchdog (level out of window) event                              */
01311     /* Note: In case of several analog watchdog enabled, if needed to know      */
01312     /* which one triggered and on which ADCx, test ADC state of Analog Watchdog */
01313     /* flags HAL_ADC_STATE_AWD/2/3 function.                                    */
01314     /* For example: "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD) "        */
01315     /*              "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD2)"        */
01316     /*              "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD3)"        */
01317     case ADC_AWD_EVENT:
01318       /* Set ADC state */
01319       SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
01320
01321       /* Clear ADC analog watchdog flag */
01322       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
01323
01324       break;
01325
01326     /* Check analog watchdog 2 flag */
01327     case ADC_AWD2_EVENT:
01328       /* Set ADC state */
01329       SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
01330
01331       /* Clear ADC analog watchdog flag */
01332       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
01333
01334       break;
01335
01336     /* Check analog watchdog 3 flag */
01337     case ADC_AWD3_EVENT:
01338       /* Set ADC state */
01339       SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
01340
01341       /* Clear ADC analog watchdog flag */
01342       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
01343
01344       break;
01345
01346     /* Injected context queue overflow event */
01347     case ADC_JQOVF_EVENT:
01348       /* Set ADC state */
01349       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
01350
01351       /* Set ADC error code to Injected context queue overflow */
01352       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
01353
01354       /* Clear ADC Injected context queue overflow flag */
01355       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
01356
01357       break;
01358
01359     /* Overrun event */
01360     default: /* Case ADC_OVR_EVENT */
01361       /* If overrun is set to overwrite previous data, overrun event is not     */
01362       /* considered as an error.                                                */
01363       /* (cf ref manual "Managing conversions without using the DMA and without */
01364       /* overrun ")                                                             */
01365       if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
01366       {
01367         /* Set ADC state */
01368         SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
01369
01370         /* Set ADC error code to overrun */
01371         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
01372       }
01373       else
01374       {
01375         /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
01376            otherwise, data register  is potentially overwritten by new converted data as soon
01377            as OVR is cleared. */
01378         __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
01379       }
01380       break;
01381   }
01382
01383   /* Return function status */
01384   return HAL_OK;
01385 }
01386
01387
01388 /**
01389 * @brief  Enable ADC, start conversion of regular group with interruption.
01390   * @note   Interruptions enabled in this function according to initialization
01391   *         setting : EOC (end of conversion), EOS (end of sequence),
01392   *         OVR overrun.
01393   *         Each of these interruptions has its dedicated callback function.
01394   * @note   Case of multimode enabled(when multimode feature is available):
01395   *         HAL_ADC_Start_IT() must be called for ADC Slave first, then for
01396   *         ADC Master.
01397   *         For ADC Slave, ADC is enabled only (conversion is not started).
01398   *         For ADC Master, ADC is enabled and multimode conversion is started.
01399   * @note   To guarantee a proper reset of all interruptions once all the needed
01400   *         conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
01401   *         a correct stop of the IT-based conversions.
01402   * @note   By default, HAL_ADC_Start_IT() doesn't enable the End Of Sampling
01403   *         interruption. If required (e.g. in case of oversampling with trigger
01404   *         mode), the user must
01405   *         1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
01406   *         2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP);
01407   *         before calling HAL_ADC_Start_IT().
01408   * @param  hadc: ADC handle
01409   * @retval HAL status
01410   */
01411 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
01412 {
01413   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01414   ADC_TypeDef        *tmpADC_Master;
01415
01416   /* Check the parameters */
01417   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01418
01419   /* Perform ADC enable and conversion start if no conversion is on going */
01420   if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
01421   {
01422     /* Process locked */
01423     __HAL_LOCK(hadc);
01424
01425     /* Enable the ADC peripheral */
01426     tmp_hal_status = ADC_Enable(hadc);
01427
01428     /* Start conversion if ADC is effectively enabled */
01429     if (tmp_hal_status == HAL_OK)
01430     {
01431       /* State machine update: Check if an injected conversion is ongoing */
01432       if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01433       {
01434         /* Reset ADC error code fields related to regular conversions only */
01435         CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA));
01436       }
01437       else
01438       {
01439         /* Set ADC error code to none */
01440         ADC_CLEAR_ERRORCODE(hadc);
01441       }
01442       /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
01443       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
01444
01445       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
01446         - by default if ADC is Master or Independent or if multimode feature is not available
01447         - if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */
01448       if (ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
01449       {
01450         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01451       }
01452
01453       /* Clear regular group conversion flag and overrun flag */
01454       /* (To ensure of no unknown state from potential previous ADC operations) */
01455       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
01456
01457       /* By default, disable all interruptions before enabling the desired ones */
01458       __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
01459
01460       /* Enable required interruptions */
01461       switch(hadc->Init.EOCSelection)
01462       {
01463         case ADC_EOC_SEQ_CONV:
01464            __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
01465           break;
01466         /* case ADC_EOC_SINGLE_CONV */
01467         default:
01468           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
01469           break;
01470       }
01471
01472       /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
01473          ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
01474          behavior and no CPU time is lost for a non-processed interruption */
01475       if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
01476       {
01477         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
01478       }
01479
01480       /* Enable conversion of regular group.                                  */
01481       /* If software start has been selected, conversion starts immediately.  */
01482       /* If external trigger has been selected, conversion starts at next     */
01483       /* trigger event.                                                       */
01484       /* Case of multimode enabled (when multimode feature is available):     */
01485       /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
01486       /*    enabled only (conversion is not started),                         */
01487       /*  - if ADC is master, ADC is enabled and conversion is started.       */
01488       if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)   )
01489       {
01490         /* Multimode feature is not available or ADC Instance is Independent or Master,
01491            or is not Slave ADC with dual regular conversions enabled.
01492            Then set HAL_ADC_STATE_INJ_BUSY and reset HAL_ADC_STATE_INJ_EOC if JAUTO is set. */
01493         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
01494         {
01495           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01496
01497           /* Enable as well injected interruptions in case
01498            HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
01499            allows to start regular and injected conversions when JAUTO is
01500            set with a single call to HAL_ADC_Start_IT() */
01501           switch(hadc->Init.EOCSelection)
01502           {
01503             case ADC_EOC_SEQ_CONV:
01504               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
01505               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
01506               break;
01507             /* case ADC_EOC_SINGLE_CONV */
01508             default:
01509               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
01510               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
01511               break;
01512           }
01513         } /*  if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) */
01514         /* Process unlocked */
01515         __HAL_UNLOCK(hadc);
01516         /* Start ADC */
01517         SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
01518       }
01519       else
01520       {
01521         /* hadc is the handle of a Slave ADC with dual regular conversions
01522            enabled. Therefore, ADC_CR_ADSTART is NOT set */
01523         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01524         /* if Master ADC JAUTO bit is set, Slave injected interruptions
01525            are enabled nevertheless (for same reason as above) */
01526         tmpADC_Master = ADC_MASTER_REGISTER(hadc);
01527         if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET)
01528         {
01529           /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
01530              and in resetting HAL_ADC_STATE_INJ_EOC bit */
01531           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01532           /* Next, set Slave injected interruptions */
01533           switch(hadc->Init.EOCSelection)
01534           {
01535             case ADC_EOC_SEQ_CONV:
01536               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
01537               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
01538               break;
01539             /* case ADC_EOC_SINGLE_CONV */
01540             default:
01541               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
01542               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
01543               break;
01544           }
01545         }  /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */
01546         /* Process unlocked */
01547         __HAL_UNLOCK(hadc);
01548       } /*  if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)   ) */
01549     }  /*  if (tmp_hal_status == HAL_OK) */
01550     else
01551     {
01552       /* Process unlocked */
01553       __HAL_UNLOCK(hadc);
01554     }
01555   }
01556   else
01557   {
01558     tmp_hal_status = HAL_BUSY;
01559   }
01560   /* Return function status */
01561   return tmp_hal_status;
01562 }
01563
01564 /**
01565   * @brief  Stop ADC conversion of regular group (and injected group in
01566   *         case of auto_injection mode), disable interrution of
01567   *         end-of-conversion, disable ADC peripheral.
01568   * @param  hadc: ADC handle
01569   * @retval HAL status.
01570   */
01571 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
01572 {
01573   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01574
01575   /* Check the parameters */
01576   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01577
01578   /* Process locked */
01579   __HAL_LOCK(hadc);
01580
01581   /* 1. Stop potential conversion on going, on ADC groups regular and injected */
01582   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
01583
01584   /* Disable ADC peripheral if conversions are effectively stopped */
01585   if (tmp_hal_status == HAL_OK)
01586   {
01587     /* Disable ADC end of conversion interrupt for regular group */
01588     /* Disable ADC overrun interrupt */
01589     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
01590
01591     /* 2. Disable the ADC peripheral */
01592     tmp_hal_status = ADC_Disable(hadc);
01593
01594     /* Check if ADC is effectively disabled */
01595     if (tmp_hal_status == HAL_OK)
01596     {
01597       /* Set ADC state */
01598       ADC_STATE_CLR_SET(hadc->State,
01599                         (HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY),
01600                         HAL_ADC_STATE_READY);
01601     }
01602   }
01603
01604   /* Process unlocked */
01605   __HAL_UNLOCK(hadc);
01606
01607   /* Return function status */
01608   return tmp_hal_status;
01609 }
01610
01611
01612 /**
01613   * @brief  Enable ADC, start conversion of regular group and transfer result through DMA.
01614   * @note   Interruptions enabled in this function:
01615   *         overrun (if applicable), DMA half transfer, DMA transfer complete.
01616   *         Each of these interruptions has its dedicated callback function.
01617   * @note   Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
01618   *         is designed for single-ADC mode only. For multimode, the dedicated
01619   *         HAL_ADCEx_MultiModeStart_DMA() function must be used.
01620   * @param  hadc: ADC handle
01621   * @param  pData: Destination Buffer address.
01622   * @param  Length: Length of data to be transferred from ADC peripheral to memory (in bytes)
01623   * @retval HAL status.
01624   */
01625 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
01626 {
01627   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01628
01629   /* Check the parameters */
01630   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01631
01632   /* Perform ADC enable and conversion start if no conversion is on going */
01633   if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
01634   {
01635     /* Process locked */
01636     __HAL_LOCK(hadc);
01637
01638     /* Ensure that dual regular conversions are not enabled or unavailable.   */
01639     /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used.  */
01640     if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET)
01641     {
01642       /* Enable the ADC peripheral */
01643       tmp_hal_status = ADC_Enable(hadc);
01644
01645       /* Start conversion if ADC is effectively enabled */
01646       if (tmp_hal_status == HAL_OK)
01647       {
01648         /* State machine update: Check if an injected conversion is ongoing */
01649         if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01650         {
01651           /* Reset ADC error code fields related to regular conversions only */
01652           CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
01653         }
01654         else
01655         {
01656           /* Set ADC error code to none */
01657           ADC_CLEAR_ERRORCODE(hadc);
01658         }
01659         /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
01660         ADC_STATE_CLR_SET(hadc->State,
01661                           (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP),
01662                           HAL_ADC_STATE_REG_BUSY);
01663
01664         /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
01665            - by default if ADC is Master or Independent or if multimode feature is not available
01666            - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
01667         if (ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
01668         {
01669           CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01670         }
01671
01672         /* Set the DMA transfer complete callback */
01673         hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
01674
01675         /* Set the DMA half transfer complete callback */
01676         hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
01677
01678         /* Set the DMA error callback */
01679         hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
01680
01681
01682         /* Manage ADC and DMA start: ADC overrun interruption, DMA start,     */
01683         /* ADC start (in case of SW start):                                   */
01684
01685         /* Clear regular group conversion flag and overrun flag               */
01686         /* (To ensure of no unknown state from potential previous ADC         */
01687         /* operations)                                                        */
01688         __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
01689
01690         /* With DMA, overrun event is always considered as an error even if
01691            hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
01692            ADC_IT_OVR is enabled.  */
01693         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
01694
01695         /* Start the DMA channel */
01696         HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
01697
01698         /* Enable conversion of regular group.                                  */
01699         /* Process unlocked */
01700         __HAL_UNLOCK(hadc);
01701         /* If software start has been selected, conversion starts immediately.  */
01702         /* If external trigger has been selected, conversion will start at next */
01703         /* trigger event.                                                       */
01704         SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
01705       }
01706       else
01707       {
01708         /* Process unlocked */
01709         __HAL_UNLOCK(hadc);
01710       }  /* if (tmp_hal_status == HAL_OK) */
01711     }
01712     else
01713     {
01714       tmp_hal_status = HAL_ERROR;
01715       /* Process unlocked */
01716       __HAL_UNLOCK(hadc);
01717     } /* if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) */
01718
01719   }
01720   else
01721   {
01722     tmp_hal_status = HAL_BUSY;
01723   }
01724
01725   /* Return function status */
01726   return tmp_hal_status;
01727 }
01728
01729
01730 /**
01731   * @brief  Stop ADC conversion of regular group (and injected group in
01732   *         case of auto_injection mode), disable ADC DMA transfer, disable
01733   *         ADC peripheral.
01734   * @note   ADC peripheral disable is forcing stop of potential
01735   *         conversion on injected group. If injected group is under use, it
01736   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
01737   * @note   Case of multimode enabled (when multimode feature is available):
01738   *         HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
01739   *         For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
01740   * @param  hadc: ADC handle
01741   * @retval HAL status.
01742   */
01743 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
01744 {
01745   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01746
01747   /* Check the parameters */
01748   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01749
01750   /* Process locked */
01751   __HAL_LOCK(hadc);
01752
01753   /* 1. Stop potential ADC group regular conversion on going */
01754   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
01755
01756   /* Disable ADC peripheral if conversions are effectively stopped */
01757   if (tmp_hal_status == HAL_OK)
01758   {
01759     /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMNGT is kept) */
01760     MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 |ADC_CFGR_DMNGT_1, 0);
01761
01762     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
01763     /* while DMA transfer is on going)                                        */
01764     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
01765
01766     /* Check if DMA channel effectively disabled */
01767     if (tmp_hal_status != HAL_OK)
01768     {
01769       /* Update ADC state machine to error */
01770       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
01771     }
01772
01773     /* Disable ADC overrun interrupt */
01774     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01775
01776     /* 2. Disable the ADC peripheral */
01777     /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
01778     /* memory a potential failing status.                                     */
01779     if (tmp_hal_status == HAL_OK)
01780     {
01781       tmp_hal_status = ADC_Disable(hadc);
01782     }
01783     else
01784     {
01785       ADC_Disable(hadc);
01786     }
01787
01788     /* Check if ADC is effectively disabled */
01789     if (tmp_hal_status == HAL_OK)
01790     {
01791       /* Set ADC state */
01792       ADC_STATE_CLR_SET(hadc->State,
01793                         (HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY),
01794                         HAL_ADC_STATE_READY);
01795     }
01796
01797   }
01798
01799   /* Process unlocked */
01800   __HAL_UNLOCK(hadc);
01801
01802   /* Return function status */
01803   return tmp_hal_status;
01804 }
01805
01806
01807 /**
01808   * @brief  Get ADC regular group conversion result.
01809   * @note   Reading register DR automatically clears ADC flag EOC
01810   *         (ADC group regular end of unitary conversion).
01811   * @note   This function does not clear ADC flag EOS
01812   *         (ADC group regular end of sequence conversion).
01813   *         Occurrence of flag EOS rising:
01814   *          - If sequencer is composed of 1 rank, flag EOS is equivalent
01815   *            to flag EOC.
01816   *          - If sequencer is composed of several ranks, during the scan
01817   *            sequence flag EOC only is raised, at the end of the scan sequence
01818   *            both flags EOC and EOS are raised.
01819   *         To clear this flag, either use function:
01820   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
01821   *         model polling: @ref HAL_ADC_PollForConversion()
01822   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
01823   * @param  hadc: ADC handle
01824   * @retval ADC group regular conversion data
01825   */
01826 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
01827 {
01828   /* Check the parameters */
01829   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01830
01831   /* Note: EOC flag is not cleared here by software because automatically     */
01832   /*       cleared by hardware when reading register DR.                      */
01833
01834   /* Return ADC converted value */
01835   return hadc->Instance->DR;
01836 }
01837
01838
01839 /**
01840   * @brief  Handle ADC interrupt request.
01841   * @param  hadc: ADC handle
01842   * @retval None
01843   */
01844 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
01845 {
01846   uint32_t overrun_error = 0; /* flag set if overrun occurrence has to be considered as an error */
01847   ADC_Common_TypeDef *tmpADC_Common;
01848   ADC_TypeDef        *tmpADC_Master;
01849   uint32_t tmp_isr      = hadc->Instance->ISR;
01850   uint32_t tmp_ier      = hadc->Instance->IER;
01851   uint32_t tmp_cfgr     = 0x0;
01852   uint32_t tmp_cfgr_jqm = 0x0;
01853
01854
01855   /* Check the parameters */
01856   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01857   assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
01858
01859
01860   /* ====== Check End of Sampling flag for regular group ===== */
01861   if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
01862   {
01863     /* Update state machine on end of sampling status if not in error state */
01864     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
01865     {
01866       /* Set ADC state */
01867       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
01868     }
01869
01870     /* End Of Sampling callback */
01871     HAL_ADCEx_EndOfSamplingCallback(hadc);
01872
01873     /* Clear regular group conversion flag */
01874     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP );
01875   }
01876
01877   /* ====== Check End of Conversion or Sequence flags for regular group ===== */
01878   if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
01879       (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS))  )
01880   {
01881     /* Update state machine on conversion status if not in error state */
01882     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
01883     {
01884       /* Set ADC state */
01885       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
01886     }
01887
01888     /* Disable interruption if no further conversion upcoming by regular      */
01889     /* external trigger or by continuous mode,                                */
01890     /* and if scan sequence if completed.                                     */
01891     if(ADC_IS_SOFTWARE_START_REGULAR(hadc))
01892     {
01893       if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
01894       {
01895         /* check CONT bit directly in handle ADC CFGR register */
01896         tmp_cfgr = READ_REG(hadc->Instance->CFGR);
01897       }
01898       else
01899       {
01900         /* else need to check Master ADC CONT bit */
01901         tmpADC_Master = ADC_MASTER_REGISTER(hadc);
01902         tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
01903       }
01904
01905       /* Carry on if continuous mode is disabled */
01906       if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
01907       {
01908         /* If End of Sequence is reached, disable interrupts */
01909         if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
01910         {
01911           /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit           */
01912           /* ADSTART==0 (no conversion on going)                                */
01913           if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
01914           {
01915             /* Disable ADC end of sequence conversion interrupt */
01916             /* Note: if Overrun interrupt was enabled with EOC or EOS interrupt */
01917             /* in HAL_Start_IT(), it isn't disabled here because it can be used */
01918             /* by overrun IRQ process below.                                    */
01919             __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
01920             /* Clear HAL_ADC_STATE_REG_BUSY bit */
01921             CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01922             /* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */
01923             if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01924             {
01925               SET_BIT(hadc->State, HAL_ADC_STATE_READY);
01926             }
01927           }
01928           else
01929           {
01930             /* Change ADC state to error state */
01931             SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
01932
01933             /* Set ADC error code to ADC IP internal error */
01934             SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
01935           }
01936         }
01937       } /* if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) */
01938     } /* if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   */
01939
01940     /* Conversion complete callback */
01941     /* Note:  HAL_ADC_ConvCpltCallback can resort to
01942               if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) or
01943               if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOC)) to determine whether
01944               interruption has been triggered by end of conversion or end of
01945               sequence.    */
01946     HAL_ADC_ConvCpltCallback(hadc);
01947
01948
01949     /* Clear regular group conversion flag */
01950     __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
01951   }
01952
01953
01954   /* ========== Check End of Conversion flag for injected group ========== */
01955   if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
01956       (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS))  )
01957   {
01958     /* Update state machine on conversion status if not in error state */
01959     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
01960     {
01961       /* Set ADC state */
01962       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
01963     }
01964
01965
01966     /* Check whether interruptions can be disabled only if
01967         - injected conversions are software-triggered when injected queue management is disabled
01968         OR
01969         - auto-injection is enabled, continuous mode is disabled (CONT = 0)
01970           and regular conversions are software-triggered */
01971           /* If End of Sequence is reached, disable interrupts */
01972     if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
01973     {
01974
01975       /* First, retrieve proper registers to check */
01976       /* 1a. Are injected conversions that of a dual Slave ? */
01977       if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
01978       {
01979         /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
01980            check JQM bit directly in ADC CFGR register */
01981         tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR);
01982       }
01983       else
01984       {
01985         /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
01986            need to check JQM bit of Master ADC CFGR register */
01987         tmpADC_Master = ADC_MASTER_REGISTER(hadc);
01988         tmp_cfgr_jqm = READ_REG(tmpADC_Master->CFGR);
01989       }
01990       /* 1b. Is hadc the handle of a Slave ADC with regular conversions enabled? */
01991       if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
01992       {
01993         /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
01994            check JAUTO and CONT bits directly in ADC CFGR register */
01995         tmp_cfgr = READ_REG(hadc->Instance->CFGR);
01996       }
01997       else
01998       {
01999         /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
02000            check JAUTO and CONT bits of Master ADC CFGR register */
02001         tmpADC_Master = ADC_MASTER_REGISTER(hadc);
02002         tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
02003       }
02004
02005       /* Secondly, check whether JEOC and JEOS interruptions can be disabled */
02006       if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) != ADC_CFGR_JQM))
02007            && (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) &&
02008              (ADC_IS_SOFTWARE_START_REGULAR(hadc))))    )
02009       {
02010         /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit         */
02011         /* JADSTART==0 (no conversion on going)                               */
02012         if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
02013         {
02014           /* Disable ADC end of sequence conversion interrupt  */
02015           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
02016           /* Clear HAL_ADC_STATE_INJ_BUSY bit */
02017           CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
02018           /* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */
02019           if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
02020           {
02021             SET_BIT(hadc->State, HAL_ADC_STATE_READY);
02022           }
02023         }
02024         else
02025         {
02026           /* Change ADC state to error state */
02027           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02028
02029           /* Set ADC error code to ADC IP internal error */
02030           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02031         }
02032       }
02033     } /* if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) */
02034
02035     /* Injected Conversion complete callback */
02036     /* Note:  HAL_ADCEx_InjectedConvCpltCallback can resort to
02037               if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
02038               if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
02039               interruption has been triggered by end of conversion or end of
02040               sequence.    */
02041     HAL_ADCEx_InjectedConvCpltCallback(hadc);
02042
02043     /* Clear injected group conversion flag */
02044     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
02045   }
02046
02047
02048   /* ========== Check Analog watchdog flag =================================================== */
02049
02050   /* ========== Check Analog watchdog 1 flag ========== */
02051   if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
02052   {
02053     /* Set ADC state */
02054     SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
02055
02056     /* Level out of window 1 callback */
02057     HAL_ADC_LevelOutOfWindowCallback(hadc);
02058     /* Clear ADC Analog watchdog flag */
02059     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
02060   }
02061
02062   /* ========== Check Analog watchdog 2 flag ========== */
02063   if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
02064   {
02065     /* Set ADC state */
02066     SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
02067
02068     /* Level out of window 2 callback */
02069     HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
02070     /* Clear ADC Analog watchdog flag */
02071     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
02072   }
02073
02074   /* ========== Check Analog watchdog 3 flag ========== */
02075   if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
02076   {
02077     /* Set ADC state */
02078     SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
02079
02080     /* Level out of window 3 callback */
02081     HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
02082     /* Clear ADC Analog watchdog flag */
02083     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
02084   }
02085
02086
02087   /* ========== Check Overrun flag ========== */
02088   if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
02089   {
02090     /* If overrun is set to overwrite previous data (default setting),        */
02091     /* overrun event is not considered as an error.                           */
02092     /* (cf ref manual "Managing conversions without using the DMA and without */
02093     /* overrun ")                                                             */
02094     /* Exception for usage with DMA overrun event always considered as an     */
02095     /* error.                                                                 */
02096
02097     if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
02098     {
02099       overrun_error = 1;
02100     }
02101     else
02102     {
02103       /* Pointer to the common control register */
02104       if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
02105       {
02106         /* Pointer to the common control register                                 */
02107         tmpADC_Common = ADC12_COMMON_REGISTER(hadc);
02108       }
02109       else
02110       {
02111         /* Pointer to the common control register                                 */
02112         tmpADC_Common = ADC3_COMMON_REGISTER(hadc);
02113       }
02114       /* check DMA configuration, depending on MultiMode set or not */
02115       if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)
02116       {
02117         if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0))
02118         {
02119           overrun_error = 1;
02120         }
02121       }
02122       else
02123       {
02124         /* MultiMode is enabled, Common Control Register DAMDF bits must be checked */
02125         if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF) != RESET)
02126         {
02127           overrun_error = 1;
02128         }
02129       }
02130     }
02131
02132     if (overrun_error == 1)
02133     {
02134       /* Change ADC state to error state */
02135       SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
02136
02137       /* Set ADC error code to overrun */
02138       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
02139
02140       /* Error callback */
02141       HAL_ADC_ErrorCallback(hadc);
02142     }
02143
02144     /* Clear the Overrun flag, to be done AFTER HAL_ADC_ErrorCallback() since
02145        old data is preserved until OVR is reset */
02146     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
02147
02148   }
02149
02150   /* ========== Check Injected context queue overflow flag ========== */
02151   if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
02152   {
02153     /* Change ADC state to overrun state */
02154     SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
02155
02156     /* Set ADC error code to Injected context queue overflow */
02157     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
02158
02159     /* Clear the Injected context queue overflow flag */
02160     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
02161
02162     /* Error callback */
02163     HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
02164   }
02165
02166 }
02167
02168 /**
02169   * @brief  Conversion complete callback in non-blocking mode
02170   * @param  hadc: ADC handle
02171   * @retval None
02172   */
02173 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
02174 {
02175   /* Prevent unused argument(s) compilation warning */
02176   UNUSED(hadc);
02177
02178   /* NOTE : This function should not be modified. When the callback is needed,
02179             function HAL_ADC_ConvCpltCallback must be implemented in the user file.
02180    */
02181 }
02182
02183 /**
02184   * @brief  Conversion DMA half-transfer callback in non-blocking mode
02185   * @param  hadc: ADC handle
02186   * @retval None
02187   */
02188 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
02189 {
02190   /* Prevent unused argument(s) compilation warning */
02191   UNUSED(hadc);
02192
02193   /* NOTE : This function should not be modified. When the callback is needed,
02194             function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
02195   */
02196 }
02197
02198 /**
02199   * @brief  Analog watchdog 1 callback in non-blocking mode.
02200   * @param  hadc: ADC handle
02201   * @retval None
02202   */
02203 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
02204 {
02205   /* Prevent unused argument(s) compilation warning */
02206   UNUSED(hadc);
02207
02208   /* NOTE : This function should not be modified. When the callback is needed,
02209             function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
02210   */
02211 }
02212
02213 /**
02214   * @brief  ADC error callback in non-blocking mode
02215   *         (ADC conversion with interruption or transfer by DMA).
02216   * @note   In case of error due to overrun when using ADC with DMA transfer
02217   *         (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
02218   *         - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
02219   *         - If needed, restart a new ADC conversion using function
02220   *           "HAL_ADC_Start_DMA()"
02221   *           (this function is also clearing overrun flag)
02222   * @param  hadc: ADC handle
02223   * @retval None
02224   */
02225 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
02226 {
02227   /* Prevent unused argument(s) compilation warning */
02228   UNUSED(hadc);
02229
02230   /* NOTE : This function should not be modified. When the callback is needed,
02231             function HAL_ADC_ErrorCallback must be implemented in the user file.
02232   */
02233 }
02234
02235 /**
02236   * @}
02237   */
02238
02239 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
02240   * @brief    Peripheral Control functions
02241   *
02242 @verbatim
02243  ===============================================================================
02244              ##### Peripheral Control functions #####
02245  ===============================================================================
02246     [..] This section provides functions allowing to:
02247       (+) Configure channels on regular group
02248       (+) Configure the analog watchdog
02249
02250 @endverbatim
02251   * @{
02252   */
02253
02254
02255 /**
02256   * @brief  Configure a channel to be assigned to ADC group regular.
02257   * @note   In case of usage of internal measurement channels:
02258   *         Vbat/VrefInt/TempSensor.
02259   *         These internal paths can be disabled using function
02260   *         HAL_ADC_DeInit().
02261   * @note   Possibility to update parameters on the fly:
02262   *         This function initializes channel into ADC group regular,
02263   *         following calls to this function can be used to reconfigure
02264   *         some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
02265   *         without resetting the ADC.
02266   *         The setting of these parameters is conditioned to ADC state:
02267   *         Refer to comments of structure "ADC_ChannelConfTypeDef".
02268   * @param  hadc: ADC handle
02269   * @param  sConfig: Structure of ADC channel assigned to ADC group regular.
02270   * @retval HAL status
02271   */
02272 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
02273 {
02274   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
02275
02276   ADC_Common_TypeDef *tmpADC_Common;
02277   uint32_t tmpOffsetShifted;
02278   __IO uint32_t wait_loop_index = 0;
02279
02280   /* Check the parameters */
02281   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02282   assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
02283   assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
02284   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
02285   assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
02286
02287   /* Check offset range according to oversampling setting */
02288   if (hadc->Init.OversamplingMode == ENABLE)
02289   {
02290     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset/(hadc->Init.Oversampling.Ratio+1U)));
02291   }
02292   else
02293   {
02294     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
02295   }
02296
02297   /* Verification of channel number */
02298   if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
02299   {
02300      assert_param(IS_ADC_CHANNEL(sConfig->Channel));
02301   }
02302   else
02303   {
02304     if (hadc->Instance == ADC3)
02305     {
02306       assert_param(IS_ADC3_DIFF_CHANNEL(sConfig->Channel));
02307     }
02308     else if (hadc->Instance == ADC1)
02309     {
02310       assert_param(IS_ADC1_DIFF_CHANNEL(sConfig->Channel));
02311     }
02312     else
02313     {
02314       assert_param(IS_ADC2_DIFF_CHANNEL(sConfig->Channel));
02315     }
02316   }
02317
02318   /* Process locked */
02319   __HAL_LOCK(hadc);
02320
02321
02322   /* Parameters update conditioned to ADC state:                              */
02323   /* Parameters that can be updated when ADC is disabled or enabled without   */
02324   /* conversion on going on regular group:                                    */
02325   /*  - Channel number                                                        */
02326   /*  - Channel rank                                                          */
02327   /*  - Preselection of ADC inputs                                            */
02328   if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
02329   {
02330     /* ADC channels preselction */
02331     hadc->Instance->PCSEL |= (1U << sConfig->Channel);
02332
02333     /* Regular sequence configuration */
02334     /* Clear the old SQx bits then set the new ones for the selected rank */
02335     /* For Rank 1 to 4 */
02336     if (sConfig->Rank < 5)
02337     {
02338       MODIFY_REG(hadc->Instance->SQR1,
02339                 ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank),
02340                 ADC_SQR1_RK(sConfig->Channel, sConfig->Rank));
02341     }
02342     /* For Rank 5 to 9 */
02343     else if (sConfig->Rank < 10)
02344     {
02345       MODIFY_REG(hadc->Instance->SQR2,
02346                 ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank),
02347                 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank));
02348     }
02349     /* For Rank 10 to 14 */
02350     else if (sConfig->Rank < 15)
02351     {
02352       MODIFY_REG(hadc->Instance->SQR3,
02353                 ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank),
02354                 ADC_SQR3_RK(sConfig->Channel, sConfig->Rank));
02355     }
02356     /* For Rank 15 to 16 */
02357     else
02358     {
02359       MODIFY_REG(hadc->Instance->SQR4,
02360                 ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank),
02361                 ADC_SQR4_RK(sConfig->Channel, sConfig->Rank));
02362     }
02363
02364
02365     /* Parameters update conditioned to ADC state:                              */
02366     /* Parameters that can be updated when ADC is disabled or enabled without   */
02367     /* conversion on going on regular group:                                    */
02368     /*  - Channel sampling time                                                 */
02369     /*  - Channel offset                                                        */
02370     if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
02371     {
02372
02373       /* Channel sampling time configuration */
02374       /* Clear the old sample time then set the new one for the selected channel */
02375       /* For channels 10 to 18 */
02376       if (sConfig->Channel >= ADC_CHANNEL_10)
02377       {
02378         MODIFY_REG(hadc->Instance->SMPR2,
02379                   ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel),
02380                   ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel));
02381       }
02382       else /* For channels 0 to 9 */
02383       {
02384         MODIFY_REG(hadc->Instance->SMPR1,
02385                   ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel),
02386                   ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel));
02387       }
02388
02389
02390       /* Configure the offset: offset enable/disable, channel, offset value, Signed saturation feature */
02391
02392       /* Shift the offset in function of the selected ADC resolution. */
02393       /* Offset has to be left-aligned on bit 15, the LSB (right bits) are set to 0 */
02394       tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
02395
02396       switch (sConfig->OffsetNumber)
02397       {
02398          /* Configure offset register i when applicable:                         */
02399          /* - Enable offset                                                      */
02400          /* - Set channel number                                                 */
02401          /* - Set offset value                                                   */
02402          /* - Set Right shift after offset application                           */
02403         case ADC_OFFSET_1:
02404            MODIFY_REG(hadc->Instance->OFR1,
02405                    ADC_OFR_FIELDS,
02406                    ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);
02407            MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_RSHIFT1, sConfig->OffsetRightShift);
02408            /* Enable or disable the signed saturation bit */
02409            if(sConfig->OffsetSignedSaturation != DISABLE)
02410            {
02411               SET_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
02412            }
02413            else
02414            {
02415              CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
02416            }
02417           break;
02418
02419         case ADC_OFFSET_2:
02420           MODIFY_REG(hadc->Instance->OFR2,
02421                    ADC_OFR_FIELDS,
02422                    ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);
02423           MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_RSHIFT2, (sConfig->OffsetRightShift)<<1);
02424           /* Enable or disable the signed saturation bit */
02425            if(sConfig->OffsetSignedSaturation != DISABLE)
02426            {
02427               SET_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE);
02428            }
02429            else
02430            {
02431              CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE);
02432            }
02433           break;
02434
02435         case ADC_OFFSET_3:
02436           MODIFY_REG(hadc->Instance->OFR3,
02437                    ADC_OFR_FIELDS,
02438                    ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);
02439           MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_RSHIFT3, (sConfig->OffsetRightShift)<<2);
02440           /* Enable or disable the signed saturation bit */
02441            if(sConfig->OffsetSignedSaturation != DISABLE)
02442            {
02443               SET_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE);
02444            }
02445            else
02446            {
02447              CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE);
02448            }
02449           break;
02450
02451         case ADC_OFFSET_4:
02452           MODIFY_REG(hadc->Instance->OFR4,
02453                    ADC_OFR_FIELDS,
02454                    ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);
02455           MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_RSHIFT4, (sConfig->OffsetRightShift)<<3);
02456           /* Enable or disable the signed saturation bit */
02457           if(sConfig->OffsetSignedSaturation != DISABLE)
02458           {
02459             SET_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
02460           }
02461           else
02462           {
02463             CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
02464           }
02465           break;
02466
02467         /* Case ADC_OFFSET_NONE */
02468         default :
02469         /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled.
02470            If this is the case, offset OFRx is disabled since
02471            sConfig->OffsetNumber = ADC_OFFSET_NONE. */
02472           if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
02473           {
02474             CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
02475           }
02476           if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
02477           {
02478             CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE);
02479           }
02480           if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
02481           {
02482             CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE);
02483           }
02484           if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
02485           {
02486             CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
02487           }
02488           break;
02489       }  /*  switch (sConfig->OffsetNumber) */
02490
02491     }  /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
02492
02493
02494
02495     /* Parameters update conditioned to ADC state:                              */
02496     /* Parameters that can be updated only when ADC is disabled:                */
02497     /*  - Single or differential mode                                           */
02498     /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
02499     if (ADC_IS_ENABLE(hadc) == RESET)
02500     {
02501       /* Configuration of differential mode */
02502       if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
02503       {
02504         /* Disable differential mode (default mode: single-ended) */
02505         CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
02506       }
02507       else
02508       {
02509         /* Enable differential mode */
02510         SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
02511
02512         /* Sampling time configuration of channel ADC_IN+1 (negative input)     */
02513         /* Clear the old sample time then set the new one for the selected      */
02514         /* channel.                                                             */
02515         /* For channels 9 to 15 (ADC1, ADC2) or to 11 (ADC3), SMPR2 register
02516            must be configured */
02517         if (sConfig->Channel >= ADC_CHANNEL_9)
02518         {
02519           MODIFY_REG(hadc->Instance->SMPR2,
02520                   ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel +1),
02521                   ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel +1));
02522         }
02523         else /* For channels 0 to 8, SMPR1 must be configured */
02524         {
02525           MODIFY_REG(hadc->Instance->SMPR1,
02526               ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel +1),
02527                ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel +1));
02528         }
02529       }
02530       /* Management of internal measurement channels: Vbat/VrefInt/TempSensor.  */
02531       /* If internal channel selected, enable dedicated internal buffers and    */
02532       /*  paths.                                                                */
02533       /* Note: these internal measurement paths can be disabled using           */
02534       /* HAL_ADC_DeInit().                                                      */
02535
02536       /* Configuration of common ADC parameters                                 */
02537       if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
02538       {
02539         /* Pointer to the common control register                                 */
02540         tmpADC_Common = ADC12_COMMON_REGISTER(hadc);
02541       }
02542       else
02543       {
02544         /* Pointer to the common control register                                 */
02545         tmpADC_Common = ADC3_COMMON_REGISTER(hadc);
02546       }
02547
02548       /* If the requested internal measurement path has already been enabled,   */
02549       /* bypass the configuration processing.                                   */
02550       if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
02551             (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN))            ) ||
02552           ( (sConfig->Channel == ADC_CHANNEL_VBAT_DIV4)       &&
02553             (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN))          ) ||
02554           ( (sConfig->Channel == ADC_CHANNEL_VREFINT)    &&
02555             (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
02556          )
02557       {
02558         /* Configuration of common ADC parameters (continuation)                */
02559
02560         /* Software is allowed to change common parameters only when all ADCs   */
02561         /* of the common group are disabled.                                    */
02562         if ((ADC_IS_ENABLE(hadc) == RESET)   &&
02563            (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
02564         {
02565           /* Enable Temperature sensor measurement path (channel 18)            */
02566           /* Note: Temp. sensor internal channels available on ADC3    */
02567           if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((hadc->Instance == ADC3)))
02568           {
02569              SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
02570
02571             /* Wait loop initialization and execution */
02572             /* Note: Variable divided by 2 to compensate partially          */
02573             /*       CPU processing cycles.                                 */
02574             wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / (1000000 * 2)));
02575             while(wait_loop_index != 0)
02576             {
02577               wait_loop_index--;
02578             }
02579           }
02580           /* If Channel 18 is selected, enable VBAT measurement path.           */
02581           /* Note: VBAT internal internal channels available on ADC1 and ADC3   */
02582           else if ((sConfig->Channel == ADC_CHANNEL_VBAT_DIV4) && ((hadc->Instance == ADC3)))
02583           {
02584             SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
02585           }
02586           /* If Channel 19 is selected, enable VREFINT measurement path          */
02587           /* Note: VBAT internal internal channels available on ADC1 only       */
02588           else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && (hadc->Instance == ADC3))
02589           {
02590             SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
02591           }
02592         }
02593         /* If the requested internal measurement path has already been          */
02594         /* enabled and other ADC of the common group are enabled, internal      */
02595         /* measurement paths cannot be enabled.                                 */
02596         else
02597         {
02598           /* Update ADC state machine to error */
02599           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02600
02601           tmp_hal_status = HAL_ERROR;
02602         }
02603       }
02604
02605     } /* if (ADC_IS_ENABLE(hadc) == RESET) */
02606
02607   } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) */
02608
02609   /* If a conversion is on going on regular group, no update on regular       */
02610   /* channel could be done on neither of the channel configuration structure  */
02611   /* parameters.                                                              */
02612   else
02613   {
02614     /* Update ADC state machine to error */
02615     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02616
02617     tmp_hal_status = HAL_ERROR;
02618   }
02619
02620   /* Process unlocked */
02621   __HAL_UNLOCK(hadc);
02622
02623   /* Return function status */
02624   return tmp_hal_status;
02625 }
02626
02627
02628 /**
02629   * @brief  Configure the analog watchdog.
02630   * @note   Possibility to update parameters on the fly:
02631   *         This function initializes the selected analog watchdog, successive
02632   *         calls to this function can be used to reconfigure some parameters
02633   *         of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
02634   *         the ADC.
02635   *         The setting of these parameters is conditioned to ADC state.
02636   *         For parameters constraints, see comments of structure
02637   *         "ADC_AnalogWDGConfTypeDef".
02638   * @note   Analog watchdog thresholds can be modified while ADC conversion
02639   *         is on going.
02640   *         In this case, some constraints must be taken into account:
02641   *         the programmed threshold values are effective from the next
02642   *         ADC EOC (end of unitary conversion).
02643   *         Considering that registers write delay may happen due to
02644   *         bus activity, this might cause an uncertainty on the
02645   *         effective timing of the new programmed threshold values.
02646   * @param  hadc: ADC handle
02647   * @param  AnalogWDGConfig: Structure of ADC analog watchdog configuration
02648   * @retval HAL status
02649   */
02650 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
02651 {
02652   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
02653
02654   uint32_t tmpAWDHighThresholdShifted;
02655   uint32_t tmpAWDLowThresholdShifted;
02656
02657   uint32_t tmpADCFlagAWD2orAWD3;
02658   uint32_t tmpADCITAWD2orAWD3;
02659
02660   /* Check the parameters */
02661   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02662   assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
02663   assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
02664   assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
02665
02666   if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)     ||
02667      (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC)   ||
02668      (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  )
02669   {
02670     assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
02671   }
02672
02673
02674   /* Verify if threshold is within the selected ADC resolution */
02675   /* Check threshold range according to oversampling setting */
02676   if (hadc->Init.OversamplingMode == ENABLE)
02677   {
02678     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold/(hadc->Init.Oversampling.Ratio+1U)));
02679     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold/(hadc->Init.Oversampling.Ratio+1U)));
02680   }
02681   else
02682   {
02683     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
02684     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
02685   }
02686
02687   /* Process locked */
02688   __HAL_LOCK(hadc);
02689
02690   /* Parameters update conditioned to ADC state:                              */
02691   /* Parameters that can be updated when ADC is disabled or enabled without   */
02692   /* conversion on going on regular and injected groups:                      */
02693   /*  - Analog watchdog channels                                              */
02694   /*  - Analog watchdog thresholds                                            */
02695   if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
02696   {
02697
02698     /* Analog watchdogs configuration */
02699     if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
02700     {
02701       /* Configuration of analog watchdog:                                    */
02702       /*  - Set the analog watchdog enable mode: regular and/or injected      */
02703       /*    groups, one or overall group of channels.                         */
02704       /*  - Set the Analog watchdog channel (is not used if watchdog          */
02705       /*    mode "all channels": ADC_CFGR_AWD1SGL=0).                         */
02706
02707       MODIFY_REG(hadc->Instance->CFGR,  ADC_CFGR_WD_FIELDS,
02708             AnalogWDGConfig->WatchdogMode | ADC_CFGR_SET_AWD1CH(AnalogWDGConfig->Channel) );
02709
02710       /* Shift the offset with respect to the selected ADC resolution:        */
02711       /* Thresholds have to be left-aligned on bit 15, the LSB (right bits)   */
02712       /* are set to 0                                                         */
02713       tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
02714       tmpAWDLowThresholdShifted  = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
02715
02716      /* Set the high and low thresholds */
02717       MODIFY_REG(hadc->Instance->LTR1,  ADC_LTR2_LT2 , tmpAWDLowThresholdShifted);
02718       MODIFY_REG(hadc->Instance->HTR1,  ADC_HTR2_HT2 , tmpAWDHighThresholdShifted);
02719
02720       /* Clear the ADC Analog watchdog flag (in case left enabled by          */
02721       /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
02722       /* or HAL_ADC_PollForEvent().                                           */
02723       __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1);
02724
02725       /* Configure ADC Analog watchdog interrupt */
02726       if(AnalogWDGConfig->ITMode == ENABLE)
02727       {
02728         /* Enable the ADC Analog watchdog interrupt */
02729         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1);
02730       }
02731       else
02732       {
02733         /* Disable the ADC Analog watchdog interrupt */
02734         __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1);
02735       }
02736
02737       /* Update state, clear previous result related to AWD1 */
02738       CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
02739     }
02740     /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
02741     else
02742     {
02743     /* Shift the threshold with respect to the selected ADC resolution         */
02744     /* have to be left-aligned on bit 15, the LSB (right bits) are set to 0    */
02745       tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
02746       tmpAWDLowThresholdShifted  = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
02747
02748       if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
02749       {
02750         /* Set the Analog watchdog channel or group of channels. This also    */
02751         /* enables the watchdog.                                              */
02752         /* Note: Conditional register reset, because several channels can be  */
02753         /*       set by successive calls of this function.                    */
02754         if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
02755         {
02756           SET_BIT(hadc->Instance->AWD2CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
02757         }
02758         else
02759         {
02760           CLEAR_BIT(hadc->Instance->AWD2CR,  ADC_AWD2CR_AWD2CH);
02761         }
02762
02763         /* Set the high and low thresholds */
02764         MODIFY_REG(hadc->Instance->HTR2,  ADC_HTR2_HT2, tmpAWDHighThresholdShifted);
02765         MODIFY_REG(hadc->Instance->LTR2,  ADC_LTR2_LT2, tmpAWDLowThresholdShifted);
02766
02767
02768         /* Set temporary variable to flag and IT of AWD2 or AWD3 for further  */
02769         /* settings.                                                          */
02770         tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2;
02771         tmpADCITAWD2orAWD3 = ADC_IT_AWD2;
02772
02773         /* Update state, clear previous result related to AWD2 */
02774         CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
02775       }
02776       /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
02777       else
02778       {
02779         /* Set the Analog watchdog channel or group of channels. This also    */
02780         /* enables the watchdog.                                              */
02781         /* Note: Conditional register reset, because several channels can be  */
02782         /*       set by successive calls of this function.                    */
02783         if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
02784         {
02785           SET_BIT(hadc->Instance->AWD3CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
02786         }
02787         else
02788         {
02789           CLEAR_BIT(hadc->Instance->AWD3CR,  ADC_AWD3CR_AWD3CH);
02790         }
02791
02792         /* Set the high and low thresholds */
02793         MODIFY_REG(hadc->Instance->HTR3,  ADC_HTR3_HT3, tmpAWDHighThresholdShifted);
02794         MODIFY_REG(hadc->Instance->LTR3,  ADC_LTR3_LT3, tmpAWDLowThresholdShifted);
02795         /* Set temporary variable to flag and IT of AWD2 or AWD3 for further  */
02796         /* settings.                                                          */
02797         tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3;
02798         tmpADCITAWD2orAWD3 = ADC_IT_AWD3;
02799
02800         /* Update state, clear previous result related to AWD3 */
02801         CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
02802       }
02803
02804       /* Clear the ADC Analog watchdog flag (in case left enabled by          */
02805       /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
02806       /* or HAL_ADC_PollForEvent().                                           */
02807       __HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3);
02808
02809       /* Configure ADC Analog watchdog interrupt */
02810       if(AnalogWDGConfig->ITMode == ENABLE)
02811       {
02812         __HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3);
02813       }
02814       else
02815       {
02816         __HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3);
02817       }
02818     }
02819
02820   }
02821   /* If a conversion is on going on regular or injected groups, no update     */
02822   /* could be done on neither of the AWD configuration structure parameters.  */
02823   else
02824   {
02825     /* Update ADC state machine to error */
02826     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02827
02828     tmp_hal_status = HAL_ERROR;
02829   }
02830
02831
02832   /* Process unlocked */
02833   __HAL_UNLOCK(hadc);
02834
02835
02836   /* Return function status */
02837   return tmp_hal_status;
02838 }
02839
02840
02841 /**
02842   * @}
02843   */
02844
02845 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
02846   * @brief   ADC Peripheral State functions
02847   *
02848 @verbatim
02849  ===============================================================================
02850             ##### Peripheral state and errors functions #####
02851  ===============================================================================
02852     [..] This subsection provides functions to get in run-time the status of the
02853     peripheral.
02854       (+) Check the ADC state
02855       (+) Check the ADC error code
02856
02857 @endverbatim
02858   * @{
02859   */
02860
02861 /**
02862   * @brief  Return the ADC handle state.
02863   * @note   ADC state machine is managed by bitfields, ADC status must be
02864   *         compared with states bits.
02865   *         For example:
02866   *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
02867   *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)    ) "
02868   * @param  hadc: ADC handle
02869   * @retval ADC handle state (bitfield on 32 bits)
02870   */
02871 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
02872 {
02873   /* Check the parameters */
02874   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02875
02876   /* Return ADC Handle state */
02877   return hadc->State;
02878 }
02879
02880
02881 /**
02882   * @brief  Return the ADC error code.
02883   * @param  hadc: ADC handle
02884   * @retval ADC error code (bitfield on 32 bits)
02885   */
02886 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
02887 {
02888   /* Check the parameters */
02889   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02890
02891   return hadc->ErrorCode;
02892 }
02893 /**
02894   * @}
02895   */
02896
02897 /**
02898   * @}
02899   */
02900
02901 /** @defgroup ADC_Private_Functions ADC Private Functions
02902   * @{
02903   */
02904
02905 /**
02906   * @brief  Stop ADC conversion.
02907   * @param  hadc: ADC handle
02908   * @param  ConversionGroup: ADC group regular and/or injected.
02909   *          This parameter can be one of the following values:
02910   *            @arg ADC_REGULAR_GROUP           ADC regular conversion type.
02911   *            @arg ADC_INJECTED_GROUP          ADC injected conversion type.
02912   *            @arg ADC_REGULAR_INJECTED_GROUP  ADC regular and injected conversion type.
02913   * @retval HAL status.
02914   */
02915 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup)
02916 {
02917   uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0;
02918   uint32_t tickstart = 0;
02919   uint32_t Conversion_Timeout_CPU_cycles = 0;
02920
02921   /* Check the parameters */
02922   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02923   assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
02924
02925   /* Verification if ADC is not already stopped (on regular and injected      */
02926   /* groups) to bypass this function if not needed.                           */
02927   if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc))
02928   {
02929     /* Particular case of continuous auto-injection mode combined with        */
02930     /* auto-delay mode.                                                       */
02931     /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not   */
02932     /* injected group stop ADC_CR_JADSTP).                                    */
02933     /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1   */
02934     /* (see reference manual).                                                */
02935     if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
02936          && (hadc->Init.ContinuousConvMode==ENABLE)
02937          && (hadc->Init.LowPowerAutoWait==ENABLE))
02938     {
02939       /* Use stop of regular group */
02940       ConversionGroup = ADC_REGULAR_GROUP;
02941
02942       /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
02943       while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET)
02944       {
02945         if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4))
02946         {
02947           /* Update ADC state machine to error */
02948           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02949
02950           /* Set ADC error code to ADC IP internal error */
02951           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02952
02953           return HAL_ERROR;
02954         }
02955         Conversion_Timeout_CPU_cycles ++;
02956       }
02957
02958       /* Clear JEOS */
02959       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
02960     }
02961
02962     /* Stop potential conversion on going on regular group */
02963     if (ConversionGroup != ADC_INJECTED_GROUP)
02964     {
02965       /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
02966       if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
02967           HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS)     )
02968       {
02969         /* Stop conversions on regular group */
02970         SET_BIT(hadc->Instance->CR, ADC_CR_ADSTP);
02971       }
02972     }
02973
02974     /* Stop potential conversion on going on injected group */
02975     if (ConversionGroup != ADC_REGULAR_GROUP)
02976     {
02977       /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
02978       if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) &&
02979           HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS)      )
02980       {
02981         /* Stop conversions on injected group */
02982         SET_BIT(hadc->Instance->CR, ADC_CR_JADSTP);
02983       }
02984     }
02985
02986     /* Selection of start and stop bits with respect to the regular or injected group */
02987     switch(ConversionGroup)
02988     {
02989       case ADC_REGULAR_INJECTED_GROUP:
02990         tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
02991         break;
02992       case ADC_INJECTED_GROUP:
02993         tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
02994         break;
02995       /* Case ADC_REGULAR_GROUP only*/
02996       default:
02997         tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
02998         break;
02999     }
03000
03001     /* Wait for conversion effectively stopped */
03002
03003
03004     tickstart = HAL_GetTick();
03005
03006     while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET)
03007     {
03008       if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
03009       {
03010         /* Update ADC state machine to error */
03011         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
03012
03013         /* Set ADC error code to ADC IP internal error */
03014         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03015
03016         return HAL_ERROR;
03017       }
03018     }
03019
03020   } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc)) */
03021
03022   /* Return HAL status */
03023   return HAL_OK;
03024 }
03025
03026
03027
03028 /**
03029   * @brief  Enable the selected ADC.
03030   * @note   Prerequisite condition to use this function: ADC must be disabled
03031   *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
03032   * @param  hadc: ADC handle
03033   * @retval HAL status.
03034   */
03035 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
03036 {
03037   uint32_t tickstart = 0;
03038
03039   /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
03040   /* enabling phase not yet completed: flag ADC ready not yet set).           */
03041   /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
03042   /* causes: ADC clock not running, ...).                                     */
03043   if (ADC_IS_ENABLE(hadc) == RESET)
03044   {
03045     /* Check if conditions to enable the ADC are fulfilled */
03046     if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
03047     {
03048       /* Update ADC state machine to error */
03049       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
03050
03051       /* Set ADC error code to ADC IP internal error */
03052       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03053
03054       return HAL_ERROR;
03055     }
03056
03057     /* Enable the ADC peripheral */
03058     ADC_ENABLE(hadc);
03059
03060
03061     /* Wait for ADC effectively enabled */
03062     tickstart = HAL_GetTick();
03063
03064     while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
03065     {
03066       /*  If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
03067           has been cleared (after a calibration), ADEN bit is reset by the
03068           calibration logic.
03069           The workaround is to continue setting ADEN until ADRDY is becomes 1.
03070           Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
03071           4 ADC clock cycle duration */
03072       ADC_ENABLE(hadc);
03073
03074       if((HAL_GetTick()-tickstart) > ADC_ENABLE_TIMEOUT)
03075       {
03076         /* Update ADC state machine to error */
03077         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
03078
03079         /* Set ADC error code to ADC IP internal error */
03080         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03081
03082         return HAL_ERROR;
03083       }
03084     }
03085   }
03086
03087   /* Return HAL status */
03088   return HAL_OK;
03089 }
03090
03091 /**
03092   * @brief  Disable the selected ADC.
03093   * @note   Prerequisite condition to use this function: ADC conversions must be
03094   *         stopped.
03095   * @param  hadc: ADC handle
03096   * @retval HAL status.
03097   */
03098 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
03099 {
03100   uint32_t tickstart = 0;
03101
03102   /* Verification if ADC is not already disabled:                             */
03103   /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already  */
03104   /* disabled.                                                                */
03105   if (ADC_IS_ENABLE(hadc) != RESET )
03106   {
03107     /* Check if conditions to disable the ADC are fulfilled */
03108     if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
03109     {
03110       /* Disable the ADC peripheral */
03111       ADC_DISABLE(hadc);
03112     }
03113     else
03114     {
03115       /* Update ADC state machine to error */
03116       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
03117
03118       /* Set ADC error code to ADC IP internal error */
03119       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03120
03121       return HAL_ERROR;
03122     }
03123
03124     /* Wait for ADC effectively disabled */
03125     /* Get tick count */
03126     tickstart = HAL_GetTick();
03127
03128     while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
03129     {
03130       if((HAL_GetTick()-tickstart) > ADC_DISABLE_TIMEOUT)
03131       {
03132         /* Update ADC state machine to error */
03133         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
03134
03135         /* Set ADC error code to ADC IP internal error */
03136         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03137
03138         return HAL_ERROR;
03139       }
03140     }
03141   }
03142
03143   /* Return HAL status */
03144   return HAL_OK;
03145 }
03146
03147
03148 /**
03149   * @brief  DMA transfer complete callback.
03150   * @param  hdma: pointer to DMA handle.
03151   * @retval None
03152   */
03153 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
03154 {
03155   /* Retrieve ADC handle corresponding to current DMA handle */
03156   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
03157
03158   /* Update state machine on conversion status if not in error state */
03159   if (HAL_IS_BIT_CLR(hadc->State, (HAL_ADC_STATE_ERROR_INTERNAL|HAL_ADC_STATE_ERROR_DMA)))
03160   {
03161     /* Update ADC state machine */
03162     SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
03163     /* Is it the end of the regular sequence ? */
03164     if (HAL_IS_BIT_SET(hadc->Instance->ISR, ADC_FLAG_EOS))
03165     {
03166       /* Are conversions software-triggered ? */
03167       if(ADC_IS_SOFTWARE_START_REGULAR(hadc))
03168       {
03169         /* Is CONT bit set ? */
03170         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == RESET)
03171         {
03172           /* CONT bit is not set, no more conversions expected */
03173           CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
03174           if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
03175           {
03176             SET_BIT(hadc->State, HAL_ADC_STATE_READY);
03177           }
03178         }
03179       }
03180     }
03181     else
03182     {
03183       /* DMA End of Transfer interrupt was triggered but conversions sequence
03184          is not over. If DMACFG is set to 0, conversions are stopped. */
03185       if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT) == RESET)
03186       {
03187         /* DMACFG bit is not set, conversions are stopped. */
03188         CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
03189         if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
03190         {
03191           SET_BIT(hadc->State, HAL_ADC_STATE_READY);
03192         }
03193       }
03194     }
03195
03196     /* Conversion complete callback */
03197     HAL_ADC_ConvCpltCallback(hadc);
03198   }
03199   else /* DMA or internal error occured (or both) */
03200   {
03201     /* In case of internal error, */
03202     if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
03203     {
03204       /* call Error Callback function */
03205       HAL_ADC_ErrorCallback(hadc);
03206     }
03207
03208   }
03209
03210
03211 }
03212
03213 /**
03214   * @brief  DMA half transfer complete callback.
03215   * @param  hdma: pointer to DMA handle.
03216   * @retval None
03217   */
03218 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
03219 {
03220   /* Retrieve ADC handle corresponding to current DMA handle */
03221   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
03222
03223   /* Half conversion callback */
03224   HAL_ADC_ConvHalfCpltCallback(hadc);
03225 }
03226
03227 /**
03228   * @brief  DMA error callback
03229   * @param  hdma: pointer to DMA handle.
03230   * @retval None
03231   */
03232 void ADC_DMAError(DMA_HandleTypeDef *hdma)
03233 {
03234   /* Retrieve ADC handle corresponding to current DMA handle */
03235   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
03236
03237   /* Set ADC state */
03238   SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
03239
03240   /* Set ADC error code to DMA error */
03241   SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
03242
03243   /* Error callback */
03244   HAL_ADC_ErrorCallback(hadc);
03245 }
03246
03247 /**
03248   * @}
03249   */
03250
03251 #endif /* HAL_ADC_MODULE_ENABLED */
03252 /**
03253   * @}
03254   */
03255
03256 /**
03257   * @}
03258   */
03259
03260 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:37 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_adc.h Source File

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stm32h7xx_hal_adc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_adc.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of ADC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_ADC_H
00040 #define __STM32H7xx_ADC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup ADC
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup ADC_Exported_Types ADC Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  ADC Regular Conversion Oversampling structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Ratio;                         /*!< Configures the oversampling ratio. */
00068
00069
00070   uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
00071                                                This parameter can be a value of @ref ADCEx_Right_Bit_Shift */
00072
00073   uint32_t TriggeredMode;                 /*!< Selects the regular triggered oversampling mode.
00074                                                This parameter can be a value of @ref ADCEx_Triggered_Oversampling_Mode */
00075
00076   uint32_t OversamplingStopReset;         /*!< Selects the regular oversampling mode.
00077                                                The oversampling is either temporary stopped or reset upon an injected
00078                                                sequence interruption.
00079                                                If oversampling is enabled on both regular and injected groups, this parameter
00080                                                is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE"
00081                                                (the oversampling buffer is zeroed during injection sequence).
00082                                                This parameter can be a value of @ref ADCEx_Regular_Oversampling_Mode */
00083 }ADC_OversamplingTypeDef;
00084
00085 /**
00086   * @brief  Structure definition of ADC instance and ADC group regular.
00087   * @note   Parameters of this structure are shared within 2 scopes:
00088   *          - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
00089   *            ScanConvMode, EOCSelection, LowPowerAutoWait.
00090   *          - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion,
00091   *            ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
00092   * @note   The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
00093   *         ADC state can be either:
00094   *          - For all parameters: ADC disabled
00095   *          - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.
00096   *          - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected.
00097   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00098   *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter
00099   *         (which fulfills the ADC state condition) on the fly).
00100   */
00101 typedef struct
00102 {
00103   uint32_t ClockPrescaler;        /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from System/PLL2/PLL3 clocks) and clock prescaler.
00104
00105                                        This parameter can be a value of @ref ADC_ClockPrescaler.
00106                                        Note: The clock is common for all the ADCs.
00107                                        Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 16, 14, 12 or 10 bits,
00108                                              AHB clock frequency /3 for resolution 8 bits.
00109                                        Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
00110                                              if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
00111                                              must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
00112                                        Note: In case of usage of the ADC dedicated PLL clock, it must be preliminarily enabled at RCC top level.
00113                                        Note: This parameter can be modified only if all ADCs are disabled. */
00114
00115   uint32_t Resolution;            /*!< Configure the ADC resolution.
00116                                        This parameter can be a value of @ref ADC_Resolution */
00117
00118   uint32_t ScanConvMode;          /*!< Configure the sequencer of ADC groups regular and injected.
00119                                        This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
00120                                        If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
00121                                                     Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
00122                                        If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer).
00123                                                     Scan direction is upward: from rank 1 to rank 'n'.
00124                                        This parameter can be a value of @ref ADC_Scan_mode */
00125
00126   uint32_t EOCSelection;          /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
00127                                        This parameter can be a value of @ref ADC_EOCSelection. */
00128
00129   FunctionalState LowPowerAutoWait;      /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
00130                                        conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software,
00131                                        using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
00132                                        This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
00133                                        for low frequency applications.
00134                                        This parameter can be set to ENABLE or DISABLE.
00135                                        Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
00136                                              to free the IRQ vector sequencer.
00137                                              Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
00138                                              use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.
00139                                              (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
00140
00141   FunctionalState ContinuousConvMode;    /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
00142                                        after the first ADC conversion start trigger occurred (software start or external trigger).
00143                                        This parameter can be set to ENABLE or DISABLE. */
00144
00145   uint32_t NbrOfConversion;       /*!< Specify the number of ranks that will be converted within the regular group sequencer.
00146                                        To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
00147                                        This parameter must be a number between Min_Data = 1 and Max_Data = 16.
00148                                        Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without
00149                                        continuous mode or external trigger that could launch a conversion). */
00150
00151   FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
00152                                        (main sequence subdivided in successive parts).
00153                                        Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
00154                                        Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
00155                                        This parameter can be set to ENABLE or DISABLE. */
00156
00157   uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided.
00158                                        If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
00159                                        This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
00160
00161   uint32_t ExternalTrigConv;      /*!< Select the external event source used to trigger ADC group regular conversion start.
00162                                        If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
00163                                        This parameter can be a value of @ref ADC_regular_external_trigger_source.
00164                                        Caution: external trigger source is common to all ADC instances. */
00165
00166   uint32_t ExternalTrigConvEdge;  /*!< Select the external event edge used to trigger ADC group regular conversion start.
00167                                        If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
00168                                        This parameter can be a value of @ref ADC_regular_external_trigger_edge */
00169
00170   uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transfered to DFSDM register.
00171                                        Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
00172                                        This parameter can be a value of @ref ADC_ConversionDataManagement.
00173                                        Note: This parameter must be modified when no conversion is on going on both regular and injected groups
00174                                        (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
00175
00176   uint32_t Overrun;                  /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
00177                                        This parameter applies to ADC group regular only.
00178                                        This parameter can be a value of @ref ADC_Overrun.
00179                                        Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
00180                                        end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
00181                                        HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
00182                                        Note: Error reporting with respect to the conversion mode:
00183                                              - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
00184                                                overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
00185                                              - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
00186
00187   uint32_t LeftBitShift;             /*!< Configures the left shifting applied to the final result with or without oversampling.
00188                                           This parameter can be a value of @ref ADCEx_Left_Bit_Shift */
00189
00190   FunctionalState BoostMode;         /*!< Configures the Boost mode control.
00191                                         When selecting an analog ADC clock frequency bigger than 20MHz,
00192                                       it is mandatory to first enable the BOOST Mode.
00193                                           This parameter can be set to ENABLE or DISABLE. */
00194
00195   FunctionalState OversamplingMode;        /*!< Specify whether the oversampling feature is enabled or disabled.
00196                                         This parameter can be set to ENABLE or DISABLE.
00197                                         Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */
00198
00199   ADC_OversamplingTypeDef Oversampling;   /*!< Specify the Oversampling parameters.
00200                                                Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
00201 }ADC_InitTypeDef;
00202
00203 /**
00204   * @brief  Structure definition of ADC analog watchdog
00205   * @note   The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
00206   *         ADC state can be either:
00207   *         ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected.
00208   */
00209 typedef struct
00210 {
00211   uint32_t WatchdogNumber;    /*!< Select which ADC analog watchdog is monitoring the selected channel.
00212                                    For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
00213                                    For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
00214                                    This parameter can be a value of @ref ADCEx_analog_watchdog_number. */
00215
00216   uint32_t WatchdogMode;      /*!< Configure the ADC analog watchdog mode: single/all/none channels.
00217                                    For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel/all channels, ADC groups regular and/or injected.
00218                                    For Analog Watchdog 2 and 3: There is no configuration for all channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset
00219                                    channels group programmed with parameter 'Channel', set any other value to program the channel(s) to be monitored.
00220                                    This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */
00221
00222   uint32_t Channel;           /*!< Select which ADC channel to monitor by analog watchdog.
00223                                    For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
00224                                    For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
00225                                    This parameter can be a value of @ref ADC_channels. */
00226
00227   FunctionalState ITMode;            /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
00228                                    This parameter can be set to ENABLE or DISABLE */
00229
00230   uint32_t HighThreshold;     /*!< Configure the ADC analog watchdog High threshold value.
00231                                    Depending of ADC resolution selected (16, 14, 12, 10 or 8 bits), this parameter must be a number
00232                                    between Min_Data = 0x0000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. */
00233
00234   uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog Low threshold value.
00235                                    Depending of ADC resolution selected (16, 14, 12, or 8 bits), this parameter must be a number
00236                                    between Min_Data = 0x0000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. */
00237
00238 }ADC_AnalogWDGConfTypeDef;
00239
00240 /** @defgroup ADC_States ADC States
00241   * @{
00242   */
00243 /**
00244   * @brief  HAL ADC state machine: ADC states definition (bitfields)
00245   * @note   ADC state machine is managed by bitfields, state must be compared
00246   *         with bit by bit.
00247   *         For example:
00248   *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
00249   *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)    ) "
00250   */
00251 /* States of ADC global scope */
00252 #define HAL_ADC_STATE_RESET             ((uint32_t)0x00000000)    /*!< ADC not yet initialized or disabled */
00253 #define HAL_ADC_STATE_READY             ((uint32_t)0x00000001)    /*!< ADC peripheral ready for use */
00254 #define HAL_ADC_STATE_BUSY_INTERNAL     ((uint32_t)0x00000002)    /*!< ADC is busy due to an internal process (initialization, calibration) */
00255 #define HAL_ADC_STATE_TIMEOUT           ((uint32_t)0x00000004)    /*!< TimeOut occurrence */
00256
00257 /* States of ADC errors */
00258 #define HAL_ADC_STATE_ERROR_INTERNAL    ((uint32_t)0x00000010)    /*!< Internal error occurrence */
00259 #define HAL_ADC_STATE_ERROR_CONFIG      ((uint32_t)0x00000020)    /*!< Configuration error occurrence */
00260 #define HAL_ADC_STATE_ERROR_DMA         ((uint32_t)0x00000040)    /*!< DMA error occurrence */
00261
00262 /* States of ADC group regular */
00263 #define HAL_ADC_STATE_REG_BUSY          ((uint32_t)0x00000100)    /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
00264                                                                        external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
00265 #define HAL_ADC_STATE_REG_EOC           ((uint32_t)0x00000200)    /*!< Conversion data available on group regular */
00266 #define HAL_ADC_STATE_REG_OVR           ((uint32_t)0x00000400)    /*!< Overrun occurrence */
00267 #define HAL_ADC_STATE_REG_EOSMP         ((uint32_t)0x00000800)    /*!< Not available on this STM32 serie: End Of Sampling flag raised  */
00268
00269 /* States of ADC group injected */
00270 #define HAL_ADC_STATE_INJ_BUSY          ((uint32_t)0x00001000)    /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,
00271                                                                        external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
00272 #define HAL_ADC_STATE_INJ_EOC           ((uint32_t)0x00002000)    /*!< Conversion data available on group injected */
00273 #define HAL_ADC_STATE_INJ_JQOVF         ((uint32_t)0x00004000)    /*!< Injected queue overflow occurrence */
00274
00275 /* States of ADC analog watchdogs */
00276 #define HAL_ADC_STATE_AWD1              ((uint32_t)0x00010000)    /*!< Out-of-window occurrence of ADC analog watchdog 1 */
00277 #define HAL_ADC_STATE_AWD2              ((uint32_t)0x00020000)    /*!< Out-of-window occurrence of ADC analog watchdog 2 */
00278 #define HAL_ADC_STATE_AWD3              ((uint32_t)0x00040000)    /*!< Out-of-window occurrence of ADC analog watchdog 3 */
00279
00280 /* States of ADC multi-mode */
00281 #define HAL_ADC_STATE_MULTIMODE_SLAVE   ((uint32_t)0x00100000)    /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */
00282 /**
00283   * @}
00284   */
00285
00286 /**
00287   * @}
00288   */
00289
00290
00291 /* Exported constants --------------------------------------------------------*/
00292
00293 /** @defgroup ADC_Exported_Constants ADC Exported Constants
00294   * @{
00295   */
00296
00297 /** @defgroup ADC_Error_Code ADC Error Code
00298   * @{
00299   */
00300 #define HAL_ADC_ERROR_NONE         ((uint32_t)0x00)   /*!< No error                                 */
00301 #define HAL_ADC_ERROR_INTERNAL     ((uint32_t)0x01)   /*!< ADC IP internal error (problem of clocking,
00302                                                           enable/disable, erroneous state, ...)     */
00303 #define HAL_ADC_ERROR_OVR          ((uint32_t)0x02)   /*!< Overrun error                            */
00304 #define HAL_ADC_ERROR_DMA          ((uint32_t)0x04)   /*!< DMA transfer error                       */
00305 #define HAL_ADC_ERROR_JQOVF        ((uint32_t)0x08)   /*!< Injected context queue overflow error    */
00306 /**
00307   * @}
00308   */
00309
00310 /** @defgroup ADC_ClockPrescaler ADC clock source and clock prescaler
00311   * @{
00312   */
00313 #define ADC_CLOCK_SYNC_PCLK_DIV1      ((uint32_t)ADC_CCR_CKMODE_0)  /*!< ADC synchronous clock derived from AHB clock not divided  */
00314 #define ADC_CLOCK_SYNC_PCLK_DIV2      ((uint32_t)ADC_CCR_CKMODE_1)  /*!< ADC synchronous clock derived from AHB clock divided by 2 */
00315 #define ADC_CLOCK_SYNC_PCLK_DIV4      ((uint32_t)ADC_CCR_CKMODE)    /*!< ADC synchronous clock derived from AHB clock divided by 4 */
00316
00317 #define ADC_CLOCKPRESCALER_PCLK_DIV1   ADC_CLOCK_SYNC_PCLK_DIV1     /*!< Obsolete naming, kept for compatibility with some other devices */
00318 #define ADC_CLOCKPRESCALER_PCLK_DIV2   ADC_CLOCK_SYNC_PCLK_DIV2     /*!< Obsolete naming, kept for compatibility with some other devices */
00319 #define ADC_CLOCKPRESCALER_PCLK_DIV4   ADC_CLOCK_SYNC_PCLK_DIV4     /*!< Obsolete naming, kept for compatibility with some other devices */
00320
00321 #define ADC_CLOCK_ASYNC_DIV1       ((uint32_t)0x00000000)                                        /*!< ADC asynchronous clock not divided    */
00322 #define ADC_CLOCK_ASYNC_DIV2       ((uint32_t)ADC_CCR_PRESC_0)                                   /*!< ADC asynchronous clock divided by 2   */
00323 #define ADC_CLOCK_ASYNC_DIV4       ((uint32_t)ADC_CCR_PRESC_1)                                   /*!< ADC asynchronous clock divided by 4   */
00324 #define ADC_CLOCK_ASYNC_DIV6       ((uint32_t)(ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))                 /*!< ADC asynchronous clock divided by 6   */
00325 #define ADC_CLOCK_ASYNC_DIV8       ((uint32_t)(ADC_CCR_PRESC_2))                                 /*!< ADC asynchronous clock divided by 8   */
00326 #define ADC_CLOCK_ASYNC_DIV10      ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_0))                 /*!< ADC asynchronous clock divided by 10  */
00327 #define ADC_CLOCK_ASYNC_DIV12      ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1))                 /*!< ADC asynchronous clock divided by 12  */
00328 #define ADC_CLOCK_ASYNC_DIV16      ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 16  */
00329 #define ADC_CLOCK_ASYNC_DIV32      ((uint32_t)(ADC_CCR_PRESC_3))                                 /*!< ADC asynchronous clock divided by 32  */
00330 #define ADC_CLOCK_ASYNC_DIV64      ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_0))                 /*!< ADC asynchronous clock divided by 64  */
00331 #define ADC_CLOCK_ASYNC_DIV128     ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1))                 /*!< ADC asynchronous clock divided by 128 */
00332 #define ADC_CLOCK_ASYNC_DIV256     ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 256 */
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup ADC_Resolution ADC Resolution
00338   * @{
00339   */
00340 #define ADC_RESOLUTION_16B      ((uint32_t)0x00000000)                             /*!<  ADC 16-bit resolution */
00341 #define ADC_RESOLUTION_14B      ((uint32_t)ADC_CFGR_RES_0)                         /*!<  ADC 14-bit resolution */
00342 #define ADC_RESOLUTION_12B      ((uint32_t)ADC_CFGR_RES_1)                         /*!<  ADC 12-bit resolution */
00343 #define ADC_RESOLUTION_10B      ((uint32_t)(ADC_CFGR_RES_1 | ADC_CFGR_RES_0))      /*!<  ADC 10-bit resolution */
00344 #define ADC_RESOLUTION_8B       ((uint32_t)ADC_CFGR_RES_2)                         /*!<  ADC 8-bit resolution */
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup ADC_Scan_mode ADC sequencer scan mode
00350   * @{
00351   */
00352 #define ADC_SCAN_DISABLE         ((uint32_t)0x00000000)        /*!< Scan mode disabled */
00353 #define ADC_SCAN_ENABLE          ((uint32_t)0x00000001)        /*!< Scan mode enabled  */
00354 /**
00355   * @}
00356   */
00357
00358 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
00359   * @{
00360   */
00361 /* External triggers of regular group for ADC1, ADC2, ADC3 */
00362 #define ADC_EXTERNALTRIG_T1_CC1           ((uint32_t)0x00000000)
00363 #define ADC_EXTERNALTRIG_T1_CC2           ((uint32_t)ADC_CFGR_EXTSEL_0)
00364 #define ADC_EXTERNALTRIG_T1_CC3           ((uint32_t)ADC_CFGR_EXTSEL_1)
00365 #define ADC_EXTERNALTRIG_T2_CC2           ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
00366 #define ADC_EXTERNALTRIG_T3_TRGO          ((uint32_t)ADC_CFGR_EXTSEL_2)
00367 #define ADC_EXTERNALTRIG_T4_CC4           ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
00368 #define ADC_EXTERNALTRIG_EXT_IT11         ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
00369 #define ADC_EXTERNALTRIG_T8_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
00370 #define ADC_EXTERNALTRIG_T8_TRGO2         ((uint32_t) ADC_CFGR_EXTSEL_3)
00371 #define ADC_EXTERNALTRIG_T1_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
00372 #define ADC_EXTERNALTRIG_T1_TRGO2         ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
00373 #define ADC_EXTERNALTRIG_T2_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
00374 #define ADC_EXTERNALTRIG_T4_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
00375 #define ADC_EXTERNALTRIG_T6_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
00376 #define ADC_EXTERNALTRIG_T15_TRGO         ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
00377 #define ADC_EXTERNALTRIG_T3_CC4           ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
00378 #define ADC_EXTERNALTRIG_HR1_ADCTRG1      ((uint32_t) ADC_CFGR_EXTSEL_4)
00379 #define ADC_EXTERNALTRIG_HR1_ADCTRG3      ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0))
00380 #define ADC_EXTERNALTRIG_LPTIM1_OUT       ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1))
00381 #define ADC_EXTERNALTRIG_LPTIM2_OUT       ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1| ADC_CFGR_EXTSEL_0))
00382 #define ADC_EXTERNALTRIG_LPTIM3_OUT       ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2))
00383
00384 #define ADC_SOFTWARE_START                ((uint32_t)0x00000001)
00385 /**
00386   * @}
00387   */
00388
00389 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
00390   * @{
00391   */
00392 #define ADC_EXTERNALTRIGCONVEDGE_NONE           ((uint32_t)0x00000000)        /*!< Regular conversions hardware trigger detection disabled */
00393 #define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CFGR_EXTEN_0)  /*!< Regular conversions hardware trigger detection on the rising edge */
00394 #define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CFGR_EXTEN_1)  /*!< Regular conversions hardware trigger detection on the falling edge */
00395 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CFGR_EXTEN)    /*!< Regular conversions hardware trigger detection on both the rising and falling edges */
00396 /**
00397   * @}
00398   */
00399
00400 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
00401   * @{
00402   */
00403 #define ADC_EOC_SINGLE_CONV         ((uint32_t) ADC_ISR_EOC)                 /*!< End of unitary conversion flag  */
00404 #define ADC_EOC_SEQ_CONV            ((uint32_t) ADC_ISR_EOS)                 /*!< End of sequence conversions flag    */
00405 /**
00406   * @}
00407   */
00408
00409 /** @defgroup ADC_Overrun ADC overrun
00410   * @{
00411   */
00412 #define ADC_OVR_DATA_PRESERVED             ((uint32_t)0x00000000)           /*!< Data preserved in case of overrun   */
00413 #define ADC_OVR_DATA_OVERWRITTEN           ((uint32_t)ADC_CFGR_OVRMOD)      /*!< Data overwritten in case of overrun */
00414 /**
00415   * @}
00416   */
00417
00418 /** @defgroup ADC_regular_rank ADC group regular sequencer rank
00419   * @{
00420   */
00421 #define ADC_REGULAR_RANK_1    ((uint32_t)0x00000001)       /*!< ADC regular conversion rank 1  */
00422 #define ADC_REGULAR_RANK_2    ((uint32_t)0x00000002)       /*!< ADC regular conversion rank 2  */
00423 #define ADC_REGULAR_RANK_3    ((uint32_t)0x00000003)       /*!< ADC regular conversion rank 3  */
00424 #define ADC_REGULAR_RANK_4    ((uint32_t)0x00000004)       /*!< ADC regular conversion rank 4  */
00425 #define ADC_REGULAR_RANK_5    ((uint32_t)0x00000005)       /*!< ADC regular conversion rank 5  */
00426 #define ADC_REGULAR_RANK_6    ((uint32_t)0x00000006)       /*!< ADC regular conversion rank 6  */
00427 #define ADC_REGULAR_RANK_7    ((uint32_t)0x00000007)       /*!< ADC regular conversion rank 7  */
00428 #define ADC_REGULAR_RANK_8    ((uint32_t)0x00000008)       /*!< ADC regular conversion rank 8  */
00429 #define ADC_REGULAR_RANK_9    ((uint32_t)0x00000009)       /*!< ADC regular conversion rank 9  */
00430 #define ADC_REGULAR_RANK_10   ((uint32_t)0x0000000A)       /*!< ADC regular conversion rank 10 */
00431 #define ADC_REGULAR_RANK_11   ((uint32_t)0x0000000B)       /*!< ADC regular conversion rank 11 */
00432 #define ADC_REGULAR_RANK_12   ((uint32_t)0x0000000C)       /*!< ADC regular conversion rank 12 */
00433 #define ADC_REGULAR_RANK_13   ((uint32_t)0x0000000D)       /*!< ADC regular conversion rank 13 */
00434 #define ADC_REGULAR_RANK_14   ((uint32_t)0x0000000E)       /*!< ADC regular conversion rank 14 */
00435 #define ADC_REGULAR_RANK_15   ((uint32_t)0x0000000F)       /*!< ADC regular conversion rank 15 */
00436 #define ADC_REGULAR_RANK_16   ((uint32_t)0x00000010)       /*!< ADC regular conversion rank 16 */
00437 /**
00438   * @}
00439   */
00440
00441 /** @defgroup ADC_channels ADC Channels
00442   * @{
00443   */
00444 #define ADC_CHANNEL_0           ((uint32_t)(0x00000000))
00445 #define ADC_CHANNEL_1           ((uint32_t)(ADC_SQR3_SQ10_0))
00446 #define ADC_CHANNEL_2           ((uint32_t)(ADC_SQR3_SQ10_1))
00447 #define ADC_CHANNEL_3           ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
00448 #define ADC_CHANNEL_4           ((uint32_t)(ADC_SQR3_SQ10_2))
00449 #define ADC_CHANNEL_5           ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
00450 #define ADC_CHANNEL_6           ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
00451 #define ADC_CHANNEL_7           ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
00452 #define ADC_CHANNEL_8           ((uint32_t)(ADC_SQR3_SQ10_3))
00453 #define ADC_CHANNEL_9           ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0))
00454 #define ADC_CHANNEL_10          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1))
00455 #define ADC_CHANNEL_11          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
00456 #define ADC_CHANNEL_12          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2))
00457 #define ADC_CHANNEL_13          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
00458 #define ADC_CHANNEL_14          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
00459 #define ADC_CHANNEL_15          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
00460 #define ADC_CHANNEL_16          ((uint32_t)(ADC_SQR3_SQ10_4))
00461 #define ADC_CHANNEL_17          ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0))
00462 #define ADC_CHANNEL_18          ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1))
00463 #define ADC_CHANNEL_19          ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1| ADC_SQR3_SQ10_0))
00464
00465 /* Note: Vbat/4, TempSensor and VREFINT internal channels are available on ADC3 only */
00466 #define ADC_CHANNEL_VBAT_DIV4    ADC_CHANNEL_17
00467 #define ADC_CHANNEL_TEMPSENSOR   ADC_CHANNEL_18
00468 #define ADC_CHANNEL_VREFINT      ADC_CHANNEL_19
00469
00470 /* Note: DAC1CH1 and DAC1CH2 internal channels is available on ADC2 only  */
00471 #define ADC_CHANNEL_DAC1CH1_ADC2 (ADC_CHANNEL_16) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
00472 #define ADC_CHANNEL_DAC1CH2_ADC2 (ADC_CHANNEL_17) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
00473 /**
00474   * @}
00475   */
00476
00477
00478 /** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management
00479   * @{
00480   */
00481 #define ADC_CONVERSIONDATA_DR                  ((uint32_t)0x00000000)                            /*!< Regular Conversion data stored in DR register only  */
00482 #define ADC_CONVERSIONDATA_DFSDM               ((uint32_t)ADC_CFGR_DMNGT_1)                      /*!< DFSDM mode selected */
00483 #define ADC_CONVERSIONDATA_DMA_ONESHOT         ((uint32_t)ADC_CFGR_DMNGT_0)                      /*!< DMA one shot mode selected */
00484 #define ADC_CONVERSIONDATA_DMA_CIRCULAR        ((uint32_t)(ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1)) /*!< DMA circular mode selected */
00485 /**
00486   * @}
00487   */
00488
00489 /**
00490   * @}
00491   */
00492
00493 /* Private macros ------------------------------------------------------------*/
00494
00495 /** @defgroup ADC_Private_Macro ADC Private Macros
00496   * @{
00497   */
00498
00499 /**
00500   * @brief Verify the ADC data conversion setting.
00501   * @param DATA : programmed DATA conversion mode.
00502   * @retval SET (DATA is a valid value) or RESET (DATA is invalid)
00503   */
00504 #define IS_ADC_CONVERSIONDATAMGT(DATA)                                         \
00505    ((((DATA) == ADC_CONVERSIONDATA_DR))          || \
00506     (((DATA) == ADC_CONVERSIONDATA_DFSDM))       || \
00507     (((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \
00508     (((DATA) == ADC_CONVERSIONDATA_DMA_CIRCULAR)))
00509
00510 /**
00511   * @brief Test if conversion trigger of regular group is software start
00512   *        or external trigger.
00513   * @param __HANDLE__: ADC handle
00514   * @retval SET (software start) or RESET (external trigger)
00515   */
00516 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                        \
00517        (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)
00518
00519 /**
00520   * @brief Returns resolution bits in CFGR register: RES[1:0].
00521   *        Returned value is among parameters in @ref ADC_Resolution.
00522   * @param __HANDLE__: ADC handle
00523   * @retval Parameter of @ref ADC_Resolution set.
00524   */
00525 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)
00526
00527 /**
00528   * @brief Clear ADC error code (set it to error code: "no error")
00529   * @param __HANDLE__: ADC handle
00530   * @retval None
00531   */
00532 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
00533
00534 /**
00535   * @brief Verification of ADC state: enabled or disabled
00536   * @param __HANDLE__: ADC handle
00537   * @retval SET (ADC enabled) or RESET (ADC disabled)
00538   */
00539 #define ADC_IS_ENABLE(__HANDLE__)                                                    \
00540        (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
00541           ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)                  \
00542         ) ? SET : RESET)
00543
00544 /**
00545   * @brief Check if no conversion on going on regular group
00546   * @param __HANDLE__: ADC handle
00547   * @retval SET (conversion is on going) or RESET (no conversion is on going)
00548   */
00549 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__)                    \
00550        (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET             \
00551         ) ? RESET : SET)
00552
00553 /**
00554   * @brief Simultaneously clears and sets specific bits of the handle State
00555   * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
00556   *        the first parameter is the ADC handle State, the second parameter is the
00557   *        bit field to clear, the third and last parameter is the bit field to set
00558   * @retval None
00559   */
00560 #define ADC_STATE_CLR_SET MODIFY_REG
00561
00562 /**
00563   * @brief Verify that a given value is aligned with the ADC resolution range.
00564   * @param RESOLUTION: ADC resolution (16, 14, 12, 10 or 8 bits).
00565   * @param ADC_VALUE: value checked against the resolution.
00566   * @retval SET (ADC_VALUE in line with RESOLUTION) or RESET (ADC_VALUE not in line with RESOLUTION)
00567   */
00568 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE)                                         \
00569    ((((RESOLUTION) == ADC_RESOLUTION_16B) && ((ADC_VALUE) <= ((uint32_t)0xFFFF))) || \
00570     (((RESOLUTION) == ADC_RESOLUTION_14B) && ((ADC_VALUE) <= ((uint32_t)0x3FFF))) || \
00571     (((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
00572     (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
00573     (((RESOLUTION) == ADC_RESOLUTION_8B)  && ((ADC_VALUE) <= ((uint32_t)0x00FF))))
00574
00575 /**
00576   * @brief Verify the length of the scheduled regular conversions group.
00577   * @param LENGTH: number of programmed conversions.
00578   * @retval SET (LENGTH is within the maximum number of possible programmable regular conversions) or RESET (LENGTH is null or too large)
00579   */
00580 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
00581
00582 /**
00583   * @brief Verify the number of scheduled regular conversions in discontinuous mode.
00584   * @param NUMBER: number of scheduled regular conversions in discontinuous mode.
00585   * @retval SET (NUMBER is within the maximum number of regular conversions in discontinous mode) or RESET (NUMBER is null or too large)
00586   */
00587 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
00588
00589 /**
00590   * @brief Verify the ADC clock setting.
00591   * @param ADC_CLOCK : programmed ADC clock.
00592   * @retval SET (ADC_CLOCK is a valid value) or RESET (ADC_CLOCK is invalid)
00593   */
00594 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
00595                                           ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
00596                                           ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
00597                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1)     || \
00598                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2)     || \
00599                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4)     || \
00600                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6)     || \
00601                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8)     || \
00602                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10)    || \
00603                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12)    || \
00604                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16)    || \
00605                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32)    || \
00606                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64)    || \
00607                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128)   || \
00608                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256) )
00609
00610 /**
00611   * @brief Verify the ADC resolution setting.
00612   * @param RESOLUTION: programmed ADC resolution.
00613   * @retval SET (RESOLUTION is a valid value) or RESET (RESOLUTION is invalid)
00614   */
00615 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_16B) || \
00616                                        ((RESOLUTION) == ADC_RESOLUTION_14B) || \
00617                                        ((RESOLUTION) == ADC_RESOLUTION_12B) || \
00618                                        ((RESOLUTION) == ADC_RESOLUTION_10B) || \
00619                                        ((RESOLUTION) == ADC_RESOLUTION_8B)    )
00620
00621 /**
00622   * @brief Verify the ADC resolution setting when limited to 8 bits.
00623   * @param RESOLUTION: programmed ADC resolution when limited to 8 bits.
00624   * @retval SET (RESOLUTION is a valid value) or RESET (RESOLUTION is invalid)
00625   */
00626 #define IS_ADC_RESOLUTION_8_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B))
00627
00628 /**
00629   * @brief Verify the ADC scan mode.
00630   * @param SCAN_MODE: programmed ADC scan mode.
00631   * @retval SET (SCAN_MODE is valid) or RESET (SCAN_MODE is invalid)
00632   */
00633 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
00634                                      ((SCAN_MODE) == ADC_SCAN_ENABLE)    )
00635
00636 /**
00637   * @brief Verify the ADC edge trigger setting for regular group.
00638   * @param EDGE: programmed ADC edge trigger setting.
00639   * @retval SET (EDGE is a valid value) or RESET (EDGE is invalid)
00640   */
00641 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
00642                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
00643                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
00644                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )
00645
00646 /**
00647   * @brief Verify the ADC regular conversions external trigger.
00648   * @param REGTRIG: programmed ADC regular conversions external trigger.
00649   * @retval SET (REGTRIG is a valid value) or RESET (REGTRIG is invalid)
00650   */
00651 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_CC1)        || \
00652                                  ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC2)        || \
00653                                  ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC3)        || \
00654                                  ((REGTRIG) == ADC_EXTERNALTRIG_T2_CC2)        || \
00655                                  ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO)       || \
00656                                  ((REGTRIG) == ADC_EXTERNALTRIG_T4_CC4)        || \
00657                                  ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11)      || \
00658                                  ((REGTRIG) == ADC_EXTERNALTRIG_T8_TRGO)       || \
00659                                  ((REGTRIG) == ADC_EXTERNALTRIG_T8_TRGO2)      || \
00660                                  ((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO)       || \
00661                                  ((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2)      || \
00662                                  ((REGTRIG) == ADC_EXTERNALTRIG_T2_TRGO)       || \
00663                                  ((REGTRIG) == ADC_EXTERNALTRIG_T4_TRGO)       || \
00664                                  ((REGTRIG) == ADC_EXTERNALTRIG_T6_TRGO)       || \
00665                                  ((REGTRIG) == ADC_EXTERNALTRIG_T15_TRGO)      || \
00666                                  ((REGTRIG) == ADC_EXTERNALTRIG_T3_CC4)        || \
00667                                  ((REGTRIG) == ADC_EXTERNALTRIG_HR1_ADCTRG1)   || \
00668                                  ((REGTRIG) == ADC_EXTERNALTRIG_HR1_ADCTRG3)   || \
00669                                  ((REGTRIG) == ADC_EXTERNALTRIG_LPTIM1_OUT)    || \
00670                                  ((REGTRIG) == ADC_EXTERNALTRIG_LPTIM2_OUT)    || \
00671                                  ((REGTRIG) == ADC_EXTERNALTRIG_LPTIM3_OUT)    || \
00672                                  ((REGTRIG) == ADC_SOFTWARE_START)           )
00673
00674 /**
00675   * @brief Verify the ADC regular conversions check for converted data availability.
00676   * @param EOC_SELECTION: converted data availability check.
00677   * @retval SET (EOC_SELECTION is a valid value) or RESET (EOC_SELECTION is invalid)
00678   */
00679 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV)    || \
00680                                              ((EOC_SELECTION) == ADC_EOC_SEQ_CONV))
00681
00682 /**
00683   * @brief Verify the ADC regular conversions overrun handling.
00684   * @param OVR: ADC regular conversions overrun handling.
00685   * @retval SET (OVR is a valid value) or RESET (OVR is invalid)
00686   */
00687 #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED)  || \
00688                              ((OVR) == ADC_OVR_DATA_OVERWRITTEN)  )
00689
00690 /**
00691   * @brief Verify the ADC conversions sampling time.
00692   * @param TIME: ADC conversions sampling time.
00693   * @retval SET (TIME is a valid value) or RESET (TIME is invalid)
00694   */
00695 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5)    || \
00696                                   ((TIME) == ADC_SAMPLETIME_2CYCLES_5)   || \
00697                                   ((TIME) == ADC_SAMPLETIME_8CYCLES_5)  || \
00698                                   ((TIME) == ADC_SAMPLETIME_16CYCLES_5)  || \
00699                                   ((TIME) == ADC_SAMPLETIME_32CYCLES_5)  || \
00700                                   ((TIME) == ADC_SAMPLETIME_64CYCLES_5)  || \
00701                                   ((TIME) == ADC_SAMPLETIME_387CYCLES_5) || \
00702                                   ((TIME) == ADC_SAMPLETIME_810CYCLES_5)   )
00703
00704 /**
00705   * @brief Verify the ADC regular channel setting.
00706   * @param __CHANNEL__: programmed ADC regular channel.
00707   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
00708   */
00709 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
00710                                           ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
00711                                           ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
00712                                           ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
00713                                           ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
00714                                           ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
00715                                           ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
00716                                           ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
00717                                           ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
00718                                           ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
00719                                           ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
00720                                           ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
00721                                           ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
00722                                           ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
00723                                           ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
00724                                           ((__CHANNEL__) == ADC_REGULAR_RANK_16)   )
00725
00726 /**
00727   * @}
00728   */
00729
00730
00731 /* Private constants ---------------------------------------------------------*/
00732
00733 /** @defgroup ADC_Private_Constants ADC Private Constants
00734   * @{
00735   */
00736
00737 /* Fixed timeout values for ADC conversion (including sampling time)        */
00738 /* Maximum sampling time is 810.5 ADC clock cycle        */
00739 /* Maximum conversion time is 16.5 + Maximum sampling time                  */
00740 /*                       or 16.5  + 810.5 = 827 ADC clock cycles            */
00741 /* Minimum ADC Clock frequency is 0.35 MHz                                  */
00742 /* Maximum conversion time is                                               */
00743 /*              827 / 0.35 MHz = 2.36 ms                                    */
00744 #define ADC_STOP_CONVERSION_TIMEOUT     ((uint32_t) 5)
00745
00746
00747
00748 /* Delay for temperature sensor stabilization time.                         */
00749 /* Maximum delay is 120us (refer device datasheet, parameter tSTART).       */
00750 /* Unit: us                                                                 */
00751 #define ADC_TEMPSENSOR_DELAY_US         ((uint32_t) 120)
00752
00753
00754 /* Delay for ADC voltage regulator startup time                               */
00755 /*  Maximum delay is 10 microseconds                                          */
00756 /* (refer device RM, parameter Tadcvreg_stup).                                */
00757 #define ADC_STAB_DELAY_US               ((uint32_t) 10)     /*!< ADC voltage regulator startup time */
00758
00759 /**
00760   * @}
00761   */
00762
00763 /* Exported macros -----------------------------------------------------------*/
00764
00765 /** @defgroup ADC_Exported_Macro ADC Exported Macros
00766   * @{
00767   */
00768
00769 /**
00770   * @brief  Reset ADC handle state
00771   * @param  __HANDLE__: ADC handle
00772   * @retval None
00773   */
00774 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
00775
00776 /**
00777   * @brief  Checks if the specified ADC interrupt source is enabled or disabled.
00778   * @param __HANDLE__: ADC handle
00779   * @param __INTERRUPT__: ADC interrupt source to check
00780   *          This parameter can be one of the following values:
00781   *            @arg ADC_IT_RDY    ADC Ready (ADRDY) interrupt source
00782   *            @arg ADC_IT_EOSMP  ADC End of Sampling interrupt source
00783   *            @arg ADC_IT_EOC    ADC End of Regular Conversion interrupt source
00784   *            @arg ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
00785   *            @arg ADC_IT_OVR    ADC overrun interrupt source
00786   *            @arg ADC_IT_JEOC   ADC End of Injected Conversion interrupt source
00787   *            @arg ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source
00788   *            @arg ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
00789   *            @arg ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
00790   *            @arg ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
00791   *            @arg ADC_IT_JQOVF  ADC Injected Context Queue Overflow interrupt source
00792   * @retval State of interruption (SET or RESET)
00793   */
00794 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
00795     (( ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)      \
00796      )? SET : RESET                                                            \
00797     )
00798
00799 /**
00800   * @brief Enable an ADC interrupt.
00801   * @param __HANDLE__: ADC handle
00802   * @param __INTERRUPT__: ADC Interrupt to enable
00803    *          This parameter can be one of the following values:
00804   *            @arg ADC_IT_RDY    ADC Ready (ADRDY) interrupt source
00805   *            @arg ADC_IT_EOSMP  ADC End of Sampling interrupt source
00806   *            @arg ADC_IT_EOC    ADC End of Regular Conversion interrupt source
00807   *            @arg ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
00808   *            @arg ADC_IT_OVR    ADC overrun interrupt source
00809   *            @arg ADC_IT_JEOC   ADC End of Injected Conversion interrupt source
00810   *            @arg ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source
00811   *            @arg ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
00812   *            @arg ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
00813   *            @arg ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
00814   *            @arg ADC_IT_JQOVF  ADC Injected Context Queue Overflow interrupt source
00815   * @retval None
00816   */
00817 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
00818
00819 /**
00820   * @brief Disable an ADC interrupt.
00821   * @param __HANDLE__: ADC handle
00822   * @param __INTERRUPT__: ADC Interrupt to disable
00823   *            @arg ADC_IT_RDY    ADC Ready (ADRDY) interrupt source
00824   *            @arg ADC_IT_EOSMP  ADC End of Sampling interrupt source
00825   *            @arg ADC_IT_EOC    ADC End of Regular Conversion interrupt source
00826   *            @arg ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
00827   *            @arg ADC_IT_OVR    ADC overrun interrupt source
00828   *            @arg ADC_IT_JEOC   ADC End of Injected Conversion interrupt source
00829   *            @arg ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source
00830   *            @arg ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
00831   *            @arg ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
00832   *            @arg ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
00833   *            @arg ADC_IT_JQOVF  ADC Injected Context Queue Overflow interrupt source
00834   * @retval None
00835   */
00836 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
00837
00838 /**
00839   * @brief Checks whether the specified ADC flag is set or not.
00840   * @param __HANDLE__: ADC handle
00841   * @param __FLAG__: ADC flag to check
00842   *        This parameter can be one of the following values:
00843   *            @arg ADC_FLAG_RDY     ADC Ready (ADRDY) flag
00844   *            @arg ADC_FLAG_EOSMP   ADC End of Sampling flag
00845   *            @arg ADC_FLAG_EOC     ADC End of Regular Conversion flag
00846   *            @arg ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag
00847   *            @arg ADC_FLAG_OVR     ADC overrun flag
00848   *            @arg ADC_FLAG_JEOC    ADC End of Injected Conversion flag
00849   *            @arg ADC_FLAG_JEOS    ADC End of Injected sequence of Conversions flag
00850   *            @arg ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)
00851   *            @arg ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)
00852   *            @arg ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)
00853   *            @arg ADC_FLAG_JQOVF   ADC Injected Context Queue Overflow flag
00854   * @retval The new state of __FLAG__ (TRUE or FALSE).
00855   */
00856 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
00857
00858 /**
00859   * @brief Clear a specified ADC flag
00860   * @param __HANDLE__: ADC handle
00861   * @param __FLAG__: ADC flag to clear
00862   *        This parameter can be one of the following values:
00863   *            @arg ADC_FLAG_RDY     ADC Ready (ADRDY) flag
00864   *            @arg ADC_FLAG_EOSMP   ADC End of Sampling flag
00865   *            @arg ADC_FLAG_EOC     ADC End of Regular Conversion flag
00866   *            @arg ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag
00867   *            @arg ADC_FLAG_OVR     ADC overrun flag
00868   *            @arg ADC_FLAG_JEOC    ADC End of Injected Conversion flag
00869   *            @arg ADC_FLAG_JEOS    ADC End of Injected sequence of Conversions flag
00870   *            @arg ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)
00871   *            @arg ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)
00872   *            @arg ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)
00873   *            @arg ADC_FLAG_JQOVF   ADC Injected Context Queue Overflow flag
00874   * @note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR)
00875   * @retval None
00876   */
00877 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
00878
00879 /**
00880   * @}
00881   */
00882
00883 /* Include ADC HAL Extended module */
00884 #include "stm32h7xx_hal_adc_ex.h"
00885
00886 /* Exported functions --------------------------------------------------------*/
00887 /** @addtogroup ADC_Exported_Functions ADC Exported Functions
00888   * @{
00889   */
00890
00891 /** @addtogroup ADC_Exported_Functions_Group1 Initialization and deinitialization functions
00892   * @brief      ADC Initialization and Configuration functions
00893   * @{
00894   */
00895 /* Initialization and de-initialization functions  **********************************/
00896 HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef* hadc);
00897 HAL_StatusTypeDef       HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
00898 void                    HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
00899 void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
00900 /**
00901   * @}
00902   */
00903
00904 /** @addtogroup ADC_Exported_Functions_Group2 Input and Output operation functions
00905   * @brief      ADC IO operation functions
00906   * @{
00907   */
00908 /* IO operation functions  *****************************************************/
00909
00910 /* Blocking mode: Polling */
00911 HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef* hadc);
00912 HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
00913 HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
00914 HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
00915
00916 /* Non-blocking mode: Interruption */
00917 HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
00918 HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
00919
00920 /* Non-blocking mode: DMA */
00921 HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
00922 HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
00923
00924 /* ADC retrieve conversion value intended to be used with polling or interruption */
00925 uint32_t                HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
00926
00927 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
00928 void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
00929 void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
00930 void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
00931 void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
00932 void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
00933 /**
00934   * @}
00935   */
00936
00937 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
00938   * @brief      Peripheral Control functions
00939   * @{
00940   */
00941 /* Peripheral Control functions ***********************************************/
00942 HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
00943 HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
00944
00945 /**
00946   * @}
00947   */
00948
00949 /* Peripheral State functions *************************************************/
00950 /** @addtogroup ADC_Exported_Functions_Group4
00951   * @{
00952   */
00953 uint32_t      HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
00954 uint32_t      HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
00955
00956 /**
00957   * @}
00958   */
00959
00960
00961 /* Private functions -----------------------------------------------------------*/
00962 /** @addtogroup ADC_Private_Functions ADC Private Functions
00963   * @{
00964   */
00965 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup);
00966 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
00967 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
00968 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
00969 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
00970 void ADC_DMAError(DMA_HandleTypeDef *hdma);
00971
00972 /**
00973   * @}
00974   */
00975
00976 /**
00977   * @}
00978   */
00979
00980 /**
00981   * @}
00982   */
00983
00984 /**
00985   * @}
00986   */
00987
00988 #ifdef __cplusplus
00989 }
00990 #endif
00991
00992
00993 #endif /*__STM32H7xx_ADC_H */
00994
00995 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:37 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_adc_ex.c Source File

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stm32h7xx_hal_adc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_adc_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Analog to Digital Convertor (ADC)
00009   *          peripheral:
00010   *          + Operation functions
00011   *             ++ Start, stop, get result of conversions of injected
00012   *                group, using 2 possible modes: polling, interruption.
00013   *             ++ Calibration
00014   *               +++ ADC automatic self-calibration
00015   *               +++ Calibration factors get or set
00016   *             ++ Multimode feature when available
00017   *           + Control functions
00018   *             ++ Channels configuration on injected group
00019   *           + State functions
00020   *             ++ Injected group queues management
00021   *          Other functions (generic functions) are available in file
00022   *          "stm32h7xx_hal_adc.c".
00023   *
00024    @verbatim
00025   ==============================================================================
00026                     ##### ADC specific features #####
00027   ==============================================================================
00028   [..]
00029   (@) Sections "ADC peripheral features" and "How to use this driver" are
00030       available in file of generic functions "stm32h7xx_hal_adc.c".
00031   [..]
00032
00033     @endverbatim
00034   ******************************************************************************
00035   * @attention
00036   *
00037   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00038   *
00039   * Redistribution and use in source and binary forms, with or without modification,
00040   * are permitted provided that the following conditions are met:
00041   *   1. Redistributions of source code must retain the above copyright notice,
00042   *      this list of conditions and the following disclaimer.
00043   *   2. Redistributions in binary form must reproduce the above copyright notice,
00044   *      this list of conditions and the following disclaimer in the documentation
00045   *      and/or other materials provided with the distribution.
00046   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00047   *      may be used to endorse or promote products derived from this software
00048   *      without specific prior written permission.
00049   *
00050   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00051   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00052   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00053   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00054   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00055   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00056   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00057   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00058   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00059   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00060   *
00061   ******************************************************************************
00062   */
00063
00064 /* Includes ------------------------------------------------------------------*/
00065 #include "stm32h7xx_hal.h"
00066
00067 /** @addtogroup STM32H7xx_HAL_Driver
00068   * @{
00069   */
00070
00071 /** @defgroup ADCEx ADCEx
00072   * @brief ADC Extended HAL module driver
00073   * @{
00074   */
00075
00076 #ifdef HAL_ADC_MODULE_ENABLED
00077
00078 /* Private typedef -----------------------------------------------------------*/
00079 /* Private define ------------------------------------------------------------*/
00080
00081 /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
00082   * @{
00083   */
00084 #define ADC_JSQR_FIELDS  ((uint32_t)(ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
00085                                      ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
00086                                      ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime
00087                                                                              once the ADC is enabled */
00088
00089 #define ADC_CFGR2_INJ_FIELDS  ((uint32_t)(ADC_CFGR2_JOVSE | ADC_CFGR2_OSR  |\
00090                                           ADC_CFGR2_OVSS )) /*!< ADC_CFGR2 injected oversampling parameters that can be updated
00091                                                                   when no conversion is on-going (neither regular nor injected) */
00092
00093 /* Fixed timeout value for ADC calibration.                                   */
00094 /* Values defined to be higher than worst cases: low clock frequency,         */
00095 /* maximum prescalers.                                                        */
00096 /* Ex of profile low frequency : f_ADC at 0.35 MHz (minimum value             */
00097 /* according to Data sheet), calibration_time MAX = 112 / f_ADC               */
00098 /*           112 / 350,000 = 0.32 ms                                           */
00099 /* At maximum CPU speed (200 MHz), this means                                  */
00100 /*    0.8 ms * 200 MHz = 64000 CPU cycles                                      */
00101 #define ADC_CALIBRATION_TIMEOUT         ((uint32_t) 64000)   /*!< ADC calibration time-out value */
00102 /**
00103   * @}
00104   */
00105
00106 /* Private macro -------------------------------------------------------------*/
00107 /* Private variables ---------------------------------------------------------*/
00108 /* Private function prototypes -----------------------------------------------*/
00109 /* Exported functions --------------------------------------------------------*/
00110
00111 /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
00112   * @{
00113   */
00114
00115
00116
00117 /** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
00118   * @brief    Extended IO operation functions
00119   *
00120 @verbatim
00121  ===============================================================================
00122              ##### IO operation functions #####
00123  ===============================================================================
00124     [..]  This section provides functions allowing to:
00125
00126       (+) Perform the ADC self-calibration for single or differential ending.
00127       (+) Get calibration factors for single or differential ending.
00128       (+) Set calibration factors for single or differential ending.
00129
00130       (+) Start conversion of injected group.
00131       (+) Stop conversion of injected group.
00132       (+) Poll for conversion complete on injected group.
00133       (+) Get result of injected channel conversion.
00134       (+) Start conversion of injected group and enable interruptions.
00135       (+) Stop conversion of injected group and disable interruptions.
00136
00137       (+) When multimode feature is available, start multimode and enable DMA transfer.
00138       (+) Stop multimode and disable ADC DMA transfer.
00139       (+) Get result of multimode conversion.
00140
00141
00142
00143 @endverbatim
00144   * @{
00145   */
00146
00147 /**
00148   * @brief  Perform an ADC automatic self-calibration
00149   *         Calibration prerequisite: ADC must be disabled (execute this
00150   *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
00151   * @param  hadc   ADC handle
00152   * @param  CalibrationMode: Selection of Calibration Mode
00153   *          This parameter can be one of the following values:
00154   *            @arg ADC_CALIB_OFFSET: ADC calibration in offset mode
00155   *            @arg ADC_CALIB_OFFSET_LINEARITY: ADC calibration in Linear offset mode
00156   * @param  SingleDiff: Selection of single-ended or differential input
00157   *          This parameter can be one of the following values:
00158   *            @arg ADC_SINGLE_ENDED: Channel in mode input single ended
00159   *            @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
00160   * @retval HAL status
00161   */
00162 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t CalibrationMode, uint32_t SingleDiff)
00163 {
00164   HAL_StatusTypeDef tmp_hal_status  = HAL_OK;
00165   uint32_t WaitLoopIndex = 0;
00166
00167   /* Check the parameters */
00168   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00169   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
00170
00171   /* Process locked */
00172   __HAL_LOCK(hadc);
00173
00174   /* Calibration prerequisite: ADC must be disabled. */
00175
00176   /* Disable the ADC (if not already disabled) */
00177   tmp_hal_status  = ADC_Disable(hadc);
00178
00179   /* Check if ADC is effectively disabled */
00180   if (tmp_hal_status  == HAL_OK)
00181   {
00182     /* Change ADC state */
00183     /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_BUSY_INTERNAL bit */
00184     ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_BUSY_INTERNAL);
00185
00186     /* Select calibration mode single ended or differential ended */
00187     MODIFY_REG(hadc->Instance->CR, ADC_CR_ADCALDIF, SingleDiff);
00188
00189     /* Select the Linear calibration if enabled */
00190     MODIFY_REG(hadc->Instance->CR, ADC_CR_ADCALLIN, CalibrationMode);
00191
00192     /* Start ADC calibration */
00193     SET_BIT(hadc->Instance->CR, ADC_CR_ADCAL);
00194
00195
00196     /* Wait for calibration completion */
00197     while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
00198     {
00199       WaitLoopIndex++;
00200       if (WaitLoopIndex >= ADC_CALIBRATION_TIMEOUT)
00201       {
00202         /* Update ADC state machine to error */
00203         /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_ERROR_INTERNAL bit */
00204         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);
00205
00206         /* Process unlocked */
00207         __HAL_UNLOCK(hadc);
00208
00209         return HAL_ERROR;
00210       }
00211     }
00212
00213     /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
00214     ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
00215   }
00216   else
00217   {
00218     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00219
00220     /* Note: No need to update variable "tmp_hal_status" here: already set    */
00221     /*       to state "HAL_ERROR" by function disabling the ADC.              */
00222   }
00223
00224   /* Process unlocked */
00225   __HAL_UNLOCK(hadc);
00226
00227   /* Return function status */
00228   return tmp_hal_status ;
00229 }
00230
00231 /**
00232   * @brief  Get the calibration factor from automatic conversion result.
00233   * @param  hadc: ADC handle.
00234   * @param  SingleDiff: Selection of single-ended or differential input
00235   *          This parameter can be one of the following values:
00236   *            @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
00237   *            @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
00238   * @retval HAL state
00239   */
00240 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
00241 {
00242   /* Check the parameters */
00243   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00244   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
00245
00246   /* Return the selected ADC calibration value */
00247   if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
00248   {
00249     return ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT);
00250   }
00251   else
00252   {
00253     return ((hadc->Instance->CALFACT) & ADC_CALFACT_CALFACT_S);
00254   }
00255 }
00256
00257 /**
00258   * @brief  Get the calibration factor from automatic conversion result
00259   * @param  hadc: ADC handle
00260   * @param  LinearCalib_Buffer: Linear calibration factor
00261   * @retval HAL state
00262   */
00263 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t* LinearCalib_Buffer)
00264 {
00265   uint32_t cnt = 0;
00266   uint32_t WaitLoopIndex = 0;
00267
00268   /* Check the parameters */
00269   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00270
00271   /* Enable the ADC ADEN = 1 to be able to read the linear calibration factor */
00272   ADC_Enable(hadc);
00273
00274   for(cnt = 0; cnt < 6; cnt++)
00275   {
00276     /* Clear LINCALRDYWx */
00277     CLEAR_BIT(hadc->Instance->CR, ADC_CR_LINCALRDYW6 >> cnt);
00278     /* Wait untill LINCALRDYWx is reset */
00279     while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_LINCALRDYW6 >> cnt))
00280     {
00281       WaitLoopIndex++;
00282       if (WaitLoopIndex >= ADC_CALIBRATION_TIMEOUT)
00283       {
00284         return HAL_ERROR;
00285       }
00286     }
00287
00288     /* Read the ADCx_CALFACT2[29:0] containing the LINCALWx*/
00289     *(LinearCalib_Buffer + cnt) = hadc->Instance->CALFACT2;
00290   }
00291   return HAL_OK;
00292 }
00293
00294 /**
00295   * @brief  Set the calibration factor to overwrite automatic conversion result, ADC must be enabled and no conversion on going.
00296   * @param  hadc: ADC handle.
00297   * @param  SingleDiff: Selection of single-ended or differential input.
00298   *          This parameter can be one of the following values:
00299   *            @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
00300   *            @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
00301   * @param  CalibrationFactor: Calibration factor (coded on 7 bits maximum)
00302   * @retval HAL state
00303   */
00304 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
00305 {
00306   HAL_StatusTypeDef tmp_hal_status  = HAL_OK;
00307
00308   /* Check the parameters */
00309   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00310   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
00311   assert_param(IS_ADC_CALFACT(CalibrationFactor));
00312
00313   /* Process locked */
00314   __HAL_LOCK(hadc);
00315
00316   /* Verification of hardware constraints before modifying the calibration    */
00317   /* factors register: ADC must be enabled, no conversion on going.           */
00318   if ( (ADC_IS_ENABLE(hadc) != RESET)                            &&
00319        (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)  )
00320   {
00321     /* Set the selected ADC calibration value */
00322     if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
00323     {
00324       MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D, ADC_CALFACT_DIFF_SET(CalibrationFactor));
00325     }
00326     else
00327     {
00328       MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_S, CalibrationFactor);
00329     }
00330   }
00331   else
00332   {
00333     /* Update ADC state machine */
00334     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00335
00336     /* Update ADC state machine to error */
00337     tmp_hal_status  = HAL_ERROR;
00338   }
00339
00340   /* Process unlocked */
00341   __HAL_UNLOCK(hadc);
00342
00343   /* Return function status */
00344   return tmp_hal_status ;
00345 }
00346
00347 /**
00348   * @brief  Set the linear calibration factor
00349   * @param  hadc: ADC handle
00350   * @param  LinearCalib_Buffer: Linear calibration factor
00351   * @retval HAL state
00352   */
00353 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer)
00354 {
00355   uint32_t cnt = 0;
00356   __IO uint32_t wait_loop_index = 0;
00357
00358   /* Check the parameters */
00359   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00360
00361   /* - Exit from deep-power-down mode and ADC voltage regulator enable        */
00362   /*  Exit deep power down mode if still in that state                        */
00363   if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD))
00364   {
00365     /* Exit deep power down mode */
00366     CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
00367
00368     /* System was in deep power down mode, calibration must
00369        be relaunched or a previously saved calibration factor
00370        re-applied once the ADC voltage regulator is enabled */
00371   }
00372
00373
00374   if  (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
00375   {
00376     /* Enable ADC internal voltage regulator                                  */
00377     SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
00378     /* Delay for ADC stabilization time                                       */
00379     /* Wait loop initialization and execution                                 */
00380     /* Note: Variable divided by 2 to compensate partially                    */
00381     /*       CPU processing cycles.                                           */
00382     wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000 * 2)));
00383     while(wait_loop_index != 0)
00384     {
00385       wait_loop_index--;
00386     }
00387   }
00388
00389
00390   /* Verification that ADC voltage regulator is correctly enabled, whether    */
00391   /* or not ADC is coming from state reset (if any potential problem of       */
00392   /* clocking, voltage regulator would not be enabled).                       */
00393   if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
00394   {
00395     /* Update ADC state machine to error */
00396     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00397
00398     /* Set ADC error code to ADC IP internal error */
00399     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00400
00401     return  HAL_ERROR;
00402   }
00403
00404   for(cnt = 0; cnt < 6; cnt++)
00405   {
00406     /* Write the LINCALWx in ADCx_CALFACT2[29:0]  */
00407     hadc->Instance->CALFACT2 = *(LinearCalib_Buffer + cnt);
00408
00409     /* Set LINCALRDYWx */
00410     SET_BIT(hadc->Instance->CR, ADC_CR_LINCALRDYW6 >> cnt);
00411
00412     /* Wait untill LINCALRDYWx is set */
00413     while(HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_LINCALRDYW6 >> cnt))
00414     {
00415       wait_loop_index++;
00416       if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
00417       {
00418         return HAL_ERROR;
00419       }
00420     }
00421   }
00422   return HAL_OK;
00423 }
00424
00425 /**
00426   * @brief  Enable ADC, start conversion of injected group.
00427   * @note   Interruptions enabled in this function: None.
00428   * @note   Case of multimode enabled when multimode feature is available:
00429   *         HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
00430   *         then for ADC master.
00431   *         For ADC slave, ADC is enabled only (conversion is not started).
00432   *         For ADC master, ADC is enabled and multimode conversion is started.
00433   * @param  hadc: ADC handle.
00434   * @retval HAL status
00435   */
00436 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
00437 {
00438   HAL_StatusTypeDef tmp_hal_status  = HAL_OK;
00439
00440   /* Check the parameters */
00441   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00442
00443   if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc))
00444   {
00445     return HAL_BUSY;
00446   }
00447   else
00448   {
00449
00450     /* In case of software trigger detection enabled, JQDIS must be set
00451       (which can be done only if ADSTART and JADSTART are both cleared).
00452        If JQDIS is not set at that point, returns an error
00453        - since software trigger detection is disabled. User needs to
00454        resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
00455        - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
00456          the queue is empty */
00457     if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET)
00458         && (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET))
00459     {
00460       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00461       return HAL_ERROR;
00462     }
00463
00464
00465     /* Process locked */
00466     __HAL_LOCK(hadc);
00467
00468     /* Enable the ADC peripheral */
00469     tmp_hal_status  = ADC_Enable(hadc);
00470
00471     /* Start conversion if ADC is effectively enabled */
00472     if (tmp_hal_status  == HAL_OK)
00473     {
00474       /* Check if a regular conversion is ongoing */
00475       if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY))
00476       {
00477         /* Reset ADC error code field related to injected conversions only */
00478         CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
00479       }
00480       else
00481       {
00482         /* Set ADC error code to none */
00483         ADC_CLEAR_ERRORCODE(hadc);
00484       }
00485       /* Update ADC state */
00486       /* Clear HAL_ADC_STATE_READY and HAL_ADC_STATE_INJ_EOC bits, set HAL_ADC_STATE_INJ_BUSY bit */
00487       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_INJ_EOC), HAL_ADC_STATE_INJ_BUSY);
00488
00489       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
00490         - by default if ADC is Master or Independent or if multimode feature is not available
00491         - if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */
00492       if (ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
00493       {
00494         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00495       }
00496
00497
00498       /* Clear injected group conversion flag */
00499       /* (To ensure of no unknown state from potential previous ADC operations) */
00500       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
00501
00502       /* Enable conversion of injected group, if automatic injected conversion  */
00503       /* is disabled.                                                           */
00504       /* If software start has been selected, conversion starts immediately.    */
00505       /* If external trigger has been selected, conversion will start at next   */
00506       /* trigger event.                                                         */
00507       /* Case of multimode enabled (when multimode feature is available):       */
00508       /* if ADC is slave,                                                       */
00509       /*    - ADC is enabled only (conversion is not started).                  */
00510       /*    - if multimode only concerns regular conversion, ADC is enabled     */
00511       /*     and conversion is started.                                         */
00512       /* If ADC is master or independent,                                       */
00513       /*    - ADC is enabled and conversion is started.                         */
00514
00515       /* Are injected conversions that of a dual Slave ? */
00516       if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
00517       {
00518         /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
00519            set ADSTART only if JAUTO is cleared */
00520         /* Process unlocked */
00521         __HAL_UNLOCK(hadc);
00522
00523         if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
00524         {
00525           SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ;
00526         }
00527       }
00528       else
00529       {
00530         /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
00531            ADSTART is not set */
00532         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00533         /* Process unlocked */
00534         __HAL_UNLOCK(hadc);
00535       }
00536     }
00537     else
00538     {
00539       /* Process unlocked */
00540       __HAL_UNLOCK(hadc);
00541     } /* if (tmp_hal_status == HAL_OK) */
00542
00543     /* Return function status */
00544     return tmp_hal_status;
00545   } /*  if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc)) */
00546 }
00547
00548 /**
00549   * @brief  Stop conversion of injected channels and disable ADC peripheral if
00550   *         no regular conversion is on going.
00551   * @note   If ADC must be disabled and if conversion is on going on
00552   *         regular group, function HAL_ADC_Stop must be used to stop both
00553   *         injected and regular groups, and disable the ADC.
00554   * @note   If injected group mode auto-injection is enabled,
00555   *         function HAL_ADC_Stop must be used.
00556   * @note   In case of multimode enabled (when multimode feature is available),
00557   *         HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
00558   *         For ADC master, conversion is stopped and ADC is disabled.
00559   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
00560   *         has already stopped conversion of ADC slave).
00561   * @param  hadc: ADC handle.
00562   * @retval HAL status
00563   */
00564 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
00565 {
00566   HAL_StatusTypeDef tmp_hal_status  = HAL_OK;
00567
00568   /* Check the parameters */
00569   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00570
00571   /* Process locked */
00572   __HAL_LOCK(hadc);
00573
00574   /* 1. Stop potential conversion on going on injected group only. */
00575   tmp_hal_status  = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
00576
00577   /* Disable ADC peripheral if injected conversions are effectively stopped   */
00578   /* and if no conversion on regular group is on-going                       */
00579   if (tmp_hal_status  == HAL_OK)
00580   {
00581     if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
00582     {
00583       /* 2. Disable the ADC peripheral */
00584       tmp_hal_status  = ADC_Disable(hadc);
00585
00586       /* Check if ADC is effectively disabled */
00587       if (tmp_hal_status  == HAL_OK)
00588       {
00589         /* Change ADC state */
00590         /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
00591         ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
00592       }
00593     }
00594     /* Conversion on injected group is stopped, but ADC not disabled since    */
00595     /* conversion on regular group is still running.                          */
00596     else
00597     {
00598       /* Clear HAL_ADC_STATE_INJ_BUSY bit */
00599       CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00600     }
00601   }
00602
00603   /* Process unlocked */
00604   __HAL_UNLOCK(hadc);
00605
00606   /* Return function status */
00607   return tmp_hal_status ;
00608 }
00609
00610
00611
00612 /**
00613   * @brief  Wait for injected group conversion to be completed.
00614   * @param  hadc: ADC handle
00615   * @param  Timeout: Timeout value in millisecond.
00616   * @note   Depending on hadc->Init.EOCSelection, JEOS or JEOC is
00617   *         checked and cleared depending on AUTDLY bit status.
00618   * @retval HAL status
00619   */
00620 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
00621 {
00622   uint32_t           tickstart;
00623   uint32_t           tmp_Flag_End        = 0x00;
00624   ADC_TypeDef        *tmpADC_Master;
00625   uint32_t           tmp_cfgr            = 0x00;
00626   uint32_t           tmp_cfgr_jqm_autdly = 0x00;
00627   uint32_t           tmp_jeos_raised     = 0x01; /* by default, assume that JEOS is set,
00628                                                     tmp_jeos_raised will be corrected
00629                                                     accordingly during API execution */
00630
00631   /* Check the parameters */
00632   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00633
00634   /* If end of sequence selected */
00635   if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
00636   {
00637     tmp_Flag_End = ADC_FLAG_JEOS;
00638   }
00639   else /* end of conversion selected */
00640   {
00641     tmp_Flag_End = ADC_FLAG_JEOC;
00642   }
00643
00644   /* Get timeout */
00645   tickstart = HAL_GetTick();
00646
00647    /* Wait until End of Conversion or Sequence flag is raised */
00648   while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End))
00649   {
00650     /* Check if timeout is disabled (set to infinite wait) */
00651     if(Timeout != HAL_MAX_DELAY)
00652     {
00653       if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
00654       {
00655         /* Update ADC state machine to timeout */
00656         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
00657
00658         /* Process unlocked */
00659         __HAL_UNLOCK(hadc);
00660
00661         return HAL_TIMEOUT;
00662       }
00663     }
00664   }
00665
00666   /* Next, to clear the polled flag as well as to update the handle State,
00667      JEOS is checked and the relevant configuration registers are retrieved.
00668      JQM, JAUTO and CONT bits will have to be read for the State update,
00669      AUTDLY for JEOS clearing. */
00670   /*   1. Check whether or not JEOS is set */
00671   if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_JEOS))
00672   {
00673     tmp_jeos_raised = 0;
00674   }
00675   /*  2. Check whether or not hadc is the handle of a Slave ADC with dual
00676         injected conversions enabled. */
00677   if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc) == RESET)
00678   {
00679     /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
00680         check JQM and AUTDLY bits directly in ADC CFGR register */
00681     tmp_cfgr_jqm_autdly = READ_REG(hadc->Instance->CFGR);
00682   }
00683   else
00684   {
00685     /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
00686         need to check JQM and AUTDLY bits of Master ADC CFGR register */
00687     tmpADC_Master = ADC_MASTER_REGISTER(hadc);
00688     tmp_cfgr_jqm_autdly = READ_REG(tmpADC_Master->CFGR);
00689   }
00690   /* 3. Check whether or not hadc is the handle of a Slave ADC with dual
00691         regular conversions enabled. */
00692   if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
00693   {
00694     /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
00695        check JAUTO and CONT bits directly in ADC CFGR register */
00696     tmp_cfgr = READ_REG(hadc->Instance->CFGR);
00697   }
00698   else
00699   {
00700     /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
00701       check JAUTO and CONT bits of Master ADC CFGR register */
00702     tmpADC_Master = ADC_MASTER_REGISTER(hadc);
00703     tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
00704   }
00705
00706
00707
00708   /* Clear polled flag */
00709   if (tmp_Flag_End == ADC_FLAG_JEOS)
00710   {
00711     /* Clear end of sequence JEOS flag of injected group if low power feature */
00712     /* "LowPowerAutoWait " is disabled, to not interfere with this feature.   */
00713     /* For injected groups, no new conversion will start before JEOS is       */
00714     /* cleared.                                                               */
00715     /* Note that 1. reading ADCx_JDRy clears JEOC.                            */
00716     /*           2. in MultiMode with dual injected conversions enabled,      */
00717     /*              Master AUTDLY bit must be checked                         */
00718
00719     if (READ_BIT (tmp_cfgr_jqm_autdly, ADC_CFGR_AUTDLY) == RESET)
00720     {
00721       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
00722     }
00723   }
00724   else
00725   {
00726     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
00727   }
00728
00729
00730   /* Update ADC state machine */
00731   SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
00732   /* Are injected conversions over ? This is the case if JEOS is set AND
00733         - injected conversions are software-triggered when injected queue management is disabled
00734         OR
00735         - autoinjection is enabled, continuous mode is disabled,
00736           and regular conversions are software-triggered */
00737
00738   if (tmp_jeos_raised)
00739   {
00740     if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm_autdly, ADC_CFGR_JQM) != ADC_CFGR_JQM))
00741         && (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) &&
00742             (ADC_IS_SOFTWARE_START_REGULAR(hadc)))    ))
00743     {
00744       /* Clear HAL_ADC_STATE_INJ_BUSY bit */
00745       CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00746       /* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */
00747       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
00748       {
00749         SET_BIT(hadc->State, HAL_ADC_STATE_READY);
00750       }
00751     }
00752   }
00753
00754
00755
00756   /* Return API HAL status */
00757   return HAL_OK;
00758 }
00759
00760
00761
00762 /**
00763   * @brief  Enable ADC, start conversion of injected group with interruption.
00764   * @note   Interruptions enabled in this function according to initialization
00765   *         setting : JEOC (end of conversion) or JEOS (end of sequence)
00766   * @note   Case of multimode enabled (when multimode feature is enabled):
00767   *         HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
00768   *         then for ADC master.
00769   *         For ADC slave, ADC is enabled only (conversion is not started).
00770   *         For ADC master, ADC is enabled and multimode conversion is started.
00771   * @param  hadc: ADC handle.
00772   * @retval HAL status.
00773   */
00774 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
00775 {
00776   HAL_StatusTypeDef tmp_hal_status  = HAL_OK;
00777
00778   /* Check the parameters */
00779   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00780
00781   if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc))
00782   {
00783     return HAL_BUSY;
00784   }
00785   else
00786   {
00787
00788     /* In case of software trigger detection enabled, JQDIS must be set
00789       (which can be done only if ADSTART and JADSTART are both cleared).
00790        If JQDIS is not set at that point, returns an error
00791        - since software trigger detection is disabled. User needs to
00792        resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
00793        - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
00794          the queue is empty */
00795     if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET)
00796         && (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET))
00797     {
00798       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00799       return HAL_ERROR;
00800     }
00801
00802     /* Process locked */
00803     __HAL_LOCK(hadc);
00804
00805     /* Enable the ADC peripheral */
00806     tmp_hal_status  = ADC_Enable(hadc);
00807
00808     /* Start conversion if ADC is effectively enabled */
00809     if (tmp_hal_status  == HAL_OK)
00810     {
00811       /* Check if a regular conversion is ongoing */
00812       if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY))
00813       {
00814         /* Reset ADC error code field related to injected conversions only */
00815         CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
00816       }
00817       else
00818       {
00819         /* Set ADC error code to none */
00820         ADC_CLEAR_ERRORCODE(hadc);
00821       }
00822       /* Clear HAL_ADC_STATE_READY and HAL_ADC_STATE_INJ_EOC bits, set HAL_ADC_STATE_INJ_BUSY bit */
00823       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_INJ_EOC), HAL_ADC_STATE_INJ_BUSY);
00824
00825       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
00826         - by default if ADC is Master or Independent
00827         - if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */
00828       if (ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
00829       {
00830         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00831       }
00832
00833       /* Clear injected group conversion flag */
00834       /* (To ensure of no unknown state from potential previous ADC operations) */
00835       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
00836
00837       /* Enable ADC Injected context queue overflow interrupt if this feature   */
00838       /* is enabled.                                                            */
00839       if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET)
00840       {
00841         __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
00842       }
00843
00844       /* Enable ADC end of conversion interrupt */
00845       switch(hadc->Init.EOCSelection)
00846       {
00847         case ADC_EOC_SEQ_CONV:
00848           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
00849           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
00850           break;
00851         /* case ADC_EOC_SINGLE_CONV */
00852         default:
00853           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
00854           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
00855           break;
00856       }
00857
00858       /* Enable conversion of injected group, if automatic injected conversion  */
00859       /* is disabled.                                                           */
00860       /* If software start has been selected, conversion starts immediately.    */
00861       /* If external trigger has been selected, conversion will start at next   */
00862       /* trigger event.                                                         */
00863       /* Case of multimode enabled:                                             */
00864       /* if ADC is slave,                                                       */
00865       /*    - ADC is enabled only (conversion is not started).                  */
00866       /*    - if multimode only concerns regular conversion, ADC is enabled     */
00867       /*     and conversion is started.                                         */
00868       /* If ADC is master or independent,                                       */
00869       /*    - ADC is enabled and conversion is started.                         */
00870
00871       /* Are injected conversions that of a dual Slave ? */
00872       if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
00873       {
00874         /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
00875            set ADSTART only if JAUTO is cleared */
00876         /* Process unlocked */
00877         __HAL_UNLOCK(hadc);
00878         if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
00879         {
00880           SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ;
00881         }
00882       }
00883       else
00884       {
00885         /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
00886            ADSTART is not set */
00887         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00888         /* Process unlocked */
00889         __HAL_UNLOCK(hadc);
00890       }
00891     }
00892     else
00893     {
00894       /* Process unlocked */
00895       __HAL_UNLOCK(hadc);
00896     }
00897
00898     /* Return function status */
00899     return tmp_hal_status;
00900 }
00901 }
00902
00903 /**
00904   * @brief  Stop conversion of injected channels, disable interruption of
00905   *         end-of-conversion, disable ADC peripheral if no regular conversion
00906   *         is on going.
00907   * @note   If ADC must be disabled and if conversion is on going on
00908   *         regular group, function HAL_ADC_Stop must be used to stop both
00909   *         injected and regular groups, and disable the ADC.
00910   * @note   If injected group mode auto-injection is enabled,
00911   *         function HAL_ADC_Stop must be used.
00912   * @note   Case of multimode enabled (when multimode feature is available):
00913   *         HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
00914   *         then for ADC slave.
00915   *         For ADC master, conversion is stopped and ADC is disabled.
00916   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
00917   *         has already stopped conversion of ADC slave).
00918   * @note   In case of auto-injection mode, HAL_ADC_Stop() must be used.
00919   * @param  hadc: ADC handle
00920   * @retval HAL status
00921   */
00922 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
00923 {
00924   HAL_StatusTypeDef tmp_hal_status  = HAL_OK;
00925
00926   /* Check the parameters */
00927   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00928
00929   /* Process locked */
00930   __HAL_LOCK(hadc);
00931
00932   /* 1. Stop potential conversion on going on injected group only. */
00933   tmp_hal_status  = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
00934
00935   /* Disable ADC peripheral if injected conversions are effectively stopped   */
00936   /* and if no conversion on the other group (regular group) is intended to   */
00937   /* continue.                                                                */
00938   if (tmp_hal_status  == HAL_OK)
00939   {
00940     /* Disable ADC end of conversion interrupt for injected channels */
00941     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
00942
00943     if ((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET))
00944     {
00945       /* 2. Disable the ADC peripheral */
00946       tmp_hal_status  = ADC_Disable(hadc);
00947
00948       /* Check if ADC is effectively disabled */
00949       if (tmp_hal_status  == HAL_OK)
00950       {
00951         /* Change ADC state */
00952         /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
00953         ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
00954       }
00955     }
00956     /* Conversion on injected group is stopped, but ADC not disabled since    */
00957     /* conversion on regular group is still running.                          */
00958     else
00959     {
00960       /* Clear HAL_ADC_STATE_INJ_BUSY bit */
00961       CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00962     }
00963   }
00964
00965   /* Process unlocked */
00966   __HAL_UNLOCK(hadc);
00967
00968   /* Return function status */
00969   return tmp_hal_status ;
00970 }
00971
00972 /**
00973   * @brief  Enable ADC, start MultiMode conversion and transfer regular results through DMA.
00974   * @note   Multimode must have been previously configured using
00975   *         HAL_ADCEx_MultiModeConfigChannel() function.
00976   *         Interruptions enabled in this function:
00977   *          overrun, DMA half transfer, DMA transfer complete.
00978   *         Each of these interruptions has its dedicated callback function.
00979   * @note   State field of Slave ADC handle is not updated in this configuration:
00980   *          user should not rely on it for information related to Slave regular
00981   *         conversions.
00982   * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
00983   * @param  pData: Destination Buffer address.
00984   * @param  Length: Length of data to be transferred from ADC peripheral to memory (in bytes).
00985   * @retval HAL status
00986   */
00987 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
00988 {
00989   HAL_StatusTypeDef tmp_hal_status  = HAL_OK;
00990   ADC_HandleTypeDef tmphadcSlave;
00991   ADC_Common_TypeDef *tmpADC_Common;
00992
00993   /* Check the parameters */
00994   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
00995   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00996   assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
00997
00998   if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
00999   {
01000     return HAL_BUSY;
01001   }
01002   else
01003   {
01004     /* Process locked */
01005     __HAL_LOCK(hadc);
01006
01007     /* Set a temporary handle of the ADC slave associated to the ADC master   */
01008     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
01009
01010     if (tmphadcSlave.Instance == NULL)
01011     {
01012       /* Update ADC state machine to error */
01013       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01014
01015       /* Process unlocked */
01016       __HAL_UNLOCK(hadc);
01017
01018       return HAL_ERROR;
01019     }
01020
01021
01022     /* Enable the ADC peripherals: master and slave (in case if not already   */
01023     /* enabled previously)                                                    */
01024     tmp_hal_status  = ADC_Enable(hadc);
01025     if (tmp_hal_status  == HAL_OK)
01026     {
01027       tmp_hal_status  = ADC_Enable(&tmphadcSlave);
01028     }
01029
01030     /* Start multimode conversion of ADCs pair */
01031     if (tmp_hal_status  == HAL_OK)
01032     {
01033       /* Update Master State */
01034       /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
01035       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
01036
01037
01038       /* Set ADC error code to none */
01039       ADC_CLEAR_ERRORCODE(hadc);
01040
01041
01042       /* Set the DMA transfer complete callback */
01043       hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
01044
01045       /* Set the DMA half transfer complete callback */
01046       hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
01047
01048       /* Set the DMA error callback */
01049       hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
01050
01051       /* Pointer to the common control register  */
01052       tmpADC_Common = ADC12_COMMON_REGISTER(hadc);
01053
01054
01055       /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
01056       /* start (in case of SW start):                                           */
01057
01058       /* Clear regular group conversion flag and overrun flag */
01059       /* (To ensure of no unknown state from potential previous ADC operations) */
01060       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
01061
01062       /* Enable ADC overrun interrupt */
01063       __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
01064
01065       /* Start the DMA channel */
01066       HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
01067
01068       /* Enable conversion of regular group.                                    */
01069       /* Process unlocked */
01070       __HAL_UNLOCK(hadc);
01071       /* If software start has been selected, conversion starts immediately.    */
01072       /* If external trigger has been selected, conversion will start at next   */
01073       /* trigger event.                                                         */
01074       SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
01075
01076     }
01077     else
01078     {
01079       /* Process unlocked */
01080       __HAL_UNLOCK(hadc);
01081     }
01082
01083     /* Return function status */
01084     return tmp_hal_status;
01085   }
01086 }
01087
01088 /**
01089   * @brief  Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
01090   * @note   Multimode is kept enabled after this function. MultiMode DMA bits
01091   *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable
01092   *         Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
01093   *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
01094   *         resort to HAL_ADCEx_DisableMultiMode() API.
01095   * @note   In case of DMA configured in circular mode, function
01096   *         HAL_ADC_Stop_DMA() must be called after this function with handle of
01097   *         ADC slave, to properly disable the DMA channel.
01098   * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
01099   * @retval HAL status
01100   */
01101 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
01102 {
01103   HAL_StatusTypeDef tmp_hal_status  = HAL_OK;
01104   uint32_t tickstart;
01105   ADC_HandleTypeDef tmphadcSlave;
01106
01107   /* Check the parameters */
01108   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
01109
01110   /* Process locked */
01111   __HAL_LOCK(hadc);
01112
01113
01114   /* 1. Stop potential multimode conversion on going, on regular and injected groups */
01115   tmp_hal_status  = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
01116
01117   /* Disable ADC peripheral if conversions are effectively stopped */
01118   if (tmp_hal_status  == HAL_OK)
01119   {
01120     /* Set a temporary handle of the ADC slave associated to the ADC master   */
01121     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
01122
01123     if (tmphadcSlave.Instance == NULL)
01124     {
01125       /* Update ADC state machine to error */
01126       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01127
01128       /* Process unlocked */
01129       __HAL_UNLOCK(hadc);
01130
01131       return HAL_ERROR;
01132     }
01133
01134     /* Procedure to disable the ADC peripheral: wait for conversions          */
01135     /* effectively stopped (ADC master and ADC slave), then disable ADC       */
01136
01137     /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
01138     tickstart = HAL_GetTick();
01139
01140     while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)          ||
01141           ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave)   )
01142     {
01143       if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
01144       {
01145         /* Update ADC state machine to error */
01146         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
01147
01148         /* Process unlocked */
01149         __HAL_UNLOCK(hadc);
01150
01151         return HAL_ERROR;
01152       }
01153     }
01154
01155     /* Disable the DMA channel (in case of DMA in circular mode or stop       */
01156     /* while DMA transfer is on going)                                        */
01157     /* Note: DMA channel of ADC slave should be stopped after this function   */
01158     /*       with HAL_ADC_Stop_DMA() API.                                     */
01159     tmp_hal_status  = HAL_DMA_Abort(hadc->DMA_Handle);
01160
01161     /* Check if DMA channel effectively disabled */
01162     if (tmp_hal_status  == HAL_ERROR)
01163     {
01164       /* Update ADC state machine to error */
01165       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
01166     }
01167
01168     /* Disable ADC overrun interrupt */
01169     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01170
01171
01172
01173     /* 2. Disable the ADC peripherals: master and slave */
01174     /* Update "tmp_hal_status " only if DMA channel disabling passed, to keep in */
01175     /* memory a potential failing status.                                     */
01176     if (tmp_hal_status  == HAL_OK)
01177     {
01178       /* Check if ADC are effectively disabled */
01179       if ((ADC_Disable(hadc) == HAL_OK)         &&
01180           (ADC_Disable(&tmphadcSlave) == HAL_OK)   )
01181       {
01182         tmp_hal_status  = HAL_OK;
01183       }
01184     }
01185     else
01186     {
01187       ADC_Disable(hadc);
01188       ADC_Disable(&tmphadcSlave);
01189     }
01190     /* Change ADC state (ADC master) */
01191     /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
01192     ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
01193
01194   }
01195
01196   /* Process unlocked */
01197   __HAL_UNLOCK(hadc);
01198
01199   /* Return function status */
01200   return tmp_hal_status ;
01201 }
01202
01203
01204 /**
01205   * @brief  Return the last ADC Master and Slave regular conversions results when in multimode configuration.
01206   * @param  hadc: ADC handle of ADC Master (handle of ADC Slave must not be used)
01207   * @retval The converted data values.
01208   */
01209 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
01210 {
01211   ADC_Common_TypeDef *tmpADC_Common;
01212
01213   /* Check the parameters */
01214   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
01215
01216   /* Pointer to the common control register  */
01217   tmpADC_Common = ADC12_COMMON_REGISTER(hadc);
01218
01219   /* Return the multi mode conversion value */
01220   return tmpADC_Common->CDR;
01221 }
01222
01223
01224 /**
01225   * @brief  Get ADC injected group conversion result.
01226   * @note   Reading register JDRx automatically clears ADC flag JEOC
01227   *         (ADC group injected end of unitary conversion).
01228   * @note   This function does not clear ADC flag JEOS
01229   *         (ADC group injected end of sequence conversion)
01230   *         Occurrence of flag JEOS rising:
01231   *          - If sequencer is composed of 1 rank, flag JEOS is equivalent
01232   *            to flag JEOC.
01233   *          - If sequencer is composed of several ranks, during the scan
01234   *            sequence flag JEOC only is raised, at the end of the scan sequence
01235   *            both flags JEOC and EOS are raised.
01236   *         Flag JEOS must not be cleared by this function because
01237   *         it would not be compliant with low power features
01238   *         (feature low power auto-wait, not available on all STM32 families).
01239   *         To clear this flag, either use function:
01240   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
01241   *         model polling: @ref HAL_ADCEx_InjectedPollForConversion()
01242   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
01243   * @param  hadc: ADC handle
01244   * @param  InjectedRank: the converted ADC injected rank.
01245   *          This parameter can be one of the following values:
01246   *            @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
01247   *            @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
01248   *            @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
01249   *            @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
01250   * @retval ADC group injected conversion data
01251   */
01252 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
01253 {
01254   uint32_t tmp_jdr = 0;
01255
01256   /* Check the parameters */
01257   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01258   assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
01259
01260
01261   /* Get ADC converted value */
01262   switch(InjectedRank)
01263   {
01264     case ADC_INJECTED_RANK_4:
01265       tmp_jdr = hadc->Instance->JDR4;
01266       break;
01267     case ADC_INJECTED_RANK_3:
01268       tmp_jdr = hadc->Instance->JDR3;
01269       break;
01270     case ADC_INJECTED_RANK_2:
01271       tmp_jdr = hadc->Instance->JDR2;
01272       break;
01273     case ADC_INJECTED_RANK_1:
01274     default:
01275       tmp_jdr = hadc->Instance->JDR1;
01276       break;
01277   }
01278
01279   /* Return ADC converted value */
01280   return tmp_jdr;
01281 }
01282
01283 /**
01284   * @brief  Injected conversion complete callback in non-blocking mode.
01285   * @param  hadc: ADC handle
01286   * @retval None
01287   */
01288 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
01289 {
01290   /* Prevent unused argument(s) compilation warning */
01291   UNUSED(hadc);
01292
01293   /* NOTE : This function should not be modified. When the callback is needed,
01294             function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
01295   */
01296 }
01297
01298
01299 /**
01300   * @brief  Injected context queue overflow callback.
01301   * @note   This callback is called if injected context queue is enabled
01302             (parameter "QueueInjectedContext" in injected channel configuration)
01303             and if a new injected context is set when queue is full (maximum 2
01304             contexts).
01305   * @param  hadc: ADC handle
01306   * @retval None
01307   */
01308 __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc)
01309 {
01310   /* Prevent unused argument(s) compilation warning */
01311   UNUSED(hadc);
01312
01313   /* NOTE : This function should not be modified. When the callback is needed,
01314             function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
01315   */
01316 }
01317
01318 /**
01319   * @brief  Analog watchdog 2 callback in non-blocking mode.
01320   * @param  hadc: ADC handle
01321   * @retval None
01322   */
01323 __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc)
01324 {
01325   /* Prevent unused argument(s) compilation warning */
01326   UNUSED(hadc);
01327
01328   /* NOTE : This function should not be modified. When the callback is needed,
01329             function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
01330   */
01331 }
01332
01333 /**
01334   * @brief  Analog watchdog 3 callback in non-blocking mode.
01335   * @param  hadc: ADC handle
01336   * @retval None
01337   */
01338 __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc)
01339 {
01340   /* Prevent unused argument(s) compilation warning */
01341   UNUSED(hadc);
01342
01343   /* NOTE : This function should not be modified. When the callback is needed,
01344             function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
01345   */
01346 }
01347
01348
01349 /**
01350   * @brief  End Of Sampling callback in non-blocking mode.
01351   * @param  hadc: ADC handle
01352   * @retval None
01353   */
01354 __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc)
01355 {
01356   /* Prevent unused argument(s) compilation warning */
01357   UNUSED(hadc);
01358
01359   /* NOTE : This function should not be modified. When the callback is needed,
01360             function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
01361   */
01362 }
01363
01364 /**
01365   * @brief  Stop ADC conversion of regular group (and injected channels in
01366   *         case of auto_injection mode), disable ADC peripheral if no
01367   *         conversion is on going on injected group.
01368   * @param  hadc: ADC handle
01369   * @retval HAL status.
01370   */
01371 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc)
01372 {
01373   HAL_StatusTypeDef tmp_hal_status  = HAL_OK;
01374
01375   /* Check the parameters */
01376   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01377
01378   /* Process locked */
01379   __HAL_LOCK(hadc);
01380
01381   /* 1. Stop potential regular conversion on going */
01382   tmp_hal_status  = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
01383
01384   /* Disable ADC peripheral if regular conversions are effectively stopped
01385      and if no injected conversions are on-going */
01386   if (tmp_hal_status  == HAL_OK)
01387   {
01388     /* Clear HAL_ADC_STATE_REG_BUSY bit */
01389     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01390
01391     if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
01392     {
01393       /* 2. Disable the ADC peripheral */
01394       tmp_hal_status  = ADC_Disable(hadc);
01395
01396       /* Check if ADC is effectively disabled */
01397       if (tmp_hal_status  == HAL_OK)
01398       {
01399         /* Change ADC state */
01400         /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
01401         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
01402       }
01403     }
01404     /* Conversion on injected group is stopped, but ADC not disabled since    */
01405     /* conversion on regular group is still running.                          */
01406     else
01407     {
01408       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
01409     }
01410   }
01411
01412   /* Process unlocked */
01413   __HAL_UNLOCK(hadc);
01414
01415   /* Return function status */
01416   return tmp_hal_status ;
01417 }
01418
01419
01420 /**
01421   * @brief  Stop ADC conversion of ADC groups regular and injected,
01422   *         disable interrution of end-of-conversion,
01423   *         disable ADC peripheral if no conversion is on going
01424   *         on injected group.
01425   * @param  hadc: ADC handle
01426   * @retval HAL status.
01427   */
01428 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc)
01429 {
01430   HAL_StatusTypeDef tmp_hal_status  = HAL_OK;
01431
01432   /* Check the parameters */
01433   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01434
01435   /* Process locked */
01436   __HAL_LOCK(hadc);
01437
01438   /* 1. Stop potential regular conversion on going */
01439   tmp_hal_status  = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
01440
01441   /* Disable ADC peripheral if conversions are effectively stopped
01442     and if no injected conversion is on-going */
01443   if (tmp_hal_status  == HAL_OK)
01444   {
01445     /* Clear HAL_ADC_STATE_REG_BUSY bit */
01446     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01447
01448     /* Disable all regular-related interrupts */
01449     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
01450
01451     /* 2. Disable ADC peripheral if no injected conversions are on-going */
01452     if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
01453     {
01454       tmp_hal_status  = ADC_Disable(hadc);
01455       /* if no issue reported */
01456       if (tmp_hal_status  == HAL_OK)
01457       {
01458         /* Change ADC state */
01459         /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
01460         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
01461       }
01462     }
01463     else
01464     {
01465       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
01466     }
01467   }
01468
01469   /* Process unlocked */
01470   __HAL_UNLOCK(hadc);
01471
01472   /* Return function status */
01473   return tmp_hal_status ;
01474 }
01475
01476
01477 /**
01478   * @brief  Stop ADC conversion of regular group (and injected group in
01479   *         case of auto_injection mode), disable ADC DMA transfer, disable
01480   *         ADC peripheral if no conversion is on going
01481   *         on injected group.
01482   * @note   HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
01483   *         For multimode (when multimode feature is available),
01484   *         HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
01485   * @param  hadc: ADC handle
01486   * @retval HAL status.
01487   */
01488 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc)
01489 {
01490   HAL_StatusTypeDef tmp_hal_status  = HAL_OK;
01491
01492   /* Check the parameters */
01493   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01494
01495   /* Process locked */
01496   __HAL_LOCK(hadc);
01497
01498   /* 1. Stop potential regular conversion on going */
01499   tmp_hal_status  = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
01500
01501   /* Disable ADC peripheral if conversions are effectively stopped
01502      and if no injected conversion is on-going */
01503   if (tmp_hal_status  == HAL_OK)
01504   {
01505     /* Clear HAL_ADC_STATE_REG_BUSY bit */
01506     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01507
01508     /* Disable ADC DMA */
01509     MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 |ADC_CFGR_DMNGT_1, 0);
01510
01511     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
01512     /* while DMA transfer is on going)                                        */
01513     tmp_hal_status  = HAL_DMA_Abort(hadc->DMA_Handle);
01514
01515     /* Check if DMA channel effectively disabled */
01516     if (tmp_hal_status  != HAL_OK)
01517     {
01518       /* Update ADC state machine to error */
01519       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
01520     }
01521
01522     /* Disable ADC overrun interrupt */
01523     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01524
01525     /* 2. Disable the ADC peripheral */
01526     /* Update "tmp_hal_status " only if DMA channel disabling passed, to keep in */
01527     /* memory a potential failing status.                                     */
01528     if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
01529     {
01530       if (tmp_hal_status  == HAL_OK)
01531       {
01532         tmp_hal_status  = ADC_Disable(hadc);
01533       }
01534       else
01535       {
01536         ADC_Disable(hadc);
01537       }
01538
01539       /* Check if ADC is effectively disabled */
01540       if (tmp_hal_status  == HAL_OK)
01541       {
01542         /* Change ADC state */
01543         /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
01544         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
01545       }
01546     }
01547     else
01548     {
01549       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
01550     }
01551   }
01552
01553   /* Process unlocked */
01554   __HAL_UNLOCK(hadc);
01555
01556   /* Return function status */
01557   return tmp_hal_status ;
01558 }
01559
01560
01561
01562 /**
01563   * @brief  Stop DMA-based MultiMode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
01564   * @note   MultiMode is kept enabled after this function. MultiMode DMA bits
01565   *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable
01566   *         MultiMode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
01567   *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
01568   *         resort to HAL_ADCEx_DisableMultiMode() API.
01569   * @note   In case of DMA configured in circular mode, function
01570   *         HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
01571   *         ADC slave, to properly disable the DMA channel.
01572   * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
01573   * @retval HAL status
01574   */
01575 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc)
01576 {
01577   HAL_StatusTypeDef tmp_hal_status  = HAL_OK;
01578   uint32_t tickstart;
01579   ADC_HandleTypeDef tmphadcSlave;
01580
01581   /* Check the parameters */
01582   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
01583
01584   /* Process locked */
01585   __HAL_LOCK(hadc);
01586
01587
01588   /* 1. Stop potential multimode conversion on going, on regular groups */
01589   tmp_hal_status  = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
01590
01591   /* Disable ADC peripheral if conversions are effectively stopped */
01592   if (tmp_hal_status  == HAL_OK)
01593   {
01594     /* Clear HAL_ADC_STATE_REG_BUSY bit */
01595     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01596
01597     /* Set a temporary handle of the ADC slave associated to the ADC master   */
01598     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
01599
01600     if (tmphadcSlave.Instance == NULL)
01601     {
01602       /* Update ADC state machine to error */
01603       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01604
01605       /* Process unlocked */
01606       __HAL_UNLOCK(hadc);
01607
01608       return HAL_ERROR;
01609     }
01610
01611     /* Procedure to disable the ADC peripheral: wait for conversions          */
01612     /* effectively stopped (ADC master and ADC slave), then disable ADC       */
01613
01614     /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
01615     tickstart = HAL_GetTick();
01616
01617     while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)          ||
01618           ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave)   )
01619     {
01620       if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
01621       {
01622         /* Update ADC state machine to error */
01623         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
01624
01625         /* Process unlocked */
01626         __HAL_UNLOCK(hadc);
01627
01628         return HAL_ERROR;
01629       }
01630     }
01631
01632     /* Disable the DMA channel (in case of DMA in circular mode or stop       */
01633     /* while DMA transfer is on going)                                        */
01634     /* Note: DMA channel of ADC slave should be stopped after this function   */
01635     /* with HAL_ADCEx_RegularStop_DMA() API.                                  */
01636     tmp_hal_status  = HAL_DMA_Abort(hadc->DMA_Handle);
01637
01638     /* Check if DMA channel effectively disabled */
01639     if (tmp_hal_status  != HAL_OK)
01640     {
01641       /* Update ADC state machine to error */
01642       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
01643     }
01644
01645     /* Disable ADC overrun interrupt */
01646     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01647
01648
01649
01650     /* 2. Disable the ADC peripherals: master and slave if no injected        */
01651     /*   conversion is on-going.                                              */
01652     /* Update "tmp_hal_status " only if DMA channel disabling passed, to keep in */
01653     /* memory a potential failing status.                                     */
01654     if (tmp_hal_status  == HAL_OK)
01655     {
01656       if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
01657       {
01658         tmp_hal_status  =  ADC_Disable(hadc);
01659         if (tmp_hal_status  == HAL_OK)
01660         {
01661           if (ADC_IS_CONVERSION_ONGOING_INJECTED(&tmphadcSlave) == RESET)
01662           {
01663             tmp_hal_status  =  ADC_Disable(&tmphadcSlave);
01664           }
01665         }
01666       }
01667
01668       if (tmp_hal_status  == HAL_OK)
01669       {
01670         /* Both Master and Slave ADC's could be disabled. Update Master State */
01671         /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
01672         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
01673       }
01674       else
01675       {
01676         /* injected (Master or Slave) conversions are still on-going,
01677            no Master State change */
01678       }
01679
01680     }
01681
01682   }
01683
01684   /* Process unlocked */
01685   __HAL_UNLOCK(hadc);
01686
01687   /* Return function status */
01688   return tmp_hal_status ;
01689 }
01690
01691 /**
01692   * @}
01693   */
01694
01695 /** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
01696   * @brief    ADC Extended Peripheral Control functions
01697   *
01698 @verbatim
01699  ===============================================================================
01700              ##### Peripheral Control functions #####
01701  ===============================================================================
01702     [..]  This section provides functions allowing to:
01703       (+) Configure channels on injected group
01704       (+) Configure multimode when multimode feature is available
01705       (+) Enable or Disable Injected Queue
01706       (+) Disable ADC voltage regulator
01707       (+) Enter ADC deep-power-down mode
01708
01709
01710 @endverbatim
01711   * @{
01712   */
01713
01714 /**
01715   * @brief  Configure a channel to be assigned to ADC group injected.
01716   * @note   Possibility to update parameters on the fly:
01717   *         This function initializes injected group, following calls to this
01718   *         function can be used to reconfigure some parameters of structure
01719   *         "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
01720   *         The setting of these parameters is conditioned to ADC state:
01721   *         Refer to comments of structure "ADC_InjectionConfTypeDef".
01722   * @note   In case of usage of internal measurement channels:
01723   *         Vbat/VrefInt/TempSensor.
01724   *         These internal paths can be disabled using function
01725   *         HAL_ADC_DeInit().
01726   * @note   Caution: For Injected Context Queue use, a context must be fully
01727   *         defined before start of injected conversion. All channels are configured
01728   *         consecutively for the same ADC instance. Therefore, the number of calls to
01729   *         HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter
01730   *         InjectedNbrOfConversion for each context.
01731   *  - Example 1: If 1 context is intended to be used (or if there is no use of the
01732   *    Injected Queue Context feature) and if the context contains 3 injected ranks
01733   *    (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be
01734   *    called once for each channel (i.e. 3 times) before starting a conversion.
01735   *    This function must not be called to configure a 4th injected channel:
01736   *    it would start a new context into context queue.
01737   *  - Example 2: If 2 contexts are intended to be used and each of them contains
01738   *    3 injected ranks (InjectedNbrOfConversion = 3),
01739   *    HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
01740   *    for each context (3 channels x 2 contexts = 6 calls). Conversion can
01741   *    start once the 1st context is set, that is after the first three
01742   *    HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
01743   * @param  hadc: ADC handle
01744   * @param  sConfigInjected: Structure of ADC injected group and ADC channel for
01745   *         injected group.
01746   * @retval HAL status
01747   */
01748 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
01749 {
01750   HAL_StatusTypeDef tmp_hal_status  = HAL_OK;
01751   ADC_Common_TypeDef *tmpADC_Common;
01752   uint32_t tmpOffsetShifted;
01753   uint32_t WaitLoopIndex = 0;
01754
01755
01756   uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0;
01757
01758   /* Check the parameters */
01759   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01760   assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
01761   assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
01762   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
01763   assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
01764   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
01765   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
01766   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
01767   assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
01768   assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
01769   assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
01770   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode));
01771
01772   if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
01773   {
01774     assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
01775     assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
01776     assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
01777   }
01778
01779   /* Check offset range according to oversampling setting */
01780   if (hadc->Init.OversamplingMode == ENABLE)
01781   {
01782     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset/(hadc->Init.Oversampling.Ratio+1U)));
01783   }
01784   else
01785   {
01786     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
01787   }
01788
01789   /* JDISCEN and JAUTO bits can't be set at the same time  */
01790   assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
01791
01792   /*  DISCEN and JAUTO bits can't be set at the same time */
01793   assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
01794
01795   /* Only rank 1 can be configured if there is only one conversion or if Scan conversion mode is disabled */
01796   assert_param(!(((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) || (sConfigInjected->InjectedNbrOfConversion == 1)  ) && (sConfigInjected->InjectedRank != ADC_INJECTED_RANK_1)));
01797
01798
01799   /* Verification of channel number.
01800      For ADC1 and ADC2, channels 1 to 15 are available in differential mode,
01801                         channels 16 to 18 can be only used in single-ended mode.
01802      For ADC3, channels 1 to 11 are available in differential mode,
01803                 channels 12 to 18 can only be used in single-ended mode.  */
01804   if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
01805   {
01806     assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
01807   }
01808   else
01809   {
01810     if (hadc->Instance == ADC3)
01811     {
01812       assert_param(IS_ADC3_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
01813     }
01814     else if(hadc->Instance == ADC2)
01815     {
01816       assert_param(IS_ADC2_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
01817     }
01818     else
01819     {
01820       assert_param(IS_ADC1_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
01821     }
01822   }
01823
01824   /* Process locked */
01825   __HAL_LOCK(hadc);
01826
01827
01828
01829   /* Configuration of Injected group sequencer.                               */
01830   /* Hardware constraint: Must fully define injected context register JSQR    */
01831   /* before make it entering into injected sequencer queue.                   */
01832   /*                                                                          */
01833   /* - if scan mode is disabled:                                              */
01834   /*    * Injected channels sequence length is set to 0x00: 1 channel         */
01835   /*      converted (channel on injected rank 1)                              */
01836   /*      Parameter "InjectedNbrOfConversion" is discarded.                   */
01837   /*    * Injected context register JSQR setting is simple: register is fully */
01838   /*      defined on one call of this function (for injected rank 1) and can  */
01839   /*      be entered into queue directly.                                     */
01840   /* - if scan mode is enabled:                                               */
01841   /*    * Injected channels sequence length is set to parameter               */
01842   /*      "InjectedNbrOfConversion".                                          */
01843   /*    * Injected context register JSQR setting more complex: register is    */
01844   /*      fully defined over successive calls of this function, for each      */
01845   /*      injected channel rank. It is entered into queue only when all       */
01846   /*      injected ranks have been set.                                       */
01847   /*   Note: Scan mode is not present by hardware on this device, but used    */
01848   /*   by software for alignment over all STM32 devices.                      */
01849
01850   if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)  ||
01851       (sConfigInjected->InjectedNbrOfConversion == 1)  )
01852   {
01853     /* Configuration of context register JSQR:                                */
01854     /*  - number of ranks in injected group sequencer: fixed to 1st rank      */
01855     /*    (scan mode disabled, only rank 1 used)                              */
01856     /*  - external trigger to start conversion                                */
01857     /*  - external trigger polarity                                           */
01858     /*  - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
01859
01860     if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
01861     {
01862       /* Enable external trigger if trigger selection is different of         */
01863       /* software start.                                                      */
01864       /* Note: This configuration keeps the hardware feature of parameter     */
01865       /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
01866       /*       software start.                                                */
01867       if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
01868           && (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
01869       {
01870         tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) |
01871                                              sConfigInjected->ExternalTrigInjecConv     |
01872                                              sConfigInjected->ExternalTrigInjecConvEdge                                );
01873       }
01874       else
01875       {
01876         tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) );
01877       }
01878
01879
01880       MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt);
01881       /* For debug and informative reasons, hadc handle saves JSQR setting */
01882       hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
01883
01884     }
01885   }
01886   else
01887   {
01888     /* Case of scan mode enabled, several channels to set into injected group */
01889     /* sequencer.                                                             */
01890     /*                                                                        */
01891     /* Procedure to define injected context register JSQR over successive     */
01892     /* calls of this function, for each injected channel rank:                */
01893     /* 1. Start new context and set parameters related to all injected        */
01894     /*    channels: injected sequence length and trigger.                     */
01895
01896     /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
01897     /*   call of the context under setting                                    */
01898     if (hadc->InjectionConfig.ChannelCount == 0)
01899     {
01900       /* Initialize number of channels that will be configured on the context */
01901       /*  being built                                                         */
01902       hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
01903       /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
01904          call, this context will be written in JSQR register at the last call.
01905          At this point, the context is merely reset  */
01906       hadc->InjectionConfig.ContextQueue = (uint32_t)0x00000000;
01907
01908       /* Configuration of context register JSQR:                              */
01909       /*  - number of ranks in injected group sequencer                       */
01910       /*  - external trigger to start conversion                              */
01911       /*  - external trigger polarity                                         */
01912
01913       /* Enable external trigger if trigger selection is different of         */
01914       /* software start.                                                      */
01915       /* Note: This configuration keeps the hardware feature of parameter     */
01916       /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
01917       /*       software start.                                                */
01918       if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
01919           && (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
01920       {
01921         tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1)              |
01922                                              sConfigInjected->ExternalTrigInjecConv |
01923                                              sConfigInjected->ExternalTrigInjecConvEdge                            );
01924       }
01925       else
01926       {
01927         tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) );
01928       }
01929
01930
01931     } /* if (hadc->InjectionConfig.ChannelCount == 0) */
01932
01933
01934     /* 2. Continue setting of context under definition with parameter       */
01935     /*    related to each channel: channel rank sequence                    */
01936     /* Clear the old JSQx bits for the selected rank */
01937     tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank);
01938
01939     /* Set the JSQx bits for the selected rank */
01940     tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank);
01941
01942     /* Decrease channel count  */
01943     hadc->InjectionConfig.ChannelCount--;
01944
01945
01946     /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel()
01947           call, aggregate the setting to those already built during the previous
01948           HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course)  */
01949     hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt;
01950
01951     /* 4. End of context setting: if this is the last channel set, then write context
01952         into register JSQR and make it enter into queue                   */
01953     if (hadc->InjectionConfig.ChannelCount == 0)
01954     {
01955       MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
01956     }
01957
01958
01959   }
01960
01961   /* Parameters update conditioned to ADC state:                              */
01962   /* Parameters that can be updated when ADC is disabled or enabled without   */
01963   /* conversion on going on injected group:                                   */
01964   /*  - Injected context queue: Queue disable (active context is kept) or     */
01965   /*    enable (context decremented, up to 2 contexts queued)                 */
01966   /*  - Injected discontinuous mode: can be enabled only if auto-injected     */
01967   /*    mode is disabled.                                                     */
01968   if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
01969   {
01970
01971     /* If auto-injected mode is disabled: no constraint                       */
01972     if (sConfigInjected->AutoInjectedConv == DISABLE)
01973     {
01974       MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
01975                                ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext)          |
01976                                ADC_CFGR_INJECT_DISCCONTINUOUS(sConfigInjected->InjectedDiscontinuousConvMode) );
01977     }
01978     /* If auto-injected mode is enabled: Injected discontinuous setting is   */
01979     /* discarded.                                                             */
01980     else
01981     {
01982        MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
01983                   ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) );
01984     }
01985
01986   }
01987
01988   /* Parameters update conditioned to ADC state:                              */
01989   /* Parameters that can be updated when ADC is disabled or enabled without   */
01990   /* conversion on going on regular and injected groups:                      */
01991   /*  - Automatic injected conversion: can be enabled if injected group       */
01992   /*    external triggers are disabled.                                       */
01993   /*  - Channel sampling time                                                 */
01994   /*  - Channel offset                                                        */
01995   if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
01996   {
01997     /* If injected group external triggers are disabled (set to injected      */
01998     /* software start): no constraint                                         */
01999     if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
02000         || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
02001     {
02002       if (sConfigInjected->AutoInjectedConv == ENABLE)
02003       {
02004         SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
02005       }
02006       else
02007       {
02008         CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
02009       }
02010     }
02011     /* If Automatic injected conversion was intended to be set and could not  */
02012     /* due to injected group external triggers enabled, error is reported.    */
02013     else
02014     {
02015       if (sConfigInjected->AutoInjectedConv == ENABLE)
02016       {
02017         /* Update ADC state machine to error */
02018         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02019
02020         tmp_hal_status  = HAL_ERROR;
02021       }
02022       else
02023       {
02024         CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
02025       }
02026     }
02027
02028     if (sConfigInjected->InjecOversamplingMode == ENABLE)
02029     {
02030       assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
02031       assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
02032
02033       /*  JOVSE must be reset in case of triggered regular mode  */
02034       assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS)));
02035
02036       /* Configuration of Injected Oversampler:                                 */
02037       /*  - Oversampling Ratio                                                  */
02038       /*  - Right bit shift                                                     */
02039       /*  - Left  bit shift                                                     */
02040
02041       /* Enable OverSampling mode */
02042
02043       MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_INJ_FIELDS,
02044                                         ADC_CFGR2_JOVSE                          |
02045                                         sConfigInjected->InjecOversampling.Ratio |
02046                                         sConfigInjected->InjecOversampling.RightBitShift);
02047     }
02048     else
02049     {
02050       /* Disable Regular OverSampling */
02051        CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
02052     }
02053      /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */
02054      MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, sConfigInjected->InjectedLeftBitShift);
02055
02056     /* Sampling time configuration of the selected channel */
02057     /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
02058     if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
02059     {
02060       /* Clear the old sample time and set the new one */
02061       MODIFY_REG(hadc->Instance->SMPR2,
02062           ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel),
02063           ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel));
02064     }
02065     else /* if ADC_Channel_0 ... ADC_Channel_9 is selected */
02066     {
02067       /* Clear the old sample time and set the new one */
02068       MODIFY_REG(hadc->Instance->SMPR1,
02069           ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel),
02070           ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel));
02071     }
02072
02073
02074     /* Configure the offset: offset enable/disable, channel, offset value */
02075
02076     /* Shift the offset in function of the selected ADC resolution. */
02077     /* Offset has to be left-aligned on bit 15, the LSB (right bits) are set to 0 */
02078     tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
02079
02080     switch (sConfigInjected->InjectedOffsetNumber)
02081     {
02082       case ADC_OFFSET_1:
02083         /* Configure offset register 1:                                         */
02084         /* - Enable offset                                                      */
02085         /* - Set channel number                                                 */
02086         /* - Set offset value                                                   */
02087         MODIFY_REG(hadc->Instance->OFR1,
02088                   ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH,
02089                   ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);
02090         MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_RSHIFT1, sConfigInjected-> InjectedOffsetRightShift);
02091         /* Enable or disable the signed saturation bit */
02092         if(sConfigInjected->InjectedOffsetSignedSaturation != DISABLE)
02093         {
02094           SET_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
02095         }
02096         else
02097         {
02098           CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
02099         }
02100         break;
02101
02102       case ADC_OFFSET_2:
02103         /* Configure offset register 2:                                         */
02104         /* - Enable offset                                                      */
02105         /* - Set channel number                                                 */
02106         /* - Set offset value                                                   */
02107         /* - Set Right shift after offset application                           */
02108         MODIFY_REG(hadc->Instance->OFR2,
02109                   ADC_OFR2_OFFSET2 | ADC_OFR2_OFFSET2_CH,
02110                   ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);
02111          MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_RSHIFT2, sConfigInjected-> InjectedOffsetRightShift<<1);
02112         /* Enable or disable the signed saturation bit */
02113         if(sConfigInjected->InjectedOffsetSignedSaturation != DISABLE)
02114         {
02115           SET_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE);
02116         }
02117         else
02118         {
02119           CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE);
02120         }
02121         break;
02122
02123       case ADC_OFFSET_3:
02124         /* Configure offset register 3:                                         */
02125         /* - Enable offset                                                      */
02126         /* - Set channel number                                                 */
02127         /* - Set offset value                                                   */
02128         /* - Set Right shift after offset application                           */
02129         MODIFY_REG(hadc->Instance->OFR3,
02130                   ADC_OFR3_OFFSET3 | ADC_OFR3_OFFSET3_CH,
02131                   ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);
02132         MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_RSHIFT3, sConfigInjected-> InjectedOffsetRightShift<<2);
02133         /* Enable or disable the signed saturation bit */
02134         if(sConfigInjected->InjectedOffsetSignedSaturation != DISABLE)
02135         {
02136           SET_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE);
02137         }
02138         else
02139         {
02140           CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE);
02141         }
02142         break;
02143
02144       case ADC_OFFSET_4:
02145         /* Configure offset register 1:                                         */
02146         /* - Enable offset                                                      */
02147         /* - Set channel number                                                 */
02148         /* - Set offset value                                                   */
02149         MODIFY_REG(hadc->Instance->OFR4,
02150                   ADC_OFR4_OFFSET4 | ADC_OFR4_OFFSET4_CH,
02151                   ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);
02152         MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_RSHIFT4, sConfigInjected-> InjectedOffsetRightShift<<3);
02153         /* Enable or disable the signed saturation bit */
02154         if(sConfigInjected->InjectedOffsetSignedSaturation != DISABLE)
02155         {
02156           SET_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
02157         }
02158         else
02159         {
02160           CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
02161         }
02162         break;
02163
02164       /* Case ADC_OFFSET_NONE */
02165       default :
02166         break;
02167     }
02168
02169   } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
02170
02171
02172   /* Parameters update conditioned to ADC state:                              */
02173   /* Parameters that can be updated only when ADC is disabled:                */
02174   /*  - Single or differential mode                                           */
02175   /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
02176   if (ADC_IS_ENABLE(hadc) == RESET)
02177   {
02178     /* Configuration of differential mode */
02179     if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
02180     {
02181       /* Disable differential mode (default mode: single-ended) */
02182       CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
02183     }
02184     else
02185     {
02186       /* Enable differential mode */
02187       SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
02188
02189       /* Sampling time configuration of channel ADC_IN+1 (negative input) */
02190       /* For channels 9 to 15 for ADC1, ADC2, 9 to 11 for ADC3 */
02191       if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_9)
02192       {
02193         /* Clear the old sample time and set the new one */
02194         MODIFY_REG(hadc->Instance->SMPR2,
02195                 ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel +1),
02196                 ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1));
02197       }
02198       else /* For channels 0 to 8 */
02199       {
02200          /* Clear the old sample time and set the new one */
02201         MODIFY_REG(hadc->Instance->SMPR1,
02202             ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel +1),
02203              ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1));
02204       }
02205     }
02206
02207
02208     /* Management of internal measurement channels: Vbat/VrefInt/TempSensor   */
02209     /* internal measurement paths enable: If internal channel selected,       */
02210     /* enable dedicated internal buffers and path.                            */
02211     /* Note: these internal measurement paths can be disabled using           */
02212     /* HAL_ADC_deInit().                                                      */
02213
02214     /* Configuration of common ADC parameters                                 */
02215
02216     if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
02217     {
02218       /* Pointer to the common control register                                 */
02219       tmpADC_Common = ADC12_COMMON_REGISTER(hadc);
02220     }
02221     else
02222     {
02223       /* Pointer to the common control register                                 */
02224       tmpADC_Common = ADC3_COMMON_REGISTER(hadc);
02225     }
02226
02227     /* If the requested internal measurement path has already been enabled,   */
02228     /* bypass the configuration processing.                                   */
02229     if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) &&
02230           (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN))            ) ||
02231         ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT_DIV4)       &&
02232           (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN))          ) ||
02233         ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)    &&
02234           (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
02235        )
02236     {
02237       /* Configuration of common ADC parameters (continuation)                */
02238       /* Software is allowed to change common parameters only when all ADCs   */
02239       /* of the common group are disabled.                                    */
02240       if ((ADC_IS_ENABLE(hadc) == RESET)   &&
02241           (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
02242       {
02243         /* If Channel 17 is selected, enable Temp. sensor measurement path    */
02244         /* Note: Temp. sensor internal channels available only on ADC3        */
02245         if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) &&
02246             (hadc->Instance == ADC3))
02247         {
02248           SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
02249
02250           /* Delay for temperature sensor stabilization time */
02251           while(WaitLoopIndex < ADC_TEMPSENSOR_DELAY_US)
02252           {
02253             WaitLoopIndex++;
02254           }
02255         }
02256         /* If Channel 18 is selected, enable VBAT measurement path            */
02257         /* Note: VBAT internal internal channels available only on ADC3       */
02258         else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT_DIV4) &&
02259                  (hadc->Instance == ADC3))
02260         {
02261           SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
02262         }
02263         /* If Channel 0 is selected, enable VREFINT measurement path          */
02264         /* Note: VREFINT internal channels available only on ADC3             */
02265         else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) &&
02266                  (hadc->Instance == ADC3))
02267         {
02268           SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
02269         }
02270         else
02271         {
02272           /* Discrepancy found out between ADC instance and internal
02273              channel request */
02274           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02275           tmp_hal_status  = HAL_ERROR;
02276         }
02277       }
02278       /* If the requested internal measurement path has already been enabled  */
02279       /* and other ADC of the common group are enabled, internal              */
02280       /* measurement paths cannot be enabled.                                 */
02281       else
02282       {
02283         /* Update ADC state machine to error */
02284         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02285
02286         tmp_hal_status  = HAL_ERROR;
02287       }
02288     }
02289
02290   } /* if (ADC_IS_ENABLE(hadc) == RESET) */
02291
02292   /* Process unlocked */
02293   __HAL_UNLOCK(hadc);
02294
02295   /* Return function status */
02296   return tmp_hal_status ;
02297 }
02298
02299 /**
02300   * @brief  Enable ADC multimode and configure multimode parameters
02301   * @note   Possibility to update parameters on the fly:
02302   *         This function initializes multimode parameters, following
02303   *         calls to this function can be used to reconfigure some parameters
02304   *         of structure "ADC_MultiModeTypeDef" on the fly, without reseting
02305   *         the ADCs.
02306   *         The setting of these parameters is conditioned to ADC state.
02307   *         For parameters constraints, see comments of structure
02308   *         "ADC_MultiModeTypeDef".
02309   * @note   To move back configuration from multimode to single mode, ADC must
02310   *         be reset (using function HAL_ADC_Init() ).
02311   * @param  hadc: Master ADC handle
02312   * @param  multimode : Structure of ADC multimode configuration
02313   * @retval HAL status
02314   */
02315 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
02316 {
02317   HAL_StatusTypeDef  tmp_hal_status  = HAL_OK;
02318   ADC_Common_TypeDef *tmpADC_Common;
02319   ADC_HandleTypeDef  tmphadcSlave;
02320
02321   /* Check the parameters */
02322   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
02323   assert_param(IS_ADC_MODE(multimode->Mode));
02324   if(multimode->Mode != ADC_MODE_INDEPENDENT)
02325   {
02326     assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData));
02327     assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
02328   }
02329
02330   /* Process locked */
02331   __HAL_LOCK(hadc);
02332
02333   ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
02334
02335   if (tmphadcSlave.Instance == NULL)
02336   {
02337     /* Update ADC state machine to error */
02338     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02339
02340     /* Process unlocked */
02341     __HAL_UNLOCK(hadc);
02342
02343     return HAL_ERROR;
02344   }
02345   /* Parameters update conditioned to ADC state:                              */
02346   /* Parameters that can be updated when ADC is disabled or enabled without   */
02347   /* conversion on going on regular group:                                    */
02348   /*  - Multimode DATA Format configuration                                           */
02349   if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
02350       && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) == RESET) )
02351   {
02352
02353     /* Pointer to the common control register */
02354     tmpADC_Common = ADC12_COMMON_REGISTER(hadc);
02355
02356     /* If multimode is selected, configure all multimode paramaters.          */
02357     /* Otherwise, reset multimode parameters (can be used in case of          */
02358     /* transition from multimode to independent mode).                        */
02359     if(multimode->Mode != ADC_MODE_INDEPENDENT)
02360     {
02361       MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData);
02362
02363       /* Parameters that can be updated only when ADC is disabled:                */
02364       /*  - Multimode mode selection                                              */
02365       /*  - Multimode delay                                                       */
02366       /*    Note: Delay range depends on selected resolution:                   */
02367       /*      from 1 to 9 clock cycles for 16 bits                              */
02368       /*      from 1 to 9 clock cycles for 14 bits,                             */
02369       /*      from 1 to 8 clock cycles for 12 bits                              */
02370       /*      from 1 to 6 clock cycles for 10 and 8 bits                        */
02371       /*    If a higher delay is selected, it will be clipped to maximum delay  */
02372       /*    range                                                               */
02373       if ((ADC_IS_ENABLE(hadc) == RESET)                             &&
02374           (ADC_IS_ENABLE(&tmphadcSlave) == RESET)  )
02375       {
02376         MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY,
02377                multimode->Mode | multimode->TwoSamplingDelay );
02378       }
02379     }
02380     else /* ADC_MODE_INDEPENDENT */
02381     {
02382       CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF);
02383
02384       /* Parameters that can be updated only when ADC is disabled:                */
02385       /*  - Multimode mode selection                                              */
02386       /*  - Multimode delay                                                       */
02387       if ((ADC_IS_ENABLE(hadc) == RESET)                             &&
02388           (ADC_IS_ENABLE(&tmphadcSlave) == RESET)  )
02389       {
02390         CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
02391       }
02392     }
02393   }
02394   /* If one of the ADC sharing the same common group is enabled, no update    */
02395   /* could be done on neither of the multimode structure parameters.          */
02396   else
02397   {
02398     /* Update ADC state machine to error */
02399     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02400
02401     tmp_hal_status  = HAL_ERROR;
02402   }
02403
02404
02405   /* Process unlocked */
02406   __HAL_UNLOCK(hadc);
02407
02408   /* Return function status */
02409   return tmp_hal_status ;
02410 }
02411
02412
02413
02414 /**
02415   * @brief  Enable Injected Queue
02416   * @note   This function resets CFGR register JQDIS bit in order to enable the
02417   *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
02418   *         are both equal to 0 to ensure that no regulart nor injected
02419   *         conversion is ongoing.
02420   * @param  hadc: ADC handle
02421   * @retval HAL status
02422   */
02423 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc)
02424 {
02425   /* Parameter can be set only if no conversion is on-going                   */
02426   if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
02427   {
02428     CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
02429
02430     /* Update state, clear previous result related to injected queue overflow */
02431     CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
02432
02433     return HAL_OK;
02434   }
02435   else
02436   {
02437     return HAL_ERROR;
02438   }
02439 }
02440
02441 /**
02442   * @brief  Disable Injected Queue
02443   * @note   This function sets CFGR register JQDIS bit in order to disable the
02444   *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
02445   *         are both equal to 0 to ensure that no regulart nor injected
02446   *         conversion is ongoing.
02447   * @param  hadc: ADC handle
02448   * @retval HAL status
02449   */
02450 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc)
02451 {
02452   /* Parameter can be set only if no conversion is on-going                   */
02453   if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
02454   {
02455     SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
02456     return HAL_OK;
02457   }
02458   else
02459   {
02460     return HAL_ERROR;
02461   }
02462 }
02463
02464
02465 /**
02466   * @brief  Disable ADC voltage regulator.
02467   * @note   Disabling voltage regulator allows to save power. This operation can
02468   *         be carried out only when ADC is disabled.
02469   * @note   To enable again the voltage regulator, the user is expected to
02470   *         resort to HAL_ADC_Init() API.
02471   * @param  hadc: ADC handle
02472   * @retval HAL status
02473   */
02474 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc)
02475 {
02476   /* ADVREGEN can be written only when the ADC is disabled  */
02477   if (ADC_IS_ENABLE(hadc) == RESET)
02478   {
02479     CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
02480     return HAL_OK;
02481   }
02482   else
02483   {
02484     return HAL_ERROR;
02485   }
02486 }
02487
02488 /**
02489   * @brief  Enter ADC deep-power-down mode
02490   * @note   This mode is achieved in setting DEEPPWD bit and allows to save power
02491   *         in reducing leakage currents. It is particularly interesting before
02492   *         entering STOP1 or STOP2 modes.
02493   * @note   Setting DEEPPWD automatically clears ADVREGEN bit and disables the
02494   *         ADC voltage regulator. This means that this API encompasses
02495   *         HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
02496   *         calibration is lost.
02497   * @note   To exit the ADC deep-power-down mode, the user is expected to
02498   *         resort to HAL_ADC_Init() API as well as to relaunch a calibration
02499   *         with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
02500   *         saved calibration factor.
02501   * @param  hadc: ADC handle
02502   * @retval HAL status
02503   */
02504 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc)
02505 {
02506   /* DEEPPWD can be written only when the ADC is disabled  */
02507   if (ADC_IS_ENABLE(hadc) == RESET)
02508   {
02509     SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
02510     return HAL_OK;
02511   }
02512   else
02513   {
02514     return HAL_ERROR;
02515   }
02516 }
02517
02518 /**
02519   * @}
02520   */
02521
02522 /**
02523   * @}
02524   */
02525
02526
02527
02528 #endif /* HAL_ADC_MODULE_ENABLED */
02529 /**
02530   * @}
02531   */
02532
02533 /**
02534   * @}
02535   */
02536
02537 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:37 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_adc_ex.h Source File

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stm32h7xx_hal_adc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_adc_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of ADC HAL extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_ADC_EX_H
00040 #define __STM32H7xx_ADC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup ADCEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  ADC group injected contexts queue configuration
00064   */
00065 typedef struct
00066 {
00067   uint32_t ContextQueue;                 /*!< Injected channel configuration context: build-up over each
00068                                               HAL_ADCEx_InjectedConfigChannel() call to finally initialize
00069                                               JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
00070
00071   uint32_t ChannelCount;                 /*!< Number of channels in the injected sequence */
00072 }ADC_InjectionConfigTypeDef;
00073
00074 /**
00075   * @brief  ADC handle Structure definition
00076   */
00077 typedef struct
00078 {
00079   ADC_TypeDef                   *Instance;              /*!< Register base address */
00080
00081   ADC_InitTypeDef               Init;                   /*!< ADC initialization parameters and regular conversions setting */
00082
00083   DMA_HandleTypeDef             *DMA_Handle;            /*!< Pointer DMA Handler */
00084
00085   HAL_LockTypeDef               Lock;                   /*!< ADC locking object */
00086
00087   __IO uint32_t                 State;                  /*!< ADC communication state (bit-map of ADC states) */
00088
00089   __IO uint32_t                 ErrorCode;              /*!< ADC Error code */
00090
00091   ADC_InjectionConfigTypeDef    InjectionConfig ;       /*!< ADC injected channel configuration build-up structure */
00092 }ADC_HandleTypeDef;
00093
00094 /**
00095   * @brief  ADC Injected Conversion Oversampling structure definition
00096   */
00097 typedef struct
00098 {
00099   uint32_t Ratio;                         /*!< Configures the oversampling ratio.
00100                                                This parameter can be a value between 0 to 1023 */
00101
00102   uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
00103                                                This parameter can be a value of @ref ADCEx_Right_Bit_Shift */
00104 }ADC_InjOversamplingTypeDef;
00105
00106 /**
00107   * @brief  Structure definition of ADC channel for regular group
00108   * @note   The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
00109   *         ADC state can be either:
00110   *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
00111   *          - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
00112   *          - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
00113   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00114   *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter
00115   *        (which fulfills the ADC state condition) on the fly).
00116   */
00117 typedef struct
00118 {
00119   uint32_t Channel;                /*!< Specify the channel to configure into ADC regular group.
00120                                         This parameter can be a value of @ref ADC_channels
00121                                         Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device DataSheet for channels availability. */
00122
00123   uint32_t Rank;                   /*!< Specify the rank in the regular group sequencer.
00124                                         This parameter can be a value of @ref ADC_regular_rank
00125                                         Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
00126                                         the new channel setting (or parameter number of conversions adjusted) */
00127
00128   uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
00129                                         Unit: ADC clock cycles
00130                                         Conversion time is the addition of sampling time and processing time
00131                                         This parameter can be a value of @ref ADC_sampling_times
00132                                         Caution: This parameter applies to a channel that can be used into regular and/or injected group.
00133                                                  It overwrites the last setting.
00134                                         Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
00135                                               sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
00136                                               Refer to device DataSheet for timings values. */
00137
00138   uint32_t SingleDiff;             /*!< Select single-ended or differential input.
00139                                         In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
00140                                                               Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
00141                                         This parameter must be a value of @ref ADCEx_SingleDifferential
00142                                        Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
00143                                                  It overwrites the last setting.
00144                                         Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
00145                                         Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
00146                                         Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
00147                                               If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
00148                                         of another parameter update on the fly) */
00149
00150   uint32_t OffsetNumber;           /*!< Select the offset number
00151                                         This parameter can be a value of @ref ADCEx_OffsetNumber
00152                                         Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
00153
00154   uint32_t Offset;                 /*!< Define the offset to be subtracted from the raw converted data.
00155                                         Offset value must be a positive number.
00156                                         Depending of ADC resolution selected (16, 14, 12, 10 or 8 bits), this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF,
00157                                         0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.
00158                                         Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
00159                                         without continuous mode or external trigger that could launch a conversion). */
00160
00161   FunctionalState OffsetRightShift;   /*!< Define the Right-shift data after Offset correction.
00162                                         This parameter is applied only for 16-bit or 8-bit resolution.
00163                                         This parameter can be set to ENABLE or DISABLE.*/
00164
00165   FunctionalState OffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not.
00166                                              This parameter is applied only for 16-bit or 8-bit resolution.
00167                                              This parameter can be set to ENABLE or DISABLE. */
00168 }ADC_ChannelConfTypeDef;
00169
00170 /**
00171   * @brief  Structure definition of ADC group injected and ADC channel affected to ADC group injected
00172   * @note   Parameters of this structure are shared within 2 scopes:
00173   *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
00174   *          - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
00175   *            AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
00176   * @note   The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
00177   *         ADC state can be either:
00178   *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
00179   *          - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
00180   *          - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
00181   *          - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
00182   *            on ADC groups regular and injected.
00183   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00184   *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
00185   */
00186 typedef struct
00187 {
00188   uint32_t InjectedChannel;               /*!< Specifies the channel to configure into ADC group injected.
00189                                                This parameter can be a value of @ref ADC_channels
00190                                                Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
00191
00192   uint32_t InjectedRank;                  /*!< Specifies the rank in the ADC group injected sequencer.
00193                                                This parameter must be a value of @ref ADCEx_injected_rank.
00194                                                Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
00195                                                the new channel setting (or parameter number of conversions adjusted) */
00196
00197   uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
00198                                                Unit: ADC clock cycles.
00199                                                Conversion time is the addition of sampling time and processing time
00200                                                This parameter can be a value of @ref ADC_sampling_times.
00201                                                Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
00202                                                         It overwrites the last setting.
00203                                                Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
00204                                                      sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
00205                                                      Refer to device datasheet for timings values. */
00206
00207   uint32_t InjectedSingleDiff;            /*!< Selection of single-ended or differential input.
00208                                                In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
00209                                                Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
00210                                                This parameter must be a value of @ref ADCEx_SingleDifferential.
00211                                                Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
00212                                                         It overwrites the last setting.
00213                                                Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
00214                                                Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
00215                                                Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
00216                                                If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
00217                                                of another parameter update on the fly) */
00218
00219   uint32_t InjectedOffsetNumber;          /*!< Selects the offset number.
00220                                                This parameter can be a value of @ref ADCEx_OffsetNumber.
00221                                                Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
00222
00223   uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data.
00224                                                Offset value must be a positive number.
00225                                                Depending of ADC resolution selected (16, 14, 12, 10 or 8bits), this parameter must be a number
00226                                                between Min_Data = 0x0000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.
00227                                                Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
00228                                                without continuous mode or external trigger that could launch a conversion). */
00229   uint32_t InjectedOffsetRightShift;       /*!< Defines the Right-shift data after Offset correction.
00230                                                 This parameter is applied only for 16-bit or 8-bit resolution.
00231                                                 This parameter must be a value of @ref ADCEx_Right_Bit_Shift.*/
00232   FunctionalState InjectedOffsetSignedSaturation;      /*!< Specifies whether the Signed saturation feature is used or not.
00233                                                This parameter is applied only for 16-bit or 8-bit resolution.
00234                                                This parameter can be set to ENABLE or DISABLE. */
00235   uint32_t InjectedLeftBitShift;          /*!< Configures the left shifting applied to the final result with or without oversampling.
00236                                                This parameter can be a value of @ref ADCEx_Left_Bit_Shift */
00237   uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.
00238                                                To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
00239                                                This parameter must be a number between Min_Data = 1 and Max_Data = 4.
00240                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00241                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00242
00243   FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence
00244                                                (main sequence subdivided in successive parts).
00245                                                Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
00246                                                Discontinuous mode can be enabled only if continuous mode is disabled.
00247                                                This parameter can be set to ENABLE or DISABLE.
00248                                                Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
00249                                                Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank).
00250                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00251                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00252
00253   FunctionalState AutoInjectedConv;              /*!< Enables or disables the selected ADC group injected automatic conversion after regular one
00254                                                This parameter can be set to ENABLE or DISABLE.
00255                                                Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
00256                                                Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START)
00257                                                Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
00258                                                      To maintain JAUTO always enabled, DMA must be configured in circular mode.
00259                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00260                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00261
00262   FunctionalState QueueInjectedContext;          /*!< Specifies whether the context queue feature is enabled.
00263                                                This parameter can be set to ENABLE or DISABLE.
00264                                                If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
00265                                                new injected context is set when queue is full, error is triggered by interruption and through function
00266                                                'HAL_ADCEx_InjectedQueueOverflowCallback'.
00267                                                Caution: This feature request that the sequence is fully configured before injected conversion start.
00268                                                         Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.
00269                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00270                                                         configure a channel on injected group can impact the configuration of other channels previously set.
00271                                                Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
00272
00273   uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.
00274                                                If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
00275                                                This parameter can be a value of @ref ADCEx_Injected_External_Trigger_Source.
00276                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00277                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00278
00279   uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.
00280                                                This parameter can be a value of @ref ADC_injected_external_trigger_edge.
00281                                                If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
00282                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00283                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00284
00285   FunctionalState InjecOversamplingMode;                 /*!< Specifies whether the oversampling feature is enabled or disabled.
00286                                                        This parameter can be set to ENABLE or DISABLE.
00287                                                        Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared) */
00288
00289   ADC_InjOversamplingTypeDef  InjecOversampling; /*!< Specifies the Oversampling parameters.
00290                                                       Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
00291                                                       Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
00292 }ADC_InjectionConfTypeDef;
00293
00294
00295
00296 /**
00297   * @brief  Structure definition of ADC MultiMode
00298   * @note   The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs).
00299   *         Both Master and Slave ADCs must be disabled.
00300   */
00301 typedef struct
00302 {
00303   uint32_t Mode;              /*!< Configures the ADC to operate in independent or MultiMode.
00304                                    This parameter can be a value of @ref ADCEx_Common_mode */
00305   uint32_t DualModeData;      /*!< Configures the Dual ADC Mode Data Format:
00306                                    This parameter can be a value of @ref ADCEx_Dual_Mode_Data_Format */
00307   uint32_t TwoSamplingDelay;  /*!< Configures the Delay between 2 sampling phases.
00308                                    This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases
00309                                    Delay range depends on selected resolution:
00310                                     from 1 to 9 clock cycles for 16 bits,
00311                                     from 1 to 9 clock cycles for 14 bits
00312                                     from 1 to 8 clock cycles for 12 bits
00313                                     from 1 to 6 clock cycles for 10 bits
00314                                     from 1 to 6 clock cycles for 8 bits     */
00315 }ADC_MultiModeTypeDef;
00316
00317
00318 /**
00319   * @}
00320   */
00321
00322 /* Exported constants --------------------------------------------------------*/
00323 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
00324   * @{
00325   */
00326
00327 /** @defgroup ADCEx_Injected_External_Trigger_Source ADC Extended External Trigger Source for Injected Group
00328   * @{
00329   */
00330 #define ADC_EXTERNALTRIGINJEC_T1_TRGO       ((uint32_t)0x00000000)                                                                             /*!< Event 0 triggers injected group conversion start  */
00331 #define ADC_EXTERNALTRIGINJEC_T1_CC4        ((uint32_t)ADC_JSQR_JEXTSEL_0)                                                                     /*!< Event 1 triggers injected group conversion start  */
00332 #define ADC_EXTERNALTRIGINJEC_T2_TRGO       ((uint32_t)ADC_JSQR_JEXTSEL_1)                                                                     /*!< Event 2 triggers injected group conversion start  */
00333 #define ADC_EXTERNALTRIGINJEC_T2_CC1        ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))                                              /*!< Event 3 triggers injected group conversion start  */
00334 #define ADC_EXTERNALTRIGINJEC_T3_CC4        ((uint32_t)ADC_JSQR_JEXTSEL_2)                                                                     /*!< Event 4 triggers injected group conversion start  */
00335 #define ADC_EXTERNALTRIGINJEC_T4_TRGO       ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))                                              /*!< Event 5 triggers injected group conversion start  */
00336 #define ADC_EXTERNALTRIGINJEC_EXT_IT15      ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))                                              /*!< Event 6 triggers injected group conversion start  */
00337 #define ADC_EXTERNALTRIGINJEC_T8_CC4        ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))                         /*!< Event 7 triggers injected group conversion start  */
00338 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2      ((uint32_t)ADC_JSQR_JEXTSEL_3)                                                                     /*!< Event 8 triggers injected group conversion start  */
00339 #define ADC_EXTERNALTRIGINJEC_T8_TRGO       ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))                                              /*!< Event 9 triggers injected group conversion start  */
00340 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2      ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))                                              /*!< Event 10 triggers injected group conversion start  */
00341 #define ADC_EXTERNALTRIGINJEC_T3_CC3        ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))                         /*!< Event 11 triggers injected group conversion start  */
00342 #define ADC_EXTERNALTRIGINJEC_T3_TRGO       ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))                                              /*!< Event 12 triggers injected group conversion start  */
00343 #define ADC_EXTERNALTRIGINJEC_T3_CC1        ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))                         /*!< Event 13 triggers injected group conversion start  */
00344 #define ADC_EXTERNALTRIGINJEC_T6_TRGO       ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))                         /*!< Event 14 triggers injected group conversion start  */
00345 #define ADC_EXTERNALTRIGINJEC_T15_TRGO      ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))    /*!< Event 15 triggers injected group conversion start  */
00346 #define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2   ((uint32_t)ADC_JSQR_JEXTSEL_4)                                                                     /*!< Event 16 triggers injected group conversion start  */
00347 #define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4   ((uint32_t)(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0))                                              /*!< Event 17 triggers injected group conversion start  */
00348 #define ADC_EXTERNALTRIGINJEC_LPTIM1_OUT    ((uint32_t)(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1))                                              /*!< Event 18 triggers injected group conversion start  */
00349 #define ADC_EXTERNALTRIGINJEC_LPTIM2_OUT    ((uint32_t)(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))                         /*!< Event 19 triggers injected group conversion start  */
00350 #define ADC_EXTERNALTRIGINJEC_LPTIM3_OUT    ((uint32_t)(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2))                                              /*!< Event 20 triggers injected group conversion start  */
00351
00352 #define ADC_INJECTED_SOFTWARE_START      ((uint32_t)0x00000001)                                                                                /*!< Software triggers injected group conversion start */
00353 /**
00354   * @}
00355   */
00356
00357 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
00358   * @{
00359   */
00360 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE           ((uint32_t)0x00000000)          /*!< Injected conversions hardware trigger detection disabled                             */
00361 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING         ((uint32_t)ADC_JSQR_JEXTEN_0)   /*!< Injected conversions hardware trigger detection on the rising edge                   */
00362 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING        ((uint32_t)ADC_JSQR_JEXTEN_1)   /*!< Injected conversions hardware trigger detection on the falling edge                  */
00363 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING  ((uint32_t)ADC_JSQR_JEXTEN)     /*!< Injected conversions hardware trigger detection on both the rising and falling edges */
00364 /**
00365   * @}
00366   */
00367
00368 /** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode
00369   * @{
00370   */
00371 #define ADC_SINGLE_ENDED                ((uint32_t)0x00000000)       /*!< ADC channel set in single-ended input mode */
00372 #define ADC_DIFFERENTIAL_ENDED          ((uint32_t)ADC_CR_ADCALDIF)  /*!< ADC channel set in differential mode       */
00373 /**
00374   * @}
00375   */
00376
00377 /** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number
00378   * @{
00379   */
00380 #define ADC_OFFSET_NONE               ((uint32_t)0x00)     /*!< No offset correction                           */
00381 #define ADC_OFFSET_1                  ((uint32_t)0x01)     /*!< Offset correction to apply to a first channel  */
00382 #define ADC_OFFSET_2                  ((uint32_t)0x02)     /*!< Offset correction to apply to a second channel */
00383 #define ADC_OFFSET_3                  ((uint32_t)0x03)     /*!< Offset correction to apply to a third channel  */
00384 #define ADC_OFFSET_4                  ((uint32_t)0x04)     /*!< Offset correction to apply to a fourth channel */
00385 /**
00386   * @}
00387   */
00388
00389 /** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
00390   * @{
00391   */
00392 #define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001)      /*!< ADC injected conversion rank 1 */
00393 #define ADC_INJECTED_RANK_2    ((uint32_t)0x00000002)      /*!< ADC injected conversion rank 2 */
00394 #define ADC_INJECTED_RANK_3    ((uint32_t)0x00000003)      /*!< ADC injected conversion rank 3 */
00395 #define ADC_INJECTED_RANK_4    ((uint32_t)0x00000004)      /*!< ADC injected conversion rank 4 */
00396 /**
00397   * @}
00398   */
00399
00400 /** @defgroup ADCEx_Common_mode ADC Extended multimode dual mode
00401   * @{
00402   */
00403 #define ADC_MODE_INDEPENDENT                  ((uint32_t)(0x00000000))                                       /*!< Independent ADC conversions mode                           */
00404 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT    ((uint32_t)(ADC_CCR_DUAL_0))                                   /*!< Combined regular simultaneous + injected simultaneous mode */
00405 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG      ((uint32_t)(ADC_CCR_DUAL_1))                                   /*!< Combined regular simultaneous + alternate trigger mode     */
00406 #define ADC_DUALMODE_REGINTERL_INJECSIMULT    ((uint32_t)(ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0))                  /*!< Combined Interleaved mode + injected simultaneous mode     */
00407 #define ADC_DUALMODE_INJECSIMULT              ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0))                  /*!< Injected simultaneous mode only                            */
00408 #define ADC_DUALMODE_REGSIMULT                ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1))                  /*!< Regular simultaneous mode only                             */
00409 #define ADC_DUALMODE_INTERL                   ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)) /*!< Interleaved mode only                                      */
00410 #define ADC_DUALMODE_ALTERTRIG                ((uint32_t)(ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0))                  /*!< Alternate trigger mode only                                */
00411 /**
00412   * @}
00413   */
00414
00415
00416 /** @defgroup ADCEx_Dual_Mode_Data_Format ADC Extended Dual Mode Data Formatting
00417   * @{
00418   */
00419 #define ADC_DUALMODEDATAFORMAT_DISABLED      ((uint32_t)0x00000000)                        /*!< Dual ADC mode without data packing: ADCx_CDR and ADCx_CDR2 registers not used */
00420 #define ADC_DUALMODEDATAFORMAT_32_10_BITS    ((uint32_t)ADC_CCR_DAMDF_1)                    /*!< Data formatting mode for 32 down to 10-bit resolution */
00421 #define ADC_DUALMODEDATAFORMAT_8_BITS        ((uint32_t)(ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1)) /*!< Data formatting mode for 8-bit resolution */
00422 /**
00423   * @}
00424   */
00425
00426 /** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended delay between 2 sampling phases
00427   * @{
00428   */
00429 #define ADC_TWOSAMPLINGDELAY_1CYCLE     ((uint32_t)(0x00000000))                                          /*!< 1 ADC clock cycle delay                                          */
00430 #define ADC_TWOSAMPLINGDELAY_2CYCLES    ((uint32_t)(ADC_CCR_DELAY_0))                                     /*!< 2 ADC clock cycles delay                                         */
00431 #define ADC_TWOSAMPLINGDELAY_3CYCLES    ((uint32_t)(ADC_CCR_DELAY_1))                                     /*!< 3 ADC clock cycles delay                                         */
00432 #define ADC_TWOSAMPLINGDELAY_4CYCLES    ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))                   /*!< 4 ADC clock cycles delay (lower for less then 10-bit resolution) */
00433 #define ADC_TWOSAMPLINGDELAY_5CYCLES    ((uint32_t)(ADC_CCR_DELAY_2))                                     /*!< 5 ADC clock cycles delay (lower for less then 12-bit resolution) */
00434 #define ADC_TWOSAMPLINGDELAY_6CYCLES    ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))                   /*!< 6 ADC clock cycles delay (lower for less then 14-bit resolution) */
00435 #define ADC_TWOSAMPLINGDELAY_7CYCLES    ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))                   /*!< 7 ADC clock cycles delay (lower for less then 16-bit resolution) */
00436 #define ADC_TWOSAMPLINGDELAY_8CYCLES    ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 8 ADC clock cycles delay (lower for less then 16-bit resolution) */
00437 #define ADC_TWOSAMPLINGDELAY_9CYCLES    ((uint32_t)(ADC_CCR_DELAY_3))                                     /*!< 9 ADC clock cycles delay (lower for less then 16-bit resolution) */
00438 /**
00439   * @}
00440   */
00441
00442 /** @defgroup ADCEx_analog_watchdog_number ADC Extended Analog Watchdog Selection
00443   * @{
00444   */
00445 #define ADC_ANALOGWATCHDOG_1                    ((uint32_t)0x00000001)   /*!< Analog watchdog 1 selection */
00446 #define ADC_ANALOGWATCHDOG_2                    ((uint32_t)0x00000002)   /*!< Analog watchdog 2 selection */
00447 #define ADC_ANALOGWATCHDOG_3                    ((uint32_t)0x00000003)   /*!< Analog watchdog 3 selection */
00448 /**
00449   * @}
00450   */
00451
00452 /** @defgroup ADCEx_analog_watchdog_mode ADC Extended Analog Watchdog Mode
00453   * @{
00454   */
00455 #define ADC_ANALOGWATCHDOG_NONE                 ((uint32_t) 0x00000000)                                             /*!< No analog watchdog selected                                             */
00456 #define ADC_ANALOGWATCHDOG_SINGLE_REG           ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN))                    /*!< Analog watchdog applied to a regular group single channel               */
00457 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC         ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN))                   /*!< Analog watchdog applied to an injected group single channel             */
00458 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC      ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to a regular and injected groups single channel */
00459 #define ADC_ANALOGWATCHDOG_ALL_REG              ((uint32_t) ADC_CFGR_AWD1EN)                                        /*!< Analog watchdog applied to regular group all channels                   */
00460 #define ADC_ANALOGWATCHDOG_ALL_INJEC            ((uint32_t) ADC_CFGR_JAWD1EN)                                       /*!< Analog watchdog applied to injected group all channels                  */
00461 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC         ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))                    /*!< Analog watchdog applied to regular and injected groups all channels     */
00462 /**
00463   * @}
00464   */
00465
00466 /** @defgroup ADCEx_conversion_group ADC Extended Conversion Group
00467   * @{
00468   */
00469 #define ADC_REGULAR_GROUP             ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))                                 /*!< ADC regular group selection               */
00470 #define ADC_INJECTED_GROUP            ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS))                               /*!< ADC injected group selection              */
00471 #define ADC_REGULAR_INJECTED_GROUP    ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS)) /*!< ADC regular and injected groups selection */
00472 /**
00473   * @}
00474   */
00475
00476 /** @defgroup ADCEx_Event_type ADC Extended Event Type
00477   * @{
00478   */
00479 #define ADC_EOSMP_EVENT          ((uint32_t)ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
00480 #define ADC_AWD1_EVENT           ((uint32_t)ADC_FLAG_AWD1)  /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
00481 #define ADC_AWD2_EVENT           ((uint32_t)ADC_FLAG_AWD2)  /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
00482 #define ADC_AWD3_EVENT           ((uint32_t)ADC_FLAG_AWD3)  /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
00483 #define ADC_OVR_EVENT            ((uint32_t)ADC_FLAG_OVR)   /*!< ADC overrun event */
00484 #define ADC_JQOVF_EVENT          ((uint32_t)ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
00485 /**
00486   * @}
00487   */
00488 #define ADC_AWD_EVENT            ADC_AWD1_EVENT      /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
00489
00490 /** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition
00491   * @{
00492   */
00493 #define ADC_IT_RDY           ADC_IER_RDY        /*!< ADC Ready (ADRDY) interrupt source */
00494 #define ADC_IT_EOSMP         ADC_IER_EOSMP      /*!< ADC End of Sampling interrupt source */
00495 #define ADC_IT_EOC           ADC_IER_EOC        /*!< ADC End of Regular Conversion interrupt source */
00496 #define ADC_IT_EOS           ADC_IER_EOS        /*!< ADC End of Regular sequence of Conversions interrupt source */
00497 #define ADC_IT_OVR           ADC_IER_OVR        /*!< ADC overrun interrupt source */
00498 #define ADC_IT_JEOC          ADC_IER_JEOC       /*!< ADC End of Injected Conversion interrupt source */
00499 #define ADC_IT_JEOS          ADC_IER_JEOS       /*!< ADC End of Injected sequence of Conversions interrupt source */
00500 #define ADC_IT_AWD1          ADC_IER_AWD1       /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
00501 #define ADC_IT_AWD2          ADC_IER_AWD2       /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
00502 #define ADC_IT_AWD3          ADC_IER_AWD3       /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
00503 #define ADC_IT_JQOVF         ADC_IER_JQOVF      /*!< ADC Injected Context Queue Overflow interrupt source */
00504
00505 #define ADC_IT_AWD           ADC_IT_AWD1        /*!< ADC Analog watchdog 1 interrupt source: Naming for compatibility with other STM32 devices having only one analog watchdog */
00506 /**
00507   * @}
00508   */
00509
00510 /** @defgroup ADCEx_flags_definition ADC Extended Flags Definition
00511   * @{
00512   */
00513 #define ADC_FLAG_RDY           ADC_ISR_ADRD     /*!< ADC Ready (ADRDY) flag */
00514 #define ADC_FLAG_EOSMP         ADC_ISR_EOSMP    /*!< ADC End of Sampling flag */
00515 #define ADC_FLAG_EOC           ADC_ISR_EOC      /*!< ADC End of Regular Conversion flag */
00516 #define ADC_FLAG_EOS           ADC_ISR_EOS      /*!< ADC End of Regular sequence of Conversions flag */
00517 #define ADC_FLAG_OVR           ADC_ISR_OVR      /*!< ADC overrun flag */
00518 #define ADC_FLAG_JEOC          ADC_ISR_JEOC     /*!< ADC End of Injected Conversion flag */
00519 #define ADC_FLAG_JEOS          ADC_ISR_JEOS     /*!< ADC End of Injected sequence of Conversions flag */
00520 #define ADC_FLAG_AWD1          ADC_ISR_AWD1     /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
00521 #define ADC_FLAG_AWD2          ADC_ISR_AWD2     /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
00522 #define ADC_FLAG_AWD3          ADC_ISR_AWD3     /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
00523 #define ADC_FLAG_JQOVF         ADC_ISR_JQOVF    /*!< ADC Injected Context Queue Overflow flag */
00524
00525 #define ADC_FLAG_AWD           ADC_FLAG_AWD1    /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog */
00526
00527 #define ADC_FLAG_ALL    (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS |  \
00528                          ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \
00529                          ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF)  /*!< ADC all flags */
00530
00531 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx, JQOVF */
00532 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS  | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \
00533                                ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \
00534                                ADC_FLAG_JQOVF) /*!< ADC post-conversion all flags */
00535 /**
00536   * @}
00537   */
00538
00539
00540 /** @defgroup ADCEx_Right_Bit_Shift   ADC Extended Oversampling Right Shift
00541   * @{
00542   */
00543 #define ADC_RIGHTBITSHIFT_NONE  ((uint32_t)0x00000000)                                               /*!<  ADC No bit shift for oversampling */
00544 #define ADC_RIGHTBITSHIFT_1     ((uint32_t)ADC_CFGR2_OVSS_0)                                         /*!<  ADC 1 bit shift for oversampling  */
00545 #define ADC_RIGHTBITSHIFT_2     ((uint32_t)ADC_CFGR2_OVSS_1)                                         /*!<  ADC 2 bits shift for oversampling */
00546 #define ADC_RIGHTBITSHIFT_3     ((uint32_t)(ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0))                    /*!<  ADC 3 bits shift for oversampling */
00547 #define ADC_RIGHTBITSHIFT_4     ((uint32_t)ADC_CFGR2_OVSS_2)                                         /*!<  ADC 4 bits shift for oversampling */
00548 #define ADC_RIGHTBITSHIFT_5     ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0))                    /*!<  ADC 5 bits shift for oversampling */
00549 #define ADC_RIGHTBITSHIFT_6     ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1))                    /*!<  ADC 6 bits shift for oversampling */
00550 #define ADC_RIGHTBITSHIFT_7     ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)) /*!<  ADC 7 bits shift for oversampling */
00551 #define ADC_RIGHTBITSHIFT_8     ((uint32_t)ADC_CFGR2_OVSS_3)                                         /*!<  ADC 8 bits shift for oversampling */
00552 #define ADC_RIGHTBITSHIFT_9     ((uint32_t)(ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0))                    /*!<  ADC 9 bits shift for oversampling */
00553 #define ADC_RIGHTBITSHIFT_10    ((uint32_t)(ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1))                    /*!<  ADC 10 bits shift for oversampling */
00554 #define ADC_RIGHTBITSHIFT_11    ((uint32_t)(ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)) /*!<  ADC 11 bits shift for oversampling */
00555 /**
00556   * @}
00557   */
00558
00559 /** @defgroup ADCEx_Left_Bit_Shift   ADC Extended Oversampling left Shift
00560   * @{
00561   */
00562 #define ADC_LEFTBITSHIFT_NONE  ((uint32_t)0x00000000)                                                                           /*!<  ADC No bit shift */
00563 #define ADC_LEFTBITSHIFT_1     ((uint32_t)ADC_CFGR2_LSHIFT_0)                                                                   /*!<  ADC 1 bit shift  */
00564 #define ADC_LEFTBITSHIFT_2     ((uint32_t)ADC_CFGR2_LSHIFT_1)                                                                   /*!<  ADC 2 bits shift */
00565 #define ADC_LEFTBITSHIFT_3     ((uint32_t)(ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0))                                            /*!<  ADC 3 bits shift */
00566 #define ADC_LEFTBITSHIFT_4     ((uint32_t)ADC_CFGR2_LSHIFT_2)                                                                   /*!<  ADC 4 bits shift */
00567 #define ADC_LEFTBITSHIFT_5     ((uint32_t)(ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0))                                            /*!<  ADC 5 bits shift */
00568 #define ADC_LEFTBITSHIFT_6     ((uint32_t)(ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1))                                            /*!<  ADC 6 bits shift */
00569 #define ADC_LEFTBITSHIFT_7     ((uint32_t)(ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0))                       /*!<  ADC 7 bits shift */
00570 #define ADC_LEFTBITSHIFT_8     ((uint32_t)ADC_CFGR2_LSHIFT_3)                                                                   /*!<  ADC 8 bits shift */
00571 #define ADC_LEFTBITSHIFT_9     ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0))                                            /*!<  ADC 9 bits shift */
00572 #define ADC_LEFTBITSHIFT_10    ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1))                                            /*!<  ADC 10 bits shift */
00573 #define ADC_LEFTBITSHIFT_11    ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0))                       /*!<  ADC 11 bits shift */
00574 #define ADC_LEFTBITSHIFT_12    ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2))                                            /*!<  ADC 12 bits shift */
00575 #define ADC_LEFTBITSHIFT_13    ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0))                       /*!<  ADC 13 bits shift */
00576 #define ADC_LEFTBITSHIFT_14    ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1))                       /*!<  ADC 14 bits shift */
00577 #define ADC_LEFTBITSHIFT_15    ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0))  /*!<  ADC 15 bits shift */
00578 /**
00579   * @}
00580   */
00581
00582 /** @defgroup ADCEx_Triggered_Oversampling_Mode   ADC Extended Triggered Regular Oversampling
00583   * @{
00584   */
00585 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER      ((uint32_t)0x00000000)      /*!<  A single trigger for all channel oversampled conversions */
00586 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER       ((uint32_t)ADC_CFGR2_TROVS) /*!<  A trigger for each oversampled conversion                */
00587 /**
00588   * @}
00589   */
00590
00591 /** @defgroup ADCEx_Regular_Oversampling_Mode   ADC Extended Regular Oversampling Continued or Resumed Mode
00592   * @{
00593   */
00594 #define ADC_REGOVERSAMPLING_CONTINUED_MODE    ((uint32_t)0x00000000)      /*!<  Oversampling buffer maintained during injection sequence */
00595 #define ADC_REGOVERSAMPLING_RESUMED_MODE      ((uint32_t)ADC_CFGR2_ROVSM) /*!<  Oversampling buffer zeroed during injection sequence     */
00596 /**
00597   * @}
00598   */
00599
00600 /** @defgroup ADC_sampling_times ADC Sampling Times
00601   * @{
00602   */
00603 #define ADC_SAMPLETIME_1CYCLE_5       ((uint32_t)0x00000000)                              /*!< Sampling time 1.5 ADC clock cycle    */
00604 #define ADC_SAMPLETIME_2CYCLES_5      ((uint32_t)ADC_SMPR2_SMP10_0)                       /*!< Sampling time 2.5 ADC clock cycles   */
00605 #define ADC_SAMPLETIME_8CYCLES_5      ((uint32_t)ADC_SMPR2_SMP10_1)                       /*!< Sampling time 8.5 ADC clock cycles  */
00606 #define ADC_SAMPLETIME_16CYCLES_5     ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 16.5 ADC clock cycles  */
00607 #define ADC_SAMPLETIME_32CYCLES_5     ((uint32_t)ADC_SMPR2_SMP10_2)                       /*!< Sampling time 32.5 ADC clock cycles  */
00608 #define ADC_SAMPLETIME_64CYCLES_5     ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 64.5 ADC clock cycles  */
00609 #define ADC_SAMPLETIME_387CYCLES_5    ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1)) /*!< Sampling time 387.5 ADC clock cycles */
00610 #define ADC_SAMPLETIME_810CYCLES_5    ((uint32_t)ADC_SMPR2_SMP10)                         /*!< Sampling time 810.5 ADC clock cycles */
00611 /**
00612   * @}
00613   */
00614
00615 /** @defgroup ADCEx_Calibration_Mode   ADC Extended Calibration mode offset mode or linear mode
00616   * @{
00617   */
00618 #define ADC_CALIB_OFFSET                 ((uint32_t)0x00000000)
00619 #define ADC_CALIB_OFFSET_LINEARITY         (ADC_CR_ADCALLIN)
00620 /**
00621   * @}
00622   */
00623
00624 /**
00625   * @}
00626   */
00627
00628 /* Exported macros -----------------------------------------------------------*/
00629
00630 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
00631   * @{
00632   */
00633
00634 /**
00635   * @brief Verify the length of scheduled injected conversions group.
00636   * @param LENGTH : number of programmed conversions.
00637   * @retval SET (LENGTH is within the maximum number of possible programmable injected conversions) or RESET (LENGTH is null or too large)
00638   */
00639 #define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
00640
00641 /**
00642   * @brief Calibration factor length verification (7 bits maximum)
00643   * @param _Calibration_Factor_: Calibration factor value
00644   * @retval None
00645   */
00646 #define IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= ((uint32_t)0x7F))
00647
00648 /**
00649   * @brief Verify the ADC channel setting.
00650   * @param __CHANNEL__: programmed ADC channel.
00651   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
00652   */
00653 #define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0)       || \
00654                                  ((__CHANNEL__) == ADC_CHANNEL_1)           || \
00655                                  ((__CHANNEL__) == ADC_CHANNEL_2)           || \
00656                                  ((__CHANNEL__) == ADC_CHANNEL_3)           || \
00657                                  ((__CHANNEL__) == ADC_CHANNEL_4)           || \
00658                                  ((__CHANNEL__) == ADC_CHANNEL_5)           || \
00659                                  ((__CHANNEL__) == ADC_CHANNEL_6)           || \
00660                                  ((__CHANNEL__) == ADC_CHANNEL_7)           || \
00661                                  ((__CHANNEL__) == ADC_CHANNEL_8)           || \
00662                                  ((__CHANNEL__) == ADC_CHANNEL_9)           || \
00663                                  ((__CHANNEL__) == ADC_CHANNEL_10)          || \
00664                                  ((__CHANNEL__) == ADC_CHANNEL_11)          || \
00665                                  ((__CHANNEL__) == ADC_CHANNEL_12)          || \
00666                                  ((__CHANNEL__) == ADC_CHANNEL_13)          || \
00667                                  ((__CHANNEL__) == ADC_CHANNEL_14)          || \
00668                                  ((__CHANNEL__) == ADC_CHANNEL_15)          || \
00669                                  ((__CHANNEL__) == ADC_CHANNEL_16)          || \
00670                                  ((__CHANNEL__) == ADC_CHANNEL_17)          || \
00671                                  ((__CHANNEL__) == ADC_CHANNEL_18)          || \
00672                                  ((__CHANNEL__) == ADC_CHANNEL_19)          || \
00673                                  ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR)  || \
00674                                  ((__CHANNEL__) == ADC_CHANNEL_VBAT_DIV4)   || \
00675                                  ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2)|| \
00676                                  ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2)|| \
00677                                  ((__CHANNEL__) == ADC_CHANNEL_VREFINT)       )
00678
00679 /**
00680   * @brief Verify the ADC channel setting in differential mode for ADC1.
00681   * @param __CHANNEL__: programmed ADC channel.
00682   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
00683   */
00684 #define IS_ADC1_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1)|| \
00685                                       ((__CHANNEL__) == ADC_CHANNEL_2)      ||\
00686                                       ((__CHANNEL__) == ADC_CHANNEL_3)      ||\
00687                                       ((__CHANNEL__) == ADC_CHANNEL_4)      ||\
00688                                       ((__CHANNEL__) == ADC_CHANNEL_5)      ||\
00689                                       ((__CHANNEL__) == ADC_CHANNEL_10)     ||\
00690                                       ((__CHANNEL__) == ADC_CHANNEL_11)     ||\
00691                                       ((__CHANNEL__) == ADC_CHANNEL_12)     ||\
00692                                       ((__CHANNEL__) == ADC_CHANNEL_16)     ||\
00693                                       ((__CHANNEL__) == ADC_CHANNEL_18)      )
00694
00695 /**
00696   * @brief Verify the ADC channel setting in differential mode for ADC2.
00697   * @param __CHANNEL__: programmed ADC channel.
00698   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
00699   */
00700 #define IS_ADC2_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1)|| \
00701                                       ((__CHANNEL__) == ADC_CHANNEL_2)      || \
00702                                       ((__CHANNEL__) == ADC_CHANNEL_3)      || \
00703                                       ((__CHANNEL__) == ADC_CHANNEL_4)      || \
00704                                       ((__CHANNEL__) == ADC_CHANNEL_5)      || \
00705                                       ((__CHANNEL__) == ADC_CHANNEL_10)     || \
00706                                       ((__CHANNEL__) == ADC_CHANNEL_11)     || \
00707                                       ((__CHANNEL__) == ADC_CHANNEL_12)     || \
00708                                       ((__CHANNEL__) == ADC_CHANNEL_18)      )
00709
00710 /**
00711   * @brief Verify the ADC channel setting in differential mode for ADC3.
00712   * @param __CHANNEL__: programmed ADC channel.
00713   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
00714   */
00715 #define IS_ADC3_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \
00716                                       ((__CHANNEL__) == ADC_CHANNEL_2)      || \
00717                                       ((__CHANNEL__) == ADC_CHANNEL_3)      || \
00718                                       ((__CHANNEL__) == ADC_CHANNEL_4)      || \
00719                                       ((__CHANNEL__) == ADC_CHANNEL_5)      || \
00720                                       ((__CHANNEL__) == ADC_CHANNEL_10)     || \
00721                                       ((__CHANNEL__) == ADC_CHANNEL_11)     || \
00722                                       ((__CHANNEL__) == ADC_CHANNEL_13)     || \
00723                                       ((__CHANNEL__) == ADC_CHANNEL_14)     || \
00724                                       ((__CHANNEL__) == ADC_CHANNEL_15)       )
00725
00726 /**
00727   * @brief Test if conversion trigger of injected group is software start
00728   *        or external trigger.
00729   * @param __HANDLE__: ADC handle
00730   * @retval SET (software start) or RESET (external trigger)
00731   */
00732 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                       \
00733        (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
00734
00735 /**
00736   * @brief Check if no conversion on going on regular or injected groups
00737   * @param __HANDLE__: ADC handle
00738   * @retval SET (conversion is on going) or RESET (no conversion is on going)
00739   */
00740 #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__)                    \
00741        (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET  \
00742         ) ? RESET : SET)
00743
00744 /**
00745   * @brief Check if no conversion on going on injected group
00746   * @param __HANDLE__: ADC handle
00747   * @retval SET (conversion is on going) or RESET (no conversion is on going)
00748   */
00749 #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__)                   \
00750        (( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET            \
00751         ) ? RESET : SET)
00752
00753 /**
00754   * @brief Check whether or not ADC is independent
00755   * @param __HANDLE__: ADC handle
00756   * @retval SET (ADC is independent) or RESET (ADC is not)
00757   */
00758 #define ADC_IS_INDEPENDENT(__HANDLE__)    \
00759   ( ( ( ((__HANDLE__)->Instance) == ADC3) \
00760     )?                                    \
00761      SET                                  \
00762      :                                    \
00763      RESET                                \
00764   )
00765
00766 /**
00767   * @brief Set the ADC's sample time for Channels numbers between 0 and 9.
00768   * @param __SAMPLETIME__: Sample time parameter.
00769   * @param __CHANNELNB__: Channel number.
00770   * @retval None
00771   */
00772 #define ADC_SMPR1(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << (POSITION_VAL(ADC_SMPR1_SMP1) * (__CHANNELNB__)))
00773
00774 /**
00775   * @brief Set the ADC's sample time for Channels numbers between 10 and 18.
00776   * @param __SAMPLETIME__: Sample time parameter.
00777   * @param __CHANNELNB__: Channel number.
00778   * @retval None
00779   */
00780 #define ADC_SMPR2(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << ((POSITION_VAL(ADC_SMPR2_SMP11) * ((__CHANNELNB__) - 10))))
00781
00782 /**
00783   * @brief Set the selected regular Channel rank for rank between 1 and 4.
00784   * @param __CHANNELNB__: Channel number.
00785   * @param __RANKNB__: Rank number.
00786   * @retval None
00787   */
00788 #define ADC_SQR1_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR1_SQ1) * (__RANKNB__)))
00789
00790 /**
00791   * @brief Set the selected regular Channel rank for rank between 5 and 9.
00792   * @param __CHANNELNB__: Channel number.
00793   * @param __RANKNB__: Rank number.
00794   * @retval None
00795   */
00796 #define ADC_SQR2_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR2_SQ6) * ((__RANKNB__) - 5)))
00797
00798 /**
00799   * @brief Set the selected regular Channel rank for rank between 10 and 14.
00800   * @param __CHANNELNB__: Channel number.
00801   * @param __RANKNB__: Rank number.
00802   * @retval None
00803   */
00804 #define ADC_SQR3_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR3_SQ11) * ((__RANKNB__) - 10)))
00805
00806 /**
00807   * @brief Set the selected regular Channel rank for rank between 15 and 16.
00808   * @param __CHANNELNB__: Channel number.
00809   * @param __RANKNB__: Rank number.
00810   * @retval None
00811   */
00812 #define ADC_SQR4_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR4_SQ16) * ((__RANKNB__) - 15)))
00813
00814 /**
00815   * @brief Set the selected injected Channel rank.
00816   * @param __CHANNELNB__: Channel number.
00817   * @param __RANKNB__: Rank number.
00818   * @retval None
00819   */
00820 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << ((POSITION_VAL(ADC_JSQR_JSQ1)-3) * (__RANKNB__) +3))
00821
00822 /**
00823   * @brief Set the Analog Watchdog 1 channel.
00824   * @param __CHANNEL__: channel to be monitored by Analog Watchdog 1.
00825   * @retval None
00826   */
00827 #define ADC_CFGR_SET_AWD1CH(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_CFGR_AWD1CH))
00828
00829 /**
00830   * @brief Configure the channel number into Analog Watchdog 2 or 3.
00831   * @param __CHANNEL__: ADC Channel
00832   * @retval None
00833   */
00834 #define ADC_CFGR_SET_AWD23CR(__CHANNEL__) (1U << (__CHANNEL__))
00835
00836 /**
00837   * @brief Enable ADC injected context queue
00838   * @param __INJECT_CONTEXT_QUEUE_MODE__: Injected context queue mode.
00839   * @retval None
00840   */
00841 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((uint32_t)(__INJECT_CONTEXT_QUEUE_MODE__) << POSITION_VAL(ADC_CFGR_JQM))
00842
00843 /**
00844   * @brief Enable ADC discontinuous conversion mode for injected group
00845   * @param __INJECT_DISCONTINUOUS_MODE__: Injected discontinuous mode.
00846   * @retval None
00847   */
00848 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) <<  POSITION_VAL(ADC_CFGR_JDISCEN))
00849
00850 /**
00851   * @brief Enable ADC discontinuous conversion mode for regular group
00852   * @param __REG_DISCONTINUOUS_MODE__: Regular discontinuous mode.
00853   * @retval None
00854   */
00855 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_DISCEN))
00856
00857 /**
00858   * @brief Configures the number of discontinuous conversions for regular group.
00859   * @param __NBR_DISCONTINUOUS_CONV__: Number of discontinuous conversions.
00860   * @retval None
00861   */
00862 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << POSITION_VAL(ADC_CFGR_DISCNUM))
00863
00864 /**
00865   * @brief Enable the ADC auto delay mode.
00866   * @param __AUTOWAIT__: Auto delay bit enable or disable.
00867   * @retval None
00868   */
00869 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << POSITION_VAL(ADC_CFGR_AUTDLY))
00870
00871 /**
00872   * @brief Enable ADC continuous conversion mode.
00873   * @param __CONTINUOUS_MODE__: Continuous mode.
00874   * @retval None
00875   */
00876 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_CONT))
00877
00878 /**
00879   * @brief Enable the ADC DMA continuous request.
00880   * @param __DMACONTREQ_MODE__: DMA continuous request mode.
00881   * @retval None
00882   */
00883 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__))
00884
00885 /**
00886   * @brief Configure the channel number into offset OFRx register
00887   * @param __CHANNEL__: ADC Channel
00888   * @retval None
00889   */
00890 #define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_OFR1_OFFSET1_CH))
00891
00892 /**
00893   * @brief Configure the channel number into differential mode selection register
00894   * @param __CHANNEL__: ADC Channel
00895   * @retval None
00896   */
00897 #define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1U << (__CHANNEL__))
00898
00899 /**
00900   * @brief Calibration factor in differential mode to be set into calibration register
00901   * @param __CALIBRATION_FACTOR__: Calibration factor value
00902   * @retval None
00903   */
00904 #define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D >> POSITION_VAL(ADC_CALFACT_CALFACT_D)) ) << POSITION_VAL(ADC_CALFACT_CALFACT_D))
00905
00906 /**
00907   * @brief Calibration factor in differential mode to be retrieved from calibration register
00908   * @param __CALIBRATION_FACTOR__: Calibration factor value
00909   * @retval None
00910   */
00911 #define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> POSITION_VAL(ADC_CALFACT_CALFACT_D))
00912
00913 /**
00914   * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
00915   * @param __THRESHOLD__: Threshold value
00916   * @retval None
00917   */
00918 #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16)
00919
00920 /**
00921   * @brief Enable the ADC DMA continuous request for ADC multimode.
00922   * @param __DMACONTREQ_MODE__: DMA continuous request mode.
00923   * @retval None
00924   */
00925 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CCR_DMACFG))
00926
00927 /**
00928   * @brief Enable the ADC peripheral
00929   * @param __HANDLE__: ADC handle
00930   * @retval None
00931   */
00932 #define ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
00933
00934 /**
00935   * @brief Verification of hardware constraints before ADC can be enabled
00936   * @param __HANDLE__: ADC handle
00937   * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
00938   */
00939 #define ADC_ENABLING_CONDITIONS(__HANDLE__)                             \
00940        (( ( ((__HANDLE__)->Instance->CR) &                                    \
00941             (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART |  \
00942              ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN                    ) \
00943            ) == RESET                                                         \
00944         ) ? SET : RESET)
00945
00946 /**
00947   * @brief Disable the ADC peripheral
00948   * @param __HANDLE__: ADC handle
00949   * @retval None
00950   */
00951 #define ADC_DISABLE(__HANDLE__)                                          \
00952   do{                                                                          \
00953          (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS;                           \
00954           __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
00955   } while(0)
00956
00957 /**
00958   * @brief Verification of hardware constraints before ADC can be disabled
00959   * @param __HANDLE__: ADC handle
00960   * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
00961   */
00962 #define ADC_DISABLING_CONDITIONS(__HANDLE__)                             \
00963        (( ( ((__HANDLE__)->Instance->CR) &                                     \
00964             (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN   \
00965         ) ? SET : RESET)
00966
00967 /**
00968   * @brief Shift the offset in function of the selected ADC resolution.
00969   *        Offset has to be left-aligned on bit 15, the LSB (right bits) are set to 0
00970   *        If resolution 16 bits, no shift.
00971   *        If resolution 14 bits, shift of 2 ranks on the left.
00972   *        If resolution 12 bits, shift of 4 ranks on the left.
00973   *        If resolution 10 bits, shift of 6 ranks on the left.
00974   *        If resolution 8 bits, shift of 8 ranks on the left.
00975   *        therefore, shift = (16 - resolution) = 16 - (16 - (((RES[2:0]) >> 2)*2))
00976   * @param __HANDLE__: ADC handle
00977   * @param __OFFSET__: Value to be shifted
00978   * @retval None
00979   */
00980 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
00981         ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 2)*2))
00982
00983 /**
00984   * @brief Shift the AWD1 threshold in function of the selected ADC resolution.
00985   *        Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0.
00986   *        If resolution 16 bits, no shift.
00987   *        If resolution 14 bits, shift of 2 ranks on the left.
00988   *        If resolution 12 bits, shift of 4 ranks on the left.
00989   *        If resolution 10 bits, shift of 6 ranks on the left.
00990   *        If resolution 8 bits, shift of 8 ranks on the left.
00991   *        therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2))
00992   * @param __HANDLE__: ADC handle
00993   * @param __THRESHOLD__: Value to be shifted
00994   * @retval None
00995   */
00996 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
00997         ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 2)*2))
00998
00999 /**
01000   * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.
01001   *        Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0.
01002   *        If resolution 16 bits, no shift.
01003   *        If resolution 14 bits, shift of 2 ranks on the left.
01004   *        If resolution 12 bits, shift of 4 ranks on the left.
01005   *        If resolution 10 bits, shift of 6 ranks on the left.
01006   *        If resolution 8 bits, shift of 8 ranks on the left.
01007   *        therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2))
01008   * @param __HANDLE__: ADC handle
01009   * @param __THRESHOLD__: Value to be shifted
01010   * @retval None
01011   */
01012 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
01013         ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 2)*2))
01014
01015 /**
01016   * @brief Report common register to ADC1 and ADC2
01017   * @param __HANDLE__: ADC handle
01018   * @retval Common control register
01019   */
01020 #define ADC12_COMMON_REGISTER(__HANDLE__)   (ADC12_COMMON)
01021
01022 /**
01023   * @brief Report common register to ADC1 and ADC2
01024   * @param __HANDLE__: ADC handle
01025   * @retval Common control register
01026   */
01027 #define ADC3_COMMON_REGISTER(__HANDLE__)   (ADC3_COMMON)
01028
01029 /**
01030   * @brief Report Master Instance
01031   * @param __HANDLE__: ADC handle
01032   * @note return same instance if ADC of input handle is independent ADC
01033   * @retval Master Instance
01034   */
01035 #define ADC_MASTER_REGISTER(__HANDLE__)                                          \
01036   ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \
01037     )?                                                                           \
01038      ((__HANDLE__)->Instance)                                                    \
01039      :                                                                           \
01040      (ADC1)                                                                      \
01041   )
01042
01043 /**
01044   * @brief Check whether or not dual regular conversions are enabled
01045   * @param __HANDLE__: ADC handle
01046   * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)
01047   */
01048 #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__)                        \
01049   ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
01050     )?                                                                           \
01051      ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT)     &&      \
01052        ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) &&      \
01053        ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) )         \
01054      :                                                                           \
01055      RESET                                                                       \
01056   )
01057
01058 /**
01059   * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master
01060   * @param __HANDLE__: ADC handle
01061   * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode)
01062   */
01063 #define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)                        \
01064   ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)     \
01065     )?                                                                         \
01066      SET                                                                       \
01067      :                                                                         \
01068      ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET)                            \
01069   )
01070
01071 /**
01072   * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master
01073   * @param __HANDLE__: ADC handle
01074   * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode)
01075   */
01076 #define ADC3_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)                        \
01077   ( ( ((__HANDLE__)->Instance == ADC3)                                          \
01078     )?                                                                         \
01079      SET                                                                       \
01080      :                                                                         \
01081      ((ADC3_COMMON->CCR & ADC_CCR_DUAL) == RESET)                            \
01082   )
01083
01084 /**
01085   * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled
01086   * @param __HANDLE__: ADC handle
01087   * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)
01088   */
01089 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__)            \
01090   ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3)  \
01091     )?                                                                      \
01092      SET                                                                    \
01093      :                                                                      \
01094      ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)     || \
01095        ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
01096        ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
01097
01098 /**
01099   * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled
01100   * @param __HANDLE__: ADC handle
01101   * @retval SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)
01102   */
01103 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__)         \
01104   ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
01105     )?                                                                     \
01106      SET                                                                   \
01107      :                                                                     \
01108      ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)    || \
01109        ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT)  || \
01110        ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
01111
01112 /**
01113   * @brief Verification of ADC state: enabled or disabled, directly checked on instance as input parameter
01114   * @param __INSTANCE__: ADC instance
01115   * @retval SET (ADC enabled) or RESET (ADC disabled)
01116   */
01117 #define ADC_INSTANCE_IS_ENABLED(__INSTANCE__)                                                    \
01118        (( ((((__INSTANCE__)->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
01119           ((((__INSTANCE__)->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)                  \
01120         ) ? SET : RESET)
01121
01122 /**
01123   * @brief Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle
01124   * @param __HANDLE__: ADC handle
01125   * @retval SET (at least one other ADC is enabled) or RESET (no other ADC is enabled, all other ADCs are disabled)
01126   */
01127 #define ADC_ANY_OTHER_ENABLED(__HANDLE__)           \
01128   ( ( ((__HANDLE__)->Instance == ADC1)                                         \
01129     )?                                                                         \
01130      (ADC_INSTANCE_IS_ENABLED(ADC2)) || (ADC_INSTANCE_IS_ENABLED(ADC3))  \
01131      :                                                                         \
01132      ( ( ((__HANDLE__)->Instance == ADC2)                                      \
01133        )?                                                                      \
01134          (ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC3))  \
01135         :                                                                      \
01136           ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC2))    \
01137      )                                                                         \
01138
01139 /**
01140   * @brief Set handle instance of the ADC slave associated to the ADC master
01141   * @param __HANDLE_MASTER__: ADC master handle
01142   * @param __HANDLE_SLAVE__: ADC slave handle
01143   * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC (ADC3), __HANDLE_SLAVE__ instance is set to NULL
01144   * @retval None
01145   */
01146 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)             \
01147   ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
01148
01149 /**
01150   * @brief Verify the ADC single-ended input or differential mode setting.
01151   * @param SING_DIFF: programmed channel setting.
01152   * @retval SET (SING_DIFF is valid) or RESET (SING_DIFF is invalid)
01153   */
01154 #define IS_ADC_SINGLE_DIFFERENTIAL(SING_DIFF) (((SING_DIFF) == ADC_SINGLE_ENDED)      || \
01155                                                ((SING_DIFF) == ADC_DIFFERENTIAL_ENDED)  )
01156
01157 /**
01158   * @brief Verify the ADC offset management setting.
01159   * @param OFFSET_NUMBER: ADC offset management.
01160   * @retval SET (OFFSET_NUMBER is valid) or RESET (OFFSET_NUMBER is invalid)
01161   */
01162 #define IS_ADC_OFFSET_NUMBER(OFFSET_NUMBER) (((OFFSET_NUMBER) == ADC_OFFSET_NONE) || \
01163                                              ((OFFSET_NUMBER) == ADC_OFFSET_1)    || \
01164                                              ((OFFSET_NUMBER) == ADC_OFFSET_2)    || \
01165                                              ((OFFSET_NUMBER) == ADC_OFFSET_3)    || \
01166                                              ((OFFSET_NUMBER) == ADC_OFFSET_4)      )
01167
01168 /**
01169   * @brief Verify the ADC injected channel setting.
01170   * @param CHANNEL: programmed ADC injected channel.
01171   * @retval SET (CHANNEL is valid) or RESET (__CHANNEL__ is invalid)
01172   */
01173 #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
01174                                        ((CHANNEL) == ADC_INJECTED_RANK_2) || \
01175                                        ((CHANNEL) == ADC_INJECTED_RANK_3) || \
01176                                        ((CHANNEL) == ADC_INJECTED_RANK_4)   )
01177
01178 /**
01179   * @brief Verify the ADC injected conversions external trigger.
01180   * @param INJTRIG: programmed ADC injected conversions external trigger.
01181   * @retval SET (INJTRIG is a valid value) or RESET (INJTRIG is invalid)
01182   */
01183 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJEC_T1_TRGO)     || \
01184                                       ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T1_CC4)      || \
01185                                       ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T2_TRGO)     || \
01186                                       ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T2_CC1)      || \
01187                                       ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T3_CC4)      || \
01188                                       ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T4_TRGO)     || \
01189                                       ((INJTRIG) == ADC_EXTERNALTRIGINJEC_EXT_IT15)    || \
01190                                       ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T8_CC4)      || \
01191                                       ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)    || \
01192                                       ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T8_TRGO)     || \
01193                                       ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)    || \
01194                                       ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T3_CC3)      || \
01195                                       ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T3_TRGO)     || \
01196                                       ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T3_CC1)      || \
01197                                       ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T6_TRGO)     || \
01198                                       ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T15_TRGO)    || \
01199                                                                                           \
01200                                       ((INJTRIG) == ADC_SOFTWARE_START)                   )
01201
01202 /**
01203   * @brief Verify the ADC edge trigger setting for injected group.
01204   * @param EDGE: programmed ADC edge trigger setting.
01205   * @retval SET (EDGE is a valid value) or RESET (EDGE is invalid)
01206   */
01207 #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)         || \
01208                                         ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
01209                                         ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
01210                                         ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING)  )
01211
01212 /**
01213   * @brief Verify the ADC multimode setting.
01214   * @param MODE: programmed ADC multimode setting.
01215   * @retval SET (MODE is valid) or RESET (MODE is invalid)
01216   */
01217 #define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT)               || \
01218                            ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
01219                            ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)   || \
01220                            ((MODE) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
01221                            ((MODE) == ADC_DUALMODE_INJECSIMULT)           || \
01222                            ((MODE) == ADC_DUALMODE_REGSIMULT)             || \
01223                            ((MODE) == ADC_DUALMODE_INTERL)                || \
01224                            ((MODE) == ADC_DUALMODE_ALTERTRIG)               )
01225
01226 /**
01227   * @brief Verify the ADC dual data mode setting.
01228   * @param MODE: programmed ADC dual mode setting.
01229   * @retval SET (MODE is valid) or RESET (MODE is invalid)
01230   */
01231 #define IS_ADC_DUAL_DATA_MODE(MODE) (((MODE) == ADC_DUALMODEDATAFORMAT_DISABLED)   || \
01232                                      ((MODE) == ADC_DUALMODEDATAFORMAT_32_10_BITS) || \
01233                                      ((MODE) == ADC_DUALMODEDATAFORMAT_8_BITS)     )
01234
01235 /**
01236   * @brief Verify the ADC multimode delay setting.
01237   * @param DELAY: programmed ADC multimode delay setting.
01238   * @retval SET (DELAY is a valid value) or RESET (DELAY is invalid)
01239   */
01240 #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_1CYCLE)   || \
01241                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_2CYCLES)  || \
01242                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_3CYCLES)  || \
01243                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_4CYCLES)  || \
01244                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
01245                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
01246                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
01247                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
01248                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES))
01249
01250 /**
01251   * @brief Verify the ADC analog watchdog setting.
01252   * @param WATCHDOG: programmed ADC analog watchdog setting.
01253   * @retval SET (WATCHDOG is valid) or RESET (WATCHDOG is invalid)
01254   */
01255 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \
01256                                                  ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \
01257                                                  ((WATCHDOG) == ADC_ANALOGWATCHDOG_3)   )
01258
01259 /**
01260   * @brief Verify the ADC analog watchdog mode setting.
01261   * @param WATCHDOG: programmed ADC analog watchdog mode setting.
01262   * @retval SET (WATCHDOG is valid) or RESET (WATCHDOG is invalid)
01263   */
01264 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)             || \
01265                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
01266                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)     || \
01267                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  || \
01268                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)          || \
01269                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC)        || \
01270                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)       )
01271
01272 /**
01273   * @brief Verify the ADC conversion (regular or injected or both).
01274   * @param CONVERSION: ADC conversion group.
01275   * @retval SET (CONVERSION is valid) or RESET (CONVERSION is invalid)
01276   */#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP)         || \
01277                                                  ((CONVERSION) == ADC_INJECTED_GROUP)        || \
01278                                                  ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP)  )
01279
01280 /**
01281   * @brief Verify the ADC event type.
01282   * @param EVENT: ADC event.
01283   * @retval SET (EVENT is valid) or RESET (EVENT is invalid)
01284   */
01285 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_EOSMP_EVENT) || \
01286                                   ((EVENT) == ADC_AWD_EVENT)   || \
01287                                   ((EVENT) == ADC_AWD2_EVENT)  || \
01288                                   ((EVENT) == ADC_AWD3_EVENT)  || \
01289                                   ((EVENT) == ADC_OVR_EVENT)   || \
01290                                   ((EVENT) == ADC_JQOVF_EVENT)  )
01291
01292 /**
01293   * @brief Verify the ADC scan mode.
01294   * @param SCAN_MODE: ADC scan mode.
01295   * @retval SET (SCAN_MODE is valid) or RESET (SCAN_MODE is invalid)
01296   */
01297 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
01298                                      ((SCAN_MODE) == ADC_SCAN_ENABLE)    )
01299
01300 /**
01301   * @brief Verify the ADC oversampling ratio.
01302   * @param RATIO: programmed ADC oversampling ratio.
01303   * @retval SET (RATIO is a valid value) or RESET (RATIO is invalid)
01304   */
01305 #define IS_ADC_OVERSAMPLING_RATIO(RATIO)  ((RATIO) < 1024)
01306
01307 /**
01308   * @brief Verify the ADC oversampling right shift.
01309   * @param SHIFT: programmed ADC oversampling right shift.
01310   * @retval SET (SHIFT is a valid value) or RESET (SHIFT is invalid)
01311   */
01312 #define IS_ADC_RIGHT_BIT_SHIFT(SHIFT)               (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) || \
01313                                                      ((SHIFT) == ADC_RIGHTBITSHIFT_1   ) || \
01314                                                      ((SHIFT) == ADC_RIGHTBITSHIFT_2   ) || \
01315                                                      ((SHIFT) == ADC_RIGHTBITSHIFT_3   ) || \
01316                                                      ((SHIFT) == ADC_RIGHTBITSHIFT_4   ) || \
01317                                                      ((SHIFT) == ADC_RIGHTBITSHIFT_5   ) || \
01318                                                      ((SHIFT) == ADC_RIGHTBITSHIFT_6   ) || \
01319                                                      ((SHIFT) == ADC_RIGHTBITSHIFT_7   ) || \
01320                                                      ((SHIFT) == ADC_RIGHTBITSHIFT_8   ))
01321
01322 /**
01323   * @brief Verify the ADC oversampling left shift.
01324   * @param SHIFT: programmed ADC oversampling left shift.
01325   * @retval SET (SHIFT is a valid value) or RESET (SHIFT is invalid)
01326   */
01327 #define IS_ADC_LEFT_BIT_SHIFT(SHIFT)                (((SHIFT) == ADC_LEFTBITSHIFT_NONE) || \
01328                                                      ((SHIFT) == ADC_LEFTBITSHIFT_1   ) || \
01329                                                      ((SHIFT) == ADC_LEFTBITSHIFT_2   ) || \
01330                                                      ((SHIFT) == ADC_LEFTBITSHIFT_3   ) || \
01331                                                      ((SHIFT) == ADC_LEFTBITSHIFT_4   ) || \
01332                                                      ((SHIFT) == ADC_LEFTBITSHIFT_5   ) || \
01333                                                      ((SHIFT) == ADC_LEFTBITSHIFT_6   ) || \
01334                                                      ((SHIFT) == ADC_LEFTBITSHIFT_7   ) || \
01335                                                      ((SHIFT) == ADC_LEFTBITSHIFT_8   ) || \
01336                                                      ((SHIFT) == ADC_LEFTBITSHIFT_9   ) || \
01337                                                      ((SHIFT) == ADC_LEFTBITSHIFT_10   ) || \
01338                                                      ((SHIFT) == ADC_LEFTBITSHIFT_11   ) || \
01339                                                      ((SHIFT) == ADC_LEFTBITSHIFT_12   ) || \
01340                                                      ((SHIFT) == ADC_LEFTBITSHIFT_13   ) || \
01341                                                      ((SHIFT) == ADC_LEFTBITSHIFT_14   ) || \
01342                                                      ((SHIFT) == ADC_LEFTBITSHIFT_15   ))
01343
01344 /**
01345   * @brief Verify the ADC oversampling triggered mode.
01346   * @param MODE: programmed ADC oversampling triggered mode.
01347   * @retval SET (MODE is valid) or RESET (MODE is invalid)
01348   */
01349 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE) (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
01350                                                   ((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
01351
01352 /**
01353   * @brief Verify the ADC oversampling regular conversion resumed or continued mode.
01354   * @param MODE: programmed ADC oversampling regular conversion resumed or continued mode.
01355   * @retval SET (MODE is valid) or RESET (MODE is invalid)
01356   */
01357 #define IS_ADC_REGOVERSAMPLING_MODE(MODE) (((MODE) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
01358                                            ((MODE) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
01359
01360 /**
01361   * @}
01362   */
01363
01364
01365 /* Exported functions --------------------------------------------------------*/
01366 /** @addtogroup ADCEx_Exported_Functions ADC Extended Exported Functions
01367   * @{
01368   */
01369
01370 /* Initialization/de-initialization functions *********************************/
01371
01372 /** @addtogroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
01373   * @brief    Extended IO operation functions
01374   * @{
01375   */
01376 /* I/O operation functions ****************************************************/
01377
01378 /* ADC calibration */
01379
01380 HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t CalibrationMode, uint32_t SingleDiff);
01381 uint32_t                HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
01382 HAL_StatusTypeDef       HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t* LinearCalib_Buffer);
01383 HAL_StatusTypeDef       HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
01384 HAL_StatusTypeDef       HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer);
01385
01386
01387 /* Blocking mode: Polling */
01388 HAL_StatusTypeDef       HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
01389 HAL_StatusTypeDef       HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
01390 HAL_StatusTypeDef       HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
01391
01392 /* Non-blocking mode: Interruption */
01393 HAL_StatusTypeDef       HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
01394 HAL_StatusTypeDef       HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
01395
01396
01397 /* ADC multimode */
01398 HAL_StatusTypeDef       HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
01399 HAL_StatusTypeDef       HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
01400 uint32_t                HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
01401
01402
01403 /* ADC retrieve conversion value intended to be used with polling or interruption */
01404 uint32_t                HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
01405
01406 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
01407 void                    HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
01408 void                    HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc);
01409 void                    HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc);
01410 void                    HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc);
01411 void                    HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc);
01412
01413
01414 /* ADC Regular conversions stop */
01415 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc);
01416 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc);
01417 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc);
01418 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc);
01419
01420 /**
01421   * @}
01422   */
01423
01424 /** @addtogroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
01425   * @brief    ADC Extended Peripheral Control functions
01426   * @{
01427   */
01428 /* Peripheral Control functions ***********************************************/
01429 HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
01430 HAL_StatusTypeDef       HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
01431 HAL_StatusTypeDef       HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc);
01432 HAL_StatusTypeDef       HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc);
01433 HAL_StatusTypeDef       HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc);
01434 HAL_StatusTypeDef       HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc);
01435
01436 /**
01437   * @}
01438   */
01439
01440 /**
01441   * @}
01442   */
01443
01444 /**
01445   * @}
01446   */
01447
01448 /**
01449   * @}
01450   */
01451
01452 #ifdef __cplusplus
01453 }
01454 #endif
01455
01456 #endif /*__STM32H7xx_ADC_EX_H */
01457
01458
01459 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:37 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_cec.c Source File

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stm32h7xx_hal_cec.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_cec.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   CEC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the High Definition Multimedia Interface
00010   *          Consumer Electronics Control Peripheral (CEC).
00011   *           + Initialization and de-initialization function
00012   *           + IO operation function
00013   *           + Peripheral Control function
00014   *
00015   *
00016   @verbatim
00017  ===============================================================================
00018                         ##### How to use this driver #####
00019  ===============================================================================
00020     [..]
00021     The CEC HAL driver can be used as follow:
00022
00023     (#) Declare a CEC_HandleTypeDef handle structure.
00024     (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
00025         (##) Enable the CEC interface clock.
00026         (##) CEC pins configuration:
00027             (+++) Enable the clock for the CEC GPIOs.
00028             (+++) Configure these CEC pins as alternate function pull-up.
00029         (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
00030              and HAL_CEC_Receive_IT() APIs):
00031             (+++) Configure the CEC interrupt priority.
00032             (+++) Enable the NVIC CEC IRQ handle.
00033             (+++) The specific CEC interrupts (Transmission complete interrupt,
00034                   RXNE interrupt and Error Interrupts) will be managed using the macros
00035                   __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
00036                   and receive process.
00037
00038     (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
00039         in case of Bit Rising Error, Error-Bit generation conditions, device logical
00040         address and Listen mode in the hcec Init structure.
00041
00042     (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
00043
00044   [..]
00045     (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
00046         by calling the customed HAL_CEC_MspInit() API.
00047
00048   @endverbatim
00049   ******************************************************************************
00050   * @attention
00051   *
00052   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00053   *
00054   * Redistribution and use in source and binary forms, with or without modification,
00055   * are permitted provided that the following conditions are met:
00056   *   1. Redistributions of source code must retain the above copyright notice,
00057   *      this list of conditions and the following disclaimer.
00058   *   2. Redistributions in binary form must reproduce the above copyright notice,
00059   *      this list of conditions and the following disclaimer in the documentation
00060   *      and/or other materials provided with the distribution.
00061   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00062   *      may be used to endorse or promote products derived from this software
00063   *      without specific prior written permission.
00064   *
00065   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00066   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00067   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00068   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00069   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00070   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00071   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00072   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00073   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00074   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00075   *
00076   ******************************************************************************
00077   */
00078
00079 /* Includes ------------------------------------------------------------------*/
00080 #include "stm32h7xx_hal.h"
00081
00082 /** @addtogroup STM32H7xx_HAL_Driver
00083   * @{
00084   */
00085
00086 /** @defgroup CEC CEC
00087   * @brief HAL CEC module driver
00088   * @{
00089   */
00090 #ifdef HAL_CEC_MODULE_ENABLED
00091
00092 /* Private typedef -----------------------------------------------------------*/
00093 /* Private define ------------------------------------------------------------*/
00094 /** @defgroup CEC_Private_Constants CEC Private Constants
00095   * @{
00096   */
00097 /**
00098   * @}
00099   */
00100
00101 /* Private macro -------------------------------------------------------------*/
00102 /* Private variables ---------------------------------------------------------*/
00103 /* Private function prototypes -----------------------------------------------*/
00104 /** @defgroup CEC_Private_Functions CEC Private Functions
00105   * @{
00106   */
00107 /**
00108   * @}
00109   */
00110
00111 /* Exported functions ---------------------------------------------------------*/
00112
00113 /** @defgroup CEC_Exported_Functions CEC Exported Functions
00114   * @{
00115   */
00116
00117 /** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
00118   *  @brief    Initialization and Configuration functions
00119   *
00120 @verbatim
00121 ===============================================================================
00122             ##### Initialization and Configuration functions #####
00123  ===============================================================================
00124     [..]
00125     This subsection provides a set of functions allowing to initialize the CEC
00126       (+) The following parameters need to be configured:
00127         (++) SignalFreeTime
00128         (++) Tolerance
00129         (++) BRERxStop                 (RX stopped or not upon Bit Rising Error)
00130         (++) BREErrorBitGen            (Error-Bit generation in case of Bit Rising Error)
00131         (++) LBPEErrorBitGen           (Error-Bit generation in case of Long Bit Period Error)
00132         (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
00133         (++) SignalFreeTimeOption      (SFT Timer start definition)
00134         (++) OwnAddress                (CEC device address)
00135         (++) ListenMode
00136
00137 @endverbatim
00138   * @{
00139   */
00140
00141 /**
00142   * @brief Initializes the CEC mode according to the specified
00143   *         parameters in the CEC_InitTypeDef and creates the associated handle.
00144   * @param hcec: CEC handle
00145   * @retval HAL status
00146   */
00147 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
00148 {
00149   /* Check the CEC handle allocation */
00150   if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))
00151   {
00152     return HAL_ERROR;
00153   }
00154
00155   /* Check the parameters */
00156   assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
00157   assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
00158   assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
00159   assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
00160   assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));
00161   assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
00162   assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
00163   assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
00164   assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
00165   assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress));
00166
00167   if(hcec->gState == HAL_CEC_STATE_RESET)
00168   {
00169     /* Allocate lock resource and initialize it */
00170     hcec->Lock = HAL_UNLOCKED;
00171     /* Init the low level hardware : GPIO, CLOCK */
00172     HAL_CEC_MspInit(hcec);
00173   }
00174   hcec->gState = HAL_CEC_STATE_BUSY;
00175
00176   /* Disable the Peripheral */
00177   __HAL_CEC_DISABLE(hcec);
00178
00179   /* Write to CEC Control Register */
00180   hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop|\
00181                          hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen |\
00182                          hcec->Init.SignalFreeTimeOption |((uint32_t)(hcec->Init.OwnAddress)<<16U) |\
00183                          hcec->Init.ListenMode;
00184
00185   /* Enable the following CEC Transmission/Reception interrupts as
00186    * well as the following CEC Transmission/Reception Errors interrupts
00187    * Rx Byte Received IT
00188    * End of Reception IT
00189    * Rx overrun
00190    * Rx bit rising error
00191    * Rx short bit period error
00192    * Rx long bit period error
00193    * Rx missing acknowledge
00194    * Tx Byte Request IT
00195    * End of Transmission IT
00196    * Tx Missing Acknowledge IT
00197    * Tx-Error IT
00198    * Tx-Buffer Underrun IT
00199    * Tx arbitration lost */
00200   __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
00201
00202   /* Enable the CEC Peripheral */
00203   __HAL_CEC_ENABLE(hcec);
00204
00205   hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00206   hcec->gState = HAL_CEC_STATE_READY;
00207   hcec->RxState = HAL_CEC_STATE_READY;
00208
00209   return HAL_OK;
00210 }
00211
00212 /**
00213   * @brief DeInitializes the CEC peripheral
00214   * @param hcec: CEC handle
00215   * @retval HAL status
00216   */
00217 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
00218 {
00219   /* Check the CEC handle allocation */
00220   if(hcec == NULL)
00221   {
00222     return HAL_ERROR;
00223   }
00224
00225   /* Check the parameters */
00226   assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
00227
00228   hcec->gState = HAL_CEC_STATE_BUSY;
00229
00230   /* DeInit the low level hardware */
00231   HAL_CEC_MspDeInit(hcec);
00232
00233   /* Disable the Peripheral */
00234   __HAL_CEC_DISABLE(hcec);
00235
00236   /* Clear Flags */
00237   __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXEND|CEC_FLAG_TXBR|CEC_FLAG_RXBR|CEC_FLAG_RXEND|CEC_ISR_ALL_ERROR);
00238
00239   /* Disable the following CEC Transmission/Reception interrupts as
00240    * well as the following CEC Transmission/Reception Errors interrupts
00241    * Rx Byte Received IT
00242    * End of Reception IT
00243    * Rx overrun
00244    * Rx bit rising error
00245    * Rx short bit period error
00246    * Rx long bit period error
00247    * Rx missing acknowledge
00248    * Tx Byte Request IT
00249    * End of Transmission IT
00250    * Tx Missing Acknowledge IT
00251    * Tx-Error IT
00252    * Tx-Buffer Underrun IT
00253    * Tx arbitration lost */
00254   __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
00255
00256   hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00257   hcec->gState = HAL_CEC_STATE_RESET;
00258   hcec->RxState = HAL_CEC_STATE_RESET;
00259
00260   /* Process Unlock */
00261   __HAL_UNLOCK(hcec);
00262
00263   return HAL_OK;
00264 }
00265
00266 /**
00267   * @brief Initializes the Own Address of the CEC device
00268   * @param hcec: CEC handle
00269   * @param  CEC_OwnAddress: The CEC own address.
00270   * @retval HAL status
00271   */
00272 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
00273 {
00274   /* Check the parameters */
00275   assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
00276
00277   if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
00278   {
00279     /* Process Locked */
00280     __HAL_LOCK(hcec);
00281
00282     hcec->gState = HAL_CEC_STATE_BUSY;
00283
00284     /* Disable the Peripheral */
00285     __HAL_CEC_DISABLE(hcec);
00286
00287     if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
00288     {
00289       hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16);
00290     }
00291     else
00292     {
00293       hcec->Instance->CFGR &= ~(CEC_CFGR_OAR);
00294     }
00295
00296     hcec->gState = HAL_CEC_STATE_READY;
00297     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00298
00299     /* Process Unlocked */
00300     __HAL_UNLOCK(hcec);
00301
00302     /* Enable the Peripheral */
00303     __HAL_CEC_ENABLE(hcec);
00304
00305     return  HAL_OK;
00306   }
00307   else
00308   {
00309     return HAL_BUSY;
00310   }
00311 }
00312
00313 /**
00314   * @brief CEC MSP Init
00315   * @param hcec: CEC handle
00316   * @retval None
00317   */
00318  __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
00319 {
00320   /* Prevent unused argument(s) compilation warning */
00321   UNUSED(hcec);
00322   /* NOTE : This function should not be modified, when the callback is needed,
00323             the HAL_CEC_MspInit can be implemented in the user file
00324    */
00325 }
00326
00327 /**
00328   * @brief CEC MSP DeInit
00329   * @param hcec: CEC handle
00330   * @retval None
00331   */
00332  __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
00333 {
00334   /* Prevent unused argument(s) compilation warning */
00335   UNUSED(hcec);
00336   /* NOTE : This function should not be modified, when the callback is needed,
00337             the HAL_CEC_MspDeInit can be implemented in the user file
00338    */
00339 }
00340
00341 /**
00342   * @}
00343   */
00344
00345 /** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
00346   *  @brief CEC Transmit/Receive functions
00347   *
00348 @verbatim
00349  ===============================================================================
00350                       ##### IO operation functions #####
00351  ===============================================================================
00352     This subsection provides a set of functions allowing to manage the CEC data transfers.
00353
00354     (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
00355         logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
00356
00357     (#) The communication is performed using Interrupts.
00358            These API's return the HAL status.
00359            The end of the data processing will be indicated through the
00360            dedicated CEC IRQ when using Interrupt mode.
00361            The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
00362            will be executed respectively at the end of the transmit or Receive process
00363            The HAL_CEC_ErrorCallback() user callback will be executed when a communication
00364            error is detected
00365
00366     (#) API's with Interrupt are :
00367          (+) HAL_CEC_Transmit_IT()
00368          (+) HAL_CEC_IRQHandler()
00369
00370     (#) A set of User Callbacks are provided:
00371          (+) HAL_CEC_TxCpltCallback()
00372          (+) HAL_CEC_RxCpltCallback()
00373          (+) HAL_CEC_ErrorCallback()
00374
00375 @endverbatim
00376   * @{
00377   */
00378
00379 /**
00380   * @brief Send data in interrupt mode
00381   * @param hcec: CEC handle
00382   * @param InitiatorAddress: Initiator address
00383   * @param DestinationAddress: destination logical address
00384   * @param pData: pointer to input byte data buffer
00385   * @param Size: amount of data to be sent in bytes (without counting the header).
00386   *              0 means only the header is sent (ping operation).
00387   *              Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
00388   * @retval HAL status
00389   */
00390 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
00391 {
00392   /* if the IP isn't already busy and if there is no previous transmission
00393      already pending due to arbitration lost */
00394   if (hcec->gState == HAL_CEC_STATE_READY)
00395   {
00396     if((pData == NULL ) && (Size > 0))
00397     {
00398       return  HAL_ERROR;
00399     }
00400
00401     assert_param(IS_CEC_ADDRESS(DestinationAddress));
00402     assert_param(IS_CEC_ADDRESS(InitiatorAddress));
00403     assert_param(IS_CEC_MSGSIZE(Size));
00404
00405     /* Process Locked */
00406     __HAL_LOCK(hcec);
00407     hcec->pTxBuffPtr = pData;
00408     hcec->gState = HAL_CEC_STATE_BUSY_TX;
00409     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00410
00411     /* initialize the number of bytes to send,
00412      * 0 means only one header is sent (ping operation) */
00413     hcec->TxXferCount = Size;
00414
00415     /* in case of no payload (Size = 0), sender is only pinging the system;
00416        Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
00417     if (Size == 0)
00418     {
00419       __HAL_CEC_LAST_BYTE_TX_SET(hcec);
00420     }
00421     /* send header block */
00422     hcec->Instance->TXDR = ((uint8_t)(InitiatorAddress << CEC_INITIATOR_LSB_POS) |(uint8_t) DestinationAddress);
00423     /* Set TX Start of Message  (TXSOM) bit */
00424     __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
00425
00426     /* Process Unlocked */
00427     __HAL_UNLOCK(hcec);
00428
00429     return HAL_OK;
00430
00431   }
00432   else
00433   {
00434     return HAL_BUSY;
00435   }
00436 }
00437
00438 /**
00439   * @brief Get size of the received frame.
00440   * @param hcec: CEC handle
00441   * @retval Frame size
00442   */
00443 uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
00444 {
00445   return hcec->RxXferSize;
00446 }
00447
00448 /**
00449   * @brief Change Rx Buffer.
00450   * @param hcec: CEC handle
00451   * @param Rxbuffer: Rx Buffer
00452   * @note  This function can be called only inside the HAL_CEC_RxCpltCallback()
00453   * @retval Frame size
00454   */
00455 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)
00456 {
00457   hcec->Init.RxBuffer = Rxbuffer;
00458 }
00459
00460 /**
00461   * @brief This function handles CEC interrupt requests.
00462   * @param hcec: CEC handle
00463   * @retval None
00464   */
00465 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
00466 {
00467   /* save interrupts register for further error or interrupts handling purposes */
00468   uint32_t reg = 0;
00469   reg = hcec->Instance->ISR;
00470
00471   /*----------------------- Arbitration Lost Management ----------------------*/
00472   /* CEC TX arbitration error interrupt occurred -----------------------------*/
00473   if((reg & CEC_FLAG_ARBLST) != RESET)
00474   {
00475     hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
00476     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
00477   }
00478
00479   /*------------------------------ Rx Management -----------------------------*/
00480   /* CEC RX byte received interrupt  -----------------------------------------*/
00481   if((reg & CEC_FLAG_RXBR) != RESET)
00482   {
00483     /* reception is starting */
00484     hcec->RxState = HAL_CEC_STATE_BUSY_RX;
00485     hcec->RxXferSize++;
00486     /* read received byte */
00487     *hcec->Init.RxBuffer++ = hcec->Instance->RXDR;
00488     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
00489   }
00490
00491   /* CEC RX end received interrupt  ------------------------------------------*/
00492   if((reg & CEC_FLAG_RXEND) != RESET)
00493   {
00494     /* clear IT */
00495     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
00496
00497     /* Rx process is completed, restore hcec->RxState to Ready */
00498     hcec->RxState = HAL_CEC_STATE_READY;
00499     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00500     hcec->Init.RxBuffer-=hcec->RxXferSize;
00501     HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
00502     hcec->RxXferSize = 0;
00503   }
00504
00505   /*------------------------------ Tx Management -----------------------------*/
00506   /* CEC TX byte request interrupt -------------------------------------------*/
00507   if((reg & CEC_FLAG_TXBR) != RESET)
00508   {
00509     if (hcec->TxXferCount == 0)
00510     {
00511       /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
00512       __HAL_CEC_LAST_BYTE_TX_SET(hcec);
00513       hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
00514     }
00515     else
00516     {
00517       hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
00518       hcec->TxXferCount--;
00519     }
00520     /* clear Tx-Byte request flag */
00521     __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
00522   }
00523
00524   /* CEC TX end interrupt ----------------------------------------------------*/
00525   if((reg & CEC_FLAG_TXEND) != RESET)
00526   {
00527     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
00528
00529     /* Tx process is ended, restore hcec->gState to Ready */
00530     hcec->gState = HAL_CEC_STATE_READY;
00531     /* Call the Process Unlocked before calling the Tx call back API to give the
00532        possibility to start again the Transmission under the Tx call back API */
00533     __HAL_UNLOCK(hcec);
00534     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00535     HAL_CEC_TxCpltCallback(hcec);
00536   }
00537
00538   /*------------------------- Rx/Tx Error Management -------------------------*/
00539   if ((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0)
00540   {
00541     hcec->ErrorCode = reg;
00542     __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR|HAL_CEC_ERROR_BRE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|HAL_CEC_ERROR_RXACKE|HAL_CEC_ERROR_TXUDR|HAL_CEC_ERROR_TXERR|HAL_CEC_ERROR_TXACKE);
00543
00544     if((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE)) != RESET)
00545     {
00546       hcec->Init.RxBuffer-=hcec->RxXferSize;
00547       hcec->RxXferSize = 0;
00548       hcec->RxState = HAL_CEC_STATE_READY;
00549     }
00550     else if (((reg & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != RESET) && ((reg & CEC_ISR_ARBLST) == RESET))
00551     {
00552       /* Set the CEC state ready to be able to start again the process */
00553       hcec->gState = HAL_CEC_STATE_READY;
00554     }
00555
00556     /* Error  Call Back */
00557     HAL_CEC_ErrorCallback(hcec);
00558   }
00559 }
00560
00561 /**
00562   * @brief Tx Transfer completed callback
00563   * @param hcec: CEC handle
00564   * @retval None
00565   */
00566  __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
00567 {
00568   /* Prevent unused argument(s) compilation warning */
00569   UNUSED(hcec);
00570   /* NOTE : This function should not be modified, when the callback is needed,
00571             the HAL_CEC_TxCpltCallback can be implemented in the user file
00572    */
00573 }
00574
00575 /**
00576   * @brief Rx Transfer completed callback
00577   * @param hcec: CEC handle
00578   * @param RxFrameSize: Size of frame
00579   * @retval None
00580   */
00581 __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
00582 {
00583   /* Prevent unused argument(s) compilation warning */
00584   UNUSED(hcec);
00585   UNUSED(RxFrameSize);
00586   /* NOTE : This function should not be modified, when the callback is needed,
00587             the HAL_CEC_RxCpltCallback can be implemented in the user file
00588    */
00589 }
00590
00591 /**
00592   * @brief CEC error callbacks
00593   * @param hcec: CEC handle
00594   * @retval None
00595   */
00596  __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
00597 {
00598   /* Prevent unused argument(s) compilation warning */
00599   UNUSED(hcec);
00600   /* NOTE : This function should not be modified, when the callback is needed,
00601             the HAL_CEC_ErrorCallback can be implemented in the user file
00602    */
00603 }
00604
00605 /**
00606   * @}
00607   */
00608
00609 /** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function
00610   *  @brief   CEC control functions
00611   *
00612 @verbatim
00613  ===============================================================================
00614                       ##### Peripheral Control function #####
00615  ===============================================================================
00616     [..]
00617     This subsection provides a set of functions allowing to control the CEC.
00618      (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
00619      (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
00620 @endverbatim
00621   * @{
00622   */
00623 /**
00624   * @brief return the CEC state
00625   * @param hcec: pointer to a CEC_HandleTypeDef structure that contains
00626   *              the configuration information for the specified CEC module.
00627   * @retval HAL state
00628   */
00629 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
00630 {
00631   uint32_t temp1= 0x00U, temp2 = 0x00U;
00632   temp1 = hcec->gState;
00633   temp2 = hcec->RxState;
00634
00635   return (HAL_CEC_StateTypeDef)(temp1 | temp2);
00636 }
00637
00638 /**
00639 * @brief  Return the CEC error code
00640 * @param  hcec : pointer to a CEC_HandleTypeDef structure that contains
00641   *              the configuration information for the specified CEC.
00642 * @retval CEC Error Code
00643 */
00644 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
00645 {
00646   return hcec->ErrorCode;
00647 }
00648
00649 /**
00650   * @}
00651   */
00652
00653 /**
00654   * @}
00655   */
00656 #endif /* HAL_CEC_MODULE_ENABLED */
00657 /**
00658   * @}
00659   */
00660
00661 /**
00662   * @}
00663   */
00664
00665 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:37 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_cec.h Source File

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stm32h7xx_hal_cec.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_cec.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of CEC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_CEC_H
00040 #define __STM32H7xx_HAL_CEC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup CEC
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup CEC_Exported_Types CEC Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief CEC Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t SignalFreeTime;               /*!< Set SFT field, specifies the Signal Free Time.
00068                                               It can be one of @ref CEC_Signal_Free_Time
00069                                               and belongs to the set {0,...,7} where
00070                                               0x0 is the default configuration
00071                                               else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
00072
00073   uint32_t Tolerance;                    /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
00074                                               it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
00075                                               or CEC_EXTENDED_TOLERANCE */
00076
00077   uint32_t BRERxStop;                    /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
00078                                                - CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
00079                                                - CEC_RX_STOP_ON_BRE: reception is stopped. */
00080
00081   uint32_t BREErrorBitGen;               /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
00082                                               CEC line upon Bit Rising Error detection.
00083                                                - CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
00084                                                - CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
00085
00086   uint32_t LBPEErrorBitGen;              /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
00087                                               CEC line upon Long Bit Period Error detection.
00088                                                - CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
00089                                                - CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
00090
00091   uint32_t BroadcastMsgNoErrorBitGen;    /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
00092                                               upon an error detected on a broadcast message.
00093
00094                                               It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
00095
00096                                               - CEC_BROADCASTERROR_ERRORBIT_GENERATION.
00097                                                  - a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
00098                                                     and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
00099                                                  - b) LBPE detection: error-bit generation on the CEC line
00100                                                     if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
00101
00102                                               - CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
00103                                                  no error-bit generation in case neither a) nor b) are satisfied. Additionally,
00104                                                  there is no error-bit generation in case of Short Bit Period Error detection in
00105                                                  a broadcast message while LSTN bit is set. */
00106
00107   uint32_t SignalFreeTimeOption;         /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
00108                                                - CEC_SFT_START_ON_TXSOM SFT:    timer starts when TXSOM is set by software.
00109                                                - CEC_SFT_START_ON_TX_RX_END:  SFT timer starts automatically at the end of message transmission/reception. */
00110
00111   uint32_t ListenMode;                   /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
00112
00113                                               - CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
00114                                                 own address (OAR). Messages addressed to different destination are ignored.
00115                                                 Broadcast messages are always received.
00116
00117                                               - CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
00118                                                 address (OAR) with positive acknowledge. Messages addressed to different destination
00119                                                 are received, but without interfering with the CEC bus: no acknowledge sent.  */
00120
00121   uint16_t  OwnAddress;                  /*!< Own addresses configuration
00122                                              This parameter can be a value of @ref CEC_OWN_ADDRESS */
00123
00124   uint8_t  *RxBuffer;                    /*!< CEC Rx buffer pointer */
00125
00126 }CEC_InitTypeDef;
00127
00128 /**
00129   * @brief HAL CEC State structures definition
00130   * @note  HAL CEC State value is a combination of 2 different substates: gState and RxState.
00131   *        - gState contains CEC state information related to global Handle management
00132   *          and also information related to Tx operations.
00133   *          gState value coding follow below described bitmap :
00134   *          b7 (not used)
00135   *             x  : Should be set to 0
00136   *          b6  Error information
00137   *             0  : No Error
00138   *             1  : Error
00139   *          b5     IP initilisation status
00140   *             0  : Reset (IP not initialized)
00141   *             1  : Init done (IP initialized. HAL CEC Init function already called)
00142   *          b4-b3  (not used)
00143   *             xx : Should be set to 00
00144   *          b2     Intrinsic process state
00145   *             0  : Ready
00146   *             1  : Busy (IP busy with some configuration or internal operations)
00147   *          b1     (not used)
00148   *             x  : Should be set to 0
00149   *          b0     Tx state
00150   *             0  : Ready (no Tx operation ongoing)
00151   *             1  : Busy (Tx operation ongoing)
00152   *        - RxState contains information related to Rx operations.
00153   *          RxState value coding follow below described bitmap :
00154   *          b7-b6  (not used)
00155   *             xx : Should be set to 00
00156   *          b5     IP initilisation status
00157   *             0  : Reset (IP not initialized)
00158   *             1  : Init done (IP initialized)
00159   *          b4-b2  (not used)
00160   *            xxx : Should be set to 000
00161   *          b1     Rx state
00162   *             0  : Ready (no Rx operation ongoing)
00163   *             1  : Busy (Rx operation ongoing)
00164   *          b0     (not used)
00165   *             x  : Should be set to 0.
00166   */
00167 typedef enum
00168 {
00169   HAL_CEC_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
00170                                                    Value is allowed for gState and RxState             */
00171   HAL_CEC_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
00172                                                    Value is allowed for gState and RxState             */
00173   HAL_CEC_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing
00174                                                    Value is allowed for gState only                    */
00175   HAL_CEC_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
00176                                                    Value is allowed for RxState only                   */
00177   HAL_CEC_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
00178                                                    Value is allowed for gState only                    */
00179   HAL_CEC_STATE_BUSY_RX_TX        = 0x23U,    /*!< an internal process is ongoing
00180                                                    Value is allowed for gState only                    */
00181   HAL_CEC_STATE_ERROR             = 0x60U     /*!< Error Value is allowed for gState only              */
00182 }HAL_CEC_StateTypeDef;
00183
00184 /**
00185   * @brief  CEC handle Structure definition
00186   */
00187 typedef struct
00188 {
00189   CEC_TypeDef             *Instance;      /*!< CEC registers base address */
00190
00191   CEC_InitTypeDef         Init;           /*!< CEC communication parameters */
00192
00193   uint8_t                 *pTxBuffPtr;    /*!< Pointer to CEC Tx transfer Buffer */
00194
00195   uint16_t                TxXferCount;    /*!< CEC Tx Transfer Counter */
00196
00197   uint16_t                RxXferSize;     /*!< CEC Rx Transfer size, 0: header received only */
00198
00199   HAL_LockTypeDef         Lock;           /*!< Locking object */
00200
00201   HAL_CEC_StateTypeDef    gState;         /*!< CEC state information related to global Handle management
00202                                                and also related to Tx operations.
00203                                                This parameter can be a value of @ref HAL_CEC_StateTypeDef */
00204
00205   HAL_CEC_StateTypeDef    RxState;        /*!< CEC state information related to Rx operations.
00206                                                This parameter can be a value of @ref HAL_CEC_StateTypeDef */
00207
00208   uint32_t                ErrorCode;      /*!< For errors handling purposes, copy of ISR register
00209                                                in case error is reported */
00210 }CEC_HandleTypeDef;
00211 /**
00212   * @}
00213   */
00214
00215 /* Exported constants --------------------------------------------------------*/
00216 /** @defgroup CEC_Exported_Constants CEC Exported Constants
00217   * @{
00218   */
00219
00220 /** @defgroup CEC_Error_Code CEC Error Code
00221   * @{
00222   */
00223 #define HAL_CEC_ERROR_NONE    (uint32_t) 0x0000U     /*!< no error                      */
00224 #define HAL_CEC_ERROR_RXOVR   CEC_ISR_RXOVR          /*!< CEC Rx-Overrun                */
00225 #define HAL_CEC_ERROR_BRE     CEC_ISR_BRE            /*!< CEC Rx Bit Rising Error       */
00226 #define HAL_CEC_ERROR_SBPE    CEC_ISR_SBPE           /*!< CEC Rx Short Bit period Error */
00227 #define HAL_CEC_ERROR_LBPE    CEC_ISR_LBPE           /*!< CEC Rx Long Bit period Error  */
00228 #define HAL_CEC_ERROR_RXACKE  CEC_ISR_RXACKE         /*!< CEC Rx Missing Acknowledge    */
00229 #define HAL_CEC_ERROR_ARBLST  CEC_ISR_ARBLST         /*!< CEC Arbitration Lost          */
00230 #define HAL_CEC_ERROR_TXUDR   CEC_ISR_TXUDR          /*!< CEC Tx-Buffer Underrun        */
00231 #define HAL_CEC_ERROR_TXERR   CEC_ISR_TXERR          /*!< CEC Tx-Error                  */
00232 #define HAL_CEC_ERROR_TXACKE  CEC_ISR_TXACKE         /*!< CEC Tx Missing Acknowledge    */
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup CEC_Signal_Free_Time  CEC Signal Free Time setting parameter
00238   * @{
00239   */
00240 #define CEC_DEFAULT_SFT                    ((uint32_t)0x00000000U)
00241 #define CEC_0_5_BITPERIOD_SFT              ((uint32_t)0x00000001U)
00242 #define CEC_1_5_BITPERIOD_SFT              ((uint32_t)0x00000002U)
00243 #define CEC_2_5_BITPERIOD_SFT              ((uint32_t)0x00000003U)
00244 #define CEC_3_5_BITPERIOD_SFT              ((uint32_t)0x00000004U)
00245 #define CEC_4_5_BITPERIOD_SFT              ((uint32_t)0x00000005U)
00246 #define CEC_5_5_BITPERIOD_SFT              ((uint32_t)0x00000006U)
00247 #define CEC_6_5_BITPERIOD_SFT              ((uint32_t)0x00000007U)
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup CEC_Tolerance CEC Receiver Tolerance
00253   * @{
00254   */
00255 #define CEC_STANDARD_TOLERANCE             ((uint32_t)0x00000000U)
00256 #define CEC_EXTENDED_TOLERANCE             ((uint32_t)CEC_CFGR_RXTOL)
00257 /**
00258   * @}
00259   */
00260
00261 /** @defgroup CEC_BRERxStop CEC Reception Stop on Error
00262   * @{
00263   */
00264 #define CEC_NO_RX_STOP_ON_BRE             ((uint32_t)0x00000000U)
00265 #define CEC_RX_STOP_ON_BRE                ((uint32_t)CEC_CFGR_BRESTP)
00266 /**
00267   * @}
00268   */
00269
00270 /** @defgroup CEC_BREErrorBitGen  CEC Error Bit Generation if Bit Rise Error reported
00271   * @{
00272   */
00273 #define CEC_BRE_ERRORBIT_NO_GENERATION     ((uint32_t)0x00000000U)
00274 #define CEC_BRE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_BREGEN)
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup CEC_LBPEErrorBitGen  CEC Error Bit Generation if Long Bit Period Error reported
00280   * @{
00281   */
00282 #define CEC_LBPE_ERRORBIT_NO_GENERATION     ((uint32_t)0x00000000U)
00283 #define CEC_LBPE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_LBPEGEN)
00284 /**
00285   * @}
00286   */
00287
00288 /** @defgroup CEC_BroadCastMsgErrorBitGen  CEC Error Bit Generation on Broadcast message
00289   * @{
00290   */
00291 #define CEC_BROADCASTERROR_ERRORBIT_GENERATION     ((uint32_t)0x00000000U)
00292 #define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION  ((uint32_t)CEC_CFGR_BRDNOGEN)
00293 /**
00294   * @}
00295   */
00296
00297 /** @defgroup CEC_SFT_Option     CEC Signal Free Time start option
00298   * @{
00299   */
00300 #define CEC_SFT_START_ON_TXSOM           ((uint32_t)0x00000000U)
00301 #define CEC_SFT_START_ON_TX_RX_END       ((uint32_t)CEC_CFGR_SFTOPT)
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup CEC_Listening_Mode    CEC Listening mode option
00307   * @{
00308   */
00309 #define CEC_REDUCED_LISTENING_MODE          ((uint32_t)0x00000000U)
00310 #define CEC_FULL_LISTENING_MODE             ((uint32_t)CEC_CFGR_LSTN)
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup CEC_OAR_Position   CEC Device Own Address position in CEC CFGR register
00316   * @{
00317   */
00318 #define CEC_CFGR_OAR_LSB_POS            ((uint32_t) 16U)
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup CEC_Initiator_Position   CEC Initiator logical address position in message header
00324   * @{
00325   */
00326 #define CEC_INITIATOR_LSB_POS           ((uint32_t) 4U)
00327 /**
00328   * @}
00329   */
00330
00331 /** @defgroup CEC_OWN_ADDRESS   CEC Own Address
00332   * @{
00333   */
00334 #define CEC_OWN_ADDRESS_NONE           ((uint16_t) 0x0000U)   /* Reset value */
00335 #define CEC_OWN_ADDRESS_0              ((uint16_t) 0x0001U)   /* Logical Address 0 */
00336 #define CEC_OWN_ADDRESS_1              ((uint16_t) 0x0002U)   /* Logical Address 1 */
00337 #define CEC_OWN_ADDRESS_2              ((uint16_t) 0x0004U)   /* Logical Address 2 */
00338 #define CEC_OWN_ADDRESS_3              ((uint16_t) 0x0008U)   /* Logical Address 3 */
00339 #define CEC_OWN_ADDRESS_4              ((uint16_t) 0x0010U)   /* Logical Address 4 */
00340 #define CEC_OWN_ADDRESS_5              ((uint16_t) 0x0020U)   /* Logical Address 5 */
00341 #define CEC_OWN_ADDRESS_6              ((uint16_t) 0x0040U)   /* Logical Address 6 */
00342 #define CEC_OWN_ADDRESS_7              ((uint16_t) 0x0080U)   /* Logical Address 7 */
00343 #define CEC_OWN_ADDRESS_8              ((uint16_t) 0x0100U)   /* Logical Address 9 */
00344 #define CEC_OWN_ADDRESS_9              ((uint16_t) 0x0200U)   /* Logical Address 10 */
00345 #define CEC_OWN_ADDRESS_10             ((uint16_t) 0x0400U)   /* Logical Address 11 */
00346 #define CEC_OWN_ADDRESS_11             ((uint16_t) 0x0800U)   /* Logical Address 12 */
00347 #define CEC_OWN_ADDRESS_12             ((uint16_t) 0x1000U)   /* Logical Address 13 */
00348 #define CEC_OWN_ADDRESS_13             ((uint16_t) 0x2000U)   /* Logical Address 14 */
00349 #define CEC_OWN_ADDRESS_14             ((uint16_t) 0x4000U)   /* Logical Address 15 */
00350 /**
00351   * @}
00352   */
00353
00354 /** @defgroup CEC_Interrupts_Definitions  CEC Interrupts definition
00355   * @{
00356   */
00357 #define CEC_IT_TXACKE                   CEC_IER_TXACKEIE
00358 #define CEC_IT_TXERR                    CEC_IER_TXERRIE
00359 #define CEC_IT_TXUDR                    CEC_IER_TXUDRIE
00360 #define CEC_IT_TXEND                    CEC_IER_TXENDIE
00361 #define CEC_IT_TXBR                     CEC_IER_TXBRIE
00362 #define CEC_IT_ARBLST                   CEC_IER_ARBLSTIE
00363 #define CEC_IT_RXACKE                   CEC_IER_RXACKEIE
00364 #define CEC_IT_LBPE                     CEC_IER_LBPEIE
00365 #define CEC_IT_SBPE                     CEC_IER_SBPEIE
00366 #define CEC_IT_BRE                      CEC_IER_BREIE
00367 #define CEC_IT_RXOVR                    CEC_IER_RXOVRIE
00368 #define CEC_IT_RXEND                    CEC_IER_RXENDIE
00369 #define CEC_IT_RXBR                     CEC_IER_RXBRIE
00370 /**
00371   * @}
00372   */
00373
00374 /** @defgroup CEC_Flags_Definitions  CEC Flags definition
00375   * @{
00376   */
00377 #define CEC_FLAG_TXACKE                 CEC_ISR_TXACKE
00378 #define CEC_FLAG_TXERR                  CEC_ISR_TXERR
00379 #define CEC_FLAG_TXUDR                  CEC_ISR_TXUDR
00380 #define CEC_FLAG_TXEND                  CEC_ISR_TXEND
00381 #define CEC_FLAG_TXBR                   CEC_ISR_TXBR
00382 #define CEC_FLAG_ARBLST                 CEC_ISR_ARBLST
00383 #define CEC_FLAG_RXACKE                 CEC_ISR_RXACKE
00384 #define CEC_FLAG_LBPE                   CEC_ISR_LBPE
00385 #define CEC_FLAG_SBPE                   CEC_ISR_SBPE
00386 #define CEC_FLAG_BRE                    CEC_ISR_BRE
00387 #define CEC_FLAG_RXOVR                  CEC_ISR_RXOVR
00388 #define CEC_FLAG_RXEND                  CEC_ISR_RXEND
00389 #define CEC_FLAG_RXBR                   CEC_ISR_RXBR
00390 /**
00391   * @}
00392   */
00393
00394 /** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
00395   * @{
00396   */
00397 #define CEC_ISR_ALL_ERROR              ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
00398                                                   CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
00399 /**
00400   * @}
00401   */
00402
00403 /** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
00404   * @{
00405   */
00406 #define CEC_IER_RX_ALL_ERR              ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
00407 /**
00408   * @}
00409   */
00410
00411 /** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
00412   * @{
00413   */
00414 #define CEC_IER_TX_ALL_ERR              ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
00415 /**
00416   * @}
00417   */
00418
00419 /**
00420   * @}
00421   */
00422
00423 /* Exported macros -----------------------------------------------------------*/
00424 /** @defgroup CEC_Exported_Macros CEC Exported Macros
00425   * @{
00426   */
00427
00428 /** @brief  Reset CEC handle gstate & RxState
00429   * @param  __HANDLE__: CEC handle.
00430   * @retval None
00431   */
00432 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \
00433                                                        (__HANDLE__)->gState = HAL_CEC_STATE_RESET;     \
00434                                                        (__HANDLE__)->RxState = HAL_CEC_STATE_RESET;    \
00435                                                      } while(0)
00436
00437 /** @brief  Checks whether or not the specified CEC interrupt flag is set.
00438   * @param  __HANDLE__: specifies the CEC Handle.
00439   * @param  __FLAG__: specifies the flag to check.
00440   *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
00441   *            @arg CEC_FLAG_TXERR: Tx Error.
00442   *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
00443   *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
00444   *            @arg CEC_FLAG_TXBR: Tx-Byte Request.
00445   *            @arg CEC_FLAG_ARBLST: Arbitration Lost
00446   *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
00447   *            @arg CEC_FLAG_LBPE: Rx Long period Error
00448   *            @arg CEC_FLAG_SBPE: Rx Short period Error
00449   *            @arg CEC_FLAG_BRE: Rx Bit Rising Error
00450   *            @arg CEC_FLAG_RXOVR: Rx Overrun.
00451   *            @arg CEC_FLAG_RXEND: End Of Reception.
00452   *            @arg CEC_FLAG_RXBR: Rx-Byte Received.
00453   * @retval ITStatus
00454   */
00455 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ISR & (__FLAG__))
00456
00457 /** @brief  Clears the interrupt or status flag when raised (write at 1)
00458   * @param  __HANDLE__: specifies the CEC Handle.
00459   * @param  __FLAG__: specifies the interrupt/status flag to clear.
00460   *        This parameter can be one of the following values:
00461   *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
00462   *            @arg CEC_FLAG_TXERR: Tx Error.
00463   *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
00464   *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
00465   *            @arg CEC_FLAG_TXBR: Tx-Byte Request.
00466   *            @arg CEC_FLAG_ARBLST: Arbitration Lost
00467   *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
00468   *            @arg CEC_FLAG_LBPE: Rx Long period Error
00469   *            @arg CEC_FLAG_SBPE: Rx Short period Error
00470   *            @arg CEC_FLAG_BRE: Rx Bit Rising Error
00471   *            @arg CEC_FLAG_RXOVR: Rx Overrun.
00472   *            @arg CEC_FLAG_RXEND: End Of Reception.
00473   *            @arg CEC_FLAG_RXBR: Rx-Byte Received.
00474   * @retval none
00475   */
00476 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->ISR |= (__FLAG__))
00477
00478 /** @brief  Enables the specified CEC interrupt.
00479   * @param  __HANDLE__: specifies the CEC Handle.
00480   * @param  __INTERRUPT__: specifies the CEC interrupt to enable.
00481   *          This parameter can be one of the following values:
00482   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
00483   *            @arg CEC_IT_TXERR: Tx Error IT Enable
00484   *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
00485   *            @arg CEC_IT_TXEND: End of transmission IT Enable
00486   *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
00487   *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
00488   *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
00489   *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable
00490   *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable
00491   *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
00492   *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable
00493   *            @arg CEC_IT_RXEND: End Of Reception IT Enable
00494   *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
00495   * @retval none
00496   */
00497 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
00498
00499 /** @brief  Disables the specified CEC interrupt.
00500   * @param  __HANDLE__: specifies the CEC Handle.
00501   * @param  __INTERRUPT__: specifies the CEC interrupt to disable.
00502   *          This parameter can be one of the following values:
00503   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
00504   *            @arg CEC_IT_TXERR: Tx Error IT Enable
00505   *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
00506   *            @arg CEC_IT_TXEND: End of transmission IT Enable
00507   *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
00508   *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
00509   *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
00510   *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable
00511   *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable
00512   *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
00513   *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable
00514   *            @arg CEC_IT_RXEND: End Of Reception IT Enable
00515   *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
00516   * @retval none
00517   */
00518 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
00519
00520 /** @brief  Checks whether or not the specified CEC interrupt is enabled.
00521   * @param  __HANDLE__: specifies the CEC Handle.
00522   * @param  __INTERRUPT__: specifies the CEC interrupt to check.
00523   *          This parameter can be one of the following values:
00524   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
00525   *            @arg CEC_IT_TXERR: Tx Error IT Enable
00526   *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
00527   *            @arg CEC_IT_TXEND: End of transmission IT Enable
00528   *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
00529   *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
00530   *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
00531   *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable
00532   *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable
00533   *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
00534   *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable
00535   *            @arg CEC_IT_RXEND: End Of Reception IT Enable
00536   *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
00537   * @retval FlagStatus
00538   */
00539 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
00540
00541 /** @brief  Enables the CEC device
00542   * @param  __HANDLE__: specifies the CEC Handle.
00543   * @retval none
00544   */
00545 #define __HAL_CEC_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR |=  CEC_CR_CECEN)
00546
00547 /** @brief  Disables the CEC device
00548   * @param  __HANDLE__: specifies the CEC Handle.
00549   * @retval none
00550   */
00551 #define __HAL_CEC_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR &=  ~CEC_CR_CECEN)
00552
00553 /** @brief  Set Transmission Start flag
00554   * @param  __HANDLE__: specifies the CEC Handle.
00555   * @retval none
00556   */
00557 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__)        ((__HANDLE__)->Instance->CR |=  CEC_CR_TXSOM)
00558
00559 /** @brief  Set Transmission End flag
00560   * @param  __HANDLE__: specifies the CEC Handle.
00561   * @retval none
00562   * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
00563   */
00564 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__)         ((__HANDLE__)->Instance->CR |=  CEC_CR_TXEOM)
00565
00566 /** @brief  Get Transmission Start flag
00567   * @param  __HANDLE__: specifies the CEC Handle.
00568   * @retval FlagStatus
00569   */
00570 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
00571
00572 /** @brief  Get Transmission End flag
00573   * @param  __HANDLE__: specifies the CEC Handle.
00574   * @retval FlagStatus
00575   */
00576 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__)   ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
00577
00578 /** @brief  Clear OAR register
00579   * @param  __HANDLE__: specifies the CEC Handle.
00580   * @retval none
00581   */
00582 #define __HAL_CEC_CLEAR_OAR(__HANDLE__)   CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
00583
00584 /** @brief  Set OAR register (without resetting previously set address in case of multi-address mode)
00585   *          To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
00586   * @param  __HANDLE__: specifies the CEC Handle.
00587   * @param  __ADDRESS__: Own Address value (CEC logical address is identified by bit position)
00588   * @retval none
00589   */
00590 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__)   SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
00591
00592 /**
00593   * @}
00594   */
00595
00596 /* Exported functions --------------------------------------------------------*/
00597 /** @addtogroup CEC_Exported_Functions
00598   * @{
00599   */
00600
00601 /** @addtogroup CEC_Exported_Functions_Group1
00602   * @{
00603   */
00604 /* Initialization and de-initialization functions  ****************************/
00605 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
00606 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
00607 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
00608 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
00609 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
00610 /**
00611   * @}
00612   */
00613
00614 /** @addtogroup CEC_Exported_Functions_Group2
00615   * @{
00616   */
00617 /* I/O operation functions  ***************************************************/
00618 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
00619 uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
00620 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
00621 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
00622 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
00623 void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
00624 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
00625 /**
00626   * @}
00627   */
00628
00629 /** @addtogroup CEC_Exported_Functions_Group3
00630   * @{
00631   */
00632 /* Peripheral State functions  ************************************************/
00633 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
00634 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
00635 /**
00636   * @}
00637   */
00638
00639 /**
00640   * @}
00641   */
00642
00643 /* Private types -------------------------------------------------------------*/
00644 /** @defgroup CEC_Private_Types CEC Private Types
00645   * @{
00646   */
00647
00648 /**
00649   * @}
00650   */
00651
00652 /* Private variables ---------------------------------------------------------*/
00653 /** @defgroup CEC_Private_Variables CEC Private Variables
00654   * @{
00655   */
00656
00657 /**
00658   * @}
00659   */
00660
00661 /* Private constants ---------------------------------------------------------*/
00662 /** @defgroup CEC_Private_Constants CEC Private Constants
00663   * @{
00664   */
00665
00666 /**
00667   * @}
00668   */
00669
00670 /* Private macros ------------------------------------------------------------*/
00671 /** @defgroup CEC_Private_Macros CEC Private Macros
00672   * @{
00673   */
00674
00675 #define IS_CEC_SIGNALFREETIME(__SFT__)     ((__SFT__) <= CEC_CFGR_SFT)
00676
00677 #define IS_CEC_TOLERANCE(__RXTOL__)        (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
00678                                             ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
00679
00680 #define IS_CEC_BRERXSTOP(__BRERXSTOP__)   (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
00681                                            ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
00682
00683 #define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
00684                                                 ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
00685
00686 #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
00687                                                  ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
00688
00689 #define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
00690                                                                        ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
00691
00692 #define IS_CEC_SFTOP(__SFTOP__)          (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
00693                                           ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
00694
00695 #define IS_CEC_LISTENING_MODE(__MODE__)     (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
00696                                              ((__MODE__) == CEC_FULL_LISTENING_MODE))
00697
00698 /** @brief Check CEC message size.
00699   *       The message size is the payload size: without counting the header,
00700   *       it varies from 0 byte (ping operation, one header only, no payload) to
00701   *       15 bytes (1 opcode and up to 14 operands following the header).
00702   * @param  __SIZE__: CEC message size.
00703   * @retval Test result (TRUE or FALSE).
00704   */
00705 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10)
00706
00707 /** @brief Check CEC device Own Address Register (OAR) setting.
00708   *        OAR address is written in a 15-bit field within CEC_CFGR register.
00709   * @param  __ADDRESS__: CEC own address.
00710   * @retval Test result (TRUE or FALSE).
00711   */
00712 #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFF)
00713
00714 /** @brief Check CEC initiator or destination logical address setting.
00715   *        Initiator and destination addresses are coded over 4 bits.
00716   * @param  __ADDRESS__: CEC initiator or logical address.
00717   * @retval Test result (TRUE or FALSE).
00718   */
00719 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
00720 /**
00721   * @}
00722   */
00723 /* Private functions ---------------------------------------------------------*/
00724 /** @defgroup CEC_Private_Functions CEC Private Functions
00725   * @{
00726   */
00727
00728 /**
00729   * @}
00730   */
00731
00732 /**
00733   * @}
00734   */
00735
00736 /**
00737   * @}
00738   */
00739
00740 #ifdef __cplusplus
00741 }
00742 #endif
00743
00744 #endif /* __STM32H7xx_HAL_CEC_H */
00745
00746 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:37 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_comp.c Source File

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stm32h7xx_hal_comp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_comp.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   COMP HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the COMP peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + Start/Stop operation functions in polling mode
00012   *           + Start/Stop operation functions in interrupt mode
00013   *           + Peripheral control functions
00014   *           + Peripheral state functions
00015   @verbatim
00016   ================================================================================
00017                    ##### COMP Peripheral features #####
00018   ================================================================================
00019
00020   [..]
00021       The STM32H7xx device family integrates two analog comparators instances
00022       COMP1 and COMP2:
00023       (#) The COMP input minus (inverting input) and input plus (non inverting input)
00024           can be set to internal references or to GPIO pins
00025           (refer to GPIO list in reference manual).
00026
00027       (#) The COMP output level is available using HAL_COMP_GetOutputLevel()
00028           and can be redirected to other peripherals: GPIO pins (in mode
00029           alternate functions for comparator), timers.
00030           (refer to GPIO list in reference manual).
00031
00032       (#) Pairs of comparators instances can be combined in window mode
00033           (2 consecutive instances odd and even COMP<x> and COMP<x+1>).
00034
00035       (#) The comparators have interrupt capability through the EXTI controller
00036           with wake-up from sleep and stop modes:
00037           (++) COMP1 is internally connected to EXTI Line 20
00038           (++) COMP2 is internally connected to EXTI Line 21
00039
00040   [..]
00041           From the corresponding IRQ handler, the right interrupt source can be retrieved
00042           using macro __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG().
00043
00044
00045
00046             ##### How to use this driver #####
00047   ================================================================================
00048   [..]
00049       This driver provides functions to configure and program the comparator instances of
00050       STM32H7xx devices.
00051
00052       To use the comparator, perform the following steps:
00053
00054       (#)  Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
00055       (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
00056            using HAL_GPIO_Init().
00057       (++) If needed, configure the GPIO connected to comparator output in alternate function mode
00058            using HAL_GPIO_Init().
00059       (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
00060            selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
00061            interrupt vector using HAL_NVIC_EnableIRQ() function.
00062
00063       (#) Configure the comparator using HAL_COMP_Init() function:
00064       (++) Select the input minus (inverting input)
00065       (++) Select the input plus (non-inverting input)
00066       (++) Select the hysteresis
00067       (++) Select the blanking source
00068       (++) Select the output polarity
00069       (++) Select the power mode
00070       (++) Select the window mode
00071       -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
00072           to enable internal control clock of the comparators.
00073           However, this is a legacy strategy.
00074           Therefore, for compatibility anticipation, it is recommended to
00075           implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".
00076           In STM32H7,COMP clock enable  __HAL_RCC_COMP12_CLK_ENABLE() must
00077           be implemented by user in "HAL_COMP_MspInit()".
00078       (#) Reconfiguration on-the-fly of comparator can be done by calling again
00079           function HAL_COMP_Init() with new input structure parameters values.
00080
00081       (#) Enable the comparator using HAL_COMP_Start() or HAL_COMP_Start_IT()to be enabled
00082           with the interrupt through NVIC of the CPU.
00083       Note: HAL_COMP_Start_IT() must be called after each interrupt otherwise the interrupt
00084       mode will stay disabled.
00085
00086       (#) Use HAL_COMP_GetOutputLevel() or HAL_COMP_TriggerCallback()
00087           functions to manage comparator outputs(output level or events)
00088
00089       (#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT()
00090           to disable the interrupt too.
00091
00092       (#) De-initialize the comparator using HAL_COMP_DeInit() function.
00093
00094       (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
00095           The only way to unlock the comparator is a device hardware reset.
00096   @endverbatim
00097   ******************************************************************************
00098
00099   Table 1. COMP inputs and output for STM32H7xx devices
00100   +---------------------------------------------------------+
00101   |                |                |   COMP1   |   COMP2   |
00102   |----------------|----------------|-----------|-----------|
00103   |                | IO1            |    PB0    |    PE9    |
00104   | Input plus     | IO2            |    PB2    |    PE11   |
00105   |                |                |           |           |
00106   |----------------|----------------|-----------------------|
00107   |                | 1/4 VrefInt    | Available | Available |
00108   |                | 1/2 VrefInt    | Available | Available |
00109   |                | 3/4 VrefInt    | Available | Available |
00110   | Input minus    | VrefInt        | Available | Available |
00111   |                | DAC1 channel 1 | Available | Available |
00112   |                | DAC1 channel 2 | Available | Available |
00113   |                | IO1            |    PB1    |    PE10   |
00114   |                | IO2            |    PC4    |    PE7    |
00115   |                |                |           |           |
00116   |                |                |           |           |
00117   |                |                |           |           |
00118   +---------------------------------------------------------+
00119   | Output         |                |  PC5  (1) |  PE8  (1) |
00120   |                |                |  PE12 (1) |  PE13 (1) |
00121   |                |                |  TIM  (2) |  TIM  (2) |
00122   +---------------------------------------------------------+
00123   (1) GPIO must be set to alternate function for comparator
00124   (2) Comparators output to timers is set in timers instances.
00125
00126   ******************************************************************************
00127   * @attention
00128   *
00129   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00130   *
00131   * Redistribution and use in source and binary forms, with or without modification,
00132   * are permitted provided that the following conditions are met:
00133   *   1. Redistributions of source code must retain the above copyright notice,
00134   *      this list of conditions and the following disclaimer.
00135   *   2. Redistributions in binary form must reproduce the above copyright notice,
00136   *      this list of conditions and the following disclaimer in the documentation
00137   *      and/or other materials provided with the distribution.
00138   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00139   *      may be used to endorse or promote products derived from this software
00140   *      without specific prior written permission.
00141   *
00142   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00143   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00144   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00145   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00146   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00147   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00148   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00149   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00150   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00151   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00152   *
00153   ******************************************************************************
00154   */
00155
00156 /* Includes ------------------------------------------------------------------*/
00157 #include "stm32h7xx_hal.h"
00158
00159 /** @addtogroup STM32H7xx_HAL_Driver
00160   * @{
00161   */
00162
00163 /** @defgroup COMP COMP
00164   * @brief COMP HAL module driver
00165   * @{
00166   */
00167
00168 #ifdef HAL_COMP_MODULE_ENABLED
00169
00170 /* Private typedef -----------------------------------------------------------*/
00171 /* Private define ------------------------------------------------------------*/
00172 /** @addtogroup COMP_Private_Constants
00173   * @{
00174   */
00175
00176 /* Delay for COMP startup time.                                               */
00177 /* Note: Delay required to reach propagation delay specification.             */
00178 /* Literal set to maximum value (refer to device datasheet,                   */
00179 /* parameter "tSTART").                                                       */
00180 /* Unit: us                                                                   */
00181 #define COMP_DELAY_STARTUP_US          ((uint32_t) 80U)  /*!< Delay for COMP startup time */
00182
00183 /* Delay for COMP voltage scaler stabilization time.                          */
00184 /* Literal set to maximum value (refer to device datasheet,                   */
00185 /* parameter "tSTART_SCALER").                                                */
00186 /* Unit: us                                                                   */
00187 #define COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U)  /*!< Delay for COMP voltage scaler stabilization time */
00188
00189
00190 /**
00191   * @}
00192   */
00193
00194 /* Private macro -------------------------------------------------------------*/
00195 /* Private variables ---------------------------------------------------------*/
00196 /* Private function prototypes -----------------------------------------------*/
00197 /* Exported functions --------------------------------------------------------*/
00198
00199 /** @defgroup COMP_Exported_Functions COMP Exported Functions
00200   * @{
00201   */
00202
00203 /** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
00204  *  @brief    Initialization and de-initialization functions.
00205  *
00206 @verbatim
00207  ===============================================================================
00208               ##### Initialization and de-initialization functions #####
00209  ===============================================================================
00210     [..]  This section provides functions to initialize and de-initialize comparators
00211
00212 @endverbatim
00213   * @{
00214   */
00215
00216 /**
00217   * @brief  Initialize the COMP according to the specified
00218   *         parameters in the COMP_InitTypeDef and initialize the associated handle.
00219   * @note   If the selected comparator is locked, initialization can't be performed.
00220   *         To unlock the configuration, perform a system reset.
00221   * @param  hcomp: COMP handle
00222   * @retval HAL status
00223   */
00224 HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
00225 {
00226   uint32_t tmp_csr = 0;
00227   uint32_t exti_line = 0;
00228   uint32_t comp_voltage_scaler_not_initialized = 0;
00229   __IO uint32_t wait_loop_index = 0;
00230
00231   HAL_StatusTypeDef status = HAL_OK;
00232
00233   /* Check the COMP handle allocation and lock status */
00234   if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
00235   {
00236     status = HAL_ERROR;
00237   }
00238   else
00239   {
00240     /* Check the parameters */
00241     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00242     assert_param(IS_COMP_INPUT_PLUS(hcomp->Instance, hcomp->Init.NonInvertingInput));
00243     assert_param(IS_COMP_INPUT_MINUS(hcomp->Instance, hcomp->Init.InvertingInput));
00244     assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
00245     assert_param(IS_COMP_POWERMODE(hcomp->Init.Mode));
00246     assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
00247     assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce));
00248     assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
00249     assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));
00250
00251     if(hcomp->State == HAL_COMP_STATE_RESET)
00252     {
00253    /* Allocate lock resource and initialize it */
00254       hcomp->Lock = HAL_UNLOCKED;
00255
00256       /* Init the low level hardware */
00257       HAL_COMP_MspInit(hcomp);
00258     }
00259     /* Memorize voltage scaler state before initialization */
00260     comp_voltage_scaler_not_initialized = (READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN) == 0);
00261
00262     /* Set COMP parameters */
00263     /*     Set INMSEL bits according to hcomp->Init.InvertingInput value       */
00264     /*     Set INPSEL bits according to hcomp->Init.NonInvertingInput value    */
00265     /*     Set BLANKING bits according to hcomp->Init.BlankingSrce value       */
00266     /*     Set HYST bits according to hcomp->Init.Hysteresis value             */
00267     /*     Set POLARITY bit according to hcomp->Init.OutputPol value           */
00268     /*     Set POWERMODE bits according to hcomp->Init.Mode value              */
00269
00270     tmp_csr = (hcomp->Init.InvertingInput    |  \
00271               hcomp->Init.NonInvertingInput  |  \
00272               hcomp->Init.BlankingSrce       |  \
00273               hcomp->Init.Hysteresis         |  \
00274               hcomp->Init.OutputPol          |  \
00275               hcomp->Init.Mode                );
00276
00277     /* Set parameters in COMP register */
00278     /* Note: Update all bits except read-only, lock and enable bits */
00279     MODIFY_REG(hcomp->Instance->CFGR,
00280                COMP_CFGRx_PWRMODE  | COMP_CFGRx_INMSEL   | COMP_CFGRx_INPSEL  |
00281                COMP_CFGRx_WINMODE  | COMP_CFGRx_POLARITY | COMP_CFGRx_HYST    |
00282                COMP_CFGRx_BLANKING | COMP_CFGRx_BRGEN    | COMP_CFGRx_SCALEN,
00283                tmp_csr
00284               );
00285
00286     /* Set window mode */
00287     /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP     */
00288     /*       instances. Therefore, this function can update another COMP      */
00289     /*       instance that the one currently selected.                        */
00290     if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)
00291     {
00292       SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE);
00293     }
00294     else
00295     {
00296       CLEAR_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE);
00297     }
00298     /* Delay for COMP scaler bridge voltage stabilization */
00299     /* Apply the delay if voltage scaler bridge is enabled for the first time */
00300     if ((READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN) != 0) &&
00301         (comp_voltage_scaler_not_initialized != 0)               )
00302     {
00303       /* Wait loop initialization and execution */
00304       /* Note: Variable divided by 2 to compensate partially                  */
00305       /*       CPU processing cycles.*/
00306
00307      wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000 * 2)));
00308
00309      while(wait_loop_index != 0)
00310      {
00311        wait_loop_index --;
00312      }
00313     }
00314
00315     /* Get the EXTI line corresponding to the selected COMP instance */
00316     exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
00317
00318     /* Manage EXTI settings */
00319     if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != RESET)
00320     {
00321       /* Configure EXTI rising edge */
00322       if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != RESET)
00323       {
00324         SET_BIT(EXTI->RTSR1, exti_line);
00325       }
00326       else
00327       {
00328         CLEAR_BIT(EXTI->RTSR1, exti_line);
00329       }
00330
00331       /* Configure EXTI falling edge */
00332       if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != RESET)
00333       {
00334         SET_BIT(EXTI->FTSR1, exti_line);
00335       }
00336       else
00337       {
00338         CLEAR_BIT(EXTI->FTSR1, exti_line);
00339       }
00340
00341       /* Clear COMP EXTI pending bit (if any) */
00342       WRITE_REG(EXTI_D1->PR1, exti_line);
00343
00344
00345       /* Configure EXTI event mode */
00346       if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != RESET)
00347       {
00348         SET_BIT(EXTI_D1->EMR1, exti_line);
00349       }
00350       else
00351       {
00352         CLEAR_BIT(EXTI_D1->EMR1, exti_line);
00353       }
00354
00355        /* Configure EXTI interrupt mode */
00356       if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != RESET)
00357       {
00358       SET_BIT(EXTI_D1->IMR1, exti_line);
00359       }
00360       else
00361       {
00362         CLEAR_BIT(EXTI_D1->IMR1, exti_line);
00363       }
00364     }
00365     else
00366     {
00367       /* Disable EXTI event mode */
00368       CLEAR_BIT(EXTI_D1->EMR1, exti_line);
00369
00370       /* Disable EXTI interrupt mode */
00371       CLEAR_BIT(EXTI_D1->IMR1, exti_line);
00372     }
00373     /* Set HAL COMP handle state */
00374     /* Note: Transition from state reset to state ready,                      */
00375     /*       otherwise (coming from state ready or busy) no state update.     */
00376     if (hcomp->State == HAL_COMP_STATE_RESET)
00377     {
00378
00379       hcomp->State = HAL_COMP_STATE_READY;
00380     }
00381
00382   }
00383
00384   return status;
00385 }
00386
00387 /**
00388   * @brief  DeInitialize the COMP peripheral.
00389   * @note   Deinitialization cannot be performed if the COMP configuration is locked.
00390   *         To unlock the configuration, perform a system reset.
00391   * @param  hcomp  COMP handle
00392   * @retval HAL status
00393   */
00394 HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
00395 {
00396   HAL_StatusTypeDef status = HAL_OK;
00397
00398   /* Check the COMP handle allocation and lock status */
00399   if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
00400   {
00401     status = HAL_ERROR;
00402   }
00403   else
00404   {
00405     /* Check the parameter */
00406     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00407
00408     /* Set COMP_CFGR register to reset value */
00409     WRITE_REG(hcomp->Instance->CFGR, 0x00000000);
00410
00411     /* DeInit the low level hardware */
00412     HAL_COMP_MspDeInit(hcomp);
00413
00414     /* Set HAL COMP handle state */
00415     hcomp->State = HAL_COMP_STATE_RESET;
00416
00417     /* Release Lock */
00418     __HAL_UNLOCK(hcomp);
00419   }
00420
00421   return status;
00422 }
00423
00424 /**
00425   * @brief  Initialize the COMP MSP.
00426   * @param  hcomp COMP handle
00427   * @retval None
00428   */
00429 __weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
00430 {
00431   /* Prevent unused argument(s) compilation warning */
00432   UNUSED(hcomp);
00433   /* NOTE : This function should not be modified, when the callback is needed,
00434             the HAL_COMP_MspInit could be implemented in the user file
00435    */
00436 }
00437
00438 /**
00439   * @brief  DeInitialize the COMP MSP.
00440   * @param  hcomp COMP handle
00441   * @retval None
00442   */
00443 __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
00444 {
00445   /* Prevent unused argument(s) compilation warning */
00446    UNUSED(hcomp);
00447   /* NOTE : This function should not be modified, when the callback is needed,
00448             the HAL_COMP_MspDeInit could be implemented in the user file
00449    */
00450 }
00451
00452 /**
00453   * @}
00454   */
00455
00456 /** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions
00457  *  @brief   Start-Stop operation functions.
00458  *
00459 @verbatim
00460  ===============================================================================
00461                       ##### IO operation functions #####
00462  ===============================================================================
00463     [..]  This section provides functions allowing to:
00464       (+) Start a Comparator instance without interrupt.
00465       (+) Stop a Comparator instance without interrupt.
00466       (+) Start a Comparator instance with interrupt generation.
00467       (+) Stop a Comparator instance with interrupt generation.
00468
00469 @endverbatim
00470   * @{
00471   */
00472
00473 /**
00474   * @brief  Start the comparator.
00475   * @param  hcomp COMP handle
00476   * @retval HAL status
00477   */
00478 HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
00479 {
00480   __IO uint32_t wait_loop_index = 0;
00481
00482   HAL_StatusTypeDef status = HAL_OK;
00483
00484   /* Check the COMP handle allocation and lock status */
00485   if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
00486   {
00487     status = HAL_ERROR;
00488   }
00489   else
00490   {
00491     /* Check the parameter */
00492     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00493
00494     if(hcomp->State == HAL_COMP_STATE_READY)
00495     {
00496       /* Enable the selected comparator */
00497       SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN);
00498
00499       /* Set HAL COMP handle state */
00500       hcomp->State = HAL_COMP_STATE_BUSY;
00501
00502      /* Delay for COMP startup time */
00503      /* Wait loop initialization and execution */
00504      /* Note: Variable divided by 2 to compensate partially    */
00505      /*       CPU processing cycles.                           */
00506
00507      wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000 * 2)));
00508      while(wait_loop_index != 0)
00509      {
00510        wait_loop_index--;
00511      }
00512     }
00513     else
00514     {
00515       status = HAL_ERROR;
00516     }
00517   }
00518
00519   return status;
00520 }
00521
00522 /**
00523   * @brief  Stop the comparator.
00524   * @param  hcomp COMP handle
00525   * @retval HAL status
00526   */
00527 HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
00528 {
00529   HAL_StatusTypeDef status = HAL_OK;
00530
00531   /* Check the COMP handle allocation and lock status */
00532   if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
00533   {
00534     status = HAL_ERROR;
00535   }
00536   else
00537   {
00538     /* Check the parameter */
00539     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00540
00541     if((hcomp->State == HAL_COMP_STATE_BUSY)  ||
00542        (hcomp->State == HAL_COMP_STATE_READY)   )
00543     {
00544
00545       /* Disable the selected comparator */
00546       CLEAR_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN);
00547
00548       /* Set HAL COMP handle state */
00549       hcomp->State = HAL_COMP_STATE_READY;
00550     }
00551     else
00552     {
00553       status = HAL_ERROR;
00554     }
00555   }
00556
00557   return status;
00558 }
00559
00560 /**
00561   * @brief  Enable the interrupt and start the comparator.
00562   * @param  hcomp COMP handle
00563   * @retval HAL status
00564   */
00565 HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
00566 {
00567
00568  __IO uint32_t wait_loop_index = 0;
00569  HAL_StatusTypeDef status = HAL_OK;
00570
00571   /* Check the COMP handle allocation and lock status */
00572   if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
00573   {
00574     status = HAL_ERROR;
00575   }
00576   else
00577   {
00578     /* Check the parameter */
00579     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00580     /* Set HAL COMP handle state */
00581     if(hcomp->State == HAL_COMP_STATE_READY)
00582     {
00583
00584     /* Enable the selected comparator */
00585     SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN);
00586     /* Enable the Interrupt comparator */
00587     SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_ITEN);
00588
00589     hcomp->State = HAL_COMP_STATE_BUSY;
00590       /* Delay for COMP startup time */
00591       /* Wait loop initialization and execution */
00592       /* Note: Variable divided by 2 to compensate partially                  */
00593       /*       CPU processing cycles.                                         */
00594
00595      wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000 * 2)));
00596      while(wait_loop_index != 0)
00597      {
00598        wait_loop_index--;
00599      }
00600
00601    }
00602    else
00603    {
00604       status = HAL_ERROR;
00605    }
00606   }
00607
00608   return status;
00609 }
00610
00611 /**
00612   * @brief  Disable the interrupt and Stop the comparator.
00613   * @param  hcomp COMP handle
00614   * @retval HAL status
00615   */
00616 HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp)
00617 {
00618   HAL_StatusTypeDef status = HAL_OK;
00619
00620   /* Disable the EXTI Line interrupt mode */
00621    CLEAR_BIT(EXTI_D1->IMR1, COMP_GET_EXTI_LINE(hcomp->Instance));
00622   /* Disable the Interrupt comparator */
00623    CLEAR_BIT(hcomp->Instance->CFGR, COMP_CFGRx_ITEN);
00624
00625   status = HAL_COMP_Stop(hcomp);
00626
00627   return status;
00628
00629 }
00630
00631 /**
00632   * @brief  Comparator IRQ Handler.
00633   * @param  hcomp COMP handle
00634   * @retval HAL status
00635   */
00636 void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
00637 {
00638   /* Get the EXTI line corresponding to the selected COMP instance */
00639   uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
00640
00641
00642     /* Check COMP EXTI flag */
00643     if(READ_BIT(EXTI_D1->PR1, exti_line) != RESET)
00644     {
00645        /* Check whether comparator is in independent or window mode */
00646         if(READ_BIT(COMP12_COMMON->CFGR, COMP_CFGRx_WINMODE) != RESET)
00647         {
00648           /* Clear COMP EXTI line pending bit of the pair of comparators          */
00649           /* in window mode.                                                      */
00650           /* Note: Pair of comparators in window mode can both trig IRQ when      */
00651           /*       input voltage is changing from "out of window" area            */
00652           /*       (low or high ) to the other "out of window" area (high or low).*/
00653           /*       Both flags must be cleared to call comparator trigger          */
00654           /*       callback is called once.                                       */
00655           WRITE_REG(EXTI_D1->PR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
00656         }
00657         else
00658         {
00659           /* Clear COMP EXTI line pending bit */
00660           WRITE_REG(EXTI_D1->PR1, exti_line);
00661         }
00662
00663       /* COMP trigger user callback */
00664         HAL_COMP_TriggerCallback(hcomp);
00665     }
00666
00667    /* Get COMP interrupt source */
00668   if (__HAL_COMP_GET_IT_SOURCE(hcomp, COMP_IT_EN) != RESET)
00669   {
00670
00671     if((__HAL_COMP_GET_FLAG( COMP_FLAG_C1I)) != RESET)
00672     {
00673       /* Clear the COMP channel 1 interrupt flag */
00674          __HAL_COMP_CLEAR_C1IFLAG();
00675
00676       /* Disable COMP interrupt */
00677        __HAL_COMP_DISABLE_IT(hcomp,COMP_IT_EN);
00678
00679     }
00680     if((__HAL_COMP_GET_FLAG( COMP_FLAG_C2I)) != RESET)
00681     {
00682      /* Clear the COMP channel 2 interrupt flag */
00683        __HAL_COMP_CLEAR_C2IFLAG();
00684
00685      /* Disable COMP interrupt */
00686      __HAL_COMP_DISABLE_IT(hcomp,COMP_IT_EN);
00687
00688     }
00689
00690     /* Change COMP state */
00691     hcomp->State = HAL_COMP_STATE_READY;
00692
00693   /* COMP trigger user callback */
00694     HAL_COMP_TriggerCallback(hcomp);
00695   }
00696
00697
00698 }
00699
00700 /**
00701   * @}
00702   */
00703
00704 /** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
00705  *  @brief   Management functions.
00706  *
00707 @verbatim
00708  ===============================================================================
00709                       ##### Peripheral Control functions #####
00710  ===============================================================================
00711     [..]
00712     This subsection provides a set of functions allowing to control the comparators.
00713
00714 @endverbatim
00715   * @{
00716   */
00717
00718 /**
00719   * @brief  Lock the selected comparator configuration.
00720   * @note   A system reset is required to unlock the comparator configuration.
00721   * @param  hcomp COMP handle
00722   * @retval HAL status
00723   */
00724 HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
00725 {
00726  HAL_StatusTypeDef status = HAL_OK;
00727
00728   /* Check the COMP handle allocation and lock status */
00729   if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
00730   {
00731     status = HAL_ERROR;
00732   }
00733   else
00734   {
00735     /* Check the parameter */
00736     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00737     /* Set HAL COMP handle state */
00738     hcomp->State = ((HAL_COMP_StateTypeDef)(hcomp->State | COMP_STATE_BITFIELD_LOCK));
00739   }
00740
00741   if(status == HAL_OK)
00742   {
00743     /* Set the lock bit corresponding to selected comparator */
00744     __HAL_COMP_LOCK(hcomp);
00745   }
00746
00747   return status;
00748 }
00749
00750 /**
00751   * @brief  Return the output level (high or low) of the selected comparator.
00752   * @note   The output level depends on the selected polarity.
00753   *         If the polarity is not inverted:
00754   *           - Comparator output is low when the input plus is at a lower
00755   *             voltage than the input minus
00756   *           - Comparator output is high when the input plus is at a higher
00757   *             voltage than the input minus
00758   *         If the polarity is inverted:
00759   *           - Comparator output is high when the input plus is at a lower
00760   *             voltage than the input minus
00761   *           - Comparator output is low when the input plus is at a higher
00762   *             voltage than the input minus
00763   * @param  hcomp  COMP handle
00764   * @retval Returns the selected comparator output level:
00765   *         @arg @ref COMP_OUTPUT_LEVEL_LOW
00766   *         @arg @ref COMP_OUTPUT_LEVEL_HIGH
00767   *
00768   */
00769 uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
00770 {
00771   /* Check the parameter */
00772   assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00773
00774   if (hcomp->Instance == COMP1)
00775   {
00776     return (uint32_t)(READ_BIT(COMP12->SR, COMP_SR_C1VAL));
00777   }
00778   else
00779   {
00780     return (uint32_t)((READ_BIT(COMP12->SR, COMP_SR_C2VAL))>> 1);
00781   }
00782 }
00783
00784 /**
00785   * @brief  Comparator callback.
00786   * @param  hcomp COMP handle
00787   * @retval None
00788   */
00789 __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
00790 {
00791    /* Prevent unused argument(s) compilation warning */
00792    UNUSED(hcomp);
00793   /* NOTE : This function should not be modified, when the callback is needed,
00794             the HAL_COMP_TriggerCallback should be implemented in the user file
00795    */
00796 }
00797
00798
00799 /**
00800   * @}
00801   */
00802
00803 /** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions
00804  *  @brief   Peripheral State functions.
00805  *
00806 @verbatim
00807  ===============================================================================
00808                       ##### Peripheral State functions #####
00809  ===============================================================================
00810     [..]
00811     This subsection permit to get in run-time the status of the peripheral.
00812
00813 @endverbatim
00814   * @{
00815   */
00816
00817 /**
00818   * @brief  Return the COMP handle state.
00819   * @param  hcomp  COMP handle
00820   * @retval HAL state
00821   */
00822 HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
00823 {
00824   /* Check the COMP handle allocation */
00825   if(hcomp == NULL)
00826   {
00827     return HAL_COMP_STATE_RESET;
00828   }
00829
00830   /* Check the parameter */
00831   assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00832
00833   /* Return HAL COMP handle state */
00834   return hcomp->State;
00835 }
00836 /**
00837   * @}
00838   */
00839
00840 /**
00841   * @}
00842   */
00843
00844 #endif /* HAL_COMP_MODULE_ENABLED */
00845 /**
00846   * @}
00847   */
00848
00849 /**
00850   * @}
00851   */
00852
00853 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_comp.h Source File

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stm32h7xx_hal_comp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_comp.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of COMP HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_COMP_H
00040 #define __STM32H7xx_HAL_COMP_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup COMP
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup COMP_Exported_Types COMP Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  COMP Init structure definition
00064   */
00065 typedef struct
00066 {
00067
00068   uint32_t WindowMode;         /*!< Set window mode of a pair of comparators instances
00069                                     (2 consecutive instances odd and even COMP<x> and COMP<x+1>).
00070                                     Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode.
00071                                     This parameter can be a value of @ref COMP_WindowMode */
00072
00073   uint32_t Mode;               /*!< Set comparator operating mode to adjust power and speed.
00074                                     Note: For the characteritics of comparator power modes
00075                                           (propagation delay and power consumption), refer to device datasheet.
00076                                     This parameter can be a value of @ref COMP_PowerMode */
00077
00078   uint32_t NonInvertingInput;  /*!< Set comparator input plus (non-inverting input).
00079                                     This parameter can be a value of @ref COMP_InputPlus */
00080
00081   uint32_t InvertingInput;     /*!< Set comparator input minus (inverting input).
00082                                     This parameter can be a value of @ref COMP_InputMinus */
00083
00084   uint32_t Hysteresis;         /*!< Set comparator hysteresis mode of the input minus.
00085                                     This parameter can be a value of @ref COMP_Hysteresis */
00086
00087   uint32_t OutputPol;          /*!< Set comparator output polarity.
00088                                     This parameter can be a value of @ref COMP_OutputPolarity */
00089
00090   uint32_t BlankingSrce;       /*!< Set comparator blanking source.
00091                                     This parameter can be a value of @ref COMP_BlankingSrce */
00092
00093   uint32_t TriggerMode;        /*!< Set the comparator output triggering External Interrupt Line (EXTI).
00094                                     This parameter can be a value of @ref COMP_EXTI_TriggerMode */
00095
00096 }COMP_InitTypeDef;
00097
00098 /**
00099   * @brief  HAL COMP state machine: HAL COMP states definition
00100   */
00101 #define COMP_STATE_BITFIELD_LOCK  ((uint32_t)0x10)
00102 typedef enum
00103 {
00104   HAL_COMP_STATE_RESET             = 0x00,                                              /*!< COMP not yet initialized                             */
00105   HAL_COMP_STATE_RESET_LOCKED      = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
00106   HAL_COMP_STATE_READY             = 0x01,                                              /*!< COMP initialized and ready for use                   */
00107   HAL_COMP_STATE_READY_LOCKED      = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked         */
00108   HAL_COMP_STATE_BUSY              = 0x02,                                              /*!< COMP is running                                      */
00109   HAL_COMP_STATE_BUSY_LOCKED       = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)   /*!< COMP is running and configuration is locked          */
00110 }HAL_COMP_StateTypeDef;
00111
00112 /**
00113   * @brief  COMP Handle Structure definition
00114   */
00115 typedef struct
00116 {
00117   COMP_TypeDef       *Instance;       /*!< Register base address    */
00118   COMP_InitTypeDef   Init;            /*!< COMP required parameters */
00119   HAL_LockTypeDef    Lock;            /*!< Locking object           */
00120   __IO HAL_COMP_StateTypeDef  State;  /*!< COMP communication state */
00121
00122 } COMP_HandleTypeDef;
00123
00124 /**
00125   * @}
00126   */
00127
00128 /* Exported constants --------------------------------------------------------*/
00129 /** @defgroup COMP_Exported_Constants COMP Exported Constants
00130   * @{
00131   */
00132 /** @defgroup COMP_WindowMode COMP Window Mode
00133   * @{
00134   */
00135 #define COMP_WINDOWMODE_DISABLE                 ((uint32_t)0x00000000)   /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */
00136 #define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CFGRx_WINMODE)     /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
00137
00138 /**
00139   * @}
00140   */
00141
00142 /** @defgroup COMP_PowerMode COMP power mode
00143   * @{
00144   */
00145 /* Note: For the characteritics of comparator power modes                     */
00146 /*       (propagation delay and power consumption),                           */
00147 /*       refer to device datasheet.                                           */
00148 #define COMP_POWERMODE_HIGHSPEED       ((uint32_t)0x00000000)   /*!< High Speed */
00149 #define COMP_POWERMODE_MEDIUMSPEED     (COMP_CFGRx_PWRMODE_0)   /*!< Medium Speed */
00150 #define COMP_POWERMODE_ULTRALOWPOWER   (COMP_CFGRx_PWRMODE)     /*!< Ultra-low power mode */
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
00156   * @{
00157   */
00158 #define COMP_INPUT_PLUS_IO1            ((uint32_t)0x00000000) /*!< Comparator input plus connected to IO1 (pin PB0 for COMP1, pin PE9 for COMP2) */
00159 #define COMP_INPUT_PLUS_IO2            (COMP_CFGRx_INPSEL)    /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PE11 for COMP2) */
00160 /**
00161   * @}
00162   */
00163
00164 /** @defgroup COMP_InputMinus COMP input minus (inverting input)
00165   * @{
00166   */
00167 #define COMP_INPUT_MINUS_1_4VREFINT     (                                                                  COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)        /*!< Comparator input minus connected to 1/4 VrefInt */
00168 #define COMP_INPUT_MINUS_1_2VREFINT     (                                            COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)        /*!< Comparator input minus connected to 1/2 VrefInt */
00169 #define COMP_INPUT_MINUS_3_4VREFINT     (                      COMP_CFGRx_INMSEL_1                       | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)        /*!< Comparator input minus connected to 3/4 VrefInt */
00170 #define COMP_INPUT_MINUS_VREFINT        (                      COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN                 )          /*!< Comparator input minus connected to VrefInt */
00171 #define COMP_INPUT_MINUS_DAC1_CH1       (COMP_CFGRx_INMSEL_2                                            )                                               /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
00172 #define COMP_INPUT_MINUS_DAC1_CH2       (COMP_CFGRx_INMSEL_2                       | COMP_CFGRx_INMSEL_0)                                               /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
00173 #define COMP_INPUT_MINUS_IO1            (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1                      )                                               /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PE10 for COMP2) */
00174 #define COMP_INPUT_MINUS_IO2            (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0)                                               /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PE7 for COMP2) */
00175 /**
00176   * @}
00177   */
00178
00179 /** @defgroup COMP_Hysteresis COMP hysteresis
00180   * @{
00181   */
00182 #define COMP_HYSTERESIS_NONE           ((uint32_t)0x00000000)   /*!< No hysteresis */
00183 #define COMP_HYSTERESIS_LOW            (COMP_CFGRx_HYST_0)      /*!< Hysteresis level low */
00184 #define COMP_HYSTERESIS_MEDIUM         (COMP_CFGRx_HYST_1)      /*!< Hysteresis level medium */
00185 #define COMP_HYSTERESIS_HIGH           (COMP_CFGRx_HYST)        /*!< Hysteresis level high */
00186 /**
00187   * @}
00188   */
00189
00190 /** @defgroup COMP_OutputPolarity COMP Output Polarity
00191   * @{
00192   */
00193 #define COMP_OUTPUTPOL_NONINVERTED     ((uint32_t)0x00000000)  /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
00194 #define COMP_OUTPUTPOL_INVERTED        (COMP_CFGRx_POLARITY)     /*!< COMP output level is inverted     (comparator output is low  when the input plus is at a higher voltage than the input minus) */
00195 /**
00196   * @}
00197   */
00198
00199
00200 /** @defgroup COMP_BlankingSrce  COMP Blanking Source
00201   * @{
00202   */
00203 /* Any blanking source can be selected for all comparators */
00204 #define COMP_BLANKINGSRC_NONE             ((uint32_t)0x00000000)                           /*!< No blanking source */
00205 #define COMP_BLANKINGSRC_TIM1_OC5         (COMP_CFGRx_BLANKING_0)                          /*!< TIM1 OC5 selected as blanking source for comparator */
00206 #define COMP_BLANKINGSRC_TIM2_OC3         (COMP_CFGRx_BLANKING_1)                          /*!< TIM2 OC3 selected as blanking source for comparator */
00207 #define COMP_BLANKINGSRC_TIM3_OC3         (COMP_CFGRx_BLANKING_0 |COMP_CFGRx_BLANKING_1)   /*!< TIM3 OC3 selected as blanking source for compartor */
00208 #define COMP_BLANKINGSRC_TIM3_OC4         (COMP_CFGRx_BLANKING_2)                          /*!< TIM3 OC4 selected as blanking source for comparator */
00209 #define COMP_BLANKINGSRC_TIM8_OC5         (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_0)    /*!< TIM8 OC5 selected as blanking source for comparator */
00210 #define COMP_BLANKINGSRC_TIM15_OC1        (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_1)    /*!< TIM15 OC1 selected as blanking source for comparator */
00211 /**
00212   * @}
00213   */
00214
00215
00216
00217
00218 /** @defgroup COMP_OutputLevel COMP Output Level
00219   * @{
00220   */
00221
00222 /* Note: Comparator output level values are fixed to "0" and "1",             */
00223 /* corresponding COMP register bit is managed by HAL function to match        */
00224 /* with these values (independently of bit position in register).             */
00225
00226 /* When output polarity is not inverted, comparator output is low when
00227    the input plus is at a lower voltage than the input minus */
00228 #define COMP_OUTPUT_LEVEL_LOW              ((uint32_t)0x00000000)
00229 /* When output polarity is not inverted, comparator output is high when
00230    the input plus is at a higher voltage than the input minus */
00231 #define COMP_OUTPUT_LEVEL_HIGH             ((uint32_t)0x00000001)
00232
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
00238   * @{
00239   */
00240 #define COMP_TRIGGERMODE_NONE                 ((uint32_t)0x00000000)                                    /*!< Comparator output triggering no External Interrupt Line */
00241 #define COMP_TRIGGERMODE_IT_RISING            (COMP_EXTI_IT | COMP_EXTI_RISING)                         /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
00242 #define COMP_TRIGGERMODE_IT_FALLING           (COMP_EXTI_IT | COMP_EXTI_FALLING)                        /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
00243 #define COMP_TRIGGERMODE_IT_RISING_FALLING    (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)     /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
00244 #define COMP_TRIGGERMODE_EVENT_RISING         (COMP_EXTI_EVENT | COMP_EXTI_RISING)                      /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
00245 #define COMP_TRIGGERMODE_EVENT_FALLING        (COMP_EXTI_EVENT | COMP_EXTI_FALLING)                     /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
00246 #define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)  /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
00247
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup COMP_Flag COMP Flag
00253   * @{
00254   */
00255 #define COMP_FLAG_C1I           COMP_SR_C1IF           /*!< Comparator 1 Interrupt Flag */
00256 #define COMP_FLAG_C2I           COMP_SR_C2IF           /*!< Comparator 2 Interrupt Flag */
00257 #define COMP_FLAG_LOCK          COMP_CFGRx_LOCK        /*!< Lock flag */
00258 /**
00259   * @}
00260   */
00261 /** @defgroup COMP_IT_CLEAR_Flags  COMP Interruption Clear Flags
00262   * @{
00263   */
00264 #define COMP_CLEAR_C1IF          COMP_ICFR_C1IF     /*!< Clear Comparator 1 Interrupt Flag */
00265 #define COMP_CLEAR_C2IF          COMP_ICFR_C2IF     /*!< Clear Comparator 2 Interrupt Flag */
00266 /**
00267   * @}
00268   */
00269 /** @defgroup COMP_Interrupts_Definitions COMP Interrupts Definitions
00270   * @{
00271   */
00272 #define COMP_IT_EN               COMP_CFGRx_ITEN
00273
00274 /**
00275   * @}
00276   */
00277
00278
00279 /**
00280   * @}
00281   */
00282
00283 /* Exported macros -----------------------------------------------------------*/
00284 /** @defgroup COMP_Exported_Macros COMP Exported Macros
00285   * @{
00286   */
00287 /** @defgroup COMP_Handle_Management  COMP Handle Management
00288  * @{
00289   */
00290
00291 /** @brief  Reset COMP handle state.
00292   * @param  __HANDLE__ COMP handle
00293   * @retval None
00294   */
00295 #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
00296
00297 /**
00298   * @brief  Enable the specified comparator.
00299   * @param  __HANDLE__ COMP handle
00300   * @retval None
00301   */
00302 #define __HAL_COMP_ENABLE(__HANDLE__)                 SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)
00303
00304 /**
00305   * @brief  Disable the specified comparator.
00306   * @param  __HANDLE__ COMP handle
00307   * @retval None
00308   */
00309 #define __HAL_COMP_DISABLE(__HANDLE__)                CLEAR_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)
00310
00311 /**
00312   * @brief  Lock the specified comparator configuration.
00313   * @note   Using this macro induce HAL COMP handle state machine being no
00314   *         more in line with COMP instance state.
00315   *         To keep HAL COMP handle state machine updated, it is recommended
00316   *         to use function "HAL_COMP_Lock')".
00317   * @param  __HANDLE__ COMP handle
00318   * @retval None
00319   */
00320 #define __HAL_COMP_LOCK(__HANDLE__)                   SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK)
00321
00322 /**
00323   * @brief  Check whether the specified comparator is locked.
00324   * @param  __HANDLE__  COMP handle
00325   * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
00326   */
00327 #define __HAL_COMP_IS_LOCKED(__HANDLE__)           (READ_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK) == COMP_CFGRx_LOCK)
00328
00329 /**
00330   * @}
00331   */
00332
00333 /** @defgroup COMP_Exti_Management  COMP external interrupt line management
00334   * @{
00335   */
00336
00337 /**
00338   * @brief  Enable the COMP1 EXTI line rising edge trigger.
00339   * @retval None
00340   */
00341 #define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
00342
00343
00344 /**
00345   * @brief  Disable the COMP1 EXTI line rising edge trigger.
00346   * @retval None
00347   */
00348 #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE()    CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
00349
00350 /**
00351   * @brief  Enable the COMP1 EXTI line falling edge trigger.
00352   * @retval None
00353   */
00354 #define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE()    SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
00355
00356 /**
00357   * @brief  Disable the COMP1 EXTI line falling edge trigger.
00358   * @retval None
00359   */
00360 #define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE()    CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
00361
00362
00363 /**
00364   * @brief  Enable the COMP1 EXTI line rising & falling edge trigger.
00365   * @retval None
00366   */
00367 #define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
00368                                                                __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
00369                                                                __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
00370                                                              } while(0)
00371
00372
00373 /**
00374   * @brief  Disable the COMP1 EXTI line rising & falling edge trigger.
00375   * @retval None
00376   */
00377 #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
00378                                                                __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
00379                                                                __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
00380                                                              } while(0)
00381
00382
00383 /**
00384   * @brief  Enable the COMP1 EXTI line in interrupt mode.
00385   * @retval None
00386   */
00387 #define __HAL_COMP_COMP1_EXTI_ENABLE_IT()             SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)
00388
00389 /**
00390   * @brief  Disable the COMP1 EXTI line in interrupt mode.
00391   * @retval None
00392   */
00393 #define __HAL_COMP_COMP1_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)
00394
00395 /**
00396   * @brief  Enable the COMP1 EXTI Line in event mode.
00397   * @retval None
00398   */
00399 #define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT()           SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)
00400
00401 /**
00402   * @brief  Disable the COMP1 EXTI Line in event mode.
00403   * @retval None
00404   */
00405 #define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT()          CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)
00406
00407 /**
00408   * @brief  Check whether the COMP1 EXTI line flag is set or not.
00409   * @retval RESET or SET
00410   */
00411 #define __HAL_COMP_COMP1_EXTI_GET_FLAG()              READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)
00412 /**
00413   * @brief  Clear the COMP1 EXTI flag.
00414   * @retval None
00415   */
00416 #define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)
00417
00418 /**
00419   * @brief  Generate a software interrupt on the COMP1 EXTI line.
00420   * @retval None
00421   */
00422 #define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1)
00423
00424 /**
00425   * @brief  Enable the COMP1 D3 EXTI Line in event mode.
00426   * @retval None
00427   */
00428 #define __HAL_COMP_COMP1_EXTID3_ENABLE_EVENT()        SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)
00429
00430 /**
00431   * @brief  Disable the COMP1 D3 EXTI Line in event mode.
00432   * @retval None
00433   */
00434 #define __HAL_COMP_COMP1_EXTID3_DISABLE_EVENT()        CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)
00435
00436
00437 /**
00438   * @brief  Enable the COMP2 EXTI line rising edge trigger.
00439   * @retval None
00440   */
00441 #define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
00442
00443 /**
00444   * @brief  Disable the COMP2 EXTI line rising edge trigger.
00445   * @retval None
00446   */
00447 #define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
00448
00449 /**
00450   * @brief  Enable the COMP2 EXTI line falling edge trigger.
00451   * @retval None
00452   */
00453 #define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
00454
00455 /**
00456   * @brief  Disable the COMP2 EXTI line falling edge trigger.
00457   * @retval None
00458   */
00459 #define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
00460
00461 /**
00462   * @brief  Enable the COMP2 EXTI line rising & falling edge trigger.
00463   * @retval None
00464   */
00465 #define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
00466                                                                __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
00467                                                                __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
00468                                                              } while(0)
00469
00470 /**
00471   * @brief  Disable the COMP2 EXTI line rising & falling edge trigger.
00472   * @retval None
00473   */
00474 #define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()   do { \
00475                                                                __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
00476                                                                __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
00477                                                              } while(0)
00478 /**
00479   * @brief  Enable the COMP2 EXTI line.
00480   * @retval None
00481   */
00482 #define __HAL_COMP_COMP2_EXTI_ENABLE_IT()             SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)
00483
00484 /**
00485   * @brief  Disable the COMP2 EXTI line.
00486   * @retval None
00487   */
00488 #define __HAL_COMP_COMP2_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)
00489
00490 /**
00491   * @brief  Enable the COMP2 EXTI Line in event mode.
00492   * @retval None
00493   */
00494 #define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT()          SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)
00495
00496 /**
00497   * @brief  Disable the COMP2 EXTI Line in event mode.
00498   * @retval None
00499   */
00500 #define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT()          CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)
00501
00502 /**
00503   * @brief  Check whether the COMP2 EXTI line flag is set or not.
00504   * @retval RESET or SET
00505   */
00506 #define __HAL_COMP_COMP2_EXTI_GET_FLAG()              READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)
00507
00508 /**
00509   * @brief  Clear the the COMP2 EXTI flag.
00510   * @retval None
00511   */
00512 #define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)
00513
00514 /**
00515   * @brief  Enable the COMP2 D3 EXTI Line in event mode.
00516   * @retval None
00517   */
00518 #define __HAL_COMP_COMP2_EXTID3_ENABLE_EVENT()        SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)
00519
00520 /**
00521   * @brief  Disable the COMP2 D3 EXTI Line in event mode.
00522   * @retval None
00523   */
00524 #define __HAL_COMP_COMP2_EXTID3_DISABLE_EVENT()       CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)
00525
00526 /**
00527   * @brief  Generate a software interrupt on the COMP2 EXTI line.
00528   * @retval None
00529   */
00530 #define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2)
00531
00532 /** @brief  Checks if the specified COMP interrupt source is enabled or disabled.
00533   * @param  __HANDLE__: specifies the COMP Handle.
00534   *         This parameter can be COMP1 where x: 1 or 2 to select the COMP peripheral.
00535   * @param  __INTERRUPT__: specifies the COMP interrupt source to check.
00536   *          This parameter can be one of the following values:
00537   *            @arg COMP_IT_EN: Comparator interrupt enable
00538   *
00539   * @retval The new state of __IT__ (TRUE or FALSE)
00540   */
00541 #define __HAL_COMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CFGR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00542
00543 /** @brief  Checks whether the specified COMP flag is set or not.
00544   * @param  __FLAG__: specifies the flag to check.
00545   *        This parameter can be one of the following values:
00546   *            @arg COMP_FLAG_C1I:  Comparator 1 Interrupt Flag
00547   *            @arg COMP_FLAG_C2I:  Comparator 2 Interrupt Flag
00548   *            @retval The new state of __FLAG__ (TRUE or FALSE)
00549   */
00550 #define __HAL_COMP_GET_FLAG(__FLAG__)     ((COMP12->SR & (__FLAG__)) == (__FLAG__))
00551
00552 /** @brief  Clears the specified COMP pending flag.
00553   * @param  __FLAG__: specifies the flag to check.
00554   *          This parameter can be any combination of the following values:
00555   *            @arg COMP_CLEAR_C1IF  : Clear Comparator 1 Interrupt Flag
00556   *            @arg COMP_CLEAR_C2IF  : Clear Comparator 2 Interrupt Flag
00557   * @retval None
00558   */
00559 #define __HAL_COMP_CLEAR_FLAG(__FLAG__)   (COMP12->ICFR = (__FLAG__))
00560
00561 /** @brief  Clear the COMP C1I  flag.
00562   * @retval None
00563   */
00564 #define __HAL_COMP_CLEAR_C1IFLAG()   __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C1IF)
00565
00566 /** @brief  Clear the COMP C2I  flag.
00567   * @retval None
00568   */
00569 #define __HAL_COMP_CLEAR_C2IFLAG()   __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C2IF)
00570
00571 /** @brief  Enable the specified COMP interrupt.
00572   * @param  __HANDLE__: specifies the COMP Handle.
00573   * @param  __INTERRUPT__: specifies the COMP interrupt source to enable.
00574   *          This parameter can be one of the following values:
00575   *            @arg COMP_CFGRx_ITEN :  Comparator  interrupt
00576   * @retval None
00577   */
00578 #define __HAL_COMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ( ((__HANDLE__)->Instance->CFGR) |= (__INTERRUPT__) )
00579
00580 /** @brief  Disable the specified COMP interrupt.
00581   * @param  __HANDLE__: specifies the COMP Handle.
00582   * @param  __INTERRUPT__: specifies the COMP interrupt source to enable.
00583   *          This parameter can be one of the following values:
00584   *            @arg COMP_CFGRx_ITEN :  Comparator  interrupt
00585   * @retval None
00586   */
00587 #define __HAL_COMP_DISABLE_IT(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->CFGR) &= ~(__INTERRUPT__))
00588
00589 /**
00590   * @}
00591   */
00592 /** @brief  Enable the specified bit in the Option register.
00593   * @param  __AF__: specifies the Alternate Function source selection .
00594   *          This parameter can be one of the following values:
00595   *            @arg COMP_OR_AFOPA6  :  Alternate Function PA6 source selection
00596   *            @arg COMP_OR_AFOPA8  :  Alternate Function PA8 source selection
00597   *            @arg COMP_OR_AFOPB12 :  Alternate Function PB12 source selection
00598   *            @arg COMP_OR_AFOPE6  :  Alternate Function PE6 source selection
00599   *            @arg COMP_OR_AFOPE15 :  Alternate Function PE15 source selection
00600   *            @arg COMP_OR_AFOPG2  :  Alternate Function PG2 source selection
00601   *            @arg COMP_OR_AFOPG3  :  Alternate Function PG3 source selection
00602   *            @arg COMP_OR_AFOPG4  :  Alternate Function PG4 source selection
00603   *            @arg COMP_OR_AFOPI1  :  Alternate Function PI1 source selection
00604   *            @arg COMP_OR_AFOPI4  :  Alternate Function PI4 source selection
00605   *            @arg COMP_OR_AFOPK2  :  Alternate Function PK2 source selection
00606   * @retval None
00607   */
00608 #define __HAL_COMP_ENABLE_OR(__AF__) SET_BIT(COMP12->OR, (__AF__))
00609
00610 /** @brief  Disable the specified bit in the Option register.
00611   * @param  __AF__: specifies the Alternate Function source selection .
00612   *          This parameter can be one of the following values:
00613   *            @arg COMP_OR_AFOPA6  :  Alternate Function PA6 source selection
00614   *            @arg COMP_OR_AFOPA8  :  Alternate Function PA8 source selection
00615   *            @arg COMP_OR_AFOPB12 :  Alternate Function PB12 source selection
00616   *            @arg COMP_OR_AFOPE6  :  Alternate Function PE6 source selection
00617   *            @arg COMP_OR_AFOPE15 :  Alternate Function PE15 source selection
00618   *            @arg COMP_OR_AFOPG2  :  Alternate Function PG2 source selection
00619   *            @arg COMP_OR_AFOPG3  :  Alternate Function PG3 source selection
00620   *            @arg COMP_OR_AFOPG4  :  Alternate Function PG4 source selection
00621   *            @arg COMP_OR_AFOPI1  :  Alternate Function PI1 source selection
00622   *            @arg COMP_OR_AFOPI4  :  Alternate Function PI4 source selection
00623   *            @arg COMP_OR_AFOPK2  :  Alternate Function PK2 source selection
00624   * @retval None
00625   */
00626 #define __HAL_COMP_DISABLE_OR(__AF__) CLEAR_BIT(COMP12->OR, (__AF__))
00627 /**
00628   * @}
00629   */
00630
00631 /* Private types -------------------------------------------------------------*/
00632 /* Private constants ---------------------------------------------------------*/
00633 /** @defgroup COMP_Private_Constants COMP Private Constants
00634   * @{
00635   */
00636 /** @defgroup COMP_ExtiLine COMP EXTI Lines
00637   * @{
00638   */
00639 #define COMP_EXTI_LINE_COMP1           (EXTI_IMR1_IM20)  /*!< EXTI line 20 connected to COMP1 output */
00640 #define COMP_EXTI_LINE_COMP2           (EXTI_IMR1_IM21)  /*!< EXTI line 21 connected to COMP2 output */
00641 /**
00642   * @}
00643   */
00644 /** @defgroup COMP_ExtiLine COMP EXTI Lines
00645   * @{
00646   */
00647 #define COMP_EXTI_IT                        ((uint32_t) 0x01)  /*!< EXTI line event with interruption */
00648 #define COMP_EXTI_EVENT                     ((uint32_t) 0x02)  /*!< EXTI line event only (without interruption) */
00649 #define COMP_EXTI_RISING                    ((uint32_t) 0x10)  /*!< EXTI line event on rising edge */
00650 #define COMP_EXTI_FALLING                   ((uint32_t) 0x20)  /*!< EXTI line event on falling edge */
00651 /**
00652   * @}
00653   */
00654 /**
00655   * @}
00656   */
00657
00658 /* Private macros ------------------------------------------------------------*/
00659 /** @defgroup COMP_Private_Macros COMP Private Macros
00660   * @{
00661   */
00662 /** @defgroup COMP_GET_EXTI_LINE COMP Private macros to get EXTI line associated with Comparators
00663   * @{
00664   */
00665 /**
00666   * @brief  Get the specified EXTI line for a comparator instance.
00667   * @param  __INSTANCE__: specifies the COMP instance.
00668   * @retval value of @ref COMP_ExtiLine
00669   */
00670 #define COMP_GET_EXTI_LINE(__INSTANCE__)             (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
00671                                                       COMP_EXTI_LINE_COMP2)
00672 /**
00673   * @}
00674   */
00675 /** @defgroup COMP_IS_COMP_Definitions COMP private macros to check input parameters
00676   * @{
00677   */
00678 #define IS_COMP_WINDOWMODE(__WINDOWMODE__)  (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE)                || \
00679                                              ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)  )
00680
00681 #define IS_COMP_POWERMODE(__POWERMODE__)    (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED)    || \
00682                                              ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED)  || \
00683                                              ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER)  )
00684
00685
00686 #define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
00687                                                                ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2))
00688
00689
00690
00691 #define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
00692                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
00693                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
00694                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
00695                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)    || \
00696                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)    || \
00697                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
00698                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2))
00699
00700
00701 #define IS_COMP_HYSTERESIS(__HYSTERESIS__)  (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE)   || \
00702                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW)    || \
00703                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
00704                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))
00705
00706 #define IS_COMP_OUTPUTPOL(__POL__)          (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
00707                                              ((__POL__) == COMP_OUTPUTPOL_INVERTED))
00708
00709 #define IS_COMP_BLANKINGSRCE(__SOURCE__)    (((__SOURCE__) == COMP_BLANKINGSRC_NONE)            || \
00710                                              ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5)  || \
00711                                              ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3)  || \
00712                                              ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3)  || \
00713                                              ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4)  || \
00714                                              ((__SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5)  || \
00715                                              ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1))
00716
00717
00718 #define IS_COMP_TRIGGERMODE(__MODE__)       (((__MODE__) == COMP_TRIGGERMODE_NONE)                 || \
00719                                              ((__MODE__) == COMP_TRIGGERMODE_IT_RISING)            || \
00720                                              ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \
00721                                              ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \
00722                                              ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \
00723                                              ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \
00724                                              ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
00725
00726 #define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW)     || \
00727                                                 ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
00728
00729 /**
00730   * @}
00731   */
00732
00733 /**
00734   * @}
00735   */
00736
00737 /* Exported functions --------------------------------------------------------*/
00738 /** @addtogroup COMP_Exported_Functions
00739   * @{
00740   */
00741
00742 /** @addtogroup COMP_Exported_Functions_Group1
00743   * @{
00744   */
00745 /* Initialization and de-initialization functions  **********************************/
00746 HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
00747 HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
00748 void              HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
00749 void              HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
00750 /**
00751   * @}
00752   */
00753
00754 /* IO operation functions  *****************************************************/
00755 /** @addtogroup COMP_Exported_Functions_Group2
00756   * @{
00757   */
00758 HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
00759 HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
00760 HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp);
00761 HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp);
00762 void              HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
00763
00764 /**
00765   * @}
00766   */
00767
00768 /* Peripheral Control functions  ************************************************/
00769 /** @addtogroup COMP_Exported_Functions_Group3
00770   * @{
00771   */
00772 HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
00773 uint32_t          HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
00774 /* Callback in Interrupt mode */
00775 void              HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
00776 /**
00777   * @}
00778   */
00779
00780 /* Peripheral State functions  **************************************************/
00781 /** @addtogroup COMP_Exported_Functions_Group4
00782   * @{
00783   */
00784 HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
00785 /**
00786   * @}
00787   */
00788
00789 /**
00790   * @}
00791   */
00792
00793 /**
00794   * @}
00795   */
00796
00797 /**
00798   * @}
00799   */
00800
00801 #ifdef __cplusplus
00802 }
00803 #endif
00804
00805 #endif /* __STM32H7xx_HAL_COMP_H */
00806
00807 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_conf.h Source File

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stm32h7xx_hal_conf.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_conf_template.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   HAL configuration template file.
00008   *          This file should be copied to the application folder and renamed
00009   *          to stm32h7xx_hal_conf.h.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00014   *
00015   * Redistribution and use in source and binary forms, with or without modification,
00016   * are permitted provided that the following conditions are met:
00017   *   1. Redistributions of source code must retain the above copyright notice,
00018   *      this list of conditions and the following disclaimer.
00019   *   2. Redistributions in binary form must reproduce the above copyright notice,
00020   *      this list of conditions and the following disclaimer in the documentation
00021   *      and/or other materials provided with the distribution.
00022   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00023   *      may be used to endorse or promote products derived from this software
00024   *      without specific prior written permission.
00025   *
00026   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00027   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00028   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00029   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00030   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00031   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00032   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00033   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00034   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00035   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00036   *
00037   ******************************************************************************
00038   */
00039
00040 /* Define to prevent recursive inclusion -------------------------------------*/
00041 #ifndef __STM32H7xx_HAL_CONF_H
00042 #define __STM32H7xx_HAL_CONF_H
00043
00044 #ifdef __cplusplus
00045  extern "C" {
00046 #endif
00047
00048 /* Exported types ------------------------------------------------------------*/
00049 /* Exported constants --------------------------------------------------------*/
00050
00051 /* ########################## Module Selection ############################## */
00052 /**
00053   * @brief This is the list of modules to be used in the HAL driver
00054   */
00055 #define HAL_MODULE_ENABLED
00056 #define HAL_ADC_MODULE_ENABLED
00057 #define HAL_CEC_MODULE_ENABLED
00058 #define HAL_COMP_MODULE_ENABLED
00059 #define HAL_CORTEX_MODULE_ENABLED
00060 #define HAL_CRC_MODULE_ENABLED
00061 #define HAL_CRYP_MODULE_ENABLED
00062 #define HAL_DAC_MODULE_ENABLED
00063 #define HAL_DCMI_MODULE_ENABLED
00064 #define HAL_DFSDM_MODULE_ENABLED
00065 #define HAL_DMA_MODULE_ENABLED
00066 #define HAL_DMA2D_MODULE_ENABLED
00067 #define HAL_ETH_MODULE_ENABLED
00068 #define HAL_FDCAN_MODULE_ENABLED
00069 #define HAL_FLASH_MODULE_ENABLED
00070 #define HAL_GPIO_MODULE_ENABLED
00071 #define HAL_HASH_MODULE_ENABLED
00072 #define HAL_HCD_MODULE_ENABLED
00073 #define HAL_HRTIM_MODULE_ENABLED
00074 #define HAL_HSEM_MODULE_ENABLED
00075 #define HAL_I2C_MODULE_ENABLED
00076 #define HAL_I2S_MODULE_ENABLED
00077 #define HAL_IRDA_MODULE_ENABLED
00078 #define HAL_IWDG_MODULE_ENABLED
00079 #define HAL_JPEG_MODULE_ENABLED
00080 #define HAL_LPTIM_MODULE_ENABLED
00081 #define HAL_LTDC_MODULE_ENABLED
00082 #define HAL_MDIOS_MODULE_ENABLED
00083 #define HAL_MDMA_MODULE_ENABLED
00084 #define HAL_MMC_MODULE_ENABLED
00085 #define HAL_NAND_MODULE_ENABLED
00086 #define HAL_NOR_MODULE_ENABLED
00087 #define HAL_OPAMP_MODULE_ENABLED
00088 #define HAL_PCD_MODULE_ENABLED
00089 #define HAL_PWR_MODULE_ENABLED
00090 #define HAL_QSPI_MODULE_ENABLED
00091 #define HAL_RCC_MODULE_ENABLED
00092 #define HAL_RNG_MODULE_ENABLED
00093 #define HAL_RTC_MODULE_ENABLED
00094 #define HAL_SAI_MODULE_ENABLED
00095 #define HAL_SD_MODULE_ENABLED
00096 #define HAL_SDRAM_MODULE_ENABLED
00097 #define HAL_SMARTCARD_MODULE_ENABLED
00098 #define HAL_SMBUS_MODULE_ENABLED
00099 #define HAL_SPDIFRX_MODULE_ENABLED
00100 #define HAL_SPI_MODULE_ENABLED
00101 #define HAL_SRAM_MODULE_ENABLED
00102 #define HAL_SWPMI_MODULE_ENABLED
00103 #define HAL_TIM_MODULE_ENABLED
00104 #define HAL_UART_MODULE_ENABLED
00105 #define HAL_USART_MODULE_ENABLED
00106 #define HAL_WWDG_MODULE_ENABLED
00107
00108 /* ########################## Oscillator Values adaptation ####################*/
00109 /**
00110   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
00111   *        This value is used by the RCC HAL module to compute the system frequency
00112   *        (when HSE is used as system clock source, directly or through the PLL).
00113   */
00114 #if !defined  (HSE_VALUE)
00115 #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
00116 #endif /* HSE_VALUE */
00117
00118 #if !defined  (HSE_STARTUP_TIMEOUT)
00119   #define HSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for HSE start up, in ms */
00120 #endif /* HSE_STARTUP_TIMEOUT */
00121
00122 /**
00123   * @brief Internal  oscillator (CSI) default value.
00124   *        This value is the default CSI value after Reset.
00125   */
00126 #if !defined  (CSI_VALUE)
00127   #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
00128 #endif /* CSI_VALUE */
00129
00130 /**
00131   * @brief Internal High Speed oscillator (HSI) value.
00132   *        This value is used by the RCC HAL module to compute the system frequency
00133   *        (when HSI is used as system clock source, directly or through the PLL).
00134   */
00135 #if !defined  (HSI_VALUE)
00136   #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
00137 #endif /* HSI_VALUE */
00138
00139 /**
00140   * @brief External Low Speed oscillator (LSE) value.
00141   *        This value is used by the UART, RTC HAL module to compute the system frequency
00142   */
00143 #if !defined  (LSE_VALUE)
00144   #define LSE_VALUE    ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
00145 #endif /* LSE_VALUE */
00146
00147
00148 #if !defined  (LSE_STARTUP_TIMEOUT)
00149   #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for LSE start up, in ms */
00150 #endif /* LSE_STARTUP_TIMEOUT */
00151
00152 /**
00153   * @brief External clock source for I2S peripheral
00154   *        This value is used by the I2S HAL module to compute the I2S clock source
00155   *        frequency, this source is inserted directly through I2S_CKIN pad.
00156   */
00157 #if !defined  (EXTERNAL_CLOCK_VALUE)
00158   #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External clock in Hz*/
00159 #endif /* EXTERNAL_CLOCK_VALUE */
00160
00161 /* Tip: To avoid modifying this file each time you need to use different HSE,
00162    ===  you can define the HSE value in your toolchain compiler preprocessor. */
00163
00164 /* ########################### System Configuration ######################### */
00165 /**
00166   * @brief This is the HAL system configuration section
00167   */
00168 #define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
00169 #define  TICK_INT_PRIORITY            ((uint32_t)0x0F) /*!< tick interrupt priority */
00170 #define  USE_RTOS                     0
00171 #define  USE_SD_TRANSCEIVER           1U               /*!< use uSD Transceiver */
00172
00173 /* ########################### Ethernet Configuration ######################### */
00174 #define ETH_TX_DESC_CNT         4  /* number of Ethernet Tx DMA descriptors */
00175 #define ETH_RX_DESC_CNT         4  /* number of Ethernet Rx DMA descriptors */
00176
00177 #define ETH_MAC_ADDR0    ((uint8_t)0x02)
00178 #define ETH_MAC_ADDR1    ((uint8_t)0x00)
00179 #define ETH_MAC_ADDR2    ((uint8_t)0x00)
00180 #define ETH_MAC_ADDR3    ((uint8_t)0x00)
00181 #define ETH_MAC_ADDR4    ((uint8_t)0x00)
00182 #define ETH_MAC_ADDR5    ((uint8_t)0x00)
00183
00184 /* ########################## Assert Selection ############################## */
00185 /**
00186   * @brief Uncomment the line below to expanse the "assert_param" macro in the
00187   *        HAL drivers code
00188   */
00189 /* #define USE_FULL_ASSERT    1 */
00190
00191
00192 /* Includes ------------------------------------------------------------------*/
00193 /**
00194   * @brief Include module's header file
00195   */
00196
00197 #ifdef HAL_RCC_MODULE_ENABLED
00198   #include "stm32h7xx_hal_rcc.h"
00199 #endif /* HAL_RCC_MODULE_ENABLED */
00200
00201 #ifdef HAL_GPIO_MODULE_ENABLED
00202   #include "stm32h7xx_hal_gpio.h"
00203 #endif /* HAL_GPIO_MODULE_ENABLED */
00204
00205 #ifdef HAL_DMA_MODULE_ENABLED
00206   #include "stm32h7xx_hal_dma.h"
00207 #endif /* HAL_DMA_MODULE_ENABLED */
00208
00209 #ifdef HAL_HASH_MODULE_ENABLED
00210   #include "stm32h7xx_hal_hash.h"
00211 #endif /* HAL_HASH_MODULE_ENABLED */
00212
00213 #ifdef HAL_DCMI_MODULE_ENABLED
00214   #include "stm32h7xx_hal_dcmi.h"
00215 #endif /* HAL_DCMI_MODULE_ENABLED */
00216
00217 #ifdef HAL_DMA2D_MODULE_ENABLED
00218   #include "stm32h7xx_hal_dma2d.h"
00219 #endif /* HAL_DMA2D_MODULE_ENABLED */
00220
00221 #ifdef HAL_DFSDM_MODULE_ENABLED
00222   #include "stm32h7xx_hal_dfsdm.h"
00223 #endif /* HAL_DFSDM_MODULE_ENABLED */
00224
00225 #ifdef HAL_ETH_MODULE_ENABLED
00226   #include "stm32h7xx_hal_eth.h"
00227 #endif /* HAL_ETH_MODULE_ENABLED */
00228
00229 #ifdef HAL_CORTEX_MODULE_ENABLED
00230   #include "stm32h7xx_hal_cortex.h"
00231 #endif /* HAL_CORTEX_MODULE_ENABLED */
00232
00233 #ifdef HAL_ADC_MODULE_ENABLED
00234   #include "stm32h7xx_hal_adc.h"
00235 #endif /* HAL_ADC_MODULE_ENABLED */
00236
00237 #ifdef HAL_FDCAN_MODULE_ENABLED
00238   #include "stm32h7xx_hal_fdcan.h"
00239 #endif /* HAL_FDCAN_MODULE_ENABLED */
00240
00241 #ifdef HAL_CEC_MODULE_ENABLED
00242   #include "stm32h7xx_hal_cec.h"
00243 #endif /* HAL_CEC_MODULE_ENABLED */
00244
00245 #ifdef HAL_COMP_MODULE_ENABLED
00246   #include "stm32h7xx_hal_comp.h"
00247 #endif /* HAL_COMP_MODULE_ENABLED */
00248
00249 #ifdef HAL_CRC_MODULE_ENABLED
00250   #include "stm32h7xx_hal_crc.h"
00251 #endif /* HAL_CRC_MODULE_ENABLED */
00252
00253 #ifdef HAL_CRYP_MODULE_ENABLED
00254   #include "stm32h7xx_hal_cryp.h"
00255 #endif /* HAL_CRYP_MODULE_ENABLED */
00256
00257 #ifdef HAL_DAC_MODULE_ENABLED
00258   #include "stm32h7xx_hal_dac.h"
00259 #endif /* HAL_DAC_MODULE_ENABLED */
00260
00261 #ifdef HAL_FLASH_MODULE_ENABLED
00262   #include "stm32h7xx_hal_flash.h"
00263 #endif /* HAL_FLASH_MODULE_ENABLED */
00264
00265 #ifdef HAL_HRTIM_MODULE_ENABLED
00266   #include "stm32h7xx_hal_hrtim.h"
00267 #endif /* HAL_HRTIM_MODULE_ENABLED */
00268
00269 #ifdef HAL_HSEM_MODULE_ENABLED
00270   #include "stm32h7xx_hal_hsem.h"
00271 #endif /* HAL_HSEM_MODULE_ENABLED */
00272
00273 #ifdef HAL_SRAM_MODULE_ENABLED
00274   #include "stm32h7xx_hal_sram.h"
00275 #endif /* HAL_SRAM_MODULE_ENABLED */
00276
00277 #ifdef HAL_NOR_MODULE_ENABLED
00278   #include "stm32h7xx_hal_nor.h"
00279 #endif /* HAL_NOR_MODULE_ENABLED */
00280
00281 #ifdef HAL_NAND_MODULE_ENABLED
00282   #include "stm32h7xx_hal_nand.h"
00283 #endif /* HAL_NAND_MODULE_ENABLED */
00284
00285 #ifdef HAL_I2C_MODULE_ENABLED
00286  #include "stm32h7xx_hal_i2c.h"
00287 #endif /* HAL_I2C_MODULE_ENABLED */
00288
00289 #ifdef HAL_I2S_MODULE_ENABLED
00290  #include "stm32h7xx_hal_i2s.h"
00291 #endif /* HAL_I2S_MODULE_ENABLED */
00292
00293 #ifdef HAL_IWDG_MODULE_ENABLED
00294  #include "stm32h7xx_hal_iwdg.h"
00295 #endif /* HAL_IWDG_MODULE_ENABLED */
00296
00297 #ifdef HAL_JPEG_MODULE_ENABLED
00298  #include "stm32h7xx_hal_jpeg.h"
00299 #endif /* HAL_JPEG_MODULE_ENABLED */
00300
00301 #ifdef HAL_MDIOS_MODULE_ENABLED
00302  #include "stm32h7xx_hal_mdios.h"
00303 #endif /* HAL_MDIOS_MODULE_ENABLED */
00304
00305 #ifdef HAL_MDMA_MODULE_ENABLED
00306  #include "stm32h7xx_hal_mdma.h"
00307 #endif /* HAL_MDMA_MODULE_ENABLED */
00308
00309 #ifdef HAL_MMC_MODULE_ENABLED
00310  #include "stm32h7xx_hal_mmc.h"
00311 #endif /* HAL_MMC_MODULE_ENABLED */
00312
00313 #ifdef HAL_LPTIM_MODULE_ENABLED
00314 #include "stm32h7xx_hal_lptim.h"
00315 #endif /* HAL_LPTIM_MODULE_ENABLED */
00316
00317 #ifdef HAL_LTDC_MODULE_ENABLED
00318 #include "stm32h7xx_hal_ltdc.h"
00319 #endif /* HAL_LTDC_MODULE_ENABLED */
00320
00321 #ifdef HAL_OPAMP_MODULE_ENABLED
00322 #include "stm32h7xx_hal_opamp.h"
00323 #endif /* HAL_OPAMP_MODULE_ENABLED */
00324
00325 #ifdef HAL_PWR_MODULE_ENABLED
00326  #include "stm32h7xx_hal_pwr.h"
00327 #endif /* HAL_PWR_MODULE_ENABLED */
00328
00329 #ifdef HAL_QSPI_MODULE_ENABLED
00330  #include "stm32h7xx_hal_qspi.h"
00331 #endif /* HAL_QSPI_MODULE_ENABLED */
00332
00333 #ifdef HAL_RNG_MODULE_ENABLED
00334  #include "stm32h7xx_hal_rng.h"
00335 #endif /* HAL_RNG_MODULE_ENABLED */
00336
00337 #ifdef HAL_RTC_MODULE_ENABLED
00338  #include "stm32h7xx_hal_rtc.h"
00339 #endif /* HAL_RTC_MODULE_ENABLED */
00340
00341 #ifdef HAL_SAI_MODULE_ENABLED
00342  #include "stm32h7xx_hal_sai.h"
00343 #endif /* HAL_SAI_MODULE_ENABLED */
00344
00345 #ifdef HAL_SD_MODULE_ENABLED
00346  #include "stm32h7xx_hal_sd.h"
00347 #endif /* HAL_SD_MODULE_ENABLED */
00348
00349 #ifdef HAL_SDRAM_MODULE_ENABLED
00350  #include "stm32h7xx_hal_sdram.h"
00351 #endif /* HAL_SDRAM_MODULE_ENABLED */
00352
00353 #ifdef HAL_SPI_MODULE_ENABLED
00354  #include "stm32h7xx_hal_spi.h"
00355 #endif /* HAL_SPI_MODULE_ENABLED */
00356
00357 #ifdef HAL_SPDIFRX_MODULE_ENABLED
00358  #include "stm32h7xx_hal_spdifrx.h"
00359 #endif /* HAL_SPDIFRX_MODULE_ENABLED */
00360
00361 #ifdef HAL_SWPMI_MODULE_ENABLED
00362  #include "stm32h7xx_hal_swpmi.h"
00363 #endif /* HAL_SWPMI_MODULE_ENABLED */
00364
00365 #ifdef HAL_TIM_MODULE_ENABLED
00366  #include "stm32h7xx_hal_tim.h"
00367 #endif /* HAL_TIM_MODULE_ENABLED */
00368
00369 #ifdef HAL_UART_MODULE_ENABLED
00370  #include "stm32h7xx_hal_uart.h"
00371 #endif /* HAL_UART_MODULE_ENABLED */
00372
00373 #ifdef HAL_USART_MODULE_ENABLED
00374  #include "stm32h7xx_hal_usart.h"
00375 #endif /* HAL_USART_MODULE_ENABLED */
00376
00377 #ifdef HAL_IRDA_MODULE_ENABLED
00378  #include "stm32h7xx_hal_irda.h"
00379 #endif /* HAL_IRDA_MODULE_ENABLED */
00380
00381 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00382  #include "stm32h7xx_hal_smartcard.h"
00383 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
00384
00385 #ifdef HAL_SMBUS_MODULE_ENABLED
00386  #include "stm32h7xx_hal_smbus.h"
00387 #endif /* HAL_SMBUS_MODULE_ENABLED */
00388
00389 #ifdef HAL_WWDG_MODULE_ENABLED
00390  #include "stm32h7xx_hal_wwdg.h"
00391 #endif /* HAL_WWDG_MODULE_ENABLED */
00392
00393 #ifdef HAL_PCD_MODULE_ENABLED
00394  #include "stm32h7xx_hal_pcd.h"
00395 #endif /* HAL_PCD_MODULE_ENABLED */
00396
00397 #ifdef HAL_HCD_MODULE_ENABLED
00398  #include "stm32h7xx_hal_hcd.h"
00399 #endif /* HAL_HCD_MODULE_ENABLED */
00400
00401 /* Exported macro ------------------------------------------------------------*/
00402 #ifdef  USE_FULL_ASSERT
00403 /**
00404   * @brief  The assert_param macro is used for function's parameters check.
00405   * @param  expr: If expr is false, it calls assert_failed function
00406   *         which reports the name of the source file and the source
00407   *         line number of the call that failed.
00408   *         If expr is true, it returns no value.
00409   * @retval None
00410   */
00411   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00412 /* Exported functions ------------------------------------------------------- */
00413   void assert_failed(uint8_t* file, uint32_t line);
00414 #else
00415   #define assert_param(expr) ((void)0)
00416 #endif /* USE_FULL_ASSERT */
00417
00418 #ifdef __cplusplus
00419 }
00420 #endif
00421
00422 #endif /* __STM32H7xx_HAL_CONF_H */
00423
00424
00425 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_cortex.c Source File

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stm32h7xx_hal_cortex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_cortex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   CORTEX HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the CORTEX:
00010   *           + Initialization and de-initialization functions
00011   *           + Peripheral Control functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017
00018     [..]
00019     *** How to configure Interrupts using CORTEX HAL driver ***
00020     ===========================================================
00021     [..]
00022     This section provides functions allowing to configure the NVIC interrupts (IRQ).
00023     The Cortex-M exceptions are managed by CMSIS functions.
00024
00025     (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
00026         function according to the following table.
00027     (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
00028     (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
00029     (#) please refer to programming manual for details in how to configure priority.
00030
00031      -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
00032          The pending IRQ priority will be managed only by the sub priority.
00033
00034      -@- IRQ priority order (sorted by highest to lowest priority):
00035         (+@) Lowest preemption priority
00036         (+@) Lowest sub priority
00037         (+@) Lowest hardware priority (IRQ number)
00038
00039     [..]
00040     *** How to configure Systick using CORTEX HAL driver ***
00041     ========================================================
00042     [..]
00043     Setup SysTick Timer for time base.
00044
00045    (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
00046        is a CMSIS function that:
00047         (++) Configures the SysTick Reload register with value passed as function parameter.
00048         (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
00049         (++) Resets the SysTick Counter register.
00050         (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
00051         (++) Enables the SysTick Interrupt.
00052         (++) Starts the SysTick Counter.
00053
00054    (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
00055        HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
00056        HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined
00057        inside the stm32h7xx_hal_cortex.h file.
00058
00059    (+) You can change the SysTick IRQ priority by calling the
00060        HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
00061        call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
00062
00063    (+) To adjust the SysTick time base, use the following formula:
00064
00065        Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
00066        (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
00067        (++) Reload Value should not exceed 0xFFFFFF
00068
00069   @endverbatim
00070   ******************************************************************************
00071   * @attention
00072   *
00073   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00074   *
00075   * Redistribution and use in source and binary forms, with or without modification,
00076   * are permitted provided that the following conditions are met:
00077   *   1. Redistributions of source code must retain the above copyright notice,
00078   *      this list of conditions and the following disclaimer.
00079   *   2. Redistributions in binary form must reproduce the above copyright notice,
00080   *      this list of conditions and the following disclaimer in the documentation
00081   *      and/or other materials provided with the distribution.
00082   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00083   *      may be used to endorse or promote products derived from this software
00084   *      without specific prior written permission.
00085   *
00086   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00087   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00088   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00089   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00090   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00091   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00092   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00093   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00094   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00095   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00096   *
00097   ******************************************************************************
00098   */
00099
00100 /* Includes ------------------------------------------------------------------*/
00101 #include "stm32h7xx_hal.h"
00102
00103 /** @addtogroup STM32H7xx_HAL_Driver
00104   * @{
00105   */
00106
00107 /** @defgroup CORTEX CORTEX
00108   * @brief CORTEX HAL module driver
00109   * @{
00110   */
00111
00112 #ifdef HAL_CORTEX_MODULE_ENABLED
00113
00114 /* Private types -------------------------------------------------------------*/
00115 /* Private variables ---------------------------------------------------------*/
00116 /* Private constants ---------------------------------------------------------*/
00117 /* Private macros ------------------------------------------------------------*/
00118 /* Private functions ---------------------------------------------------------*/
00119 /* Exported functions --------------------------------------------------------*/
00120
00121 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
00122   * @{
00123   */
00124
00125
00126 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
00127  *  @brief    Initialization and Configuration functions
00128  *
00129 @verbatim
00130   ==============================================================================
00131               ##### Initialization and de-initialization functions #####
00132   ==============================================================================
00133     [..]
00134       This section provides the CORTEX HAL driver functions allowing to configure Interrupts
00135       Systick functionalities
00136
00137 @endverbatim
00138   * @{
00139   */
00140
00141
00142 /**
00143   * @brief  Sets the priority grouping field (preemption priority and subpriority)
00144   *         using the required unlock sequence.
00145   * @param  PriorityGroup: The priority grouping bits length.
00146   *         This parameter can be one of the following values:
00147   *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
00148   *                                    4 bits for subpriority
00149   *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
00150   *                                    3 bits for subpriority
00151   *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
00152   *                                    2 bits for subpriority
00153   *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
00154   *                                    1 bits for subpriority
00155   *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
00156   *                                    0 bits for subpriority
00157   * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
00158   *         The pending IRQ priority will be managed only by the subpriority.
00159   * @retval None
00160   */
00161 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
00162 {
00163   /* Check the parameters */
00164   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
00165
00166   /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
00167   NVIC_SetPriorityGrouping(PriorityGroup);
00168 }
00169
00170 /**
00171   * @brief  Sets the priority of an interrupt.
00172   * @param  IRQn: External interrupt number.
00173   *         This parameter can be an enumerator of IRQn_Type enumeration
00174   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
00175   * @param  PreemptPriority: The preemption priority for the IRQn channel.
00176   *         This parameter can be a value between 0 and 15
00177   *         A lower priority value indicates a higher priority
00178   * @param  SubPriority: the subpriority level for the IRQ channel.
00179   *         This parameter can be a value between 0 and 15
00180   *         A lower priority value indicates a higher priority.
00181   * @retval None
00182   */
00183 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
00184 {
00185   uint32_t prioritygroup = 0x00;
00186
00187   /* Check the parameters */
00188   assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
00189   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
00190
00191   prioritygroup = NVIC_GetPriorityGrouping();
00192
00193   NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
00194 }
00195
00196 /**
00197   * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
00198   * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
00199   *         function should be called before.
00200   * @param  IRQn External interrupt number.
00201   *         This parameter can be an enumerator of IRQn_Type enumeration
00202   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
00203   * @retval None
00204   */
00205 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
00206 {
00207   /* Check the parameters */
00208   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00209
00210   /* Enable interrupt */
00211   NVIC_EnableIRQ(IRQn);
00212 }
00213
00214 /**
00215   * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
00216   * @param  IRQn External interrupt number.
00217   *         This parameter can be an enumerator of IRQn_Type enumeration
00218   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
00219   * @retval None
00220   */
00221 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
00222 {
00223   /* Check the parameters */
00224   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00225
00226   /* Disable interrupt */
00227   NVIC_DisableIRQ(IRQn);
00228 }
00229
00230 /**
00231   * @brief  Initiates a system reset request to reset the MCU.
00232   * @retval None
00233   */
00234 void HAL_NVIC_SystemReset(void)
00235 {
00236   /* System Reset */
00237   NVIC_SystemReset();
00238 }
00239
00240 /**
00241   * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
00242   *         Counter is in free running mode to generate periodic interrupts.
00243   * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
00244   * @retval status:  - 0  Function succeeded.
00245   *                  - 1  Function failed.
00246   */
00247 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
00248 {
00249    return SysTick_Config(TicksNumb);
00250 }
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
00256  *  @brief   Cortex control functions
00257  *
00258 @verbatim
00259   ==============================================================================
00260                       ##### Peripheral Control functions #####
00261   ==============================================================================
00262     [..]
00263       This subsection provides a set of functions allowing to control the CORTEX
00264       (NVIC, SYSTICK, MPU) functionalities.
00265
00266
00267 @endverbatim
00268   * @{
00269   */
00270 #if (__MPU_PRESENT == 1)
00271 /**
00272   * @brief  Initializes and configures the Region and the memory to be protected.
00273   * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
00274   *                the initialization and configuration information.
00275   * @retval None
00276   */
00277 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
00278 {
00279   /* Check the parameters */
00280   assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
00281   assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
00282
00283   /* Set the Region number */
00284   MPU->RNR = MPU_Init->Number;
00285
00286   if ((MPU_Init->Enable) != RESET)
00287   {
00288     /* Check the parameters */
00289     assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
00290     assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
00291     assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
00292     assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
00293     assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
00294     assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
00295     assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
00296     assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
00297
00298     MPU->RBAR = MPU_Init->BaseAddress;
00299     MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
00300                 ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
00301                 ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
00302                 ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
00303                 ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
00304                 ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
00305                 ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
00306                 ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
00307                 ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
00308   }
00309   else
00310   {
00311     MPU->RBAR = 0x00;
00312     MPU->RASR = 0x00;
00313   }
00314 }
00315 #endif /* __MPU_PRESENT */
00316
00317 /**
00318   * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
00319   * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
00320   */
00321 uint32_t HAL_NVIC_GetPriorityGrouping(void)
00322 {
00323   /* Get the PRIGROUP[10:8] field value */
00324   return NVIC_GetPriorityGrouping();
00325 }
00326
00327 /**
00328   * @brief  Gets the priority of an interrupt.
00329   * @param  IRQn: External interrupt number.
00330   *         This parameter can be an enumerator of IRQn_Type enumeration
00331   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
00332   * @param   PriorityGroup: the priority grouping bits length.
00333   *         This parameter can be one of the following values:
00334   *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
00335   *                                      4 bits for subpriority
00336   *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
00337   *                                      3 bits for subpriority
00338   *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
00339   *                                      2 bits for subpriority
00340   *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
00341   *                                      1 bits for subpriority
00342   *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
00343   *                                      0 bits for subpriority
00344   * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
00345   * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
00346   * @retval None
00347   */
00348 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
00349 {
00350   /* Check the parameters */
00351   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
00352  /* Get priority for Cortex-M system or device specific interrupts */
00353   NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
00354 }
00355
00356 /**
00357   * @brief  Sets Pending bit of an external interrupt.
00358   * @param  IRQn External interrupt number
00359   *         This parameter can be an enumerator of IRQn_Type enumeration
00360   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
00361   * @retval None
00362   */
00363 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
00364 {
00365   /* Check the parameters */
00366   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00367
00368   /* Set interrupt pending */
00369   NVIC_SetPendingIRQ(IRQn);
00370 }
00371
00372 /**
00373   * @brief  Gets Pending Interrupt (reads the pending register in the NVIC
00374   *         and returns the pending bit for the specified interrupt).
00375   * @param  IRQn External interrupt number.
00376   *          This parameter can be an enumerator of IRQn_Type enumeration
00377   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
00378   * @retval status: - 0  Interrupt status is not pending.
00379   *                 - 1  Interrupt status is pending.
00380   */
00381 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
00382 {
00383   /* Check the parameters */
00384   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00385
00386   /* Return 1 if pending else 0 */
00387   return NVIC_GetPendingIRQ(IRQn);
00388 }
00389
00390 /**
00391   * @brief  Clears the pending bit of an external interrupt.
00392   * @param  IRQn External interrupt number.
00393   *         This parameter can be an enumerator of IRQn_Type enumeration
00394   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
00395   * @retval None
00396   */
00397 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
00398 {
00399   /* Check the parameters */
00400   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00401
00402   /* Clear pending interrupt */
00403   NVIC_ClearPendingIRQ(IRQn);
00404 }
00405
00406 /**
00407   * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
00408   * @param IRQn External interrupt number
00409   *         This parameter can be an enumerator of IRQn_Type enumeration
00410   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
00411   * @retval status: - 0  Interrupt status is not pending.
00412   *                 - 1  Interrupt status is pending.
00413   */
00414 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
00415 {
00416   /* Check the parameters */
00417   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00418
00419   /* Return 1 if active else 0 */
00420   return NVIC_GetActive(IRQn);
00421 }
00422
00423 /**
00424   * @brief  Configures the SysTick clock source.
00425   * @param  CLKSource: specifies the SysTick clock source.
00426   *          This parameter can be one of the following values:
00427   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
00428   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
00429   * @retval None
00430   */
00431 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
00432 {
00433   /* Check the parameters */
00434   assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
00435   if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
00436   {
00437     SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
00438   }
00439   else
00440   {
00441     SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
00442   }
00443 }
00444
00445 /**
00446   * @brief  This function handles SYSTICK interrupt request.
00447   * @retval None
00448   */
00449 void HAL_SYSTICK_IRQHandler(void)
00450 {
00451   HAL_SYSTICK_Callback();
00452 }
00453
00454 /**
00455   * @brief  SYSTICK callback.
00456   * @retval None
00457   */
00458 __weak void HAL_SYSTICK_Callback(void)
00459 {
00460   /* NOTE : This function Should not be modified, when the callback is needed,
00461             the HAL_SYSTICK_Callback could be implemented in the user file
00462    */
00463 }
00464
00465
00466 /**
00467 * @brief  Returns the current CPU ID.
00468 * @retval CPU identifier
00469 */
00470 uint32_t HAL_GetCurrentCPUID(void)
00471 {
00472   return  CM7_CPUID;
00473 }
00474
00475 /**
00476   * @}
00477   */
00478
00479 /**
00480   * @}
00481   */
00482
00483 #endif /* HAL_CORTEX_MODULE_ENABLED */
00484 /**
00485   * @}
00486   */
00487
00488 /**
00489   * @}
00490   */
00491
00492 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_cortex.h Source File

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stm32h7xx_hal_cortex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_cortex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of CORTEX HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_CORTEX_H
00040 #define __STM32H7xx_HAL_CORTEX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup CORTEX
00054   * @{
00055   */
00056 /* Exported types ------------------------------------------------------------*/
00057 /** @defgroup CORTEX_Exported_Types Cortex Exported Types
00058   * @{
00059   */
00060
00061 #if (__MPU_PRESENT == 1)
00062 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
00063   * @brief  MPU Region initialization structure
00064   * @{
00065   */
00066 typedef struct
00067 {
00068   uint8_t                Enable;                /*!< Specifies the status of the region.
00069                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
00070   uint8_t                Number;                /*!< Specifies the number of the region to protect.
00071                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
00072   uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
00073   uint8_t                Size;                  /*!< Specifies the size of the region to protect.
00074                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
00075   uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
00076                                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
00077   uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
00078                                                      This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
00079   uint8_t                AccessPermission;      /*!< Specifies the region access permission type.
00080                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
00081   uint8_t                DisableExec;           /*!< Specifies the instruction access status.
00082                                                      This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
00083   uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.
00084                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
00085   uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.
00086                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
00087   uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.
00088                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
00089 }MPU_Region_InitTypeDef;
00090 /**
00091   * @}
00092   */
00093 #endif /* __MPU_PRESENT */
00094
00095 /**
00096   * @}
00097   */
00098
00099 /* Exported constants --------------------------------------------------------*/
00100
00101 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
00102   * @{
00103   */
00104
00105 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
00106   * @{
00107   */
00108 #define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
00109                                                                  4 bits for subpriority */
00110 #define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
00111                                                                  3 bits for subpriority */
00112 #define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
00113                                                                  2 bits for subpriority */
00114 #define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
00115                                                                  1 bits for subpriority */
00116 #define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
00117                                                                  0 bits for subpriority */
00118 /**
00119   * @}
00120   */
00121
00122 /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
00123   * @{
00124   */
00125 #define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
00126 #define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
00127
00128 /**
00129   * @}
00130   */
00131
00132 #if (__MPU_PRESENT == 1)
00133 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
00134   * @{
00135   */
00136 #define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)
00137 #define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)
00138 #define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)
00139 #define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)
00140 /**
00141   * @}
00142   */
00143
00144 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
00145   * @{
00146   */
00147 #define  MPU_REGION_ENABLE     ((uint8_t)0x01)
00148 #define  MPU_REGION_DISABLE    ((uint8_t)0x00)
00149 /**
00150   * @}
00151   */
00152
00153 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
00154   * @{
00155   */
00156 #define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
00157 #define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
00163   * @{
00164   */
00165 #define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
00166 #define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
00172   * @{
00173   */
00174 #define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)
00175 #define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
00181   * @{
00182   */
00183 #define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)
00184 #define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
00190   * @{
00191   */
00192 #define  MPU_TEX_LEVEL0    ((uint8_t)0x00)
00193 #define  MPU_TEX_LEVEL1    ((uint8_t)0x01)
00194 #define  MPU_TEX_LEVEL2    ((uint8_t)0x02)
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
00200   * @{
00201   */
00202 #define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
00203 #define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
00204 #define   MPU_REGION_SIZE_128B     ((uint8_t)0x06)
00205 #define   MPU_REGION_SIZE_256B     ((uint8_t)0x07)
00206 #define   MPU_REGION_SIZE_512B     ((uint8_t)0x08)
00207 #define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)
00208 #define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
00209 #define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B)
00210 #define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C)
00211 #define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D)
00212 #define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E)
00213 #define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F)
00214 #define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
00215 #define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
00216 #define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
00217 #define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13)
00218 #define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14)
00219 #define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15)
00220 #define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16)
00221 #define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
00222 #define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
00223 #define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
00224 #define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
00225 #define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
00226 #define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
00227 #define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D)
00228 #define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E)
00229 #define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
00235   * @{
00236   */
00237 #define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)
00238 #define  MPU_REGION_PRIV_RW        ((uint8_t)0x01)
00239 #define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)
00240 #define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)
00241 #define  MPU_REGION_PRIV_RO        ((uint8_t)0x05)
00242 #define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
00248   * @{
00249   */
00250 #define  MPU_REGION_NUMBER0    ((uint8_t)0x00)
00251 #define  MPU_REGION_NUMBER1    ((uint8_t)0x01)
00252 #define  MPU_REGION_NUMBER2    ((uint8_t)0x02)
00253 #define  MPU_REGION_NUMBER3    ((uint8_t)0x03)
00254 #define  MPU_REGION_NUMBER4    ((uint8_t)0x04)
00255 #define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
00256 #define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
00257 #define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
00258 /**
00259   * @}
00260   */
00261 #endif /* __MPU_PRESENT */
00262
00263 /**
00264   * @}
00265   */
00266
00267
00268 /* Exported Macros -----------------------------------------------------------*/
00269 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
00270   * @{
00271   */
00272
00273 /**
00274   * @}
00275   */
00276
00277
00278
00279 /** @defgroup CORTEX_CPU_Identifier CORTEX_CPU_Identifier
00280   * @{
00281   */
00282 #define CM7_CPUID        (uint32_t)0x00000003
00283
00284 /**
00285   * @}
00286   */
00287
00288
00289 /* Exported functions --------------------------------------------------------*/
00290 /** @addtogroup CORTEX_Exported_Functions
00291   * @{
00292   */
00293
00294 /** @addtogroup CORTEX_Exported_Functions_Group1
00295  * @{
00296  */
00297 /* Initialization and de-initialization functions *****************************/
00298 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
00299 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
00300 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
00301 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
00302 void HAL_NVIC_SystemReset(void);
00303 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
00304 /**
00305   * @}
00306   */
00307
00308 /** @addtogroup CORTEX_Exported_Functions_Group2
00309  * @{
00310  */
00311 /* Peripheral Control functions ***********************************************/
00312 #if (__MPU_PRESENT == 1)
00313 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
00314 #endif /* __MPU_PRESENT */
00315 uint32_t HAL_NVIC_GetPriorityGrouping(void);
00316 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
00317 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
00318 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
00319 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
00320 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
00321 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
00322 void HAL_SYSTICK_IRQHandler(void);
00323 void HAL_SYSTICK_Callback(void);
00324 uint32_t HAL_GetCurrentCPUID(void);
00325
00326
00327 /**
00328   * @}
00329   */
00330
00331 /**
00332   * @}
00333   */
00334
00335 /* Private types -------------------------------------------------------------*/
00336 /* Private variables ---------------------------------------------------------*/
00337 /* Private constants ---------------------------------------------------------*/
00338 /* Private macros ------------------------------------------------------------*/
00339 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
00340   * @{
00341   */
00342 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
00343                                        ((GROUP) == NVIC_PRIORITYGROUP_1) || \
00344                                        ((GROUP) == NVIC_PRIORITYGROUP_2) || \
00345                                        ((GROUP) == NVIC_PRIORITYGROUP_3) || \
00346                                        ((GROUP) == NVIC_PRIORITYGROUP_4))
00347
00348 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
00349
00350 #define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10)
00351
00352 #define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= 0x00)
00353
00354 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
00355                                        ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
00356
00357 #if (__MPU_PRESENT == 1)
00358 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
00359                                      ((STATE) == MPU_REGION_DISABLE))
00360
00361 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
00362                                           ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
00363
00364 #define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
00365                                           ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
00366
00367 #define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
00368                                           ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
00369
00370 #define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
00371                                           ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
00372
00373 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
00374                                 ((TYPE) == MPU_TEX_LEVEL1)  || \
00375                                 ((TYPE) == MPU_TEX_LEVEL2))
00376
00377 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
00378                                                   ((TYPE) == MPU_REGION_PRIV_RW)     || \
00379                                                   ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
00380                                                   ((TYPE) == MPU_REGION_FULL_ACCESS) || \
00381                                                   ((TYPE) == MPU_REGION_PRIV_RO)     || \
00382                                                   ((TYPE) == MPU_REGION_PRIV_RO_URO))
00383
00384 #define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
00385                                          ((NUMBER) == MPU_REGION_NUMBER1) || \
00386                                          ((NUMBER) == MPU_REGION_NUMBER2) || \
00387                                          ((NUMBER) == MPU_REGION_NUMBER3) || \
00388                                          ((NUMBER) == MPU_REGION_NUMBER4) || \
00389                                          ((NUMBER) == MPU_REGION_NUMBER5) || \
00390                                          ((NUMBER) == MPU_REGION_NUMBER6) || \
00391                                          ((NUMBER) == MPU_REGION_NUMBER7))
00392
00393 #define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
00394                                      ((SIZE) == MPU_REGION_SIZE_64B)   || \
00395                                      ((SIZE) == MPU_REGION_SIZE_128B)  || \
00396                                      ((SIZE) == MPU_REGION_SIZE_256B)  || \
00397                                      ((SIZE) == MPU_REGION_SIZE_512B)  || \
00398                                      ((SIZE) == MPU_REGION_SIZE_1KB)   || \
00399                                      ((SIZE) == MPU_REGION_SIZE_2KB)   || \
00400                                      ((SIZE) == MPU_REGION_SIZE_4KB)   || \
00401                                      ((SIZE) == MPU_REGION_SIZE_8KB)   || \
00402                                      ((SIZE) == MPU_REGION_SIZE_16KB)  || \
00403                                      ((SIZE) == MPU_REGION_SIZE_32KB)  || \
00404                                      ((SIZE) == MPU_REGION_SIZE_64KB)  || \
00405                                      ((SIZE) == MPU_REGION_SIZE_128KB) || \
00406                                      ((SIZE) == MPU_REGION_SIZE_256KB) || \
00407                                      ((SIZE) == MPU_REGION_SIZE_512KB) || \
00408                                      ((SIZE) == MPU_REGION_SIZE_1MB)   || \
00409                                      ((SIZE) == MPU_REGION_SIZE_2MB)   || \
00410                                      ((SIZE) == MPU_REGION_SIZE_4MB)   || \
00411                                      ((SIZE) == MPU_REGION_SIZE_8MB)   || \
00412                                      ((SIZE) == MPU_REGION_SIZE_16MB)  || \
00413                                      ((SIZE) == MPU_REGION_SIZE_32MB)  || \
00414                                      ((SIZE) == MPU_REGION_SIZE_64MB)  || \
00415                                      ((SIZE) == MPU_REGION_SIZE_128MB) || \
00416                                      ((SIZE) == MPU_REGION_SIZE_256MB) || \
00417                                      ((SIZE) == MPU_REGION_SIZE_512MB) || \
00418                                      ((SIZE) == MPU_REGION_SIZE_1GB)   || \
00419                                      ((SIZE) == MPU_REGION_SIZE_2GB)   || \
00420                                      ((SIZE) == MPU_REGION_SIZE_4GB))
00421
00422 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
00423 #endif /* __MPU_PRESENT */
00424
00425 /**
00426   * @}
00427   */
00428
00429 /* Private functions ---------------------------------------------------------*/
00430 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions
00431   * @brief    CORTEX private  functions
00432   * @{
00433   */
00434
00435 #if (__MPU_PRESENT == 1)
00436 /**
00437   * @brief  Disables the MPU
00438   * @retval None
00439   */
00440 __STATIC_INLINE void HAL_MPU_Disable(void)
00441 {
00442   /* Disable fault exceptions */
00443   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
00444
00445   /* Disable the MPU */
00446   MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
00447 }
00448
00449 /**
00450   * @brief  Enables the MPU
00451   * @param  MPU_Control: Specifies the control mode of the MPU during hard fault,
00452   *          NMI, FAULTMASK and privileged access to the default memory
00453   *          This parameter can be one of the following values:
00454   *            @arg MPU_HFNMI_PRIVDEF_NONE
00455   *            @arg MPU_HARDFAULT_NMI
00456   *            @arg MPU_PRIVILEGED_DEFAULT
00457   *            @arg MPU_HFNMI_PRIVDEF
00458   * @retval None
00459   */
00460 __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
00461 {
00462   /* Enable the MPU */
00463   MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
00464
00465   /* Enable fault exceptions */
00466   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
00467 }
00468 #endif /* __MPU_PRESENT */
00469
00470 /**
00471   * @}
00472   */
00473
00474 /**
00475   * @}
00476   */
00477
00478 /**
00479   * @}
00480   */
00481
00482 #ifdef __cplusplus
00483 }
00484 #endif
00485
00486 #endif /* __STM32H7xx_HAL_CORTEX_H */
00487
00488
00489 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_crc.c Source File

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stm32h7xx_hal_crc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_crc.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   CRC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + Peripheral Control functions
00012   *           + Peripheral State functions
00013   *
00014   @verbatim
00015  ===============================================================================
00016                      ##### CRC How to use this driver #####
00017  ===============================================================================
00018     [..]
00019
00020     (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
00021
00022     (#) Initialize CRC calculator
00023          (++) specify generating polynomial (IP default or non-default one)
00024          (++) specify initialization value (IP default or non-default one)
00025          (++) specify input data format
00026          (++) specify input or output data inversion mode if any
00027
00028     (#) Use HAL_CRC_Accumulate() function to compute the CRC value of the
00029         input data buffer starting with the previously computed CRC as
00030         initialization value
00031
00032     (#) Use HAL_CRC_Calculate() function to compute the CRC value of the
00033         input data buffer starting with the defined initialization value
00034         (default or non-default) to initiate CRC calculation
00035
00036   @endverbatim
00037   ******************************************************************************
00038   * @attention
00039   *
00040   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00041   *
00042   * Redistribution and use in source and binary forms, with or without modification,
00043   * are permitted provided that the following conditions are met:
00044   *   1. Redistributions of source code must retain the above copyright notice,
00045   *      this list of conditions and the following disclaimer.
00046   *   2. Redistributions in binary form must reproduce the above copyright notice,
00047   *      this list of conditions and the following disclaimer in the documentation
00048   *      and/or other materials provided with the distribution.
00049   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00050   *      may be used to endorse or promote products derived from this software
00051   *      without specific prior written permission.
00052   *
00053   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00054   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00055   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00056   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00057   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00058   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00059   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00060   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00061   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00062   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00063   *
00064   ******************************************************************************
00065   */
00066
00067 /* Includes ------------------------------------------------------------------*/
00068 #include "stm32h7xx_hal.h"
00069
00070 /** @addtogroup STM32H7xx_HAL_Driver
00071   * @{
00072   */
00073
00074 /** @defgroup CRC CRC
00075   * @brief CRC HAL module driver.
00076   * @{
00077   */
00078
00079 #ifdef HAL_CRC_MODULE_ENABLED
00080
00081 /* Private typedef -----------------------------------------------------------*/
00082 /* Private define ------------------------------------------------------------*/
00083 /* Private macro -------------------------------------------------------------*/
00084 /* Private variables ---------------------------------------------------------*/
00085 /* Private function prototypes -----------------------------------------------*/
00086 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
00087 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
00088 /* Exported functions --------------------------------------------------------*/
00089
00090 /** @defgroup CRC_Exported_Functions CRC Exported Functions
00091   * @{
00092   */
00093
00094 /** @defgroup HAL_CRC_Group1 Initialization/de-initialization functions
00095   *  @brief    Initialization and Configuration functions.
00096   *
00097 @verbatim
00098  ===============================================================================
00099             ##### Initialization and de-initialization functions #####
00100  ===============================================================================
00101     [..]  This section provides functions allowing to:
00102       (+) Initialize the CRC according to the specified parameters
00103           in the CRC_InitTypeDef and create the associated handle
00104       (+) DeInitialize the CRC peripheral
00105       (+) Initialize the CRC MSP
00106       (+) DeInitialize CRC MSP
00107
00108 @endverbatim
00109   * @{
00110   */
00111
00112 /**
00113   * @brief  Initialize the CRC according to the specified
00114   *         parameters in the CRC_InitTypeDef and create the associated handle.
00115   * @param  hcrc: CRC handle
00116   * @retval HAL status
00117   */
00118 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
00119 {
00120   /* Check the CRC handle allocation */
00121   if(hcrc == NULL)
00122   {
00123     return HAL_ERROR;
00124   }
00125
00126   /* Check the parameters */
00127   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
00128
00129   if(hcrc->State == HAL_CRC_STATE_RESET)
00130   {
00131     /* Allocate lock resource and initialize it */
00132     hcrc->Lock = HAL_UNLOCKED;
00133     /* Init the low level hardware */
00134     HAL_CRC_MspInit(hcrc);
00135   }
00136
00137   /* Change CRC peripheral state */
00138   hcrc->State = HAL_CRC_STATE_BUSY;
00139
00140   /* check whether or not non-default generating polynomial has been
00141    * picked up by user */
00142   assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
00143   if(hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
00144   {
00145     /* initialize IP with default generating polynomial */
00146     WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
00147     MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
00148   }
00149   else
00150   {
00151     /* initialize CRC IP with generating polynomial defined by user */
00152     if(HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
00153     {
00154       return HAL_ERROR;
00155     }
00156   }
00157
00158   /* check whether or not non-default CRC initial value has been
00159    * picked up by user */
00160   assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
00161   if(hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
00162   {
00163     WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
00164   }
00165   else
00166   {
00167     WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
00168   }
00169
00170
00171   /* set input data inversion mode */
00172   assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
00173   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
00174
00175   /* set output data inversion mode */
00176   assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
00177   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
00178
00179   /* makes sure the input data format (bytes, halfwords or words stream)
00180    * is properly specified by user */
00181   assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
00182
00183   /* Change CRC peripheral state */
00184   hcrc->State = HAL_CRC_STATE_READY;
00185
00186   /* Return function status */
00187   return HAL_OK;
00188 }
00189
00190 /**
00191   * @brief  DeInitialize the CRC peripheral.
00192   * @param  hcrc: CRC handle
00193   * @retval HAL status
00194   */
00195 HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
00196 {
00197   /* Check the CRC handle allocation */
00198   if(hcrc == NULL)
00199   {
00200     return HAL_ERROR;
00201   }
00202
00203   /* Check the parameters */
00204   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
00205
00206   /* Check the CRC peripheral state */
00207   if(hcrc->State == HAL_CRC_STATE_BUSY)
00208   {
00209     return HAL_BUSY;
00210   }
00211
00212   /* Change CRC peripheral state */
00213   hcrc->State = HAL_CRC_STATE_BUSY;
00214
00215   /* Reset CRC calculation unit */
00216   __HAL_CRC_DR_RESET(hcrc);
00217
00218   /* Reset IDR register content */
00219   CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
00220
00221   /* DeInit the low level hardware */
00222   HAL_CRC_MspDeInit(hcrc);
00223
00224   /* Change CRC peripheral state */
00225   hcrc->State = HAL_CRC_STATE_RESET;
00226
00227   /* Process unlocked */
00228   __HAL_UNLOCK(hcrc);
00229
00230   /* Return function status */
00231   return HAL_OK;
00232 }
00233
00234 /**
00235   * @brief  Initialize the CRC MSP.
00236   * @param  hcrc: CRC handle
00237   * @retval None
00238   */
00239 __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
00240 {
00241   /* Prevent unused argument(s) compilation warning */
00242   UNUSED(hcrc);
00243
00244   /* NOTE : This function should not be modified, when the callback is needed,
00245             the HAL_CRC_MspInit can be implemented in the user file
00246    */
00247 }
00248
00249 /**
00250   * @brief  DeInitialize the CRC MSP.
00251   * @param  hcrc: CRC handle
00252   * @retval None
00253   */
00254 __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
00255 {
00256   /* Prevent unused argument(s) compilation warning */
00257   UNUSED(hcrc);
00258
00259   /* NOTE : This function should not be modified, when the callback is needed,
00260             the HAL_CRC_MspDeInit can be implemented in the user file
00261    */
00262 }
00263
00264 /**
00265   * @}
00266   */
00267
00268 /** @defgroup HAL_CRC_Group2 Peripheral Control functions
00269   *  @brief   Peripheral Control functions
00270   *
00271 @verbatim
00272  ==============================================================================
00273                       ##### Peripheral Control functions #####
00274  ==============================================================================
00275     [..]  This section provides functions allowing to:
00276       (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00277           using combination of the previous CRC value and the new one.
00278
00279           or
00280
00281       (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00282           independently of the previous CRC value.
00283
00284 @endverbatim
00285   * @{
00286   */
00287
00288 /**
00289   * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00290   *         starting with the previously computed CRC as initialization value.
00291   * @param  hcrc: CRC handle
00292   * @param  pBuffer: pointer to the input data buffer, exact input data format is
00293   *         provided by hcrc->InputDataFormat.
00294   * @param  BufferLength: input data buffer length (number of bytes if pBuffer
00295   *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
00296   *         number of words if pBuffer type is * uint32_t).
00297   * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
00298   *        Input buffer pointers with other types simply need to be cast in uint32_t
00299   *        and the API will internally adjust its input data processing based on the
00300   *        handle field hcrc->InputDataFormat.
00301   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00302   */
00303 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
00304 {
00305   uint32_t index = 0; /* CRC input data buffer index */
00306   uint32_t temp = 0;  /* CRC output (read from hcrc->Instance->DR register) */
00307
00308   /* Process locked */
00309   __HAL_LOCK(hcrc);
00310
00311   /* Change CRC peripheral state */
00312   hcrc->State = HAL_CRC_STATE_BUSY;
00313
00314   switch (hcrc->InputDataFormat)
00315   {
00316     case CRC_INPUTDATA_FORMAT_WORDS:
00317       /* Enter Data to the CRC calculator */
00318       for(index = 0; index < BufferLength; index++)
00319       {
00320         hcrc->Instance->DR = pBuffer[index];
00321       }
00322       temp = hcrc->Instance->DR;
00323       break;
00324
00325     case CRC_INPUTDATA_FORMAT_BYTES:
00326       temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
00327       break;
00328
00329     case CRC_INPUTDATA_FORMAT_HALFWORDS:
00330       temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
00331       break;
00332     default:
00333       break;
00334   }
00335
00336   /* Change CRC peripheral state */
00337   hcrc->State = HAL_CRC_STATE_READY;
00338
00339   /* Process unlocked */
00340   __HAL_UNLOCK(hcrc);
00341
00342   /* Return the CRC computed value */
00343   return temp;
00344 }
00345
00346 /**
00347   * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00348   *         starting with hcrc->Instance->INIT as initialization value.
00349   * @param  hcrc: CRC handle
00350   * @param  pBuffer: pointer to the input data buffer, exact input data format is
00351   *         provided by hcrc->InputDataFormat.
00352   * @param  BufferLength: input data buffer length (number of bytes if pBuffer
00353   *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
00354   *         number of words if pBuffer type is * uint32_t).
00355   * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
00356   *        Input buffer pointers with other types simply need to be cast in uint32_t
00357   *        and the API will internally adjust its input data processing based on the
00358   *        handle field hcrc->InputDataFormat.
00359   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00360   */
00361 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
00362 {
00363   uint32_t index = 0; /* CRC input data buffer index */
00364   uint32_t temp = 0;  /* CRC output (read from hcrc->Instance->DR register) */
00365
00366   /* Process locked */
00367   __HAL_LOCK(hcrc);
00368
00369   /* Change CRC peripheral state */
00370   hcrc->State = HAL_CRC_STATE_BUSY;
00371
00372   /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
00373   *  written in hcrc->Instance->DR) */
00374   __HAL_CRC_DR_RESET(hcrc);
00375
00376   switch (hcrc->InputDataFormat)
00377   {
00378     case CRC_INPUTDATA_FORMAT_WORDS:
00379       /* Enter 32-bit input data to the CRC calculator */
00380       for(index = 0; index < BufferLength; index++)
00381       {
00382         hcrc->Instance->DR = pBuffer[index];
00383       }
00384       temp = hcrc->Instance->DR;
00385       break;
00386
00387     case CRC_INPUTDATA_FORMAT_BYTES:
00388       /* Specific 8-bit input data handling  */
00389       temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
00390       break;
00391
00392     case CRC_INPUTDATA_FORMAT_HALFWORDS:
00393       /* Specific 16-bit input data handling  */
00394       temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
00395       break;
00396     default:
00397       break;
00398   }
00399
00400   /* Change CRC peripheral state */
00401   hcrc->State = HAL_CRC_STATE_READY;
00402
00403   /* Process unlocked */
00404   __HAL_UNLOCK(hcrc);
00405
00406   /* Return the CRC computed value */
00407   return temp;
00408 }
00409
00410 /**
00411   * @brief  Enter 8-bit input data to the CRC calculator.
00412   *         Specific data handling to optimize processing time.
00413   * @param  hcrc: CRC handle
00414   * @param  pBuffer: pointer to the input data buffer
00415   * @param  BufferLength: input data buffer length
00416   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00417   */
00418 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
00419 {
00420   uint32_t i = 0; /* input data buffer index */
00421
00422    /* Processing time optimization: 4 bytes are entered in a row with a single word write,
00423     * last bytes must be carefully fed to the CRC calculator to ensure a correct type
00424     * handling by the IP */
00425    for(i = 0; i < (BufferLength/4); i++)
00426    {
00427      hcrc->Instance->DR = (uint32_t)(((uint32_t)(pBuffer[4*i])<<24) | ((uint32_t)(pBuffer[4*i+1])<<16) | ((uint32_t)(pBuffer[4*i+2])<<8) | (uint32_t)(pBuffer[4*i+3]));
00428    }
00429    /* last bytes specific handling */
00430    if((BufferLength%4) != 0)
00431    {
00432      if(BufferLength%4 == 1)
00433      {
00434        *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i];
00435      }
00436      if(BufferLength%4 == 2)
00437      {
00438        *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)((uint16_t)((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));
00439      }
00440      if(BufferLength%4 == 3)
00441      {
00442        *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)((uint16_t)((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));
00443        *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
00444      }
00445    }
00446
00447   /* Return the CRC computed value */
00448   return hcrc->Instance->DR;
00449 }
00450
00451 /**
00452   * @brief  Enter 16-bit input data to the CRC calculator.
00453   *         Specific data handling to optimize processing time.
00454   * @param  hcrc: CRC handle
00455   * @param  pBuffer: pointer to the input data buffer
00456   * @param  BufferLength: input data buffer length
00457   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00458   */
00459 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
00460 {
00461   uint32_t i = 0;  /* input data buffer index */
00462
00463   /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
00464    * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
00465    * a correct type handling by the IP */
00466   for(i = 0; i < (BufferLength/2); i++)
00467   {
00468     hcrc->Instance->DR = (((uint32_t)(pBuffer[2*i])<<16) | (uint32_t)(pBuffer[2*i+1]));
00469   }
00470   if((BufferLength%2) != 0)
00471   {
00472      *(__IO uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i];
00473   }
00474
00475   /* Return the CRC computed value */
00476   return hcrc->Instance->DR;
00477 }
00478
00479 /**
00480   * @}
00481   */
00482
00483 /** @defgroup HAL_CRC_Group3 Peripheral State functions
00484   *  @brief    Peripheral State functions.
00485   *
00486 @verbatim
00487  ==============================================================================
00488                       ##### Peripheral State functions #####
00489  ==============================================================================
00490     [..]
00491     This subsection permits to get in run-time the status of the peripheral
00492     and the data flow.
00493
00494 @endverbatim
00495   * @{
00496   */
00497
00498 /**
00499   * @brief  Return the CRC state.
00500   * @param  hcrc: CRC handle
00501   * @retval HAL state
00502   */
00503 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
00504 {
00505   return hcrc->State;
00506 }
00507
00508 /**
00509   * @}
00510   */
00511
00512 /**
00513   * @}
00514   */
00515
00516 #endif /* HAL_CRC_MODULE_ENABLED */
00517 /**
00518   * @}
00519   */
00520
00521 /**
00522   * @}
00523   */
00524
00525 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_crc.h Source File

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stm32h7xx_hal_crc.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_crc.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of CRC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_CRC_H
00040 #define __STM32H7xx_HAL_CRC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup CRC CRC
00054   * @brief CRC HAL module driver
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup CRC_Exported_Types CRC Exported Types
00060   * @{
00061   */
00062
00063 /** @defgroup CRC_Exported_Types_Group1 CRC State Structure definition
00064   * @{
00065   */
00066 typedef enum
00067 {
00068   HAL_CRC_STATE_RESET     = 0x00U,  /*!< CRC not yet initialized or disabled */
00069   HAL_CRC_STATE_READY     = 0x01U,  /*!< CRC initialized and ready for use   */
00070   HAL_CRC_STATE_BUSY      = 0x02U,  /*!< CRC internal process is ongoing     */
00071   HAL_CRC_STATE_TIMEOUT   = 0x03U,  /*!< CRC timeout state                   */
00072   HAL_CRC_STATE_ERROR     = 0x04U   /*!< CRC error state                     */
00073 }HAL_CRC_StateTypeDef;
00074 /**
00075   * @}
00076   */
00077
00078 /** @defgroup CRC_Exported_Types_Group2 CRC Init Structure definition
00079   * @{
00080   */
00081 typedef struct
00082 {
00083   uint8_t DefaultPolynomialUse;       /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
00084                                             If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
00085                                             X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
00086                                             In that case, there is no need to set GeneratingPolynomial field.
00087                                             If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set */
00088
00089   uint8_t DefaultInitValueUse;        /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
00090                                            If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
00091                                            0xFFFFFFFF value. In that case, there is no need to set InitValue field.
00092                                            If otherwise set to DEFAULT_INIT_VALUE_DISABLE,  InitValue field must be set */
00093
00094   uint32_t GeneratingPolynomial;      /*!< Set CRC generating polynomial. 7, 8, 16 or 32-bit long value for a polynomial degree
00095                                            respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
00096                                            e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
00097                                            No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE   */
00098
00099   uint32_t CRCLength;                 /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
00100                                            Value can be either one of
00101                                            CRC_POLYLENGTH_32B                  (32-bit CRC)
00102                                            CRC_POLYLENGTH_16B                  (16-bit CRC)
00103                                            CRC_POLYLENGTH_8B                   (8-bit CRC)
00104                                            CRC_POLYLENGTH_7B                   (7-bit CRC) */
00105
00106   uint32_t InitValue;                 /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
00107                                            is set to DEFAULT_INIT_VALUE_ENABLE   */
00108
00109   uint32_t InputDataInversionMode;    /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
00110                                            Can be either one of the following values
00111                                            CRC_INPUTDATA_INVERSION_NONE      no input data inversion
00112                                            CRC_INPUTDATA_INVERSION_BYTE      byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
00113                                            CRC_INPUTDATA_INVERSION_HALFWORD  halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
00114                                            CRC_INPUTDATA_INVERSION_WORD      word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
00115
00116   uint32_t OutputDataInversionMode;   /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
00117                                             Can be either
00118                                             CRC_OUTPUTDATA_INVERSION_DISABLE   no CRC inversion, or
00119                                             CRC_OUTPUTDATA_INVERSION_ENABLE    CRC 0x11223344 is converted into 0x22CC4488 */
00120 }CRC_InitTypeDef;
00121 /**
00122   * @}
00123   */
00124
00125 /** @defgroup CRC_Exported_Types_Group3 CRC Handle Structure definition
00126   * @{
00127   */
00128 typedef struct
00129 {
00130   CRC_TypeDef                 *Instance;   /*!< Register base address        */
00131
00132   CRC_InitTypeDef             Init;        /*!< CRC configuration parameters */
00133
00134   HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */
00135
00136   __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */
00137
00138   uint32_t InputDataFormat;                /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
00139                                             Can be either
00140                                             CRC_INPUTDATA_FORMAT_BYTES       input data is a stream of bytes (8-bit data)
00141                                             CRC_INPUTDATA_FORMAT_HALFWORDS   input data is a stream of half-words (16-bit data)
00142                                             CRC_INPUTDATA_FORMAT_WORDS       input data is a stream of words (32-bits data)
00143                                            Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
00144                                            must occur if InputBufferFormat is not one of the three values listed above  */
00145 }CRC_HandleTypeDef;
00146 /**
00147   * @}
00148   */
00149
00150 /**
00151   * @}
00152   */
00153
00154 /* Exported constants --------------------------------------------------------*/
00155 /** @defgroup CRC_Exported_Constants   CRC exported constants
00156   * @{
00157   */
00158
00159 /** @defgroup CRC_Default_Polynomial_Value    Default CRC generating polynomial
00160   * @{
00161   */
00162 #define DEFAULT_CRC32_POLY      0x04C11DB7U
00163
00164 /**
00165   * @}
00166   */
00167
00168 /** @defgroup CRC_Default_InitValue    Default CRC computation initialization value
00169   * @{
00170   */
00171 #define DEFAULT_CRC_INITVALUE   0xFFFFFFFFU
00172
00173 /**
00174   * @}
00175   */
00176
00177 /** @defgroup CRC_Default_Polynomial    Indicates whether or not default polynomial is used
00178   * @{
00179   */
00180 #define DEFAULT_POLYNOMIAL_ENABLE       ((uint8_t)0x00U)
00181 #define DEFAULT_POLYNOMIAL_DISABLE      ((uint8_t)0x01U)
00182
00183
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup CRC_Default_InitValue_Use    Indicates whether or not default init value is used
00189   * @{
00190   */
00191 #define DEFAULT_INIT_VALUE_ENABLE      ((uint8_t)0x00U)
00192 #define DEFAULT_INIT_VALUE_DISABLE     ((uint8_t)0x01U)
00193
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
00199   * @{
00200   */
00201 #define CRC_POLYLENGTH_32B                  ((uint32_t)0x00000000U)
00202 #define CRC_POLYLENGTH_16B                  ((uint32_t)CRC_CR_POLYSIZE_0)
00203 #define CRC_POLYLENGTH_8B                   ((uint32_t)CRC_CR_POLYSIZE_1)
00204 #define CRC_POLYLENGTH_7B                   ((uint32_t)CRC_CR_POLYSIZE)
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
00210   * @{
00211   */
00212 #define HAL_CRC_LENGTH_32B     32U
00213 #define HAL_CRC_LENGTH_16B     16U
00214 #define HAL_CRC_LENGTH_8B       8U
00215 #define HAL_CRC_LENGTH_7B       7U
00216
00217 /**
00218   * @}
00219   */
00220
00221 /** @defgroup CRC_Input_Buffer_Format CRC input buffer format
00222   * @{
00223   */
00224 /* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
00225  * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
00226  * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
00227  * the CRC APIs to provide a correct result */
00228 #define CRC_INPUTDATA_FORMAT_UNDEFINED             ((uint32_t)0x00000000U)
00229 #define CRC_INPUTDATA_FORMAT_BYTES                 ((uint32_t)0x00000001U)
00230 #define CRC_INPUTDATA_FORMAT_HALFWORDS             ((uint32_t)0x00000002U)
00231 #define CRC_INPUTDATA_FORMAT_WORDS                 ((uint32_t)0x00000003U)
00232 /**
00233   * @}
00234   */
00235
00236 /**
00237   * @}
00238   */
00239 /* Exported macros -----------------------------------------------------------*/
00240
00241 /** @defgroup CRC_Exported_Macros CRC exported macros
00242   * @{
00243   */
00244
00245 /** @brief Reset CRC handle state
00246   * @param  __HANDLE__: CRC handle.
00247   * @retval None
00248   */
00249 #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
00250
00251 /**
00252   * @brief  Reset CRC Data Register.
00253   * @param  __HANDLE__: CRC handle
00254   * @retval None.
00255   */
00256 #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
00257
00258 /**
00259   * @brief  Set CRC INIT non-default value
00260   * @param  __HANDLE__    : CRC handle
00261   * @param  __INIT__      : 32-bit initial value
00262   * @retval None.
00263   */
00264 #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
00265
00266 /**
00267   * @brief Stores a 32-bit data in the Independent Data(ID) register.
00268   * @param __HANDLE__: CRC handle
00269   * @param __VALUE__: 32-bit value to be stored in the ID register
00270   * @retval None
00271   */
00272 #define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
00273
00274 /**
00275   * @brief Returns the 32-bit data stored in the Independent Data(ID) register.
00276   * @param __HANDLE__: CRC handle
00277   * @retval 32-bit value of the ID register
00278   */
00279 #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
00280 /**
00281   * @}
00282   */
00283
00284
00285 /* Include CRC HAL Extension module */
00286 #include "stm32h7xx_hal_crc_ex.h"
00287
00288 /* Exported functions --------------------------------------------------------*/
00289 /** @defgroup CRC_Exported_Functions CRC Exported Functions
00290   * @{
00291   */
00292
00293 /** @defgroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions
00294   * @{
00295   */
00296 /* Initialization and de-initialization functions  ****************************/
00297 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
00298 HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
00299 void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
00300 void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
00301 /**
00302   * @}
00303   */
00304
00305 /* Aliases for inter STM32 series compatibility */
00306 #define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse
00307 #define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse
00308
00309 /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
00310   * @{
00311   */
00312 /* Peripheral Control functions ***********************************************/
00313 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
00314 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
00320   * @{
00321   */
00322 /* Peripheral State and Error functions ***************************************/
00323 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
00324 /**
00325   * @}
00326   */
00327
00328 /**
00329   * @}
00330   */
00331
00332
00333 /* Private types -------------------------------------------------------------*/
00334 /** @defgroup CRC_Private_Types CRC Private Types
00335   * @{
00336   */
00337
00338 /**
00339   * @}
00340   */
00341
00342 /* Private defines -----------------------------------------------------------*/
00343 /** @defgroup CRC_Private_Defines CRC Private Defines
00344   * @{
00345   */
00346
00347 /**
00348   * @}
00349   */
00350
00351 /* Private variables ---------------------------------------------------------*/
00352 /** @defgroup CRC_Private_Variables CRC Private Variables
00353   * @{
00354   */
00355
00356 /**
00357   * @}
00358   */
00359
00360 /* Private constants ---------------------------------------------------------*/
00361 /** @defgroup CRC_Private_Constants CRC Private Constants
00362   * @{
00363   */
00364
00365 /**
00366   * @}
00367   */
00368
00369 /* Private macros ------------------------------------------------------------*/
00370 /** @defgroup CRC_Private_Macros CRC Private Macros
00371   * @{
00372   */
00373 #define IS_DEFAULT_POLYNOMIAL(__DEFAULT__) (((__DEFAULT__) == DEFAULT_POLYNOMIAL_ENABLE) || \
00374                                             ((__DEFAULT__) == DEFAULT_POLYNOMIAL_DISABLE))
00375 #define IS_DEFAULT_INIT_VALUE(__VALUE__)  (((__VALUE__) == DEFAULT_INIT_VALUE_ENABLE) || \
00376                                            ((__VALUE__) == DEFAULT_INIT_VALUE_DISABLE))
00377 #define IS_CRC_POL_LENGTH(__LENGTH__)     (((__LENGTH__) == CRC_POLYLENGTH_32B) || \
00378                                            ((__LENGTH__) == CRC_POLYLENGTH_16B) || \
00379                                            ((__LENGTH__) == CRC_POLYLENGTH_8B)  || \
00380                                            ((__LENGTH__) == CRC_POLYLENGTH_7B))
00381 #define IS_CRC_INPUTDATA_FORMAT(__FORMAT__)       (((__FORMAT__) == CRC_INPUTDATA_FORMAT_BYTES) || \
00382                                                    ((__FORMAT__) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
00383                                                    ((__FORMAT__) == CRC_INPUTDATA_FORMAT_WORDS))
00384
00385
00386 /**
00387   * @}
00388   */
00389
00390 /* Private functions prototypes ----------------------------------------------*/
00391 /** @defgroup CRC_Private_Functions_Prototypes CRC Private Functions Prototypes
00392   * @{
00393   */
00394
00395 /**
00396   * @}
00397   */
00398
00399 /* Private functions ---------------------------------------------------------*/
00400 /** @defgroup CRC_Private_Functions CRC Private Functions
00401   * @{
00402   */
00403
00404 /**
00405   * @}
00406   */
00407
00408 /**
00409   * @}
00410   */
00411
00412 /**
00413   * @}
00414   */
00415
00416 #ifdef __cplusplus
00417 }
00418 #endif
00419
00420 #endif /* __STM32H7xx_HAL_CRC_H */
00421
00422 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00423
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_crc_ex.c Source File

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stm32h7xx_hal_crc_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_crc_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Extended CRC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the CRC peripheral:
00010   *           + Initialization/de-initialization functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                     ##### CRC specific features #####
00015   ==============================================================================
00016   [..]
00017   (#) Polynomial configuration.
00018   (#) Input data reverse mode.
00019   (#) Output data reverse mode.
00020
00021   @endverbatim
00022   ******************************************************************************
00023   * @attention
00024   *
00025   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00026   *
00027   * Redistribution and use in source and binary forms, with or without modification,
00028   * are permitted provided that the following conditions are met:
00029   *   1. Redistributions of source code must retain the above copyright notice,
00030   *      this list of conditions and the following disclaimer.
00031   *   2. Redistributions in binary form must reproduce the above copyright notice,
00032   *      this list of conditions and the following disclaimer in the documentation
00033   *      and/or other materials provided with the distribution.
00034   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00035   *      may be used to endorse or promote products derived from this software
00036   *      without specific prior written permission.
00037   *
00038   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00039   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00040   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00041   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00042   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00043   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00044   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00045   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00046   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00047   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00048   *
00049   ******************************************************************************
00050   */
00051
00052 /* Includes ------------------------------------------------------------------*/
00053 #include "stm32h7xx_hal.h"
00054
00055 /** @addtogroup STM32H7xx_HAL_Driver
00056   * @{
00057   */
00058
00059 /** @addtogroup CRCEx
00060   * @brief CRC Extended HAL module driver
00061   * @{
00062   */
00063
00064 #ifdef HAL_CRC_MODULE_ENABLED
00065
00066 /* Private typedef -----------------------------------------------------------*/
00067 /* Private define ------------------------------------------------------------*/
00068 /* Private macro -------------------------------------------------------------*/
00069 /* Private variables ---------------------------------------------------------*/
00070 /* Private function prototypes -----------------------------------------------*/
00071 /* Private functions ---------------------------------------------------------*/
00072
00073 /** @addtogroup CRCEx_Exported_Functions
00074   * @{
00075   */
00076
00077 /** @addtogroup CRCEx_Exported_Functions_Group1
00078  *  @brief    Extended CRC features functions
00079  *
00080 @verbatim
00081  ===============================================================================
00082             ##### CRC Extended features functions #####
00083  ===============================================================================
00084     [..]
00085 This subsection provides function allowing to:
00086       (+) Set CRC polynomial if different from default one.
00087
00088 @endverbatim
00089   * @{
00090   */
00091
00092
00093 /**
00094   * @brief  Initializes the CRC polynomial if different from default one.
00095   * @param  hcrc: CRC handle
00096   * @param  Pol: CRC generating polynomial (7, 8, 16 or 32-bit long)
00097   *         This parameter is written in normal representation, e.g.
00098   *         for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
00099   *         for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
00100   * @param  PolyLength: CRC polynomial length
00101   *         This parameter can be one of the following values:
00102   *          @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)
00103   *          @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)
00104   *          @arg CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16)
00105   *          @arg CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32)
00106   * @retval HAL status
00107   */
00108 HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
00109 {
00110   uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */
00111
00112   /* Check the parameters */
00113   assert_param(IS_CRC_POL_LENGTH(PolyLength));
00114
00115   /* check polynomial definition vs polynomial size:
00116    * polynomial length must be aligned with polynomial
00117    * definition. HAL_ERROR is reported if Pol degree is
00118    * larger than that indicated by PolyLength.
00119    * Look for MSB position: msb will contain the degree of
00120    *  the second to the largest polynomial member. E.g., for
00121    *  X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
00122   while (((Pol & ((uint32_t)(0x1) << msb)) == 0) && (msb-- > 0))
00123   {
00124   }
00125
00126   switch (PolyLength)
00127   {
00128     case CRC_POLYLENGTH_7B:
00129       if (msb >= HAL_CRC_LENGTH_7B)
00130       {
00131         return  HAL_ERROR;
00132       }
00133       break;
00134     case CRC_POLYLENGTH_8B:
00135       if (msb >= HAL_CRC_LENGTH_8B)
00136       {
00137         return  HAL_ERROR;
00138       }
00139       break;
00140     case CRC_POLYLENGTH_16B:
00141       if (msb >= HAL_CRC_LENGTH_16B)
00142       {
00143         return  HAL_ERROR;
00144       }
00145       break;
00146     case CRC_POLYLENGTH_32B:
00147       /* no polynomial definition vs. polynomial length issue possible */
00148       break;
00149     default:
00150       return HAL_ERROR;
00151   }
00152
00153   /* set generating polynomial */
00154   WRITE_REG(hcrc->Instance->POL, Pol);
00155
00156   /* set generating polynomial size */
00157   MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
00158
00159   /* Return function status */
00160   return HAL_OK;
00161 }
00162
00163 /**
00164   * @brief  Set the Reverse Input data mode.
00165   * @param  hcrc: CRC handle
00166   * @param  InputReverseMode: Input Data inversion mode
00167   *         This parameter can be one of the following values:
00168   *          @arg CRC_INPUTDATA_INVERSION_NONE: no change in bit order (default value)
00169   *          @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal
00170   *          @arg CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal
00171   *          @arg CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal
00172   * @retval HAL status
00173   */
00174 HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
00175 {
00176   /* Check the parameters */
00177   assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
00178
00179   /* Change CRC peripheral state */
00180   hcrc->State = HAL_CRC_STATE_BUSY;
00181
00182   /* set input data inversion mode */
00183   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
00184   /* Change CRC peripheral state */
00185   hcrc->State = HAL_CRC_STATE_READY;
00186
00187   /* Return function status */
00188   return HAL_OK;
00189 }
00190
00191 /**
00192   * @brief  Set the Reverse Output data mode.
00193   * @param  hcrc: CRC handle
00194   * @param  OutputReverseMode: Output Data inversion mode
00195   *         This parameter can be one of the following values:
00196   *          @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)
00197   *          @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD)
00198   * @retval HAL status
00199   */
00200 HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
00201 {
00202   /* Check the parameters */
00203   assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
00204
00205   /* Change CRC peripheral state */
00206   hcrc->State = HAL_CRC_STATE_BUSY;
00207
00208   /* set output data inversion mode */
00209   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
00210
00211   /* Change CRC peripheral state */
00212   hcrc->State = HAL_CRC_STATE_READY;
00213
00214   /* Return function status */
00215   return HAL_OK;
00216 }
00217
00218
00219
00220
00221 /**
00222   * @}
00223   */
00224
00225
00226 /**
00227   * @}
00228   */
00229
00230
00231 #endif /* HAL_CRC_MODULE_ENABLED */
00232 /**
00233   * @}
00234   */
00235
00236 /**
00237   * @}
00238   */
00239
00240 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00241
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_crc_ex.h Source File

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stm32h7xx_hal_crc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_crc_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of CRC HAL extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_CRC_EX_H
00040 #define __STM32H7xx_HAL_CRC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup CRCEx CRCEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059
00060 /** @defgroup CRCEx_Exported_Constants CRC Extended exported constants
00061  * @{
00062  */
00063
00064 /** @defgroup CRCEx_Input_Data_Inversion CRC Extended input data inversion modes
00065   * @{
00066   */
00067 #define CRC_INPUTDATA_INVERSION_NONE              ((uint32_t)0x00000000U)
00068 #define CRC_INPUTDATA_INVERSION_BYTE              ((uint32_t)CRC_CR_REV_IN_0)
00069 #define CRC_INPUTDATA_INVERSION_HALFWORD          ((uint32_t)CRC_CR_REV_IN_1)
00070 #define CRC_INPUTDATA_INVERSION_WORD              ((uint32_t)CRC_CR_REV_IN)
00071
00072 #define IS_CRC_INPUTDATA_INVERSION_MODE(__MODE__)     (((__MODE__) == CRC_INPUTDATA_INVERSION_NONE) || \
00073                                                        ((__MODE__) == CRC_INPUTDATA_INVERSION_BYTE) || \
00074                                                        ((__MODE__) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
00075                                                        ((__MODE__) == CRC_INPUTDATA_INVERSION_WORD))
00076 /**
00077   * @}
00078   */
00079
00080 /** @defgroup CRCEx_Output_Data_Inversion CRC Extended output data inversion modes
00081   * @{
00082   */
00083 #define CRC_OUTPUTDATA_INVERSION_DISABLE         ((uint32_t)0x00000000U)
00084 #define CRC_OUTPUTDATA_INVERSION_ENABLE          ((uint32_t)CRC_CR_REV_OUT)
00085
00086 #define IS_CRC_OUTPUTDATA_INVERSION_MODE(__MODE__)    (((__MODE__) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
00087                                                        ((__MODE__) == CRC_OUTPUTDATA_INVERSION_ENABLE))
00088 /**
00089   * @}
00090   */
00091
00092
00093 /**
00094  * @}
00095  */
00096 /* Exported macro ------------------------------------------------------------*/
00097
00098 /** @defgroup CRCEx_Exported_Macros CRC Extended exported macros
00099   * @{
00100   */
00101
00102 /**
00103   * @brief  Set CRC output reversal
00104   * @param  __HANDLE__    : CRC handle
00105   * @retval None.
00106   */
00107 #define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
00108
00109 /**
00110   * @brief  Unset CRC output reversal
00111   * @param  __HANDLE__    : CRC handle
00112   * @retval None.
00113   */
00114 #define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
00115
00116 /**
00117   * @brief  Set CRC non-default polynomial
00118   * @param  __HANDLE__    : CRC handle
00119   * @param  __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial
00120   * @retval None.
00121   */
00122 #define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
00123
00124 /**
00125   * @}
00126   */
00127
00128
00129 /** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
00130   * @{
00131   */
00132
00133 /** @defgroup CRCEx_Exported_Functions_Group1 Extended CRC features functions
00134   * @{
00135   */
00136 /* Exported functions --------------------------------------------------------*/
00137 /* Initialization and de-initialization functions  ****************************/
00138 HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
00139 HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
00140 HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
00141
00142 /* Peripheral Control functions ***********************************************/
00143 /* Peripheral State and Error functions ***************************************/
00144
00145 /**
00146   * @}
00147   */
00148
00149 /**
00150   * @}
00151   */
00152
00153
00154 /**
00155   * @}
00156   */
00157
00158 /**
00159   * @}
00160   */
00161
00162 #ifdef __cplusplus
00163 }
00164 #endif
00165
00166 #endif /* __STM32H7xx_HAL_CRC_EX_H */
00167
00168 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_cryp.c Source File

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stm32h7xx_hal_cryp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_cryp.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   CRYP HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Cryptography (CRYP) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + AES processing functions
00012   *           + DES processing functions
00013   *           + TDES processing functions
00014   *           + DMA callback functions
00015   *           + CRYP IRQ handler management
00016   *           + Peripheral State functions
00017   *
00018   @verbatim
00019   ==============================================================================
00020                      ##### How to use this driver #####
00021   ==============================================================================
00022     [..]
00023       The CRYP HAL driver can be used in CRYP IP as follows:
00024
00025       (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
00026          (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
00027          (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
00028              (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
00029              (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
00030              (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
00031          (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
00032              (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
00033              (+++) Configure and enable two DMA streams one for managing data transfer from
00034                  memory to peripheral (input stream) and another stream for managing data
00035                  transfer from peripheral to memory (output stream)
00036              (+++) Associate the initialized DMA handle to the CRYP DMA handle
00037                  using  __HAL_LINKDMA()
00038              (+++) Configure the priority and enable the NVIC for the transfer complete
00039                  interrupt on the two DMA Streams. The output stream should have higher
00040                  priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
00041
00042       (#)Initialize the CRYP according to the specified parameters :
00043          (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
00044          (##) The key size: 128, 192 or 256.
00045          (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM.
00046          (##) The initialization vector (counter). It is not used in ECB mode.
00047          (##) The key buffer used for encryption/decryption.
00048          (##) The Header used only in AES GCM and CCM Algorithm for authentication.
00049          (##) The HeaderSize The size of header buffer in word.
00050          (##) The B0 block is the first authentication block used only  in AES CCM mode.
00051
00052       (#)Three processing (encryption/decryption) functions are available:
00053          (##) Polling mode: encryption and decryption APIs are blocking functions
00054               i.e. they process the data and wait till the processing is finished,
00055               e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
00056          (##) Interrupt mode: encryption and decryption APIs are not blocking functions
00057               i.e. they process the data under interrupt,
00058               e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
00059          (##) DMA mode: encryption and decryption APIs are not blocking functions
00060               i.e. the data transfer is ensured by DMA,
00061               e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
00062
00063       (#)When the processing function is called at first time after HAL_CRYP_Init()
00064          the CRYP peripheral is configured and processes the buffer in input.
00065          At second call, no need to Initialize the CRYP, user have to get current configuration via
00066          HAL_CRYP_GetConfig() API, then only  HAL_CRYP_SetConfig() is requested to set
00067          new parametres, finally user can  start encryption/decryption.
00068
00069        (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
00070
00071     [..]
00072       The cryptographic processor supports following standards:
00073       (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP:
00074          (##)64-bit data block processing
00075          (##) chaining modes supported :
00076              (+++)  Electronic Code Book(ECB)
00077              (+++)  Cipher Block Chaining (CBC)
00078          (##) keys length supported :64-bit, 128-bit and 192-bit.
00079       (#) The advanced encryption standard (AES) supported  by CRYP1:
00080          (##)128-bit data block processing
00081          (##) chaining modes supported :
00082              (+++)  Electronic Code Book(ECB)
00083              (+++)  Cipher Block Chaining (CBC)
00084              (+++)  Counter mode (CTR)
00085              (+++)  Galois/counter mode (GCM/GMAC)
00086              (+++)  Counter with Cipher Block Chaining-Message(CCM)
00087          (##) keys length Supported :
00088              (+++) for CRYP1 IP: 128-bit, 192-bit and 256-bit.
00089
00090     [..]  This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 IP:
00091       (#)  Algorithm supported :
00092          (##) Galois/counter mode (GCM)
00093          (##) Galois message authentication code (GMAC) :is exactly the same as
00094               GCM algorithm composed only by an header.
00095       (#)  Four phases are performed in GCM :
00096          (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
00097          (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
00098           computation only.
00099          (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
00100           encryption + data XORing. It works in a similar way for ciphertext (C).
00101          (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
00102       (#)  structure of message construction in GCM is defined as below  :
00103          (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
00104          (##) The authenticated header A (also knows as Additional Authentication Data AAD)
00105           this part of the message is only authenticated, not encrypted.
00106          (##) The plaintext message P is both authenticated and encrypted as ciphertext.
00107           GCM standard specifies that ciphertext has same bit length as the plaintext.
00108          (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
00109           (on 64 bits)
00110
00111     [..]  This section describe The AES Counter with Cipher Block Chaining-Message
00112           Authentication Code (CCM) supported by both CRYP1 IP:
00113       (#)  Specific parameters for CCM  :
00114
00115          (##) B0 block  : According to NIST Special Publication 800-38C,
00116             The first block B0 is formatted as follows, where l(m) is encoded in
00117             most-significant-byte first order(see below table 3)
00118
00119               (+++)  Q: a bit string representation of the octet length of P (plaintext)
00120               (+++)  q The octet length of the binary representation of the octet length of the payload
00121               (+++)  A nonce (N), n The octet length of the where n+q=15.
00122               (+++)  Flags: most significant octet containing four flags for control information,
00123               (+++)  t The octet length of the MAC.
00124          (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
00125               the associated data length expressed in bytes (a) defined as below:
00126             (+++)  If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
00127             (+++)  If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
00128             (+++)  If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
00129          (##) CTRx block  : control blocks
00130             (+++) Generation of CTR1 from first block B0 information :
00131               equal to B0 with first 5 bits zeroed and most significant bits storing octet
00132               length of P also zeroed, then incremented by one ( see below Table 4)
00133             (+++) Generation of CTR0: same as CTR1 with bit[0] set to zero.
00134
00135       (#)  Four phases are performed in CCM for CRYP1 IP:
00136          (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
00137          (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
00138           computation only.
00139          (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
00140           encryption + data XORing. It works in a similar way for ciphertext (C).
00141          (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
00142
00143   @endverbatim
00144
00145   Table 1. Initial Counter Block (ICB)
00146           +-------------------------------------------------------+
00147           |       Initialization vector (IV)      |  Counter      |
00148           |----------------|----------------|-----------|---------|
00149          127              95                63            31       0
00150
00151
00152               Bit Number    Register           Contents
00153               ----------   ---------------       -----------
00154               127 ...96    CRYP_IV1R[31:0]     ICB[127:96]
00155               95  ...64    CRYP_IV1L[31:0]     B0[95:64]
00156               63 ... 32    CRYP_IV0R[31:0]     ICB[63:32]
00157               31 ... 0     CRYP_IV0L[31:0]     ICB[31:0], where 32-bit counter= 0x2
00158
00159   Table 2.  GCM last block definition
00160
00161           +-------------------------------------------------------------------+
00162           |  Bit[0]   |  Bit[32]           |  Bit[64]  | Bit[96]              |
00163           |-----------|--------------------|-----------|----------------------|
00164           |   0x0     | Header length[31:0]|     0x0   | Payload length[31:0] |
00165           |-----------|--------------------|-----------|----------------------|
00166
00167   Table 3. B0 block
00168                 Octet Number   Contents
00169                 ------------   ---------
00170                 0              Flags
00171                 1 ... 15-q     Nonce N
00172                 16-q ... 15    Q
00173
00174             the Flags field is formatted as follows:
00175
00176                 Bit Number   Contents
00177                 ----------   ----------------------
00178                 7            Reserved (always zero)
00179                 6            Adata
00180                 5 ... 3      (t-2)/2
00181                 2 ... 0      [q-1]3
00182
00183  Table 4. CTRx block
00184                 Bit Number    Register           Contents
00185                 ----------   ---------------       -----------
00186                 127 ...96    CRYP_IV1R[31:0]     B0[127:96], where Q length bits are set to 0, except for
00187                                                  bit 0 that is set to 1
00188                 95  ...64    CRYP_IV1L[31:0]     B0[95:64]
00189                 63 ... 32    CRYP_IV0R[31:0]     B0[63:32]
00190                 31 ... 0     CRYP_IV0L[31:0]     B0[31:0], where flag bits set to 0
00191
00192
00193   ******************************************************************************
00194   * @attention
00195   *
00196   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00197   *
00198   * Redistribution and use in source and binary forms, with or without modification,
00199   * are permitted provided that the following conditions are met:
00200   *   1. Redistributions of source code must retain the above copyright notice,
00201   *      this list of conditions and the following disclaimer.
00202   *   2. Redistributions in binary form must reproduce the above copyright notice,
00203   *      this list of conditions and the following disclaimer in the documentation
00204   *      and/or other materials provided with the distribution.
00205   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00206   *      may be used to endorse or promote products derived from this software
00207   *      without specific prior written permission.
00208   *
00209   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00210   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00211   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00212   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00213   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00214   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00215   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00216   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00217   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00218   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00219   *
00220   ******************************************************************************
00221   */
00222
00223 /* Includes ------------------------------------------------------------------*/
00224 #include "stm32h7xx_hal.h"
00225
00226 /** @addtogroup STM32H7xx_HAL_Driver
00227   * @{
00228   */
00229
00230 #if defined (CRYP)
00231
00232 /** @defgroup CRYP CRYP
00233   * @brief CRYP HAL module driver.
00234   * @{
00235   */
00236
00237
00238 #ifdef HAL_CRYP_MODULE_ENABLED
00239
00240 /* Private typedef -----------------------------------------------------------*/
00241 /* Private define ------------------------------------------------------------*/
00242 /** @addtogroup CRYP_Private_Defines
00243   * @{
00244   */
00245 #define CRYP_TIMEOUT_KEYPREPARATION      82U         /*The latency of key preparation operation is 82 clock cycles.*/
00246 #define CRYP_TIMEOUT_GCMCCMINITPHASE     299U        /*  The latency of  GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
00247 #define CRYP_TIMEOUT_GCMCCMHEADERPHASE   290U        /*  The latency of  GCM/CCM header phase is 290 clock cycles.*/
00248
00249 #define  CRYP_PHASE_READY                0x00000001U /*!< CRYP peripheral is ready for initialization. */
00250 #define  CRYP_PHASE_PROCESS              0x00000002U /*!< CRYP peripheral is in processing phase */
00251
00252 #define CRYP_PHASE_INIT                  0x00000000U             /*!< GCM/GMAC (or CCM) init phase */
00253 #define CRYP_PHASE_HEADER                CRYP_CR_GCM_CCMPH_0     /*!< GCM/GMAC or CCM header phase */
00254 #define CRYP_PHASE_PAYLOAD               CRYP_CR_GCM_CCMPH_1     /*!< GCM(/CCM) payload phase      */
00255 #define CRYP_PHASE_FINAL                 CRYP_CR_GCM_CCMPH       /*!< GCM/GMAC or CCM  final phase */
00256 #define CRYP_OPERATINGMODE_ENCRYPT       0x00000000U             /*!< Encryption mode   */
00257 #define CRYP_OPERATINGMODE_DECRYPT       CRYP_CR_ALGODIR         /*!< Decryption        */
00258
00259
00260  /*  CTR1 information to use in CCM algorithm */
00261 #define CRYP_CCM_CTR1_0                  0x07FFFFFFU
00262 #define CRYP_CCM_CTR1_1                  0xFFFFFF00U
00263 #define CRYP_CCM_CTR1_2                  0x00000001U
00264
00265
00266 /**
00267   * @}
00268   */
00269
00270
00271 /* Private macro -------------------------------------------------------------*/
00272 /** @addtogroup CRYP_Private_Macros
00273   * @{
00274   */
00275
00276 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__)  do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
00277                                                         (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
00278                                                        }while(0)
00279
00280 #define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |=  CRYP_CR_FFLUSH)
00281
00282
00283 /**
00284   * @}
00285   */
00286
00287 /* Private struct -------------------------------------------------------------*/
00288 /* Private variables ---------------------------------------------------------*/
00289 /* Private function prototypes -----------------------------------------------*/
00290 /** @addtogroup CRYP_Private_Functions_prototypes
00291   * @{
00292   */
00293
00294 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
00295 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
00296 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
00297 static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
00298 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t *Key, uint32_t KeySize);
00299 static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
00300 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00301 static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
00302 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
00303 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
00304 static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00305 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
00306 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT (CRYP_HandleTypeDef *hcryp);
00307 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00308 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00309 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
00310 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
00311 static HAL_StatusTypeDef CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
00312 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00313 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00314 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
00315 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
00316 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
00317 static HAL_StatusTypeDef CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp);
00318 static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00319 static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00320 static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00321 static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00322
00323 /**
00324   * @}
00325   */
00326
00327 /* Exported functions ---------------------------------------------------------*/
00328
00329 /** @defgroup CRYP_Exported_Functions CRYP Exported Functions
00330   * @{
00331   */
00332
00333
00334 /** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
00335  *  @brief    CRYP  Initialization and Configuration functions.
00336  *
00337 @verbatim
00338   ========================================================================================
00339      ##### Initialization, de-initialization and Set and Get configuration functions #####
00340   ========================================================================================
00341     [..]  This section provides functions allowing to:
00342       (+) Initialize the CRYP
00343       (+) DeInitialize the CRYP
00344       (+) Initialize the CRYP MSP
00345       (+) DeInitialize the CRYP MSP
00346       (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
00347           Parameters which are configured in This section are :
00348           (++) Key size
00349           (++) Data Type : 32,16, 8 or 1bit
00350           (++) AlgoMode : for CRYP1 IP
00351                  ECB and CBC in DES/TDES Standard
00352                  ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
00353       (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
00354
00355
00356 @endverbatim
00357   * @{
00358   */
00359
00360
00361 /**
00362   * @brief  Initializes the CRYP according to the specified
00363   *         parameters in the CRYP_ConfigTypeDef and creates the associated handle.
00364   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00365   *         the configuration information for CRYP module
00366   * @retval HAL status
00367   */
00368 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
00369 {
00370   /* Check the CRYP handle allocation */
00371   if(hcryp == NULL)
00372   {
00373     return HAL_ERROR;
00374   }
00375
00376   /* Check parameters */
00377   assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
00378   assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
00379   assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
00380
00381   if(hcryp->State == HAL_CRYP_STATE_RESET)
00382   {
00383     /* Allocate lock resource and initialize it */
00384     hcryp->Lock = HAL_UNLOCKED;
00385
00386     /* Init the low level hardware */
00387     HAL_CRYP_MspInit(hcryp);
00388   }
00389
00390   /* Set the key size(This bit field is ‘don’t care’ in the DES or TDES modes) data type and Algorithm */
00391   MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
00392
00393   /* Reset Error Code field */
00394   hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
00395
00396   /* Change the CRYP state */
00397   hcryp->State = HAL_CRYP_STATE_READY;
00398
00399   /* Set the default CRYP phase */
00400   hcryp->Phase = CRYP_PHASE_READY;
00401
00402   /* Return function status */
00403   return HAL_OK;
00404 }
00405
00406 /**
00407   * @brief  De-Initializes the CRYP peripheral.
00408   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00409   *         the configuration information for CRYP module
00410   * @retval HAL status
00411 */
00412 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
00413 {
00414   /* Check the CRYP handle allocation */
00415   if(hcryp == NULL)
00416   {
00417     return HAL_ERROR;
00418   }
00419
00420   /* Set the default CRYP phase */
00421   hcryp->Phase = CRYP_PHASE_READY;
00422
00423   /* Reset CrypInCount and CrypOutCount */
00424   hcryp->CrypInCount = 0;
00425   hcryp->CrypOutCount = 0;
00426   hcryp->CrypHeaderCount =0;
00427
00428   /* Disable the CRYP peripheral clock */
00429   __HAL_CRYP_DISABLE(hcryp);
00430
00431   /* DeInit the low level hardware: CLOCK, NVIC.*/
00432   HAL_CRYP_MspDeInit(hcryp);
00433
00434   /* Change the CRYP state */
00435   hcryp->State = HAL_CRYP_STATE_RESET;
00436
00437   /* Release Lock */
00438   __HAL_UNLOCK(hcryp);
00439
00440   /* Return function status */
00441   return HAL_OK;
00442 }
00443
00444 /**
00445   * @brief  Configure the CRYP according to the specified
00446   *         parameters in the CRYP_ConfigTypeDef
00447   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure
00448   * @param  pConf: pointer to a CRYP_ConfigTypeDef structure that contains
00449   *         the configuration information for CRYP module
00450   * @retval HAL status
00451   */
00452 HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf )
00453 {
00454   /* Check the CRYP handle allocation */
00455   if((hcryp == NULL)|| (pConf == NULL) )
00456   {
00457     return HAL_ERROR;
00458   }
00459
00460   /* Check parameters */
00461   assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
00462   assert_param(IS_CRYP_DATATYPE(pConf->DataType));
00463   assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
00464
00465   if(hcryp->State == HAL_CRYP_STATE_READY)
00466   {
00467     /* Change the CRYP state */
00468     hcryp->State = HAL_CRYP_STATE_BUSY;
00469
00470     /* Process locked */
00471     __HAL_LOCK(hcryp);
00472
00473     /* Set  CRYP parameters  */
00474     hcryp->Init.DataType   = pConf->DataType;
00475     hcryp->Init.pKey       = pConf->pKey;
00476     hcryp->Init.Algorithm  = pConf->Algorithm;
00477     hcryp->Init.KeySize    = pConf->KeySize;
00478     hcryp->Init.pInitVect  = pConf->pInitVect;
00479     hcryp->Init.Header     = pConf->Header;
00480     hcryp->Init.HeaderSize = pConf->HeaderSize;
00481     hcryp->Init.B0         = pConf->B0;
00482
00483     /* Set the key size(This bit field is ‘don’t care’ in the DES or TDES modes) data type, AlgoMode and operating mode*/
00484     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
00485
00486     /* Process Unlocked */
00487     __HAL_UNLOCK(hcryp);
00488
00489     /* Reset Error Code field */
00490     hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
00491
00492     /* Change the CRYP state */
00493     hcryp->State = HAL_CRYP_STATE_READY;
00494
00495     /* Set the default CRYP phase */
00496     hcryp->Phase = CRYP_PHASE_READY;
00497
00498     /* Return function status */
00499     return HAL_OK;
00500   }
00501   else
00502   {
00503     /* Process Unlocked */
00504     __HAL_UNLOCK(hcryp);
00505
00506     /* Busy error code field */
00507     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
00508     return HAL_ERROR;
00509   }
00510 }
00511
00512 /**
00513   * @brief  Get CRYP Configuration parameters in associated handle.
00514   * @param  pConf: pointer to a CRYP_ConfigTypeDef structure
00515   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00516   *         the configuration information for CRYP module
00517   * @retval HAL status
00518   */
00519 HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf )
00520 {
00521   /* Check the CRYP handle allocation */
00522   if((hcryp == NULL)|| (pConf == NULL) )
00523   {
00524     return HAL_ERROR;
00525   }
00526
00527   if(hcryp->State == HAL_CRYP_STATE_READY)
00528   {
00529     /* Change the CRYP state */
00530     hcryp->State = HAL_CRYP_STATE_BUSY;
00531
00532     /* Process locked */
00533     __HAL_LOCK(hcryp);
00534
00535     /* Get  CRYP parameters  */
00536     pConf->DataType        = hcryp->Init.DataType;
00537     pConf->pKey            = hcryp->Init.pKey;
00538     pConf->Algorithm       = hcryp->Init.Algorithm;
00539     pConf->KeySize         = hcryp->Init.KeySize ;
00540     pConf->pInitVect       = hcryp->Init.pInitVect;
00541     pConf->Header          = hcryp->Init.Header ;
00542     pConf->HeaderSize      = hcryp->Init.HeaderSize;
00543     pConf->B0              = hcryp->Init.B0;
00544
00545     /* Process Unlocked */
00546     __HAL_UNLOCK(hcryp);
00547
00548     /* Change the CRYP state */
00549     hcryp->State = HAL_CRYP_STATE_READY;
00550
00551     /* Return function status */
00552     return HAL_OK;
00553   }
00554   else
00555   {
00556     /* Process Unlocked */
00557     __HAL_UNLOCK(hcryp);
00558
00559     /* Busy error code field */
00560     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
00561     return HAL_ERROR;
00562   }
00563 }
00564 /**
00565   * @brief  Initializes the CRYP MSP.
00566   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00567   *         the configuration information for CRYP module
00568   * @retval None
00569   */
00570 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
00571 {
00572   /* Prevent unused argument(s) compilation warning */
00573   UNUSED(hcryp);
00574
00575   /* NOTE : This function Should not be modified, when the callback is needed,
00576             the HAL_CRYP_MspInit could be implemented in the user file
00577    */
00578 }
00579
00580 /**
00581   * @brief  DeInitializes CRYP MSP.
00582   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00583   *         the configuration information for CRYP module
00584   * @retval None
00585   */
00586 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
00587 {
00588   /* Prevent unused argument(s) compilation warning */
00589   UNUSED(hcryp);
00590
00591   /* NOTE : This function Should not be modified, when the callback is needed,
00592             the HAL_CRYP_MspDeInit could be implemented in the user file
00593    */
00594 }
00595
00596 /**
00597   * @}
00598   */
00599
00600 /** @defgroup CRYP_Exported_Functions_Group2  Encrypt Decrypt functions
00601  *  @brief   CRYP processing functions.
00602  *
00603 @verbatim
00604   ==============================================================================
00605                       ##### Encrypt Decrypt  functions #####
00606   ==============================================================================
00607     [..]  This section provides API allowing to Encrypt/Decrypt Data following
00608           Standard DES/TDES or AES, and Algorithm configured by the user:
00609       (+) Standard DES/TDES only supported by CRYP1 IP, below list of Algorithm supported :
00610            (++)  Electronic Code Book(ECB)
00611            (++) Cipher Block Chaining (CBC)
00612       (+) Standard AES  supported by CRYP1 IP , list of Algorithm supported:
00613            (++) Electronic Code Book(ECB)
00614            (++) Cipher Block Chaining (CBC)
00615            (++) Counter mode (CTR)
00616            (++) Cipher Block Chaining (CBC)
00617            (++) Counter mode (CTR)
00618            (++) Galois/counter mode (GCM)
00619            (++) Counter with Cipher Block Chaining-Message(CCM)
00620     [..]  Three processing functions are available:
00621       (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
00622       (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
00623       (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
00624
00625 @endverbatim
00626   * @{
00627   */
00628
00629
00630 /**
00631   * @brief  Encryption mode.
00632   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00633   *         the configuration information for CRYP module
00634   * @param  Input: Pointer to the input buffer (plaintext)
00635   * @param  Size: Length of the plaintext buffer in word.
00636   * @param  Output: Pointer to the output buffer(ciphertext)
00637   * @param  Timeout: Specify Timeout value
00638   * @retval HAL status
00639   */
00640 HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
00641 {
00642   uint32_t algo = 0U;
00643   HAL_StatusTypeDef state;
00644
00645   if(hcryp->State == HAL_CRYP_STATE_READY)
00646   {
00647     /* Change state Busy */
00648     hcryp->State = HAL_CRYP_STATE_BUSY;
00649
00650     /* Process locked */
00651     __HAL_LOCK(hcryp);
00652
00653     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
00654     hcryp->CrypInCount = 0U;
00655     hcryp->CrypOutCount = 0U;
00656     hcryp->pCrypInBuffPtr = Input;
00657     hcryp->pCrypOutBuffPtr = Output;
00658     hcryp->Size = Size;
00659
00660     /* Set Encryption operating mode*/
00661     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
00662
00663     /* algo get algorithm selected */
00664     algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
00665
00666     switch(algo)
00667     {
00668     case CRYP_DES_ECB:
00669     case CRYP_DES_CBC:
00670     case CRYP_TDES_ECB:
00671     case CRYP_TDES_CBC:
00672
00673       /*Set Key */
00674       hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
00675       hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
00676       if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
00677       {
00678         hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
00679         hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
00680         hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
00681         hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
00682       }
00683
00684       /*Set Initialization Vector (IV)*/
00685       if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
00686       {
00687         hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
00688         hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
00689       }
00690
00691       /* Flush FIFO */
00692       HAL_CRYP_FIFO_FLUSH(hcryp);
00693
00694       /* Set the phase */
00695       hcryp->Phase = CRYP_PHASE_PROCESS;
00696
00697       /* Statrt DES/TDES encryption process */
00698       state = CRYP_TDES_Process(hcryp,Timeout);
00699       break;
00700
00701     case CRYP_AES_ECB:
00702     case CRYP_AES_CBC:
00703     case CRYP_AES_CTR:
00704
00705       /* AES encryption */
00706       state = CRYP_AES_Encrypt(hcryp, Timeout);
00707       break;
00708
00709     case CRYP_AES_GCM:
00710
00711       /* AES GCM encryption */
00712       state = CRYP_AESGCM_Process(hcryp, Timeout);
00713       break;
00714
00715     case CRYP_AES_CCM:
00716
00717       /* AES CCM encryption */
00718       state = CRYP_AESCCM_Process(hcryp,Timeout);
00719       break;
00720
00721     default:
00722       hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
00723       return HAL_ERROR;
00724     }
00725
00726     if (state == HAL_OK)
00727     {
00728       /* Change the CRYP peripheral state */
00729       hcryp->State = HAL_CRYP_STATE_READY;
00730
00731       /* Process unlocked */
00732       __HAL_UNLOCK(hcryp);
00733     }
00734   }
00735   else
00736   {
00737     /* Busy error code field */
00738     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
00739     return HAL_ERROR;
00740   }
00741
00742   /* Return function status */
00743   return HAL_OK;
00744 }
00745
00746 /**
00747   * @brief  Decryption mode.
00748   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00749   *         the configuration information for CRYP module
00750   * @param  Input: Pointer to the input buffer (ciphertext )
00751   * @param  Size: Length of the plaintext buffer in word.
00752   * @param  Output: Pointer to the output buffer(plaintext)
00753   * @param  Timeout: Specify Timeout value
00754   * @retval HAL status
00755   */
00756 HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
00757 {
00758   HAL_StatusTypeDef state;
00759   uint32_t algo = 0U;
00760
00761   if(hcryp->State == HAL_CRYP_STATE_READY)
00762   {
00763     /* Change state Busy */
00764     hcryp->State = HAL_CRYP_STATE_BUSY;
00765
00766     /* Process locked */
00767     __HAL_LOCK(hcryp);
00768
00769     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
00770     hcryp->CrypInCount = 0U;
00771     hcryp->CrypOutCount = 0U;
00772     hcryp->pCrypInBuffPtr = Input;
00773     hcryp->pCrypOutBuffPtr = Output;
00774     hcryp->Size = Size;
00775
00776     /* Set Decryption operating mode*/
00777     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
00778
00779     /* algo get algorithm selected */
00780     algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
00781
00782     switch(algo)
00783     {
00784     case CRYP_DES_ECB:
00785     case CRYP_DES_CBC:
00786     case CRYP_TDES_ECB:
00787     case CRYP_TDES_CBC:
00788
00789       /*Set Key */
00790       hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
00791       hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
00792       if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
00793       {
00794         hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
00795         hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
00796         hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
00797         hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
00798       }
00799
00800       /*Set Initialization Vector (IV)*/
00801       if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
00802       {
00803         hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
00804         hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
00805       }
00806
00807       /* Flush FIFO */
00808       HAL_CRYP_FIFO_FLUSH(hcryp);
00809
00810       /* Set the phase */
00811       hcryp->Phase = CRYP_PHASE_PROCESS;
00812
00813       /* Start DES/TDES decryption process */
00814       state = CRYP_TDES_Process(hcryp, Timeout);
00815
00816       break;
00817
00818     case CRYP_AES_ECB:
00819     case CRYP_AES_CBC:
00820     case CRYP_AES_CTR:
00821
00822       /* AES decryption */
00823       state = CRYP_AES_Decrypt(hcryp, Timeout);
00824       break;
00825
00826     case CRYP_AES_GCM:
00827
00828       /* AES GCM decryption */
00829       state = CRYP_AESGCM_Process (hcryp, Timeout) ;
00830       break;
00831
00832     case CRYP_AES_CCM:
00833
00834       /* AES CCM decryption */
00835       state = CRYP_AESCCM_Process(hcryp, Timeout);
00836       break;
00837
00838     default:
00839       hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
00840       return HAL_ERROR;
00841     }
00842
00843     if (state == HAL_OK)
00844     {
00845       /* Change the CRYP peripheral state */
00846       hcryp->State = HAL_CRYP_STATE_READY;
00847
00848       /* Process unlocked */
00849       __HAL_UNLOCK(hcryp);
00850     }
00851   }
00852   else
00853   {
00854     /* Busy error code field */
00855     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
00856     return HAL_ERROR;
00857   }
00858
00859   /* Return function status */
00860   return HAL_OK;
00861 }
00862
00863 /**
00864   * @brief  Encryption in interrupt mode.
00865   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00866   *         the configuration information for CRYP module
00867   * @param  Input: Pointer to the input buffer (plaintext)
00868   * @param  Size: Length of the plaintext buffer in word
00869   * @param  Output: Pointer to the output buffer(ciphertext)
00870   * @retval HAL status
00871   */
00872 HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
00873 {
00874   uint32_t algo = 0U;
00875
00876   if(hcryp->State == HAL_CRYP_STATE_READY)
00877   {
00878     /* Change state Busy */
00879     hcryp->State = HAL_CRYP_STATE_BUSY;
00880
00881     /* Process locked */
00882     __HAL_LOCK(hcryp);
00883
00884     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
00885     hcryp->CrypInCount = 0U;
00886     hcryp->CrypOutCount = 0U;
00887     hcryp->pCrypInBuffPtr = Input;
00888     hcryp->pCrypOutBuffPtr = Output;
00889     hcryp->Size = Size;
00890
00891     /* Set encryption operating mode*/
00892     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
00893
00894     /* algo get algorithm selected */
00895     algo = (hcryp->Instance->CR & CRYP_CR_ALGOMODE);
00896
00897     switch(algo)
00898     {
00899     case CRYP_DES_ECB:
00900     case CRYP_DES_CBC:
00901     case CRYP_TDES_ECB:
00902     case CRYP_TDES_CBC:
00903
00904       /*Set Key */
00905       hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
00906       hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
00907       if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
00908       {
00909         hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
00910         hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
00911         hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
00912         hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
00913       }
00914       /* Set the Initialization Vector*/
00915       if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
00916       {
00917         hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
00918         hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
00919       }
00920
00921       /* Flush FIFO */
00922       HAL_CRYP_FIFO_FLUSH(hcryp);
00923
00924       /* Set the phase */
00925       hcryp->Phase = CRYP_PHASE_PROCESS;
00926
00927       /* Enable interrupts */
00928       __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
00929
00930       /* Enable CRYP to start DES/TDES process*/
00931       __HAL_CRYP_ENABLE(hcryp);
00932
00933       break;
00934
00935     case CRYP_AES_ECB:
00936     case CRYP_AES_CBC:
00937     case CRYP_AES_CTR:
00938
00939       CRYP_AES_Encrypt_IT(hcryp);
00940       break;
00941
00942     case CRYP_AES_GCM:
00943
00944       CRYP_AESGCM_Process_IT (hcryp) ;
00945       break;
00946
00947     case CRYP_AES_CCM:
00948
00949       CRYP_AESCCM_Process_IT(hcryp);
00950       break;
00951
00952     default:
00953       hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
00954       return HAL_ERROR;
00955     }
00956   }
00957   else
00958   {
00959     /* Busy error code field */
00960     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
00961     return HAL_ERROR;
00962   }
00963
00964   /* Return function status */
00965   return HAL_OK;
00966 }
00967
00968 /**
00969   * @brief  Decryption in itnterrupt mode.
00970   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00971   *         the configuration information for CRYP module
00972   * @param  Input: Pointer to the input buffer (ciphertext )
00973   * @param  Size: Length of the plaintext buffer in word.
00974   * @param  Output: Pointer to the output buffer(plaintext)
00975   * @retval HAL status
00976   */
00977 HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
00978 {
00979   uint32_t algo = 0U;
00980
00981   if(hcryp->State == HAL_CRYP_STATE_READY)
00982   {
00983     /* Change state Busy */
00984     hcryp->State = HAL_CRYP_STATE_BUSY;
00985
00986     /* Process locked */
00987     __HAL_LOCK(hcryp);
00988
00989     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
00990     hcryp->CrypInCount = 0U;
00991     hcryp->CrypOutCount = 0U;
00992     hcryp->pCrypInBuffPtr = Input;
00993     hcryp->pCrypOutBuffPtr = Output;
00994     hcryp->Size = Size;
00995
00996     /* Set decryption operating mode*/
00997     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR,CRYP_OPERATINGMODE_DECRYPT);
00998
00999     /* algo get algorithm selected */
01000     algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
01001
01002     switch(algo)
01003     {
01004     case CRYP_DES_ECB:
01005     case CRYP_DES_CBC:
01006     case CRYP_TDES_ECB:
01007     case CRYP_TDES_CBC:
01008
01009       /*Set Key */
01010       hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
01011       hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
01012       if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
01013       {
01014         hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
01015         hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
01016         hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
01017         hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
01018       }
01019
01020       /* Set the Initialization Vector*/
01021       if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
01022       {
01023         hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
01024         hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
01025       }
01026       /* Flush FIFO */
01027       HAL_CRYP_FIFO_FLUSH(hcryp);
01028
01029       /* Set the phase */
01030       hcryp->Phase = CRYP_PHASE_PROCESS;
01031
01032       /* Enable interrupts */
01033       __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01034
01035       /* Enable CRYP and start DES/TDES process*/
01036       __HAL_CRYP_ENABLE(hcryp);
01037
01038       break;
01039
01040     case CRYP_AES_ECB:
01041     case CRYP_AES_CBC:
01042     case CRYP_AES_CTR:
01043
01044       /* AES decryption */
01045       CRYP_AES_Decrypt_IT(hcryp);
01046       break;
01047
01048     case CRYP_AES_GCM:
01049
01050       /* AES GCM decryption */
01051       CRYP_AESGCM_Process_IT (hcryp) ;
01052       break;
01053
01054     case CRYP_AES_CCM:
01055
01056       /* AES CCMdecryption */
01057       CRYP_AESCCM_Process_IT(hcryp);
01058       break;
01059
01060     default:
01061       hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01062       return HAL_ERROR;
01063     }
01064   }
01065   else
01066   {
01067     /* Busy error code field */
01068     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01069     return HAL_ERROR;
01070   }
01071
01072   /* Return function status */
01073   return HAL_OK;
01074 }
01075
01076 /**
01077   * @brief  Encryption in DMA mode.
01078   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01079   *         the configuration information for CRYP module
01080   * @param  Input: Pointer to the input buffer (plaintext)
01081   * @param  Size: Length of the plaintext buffer in word.
01082   * @param  Output: Pointer to the output buffer(ciphertext)
01083   * @retval HAL status
01084   */
01085 HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
01086 {
01087   uint32_t algo = 0U;
01088
01089   if(hcryp->State == HAL_CRYP_STATE_READY)
01090   {
01091     /* Change state Busy */
01092     hcryp->State = HAL_CRYP_STATE_BUSY;
01093
01094     /* Process locked */
01095     __HAL_LOCK(hcryp);
01096
01097     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
01098     hcryp->CrypInCount = 0U;
01099     hcryp->CrypOutCount = 0U;
01100     hcryp->pCrypInBuffPtr = Input;
01101     hcryp->pCrypOutBuffPtr = Output;
01102     hcryp->Size = Size;
01103
01104     /* Set encryption operating mode*/
01105     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
01106
01107     /* algo get algorithm selected */
01108     algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
01109
01110     switch(algo)
01111     {
01112     case CRYP_DES_ECB:
01113     case CRYP_DES_CBC:
01114     case CRYP_TDES_ECB:
01115     case CRYP_TDES_CBC:
01116
01117       /*Set Key */
01118       hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
01119       hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
01120       if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
01121       {
01122         hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
01123         hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
01124         hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
01125         hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
01126       }
01127
01128       /* Set the Initialization Vector*/
01129       if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
01130       {
01131         hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
01132         hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
01133       }
01134
01135       /* Flush FIFO */
01136       HAL_CRYP_FIFO_FLUSH(hcryp);
01137
01138       /* Set the phase */
01139       hcryp->Phase = CRYP_PHASE_PROCESS;
01140
01141       /* Start DMA process transfer for DES/TDES */
01142       CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size), (uint32_t)(hcryp->pCrypOutBuffPtr));
01143
01144       break;
01145
01146     case CRYP_AES_ECB:
01147     case CRYP_AES_CBC:
01148     case CRYP_AES_CTR:
01149
01150       /*  Set the Key*/
01151       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01152
01153       /* Set the Initialization Vector IV */
01154       if (hcryp->Init.Algorithm != CRYP_AES_ECB)
01155       {
01156         hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
01157         hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
01158         hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
01159         hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
01160       }
01161
01162       /* Set the phase */
01163       hcryp->Phase = CRYP_PHASE_PROCESS;
01164
01165       /* Start DMA process transfer for AES */
01166       CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), Size, (uint32_t)(hcryp->pCrypOutBuffPtr));
01167       break;
01168
01169     case CRYP_AES_GCM:
01170
01171       /* AES GCM encryption */
01172       CRYP_AESGCM_Process_DMA (hcryp) ;
01173       break;
01174
01175     case CRYP_AES_CCM:
01176
01177       /* AES CCM encryption */
01178       CRYP_AESCCM_Process_DMA(hcryp);
01179       break;
01180
01181     default:
01182       hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01183       return HAL_ERROR;
01184     }
01185   }
01186   else
01187   {
01188     /* Busy error code field */
01189     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01190     return HAL_ERROR;
01191   }
01192
01193   /* Return function status */
01194   return HAL_OK;
01195 }
01196
01197 /**
01198   * @brief  Decryption in DMA mode.
01199   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01200   *         the configuration information for CRYP module
01201   * @param  Input: Pointer to the input buffer (ciphertext )
01202   * @param  Size: Length of the plaintext buffer in word
01203   * @param  Output: Pointer to the output buffer(plaintext)
01204   * @retval HAL status
01205   */
01206 HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
01207 {
01208   uint32_t algo = 0U;
01209
01210   if(hcryp->State == HAL_CRYP_STATE_READY)
01211   {
01212     /* Change state Busy */
01213     hcryp->State = HAL_CRYP_STATE_BUSY;
01214
01215     /* Process locked */
01216     __HAL_LOCK(hcryp);
01217
01218     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
01219     hcryp->CrypInCount = 0U;
01220     hcryp->CrypOutCount = 0U;
01221     hcryp->pCrypInBuffPtr = Input;
01222     hcryp->pCrypOutBuffPtr = Output;
01223     hcryp->Size = Size;
01224
01225     /* Set decryption operating mode*/
01226     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
01227
01228     /* algo get algorithm selected */
01229     algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
01230
01231     switch(algo)
01232     {
01233     case CRYP_DES_ECB:
01234     case CRYP_DES_CBC:
01235     case CRYP_TDES_ECB:
01236     case CRYP_TDES_CBC:
01237
01238       /*Set Key */
01239       hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
01240       hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
01241       if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
01242       {
01243         hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
01244         hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
01245         hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
01246         hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
01247       }
01248
01249       /* Set the Initialization Vector*/
01250       if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
01251       {
01252         hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
01253         hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
01254       }
01255
01256       /* Flush FIFO */
01257       HAL_CRYP_FIFO_FLUSH(hcryp);
01258
01259       /* Set the phase */
01260       hcryp->Phase = CRYP_PHASE_PROCESS;
01261
01262       /* Start DMA process transfer for DES/TDES */
01263       CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size), (uint32_t)(hcryp->pCrypOutBuffPtr));
01264       break;
01265
01266     case CRYP_AES_ECB:
01267     case CRYP_AES_CBC:
01268     case CRYP_AES_CTR:
01269
01270       /* AES decryption */
01271       CRYP_AES_Decrypt_DMA(hcryp);
01272       break;
01273
01274     case CRYP_AES_GCM:
01275
01276       /* AES GCM decryption */
01277       CRYP_AESGCM_Process_DMA (hcryp) ;
01278
01279       break;
01280
01281     case CRYP_AES_CCM:
01282
01283       /* AES CCM decryption */
01284       CRYP_AESCCM_Process_DMA(hcryp);
01285       break;
01286
01287     default:
01288       hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01289       return HAL_ERROR;
01290     }
01291   }
01292   else
01293   {
01294     /* Busy error code field */
01295     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01296     return HAL_ERROR;
01297   }
01298
01299   /* Return function status */
01300   return HAL_OK;
01301 }
01302
01303 /**
01304   * @}
01305   */
01306
01307 /** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
01308  *  @brief    CRYP IRQ handler.
01309  *
01310 @verbatim
01311   ==============================================================================
01312                 ##### CRYP IRQ handler management #####
01313   ==============================================================================
01314 [..]  This section provides CRYP IRQ handler and callback functions.
01315       (+) HAL_CRYP_IRQHandler CRYP interrupt request
01316       (+) HAL_CRYP_InCpltCallback input data transfer complete callback
01317       (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
01318       (+) HAL_CRYP_ErrorCallback  CRYP error callback
01319       (+) HAL_CRYP_GetState return the CRYP state
01320       (+) HAL_CRYP_GetError return the CRYP error code
01321 @endverbatim
01322   * @{
01323   */
01324
01325 /**
01326   * @brief  This function handles cryptographic interrupt request.
01327   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01328   *         the configuration information for CRYP module
01329   * @retval None
01330   */
01331 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
01332 {
01333   uint32_t CurrentMode  = 0U;
01334
01335   /*put CRYP_IT_OUTI flag status in CurrentMode variable*/
01336   CurrentMode  = __HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI);
01337
01338   if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != RESET)| (CurrentMode != RESET))
01339   {
01340     if ((hcryp->Init.Algorithm == CRYP_DES_ECB)|| (hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
01341     {
01342       CRYP_TDES_IT(hcryp); /* DES or TDES*/
01343     }
01344     else if((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC) || (hcryp->Init.Algorithm == CRYP_AES_CTR))
01345     {
01346       CRYP_AES_IT(hcryp); /*AES*/
01347     }
01348
01349     else if((hcryp->Init.Algorithm == CRYP_AES_GCM) ||(hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM) )
01350     {
01351       /* if header phase */
01352       if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER )
01353       {
01354         CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
01355       }
01356       else  /* if payload phase */
01357       {
01358         CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
01359       }
01360     }
01361   }
01362 }
01363
01364 /**
01365   * @brief  Return the CRYP error code.
01366   * @param  hcryp : pointer to a CRYP_HandleTypeDef structure that contains
01367   *                 the configuration information for the  CRYP IP
01368   * @retval CRYP error code
01369   */
01370 uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
01371 {
01372   return hcryp->ErrorCode;
01373 }
01374
01375 /**
01376   * @brief  Returns the CRYP state.
01377   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01378   *         the configuration information for CRYP module.
01379   * @retval HAL state
01380   */
01381 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
01382 {
01383   return hcryp->State;
01384 }
01385
01386 /**
01387   * @brief  Input FIFO transfer completed callback.
01388   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01389   *         the configuration information for CRYP module.
01390   * @retval None
01391   */
01392 __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
01393 {
01394   /* Prevent unused argument(s) compilation warning */
01395   UNUSED(hcryp);
01396
01397   /* NOTE : This function Should not be modified, when the callback is needed,
01398             the HAL_CRYP_InCpltCallback could be implemented in the user file
01399    */
01400 }
01401
01402 /**
01403   * @brief  Output FIFO transfer completed callback.
01404   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01405   *         the configuration information for CRYP module.
01406   * @retval None
01407   */
01408 __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
01409 {
01410   /* Prevent unused argument(s) compilation warning */
01411   UNUSED(hcryp);
01412
01413   /* NOTE : This function Should not be modified, when the callback is needed,
01414             the HAL_CRYP_OutCpltCallback could be implemented in the user file
01415    */
01416 }
01417
01418 /**
01419   * @brief  CRYP error callback.
01420   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01421   *         the configuration information for CRYP module.
01422   * @retval None
01423   */
01424  __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
01425 {
01426   /* Prevent unused argument(s) compilation warning */
01427   UNUSED(hcryp);
01428
01429   /* NOTE : This function Should not be modified, when the callback is needed,
01430             the HAL_CRYP_ErrorCallback could be implemented in the user file
01431    */
01432 }
01433 /**
01434   * @}
01435   */
01436
01437 /* Private functions ---------------------------------------------------------*/
01438 /** @addtogroup CRYP_Private_Functions
01439   * @{
01440   */
01441
01442 /**
01443   * @brief  Encryption in ECB/CBC Algorithm with DES/TDES standard.
01444   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01445   *         the configuration information for CRYP module
01446   * @param  Timeout: Timeout value
01447   * @retval HAL status
01448   */
01449 static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
01450 {
01451
01452   uint32_t temp = 0U;  /* Temporary CrypOutBuff */
01453
01454   /* Enable CRYP */
01455   __HAL_CRYP_ENABLE(hcryp);
01456
01457   /*Start processing*/
01458   while((hcryp->CrypInCount < hcryp->Size) && (hcryp->CrypOutCount < hcryp->Size))
01459   {
01460     /* Write plain data and get cipher data */
01461     if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != RESET) && (hcryp->CrypInCount < hcryp->Size))
01462     {
01463       /* Write the input block in the IN FIFO */
01464       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
01465       hcryp->CrypInCount++;
01466       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
01467       hcryp->CrypInCount++;
01468     }
01469
01470     /* Wait for OFNE flag to be raised */
01471     if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
01472     {
01473       /* Disable the CRYP peripheral clock */
01474       __HAL_CRYP_DISABLE(hcryp);
01475
01476       /* Change state & errorCode*/
01477       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
01478       hcryp->State = HAL_CRYP_STATE_READY;
01479
01480       /* Process unlocked */
01481       __HAL_UNLOCK(hcryp);
01482       HAL_CRYP_ErrorCallback(hcryp);
01483     }
01484
01485     if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != RESET) && (hcryp->CrypOutCount < hcryp->Size))
01486     {
01487       /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer  */
01488       temp = hcryp->Instance->DOUT;
01489       *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
01490       hcryp->CrypOutCount++;
01491       temp = hcryp->Instance->DOUT;
01492       *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
01493       hcryp->CrypOutCount++;
01494     }
01495   }
01496   /* Disable CRYP */
01497   __HAL_CRYP_DISABLE(hcryp);
01498   /* Change the CRYP state */
01499   hcryp->State = HAL_CRYP_STATE_READY;
01500
01501   /* Return function status */
01502   return HAL_OK;
01503 }
01504
01505 /**
01506   * @brief  CRYP block input/output data handling under interruption with DES/TDES standard.
01507   * @note   The function is called under interruption only, once
01508   *         interruptions have been enabled by CRYP_Decrypt_IT() and CRYP_Encrypt_IT().
01509   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01510   *         the configuration information for CRYP module.
01511   * @retval HAL status
01512   */
01513 static HAL_StatusTypeDef CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
01514 {
01515   uint32_t temp = 0U;  /* Temporary CrypOutBuff */
01516
01517   if(hcryp->State == HAL_CRYP_STATE_BUSY)
01518   {
01519     if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != RESET) && (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != RESET))
01520
01521     {
01522       /* Write input block in the IN FIFO */
01523       hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
01524       hcryp->CrypInCount++;
01525       hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
01526       hcryp->CrypInCount++;
01527
01528       if(hcryp->CrypInCount ==  hcryp->Size)
01529       {
01530         /* Disable interruption */
01531         __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
01532
01533         /* Call the input data transfer complete callback */
01534         HAL_CRYP_InCpltCallback(hcryp);
01535       }
01536     }
01537     if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != RESET)&& (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != RESET))
01538     {
01539       /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer  */
01540       temp = hcryp->Instance->DOUT;
01541       *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
01542       hcryp->CrypOutCount++;
01543       temp = hcryp->Instance->DOUT;
01544       *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
01545       hcryp->CrypOutCount++;
01546       if(hcryp->CrypOutCount ==  hcryp->Size)
01547       {
01548         /* Disable interruption */
01549         __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
01550
01551         /* Disable CRYP */
01552         __HAL_CRYP_DISABLE(hcryp);
01553
01554         /* Process unlocked */
01555         __HAL_UNLOCK(hcryp);
01556
01557         /* Change the CRYP state */
01558         hcryp->State = HAL_CRYP_STATE_READY;
01559
01560         /* Call output transfer complete callback */
01561         HAL_CRYP_OutCpltCallback(hcryp);
01562       }
01563     }
01564     return HAL_OK;
01565   }
01566   else
01567   {
01568     /* Busy error code field */
01569     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01570     return HAL_ERROR;
01571   }
01572 }
01573
01574 /**
01575   * @brief  Encryption in ECB/CBC & CTR Algorithm with AES Standard
01576   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure
01577   * @param  Timeout: specify Timeout value
01578   * @retval HAL status
01579   */
01580 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
01581 {
01582
01583   /*  Set the Key*/
01584   CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01585
01586   if (hcryp->Init.Algorithm != CRYP_AES_ECB)
01587   {
01588     /* Set the Initialization Vector*/
01589     hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
01590     hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
01591     hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
01592     hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
01593   }
01594
01595   /* Set the phase */
01596   hcryp->Phase = CRYP_PHASE_PROCESS;
01597
01598   /* Enable CRYP */
01599   __HAL_CRYP_ENABLE(hcryp);
01600
01601   while((hcryp->CrypInCount < hcryp->Size) && (hcryp->CrypOutCount < hcryp->Size))
01602   {
01603     /* Write plain Ddta and get cipher data */
01604     CRYP_AES_ProcessData(hcryp,Timeout);
01605   }
01606
01607   /* Disable CRYP */
01608   __HAL_CRYP_DISABLE(hcryp);
01609
01610   /* Change the CRYP state */
01611   hcryp->State = HAL_CRYP_STATE_READY;
01612
01613   /* Return function status */
01614   return HAL_OK;
01615 }
01616
01617 /**
01618   * @brief  Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
01619   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01620   *         the configuration information for CRYP module
01621   * @retval HAL status
01622   */
01623 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
01624 {
01625
01626   /*  Set the Key*/
01627   CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01628
01629   if (hcryp->Init.Algorithm != CRYP_AES_ECB)
01630   {
01631     /* Set the Initialization Vector*/
01632     hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
01633     hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
01634     hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
01635     hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
01636   }
01637   /* Set the phase */
01638   hcryp->Phase = CRYP_PHASE_PROCESS;
01639
01640   if(hcryp->Size != 0U)
01641   {
01642     /* Enable interrupts */
01643     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01644
01645     /* Enable CRYP */
01646     __HAL_CRYP_ENABLE(hcryp);
01647   }
01648   else
01649   {
01650     /* Change the CRYP state */
01651     hcryp->State = HAL_CRYP_STATE_READY;
01652
01653     /* Process unlocked */
01654     __HAL_UNLOCK(hcryp);
01655   }
01656
01657   /* Return function status */
01658   return HAL_OK;
01659 }
01660
01661 /**
01662   * @brief  Decryption in ECB/CBC & CTR mode with AES Standard
01663   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure
01664   * @param  Timeout: Specify Timeout value
01665   * @retval HAL status
01666   */
01667 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout )
01668 {
01669   /*  Key preparation for ECB/CBC */
01670   if (hcryp->Init.Algorithm != CRYP_AES_CTR)   /*ECB or CBC*/
01671   {
01672     /* change ALGOMODE to key preparation for decryption*/
01673     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
01674
01675     /*  Set the Key*/
01676     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01677
01678     /* Enable CRYP */
01679     __HAL_CRYP_ENABLE(hcryp);
01680
01681     /* Wait for BUSY flag to be raised */
01682     if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
01683     {
01684       /* Disable the CRYP peripheral clock */
01685       __HAL_CRYP_DISABLE(hcryp);
01686
01687       /* Change state */
01688       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
01689       hcryp->State = HAL_CRYP_STATE_READY;
01690
01691       /* Process unlocked */
01692       __HAL_UNLOCK(hcryp);
01693       return HAL_ERROR;
01694     }
01695     /* Turn back to ALGOMODE of the configuration */
01696     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
01697   }
01698   else  /*Algorithm CTR */
01699   {
01700     /*  Set the Key*/
01701     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01702   }
01703
01704   /* Set IV */
01705   if (hcryp->Init.Algorithm != CRYP_AES_ECB)
01706   {
01707     /* Set the Initialization Vector*/
01708     hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
01709     hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
01710     hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
01711     hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
01712   }
01713   /* Set the phase */
01714   hcryp->Phase = CRYP_PHASE_PROCESS;
01715
01716   /* Enable CRYP */
01717   __HAL_CRYP_ENABLE(hcryp);
01718
01719   while((hcryp->CrypInCount < hcryp->Size) && (hcryp->CrypOutCount < hcryp->Size))
01720   {
01721     /* Write plain data and get cipher data */
01722     CRYP_AES_ProcessData(hcryp,Timeout);
01723   }
01724
01725   /* Disable CRYP */
01726   __HAL_CRYP_DISABLE(hcryp);
01727
01728   /* Change the CRYP state */
01729   hcryp->State = HAL_CRYP_STATE_READY;
01730
01731   /* Return function status */
01732   return HAL_OK;
01733 }
01734 /**
01735   * @brief  Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
01736   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01737   *         the configuration information for CRYP module
01738   * @retval HAL status
01739   */
01740 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
01741 {
01742   __IO uint32_t count = 0U;
01743
01744   /*  Key preparation for ECB/CBC */
01745   if (hcryp->Init.Algorithm != CRYP_AES_CTR)
01746   {
01747     /* change ALGOMODE to key preparation for decryption*/
01748     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
01749
01750     /*  Set the Key*/
01751     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01752
01753     /* Enable CRYP */
01754     __HAL_CRYP_ENABLE(hcryp);
01755
01756     /* Wait for BUSY flag to be raised */
01757     count = CRYP_TIMEOUT_KEYPREPARATION;
01758     do
01759     {
01760       if(count-- == 0U)
01761       {
01762         /* Change state */
01763         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
01764         hcryp->State = HAL_CRYP_STATE_READY;
01765
01766         /* Process unlocked */
01767         __HAL_UNLOCK(hcryp);
01768         return HAL_ERROR;
01769       }
01770     }
01771     while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
01772
01773     /* Turn back to ALGOMODE of the configuration */
01774     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
01775   }
01776   else  /*Algorithm CTR */
01777   {
01778     /*  Set the Key*/
01779     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01780   }
01781
01782   /* Set IV */
01783   if (hcryp->Init.Algorithm != CRYP_AES_ECB)
01784   {
01785     /* Set the Initialization Vector*/
01786     hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
01787     hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
01788     hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
01789     hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
01790   }
01791   /* Set the phase */
01792   hcryp->Phase = CRYP_PHASE_PROCESS;
01793   if(hcryp->Size != 0)
01794   {
01795     /* Enable interrupts */
01796     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01797
01798     /* Enable CRYP */
01799     __HAL_CRYP_ENABLE(hcryp);
01800   }
01801   else
01802   {
01803     /* Process locked */
01804     __HAL_UNLOCK(hcryp);
01805
01806     /* Change the CRYP state */
01807     hcryp->State = HAL_CRYP_STATE_READY;
01808   }
01809   /* Return function status */
01810   return HAL_OK;
01811 }
01812 /**
01813   * @brief  Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode
01814   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01815   *         the configuration information for CRYP module
01816   * @retval HAL status
01817   */
01818 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
01819 {
01820   __IO uint32_t count = 0U;
01821
01822   /*  Key preparation for ECB/CBC */
01823   if (hcryp->Init.Algorithm != CRYP_AES_CTR)
01824   {
01825     /* change ALGOMODE to key preparation for decryption*/
01826     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
01827
01828     /*  Set the Key*/
01829     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01830
01831     /* Enable CRYP */
01832     __HAL_CRYP_ENABLE(hcryp);
01833
01834     /* Wait for BUSY flag to be raised */
01835     count = CRYP_TIMEOUT_KEYPREPARATION;
01836     do
01837     {
01838       if(count-- == 0U)
01839       {
01840         /* Disable the CRYP peripheral clock */
01841         __HAL_CRYP_DISABLE(hcryp);
01842
01843         /* Change state */
01844         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
01845         hcryp->State = HAL_CRYP_STATE_READY;
01846
01847         /* Process unlocked */
01848         __HAL_UNLOCK(hcryp);
01849         return HAL_ERROR;
01850       }
01851     }
01852     while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
01853
01854     /* Turn back to ALGOMODE of the configuration */
01855     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
01856   }
01857   else  /*Algorithm CTR */
01858   {
01859     /*  Set the Key*/
01860     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01861   }
01862
01863   if (hcryp->Init.Algorithm != CRYP_AES_ECB)
01864   {
01865     /* Set the Initialization Vector*/
01866     hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
01867     hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
01868     hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
01869     hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
01870   }
01871   /* Set the phase */
01872   hcryp->Phase = CRYP_PHASE_PROCESS;
01873
01874   if(hcryp->Size != 0)
01875   {
01876     /* Set the input and output addresses and start DMA transfer */
01877     CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), hcryp->Size, (uint32_t)(hcryp->pCrypOutBuffPtr));
01878   }
01879   else
01880   {
01881     /* Process unlocked */
01882     __HAL_UNLOCK(hcryp);
01883
01884     /* Change the CRYP state */
01885     hcryp->State = HAL_CRYP_STATE_READY;
01886   }
01887
01888   /* Return function status */
01889   return HAL_OK;
01890 }
01891
01892
01893 /**
01894   * @brief  DMA CRYP input data process complete callback.
01895   * @param  hdma: DMA handle
01896   * @retval None
01897   */
01898 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
01899 {
01900   CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01901
01902   /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
01903   in the DMACR register */
01904   hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
01905
01906   /* Call input data transfer complete callback */
01907   HAL_CRYP_InCpltCallback(hcryp);
01908 }
01909
01910 /**
01911   * @brief  DMA CRYP output data process complete callback.
01912   * @param  hdma: DMA handle
01913   * @retval None
01914   */
01915 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
01916 {
01917   CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01918
01919   /* Disable the DMA transfer for output FIFO request by resetting
01920   the DOEN bit in the DMACR register */
01921   hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
01922   if((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
01923   {
01924     /* Disable CRYP  (not allowed in  GCM)*/
01925     __HAL_CRYP_DISABLE(hcryp);
01926   }
01927
01928   /* Change the CRYP state to ready */
01929   hcryp->State = HAL_CRYP_STATE_READY;
01930
01931   /* Process unlocked */
01932   __HAL_UNLOCK(hcryp);
01933
01934   /* Call output data transfer complete callback */
01935   HAL_CRYP_OutCpltCallback(hcryp);
01936 }
01937
01938 /**
01939   * @brief  DMA CRYP communication error callback.
01940   * @param  hdma: DMA handle
01941   * @retval None
01942   */
01943 static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
01944 {
01945   CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01946
01947   /* Change the CRYP peripheral state */
01948   hcryp->State= HAL_CRYP_STATE_READY;
01949
01950   /* DMA error code field */
01951   hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
01952
01953   /* Call error callback */
01954   HAL_CRYP_ErrorCallback(hcryp);
01955 }
01956
01957 /**
01958   * @brief  Set the DMA configuration and start the DMA transfer
01959   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01960   *         the configuration information for CRYP module
01961   * @param  inputaddr: address of the input buffer
01962   * @param  Size: size of the input buffer, must be a multiple of 16.
01963   * @param  outputaddr: address of the output buffer
01964   * @retval None
01965   */
01966 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
01967 {
01968   /* Set the CRYP DMA transfer complete callback */
01969   hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
01970
01971   /* Set the DMA input error callback */
01972   hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
01973
01974   /* Set the CRYP DMA transfer complete callback */
01975   hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
01976
01977   /* Set the DMA output error callback */
01978   hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
01979
01980   /* Enable CRYP */
01981   __HAL_CRYP_ENABLE(hcryp);
01982
01983   /* Enable the input DMA Stream */
01984   HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size);
01985
01986   /* Enable the output DMA Stream */
01987   HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size);
01988
01989   /* Enable In/Out DMA request */
01990   hcryp->Instance->DMACR = CRYP_DMACR_DOEN | CRYP_DMACR_DIEN;
01991 }
01992
01993 /**
01994   * @brief  Process Data: Write Input data in polling mode and used in AES functions.
01995   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01996   *         the configuration information for CRYP module
01997   * @param  Timeout: Specify Timeout value
01998   * @retval None
01999   */
02000 static HAL_StatusTypeDef CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
02001 {
02002
02003   uint32_t temp = 0U;  /* Temporary CrypOutBuff */
02004
02005   if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != RESET) && (hcryp->CrypInCount < hcryp->Size))
02006   {
02007     /* Write the input block in the IN FIFO */
02008     hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
02009     hcryp->CrypInCount++;
02010     hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
02011     hcryp->CrypInCount++;
02012     hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
02013     hcryp->CrypInCount++;
02014     hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
02015     hcryp->CrypInCount++;
02016   }
02017
02018   /* Wait for OFNE flag to be raised */
02019   if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
02020   {
02021     /* Disable the CRYP peripheral clock */
02022     __HAL_CRYP_DISABLE(hcryp);
02023
02024     /* Change state & error code*/
02025     hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02026     hcryp->State = HAL_CRYP_STATE_READY;
02027
02028     /* Process unlocked */
02029     __HAL_UNLOCK(hcryp);
02030     HAL_CRYP_ErrorCallback(hcryp);
02031   }
02032
02033   if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != RESET) && (hcryp->CrypOutCount < hcryp->Size))
02034   {
02035     /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer  */
02036     temp  = hcryp->Instance->DOUT;
02037     *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
02038     hcryp->CrypOutCount++;
02039     temp  = hcryp->Instance->DOUT;
02040     *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
02041     hcryp->CrypOutCount++;
02042     temp  = hcryp->Instance->DOUT;
02043     *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
02044     hcryp->CrypOutCount++;
02045     temp  = hcryp->Instance->DOUT;
02046     *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
02047     hcryp->CrypOutCount++;
02048   }
02049
02050   /* Return function status */
02051   return HAL_OK;
02052 }
02053
02054 /**
02055   * @brief  Handle CRYP block input/output data handling under interruption.
02056   * @note   The function is called under interruption only, once
02057   *         interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
02058   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02059   *         the configuration information for CRYP module.
02060   * @retval HAL status
02061   */
02062 static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
02063 {
02064   uint32_t temp = 0U;  /* Temporary CrypOutBuff */
02065
02066   if(hcryp->State == HAL_CRYP_STATE_BUSY)
02067   {
02068     if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != RESET) && (hcryp->CrypInCount < hcryp->Size))
02069     {
02070       /* Write the input block in the IN FIFO */
02071       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
02072       hcryp->CrypInCount++;
02073       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
02074       hcryp->CrypInCount++;
02075       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
02076       hcryp->CrypInCount++;
02077       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
02078       hcryp->CrypInCount++;
02079       if(hcryp->CrypInCount ==  hcryp->Size)
02080       {
02081         /* Disable interrupts */
02082         __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
02083
02084         /* Call the input data transfer complete callback */
02085         HAL_CRYP_InCpltCallback(hcryp);
02086       }
02087     }
02088     if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != RESET) && (hcryp->CrypOutCount < hcryp->Size))
02089     {
02090       /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer  */
02091       temp  = hcryp->Instance->DOUT;
02092       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
02093       hcryp->CrypOutCount++;
02094       temp  = hcryp->Instance->DOUT;
02095       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
02096       hcryp->CrypOutCount++;
02097       temp  = hcryp->Instance->DOUT;
02098       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
02099       hcryp->CrypOutCount++;
02100       temp  = hcryp->Instance->DOUT;
02101       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
02102       hcryp->CrypOutCount++;
02103       if(hcryp->CrypOutCount ==  hcryp->Size)
02104       {
02105         /* Disable interrupts */
02106         __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
02107
02108         /* Change the CRYP state */
02109         hcryp->State = HAL_CRYP_STATE_READY;
02110
02111         /* Disable CRYP */
02112         __HAL_CRYP_DISABLE(hcryp);
02113
02114         /* Process unlocked */
02115         __HAL_UNLOCK(hcryp);
02116
02117         /* Call output transfer complete callback */
02118         HAL_CRYP_OutCpltCallback(hcryp);
02119       }
02120     }
02121     /* Return function status */
02122     return HAL_OK;
02123   }
02124   else
02125   {
02126     /* Busy error code field */
02127     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
02128     return HAL_ERROR;
02129   }
02130 }
02131
02132 /**
02133   * @brief  Writes Key in Key registers.
02134   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02135   *         the configuration information for CRYP module
02136   * @param  Key: Pointer to Key buffer
02137   * @param  KeySize: Size of Key
02138   * @retval None
02139   */
02140 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t *Key, uint32_t KeySize)
02141 {
02142   switch(KeySize)
02143   {
02144   case CRYP_KEYSIZE_256B:
02145     hcryp->Instance->K0LR = *(uint32_t*)(hcryp->Init.pKey);
02146     hcryp->Instance->K0RR = *(uint32_t*)(hcryp->Init.pKey+1);
02147     hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey+2);
02148     hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+3);
02149     hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+4);
02150     hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+5);
02151     hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+6);
02152     hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+7);
02153     break;
02154   case CRYP_KEYSIZE_192B:
02155     hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
02156     hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
02157     hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
02158     hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
02159     hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
02160     hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
02161     break;
02162   case CRYP_KEYSIZE_128B:
02163     hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey);
02164     hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+1);
02165     hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+2);
02166     hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+3);
02167
02168     break;
02169   default:
02170     break;
02171   }
02172 }
02173
02174 /**
02175   * @brief  Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
02176   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02177   *         the configuration information for CRYP module
02178   * @param  Timeout: Timeout duration
02179   * @retval HAL status
02180   */
02181 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
02182 {
02183   uint32_t tickstart = 0U;
02184   uint32_t payloadlength = 0U;
02185
02186   /*  Reset CrypHeaderCount */
02187   hcryp->CrypHeaderCount = 0U;
02188
02189   /****************************** Init phase **********************************/
02190
02191   CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
02192
02193   /* Set the key */
02194   CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02195
02196   /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
02197   hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
02198   hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
02199   hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
02200   hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
02201
02202   /* Enable the CRYP peripheral */
02203   __HAL_CRYP_ENABLE(hcryp);
02204
02205   /* Get tick */
02206   tickstart = HAL_GetTick();
02207
02208   /*Wait for the CRYPEN bit to be cleared*/
02209   while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
02210   {
02211     /* Check for the Timeout */
02212     if(Timeout != HAL_MAX_DELAY)
02213     {
02214       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
02215       {
02216         /* Disable the CRYP peripheral clock */
02217         __HAL_CRYP_DISABLE(hcryp);
02218
02219         /* Change state */
02220         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02221         hcryp->State = HAL_CRYP_STATE_READY;
02222
02223         /* Process unlocked */
02224         __HAL_UNLOCK(hcryp);
02225         return HAL_ERROR;
02226       }
02227     }
02228   }
02229
02230   /************************ Header phase *************************************/
02231
02232   if(CRYP_GCMCCM_SetHeaderPhase(hcryp,  Timeout) != HAL_OK)
02233   {
02234     return HAL_ERROR;
02235   }
02236
02237   /*************************Payload phase ************************************/
02238
02239   /* Set the phase */
02240   hcryp->Phase = CRYP_PHASE_PROCESS;
02241
02242   /* Disable the CRYP peripheral */
02243   __HAL_CRYP_DISABLE(hcryp);
02244
02245   /* Select payload phase once the header phase is performed */
02246   CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
02247
02248   /* Enable the CRYP peripheral */
02249   __HAL_CRYP_ENABLE(hcryp);
02250
02251   /* Get tick */
02252   tickstart = HAL_GetTick();
02253
02254   /* Write input data and get output Data */
02255   if ((hcryp->Size % 4U) == 0U)
02256   {
02257     while((hcryp->CrypInCount < hcryp->Size) && (hcryp->CrypOutCount < hcryp->Size))
02258     {
02259       /* Write plain data and get cipher data */
02260       CRYP_AES_ProcessData(hcryp,Timeout);
02261
02262       /* Check for the Timeout */
02263       if(Timeout != HAL_MAX_DELAY)
02264       {
02265         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
02266         {
02267           /* Disable the CRYP peripheral clock */
02268           __HAL_CRYP_DISABLE(hcryp);
02269
02270           /* Change state & error code */
02271           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02272           hcryp->State = HAL_CRYP_STATE_READY;
02273
02274           /* Process unlocked */
02275           __HAL_UNLOCK(hcryp);
02276           return HAL_ERROR;
02277         }
02278       }
02279     }
02280   }
02281   else
02282   {
02283     payloadlength =  (((hcryp->Size)/4U)*4U) ;
02284
02285     /*Write input block in the IN FIFO without last block */
02286     while((hcryp->CrypInCount < payloadlength) && (hcryp->CrypOutCount < payloadlength))
02287     {
02288       /* Write input Data and get output Data */
02289       CRYP_AES_ProcessData(hcryp,Timeout);
02290
02291       /* Check for the Timeout */
02292       if(Timeout != HAL_MAX_DELAY)
02293       {
02294         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
02295         {
02296           /* Disable the CRYP peripheral clock */
02297           __HAL_CRYP_DISABLE(hcryp);
02298
02299           /* Change state */
02300           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02301           hcryp->State = HAL_CRYP_STATE_READY;
02302
02303           /* Process unlocked */
02304           __HAL_UNLOCK(hcryp);
02305           return HAL_ERROR;
02306         }
02307       }
02308     }
02309     /*  Workaround 2 :  CRYP1 & AES generates correct TAG for GCM mode only when input block size is multiple of
02310     128 bits. If lthe size of the last block of payload is inferior to 128 bits, when GCM encryption
02311     is selected, then the TAG message will be wrong.*/
02312     CRYP_Workaround(hcryp,Timeout);
02313   }
02314
02315   /* Return function status */
02316   return HAL_OK;
02317 }
02318
02319 /**
02320   * @brief  Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode
02321   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02322   *         the configuration information for CRYP module
02323   * @retval HAL status
02324   */
02325 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
02326 {
02327   __IO uint32_t count = 0U;
02328
02329   /*  Reset CrypHeaderCount */
02330   hcryp->CrypHeaderCount =0U;
02331
02332   /******************************* Init phase *********************************/
02333
02334   CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
02335
02336   /* Set the key */
02337   CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02338
02339   /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
02340   hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
02341   hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
02342   hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
02343   hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
02344
02345   /* Enable the CRYP peripheral */
02346   __HAL_CRYP_ENABLE(hcryp);
02347
02348   /*Wait for the CRYPEN bit to be cleared*/
02349   count = CRYP_TIMEOUT_GCMCCMINITPHASE;
02350   do
02351   {
02352     if(count-- == 0U)
02353     {
02354       /* Disable the CRYP peripheral clock */
02355       __HAL_CRYP_DISABLE(hcryp);
02356
02357       /* Change state */
02358       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02359       hcryp->State = HAL_CRYP_STATE_READY;
02360
02361       /* Process unlocked */
02362       __HAL_UNLOCK(hcryp);
02363       return HAL_ERROR;
02364     }
02365   }
02366   while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
02367
02368   /***************************** Header phase *********************************/
02369
02370   /* Select header phase */
02371   CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
02372
02373   /* Enable interrupts */
02374   __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
02375
02376   /* Enable CRYP */
02377   __HAL_CRYP_ENABLE(hcryp);
02378
02379   /* Return function status */
02380   return HAL_OK;
02381 }
02382
02383
02384 /**
02385   * @brief  Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA
02386   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02387   *         the configuration information for CRYP module
02388   * @retval HAL status
02389   */
02390 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
02391 {
02392   __IO uint32_t count = 0U;
02393   uint32_t payloadlength = 0U;
02394
02395   /*  Reset CrypHeaderCount */
02396   hcryp->CrypHeaderCount = 0U;
02397
02398   /*************************** Init phase ************************************/
02399
02400   CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
02401
02402   /* Set the key */
02403   CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02404
02405   /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
02406   hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
02407   hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
02408   hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
02409   hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
02410
02411   /* Enable the CRYP peripheral */
02412   __HAL_CRYP_ENABLE(hcryp);
02413
02414   /*Wait for the CRYPEN bit to be cleared*/
02415   count = CRYP_TIMEOUT_GCMCCMINITPHASE;
02416   do
02417   {
02418     if(count-- == 0U)
02419     {
02420       /* Disable the CRYP peripheral clock */
02421       __HAL_CRYP_DISABLE(hcryp);
02422
02423       /* Change state */
02424       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02425       hcryp->State = HAL_CRYP_STATE_READY;
02426
02427       /* Process unlocked */
02428       __HAL_UNLOCK(hcryp);
02429       return HAL_ERROR;
02430     }
02431   }
02432   while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
02433
02434   /************************ Header phase *************************************/
02435
02436   if(CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
02437   {
02438     return HAL_ERROR;
02439   }
02440
02441   /************************ Payload phase ************************************/
02442
02443   /* Set the phase */
02444   hcryp->Phase = CRYP_PHASE_PROCESS;
02445
02446   /* Disable the CRYP peripheral */
02447   __HAL_CRYP_DISABLE(hcryp);
02448
02449   /* Select payload phase once the header phase is performed */
02450   CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
02451
02452   if(hcryp->Size != 0U)
02453   {
02454     /* Size should be %4  otherwise Tag will  be incorrectly generated for GCM Encryption:
02455     Workaround is implemented in polling mode, so if last block of
02456     payload <128bit don't use DMA mode otherwise TAG is incorrectly generated . */
02457     /* Set the input and output addresses and start DMA transfer */
02458     if ((hcryp->Size % 4U) == 0U)
02459     {
02460       CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), hcryp->Size, (uint32_t)(hcryp->pCrypOutBuffPtr));
02461     }
02462     else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */
02463     {
02464       payloadlength =  (hcryp->Size)+(4-(hcryp->Size)%4U) ;
02465
02466       /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
02467       CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), payloadlength, (uint32_t)(hcryp->pCrypOutBuffPtr));
02468     }
02469   }
02470   else
02471   {
02472     /* Process unLocked */
02473     __HAL_UNLOCK(hcryp);
02474
02475     /* Change the CRYP state and phase */
02476     hcryp->State = HAL_CRYP_STATE_READY;
02477   }
02478
02479   /* Return function status */
02480   return HAL_OK;
02481 }
02482
02483
02484 /**
02485   * @brief  AES CCM encryption/decryption processing in polling mode
02486   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02487   *         the configuration information for CRYP module
02488   * @param  Timeout: Timeout duration
02489   * @retval HAL status
02490   */
02491 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
02492 {
02493   uint32_t tickstart = 0U;
02494   uint32_t payloadlength =0U;
02495
02496   /*  Reset CrypHeaderCount */
02497   hcryp->CrypHeaderCount = 0U;
02498
02499   /********************** Init phase ******************************************/
02500
02501   CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
02502
02503   /* Set the key */
02504   CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02505
02506   /* Set the initialization vector (IV) with CTR1 information */
02507   hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
02508   hcryp->Instance->IV0RR = hcryp->Init.B0[1];
02509   hcryp->Instance->IV1LR = hcryp->Init.B0[2];
02510   hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)|  CRYP_CCM_CTR1_2;
02511
02512   /* Enable the CRYP peripheral */
02513   __HAL_CRYP_ENABLE(hcryp);
02514
02515   /*Write  B0 packet into CRYP_DR*/
02516   if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
02517   {
02518     hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0));
02519     hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1));
02520     hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2));
02521     hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3));
02522   }
02523   else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
02524   {
02525     hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16);
02526     hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16);
02527     hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16);
02528     hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16);
02529   }
02530   else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
02531   {
02532     hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0));
02533     hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1));
02534     hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2));
02535     hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3));
02536   }
02537   else
02538   {
02539     hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0);
02540     hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1);
02541     hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2);
02542     hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3);
02543   }
02544   /* Get tick */
02545   tickstart = HAL_GetTick();
02546
02547   /*Wait for the CRYPEN bit to be cleared*/
02548   while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
02549   {
02550     /* Check for the Timeout */
02551     if(Timeout != HAL_MAX_DELAY)
02552     {
02553       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
02554       {
02555         /* Disable the CRYP peripheral clock */
02556         __HAL_CRYP_DISABLE(hcryp);
02557
02558         /* Change state */
02559         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02560         hcryp->State = HAL_CRYP_STATE_READY;
02561
02562         /* Process unlocked */
02563         __HAL_UNLOCK(hcryp);
02564         return HAL_ERROR;
02565       }
02566     }
02567   }
02568
02569   /************************* Header phase *************************************/
02570   /* Header block(B1) : associated data length expressed in bytes concatenated
02571   with Associated Data (A)*/
02572
02573   if(CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
02574   {
02575     return HAL_ERROR;
02576   }
02577   /********************** Payload phase ***************************************/
02578
02579   /* Set the phase */
02580   hcryp->Phase = CRYP_PHASE_PROCESS;
02581
02582   /* Disable the CRYP peripheral */
02583   __HAL_CRYP_DISABLE(hcryp);
02584
02585   /* Select payload phase once the header phase is performed */
02586   CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
02587
02588   /* Enable the CRYP peripheral */
02589   __HAL_CRYP_ENABLE(hcryp);
02590
02591   /* Get tick */
02592   tickstart = HAL_GetTick();
02593
02594   /* Write input data and get output data */
02595   if((hcryp->Size % 4U) == 0U)
02596   {
02597     while((hcryp->CrypInCount < hcryp->Size) && (hcryp->CrypOutCount < hcryp->Size))
02598     {
02599       /* Write plain data and get cipher data */
02600       CRYP_AES_ProcessData(hcryp,Timeout);
02601
02602       /* Check for the Timeout */
02603       if(Timeout != HAL_MAX_DELAY)
02604       {
02605         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
02606         {
02607           /* Disable the CRYP peripheral clock */
02608           __HAL_CRYP_DISABLE(hcryp);
02609
02610           /* Change state */
02611           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02612           hcryp->State = HAL_CRYP_STATE_READY;
02613
02614           /* Process unlocked */
02615           __HAL_UNLOCK(hcryp);
02616           return HAL_ERROR;
02617         }
02618       }
02619     }
02620   }
02621   else
02622   {
02623     if(hcryp->Size > 4U)
02624     {
02625       payloadlength =  (((hcryp->Size)/4)*4) ;
02626       /*Write input block in the IN FIFO without last block */
02627       while((hcryp->CrypInCount < payloadlength) && (hcryp->CrypOutCount < payloadlength))
02628       {
02629         /* Write input data and get output data */
02630         CRYP_AES_ProcessData(hcryp,Timeout);
02631
02632         /* Check for the Timeout */
02633         if(Timeout != HAL_MAX_DELAY)
02634         {
02635           if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
02636           {
02637             /* Disable the CRYP peripheral clock */
02638             __HAL_CRYP_DISABLE(hcryp);
02639
02640             /* Change state */
02641             hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02642             hcryp->State = HAL_CRYP_STATE_READY;
02643
02644             /* Process unlocked */
02645             __HAL_UNLOCK(hcryp);
02646             return HAL_ERROR;
02647           }
02648         }
02649       }
02650     }
02651     /* CRYP Workaround :  CRYP1 generates correct TAG  during CCM decryption only when ciphertext blocks size is multiple of
02652     128 bits. If lthe size of the last block of payload is inferior to 128 bits, when CCM decryption
02653     is selected, then the TAG message will be wrong.*/
02654     CRYP_Workaround(hcryp,Timeout);
02655   }
02656
02657   /* Return function status */
02658   return HAL_OK;
02659 }
02660
02661 /**
02662   * @brief  AES CCM encryption/decryption process in interrupt mode
02663   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02664   *         the configuration information for CRYP module
02665   * @retval HAL status
02666   */
02667 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
02668 {
02669   __IO uint32_t count = 0U;
02670
02671   /*  Reset CrypHeaderCount */
02672   hcryp->CrypHeaderCount = 0U;
02673
02674   /************ Init phase ************/
02675
02676   CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
02677
02678   /* Set the key */
02679   CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02680
02681   /* Set the initialization vector (IV) with CTR1 information */
02682   hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
02683   hcryp->Instance->IV0RR = hcryp->Init.B0[1];
02684   hcryp->Instance->IV1LR = hcryp->Init.B0[2];
02685   hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)|  CRYP_CCM_CTR1_2;
02686
02687   /* Enable the CRYP peripheral */
02688   __HAL_CRYP_ENABLE(hcryp);
02689
02690   /*Write the B0 packet into CRYP_DR*/
02691   if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
02692   {
02693     hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0));
02694     hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1));
02695     hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2));
02696     hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3));
02697   }
02698   else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
02699   {
02700     hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16);
02701     hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16);
02702     hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16);
02703     hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16);
02704   }
02705   else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
02706   {
02707     hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0));
02708     hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1));
02709     hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2));
02710     hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3));
02711   }
02712   else
02713   {
02714     hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0);
02715     hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1);
02716     hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2);
02717     hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3);
02718   }
02719   /*Wait for the CRYPEN bit to be cleared*/
02720   count = CRYP_TIMEOUT_GCMCCMINITPHASE;
02721   do
02722   {
02723     if(count-- == 0U)
02724     {
02725       /* Disable the CRYP peripheral clock */
02726       __HAL_CRYP_DISABLE(hcryp);
02727
02728       /* Change state */
02729       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02730       hcryp->State = HAL_CRYP_STATE_READY;
02731
02732       /* Process unlocked */
02733       __HAL_UNLOCK(hcryp);
02734       return HAL_ERROR;
02735     }
02736   }
02737   while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
02738
02739   /* Select header phase */
02740   CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
02741
02742   /* Enable interrupts */
02743   __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
02744
02745   /* Enable CRYP */
02746   __HAL_CRYP_ENABLE(hcryp);
02747
02748   /* Return function status */
02749   return HAL_OK;
02750 }
02751 /**
02752   * @brief  AES CCM encryption/decryption process in DMA mode
02753   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02754   *         the configuration information for CRYP module
02755   * @retval HAL status
02756   */
02757 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
02758 {
02759   uint32_t payloadlength = 0U;
02760   __IO uint32_t count    = 0U;
02761
02762   /*  Reset CrypHeaderCount */
02763   hcryp->CrypHeaderCount = 0U;
02764
02765   /************************** Init phase **************************************/
02766
02767   CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
02768
02769   /* Set the key */
02770   CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02771
02772   /* Set the initialization vector (IV) with CTR1 information */
02773   hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
02774   hcryp->Instance->IV0RR = hcryp->Init.B0[1];
02775   hcryp->Instance->IV1LR = hcryp->Init.B0[2];
02776   hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)|  CRYP_CCM_CTR1_2;
02777
02778   /* Enable the CRYP peripheral */
02779   __HAL_CRYP_ENABLE(hcryp);
02780
02781   /*Write the B0 packet into CRYP_DR*/
02782   if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
02783   {
02784     hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0));
02785     hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1));
02786     hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2));
02787     hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3));
02788   }
02789   else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
02790   {
02791     hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16);
02792     hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16);
02793     hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16);
02794     hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16);
02795   }
02796   else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
02797   {
02798     hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0));
02799     hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1));
02800     hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2));
02801     hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3));
02802   }
02803   else
02804   {
02805     hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0);
02806     hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1);
02807     hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2);
02808     hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3);
02809   }
02810
02811   /*Wait for the CRYPEN bit to be cleared*/
02812   count = CRYP_TIMEOUT_GCMCCMINITPHASE;
02813   do
02814   {
02815     if(count-- == 0U)
02816     {
02817       /* Disable the CRYP peripheral clock */
02818       __HAL_CRYP_DISABLE(hcryp);
02819
02820       /* Change state */
02821       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02822       hcryp->State = HAL_CRYP_STATE_READY;
02823
02824       /* Process unlocked */
02825       __HAL_UNLOCK(hcryp);
02826       return HAL_ERROR;
02827     }
02828   }
02829   while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
02830
02831   /********************* Header phase *****************************************/
02832
02833   if(CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
02834   {
02835     return HAL_ERROR;
02836   }
02837
02838   /******************** Payload phase *****************************************/
02839
02840   /* Set the phase */
02841   hcryp->Phase = CRYP_PHASE_PROCESS;
02842
02843   /* Disable the CRYP peripheral */
02844   __HAL_CRYP_DISABLE(hcryp);
02845
02846   /* Select payload phase once the header phase is performed */
02847   CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
02848
02849   if(hcryp->Size != 0U)
02850   {
02851     /* Size should be %4  otherwise Tag will  be incorrectly generated for GCM Encryption & CCM Decryption
02852     Workaround is implemented in polling mode, so if last block of
02853     payload <128bit don't use HAL_CRYP_AESGCM_DMA otherwise TAG is incorrectly generated for GCM Encryption. */
02854     /* Set the input and output addresses and start DMA transfer */
02855     if ((hcryp->Size % 4U) == 0U)
02856     {
02857       CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), hcryp->Size, (uint32_t)(hcryp->pCrypOutBuffPtr));
02858     }
02859     else
02860     {
02861       payloadlength =  (hcryp->Size)+(4-(hcryp->Size %4)) ;
02862
02863       /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4*/
02864       CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), payloadlength, (uint32_t)(hcryp->pCrypOutBuffPtr));
02865     }
02866   }
02867   else /*Size = 0*/
02868   {
02869     /* Process unlocked */
02870     __HAL_UNLOCK(hcryp);
02871
02872     /* Change the CRYP state and phase */
02873     hcryp->State = HAL_CRYP_STATE_READY;
02874   }
02875
02876   /* Return function status */
02877   return HAL_OK;
02878 }
02879
02880 /**
02881   * @brief  Sets the payload phase in iterrupt mode
02882   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02883   *         the configuration information for CRYP module
02884   * @retval state
02885   */
02886 static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
02887 {
02888   uint32_t loopcounter = 0U;
02889   uint32_t temp        = 0U;  /* Temporary CrypOutBuff */
02890
02891   /***************************** Payload phase *******************************/
02892
02893   if(hcryp->Size == 0U)
02894   {
02895     /* Disable interrupts */
02896     __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI| CRYP_IT_OUTI);
02897
02898     /* Process unlocked */
02899     __HAL_UNLOCK(hcryp);
02900
02901     /* Change the CRYP state */
02902     hcryp->State = HAL_CRYP_STATE_READY;
02903   }
02904
02905   else if ((hcryp->Size) - (hcryp->CrypInCount) >= 4)
02906   {
02907     /* Write the input block in the IN FIFO */
02908     hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
02909     hcryp->CrypInCount++;
02910     hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
02911     hcryp->CrypInCount++;
02912     hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
02913     hcryp->CrypInCount++;
02914     hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
02915     hcryp->CrypInCount++;
02916     if(hcryp->Size == hcryp->CrypInCount)
02917     {
02918       /* Disable interrupts */
02919       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
02920
02921       /* Call the input data transfer complete callback */
02922       HAL_CRYP_InCpltCallback(hcryp);
02923     }
02924     if(hcryp->CrypOutCount < hcryp->Size)
02925     {
02926       /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer  */
02927       temp  = hcryp->Instance->DOUT;
02928       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
02929       hcryp->CrypOutCount++;
02930       temp  = hcryp->Instance->DOUT;
02931       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
02932       hcryp->CrypOutCount++;
02933       temp  = hcryp->Instance->DOUT;
02934       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
02935       hcryp->CrypOutCount++;
02936       temp  = hcryp->Instance->DOUT;
02937       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
02938       hcryp->CrypOutCount++;
02939       if (hcryp->Size == hcryp->CrypOutCount)
02940       {
02941         /* Disable interrupts */
02942         __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
02943
02944         /* Change the CRYP state */
02945         hcryp->State = HAL_CRYP_STATE_READY;
02946
02947         /* Disable CRYP */
02948         __HAL_CRYP_DISABLE(hcryp);
02949
02950         /* Process unlocked */
02951         __HAL_UNLOCK(hcryp);
02952
02953         /* Call output transfer complete callback */
02954         HAL_CRYP_OutCpltCallback(hcryp);
02955       }
02956     }
02957   }
02958   else if ((hcryp->Size %4U )!= 0U)
02959   {
02960     /* Size should be %4  otherwise TAG will  be incorrectly generated for GCM Encryption & CCM Decryption
02961     Workaround is implemented in polling mode, so if last block of
02962     payload <128bit don't use CRYP_AESGCM_Encrypt_IT otherwise TAG is incorrectly generated. */
02963
02964     /*  Last block optionally pad the data with zeros*/
02965     for(loopcounter = 0U; loopcounter < (hcryp->Size %4 ); loopcounter++)
02966     {
02967       hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
02968       hcryp->CrypInCount++;
02969     }
02970     while(loopcounter < 4U )
02971     {
02972       /* Pad the data with zeros to have a complete block */
02973       hcryp->Instance->DIN = 0x0U;
02974       loopcounter++;
02975     }
02976     __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
02977
02978     if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != RESET)
02979     {
02980       for(loopcounter = 0U; loopcounter < 4U; loopcounter++)
02981       {
02982         /* Read the output block from the output FIFO and put them in temporary buffer */
02983         temp= hcryp->Instance->DOUT;
02984
02985         /*get CrypOutBuff from temporary buffer  */
02986         *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=temp;
02987         hcryp->CrypOutCount++;
02988       }
02989     }
02990     if(hcryp->CrypOutCount >=  hcryp->Size)
02991     {
02992       /* Disable interrupts */
02993       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI|CRYP_IT_INI);
02994
02995       /* Change the CRYP peripheral state */
02996       hcryp->State = HAL_CRYP_STATE_READY;
02997
02998       /* Process unlocked */
02999       __HAL_UNLOCK(hcryp);
03000
03001       /* Call output transfer complete callback */
03002       HAL_CRYP_OutCpltCallback(hcryp);
03003     }
03004   }
03005
03006   /* Return function status */
03007   return HAL_OK;
03008 }
03009
03010
03011 /**
03012   * @brief  Sets the header phase in polling mode
03013   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03014   *         the configuration information for CRYP module(Header & HeaderSize)
03015   * @param  Timeout: Timeout value
03016   * @retval state
03017   */
03018 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
03019 {
03020   uint32_t loopcounter = 0U;
03021
03022   /***************************** Header phase for GCM/GMAC or CCM *********************************/
03023
03024   if((hcryp->Init.HeaderSize != 0U))
03025   {
03026     /* Select header phase */
03027     CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
03028
03029     /* Enable the CRYP peripheral */
03030     __HAL_CRYP_ENABLE(hcryp);
03031
03032     if ((hcryp->Init.HeaderSize %4U )== 0U)
03033     {
03034       /* HeaderSize %4, no padding */
03035       for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4)
03036       {
03037         hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03038         hcryp->CrypHeaderCount++ ;
03039         hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03040         hcryp->CrypHeaderCount++ ;
03041         hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03042         hcryp->CrypHeaderCount++ ;
03043         hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03044         hcryp->CrypHeaderCount++ ;
03045
03046         /* Wait for IFEM to be raised */
03047         if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
03048         {
03049           /* Disable the CRYP peripheral clock */
03050           __HAL_CRYP_DISABLE(hcryp);
03051
03052           /* Change state */
03053           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03054           hcryp->State = HAL_CRYP_STATE_READY;
03055
03056           /* Process unlocked */
03057           __HAL_UNLOCK(hcryp);
03058           return HAL_ERROR;
03059         }
03060       }
03061     }
03062     else
03063     {
03064       /*Write header block in the IN FIFO without last block */
03065       for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+= 4U)
03066       {
03067         hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03068         hcryp->CrypHeaderCount++ ;
03069         hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03070         hcryp->CrypHeaderCount++ ;
03071         hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03072         hcryp->CrypHeaderCount++ ;
03073         hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03074         hcryp->CrypHeaderCount++ ;
03075
03076         /* Wait for IFEM to be raised */
03077         if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
03078         {
03079           /* Disable the CRYP peripheral clock */
03080           __HAL_CRYP_DISABLE(hcryp);
03081
03082           /* Change state */
03083           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03084           hcryp->State = HAL_CRYP_STATE_READY;
03085
03086           /* Process unlocked */
03087           __HAL_UNLOCK(hcryp);
03088           return HAL_ERROR;
03089         }
03090       }
03091       /*  Last block optionally pad the data with zeros*/
03092       for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
03093       {
03094         hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03095         hcryp->CrypHeaderCount++ ;
03096       }
03097       while(loopcounter <4U )
03098       {
03099         /* pad the data with zeros to have a complete block */
03100         hcryp->Instance->DIN = 0x0U;
03101         loopcounter++;
03102       }
03103       /* Wait for CCF IFEM to be raised */
03104       if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
03105       {
03106         /* Disable the CRYP peripheral clock */
03107         __HAL_CRYP_DISABLE(hcryp);
03108
03109         /* Change state */
03110         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03111         hcryp->State = HAL_CRYP_STATE_READY;
03112
03113         /* Process unlocked */
03114         __HAL_UNLOCK(hcryp);
03115         return HAL_ERROR;
03116       }
03117     }
03118     /* Wait until the complete message has been processed */
03119     if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
03120     {
03121       /* Disable the CRYP peripheral clock */
03122       __HAL_CRYP_DISABLE(hcryp);
03123
03124       /* Change state */
03125       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03126       hcryp->State = HAL_CRYP_STATE_READY;
03127
03128       /* Process unlocked & return error */
03129       __HAL_UNLOCK(hcryp);
03130       return HAL_ERROR;
03131     }
03132   }
03133   /* Return function status */
03134   return HAL_OK;
03135 }
03136
03137 /**
03138   * @brief  Sets the header phase when using DMA in process
03139   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03140   *         the configuration information for CRYP module(Header & HeaderSize)
03141   * @retval None
03142   */
03143 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
03144 {
03145   __IO uint32_t count  = 0U;
03146   uint32_t loopcounter = 0U;
03147
03148   /***************************** Header phase for GCM/GMAC or CCM *********************************/
03149   if((hcryp->Init.HeaderSize != 0U))
03150   {
03151     /* Select header phase */
03152     CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
03153
03154     /* Enable the CRYP peripheral */
03155     __HAL_CRYP_ENABLE(hcryp);
03156
03157     if ((hcryp->Init.HeaderSize %4U )== 0U)
03158     {
03159       /* HeaderSize %4, no padding */
03160       for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4)
03161       {
03162         hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03163         hcryp->CrypHeaderCount++ ;
03164         hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03165         hcryp->CrypHeaderCount++ ;
03166         hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03167         hcryp->CrypHeaderCount++ ;
03168         hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03169         hcryp->CrypHeaderCount++ ;
03170
03171         /* Wait for IFEM to be raised */
03172         count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
03173         do
03174         {
03175           if(count-- == 0U)
03176           {
03177             /* Disable the CRYP peripheral clock */
03178             __HAL_CRYP_DISABLE(hcryp);
03179
03180             /* Change state */
03181             hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03182             hcryp->State = HAL_CRYP_STATE_READY;
03183
03184             /* Process unlocked */
03185             __HAL_UNLOCK(hcryp);
03186             return HAL_ERROR;
03187           }
03188         }
03189         while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
03190       }
03191     }
03192     else
03193     {
03194       /*Write header block in the IN FIFO without last block */
03195       for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4 ))); loopcounter+=4)
03196       {
03197         hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03198         hcryp->CrypHeaderCount++ ;
03199         hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03200         hcryp->CrypHeaderCount++ ;
03201         hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03202         hcryp->CrypHeaderCount++ ;
03203         hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03204         hcryp->CrypHeaderCount++ ;
03205
03206         /* Wait for IFEM to be raised */
03207         count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
03208         do
03209         {
03210           if(count-- == 0U)
03211           {
03212             /* Disable the CRYP peripheral clock */
03213             __HAL_CRYP_DISABLE(hcryp);
03214
03215             /* Change state */
03216             hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03217             hcryp->State = HAL_CRYP_STATE_READY;
03218
03219             /* Process unlocked */
03220             __HAL_UNLOCK(hcryp);
03221             return HAL_ERROR;
03222           }
03223         }
03224         while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
03225       }
03226       /*  Last block optionally pad the data with zeros*/
03227       for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
03228       {
03229         hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03230         hcryp->CrypHeaderCount++ ;
03231       }
03232       while(loopcounter < 4U )
03233       {
03234         /* Pad the data with zeros to have a complete block */
03235         hcryp->Instance->DIN = 0x0U;
03236         loopcounter++;
03237       }
03238       /* Wait for IFEM to be raised */
03239       count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
03240       do
03241       {
03242         if(count-- == 0U)
03243         {
03244           /* Disable the CRYP peripheral clock */
03245           __HAL_CRYP_DISABLE(hcryp);
03246
03247           /* Change state */
03248           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03249           hcryp->State = HAL_CRYP_STATE_READY;
03250
03251           /* Process unlocked */
03252           __HAL_UNLOCK(hcryp);
03253           return HAL_ERROR;
03254         }
03255       }
03256       while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
03257     }
03258     /* Wait until the complete message has been processed */
03259     count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
03260     do
03261     {
03262       if(count-- == 0U)
03263       {
03264         /* Disable the CRYP peripheral clock */
03265         __HAL_CRYP_DISABLE(hcryp);
03266
03267         /* Change state */
03268         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03269         hcryp->State = HAL_CRYP_STATE_READY;
03270
03271         /* Process unlocked */
03272         __HAL_UNLOCK(hcryp);
03273         return HAL_ERROR;
03274       }
03275     }
03276     while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
03277   }
03278
03279   /* Return function status */
03280   return HAL_OK;
03281 }
03282
03283 /**
03284   * @brief  Sets the header phase in interrupt mode
03285   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03286   *         the configuration information for CRYP module(Header & HeaderSize)
03287   * @retval None
03288   */
03289 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
03290 {
03291   uint32_t loopcounter = 0U;
03292
03293   /***************************** Header phase *********************************/
03294
03295   if(hcryp->Init.HeaderSize ==  hcryp->CrypHeaderCount)
03296   {
03297     /* Disable interrupts */
03298     __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI );
03299
03300     /* Disable the CRYP peripheral */
03301     __HAL_CRYP_DISABLE(hcryp);
03302
03303     /* Set the phase */
03304     hcryp->Phase = CRYP_PHASE_PROCESS;
03305
03306     /* Select payload phase once the header phase is performed */
03307     CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
03308
03309     /* Enable Interrupts */
03310     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI );
03311
03312     /* Enable the CRYP peripheral */
03313     __HAL_CRYP_ENABLE(hcryp);
03314   }
03315   else if ((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount) >= 4U)
03316
03317   { /* HeaderSize %4, no padding */
03318     hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount );
03319     hcryp->CrypHeaderCount++ ;
03320     hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03321     hcryp->CrypHeaderCount++  ;
03322     hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03323     hcryp->CrypHeaderCount++ ;
03324     hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03325     hcryp->CrypHeaderCount++ ;
03326   }
03327   else
03328   {
03329     /*  Last block optionally pad the data with zeros*/
03330     for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++)
03331     {
03332       hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header+ hcryp->CrypHeaderCount);
03333       hcryp->CrypHeaderCount++ ;
03334     }
03335     while(loopcounter <4U )
03336     {
03337       /* Pad the data with zeros to have a complete block */
03338       hcryp->Instance->DIN = 0x0U;
03339       loopcounter++;
03340     }
03341   }
03342
03343   /* Return function status */
03344   return HAL_OK;
03345 }
03346
03347
03348 /**
03349   * @brief  Workaround used for GCM/CCM mode.
03350   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03351   *         the configuration information for CRYP module
03352   * @param  Timeout: Timeout value
03353   * @retval None
03354   */
03355 static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout )
03356 {
03357   uint32_t  plength = 0U;
03358   uint32_t  iv1temp = 0U;
03359   uint32_t  temp[4] = {0};
03360   uint32_t  temp2[4]= {0};
03361   uint32_t intermediate_data[4]={0};
03362   uint32_t index = 0U;
03363
03364   /* Workaround 2, case GCM encryption */
03365   if (hcryp->Init.Algorithm == CRYP_AES_GCM)
03366   {
03367     if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
03368     {/*Workaround in order to properly compute authentication tags while doing
03369       a GCM encryption with the last block of payload size inferior to 128 bits*/
03370       /* Disable CRYP to start the final phase */
03371       __HAL_CRYP_DISABLE(hcryp);
03372
03373       /*Load CRYP_IV1R register content in a temporary variable. Decrement the value
03374       by 1 and reinsert the result in CRYP_IV1R register*/
03375       hcryp->Instance->IV1RR = 0x5U;
03376       MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
03377
03378       /* Enable CRYP to start the final phase */
03379       __HAL_CRYP_ENABLE(hcryp);
03380     }
03381     /*  Last block optionally pad the data with zeros*/
03382     for(index=0; index < (hcryp->Size % 4); index ++)
03383     {
03384       /* Write the last input block in the IN FIFO */
03385       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
03386       hcryp->CrypInCount++;
03387     }
03388     while(index < 4U)
03389     {
03390       /* Pad the data with zeros to have a complete block */
03391       hcryp->Instance->DIN  = 0U;
03392       index++;
03393     }
03394     /* Wait for OFNE flag to be raised */
03395     if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
03396     {
03397       /* Disable the CRYP peripheral clock */
03398       __HAL_CRYP_DISABLE(hcryp);
03399
03400       /* Change state */
03401       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03402       hcryp->State = HAL_CRYP_STATE_READY;
03403
03404       /* Process Unlocked */
03405       __HAL_UNLOCK(hcryp);
03406       HAL_CRYP_ErrorCallback(hcryp);
03407     }
03408     if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != RESET) && (hcryp->CrypOutCount < hcryp->Size))
03409     {
03410       for(index=0U; index< 4U;index++)
03411       {
03412         /* Read the output block from the output FIFO */
03413         intermediate_data[index] = hcryp->Instance->DOUT;
03414
03415         /* Intermediate data buffer to be used in for the workaround*/
03416         *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=intermediate_data[index];
03417         hcryp->CrypOutCount++;
03418       }
03419     }
03420
03421     if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
03422     {
03423       /*workaround in order to properly compute authentication tags while doing
03424       a GCM encryption with the last block of payload size inferior to 128 bits*/
03425       /* Change the AES mode to GCM mode and Select Final phase */
03426       /* configured  CHMOD GCM   */
03427       MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_GCM);
03428
03429       /* configured  final phase  */
03430       MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
03431
03432       for (index=0U; index < (hcryp->Size % 4U); index ++)
03433       {
03434         /*Write the intermediate_data in the IN FIFO */
03435         hcryp->Instance->DIN=intermediate_data[index];
03436       }
03437       while(index < 4U)
03438       {
03439         /* Pad the data with zeros to have a complete block */
03440         hcryp->Instance->DIN  = 0x0U;
03441         index++;
03442       }
03443       /* Wait for OFNE flag to be raised */
03444       if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
03445       {
03446         /* Disable the CRYP peripheral clock */
03447         __HAL_CRYP_DISABLE(hcryp);
03448
03449         /* Change state */
03450         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03451         hcryp->State = HAL_CRYP_STATE_READY;
03452
03453         /* Process unlocked */
03454         __HAL_UNLOCK(hcryp);
03455         HAL_CRYP_ErrorCallback(hcryp);
03456       }
03457
03458       if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != RESET)
03459       {
03460         for( index=0U; index< 4U;index++)
03461         {
03462           intermediate_data[index]=hcryp->Instance->DOUT;
03463         }
03464       }
03465     }
03466   } /* End of GCM encryption */
03467   else{    /* Workaround 2, case CCM decryption, in order to properly compute
03468     authentication tags while doing a CCM decryption with the last block
03469     of payload size inferior to 128 bits*/
03470
03471     if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
03472     {
03473       iv1temp = hcryp->Instance->CSGCMCCM7R;
03474
03475       /* Disable CRYP to start the final phase */
03476       __HAL_CRYP_DISABLE(hcryp);
03477
03478       temp[0]=  hcryp->Instance->CSGCMCCM0R;
03479       temp[1]=  hcryp->Instance->CSGCMCCM1R;
03480       temp[2]=  hcryp->Instance->CSGCMCCM2R;
03481       temp[3]=  hcryp->Instance->CSGCMCCM3R;
03482
03483       hcryp->Instance->IV1RR= iv1temp;
03484
03485       /* Configured  CHMOD CTR   */
03486       MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
03487
03488       /* Enable CRYP to start the final phase */
03489       __HAL_CRYP_ENABLE(hcryp);
03490     }
03491     /*  Last block optionally pad the data with zeros*/
03492     for(index=0; index < (hcryp->Size % 4); index ++)
03493     {
03494       /* Write the last Input block in the IN FIFO */
03495       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
03496       hcryp->CrypInCount++;
03497     }
03498     while(index < 4)
03499     {
03500       /* Pad the data with zeros to have a complete block */
03501       hcryp->Instance->DIN  = 0;
03502       index++;
03503     }
03504     /* Wait for OFNE flag to be raised */
03505     if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
03506     {
03507       /* Disable the CRYP peripheral clock */
03508       __HAL_CRYP_DISABLE(hcryp);
03509
03510       /* Change state */
03511       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03512       hcryp->State = HAL_CRYP_STATE_READY;
03513
03514       /* Process Unlocked */
03515       __HAL_UNLOCK(hcryp);
03516       HAL_CRYP_ErrorCallback(hcryp);
03517     }
03518
03519     if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != RESET) && (hcryp->CrypOutCount < hcryp->Size))
03520     {
03521       for(index=0U; index< 4U;index++)
03522       {
03523         /* Read the Output block from the Output FIFO */
03524         intermediate_data[index] = hcryp->Instance->DOUT;
03525
03526         /*intermediate data buffer to be used in for the workaround*/
03527         *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=intermediate_data[index];
03528         hcryp->CrypOutCount++;
03529       }
03530     }
03531
03532     if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
03533     {
03534       temp2[0]=  hcryp->Instance->CSGCMCCM0R;
03535       temp2[1]=  hcryp->Instance->CSGCMCCM1R;
03536       temp2[2]=  hcryp->Instance->CSGCMCCM2R;
03537       temp2[3]=  hcryp->Instance->CSGCMCCM3R;
03538
03539       /* configured  CHMOD CCM   */
03540       MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CCM);
03541
03542       /* configured  Header phase  */
03543       MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_HEADER);
03544
03545       plength=(hcryp->Init.B0[3] & 0x000000FFU);
03546
03547       /*set to zero the bits corresponding to the padded bits*/
03548       for(index = (hcryp->Size % 4U); index<4U; index ++)
03549       {
03550         intermediate_data[index] =0U;
03551       }
03552
03553       if ((plength %4U)==1U)
03554       {
03555         intermediate_data[(hcryp->Size % 4U)-1U] = intermediate_data[(hcryp->Size % 4U)-1U] & 0xFF000000U;
03556       }
03557       if ((plength %4U)==2U)
03558       {
03559         intermediate_data[(hcryp->Size % 4U)-1U] = intermediate_data[(hcryp->Size % 4U)-1U] & 0xFFFF0000U;
03560       }
03561       if ((plength %4U)==3U)
03562       {
03563         intermediate_data[(hcryp->Size % 4U)-1U] = intermediate_data[(hcryp->Size % 4U)-1U] & 0xFFFFFF00U;
03564       }
03565       ;
03566       for(index=0U; index < 4U ; index ++)
03567       {
03568         intermediate_data[index] ^=  temp[index];
03569         intermediate_data[index] ^=  temp2[index];
03570       }
03571       for(index = 0U; index < 4U; index ++)
03572       {
03573         /* Write the last Input block in the IN FIFO */
03574         hcryp->Instance->DIN  = intermediate_data[index] ;
03575       }
03576
03577       /* Wait for BUSY flag to be raised */
03578       if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
03579       {
03580         /* Disable the CRYP peripheral clock */
03581         __HAL_CRYP_DISABLE(hcryp);
03582
03583         /* Change state */
03584         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03585         hcryp->State = HAL_CRYP_STATE_READY;
03586
03587         /* Process Unlocked */
03588         __HAL_UNLOCK(hcryp);
03589         HAL_CRYP_ErrorCallback(hcryp);
03590       }
03591     }
03592   } /* End of CCM WKA*/
03593
03594   /* Process Unlocked */
03595   __HAL_UNLOCK(hcryp);
03596 }
03597
03598
03599 /**
03600   * @brief  Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.
03601   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03602   *         the configuration information for CRYP module.
03603   * @param  Timeout: Timeout duration.
03604   * @retval HAL status
03605   */
03606 static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
03607 {
03608   uint32_t tickstart = 0U;
03609
03610   /* Get timeout */
03611   tickstart = HAL_GetTick();
03612
03613   while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
03614   {
03615     /* Check for the Timeout */
03616     if(Timeout != HAL_MAX_DELAY)
03617     {
03618       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
03619       {
03620         return HAL_ERROR;
03621       }
03622     }
03623   }
03624   return HAL_OK;
03625 }
03626 /**
03627   * @brief  Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.
03628   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03629   *         the configuration information for CRYP module.
03630   * @param  Timeout: Timeout duration.
03631   * @retval HAL status
03632   */
03633 static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
03634 {
03635   uint32_t tickstart = 0U;
03636
03637   /* Get timeout */
03638   tickstart = HAL_GetTick();
03639
03640   while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
03641   {
03642     /* Check for the Timeout */
03643     if(Timeout != HAL_MAX_DELAY)
03644     {
03645       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
03646       {
03647         return HAL_ERROR;
03648       }
03649     }
03650   }
03651   return HAL_OK;
03652 }
03653
03654
03655 /**
03656   * @brief  Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.
03657   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03658   *         the configuration information for CRYP module.
03659   * @param  Timeout: Timeout duration.
03660   * @retval HAL status
03661   */
03662 static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
03663 {
03664   uint32_t tickstart = 0U;
03665
03666   /* Get timeout */
03667   tickstart = HAL_GetTick();
03668
03669   while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
03670   {
03671     /* Check for the Timeout */
03672     if(Timeout != HAL_MAX_DELAY)
03673     {
03674       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
03675       {
03676         return HAL_ERROR;
03677       }
03678     }
03679   }
03680   return HAL_OK;
03681 }
03682
03683
03684 /**
03685   * @}
03686   */
03687
03688
03689
03690 /**
03691   * @}
03692   */
03693
03694 /**
03695   * @}
03696   */
03697
03698 #endif /* HAL_CRYP_MODULE_ENABLED */
03699
03700
03701 /**
03702   * @}
03703   */
03704 #endif /*  CRYP*/
03705 /**
03706   * @}
03707   */
03708
03709 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_cryp.h Source File

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stm32h7xx_hal_cryp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_cryp.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of CRYP HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_CRYP_H
00040 #define __STM32H7xx_HAL_CRYP_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32h7xx_hal_def.h"
00049
00050 /** @addtogroup STM32H7xx_HAL_Driver
00051   * @{
00052   */
00053 #if defined (CRYP)
00054 /** @addtogroup CRYP
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup CRYP_Exported_Types CRYP Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief CRYP Init Structure definition
00065   */
00066
00067 typedef struct
00068 {
00069   uint32_t DataType;                   /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
00070                                         This parameter can be a value of @ref CRYP_Data_Type */
00071   uint32_t KeySize;                    /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
00072                                             This parameter can be a value of @ref CRYP_Key_Size */
00073   uint32_t* pKey;                      /*!< The key used for encryption/decryption */
00074   uint32_t* pInitVect;                 /*!< The initialization vector used also as initialization
00075                                          counter in CTR mode */
00076   uint32_t Algorithm;                  /*!<  DES/ TDES Algorithm ECB/CBC
00077                                         AES Algorithm ECB/CBC/CTR/GCM or CCM
00078                                         This parameter can be a value of @ref CRYP_Algorithm_Mode */
00079   uint32_t* Header;                    /*!< used only in AES GCM and CCM Algorithm for authentication,
00080                                         GCM : also known as Additional Authentication Data
00081                                         CCM : named B1 composed of the associated data length and Associated Data. */
00082   uint32_t HeaderSize;                /*!< The size of header buffer in word  */
00083   uint32_t* B0;                       /*!< B0 is first authentication block used only  in AES CCM mode */
00084 }CRYP_ConfigTypeDef;
00085
00086
00087 /**
00088   * @brief  CRYP State Structure definition
00089   */
00090
00091 typedef enum
00092 {
00093   HAL_CRYP_STATE_RESET             = 0x00U,  /*!< CRYP not yet initialized or disabled  */
00094   HAL_CRYP_STATE_READY             = 0x01U,  /*!< CRYP initialized and ready for use    */
00095   HAL_CRYP_STATE_BUSY              = 0x02U  /*!< CRYP BUSY, internal processing is ongoing  */
00096 }HAL_CRYP_STATETypeDef;
00097
00098
00099 /**
00100   * @brief  CRYP handle Structure definition
00101   */
00102
00103 typedef struct
00104 {
00105
00106       CRYP_TypeDef                      *Instance;            /*!< CRYP registers base address */
00107
00108       CRYP_ConfigTypeDef                Init;             /*!< CRYP required parameters */
00109
00110       uint32_t                          *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
00111
00112       uint32_t                          *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
00113
00114       __IO uint16_t                     CrypHeaderCount;   /*!< Counter of header data */
00115
00116       __IO uint16_t                     CrypInCount;      /*!< Counter of input data */
00117
00118       __IO uint16_t                     CrypOutCount;     /*!< Counter of output data */
00119
00120       uint16_t                          Size;           /*!< length of input data in word */
00121
00122       uint32_t                          Phase;            /*!< CRYP peripheral phase */
00123
00124       DMA_HandleTypeDef                 *hdmain;          /*!< CRYP In DMA handle parameters */
00125
00126       DMA_HandleTypeDef                 *hdmaout;         /*!< CRYP Out DMA handle parameters */
00127
00128       HAL_LockTypeDef                   Lock;             /*!< CRYP locking object */
00129
00130       __IO  HAL_CRYP_STATETypeDef       State;            /*!< CRYP peripheral state */
00131
00132       __IO uint32_t                     ErrorCode;        /*!< CRYP peripheral error code */
00133
00134 }CRYP_HandleTypeDef;
00135
00136
00137 /**
00138   * @}
00139   */
00140
00141 /* Exported constants --------------------------------------------------------*/
00142 /** @defgroup CRYP_Exported_Constants CRYP Exported Constants
00143   * @{
00144   */
00145
00146 /** @defgroup CRYP_Error_Definition   CRYP Error Definition
00147   * @{
00148   */
00149 #define HAL_CRYP_ERROR_NONE              0x00000000U  /*!< No error        */
00150 #define HAL_CRYP_ERROR_WRITE             0x00000001U  /*!< Write error     */
00151 #define HAL_CRYP_ERROR_READ              0x00000002U  /*!< Read error      */
00152 #define HAL_CRYP_ERROR_DMA               0x00000004U  /*!< DMA error       */
00153 #define HAL_CRYP_ERROR_BUSY              0x00000008U  /*!< Busy flag error */
00154 #define HAL_CRYP_ERROR_TIMEOUT           0x00000010U  /*!< Timeout error */
00155 #define HAL_CRYP_ERROR_NOT_SUPPORTED     0x00000020U  /*!< Not supported mode */
00156 #define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U  /*!< Sequence are not respected only for GCM or CCM */
00157 /**
00158   * @}
00159   */
00160
00161
00162 /** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
00163   * @{
00164   */
00165
00166 #define CRYP_DES_ECB     CRYP_CR_ALGOMODE_DES_ECB
00167 #define CRYP_DES_CBC     CRYP_CR_ALGOMODE_DES_CBC
00168 #define CRYP_TDES_ECB    CRYP_CR_ALGOMODE_TDES_ECB
00169 #define CRYP_TDES_CBC    CRYP_CR_ALGOMODE_TDES_CBC
00170 #define CRYP_AES_ECB     CRYP_CR_ALGOMODE_AES_ECB
00171 #define CRYP_AES_CBC     CRYP_CR_ALGOMODE_AES_CBC
00172 #define CRYP_AES_CTR     CRYP_CR_ALGOMODE_AES_CTR
00173 #define CRYP_AES_GCM     CRYP_CR_ALGOMODE_AES_GCM
00174 #define CRYP_AES_CCM     CRYP_CR_ALGOMODE_AES_CCM
00175
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup CRYP_Key_Size CRYP Key Size
00181   * @{
00182   */
00183
00184 #define CRYP_KEYSIZE_128B         0x00000000U
00185 #define CRYP_KEYSIZE_192B         CRYP_CR_KEYSIZE_0
00186 #define CRYP_KEYSIZE_256B         CRYP_CR_KEYSIZE_1
00187
00188 /**
00189   * @}
00190   */
00191
00192 /** @defgroup CRYP_Data_Type CRYP Data Type
00193   * @{
00194   */
00195
00196 #define CRYP_DATATYPE_32B         0x00000000U
00197 #define CRYP_DATATYPE_16B         CRYP_CR_DATATYPE_0
00198 #define CRYP_DATATYPE_8B          CRYP_CR_DATATYPE_1
00199 #define CRYP_DATATYPE_1B          CRYP_CR_DATATYPE
00200
00201 /**
00202   * @}
00203   */
00204
00205 /** @defgroup CRYP_Interrupt  CRYP Interrupt
00206   * @{
00207   */
00208
00209 #define CRYP_IT_INI       CRYP_IMSCR_INIM   /*!< Input FIFO Interrupt */
00210 #define CRYP_IT_OUTI      CRYP_IMSCR_OUTIM  /*!< Output FIFO Interrupt */
00211
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup CRYP_Flags CRYP Flags
00217   * @{
00218   */
00219
00220 /* Flags in the SR register */
00221 #define CRYP_FLAG_IFEM    CRYP_SR_IFEM  /*!< Input FIFO is empty */
00222 #define CRYP_FLAG_IFNF    CRYP_SR_IFNF  /*!< Input FIFO is not Full */
00223 #define CRYP_FLAG_OFNE    CRYP_SR_OFNE  /*!< Output FIFO is not empty */
00224 #define CRYP_FLAG_OFFU    CRYP_SR_OFFU  /*!< Output FIFO is Full */
00225 #define CRYP_FLAG_BUSY    CRYP_SR_BUSY  /*!< The CRYP core is currently processing a block of data
00226                                              or a key preparation (for AES decryption). */
00227 /* Flags in the RISR register */
00228 #define CRYP_FLAG_OUTRIS  0x01000002U  /*!< Output FIFO service raw interrupt status */
00229 #define CRYP_FLAG_INRIS   0x01000001U  /*!< Input FIFO service raw interrupt status*/
00230
00231 /**
00232   * @}
00233   */
00234
00235
00236 /**
00237   * @}
00238   */
00239
00240 /* Exported macros -----------------------------------------------------------*/
00241 /** @defgroup CRYP_Exported_Macros CRYP Exported Macros
00242   * @{
00243   */
00244
00245 /**
00246   * @brief  Enable/Disable the CRYP peripheral.
00247   * @param  __HANDLE__: specifies the CRYP handle.
00248   * @retval None
00249   */
00250
00251 #define __HAL_CRYP_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  CRYP_CR_CRYPEN)
00252 #define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~CRYP_CR_CRYPEN)
00253
00254 /** @brief  Check whether the specified CRYP status flag is set or not.
00255   * @param  __FLAG__: specifies the flag to check.
00256   *         This parameter can be one of the following values for CRYP:
00257   *            @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
00258   *                                 or a key preparation (for AES decryption).
00259   *            @arg CRYP_FLAG_IFEM: Input FIFO is empty
00260   *            @arg CRYP_FLAG_IFNF: Input FIFO is not full
00261   *            @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
00262   *            @arg CRYP_FLAG_OFNE: Output FIFO is not empty
00263   *            @arg CRYP_FLAG_OFFU: Output FIFO is full
00264   *            @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
00265  * @retval The state of __FLAG__ (TRUE or FALSE).
00266   */
00267 #define CRYP_FLAG_MASK  0x0000001FU
00268
00269 #define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
00270                                                  ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
00271
00272 /** @brief  Check whether the specified CRYP interrupt is set or not.
00273   * @param  __HANDLE__: specifies the CRYP handle.
00274   * @param  __INTERRUPT__: specifies the interrupt to check.
00275   *         This parameter can be one of the following values for CRYP:
00276   *            @arg CRYP_IT_INI: Input FIFO service masked interrupt status
00277   *            @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
00278   * @retval The state of __INTERRUPT__ (TRUE or FALSE).
00279   */
00280
00281 #define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
00282
00283 /**
00284   * @brief  Enable the CRYP interrupt.
00285   * @param  __HANDLE__: specifies the CRYP handle.
00286   * @param  __INTERRUPT__: CRYP Interrupt.
00287   *         This parameter can be one of the following values for CRYP:
00288   *            @ CRYP_IT_INI : Input FIFO service interrupt mask.
00289   *            @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
00290   * @retval None
00291   */
00292
00293 #define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
00294
00295 /**
00296   * @brief  Disable the CRYP interrupt.
00297   * @param  __HANDLE__: specifies the CRYP handle.
00298   * @param  __INTERRUPT__: CRYP Interrupt.
00299   *         This parameter can be one of the following values for CRYP:
00300   *            @ CRYP_IT_INI : Input FIFO service interrupt mask.
00301   *            @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
00302   * @retval None
00303   */
00304
00305 #define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
00306
00307 /**
00308   * @}
00309   */
00310
00311 /* Include CRYP HAL Extended module */
00312 #include "stm32h7xx_hal_cryp_ex.h"
00313
00314 /* Exported functions --------------------------------------------------------*/
00315 /** @defgroup CRYP_Exported_Functions CRYP Exported Functions
00316   * @{
00317   */
00318
00319 /** @addtogroup CRYP_Exported_Functions_Group1
00320   * @{
00321   */
00322 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
00323 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
00324 void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
00325 void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
00326 HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
00327 HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
00328
00329 /**
00330   * @}
00331   */
00332
00333 /** @addtogroup CRYP_Exported_Functions_Group2
00334   * @{
00335   */
00336
00337 /* encryption/decryption ***********************************/
00338 HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
00339 HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
00340 HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
00341 HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
00342 HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
00343 HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
00344
00345 /**
00346   * @}
00347   */
00348
00349
00350 /** @addtogroup CRYP_Exported_Functions_Group3
00351   * @{
00352   */
00353 /* Interrupt Handler functions  **********************************************/
00354 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
00355 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
00356 void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
00357 void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
00358 void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
00359 uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
00360
00361 /**
00362   * @}
00363   */
00364
00365 /**
00366   * @}
00367   */
00368
00369 /* Private macros --------------------------------------------------------*/
00370 /** @defgroup CRYP_Private_Macros   CRYP Private Macros
00371   * @{
00372   */
00373
00374 /** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
00375   * @{
00376   */
00377
00378 #define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB)   || \
00379                                    ((ALGORITHM)  == CRYP_DES_CBC)   || \
00380                                    ((ALGORITHM)  == CRYP_TDES_ECB)  || \
00381                                    ((ALGORITHM)  == CRYP_TDES_CBC)  || \
00382                                    ((ALGORITHM)  == CRYP_AES_ECB)   || \
00383                                    ((ALGORITHM)  == CRYP_AES_CBC)   || \
00384                                    ((ALGORITHM)  == CRYP_AES_CTR)   || \
00385                                    ((ALGORITHM)  == CRYP_AES_GCM)   || \
00386                                    ((ALGORITHM)  == CRYP_AES_CCM))
00387
00388 #define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B)   || \
00389                                  ((KEYSIZE) == CRYP_KEYSIZE_192B)   || \
00390                                  ((KEYSIZE) == CRYP_KEYSIZE_256B))
00391
00392 #define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B)   || \
00393                                    ((DATATYPE) == CRYP_DATATYPE_16B) || \
00394                                    ((DATATYPE) == CRYP_DATATYPE_8B) || \
00395                                    ((DATATYPE) == CRYP_DATATYPE_1B))
00396
00397 /**
00398   * @}
00399   */
00400
00401 /**
00402   * @}
00403   */
00404
00405
00406 /* Private constants ---------------------------------------------------------*/
00407 /** @defgroup CRYP_Private_Constants CRYP Private Constants
00408   * @{
00409   */
00410
00411 /**
00412   * @}
00413   */
00414 /* Private defines -----------------------------------------------------------*/
00415 /** @defgroup CRYP_Private_Defines CRYP Private Defines
00416   * @{
00417   */
00418
00419 /**
00420   * @}
00421   */
00422
00423 /* Private variables ---------------------------------------------------------*/
00424 /** @defgroup CRYP_Private_Variables CRYP Private Variables
00425   * @{
00426   */
00427
00428 /**
00429   * @}
00430   */
00431 /* Private functions prototypes ----------------------------------------------*/
00432 /** @defgroup CRYP_Private_Functions_Prototypes CRYP Private Functions Prototypes
00433   * @{
00434   */
00435
00436 /**
00437   * @}
00438   */
00439
00440 /* Private functions ---------------------------------------------------------*/
00441 /** @defgroup CRYP_Private_Functions CRYP Private Functions
00442   * @{
00443   */
00444
00445 /**
00446   * @}
00447   */
00448
00449
00450 /**
00451   * @}
00452   */
00453
00454
00455 #endif /* CRYP */
00456 /**
00457   * @}
00458   */
00459
00460 #ifdef __cplusplus
00461 }
00462 #endif
00463
00464 #endif /* __STM32H7xx_HAL_CRYP_H */
00465
00466 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_cryp_ex.c Source File

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stm32h7xx_hal_cryp_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_cryp_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Extended CRYP HAL module driver
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of CRYP extension peripheral:
00010   *           + Extended AES processing functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                      ##### How to use this driver #####
00015   ==============================================================================
00016     [..]
00017     The CRYP extension HAL driver can be used after AES-GCM or AES-CCM
00018     Encryption/Decryption to get the authentication messages.
00019
00020   @endverbatim
00021   ******************************************************************************
00022   * @attention
00023   *
00024   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00025   *
00026   * Redistribution and use in source and binary forms, with or without modification,
00027   * are permitted provided that the following conditions are met:
00028   *   1. Redistributions of source code must retain the above copyright notice,
00029   *      this list of conditions and the following disclaimer.
00030   *   2. Redistributions in binary form must reproduce the above copyright notice,
00031   *      this list of conditions and the following disclaimer in the documentation
00032   *      and/or other materials provided with the distribution.
00033   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00034   *      may be used to endorse or promote products derived from this software
00035   *      without specific prior written permission.
00036   *
00037   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00038   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00039   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00040   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00041   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00042   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00043   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00044   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00045   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00046   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00047   *
00048   ******************************************************************************
00049   */
00050
00051 /* Includes ------------------------------------------------------------------*/
00052 #include "stm32h7xx_hal.h"
00053
00054 /** @addtogroup STM32H7xx_HAL_Driver
00055   * @{
00056   */
00057 #if defined (CRYP)
00058 /** @defgroup CRYPEx CRYPEx
00059   * @brief CRYP Extension HAL module driver.
00060   * @{
00061   */
00062
00063 #ifdef HAL_CRYP_MODULE_ENABLED
00064
00065 /* Private typedef -----------------------------------------------------------*/
00066 /* Private define ------------------------------------------------------------*/
00067 /** @addtogroup CRYPEx_Private_Defines
00068   * @{
00069   */
00070
00071 #define CRYP_PHASE_INIT                 0x00000000U
00072 #define CRYP_PHASE_HEADER               CRYP_CR_GCM_CCMPH_0
00073 #define CRYP_PHASE_PAYLOAD              CRYP_CR_GCM_CCMPH_1
00074 #define CRYP_PHASE_FINAL                CRYP_CR_GCM_CCMPH
00075
00076 #define CRYP_OPERATINGMODE_ENCRYPT      0x00000000U
00077 #define CRYP_OPERATINGMODE_DECRYPT      CRYP_CR_ALGODIR
00078
00079 #define  CRYPEx_PHASE_PROCESS       0x02U     /*!< CRYP peripheral is in processing phase */
00080 #define  CRYPEx_PHASE_FINAL         0x03U     /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */
00081
00082  /*  CTR0 information to use in CCM algorithm */
00083 #define CRYP_CCM_CTR0_0            0x07FFFFFFU
00084 #define CRYP_CCM_CTR0_3            0xFFFFFF00U
00085
00086
00087 /**
00088   * @}
00089   */
00090
00091 /* Private macro -------------------------------------------------------------*/
00092 /* Private variables ---------------------------------------------------------*/
00093 /* Private function prototypes -----------------------------------------------*/
00094
00095
00096
00097 /* Exported functions---------------------------------------------------------*/
00098 /** @addtogroup CRYPEx_Exported_Functions
00099   * @{
00100   */
00101
00102 /** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
00103  *  @brief    CRYPEx Extended processing functions.
00104  *
00105 @verbatim
00106   ==============================================================================
00107               ##### Extended AES processing functions #####
00108   ==============================================================================
00109     [..]  This section provides functions allowing to generate the authentication
00110           TAG in Polling mode
00111       (+)HAL_CRYPEx_AESGCM_GenerateAuthTAG
00112       (+)HAL_CRYPEx_AESCCM_GenerateAuthTAG
00113          they should be used after Encrypt/Decrypt operation.
00114
00115 @endverbatim
00116   * @{
00117   */
00118
00119
00120 /**
00121   * @brief  generate the GCM authentication TAG.
00122   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00123   *         the configuration information for CRYP module
00124   * @param  AuthTag: Pointer to the authentication buffer
00125   * @param  Timeout: Timeout duration
00126   * @retval HAL status
00127   */
00128 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
00129 {
00130   uint32_t tickstart = 0U;
00131   uint64_t headerlength = hcryp->Init.HeaderSize * 32U; /* Header length in bits */
00132   uint64_t inputlength = (hcryp->Size) * 32U; /* input length in bits */
00133   uint32_t tagaddr = (uint32_t)AuthTag;
00134
00135   if(hcryp->State == HAL_CRYP_STATE_READY)
00136   {
00137     /* Process locked */
00138     __HAL_LOCK(hcryp);
00139
00140     /* Change the CRYP peripheral state */
00141     hcryp->State = HAL_CRYP_STATE_BUSY;
00142
00143     /* Check if initialization phase has already been performed */
00144     if(hcryp->Phase == CRYPEx_PHASE_PROCESS)
00145     {
00146       /* Change the CRYP phase */
00147       hcryp->Phase = CRYPEx_PHASE_FINAL;
00148     }
00149     else /* Initialization phase has not been performed*/
00150     {
00151       /* Disable the Peripheral */
00152       __HAL_CRYP_DISABLE(hcryp);
00153
00154       /* Sequence error code field */
00155       hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
00156
00157       /* Change the CRYP peripheral state */
00158       hcryp->State = HAL_CRYP_STATE_READY;
00159
00160       /* Process unlocked */
00161       __HAL_UNLOCK(hcryp);
00162       return HAL_ERROR;
00163     }
00164
00165     /* Disable CRYP to start the final phase */
00166     __HAL_CRYP_DISABLE(hcryp);
00167
00168     /* Select final phase */
00169     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
00170
00171     /*ALGODIR bit must be set to ‘0’.*/
00172     hcryp->Instance->CR &=  ~CRYP_CR_ALGODIR;
00173
00174     /* Enable the CRYP peripheral */
00175     __HAL_CRYP_ENABLE(hcryp);
00176
00177     /* Write the number of bits in header (64 bits) followed by the number of bits
00178     in the payload */
00179     if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
00180     {
00181       hcryp->Instance->DIN = 0U;
00182       hcryp->Instance->DIN = __RBIT((uint32_t)(headerlength));
00183       hcryp->Instance->DIN = 0U;
00184       hcryp->Instance->DIN = __RBIT((uint32_t)(inputlength));
00185     }
00186     else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
00187     {
00188       hcryp->Instance->DIN = 0U;
00189       hcryp->Instance->DIN = __REV((uint32_t)(headerlength));
00190       hcryp->Instance->DIN = 0U;
00191       hcryp->Instance->DIN = __REV((uint32_t)(inputlength));
00192     }
00193     else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
00194     {
00195       hcryp->Instance->DIN = 0U;
00196       hcryp->Instance->DIN = __ROR((uint32_t)headerlength, 16U);
00197       hcryp->Instance->DIN = 0U;
00198       hcryp->Instance->DIN = __ROR((uint32_t)inputlength, 16U);
00199     }
00200     else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
00201     {
00202       hcryp->Instance->DIN = 0U;
00203       hcryp->Instance->DIN = (uint32_t)(headerlength);
00204       hcryp->Instance->DIN = 0U;
00205       hcryp->Instance->DIN = (uint32_t)(inputlength);
00206     }
00207
00208     /* Wait for OFNE flag to be raised */
00209     tickstart = HAL_GetTick();
00210     while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
00211     {
00212       /* Check for the Timeout */
00213       if(Timeout != HAL_MAX_DELAY)
00214       {
00215         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00216         {
00217           /* Disable the CRYP Peripheral Clock */
00218           __HAL_CRYP_DISABLE(hcryp);
00219
00220           /* Change state */
00221           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
00222           hcryp->State = HAL_CRYP_STATE_READY;
00223
00224           /* Process unlocked */
00225           __HAL_UNLOCK(hcryp);
00226           return HAL_ERROR;
00227         }
00228       }
00229     }
00230
00231     /* Read the authentication TAG in the output FIFO */
00232     *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
00233     tagaddr+=4U;
00234     *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
00235     tagaddr+=4U;
00236     *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
00237     tagaddr+=4U;
00238     *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
00239
00240     /* Disable the peripheral */
00241     __HAL_CRYP_DISABLE(hcryp);
00242
00243     /* Change the CRYP peripheral state */
00244     hcryp->State = HAL_CRYP_STATE_READY;
00245
00246     /* Process unlocked */
00247     __HAL_UNLOCK(hcryp);
00248   }
00249   else
00250   {
00251     /* Busy error code field */
00252     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
00253     return HAL_ERROR;
00254   }
00255   /* Return function status */
00256   return HAL_OK;
00257 }
00258
00259 /**
00260   * @brief  AES CCM Authentication TAG generation.
00261   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00262   *         the configuration information for CRYP module
00263   * @param  AuthTag: Pointer to the authentication buffer
00264   * @param  Timeout: Timeout duration
00265   * @retval HAL status
00266   */
00267 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
00268 {
00269   uint32_t tagaddr = (uint32_t)AuthTag;
00270   uint32_t ctr0 [4]={0};
00271   uint32_t ctr0addr = (uint32_t)ctr0;
00272   uint32_t tickstart = 0U;
00273
00274   if(hcryp->State == HAL_CRYP_STATE_READY)
00275   {
00276     /* Process locked */
00277     __HAL_LOCK(hcryp);
00278
00279     /* Change the CRYP peripheral state */
00280     hcryp->State = HAL_CRYP_STATE_BUSY;
00281
00282     /* Check if initialization phase has already been performed */
00283     if(hcryp->Phase == CRYPEx_PHASE_PROCESS)
00284     {
00285       /* Change the CRYP phase */
00286       hcryp->Phase = CRYPEx_PHASE_FINAL;
00287     }
00288     else /* Initialization phase has not been performed*/
00289     {
00290       /* Disable the peripheral */
00291       __HAL_CRYP_DISABLE(hcryp);
00292
00293       /* Sequence error code field */
00294      hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
00295
00296      /* Change the CRYP peripheral state */
00297       hcryp->State = HAL_CRYP_STATE_READY;
00298
00299       /* Process unlocked */
00300       __HAL_UNLOCK(hcryp);
00301       return HAL_ERROR;
00302     }
00303
00304     /* Disable CRYP to start the final phase */
00305     __HAL_CRYP_DISABLE(hcryp);
00306
00307     /* Select final phase & ALGODIR bit must be set to ‘0’. */
00308     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH|CRYP_CR_ALGODIR, CRYP_PHASE_FINAL|CRYP_OPERATINGMODE_ENCRYPT);
00309
00310     /* Enable the CRYP peripheral */
00311     __HAL_CRYP_ENABLE(hcryp);
00312
00313     /* Write the counter block in the IN FIFO, CTR0 information from B0
00314     data has to be swapped according to the DATATYPE*/
00315     ctr0[0]=(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0;
00316     ctr0[1]=hcryp->Init.B0[1];
00317     ctr0[2]=hcryp->Init.B0[2];
00318     ctr0[3]=hcryp->Init.B0[3] &  CRYP_CCM_CTR0_3;
00319
00320     if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
00321     {
00322       hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
00323       ctr0addr+=4;
00324       hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
00325       ctr0addr+=4;
00326       hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
00327       ctr0addr+=4;
00328       hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
00329     }
00330     else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
00331     {
00332       hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
00333       ctr0addr+=4;
00334       hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
00335       ctr0addr+=4;
00336       hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
00337       ctr0addr+=4;
00338       hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
00339     }
00340     else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
00341     {
00342       hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
00343       ctr0addr+=4;
00344       hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
00345       ctr0addr+=4;
00346       hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
00347       ctr0addr+=4;
00348       hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
00349     }
00350     else
00351     {
00352       hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
00353       ctr0addr+=4;
00354       hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
00355       ctr0addr+=4;
00356       hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
00357       ctr0addr+=4;
00358       hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);;
00359     }
00360     /* Wait for OFNE flag to be raised */
00361     tickstart = HAL_GetTick();
00362     while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
00363     {
00364       /* Check for the Timeout */
00365       if(Timeout != HAL_MAX_DELAY)
00366       {
00367         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00368         {
00369           /* Disable the CRYP peripheral Clock */
00370           __HAL_CRYP_DISABLE(hcryp);
00371
00372           /* Change state */
00373           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
00374           hcryp->State = HAL_CRYP_STATE_READY;
00375
00376           /* Process unlocked */
00377           __HAL_UNLOCK(hcryp);
00378           return HAL_ERROR;
00379         }
00380       }
00381     }
00382
00383     /* Read the Auth TAG in the IN FIFO */
00384     *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
00385     tagaddr+=4U;
00386     *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
00387     tagaddr+=4U;
00388     *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
00389     tagaddr+=4U;
00390     *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
00391
00392     /* Change the CRYP peripheral state */
00393     hcryp->State = HAL_CRYP_STATE_READY;
00394
00395     /* Process unlocked */
00396     __HAL_UNLOCK(hcryp);
00397
00398     /* Disable CRYP  */
00399     __HAL_CRYP_DISABLE(hcryp);
00400   }
00401   else
00402   {
00403     /* Busy error code field */
00404     hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
00405     return HAL_ERROR;
00406   }
00407   /* Return function status */
00408   return HAL_OK;
00409 }
00410
00411 /**
00412   * @}
00413   */
00414
00415
00416 #endif /* HAL_CRYP_MODULE_ENABLED */
00417
00418 /**
00419   * @}
00420   */
00421 #endif /*  CRYP*/
00422 /**
00423   * @}
00424   */
00425
00426 /**
00427   * @}
00428   */
00429 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_cryp_ex.h Source File

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stm32h7xx_hal_cryp_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_cryp_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of CRYP HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_CRYP_EX_H
00040 #define __STM32H7xx_HAL_CRYP_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052 #if defined (CRYP)
00053 /** @addtogroup CRYPEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059
00060  /* Private types -------------------------------------------------------------*/
00061 /** @defgroup CRYPEx_Private_Types CRYPEx Private Types
00062   * @{
00063   */
00064
00065 /**
00066   * @}
00067   */
00068
00069 /* Private variables ---------------------------------------------------------*/
00070 /** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
00071   * @{
00072   */
00073
00074 /**
00075   * @}
00076   */
00077
00078 /* Private constants ---------------------------------------------------------*/
00079 /** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
00080   * @{
00081   */
00082
00083 /**
00084   * @}
00085   */
00086
00087 /* Private macros ------------------------------------------------------------*/
00088 /** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
00089   * @{
00090   */
00091
00092  /**
00093   * @}
00094   */
00095
00096 /* Private functions ---------------------------------------------------------*/
00097 /** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
00098   * @{
00099   */
00100
00101 /**
00102   * @}
00103   */
00104
00105 /* Exported functions --------------------------------------------------------*/
00106 /** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
00107   * @{
00108   */
00109
00110 /** @addtogroup CRYPEx_Exported_Functions_Group1
00111   * @{
00112   */
00113 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
00114 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
00115
00116
00117 /**
00118   * @}
00119   */
00120
00121
00122 /**
00123   * @}
00124   */
00125
00126 /**
00127   * @}
00128   */
00129 #endif /* CRYP */
00130 /**
00131   * @}
00132   */
00133
00134
00135 #ifdef __cplusplus
00136 }
00137 #endif
00138
00139 #endif /* __STM32H7xx_HAL_CRYP_EX_H */
00140
00141 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dac.c Source File

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stm32h7xx_hal_dac.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dac.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   DAC HAL module driver.
00008   *         This file provides firmware functions to manage the following
00009   *         functionalities of the Digital to Analog Converter (DAC) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Errors functions
00014   *
00015   *
00016   @verbatim
00017   ==============================================================================
00018                       ##### DAC Peripheral features #####
00019   ==============================================================================
00020     [..]
00021       *** DAC Channels ***
00022       ====================
00023     [..]
00024     STM32H7 devices integrate two 12-bit Digital Analog Converters.
00025
00026     The 2 converters (i.e. channel1 & channel2) can be used independently or simultaneously (dual mode):
00027       (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip
00028           peripherals (ex. OPAMPs, comparators).
00029       (#) DAC channel2 with DAC_OUT2 (PA5) as output or connected to on-chip
00030           peripherals (ex. OPAMPs, comparators).
00031
00032       *** DAC Triggers ***
00033       ====================
00034     [..]
00035     Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
00036     and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
00037     [..]
00038     Digital to Analog conversion can be triggered by:
00039       (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
00040           The used pin (GPIOx_PIN_9) must be configured in input mode.
00041
00042
00043       (#) Timers TRGO:TIM1,TIM2,TIM4, TIM5, TIM6, TIM7,TIM8 and TIM15
00044           (DAC_TRIGGER_T1_TRGO, DAC_TRIGGER_T2_TRGO...)
00045
00046       (#) Timers TRGO: HRTIM1,LPTIM1,LPTIM2
00047       (DAC_TRIGGER_HR1_TRGO1,DAC_TRIGGER_HR1_TRGO2,DAC_TRIGGER_LP1_OUT,DAC_TRIGGER_LP2_OUT)
00048       (#) Software using DAC_TRIGGER_SOFTWARE
00049
00050       *** DAC Buffer mode feature ***
00051       ===============================
00052       [..]
00053       Each DAC channel integrates an output buffer that can be used to
00054       reduce the output impedance, and to drive external loads directly
00055       without having to add an external operational amplifier.
00056       To enable, the output buffer use
00057       sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
00058       [..]
00059       (@) Refer to the device datasheet for more details about output
00060           impedance value with and without output buffer.
00061
00062       *** DAC connect feature ***
00063       ===============================
00064       [..]
00065       Each DAC channel can be connected internally.
00066       To connect, use
00067       sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE;
00068
00069       *** GPIO configurations guidelines ***
00070       ====================================
00071       [..]
00072       When a DAC channel is used (ex channel1 on PA4) and the other is not
00073       (ex channel2 on PA5 is configured in Analog and disabled).
00074       Channel1 may disturb channel2 as coupling effect.
00075       Note that there is no coupling on channel2 as soon as channel2 is turned on.
00076       Coupling on adjacent channel could be avoided as follows:
00077       when unused PA5 is configured as INPUT PULL-UP or DOWN.
00078       PA5 is configured in ANALOG just before it is turned on.
00079
00080       *** DAC Sample and Hold feature ***
00081       ===================================
00082       [..]
00083       For each converter, 2 modes are supported: normal mode and
00084       "sample and hold" mode (i.e. low power mode).
00085       In the sample and hold mode, the DAC core converts data, then holds the
00086       converted voltage on a capacitor. When not converting, the DAC cores and
00087       buffer are completely turned off between samples and the DAC output is
00088       tri-stated, therefore  reducing the overall power consumption. A new
00089       stabilization period is needed before each new conversion.
00090       [..]
00091       The sample and hold allow setting internal or external voltage @
00092       low power consumption cost (output value can be at any given rate either
00093       by CPU or DMA).
00094       [..]
00095       The Sample and hold block and registers uses either LSI & run in
00096       several power modes: run mode, sleep mode & stop mode.
00097
00098       To enable Sample and Hold mode ,enable LSI using HAL_RCC_OscConfig with
00099     RCC_OSCILLATORTYPE_LSI & RCC_LSI_ON parameters.
00100
00101       Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE
00102          & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
00103            DAC_HoldTime & DAC_RefreshTime.
00104
00105
00106        *** DAC calibration feature ***
00107        ===================================
00108       [..]
00109        (#)  The 2 converters (channel1 & channel2) provide calibration capabilities.
00110        (++) Calibration aims at correcting some offset of output buffer.
00111        (++) The DAC uses either factory calibration settings OR user defined
00112            calibration (trimming) settings (i.e. trimming mode).
00113        (++) The user defined settings can be figured out using self calibration
00114            handled by HAL_DACEx_SelfCalibrate.
00115        (++) HAL_DACEx_SelfCalibrate:
00116        (+++) Runs automatically the calibration.
00117        (+++) Enables the user trimming mode
00118        (+++) Updates a structure with trimming values with fresh calibration
00119             results.
00120             The user may store the calibration results for larger
00121             (ex monitoring the trimming as a function of temperature
00122             for instance)
00123
00124        *** DAC wave generation feature ***
00125        ===================================
00126        [..]
00127        Both DAC channels can be used to generate:
00128          (#) Noise wave
00129          (#) Triangle wave
00130
00131        *** DAC data format ***
00132        =======================
00133        [..]
00134        The DAC data format can be:
00135          (#) 8-bit right alignment using DAC_ALIGN_8B_R
00136          (#) 12-bit left alignment using DAC_ALIGN_12B_L
00137          (#) 12-bit right alignment using DAC_ALIGN_12B_R
00138
00139        *** DAC data value to voltage correspondence ***
00140        ================================================
00141        [..]
00142        The analog output voltage on each DAC channel pin is determined
00143        by the following equation:
00144        [..]
00145        DAC_OUTx = VREF+ * DOR / 4095
00146        (+) with  DOR is the Data Output Register
00147        [..]
00148           VREF+ is the input voltage reference (refer to the device datasheet)
00149        [..]
00150         e.g. To set DAC_OUT1 to 0.7V:
00151        (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
00152
00153        *** DMA requests  ***
00154        =====================
00155        [..]
00156        A DMA request can be generated when an external trigger (but not
00157        a software trigger) occurs if DMA requests are enabled using
00158        HAL_DAC_Start_DMA().
00159        DMA requests are mapped as following:
00160       (#) DAC channel1: mapped on DMA_REQUEST_DAC1
00161       (#) DAC channel2: mapped on DMA_REQUEST_DAC2
00162       [..]
00163     -@- For Dual mode and specific signal (Triangle and noise) generation please
00164         refer to Extended Features Driver description
00165
00166                       ##### How to use this driver #####
00167   ==============================================================================
00168     [..]
00169       (+) DAC APB clock must be enabled to get write access to DAC
00170           registers using HAL_DAC_Init()
00171       (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
00172       (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
00173       (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.
00174
00175      *** Calibration mode IO operation ***
00176      ======================================
00177      [..]
00178        (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset()
00179        (+) Run the calibration using HAL_DACEx_SelfCalibrate()
00180        (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming()
00181
00182      *** Polling mode IO operation ***
00183      =================================
00184      [..]
00185        (+) Start the DAC peripheral using HAL_DAC_Start()
00186        (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
00187        (+) Stop the DAC peripheral using HAL_DAC_Stop()
00188
00189      *** DMA mode IO operation ***
00190      ==============================
00191      [..]
00192        (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
00193            of data to be transferred at each end of conversion.
00194        (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1()or HAL_DACEx_ConvHalfCpltCallbackCh2()
00195            function is executed and user can add his own code by customization of function pointer
00196            HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2().
00197        (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DACEx_ConvHalfCpltCallbackCh2()
00198            function is executed and user can add his own code by customization of function pointer
00199            HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2().
00200        (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
00201             add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1.
00202        (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
00203            HAL_DAC_DMAUnderrunCallbackCh1()or HAL_DACEx_DMAUnderrunCallbackCh2()
00204            function is executed and user can add his own code by customization of function pointer
00205            HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()and
00206            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1().
00207        (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
00208
00209      *** DAC HAL driver macros list ***
00210      =============================================
00211      [..]
00212        Below the list of most used macros in DAC HAL driver.
00213
00214       (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
00215       (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
00216       (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
00217       (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
00218
00219      [..]
00220       (@) You can refer to the DAC HAL driver header file for more useful macros
00221
00222  @endverbatim
00223   ******************************************************************************
00224   * @attention
00225   *
00226   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00227   *
00228   * Redistribution and use in source and binary forms, with or without modification,
00229   * are permitted provided that the following conditions are met:
00230   *   1. Redistributions of source code must retain the above copyright notice,
00231   *      this list of conditions and the following disclaimer.
00232   *   2. Redistributions in binary form must reproduce the above copyright notice,
00233   *      this list of conditions and the following disclaimer in the documentation
00234   *      and/or other materials provided with the distribution.
00235   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00236   *      may be used to endorse or promote products derived from this software
00237   *      without specific prior written permission.
00238   *
00239   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00240   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00241   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00242   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00243   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00244   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00245   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00246   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00247   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00248   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00249   *
00250   ******************************************************************************
00251   */
00252
00253
00254 /* Includes ------------------------------------------------------------------*/
00255 #include "stm32h7xx_hal.h"
00256
00257 /** @addtogroup STM32H7xx_HAL_Driver
00258   * @{
00259   */
00260
00261 /** @defgroup DAC DAC
00262   * @brief DAC driver modules
00263   * @{
00264   */
00265
00266 #ifdef HAL_DAC_MODULE_ENABLED
00267
00268 /* Private typedef -----------------------------------------------------------*/
00269 /* Private define ------------------------------------------------------------*/
00270 /* Private constants ---------------------------------------------------------*/
00271 /** @addtogroup DAC_Private_Constants DAC Private Constants
00272   * @{
00273   */
00274 #define TIMEOUT_DAC_CALIBCONFIG    ((uint32_t)1)  /* 1ms                  */
00275
00276 /* Private macro -------------------------------------------------------------*/
00277 /* Private variables ---------------------------------------------------------*/
00278 /* Private function prototypes -----------------------------------------------*/
00279 /** @defgroup DAC_Private_Functions DAC Private Functions
00280   * @{
00281   */
00282 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
00283 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
00284 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
00285
00286 /**
00287   * @}
00288   */
00289 /* Exported functions ---------------------------------------------------------*/
00290
00291 /** @defgroup DAC_Exported_Functions DAC Exported Functions
00292   * @{
00293   */
00294
00295 /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
00296  *  @brief    Initialization and Configuration functions
00297  *
00298 @verbatim
00299   ==============================================================================
00300               ##### Initialization and de-initialization functions #####
00301   ==============================================================================
00302     [..]  This section provides functions allowing to:
00303       (+) Initialize and configure the DAC.
00304       (+) De-initialize the DAC.
00305
00306 @endverbatim
00307   * @{
00308   */
00309
00310 /**
00311   * @brief  Initialize the DAC peripheral according to the specified parameters
00312   *         in the DAC_InitStruct and initialize the associated handle.
00313   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00314   *         the configuration information for the specified DAC.
00315   * @retval HAL status
00316   */
00317 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
00318 {
00319   /* Check DAC handle */
00320   if(hdac == NULL)
00321   {
00322      return HAL_ERROR;
00323   }
00324   /* Check the parameters */
00325   assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
00326
00327   if(hdac->State == HAL_DAC_STATE_RESET)
00328   {
00329   /* Allocate lock resource and initialize it */
00330     hdac->Lock = HAL_UNLOCKED;
00331     /* Init the low level hardware */
00332     HAL_DAC_MspInit(hdac);
00333   }
00334
00335   /* Initialize the DAC state*/
00336   hdac->State = HAL_DAC_STATE_BUSY;
00337
00338   /* Set DAC error code to none */
00339   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
00340
00341   /* Initialize the DAC state*/
00342   hdac->State = HAL_DAC_STATE_READY;
00343
00344   /* Return function status */
00345   return HAL_OK;
00346 }
00347
00348 /**
00349   * @brief  Deinitialize the DAC peripheral registers to their default reset values.
00350   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00351   *         the configuration information for the specified DAC.
00352   * @retval HAL status
00353   */
00354 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
00355 {
00356   /* Check DAC handle */
00357   if(hdac == NULL)
00358   {
00359      return HAL_ERROR;
00360   }
00361
00362   /* Check the parameters */
00363   assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
00364
00365   /* Change DAC state */
00366   hdac->State = HAL_DAC_STATE_BUSY;
00367
00368   /* DeInit the low level hardware */
00369   HAL_DAC_MspDeInit(hdac);
00370
00371   /* Set DAC error code to none */
00372   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
00373
00374   /* Change DAC state */
00375   hdac->State = HAL_DAC_STATE_RESET;
00376
00377   /* Release Lock */
00378   __HAL_UNLOCK(hdac);
00379
00380   /* Return function status */
00381   return HAL_OK;
00382 }
00383
00384 /**
00385   * @brief  Initialize the DAC MSP.
00386   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00387   *         the configuration information for the specified DAC.
00388   * @retval None
00389   */
00390 __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
00391 {
00392    /* Prevent unused argument(s) compilation warning */
00393     UNUSED(hdac);
00394     /* NOTE : This function should not be modified, when the callback is needed,
00395             the HAL_DAC_MspInit could be implemented in the user file
00396    */
00397 }
00398
00399 /**
00400   * @brief  DeInitialize the DAC MSP.
00401   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00402   *         the configuration information for the specified DAC.
00403   * @retval None
00404   */
00405 __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
00406 {
00407   /* Prevent unused argument(s) compilation warning */
00408     UNUSED(hdac);
00409     /* NOTE : This function should not be modified, when the callback is needed,
00410             the HAL_DAC_MspDeInit could be implemented in the user file
00411    */
00412 }
00413
00414 /**
00415   * @}
00416   */
00417
00418 /** @defgroup DAC_Exported_Functions_Group2 IO operation functions
00419  *  @brief    IO operation functions
00420  *
00421 @verbatim
00422   ==============================================================================
00423              ##### IO operation functions #####
00424   ==============================================================================
00425     [..]  This section provides functions allowing to:
00426       (+) Start conversion.
00427       (+) Stop conversion.
00428       (+) Start conversion and enable DMA transfer.
00429       (+) Stop conversion and disable DMA transfer.
00430       (+) Set the specified data holding register value for DAC channel.
00431
00432
00433 @endverbatim
00434   * @{
00435   */
00436
00437 /**
00438   * @brief  Enable DAC and start conversion of channel.
00439   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00440   *         the configuration information for the specified DAC.
00441   * @param  Channel: The selected DAC channel.
00442   *          This parameter can be one of the following values:
00443   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00444   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00445   * @retval HAL status
00446   */
00447 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
00448 {
00449
00450   /* Check the parameters */
00451   assert_param(IS_DAC_CHANNEL(Channel));
00452
00453   /* Process locked */
00454   __HAL_LOCK(hdac);
00455
00456   /* Change DAC state */
00457   hdac->State = HAL_DAC_STATE_BUSY;
00458
00459   /* Enable the Peripheral */
00460   __HAL_DAC_ENABLE(hdac, Channel);
00461
00462   if(Channel == DAC_CHANNEL_1)
00463   {
00464
00465     /* Check if software trigger enabled */
00466     if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_CR_TEN1)
00467     {
00468       /* Enable the selected DAC software conversion */
00469       SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
00470     }
00471   }
00472   else
00473   {
00474     /* Check if software trigger enabled */
00475     if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == DAC_CR_TEN2)
00476     {
00477       /* Enable the selected DAC software conversion*/
00478       SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
00479     }
00480   }
00481
00482   /* Change DAC state */
00483   hdac->State = HAL_DAC_STATE_READY;
00484
00485   /* Process unlocked */
00486   __HAL_UNLOCK(hdac);
00487
00488   /* Return function status */
00489   return HAL_OK;
00490 }
00491
00492 /**
00493   * @brief  Disable DAC and stop conversion of channel.
00494   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00495   *         the configuration information for the specified DAC.
00496   * @param  Channel: The selected DAC channel.
00497   *          This parameter can be one of the following values:
00498   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00499   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00500   * @retval HAL status
00501   */
00502 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
00503 {
00504   /* Check the parameters */
00505   assert_param(IS_DAC_CHANNEL(Channel));
00506
00507   /* Disable the Peripheral */
00508   __HAL_DAC_DISABLE(hdac, Channel);
00509
00510   /* Change DAC state */
00511   hdac->State = HAL_DAC_STATE_READY;
00512
00513   /* Return function status */
00514   return HAL_OK;
00515 }
00516
00517 /**
00518   * @brief  Enable DAC and start conversion of channel.
00519   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00520   *         the configuration information for the specified DAC.
00521   * @param  Channel: The selected DAC channel.
00522   *          This parameter can be one of the following values:
00523   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00524   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00525   * @param  pData: The destination peripheral Buffer address.
00526   * @param  Length: The length of data to be transferred from memory to DAC peripheral
00527   * @param  Alignment: Specifies the data alignment for DAC channel.
00528   *          This parameter can be one of the following values:
00529   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00530   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00531   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00532   * @retval HAL status
00533   */
00534 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
00535 {
00536   uint32_t tmpreg = 0;
00537
00538   /* Check the parameters */
00539   assert_param(IS_DAC_CHANNEL(Channel));
00540   assert_param(IS_DAC_ALIGN(Alignment));
00541
00542   /* Process locked */
00543   __HAL_LOCK(hdac);
00544
00545   /* Change DAC state */
00546   hdac->State = HAL_DAC_STATE_BUSY;
00547
00548   if(Channel == DAC_CHANNEL_1)
00549   {
00550     /* Set the DMA transfer complete callback for channel1 */
00551     hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
00552
00553     /* Set the DMA half transfer complete callback for channel1 */
00554     hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
00555
00556     /* Set the DMA error callback for channel1 */
00557     hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
00558
00559     /* Enable the selected DAC channel1 DMA request */
00560     SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
00561
00562     /* Case of use of channel 1 */
00563     switch(Alignment)
00564     {
00565       case DAC_ALIGN_12B_R:
00566         /* Get DHR12R1 address */
00567         tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
00568         break;
00569       case DAC_ALIGN_12B_L:
00570         /* Get DHR12L1 address */
00571         tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
00572         break;
00573       case DAC_ALIGN_8B_R:
00574         /* Get DHR8R1 address */
00575         tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
00576         break;
00577       default:
00578         break;
00579     }
00580   }
00581   else
00582   {
00583     /* Set the DMA transfer complete callback for channel2 */
00584     hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
00585
00586     /* Set the DMA half transfer complete callback for channel2 */
00587     hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
00588
00589     /* Set the DMA error callback for channel2 */
00590     hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
00591
00592     /* Enable the selected DAC channel2 DMA request */
00593     SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
00594
00595     /* Case of use of channel 2 */
00596     switch(Alignment)
00597     {
00598       case DAC_ALIGN_12B_R:
00599         /* Get DHR12R2 address */
00600         tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
00601         break;
00602       case DAC_ALIGN_12B_L:
00603         /* Get DHR12L2 address */
00604         tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
00605         break;
00606       case DAC_ALIGN_8B_R:
00607         /* Get DHR8R2 address */
00608         tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
00609         break;
00610       default:
00611         break;
00612     }
00613   }
00614
00615   /* Enable the DMA Stream */
00616   if(Channel == DAC_CHANNEL_1)
00617   {
00618     /* Enable the DAC DMA underrun interrupt */
00619     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
00620
00621     /* Enable the DMA Stream */
00622     HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
00623   }
00624   else
00625   {
00626     /* Enable the DAC DMA underrun interrupt */
00627     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
00628
00629     /* Enable the DMA Stream */
00630     HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
00631   }
00632
00633   /* Process Unlocked */
00634   __HAL_UNLOCK(hdac);
00635   /* Enable the Peripheral */
00636   __HAL_DAC_ENABLE(hdac, Channel);
00637
00638
00639
00640   /* Return function status */
00641   return HAL_OK;
00642 }
00643
00644 /**
00645   * @brief  Disable DAC and stop conversion of channel.
00646   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00647   *         the configuration information for the specified DAC.
00648   * @param  Channel: The selected DAC channel.
00649   *          This parameter can be one of the following values:
00650   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00651   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00652   * @retval HAL status
00653   */
00654 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
00655 {
00656    HAL_StatusTypeDef status = HAL_OK;
00657
00658   /* Check the parameters */
00659   assert_param(IS_DAC_CHANNEL(Channel));
00660
00661   /* Disable the selected DAC channel DMA request */
00662     hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
00663
00664   /* Disable the Peripheral */
00665   __HAL_DAC_DISABLE(hdac, Channel);
00666
00667   /* Disable the DMA stream */
00668   /* Channel1 is used */
00669   if (Channel == DAC_CHANNEL_1)
00670   {
00671     /* Disable the DMA stream */
00672     status = HAL_DMA_Abort(hdac->DMA_Handle1);
00673     /* Disable the DAC DMA underrun interrupt */
00674     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
00675   }
00676   else /* Channel2 is used for */
00677   {
00678     /* Disable the DMA stream */
00679     status = HAL_DMA_Abort(hdac->DMA_Handle2);
00680   /* Disable the DAC DMA underrun interrupt */
00681     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
00682   }
00683
00684   /* Check if DMA Channel effectively disabled */
00685   if (status != HAL_OK)
00686   {
00687     /* Update DAC state machine to error */
00688     hdac->State = HAL_DAC_STATE_ERROR;
00689   }
00690   else
00691   {
00692     /* Change DAC state */
00693     hdac->State = HAL_DAC_STATE_READY;
00694   }
00695
00696   /* Return function status */
00697   return status;
00698 }
00699
00700 /**
00701   * @brief  Handle DAC interrupt request
00702   *         This function uses the interruption of DMA
00703   *         underrun.
00704   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00705   *         the configuration information for the specified DAC.
00706   * @retval None
00707   */
00708 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
00709 {
00710   if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
00711   {
00712     /* Check underrun flag of DAC channel 1 */
00713     if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
00714     {
00715       /* Change DAC state to error state */
00716       hdac->State = HAL_DAC_STATE_ERROR;
00717
00718       /* Set DAC error code to chanel1 DMA underrun error */
00719       SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
00720
00721       /* Clear the underrun flag */
00722       __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
00723
00724       /* Disable the selected DAC channel1 DMA request */
00725       CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
00726
00727       /* Error callback */
00728       HAL_DAC_DMAUnderrunCallbackCh1(hdac);
00729     }
00730   }
00731   if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
00732   {
00733     /* Check underrun flag of DAC channel 1 */
00734     if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
00735     {
00736       /* Change DAC state to error state */
00737       hdac->State = HAL_DAC_STATE_ERROR;
00738
00739       /* Set DAC error code to channel2 DMA underrun error */
00740       SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
00741
00742       /* Clear the underrun flag */
00743       __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
00744
00745       /* Disable the selected DAC channel1 DMA request */
00746       CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
00747
00748       /* Error callback */
00749       HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
00750     }
00751   }
00752 }
00753
00754 /**
00755   * @brief  Set the specified data holding register value for DAC channel.
00756   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00757   *         the configuration information for the specified DAC.
00758   * @param  Channel: The selected DAC channel.
00759   *          This parameter can be one of the following values:
00760   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00761   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00762   * @param  Alignment: Specifies the data alignment.
00763   *          This parameter can be one of the following values:
00764   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00765   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00766   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00767   * @param  Data: Data to be loaded in the selected data holding register.
00768   * @retval HAL status
00769   */
00770 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
00771 {
00772   __IO uint32_t tmp = 0;
00773
00774   /* Check the parameters */
00775   assert_param(IS_DAC_CHANNEL(Channel));
00776   assert_param(IS_DAC_ALIGN(Alignment));
00777   assert_param(IS_DAC_DATA(Data));
00778
00779   tmp = (uint32_t)hdac->Instance;
00780   if(Channel == DAC_CHANNEL_1)
00781   {
00782     tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
00783   }
00784   else
00785   {
00786     tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
00787   }
00788
00789   /* Set the DAC channel selected data holding register */
00790   *(__IO uint32_t *) tmp = Data;
00791
00792   /* Return function status */
00793   return HAL_OK;
00794 }
00795
00796 /**
00797   * @brief  Conversion complete callback in non-blocking mode for Channel1
00798   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00799   *         the configuration information for the specified DAC.
00800   * @retval None
00801   */
00802 __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
00803 {
00804   /* Prevent unused argument(s) compilation warning */
00805   UNUSED(hdac);
00806
00807   /* NOTE : This function should not be modified, when the callback is needed,
00808             the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
00809    */
00810 }
00811
00812 /**
00813   * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel1
00814   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00815   *         the configuration information for the specified DAC.
00816   * @retval None
00817   */
00818 __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
00819 {
00820   /* Prevent unused argument(s) compilation warning */
00821   UNUSED(hdac);
00822
00823   /* NOTE : This function should not be modified, when the callback is needed,
00824             the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
00825    */
00826 }
00827
00828 /**
00829   * @brief  Error DAC callback for Channel1.
00830   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00831   *         the configuration information for the specified DAC.
00832   * @retval None
00833   */
00834 __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
00835 {
00836   /* Prevent unused argument(s) compilation warning */
00837   UNUSED(hdac);
00838
00839   /* NOTE : This function should not be modified, when the callback is needed,
00840             the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
00841    */
00842 }
00843
00844 /**
00845   * @brief  DMA underrun DAC callback for channel1.
00846   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00847   *         the configuration information for the specified DAC.
00848   * @retval None
00849   */
00850 __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
00851 {
00852   /* Prevent unused argument(s) compilation warning */
00853   UNUSED(hdac);
00854
00855   /* NOTE : This function should not be modified, when the callback is needed,
00856             the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
00857    */
00858 }
00859
00860 /**
00861   * @}
00862   */
00863
00864 /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
00865  *  @brief    Peripheral Control functions
00866  *
00867 @verbatim
00868   ==============================================================================
00869              ##### Peripheral Control functions #####
00870   ==============================================================================
00871     [..]  This section provides functions allowing to:
00872       (+) Configure channels.
00873       (+) Get result of conversion.
00874
00875 @endverbatim
00876   * @{
00877   */
00878
00879
00880 /**
00881   * @brief  Return the last data output value of the selected DAC channel.
00882   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00883   *         the configuration information for the specified DAC.
00884   * @param  Channel: The selected DAC channel.
00885   *          This parameter can be one of the following values:
00886   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00887   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00888   * @retval The selected DAC channel data output value.
00889   */
00890 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
00891 {
00892   /* Check the parameters */
00893   assert_param(IS_DAC_CHANNEL(Channel));
00894
00895   /* Returns the DAC channel data output register value */
00896   if(Channel == DAC_CHANNEL_1)
00897   {
00898     return hdac->Instance->DOR1;
00899   }
00900   else
00901   {
00902     return hdac->Instance->DOR2;
00903   }
00904 }
00905 /**
00906   * @brief  Configure the selected DAC channel.
00907   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00908   *         the configuration information for the specified DAC.
00909   * @param  sConfig: DAC configuration structure.
00910   * @param  Channel: The selected DAC channel.
00911   *          This parameter can be one of the following values:
00912   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00913   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00914   * @retval HAL status
00915   */
00916 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
00917 {
00918   uint32_t tmpreg1 = 0, tmpreg2 = 0;
00919   uint32_t tickstart = 0;
00920
00921   /* Check the DAC parameters */
00922   assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
00923   assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
00924   assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral));
00925   assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming));
00926   if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER)
00927   {
00928     assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue));
00929   }
00930   assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold));
00931   if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE)
00932   {
00933     assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime));
00934     assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime));
00935     assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime));
00936   }
00937   assert_param(IS_DAC_CHANNEL(Channel));
00938
00939   /* Process locked */
00940   __HAL_LOCK(hdac);
00941
00942   /* Change DAC state */
00943   hdac->State = HAL_DAC_STATE_BUSY;
00944
00945   if(sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
00946   /* Sample on old configuration */
00947   {
00948     /* SampleTime */
00949     if (Channel == DAC_CHANNEL_1)
00950     {
00951       /* Get timeout */
00952       tickstart = HAL_GetTick();
00953
00954
00955       /* SHSR1 can be written when BWST1  equals RESET */
00956       while (((hdac->Instance->SR) & DAC_SR_BWST1)!= RESET)
00957       {
00958         /* Check for the Timeout */
00959         if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
00960         {
00961           /* Update error code */
00962           SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
00963
00964           /* Change the DMA state */
00965           hdac->State = HAL_DAC_STATE_TIMEOUT;
00966
00967           return HAL_TIMEOUT;
00968         }
00969       }
00970       HAL_Delay(1);
00971       hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
00972     }
00973     else /* Channel 2 */
00974     {
00975       /* SHSR2 can be written when BWST2 equals RESET */
00976
00977       while (((hdac->Instance->SR) & DAC_SR_BWST2)!= RESET)
00978       {
00979         /* Check for the Timeout */
00980         if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
00981         {
00982           /* Update error code */
00983           SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
00984
00985           /* Change the DMA state */
00986           hdac->State = HAL_DAC_STATE_TIMEOUT;
00987
00988           return HAL_TIMEOUT;
00989         }
00990       }
00991       HAL_Delay(1);
00992       hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
00993     }
00994     /* HoldTime */
00995     hdac->Instance->SHHR = (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)<<Channel;
00996     /* RefreshTime */
00997     hdac->Instance->SHRR = (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)<<Channel;
00998   }
00999
01000   if(sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
01001   /* USER TRIMMING */
01002   {
01003   /* Get the DAC CCR value */
01004   tmpreg1 = hdac->Instance->CCR;
01005   /* Clear trimming value */
01006   tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << Channel);
01007   /* Configure for the selected trimming offset */
01008   tmpreg2 = sConfig->DAC_TrimmingValue;
01009   /* Calculate CCR register value depending on DAC_Channel */
01010   tmpreg1 |= tmpreg2 << Channel;
01011   /* Write to DAC CCR */
01012   hdac->Instance->CCR = tmpreg1;
01013   }
01014   /* else factory trimming is used (factory setting are available at reset)*/
01015   /* SW Nothing has nothing to do */
01016
01017   /* Get the DAC MCR value */
01018   tmpreg1 = hdac->Instance->MCR;
01019   /* Clear DAC_MCR_MODE2_0, DAC_MCR_MODE2_1 and DAC_MCR_MODE2_2 bits */
01020   tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << Channel);
01021   /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
01022   tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | sConfig->DAC_ConnectOnChipPeripheral);
01023   /* Calculate MCR register value depending on DAC_Channel */
01024   tmpreg1 |= tmpreg2 << Channel;
01025   /* Write to DAC MCR */
01026   hdac->Instance->MCR = tmpreg1;
01027
01028   /* DAC in normal operating mode hence clear DAC_CR_CENx bit */
01029   CLEAR_BIT (hdac->Instance->CR, DAC_CR_CEN1 << Channel);
01030
01031   /* Get the DAC CR value */
01032   tmpreg1 = hdac->Instance->CR;
01033   /* Clear TENx, TSELx, WAVEx and MAMPx bits */
01034   tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << Channel);
01035   /* Configure for the selected DAC channel: trigger */
01036   /* Set TSELx and TENx bits according to DAC_Trigger value */
01037   tmpreg2 = (sConfig->DAC_Trigger);
01038   /* Calculate CR register value depending on DAC_Channel */
01039   tmpreg1 |= tmpreg2 << Channel;
01040
01041   /* Write to DAC CR */
01042   hdac->Instance->CR = tmpreg1;
01043
01044   /* Disable wave generation */
01045   hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
01046
01047   /* Change DAC state */
01048   hdac->State = HAL_DAC_STATE_READY;
01049
01050   /* Process unlocked */
01051   __HAL_UNLOCK(hdac);
01052
01053   /* Return function status */
01054   return HAL_OK;
01055 }
01056
01057
01058
01059 /**
01060   * @}
01061   */
01062
01063 /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
01064  *  @brief   Peripheral State and Errors functions
01065  *
01066 @verbatim
01067   ==============================================================================
01068             ##### Peripheral State and Errors functions #####
01069   ==============================================================================
01070     [..]
01071     This subsection provides functions allowing to
01072       (+) Check the DAC state.
01073       (+) Check the DAC Errors.
01074
01075 @endverbatim
01076   * @{
01077   */
01078
01079 /**
01080   * @brief  return the DAC handle state
01081   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
01082   *         the configuration information for the specified DAC.
01083   * @retval HAL state
01084   */
01085 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
01086 {
01087   /* Return DAC handle state */
01088   return hdac->State;
01089 }
01090
01091 /**
01092   * @brief  Return the DAC error code
01093   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
01094   *         the configuration information for the specified DAC.
01095   * @retval DAC Error Code
01096   */
01097 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
01098 {
01099   return hdac->ErrorCode;
01100 }
01101
01102 /**
01103   * @}
01104   */
01105
01106 /**
01107   * @}
01108   */
01109
01110
01111 /** @addtogroup DAC_Private_Functions
01112   * @{
01113   */
01114
01115 /**
01116   * @brief  DMA conversion complete callback.
01117   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01118   *                the configuration information for the specified DMA module.
01119   * @retval None
01120   */
01121 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
01122 {
01123   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01124
01125   HAL_DAC_ConvCpltCallbackCh1(hdac);
01126
01127   hdac->State= HAL_DAC_STATE_READY;
01128 }
01129
01130 /**
01131   * @brief  DMA half transfer complete callback.
01132   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01133   *                the configuration information for the specified DMA module.
01134   * @retval None
01135   */
01136 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
01137 {
01138     DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01139     /* Conversion complete callback */
01140     HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
01141 }
01142
01143 /**
01144   * @brief  DMA error callback
01145   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01146   *                the configuration information for the specified DMA module.
01147   * @retval None
01148   */
01149 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
01150 {
01151   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01152
01153   /* Set DAC error code to DMA error */
01154   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
01155
01156   HAL_DAC_ErrorCallbackCh1(hdac);
01157
01158   hdac->State= HAL_DAC_STATE_READY;
01159 }
01160
01161 /**
01162   * @}
01163   */
01164
01165 /**
01166   * @}
01167   */
01168 #endif /* HAL_DAC_MODULE_ENABLED */
01169
01170 /**
01171   * @}
01172   */
01173
01174 /**
01175   * @}
01176   */
01177
01178 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dac.h Source File

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stm32h7xx_hal_dac.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dac.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of DAC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_DAC_H
00040 #define __STM32H7xx_HAL_DAC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32h7xx_hal_def.h"
00049
00050 /** @addtogroup STM32H7xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup DAC
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059
00060 /** @defgroup DAC_Exported_Types DAC Exported Types
00061   * @{
00062   */
00063
00064 /**
00065   * @brief  HAL State structures definition
00066   */
00067 typedef enum
00068 {
00069   HAL_DAC_STATE_RESET             = 0x00,  /*!< DAC not yet initialized or disabled  */
00070   HAL_DAC_STATE_READY             = 0x01,  /*!< DAC initialized and ready for use    */
00071   HAL_DAC_STATE_BUSY              = 0x02,  /*!< DAC internal processing is ongoing   */
00072   HAL_DAC_STATE_TIMEOUT           = 0x03,  /*!< DAC timeout state                    */
00073   HAL_DAC_STATE_ERROR             = 0x04   /*!< DAC error state                      */
00074
00075 }HAL_DAC_StateTypeDef;
00076
00077 /**
00078   * @brief  DAC handle Structure definition
00079   */
00080 typedef struct
00081 {
00082   DAC_TypeDef                 *Instance;     /*!< Register base address             */
00083
00084   __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
00085
00086   HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
00087
00088   DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
00089
00090   DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */
00091
00092   __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
00093
00094 }DAC_HandleTypeDef;
00095
00096 /**
00097   * @brief   DAC Configuration sample and hold Channel structure definition
00098   */
00099 typedef struct
00100 {
00101   uint32_t DAC_SampleTime ;          /*!< Specifies the Sample time for the selected channel.
00102                                           This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
00103                                           This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
00104
00105   uint32_t DAC_HoldTime ;            /*!< Specifies the hold time for the selected channel
00106                                           This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
00107                                           This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
00108
00109   uint32_t DAC_RefreshTime ;         /*!< Specifies the refresh time for the selected channel
00110                                           This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
00111                                           This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
00112 }
00113 DAC_SampleAndHoldConfTypeDef;
00114
00115 /**
00116   * @brief   DAC Configuration regular Channel structure definition
00117   */
00118 typedef struct
00119 {
00120   uint32_t DAC_SampleAndHold;            /*!< Specifies whether the DAC mode.
00121                                               This parameter can be a value of @ref DAC_SampleAndHold */
00122
00123   uint32_t DAC_Trigger;                  /*!< Specifies the external trigger for the selected DAC channel.
00124                                               This parameter can be a value of @ref DAC_trigger_selection */
00125
00126   uint32_t DAC_OutputBuffer;             /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
00127                                                This parameter can be a value of @ref DAC_output_buffer */
00128
00129   uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
00130                                               This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
00131
00132   uint32_t DAC_UserTrimming;             /*!< Specifies the trimming mode
00133                                               This parameter must be a value of @ref DAC_UserTrimming
00134                                               DAC_UserTrimming is either factory or user trimming */
00135
00136   uint32_t DAC_TrimmingValue;             /*!< Specifies the offset trimming value
00137                                                i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
00138                                                This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
00139
00140   DAC_SampleAndHoldConfTypeDef  DAC_SampleAndHoldConfig;  /*!< Sample and Hold settings */
00141
00142 }DAC_ChannelConfTypeDef;
00143
00144 /**
00145   * @}
00146   */
00147
00148 /* Exported constants --------------------------------------------------------*/
00149
00150 /** @defgroup DAC_Exported_Constants DAC Exported Constants
00151   * @{
00152   */
00153
00154 /** @defgroup DAC_Error_Code DAC Error Code
00155   * @{
00156   */
00157 #define  HAL_DAC_ERROR_NONE              0x00    /*!< No error                          */
00158 #define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01    /*!< DAC channel1 DMA underrun error   */
00159 #define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02    /*!< DAC channel2 DMA underrun error   */
00160 #define  HAL_DAC_ERROR_DMA               0x04    /*!< DMA error                         */
00161 #define  HAL_DAC_ERROR_TIMEOUT           0x08    /*!< Timeout error                     */
00162 /**
00163   * @}
00164   */
00165
00166 /** @defgroup DAC_trigger_selection DAC trigger selection
00167   * @{
00168   */
00169 #define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000)        /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
00170 #define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TEN1))     /*!< Conversion started by software trigger for DAC channel */
00171 #define DAC_TRIGGER_T1_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */
00172 #define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
00173 #define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
00174 #define DAC_TRIGGER_T5_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 |DAC_CR_TEN1))   /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
00175 #define DAC_TRIGGER_T6_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
00176 #define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
00177 #define DAC_TRIGGER_T8_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
00178 #define DAC_TRIGGER_T15_TRGO               ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
00179 #define DAC_TRIGGER_HR1_TRGO1              ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel */
00180 #define DAC_TRIGGER_HR1_TRGO2              ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel */
00181 #define DAC_TRIGGER_LP1_OUT                ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< LP1 OUT TRGO selected as external conversion trigger for DAC channel */
00182 #define DAC_TRIGGER_LP2_OUT                ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< LP2 OUT TRGO selected as external conversion trigger for DAC channel */
00183 #define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
00184 /**
00185   * @}
00186   */
00187
00188   /** @defgroup DAC_output_buffer DAC output buffer
00189   * @{
00190   */
00191 #define DAC_OUTPUTBUFFER_ENABLE            ((uint32_t)0x00000000)
00192 #define DAC_OUTPUTBUFFER_DISABLE           ((uint32_t)DAC_MCR_MODE1_1)
00193
00194   /**
00195   * @}
00196   */
00197
00198 /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
00199   * @{
00200   */
00201 #define DAC_CHIPCONNECT_DISABLE      ((uint32_t)0x00000000)
00202 #define DAC_CHIPCONNECT_ENABLE       ((uint32_t)DAC_MCR_MODE1_0)
00203
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup DAC_UserTrimming DAC User Trimming
00209   * @{
00210   */
00211
00212 #define DAC_TRIMMING_FACTORY        ((uint32_t)0x00000000)           /*!< Factory trimming */
00213 #define DAC_TRIMMING_USER           ((uint32_t)0x00000001)           /*!< User trimming */
00214
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup DAC_SampleAndHold. Mode is Sample and hold (low power or normal)
00220   * @{
00221   */
00222 #define DAC_SAMPLEANDHOLD_DISABLE     ((uint32_t)0x00000000)
00223 #define DAC_SAMPLEANDHOLD_ENABLE      ((uint32_t)DAC_MCR_MODE1_2)
00224
00225
00226 /**
00227   * @}
00228   */
00229
00230
00231 /** @defgroup DAC_Channel_selection DAC Channel selection
00232   * @{
00233   */
00234 #define DAC_CHANNEL_1                      ((uint32_t)0x00000000)
00235 #define DAC_CHANNEL_2                      ((uint32_t)0x00000010)
00236
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup DAC_data_alignment DAC data alignment
00242   * @{
00243   */
00244 #define DAC_ALIGN_12B_R                    ((uint32_t)0x00000000)
00245 #define DAC_ALIGN_12B_L                    ((uint32_t)0x00000004)
00246 #define DAC_ALIGN_8B_R                     ((uint32_t)0x00000008)
00247 /**
00248   * @}
00249   */
00250
00251 /** @defgroup DAC_flags_definition DAC flags definition
00252   * @{
00253   */
00254 #define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
00255 #define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
00256
00257 /**
00258   * @}
00259   */
00260
00261 /** @defgroup DAC_IT_definition  DAC IT definition
00262   * @{
00263   */
00264 #define DAC_IT_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
00265 #define DAC_IT_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
00266
00267 /**
00268   * @}
00269   */
00270
00271 /**
00272   * @}
00273   */
00274
00275 /* Exported macro ------------------------------------------------------------*/
00276
00277 /** @defgroup DAC_Exported_Macros DAC Exported Macros
00278   * @{
00279   */
00280
00281 /** @brief Reset DAC handle state.
00282   * @param  __HANDLE__: specifies the DAC handle.
00283   * @retval None
00284   */
00285 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
00286
00287 /** @brief Enable the DAC channel.
00288   * @param  __HANDLE__: specifies the DAC handle.
00289   * @param  __DAC_Channel__: specifies the DAC channel
00290   * @retval None
00291   */
00292 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
00293 ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << (__DAC_Channel__)))
00294
00295 /** @brief Disable the DAC channel.
00296   * @param  __HANDLE__: specifies the DAC handle
00297   * @param  __DAC_Channel__: specifies the DAC channel.
00298   * @retval None
00299   */
00300 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
00301 ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_Channel__)))
00302
00303 /** @brief Set DHR12R1 alignment.
00304   * @param  __ALIGNMENT__: specifies the DAC alignment
00305   * @retval None
00306   */
00307 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
00308
00309 /** @brief  Set DHR12R2 alignment.
00310   * @param  __ALIGNMENT__: specifies the DAC alignment
00311   * @retval None
00312   */
00313 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
00314
00315 /** @brief  Set DHR12RD alignment.
00316   * @param  __ALIGNMENT__: specifies the DAC alignment
00317   * @retval None
00318   */
00319 #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
00320
00321 /** @brief Enable the DAC interrupt.
00322   * @param  __HANDLE__: specifies the DAC handle
00323   * @param  __INTERRUPT__: specifies the DAC interrupt.
00324   *          This parameter can be any combination of the following values:
00325   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
00326   *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
00327   * @retval None
00328   */
00329 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
00330
00331 /** @brief Disable the DAC interrupt.
00332   * @param  __HANDLE__: specifies the DAC handle
00333   * @param  __INTERRUPT__: specifies the DAC interrupt.
00334   *          This parameter can be any combination of the following values:
00335   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
00336   *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
00337   * @retval None
00338   */
00339 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
00340
00341 /** @brief  Check whether the specified DAC interrupt source is enabled or not.
00342   * @param __HANDLE__: DAC handle
00343   * @param __INTERRUPT__: DAC interrupt source to check
00344   *          This parameter can be any combination of the following values:
00345   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
00346   *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
00347   * @retval State of interruption (SET or RESET)
00348   */
00349 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
00350
00351 /** @brief  Get the selected DAC's flag status.
00352   * @param  __HANDLE__: specifies the DAC handle.
00353   * @param  __FLAG__: specifies the DAC flag to get.
00354   *          This parameter can be any combination of the following values:
00355   *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
00356   *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
00357   * @retval None
00358   */
00359 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00360
00361 /** @brief  Clear the DAC's flag.
00362   * @param  __HANDLE__: specifies the DAC handle.
00363   * @param  __FLAG__: specifies the DAC flag to clear.
00364   *          This parameter can be any combination of the following values:
00365   *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
00366   *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
00367   * @retval None
00368   */
00369 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
00370
00371 /**
00372   * @}
00373   */
00374
00375 /* Private macro -------------------------------------------------------------*/
00376
00377 /** @defgroup DAC_Private_Macros DAC Private Macros
00378   * @{
00379   */
00380 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
00381                                            ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
00382
00383 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
00384                                 ((CHANNEL) == DAC_CHANNEL_2))
00385
00386 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
00387                              ((ALIGN) == DAC_ALIGN_12B_L) || \
00388                              ((ALIGN) == DAC_ALIGN_8B_R))
00389
00390 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
00391
00392 #define IS_DAC_REFRESHTIME(TIME)   ((TIME) <= 0x0000000FF)
00393
00394 /**
00395   * @}
00396   */
00397
00398 /* Include DAC HAL Extended module */
00399 #include "stm32h7xx_hal_dac_ex.h"
00400
00401 /* Exported functions --------------------------------------------------------*/
00402
00403 /** @addtogroup DAC_Exported_Functions
00404   * @{
00405   */
00406
00407 /** @addtogroup DAC_Exported_Functions_Group1
00408   * @{
00409   */
00410 /* Initialization and de-initialization functions *****************************/
00411 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
00412 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
00413 void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
00414 void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
00415
00416 /**
00417   * @}
00418   */
00419
00420 /** @addtogroup DAC_Exported_Functions_Group2
00421  * @{
00422  */
00423 /* IO operation functions *****************************************************/
00424 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
00425 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
00426 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
00427 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
00428
00429 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
00430 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
00431 void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
00432 void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
00433 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
00434 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
00435 /**
00436   * @}
00437   */
00438
00439 /** @addtogroup DAC_Exported_Functions_Group3
00440   * @{
00441   */
00442 /* Peripheral Control functions ***********************************************/
00443 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
00444 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
00445 /**
00446   * @}
00447   */
00448
00449 /** @addtogroup DAC_Exported_Functions_Group4
00450   * @{
00451   */
00452 /* Peripheral State and Error functions ***************************************/
00453 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
00454 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
00455
00456 /**
00457   * @}
00458   */
00459
00460 /**
00461   * @}
00462   */
00463
00464 /**
00465   * @}
00466   */
00467
00468 /**
00469   * @}
00470   */
00471
00472 #ifdef __cplusplus
00473 }
00474 #endif
00475
00476
00477 #endif /*__STM32H7xx_HAL_DAC_H */
00478
00479 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00480
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dac_ex.c Source File

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stm32h7xx_hal_dac_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dac_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Extended DAC HAL module driver.
00008   *         This file provides firmware functions to manage the extended
00009   *         functionalities of DAC peripheral.
00010   *
00011   *
00012   @verbatim
00013   ==============================================================================
00014                       ##### How to use this driver #####
00015   ==============================================================================
00016     [..]
00017       (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
00018           Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
00019           HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
00020       (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
00021       (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
00022
00023       (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
00024       (+) HAL_DACEx_SetUserTrimming to set user trimming value.
00025       (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
00026           after reset, user setting if HAL_DACEx_SetUserTrimming have been used
00027           at least one time after reset).
00028
00029  @endverbatim
00030   ******************************************************************************
00031   * @attention
00032   *
00033   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00034   *
00035   * Redistribution and use in source and binary forms, with or without modification,
00036   * are permitted provided that the following conditions are met:
00037   *   1. Redistributions of source code must retain the above copyright notice,
00038   *      this list of conditions and the following disclaimer.
00039   *   2. Redistributions in binary form must reproduce the above copyright notice,
00040   *      this list of conditions and the following disclaimer in the documentation
00041   *      and/or other materials provided with the distribution.
00042   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00043   *      may be used to endorse or promote products derived from this software
00044   *      without specific prior written permission.
00045   *
00046   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00047   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00048   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00049   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00050   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00051   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00052   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00053   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00054   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00055   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00056   *
00057   ******************************************************************************
00058   */
00059
00060
00061 /* Includes ------------------------------------------------------------------*/
00062 #include "stm32h7xx_hal.h"
00063
00064 /** @addtogroup STM32H7xx_HAL_Driver
00065   * @{
00066   */
00067
00068 /** @defgroup DACEx DACEx
00069   * @brief DAC Extended HAL module driver
00070   * @{
00071   */
00072
00073 #ifdef HAL_DAC_MODULE_ENABLED
00074
00075 /* Private typedef -----------------------------------------------------------*/
00076 /* Private define ------------------------------------------------------------*/
00077 /* Private macro -------------------------------------------------------------*/
00078 /* Private variables ---------------------------------------------------------*/
00079 /* Private function prototypes -----------------------------------------------*/
00080 /* Private functions ---------------------------------------------------------*/
00081 /* Exported functions --------------------------------------------------------*/
00082 /** @defgroup DACEx_Exported_Functions DACEx Exported Functions
00083   * @{
00084   */
00085
00086 /** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
00087  *  @brief    Extended IO operation functions
00088  *
00089 @verbatim
00090   ==============================================================================
00091                  ##### Extended features functions #####
00092   ==============================================================================
00093     [..]  This section provides functions allowing to:
00094       (+) Start conversion with triangle wave generation.
00095       (+) Start conversion with noise wave generation.
00096       (+) Start self calibration.
00097       (+) Set user trimming mode.
00098       (+) Get result of dual mode conversion.
00099
00100 @endverbatim
00101   * @{
00102   */
00103
00104
00105
00106 /**
00107   * @brief  Enable or disable the selected DAC channel wave generation.
00108   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00109   *         the configuration information for the specified DAC.
00110   * @param  Channel: The selected DAC channel.
00111   *          This parameter can be one of the following values:
00112   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00113   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00114   * @param  Amplitude: Select max triangle amplitude.
00115   *          This parameter can be one of the following values:
00116   *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
00117   *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
00118   *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
00119   *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
00120   *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
00121   *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
00122   *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
00123   *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
00124   *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
00125   *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
00126   *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
00127   *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
00128   * @retval HAL status
00129   */
00130 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
00131 {
00132   /* Check the parameters */
00133   assert_param(IS_DAC_CHANNEL(Channel));
00134   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
00135
00136   /* Process locked */
00137   __HAL_LOCK(hdac);
00138
00139   /* Change DAC state */
00140   hdac->State = HAL_DAC_STATE_BUSY;
00141
00142   /* Enable the triangle wave generation for the selected DAC channel */
00143   MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
00144
00145   /* Change DAC state */
00146   hdac->State = HAL_DAC_STATE_READY;
00147
00148   /* Process unlocked */
00149   __HAL_UNLOCK(hdac);
00150
00151   /* Return function status */
00152   return HAL_OK;
00153 }
00154
00155 /**
00156   * @brief  Enable or disable the selected DAC channel wave generation.
00157   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00158   *         the configuration information for the specified DAC.
00159   * @param  Channel: The selected DAC channel.
00160   *          This parameter can be one of the following values:
00161   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00162   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00163   * @param  Amplitude: Unmask DAC channel LFSR for noise wave generation.
00164   *          This parameter can be one of the following values:
00165   *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
00166   *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
00167   *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
00168   *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
00169   *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
00170   *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
00171   *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
00172   *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
00173   *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
00174   *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
00175   *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
00176   *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
00177   * @retval HAL status
00178   */
00179 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
00180 {
00181   /* Check the parameters */
00182   assert_param(IS_DAC_CHANNEL(Channel));
00183   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
00184
00185   /* Process locked */
00186   __HAL_LOCK(hdac);
00187
00188   /* Change DAC state */
00189   hdac->State = HAL_DAC_STATE_BUSY;
00190
00191   /* Enable the noise wave generation for the selected DAC channel */
00192   MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
00193
00194   /* Change DAC state */
00195   hdac->State = HAL_DAC_STATE_READY;
00196
00197   /* Process unlocked */
00198   __HAL_UNLOCK(hdac);
00199
00200   /* Return function status */
00201   return HAL_OK;
00202 }
00203
00204
00205
00206 /**
00207   * @brief  Set the specified data holding register value for dual DAC channel.
00208   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00209   *               the configuration information for the specified DAC.
00210   * @param  Alignment: Specifies the data alignment for dual channel DAC.
00211   *          This parameter can be one of the following values:
00212   *            DAC_ALIGN_8B_R: 8bit right data alignment selected
00213   *            DAC_ALIGN_12B_L: 12bit left data alignment selected
00214   *            DAC_ALIGN_12B_R: 12bit right data alignment selected
00215   * @param  Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
00216   * @param  Data2: Data for DAC Channel1 to be loaded in the selected data  holding register.
00217   * @note   In dual mode, a unique register access is required to write in both
00218   *          DAC channels at the same time.
00219   * @retval HAL status
00220   */
00221 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
00222 {
00223   uint32_t data = 0, tmp = 0;
00224
00225   /* Check the parameters */
00226   assert_param(IS_DAC_ALIGN(Alignment));
00227   assert_param(IS_DAC_DATA(Data1));
00228   assert_param(IS_DAC_DATA(Data2));
00229
00230   /* Calculate and set dual DAC data holding register value */
00231   if (Alignment == DAC_ALIGN_8B_R)
00232   {
00233     data = ((uint32_t)Data2 << 8) | Data1;
00234   }
00235   else
00236   {
00237     data = ((uint32_t)Data2 << 16) | Data1;
00238   }
00239
00240   tmp = (uint32_t)hdac->Instance;
00241   tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
00242
00243   /* Set the dual DAC selected data holding register */
00244   *(__IO uint32_t *)tmp = data;
00245
00246   /* Return function status */
00247   return HAL_OK;
00248 }
00249
00250 /**
00251   * @brief  Conversion complete callback in non-blocking mode for Channel2.
00252   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00253   *         the configuration information for the specified DAC.
00254   * @retval None
00255   */
00256 __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
00257 {
00258   /* Prevent unused argument(s) compilation warning */
00259   UNUSED(hdac);
00260
00261   /* NOTE : This function should not be modified, when the callback is needed,
00262             the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
00263    */
00264 }
00265
00266 /**
00267   * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel2.
00268   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00269   *         the configuration information for the specified DAC.
00270   * @retval None
00271   */
00272 __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
00273 {
00274   /* Prevent unused argument(s) compilation warning */
00275   UNUSED(hdac);
00276
00277   /* NOTE : This function should not be modified, when the callback is needed,
00278             the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
00279    */
00280 }
00281
00282 /**
00283   * @brief  Error DAC callback for Channel2.
00284   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00285   *         the configuration information for the specified DAC.
00286   * @retval None
00287   */
00288 __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
00289 {
00290   /* Prevent unused argument(s) compilation warning */
00291   UNUSED(hdac);
00292
00293   /* NOTE : This function should not be modified, when the callback is needed,
00294             the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
00295    */
00296 }
00297
00298 /**
00299   * @brief  DMA underrun DAC callback for channel2.
00300   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00301   *         the configuration information for the specified DAC.
00302   * @retval None
00303   */
00304 __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
00305 {
00306   /* Prevent unused argument(s) compilation warning */
00307   UNUSED(hdac);
00308
00309   /* NOTE : This function should not be modified, when the callback is needed,
00310             the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
00311    */
00312 }
00313
00314
00315 /**
00316   * @brief  Run the self calibration of one DAC channel.
00317   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00318   *         the configuration information for the specified DAC.
00319   * @param  sConfig: DAC channel configuration structure.
00320   * @param  Channel: The selected DAC channel.
00321   *          This parameter can be one of the following values:
00322   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00323   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00324   * @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
00325   * @retval HAL status
00326   * @note   Calibration runs about 7 ms.
00327   */
00328
00329 HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
00330 {
00331   HAL_StatusTypeDef status = HAL_OK;
00332
00333   __IO uint32_t tmp = 0;
00334   uint32_t trimmingvalue = 0;
00335   uint32_t delta;
00336
00337   /* store/restore channel configuration structure purpose */
00338   uint32_t oldmodeconfiguration = 0;
00339
00340   /* Check the parameters */
00341   assert_param(IS_DAC_CHANNEL(Channel));
00342
00343  /* Check the DAC handle allocation */
00344  /* Check if DAC running */
00345   if((hdac == NULL) || (hdac->State == HAL_DAC_STATE_BUSY))
00346   {
00347     status = HAL_ERROR;
00348   }
00349   else
00350   {
00351     /* Process locked */
00352     __HAL_LOCK(hdac);
00353
00354     /* Store configuration */
00355     oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << Channel));
00356
00357     /* Disable the selected DAC channel */
00358     CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_EN1 << Channel));
00359
00360     /* Set mode in MCR  for calibration */
00361      MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), 0);
00362
00363     /* Set DAC Channel1 DHR register to the middle value */
00364
00365     tmp = (uint32_t)hdac->Instance;
00366     if(Channel == DAC_CHANNEL_1)
00367     {
00368       tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
00369     }
00370     else
00371     {
00372       tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
00373     }
00374     *(__IO uint32_t *) tmp = 0x0800;
00375
00376     /* Enable the selected DAC channel calibration */
00377     /* i.e. set DAC_CR_CENx bit */
00378     SET_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel));
00379
00380     /* Init trimming counter */
00381     /* Medium value */
00382     trimmingvalue = 16;
00383     delta = 8;
00384     while (delta != 0)
00385     {
00386       /* Set candidate trimming */
00387       MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
00388
00389       /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
00390       /* i.e. minimum time needed between two calibration steps */
00391       HAL_Delay(1);
00392
00393       if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1<<Channel)) == (DAC_SR_CAL_FLAG1<<Channel))
00394       {
00395         /* DAC_SR_CAL_FLAGx is HIGH try higher trimming */
00396         trimmingvalue -= delta;
00397       }
00398       else
00399       {
00400          /* DAC_SR_CAL_FLAGx is LOW try lower trimming */
00401          trimmingvalue += delta;
00402
00403       }
00404       delta >>= 1;
00405     }
00406
00407     /* Still need to check if right calibration is current value or one step below */
00408     /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1  */
00409     /* Set candidate trimming */
00410     MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
00411
00412     /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
00413     /* i.e. minimum time needed between two calibration steps */
00414     HAL_Delay(1);
00415
00416     if (!(hdac->Instance->SR & (DAC_SR_CAL_FLAG1<<Channel)))
00417     {
00418       /* Trimming is actually one value more */
00419       trimmingvalue ++;
00420       /* Set right trimming */
00421       MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
00422     }
00423
00424     /* Disable the selected DAC channel calibration */
00425     /* i.e. clear DAC_CR_CENx bit */
00426     CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel));
00427
00428     sConfig->DAC_TrimmingValue = trimmingvalue;
00429     sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
00430
00431     /* Restore configuration */
00432     MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), oldmodeconfiguration);
00433
00434     /* Process unlocked */
00435     __HAL_UNLOCK(hdac);
00436   }
00437
00438   return status;
00439 }
00440
00441 /**
00442   * @}
00443   */
00444
00445 /**
00446   * @brief  Set the trimming mode and trimming value (user trimming mode applied).
00447   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00448   *         the configuration information for the specified DAC.
00449   * @param  sConfig: DAC configuration structure updated with new DAC trimming value.
00450   * @param  Channel: The selected DAC channel.
00451   *          This parameter can be one of the following values:
00452   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00453   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00454   * @param  NewTrimmingValue: DAC new trimming value
00455   * @retval HAL status
00456   */
00457
00458 HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
00459 {
00460   HAL_StatusTypeDef status = HAL_OK;
00461
00462   /* Check the parameters */
00463   assert_param(IS_DAC_CHANNEL(Channel));
00464   assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
00465
00466  /* Check the DAC handle allocation */
00467   if(hdac == NULL)
00468   {
00469     status = HAL_ERROR;
00470   }
00471   else
00472   {
00473
00474     /* Process locked */
00475     __HAL_LOCK(hdac);
00476
00477     /* Set new trimming */
00478     MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (NewTrimmingValue<<Channel));
00479
00480     /* Update trimming mode */
00481     sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
00482     sConfig->DAC_TrimmingValue = NewTrimmingValue;
00483
00484     /* Process unlocked */
00485     __HAL_UNLOCK(hdac);
00486
00487   }
00488   return status;
00489 }
00490
00491
00492 /**
00493   * @brief  Return the DAC trimming value.
00494   * @param  hdac : DAC handle
00495   * @param  Channel: The selected DAC channel.
00496   *          This parameter can be one of the following values:
00497   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00498   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00499   * @retval Trimming value : range: 0->31
00500   *
00501  */
00502
00503 uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
00504 {
00505   uint32_t trimmingvalue = 0;
00506
00507   /* Check the DAC handle allocation */
00508   /* And not in Reset state */
00509   if((hdac == NULL) || (hdac->State == HAL_DAC_STATE_RESET))
00510   {
00511     return HAL_ERROR;
00512   }
00513   else
00514   {
00515     /* Check the parameter */
00516     assert_param(IS_DAC_CHANNEL(Channel));
00517
00518     /* Retrieve trimming  */
00519     trimmingvalue = ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << Channel)) >> Channel);
00520   }
00521   return trimmingvalue;
00522 }
00523 /**
00524   * @}
00525   */
00526
00527
00528 /** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
00529  *  @brief    Extended Peripheral Control functions
00530  *
00531 @verbatim
00532   ==============================================================================
00533              ##### Peripheral Control functions #####
00534   ==============================================================================
00535     [..]  This section provides functions allowing to:
00536       (+) Configure channels.
00537       (+) Set the specified data holding register value for DAC channel.
00538
00539 @endverbatim
00540   * @{
00541   */
00542
00543 /**
00544   * @brief  Return the last data output value of the selected DAC channel.
00545   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00546   *         the configuration information for the specified DAC.
00547   * @retval The selected DAC channel data output value.
00548   */
00549 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
00550 {
00551   uint32_t tmp = 0;
00552
00553   tmp |= hdac->Instance->DOR1;
00554
00555   tmp |= hdac->Instance->DOR2 << 16;
00556
00557   /* Returns the DAC channel data output register value */
00558   return tmp;
00559 }
00560
00561 /**
00562   * @}
00563   */
00564
00565
00566 /* Private functions ---------------------------------------------------------*/
00567 /** @defgroup DACEx_Private_Functions DACEx private functions
00568  *  @brief    Extended private functions
00569    * @{
00570   */
00571
00572 /**
00573   * @brief  DMA conversion complete callback.
00574   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00575   *                the configuration information for the specified DMA module.
00576   * @retval None
00577   */
00578 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
00579 {
00580   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00581
00582   HAL_DACEx_ConvCpltCallbackCh2(hdac);
00583
00584   hdac->State= HAL_DAC_STATE_READY;
00585 }
00586
00587 /**
00588   * @brief  DMA half transfer complete callback.
00589   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00590   *                the configuration information for the specified DMA module.
00591   * @retval None
00592   */
00593 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
00594 {
00595     DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00596     /* Conversion complete callback */
00597     HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
00598 }
00599
00600 /**
00601   * @brief  DMA error callback.
00602   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00603   *                the configuration information for the specified DMA module.
00604   * @retval None
00605   */
00606 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
00607 {
00608   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00609
00610   /* Set DAC error code to DMA error */
00611   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
00612
00613   HAL_DACEx_ErrorCallbackCh2(hdac);
00614
00615   hdac->State= HAL_DAC_STATE_READY;
00616 }
00617
00618 /**
00619   * @}
00620   */
00621
00622 #endif /* HAL_DAC_MODULE_ENABLED */
00623
00624 /**
00625   * @}
00626   */
00627
00628 /**
00629   * @}
00630   */
00631
00632 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dac_ex.h Source File

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stm32h7xx_hal_dac_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dac_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of DAC HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_DAC_EX_H
00040 #define __STM32H7xx_HAL_DAC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup DACEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /**
00060   * @brief  HAL State structures definition
00061   */
00062
00063 /* Exported constants --------------------------------------------------------*/
00064
00065 /** @defgroup DACEx_Exported_Constants DACEx Exported Constants
00066   * @{
00067   */
00068 /** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
00069   * @{
00070   */
00071 #define DAC_LFSRUNMASK_BIT0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
00072 #define DAC_LFSRUNMASK_BITS1_0             ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
00073 #define DAC_LFSRUNMASK_BITS2_0             ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
00074 #define DAC_LFSRUNMASK_BITS3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
00075 #define DAC_LFSRUNMASK_BITS4_0             ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
00076 #define DAC_LFSRUNMASK_BITS5_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
00077 #define DAC_LFSRUNMASK_BITS6_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
00078 #define DAC_LFSRUNMASK_BITS7_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
00079 #define DAC_LFSRUNMASK_BITS8_0             ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
00080 #define DAC_LFSRUNMASK_BITS9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
00081 #define DAC_LFSRUNMASK_BITS10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
00082 #define DAC_LFSRUNMASK_BITS11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
00083 #define DAC_TRIANGLEAMPLITUDE_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
00084 #define DAC_TRIANGLEAMPLITUDE_3            ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
00085 #define DAC_TRIANGLEAMPLITUDE_7            ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
00086 #define DAC_TRIANGLEAMPLITUDE_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
00087 #define DAC_TRIANGLEAMPLITUDE_31           ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
00088 #define DAC_TRIANGLEAMPLITUDE_63           ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
00089 #define DAC_TRIANGLEAMPLITUDE_127          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
00090 #define DAC_TRIANGLEAMPLITUDE_255          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
00091 #define DAC_TRIANGLEAMPLITUDE_511          ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
00092 #define DAC_TRIANGLEAMPLITUDE_1023         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
00093 #define DAC_TRIANGLEAMPLITUDE_2047         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
00094 #define DAC_TRIANGLEAMPLITUDE_4095         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
00095 /**
00096   * @}
00097   */
00098
00099 /**
00100   * @}
00101   */
00102
00103 /* Exported macro ------------------------------------------------------------*/
00104
00105
00106 /* Private macro -------------------------------------------------------------*/
00107
00108 /** @defgroup DACEx_Private_Macros DACEx Private Macros
00109   * @{
00110   */
00111
00112 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
00113                                  ((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \
00114                                  ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
00115                                  ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
00116                                  ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
00117                                  ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
00118                                  ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
00119                                  ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
00120                                  ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
00121                                  ((TRIGGER) == DAC_TRIGGER_HR1_TRGO1) || \
00122                                  ((TRIGGER) == DAC_TRIGGER_HR1_TRGO2) || \
00123                                  ((TRIGGER) == DAC_TRIGGER_LP1_OUT) || \
00124                                  ((TRIGGER) == DAC_TRIGGER_LP2_OUT) || \
00125                                  ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
00126                                  ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
00127
00128 #define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x0000003FF)
00129
00130 #define IS_DAC_HOLDTIME(TIME)   ((TIME) <= 0x0000003FF)
00131
00132 #define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
00133                                     ((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
00134
00135
00136 #define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
00137
00138 #define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
00139
00140 #define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_DISABLE) || \
00141                                          ((CONNECT) == DAC_CHIPCONNECT_ENABLE))
00142
00143 #define IS_DAC_TRIMMING(TRIMMING)       (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
00144                                         ((TRIMMING) == DAC_TRIMMING_USER))
00145
00146 #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
00147                                                       ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
00148                                                       ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
00149                                                       ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
00150                                                       ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
00151                                                       ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
00152                                                       ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
00153                                                       ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
00154                                                       ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
00155                                                       ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
00156                                                       ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
00157                                                       ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
00158                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
00159                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
00160                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
00161                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
00162                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
00163                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
00164                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
00165                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
00166                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
00167                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
00168                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
00169                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
00170
00171
00172 /**
00173   * @}
00174   */
00175
00176 /* Exported functions --------------------------------------------------------*/
00177 /* Extended features functions ***********************************************/
00178
00179 /** @addtogroup DACEx_Exported_Functions
00180   * @{
00181   */
00182   /** @addtogroup DACEx_Exported_Functions_Group2
00183  * @{
00184  */
00185 /* IO operation functions *****************************************************/
00186
00187 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
00188 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
00189 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
00190
00191 void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
00192 void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
00193 void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
00194 void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
00195
00196 HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
00197 HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue);
00198
00199 /**
00200   * @}
00201   */
00202
00203 /** @addtogroup DACEx_Exported_Functions_Group3
00204   * @{
00205   */
00206 /* Peripheral Control functions ***********************************************/
00207
00208 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
00209 uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel);
00210
00211 /**
00212   * @}
00213   */
00214
00215 /**
00216   * @}
00217   */
00218
00219 /** @addtogroup DACEx_Private_Functions
00220   * @{
00221   */
00222
00223 /* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
00224 /* are called by HAL_DAC_Start_DMA */
00225 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
00226 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
00227 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
00228
00229 /**
00230   * @}
00231   */
00232
00233  /**
00234  * @}
00235  */
00236
00237 /**
00238   * @}
00239   */
00240
00241
00242 #ifdef __cplusplus
00243 }
00244 #endif
00245
00246 #endif /*__STM32H7xx_HAL_DAC_EX_H */
00247
00248 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dcmi.c Source File

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stm32h7xx_hal_dcmi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dcmi.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   DCMI HAL module driver
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Digital Camera Interface (DCMI) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Error functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019   [..]
00020       The sequence below describes how to use this driver to capture image
00021       from a camera module connected to the DCMI Interface.
00022       This sequence does not take into account the configuration of the
00023       camera module, which should be made before to configure and enable
00024       the DCMI to capture images.
00025
00026     (#) Program the required configuration through following parameters:
00027         horizontal and vertical polarity, pixel clock polarity, Capture Rate,
00028         Synchronization Mode, code of the frame delimiter and data width
00029         using HAL_DCMI_Init() function.
00030
00031     (#) Configure the selected DMA stream to transfer Data from DCMI DR
00032         register to the destination memory buffer.
00033
00034     (#) Program the required configuration through following parameters:
00035         DCMI mode, destination memory Buffer address and the data length
00036         and enable capture using HAL_DCMI_Start_DMA() function.
00037
00038     (#) Optionally, configure and Enable the CROP feature to select a rectangular
00039         window from the received image using HAL_DCMI_ConfigCrop()
00040         and HAL_DCMI_EnableCrop() functions
00041
00042     (#) The capture can be stopped using HAL_DCMI_Stop() function.
00043
00044     (#) To control DCMI state you can use the function HAL_DCMI_GetState().
00045
00046      *** DCMI HAL driver macros list ***
00047      =============================================
00048      [..]
00049        Below the list of most used macros in DCMI HAL driver.
00050
00051       (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.
00052       (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.
00053       (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.
00054       (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.
00055       (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
00056       (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
00057       (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.
00058
00059      [..]
00060        (@) You can refer to the DCMI HAL driver header file for more useful macros
00061
00062   @endverbatim
00063   ******************************************************************************
00064   * @attention
00065   *
00066   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00067   *
00068   * Redistribution and use in source and binary forms, with or without modification,
00069   * are permitted provided that the following conditions are met:
00070   *   1. Redistributions of source code must retain the above copyright notice,
00071   *      this list of conditions and the following disclaimer.
00072   *   2. Redistributions in binary form must reproduce the above copyright notice,
00073   *      this list of conditions and the following disclaimer in the documentation
00074   *      and/or other materials provided with the distribution.
00075   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00076   *      may be used to endorse or promote products derived from this software
00077   *      without specific prior written permission.
00078   *
00079   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00080   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00081   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00082   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00083   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00084   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00085   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00086   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00087   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00088   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00089   *
00090   ******************************************************************************
00091   */
00092
00093 /* Includes ------------------------------------------------------------------*/
00094 #include "stm32h7xx_hal.h"
00095
00096 /** @addtogroup STM32H7xx_HAL_Driver
00097   * @{
00098   */
00099 /** @defgroup DCMI DCMI
00100   * @brief DCMI HAL module driver
00101   * @{
00102   */
00103
00104 #ifdef HAL_DCMI_MODULE_ENABLED
00105
00106 /* Private typedef -----------------------------------------------------------*/
00107 /* Private define ------------------------------------------------------------*/
00108 #define HAL_TIMEOUT_DCMI_STOP    ((uint32_t)1000) /* Set timeout to 1s  */
00109
00110 #define DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE) /*!< Required left shift to set crop window vertical line count       */
00111 #define DCMI_POSITION_CWSTRT_VST   (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST)   /*!< Required left shift to set crop window vertical start line count */
00112
00113 #define DCMI_POSITION_ESCR_LSC     (uint32_t)POSITION_VAL(DCMI_ESCR_LSC)     /*!< Required left shift to set line start delimiter */
00114 #define DCMI_POSITION_ESCR_LEC     (uint32_t)POSITION_VAL(DCMI_ESCR_LEC)     /*!< Required left shift to set line end delimiter   */
00115 #define DCMI_POSITION_ESCR_FEC     (uint32_t)POSITION_VAL(DCMI_ESCR_FEC)     /*!< Required left shift to set frame end delimiter  */
00116
00117 /* Private macro -------------------------------------------------------------*/
00118 /* Private variables ---------------------------------------------------------*/
00119 /* Private function prototypes -----------------------------------------------*/
00120 static void       DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma);
00121 static void       DCMI_DMAError(DMA_HandleTypeDef *hdma);
00122
00123 /* Exported functions --------------------------------------------------------*/
00124
00125 /** @defgroup DCMI_Exported_Functions DCMI Exported Functions
00126   * @{
00127   */
00128
00129 /** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
00130  *  @brief   Initialization and Configuration functions
00131  *
00132 @verbatim
00133  ===============================================================================
00134                 ##### Initialization and Configuration functions #####
00135  ===============================================================================
00136     [..]  This section provides functions allowing to:
00137       (+) Initialize and configure the DCMI
00138       (+) De-initialize the DCMI
00139
00140 @endverbatim
00141   * @{
00142   */
00143
00144 /**
00145   * @brief  Initializes the DCMI according to the specified
00146   *         parameters in the DCMI_InitTypeDef and create the associated handle.
00147   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00148   *                the configuration information for DCMI.
00149   * @retval HAL status
00150   */
00151 HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
00152 {
00153   /* Check the DCMI peripheral state */
00154   if(hdcmi == NULL)
00155   {
00156      return HAL_ERROR;
00157   }
00158
00159   /* Check function parameters */
00160   assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
00161   assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
00162   assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));
00163   assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));
00164   assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));
00165   assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));
00166   assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
00167   assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
00168
00169   assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode));
00170   assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart));
00171   assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode));
00172   assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart));
00173
00174   if(hdcmi->State == HAL_DCMI_STATE_RESET)
00175   {
00176     /* Init the low level hardware */
00177     HAL_DCMI_MspInit(hdcmi);
00178   }
00179
00180   /* Change the DCMI state */
00181   hdcmi->State = HAL_DCMI_STATE_BUSY;
00182                           /* Configures the HS, VS, DE and PC polarity */
00183   hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL  | DCMI_CR_VSPOL  | DCMI_CR_EDM_0 |\
00184                            DCMI_CR_EDM_1  | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG  |\
00185                            DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\
00186                            DCMI_CR_LSM | DCMI_CR_OELS);
00187
00188   hdcmi->Instance->CR |=  (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\
00189                                      hdcmi->Init.VSPolarity  | hdcmi->Init.HSPolarity  |\
00190                                      hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\
00191                                      hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode |\
00192                                      hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\
00193                                      hdcmi->Init.LineSelectStart);
00194
00195   if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
00196   {
00197     hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode)    |\
00198                              ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_POSITION_ESCR_LSC)|\
00199                              ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_POSITION_ESCR_LEC) |\
00200                              ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_POSITION_ESCR_FEC));
00201
00202   }
00203
00204   /* Enable the Line, Vsync, Error and Overrun interrupts */
00205   __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
00206
00207   /* Update error code */
00208   hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
00209
00210   /* Initialize the DCMI state*/
00211   hdcmi->State  = HAL_DCMI_STATE_READY;
00212
00213   return HAL_OK;
00214 }
00215
00216 /**
00217   * @brief  Deinitializes the DCMI peripheral registers to their default reset
00218   *         values.
00219   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00220   *                the configuration information for DCMI.
00221   * @retval HAL status
00222   */
00223
00224 HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
00225 {
00226   /* DeInit the low level hardware */
00227   HAL_DCMI_MspDeInit(hdcmi);
00228
00229   /* Update error code */
00230   hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
00231
00232   /* Initialize the DCMI state*/
00233   hdcmi->State = HAL_DCMI_STATE_RESET;
00234
00235   /* Release Lock */
00236   __HAL_UNLOCK(hdcmi);
00237
00238   return HAL_OK;
00239 }
00240
00241 /**
00242   * @brief  Initializes the DCMI MSP.
00243   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00244   *                the configuration information for DCMI.
00245   * @retval None
00246   */
00247 __weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
00248 {
00249   /* Prevent unused argument(s) compilation warning */
00250   UNUSED(hdcmi);
00251
00252   /* NOTE : This function Should not be modified, when the callback is needed,
00253             the HAL_DCMI_MspInit could be implemented in the user file
00254    */
00255 }
00256
00257 /**
00258   * @brief  DeInitializes the DCMI MSP.
00259   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00260   *                the configuration information for DCMI.
00261   * @retval None
00262   */
00263 __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
00264 {
00265   /* Prevent unused argument(s) compilation warning */
00266   UNUSED(hdcmi);
00267
00268   /* NOTE : This function Should not be modified, when the callback is needed,
00269             the HAL_DCMI_MspDeInit could be implemented in the user file
00270    */
00271 }
00272
00273 /**
00274   * @}
00275   */
00276 /** @defgroup DCMI_Exported_Functions_Group2 IO operation functions
00277  *  @brief   IO operation functions
00278  *
00279 @verbatim
00280  ===============================================================================
00281                       #####  IO operation functions  #####
00282  ===============================================================================
00283     [..]  This section provides functions allowing to:
00284       (+) Configure destination address and data length and
00285           Enables DCMI DMA request and enables DCMI capture
00286       (+) Stop the DCMI capture.
00287       (+) Handles DCMI interrupt request.
00288
00289 @endverbatim
00290   * @{
00291   */
00292
00293 /**
00294   * @brief  Enables DCMI DMA request and enables DCMI capture
00295   * @param  hdcmi:     pointer to a DCMI_HandleTypeDef structure that contains
00296   *                    the configuration information for DCMI.
00297   * @param  DCMI_Mode: DCMI capture mode snapshot or continuous grab.
00298   * @param  pData:     The destination memory Buffer address (LCD Frame buffer).
00299   * @param  Length:    The length of capture to be transferred.
00300   * @retval HAL status
00301   */
00302 HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
00303 {
00304   /* Initialize the second memory address */
00305   uint32_t SecondMemAddress = 0;
00306
00307   /* Check function parameters */
00308   assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
00309
00310   /* Process Locked */
00311   __HAL_LOCK(hdcmi);
00312
00313   /* Lock the DCMI peripheral state */
00314   hdcmi->State = HAL_DCMI_STATE_BUSY;
00315
00316   /* Enable DCMI by setting DCMIEN bit */
00317   __HAL_DCMI_ENABLE(hdcmi);
00318
00319   /* Configure the DCMI Mode */
00320   hdcmi->Instance->CR &= ~(DCMI_CR_CM);
00321   hdcmi->Instance->CR |=  (uint32_t)(DCMI_Mode);
00322
00323   /* Set the DMA memory0 conversion complete callback */
00324   hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt;
00325
00326   /* Set the DMA error callback */
00327   hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;
00328
00329   /* Set the dma abort callback */
00330   hdcmi->DMA_Handle->XferAbortCallback = NULL;
00331
00332   /* Reset transfer counters value */
00333   hdcmi->XferCount = 0;
00334   hdcmi->XferTransferNumber = 0;
00335
00336   if(Length <= 0xFFFF)
00337   {
00338     /* Enable the DMA Stream */
00339     HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length);
00340   }
00341   else /* DCMI_DOUBLE_BUFFER Mode */
00342   {
00343     /* Set the DMA memory1 conversion complete callback */
00344     hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAXferCplt;
00345
00346     /* Initialize transfer parameters */
00347     hdcmi->XferCount = 1;
00348     hdcmi->XferSize = Length;
00349     hdcmi->pBuffPtr = pData;
00350
00351     /* Get the number of buffer */
00352     while(hdcmi->XferSize > 0xFFFF)
00353     {
00354       hdcmi->XferSize = (hdcmi->XferSize/2);
00355       hdcmi->XferCount = hdcmi->XferCount*2;
00356     }
00357
00358     /* Update DCMI counter  and transfer number*/
00359     hdcmi->XferCount = (hdcmi->XferCount - 2);
00360     hdcmi->XferTransferNumber = hdcmi->XferCount;
00361
00362     /* Update second memory address */
00363     SecondMemAddress = (uint32_t)(pData + (4*hdcmi->XferSize));
00364
00365     /* Start DMA multi buffer transfer */
00366     HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize);
00367   }
00368
00369   /* Enable Capture */
00370   hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
00371
00372   /* Release Lock */
00373   __HAL_UNLOCK(hdcmi);
00374
00375   /* Return function status */
00376   return HAL_OK;
00377 }
00378
00379 /**
00380   * @brief  Disable DCMI DMA request and Disable DCMI capture
00381   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00382   *                the configuration information for DCMI.
00383   * @retval HAL status
00384   */
00385 HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
00386 {
00387   register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000);
00388   HAL_StatusTypeDef status = HAL_OK;
00389
00390   /* Process locked */
00391   __HAL_LOCK(hdcmi);
00392
00393   /* Lock the DCMI peripheral state */
00394   hdcmi->State = HAL_DCMI_STATE_BUSY;
00395
00396   /* Disable Capture */
00397   hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
00398
00399   /* Check if the DCMI capture effectively disabled */
00400   do
00401   {
00402     if (count-- == 0)
00403     {
00404       /* Update error code */
00405       hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
00406
00407       status = HAL_TIMEOUT;
00408       break;
00409     }
00410   }
00411   while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);
00412
00413   /* Disable the DCMI */
00414   __HAL_DCMI_DISABLE(hdcmi);
00415
00416   /* Disable the DMA */
00417   HAL_DMA_Abort(hdcmi->DMA_Handle);
00418
00419   /* Update error code */
00420   hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE;
00421
00422   /* Change DCMI state */
00423   hdcmi->State = HAL_DCMI_STATE_READY;
00424
00425   /* Process Unlocked */
00426   __HAL_UNLOCK(hdcmi);
00427
00428   /* Return function status */
00429   return status;
00430 }
00431
00432 /**
00433   * @brief  Suspend DCMI capture
00434   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00435   *                the configuration information for DCMI.
00436   * @retval HAL status
00437   */
00438 HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
00439 {
00440   register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000);
00441   HAL_StatusTypeDef status = HAL_OK;
00442
00443   /* Process locked */
00444   __HAL_LOCK(hdcmi);
00445
00446   if(hdcmi->State == HAL_DCMI_STATE_BUSY)
00447   {
00448     /* Change DCMI state */
00449     hdcmi->State = HAL_DCMI_STATE_SUSPENDED;
00450
00451     /* Disable Capture */
00452     hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
00453
00454     /* Check if the DCMI capture effectively disabled */
00455     do
00456     {
00457       if (count-- == 0)
00458       {
00459         /* Update error code */
00460         hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
00461
00462         /* Change DCMI state */
00463         hdcmi->State = HAL_DCMI_STATE_READY;
00464
00465         status = HAL_TIMEOUT;
00466         break;
00467       }
00468     }
00469     while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);
00470   }
00471   /* Process Unlocked */
00472   __HAL_UNLOCK(hdcmi);
00473
00474   /* Return function status */
00475   return status;
00476 }
00477
00478 /**
00479   * @brief  Resume DCMI capture
00480   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00481   *                the configuration information for DCMI.
00482   * @retval HAL status
00483   */
00484 HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi)
00485 {
00486   /* Process locked */
00487   __HAL_LOCK(hdcmi);
00488
00489   if(hdcmi->State == HAL_DCMI_STATE_SUSPENDED)
00490   {
00491     /* Change DCMI state */
00492     hdcmi->State = HAL_DCMI_STATE_BUSY;
00493
00494     /* Disable Capture */
00495     hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
00496   }
00497   /* Process Unlocked */
00498   __HAL_UNLOCK(hdcmi);
00499
00500   /* Return function status */
00501   return HAL_OK;
00502 }
00503
00504 /**
00505   * @brief  Handles DCMI interrupt request.
00506   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00507   *                the configuration information for the DCMI.
00508   * @retval None
00509   */
00510 void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
00511 {
00512   uint32_t isr_value = READ_REG(hdcmi->Instance->MISR);
00513
00514   /* Synchronization error interrupt management *******************************/
00515   if((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI)
00516   {
00517     /* Clear the Synchronization error flag */
00518     __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
00519
00520     /* Update error code */
00521     hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;
00522
00523     /* Change DCMI state */
00524     hdcmi->State = HAL_DCMI_STATE_ERROR;
00525
00526     /* Set the synchronization error callback */
00527     hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
00528
00529     /* Abort the DMA Transfer */
00530     HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
00531   }
00532   /* Overflow interrupt management ********************************************/
00533   if((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)
00534   {
00535     /* Clear the Overflow flag */
00536     __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI);
00537
00538     /* Update error code */
00539     hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR;
00540
00541     /* Change DCMI state */
00542     hdcmi->State = HAL_DCMI_STATE_ERROR;
00543
00544     /* Set the overflow callback */
00545     hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
00546
00547     /* Abort the DMA Transfer */
00548     HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
00549   }
00550   /* Line Interrupt management ************************************************/
00551   if((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI)
00552   {
00553     /* Clear the Line interrupt flag */
00554     __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
00555
00556     /* Line interrupt Callback */
00557     HAL_DCMI_LineEventCallback(hdcmi);
00558   }
00559   /* VSYNC interrupt management ***********************************************/
00560   if((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)
00561   {
00562     /* Clear the VSYNC flag */
00563     __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
00564
00565     /* VSYNC Callback */
00566     HAL_DCMI_VsyncEventCallback(hdcmi);
00567   }
00568   /* FRAME interrupt management ***********************************************/
00569   if((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI)
00570   {
00571     /* When snapshot mode, disable Vsync, Error and Overrun interrupts */
00572     if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
00573     {
00574       /* Disable the Line, Vsync, Error and Overrun interrupts */
00575       __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
00576     }
00577
00578     /* Disable the Frame interrupt */
00579     __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);
00580
00581     /* Clear the End of Frame flag */
00582     __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);
00583
00584     /* Frame Callback */
00585     HAL_DCMI_FrameEventCallback(hdcmi);
00586   }
00587 }
00588
00589 /**
00590   * @brief  Error DCMI callback.
00591   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00592   *                the configuration information for DCMI.
00593   * @retval None
00594   */
00595 __weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
00596 {
00597   /* Prevent unused argument(s) compilation warning */
00598   UNUSED(hdcmi);
00599
00600   /* NOTE : This function Should not be modified, when the callback is needed,
00601             the HAL_DCMI_ErrorCallback could be implemented in the user file
00602    */
00603 }
00604
00605 /**
00606   * @brief  Line Event callback.
00607   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00608   *                the configuration information for DCMI.
00609   * @retval None
00610   */
00611 __weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)
00612 {
00613   /* NOTE : This function Should not be modified, when the callback is needed,
00614             the HAL_DCMI_LineEventCallback could be implemented in the user file
00615    */
00616 }
00617
00618 /**
00619   * @brief  VSYNC Event callback.
00620   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00621   *                the configuration information for DCMI.
00622   * @retval None
00623   */
00624 __weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
00625 {
00626   /* Prevent unused argument(s) compilation warning */
00627   UNUSED(hdcmi);
00628
00629   /* NOTE : This function Should not be modified, when the callback is needed,
00630             the HAL_DCMI_VsyncEventCallback could be implemented in the user file
00631    */
00632 }
00633
00634 /**
00635   * @brief  Frame Event callback.
00636   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00637   *                the configuration information for DCMI.
00638   * @retval None
00639   */
00640 __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
00641 {
00642   /* Prevent unused argument(s) compilation warning */
00643   UNUSED(hdcmi);
00644
00645   /* NOTE : This function Should not be modified, when the callback is needed,
00646             the HAL_DCMI_FrameEventCallback could be implemented in the user file
00647    */
00648 }
00649
00650 /**
00651   * @}
00652   */
00653
00654 /** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions
00655  *  @brief    Peripheral Control functions
00656  *
00657 @verbatim
00658  ===============================================================================
00659                     ##### Peripheral Control functions #####
00660  ===============================================================================
00661 [..]  This section provides functions allowing to:
00662       (+) Configure the CROP feature.
00663       (+) Enable/Disable the CROP feature.
00664
00665 @endverbatim
00666   * @{
00667   */
00668
00669 /**
00670   * @brief  Configure the DCMI CROP coordinate.
00671   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00672   *                the configuration information for DCMI.
00673   * @param  YSize: DCMI Line number
00674   * @param  XSize: DCMI Pixel per line
00675   * @param  X0:    DCMI window X offset
00676   * @param  Y0:    DCMI window Y offset
00677   * @retval HAL status
00678   */
00679 HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
00680 {
00681   /* Process Locked */
00682   __HAL_LOCK(hdcmi);
00683
00684   /* Lock the DCMI peripheral state */
00685   hdcmi->State = HAL_DCMI_STATE_BUSY;
00686
00687   /* Check the parameters */
00688   assert_param(IS_DCMI_WINDOW_COORDINATE(X0));
00689   assert_param(IS_DCMI_WINDOW_HEIGHT(Y0));
00690   assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));
00691   assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));
00692
00693   /* Configure CROP */
00694   hdcmi->Instance->CWSIZER = (XSize | (YSize << DCMI_POSITION_CWSIZE_VLINE));
00695   hdcmi->Instance->CWSTRTR = (X0 | (Y0 << DCMI_POSITION_CWSTRT_VST));
00696
00697   /* Initialize the DCMI state*/
00698   hdcmi->State  = HAL_DCMI_STATE_READY;
00699
00700   /* Process Unlocked */
00701   __HAL_UNLOCK(hdcmi);
00702
00703   return HAL_OK;
00704 }
00705
00706 /**
00707   * @brief  Disable the Crop feature.
00708   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00709   *                the configuration information for DCMI.
00710   * @retval HAL status
00711   */
00712 HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi)
00713 {
00714   /* Process Locked */
00715   __HAL_LOCK(hdcmi);
00716
00717   /* Lock the DCMI peripheral state */
00718   hdcmi->State = HAL_DCMI_STATE_BUSY;
00719
00720   /* Disable DCMI Crop feature */
00721   hdcmi->Instance->CR &= ~(uint32_t)DCMI_CR_CROP;
00722
00723   /* Change the DCMI state*/
00724   hdcmi->State = HAL_DCMI_STATE_READY;
00725
00726   /* Process Unlocked */
00727   __HAL_UNLOCK(hdcmi);
00728
00729   return HAL_OK;
00730 }
00731
00732 /**
00733   * @brief  Enable the Crop feature.
00734   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00735   *                the configuration information for DCMI.
00736   * @retval HAL status
00737   */
00738 HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi)
00739 {
00740   /* Process Locked */
00741   __HAL_LOCK(hdcmi);
00742
00743   /* Lock the DCMI peripheral state */
00744   hdcmi->State = HAL_DCMI_STATE_BUSY;
00745
00746   /* Enable DCMI Crop feature */
00747   hdcmi->Instance->CR |= (uint32_t)DCMI_CR_CROP;
00748
00749   /* Change the DCMI state*/
00750   hdcmi->State = HAL_DCMI_STATE_READY;
00751
00752   /* Process Unlocked */
00753   __HAL_UNLOCK(hdcmi);
00754
00755   return HAL_OK;
00756 }
00757
00758 /**
00759   * @}
00760   */
00761
00762 /** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions
00763  *  @brief    Peripheral State functions
00764  *
00765 @verbatim
00766  ===============================================================================
00767                ##### Peripheral State and Errors functions #####
00768  ===============================================================================
00769     [..]
00770     This subsection provides functions allowing to
00771       (+) Check the DCMI state.
00772       (+) Get the specific DCMI error flag.
00773
00774 @endverbatim
00775   * @{
00776   */
00777
00778 /**
00779   * @brief  Return the DCMI state
00780   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00781   *                the configuration information for DCMI.
00782   * @retval HAL state
00783   */
00784 HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
00785 {
00786   return hdcmi->State;
00787 }
00788
00789 /**
00790 * @brief  Return the DCMI error code
00791 * @param  hdcmi : pointer to a DCMI_HandleTypeDef structure that contains
00792   *               the configuration information for DCMI.
00793 * @retval DCMI Error Code
00794 */
00795 uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
00796 {
00797   return hdcmi->ErrorCode;
00798 }
00799
00800 /**
00801   * @}
00802   */
00803 /* Private functions ---------------------------------------------------------*/
00804 /** @defgroup DCMI_Private_Functions DCMI Private Functions
00805   * @{
00806   */
00807   /**
00808   * @brief  DMA conversion complete callback.
00809   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00810   *                the configuration information for the specified DMA module.
00811   * @retval None
00812   */
00813 static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
00814 {
00815   uint32_t tmp = 0;
00816
00817   DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00818
00819   if(hdcmi->XferCount != 0)
00820   {
00821     /* Update memory 0 address location */
00822     tmp = ((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR) & DMA_SxCR_CT);
00823     if(((hdcmi->XferCount % 2) == 0) && (tmp != 0))
00824     {
00825       tmp = ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M0AR;
00826       HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY0);
00827       hdcmi->XferCount--;
00828     }
00829     /* Update memory 1 address location */
00830     else if((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) == 0)
00831     {
00832       tmp = ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M1AR;
00833       HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY1);
00834       hdcmi->XferCount--;
00835     }
00836   }
00837   /* Update memory 0 address location */
00838   else if((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) != 0)
00839   {
00840     ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M0AR = hdcmi->pBuffPtr;
00841   }
00842   /* Update memory 1 address location */
00843   else if((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) == 0)
00844   {
00845     tmp = hdcmi->pBuffPtr;
00846     ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M1AR = (tmp + (4*hdcmi->XferSize));
00847     hdcmi->XferCount = hdcmi->XferTransferNumber;
00848   }
00849
00850   /* Check if the frame is transferred */
00851   if(hdcmi->XferCount == hdcmi->XferTransferNumber)
00852   {
00853     /* Enable the Frame interrupt */
00854     __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
00855
00856     /* When snapshot mode, set dcmi state to ready */
00857     if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
00858     {
00859       hdcmi->State= HAL_DCMI_STATE_READY;
00860     }
00861   }
00862 }
00863
00864 /**
00865   * @brief  DMA error callback
00866   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00867   *                the configuration information for the specified DMA module.
00868   * @retval None
00869   */
00870 static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
00871 {
00872   DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00873
00874   if(hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE)
00875   {
00876     /* Initialize the DCMI state*/
00877     hdcmi->State = HAL_DCMI_STATE_READY;
00878
00879     /* Set DCMI Error Code */
00880     hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA;
00881   }
00882
00883   /* DCMI error Callback */
00884   HAL_DCMI_ErrorCallback(hdcmi);
00885 }
00886
00887 /**
00888   * @}
00889   */
00890
00891 /**
00892   * @}
00893   */
00894 #endif /* HAL_DCMI_MODULE_ENABLED */
00895 /**
00896   * @}
00897   */
00898
00899 /**
00900   * @}
00901   */
00902
00903 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dcmi.h Source File

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stm32h7xx_hal_dcmi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dcmi.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of DCMI HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_DCMI_H
00040 #define __STM32H7xx_HAL_DCMI_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049
00050 /** @addtogroup STM32H7xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup DCMI DCMI
00055   * @brief DCMI HAL module driver
00056   * @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060 /** @defgroup DCMI_Exported_Types DCMI Exported Types
00061   * @{
00062   */
00063 /**
00064   * @brief  HAL DCMI State structures definition
00065   */
00066 typedef enum
00067 {
00068   HAL_DCMI_STATE_RESET             = 0x00U,  /*!< DCMI not yet initialized or disabled  */
00069   HAL_DCMI_STATE_READY             = 0x01U,  /*!< DCMI initialized and ready for use    */
00070   HAL_DCMI_STATE_BUSY              = 0x02U,  /*!< DCMI internal processing is ongoing   */
00071   HAL_DCMI_STATE_TIMEOUT           = 0x03U,  /*!< DCMI timeout state                    */
00072   HAL_DCMI_STATE_ERROR             = 0x04U,  /*!< DCMI error state                      */
00073   HAL_DCMI_STATE_SUSPENDED         = 0x05U   /*!< DCMI suspend state                    */
00074 }HAL_DCMI_StateTypeDef;
00075
00076 /**
00077   * @brief   DCMI Embedded Synchronisation CODE Init structure definition
00078   */
00079 typedef struct
00080 {
00081   uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
00082   uint8_t LineStartCode;  /*!< Specifies the code of the line start delimiter.  */
00083   uint8_t LineEndCode;    /*!< Specifies the code of the line end delimiter.    */
00084   uint8_t FrameEndCode;   /*!< Specifies the code of the frame end delimiter.   */
00085 }DCMI_CodesInitTypeDef;
00086
00087 /**
00088   * @brief   DCMI Init structure definition
00089   */
00090 typedef struct
00091 {
00092   uint32_t  SynchroMode;                /*!< Specifies the Synchronization Mode: Hardware or Embedded.
00093                                              This parameter can be a value of @ref DCMI_Synchronization_Mode */
00094
00095   uint32_t  PCKPolarity;                /*!< Specifies the Pixel clock polarity: Falling or Rising.
00096                                              This parameter can be a value of @ref DCMI_PIXCK_Polarity       */
00097
00098   uint32_t  VSPolarity;                 /*!< Specifies the Vertical synchronization polarity: High or Low.
00099                                              This parameter can be a value of @ref DCMI_VSYNC_Polarity       */
00100
00101   uint32_t  HSPolarity;                 /*!< Specifies the Horizontal synchronization polarity: High or Low.
00102                                              This parameter can be a value of @ref DCMI_HSYNC_Polarity       */
00103
00104   uint32_t  CaptureRate;                /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
00105                                              This parameter can be a value of @ref DCMI_Capture_Rate         */
00106
00107   uint32_t  ExtendedDataMode;           /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
00108                                              This parameter can be a value of @ref DCMI_Extended_Data_Mode   */
00109
00110   DCMI_CodesInitTypeDef SyncroCode;     /*!< Specifies the code of the line/frame start delimiter and the
00111                                              line/frame end delimiter */
00112
00113   uint32_t JPEGMode;                    /*!< Enable or Disable the JPEG mode.
00114                                              This parameter can be a value of @ref DCMI_MODE_JPEG            */
00115
00116   uint32_t ByteSelectMode;              /*!< Specifies the data to be captured by the interface
00117                                             This parameter can be a value of @ref DCMI_Byte_Select_Mode      */
00118
00119   uint32_t ByteSelectStart;             /*!< Specifies if the data to be captured by the interface is even or odd
00120                                             This parameter can be a value of @ref DCMI_Byte_Select_Start     */
00121
00122   uint32_t LineSelectMode;              /*!< Specifies the line of data to be captured by the interface
00123                                             This parameter can be a value of @ref DCMI_Line_Select_Mode      */
00124
00125   uint32_t LineSelectStart;             /*!< Specifies if the line of data to be captured by the interface is even or odd
00126                                             This parameter can be a value of @ref DCMI_Line_Select_Start     */
00127 }DCMI_InitTypeDef;
00128
00129 /**
00130   * @brief  DCMI handle Structure definition
00131   */
00132 typedef struct
00133 {
00134   DCMI_TypeDef                  *Instance;           /*!< DCMI Register base address   */
00135
00136   DCMI_InitTypeDef              Init;                /*!< DCMI parameters              */
00137
00138   HAL_LockTypeDef               Lock;                /*!< DCMI locking object          */
00139
00140   __IO HAL_DCMI_StateTypeDef    State;               /*!< DCMI state                   */
00141
00142   __IO uint32_t                 XferCount;           /*!< DMA transfer counter         */
00143
00144   __IO uint32_t                 XferSize;            /*!< DMA transfer size            */
00145
00146   uint32_t                      XferTransferNumber;  /*!< DMA transfer number          */
00147
00148   uint32_t                      pBuffPtr;            /*!< Pointer to DMA output buffer */
00149
00150   DMA_HandleTypeDef             *DMA_Handle;         /*!< Pointer to the DMA handler   */
00151
00152   __IO uint32_t                 ErrorCode;           /*!< DCMI Error code              */
00153
00154 }DCMI_HandleTypeDef;
00155 /**
00156   * @}
00157   */
00158 /* Exported constants --------------------------------------------------------*/
00159
00160 /** @defgroup DCMI_Exported_Constants DCMI Exported Constants
00161   * @{
00162   */
00163
00164 /** @defgroup DCMI_Error_Code DCMI Error Code
00165   * @{
00166   */
00167 #define HAL_DCMI_ERROR_NONE      (0x00000000U)    /*!< No error              */
00168 #define HAL_DCMI_ERROR_OVR       (0x00000001U)    /*!< Overrun error         */
00169 #define HAL_DCMI_ERROR_SYNC      (0x00000002U)    /*!< Synchronization error */
00170 #define HAL_DCMI_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
00171 #define HAL_DCMI_ERROR_DMA       (0x00000040U)    /*!< DMA error             */
00172 /**
00173   * @}
00174   */
00175
00176 /** @defgroup DCMI_Capture_Mode DCMI Capture Mode
00177   * @{
00178   */
00179 #define DCMI_MODE_CONTINUOUS           (0x00000000U)  /*!< The received data are transferred continuously
00180                                                                     into the destination memory through the DMA             */
00181 #define DCMI_MODE_SNAPSHOT             ((uint32_t)DCMI_CR_CM)  /*!< Once activated, the interface waits for the start of
00182                                                                     frame and then transfers a single frame through the DMA */
00183 /**
00184   * @}
00185   */
00186
00187 /** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
00188   * @{
00189   */
00190 #define DCMI_SYNCHRO_HARDWARE        (0x00000000U)   /*!< Hardware synchronization data capture (frame/line start/stop)
00191                                                                    is synchronized with the HSYNC/VSYNC signals                  */
00192 #define DCMI_SYNCHRO_EMBEDDED        ((uint32_t)DCMI_CR_ESS)  /*!< Embedded synchronization data capture is synchronized with
00193                                                                    synchronization codes embedded in the data flow               */
00194
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
00200   * @{
00201   */
00202 #define DCMI_PCKPOLARITY_FALLING    (0x00000000U)      /*!< Pixel clock active on Falling edge */
00203 #define DCMI_PCKPOLARITY_RISING     ((uint32_t)DCMI_CR_PCKPOL)  /*!< Pixel clock active on Rising edge  */
00204
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
00210   * @{
00211   */
00212 #define DCMI_VSPOLARITY_LOW     (0x00000000U)     /*!< Vertical synchronization active Low  */
00213 #define DCMI_VSPOLARITY_HIGH    ((uint32_t)DCMI_CR_VSPOL)  /*!< Vertical synchronization active High */
00214
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
00220   * @{
00221   */
00222 #define DCMI_HSPOLARITY_LOW     (0x00000000U)     /*!< Horizontal synchronization active Low  */
00223 #define DCMI_HSPOLARITY_HIGH    ((uint32_t)DCMI_CR_HSPOL)  /*!< Horizontal synchronization active High */
00224
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
00230   * @{
00231   */
00232 #define DCMI_JPEG_DISABLE   (0x00000000U)    /*!< Mode JPEG Disabled  */
00233 #define DCMI_JPEG_ENABLE    ((uint32_t)DCMI_CR_JPEG)  /*!< Mode JPEG Enabled   */
00234
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup DCMI_Capture_Rate DCMI Capture Rate
00240   * @{
00241   */
00242 #define DCMI_CR_ALL_FRAME            (0x00000000U)      /*!< All frames are captured        */
00243 #define DCMI_CR_ALTERNATE_2_FRAME    ((uint32_t)DCMI_CR_FCRC_0)  /*!< Every alternate frame captured */
00244 #define DCMI_CR_ALTERNATE_4_FRAME    ((uint32_t)DCMI_CR_FCRC_1)  /*!< One frame in 4 frames captured */
00245
00246 /**
00247   * @}
00248   */
00249
00250 /** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
00251   * @{
00252   */
00253 #define DCMI_EXTEND_DATA_8B     (0x00000000U)                       /*!< Interface captures 8-bit data on every pixel clock  */
00254 #define DCMI_EXTEND_DATA_10B    ((uint32_t)DCMI_CR_EDM_0)                    /*!< Interface captures 10-bit data on every pixel clock */
00255 #define DCMI_EXTEND_DATA_12B    ((uint32_t)DCMI_CR_EDM_1)                    /*!< Interface captures 12-bit data on every pixel clock */
00256 #define DCMI_EXTEND_DATA_14B    ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))  /*!< Interface captures 14-bit data on every pixel clock */
00257
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
00263   * @{
00264   */
00265 #define DCMI_WINDOW_COORDINATE    (0x3FFFU)  /*!< Window coordinate */
00266
00267 /**
00268   * @}
00269   */
00270
00271 /** @defgroup DCMI_Window_Height DCMI Window Height
00272   * @{
00273   */
00274 #define DCMI_WINDOW_HEIGHT    (0x1FFFU)  /*!< Window Height */
00275
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup DCMI_interrupt_sources  DCMI interrupt sources
00281   * @{
00282   */
00283 #define DCMI_IT_FRAME    ((uint32_t)DCMI_IER_FRAME_IE)    /*!< Capture complete interrupt      */
00284 #define DCMI_IT_OVR      ((uint32_t)DCMI_IER_OVR_IE)      /*!< Overrun interrupt               */
00285 #define DCMI_IT_ERR      ((uint32_t)DCMI_IER_ERR_IE)      /*!< Synchronization error interrupt */
00286 #define DCMI_IT_VSYNC    ((uint32_t)DCMI_IER_VSYNC_IE)    /*!< VSYNC interrupt                 */
00287 #define DCMI_IT_LINE     ((uint32_t)DCMI_IER_LINE_IE)     /*!< Line interrupt                  */
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup DCMI_Flags DCMI Flags
00293   * @{
00294   */
00295
00296 /**
00297   * @brief   DCMI SR register
00298   */
00299 #define DCMI_FLAG_HSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines)   */
00300 #define DCMI_FLAG_VSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */
00301 #define DCMI_FLAG_FNE       ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE)   /*!< FIFO not empty flag                                                 */
00302 /**
00303   * @brief   DCMI RIS register
00304   */
00305 #define DCMI_FLAG_FRAMERI    ((uint32_t)DCMI_RIS_FRAME_RIS)  /*!< Frame capture complete interrupt flag */
00306 #define DCMI_FLAG_OVRRI      ((uint32_t)DCMI_RIS_OVR_RIS)    /*!< Overrun interrupt flag                */
00307 #define DCMI_FLAG_ERRRI      ((uint32_t)DCMI_RIS_ERR_RIS)    /*!< Synchronization error interrupt flag  */
00308 #define DCMI_FLAG_VSYNCRI    ((uint32_t)DCMI_RIS_VSYNC_RIS)  /*!< VSYNC interrupt flag                  */
00309 #define DCMI_FLAG_LINERI     ((uint32_t)DCMI_RIS_LINE_RIS)   /*!< Line interrupt flag                   */
00310 /**
00311   * @brief   DCMI MIS register
00312   */
00313 #define DCMI_FLAG_FRAMEMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS)  /*!< DCMI Frame capture complete masked interrupt status */
00314 #define DCMI_FLAG_OVRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS  )  /*!< DCMI Overrun masked interrupt status                */
00315 #define DCMI_FLAG_ERRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS  )  /*!< DCMI Synchronization error masked interrupt status  */
00316 #define DCMI_FLAG_VSYNCMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS)  /*!< DCMI VSYNC masked interrupt status                  */
00317 #define DCMI_FLAG_LINEMI     ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS )  /*!< DCMI Line masked interrupt status                   */
00318 /**
00319   * @}
00320   */
00321
00322 /** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode
00323   * @{
00324   */
00325 #define DCMI_BSM_ALL                 (0x00000000U) /*!< Interface captures all received data */
00326 #define DCMI_BSM_OTHER               ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */
00327 #define DCMI_BSM_ALTERNATE_4         ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
00328 #define DCMI_BSM_ALTERNATE_2         ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
00329
00330 /**
00331   * @}
00332   */
00333
00334 /** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start
00335   * @{
00336   */
00337 #define DCMI_OEBS_ODD               (0x00000000U) /*!< Interface captures first data from the frame/line start, second one being dropped */
00338 #define DCMI_OEBS_EVEN              ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */
00339
00340 /**
00341   * @}
00342   */
00343
00344 /** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode
00345   * @{
00346   */
00347 #define DCMI_LSM_ALL                 (0x00000000U) /*!< Interface captures all received lines */
00348 #define DCMI_LSM_ALTERNATE_2         ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
00349
00350 /**
00351   * @}
00352   */
00353
00354 /** @defgroup DCMI_Line_Select_Start DCMI Line Select Start
00355   * @{
00356   */
00357 #define DCMI_OELS_ODD               (0x00000000U) /*!< Interface captures first line from the frame start, second one being dropped */
00358 #define DCMI_OELS_EVEN              ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */
00359
00360 /**
00361   * @}
00362   */
00363
00364 /**
00365   * @}
00366   */
00367
00368 /* Exported macro ------------------------------------------------------------*/
00369 /** @defgroup DCMI_Exported_Macros DCMI Exported Macros
00370   * @{
00371   */
00372
00373 /** @brief Reset DCMI handle state
00374   * @param  __HANDLE__: specifies the DCMI handle.
00375   * @retval None
00376   */
00377 #define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
00378
00379 /**
00380   * @brief  Enable the DCMI.
00381   * @param  __HANDLE__: DCMI handle
00382   * @retval None
00383   */
00384 #define __HAL_DCMI_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
00385
00386 /**
00387   * @brief  Disable the DCMI.
00388   * @param  __HANDLE__: DCMI handle
00389   * @retval None
00390   */
00391 #define __HAL_DCMI_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
00392
00393 /* Interrupt & Flag management */
00394 /**
00395   * @brief  Get the DCMI pending flag.
00396   * @param  __HANDLE__: DCMI handle
00397   * @param  __FLAG__: Get the specified flag.
00398   *         This parameter can be one of the following values (no combination allowed)
00399   *            @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
00400   *            @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
00401   *            @arg DCMI_FLAG_FNE: FIFO empty flag
00402   *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
00403   *            @arg DCMI_FLAG_OVRRI: Overrun flag mask
00404   *            @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
00405   *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
00406   *            @arg DCMI_FLAG_LINERI: Line flag mask
00407   *            @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
00408   *            @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
00409   *            @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
00410   *            @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
00411   *            @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
00412   * @retval The state of FLAG.
00413   */
00414 #define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
00415 ((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\
00416  (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
00417
00418 /**
00419   * @brief  Clear the DCMI pending flags.
00420   * @param  __HANDLE__: DCMI handle
00421   * @param  __FLAG__: specifies the flag to clear.
00422   *         This parameter can be any combination of the following values:
00423   *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
00424   *            @arg DCMI_FLAG_OVFRI: Overflow flag mask
00425   *            @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
00426   *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
00427   *            @arg DCMI_FLAG_LINERI: Line flag mask
00428   * @retval None
00429   */
00430 #define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00431
00432 /**
00433   * @brief  Enable the specified DCMI interrupts.
00434   * @param  __HANDLE__:    DCMI handle
00435   * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
00436   *         This parameter can be any combination of the following values:
00437   *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
00438   *            @arg DCMI_IT_OVF: Overflow interrupt mask
00439   *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
00440   *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
00441   *            @arg DCMI_IT_LINE: Line interrupt mask
00442   * @retval None
00443   */
00444 #define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
00445
00446 /**
00447   * @brief  Disable the specified DCMI interrupts.
00448   * @param  __HANDLE__: DCMI handle
00449   * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
00450   *         This parameter can be any combination of the following values:
00451   *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
00452   *            @arg DCMI_IT_OVF: Overflow interrupt mask
00453   *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
00454   *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
00455   *            @arg DCMI_IT_LINE: Line interrupt mask
00456   * @retval None
00457   */
00458 #define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
00459
00460 /**
00461   * @brief  Check whether the specified DCMI interrupt has occurred or not.
00462   * @param  __HANDLE__: DCMI handle
00463   * @param  __INTERRUPT__: specifies the DCMI interrupt source to check.
00464   *         This parameter can be one of the following values:
00465   *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
00466   *            @arg DCMI_IT_OVF: Overflow interrupt mask
00467   *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
00468   *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
00469   *            @arg DCMI_IT_LINE: Line interrupt mask
00470   * @retval The state of INTERRUPT.
00471   */
00472 #define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
00473
00474 /**
00475   * @}
00476   */
00477
00478 /* Exported functions --------------------------------------------------------*/
00479 /** @addtogroup DCMI_Exported_Functions DCMI Exported Functions
00480   * @{
00481   */
00482
00483 /** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
00484  * @{
00485  */
00486 /* Initialization and de-initialization functions *****************************/
00487 HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
00488 HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
00489 void       HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
00490 void       HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
00491 /**
00492   * @}
00493   */
00494
00495 /** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions
00496  * @{
00497  */
00498 /* IO operation functions *****************************************************/
00499 HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
00500 HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
00501 HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi);
00502 HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi);
00503 void       HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
00504 void       HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
00505 void       HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
00506 void       HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
00507 void       HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
00508 /**
00509   * @}
00510   */
00511
00512 /** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions
00513  * @{
00514  */
00515 /* Peripheral Control functions ***********************************************/
00516 HAL_StatusTypeDef     HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
00517 HAL_StatusTypeDef     HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
00518 HAL_StatusTypeDef     HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
00519
00520 /**
00521   * @}
00522   */
00523
00524 /** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions
00525  * @{
00526  */
00527 /* Peripheral State functions *************************************************/
00528 HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
00529 uint32_t              HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
00530 /**
00531   * @}
00532   */
00533
00534 /**
00535   * @}
00536   */
00537
00538 /* Private types -------------------------------------------------------------*/
00539 /* Private variables ---------------------------------------------------------*/
00540 /* Private constants ---------------------------------------------------------*/
00541 /** @defgroup DCMI_Private_Constants DCMI Private Constants
00542   * @{
00543   */
00544 #define DCMI_MIS_INDEX        (0x1000) /*!< DCMI MIS register index */
00545 #define DCMI_SR_INDEX         (0x2000) /*!< DCMI SR register index  */
00546 /**
00547   * @}
00548   */
00549 /* Private macro -------------------------------------------------------------*/
00550 /** @defgroup DCMI_Private_Macros DCMI Private Macros
00551   * @{
00552   */
00553 #define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
00554                                    ((MODE) == DCMI_MODE_SNAPSHOT))
00555
00556 #define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
00557                               ((MODE) == DCMI_SYNCHRO_EMBEDDED))
00558
00559 #define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
00560                                       ((POLARITY) == DCMI_PCKPOLARITY_RISING))
00561
00562 #define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
00563                                      ((POLARITY) == DCMI_VSPOLARITY_HIGH))
00564
00565 #define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
00566                                      ((POLARITY) == DCMI_HSPOLARITY_HIGH))
00567
00568 #define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
00569                                      ((JPEG_MODE) == DCMI_JPEG_ENABLE))
00570
00571 #define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME)         || \
00572                                     ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
00573                                     ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
00574
00575 #define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B)  || \
00576                                     ((DATA) == DCMI_EXTEND_DATA_10B) || \
00577                                     ((DATA) == DCMI_EXTEND_DATA_12B) || \
00578                                     ((DATA) == DCMI_EXTEND_DATA_14B))
00579
00580 #define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
00581
00582 #define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
00583
00584 #define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \
00585                                        ((MODE) == DCMI_BSM_OTHER) || \
00586                                        ((MODE) == DCMI_BSM_ALTERNATE_4) || \
00587                                        ((MODE) == DCMI_BSM_ALTERNATE_2))
00588
00589 #define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \
00590                                             ((POLARITY) == DCMI_OEBS_EVEN))
00591
00592 #define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \
00593                                        ((MODE) == DCMI_LSM_ALTERNATE_2))
00594
00595 #define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \
00596                                             ((POLARITY) == DCMI_OELS_EVEN))
00597
00598 /**
00599   * @}
00600   */
00601
00602 /* Private functions ---------------------------------------------------------*/
00603 /** @addtogroup DCMI_Private_Functions DCMI Private Functions
00604   * @{
00605   */
00606
00607 /**
00608   * @}
00609   */
00610
00611 /**
00612   * @}
00613   */
00614 /**
00615   * @}
00616   */
00617
00618 #ifdef __cplusplus
00619 }
00620 #endif
00621
00622 #endif /* __STM32H7xx_HAL_DCMI_H */
00623
00624 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dfsdm.c Source File

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stm32h7xx_hal_dfsdm.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dfsdm.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Digital Filter for Sigma-Delta Modulators
00009   *          (DFSDM) peripherals:
00010   *           + Initialization and configuration of channels and filters
00011   *           + Regular channels configuration
00012   *           + Injected channels configuration
00013   *           + Regular/Injected Channels DMA Configuration
00014   *           + Interrupts and flags management
00015   *           + Analog watchdog feature
00016   *           + Short-circuit detector feature
00017   *           + Extremes detector feature
00018   *           + Clock absence detector feature
00019   *           + Break generation on analog watchdog or short-circuit event
00020   *
00021   @verbatim
00022   ==============================================================================
00023                      ##### How to use this driver #####
00024   ==============================================================================
00025   [..]
00026     *** Channel initialization ***
00027     ==============================
00028     [..]
00029       (#) User has first to initialize channels (before filters initialization).
00030       (#) As prerequisite, fill in the HAL_DFSDM_ChannelMspInit() :
00031         (++) Enable DFSDMz clock interface with __HAL_RCC_DFSDMz_CLK_ENABLE().
00032         (++) Enable the clocks for the DFSDMz GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
00033         (++) Configure these DFSDMz pins in alternate mode using HAL_GPIO_Init().
00034         (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global
00035             interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00036       (#) Configure the output clock, input, serial interface, analog watchdog,
00037           offset and data right bit shift parameters for this channel using the
00038           HAL_DFSDM_ChannelInit() function.
00039
00040     *** Channel clock absence detector ***
00041     ======================================
00042     [..]
00043       (#) Start clock absence detector using HAL_DFSDM_ChannelCkabStart() or
00044           HAL_DFSDM_ChannelCkabStart_IT().
00045       (#) In polling mode, use HAL_DFSDM_ChannelPollForCkab() to detect the clock
00046           absence.
00047       (#) In interrupt mode, HAL_DFSDM_ChannelCkabCallback() will be called if
00048           clock absence is detected.
00049       (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or
00050           HAL_DFSDM_ChannelCkabStop_IT().
00051       (#) Please note that the same mode (polling or interrupt) has to be used
00052           for all channels because the channels are sharing the same interrupt.
00053       (#) Please note also that in interrupt mode, if clock absence detector is
00054           stopped for one channel, interrupt will be disabled for all channels.
00055
00056     *** Channel short circuit detector ***
00057     ======================================
00058     [..]
00059       (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or
00060           or HAL_DFSDM_ChannelScdStart_IT().
00061       (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short
00062           circuit.
00063       (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if
00064           short circuit is detected.
00065       (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or
00066           or HAL_DFSDM_ChannelScdStop_IT().
00067       (#) Please note that the same mode (polling or interrupt) has to be used
00068           for all channels because the channels are sharing the same interrupt.
00069       (#) Please note also that in interrupt mode, if short circuit detector is
00070           stopped for one channel, interrupt will be disabled for all channels.
00071
00072     *** Channel analog watchdog value ***
00073     =====================================
00074     [..]
00075       (#) Get analog watchdog filter value of a channel using
00076           HAL_DFSDM_ChannelGetAwdValue().
00077
00078     *** Channel offset value ***
00079     =====================================
00080     [..]
00081       (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset().
00082
00083     *** Filter initialization ***
00084     =============================
00085     [..]
00086       (#) After channel initialization, user has to init filters.
00087       (#) As prerequisite, fill in the HAL_DFSDM_FilterMspInit() :
00088         (++) If interrupt mode is used , enable and configure DFSDMz_FLTx global
00089             interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00090             Please note that DFSDMz_FLT0 global interrupt could be already
00091             enabled if interrupt is used for channel.
00092         (++) If DMA mode is used, configure DMA with HAL_DMA_Init() and link it
00093             with DFSDMz filter handle using __HAL_LINKDMA().
00094       (#) Configure the regular conversion, injected conversion and filter
00095           parameters for this filter using the HAL_DFSDM_FilterInit() function.
00096
00097     *** Filter regular channel conversion ***
00098     =========================================
00099     [..]
00100       (#) Select regular channel and enable/disable continuous mode using
00101           HAL_DFSDM_FilterConfigRegChannel().
00102       (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(),
00103           HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or
00104           HAL_DFSDM_FilterRegularMsbStart_DMA().
00105       (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect
00106           the end of regular conversion.
00107       (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called
00108           at the end of regular conversion.
00109       (#) Get value of regular conversion and corresponding channel using
00110           HAL_DFSDM_FilterGetRegularValue().
00111       (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and
00112           HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the
00113           half transfer and at the transfer complete. Please note that
00114           HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA
00115           circular mode.
00116       (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(),
00117           HAL_DFSDM_FilterRegularStop_IT() or HAL_DFSDM_FilterRegularStop_DMA().
00118
00119     *** Filter injected channels conversion ***
00120     ===========================================
00121     [..]
00122       (#) Select injected channels using HAL_DFSDM_FilterConfigInjChannel().
00123       (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(),
00124           HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or
00125           HAL_DFSDM_FilterInjectedMsbStart_DMA().
00126       (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect
00127           the end of injected conversion.
00128       (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called
00129           at the end of injected conversion.
00130       (#) Get value of injected conversion and corresponding channel using
00131           HAL_DFSDM_FilterGetInjectedValue().
00132       (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and
00133           HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the
00134           half transfer and at the transfer complete. Please note that
00135           HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA
00136           circular mode.
00137       (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(),
00138           HAL_DFSDM_FilterInjectedStop_IT() or HAL_DFSDM_FilterInjectedStop_DMA().
00139
00140     *** Filter analog watchdog ***
00141     ==============================
00142     [..]
00143       (#) Start filter analog watchdog using HAL_DFSDM_FilterAwdStart_IT().
00144       (#) HAL_DFSDM_FilterAwdCallback() will be called if analog watchdog occurs.
00145       (#) Stop filter analog watchdog using HAL_DFSDM_FilterAwdStop_IT().
00146
00147     *** Filter extreme detector ***
00148     ===============================
00149     [..]
00150       (#) Start filter extreme detector using HAL_DFSDM_FilterExdStart().
00151       (#) Get extreme detector maximum value using HAL_DFSDM_FilterGetExdMaxValue().
00152       (#) Get extreme detector minimum value using HAL_DFSDM_FilterGetExdMinValue().
00153       (#) Start filter extreme detector using HAL_DFSDM_FilterExdStop().
00154
00155     *** Filter conversion time ***
00156     ==============================
00157     [..]
00158       (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue().
00159
00160     @endverbatim
00161   ******************************************************************************
00162   * @attention
00163   *
00164   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00165   *
00166   * Redistribution and use in source and binary forms, with or without modification,
00167   * are permitted provided that the following conditions are met:
00168   *   1. Redistributions of source code must retain the above copyright notice,
00169   *      this list of conditions and the following disclaimer.
00170   *   2. Redistributions in binary form must reproduce the above copyright notice,
00171   *      this list of conditions and the following disclaimer in the documentation
00172   *      and/or other materials provided with the distribution.
00173   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00174   *      may be used to endorse or promote products derived from this software
00175   *      without specific prior written permission.
00176   *
00177   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00178   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00179   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00180   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00181   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00182   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00183   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00184   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00185   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00186   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00187   *
00188   ******************************************************************************
00189   */
00190
00191 /* Includes ------------------------------------------------------------------*/
00192 #include "stm32h7xx_hal.h"
00193
00194 /** @addtogroup STM32H7xx_HAL_Driver
00195   * @{
00196   */
00197 #ifdef HAL_DFSDM_MODULE_ENABLED
00198 /** @defgroup DFSDM DFSDM
00199   * @brief DFSDM HAL driver module
00200   * @{
00201   */
00202
00203 /* Private typedef -----------------------------------------------------------*/
00204 /* Private define ------------------------------------------------------------*/
00205 /** @defgroup DFSDM_Private_Define DFSDM Private Define
00206  * @{
00207  */
00208 #define DFSDM_CHCFGR1_CLK_DIV_OFFSET POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV)
00209 #define DFSDM_CHAWSCDR_BKSCD_OFFSET    POSITION_VAL(DFSDM_CHAWSCDR_BKSCD)
00210 #define DFSDM_CHAWSCDR_FOSR_OFFSET     POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR)
00211 #define DFSDM_CHCFGR2_OFFSET_OFFSET  POSITION_VAL(DFSDM_CHCFGR2_OFFSET)
00212 #define DFSDM_CHCFGR2_DTRBS_OFFSET   POSITION_VAL(DFSDM_CHCFGR2_DTRBS)
00213 #define DFSDM_FLTFCR_FOSR_OFFSET        POSITION_VAL(DFSDM_FLTFCR_FOSR)
00214 #define DFSDM_FLTCR1_MSB_RCH_OFFSET     8
00215 #define DFSDM_FLTCR2_EXCH_OFFSET        POSITION_VAL(DFSDM_FLTCR2_EXCH)
00216 #define DFSDM_FLTCR2_AWDCH_OFFSET       POSITION_VAL(DFSDM_FLTCR2_AWDCH)
00217 #define DFSDM_FLTISR_CKABF_OFFSET       POSITION_VAL(DFSDM_FLTISR_CKABF)
00218 #define DFSDM_FLTISR_SCDF_OFFSET        POSITION_VAL(DFSDM_FLTISR_SCDF)
00219 #define DFSDM_FLTICR_CLRCKABF_OFFSET    POSITION_VAL(DFSDM_FLTICR_CLRCKABF)
00220 #define DFSDM_FLTICR_CLRSCDF_OFFSET     POSITION_VAL(DFSDM_FLTICR_CLRSCDF)
00221 #define DFSDM_FLTRDATAR_DATA_OFFSET     POSITION_VAL(DFSDM_FLTRDATAR_RDATA)
00222 #define DFSDM_FLTJDATAR_DATA_OFFSET     POSITION_VAL(DFSDM_FLTJDATAR_JDATA)
00223 #define DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT)
00224 #define DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT)
00225 #define DFSDM_FLTEXMAX_DATA_OFFSET      POSITION_VAL(DFSDM_FLTEXMAX_EXMAX)
00226 #define DFSDM_FLTEXMIN_DATA_OFFSET      POSITION_VAL(DFSDM_FLTEXMIN_EXMIN)
00227 #define DFSDM_FLTCNVTIMR_DATA_OFFSET    POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT)
00228 #define DFSDM_FLTAWSR_HIGH_OFFSET       POSITION_VAL(DFSDM_FLTAWSR_AWHTF)
00229 #define DFSDM_MSB_MASK               0xFFFF0000
00230 #define DFSDM_LSB_MASK               0x0000FFFF
00231 #define DFSDM_CKAB_TIMEOUT           5000
00232 #define DFSDM1_CHANNEL_NUMBER         8
00233 /**
00234   * @}
00235   */
00236
00237 /* Private macro -------------------------------------------------------------*/
00238 /* Private variables ---------------------------------------------------------*/
00239 /** @defgroup DFSDM_Private_Variables DFSDM Private Variables
00240   * @{
00241   */
00242 __IO uint32_t                v_dfsdm1ChannelCounter = 0;
00243 DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL};
00244 /**
00245   * @}
00246   */
00247
00248 /* Private function prototypes -----------------------------------------------*/
00249 /** @defgroup DFSDM_Private_Functions DFSDM Private Functions
00250   * @{
00251   */
00252 static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels);
00253 static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance);
00254 static void     DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00255 static void     DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
00256 static void     DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
00257 static void     DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
00258 static void     DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);
00259 static void     DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma);
00260 static void     DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);
00261 static void     DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);
00262 static void     DFSDM_DMAError(DMA_HandleTypeDef *hdma);
00263 /**
00264   * @}
00265   */
00266
00267 /* Exported functions --------------------------------------------------------*/
00268 /** @defgroup DFSDM_Exported_Functions DFSDM Exported Functions
00269   * @{
00270   */
00271
00272 /** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
00273  *  @brief    Channel initialization and de-initialization functions
00274  *
00275 @verbatim
00276   ==============================================================================
00277         ##### Channel initialization and de-initialization functions #####
00278   ==============================================================================
00279     [..]  This section provides functions allowing to:
00280       (+) Initialize the DFSDM channel.
00281       (+) De-initialize the DFSDM channel.
00282 @endverbatim
00283   * @{
00284   */
00285
00286 /**
00287   * @brief  Initialize the DFSDM channel according to the specified parameters
00288   *         in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
00289   * @param  hdfsdm_channel : DFSDM channel handle.
00290   * @retval HAL status.
00291   */
00292 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00293 {
00294   /* Check DFSDM Channel handle */
00295   if(hdfsdm_channel == NULL)
00296   {
00297     return HAL_ERROR;
00298   }
00299
00300   /* Check parameters */
00301   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00302   assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation));
00303   assert_param(IS_DFSDM_CHANNEL_INPUT(hdfsdm_channel->Init.Input.Multiplexer));
00304   assert_param(IS_DFSDM_CHANNEL_DATA_PACKING(hdfsdm_channel->Init.Input.DataPacking));
00305   assert_param(IS_DFSDM_CHANNEL_INPUT_PINS(hdfsdm_channel->Init.Input.Pins));
00306   assert_param(IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(hdfsdm_channel->Init.SerialInterface.Type));
00307   assert_param(IS_DFSDM_CHANNEL_SPI_CLOCK(hdfsdm_channel->Init.SerialInterface.SpiClock));
00308   assert_param(IS_DFSDM_CHANNEL_FILTER_ORDER(hdfsdm_channel->Init.Awd.FilterOrder));
00309   assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));
00310   assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));
00311   assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));
00312
00313   /* Check that channel has not been already initialized */
00314   if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
00315   {
00316     return HAL_ERROR;
00317   }
00318
00319   /* Call MSP init function */
00320   HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
00321
00322   /* Update the channel counter */
00323   v_dfsdm1ChannelCounter++;
00324
00325   /* Configure output serial clock and enable global DFSDM interface only for first channel */
00326   if(v_dfsdm1ChannelCounter == 1)
00327   {
00328     assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
00329     /* Set the output serial clock source */
00330     DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
00331     DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
00332
00333     /* Reset clock divider */
00334     DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
00335     if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
00336     {
00337       assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
00338       /* Set the output clock divider */
00339       DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1) <<
00340                                              DFSDM_CHCFGR1_CLK_DIV_OFFSET);
00341     }
00342
00343     /* enable the DFSDM global interface */
00344     DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
00345   }
00346
00347   /* Set channel input parameters */
00348   hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
00349                                          DFSDM_CHCFGR1_CHINSEL);
00350   hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
00351                                         hdfsdm_channel->Init.Input.DataPacking |
00352                                         hdfsdm_channel->Init.Input.Pins);
00353
00354   /* Set serial interface parameters */
00355   hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
00356   hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
00357                                         hdfsdm_channel->Init.SerialInterface.SpiClock);
00358
00359   /* Set analog watchdog parameters */
00360   hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
00361   hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
00362                                        ((hdfsdm_channel->Init.Awd.Oversampling - 1) << DFSDM_CHAWSCDR_FOSR_OFFSET));
00363
00364   /* Set channel offset and right bit shift */
00365   hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
00366   hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_OFFSET) |
00367                                         (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_OFFSET));
00368
00369   /* Enable DFSDM channel */
00370   hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
00371
00372   /* Set DFSDM Channel to ready state */
00373   hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
00374
00375   /* Store channel handle in DFSDM channel handle table */
00376   a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
00377
00378   return HAL_OK;
00379 }
00380
00381 /**
00382   * @brief  De-initialize the DFSDM channel.
00383   * @param  hdfsdm_channel : DFSDM channel handle.
00384   * @retval HAL status.
00385   */
00386 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00387 {
00388   /* Check DFSDM Channel handle */
00389   if(hdfsdm_channel == NULL)
00390   {
00391     return HAL_ERROR;
00392   }
00393
00394   /* Check parameters */
00395   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00396
00397   /* Check that channel has not been already deinitialized */
00398   if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)
00399   {
00400     return HAL_ERROR;
00401   }
00402
00403   /* Disable the DFSDM channel */
00404   hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
00405
00406   /* Update the channel counter */
00407   v_dfsdm1ChannelCounter--;
00408
00409   /* Disable global DFSDM at deinit of last channel */
00410   if(v_dfsdm1ChannelCounter == 0)
00411   {
00412     DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
00413   }
00414
00415   /* Call MSP deinit function */
00416   HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);
00417
00418   /* Set DFSDM Channel in reset state */
00419   hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;
00420
00421   /* Reset channel handle in DFSDM channel handle table */
00422   a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = (DFSDM_Channel_HandleTypeDef *) NULL;
00423
00424   return HAL_OK;
00425 }
00426
00427 /**
00428   * @brief  Initialize the DFSDM channel MSP.
00429   * @param  hdfsdm_channel : DFSDM channel handle.
00430   * @retval None
00431   */
00432 __weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00433 {
00434   /* Prevent unused argument(s) compilation warning */
00435   UNUSED(hdfsdm_channel);
00436
00437   /* NOTE : This function should not be modified, when the function is needed,
00438             the HAL_DFSDM_ChannelMspInit could be implemented in the user file.
00439    */
00440 }
00441
00442 /**
00443   * @brief  De-initialize the DFSDM channel MSP.
00444   * @param  hdfsdm_channel : DFSDM channel handle.
00445   * @retval None
00446   */
00447 __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00448 {
00449   /* Prevent unused argument(s) compilation warning */
00450   UNUSED(hdfsdm_channel);
00451
00452   /* NOTE : This function should not be modified, when the function is needed,
00453             the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file.
00454    */
00455 }
00456
00457 /**
00458   * @}
00459   */
00460
00461 /** @defgroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
00462  *  @brief    Channel operation functions
00463  *
00464 @verbatim
00465   ==============================================================================
00466                    ##### Channel operation functions #####
00467   ==============================================================================
00468     [..]  This section provides functions allowing to:
00469       (+) Manage clock absence detector feature.
00470       (+) Manage short circuit detector feature.
00471       (+) Get analog watchdog value.
00472       (+) Modify offset value.
00473 @endverbatim
00474   * @{
00475   */
00476
00477 /**
00478   * @brief  This function allows to start clock absence detection in polling mode.
00479   * @note   Same mode has to be used for all channels.
00480   * @note   If clock is not available on this channel during 5 seconds,
00481   *         clock absence detection will not be activated and function
00482   *         will return HAL_TIMEOUT error.
00483   * @param  hdfsdm_channel : DFSDM channel handle.
00484   * @retval HAL status
00485   */
00486 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00487 {
00488   HAL_StatusTypeDef status = HAL_OK;
00489   uint32_t channel;
00490   uint32_t tickstart;
00491
00492   /* Check parameters */
00493   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00494
00495   /* Check DFSDM channel state */
00496   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00497   {
00498     /* Return error status */
00499     status = HAL_ERROR;
00500   }
00501   else
00502   {
00503     /* Get channel number from channel instance */
00504     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
00505
00506     /* Get timeout */
00507     tickstart = HAL_GetTick();
00508
00509     /* Clear clock absence flag */
00510     while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0)
00511     {
00512       DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
00513
00514       /* Check the Timeout */
00515       if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
00516       {
00517         /* Set timeout status */
00518         status = HAL_TIMEOUT;
00519         break;
00520       }
00521     }
00522
00523     if(status == HAL_OK)
00524     {
00525       /* Start clock absence detection */
00526       hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
00527     }
00528   }
00529   /* Return function status */
00530   return status;
00531 }
00532
00533 /**
00534   * @brief  This function allows to poll for the clock absence detection.
00535   * @param  hdfsdm_channel : DFSDM channel handle.
00536   * @param  Timeout : Timeout value in milliseconds.
00537   * @retval HAL status
00538   */
00539 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
00540                                                uint32_t Timeout)
00541 {
00542   uint32_t tickstart;
00543   uint32_t channel;
00544
00545   /* Check parameters */
00546   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00547
00548   /* Check DFSDM channel state */
00549   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00550   {
00551     /* Return error status */
00552     return HAL_ERROR;
00553   }
00554   else
00555   {
00556     /* Get channel number from channel instance */
00557     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
00558
00559     /* Get timeout */
00560     tickstart = HAL_GetTick();
00561
00562     /* Wait clock absence detection */
00563     while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) == 0)
00564     {
00565       /* Check the Timeout */
00566       if(Timeout != HAL_MAX_DELAY)
00567       {
00568         if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
00569         {
00570           /* Return timeout status */
00571           return HAL_TIMEOUT;
00572         }
00573       }
00574     }
00575
00576     /* Clear clock absence detection flag */
00577     DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
00578
00579     /* Return function status */
00580     return HAL_OK;
00581   }
00582 }
00583
00584 /**
00585   * @brief  This function allows to stop clock absence detection in polling mode.
00586   * @param  hdfsdm_channel : DFSDM channel handle.
00587   * @retval HAL status
00588   */
00589 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00590 {
00591   HAL_StatusTypeDef status = HAL_OK;
00592   uint32_t channel;
00593
00594   /* Check parameters */
00595   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00596
00597   /* Check DFSDM channel state */
00598   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00599   {
00600     /* Return error status */
00601     status = HAL_ERROR;
00602   }
00603   else
00604   {
00605     /* Stop clock absence detection */
00606     hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
00607
00608     /* Clear clock absence flag */
00609     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
00610     DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
00611   }
00612   /* Return function status */
00613   return status;
00614 }
00615
00616 /**
00617   * @brief  This function allows to start clock absence detection in interrupt mode.
00618   * @note   Same mode has to be used for all channels.
00619   * @note   If clock is not available on this channel during 5 seconds,
00620   *         clock absence detection will not be activated and function
00621   *         will return HAL_TIMEOUT error.
00622   * @param  hdfsdm_channel : DFSDM channel handle.
00623   * @retval HAL status
00624   */
00625 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00626 {
00627   HAL_StatusTypeDef status = HAL_OK;
00628   uint32_t channel;
00629   uint32_t tickstart;
00630
00631   /* Check parameters */
00632   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00633
00634   /* Check DFSDM channel state */
00635   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00636   {
00637     /* Return error status */
00638     status = HAL_ERROR;
00639   }
00640   else
00641   {
00642     /* Get channel number from channel instance */
00643     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
00644
00645     /* Get timeout */
00646     tickstart = HAL_GetTick();
00647
00648     /* Clear clock absence flag */
00649     while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0)
00650     {
00651       DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
00652
00653       /* Check the Timeout */
00654       if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
00655       {
00656         /* Set timeout status */
00657         status = HAL_TIMEOUT;
00658         break;
00659       }
00660     }
00661
00662     if(status == HAL_OK)
00663     {
00664       /* Activate clock absence detection interrupt */
00665       DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_CKABIE;
00666
00667       /* Start clock absence detection */
00668       hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
00669     }
00670   }
00671   /* Return function status */
00672   return status;
00673 }
00674
00675 /**
00676   * @brief  Clock absence detection callback.
00677   * @param  hdfsdm_channel : DFSDM channel handle.
00678   * @retval None
00679   */
00680 __weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00681 {
00682   /* Prevent unused argument(s) compilation warning */
00683   UNUSED(hdfsdm_channel);
00684
00685   /* NOTE : This function should not be modified, when the callback is needed,
00686             the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file
00687    */
00688 }
00689
00690 /**
00691   * @brief  This function allows to stop clock absence detection in interrupt mode.
00692   * @note   Interrupt will be disabled for all channels
00693   * @param  hdfsdm_channel : DFSDM channel handle.
00694   * @retval HAL status
00695   */
00696 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00697 {
00698   HAL_StatusTypeDef status = HAL_OK;
00699   uint32_t channel;
00700
00701   /* Check parameters */
00702   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00703
00704   /* Check DFSDM channel state */
00705   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00706   {
00707     /* Return error status */
00708     status = HAL_ERROR;
00709   }
00710   else
00711   {
00712     /* Stop clock absence detection */
00713     hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
00714
00715     /* Clear clock absence flag */
00716     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
00717     DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
00718
00719     /* Disable clock absence detection interrupt */
00720     DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);
00721   }
00722   /* Return function status */
00723   return status;
00724 }
00725
00726 /**
00727   * @brief  This function allows to start short circuit detection in polling mode.
00728   * @note   Same mode has to be used for all channels
00729   * @param  hdfsdm_channel : DFSDM channel handle.
00730   * @param  Threshold : Short circuit detector threshold.
00731   *         This parameter must be a number between Min_Data = 0 and Max_Data = 255.
00732   * @param  BreakSignal : Break signals assigned to short circuit event.
00733   *         This parameter can be a values combination of @ref DFSDM_BreakSignals.
00734   * @retval HAL status
00735   */
00736 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
00737                                             uint32_t Threshold,
00738                                             uint32_t BreakSignal)
00739 {
00740   HAL_StatusTypeDef status = HAL_OK;
00741
00742   /* Check parameters */
00743   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00744   assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
00745   assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
00746
00747   /* Check DFSDM channel state */
00748   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00749   {
00750     /* Return error status */
00751     status = HAL_ERROR;
00752   }
00753   else
00754   {
00755     /* Configure threshold and break signals */
00756     hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
00757     hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \
00758                                          Threshold);
00759
00760     /* Start short circuit detection */
00761     hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
00762   }
00763   /* Return function status */
00764   return status;
00765 }
00766
00767 /**
00768   * @brief  This function allows to poll for the short circuit detection.
00769   * @param  hdfsdm_channel : DFSDM channel handle.
00770   * @param  Timeout : Timeout value in milliseconds.
00771   * @retval HAL status
00772   */
00773 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
00774                                               uint32_t Timeout)
00775 {
00776   uint32_t tickstart;
00777   uint32_t channel;
00778
00779   /* Check parameters */
00780   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00781
00782   /* Check DFSDM channel state */
00783   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00784   {
00785     /* Return error status */
00786     return HAL_ERROR;
00787   }
00788   else
00789   {
00790     /* Get channel number from channel instance */
00791     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
00792
00793     /* Get timeout */
00794     tickstart = HAL_GetTick();
00795
00796     /* Wait short circuit detection */
00797     while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_OFFSET + channel)) == 0)
00798     {
00799       /* Check the Timeout */
00800       if(Timeout != HAL_MAX_DELAY)
00801       {
00802         if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
00803         {
00804           /* Return timeout status */
00805           return HAL_TIMEOUT;
00806         }
00807       }
00808     }
00809
00810     /* Clear short circuit detection flag */
00811     DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
00812
00813     /* Return function status */
00814     return HAL_OK;
00815   }
00816 }
00817
00818 /**
00819   * @brief  This function allows to stop short circuit detection in polling mode.
00820   * @param  hdfsdm_channel : DFSDM channel handle.
00821   * @retval HAL status
00822   */
00823 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00824 {
00825   HAL_StatusTypeDef status = HAL_OK;
00826   uint32_t channel;
00827
00828   /* Check parameters */
00829   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00830
00831   /* Check DFSDM channel state */
00832   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00833   {
00834     /* Return error status */
00835     status = HAL_ERROR;
00836   }
00837   else
00838   {
00839     /* Stop short circuit detection */
00840     hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
00841
00842     /* Clear short circuit detection flag */
00843     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
00844     DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
00845   }
00846   /* Return function status */
00847   return status;
00848 }
00849
00850 /**
00851   * @brief  This function allows to start short circuit detection in interrupt mode.
00852   * @note   Same mode has to be used for all channels
00853   * @param  hdfsdm_channel : DFSDM channel handle.
00854   * @param  Threshold : Short circuit detector threshold.
00855   *         This parameter must be a number between Min_Data = 0 and Max_Data = 255.
00856   * @param  BreakSignal : Break signals assigned to short circuit event.
00857   *         This parameter can be a values combination of @ref DFSDM_BreakSignals.
00858   * @retval HAL status
00859   */
00860 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
00861                                                uint32_t Threshold,
00862                                                uint32_t BreakSignal)
00863 {
00864   HAL_StatusTypeDef status = HAL_OK;
00865
00866   /* Check parameters */
00867   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00868   assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
00869   assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
00870
00871   /* Check DFSDM channel state */
00872   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00873   {
00874     /* Return error status */
00875     status = HAL_ERROR;
00876   }
00877   else
00878   {
00879     /* Activate short circuit detection interrupt */
00880     DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_SCDIE;
00881
00882     /* Configure threshold and break signals */
00883     hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
00884     hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \
00885                                          Threshold);
00886
00887     /* Start short circuit detection */
00888     hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
00889   }
00890   /* Return function status */
00891   return status;
00892 }
00893
00894 /**
00895   * @brief  Short circuit detection callback.
00896   * @param  hdfsdm_channel : DFSDM channel handle.
00897   * @retval None
00898   */
00899 __weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00900 {
00901   /* Prevent unused argument(s) compilation warning */
00902   UNUSED(hdfsdm_channel);
00903
00904   /* NOTE : This function should not be modified, when the callback is needed,
00905             the HAL_DFSDM_ChannelScdCallback could be implemented in the user file
00906    */
00907 }
00908
00909 /**
00910   * @brief  This function allows to stop short circuit detection in interrupt mode.
00911   * @note   Interrupt will be disabled for all channels
00912   * @param  hdfsdm_channel : DFSDM channel handle.
00913   * @retval HAL status
00914   */
00915 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00916 {
00917   HAL_StatusTypeDef status = HAL_OK;
00918   uint32_t channel;
00919
00920   /* Check parameters */
00921   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00922
00923   /* Check DFSDM channel state */
00924   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00925   {
00926     /* Return error status */
00927     status = HAL_ERROR;
00928   }
00929   else
00930   {
00931     /* Stop short circuit detection */
00932     hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
00933
00934     /* Clear short circuit detection flag */
00935     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
00936     DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
00937
00938     /* Disable short circuit detection interrupt */
00939     DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);
00940   }
00941   /* Return function status */
00942   return status;
00943 }
00944
00945 /**
00946   * @brief  This function allows to get channel analog watchdog value.
00947   * @param  hdfsdm_channel : DFSDM channel handle.
00948   * @retval Channel analog watchdog value.
00949   */
00950 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00951 {
00952   return (int16_t) hdfsdm_channel->Instance->CHWDATAR;
00953 }
00954
00955 /**
00956   * @brief  This function allows to modify channel offset value.
00957   * @param  hdfsdm_channel : DFSDM channel handle.
00958   * @param  Offset : DFSDM channel offset.
00959   *         This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607.
00960   * @retval HAL status.
00961   */
00962 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
00963                                                 int32_t Offset)
00964 {
00965   HAL_StatusTypeDef status = HAL_OK;
00966
00967   /* Check parameters */
00968   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00969   assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset));
00970
00971   /* Check DFSDM channel state */
00972   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00973   {
00974     /* Return error status */
00975     status = HAL_ERROR;
00976   }
00977   else
00978   {
00979     /* Modify channel offset */
00980     hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET);
00981     hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_OFFSET);
00982   }
00983   /* Return function status */
00984   return status;
00985 }
00986
00987 /**
00988   * @}
00989   */
00990
00991 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
00992  *  @brief    Channel state function
00993  *
00994 @verbatim
00995   ==============================================================================
00996                    ##### Channel state function #####
00997   ==============================================================================
00998     [..]  This section provides function allowing to:
00999       (+) Get channel handle state.
01000 @endverbatim
01001   * @{
01002   */
01003
01004 /**
01005   * @brief  This function allows to get the current DFSDM channel handle state.
01006   * @param  hdfsdm_channel : DFSDM channel handle.
01007   * @retval DFSDM channel state.
01008   */
01009 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
01010 {
01011   /* Return DFSDM channel handle state */
01012   return hdfsdm_channel->State;
01013 }
01014
01015 /**
01016   * @}
01017   */
01018
01019 /** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
01020  *  @brief    Filter initialization and de-initialization functions
01021  *
01022 @verbatim
01023   ==============================================================================
01024         ##### Filter initialization and de-initialization functions #####
01025   ==============================================================================
01026     [..]  This section provides functions allowing to:
01027       (+) Initialize the DFSDM filter.
01028       (+) De-initialize the DFSDM filter.
01029 @endverbatim
01030   * @{
01031   */
01032
01033 /**
01034   * @brief  Initialize the DFSDM filter according to the specified parameters
01035   *         in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
01036   * @param  hdfsdm_filter : DFSDM filter handle.
01037   * @retval HAL status.
01038   */
01039 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01040 {
01041   /* Check DFSDM Channel handle */
01042   if(hdfsdm_filter == NULL)
01043   {
01044     return HAL_ERROR;
01045   }
01046
01047   /* Check parameters */
01048   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01049   assert_param(IS_DFSDM_FILTER_REG_TRIGGER(hdfsdm_filter->Init.RegularParam.Trigger));
01050   assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.FastMode));
01051   assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.DmaMode));
01052   assert_param(IS_DFSDM_FILTER_INJ_TRIGGER(hdfsdm_filter->Init.InjectedParam.Trigger));
01053   assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.ScanMode));
01054   assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.DmaMode));
01055   assert_param(IS_DFSDM_FILTER_SINC_ORDER(hdfsdm_filter->Init.FilterParam.SincOrder));
01056   assert_param(IS_DFSDM_FILTER_OVS_RATIO(hdfsdm_filter->Init.FilterParam.Oversampling));
01057   assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling));
01058
01059   /* Check parameters compatibility */
01060   if((hdfsdm_filter->Instance == DFSDM1_Filter0) &&
01061     ((hdfsdm_filter->Init.RegularParam.Trigger  == DFSDM_FILTER_SYNC_TRIGGER) ||
01062      (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))
01063   {
01064     return HAL_ERROR;
01065   }
01066
01067   /* Initialize DFSDM filter variables with default values */
01068   hdfsdm_filter->RegularContMode     = DFSDM_CONTINUOUS_CONV_OFF;
01069   hdfsdm_filter->InjectedChannelsNbr = 1;
01070   hdfsdm_filter->InjConvRemaining    = 1;
01071   hdfsdm_filter->ErrorCode           = DFSDM_FILTER_ERROR_NONE;
01072
01073   /* Call MSP init function */
01074   HAL_DFSDM_FilterMspInit(hdfsdm_filter);
01075
01076   /* Set regular parameters */
01077   hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
01078   if(hdfsdm_filter->Init.RegularParam.FastMode == ENABLE)
01079   {
01080     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST;
01081   }
01082   else
01083   {
01084     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST);
01085   }
01086
01087   if(hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE)
01088   {
01089     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN;
01090   }
01091   else
01092   {
01093     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RDMAEN);
01094   }
01095
01096   /* Set injected parameters */
01097   hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL);
01098   if(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER)
01099   {
01100     assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger));
01101     assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge));
01102     hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger);
01103   }
01104
01105   if(hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE)
01106   {
01107     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN;
01108   }
01109   else
01110   {
01111     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN);
01112   }
01113
01114   if(hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE)
01115   {
01116     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN;
01117   }
01118   else
01119   {
01120     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN);
01121   }
01122
01123   /* Set filter parameters */
01124   hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);
01125   hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder |
01126                                     ((hdfsdm_filter->Init.FilterParam.Oversampling - 1) << DFSDM_FLTFCR_FOSR_OFFSET) |
01127                                   (hdfsdm_filter->Init.FilterParam.IntOversampling - 1));
01128
01129   /* Store regular and injected triggers and injected scan mode*/
01130   hdfsdm_filter->RegularTrigger   = hdfsdm_filter->Init.RegularParam.Trigger;
01131   hdfsdm_filter->InjectedTrigger  = hdfsdm_filter->Init.InjectedParam.Trigger;
01132   hdfsdm_filter->ExtTriggerEdge   = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge;
01133   hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode;
01134
01135   /* Enable DFSDM filter */
01136   hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
01137
01138   /* Set DFSDM filter to ready state */
01139   hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY;
01140
01141   return HAL_OK;
01142 }
01143
01144 /**
01145   * @brief  De-initializes the DFSDM filter.
01146   * @param  hdfsdm_filter : DFSDM filter handle.
01147   * @retval HAL status.
01148   */
01149 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01150 {
01151   /* Check DFSDM filter handle */
01152   if(hdfsdm_filter == NULL)
01153   {
01154     return HAL_ERROR;
01155   }
01156
01157   /* Check parameters */
01158   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01159
01160   /* Disable the DFSDM filter */
01161   hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
01162
01163   /* Call MSP deinit function */
01164   HAL_DFSDM_FilterMspDeInit(hdfsdm_filter);
01165
01166   /* Set DFSDM filter in reset state */
01167   hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET;
01168
01169   return HAL_OK;
01170 }
01171
01172 /**
01173   * @brief  Initializes the DFSDM filter MSP.
01174   * @param  hdfsdm_filter : DFSDM filter handle.
01175   * @retval None
01176   */
01177 __weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01178 {
01179   /* Prevent unused argument(s) compilation warning */
01180   UNUSED(hdfsdm_filter);
01181
01182   /* NOTE : This function should not be modified, when the function is needed,
01183             the HAL_DFSDM_FilterMspInit could be implemented in the user file.
01184    */
01185 }
01186
01187 /**
01188   * @brief  De-initializes the DFSDM filter MSP.
01189   * @param  hdfsdm_filter : DFSDM filter handle.
01190   * @retval None
01191   */
01192 __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01193 {
01194   /* Prevent unused argument(s) compilation warning */
01195   UNUSED(hdfsdm_filter);
01196
01197   /* NOTE : This function should not be modified, when the function is needed,
01198             the HAL_DFSDM_FilterMspDeInit could be implemented in the user file.
01199    */
01200 }
01201
01202 /**
01203   * @}
01204   */
01205
01206 /** @defgroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
01207  *  @brief    Filter control functions
01208  *
01209 @verbatim
01210   ==============================================================================
01211                     ##### Filter control functions #####
01212   ==============================================================================
01213     [..]  This section provides functions allowing to:
01214       (+) Select channel and enable/disable continuous mode for regular conversion.
01215       (+) Select channels for injected conversion.
01216 @endverbatim
01217   * @{
01218   */
01219
01220 /**
01221   * @brief  This function allows to select channel and to enable/disable
01222   *         continuous mode for regular conversion.
01223   * @param  hdfsdm_filter : DFSDM filter handle.
01224   * @param  Channel : Channel for regular conversion.
01225   *         This parameter can be a value of @ref DFSDM_Channel_Selection.
01226   * @param  ContinuousMode : Enable/disable continuous mode for regular conversion.
01227   *         This parameter can be a value of @ref DFSDM_ContinuousMode.
01228   * @retval HAL status
01229   */
01230 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
01231                                                    uint32_t                    Channel,
01232                                                    uint32_t                    ContinuousMode)
01233 {
01234   HAL_StatusTypeDef status = HAL_OK;
01235
01236   /* Check parameters */
01237   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01238   assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel));
01239   assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode));
01240
01241   /* Check DFSDM filter state */
01242   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
01243      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
01244   {
01245     /* Configure channel and continuous mode for regular conversion */
01246     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT);
01247     if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON)
01248     {
01249       hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) |
01250                                                      DFSDM_FLTCR1_RCONT);
01251     }
01252     else
01253     {
01254       hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) ((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET);
01255     }
01256     /* Store continuous mode information */
01257     hdfsdm_filter->RegularContMode = ContinuousMode;
01258   }
01259   else
01260   {
01261     status = HAL_ERROR;
01262   }
01263
01264   /* Return function status */
01265   return status;
01266 }
01267
01268 /**
01269   * @brief  This function allows to select channels for injected conversion.
01270   * @param  hdfsdm_filter : DFSDM filter handle.
01271   * @param  Channel : Channels for injected conversion.
01272   *         This parameter can be a values combination of @ref DFSDM_Channel_Selection.
01273   * @retval HAL status
01274   */
01275 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
01276                                                    uint32_t                    Channel)
01277 {
01278   HAL_StatusTypeDef status = HAL_OK;
01279
01280   /* Check parameters */
01281   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01282   assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
01283
01284   /* Check DFSDM filter state */
01285   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
01286      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
01287   {
01288     /* Configure channel for injected conversion */
01289     hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK);
01290     /* Store number of injected channels */
01291     hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel);
01292     /* Update number of injected channels remaining */
01293     hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
01294                                       hdfsdm_filter->InjectedChannelsNbr : 1;
01295   }
01296   else
01297   {
01298     status = HAL_ERROR;
01299   }
01300   /* Return function status */
01301   return status;
01302 }
01303
01304 /**
01305   * @}
01306   */
01307
01308 /** @defgroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
01309  *  @brief    Filter operation functions
01310  *
01311 @verbatim
01312   ==============================================================================
01313                     ##### Filter operation functions #####
01314   ==============================================================================
01315     [..]  This section provides functions allowing to:
01316       (+) Start conversion of regular/injected channel.
01317       (+) Poll for the end of regular/injected conversion.
01318       (+) Stop conversion of regular/injected channel.
01319       (+) Start conversion of regular/injected channel and enable interrupt.
01320       (+) Call the callback functions at the end of regular/injected conversions.
01321       (+) Stop conversion of regular/injected channel and disable interrupt.
01322       (+) Start conversion of regular/injected channel and enable DMA transfer.
01323       (+) Stop conversion of regular/injected channel and disable DMA transfer.
01324       (+) Start analog watchdog and enable interrupt.
01325       (+) Call the callback function when analog watchdog occurs.
01326       (+) Stop analog watchdog and disable interrupt.
01327       (+) Start extreme detector.
01328       (+) Stop extreme detector.
01329       (+) Get result of regular channel conversion.
01330       (+) Get result of injected channel conversion.
01331       (+) Get extreme detector maximum and minimum values.
01332       (+) Get conversion time.
01333       (+) Handle DFSDM interrupt request.
01334 @endverbatim
01335   * @{
01336   */
01337
01338 /**
01339   * @brief  This function allows to start regular conversion in polling mode.
01340   * @note   This function should be called only when DFSDM filter instance is
01341   *         in idle state or if injected conversion is ongoing.
01342   * @param  hdfsdm_filter : DFSDM filter handle.
01343   * @retval HAL status
01344   */
01345 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01346 {
01347   HAL_StatusTypeDef status = HAL_OK;
01348
01349   /* Check parameters */
01350   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01351
01352   /* Check DFSDM filter state */
01353   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
01354      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
01355   {
01356     /* Start regular conversion */
01357     DFSDM_RegConvStart(hdfsdm_filter);
01358   }
01359   else
01360   {
01361     status = HAL_ERROR;
01362   }
01363   /* Return function status */
01364   return status;
01365 }
01366
01367 /**
01368   * @brief  This function allows to poll for the end of regular conversion.
01369   * @note   This function should be called only if regular conversion is ongoing.
01370   * @param  hdfsdm_filter : DFSDM filter handle.
01371   * @param  Timeout : Timeout value in milliseconds.
01372   * @retval HAL status
01373   */
01374 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
01375                                                        uint32_t                    Timeout)
01376 {
01377   uint32_t tickstart;
01378
01379   /* Check parameters */
01380   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01381
01382   /* Check DFSDM filter state */
01383   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
01384      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
01385   {
01386     /* Return error status */
01387     return HAL_ERROR;
01388   }
01389   else
01390   {
01391     /* Get timeout */
01392     tickstart = HAL_GetTick();
01393
01394     /* Wait end of regular conversion */
01395     while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF)
01396     {
01397       /* Check the Timeout */
01398       if(Timeout != HAL_MAX_DELAY)
01399       {
01400         if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
01401         {
01402           /* Return timeout status */
01403           return HAL_TIMEOUT;
01404         }
01405       }
01406     }
01407     /* Check if overrun occurs */
01408     if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF)
01409     {
01410       /* Update error code and call error callback */
01411       hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
01412       HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
01413
01414       /* Clear regular overrun flag */
01415       hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
01416     }
01417     /* Update DFSDM filter state only if not continuous conversion and SW trigger */
01418     if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
01419        (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
01420     {
01421       hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
01422                              HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
01423     }
01424     /* Return function status */
01425     return HAL_OK;
01426   }
01427 }
01428
01429 /**
01430   * @brief  This function allows to stop regular conversion in polling mode.
01431   * @note   This function should be called only if regular conversion is ongoing.
01432   * @param  hdfsdm_filter : DFSDM filter handle.
01433   * @retval HAL status
01434   */
01435 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01436 {
01437   HAL_StatusTypeDef status = HAL_OK;
01438
01439   /* Check parameters */
01440   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01441
01442   /* Check DFSDM filter state */
01443   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
01444      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
01445   {
01446     /* Return error status */
01447     status = HAL_ERROR;
01448   }
01449   else
01450   {
01451     /* Stop regular conversion */
01452     DFSDM_RegConvStop(hdfsdm_filter);
01453   }
01454   /* Return function status */
01455   return status;
01456 }
01457
01458 /**
01459   * @brief  This function allows to start regular conversion in interrupt mode.
01460   * @note   This function should be called only when DFSDM filter instance is
01461   *         in idle state or if injected conversion is ongoing.
01462   * @param  hdfsdm_filter : DFSDM filter handle.
01463   * @retval HAL status
01464   */
01465 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01466 {
01467   HAL_StatusTypeDef status = HAL_OK;
01468
01469   /* Check parameters */
01470   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01471
01472   /* Check DFSDM filter state */
01473   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
01474      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
01475   {
01476     /* Enable interrupts for regular conversions */
01477     hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
01478
01479     /* Start regular conversion */
01480     DFSDM_RegConvStart(hdfsdm_filter);
01481   }
01482   else
01483   {
01484     status = HAL_ERROR;
01485   }
01486   /* Return function status */
01487   return status;
01488 }
01489
01490 /**
01491   * @brief  This function allows to stop regular conversion in interrupt mode.
01492   * @note   This function should be called only if regular conversion is ongoing.
01493   * @param  hdfsdm_filter : DFSDM filter handle.
01494   * @retval HAL status
01495   */
01496 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01497 {
01498   HAL_StatusTypeDef status = HAL_OK;
01499
01500   /* Check parameters */
01501   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01502
01503   /* Check DFSDM filter state */
01504   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
01505      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
01506   {
01507     /* Return error status */
01508     status = HAL_ERROR;
01509   }
01510   else
01511   {
01512     /* Disable interrupts for regular conversions */
01513     hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
01514
01515     /* Stop regular conversion */
01516     DFSDM_RegConvStop(hdfsdm_filter);
01517   }
01518   /* Return function status */
01519   return status;
01520 }
01521
01522 /**
01523   * @brief  This function allows to start regular conversion in DMA mode.
01524   * @note   This function should be called only when DFSDM filter instance is
01525   *         in idle state or if injected conversion is ongoing.
01526   *         Please note that data on buffer will contain signed regular conversion
01527   *         value on 24 most significant bits and corresponding channel on 3 least
01528   *         significant bits.
01529   * @param  hdfsdm_filter : DFSDM filter handle.
01530   * @param  pData : The destination buffer address.
01531   * @param  Length : The length of data to be transferred from DFSDM filter to memory.
01532   * @retval HAL status
01533   */
01534 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
01535                                                    int32_t                    *pData,
01536                                                    uint32_t                    Length)
01537 {
01538   HAL_StatusTypeDef status = HAL_OK;
01539
01540   /* Check parameters */
01541   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01542
01543   /* Check destination address and length */
01544   if((pData == NULL) || (Length == 0))
01545   {
01546     status = HAL_ERROR;
01547   }
01548   /* Check that DMA is enabled for regular conversion */
01549   else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
01550   {
01551     status = HAL_ERROR;
01552   }
01553   /* Check parameters compatibility */
01554   else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
01555           (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
01556           (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
01557           (Length != 1))
01558   {
01559     status = HAL_ERROR;
01560   }
01561   else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
01562           (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
01563           (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
01564   {
01565     status = HAL_ERROR;
01566   }
01567   /* Check DFSDM filter state */
01568   else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
01569           (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
01570   {
01571     /* Set callbacks on DMA handler */
01572     hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
01573     hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
01574     hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
01575                                                    DFSDM_DMARegularHalfConvCplt : NULL;
01576
01577     /* Start DMA in interrupt mode */
01578     if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \
01579                         (uint32_t) pData, Length) != HAL_OK)
01580     {
01581       /* Set DFSDM filter in error state */
01582       hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
01583       status = HAL_ERROR;
01584     }
01585     else
01586     {
01587       /* Start regular conversion */
01588       DFSDM_RegConvStart(hdfsdm_filter);
01589     }
01590   }
01591   else
01592   {
01593     status = HAL_ERROR;
01594   }
01595   /* Return function status */
01596   return status;
01597 }
01598
01599 /**
01600   * @brief  This function allows to start regular conversion in DMA mode and to get
01601   *         only the 16 most significant bits of conversion.
01602   * @note   This function should be called only when DFSDM filter instance is
01603   *         in idle state or if injected conversion is ongoing.
01604   *         Please note that data on buffer will contain signed 16 most significant
01605   *         bits of regular conversion.
01606   * @param  hdfsdm_filter : DFSDM filter handle.
01607   * @param  pData : The destination buffer address.
01608   * @param  Length : The length of data to be transferred from DFSDM filter to memory.
01609   * @retval HAL status
01610   */
01611 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
01612                                                       int16_t                    *pData,
01613                                                       uint32_t                    Length)
01614 {
01615   HAL_StatusTypeDef status = HAL_OK;
01616
01617   /* Check parameters */
01618   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01619
01620   /* Check destination address and length */
01621   if((pData == NULL) || (Length == 0))
01622   {
01623     status = HAL_ERROR;
01624   }
01625   /* Check that DMA is enabled for regular conversion */
01626   else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
01627   {
01628     status = HAL_ERROR;
01629   }
01630   /* Check parameters compatibility */
01631   else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
01632           (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
01633           (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
01634           (Length != 1))
01635   {
01636     status = HAL_ERROR;
01637   }
01638   else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
01639           (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
01640           (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
01641   {
01642     status = HAL_ERROR;
01643   }
01644   /* Check DFSDM filter state */
01645   else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
01646           (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
01647   {
01648     /* Set callbacks on DMA handler */
01649     hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
01650     hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
01651     hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
01652                                                    DFSDM_DMARegularHalfConvCplt : NULL;
01653
01654     /* Start DMA in interrupt mode */
01655     if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2, \
01656                         (uint32_t) pData, Length) != HAL_OK)
01657     {
01658       /* Set DFSDM filter in error state */
01659       hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
01660       status = HAL_ERROR;
01661     }
01662     else
01663     {
01664       /* Start regular conversion */
01665       DFSDM_RegConvStart(hdfsdm_filter);
01666     }
01667   }
01668   else
01669   {
01670     status = HAL_ERROR;
01671   }
01672   /* Return function status */
01673   return status;
01674 }
01675
01676 /**
01677   * @brief  This function allows to stop regular conversion in DMA mode.
01678   * @note   This function should be called only if regular conversion is ongoing.
01679   * @param  hdfsdm_filter : DFSDM filter handle.
01680   * @retval HAL status
01681   */
01682 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01683 {
01684   HAL_StatusTypeDef status = HAL_OK;
01685
01686   /* Check parameters */
01687   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01688
01689   /* Check DFSDM filter state */
01690   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
01691      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
01692   {
01693     /* Return error status */
01694     status = HAL_ERROR;
01695   }
01696   else
01697   {
01698     /* Stop current DMA transfer */
01699     if(HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK)
01700     {
01701       /* Set DFSDM filter in error state */
01702       hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
01703       status = HAL_ERROR;
01704     }
01705     else
01706     {
01707       /* Stop regular conversion */
01708       DFSDM_RegConvStop(hdfsdm_filter);
01709     }
01710   }
01711   /* Return function status */
01712   return status;
01713 }
01714
01715 /**
01716   * @brief  This function allows to get regular conversion value.
01717   * @param  hdfsdm_filter : DFSDM filter handle.
01718   * @param  Channel : Corresponding channel of regular conversion.
01719   * @retval Regular conversion value
01720   */
01721 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
01722                                         uint32_t                   *Channel)
01723 {
01724   uint32_t reg = 0;
01725   int32_t  value = 0;
01726
01727   /* Check parameters */
01728   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01729   assert_param(Channel != NULL);
01730
01731   /* Get value of data register for regular channel */
01732   reg = hdfsdm_filter->Instance->FLTRDATAR;
01733
01734   /* Extract channel and regular conversion value */
01735   *Channel = (reg & DFSDM_FLTRDATAR_RDATACH);
01736   value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_DATA_OFFSET);
01737
01738   /* return regular conversion value */
01739   return value;
01740 }
01741
01742 /**
01743   * @brief  This function allows to start injected conversion in polling mode.
01744   * @note   This function should be called only when DFSDM filter instance is
01745   *         in idle state or if regular conversion is ongoing.
01746   * @param  hdfsdm_filter : DFSDM filter handle.
01747   * @retval HAL status
01748   */
01749 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01750 {
01751   HAL_StatusTypeDef status = HAL_OK;
01752
01753   /* Check parameters */
01754   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01755
01756   /* Check DFSDM filter state */
01757   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
01758      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
01759   {
01760     /* Start injected conversion */
01761     DFSDM_InjConvStart(hdfsdm_filter);
01762   }
01763   else
01764   {
01765     status = HAL_ERROR;
01766   }
01767   /* Return function status */
01768   return status;
01769 }
01770
01771 /**
01772   * @brief  This function allows to poll for the end of injected conversion.
01773   * @note   This function should be called only if injected conversion is ongoing.
01774   * @param  hdfsdm_filter : DFSDM filter handle.
01775   * @param  Timeout : Timeout value in milliseconds.
01776   * @retval HAL status
01777   */
01778 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
01779                                                        uint32_t                    Timeout)
01780 {
01781   uint32_t tickstart;
01782
01783   /* Check parameters */
01784   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01785
01786   /* Check DFSDM filter state */
01787   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
01788      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
01789   {
01790     /* Return error status */
01791     return HAL_ERROR;
01792   }
01793   else
01794   {
01795     /* Get timeout */
01796     tickstart = HAL_GetTick();
01797
01798     /* Wait end of injected conversions */
01799     while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF)
01800     {
01801       /* Check the Timeout */
01802       if(Timeout != HAL_MAX_DELAY)
01803       {
01804         if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
01805         {
01806           /* Return timeout status */
01807           return HAL_TIMEOUT;
01808         }
01809       }
01810     }
01811     /* Check if overrun occurs */
01812     if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF)
01813     {
01814       /* Update error code and call error callback */
01815       hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
01816       HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
01817
01818       /* Clear injected overrun flag */
01819       hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
01820     }
01821
01822     /* Update remaining injected conversions */
01823     hdfsdm_filter->InjConvRemaining--;
01824     if(hdfsdm_filter->InjConvRemaining == 0)
01825     {
01826       /* Update DFSDM filter state only if trigger is software */
01827       if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
01828       {
01829         hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
01830                                HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
01831       }
01832
01833       /* end of injected sequence, reset the value */
01834       hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
01835                                          hdfsdm_filter->InjectedChannelsNbr : 1;
01836     }
01837
01838     /* Return function status */
01839     return HAL_OK;
01840   }
01841 }
01842
01843 /**
01844   * @brief  This function allows to stop injected conversion in polling mode.
01845   * @note   This function should be called only if injected conversion is ongoing.
01846   * @param  hdfsdm_filter : DFSDM filter handle.
01847   * @retval HAL status
01848   */
01849 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01850 {
01851   HAL_StatusTypeDef status = HAL_OK;
01852
01853   /* Check parameters */
01854   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01855
01856   /* Check DFSDM filter state */
01857   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
01858      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
01859   {
01860     /* Return error status */
01861     status = HAL_ERROR;
01862   }
01863   else
01864   {
01865     /* Stop injected conversion */
01866     DFSDM_InjConvStop(hdfsdm_filter);
01867   }
01868   /* Return function status */
01869   return status;
01870 }
01871
01872 /**
01873   * @brief  This function allows to start injected conversion in interrupt mode.
01874   * @note   This function should be called only when DFSDM filter instance is
01875   *         in idle state or if regular conversion is ongoing.
01876   * @param  hdfsdm_filter : DFSDM filter handle.
01877   * @retval HAL status
01878   */
01879 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01880 {
01881   HAL_StatusTypeDef status = HAL_OK;
01882
01883   /* Check parameters */
01884   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01885
01886   /* Check DFSDM filter state */
01887   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
01888      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
01889   {
01890     /* Enable interrupts for injected conversions */
01891     hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
01892
01893     /* Start injected conversion */
01894     DFSDM_InjConvStart(hdfsdm_filter);
01895   }
01896   else
01897   {
01898     status = HAL_ERROR;
01899   }
01900   /* Return function status */
01901   return status;
01902 }
01903
01904 /**
01905   * @brief  This function allows to stop injected conversion in interrupt mode.
01906   * @note   This function should be called only if injected conversion is ongoing.
01907   * @param  hdfsdm_filter : DFSDM filter handle.
01908   * @retval HAL status
01909   */
01910 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01911 {
01912   HAL_StatusTypeDef status = HAL_OK;
01913
01914   /* Check parameters */
01915   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01916
01917   /* Check DFSDM filter state */
01918   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
01919      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
01920   {
01921     /* Return error status */
01922     status = HAL_ERROR;
01923   }
01924   else
01925   {
01926     /* Disable interrupts for injected conversions */
01927     hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
01928
01929     /* Stop injected conversion */
01930     DFSDM_InjConvStop(hdfsdm_filter);
01931   }
01932   /* Return function status */
01933   return status;
01934 }
01935
01936 /**
01937   * @brief  This function allows to start injected conversion in DMA mode.
01938   * @note   This function should be called only when DFSDM filter instance is
01939   *         in idle state or if regular conversion is ongoing.
01940   *         Please note that data on buffer will contain signed injected conversion
01941   *         value on 24 most significant bits and corresponding channel on 3 least
01942   *         significant bits.
01943   * @param  hdfsdm_filter : DFSDM filter handle.
01944   * @param  pData : The destination buffer address.
01945   * @param  Length : The length of data to be transferred from DFSDM filter to memory.
01946   * @retval HAL status
01947   */
01948 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
01949                                                     int32_t                    *pData,
01950                                                     uint32_t                    Length)
01951 {
01952   HAL_StatusTypeDef status = HAL_OK;
01953
01954   /* Check parameters */
01955   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01956
01957   /* Check destination address and length */
01958   if((pData == NULL) || (Length == 0))
01959   {
01960     status = HAL_ERROR;
01961   }
01962   /* Check that DMA is enabled for injected conversion */
01963   else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
01964   {
01965     status = HAL_ERROR;
01966   }
01967   /* Check parameters compatibility */
01968   else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
01969           (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
01970           (Length > hdfsdm_filter->InjConvRemaining))
01971   {
01972     status = HAL_ERROR;
01973   }
01974   else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
01975           (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
01976   {
01977     status = HAL_ERROR;
01978   }
01979   /* Check DFSDM filter state */
01980   else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
01981           (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
01982   {
01983     /* Set callbacks on DMA handler */
01984     hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
01985     hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
01986     hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
01987                                                    DFSDM_DMAInjectedHalfConvCplt : NULL;
01988
01989     /* Start DMA in interrupt mode */
01990     if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \
01991                         (uint32_t) pData, Length) != HAL_OK)
01992     {
01993       /* Set DFSDM filter in error state */
01994       hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
01995       status = HAL_ERROR;
01996     }
01997     else
01998     {
01999       /* Start injected conversion */
02000       DFSDM_InjConvStart(hdfsdm_filter);
02001     }
02002   }
02003   else
02004   {
02005     status = HAL_ERROR;
02006   }
02007   /* Return function status */
02008   return status;
02009 }
02010
02011 /**
02012   * @brief  This function allows to start injected conversion in DMA mode and to get
02013   *         only the 16 most significant bits of conversion.
02014   * @note   This function should be called only when DFSDM filter instance is
02015   *         in idle state or if regular conversion is ongoing.
02016   *         Please note that data on buffer will contain signed 16 most significant
02017   *         bits of injected conversion.
02018   * @param  hdfsdm_filter : DFSDM filter handle.
02019   * @param  pData : The destination buffer address.
02020   * @param  Length : The length of data to be transferred from DFSDM filter to memory.
02021   * @retval HAL status
02022   */
02023 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
02024                                                        int16_t                    *pData,
02025                                                        uint32_t                    Length)
02026 {
02027   HAL_StatusTypeDef status = HAL_OK;
02028
02029   /* Check parameters */
02030   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02031
02032   /* Check destination address and length */
02033   if((pData == NULL) || (Length == 0))
02034   {
02035     status = HAL_ERROR;
02036   }
02037   /* Check that DMA is enabled for injected conversion */
02038   else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
02039   {
02040     status = HAL_ERROR;
02041   }
02042   /* Check parameters compatibility */
02043   else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
02044           (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
02045           (Length > hdfsdm_filter->InjConvRemaining))
02046   {
02047     status = HAL_ERROR;
02048   }
02049   else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
02050           (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
02051   {
02052     status = HAL_ERROR;
02053   }
02054   /* Check DFSDM filter state */
02055   else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
02056           (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
02057   {
02058     /* Set callbacks on DMA handler */
02059     hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
02060     hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
02061     hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
02062                                                    DFSDM_DMAInjectedHalfConvCplt : NULL;
02063
02064     /* Start DMA in interrupt mode */
02065     if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2, \
02066                         (uint32_t) pData, Length) != HAL_OK)
02067     {
02068       /* Set DFSDM filter in error state */
02069       hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
02070       status = HAL_ERROR;
02071     }
02072     else
02073     {
02074       /* Start injected conversion */
02075       DFSDM_InjConvStart(hdfsdm_filter);
02076     }
02077   }
02078   else
02079   {
02080     status = HAL_ERROR;
02081   }
02082   /* Return function status */
02083   return status;
02084 }
02085
02086 /**
02087   * @brief  This function allows to stop injected conversion in DMA mode.
02088   * @note   This function should be called only if injected conversion is ongoing.
02089   * @param  hdfsdm_filter : DFSDM filter handle.
02090   * @retval HAL status
02091   */
02092 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02093 {
02094   HAL_StatusTypeDef status = HAL_OK;
02095
02096   /* Check parameters */
02097   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02098
02099   /* Check DFSDM filter state */
02100   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
02101      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
02102   {
02103     /* Return error status */
02104     status = HAL_ERROR;
02105   }
02106   else
02107   {
02108     /* Stop current DMA transfer */
02109     if(HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK)
02110     {
02111       /* Set DFSDM filter in error state */
02112       hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
02113       status = HAL_ERROR;
02114     }
02115     else
02116     {
02117       /* Stop regular conversion */
02118       DFSDM_InjConvStop(hdfsdm_filter);
02119     }
02120   }
02121   /* Return function status */
02122   return status;
02123 }
02124
02125 /**
02126   * @brief  This function allows to get injected conversion value.
02127   * @param  hdfsdm_filter : DFSDM filter handle.
02128   * @param  Channel : Corresponding channel of injected conversion.
02129   * @retval Injected conversion value
02130   */
02131 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
02132                                          uint32_t                   *Channel)
02133 {
02134   uint32_t reg = 0;
02135   int32_t  value = 0;
02136
02137   /* Check parameters */
02138   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02139   assert_param(Channel != NULL);
02140
02141   /* Get value of data register for injected channel */
02142   reg = hdfsdm_filter->Instance->FLTJDATAR;
02143
02144   /* Extract channel and injected conversion value */
02145   *Channel = (reg & DFSDM_FLTJDATAR_JDATACH);
02146   value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_DATA_OFFSET);
02147
02148   /* return regular conversion value */
02149   return value;
02150 }
02151
02152 /**
02153   * @brief  This function allows to start filter analog watchdog in interrupt mode.
02154   * @param  hdfsdm_filter : DFSDM filter handle.
02155   * @param  awdParam : DFSDM filter analog watchdog parameters.
02156   * @retval HAL status
02157   */
02158 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef   *hdfsdm_filter,
02159                                               DFSDM_Filter_AwdParamTypeDef *awdParam)
02160 {
02161   HAL_StatusTypeDef status = HAL_OK;
02162
02163   /* Check parameters */
02164   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02165   assert_param(IS_DFSDM_FILTER_AWD_DATA_SOURCE(awdParam->DataSource));
02166   assert_param(IS_DFSDM_INJECTED_CHANNEL(awdParam->Channel));
02167   assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->HighThreshold));
02168   assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold));
02169   assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal));
02170   assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal));
02171
02172   /* Check DFSDM filter state */
02173   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
02174      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
02175   {
02176     /* Return error status */
02177     status = HAL_ERROR;
02178   }
02179   else
02180   {
02181     /* Set analog watchdog data source */
02182     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
02183     hdfsdm_filter->Instance->FLTCR1 |= awdParam->DataSource;
02184
02185     /* Set thresholds and break signals */
02186     hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
02187     hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_THRESHOLD_OFFSET) | \
02188                                         awdParam->HighBreakSignal);
02189     hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
02190     hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_THRESHOLD_OFFSET) | \
02191                                         awdParam->LowBreakSignal);
02192
02193     /* Set channels and interrupt for analog watchdog */
02194     hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH);
02195     hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_OFFSET) | \
02196                                         DFSDM_FLTCR2_AWDIE);
02197   }
02198   /* Return function status */
02199   return status;
02200 }
02201
02202 /**
02203   * @brief  This function allows to stop filter analog watchdog in interrupt mode.
02204   * @param  hdfsdm_filter : DFSDM filter handle.
02205   * @retval HAL status
02206   */
02207 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02208 {
02209   HAL_StatusTypeDef status = HAL_OK;
02210
02211   /* Check parameters */
02212   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02213
02214   /* Check DFSDM filter state */
02215   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
02216      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
02217   {
02218     /* Return error status */
02219     status = HAL_ERROR;
02220   }
02221   else
02222   {
02223     /* Reset channels for analog watchdog and deactivate interrupt */
02224     hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH | DFSDM_FLTCR2_AWDIE);
02225
02226     /* Clear all analog watchdog flags */
02227     hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF);
02228
02229     /* Reset thresholds and break signals */
02230     hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
02231     hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
02232
02233     /* Reset analog watchdog data source */
02234     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
02235   }
02236   /* Return function status */
02237   return status;
02238 }
02239
02240 /**
02241   * @brief  This function allows to start extreme detector feature.
02242   * @param  hdfsdm_filter : DFSDM filter handle.
02243   * @param  Channel : Channels where extreme detector is enabled.
02244   *         This parameter can be a values combination of @ref DFSDM_Channel_Selection.
02245   * @retval HAL status
02246   */
02247 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
02248                                            uint32_t                    Channel)
02249 {
02250   HAL_StatusTypeDef status = HAL_OK;
02251
02252   /* Check parameters */
02253   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02254   assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
02255
02256   /* Check DFSDM filter state */
02257   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
02258      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
02259   {
02260     /* Return error status */
02261     status = HAL_ERROR;
02262   }
02263   else
02264   {
02265     /* Set channels for extreme detector */
02266     hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
02267     hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_OFFSET);
02268   }
02269   /* Return function status */
02270   return status;
02271 }
02272
02273 /**
02274   * @brief  This function allows to stop extreme detector feature.
02275   * @param  hdfsdm_filter : DFSDM filter handle.
02276   * @retval HAL status
02277   */
02278 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02279 {
02280   HAL_StatusTypeDef status = HAL_OK;
02281   __IO uint32_t     reg1;
02282   __IO uint32_t     reg2;
02283
02284   /* Check parameters */
02285   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02286
02287   /* Check DFSDM filter state */
02288   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
02289      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
02290   {
02291     /* Return error status */
02292     status = HAL_ERROR;
02293   }
02294   else
02295   {
02296     /* Reset channels for extreme detector */
02297     hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
02298
02299     /* Clear extreme detector values */
02300     reg1 = hdfsdm_filter->Instance->FLTEXMAX;
02301     reg2 = hdfsdm_filter->Instance->FLTEXMIN;
02302     UNUSED(reg1); /* To avoid GCC warning */
02303     UNUSED(reg2); /* To avoid GCC warning */
02304   }
02305   /* Return function status */
02306   return status;
02307 }
02308
02309 /**
02310   * @brief  This function allows to get extreme detector maximum value.
02311   * @param  hdfsdm_filter : DFSDM filter handle.
02312   * @param  Channel : Corresponding channel.
02313   * @retval Extreme detector maximum value
02314   *         This value is between Min_Data = -8388608 and Max_Data = 8388607.
02315   */
02316 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
02317                                        uint32_t                   *Channel)
02318 {
02319   uint32_t reg = 0;
02320   int32_t  value = 0;
02321
02322   /* Check parameters */
02323   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02324   assert_param(Channel != NULL);
02325
02326   /* Get value of extreme detector maximum register */
02327   reg = hdfsdm_filter->Instance->FLTEXMAX;
02328
02329   /* Extract channel and extreme detector maximum value */
02330   *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);
02331   value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_DATA_OFFSET);
02332
02333   /* return extreme detector maximum value */
02334   return value;
02335 }
02336
02337 /**
02338   * @brief  This function allows to get extreme detector minimum value.
02339   * @param  hdfsdm_filter : DFSDM filter handle.
02340   * @param  Channel : Corresponding channel.
02341   * @retval Extreme detector minimum value
02342   *         This value is between Min_Data = -8388608 and Max_Data = 8388607.
02343   */
02344 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
02345                                        uint32_t                   *Channel)
02346 {
02347   uint32_t reg = 0;
02348   int32_t  value = 0;
02349
02350   /* Check parameters */
02351   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02352   assert_param(Channel != NULL);
02353
02354   /* Get value of extreme detector minimum register */
02355   reg = hdfsdm_filter->Instance->FLTEXMIN;
02356
02357   /* Extract channel and extreme detector minimum value */
02358   *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);
02359   value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_DATA_OFFSET);
02360
02361   /* return extreme detector minimum value */
02362   return value;
02363 }
02364
02365 /**
02366   * @brief  This function allows to get conversion time value.
02367   * @param  hdfsdm_filter : DFSDM filter handle.
02368   * @retval Conversion time value
02369   * @note   To get time in second, this value has to be divided by DFSDM clock frequency.
02370   */
02371 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02372 {
02373   uint32_t reg = 0;
02374   uint32_t value = 0;
02375
02376   /* Check parameters */
02377   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02378
02379   /* Get value of conversion timer register */
02380   reg = hdfsdm_filter->Instance->FLTCNVTIMR;
02381
02382   /* Extract conversion time value */
02383   value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_DATA_OFFSET);
02384
02385   /* return extreme detector minimum value */
02386   return value;
02387 }
02388
02389 /**
02390   * @brief  This function handles the DFSDM interrupts.
02391   * @param  hdfsdm_filter : DFSDM filter handle.
02392   * @retval None
02393   */
02394 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02395 {
02396   /* Check if overrun occurs during regular conversion */
02397   if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) != 0) && \
02398      ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_ROVRIE) != 0))
02399   {
02400     /* Clear regular overrun flag */
02401     hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
02402
02403     /* Update error code */
02404     hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
02405
02406     /* Call error callback */
02407     HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
02408   }
02409   /* Check if overrun occurs during injected conversion */
02410   else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0) && \
02411           ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JOVRIE) != 0))
02412   {
02413     /* Clear injected overrun flag */
02414     hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
02415
02416     /* Update error code */
02417     hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
02418
02419     /* Call error callback */
02420     HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
02421   }
02422   /* Check if end of regular conversion */
02423   else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0) && \
02424           ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0))
02425   {
02426     /* Call regular conversion complete callback */
02427     HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
02428
02429     /* End of conversion if mode is not continuous and software trigger */
02430     if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
02431        (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
02432     {
02433       /* Disable interrupts for regular conversions */
02434       hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE);
02435
02436       /* Update DFSDM filter state */
02437       hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
02438                              HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
02439     }
02440   }
02441   /* Check if end of injected conversion */
02442   else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != 0) && \
02443           ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0))
02444   {
02445     /* Call injected conversion complete callback */
02446     HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
02447
02448     /* Update remaining injected conversions */
02449     hdfsdm_filter->InjConvRemaining--;
02450     if(hdfsdm_filter->InjConvRemaining == 0)
02451     {
02452       /* End of conversion if trigger is software */
02453       if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
02454       {
02455         /* Disable interrupts for injected conversions */
02456         hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE);
02457
02458         /* Update DFSDM filter state */
02459         hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
02460                                HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
02461       }
02462       /* end of injected sequence, reset the value */
02463       hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
02464                                          hdfsdm_filter->InjectedChannelsNbr : 1;
02465     }
02466   }
02467   /* Check if analog watchdog occurs */
02468   else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_AWDF) != 0) && \
02469           ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_AWDIE) != 0))
02470   {
02471     uint32_t reg = 0;
02472     uint32_t threshold = 0;
02473     uint32_t channel = 0;
02474
02475     /* Get channel and threshold */
02476     reg = hdfsdm_filter->Instance->FLTAWSR;
02477     threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD;
02478     if(threshold == DFSDM_AWD_HIGH_THRESHOLD)
02479     {
02480       reg = reg >> DFSDM_FLTAWSR_HIGH_OFFSET;
02481     }
02482     while((reg & 1) == 0)
02483     {
02484       channel++;
02485       reg = reg >> 1;
02486     }
02487     /* Clear analog watchdog flag */
02488     hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \
02489                                         (1 << (DFSDM_FLTAWSR_HIGH_OFFSET + channel)) : \
02490                                      (1 << channel);
02491
02492     /* Call analog watchdog callback */
02493     HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold);
02494   }
02495   /* Check if clock absence occurs */
02496   else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
02497          ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0) && \
02498          ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0))
02499   {
02500     uint32_t reg = 0;
02501     uint32_t channel = 0;
02502
02503     reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_OFFSET);
02504
02505     while(channel < DFSDM1_CHANNEL_NUMBER)
02506     {
02507       /* Check if flag is set and corresponding channel is enabled */
02508       if(((reg & 1) != 0) && (a_dfsdm1ChannelHandle[channel] != NULL))
02509       {
02510         /* Check clock absence has been enabled for this channel */
02511         if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0)
02512         {
02513           /* Clear clock absence flag */
02514           hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
02515
02516           /* Call clock absence callback */
02517           HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]);
02518         }
02519       }
02520       channel++;
02521       reg = reg >> 1;
02522     }
02523   }
02524   /* Check if short circuit detection occurs */
02525   else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
02526          ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0) && \
02527          ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0))
02528   {
02529     uint32_t reg = 0;
02530     uint32_t channel = 0;
02531
02532     /* Get channel */
02533     reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_OFFSET);
02534     while((reg & 1) == 0)
02535     {
02536       channel++;
02537       reg = reg >> 1;
02538     }
02539
02540     /* Clear short circuit detection flag */
02541     hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
02542
02543     /* Call short circuit detection callback */
02544     HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);
02545   }
02546 }
02547
02548 /**
02549   * @brief  Regular conversion complete callback.
02550   * @note   In interrupt mode, user has to read conversion value in this function
02551   *         using HAL_DFSDM_FilterGetRegularValue.
02552   * @param  hdfsdm_filter : DFSDM filter handle.
02553   * @retval None
02554   */
02555 __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02556 {
02557   /* Prevent unused argument(s) compilation warning */
02558   UNUSED(hdfsdm_filter);
02559
02560   /* NOTE : This function should not be modified, when the callback is needed,
02561             the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file.
02562    */
02563 }
02564
02565 /**
02566   * @brief  Half regular conversion complete callback.
02567   * @param  hdfsdm_filter : DFSDM filter handle.
02568   * @retval None
02569   */
02570 __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02571 {
02572   /* Prevent unused argument(s) compilation warning */
02573   UNUSED(hdfsdm_filter);
02574
02575   /* NOTE : This function should not be modified, when the callback is needed,
02576             the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file.
02577    */
02578 }
02579
02580 /**
02581   * @brief  Injected conversion complete callback.
02582   * @note   In interrupt mode, user has to read conversion value in this function
02583   *         using HAL_DFSDM_FilterGetInjectedValue.
02584   * @param  hdfsdm_filter : DFSDM filter handle.
02585   * @retval None
02586   */
02587 __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02588 {
02589   /* Prevent unused argument(s) compilation warning */
02590   UNUSED(hdfsdm_filter);
02591
02592   /* NOTE : This function should not be modified, when the callback is needed,
02593             the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file.
02594    */
02595 }
02596
02597 /**
02598   * @brief  Half injected conversion complete callback.
02599   * @param  hdfsdm_filter : DFSDM filter handle.
02600   * @retval None
02601   */
02602 __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02603 {
02604   /* Prevent unused argument(s) compilation warning */
02605   UNUSED(hdfsdm_filter);
02606
02607   /* NOTE : This function should not be modified, when the callback is needed,
02608             the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file.
02609    */
02610 }
02611
02612 /**
02613   * @brief  Filter analog watchdog callback.
02614   * @param  hdfsdm_filter : DFSDM filter handle.
02615   * @param  Channel : Corresponding channel.
02616   * @param  Threshold : Low or high threshold has been reached.
02617   * @retval None
02618   */
02619 __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
02620                                         uint32_t Channel, uint32_t Threshold)
02621 {
02622   /* Prevent unused argument(s) compilation warning */
02623   UNUSED(hdfsdm_filter);
02624   UNUSED(Channel);
02625   UNUSED(Threshold);
02626
02627   /* NOTE : This function should not be modified, when the callback is needed,
02628             the HAL_DFSDM_FilterAwdCallback could be implemented in the user file.
02629    */
02630 }
02631
02632 /**
02633   * @brief  Error callback.
02634   * @param  hdfsdm_filter : DFSDM filter handle.
02635   * @retval None
02636   */
02637 __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02638 {
02639   /* Prevent unused argument(s) compilation warning */
02640   UNUSED(hdfsdm_filter);
02641
02642   /* NOTE : This function should not be modified, when the callback is needed,
02643             the HAL_DFSDM_FilterErrorCallback could be implemented in the user file.
02644    */
02645 }
02646
02647 /**
02648   * @}
02649   */
02650
02651 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
02652  *  @brief    Filter state functions
02653  *
02654 @verbatim
02655   ==============================================================================
02656                      ##### Filter state functions #####
02657   ==============================================================================
02658     [..]  This section provides functions allowing to:
02659       (+) Get the DFSDM filter state.
02660       (+) Get the DFSDM filter error.
02661 @endverbatim
02662   * @{
02663   */
02664
02665 /**
02666   * @brief  This function allows to get the current DFSDM filter handle state.
02667   * @param  hdfsdm_filter : DFSDM filter handle.
02668   * @retval DFSDM filter state.
02669   */
02670 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02671 {
02672   /* Return DFSDM filter handle state */
02673   return hdfsdm_filter->State;
02674 }
02675
02676 /**
02677   * @brief  This function allows to get the current DFSDM filter error.
02678   * @param  hdfsdm_filter : DFSDM filter handle.
02679   * @retval DFSDM filter error code.
02680   */
02681 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02682 {
02683   return hdfsdm_filter->ErrorCode;
02684 }
02685
02686 /**
02687   * @}
02688   */
02689
02690 /**
02691   * @}
02692   */
02693 /* End of exported functions -------------------------------------------------*/
02694
02695 /* Private functions ---------------------------------------------------------*/
02696 /** @addtogroup DFSDM_Private_Functions DFSDM Private Functions
02697   * @{
02698   */
02699
02700 /**
02701   * @brief  DMA half transfer complete callback for regular conversion.
02702   * @param  hdma : DMA handle.
02703   * @retval None
02704   */
02705 static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
02706 {
02707   /* Get DFSDM filter handle */
02708   DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
02709
02710   /* Call regular half conversion complete callback */
02711   HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter);
02712 }
02713
02714 /**
02715   * @brief  DMA transfer complete callback for regular conversion.
02716   * @param  hdma : DMA handle.
02717   * @retval None
02718   */
02719 static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
02720 {
02721   /* Get DFSDM filter handle */
02722   DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
02723
02724   /* Call regular conversion complete callback */
02725   HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
02726 }
02727
02728 /**
02729   * @brief  DMA half transfer complete callback for injected conversion.
02730   * @param  hdma : DMA handle.
02731   * @retval None
02732   */
02733 static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
02734 {
02735   /* Get DFSDM filter handle */
02736   DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
02737
02738   /* Call injected half conversion complete callback */
02739   HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter);
02740 }
02741
02742 /**
02743   * @brief  DMA transfer complete callback for injected conversion.
02744   * @param  hdma : DMA handle.
02745   * @retval None
02746   */
02747 static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
02748 {
02749   /* Get DFSDM filter handle */
02750   DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
02751
02752   /* Call injected conversion complete callback */
02753   HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
02754 }
02755
02756 /**
02757   * @brief  DMA error callback.
02758   * @param  hdma : DMA handle.
02759   * @retval None
02760   */
02761 static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
02762 {
02763   /* Get DFSDM filter handle */
02764   DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
02765
02766   /* Update error code */
02767   hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA;
02768
02769   /* Call error callback */
02770   HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
02771 }
02772
02773 /**
02774   * @brief  This function allows to get the number of injected channels.
02775   * @param  Channels : bitfield of injected channels.
02776   * @retval Number of injected channels.
02777   */
02778 static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)
02779 {
02780   uint32_t nbChannels = 0;
02781   uint32_t tmp;
02782
02783   /* Get the number of channels from bitfield */
02784   tmp = (uint32_t) (Channels & DFSDM_LSB_MASK);
02785   while(tmp != 0)
02786   {
02787     if((tmp & 1) != 0)
02788     {
02789       nbChannels++;
02790     }
02791     tmp = (uint32_t) (tmp >> 1);
02792   }
02793   return nbChannels;
02794 }
02795
02796 /**
02797   * @brief  This function allows to get the channel number from channel instance.
02798   * @param  Instance : DFSDM channel instance.
02799   * @retval Channel number.
02800   */
02801 static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)
02802 {
02803   uint32_t channel = 0xFF;
02804
02805   /* Get channel from instance */
02806   if(Instance == DFSDM1_Channel0)
02807   {
02808     channel = 0;
02809   }
02810   else if(Instance == DFSDM1_Channel1)
02811   {
02812     channel = 1;
02813   }
02814   else if(Instance == DFSDM1_Channel2)
02815   {
02816     channel = 2;
02817   }
02818   else if(Instance == DFSDM1_Channel3)
02819   {
02820     channel = 3;
02821   }
02822   else if(Instance == DFSDM1_Channel4)
02823   {
02824     channel = 4;
02825   }
02826   else if(Instance == DFSDM1_Channel5)
02827   {
02828     channel = 5;
02829   }
02830   else if(Instance == DFSDM1_Channel6)
02831   {
02832     channel = 6;
02833   }
02834   else if(Instance == DFSDM1_Channel7)
02835   {
02836     channel = 7;
02837   }
02838
02839   return channel;
02840 }
02841
02842 /**
02843   * @brief  This function allows to really start regular conversion.
02844   * @param  hdfsdm_filter : DFSDM filter handle.
02845   * @retval None
02846   */
02847 static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
02848 {
02849   /* Check regular trigger */
02850   if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)
02851   {
02852     /* Software start of regular conversion */
02853     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
02854   }
02855   else /* synchronous trigger */
02856   {
02857     /* Disable DFSDM filter */
02858     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
02859
02860     /* Set RSYNC bit in DFSDM_FLTCR1 register */
02861     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
02862
02863     /* Enable DFSDM  filter */
02864     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
02865
02866     /* If injected conversion was in progress, restart it */
02867     if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)
02868     {
02869       if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
02870       {
02871         hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
02872       }
02873       /* Update remaining injected conversions */
02874       hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
02875                                          hdfsdm_filter->InjectedChannelsNbr : 1;
02876     }
02877   }
02878   /* Update DFSDM filter state */
02879   hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
02880                           HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ;
02881 }
02882
02883 /**
02884   * @brief  This function allows to really stop regular conversion.
02885   * @param  hdfsdm_filter : DFSDM filter handle.
02886   * @retval None
02887   */
02888 static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
02889 {
02890   /* Disable DFSDM filter */
02891   hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
02892
02893   /* If regular trigger was synchronous, reset RSYNC bit in DFSDM_FLTCR1 register */
02894   if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER)
02895   {
02896     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
02897   }
02898
02899   /* Enable DFSDM filter */
02900   hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
02901
02902   /* If injected conversion was in progress, restart it */
02903   if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ)
02904   {
02905     if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
02906     {
02907       hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
02908     }
02909     /* Update remaining injected conversions */
02910     hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
02911                                        hdfsdm_filter->InjectedChannelsNbr : 1;
02912   }
02913
02914   /* Update DFSDM filter state */
02915   hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
02916                           HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
02917 }
02918
02919 /**
02920   * @brief  This function allows to really start injected conversion.
02921   * @param  hdfsdm_filter : DFSDM filter handle.
02922   * @retval None
02923   */
02924 static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
02925 {
02926   /* Check injected trigger */
02927   if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
02928   {
02929     /* Software start of injected conversion */
02930     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
02931   }
02932   else /* external or synchronous trigger */
02933   {
02934     /* Disable DFSDM filter */
02935     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
02936
02937     if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
02938     {
02939       /* Set JSYNC bit in DFSDM_FLTCR1 register */
02940       hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC;
02941     }
02942     else /* external trigger */
02943     {
02944       /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
02945       hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge;
02946     }
02947
02948     /* Enable DFSDM filter */
02949     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
02950
02951     /* If regular conversion was in progress, restart it */
02952     if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \
02953        (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
02954     {
02955       hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
02956     }
02957   }
02958   /* Update DFSDM filter state */
02959   hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
02960                          HAL_DFSDM_FILTER_STATE_INJ : HAL_DFSDM_FILTER_STATE_REG_INJ;
02961 }
02962
02963 /**
02964   * @brief  This function allows to really stop injected conversion.
02965   * @param  hdfsdm_filter : DFSDM filter handle.
02966   * @retval None
02967   */
02968 static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
02969 {
02970   /* Disable DFSDM filter */
02971   hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
02972
02973   /* If injected trigger was synchronous, reset JSYNC bit in DFSDM_FLTCR1 register */
02974   if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
02975   {
02976     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC);
02977   }
02978   else if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER)
02979   {
02980     /* Reset JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
02981     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN);
02982   }
02983
02984   /* Enable DFSDM filter */
02985   hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
02986
02987   /* If regular conversion was in progress, restart it */
02988   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \
02989      (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
02990   {
02991     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
02992   }
02993
02994   /* Update remaining injected conversions */
02995   hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
02996                                      hdfsdm_filter->InjectedChannelsNbr : 1;
02997
02998   /* Update DFSDM filter state */
02999   hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
03000                           HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
03001 }
03002
03003 /**
03004   * @}
03005   */
03006 /* End of private functions --------------------------------------------------*/
03007
03008 /**
03009   * @}
03010   */
03011 #endif /* HAL_DFSDM_MODULE_ENABLED */
03012 /**
03013   * @}
03014   */
03015
03016 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dfsdm.h Source File

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stm32h7xx_hal_dfsdm.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dfsdm.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of DFSDM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_DFSDM_H
00040 #define __STM32H7xx_HAL_DFSDM_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup DFSDM
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup DFSDM_Exported_Types DFSDM Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  HAL DFSDM Channel states definition
00064   */
00065 typedef enum
00066 {
00067   HAL_DFSDM_CHANNEL_STATE_RESET = 0x00, /*!< DFSDM channel not initialized */
00068   HAL_DFSDM_CHANNEL_STATE_READY = 0x01, /*!< DFSDM channel initialized and ready for use */
00069   HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFF  /*!< DFSDM channel state error */
00070 }HAL_DFSDM_Channel_StateTypeDef;
00071
00072 /**
00073   * @brief  DFSDM channel output clock structure definition
00074   */
00075 typedef struct
00076 {
00077   FunctionalState Activation; /*!< Output clock enable/disable */
00078   uint32_t        Selection;  /*!< Output clock is system clock or audio clock.
00079                                    This parameter can be a value of @ref DFSDM_Channel_OuputClock */
00080   uint32_t        Divider;    /*!< Output clock divider.
00081                                    This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
00082 }DFSDM_Channel_OutputClockTypeDef;
00083
00084 /**
00085   * @brief  DFSDM channel input structure definition
00086   */
00087 typedef struct
00088 {
00089   uint32_t Multiplexer; /*!< Input is external serial inputs ,internal register or ADC output.
00090                              This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
00091   uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
00092                              This parameter can be a value of @ref DFSDM_Channel_DataPacking */
00093   uint32_t Pins;        /*!< Input pins are taken from same or following channel.
00094                              This parameter can be a value of @ref DFSDM_Channel_InputPins */
00095 }DFSDM_Channel_InputTypeDef;
00096
00097 /**
00098   * @brief  DFSDM channel serial interface structure definition
00099   */
00100 typedef struct
00101 {
00102   uint32_t Type;     /*!< SPI or Manchester modes.
00103                           This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
00104   uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
00105                           This parameter can be a value of @ref DFSDM_Channel_SpiClock */
00106 }DFSDM_Channel_SerialInterfaceTypeDef;
00107
00108 /**
00109   * @brief  DFSDM channel analog watchdog structure definition
00110   */
00111 typedef struct
00112 {
00113   uint32_t FilterOrder;  /*!< Analog watchdog Sinc filter order.
00114                               This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
00115   uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
00116                               This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
00117 }DFSDM_Channel_AwdTypeDef;
00118
00119 /**
00120   * @brief  DFSDM channel init structure definition
00121   */
00122 typedef struct
00123 {
00124   DFSDM_Channel_OutputClockTypeDef     OutputClock;     /*!< DFSDM channel output clock parameters */
00125   DFSDM_Channel_InputTypeDef           Input;           /*!< DFSDM channel input parameters */
00126   DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */
00127   DFSDM_Channel_AwdTypeDef             Awd;             /*!< DFSDM channel analog watchdog parameters */
00128   int32_t                              Offset;          /*!< DFSDM channel offset.
00129                                                              This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
00130   uint32_t                             RightBitShift;   /*!< DFSDM channel right bit shift.
00131                                                              This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
00132 }DFSDM_Channel_InitTypeDef;
00133
00134 /**
00135   * @brief  DFSDM channel handle structure definition
00136   */
00137 typedef struct
00138 {
00139   DFSDM_Channel_TypeDef          *Instance; /*!< DFSDM channel instance */
00140   DFSDM_Channel_InitTypeDef      Init;      /*!< DFSDM channel init parameters */
00141   HAL_DFSDM_Channel_StateTypeDef State;     /*!< DFSDM channel state */
00142 }DFSDM_Channel_HandleTypeDef;
00143
00144 /**
00145   * @brief  HAL DFSDM Filter states definition
00146   */
00147 typedef enum
00148 {
00149   HAL_DFSDM_FILTER_STATE_RESET   = 0x00, /*!< DFSDM filter not initialized */
00150   HAL_DFSDM_FILTER_STATE_READY   = 0x01, /*!< DFSDM filter initialized and ready for use */
00151   HAL_DFSDM_FILTER_STATE_REG     = 0x02, /*!< DFSDM filter regular conversion in progress */
00152   HAL_DFSDM_FILTER_STATE_INJ     = 0x03, /*!< DFSDM filter injected conversion in progress */
00153   HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04, /*!< DFSDM filter regular and injected conversions in progress */
00154   HAL_DFSDM_FILTER_STATE_ERROR   = 0xFF  /*!< DFSDM filter state error */
00155 }HAL_DFSDM_Filter_StateTypeDef;
00156
00157 /**
00158   * @brief  DFSDM filter regular conversion parameters structure definition
00159   */
00160 typedef struct
00161 {
00162   uint32_t        Trigger;  /*!< Trigger used to start regular conversion: software or synchronous.
00163                                  This parameter can be a value of @ref DFSDM_Filter_Trigger */
00164   FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */
00165   FunctionalState DmaMode;  /*!< Enable/disable DMA for regular conversion */
00166 }DFSDM_Filter_RegularParamTypeDef;
00167
00168 /**
00169   * @brief  DFSDM filter injected conversion parameters structure definition
00170   */
00171 typedef struct
00172 {
00173   uint32_t        Trigger;        /*!< Trigger used to start injected conversion: software, external or synchronous.
00174                                        This parameter can be a value of @ref DFSDM_Filter_Trigger */
00175   FunctionalState ScanMode;       /*!< Enable/disable scanning mode for injected conversion */
00176   FunctionalState DmaMode;        /*!< Enable/disable DMA for injected conversion */
00177   uint32_t        ExtTrigger;     /*!< External trigger.
00178                                        This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
00179   uint32_t        ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
00180                                        This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
00181 }DFSDM_Filter_InjectedParamTypeDef;
00182
00183 /**
00184   * @brief  DFSDM filter parameters structure definition
00185   */
00186 typedef struct
00187 {
00188   uint32_t SincOrder;       /*!< Sinc filter order.
00189                                  This parameter can be a value of @ref DFSDM_Filter_SincOrder */
00190   uint32_t Oversampling;    /*!< Filter oversampling ratio.
00191                                  This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
00192   uint32_t IntOversampling; /*!< Integrator oversampling ratio.
00193                                  This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
00194 }DFSDM_Filter_FilterParamTypeDef;
00195
00196 /**
00197   * @brief  DFSDM filter init structure definition
00198   */
00199 typedef struct
00200 {
00201   DFSDM_Filter_RegularParamTypeDef  RegularParam;  /*!< DFSDM regular conversion parameters */
00202   DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */
00203   DFSDM_Filter_FilterParamTypeDef   FilterParam;   /*!< DFSDM filter parameters */
00204 }DFSDM_Filter_InitTypeDef;
00205
00206 /**
00207   * @brief  DFSDM filter handle structure definition
00208   */
00209 typedef struct
00210 {
00211   DFSDM_Filter_TypeDef          *Instance;           /*!< DFSDM filter instance */
00212   DFSDM_Filter_InitTypeDef      Init;                /*!< DFSDM filter init parameters */
00213   DMA_HandleTypeDef             *hdmaReg;            /*!< Pointer on DMA handler for regular conversions */
00214   DMA_HandleTypeDef             *hdmaInj;            /*!< Pointer on DMA handler for injected conversions */
00215   uint32_t                      RegularContMode;     /*!< Regular conversion continuous mode */
00216   uint32_t                      RegularTrigger;      /*!< Trigger used for regular conversion */
00217   uint32_t                      InjectedTrigger;     /*!< Trigger used for injected conversion */
00218   uint32_t                      ExtTriggerEdge;      /*!< Rising, falling or both edges selected */
00219   FunctionalState               InjectedScanMode;    /*!< Injected scanning mode */
00220   uint32_t                      InjectedChannelsNbr; /*!< Number of channels in injected sequence */
00221   uint32_t                      InjConvRemaining;    /*!< Injected conversions remaining */
00222   HAL_DFSDM_Filter_StateTypeDef State;               /*!< DFSDM filter state */
00223   uint32_t                      ErrorCode;           /*!< DFSDM filter error code */
00224 }DFSDM_Filter_HandleTypeDef;
00225
00226 /**
00227   * @brief  DFSDM filter analog watchdog parameters structure definition
00228   */
00229 typedef struct
00230 {
00231   uint32_t DataSource;      /*!< Values from digital filter or from channel watchdog filter.
00232                                  This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */
00233   uint32_t Channel;         /*!< Analog watchdog channel selection.
00234                                  This parameter can be a values combination of @ref DFSDM_Channel_Selection */
00235   int32_t  HighThreshold;   /*!< High threshold for the analog watchdog.
00236                                  This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
00237   int32_t  LowThreshold;    /*!< Low threshold for the analog watchdog.
00238                                  This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
00239   uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.
00240                                  This parameter can be a values combination of @ref DFSDM_BreakSignals */
00241   uint32_t LowBreakSignal;  /*!< Break signal assigned to analog watchdog low threshold event.
00242                                  This parameter can be a values combination of @ref DFSDM_BreakSignals */
00243 }DFSDM_Filter_AwdParamTypeDef;
00244
00245 /**
00246   * @}
00247   */
00248 /* End of exported types -----------------------------------------------------*/
00249
00250 /* Exported constants --------------------------------------------------------*/
00251 /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants
00252   * @{
00253   */
00254
00255 /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
00256   * @{
00257   */
00258 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM    ((uint32_t)0x00000000) /*!< Source for ouput clock is system clock */
00259 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO     DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
00265   * @{
00266   */
00267 #define DFSDM_CHANNEL_EXTERNAL_INPUTS    ((uint32_t)0x00000000)  /*!< Data are taken from external inputs */
00268 #define DFSDM_CHANNEL_ADC_OUTPUT         DFSDM_CHCFGR1_DATMPX_0  /*!< Data are taken from ADC output */
00269 #define DFSDM_CHANNEL_INTERNAL_REGISTER  DFSDM_CHCFGR1_DATMPX_1  /*!< Data are taken from internal register */
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
00275   * @{
00276   */
00277 #define DFSDM_CHANNEL_STANDARD_MODE         ((uint32_t)0x00000000)  /*!< Standard data packing mode */
00278 #define DFSDM_CHANNEL_INTERLEAVED_MODE      DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */
00279 #define DFSDM_CHANNEL_DUAL_MODE             DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
00285   * @{
00286   */
00287 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS      ((uint32_t)0x00000000) /*!< Input from pins on same channel */
00288 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL  /*!< Input from pins on following channel */
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
00294   * @{
00295   */
00296 #define DFSDM_CHANNEL_SPI_RISING         ((uint32_t)0x00000000) /*!< SPI with rising edge */
00297 #define DFSDM_CHANNEL_SPI_FALLING        DFSDM_CHCFGR1_SITP_0   /*!< SPI with falling edge */
00298 #define DFSDM_CHANNEL_MANCHESTER_RISING  DFSDM_CHCFGR1_SITP_1   /*!< Manchester with rising edge */
00299 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP     /*!< Manchester with falling edge */
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
00305   * @{
00306   */
00307 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL              ((uint32_t)0x00000000)   /*!< External SPI clock */
00308 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL              DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */
00309 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */
00310 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING  DFSDM_CHCFGR1_SPICKSEL   /*!< Internal SPI clock divided by 2, rising edge */
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
00316   * @{
00317   */
00318 #define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000) /*!< FastSinc filter type */
00319 #define DFSDM_CHANNEL_SINC1_ORDER    DFSDM_CHAWSCDR_AWFORD_0  /*!< Sinc 1 filter type */
00320 #define DFSDM_CHANNEL_SINC2_ORDER    DFSDM_CHAWSCDR_AWFORD_1  /*!< Sinc 2 filter type */
00321 #define DFSDM_CHANNEL_SINC3_ORDER    DFSDM_CHAWSCDR_AWFORD    /*!< Sinc 3 filter type */
00322 /**
00323   * @}
00324   */
00325
00326 /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
00327   * @{
00328   */
00329 #define DFSDM_FILTER_SW_TRIGGER   ((uint32_t)0x00000000) /*!< Software trigger */
00330 #define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001) /*!< Synchronous with DFSDM0 */
00331 #define DFSDM_FILTER_EXT_TRIGGER  ((uint32_t)0x00000002) /*!< External trigger (only for injected conversion) */
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
00337   * @{
00338   */
00339 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  ((uint32_t)0x00000000)                      /*!< For DFSDM 0, 1, 2 and 3 */
00340 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0                         /*!< For DFSDM 0, 1, 2 and 3 */
00341 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO  DFSDM_FLTCR1_JEXTSEL_1                         /*!< For DFSDM 0, 1, 2 and 3 */
00342 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM 0, 1 and 2 */
00343 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  DFSDM_FLTCR1_JEXTSEL_2                        /*!< For DFSDM 3 */
00344 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)                         /*!< For DFSDM 0, 1 and 2 */
00345 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1  (DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)                        /*!< For DFSDM 3 */
00346 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM 0 and 1 */
00347 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO  DFSDM_FLTCR1_JEXTSEL_3 /*!< For DFSDM 2 and 3 */
00348 #define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1  (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)
00349 #define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3  (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)
00350 #define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3) /*!< For DFSDM 0, 1, 2 and 3 */
00351 #define DFSDM_FILTER_EXT_TRIG_EXTI15     (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)                           /*!< For DFSDM 0, 1, 2 and 3 */
00352 #define DFSDM_FILTER_EXT_TRIG_LPTIM1     (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)                           /*!< For DFSDM 0, 1, 2 and 3 */
00353 #define DFSDM_FILTER_EXT_TRIG_LPTIM2     (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_0)  /*!< For DFSDM 0, 1, 2 and 3 */
00354 #define DFSDM_FILTER_EXT_TRIG_LPTIM3     (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2)                           /*!< For DFSDM 0, 1, 2 and 3 */
00355 /**
00356   * @}
00357   */
00358
00359 /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
00360   * @{
00361   */
00362 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE  DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */
00363 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */
00364 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES   DFSDM_FLTCR1_JEXTEN   /*!< External rising and falling edges */
00365 /**
00366   * @}
00367   */
00368
00369 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
00370   * @{
00371   */
00372 #define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000)                   /*!< FastSinc filter type */
00373 #define DFSDM_FILTER_SINC1_ORDER    DFSDM_FLTFCR_FORD_0                      /*!< Sinc 1 filter type */
00374 #define DFSDM_FILTER_SINC2_ORDER    DFSDM_FLTFCR_FORD_1                      /*!< Sinc 2 filter type */
00375 #define DFSDM_FILTER_SINC3_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
00376 #define DFSDM_FILTER_SINC4_ORDER    DFSDM_FLTFCR_FORD_2                      /*!< Sinc 4 filter type */
00377 #define DFSDM_FILTER_SINC5_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */
00378 /**
00379   * @}
00380   */
00381
00382 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
00383   * @{
00384   */
00385 #define DFSDM_FILTER_AWD_FILTER_DATA  ((uint32_t)0x00000000)    /*!< From digital filter */
00386 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL       /*!< From analog watchdog channel */
00387 /**
00388   * @}
00389   */
00390
00391 /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
00392   * @{
00393   */
00394 #define DFSDM_FILTER_ERROR_NONE             ((uint32_t)0x00000000) /*!< No error */
00395 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN  ((uint32_t)0x00000001) /*!< Overrun occurs during regular conversion */
00396 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002) /*!< Overrun occurs during injected conversion */
00397 #define DFSDM_FILTER_ERROR_DMA              ((uint32_t)0x00000003) /*!< DMA error occurs */
00398 /**
00399   * @}
00400   */
00401
00402 /** @defgroup DFSDM_BreakSignals DFSDM break signals
00403   * @{
00404   */
00405 #define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000) /*!< No break signal */
00406 #define DFSDM_BREAK_SIGNAL_0  ((uint32_t)0x00000001) /*!< Break signal 0 */
00407 #define DFSDM_BREAK_SIGNAL_1  ((uint32_t)0x00000002) /*!< Break signal 1 */
00408 #define DFSDM_BREAK_SIGNAL_2  ((uint32_t)0x00000004) /*!< Break signal 2 */
00409 #define DFSDM_BREAK_SIGNAL_3  ((uint32_t)0x00000008) /*!< Break signal 3 */
00410 /**
00411   * @}
00412   */
00413
00414 /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection
00415   * @{
00416   */
00417 /* DFSDM Channels ------------------------------------------------------------*/
00418 /* The DFSDM channels are defined as follows:
00419    - in 16-bit LSB the channel mask is set
00420    - in 16-bit MSB the channel number is set
00421    e.g. for channel 5 definition:
00422         - the channel mask is 0x00000020 (bit 5 is set)
00423         - the channel number 5 is 0x00050000
00424         --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
00425 #define DFSDM_CHANNEL_0                              ((uint32_t)0x00000001)
00426 #define DFSDM_CHANNEL_1                              ((uint32_t)0x00010002)
00427 #define DFSDM_CHANNEL_2                              ((uint32_t)0x00020004)
00428 #define DFSDM_CHANNEL_3                              ((uint32_t)0x00030008)
00429 #define DFSDM_CHANNEL_4                              ((uint32_t)0x00040010)
00430 #define DFSDM_CHANNEL_5                              ((uint32_t)0x00050020)
00431 #define DFSDM_CHANNEL_6                              ((uint32_t)0x00060040)
00432 #define DFSDM_CHANNEL_7                              ((uint32_t)0x00070080)
00433 /**
00434   * @}
00435   */
00436
00437 /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
00438   * @{
00439   */
00440 #define DFSDM_CONTINUOUS_CONV_OFF            ((uint32_t)0x00000000) /*!< Conversion are not continuous */
00441 #define DFSDM_CONTINUOUS_CONV_ON             ((uint32_t)0x00000001) /*!< Conversion are continuous */
00442 /**
00443   * @}
00444   */
00445
00446 /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
00447   * @{
00448   */
00449 #define DFSDM_AWD_HIGH_THRESHOLD            ((uint32_t)0x00000000) /*!< Analog watchdog high threshold */
00450 #define DFSDM_AWD_LOW_THRESHOLD             ((uint32_t)0x00000001) /*!< Analog watchdog low threshold */
00451 /**
00452   * @}
00453   */
00454
00455 /**
00456   * @}
00457   */
00458 /* End of exported constants -------------------------------------------------*/
00459
00460 /* Exported macros -----------------------------------------------------------*/
00461 /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
00462  * @{
00463  */
00464
00465 /** @brief  Reset DFSDM channel handle state.
00466   * @param  __HANDLE__: DFSDM channel handle.
00467   * @retval None
00468   */
00469 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
00470
00471 /** @brief  Reset DFSDM filter handle state.
00472   * @param  __HANDLE__: DFSDM filter handle.
00473   * @retval None
00474   */
00475 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
00476
00477 /**
00478   * @}
00479   */
00480 /* End of exported macros -----------------------------------------------------------*/
00481
00482 /* Exported functions --------------------------------------------------------*/
00483 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
00484   * @{
00485   */
00486
00487 /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
00488   * @{
00489   */
00490 /* Channel initialization and de-initialization functions *********************/
00491 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00492 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00493 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00494 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00495 /**
00496   * @}
00497   */
00498
00499 /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
00500   * @{
00501   */
00502 /* Channel operation functions ************************************************/
00503 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00504 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00505 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00506 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00507
00508 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
00509 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
00510 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00511 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00512
00513 int16_t           HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00514 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
00515
00516 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
00517 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
00518
00519 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00520 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00521 /**
00522   * @}
00523   */
00524
00525 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
00526   * @{
00527   */
00528 /* Channel state function *****************************************************/
00529 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00530 /**
00531   * @}
00532   */
00533
00534 /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
00535   * @{
00536   */
00537 /* Filter initialization and de-initialization functions *********************/
00538 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00539 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00540 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00541 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00542 /**
00543   * @}
00544   */
00545
00546 /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
00547   * @{
00548   */
00549 /* Filter control functions *********************/
00550 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
00551                                                    uint32_t                    Channel,
00552                                                    uint32_t                    ContinuousMode);
00553 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
00554                                                    uint32_t                    Channel);
00555 /**
00556   * @}
00557   */
00558
00559 /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
00560   * @{
00561   */
00562 /* Filter operation functions *********************/
00563 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00564 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00565 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
00566 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
00567 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00568 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00569 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00570 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00571 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00572 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
00573 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
00574 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00575 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00576 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00577 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
00578                                               DFSDM_Filter_AwdParamTypeDef* awdParam);
00579 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00580 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
00581 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00582
00583 int32_t  HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
00584 int32_t  HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
00585 int32_t  HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
00586 int32_t  HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
00587 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00588
00589 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00590
00591 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
00592 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
00593
00594 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00595 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00596 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00597 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00598 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
00599 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00600 /**
00601   * @}
00602   */
00603
00604 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
00605   * @{
00606   */
00607 /* Filter state functions *****************************************************/
00608 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00609 uint32_t                      HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00610 /**
00611   * @}
00612   */
00613
00614 /**
00615   * @}
00616   */
00617 /* End of exported functions -------------------------------------------------*/
00618
00619 /* Private macros ------------------------------------------------------------*/
00620 /** @defgroup DFSDM_Private_Macros DFSDM Private Macros
00621 * @{
00622 */
00623 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK)          (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
00624                                                        ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
00625 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))
00626 #define IS_DFSDM_CHANNEL_INPUT(INPUT)                 (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
00627                                                        ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \
00628                                                        ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
00629 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE)           (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
00630                                                        ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
00631                                                        ((MODE) == DFSDM_CHANNEL_DUAL_MODE))
00632 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS)             (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
00633                                                        ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
00634 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE)  (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
00635                                                        ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
00636                                                        ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
00637                                                        ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
00638 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE)              (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
00639                                                        ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
00640                                                        ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
00641                                                        ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
00642 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER)          (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
00643                                                        ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
00644                                                        ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
00645                                                        ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
00646 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO)       ((1 <= (RATIO)) && ((RATIO) <= 32))
00647 #define IS_DFSDM_CHANNEL_OFFSET(VALUE)                 ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
00648 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE)        ((VALUE) <= 0x1F)
00649 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE)          ((VALUE) <= 0xFF)
00650 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
00651                                                        ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
00652 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
00653                                                        ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
00654                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
00655 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
00656                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
00657                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
00658                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \
00659                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
00660                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
00661                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
00662                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
00663                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
00664                                                                                                              ((TRIG) == DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1) || \
00665                                                                                                              ((TRIG) == DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3) || \
00666                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
00667                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \
00668                                                                                                              ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1) || \
00669                                                                                                              ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM2) || \
00670                                                                                                              ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3))
00671 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)           (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE)  || \
00672                                                        ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE)  || \
00673                                                        ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
00674 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER)             (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
00675                                                        ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
00676                                                        ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
00677                                                        ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
00678                                                        ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
00679                                                        ((ORDER) == DFSDM_FILTER_SINC5_ORDER))
00680 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO)               ((1 <= (RATIO)) && ((RATIO) <= 1024))
00681 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO)    ((1 <= (RATIO)) && ((RATIO) <= 256))
00682 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA)         (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA)  || \
00683                                                        ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
00684 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE)           ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
00685 #define IS_DFSDM_BREAK_SIGNALS(VALUE)                  ((VALUE) <= 0xF)
00686 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL)             (((CHANNEL) == DFSDM_CHANNEL_0)  || \
00687                                                        ((CHANNEL) == DFSDM_CHANNEL_1)  || \
00688                                                        ((CHANNEL) == DFSDM_CHANNEL_2)  || \
00689                                                        ((CHANNEL) == DFSDM_CHANNEL_3)  || \
00690                                                        ((CHANNEL) == DFSDM_CHANNEL_4)  || \
00691                                                        ((CHANNEL) == DFSDM_CHANNEL_5)  || \
00692                                                        ((CHANNEL) == DFSDM_CHANNEL_6)  || \
00693                                                        ((CHANNEL) == DFSDM_CHANNEL_7))
00694 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FF))
00695 #define IS_DFSDM_CONTINUOUS_MODE(MODE)                (((MODE) == DFSDM_CONTINUOUS_CONV_OFF)  || \
00696                                                        ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
00697 /**
00698 * @}
00699 */
00700 /* End of private macros ------------------------------------------------------------*/
00701
00702 /**
00703   * @}
00704   */
00705
00706 /**
00707   * @}
00708   */
00709
00710 #ifdef __cplusplus
00711 }
00712 #endif
00713
00714 #endif /* __STM32H7xx_HAL_DFSDM_H */
00715
00716 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dma2d.c Source File

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stm32h7xx_hal_dma2d.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dma2d.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   DMA2D HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the DMA2D peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Errors functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020       (#) Program the required configuration through the following parameters:
00021           the transfer mode, the output color mode and the output offset using
00022           HAL_DMA2D_Init() function.
00023
00024       (#) Program the required configuration through the following parameters:
00025           the input color mode, the input color, the input alpha value, the alpha mode,
00026           the red/blue swap mode, the inverted alpha mode and the input offset using
00027           HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.
00028
00029      *** Polling mode IO operation ***
00030      =================================
00031     [..]
00032        (#) Configure pdata parameter (explained hereafter), destination and data length
00033            and enable the transfer using HAL_DMA2D_Start().
00034        (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
00035            user can specify the value of timeout according to his end application.
00036
00037      *** Interrupt mode IO operation ***
00038      ===================================
00039      [..]
00040        (#) Configure pdata parameter, destination and data length and enable
00041            the transfer using HAL_DMA2D_Start_IT().
00042        (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
00043        (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
00044            add his own function by customization of function pointer XferCpltCallback (member
00045            of DMA2D handle structure).
00046        (#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback
00047            XferErrorCallback.
00048
00049          -@-   In Register-to-Memory transfer mode, pdata parameter is the register
00050                color, in Memory-to-memory or Memory-to-Memory with pixel format
00051                conversion pdata is the source address.
00052
00053          -@-   Configure the foreground source address, the background source address,
00054                the destination and data length then Enable the transfer using
00055                HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
00056                in interrupt mode.
00057
00058          -@-   HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
00059                are used if the memory to memory with blending transfer mode is selected.
00060
00061       (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
00062           mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
00063
00064       (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent()
00065
00066       (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
00067           consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
00068           and enable/disable the functionality  with the APIs HAL_DMA2D_EnableDeadTime() or
00069           HAL_DMA2D_DisableDeadTime().
00070
00071       (#) The transfer can be suspended, resumed and aborted using the following
00072           functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
00073
00074       (#) The CLUT loading can be suspended, resumed and aborted using the following
00075           functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
00076           HAL_DMA2D_CLUTLoading_Abort().
00077
00078       (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
00079
00080       (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
00081
00082      *** DMA2D HAL driver macros list ***
00083      =============================================
00084      [..]
00085        Below the list of most used macros in DMA2D HAL driver :
00086
00087       (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
00088       (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
00089       (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
00090       (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
00091       (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
00092       (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.
00093
00094      [..]
00095       (@) You can refer to the DMA2D HAL driver header file for more useful macros
00096
00097   @endverbatim
00098   ******************************************************************************
00099   * @attention
00100   *
00101   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00102   *
00103   * Redistribution and use in source and binary forms, with or without modification,
00104   * are permitted provided that the following conditions are met:
00105   *   1. Redistributions of source code must retain the above copyright notice,
00106   *      this list of conditions and the following disclaimer.
00107   *   2. Redistributions in binary form must reproduce the above copyright notice,
00108   *      this list of conditions and the following disclaimer in the documentation
00109   *      and/or other materials provided with the distribution.
00110   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00111   *      may be used to endorse or promote products derived from this software
00112   *      without specific prior written permission.
00113   *
00114   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00115   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00116   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00117   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00118   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00119   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00120   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00121   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00122   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00123   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00124   *
00125   ******************************************************************************
00126   */
00127
00128 /* Includes ------------------------------------------------------------------*/
00129 #include "stm32h7xx_hal.h"
00130
00131 /** @addtogroup STM32H7xx_HAL_Driver
00132   * @{
00133   */
00134
00135 /** @defgroup DMA2D  DMA2D
00136   * @brief DMA2D HAL module driver
00137   * @{
00138   */
00139
00140 #ifdef HAL_DMA2D_MODULE_ENABLED
00141
00142 /* Private types -------------------------------------------------------------*/
00143 /* Private define ------------------------------------------------------------*/
00144 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
00145   * @{
00146   */
00147
00148 /** @defgroup DMA2D_TimeOut DMA2D Time Out
00149   * @{
00150   */
00151 #define DMA2D_TIMEOUT_ABORT           ((uint32_t)1000)  /*!<  1s  */
00152 #define DMA2D_TIMEOUT_SUSPEND         ((uint32_t)1000)  /*!<  1s  */
00153 /**
00154   * @}
00155   */
00156
00157 /** @defgroup DMA2D_Shifts DMA2D Shifts
00158   * @{
00159   */
00160 #define DMA2D_POSITION_FGPFCCR_CS     (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS)    /*!< Required left shift to set foreground CLUT size */
00161 #define DMA2D_POSITION_BGPFCCR_CS     (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS)    /*!< Required left shift to set background CLUT size */
00162
00163 #define DMA2D_POSITION_FGPFCCR_CCM    (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM)   /*!< Required left shift to set foreground CLUT color mode */
00164 #define DMA2D_POSITION_BGPFCCR_CCM    (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM)   /*!< Required left shift to set background CLUT color mode */
00165
00166 #define DMA2D_POSITION_OPFCCR_AI      (uint32_t)POSITION_VAL(DMA2D_OPFCCR_AI)     /*!< Required left shift to set output alpha inversion     */
00167 #define DMA2D_POSITION_FGPFCCR_AI     (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AI)    /*!< Required left shift to set foreground alpha inversion */
00168 #define DMA2D_POSITION_BGPFCCR_AI     (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AI)    /*!< Required left shift to set background alpha inversion */
00169
00170 #define DMA2D_POSITION_OPFCCR_RBS     (uint32_t)POSITION_VAL(DMA2D_OPFCCR_RBS)    /*!< Required left shift to set output Red/Blue swap     */
00171 #define DMA2D_POSITION_FGPFCCR_RBS    (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_RBS)   /*!< Required left shift to set foreground Red/Blue swap */
00172 #define DMA2D_POSITION_BGPFCCR_RBS    (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_RBS)   /*!< Required left shift to set background Red/Blue swap */
00173
00174 #define DMA2D_POSITION_AMTCR_DT       (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT)      /*!< Required left shift to set deadtime value */
00175
00176 #define DMA2D_POSITION_FGPFCCR_AM     (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM)    /*!< Required left shift to set foreground alpha mode */
00177 #define DMA2D_POSITION_BGPFCCR_AM     (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM)    /*!< Required left shift to set background alpha mode */
00178
00179 #define DMA2D_POSITION_FGPFCCR_ALPHA  (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /*!< Required left shift to set foreground alpha value */
00180 #define DMA2D_POSITION_BGPFCCR_ALPHA  (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /*!< Required left shift to set background alpha value */
00181
00182 #define DMA2D_POSITION_NLR_PL         (uint32_t)POSITION_VAL(DMA2D_NLR_PL)        /*!< Required left shift to set pixels per lines value */
00183
00184 #define DMA2D_POSITION_FGPFCCR_CSS    (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CSS)   /*!< Required left shift to set foreground Chroma sub-sampling */
00185 /**
00186   * @}
00187   */
00188
00189 /**
00190   * @}
00191   */
00192
00193 /* Private variables ---------------------------------------------------------*/
00194 /* Private constants ---------------------------------------------------------*/
00195 /* Private macro -------------------------------------------------------------*/
00196 /* Private function prototypes -----------------------------------------------*/
00197 /** @addtogroup DMA2D_Private_Functions_Prototypes
00198   * @{
00199   */
00200 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
00201 /**
00202   * @}
00203   */
00204
00205 /* Private functions ---------------------------------------------------------*/
00206 /* Exported functions --------------------------------------------------------*/
00207 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
00208   * @{
00209   */
00210
00211 /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
00212  *  @brief   Initialization and Configuration functions
00213  *
00214 @verbatim
00215  ===============================================================================
00216                 ##### Initialization and Configuration functions #####
00217  ===============================================================================
00218     [..]  This section provides functions allowing to:
00219       (+) Initialize and configure the DMA2D
00220       (+) De-initialize the DMA2D
00221
00222 @endverbatim
00223   * @{
00224   */
00225
00226 /**
00227   * @brief  Initialize the DMA2D according to the specified
00228   *         parameters in the DMA2D_InitTypeDef and create the associated handle.
00229   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00230   *                 the configuration information for the DMA2D.
00231   * @retval HAL status
00232   */
00233 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
00234 {
00235   /* Check the DMA2D peripheral state */
00236   if(hdma2d == NULL)
00237   {
00238      return HAL_ERROR;
00239   }
00240
00241   /* Check the parameters */
00242   assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
00243   assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
00244   assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
00245   assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
00246
00247   if(hdma2d->State == HAL_DMA2D_STATE_RESET)
00248   {
00249     /* Allocate lock resource and initialize it */
00250     hdma2d->Lock = HAL_UNLOCKED;
00251     /* Init the low level hardware */
00252     HAL_DMA2D_MspInit(hdma2d);
00253   }
00254
00255   /* Change DMA2D peripheral state */
00256   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00257
00258   /* DMA2D CR register configuration -------------------------------------------*/
00259   MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
00260
00261   /* DMA2D OPFCCR register configuration ---------------------------------------*/
00262   MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
00263
00264   /* DMA2D OOR register configuration ------------------------------------------*/
00265   MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
00266
00267   /* DMA2D OPFCCR AI fields setting (Output Alpha Inversion)*/
00268   MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_AI, (hdma2d->Init.AlphaInverted << DMA2D_POSITION_OPFCCR_AI));
00269
00270   MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_RBS,(hdma2d->Init.RedBlueSwap << DMA2D_POSITION_OPFCCR_RBS));
00271
00272
00273   /* Update error code */
00274   hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
00275
00276   /* Initialize the DMA2D state*/
00277   hdma2d->State  = HAL_DMA2D_STATE_READY;
00278
00279   return HAL_OK;
00280 }
00281
00282 /**
00283   * @brief  Deinitializes the DMA2D peripheral registers to their default reset
00284   *         values.
00285   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00286   *                 the configuration information for the DMA2D.
00287   * @retval None
00288   */
00289
00290 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
00291 {
00292
00293   /* Check the DMA2D peripheral state */
00294   if(hdma2d == NULL)
00295   {
00296      return HAL_ERROR;
00297   }
00298
00299   /* Abort DMA2D transfer if any */
00300   if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
00301   {
00302     if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
00303     {
00304       /* Issue when aborting DMA2D transfer */
00305       return HAL_ERROR;
00306     }
00307   }
00308   else
00309   {
00310     /* Abort background CLUT loading if any */
00311     if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
00312     {
00313       if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0) != HAL_OK)
00314       {
00315         /* Issue when aborting background CLUT loading */
00316         return HAL_ERROR;
00317       }
00318     }
00319     else
00320     {
00321       /* Abort foreground CLUT loading if any */
00322       if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
00323       {
00324         if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1) != HAL_OK)
00325         {
00326           /* Issue when aborting foreground CLUT loading */
00327           return HAL_ERROR;
00328         }
00329       }
00330     }
00331   }
00332
00333
00334
00335   /* Carry on with de-initialization of low level hardware */
00336   HAL_DMA2D_MspDeInit(hdma2d);
00337
00338   /* Reset DMA2D control registers*/
00339   hdma2d->Instance->CR = 0;
00340   hdma2d->Instance->FGOR = 0;
00341   hdma2d->Instance->BGOR = 0;
00342   hdma2d->Instance->FGPFCCR = 0;
00343   hdma2d->Instance->BGPFCCR = 0;
00344   hdma2d->Instance->OPFCCR = 0;
00345
00346   /* Update error code */
00347   hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
00348
00349   /* Initialize the DMA2D state*/
00350   hdma2d->State  = HAL_DMA2D_STATE_RESET;
00351
00352   /* Release Lock */
00353   __HAL_UNLOCK(hdma2d);
00354
00355   return HAL_OK;
00356 }
00357
00358 /**
00359   * @brief  Initializes the DMA2D MSP.
00360   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00361   *                 the configuration information for the DMA2D.
00362   * @retval None
00363   */
00364 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
00365 {
00366   /* Prevent unused argument(s) compilation warning */
00367   UNUSED(hdma2d);
00368
00369   /* NOTE : This function should not be modified; when the callback is needed,
00370             the HAL_DMA2D_MspInit can be implemented in the user file.
00371    */
00372 }
00373
00374 /**
00375   * @brief  DeInitializes the DMA2D MSP.
00376   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00377   *                 the configuration information for the DMA2D.
00378   * @retval None
00379   */
00380 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
00381 {
00382   /* Prevent unused argument(s) compilation warning */
00383   UNUSED(hdma2d);
00384
00385   /* NOTE : This function should not be modified; when the callback is needed,
00386             the HAL_DMA2D_MspDeInit can be implemented in the user file.
00387    */
00388 }
00389
00390 /**
00391   * @}
00392   */
00393
00394
00395 /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
00396  *  @brief   IO operation functions
00397  *
00398 @verbatim
00399  ===============================================================================
00400                       #####  IO operation functions  #####
00401  ===============================================================================
00402     [..]  This section provides functions allowing to:
00403       (+) Configure the pdata, destination address and data size then
00404           start the DMA2D transfer.
00405       (+) Configure the source for foreground and background, destination address
00406           and data size then start a MultiBuffer DMA2D transfer.
00407       (+) Configure the pdata, destination address and data size then
00408           start the DMA2D transfer with interrupt.
00409       (+) Configure the source for foreground and background, destination address
00410           and data size then start a MultiBuffer DMA2D transfer with interrupt.
00411       (+) Abort DMA2D transfer.
00412       (+) Suspend DMA2D transfer.
00413       (+) Resume DMA2D transfer.
00414       (+) Enable CLUT transfer.
00415       (+) Configure CLUT loading then start transfer in polling mode.
00416       (+) Configure CLUT loading then start transfer in interrupt mode.
00417       (+) Abort DMA2D CLUT loading.
00418       (+) Suspend DMA2D CLUT loading.
00419       (+) Resume DMA2D CLUT loading.
00420       (+) Poll for transfer complete.
00421       (+) handle DMA2D interrupt request.
00422       (+) Transfer watermark callback.
00423       (+) CLUT Transfer Complete callback.
00424
00425
00426 @endverbatim
00427   * @{
00428   */
00429
00430 /**
00431   * @brief  Start the DMA2D Transfer.
00432   * @param  hdma2d:     Pointer to a DMA2D_HandleTypeDef structure that contains
00433   *                     the configuration information for the DMA2D.
00434   * @param  pdata:      Configure the source memory Buffer address if
00435   *                     Memory-to-Memory or Memory-to-Memory with pixel format
00436   *                     conversion mode is selected, or configure
00437   *                     the color value if Register-to-Memory mode is selected.
00438   * @param  DstAddress: The destination memory Buffer address.
00439   * @param  Width:      The width of data to be transferred from source to destination (expressed in number of pixels per line).
00440   * @param  Height:     The height of data to be transferred from source to destination (expressed in number of lines).
00441   * @retval HAL status
00442   */
00443 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00444 {
00445   /* Check the parameters */
00446   assert_param(IS_DMA2D_LINE(Height));
00447   assert_param(IS_DMA2D_PIXEL(Width));
00448
00449   /* Process locked */
00450   __HAL_LOCK(hdma2d);
00451
00452   /* Change DMA2D peripheral state */
00453   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00454
00455   /* Configure the source, destination address and the data size */
00456   DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
00457
00458   /* Enable the Peripheral */
00459   __HAL_DMA2D_ENABLE(hdma2d);
00460
00461   return HAL_OK;
00462 }
00463
00464 /**
00465   * @brief  Start the DMA2D Transfer with interrupt enabled.
00466   * @param  hdma2d:     Pointer to a DMA2D_HandleTypeDef structure that contains
00467   *                     the configuration information for the DMA2D.
00468   * @param  pdata:      Configure the source memory Buffer address if
00469   *                     the Memory-to-Memory or Memory-to-Memory with pixel format
00470   *                     conversion mode is selected, or configure
00471   *                     the color value if Register-to-Memory mode is selected.
00472   * @param  DstAddress: The destination memory Buffer address.
00473   * @param  Width:      The width of data to be transferred from source to destination (expressed in number of pixels per line).
00474   * @param  Height:     The height of data to be transferred from source to destination (expressed in number of lines).
00475   * @retval HAL status
00476   */
00477 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00478 {
00479   /* Check the parameters */
00480   assert_param(IS_DMA2D_LINE(Height));
00481   assert_param(IS_DMA2D_PIXEL(Width));
00482
00483   /* Process locked */
00484   __HAL_LOCK(hdma2d);
00485
00486   /* Change DMA2D peripheral state */
00487   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00488
00489   /* Configure the source, destination address and the data size */
00490   DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
00491
00492   /* Enable the transfer complete, transfer error and configuration error interrupts */
00493   __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
00494
00495   /* Enable the Peripheral */
00496   __HAL_DMA2D_ENABLE(hdma2d);
00497
00498   return HAL_OK;
00499 }
00500
00501 /**
00502   * @brief  Start the multi-source DMA2D Transfer.
00503   * @param  hdma2d:      Pointer to a DMA2D_HandleTypeDef structure that contains
00504   *                      the configuration information for the DMA2D.
00505   * @param  SrcAddress1: The source memory Buffer address for the foreground layer.
00506   * @param  SrcAddress2: The source memory Buffer address for the background layer.
00507   * @param  DstAddress:  The destination memory Buffer address.
00508   * @param  Width:       The width of data to be transferred from source to destination (expressed in number of pixels per line).
00509   * @param  Height:      The height of data to be transferred from source to destination (expressed in number of lines).
00510   * @retval HAL status
00511   */
00512 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00513 {
00514   /* Check the parameters */
00515   assert_param(IS_DMA2D_LINE(Height));
00516   assert_param(IS_DMA2D_PIXEL(Width));
00517
00518   /* Process locked */
00519   __HAL_LOCK(hdma2d);
00520
00521   /* Change DMA2D peripheral state */
00522   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00523
00524   /* Configure DMA2D Stream source2 address */
00525   WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
00526
00527   /* Configure the source, destination address and the data size */
00528   DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
00529
00530   /* Enable the Peripheral */
00531   __HAL_DMA2D_ENABLE(hdma2d);
00532
00533   return HAL_OK;
00534 }
00535
00536 /**
00537   * @brief  Start the multi-source DMA2D Transfer with interrupt enabled.
00538   * @param  hdma2d:     Pointer to a DMA2D_HandleTypeDef structure that contains
00539   *                     the configuration information for the DMA2D.
00540   * @param  SrcAddress1: The source memory Buffer address for the foreground layer.
00541   * @param  SrcAddress2: The source memory Buffer address for the background layer.
00542   * @param  DstAddress:  The destination memory Buffer address.
00543   * @param  Width:       The width of data to be transferred from source to destination (expressed in number of pixels per line).
00544   * @param  Height:      The height of data to be transferred from source to destination (expressed in number of lines).
00545   * @retval HAL status
00546   */
00547 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00548 {
00549   /* Check the parameters */
00550   assert_param(IS_DMA2D_LINE(Height));
00551   assert_param(IS_DMA2D_PIXEL(Width));
00552
00553   /* Process locked */
00554   __HAL_LOCK(hdma2d);
00555
00556   /* Change DMA2D peripheral state */
00557   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00558
00559   /* Configure DMA2D Stream source2 address */
00560   WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
00561
00562   /* Configure the source, destination address and the data size */
00563   DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
00564
00565   /* Enable the transfer complete, transfer error and configuration error interrupts */
00566   __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
00567
00568   /* Enable the Peripheral */
00569   __HAL_DMA2D_ENABLE(hdma2d);
00570
00571   return HAL_OK;
00572 }
00573
00574 /**
00575   * @brief  Abort the DMA2D Transfer.
00576   * @param  hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
00577   *                  the configuration information for the DMA2D.
00578   * @retval HAL status
00579   */
00580 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
00581 {
00582   uint32_t tickstart = 0;
00583
00584   /* Abort the DMA2D transfer */
00585   /* START bit is reset to make sure not to set it again, in the event the HW clears it
00586      between the register read and the register write by the CPU (writing ‘0’ has no
00587      effect on START bitvalue). */
00588    MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
00589
00590   /* Get tick */
00591   tickstart = HAL_GetTick();
00592
00593   /* Check if the DMA2D is effectively disabled */
00594   while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
00595   {
00596     if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
00597     {
00598       /* Update error code */
00599       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
00600
00601       /* Change the DMA2D state */
00602       hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
00603
00604       /* Process Unlocked */
00605       __HAL_UNLOCK(hdma2d);
00606
00607       return HAL_TIMEOUT;
00608     }
00609   }
00610
00611   /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
00612   __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
00613
00614   /* Change the DMA2D state*/
00615   hdma2d->State = HAL_DMA2D_STATE_READY;
00616
00617   /* Process Unlocked */
00618   __HAL_UNLOCK(hdma2d);
00619
00620   return HAL_OK;
00621 }
00622
00623 /**
00624   * @brief  Suspend the DMA2D Transfer.
00625   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00626   *                 the configuration information for the DMA2D.
00627   * @retval HAL status
00628   */
00629 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
00630 {
00631   uint32_t tickstart = 0;
00632
00633   /* Suspend the DMA2D transfer */
00634   /* START bit is reset to make sure not to set it again, in the event the HW clears it
00635      between the register read and the register write by the CPU (writing ‘0’ has no
00636      effect on START bitvalue). */
00637   MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
00638
00639   /* Get tick */
00640   tickstart = HAL_GetTick();
00641
00642   /* Check if the DMA2D is effectively suspended */
00643   while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
00644     && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))
00645   {
00646     if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
00647     {
00648       /* Update error code */
00649       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
00650
00651       /* Change the DMA2D state */
00652       hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
00653
00654       return HAL_TIMEOUT;
00655     }
00656   }
00657
00658    /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
00659   if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
00660   {
00661     hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
00662   }
00663   else
00664   {
00665     /* Make sure SUSP bit is cleared since it is meaningless
00666        when no tranfer is on-going */
00667     CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
00668   }
00669
00670   return HAL_OK;
00671 }
00672
00673 /**
00674   * @brief  Resume the DMA2D Transfer.
00675   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00676   *                 the configuration information for the DMA2D.
00677   * @retval HAL status
00678   */
00679 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
00680 {
00681   /* Check the SUSP and START bits */
00682   if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
00683   {
00684     /* Ongoing transfer is suspended: change the DMA2D state before resuming */
00685     hdma2d->State = HAL_DMA2D_STATE_BUSY;
00686   }
00687
00688   /* Resume the DMA2D transfer */
00689   /* START bit is reset to make sure not to set it again, in the event the HW clears it
00690      between the register read and the register write by the CPU (writing ‘0’ has no
00691      effect on START bitvalue). */
00692   CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
00693
00694   return HAL_OK;
00695 }
00696
00697
00698 /**
00699   * @brief  Enable the DMA2D CLUT Transfer.
00700   * @param  hdma2d:   Pointer to a DMA2D_HandleTypeDef structure that contains
00701   *                   the configuration information for the DMA2D.
00702   * @param  LayerIdx: DMA2D Layer index.
00703   *                   This parameter can be one of the following values:
00704   *                   0(background) / 1(foreground)
00705   * @retval HAL status
00706   */
00707 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
00708 {
00709   /* Check the parameters */
00710   assert_param(IS_DMA2D_LAYER(LayerIdx));
00711
00712   /* Process locked */
00713   __HAL_LOCK(hdma2d);
00714
00715   /* Change DMA2D peripheral state */
00716   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00717
00718   if(LayerIdx == 0)
00719   {
00720     /* Enable the background CLUT loading */
00721     SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
00722   }
00723   else
00724   {
00725     /* Enable the foreground CLUT loading */
00726     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
00727   }
00728
00729   return HAL_OK;
00730 }
00731
00732
00733 /**
00734   * @brief  Start DMA2D CLUT Loading.
00735   * @param  hdma2d:   Pointer to a DMA2D_HandleTypeDef structure that contains
00736   *                   the configuration information for the DMA2D.
00737   * @param  CLUTCfg:  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
00738   *                   the configuration information for the color look up table.
00739   * @param  LayerIdx: DMA2D Layer index.
00740   *                   This parameter can be one of the following values:
00741   *                   0(background) / 1(foreground)
00742   * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
00743   * @retval HAL status
00744   */
00745 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
00746 {
00747   /* Check the parameters */
00748   assert_param(IS_DMA2D_LAYER(LayerIdx));
00749   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
00750   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
00751
00752   /* Process locked */
00753   __HAL_LOCK(hdma2d);
00754
00755   /* Change DMA2D peripheral state */
00756   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00757
00758   /* Configure the CLUT of the background DMA2D layer */
00759   if(LayerIdx == 0)
00760   {
00761     /* Write background CLUT memory address */
00762     WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
00763
00764     /* Write background CLUT size and CLUT color mode */
00765     MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
00766             ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
00767
00768     /* Enable the CLUT loading for the background */
00769     SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
00770   }
00771   /* Configure the CLUT of the foreground DMA2D layer */
00772   else
00773   {
00774     /* Write foreground CLUT memory address */
00775     WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
00776
00777     /* Write foreground CLUT size and CLUT color mode */
00778     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
00779             ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
00780
00781  /* Enable the CLUT loading for the foreground */
00782     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
00783   }
00784
00785   return HAL_OK;
00786 }
00787
00788 /**
00789   * @brief  Start DMA2D CLUT Loading with interrupt enabled.
00790   * @param  hdma2d:   Pointer to a DMA2D_HandleTypeDef structure that contains
00791   *                   the configuration information for the DMA2D.
00792   * @param  CLUTCfg:  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
00793   *                   the configuration information for the color look up table.
00794   * @param  LayerIdx: DMA2D Layer index.
00795   *                   This parameter can be one of the following values:
00796   *                   0(background) / 1(foreground)
00797   * @retval HAL status
00798   */
00799 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
00800 {
00801   /* Check the parameters */
00802   assert_param(IS_DMA2D_LAYER(LayerIdx));
00803   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
00804   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
00805
00806   /* Process locked */
00807   __HAL_LOCK(hdma2d);
00808
00809   /* Change DMA2D peripheral state */
00810   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00811
00812   /* Configure the CLUT of the background DMA2D layer */
00813   if(LayerIdx == 0)
00814   {
00815     /* Write background CLUT memory address */
00816     WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
00817
00818     /* Write background CLUT size and CLUT color mode */
00819     MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
00820             ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
00821
00822     /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
00823     __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
00824
00825     /* Enable the CLUT loading for the background */
00826     SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
00827   }
00828   /* Configure the CLUT of the foreground DMA2D layer */
00829   else
00830   {
00831     /* Write foreground CLUT memory address */
00832     WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
00833
00834     /* Write foreground CLUT size and CLUT color mode */
00835     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
00836             ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
00837
00838     /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
00839     __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
00840
00841     /* Enable the CLUT loading for the foreground */
00842     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
00843   }
00844
00845   return HAL_OK;
00846 }
00847
00848 /**
00849   * @brief  Abort the DMA2D CLUT loading.
00850   * @param  hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains
00851   *                  the configuration information for the DMA2D.
00852   * @param  LayerIdx: DMA2D Layer index.
00853   *                   This parameter can be one of the following values:
00854   *                   0(background) / 1(foreground)
00855   * @retval HAL status
00856   */
00857 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
00858 {
00859   uint32_t tickstart  = 0;
00860   __IO uint32_t * reg =  &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
00861   uint32_t mask       = DMA2D_BGPFCCR_START;           /* by default, set to background constant   */
00862
00863
00864   /* Abort the CLUT loading */
00865   SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
00866
00867   /* If foreground CLUT loading is considered, update local variables */
00868   if(LayerIdx == 1)
00869   {
00870     reg  = &(hdma2d->Instance->FGPFCCR);
00871   }
00872
00873
00874   /* Get tick */
00875   tickstart = HAL_GetTick();
00876
00877   /* Check if the CLUT loading is aborted */
00878   while((*reg & mask) != RESET)
00879   {
00880     if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
00881     {
00882       /* Update error code */
00883       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
00884
00885       /* Change the DMA2D state */
00886       hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
00887
00888       /* Process Unlocked */
00889       __HAL_UNLOCK(hdma2d);
00890
00891       return HAL_TIMEOUT;
00892     }
00893   }
00894
00895   /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
00896   __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
00897
00898   /* Change the DMA2D state*/
00899   hdma2d->State = HAL_DMA2D_STATE_READY;
00900
00901   /* Process Unlocked */
00902   __HAL_UNLOCK(hdma2d);
00903
00904   return HAL_OK;
00905 }
00906
00907 /**
00908   * @brief  Suspend the DMA2D CLUT loading.
00909   * @param  hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
00910   *                 the configuration information for the DMA2D.
00911   * @param  LayerIdx: DMA2D Layer index.
00912   *                   This parameter can be one of the following values:
00913   *                   0(background) / 1(foreground)
00914   * @retval HAL status
00915   */
00916 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
00917 {
00918   uint32_t tickstart = 0;
00919   __IO uint32_t * reg =  &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
00920   uint32_t mask       = DMA2D_BGPFCCR_START;           /* by default, set to background constant   */
00921
00922
00923   /* Suspend the CLUT loading */
00924   SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
00925
00926   /* If foreground CLUT loading is considered, update local variables */
00927   if(LayerIdx == 1)
00928   {
00929     reg  = &(hdma2d->Instance->FGPFCCR);
00930   }
00931
00932   /* Get tick */
00933   tickstart = HAL_GetTick();
00934
00935   /* Check if the CLUT loading is suspended */
00936   while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
00937     && ((*reg & mask) == mask))
00938   {
00939     if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
00940     {
00941       /* Update error code */
00942       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
00943
00944       /* Change the DMA2D state */
00945       hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
00946
00947       return HAL_TIMEOUT;
00948     }
00949   }
00950
00951    /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
00952   if ((*reg & mask) != RESET)
00953   {
00954     hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
00955   }
00956   else
00957   {
00958     /* Make sure SUSP bit is cleared since it is meaningless
00959        when no tranfer is on-going */
00960     CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
00961   }
00962
00963   return HAL_OK;
00964 }
00965
00966 /**
00967   * @brief  Resume the DMA2D CLUT loading.
00968   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00969   *                 the configuration information for the DMA2D.
00970   * @param  LayerIdx: DMA2D Layer index.
00971   *                   This parameter can be one of the following values:
00972   *                   0(background) / 1(foreground)
00973   * @retval HAL status
00974   */
00975 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
00976 {
00977   /* Check the SUSP and START bits for background or foreground CLUT loading */
00978   if(LayerIdx == 0)
00979   {
00980     /* Background CLUT loading suspension check */
00981     if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
00982       && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
00983     {
00984       /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
00985       hdma2d->State = HAL_DMA2D_STATE_BUSY;
00986     }
00987   }
00988   else
00989   {
00990     /* Foreground CLUT loading suspension check */
00991     if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
00992       && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START))
00993     {
00994       /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
00995       hdma2d->State = HAL_DMA2D_STATE_BUSY;
00996     }
00997   }
00998
00999   /* Resume the CLUT loading */
01000   CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
01001
01002   return HAL_OK;
01003 }
01004
01005
01006 /**
01007
01008   * @brief  Polling for transfer complete or CLUT loading.
01009   * @param  hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
01010   *                 the configuration information for the DMA2D.
01011   * @param  Timeout: Timeout duration
01012   * @retval HAL status
01013   */
01014 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
01015 {
01016   uint32_t tickstart = 0;
01017   __IO uint32_t isrflags = 0x0;
01018
01019   /* Polling for DMA2D transfer */
01020   if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
01021   {
01022    /* Get tick */
01023    tickstart = HAL_GetTick();
01024
01025     while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
01026     {
01027       isrflags = READ_REG(hdma2d->Instance->ISR);
01028       if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
01029       {
01030         if ((isrflags & DMA2D_FLAG_CE) != RESET)
01031         {
01032           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
01033         }
01034         if ((isrflags & DMA2D_FLAG_TE) != RESET)
01035         {
01036           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
01037         }
01038         /* Clear the transfer and configuration error flags */
01039         __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
01040
01041         /* Change DMA2D state */
01042         hdma2d->State = HAL_DMA2D_STATE_ERROR;
01043
01044         /* Process unlocked */
01045         __HAL_UNLOCK(hdma2d);
01046
01047         return HAL_ERROR;
01048       }
01049       /* Check for the Timeout */
01050       if(Timeout != HAL_MAX_DELAY)
01051       {
01052         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01053         {
01054           /* Update error code */
01055           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
01056
01057           /* Change the DMA2D state */
01058           hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
01059
01060           /* Process unlocked */
01061           __HAL_UNLOCK(hdma2d);
01062
01063           return HAL_TIMEOUT;
01064         }
01065       }
01066     }
01067   }
01068   /* Polling for CLUT loading (foreground or background) */
01069   if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET)  ||
01070       ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET))
01071   {
01072     /* Get tick */
01073     tickstart = HAL_GetTick();
01074
01075     while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
01076     {
01077       isrflags = READ_REG(hdma2d->Instance->ISR);
01078       if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
01079       {
01080         if ((isrflags & DMA2D_FLAG_CAE) != RESET)
01081         {
01082           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
01083         }
01084         if ((isrflags & DMA2D_FLAG_CE) != RESET)
01085         {
01086           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
01087         }
01088         if ((isrflags & DMA2D_FLAG_TE) != RESET)
01089         {
01090           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
01091         }
01092         /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
01093         __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
01094
01095         /* Change DMA2D state */
01096         hdma2d->State= HAL_DMA2D_STATE_ERROR;
01097
01098         /* Process unlocked */
01099         __HAL_UNLOCK(hdma2d);
01100
01101         return HAL_ERROR;
01102       }
01103       /* Check for the Timeout */
01104       if(Timeout != HAL_MAX_DELAY)
01105       {
01106         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01107         {
01108           /* Update error code */
01109           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
01110
01111           /* Change the DMA2D state */
01112           hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
01113
01114           /* Process unlocked */
01115           __HAL_UNLOCK(hdma2d);
01116
01117           return HAL_TIMEOUT;
01118         }
01119       }
01120     }
01121   }
01122
01123   /* Clear the transfer complete and CLUT loading flags */
01124   __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
01125
01126   /* Change DMA2D state */
01127   hdma2d->State = HAL_DMA2D_STATE_READY;
01128
01129   /* Process unlocked */
01130   __HAL_UNLOCK(hdma2d);
01131
01132   return HAL_OK;
01133 }
01134 /**
01135   * @brief  Handle DMA2D interrupt request.
01136   * @param  hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
01137   *                 the configuration information for the DMA2D.
01138   * @retval HAL status
01139   */
01140 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
01141 {
01142   uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
01143   uint32_t crflags = READ_REG(hdma2d->Instance->CR);
01144
01145   /* Transfer Error Interrupt management ***************************************/
01146   if ((isrflags & DMA2D_FLAG_TE) != RESET)
01147   {
01148     if ((crflags & DMA2D_IT_TE) != RESET)
01149     {
01150       /* Disable the transfer Error interrupt */
01151       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
01152
01153       /* Update error code */
01154       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
01155
01156       /* Clear the transfer error flag */
01157       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
01158
01159       /* Change DMA2D state */
01160       hdma2d->State = HAL_DMA2D_STATE_ERROR;
01161
01162       /* Process Unlocked */
01163       __HAL_UNLOCK(hdma2d);
01164
01165       if(hdma2d->XferErrorCallback != NULL)
01166       {
01167         /* Transfer error Callback */
01168         hdma2d->XferErrorCallback(hdma2d);
01169       }
01170     }
01171   }
01172   /* Configuration Error Interrupt management **********************************/
01173   if ((isrflags & DMA2D_FLAG_CE) != RESET)
01174   {
01175     if ((crflags & DMA2D_IT_CE) != RESET)
01176     {
01177       /* Disable the Configuration Error interrupt */
01178       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
01179
01180       /* Clear the Configuration error flag */
01181       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
01182
01183       /* Update error code */
01184       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
01185
01186       /* Change DMA2D state */
01187       hdma2d->State = HAL_DMA2D_STATE_ERROR;
01188
01189       /* Process Unlocked */
01190       __HAL_UNLOCK(hdma2d);
01191
01192       if(hdma2d->XferErrorCallback != NULL)
01193       {
01194         /* Transfer error Callback */
01195         hdma2d->XferErrorCallback(hdma2d);
01196       }
01197     }
01198   }
01199   /* CLUT access Error Interrupt management ***********************************/
01200   if ((isrflags & DMA2D_FLAG_CAE) != RESET)
01201   {
01202     if ((crflags & DMA2D_IT_CAE) != RESET)
01203     {
01204       /* Disable the CLUT access error interrupt */
01205       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
01206
01207       /* Clear the CLUT access error flag */
01208       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
01209
01210       /* Update error code */
01211       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
01212
01213       /* Change DMA2D state */
01214       hdma2d->State = HAL_DMA2D_STATE_ERROR;
01215
01216       /* Process Unlocked */
01217       __HAL_UNLOCK(hdma2d);
01218
01219       if(hdma2d->XferErrorCallback != NULL)
01220       {
01221         /* Transfer error Callback */
01222         hdma2d->XferErrorCallback(hdma2d);
01223       }
01224     }
01225   }
01226   /* Transfer watermark Interrupt management **********************************/
01227   if ((isrflags & DMA2D_FLAG_TW) != RESET)
01228   {
01229     if ((crflags & DMA2D_IT_TW) != RESET)
01230     {
01231       /* Disable the transfer watermark interrupt */
01232       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
01233
01234       /* Clear the transfer watermark flag */
01235       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
01236
01237       /* Transfer watermark Callback */
01238       HAL_DMA2D_LineEventCallback(hdma2d);
01239     }
01240   }
01241   /* Transfer Complete Interrupt management ************************************/
01242   if ((isrflags & DMA2D_FLAG_TC) != RESET)
01243   {
01244     if ((crflags & DMA2D_IT_TC) != RESET)
01245     {
01246       /* Disable the transfer complete interrupt */
01247       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
01248
01249       /* Clear the transfer complete flag */
01250       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
01251
01252       /* Update error code */
01253       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
01254
01255       /* Change DMA2D state */
01256       hdma2d->State = HAL_DMA2D_STATE_READY;
01257
01258       /* Process Unlocked */
01259       __HAL_UNLOCK(hdma2d);
01260
01261       if(hdma2d->XferCpltCallback != NULL)
01262       {
01263         /* Transfer complete Callback */
01264         hdma2d->XferCpltCallback(hdma2d);
01265       }
01266     }
01267   }
01268   /* CLUT Transfer Complete Interrupt management ******************************/
01269   if ((isrflags & DMA2D_FLAG_CTC) != RESET)
01270   {
01271     if ((crflags & DMA2D_IT_CTC) != RESET)
01272     {
01273       /* Disable the CLUT transfer complete interrupt */
01274       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
01275
01276       /* Clear the CLUT transfer complete flag */
01277       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
01278
01279       /* Update error code */
01280       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
01281
01282       /* Change DMA2D state */
01283       hdma2d->State = HAL_DMA2D_STATE_READY;
01284
01285       /* Process Unlocked */
01286       __HAL_UNLOCK(hdma2d);
01287
01288       /* CLUT Transfer complete Callback */
01289       HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
01290     }
01291   }
01292
01293 }
01294
01295 /**
01296   * @brief  Transfer watermark callback.
01297   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
01298   *                 the configuration information for the DMA2D.
01299   * @retval None
01300   */
01301 __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
01302 {
01303   /* Prevent unused argument(s) compilation warning */
01304   UNUSED(hdma2d);
01305
01306   /* NOTE : This function should not be modified; when the callback is needed,
01307             the HAL_DMA2D_LineEventCallback can be implemented in the user file.
01308    */
01309 }
01310
01311 /**
01312   * @brief  CLUT Transfer Complete callback.
01313   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
01314   *                 the configuration information for the DMA2D.
01315   * @retval None
01316   */
01317 __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
01318 {
01319   /* Prevent unused argument(s) compilation warning */
01320   UNUSED(hdma2d);
01321
01322   /* NOTE : This function should not be modified; when the callback is needed,
01323             the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
01324    */
01325 }
01326
01327 /**
01328   * @}
01329   */
01330
01331 /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
01332  *  @brief    Peripheral Control functions
01333  *
01334 @verbatim
01335  ===============================================================================
01336                     ##### Peripheral Control functions #####
01337  ===============================================================================
01338     [..]  This section provides functions allowing to:
01339       (+) Configure the DMA2D foreground or background layer parameters.
01340       (+) Configure the DMA2D CLUT transfer.
01341       (+) Configure the line watermark
01342       (+) Configure the dead time value.
01343       (+) Enable or disable the dead time value functionality.
01344
01345
01346 @endverbatim
01347   * @{
01348   */
01349
01350 /**
01351   * @brief  Configure the DMA2D Layer according to the specified
01352   *         parameters in the DMA2D_InitTypeDef and create the associated handle.
01353   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
01354   *                 the configuration information for the DMA2D.
01355   * @param  LayerIdx: DMA2D Layer index.
01356   *                   This parameter can be one of the following values:
01357   *                   0(background) / 1(foreground)
01358   * @retval HAL status
01359   */
01360 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
01361 {
01362   DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
01363
01364   uint32_t regMask = 0, regValue = 0;
01365
01366   /* Check the parameters */
01367   assert_param(IS_DMA2D_LAYER(LayerIdx));
01368   assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));
01369   if(hdma2d->Init.Mode != DMA2D_R2M)
01370   {
01371     assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
01372     if(hdma2d->Init.Mode != DMA2D_M2M)
01373     {
01374       assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));
01375     }
01376   }
01377
01378   /* Process locked */
01379   __HAL_LOCK(hdma2d);
01380
01381   /* Change DMA2D peripheral state */
01382   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01383
01384   /* DMA2D BGPFCR register configuration -----------------------------------*/
01385   /* Prepare the value to be written to the BGPFCCR register */
01386
01387   regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | \
01388             (pLayerCfg->AlphaInverted << DMA2D_POSITION_BGPFCCR_AI) | \
01389             (pLayerCfg->RedBlueSwap << DMA2D_POSITION_BGPFCCR_RBS);
01390
01391   regMask  = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS;
01392
01393   if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
01394   {
01395     regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
01396   }
01397   else
01398   {
01399     regValue |=  (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA);
01400   }
01401
01402   /* Configure the background DMA2D layer */
01403   if(LayerIdx == 0)
01404   {
01405     /* Write DMA2D BGPFCCR register */
01406     MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
01407
01408     /* DMA2D BGOR register configuration -------------------------------------*/
01409     WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
01410
01411     /* DMA2D BGCOLR register configuration -------------------------------------*/
01412     if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
01413     {
01414       WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
01415     }
01416   }
01417   /* Configure the foreground DMA2D layer */
01418   else
01419   {
01420     if(pLayerCfg->InputColorMode == DMA2D_INPUT_YCBCR)
01421     {
01422       regValue |= (pLayerCfg->ChromaSubSampling << DMA2D_POSITION_FGPFCCR_CSS);
01423       regMask  |= DMA2D_FGPFCCR_CSS;
01424     }
01425
01426      /* Write DMA2D FGPFCCR register */
01427     MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
01428
01429     /* DMA2D FGOR register configuration -------------------------------------*/
01430     WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
01431
01432     /* DMA2D FGCOLR register configuration -------------------------------------*/
01433     if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
01434     {
01435       WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
01436     }
01437   }
01438   /* Initialize the DMA2D state*/
01439   hdma2d->State = HAL_DMA2D_STATE_READY;
01440
01441   /* Process unlocked */
01442   __HAL_UNLOCK(hdma2d);
01443
01444   return HAL_OK;
01445 }
01446
01447 /**
01448   * @brief  Configure the DMA2D CLUT Transfer.
01449   * @param  hdma2d:   Pointer to a DMA2D_HandleTypeDef structure that contains
01450   *                   the configuration information for the DMA2D.
01451   * @param  CLUTCfg:  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
01452   *                   the configuration information for the color look up table.
01453   * @param  LayerIdx: DMA2D Layer index.
01454   *                   This parameter can be one of the following values:
01455   *                   0(background) / 1(foreground)
01456   * @retval HAL status
01457   */
01458 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
01459 {
01460   /* Check the parameters */
01461   assert_param(IS_DMA2D_LAYER(LayerIdx));
01462   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
01463   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
01464
01465   /* Process locked */
01466   __HAL_LOCK(hdma2d);
01467
01468   /* Change DMA2D peripheral state */
01469   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01470
01471   /* Configure the CLUT of the background DMA2D layer */
01472   if(LayerIdx == 0)
01473   {
01474     /* Write background CLUT memory address */
01475     WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
01476
01477     /* Write background CLUT size and CLUT color mode */
01478     MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
01479             ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
01480  }
01481  /* Configure the CLUT of the foreground DMA2D layer */
01482  else
01483  {
01484    /* Write foreground CLUT memory address */
01485     WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
01486
01487     /* Write foreground CLUT size and CLUT color mode */
01488     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
01489             ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
01490   }
01491
01492   /* Set the DMA2D state to Ready*/
01493   hdma2d->State = HAL_DMA2D_STATE_READY;
01494
01495   /* Process unlocked */
01496   __HAL_UNLOCK(hdma2d);
01497
01498   return HAL_OK;
01499 }
01500
01501
01502 /**
01503   * @brief  Configure the line watermark.
01504   * @param  hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
01505   *                 the configuration information for the DMA2D.
01506   * @param  Line:   Line Watermark configuration (maximum 16-bit long value expected).
01507   * @note   HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
01508   * @note   The transfer watermark interrupt is disabled once it has occurred.
01509   * @retval HAL status
01510   */
01511
01512 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
01513 {
01514   /* Check the parameters */
01515   assert_param(IS_DMA2D_LINEWATERMARK(Line));
01516
01517   /* Process locked */
01518   __HAL_LOCK(hdma2d);
01519
01520   /* Change DMA2D peripheral state */
01521   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01522
01523   /* Sets the Line watermark configuration */
01524   WRITE_REG(hdma2d->Instance->LWR, Line);
01525
01526   /* Enable the Line interrupt */
01527   __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
01528
01529   /* Initialize the DMA2D state*/
01530   hdma2d->State = HAL_DMA2D_STATE_READY;
01531
01532   /* Process unlocked */
01533   __HAL_UNLOCK(hdma2d);
01534
01535   return HAL_OK;
01536 }
01537
01538 /**
01539   * @brief Enable DMA2D dead time feature.
01540   * @param hdma2d: DMA2D handle.
01541   * @retval HAL status
01542   */
01543 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
01544 {
01545   /* Process Locked */
01546   __HAL_LOCK(hdma2d);
01547
01548   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01549
01550   /* Set DMA2D_AMTCR EN bit */
01551   SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
01552
01553   hdma2d->State = HAL_DMA2D_STATE_READY;
01554
01555   /* Process Unlocked */
01556   __HAL_UNLOCK(hdma2d);
01557
01558   return HAL_OK;
01559 }
01560
01561 /**
01562   * @brief Disable DMA2D dead time feature.
01563   * @param hdma2d: DMA2D handle.
01564   * @retval HAL status
01565   */
01566 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
01567 {
01568   /* Process Locked */
01569   __HAL_LOCK(hdma2d);
01570
01571   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01572
01573   /* Clear DMA2D_AMTCR EN bit */
01574   CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
01575
01576   hdma2d->State = HAL_DMA2D_STATE_READY;
01577
01578   /* Process Unlocked */
01579   __HAL_UNLOCK(hdma2d);
01580
01581   return HAL_OK;
01582 }
01583
01584 /**
01585   * @brief Configure dead time.
01586   * @note The dead time value represents the guaranteed minimum number of cycles between
01587   *       two consecutive transactions on the AHB bus.
01588   * @param hdma2d: DMA2D handle.
01589   * @param DeadTime: dead time value.
01590   * @retval HAL status
01591   */
01592 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
01593 {
01594   /* Process Locked */
01595   __HAL_LOCK(hdma2d);
01596
01597   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01598
01599   /* Set DMA2D_AMTCR DT field */
01600   MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT));
01601
01602   hdma2d->State = HAL_DMA2D_STATE_READY;
01603
01604   /* Process Unlocked */
01605   __HAL_UNLOCK(hdma2d);
01606
01607   return HAL_OK;
01608 }
01609
01610 /**
01611   * @}
01612   */
01613
01614
01615 /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
01616  *  @brief    Peripheral State functions
01617  *
01618 @verbatim
01619  ===============================================================================
01620                   ##### Peripheral State and Errors functions #####
01621  ===============================================================================
01622     [..]
01623     This subsection provides functions allowing to :
01624       (+) Get the DMA2D state
01625       (+) Get the DMA2D error code
01626
01627 @endverbatim
01628   * @{
01629   */
01630
01631 /**
01632   * @brief  Return the DMA2D state
01633   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
01634   *                 the configuration information for the DMA2D.
01635   * @retval HAL state
01636   */
01637 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
01638 {
01639   return hdma2d->State;
01640 }
01641
01642 /**
01643   * @brief  Return the DMA2D error code
01644   * @param  hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
01645   *               the configuration information for DMA2D.
01646   * @retval DMA2D Error Code
01647   */
01648 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
01649 {
01650   return hdma2d->ErrorCode;
01651 }
01652
01653 /**
01654   * @}
01655   */
01656
01657 /**
01658   * @}
01659   */
01660
01661
01662 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
01663   * @{
01664   */
01665
01666 /**
01667   * @brief  Set the DMA2D transfer parameters.
01668   * @param  hdma2d:     Pointer to a DMA2D_HandleTypeDef structure that contains
01669   *                     the configuration information for the specified DMA2D.
01670   * @param  pdata:      The source memory Buffer address
01671   * @param  DstAddress: The destination memory Buffer address
01672   * @param  Width:      The width of data to be transferred from source to destination.
01673   * @param  Height:     The height of data to be transferred from source to destination.
01674   * @retval HAL status
01675   */
01676 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
01677 {
01678   uint32_t tmp = 0;
01679   uint32_t tmp1 = 0;
01680   uint32_t tmp2 = 0;
01681   uint32_t tmp3 = 0;
01682   uint32_t tmp4 = 0;
01683
01684   /* Configure DMA2D data size */
01685   MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL)));
01686
01687   /* Configure DMA2D destination address */
01688   WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
01689
01690   /* Register to memory DMA2D mode selected */
01691   if (hdma2d->Init.Mode == DMA2D_R2M)
01692   {
01693     tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
01694     tmp2 = pdata & DMA2D_OCOLR_RED_1;
01695     tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
01696     tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
01697
01698     /* Prepare the value to be written to the OCOLR register according to the color mode */
01699     if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
01700     {
01701       tmp = (tmp3 | tmp2 | tmp1| tmp4);
01702     }
01703     else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
01704     {
01705       tmp = (tmp3 | tmp2 | tmp4);
01706     }
01707     else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
01708     {
01709       tmp2 = (tmp2 >> 19);
01710       tmp3 = (tmp3 >> 10);
01711       tmp4 = (tmp4 >> 3 );
01712       tmp  = ((tmp3 << 5) | (tmp2 << 11) | tmp4);
01713     }
01714     else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
01715     {
01716       tmp1 = (tmp1 >> 31);
01717       tmp2 = (tmp2 >> 19);
01718       tmp3 = (tmp3 >> 11);
01719       tmp4 = (tmp4 >> 3 );
01720       tmp  = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4);
01721     }
01722     else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
01723     {
01724       tmp1 = (tmp1 >> 28);
01725       tmp2 = (tmp2 >> 20);
01726       tmp3 = (tmp3 >> 12);
01727       tmp4 = (tmp4 >> 4 );
01728       tmp  = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4);
01729     }
01730     /* Write to DMA2D OCOLR register */
01731     WRITE_REG(hdma2d->Instance->OCOLR, tmp);
01732   }
01733   else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
01734   {
01735     /* Configure DMA2D source address */
01736     WRITE_REG(hdma2d->Instance->FGMAR, pdata);
01737   }
01738 }
01739
01740 /**
01741   * @}
01742   */
01743 #endif /* HAL_DMA2D_MODULE_ENABLED */
01744 /**
01745   * @}
01746   */
01747
01748 /**
01749   * @}
01750   */
01751
01752 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dma2d.h Source File

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stm32h7xx_hal_dma2d.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dma2d.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of DMA2D HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_DMA2D_H
00040 #define __STM32H7xx_HAL_DMA2D_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup DMA2D DMA2D
00054   * @brief DMA2D HAL module driver
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types
00060   * @{
00061   */
00062 #define MAX_DMA2D_LAYER  2U  /*!< DMA2D maximum number of layers */
00063
00064 /**
00065   * @brief DMA2D color Structure definition
00066   */
00067 typedef struct
00068 {
00069   uint32_t Blue;               /*!< Configures the blue value.
00070                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00071
00072   uint32_t Green;              /*!< Configures the green value.
00073                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00074
00075   uint32_t Red;                /*!< Configures the red value.
00076                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00077 } DMA2D_ColorTypeDef;
00078
00079 /**
00080   * @brief DMA2D CLUT Structure definition
00081   */
00082 typedef struct
00083 {
00084   uint32_t *pCLUT;                  /*!< Configures the DMA2D CLUT memory address.*/
00085
00086   uint32_t CLUTColorMode;           /*!< Configures the DMA2D CLUT color mode.
00087                                          This parameter can be one value of @ref DMA2D_CLUT_CM. */
00088
00089   uint32_t Size;                    /*!< Configures the DMA2D CLUT size.
00090                                          This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
00091 } DMA2D_CLUTCfgTypeDef;
00092
00093 /**
00094   * @brief DMA2D Init structure definition
00095   */
00096 typedef struct
00097 {
00098   uint32_t             Mode;               /*!< Configures the DMA2D transfer mode.
00099                                                 This parameter can be one value of @ref DMA2D_Mode. */
00100
00101   uint32_t             ColorMode;          /*!< Configures the color format of the output image.
00102                                                 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
00103
00104   uint32_t             OutputOffset;       /*!< Specifies the Offset value.
00105                                                 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
00106   uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value for the output pixel format converter.
00107                                                This parameter can be one value of @ref DMA2D_Alpha_Inverted */
00108
00109   uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)
00110                                                for the output pixel format converter.
00111                                                This parameter can be one value of @ref DMA2D_RB_Swap. */
00112
00113 } DMA2D_InitTypeDef;
00114
00115
00116 /**
00117   * @brief DMA2D Layer structure definition
00118   */
00119 typedef struct
00120 {
00121   uint32_t             InputOffset;       /*!< Configures the DMA2D foreground or background offset.
00122                                                This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
00123
00124   uint32_t             InputColorMode;    /*!< Configures the DMA2D foreground or background color mode.
00125                                                This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
00126
00127   uint32_t             AlphaMode;         /*!< Configures the DMA2D foreground or background alpha mode.
00128                                                This parameter can be one value of @ref DMA2D_Alpha_Mode. */
00129
00130   uint32_t             InputAlpha;        /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
00131                                                This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
00132                                                @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
00133                                                Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
00134                                                - InputAlpha[24:31] is the alpha value ALPHA[0:7]
00135                                                - InputAlpha[16:23] is the red value RED[0:7]
00136                                                - InputAlpha[8:15] is the green value GREEN[0:7]
00137                                                - InputAlpha[0:7] is the blue value BLUE[0:7]. */
00138
00139   uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value.
00140                                                This parameter can be one value of @ref DMA2D_Alpha_Inverted.*/
00141
00142   uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).
00143                                                This parameter can be one value of @ref DMA2D_RB_Swap. */
00144
00145   uint32_t             ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode
00146                                                This parameter can be one value of @ref DMA2D_Chroma_Sub_Sampling */
00147 } DMA2D_LayerCfgTypeDef;
00148
00149 /**
00150   * @brief  HAL DMA2D State structures definition
00151   */
00152 typedef enum
00153 {
00154   HAL_DMA2D_STATE_RESET             = 0x00U,    /*!< DMA2D not yet initialized or disabled       */
00155   HAL_DMA2D_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
00156   HAL_DMA2D_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
00157   HAL_DMA2D_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
00158   HAL_DMA2D_STATE_ERROR             = 0x04U,    /*!< DMA2D state error                           */
00159   HAL_DMA2D_STATE_SUSPEND           = 0x05U     /*!< DMA2D process is suspended                  */
00160 }HAL_DMA2D_StateTypeDef;
00161
00162 /**
00163   * @brief  DMA2D handle Structure definition
00164   */
00165 typedef struct __DMA2D_HandleTypeDef
00166 {
00167   DMA2D_TypeDef               *Instance;                                                    /*!< DMA2D register base address.               */
00168
00169   DMA2D_InitTypeDef           Init;                                                         /*!< DMA2D communication parameters.            */
00170
00171   void                        (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d);  /*!< DMA2D transfer complete callback.          */
00172
00173   void                        (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback.             */
00174
00175   DMA2D_LayerCfgTypeDef       LayerCfg[MAX_DMA2D_LAYER];                                    /*!< DMA2D Layers parameters           */
00176
00177   HAL_LockTypeDef             Lock;                                                         /*!< DMA2D lock.                                */
00178
00179   __IO HAL_DMA2D_StateTypeDef State;                                                        /*!< DMA2D transfer state.                      */
00180
00181   __IO uint32_t               ErrorCode;                                                    /*!< DMA2D error code.                          */
00182 } DMA2D_HandleTypeDef;
00183 /**
00184   * @}
00185   */
00186
00187 /* Exported constants --------------------------------------------------------*/
00188 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
00189   * @{
00190   */
00191
00192 /** @defgroup DMA2D_Error_Code DMA2D Error Code
00193   * @{
00194   */
00195 #define HAL_DMA2D_ERROR_NONE        ((uint32_t)0x00000000U)  /*!< No error             */
00196 #define HAL_DMA2D_ERROR_TE          ((uint32_t)0x00000001U)  /*!< Transfer error       */
00197 #define HAL_DMA2D_ERROR_CE          ((uint32_t)0x00000002U)  /*!< Configuration error  */
00198 #define HAL_DMA2D_ERROR_CAE         ((uint32_t)0x00000004U)  /*!< CLUT access error    */
00199 #define HAL_DMA2D_ERROR_TIMEOUT     ((uint32_t)0x00000020U)  /*!< Timeout error        */
00200 /**
00201   * @}
00202   */
00203
00204 /** @defgroup DMA2D_Mode DMA2D Mode
00205   * @{
00206   */
00207 #define DMA2D_M2M                   ((uint32_t)0x00000000U)  /*!< DMA2D memory to memory transfer mode */
00208 #define DMA2D_M2M_PFC               DMA2D_CR_MODE_0          /*!< DMA2D memory to memory with pixel format conversion transfer mode */
00209 #define DMA2D_M2M_BLEND             DMA2D_CR_MODE_1          /*!< DMA2D memory to memory with blending transfer mode */
00210 #define DMA2D_R2M                   DMA2D_CR_MODE            /*!< DMA2D register to memory transfer mode */
00211 /**
00212   * @}
00213   */
00214
00215 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
00216   * @{
00217   */
00218 #define DMA2D_OUTPUT_ARGB8888       ((uint32_t)0x00000000U)               /*!< ARGB8888 DMA2D color mode */
00219 #define DMA2D_OUTPUT_RGB888         DMA2D_OPFCCR_CM_0                     /*!< RGB888 DMA2D color mode   */
00220 #define DMA2D_OUTPUT_RGB565         DMA2D_OPFCCR_CM_1                     /*!< RGB565 DMA2D color mode   */
00221 #define DMA2D_OUTPUT_ARGB1555       (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
00222 #define DMA2D_OUTPUT_ARGB4444       DMA2D_OPFCCR_CM_2                     /*!< ARGB4444 DMA2D color mode */
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
00228   * @{
00229   */
00230 #define DMA2D_INPUT_ARGB8888        ((uint32_t)0x00000000U)  /*!< ARGB8888 color mode */
00231 #define DMA2D_INPUT_RGB888          ((uint32_t)0x00000001U)  /*!< RGB888 color mode   */
00232 #define DMA2D_INPUT_RGB565          ((uint32_t)0x00000002U)  /*!< RGB565 color mode   */
00233 #define DMA2D_INPUT_ARGB1555        ((uint32_t)0x00000003U)  /*!< ARGB1555 color mode */
00234 #define DMA2D_INPUT_ARGB4444        ((uint32_t)0x00000004U)  /*!< ARGB4444 color mode */
00235 #define DMA2D_INPUT_L8              ((uint32_t)0x00000005U)  /*!< L8 color mode       */
00236 #define DMA2D_INPUT_AL44            ((uint32_t)0x00000006U)  /*!< AL44 color mode     */
00237 #define DMA2D_INPUT_AL88            ((uint32_t)0x00000007U)  /*!< AL88 color mode     */
00238 #define DMA2D_INPUT_L4              ((uint32_t)0x00000008U)  /*!< L4 color mode       */
00239 #define DMA2D_INPUT_A8              ((uint32_t)0x00000009U)  /*!< A8 color mode       */
00240 #define DMA2D_INPUT_A4              ((uint32_t)0x0000000AU)  /*!< A4 color mode       */
00241 #define DMA2D_INPUT_YCBCR           ((uint32_t)0x0000000BU)   /*!< YCbCr color mode */
00242 /**
00243   * @}
00244   */
00245
00246 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
00247   * @{
00248   */
00249 #define DMA2D_NO_MODIF_ALPHA        ((uint32_t)0x00000000U)  /*!< No modification of the alpha channel value */
00250 #define DMA2D_REPLACE_ALPHA         ((uint32_t)0x00000001U)  /*!< Replace original alpha channel value by programmed alpha value */
00251 #define DMA2D_COMBINE_ALPHA         ((uint32_t)0x00000002U)  /*!< Replace original alpha channel value by programmed alpha value
00252                                                                 with original alpha channel value                              */
00253 /**
00254   * @}
00255   */
00256
00257
00258 /** @defgroup DMA2D_Alpha_Inverted DMA2D ALPHA Inversion
00259   * @{
00260   */
00261 #define DMA2D_REGULAR_ALPHA         ((uint32_t)0x00000000U)  /*!< No modification of the alpha channel value */
00262 #define DMA2D_INVERTED_ALPHA        ((uint32_t)0x00000001U)  /*!< Invert the alpha channel value */
00263 /**
00264   * @}
00265   */
00266
00267
00268 /** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap
00269   * @{
00270   */
00271 #define DMA2D_RB_REGULAR            ((uint32_t)0x00000000U)  /*!< Select regular mode (RGB or ARGB) */
00272 #define DMA2D_RB_SWAP               ((uint32_t)0x00000001U)  /*!< Select swap mode (BGR or ABGR) */
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup DMA2D_Chroma_Sub_Sampling DMA2D Chroma Sub Sampling
00278   * @{
00279   */
00280 #define DMA2D_NO_CSS               ((uint32_t)0x00000000)  /*!< No chroma sub-sampling 4:4:4 */
00281 #define DMA2D_CSS_422              ((uint32_t)0x00000001)  /*!< chroma sub-sampling 4:2:2 */
00282 #define DMA2D_CSS_420              ((uint32_t)0x00000002)  /*!< chroma sub-sampling 4:2:0 */
00283 /**
00284   * @}
00285   */
00286
00287
00288 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
00289   * @{
00290   */
00291 #define DMA2D_CCM_ARGB8888          ((uint32_t)0x00000000U)  /*!< ARGB8888 DMA2D CLUT color mode */
00292 #define DMA2D_CCM_RGB888            ((uint32_t)0x00000001U)  /*!< RGB888 DMA2D CLUT color mode   */
00293 /**
00294   * @}
00295   */
00296
00297
00298 /** @defgroup DMA2D_Interrupts DMA2D Interrupts
00299   * @{
00300   */
00301 #define DMA2D_IT_CE                 DMA2D_CR_CEIE            /*!< Configuration Error Interrupt */
00302 #define DMA2D_IT_CTC                DMA2D_CR_CTCIE           /*!< CLUT Transfer Complete Interrupt */
00303 #define DMA2D_IT_CAE                DMA2D_CR_CAEIE           /*!< CLUT Access Error Interrupt */
00304 #define DMA2D_IT_TW                 DMA2D_CR_TWIE            /*!< Transfer Watermark Interrupt */
00305 #define DMA2D_IT_TC                 DMA2D_CR_TCIE            /*!< Transfer Complete Interrupt */
00306 #define DMA2D_IT_TE                 DMA2D_CR_TEIE            /*!< Transfer Error Interrupt */
00307 /**
00308   * @}
00309   */
00310
00311 /** @defgroup DMA2D_Flags DMA2D Flags
00312   * @{
00313   */
00314 #define DMA2D_FLAG_CE               DMA2D_ISR_CEIF           /*!< Configuration Error Interrupt Flag */
00315 #define DMA2D_FLAG_CTC              DMA2D_ISR_CTCIF          /*!< CLUT Transfer Complete Interrupt Flag */
00316 #define DMA2D_FLAG_CAE              DMA2D_ISR_CAEIF          /*!< CLUT Access Error Interrupt Flag */
00317 #define DMA2D_FLAG_TW               DMA2D_ISR_TWIF           /*!< Transfer Watermark Interrupt Flag */
00318 #define DMA2D_FLAG_TC               DMA2D_ISR_TCIF           /*!< Transfer Complete Interrupt Flag */
00319 #define DMA2D_FLAG_TE               DMA2D_ISR_TEIF           /*!< Transfer Error Interrupt Flag */
00320 /**
00321   * @}
00322   */
00323
00324 /** @defgroup DMA2D_Aliases DMA2D API Aliases
00325   * @{
00326   */
00327 #define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
00328 /**
00329   * @}
00330   */
00331
00332
00333 /**
00334   * @}
00335   */
00336 /* Exported macros ------------------------------------------------------------*/
00337 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
00338   * @{
00339   */
00340
00341 /** @brief Reset DMA2D handle state
00342   * @param  __HANDLE__: specifies the DMA2D handle.
00343   * @retval None
00344   */
00345 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
00346
00347 /**
00348   * @brief  Enable the DMA2D.
00349   * @param  __HANDLE__: DMA2D handle
00350   * @retval None.
00351   */
00352 #define __HAL_DMA2D_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
00353
00354
00355 /* Interrupt & Flag management */
00356 /**
00357   * @brief  Get the DMA2D pending flags.
00358   * @param  __HANDLE__: DMA2D handle
00359   * @param  __FLAG__: flag to check.
00360   *          This parameter can be any combination of the following values:
00361   *            @arg DMA2D_FLAG_CE:  Configuration error flag
00362   *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
00363   *            @arg DMA2D_FLAG_CAE: CLUT access error flag
00364   *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
00365   *            @arg DMA2D_FLAG_TC:  Transfer complete flag
00366   *            @arg DMA2D_FLAG_TE:  Transfer error flag
00367   * @retval The state of FLAG.
00368   */
00369 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
00370
00371 /**
00372   * @brief  Clear the DMA2D pending flags.
00373   * @param  __HANDLE__: DMA2D handle
00374   * @param  __FLAG__: specifies the flag to clear.
00375   *          This parameter can be any combination of the following values:
00376   *            @arg DMA2D_FLAG_CE:  Configuration error flag
00377   *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
00378   *            @arg DMA2D_FLAG_CAE: CLUT access error flag
00379   *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
00380   *            @arg DMA2D_FLAG_TC:  Transfer complete flag
00381   *            @arg DMA2D_FLAG_TE:  Transfer error flag
00382   * @retval None
00383   */
00384 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
00385
00386 /**
00387   * @brief  Enable the specified DMA2D interrupts.
00388   * @param  __HANDLE__: DMA2D handle
00389   * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
00390   *          This parameter can be any combination of the following values:
00391   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
00392   *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
00393   *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
00394   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
00395   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
00396   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
00397   * @retval None
00398   */
00399 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00400
00401 /**
00402   * @brief  Disable the specified DMA2D interrupts.
00403   * @param  __HANDLE__: DMA2D handle
00404   * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
00405   *          This parameter can be any combination of the following values:
00406   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
00407   *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
00408   *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
00409   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
00410   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
00411   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
00412   * @retval None
00413   */
00414 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00415
00416 /**
00417   * @brief  Check whether the specified DMA2D interrupt source is enabled or not.
00418   * @param  __HANDLE__: DMA2D handle
00419   * @param  __INTERRUPT__: specifies the DMA2D interrupt source to check.
00420   *          This parameter can be one of the following values:
00421   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
00422   *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
00423   *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
00424   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
00425   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
00426   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
00427   * @retval The state of INTERRUPT source.
00428   */
00429 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
00430
00431 /**
00432   * @}
00433   */
00434
00435 /* Exported functions --------------------------------------------------------*/
00436 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
00437   * @{
00438   */
00439
00440 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
00441   * @{
00442   */
00443
00444 /* Initialization and de-initialization functions *******************************/
00445 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
00446 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
00447 void              HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
00448 void              HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
00449
00450 /**
00451   * @}
00452   */
00453
00454
00455 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
00456   * @{
00457   */
00458
00459 /* IO operation functions *******************************************************/
00460 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
00461 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height);
00462 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
00463 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
00464 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
00465 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
00466 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
00467 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
00468 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
00469 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
00470 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
00471 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
00472 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
00473 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
00474 void              HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
00475 void              HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
00476 void              HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
00477
00478 /**
00479   * @}
00480   */
00481
00482 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
00483   * @{
00484   */
00485
00486 /* Peripheral Control functions *************************************************/
00487 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
00488 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
00489 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
00490 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
00491 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
00492 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
00493
00494 /**
00495   * @}
00496   */
00497
00498 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
00499   * @{
00500   */
00501
00502 /* Peripheral State functions ***************************************************/
00503 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
00504 uint32_t               HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
00505
00506 /**
00507   * @}
00508   */
00509
00510 /**
00511   * @}
00512   */
00513
00514 /* Private constants ---------------------------------------------------------*/
00515
00516 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
00517   * @{
00518   */
00519
00520 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
00521   * @{
00522   */
00523 #define DMA2D_LINE_WATERMARK_MAX            DMA2D_LWR_LW       /*!< DMA2D maximum line watermark */
00524 /**
00525   * @}
00526   */
00527
00528 /** @defgroup DMA2D_Color_Value DMA2D Color Value
00529   * @{
00530   */
00531 #define DMA2D_COLOR_VALUE                 ((uint32_t)0x000000FFU)  /*!< Color value mask */
00532 /**
00533   * @}
00534   */
00535
00536 /** @defgroup DMA2D_Offset DMA2D Offset
00537   * @{
00538   */
00539 #define DMA2D_OFFSET                DMA2D_FGOR_LO            /*!< maximum Line Offset */
00540 /**
00541   * @}
00542   */
00543
00544 /** @defgroup DMA2D_Size DMA2D Size
00545   * @{
00546   */
00547 #define DMA2D_PIXEL                 (DMA2D_NLR_PL >> 16U)    /*!< DMA2D maximum number of pixels per line */
00548 #define DMA2D_LINE                  DMA2D_NLR_NL             /*!< DMA2D maximum number of lines           */
00549 /**
00550   * @}
00551   */
00552
00553 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
00554   * @{
00555   */
00556 #define DMA2D_CLUT_SIZE             (DMA2D_FGPFCCR_CS >> 8)  /*!< DMA2D maximum CLUT size */
00557 /**
00558   * @}
00559   */
00560
00561 /**
00562   * @}
00563   */
00564
00565
00566 /* Private macros ------------------------------------------------------------*/
00567 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros
00568   * @{
00569   */
00570 #define IS_DMA2D_LAYER(LAYER)                 ((LAYER) <= MAX_DMA2D_LAYER)
00571 #define IS_DMA2D_MODE(MODE)                   (((MODE) == DMA2D_M2M)       || ((MODE) == DMA2D_M2M_PFC) || \
00572                                                ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
00573 #define IS_DMA2D_CMODE(MODE_ARGB)             (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888)   || \
00574                                                ((MODE_ARGB) == DMA2D_OUTPUT_RGB565)   || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
00575                                                ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
00576 #define IS_DMA2D_COLOR(COLOR)                 ((COLOR) <= DMA2D_COLOR_VALUE)
00577 #define IS_DMA2D_LINE(LINE)                   ((LINE) <= DMA2D_LINE)
00578 #define IS_DMA2D_PIXEL(PIXEL)                 ((PIXEL) <= DMA2D_PIXEL)
00579 #define IS_DMA2D_OFFSET(OOFFSET)              ((OOFFSET) <= DMA2D_OFFSET)
00580 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM)   (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888)   || \
00581                                                ((INPUT_CM) == DMA2D_INPUT_RGB565)   || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
00582                                                ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8)       || \
00583                                                ((INPUT_CM) == DMA2D_INPUT_AL44)     || ((INPUT_CM) == DMA2D_INPUT_AL88)     || \
00584                                                ((INPUT_CM) == DMA2D_INPUT_L4)       || ((INPUT_CM) == DMA2D_INPUT_A8)       || \
00585                                                ((INPUT_CM) == DMA2D_INPUT_A4)       || ((INPUT_CM) == DMA2D_INPUT_YCBCR))
00586 #define IS_DMA2D_ALPHA_MODE(AlphaMode)        (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
00587                                                ((AlphaMode) == DMA2D_REPLACE_ALPHA)  || \
00588                                                ((AlphaMode) == DMA2D_COMBINE_ALPHA))
00589
00590 #define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
00591                                                  ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
00592
00593 #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
00594                                    ((RB_Swap) == DMA2D_RB_SWAP))
00595
00596 #define IS_DMA2D_CHROMA_SUB_SAMPLING (CSS) (((CSS) == DMA2D_NO_CSS) || \
00597                                             ((CSS) == DMA2D_CSS_422) || \
00598                                             ((CSS) == DMA2D_CSS_420))
00599
00600 #define IS_DMA2D_CLUT_CM(CLUT_CM)             (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
00601 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE)         ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
00602 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
00603 #define IS_DMA2D_IT(IT)                       (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
00604                                                ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
00605                                                ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
00606 #define IS_DMA2D_GET_FLAG(FLAG)               (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
00607                                                ((FLAG) == DMA2D_FLAG_TW)   || ((FLAG) == DMA2D_FLAG_TC)  || \
00608                                                ((FLAG) == DMA2D_FLAG_TE)   || ((FLAG) == DMA2D_FLAG_CE))
00609 /**
00610   * @}
00611   */
00612
00613 /**
00614   * @}
00615   */
00616
00617 /**
00618   * @}
00619   */
00620
00621
00622 #ifdef __cplusplus
00623 }
00624 #endif
00625
00626 #endif /* __STM32H7xx_HAL_DMA2D_H */
00627
00628
00629 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dma.c Source File

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stm32h7xx_hal_dma.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dma.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   DMA HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Direct Memory Access (DMA) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral State and errors functions
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017   [..]
00018    (#) Enable and configure the peripheral to be connected to the DMA Stream
00019        (except for internal SRAM/FLASH memories: no initialization is
00020        necessary) please refer to Reference manual for connection between peripherals
00021        and DMA requests .
00022
00023    (#) For a given Stream, program the required configuration through the following parameters:
00024        Transfer Direction, Source and Destination data formats,
00025        Circular, Normal or peripheral flow control mode, Stream Priority level,
00026        Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
00027        Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
00028
00029      *** Polling mode IO operation ***
00030      =================================
00031     [..]
00032           (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
00033               address and destination address and the Length of data to be transferred
00034           (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
00035               case a fixed Timeout can be configured by User depending from his application.
00036
00037      *** Interrupt mode IO operation ***
00038      ===================================
00039     [..]
00040           (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
00041           (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
00042           (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
00043               Source address and destination address and the Length of data to be transferred. In this
00044               case the DMA interrupt is configured
00045           (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
00046           (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
00047               add his own function by customization of function pointer XferCpltCallback and
00048               XferErrorCallback (i.e a member of DMA handle structure).
00049     [..]
00050      (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
00051          detection.
00052
00053      (#) Use HAL_DMA_Abort() function to abort the current transfer
00054
00055      -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
00056
00057      -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
00058            possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
00059            Half-Word data size for the peripheral to access its data register and set Word data size
00060            for the Memory to gain in access time. Each two half words will be packed and written in
00061            a single access to a Word in the Memory).
00062
00063      -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
00064            and Destination. In this case the Peripheral Data Size will be applied to both Source
00065            and Destination.
00066
00067      *** DMA HAL driver macros list ***
00068      =============================================
00069      [..]
00070        Below the list of most used macros in DMA HAL driver.
00071
00072       (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
00073       (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
00074       (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
00075       (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
00076       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
00077       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
00078
00079      [..]
00080       (@) You can refer to the DMA HAL driver header file for more useful macros.
00081
00082   @endverbatim
00083   ******************************************************************************
00084   * @attention
00085   *
00086   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00087   *
00088   * Redistribution and use in source and binary forms, with or without modification,
00089   * are permitted provided that the following conditions are met:
00090   *   1. Redistributions of source code must retain the above copyright notice,
00091   *      this list of conditions and the following disclaimer.
00092   *   2. Redistributions in binary form must reproduce the above copyright notice,
00093   *      this list of conditions and the following disclaimer in the documentation
00094   *      and/or other materials provided with the distribution.
00095   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00096   *      may be used to endorse or promote products derived from this software
00097   *      without specific prior written permission.
00098   *
00099   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00100   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00101   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00102   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00103   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00104   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00105   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00106   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00107   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00108   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00109   *
00110   ******************************************************************************
00111   */
00112
00113 /* Includes ------------------------------------------------------------------*/
00114 #include "stm32h7xx_hal.h"
00115
00116 /** @addtogroup STM32H7xx_HAL_Driver
00117   * @{
00118   */
00119
00120 /** @defgroup DMA DMA
00121   * @brief DMA HAL module driver
00122   * @{
00123   */
00124
00125 #ifdef HAL_DMA_MODULE_ENABLED
00126
00127 /* Private types -------------------------------------------------------------*/
00128 typedef struct
00129 {
00130   __IO uint32_t ISR;   /*!< DMA interrupt status register */
00131   __IO uint32_t Reserved0;
00132   __IO uint32_t IFCR;  /*!< DMA interrupt flag clear register */
00133 } DMA_Base_Registers;
00134
00135 /* Private variables ---------------------------------------------------------*/
00136 /* Private constants ---------------------------------------------------------*/
00137 /** @addtogroup DMA_Private_Constants
00138  * @{
00139  */
00140  #define HAL_TIMEOUT_DMA_ABORT    (5U)  /* 5 ms */
00141
00142 /*D2 DMA to D3 DMA conversion*/
00143 #define BDMA_PERIPH_TO_MEMORY         (0x00000000U)        /*!< Peripheral to memory direction */
00144 #define BDMA_MEMORY_TO_PERIPH         ((uint32_t)BDMA_CCR_DIR)       /*!< Memory to peripheral direction */
00145 #define BDMA_MEMORY_TO_MEMORY         ((uint32_t)BDMA_CCR_MEM2MEM) /*!< Memory to memory direction     */
00146
00147 #define D2_TO_D3_DMA_DIRECTION(__D2_DMA_DIRECTION__) (((__D2_DMA_DIRECTION__)== DMA_MEMORY_TO_PERIPH)? BDMA_MEMORY_TO_PERIPH: \
00148                                                       ((__D2_DMA_DIRECTION__)== DMA_MEMORY_TO_MEMORY)? BDMA_MEMORY_TO_MEMORY: \
00149                                                        BDMA_PERIPH_TO_MEMORY)
00150
00151 #define D2_TO_D3_DMA_PERIPHERAL_INC(__D2_PERIPHERAL_INC__) ((__D2_PERIPHERAL_INC__) >> 3U)
00152 #define D2_TO_D3_DMA_MEMORY_INC(__D2_MEMORY_INC__)         ((__D2_MEMORY_INC__) >> 3U)
00153
00154 #define D2_TO_D3_DMA_PDATA_SIZE(__D2_PDATA_SIZE__) ((__D2_PDATA_SIZE__) >> 3U)
00155 #define D2_TO_D3_DMA_MDATA_SIZE(__D2_MDATA_SIZE__) ((__D2_MDATA_SIZE__) >> 3U)
00156
00157 /*BDMA doesn't support Peripheral flow control mode , force to normal in this case  */
00158 #define D2_TO_D3_DMA_MODE(__D2_MODE__) (((__D2_MODE__) >> 3U) & BDMA_CCR_CIRC)
00159
00160 #define D2_TO_D3_DMA_PRIORITY(__D2_PRIORITY__) ((__D2_PRIORITY__) >> 4U)
00161
00162 /**
00163   * @}
00164   */
00165 /* Private macros ------------------------------------------------------------*/
00166 /* Private functions ---------------------------------------------------------*/
00167 /** @addtogroup DMA_Private_Functions
00168   * @{
00169   */
00170 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00171 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
00172 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
00173 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
00174 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
00175
00176 /**
00177   * @}
00178   */
00179
00180 /* Exported functions ---------------------------------------------------------*/
00181 /** @addtogroup DMA_Exported_Functions
00182   * @{
00183   */
00184
00185 /** @addtogroup DMA_Exported_Functions_Group1
00186   *
00187 @verbatim
00188  ===============================================================================
00189              ##### Initialization and de-initialization functions  #####
00190  ===============================================================================
00191     [..]
00192     This section provides functions allowing to initialize the DMA Stream source
00193     and destination incrementation and data sizes, transfer direction,
00194     circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
00195     [..]
00196     The HAL_DMA_Init() function follows the DMA configuration procedures as described in
00197     reference manual.
00198     The HAL_DMA_DeInit function allows to deinitialize the DMA stream.
00199
00200 @endverbatim
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Initialize the DMA according to the specified
00206   *         parameters in the DMA_InitTypeDef and create the associated handle.
00207   * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
00208   *               the configuration information for the specified DMA Stream.
00209   * @retval HAL status
00210   */
00211 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
00212 {
00213   uint32_t registerValue = 0U;
00214   uint32_t tickstart = HAL_GetTick();
00215   DMA_Base_Registers *regs = NULL;
00216
00217   /* Check the DMA peripheral handle */
00218   if(hdma == NULL)
00219   {
00220     return HAL_ERROR;
00221   }
00222
00223   /* Check the parameters */
00224   assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
00225   assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
00226   assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
00227   assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
00228   assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
00229   assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
00230   assert_param(IS_DMA_MODE(hdma->Init.Mode));
00231   assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
00232
00233   if(IS_D2_DMA_INSTANCE(hdma) != RESET) /*DMA2/DMA1 stream , D2 domain*/
00234   {
00235
00236     assert_param(IS_DMA_D2_REQUEST(hdma->Init.Request));
00237     assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
00238     /* Check the memory burst, peripheral burst and FIFO threshold parameters only
00239        when FIFO mode is enabled */
00240     if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
00241     {
00242       assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
00243       assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
00244       assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
00245     }
00246
00247     /* Allocate lock resource */
00248     __HAL_UNLOCK(hdma);
00249
00250     /* Change DMA peripheral state */
00251     hdma->State = HAL_DMA_STATE_BUSY;
00252
00253     /* Disable the peripheral */
00254     __HAL_DMA_DISABLE(hdma);
00255
00256     /* Check if the DMA Stream is effectively disabled */
00257     while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != RESET)
00258     {
00259       /* Check for the Timeout */
00260       if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
00261       {
00262         /* Update error code */
00263         hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
00264
00265         /* Change the DMA state */
00266         hdma->State = HAL_DMA_STATE_ERROR;
00267
00268         return HAL_ERROR;
00269       }
00270     }
00271
00272     /* Get the CR register value */
00273     registerValue = ((DMA_Stream_TypeDef   *)hdma->Instance)->CR;
00274
00275     /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
00276     registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
00277                         DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
00278                         DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \
00279                         DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));
00280
00281     /* Prepare the DMA Stream configuration */
00282     registerValue |=  hdma->Init.Direction           |
00283             hdma->Init.PeriphInc           | hdma->Init.MemInc           |
00284             hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
00285             hdma->Init.Mode                | hdma->Init.Priority;
00286
00287     /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
00288     if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
00289     {
00290       /* Get memory burst and peripheral burst */
00291       registerValue |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;
00292     }
00293
00294     /* Write to DMA Stream CR register */
00295     ((DMA_Stream_TypeDef   *)hdma->Instance)->CR = registerValue;
00296
00297     /* Get the FCR register value */
00298     registerValue = ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR;
00299
00300     /* Clear Direct mode and FIFO threshold bits */
00301     registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
00302
00303     /* Prepare the DMA Stream FIFO configuration */
00304     registerValue |= hdma->Init.FIFOMode;
00305
00306     /* the FIFO threshold is not used when the FIFO mode is disabled */
00307     if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
00308     {
00309       /* Get the FIFO threshold */
00310       registerValue |= hdma->Init.FIFOThreshold;
00311
00312       /* Check compatibility between FIFO threshold level and size of the memory burst */
00313       /* for INCR4, INCR8, INCR16 */
00314       if(hdma->Init.MemBurst != DMA_MBURST_SINGLE)
00315       {
00316         if (DMA_CheckFifoParam(hdma) != HAL_OK)
00317         {
00318           /* Update error code */
00319           hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
00320
00321           /* Change the DMA state */
00322           hdma->State = HAL_DMA_STATE_READY;
00323
00324           return HAL_ERROR;
00325         }
00326       }
00327     }
00328
00329     /* Write to DMA Stream FCR */
00330     ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR = registerValue;
00331
00332     /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
00333        DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
00334     regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
00335
00336     /* Clear all interrupt flags */
00337     regs->IFCR = 0x3FU << hdma->StreamIndex;
00338   }
00339   else if(IS_D3_DMA_INSTANCE(hdma) != RESET) /*<BDMA channel , D3 domain*/
00340   {
00341     /* Check the request parameter */
00342     assert_param(IS_BDMA_D3_REQUEST(hdma->Init.Request));
00343
00344     /* Allocate lock resource */
00345     __HAL_UNLOCK(hdma);
00346
00347     /* Change DMA peripheral state */
00348     hdma->State = HAL_DMA_STATE_BUSY;
00349
00350     /* Get the CR register value */
00351     registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR;
00352
00353     /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
00354     registerValue &= ((uint32_t)~(BDMA_CCR_PL    | BDMA_CCR_MSIZE  | BDMA_CCR_PSIZE  | \
00355                                   BDMA_CCR_MINC  | BDMA_CCR_PINC   | BDMA_CCR_CIRC   | \
00356                                   BDMA_CCR_DIR));
00357
00358     /* Prepare the DMA Channel configuration */
00359     registerValue |=  D2_TO_D3_DMA_DIRECTION(hdma->Init.Direction)            |
00360                       D2_TO_D3_DMA_PERIPHERAL_INC(hdma->Init.PeriphInc)       |
00361                       D2_TO_D3_DMA_MEMORY_INC(hdma->Init.MemInc)              |
00362                       D2_TO_D3_DMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) |
00363                       D2_TO_D3_DMA_MDATA_SIZE(hdma->Init.MemDataAlignment)    |
00364                       D2_TO_D3_DMA_MODE(hdma->Init.Mode)                      |
00365                       D2_TO_D3_DMA_PRIORITY(hdma->Init.Priority);
00366
00367     /* Write to DMA Channel CR register */
00368     ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue;
00369
00370     /* calculation of the channel index */
00371     hdma->StreamIndex = (((uint32_t)hdma->Instance - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U;
00372
00373   }
00374   else
00375   {
00376     hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
00377     hdma->State     = HAL_DMA_STATE_ERROR;
00378
00379     return HAL_ERROR;
00380   }
00381
00382   /* Initialize parameters for DMAMUX channel :
00383      DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
00384   */
00385   DMA_CalcDMAMUXChannelBaseAndMask(hdma);
00386
00387   if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
00388   {
00389      /* if memory to memory force the request to 0*/
00390      hdma->Init.Request = DMA_REQUEST_MEM2MEM;
00391   }
00392
00393
00394   /* Set peripheral request  to DMAMUX channel */
00395   hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
00396
00397   /* Clear the DMAMUX synchro overrun flag */
00398   hdma->DMAmuxChannelStatus->CFR |= hdma->DMAmuxChannelStatusMask;
00399
00400   /* Initialize parameters for DMAMUX request generator :
00401      if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7
00402   */
00403
00404   if(((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) || \
00405     ((hdma->Init.Request >= BDMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= BDMA_REQUEST_GENERATOR7)))
00406   {
00407      /* Initialize parameters for DMAMUX request generator :
00408         DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
00409      */
00410     DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
00411
00412     /* Reset the DMAMUX request generator register*/
00413      hdma->DMAmuxRequestGen->RGCR = 0U;
00414
00415     /* Clear the DMAMUX request generator overrun flag */
00416     hdma->DMAmuxRequestGenStatus->RGCFR |= hdma->DMAmuxRequestGenStatusMask;
00417   }
00418   else
00419   {
00420     hdma->DMAmuxRequestGen = 0U;
00421     hdma->DMAmuxRequestGenStatus = 0U;
00422     hdma->DMAmuxRequestGenStatusMask = 0U;
00423   }
00424
00425   /* Initialize the error code */
00426   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00427
00428   /* Initialize the DMA state */
00429   hdma->State = HAL_DMA_STATE_READY;
00430
00431   return HAL_OK;
00432 }
00433
00434 /**
00435   * @brief  DeInitializes the DMA peripheral
00436   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00437   *               the configuration information for the specified DMA Stream.
00438   * @retval HAL status
00439   */
00440 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
00441 {
00442   DMA_Base_Registers *regs = NULL;
00443
00444   /* Check the DMA peripheral handle */
00445   if(hdma == NULL)
00446   {
00447     return HAL_ERROR;
00448   }
00449
00450   /* Check the DMA peripheral state */
00451   if(hdma->State == HAL_DMA_STATE_BUSY)
00452   {
00453     /* Return error status */
00454     return HAL_BUSY;
00455   }
00456
00457   /* Disable the selected DMA Streamx */
00458   __HAL_DMA_DISABLE(hdma);
00459
00460   if(IS_D2_DMA_INSTANCE(hdma) != RESET) /*DMA2/DMA1 stream , D2 domain*/
00461   {
00462     /* Reset DMA Streamx control register */
00463     ((DMA_Stream_TypeDef   *)hdma->Instance)->CR   = 0U;
00464
00465     /* Reset DMA Streamx number of data to transfer register */
00466     ((DMA_Stream_TypeDef   *)hdma->Instance)->NDTR = 0U;
00467
00468     /* Reset DMA Streamx peripheral address register */
00469     ((DMA_Stream_TypeDef   *)hdma->Instance)->PAR  = 0U;
00470
00471     /* Reset DMA Streamx memory 0 address register */
00472     ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = 0U;
00473
00474     /* Reset DMA Streamx memory 1 address register */
00475     ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = 0U;
00476
00477     /* Reset DMA Streamx FIFO control register */
00478     ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR  = (uint32_t)0x00000021U;
00479
00480     /* Get DMA steam Base Address */
00481     regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
00482
00483     /* Clear all interrupt flags at correct offset within the register */
00484     regs->IFCR = 0x3FU << hdma->StreamIndex;
00485   }
00486   else if(IS_D3_DMA_INSTANCE(hdma) != RESET) /*D3 domain BDMA*/
00487   {
00488
00489     /* Reset DMA Channel control register */
00490     ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR  = 0U;
00491
00492     /* Reset DMA Channel Number of Data to Transfer register */
00493     ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = 0U;
00494
00495     /* Reset DMA Channel peripheral address register */
00496     ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR  = 0U;
00497
00498     /* Reset DMA Channel memory address register */
00499     ((BDMA_Channel_TypeDef *)hdma->Instance)->CMAR = 0U;
00500
00501     /* Clear all flags */
00502     BDMA->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex));
00503   }
00504
00505   if(hdma->DMAmuxChannel != 0U)
00506   {
00507     /* Resett he DMAMUX channel that corresponds to the DMA stream */
00508     hdma->DMAmuxChannel->CCR = 0U;
00509
00510     /* Clear the DMAMUX synchro overrun flag */
00511     hdma->DMAmuxChannelStatus->CFR |= hdma->DMAmuxChannelStatusMask;
00512   }
00513
00514   /*Reset Request generator parameters if any*/
00515   if(hdma->DMAmuxRequestGen != 0U)
00516   {
00517     /* Reset the DMAMUX request generator register*/
00518     hdma->DMAmuxRequestGen->RGCR = 0U;
00519
00520     /* Clear the DMAMUX request generator overrun flag */
00521     hdma->DMAmuxRequestGenStatus->RGCFR |= hdma->DMAmuxRequestGenStatusMask;
00522   }
00523
00524   hdma->DMAmuxRequestGen = 0U;
00525   hdma->DMAmuxRequestGenStatus = 0U;
00526   hdma->DMAmuxRequestGenStatusMask = 0U;
00527
00528   /* Initialize the error code */
00529   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00530
00531   /* Initialize the DMA state */
00532   hdma->State = HAL_DMA_STATE_RESET;
00533
00534   /* Release Lock */
00535   __HAL_UNLOCK(hdma);
00536
00537   return HAL_OK;
00538 }
00539
00540 /**
00541   * @}
00542   */
00543
00544 /** @addtogroup DMA_Exported_Functions_Group2
00545   *
00546 @verbatim
00547  ===============================================================================
00548                       #####  IO operation functions  #####
00549  ===============================================================================
00550     [..]  This section provides functions allowing to:
00551       (+) Configure the source, destination address and data length and Start DMA transfer
00552       (+) Configure the source, destination address and data length and
00553           Start DMA transfer with interrupt
00554       (+) Register and Unregister DMA callbacks
00555       (+) Abort DMA transfer
00556       (+) Poll for transfer complete
00557       (+) Handle DMA interrupt request
00558
00559 @endverbatim
00560   * @{
00561   */
00562
00563 /**
00564   * @brief  Starts the DMA Transfer.
00565   * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
00566   *                     the configuration information for the specified DMA Stream.
00567   * @param  SrcAddress: The source memory Buffer address
00568   * @param  DstAddress: The destination memory Buffer address
00569   * @param  DataLength: The length of data to be transferred from source to destination
00570   * @retval HAL status
00571   */
00572 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00573 {
00574   HAL_StatusTypeDef status = HAL_OK;
00575
00576   /* Check the parameters */
00577   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00578
00579   /* Check the DMA peripheral handle */
00580   if(hdma == NULL)
00581   {
00582     return HAL_ERROR;
00583   }
00584
00585   /* Process locked */
00586   __HAL_LOCK(hdma);
00587
00588   if(HAL_DMA_STATE_READY == hdma->State)
00589   {
00590     /* Change DMA peripheral state */
00591     hdma->State = HAL_DMA_STATE_BUSY;
00592
00593     /* Initialize the error code */
00594     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00595
00596     /* Disable the peripheral */
00597     __HAL_DMA_DISABLE(hdma);
00598
00599     /* Configure the source, destination address and the data length */
00600     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
00601
00602     /* Enable the Peripheral */
00603     __HAL_DMA_ENABLE(hdma);
00604   }
00605   else
00606   {
00607     /* Process unlocked */
00608     __HAL_UNLOCK(hdma);
00609
00610     /* Return error status */
00611     status = HAL_BUSY;
00612   }
00613   return status;
00614 }
00615
00616 /**
00617   * @brief  Start the DMA Transfer with interrupt enabled.
00618   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00619   *                     the configuration information for the specified DMA Stream.
00620   * @param  SrcAddress: The source memory Buffer address
00621   * @param  DstAddress: The destination memory Buffer address
00622   * @param  DataLength: The length of data to be transferred from source to destination
00623   * @retval HAL status
00624   */
00625 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00626 {
00627   HAL_StatusTypeDef status = HAL_OK;
00628
00629   /* Check the parameters */
00630   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00631
00632   /* Check the DMA peripheral handle */
00633   if(hdma == NULL)
00634   {
00635     return HAL_ERROR;
00636   }
00637
00638   /* Process locked */
00639   __HAL_LOCK(hdma);
00640
00641   if(HAL_DMA_STATE_READY == hdma->State)
00642   {
00643     /* Change DMA peripheral state */
00644     hdma->State = HAL_DMA_STATE_BUSY;
00645
00646     /* Initialize the error code */
00647     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00648
00649     /* Disable the peripheral */
00650     __HAL_DMA_DISABLE(hdma);
00651
00652     /* Configure the source, destination address and the data length */
00653     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
00654
00655     if(IS_D2_DMA_INSTANCE(hdma) != RESET) /* D2 Domain DMA : DMA1 or DMA2 */
00656     {
00657       /* Enable Common interrupts*/
00658       MODIFY_REG(((DMA_Stream_TypeDef   *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
00659       ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR |= DMA_IT_FE;
00660
00661       if(hdma->XferHalfCpltCallback != NULL)
00662       {
00663         /*Enable Half Transfer IT if corresponding Callback is set*/
00664         ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  |= DMA_IT_HT;
00665       }
00666     }
00667     else /* D3 Domain BDMA */
00668     {
00669       /* Enable Common interrupts*/
00670       MODIFY_REG(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));
00671
00672       if(hdma->XferHalfCpltCallback != NULL)
00673       {
00674         /*Enable Half Transfer IT if corresponding Callback is set*/
00675         ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  |= BDMA_CCR_HTIE;
00676       }
00677     }
00678
00679     /* Check if DMAMUX Synchronization is enabled*/
00680     if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
00681     {
00682       /* Enable DMAMUX sync overrun IT*/
00683       hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
00684     }
00685
00686     if(hdma->DMAmuxRequestGen != 0U)
00687     {
00688       /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
00689       /* enable the request gen overrun IT*/
00690       hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
00691
00692     }
00693
00694     /* Enable the Peripheral */
00695     __HAL_DMA_ENABLE(hdma);
00696   }
00697   else
00698   {
00699     /* Process unlocked */
00700     __HAL_UNLOCK(hdma);
00701
00702     /* Return error status */
00703     status = HAL_BUSY;
00704   }
00705
00706   return status;
00707 }
00708
00709 /**
00710   * @brief  Aborts the DMA Transfer.
00711   * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
00712   *                 the configuration information for the specified DMA Stream.
00713   *
00714   * @note  After disabling a DMA Stream, a check for wait until the DMA Stream is
00715   *        effectively disabled is added. If a Stream is disabled
00716   *        while a data transfer is ongoing, the current data will be transferred
00717   *        and the Stream will be effectively disabled only after the transfer of
00718   *        this single data is finished.
00719   * @retval HAL status
00720   */
00721 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
00722 {
00723   /* calculate DMA base and stream number */
00724   DMA_Base_Registers *regs = NULL;
00725   __IO uint32_t *enableRegister = NULL;
00726
00727   uint32_t tickstart = HAL_GetTick();
00728
00729  /* Check the DMA peripheral handle */
00730   if(hdma == NULL)
00731   {
00732     return HAL_ERROR;
00733   }
00734
00735   /* Check the DMA peripheral state */
00736   if(hdma->State != HAL_DMA_STATE_BUSY)
00737   {
00738     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00739
00740     /* Process Unlocked */
00741     __HAL_UNLOCK(hdma);
00742
00743     return HAL_ERROR;
00744   }
00745   else
00746   {
00747     /* Disable all the transfer interrupts */
00748     if(IS_D2_DMA_INSTANCE(hdma) != RESET) /* D2 Domain DMA : DMA1 or DMA2*/
00749     {
00750        /* Disable DMA All Interrupts  */
00751       ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
00752       ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
00753
00754       regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
00755       enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef   *)hdma->Instance)->CR));
00756     }
00757     else /* D3 domain BDMA*/
00758     {
00759       /* Disable DMA All Interrupts  */
00760       ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
00761
00762       enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR));
00763     }
00764
00765     /* disable the DMAMUX sync overrun IT*/
00766     hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
00767
00768     /* Disable the stream */
00769     __HAL_DMA_DISABLE(hdma);
00770
00771     /* Check if the DMA Stream is effectively disabled */
00772     while(((*enableRegister) & DMA_SxCR_EN) != RESET)
00773     {
00774       /* Check for the Timeout */
00775       if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
00776       {
00777         /* Update error code */
00778         hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
00779
00780         /* Process Unlocked */
00781         __HAL_UNLOCK(hdma);
00782
00783         /* Change the DMA state */
00784         hdma->State = HAL_DMA_STATE_ERROR;
00785
00786         return HAL_ERROR;
00787       }
00788     }
00789
00790     /* Clear all interrupt flags at correct offset within the register */
00791     if(IS_D2_DMA_INSTANCE(hdma) != RESET) /* D2 Domain DMA : DMA1 or DMA2*/
00792     {
00793       regs->IFCR = 0x3FU << hdma->StreamIndex;
00794     }
00795     else /* D3 domain BDMA*/
00796     {
00797       BDMA->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex));
00798     }
00799
00800     /* Clear the DMAMUX synchro overrun flag */
00801     hdma->DMAmuxChannelStatus->CFR |= hdma->DMAmuxChannelStatusMask;
00802
00803     if(hdma->DMAmuxRequestGen != 0U)
00804     {
00805       /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
00806       /* disable the request gen overrun IT*/
00807       hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
00808
00809       /* Clear the DMAMUX request generator overrun flag */
00810       hdma->DMAmuxRequestGenStatus->RGCFR |= hdma->DMAmuxRequestGenStatusMask;
00811     }
00812
00813     /* Process Unlocked */
00814     __HAL_UNLOCK(hdma);
00815
00816     /* Change the DMA state*/
00817     hdma->State = HAL_DMA_STATE_READY;
00818   }
00819   return HAL_OK;
00820 }
00821
00822 /**
00823   * @brief  Aborts the DMA Transfer in Interrupt mode.
00824   * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
00825   *                 the configuration information for the specified DMA Stream.
00826   * @retval HAL status
00827   */
00828 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
00829 {
00830   /* Check the DMA peripheral handle */
00831   if(hdma == NULL)
00832   {
00833     return HAL_ERROR;
00834   }
00835
00836   if(hdma->State != HAL_DMA_STATE_BUSY)
00837   {
00838     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00839     return HAL_ERROR;
00840   }
00841   else
00842   {
00843     if(IS_D2_DMA_INSTANCE(hdma) != RESET) /* D2 Domain DMA : DMA1 or DMA2*/
00844     {
00845       /* Set Abort State  */
00846       hdma->State = HAL_DMA_STATE_ABORT;
00847
00848       /* Disable the stream */
00849       __HAL_DMA_DISABLE(hdma);
00850     }
00851     else /* D3 Domain BDMA */
00852     {
00853       /* Disable DMA All Interrupts  */
00854       ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
00855
00856       /* Disable the channel */
00857       __HAL_DMA_DISABLE(hdma);
00858
00859       /* disable the DMAMUX sync overrun IT*/
00860       hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
00861
00862       /* Clear all flags */
00863       BDMA->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex));
00864
00865       /* Clear the DMAMUX synchro overrun flag */
00866       hdma->DMAmuxChannelStatus->CFR |= hdma->DMAmuxChannelStatusMask;
00867
00868       if(hdma->DMAmuxRequestGen != 0U)
00869       {
00870         /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
00871         /* disable the request gen overrun IT*/
00872         hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
00873
00874         /* Clear the DMAMUX request generator overrun flag */
00875         hdma->DMAmuxRequestGenStatus->RGCFR |= hdma->DMAmuxRequestGenStatusMask;
00876       }
00877
00878       /* Process Unlocked */
00879       __HAL_UNLOCK(hdma);
00880
00881       /* Change the DMA state */
00882       hdma->State = HAL_DMA_STATE_READY;
00883
00884       /* Call User Abort callback */
00885       if(hdma->XferAbortCallback != NULL)
00886       {
00887         hdma->XferAbortCallback(hdma);
00888       }
00889     }
00890   }
00891
00892   return HAL_OK;
00893 }
00894
00895 /**
00896   * @brief  Polling for transfer complete.
00897   * @param  hdma:          pointer to a DMA_HandleTypeDef structure that contains
00898   *                        the configuration information for the specified DMA Stream.
00899   * @param  CompleteLevel: Specifies the DMA level complete.
00900   * @note   The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
00901   *         This model could be used for debug purpose.
00902   * @note   The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
00903   * @param  Timeout:       Timeout duration.
00904   * @retval HAL status
00905   */
00906 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
00907 {
00908   HAL_StatusTypeDef status = HAL_OK;
00909   uint32_t cpltlevel_mask = 0U;
00910   uint32_t tickstart = HAL_GetTick();
00911
00912   /* IT status register */
00913   __IO uint32_t *isr_reg = NULL;
00914   /* IT clear flag register */
00915   __IO uint32_t *ifcr_reg = NULL;
00916
00917   /* Check the DMA peripheral handle */
00918   if(hdma == NULL)
00919   {
00920     return HAL_ERROR;
00921   }
00922
00923   if(HAL_DMA_STATE_BUSY != hdma->State)
00924   {
00925     /* No transfer ongoing */
00926     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00927     __HAL_UNLOCK(hdma);
00928
00929     return HAL_ERROR;
00930   }
00931
00932   if(IS_D2_DMA_INSTANCE(hdma) != RESET) /* D2 Domain DMA : DMA1 or DMA2 */
00933   {
00934     /* Polling mode not supported in circular mode and double buffering mode */
00935     if ((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) != RESET)
00936     {
00937       hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
00938       return HAL_ERROR;
00939     }
00940
00941     /* Get the level transfer complete flag */
00942     if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
00943     {
00944       /* Transfer Complete flag */
00945       cpltlevel_mask = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
00946     }
00947     else
00948     {
00949       /* Half Transfer Complete flag */
00950       cpltlevel_mask = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
00951     }
00952
00953     isr_reg  = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->ISR);
00954     ifcr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR);
00955   }
00956   else /* D3 Domain BDMA */
00957   {
00958     /* Polling mode not supported in circular mode */
00959     if ((((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR & BDMA_CCR_CIRC) != RESET)
00960     {
00961       hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
00962       return HAL_ERROR;
00963     }
00964
00965     /* Get the level transfer complete flag */
00966     if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
00967     {
00968       /* Transfer Complete flag */
00969       cpltlevel_mask = BDMA_FLAG_TC0 << hdma->StreamIndex;
00970     }
00971     else
00972     {
00973       /* Half Transfer Complete flag */
00974       cpltlevel_mask = BDMA_FLAG_HT0 << hdma->StreamIndex;
00975     }
00976
00977     isr_reg  = &(BDMA->ISR);
00978     ifcr_reg = &(BDMA->IFCR);
00979   }
00980
00981   while((((*isr_reg) & cpltlevel_mask) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))
00982   {
00983     /* Check for the Timeout (Not applicable in circular mode)*/
00984     if(Timeout != HAL_MAX_DELAY)
00985     {
00986       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00987       {
00988         /* Update error code */
00989         hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
00990
00991         HAL_DMA_Abort(hdma); /* if timeout then abort the current transfer */
00992
00993         /*
00994           Note that the Abort function will
00995             - Clear the transfer error flags
00996             - Unlock
00997             - Set the State
00998         */
00999
01000         return HAL_ERROR;
01001       }
01002     }
01003
01004     /*Check for DMAMUX Request generator (if used) overrun status */
01005     if(hdma->DMAmuxRequestGen != 0U)
01006     {
01007       /* if using DMAMUX request generator Check for DMAMUX request generator overrun */
01008       if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
01009       {
01010         /* Disable the request gen overrun interrupt */
01011         hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
01012
01013         /* Clear the DMAMUX request generator overrun flag */
01014         hdma->DMAmuxRequestGenStatus->RGCFR |= hdma->DMAmuxRequestGenStatusMask;
01015
01016         /* Update error code */
01017         hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
01018       }
01019     }
01020
01021     /* Check for DMAMUX Synchronization overrun */
01022     if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
01023     {
01024       /* Clear the DMAMUX synchro overrun flag */
01025       hdma->DMAmuxChannelStatus->CFR |= hdma->DMAmuxChannelStatusMask;
01026
01027       /* Update error code */
01028       hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
01029     }
01030
01031     if(IS_D2_DMA_INSTANCE(hdma) != RESET) /* D2 Domain DMA : DMA1 or DMA2 */
01032     {
01033       if(((*isr_reg) & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
01034       {
01035         /* Update error code */
01036         hdma->ErrorCode |= HAL_DMA_ERROR_TE;
01037
01038         /* Clear the transfer error flag */
01039         (*ifcr_reg) = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
01040       }
01041
01042       if(((*isr_reg) & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
01043       {
01044         /* Update error code */
01045         hdma->ErrorCode |= HAL_DMA_ERROR_FE;
01046
01047         /* Clear the FIFO error flag */
01048         (*ifcr_reg) = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
01049       }
01050
01051       if(((*isr_reg) & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
01052       {
01053         /* Update error code */
01054         hdma->ErrorCode |= HAL_DMA_ERROR_DME;
01055
01056         /* Clear the Direct Mode error flag */
01057         (*ifcr_reg) = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
01058       }
01059     }
01060     else /* D3 Domain BDMA */
01061     {
01062       if((RESET != (BDMA->ISR & (BDMA_FLAG_TE0 << hdma->StreamIndex))))
01063       {
01064         /* When a DMA transfer error occurs */
01065         /* A hardware clear of its EN bits is performed */
01066         /* Clear all flags */
01067         BDMA->IFCR |= ((BDMA_ISR_GIF0) << (hdma->StreamIndex));
01068
01069         /* Update error code */
01070         hdma->ErrorCode = HAL_DMA_ERROR_TE;
01071       }
01072     }
01073   }
01074
01075
01076   if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
01077   {
01078     if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
01079     {
01080       if(IS_D2_DMA_INSTANCE(hdma) != RESET) /* D2 Domain DMA : DMA1 or DMA2 */
01081       {
01082         HAL_DMA_Abort(hdma);
01083
01084         /*
01085           Note that the Abort function will
01086             - Disable the DMA
01087             - Clear the transfer error flags
01088             - Unlock
01089             - Set the State
01090         */
01091       }
01092       else
01093       {
01094         /* Process Unlocked */
01095         __HAL_UNLOCK(hdma);
01096
01097         /* Change the DMA state */
01098         hdma->State= HAL_DMA_STATE_READY;
01099       }
01100
01101       return HAL_ERROR;
01102     }
01103   }
01104
01105   /* Get the level transfer complete flag */
01106   if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
01107   {
01108     /* Clear the half transfer and transfer complete flags */
01109     if(IS_D2_DMA_INSTANCE(hdma) != RESET) /* D2 Domain DMA : DMA1 or DMA2 */
01110     {
01111       (*ifcr_reg) = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
01112     }
01113     else /* D3 Domain BDMA */
01114     {
01115       BDMA->IFCR  |= (BDMA_FLAG_TC0 << hdma->StreamIndex);
01116     }
01117
01118     /* Process Unlocked */
01119     __HAL_UNLOCK(hdma);
01120
01121     hdma->State = HAL_DMA_STATE_READY;
01122   }
01123   else /*CompleteLevel = HAL_DMA_HALF_TRANSFER*/
01124   {
01125     /* Clear the half transfer and transfer complete flags */
01126     if(IS_D2_DMA_INSTANCE(hdma) != RESET) /* D2 Domain DMA : DMA1 or DMA2 */
01127     {
01128       (*ifcr_reg) = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
01129     }
01130     else /* D3 Domain BDMA */
01131     {
01132       BDMA->IFCR |= (BDMA_FLAG_HT0 << hdma->StreamIndex);
01133     }
01134   }
01135
01136   return status;
01137 }
01138
01139 /**
01140   * @brief  Handles DMA interrupt request.
01141   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01142   *               the configuration information for the specified DMA Stream.
01143   * @retval None
01144   */
01145 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
01146 {
01147   uint32_t tmpisr = 0U;
01148   __IO uint32_t *ccr_reg = NULL;
01149   __IO uint32_t count = 0U;
01150   uint32_t timeout = SystemCoreClock / 9600U;
01151
01152   /* calculate DMA base and stream number */
01153   DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
01154
01155   tmpisr = regs->ISR;
01156
01157   if(IS_D2_DMA_INSTANCE(hdma) != RESET)  /*D2 domain DMA : DMA1 or DMA2*/
01158   {
01159     /* Transfer Error Interrupt management ***************************************/
01160     if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
01161     {
01162       if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
01163       {
01164         /* Disable the transfer error interrupt */
01165         ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TE);
01166
01167         /* Clear the transfer error flag */
01168         regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
01169
01170         /* Update error code */
01171         hdma->ErrorCode |= HAL_DMA_ERROR_TE;
01172       }
01173     }
01174     /* FIFO Error Interrupt management ******************************************/
01175     if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
01176     {
01177       if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
01178       {
01179         /* Clear the FIFO error flag */
01180         regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
01181
01182         /* Update error code */
01183         hdma->ErrorCode |= HAL_DMA_ERROR_FE;
01184       }
01185     }
01186     /* Direct Mode Error Interrupt management ***********************************/
01187     if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
01188     {
01189       if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
01190       {
01191         /* Clear the direct mode error flag */
01192         regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
01193
01194         /* Update error code */
01195         hdma->ErrorCode |= HAL_DMA_ERROR_DME;
01196       }
01197     }
01198     /* Half Transfer Complete Interrupt management ******************************/
01199     if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
01200     {
01201       if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
01202       {
01203         /* Clear the half transfer complete flag */
01204         regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
01205
01206         /* Multi_Buffering mode enabled */
01207         if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
01208         {
01209           /* Current memory buffer used is Memory 0 */
01210           if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CT) == RESET)
01211           {
01212             if(hdma->XferHalfCpltCallback != NULL)
01213             {
01214               /* Half transfer callback */
01215               hdma->XferHalfCpltCallback(hdma);
01216             }
01217           }
01218           /* Current memory buffer used is Memory 1 */
01219           else
01220           {
01221             if(hdma->XferM1HalfCpltCallback != NULL)
01222             {
01223               /* Half transfer callback */
01224               hdma->XferM1HalfCpltCallback(hdma);
01225             }
01226           }
01227         }
01228         else
01229         {
01230           /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
01231           if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == RESET)
01232           {
01233             /* Disable the half transfer interrupt */
01234             ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
01235           }
01236
01237           if(hdma->XferHalfCpltCallback != NULL)
01238           {
01239             /* Half transfer callback */
01240             hdma->XferHalfCpltCallback(hdma);
01241           }
01242         }
01243       }
01244     }
01245     /* Transfer Complete Interrupt management ***********************************/
01246     if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
01247     {
01248       if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
01249       {
01250         /* Clear the transfer complete flag */
01251         regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
01252
01253         if(HAL_DMA_STATE_ABORT == hdma->State)
01254         {
01255           /* Disable all the transfer interrupts */
01256           ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
01257           ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
01258
01259           if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
01260           {
01261             ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
01262           }
01263
01264           /* Clear all interrupt flags at correct offset within the register */
01265           regs->IFCR = 0x3FU << hdma->StreamIndex;
01266
01267           /* Process Unlocked */
01268           __HAL_UNLOCK(hdma);
01269
01270           /* Change the DMA state */
01271           hdma->State = HAL_DMA_STATE_READY;
01272
01273           if(hdma->XferAbortCallback != NULL)
01274           {
01275             hdma->XferAbortCallback(hdma);
01276           }
01277           return;
01278         }
01279
01280         if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
01281         {
01282           /* Current memory buffer used is Memory 0 */
01283           if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CT) == RESET)
01284           {
01285             if(hdma->XferM1CpltCallback != NULL)
01286             {
01287               /* Transfer complete Callback for memory1 */
01288               hdma->XferM1CpltCallback(hdma);
01289             }
01290           }
01291           /* Current memory buffer used is Memory 1 */
01292           else
01293           {
01294             if(hdma->XferCpltCallback != NULL)
01295             {
01296               /* Transfer complete Callback for memory0 */
01297               hdma->XferCpltCallback(hdma);
01298             }
01299           }
01300         }
01301         /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
01302         else
01303         {
01304           if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == RESET)
01305           {
01306             /* Disable the transfer complete interrupt */
01307             ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC);
01308
01309             /* Process Unlocked */
01310             __HAL_UNLOCK(hdma);
01311
01312             /* Change the DMA state */
01313             hdma->State = HAL_DMA_STATE_READY;
01314           }
01315
01316           if(hdma->XferCpltCallback != NULL)
01317           {
01318             /* Transfer complete callback */
01319             hdma->XferCpltCallback(hdma);
01320           }
01321         }
01322       }
01323     }
01324
01325     /* manage error case */
01326     if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
01327     {
01328       if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
01329       {
01330         hdma->State = HAL_DMA_STATE_ABORT;
01331
01332         /* Disable the stream */
01333         __HAL_DMA_DISABLE(hdma);
01334
01335         do
01336         {
01337           if (++count > timeout)
01338           {
01339             break;
01340           }
01341         }
01342         while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != RESET);
01343
01344         /* Process Unlocked */
01345         __HAL_UNLOCK(hdma);
01346
01347         if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != RESET)
01348         {
01349           /* Change the DMA state to error if DMA disable fails */
01350           hdma->State = HAL_DMA_STATE_ERROR;
01351         }
01352         else
01353         {
01354           /* Change the DMA state to Ready if DMA disable success */
01355           hdma->State = HAL_DMA_STATE_READY;
01356         }
01357       }
01358
01359       if(hdma->XferErrorCallback != NULL)
01360       {
01361         /* Transfer error callback */
01362         hdma->XferErrorCallback(hdma);
01363       }
01364     }
01365   }
01366   else if(IS_D3_DMA_INSTANCE(hdma) != RESET)  /*D3 domain BDMA */
01367   {
01368     ccr_reg = &(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR);
01369
01370     /* Half Transfer Complete Interrupt management ******************************/
01371     if ((RESET != (BDMA->ISR & (BDMA_FLAG_HT0 << hdma->StreamIndex))) && (RESET != ((*ccr_reg) & BDMA_CCR_HTIE)))
01372     {
01373         /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
01374         if(((*ccr_reg) & BDMA_CCR_CIRC) == 0U)
01375         {
01376           /* Disable the half transfer interrupt */
01377           (*ccr_reg) &= ~BDMA_CCR_HTIE;
01378         }
01379         /* Clear the half transfer complete flag */
01380         BDMA->IFCR  |= (BDMA_ISR_HTIF0 << hdma->StreamIndex);
01381
01382         /* DMA peripheral state is not updated in Half Transfer */
01383         /* but in Transfer Complete case */
01384
01385        if(hdma->XferHalfCpltCallback != NULL)
01386         {
01387           /* Half transfer callback */
01388           hdma->XferHalfCpltCallback(hdma);
01389         }
01390     }
01391
01392     /* Transfer Complete Interrupt management ***********************************/
01393     else if ((RESET != (BDMA->ISR & (BDMA_FLAG_TC0 << hdma->StreamIndex))) && (RESET != ((*ccr_reg) & BDMA_CCR_TCIE)))
01394     {
01395       if(((*ccr_reg) & BDMA_CCR_CIRC) == 0U)
01396       {
01397         /* Disable TE & TC */
01398         (*ccr_reg) &= ~(BDMA_CCR_TEIE | BDMA_CCR_TCIE);
01399
01400       /* Process Unlocked */
01401       __HAL_UNLOCK(hdma);
01402
01403         /* Change the DMA state */
01404         hdma->State = HAL_DMA_STATE_READY;
01405       }
01406       /* Clear the transfer complete flag */
01407       BDMA->IFCR |= (BDMA_ISR_TCIF0 << hdma->StreamIndex);
01408
01409       if(hdma->XferCpltCallback != NULL)
01410       {
01411         /* Transfer complete callback */
01412         hdma->XferCpltCallback(hdma);
01413       }
01414     }
01415
01416     /* Transfer Error Interrupt management **************************************/
01417     else if (( RESET != (BDMA->ISR & (BDMA_FLAG_TE0 << hdma->StreamIndex))) && (RESET != ((*ccr_reg) & BDMA_CCR_TEIE)))
01418     {
01419       /* When a DMA transfer error occurs */
01420       /* A hardware clear of its EN bits is performed */
01421       /* Disable ALL DMA IT */
01422       (*ccr_reg) &= ~(BDMA_CCR_TEIE | BDMA_CCR_TCIE | BDMA_CCR_HTIE);
01423
01424       /* Clear all flags */
01425       BDMA->IFCR  |= (BDMA_ISR_GIF0 << hdma->StreamIndex);
01426
01427       /* Update error code */
01428       hdma->ErrorCode = HAL_DMA_ERROR_TE;
01429
01430       /* Process Unlocked */
01431       __HAL_UNLOCK(hdma);
01432
01433       /* Change the DMA state */
01434       hdma->State = HAL_DMA_STATE_READY;
01435
01436       if (hdma->XferErrorCallback != NULL)
01437       {
01438         /* Transfer error callback */
01439         hdma->XferErrorCallback(hdma);
01440       }
01441     }
01442   }
01443 }
01444
01445 /**
01446   * @brief  Register callbacks
01447   * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
01448   *                               the configuration information for the specified DMA Stream.
01449   * @param  CallbackID:           User Callback identifer
01450   *                               a DMA_HandleTypeDef structure as parameter.
01451   * @param  pCallback:            pointer to private callbacsk function which has pointer to
01452   *                               a DMA_HandleTypeDef structure as parameter.
01453   * @retval HAL status
01454   */
01455 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
01456 {
01457
01458   HAL_StatusTypeDef status = HAL_OK;
01459
01460   /* Check the DMA peripheral handle */
01461   if(hdma == NULL)
01462   {
01463     return HAL_ERROR;
01464   }
01465
01466   /* Process locked */
01467   __HAL_LOCK(hdma);
01468
01469   if(HAL_DMA_STATE_READY == hdma->State)
01470   {
01471     switch (CallbackID)
01472     {
01473     case  HAL_DMA_XFER_CPLT_CB_ID:
01474       hdma->XferCpltCallback = pCallback;
01475       break;
01476
01477     case  HAL_DMA_XFER_HALFCPLT_CB_ID:
01478       hdma->XferHalfCpltCallback = pCallback;
01479       break;
01480
01481     case  HAL_DMA_XFER_M1CPLT_CB_ID:
01482       hdma->XferM1CpltCallback = pCallback;
01483       break;
01484
01485     case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
01486       hdma->XferM1HalfCpltCallback = pCallback;
01487       break;
01488
01489     case  HAL_DMA_XFER_ERROR_CB_ID:
01490       hdma->XferErrorCallback = pCallback;
01491       break;
01492
01493     case  HAL_DMA_XFER_ABORT_CB_ID:
01494       hdma->XferAbortCallback = pCallback;
01495       break;
01496
01497     default:
01498       break;
01499     }
01500   }
01501   else
01502   {
01503     /* Return error status */
01504     status =  HAL_ERROR;
01505   }
01506
01507   /* Release Lock */
01508   __HAL_UNLOCK(hdma);
01509
01510   return status;
01511 }
01512
01513 /**
01514   * @brief  UnRegister callbacks
01515   * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
01516   *                               the configuration information for the specified DMA Stream.
01517   * @param  CallbackID:           User Callback identifer
01518   *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
01519   * @retval HAL status
01520   */
01521 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
01522 {
01523   HAL_StatusTypeDef status = HAL_OK;
01524
01525   /* Check the DMA peripheral handle */
01526   if(hdma == NULL)
01527   {
01528     return HAL_ERROR;
01529   }
01530
01531   /* Process locked */
01532   __HAL_LOCK(hdma);
01533
01534   if(HAL_DMA_STATE_READY == hdma->State)
01535   {
01536     switch (CallbackID)
01537     {
01538     case  HAL_DMA_XFER_CPLT_CB_ID:
01539       hdma->XferCpltCallback = NULL;
01540       break;
01541
01542     case  HAL_DMA_XFER_HALFCPLT_CB_ID:
01543       hdma->XferHalfCpltCallback = NULL;
01544       break;
01545
01546     case  HAL_DMA_XFER_M1CPLT_CB_ID:
01547       hdma->XferM1CpltCallback = NULL;
01548       break;
01549
01550     case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
01551       hdma->XferM1HalfCpltCallback = NULL;
01552       break;
01553
01554     case  HAL_DMA_XFER_ERROR_CB_ID:
01555       hdma->XferErrorCallback = NULL;
01556       break;
01557
01558     case  HAL_DMA_XFER_ABORT_CB_ID:
01559       hdma->XferAbortCallback = NULL;
01560       break;
01561
01562     case   HAL_DMA_XFER_ALL_CB_ID:
01563       hdma->XferCpltCallback = NULL;
01564       hdma->XferHalfCpltCallback = NULL;
01565       hdma->XferM1CpltCallback = NULL;
01566       hdma->XferM1HalfCpltCallback = NULL;
01567       hdma->XferErrorCallback = NULL;
01568       hdma->XferAbortCallback = NULL;
01569       break;
01570
01571     default:
01572       status = HAL_ERROR;
01573       break;
01574     }
01575   }
01576   else
01577   {
01578     status = HAL_ERROR;
01579   }
01580
01581   /* Release Lock */
01582   __HAL_UNLOCK(hdma);
01583
01584   return status;
01585 }
01586
01587 /**
01588   * @}
01589   */
01590
01591 /** @addtogroup DMA_Exported_Functions_Group3
01592   *
01593 @verbatim
01594  ===============================================================================
01595                     ##### State and Errors functions #####
01596  ===============================================================================
01597     [..]
01598     This subsection provides functions allowing to
01599       (+) Check the DMA state
01600       (+) Get error code
01601
01602 @endverbatim
01603   * @{
01604   */
01605
01606 /**
01607   * @brief  Returns the DMA state.
01608   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01609   *               the configuration information for the specified DMA Stream.
01610   * @retval HAL state
01611   */
01612 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
01613 {
01614   return hdma->State;
01615 }
01616
01617 /**
01618   * @brief  Return the DMA error code
01619   * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
01620   *              the configuration information for the specified DMA Stream.
01621   * @retval DMA Error Code
01622   */
01623 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
01624 {
01625   return hdma->ErrorCode;
01626 }
01627
01628 /**
01629   * @}
01630   */
01631
01632 /**
01633   * @}
01634   */
01635
01636 /** @addtogroup DMA_Private_Functions
01637   * @{
01638   */
01639
01640 /**
01641   * @brief  Sets the DMA Transfer parameter.
01642   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
01643   *                     the configuration information for the specified DMA Stream.
01644   * @param  SrcAddress: The source memory Buffer address
01645   * @param  DstAddress: The destination memory Buffer address
01646   * @param  DataLength: The length of data to be transferred from source to destination
01647   * @retval HAL status
01648   */
01649 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
01650 {
01651   /* calculate DMA base and stream number */
01652   DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
01653
01654   /* Clear the DMAMUX synchro overrun flag */
01655   hdma->DMAmuxChannelStatus->CFR |= hdma->DMAmuxChannelStatusMask;
01656
01657   if(hdma->DMAmuxRequestGen != 0U)
01658   {
01659     /* Clear the DMAMUX request generator overrun flag */
01660     hdma->DMAmuxRequestGenStatus->RGCFR |= hdma->DMAmuxRequestGenStatusMask;
01661   }
01662
01663   if(IS_D2_DMA_INSTANCE(hdma) != RESET) /* D2 Domain DMA : DMA1 or DMA2 */
01664   {
01665     /* Clear all interrupt flags at correct offset within the register */
01666     regs->IFCR = 0x3FU << hdma->StreamIndex;
01667
01668     /* Clear DBM bit */
01669     ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM);
01670
01671     /* Configure DMA Stream data length */
01672     ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;
01673
01674     /* Peripheral to Memory */
01675     if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
01676     {
01677       /* Configure DMA Stream destination address */
01678       ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;
01679
01680       /* Configure DMA Stream source address */
01681       ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;
01682     }
01683     /* Memory to Peripheral */
01684     else
01685     {
01686       /* Configure DMA Stream source address */
01687       ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;
01688
01689       /* Configure DMA Stream destination address */
01690       ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;
01691     }
01692   }
01693   else if(IS_D3_DMA_INSTANCE(hdma)) /* D3 Domain BDMA */
01694   {
01695     /* Clear all flags */
01696     BDMA->IFCR  |= (BDMA_ISR_GIF0 << hdma->StreamIndex);
01697
01698     /* Configure DMA Channel data length */
01699     ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength;
01700
01701     /* Peripheral to Memory */
01702     if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
01703     {
01704       /* Configure DMA Channel destination address */
01705       ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress;
01706
01707       /* Configure DMA Channel source address */
01708       ((BDMA_Channel_TypeDef *)hdma->Instance)->CMAR = SrcAddress;
01709     }
01710     /* Memory to Peripheral */
01711     else
01712     {
01713       /* Configure DMA Channel source address */
01714       ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress;
01715
01716       /* Configure DMA Channel destination address */
01717       ((BDMA_Channel_TypeDef *)hdma->Instance)->CMAR = DstAddress;
01718     }
01719   }
01720 }
01721
01722 /**
01723   * @brief  Returns the DMA Stream base address depending on stream number
01724   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
01725   *                     the configuration information for the specified DMA Stream.
01726   * @retval Stream base address
01727   */
01728 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
01729 {
01730   uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
01731
01732   /* lookup table for necessary bitshift of flags within status registers */
01733   static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
01734   hdma->StreamIndex = flagBitshiftOffset[stream_number];
01735
01736   if (stream_number > 3U)
01737   {
01738     /* return pointer to HISR and HIFCR */
01739     hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
01740   }
01741   else
01742   {
01743     /* return pointer to LISR and LIFCR */
01744     hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
01745   }
01746
01747   return hdma->StreamBaseAddress;
01748 }
01749
01750 /**
01751   * @brief  Check compatibility between FIFO threshold level and size of the memory burst
01752   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
01753   *                     the configuration information for the specified DMA Stream.
01754   * @retval HAL status
01755   */
01756 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
01757 {
01758   HAL_StatusTypeDef status = HAL_OK;
01759
01760   /* Memory Data size equal to Byte */
01761   if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
01762   {
01763     switch (hdma->Init.FIFOThreshold)
01764     {
01765       case DMA_FIFO_THRESHOLD_1QUARTERFULL:
01766       case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
01767
01768         if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
01769         {
01770           status = HAL_ERROR;
01771         }
01772         break;
01773
01774       case DMA_FIFO_THRESHOLD_HALFFULL:
01775         if (hdma->Init.MemBurst == DMA_MBURST_INC16)
01776         {
01777           status = HAL_ERROR;
01778         }
01779         break;
01780
01781       case DMA_FIFO_THRESHOLD_FULL:
01782         break;
01783
01784       default:
01785         break;
01786     }
01787   }
01788
01789   /* Memory Data size equal to Half-Word */
01790   else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
01791   {
01792     switch (hdma->Init.FIFOThreshold)
01793     {
01794       case DMA_FIFO_THRESHOLD_1QUARTERFULL:
01795       case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
01796         status = HAL_ERROR;
01797         break;
01798
01799       case DMA_FIFO_THRESHOLD_HALFFULL:
01800         if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
01801         {
01802           status = HAL_ERROR;
01803         }
01804         break;
01805
01806       case DMA_FIFO_THRESHOLD_FULL:
01807         if (hdma->Init.MemBurst == DMA_MBURST_INC16)
01808         {
01809           status = HAL_ERROR;
01810         }
01811         break;
01812
01813       default:
01814         break;
01815     }
01816   }
01817
01818   /* Memory Data size equal to Word */
01819   else
01820   {
01821     switch (hdma->Init.FIFOThreshold)
01822     {
01823       case DMA_FIFO_THRESHOLD_1QUARTERFULL:
01824       case DMA_FIFO_THRESHOLD_HALFFULL:
01825       case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
01826         status = HAL_ERROR;
01827         break;
01828
01829       case DMA_FIFO_THRESHOLD_FULL:
01830         if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
01831         {
01832           status = HAL_ERROR;
01833         }
01834     break;
01835
01836       default:
01837         break;
01838     }
01839   }
01840
01841   return status;
01842 }
01843
01844 /**
01845   * @brief  Updates the DMA handle with the DMAMUX  channel and status mask depending on stream number
01846   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
01847   *                     the configuration information for the specified DMA Stream.
01848   * @retval HAL status
01849   */
01850 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
01851 {
01852   uint32_t stream_number = 0U;
01853   uint32_t stream_baseaddress = (uint32_t)hdma->Instance;
01854
01855   if((stream_baseaddress <= ((uint32_t)BDMA_Channel7) ) && \
01856      (stream_baseaddress >= ((uint32_t)BDMA_Channel0)))
01857   {
01858     /*BDMA Channels are connected to DMAMUX2 channels*/
01859     stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
01860     hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U)));
01861     hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus;
01862     hdma->DMAmuxChannelStatusMask = 1U << stream_number;
01863   }
01864   else
01865   {
01866     /*DMA1/DMA2 Streams are connected to DMAMUX1 channels*/
01867     stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
01868
01869     if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \
01870      (stream_baseaddress >= ((uint32_t)DMA2_Stream0)))
01871     {
01872       stream_number += 8U;
01873     }
01874     hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U)));
01875     hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
01876     hdma->DMAmuxChannelStatusMask = 1U << stream_number;
01877   }
01878 }
01879
01880 /**
01881   * @brief  Updates the DMA handle with the DMAMUX  request generator params
01882   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
01883   *                     the configuration information for the specified DMA Stream.
01884   * @retval HAL status
01885   */
01886 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
01887 {
01888   uint32_t stream_baseaddress = (uint32_t)hdma->Instance;
01889   uint32_t request =  hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
01890
01891   if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7))
01892   {
01893     if((stream_baseaddress <= ((uint32_t)BDMA_Channel7) ) && \
01894       (stream_baseaddress >= ((uint32_t)BDMA_Channel0)))
01895     {
01896       /*BDMA Channels are connected to DMAMUX2 request generator blocks*/
01897       hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U)));
01898
01899       hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus;
01900     }
01901     else
01902     {
01903       /*DMA1 and DMA2 Streams use DMAMUX1 request generator blocks*/
01904       hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
01905
01906       hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
01907     }
01908
01909     hdma->DMAmuxRequestGenStatusMask = 1U << (request - 1U);
01910   }
01911 }
01912
01913 /**
01914   * @}
01915   */
01916
01917 #endif /* HAL_DMA_MODULE_ENABLED */
01918 /**
01919   * @}
01920   */
01921
01922 /**
01923   * @}
01924   */
01925
01926 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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STM32H753xx HAL User Manual: stm32h7xx_hal_dma.h Source File

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stm32h7xx_hal_dma.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dma.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of DMA HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_DMA_H
00040 #define __STM32H7xx_HAL_DMA_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup DMA
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup DMA_Exported_Types DMA Exported Types
00060   * @brief    DMA Exported Types
00061   * @{
00062   */
00063
00064 /**
00065   * @brief  DMA Configuration Structure definition
00066   */
00067 typedef struct
00068 {
00069   uint32_t Request;               /*!< Specifies the request selected for the specified stream.
00070                                            This parameter can be a value of @ref DMA_Request_selection              */
00071
00072   uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral,
00073                                       from memory to memory or from peripheral to memory.
00074                                       This parameter can be a value of @ref DMA_Data_transfer_direction              */
00075
00076   uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.
00077                                       This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */
00078
00079   uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.
00080                                       This parameter can be a value of @ref DMA_Memory_incremented_mode              */
00081
00082   uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.
00083                                       This parameter can be a value of @ref DMA_Peripheral_data_size                 */
00084
00085   uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.
00086                                       This parameter can be a value of @ref DMA_Memory_data_size                     */
00087
00088   uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.
00089                                       This parameter can be a value of @ref DMA_mode
00090                                       @note The circular buffer mode cannot be used if the memory-to-memory
00091                                             data transfer is configured on the selected Stream                        */
00092
00093   uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.
00094                                       This parameter can be a value of @ref DMA_Priority_level                        */
00095
00096   uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
00097                                       This parameter can be a value of @ref DMA_FIFO_direct_mode
00098                                       @note The Direct mode (FIFO mode disabled) cannot be used if the
00099                                             memory-to-memory data transfer is configured on the selected stream       */
00100
00101   uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.
00102                                       This parameter can be a value of @ref DMA_FIFO_threshold_level                  */
00103
00104   uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers.
00105                                       It specifies the amount of data to be transferred in a single non interruptible
00106                                       transaction.
00107                                       This parameter can be a value of @ref DMA_Memory_burst
00108                                       @note The burst mode is possible only if the address Increment mode is enabled. */
00109
00110   uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers.
00111                                       It specifies the amount of data to be transferred in a single non interruptible
00112                                       transaction.
00113                                       This parameter can be a value of @ref DMA_Peripheral_burst
00114                                       @note The burst mode is possible only if the address Increment mode is enabled. */
00115 }DMA_InitTypeDef;
00116
00117 /**
00118   * @brief  HAL DMA State structures definition
00119   */
00120 typedef enum
00121 {
00122   HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
00123   HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
00124   HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
00125   HAL_DMA_STATE_ERROR             = 0x03U,  /*!< DMA error state                     */
00126   HAL_DMA_STATE_ABORT             = 0x04U,  /*!< DMA Abort state                     */
00127 }HAL_DMA_StateTypeDef;
00128
00129 /**
00130   * @brief  HAL DMA Transfer complete level structure definition
00131   */
00132 typedef enum
00133 {
00134   HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
00135   HAL_DMA_HALF_TRANSFER      = 0x01U,    /*!< Half Transfer     */
00136 }HAL_DMA_LevelCompleteTypeDef;
00137
00138 /**
00139   * @brief  HAL DMA Callbacks IDs structure definition
00140   */
00141 typedef enum
00142 {
00143   HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
00144   HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half Transfer     */
00145   HAL_DMA_XFER_M1CPLT_CB_ID        = 0x02U,    /*!< M1 Full Transfer  */
00146   HAL_DMA_XFER_M1HALFCPLT_CB_ID    = 0x03U,    /*!< M1 Half Transfer  */
00147   HAL_DMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error             */
00148   HAL_DMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort             */
00149   HAL_DMA_XFER_ALL_CB_ID           = 0x06U     /*!< All               */
00150 }HAL_DMA_CallbackIDTypeDef;
00151
00152 /**
00153   * @brief  DMA handle Structure definition
00154   */
00155 typedef struct __DMA_HandleTypeDef
00156 {
00157   void                            *Instance;                                                        /*!< Register base address                         */
00158
00159   DMA_InitTypeDef                 Init;                                                             /*!< DMA communication parameters                  */
00160
00161   HAL_LockTypeDef                 Lock;                                                             /*!< DMA locking object                            */
00162
00163   __IO HAL_DMA_StateTypeDef       State;                                                            /*!< DMA transfer state                            */
00164
00165   void                            *Parent;                                                          /*!< Parent object state                           */
00166
00167   void                            (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);         /*!< DMA transfer complete callback                */
00168
00169   void                            (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA Half transfer complete callback           */
00170
00171   void                            (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer complete Memory1 callback        */
00172
00173   void                            (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback   */
00174
00175   void                            (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer error callback                   */
00176
00177   void                            (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer Abort callback                   */
00178
00179  __IO uint32_t                    ErrorCode;                                                        /*!< DMA Error code                                */
00180
00181  uint32_t                         StreamBaseAddress;                                                /*!< DMA Stream Base Address                       */
00182
00183  uint32_t                         StreamIndex;                                                      /*!< DMA Stream Index                              */
00184
00185  DMAMUX_Channel_TypeDef           *DMAmuxChannel;                                                   /*!< DMAMUX Channel Base Address                   */
00186
00187  DMAMUX_ChannelStatus_TypeDef     *DMAmuxChannelStatus;                                             /*!< DMAMUX Channels Status Base Address           */
00188
00189  uint32_t                         DMAmuxChannelStatusMask;                                          /*!< DMAMUX Channel Status Mask                    */
00190
00191
00192  DMAMUX_RequestGen_TypeDef        *DMAmuxRequestGen;                                                /*!< DMAMUX request generator Base Address         */
00193
00194  DMAMUX_RequestGenStatus_TypeDef  *DMAmuxRequestGenStatus;                                          /*!< DMAMUX request generator Status Address       */
00195
00196  uint32_t                         DMAmuxRequestGenStatusMask;                                       /*!< DMAMUX request generator Status mask          */
00197
00198 }DMA_HandleTypeDef;
00199
00200 /**
00201   * @}
00202   */
00203
00204
00205 /* Exported constants --------------------------------------------------------*/
00206
00207 /** @defgroup DMA_Exported_Constants DMA Exported Constants
00208   * @brief    DMA Exported constants
00209   * @{
00210   */
00211
00212 /** @defgroup DMA_Error_Code DMA Error Code
00213   * @brief    DMA Error Code
00214   * @{
00215   */
00216 #define HAL_DMA_ERROR_NONE            ((uint32_t)0x00000000U)    /*!< No error                                */
00217 #define HAL_DMA_ERROR_TE              ((uint32_t)0x00000001U)    /*!< Transfer error                          */
00218 #define HAL_DMA_ERROR_FE              ((uint32_t)0x00000002U)    /*!< FIFO error                              */
00219 #define HAL_DMA_ERROR_DME             ((uint32_t)0x00000004U)    /*!< Direct Mode error                       */
00220 #define HAL_DMA_ERROR_TIMEOUT         ((uint32_t)0x00000020U)    /*!< Timeout error                           */
00221 #define HAL_DMA_ERROR_PARAM           ((uint32_t)0x00000040U)    /*!< Parameter error                         */
00222 #define HAL_DMA_ERROR_NO_XFER         ((uint32_t)0x00000080U)    /*!< Abort requested with no Xfer ongoing    */
00223 #define HAL_DMA_ERROR_NOT_SUPPORTED   ((uint32_t)0x00000100U)    /*!< Not supported mode                      */
00224 #define HAL_DMA_ERROR_SYNC            ((uint32_t)0x00000200U)    /*!< DMAMUX sync overrun  error              */
00225 #define HAL_DMA_ERROR_REQGEN          ((uint32_t)0x00000400U)    /*!< DMAMUX request generator overrun  error */
00226
00227 /**
00228   * @}
00229   */
00230
00231 /** @defgroup DMA_Request_selection DMA Request selection
00232   * @brief    DMA Request selection
00233   * @{
00234   */
00235 /* D2 Domain : DMAMUX1 requests */
00236 #define DMA_REQUEST_MEM2MEM          ((uint32_t)0x00000000)  /*!< memory to memory transfer   */
00237
00238 #define DMA_REQUEST_GENERATOR0       ((uint32_t)0x00000001)  /*!< DMAMUX1 request generator 0 */
00239 #define DMA_REQUEST_GENERATOR1       ((uint32_t)0x00000002)  /*!< DMAMUX1 request generator 1 */
00240 #define DMA_REQUEST_GENERATOR2       ((uint32_t)0x00000003)  /*!< DMAMUX1 request generator 2 */
00241 #define DMA_REQUEST_GENERATOR3       ((uint32_t)0x00000004)  /*!< DMAMUX1 request generator 3 */
00242 #define DMA_REQUEST_GENERATOR4       ((uint32_t)0x00000005)  /*!< DMAMUX1 request generator 4 */
00243 #define DMA_REQUEST_GENERATOR5       ((uint32_t)0x00000006)  /*!< DMAMUX1 request generator 5 */
00244 #define DMA_REQUEST_GENERATOR6       ((uint32_t)0x00000007)  /*!< DMAMUX1 request generator 6 */
00245 #define DMA_REQUEST_GENERATOR7       ((uint32_t)0x00000008)  /*!< DMAMUX1 request generator 7 */
00246
00247 #define DMA_REQUEST_ADC1             ((uint32_t)0x00000009)  /*!< DMAMUX1 ADC1 request */
00248 #define DMA_REQUEST_ADC2             ((uint32_t)0x0000000A)  /*!< DMAMUX1 ADC2 request */
00249
00250 #define DMA_REQUEST_TIM1_CH1         ((uint32_t)0x0000000B)  /*!< DMAMUX1 TIM1 CH1 request  */
00251 #define DMA_REQUEST_TIM1_CH2         ((uint32_t)0x0000000C)  /*!< DMAMUX1 TIM1 CH2 request  */
00252 #define DMA_REQUEST_TIM1_CH3         ((uint32_t)0x0000000D)  /*!< DMAMUX1 TIM1 CH3 request  */
00253 #define DMA_REQUEST_TIM1_CH4         ((uint32_t)0x0000000E)  /*!< DMAMUX1 TIM1 CH4 request  */
00254 #define DMA_REQUEST_TIM1_UP          ((uint32_t)0x0000000F)  /*!< DMAMUX1 TIM1 UP request   */
00255 #define DMA_REQUEST_TIM1_TRIG        ((uint32_t)0x00000010)  /*!< DMAMUX1 TIM1 TRIG request */
00256 #define DMA_REQUEST_TIM1_COM         ((uint32_t)0x00000011)  /*!< DMAMUX1 TIM1 COM request  */
00257
00258 #define DMA_REQUEST_TIM2_CH1         ((uint32_t)0x00000012)  /*!< DMAMUX1 TIM2 CH1 request  */
00259 #define DMA_REQUEST_TIM2_CH2         ((uint32_t)0x00000013)  /*!< DMAMUX1 TIM2 CH2 request  */
00260 #define DMA_REQUEST_TIM2_CH3         ((uint32_t)0x00000014)  /*!< DMAMUX1 TIM2 CH3 request  */
00261 #define DMA_REQUEST_TIM2_CH4         ((uint32_t)0x00000015)  /*!< DMAMUX1 TIM2 CH4 request  */
00262 #define DMA_REQUEST_TIM2_UP          ((uint32_t)0x00000016)  /*!< DMAMUX1 TIM2 UP request   */
00263
00264 #define DMA_REQUEST_TIM3_CH1         ((uint32_t)0x00000017)  /*!< DMAMUX1 TIM3 CH1 request  */
00265 #define DMA_REQUEST_TIM3_CH2         ((uint32_t)0x00000018)  /*!< DMAMUX1 TIM3 CH2 request  */
00266 #define DMA_REQUEST_TIM3_CH3         ((uint32_t)0x00000019)  /*!< DMAMUX1 TIM3 CH3 request  */
00267 #define DMA_REQUEST_TIM3_CH4         ((uint32_t)0x0000001A)  /*!< DMAMUX1 TIM3 CH4 request  */
00268 #define DMA_REQUEST_TIM3_UP          ((uint32_t)0x0000001B)  /*!< DMAMUX1 TIM3 UP request   */
00269 #define DMA_REQUEST_TIM3_TRIG        ((uint32_t)0x0000001C)  /*!< DMAMUX1 TIM3 TRIG request */
00270
00271 #define DMA_REQUEST_TIM4_CH1         ((uint32_t)0x0000001D)  /*!< DMAMUX1 TIM4 CH1 request  */
00272 #define DMA_REQUEST_TIM4_CH2         ((uint32_t)0x0000001E)  /*!< DMAMUX1 TIM4 CH2 request  */
00273 #define DMA_REQUEST_TIM4_CH3         ((uint32_t)0x0000001F)  /*!< DMAMUX1 TIM4 CH3 request  */
00274 #define DMA_REQUEST_TIM4_UP          ((uint32_t)0x00000020)  /*!< DMAMUX1 TIM4 UP request   */
00275
00276 #define DMA_REQUEST_I2C1_RX          ((uint32_t)0x00000021)  /*!< DMAMUX1 I2C1 RX request   */
00277 #define DMA_REQUEST_I2C1_TX          ((uint32_t)0x00000022)  /*!< DMAMUX1 I2C1 TX request   */
00278 #define DMA_REQUEST_I2C2_RX          ((uint32_t)0x00000023)  /*!< DMAMUX1 I2C2 RX request   */
00279 #define DMA_REQUEST_I2C2_TX          ((uint32_t)0x00000024)  /*!< DMAMUX1 I2C2 TX request   */
00280
00281 #define DMA_REQUEST_SPI1_RX          ((uint32_t)0x00000025)  /*!< DMAMUX1 SPI1 RX request   */
00282 #define DMA_REQUEST_SPI1_TX          ((uint32_t)0x00000026)  /*!< DMAMUX1 SPI1 TX request   */
00283 #define DMA_REQUEST_SPI2_RX          ((uint32_t)0x00000027)  /*!< DMAMUX1 SPI2 RX request   */
00284 #define DMA_REQUEST_SPI2_TX          ((uint32_t)0x00000028)  /*!< DMAMUX1 SPI2 TX request   */
00285
00286 #define DMA_REQUEST_USART1_RX        ((uint32_t)0x00000029)  /*!< DMAMUX1 USART1 RX request */
00287 #define DMA_REQUEST_USART1_TX        ((uint32_t)0x0000002A)  /*!< DMAMUX1 USART1 TX request */
00288 #define DMA_REQUEST_USART2_RX        ((uint32_t)0x0000002B)  /*!< DMAMUX1 USART2 RX request */
00289 #define DMA_REQUEST_USART2_TX        ((uint32_t)0x0000002C)  /*!< DMAMUX1 USART2 TX request */
00290 #define DMA_REQUEST_USART3_RX        ((uint32_t)0x0000002D)  /*!< DMAMUX1 USART3 RX request */
00291 #define DMA_REQUEST_USART3_TX        ((uint32_t)0x0000002E)  /*!< DMAMUX1 USART3 TX request */
00292
00293 #define DMA_REQUEST_TIM8_CH1         ((uint32_t)0x0000002F)  /*!< DMAMUX1 TIM8 CH1 request  */
00294 #define DMA_REQUEST_TIM8_CH2         ((uint32_t)0x00000030)  /*!< DMAMUX1 TIM8 CH2 request  */
00295 #define DMA_REQUEST_TIM8_CH3         ((uint32_t)0x00000031)  /*!< DMAMUX1 TIM8 CH3 request  */
00296 #define DMA_REQUEST_TIM8_CH4         ((uint32_t)0x00000032)  /*!< DMAMUX1 TIM8 CH4 request  */
00297 #define DMA_REQUEST_TIM8_UP          ((uint32_t)0x00000033)  /*!< DMAMUX1 TIM8 UP request   */
00298 #define DMA_REQUEST_TIM8_TRIG        ((uint32_t)0x00000034)  /*!< DMAMUX1 TIM8 TRIG request */
00299 #define DMA_REQUEST_TIM8_COM         ((uint32_t)0x00000035)  /*!< DMAMUX1 TIM8 COM request  */
00300
00301 #define DMA_REQUEST_TIM5_CH1         ((uint32_t)0x00000037)  /*!< DMAMUX1 TIM5 CH1 request  */
00302 #define DMA_REQUEST_TIM5_CH2         ((uint32_t)0x00000038)  /*!< DMAMUX1 TIM5 CH2 request  */
00303 #define DMA_REQUEST_TIM5_CH3         ((uint32_t)0x00000039)  /*!< DMAMUX1 TIM5 CH3 request  */
00304 #define DMA_REQUEST_TIM5_CH4         ((uint32_t)0x0000003A)  /*!< DMAMUX1 TIM5 CH4 request  */
00305 #define DMA_REQUEST_TIM5_UP          ((uint32_t)0x0000003B)  /*!< DMAMUX1 TIM5 UP request   */
00306 #define DMA_REQUEST_TIM5_TRIG        ((uint32_t)0x0000003C)  /*!< DMAMUX1 TIM5 TRIG request */
00307
00308 #define DMA_REQUEST_SPI3_RX          ((uint32_t)0x0000003D)  /*!< DMAMUX1 SPI3 RX request   */
00309 #define DMA_REQUEST_SPI3_TX          ((uint32_t)0x0000003E)  /*!< DMAMUX1 SPI3 TX request   */
00310
00311 #define DMA_REQUEST_UART4_RX         ((uint32_t)0x0000003F)  /*!< DMAMUX1 UART4 RX request */
00312 #define DMA_REQUEST_UART4_TX         ((uint32_t)0x00000040)  /*!< DMAMUX1 UART4 TX request */
00313 #define DMA_REQUEST_UART5_RX         ((uint32_t)0x00000041)  /*!< DMAMUX1 UART5 RX request */
00314 #define DMA_REQUEST_UART5_TX         ((uint32_t)0x00000042)  /*!< DMAMUX1 UART5 TX request */
00315
00316 #define DMA_REQUEST_DAC1             ((uint32_t)0x00000043)  /*!< DMAMUX1 DAC1 request      */
00317 #define DMA_REQUEST_DAC2             ((uint32_t)0x00000044)  /*!< DMAMUX1 DAC2 request      */
00318
00319 #define DMA_REQUEST_TIM6_UP          ((uint32_t)0x00000045)  /*!< DMAMUX1 TIM6 UP request   */
00320 #define DMA_REQUEST_TIM7_UP          ((uint32_t)0x00000046)  /*!< DMAMUX1 TIM7 UP request   */
00321
00322 #define DMA_REQUEST_USART6_RX        ((uint32_t)0x00000047)  /*!< DMAMUX1 USART6 RX request */
00323 #define DMA_REQUEST_USART6_TX        ((uint32_t)0x00000048)  /*!< DMAMUX1 USART6 TX request */
00324
00325 #define DMA_REQUEST_I2C3_RX          ((uint32_t)0x00000049)  /*!< DMAMUX1 I2C3 RX request   */
00326 #define DMA_REQUEST_I2C3_TX          ((uint32_t)0x0000004A)  /*!< DMAMUX1 I2C3 TX request   */
00327
00328 #define DMA_REQUEST_DCMI             ((uint32_t)0x0000004B)  /*!< DMAMUX1 DCMI request      */
00329
00330 #define DMA_REQUEST_CRYP_IN          ((uint32_t)0x0000004C)  /*!< DMAMUX1 CRYP IN request   */
00331 #define DMA_REQUEST_CRYP_OUT         ((uint32_t)0x0000004D)  /*!< DMAMUX1 CRYP OUT request  */
00332
00333 #define DMA_REQUEST_HASH_IN          ((uint32_t)0x0000004E)  /*!< DMAMUX1 HASH IN request   */
00334
00335 #define DMA_REQUEST_UART7_RX         ((uint32_t)0x0000004F)  /*!< DMAMUX1 UART7 RX request  */
00336 #define DMA_REQUEST_UART7_TX         ((uint32_t)0x00000050)  /*!< DMAMUX1 UART7 TX request  */
00337 #define DMA_REQUEST_UART8_RX         ((uint32_t)0x00000051)  /*!< DMAMUX1 UART8 RX request  */
00338 #define DMA_REQUEST_UART8_TX         ((uint32_t)0x00000052)  /*!< DMAMUX1 UART8 TX request  */
00339
00340 #define DMA_REQUEST_SPI4_RX          ((uint32_t)0x00000053)  /*!< DMAMUX1 SPI4 RX request   */
00341 #define DMA_REQUEST_SPI4_TX          ((uint32_t)0x00000054)  /*!< DMAMUX1 SPI4 TX request   */
00342 #define DMA_REQUEST_SPI5_RX          ((uint32_t)0x00000055)  /*!< DMAMUX1 SPI5 RX request   */
00343 #define DMA_REQUEST_SPI5_TX          ((uint32_t)0x00000056)  /*!< DMAMUX1 SPI5 TX request   */
00344
00345 #define DMA_REQUEST_SAI1_A           ((uint32_t)0x00000057)  /*!< DMAMUX1 SAI1 A request    */
00346 #define DMA_REQUEST_SAI1_B           ((uint32_t)0x00000058)  /*!< DMAMUX1 SAI1 B request    */
00347 #define DMA_REQUEST_SAI2_A           ((uint32_t)0x00000059)  /*!< DMAMUX1 SAI2 A request    */
00348 #define DMA_REQUEST_SAI2_B           ((uint32_t)0x0000005A)  /*!< DMAMUX1 SAI2 B request    */
00349
00350 #define DMA_REQUEST_SWPMI_RX         ((uint32_t)0x0000005B)  /*!< DMAMUX1 SWPMI RX request  */
00351 #define DMA_REQUEST_SWPMI_TX         ((uint32_t)0x0000005C)  /*!< DMAMUX1 SWPMI TX request  */
00352
00353 #define DMA_REQUEST_SPDIF_RX_DT      ((uint32_t)0x0000005D)  /*!< DMAMUX1 SPDIF RXDT request*/
00354 #define DMA_REQUEST_SPDIF_RX_CS      ((uint32_t)0x0000005E)  /*!< DMAMUX1 SPDIF RXCS request*/
00355
00356 #define DMA_REQUEST_HRTIM_MASTER     ((uint32_t)0x0000005F)  /*!< DMAMUX1 HRTIM1 Master request 1 */
00357 #define DMA_REQUEST_HRTIM_TIMER_A    ((uint32_t)0x00000060)  /*!< DMAMUX1 HRTIM1 TimerA request 2 */
00358 #define DMA_REQUEST_HRTIM_TIMER_B    ((uint32_t)0x00000061)  /*!< DMAMUX1 HRTIM1 TimerB request 3 */
00359 #define DMA_REQUEST_HRTIM_TIMER_C    ((uint32_t)0x00000062)  /*!< DMAMUX1 HRTIM1 TimerC request 4 */
00360 #define DMA_REQUEST_HRTIM_TIMER_D    ((uint32_t)0x00000063)  /*!< DMAMUX1 HRTIM1 TimerD request 5 */
00361 #define DMA_REQUEST_HRTIM_TIMER_E    ((uint32_t)0x00000064)  /*!< DMAMUX1 HRTIM1 TimerE request 6 */
00362
00363 #define DMA_REQUEST_DFSDM1_FLT0      ((uint32_t)0x00000065)  /*!< DMAMUX1 DFSDM Filter0 request */
00364 #define DMA_REQUEST_DFSDM1_FLT1      ((uint32_t)0x00000066)  /*!< DMAMUX1 DFSDM Filter1 request */
00365 #define DMA_REQUEST_DFSDM1_FLT2      ((uint32_t)0x00000067)  /*!< DMAMUX1 DFSDM Filter2 request */
00366 #define DMA_REQUEST_DFSDM1_FLT3      ((uint32_t)0x00000068)  /*!< DMAMUX1 DFSDM Filter3 request */
00367
00368 #define DMA_REQUEST_TIM15_CH1        ((uint32_t)0x00000069)  /*!< DMAMUX1 TIM15 CH1 request  */
00369 #define DMA_REQUEST_TIM15_UP         ((uint32_t)0x0000006A)  /*!< DMAMUX1 TIM15 UP request   */
00370 #define DMA_REQUEST_TIM15_TRIG       ((uint32_t)0x0000006B)  /*!< DMAMUX1 TIM15 TRIG request */
00371 #define DMA_REQUEST_TIM15_COM        ((uint32_t)0x0000006C)  /*!< DMAMUX1 TIM15 COM request  */
00372
00373 #define DMA_REQUEST_TIM16_CH1        ((uint32_t)0x0000006D)  /*!< DMAMUX1 TIM16 CH1 request  */
00374 #define DMA_REQUEST_TIM16_UP         ((uint32_t)0x0000006E)  /*!< DMAMUX1 TIM16 UP request   */
00375
00376 #define DMA_REQUEST_TIM17_CH1        ((uint32_t)0x0000006F)  /*!< DMAMUX1 TIM17 CH1 request  */
00377 #define DMA_REQUEST_TIM17_UP         ((uint32_t)0x00000070)  /*!< DMAMUX1 TIM17 UP request   */
00378
00379 #define DMA_REQUEST_SAI3_A           ((uint32_t)0x00000071)  /*!< DMAMUX1 SAI3 A request  */
00380 #define DMA_REQUEST_SAI3_B           ((uint32_t)0x00000072)  /*!< DMAMUX1 SAI3 B request  */
00381
00382 #define DMA_REQUEST_ADC3             ((uint32_t)0x00000073)  /*!< DMAMUX1 ADC3  request  */
00383
00384
00385 /* D3 Domain : DMAMUX2 requests */
00386 #define BDMA_REQUEST_MEM2MEM          ((uint32_t)0x00000000)  /*!< memory to memory transfer   */
00387 #define BDMA_REQUEST_GENERATOR0       ((uint32_t)0x10000001)  /*!< DMAMUX2 request generator 0 */
00388 #define BDMA_REQUEST_GENERATOR1       ((uint32_t)0x10000002)  /*!< DMAMUX2 request generator 1 */
00389 #define BDMA_REQUEST_GENERATOR2       ((uint32_t)0x10000003)  /*!< DMAMUX2 request generator 2 */
00390 #define BDMA_REQUEST_GENERATOR3       ((uint32_t)0x10000004)  /*!< DMAMUX2 request generator 3 */
00391 #define BDMA_REQUEST_GENERATOR4       ((uint32_t)0x10000005)  /*!< DMAMUX2 request generator 4 */
00392 #define BDMA_REQUEST_GENERATOR5       ((uint32_t)0x10000006)  /*!< DMAMUX2 request generator 5 */
00393 #define BDMA_REQUEST_GENERATOR6       ((uint32_t)0x10000007)  /*!< DMAMUX2 request generator 6 */
00394 #define BDMA_REQUEST_GENERATOR7       ((uint32_t)0x10000008)  /*!< DMAMUX2 request generator 7 */
00395 #define BDMA_REQUEST_LP_UART1_RX      ((uint32_t)0x10000009)  /*!< DMAMUX2 LP_UART1_RX request */
00396 #define BDMA_REQUEST_LP_UART1_TX      ((uint32_t)0x1000000A)  /*!< DMAMUX2 LP_UART1_TX request */
00397 #define BDMA_REQUEST_SPI6_RX          ((uint32_t)0x1000000B)  /*!< DMAMUX2 SPI6 RX request     */
00398 #define BDMA_REQUEST_SPI6_TX          ((uint32_t)0x1000000C)  /*!< DMAMUX2 SPI6 TX request     */
00399 #define BDMA_REQUEST_I2C4_RX          ((uint32_t)0x1000000D)  /*!< DMAMUX2 I2C4 RX request     */
00400 #define BDMA_REQUEST_I2C4_TX          ((uint32_t)0x1000000E)  /*!< DMAMUX2 I2C4 TX request     */
00401 #define BDMA_REQUEST_SAI4_A           ((uint32_t)0x1000000F)  /*!< DMAMUX2 SAI4 A request      */
00402 #define BDMA_REQUEST_SAI4_B           ((uint32_t)0x10000010)  /*!< DMAMUX2 SAI4 B request      */
00403 #define BDMA_REQUEST_ADC3             ((uint32_t)0x10000011)  /*!< DMAMUX2 ADC3 request        */
00404
00405 /**
00406   * @}
00407   */
00408
00409 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
00410   * @brief    DMA data transfer direction
00411   * @{
00412   */
00413 #define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000U)      /*!< Peripheral to memory direction */
00414 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */
00415 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
00416 /**
00417   * @}
00418   */
00419
00420 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
00421   * @brief    DMA peripheral incremented mode
00422   * @{
00423   */
00424 #define DMA_PINC_ENABLE        ((uint32_t)DMA_SxCR_PINC)  /*!< Peripheral increment mode enable  */
00425 #define DMA_PINC_DISABLE       ((uint32_t)0x00000000U)     /*!< Peripheral increment mode disable */
00426 /**
00427   * @}
00428   */
00429
00430 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
00431   * @brief    DMA memory incremented mode
00432   * @{
00433   */
00434 #define DMA_MINC_ENABLE         ((uint32_t)DMA_SxCR_MINC)  /*!< Memory increment mode enable  */
00435 #define DMA_MINC_DISABLE        ((uint32_t)0x00000000U)     /*!< Memory increment mode disable */
00436 /**
00437   * @}
00438   */
00439
00440 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
00441   * @brief    DMA peripheral data size
00442   * @{
00443   */
00444 #define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000U)        /*!< Peripheral data alignment: Byte     */
00445 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord */
00446 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_SxCR_PSIZE_1)  /*!< Peripheral data alignment: Word     */
00447 /**
00448   * @}
00449   */
00450
00451 /** @defgroup DMA_Memory_data_size DMA Memory data size
00452   * @brief    DMA memory data size
00453   * @{
00454   */
00455 #define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000U)        /*!< Memory data alignment: Byte     */
00456 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */
00457 #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_SxCR_MSIZE_1)  /*!< Memory data alignment: Word     */
00458 /**
00459   * @}
00460   */
00461
00462 /** @defgroup DMA_mode DMA mode
00463   * @brief    DMA mode
00464   * @{
00465   */
00466 #define DMA_NORMAL         ((uint32_t)0x00000000U)       /*!< Normal mode                  */
00467 #define DMA_CIRCULAR       ((uint32_t)DMA_SxCR_CIRC)    /*!< Circular mode                */
00468 #define DMA_PFCTRL         ((uint32_t)DMA_SxCR_PFCTRL)  /*!< Peripheral flow control mode */
00469 /**
00470   * @}
00471   */
00472
00473 /** @defgroup DMA_Priority_level DMA Priority level
00474   * @brief    DMA priority levels
00475   * @{
00476   */
00477 #define DMA_PRIORITY_LOW             ((uint32_t)0x00000000U)     /*!< Priority level: Low       */
00478 #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_SxCR_PL_0)  /*!< Priority level: Medium    */
00479 #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_SxCR_PL_1)  /*!< Priority level: High      */
00480 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_SxCR_PL)    /*!< Priority level: Very High */
00481 /**
00482   * @}
00483   */
00484
00485 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
00486   * @brief    DMA FIFO direct mode
00487   * @{
00488   */
00489 #define DMA_FIFOMODE_DISABLE        ((uint32_t)0x00000000U)       /*!< FIFO mode disable */
00490 #define DMA_FIFOMODE_ENABLE         ((uint32_t)DMA_SxFCR_DMDIS)  /*!< FIFO mode enable  */
00491 /**
00492   * @}
00493   */
00494
00495 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
00496   * @brief    DMA FIFO level
00497   * @{
00498   */
00499 #define DMA_FIFO_THRESHOLD_1QUARTERFULL       ((uint32_t)0x00000000U)       /*!< FIFO threshold 1 quart full configuration  */
00500 #define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */
00501 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */
00502 #define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */
00503 /**
00504   * @}
00505   */
00506
00507 /** @defgroup DMA_Memory_burst DMA Memory burst
00508   * @brief    DMA memory burst
00509   * @{
00510   */
00511 #define DMA_MBURST_SINGLE       ((uint32_t)0x00000000U)
00512 #define DMA_MBURST_INC4         ((uint32_t)DMA_SxCR_MBURST_0)
00513 #define DMA_MBURST_INC8         ((uint32_t)DMA_SxCR_MBURST_1)
00514 #define DMA_MBURST_INC16        ((uint32_t)DMA_SxCR_MBURST)
00515 /**
00516   * @}
00517   */
00518
00519 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
00520   * @brief    DMA peripheral burst
00521   * @{
00522   */
00523 #define DMA_PBURST_SINGLE       ((uint32_t)0x00000000U)
00524 #define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)
00525 #define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)
00526 #define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)
00527 /**
00528   * @}
00529   */
00530
00531 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
00532   * @brief    DMA interrupts definition
00533   * @{
00534   */
00535 #define DMA_IT_TC                         ((uint32_t)DMA_SxCR_TCIE)
00536 #define DMA_IT_HT                         ((uint32_t)DMA_SxCR_HTIE)
00537 #define DMA_IT_TE                         ((uint32_t)DMA_SxCR_TEIE)
00538 #define DMA_IT_DME                        ((uint32_t)DMA_SxCR_DMEIE)
00539 #define DMA_IT_FE                         ((uint32_t)0x00000080U)
00540 /**
00541   * @}
00542   */
00543
00544 /** @defgroup DMA_flag_definitions DMA flag definitions
00545   * @brief    DMA flag definitions
00546   * @{
00547   */
00548 #define DMA_FLAG_FEIF0_4                    ((uint32_t)0x00800001U)
00549 #define DMA_FLAG_DMEIF0_4                   ((uint32_t)0x00800004U)
00550 #define DMA_FLAG_TEIF0_4                    ((uint32_t)0x00000008U)
00551 #define DMA_FLAG_HTIF0_4                    ((uint32_t)0x00000010U)
00552 #define DMA_FLAG_TCIF0_4                    ((uint32_t)0x00000020U)
00553 #define DMA_FLAG_FEIF1_5                    ((uint32_t)0x00000040U)
00554 #define DMA_FLAG_DMEIF1_5                   ((uint32_t)0x00000100U)
00555 #define DMA_FLAG_TEIF1_5                    ((uint32_t)0x00000200U)
00556 #define DMA_FLAG_HTIF1_5                    ((uint32_t)0x00000400U)
00557 #define DMA_FLAG_TCIF1_5                    ((uint32_t)0x00000800U)
00558 #define DMA_FLAG_FEIF2_6                    ((uint32_t)0x00010000U)
00559 #define DMA_FLAG_DMEIF2_6                   ((uint32_t)0x00040000U)
00560 #define DMA_FLAG_TEIF2_6                    ((uint32_t)0x00080000U)
00561 #define DMA_FLAG_HTIF2_6                    ((uint32_t)0x00100000U)
00562 #define DMA_FLAG_TCIF2_6                    ((uint32_t)0x00200000U)
00563 #define DMA_FLAG_FEIF3_7                    ((uint32_t)0x00400000U)
00564 #define DMA_FLAG_DMEIF3_7                   ((uint32_t)0x01000000U)
00565 #define DMA_FLAG_TEIF3_7                    ((uint32_t)0x02000000U)
00566 #define DMA_FLAG_HTIF3_7                    ((uint32_t)0x04000000U)
00567 #define DMA_FLAG_TCIF3_7                    ((uint32_t)0x08000000U)
00568 /**
00569   * @}
00570   */
00571
00572 /** @defgroup BDMA_flag_definitions BDMA flag definitions
00573   * @brief    BDMA flag definitions
00574   * @{
00575   */
00576 #define BDMA_FLAG_GL0                      ((uint32_t)0x00000001)
00577 #define BDMA_FLAG_TC0                      ((uint32_t)0x00000002)
00578 #define BDMA_FLAG_HT0                      ((uint32_t)0x00000004)
00579 #define BDMA_FLAG_TE0                      ((uint32_t)0x00000008)
00580 #define BDMA_FLAG_GL1                      ((uint32_t)0x00000010)
00581 #define BDMA_FLAG_TC1                      ((uint32_t)0x00000020)
00582 #define BDMA_FLAG_HT1                      ((uint32_t)0x00000040)
00583 #define BDMA_FLAG_TE1                      ((uint32_t)0x00000080)
00584 #define BDMA_FLAG_GL2                      ((uint32_t)0x00000100)
00585 #define BDMA_FLAG_TC2                      ((uint32_t)0x00000200)
00586 #define BDMA_FLAG_HT2                      ((uint32_t)0x00000400)
00587 #define BDMA_FLAG_TE2                      ((uint32_t)0x00000800)
00588 #define BDMA_FLAG_GL3                      ((uint32_t)0x00001000)
00589 #define BDMA_FLAG_TC3                      ((uint32_t)0x00002000)
00590 #define BDMA_FLAG_HT3                      ((uint32_t)0x00004000)
00591 #define BDMA_FLAG_TE3                      ((uint32_t)0x00008000)
00592 #define BDMA_FLAG_GL4                      ((uint32_t)0x00010000)
00593 #define BDMA_FLAG_TC4                      ((uint32_t)0x00020000)
00594 #define BDMA_FLAG_HT4                      ((uint32_t)0x00040000)
00595 #define BDMA_FLAG_TE4                      ((uint32_t)0x00080000)
00596 #define BDMA_FLAG_GL5                      ((uint32_t)0x00100000)
00597 #define BDMA_FLAG_TC5                      ((uint32_t)0x00200000)
00598 #define BDMA_FLAG_HT5                      ((uint32_t)0x00400000)
00599 #define BDMA_FLAG_TE5                      ((uint32_t)0x00800000)
00600 #define BDMA_FLAG_GL6                      ((uint32_t)0x01000000)
00601 #define BDMA_FLAG_TC6                      ((uint32_t)0x02000000)
00602 #define BDMA_FLAG_HT6                      ((uint32_t)0x04000000)
00603 #define BDMA_FLAG_TE6                      ((uint32_t)0x08000000)
00604 #define BDMA_FLAG_GL7                      ((uint32_t)0x10000000)
00605 #define BDMA_FLAG_TC7                      ((uint32_t)0x20000000)
00606 #define BDMA_FLAG_HT7                      ((uint32_t)0x40000000)
00607 #define BDMA_FLAG_TE7                      ((uint32_t)0x80000000)
00608
00609 /**
00610   * @}
00611   */
00612
00613 /**
00614   * @}
00615   */
00616
00617 /* Exported macro ------------------------------------------------------------*/
00618 /** @defgroup DMA_Exported_Macros DMA Exported Macros
00619   * @{
00620   */
00621
00622 /** @brief Reset DMA handle state
00623   * @param  __HANDLE__: specifies the DMA handle.
00624   * @retval None
00625   */
00626 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
00627
00628 /**
00629   * @brief  Return the current DMA Stream FIFO filled level.
00630   * @param  __HANDLE__: DMA handle
00631   * @retval The FIFO filling state.
00632   *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
00633   *                                              and not empty.
00634   *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
00635   *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
00636   *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
00637   *           - DMA_FIFOStatus_Empty: when FIFO is empty
00638   *           - DMA_FIFOStatus_Full: when FIFO is full
00639   */
00640 #define __HAL_DMA_GET_FS(__HANDLE__) ((IS_D2_DMA_INSTANCE(__HANDLE__))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0)
00641
00642 /**
00643   * @brief  Enable the specified DMA Stream.
00644   * @param  __HANDLE__: DMA handle
00645   * @retval None
00646   */
00647 #define __HAL_DMA_ENABLE(__HANDLE__) \
00648 ((IS_D2_DMA_INSTANCE(__HANDLE__))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |=  DMA_SxCR_EN) : \
00649 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |=  BDMA_CCR_EN))
00650
00651 /**
00652   * @brief  Disable the specified DMA Stream.
00653   * @param  __HANDLE__: DMA handle
00654   * @retval None
00655   */
00656 #define __HAL_DMA_DISABLE(__HANDLE__) \
00657 ((IS_D2_DMA_INSTANCE(__HANDLE__))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &=  ~DMA_SxCR_EN) : \
00658 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &=  ~BDMA_CCR_EN))
00659
00660 /* Interrupt & Flag management */
00661
00662 /**
00663   * @brief  Return the current DMA Stream transfer complete flag.
00664   * @param  __HANDLE__: DMA handle
00665   * @retval The specified transfer complete flag index.
00666   */
00667 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
00668 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
00669  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
00670  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
00671  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
00672  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
00673  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
00674  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
00675  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
00676  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
00677  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
00678  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
00679  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
00680  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
00681  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
00682  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
00683  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
00684  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TC0    :\
00685  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TC1    :\
00686  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TC2    :\
00687  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TC3    :\
00688  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TC4    :\
00689  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TC5    :\
00690  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6    :\
00691  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7    :\
00692  (uint32_t)0x00000000)
00693
00694 /**
00695   * @brief  Return the current DMA Stream half transfer complete flag.
00696   * @param  __HANDLE__: DMA handle
00697   * @retval The specified half transfer complete flag index.
00698   */
00699 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
00700 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
00701  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
00702  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
00703  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
00704  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
00705  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
00706  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
00707  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
00708  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
00709  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
00710  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
00711  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
00712  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
00713  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
00714  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
00715  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
00716  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_HT0    :\
00717  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_HT1    :\
00718  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_HT2    :\
00719  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_HT3    :\
00720  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_HT4    :\
00721  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_HT5    :\
00722  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6    :\
00723  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7    :\
00724  (uint32_t)0x00000000)
00725
00726 /**
00727   * @brief  Return the current DMA Stream transfer error flag.
00728   * @param  __HANDLE__: DMA handle
00729   * @retval The specified transfer error flag index.
00730   */
00731 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
00732 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
00733  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
00734  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
00735  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
00736  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
00737  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
00738  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
00739  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
00740  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
00741  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
00742  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
00743  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
00744  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
00745  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
00746  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
00747  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
00748  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TE0    :\
00749  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TE1    :\
00750  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TE2    :\
00751  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TE3    :\
00752  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TE4    :\
00753  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TE5    :\
00754  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6    :\
00755  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7    :\
00756  (uint32_t)0x00000000)
00757
00758 /**
00759   * @brief  Return the current DMA Stream FIFO error flag.
00760   * @param  __HANDLE__: DMA handle
00761   * @retval The specified FIFO error flag index.
00762   */
00763 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
00764 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
00765  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
00766  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
00767  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
00768  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
00769  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
00770  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
00771  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
00772  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
00773  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
00774  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
00775  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
00776  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\
00777  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\
00778  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\
00779  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\
00780   (uint32_t)0x00000000)
00781
00782 /**
00783   * @brief  Return the current DMA Stream direct mode error flag.
00784   * @param  __HANDLE__: DMA handle
00785   * @retval The specified direct mode error flag index.
00786   */
00787 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
00788 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
00789  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
00790  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
00791  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
00792  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
00793  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
00794  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
00795  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
00796  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
00797  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
00798  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
00799  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
00800  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\
00801  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\
00802  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\
00803  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\
00804   (uint32_t)0x00000000)
00805
00806 /**
00807   * @brief  Returns the current BDMA Channel Global interrupt flag.
00808   * @param  __HANDLE__: DMA handle
00809   * @retval The specified transfer error flag index.
00810   */
00811 #define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
00812 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\
00813  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\
00814  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_ISR_GIF2 :\
00815  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_ISR_GIF3 :\
00816  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_ISR_GIF4 :\
00817  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_ISR_GIF5 :\
00818  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\
00819  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\
00820   (uint32_t)0x00000000)
00821
00822 /**
00823   * @brief  Get the DMA Stream pending flags.
00824   * @param  __HANDLE__: DMA handle
00825   * @param  __FLAG__: Get the specified flag.
00826   *          This parameter can be any combination of the following values:
00827   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
00828   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
00829   *            @arg DMA_FLAG_TEIFx: Transfer error flag.
00830   *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
00831   *            @arg DMA_FLAG_FEIFx: FIFO error flag.
00832   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
00833   * @retval The state of FLAG (SET or RESET).
00834   */
00835 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
00836 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__))  :\
00837  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
00838  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
00839  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
00840
00841 /**
00842   * @brief  Clear the DMA Stream pending flags.
00843   * @param  __HANDLE__: DMA handle
00844   * @param  __FLAG__: specifies the flag to clear.
00845   *          This parameter can be any combination of the following values:
00846   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
00847   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
00848   *            @arg DMA_FLAG_TEIFx: Transfer error flag.
00849   *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
00850   *            @arg DMA_FLAG_FEIFx: FIFO error flag.
00851   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
00852   * @retval None
00853   */
00854 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
00855 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__))  :\
00856  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
00857  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
00858  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
00859
00860
00861 #define D2_TO_D3_DMA_IT(__DMA_IT__) \
00862 ((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
00863 (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) :\
00864 (((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE)  :\
00865 (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE)  :\
00866 ((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE :\
00867 ((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE :\
00868 ((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE :\
00869 (uint32_t)0x00000000)
00870
00871
00872 #define __HAL_DMA_D3_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
00873 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (D2_TO_D3_DMA_IT(__INTERRUPT__)))
00874
00875 #define __HAL_DMA_D2_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \
00876 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__)))
00877
00878 /**
00879   * @brief  Enable the specified DMA Stream interrupts.
00880   * @param  __HANDLE__: DMA handle
00881   * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
00882   *        This parameter can be one of the following values:
00883   *           @arg DMA_IT_TC: Transfer complete interrupt mask.
00884   *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
00885   *           @arg DMA_IT_TE: Transfer error interrupt mask.
00886   *           @arg DMA_IT_FE: FIFO error interrupt mask.
00887   *           @arg DMA_IT_DME: Direct mode error interrupt.
00888   * @retval None
00889   */
00890 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_D2_DMA_INSTANCE(__HANDLE__))?\
00891                                                         (__HAL_DMA_D2_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
00892                                                         (__HAL_DMA_D3_ENABLE_IT((__HANDLE__), (__INTERRUPT__))))
00893
00894
00895 #define __HAL_DMA_D3_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(D2_TO_D3_DMA_IT(__INTERRUPT__)))
00896
00897 #define __HAL_DMA_D2_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
00898 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__)))
00899
00900 /**
00901   * @brief  Disable the specified DMA Stream interrupts.
00902   * @param  __HANDLE__: DMA handle
00903   * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
00904   *         This parameter can be one of the following values:
00905   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
00906   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
00907   *            @arg DMA_IT_TE: Transfer error interrupt mask.
00908   *            @arg DMA_IT_FE: FIFO error interrupt mask.
00909   *            @arg DMA_IT_DME: Direct mode error interrupt.
00910   * @retval None
00911   */
00912 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_D2_DMA_INSTANCE(__HANDLE__))?\
00913                                                          (__HAL_DMA_D2_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
00914                                                          (__HAL_DMA_D3_DISABLE_IT((__HANDLE__), (__INTERRUPT__))))
00915
00916
00917 #define __HAL_DMA_D3_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (D2_TO_D3_DMA_IT(__INTERRUPT__))))
00918
00919 #define __HAL_DMA_D2_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
00920                                                         (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \
00921                                                         (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__)))
00922
00923 /**
00924   * @brief  Check whether the specified DMA Stream interrupt is enabled or not.
00925   * @param  __HANDLE__: DMA handle
00926   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
00927   *         This parameter can be one of the following values:
00928   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
00929   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
00930   *            @arg DMA_IT_TE: Transfer error interrupt mask.
00931   *            @arg DMA_IT_FE: FIFO error interrupt mask.
00932   *            @arg DMA_IT_DME: Direct mode error interrupt.
00933   * @retval The state of DMA_IT.
00934   */
00935 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((IS_D2_DMA_INSTANCE(__HANDLE__))? \
00936                                                             (__HAL_DMA_D2_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\
00937                                                             (__HAL_DMA_D3_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))))
00938
00939 /**
00940   * @brief  Writes the number of data units to be transferred on the DMA Stream.
00941   * @param  __HANDLE__: DMA handle
00942   * @param  __COUNTER__: Number of data units to be transferred (from 0 to 65535)
00943   *          Number of data items depends only on the Peripheral data format.
00944   *
00945   * @note   If Peripheral data format is Bytes: number of data units is equal
00946   *         to total number of bytes to be transferred.
00947   *
00948   * @note   If Peripheral data format is Half-Word: number of data units is
00949   *         equal to total number of bytes to be transferred / 2.
00950   *
00951   * @note   If Peripheral data format is Word: number of data units is equal
00952   *         to total  number of bytes to be transferred / 4.
00953   *
00954   * @retval The number of remaining data units in the current DMAy Streamx transfer.
00955   */
00956 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((IS_D2_DMA_INSTANCE(__HANDLE__))? \
00957                                                         (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) :\
00958                                                         (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__)))
00959
00960 /**
00961   * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
00962   * @param  __HANDLE__: DMA handle
00963   *
00964   * @retval The number of remaining data units in the current DMA Stream transfer.
00965   */
00966 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((IS_D2_DMA_INSTANCE(__HANDLE__))?\
00967                                            (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) :\
00968                                            (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR))
00969
00970 /**
00971   * @}
00972   */
00973
00974 /* Include DMA HAL Extension module */
00975 #include "stm32h7xx_hal_dma_ex.h"
00976
00977 /* Exported functions --------------------------------------------------------*/
00978
00979 /** @defgroup DMA_Exported_Functions DMA Exported Functions
00980   * @brief    DMA Exported functions
00981   * @{
00982   */
00983
00984 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
00985   * @brief   Initialization and de-initialization functions
00986   * @{
00987   */
00988 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
00989 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
00990 /**
00991   * @}
00992   */
00993
00994 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
00995   * @brief   I/O operation functions
00996   * @{
00997   */
00998 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00999 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
01000 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
01001 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
01002 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
01003 void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
01004 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
01005 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
01006
01007 /**
01008   * @}
01009   */
01010
01011 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
01012   * @brief    Peripheral State functions
01013   * @{
01014   */
01015 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
01016 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
01017 /**
01018   * @}
01019   */
01020 /**
01021   * @}
01022   */
01023 /* Private Constants -------------------------------------------------------------*/
01024 /** @defgroup DMA_Private_Constants DMA Private Constants
01025   * @brief    DMA private defines and constants
01026   * @{
01027   */
01028 /**
01029   * @}
01030   */
01031
01032 /* Private macros ------------------------------------------------------------*/
01033 /** @defgroup DMA_Private_Macros DMA Private Macros
01034   * @brief    DMA private macros
01035   * @{
01036   */
01037
01038 #define IS_DMA_D2_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3))
01039
01040 #define IS_BDMA_D3_REQUEST(REQUEST) (((REQUEST) == BDMA_REQUEST_MEM2MEM) || \
01041                                     (((REQUEST) >= BDMA_REQUEST_GENERATOR0) &&  ((REQUEST) <= BDMA_REQUEST_ADC3)))
01042
01043 #define IS_D2_DMA_INSTANCE(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) >= ((uint32_t)DMA1_Stream0)) && ((uint32_t)((__HANDLE__)->Instance) <= ((uint32_t)DMA2_Stream7)))
01044 #define IS_D3_DMA_INSTANCE(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) >= ((uint32_t)BDMA_Channel0)) && ((uint32_t)((__HANDLE__)->Instance) <= ((uint32_t)BDMA_Channel7)))
01045
01046
01047 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
01048                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
01049                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
01050
01051 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
01052
01053 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
01054                                             ((STATE) == DMA_PINC_DISABLE))
01055
01056 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
01057                                         ((STATE) == DMA_MINC_DISABLE))
01058
01059 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
01060                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
01061                                            ((SIZE) == DMA_PDATAALIGN_WORD))
01062
01063 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
01064                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
01065                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
01066
01067 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
01068                            ((MODE) == DMA_CIRCULAR) || \
01069                            ((MODE) == DMA_PFCTRL))
01070
01071 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
01072                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
01073                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
01074                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
01075
01076 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
01077                                        ((STATE) == DMA_FIFOMODE_ENABLE))
01078
01079 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
01080                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
01081                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
01082                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
01083
01084 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
01085                                     ((BURST) == DMA_MBURST_INC4)   || \
01086                                     ((BURST) == DMA_MBURST_INC8)   || \
01087                                     ((BURST) == DMA_MBURST_INC16))
01088
01089 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
01090                                         ((BURST) == DMA_PBURST_INC4)   || \
01091                                         ((BURST) == DMA_PBURST_INC8)   || \
01092                                         ((BURST) == DMA_PBURST_INC16))
01093 /**
01094   * @}
01095   */
01096
01097 /* Private functions ---------------------------------------------------------*/
01098 /** @defgroup DMA_Private_Functions DMA Private Functions
01099   * @brief    DMA private  functions
01100   * @{
01101   */
01102 /**
01103   * @}
01104   */
01105
01106 /**
01107   * @}
01108   */
01109
01110 /**
01111   * @}
01112   */
01113
01114 #ifdef __cplusplus
01115 }
01116 #endif
01117
01118 #endif /* __STM32H7xx_HAL_DMA_H */
01119
01120 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dma_ex.c Source File

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stm32h7xx_hal_dma_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dma_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   DMA Extension HAL module driver
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the DMA Extension peripheral:
00010   *           + Extended features functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                         ##### How to use this driver #####
00015   ==============================================================================
00016   [..]
00017   The DMA Extension HAL driver can be used as follows:
00018    (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
00019        for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
00020
00021    (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
00022    (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
00023        Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
00024        to respectively enable/disable the request generator.
00025
00026    (+) To handle the DMAMUX Interrupts, the function  HAL_DMA_MUX_IRQHandler should be called from
00027        the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler .
00028        As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMA_MUX_IRQHandler should be
00029        called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
00030       (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
00031
00032      -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
00033      -@-  When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
00034      -@-  In Multi (Double) buffer mode, it is possible to update the base address for
00035           the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
00036      -@-  Multi (Double) buffer mode is only possible with D2 DMAs i.e DMA1 or DMA2. not BDMA.
00037           Multi (Double) buffer mode is not possible with D3 BDMA.
00038
00039   @endverbatim
00040   ******************************************************************************
00041   * @attention
00042   *
00043   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00044   *
00045   * Redistribution and use in source and binary forms, with or without modification,
00046   * are permitted provided that the following conditions are met:
00047   *   1. Redistributions of source code must retain the above copyright notice,
00048   *      this list of conditions and the following disclaimer.
00049   *   2. Redistributions in binary form must reproduce the above copyright notice,
00050   *      this list of conditions and the following disclaimer in the documentation
00051   *      and/or other materials provided with the distribution.
00052   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00053   *      may be used to endorse or promote products derived from this software
00054   *      without specific prior written permission.
00055   *
00056   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00057   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00058   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00059   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00060   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00061   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00062   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00063   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00064   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00065   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00066   *
00067   ******************************************************************************
00068   */
00069
00070 /* Includes ------------------------------------------------------------------*/
00071 #include "stm32h7xx_hal.h"
00072
00073 /** @addtogroup STM32H7xx_HAL_Driver
00074   * @{
00075   */
00076
00077 /** @defgroup DMAEx DMAEx
00078   * @brief DMA Extended HAL module driver
00079   * @{
00080   */
00081
00082 #ifdef HAL_DMA_MODULE_ENABLED
00083
00084 /* Private types -------------------------------------------------------------*/
00085 /* Private variables ---------------------------------------------------------*/
00086 /* Private Constants ---------------------------------------------------------*/
00087 #define DMAMUX_POSITION_CxCR_SE      (uint32_t)POSITION_VAL(DMAMUX_CxCR_SE)    /*!< Required for left shift of the DMAMUX SYNC enable/disable       */
00088 #define DMAMUX_POSITION_CxCR_EGE     (uint32_t)POSITION_VAL(DMAMUX_CxCR_EGE)   /*!< Required for left shift of the DMAMUX SYNC EVENT enable/disable */
00089 /* Private macros ------------------------------------------------------------*/
00090 /* Private functions ---------------------------------------------------------*/
00091 /** @addtogroup DMAEx_Private_Functions
00092   * @{
00093   */
00094
00095 static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00096
00097 /**
00098   * @}
00099   */
00100
00101 /* Exported functions ---------------------------------------------------------*/
00102
00103 /** @addtogroup DMAEx_Exported_Functions
00104   * @{
00105   */
00106
00107
00108 /** @addtogroup DMAEx_Exported_Functions_Group1
00109   *
00110 @verbatim
00111  ===============================================================================
00112                 #####  Extended features functions  #####
00113  ===============================================================================
00114     [..]  This section provides functions allowing to:
00115       (+) Configure the source, destination address and data length and
00116           Start MultiBuffer DMA transfer
00117       (+) Configure the source, destination address and data length and
00118           Start MultiBuffer DMA transfer with interrupt
00119       (+) Change on the fly the memory0 or memory1 address.
00120
00121 @endverbatim
00122   * @{
00123   */
00124
00125
00126 /**
00127   * @brief  Starts the multi_buffer DMA Transfer.
00128   * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
00129   *                     the configuration information for the specified DMA Stream.
00130   * @param  SrcAddress: The source memory Buffer address
00131   * @param  DstAddress: The destination memory Buffer address
00132   * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
00133   * @param  DataLength: The length of data to be transferred from source to destination
00134   * @retval HAL status
00135   */
00136 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
00137 {
00138   HAL_StatusTypeDef status = HAL_OK;
00139   __IO uint32_t *ifcRegister_Base = NULL; /* DMA Stream Interrupt Clear register */
00140
00141   /* Check the parameters */
00142   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00143
00144   /* Memory-to-memory transfer not supported in double buffering mode */
00145   /* double buffering mode not supported for BDMA (D3 DMA)            */
00146   if ( (IS_D2_DMA_INSTANCE(hdma) == 0U) || (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY))
00147   {
00148     hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
00149     status = HAL_ERROR;
00150   }
00151   else
00152   {
00153     /* Process Locked */
00154     __HAL_LOCK(hdma);
00155
00156     if(HAL_DMA_STATE_READY == hdma->State)
00157     {
00158       /* Change DMA peripheral state */
00159       hdma->State = HAL_DMA_STATE_BUSY;
00160
00161       /* Enable the double buffer mode */
00162       ((DMA_Stream_TypeDef   *)hdma->Instance)->CR |= (uint32_t)DMA_SxCR_DBM;
00163
00164       /* Configure DMA Stream destination address */
00165       ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = SecondMemAddress;
00166
00167       /* Configure the source, destination address and the data length */
00168       DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
00169
00170       /* Calculate the interrupt clear flag register (IFCR) base address  */
00171       ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
00172
00173       /* Clear all flags */
00174       *ifcRegister_Base = 0x3FU << hdma->StreamIndex;
00175
00176       /* Clear the DMAMUX synchro overrun flag */
00177       hdma->DMAmuxChannelStatus->CFR |= hdma->DMAmuxChannelStatusMask;
00178
00179       if(hdma->DMAmuxRequestGen != 0U)
00180       {
00181         /* Clear the DMAMUX request generator overrun flag */
00182         hdma->DMAmuxRequestGenStatus->RGCFR |= hdma->DMAmuxRequestGenStatusMask;
00183       }
00184
00185       /* Enable the peripheral */
00186       __HAL_DMA_ENABLE(hdma);
00187     }
00188     else
00189     {
00190       /* Return error status */
00191       status = HAL_BUSY;
00192     }
00193   }
00194   return status;
00195 }
00196
00197 /**
00198   * @brief  Starts the multi_buffer DMA Transfer with interrupt enabled.
00199   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00200   *                     the configuration information for the specified DMA Stream.
00201   * @param  SrcAddress: The source memory Buffer address
00202   * @param  DstAddress: The destination memory Buffer address
00203   * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
00204   * @param  DataLength: The length of data to be transferred from source to destination
00205   * @retval HAL status
00206   */
00207 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
00208 {
00209   HAL_StatusTypeDef status = HAL_OK;
00210   __IO uint32_t *ifcRegister_Base = NULL; /* DMA Stream Interrupt Clear register */
00211
00212   /* Check the parameters */
00213   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00214
00215   /* Memory-to-memory transfer not supported in double buffering mode */
00216   /* double buffering mode not supported for BDMA (D3 DMA)            */
00217   if( (IS_D2_DMA_INSTANCE(hdma) == 0U) || (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY))
00218   {
00219     hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
00220     return HAL_ERROR;
00221   }
00222
00223   /* Process locked */
00224   __HAL_LOCK(hdma);
00225
00226   if(HAL_DMA_STATE_READY == hdma->State)
00227   {
00228     /* Change DMA peripheral state */
00229     hdma->State = HAL_DMA_STATE_BUSY;
00230
00231     /* Initialize the error code */
00232     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00233
00234     /* Enable the Double buffer mode */
00235     ((DMA_Stream_TypeDef   *)hdma->Instance)->CR |= (uint32_t)DMA_SxCR_DBM;
00236
00237     /* Configure DMA Stream destination address */
00238     ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = SecondMemAddress;
00239
00240     /* Configure the source, destination address and the data length */
00241     DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
00242
00243     /* Calculate the interrupt clear flag register (IFCR) base address  */
00244     ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
00245
00246     /* Clear all flags */
00247     *ifcRegister_Base = 0x3FU << hdma->StreamIndex;
00248
00249     /* Clear the DMAMUX synchro overrun flag */
00250     hdma->DMAmuxChannelStatus->CFR |= hdma->DMAmuxChannelStatusMask;
00251
00252     if(hdma->DMAmuxRequestGen != 0U)
00253     {
00254       /* Clear the DMAMUX request generator overrun flag */
00255       hdma->DMAmuxRequestGenStatus->RGCFR |= hdma->DMAmuxRequestGenStatusMask;
00256     }
00257
00258     /* Enable Common interrupts*/
00259     MODIFY_REG(((DMA_Stream_TypeDef   *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
00260     ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR |= DMA_IT_FE;
00261
00262     if(hdma->XferHalfCpltCallback != NULL)
00263     {
00264       /*Enable Half Transfer IT if corresponding Callback is set*/
00265       ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  |= DMA_IT_HT;
00266     }
00267
00268     /* Check if DMAMUX Synchronization is enabled*/
00269     if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0)
00270     {
00271       /* Enable DMAMUX sync overrun IT*/
00272       hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
00273     }
00274
00275     if(hdma->DMAmuxRequestGen != 0U)
00276     {
00277       /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
00278       /* enable the request gen overrun IT*/
00279       hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
00280     }
00281
00282     /* Enable the peripheral */
00283     __HAL_DMA_ENABLE(hdma);
00284   }
00285   else
00286   {
00287     /* Process unlocked */
00288     __HAL_UNLOCK(hdma);
00289
00290     /* Return error status */
00291     status = HAL_BUSY;
00292   }
00293   return status;
00294 }
00295
00296 /**
00297   * @brief  Change the memory0 or memory1 address on the fly.
00298   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00299   *                     the configuration information for the specified DMA Stream.
00300   * @param  Address:    The new address
00301   * @param  memory:     the memory to be changed, This parameter can be one of
00302   *                     the following values:
00303   *                      MEMORY0 /
00304   *                      MEMORY1
00305   * @note   The MEMORY0 address can be changed only when the current transfer use
00306   *         MEMORY1 and the MEMORY1 address can be changed only when the current
00307   *         transfer use MEMORY0.
00308   * @retval HAL status
00309   */
00310 HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
00311 {
00312   if(memory == MEMORY0)
00313   {
00314     /* change the memory0 address */
00315     ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = Address;
00316   }
00317   else
00318   {
00319     /* change the memory1 address */
00320     ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = Address;
00321   }
00322
00323   return HAL_OK;
00324 }
00325
00326 /**
00327   * @brief  Configure the DMAMUX synchronization parameters for a given DMA stream (instance).
00328   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00329   *                     the configuration information for the specified DMA Stream.
00330   * @param  pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
00331   * @retval HAL status
00332   */
00333 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
00334 {
00335   /* Check the parameters */
00336   assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
00337
00338   if(IS_D2_DMA_INSTANCE(hdma) != 0U)
00339   {
00340     assert_param(IS_D2_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
00341   }
00342   else
00343   {
00344     assert_param(IS_D3_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
00345   }
00346
00347   assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity));
00348   assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
00349   assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
00350   assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
00351
00352   /*Check if the DMA state is ready */
00353   if(hdma->State == HAL_DMA_STATE_READY)
00354   {
00355     /* Process Locked */
00356     __HAL_LOCK(hdma);
00357
00358     /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
00359     MODIFY_REG( hdma->DMAmuxChannel->CCR, \
00360                (~DMAMUX_CxCR_DMAREQ_ID) , \
00361                pSyncConfig->SyncSignalID | ((pSyncConfig->RequestNumber - 1U) << POSITION_VAL(DMAMUX_CxCR_NBREQ)) | \
00362                pSyncConfig->SyncPolarity | (pSyncConfig->SyncEnable << DMAMUX_POSITION_CxCR_SE) | \
00363                  (pSyncConfig->EventEnable << DMAMUX_POSITION_CxCR_EGE));
00364
00365       /* Process Locked */
00366     __HAL_UNLOCK(hdma);
00367
00368     return HAL_OK;
00369   }
00370   else
00371   {
00372     /*DMA State not Ready*/
00373     return HAL_ERROR;
00374   }
00375 }
00376
00377 /**
00378   * @brief  Configure the DMAMUX request generator block used by the given DMA stream (instance).
00379   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00380   *                     the configuration information for the specified DMA Stream.
00381   * @param  pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
00382   *         contains the request generator parameters.
00383   *
00384   * @retval HAL status
00385   */
00386 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
00387 {
00388   /* Check the parameters */
00389   assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
00390
00391   if(IS_D2_DMA_INSTANCE(hdma) != 0U)
00392   {
00393     assert_param(IS_D2_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
00394   }
00395   else
00396   {
00397     assert_param(IS_D3_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
00398   }
00399
00400
00401   assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
00402   assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
00403
00404   /* check if the DMA state is ready
00405      and DMA is using a DMAMUX request generator block
00406   */
00407   if((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U))
00408   {
00409     /* Process Locked */
00410     __HAL_LOCK(hdma);
00411
00412     /* Set the request generator new parameters*/
00413     hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
00414                                   ((pRequestGeneratorConfig->RequestNumber - 1U) << POSITION_VAL(DMAMUX_RGxCR_NBREQ))| \
00415                                   pRequestGeneratorConfig->Polarity;
00416    /* Process Locked */
00417    __HAL_UNLOCK(hdma);
00418
00419    return HAL_OK;
00420  }
00421  else
00422  {
00423    return HAL_ERROR;
00424  }
00425 }
00426
00427 /**
00428   * @brief  Enable the DMAMUX request generator block used by the given DMA stream (instance).
00429   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00430   *                     the configuration information for the specified DMA Stream.
00431   * @retval HAL status
00432   */
00433 HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
00434 {
00435   /* Check the parameters */
00436   assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
00437
00438   /* check if the DMA state is ready
00439      and DMA is using a DMAMUX request generator block
00440   */
00441   if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
00442   {
00443
00444     /* Enable the request generator*/
00445     hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
00446
00447    return HAL_OK;
00448  }
00449  else
00450  {
00451    return HAL_ERROR;
00452  }
00453 }
00454
00455 /**
00456   * @brief  Disable the DMAMUX request generator block used by the given DMA stream (instance).
00457   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00458   *                     the configuration information for the specified DMA Stream.
00459   * @retval HAL status
00460   */
00461 HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
00462 {
00463   /* Check the parameters */
00464   assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
00465
00466   /* check if the DMA state is ready
00467      and DMA is using a DMAMUX request generator block
00468   */
00469   if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
00470   {
00471
00472     /* Disable the request generator*/
00473     hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
00474
00475    return HAL_OK;
00476  }
00477  else
00478  {
00479    return HAL_ERROR;
00480  }
00481 }
00482
00483 /**
00484   * @brief  Handles DMAMUX interrupt request.
00485   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00486   *               the configuration information for the specified DMA Stream.
00487   * @retval None
00488   */
00489 void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
00490 {
00491   /* Check for DMAMUX Synchronization overrun */
00492   if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
00493   {
00494     /* Disable the synchro overrun interrupt */
00495     hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
00496
00497     /* Clear the DMAMUX synchro overrun flag */
00498     hdma->DMAmuxChannelStatus->CFR |= hdma->DMAmuxChannelStatusMask;
00499
00500     /* Update error code */
00501     hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
00502
00503     if(hdma->XferErrorCallback != NULL)
00504     {
00505       /* Transfer error callback */
00506       hdma->XferErrorCallback(hdma);
00507     }
00508   }
00509
00510   if(hdma->DMAmuxRequestGen != 0)
00511   {
00512    /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
00513     if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
00514     {
00515       /* Disable the request gen overrun interrupt */
00516       hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
00517
00518       /* Clear the DMAMUX request generator overrun flag */
00519       hdma->DMAmuxRequestGenStatus->RGCFR |= hdma->DMAmuxRequestGenStatusMask;
00520
00521       /* Update error code */
00522       hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
00523
00524       if(hdma->XferErrorCallback != NULL)
00525       {
00526         /* Transfer error callback */
00527         hdma->XferErrorCallback(hdma);
00528       }
00529     }
00530   }
00531 }
00532
00533
00534 /**
00535   * @}
00536   */
00537
00538 /**
00539   * @}
00540   */
00541
00542 /** @addtogroup DMAEx_Private_Functions
00543   * @{
00544   */
00545
00546 /**
00547   * @brief  Set the DMA Transfer parameter.
00548   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00549   *                     the configuration information for the specified DMA Stream.
00550   * @param  SrcAddress: The source memory Buffer address
00551   * @param  DstAddress: The destination memory Buffer address
00552   * @param  DataLength: The length of data to be transferred from source to destination
00553   * @retval HAL status
00554   */
00555 static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00556 {
00557   /* Configure DMA Stream data length */
00558   ((DMA_Stream_TypeDef   *)hdma->Instance)->NDTR = DataLength;
00559
00560   /* Peripheral to Memory */
00561   if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
00562   {
00563     /* Configure DMA Stream destination address */
00564     ((DMA_Stream_TypeDef   *)hdma->Instance)->PAR = DstAddress;
00565
00566     /* Configure DMA Stream source address */
00567     ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = SrcAddress;
00568   }
00569   /* Memory to Peripheral */
00570   else
00571   {
00572     /* Configure DMA Stream source address */
00573     ((DMA_Stream_TypeDef   *)hdma->Instance)->PAR = SrcAddress;
00574
00575     /* Configure DMA Stream destination address */
00576     ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = DstAddress;
00577   }
00578 }
00579
00580 /**
00581   * @}
00582   */
00583
00584 #endif /* HAL_DMA_MODULE_ENABLED */
00585 /**
00586   * @}
00587   */
00588
00589 /**
00590   * @}
00591   */
00592
00593 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_dma_ex.h Source File

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stm32h7xx_hal_dma_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_dma_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of DMA HAL extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_DMA_EX_H
00040 #define __STM32H7xx_HAL_DMA_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup DMAEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup DMAEx_Exported_Types DMAEx Exported Types
00059   * @brief DMAEx Exported types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  HAL DMA Memory definition
00065   */
00066 typedef enum
00067 {
00068   MEMORY0      = 0x00U,    /*!< Memory 0     */
00069   MEMORY1      = 0x01U,    /*!< Memory 1     */
00070
00071 }HAL_DMA_MemoryTypeDef;
00072
00073 /**
00074   * @brief  HAL DMAMUX Synchronization configuration structure definition
00075   */
00076 typedef struct
00077 {
00078   uint32_t SyncSignalID;  /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
00079                               This parameter can be a value of @ref DMAEx_MUX_SyncSignalID_selection */
00080
00081   uint32_t SyncPolarity;  /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
00082                               This parameter can be a value of @ref DMAEx_MUX_SyncPolarity_selection */
00083
00084   FunctionalState SyncEnable;  /*!< Specifies if the synchronization shall be enabled or disabled
00085                                     This parameter can take the value ENABLE or DISABLE*/
00086
00087
00088   FunctionalState EventEnable;    /*!< Specifies if an event shall be generated once the RequestNumber is reached.
00089                                        This parameter can take the value ENABLE or DISABLE */
00090
00091   uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event*/
00092
00093 }HAL_DMA_MuxSyncConfigTypeDef;
00094
00095
00096 /**
00097   * @brief  HAL DMAMUX request generator parameters structure definition
00098   */
00099 typedef struct
00100 {
00101  uint32_t SignalID;      /*!< Specifies the ID of the signal used for DMAMUX request generator
00102                               This parameter can be a value of @ref DMAEx_MUX_SignalGeneratorID_selection */
00103
00104   uint32_t Polarity;       /*!< Specifies the polarity of the signal on which the request is generated.
00105                              This parameter can be a value of @ref DMAEx_MUX_RequestGeneneratorPolarity_selection */
00106
00107   uint32_t RequestNumber;  /*!< Specifies the number of DMA request that will be generated after a signal event*/
00108
00109 }HAL_DMA_MuxRequestGeneratorConfigTypeDef;
00110
00111 /**
00112   * @}
00113   */
00114
00115 /* Exported constants --------------------------------------------------------*/
00116
00117 /** @defgroup DMAEx_Exported_Constants DMA Exported Constants
00118   * @brief    DMAEx Exported constants
00119   * @{
00120   */
00121
00122 /** @defgroup DMAEx_MUX_SyncSignalID_selection DMAEx MUX SyncSignalID selection
00123   * @brief    DMAEx MUX SyncSignalID selection
00124   * @{
00125   */
00126 #define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT  ((uint32_t)0x00000000)       /*!< D2 Domain synchronization Signal is DMAMUX1 Channel0 Event */
00127 #define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT  ((uint32_t)0x01000000)       /*!< D2 Domain synchronization Signal is DMAMUX1 Channel1 Event */
00128 #define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT  ((uint32_t)0x02000000)       /*!< D2 Domain synchronization Signal is DMAMUX1 Channel2 Event */
00129 #define HAL_DMAMUX1_SYNC_LPTIM1_OUT       ((uint32_t)0x03000000)       /*!< D2 Domain synchronization Signal is LPTIM1 OUT */
00130 #define HAL_DMAMUX1_SYNC_LPTIM2_OUT       ((uint32_t)0x04000000)       /*!< D2 Domain synchronization Signal is LPTIM2 OUT */
00131 #define HAL_DMAMUX1_SYNC_LPTIM3_OUT       ((uint32_t)0x05000000)       /*!< D2 Domain synchronization Signal is LPTIM3 OUT */
00132 #define HAL_DMAMUX1_SYNC_EXTI0            ((uint32_t)0x06000000)       /*!< D2 Domain synchronization Signal is EXTI0 IT   */
00133 #define HAL_DMAMUX1_SYNC_TIM12_TRGO       ((uint32_t)0x07000000)       /*!< D2 Domain synchronization Signal is TIM12 TRGO */
00134
00135 #define HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT  ((uint32_t)0x00000000)       /*!< D3 Domain synchronization Signal is DMAMUX2 Channel0 Event */
00136 #define HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT  ((uint32_t)0x01000000)       /*!< D3 Domain synchronization Signal is DMAMUX2 Channel1 Event */
00137 #define HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT  ((uint32_t)0x02000000)       /*!< D3 Domain synchronization Signal is DMAMUX2 Channel2 Event */
00138 #define HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT  ((uint32_t)0x03000000)       /*!< D3 Domain synchronization Signal is DMAMUX2 Channel3 Event */
00139 #define HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT  ((uint32_t)0x04000000)       /*!< D3 Domain synchronization Signal is DMAMUX2 Channel4 Event */
00140 #define HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT  ((uint32_t)0x05000000)       /*!< D3 Domain synchronization Signal is DMAMUX2 Channel5 Event */
00141 #define HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP  ((uint32_t)0x06000000)       /*!< D3 Domain synchronization Signal is LPUART1 RX Wakeup */
00142 #define HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP  ((uint32_t)0x07000000)       /*!< D3 Domain synchronization Signal is LPUART1 TX Wakeup */
00143 #define HAL_DMAMUX2_SYNC_LPTIM2_OUT       ((uint32_t)0x08000000)       /*!< D3 Domain synchronization Signal is LPTIM2 output */
00144 #define HAL_DMAMUX2_SYNC_LPTIM3_OUT       ((uint32_t)0x09000000)       /*!< D3 Domain synchronization Signal is LPTIM3 output */
00145 #define HAL_DMAMUX2_SYNC_I2C4_WKUP        ((uint32_t)0x0A000000)       /*!< D3 Domain synchronization Signal is I2C4 Wakeup   */
00146 #define HAL_DMAMUX2_SYNC_SPI6_WKUP        ((uint32_t)0x0B000000)       /*!< D3 Domain synchronization Signal is SPI6 Wakeup   */
00147 #define HAL_DMAMUX2_SYNC_COMP1_OUT        ((uint32_t)0x0C000000)       /*!< D3 Domain synchronization Signal is Comparator 1 output */
00148 #define HAL_DMAMUX2_SYNC_RTC_WKUP         ((uint32_t)0x0D000000)       /*!< D3 Domain synchronization Signal is RTC Wakeup */
00149 #define HAL_DMAMUX2_SYNC_EXTI0            ((uint32_t)0x0E000000)       /*!< D3 Domain synchronization Signal is EXTI0 IT   */
00150 #define HAL_DMAMUX2_SYNC_EXTI2            ((uint32_t)0x0F000000)       /*!< D3 Domain synchronization Signal is EXTI2 IT   */
00151
00152 /**
00153   * @}
00154   */
00155
00156 /** @defgroup DMAEx_MUX_SyncPolarity_selection DMAEx MUX SyncPolarity selection
00157   * @brief    DMAEx MUX SyncPolarity selection
00158   * @{
00159   */
00160 #define HAL_DMAMUX_SYNC_NO_EVENT   ((uint32_t)0x00000000)            /*!< block synchronization events        */
00161 #define HAL_DMAMUX_SYNC_RISING     ((uint32_t)DMAMUX_CxCR_SPOL_0)    /*!< synchronize with rising edge events */
00162 #define HAL_DMAMUX_SYNC_FALLING    ((uint32_t)DMAMUX_CxCR_SPOL_1)    /*!< synchronize with falling edge events */
00163 #define HAL_DMAMUX_SYNC_RISING_FALLING ((uint32_t)DMAMUX_CxCR_SPOL)  /*!< synchronize with rising and falling edge events */
00164
00165 /**
00166   * @}
00167   */
00168
00169
00170 /** @defgroup DMAEx_MUX_SignalGeneratorID_selection DMAEx MUX SignalGeneratorID selection
00171   * @brief    DMAEx MUX SignalGeneratorID selection
00172   * @{
00173   */
00174 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  ((uint32_t)0x00000000)   /*!< D2 domain Request generator Signal is DMAMUX1 Channel0 Event */
00175 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  ((uint32_t)0x00000001)   /*!< D2 domain Request generator Signal is DMAMUX1 Channel1 Event */
00176 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  ((uint32_t)0x00000002)   /*!< D2 domain Request generator Signal is DMAMUX1 Channel2 Event */
00177 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       ((uint32_t)0x00000003)   /*!< D2 domain Request generator Signal is LPTIM1 OUT */
00178 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       ((uint32_t)0x00000004)   /*!< D2 domain Request generator Signal is LPTIM2 OUT */
00179 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT       ((uint32_t)0x00000005)   /*!< D2 domain Request generator Signal is LPTIM3 OUT */
00180 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0            ((uint32_t)0x00000006)   /*!< D2 domain Request generator Signal is EXTI0 IT   */
00181 #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO       ((uint32_t)0x00000007)   /*!< D2 domain Request generator Signal is TIM12 TRGO */
00182
00183 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT  ((uint32_t)0x00000000)   /*!< D3 domain Request generator Signal is DMAMUX2 Channel0 Event */
00184 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT  ((uint32_t)0x00000001)   /*!< D3 domain Request generator Signal is DMAMUX2 Channel1 Event */
00185 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT  ((uint32_t)0x00000002)   /*!< D3 domain Request generator Signal is DMAMUX2 Channel2 Event */
00186 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT  ((uint32_t)0x00000003)   /*!< D3 domain Request generator Signal is DMAMUX2 Channel3 Event */
00187 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT  ((uint32_t)0x00000004)   /*!< D3 domain Request generator Signal is DMAMUX2 Channel4 Event */
00188 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT  ((uint32_t)0x00000005)   /*!< D3 domain Request generator Signal is DMAMUX2 Channel5 Event */
00189 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT  ((uint32_t)0x00000006)   /*!< D3 domain Request generator Signal is DMAMUX2 Channel6 Event */
00190 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP  ((uint32_t)0x00000007)   /*!< D3 domain Request generator Signal is LPUART1 RX Wakeup   */
00191 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP  ((uint32_t)0x00000008)   /*!< D3 domain Request generator Signal is LPUART1 TX Wakeup   */
00192 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP      ((uint32_t)0x00000009)   /*!< D3 domain Request generator Signal is LPTIM2 Wakeup       */
00193 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT       ((uint32_t)0x0000000A)   /*!< D3 domain Request generator Signal is LPTIM2 OUT          */
00194 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP      ((uint32_t)0x0000000B)   /*!< D3 domain Request generator Signal is LPTIM3 Wakeup       */
00195 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT       ((uint32_t)0x0000000C)   /*!< D3 domain Request generator Signal is LPTIM3 OUT          */
00196 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP      ((uint32_t)0x0000000D)   /*!< D3 domain Request generator Signal is LPTIM4 Wakeup       */
00197 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP      ((uint32_t)0x0000000E)   /*!< D3 domain Request generator Signal is LPTIM5 Wakeup       */
00198 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP        ((uint32_t)0x0000000F)   /*!< D3 domain Request generator Signal is I2C4 Wakeup         */
00199 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP        ((uint32_t)0x00000010)   /*!< D3 domain Request generator Signal is SPI6 Wakeup         */
00200 #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT        ((uint32_t)0x00000011)   /*!< D3 domain Request generator Signal is Comparator 1 output */
00201 #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT        ((uint32_t)0x00000012)   /*!< D3 domain Request generator Signal is Comparator 2 output */
00202 #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP         ((uint32_t)0x00000013)   /*!< D3 domain Request generator Signal is RTC Wakeup          */
00203 #define HAL_DMAMUX2_REQUEST_GEN_EXTI0            ((uint32_t)0x00000014)   /*!< D3 domain Request generator Signal is EXTI0               */
00204 #define HAL_DMAMUX2_REQUEST_GEN_EXTI2            ((uint32_t)0x00000015)   /*!< D3 domain Request generator Signal is EXTI2               */
00205 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT      ((uint32_t)0x00000016)   /*!< D3 domain Request generator Signal is I2C4 IT Event       */
00206 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT          ((uint32_t)0x00000017)   /*!< D3 domain Request generator Signal is SPI6 IT             */
00207 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT    ((uint32_t)0x00000018)   /*!< D3 domain Request generator Signal is LPUART1 Tx IT       */
00208 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT    ((uint32_t)0x00000019)   /*!< D3 domain Request generator Signal is LPUART1 Rx IT       */
00209 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT          ((uint32_t)0x0000001A)   /*!< D3 domain Request generator Signal is ADC3 IT             */
00210 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT    ((uint32_t)0x0000001B)   /*!< D3 domain Request generator Signal is ADC3 Analog Watchdog 1 output */
00211 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT      ((uint32_t)0x0000001C)   /*!< D3 domain Request generator Signal is BDMA Channel 0 IT    */
00212 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT      ((uint32_t)0x0000001D)   /*!< D3 domain Request generator Signal is BDMA Channel 1 IT    */
00213
00214
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup DMAEx_MUX_RequestGeneneratorPolarity_selection DMAEx MUX RequestGeneneratorPolarity selection
00220   * @brief    DMAEx MUX RequestGeneneratorPolarity selection
00221   * @{
00222   */
00223 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT       ((uint32_t)0x00000000)           /*!< block request generator events                     */
00224 #define HAL_DMAMUX_REQUEST_GEN_RISING         ((uint32_t)DMAMUX_RGxCR_GPOL_0)  /*!< generate request on rising edge events             */
00225 #define HAL_DMAMUX_REQUEST_GEN_FALLING        ((uint32_t)DMAMUX_RGxCR_GPOL_1)  /*!< generate request on falling edge events            */
00226 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING ((uint32_t)DMAMUX_RGxCR_GPOL)    /*!< generate request on rising and falling edge events */
00227
00228 /**
00229   * @}
00230   */
00231
00232 /**
00233   * @}
00234   */
00235
00236 /* Exported functions --------------------------------------------------------*/
00237 /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
00238   * @brief   DMAEx Exported functions
00239   * @{
00240   */
00241
00242 /** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
00243   * @brief   Extended features functions
00244   * @{
00245   */
00246
00247 /* IO operation functions *******************************************************/
00248 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
00249 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
00250 HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
00251 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
00252 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
00253 HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
00254 HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
00255
00256 void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
00257 /**
00258   * @}
00259   */
00260 /**
00261   * @}
00262   */
00263
00264 /* Private macros ------------------------------------------------------------*/
00265 /** @defgroup DMAEx_Private_Macros DMA Private Macros
00266   * @brief    DMAEx private macros
00267   * @{
00268   */
00269
00270 #define IS_D2_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO)
00271 #define IS_D3_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2)
00272
00273 #define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32))
00274
00275 #define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT)    || \
00276                                            ((POLARITY) == HAL_DMAMUX_SYNC_RISING)   || \
00277                                            ((POLARITY) == HAL_DMAMUX_SYNC_FALLING)  || \
00278                                            ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
00279
00280 #define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE)   || ((SYNC) == ENABLE))
00281
00282 #define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE)   || \
00283                                      ((EVENT) == ENABLE))
00284
00285 #define IS_D2_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO)
00286 #define IS_D3_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT)
00287
00288 #define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32))
00289
00290 #define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQUEST_GEN_NO_EVENT) || \
00291                                                   ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_RISING)   || \
00292                                                   ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_FALLING)   || \
00293                                                   ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_RISING_FALLING))
00294
00295 /**
00296   * @}
00297   */
00298
00299 /* Private functions ---------------------------------------------------------*/
00300 /** @defgroup DMAEx_Private_Functions DMAEx Private Functions
00301   * @brief DMAEx Private functions
00302   * @{
00303   */
00304 /**
00305   * @}
00306   */
00307
00308 /**
00309   * @}
00310   */
00311
00312 /**
00313   * @}
00314   */
00315
00316 #ifdef __cplusplus
00317 }
00318 #endif
00319
00320 #endif /* __STM32H7xx_HAL_DMA_H */
00321
00322 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_eth.c Source File

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stm32h7xx_hal_eth.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_eth.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   ETH HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Ethernet (ETH) peripheral:
00010   *           + Initialization and deinitialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Errors functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                     ##### How to use this driver #####
00018   ==============================================================================
00019      [..]
00020      The ETH HAL driver can be used as follows:
00021
00022       (#)Declare a ETH_HandleTypeDef handle structure, for example:
00023          ETH_HandleTypeDef  heth;
00024
00025       (#)Fill parameters of Init structure in heth handle
00026
00027       (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
00028
00029       (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
00030           (##) Enable the Ethernet interface clock using
00031                 (+++)  __HAL_RCC_ETH1MAC_CLK_ENABLE()
00032                 (+++)  __HAL_RCC_ETH1TX_CLK_ENABLE()
00033                 (+++)  __HAL_RCC_ETH1RX_CLK_ENABLE()
00034
00035           (##) Initialize the related GPIO clocks
00036           (##) Configure Ethernet pinout
00037           (##) Configure Ethernet NVIC interrupt (in Interrupt mode)
00038
00039       (#) Ethernet data reception is asynchronous, so call the following API
00040           to start the listening mode:
00041           (##) HAL_ETH_Start():
00042                This API starts the MAC and DMA transmission and reception process,
00043                without enabling end of transfer interrupts, in this mode user
00044                has to poll for data availability by calling HAL_ETH_IsRxDataAvailable()
00045           (##) HAL_ETH_Start_IT():
00046                This API starts the MAC and DMA transmission and reception process,
00047                end of transfer interrupts are enabled in this mode,
00048                HAL_ETH_RxCpltCallback() will be executed when an Ethernet packet is received
00049
00050       (#) When data is received (HAL_ETH_IsRxDataAvailable() returns 1 or Rx interrupt
00051           occurred), user can call the following APIs to get received data:
00052           (##) HAL_ETH_GetRxDataBuffer(): Get buffer address of received frame
00053           (##) HAL_ETH_GetRxDataLength(): Get received frame length
00054           (##) HAL_ETH_GetRxDataInfo(): Get received frame additional info,
00055                please refer to ETH_RxPacketInfo typedef structure
00056
00057       (#) For transmission path, two APIs are available:
00058          (##) HAL_ETH_Transmit(): Transmit an ETH frame in blocking mode
00059          (##) HAL_ETH_Transmit_IT(): Transmit an ETH frame in interrupt mode,
00060               HAL_ETH_TxCpltCallback() will be executed when end of transfer occur
00061
00062       (#) Communication with an external PHY device:
00063          (##) HAL_ETH_ReadPHYRegister(): Read a register from an external PHY
00064          (##) HAL_ETH_WritePHYRegister(): Write data to an external RHY register
00065
00066       (#) Configure the Ethernet MAC after ETH peripheral initialization
00067           (##) HAL_ETH_GetMACConfig(): Get MAC actual configuration into ETH_MACConfigTypeDef
00068           (##) HAL_ETH_SetMACConfig(): Set MAC configuration based on ETH_MACConfigTypeDef
00069
00070       (#) Configure the Ethernet DMA after ETH peripheral initialization
00071           (##) HAL_ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef
00072           (##) HAL_ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef
00073
00074       -@- The PTP protocol offload APIs are  not supported in this driver.
00075
00076   @endverbatim
00077   ******************************************************************************
00078   * @attention
00079   *
00080   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00081   *
00082   * Redistribution and use in source and binary forms, with or without modification,
00083   * are permitted provided that the following conditions are met:
00084   *   1. Redistributions of source code must retain the above copyright notice,
00085   *      this list of conditions and the following disclaimer.
00086   *   2. Redistributions in binary form must reproduce the above copyright notice,
00087   *      this list of conditions and the following disclaimer in the documentation
00088   *      and/or other materials provided with the distribution.
00089   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00090   *      may be used to endorse or promote products derived from this software
00091   *      without specific prior written permission.
00092   *
00093   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00094   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00095   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00096   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00097   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00098   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00099   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00100   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00101   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00102   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00103   *
00104   ******************************************************************************
00105   */
00106
00107 /* Includes ------------------------------------------------------------------*/
00108 #include "stm32h7xx_hal.h"
00109
00110 /** @addtogroup STM32H7xx_HAL_Driver
00111   * @{
00112   */
00113
00114 /** @defgroup ETH ETH
00115   * @brief ETH HAL module driver
00116   * @{
00117   */
00118 #ifdef HAL_ETH_MODULE_ENABLED
00119
00120 /* Private typedef -----------------------------------------------------------*/
00121 /* Private define ------------------------------------------------------------*/
00122 /** @addtogroup ETH_Private_Constants ETH Private Constants
00123   * @{
00124   */
00125 #define ETH_MACCR_MASK       ((uint32_t)0xFFFB7F7CU)
00126 #define ETH_MACECR_MASK      ((uint32_t)0x3F077FFFU)
00127 #define ETH_MACPFR_MASK      ((uint32_t)0x800007FFF)
00128 #define ETH_MACWTR_MASK      ((uint32_t)0x0000010FU)
00129 #define ETH_MACTFCR_MASK     ((uint32_t)0xFFFF00F2U)
00130 #define ETH_MACRFCR_MASK     ((uint32_t)0x00000003U)
00131 #define ETH_MTLTQOMR_MASK    ((uint32_t)0x00000072U)
00132 #define ETH_MTLRQOMR_MASK    ((uint32_t)0x0000007BU)
00133
00134 #define ETH_DMAMR_MASK       ((uint32_t)0x00007802U)
00135 #define ETH_DMASBMR_MASK     ((uint32_t)0x0000D001U)
00136 #define ETH_DMACCR_MASK      ((uint32_t)0x00013FFFU)
00137 #define ETH_DMACTCR_MASK     ((uint32_t)0x003F1010U)
00138 #define ETH_DMACRCR_MASK     ((uint32_t)0x803F0000U)
00139 #define ETH_MACPCSR_MASK     (ETH_MACPCSR_PWRDWN | ETH_MACPCSR_RWKPKTEN | \
00140                               ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | \
00141                               ETH_MACPCSR_RWKPFE)
00142
00143 /* Timeout values */
00144 #define ETH_SWRESET_TIMEOUT                 ((uint32_t)500U)
00145 #define ETH_MDIO_BUS_TIMEOUT                ((uint32_t)1000U)
00146
00147 #define ETH_DMARXNDESCWBF_ERRORS_MASK ((uint32_t)(ETH_DMARXNDESCWBF_DE | ETH_DMARXNDESCWBF_RE | \
00148                                                   ETH_DMARXNDESCWBF_OE | ETH_DMARXNDESCWBF_RWT |\
00149                                                   ETH_DMARXNDESCWBF_GP | ETH_DMARXNDESCWBF_CE))
00150
00151 #define ETH_MAC_US_TICK               ((uint32_t)1000000U)
00152 /**
00153   * @}
00154   */
00155
00156 /* Private macros ------------------------------------------------------------*/
00157 /** @defgroup ETH_Private_Macros ETH Private Macros
00158   * @{
00159   */
00160 /* Helper macros for TX descriptor handling */
00161 #define INCR_TX_DESC_INDEX(inx, offset) do {\
00162         (inx) += (offset);\
00163           if ((inx) >= ETH_TX_DESC_CNT){\
00164             (inx) = ((inx) - ETH_TX_DESC_CNT);}\
00165 } while (0)
00166
00167 /* Helper macros for RX descriptor handling */
00168 #define INCR_RX_DESC_INDEX(inx, offset) do {\
00169         (inx) += (offset);\
00170           if ((inx) >= ETH_RX_DESC_CNT){\
00171             (inx) = ((inx) - ETH_RX_DESC_CNT);}\
00172 } while (0)
00173 /**
00174   * @}
00175   */
00176 /* Private function prototypes -----------------------------------------------*/
00177 /** @defgroup ETH_Private_Functions   ETH Private Functions
00178   * @{
00179   */
00180 static void ETH_MAC_MDIO_ClkConfig(ETH_HandleTypeDef *heth);
00181 static void ETH_SetMACConfig(ETH_HandleTypeDef *heth,  ETH_MACConfigTypeDef *macconf);
00182 static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth,  ETH_DMAConfigTypeDef *dmaconf);
00183 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth);
00184 static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth);
00185 static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth);
00186 static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode);
00187 /**
00188   * @}
00189   */
00190
00191 /* Exported functions ---------------------------------------------------------*/
00192 /** @defgroup ETH_Exported_Functions ETH Exported Functions
00193   * @{
00194   */
00195
00196 /** @defgroup ETH_Exported_Functions_Group1 Initialization and deinitialization functions
00197   *  @brief    Initialization and Configuration functions
00198   *
00199 @verbatim
00200 ===============================================================================
00201             ##### Initialization and Configuration functions #####
00202  ===============================================================================
00203     [..]  This subsection provides a set of functions allowing to initialize and
00204           deinitialize the ETH peripheral:
00205
00206       (+) User must Implement HAL_ETH_MspInit() function in which he configures
00207           all related peripherals resources (CLOCK, GPIO and NVIC ).
00208
00209       (+) Call the function HAL_ETH_Init() to configure the selected device with
00210           the selected configuration:
00211         (++) MAC address
00212         (++) Media interface (MII or RMII)
00213         (++) Rx DMA Descriptors Tab
00214         (++) Tx DMA Descriptors Tab
00215         (++) Length of Rx Buffers
00216
00217       (+) Call the function HAL_ETH_DescAssignMemory() to assign data buffers
00218           for each Rx DMA Descriptor
00219
00220       (+) Call the function HAL_ETH_DeInit() to restore the default configuration
00221           of the selected ETH peripheral.
00222
00223 @endverbatim
00224   * @{
00225   */
00226
00227 /**
00228   * @brief  Initialize the Ethernet peripheral registers.
00229   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00230   *         the configuration information for ETHERNET module
00231   * @retval HAL status
00232   */
00233 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
00234 {
00235   uint32_t tickstart = 0;
00236
00237   if(heth == NULL)
00238   {
00239     return HAL_ERROR;
00240   }
00241
00242   /* Check the ETH peripheral state */
00243   if(heth->gState == HAL_ETH_STATE_RESET)
00244   {
00245     /* Init the low level hardware : GPIO, CLOCK, NVIC. */
00246     HAL_ETH_MspInit(heth);
00247   }
00248
00249   heth->gState = HAL_ETH_STATE_BUSY;
00250
00251   __HAL_RCC_SYSCFG_CLK_ENABLE();
00252
00253   if(heth->Init.MediaInterface == HAL_ETH_MII_MODE)
00254   {
00255     HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_MII);
00256   }
00257   else
00258   {
00259     HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII);
00260   }
00261
00262   /* Ethernet Software reset */
00263   /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
00264   /* After reset all the registers holds their respective reset values */
00265   SET_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR);
00266
00267   /* Get tick */
00268   tickstart = HAL_GetTick();
00269
00270   /* Wait for software reset */
00271   while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR))
00272   {
00273     if(((HAL_GetTick() - tickstart ) > ETH_SWRESET_TIMEOUT))
00274     {
00275       /* Set Error Code */
00276       heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
00277       /* Set State as Error */
00278       heth->gState = HAL_ETH_STATE_ERROR;
00279       /* Return Error */
00280       return HAL_ERROR;
00281     }
00282   }
00283
00284   /*------------------ MDIO CSR Clock Range Configuration --------------------*/
00285   ETH_MAC_MDIO_ClkConfig(heth);
00286
00287   /*------------------ MAC LPI 1US Tic Counter Configuration --------------------*/
00288   WRITE_REG(heth->Instance->MAC1USTCR, ((HAL_RCC_GetHCLKFreq() / ETH_MAC_US_TICK) - 1));
00289
00290   /*------------------ MAC, MTL and DMA default Configuration ----------------*/
00291   ETH_MACDMAConfig(heth);
00292
00293   /* SET DSL to 64 bit */
00294   MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_DSL, ETH_DMACCR_DSL_64BIT);
00295
00296   /* Set Receive Buffers Length (must be a multiple of 4) */
00297   if (heth->Init.RxBuffLen % 4)
00298   {
00299     /* Set Error Code */
00300     heth->ErrorCode = HAL_ETH_ERROR_PARAM;
00301     /* Set State as Error */
00302     heth->gState = HAL_ETH_STATE_ERROR;
00303     /* Return Error */
00304     return HAL_ERROR;
00305   }
00306   else
00307   {
00308     MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_RBSZ, ((heth->Init.RxBuffLen) << 1));
00309   }
00310
00311   /*------------------ DMA Tx Descriptors Configuration ----------------------*/
00312   ETH_DMATxDescListInit(heth);
00313
00314   /*------------------ DMA Rx Descriptors Configuration ----------------------*/
00315   ETH_DMARxDescListInit(heth);
00316
00317   /*--------------------- ETHERNET MAC Address Configuration ------------------*/
00318   /* Set MAC addr bits 32 to 47 */
00319   heth->Instance->MACA0HR = ((heth->Init.MACAddr[5] << 8) | heth->Init.MACAddr[4]);
00320   /* Set MAC addr bits 0 to 31 */
00321   heth->Instance->MACA0LR = ((heth->Init.MACAddr[3] << 24) | (heth->Init.MACAddr[2] << 16) | (heth->Init.MACAddr[1] << 8) | heth->Init.MACAddr[0]);
00322
00323   heth->ErrorCode = HAL_ETH_ERROR_NONE;
00324   heth->gState = HAL_ETH_STATE_READY;
00325   heth->RxState = HAL_ETH_STATE_READY;
00326
00327   return HAL_OK;
00328 }
00329
00330 /**
00331   * @brief  DeInitializes the ETH peripheral.
00332   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00333   *         the configuration information for ETHERNET module
00334   * @retval HAL status
00335   */
00336 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
00337 {
00338   /* Set the ETH peripheral state to BUSY */
00339   heth->gState = HAL_ETH_STATE_BUSY;
00340
00341   /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
00342   HAL_ETH_MspDeInit(heth);
00343
00344   /* Set ETH HAL state to Disabled */
00345   heth->gState= HAL_ETH_STATE_RESET;
00346
00347   /* Return function status */
00348   return HAL_OK;
00349 }
00350
00351 /**
00352   * @brief  Initializes the ETH MSP.
00353   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00354   *         the configuration information for ETHERNET module
00355   * @retval None
00356   */
00357 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
00358 {
00359   /* Prevent unused argument(s) compilation warning */
00360   UNUSED(heth);
00361   /* NOTE : This function Should not be modified, when the callback is needed,
00362   the HAL_ETH_MspInit could be implemented in the user file
00363   */
00364 }
00365
00366 /**
00367   * @brief  DeInitializes ETH MSP.
00368   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00369   *         the configuration information for ETHERNET module
00370   * @retval None
00371   */
00372 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
00373 {
00374   /* Prevent unused argument(s) compilation warning */
00375   UNUSED(heth);
00376   /* NOTE : This function Should not be modified, when the callback is needed,
00377   the HAL_ETH_MspDeInit could be implemented in the user file
00378   */
00379 }
00380
00381 /**
00382   * @brief  Assign memory buffers to a DMA Rx descriptor
00383   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00384   *         the configuration information for ETHERNET module
00385   * @param  Index : index of the DMA Rx descriptor
00386   *                  this parameter can be a value from 0x0 to (ETH_RX_DESC_CNT -1)
00387   * @param  pBuffer1: address of buffer1
00388   * @param  pBuffer2: address of buffer 2 if available
00389   * @retval HAL status
00390   */
00391 HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1, uint8_t *pBuffer2)
00392 {
00393   ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[Index];
00394
00395   if((pBuffer1 == NULL) || (Index >= ETH_RX_DESC_CNT))
00396   {
00397     /* Set Error Code */
00398     heth->ErrorCode = HAL_ETH_ERROR_PARAM;
00399     /* Return Error */
00400     return HAL_ERROR;
00401   }
00402
00403   /* write buffer address to RDES0 */
00404   WRITE_REG(dmarxdesc->DESC0, (uint32_t)pBuffer1);
00405   /* store buffer address */
00406   WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)pBuffer1);
00407   /* set buffer address valid bit to RDES3 */
00408   SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
00409
00410   if(pBuffer2 != NULL)
00411   {
00412     /* write buffer 2 address to RDES1 */
00413     WRITE_REG(dmarxdesc->DESC2, (uint32_t)pBuffer2);
00414      /* store buffer 2 address */
00415     WRITE_REG(dmarxdesc->BackupAddr1, (uint32_t)pBuffer2);
00416     /* set buffer 2 address valid bit to RDES3 */
00417     SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
00418   }
00419   /* set OWN bit to RDES3 */
00420   SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
00421
00422   return HAL_OK;
00423 }
00424
00425 /**
00426   * @}
00427   */
00428
00429 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
00430   *  @brief ETH Transmit and Receive functions
00431   *
00432 @verbatim
00433   ==============================================================================
00434                       ##### IO operation functions #####
00435   ==============================================================================
00436   [..]
00437     This subsection provides a set of functions allowing to manage the ETH
00438     data transfer.
00439
00440 @endverbatim
00441   * @{
00442   */
00443
00444 /**
00445   * @brief  Enables Ethernet MAC and DMA reception and transmission
00446   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00447   *         the configuration information for ETHERNET module
00448   * @retval HAL status
00449   */
00450 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
00451 {
00452   if(heth->gState == HAL_ETH_STATE_READY)
00453   {
00454     heth->gState = HAL_ETH_STATE_BUSY;
00455
00456     /* Enable the MAC transmission */
00457     SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
00458
00459     /* Enable the MAC reception */
00460     SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
00461
00462     /* Set the Flush Transmit FIFO bit */
00463     SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
00464
00465     /* Enable the DMA transmission */
00466     SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
00467
00468     /* Enable the DMA reception */
00469     SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
00470
00471     /* Clear Tx and Rx process stopped flags */
00472     heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
00473
00474     heth->gState = HAL_ETH_STATE_READY;
00475     heth->RxState = HAL_ETH_STATE_BUSY_RX;
00476
00477     return HAL_OK;
00478   }
00479   else
00480   {
00481     return HAL_ERROR;
00482   }
00483 }
00484
00485 /**
00486   * @brief  Enables Ethernet MAC and DMA reception/transmission in Interrupt mode
00487   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00488   *         the configuration information for ETHERNET module
00489   * @retval HAL status
00490   */
00491 HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
00492 {
00493   uint32_t descindex = 0, counter;
00494   ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
00495
00496   if(heth->gState == HAL_ETH_STATE_READY)
00497   {
00498     heth->gState = HAL_ETH_STATE_BUSY;
00499
00500     /* Set IOC bit to all Rx descriptors */
00501     for(counter= 0; counter < ETH_RX_DESC_CNT; counter++)
00502     {
00503       SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
00504       INCR_RX_DESC_INDEX(descindex, 1);
00505       dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
00506     }
00507
00508     /* save IT mode to ETH Handle */
00509     heth->RxDescList.ItMode = 1U;
00510
00511     /* Enable the MAC transmission */
00512     SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
00513
00514     /* Enable the MAC reception */
00515     SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
00516
00517     /* Set the Flush Transmit FIFO bit */
00518     SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
00519
00520     /* Enable the DMA transmission */
00521     SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
00522
00523     /* Enable the DMA reception */
00524     SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
00525
00526     /* Clear Tx and Rx process stopped flags */
00527     heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
00528
00529     heth->gState = HAL_ETH_STATE_READY;
00530     heth->RxState = HAL_ETH_STATE_BUSY_RX;
00531
00532     /* Enable ETH DMA interrupts:
00533     - Tx complete interrupt
00534     - Rx complete interrupt
00535     - Fatal bus interrupt
00536     */
00537     __HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE  |
00538                                    ETH_DMACIER_FBEE | ETH_DMACIER_AIE));
00539
00540     return HAL_OK;
00541   }
00542   else
00543   {
00544     return HAL_ERROR;
00545   }
00546 }
00547
00548 /**
00549   * @brief  Stop Ethernet MAC and DMA reception/transmission
00550   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00551   *         the configuration information for ETHERNET module
00552   * @retval HAL status
00553   */
00554 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
00555 {
00556   if(heth->gState != HAL_ETH_STATE_RESET)
00557   {
00558      /* Set the ETH peripheral state to BUSY */
00559     heth->gState = HAL_ETH_STATE_BUSY;
00560
00561     /* Disable the DMA transmission */
00562     CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
00563
00564     /* Disable the DMA reception */
00565     CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
00566
00567     /* Disable the MAC reception */
00568     CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE);
00569
00570     /* Set the Flush Transmit FIFO bit */
00571     SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
00572
00573     /* Disable the MAC transmission */
00574     CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
00575
00576     heth->gState = HAL_ETH_STATE_READY;
00577     heth->RxState = HAL_ETH_STATE_READY;
00578
00579     /* Return function status */
00580     return HAL_OK;
00581   }
00582   else
00583   {
00584     return HAL_ERROR;
00585   }
00586 }
00587
00588 /**
00589   * @brief  Stop Ethernet MAC and DMA reception/transmission in Interrupt mode
00590   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00591   *         the configuration information for ETHERNET module
00592   * @retval HAL status
00593   */
00594 HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
00595 {
00596   ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[0];
00597   uint32_t index;
00598
00599   if(heth->gState != HAL_ETH_STATE_RESET)
00600   {
00601     /* Set the ETH peripheral state to BUSY */
00602     heth->gState = HAL_ETH_STATE_BUSY;
00603
00604     /* Disable intrrupts:
00605     - Tx complete interrupt
00606     - Rx complete interrupt     */
00607     __HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMA_NORMAL_IT | ETH_DMA_RX_IT | ETH_DMA_TX_IT));
00608
00609     /* Disable the DMA transmission */
00610     CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
00611
00612     /* Disable the DMA reception */
00613     CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
00614
00615     /* Disable the MAC reception */
00616     CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE);
00617
00618     /* Set the Flush Transmit FIFO bit */
00619     SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
00620
00621     /* Disable the MAC transmission */
00622     CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
00623
00624     /* Clear IOC bit to all Rx descriptors */
00625     for(index = 0; index < ETH_RX_DESC_CNT; index++)
00626     {
00627       CLEAR_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
00628     }
00629
00630     heth->RxDescList.ItMode = 0U;
00631
00632     heth->gState = HAL_ETH_STATE_READY;
00633     heth->RxState = HAL_ETH_STATE_READY;
00634
00635     /* Return function status */
00636     return HAL_OK;
00637   }
00638   else
00639   {
00640     return HAL_ERROR;
00641   }
00642 }
00643
00644 /**
00645   * @brief  Sends an Ethernet Packet in polling mode.
00646   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00647   *         the configuration information for ETHERNET module
00648   * @param  pTxConfig: Hold the configuration of packet to be transmitted
00649   * @param  Timeout: timeout value
00650   * @retval HAL status
00651   */
00652 HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout)
00653 {
00654   uint32_t tickstart = 0;
00655   uint32_t lastdescid;
00656   ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
00657   ETH_DMADescTypeDef *dmatxdesc;
00658
00659   if(pTxConfig == NULL)
00660   {
00661     heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
00662     return HAL_ERROR;
00663   }
00664
00665   if((heth->gState == HAL_ETH_STATE_READY) || (heth->gState == HAL_ETH_STATE_BUSY_TX))
00666   {
00667
00668     /* Set ETH HAL State to Busy */
00669     heth->gState = HAL_ETH_STATE_BUSY_TX;
00670
00671     /* Config DMA Tx descriptor by Tx Packet info */
00672     if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != HAL_ETH_ERROR_NONE)
00673     {
00674       /* Set the ETH error code */
00675       heth->ErrorCode |= HAL_ETH_ERROR_BUSY;
00676       return HAL_ERROR;
00677     }
00678
00679     /* Save last Tx desc index to be used for Tx status */
00680     lastdescid= heth->TxDescList.CurTxDesc;
00681     dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[lastdescid];
00682
00683     /* Incr current tx desc index */
00684     INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1);
00685
00686     /* Start transmission */
00687     /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
00688     WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc]));
00689
00690     tickstart = HAL_GetTick();
00691
00692     /* Wait for data to be transmitted or timeout occured */
00693     while((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET)
00694     {
00695       if(heth->Instance->DMACSR & ETH_DMACSR_FBE)
00696       {
00697         heth->ErrorCode |= HAL_ETH_ERROR_DMA;
00698         heth->DMAErrorCode = heth->Instance->DMACSR;
00699         /* Set ETH HAL State to Ready */
00700         heth->gState = HAL_ETH_STATE_ERROR;
00701         /* Return function status */
00702         return HAL_ERROR;
00703       }
00704
00705       /* Check for the Timeout */
00706       if(Timeout != HAL_MAX_DELAY)
00707       {
00708         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00709         {
00710           heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT;
00711           heth->gState = HAL_ETH_STATE_READY;
00712           return HAL_ERROR;
00713         }
00714       }
00715     }
00716
00717     /* Set ETH HAL State to Ready */
00718     heth->gState = HAL_ETH_STATE_READY;
00719
00720     /* Return function status */
00721     return HAL_OK;
00722   }
00723   else
00724   {
00725     return HAL_ERROR;
00726   }
00727 }
00728
00729 /**
00730   * @brief  Sends an Ethernet Packet in interrupt mode.
00731   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00732   *         the configuration information for ETHERNET module
00733   * @param  pTxConfig: Hold the configuration of packet to be transmitted
00734   * @retval HAL status
00735   */
00736 HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig)
00737 {
00738   if(pTxConfig == NULL)
00739   {
00740     return HAL_ERROR;
00741   }
00742
00743   if((heth->gState == HAL_ETH_STATE_READY) || (heth->gState == HAL_ETH_STATE_BUSY_TX))
00744   {
00745     /* Set ETH HAL State to Busy */
00746     heth->gState = HAL_ETH_STATE_BUSY_TX;
00747
00748     /* Config DMA Tx descriptor by Tx Packet info */
00749     if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE)
00750     {
00751       heth->ErrorCode = HAL_ETH_ERROR_BUSY;
00752       return HAL_ERROR;
00753     }
00754
00755     /* Incr current tx desc index */
00756     INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1);
00757
00758     /* Start transmission */
00759     /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
00760     WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc]));
00761
00762     return HAL_OK;
00763
00764   }
00765   else
00766   {
00767     return HAL_ERROR;
00768   }
00769 }
00770
00771 /**
00772   * @brief  Checks for received Packets.
00773   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00774   *         the configuration information for ETHERNET module
00775   * @retval  1: A Packet is received
00776   *          0: no Packet received
00777   */
00778 uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth)
00779 {
00780   ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
00781   uint32_t descidx = dmarxdesclist->CurRxDesc;
00782   ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
00783   uint32_t descscancnt = 0;
00784   uint32_t appdesccnt = 0, firstappdescidx = 0;
00785
00786   if(dmarxdesclist->AppDescNbr != 0)
00787   {
00788     /* data already received by not yet processed*/
00789     return 0;
00790   }
00791
00792   /* Check if descriptor is not owned by DMA */
00793   while((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (descscancnt < ETH_RX_DESC_CNT))
00794   {
00795     descscancnt++;
00796
00797     /* Check if last descriptor */
00798     if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET)
00799     {
00800       /* Increment the number of descriptors to be passed to the application */
00801       appdesccnt += 1U;
00802
00803       if(appdesccnt == 1)
00804       {
00805         WRITE_REG(firstappdescidx, descidx);
00806       }
00807
00808       /* Increment current rx descriptor index */
00809       INCR_RX_DESC_INDEX(descidx, 1);
00810
00811       /* Check for Context descriptor */
00812       /* Get current descriptor address */
00813       dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
00814
00815       if((READ_BIT(dmarxdesc->DESC3,  ETH_DMARXNDESCWBF_OWN)  == (uint32_t)RESET) &&
00816          (READ_BIT(dmarxdesc->DESC3,  ETH_DMARXNDESCWBF_CTXT)  != (uint32_t)RESET))
00817       {
00818         /* Increment the number of descriptors to be passed to the application */
00819         dmarxdesclist->AppContextDesc = 1;
00820         /* Increment current rx descriptor index */
00821         INCR_RX_DESC_INDEX(descidx, 1);
00822       }
00823
00824       /* Fill information to Rx descriptors list */
00825       dmarxdesclist->CurRxDesc = descidx;
00826       dmarxdesclist->FirstAppDesc = firstappdescidx;
00827       dmarxdesclist->AppDescNbr = appdesccnt;
00828
00829       /* Return function status */
00830       return 1;
00831     }
00832     /* Check if first descriptor */
00833     else if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET)
00834     {
00835       WRITE_REG(firstappdescidx, descidx);
00836       /* Increment the number of descriptors to be passed to the application */
00837       appdesccnt = 1U;
00838
00839       /* Increment current rx descriptor index */
00840       INCR_RX_DESC_INDEX(descidx, 1U);
00841       /* Get current descriptor address */
00842       dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
00843     }
00844     /* It should be an intermediate descriptor */
00845     else
00846     {
00847       /* Increment the number of descriptors to be passed to the application */
00848       appdesccnt += 1U;
00849
00850       /* Increment current rx descriptor index */
00851       INCR_RX_DESC_INDEX(descidx, 1U);
00852       /* Get current descriptor address */
00853       dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
00854     }
00855   }
00856
00857   /* Build Descriptors if an incomplete Packet is received */
00858   if(appdesccnt > 0)
00859   {
00860     descidx = firstappdescidx;
00861     dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
00862
00863     for(descscancnt = 0; descscancnt < appdesccnt; descscancnt++)
00864     {
00865       WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0);
00866       WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
00867
00868       if (READ_REG(dmarxdesc->BackupAddr1))
00869       {
00870         WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1);
00871         SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
00872       }
00873
00874       SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
00875
00876       if(dmarxdesclist->ItMode)
00877       {
00878         SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
00879       }
00880
00881       /* Increment rx descriptor index */
00882       INCR_RX_DESC_INDEX(descidx, 1);
00883       /* Get descriptor address */
00884       dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
00885     }
00886   }
00887
00888   /* Fill information to Rx descriptors list: No received Packet */
00889   dmarxdesclist->AppDescNbr = 0U;
00890
00891   return 0;
00892 }
00893
00894 /**
00895   * @brief  This function gets the buffer address of last received Packet.
00896   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00897   *         the configuration information for ETHERNET module
00898   * @param  RxBuffer: Pointer to a ETH_BufferTypeDef structure
00899   * @retval HAL status
00900   */
00901 HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer)
00902 {
00903   ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
00904   uint32_t descidx = dmarxdesclist->FirstAppDesc;
00905   uint32_t index, accumulatedlen = 0, lastdesclen=0;
00906   __IO ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
00907
00908   if(dmarxdesclist->AppDescNbr ==0)
00909   {
00910     if(HAL_ETH_IsRxDataAvailable(heth) == 0)
00911     {
00912       /* No data to be transferred to the application */
00913       return HAL_ERROR;
00914     }
00915   }
00916
00917   /* Get intermediate descriptors buffers: in case of the Packet is splitted into multi descriptors */
00918   for(index = 0; index < (dmarxdesclist->AppDescNbr - 1); index++)
00919   {
00920     /* Both rx descriptor buffers are valid */
00921     if(dmarxdesc->BackupAddr1 != 0)
00922     {
00923       if(RxBuffer == NULL)
00924       {
00925         return HAL_ERROR;
00926       }
00927
00928       RxBuffer->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
00929       RxBuffer->len = heth->Init.RxBuffLen;
00930
00931       RxBuffer = (ETH_BufferTypeDef *)RxBuffer->next;
00932
00933       if(RxBuffer == NULL)
00934       {
00935         return HAL_ERROR;
00936       }
00937
00938       RxBuffer->buffer = (uint8_t *) dmarxdesc->BackupAddr1;
00939       RxBuffer->len =  heth->Init.RxBuffLen;
00940     }
00941     /* Only buffer 1 address is valid */
00942     else
00943     {
00944       RxBuffer->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
00945       RxBuffer->len =  heth->Init.RxBuffLen;
00946     }
00947
00948     /* get total length until this descriptor */
00949     accumulatedlen = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL);
00950
00951     /* Increment to next descriptor */
00952     INCR_RX_DESC_INDEX(descidx, 1);
00953     dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
00954
00955     /* Point to next buffer */
00956     RxBuffer = (ETH_BufferTypeDef *)RxBuffer->next;
00957   }
00958
00959   /* Get last descriptor buffers */
00960   if(RxBuffer == NULL)
00961   {
00962     return HAL_ERROR;
00963   }
00964
00965   /* last descriptor data length */
00966   lastdesclen = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - accumulatedlen;
00967
00968   /* data is in only one buffer */
00969   if(lastdesclen <= heth->Init.RxBuffLen)
00970   {
00971     RxBuffer->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
00972     RxBuffer->len = lastdesclen;
00973   }
00974   /* data is in two buffers */
00975   else if(dmarxdesc->BackupAddr1 != 0)
00976   {
00977     RxBuffer->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
00978     RxBuffer->len = heth->Init.RxBuffLen;
00979
00980     RxBuffer = (ETH_BufferTypeDef *)RxBuffer->next;
00981
00982     if(RxBuffer == NULL)
00983     {
00984       return HAL_ERROR;
00985     }
00986
00987     RxBuffer->buffer = (uint8_t *) dmarxdesc->BackupAddr1;
00988     RxBuffer->len =  lastdesclen - (heth->Init.RxBuffLen);
00989   }
00990   else /* Buffer 2 not valid*/
00991   {
00992     return HAL_ERROR;
00993   }
00994
00995   return HAL_OK;
00996 }
00997
00998 /**
00999   * @brief  This function gets the length of last received Packet.
01000   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01001   *         the configuration information for ETHERNET module
01002   * @param  Length: parameter to hold Rx packet length
01003   * @retval HAL Status
01004   */
01005 HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length)
01006 {
01007   ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
01008   uint32_t descidx = dmarxdesclist->FirstAppDesc;
01009   __IO ETH_DMADescTypeDef *dmarxdesc;
01010
01011   if(dmarxdesclist->AppDescNbr ==0)
01012   {
01013     if(HAL_ETH_IsRxDataAvailable(heth) == 0)
01014     {
01015       /* No data to be transferred to the application */
01016       return HAL_ERROR;
01017     }
01018   }
01019
01020   /* Get index of last descriptor */
01021   INCR_RX_DESC_INDEX(descidx, (dmarxdesclist->AppDescNbr-1));
01022   /* Point to last descriptor */
01023   dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
01024
01025   *Length = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL);
01026
01027   return HAL_OK;
01028 }
01029
01030 /**
01031   * @brief  Get the Rx data info (Packet type, VLAN tag, Filters status, ...)
01032   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01033   *         the configuration information for ETHERNET module
01034   * @param  RxPacketInfo: parameter to hold info of received buffer
01035   * @retval HAL status
01036   */
01037 HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo)
01038 {
01039   ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
01040   uint32_t descidx = dmarxdesclist->FirstAppDesc;
01041   __IO ETH_DMADescTypeDef *dmarxdesc;
01042
01043   if(dmarxdesclist->AppDescNbr ==0)
01044   {
01045     if(HAL_ETH_IsRxDataAvailable(heth) == 0)
01046     {
01047       /* No data to be transferred to the application */
01048       return HAL_ERROR;
01049     }
01050   }
01051
01052   /* Get index of last descriptor */
01053   INCR_RX_DESC_INDEX(descidx, ((dmarxdesclist->AppDescNbr) - 1U));
01054   /* Point to last descriptor */
01055   dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
01056
01057   if(dmarxdesc->DESC3 & ETH_DMARXNDESCWBF_ES)
01058   {
01059     RxPacketInfo->ErrorCode = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_ERRORS_MASK);
01060   }
01061   else
01062   {
01063     if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS0V))
01064     {
01065
01066       if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LT) == ETH_DMARXNDESCWBF_LT_DVLAN)
01067       {
01068         RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT);
01069         RxPacketInfo->InnerVlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_IVT) >> 16;
01070       }
01071       else if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LT) == ETH_DMARXNDESCWBF_LT_VLAN)
01072       {
01073         RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT);
01074       }
01075     }
01076
01077     if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS1V))
01078     {
01079       /* Get Payload type */
01080       RxPacketInfo->PayloadType =READ_BIT( dmarxdesc->DESC1, ETH_DMARXNDESCWBF_PT);
01081       /* Get Header type */
01082       RxPacketInfo->HeaderType = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPV4 | ETH_DMARXNDESCWBF_IPV6));
01083       /* Get Checksum status */
01084       RxPacketInfo->Checksum = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPCE | ETH_DMARXNDESCWBF_IPCB | ETH_DMARXNDESCWBF_IPHE));
01085     }
01086
01087     if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS2V))
01088     {
01089       RxPacketInfo->MacFilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_HF | ETH_DMARXNDESCWBF_DAF | ETH_DMARXNDESCWBF_SAF | ETH_DMARXNDESCWBF_VF));
01090       RxPacketInfo->L3FilterStatus = READ_BIT(dmarxdesc->DESC2,  (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM));
01091       RxPacketInfo->L4FilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM));
01092     }
01093   }
01094
01095   /* Get the segment count */
01096   WRITE_REG(RxPacketInfo->SegmentCnt, dmarxdesclist->AppDescNbr);
01097
01098   return HAL_OK;
01099 }
01100
01101 /**
01102 * @brief  This function gives back Rx Desc of the last received Packet
01103 *         to the DMA, so ETH DMA will be able to use these descriptors
01104 *         to receive next Packets.
01105 *         It should be called after processing the received Packet.
01106 * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01107 *         the configuration information for ETHERNET module
01108 * @retval HAL status.
01109 */
01110 HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth)
01111 {
01112   ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
01113   uint32_t descindex = dmarxdesclist->FirstAppDesc;
01114   __IO ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex];
01115   uint32_t totalappdescnbr = dmarxdesclist->AppDescNbr;
01116   uint32_t descscan;
01117
01118   if(dmarxdesclist->AppDescNbr ==0)
01119   {
01120     /* No Rx descriptors to build */
01121     return HAL_ERROR;
01122   }
01123
01124   if(dmarxdesclist->AppContextDesc)
01125   {
01126     /* A context descriptor is available */
01127     totalappdescnbr += 1;
01128   }
01129
01130   for(descscan =0; descscan < totalappdescnbr; descscan++)
01131   {
01132     WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0);
01133     WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
01134
01135     if (READ_REG(dmarxdesc->BackupAddr1))
01136     {
01137       WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1);
01138       SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
01139     }
01140
01141     SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
01142
01143     if(dmarxdesclist->ItMode)
01144     {
01145       SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
01146     }
01147
01148     if(descscan < (dmarxdesclist->AppDescNbr -1))
01149     {
01150       /* Increment rx descriptor index */
01151       INCR_RX_DESC_INDEX(descindex, 1);
01152       /* Get descriptor address */
01153       dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex];
01154     }
01155   }
01156
01157   /* Set the Tail pointer address to the last rx descriptor hold by the app */
01158   WRITE_REG(heth->Instance->DMACRDTPR, (uint32_t)dmarxdesc);
01159
01160   /* reset the Application desc number */
01161   WRITE_REG(dmarxdesclist->AppDescNbr, 0);
01162
01163   return HAL_OK;
01164 }
01165
01166
01167 /**
01168   * @brief  This function handles ETH interrupt request.
01169   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01170   *         the configuration information for ETHERNET module
01171   * @retval HAL status
01172   */
01173 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
01174 {
01175   /* Packet received */
01176   if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_RI) && __HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE))
01177   {
01178     /* Call this function to update handle fields */
01179     HAL_ETH_IsRxDataAvailable(heth);
01180
01181     /* Receive complete callback */
01182     HAL_ETH_RxCpltCallback(heth);
01183
01184     /* Clear the Eth DMA Rx IT pending bits */
01185     __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
01186   }
01187
01188   /* Packet transmitted */
01189   if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_TI) && __HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_TIE))
01190   {
01191     /* Transfer complete callback */
01192     HAL_ETH_TxCpltCallback(heth);
01193
01194     /* Clear the Eth DMA Tx IT pending bits */
01195     __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS);
01196
01197     heth->ErrorCode = HAL_ETH_ERROR_NONE;
01198     heth->gState = HAL_ETH_STATE_READY;
01199   }
01200
01201
01202   /* ETH DMA Error */
01203   if(__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_AIS) && __HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_AIE))
01204   {
01205     heth->ErrorCode |= HAL_ETH_ERROR_DMA;
01206
01207     /* if fatal bus error occured */
01208     if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_FBE) && __HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_FBEE))
01209     {
01210       /* Get DMA error code  */
01211       heth->DMAErrorCode = __HAL_ETH_DMA_GET_IT(heth, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS));
01212
01213       /* Disable all interrupts */
01214       __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE);
01215
01216       /* Set HAL state to ERROR */
01217       heth->gState = HAL_ETH_STATE_ERROR;
01218     }
01219     else
01220     {
01221       /* Get DMA error status  */
01222       heth->DMAErrorCode = __HAL_ETH_DMA_GET_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
01223                                                        ETH_DMACSR_RBU | ETH_DMACSR_AIS));
01224
01225       /* Clear the interrupt summary flag */
01226       __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
01227                                     ETH_DMACSR_RBU | ETH_DMACSR_AIS));
01228     }
01229
01230     /* Ethernet Error callback */
01231     HAL_ETH_DMAErrorCallback(heth);
01232   }
01233
01234   /* ETH MAC Error IT */
01235   if(__HAL_ETH_MAC_GET_IT(heth, (ETH_MACIER_RXSTSIE | ETH_MACIER_TXSTSIE)))
01236   {
01237     /* Get MAC Rx Tx status and clear Status register pending bit */
01238     heth->MACErrorCode = READ_REG(heth->Instance->MACRXTXSR);
01239
01240     heth->gState = HAL_ETH_STATE_ERROR;
01241
01242     /* Ethernet PMT callback */
01243     HAL_ETH_MACErrorCallback(heth);
01244
01245     heth->MACErrorCode = (uint32_t)(0x0U);
01246   }
01247
01248   /* ETH PMT IT */
01249   if(__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT))
01250   {
01251     /* Get MAC Wake-up source and clear the status register pending bit */
01252     heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD));
01253
01254     /* Ethernet PMT callback */
01255     HAL_ETH_PMTCallback(heth);
01256
01257     heth->MACWakeUpEvent = (uint32_t)(0x0U);
01258   }
01259
01260   /* ETH EEE IT */
01261   if(__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_LPI_IT))
01262   {
01263     /* Get MAC LPI interrupt source and clear the status register pending bit */
01264     heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU);
01265
01266     /* Ethernet EEE callback */
01267     HAL_ETH_EEECallback(heth);
01268
01269     heth->MACLPIEvent = (uint32_t)(0x0U);
01270   }
01271
01272   /* check ETH WAKEUP exti flag */
01273   if(__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != RESET)
01274   {
01275     /* Clear ETH WAKEUP Exti pending bit */
01276     __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
01277     /* ETH WAKEUP interrupt user callback */
01278     HAL_ETH_WakeUpCallback(heth);
01279   }
01280 }
01281
01282 /**
01283   * @brief  Tx Transfer completed callbacks.
01284   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01285   *         the configuration information for ETHERNET module
01286   * @retval None
01287   */
01288 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
01289 {
01290   /* Prevent unused argument(s) compilation warning */
01291   UNUSED(heth);
01292   /* NOTE : This function Should not be modified, when the callback is needed,
01293   the HAL_ETH_TxCpltCallback could be implemented in the user file
01294   */
01295 }
01296
01297 /**
01298   * @brief  Rx Transfer completed callbacks.
01299   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01300   *         the configuration information for ETHERNET module
01301   * @retval None
01302   */
01303 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
01304 {
01305   /* Prevent unused argument(s) compilation warning */
01306   UNUSED(heth);
01307   /* NOTE : This function Should not be modified, when the callback is needed,
01308   the HAL_ETH_RxCpltCallback could be implemented in the user file
01309   */
01310 }
01311
01312 /**
01313   * @brief  Ethernet DMA transfer error callbacks
01314   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01315   *         the configuration information for ETHERNET module
01316   * @retval None
01317   */
01318 __weak void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth)
01319 {
01320   /* NOTE : This function Should not be modified, when the callback is needed,
01321   the HAL_ETH_DMAErrorCallback could be implemented in the user file
01322   */
01323 }
01324
01325 /**
01326 * @brief  Ethernet MAC transfer error callbacks
01327   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01328   *         the configuration information for ETHERNET module
01329   * @retval None
01330   */
01331 __weak void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth)
01332 {
01333   /* Prevent unused argument(s) compilation warning */
01334   UNUSED(heth);
01335   /* NOTE : This function Should not be modified, when the callback is needed,
01336   the HAL_ETH_MACErrorCallback could be implemented in the user file
01337   */
01338 }
01339
01340 /**
01341   * @brief  Ethernet Power Management module IT callback
01342   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01343   *         the configuration information for ETHERNET module
01344   * @retval None
01345   */
01346 __weak void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth)
01347 {
01348   /* Prevent unused argument(s) compilation warning */
01349   UNUSED(heth);
01350   /* NOTE : This function Should not be modified, when the callback is needed,
01351   the HAL_ETH_PMTCallback could be implemented in the user file
01352   */
01353 }
01354
01355 /**
01356   * @brief  Energy Efficient Etherent IT callback
01357   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01358   *         the configuration information for ETHERNET module
01359   * @retval None
01360   */
01361 __weak void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth)
01362 {
01363   /* Prevent unused argument(s) compilation warning */
01364   UNUSED(heth);
01365   /* NOTE : This function Should not be modified, when the callback is needed,
01366   the HAL_ETH_EEECallback could be implemented in the user file
01367   */
01368 }
01369
01370 /**
01371   * @brief  ETH WAKEUP interrupt callback
01372   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01373   *         the configuration information for ETHERNET module
01374   * @retval None
01375   */
01376 __weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth)
01377 {
01378   /* Prevent unused argument(s) compilation warning */
01379   UNUSED(heth);
01380   /* NOTE : This function Should not be modified, when the callback is needed,
01381             the HAL_ETH_WakeUpCallback could be implemented in the user file
01382    */
01383 }
01384
01385 /**
01386   * @brief  Read a PHY register
01387   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01388   *         the configuration information for ETHERNET module
01389   * @param  PHYAddr: PHY port address, must be a value from 0 to 31
01390   * @param  PHYReg: PHY register address, must be a value from 0 to 31
01391   * @param pRegValue: parameter to hold read value
01392   * @retval HAL status
01393   */
01394 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue)
01395 {
01396   uint32_t tmpreg = 0;
01397   uint32_t tickstart = 0;
01398
01399   /* Check for the Busy flag */
01400   if(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB))
01401   {
01402     return HAL_ERROR;
01403   }
01404
01405   /* Get the  MACMDIOAR value */
01406   WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
01407
01408   /* Prepare the MDIO Address Register value
01409      - Set the PHY device address
01410      - Set the PHY register address
01411      - Set the read mode
01412      - Set the MII Busy bit */
01413
01414   MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr <<21));
01415   MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
01416   MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_RD);
01417   SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
01418
01419   /* Write the result value into the MDII Address register */
01420   WRITE_REG(heth->Instance->MACMDIOAR, tmpreg);
01421
01422   tickstart = HAL_GetTick();
01423
01424   /* Wait for the Busy flag */
01425   while(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB))
01426   {
01427     if(((HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT))
01428     {
01429       return HAL_ERROR;
01430     }
01431   }
01432
01433   /* Get MACMIIDR value */
01434   WRITE_REG(*pRegValue, (uint16_t)heth->Instance->MACMDIODR);
01435
01436   return HAL_OK;
01437 }
01438
01439
01440 /**
01441   * @brief  Writes to a PHY register.
01442   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01443   *         the configuration information for ETHERNET module
01444   * @param  PHYAddr: PHY port address, must be a value from 0 to 31
01445   * @param  PHYReg: PHY register address, must be a value from 0 to 31
01446   * @param  RegValue: the value to write
01447   * @retval HAL status
01448   */
01449 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue)
01450 {
01451   uint32_t tmpreg = 0;
01452   uint32_t tickstart = 0;
01453
01454   /* Check for the Busy flag */
01455   if(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB))
01456   {
01457     return HAL_ERROR;
01458   }
01459
01460   /* Get the  MACMDIOAR value */
01461   WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
01462
01463   /* Prepare the MDIO Address Register value
01464      - Set the PHY device address
01465      - Set the PHY register address
01466      - Set the write mode
01467      - Set the MII Busy bit */
01468
01469   MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr <<21));
01470   MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
01471   MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_WR);
01472   SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
01473
01474
01475   /* Give the value to the MII data register */
01476   WRITE_REG(ETH->MACMDIODR, (uint16_t)RegValue);
01477
01478   /* Write the result value into the MII Address register */
01479   WRITE_REG(ETH->MACMDIOAR, tmpreg);
01480
01481   tickstart = HAL_GetTick();
01482
01483   /* Wait for the Busy flag */
01484   while(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB))
01485   {
01486     if(((HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT))
01487     {
01488       return HAL_ERROR;
01489     }
01490   }
01491
01492   return HAL_OK;
01493 }
01494
01495 /**
01496   * @}
01497   */
01498
01499 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
01500   *  @brief   ETH control functions
01501   *
01502 @verbatim
01503   ==============================================================================
01504                       ##### Peripheral Control functions #####
01505   ==============================================================================
01506   [..]
01507     This subsection provides a set of functions allowing to control the ETH
01508     peripheral.
01509
01510 @endverbatim
01511   * @{
01512   */
01513 /**
01514   * @brief  Get the configuration of the MAC and MTL subsystems.
01515   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01516   *         the configuration information for ETHERNET module
01517   * @param  macconf: pointer to a ETH_MACConfigTypeDef structure that will hold
01518   *         the configuration of the MAC.
01519   * @retval HAL Status
01520   */
01521 HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
01522 {
01523   if (macconf == NULL)
01524   {
01525     return HAL_ERROR;
01526   }
01527
01528   /* Get MAC parameters */
01529   macconf->PreambleLength = READ_BIT(heth->Instance->MACCR, ETH_MACCR_PRELEN);
01530   macconf->DeferralCheck = (FunctionalState)(READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC)>> 4);
01531   macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL);
01532   macconf->RetryTransmission = (FunctionalState)(!(READ_BIT(heth->Instance->MACCR, ETH_MACCR_DR) >> 8));
01533   macconf->CarrierSenseDuringTransmit = (FunctionalState)(READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9);
01534   macconf->ReceiveOwn = (FunctionalState)(!(READ_BIT(heth->Instance->MACCR, ETH_MACCR_DO) >> 10));
01535   macconf->CarrierSenseBeforeTransmit = (FunctionalState)(READ_BIT(heth->Instance->MACCR, ETH_MACCR_ECRSFD) >> 11);
01536   macconf->LoopbackMode = (FunctionalState)(READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12);
01537   macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM);
01538   macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES);
01539   macconf->JumboPacket = (FunctionalState)(READ_BIT(heth->Instance->MACCR, ETH_MACCR_JE) >> 16);
01540   macconf->Jabber = (FunctionalState)(!(READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >>17));
01541   macconf->Watchdog = (FunctionalState)(!(READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >>19));
01542   macconf->AutomaticPadCRCStrip = (FunctionalState)(READ_BIT(heth->Instance->MACCR, ETH_MACCR_ACS) >> 20);
01543   macconf->CRCStripTypePacket = (FunctionalState)(READ_BIT(heth->Instance->MACCR, ETH_MACCR_CST) >> 21);
01544   macconf->Support2KPacket = (FunctionalState)(READ_BIT(heth->Instance->MACCR, ETH_MACCR_S2KP) >> 22);
01545   macconf->GiantPacketSizeLimitControl = (FunctionalState)(READ_BIT(heth->Instance->MACCR, ETH_MACCR_GPSLCE) >> 23);
01546   macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPG);
01547   macconf->ChecksumOffload = (FunctionalState)(READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPC) >> 27);
01548   macconf->SourceAddrControl = READ_BIT(heth->Instance->MACCR, ETH_MACCR_SARC);
01549
01550   macconf->GiantPacketSizeLimit = READ_BIT(heth->Instance->MACECR, ETH_MACECR_GPSL);
01551   macconf->CRCCheckingRxPackets = (FunctionalState)(!(READ_BIT(heth->Instance->MACECR, ETH_MACECR_DCRCC) >> 16));
01552   macconf->SlowProtocolDetect = (FunctionalState)(READ_BIT(heth->Instance->MACECR, ETH_MACECR_SPEN) >> 17);
01553   macconf->UnicastSlowProtocolPacketDetect = (FunctionalState)(READ_BIT(heth->Instance->MACECR, ETH_MACECR_USP) >> 18);
01554   macconf->ExtendedInterPacketGap = (FunctionalState)(READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24);
01555   macconf->ExtendedInterPacketGapVal = READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPG) >> 25;
01556
01557
01558   macconf->ProgrammableWatchdog = (FunctionalState)(READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_PWE) >> 8);
01559   macconf->WatchdogTimeout = READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_WTO);
01560
01561   macconf->TransmitFlowControl = (FunctionalState)(READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_TFE) >> 1);
01562   macconf->ZeroQuantaPause = (FunctionalState)(!(READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_DZPQ) >> 7));
01563   macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PLT);
01564   macconf->PauseTime = (READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PT) >> 16);
01565
01566
01567   macconf->ReceiveFlowControl = (FunctionalState)READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_RFE);
01568   macconf->UnicastPausePacketDetect = (FunctionalState)(READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1);
01569
01570   macconf->TransmitQueueMode = READ_BIT(heth->Instance->MTLTQOMR, (ETH_MTLTQOMR_TTC | ETH_MTLTQOMR_TSF));
01571
01572   macconf->ReceiveQueueMode = READ_BIT(heth->Instance->MTLRQOMR, (ETH_MTLRQOMR_RTC | ETH_MTLRQOMR_RSF));
01573   macconf->ForwardRxUndersizedGoodPacket = (FunctionalState)(READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FUP) >> 3);
01574   macconf->ForwardRxErrorPacket = (FunctionalState)(READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FEP) >> 4);
01575   macconf->DropTCPIPChecksumErrorPacket = (FunctionalState)(!(READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_DISTCPEF) >> 6));
01576
01577   return HAL_OK;
01578 }
01579
01580 /**
01581   * @brief  Get the configuration of the DMA.
01582   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01583   *         the configuration information for ETHERNET module
01584   * @param  dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold
01585   *         the configuration of the ETH DMA.
01586   * @retval HAL Status
01587   */
01588 HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
01589 {
01590   if (dmaconf == NULL)
01591   {
01592     return HAL_ERROR;
01593   }
01594
01595   dmaconf->AddressAlignedBeats = (FunctionalState)(READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_AAL) >> 12);
01596   dmaconf->BurstMode = READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_FB | ETH_DMASBMR_MB);
01597   dmaconf->RebuildINCRxBurst = (FunctionalState)(READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_RB)>> 15);
01598
01599   dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMAMR, (ETH_DMAMR_TXPR |ETH_DMAMR_PR | ETH_DMAMR_DA));
01600
01601   dmaconf->PBLx8Mode =  (FunctionalState)(READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_8PBL)>> 16);
01602   dmaconf->MaximumSegmentSize = READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_MSS);
01603
01604   dmaconf->FlushRxPacket = (FunctionalState)(READ_BIT(heth->Instance->DMACRCR,  ETH_DMACRCR_RPF) >> 31);
01605   dmaconf->RxDMABurstLength = READ_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_RPBL);
01606
01607   dmaconf->SecondPacketOperate = (FunctionalState)(READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_OSP) >> 4);
01608   dmaconf->TCPSegmentation = (FunctionalState)(READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TSE) >> 12);
01609   dmaconf->TxDMABurstLength = READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TPBL);
01610
01611   return HAL_OK;
01612 }
01613
01614 /**
01615   * @brief  Set the MAC configuration.
01616   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01617   *         the configuration information for ETHERNET module
01618   * @param  macconf: pointer to a ETH_MACConfigTypeDef structure that contains
01619   *         the configuration of the MAC.
01620   * @retval HAL status
01621   */
01622 HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth,  ETH_MACConfigTypeDef *macconf)
01623 {
01624   if(macconf == NULL)
01625   {
01626     return HAL_ERROR;
01627   }
01628
01629   if(heth->RxState == HAL_ETH_STATE_READY)
01630   {
01631     ETH_SetMACConfig(heth, macconf);
01632
01633     return HAL_OK;
01634   }
01635   else
01636   {
01637     return HAL_ERROR;
01638   }
01639 }
01640
01641 /**
01642   * @brief  Set the ETH DMA configuration.
01643   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01644   *         the configuration information for ETHERNET module
01645   * @param  dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold
01646   *         the configuration of the ETH DMA.
01647   * @retval HAL status
01648   */
01649 HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth,  ETH_DMAConfigTypeDef *dmaconf)
01650 {
01651   if(dmaconf == NULL)
01652   {
01653     return HAL_ERROR;
01654   }
01655
01656   if(heth->RxState == HAL_ETH_STATE_READY)
01657   {
01658     ETH_SetDMAConfig(heth, dmaconf);
01659
01660     return HAL_OK;
01661   }
01662   else
01663   {
01664     return HAL_ERROR;
01665   }
01666 }
01667
01668 /**
01669   * @brief  Configures the Clock range of ETH MDIO interface.
01670   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01671   *         the configuration information for ETHERNET module
01672   * @retval None
01673   */
01674 void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
01675 {
01676         uint32_t tmpreg = 0;
01677         uint32_t hclk = 0;
01678
01679   /* Get the ETHERNET MACMDIOAR value */
01680   tmpreg = (heth->Instance)->MACMDIOAR;
01681
01682         /* Clear CSR Clock Range bits */
01683   tmpreg &= ~ETH_MACMDIOAR_CR;
01684
01685         /* Get hclk frequency value */
01686   hclk = HAL_RCC_GetHCLKFreq();
01687
01688         /* Set CR bits depending on hclk value */
01689   if((hclk >= 20000000)&&(hclk < 35000000))
01690   {
01691     /* CSR Clock Range between 20-35 MHz */
01692     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
01693   }
01694   else if((hclk >= 35000000)&&(hclk < 60000000))
01695   {
01696     /* CSR Clock Range between 35-60 MHz */
01697     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
01698   }
01699   else if((hclk >= 60000000)&&(hclk < 100000000))
01700   {
01701     /* CSR Clock Range between 60-100 MHz */
01702     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
01703   }
01704   else if((hclk >= 100000000)&&(hclk < 150000000))
01705   {
01706     /* CSR Clock Range between 100-150 MHz */
01707     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
01708   }
01709   else /* (hclk >= 150000000)&&(hclk <= 200000000) */
01710   {
01711     /* CSR Clock Range between 150-200 MHz */
01712     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
01713   }
01714
01715   /* Configure the CSR Clock Range */
01716   (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
01717 }
01718
01719 /**
01720   * @brief  Set the ETH MAC (L2) Filters configuration.
01721   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01722   *         the configuration information for ETHERNET module
01723   * @param  pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that contains
01724   *         the configuration of the ETH MAC filters.
01725   * @retval HAL status
01726   */
01727 HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
01728 {
01729   uint32_t filterconfig = 0;
01730
01731   if(pFilterConfig == NULL)
01732   {
01733     return HAL_ERROR;
01734   }
01735
01736   filterconfig = (pFilterConfig->PromiscuousMode |
01737                   ((uint32_t)pFilterConfig->HashUnicast << 1) |
01738                     ((uint32_t)pFilterConfig->HashMulticast << 2)  |
01739                       ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) |
01740                         ((uint32_t)pFilterConfig->PassAllMulticast << 4) |
01741                           ((uint32_t)!pFilterConfig->BroadcastFilter << 5) |
01742                             ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) |
01743                               ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) |
01744                                 ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) |
01745                                   ((uint32_t)pFilterConfig->ReceiveAllMode << 31) |
01746                                     pFilterConfig->ControlPacketsFilter);
01747
01748   MODIFY_REG(heth->Instance->MACPFR, ETH_MACPFR_MASK, filterconfig);
01749
01750   return HAL_OK;
01751 }
01752
01753 /**
01754   * @brief  Get the ETH MAC (L2) Filters configuration.
01755   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01756   *         the configuration information for ETHERNET module
01757   * @param  pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that will hold
01758   *         the configuration of the ETH MAC filters.
01759   * @retval HAL status
01760   */
01761 HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
01762 {
01763   if(pFilterConfig == NULL)
01764   {
01765     return HAL_ERROR;
01766   }
01767
01768   pFilterConfig->PromiscuousMode = (FunctionalState)(READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PR));
01769   pFilterConfig->HashUnicast = (FunctionalState)(READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HUC) >> 1);
01770   pFilterConfig->HashMulticast = (FunctionalState)(READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HMC) >> 2);
01771   pFilterConfig->DestAddrInverseFiltering = (FunctionalState)(READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DAIF) >> 3);
01772   pFilterConfig->PassAllMulticast = (FunctionalState)(READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PM) >> 4);
01773   pFilterConfig->BroadcastFilter = (FunctionalState)(!(READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5));
01774   pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PCF);
01775   pFilterConfig->SrcAddrInverseFiltering = (FunctionalState)(READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAIF) >> 8);
01776   pFilterConfig->SrcAddrFiltering = (FunctionalState)(READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAF) >> 9);
01777   pFilterConfig->HachOrPerfectFilter = (FunctionalState)(READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HPF) >> 10);
01778   pFilterConfig->ReceiveAllMode = (FunctionalState)(READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_RA) >> 31);
01779
01780   return HAL_OK;
01781 }
01782
01783 /**
01784   * @brief  Set the source MAC Address to be matched.
01785   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01786   *         the configuration information for ETHERNET module
01787   * @param  AddrNbr: The MAC address to configure
01788   *          This parameter must be a value of the following:
01789   *            ETH_MAC_ADDRESS1
01790   *            ETH_MAC_ADDRESS2
01791   *            ETH_MAC_ADDRESS3
01792   * @param  pMACAddr: Pointer to MAC address buffer data (6 bytes)
01793   * @retval HAL status
01794   */
01795 HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr)
01796 {
01797   uint32_t macaddrhr, macaddrlr;
01798
01799   if(pMACAddr == NULL)
01800   {
01801     return HAL_ERROR;
01802   }
01803
01804   /* Get mac addr high reg offset */
01805   macaddrhr = ((uint32_t)&(heth->Instance->MACA0HR) + AddrNbr);
01806   /* Get mac addr low reg offset */
01807   macaddrlr = ((uint32_t)&(heth->Instance->MACA0LR) + AddrNbr);
01808
01809   /* Set MAC addr bits 32 to 47 */
01810   (*(__IO uint32_t *)macaddrhr) = ((pMACAddr[5] << 8) | pMACAddr[4]);
01811   /* Set MAC addr bits 0 to 31 */
01812   (*(__IO uint32_t *)macaddrlr) = ((pMACAddr[3] << 24) | (pMACAddr[2] << 16) | (pMACAddr[1] << 8) | pMACAddr[0]);
01813
01814    /* Enable address and set source address bit */
01815   (*(__IO uint32_t *)macaddrhr) |= (ETH_MACAHR_SA | ETH_MACAHR_AE);
01816
01817   return HAL_OK;
01818 }
01819
01820 /**
01821   * @brief  Set the ETH Hash Table Value.
01822   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01823   *         the configuration information for ETHERNET module
01824   * @param  pHashTable: pointer to a table of two 32 bit values, that contains
01825   *         the 64 bits of the hash table.
01826   * @retval HAL status
01827   */
01828 HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable)
01829 {
01830   if(pHashTable == NULL)
01831   {
01832     return HAL_ERROR;
01833   }
01834
01835   heth->Instance->MACHT0R = pHashTable[0];
01836   heth->Instance->MACHT1R = pHashTable[1];
01837
01838   return HAL_OK;
01839 }
01840
01841 /**
01842   * @brief  Set the VLAN Identifier for Rx packets
01843   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01844   *         the configuration information for ETHERNET module
01845   * @param  ComparisonBits: 12 or 16 bit comparison mode
01846             must be a value of @ref ETH_VLAN_Tag_Comparison
01847   * @param  VLANIdentifier: VLAN Identifier value
01848   * @retval None
01849   */
01850 void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier)
01851 {
01852   if(ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT)
01853   {
01854     MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL , VLANIdentifier);
01855     CLEAR_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV);
01856   }
01857   else
01858   {
01859     MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL_VID , VLANIdentifier);
01860     SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV);
01861   }
01862 }
01863
01864 /**
01865   * @brief  Enters the Power down mode.
01866   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01867   *         the configuration information for ETHERNET module
01868   * @param  pPowerDownConfig: a pointer to ETH_PowerDownConfigTypeDef structure
01869   *         that contains the Power Down configration
01870   * @retval None.
01871   */
01872 void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig)
01873 {
01874   uint32_t powerdownconfig;
01875
01876   powerdownconfig = (((uint32_t)pPowerDownConfig->MagicPacket << 1) |
01877                      ((uint32_t)pPowerDownConfig->WakeUpPacket << 2) |
01878                        ((uint32_t)pPowerDownConfig->GlobalUnicast << 9) |
01879                          ((uint32_t)pPowerDownConfig->WakeUpForward << 10) |
01880                            ETH_MACPCSR_PWRDWN);
01881
01882   /* Enable PMT interrupt */
01883   __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_PMTIE);
01884
01885   MODIFY_REG(heth->Instance->MACPCSR, ETH_MACPCSR_MASK, powerdownconfig);
01886 }
01887
01888 /**
01889   * @brief  Exits from the Power down mode.
01890   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01891   *         the configuration information for ETHERNET module
01892   * @retval None.
01893   */
01894 void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth)
01895 {
01896   /* clear wake up sources */
01897   CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKPKTEN | ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | ETH_MACPCSR_RWKPFE);
01898
01899   if(READ_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN))
01900   {
01901     /* Exit power down mode */
01902     CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN);
01903   }
01904
01905   /* Disable PMT interrupt */
01906   __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_PMTIE);
01907 }
01908
01909 /**
01910   * @brief  Set the WakeUp filter.
01911   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01912   *         the configuration information for ETHERNET module
01913   * @param  pFilter: pointer to filter registers values
01914   * @param  Count: number of filter registers, must be from 1 to 8.
01915   * @retval None.
01916   */
01917 HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count)
01918 {
01919   uint32_t regindex;
01920
01921   if(pFilter == NULL)
01922   {
01923     return HAL_ERROR;
01924   }
01925
01926   /* Reset Filter Pointer */
01927   SET_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKFILTRST);
01928
01929   /* Wake up packet filter config */
01930   for(regindex = 0; regindex < Count; regindex++)
01931   {
01932     /* Write filter regs */
01933     WRITE_REG(heth->Instance->MACRWKPFR, pFilter[regindex]);
01934   }
01935
01936   return HAL_OK;
01937 }
01938
01939 /**
01940   * @}
01941   */
01942
01943 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State and Errors functions
01944   *  @brief   ETH State and Errors functions
01945   *
01946 @verbatim
01947   ==============================================================================
01948                  ##### Peripheral State and Errors functions #####
01949   ==============================================================================
01950  [..]
01951    This subsection provides a set of functions allowing to return the State of
01952    ETH communication process, return Peripheral Errors occurred during communication
01953    process
01954
01955
01956 @endverbatim
01957   * @{
01958   */
01959
01960 /**
01961   * @brief  Returns the ETH state.
01962   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01963   *         the configuration information for ETHERNET module
01964   * @retval HAL state
01965   */
01966 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
01967 {
01968   uint32_t gstate= 0x00U, rxstate = 0x00U;
01969   gstate = heth->gState;
01970   rxstate = heth->RxState;
01971
01972   return (HAL_ETH_StateTypeDef)(gstate | rxstate);
01973 }
01974
01975 /**
01976   * @brief  Returns the ETH error code
01977   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01978   *         the configuration information for ETHERNET module
01979   * @retval ETH Error Code
01980   */
01981 uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth)
01982 {
01983   return heth->ErrorCode;
01984 }
01985
01986 /**
01987   * @brief  Returns the ETH DMA error code
01988   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01989   *         the configuration information for ETHERNET module
01990   * @retval ETH DMA Error Code
01991   */
01992 uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth)
01993 {
01994   return heth->DMAErrorCode;
01995 }
01996
01997 /**
01998   * @brief  Returns the ETH MAC error code
01999   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02000   *         the configuration information for ETHERNET module
02001   * @retval ETH MAC Error Code
02002   */
02003 uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth)
02004 {
02005   return heth->MACErrorCode;
02006 }
02007
02008 /**
02009   * @brief  Returns the ETH MAC WakeUp event source
02010   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02011   *         the configuration information for ETHERNET module
02012   * @retval ETH MAC WakeUp event source
02013   */
02014 uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth)
02015 {
02016   return heth->MACWakeUpEvent;
02017 }
02018
02019 /**
02020   * @}
02021   */
02022
02023 /**
02024   * @}
02025   */
02026
02027 static void ETH_SetMACConfig(ETH_HandleTypeDef *heth,  ETH_MACConfigTypeDef *macconf)
02028 {
02029   uint32_t macregval = 0;
02030
02031   /*------------------------ MACCR Configuration --------------------*/
02032   macregval =(macconf->InterPacketGapVal |
02033               macconf->SourceAddrControl |
02034                 (uint32_t)(macconf->ChecksumOffload << 27) |
02035                   (uint32_t)(macconf->GiantPacketSizeLimitControl << 23) |
02036                     (uint32_t)(macconf->Support2KPacket << 22) |
02037                       (uint32_t)(macconf->CRCStripTypePacket << 21) |
02038                         (uint32_t)(macconf->AutomaticPadCRCStrip << 20) |
02039                           (uint32_t)(!macconf->Watchdog << 19) |
02040                             (uint32_t)(!macconf->Jabber << 17) |
02041                               (uint32_t)(macconf->JumboPacket << 16) |
02042                                 macconf->Speed |
02043                                   macconf->DuplexMode |
02044                                     (uint32_t)(macconf->LoopbackMode << 12) |
02045                                       (uint32_t)(macconf->CarrierSenseBeforeTransmit << 11)|
02046                                         (uint32_t)(!macconf->ReceiveOwn << 10)|
02047                                           (uint32_t)(macconf->CarrierSenseDuringTransmit << 9)|
02048                                             (uint32_t)(!macconf->RetryTransmission << 8)|
02049                                               macconf->BackOffLimit |
02050                                                 (uint32_t)(macconf->DeferralCheck << 4)|
02051                                                   macconf->PreambleLength);
02052
02053   /* Write to MACCR */
02054   MODIFY_REG(heth->Instance->MACCR, ETH_MACCR_MASK, macregval);
02055
02056   /*------------------------ MACECR Configuration --------------------*/
02057   macregval = ((macconf->ExtendedInterPacketGapVal << 25)|
02058                (uint32_t)(macconf->ExtendedInterPacketGap << 24)|
02059                  (uint32_t)(macconf->UnicastSlowProtocolPacketDetect << 18)|
02060                    (uint32_t)(macconf->SlowProtocolDetect << 17)|
02061                      (uint32_t)(!macconf->CRCCheckingRxPackets << 16) |
02062                        macconf->GiantPacketSizeLimit);
02063
02064   /* Write to MACECR */
02065   MODIFY_REG(heth->Instance->MACECR, ETH_MACECR_MASK, macregval);
02066
02067   /*------------------------ MACWTR Configuration --------------------*/
02068   macregval = ((uint32_t)(macconf->ProgrammableWatchdog << 8) |
02069                macconf->WatchdogTimeout);
02070
02071   /* Write to MACWTR */
02072   MODIFY_REG(heth->Instance->MACWTR, ETH_MACWTR_MASK, macregval);
02073
02074   /*------------------------ MACTFCR Configuration --------------------*/
02075   macregval = ((uint32_t)(macconf->TransmitFlowControl << 1) |
02076                macconf->PauseLowThreshold |
02077                  (uint32_t)(!macconf->ZeroQuantaPause << 7) |
02078                    (macconf->PauseTime << 16));
02079
02080   /* Write to MACTFCR */
02081   MODIFY_REG(heth->Instance->MACTFCR, ETH_MACTFCR_MASK, macregval);
02082
02083   /*------------------------ MACRFCR Configuration --------------------*/
02084   macregval = ((uint32_t)macconf->ReceiveFlowControl |
02085                (uint32_t)(macconf->UnicastPausePacketDetect << 1));
02086
02087   /* Write to MACRFCR */
02088   MODIFY_REG(heth->Instance->MACRFCR, ETH_MACRFCR_MASK, macregval);
02089
02090   /*------------------------ MTLTQOMR Configuration --------------------*/
02091   /* Write to MTLTQOMR */
02092   MODIFY_REG(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_MASK, macconf->TransmitQueueMode);
02093
02094   /*------------------------ MTLRQOMR Configuration --------------------*/
02095   macregval = (macconf->ReceiveQueueMode |
02096                (uint32_t)(!macconf->DropTCPIPChecksumErrorPacket << 6) |
02097                  (uint32_t)(macconf->ForwardRxErrorPacket << 4) |
02098                    (uint32_t)(macconf->ForwardRxUndersizedGoodPacket << 3));
02099
02100   /* Write to MTLRQOMR */
02101   MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval);
02102 }
02103
02104 static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth,  ETH_DMAConfigTypeDef *dmaconf)
02105 {
02106   uint32_t dmaregval = 0;
02107
02108   /*------------------------ DMAMR Configuration --------------------*/
02109   MODIFY_REG(heth->Instance->DMAMR, ETH_DMAMR_MASK, dmaconf->DMAArbitration);
02110
02111   /*------------------------ DMASBMR Configuration --------------------*/
02112   dmaregval = ((uint32_t)(dmaconf->AddressAlignedBeats << 12) |
02113                dmaconf->BurstMode |
02114                  (uint32_t)(dmaconf->RebuildINCRxBurst << 15));
02115
02116   MODIFY_REG(heth->Instance->DMASBMR, ETH_DMASBMR_MASK, dmaregval);
02117
02118   /*------------------------ DMACCR Configuration --------------------*/
02119   dmaregval = ((uint32_t)(dmaconf->PBLx8Mode <<16) |
02120                dmaconf->MaximumSegmentSize);
02121
02122   MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_MASK, dmaregval);
02123
02124   /*------------------------ DMACTCR Configuration --------------------*/
02125   dmaregval = (dmaconf->TxDMABurstLength |
02126                (uint32_t)(dmaconf->SecondPacketOperate << 4)|
02127                  (uint32_t)(dmaconf->TCPSegmentation << 12));
02128
02129   MODIFY_REG(heth->Instance->DMACTCR, ETH_DMACTCR_MASK, dmaregval);
02130
02131   /*------------------------ DMACRCR Configuration --------------------*/
02132   dmaregval = ((uint32_t)(dmaconf->FlushRxPacket << 31) |
02133                dmaconf->RxDMABurstLength);
02134
02135   /* Write to DMACRCR */
02136   MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_MASK, dmaregval);
02137 }
02138
02139 /**
02140   * @brief  Configures Ethernet MAC and DMA with default parameters.
02141   *         called by HAL_ETH_Init() API.
02142   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02143   *         the configuration information for ETHERNET module
02144   * @retval HAL status
02145   */
02146 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
02147 {
02148   ETH_MACConfigTypeDef macDefaultConf;
02149   ETH_DMAConfigTypeDef dmaDefaultConf;
02150
02151   /*--------------- ETHERNET MAC registers default Configuration --------------*/
02152   macDefaultConf.AutomaticPadCRCStrip = ENABLE;
02153   macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10;
02154   macDefaultConf.CarrierSenseBeforeTransmit = DISABLE;
02155   macDefaultConf.CarrierSenseDuringTransmit = DISABLE;
02156   macDefaultConf.ChecksumOffload = ENABLE;
02157   macDefaultConf.CRCCheckingRxPackets = ENABLE;
02158   macDefaultConf.CRCStripTypePacket = ENABLE;
02159   macDefaultConf.DeferralCheck = DISABLE;
02160   macDefaultConf.DropTCPIPChecksumErrorPacket = ENABLE;
02161   macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE;
02162   macDefaultConf.ExtendedInterPacketGap = DISABLE;
02163   macDefaultConf.ExtendedInterPacketGapVal = 0x0;
02164   macDefaultConf.ForwardRxErrorPacket = DISABLE;
02165   macDefaultConf.ForwardRxUndersizedGoodPacket = DISABLE;
02166   macDefaultConf.GiantPacketSizeLimit = 0x618;
02167   macDefaultConf.GiantPacketSizeLimitControl = DISABLE;
02168   macDefaultConf.InterPacketGapVal = ETH_INTERPACKETGAP_96BIT;
02169   macDefaultConf.Jabber = ENABLE;
02170   macDefaultConf.JumboPacket = DISABLE;
02171   macDefaultConf.LoopbackMode = DISABLE;
02172   macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS_4;
02173   macDefaultConf.PauseTime = 0x0;
02174   macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7;
02175   macDefaultConf.ProgrammableWatchdog = DISABLE;
02176   macDefaultConf.ReceiveFlowControl = DISABLE;
02177   macDefaultConf.ReceiveOwn = ENABLE;
02178   macDefaultConf.ReceiveQueueMode = ETH_RECEIVESTOREFORWARD;
02179   macDefaultConf.RetryTransmission = ENABLE;
02180   macDefaultConf.SlowProtocolDetect = DISABLE;
02181   macDefaultConf.SourceAddrControl = ETH_SOURCEADDRESS_REPLACE_ADDR0;
02182   macDefaultConf.Speed = ETH_SPEED_100M;
02183   macDefaultConf.Support2KPacket = DISABLE;
02184   macDefaultConf.TransmitQueueMode = ETH_TRANSMITSTOREFORWARD;
02185   macDefaultConf.TransmitFlowControl = DISABLE;
02186   macDefaultConf.UnicastPausePacketDetect = DISABLE;
02187   macDefaultConf.UnicastSlowProtocolPacketDetect = DISABLE;
02188   macDefaultConf.Watchdog = ENABLE;
02189   macDefaultConf.WatchdogTimeout =  ETH_MACWTR_WTO_2KB;
02190   macDefaultConf.ZeroQuantaPause = ENABLE;
02191
02192   /* MAC default configuration */
02193   ETH_SetMACConfig(heth, &macDefaultConf);
02194
02195   /*--------------- ETHERNET DMA registers default Configuration --------------*/
02196   dmaDefaultConf.AddressAlignedBeats = ENABLE;
02197   dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED;
02198   dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_RX1_TX1;
02199   dmaDefaultConf.FlushRxPacket = DISABLE;
02200   dmaDefaultConf.PBLx8Mode = DISABLE;
02201   dmaDefaultConf.RebuildINCRxBurst = DISABLE;
02202   dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
02203   dmaDefaultConf.SecondPacketOperate = DISABLE;
02204   dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
02205   dmaDefaultConf.TCPSegmentation = DISABLE;
02206   dmaDefaultConf.MaximumSegmentSize = 536;
02207
02208   /* DMA default configuration */
02209   ETH_SetDMAConfig(heth, &dmaDefaultConf);
02210 }
02211
02212 /**
02213   * @brief  Configures the Clock range of SMI interface.
02214   *         called by HAL_ETH_Init() API.
02215   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02216   *         the configuration information for ETHERNET module
02217   * @retval None
02218   */
02219 static void ETH_MAC_MDIO_ClkConfig(ETH_HandleTypeDef *heth)
02220 {
02221   uint32_t tmpreg = 0;
02222   uint32_t hclk = 0;
02223
02224   /* Get the ETHERNET MACMDIOAR value */
02225   tmpreg = (heth->Instance)->MACMDIOAR;
02226
02227   /* Clear CSR Clock Range bits */
02228   tmpreg &= ~ETH_MACMDIOAR_CR;
02229
02230   /* Get hclk frequency value */
02231   hclk = HAL_RCC_GetHCLKFreq();
02232
02233   /* Set CR bits depending on hclk value */
02234   if((hclk >= 20000000)&&(hclk < 35000000))
02235   {
02236     /* CSR Clock Range between 20-35 MHz */
02237     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
02238   }
02239   else if((hclk >= 35000000)&&(hclk < 60000000))
02240   {
02241     /* CSR Clock Range between 35-60 MHz */
02242     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
02243   }
02244   else if((hclk >= 60000000)&&(hclk < 100000000))
02245   {
02246     /* CSR Clock Range between 60-100 MHz */
02247     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
02248   }
02249   else if((hclk >= 100000000)&&(hclk < 150000000))
02250   {
02251     /* CSR Clock Range between 100-150 MHz */
02252     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
02253   }
02254   else /* (hclk >= 150000000)&&(hclk <= 200000000) */
02255   {
02256     /* CSR Clock Range between 150-200 MHz */
02257     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
02258   }
02259
02260   /* Configure the CSR Clock Range */
02261   (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
02262 }
02263
02264 /**
02265   * @brief  Initializes the DMA Tx descriptors.
02266   *         called by HAL_ETH_Init() API.
02267   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02268   *         the configuration information for ETHERNET module
02269   * @retval None
02270   */
02271 static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth)
02272 {
02273   ETH_DMADescTypeDef *dmatxdesc;
02274   uint32_t i;
02275
02276   /* Fill each DMATxDesc descriptor with the right values */
02277   for(i=0; i < ETH_TX_DESC_CNT; i++)
02278   {
02279     dmatxdesc = heth->Init.TxDesc + i;
02280
02281     WRITE_REG(dmatxdesc->DESC0, 0x0);
02282     WRITE_REG(dmatxdesc->DESC1, 0x0);
02283     WRITE_REG(dmatxdesc->DESC2, 0x0);
02284     WRITE_REG(dmatxdesc->DESC3, 0x0);
02285
02286     WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc);
02287   }
02288
02289   heth->TxDescList.CurTxDesc = 0;
02290
02291   /* Set Transmit Descriptor Ring Length */
02292   WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT -1));
02293
02294   /* Set Transmit Descriptor List Address */
02295   WRITE_REG(heth->Instance->DMACTDLAR, (uint32_t) heth->Init.TxDesc);
02296
02297   /* Set Transmit Descriptor Tail pointer */
02298   WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t) heth->Init.TxDesc);
02299 }
02300
02301 /**
02302   * @brief  Initializes the DMA Rx descriptors in chain mode.
02303   *         called by HAL_ETH_Init() API.
02304   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02305   *         the configuration information for ETHERNET module
02306   * @retval None
02307   */
02308 static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
02309 {
02310   ETH_DMADescTypeDef *dmarxdesc;
02311   uint32_t i;
02312
02313   for(i = 0; i < ETH_RX_DESC_CNT; i++)
02314   {
02315     dmarxdesc =  heth->Init.RxDesc + i;
02316
02317     WRITE_REG(dmarxdesc->DESC0, 0x0);
02318     WRITE_REG(dmarxdesc->DESC1, 0x0);
02319     WRITE_REG(dmarxdesc->DESC2, 0x0);
02320     WRITE_REG(dmarxdesc->DESC3, 0x0);
02321     WRITE_REG(dmarxdesc->BackupAddr0, 0x0);
02322     WRITE_REG(dmarxdesc->BackupAddr1, 0x0);
02323
02324     /* Set Rx descritors adresses */
02325     WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);
02326   }
02327
02328   WRITE_REG(heth->RxDescList.CurRxDesc, 0);
02329   WRITE_REG(heth->RxDescList.FirstAppDesc, 0);
02330   WRITE_REG(heth->RxDescList.AppDescNbr, 0);
02331   WRITE_REG(heth->RxDescList.ItMode, 0);
02332   WRITE_REG(heth->RxDescList.AppContextDesc, 0);
02333
02334   /* Set Receive Descriptor Ring Length */
02335   WRITE_REG(heth->Instance->DMACRDRLR, (ETH_RX_DESC_CNT - 1));
02336
02337   /* Set Receive Descriptor List Address */
02338   WRITE_REG(heth->Instance->DMACRDLAR, (uint32_t) heth->Init.RxDesc);
02339
02340   /* Set Receive Descriptor Tail pointer Address */
02341   WRITE_REG(heth->Instance->DMACRDTPR, (uint32_t) dmarxdesc);
02342 }
02343
02344 /**
02345   * @brief  Prepare Tx DMA descriptor before transmission.
02346   *         called by HAL_ETH_Transmit_IT and HAL_ETH_Transmit_IT() API.
02347   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02348   *         the configuration information for ETHERNET module
02349   * @param  pTxConfig: Tx packet configuration
02350   * @param  ItMode: Enable or disable Tx EOT interrept
02351   * @retval None
02352   */
02353 static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode)
02354 {
02355   ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
02356   uint32_t descidx = dmatxdesclist->CurTxDesc;
02357   uint32_t firstdescidx = dmatxdesclist->CurTxDesc;
02358   uint32_t descnbr = 0, idx = 0;
02359   ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
02360
02361   ETH_BufferTypeDef  *txbuffer = pTxConfig->TxBuffer;
02362
02363   /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
02364   if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
02365   {
02366     return HAL_ETH_ERROR_BUSY;
02367   }
02368
02369   /***************************************************************************/
02370   /*****************    Context descriptor configuration (Optional) **********/
02371   /***************************************************************************/
02372   /* If VLAN tag is enabled for this packet */
02373   if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG))
02374   {
02375     /* Set vlan tag value */
02376     MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_VT, pTxConfig->VlanTag);
02377     /* Set vlan tag valid bit */
02378     SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_VLTV);
02379     /* Set the descriptor as the vlan input source */
02380     SET_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI);
02381
02382     /* if inner VLAN is enabled */
02383     if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG))
02384     {
02385       /* Set inner vlan tag value */
02386       MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16));
02387       /* Set inner vlan tag valid bit */
02388       SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_IVLTV);
02389
02390       /* Set Vlan Tag control */
02391       MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_IVTIR, pTxConfig->InnerVlanCtrl);
02392
02393       /* Set the descriptor as the inner vlan input source */
02394       SET_BIT(heth->Instance->MACIVIR, ETH_MACIVIR_VLTI);
02395       /* Enable double VLAN processing */
02396       SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
02397     }
02398   }
02399
02400   /* if tcp segementation is enabled for this packet */
02401   if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO))
02402   {
02403     /* Set MSS value */
02404     MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize);
02405     /* Set MSS valid bit */
02406     SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_TCMSSV);
02407   }
02408
02409   if((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG)) || (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO)))
02410   {
02411     /* Set as context descriptor */
02412     SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_CTXT);
02413     /* Set own bit */
02414     SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
02415     /* Increment current tx descriptor index */
02416     INCR_TX_DESC_INDEX(descidx, 1);
02417     /* Get current descriptor address */
02418     dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
02419
02420     descnbr += 1U;
02421
02422     /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
02423     if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
02424     {
02425       dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx];
02426       /* Clear own bit */
02427       CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
02428
02429       return HAL_ETH_ERROR_BUSY;
02430     }
02431   }
02432
02433   /***************************************************************************/
02434   /*****************    Normal descriptors configuration     *****************/
02435   /***************************************************************************/
02436
02437   descnbr += 1U;
02438
02439   /* Set header or buffer 1 address */
02440   WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
02441   /* Set header or buffer 1 Length */
02442   MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
02443
02444   if(txbuffer->next != NULL)
02445   {
02446     txbuffer = txbuffer->next;
02447     /* Set buffer 2 address */
02448     WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
02449     /* Set buffer 2 Length */
02450     MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
02451   }
02452   else
02453   {
02454     WRITE_REG(dmatxdesc->DESC1, 0x0);
02455     /* Set buffer 2 Length */
02456     MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0);
02457   }
02458
02459   if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO))
02460   {
02461     /* Set TCP Header length */
02462     MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_THL, (pTxConfig->TCPHeaderLen << 19));
02463     /* Set TCP payload length */
02464     MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
02465     /* Set TCP Segmentation Enabled bit */
02466     SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
02467   }
02468   else
02469   {
02470     MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
02471
02472     if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM))
02473     {
02474       MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
02475     }
02476
02477     if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD))
02478     {
02479       MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CPC, pTxConfig->CRCPadCtrl);
02480     }
02481   }
02482
02483   if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG))
02484   {
02485     /* Set Vlan Tag control */
02486     MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl);
02487   }
02488
02489   /* Mark it as First Descriptor */
02490   SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
02491   /* Mark it as NORMAL descriptor */
02492   CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
02493   /* set OWN bit of FIRST descriptor */
02494   SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
02495
02496   /* If source address insertion/replacement is enabled for this packet */
02497   if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC))
02498   {
02499     MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl);
02500   }
02501
02502   /* only if the packet is splitted into more than one descriptors > 1 */
02503   while (txbuffer->next != NULL)
02504   {
02505     /* Increment current tx descriptor index */
02506     INCR_TX_DESC_INDEX(descidx, 1);
02507     /* Get current descriptor address */
02508     dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
02509
02510     /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
02511     if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN)
02512     {
02513       descidx = firstdescidx;
02514       dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
02515
02516       /* clear previous desc own bit */
02517       for(idx = 0; idx < descnbr; idx ++)
02518       {
02519         CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
02520
02521         /* Increment current tx descriptor index */
02522         INCR_TX_DESC_INDEX(descidx, 1);
02523         /* Get current descriptor address */
02524         dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
02525       }
02526
02527       return HAL_ETH_ERROR_BUSY;
02528     }
02529
02530     descnbr += 1U;
02531
02532     /* Get the next Tx buffer in the list */
02533     txbuffer = (ETH_BufferTypeDef *)txbuffer->next;
02534
02535     /* Set header or buffer 1 address */
02536     WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
02537     /* Set header or buffer 1 Length */
02538     MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
02539
02540     if (txbuffer->next != NULL)
02541     {
02542       /* Get the next Tx buffer in the list */
02543       txbuffer = (ETH_BufferTypeDef *)txbuffer->next;
02544       /* Set buffer 2 address */
02545       WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
02546       /* Set buffer 2 Length */
02547       MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
02548     }
02549     else
02550     {
02551       WRITE_REG(dmatxdesc->DESC1, 0x0);
02552       /* Set buffer 2 Length */
02553       MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0);
02554     }
02555
02556     if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO))
02557     {
02558       /* Set TCP payload length */
02559       MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
02560       /* Set TCP Segmentation Enabled bit */
02561       SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
02562     }
02563     else
02564     {
02565       /* Set the packet length */
02566       MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
02567
02568       if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM))
02569       {
02570         /* Checksum Insertion Control */
02571         MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
02572       }
02573     }
02574
02575     /* Set Own bit */
02576     SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
02577     /* Mark it as NORMAL descriptor */
02578     CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
02579   }
02580
02581   if(ItMode)
02582   {
02583     /* Set Interrupt on completition bit */
02584     SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
02585   }
02586   else
02587   {
02588     /* Clear Interrupt on completition bit */
02589     CLEAR_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
02590   }
02591
02592   /* Mark it as LAST descriptor */
02593   SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
02594
02595   dmatxdesclist->CurTxDesc = descidx;
02596
02597   /* Return function status */
02598   return HAL_ETH_ERROR_NONE;
02599 }
02600
02601 #endif /* HAL_ETH_MODULE_ENABLED */
02602 /**
02603   * @}
02604   */
02605
02606 /**
02607   * @}
02608   */
02609
02610 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_eth.h Source File

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stm32h7xx_hal_eth.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_eth.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of ETH HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_ETH_H
00040 #define __STM32H7xx_HAL_ETH_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup ETH
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 #ifndef ETH_TX_DESC_CNT
00059  #define ETH_TX_DESC_CNT         4
00060 #endif
00061
00062 #ifndef ETH_RX_DESC_CNT
00063  #define ETH_RX_DESC_CNT         4
00064 #endif
00065
00066 /*********************** Descriptors struct def section ************************/
00067 /** @defgroup ETH_Exported_Types ETH Exported Types
00068   * @{
00069   */
00070
00071 /**
00072   * @brief  ETH DMA Descriptor structure definition
00073   */
00074 #if defined ( __GNUC__ )
00075 typedef struct __attribute__((packed))
00076 #else
00077 typedef __packed struct
00078 #endif
00079 {
00080   uint32_t DESC0;
00081   uint32_t DESC1;
00082   uint32_t DESC2;
00083   uint32_t DESC3;
00084   uint32_t BackupAddr0; /* used to store rx buffer 1 address */
00085   uint32_t BackupAddr1; /* used to store rx buffer 2 address */
00086 }ETH_DMADescTypeDef;
00087 /**
00088   *
00089   */
00090
00091 /**
00092   * @brief  ETH Buffers List structure definition
00093   */
00094 typedef struct __ETH_BufferTypeDef
00095 {
00096   uint8_t *buffer;                /*<! buffer address */
00097
00098   uint32_t len;                   /*<! buffer length */
00099
00100   struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */
00101 }ETH_BufferTypeDef;
00102 /**
00103   *
00104   */
00105
00106 /**
00107   * @brief  DMA Transmit Descriptors Wrapper structure definition
00108   */
00109 typedef struct
00110 {
00111   uint32_t  TxDesc[ETH_TX_DESC_CNT];     /*<! Tx DMA descriptors addresses */
00112
00113   uint32_t  CurTxDesc;               /*<! Current Tx descriptor index for packet transmission */
00114
00115 }ETH_TxDescListTypeDef;
00116 /**
00117   *
00118   */
00119
00120  /**
00121   * @brief  Transmit Packet Configuration structure definition
00122   */
00123 typedef struct
00124 {
00125   uint32_t Attributes;              /*!< Tx packet HW features capabilities.
00126                                          This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/
00127
00128   uint32_t Length;                  /*!< Total packet length   */
00129
00130   ETH_BufferTypeDef *TxBuffer;      /*!< Tx buffers pointers */
00131
00132   uint32_t SrcAddrCtrl;             /*!< Specifies the source address insertion control.
00133                                          This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */
00134
00135   uint32_t CRCPadCtrl;             /*!< Specifies the CRC and Pad insertion and replacement control.
00136                                         This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control  */
00137
00138   uint32_t ChecksumCtrl;           /*!< Specifies the checksum insertion control.
00139                                         This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control  */
00140
00141   uint32_t MaxSegmentSize;         /*!< Sets TCP maximum segment size only when TCP segmentation is enabled.
00142                                         This parameter can be a value from 0x0 to 0x3FFF */
00143
00144   uint32_t PayloadLen;             /*!< Sets Total payload length only when TCP segmentation is enabled.
00145                                         This parameter can be a value from 0x0 to 0x3FFFF */
00146
00147   uint32_t TCPHeaderLen;           /*!< Sets TCP header length only when TCP segmentation is enabled.
00148                                         This parameter can be a value from 0x5 to 0xF */
00149
00150   uint32_t VlanTag;                /*!< Sets VLAN Tag only when VLAN is enabled.
00151                                         This parameter can be a value from 0x0 to 0xFFFF*/
00152
00153   uint32_t VlanCtrl;               /*!< Specifies VLAN Tag insertion control only when VLAN is enabled.
00154                                         This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */
00155
00156   uint32_t InnerVlanTag;           /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled.
00157                                         This parameter can be a value from 0x0 to 0x3FFFF */
00158
00159   uint32_t InnerVlanCtrl;          /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled.
00160                                         This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control   */
00161
00162 }ETH_TxPacketConfig;
00163 /**
00164   *
00165   */
00166
00167 /**
00168  * @brief  DMA Receive Descriptors Wrapper structure definition
00169  */
00170 typedef struct
00171 {
00172   uint32_t RxDesc[ETH_RX_DESC_CNT];     /*<! Rx DMA descriptors addresses. */
00173
00174   uint32_t CurRxDesc;                   /*<! Current Rx descriptor, ready for next reception. */
00175
00176   uint32_t FirstAppDesc;                /*<! First descriptor of last received packet. */
00177
00178   uint32_t AppDescNbr;                  /*<! Number of descriptors of last received packet. */
00179
00180   uint32_t AppContextDesc;              /*<! If 1 a context descriptor is present in last received packet.
00181                                              If 0 no context descriptor is present in last received packet. */
00182
00183   uint32_t ItMode;                      /*<! If 1, DMA will generate the Rx complete interrupt.
00184                                              If 0, DMA will not generate the Rx complete interrupt. */
00185 }ETH_RxDescListTypeDef;
00186 /**
00187   *
00188   */
00189
00190 /**
00191   * @brief  Received Packet Information structure definition
00192   */
00193 typedef struct
00194 {
00195   uint32_t SegmentCnt;      /*<! Number of Rx Descriptors */
00196
00197   uint32_t VlanTag;         /*<! Vlan Tag value */
00198
00199   uint32_t InnerVlanTag;    /*<! Inner Vlan Tag value */
00200
00201   uint32_t Checksum;        /*<! Rx Checksum status.
00202                                  This parameter can be a value of @ref ETH_Rx_Checksum_Status */
00203
00204   uint32_t HeaderType;      /*<! IP header type.
00205                                  This parameter can be a value of @ref ETH_Rx_IP_Header_Type */
00206
00207   uint32_t PayloadType;     /*<! Payload type.
00208                                  This parameter can be a value of @ref ETH_Rx_Payload_Type */
00209
00210   uint32_t MacFilterStatus; /*<! MAC filter status.
00211                                  This parameter can be a value of @ref ETH_Rx_MAC_Filter_Status */
00212
00213   uint32_t L3FilterStatus;  /*<! L3 filter status
00214                                  This parameter can be a value of @ref ETH_Rx_L3_Filter_Status */
00215
00216   uint32_t L4FilterStatus;  /*<! L4 filter status
00217                                  This parameter can be a value of @ref ETH_Rx_L4_Filter_Status */
00218
00219   uint32_t ErrorCode;       /*<! Rx error code
00220                                  This parameter can be a combination of @ref ETH_Rx_Error_Code */
00221
00222 } ETH_RxPacketInfo;
00223 /**
00224   *
00225   */
00226
00227 /**
00228   * @brief  ETH MAC Configuration Structure definition
00229   */
00230 typedef struct
00231 {
00232   uint32_t         SourceAddrControl;           /*!< Selects the Source Address Insertion or Replacement Control.
00233                                                      This parameter can be a value of @ref ETH_Source_Addr_Control */
00234
00235   FunctionalState  ChecksumOffload;             /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */
00236
00237   uint32_t         InterPacketGapVal;           /*!< Sets the minimum IPG between Packet during transmission.
00238                                                      This parameter can be a value of @ref ETH_Inter_Packet_Gap */
00239
00240   FunctionalState  GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */
00241
00242   FunctionalState  Support2KPacket;             /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */
00243
00244   FunctionalState  CRCStripTypePacket;          /*!< Enables or disables the CRC stripping for Type packets.*/
00245
00246   FunctionalState  AutomaticPadCRCStrip;        /*!< Enables or disables  the Automatic MAC Pad/CRC Stripping.*/
00247
00248   FunctionalState  Watchdog;                    /*!< Enables or disables the Watchdog timer on Rx path
00249                                                            When enabled, the MAC allows no more then 2048 bytes to be received.
00250                                                            When disabled, the MAC can receive up to 16384 bytes. */
00251
00252   FunctionalState  Jabber;                      /*!< Enables or disables Jabber timer on Tx path
00253                                                            When enabled, the MAC allows no more then 2048 bytes to be sent.
00254                                                            When disabled, the MAC can send up to 16384 bytes. */
00255
00256   FunctionalState  JumboPacket;                 /*!< Enables or disables receiving Jumbo Packet
00257                                                            When enabled, the MAC allows jumbo packets of 9,018 bytes
00258                                                            without reporting a giant packet error */
00259
00260   uint32_t         Speed;                       /*!< Sets the Ethernet speed: 10/100 Mbps.
00261                                                            This parameter can be a value of @ref ETH_Speed */
00262
00263   uint32_t         DuplexMode;                  /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
00264                                                            This parameter can be a value of @ref ETH_Duplex_Mode */
00265
00266   FunctionalState  LoopbackMode;                /*!< Enables or disables the loopback mode */
00267
00268   FunctionalState  CarrierSenseBeforeTransmit;  /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */
00269
00270   FunctionalState  ReceiveOwn;                  /*!< Enables or disables the Receive Own in Half Duplex mode. */
00271
00272   FunctionalState  CarrierSenseDuringTransmit;  /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */
00273
00274   FunctionalState  RetryTransmission;           /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/
00275
00276   uint32_t         BackOffLimit;                /*!< Selects the BackOff limit value.
00277                                                         This parameter can be a value of @ref ETH_Back_Off_Limit */
00278
00279   FunctionalState  DeferralCheck;               /*!< Enables or disables the deferral check function in Half Duplex mode. */
00280
00281   uint32_t         PreambleLength;              /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode).
00282                                                            This parameter can be a value of @ref ETH_Preamble_Length */
00283
00284   FunctionalState  UnicastSlowProtocolPacketDetect;   /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */
00285
00286   FunctionalState  SlowProtocolDetect;          /*!< Enable or disables the Slow Protocol Detection. */
00287
00288   FunctionalState  CRCCheckingRxPackets;        /*!< Enable or disables the CRC Checking for Received Packets. */
00289
00290   uint32_t         GiantPacketSizeLimit;        /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is
00291                                                           greater than the value programmed in this field in units of bytes
00292                                                           This parameter must be a number between Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte)*/
00293
00294   FunctionalState  ExtendedInterPacketGap;      /*!< Enable or disables the extended inter packet gap. */
00295
00296   uint32_t         ExtendedInterPacketGapVal;   /*!< Sets the Extended IPG between Packet during transmission.
00297                                                            This parameter can be a value from 0x0 to 0xFF */
00298
00299   FunctionalState  ProgrammableWatchdog;        /*!< Enable or disables the Programmable Watchdog.*/
00300
00301   uint32_t         WatchdogTimeout;             /*!< This field is used as watchdog timeout for a received packet
00302                                                         This parameter can be a value of @ref ETH_Watchdog_Timeout */
00303
00304    uint32_t        PauseTime;                   /*!< This field holds the value to be used in the Pause Time field in the transmit control packet.
00305                                                    This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
00306
00307   FunctionalState  ZeroQuantaPause;             /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/
00308
00309   uint32_t         PauseLowThreshold;           /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet.
00310                                                    This parameter can be a value of @ref ETH_Pause_Low_Threshold */
00311
00312   FunctionalState  TransmitFlowControl;         /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode
00313                                                    or the MAC back pressure operation in Half Duplex mode */
00314
00315   FunctionalState  UnicastPausePacketDetect;    /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */
00316
00317   FunctionalState  ReceiveFlowControl;          /*!< Enables or disables the MAC to decodes the received Pause packet
00318                                                   and disables its transmitter for a specified (Pause) time */
00319
00320   uint32_t         TransmitQueueMode;           /*!< Specifies the Transmit Queue operating mode.
00321                                                       This parameter can be a value of @ref ETH_Transmit_Mode */
00322
00323   uint32_t         ReceiveQueueMode;            /*!< Specifies the Receive Queue operating mode.
00324                                                              This parameter can be a value of @ref ETH_Receive_Mode */
00325
00326   FunctionalState  DropTCPIPChecksumErrorPacket; /*!< Enables or disables Dropping of TCPIP Checksum Error Packets. */
00327
00328   FunctionalState  ForwardRxErrorPacket;        /*!< Enables or disables  forwarding Error Packets. */
00329
00330   FunctionalState  ForwardRxUndersizedGoodPacket;  /*!< Enables or disables  forwarding Undersized Good Packets.*/
00331 } ETH_MACConfigTypeDef;
00332 /**
00333   *
00334   */
00335
00336 /**
00337   * @brief  ETH DMA Configuration Structure definition
00338   */
00339  typedef struct
00340  {
00341    uint32_t        DMAArbitration;          /*!< Sets the arbitration scheme between DMA Tx and Rx
00342                                                          This parameter can be a value of @ref ETH_DMA_Arbitration */
00343
00344    FunctionalState AddressAlignedBeats;     /*!< Enables or disables the AHB Master interface address aligned
00345                                                             burst transfers on Read and Write channels  */
00346
00347    uint32_t        BurstMode;               /*!< Sets the AHB Master interface burst transfers.
00348                                                      This parameter can be a value of @ref ETH_Burst_Mode */
00349
00350    FunctionalState RebuildINCRxBurst;       /*!< Enables or disables the AHB Master to rebuild the pending beats
00351                                                    of any initiated burst transfer with INCRx and SINGLE transfers. */
00352
00353    FunctionalState PBLx8Mode;               /*!< Enables or disables the PBL multiplication by eight. */
00354
00355    uint32_t        TxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
00356                                                      This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
00357
00358    FunctionalState SecondPacketOperate;     /*!< Enables or disables the Operate on second Packet mode, which allows the DMA to process a second
00359                                                       Packet of Transmit data even before obtaining the status for the first one. */
00360
00361    uint32_t        RxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
00362                                                     This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
00363
00364    FunctionalState FlushRxPacket;           /*!< Enables or disables the Rx Packet Flush */
00365
00366    FunctionalState TCPSegmentation;         /*!< Enables or disables the TCP Segmentation */
00367
00368    uint32_t        MaximumSegmentSize;      /*!< Sets the maximum segment size that should be used while segmenting the packet
00369                                                   This parameter can be a value from 0x40 to 0x3FFF */
00370 } ETH_DMAConfigTypeDef;
00371 /**
00372   *
00373   */
00374
00375 /**
00376   * @brief  HAL ETH Media Interfaces enum definition
00377   */
00378 typedef enum
00379 {
00380   HAL_ETH_MII_MODE             = 0x00,   /*!<  Media Independent Interface               */
00381   HAL_ETH_RMII_MODE            = 0x01    /*!<   Reduced Media Independent Interface       */
00382 }ETH_MediaInterfaceTypeDef;
00383 /**
00384   *
00385   */
00386
00387 /**
00388   * @brief  ETH Init Structure definition
00389   */
00390 typedef struct
00391 {
00392
00393   uint8_t                     *MACAddr;                  /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
00394
00395   ETH_MediaInterfaceTypeDef   MediaInterface;            /*!< Selects the MII interface or the RMII interface. */
00396
00397   ETH_DMADescTypeDef          *TxDesc;                   /*!< Provides the address of the first DMA Tx descriptor in the list */
00398
00399   ETH_DMADescTypeDef          *RxDesc;                   /*!< Provides the address of the first DMA Rx descriptor in the list */
00400
00401   uint32_t                    RxBuffLen;                 /*!< Provides the length of Rx buffers size */
00402
00403 }ETH_InitTypeDef;
00404 /**
00405   *
00406   */
00407
00408 /**
00409   * @brief  HAL State structures definition
00410   */
00411 typedef enum
00412 {
00413   HAL_ETH_STATE_RESET             = 0x00,    /*!< Peripheral not yet Initialized or disabled         */
00414   HAL_ETH_STATE_READY             = 0x10,    /*!< Peripheral Communication started                   */
00415   HAL_ETH_STATE_BUSY              = 0x23,    /*!< an internal process is ongoing                     */
00416   HAL_ETH_STATE_BUSY_TX           = 0x21,    /*!< Transmission process is ongoing                    */
00417   HAL_ETH_STATE_BUSY_RX           = 0x22,    /*!< Reception process is ongoing                       */
00418   HAL_ETH_STATE_ERROR             = 0xE0     /*!< Error State                                        */
00419 }HAL_ETH_StateTypeDef;
00420 /**
00421   *
00422   */
00423
00424 /**
00425   * @brief  ETH Handle Structure definition
00426   */
00427 typedef struct
00428 {
00429   ETH_TypeDef                *Instance;                 /*!< Register base address       */
00430
00431   ETH_InitTypeDef            Init;                      /*!< Ethernet Init Configuration */
00432
00433   ETH_TxDescListTypeDef      TxDescList;                /*!< Tx descriptor wrapper: holds all Tx descriptors list
00434                                                             addresses and current descriptor index  */
00435
00436   ETH_RxDescListTypeDef      RxDescList;                /*!< Rx descriptor wrapper: holds all Rx descriptors list
00437                                                             addresses and current descriptor index  */
00438
00439   HAL_LockTypeDef            Lock;                      /*!< Locking object             */
00440
00441   __IO HAL_ETH_StateTypeDef  gState;                   /*!< ETH state information related to global Handle management
00442                                                               and also related to Tx operations.
00443                                                              This parameter can be a value of @ref HAL_ETH_StateTypeDef */
00444
00445   __IO HAL_ETH_StateTypeDef  RxState;                   /*!< ETH state information related to Rx operations.
00446                                                              This parameter can be a value of @ref HAL_ETH_StateTypeDef */
00447
00448   __IO uint32_t              ErrorCode;                 /*!< Holds the global Error code of the ETH HAL status machine
00449                                                              This parameter can be a value of of @ref ETH_Error_Code */
00450
00451   __IO uint32_t              DMAErrorCode;              /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs
00452                                                              This parameter can be a combination of @ref ETH_DMA_Status_Flags */
00453
00454   __IO uint32_t              MACErrorCode;              /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs
00455                                                              This parameter can be a combination of @ref ETH_MAC_Rx_Tx_Status */
00456
00457   __IO uint32_t              MACWakeUpEvent;            /*!< Holds the Wake Up event when the MAC exit the power down mode
00458                                                              This parameter can be a value of @ref ETH_MAC_Wake_Up_Event */
00459
00460   __IO uint32_t              MACLPIEvent;               /*!< Holds the LPI event when the an LPI status interrupt occurs.
00461                                                              This parameter can be a value of @ref ETHEx_LPI_Event */
00462
00463 } ETH_HandleTypeDef;
00464 /**
00465   *
00466   */
00467
00468 /**
00469   * @brief  ETH MAC filter structure definition
00470   */
00471 typedef struct{
00472   FunctionalState PromiscuousMode;          /*!< Enable or Disable Promiscuous Mode */
00473
00474   FunctionalState ReceiveAllMode;           /*!< Enable or Disable Receive All Mode */
00475
00476   FunctionalState HachOrPerfectFilter;      /*!< Enable or Disable Perfect filtering in addition to Hash filtering */
00477
00478   FunctionalState HashUnicast;              /*!< Enable or Disable Hash filtering on unicast packets */
00479
00480   FunctionalState HashMulticast;            /*!< Enable or Disable Hash filtering on multicast packets */
00481
00482   FunctionalState PassAllMulticast;         /*!< Enable or Disable passing all multicast packets */
00483
00484   FunctionalState SrcAddrFiltering;         /*!< Enable or Disable source address filtering module */
00485
00486   FunctionalState SrcAddrInverseFiltering;  /*!< Enable or Disable source address inverse filtering */
00487
00488   FunctionalState DestAddrInverseFiltering; /*!< Enable or Disable destination address inverse filtering */
00489
00490   FunctionalState BroadcastFilter;          /*!< Enable or Disable broadcast filter */
00491
00492   uint32_t        ControlPacketsFilter;     /*!< Set the control packets filter
00493                                                  This parameter can be a value of @ref ETH_Control_Packets_Filter */
00494 }ETH_MACFilterConfigTypeDef;
00495 /**
00496   *
00497   */
00498
00499 /**
00500   * @brief  ETH Power Down structure definition
00501   */
00502 typedef struct{
00503   FunctionalState WakeUpPacket;    /*!< Enable or Disable Wake up packet detection in power down mode */
00504
00505   FunctionalState MagicPacket;     /*!< Enable or Disable Magic packet detection in power down mode */
00506
00507   FunctionalState GlobalUnicast;    /*!< Enable or Disable Global unicast packet detection in power down mode */
00508
00509   FunctionalState WakeUpForward;    /*!< Enable or Disable Forwarding Wake up packets */
00510
00511 }ETH_PowerDownConfigTypeDef;
00512 /**
00513   *
00514   */
00515
00516 /**
00517   * @}
00518   */
00519
00520 /* Exported constants --------------------------------------------------------*/
00521 /** @defgroup ETH_Exported_Constants ETH Exported Constants
00522   * @{
00523   */
00524
00525 /** @defgroup ETH_DMA_Tx_Descriptor_Bit_Definition ETH DMA Tx Descriptor Bit Definition
00526   * @{
00527   */
00528
00529 /*
00530    DMA Tx Normal Desciptor Read Format
00531   -----------------------------------------------------------------------------------------------
00532   TDES0 |                         Buffer1 or Header Address  [31:0]                              |
00533   -----------------------------------------------------------------------------------------------
00534   TDES1 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]              |
00535   -----------------------------------------------------------------------------------------------
00536   TDES2 | IOC(31) | TTSE(30) | Buff2 Length[29:16] | VTIR[15:14] | Header or Buff1 Length[13:0]  |
00537   -----------------------------------------------------------------------------------------------
00538   TDES3 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
00539   -----------------------------------------------------------------------------------------------
00540 */
00541
00542 /**
00543   * @brief  Bit definition of TDES0 RF register
00544   */
00545 #define ETH_DMATXNDESCRF_B1AP  ((uint32_t)0xFFFFFFFF)  /*!< Transmit Packet Timestamp Low */
00546
00547 /**
00548   * @brief  Bit definition of TDES1 RF register
00549   */
00550 #define ETH_DMATXNDESCRF_B2AP  ((uint32_t)0xFFFFFFFF)  /*!< Transmit Packet Timestamp High */
00551
00552 /**
00553   * @brief  Bit definition of TDES2 RF register
00554   */
00555 #define ETH_DMATXNDESCRF_IOC          ((uint32_t)0x80000000)  /*!< Interrupt on Completion */
00556 #define ETH_DMATXNDESCRF_TTSE         ((uint32_t)0x40000000)  /*!< Transmit Timestamp Enable */
00557 #define ETH_DMATXNDESCRF_B2L          ((uint32_t)0x3FFF0000)  /*!< Buffer 2 Length */
00558 #define ETH_DMATXNDESCRF_VTIR         ((uint32_t)0x0000C000)  /*!< VLAN Tag Insertion or Replacement mask */
00559 #define ETH_DMATXNDESCRF_VTIR_DISABLE ((uint32_t)0x00000000)  /*!< Do not add a VLAN tag. */
00560 #define ETH_DMATXNDESCRF_VTIR_REMOVE  ((uint32_t)0x00004000)  /*!< Remove the VLAN tag from the packets before transmission. */
00561 #define ETH_DMATXNDESCRF_VTIR_INSERT  ((uint32_t)0x00008000)  /*!< Insert a VLAN tag. */
00562 #define ETH_DMATXNDESCRF_VTIR_REPLACE ((uint32_t)0x0000C000)  /*!< Replace the VLAN tag. */
00563 #define ETH_DMATXNDESCRF_B1L          ((uint32_t)0x00003FFF)  /*!< Buffer 1 Length */
00564 #define ETH_DMATXNDESCRF_HL           ((uint32_t)0x000003FF)  /*!< Header Length */
00565
00566 /**
00567   * @brief  Bit definition of TDES3 RF register
00568   */
00569 #define ETH_DMATXNDESCRF_OWN                                 ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine */
00570 #define ETH_DMATXNDESCRF_CTXT                                ((uint32_t)0x40000000)  /*!< Context Type */
00571 #define ETH_DMATXNDESCRF_FD                                  ((uint32_t)0x20000000)  /*!< First Descriptor */
00572 #define ETH_DMATXNDESCRF_LD                                  ((uint32_t)0x10000000)  /*!< Last Descriptor */
00573 #define ETH_DMATXNDESCRF_CPC                                 ((uint32_t)0x0C000000)  /*!< CRC Pad Control mask */
00574 #define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT                   ((uint32_t)0x00000000)  /*!< CRC Pad Control: CRC and Pad Insertion */
00575 #define ETH_DMATXNDESCRF_CPC_CRC_INSERT                      ((uint32_t)0x04000000)  /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */
00576 #define ETH_DMATXNDESCRF_CPC_DISABLE                         ((uint32_t)0x08000000)  /*!< CRC Pad Control: Disable CRC Insertion */
00577 #define ETH_DMATXNDESCRF_CPC_CRC_REPLACE                     ((uint32_t)0x0C000000)  /*!< CRC Pad Control: CRC Replacement */
00578 #define ETH_DMATXNDESCRF_SAIC                                ((uint32_t)0x03800000)  /*!< SA Insertion Control mask*/
00579 #define ETH_DMATXNDESCRF_SAIC_DISABLE                        ((uint32_t)0x00000000)  /*!< SA Insertion Control: Do not include the source address */
00580 #define ETH_DMATXNDESCRF_SAIC_INSERT                         ((uint32_t)0x00800000)  /*!< SA Insertion Control: Include or insert the source address */
00581 #define ETH_DMATXNDESCRF_SAIC_REPLACE                        ((uint32_t)0x01000000)  /*!< SA Insertion Control: Replace the source address */
00582 #define ETH_DMATXNDESCRF_THL                                 ((uint32_t)0x00780000)  /*!< TCP Header Length */
00583 #define ETH_DMATXNDESCRF_TSE                                 ((uint32_t)0x00040000)  /*!< TCP segmentation enable */
00584 #define ETH_DMATXNDESCRF_CIC                                 ((uint32_t)0x00030000)  /*!< Checksum Insertion Control: 4 cases */
00585 #define ETH_DMATXNDESCRF_CIC_DISABLE                         ((uint32_t)0x00000000)  /*!< Do Nothing: Checksum Engine is disabled */
00586 #define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT                    ((uint32_t)0x00010000)  /*!< Only IP header checksum calculation and insertion are enabled. */
00587 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT            ((uint32_t)0x00020000)  /*!< IP header checksum and payload checksum calculation and insertion are
00588                                                                                           enabled, but pseudo header checksum is not calculated in hardware */
00589 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC  ((uint32_t)0x00030000)  /*!< IP Header checksum and payload checksum calculation and insertion are
00590                                                                                           enabled, and pseudo header checksum is calculated in hardware. */
00591 #define ETH_DMATXNDESCRF_TPL                                 ((uint32_t)0x0003FFFF)  /*!< TCP Payload Length */
00592 #define ETH_DMATXNDESCRF_FL                                  ((uint32_t)0x00007FFF)  /*!< Transmit End of Ring */
00593
00594 /*
00595    DMA Tx Normal Descriptor Write Back Format
00596   -----------------------------------------------------------------------------------------------
00597   TDES0 |                         Timestamp Low                                                  |
00598   -----------------------------------------------------------------------------------------------
00599   TDES1 |                         Timestamp High                                                 |
00600   -----------------------------------------------------------------------------------------------
00601   TDES2 |                           Reserved[31:0]                                               |
00602   -----------------------------------------------------------------------------------------------
00603   TDES3 | OWN(31) |                          Status[30:0]                                        |
00604   -----------------------------------------------------------------------------------------------
00605 */
00606
00607 /**
00608   * @brief  Bit definition of TDES0 WBF register
00609   */
00610 #define ETH_DMATXNDESCWBF_TTSL  ((uint32_t)0xFFFFFFFF)  /*!< Buffer1 Address Pointer or TSO Header Address Pointer */
00611
00612 /**
00613   * @brief  Bit definition of TDES1 WBF register
00614   */
00615 #define ETH_DMATXNDESCWBF_TTSH  ((uint32_t)0xFFFFFFFF)  /*!< Buffer2 Address Pointer */
00616
00617 /**
00618   * @brief  Bit definition of TDES3 WBF register
00619   */
00620 #define ETH_DMATXNDESCWBF_OWN                     ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine */
00621 #define ETH_DMATXNDESCWBF_CTXT                    ((uint32_t)0x40000000)  /*!< Context Type */
00622 #define ETH_DMATXNDESCWBF_FD                      ((uint32_t)0x20000000)  /*!< First Descriptor */
00623 #define ETH_DMATXNDESCWBF_LD                      ((uint32_t)0x10000000)  /*!< Last Descriptor */
00624 #define ETH_DMATXNDESCWBF_TTSS                    ((uint32_t)0x00020000)  /*!< Tx Timestamp Status */
00625 #define ETH_DMATXNDESCWBF_DP                      ((uint32_t)0x04000000)  /*!< Disable Padding */
00626 #define ETH_DMATXNDESCWBF_TTSE                    ((uint32_t)0x02000000)  /*!< Transmit Timestamp Enable */
00627 #define ETH_DMATXNDESCWBF_ES                      ((uint32_t)0x00008000)  /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */
00628 #define ETH_DMATXNDESCWBF_JT                      ((uint32_t)0x00004000)  /*!< Jabber Timeout */
00629 #define ETH_DMATXNDESCWBF_FF                      ((uint32_t)0x00002000)  /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */
00630 #define ETH_DMATXNDESCWBF_PCE                     ((uint32_t)0x00001000)  /*!< Payload Checksum Error */
00631 #define ETH_DMATXNDESCWBF_LCA                     ((uint32_t)0x00000800)  /*!< Loss of Carrier: carrier lost during transmission */
00632 #define ETH_DMATXNDESCWBF_NC                      ((uint32_t)0x00000400)  /*!< No Carrier: no carrier signal from the transceiver */
00633 #define ETH_DMATXNDESCWBF_LCO                     ((uint32_t)0x00000200)  /*!< Late Collision: transmission aborted due to collision */
00634 #define ETH_DMATXNDESCWBF_EC                      ((uint32_t)0x00000100)  /*!< Excessive Collision: transmission aborted after 16 collisions */
00635 #define ETH_DMATXNDESCWBF_CC                      ((uint32_t)0x000000F0)  /*!< Collision Count */
00636 #define ETH_DMATXNDESCWBF_ED                      ((uint32_t)0x00000008)  /*!< Excessive Deferral */
00637 #define ETH_DMATXNDESCWBF_UF                      ((uint32_t)0x00000004)  /*!< Underflow Error: late data arrival from the memory */
00638 #define ETH_DMATXNDESCWBF_DB                      ((uint32_t)0x00000002)  /*!< Deferred Bit */
00639 #define ETH_DMATXNDESCWBF_IHE                     ((uint32_t)0x00000004)  /*!< IP Header Error */
00640
00641
00642 /*
00643    DMA Tx Context Desciptor
00644   -----------------------------------------------------------------------------------------------
00645   TDES0 |                               Timestamp Low                                            |
00646   -----------------------------------------------------------------------------------------------
00647   TDES1 |                               Timestamp High                                           |
00648   -----------------------------------------------------------------------------------------------
00649   TDES2 |      Inner VLAN Tag[31:16]    | Reserved(15) |     Maximum Segment Size [14:0]         |
00650   -----------------------------------------------------------------------------------------------
00651   TDES3 | OWN(31) |                          Status[30:0]                                        |
00652   -----------------------------------------------------------------------------------------------
00653 */
00654
00655 /**
00656   * @brief  Bit definition of Tx context descriptor register 0
00657   */
00658 #define ETH_DMATXCDESC_TTSL  ((uint32_t)0xFFFFFFFF)  /*!< Transmit Packet Timestamp Low */
00659
00660 /**
00661   * @brief  Bit definition of Tx context descriptor register 1
00662   */
00663 #define ETH_DMATXCDESC_TTSH  ((uint32_t)0xFFFFFFFF)  /*!< Transmit Packet Timestamp High */
00664
00665 /**
00666   * @brief  Bit definition of Tx context descriptor register 2
00667   */
00668 #define ETH_DMATXCDESC_IVT   ((uint32_t)0xFFFF0000)  /*!< Inner VLAN Tag */
00669 #define ETH_DMATXCDESC_MSS   ((uint32_t)0x00003FFF)  /*!< Maximum Segment Size */
00670
00671 /**
00672   * @brief  Bit definition of Tx context descriptor register 3
00673   */
00674 #define ETH_DMATXCDESC_OWN                     ((uint32_t)0x80000000)     /*!< OWN bit: descriptor is owned by DMA engine */
00675 #define ETH_DMATXCDESC_CTXT                    ((uint32_t)0x40000000)     /*!< Context Type */
00676 #define ETH_DMATXCDESC_OSTC                    ((uint32_t)0x08000000)     /*!< One-Step Timestamp Correction Enable */
00677 #define ETH_DMATXCDESC_TCMSSV                  ((uint32_t)0x04000000)     /*!< One-Step Timestamp Correction Input or MSS Valid */
00678 #define ETH_DMATXCDESC_CDE                     ((uint32_t)0x00800000)     /*!< Context Descriptor Error */
00679 #define ETH_DMATXCDESC_IVTIR                   ((uint32_t)0x000C0000)     /*!< Inner VLAN Tag Insert or Replace Mask */
00680 #define ETH_DMATXCDESC_IVTIR_DISABLE           ((uint32_t)0x00000000)     /*!< Do not add the inner VLAN tag. */
00681 #define ETH_DMATXCDESC_IVTIR_REMOVE            ((uint32_t)0x00040000)     /*!< Remove the inner VLAN tag from the packets before transmission. */
00682 #define ETH_DMATXCDESC_IVTIR_INSERT            ((uint32_t)0x00080000)     /*!< Insert the inner VLAN tag. */
00683 #define ETH_DMATXCDESC_IVTIR_REPLACE           ((uint32_t)0x000C0000)     /*!< Replace the inner VLAN tag. */
00684 #define ETH_DMATXCDESC_IVLTV                   ((uint32_t)0x00020000)     /*!< Inner VLAN Tag Valid */
00685 #define ETH_DMATXCDESC_VLTV                    ((uint32_t)0x00010000)     /*!< VLAN Tag Valid */
00686 #define ETH_DMATXCDESC_VT                      ((uint32_t)0x0000FFFF)     /*!< VLAN Tag */
00687
00688 /**
00689   * @}
00690   */
00691
00692
00693 /** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition
00694   * @{
00695   */
00696
00697 /*
00698   DMA Rx Normal Descriptor read format
00699   -----------------------------------------------------------------------------------------------------------
00700   RDES0 |                                  Buffer1 or Header Address [31:0]                                 |
00701   -----------------------------------------------------------------------------------------------------------
00702   RDES1 |                                            Reserved                                               |
00703   -----------------------------------------------------------------------------------------------------------
00704   RDES2 |                                      Payload or Buffer2 Address[31:0]                             |
00705   -----------------------------------------------------------------------------------------------------------
00706   RDES3 | OWN(31) | IOC(30) | Reserved [29:26] | BUF2V(25) | BUF1V(24) |           Reserved [23:0]          |
00707   -----------------------------------------------------------------------------------------------------------
00708 */
00709
00710 /**
00711   * @brief  Bit definition of Rx normal descriptor register 0 read format
00712   */
00713 #define ETH_DMARXNDESCRF_BUF1AP        ((uint32_t)0xFFFFFFFF)  /*!< Header or Buffer 1 Address Pointer  */
00714
00715 /**
00716   * @brief  Bit definition of Rx normal descriptor register 2 read format
00717   */
00718 #define ETH_DMARXNDESCRF_BUF2AP        ((uint32_t)0xFFFFFFFF)  /*!< Buffer 2 Address Pointer  */
00719
00720 /**
00721   * @brief  Bit definition of Rx normal descriptor register 3 read format
00722   */
00723 #define ETH_DMARXNDESCRF_OWN         ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine  */
00724 #define ETH_DMARXNDESCRF_IOC         ((uint32_t)0x40000000)  /*!< Interrupt Enabled on Completion  */
00725 #define ETH_DMARXNDESCRF_BUF2V       ((uint32_t)0x02000000)  /*!< Buffer 2 Address Valid */
00726 #define ETH_DMARXNDESCRF_BUF1V       ((uint32_t)0x01000000)  /*!< Buffer 1 Address Valid */
00727
00728 /*
00729   DMA Rx Normal Descriptor write back format
00730   ---------------------------------------------------------------------------------------------------------------------
00731   RDES0 |                 Inner VLAN Tag[31:16]                 |                 Outer VLAN Tag[15:0]                |
00732         ---------------------------------------------------------------------------------------------------------------------
00733   RDES1 |       OAM code, or MAC Control Opcode [31:16]         |               Extended Status                       |
00734   ---------------------------------------------------------------------------------------------------------------------
00735   RDES2 |      MAC Filter Status[31:16]        | VF(15) | Reserved [14:12] | ARP Status [11:10] | Header Length [9:0] |
00736   ---------------------------------------------------------------------------------------------------------------------
00737   RDES3 | OWN(31) | CTXT(30) |  FD(29) | LD(28) |   Status[27:16]     | ES(15) |        Packet Length[14:0]           |
00738   ---------------------------------------------------------------------------------------------------------------------
00739 */
00740
00741 /**
00742   * @brief  Bit definition of Rx normal descriptor register 0 write back format
00743   */
00744 #define ETH_DMARXNDESCWBF_IVT        ((uint32_t)0xFFFF0000)  /*!< Inner VLAN Tag  */
00745 #define ETH_DMARXNDESCWBF_OVT        ((uint32_t)0x0000FFFF)  /*!< Outer VLAN Tag  */
00746
00747 /**
00748   * @brief  Bit definition of Rx normal descriptor register 1 write back format
00749   */
00750 #define ETH_DMARXNDESCWBF_OPC             ((uint32_t)0xFFFF0000)  /*!< OAM Sub-Type Code, or MAC Control Packet opcode  */
00751 #define ETH_DMARXNDESCWBF_TD              ((uint32_t)0x00008000)  /*!< Timestamp Dropped  */
00752 #define ETH_DMARXNDESCWBF_TSA             ((uint32_t)0x00004000)  /*!< Timestamp Available  */
00753 #define ETH_DMARXNDESCWBF_PV              ((uint32_t)0x00002000)  /*!< PTP Version  */
00754 #define ETH_DMARXNDESCWBF_PFT             ((uint32_t)0x00001000)  /*!< PTP Packet Type  */
00755 #define ETH_DMARXNDESCWBF_PMT_NO          ((uint32_t)0x00000000)  /*!< PTP Message Type: No PTP message received  */
00756 #define ETH_DMARXNDESCWBF_PMT_SYNC        ((uint32_t)0x00000100)  /*!< PTP Message Type: SYNC (all clock types)  */
00757 #define ETH_DMARXNDESCWBF_PMT_FUP         ((uint32_t)0x00000200)  /*!< PTP Message Type: Follow_Up (all clock types)  */
00758 #define ETH_DMARXNDESCWBF_PMT_DREQ        ((uint32_t)0x00000300)  /*!< PTP Message Type: Delay_Req (all clock types)  */
00759 #define ETH_DMARXNDESCWBF_PMT_DRESP       ((uint32_t)0x00000400)  /*!< PTP Message Type: Delay_Resp (all clock types)  */
00760 #define ETH_DMARXNDESCWBF_PMT_PDREQ       ((uint32_t)0x00000500)  /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock)  */
00761 #define ETH_DMARXNDESCWBF_PMT_PDRESP      ((uint32_t)0x00000600)  /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock)  */
00762 #define ETH_DMARXNDESCWBF_PMT_PDRESPFUP   ((uint32_t)0x00000700)  /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock)  */
00763 #define ETH_DMARXNDESCWBF_PMT_ANNOUNCE    ((uint32_t)0x00000800)  /*!< PTP Message Type: Announce  */
00764 #define ETH_DMARXNDESCWBF_PMT_MANAG       ((uint32_t)0x00000900)  /*!< PTP Message Type: Management  */
00765 #define ETH_DMARXNDESCWBF_PMT_SIGN        ((uint32_t)0x00000A00)  /*!< PTP Message Type: Signaling  */
00766 #define ETH_DMARXNDESCWBF_PMT_RESERVED    ((uint32_t)0x00000F00)  /*!< PTP Message Type: PTP packet with Reserved message type  */
00767 #define ETH_DMARXNDESCWBF_IPCE            ((uint32_t)0x00000080)  /*!< IP Payload Error */
00768 #define ETH_DMARXNDESCWBF_IPCB            ((uint32_t)0x00000040)  /*!< IP Checksum Bypassed */
00769 #define ETH_DMARXNDESCWBF_IPV6            ((uint32_t)0x00000020)  /*!< IPv6 header Present */
00770 #define ETH_DMARXNDESCWBF_IPV4            ((uint32_t)0x00000010)  /*!< IPv4 header Present */
00771 #define ETH_DMARXNDESCWBF_IPHE            ((uint32_t)0x00000008)  /*!< IP Header Error */
00772 #define ETH_DMARXNDESCWBF_PT              ((uint32_t)0x00000003)  /*!< Payload Type mask */
00773 #define ETH_DMARXNDESCWBF_PT_UNKNOWN      ((uint32_t)0x00000000)  /*!< Payload Type: Unknown type or IP/AV payload not processed */
00774 #define ETH_DMARXNDESCWBF_PT_UDP          ((uint32_t)0x00000001)  /*!< Payload Type: UDP */
00775 #define ETH_DMARXNDESCWBF_PT_TCP          ((uint32_t)0x00000002)  /*!< Payload Type: TCP  */
00776 #define ETH_DMARXNDESCWBF_PT_ICMP         ((uint32_t)0x00000003)  /*!< Payload Type: ICMP */
00777
00778 /**
00779   * @brief  Bit definition of Rx normal descriptor register 2 write back format
00780   */
00781 #define ETH_DMARXNDESCWBF_L3L4FM          ((uint32_t)0x20000000)  /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */
00782 #define ETH_DMARXNDESCWBF_L4FM            ((uint32_t)0x10000000)  /*!< Layer 4 Filter Match                  */
00783 #define ETH_DMARXNDESCWBF_L3FM            ((uint32_t)0x08000000)  /*!< Layer 3 Filter Match                  */
00784 #define ETH_DMARXNDESCWBF_MADRM           ((uint32_t)0x07F80000)  /*!< MAC Address Match or Hash Value       */
00785 #define ETH_DMARXNDESCWBF_HF              ((uint32_t)0x00040000)  /*!< Hash Filter Status                    */
00786 #define ETH_DMARXNDESCWBF_DAF             ((uint32_t)0x00020000)  /*!< Destination Address Filter Fail       */
00787 #define ETH_DMARXNDESCWBF_SAF             ((uint32_t)0x00010000)  /*!< SA Address Filter Fail                */
00788 #define ETH_DMARXNDESCWBF_VF              ((uint32_t)0x00008000)  /*!< VLAN Filter Status                    */
00789 #define ETH_DMARXNDESCWBF_ARPNR           ((uint32_t)0x00000400)  /*!< ARP Reply Not Generated               */
00790
00791
00792 /**
00793   * @brief  Bit definition of Rx normal descriptor register 3 write back format
00794   */
00795 #define ETH_DMARXNDESCWBF_OWN        ((uint32_t)0x80000000)  /*!< Own Bit */
00796 #define ETH_DMARXNDESCWBF_CTXT       ((uint32_t)0x40000000)  /*!< Receive Context Descriptor */
00797 #define ETH_DMARXNDESCWBF_FD         ((uint32_t)0x20000000)  /*!< First Descriptor */
00798 #define ETH_DMARXNDESCWBF_LD         ((uint32_t)0x10000000)  /*!< Last Descriptor */
00799 #define ETH_DMARXNDESCWBF_RS2V       ((uint32_t)0x08000000)  /*!< Receive Status RDES2 Valid */
00800 #define ETH_DMARXNDESCWBF_RS1V       ((uint32_t)0x04000000)  /*!< Receive Status RDES1 Valid */
00801 #define ETH_DMARXNDESCWBF_RS0V       ((uint32_t)0x02000000)  /*!< Receive Status RDES0 Valid */
00802 #define ETH_DMARXNDESCWBF_CE         ((uint32_t)0x01000000)  /*!< CRC Error */
00803 #define ETH_DMARXNDESCWBF_GP         ((uint32_t)0x00800000)  /*!< Giant Packet */
00804 #define ETH_DMARXNDESCWBF_RWT        ((uint32_t)0x00400000)  /*!< Receive Watchdog Timeout */
00805 #define ETH_DMARXNDESCWBF_OE         ((uint32_t)0x00200000)  /*!< Overflow Error */
00806 #define ETH_DMARXNDESCWBF_RE         ((uint32_t)0x00100000)  /*!< Receive Error */
00807 #define ETH_DMARXNDESCWBF_DE         ((uint32_t)0x00080000)  /*!< Dribble Bit Error */
00808 #define ETH_DMARXNDESCWBF_LT         ((uint32_t)0x00070000)  /*!< Length/Type Field */
00809 #define ETH_DMARXNDESCWBF_LT_LP      ((uint32_t)0x00000000)  /*!< The packet is a length packet */
00810 #define ETH_DMARXNDESCWBF_LT_TP      ((uint32_t)0x00010000)  /*!< The packet is a type packet */
00811 #define ETH_DMARXNDESCWBF_LT_ARP     ((uint32_t)0x00030000)  /*!< The packet is a ARP Request packet type */
00812 #define ETH_DMARXNDESCWBF_LT_VLAN    ((uint32_t)0x00040000)  /*!< The packet is a type packet with VLAN Tag */
00813 #define ETH_DMARXNDESCWBF_LT_DVLAN   ((uint32_t)0x00050000)  /*!< The packet is a type packet with Double VLAN Tag */
00814 #define ETH_DMARXNDESCWBF_LT_MAC     ((uint32_t)0x00060000)  /*!< The packet is a MAC Control packet type */
00815 #define ETH_DMARXNDESCWBF_LT_OAM     ((uint32_t)0x00070000)  /*!< The packet is a OAM packet type */
00816 #define ETH_DMARXNDESCWBF_ES         ((uint32_t)0x00008000)  /*!< Error Summary */
00817 #define ETH_DMARXNDESCWBF_PL         ((uint32_t)0x00007FFF)  /*!< Packet Length */
00818
00819 /*
00820   DMA Rx context Descriptor
00821   ---------------------------------------------------------------------------------------------------------------------
00822   RDES0 |                                     Timestamp Low[31:0]                                                     |
00823         ---------------------------------------------------------------------------------------------------------------------
00824   RDES1 |                                     Timestamp High[31:0]                                                    |
00825   ---------------------------------------------------------------------------------------------------------------------
00826   RDES2 |                                          Reserved                                                           |
00827   ---------------------------------------------------------------------------------------------------------------------
00828   RDES3 | OWN(31) | CTXT(30) |                                Reserved[29:0]                                          |
00829   ---------------------------------------------------------------------------------------------------------------------
00830 */
00831
00832 /**
00833   * @brief  Bit definition of Rx context descriptor register 0
00834   */
00835 #define ETH_DMARXCDESC_RTSL        ((uint32_t)0xFFFFFFFF)  /*!< Receive Packet Timestamp Low  */
00836
00837 /**
00838   * @brief  Bit definition of Rx context descriptor register 1
00839   */
00840 #define ETH_DMARXCDESC_RTSH        ((uint32_t)0xFFFFFFFF)  /*!< Receive Packet Timestamp High  */
00841
00842 /**
00843   * @brief  Bit definition of Rx context descriptor register 3
00844   */
00845 #define ETH_DMARXCDESC_OWN        ((uint32_t)0x80000000)  /*!< Own Bit  */
00846 #define ETH_DMARXCDESC_CTXT       ((uint32_t)0x40000000)  /*!< Receive Context Descriptor  */
00847
00848 /**
00849   * @}
00850   */
00851
00852 /** @defgroup ETH_Frame_settings ETH frame settings
00853   * @{
00854   */
00855 #define ETH_MAX_PACKET_SIZE      ((uint32_t)1528)    /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
00856 #define ETH_HEADER               ((uint32_t)14)    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
00857 #define ETH_CRC                  ((uint32_t)4)    /*!< Ethernet CRC */
00858 #define ETH_VLAN_TAG             ((uint32_t)4)    /*!< optional 802.1q VLAN Tag */
00859 #define ETH_MIN_PAYLOAD          ((uint32_t)46)    /*!< Minimum Ethernet payload size */
00860 #define ETH_MAX_PAYLOAD          ((uint32_t)1500)    /*!< Maximum Ethernet payload size */
00861 #define ETH_JUMBO_FRAME_PAYLOAD  ((uint32_t)9000)    /*!< Jumbo frame payload size */
00862 /**
00863   * @}
00864   */
00865
00866 /** @defgroup ETH_Error_Code ETH Error Code
00867   * @{
00868   */
00869 #define HAL_ETH_ERROR_NONE         ((uint32_t)0x00000000U)   /*!< No error            */
00870 #define HAL_ETH_ERROR_PARAM        ((uint32_t)0x00000001U)   /*!< Busy error          */
00871 #define HAL_ETH_ERROR_BUSY         ((uint32_t)0x00000002U)   /*!< Parameter error     */
00872 #define HAL_ETH_ERROR_TIMEOUT      ((uint32_t)0x00000004U)   /*!< Timeout error       */
00873 #define HAL_ETH_ERROR_DMA          ((uint32_t)0x00000008U)   /*!< DMA transfer error  */
00874 #define HAL_ETH_ERROR_MAC          ((uint32_t)0x00000010U)   /*!< MAC transfer error  */
00875 /**
00876   * @}
00877   */
00878
00879 /** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes
00880   * @{
00881   */
00882 #define ETH_TX_PACKETS_FEATURES_CSUM          ((uint32_t)0x00000001)
00883 #define ETH_TX_PACKETS_FEATURES_SAIC          ((uint32_t)0x00000002)
00884 #define ETH_TX_PACKETS_FEATURES_VLANTAG       ((uint32_t)0x00000004)
00885 #define ETH_TX_PACKETS_FEATURES_INNERVLANTAG  ((uint32_t)0x00000008)
00886 #define ETH_TX_PACKETS_FEATURES_TSO           ((uint32_t)0x00000010)
00887 #define ETH_TX_PACKETS_FEATURES_CRCPAD        ((uint32_t)0x00000020)
00888 /**
00889   * @}
00890   */
00891
00892 /** @defgroup ETH_Tx_Packet_Source_Addr_Control ETH Tx Packet Source Addr Control
00893   * @{
00894   */
00895 #define ETH_SRC_ADDR_CONTROL_DISABLE          ETH_DMATXNDESCRF_SAIC_DISABLE
00896 #define ETH_SRC_ADDR_INSERT                   ETH_DMATXNDESCRF_SAIC_INSERT
00897 #define ETH_SRC_ADDR_REPLACE                  ETH_DMATXNDESCRF_SAIC_REPLACE
00898 /**
00899   * @}
00900   */
00901
00902 /** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control
00903   * @{
00904   */
00905 #define ETH_CRC_PAD_DISABLE      ETH_DMATXNDESCRF_CPC_DISABLE
00906 #define ETH_CRC_PAD_INSERT       ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT
00907 #define ETH_CRC_INSERT           ETH_DMATXNDESCRF_CPC_CRC_INSERT
00908 #define ETH_CRC_REPLACE          ETH_DMATXNDESCRF_CPC_CRC_REPLACE
00909 /**
00910   * @}
00911   */
00912
00913 /** @defgroup ETH_Tx_Packet_Checksum_Control ETH Tx Packet Checksum Control
00914   * @{
00915   */
00916 #define ETH_CHECKSUM_DISABLE                         ETH_DMATXNDESCRF_CIC_DISABLE
00917 #define ETH_CHECKSUM_IPHDR_INSERT                    ETH_DMATXNDESCRF_CIC_IPHDR_INSERT
00918 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT            ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT
00919 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC  ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC
00920 /**
00921   * @}
00922   */
00923
00924 /** @defgroup ETH_Tx_Packet_VLAN_Control ETH Tx Packet VLAN Control
00925   * @{
00926   */
00927 #define ETH_VLAN_DISABLE  ETH_DMATXNDESCRF_VTIR_DISABLE
00928 #define ETH_VLAN_REMOVE   ETH_DMATXNDESCRF_VTIR_REMOVE
00929 #define ETH_VLAN_INSERT   ETH_DMATXNDESCRF_VTIR_INSERT
00930 #define ETH_VLAN_REPLACE  ETH_DMATXNDESCRF_VTIR_REPLACE
00931 /**
00932   * @}
00933   */
00934
00935 /** @defgroup ETH_Tx_Packet_Inner_VLAN_Control ETH Tx Packet Inner VLAN Control
00936   * @{
00937   */
00938 #define ETH_INNER_VLAN_DISABLE  ETH_DMATXCDESC_IVTIR_DISABLE
00939 #define ETH_INNER_VLAN_REMOVE   ETH_DMATXCDESC_IVTIR_REMOVE
00940 #define ETH_INNER_VLAN_INSERT   ETH_DMATXCDESC_IVTIR_INSERT
00941 #define ETH_INNER_VLAN_REPLACE  ETH_DMATXCDESC_IVTIR_REPLACE
00942 /**
00943   * @}
00944   */
00945
00946 /** @defgroup ETH_Rx_Checksum_Status ETH Rx Checksum Status
00947   * @{
00948   */
00949 #define ETH_CHECKSUM_BYPASSED           ETH_DMARXNDESCWBF_IPCB
00950 #define ETH_CHECKSUM_IP_HEADER_ERROR    ETH_DMARXNDESCWBF_IPHE
00951 #define ETH_CHECKSUM_IP_PAYLOAD_ERROR   ETH_DMARXNDESCWBF_IPCE
00952 /**
00953   * @}
00954   */
00955
00956 /** @defgroup ETH_Rx_IP_Header_Type ETH Rx IP Header Type
00957   * @{
00958   */
00959 #define ETH_IP_HEADER_IPV4   ETH_DMARXNDESCWBF_IPV4
00960 #define ETH_IP_HEADER_IPV6   ETH_DMARXNDESCWBF_IPV6
00961 /**
00962   * @}
00963   */
00964
00965 /** @defgroup ETH_Rx_Payload_Type ETH Rx Payload Type
00966   * @{
00967   */
00968 #define ETH_IP_PAYLOAD_UNKNOWN   ETH_DMARXNDESCWBF_PT_UNKNOWN
00969 #define ETH_IP_PAYLOAD_UDP       ETH_DMARXNDESCWBF_PT_UDP
00970 #define ETH_IP_PAYLOAD_TCP       ETH_DMARXNDESCWBF_PT_TCP
00971 #define ETH_IP_PAYLOAD_ICMPN     ETH_DMARXNDESCWBF_PT_ICMP
00972 /**
00973   * @}
00974   */
00975
00976 /** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status
00977   * @{
00978   */
00979 #define ETH_HASH_FILTER_PASS        ETH_DMARXNDESCWBF_HF
00980 #define ETH_VLAN_FILTER_PASS        ETH_DMARXNDESCWBF_VF
00981 #define ETH_DEST_ADDRESS_FAIL       ETH_DMARXNDESCWBF_DAF
00982 #define ETH_SOURCE_ADDRESS_FAIL     ETH_DMARXNDESCWBF_SAF
00983 /**
00984   * @}
00985   */
00986
00987 /** @defgroup ETH_Rx_L3_Filter_Status ETH Rx L3 Filter Status
00988   * @{
00989   */
00990 #define ETH_L3_FILTER0_MATCH        ETH_DMARXNDESCWBF_L3FM
00991 #define ETH_L3_FILTER1_MATCH        (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM)
00992 /**
00993   * @}
00994   */
00995
00996 /** @defgroup ETH_Rx_L4_Filter_Status ETH Rx L4 Filter Status
00997   * @{
00998   */
00999 #define ETH_L4_FILTER0_MATCH        ETH_DMARXNDESCWBF_L4FM
01000 #define ETH_L4_FILTER1_MATCH        (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM)
01001 /**
01002   * @}
01003   */
01004
01005 /** @defgroup ETH_Rx_Error_Code ETH Rx Error Code
01006   * @{
01007   */
01008 #define ETH_DRIBBLE_BIT_ERROR   ETH_DMARXNDESCWBF_DE
01009 #define ETH_RECEIVE_ERROR       ETH_DMARXNDESCWBF_RE
01010 #define ETH_RECEIVE_OVERFLOW    ETH_DMARXNDESCWBF_OE
01011 #define ETH_WATCHDOG_TIMEOUT    ETH_DMARXNDESCWBF_RWT
01012 #define ETH_GIANT_PACKET        ETH_DMARXNDESCWBF_GP
01013 #define ETH_CRC_ERROR           ETH_DMARXNDESCWBF_CE
01014 /**
01015   * @}
01016   */
01017
01018 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
01019   * @{
01020   */
01021 #define ETH_DMAARBITRATION_RX        ETH_DMAMR_DA
01022 #define ETH_DMAARBITRATION_RX1_TX1   ((uint32_t)0x00000000)
01023 #define ETH_DMAARBITRATION_RX2_TX1   ETH_DMAMR_PR_2_1
01024 #define ETH_DMAARBITRATION_RX3_TX1   ETH_DMAMR_PR_3_1
01025 #define ETH_DMAARBITRATION_RX4_TX1   ETH_DMAMR_PR_4_1
01026 #define ETH_DMAARBITRATION_RX5_TX1   ETH_DMAMR_PR_5_1
01027 #define ETH_DMAARBITRATION_RX6_TX1   ETH_DMAMR_PR_6_1
01028 #define ETH_DMAARBITRATION_RX7_TX1   ETH_DMAMR_PR_7_1
01029 #define ETH_DMAARBITRATION_RX8_TX1   ETH_DMAMR_PR_8_1
01030 #define ETH_DMAARBITRATION_TX        (ETH_DMAMR_TXPR | ETH_DMAMR_DA)
01031 #define ETH_DMAARBITRATION_TX1_RX1   ((uint32_t)0x00000000)
01032 #define ETH_DMAARBITRATION_TX2_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)
01033 #define ETH_DMAARBITRATION_TX3_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1)
01034 #define ETH_DMAARBITRATION_TX4_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1)
01035 #define ETH_DMAARBITRATION_TX5_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1)
01036 #define ETH_DMAARBITRATION_TX6_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1)
01037 #define ETH_DMAARBITRATION_TX7_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1)
01038 #define ETH_DMAARBITRATION_TX8_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1)
01039 /**
01040   * @}
01041   */
01042
01043  /** @defgroup ETH_Burst_Mode ETH Burst Mode
01044   * @{
01045   */
01046 #define ETH_BURSTLENGTH_FIXED           ETH_DMASBMR_FB
01047 #define ETH_BURSTLENGTH_MIXED           ETH_DMASBMR_MB
01048 #define ETH_BURSTLENGTH_UNSPECIFIED     ((uint32_t)0x00000000)
01049 /**
01050   * @}
01051   */
01052
01053 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
01054   * @{
01055   */
01056 #define ETH_TXDMABURSTLENGTH_1BEAT          ETH_DMACTCR_TPBL_1PBL
01057 #define ETH_TXDMABURSTLENGTH_2BEAT          ETH_DMACTCR_TPBL_2PBL
01058 #define ETH_TXDMABURSTLENGTH_4BEAT          ETH_DMACTCR_TPBL_4PBL
01059 #define ETH_TXDMABURSTLENGTH_8BEAT          ETH_DMACTCR_TPBL_8PBL
01060 #define ETH_TXDMABURSTLENGTH_16BEAT         ETH_DMACTCR_TPBL_16PBL
01061 #define ETH_TXDMABURSTLENGTH_32BEAT         ETH_DMACTCR_TPBL_32PBL
01062 /**
01063   * @}
01064   */
01065
01066 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
01067   * @{
01068   */
01069 #define ETH_RXDMABURSTLENGTH_1BEAT          ETH_DMACRCR_RPBL_1PBL
01070 #define ETH_RXDMABURSTLENGTH_2BEAT          ETH_DMACRCR_RPBL_2PBL
01071 #define ETH_RXDMABURSTLENGTH_4BEAT          ETH_DMACRCR_RPBL_4PBL
01072 #define ETH_RXDMABURSTLENGTH_8BEAT          ETH_DMACRCR_RPBL_8PBL
01073 #define ETH_RXDMABURSTLENGTH_16BEAT         ETH_DMACRCR_RPBL_16PBL
01074 #define ETH_RXDMABURSTLENGTH_32BEAT         ETH_DMACRCR_RPBL_32PBL
01075 /**
01076   * @}
01077   */
01078
01079 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
01080   * @{
01081   */
01082 #define ETH_DMA_NORMAL_IT                 ETH_DMACIER_NIE
01083 #define ETH_DMA_ABNORMAL_IT               ETH_DMACIER_AIE
01084 #define ETH_DMA_CONTEXT_DESC_ERROR_IT     ETH_DMACIER_CDEE
01085 #define ETH_DMA_FATAL_BUS_ERROR_IT        ETH_DMACIER_FBEE
01086 #define ETH_DMA_EARLY_RX_IT               ETH_DMACIER_ERIE
01087 #define ETH_DMA_EARLY_TX_IT               ETH_DMACIER_ETIE
01088 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT    ETH_DMACIER_RWTE
01089 #define ETH_DMA_RX_PROCESS_STOPPED_IT     ETH_DMACIER_RSE
01090 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT  ETH_DMACIER_RBUE
01091 #define ETH_DMA_RX_IT                     ETH_DMACIER_RIE
01092 #define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT  ETH_DMACIER_TBUE
01093 #define ETH_DMA_TX_PROCESS_STOPPED_IT     ETH_DMACIER_TXSE
01094 #define ETH_DMA_TX_IT                     ETH_DMACIER_TIE
01095 /**
01096   * @}
01097   */
01098
01099 /** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags
01100   * @{
01101   */
01102 #define ETH_DMA_RX_NO_ERROR_FLAG                 ((uint32_t)0x00000000U)
01103 #define ETH_DMA_RX_DESC_READ_ERROR_FLAG          (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0)
01104 #define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG         (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1)
01105 #define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG        (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0)
01106 #define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG        ETH_DMACSR_REB_BIT_2
01107 #define ETH_DMA_TX_NO_ERROR_FLAG                 ((uint32_t)0x00000000U)
01108 #define ETH_DMA_TX_DESC_READ_ERROR_FLAG          (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0)
01109 #define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG         (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1)
01110 #define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG        (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0)
01111 #define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG        ETH_DMACSR_TEB_BIT_2
01112 #define ETH_DMA_CONTEXT_DESC_ERROR_FLAG           ETH_DMACSR_CDE
01113 #define ETH_DMA_FATAL_BUS_ERROR_FLAG              ETH_DMACSR_FBE
01114 #define ETH_DMA_EARLY_TX_IT_FLAG                  ETH_DMACSR_ERI
01115 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG          ETH_DMACSR_RWT
01116 #define ETH_DMA_RX_PROCESS_STOPPED_FLAG           ETH_DMACSR_RPS
01117 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG        ETH_DMACSR_RBU
01118 #define ETH_DMA_TX_PROCESS_STOPPED_FLAG           ETH_DMACSR_TPS
01119 /**
01120   * @}
01121   */
01122
01123 /** @defgroup ETH_Transmit_Mode ETH Transmit Mode
01124   * @{
01125   */
01126 #define ETH_TRANSMITSTOREFORWARD       ETH_MTLTQOMR_TSF
01127 #define ETH_TRANSMITTHRESHOLD_32       ETH_MTLTQOMR_TTC_32BITS
01128 #define ETH_TRANSMITTHRESHOLD_64       ETH_MTLTQOMR_TTC_64BITS
01129 #define ETH_TRANSMITTHRESHOLD_96       ETH_MTLTQOMR_TTC_96BITS
01130 #define ETH_TRANSMITTHRESHOLD_128      ETH_MTLTQOMR_TTC_128BITS
01131 #define ETH_TRANSMITTHRESHOLD_192      ETH_MTLTQOMR_TTC_192BITS
01132 #define ETH_TRANSMITTHRESHOLD_256      ETH_MTLTQOMR_TTC_256BITS
01133 #define ETH_TRANSMITTHRESHOLD_384      ETH_MTLTQOMR_TTC_384BITS
01134 #define ETH_TRANSMITTHRESHOLD_512      ETH_MTLTQOMR_TTC_512BITS
01135 /**
01136   * @}
01137   */
01138
01139 /** @defgroup ETH_Receive_Mode ETH Receive Mode
01140   * @{
01141   */
01142 #define ETH_RECEIVESTOREFORWARD        ETH_MTLRQOMR_RSF
01143 #define ETH_RECEIVETHRESHOLD8_64       ETH_MTLRQOMR_RTC_64BITS
01144 #define ETH_RECEIVETHRESHOLD8_32       ETH_MTLRQOMR_RTC_32BITS
01145 #define ETH_RECEIVETHRESHOLD8_96       ETH_MTLRQOMR_RTC_96BITS
01146 #define ETH_RECEIVETHRESHOLD8_128      ETH_MTLRQOMR_RTC_128BITS
01147 /**
01148   * @}
01149   */
01150
01151 /** @defgroup ETH_Pause_Low_Threshold  ETH Pause Low Threshold
01152   * @{
01153   */
01154 #define ETH_PAUSELOWTHRESHOLD_MINUS_4        ETH_MACTFCR_PLT_MINUS4
01155 #define ETH_PAUSELOWTHRESHOLD_MINUS_28       ETH_MACTFCR_PLT_MINUS28
01156 #define ETH_PAUSELOWTHRESHOLD_MINUS_36       ETH_MACTFCR_PLT_MINUS36
01157 #define ETH_PAUSELOWTHRESHOLD_MINUS_144      ETH_MACTFCR_PLT_MINUS144
01158 #define ETH_PAUSELOWTHRESHOLD_MINUS_256      ETH_MACTFCR_PLT_MINUS256
01159 #define ETH_PAUSELOWTHRESHOLD_MINUS_512      ETH_MACTFCR_PLT_MINUS512
01160 /**
01161   * @}
01162   */
01163
01164 /** @defgroup ETH_Watchdog_Timeout ETH Watchdog Timeout
01165   * @{
01166   */
01167 #define ETH_WATCHDOGTIMEOUT_2KB      ETH_MACWTR_WTO_2KB
01168 #define ETH_WATCHDOGTIMEOUT_3KB      ETH_MACWTR_WTO_3KB
01169 #define ETH_WATCHDOGTIMEOUT_4KB      ETH_MACWTR_WTO_4KB
01170 #define ETH_WATCHDOGTIMEOUT_5KB      ETH_MACWTR_WTO_5KB
01171 #define ETH_WATCHDOGTIMEOUT_6KB      ETH_MACWTR_WTO_6KB
01172 #define ETH_WATCHDOGTIMEOUT_7KB      ETH_MACWTR_WTO_7KB
01173 #define ETH_WATCHDOGTIMEOUT_8KB      ETH_MACWTR_WTO_8KB
01174 #define ETH_WATCHDOGTIMEOUT_9KB      ETH_MACWTR_WTO_9KB
01175 #define ETH_WATCHDOGTIMEOUT_10KB     ETH_MACWTR_WTO_10KB
01176 #define ETH_WATCHDOGTIMEOUT_11KB     ETH_MACWTR_WTO_12KB
01177 #define ETH_WATCHDOGTIMEOUT_12KB     ETH_MACWTR_WTO_12KB
01178 #define ETH_WATCHDOGTIMEOUT_13KB     ETH_MACWTR_WTO_13KB
01179 #define ETH_WATCHDOGTIMEOUT_14KB     ETH_MACWTR_WTO_14KB
01180 #define ETH_WATCHDOGTIMEOUT_15KB     ETH_MACWTR_WTO_15KB
01181 #define ETH_WATCHDOGTIMEOUT_16KB     ETH_MACWTR_WTO_16KB
01182 /**
01183   * @}
01184   */
01185
01186 /** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap
01187   * @{
01188   */
01189 #define ETH_INTERPACKETGAP_96BIT   ETH_MACCR_IPG_96BIT
01190 #define ETH_INTERPACKETGAP_88BIT   ETH_MACCR_IPG_88BIT
01191 #define ETH_INTERPACKETGAP_80BIT   ETH_MACCR_IPG_80BIT
01192 #define ETH_INTERPACKETGAP_72BIT   ETH_MACCR_IPG_72BIT
01193 #define ETH_INTERPACKETGAP_64BIT   ETH_MACCR_IPG_64BIT
01194 #define ETH_INTERPACKETGAP_56BIT   ETH_MACCR_IPG_56BIT
01195 #define ETH_INTERPACKETGAP_48BIT   ETH_MACCR_IPG_48BIT
01196 #define ETH_INTERPACKETGAP_40BIT   ETH_MACCR_IPG_40BIT
01197 /**
01198   * @}
01199   */
01200
01201 /** @defgroup ETH_Speed  ETH Speed
01202   * @{
01203   */
01204 #define ETH_SPEED_10M        ((uint32_t)0x00000000)
01205 #define ETH_SPEED_100M       ETH_MACCR_FES
01206 /**
01207   * @}
01208   */
01209
01210 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
01211   * @{
01212   */
01213 #define ETH_FULLDUPLEX_MODE       ETH_MACCR_DM
01214 #define ETH_HALFDUPLEX_MODE       ((uint32_t)0x00000000)
01215 /**
01216   * @}
01217   */
01218
01219 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
01220   * @{
01221   */
01222 #define ETH_BACKOFFLIMIT_10  ETH_MACCR_BL_10
01223 #define ETH_BACKOFFLIMIT_8   ETH_MACCR_BL_8
01224 #define ETH_BACKOFFLIMIT_4   ETH_MACCR_BL_4
01225 #define ETH_BACKOFFLIMIT_1   ETH_MACCR_BL_1
01226 /**
01227   * @}
01228   */
01229
01230 /** @defgroup ETH_Preamble_Length ETH Preamble Length
01231   * @{
01232   */
01233 #define ETH_PREAMBLELENGTH_7      ETH_MACCR_PRELEN_7
01234 #define ETH_PREAMBLELENGTH_5      ETH_MACCR_PRELEN_5
01235 #define ETH_PREAMBLELENGTH_3      ETH_MACCR_PRELEN_3
01236 /**
01237   * @}
01238   */
01239
01240 /** @defgroup ETH_Source_Addr_Control ETH Source Addr Control
01241   * @{
01242   */
01243 #define ETH_SOURCEADDRESS_DISABLE           ((uint32_t)0x00000000)
01244 #define ETH_SOURCEADDRESS_INSERT_ADDR0      ETH_MACCR_SARC_INSADDR0
01245 #define ETH_SOURCEADDRESS_INSERT_ADDR1      ETH_MACCR_SARC_INSADDR1
01246 #define ETH_SOURCEADDRESS_REPLACE_ADDR0     ETH_MACCR_SARC_REPADDR0
01247 #define ETH_SOURCEADDRESS_REPLACE_ADDR1     ETH_MACCR_SARC_REPADDR1
01248 /**
01249   * @}
01250   */
01251
01252 /** @defgroup ETH_Control_Packets_Filter ETH Control Packets Filter
01253   * @{
01254   */
01255 #define ETH_CTRLPACKETS_BLOCK_ALL                      ETH_MACPFR_PCF_BLOCKALL
01256 #define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA          ETH_MACPFR_PCF_FORWARDALLEXCEPTPA
01257 #define ETH_CTRLPACKETS_FORWARD_ALL                    ETH_MACPFR_PCF_FORWARDALL
01258 #define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER     ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER
01259 /**
01260   * @}
01261   */
01262
01263 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
01264   * @{
01265   */
01266 #define ETH_VLANTAGCOMPARISON_16BIT          ((uint32_t)0x00000000U)
01267 #define ETH_VLANTAGCOMPARISON_12BIT          ETH_MACVTR_ETV
01268 /**
01269   * @}
01270   */
01271
01272 /** @defgroup ETH_MAC_addresses ETH MAC addresses
01273   * @{
01274   */
01275 #define ETH_MAC_ADDRESS0     ((uint32_t)0x00000000U)
01276 #define ETH_MAC_ADDRESS1     ((uint32_t)0x00000008U)
01277 #define ETH_MAC_ADDRESS2     ((uint32_t)0x00000010U)
01278 #define ETH_MAC_ADDRESS3     ((uint32_t)0x00000018U)
01279 /**
01280   * @}
01281   */
01282
01283 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
01284   * @{
01285   */
01286 #define ETH_MAC_RX_STATUS_IT     ETH_MACIER_RXSTSIE
01287 #define ETH_MAC_TX_STATUS_IT     ETH_MACIER_TXSTSIE
01288 #define ETH_MAC_TIMESTAMP_IT     ETH_MACIER_TSIE
01289 #define ETH_MAC_LPI_IT           ETH_MACIER_LPIIE
01290 #define ETH_MAC_PMT_IT           ETH_MACIER_PMTIE
01291 #define ETH_MAC_PHY_IT           ETH_MACIER_PHYIE
01292 /**
01293   * @}
01294   */
01295
01296 /** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event
01297   * @{
01298   */
01299 #define ETH_WAKEUP_PACKET_RECIEVED    ETH_MACPCSR_RWKPRCVD
01300 #define ETH_MAGIC_PACKET_RECIEVED     ETH_MACPCSR_MGKPRCVD
01301 /**
01302   * @}
01303   */
01304
01305 /** @defgroup ETH_MAC_Rx_Tx_Status ETH MAC Rx Tx Status
01306   * @{
01307   */
01308 #define ETH_RECEIVE_WATCHDOG_TIMEOUT        ETH_MACRXTXSR_RWT
01309 #define ETH_EXECESSIVE_COLLISIONS           ETH_MACRXTXSR_EXCOL
01310 #define ETH_LATE_COLLISIONS                 ETH_MACRXTXSR_LCOL
01311 #define ETH_EXECESSIVE_DEFERRAL             ETH_MACRXTXSR_EXDEF
01312 #define ETH_LOSS_OF_CARRIER                 ETH_MACRXTXSR_LCARR
01313 #define ETH_NO_CARRIER                      ETH_MACRXTXSR_NCARR
01314 #define ETH_TRANSMIT_JABBR_TIMEOUT          ETH_MACRXTXSR_TJT
01315 /**
01316   * @}
01317   */
01318
01319 /**
01320   * @}
01321   */
01322
01323 /* Exported macro ------------------------------------------------------------*/
01324 /** @defgroup ETH_Exported_Macros ETH Exported Macros
01325   * @{
01326   */
01327
01328 /** @brief Reset ETH handle state
01329   * @param  __HANDLE__: specifies the ETH handle.
01330   * @retval None
01331   */
01332 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
01333
01334 /**
01335   * @brief  Enables the specified ETHERNET DMA interrupts.
01336   * @param  __HANDLE__   : ETH Handle
01337   * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
01338   *   enabled @ref ETH_DMA_Interrupts
01339   * @retval None
01340   */
01341 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__))
01342
01343 /**
01344   * @brief  Disables the specified ETHERNET DMA interrupts.
01345   * @param  __HANDLE__   : ETH Handle
01346   * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
01347   *   disabled. @ref ETH_DMA_Interrupts
01348   * @retval None
01349   */
01350 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))
01351
01352 /**
01353   * @brief  Gets the ETHERNET DMA IT source enabled or disabled.
01354   * @param  __HANDLE__   : ETH Handle
01355   * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
01356   * @retval The ETH DMA IT Source enabled or disabled
01357   */
01358 #define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      (((__HANDLE__)->Instance->DMACIER &  (__INTERRUPT__)) == (__INTERRUPT__))
01359
01360 /**
01361   * @brief  Gets the ETHERNET DMA IT pending bit.
01362   * @param  __HANDLE__   : ETH Handle
01363   * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
01364   * @retval The state of ETH DMA IT (SET or RESET)
01365   */
01366 #define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__)      (((__HANDLE__)->Instance->DMACSR &  (__INTERRUPT__)) == (__INTERRUPT__))
01367
01368 /**
01369   * @brief  Clears the ETHERNET DMA IT pending bit.
01370   * @param  __HANDLE__   : ETH Handle
01371   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
01372   * @retval None
01373   */
01374 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))
01375
01376 /**
01377   * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
01378 * @param  __HANDLE__: ETH Handle
01379   * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
01380   * @retval The state of ETH DMA FLAG (SET or RESET).
01381   */
01382 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))
01383
01384 /**
01385   * @brief  Clears the specified ETHERNET DMA flag.
01386 * @param  __HANDLE__: ETH Handle
01387   * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
01388   * @retval The state of ETH DMA FLAG (SET or RESET).
01389   */
01390 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)                   ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))
01391
01392 /**
01393   * @brief  Enables the specified ETHERNET MAC interrupts.
01394   * @param  __HANDLE__   : ETH Handle
01395   * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
01396   *   enabled @ref ETH_MAC_Interrupts
01397   * @retval None
01398   */
01399 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))
01400
01401 /**
01402   * @brief  Disables the specified ETHERNET MAC interrupts.
01403   * @param  __HANDLE__   : ETH Handle
01404   * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
01405   *   enabled @ref ETH_MAC_Interrupts
01406   * @retval None
01407   */
01408 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))
01409
01410 /**
01411   * @brief  Checks whether the specified ETHERNET MAC flag is set or not.
01412   * @param  __HANDLE__: ETH Handle
01413   * @param  __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts
01414   * @retval The state of ETH MAC IT (SET or RESET).
01415   */
01416 #define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__)                   (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__))
01417
01418 /*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */
01419 #define ETH_WAKEUP_EXTI_LINE  ((uint32_t)0x00400000)  /* !<  86 - 64 = 22 */
01420
01421 /**
01422   * @brief Enable the ETH WAKEUP Exti Line.
01423   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
01424   *   @arg ETH_WAKEUP_EXTI_LINE
01425   * @retval None.
01426   */
01427 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__)   (EXTI_D1->IMR3 |= (__EXTI_LINE__))
01428
01429 /**
01430   * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
01431   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
01432   *   @arg ETH_WAKEUP_EXTI_LINE
01433   * @retval EXTI ETH WAKEUP Line Status.
01434   */
01435 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__)  (EXTI_D1->PR3 & (__EXTI_LINE__))
01436
01437 /**
01438   * @brief Clear the ETH WAKEUP Exti flag.
01439   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
01440   *   @arg ETH_WAKEUP_EXTI_LINE
01441   * @retval None.
01442   */
01443 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__))
01444
01445
01446 /**
01447   * @brief  enable rising edge interrupt on selected EXTI line.
01448   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
01449   *  @arg ETH_WAKEUP_EXTI_LINE
01450   * @retval None
01451   */
01452 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \
01453                                                                 (EXTI->RTSR3 |= (__EXTI_LINE__))
01454
01455 /**
01456   * @brief  enable falling edge interrupt on selected EXTI line.
01457   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
01458   *  @arg ETH_WAKEUP_EXTI_LINE
01459   * @retval None
01460   */
01461 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\
01462                                                                  (EXTI->FTSR3 |= (__EXTI_LINE__))
01463
01464 /**
01465   * @brief  enable falling edge interrupt on selected EXTI line.
01466   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
01467   *  @arg ETH_WAKEUP_EXTI_LINE
01468   * @retval None
01469   */
01470 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\
01471                                                                         (EXTI->FTSR3 |= (__EXTI_LINE__))
01472
01473 /**
01474   * @brief  Generates a Software interrupt on selected EXTI line.
01475   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
01476   *  @arg ETH_WAKEUP_EXTI_LINE
01477   * @retval None
01478   */
01479 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__))
01480
01481 /**
01482   * @}
01483   */
01484
01485 /* Include ETH HAL Extension module */
01486 #include "stm32h7xx_hal_eth_ex.h"
01487
01488 /* Exported functions --------------------------------------------------------*/
01489
01490 /** @addtogroup ETH_Exported_Functions
01491   * @{
01492   */
01493
01494 /** @addtogroup ETH_Exported_Functions_Group1
01495   * @{
01496   */
01497 /* Initialization and de initialization functions  **********************************/
01498 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
01499 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
01500 void              HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
01501 void              HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
01502 HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1,uint8_t *pBuffer2);
01503 /**
01504   * @}
01505   */
01506
01507 /** @addtogroup ETH_Exported_Functions_Group2
01508   * @{
01509   */
01510 /* IO operation functions *******************************************************/
01511 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
01512 HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth);
01513 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
01514 HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth);
01515
01516 uint8_t           HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth);
01517 HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *pBuffer);
01518 HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length);
01519 HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo);
01520 HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth);
01521
01522 HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout);
01523 HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig);
01524
01525 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue);
01526 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue);
01527
01528 void              HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
01529 void              HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
01530 void              HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
01531 void              HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth);
01532 void              HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth);
01533 void              HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth);
01534 void              HAL_ETH_EEECallback(ETH_HandleTypeDef *heth);
01535 void              HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);
01536 /**
01537   * @}
01538   */
01539
01540 /** @addtogroup ETH_Exported_Functions_Group3
01541   * @{
01542   */
01543 /* Peripheral Control functions  **********************************************/
01544 /* MAC & DMA Configuration APIs  **********************************************/
01545 HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
01546 HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
01547 HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
01548 HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
01549 void              HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
01550
01551 /* MAC VLAN Processing APIs    ************************************************/
01552 void              HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier);
01553
01554 /* MAC L2 Packet Filtering APIs  **********************************************/
01555 HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
01556 HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
01557 HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);
01558 HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr);
01559
01560 /* MAC Power Down APIs    *****************************************************/
01561 void              HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig);
01562 void              HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);
01563 HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);
01564
01565 /**
01566   * @}
01567   */
01568
01569 /** @addtogroup ETH_Exported_Functions_Group4
01570   * @{
01571   */
01572 /* Peripheral State functions  **************************************************/
01573 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
01574 uint32_t             HAL_ETH_GetError(ETH_HandleTypeDef *heth);
01575 uint32_t             HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth);
01576 uint32_t             HAL_ETH_GetMACError(ETH_HandleTypeDef *heth);
01577 uint32_t             HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);
01578 /**
01579   * @}
01580   */
01581
01582 /**
01583   * @}
01584   */
01585
01586 /**
01587   * @}
01588   */
01589
01590 /**
01591   * @}
01592   */
01593
01594 #ifdef __cplusplus
01595 }
01596 #endif
01597
01598 #endif /* __STM32H7xx_HAL_ETH_H */
01599
01600
01601
01602 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_eth_ex.c Source File

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stm32h7xx_hal_eth_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_eth_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   ETH HAL Extended module driver.
00008   *
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00013   *
00014   * Redistribution and use in source and binary forms, with or without modification,
00015   * are permitted provided that the following conditions are met:
00016   *   1. Redistributions of source code must retain the above copyright notice,
00017   *      this list of conditions and the following disclaimer.
00018   *   2. Redistributions in binary form must reproduce the above copyright notice,
00019   *      this list of conditions and the following disclaimer in the documentation
00020   *      and/or other materials provided with the distribution.
00021   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00022   *      may be used to endorse or promote products derived from this software
00023   *      without specific prior written permission.
00024   *
00025   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00026   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00027   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00028   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00029   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00030   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00031   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00032   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00033   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00034   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00035   *
00036   ******************************************************************************
00037   */
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32h7xx_hal.h"
00041
00042 /** @addtogroup STM32H7xx_HAL_Driver
00043   * @{
00044   */
00045
00046 /** @defgroup ETHEx ETHEx
00047   * @brief ETH HAL Extended module driver
00048   * @{
00049   */
00050
00051 #ifdef HAL_ETH_MODULE_ENABLED
00052
00053 /* Private typedef -----------------------------------------------------------*/
00054 /* Private define ------------------------------------------------------------*/
00055 /** @defgroup ETHEx_Private_Constants ETHEx Private Constants
00056   * @{
00057   */
00058 #define ETH_MACL4CR_MASK     (ETH_MACL3L4CR_L4PEN | ETH_MACL3L4CR_L4SPM | \
00059                               ETH_MACL3L4CR_L4SPIM | ETH_MACL3L4CR_L4DPM | \
00060                               ETH_MACL3L4CR_L4DPIM)
00061
00062 #define ETH_MACL3CR_MASK     (ETH_MACL3L4CR_L3PEN | ETH_MACL3L4CR_L3SAM | \
00063                               ETH_MACL3L4CR_L3SAIM | ETH_MACL3L4CR_L3DAM | \
00064                               ETH_MACL3L4CR_L3DAIM | ETH_MACL3L4CR_L3HSBM | \
00065                               ETH_MACL3L4CR_L3HDBM)
00066
00067 #define ETH_MACRXVLAN_MASK (ETH_MACVTR_EIVLRXS | ETH_MACVTR_EIVLS | \
00068                             ETH_MACVTR_ERIVLT | ETH_MACVTR_EDVLP | \
00069                             ETH_MACVTR_VTHM | ETH_MACVTR_EVLRXS | \
00070                             ETH_MACVTR_EVLS | ETH_MACVTR_DOVLTC | \
00071                             ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL | \
00072                             ETH_MACVTR_VTIM | ETH_MACVTR_ETV)
00073
00074 #define ETH_MACTXVLAN_MASK (ETH_MACVIR_VLTI | ETH_MACVIR_CSVL | \
00075                             ETH_MACVIR_VLP | ETH_MACVIR_VLC)
00076 /**
00077   * @}
00078   */
00079
00080 /* Private macros ------------------------------------------------------------*/
00081 /* Private function prototypes -----------------------------------------------*/
00082 /* Exported functions ---------------------------------------------------------*/
00083 /** @defgroup ETHEx_Exported_Functions ETH Extended Exported Functions
00084   * @{
00085   */
00086
00087 /** @defgroup ETHEx_Exported_Functions_Group1 Extended features functions
00088   * @brief    Extended features functions
00089  *
00090 @verbatim
00091  ===============================================================================
00092                       ##### Extended features functions #####
00093  ===============================================================================
00094     [..] This section provides functions allowing to:
00095       (+) Configure ARP offload module
00096       (+) Configure L3 and L4 filters
00097       (+) Configure Extended VLAN features
00098       (+) Configure Energy Efficient Ethernet module
00099
00100 @endverbatim
00101   * @{
00102   */
00103
00104 /**
00105   * @brief  Enables ARP Offload.
00106   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00107   *         the configuration information for ETHERNET module
00108   * @retval None
00109   */
00110 void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth)
00111 {
00112   SET_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
00113 }
00114
00115 /**
00116   * @brief  Disables ARP Offload.
00117   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00118   *         the configuration information for ETHERNET module
00119   * @retval None
00120   */
00121 void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth)
00122 {
00123   CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
00124 }
00125
00126 /**
00127   * @brief  Set the ARP Match IP address
00128   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00129   *         the configuration information for ETHERNET module
00130   *  @param IpAddress: IP Address to be matched for incoming ARP requests
00131   * @retval None
00132   */
00133 void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress)
00134 {
00135   WRITE_REG(heth->Instance->MACARPAR, IpAddress);
00136 }
00137
00138 /**
00139   * @brief  Configures the L4 Filter, this function allow to:
00140   *         set the layer 4 protocol to be matched (TCP or UDP)
00141   *         enable/disable L4 source/destination port perfect/inverse match.
00142   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00143   *         the configuration information for ETHERNET module
00144   * @param  Filter: L4 filter to configured, this parameter must be one of the following
00145   *           ETH_L4_FILTER_0
00146   *           ETH_L4_FILTER_1
00147   * @param  pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure
00148   *         that contains L4 filter configuration.
00149   * @retval HAL status
00150   */
00151 HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter , ETH_L4FilterConfigTypeDef *pL4FilterConfig)
00152 {
00153   uint32_t l4filteraddr;
00154   uint32_t l4filterval = 0;
00155
00156   if(pL4FilterConfig == NULL)
00157   {
00158     return HAL_ERROR;
00159   }
00160
00161   l4filteraddr = (uint32_t)(&(heth->Instance->MACL3L4C0R) + Filter);
00162
00163   l4filterval = (pL4FilterConfig->Protocol |
00164              pL4FilterConfig->SrcPortFilterMatch |
00165              pL4FilterConfig->DestPortFilterMatch);
00166
00167   /* Write configuration to (MACL3L4C0R + filter )register */
00168   MODIFY_REG((*(__IO uint32_t *)l4filteraddr), ETH_MACL4CR_MASK ,l4filterval);
00169
00170   /* Get address of  (MACL4A0R + filter) register */
00171   l4filteraddr = (uint32_t)(&(heth->Instance->MACL4A0R) + Filter);
00172
00173   l4filterval = (pL4FilterConfig->SourcePort |
00174              (pL4FilterConfig->DestinationPort << 16));
00175
00176   /* Write configuration to (MACL4A0R + filter )register */
00177   MODIFY_REG((*(__IO uint32_t *)l4filteraddr), (ETH_MACL4AR_L4DP | ETH_MACL4AR_L4SP) , l4filterval);
00178
00179   /* Enable L4 filter */
00180   SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
00181
00182   return HAL_OK;
00183 }
00184
00185 /**
00186   * @brief  Configures the L4 Filter, this function allow to:
00187   *         set the layer 4 protocol to be matched (TCP or UDP)
00188   *         enable/disable L4 source/destination port perfect/inverse match.
00189   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00190   *         the configuration information for ETHERNET module
00191   * @param  Filter: L4 filter to configured, this parameter must be one of the following
00192   *           ETH_L4_FILTER_0
00193   *           ETH_L4_FILTER_1
00194   * @param  pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure
00195   *         that contains L4 filter configuration.
00196   * @retval HAL status
00197   */
00198 HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig)
00199 {
00200   uint32_t l4filterval = *((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
00201
00202   if(pL4FilterConfig == NULL)
00203   {
00204     return HAL_ERROR;
00205   }
00206
00207   /* Get configuration to (MACL3L4C0R + filter )register */
00208   pL4FilterConfig->Protocol = READ_BIT(l4filterval, ETH_MACL3L4CR_L4PEN);
00209   pL4FilterConfig->DestPortFilterMatch = READ_BIT(l4filterval, (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
00210   pL4FilterConfig->SrcPortFilterMatch = READ_BIT(l4filterval, (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
00211
00212   /* Get address of  (MACL4A0R + filter) register */
00213   l4filterval = *((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter));
00214
00215   /* Get configuration to (MACL3L4C0R + filter )register */
00216   pL4FilterConfig->DestinationPort = (READ_BIT(l4filterval, ETH_MACL4AR_L4DP) >> 16);
00217   pL4FilterConfig->SourcePort = READ_BIT(l4filterval, ETH_MACL4AR_L4SP);
00218
00219   return HAL_OK;
00220 }
00221
00222 /**
00223   * @brief  Configures the L3 Filter, this function allow to:
00224   *         set the layer 3 protocol to be matched (IPv4 or IPv6)
00225   *         enable/disable L3 source/destination port perfect/inverse match.
00226   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00227   *         the configuration information for ETHERNET module
00228   * @param  Filter: L3 filter to configured, this parameter must be one of the following
00229   *           ETH_L3_FILTER_0
00230   *           ETH_L3_FILTER_1
00231   * @param  pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure
00232   *         that contains L3 filter configuration.
00233   * @retval HAL status
00234   */
00235 HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
00236 {
00237   __IO uint32_t *l3filteraddr;
00238   uint32_t l3filterval = 0;
00239
00240   if(pL3FilterConfig == NULL)
00241   {
00242     return HAL_ERROR;
00243   }
00244
00245   l3filteraddr = (__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter);
00246
00247   l3filterval = (pL3FilterConfig->Protocol |
00248                  pL3FilterConfig->SrcAddrFilterMatch |
00249                    pL3FilterConfig->DestAddrFilterMatch |
00250                      (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
00251                        (pL3FilterConfig->DestAddrHigherBitsMatch << 11));
00252
00253   /* Write configuration to (MACL3L4C0R + filter )register */
00254   MODIFY_REG(*l3filteraddr, ETH_MACL3CR_MASK, l3filterval);
00255
00256   /* Check if IPv6 protocol is selected */
00257   if(pL3FilterConfig->Protocol)
00258   {
00259     /* Set the IPv6 address match */
00260     /* Set Bits[31:0] of 128-bit IP addr */
00261     *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip6Addr[0];
00262     /* Set Bits[63:32] of 128-bit IP addr */
00263     *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip6Addr[1];
00264     /* update Bits[95:64] of 128-bit IP addr */
00265     *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter)) = pL3FilterConfig->Ip6Addr[2];
00266     /* update Bits[127:96] of 128-bit IP addr */
00267     *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter)) = pL3FilterConfig->Ip6Addr[3];
00268   }
00269   else /* IPv4 protocol is selected */
00270   {
00271     /* Set the IPv4 source address match */
00272     *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip4SrcAddr;
00273     /* Set the IPv4 destination address match */
00274     *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip4DestAddr;
00275   }
00276
00277   return HAL_OK;
00278 }
00279
00280 /**
00281   * @brief  Configures the L3 Filter, this function allow to:
00282   *         set the layer 3 protocol to be matched (IPv4 or IPv6)
00283   *         enable/disable L3 source/destination port perfect/inverse match.
00284   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00285   *         the configuration information for ETHERNET module
00286   * @param  Filter: L3 filter to configured, this parameter must be one of the following
00287   *           ETH_L3_FILTER_0
00288   *           ETH_L3_FILTER_1
00289   * @param  pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure
00290   *         that will contain the L3 filter configuration.
00291   * @retval HAL status
00292   */
00293 HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
00294 {
00295   uint32_t l3filterval = *((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
00296
00297   if(pL3FilterConfig == NULL)
00298   {
00299     return HAL_ERROR;
00300   }
00301
00302   pL3FilterConfig->Protocol = READ_BIT(l3filterval, ETH_MACL3L4CR_L3PEN);
00303   pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(l3filterval, (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM));
00304   pL3FilterConfig->DestAddrFilterMatch = READ_BIT(l3filterval, (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM));
00305   pL3FilterConfig->SrcAddrHigherBitsMatch = (READ_BIT(l3filterval, ETH_MACL3L4CR_L3HSBM) >> 6);
00306   pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(l3filterval, ETH_MACL3L4CR_L3HDBM) >> 11);
00307
00308   if(pL3FilterConfig->Protocol)
00309   {
00310     pL3FilterConfig->Ip6Addr[0] = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
00311     pL3FilterConfig->Ip6Addr[1] = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
00312     pL3FilterConfig->Ip6Addr[2] = *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter));
00313     pL3FilterConfig->Ip6Addr[3] = *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter));
00314   }
00315   else
00316   {
00317     pL3FilterConfig->Ip4SrcAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
00318     pL3FilterConfig->Ip4DestAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
00319   }
00320
00321   return HAL_OK;
00322 }
00323
00324 /**
00325   * @brief  Enables L3 and L4 filtering process.
00326   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00327   *         the configuration information for ETHERNET module
00328   * @retval None.
00329   */
00330 void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth)
00331 {
00332   /* Enable L3/L4 filter */
00333   SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
00334 }
00335
00336 /**
00337   * @brief  Disables L3 and L4 filtering process.
00338   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00339   *         the configuration information for ETHERNET module
00340   * @retval None.
00341   */
00342 void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth)
00343 {
00344   /* Disable L3/L4 filter */
00345   CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
00346 }
00347
00348 /**
00349   * @brief  Get the VLAN Configuration for Receive Packets.
00350   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00351   *         the configuration information for ETHERNET module
00352   * @param  pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure
00353   *         that will contain the VLAN filter configuration.
00354   * @retval HAL status
00355   */
00356 HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
00357 {
00358   if(pVlanConfig == NULL)
00359   {
00360     return HAL_ERROR;
00361   }
00362
00363   pVlanConfig->InnerVLANTagInStatus = (FunctionalState)(READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLRXS) >> 31);
00364   pVlanConfig->StripInnerVLANTag  = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLS);
00365   pVlanConfig->InnerVLANTag = (FunctionalState)(READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_ERIVLT) >> 27);
00366   pVlanConfig->DoubleVLANProcessing = (FunctionalState)(READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP) >> 26);
00367   pVlanConfig->VLANTagHashTableMatch = (FunctionalState)(READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTHM) >> 25);
00368   pVlanConfig->VLANTagInStatus = (FunctionalState)(READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLRXS) >> 24);
00369   pVlanConfig->StripVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLS);
00370   pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR, (ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL));
00371   pVlanConfig->VLANTagInverceMatch = (FunctionalState)(READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTIM) >> 17);
00372
00373   return HAL_OK;
00374 }
00375
00376 /**
00377   * @brief  Set the VLAN Configuration for Receive Packets.
00378   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00379   *         the configuration information for ETHERNET module
00380   * @param  pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure
00381   *         that contains VLAN filter configuration.
00382   * @retval HAL status
00383   */
00384 HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
00385 {
00386   uint32_t rxvlanval = 0;
00387
00388   if(pVlanConfig == NULL)
00389   {
00390     return HAL_ERROR;
00391   }
00392
00393   rxvlanval = ((uint32_t)(pVlanConfig->InnerVLANTagInStatus << 31) |
00394                pVlanConfig->StripInnerVLANTag |
00395                  (uint32_t)(pVlanConfig->InnerVLANTag << 27) |
00396                    (uint32_t)(pVlanConfig->DoubleVLANProcessing << 26) |
00397                      (uint32_t)(pVlanConfig->VLANTagHashTableMatch << 25) |
00398                        (uint32_t)(pVlanConfig->VLANTagInStatus << 24) |
00399                          pVlanConfig->StripVLANTag |
00400                            pVlanConfig->VLANTypeCheck |
00401                              (uint32_t)(pVlanConfig->VLANTagInverceMatch << 17));
00402
00403   /* Write config to MACVTR */
00404   MODIFY_REG(heth->Instance->MACVTR, ETH_MACRXVLAN_MASK, rxvlanval);
00405
00406   return HAL_OK;
00407 }
00408
00409 /**
00410   * @brief  Set the VLAN Hash Table
00411   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00412   *         the configuration information for ETHERNET module
00413   * @param  VLANHashTable: VLAN hash table 16 bit value
00414   * @retval None
00415   */
00416 void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable)
00417 {
00418   MODIFY_REG(heth->Instance->MACVHTR, ETH_MACVHTR_VLHT, VLANHashTable);
00419 }
00420
00421 /**
00422   * @brief  Get the VLAN Configuration for Transmit Packets.
00423   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00424   *         the configuration information for ETHERNET module
00425   * @param  VLANTag: Selects the vlan tag, this parameter must be one of the following
00426   *                 ETH_OUTER_TX_VLANTAG
00427   *                 ETH_INNER_TX_VLANTAG
00428   * @param  pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure
00429   *         that will contain the Tx VLAN filter configuration.
00430   * @retval HAL Status.
00431   */
00432 HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig)
00433 {
00434   uint32_t vlanreg;
00435
00436   if (pVlanConfig == NULL)
00437   {
00438     return HAL_ERROR;
00439   }
00440
00441   if(VLANTag == ETH_INNER_TX_VLANTAG)
00442   {
00443     vlanreg = heth->Instance->MACIVIR;
00444   }
00445   else
00446   {
00447     vlanreg = heth->Instance->MACVIR;
00448   }
00449
00450
00451   pVlanConfig->SourceTxDesc = (FunctionalState)(READ_BIT(vlanreg, ETH_MACVIR_VLTI) >> 20);
00452   pVlanConfig->SVLANType = (FunctionalState)(READ_BIT(vlanreg, ETH_MACVIR_CSVL) >> 19);
00453   pVlanConfig->VLANTagControl = READ_BIT(vlanreg, (ETH_MACVIR_VLP | ETH_MACVIR_VLC));
00454
00455   return HAL_OK;;
00456 }
00457
00458 /**
00459   * @brief  Set the VLAN Configuration for Transmit Packets.
00460   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00461   *         the configuration information for ETHERNET module
00462   * @param  VLANTag: Selects the vlan tag, this parameter must be one of the following
00463   *                 ETH_OUTER_TX_VLANTAG
00464   *                 ETH_INNER_TX_VLANTAG
00465   * @param  pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure
00466   *         that contains Tx VLAN filter configuration.
00467   * @retval HAL Status
00468   */
00469 HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig)
00470 {
00471   uint32_t vlanconfigval = 0;
00472   uint32_t vlanreg;
00473
00474   if(VLANTag == ETH_INNER_TX_VLANTAG)
00475   {
00476     vlanreg = (uint32_t)&(heth->Instance->MACIVIR);
00477     /* Enable Double VLAN processing */
00478     SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
00479   }
00480   else
00481   {
00482     vlanreg = (uint32_t)&(heth->Instance->MACVIR);
00483   }
00484
00485   vlanconfigval = ((uint32_t)(pVlanConfig->SourceTxDesc << 20) |
00486                    (uint32_t)(pVlanConfig->SVLANType << 19) |
00487                      pVlanConfig->VLANTagControl);
00488
00489   MODIFY_REG(*((uint32_t *)vlanreg), ETH_MACTXVLAN_MASK, vlanconfigval);
00490
00491   return HAL_OK;
00492 }
00493
00494 /**
00495   * @brief  Set the VLAN Tag Identifier for Transmit Packets.
00496   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00497   *         the configuration information for ETHERNET module
00498   * @param  VLANTag: Selects the vlan tag, this parameter must be one of the following
00499   *                 ETH_OUTER_TX_VLANTAG
00500   *                 ETH_INNER_TX_VLANTAG
00501   * @param  VLANIdentifier: VLAN Identifier 16 bit value
00502   * @retval None
00503   */
00504 void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier)
00505 {
00506   uint32_t vlanreg;
00507
00508   if(VLANTag == ETH_INNER_TX_VLANTAG)
00509   {
00510     vlanreg = (uint32_t)&(heth->Instance->MACIVIR);
00511   }
00512   else
00513   {
00514     vlanreg = (uint32_t)&(heth->Instance->MACVIR);
00515   }
00516
00517   MODIFY_REG(*((uint32_t *)vlanreg), ETH_MACVIR_VLT, VLANIdentifier);
00518 }
00519
00520 /**
00521   * @brief  Enables the VLAN Tag Filtering process.
00522   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00523   *         the configuration information for ETHERNET module
00524   * @retval None.
00525   */
00526 void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth)
00527 {
00528   /* Enable VLAN processing */
00529   SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE);
00530 }
00531
00532 /**
00533   * @brief  Disables the VLAN Tag Filtering process.
00534   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00535   *         the configuration information for ETHERNET module
00536   * @retval None.
00537   */
00538 void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth)
00539 {
00540   /* Disable VLAN processing */
00541   CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE);
00542 }
00543
00544 /**
00545   * @brief  Enters the Low Power Idle (LPI) mode
00546   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00547   *         the configuration information for ETHERNET module
00548   * @param  TxAutomate: Enable/Disbale automate enter/exit LPI mode.
00549   * @param  TxClockStop: Enable/Disbale Tx clock stop in LPI mode.
00550   * @retval None
00551   */
00552 void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop)
00553 {
00554   uint32_t lpiconfig;
00555
00556   lpiconfig = (((uint32_t)TxAutomate << 19) |
00557                ((uint32_t)TxClockStop << 21) |
00558                  ETH_MACLCSR_LPIEN);
00559
00560   /* Enable LPI Interrupts */
00561   __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_LPIIE);
00562
00563   /* Write to LPI Control register: Enter low power mode */
00564   MODIFY_REG(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE), lpiconfig);
00565 }
00566
00567 /**
00568   * @brief  Exits the Low Power Idle (LPI) mode.
00569   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00570   *         the configuration information for ETHERNET module
00571   * @retval None
00572   */
00573 void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth)
00574 {
00575   /* Clear the LPI Config and exit low power mode */
00576   CLEAR_BIT(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE));
00577
00578   /* Enable LPI Interrupts */
00579   __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_LPIIE);
00580 }
00581
00582
00583 /**
00584   * @brief  Returns the ETH MAC LPI event
00585   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00586   *         the configuration information for ETHERNET module
00587   * @retval ETH MAC WakeUp event
00588   */
00589 uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth)
00590 {
00591   return heth->MACLPIEvent;
00592 }
00593
00594 /**
00595   * @}
00596   */
00597
00598 /**
00599   * @}
00600   */
00601
00602 #endif /* HAL_ETH_MODULE_ENABLED */
00603 /**
00604   * @}
00605   */
00606
00607 /**
00608   * @}
00609   */
00610
00611 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_eth_ex.h Source File

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stm32h7xx_hal_eth_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_eth_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of ETH HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_ETH_EX_H
00040 #define __STM32H7xx_HAL_ETH_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup ETHEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup ETHEx_Exported_Types ETHEx Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  ETH RX VLAN structure definition
00064   */
00065 typedef struct{
00066   FunctionalState InnerVLANTagInStatus;      /*!< Enables or disables Inner VLAN Tag in Rx Status  */
00067
00068   uint32_t StripInnerVLANTag;                /*!< Sets the Inner VLAN Tag Stripping on Receive
00069                                                   This parameter can be a value of @ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */
00070
00071   FunctionalState InnerVLANTag;              /*!< Enables or disables Inner VLAN Tag */
00072
00073   FunctionalState DoubleVLANProcessing;      /*!< Enable or Disable double VLAN processing */
00074
00075   FunctionalState VLANTagHashTableMatch;     /*!< Enable or Disable VLAN Tag Hash Table Match */
00076
00077   FunctionalState VLANTagInStatus;           /*!< Enable or Disable VLAN Tag in Rx status */
00078
00079   uint32_t StripVLANTag;                     /*!< Set the VLAN Tag Stripping on Receive
00080                                                   This parameter can be a value of @ref ETHEx_Rx_VLAN_Tag_Stripping */
00081
00082   uint32_t VLANTypeCheck;                    /*!< Enable or Disable VLAN Type Check
00083                                                   This parameter can be a value of @ref ETHEx_VLAN_Type_Check */
00084
00085   FunctionalState VLANTagInverceMatch;       /*!< Enable or disable VLAN Tag Inverse Match */
00086 }ETH_RxVLANConfigTypeDef;
00087 /**
00088   *
00089   */
00090
00091 /**
00092   * @brief  ETH TX VLAN structure definition
00093   */
00094 typedef struct{
00095   FunctionalState SourceTxDesc;   /*!< Enable or Disable VLAN tag source from DMA tx descriptors */
00096
00097   FunctionalState SVLANType;      /*!< Enable or Disable insertion of SVLAN type */
00098
00099   uint32_t VLANTagControl;        /*!< Sets the VLAN tag control in tx packets
00100                                       This parameter can be a value of @ref ETHEx_VLAN_Tag_Control */
00101 }ETH_TxVLANConfigTypeDef;
00102 /**
00103   *
00104   */
00105
00106 /**
00107   * @brief  ETH L3 filter structure definition
00108   */
00109 typedef struct{
00110   uint32_t Protocol;                /*!< Sets the L3 filter protocol to IPv4 or IPv6
00111                                          This parameter can be a value of @ref ETHEx_L3_Protocol */
00112
00113   uint32_t SrcAddrFilterMatch;      /*!< Sets the L3 filter source address match
00114                                          This parameter can be a value of @ref ETHEx_L3_Source_Match */
00115
00116   uint32_t DestAddrFilterMatch;     /*!< Sets the L3 filter destination address match
00117                                          This parameter can be a value of @ref ETHEx_L3_Destination_Match */
00118
00119   uint32_t SrcAddrHigherBitsMatch;  /*!< Sets the L3 filter source address higher bits match
00120                                          This parameter can be a value from 0 to 31 */
00121
00122   uint32_t DestAddrHigherBitsMatch; /*!< Sets the L3 filter destination address higher bits match
00123                                          This parameter can be a value from 0 to 31 */
00124
00125   uint32_t Ip4SrcAddr;              /*!< Sets the L3 filter IPv4 source address if IPv4 protocol is used
00126                                          This parameter can be a value from 0x0 to 0xFFFFFFFF */
00127
00128   uint32_t Ip4DestAddr;             /*!< Sets the L3 filter IPv4 destination  address if IPv4 protocol is used
00129                                          This parameter can be a value from 0 to 0xFFFFFFFF  */
00130
00131   uint32_t Ip6Addr[4];                 /*!< Sets the L3 filter IPv6 address if IPv6 protocol is used
00132                                           This parameter must be a table of 4 words (4* 32 bits) */
00133 }ETH_L3FilterConfigTypeDef;
00134 /**
00135   *
00136   */
00137
00138 /**
00139   * @brief  ETH L4 filter structure definition
00140   */
00141 typedef struct{
00142   uint32_t Protocol;               /*!< Sets the L4 filter protocol to TCP or UDP
00143                                         This parameter can be a value of @ref ETHEx_L4_Protocol */
00144
00145   uint32_t SrcPortFilterMatch;     /*!< Sets the L4 filter source port match
00146                                         This parameter can be a value of @ref ETHEx_L4_Source_Match */
00147
00148   uint32_t DestPortFilterMatch;    /*!< Sets the L4 filter destination port match
00149                                         This parameter can be a value of @ref ETHEx_L4_Destination_Match */
00150
00151   uint32_t SourcePort;             /*!< Sets the L4 filter source port
00152                                         This parameter must be a value from 0x0 to 0xFFFF */
00153
00154   uint32_t DestinationPort;        /*!< Sets the L4 filter destination port
00155                                         This parameter must be a value from 0x0 to 0xFFFF */
00156 }ETH_L4FilterConfigTypeDef;
00157 /**
00158   *
00159   */
00160
00161 /**
00162   * @}
00163   */
00164
00165 /* Exported constants --------------------------------------------------------*/
00166 /** @defgroup ETHEx_Exported_Constants ETHEx Exported Constants
00167   * @{
00168   */
00169
00170 /** @defgroup ETHEx_LPI_Event ETHEx LPI Event
00171   * @{
00172   */
00173 #define ETH_TX_LPI_ENTRY    ETH_MACLCSR_TLPIEN
00174 #define ETH_TX_LPI_EXIT     ETH_MACLCSR_TLPIEX
00175 #define ETH_RX_LPI_ENTRY    ETH_MACLCSR_RLPIEN
00176 #define ETH_RX_LPI_EXIT     ETH_MACLCSR_RLPIEX
00177 /**
00178   * @}
00179   */
00180
00181 /** @defgroup ETHEx_L3_Filter ETHEx L3 Filter
00182   * @{
00183   */
00184 #define ETH_L3_FILTER_0                 ((uint32_t)0x00000000)
00185 #define ETH_L3_FILTER_1                 ((uint32_t)0x0000000C)
00186 /**
00187   * @}
00188   */
00189
00190 /** @defgroup ETHEx_L4_Filter ETHEx L4 Filter
00191   * @{
00192   */
00193 #define ETH_L4_FILTER_0                 ((uint32_t)0x00000000)
00194 #define ETH_L4_FILTER_1                 ((uint32_t)0x0000000C)
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup ETHEx_L3_Protocol ETHEx L3 Protocol
00200   * @{
00201   */
00202 #define ETH_L3_IPV6_MATCH                       ETH_MACL3L4CR_L3PEN
00203 #define ETH_L3_IPV4_MATCH                       ((uint32_t)0x00000000)
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup ETHEx_L3_Source_Match ETHEx L3 Source Match
00209   * @{
00210   */
00211 #define ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE    ETH_MACL3L4CR_L3SAM
00212 #define ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE    (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM)
00213 #define ETH_L3_SRC_ADDR_MATCH_DISABLE           ((uint32_t)0x00000000)
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup ETHEx_L3_Destination_Match ETHEx L3 Destination Match
00219   * @{
00220   */
00221 #define ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE   ETH_MACL3L4CR_L3DAM
00222 #define ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE   (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM)
00223 #define ETH_L3_DEST_ADDR_MATCH_DISABLE          ((uint32_t)0x00000000)
00224 /**
00225   * @}
00226   */
00227
00228 /** @defgroup ETHEx_L4_Protocol ETHEx L4 Protocol
00229   * @{
00230   */
00231 #define ETH_L4_UDP_MATCH                        ETH_MACL3L4CR_L4PEN
00232 #define ETH_L4_TCP_MATCH                        ((uint32_t)0x00000000)
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup ETHEx_L4_Source_Match ETHEx L4 Source Match
00238   * @{
00239   */
00240 #define ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE    ETH_MACL3L4CR_L4SPM
00241 #define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE    (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM)
00242 #define ETH_L4_SRC_PORT_MATCH_DISABLE           ((uint32_t)0x00000000)
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup ETHEx_L4_Destination_Match ETHEx L4 Destination Match
00248   * @{
00249   */
00250 #define ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE   ETH_MACL3L4CR_L4DPM
00251 #define ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE   (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)
00252 #define ETH_L4_DEST_PORT_MATCH_DISABLE          ((uint32_t)0x00000000)
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup ETHEx_Rx_Inner_VLAN_Tag_Stripping ETHEx Rx Inner VLAN Tag Stripping
00258   * @{
00259   */
00260 #define ETH_INNERVLANTAGRXSTRIPPING_NONE      ETH_MACVTR_EIVLS_DONOTSTRIP
00261 #define ETH_INNERVLANTAGRXSTRIPPING_IFPASS    ETH_MACVTR_EIVLS_STRIPIFPASS
00262 #define ETH_INNERVLANTAGRXSTRIPPING_IFFAILS   ETH_MACVTR_EIVLS_STRIPIFFAILS
00263 #define ETH_INNERVLANTAGRXSTRIPPING_ALWAYS    ETH_MACVTR_EIVLS_ALWAYSSTRIP
00264 /**
00265   * @}
00266   */
00267
00268 /** @defgroup ETHEx_Rx_VLAN_Tag_Stripping ETHEx Rx VLAN Tag Stripping
00269   * @{
00270   */
00271 #define ETH_VLANTAGRXSTRIPPING_NONE      ETH_MACVTR_EVLS_DONOTSTRIP
00272 #define ETH_VLANTAGRXSTRIPPING_IFPASS    ETH_MACVTR_EVLS_STRIPIFPASS
00273 #define ETH_VLANTAGRXSTRIPPING_IFFAILS   ETH_MACVTR_EVLS_STRIPIFFAILS
00274 #define ETH_VLANTAGRXSTRIPPING_ALWAYS    ETH_MACVTR_EVLS_ALWAYSSTRIP
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup ETHEx_VLAN_Type_Check ETHEx VLAN Type Check
00280   * @{
00281   */
00282 #define ETH_VLANTYPECHECK_DISABLE    ETH_MACVTR_DOVLTC
00283 #define ETH_VLANTYPECHECK_SVLAN      (ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL)
00284 #define ETH_VLANTYPECHECK_CVLAN      ((uint32_t)0x00000000)
00285 /**
00286   * @}
00287   */
00288
00289 /** @defgroup ETHEx_VLAN_Tag_Control ETHEx_VLAN_Tag_Control
00290   * @{
00291   */
00292 #define ETH_VLANTAGCONTROL_NONE       (ETH_MACVIR_VLP | ETH_MACVIR_VLC_NOVLANTAG)
00293 #define ETH_VLANTAGCONTROL_DELETE     (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGDELETE)
00294 #define ETH_VLANTAGCONTROL_INSERT     (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGINSERT)
00295 #define ETH_VLANTAGCONTROL_REPLACE    (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGREPLACE)
00296 /**
00297   * @}
00298   */
00299
00300 /** @defgroup ETHEx_Tx_VLAN_Tag ETHEx Tx VLAN Tag
00301   * @{
00302   */
00303 #define ETH_INNER_TX_VLANTAG    ((uint32_t)0x00000001U)
00304 #define ETH_OUTER_TX_VLANTAG    ((uint32_t)0x00000000U)
00305 /**
00306   * @}
00307   */
00308
00309 /**
00310   * @}
00311   */
00312
00313 /* Exported functions --------------------------------------------------------*/
00314 /** @addtogroup ETHEx_Exported_Functions
00315   * @{
00316   */
00317
00318 /** @addtogroup ETHEx_Exported_Functions_Group1
00319   * @{
00320   */
00321 /* MAC ARP Offloading APIs  ***************************************************/
00322 void              HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth);
00323 void              HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth);
00324 void              HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress);
00325
00326 /* MAC L3 L4 Filtering APIs ***************************************************/
00327 void              HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth);
00328 void              HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth);
00329 HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);
00330 HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);
00331 HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);
00332 HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);
00333
00334 /* MAC VLAN Processing APIs    ************************************************/
00335 void              HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth);
00336 void              HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth);
00337 HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
00338 HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
00339 void              HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable);
00340 HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);
00341 HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);
00342 void              HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier);
00343
00344 /* Energy Efficient Ethernet APIs *********************************************/
00345 void              HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop);
00346 void              HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth);
00347 uint32_t          HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth);
00348
00349 /**
00350   * @}
00351   */
00352
00353 /**
00354   * @}
00355   */
00356
00357 /**
00358   * @}
00359   */
00360
00361 /**
00362   * @}
00363   */
00364
00365 #ifdef __cplusplus
00366 }
00367 #endif
00368
00369 #endif /* __STM32H7xx_HAL_ETH_EX_H */
00370
00371 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_fdcan.c Source File

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stm32h7xx_hal_fdcan.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_fdcan.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   FDCAN HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Flexible DataRate Controller Area Network
00010   *          (FDCAN) peripheral:
00011   *           + Initialization and de-initialization functions
00012   *           + IO operation functions
00013   *           + Peripheral Configuration and Control functions
00014   *           + Peripheral State and Error functions
00015   *
00016   @verbatim
00017   ==============================================================================
00018                         ##### How to use this driver #####
00019   ==============================================================================
00020     [..]
00021       (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function.
00022
00023       (#) If needed , configure the reception filters and optional features using
00024           the following configuration functions:
00025             (++) HAL_FDCAN_ConfigClockCalibration
00026             (++) HAL_FDCAN_ConfigFilter
00027             (++) HAL_FDCAN_ConfigGlobalFilter
00028             (++) HAL_FDCAN_ConfigExtendedIdMask
00029             (++) HAL_FDCAN_ConfigRxFifoOverwrite
00030             (++) HAL_FDCAN_ConfigFifoWatermark
00031             (++) HAL_FDCAN_ConfigRamWatchdog
00032             (++) HAL_FDCAN_ConfigTimestampCounter
00033             (++) HAL_FDCAN_EnableTimestampCounter
00034             (++) HAL_FDCAN_DisableTimestampCounter
00035             (++) HAL_FDCAN_ConfigTimeoutCounter
00036             (++) HAL_FDCAN_EnableTimeoutCounter
00037             (++) HAL_FDCAN_DisableTimeoutCounter
00038             (++) HAL_FDCAN_ConfigTxDelayCompensation
00039             (++) HAL_FDCAN_EnableTxDelayCompensation
00040             (++) HAL_FDCAN_DisableTxDelayCompensation
00041             (++) HAL_FDCAN_TT_ConfigOperation
00042             (++) HAL_FDCAN_TT_ConfigReferenceMessage
00043             (++) HAL_FDCAN_TT_ConfigTrigger
00044
00045       (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level
00046           the node is active on the bus: it can send and receive messages.
00047
00048       (#) The following Tx control functions can only be called when the FDCAN
00049           module is started:
00050             (++) HAL_FDCAN_AddMessageToTxFifoQ
00051             (++) HAL_FDCAN_EnableTxBufferRequest
00052             (++) HAL_FDCAN_AbortTxRequest
00053
00054       (#) When a message is received into the FDCAN message RAM, it can be
00055           retrieved using the HAL_FDCAN_GetRxMessage function.
00056
00057       (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering
00058           it to initialization mode and re-enabling access to configuration
00059           registers through the configuration functions listed here above.
00060
00061       (#) All other control functions can be called any time after initialization
00062           phase, no matter if the FDCAN module is started or stoped.
00063
00064       *** Polling mode operation ***
00065       ==============================
00066
00067     [..]
00068         (#) Reception and transmission states can be monitored via the following
00069             functions:
00070               (++) HAL_FDCAN_IsRxBufferMessageAvailable
00071               (++) HAL_FDCAN_IsTxBufferMessagePending
00072               (++) HAL_FDCAN_GetRxFifoFillLevel
00073               (++) HAL_FDCAN_GetTxFifoFreeLevel
00074
00075       *** Interrupt mode operation ***
00076       ================================
00077       [..]
00078         (#) There are two interrupt lines: line 0 and 1.
00079             By default, all interrupts are assigned to line 0. Interrupt lines
00080             can be configured using HAL_FDCAN_ConfigInterruptLines function.
00081
00082         (#) Notifications are activated using HAL_FDCAN_ActivateNotification
00083             function. Then, the process can be controlled through one of the
00084             available user callbacks: HAL_FDCAN_xxxCallback.
00085
00086   @endverbatim
00087
00088   ******************************************************************************
00089   * @attention
00090   *
00091   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00092   *
00093   * Redistribution and use in source and binary forms, with or without modification,
00094   * are permitted provided that the following conditions are met:
00095   *   1. Redistributions of source code must retain the above copyright notice,
00096   *      this list of conditions and the following disclaimer.
00097   *   2. Redistributions in binary form must reproduce the above copyright notice,
00098   *      this list of conditions and the following disclaimer in the documentation
00099   *      and/or other materials provided with the distribution.
00100   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00101   *      may be used to endorse or promote products derived from this software
00102   *      without specific prior written permission.
00103   *
00104   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00105   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00106   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00107   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00108   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00109   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00110   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00111   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00112   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00113   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00114   *
00115   ******************************************************************************
00116   */
00117
00118 /* Includes ------------------------------------------------------------------*/
00119 #include "stm32h7xx_hal.h"
00120
00121 /** @addtogroup STM32H7xx_HAL_Driver
00122   * @{
00123   */
00124
00125 /** @defgroup FDCAN FDCAN
00126   * @brief FDCAN HAL module driver
00127   * @{
00128   */
00129
00130 #ifdef HAL_FDCAN_MODULE_ENABLED
00131
00132 /* Private typedef -----------------------------------------------------------*/
00133 /* Private define ------------------------------------------------------------*/
00134 /** @addtogroup FDCAN_Private_Constants
00135   * @{
00136   */
00137 #define FDCAN_TIMEOUT_VALUE 10
00138
00139 #define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFW | FDCAN_IR_TEFN)
00140 #define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0W | FDCAN_IR_RF0N)
00141 #define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1W | FDCAN_IR_RF1N)
00142 #define FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO | \
00143                           FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
00144 #define FDCAN_TT_SCHEDULE_SYNC_MASK (FDCAN_TTIR_SBC | FDCAN_TTIR_SMC | FDCAN_TTIR_CSM | FDCAN_TTIR_SOG)
00145 #define FDCAN_TT_TIME_MARK_MASK (FDCAN_TTIR_RTMI | FDCAN_TTIR_TTMI)
00146 #define FDCAN_TT_GLOBAL_TIME_MASK (FDCAN_TTIR_GTW | FDCAN_TTIR_GTD)
00147 #define FDCAN_TT_DISTURBING_ERROR_MASK (FDCAN_TTIR_GTE | FDCAN_TTIR_TXU | FDCAN_TTIR_TXO | \
00148                                         FDCAN_TTIR_SE1 | FDCAN_TTIR_SE2 | FDCAN_TTIR_ELC)
00149 #define FDCAN_TT_FATAL_ERROR_MASK (FDCAN_TTIR_IWT | FDCAN_TTIR_WT | FDCAN_TTIR_AW | FDCAN_TTIR_CER)
00150
00151 #define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier         */
00152 #define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier         */
00153 #define FDCAN_ELEMENT_MASK_RTR   ((uint32_t)0x20000000U) /* Remote Transmission Request */
00154 #define FDCAN_ELEMENT_MASK_XTD   ((uint32_t)0x40000000U) /* Extended Identifier         */
00155 #define FDCAN_ELEMENT_MASK_ESI   ((uint32_t)0x80000000U) /* Error State Indicator       */
00156 #define FDCAN_ELEMENT_MASK_TS    ((uint32_t)0x0000FFFFU) /* Timestamp                   */
00157 #define FDCAN_ELEMENT_MASK_DLC   ((uint32_t)0x000F0000U) /* Data Length Code            */
00158 #define FDCAN_ELEMENT_MASK_BRS   ((uint32_t)0x00100000U) /* Bit Rate Switch             */
00159 #define FDCAN_ELEMENT_MASK_FDF   ((uint32_t)0x00200000U) /* FD Format                   */
00160 #define FDCAN_ELEMENT_MASK_EFC   ((uint32_t)0x00800000U) /* Event FIFO Control          */
00161 #define FDCAN_ELEMENT_MASK_MM    ((uint32_t)0xFF000000U) /* Message Marker              */
00162 #define FDCAN_ELEMENT_MASK_FIDX  ((uint32_t)0x7F000000U) /* Filter Index                */
00163 #define FDCAN_ELEMENT_MASK_ANMF  ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
00164 #define FDCAN_ELEMENT_MASK_ET    ((uint32_t)0x00C00000U) /* Event type                  */
00165
00166 /**
00167   * @}
00168   */
00169
00170 /* Private macro -------------------------------------------------------------*/
00171 /* Private variables ---------------------------------------------------------*/
00172 static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
00173 static const uint8_t CvtEltSize[] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7};
00174
00175 /* Private function prototypes -----------------------------------------------*/
00176 /** @addtogroup FDCAN_Private_Functions_Prototypes
00177   * @{
00178   */
00179 static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
00180 static HAL_StatusTypeDef FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
00181 /**
00182   * @}
00183   */
00184
00185 /* Exported functions --------------------------------------------------------*/
00186 /** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions
00187   * @{
00188   */
00189
00190 /** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions
00191  *  @brief    Initialization and Configuration functions
00192  *
00193 @verbatim
00194   ==============================================================================
00195               ##### Initialization and de-initialization functions #####
00196   ==============================================================================
00197     [..]  This section provides functions allowing to:
00198       (+) Initialize and configure the FDCAN.
00199       (+) De-initialize the FDCAN.
00200       (+) Enter FDCAN peripheral in power down mode.
00201       (+) Exit power down mode.
00202
00203 @endverbatim
00204   * @{
00205   */
00206
00207 /**
00208   * @brief  Initializes the FDCAN peripheral according to the specified
00209   *         parameters in the FDCAN_InitTypeDef structure.
00210   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
00211   *         the configuration information for the specified FDCAN.
00212   * @retval HAL status
00213   */
00214 HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef* hfdcan)
00215 {
00216   uint32_t tickstart = 0U;
00217
00218   /* Check FDCAN handle */
00219   if(hfdcan == NULL)
00220   {
00221      return HAL_ERROR;
00222   }
00223
00224   /* Check FDCAN instance */
00225   if(hfdcan->Instance == FDCAN1)
00226   {
00227     hfdcan->ttcan = (TTCAN_TypeDef *)((uint32_t)hfdcan->Instance + 0x100);
00228   }
00229
00230   /* Check function parameters */
00231   assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
00232   assert_param(IS_FDCAN_FRAME_FORMAT(hfdcan->Init.FrameFormat));
00233   assert_param(IS_FDCAN_MODE(hfdcan->Init.Mode));
00234   assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.AutoRetransmission));
00235   assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.TransmitPause));
00236   assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.ProtocolException));
00237   assert_param(IS_FDCAN_NOMINAL_PRESCALER(hfdcan->Init.NominalPrescaler));
00238   assert_param(IS_FDCAN_NOMINAL_SJW(hfdcan->Init.NominalSyncJumpWidth));
00239   assert_param(IS_FDCAN_NOMINAL_TSEG1(hfdcan->Init.NominalTimeSeg1));
00240   assert_param(IS_FDCAN_NOMINAL_TSEG2(hfdcan->Init.NominalTimeSeg2));
00241   if(hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
00242   {
00243     assert_param(IS_FDCAN_DATA_PRESCALER(hfdcan->Init.DataPrescaler));
00244     assert_param(IS_FDCAN_DATA_SJW(hfdcan->Init.DataSyncJumpWidth));
00245     assert_param(IS_FDCAN_DATA_TSEG1(hfdcan->Init.DataTimeSeg1));
00246     assert_param(IS_FDCAN_DATA_TSEG2(hfdcan->Init.DataTimeSeg2));
00247   }
00248   assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.StdFiltersNbr, 128));
00249   assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.ExtFiltersNbr, 64));
00250   assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo0ElmtsNbr, 64));
00251   if(hfdcan->Init.RxFifo0ElmtsNbr > 0)
00252   {
00253     assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo0ElmtSize));
00254   }
00255   assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo1ElmtsNbr, 64));
00256   if(hfdcan->Init.RxFifo1ElmtsNbr > 0)
00257   {
00258     assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo1ElmtSize));
00259   }
00260   assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxBuffersNbr, 64));
00261   if(hfdcan->Init.RxBuffersNbr > 0)
00262   {
00263     assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxBufferSize));
00264   }
00265   assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.TxEventsNbr, 32));
00266   assert_param(IS_FDCAN_MAX_VALUE((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr), 32));
00267   if(hfdcan->Init.TxFifoQueueElmtsNbr > 0)
00268   {
00269     assert_param(IS_FDCAN_TX_FIFO_QUEUE_MODE(hfdcan->Init.TxFifoQueueMode));
00270   }
00271   if((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0)
00272   {
00273     assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.TxElmtSize));
00274   }
00275
00276   if(hfdcan->State == HAL_FDCAN_STATE_RESET)
00277   {
00278     /* Allocate lock resource and initialize it */
00279     hfdcan->Lock = HAL_UNLOCKED;
00280
00281     /* Init the low level hardware */
00282     HAL_FDCAN_MspInit(hfdcan);
00283   }
00284
00285   /* Exit from Sleep mode */
00286   CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
00287
00288   /* Get tick */
00289   tickstart = HAL_GetTick();
00290
00291   /* Check Sleep mode acknowledge */
00292   while((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
00293   {
00294     if((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
00295     {
00296       /* Update error code */
00297       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
00298
00299       /* Change FDCAN state */
00300       hfdcan->State = HAL_FDCAN_STATE_ERROR;
00301
00302       return HAL_ERROR;
00303     }
00304   }
00305
00306   /* Request initialisation */
00307   SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
00308
00309   /* Get tick */
00310   tickstart = HAL_GetTick();
00311
00312   /* Wait until the INIT bit into CCCR register is set */
00313   while((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == RESET)
00314   {
00315     /* Check for the Timeout */
00316     if((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
00317     {
00318       /* Update error code */
00319       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
00320
00321       /* Change FDCAN state */
00322       hfdcan->State = HAL_FDCAN_STATE_ERROR;
00323
00324       return HAL_ERROR;
00325     }
00326   }
00327
00328   /* Enable configuration change */
00329   SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
00330
00331   /* Set the no automatic retransmission */
00332   if(hfdcan->Init.AutoRetransmission == ENABLE)
00333   {
00334     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
00335   }
00336   else
00337   {
00338     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
00339   }
00340
00341   /* Set the transmit pause feature */
00342   if(hfdcan->Init.TransmitPause == ENABLE)
00343   {
00344     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
00345   }
00346   else
00347   {
00348     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
00349   }
00350
00351   /* Set the Protocol Exception Handling */
00352   if(hfdcan->Init.ProtocolException == ENABLE)
00353   {
00354     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
00355   }
00356   else
00357   {
00358     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
00359   }
00360
00361   /* Set FDCAN Frame Format */
00362   MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat);
00363
00364   /* Set FDCAN Operating Mode:
00365                | Normal | Restricted |    Bus     | Internal | External
00366                |        | Operation  | Monitoring | LoopBack | LoopBack
00367      CCCR.TEST |   0    |     0      |     0      |    1     |    1
00368      CCCR.MON  |   0    |     0      |     1      |    0     |    1
00369      TEST.LBCK |   0    |     0      |     0      |    1     |    1
00370      CCCR.ASM  |   0    |     1      |     0      |    0     |    0
00371   */
00372   if(hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION)
00373   {
00374     /* Enable Restricted Operation mode */
00375     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
00376   }
00377   else if(hfdcan->Init.Mode != FDCAN_MODE_NORMAL)
00378   {
00379     if(hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING)
00380     {
00381       /* Enable write access to TEST register */
00382       SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST);
00383
00384       /* Enable LoopBack mode */
00385       SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
00386
00387       if(hfdcan->Init.Mode == FDCAN_MODE_EXTERNAL_LOOPBACK)
00388       {
00389         SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
00390       }
00391     }
00392     else
00393     {
00394       /* Enable bus monitoring mode */
00395       SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
00396     }
00397   }
00398
00399   /* Set the nominal bit timing register */
00400   hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1) << 25) | \
00401                             (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1) << 8)       | \
00402                             ((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1)              | \
00403                             (((uint32_t)hfdcan->Init.NominalPrescaler - 1) << 16));
00404
00405   /* If FD operation with BRS is selected, set the data bit timing register */
00406   if(hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
00407   {
00408     hfdcan->Instance->DBTP = (((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1)   | \
00409                               (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1) << 8) | \
00410                               (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1) << 4) | \
00411                               (((uint32_t)hfdcan->Init.DataPrescaler - 1) << 16));
00412   }
00413
00414   if(hfdcan->Init.TxFifoQueueElmtsNbr > 0)
00415   {
00416     /* Select between Tx FIFO and Tx Queue operation modes */
00417     SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode);
00418   }
00419
00420   /* Configure Tx element size */
00421   if((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0)
00422   {
00423     MODIFY_REG(hfdcan->Instance->TXESC, FDCAN_TXESC_TBDS, CvtEltSize[hfdcan->Init.TxElmtSize]);
00424   }
00425
00426   /* Configure Rx FIFO 0 element size */
00427   if(hfdcan->Init.RxFifo0ElmtsNbr > 0)
00428   {
00429     MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F0DS, CvtEltSize[hfdcan->Init.RxFifo0ElmtSize]);
00430   }
00431
00432   /* Configure Rx FIFO 1 element size */
00433   if(hfdcan->Init.RxFifo1ElmtsNbr > 0)
00434   {
00435     MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F1DS, (CvtEltSize[hfdcan->Init.RxFifo1ElmtSize] << 4));
00436   }
00437
00438   /* Configure Rx buffer element size */
00439   if(hfdcan->Init.RxBuffersNbr > 0)
00440   {
00441     MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_RBDS, (CvtEltSize[hfdcan->Init.RxBufferSize] << 8));
00442   }
00443
00444   /* By default operation mode is set to Event-driven communication.
00445      If Time-triggered communication is needed, user should call the
00446      HAL_FDCAN_TT_ConfigOperation function just after the HAL_FDCAN_Init */
00447   if(hfdcan->Instance == FDCAN1)
00448   {
00449     CLEAR_BIT(hfdcan->ttcan->TTOCF, FDCAN_TTOCF_OM);
00450   }
00451
00452   /* Calculate each RAM block address */
00453   FDCAN_CalcultateRamBlockAddresses(hfdcan);
00454
00455   /* Initialize the error code */
00456   hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
00457
00458   /* Initialize the FDCAN state */
00459   hfdcan->State = HAL_FDCAN_STATE_READY;
00460
00461   /* Return function status */
00462   return HAL_OK;
00463 }
00464
00465 /**
00466   * @brief  Deinitializes the FDCAN peripheral registers to their default reset values.
00467   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
00468   *         the configuration information for the specified FDCAN.
00469   * @retval HAL status
00470   */
00471 HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef* hfdcan)
00472 {
00473   /* Check FDCAN handle */
00474   if(hfdcan == NULL)
00475   {
00476      return HAL_ERROR;
00477   }
00478
00479   /* Check function parameters */
00480   assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
00481
00482   /* Stop the FDCAN module */
00483   HAL_FDCAN_Stop(hfdcan);
00484
00485   /* DeInit the low level hardware */
00486   HAL_FDCAN_MspDeInit(hfdcan);
00487
00488   /* Reset the FDCAN ErrorCode */
00489   hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
00490
00491   /* Change FDCAN state */
00492   hfdcan->State = HAL_FDCAN_STATE_RESET;
00493
00494   /* Return function status */
00495   return HAL_OK;
00496 }
00497
00498 /**
00499   * @brief  Initializes the FDCAN MSP.
00500   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
00501   *         the configuration information for the specified FDCAN.
00502   * @retval None
00503   */
00504 __weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan)
00505 {
00506   /* Prevent unused argument(s) compilation warning */
00507   UNUSED(hfdcan);
00508   /* NOTE : This function Should not be modified, when the callback is needed,
00509             the HAL_FDCAN_MspInit could be implemented in the user file
00510    */
00511 }
00512
00513 /**
00514   * @brief  DeInitializes the FDCAN MSP.
00515   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
00516   *         the configuration information for the specified FDCAN.
00517   * @retval None
00518   */
00519 __weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* hfdcan)
00520 {
00521   /* Prevent unused argument(s) compilation warning */
00522   UNUSED(hfdcan);
00523   /* NOTE : This function Should not be modified, when the callback is needed,
00524             the HAL_FDCAN_MspDeInit could be implemented in the user file
00525    */
00526 }
00527
00528 /**
00529   * @brief  Enter FDCAN peripheral in sleep mode.
00530   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
00531   *         the configuration information for the specified FDCAN.
00532   * @retval HAL status
00533   */
00534 HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
00535 {
00536   uint32_t tickstart = 0U;
00537
00538   /* Request clock stop */
00539   SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
00540
00541   /* Get tick */
00542   tickstart = HAL_GetTick();
00543
00544   /* Wait until FDCAN is ready for power down */
00545   while((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == RESET)
00546   {
00547     if((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
00548     {
00549       /* Update error code */
00550       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
00551
00552       /* Change FDCAN state */
00553       hfdcan->State = HAL_FDCAN_STATE_ERROR;
00554
00555       return HAL_ERROR;
00556     }
00557   }
00558
00559   /* Return function status */
00560   return HAL_OK;
00561 }
00562
00563 /**
00564   * @brief  Exit power down mode.
00565   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
00566   *         the configuration information for the specified FDCAN.
00567   * @retval HAL status
00568   */
00569 HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
00570 {
00571   uint32_t tickstart = 0U;
00572
00573   /* Reset clock stop request */
00574   CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
00575
00576   /* Get tick */
00577   tickstart = HAL_GetTick();
00578
00579   /* Wait until FDCAN exits sleep mode */
00580   while((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
00581   {
00582     if((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
00583     {
00584       /* Update error code */
00585       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
00586
00587       /* Change FDCAN state */
00588       hfdcan->State = HAL_FDCAN_STATE_ERROR;
00589
00590       return HAL_ERROR;
00591     }
00592   }
00593
00594   /* Enter normal operation */
00595   CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
00596
00597   /* Return function status */
00598   return HAL_OK;
00599 }
00600
00601 /**
00602   * @}
00603   */
00604
00605 /** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions
00606  *  @brief    FDCAN Configuration functions.
00607  *
00608 @verbatim
00609   ==============================================================================
00610               ##### Configuration functions #####
00611   ==============================================================================
00612     [..]  This section provides functions allowing to:
00613       (+) HAL_FDCAN_ConfigClockCalibration        : Configure the FDCAN clock calibration unit
00614         (+) HAL_FDCAN_GetClockCalibrationState      : Get the clock calibration state
00615         (+) HAL_FDCAN_ResetClockCalibrationState    : Reset the clock calibration state
00616         (+) HAL_FDCAN_GetClockCalibrationCounter    : Get the clock calibration counters values
00617       (+) HAL_FDCAN_ConfigFilter                  : Configure the FDCAN reception filters
00618       (+) HAL_FDCAN_ConfigGlobalFilter            : Configure the FDCAN global filter
00619       (+) HAL_FDCAN_ConfigExtendedIdMask          : Configure the extended ID mask
00620       (+) HAL_FDCAN_ConfigRxFifoOverwrite         : Configure the Rx FIFO operation mode
00621       (+) HAL_FDCAN_ConfigFifoWatermark           : Configure the FIFO watermark
00622       (+) HAL_FDCAN_ConfigRamWatchdog             : Configure the RAM watchdog
00623       (+) HAL_FDCAN_ConfigTimestampCounter        : Configure the timestamp counter
00624         (+) HAL_FDCAN_EnableTimestampCounter        : Enable the timestamp counter
00625         (+) HAL_FDCAN_DisableTimestampCounter       : Disable the timestamp counter
00626         (+) HAL_FDCAN_GetTimestampCounter           : Get the timestamp counter value
00627         (+) HAL_FDCAN_ResetTimestampCounter         : Reset the timestamp counter to zero
00628       (+) HAL_FDCAN_ConfigTimeoutCounter          : Configure the timeout counter
00629         (+) HAL_FDCAN_EnableTimeoutCounter          : Enable the timeout counter
00630         (+) HAL_FDCAN_DisableTimeoutCounter         : Disable the timeout counter
00631         (+) HAL_FDCAN_GetTimeoutCounter             : Get the timeout counter value
00632         (+) HAL_FDCAN_ResetTimeoutCounter           : Reset the timeout counter to its start value
00633       (+) HAL_FDCAN_ConfigTxDelayCompensation     : Configure the transmitter delay compensation
00634         (+) HAL_FDCAN_EnableTxDelayCompensation     : Enable the transmitter delay compensation
00635         (+) HAL_FDCAN_DisableTxDelayCompensation    : Disable the transmitter delay compensation
00636
00637 @endverbatim
00638   * @{
00639   */
00640
00641 /**
00642   * @brief  Configure the FDCAN clock calibration unit according to the specified
00643   *         parameters in the FDCAN_ClkCalUnitTypeDef structure.
00644   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
00645   *         the configuration information for the specified FDCAN.
00646   * @param  sCcuConfig: pointer to an FDCAN_ClkCalUnitTypeDef structure that
00647   *         contains the clock calibration information
00648   * @retval HAL status
00649   */
00650 HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef* hfdcan, FDCAN_ClkCalUnitTypeDef* sCcuConfig)
00651 {
00652   /* Check function parameters */
00653   assert_param(IS_FUNCTIONAL_STATE(sCcuConfig->ClockCalibration));
00654   if(sCcuConfig->ClockCalibration == DISABLE)
00655   {
00656     assert_param(IS_FDCAN_CKDIV(sCcuConfig->ClockDivider));
00657   }
00658   else
00659   {
00660     assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->MinOscClkPeriods, 0xFF));
00661     assert_param(IS_FDCAN_CALIBRATION_FIELD_LENGTH(sCcuConfig->CalFieldLength));
00662     assert_param(IS_FDCAN_MIN_VALUE(sCcuConfig->TimeQuantaPerBitTime, 4));
00663     assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->TimeQuantaPerBitTime, 0x25));
00664     assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->WatchdogStartValue, 0xFFFF));
00665   }
00666
00667   /* FDCAN1 should be initialized in order to use clock calibration */
00668   if(hfdcan->Instance != FDCAN1)
00669   {
00670     /* Update error code */
00671     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
00672
00673     return HAL_ERROR;
00674   }
00675
00676   if(hfdcan->State == HAL_FDCAN_STATE_READY)
00677   {
00678     if(sCcuConfig->ClockCalibration == DISABLE)
00679     {
00680       /* Bypass clock calibration */
00681       SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
00682
00683       /* Configure clock divider */
00684       MODIFY_REG(FDCAN_CCU->CCFG, FDCANCCU_CCFG_CDIV, sCcuConfig->ClockDivider);
00685     }
00686     else /* sCcuConfig->ClockCalibration == ENABLE */
00687     {
00688       /* Clock calibration unit generates time quanta clock */
00689       CLEAR_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
00690
00691       /* Configure clock calibration unit */
00692       MODIFY_REG(FDCAN_CCU->CCFG,
00693                  (FDCANCCU_CCFG_TQBT | FDCANCCU_CCFG_CFL | FDCANCCU_CCFG_OCPM),
00694                  (sCcuConfig->TimeQuantaPerBitTime | sCcuConfig->CalFieldLength | (sCcuConfig->MinOscClkPeriods << 8)));
00695
00696       /* Configure the start value of the calibration watchdog counter */
00697       MODIFY_REG(FDCAN_CCU->CWD, FDCANCCU_CWD_WDC, sCcuConfig->WatchdogStartValue);
00698     }
00699
00700     /* Return function status */
00701     return HAL_OK;
00702   }
00703   else
00704   {
00705     /* Update error code */
00706     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
00707
00708     return HAL_ERROR;
00709   }
00710 }
00711
00712 /**
00713   * @brief  Get the clock calibration state.
00714   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
00715   *         the configuration information for the specified FDCAN.
00716   * @retval State: clock calibration state (can be a value of @arg FDCAN_calibration_state)
00717   */
00718 uint32_t HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef* hfdcan)
00719 {
00720   return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_CALS);
00721 }
00722
00723 /**
00724   * @brief  Reset the clock calibration state.
00725   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
00726   *         the configuration information for the specified FDCAN.
00727   * @retval HAL status
00728   */
00729 HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef* hfdcan)
00730 {
00731   /* Calibration software reset */
00732   SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_SWR);
00733
00734   /* Return function status */
00735   return HAL_OK;
00736 }
00737
00738 /**
00739   * @brief  Get the clock calibration counter value.
00740   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
00741   *         the configuration information for the specified FDCAN.
00742   * @param  Counter: clock calibration counter.
00743   *                  This parameter can be a value of @arg FDCAN_calibration_counter.
00744   * @retval Value: clock calibration counter value
00745   */
00746 uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef* hfdcan, uint32_t Counter)
00747 {
00748   if(Counter == FDCAN_CALIB_TIME_QUANTA_COUNTER)
00749   {
00750     return ((FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_TQC) >> 18);
00751   }
00752   else if(Counter == FDCAN_CALIB_CLOCK_PERIOD_COUNTER)
00753   {
00754     return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_OCPC);
00755   }
00756   else /* Counter == FDCAN_CALIB_WATCHDOG_COUNTER */
00757   {
00758     return ((FDCAN_CCU->CWD & FDCANCCU_CWD_WDV) >> 16);
00759   }
00760 }
00761
00762 /**
00763   * @brief  Configure the FDCAN reception filter according to the specified
00764   *         parameters in the FDCAN_FilterTypeDef structure.
00765   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
00766   *         the configuration information for the specified FDCAN.
00767   * @param  sFilterConfig: pointer to an FDCAN_FilterTypeDef structure that
00768   *         contains the filter configuration information
00769   * @retval HAL status
00770   */
00771 HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef* hfdcan, FDCAN_FilterTypeDef* sFilterConfig)
00772 {
00773   uint32_t FilterElementW1;
00774   uint32_t FilterElementW2;
00775   uint32_t *FilterAddress;
00776
00777   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
00778   {
00779     /* Check function parameters */
00780     assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType));
00781     assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig));
00782     if(sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
00783     {
00784       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->RxBufferIndex, 63));
00785       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->IsCalibrationMsg, 1));
00786     }
00787
00788     if(sFilterConfig->IdType == FDCAN_STANDARD_ID)
00789     {
00790       /* Check function parameters */
00791       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1)));
00792       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FF));
00793       if(sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
00794       {
00795         assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FF));
00796         assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType));
00797       }
00798
00799       /* Build filter element */
00800       if(sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
00801       {
00802         FilterElementW1 = ((FDCAN_FILTER_TO_RXBUFFER << 27)       |
00803                            (sFilterConfig->FilterID1 << 16)       |
00804                            (sFilterConfig->IsCalibrationMsg << 8) |
00805                            sFilterConfig->RxBufferIndex            );
00806       }
00807       else
00808       {
00809         FilterElementW1 = ((sFilterConfig->FilterType << 30)   |
00810                            (sFilterConfig->FilterConfig << 27) |
00811                            (sFilterConfig->FilterID1 << 16)    |
00812                            sFilterConfig->FilterID2             );
00813       }
00814
00815       /* Calculate filter address */
00816       FilterAddress = (uint32_t *)(hfdcan->msgRam.StandardFilterSA + (sFilterConfig->FilterIndex * 4));
00817
00818       /* Write filter element to the message RAM */
00819       *FilterAddress = FilterElementW1;
00820     }
00821     else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */
00822     {
00823       /* Check function parameters */
00824       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1)));
00825       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFF));
00826       if(sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
00827       {
00828         assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFF));
00829         assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType));
00830       }
00831
00832       /* Build first word of filter element */
00833       FilterElementW1 = ((sFilterConfig->FilterConfig << 29) | sFilterConfig->FilterID1);
00834
00835       /* Build second word of filter element */
00836       if(sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
00837       {
00838         FilterElementW2 = sFilterConfig->RxBufferIndex;
00839       }
00840       else
00841       {
00842         FilterElementW2 = ((sFilterConfig->FilterType << 30) | sFilterConfig->FilterID2);
00843       }
00844
00845       /* Calculate filter address */
00846       FilterAddress = (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA + (sFilterConfig->FilterIndex * 4 * 2));
00847
00848       /* Write filter element to the message RAM */
00849       *FilterAddress++ = FilterElementW1;
00850       *FilterAddress = FilterElementW2;
00851     }
00852
00853     /* Return function status */
00854     return HAL_OK;
00855   }
00856   else
00857   {
00858     /* Update error code */
00859     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
00860
00861     return HAL_ERROR;
00862   }
00863 }
00864
00865 /**
00866   * @brief  Configure the FDCAN global filter.
00867   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
00868   *         the configuration information for the specified FDCAN.
00869   * @param  NonMatchingStd: Defines how received messages with 11-bit IDs that
00870                             do not match any element of the filter list are treated.
00871                             This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
00872   * @param  NonMatchingExt: Defines how received messages with 29-bit IDs that
00873                             do not match any element of the filter list are treated.
00874                             This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
00875   * @param  RejectRemoteStd: Enable or disable the remote standard frames rejection.
00876                              This parameter can be set to ENABLE or DISABLE.
00877   * @param  RejectRemoteExt: Enable or disable the remote extended frames rejection.
00878                              This parameter can be set to ENABLE or DISABLE.
00879   * @retval HAL status
00880   */
00881 HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
00882                                                uint32_t NonMatchingStd,
00883                                                uint32_t NonMatchingExt,
00884                                                uint32_t RejectRemoteStd,
00885                                                uint32_t RejectRemoteExt)
00886 {
00887   /* Check function parameters */
00888   assert_param(IS_FDCAN_NON_MATCHING(NonMatchingStd));
00889   assert_param(IS_FDCAN_NON_MATCHING(NonMatchingExt));
00890   assert_param(IS_FUNCTIONAL_STATE(RejectRemoteStd));
00891   assert_param(IS_FUNCTIONAL_STATE(RejectRemoteExt));
00892
00893   if(hfdcan->State == HAL_FDCAN_STATE_READY)
00894   {
00895     /* Configure global filter */
00896     hfdcan->Instance->GFC = ((NonMatchingStd << 4U) | (NonMatchingExt << 2U) | (RejectRemoteStd << 1U) | RejectRemoteExt);
00897
00898     /* Return function status */
00899     return HAL_OK;
00900   }
00901   else
00902   {
00903     /* Update error code */
00904     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
00905
00906     return HAL_ERROR;
00907   }
00908 }
00909
00910 /**
00911   * @brief  Configure the extended ID mask.
00912   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
00913   *         the configuration information for the specified FDCAN.
00914   * @param  Mask: Extended ID Mask.
00915                   This parameter must be a number between 0 and 0x1FFFFFFF
00916   * @retval HAL status
00917   */
00918 HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
00919 {
00920   /* Check function parameters */
00921   assert_param(IS_FDCAN_MAX_VALUE(Mask, 0x1FFFFFFF));
00922
00923   if(hfdcan->State == HAL_FDCAN_STATE_READY)
00924   {
00925     /* Configure the extended ID mask */
00926     hfdcan->Instance->XIDAM = Mask;
00927
00928     /* Return function status */
00929     return HAL_OK;
00930   }
00931   else
00932   {
00933     /* Update error code */
00934     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
00935
00936     return HAL_ERROR;
00937   }
00938 }
00939
00940 /**
00941   * @brief  Configure the Rx FIFO operation mode.
00942   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
00943   *         the configuration information for the specified FDCAN.
00944   * @param  RxFifo: Rx FIFO.
00945   *                 This parameter can be one of the following values:
00946   *                   @arg FDCAN_RX_FIFO0: Rx FIFO 0
00947   *                   @arg FDCAN_RX_FIFO1: Rx FIFO 1
00948   * @param  OperationMode: operation mode.
00949   *                        This parameter can be a value of @arg FDCAN_Rx_FIFO_operation_mode.
00950   * @retval HAL status
00951   */
00952 HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
00953 {
00954   /* Check function parameters */
00955   assert_param(IS_FDCAN_RX_FIFO(RxFifo));
00956   assert_param(IS_FDCAN_RX_FIFO_MODE(OperationMode));
00957
00958   if(hfdcan->State == HAL_FDCAN_STATE_READY)
00959   {
00960     if(RxFifo == FDCAN_RX_FIFO0)
00961     {
00962       /* Select FIFO 0 Operation Mode */
00963       MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0OM, OperationMode);
00964     }
00965     else /* RxFifo == FDCAN_RX_FIFO1 */
00966     {
00967       /* Select FIFO 1 Operation Mode */
00968       MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1OM, OperationMode);
00969     }
00970
00971     /* Return function status */
00972     return HAL_OK;
00973   }
00974   else
00975   {
00976     /* Update error code */
00977     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
00978
00979     return HAL_ERROR;
00980   }
00981 }
00982
00983 /**
00984   * @brief  Configure the FIFO watermark.
00985   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
00986   *         the configuration information for the specified FDCAN.
00987   * @param  FIFO: select the FIFO to be configured.
00988   *               This parameter can be a value of @arg FDCAN_FIFO_watermark.
00989   * @param  Watermark: level for FIFO watermark interrupt.
00990   *                    This parameter must be a number between:
00991   *                     - 0 and 32, if FIFO is FDCAN_CFG_TX_EVENT_FIFO
00992   *                     - 0 and 64, if FIFO is FDCAN_CFG_RX_FIFO0 or FDCAN_CFG_RX_FIFO1
00993   * @retval HAL status
00994   */
00995 HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark)
00996 {
00997   /* Check function parameters */
00998   assert_param(IS_FDCAN_FIFO_WATERMARK(FIFO));
00999   if(FIFO == FDCAN_CFG_TX_EVENT_FIFO)
01000   {
01001     assert_param(IS_FDCAN_MAX_VALUE(Watermark, 32));
01002   }
01003   else /* (FIFO == FDCAN_CFG_RX_FIFO0) || (FIFO == FDCAN_CFG_RX_FIFO1) */
01004   {
01005     assert_param(IS_FDCAN_MAX_VALUE(Watermark, 64));
01006   }
01007
01008   if(hfdcan->State == HAL_FDCAN_STATE_READY)
01009   {
01010     /* Set the level for FIFO watermark interrupt */
01011     if(FIFO == FDCAN_CFG_TX_EVENT_FIFO)
01012     {
01013       MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFWM, (Watermark << 24));
01014     }
01015     else if(FIFO == FDCAN_CFG_RX_FIFO0)
01016     {
01017       MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0WM, (Watermark << 24));
01018     }
01019     else /* FIFO == FDCAN_CFG_RX_FIFO1 */
01020     {
01021       MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1WM, (Watermark << 24));
01022     }
01023
01024     /* Return function status */
01025     return HAL_OK;
01026   }
01027   else
01028   {
01029     /* Update error code */
01030     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01031
01032     return HAL_ERROR;
01033   }
01034 }
01035
01036 /**
01037   * @brief  Configure the RAM watchdog.
01038   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01039   *         the configuration information for the specified FDCAN.
01040   * @param  CounterStartValue: Start value of the Message RAM Watchdog Counter,
01041   *                            This parameter must be a number between 0x00 and 0xFF,
01042   *                            with the reset value of 0x00 the counter is disabled.
01043   * @retval HAL status
01044   */
01045 HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
01046 {
01047   /* Check function parameters */
01048   assert_param(IS_FDCAN_MAX_VALUE(CounterStartValue, 0xFF));
01049
01050   if(hfdcan->State == HAL_FDCAN_STATE_READY)
01051   {
01052     /* Configure the RAM watchdog counter start value */
01053     MODIFY_REG(hfdcan->Instance->RWD, FDCAN_RWD_WDC, CounterStartValue);
01054
01055     /* Return function status */
01056     return HAL_OK;
01057   }
01058   else
01059   {
01060     /* Update error code */
01061     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01062
01063     return HAL_ERROR;
01064   }
01065 }
01066
01067 /**
01068   * @brief  Configure the timestamp counter.
01069   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01070   *         the configuration information for the specified FDCAN.
01071   * @param  TimestampPrescaler: Timestamp Counter Prescaler.
01072   *                             This parameter can be a value of @arg FDCAN_Timestamp_Prescaler.
01073   * @retval HAL status
01074   */
01075 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
01076 {
01077   /* Check function parameters */
01078   assert_param(IS_FDCAN_TIMESTAMP_PRESCALER(TimestampPrescaler));
01079
01080   if(hfdcan->State == HAL_FDCAN_STATE_READY)
01081   {
01082     /* Configure prescaler */
01083     MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TCP, TimestampPrescaler);
01084
01085     /* Return function status */
01086     return HAL_OK;
01087   }
01088   else
01089   {
01090     /* Update error code */
01091     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01092
01093     return HAL_ERROR;
01094   }
01095 }
01096
01097 /**
01098   * @brief  Enable the timestamp counter.
01099   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01100   *         the configuration information for the specified FDCAN.
01101   * @param  TimestampOperation: Timestamp counter operation.
01102   *                             This parameter can be a value of @arg FDCAN_Timestamp.
01103   * @retval HAL status
01104   */
01105 HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
01106 {
01107   /* Check function parameters */
01108   assert_param(IS_FDCAN_TIMESTAMP(TimestampOperation));
01109
01110   if(hfdcan->State == HAL_FDCAN_STATE_READY)
01111   {
01112     /* Enable timestamp counter */
01113     MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS, TimestampOperation);
01114
01115     /* Return function status */
01116     return HAL_OK;
01117   }
01118   else
01119   {
01120     /* Update error code */
01121     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01122
01123     return HAL_ERROR;
01124   }
01125 }
01126
01127 /**
01128   * @brief  Disable the timestamp counter.
01129   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01130   *         the configuration information for the specified FDCAN.
01131   * @retval HAL status
01132   */
01133 HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
01134 {
01135   if(hfdcan->State == HAL_FDCAN_STATE_READY)
01136   {
01137     /* Disable timestamp counter */
01138     CLEAR_BIT(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS);
01139
01140     /* Return function status */
01141     return HAL_OK;
01142   }
01143   else
01144   {
01145     /* Update error code */
01146     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01147
01148     return HAL_ERROR;
01149   }
01150 }
01151
01152 /**
01153   * @brief  Get the timestamp counter value.
01154   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01155   *         the configuration information for the specified FDCAN.
01156   * @retval Value: Timestamp counter value
01157   */
01158 uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
01159 {
01160   return (uint16_t)(hfdcan->Instance->TSCV);
01161 }
01162
01163 /**
01164   * @brief  Reset the timestamp counter to zero.
01165   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01166   *         the configuration information for the specified FDCAN.
01167   * @retval HAL status
01168   */
01169 HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
01170 {
01171   if((hfdcan->Instance->TSCC & FDCAN_TSCC_TSS) != FDCAN_TIMESTAMP_EXTERNAL)
01172   {
01173     /* Reset timestamp counter.
01174        Actually any write operation to TSCV clears the counter */
01175     CLEAR_REG(hfdcan->Instance->TSCV);
01176   }
01177   else
01178   {
01179     /* Update error code.
01180        Unable to reset external counter */
01181     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
01182
01183     return HAL_ERROR;
01184   }
01185
01186   /* Return function status */
01187   return HAL_OK;
01188 }
01189
01190 /**
01191   * @brief  Configure the timeout counter.
01192   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01193   *         the configuration information for the specified FDCAN.
01194   * @param  TimeoutOperation: Timeout counter operation.
01195   *                           This parameter can be a value of @arg FDCAN_Timeout_Operation.
01196   * @param  TimeoutPeriod: Start value of the timeout down-counter.
01197   *                        This parameter must be a number between 0x0000 and 0xFFFF
01198   * @retval HAL status
01199   */
01200 HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
01201 {
01202   /* Check function parameters */
01203   assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation));
01204   assert_param(IS_FDCAN_MAX_VALUE(TimeoutPeriod, 0xFFFF));
01205
01206   if(hfdcan->State == HAL_FDCAN_STATE_READY)
01207   {
01208     /* Select timeout operation and configure period */
01209     MODIFY_REG(hfdcan->Instance->TOCC, (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << 16)));
01210
01211     /* Return function status */
01212     return HAL_OK;
01213   }
01214   else
01215   {
01216     /* Update error code */
01217     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01218
01219     return HAL_ERROR;
01220   }
01221 }
01222
01223 /**
01224   * @brief  Enable the timeout counter.
01225   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01226   *         the configuration information for the specified FDCAN.
01227   * @retval HAL status
01228   */
01229 HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
01230 {
01231   if(hfdcan->State == HAL_FDCAN_STATE_READY)
01232   {
01233     /* Enable timeout counter */
01234     SET_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
01235
01236     /* Return function status */
01237     return HAL_OK;
01238   }
01239   else
01240   {
01241     /* Update error code */
01242     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01243
01244     return HAL_ERROR;
01245   }
01246 }
01247
01248 /**
01249   * @brief  Disable the timeout counter.
01250   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01251   *         the configuration information for the specified FDCAN.
01252   * @retval HAL status
01253   */
01254 HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
01255 {
01256   if(hfdcan->State == HAL_FDCAN_STATE_READY)
01257   {
01258     /* Disable timeout counter */
01259     CLEAR_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
01260
01261     /* Return function status */
01262     return HAL_OK;
01263   }
01264   else
01265   {
01266     /* Update error code */
01267     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01268
01269     return HAL_ERROR;
01270   }
01271 }
01272
01273 /**
01274   * @brief  Get the timeout counter value.
01275   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01276   *         the configuration information for the specified FDCAN.
01277   * @retval Value: Timeout counter value
01278   */
01279 uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
01280 {
01281   return (uint16_t)(hfdcan->Instance->TOCV);
01282 }
01283
01284 /**
01285   * @brief  Reset the timeout counter to its start value.
01286   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01287   *         the configuration information for the specified FDCAN.
01288   * @retval HAL status
01289   */
01290 HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
01291 {
01292   if((hfdcan->Instance->TOCC & FDCAN_TOCC_TOS) != FDCAN_TIMEOUT_CONTINUOUS)
01293   {
01294     /* Reset timestamp counter to start value */
01295     CLEAR_REG(hfdcan->Instance->TOCV);
01296
01297     /* Return function status */
01298     return HAL_OK;
01299   }
01300   else
01301   {
01302     /* Update error code.
01303        Unable to reset counter: controlled only by FIFO empty state */
01304     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
01305
01306     return HAL_ERROR;
01307   }
01308 }
01309
01310 /**
01311   * @brief  Configure the transmitter delay compensation.
01312   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01313   *         the configuration information for the specified FDCAN.
01314   * @param  TdcOffset: Transmitter Delay Compensation Offset.
01315   *                    This parameter must be a number between 0x00 and 0xFF.
01316   * @param  TdcFilter: Transmitter Delay Compensation Filter Window Length.
01317   *                    This parameter must be a number between 0x00 and 0xFF.
01318   * @retval HAL status
01319   */
01320 HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
01321 {
01322   /* Check function parameters */
01323   assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0xFF));
01324   assert_param(IS_FDCAN_MAX_VALUE(TdcFilter, 0xFF));
01325
01326   if(hfdcan->State == HAL_FDCAN_STATE_READY)
01327   {
01328     /* Configure TDC offset and filter window */
01329     hfdcan->Instance->TDCR = (TdcFilter | (TdcOffset << 8));
01330
01331     /* Return function status */
01332     return HAL_OK;
01333   }
01334   else
01335   {
01336     /* Update error code */
01337     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01338
01339     return HAL_ERROR;
01340   }
01341 }
01342
01343 /**
01344   * @brief  Enable the transmitter delay compensation.
01345   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01346   *         the configuration information for the specified FDCAN.
01347   * @retval HAL status
01348   */
01349 HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
01350 {
01351   if(hfdcan->State == HAL_FDCAN_STATE_READY)
01352   {
01353     /* Enable transmitter delay compensation */
01354     SET_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
01355
01356     /* Return function status */
01357     return HAL_OK;
01358   }
01359   else
01360   {
01361     /* Update error code */
01362     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01363
01364     return HAL_ERROR;
01365   }
01366 }
01367
01368 /**
01369   * @brief  Disable the transmitter delay compensation.
01370   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01371   *         the configuration information for the specified FDCAN.
01372   * @retval HAL status
01373   */
01374 HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
01375 {
01376   if(hfdcan->State == HAL_FDCAN_STATE_READY)
01377   {
01378     /* Disable transmitter delay compensation */
01379     CLEAR_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
01380
01381     /* Return function status */
01382     return HAL_OK;
01383   }
01384   else
01385   {
01386     /* Update error code */
01387     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01388
01389     return HAL_ERROR;
01390   }
01391 }
01392
01393 /**
01394   * @}
01395   */
01396
01397 /** @defgroup FDCAN_Exported_Functions_Group3 Control functions
01398  *  @brief    Control functions
01399  *
01400 @verbatim
01401   ==============================================================================
01402                           ##### Control functions #####
01403   ==============================================================================
01404     [..]  This section provides functions allowing to:
01405       (+) HAL_FDCAN_Start                        : Start the FDCAN module
01406       (+) HAL_FDCAN_Stop                         : Stop the FDCAN module and enable access to configuration registers
01407       (+) HAL_FDCAN_AddMessageToTxFifoQ          : Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
01408       (+) HAL_FDCAN_AddMessageToTxBuffer         : Add a message to a dedicated Tx buffer
01409       (+) HAL_FDCAN_EnableTxBufferRequest        : Enable transmission request
01410       (+) HAL_FDCAN_AbortTxRequest               : Abort transmission request
01411       (+) HAL_FDCAN_GetRxMessage                 : Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM
01412       (+) HAL_FDCAN_GetTxEvent                   : Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM
01413       (+) HAL_FDCAN_GetHighPriorityMessageStatus : Get high priority message status
01414       (+) HAL_FDCAN_GetProtocolStatus            : Get protocol status
01415       (+) HAL_FDCAN_GetErrorCounters             : Get error counter values
01416       (+) HAL_FDCAN_IsRxBufferMessageAvailable   : Check if a new message is received in the selected Rx buffer
01417       (+) HAL_FDCAN_IsTxBufferMessagePending     : Check if a transmission request is pending on the selected Tx buffer
01418       (+) HAL_FDCAN_GetRxFifoFillLevel           : Return Rx FIFO fill level
01419       (+) HAL_FDCAN_GetTxFifoFreeLevel           : Return Tx FIFO free level
01420       (+) HAL_FDCAN_IsRestrictedOperationMode    : Check if the FDCAN peripheral entered Restricted Operation Mode
01421       (+) HAL_FDCAN_ExitRestrictedOperationMode  : Exit Restricted Operation Mode
01422
01423 @endverbatim
01424   * @{
01425   */
01426
01427 /**
01428   * @brief  Start the FDCAN module.
01429   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01430   *         the configuration information for the specified FDCAN.
01431   * @retval HAL status
01432   */
01433 HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan)
01434 {
01435   if(hfdcan->State == HAL_FDCAN_STATE_READY)
01436   {
01437     /* Change FDCAN peripheral state */
01438     hfdcan->State = HAL_FDCAN_STATE_BUSY;
01439
01440     /* Request leave initialisation */
01441     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
01442
01443     /* Reset the FDCAN ErrorCode */
01444     hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
01445
01446     /* Return function status */
01447     return HAL_OK;
01448   }
01449   else
01450   {
01451     /* Update error code */
01452     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01453
01454     return HAL_ERROR;
01455   }
01456 }
01457
01458 /**
01459   * @brief  Stop the FDCAN module and enable access to configuration registers.
01460   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01461   *         the configuration information for the specified FDCAN.
01462   * @retval HAL status
01463   */
01464 HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan)
01465 {
01466   uint32_t Counter = 0U;
01467
01468   if(hfdcan->State == HAL_FDCAN_STATE_BUSY)
01469   {
01470     /* Request initialisation */
01471     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
01472
01473     /* Wait until the INIT bit into CCCR register is set */
01474     while((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == RESET)
01475     {
01476       /* Check for the Timeout */
01477       if(Counter++ > FDCAN_TIMEOUT_VALUE)
01478       {
01479         /* Update error code */
01480         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
01481
01482         /* Change FDCAN state */
01483         hfdcan->State = HAL_FDCAN_STATE_ERROR;
01484
01485         return HAL_ERROR;
01486       }
01487     }
01488
01489     /* Enable configuration change */
01490     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
01491
01492     /* Change FDCAN peripheral state */
01493     hfdcan->State = HAL_FDCAN_STATE_READY;
01494
01495     /* Return function status */
01496     return HAL_OK;
01497   }
01498   else
01499   {
01500     /* Update error code */
01501     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
01502
01503     return HAL_ERROR;
01504   }
01505 }
01506
01507 /**
01508   * @brief  Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
01509   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01510   *         the configuration information for the specified FDCAN.
01511   * @param  pTxHeader: pointer to a FDCAN_TxHeaderTypeDef structure.
01512   * @param  pTxData: pointer to a buffer containing the payload of the Tx frame.
01513   * @retval HAL status
01514   */
01515 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData)
01516 {
01517   uint32_t PutIndex;
01518
01519   /* Check function parameters */
01520   assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
01521   if(pTxHeader->IdType == FDCAN_STANDARD_ID)
01522   {
01523     assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FF));
01524   }
01525   else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
01526   {
01527     assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFF));
01528   }
01529   assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
01530   assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
01531   assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
01532   assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
01533   assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
01534   assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
01535   assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFF));
01536
01537   if(hfdcan->State == HAL_FDCAN_STATE_BUSY)
01538   {
01539     /* Check that the Tx FIFO/Queue has an allocated area into the RAM */
01540     if((hfdcan->Instance->TXBC & FDCAN_TXBC_TFQS) == 0)
01541     {
01542       /* Update error code */
01543       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
01544
01545       return HAL_ERROR;
01546     }
01547
01548     /* Check that the Tx FIFO/Queue is not full */
01549     if((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0)
01550     {
01551       /* Update error code */
01552       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
01553
01554       return HAL_ERROR;
01555     }
01556     else
01557     {
01558       /* Retrieve the Tx FIFO PutIndex */
01559       PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> 16);
01560
01561       /* Add the message to the Tx FIFO/Queue */
01562       FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex);
01563
01564       /* Activate the corresponding transmission request */
01565       hfdcan->Instance->TXBAR = (1 << PutIndex);
01566     }
01567
01568     /* Return function status */
01569     return HAL_OK;
01570   }
01571   else
01572   {
01573     /* Update error code */
01574     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
01575
01576     return HAL_ERROR;
01577   }
01578 }
01579
01580 /**
01581   * @brief  Add a message to a dedicated Tx buffer
01582   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01583   *         the configuration information for the specified FDCAN.
01584   * @param  pTxHeader: pointer to a FDCAN_TxHeaderTypeDef structure.
01585   * @param  pTxData: pointer to a buffer containing the payload of the Tx frame.
01586   * @param  BufferIndex: index of the buffer to be configured.
01587   *                      This parameter can be a value of @arg FDCAN_Tx_location.
01588   * @retval HAL status
01589   */
01590 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
01591 {
01592   /* Check function parameters */
01593   assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
01594   if(pTxHeader->IdType == FDCAN_STANDARD_ID)
01595   {
01596     assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FF));
01597   }
01598   else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
01599   {
01600     assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFF));
01601   }
01602   assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
01603   assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
01604   assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
01605   assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
01606   assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
01607   assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
01608   assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFF));
01609   assert_param(IS_FDCAN_TX_LOCATION(BufferIndex));
01610
01611   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
01612   {
01613     /* Check that the selected buffer has an allocated area into the RAM */
01614     if(POSITION_VAL(BufferIndex) >= ((hfdcan->Instance->TXBC & FDCAN_TXBC_NDTB) >> 16))
01615     {
01616       /* Update error code */
01617       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
01618
01619       return HAL_ERROR;
01620     }
01621
01622     /* Check that there is no transmittion request pending for the selected buffer */
01623     if((hfdcan->Instance->TXBRP & BufferIndex) != 0)
01624     {
01625       /* Update error code */
01626       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
01627
01628       return HAL_ERROR;
01629     }
01630     else
01631     {
01632       /* Add the message to the Tx buffer */
01633       FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, POSITION_VAL(BufferIndex));
01634     }
01635
01636     /* Return function status */
01637     return HAL_OK;
01638   }
01639   else
01640   {
01641     /* Update error code */
01642     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
01643
01644     return HAL_ERROR;
01645   }
01646 }
01647
01648 /**
01649   * @brief  Enable transmission request.
01650   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01651   *         the configuration information for the specified FDCAN.
01652   * @param  BufferIndex: buffer index.
01653   *                      This parameter can be any combination of @arg FDCAN_Tx_location.
01654   * @retval HAL status
01655   */
01656 HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
01657 {
01658   if(hfdcan->State == HAL_FDCAN_STATE_BUSY)
01659   {
01660     /* Add transmission request */
01661     hfdcan->Instance->TXBAR = BufferIndex;
01662
01663     /* Return function status */
01664     return HAL_OK;
01665   }
01666   else
01667   {
01668     /* Update error code */
01669     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
01670
01671     return HAL_ERROR;
01672   }
01673 }
01674
01675 /**
01676   * @brief  Abort transmission request
01677   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01678   *         the configuration information for the specified FDCAN.
01679   * @param  BufferIndex: buffer index.
01680   *                      This parameter can be any combination of @arg FDCAN_Tx_location.
01681   * @retval HAL status
01682   */
01683 HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
01684 {
01685   if(hfdcan->State == HAL_FDCAN_STATE_BUSY)
01686   {
01687     /* Add cancellation request */
01688     hfdcan->Instance->TXBCR = BufferIndex;
01689
01690     /* Return function status */
01691     return HAL_OK;
01692   }
01693   else
01694   {
01695     /* Update error code */
01696     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
01697
01698     return HAL_ERROR;
01699   }
01700 }
01701
01702 /**
01703   * @brief  Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM.
01704   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01705   *         the configuration information for the specified FDCAN.
01706   * @param  RxLocation: Location of the received message to be read.
01707                         This parameter can be a value of @arg FDCAN_Rx_location.
01708   * @param  pRxHeader: pointer to a FDCAN_RxHeaderTypeDef structure.
01709   * @param  pRxData: pointer to a buffer where the payload of the Rx frame will be stored.
01710   * @retval HAL status
01711   */
01712 HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
01713 {
01714   uint32_t *RxAddress;
01715   uint8_t  *pData;
01716   uint32_t ByteCounter;
01717   uint32_t GetIndex = 0;
01718
01719   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
01720   {
01721     if(RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
01722     {
01723       /* Check that the Rx FIFO 0 has an allocated area into the RAM */
01724       if((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0S) == 0)
01725       {
01726         /* Update error code */
01727         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
01728
01729         return HAL_ERROR;
01730       }
01731
01732       /* Check that the Rx FIFO 0 is not empty */
01733       if((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0)
01734       {
01735         /* Update error code */
01736         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
01737
01738         return HAL_ERROR;
01739       }
01740       else
01741       {
01742         /* Calculate Rx FIFO 0 element address */
01743         GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> 8);
01744         RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * hfdcan->Init.RxFifo0ElmtSize * 4));
01745       }
01746     }
01747     else if(RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
01748     {
01749       /* Check that the Rx FIFO 1 has an allocated area into the RAM */
01750       if((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1S) == 0)
01751       {
01752         /* Update error code */
01753         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
01754
01755         return HAL_ERROR;
01756       }
01757
01758       /* Check that the Rx FIFO 0 is not empty */
01759       if((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0)
01760       {
01761         /* Update error code */
01762         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
01763
01764         return HAL_ERROR;
01765       }
01766       else
01767       {
01768         /* Calculate Rx FIFO 1 element address */
01769         GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> 8);
01770         RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * hfdcan->Init.RxFifo1ElmtSize * 4));
01771       }
01772     }
01773     else /* Rx element is assigned to a dedicated Rx buffer */
01774     {
01775       /* Check that the selected buffer has an allocated area into the RAM */
01776       if(RxLocation >= hfdcan->Init.RxBuffersNbr)
01777       {
01778         /* Update error code */
01779         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
01780
01781         return HAL_ERROR;
01782       }
01783       else
01784       {
01785         /* Calculate Rx buffer address */
01786         RxAddress = (uint32_t *)(hfdcan->msgRam.RxBufferSA + (RxLocation * hfdcan->Init.RxBufferSize * 4));
01787       }
01788     }
01789
01790     /* Retrieve IdType */
01791     pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD;
01792
01793     /* Retrieve Identifier */
01794     if(pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
01795     {
01796       pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18);
01797     }
01798     else /* Extended ID element */
01799     {
01800       pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID);
01801     }
01802
01803     /* Retrieve RxFrameType */
01804     pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR);
01805
01806     /* Retrieve ErrorStateIndicator */
01807     pRxHeader->ErrorStateIndicator = (*RxAddress++ & FDCAN_ELEMENT_MASK_ESI);
01808
01809     /* Retrieve RxTimestamp */
01810     pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
01811
01812     /* Retrieve DataLength */
01813     pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC);
01814
01815     /* Retrieve BitRateSwitch */
01816     pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
01817
01818     /* Retrieve FDFormat */
01819     pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF);
01820
01821     /* Retrieve FilterIndex */
01822     pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24);
01823
01824     /* Retrieve NonMatchingFrame */
01825     pRxHeader->IsFilterMatchingFrame = ((*RxAddress++ & FDCAN_ELEMENT_MASK_ANMF) >> 31);
01826
01827     /* Retrieve Rx payload */
01828     pData = (uint8_t *)RxAddress;
01829     for(ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16]; ByteCounter++)
01830     {
01831       *pRxData++ = *pData++;
01832     }
01833
01834     if(RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
01835     {
01836       /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */
01837       hfdcan->Instance->RXF0A = GetIndex;
01838     }
01839     else if(RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
01840     {
01841       /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */
01842       hfdcan->Instance->RXF1A = GetIndex;
01843     }
01844     else /* Rx element is assigned to a dedicated Rx buffer */
01845     {
01846       /* Clear the New Data flag of the current Rx buffer */
01847       if(RxLocation < FDCAN_RX_BUFFER32)
01848       {
01849         hfdcan->Instance->NDAT1 = (1 << RxLocation);
01850       }
01851       else /* FDCAN_RX_BUFFER32 <= RxLocation <= FDCAN_RX_BUFFER63 */
01852       {
01853         hfdcan->Instance->NDAT2 = (1 << (RxLocation - 0x20));
01854       }
01855     }
01856
01857     /* Return function status */
01858     return HAL_OK;
01859   }
01860   else
01861   {
01862     /* Update error code */
01863     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
01864
01865     return HAL_ERROR;
01866   }
01867 }
01868
01869 /**
01870   * @brief  Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
01871   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01872   *         the configuration information for the specified FDCAN.
01873   * @param  pTxEvent: pointer to a FDCAN_TxEventFifoTypeDef structure.
01874   * @retval HAL status
01875   */
01876 HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
01877 {
01878   uint32_t *TxEventAddress;
01879   uint32_t GetIndex;
01880
01881   /* Check function parameters */
01882   assert_param(IS_FDCAN_MIN_VALUE(hfdcan->Init.TxEventsNbr, 1));
01883
01884   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
01885   {
01886     /* Check that the Tx Event FIFO has an allocated area into the RAM */
01887     if((hfdcan->Instance->TXEFC & FDCAN_TXEFC_EFS) == 0)
01888     {
01889       /* Update error code */
01890       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
01891
01892       return HAL_ERROR;
01893     }
01894
01895     /* Check that the Tx event FIFO is not empty */
01896     if((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFFL) == 0)
01897     {
01898       /* Update error code */
01899       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
01900
01901       return HAL_ERROR;
01902     }
01903
01904     /* Calculate Tx event FIFO element address */
01905     GetIndex = ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFGI) >> 8);
01906     TxEventAddress = (uint32_t *)(hfdcan->msgRam.TxEventFIFOSA + (GetIndex * 2 * 4));
01907
01908     /* Retrieve IdType */
01909     pTxEvent->IdType = *TxEventAddress & FDCAN_ELEMENT_MASK_XTD;
01910
01911     /* Retrieve Identifier */
01912     if(pTxEvent->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
01913     {
01914       pTxEvent->Identifier = ((*TxEventAddress & FDCAN_ELEMENT_MASK_STDID) >> 18);
01915     }
01916     else /* Extended ID element */
01917     {
01918       pTxEvent->Identifier = (*TxEventAddress & FDCAN_ELEMENT_MASK_EXTID);
01919     }
01920
01921     /* Retrieve RxFrameType */
01922     pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_MASK_RTR);
01923
01924     /* Retrieve ErrorStateIndicator */
01925     pTxEvent->ErrorStateIndicator = (*TxEventAddress++ & FDCAN_ELEMENT_MASK_ESI);
01926
01927     /* Retrieve RxTimestamp */
01928     pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS);
01929
01930     /* Retrieve DataLength */
01931     pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_MASK_DLC);
01932
01933     /* Retrieve BitRateSwitch */
01934     pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS);
01935
01936     /* Retrieve FDFormat */
01937     pTxEvent->FDFormat = (*TxEventAddress & FDCAN_ELEMENT_MASK_FDF);
01938
01939     /* Retrieve EventType */
01940     pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET);
01941
01942     /* Retrieve MessageMarker */
01943     pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24);
01944
01945     /* Acknowledge the Tx Event FIFO that the oldest element is read so that it increments the GetIndex */
01946     hfdcan->Instance->TXEFA = GetIndex;
01947
01948     /* Return function status */
01949     return HAL_OK;
01950   }
01951   else
01952   {
01953     /* Update error code */
01954     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
01955
01956     return HAL_ERROR;
01957   }
01958 }
01959
01960 /**
01961   * @brief  Get high priority message status.
01962   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01963   *         the configuration information for the specified FDCAN.
01964   * @param  HpMsgStatus: pointer to an FDCAN_HpMsgStatusTypeDef structure.
01965   * @retval HAL status
01966   */
01967 HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
01968 {
01969   HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> 15);
01970   HpMsgStatus->FilterIndex = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> 8);
01971   HpMsgStatus->MessageStorage = (hfdcan->Instance->HPMS & FDCAN_HPMS_MSI);
01972   HpMsgStatus->MessageIndex = (hfdcan->Instance->HPMS & FDCAN_HPMS_BIDX);
01973
01974   /* Return function status */
01975   return HAL_OK;
01976 }
01977
01978 /**
01979   * @brief  Get protocol status.
01980   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
01981   *         the configuration information for the specified FDCAN.
01982   * @param  ProtocolStatus: pointer to an FDCAN_ProtocolStatusTypeDef structure.
01983   * @retval HAL status
01984   */
01985 HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
01986 {
01987   uint32_t StatusReg;
01988
01989   /* Read the protocol status register */
01990   StatusReg = READ_REG(hfdcan->Instance->PSR);
01991
01992   /* Fill the protocol status structure */
01993   ProtocolStatus->LastErrorCode = (StatusReg & FDCAN_PSR_LEC);
01994   ProtocolStatus->DataLastErrorCode =  ((StatusReg & FDCAN_PSR_DLEC) >> 8);
01995   ProtocolStatus->Activity =  (StatusReg & FDCAN_PSR_ACT);
01996   ProtocolStatus->ErrorPassive =  ((StatusReg & FDCAN_PSR_EP) >> 5);
01997   ProtocolStatus->Warning =  ((StatusReg & FDCAN_PSR_EW) >> 6);
01998   ProtocolStatus->BusOff =  ((StatusReg & FDCAN_PSR_BO) >> 7);
01999   ProtocolStatus->RxESIflag =  ((StatusReg & FDCAN_PSR_RESI) >> 11);
02000   ProtocolStatus->RxBRSflag =  ((StatusReg & FDCAN_PSR_RBRS) >> 12);
02001   ProtocolStatus->RxFDFflag =  ((StatusReg & FDCAN_PSR_REDL) >> 13);
02002   ProtocolStatus->ProtocolException =  ((StatusReg & FDCAN_PSR_PXE) >> 14);
02003   ProtocolStatus->TDCvalue =  ((StatusReg & FDCAN_PSR_TDCV) >> 16);
02004
02005   /* Return function status */
02006   return HAL_OK;
02007 }
02008
02009 /**
02010   * @brief  Get error counter values.
02011   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
02012   *         the configuration information for the specified FDCAN.
02013   * @param  ErrorCounters: pointer to an FDCAN_ErrorCountersTypeDef structure.
02014   * @retval HAL status
02015   */
02016 HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
02017 {
02018   uint32_t CountersReg;
02019
02020   /* Read the error counters register */
02021   CountersReg = READ_REG(hfdcan->Instance->ECR);
02022
02023   /* Fill the error counters structure */
02024   ErrorCounters->TxErrorCnt = (CountersReg & FDCAN_ECR_TEC);
02025   ErrorCounters->RxErrorCnt = ((CountersReg & FDCAN_ECR_TREC) >> 8);
02026   ErrorCounters->RxErrorPassive = ((CountersReg & FDCAN_ECR_RP) >> 15);
02027   ErrorCounters->ErrorLogging = ((CountersReg & FDCAN_ECR_CEL) >> 16);
02028
02029   /* Return function status */
02030   return HAL_OK;
02031 }
02032
02033 /**
02034   * @brief  Check if a new message is received in the selected Rx buffer.
02035   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
02036   *         the configuration information for the specified FDCAN.
02037   * @param  RxBufferIndex: Rx buffer index.
02038   *                        This parameter must be a number between 0 and 63.
02039   * @retval Status:
02040   *          - 0 : No new message on RxBufferIndex.
02041   *          - 1 : New message received on RxBufferIndex.
02042   */
02043 uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex)
02044 {
02045   /* Check function parameters */
02046   assert_param(IS_FDCAN_MAX_VALUE(RxBufferIndex, 63));
02047
02048   /* Check new message reception on the selected buffer */
02049   if(((RxBufferIndex < 32) && ((hfdcan->Instance->NDAT1 & (1 << RxBufferIndex)) == 0)) ||
02050      ((RxBufferIndex >= 32) && ((hfdcan->Instance->NDAT2 & (1 << (RxBufferIndex - 0x20))) == 0)))
02051   {
02052     return 0;
02053   }
02054
02055   /* Clear the New Data flag of the current Rx buffer */
02056   if(RxBufferIndex < 32)
02057   {
02058     hfdcan->Instance->NDAT1 = (1 << RxBufferIndex);
02059   }
02060   else /* 32 <= RxBufferIndex <= 63 */
02061   {
02062     hfdcan->Instance->NDAT2 = (1 << (RxBufferIndex - 0x20));
02063   }
02064
02065   return 1;
02066 }
02067
02068 /**
02069   * @brief  Check if a transmission request is pending on the selected Tx buffer.
02070   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
02071   *         the configuration information for the specified FDCAN.
02072   * @param  TxBufferIndex: Tx buffer index.
02073   *                        This parameter can be a value of @arg FDCAN_Tx_location.
02074   * @retval Status:
02075   *          - 0 : No pending transmission request on RxBufferIndex.
02076   *          - 1 : Pending transmission request on RxBufferIndex.
02077   */
02078 uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
02079 {
02080   /* Check function parameters */
02081   assert_param(IS_FDCAN_TX_LOCATION(TxBufferIndex));
02082
02083   /* Check pending transmittion request on the selected buffer */
02084   if((hfdcan->Instance->TXBRP & TxBufferIndex) == 0)
02085   {
02086     return 0;
02087   }
02088   return 1;
02089 }
02090
02091 /**
02092   * @brief  Return Rx FIFO fill level.
02093   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
02094   *         the configuration information for the specified FDCAN.
02095   * @param  RxFifo: Rx FIFO.
02096   *                 This parameter can be one of the following values:
02097   *                   @arg FDCAN_RX_FIFO0: Rx FIFO 0
02098   *                   @arg FDCAN_RX_FIFO1: Rx FIFO 1
02099   * @retval Level: Rx FIFO fill level.
02100   */
02101 uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
02102 {
02103   uint32_t FillLevel;
02104
02105   /* Check function parameters */
02106   assert_param(IS_FDCAN_RX_FIFO(RxFifo));
02107
02108   if(RxFifo == FDCAN_RX_FIFO0)
02109   {
02110     FillLevel = hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL;
02111   }
02112   else /* RxFifo == FDCAN_RX_FIFO1 */
02113   {
02114     FillLevel = hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL;
02115   }
02116
02117   /* Return Rx FIFO fill level */
02118   return FillLevel;
02119 }
02120
02121 /**
02122   * @brief  Return Tx FIFO free level: number of consecutive free Tx FIFO
02123   *         elements starting from Tx FIFO GetIndex.
02124   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
02125   *         the configuration information for the specified FDCAN.
02126   * @retval Level: Tx FIFO free level.
02127   */
02128 uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan)
02129 {
02130   uint32_t FreeLevel;
02131
02132   FreeLevel = hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFFL;
02133
02134   /* Return Tx FIFO free level */
02135   return FreeLevel;
02136 }
02137
02138 /**
02139   * @brief  Check if the FDCAN peripheral entered Restricted Operation Mode.
02140   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
02141   *         the configuration information for the specified FDCAN.
02142   * @retval Status:
02143   *          - 0 : Normal FDCAN operation.
02144   *          - 1 : Restricted Operation Mode active.
02145   */
02146 uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
02147 {
02148   uint32_t OperationMode;
02149
02150   /* Get Operation Mode */
02151   OperationMode = ((hfdcan->Instance->CCCR & FDCAN_CCCR_ASM) >> 2);
02152
02153   return OperationMode;
02154 }
02155
02156 /**
02157   * @brief  Exit Restricted Operation Mode.
02158   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
02159   *         the configuration information for the specified FDCAN.
02160   * @retval HAL status
02161   */
02162 HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
02163 {
02164   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
02165   {
02166     /* Exit Restricted Operation mode */
02167     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
02168
02169     /* Return function status */
02170     return HAL_OK;
02171   }
02172   else
02173   {
02174     /* Update error code */
02175     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
02176
02177     return HAL_ERROR;
02178   }
02179 }
02180
02181 /**
02182   * @}
02183   */
02184
02185 /** @defgroup FDCAN_Exported_Functions_Group4 TT Configuration and control functions
02186  *  @brief    TT Configuration and control functions
02187  *
02188 @verbatim
02189   ==============================================================================
02190               ##### TT Configuration and control functions #####
02191   ==============================================================================
02192     [..]  This section provides functions allowing to:
02193       (+) HAL_FDCAN_TT_ConfigOperation                  : Initialize TT operation parameters
02194       (+) HAL_FDCAN_TT_ConfigReferenceMessage           : Configure the reference message
02195       (+) HAL_FDCAN_TT_ConfigTrigger                    : Configure the FDCAN trigger
02196       (+) HAL_FDCAN_TT_SetGlobalTime                    : Schedule global time adjustment
02197       (+) HAL_FDCAN_TT_SetClockSynchronization          : Schedule TUR numerator update
02198       (+) HAL_FDCAN_TT_ConfigStopWatch                  : Configure stop watch source and polarity
02199       (+) HAL_FDCAN_TT_ConfigRegisterTimeMark           : Configure register time mark pulse generation
02200         (+) HAL_FDCAN_TT_EnableRegisterTimeMarkPulse      : Enable register time mark pulse generation
02201         (+) HAL_FDCAN_TT_DisableRegisterTimeMarkPulse     : Disable register time mark pulse generation
02202       (+) HAL_FDCAN_TT_EnableTriggerTimeMarkPulse       : Enable trigger time mark pulse generation
02203       (+) HAL_FDCAN_TT_DisableTriggerTimeMarkPulse      : Disable trigger time mark pulse generation
02204       (+) HAL_FDCAN_TT_EnableHardwareGapControl         : Enable gap control by input pin fdcan1_evt
02205       (+) HAL_FDCAN_TT_DisableHardwareGapControl        : Disable gap control by input pin fdcan1_evt
02206       (+) HAL_FDCAN_TT_EnableTimeMarkGapControl         : Enable gap control (finish only) by register time mark interrupt
02207       (+) HAL_FDCAN_TT_DisableTimeMarkGapControl        : Disable gap control by register time mark interrupt
02208       (+) HAL_FDCAN_TT_SetNextIsGap                     : Transmit next reference message with Next_is_Gap = "1"
02209       (+) HAL_FDCAN_TT_SetEndOfGap                      : Finish a Gap by requesting start of reference message
02210       (+) HAL_FDCAN_TT_ConfigExternalSyncPhase          : Configure target phase used for external synchronization
02211         (+) HAL_FDCAN_TT_EnableExternalSynchronization    : Synchronize the phase of the FDCAN schedule to an external schedule
02212         (+) HAL_FDCAN_TT_DisableExternalSynchronization   : Disable external schedule synchronization
02213       (+) HAL_FDCAN_TT_GetOperationStatus               : Get TT operation status
02214
02215 @endverbatim
02216   * @{
02217   */
02218
02219 /**
02220   * @brief  Initialize TT operation parameters.
02221   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
02222   *         the configuration information for the specified FDCAN.
02223   * @param  pTTParams: pointer to a FDCAN_TT_ConfigTypeDef structure.
02224   * @retval HAL status
02225   */
02226 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams)
02227 {
02228   uint32_t tickstart = 0U;
02229   uint32_t RAMcounter;
02230
02231   /* Check function parameters */
02232   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
02233   assert_param(IS_FDCAN_TT_TUR_NUMERATOR(pTTParams->TURNumerator));
02234   assert_param(IS_FDCAN_TT_TUR_DENOMINATOR(pTTParams->TURDenominator));
02235   assert_param(IS_FDCAN_TT_TIME_MASTER(pTTParams->TimeMaster));
02236   assert_param(IS_FDCAN_MAX_VALUE(pTTParams->SyncDevLimit, 7));
02237   assert_param(IS_FDCAN_MAX_VALUE(pTTParams->InitRefTrigOffset, 127));
02238   assert_param(IS_FDCAN_MAX_VALUE(pTTParams->TriggerMemoryNbr, 64));
02239   assert_param(IS_FDCAN_TT_CYCLE_START_SYNC(pTTParams->CycleStartSync));
02240   assert_param(IS_FDCAN_TT_STOP_WATCH_TRIGGER(pTTParams->StopWatchTrigSel));
02241   assert_param(IS_FDCAN_TT_EVENT_TRIGGER(pTTParams->EventTrigSel));
02242   if(pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER)
02243   {
02244     assert_param(IS_FDCAN_TT_BASIC_CYCLES_NUMBER(pTTParams->BasicCyclesNbr));
02245   }
02246   if(pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
02247   {
02248     assert_param(IS_FDCAN_TT_OPERATION(pTTParams->GapEnable));
02249     assert_param(IS_FDCAN_MAX_VALUE(pTTParams->AppWdgLimit, 255));
02250     assert_param(IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(pTTParams->EvtTrigPolarity));
02251     assert_param(IS_FDCAN_TT_TX_ENABLE_WINDOW(pTTParams->TxEnableWindow));
02252     assert_param(IS_FDCAN_MAX_VALUE(pTTParams->ExpTxTrigNbr, 4095));
02253   }
02254   if(pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1)
02255   {
02256     assert_param(IS_FDCAN_TT_TUR_LEVEL_0_2(pTTParams->TURNumerator, pTTParams->TURDenominator));
02257     assert_param(IS_FDCAN_TT_EXTERNAL_CLK_SYNC(pTTParams->ExternalClkSync));
02258     assert_param(IS_FDCAN_TT_GLOBAL_TIME_FILTERING(pTTParams->GlobalTimeFilter));
02259     assert_param(IS_FDCAN_TT_AUTO_CLK_CALIBRATION(pTTParams->ClockCalibration));
02260   }
02261   else
02262   {
02263     assert_param(IS_FDCAN_TT_TUR_LEVEL_1(pTTParams->TURNumerator, pTTParams->TURDenominator));
02264   }
02265
02266   if(hfdcan->State == HAL_FDCAN_STATE_READY)
02267   {
02268     /* Stop local time in order to enable write access to the other bits of TURCF register */
02269     CLEAR_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT);
02270
02271     /* Get tick */
02272     tickstart = HAL_GetTick();
02273
02274     /* Wait until the ELT bit into TURCF register is reset */
02275     while((hfdcan->ttcan->TURCF & FDCAN_TURCF_ELT) != RESET)
02276     {
02277       /* Check for the Timeout */
02278       if((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
02279       {
02280         /* Update error code */
02281         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
02282
02283         /* Change FDCAN state */
02284         hfdcan->State = HAL_FDCAN_STATE_ERROR;
02285
02286         return HAL_ERROR;
02287       }
02288     }
02289
02290     /* Configure TUR (Time Unit Ratio) */
02291     MODIFY_REG(hfdcan->ttcan->TURCF,
02292                (FDCAN_TURCF_NCL | FDCAN_TURCF_DC),
02293                ((pTTParams->TURNumerator - 0x10000) | (pTTParams->TURDenominator << 16)));
02294
02295     /* Enable local time */
02296     SET_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT);
02297
02298     /* Configure TT operation */
02299     MODIFY_REG(hfdcan->ttcan->TTOCF,
02300                (FDCAN_TTOCF_OM | FDCAN_TTOCF_TM | FDCAN_TTOCF_LDSDL | FDCAN_TTOCF_IRTO),
02301                (pTTParams->OperationMode            | \
02302                 pTTParams->TimeMaster               | \
02303                 (pTTParams->SyncDevLimit << 5)      | \
02304                 (pTTParams->InitRefTrigOffset << 8)));
02305     if(pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
02306     {
02307       MODIFY_REG(hfdcan->ttcan->TTOCF,
02308                 (FDCAN_TTOCF_GEN | FDCAN_TTOCF_AWL | FDCAN_TTOCF_EVTP),
02309                 (pTTParams->GapEnable           | \
02310                  (pTTParams->AppWdgLimit << 16) | \
02311                  pTTParams->EvtTrigPolarity));
02312     }
02313     if(pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1)
02314     {
02315       MODIFY_REG(hfdcan->ttcan->TTOCF,
02316                  (FDCAN_TTOCF_EECS | FDCAN_TTOCF_EGTF | FDCAN_TTOCF_ECC),
02317                  (pTTParams->ExternalClkSync  | \
02318                   pTTParams->GlobalTimeFilter | \
02319                   pTTParams->ClockCalibration));
02320     }
02321
02322     /* Configure system matrix limits */
02323     MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CSS, pTTParams->CycleStartSync);
02324     if(pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
02325     {
02326       MODIFY_REG(hfdcan->ttcan->TTMLM,
02327                  (FDCAN_TTMLM_TXEW | FDCAN_TTMLM_ENTT),
02328                  (((pTTParams->TxEnableWindow - 1) << 8) | (pTTParams->ExpTxTrigNbr << 16)));
02329     }
02330     if(pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER)
02331     {
02332       MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CCM, pTTParams->BasicCyclesNbr);
02333     }
02334
02335     /* Configure input triggers: Stop watch and Event */
02336     MODIFY_REG(hfdcan->ttcan->TTTS,
02337                (FDCAN_TTTS_SWTSEL | FDCAN_TTTS_EVTSEL),
02338                (pTTParams->StopWatchTrigSel | pTTParams->EventTrigSel));
02339
02340     /* Configure trigger memory start address */
02341      hfdcan->msgRam.TTMemorySA = (hfdcan->msgRam.EndAddress - SRAMCAN_BASE) / 4;
02342      MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TMSA, (hfdcan->msgRam.TTMemorySA << 2));
02343
02344      /* Trigger memory elements number */
02345      MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TME, (pTTParams->TriggerMemoryNbr << 16));
02346
02347     /* Recalculate End Address */
02348     hfdcan->msgRam.TTMemorySA = SRAMCAN_BASE + (hfdcan->msgRam.TTMemorySA * 4);
02349     hfdcan->msgRam.EndAddress = hfdcan->msgRam.TTMemorySA + (pTTParams->TriggerMemoryNbr * 2 * 4);
02350
02351     if(hfdcan->msgRam.EndAddress > 0x4000B5FC) /* Last address of the Message RAM */
02352     {
02353       /* Update error code.
02354          Message RAM overflow */
02355       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
02356
02357       return HAL_ERROR;
02358     }
02359     else
02360     {
02361       /* Flush the allocated Message RAM area */
02362       for(RAMcounter = hfdcan->msgRam.TTMemorySA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4)
02363       {
02364         *(__IO uint32_t *)(RAMcounter) = 0x00000000;
02365       }
02366     }
02367
02368     /* Return function status */
02369     return HAL_OK;
02370   }
02371   else
02372   {
02373     /* Update error code */
02374     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02375
02376     return HAL_ERROR;
02377   }
02378 }
02379
02380 /**
02381   * @brief  Configure the reference message.
02382   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
02383   *         the configuration information for the specified FDCAN.
02384   * @param  IdType: Identifier Type.
02385   *                 This parameter can be a value of @arg FDCAN_id_type.
02386   * @param  Identifier: Reference Identifier.
02387   *                     This parameter must be a number between:
02388   *                      - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
02389   *                      - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID
02390   * @param  Payload: Enable or disable the additional payload.
02391   *                  This parameter can be a value of @arg FDCAN_TT_Reference_Message_Payload.
02392   *                  This parameter is ignored in case of time slaves.
02393   *                  If this parameter is set to FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD, the
02394   *                  following elements are taken from Tx Buffer 0:
02395   *                   - MessageMarker
02396   *                   - TxEventFifoControl
02397   *                   - DataLength
02398   *                   - Data Bytes (payload):
02399   *                      - bytes 2-8, for Level 1
02400   *                      - bytes 5-8, for Level 0 and Level 2
02401   * @retval HAL status
02402   */
02403 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload)
02404 {
02405   /* Check function parameters */
02406   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
02407   assert_param(IS_FDCAN_ID_TYPE(IdType));
02408   if(IdType == FDCAN_STANDARD_ID)
02409   {
02410     assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x7FF));
02411   }
02412   else /* IdType == FDCAN_EXTENDED_ID */
02413   {
02414     assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x1FFFFFFF));
02415   }
02416   assert_param(IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(Payload));
02417
02418   if(hfdcan->State == HAL_FDCAN_STATE_READY)
02419   {
02420     /* Configure reference message identifier type, identifier and payload */
02421     if(IdType == FDCAN_EXTENDED_ID)
02422     {
02423       MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | Identifier));
02424     }
02425     else /* IdType == FDCAN_STANDARD_ID */
02426     {
02427       MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | (Identifier << 18)));
02428     }
02429
02430     /* Return function status */
02431     return HAL_OK;
02432   }
02433   else
02434   {
02435     /* Update error code */
02436     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02437
02438     return HAL_ERROR;
02439   }
02440 }
02441
02442 /**
02443   * @brief  Configure the FDCAN trigger according to the specified
02444   *         parameters in the FDCAN_TriggerTypeDef structure.
02445   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
02446   *         the configuration information for the specified FDCAN.
02447   * @param  sTriggerConfig: pointer to an FDCAN_TriggerTypeDef structure that
02448   *         contains the trigger configuration information
02449   * @retval HAL status
02450   */
02451 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef* hfdcan, FDCAN_TriggerTypeDef* sTriggerConfig)
02452 {
02453   uint32_t CycleCode;
02454   uint32_t MessageNumber;
02455   uint32_t TriggerElementW1;
02456   uint32_t TriggerElementW2;
02457   uint32_t *TriggerAddress;
02458
02459   /* Check function parameters */
02460   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
02461   assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TriggerIndex, 63));
02462   assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TimeMark, 0xFFFF));
02463   assert_param(IS_FDCAN_TT_REPEAT_FACTOR(sTriggerConfig->RepeatFactor));
02464   if(sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE)
02465   {
02466     assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->StartCycle, (sTriggerConfig->RepeatFactor - 1)));
02467   }
02468   assert_param(IS_FDCAN_TT_TM_EVENT_INTERNAL(sTriggerConfig->TmEventInt));
02469   assert_param(IS_FDCAN_TT_TM_EVENT_EXTERNAL(sTriggerConfig->TmEventExt));
02470   assert_param(IS_FDCAN_TT_TRIGGER_TYPE(sTriggerConfig->TriggerType));
02471   assert_param(IS_FDCAN_ID_TYPE(sTriggerConfig->FilterType));
02472   if((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE     ) ||
02473      (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) ||
02474      (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) ||
02475      (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED     ))
02476   {
02477     assert_param(IS_FDCAN_TX_LOCATION(sTriggerConfig->TxBufferIndex));
02478   }
02479   if(sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER)
02480   {
02481     if(sTriggerConfig->FilterType == FDCAN_STANDARD_ID)
02482     {
02483       assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 63));
02484     }
02485     else /* sTriggerConfig->FilterType == FDCAN_EXTENDED_ID */
02486     {
02487       assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 127));
02488     }
02489   }
02490
02491   if(hfdcan->State == HAL_FDCAN_STATE_READY)
02492   {
02493     /* Calculate cycle code */
02494     if(sTriggerConfig->RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE)
02495     {
02496       CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE;
02497     }
02498     else /* sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */
02499     {
02500       CycleCode = sTriggerConfig->RepeatFactor + sTriggerConfig->StartCycle;
02501     }
02502
02503     /* Build first word of trigger element */
02504     TriggerElementW1 = ((sTriggerConfig->TimeMark << 16) | \
02505                         (CycleCode << 8)                 | \
02506                         sTriggerConfig->TmEventInt       | \
02507                         sTriggerConfig->TmEventExt       | \
02508                         sTriggerConfig->TriggerType);
02509
02510     /* Select message number depending on trigger type (transmission or reception) */
02511     if(sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER)
02512     {
02513       MessageNumber = sTriggerConfig->FilterIndex;
02514     }
02515     else if((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE     ) ||
02516             (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) ||
02517             (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) ||
02518             (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED     ))
02519     {
02520       MessageNumber = POSITION_VAL(sTriggerConfig->TxBufferIndex);
02521     }
02522     else
02523     {
02524       MessageNumber = 0U;
02525     }
02526
02527     /* Build second word of trigger element */
02528     TriggerElementW2 = ((sTriggerConfig->FilterType >> 7) | (MessageNumber << 16));
02529
02530     /* Calculate trigger address */
02531     TriggerAddress = (uint32_t *)(hfdcan->msgRam.TTMemorySA + (sTriggerConfig->TriggerIndex * 4 * 2));
02532
02533     /* Write trigger element to the message RAM */
02534     *TriggerAddress++ = TriggerElementW1;
02535     *TriggerAddress = TriggerElementW2;
02536
02537     /* Return function status */
02538     return HAL_OK;
02539   }
02540   else
02541   {
02542     /* Update error code */
02543     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02544
02545     return HAL_ERROR;
02546   }
02547 }
02548
02549 /**
02550   * @brief  Schedule global time adjustment for the next reference message.
02551   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
02552   *         the configuration information for the specified FDCAN.
02553   * @param  TimePreset: time preset value.
02554   *                     This parameter must be a number between:
02555   *                      - 0x0000 and 0x7FFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark + TimePreset
02556   *                      or:
02557   *                      - 0x8001 and 0xFFFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark - (0x10000 - TimePreset)
02558   * @retval HAL status
02559   */
02560 HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef* hfdcan, uint32_t TimePreset)
02561 {
02562   uint32_t Counter = 0U;
02563
02564   /* Check function parameters */
02565   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
02566   assert_param(IS_FDCAN_TT_TIME_PRESET(TimePreset));
02567
02568   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
02569   {
02570     /* Check that the external clock synchronization is enabled */
02571     if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS)
02572     {
02573       /* Update error code */
02574       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
02575
02576       return HAL_ERROR;
02577     }
02578
02579     /* Check that no global time preset is pending */
02580     if((hfdcan->ttcan->TTOST & FDCAN_TTOST_WGTD) == FDCAN_TTOST_WGTD)
02581     {
02582       /* Update error code */
02583       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
02584
02585       return HAL_ERROR;
02586     }
02587
02588     /* Configure time preset */
02589     MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_TP, TimePreset);
02590
02591     /* Wait until the LCKC bit into TTOCN register is reset */
02592     while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
02593     {
02594       /* Check for the Timeout */
02595       if(Counter++ > FDCAN_TIMEOUT_VALUE)
02596       {
02597         /* Update error code */
02598         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
02599
02600         /* Change FDCAN state */
02601         hfdcan->State = HAL_FDCAN_STATE_ERROR;
02602
02603         return HAL_ERROR;
02604       }
02605     }
02606
02607     /* Schedule time preset to take effect by the next reference message */
02608     SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_SGT);
02609
02610     /* Return function status */
02611     return HAL_OK;
02612   }
02613   else
02614   {
02615     /* Update error code */
02616     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
02617
02618     return HAL_ERROR;
02619   }
02620 }
02621
02622 /**
02623   * @brief  Schedule TUR numerator update for the next reference message.
02624   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
02625   *         the configuration information for the specified FDCAN.
02626   * @param  NewTURNumerator: new value of the TUR numerator.
02627   *                          This parameter must be a number between 0x10000 and 0x1FFFF.
02628   * @retval HAL status
02629   */
02630 HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef* hfdcan, uint32_t NewTURNumerator)
02631 {
02632   uint32_t Counter = 0U;
02633
02634   /* Check function parameters */
02635   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
02636   assert_param(IS_FDCAN_TT_TUR_NUMERATOR(NewTURNumerator));
02637
02638   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
02639   {
02640     /* Check that the external clock synchronization is enabled */
02641     if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS)
02642     {
02643       /* Update error code */
02644       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
02645
02646       return HAL_ERROR;
02647     }
02648
02649     /* Check that no external clock synchronization is pending */
02650     if((hfdcan->ttcan->TTOST & FDCAN_TTOST_WECS) == FDCAN_TTOST_WECS)
02651     {
02652       /* Update error code */
02653       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
02654
02655       return HAL_ERROR;
02656     }
02657
02658     /* Configure new TUR numerator */
02659     MODIFY_REG(hfdcan->ttcan->TURCF, FDCAN_TURCF_NCL, (NewTURNumerator - 0x10000));
02660
02661     /* Wait until the LCKC bit into TTOCN register is reset */
02662     while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
02663     {
02664       /* Check for the Timeout */
02665       if(Counter++ > FDCAN_TIMEOUT_VALUE)
02666       {
02667         /* Update error code */
02668         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
02669
02670         /* Change FDCAN state */
02671         hfdcan->State = HAL_FDCAN_STATE_ERROR;
02672
02673         return HAL_ERROR;
02674       }
02675     }
02676
02677     /* Schedule TUR numerator update by the next reference message */
02678     SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ECS);
02679
02680     /* Return function status */
02681     return HAL_OK;
02682   }
02683   else
02684   {
02685     /* Update error code */
02686     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
02687
02688     return HAL_ERROR;
02689   }
02690 }
02691
02692 /**
02693   * @brief  Configure stop watch source and polarity.
02694   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
02695   *         the configuration information for the specified FDCAN.
02696   * @param  Source: stop watch source.
02697   *                 This parameter can be a value of @arg FDCAN_TT_stop_watch_source.
02698   * @param  Polarity: stop watch polarity.
02699   *                   This parameter can be a value of @arg FDCAN_TT_stop_watch_polarity.
02700   * @retval HAL status
02701   */
02702 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef* hfdcan, uint32_t Source, uint32_t Polarity)
02703 {
02704   uint32_t Counter = 0U;
02705
02706   /* Check function parameters */
02707   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
02708   assert_param(IS_FDCAN_TT_STOP_WATCH_SOURCE(Source));
02709   assert_param(IS_FDCAN_TT_STOP_WATCH_POLARITY(Polarity));
02710
02711   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
02712   {
02713     /* Wait until the LCKC bit into TTOCN register is reset */
02714     while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
02715     {
02716       /* Check for the Timeout */
02717       if(Counter++ > FDCAN_TIMEOUT_VALUE)
02718       {
02719         /* Update error code */
02720         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
02721
02722         /* Change FDCAN state */
02723         hfdcan->State = HAL_FDCAN_STATE_ERROR;
02724
02725         return HAL_ERROR;
02726       }
02727     }
02728
02729     /* Select stop watch source and polarity */
02730     MODIFY_REG(hfdcan->ttcan->TTOCN, (FDCAN_TTOCN_SWS | FDCAN_TTOCN_SWP), (Source | Polarity));
02731
02732     /* Return function status */
02733     return HAL_OK;
02734   }
02735   else
02736   {
02737     /* Update error code */
02738     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
02739
02740     return HAL_ERROR;
02741   }
02742 }
02743
02744 /**
02745   * @brief  Configure register time mark pulse generation.
02746   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
02747   *         the configuration information for the specified FDCAN.
02748   * @param  TimeMarkSource: time mark source.
02749   *                         This parameter can be a value of @arg FDCAN_TT_time_mark_source.
02750   * @param  TimeMarkValue: time mark value (reference).
02751   *                        This parameter must be a number between 0 and 0xFFFF.
02752   * @param  RepeatFactor: repeat factor of the cycle for which the time mark is valid.
02753   *                       This parameter can be a value of @arg FDCAN_TT_Repeat_Factor.
02754   * @param  StartCycle: index of the first cycle in which the time mark becomes valid.
02755   *                     This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
02756   *                     This parameter must be a number between 0 and RepeatFactor.
02757   * @retval HAL status
02758   */
02759 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef* hfdcan,
02760                                                      uint32_t TimeMarkSource, uint32_t TimeMarkValue,
02761                                                      uint32_t RepeatFactor, uint32_t StartCycle)
02762 {
02763   uint32_t Counter = 0U;
02764   uint32_t CycleCode;
02765
02766   /* Check function parameters */
02767   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
02768   assert_param(IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(TimeMarkSource));
02769   assert_param(IS_FDCAN_MAX_VALUE(TimeMarkValue, 0xFFFF));
02770   assert_param(IS_FDCAN_TT_REPEAT_FACTOR(RepeatFactor));
02771   if(RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE)
02772   {
02773     assert_param(IS_FDCAN_MAX_VALUE(StartCycle, (RepeatFactor - 1)));
02774   }
02775
02776   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
02777   {
02778     /* Wait until the LCKC bit into TTOCN register is reset */
02779     while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
02780     {
02781       /* Check for the Timeout */
02782       if(Counter++ > FDCAN_TIMEOUT_VALUE)
02783       {
02784         /* Update error code */
02785         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
02786
02787         /* Change FDCAN state */
02788         hfdcan->State = HAL_FDCAN_STATE_ERROR;
02789
02790         return HAL_ERROR;
02791       }
02792     }
02793
02794     /* Disable the time mark compare function */
02795     CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC);
02796
02797     if(TimeMarkSource != FDCAN_TT_REG_TIMEMARK_DIABLED)
02798     {
02799       /* Calculate cycle code */
02800       if(RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE)
02801       {
02802         CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE;
02803       }
02804       else /* RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */
02805       {
02806         CycleCode = RepeatFactor + StartCycle;
02807       }
02808
02809       Counter = 0U;
02810
02811       /* Wait until the LCKM bit into TTTMK register is reset */
02812       while((hfdcan->ttcan->TTTMK & FDCAN_TTTMK_LCKM) != RESET)
02813       {
02814         /* Check for the Timeout */
02815         if(Counter++ > FDCAN_TIMEOUT_VALUE)
02816         {
02817           /* Update error code */
02818           hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
02819
02820           /* Change FDCAN state */
02821           hfdcan->State = HAL_FDCAN_STATE_ERROR;
02822
02823           return HAL_ERROR;
02824         }
02825       }
02826
02827       /* Configure time mark value and cycle code */
02828       hfdcan->ttcan->TTTMK = (TimeMarkValue | (CycleCode << 16));
02829
02830       Counter = 0U;
02831
02832       /* Wait until the LCKC bit into TTOCN register is reset */
02833       while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
02834       {
02835         /* Check for the Timeout */
02836         if(Counter++ > FDCAN_TIMEOUT_VALUE)
02837         {
02838           /* Update error code */
02839           hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
02840
02841           /* Change FDCAN state */
02842           hfdcan->State = HAL_FDCAN_STATE_ERROR;
02843
02844           return HAL_ERROR;
02845         }
02846       }
02847
02848       /* Update the register time mark compare source */
02849       MODIFY_REG(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC, TimeMarkSource);
02850     }
02851
02852     /* Return function status */
02853     return HAL_OK;
02854   }
02855   else
02856   {
02857     /* Update error code */
02858     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
02859
02860     return HAL_ERROR;
02861   }
02862 }
02863
02864 /**
02865   * @brief  Enable register time mark pulse generation.
02866   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
02867   *         the configuration information for the specified FDCAN.
02868   * @retval HAL status
02869   */
02870 HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
02871 {
02872   uint32_t Counter = 0U;
02873
02874   /* Check function parameters */
02875   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
02876
02877   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
02878   {
02879     /* Wait until the LCKC bit into TTOCN register is reset */
02880     while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
02881     {
02882       /* Check for the Timeout */
02883       if(Counter++ > FDCAN_TIMEOUT_VALUE)
02884       {
02885         /* Update error code */
02886         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
02887
02888         /* Change FDCAN state */
02889         hfdcan->State = HAL_FDCAN_STATE_ERROR;
02890
02891         return HAL_ERROR;
02892       }
02893     }
02894
02895     /* Enable Register Time Mark Interrupt output on fdcan1_rtp */
02896     SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE);
02897
02898     /* Return function status */
02899     return HAL_OK;
02900   }
02901   else
02902   {
02903     /* Update error code */
02904     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
02905
02906     return HAL_ERROR;
02907   }
02908 }
02909
02910 /**
02911   * @brief  Disable register time mark pulse generation.
02912   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
02913   *         the configuration information for the specified FDCAN.
02914   * @retval HAL status
02915   */
02916 HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
02917 {
02918   uint32_t Counter = 0U;
02919
02920   /* Check function parameters */
02921   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
02922
02923   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
02924   {
02925     /* Wait until the LCKC bit into TTOCN register is reset */
02926     while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
02927     {
02928       /* Check for the Timeout */
02929       if(Counter++ > FDCAN_TIMEOUT_VALUE)
02930       {
02931         /* Update error code */
02932         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
02933
02934         /* Change FDCAN state */
02935         hfdcan->State = HAL_FDCAN_STATE_ERROR;
02936
02937         return HAL_ERROR;
02938       }
02939     }
02940
02941     /* Disable Register Time Mark Interrupt output on fdcan1_rtp */
02942     CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE);
02943
02944     /* Return function status */
02945     return HAL_OK;
02946   }
02947   else
02948   {
02949     /* Update error code */
02950     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
02951
02952     return HAL_ERROR;
02953   }
02954 }
02955
02956 /**
02957   * @brief  Enable trigger time mark pulse generation.
02958   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
02959   *         the configuration information for the specified FDCAN.
02960   * @retval HAL status
02961   */
02962 HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
02963 {
02964   uint32_t Counter = 0U;
02965
02966   /* Check function parameters */
02967   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
02968
02969   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
02970   {
02971     if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
02972     {
02973       /* Wait until the LCKC bit into TTOCN register is reset */
02974       while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
02975       {
02976         /* Check for the Timeout */
02977         if(Counter++ > FDCAN_TIMEOUT_VALUE)
02978         {
02979           /* Update error code */
02980           hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
02981
02982           /* Change FDCAN state */
02983           hfdcan->State = HAL_FDCAN_STATE_ERROR;
02984
02985           return HAL_ERROR;
02986         }
02987       }
02988
02989       /* Enable Trigger Time Mark Interrupt output on fdcan1_tmp */
02990       SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE);
02991
02992       /* Return function status */
02993       return HAL_OK;
02994     }
02995     else
02996     {
02997       /* Update error code.
02998          Feature not supported for TT Level 0 */
02999       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
03000
03001       return HAL_ERROR;
03002     }
03003   }
03004   else
03005   {
03006     /* Update error code */
03007     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
03008
03009     return HAL_ERROR;
03010   }
03011 }
03012
03013 /**
03014   * @brief  Disable trigger time mark pulse generation.
03015   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
03016   *         the configuration information for the specified FDCAN.
03017   * @retval HAL status
03018   */
03019 HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
03020 {
03021   uint32_t Counter = 0U;
03022
03023   /* Check function parameters */
03024   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
03025
03026   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
03027   {
03028     if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
03029     {
03030       /* Wait until the LCKC bit into TTOCN register is reset */
03031       while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
03032       {
03033         /* Check for the Timeout */
03034         if(Counter++ > FDCAN_TIMEOUT_VALUE)
03035         {
03036           /* Update error code */
03037           hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
03038
03039           /* Change FDCAN state */
03040           hfdcan->State = HAL_FDCAN_STATE_ERROR;
03041
03042           return HAL_ERROR;
03043         }
03044       }
03045
03046       /* Disable Trigger Time Mark Interrupt output on fdcan1_rtp */
03047       CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE);
03048
03049       /* Return function status */
03050       return HAL_OK;
03051     }
03052     else
03053     {
03054       /* Update error code.
03055          Feature not supported for TT Level 0 */
03056       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
03057
03058       return HAL_ERROR;
03059     }
03060   }
03061   else
03062   {
03063     /* Update error code */
03064     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
03065
03066     return HAL_ERROR;
03067   }
03068 }
03069
03070 /**
03071   * @brief  Enable gap control by input pin fdcan1_evt.
03072   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
03073   *         the configuration information for the specified FDCAN.
03074   * @retval HAL status
03075   */
03076 HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan)
03077 {
03078   uint32_t Counter = 0U;
03079
03080   /* Check function parameters */
03081   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
03082
03083   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
03084   {
03085     if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
03086     {
03087       /* Wait until the LCKC bit into TTOCN register is reset */
03088       while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
03089       {
03090         /* Check for the Timeout */
03091         if(Counter++ > FDCAN_TIMEOUT_VALUE)
03092         {
03093           /* Update error code */
03094           hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
03095
03096           /* Change FDCAN state */
03097           hfdcan->State = HAL_FDCAN_STATE_ERROR;
03098
03099           return HAL_ERROR;
03100         }
03101       }
03102
03103       /* Enable gap control by pin fdcan1_evt */
03104       SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS);
03105
03106       /* Return function status */
03107       return HAL_OK;
03108     }
03109     else
03110     {
03111       /* Update error code.
03112          Feature not supported for TT Level 0 */
03113       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
03114
03115       return HAL_ERROR;
03116     }
03117   }
03118   else
03119   {
03120     /* Update error code */
03121     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
03122
03123     return HAL_ERROR;
03124   }
03125 }
03126
03127 /**
03128   * @brief  Disable gap control by input pin fdcan1_evt.
03129   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
03130   *         the configuration information for the specified FDCAN.
03131   * @retval HAL status
03132   */
03133 HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan)
03134 {
03135   uint32_t Counter = 0U;
03136
03137   /* Check function parameters */
03138   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
03139
03140   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
03141   {
03142     if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
03143     {
03144       /* Wait until the LCKC bit into TTOCN register is reset */
03145       while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
03146       {
03147         /* Check for the Timeout */
03148         if(Counter++ > FDCAN_TIMEOUT_VALUE)
03149         {
03150           /* Update error code */
03151           hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
03152
03153           /* Change FDCAN state */
03154           hfdcan->State = HAL_FDCAN_STATE_ERROR;
03155
03156           return HAL_ERROR;
03157         }
03158       }
03159
03160       /* Disable gap control by pin fdcan1_evt */
03161       CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS);
03162
03163       /* Return function status */
03164       return HAL_OK;
03165     }
03166     else
03167     {
03168       /* Update error code.
03169          Feature not supported for TT Level 0 */
03170       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
03171
03172       return HAL_ERROR;
03173     }
03174   }
03175   else
03176   {
03177     /* Update error code */
03178     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
03179
03180     return HAL_ERROR;
03181   }
03182 }
03183
03184 /**
03185   * @brief  Enable gap control (finish only) by register time mark interrupt.
03186   *         The next register time mark interrupt (TTIR.RTMI = "1") will finish
03187   *         the Gap and start the reference message.
03188   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
03189   *         the configuration information for the specified FDCAN.
03190   * @retval HAL status
03191   */
03192 HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan)
03193 {
03194   uint32_t Counter = 0U;
03195
03196   /* Check function parameters */
03197   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
03198
03199   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
03200   {
03201     if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
03202     {
03203       /* Wait until the LCKC bit into TTOCN register is reset */
03204       while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
03205       {
03206         /* Check for the Timeout */
03207         if(Counter++ > FDCAN_TIMEOUT_VALUE)
03208         {
03209           /* Update error code */
03210           hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
03211
03212           /* Change FDCAN state */
03213           hfdcan->State = HAL_FDCAN_STATE_ERROR;
03214
03215           return HAL_ERROR;
03216         }
03217       }
03218
03219       /* Enable gap control by register time mark interrupt */
03220       SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG);
03221
03222       /* Return function status */
03223       return HAL_OK;
03224     }
03225     else
03226     {
03227       /* Update error code.
03228          Feature not supported for TT Level 0 */
03229       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
03230
03231       return HAL_ERROR;
03232     }
03233   }
03234   else
03235   {
03236     /* Update error code */
03237     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
03238
03239     return HAL_ERROR;
03240   }
03241 }
03242
03243 /**
03244   * @brief  Disable gap control by register time mark interrupt.
03245   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
03246   *         the configuration information for the specified FDCAN.
03247   * @retval HAL status
03248   */
03249 HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan)
03250 {
03251   uint32_t Counter = 0U;
03252
03253   /* Check function parameters */
03254   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
03255
03256   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
03257   {
03258     if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
03259     {
03260       /* Wait until the LCKC bit into TTOCN register is reset */
03261       while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
03262       {
03263         /* Check for the Timeout */
03264         if(Counter++ > FDCAN_TIMEOUT_VALUE)
03265         {
03266           /* Update error code */
03267           hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
03268
03269           /* Change FDCAN state */
03270           hfdcan->State = HAL_FDCAN_STATE_ERROR;
03271
03272           return HAL_ERROR;
03273         }
03274       }
03275
03276       /* Disable gap control by register time mark interrupt */
03277       CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG);
03278
03279       /* Return function status */
03280       return HAL_OK;
03281     }
03282     else
03283     {
03284       /* Update error code.
03285          Feature not supported for TT Level 0 */
03286       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
03287
03288       return HAL_ERROR;
03289     }
03290   }
03291   else
03292   {
03293     /* Update error code */
03294     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
03295
03296     return HAL_ERROR;
03297   }
03298 }
03299
03300 /**
03301   * @brief  Transmit next reference message with Next_is_Gap = "1".
03302   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
03303   *         the configuration information for the specified FDCAN.
03304   * @retval HAL status
03305   */
03306 HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan)
03307 {
03308   uint32_t Counter = 0U;
03309
03310   /* Check function parameters */
03311   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
03312
03313   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
03314   {
03315     /* Check that the node is configured for external event-synchronized TT operation */
03316     if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN)
03317     {
03318       /* Update error code */
03319       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
03320
03321       return HAL_ERROR;
03322     }
03323
03324     if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
03325     {
03326       /* Wait until the LCKC bit into TTOCN register is reset */
03327       while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
03328       {
03329         /* Check for the Timeout */
03330         if(Counter++ > FDCAN_TIMEOUT_VALUE)
03331         {
03332           /* Update error code */
03333           hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
03334
03335           /* Change FDCAN state */
03336           hfdcan->State = HAL_FDCAN_STATE_ERROR;
03337
03338           return HAL_ERROR;
03339         }
03340       }
03341
03342       /* Set Next is Gap */
03343       SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_NIG);
03344
03345       /* Return function status */
03346       return HAL_OK;
03347     }
03348     else
03349     {
03350       /* Update error code.
03351          Feature not supported for TT Level 0 */
03352       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
03353
03354       return HAL_ERROR;
03355     }
03356   }
03357   else
03358   {
03359     /* Update error code */
03360     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
03361
03362     return HAL_ERROR;
03363   }
03364 }
03365
03366 /**
03367   * @brief  Finish a Gap by requesting start of reference message.
03368   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
03369   *         the configuration information for the specified FDCAN.
03370   * @retval HAL status
03371   */
03372 HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan)
03373 {
03374   uint32_t Counter = 0U;
03375
03376   /* Check function parameters */
03377   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
03378
03379   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
03380   {
03381     /* Check that the node is configured for external event-synchronized TT operation */
03382     if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN)
03383     {
03384       /* Update error code */
03385       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
03386
03387       return HAL_ERROR;
03388     }
03389
03390     if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
03391     {
03392       /* Wait until the LCKC bit into TTOCN register is reset */
03393       while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
03394       {
03395         /* Check for the Timeout */
03396         if(Counter++ > FDCAN_TIMEOUT_VALUE)
03397         {
03398           /* Update error code */
03399           hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
03400
03401           /* Change FDCAN state */
03402           hfdcan->State = HAL_FDCAN_STATE_ERROR;
03403
03404           return HAL_ERROR;
03405         }
03406       }
03407
03408       /* Set Finish Gap */
03409       SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_FGP);
03410
03411       /* Return function status */
03412       return HAL_OK;
03413     }
03414     else
03415     {
03416       /* Update error code.
03417          Feature not supported for TT Level 0 */
03418       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
03419
03420       return HAL_ERROR;
03421     }
03422   }
03423   else
03424   {
03425     /* Update error code */
03426     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
03427
03428     return HAL_ERROR;
03429   }
03430 }
03431
03432 /**
03433   * @brief  Configure target phase used for external synchronization by event
03434   *         trigger input pin fdcan1_evt.
03435   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
03436   *         the configuration information for the specified FDCAN.
03437   * @param  TargetPhase: defines target value of cycle time when a rising edge
03438   *                      of fdcan1_evt is expected.
03439   *                      This parameter must be a number between 0 and 0xFFFF.
03440   * @retval HAL status
03441   */
03442 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase)
03443 {
03444   /* Check function parameters */
03445   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
03446   assert_param(IS_FDCAN_MAX_VALUE(TargetPhase, 0xFFFF));
03447
03448   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
03449   {
03450     /* Check that no external schedule synchronization is pending */
03451     if((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_ESCN) == FDCAN_TTOCN_ESCN)
03452     {
03453       /* Update error code */
03454       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
03455
03456       return HAL_ERROR;
03457     }
03458
03459     /* Configure cycle time target phase */
03460     MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_CTP, (TargetPhase << 16));
03461
03462     /* Return function status */
03463     return HAL_OK;
03464   }
03465   else
03466   {
03467     /* Update error code */
03468     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
03469
03470     return HAL_ERROR;
03471   }
03472 }
03473
03474 /**
03475   * @brief  Synchronize the phase of the FDCAN schedule to an external schedule
03476   *         using event trigger input pin fdcan1_evt.
03477   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
03478   *         the configuration information for the specified FDCAN.
03479   * @retval HAL status
03480   */
03481 HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan)
03482 {
03483   uint32_t Counter = 0U;
03484
03485   /* Check function parameters */
03486   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
03487
03488   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
03489   {
03490     /* Wait until the LCKC bit into TTOCN register is reset */
03491     while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
03492     {
03493       /* Check for the Timeout */
03494       if(Counter++ > FDCAN_TIMEOUT_VALUE)
03495       {
03496         /* Update error code */
03497         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
03498
03499         /* Change FDCAN state */
03500         hfdcan->State = HAL_FDCAN_STATE_ERROR;
03501
03502         return HAL_ERROR;
03503       }
03504     }
03505
03506     /* Enable external synchronization */
03507     SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN);
03508
03509     /* Return function status */
03510     return HAL_OK;
03511   }
03512   else
03513   {
03514     /* Update error code */
03515     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
03516
03517     return HAL_ERROR;
03518   }
03519 }
03520
03521 /**
03522   * @brief  Disable external schedule synchronization.
03523   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
03524   *         the configuration information for the specified FDCAN.
03525   * @retval HAL status
03526   */
03527 HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan)
03528 {
03529   uint32_t Counter = 0U;
03530
03531   /* Check function parameters */
03532   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
03533
03534   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
03535   {
03536     /* Wait until the LCKC bit into TTOCN register is reset */
03537     while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
03538     {
03539       /* Check for the Timeout */
03540       if(Counter++ > FDCAN_TIMEOUT_VALUE)
03541       {
03542         /* Update error code */
03543         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
03544
03545         /* Change FDCAN state */
03546         hfdcan->State = HAL_FDCAN_STATE_ERROR;
03547
03548         return HAL_ERROR;
03549       }
03550     }
03551
03552     /* Disable external synchronization */
03553     CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN);
03554
03555     /* Return function status */
03556     return HAL_OK;
03557   }
03558   else
03559   {
03560     /* Update error code */
03561     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
03562
03563     return HAL_ERROR;
03564   }
03565 }
03566
03567 /**
03568   * @brief  Get TT operation status.
03569   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
03570   *         the configuration information for the specified FDCAN.
03571   * @param  TTOpStatus: pointer to an FDCAN_TTOperationStatusTypeDef structure.
03572   * @retval HAL status
03573   */
03574 HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus)
03575 {
03576   uint32_t TTStatusReg;
03577
03578   /* Check function parameters */
03579   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
03580
03581   /* Read the TT operation status register */
03582   TTStatusReg = READ_REG(hfdcan->ttcan->TTOST);
03583
03584   /* Fill the TT operation status structure */
03585   TTOpStatus->ErrorLevel = (TTStatusReg & FDCAN_TTOST_EL);
03586   TTOpStatus->MasterState =  (TTStatusReg & FDCAN_TTOST_MS);
03587   TTOpStatus->SyncState =  (TTStatusReg & FDCAN_TTOST_SYS);
03588   TTOpStatus->GTimeQuality =  ((TTStatusReg & FDCAN_TTOST_QGTP) >> 6);
03589   TTOpStatus->ClockQuality =  ((TTStatusReg & FDCAN_TTOST_QCS) >> 7);
03590   TTOpStatus->RefTrigOffset =  ((TTStatusReg & FDCAN_TTOST_RTO) >> 8);
03591   TTOpStatus->GTimeDiscPending =  ((TTStatusReg & FDCAN_TTOST_WGTD) >> 22);
03592   TTOpStatus->GapFinished =  ((TTStatusReg & FDCAN_TTOST_GFI) >> 23);
03593   TTOpStatus->MasterPriority =  ((TTStatusReg & FDCAN_TTOST_TMP) >> 24);
03594   TTOpStatus->GapStarted =  ((TTStatusReg & FDCAN_TTOST_GSI) >> 27);
03595   TTOpStatus->WaitForEvt =  ((TTStatusReg & FDCAN_TTOST_WFE) >> 28);
03596   TTOpStatus->AppWdgEvt =  ((TTStatusReg & FDCAN_TTOST_AWE) >> 29);
03597   TTOpStatus->ECSPending =  ((TTStatusReg & FDCAN_TTOST_WECS) >> 30);
03598   TTOpStatus->PhaseLock =  ((TTStatusReg & FDCAN_TTOST_SPL) >> 31);
03599
03600   /* Return function status */
03601   return HAL_OK;
03602 }
03603
03604 /**
03605   * @}
03606   */
03607
03608 /** @defgroup FDCAN_Exported_Functions_Group5 Interrupts management
03609  *  @brief    Interrupts management
03610  *
03611 @verbatim
03612   ==============================================================================
03613                        ##### Interrupts management #####
03614   ==============================================================================
03615     [..]  This section provides functions allowing to:
03616       (+) HAL_FDCAN_ConfigInterruptLines      : Assign interrupts to either Interrupt line 0 or 1
03617       (+) HAL_FDCAN_TT_ConfigInterruptLines   : Assign TT interrupts to either Interrupt line 0 or 1
03618       (+) HAL_FDCAN_ActivateNotification      : Enable interrupts
03619       (+) HAL_FDCAN_DeactivateNotification    : Disable interrupts
03620       (+) HAL_FDCAN_TT_ActivateNotification   : Enable TT interrupts
03621       (+) HAL_FDCAN_TT_DeactivateNotification : Disable TT interrupts
03622       (+) HAL_FDCAN_IRQHandler                : Handles FDCAN interrupt request
03623
03624 @endverbatim
03625   * @{
03626   */
03627
03628 /**
03629   * @brief  Assign interrupts to either Interrupt line 0 or 1.
03630   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
03631   *         the configuration information for the specified FDCAN.
03632   * @param  ITList: indicates which interrupts will be assigned to the selected interrupt line.
03633   *                 This parameter can be any combination of @arg FDCAN_Interrupts.
03634   * @param  InterruptLine: Interrupt line.
03635   *                        This parameter can be a value of @arg FDCAN_Interrupt_Line.
03636   * @retval HAL status
03637   */
03638 HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
03639 {
03640   /* Check function parameters */
03641   assert_param(IS_FDCAN_IT(ITList));
03642   assert_param(IS_FDCAN_IT_LINE(InterruptLine));
03643
03644   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
03645   {
03646     /* Assign list of interrupts to the selected line */
03647     if(InterruptLine == FDCAN_INTERRUPT_LINE0)
03648     {
03649       CLEAR_BIT(hfdcan->Instance->ILS, ITList);
03650     }
03651     else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
03652     {
03653       SET_BIT(hfdcan->Instance->ILS, ITList);
03654     }
03655
03656     /* Return function status */
03657     return HAL_OK;
03658   }
03659   else
03660   {
03661     /* Update error code */
03662     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
03663
03664     return HAL_ERROR;
03665   }
03666 }
03667
03668 /**
03669   * @brief  Assign TT interrupts to either Interrupt line 0 or 1.
03670   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
03671   *         the configuration information for the specified FDCAN.
03672   * @param  TTITList: indicates which interrupts will be assigned to the selected interrupt line.
03673   *                   This parameter can be any combination of @arg FDCAN_TTInterrupts.
03674   * @param  InterruptLine: Interrupt line.
03675   *                        This parameter can be a value of @arg FDCAN_Interrupt_Line.
03676   * @retval HAL status
03677   */
03678 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine)
03679 {
03680   /* Check function parameters */
03681   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
03682   assert_param(IS_FDCAN_TT_IT(TTITList));
03683   assert_param(IS_FDCAN_IT_LINE(InterruptLine));
03684
03685   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
03686   {
03687     /* Assign list of interrupts to the selected line */
03688     if(InterruptLine == FDCAN_INTERRUPT_LINE0)
03689     {
03690       CLEAR_BIT(hfdcan->ttcan->TTILS, TTITList);
03691     }
03692     else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
03693     {
03694       SET_BIT(hfdcan->ttcan->TTILS, TTITList);
03695     }
03696
03697     /* Return function status */
03698     return HAL_OK;
03699   }
03700   else
03701   {
03702     /* Update error code */
03703     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
03704
03705     return HAL_ERROR;
03706   }
03707 }
03708
03709 /**
03710   * @brief  Enable interrupts.
03711   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
03712   *         the configuration information for the specified FDCAN.
03713   * @param  ActiveITs: indicates which interrupts will be enabled.
03714   *                    This parameter can be any combination of @arg FDCAN_Interrupts.
03715   * @param  BufferIndexes: Tx Buffer Indexes.
03716   *                        This parameter can be any combination of @arg FDCAN_Tx_location.
03717   *                        This parameter is ignored if ActiveITs does not include one of the following:
03718   *                         - FDCAN_IT_TX_COMPLETE
03719   *                         - FDCAN_IT_TX_ABORT_COMPLETE
03720   * @retval HAL status
03721   */
03722 HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
03723 {
03724   /* Check function parameters */
03725   assert_param(IS_FDCAN_IT(ActiveITs));
03726
03727   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
03728   {
03729     /* Enable Interrupt lines */
03730     if((ActiveITs & hfdcan->Instance->ILS) == RESET)
03731     {
03732       /* Enable Interrupt line 0 */
03733       SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
03734     }
03735     else if((ActiveITs & hfdcan->Instance->ILS) == ActiveITs)
03736     {
03737       /* Enable Interrupt line 1 */
03738       SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
03739     }
03740     else
03741     {
03742       /* Enable Interrupt lines 0 and 1 */
03743       hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
03744     }
03745
03746     if((ActiveITs & FDCAN_IT_TX_COMPLETE) != RESET)
03747     {
03748       /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register,
03749          but interrupt will only occure if TC is enabled in IE register */
03750       SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes);
03751     }
03752
03753     if((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != RESET)
03754     {
03755       /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register,
03756          but interrupt will only occure if TCF is enabled in IE register */
03757       SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes);
03758     }
03759
03760     /* Enable the selected interrupts */
03761     __HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs);
03762
03763     /* Return function status */
03764     return HAL_OK;
03765   }
03766   else
03767   {
03768     /* Update error code */
03769     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
03770
03771     return HAL_ERROR;
03772   }
03773 }
03774
03775 /**
03776   * @brief  Disable interrupts.
03777   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
03778   *         the configuration information for the specified FDCAN.
03779   * @param  InactiveITs: indicates which interrupts will be disabled.
03780   *                      This parameter can be any combination of @arg FDCAN_Interrupts.
03781   * @retval HAL status
03782   */
03783 HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
03784 {
03785   /* Check function parameters */
03786   assert_param(IS_FDCAN_IT(InactiveITs));
03787
03788   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
03789   {
03790     /* Disable the selected interrupts */
03791     __HAL_FDCAN_DISABLE_IT(hfdcan, InactiveITs);
03792
03793     /* Return function status */
03794     return HAL_OK;
03795   }
03796   else
03797   {
03798     /* Update error code */
03799     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
03800
03801     return HAL_ERROR;
03802   }
03803 }
03804
03805 /**
03806   * @brief  Enable TT interrupts.
03807   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
03808   *         the configuration information for the specified FDCAN.
03809   * @param  ActiveTTITs: indicates which TT interrupts will be enabled.
03810   *                      This parameter can be any combination of @arg FDCAN_TTInterrupts.
03811   * @retval HAL status
03812   */
03813 HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs)
03814 {
03815   /* Check function parameters */
03816   assert_param(IS_FDCAN_TT_IT(ActiveTTITs));
03817
03818   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
03819   {
03820     /* Enable Interrupt lines */
03821     if((ActiveTTITs & hfdcan->ttcan->TTILS) == RESET)
03822     {
03823       /* Enable Interrupt line 0 */
03824       SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
03825     }
03826     else if((ActiveTTITs & hfdcan->ttcan->TTILS) == ActiveTTITs)
03827     {
03828       /* Enable Interrupt line 1 */
03829       SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
03830     }
03831     else
03832     {
03833       /* Enable Interrupt lines 0 and 1 */
03834       hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
03835     }
03836
03837     /* Enable the selected TT interrupts */
03838     __HAL_FDCAN_TT_ENABLE_IT(hfdcan, ActiveTTITs);
03839
03840     /* Return function status */
03841     return HAL_OK;
03842   }
03843   else
03844   {
03845     /* Update error code */
03846     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
03847
03848     return HAL_ERROR;
03849   }
03850 }
03851
03852 /**
03853   * @brief  Disable TT interrupts.
03854   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
03855   *         the configuration information for the specified FDCAN.
03856   * @param  InactiveTTITs: indicates which TT interrupts will be disabled.
03857   *                        This parameter can be any combination of @arg FDCAN_TTInterrupts.
03858   * @retval HAL status
03859   */
03860 HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs)
03861 {
03862   /* Check function parameters */
03863   assert_param(IS_FDCAN_TT_IT(InactiveTTITs));
03864
03865   if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
03866   {
03867     /* Disable the selected TT interrupts */
03868     __HAL_FDCAN_TT_DISABLE_IT(hfdcan, InactiveTTITs);
03869
03870     /* Return function status */
03871     return HAL_OK;
03872   }
03873   else
03874   {
03875     /* Update error code */
03876     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
03877
03878     return HAL_ERROR;
03879   }
03880 }
03881
03882 /**
03883   * @brief  Handles FDCAN interrupt request.
03884   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
03885   *         the configuration information for the specified FDCAN.
03886   * @retval HAL status
03887   */
03888 void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
03889 {
03890   uint32_t ClkCalibrationITs;
03891   uint32_t TxEventFifoITs;
03892   uint32_t RxFifo0ITs;
03893   uint32_t RxFifo1ITs;
03894   uint32_t ErrStatus;
03895   uint32_t TransmittedBuffers;
03896   uint32_t AbortedBuffers;
03897   uint32_t TTSchedSyncITs;
03898   uint32_t TTTimeMarkITs;
03899   uint32_t TTGlobTimeITs;
03900   uint32_t TTDistErrors;
03901   uint32_t TTFatalErrors;
03902   uint32_t SWTime;
03903   uint32_t SWCycleCount;
03904
03905   ClkCalibrationITs = (FDCAN_CCU->IR << 30);
03906   ClkCalibrationITs &= (FDCAN_CCU->IE << 30);
03907   TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK;
03908   TxEventFifoITs &= hfdcan->Instance->IE;
03909   RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK;
03910   RxFifo0ITs &= hfdcan->Instance->IE;
03911   RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK;
03912   RxFifo1ITs &= hfdcan->Instance->IE;
03913   ErrStatus = hfdcan->Instance->IR & FDCAN_ERROR_MASK;
03914   ErrStatus &= hfdcan->Instance->IE;
03915
03916   /* High Priority Message interrupt management *******************************/
03917   if(__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET)
03918   {
03919     if(__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != RESET)
03920     {
03921       /* Disable the High Priority Message interrupt */
03922       __HAL_FDCAN_DISABLE_IT(hfdcan, FDCAN_IT_RX_HIGH_PRIORITY_MSG);
03923
03924       /* Clear the High Priority Message flag */
03925       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
03926
03927       /* High Priority Message Callback */
03928       HAL_FDCAN_HighPriorityMessageCallback(hfdcan);
03929     }
03930   }
03931
03932   /* Transmission Abort interrupt management **********************************/
03933   if(__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET)
03934   {
03935     if(__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_ABORT_COMPLETE) != RESET)
03936     {
03937       /* Disable the Transmission Cancellation interrupt */
03938       __HAL_FDCAN_DISABLE_IT(hfdcan, FDCAN_IT_TX_ABORT_COMPLETE);
03939
03940       /* List of aborted monitored buffers */
03941       AbortedBuffers = hfdcan->Instance->TXBCF;
03942       AbortedBuffers &= hfdcan->Instance->TXBCIE;
03943
03944       /* Disable the Tx Buffer Cancellation Finished Interrupt */
03945       CLEAR_BIT(hfdcan->Instance->TXBCIE, AbortedBuffers);
03946
03947       /* Clear the Transmission Cancellation flag */
03948       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE);
03949
03950       /* Transmission Cancellation Callback */
03951       HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers);
03952     }
03953   }
03954
03955   /* Clock calibration unit interrupts management *****************************/
03956   if(ClkCalibrationITs != 0U)
03957   {
03958     /* Disable the Clock Calibration interrupts */
03959     __HAL_FDCAN_DISABLE_IT(hfdcan, ClkCalibrationITs);
03960
03961     /* Clear the Clock Calibration flags */
03962     __HAL_FDCAN_CLEAR_FLAG(hfdcan, ClkCalibrationITs);
03963
03964     /* Clock Calibration Callback */
03965     HAL_FDCAN_ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
03966   }
03967
03968   /* Tx event FIFO interrupts management **************************************/
03969   if(TxEventFifoITs != 0U)
03970   {
03971     /* Disable the Tx Event FIFO interrupts */
03972     __HAL_FDCAN_DISABLE_IT(hfdcan, TxEventFifoITs);
03973
03974     /* Clear the Tx Event FIFO flags */
03975     __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs);
03976
03977     /* Tx Event FIFO Callback */
03978     HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs);
03979   }
03980
03981   /* Rx FIFO 0 interrupts management ******************************************/
03982   if(RxFifo0ITs != 0U)
03983   {
03984     /* Disable the Rx FIFO 0 interrupts */
03985     __HAL_FDCAN_DISABLE_IT(hfdcan, RxFifo0ITs);
03986
03987     /* Clear the Rx FIFO 0 flags */
03988     __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs);
03989
03990     /* Rx FIFO 0 Callback */
03991     HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs);
03992   }
03993
03994   /* Rx FIFO 1 interrupts management ******************************************/
03995   if(RxFifo1ITs != 0U)
03996   {
03997     /* Disable the Rx FIFO 1 interrupts */
03998     __HAL_FDCAN_DISABLE_IT(hfdcan, RxFifo1ITs);
03999
04000     /* Clear the Rx FIFO 1 flags */
04001     __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs);
04002
04003     /* Rx FIFO 1 Callback */
04004     HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs);
04005   }
04006
04007   /* Tx FIFO empty interrupt management ***************************************/
04008   if(__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET)
04009   {
04010     if(__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_FIFO_EMPTY) != RESET)
04011     {
04012       /* Disable the Tx FIFO empty interrupt */
04013       __HAL_FDCAN_DISABLE_IT(hfdcan, FDCAN_IT_TX_FIFO_EMPTY);
04014
04015       /* Clear the Tx FIFO empty flag */
04016       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
04017
04018       /* Tx FIFO empty Callback */
04019       HAL_FDCAN_TxFifoEmptyCallback(hfdcan);
04020     }
04021   }
04022
04023   /* Transmission Complete interrupt management *******************************/
04024   if(__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE) != RESET)
04025   {
04026     if(__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_COMPLETE) != RESET)
04027     {
04028       /* Disable the Transmission Complete interrupt */
04029       __HAL_FDCAN_DISABLE_IT(hfdcan, FDCAN_IT_TX_COMPLETE);
04030
04031       /* List of transmitted monitored buffers */
04032       TransmittedBuffers = hfdcan->Instance->TXBTO;
04033       TransmittedBuffers &= hfdcan->Instance->TXBTIE;
04034
04035       /* Disable the Tx Buffer Transmission Interrupt */
04036       CLEAR_BIT(hfdcan->Instance->TXBTIE, TransmittedBuffers);
04037
04038       /* Clear the Transmission Complete flag */
04039       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE);
04040
04041       /* Transmission Complete Callback */
04042       HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
04043     }
04044   }
04045
04046   /* Rx Buffer New Message interrupt management *******************************/
04047   if(__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != RESET)
04048   {
04049     if(__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != RESET)
04050     {
04051       /* Disable the Rx Buffer New Message interrupt */
04052       __HAL_FDCAN_DISABLE_IT(hfdcan, FDCAN_IT_RX_BUFFER_NEW_MESSAGE);
04053
04054       /* Clear the Rx Buffer New Message flag */
04055       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE);
04056
04057       /* Rx Buffer New Message Callback */
04058       HAL_FDCAN_RxBufferNewMessageCallback(hfdcan);
04059     }
04060   }
04061
04062   /* Timestamp Wraparound interrupt management ********************************/
04063   if(__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET)
04064   {
04065     if(__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMESTAMP_WRAPAROUND) != RESET)
04066     {
04067       /* Disable the Timestamp Wraparound interrupt */
04068       __HAL_FDCAN_DISABLE_IT(hfdcan, FDCAN_IT_TIMESTAMP_WRAPAROUND);
04069
04070       /* Clear the Timestamp Wraparound flag */
04071       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
04072
04073       /* Timestamp Wraparound Callback */
04074       HAL_FDCAN_TimestampWraparoundCallback(hfdcan);
04075     }
04076   }
04077
04078   /* Timeout Occurred interrupt management ************************************/
04079   if(__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET)
04080   {
04081     if(__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMEOUT_OCCURRED) != RESET)
04082     {
04083       /* Disable the Timeout Occurred interrupt */
04084       __HAL_FDCAN_DISABLE_IT(hfdcan, FDCAN_IT_TIMEOUT_OCCURRED);
04085
04086       /* Clear the Timeout Occurred flag */
04087       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
04088
04089       /* Timeout Occurred Callback */
04090       HAL_FDCAN_TimeoutOccurredCallback(hfdcan);
04091     }
04092   }
04093
04094   /* Message RAM access failure interrupt management **************************/
04095   if(__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET)
04096   {
04097     if(__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET)
04098     {
04099       /* Disable the Timeout Occurred interrupt */
04100       __HAL_FDCAN_DISABLE_IT(hfdcan, FDCAN_IT_RAM_ACCESS_FAILURE);
04101
04102       /* Clear the Timeout Occurred flag */
04103       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
04104
04105       /* Update error code */
04106       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS;
04107     }
04108   }
04109
04110   /* Error interrupts management **********************************************/
04111   if(ErrStatus != 0U)
04112   {
04113     /* Disable the Error interrupts */
04114     __HAL_FDCAN_DISABLE_IT(hfdcan, ErrStatus);
04115
04116     /* Clear the Error flags */
04117     __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrStatus);
04118
04119     /* Update error code */
04120     hfdcan->ErrorCode |= ErrStatus;
04121   }
04122
04123   if((hfdcan->Instance == FDCAN1) && \
04124      ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != 0))
04125   {
04126     TTSchedSyncITs = hfdcan->ttcan->TTIR & FDCAN_TT_SCHEDULE_SYNC_MASK;
04127     TTSchedSyncITs &= hfdcan->ttcan->TTIE;
04128     TTTimeMarkITs = hfdcan->ttcan->TTIR & FDCAN_TT_TIME_MARK_MASK;
04129     TTTimeMarkITs &= hfdcan->ttcan->TTIE;
04130     TTGlobTimeITs = hfdcan->ttcan->TTIR & FDCAN_TT_GLOBAL_TIME_MASK;
04131     TTGlobTimeITs &= hfdcan->ttcan->TTIE;
04132     TTDistErrors = hfdcan->ttcan->TTIR & FDCAN_TT_DISTURBING_ERROR_MASK;
04133     TTDistErrors &= hfdcan->ttcan->TTIE;
04134     TTFatalErrors = hfdcan->ttcan->TTIR & FDCAN_TT_FATAL_ERROR_MASK;
04135     TTFatalErrors &= hfdcan->ttcan->TTIE;
04136
04137     /* TT Schedule Synchronization interrupts management **********************/
04138     if(TTSchedSyncITs != 0U)
04139     {
04140       /* Disable the TT Schedule Synchronization interrupts */
04141       __HAL_FDCAN_TT_DISABLE_IT(hfdcan, TTSchedSyncITs);
04142
04143       /* Clear the TT Schedule Synchronization flags */
04144       __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTSchedSyncITs);
04145
04146       /* TT Schedule Synchronization Callback */
04147       HAL_FDCAN_TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
04148     }
04149
04150     /* TT Time Mark interrupts management *************************************/
04151     if(TTTimeMarkITs != 0U)
04152     {
04153       /* Disable the TT Time Mark interrupts */
04154       __HAL_FDCAN_TT_DISABLE_IT(hfdcan, TTTimeMarkITs);
04155
04156       /* Clear the TT Time Mark flags */
04157       __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTTimeMarkITs);
04158
04159       /* TT Time Mark Callback */
04160       HAL_FDCAN_TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
04161     }
04162
04163     /* TT Stop Watch interrupt management *************************************/
04164     if(__HAL_FDCAN_TT_GET_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH) != RESET)
04165     {
04166       if(__HAL_FDCAN_TT_GET_IT_SOURCE(hfdcan, FDCAN_TT_IT_STOP_WATCH) != RESET)
04167       {
04168         /* Disable the TT Stop Watch interrupt */
04169         __HAL_FDCAN_TT_DISABLE_IT(hfdcan, FDCAN_TT_IT_STOP_WATCH);
04170
04171         /* Retrieve Stop watch Time and Cycle count */
04172         SWTime = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_SWV) >> 16);
04173         SWCycleCount = hfdcan->ttcan->TTCPT & FDCAN_TTCPT_CCV;
04174
04175         /* Clear the TT Stop Watch flag */
04176         __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH);
04177
04178         /* TT Stop Watch Callback */
04179         HAL_FDCAN_TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
04180       }
04181     }
04182
04183     /* TT Global Time interrupts management ***********************************/
04184     if(TTGlobTimeITs != 0U)
04185     {
04186       /* Disable the TT Global Time interrupts */
04187       __HAL_FDCAN_TT_DISABLE_IT(hfdcan, TTGlobTimeITs);
04188
04189       /* Clear the TT Global Time flags */
04190       __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTGlobTimeITs);
04191
04192       /* TT Global Time Callback */
04193       HAL_FDCAN_TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
04194     }
04195
04196     /* TT Disturbing Error interrupts management ******************************/
04197     if(TTDistErrors != 0U)
04198     {
04199       /* Disable the TT Disturbing Error interrupts */
04200       __HAL_FDCAN_TT_DISABLE_IT(hfdcan, TTDistErrors);
04201
04202       /* Clear the TT Disturbing Error flags */
04203       __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTDistErrors);
04204
04205       /* Update error code */
04206       hfdcan->ErrorCode |= TTDistErrors;
04207     }
04208
04209     /* TT Fatal Error interrupts management ***********************************/
04210     if(TTFatalErrors != 0U)
04211     {
04212       /* Disable the TT Fatal Error interrupts */
04213       __HAL_FDCAN_TT_DISABLE_IT(hfdcan, TTFatalErrors);
04214
04215       /* Clear the TT Fatal Error flags */
04216       __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTFatalErrors);
04217
04218       /* Update error code */
04219       hfdcan->ErrorCode |= TTFatalErrors;
04220     }
04221   }
04222
04223   if(hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE)
04224   {
04225     /* Error Callback */
04226     HAL_FDCAN_ErrorCallback(hfdcan);
04227   }
04228 }
04229
04230 /**
04231   * @}
04232   */
04233
04234 /** @defgroup FDCAN_Exported_Functions_Group6 Callback functions
04235  *  @brief   FDCAN Callback functions
04236  *
04237 @verbatim
04238   ==============================================================================
04239                           ##### Callback functions #####
04240   ==============================================================================
04241     [..]
04242     This subsection provides the following callback functions:
04243       (+) HAL_FDCAN_ClockCalibrationCallback
04244       (+) HAL_FDCAN_TxEventFifoCallback
04245       (+) HAL_FDCAN_RxFifo0Callback
04246       (+) HAL_FDCAN_RxFifo1Callback
04247       (+) HAL_FDCAN_TxFifoEmptyCallback
04248       (+) HAL_FDCAN_TxBufferCompleteCallback
04249       (+) HAL_FDCAN_TxBufferAbortCallback
04250       (+) HAL_FDCAN_RxBufferNewMessageCallback
04251       (+) HAL_FDCAN_HighPriorityMessageCallback
04252       (+) HAL_FDCAN_TimestampWraparoundCallback
04253       (+) HAL_FDCAN_TimeoutOccurredCallback
04254       (+) HAL_FDCAN_ErrorCallback
04255       (+) HAL_FDCAN_TTSchedSyncCallback
04256       (+) HAL_FDCAN_TTTimeMarkCallback
04257       (+) HAL_FDCAN_TTStopWatchCallback
04258       (+) HAL_FDCAN_TTGlobalTimeCallback
04259
04260 @endverbatim
04261   * @{
04262   */
04263
04264 /**
04265   * @brief  Clock Calibration callback.
04266   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
04267   *         the configuration information for the specified FDCAN.
04268   * @param  ClkCalibrationITs: indicates which Clock Calibration interrupts are signalled.
04269   *                            This parameter can be any combination of @arg FDCAN_Clock_Calibration_Interrupts.
04270   * @retval None
04271   */
04272 __weak void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)
04273 {
04274   /* Prevent unused argument(s) compilation warning */
04275   UNUSED(hfdcan);
04276   UNUSED(ClkCalibrationITs);
04277
04278   /* NOTE : This function Should not be modified, when the callback is needed,
04279             the HAL_FDCAN_ClockCalibrationCallback could be implemented in the user file
04280    */
04281 }
04282
04283 /**
04284   * @brief  Tx Event callback.
04285   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
04286   *         the configuration information for the specified FDCAN.
04287   * @param  TxEventFifoITs: indicates which Tx Event FIFO interrupts are signalled.
04288   *                         This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts.
04289   * @retval None
04290   */
04291 __weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
04292 {
04293   /* Prevent unused argument(s) compilation warning */
04294   UNUSED(hfdcan);
04295   UNUSED(TxEventFifoITs);
04296
04297   /* NOTE : This function Should not be modified, when the callback is needed,
04298             the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file
04299    */
04300 }
04301
04302 /**
04303   * @brief  Rx FIFO 0 callback.
04304   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
04305   *         the configuration information for the specified FDCAN.
04306   * @param  RxFifo0ITs: indicates which Rx FIFO 0 interrupts are signalled.
04307   *                     This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts.
04308   * @retval None
04309   */
04310 __weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
04311 {
04312   /* Prevent unused argument(s) compilation warning */
04313   UNUSED(hfdcan);
04314   UNUSED(RxFifo0ITs);
04315
04316   /* NOTE : This function Should not be modified, when the callback is needed,
04317             the HAL_FDCAN_RxFifo0Callback could be implemented in the user file
04318    */
04319 }
04320
04321 /**
04322   * @brief  Rx FIFO 1 callback.
04323   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
04324   *         the configuration information for the specified FDCAN.
04325   * @param  RxFifo1ITs: indicates which Rx FIFO 1 interrupts are signalled.
04326   *                     This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts.
04327   * @retval None
04328   */
04329 __weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
04330 {
04331   /* Prevent unused argument(s) compilation warning */
04332   UNUSED(hfdcan);
04333   UNUSED(RxFifo1ITs);
04334
04335   /* NOTE : This function Should not be modified, when the callback is needed,
04336             the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
04337    */
04338 }
04339
04340 /**
04341   * @brief  Tx FIFO Empty callback.
04342   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
04343   *         the configuration information for the specified FDCAN.
04344   * @retval None
04345   */
04346 __weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
04347 {
04348   /* Prevent unused argument(s) compilation warning */
04349   UNUSED(hfdcan);
04350
04351   /* NOTE : This function Should not be modified, when the callback is needed,
04352             the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file
04353    */
04354 }
04355
04356 /**
04357   * @brief  Transmission Complete callback.
04358   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
04359   *         the configuration information for the specified FDCAN.
04360   * @param  BufferIndexes: Indexes of the transmitted buffers.
04361   *                        This parameter can be any combination of @arg FDCAN_Tx_location.
04362   * @retval None
04363   */
04364 __weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
04365 {
04366   /* Prevent unused argument(s) compilation warning */
04367   UNUSED(hfdcan);
04368   UNUSED(BufferIndexes);
04369
04370   /* NOTE : This function Should not be modified, when the callback is needed,
04371             the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file
04372    */
04373 }
04374
04375 /**
04376   * @brief  Transmission Cancellation callback.
04377   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
04378   *         the configuration information for the specified FDCAN.
04379   * @param  BufferIndexes: Indexes of the aborted buffers.
04380   *                        This parameter can be any combination of @arg FDCAN_Tx_location.
04381   * @retval None
04382   */
04383 __weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
04384 {
04385   /* Prevent unused argument(s) compilation warning */
04386   UNUSED(hfdcan);
04387   UNUSED(BufferIndexes);
04388
04389   /* NOTE : This function Should not be modified, when the callback is needed,
04390             the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file
04391    */
04392 }
04393
04394 /**
04395   * @brief  Rx Buffer New Message callback.
04396   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
04397   *         the configuration information for the specified FDCAN.
04398   * @retval None
04399   */
04400 __weak void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan)
04401 {
04402   /* Prevent unused argument(s) compilation warning */
04403   UNUSED(hfdcan);
04404
04405   /* NOTE : This function Should not be modified, when the callback is needed,
04406             the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file
04407    */
04408 }
04409
04410 /**
04411   * @brief  Timestamp Wraparound callback.
04412   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
04413   *         the configuration information for the specified FDCAN.
04414   * @retval None
04415   */
04416 __weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan)
04417 {
04418   /* Prevent unused argument(s) compilation warning */
04419   UNUSED(hfdcan);
04420
04421   /* NOTE : This function Should not be modified, when the callback is needed,
04422             the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file
04423    */
04424 }
04425
04426 /**
04427   * @brief  Timeout Occurred callback.
04428   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
04429   *         the configuration information for the specified FDCAN.
04430   * @retval None
04431   */
04432 __weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan)
04433 {
04434   /* Prevent unused argument(s) compilation warning */
04435   UNUSED(hfdcan);
04436
04437   /* NOTE : This function Should not be modified, when the callback is needed,
04438             the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file
04439    */
04440 }
04441
04442 /**
04443   * @brief  High Priority Message callback.
04444   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
04445   *         the configuration information for the specified FDCAN.
04446   * @retval None
04447   */
04448 __weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan)
04449 {
04450   /* Prevent unused argument(s) compilation warning */
04451   UNUSED(hfdcan);
04452
04453   /* NOTE : This function Should not be modified, when the callback is needed,
04454             the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file
04455    */
04456 }
04457
04458 /**
04459   * @brief  Error callback.
04460   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
04461   *         the configuration information for the specified FDCAN.
04462   * @retval None
04463   */
04464 __weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
04465 {
04466   /* Prevent unused argument(s) compilation warning */
04467   UNUSED(hfdcan);
04468
04469   /* NOTE : This function Should not be modified, when the callback is needed,
04470             the HAL_FDCAN_ErrorCallback could be implemented in the user file
04471    */
04472 }
04473
04474 /**
04475   * @brief  TT Schedule Synchronization callback.
04476   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
04477   *         the configuration information for the specified FDCAN.
04478   * @param  TTSchedSyncITs: indicates which TT Schedule Synchronization interrupts are signalled.
04479   *                         This parameter can be any combination of @arg FDCAN_TTScheduleSynchronization_Interrupts.
04480   * @retval None
04481   */
04482 __weak void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)
04483 {
04484   /* Prevent unused argument(s) compilation warning */
04485   UNUSED(hfdcan);
04486   UNUSED(TTSchedSyncITs);
04487
04488   /* NOTE : This function Should not be modified, when the callback is needed,
04489             the HAL_FDCAN_TTSchedSyncCallback could be implemented in the user file
04490    */
04491 }
04492
04493 /**
04494   * @brief  TT Time Mark callback.
04495   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
04496   *         the configuration information for the specified FDCAN.
04497   * @param  TTTimeMarkITs: indicates which TT Schedule Synchronization interrupts are signalled.
04498   *                        This parameter can be any combination of @arg FDCAN_TTTimeMark_Interrupts.
04499   * @retval None
04500   */
04501 __weak void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)
04502 {
04503   /* Prevent unused argument(s) compilation warning */
04504   UNUSED(hfdcan);
04505   UNUSED(TTTimeMarkITs);
04506
04507   /* NOTE : This function Should not be modified, when the callback is needed,
04508             the HAL_FDCAN_TTTimeMarkCallback could be implemented in the user file
04509    */
04510 }
04511
04512 /**
04513   * @brief  TT Stop Watch callback.
04514   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
04515   *         the configuration information for the specified FDCAN.
04516   * @param  SWTime: Time Value captured at the Stop Watch Trigger pin (fdcan1_swt) falling/rising
04517   *                 edge (as configured via HAL_FDCAN_TTConfigStopWatch).
04518   *                 This parameter is a number between 0 and 0xFFFF.
04519   * @param  SWCycleCount: Cycle count value captured together with SWTime.
04520   *                       This parameter is a number between 0 and 0x3F.
04521   * @retval None
04522   */
04523 __weak void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)
04524 {
04525   /* Prevent unused argument(s) compilation warning */
04526   UNUSED(hfdcan);
04527   UNUSED(SWTime);
04528   UNUSED(SWCycleCount);
04529
04530   /* NOTE : This function Should not be modified, when the callback is needed,
04531             the HAL_FDCAN_TTStopWatchCallback could be implemented in the user file
04532    */
04533 }
04534
04535 /**
04536   * @brief  TT Global Time callback.
04537   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
04538   *         the configuration information for the specified FDCAN.
04539   * @param  TTGlobTimeITs: indicates which TT Global Time interrupts are signalled.
04540   *                        This parameter can be any combination of @arg FDCAN_TTGlobalTime_Interrupts.
04541   * @retval None
04542   */
04543 __weak void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)
04544 {
04545   /* Prevent unused argument(s) compilation warning */
04546   UNUSED(hfdcan);
04547   UNUSED(TTGlobTimeITs);
04548
04549   /* NOTE : This function Should not be modified, when the callback is needed,
04550             the HAL_FDCAN_TTGlobalTimeCallback could be implemented in the user file
04551    */
04552 }
04553
04554 /**
04555   * @}
04556   */
04557
04558 /** @defgroup FDCAN_Exported_Functions_Group7 Peripheral State functions
04559  *  @brief   FDCAN Peripheral State functions
04560  *
04561 @verbatim
04562   ==============================================================================
04563                       ##### Peripheral State functions #####
04564   ==============================================================================
04565     [..]
04566     This subsection provides functions allowing to :
04567       (+) HAL_FDCAN_GetState()  : Return the FDCAN state.
04568       (+) HAL_FDCAN_GetError()  : Return the FDCAN error code if any.
04569
04570 @endverbatim
04571   * @{
04572   */
04573 /**
04574   * @brief  Return the FDCAN state
04575   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
04576   *         the configuration information for the specified FDCAN.
04577   * @retval HAL state
04578   */
04579 HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef* hfdcan)
04580 {
04581   /* Return FDCAN state */
04582   return hfdcan->State;
04583 }
04584
04585 /**
04586   * @brief  Return the FDCAN error code
04587   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
04588   *         the configuration information for the specified FDCAN.
04589   * @retval FDCAN Error Code
04590   */
04591 uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan)
04592 {
04593   /* Return FDCAN error code */
04594   return hfdcan->ErrorCode;
04595 }
04596
04597 /**
04598   * @}
04599   */
04600
04601 /**
04602   * @}
04603   */
04604
04605 /** @addtogroup FDCAN_Private_Functions
04606   * @{
04607   */
04608
04609 /**
04610   * @brief  Calculate each RAM block start address and size
04611   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
04612   *                 the configuration information for the specified FDCAN.
04613   * @retval HAL status
04614  */
04615 static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan)
04616 {
04617   uint32_t RAMcounter;
04618
04619   hfdcan->msgRam.StandardFilterSA = hfdcan->Init.MessageRAMOffset;
04620
04621   /* Standard filter list start address */
04622   MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_FLSSA, (hfdcan->msgRam.StandardFilterSA << 2));
04623
04624   /* Standard filter elements number */
04625   MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_LSS, (hfdcan->Init.StdFiltersNbr << 16));
04626
04627   /* Extended filter list start address */
04628   hfdcan->msgRam.ExtendedFilterSA = hfdcan->msgRam.StandardFilterSA + hfdcan->Init.StdFiltersNbr;
04629   MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_FLESA, (hfdcan->msgRam.ExtendedFilterSA << 2));
04630
04631   /* Extended filter elements number */
04632   MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_LSE, (hfdcan->Init.ExtFiltersNbr << 16));
04633
04634   /* Rx FIFO 0 start address */
04635   hfdcan->msgRam.RxFIFO0SA = hfdcan->msgRam.ExtendedFilterSA + (hfdcan->Init.ExtFiltersNbr * 2);
04636   MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0SA, (hfdcan->msgRam.RxFIFO0SA << 2));
04637
04638   /* Rx FIFO 0 elements number */
04639   MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0S, (hfdcan->Init.RxFifo0ElmtsNbr << 16));
04640
04641   /* Rx FIFO 1 start address */
04642   hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA + (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize);
04643   MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1SA, (hfdcan->msgRam.RxFIFO1SA << 2));
04644
04645   /* Rx FIFO 1 elements number */
04646   MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1S, (hfdcan->Init.RxFifo1ElmtsNbr << 16));
04647
04648   /* Rx buffer list start address */
04649   hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA + (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize);
04650   MODIFY_REG(hfdcan->Instance->RXBC, FDCAN_RXBC_RBSA, (hfdcan->msgRam.RxBufferSA << 2));
04651
04652   /* Tx event FIFO start address */
04653   hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA + (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize);
04654   MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFSA, (hfdcan->msgRam.TxEventFIFOSA << 2));
04655
04656   /* Tx event FIFO elements number */
04657   MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFS, (hfdcan->Init.TxEventsNbr << 16));
04658
04659   /* Tx buffer list start address */
04660   hfdcan->msgRam.TxBufferSA = hfdcan->msgRam.TxEventFIFOSA + (hfdcan->Init.TxEventsNbr * 2);
04661   MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TBSA, (hfdcan->msgRam.TxBufferSA << 2));
04662
04663   /* Dedicated Tx buffers number */
04664   MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_NDTB, (hfdcan->Init.TxBuffersNbr << 16));
04665
04666   /* Tx FIFO/queue start address */
04667   hfdcan->msgRam.TxFIFOQSA = hfdcan->msgRam.TxBufferSA + (hfdcan->Init.TxBuffersNbr * hfdcan->Init.TxElmtSize);
04668
04669   /* Tx FIFO/queue elements number */
04670   MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TFQS, (hfdcan->Init.TxFifoQueueElmtsNbr << 24));
04671
04672   hfdcan->msgRam.StandardFilterSA = SRAMCAN_BASE + (hfdcan->Init.MessageRAMOffset * 4);
04673   hfdcan->msgRam.ExtendedFilterSA = hfdcan->msgRam.StandardFilterSA + (hfdcan->Init.StdFiltersNbr * 4);
04674   hfdcan->msgRam.RxFIFO0SA = hfdcan->msgRam.ExtendedFilterSA + (hfdcan->Init.ExtFiltersNbr * 2 * 4);
04675   hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA + (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize * 4);
04676   hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA + (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize * 4);
04677   hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA + (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize * 4);
04678   hfdcan->msgRam.TxBufferSA = hfdcan->msgRam.TxEventFIFOSA + (hfdcan->Init.TxEventsNbr * 2 * 4);
04679   hfdcan->msgRam.TxFIFOQSA = hfdcan->msgRam.TxBufferSA + (hfdcan->Init.TxBuffersNbr * hfdcan->Init.TxElmtSize * 4);
04680
04681   hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA + (hfdcan->Init.TxFifoQueueElmtsNbr * hfdcan->Init.TxElmtSize * 4);
04682
04683   if(hfdcan->msgRam.EndAddress > 0x4000B5FC) /* Last address of the Message RAM */
04684   {
04685     /* Update error code.
04686        Message RAM overflow */
04687     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
04688
04689     return HAL_ERROR;
04690   }
04691   else
04692   {
04693     /* Flush the allocated Message RAM area */
04694     for(RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4)
04695     {
04696       *(__IO uint32_t *)(RAMcounter) = 0x00000000;
04697     }
04698   }
04699
04700   /* Return function status */
04701   return HAL_OK;
04702 }
04703
04704 /**
04705   * @brief  Copy Tx message to the message RAM.
04706   * @param  hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
04707   *                 the configuration information for the specified FDCAN.
04708   * @param  pTxHeader: pointer to a FDCAN_TxHeaderTypeDef structure.
04709   * @param  pTxData: pointer to a buffer containing the payload of the Tx frame.
04710   * @param  BufferIndex: index of the buffer to be configured.
04711   * @retval HAL status
04712  */
04713 static HAL_StatusTypeDef FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
04714 {
04715   uint32_t TxElementW1;
04716   uint32_t TxElementW2;
04717   uint32_t *TxAddress;
04718   uint32_t ByteCounter;
04719
04720   /* Build first word of Tx header element */
04721   if(pTxHeader->IdType == FDCAN_STANDARD_ID)
04722   {
04723     TxElementW1 = (pTxHeader->ErrorStateIndicator |
04724                    FDCAN_STANDARD_ID |
04725                    pTxHeader->TxFrameType |
04726                    (pTxHeader->Identifier << 18));
04727   }
04728   else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
04729   {
04730     TxElementW1 = (pTxHeader->ErrorStateIndicator |
04731                    FDCAN_EXTENDED_ID |
04732                    pTxHeader->TxFrameType |
04733                    pTxHeader->Identifier);
04734   }
04735
04736   /* Build second word of Tx header element */
04737   TxElementW2 = ((pTxHeader->MessageMarker << 24) |
04738                  pTxHeader->TxEventFifoControl |
04739                  pTxHeader->FDFormat |
04740                  pTxHeader->BitRateSwitch |
04741                  pTxHeader->DataLength);
04742
04743   /* Calculate Tx element address */
04744   TxAddress = (uint32_t *)(hfdcan->msgRam.TxBufferSA + (BufferIndex * hfdcan->Init.TxElmtSize * 4));
04745
04746   /* Write Tx element header to the message RAM */
04747   *TxAddress++ = TxElementW1;
04748   *TxAddress++ = TxElementW2;
04749
04750   /* Write Tx payload to the message RAM */
04751   for(ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16]; ByteCounter += 4)
04752   {
04753     *TxAddress++ = ((pTxData[ByteCounter+3] << 24) |
04754                     (pTxData[ByteCounter+2] << 16) |
04755                     (pTxData[ByteCounter+1] << 8) |
04756                     pTxData[ByteCounter]);
04757   }
04758
04759   /* Return function status */
04760   return HAL_OK;
04761 }
04762
04763 /**
04764   * @}
04765   */
04766 #endif /* HAL_FDCAN_MODULE_ENABLED */
04767 /**
04768   * @}
04769   */
04770
04771 /**
04772   * @}
04773   */
04774
04775 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_fdcan.h Source File

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stm32h7xx_hal_fdcan.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_fdcan.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of FDCAN HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_FDCAN_H
00040 #define __STM32H7xx_HAL_FDCAN_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup FDCAN
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup FDCAN_Exported_Types FDCAN Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief HAL State structures definition
00064   */
00065 typedef enum
00066 {
00067   HAL_FDCAN_STATE_RESET      = 0x00U, /*!< FDCAN not yet initialized or disabled */
00068   HAL_FDCAN_STATE_READY      = 0x01U, /*!< FDCAN initialized and ready for use   */
00069   HAL_FDCAN_STATE_BUSY       = 0x02U, /*!< FDCAN process is ongoing              */
00070   HAL_FDCAN_STATE_ERROR      = 0x03U  /*!< FDCAN error state                     */
00071 }HAL_FDCAN_StateTypeDef;
00072
00073 /**
00074   * @brief FDCAN Init structure definition
00075   */
00076 typedef struct
00077 {
00078   uint32_t FrameFormat;                  /*!< Specifies the FDCAN frame format.
00079                                               This parameter can be a value of @ref FDCAN_frame_format     */
00080
00081   uint32_t Mode;                         /*!< Specifies the FDCAN mode.
00082                                               This parameter can be a value of @ref FDCAN_operating_mode   */
00083
00084   FunctionalState AutoRetransmission;    /*!< Enable or disable the automatic retransmission mode.
00085                                               This parameter can be set to ENABLE or DISABLE               */
00086
00087   FunctionalState TransmitPause;         /*!< Enable or disable the Transmit Pause feature.
00088                                               This parameter can be set to ENABLE or DISABLE               */
00089
00090   FunctionalState ProtocolException;      /*!< Enable or disable the Protocol Exception Handling.
00091                                               This parameter can be set to ENABLE or DISABLE               */
00092
00093   uint32_t NominalPrescaler;             /*!< Specifies the value by which the oscillator frequency is
00094                                               divided for generating the nominal bit time quanta.
00095                                               This parameter must be a number between 1 and 512            */
00096
00097   uint32_t NominalSyncJumpWidth;         /*!< Specifies the maximum number of time quanta the FDCAN
00098                                               hardware is allowed to lengthen or shorten a bit to perform
00099                                               resynchronization.
00100                                               This parameter must be a number between 1 and 128            */
00101
00102   uint32_t NominalTimeSeg1;              /*!< Specifies the number of time quanta in Bit Segment 1.
00103                                               This parameter must be a number between 2 and 256            */
00104
00105   uint32_t NominalTimeSeg2;              /*!< Specifies the number of time quanta in Bit Segment 2.
00106                                               This parameter must be a number between 2 and 128            */
00107
00108   uint32_t DataPrescaler;                /*!< Specifies the value by which the oscillator frequency is
00109                                               divided for generating the data bit time quanta.
00110                                               This parameter must be a number between 1 and 32             */
00111
00112   uint32_t DataSyncJumpWidth;            /*!< Specifies the maximum number of time quanta the FDCAN
00113                                               hardware is allowed to lengthen or shorten a data bit to
00114                                               perform resynchronization.
00115                                               This parameter must be a number between 1 and 16             */
00116
00117   uint32_t DataTimeSeg1;                 /*!< Specifies the number of time quanta in Data Bit Segment 1.
00118                                               This parameter must be a number between 1 and 32             */
00119
00120   uint32_t DataTimeSeg2;                 /*!< Specifies the number of time quanta in Data Bit Segment 2.
00121                                               This parameter must be a number between 1 and 16             */
00122
00123   uint32_t MessageRAMOffset;             /*!< Specifies the message RAM start address.
00124                                               This parameter must be a number between 0 and 2560           */
00125
00126   uint32_t StdFiltersNbr;                /*!< Specifies the number of standard Message ID filters.
00127                                               This parameter must be a number between 0 and 128            */
00128
00129   uint32_t ExtFiltersNbr;                /*!< Specifies the number of extended Message ID filters.
00130                                               This parameter must be a number between 0 and 64             */
00131
00132   uint32_t RxFifo0ElmtsNbr;              /*!< Specifies the number of Rx FIFO0 Elements.
00133                                               This parameter must be a number between 0 and 64             */
00134
00135   uint32_t RxFifo0ElmtSize;              /*!< Specifies the Data Field Size in an Rx FIFO 0 element.
00136                                               This parameter can be a value of @ref FDCAN_data_field_size  */
00137
00138   uint32_t RxFifo1ElmtsNbr;              /*!< Specifies the number of Rx FIFO 1 Elements.
00139                                               This parameter must be a number between 0 and 64             */
00140
00141   uint32_t RxFifo1ElmtSize;              /*!< Specifies the Data Field Size in an Rx FIFO 1 element.
00142                                               This parameter can be a value of @ref FDCAN_data_field_size  */
00143
00144   uint32_t RxBuffersNbr;                 /*!< Specifies the number of Dedicated Rx Buffer elements.
00145                                               This parameter must be a number between 0 and 64             */
00146
00147   uint32_t RxBufferSize;                 /*!< Specifies the Data Field Size in an Rx Buffer element.
00148                                               This parameter can be a value of @ref FDCAN_data_field_size  */
00149
00150   uint32_t TxEventsNbr;                  /*!< Specifies the number of Tx Event FIFO elements.
00151                                               This parameter must be a number between 0 and 32             */
00152
00153   uint32_t TxBuffersNbr;                 /*!< Specifies the number of Dedicated Tx Buffers.
00154                                               This parameter must be a number between 0 and 32             */
00155
00156   uint32_t TxFifoQueueElmtsNbr;          /*!< Specifies the number of Tx Buffers used for Tx FIFO/Queue.
00157                                               This parameter must be a number between 0 and 32             */
00158
00159   uint32_t TxFifoQueueMode;              /*!< Tx FIFO/Queue Mode selection.
00160                                               This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */
00161
00162   uint32_t TxElmtSize;                   /*!< Specifies the Data Field Size in a Tx Element.
00163                                               This parameter can be a value of @ref FDCAN_data_field_size  */
00164
00165 }FDCAN_InitTypeDef;
00166
00167 /**
00168   * @brief  FDCAN clock calibration unit structure definition
00169   */
00170 typedef struct
00171 {
00172   uint32_t ClockCalibration;     /*!< Enable or disable the clock calibration.
00173                                       This parameter can be set to ENABLE or DISABLE                       */
00174
00175   uint32_t ClockDivider;         /*!< Specifies the FDCAN kernel clock divider when the clock calibration
00176                                       is bypassed.
00177                                       This parameter can be a value of @ref FDCAN_clock_divider            */
00178
00179   uint32_t MinOscClkPeriods;     /*!< Configures the minimum number of periods in two CAN bit times. The
00180                                       actual configured number of periods is MinOscClkPeriods x 32.
00181                                       This parameter must be a number between 0x00 and 0xFF                */
00182
00183   uint32_t CalFieldLength;       /*!< Specifies the calibration field length.
00184                                       This parameter can be a value of @ref FDCAN_calibration_field_length */
00185
00186   uint32_t TimeQuantaPerBitTime; /*!< Configures the number of time quanta per bit time.
00187                                       This parameter must be a number between 4 and 25                     */
00188
00189   uint32_t WatchdogStartValue;   /*!< Start value of the Calibration Watchdog Counter.
00190                                       If set to zero the counter is disabled.
00191                                       This parameter must be a number between 0x0000 and 0xFFFF            */
00192
00193 }FDCAN_ClkCalUnitTypeDef;
00194
00195 /**
00196   * @brief  FDCAN filter structure definition
00197   */
00198 typedef struct
00199 {
00200   uint32_t IdType;           /*!< Specifies the identifier type.
00201                                   This parameter can be a value of @ref FDCAN_id_type       */
00202
00203   uint32_t FilterIndex;      /*!< Specifies the filter which will be initialized.
00204                                   This parameter must be a number between:
00205                                    - 0 and 127, if IdType is FDCAN_STANDARD_ID
00206                                    - 0 and 63, if IdType is FDCAN_EXTENDED_ID               */
00207
00208   uint32_t FilterType;       /*!< Specifies the filter type.
00209                                   This parameter can be a value of @ref FDCAN_filter_type.
00210                                   The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted
00211                                   only when IdType is FDCAN_EXTENDED_ID.
00212                                   This parameter is ignored if FilterConfig is set to
00213                                   FDCAN_FILTER_TO_RXBUFFER                                  */
00214
00215   uint32_t FilterConfig;     /*!< Specifies the filter configuration.
00216                                   This parameter can be a value of @ref FDCAN_filter_config */
00217
00218   uint32_t FilterID1;        /*!< Specifies the filter identification 1.
00219                                   This parameter must be a number between:
00220                                    - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
00221                                    - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
00222
00223   uint32_t FilterID2;        /*!< Specifies the filter identification 2.
00224                                   This parameter is ignored if FilterConfig is set to
00225                                   FDCAN_FILTER_TO_RXBUFFER.
00226                                   This parameter must be a number between:
00227                                    - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
00228                                    - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
00229
00230   uint32_t RxBufferIndex;    /*!< Contains the index of the Rx buffer in which the
00231                                   matching message will be stored.
00232                                   This parameter must be a number between 0 and 63.
00233                                   This parameter is ignored if FilterConfig is different
00234                                   from FDCAN_FILTER_TO_RXBUFFER                             */
00235
00236   uint32_t IsCalibrationMsg; /*!< Specifies whether the filter is configured for
00237                                   calibration messages.
00238                                   This parameter is ignored if FilterConfig is different
00239                                   from FDCAN_FILTER_TO_RXBUFFER.
00240                                   This parameter can be:
00241                                    - 0 : ordinary message
00242                                    - 1 : calibration message                                */
00243
00244 }FDCAN_FilterTypeDef;
00245
00246 /**
00247   * @brief  FDCAN Tx header structure definition
00248   */
00249 typedef struct
00250 {
00251   uint32_t Identifier;          /*!< Specifies the identifier.
00252                                      This parameter must be a number between:
00253                                       - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
00254                                       - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
00255
00256   uint32_t IdType;              /*!< Specifies the identifier type for the message that will be
00257                                      transmitted.
00258                                      This parameter can be a value of @ref FDCAN_id_type               */
00259
00260   uint32_t TxFrameType;         /*!< Specifies the frame type of the message that will be transmitted.
00261                                      This parameter can be a value of @ref FDCAN_frame_type            */
00262
00263   uint32_t DataLength;          /*!< Specifies the length of the frame that will be transmitted.
00264                                       This parameter can be a value of @ref FDCAN_data_length_code     */
00265
00266   uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
00267                                      This parameter can be a value of @ref FDCAN_error_state_indicator */
00268
00269   uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame will be transmitted with or without
00270                                      bit rate switching.
00271                                      This parameter can be a value of @ref FDCAN_bit_rate_switching    */
00272
00273   uint32_t FDFormat;            /*!< Specifies whether the Tx frame will be transmitted in classic or
00274                                      FD format.
00275                                      This parameter can be a value of @ref FDCAN_format                */
00276
00277   uint32_t TxEventFifoControl;  /*!< Specifies the event FIFO control.
00278                                      This parameter can be a value of @ref FDCAN_EFC                   */
00279
00280   uint32_t MessageMarker;       /*!< Specifies the message marker to be copied into Tx Event FIFO
00281                                      element for identification of Tx message status.
00282                                      This parameter must be a number between 0 and 0xFF                */
00283
00284 }FDCAN_TxHeaderTypeDef;
00285
00286 /**
00287   * @brief  FDCAN Rx header structure definition
00288   */
00289 typedef struct
00290 {
00291   uint32_t Identifier;            /*!< Specifies the identifier.
00292                                        This parameter must be a number between:
00293                                         - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
00294                                         - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
00295
00296   uint32_t IdType;                /*!< Specifies the identifier type of the received message.
00297                                        This parameter can be a value of @ref FDCAN_id_type               */
00298
00299   uint32_t RxFrameType;           /*!< Specifies the the received message frame type.
00300                                        This parameter can be a value of @ref FDCAN_frame_type            */
00301
00302   uint32_t DataLength;            /*!< Specifies the received frame length.
00303                                         This parameter can be a value of @ref FDCAN_data_length_code     */
00304
00305   uint32_t ErrorStateIndicator;   /*!< Specifies the error state indicator.
00306                                        This parameter can be a value of @ref FDCAN_error_state_indicator */
00307
00308   uint32_t BitRateSwitch;         /*!< Specifies whether the Rx frame is received with or without bit
00309                                        rate switching.
00310                                        This parameter can be a value of @ref FDCAN_bit_rate_switching    */
00311
00312   uint32_t FDFormat;              /*!< Specifies whether the Rx frame is received in classic or FD
00313                                        format.
00314                                        This parameter can be a value of @ref FDCAN_format                */
00315
00316   uint32_t RxTimestamp;           /*!< Specifies the timestamp counter value captured on start of frame
00317                                        reception.
00318                                        This parameter must be a number between 0 and 0xFFFF              */
00319
00320   uint32_t FilterIndex;           /*!< Specifies the index of matching Rx acceptance filter element.
00321                                        This parameter must be a number between:
00322                                         - 0 and 127, if IdType is FDCAN_STANDARD_ID
00323                                         - 0 and 63, if IdType is FDCAN_EXTENDED_ID                       */
00324
00325   uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.
00326                                          Acceptance of non-matching frames may be enabled via
00327                                          HAL_FDCAN_ConfigGlobalFilter().
00328                                          This parameter can be 0 or 1                                    */
00329
00330 }FDCAN_RxHeaderTypeDef;
00331
00332 /**
00333   * @brief  FDCAN Tx event FIFO structure definition
00334   */
00335 typedef struct
00336 {
00337   uint32_t Identifier;          /*!< Specifies the identifier.
00338                                      This parameter must be a number between:
00339                                       - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
00340                                       - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
00341
00342   uint32_t IdType;              /*!< Specifies the identifier type for the transmitted message.
00343                                      This parameter can be a value of @ref FDCAN_id_type               */
00344
00345   uint32_t TxFrameType;         /*!< Specifies the frame type of the transmitted message.
00346                                      This parameter can be a value of @ref FDCAN_frame_type            */
00347
00348   uint32_t DataLength;          /*!< Specifies the length of the transmitted frame.
00349                                      This parameter can be a value of @ref FDCAN_data_length_code      */
00350
00351   uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
00352                                      This parameter can be a value of @ref FDCAN_error_state_indicator */
00353
00354   uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame is transmitted with or without bit
00355                                      rate switching.
00356                                      This parameter can be a value of @ref FDCAN_bit_rate_switching    */
00357
00358   uint32_t FDFormat;            /*!< Specifies whether the Tx frame is transmitted in classic or FD
00359                                      format.
00360                                      This parameter can be a value of @ref FDCAN_format                */
00361
00362   uint32_t TxTimestamp;         /*!< Specifies the timestamp counter value captured on start of frame
00363                                      transmission.
00364                                      This parameter must be a number between 0 and 0xFFFF              */
00365
00366   uint32_t MessageMarker;       /*!< Specifies the message marker copied into Tx Event FIFO element
00367                                      for identification of Tx message status.
00368                                      This parameter must be a number between 0 and 0xFF                */
00369
00370   uint32_t EventType;           /*!< Specifies the event type.
00371                                      This parameter can be a value of @ref FDCAN_event_type            */
00372
00373 }FDCAN_TxEventFifoTypeDef;
00374
00375 /**
00376   * @brief  FDCAN High Priority Message Status structure definition
00377   */
00378 typedef struct
00379 {
00380   uint32_t FilterList;     /*!< Specifies the filter list of the matching filter element.
00381                                 This parameter can be:
00382                                  - 0 : Standard Filter List
00383                                  - 1 : Extended Filter List                                */
00384
00385   uint32_t FilterIndex;    /*!< Specifies the index of matching filter element.
00386                                 This parameter can be a number between:
00387                                 - 0 and 127, if FilterList is 0 (Standard)
00388                                 - 0 and 63, if FilterList is 1 (Extended)                  */
00389
00390   uint32_t MessageStorage; /*!< Specifies the HP Message Storage.
00391                                 This parameter can be a value of @ref FDCAN_hp_msg_storage */
00392
00393   uint32_t MessageIndex;   /*!< Specifies the Index of Rx FIFO element to which the
00394                                 message was stored.
00395                                 This parameter is valid only when MessageStorage is:
00396                                   FDCAN_HP_STORAGE_RXFIFO0
00397                                  or
00398                                   FDCAN_HP_STORAGE_RXFIFO1                                 */
00399
00400 }FDCAN_HpMsgStatusTypeDef;
00401
00402 /**
00403   * @brief FDCAN Protocol Status structure definition
00404   */
00405 typedef struct
00406 {
00407   uint32_t LastErrorCode;     /*!< Specifies the type of the last error that occurred on the FDCAN bus.
00408                                    This parameter can be a value of @ref FDCAN_protocol_error_code                           */
00409
00410   uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format
00411                                    frame with its BRS flag set.
00412                                    This parameter can be a value of @ref FDCAN_protocol_error_code                           */
00413
00414   uint32_t Activity;          /*!< Specifies the FDCAN module communication state.
00415                                    This parameter can be a value of @ref FDCAN_communication_state                           */
00416
00417   uint32_t ErrorPassive;      /*!< Specifies the FDCAN module error status.
00418                                    This parameter can be:
00419                                     - 0 : The FDCAN is in Error_Active state
00420                                     - 1 : The FDCAN is in Error_Passive state                                                */
00421
00422   uint32_t Warning;           /*!< Specifies the FDCAN module warning status.
00423                                    This parameter can be:
00424                                     - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96
00425                                     - 1 : at least one of error counters has reached the Error_Warning limit of 96           */
00426
00427   uint32_t BusOff;            /*!< Specifies the FDCAN module Bus_Off status.
00428                                    This parameter can be:
00429                                     - 0 : The FDCAN is not in Bus_Off state
00430                                     - 1 : The FDCAN is in Bus_Off state                                                      */
00431
00432   uint32_t RxESIflag;         /*!< Specifies ESI flag of last received CAN FD message.
00433                                    This parameter can be:
00434                                     - 0 : Last received CAN FD message did not have its ESI flag set
00435                                     - 1 : Last received CAN FD message had its ESI flag set                                  */
00436
00437   uint32_t RxBRSflag;         /*!< Specifies BRS flag of last received CAN FD message.
00438                                    This parameter can be:
00439                                     - 0 : Last received CAN FD message did not have its BRS flag set
00440                                     - 1 : Last received CAN FD message had its BRS flag set                                  */
00441
00442   uint32_t RxFDFflag;         /*!< Specifies FDF flag of last received CAN FD message.
00443                                    This parameter can be:
00444                                     - 0 : Last received CAN FD message did not have its FDF flag set
00445                                     - 1 : Last received CAN FD message had its FDF flag set                                  */
00446
00447   uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
00448                                    This parameter can be:
00449                                     - 0 : No protocol exception event occurred since last read access
00450                                     - 1 : Protocol exception event occurred                                                  */
00451
00452   uint32_t TDCvalue;          /*!< Specifies the Transmitter Delay Compensation Value.
00453                                    This parameter can be a number between 0 and 127                                          */
00454
00455 }FDCAN_ProtocolStatusTypeDef;
00456
00457 /**
00458   * @brief FDCAN Error Counters structure definition
00459   */
00460 typedef struct
00461 {
00462   uint32_t TxErrorCnt;     /*!< Specifies the Transmit Error Counter Value.
00463                                 This parameter can be a number between 0 and 255                                         */
00464
00465   uint32_t RxErrorCnt;     /*!< Specifies the Receive Error Counter Value.
00466                                 This parameter can be a number between 0 and 127                                         */
00467
00468   uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
00469                                 This parameter can be:
00470                                  - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
00471                                  - 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */
00472
00473   uint32_t ErrorLogging;   /*!< Specifies the Transmit/Receive error logging counter value.
00474                                 This parameter can be a number between 0 and 127.
00475                                 This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt
00476                                 or the RxErrorCnt to be incremented. The counter stops at 127; the next increment of
00477                                 TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW           */
00478
00479 }FDCAN_ErrorCountersTypeDef;
00480
00481 /**
00482   * @brief FDCAN TT Init structure definition
00483   */
00484 typedef struct
00485 {
00486   uint32_t OperationMode;     /*!< Specifies the FDCAN Operation Mode.
00487                                    This parameter can be a value of @ref FDCAN_operation_mode               */
00488
00489   uint32_t GapEnable;         /*!< Specifies the FDCAN TT Operation.
00490                                    This parameter can be a value of @ref FDCAN_TT_operation.
00491                                    This parameter is ignored if OperationMode is set to
00492                                    FDCAN_TT_COMMUNICATION_LEVEL0                                            */
00493
00494   uint32_t TimeMaster;        /*!< Specifies whether the instance is a slave or a potential master.
00495                                    This parameter can be a value of @ref FDCAN_TT_time_master               */
00496
00497   uint32_t SyncDevLimit;      /*!< Specifies the Synchronization Deviation Limit SDL of the TUR
00498                                    numerator : TUR = (Numerator ± SDL) / Denominator.
00499                                    With : SDL = 2^(SyncDevLimit+5).
00500                                    This parameter must be a number between 0 and 7                          */
00501
00502   uint32_t InitRefTrigOffset; /*!< Specifies the Initial Reference Trigger Offset.
00503                                    This parameter must be a number between 0 and 127                        */
00504
00505   uint32_t ExternalClkSync;   /*!< Enable or disable External Clock Synchronization.
00506                                    This parameter can be a value of @ref FDCAN_TT_external_clk_sync.
00507                                    This parameter is ignored if OperationMode is set to
00508                                    FDCAN_TT_COMMUNICATION_LEVEL1                                            */
00509
00510   uint32_t AppWdgLimit;       /*!< Specifies the Application Watchdog Limit : maximum time after
00511                                    which the application has to serve the application watchdog.
00512                                    The application watchdog is incremented once each 256 NTUs.
00513                                    The application watchdog can be disabled by setting AppWdgLimit to 0.
00514                                    This parameter must be a number between 0 and 255.
00515                                    This parameter is ignored if OperationMode is set to
00516                                    FDCAN_TT_COMMUNICATION_LEVEL0                                            */
00517
00518   uint32_t GlobalTimeFilter;  /*!< Enable or disable Global Time Filtering.
00519                                    This parameter can be a value of @ref FDCAN_TT_global_time_filtering.
00520                                    This parameter is ignored if OperationMode is set to
00521                                    FDCAN_TT_COMMUNICATION_LEVEL1                                            */
00522
00523   uint32_t ClockCalibration;  /*!< Enable or disable Automatic Clock Calibration.
00524                                    This parameter can be a value of @ref FDCAN_TT_auto_clk_calibration.
00525                                    This parameter is ignored if OperationMode is set to
00526                                    FDCAN_TT_COMMUNICATION_LEVEL1                                            */
00527
00528   uint32_t EvtTrigPolarity;   /*!< Specifies the Event Trigger Polarity.
00529                                    This parameter can be a value of @ref FDCAN_TT_event_trig_polarity.
00530                                    This parameter is ignored if OperationMode is set to
00531                                    FDCAN_TT_COMMUNICATION_LEVEL0                                            */
00532
00533   uint32_t BasicCyclesNbr;    /*!< Specifies the nubmer of basic cycles in the system matrix.
00534                                    This parameter can be a value of @ref FDCAN_TT_basic_cycle_number        */
00535
00536   uint32_t CycleStartSync;    /*!< Enable or disable synchronization pulse output at pin fdcan1_soc.
00537                                    This parameter can be a value of @ref FDCAN_TT_cycle_start_sync          */
00538
00539   uint32_t TxEnableWindow;    /*!< Specifies the length of Tx enable window in NTUs.
00540                                    This parameter must be a number between 1 and 16                         */
00541
00542   uint32_t ExpTxTrigNbr;      /*!< Specifies the number of expected Tx_Triggers in the system matrix.
00543                                    This is the sum of Tx_Triggers for exclusive, single arbitrating and
00544                                    merged arbitrating windows.
00545                                    This parameter must be a number between 0 and 4095                       */
00546
00547   uint32_t TURNumerator;      /*!< Specifies the TUR (Time Unit Ratio) numerator.
00548                                    It is adviced to set this parameter to the largest applicable value.
00549                                    This parameter must be a number between 0x10000 and 0x1FFFF              */
00550
00551   uint32_t TURDenominator;    /*!< Specifies the TUR (Time Unit Ratio) denominator.
00552                                    This parameter must be a number between 0x0001 and 0x3FFF                */
00553
00554   uint32_t TriggerMemoryNbr;  /*!< Specifies the number of trigger memory elements.
00555                                    This parameter must be a number between 0 and 64                         */
00556
00557   uint32_t StopWatchTrigSel;  /*!< Specifies the input to be used as stop watch trigger.
00558                                    This parameter can be a value of @ref FDCAN_TT_stop_watch_trig_selection */
00559
00560   uint32_t EventTrigSel;      /*!< Specifies the input to be used as event trigger.
00561                                    This parameter can be a value of @ref FDCAN_TT_event_trig_selection      */
00562
00563 }FDCAN_TT_ConfigTypeDef;
00564
00565 /**
00566   * @brief  FDCAN Trigger structure definition
00567   */
00568 typedef struct
00569 {
00570   uint32_t TriggerIndex;  /*!< Specifies the trigger which will be configured.
00571                                This parameter must be a number between 0 and 63                                 */
00572
00573   uint32_t TimeMark;      /*!< Specifies the cycle time for which the trigger becomes active.
00574                                This parameter must be a number between 0 and 0xFFFF                             */
00575
00576   uint32_t RepeatFactor;  /*!< Specifies the trigger repeat factor.
00577                                This parameter can be a value of @ref FDCAN_TT_Repeat_Factor                     */
00578
00579   uint32_t StartCycle;    /*!< Specifies the index of the first cycle in which the trigger becomes active.
00580                                This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
00581                                This parameter must be a number between 0 and RepeatFactor                       */
00582
00583   uint32_t TmEventInt;    /*!< Enable or disable the internal time mark event.
00584                                If enabled, FDCAN_TT_FLAG_TRIG_TIME_MARK flag is set when trigger memory element
00585                                becomes active.
00586                                This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_Internal          */
00587
00588   uint32_t TmEventExt;    /*!< Enable or disable the external time mark event.
00589                                If enabled, and if TTOCN.TTIE is set, a pulse is generated at fdcan1_tmp when
00590                                trigger memory element becomes active.
00591                                This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_External          */
00592
00593   uint32_t TriggerType;   /*!< Specifies the trigger type.
00594                                This parameter can be a value of @ref FDCAN_TT_Trigger_Type                      */
00595
00596   uint32_t FilterType;    /*!< Specifies the filter identifier type.
00597                                This parameter can be a value of @ref FDCAN_id_type                              */
00598
00599   uint32_t TxBufferIndex; /*!< Specifies the index of the Tx buffer for which the trigger is valid.
00600                                This parameter can be a value of @ref FDCAN_Tx_location.
00601                                This parameter is taken in consideration only if the trigger is configured for
00602                                transmission.                                                                    */
00603
00604   uint32_t FilterIndex;   /*!< Specifies the filter for which the trigger is valid.
00605                                This parameter is taken in consideration only if the trigger is configured for
00606                                reception.
00607                                This parameter must be a number between:
00608                                 - 0 and 127, if FilterType is FDCAN_STANDARD_ID
00609                                 - 0 and 63, if FilterType is FDCAN_EXTENDED_ID                                  */
00610
00611 }FDCAN_TriggerTypeDef;
00612
00613 /**
00614   * @brief  FDCAN TT Operation Status structure definition
00615   */
00616 typedef struct
00617 {
00618   uint32_t ErrorLevel;       /*!< Specifies the type of the TT operation error level.
00619                                   This parameter can be a value of @ref FDCAN_TT_error_level                    */
00620
00621   uint32_t MasterState;      /*!< Specifies the type of the TT master state.
00622                                   This parameter can be a value of @ref FDCAN_TT_master_state                   */
00623
00624   uint32_t SyncState;        /*!< Specifies the type of the TT synchronization state.
00625                                   This parameter can be a value of @ref FDCAN_TT_sync_state                     */
00626
00627   uint32_t GTimeQuality;     /*!< Specifies the Quality of Global Time Phase.
00628                                   This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0.
00629                                   This parameter can be:
00630                                    - 0 : Global time not valid
00631                                    - 1 : Global time in phase with Time Master                                  */
00632
00633   uint32_t ClockQuality;     /*!< Specifies the Quality of Clock Speed.
00634                                   This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1.
00635                                   This parameter can be:
00636                                    - 0 : Local clock speed not synchronized to Time Master clock speed
00637                                    - 1 : Synchronization Deviation ≤ SDL                                        */
00638
00639   uint32_t RefTrigOffset;    /*!< Specifies the Actual Reference Trigger Offset Value.
00640                                   This parameter can be a number between 0 and 0xFF                             */
00641
00642   uint32_t GTimeDiscPending; /*!< Specifies the Global Time Discontinuity State.
00643                                   This parameter can be:
00644                                    - 0 : No global time preset pending
00645                                    - 1 : Node waits for the global time preset to take effect                   */
00646
00647   uint32_t GapFinished;      /*!< Specifies whether a Gap is finished.
00648                                   This parameter can be:
00649                                    - 0 : Reset at the end of each reference message
00650                                    - 1 : Gap finished                                                           */
00651
00652   uint32_t MasterPriority;   /*!< Specifies the Priority of actual Time Master.
00653                                   This parameter can be a number between 0 and 0x7                              */
00654
00655   uint32_t GapStarted;       /*!< Specifies whether a Gap is started.
00656                                   This parameter can be:
00657                                    - 0 : No Gap in schedule
00658                                    - 1 : Gap time after Basic Cycle has started                                 */
00659
00660   uint32_t WaitForEvt;       /*!< Specifies whether a Gap is annouced.
00661                                   This parameter can be:
00662                                    - 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0
00663                                    - 1 : Reference message with Next_is_Gap = 1 received                        */
00664
00665   uint32_t AppWdgEvt;        /*!< Specifies the Application Watchdog State.
00666                                   This parameter can be:
00667                                    - 0 : Application Watchdog served in time
00668                                    - 1 : Failed to serve Application Watchdog in time                           */
00669
00670   uint32_t ECSPending;       /*!< Specifies the External Clock Synchronization State.
00671                                   This parameter can be:
00672                                    - 0 : No external clock synchronization pending
00673                                    - 1 : Node waits for external clock synchronization to take effect           */
00674
00675   uint32_t PhaseLock;        /*!< Specifies the Phase Lock State.
00676                                   This parameter can be:
00677                                    - 0 : Phase outside range
00678                                    - 1 : Phase inside range                                                     */
00679
00680 }FDCAN_TTOperationStatusTypeDef;
00681
00682 /**
00683   * @brief  FDCAN Message RAM blocks
00684   */
00685 typedef struct
00686 {
00687   uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address.
00688                                   This parameter must be a 32-bit word address      */
00689
00690   uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address.
00691                                   This parameter must be a 32-bit word address      */
00692
00693   uint32_t RxFIFO0SA;        /*!< Specifies the Rx FIFO 0 Start Address.
00694                                   This parameter must be a 32-bit word address      */
00695
00696   uint32_t RxFIFO1SA;        /*!< Specifies the Rx FIFO 1 Start Address.
00697                                   This parameter must be a 32-bit word address      */
00698
00699   uint32_t RxBufferSA;       /*!< Specifies the Rx Buffer Start Address.
00700                                   This parameter must be a 32-bit word address      */
00701
00702   uint32_t TxEventFIFOSA;    /*!< Specifies the Tx Event FIFO Start Address.
00703                                   This parameter must be a 32-bit word address      */
00704
00705   uint32_t TxBufferSA;       /*!< Specifies the Tx Buffers Start Address.
00706                                   This parameter must be a 32-bit word address      */
00707
00708   uint32_t TxFIFOQSA;        /*!< Specifies the Tx FIFO/Queue Start Address.
00709                                   This parameter must be a 32-bit word address      */
00710
00711   uint32_t TTMemorySA;       /*!< Specifies the Trigger Memory Start Address.
00712                                   This parameter must be a 32-bit word address      */
00713
00714   uint32_t EndAddress;       /*!< Specifies the End Address of the allocated RAM.
00715                                   This parameter must be a 32-bit word address      */
00716
00717 }FDCAN_MsgRamAddressTypeDef;
00718
00719 /**
00720   * @brief  FDCAN handle structure definition
00721   */
00722 typedef struct
00723 {
00724   FDCAN_GlobalTypeDef         *Instance;  /*!< Register base address     */
00725
00726   TTCAN_TypeDef               *ttcan;     /*!< TT register base address  */
00727
00728   FDCAN_InitTypeDef           Init;       /*!< FDCAN required parameters */
00729
00730   FDCAN_MsgRamAddressTypeDef  msgRam;     /*!< FDCAN Message RAM blocks  */
00731
00732   __IO HAL_FDCAN_StateTypeDef State;      /*!< FDCAN communication state */
00733
00734   HAL_LockTypeDef             Lock;       /*!< FDCAN locking object      */
00735
00736   __IO uint32_t               ErrorCode;  /*!< FDCAN Error code          */
00737
00738 }FDCAN_HandleTypeDef;
00739
00740
00741 /**
00742   * @}
00743   */
00744
00745 /* Exported constants --------------------------------------------------------*/
00746 /** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants
00747   * @{
00748   */
00749
00750 /** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code
00751   * @{
00752   */
00753 #define HAL_FDCAN_ERROR_NONE            ((uint32_t)0x00000000U) /*!< No error                                                               */
00754 #define HAL_FDCAN_ERROR_TIMEOUT         ((uint32_t)0x00000001U) /*!< Timeout error                                                          */
00755 #define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized                                             */
00756 #define HAL_FDCAN_ERROR_NOT_READY       ((uint32_t)0x00000004U) /*!< Peripheral not ready                                                   */
00757 #define HAL_FDCAN_ERROR_NOT_STARTED     ((uint32_t)0x00000008U) /*!< Peripheral not started                                                 */
00758 #define HAL_FDCAN_ERROR_NOT_SUPPORTED   ((uint32_t)0x00000010U) /*!< Mode not supported                                                     */
00759 #define HAL_FDCAN_ERROR_PARAM           ((uint32_t)0x00000020U) /*!< Parameter error                                                        */
00760 #define HAL_FDCAN_ERROR_PENDING         ((uint32_t)0x00000040U) /*!< Pending operation                                                      */
00761 #define HAL_FDCAN_ERROR_RAM_ACCESS      ((uint32_t)0x00000080U) /*!< Message RAM Access Failure                                             */
00762 #define HAL_FDCAN_ERROR_LOG_OVERFLOW    FDCAN_IR_ELO            /*!< Overflow of CAN Error Logging Counter                                  */
00763 #define HAL_FDCAN_ERROR_RAM_WDG         FDCAN_IR_WDI            /*!< Message RAM Watchdog event occurred                                    */
00764 #define HAL_FDCAN_ERROR_PROTOCOL_ARBT   FDCAN_IR_PEA            /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used)         */
00765 #define HAL_FDCAN_ERROR_PROTOCOL_DATA   FDCAN_IR_PED            /*!< Protocol Error in Data Phase (Data Bit Time is used)                   */
00766 #define HAL_FDCAN_ERROR_RESEVED_AREA    FDCAN_IR_ARA            /*!< Access to Reserved Address                                             */
00767 #define HAL_FDCAN_ERROR_TT_GLOBAL_TIME  FDCAN_TTIR_GTE          /*!< Global Time Error : Synchronization deviation exceeded limit           */
00768 #define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU          /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */
00769 #define HAL_FDCAN_ERROR_TT_TX_OVERFLOW  FDCAN_TTIR_TXO          /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle  */
00770 #define HAL_FDCAN_ERROR_TT_SCHEDULE1    FDCAN_TTIR_SE1          /*!< Scheduling error 1                                                     */
00771 #define HAL_FDCAN_ERROR_TT_SCHEDULE2    FDCAN_TTIR_SE2          /*!< Scheduling error 2                                                     */
00772 #define HAL_FDCAN_ERROR_TT_NO_INIT_REF  FDCAN_TTIR_IWT          /*!< No system startup due to missing reference message                     */
00773 #define HAL_FDCAN_ERROR_TT_NO_REF       FDCAN_TTIR_WT           /*!< Missing reference message                                              */
00774 #define HAL_FDCAN_ERROR_TT_APPL_WDG     FDCAN_TTIR_AW           /*!< Application watchdog not served in time                                */
00775 #define HAL_FDCAN_ERROR_TT_CONFIG       FDCAN_TTIR_CER          /*!< Error found in trigger list                                            */
00776 /**
00777   * @}
00778   */
00779
00780 /** @defgroup FDCAN_frame_format FDCAN Frame Format
00781   * @{
00782   */
00783 #define FDCAN_FRAME_CLASSIC   ((uint32_t)0x00000000U)                         /*!< Classic mode                      */
00784 #define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)                     /*!< FD mode without BitRate Switshing */
00785 #define FDCAN_FRAME_FD_BRS    ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switshing    */
00786 /**
00787   * @}
00788   */
00789
00790 /** @defgroup FDCAN_operating_mode FDCAN Operating Mode
00791   * @{
00792   */
00793 #define FDCAN_MODE_NORMAL               ((uint32_t)0x00000000U) /*!< Normal mode               */
00794 #define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */
00795 #define FDCAN_MODE_BUS_MONITORING       ((uint32_t)0x00000002U) /*!< Bus Monitoring mode       */
00796 #define FDCAN_MODE_INTERNAL_LOOPBACK    ((uint32_t)0x00000003U) /*!< Internal LoopBack mode    */
00797 #define FDCAN_MODE_EXTERNAL_LOOPBACK    ((uint32_t)0x00000004U) /*!< External LoopBack mode    */
00798 /**
00799   * @}
00800   */
00801
00802 /** @defgroup FDCAN_clock_divider FDCAN Clock Divider
00803   * @{
00804   */
00805 #define FDCAN_CLOCK_DIV1  ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1  */
00806 #define FDCAN_CLOCK_DIV2  ((uint32_t)0x00010000U) /*!< Divide kernel clock by 2  */
00807 #define FDCAN_CLOCK_DIV4  ((uint32_t)0x00020000U) /*!< Divide kernel clock by 4  */
00808 #define FDCAN_CLOCK_DIV6  ((uint32_t)0x00030000U) /*!< Divide kernel clock by 6  */
00809 #define FDCAN_CLOCK_DIV8  ((uint32_t)0x00040000U) /*!< Divide kernel clock by 8  */
00810 #define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U) /*!< Divide kernel clock by 10 */
00811 #define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U) /*!< Divide kernel clock by 12 */
00812 #define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U) /*!< Divide kernel clock by 14 */
00813 #define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U) /*!< Divide kernel clock by 16 */
00814 #define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U) /*!< Divide kernel clock by 18 */
00815 #define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U) /*!< Divide kernel clock by 20 */
00816 #define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U) /*!< Divide kernel clock by 22 */
00817 #define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U) /*!< Divide kernel clock by 24 */
00818 #define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U) /*!< Divide kernel clock by 26 */
00819 #define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U) /*!< Divide kernel clock by 28 */
00820 #define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U) /*!< Divide kernel clock by 30 */
00821 /**
00822   * @}
00823   */
00824
00825 /** @defgroup FDCAN_calibration_field_length FDCAN Calibration Field Length
00826   * @{
00827   */
00828 #define FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U)       /*!< Calibration field length is 32 bits */
00829 #define FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL) /*!< Calibration field length is 64 bits */
00830 /**
00831   * @}
00832   */
00833
00834 /** @defgroup FDCAN_calibration_state FDCAN Calibration State
00835   * @{
00836   */
00837 #define FDCAN_CLOCK_NOT_CALIBRATED       ((uint32_t)0x00000000U) /*!< Clock not calibrated       */
00838 #define FDCAN_CLOCK_BASIC_CALIBRATED     ((uint32_t)0x40000000U) /*!< Clock basic calibrated     */
00839 #define FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U) /*!< Clock precision calibrated */
00840 /**
00841   * @}
00842   */
00843
00844 /** @defgroup FDCAN_calibration_counter FDCAN Calibration Counter
00845   * @{
00846   */
00847 #define FDCAN_CALIB_TIME_QUANTA_COUNTER  ((uint32_t)0x00000000U) /*!< Time Quanta Counter             */
00848 #define FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U) /*!< Oscillator Clock Period Counter */
00849 #define FDCAN_CALIB_WATCHDOG_COUNTER     ((uint32_t)0x00000002U) /*!< Calibration Watchdog Counter    */
00850 /**
00851   * @}
00852   */
00853
00854 /** @defgroup FDCAN_data_field_size FDCAN Data Field Size
00855   * @{
00856   */
00857 #define FDCAN_DATA_BYTES_8  ((uint32_t)0x00000004U) /*!< 8 bytes data field  */
00858 #define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */
00859 #define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */
00860 #define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */
00861 #define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */
00862 #define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */
00863 #define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
00864 #define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */
00865 /**
00866   * @}
00867   */
00868
00869 /** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode
00870   * @{
00871   */
00872 #define FDCAN_TX_FIFO_OPERATION  ((uint32_t)0x00000000U)     /*!< FIFO mode  */
00873 #define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */
00874 /**
00875   * @}
00876   */
00877
00878 /** @defgroup FDCAN_id_type FDCAN ID Type
00879   * @{
00880   */
00881 #define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */
00882 #define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */
00883 /**
00884   * @}
00885   */
00886
00887 /** @defgroup FDCAN_frame_type FDCAN Frame Type
00888   * @{
00889   */
00890 #define FDCAN_DATA_FRAME   ((uint32_t)0x00000000U)  /*!< Data frame   */
00891 #define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)  /*!< Remote frame */
00892 /**
00893   * @}
00894   */
00895
00896 /** @defgroup FDCAN_data_length_code FDCAN Data Length Code
00897   * @{
00898   */
00899 #define FDCAN_DLC_BYTES_0  ((uint32_t)0x00000000U) /*!< 0 bytes data field  */
00900 #define FDCAN_DLC_BYTES_1  ((uint32_t)0x00010000U) /*!< 1 bytes data field  */
00901 #define FDCAN_DLC_BYTES_2  ((uint32_t)0x00020000U) /*!< 2 bytes data field  */
00902 #define FDCAN_DLC_BYTES_3  ((uint32_t)0x00030000U) /*!< 3 bytes data field  */
00903 #define FDCAN_DLC_BYTES_4  ((uint32_t)0x00040000U) /*!< 4 bytes data field  */
00904 #define FDCAN_DLC_BYTES_5  ((uint32_t)0x00050000U) /*!< 5 bytes data field  */
00905 #define FDCAN_DLC_BYTES_6  ((uint32_t)0x00060000U) /*!< 6 bytes data field  */
00906 #define FDCAN_DLC_BYTES_7  ((uint32_t)0x00070000U) /*!< 7 bytes data field  */
00907 #define FDCAN_DLC_BYTES_8  ((uint32_t)0x00080000U) /*!< 8 bytes data field  */
00908 #define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
00909 #define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
00910 #define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
00911 #define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
00912 #define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
00913 #define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
00914 #define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */
00915 /**
00916   * @}
00917   */
00918
00919 /** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator
00920   * @{
00921   */
00922 #define FDCAN_ESI_ACTIVE  ((uint32_t)0x00000000U) /*!< Transmitting node is error active  */
00923 #define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */
00924 /**
00925   * @}
00926   */
00927
00928 /** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching
00929   * @{
00930   */
00931 #define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */
00932 #define FDCAN_BRS_ON  ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching    */
00933 /**
00934   * @}
00935   */
00936
00937 /** @defgroup FDCAN_format FDCAN format
00938   * @{
00939   */
00940 #define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */
00941 #define FDCAN_FD_CAN      ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format       */
00942 /**
00943   * @}
00944   */
00945
00946 /** @defgroup FDCAN_EFC FDCAN Event FIFO control
00947   * @{
00948   */
00949 #define FDCAN_NO_TX_EVENTS    ((uint32_t)0x00000000U) /*!< Do not store Tx events */
00950 #define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events        */
00951 /**
00952   * @}
00953   */
00954
00955 /** @defgroup FDCAN_filter_type FDCAN Filter Type
00956   * @{
00957   */
00958 #define FDCAN_FILTER_RANGE         ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2                        */
00959 #define FDCAN_FILTER_DUAL          ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2                       */
00960 #define FDCAN_FILTER_MASK          ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask            */
00961 #define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */
00962 /**
00963   * @}
00964   */
00965
00966 /** @defgroup FDCAN_filter_config FDCAN Filter Configuration
00967   * @{
00968   */
00969 #define FDCAN_FILTER_DISABLE       ((uint32_t)0x00000000U) /*!< Disable filter element                                    */
00970 #define FDCAN_FILTER_TO_RXFIFO0    ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches                      */
00971 #define FDCAN_FILTER_TO_RXFIFO1    ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches                      */
00972 #define FDCAN_FILTER_REJECT        ((uint32_t)0x00000003U) /*!< Reject ID if filter matches                               */
00973 #define FDCAN_FILTER_HP            ((uint32_t)0x00000004U) /*!< Set high priority if filter matches                       */
00974 #define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches   */
00975 #define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches   */
00976 #define FDCAN_FILTER_TO_RXBUFFER   ((uint32_t)0x00000007U) /*!< Store into Rx Buffer, configuration of FilterType ignored */
00977 /**
00978   * @}
00979   */
00980
00981 /** @defgroup FDCAN_Tx_location FDCAN Tx Location
00982   * @{
00983   */
00984 #define FDCAN_TX_BUFFER0  ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0  */
00985 #define FDCAN_TX_BUFFER1  ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1  */
00986 #define FDCAN_TX_BUFFER2  ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2  */
00987 #define FDCAN_TX_BUFFER3  ((uint32_t)0x00000008U) /*!< Add message to Tx Buffer 3  */
00988 #define FDCAN_TX_BUFFER4  ((uint32_t)0x00000010U) /*!< Add message to Tx Buffer 4  */
00989 #define FDCAN_TX_BUFFER5  ((uint32_t)0x00000020U) /*!< Add message to Tx Buffer 5  */
00990 #define FDCAN_TX_BUFFER6  ((uint32_t)0x00000040U) /*!< Add message to Tx Buffer 6  */
00991 #define FDCAN_TX_BUFFER7  ((uint32_t)0x00000080U) /*!< Add message to Tx Buffer 7  */
00992 #define FDCAN_TX_BUFFER8  ((uint32_t)0x00000100U) /*!< Add message to Tx Buffer 8  */
00993 #define FDCAN_TX_BUFFER9  ((uint32_t)0x00000200U) /*!< Add message to Tx Buffer 9  */
00994 #define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U) /*!< Add message to Tx Buffer 10 */
00995 #define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U) /*!< Add message to Tx Buffer 11 */
00996 #define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U) /*!< Add message to Tx Buffer 12 */
00997 #define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U) /*!< Add message to Tx Buffer 13 */
00998 #define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U) /*!< Add message to Tx Buffer 14 */
00999 #define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U) /*!< Add message to Tx Buffer 15 */
01000 #define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U) /*!< Add message to Tx Buffer 16 */
01001 #define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U) /*!< Add message to Tx Buffer 17 */
01002 #define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U) /*!< Add message to Tx Buffer 18 */
01003 #define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U) /*!< Add message to Tx Buffer 19 */
01004 #define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U) /*!< Add message to Tx Buffer 20 */
01005 #define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U) /*!< Add message to Tx Buffer 21 */
01006 #define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U) /*!< Add message to Tx Buffer 22 */
01007 #define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U) /*!< Add message to Tx Buffer 23 */
01008 #define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U) /*!< Add message to Tx Buffer 24 */
01009 #define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U) /*!< Add message to Tx Buffer 25 */
01010 #define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U) /*!< Add message to Tx Buffer 26 */
01011 #define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U) /*!< Add message to Tx Buffer 27 */
01012 #define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U) /*!< Add message to Tx Buffer 28 */
01013 #define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U) /*!< Add message to Tx Buffer 29 */
01014 #define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U) /*!< Add message to Tx Buffer 30 */
01015 #define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U) /*!< Add message to Tx Buffer 31 */
01016 /**
01017   * @}
01018   */
01019
01020 /** @defgroup FDCAN_Rx_location FDCAN Rx Location
01021   * @{
01022   */
01023 #define FDCAN_RX_FIFO0    ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0    */
01024 #define FDCAN_RX_FIFO1    ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1    */
01025 #define FDCAN_RX_BUFFER0  ((uint32_t)0x00000000U) /*!< Get received message from Rx Buffer 0  */
01026 #define FDCAN_RX_BUFFER1  ((uint32_t)0x00000001U) /*!< Get received message from Rx Buffer 1  */
01027 #define FDCAN_RX_BUFFER2  ((uint32_t)0x00000002U) /*!< Get received message from Rx Buffer 2  */
01028 #define FDCAN_RX_BUFFER3  ((uint32_t)0x00000003U) /*!< Get received message from Rx Buffer 3  */
01029 #define FDCAN_RX_BUFFER4  ((uint32_t)0x00000004U) /*!< Get received message from Rx Buffer 4  */
01030 #define FDCAN_RX_BUFFER5  ((uint32_t)0x00000005U) /*!< Get received message from Rx Buffer 5  */
01031 #define FDCAN_RX_BUFFER6  ((uint32_t)0x00000006U) /*!< Get received message from Rx Buffer 6  */
01032 #define FDCAN_RX_BUFFER7  ((uint32_t)0x00000007U) /*!< Get received message from Rx Buffer 7  */
01033 #define FDCAN_RX_BUFFER8  ((uint32_t)0x00000008U) /*!< Get received message from Rx Buffer 8  */
01034 #define FDCAN_RX_BUFFER9  ((uint32_t)0x00000009U) /*!< Get received message from Rx Buffer 9  */
01035 #define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU) /*!< Get received message from Rx Buffer 10 */
01036 #define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU) /*!< Get received message from Rx Buffer 11 */
01037 #define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU) /*!< Get received message from Rx Buffer 12 */
01038 #define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU) /*!< Get received message from Rx Buffer 13 */
01039 #define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU) /*!< Get received message from Rx Buffer 14 */
01040 #define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU) /*!< Get received message from Rx Buffer 15 */
01041 #define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U) /*!< Get received message from Rx Buffer 16 */
01042 #define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U) /*!< Get received message from Rx Buffer 17 */
01043 #define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U) /*!< Get received message from Rx Buffer 18 */
01044 #define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U) /*!< Get received message from Rx Buffer 19 */
01045 #define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U) /*!< Get received message from Rx Buffer 20 */
01046 #define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U) /*!< Get received message from Rx Buffer 21 */
01047 #define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U) /*!< Get received message from Rx Buffer 22 */
01048 #define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U) /*!< Get received message from Rx Buffer 23 */
01049 #define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U) /*!< Get received message from Rx Buffer 24 */
01050 #define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U) /*!< Get received message from Rx Buffer 25 */
01051 #define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU) /*!< Get received message from Rx Buffer 26 */
01052 #define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU) /*!< Get received message from Rx Buffer 27 */
01053 #define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU) /*!< Get received message from Rx Buffer 28 */
01054 #define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU) /*!< Get received message from Rx Buffer 29 */
01055 #define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU) /*!< Get received message from Rx Buffer 30 */
01056 #define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU) /*!< Get received message from Rx Buffer 31 */
01057 #define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U) /*!< Get received message from Rx Buffer 32 */
01058 #define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U) /*!< Get received message from Rx Buffer 33 */
01059 #define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U) /*!< Get received message from Rx Buffer 34 */
01060 #define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U) /*!< Get received message from Rx Buffer 35 */
01061 #define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U) /*!< Get received message from Rx Buffer 36 */
01062 #define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U) /*!< Get received message from Rx Buffer 37 */
01063 #define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U) /*!< Get received message from Rx Buffer 38 */
01064 #define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U) /*!< Get received message from Rx Buffer 39 */
01065 #define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U) /*!< Get received message from Rx Buffer 40 */
01066 #define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U) /*!< Get received message from Rx Buffer 41 */
01067 #define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU) /*!< Get received message from Rx Buffer 42 */
01068 #define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU) /*!< Get received message from Rx Buffer 43 */
01069 #define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU) /*!< Get received message from Rx Buffer 44 */
01070 #define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU) /*!< Get received message from Rx Buffer 45 */
01071 #define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU) /*!< Get received message from Rx Buffer 46 */
01072 #define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU) /*!< Get received message from Rx Buffer 47 */
01073 #define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U) /*!< Get received message from Rx Buffer 48 */
01074 #define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U) /*!< Get received message from Rx Buffer 49 */
01075 #define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U) /*!< Get received message from Rx Buffer 50 */
01076 #define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U) /*!< Get received message from Rx Buffer 51 */
01077 #define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U) /*!< Get received message from Rx Buffer 52 */
01078 #define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U) /*!< Get received message from Rx Buffer 53 */
01079 #define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U) /*!< Get received message from Rx Buffer 54 */
01080 #define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U) /*!< Get received message from Rx Buffer 55 */
01081 #define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U) /*!< Get received message from Rx Buffer 56 */
01082 #define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U) /*!< Get received message from Rx Buffer 57 */
01083 #define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU) /*!< Get received message from Rx Buffer 58 */
01084 #define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU) /*!< Get received message from Rx Buffer 59 */
01085 #define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU) /*!< Get received message from Rx Buffer 60 */
01086 #define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU) /*!< Get received message from Rx Buffer 61 */
01087 #define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU) /*!< Get received message from Rx Buffer 62 */
01088 #define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU) /*!< Get received message from Rx Buffer 63 */
01089 /**
01090   * @}
01091   */
01092
01093 /** @defgroup FDCAN_event_type FDCAN Event Type
01094   * @{
01095   */
01096 #define FDCAN_TX_EVENT             ((uint32_t)0x00400000U) /*!< Tx event                              */
01097 #define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */
01098 /**
01099   * @}
01100   */
01101
01102 /** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage
01103   * @{
01104   */
01105 #define FDCAN_HP_STORAGE_NO_FIFO  ((uint32_t)0x00000000U) /*!< No FIFO selected         */
01106 #define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost        */
01107 #define FDCAN_HP_STORAGE_RXFIFO0  ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */
01108 #define FDCAN_HP_STORAGE_RXFIFO1  ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */
01109 /**
01110   * @}
01111   */
01112
01113 /** @defgroup FDCAN_protocol_error_code FDCAN protocol error code
01114   * @{
01115   */
01116 #define FDCAN_PROTOCOL_ERROR_NONE      ((uint32_t)0x00000000U) /*!< No error occurred         */
01117 #define FDCAN_PROTOCOL_ERROR_STUFF     ((uint32_t)0x00000001U) /*!< Stuff error               */
01118 #define FDCAN_PROTOCOL_ERROR_FORM      ((uint32_t)0x00000002U) /*!< Form error                */
01119 #define FDCAN_PROTOCOL_ERROR_ACK       ((uint32_t)0x00000003U) /*!< Acknowledge error         */
01120 #define FDCAN_PROTOCOL_ERROR_BIT1      ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error   */
01121 #define FDCAN_PROTOCOL_ERROR_BIT0      ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error    */
01122 #define FDCAN_PROTOCOL_ERROR_CRC       ((uint32_t)0x00000006U) /*!< CRC check sum error       */
01123 #define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */
01124 /**
01125   * @}
01126   */
01127
01128 /** @defgroup FDCAN_communication_state FDCAN communication state
01129   * @{
01130   */
01131 #define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */
01132 #define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter   */
01133 #define FDCAN_COM_STATE_RX   ((uint32_t)0x00000016U) /*!< Node is operating as receiver              */
01134 #define FDCAN_COM_STATE_TX   ((uint32_t)0x00000024U) /*!< Node is operating as transmitter           */
01135 /**
01136   * @}
01137   */
01138
01139 /** @defgroup FDCAN_FIFO_watermark FDCAN FIFO watermark
01140   * @{
01141   */
01142 #define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U) /*!< Tx event FIFO */
01143 #define FDCAN_CFG_RX_FIFO0      ((uint32_t)0x00000001U) /*!< Rx FIFO0      */
01144 #define FDCAN_CFG_RX_FIFO1      ((uint32_t)0x00000002U) /*!< Rx FIFO1      */
01145 /**
01146   * @}
01147   */
01148
01149 /** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode
01150   * @{
01151   */
01152 #define FDCAN_RX_FIFO_BLOCKING  ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode  */
01153 #define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U) /*!< Rx FIFO overwrite mode */
01154 /**
01155   * @}
01156   */
01157
01158 /** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames
01159   * @{
01160   */
01161 #define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */
01162 #define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */
01163 #define FDCAN_REJECT             ((uint32_t)0x00000002U) /*!< Reject              */
01164 /**
01165   * @}
01166   */
01167
01168 /** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line
01169   * @{
01170   */
01171 #define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */
01172 #define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */
01173 /**
01174   * @}
01175   */
01176
01177 /** @defgroup FDCAN_Timestamp FDCAN timestamp
01178   * @{
01179   */
01180 #define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */
01181 #define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used                */
01182 /**
01183   * @}
01184   */
01185
01186 /** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler
01187   * @{
01188   */
01189 #define FDCAN_TIMESTAMP_PRESC_1  ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time                 */
01190 #define FDCAN_TIMESTAMP_PRESC_2  ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 2  */
01191 #define FDCAN_TIMESTAMP_PRESC_3  ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 3  */
01192 #define FDCAN_TIMESTAMP_PRESC_4  ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 4  */
01193 #define FDCAN_TIMESTAMP_PRESC_5  ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 5  */
01194 #define FDCAN_TIMESTAMP_PRESC_6  ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 6  */
01195 #define FDCAN_TIMESTAMP_PRESC_7  ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 7  */
01196 #define FDCAN_TIMESTAMP_PRESC_8  ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 8  */
01197 #define FDCAN_TIMESTAMP_PRESC_9  ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 9  */
01198 #define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 10 */
01199 #define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 11 */
01200 #define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 12 */
01201 #define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 13 */
01202 #define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 14 */
01203 #define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 15 */
01204 #define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 16 */
01205 /**
01206   * @}
01207   */
01208
01209 /** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation
01210   * @{
01211   */
01212 #define FDCAN_TIMEOUT_CONTINUOUS    ((uint32_t)0x00000000U) /*!< Timeout continuous operation        */
01213 #define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */
01214 #define FDCAN_TIMEOUT_RX_FIFO0      ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0     */
01215 #define FDCAN_TIMEOUT_RX_FIFO1      ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1     */
01216 /**
01217   * @}
01218   */
01219
01220 /** @defgroup FDCAN_TT_Reference_Message_Payload FDCAN TT reference message payload
01221   * @{
01222   */
01223 #define FDCAN_TT_REF_MESSAGE_NO_PAYLOAD  ((uint32_t)0x00000000U)      /*!< Reference message has no additional payload  */
01224 #define FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS) /*!< Additional payload is taken from Tx Buffer 0 */
01225 /**
01226   * @}
01227   */
01228
01229 /** @defgroup FDCAN_TT_Repeat_Factor FDCAN TT repeat factor
01230   * @{
01231   */
01232 #define FDCAN_TT_REPEAT_EVERY_CYCLE      ((uint32_t)0x00000000U) /*!< Trigger valid for all cycles   */
01233 #define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE  ((uint32_t)0x00000002U) /*!< Trigger valid every 2dn cycle  */
01234 #define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE  ((uint32_t)0x00000004U) /*!< Trigger valid every 4th cycle  */
01235 #define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE  ((uint32_t)0x00000008U) /*!< Trigger valid every 8th cycle  */
01236 #define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U) /*!< Trigger valid every 16th cycle */
01237 #define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U) /*!< Trigger valid every 32nd cycle */
01238 #define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U) /*!< Trigger valid every 64th cycle */
01239 /**
01240   * @}
01241   */
01242
01243 /** @defgroup FDCAN_TT_Trigger_Type FDCAN TT trigger type
01244   * @{
01245   */
01246 #define FDCAN_TT_TX_REF_TRIGGER         ((uint32_t)0x00000000U) /*!< Transmit reference message in strictly time-triggered operation                                                     */
01247 #define FDCAN_TT_TX_REF_TRIGGER_GAP     ((uint32_t)0x00000001U) /*!< Transmit reference message in external event-synchronized time-triggered operation                                  */
01248 #define FDCAN_TT_TX_TRIGGER_SINGLE      ((uint32_t)0x00000002U) /*!< Start a single transmission in an exclusive time window                                                             */
01249 #define FDCAN_TT_TX_TRIGGER_CONTINUOUS  ((uint32_t)0x00000003U) /*!< Start a continuous transmission in an exclusive time window                                                         */
01250 #define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U) /*!< Start a transmission in an arbitration time window                                                                  */
01251 #define FDCAN_TT_TX_TRIGGER_MERGED      ((uint32_t)0x00000005U) /*!< Start a merged arbitration window                                                                                   */
01252 #define FDCAN_TT_WATCH_TRIGGER          ((uint32_t)0x00000006U) /*!< Check for missing reference messages in strictly time-triggered operation                                           */
01253 #define FDCAN_TT_WATCH_TRIGGER_GAP      ((uint32_t)0x00000007U) /*!< Check for missing reference messages in external event-synchronized time-triggered operation                        */
01254 #define FDCAN_TT_RX_TRIGGER             ((uint32_t)0x00000008U) /*!< Check for the reception of periodic messages in exclusive time windows                                              */
01255 #define FDCAN_TT_TIME_BASE_TRIGGER      ((uint32_t)0x00000009U) /*!< Generate internal/external events depending on TmEventInt/TmEventExt configuration                                  */
01256 #define FDCAN_TT_END_OF_LIST            ((uint32_t)0x0000000AU) /*!< Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP */
01257 /**
01258   * @}
01259   */
01260
01261 /** @defgroup FDCAN_TT_Time_Mark_Event_Internal FDCAN TT time mark event internal
01262   * @{
01263   */
01264 #define FDCAN_TT_TM_NO_INTERNAL_EVENT  ((uint32_t)0x00000000U) /*!< No action                                               */
01265 #define FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U) /*!< Internal event is generated when trigger becomes active */
01266 /**
01267   * @}
01268   */
01269
01270 /** @defgroup FDCAN_TT_Time_Mark_Event_External FDCAN TT time mark event external
01271   * @{
01272   */
01273 #define FDCAN_TT_TM_NO_EXTERNAL_EVENT  ((uint32_t)0x00000000U) /*!< No action                                                       */
01274 #define FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U) /*!< External event (pulse) is generated when trigger becomes active */
01275 /**
01276   * @}
01277   */
01278
01279 /** @defgroup FDCAN_operation_mode FDCAN Operation Mode
01280   * @{
01281   */
01282 #define FDCAN_TT_COMMUNICATION_LEVEL1    ((uint32_t)0x00000001U) /*!< Time triggered communication, level 1 */
01283 #define FDCAN_TT_COMMUNICATION_LEVEL2    ((uint32_t)0x00000002U) /*!< Time triggered communication, level 2 */
01284 #define FDCAN_TT_COMMUNICATION_LEVEL0    ((uint32_t)0x00000003U) /*!< Time triggered communication, level 0 */
01285 /**
01286   * @}
01287   */
01288
01289 /** @defgroup FDCAN_TT_operation FDCAN TT Operation
01290   * @{
01291   */
01292 #define FDCAN_STRICTLY_TT_OPERATION     ((uint32_t)0x00000000U)     /*!< Strictly time-triggered operation                    */
01293 #define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN) /*!< External event-synchronized time-triggered operation */
01294 /**
01295   * @}
01296   */
01297
01298 /** @defgroup FDCAN_TT_time_master FDCAN TT Time Master
01299   * @{
01300   */
01301 #define FDCAN_TT_SLAVE            ((uint32_t)0x00000000U)    /*!< Time slave            */
01302 #define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM) /*!< Potential time master */
01303 /**
01304   * @}
01305   */
01306
01307 /** @defgroup FDCAN_TT_external_clk_sync FDCAN TT External Clock Synchronization
01308   * @{
01309   */
01310 #define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U)      /*!< External clock synchronization in Level 0,2 disabled */
01311 #define FDCAN_TT_EXT_CLK_SYNC_ENABLE  ((uint32_t)FDCAN_TTOCF_EECS) /*!< External clock synchronization in Level 0,2 enabled  */
01312 /**
01313   * @}
01314   */
01315
01316 /** @defgroup FDCAN_TT_global_time_filtering FDCAN TT Global Time Filtering
01317   * @{
01318   */
01319 #define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U)      /*!< Global time filtering in Level 0,2 disabled */
01320 #define FDCAN_TT_GLOB_TIME_FILT_ENABLE  ((uint32_t)FDCAN_TTOCF_EGTF) /*!< Global time filtering in Level 0,2 enabled  */
01321 /**
01322   * @}
01323   */
01324
01325 /** @defgroup FDCAN_TT_auto_clk_calibration FDCAN TT Automatic Clock Calibration
01326   * @{
01327   */
01328 #define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U)     /*!< Automatic clock calibration in Level 0,2 disabled */
01329 #define FDCAN_TT_AUTO_CLK_CALIB_ENABLE  ((uint32_t)FDCAN_TTOCF_ECC) /*!< Automatic clock calibration in Level 0,2 enabled  */
01330 /**
01331   * @}
01332   */
01333
01334 /** @defgroup FDCAN_TT_event_trig_polarity FDCAN TT Event Trigger Polarity
01335   * @{
01336   */
01337 #define FDCAN_TT_EVT_TRIG_POL_RISING  ((uint32_t)0x00000000U)      /*!< Rising edge trigger  */
01338 #define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP) /*!< Falling edge trigger */
01339 /**
01340   * @}
01341   */
01342
01343 /** @defgroup FDCAN_TT_basic_cycle_number FDCAN TT Basic Cycle Number
01344   * @{
01345   */
01346 #define FDCAN_TT_CYCLES_PER_MATRIX_1  ((uint32_t)0x00000000U) /*!< 1 Basic Cycle per Matrix   */
01347 #define FDCAN_TT_CYCLES_PER_MATRIX_2  ((uint32_t)0x00000001U) /*!< 2 Basic Cycles per Matrix  */
01348 #define FDCAN_TT_CYCLES_PER_MATRIX_4  ((uint32_t)0x00000003U) /*!< 4 Basic Cycles per Matrix  */
01349 #define FDCAN_TT_CYCLES_PER_MATRIX_8  ((uint32_t)0x00000007U) /*!< 8 Basic Cycles per Matrix  */
01350 #define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU) /*!< 16 Basic Cycles per Matrix */
01351 #define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU) /*!< 32 Basic Cycles per Matrix */
01352 #define FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU) /*!< 64 Basic Cycles per Matrix */
01353 /**
01354   * @}
01355   */
01356
01357 /** @defgroup FDCAN_TT_cycle_start_sync FDCAN TT Cycle Start Sync
01358   * @{
01359   */
01360 #define FDCAN_TT_NO_SYNC_PULSE          ((uint32_t)0x00000000U) /*!< No sync pulse                      */
01361 #define FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U) /*!< Sync pulse at start of basic cycle */
01362 #define FDCAN_TT_SYNC_MATRIX_START      ((uint32_t)0x00000080U) /*!< Sync pulse at start of matrix      */
01363 /**
01364   * @}
01365   */
01366
01367 /** @defgroup FDCAN_TT_stop_watch_trig_selection FDCAN TT Stop Watch Trigger Selection
01368   * @{
01369   */
01370 #define FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as stop watch trigger  */
01371 #define FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U) /*!< TIM3 selected as stop watch trigger  */
01372 #define FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U) /*!< ETH selected as stop watch trigger   */
01373 #define FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U) /*!< HRTIM selected as stop watch trigger */
01374 /**
01375   * @}
01376   */
01377
01378 /** @defgroup FDCAN_TT_event_trig_selection FDCAN TT Event Trigger Selection
01379   * @{
01380   */
01381 #define FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as event trigger  */
01382 #define FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U) /*!< TIM3 selected as event trigger  */
01383 #define FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U) /*!< ETH selected as event trigger   */
01384 #define FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U) /*!< HRTIM selected as event trigger */
01385 /**
01386   * @}
01387   */
01388
01389 /** @defgroup FDCAN_TT_stop_watch_source FDCAN TT Stop Watch Source
01390   * @{
01391   */
01392 #define FDCAN_TT_STOP_WATCH_DISABLED    ((uint32_t)0x00000000U) /*!< Stop Watch disabled                                                        */
01393 #define FDCAN_TT_STOP_WATCH_CYCLE_TIME  ((uint32_t)0x00000008U) /*!< Actual value of cycle time is copied to Capture Time register (TTCPT.SWV)  */
01394 #define FDCAN_TT_STOP_WATCH_LOCAL_TIME  ((uint32_t)0x00000010U) /*!< Actual value of local time is copied to Capture Time register (TTCPT.SWV)  */
01395 #define FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U) /*!< Actual value of global time is copied to Capture Time register (TTCPT.SWV) */
01396 /**
01397   * @}
01398   */
01399
01400 /** @defgroup FDCAN_TT_stop_watch_polarity FDCAN TT Stop Watch Polarity
01401   * @{
01402   */
01403 #define FDCAN_TT_STOP_WATCH_RISING  ((uint32_t)0x00000000U) /*!< Selected stop watch source is captured at rising edge of fdcan1_swt  */
01404 #define FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U) /*!< Selected stop watch source is captured at falling edge of fdcan1_swt */
01405 /**
01406   * @}
01407   */
01408
01409 /** @defgroup FDCAN_TT_time_mark_source FDCAN TT Time Mark Source
01410   * @{
01411   */
01412 #define FDCAN_TT_REG_TIMEMARK_DIABLED  ((uint32_t)0x00000000U) /*!< No Register Time Mark Interrupt generated               */
01413 #define FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U) /*!< Register Time Mark Interrupt if Time Mark = cycle time  */
01414 #define FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U) /*!< Register Time Mark Interrupt if Time Mark = local time  */
01415 #define FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U) /*!< Register Time Mark Interrupt if Time Mark = global time */
01416 /**
01417   * @}
01418   */
01419
01420 /** @defgroup FDCAN_TT_error_level FDCAN TT Error Level
01421   * @{
01422   */
01423 #define FDCAN_TT_NO_ERROR     ((uint32_t)0x00000000U) /*!< Severity 0 - No Error     */
01424 #define FDCAN_TT_WARNING      ((uint32_t)0x00000001U) /*!< Severity 1 - Warning      */
01425 #define FDCAN_TT_ERROR        ((uint32_t)0x00000002U) /*!< Severity 2 - Error        */
01426 #define FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U) /*!< Severity 3 - Severe Error */
01427 /**
01428   * @}
01429   */
01430
01431 /** @defgroup FDCAN_TT_master_state FDCAN TT Master State
01432   * @{
01433   */
01434 #define FDCAN_TT_MASTER_OFF          ((uint32_t)0x00000000U) /*!< Master_Off, no master properties relevant */
01435 #define FDCAN_TT_TIME_SLAVE          ((uint32_t)0x00000004U) /*!< Operating as Time Slave                   */
01436 #define FDCAN_TT_BACKUP_TIME_MASTER  ((uint32_t)0x00000008U) /*!< Operating as Backup Time Master           */
01437 #define FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU) /*!< Operating as current Time Master          */
01438 /**
01439   * @}
01440   */
01441
01442 /** @defgroup FDCAN_TT_sync_state FDCAN TT Synchronization State
01443   * @{
01444   */
01445 #define FDCAN_TT_OUT_OF_SYNC   ((uint32_t)0x00000000U) /*!< Out of Synchronization         */
01446 #define FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U) /*!< Synchronizing to communication */
01447 #define FDCAN_TT_IN_GAP        ((uint32_t)0x00000020U) /*!< Schedule suspended by Gap      */
01448 #define FDCAN_TT_IN_SCHEDULE   ((uint32_t)0x00000030U) /*!< Synchronized to schedule       */
01449 /**
01450   * @}
01451   */
01452
01453 /** @defgroup Interrupt_Masks Interrupt masks
01454   * @{
01455   */
01456 #define FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU) /*!< FDCAN interrupts mask */
01457 #define CCU_IR_MASK   ((uint32_t)0xC0000000U) /*!< CCU interrupts mask   */
01458 /**
01459   * @}
01460   */
01461
01462 /** @defgroup FDCAN_flags FDCAN Flags
01463   * @{
01464   */
01465 #define FDCAN_FLAG_TX_COMPLETE             FDCAN_IR_TC             /*!< Transmission Completed                                */
01466 #define FDCAN_FLAG_TX_ABORT_COMPLETE       FDCAN_IR_TCF            /*!< Transmission Cancellation Finished                    */
01467 #define FDCAN_FLAG_TX_FIFO_EMPTY           FDCAN_IR_TFE            /*!< Tx FIFO Empty                                         */
01468 #define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG    FDCAN_IR_HPM            /*!< High priority message received                        */
01469 #define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE   FDCAN_IR_DRX            /*!< At least one received message stored into a Rx Buffer */
01470 #define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST    FDCAN_IR_TEFL           /*!< Tx Event FIFO element lost                            */
01471 #define FDCAN_FLAG_TX_EVT_FIFO_FULL        FDCAN_IR_TEFF           /*!< Tx Event FIFO full                                    */
01472 #define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK   FDCAN_IR_TEFW           /*!< Tx Event FIFO fill level reached watermark            */
01473 #define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA    FDCAN_IR_TEFN           /*!< Tx Handler wrote Tx Event FIFO element                */
01474 #define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST   FDCAN_IR_RF0L           /*!< Rx FIFO 0 message lost                                */
01475 #define FDCAN_FLAG_RX_FIFO0_FULL           FDCAN_IR_RF0F           /*!< Rx FIFO 0 full                                        */
01476 #define FDCAN_FLAG_RX_FIFO0_WATERMARK      FDCAN_IR_RF0W           /*!< Rx FIFO 0 fill level reached watermark                */
01477 #define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE    FDCAN_IR_RF0N           /*!< New message written to Rx FIFO 0                      */
01478 #define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST   FDCAN_IR_RF1L           /*!< Rx FIFO 1 message lost                                */
01479 #define FDCAN_FLAG_RX_FIFO1_FULL           FDCAN_IR_RF1F           /*!< Rx FIFO 1 full                                        */
01480 #define FDCAN_FLAG_RX_FIFO1_WATERMARK      FDCAN_IR_RF1W           /*!< Rx FIFO 1 fill level reached watermark                */
01481 #define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE    FDCAN_IR_RF1N           /*!< New message written to Rx FIFO 1                      */
01482 #define FDCAN_FLAG_RAM_ACCESS_FAILURE      FDCAN_IR_MRAF           /*!< Message RAM access failure occurred                   */
01483 #define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW  FDCAN_IR_ELO            /*!< Overflow of FDCAN Error Logging Counter occurred      */
01484 #define FDCAN_FLAG_ERROR_PASSIVE           FDCAN_IR_EP             /*!< Error_Passive status changed                          */
01485 #define FDCAN_FLAG_ERROR_WARNING           FDCAN_IR_EW             /*!< Error_Warning status changed                          */
01486 #define FDCAN_FLAG_BUS_OFF                 FDCAN_IR_BO             /*!< Bus_Off status changed                                */
01487 #define FDCAN_FLAG_RAM_WATCHDOG            FDCAN_IR_WDI            /*!< Message RAM Watchdog event due to missing READY       */
01488 #define FDCAN_FLAG_ARB_PROTOCOL_ERROR      FDCAN_IR_PEA            /*!< Protocol error in arbitration phase detected          */
01489 #define FDCAN_FLAG_DATA_PROTOCOL_ERROR     FDCAN_IR_PED            /*!< Protocol error in data phase detected                 */
01490 #define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA            /*!< Access to reserved address occurred                   */
01491 #define FDCAN_FLAG_TIMESTAMP_WRAPAROUND    FDCAN_IR_TSW            /*!< Timestamp counter wrapped around                      */
01492 #define FDCAN_FLAG_TIMEOUT_OCCURRED        FDCAN_IR_TOO            /*!< Timeout reached                                       */
01493 #define FDCAN_FLAG_CALIB_STATE_CHANGED     (FDCANCCU_IR_CSC << 30) /*!< Clock calibration state changed                       */
01494 #define FDCAN_FLAG_CALIB_WATCHDOG_EVENT    (FDCANCCU_IR_CWE << 30) /*!< Clock calibration watchdog event occurred             */
01495 /**
01496   * @}
01497   */
01498
01499 /** @defgroup FDCAN_Interrupts FDCAN Interrupts
01500   * @{
01501   */
01502
01503 /** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts
01504   * @{
01505   */
01506 #define FDCAN_IT_TX_COMPLETE           FDCAN_IE_TCE   /*!< Transmission Completed                                */
01507 #define FDCAN_IT_TX_ABORT_COMPLETE     FDCAN_IE_TCFE  /*!< Transmission Cancellation Finished                    */
01508 #define FDCAN_IT_TX_FIFO_EMPTY         FDCAN_IE_TFEE  /*!< Tx FIFO Empty                                         */
01509 /**
01510   * @}
01511   */
01512
01513 /** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts
01514   * @{
01515   */
01516 #define FDCAN_IT_RX_HIGH_PRIORITY_MSG  FDCAN_IE_HPME  /*!< High priority message received                        */
01517 #define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE  /*!< At least one received message stored into a Rx Buffer */
01518 /**
01519   * @}
01520   */
01521
01522 /** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts
01523   * @{
01524   */
01525 #define FDCAN_IT_TIMESTAMP_WRAPAROUND  FDCAN_IE_TSWE  /*!< Timestamp counter wrapped around                      */
01526 #define FDCAN_IT_TIMEOUT_OCCURRED      FDCAN_IE_TOOE  /*!< Timeout reached                                       */
01527 /**
01528   * @}
01529   */
01530
01531 /** @defgroup FDCAN_Clock_Calibration_Interrupts Clock Calibration Interrupts
01532   * @{
01533   */
01534 #define FDCAN_IT_CALIB_STATE_CHANGED  (FDCANCCU_IE_CSCE << 30) /*!< Clock calibration state changed           */
01535 #define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30) /*!< Clock calibration watchdog event occurred */
01536 /**
01537   * @}
01538   */
01539
01540 /** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts
01541   * @{
01542   */
01543 #define FDCAN_IT_TX_EVT_FIFO_ELT_LOST  FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost                 */
01544 #define FDCAN_IT_TX_EVT_FIFO_FULL      FDCAN_IE_TEFFE /*!< Tx Event FIFO full                         */
01545 #define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE /*!< Tx Event FIFO fill level reached watermark */
01546 #define FDCAN_IT_TX_EVT_FIFO_NEW_DATA  FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element     */
01547 /**
01548   * @}
01549   */
01550
01551 /** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts
01552   * @{
01553   */
01554 #define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost                 */
01555 #define FDCAN_IT_RX_FIFO0_FULL         FDCAN_IE_RF0FE /*!< Rx FIFO 0 full                         */
01556 #define FDCAN_IT_RX_FIFO0_WATERMARK    FDCAN_IE_RF0WE /*!< Rx FIFO 0 fill level reached watermark */
01557 #define FDCAN_IT_RX_FIFO0_NEW_MESSAGE  FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0       */
01558 /**
01559   * @}
01560   */
01561
01562 /** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts
01563   * @{
01564   */
01565 #define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost                 */
01566 #define FDCAN_IT_RX_FIFO1_FULL         FDCAN_IE_RF1FE /*!< Rx FIFO 1 full                         */
01567 #define FDCAN_IT_RX_FIFO1_WATERMARK    FDCAN_IE_RF1WE /*!< Rx FIFO 1 fill level reached watermark */
01568 #define FDCAN_IT_RX_FIFO1_NEW_MESSAGE  FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1       */
01569 /**
01570   * @}
01571   */
01572
01573 /** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts
01574   * @{
01575   */
01576 #define FDCAN_IT_RAM_ACCESS_FAILURE      FDCAN_IE_MRAFE /*!< Message RAM access failure occurred              */
01577 #define FDCAN_IT_ERROR_LOGGING_OVERFLOW  FDCAN_IE_ELOE  /*!< Overflow of FDCAN Error Logging Counter occurred */
01578 #define FDCAN_IT_ERROR_PASSIVE           FDCAN_IE_EPE   /*!< Error_Passive status changed                     */
01579 #define FDCAN_IT_ERROR_WARNING           FDCAN_IE_EWE   /*!< Error_Warning status changed                     */
01580 #define FDCAN_IT_BUS_OFF                 FDCAN_IE_BOE   /*!< Bus_Off status changed                           */
01581 #define FDCAN_IT_RAM_WATCHDOG            FDCAN_IE_WDIE  /*!< Message RAM Watchdog event due to missing READY  */
01582 #define FDCAN_IT_ARB_PROTOCOL_ERROR      FDCAN_IE_PEAE  /*!< Protocol error in arbitration phase detected     */
01583 #define FDCAN_IT_DATA_PROTOCOL_ERROR     FDCAN_IE_PEDE  /*!< Protocol error in data phase detected            */
01584 #define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE  /*!< Access to reserved address occurred              */
01585 /**
01586   * @}
01587   */
01588
01589 /**
01590   * @}
01591   */
01592
01593 /** @defgroup FDCAN_TTflags FDCAN TT Flags
01594   * @{
01595   */
01596 #define FDCAN_TT_FLAG_BASIC_CYCLE_START    FDCAN_TTIR_SBC  /*!< Start of Basic Cycle             */
01597 #define FDCAN_TT_FLAG_MATRIX_CYCLE_START   FDCAN_TTIR_SMC  /*!< Start of Matrix Cycle            */
01598 #define FDCAN_TT_FLAG_SYNC_MODE_CHANGE     FDCAN_TTIR_CSM  /*!< Change of Synchronization Mode   */
01599 #define FDCAN_TT_FLAG_START_OF_GAP         FDCAN_TTIR_SOG  /*!< Start of Gap                     */
01600 #define FDCAN_TT_FLAG_REG_TIME_MARK        FDCAN_TTIR_RTMI /*!< Register Time Mark Interrupt     */
01601 #define FDCAN_TT_FLAG_TRIG_TIME_MARK       FDCAN_TTIR_TTMI /*!< Trigger Time Mark Event Internal */
01602 #define FDCAN_TT_FLAG_STOP_WATCH           FDCAN_TTIR_SWE  /*!< Stop Watch Event                 */
01603 #define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP     FDCAN_TTIR_GTW  /*!< Global Time Wrap                 */
01604 #define FDCAN_TT_FLAG_GLOBAL_TIME_DISC     FDCAN_TTIR_GTD  /*!< Global Time Discontinuity        */
01605 #define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR    FDCAN_TTIR_GTE  /*!< Global Time Error                */
01606 #define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW   FDCAN_TTIR_TXU  /*!< Tx Count Underflow               */
01607 #define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW    FDCAN_TTIR_TXO  /*!< Tx Count Overflow                */
01608 #define FDCAN_TT_FLAG_SCHEDULING_ERROR_1   FDCAN_TTIR_SE1  /*!< Scheduling Error 1               */
01609 #define FDCAN_TT_FLAG_SCHEDULING_ERROR_2   FDCAN_TTIR_SE2  /*!< Scheduling Error 2               */
01610 #define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE   FDCAN_TTIR_ELC  /*!< Error Level Changed              */
01611 #define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER   FDCAN_TTIR_IWT  /*!< Initialization Watch Trigger     */
01612 #define FDCAN_TT_FLAG_WATCH_TRIGGER        FDCAN_TTIR_WT   /*!< Watch Trigger                    */
01613 #define FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW   /*!< Application Watchdog             */
01614 #define FDCAN_TT_FLAG_CONFIG_ERROR         FDCAN_TTIR_CER  /*!< Configuration Error              */
01615 /**
01616   * @}
01617   */
01618
01619 /** @defgroup FDCAN_TTInterrupts FDCAN TT Interrupts
01620   * @{
01621   */
01622
01623 /** @defgroup FDCAN_TTScheduleSynchronization_Interrupts FDCAN TT Schedule Synchronization Interrupts
01624   * @{
01625   */
01626 #define FDCAN_TT_IT_BASIC_CYCLE_START  FDCAN_TTIE_SBCE /*!< Start of Basic Cycle           */
01627 #define FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE /*!< Start of Matrix Cycle          */
01628 #define FDCAN_TT_IT_SYNC_MODE_CHANGE   FDCAN_TTIE_CSME /*!< Change of Synchronization Mode */
01629 #define FDCAN_TT_IT_START_OF_GAP       FDCAN_TTIE_SOGE /*!< Start of Gap                   */
01630 /**
01631   * @}
01632   */
01633
01634 /** @defgroup FDCAN_TTTimeMark_Interrupts FDCAN TT Time Mark Interrupts
01635   * @{
01636   */
01637 #define FDCAN_TT_IT_REG_TIME_MARK  FDCAN_TTIE_RTMIE /*!< Register Time Mark Interrupt     */
01638 #define FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE /*!< Trigger Time Mark Event Internal */
01639 /**
01640   * @}
01641   */
01642
01643 /** @defgroup FDCAN_TTStopWatch_Interrupt FDCAN TT Stop Watch Interrupt
01644   * @{
01645   */
01646 #define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE /*!< Stop Watch Event */
01647 /**
01648   * @}
01649   */
01650
01651 /** @defgroup FDCAN_TTGlobalTime_Interrupts FDCAN TT Global Time Interrupts
01652   * @{
01653   */
01654 #define FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE  /*!< Global Time Wrap          */
01655 #define FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE  /*!< Global Time Discontinuity */
01656 /**
01657   * @}
01658   */
01659
01660 /** @defgroup FDCAN_TTDisturbingError_Interrupts FDCAN TT Disturbing Error Interrupts
01661   * @{
01662   */
01663 #define FDCAN_TT_IT_GLOBAL_TIME_ERROR  FDCAN_TTIE_GTEE /*!< Global Time Error   */
01664 #define FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE /*!< Tx Count Underflow  */
01665 #define FDCAN_TT_IT_TX_COUNT_OVERFLOW  FDCAN_TTIE_TXOE /*!< Tx Count Overflow   */
01666 #define FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E /*!< Scheduling Error 1  */
01667 #define FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E /*!< Scheduling Error 2  */
01668 #define FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE /*!< Error Level Changed */
01669 /**
01670   * @}
01671   */
01672
01673 /** @defgroup FDCAN_TTFatalError_Interrupts FDCAN TT Fatal Error Interrupts
01674   * @{
01675   */
01676 #define FDCAN_TT_IT_INIT_WATCH_TRIGGER   FDCAN_TTIE_IWTE /*!< Initialization Watch Trigger */
01677 #define FDCAN_TT_IT_WATCH_TRIGGER        FDCAN_TTIE_WTE  /*!< Watch Trigger                */
01678 #define FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE  /*!< Application Watchdog         */
01679 #define FDCAN_TT_IT_CONFIG_ERROR         FDCAN_TTIE_CERE /*!< Configuration Error          */
01680 /**
01681   * @}
01682   */
01683
01684 /**
01685   * @}
01686   */
01687
01688 /**
01689   * @}
01690   */
01691
01692 /* Exported macro ------------------------------------------------------------*/
01693 /** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros
01694   * @{
01695   */
01696
01697 /** @brief Reset FDCAN handle state.
01698   * @param  __HANDLE__: FDCAN handle.
01699   * @retval None
01700   */
01701 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
01702
01703 /**
01704   * @brief  Enable the specified FDCAN interrupts.
01705   * @param  __HANDLE__: FDCAN handle.
01706   * @param  __INTERRUPT__: FDCAN interrupt.
01707   *          This parameter can be any combination of @arg FDCAN_Interrupts
01708   * @retval None
01709   */
01710 #define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__)             \
01711   do{                                                                \
01712     (__HANDLE__)->Instance->IE |= ((__INTERRUPT__) & FDCAN_IR_MASK); \
01713     FDCAN_CCU->IE |= (((__INTERRUPT__) & CCU_IR_MASK) >> 30);        \
01714   }while(0)
01715
01716
01717 /**
01718   * @brief  Disable the specified FDCAN interrupts.
01719   * @param  __HANDLE__: FDCAN handle.
01720   * @param  __INTERRUPT__: FDCAN interrupt.
01721   *          This parameter can be any combination of @arg FDCAN_Interrupts
01722   * @retval None
01723   */
01724 #define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__)               \
01725   do{                                                                   \
01726     ((__HANDLE__)->Instance->IE) &= ~((__INTERRUPT__) & FDCAN_IR_MASK); \
01727     FDCAN_CCU->IE &= ~(((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
01728   }while(0)
01729
01730 /**
01731   * @brief  Check whether the specified FDCAN interrupt is set or not.
01732   * @param  __HANDLE__: FDCAN handle.
01733   * @param  __INTERRUPT__: FDCAN interrupt.
01734   *          This parameter can be one of @arg FDCAN_Interrupts
01735   * @retval None
01736   */
01737 #define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
01738
01739 /**
01740   * @brief  Clear the specified FDCAN interrupts.
01741   * @param  __HANDLE__: FDCAN handle.
01742   * @param  __INTERRUPT__: specifies the interrupts to clear.
01743   *          This parameter can be any combination of @arg FDCAN_Interrupts
01744   * @retval None
01745   */
01746 #define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__)             \
01747 do{                                                              \
01748     ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \
01749     FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
01750   }while(0)
01751
01752 /**
01753   * @brief  Check whether the specified FDCAN flag is set or not.
01754   * @param  __HANDLE__: FDCAN handle.
01755   * @param  __FLAG__: FDCAN flag.
01756   *          This parameter can be one of @arg FDCAN_flags
01757   * @retval None
01758   */
01759 #define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
01760
01761 /**
01762   * @brief  Clear the specified FDCAN flags.
01763   * @param  __HANDLE__: FDCAN handle.
01764   * @param  __FLAG__: specifies the flags to clear.
01765   *          This parameter can be any combination of @arg FDCAN_flags
01766   * @retval None
01767   */
01768 #define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__)             \
01769 do{                                                              \
01770     ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \
01771     FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30);          \
01772   }while(0)
01773
01774 /** @brief  Check if the specified FDCAN interrupt source is enabled or disabled.
01775   * @param  __HANDLE__: FDCAN handle.
01776   * @param  __INTERRUPT__: specifies the FDCAN interrupt source to check.
01777   *          This parameter can be a value of @arg FDCAN_Interrupts
01778   * @retval None
01779   */
01780 #define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__)))
01781
01782 /**
01783   * @brief  Enable the specified FDCAN TT interrupts.
01784   * @param  __HANDLE__: FDCAN handle.
01785   * @param  __INTERRUPT__: FDCAN TT interrupt.
01786   *          This parameter can be any combination of @arg FDCAN_TTInterrupts
01787   * @retval None
01788   */
01789 #define __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__))
01790
01791 /**
01792   * @brief  Disable the specified FDCAN TT interrupts.
01793   * @param  __HANDLE__: FDCAN handle.
01794   * @param  __INTERRUPT__: FDCAN TT interrupt.
01795   *          This parameter can be any combination of @arg FDCAN_TTInterrupts
01796   * @retval None
01797   */
01798 #define __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__))
01799
01800 /**
01801   * @brief  Check whether the specified FDCAN TT interrupt is set or not.
01802   * @param  __HANDLE__: FDCAN handle.
01803   * @param  __INTERRUPT__: FDCAN TT interrupt.
01804   *          This parameter can be one of @arg FDCAN_TTInterrupts
01805   * @retval None
01806   */
01807 #define __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__))
01808
01809 /**
01810   * @brief  Clear the specified FDCAN TT interrupts.
01811   * @param  __HANDLE__: FDCAN handle.
01812   * @param  __INTERRUPT__: specifies the TT interrupts to clear.
01813   *          This parameter can be any combination of @arg FDCAN_TTInterrupts
01814   * @retval None
01815   */
01816 #define __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__))
01817
01818 /**
01819   * @brief  Check whether the specified FDCAN TT flag is set or not.
01820   * @param  __HANDLE__: FDCAN handle.
01821   * @param  __FLAG__: FDCAN TT flag.
01822   *          This parameter can be one of @arg FDCAN_TTflags
01823   * @retval None
01824   */
01825 #define __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__))
01826
01827 /**
01828   * @brief  Clear the specified FDCAN TT flags.
01829   * @param  __HANDLE__: FDCAN handle.
01830   * @param  __FLAG__: specifies the TT flags to clear.
01831   *          This parameter can be any combination of @arg FDCAN_TTflags
01832   * @retval None
01833   */
01834 #define __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__))
01835
01836 /** @brief  Check if the specified FDCAN TT interrupt source is enabled or disabled.
01837   * @param  __HANDLE__: FDCAN handle.
01838   * @param  __INTERRUPT__: specifies the FDCAN TT interrupt source to check.
01839   *          This parameter can be a value of @arg FDCAN_TTInterrupts
01840   * @retval None
01841   */
01842 #define __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__))
01843
01844 /**
01845   * @}
01846   */
01847
01848 /* Exported functions --------------------------------------------------------*/
01849 /** @addtogroup FDCAN_Exported_Functions
01850   * @{
01851   */
01852
01853 /** @addtogroup FDCAN_Exported_Functions_Group1
01854   * @{
01855   */
01856 /* Initialization and de-initialization functions *****************************/
01857 HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef* hfdcan);
01858 HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef* hfdcan);
01859 void              HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan);
01860 void              HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* hfdcan);
01861 HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
01862 HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
01863 /**
01864   * @}
01865   */
01866
01867 /** @addtogroup FDCAN_Exported_Functions_Group2
01868   * @{
01869   */
01870 /* Configuration functions ****************************************************/
01871 HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef* hfdcan, FDCAN_ClkCalUnitTypeDef* sCcuConfig);
01872 uint32_t          HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef* hfdcan);
01873 HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef* hfdcan);
01874 uint32_t          HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef* hfdcan, uint32_t Counter);
01875 HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef* hfdcan, FDCAN_FilterTypeDef* sFilterConfig);
01876 HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt);
01877 HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
01878 HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
01879 HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark);
01880 HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue);
01881 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
01882 HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
01883 HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
01884 uint16_t          HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
01885 HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
01886 HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod);
01887 HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
01888 HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
01889 uint16_t          HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
01890 HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
01891 HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter);
01892 HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
01893 HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
01894 /**
01895   * @}
01896   */
01897
01898 /** @addtogroup FDCAN_Exported_Functions_Group3
01899   * @{
01900   */
01901 /* Control functions **********************************************************/
01902 HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
01903 HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
01904 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData);
01905 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
01906 HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
01907 HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
01908 HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
01909 HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
01910 HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
01911 HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
01912 HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);
01913 uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex);
01914 uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
01915 uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
01916 uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan);
01917 uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
01918 HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
01919 /**
01920   * @}
01921   */
01922
01923 /** @addtogroup FDCAN_Exported_Functions_Group4
01924   * @{
01925   */
01926 /* TT Configuration and control functions**************************************/
01927 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams);
01928 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload);
01929 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef* hfdcan, FDCAN_TriggerTypeDef* sTriggerConfig);
01930 HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef* hfdcan, uint32_t TimePreset);
01931 HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef* hfdcan, uint32_t NewTURNumerator);
01932 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef* hfdcan, uint32_t Source, uint32_t Polarity);
01933 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef* hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle);
01934 HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
01935 HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
01936 HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
01937 HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
01938 HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
01939 HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
01940 HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
01941 HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
01942 HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan);
01943 HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan);
01944 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase);
01945 HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
01946 HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
01947 HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus);
01948 /**
01949   * @}
01950   */
01951
01952 /** @addtogroup FDCAN_Exported_Functions_Group5
01953   * @{
01954   */
01955 /* Interrupts management ******************************************************/
01956 HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
01957 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
01958 HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes);
01959 HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
01960 HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs);
01961 HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs);
01962 void              HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef* hfdcan);
01963 /**
01964   * @}
01965   */
01966
01967 /** @addtogroup FDCAN_Exported_Functions_Group6
01968   * @{
01969   */
01970 /* Callback functions *********************************************************/
01971 void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);
01972 void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);
01973 void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);
01974 void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);
01975 void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan);
01976 void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
01977 void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
01978 void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan);
01979 void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan);
01980 void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan);
01981 void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan);
01982 void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan);
01983 void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);
01984 void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);
01985 void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount);
01986 void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);
01987 /**
01988   * @}
01989   */
01990
01991 /** @addtogroup FDCAN_Exported_Functions_Group7
01992   * @{
01993   */
01994 /* Peripheral State functions *************************************************/
01995 uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan);
01996 HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef* hfdcan);
01997 /**
01998   * @}
01999   */
02000
02001 /**
02002   * @}
02003   */
02004
02005 /* Private types -------------------------------------------------------------*/
02006 /** @defgroup FDCAN_Private_Types FDCAN Private Types
02007   * @{
02008   */
02009
02010 /**
02011   * @}
02012   */
02013
02014 /* Private variables ---------------------------------------------------------*/
02015 /** @defgroup FDCAN_Private_Variables FDCAN Private Variables
02016   * @{
02017   */
02018
02019 /**
02020   * @}
02021   */
02022
02023 /* Private constants ---------------------------------------------------------*/
02024 /** @defgroup FDCAN_Private_Constants FDCAN Private Constants
02025   * @{
02026   */
02027
02028 /**
02029   * @}
02030   */
02031
02032 /* Private macros ------------------------------------------------------------*/
02033 /** @defgroup FDCAN_Private_Macros FDCAN Private Macros
02034   * @{
02035   */
02036 #define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC  ) || \
02037                                        ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
02038                                        ((FORMAT) == FDCAN_FRAME_FD_BRS   ))
02039 #define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL              ) || \
02040                              ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
02041                              ((MODE) == FDCAN_MODE_BUS_MONITORING      ) || \
02042                              ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK   ) || \
02043                              ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK   ))
02044 #define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \
02045                                ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \
02046                                ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \
02047                                ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \
02048                                ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \
02049                                ((CKDIV) == FDCAN_CLOCK_DIV10) || \
02050                                ((CKDIV) == FDCAN_CLOCK_DIV12) || \
02051                                ((CKDIV) == FDCAN_CLOCK_DIV14) || \
02052                                ((CKDIV) == FDCAN_CLOCK_DIV16) || \
02053                                ((CKDIV) == FDCAN_CLOCK_DIV18) || \
02054                                ((CKDIV) == FDCAN_CLOCK_DIV20) || \
02055                                ((CKDIV) == FDCAN_CLOCK_DIV22) || \
02056                                ((CKDIV) == FDCAN_CLOCK_DIV24) || \
02057                                ((CKDIV) == FDCAN_CLOCK_DIV26) || \
02058                                ((CKDIV) == FDCAN_CLOCK_DIV28) || \
02059                                ((CKDIV) == FDCAN_CLOCK_DIV30))
02060 #define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 512))
02061 #define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1) && ((SJW) <= 128))
02062 #define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 2) && ((TSEG1) <= 256))
02063 #define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 2) && ((TSEG2) <= 128))
02064 #define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 32))
02065 #define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1) && ((SJW) <= 16))
02066 #define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1) && ((TSEG1) <= 32))
02067 #define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1) && ((TSEG2) <= 16))
02068 #define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX))
02069 #define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN))
02070 #define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \
02071                                   ((SIZE) == FDCAN_DATA_BYTES_12) || \
02072                                   ((SIZE) == FDCAN_DATA_BYTES_16) || \
02073                                   ((SIZE) == FDCAN_DATA_BYTES_20) || \
02074                                   ((SIZE) == FDCAN_DATA_BYTES_24) || \
02075                                   ((SIZE) == FDCAN_DATA_BYTES_32) || \
02076                                   ((SIZE) == FDCAN_DATA_BYTES_48) || \
02077                                   ((SIZE) == FDCAN_DATA_BYTES_64))
02078 #define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
02079                                            ((MODE) == FDCAN_TX_QUEUE_OPERATION))
02080 #define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \
02081                                    ((ID_TYPE) == FDCAN_EXTENDED_ID))
02082 #define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE      ) || \
02083                                      ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0   ) || \
02084                                      ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1   ) || \
02085                                      ((CONFIG) == FDCAN_FILTER_REJECT       ) || \
02086                                      ((CONFIG) == FDCAN_FILTER_HP           ) || \
02087                                      ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
02088                                      ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP) || \
02089                                      ((CONFIG) == FDCAN_FILTER_TO_RXBUFFER  ))
02090 #define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \
02091                                         ((LOCATION) == FDCAN_TX_BUFFER2 ) || ((LOCATION) == FDCAN_TX_BUFFER3 ) || \
02092                                         ((LOCATION) == FDCAN_TX_BUFFER4 ) || ((LOCATION) == FDCAN_TX_BUFFER5 ) || \
02093                                         ((LOCATION) == FDCAN_TX_BUFFER6 ) || ((LOCATION) == FDCAN_TX_BUFFER7 ) || \
02094                                         ((LOCATION) == FDCAN_TX_BUFFER8 ) || ((LOCATION) == FDCAN_TX_BUFFER9 ) || \
02095                                         ((LOCATION) == FDCAN_TX_BUFFER10) || ((LOCATION) == FDCAN_TX_BUFFER11) || \
02096                                         ((LOCATION) == FDCAN_TX_BUFFER12) || ((LOCATION) == FDCAN_TX_BUFFER13) || \
02097                                         ((LOCATION) == FDCAN_TX_BUFFER14) || ((LOCATION) == FDCAN_TX_BUFFER15) || \
02098                                         ((LOCATION) == FDCAN_TX_BUFFER16) || ((LOCATION) == FDCAN_TX_BUFFER17) || \
02099                                         ((LOCATION) == FDCAN_TX_BUFFER18) || ((LOCATION) == FDCAN_TX_BUFFER19) || \
02100                                         ((LOCATION) == FDCAN_TX_BUFFER20) || ((LOCATION) == FDCAN_TX_BUFFER21) || \
02101                                         ((LOCATION) == FDCAN_TX_BUFFER22) || ((LOCATION) == FDCAN_TX_BUFFER23) || \
02102                                         ((LOCATION) == FDCAN_TX_BUFFER24) || ((LOCATION) == FDCAN_TX_BUFFER25) || \
02103                                         ((LOCATION) == FDCAN_TX_BUFFER26) || ((LOCATION) == FDCAN_TX_BUFFER27) || \
02104                                         ((LOCATION) == FDCAN_TX_BUFFER28) || ((LOCATION) == FDCAN_TX_BUFFER29) || \
02105                                         ((LOCATION) == FDCAN_TX_BUFFER30) || ((LOCATION) == FDCAN_TX_BUFFER31))
02106 #define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \
02107                                 ((FIFO) == FDCAN_RX_FIFO1))
02108 #define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \
02109                                      ((MODE) == FDCAN_RX_FIFO_OVERWRITE))
02110 #define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \
02111                                         ((TYPE) == FDCAN_FILTER_DUAL ) || \
02112                                         ((TYPE) == FDCAN_FILTER_MASK ))
02113 #define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE        ) || \
02114                                         ((TYPE) == FDCAN_FILTER_DUAL         ) || \
02115                                         ((TYPE) == FDCAN_FILTER_MASK         ) || \
02116                                         ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))
02117 #define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME  ) || \
02118                                    ((TYPE) == FDCAN_REMOTE_FRAME))
02119 #define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \
02120                            ((DLC) == FDCAN_DLC_BYTES_1 ) || \
02121                            ((DLC) == FDCAN_DLC_BYTES_2 ) || \
02122                            ((DLC) == FDCAN_DLC_BYTES_3 ) || \
02123                            ((DLC) == FDCAN_DLC_BYTES_4 ) || \
02124                            ((DLC) == FDCAN_DLC_BYTES_5 ) || \
02125                            ((DLC) == FDCAN_DLC_BYTES_6 ) || \
02126                            ((DLC) == FDCAN_DLC_BYTES_7 ) || \
02127                            ((DLC) == FDCAN_DLC_BYTES_8 ) || \
02128                            ((DLC) == FDCAN_DLC_BYTES_12) || \
02129                            ((DLC) == FDCAN_DLC_BYTES_16) || \
02130                            ((DLC) == FDCAN_DLC_BYTES_20) || \
02131                            ((DLC) == FDCAN_DLC_BYTES_24) || \
02132                            ((DLC) == FDCAN_DLC_BYTES_32) || \
02133                            ((DLC) == FDCAN_DLC_BYTES_48) || \
02134                            ((DLC) == FDCAN_DLC_BYTES_64))
02135 #define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \
02136                            ((ESI) == FDCAN_ESI_PASSIVE))
02137 #define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \
02138                            ((BRS) == FDCAN_BRS_ON ))
02139 #define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \
02140                            ((FDF) == FDCAN_FD_CAN     ))
02141 #define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS   ) || \
02142                            ((EFC) == FDCAN_STORE_TX_EVENTS))
02143 #define IS_FDCAN_IT(IT) (((IT) & 0xC0300000U) == RESET)
02144 #define IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == RESET)
02145 #define IS_FDCAN_FIFO_WATERMARK(FIFO) (((FIFO) == FDCAN_CFG_TX_EVENT_FIFO) || \
02146                                        ((FIFO) == FDCAN_CFG_RX_FIFO0     ) || \
02147                                        ((FIFO) == FDCAN_CFG_RX_FIFO1     ))
02148 #define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
02149                                             ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
02150                                             ((DESTINATION) == FDCAN_REJECT            ))
02151 #define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \
02152                                    ((IT_LINE) == FDCAN_INTERRUPT_LINE1))
02153 #define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
02154                                        ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))
02155 #define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \
02156                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \
02157                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \
02158                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \
02159                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \
02160                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \
02161                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \
02162                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \
02163                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \
02164                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
02165                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
02166                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
02167                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
02168                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
02169                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
02170                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))
02171 #define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS   ) || \
02172                                      ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
02173                                      ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0     ) || \
02174                                      ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1     ))
02175 #define IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH) (((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_32) || \
02176                                                    ((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_64))
02177 #define IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD) (((PAYLOAD) == FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ) || \
02178                                                         ((PAYLOAD) == FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD))
02179 #define IS_FDCAN_TT_REPEAT_FACTOR(FACTOR) (((FACTOR) == FDCAN_TT_REPEAT_EVERY_CYCLE     ) || \
02180                                            ((FACTOR) == FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ) || \
02181                                            ((FACTOR) == FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ) || \
02182                                            ((FACTOR) == FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ) || \
02183                                            ((FACTOR) == FDCAN_TT_REPEAT_EVERY_16TH_CYCLE) || \
02184                                            ((FACTOR) == FDCAN_TT_REPEAT_EVERY_32ND_CYCLE) || \
02185                                            ((FACTOR) == FDCAN_TT_REPEAT_EVERY_64TH_CYCLE))
02186 #define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_REF_TRIGGER        ) || \
02187                                         ((TYPE) == FDCAN_TT_TX_REF_TRIGGER_GAP    ) || \
02188                                         ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE     ) || \
02189                                         ((TYPE) == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) || \
02190                                         ((TYPE) == FDCAN_TT_TX_TRIGGER_ARBITRATION) || \
02191                                         ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED     ) || \
02192                                         ((TYPE) == FDCAN_TT_WATCH_TRIGGER         ) || \
02193                                         ((TYPE) == FDCAN_TT_WATCH_TRIGGER_GAP     ) || \
02194                                         ((TYPE) == FDCAN_TT_RX_TRIGGER            ) || \
02195                                         ((TYPE) == FDCAN_TT_TIME_BASE_TRIGGER     ) || \
02196                                         ((TYPE) == FDCAN_TT_END_OF_LIST           ))
02197 #define IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_INTERNAL_EVENT ) || \
02198                                               ((EVENT) == FDCAN_TT_TM_GEN_INTERNAL_EVENT))
02199 #define IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_EXTERNAL_EVENT ) || \
02200                                               ((EVENT) == FDCAN_TT_TM_GEN_EXTERNAL_EVENT))
02201 #define IS_FDCAN_OPERATION_MODE(MODE) (((MODE) == FDCAN_TT_COMMUNICATION_LEVEL1 ) || \
02202                                        ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL2 ) || \
02203                                        ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL0 ))
02204 #define IS_FDCAN_TT_OPERATION(OPERATION) (((OPERATION) == FDCAN_STRICTLY_TT_OPERATION      ) || \
02205                                           ((OPERATION) == FDCAN_EXT_EVT_SYNC_TT_OPERATION))
02206 #define IS_FDCAN_TT_TIME_MASTER(FUNCTION) (((FUNCTION) == FDCAN_TT_SLAVE           ) || \
02207                                            ((FUNCTION) == FDCAN_TT_POTENTIAL_MASTER))
02208 #define IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC) (((SYNC) == FDCAN_TT_EXT_CLK_SYNC_DISABLE) || \
02209                                              ((SYNC) == FDCAN_TT_EXT_CLK_SYNC_ENABLE ))
02210 #define IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING) (((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_DISABLE) || \
02211                                                       ((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_ENABLE ))
02212 #define IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_DISABLE) || \
02213                                                        ((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_ENABLE ))
02214 #define IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_EVT_TRIG_POL_RISING ) || \
02215                                                       ((POLARITY) == FDCAN_TT_EVT_TRIG_POL_FALLING))
02216 #define IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER) (((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_1 ) || \
02217                                                  ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_2 ) || \
02218                                                  ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_4 ) || \
02219                                                  ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_8 ) || \
02220                                                  ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_16) || \
02221                                                  ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_32) || \
02222                                                  ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_64))
02223 #define IS_FDCAN_TT_CYCLE_START_SYNC(SYNC) (((SYNC) == FDCAN_TT_NO_SYNC_PULSE         ) || \
02224                                             ((SYNC) == FDCAN_TT_SYNC_BASIC_CYCLE_START) || \
02225                                             ((SYNC) == FDCAN_TT_SYNC_MATRIX_START     ))
02226 #define IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1) && ((NTU) <= 16))
02227 #define IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000) && ((NUMERATOR) <= 0x1FFFF))
02228 #define IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001) && ((DENOMINATOR) <= 0x3FFF))
02229 #define IS_FDCAN_TT_TUR_LEVEL_1(NC,DC) ((NC) >= (4 * (DC)))
02230 #define IS_FDCAN_TT_TUR_LEVEL_0_2(NC,DC) ((NC) >= (8 * (DC)))
02231 #define IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_0) || \
02232                                                  ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_1) || \
02233                                                  ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_2) || \
02234                                                  ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_3))
02235 #define IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_0) || \
02236                                             ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_1) || \
02237                                             ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_2) || \
02238                                             ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_3))
02239 #define IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFF) && ((TIME) != 0x8000))
02240 #define IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_STOP_WATCH_DISABLED   ) || \
02241                                                ((SOURCE) == FDCAN_TT_STOP_WATCH_CYCLE_TIME ) || \
02242                                                ((SOURCE) == FDCAN_TT_STOP_WATCH_LOCAL_TIME ) || \
02243                                                ((SOURCE) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME))
02244 #define IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_STOP_WATCH_DISABLED   ) || \
02245                                                    ((POLARITY) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME))
02246 #define IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_REG_TIMEMARK_DIABLED ) || \
02247                                                        ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \
02248                                                        ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \
02249                                                        ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME))
02250 /**
02251   * @}
02252   */
02253
02254 /* Private functions prototypes ----------------------------------------------*/
02255 /** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes
02256   * @{
02257   */
02258
02259 /**
02260   * @}
02261   */
02262
02263 /* Private functions ---------------------------------------------------------*/
02264 /** @defgroup FDCAN_Private_Functions FDCAN Private Functions
02265   * @{
02266   */
02267
02268 /**
02269   * @}
02270   */
02271 /**
02272   * @}
02273   */
02274
02275 /**
02276   * @}
02277   */
02278
02279 #ifdef __cplusplus
02280 }
02281 #endif
02282
02283 #endif /* __STM32H7xx_HAL_FDCAN_H */
02284
02285
02286 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_flash.c Source File

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stm32h7xx_hal_flash.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_flash.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   FLASH HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the internal FLASH memory:
00010   *           + Program operations functions
00011   *           + Memory Control functions
00012   *           + Peripheral Errors functions
00013   *
00014  @verbatim
00015   ==============================================================================
00016                         ##### FLASH peripheral features #####
00017   ==============================================================================
00018
00019   [..] The Flash memory interface manages CPU AXI I-Code and D-Code accesses
00020        to the Flash memory. It implements the erase and program Flash memory operations
00021        and the read and write protection mechanisms.
00022
00023
00024
00025   [..] The FLASH main features are:
00026       (+) Flash memory read operations
00027       (+) Flash memory program/erase operations
00028       (+) Read / write protections
00029       (+) Option bytes programming
00030       (+) Error code correction (ECC) : Data in flash are 266-bits word
00031           (10 bits added per double word)
00032
00033
00034                         ##### How to use this driver #####
00035  ==============================================================================
00036     [..]
00037       This driver provides functions and macros to configure and program the FLASH
00038       memory of all STM32H7xx devices.
00039
00040       (#) FLASH Memory IO Programming functions:
00041            (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
00042                 HAL_FLASH_Lock() functions
00043            (++) Program functions: double word only
00044            (++) There Two modes of programming :
00045             (+++) Polling mode using HAL_FLASH_Program() function
00046             (+++) Interrupt mode using HAL_FLASH_Program_IT() function
00047
00048       (#) Interrupts and flags management functions :
00049            (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
00050            (++) Callback functions are called when the flash operations are finished :
00051                 HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
00052                 HAL_FLASH_OperationErrorCallback()
00053            (++) Get error flag status by calling HAL_FLASH_GetError()
00054
00055       (#) Option bytes management functions :
00056            (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
00057                 HAL_FLASH_OB_Lock() functions
00058            (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function.
00059                 In this case, a reset is generated
00060     [..]
00061       In addition to these functions, this driver includes a set of macros allowing
00062       to handle the following operations:
00063        (+) Set the latency
00064        (+) Enable/Disable the FLASH interrupts
00065        (+) Monitor the FLASH flags status
00066      [..]
00067     (@) For any Flash memory program operation (erase or program), the CPU clock frequency
00068         (HCLK) must be at least 1MHz.
00069     (@) The contents of the Flash memory are not guaranteed if a device reset occurs during
00070         a Flash memory operation.
00071     (@) Any attempt to read the Flash memory while it is being written or erased, causes the
00072         bus to stall. Read operations are processed correctly once the program operation has
00073         completed. This means that code or data fetches cannot be performed while a write/erase
00074         operation is ongoing
00075
00076  @endverbatim
00077   ******************************************************************************
00078   * @attention
00079   *
00080   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00081   *
00082   * Redistribution and use in source and binary forms, with or without modification,
00083   * are permitted provided that the following conditions are met:
00084   *   1. Redistributions of source code must retain the above copyright notice,
00085   *      this list of conditions and the following disclaimer.
00086   *   2. Redistributions in binary form must reproduce the above copyright notice,
00087   *      this list of conditions and the following disclaimer in the documentation
00088   *      and/or other materials provided with the distribution.
00089   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00090   *      may be used to endorse or promote products derived from this software
00091   *      without specific prior written permission.
00092   *
00093   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00094   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00095   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00096   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00097   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00098   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00099   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00100   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00101   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00102   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00103   *
00104   ******************************************************************************
00105   */
00106
00107 /* Includes ------------------------------------------------------------------*/
00108 #include "stm32h7xx_hal.h"
00109
00110 /** @addtogroup STM32H7xx_HAL_Driver
00111   * @{
00112   */
00113
00114 /** @defgroup FLASH FLASH
00115   * @brief FLASH HAL module driver
00116   * @{
00117   */
00118
00119 #ifdef HAL_FLASH_MODULE_ENABLED
00120
00121 /* Private typedef -----------------------------------------------------------*/
00122 /* Private define ------------------------------------------------------------*/
00123 /** @addtogroup FLASH_Private_Constants
00124   * @{
00125   */
00126 #define FLASH_TIMEOUT_VALUE       ((uint32_t)50000U)/* 50 s */
00127 /**
00128   * @}
00129   */
00130 /* Private macro -------------------------------------------------------------*/
00131 /* Private variables ---------------------------------------------------------*/
00132 FLASH_ProcessTypeDef pFlash;
00133 /* Private function prototypes -----------------------------------------------*/
00134 static void FLASH_SetErrorCode(uint32_t Bank);
00135 /* Private functions ---------------------------------------------------------*/
00136
00137 /** @defgroup FLASH_Private_Functions FLASH Private functions
00138   * @{
00139   */
00140
00141 /** @defgroup FLASH_Group1 Programming operation functions
00142  *  @brief   Programming operation functions
00143  *
00144 @verbatim
00145  ===============================================================================
00146                   ##### Programming operation functions #####
00147  ===============================================================================
00148     [..]
00149     This subsection provides a set of functions allowing to manage the FLASH
00150     program operations.
00151
00152 @endverbatim
00153   * @{
00154   */
00155
00156 /**
00157   * @brief  Program flash word of 256 bits at a specified address
00158   * @param  TypeProgram Indicate the way to program at a specified address.
00159   *                      This parameter can be a value of @ref FLASH_Type_Program
00160   * @param  FlashAddress specifies the address to be programmed.
00161   * @param  DataAddress specifies the address of data (256 bits) to be programmed
00162   *
00163   * @retval HAL_StatusTypeDef HAL Status
00164   */
00165 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint64_t DataAddress)
00166 {
00167   HAL_StatusTypeDef status = HAL_ERROR;
00168   __IO uint64_t *dest_addr = (__IO uint64_t *)FlashAddress;
00169   __IO uint64_t *src_addr = (__IO uint64_t*)((uint32_t)DataAddress);
00170   uint32_t bank;
00171   uint8_t row_index = 4;
00172
00173   /* Process Locked */
00174   __HAL_LOCK(&pFlash);
00175
00176   /* Check the parameters */
00177   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
00178   assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress));
00179
00180   if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress))
00181   {
00182     bank = FLASH_BANK_1;
00183   }
00184   else
00185   {
00186     bank = FLASH_BANK_2;
00187   }
00188
00189   /* Wait for last operation to be completed */
00190   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
00191
00192   if(status == HAL_OK)
00193   {
00194     if(bank == FLASH_BANK_1)
00195     {
00196       /* Clear bank 1 pending flags (if any) */
00197       __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1 | FLASH_FLAG_QW_BANK1 | FLASH_FLAG_WBNE_BANK1 | FLASH_FLAG_ALL_ERRORS_BANK1);
00198
00199       /* Set PG bit */
00200       SET_BIT(FLASH->CR1, FLASH_CR_PG);
00201     }
00202     else
00203     {
00204       /* Clear bank 2 pending flags (if any) */
00205       __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2 | FLASH_FLAG_QW_BANK2 | FLASH_FLAG_WBNE_BANK2 | FLASH_FLAG_ALL_ERRORS_BANK2);
00206
00207       /* Set PG bit */
00208       SET_BIT(FLASH->CR2, FLASH_CR_PG);
00209     }
00210
00211     /* Program the 256 bits flash word */
00212     do
00213     {
00214       *dest_addr++ = *src_addr++;
00215     } while (--row_index != 0);
00216
00217     __DSB();
00218
00219     /* Wait for last operation to be completed */
00220     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
00221
00222     if(bank == FLASH_BANK_1)
00223     {
00224       /* Check FLASH End of Operation flag  */
00225       if (__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_EOP_BANK1))
00226       {
00227         /* Clear FLASH End of Operation pending bit */
00228         __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
00229       }
00230
00231       /* If the program operation is completed, disable the PG*/
00232       CLEAR_BIT(FLASH->CR1, FLASH_CR_PG);
00233     }
00234     else
00235     {
00236       /* Check FLASH End of Operation flag  */
00237       if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_EOP_BANK2))
00238       {
00239         /* Clear FLASH End of Operation pending bit */
00240         __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
00241       }
00242
00243       /* If the program operation is completed, disable the PG */
00244       CLEAR_BIT(FLASH->CR2, FLASH_CR_PG);
00245     }
00246   }
00247
00248   /* Process Unlocked */
00249   __HAL_UNLOCK(&pFlash);
00250
00251   return status;
00252 }
00253
00254 /**
00255   * @brief  Program flash words of 256 bits at a specified address with interrupt enabled.
00256   * @param  TypeProgram Indicate the way to program at a specified address.
00257   *                      This parameter can be a value of @ref FLASH_Type_Program
00258   * @param  FlashAddress specifies the address to be programmed.
00259   * @param  DataAddress specifies the address of data (256 bits) to be programmed
00260   *
00261   * @retval HAL Status
00262   */
00263 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint64_t DataAddress)
00264 {
00265   HAL_StatusTypeDef status = HAL_OK;
00266   __IO uint64_t *dest_addr = (__IO uint64_t*)FlashAddress;
00267   __IO uint64_t *src_addr = (__IO uint64_t*)((uint32_t)DataAddress);
00268   uint32_t bank;
00269   uint8_t row_index = 4;
00270
00271   /* Process Locked */
00272   __HAL_LOCK(&pFlash);
00273
00274   /* Check the parameters */
00275   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
00276   assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress));
00277
00278   if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress))
00279   {
00280     bank = FLASH_BANK_1;
00281     pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1;
00282   }
00283   else
00284   {
00285     bank = FLASH_BANK_2;
00286     pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK2;
00287   }
00288
00289   /* Set internal variables used by the IRQ handler */
00290   pFlash.Address = FlashAddress;
00291
00292   if(bank == FLASH_BANK_1)
00293   {
00294     /* Clear bank 1 pending flags (if any) */
00295     __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1 | FLASH_FLAG_ALL_ERRORS_BANK1);
00296
00297     /* Set PG bit */
00298     SET_BIT(FLASH->CR1, FLASH_CR_PG);
00299
00300     /* Enable End of Operation and Error interrupts for Bank 1 */
00301     __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1    | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
00302                                 FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
00303   }
00304   else
00305   {
00306     /* Clear bank 2 pending flags (if any) */
00307     __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2 | FLASH_FLAG_ALL_ERRORS_BANK2);
00308
00309     /* Set PG bit */
00310     SET_BIT(FLASH->CR2, FLASH_CR_PG);
00311
00312     /* Enable End of Operation and Error interrupts for Bank2*/
00313     __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2    | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
00314                                 FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
00315   }
00316
00317   /* Program the 256 bits flash word */
00318   do
00319   {
00320     *dest_addr++ = *src_addr++;
00321   } while (--row_index != 0);
00322
00323   return status;
00324 }
00325
00326 /**
00327   * @brief This function handles FLASH interrupt request.
00328   * @retval None
00329   */
00330 void HAL_FLASH_IRQHandler(void)
00331 {
00332   uint32_t temp;
00333
00334   /* Check FLASH Bank1 End of Operation flag  */
00335   if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_SR_EOP) != RESET)
00336   {
00337     if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK1)
00338     {
00339       /*Nb of sector to erased can be decreased*/
00340       pFlash.NbSectorsToErase--;
00341
00342       /* Check if there are still sectors to erase*/
00343       if(pFlash.NbSectorsToErase != 0)
00344       {
00345         temp = pFlash.Sector;
00346         /*Indicate user which sector has been erased*/
00347         HAL_FLASH_EndOfOperationCallback(temp);
00348
00349         /* Clear pending flags (if any) */
00350         /* Clear bank 1 pending flags (if any) */
00351         __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1 | FLASH_FLAG_ALL_ERRORS_BANK1);
00352
00353         /*Increment sector number*/
00354         temp = ++pFlash.Sector;
00355         FLASH_Erase_Sector(temp, FLASH_BANK_1/*pFlash.Bank*/, pFlash.VoltageForErase);
00356       }
00357       else
00358       {
00359         /*No more sectors to Erase, user callback can be called.*/
00360         /*Reset Sector and stop Erase sectors procedure*/
00361         pFlash.Sector = temp = 0xFFFFFFFF;
00362         pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00363         /* FLASH EOP interrupt user callback */
00364         HAL_FLASH_EndOfOperationCallback(temp);
00365         /* Clear FLASH End of Operation pending bit */
00366         __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
00367       }
00368     }
00369     else
00370     {
00371       if((pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE_BANK1) || (pFlash.ProcedureOnGoing == FLASH_PROC_ALLBANK_MASSERASE))
00372       {
00373         /*MassErase ended. Return the selected bank*/
00374         /* FLASH EOP interrupt user callback */
00375         HAL_FLASH_EndOfOperationCallback(FLASH_BANK_1);
00376       }
00377       else if(pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_BANK1)
00378       {
00379         /*Program ended. Return the selected address*/
00380         /* FLASH EOP interrupt user callback */
00381         HAL_FLASH_EndOfOperationCallback(pFlash.Address);
00382       }
00383
00384       if((pFlash.ProcedureOnGoing != FLASH_PROC_SECTERASE_BANK2) && \
00385          (pFlash.ProcedureOnGoing != FLASH_PROC_MASSERASE_BANK2)&& \
00386          (pFlash.ProcedureOnGoing != FLASH_PROC_PROGRAM_BANK2))
00387       {
00388         pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00389         /* Clear FLASH End of Operation pending bit */
00390         __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
00391       }
00392     }
00393   }
00394
00395  /* Check FLASH Bank2 End of Operation flag  */
00396   if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_SR_EOP) != RESET)
00397   {
00398     if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK2)
00399     {
00400       /*Nb of sector to erased can be decreased*/
00401       pFlash.NbSectorsToErase--;
00402
00403       /* Check if there are still sectors to erase*/
00404       if(pFlash.NbSectorsToErase != 0)
00405       {
00406         temp = pFlash.Sector;
00407         /*Indicate user which sector has been erased*/
00408         HAL_FLASH_EndOfOperationCallback(temp);
00409
00410         /* Clear pending flags (if any) */
00411         /* Clear bank 2 pending flags (if any) */
00412         __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2 | FLASH_FLAG_ALL_ERRORS_BANK2);
00413
00414         /*Increment sector number*/
00415         temp = ++pFlash.Sector;
00416         FLASH_Erase_Sector(temp, FLASH_BANK_2 /*pFlash.Bank*/, pFlash.VoltageForErase);
00417       }
00418       else
00419       {
00420         /*No more sectors to Erase, user callback can be called.*/
00421         /*Reset Sector and stop Erase sectors procedure*/
00422         pFlash.Sector = temp = 0xFFFFFFFF;
00423         pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00424         /* FLASH EOP interrupt user callback */
00425         HAL_FLASH_EndOfOperationCallback(temp);
00426         /* Clear FLASH End of Operation pending bit */
00427         __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
00428       }
00429     }
00430     else
00431     {
00432       if((pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE_BANK2) || (pFlash.ProcedureOnGoing == FLASH_PROC_ALLBANK_MASSERASE))
00433       {
00434         /*MassErase ended. Return the selected bank*/
00435         /* FLASH EOP interrupt user callback */
00436         HAL_FLASH_EndOfOperationCallback(FLASH_BANK_2);
00437       }
00438       else
00439       {
00440         /*Program ended. Return the selected address*/
00441         /* FLASH EOP interrupt user callback */
00442         HAL_FLASH_EndOfOperationCallback(pFlash.Address);
00443       }
00444
00445       if((pFlash.ProcedureOnGoing != FLASH_PROC_SECTERASE_BANK1) && \
00446           (pFlash.ProcedureOnGoing != FLASH_PROC_MASSERASE_BANK1)&& \
00447           (pFlash.ProcedureOnGoing != FLASH_PROC_PROGRAM_BANK1))
00448       {
00449         pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00450         /* Clear FLASH End of Operation pending bit */
00451         __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
00452       }
00453     }
00454   }
00455
00456   /* Check FLASH Bank1 operation error flags */
00457   if(__HAL_FLASH_GET_FLAG_BANK1((FLASH_FLAG_EOP_BANK1    | FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | \
00458                                  FLASH_FLAG_STRBER_BANK1R | FLASH_FLAG_INCERR_BANK1 | FLASH_FLAG_OPERR_BANK1)) != RESET)
00459   {
00460     if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK1)
00461     {
00462       /*return the faulty sector*/
00463       temp = pFlash.Sector;
00464       pFlash.Sector = 0xFFFFFFFF;
00465     }
00466     else if((pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE_BANK1) || (pFlash.ProcedureOnGoing == FLASH_PROC_ALLBANK_MASSERASE))
00467     {
00468       /*return the faulty bank*/
00469       temp = FLASH_BANK_1;
00470     }
00471     else
00472     {
00473       /*return the faulty address*/
00474       temp = pFlash.Address;
00475     }
00476
00477     /*Save the Error code*/
00478     FLASH_SetErrorCode(FLASH_BANK_1);
00479
00480     /* FLASH error interrupt user callback */
00481     HAL_FLASH_OperationErrorCallback(temp);
00482     /* Clear FLASH error pending bits */
00483     __HAL_FLASH_CLEAR_FLAG_BANK1((FLASH_FLAG_EOP_BANK1    | FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | \
00484                                   FLASH_FLAG_STRBER_BANK1R | FLASH_FLAG_INCERR_BANK1 | FLASH_FLAG_OPERR_BANK1));
00485
00486     /*Stop the procedure ongoing*/
00487     pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00488   }
00489
00490  /* Check FLASH Bank2 operation error flags */
00491   if(__HAL_FLASH_GET_FLAG_BANK2((FLASH_FLAG_EOP_BANK2    | FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | \
00492                                  FLASH_FLAG_STRBER_BANK2R | FLASH_FLAG_INCERR_BANK2 | FLASH_FLAG_OPERR_BANK2)) != RESET)
00493
00494   {
00495     if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK2)
00496     {
00497       /*return the faulty sector*/
00498       temp = pFlash.Sector;
00499       pFlash.Sector = 0xFFFFFFFF;
00500     }
00501     else if((pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE_BANK2) || (pFlash.ProcedureOnGoing == FLASH_PROC_ALLBANK_MASSERASE))
00502     {
00503       /*return the faulty bank*/
00504       temp = FLASH_BANK_2;
00505     }
00506     else
00507     {
00508       /*return the faulty address*/
00509       temp = pFlash.Address;
00510     }
00511
00512     /*Save the Error code*/
00513     FLASH_SetErrorCode(FLASH_BANK_2);
00514
00515     /* FLASH error interrupt user callback */
00516     HAL_FLASH_OperationErrorCallback(temp);
00517     /* Clear FLASH error pending bits */
00518     __HAL_FLASH_CLEAR_FLAG_BANK2((FLASH_FLAG_EOP_BANK2    | FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | \
00519                                   FLASH_FLAG_STRBER_BANK2R | FLASH_FLAG_INCERR_BANK2 |   FLASH_FLAG_OPERR_BANK2));
00520
00521     /*Stop the procedure ongoing*/
00522     pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00523   }
00524
00525   if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
00526   {
00527     /* Disable Bank1 Operation and Error source interrupt */
00528     __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1    | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
00529                                  FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
00530
00531     /* Disable Bank2 Operation and Error source interrupt */
00532     __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2    | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
00533                                  FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
00534
00535     /* Process Unlocked */
00536     __HAL_UNLOCK(&pFlash);
00537   }
00538
00539 }
00540
00541 /**
00542   * @brief  FLASH end of operation interrupt callback
00543   * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
00544   *                  Mass Erase Bank number which has been requested to erase
00545   *                  Sectors Erase: Sector which has been erased
00546   *                    (if 0xFFFFFFFF, it means that all the selected sectors have been erased)
00547   *                  Program Address which was selected for data program
00548   * @retval None
00549   */
00550 __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
00551 {
00552   /* NOTE : This function Should not be modified, when the callback is needed,
00553             the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
00554    */
00555 }
00556
00557 /**
00558   * @brief  FLASH operation error interrupt callback
00559   * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
00560   *                 Mass Erase: Bank number which has been requested to erase
00561   *                 Sectors Erase: Sector number which returned an error
00562   *                 Program: Address which was selected for data program
00563   * @retval None
00564   */
00565 __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
00566 {
00567   /* NOTE : This function Should not be modified, when the callback is needed,
00568             the HAL_FLASH_OperationErrorCallback could be implemented in the user file
00569    */
00570 }
00571
00572 /**
00573   * @}
00574   */
00575
00576 /** @defgroup FLASH_Group2 Peripheral Control functions
00577  *  @brief   management functions
00578  *
00579 @verbatim
00580  ===============================================================================
00581                       ##### Peripheral Control functions #####
00582  ===============================================================================
00583     [..]
00584     This subsection provides a set of functions allowing to control the FLASH
00585     memory operations.
00586
00587 @endverbatim
00588   * @{
00589   */
00590
00591 /**
00592   * @brief  Unlock the FLASH control registers access
00593   * @retval HAL Status
00594   */
00595 HAL_StatusTypeDef HAL_FLASH_Unlock(void)
00596 {
00597   if((READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != RESET) && (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != RESET))
00598   {
00599     /* Authorize the FLASH A Registers access */
00600     WRITE_REG(FLASH->KEYR1, FLASH_KEY1);
00601     WRITE_REG(FLASH->KEYR1, FLASH_KEY2);
00602
00603     /* Authorize the FLASH B Registers access */
00604     WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
00605     WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
00606   }
00607   else
00608   {
00609     return HAL_ERROR;
00610   }
00611
00612   return HAL_OK;
00613 }
00614
00615 /**
00616   * @brief  Locks the FLASH control registers access
00617   * @retval HAL Status
00618   */
00619 HAL_StatusTypeDef HAL_FLASH_Lock(void)
00620 {
00621   /* Set the LOCK Bit to lock the FLASH A Registers access */
00622   SET_BIT(FLASH->CR1, FLASH_CR_LOCK);
00623
00624   /* Set the LOCK Bit to lock the FLASH B Registers access */
00625   SET_BIT(FLASH->CR2, FLASH_CR_LOCK);
00626
00627   return HAL_OK;
00628 }
00629
00630 /**
00631   * @brief  Unlock the FLASH Option Control Registers access.
00632   * @retval HAL Status
00633   */
00634 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
00635 {
00636   if(READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != RESET)
00637   {
00638     /* Authorizes the Option Byte register programming */
00639     WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY1);
00640     WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY2);
00641   }
00642   else
00643   {
00644     return HAL_ERROR;
00645   }
00646
00647   return HAL_OK;
00648 }
00649
00650 /**
00651   * @brief  Lock the FLASH Option Control Registers access.
00652   * @retval HAL Status
00653   */
00654 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
00655 {
00656   /* Set the OPTLOCK Bit to lock the FLASH A and B Option Byte Registers access */
00657   SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK);
00658
00659   return HAL_OK;
00660 }
00661
00662 /**
00663   * @brief  Launch the option byte loading.
00664   * @retval HAL Status
00665   */
00666 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
00667 {
00668   HAL_StatusTypeDef status = HAL_ERROR;
00669
00670   /* Set OPTSTRT Bit */
00671   SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTSTART);
00672
00673   /* Wait for OB change operation to be completed */
00674   status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00675
00676   return status;
00677 }
00678
00679 /**
00680   * @}
00681   */
00682
00683 /** @defgroup FLASH_Group3 Peripheral State and Errors functions
00684  *  @brief   Peripheral Errors functions
00685  *
00686 @verbatim
00687  ===============================================================================
00688                 ##### Peripheral Errors functions #####
00689  ===============================================================================
00690     [..]
00691     This subsection permits to get in run-time Errors of the FLASH peripheral.
00692
00693 @endverbatim
00694   * @{
00695   */
00696
00697 /**
00698   * @brief  Get the specific FLASH error flag.
00699   * @retval HAL_FLASH_ERRORCode The returned value can be:
00700   *            @arg HAL_FLASH_ERROR_NONE: No error set
00701   *
00702   *            @arg HAL_FLASH_ERROR_WRP_BANK1: Write Protection Error on Bank 1
00703   *            @arg HAL_FLASH_ERROR_PGS_BANK1  : Program Sequence Error on Bank 1
00704   *            @arg HAL_FLASH_ERROR_STRB_BANK1 : Strobe Error on Bank 1
00705   *            @arg HAL_FLASH_ERROR_INC_BANK1  : Inconsistency Error on Bank 1
00706   *            @arg HAL_FLASH_ERROR_OPE_BANK1  : Operation Error on Bank 1
00707   *            @arg HAL_FLASH_ERROR_RDP_BANK1  : Read Protection Error on Bank 1
00708   *            @arg HAL_FLASH_ERROR_RDS_BANK1  : Read Secured Error on Bank 1
00709   *            @arg HAL_FLASH_ERROR_SNECC_BANK1: SNECC Error on Bank 1
00710   *            @arg HAL_FLASH_ERROR_DBECC_BANK1: Double Detection ECC on Bank 1
00711   *
00712   *            @arg HAL_FLASH_ERROR_WRP_BANK2  : Write Protection Error on Bank 2
00713   *            @arg HAL_FLASH_ERROR_PGS_BANK2  : Program Sequence Error on Bank 2
00714   *            @arg HAL_FLASH_ERROR_STRB_BANK2 : Strobe Error on Bank 2
00715   *            @arg HAL_FLASH_ERROR_INC_BANK2  : Inconsistency Error on Bank 2
00716   *            @arg HAL_FLASH_ERROR_OPE_BANK2  : Operation Error on Bank 2
00717   *            @arg HAL_FLASH_ERROR_RDP_BANK2  : Read Protection Error on Bank 2
00718   *            @arg HAL_FLASH_ERROR_RDS_BANK2  : Read Secured Error on Bank 2
00719   *            @arg HAL_FLASH_ERROR_SNECC_BANK2: SNECC Error on Bank 2
00720   *            @arg HAL_FLASH_ERROR_DBECC_BANK2: Double Detection ECC on Bank 2
00721 */
00722
00723 uint32_t HAL_FLASH_GetError(void)
00724 {
00725    return pFlash.ErrorCode;
00726 }
00727
00728 /**
00729   * @}
00730   */
00731
00732 /**
00733   * @}
00734   */
00735
00736 /**
00737   * @brief  Wait for a FLASH operation to complete.
00738   * @param  Timeout maximum flash operation timeout
00739   * @param  Bank flash FLASH_BANK_1 or FLASH_BANK_2
00740   * @retval HAL_StatusTypeDef HAL Status
00741   */
00742 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
00743 {
00744   /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
00745      Even if the FLASH operation fails, the BUSY flag will be reset and an error
00746      flag will be set */
00747
00748   uint32_t bsyflag, errorflag = 0;
00749   uint32_t timeout = HAL_GetTick() + Timeout;
00750
00751   assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
00752
00753   if(Bank == FLASH_BANK_1)
00754   {
00755     bsyflag = FLASH_FLAG_BSY_BANK1 | FLASH_FLAG_QW_BANK1;
00756
00757     if((FLASH->OPTCR & FLASH_OPTCR_SWAP_BANK) == 0)
00758     {
00759       bsyflag |= FLASH_FLAG_WBNE_BANK1;
00760     }
00761     else
00762     {
00763       bsyflag |= FLASH_FLAG_WBNE_BANK2;
00764     }
00765   }
00766   else
00767   {
00768     bsyflag = FLASH_FLAG_BSY_BANK2 | FLASH_FLAG_QW_BANK2;
00769
00770     if((FLASH->OPTCR & FLASH_OPTCR_SWAP_BANK) == 0)
00771     {
00772       bsyflag |= FLASH_FLAG_WBNE_BANK2;
00773     }
00774     else
00775     {
00776       bsyflag |= FLASH_FLAG_WBNE_BANK1;
00777     }
00778   }
00779
00780   while(__HAL_FLASH_GET_FLAG(bsyflag))
00781   {
00782     if(Timeout != HAL_MAX_DELAY)
00783     {
00784       if(HAL_GetTick() >= timeout)
00785       {
00786         return HAL_TIMEOUT;
00787       }
00788     }
00789   }
00790
00791   if((Bank == FLASH_BANK_1) && ((FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1) != RESET))
00792   {
00793     errorflag = FLASH_FLAG_ALL_ERRORS_BANK1;
00794   }
00795   else if((Bank == FLASH_BANK_2) && ((FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2 & 0x7FFFFFFF) != RESET))
00796   {
00797     errorflag = FLASH_FLAG_ALL_ERRORS_BANK2;
00798   }
00799
00800   if(errorflag != 0)
00801   {
00802     /*Save the error code*/
00803     FLASH_SetErrorCode(Bank);
00804
00805     /* Clear error programming flags */
00806     __HAL_FLASH_CLEAR_FLAG(errorflag);
00807
00808     return HAL_ERROR;
00809   }
00810
00811   /* If there is an error flag set */
00812   return HAL_OK;
00813 }
00814
00815 /**
00816   * @brief  Wait for a FLASH Option Bytes change operation to complete.
00817   * @param  Timeout maximum flash operation timeout
00818   * @retval HAL_StatusTypeDef HAL Status
00819   */
00820 HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout)
00821 {
00822   uint32_t timeout = HAL_GetTick() + Timeout;
00823
00824   /* Wait for the FLASH Option Bytes change operation to complete by polling on OPT_BUSY flag to be reset.*/
00825   while(FLASH->OPTSR_CUR & FLASH_OPTSR_OPT_BUSY)
00826   {
00827     if(Timeout != HAL_MAX_DELAY)
00828     {
00829       if(HAL_GetTick() >= timeout)
00830       {
00831         return HAL_TIMEOUT;
00832       }
00833     }
00834   }
00835   if(FLASH->OPTSR_CUR & FLASH_OPTSR_OPTCHANGEERR)
00836   {
00837     /*Save the error code*/
00838     pFlash.ErrorCode |= HAL_FLASH_ERROR_OB_CHANGE;
00839
00840     /*Clear the OB error flag*/
00841     FLASH->OPTCCR |= FLASH_OPTCCR_CLR_OPTCHANGEERR;
00842
00843     return HAL_ERROR;
00844   }
00845
00846   /* If there is an error flag set */
00847   return HAL_OK;
00848 }
00849
00850 /**
00851   * @brief  Set the specific FLASH error flag.
00852   * @retval None
00853   */
00854 static void FLASH_SetErrorCode(uint32_t Bank)
00855 {
00856   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00857
00858   if(Bank == FLASH_BANK_1)
00859   {
00860     if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_WRPERR_BANK1))
00861     {
00862       pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP_BANK1;
00863     }
00864     if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_PGSERR_BANK1))
00865     {
00866       pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS_BANK1;
00867     }
00868     if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_STRBER_BANK1R))
00869     {
00870       pFlash.ErrorCode |= HAL_FLASH_ERROR_STRB_BANK1;
00871     }
00872     if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_INCERR_BANK1))
00873     {
00874       pFlash.ErrorCode |= HAL_FLASH_ERROR_INC_BANK1;
00875     }
00876     if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_OPERR_BANK1))
00877     {
00878       pFlash.ErrorCode |= HAL_FLASH_ERROR_OPE_BANK1;
00879     }
00880     if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_RDPERR_BANK1))
00881     {
00882       pFlash.ErrorCode |= HAL_FLASH_ERROR_RDP_BANK1;
00883     }
00884     if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_RDSERR_BANK1))
00885     {
00886       pFlash.ErrorCode |= HAL_FLASH_ERROR_RDS_BANK1;
00887     }
00888     if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_SNECCE_BANK1RR))
00889     {
00890       pFlash.ErrorCode |= HAL_FLASH_ERROR_SNECC_BANK1;
00891     }
00892     if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_DBECCE_BANK1RR))
00893     {
00894       pFlash.ErrorCode |= HAL_FLASH_ERROR_DBECC_BANK1;
00895     }
00896   }
00897   else if(Bank == FLASH_BANK_2)
00898   {
00899     if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_WRPERR_BANK2))
00900     {
00901       pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP_BANK2;
00902     }
00903     if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_PGSERR_BANK2))
00904     {
00905       pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS_BANK2;
00906     }
00907     if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_STRBER_BANK2R))
00908     {
00909       pFlash.ErrorCode |= HAL_FLASH_ERROR_STRB_BANK2;
00910     }
00911     if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_INCERR_BANK2))
00912     {
00913       pFlash.ErrorCode |= HAL_FLASH_ERROR_INC_BANK2;
00914     }
00915     if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_OPERR_BANK2))
00916     {
00917       pFlash.ErrorCode |= HAL_FLASH_ERROR_OPE_BANK2;
00918     }
00919     if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_RDPERR_BANK2))
00920     {
00921       pFlash.ErrorCode |= HAL_FLASH_ERROR_RDP_BANK2;
00922     }
00923     if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_RDSERR_BANK2))
00924     {
00925       pFlash.ErrorCode |= HAL_FLASH_ERROR_RDS_BANK2;
00926     }
00927     if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_SNECCE_BANK2RR))
00928     {
00929       pFlash.ErrorCode |= HAL_FLASH_ERROR_SNECC_BANK2;
00930     }
00931     if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_DBECCE_BANK2RR))
00932     {
00933       pFlash.ErrorCode |= HAL_FLASH_ERROR_DBECC_BANK2;
00934     }
00935   }
00936 }
00937
00938 #endif /* HAL_FLASH_MODULE_ENABLED */
00939
00940 /**
00941   * @}
00942   */
00943
00944 /**
00945   * @}
00946   */
00947
00948 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_flash.h Source File

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stm32h7xx_hal_flash.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_flash.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of FLASH HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_FLASH_H
00040 #define __STM32H7xx_HAL_FLASH_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup FLASH
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup FLASH_Exported_Types FLASH Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  FLASH Procedure structure definition
00064   */
00065 typedef enum
00066 {
00067   FLASH_PROC_NONE = 0U,
00068   FLASH_PROC_SECTERASE_BANK1,
00069   FLASH_PROC_MASSERASE_BANK1,
00070   FLASH_PROC_PROGRAM_BANK1,
00071   FLASH_PROC_SECTERASE_BANK2,
00072   FLASH_PROC_MASSERASE_BANK2,
00073   FLASH_PROC_PROGRAM_BANK2,
00074   FLASH_PROC_ALLBANK_MASSERASE
00075 } FLASH_ProcedureTypeDef;
00076
00077
00078 /**
00079   * @brief  FLASH handle Structure definition
00080   */
00081 typedef struct
00082 {
00083   __IO FLASH_ProcedureTypeDef ProcedureOnGoing;   /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
00084
00085   __IO uint32_t               NbSectorsToErase;   /*!< Internal variable to save the remaining sectors to erase in IT context        */
00086
00087   __IO uint8_t                VoltageForErase;    /*!< Internal variable to provide voltage range selected by user in IT context     */
00088
00089   __IO uint32_t               Sector;             /*!< Internal variable to define the current sector which is erasing               */
00090
00091   __IO uint32_t               Address;            /*!< Internal variable to save address selected for program                        */
00092
00093   HAL_LockTypeDef             Lock;               /*!< FLASH locking object                                                          */
00094
00095   __IO uint32_t               ErrorCode;          /*!< FLASH error code                                                              */
00096
00097 }FLASH_ProcessTypeDef;
00098
00099 /**
00100   * @}
00101   */
00102
00103 /* Exported constants --------------------------------------------------------*/
00104 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants
00105   * @{
00106   */
00107
00108 /** @defgroup FLASH_Error_Code FLASH Error Code
00109   * @brief    FLASH Error Code
00110   * @{
00111   */
00112
00113 #define HAL_FLASH_ERROR_NONE         ((uint32_t)0x00000000U)  /*!< No error                         */
00114
00115 #define HAL_FLASH_ERROR_WRP    ((uint32_t)0x00000001U)  /*!< Write Protection Error */
00116 #define HAL_FLASH_ERROR_PGS    ((uint32_t)0x00000002U)  /*!< Program Sequence Error */
00117 #define HAL_FLASH_ERROR_STRB   ((uint32_t)0x00000004U)  /*!< Strobe Error           */
00118 #define HAL_FLASH_ERROR_INC    ((uint32_t)0x00000008U)  /*!< Inconsistency Error    */
00119 #define HAL_FLASH_ERROR_OPE    ((uint32_t)0x00000010U)  /*!< Operation Error        */
00120 #define HAL_FLASH_ERROR_RDP    ((uint32_t)0x00000020U)  /*!< Read Protection Error  */
00121 #define HAL_FLASH_ERROR_RDS    ((uint32_t)0x00000040U)  /*!< Read Secured Error     */
00122 #define HAL_FLASH_ERROR_SNECC  ((uint32_t)0x00000080U)  /*!< Single Detection ECC   */
00123 #define HAL_FLASH_ERROR_DBECC  ((uint32_t)0x00000100U)  /*!< Double Detection ECC   */
00124
00125 #define HAL_FLASH_ERROR_WRP_BANK1    ((uint32_t)0x00000001U)  /*!< Write Protection Error on Bank 1 */
00126 #define HAL_FLASH_ERROR_PGS_BANK1    ((uint32_t)0x00000002U)  /*!< Program Sequence Error on Bank 1 */
00127 #define HAL_FLASH_ERROR_STRB_BANK1   ((uint32_t)0x00000004U)  /*!< Strobe Error on Bank 1           */
00128 #define HAL_FLASH_ERROR_INC_BANK1    ((uint32_t)0x00000008U)  /*!< Inconsistency Error on Bank 1    */
00129 #define HAL_FLASH_ERROR_OPE_BANK1    ((uint32_t)0x00000010U)  /*!< Operation Error on Bank 1        */
00130 #define HAL_FLASH_ERROR_RDP_BANK1    ((uint32_t)0x00000020U)  /*!< Read Protection Error on Bank 1  */
00131 #define HAL_FLASH_ERROR_RDS_BANK1    ((uint32_t)0x00000040U)  /*!< Read Secured Error on Bank 1     */
00132 #define HAL_FLASH_ERROR_SNECC_BANK1  ((uint32_t)0x00000080U)  /*!< Single Detection ECC on Bank 1   */
00133 #define HAL_FLASH_ERROR_DBECC_BANK1  ((uint32_t)0x00000100U)  /*!< Double Detection ECC on Bank 1   */
00134
00135 #define HAL_FLASH_ERROR_WRP_BANK2    ((uint32_t)0x00001000U)  /*!< Write Protection Error on Bank 2 */
00136 #define HAL_FLASH_ERROR_PGS_BANK2    ((uint32_t)0x00002000U)  /*!< Program Sequence Error on Bank 2 */
00137 #define HAL_FLASH_ERROR_STRB_BANK2   ((uint32_t)0x00004000U)  /*!< Strobe Error on Bank 2           */
00138 #define HAL_FLASH_ERROR_INC_BANK2    ((uint32_t)0x00008000U)  /*!< Inconsistency Error on Bank 2    */
00139 #define HAL_FLASH_ERROR_OPE_BANK2    ((uint32_t)0x00010000U)  /*!< Operation Error on Bank 2        */
00140 #define HAL_FLASH_ERROR_RDP_BANK2    ((uint32_t)0x00020000U)  /*!< Read Protection Error on Bank 2  */
00141 #define HAL_FLASH_ERROR_RDS_BANK2    ((uint32_t)0x00040000U)  /*!< Read Secured Error on Bank 2     */
00142 #define HAL_FLASH_ERROR_SNECC_BANK2  ((uint32_t)0x00080000U)  /*!< Single Detection ECC on Bank 2   */
00143 #define HAL_FLASH_ERROR_DBECC_BANK2  ((uint32_t)0x00100000U)  /*!< Double Detection ECC on Bank 2   */
00144
00145 #define HAL_FLASH_ERROR_OB_CHANGE    ((uint32_t)0x01000000U)  /*!< Option Byte Change Error         */
00146
00147 /**
00148   * @}
00149   */
00150
00151 /** @defgroup FLASH_Type_Program FLASH Type Program
00152   * @{
00153   */
00154 #define FLASH_TYPEPROGRAM_FLASHWORD  ((uint32_t)0x03U)  /*!< Program a flash word (256-bit) at a specified address */
00155 /**
00156   * @}
00157   */
00158
00159 /** @defgroup FLASH_Flag_definition FLASH Flag definition
00160   * @brief Flag definition
00161   * @{
00162   */
00163
00164
00165 #define FLASH_FLAG_BSY               FLASH_SR_BSY             /*!< FLASH Busy flag */
00166 #define FLASH_FLAG_WDW               FLASH_SR_WDW             /*!< Waiting for Data to Write on flag */
00167 #define FLASH_FLAG_QW                FLASH_SR_QW              /*!< Write Waiting in Operation Queue on flag */
00168 #define FLASH_FLAG_CRC_BUSY          FLASH_SR_CRC_BUSY        /*!< CRC module is working on flag */
00169 #define FLASH_FLAG_EOP               FLASH_SR_EOP             /*!< End Of Program on flag */
00170 #define FLASH_FLAG_WRPERR            FLASH_SR_WRPERR          /*!< Write Protection Error on flag */
00171 #define FLASH_FLAG_PGSERR            FLASH_SR_PGSERR          /*!< Program Sequence Error on flag */
00172 #define FLASH_FLAG_STRBERR           FLASH_SR_STRBERR         /*!< strobe Error on flag */
00173 #define FLASH_FLAG_INCERR            FLASH_SR_INCERR          /*!< Inconsistency Error on flag */
00174 #define FLASH_FLAG_OPERR             FLASH_SR_OPERR           /*!< Operation Error on flag */
00175 #define FLASH_FLAG_RDPERR            FLASH_SR_RDPERR          /*!< Read Protection Error on flag */
00176 #define FLASH_FLAG_RDSERR            FLASH_SR_RDSERR          /*!< Read Secured Error on flag */
00177 #define FLASH_FLAG_SNECCERR          FLASH_SR_SNECCERR        /*!< Single ECC Error Correction on flag */
00178 #define FLASH_FLAG_DBECCERR          FLASH_SR_DBECCERR        /*!< Double Detection ECC Error on flag */
00179 #define FLASH_FLAG_CRCEND            FLASH_SR_CRCEND          /*!< CRC module completes on bank flag */
00180
00181
00182 #define FLASH_FLAG_BSY_BANK1               FLASH_SR_BSY             /*!< FLASH Bank 1 Busy flag */
00183 #define FLASH_FLAG_WBNE_BANK1              FLASH_SR_WBNE            /*!< Waiting for Data to Write on Bank 1 flag */
00184 #define FLASH_FLAG_QW_BANK1                FLASH_SR_QW              /*!< Write Waiting in Operation Queue on Bank 1 flag */
00185 #define FLASH_FLAG_CRC_BUSY_BANK1          FLASH_SR_CRC_BUSY        /*!< CRC module is working on Bank 1 flag */
00186 #define FLASH_FLAG_EOP_BANK1               FLASH_SR_EOP             /*!< End Of Program on Bank 1 flag */
00187 #define FLASH_FLAG_WRPERR_BANK1            FLASH_SR_WRPERR          /*!< Write Protection Error on Bank 1 flag */
00188 #define FLASH_FLAG_PGSERR_BANK1            FLASH_SR_PGSERR          /*!< Program Sequence Error on Bank 1 flag */
00189 #define FLASH_FLAG_STRBER_BANK1R           FLASH_SR_STRBERR         /*!< strobe Error on Bank 1 flag */
00190 #define FLASH_FLAG_INCERR_BANK1            FLASH_SR_INCERR          /*!< Inconsistency Error on Bank 1 flag */
00191 #define FLASH_FLAG_OPERR_BANK1             FLASH_SR_OPERR           /*!< Operation Error on Bank 1 flag */
00192 #define FLASH_FLAG_RDPERR_BANK1            FLASH_SR_RDPERR          /*!< Read Protection Error on Bank 1 flag */
00193 #define FLASH_FLAG_RDSERR_BANK1            FLASH_SR_RDSERR          /*!< Read Secured Error on Bank 1 flag */
00194 #define FLASH_FLAG_SNECCE_BANK1RR          FLASH_SR_SNECCERR        /*!< Single ECC Error Correction on Bank 1 flag */
00195 #define FLASH_FLAG_DBECCE_BANK1RR          FLASH_SR_DBECCERR        /*!< Double Detection ECC Error on Bank 1 flag */
00196 #define FLASH_FLAG_CRCEND_BANK1            FLASH_SR_CRCEND          /*!< CRC module completes on bank Bank 1 flag */
00197
00198
00199 #define FLASH_FLAG_ALL_ERRORS_BANK1       (FLASH_FLAG_WRPERR_BANK1  | FLASH_FLAG_PGSERR_BANK1   | \
00200                                            FLASH_FLAG_STRBER_BANK1R | FLASH_FLAG_INCERR_BANK1   | \
00201                                            FLASH_FLAG_OPERR_BANK1   | FLASH_FLAG_RDPERR_BANK1   | \
00202                                            FLASH_FLAG_RDSERR_BANK1  | FLASH_FLAG_SNECCE_BANK1RR | \
00203                                            FLASH_FLAG_DBECCE_BANK1RR)
00204
00205 #define FLASH_FLAG_ALL_BANK1              (FLASH_FLAG_BSY_BANK1      | FLASH_FLAG_WBNE_BANK1      | \
00206                                            FLASH_FLAG_QW_BANK1       | FLASH_FLAG_CRC_BUSY_BANK1 | \
00207                                            FLASH_FLAG_EOP_BANK1      | FLASH_FLAG_CRCEND_BANK1   | \
00208                                            FLASH_FLAG_ALL_ERRORS_BANK1)
00209
00210 #define FLASH_FLAG_BSY_BANK2               (FLASH_SR_BSY      | 0x80000000U)        /*!< FLASH Bank 2 Busy flag */
00211 #define FLASH_FLAG_WBNE_BANK2              (FLASH_SR_WBNE     | 0x80000000U)        /*!< Waiting for Data to Write on Bank 2 flag */
00212 #define FLASH_FLAG_QW_BANK2                (FLASH_SR_QW       | 0x80000000U)        /*!< Write Waiting in Operation Queue on Bank 2 flag */
00213 #define FLASH_FLAG_CRC_BUSY_BANK2          (FLASH_SR_CRC_BUSY | 0x80000000U)        /*!< CRC module is working on Bank 2 flag */
00214 #define FLASH_FLAG_EOP_BANK2               (FLASH_SR_EOP      | 0x80000000U)        /*!< End Of Program on Bank 2 flag */
00215 #define FLASH_FLAG_WRPERR_BANK2            (FLASH_SR_WRPERR   | 0x80000000U)        /*!< Write Protection Error on Bank 2 flag */
00216 #define FLASH_FLAG_PGSERR_BANK2            (FLASH_SR_PGSERR   | 0x80000000U)        /*!< Program Sequence Error on Bank 2 flag */
00217 #define FLASH_FLAG_STRBER_BANK2R           (FLASH_SR_STRBERR  | 0x80000000U)        /*!< Strobe Error on Bank 2 flag */
00218 #define FLASH_FLAG_INCERR_BANK2            (FLASH_SR_INCERR   | 0x80000000U)        /*!< Inconsistency Error on Bank 2 flag */
00219 #define FLASH_FLAG_OPERR_BANK2             (FLASH_SR_OPERR    | 0x80000000U)        /*!< Operation Error on Bank 2 flag */
00220 #define FLASH_FLAG_RDPERR_BANK2            (FLASH_SR_RDPERR   | 0x80000000U)        /*!< Read Protection Error on Bank 2 flag */
00221 #define FLASH_FLAG_RDSERR_BANK2            (FLASH_SR_RDSERR   | 0x80000000U)        /*!< Read Secured Error on Bank 2 flag */
00222 #define FLASH_FLAG_SNECCE_BANK2RR          (FLASH_SR_SNECCERR | 0x80000000U)        /*!< Single ECC Error Correction on Bank 2 flag */
00223 #define FLASH_FLAG_DBECCE_BANK2RR          (FLASH_SR_DBECCERR | 0x80000000U)        /*!< Double Detection ECC Error on Bank 2 flag */
00224 #define FLASH_FLAG_CRCEND_BANK2            (FLASH_SR_CRCEND   | 0x80000000U)        /*!< CRC module completes on bank Bank 2 flag */
00225
00226
00227 #define FLASH_FLAG_ALL_ERRORS_BANK2       (FLASH_FLAG_WRPERR_BANK2  | FLASH_FLAG_PGSERR_BANK2   | \
00228                                            FLASH_FLAG_STRBER_BANK2R | FLASH_FLAG_INCERR_BANK2   | \
00229                                            FLASH_FLAG_OPERR_BANK2   | FLASH_FLAG_RDPERR_BANK2   | \
00230                                            FLASH_FLAG_RDSERR_BANK2  | FLASH_FLAG_SNECCE_BANK2RR | \
00231                                            FLASH_FLAG_DBECCE_BANK2RR)
00232
00233 #define FLASH_FLAG_ALL_BANK2              (FLASH_FLAG_BSY_BANK2      | FLASH_FLAG_WBNE_BANK2      | \
00234                                            FLASH_FLAG_QW_BANK2       | FLASH_FLAG_CRC_BUSY_BANK2 | \
00235                                            FLASH_FLAG_EOP_BANK2      | FLASH_FLAG_CRCEND_BANK2   | \
00236                                            FLASH_FLAG_ALL_ERRORS_BANK2)
00237
00238
00239
00240 /**
00241   * @}
00242   */
00243
00244 /** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
00245   * @brief FLASH Interrupt definition
00246   * @{
00247   */
00248
00249 #define FLASH_IT_EOP_BANK1                  FLASH_CR_EOPIE       /*!< End of FLASH Bank 1 Operation Interrupt source */
00250 #define FLASH_IT_WRPERR_BANK1               FLASH_CR_WRPERRIE    /*!< Write Protection Error on Bank 1 Interrupt source */
00251 #define FLASH_IT_PGSERR_BANK1               FLASH_CR_PGSERRIE    /*!< Program Sequence Error on Bank 1 Interrupt source */
00252 #define FLASH_IT_STRBERR_BANK1              FLASH_CR_STRBERRIE   /*!< Strobe Error on Bank 1 Interrupt source */
00253 #define FLASH_IT_INCERR_BANK1               FLASH_CR_INCERRIE    /*!< Inconsistency Error on Bank 1 Interrupt source */
00254 #define FLASH_IT_OPERR_BANK1                FLASH_CR_OPERRIE     /*!< Operation Error on Bank 1 Interrupt source */
00255 #define FLASH_IT_RDPERR_BANK1               FLASH_CR_RDPERRIE    /*!< Read protection Error on Bank 1 Interrupt source */
00256 #define FLASH_IT_RDSERR_BANK1               FLASH_CR_RDSERRIE    /*!< Read Secured Error on Bank 1 Interrupt source */
00257 #define FLASH_IT_SNECCERR_BANK1             FLASH_CR_SNECCERRIE  /*!< Single ECC Error Correction on Bank 1 Interrupt source */
00258 #define FLASH_IT_DBECCERR_BANK1             FLASH_CR_DBECCERRIE  /*!< Double Detection ECC Error on Bank 1 Interrupt source */
00259 #define FLASH_IT_CRCEND_BANK1               FLASH_CR_CRCENDIE    /*!< CRC End on Bank 1 Interrupt source */
00260
00261 #define FLASH_IT_ALL_BANK1                 (FLASH_IT_EOP_BANK1       | FLASH_IT_WRPERR_BANK1    | \
00262                                             FLASH_IT_PGSERR_BANK1    | FLASH_IT_STRBERR_BANK1   | \
00263                                             FLASH_IT_INCERR_BANK1    | FLASH_IT_OPERR_BANK1     | \
00264                                             FLASH_IT_RDPERR_BANK1    | FLASH_IT_RDSERR_BANK1    | \
00265                                             FLASH_CR_SNECCERRIE | FLASH_CR_DBECCERRIE | \
00266                                             FLASH_CR_CRCENDIE )
00267
00268 #define FLASH_IT_EOP_BANK2                 (FLASH_CR_EOPIE      | 0x80000000U)  /*!< End of FLASH Bank 2 Operation Interrupt source */
00269 #define FLASH_IT_WRPERR_BANK2              (FLASH_CR_WRPERRIE   | 0x80000000U)  /*!< Write Protection Error on Bank 2 Interrupt source */
00270 #define FLASH_IT_PGSERR_BANK2              (FLASH_CR_PGSERRIE   | 0x80000000U)  /*!< Program Sequence Error on Bank 2 Interrupt source */
00271 #define FLASH_IT_STRBERR_BANK2             (FLASH_CR_STRBERRIE  | 0x80000000U)  /*!< Strobe Error on Bank 2 Interrupt source */
00272 #define FLASH_IT_INCERR_BANK2              (FLASH_CR_INCERRIE   | 0x80000000U)  /*!< Inconsistency Error on Bank 2 Interrupt source */
00273 #define FLASH_IT_OPERR_BANK2               (FLASH_CR_OPERRIE    | 0x80000000U)  /*!< Operation Error on Bank 2 Interrupt source */
00274 #define FLASH_IT_RDPERR_BANK2              (FLASH_CR_RDPERRIE   | 0x80000000U)  /*!< Read protection Error on Bank 2 Interrupt source */
00275 #define FLASH_IT_RDSERR_BANK2              (FLASH_CR_RDSERRIE   | 0x80000000U)  /*!< Read Secured Error on Bank 2 Interrupt source */
00276 #define FLASH_IT_SNECCERR_BANK2            (FLASH_CR_SNECCERRIE | 0x80000000U)  /*!< Single ECC Error Correction on Bank 2 Interrupt source */
00277 #define FLASH_IT_DBECCERR_BANK2            (FLASH_CR_DBECCERRIE | 0x80000000U)  /*!< Double Detection ECC Error on Bank 2 Interrupt source */
00278 #define FLASH_IT_CRCEND_BANK2              (FLASH_CR_CRCENDIE   | 0x80000000U)  /*!< CRC End on Bank 2 Interrupt source */
00279
00280
00281 #define FLASH_IT_ALL_BANK2                 (FLASH_IT_EOP_BANK2       | FLASH_IT_WRPERR_BANK1    | \
00282                                             FLASH_IT_PGSERR_BANK2    | FLASH_IT_STRBERR_BANK1   | \
00283                                             FLASH_IT_INCERR_BANK2    | FLASH_IT_OPERR_BANK1     | \
00284                                             FLASH_IT_RDPERR_BANK2    | FLASH_IT_RDSERR_BANK1    | \
00285                                             FLASH_CR_SNECCERRIE | FLASH_CR_DBECCERRIE | \
00286                                             FLASH_CR_CRCENDIE )
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
00292   * @{
00293   */
00294 #define FLASH_PSIZE_BYTE           ((uint32_t)0x00000000U)
00295 #define FLASH_PSIZE_HALF_WORD      ((uint32_t)FLASH_CR_PSIZE_0)
00296 #define FLASH_PSIZE_WORD           ((uint32_t)FLASH_CR_PSIZE_1)
00297 #define FLASH_PSIZE_DOUBLE_WORD    ((uint32_t)FLASH_CR_PSIZE)
00298 #define CR_PSIZE_MASK              ((uint32_t)0xFFFFFFCFU)
00299 /**
00300   * @}
00301   */
00302
00303
00304 /** @defgroup FLASH_Keys FLASH Keys
00305   * @{
00306   */
00307 #define FLASH_KEY1               ((uint32_t)0x45670123U)
00308 #define FLASH_KEY2               ((uint32_t)0xCDEF89ABU)
00309 #define FLASH_OPT_KEY1           ((uint32_t)0x08192A3BU)
00310 #define FLASH_OPT_KEY2           ((uint32_t)0x4C5D6E7FU)
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup FLASH_Sectors FLASH Sectors
00316   * @{
00317   */
00318 #define FLASH_SECTOR_0           ((uint32_t)0U) /*!< Sector Number 0   */
00319 #define FLASH_SECTOR_1           ((uint32_t)1U) /*!< Sector Number 1   */
00320 #define FLASH_SECTOR_2           ((uint32_t)2U) /*!< Sector Number 2   */
00321 #define FLASH_SECTOR_3           ((uint32_t)3U) /*!< Sector Number 3   */
00322 #define FLASH_SECTOR_4           ((uint32_t)4U) /*!< Sector Number 4   */
00323 #define FLASH_SECTOR_5           ((uint32_t)5U) /*!< Sector Number 5   */
00324 #define FLASH_SECTOR_6           ((uint32_t)6U) /*!< Sector Number 6   */
00325 #define FLASH_SECTOR_7           ((uint32_t)7U) /*!< Sector Number 7   */
00326 /**
00327   * @}
00328   */
00329
00330 /**
00331   * @}
00332   */
00333
00334 /* Exported macro ------------------------------------------------------------*/
00335 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
00336   * @{
00337   */
00338 /**
00339   * @brief  Set the FLASH Latency.
00340   * @param  __LATENCY__: FLASH Latency
00341   *         The value of this parameter depend on device used within the same series
00342   * @retval none
00343   */
00344 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
00345                   MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
00346
00347 /**
00348   * @brief  Get the FLASH Latency.
00349   * @retval FLASH Latency
00350   *          The value of this parameter depend on device used within the same series
00351   */
00352 #define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
00353
00354 /**
00355   * @brief  Enable the specified FLASH interrupt.
00356   * @param  __INTERRUPT__ : FLASH interrupt
00357   *   In case of Bank 1 This parameter can be any combination of the following values:
00358   *     @arg FLASH_IT_EOP_BANK1       : End of FLASH Bank 1 Operation Interrupt source
00359   *     @arg FLASH_IT_WRPERR_BANK1    : Write Protection Error on Bank 1 Interrupt source
00360   *     @arg FLASH_IT_PGSERR_BANK1    : Program Sequence Error on Bank 1 Interrupt source
00361   *     @arg FLASH_IT_STRBERR_BANK1   : Strobe Error on Bank 1 Interrupt source
00362   *     @arg FLASH_IT_INCERR_BANK1    : Inconsistency Error on Bank 1 Interrupt source
00363   *     @arg FLASH_IT_OPERR_BANK1     : Operation Error on Bank 1 Interrupt source
00364   *     @arg FLASH_IT_RDPERR_BANK1    : Read protection Error on Bank 1 Interrupt source
00365   *     @arg FLASH_IT_RDSERR_BANK1    : Read secure Error on Bank 1 Interrupt source
00366   *     @arg FLASH_IT_SNECCERR_BANK1  : Single ECC Error Correction on Bank 1 Interrupt source
00367   *     @arg FLASH_IT_DBECCERR_BANK1  : Double Detection ECC Error on Bank 1 Interrupt source
00368   *     @arg FLASH_IT_CRCEND_BANK1    : CRC End on Bank 1 Interrupt source
00369
00370   *   In case of Bank 2 This parameter can be any combination of the following values:  *
00371   *     @arg FLASH_IT_EOP_BANK2       : End of FLASH Bank 2 Operation Interrupt source
00372   *     @arg FLASH_IT_WRPERR_BANK2    : Write Protection Error on Bank 2 Interrupt source
00373   *     @arg FLASH_IT_PGSERR_BANK2    : Program Sequence Error on Bank 2 Interrupt source
00374   *     @arg FLASH_IT_STRBERR_BANK2   : Strobe Error on Bank 2 Interrupt source
00375   *     @arg FLASH_IT_INCERR_BANK2    : Inconsistency Error on Bank 2 Interrupt source
00376   *     @arg FLASH_IT_OPERR_BANK2     : Operation Error on Bank 2 Interrupt source
00377   *     @arg FLASH_IT_RDPERR_BANK2    : Read protection Error on Bank 2 Interrupt source
00378   *     @arg FLASH_IT_RDSERR_BANK2    : Read secure Error on Bank 2 Interrupt source
00379   *     @arg FLASH_IT_SNECCERR_BANK2  : Single ECC Error Correction on Bank 2 Interrupt source
00380   *     @arg FLASH_IT_DBECCERR_BANK2  : Double Detection ECC Error on Bank 2 Interrupt source
00381   *     @arg FLASH_IT_CRCEND_BANK2    : CRC End on Bank 2 Interrupt source
00382   * @retval none
00383   */
00384
00385 #define __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__)      (FLASH->CR1 |= (__INTERRUPT__))
00386
00387 #define __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__)      (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFF))
00388
00389 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)    (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
00390                                                  __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) : \
00391                                                  __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__))
00392
00393
00394 /**
00395   * @brief  Disable the specified FLASH interrupt.
00396   * @param  __INTERRUPT__ : FLASH interrupt
00397   *   In case of Bank 1 This parameter can be any combination of the following values:
00398   *     @arg FLASH_IT_EOP_BANK1       : End of FLASH Bank 1 Operation Interrupt source
00399   *     @arg FLASH_IT_WRPERR_BANK1    : Write Protection Error on Bank 1 Interrupt source
00400   *     @arg FLASH_IT_PGSERR_BANK1    : Program Sequence Error on Bank 1 Interrupt source
00401   *     @arg FLASH_IT_STRBERR_BANK1   : Strobe Error on Bank 1 Interrupt source
00402   *     @arg FLASH_IT_INCERR_BANK1    : Inconsistency Error on Bank 1 Interrupt source
00403   *     @arg FLASH_IT_OPERR_BANK1     : Operation Error on Bank 1 Interrupt source
00404   *     @arg FLASH_IT_RDPERR_BANK1    : Read protection Error on Bank 1 Interrupt source
00405   *     @arg FLASH_IT_RDSERR_BANK1    : Read secure Error on Bank 1 Interrupt source
00406   *     @arg FLASH_IT_SNECCERR_BANK1  : Single ECC Error Correction on Bank 1 Interrupt source
00407   *     @arg FLASH_IT_DBECCERR_BANK1  : Double Detection ECC Error on Bank 1 Interrupt source
00408   *     @arg FLASH_IT_CRCEND_BANK1    : CRC End on Bank 1 Interrupt source
00409
00410   *   In case of Bank 2 This parameter can be any combination of the following values:  *
00411   *     @arg FLASH_IT_EOP_BANK2       : End of FLASH Bank 2 Operation Interrupt source
00412   *     @arg FLASH_IT_WRPERR_BANK2    : Write Protection Error on Bank 2 Interrupt source
00413   *     @arg FLASH_IT_PGSERR_BANK2    : Program Sequence Error on Bank 2 Interrupt source
00414   *     @arg FLASH_IT_STRBERR_BANK2   : Strobe Error on Bank 2 Interrupt source
00415   *     @arg FLASH_IT_INCERR_BANK2    : Inconsistency Error on Bank 2 Interrupt source
00416   *     @arg FLASH_IT_OPERR_BANK2     : Operation Error on Bank 2 Interrupt source
00417   *     @arg FLASH_IT_RDPERR_BANK2    : Read protection Error on Bank 2 Interrupt source
00418   *     @arg FLASH_IT_RDSERR_BANK2    : Read secure Error on Bank 2 Interrupt source
00419   *     @arg FLASH_IT_SNECCERR_BANK2  : Single ECC Error Correction on Bank 2 Interrupt source
00420   *     @arg FLASH_IT_DBECCERR_BANK2  : Double Detection ECC Error on Bank 2 Interrupt source
00421   *     @arg FLASH_IT_CRCEND_BANK2    : CRC End on Bank 2 Interrupt source
00422
00423   * @retval none
00424   */
00425
00426 #define __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__)  (FLASH->CR1 &= ~(uint32_t)(__INTERRUPT__))
00427
00428 #define __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__)  (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFF))
00429
00430 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
00431                                                 __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) : \
00432                                                 __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__))
00433
00434
00435 /**
00436   * @brief  Checks whether the specified FLASH flag is set or not.
00437   * @param  __FLAG__: specifies the FLASH flag to check.
00438   *   In case of Bank 1 This parameter can be any combination of the following values :
00439   *     @arg FLASH_FLAG_BSY_BANK1      : FLASH Bank 1 Busy flag
00440   *     @arg FLASH_FLAG_WBNE_BANK1      : Waiting for Data to Write on Bank 1 flag
00441   *     @arg FLASH_FLAG_QW_BANK1       : Write Waiting in Operation Queue on Bank 1 flag
00442   *     @arg FLASH_FLAG_CRC_BUSY_BANK1 : CRC module is working on Bank 1 flag
00443   *     @arg FLASH_FLAG_EOP_BANK1      : End Of Program on Bank 1 flag
00444   *     @arg FLASH_FLAG_WRPERR_BANK1   : Write Protection Error on Bank 1 flag
00445   *     @arg FLASH_FLAG_PGSERR_BANK1   : Program Sequence Error on Bank 1 flag
00446   *     @arg FLASH_FLAG_STRBER_BANK1   : Program Alignment Error on Bank 1 flag
00447   *     @arg FLASH_FLAG_INCERR_BANK1   : Inconsistency Error on Bank 1 flag
00448   *     @arg FLASH_FLAG_OPERR_BANK1    : Operation Error on Bank 1 flag
00449   *     @arg FLASH_FLAG_RDPERR_BANK1   : Read Protection Error on Bank 1 flag
00450   *     @arg FLASH_FLAG_RDSERR_BANK1   : Read secure  Error on Bank 1 flag
00451   *     @arg FLASH_FLAG_SNECCE_BANK1   : Single ECC Error Correction on Bank 1 flag
00452   *     @arg FLASH_FLAG_DBECCE_BANK1   : Double Detection ECC Error on Bank 1 flag
00453   *     @arg FLASH_FLAG_CRCEND_BANK1   : CRC End on Bank 1 flag
00454   *
00455   *   In case of Bank 2 This parameter can be any combination of the following values :
00456   *     @arg FLASH_FLAG_BSY_BANK2      : FLASH Bank 2 Busy flag
00457   *     @arg FLASH_FLAG_WBNE_BANK2      : Waiting for Data to Write on Bank 2 flag
00458   *     @arg FLASH_FLAG_QW_BANK2       : Write Waiting in Operation Queue on Bank 2 flag
00459   *     @arg FLASH_FLAG_CRC_BUSY_BANK2 : CRC module is working on Bank 2 flag
00460   *     @arg FLASH_FLAG_EOP_BANK2      : End Of Program on Bank 2 flag
00461   *     @arg FLASH_FLAG_WRPERR_BANK2   : Write Protection Error on Bank 2 flag
00462   *     @arg FLASH_FLAG_PGSERR_BANK2   : Program Sequence Error on Bank 2 flag
00463   *     @arg FLASH_FLAG_STRBER_BANK2   : Program Alignment Error on Bank 2 flag
00464   *     @arg FLASH_FLAG_INCERR_BANK2   : Inconsistency Error on Bank 2 flag
00465   *     @arg FLASH_FLAG_OPERR_BANK2    : Operation Error on Bank 2 flag
00466   *     @arg FLASH_FLAG_RDPERR_BANK2   : Read Protection Error on Bank 2 flag
00467   *     @arg FLASH_FLAG_RDSERR_BANK2   : Read secure  Error on Bank 2 flag
00468   *     @arg FLASH_FLAG_SNECCE_BANK2   : Single ECC Error Correction on Bank 2 flag
00469   *     @arg FLASH_FLAG_DBECCE_BANK2   : Double Detection ECC Error on Bank 2 flag
00470   *     @arg FLASH_FLAG_CRCEND_BANK2   : CRC End on Bank 2 flag
00471   * @retval The new state of FLASH_FLAG (SET or RESET).
00472   */
00473 #define __HAL_FLASH_GET_FLAG_BANK1(__FLAG__)          (READ_BIT(FLASH->SR1, (__FLAG__)) == (__FLAG__))
00474
00475 #define __HAL_FLASH_GET_FLAG_BANK2(__FLAG__)          (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFF)) == (((__FLAG__) & 0x7FFFFFFF)))
00476
00477 #define __HAL_FLASH_GET_FLAG(__FLAG__)          (IS_FLASH_FLAG_BANK1(__FLAG__) ?  __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) : \
00478                                                  __HAL_FLASH_GET_FLAG_BANK2(__FLAG__))
00479
00480
00481 /**
00482   * @brief  Clear the specified FLASH flag.
00483   * @param  __FLAG__: specifies the FLASH flags to clear.
00484   *          This parameter can be any combination of the following values:
00485   *     @arg FLASH_FLAG_EOP_BANK1      : End Of Program on Bank 1 flag
00486   *     @arg FLASH_FLAG_WRPERR_BANK1   : Write Protection Error on Bank 1 flag
00487   *     @arg FLASH_FLAG_PGSERR_BANK1   : Program Sequence Error on Bank 1 flag
00488   *     @arg FLASH_FLAG_STRBER_BANK1   : Program Alignment Error on Bank 1 flag
00489   *     @arg FLASH_FLAG_INCERR_BANK1   : Inconsistency Error on Bank 1 flag
00490   *     @arg FLASH_FLAG_OPERR_BANK1    : Operation Error on Bank 1 flag
00491   *     @arg FLASH_FLAG_RDPERR_BANK1   : Read Protection Error on Bank 1 flag
00492   *     @arg FLASH_FLAG_RDSERR_BANK1   : Read secure  Error on Bank 1 flag
00493   *     @arg FLASH_FLAG_SNECCE_BANK1   : Single ECC Error Correction on Bank 1 flag
00494   *     @arg FLASH_FLAG_DBECCE_BANK1   : Double Detection ECC Error on Bank 1 flag
00495   *     @arg FLASH_FLAG_CRCEND_BANK1   : CRC End on Bank 1 flag
00496   *
00497   *   In case of Bank 2 This parameter can be any combination of the following values :
00498   *     @arg FLASH_FLAG_EOP_BANK2      : End Of Program on Bank 2 flag
00499   *     @arg FLASH_FLAG_WRPERR_BANK2   : Write Protection Error on Bank 2 flag
00500   *     @arg FLASH_FLAG_PGSERR_BANK2   : Program Sequence Error on Bank 2 flag
00501   *     @arg FLASH_FLAG_STRBER_BANK2   : Program Alignment Error on Bank 2 flag
00502   *     @arg FLASH_FLAG_INCERR_BANK2   : Inconsistency Error on Bank 2 flag
00503   *     @arg FLASH_FLAG_OPERR_BANK2    : Operation Error on Bank 2 flag
00504   *     @arg FLASH_FLAG_RDPERR_BANK2   : Read Protection Error on Bank 2 flag
00505   *     @arg FLASH_FLAG_RDSERR_BANK2   : Read secure  Error on Bank 2 flag
00506   *     @arg FLASH_FLAG_SNECCE_BANK2   : Single ECC Error Correction on Bank 2 flag
00507   *     @arg FLASH_FLAG_DBECCE_BANK2   : Double Detection ECC Error on Bank 2 flag
00508   *     @arg FLASH_FLAG_CRCEND_BANK2   : CRC End on Bank 2 flag
00509   * @retval none
00510   */
00511
00512 #define __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__)    WRITE_REG(FLASH->CCR1, (__FLAG__))
00513
00514 #define __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__)    WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFF))
00515
00516 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__)         (IS_FLASH_FLAG_BANK1(__FLAG__) ?  __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) : \
00517                                                    __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__))
00518
00519 /**
00520   * @}
00521   */
00522
00523 /* Include FLASH HAL Extension module */
00524 #include "stm32h7xx_hal_flash_ex.h"
00525
00526 /* Exported functions --------------------------------------------------------*/
00527 /** @addtogroup FLASH_Exported_Functions
00528   * @{
00529   */
00530 /** @addtogroup FLASH_Exported_Functions_Group1
00531   * @{
00532   */
00533 /* Program operation functions  ***********************************************/
00534 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t DataAddress);
00535 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t DataAddress);
00536 /* FLASH IRQ handler method */
00537 void HAL_FLASH_IRQHandler(void);
00538 /* Callbacks in non blocking modes */
00539 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
00540 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
00541 /**
00542   * @}
00543   */
00544
00545 /** @addtogroup FLASH_Exported_Functions_Group2
00546   * @{
00547   */
00548 /* Peripheral Control functions  **********************************************/
00549 HAL_StatusTypeDef HAL_FLASH_Unlock(void);
00550 HAL_StatusTypeDef HAL_FLASH_Lock(void);
00551 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
00552 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
00553 /* Option bytes control */
00554 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
00555 /**
00556   * @}
00557   */
00558
00559 /** @addtogroup FLASH_Exported_Functions_Group3
00560   * @{
00561   */
00562 /* Peripheral State functions  ************************************************/
00563 uint32_t HAL_FLASH_GetError(void);
00564 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank);
00565 HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout);
00566 /**
00567   * @}
00568   */
00569
00570 /**
00571   * @}
00572   */
00573 /* Private types -------------------------------------------------------------*/
00574 /* Private variables ---------------------------------------------------------*/
00575 /** @defgroup FLASH_Private_Variables FLASH Private Variables
00576   * @{
00577   */
00578
00579 /**
00580   * @}
00581   */
00582 /* Private constants ---------------------------------------------------------*/
00583 /** @defgroup FLASH_Private_Constants FLASH Private Constants
00584   * @{
00585   */
00586
00587
00588 /**
00589   * @}
00590   */
00591
00592 /* Private macros ------------------------------------------------------------*/
00593 /** @defgroup FLASH_Private_Macros FLASH Private Macros
00594   * @{
00595   */
00596
00597 /** @defgroup FLASH_IS_FLASH_Definitions FLASH Definitions
00598   * @{
00599   */
00600 #define IS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD)
00601 /**
00602   * @}
00603   */
00604 /** @defgroup FLASH_IS_BANK_IT_Definitions FLASH BANK IT Definitions
00605   * @{
00606   */
00607
00608 #define IS_FLASH_IT_BANK1(IT)               (((IT) & FLASH_IT_ALL_BANK1) == (IT))
00609
00610 #define IS_FLASH_IT_BANK2(IT)               (((IT) & FLASH_IT_ALL_BANK2) == (IT))
00611
00612 /**
00613   * @}
00614   */
00615
00616 #define IS_FLASH_FLAG_BANK1(FLAG)          (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))
00617
00618 #define IS_FLASH_FLAG_BANK2(FLAG)          (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))
00619
00620 /** @defgroup FLASH_Address FLASH Address
00621   * @{
00622   */
00623
00624 #define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < (FLASH_BANK1_BASE + FLASH_BANK_SIZE) ))
00625 #define IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) < (FLASH_BANK2_BASE + FLASH_BANK_SIZE) ))
00626 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)  (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS))
00627
00628 #define IS_BOOT_ADDRESS(ADDRESS)           ((ADDRESS) <= (0x3FFF0000U))
00629
00630 #define IS_FLASH_BANK(BANK)                (((BANK) == FLASH_BANK_1)  || \
00631                                             ((BANK) == FLASH_BANK_2)  || \
00632                                             ((BANK) == FLASH_BANK_BOTH))
00633
00634 #define IS_FLASH_BANK_EXCLUSIVE(BANK)      (((BANK) == FLASH_BANK_1)  || \
00635                                             ((BANK) == FLASH_BANK_2))
00636
00637 /**
00638   * @}
00639   */
00640
00641 /**
00642   * @}
00643   */
00644 /* Private functions ---------------------------------------------------------*/
00645 /** @defgroup FLASH_Private_Functions FLASH Private functions
00646   * @{
00647   */
00648
00649 /**
00650   * @}
00651   */
00652
00653 /**
00654   * @}
00655   */
00656
00657 /**
00658   * @}
00659   */
00660
00661 #ifdef __cplusplus
00662 }
00663 #endif
00664
00665 #endif /* __STM32H7xx_HAL_FLASH_H */
00666
00667 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_flash_ex.c Source File

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stm32h7xx_hal_flash_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_flash_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Extended FLASH HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the FLASH extension peripheral:
00010   *           + Extended programming operations functions
00011   *
00012  @verbatim
00013  ==============================================================================
00014                    ##### Flash Extension features #####
00015   ==============================================================================
00016
00017   [..] Comparing to other previous devices, the FLASH interface for STM32H7xx
00018        devices contains the following additional features
00019
00020        (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
00021            capability (RWW)
00022        (+) Dual bank memory organization
00023        (+) PCROP protection for all banks
00024
00025                         ##### How to use this driver #####
00026  ==============================================================================
00027   [..] This driver provides functions to configure and program the FLASH memory
00028        of all STM32H7xx devices. It includes
00029       (#) FLASH Memory Erase functions:
00030            (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
00031                 HAL_FLASH_Lock() functions
00032            (++) Erase function: Erase sector, erase all sectors
00033            (++) There are two modes of erase :
00034              (+++) Polling Mode using HAL_FLASHEx_Erase()
00035              (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
00036
00037       (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
00038         (++) Set/Reset the write protection per bank
00039         (++) Set the Read protection Level
00040         (++) Set the BOR level
00041         (++) Program the user Option Bytes
00042         (++) PCROP protection configuration and control per bank
00043     (++) Secure area configuration and control per bank
00044     (++) Core Boot address configuration
00045
00046    (#) FLASH Memory Lock and unlock per Bank: HAL_FLASHEx_Lock_Bank1 and HAL_FLASHEx_Unlock_Bank1 functions
00047
00048
00049  @endverbatim
00050   ******************************************************************************
00051   * @attention
00052   *
00053   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00054   *
00055   * Redistribution and use in source and binary forms, with or without modification,
00056   * are permitted provided that the following conditions are met:
00057   *   1. Redistributions of source code must retain the above copyright notice,
00058   *      this list of conditions and the following disclaimer.
00059   *   2. Redistributions in binary form must reproduce the above copyright notice,
00060   *      this list of conditions and the following disclaimer in the documentation
00061   *      and/or other materials provided with the distribution.
00062   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00063   *      may be used to endorse or promote products derived from this software
00064   *      without specific prior written permission.
00065   *
00066   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00067   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00068   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00069   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00070   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00071   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00072   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00073   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00074   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00075   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00076   *
00077   ******************************************************************************
00078   */
00079
00080 /* Includes ------------------------------------------------------------------*/
00081 #include "stm32h7xx_hal.h"
00082
00083 /** @addtogroup STM32H7xx_HAL_Driver
00084   * @{
00085   */
00086
00087 /** @defgroup FLASHEx  FLASHEx
00088   * @brief FLASH HAL Extension module driver
00089   * @{
00090   */
00091
00092 #ifdef HAL_FLASH_MODULE_ENABLED
00093
00094 /* Private typedef -----------------------------------------------------------*/
00095 /* Private define ------------------------------------------------------------*/
00096 /** @addtogroup FLASHEx_Private_Constants
00097   * @{
00098   */
00099 #define FLASH_TIMEOUT_VALUE       50000U/* 50 s */
00100 /**
00101   * @}
00102   */
00103 /* Private macro -------------------------------------------------------------*/
00104 /* Private variables ---------------------------------------------------------*/
00105 extern FLASH_ProcessTypeDef pFlash;
00106
00107 /* Private function prototypes -----------------------------------------------*/
00108
00109 static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks);
00110 void FLASH_Erase_Sector(uint32_t Sector, uint32_t Bank, uint32_t VoltageRange);
00111 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
00112 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Bank);
00113 static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank);
00114 static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel);
00115 static uint32_t FLASH_OB_GetRDP(void);
00116 static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROConfigRDP, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks);
00117 static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr,uint32_t *PCROPEndAddr, uint32_t Bank);
00118 static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level);
00119 static uint32_t FLASH_OB_GetBOR(void);
00120 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
00121 static uint32_t FLASH_OB_GetUser(void);
00122 static HAL_StatusTypeDef FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1);
00123 static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1);
00124 static HAL_StatusTypeDef FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks);
00125 static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank);
00126
00127 /* Private functions ---------------------------------------------------------*/
00128
00129 /** @defgroup FLASHEx_Private_Functions Extended FLASH Private functions
00130   * @{
00131   */
00132
00133 /** @defgroup FLASHEx_Group1 Extended IO operation functions
00134  *  @brief   Extended IO operation functions
00135  *
00136 @verbatim
00137  ===============================================================================
00138                 ##### Extended programming operation functions #####
00139  ===============================================================================
00140     [..]
00141     This subsection provides a set of functions allowing to manage the Extension FLASH
00142     programming operations Operations.
00143
00144 @endverbatim
00145   * @{
00146   */
00147 /**
00148   * @brief  Perform a mass erase or erase the specified FLASH memory sectors
00149   * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
00150   *         contains the configuration information for the erasing.
00151   *
00152   * @param[out]  SectorError pointer to variable  that
00153   *         contains the configuration information on faulty sector in case of error
00154   *         (0xFFFFFFFF means that all the sectors have been correctly erased)
00155   *
00156   * @retval HAL Status
00157   */
00158 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
00159 {
00160   HAL_StatusTypeDef status = HAL_OK;
00161   uint32_t index = 0;
00162
00163   /* Process Locked */
00164   __HAL_LOCK(&pFlash);
00165
00166   /* Check the parameters */
00167   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
00168   assert_param(IS_VOLTAGERANGE(pEraseInit->VoltageRange));
00169   assert_param(IS_FLASH_BANK(pEraseInit->Banks));
00170
00171
00172   /* Wait for last operation to be completed */
00173   if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
00174   {
00175     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
00176   }
00177
00178   if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
00179   {
00180     status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
00181   }
00182
00183   if(status == HAL_OK)
00184   {
00185     /*Initialization of SectorError variable*/
00186     *SectorError = 0xFFFFFFFF;
00187
00188     if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
00189     {
00190       /*Mass erase to be done*/
00191       FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks);
00192
00193       /* Wait for last operation to be completed */
00194       if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
00195       {
00196         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
00197         /* if the erase operation is completed, disable the Bank1 BER Bit */
00198         FLASH->CR1 &= (~FLASH_CR_BER);
00199       }
00200       if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
00201       {
00202         status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
00203         /* if the erase operation is completed, disable the Bank2 BER Bit */
00204         FLASH->CR2 &= (~FLASH_CR_BER);
00205       }
00206     }
00207     else
00208     {
00209       /* Check the parameters */
00210       assert_param(IS_FLASH_BANK_EXCLUSIVE(pEraseInit->Banks));
00211       assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
00212
00213       /* Erase by sector by sector to be done*/
00214       for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
00215       {
00216         FLASH_Erase_Sector(index, pEraseInit->Banks, pEraseInit->VoltageRange);
00217
00218         if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
00219         {
00220           /* Wait for last operation to be completed */
00221           status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
00222
00223           /* If the erase operation is completed, disable the SER Bit */
00224           FLASH->CR1 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
00225         }
00226         if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
00227         {
00228           /* Wait for last operation to be completed */
00229           status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
00230
00231           /* If the erase operation is completed, disable the SER Bit */
00232           FLASH->CR2 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
00233         }
00234
00235         if(status != HAL_OK)
00236         {
00237           /* In case of error, stop erase procedure and return the faulty sector*/
00238           *SectorError = index;
00239           break;
00240         }
00241       }
00242     }
00243   }
00244
00245   /* Process Unlocked */
00246   __HAL_UNLOCK(&pFlash);
00247
00248   return status;
00249 }
00250
00251 /**
00252   * @brief  Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
00253   * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
00254   *         contains the configuration information for the erasing.
00255   *
00256   * @retval HAL Status
00257   */
00258 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
00259 {
00260   HAL_StatusTypeDef status = HAL_OK;
00261
00262   /* Process Locked */
00263   __HAL_LOCK(&pFlash);
00264
00265   /* Check the parameters */
00266   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
00267   assert_param(IS_VOLTAGERANGE(pEraseInit->VoltageRange));
00268   assert_param(IS_FLASH_BANK(pEraseInit->Banks));
00269
00270   if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
00271   {
00272     /* Clear bank 1 pending flags (if any) */
00273     __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1 | FLASH_FLAG_ALL_ERRORS_BANK1);
00274
00275     /* Enable End of Operation and Error interrupts for Bank 1 */
00276     __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1    | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
00277                                 FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
00278   }
00279   if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
00280   {
00281     /* Clear bank 2 pending flags (if any) */
00282     __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2 | FLASH_FLAG_ALL_ERRORS_BANK2);
00283
00284     /* Enable End of Operation and Error interrupts for Bank 2 */
00285     __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2    | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
00286                                 FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
00287   }
00288
00289   if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
00290   {
00291     /*Mass erase to be done*/
00292     if(pEraseInit->Banks == FLASH_BANK_1)
00293     {
00294       pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK1;
00295     }
00296     else if(pEraseInit->Banks == FLASH_BANK_2)
00297     {
00298       pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK2;
00299     }
00300     else
00301     {
00302       pFlash.ProcedureOnGoing = FLASH_PROC_ALLBANK_MASSERASE;
00303     }
00304
00305     FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks);
00306   }
00307   else
00308   {
00309     /* Erase by sector to be done*/
00310
00311     /* Check the parameters */
00312     assert_param(IS_FLASH_BANK_EXCLUSIVE(pEraseInit->Banks));
00313     assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
00314
00315     if(pEraseInit->Banks == FLASH_BANK_1)
00316     {
00317       pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1;
00318     }
00319     else
00320     {
00321       pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK2;
00322     }
00323
00324     pFlash.NbSectorsToErase = pEraseInit->NbSectors;
00325     pFlash.Sector = pEraseInit->Sector;
00326     pFlash.VoltageForErase = pEraseInit->VoltageRange;
00327
00328     /*Erase 1st sector and wait for IT*/
00329     FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->Banks, pEraseInit->VoltageRange);
00330   }
00331
00332   return status;
00333 }
00334
00335 /**
00336   * @brief  Program option bytes
00337   * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
00338   *         contains the configuration information for the programming.
00339   *
00340   * @retval HAL Status
00341   */
00342 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
00343 {
00344   HAL_StatusTypeDef status = HAL_OK;
00345
00346   /* Process Locked */
00347   __HAL_LOCK(&pFlash);
00348
00349   /* Check the parameters */
00350   assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
00351
00352   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00353
00354   /*Write protection configuration*/
00355   if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
00356   {
00357     assert_param(IS_WRPSTATE(pOBInit->WRPState));
00358     assert_param(IS_FLASH_BANK(pOBInit->Banks));
00359
00360     if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
00361     {
00362       /*Enable of Write protection on the selected Sector*/
00363       status = FLASH_OB_EnableWRP(pOBInit->WRPSector,pOBInit->Banks);
00364     }
00365     else
00366     {
00367       /*Disable of Write protection on the selected Sector*/
00368       status = FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks);
00369     }
00370     if(status != HAL_OK)
00371     {
00372       /* Process Unlocked */
00373       __HAL_UNLOCK(&pFlash);
00374       return status;
00375     }
00376   }
00377
00378   /* Read protection configuration */
00379   if((pOBInit->OptionType & OPTIONBYTE_RDP) != RESET)
00380   {
00381     /* Configure the Read protection level */
00382     status = FLASH_OB_RDPConfig(pOBInit->RDPLevel);
00383     if(status != HAL_OK)
00384     {
00385       /* Process Unlocked */
00386       __HAL_UNLOCK(&pFlash);
00387       return status;
00388     }
00389   }
00390
00391   /* User Configuration */
00392   if((pOBInit->OptionType & OPTIONBYTE_USER) != RESET)
00393   {
00394     /* Configure the user option bytes */
00395     status = FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig);
00396     if(status != HAL_OK)
00397     {
00398       /* Process Unlocked */
00399       __HAL_UNLOCK(&pFlash);
00400       return status;
00401     }
00402   }
00403
00404   /* PCROP Configuration */
00405   if((pOBInit->OptionType & OPTIONBYTE_PCROP) != RESET)
00406   {
00407     assert_param(IS_FLASH_BANK(pOBInit->Banks));
00408
00409     /*Configure the Proprietary code readout protection */
00410     status = FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr, pOBInit->Banks);
00411     if(status != HAL_OK)
00412     {
00413       /* Process Unlocked */
00414       __HAL_UNLOCK(&pFlash);
00415       return status;
00416     }
00417
00418   }
00419
00420   /*BOR Level  configuration*/
00421   if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
00422   {
00423     status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
00424     if(status != HAL_OK)
00425     {
00426       /* Process Unlocked */
00427       __HAL_UNLOCK(&pFlash);
00428       return status;
00429     }
00430   }
00431
00432   /*Boot Address  configuration*/
00433   if((pOBInit->OptionType & OPTIONBYTE_BOOTADD) == OPTIONBYTE_BOOTADD)
00434   {
00435     status = FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
00436     if(status != HAL_OK)
00437     {
00438       /* Process Unlocked */
00439       __HAL_UNLOCK(&pFlash);
00440       return status;
00441     }
00442   }
00443   /*Bank1 secure area  configuration*/
00444   if((pOBInit->OptionType & OPTIONBYTE_SECURE_AREA) == OPTIONBYTE_SECURE_AREA)
00445   {
00446     status = FLASH_OB_SecureAreaConfig(pOBInit->SecureAreaConfig, pOBInit->SecureAreaStartAddr, pOBInit->SecureAreaEndAddr,pOBInit->Banks);
00447     if(status != HAL_OK)
00448     {
00449       /* Process Unlocked */
00450       __HAL_UNLOCK(&pFlash);
00451       return status;
00452     }
00453   }
00454
00455   /* Process Unlocked */
00456   __HAL_UNLOCK(&pFlash);
00457
00458   return status;
00459 }
00460
00461 /**
00462   * @brief Get the Option byte configuration
00463   * @note  The parameter Banks of the pOBInit structure must be exclusively FLASH_BANK_1 or FLASH_BANK_2
00464            as this parameter is use to get the given Bank WRP, PCROP and secured area.
00465   * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
00466   *         contains the configuration information for the programming.
00467   *
00468   * @retval None
00469   */
00470 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
00471 {
00472   /* Check the parameters */
00473   assert_param(IS_FLASH_BANK_EXCLUSIVE(pOBInit->Banks));
00474   pOBInit->OptionType = (OPTIONBYTE_WRP  | OPTIONBYTE_RDP         | \
00475                          OPTIONBYTE_USER | OPTIONBYTE_PCROP       | \
00476                          OPTIONBYTE_BOR  | OPTIONBYTE_BOOTADD | \
00477                          OPTIONBYTE_SECURE_AREA);
00478
00479   /* Get write protection on the selected area */
00480   FLASH_OB_GetWRP(&(pOBInit->WRPState), &(pOBInit->WRPSector), pOBInit->Banks);
00481
00482   /* Get Read protection level */
00483   pOBInit->RDPLevel = FLASH_OB_GetRDP();
00484
00485   /* Get the user option bytes */
00486   pOBInit->USERConfig = FLASH_OB_GetUser();
00487
00488   /* Get the Proprietary code readout protection */
00489   FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr), pOBInit->Banks);
00490
00491   /*Get BOR Level*/
00492   pOBInit->BORLevel = FLASH_OB_GetBOR();
00493
00494   /*Get Boot Address*/
00495   FLASH_OB_GetBootAdd(&(pOBInit->BootAddr0), &(pOBInit->BootAddr1));
00496   /*Get Bank Secure area*/
00497   FLASH_OB_GetSecureArea(&(pOBInit->SecureAreaConfig), &(pOBInit->SecureAreaStartAddr), &(pOBInit->SecureAreaEndAddr), pOBInit->Banks);
00498 }
00499
00500 /**
00501   * @brief  Unlock the FLASH Bank1 control registers access
00502   * @retval HAL Status
00503   */
00504 HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void)
00505 {
00506   if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != RESET)
00507   {
00508     /* Authorize the FLASH A Registers access */
00509     WRITE_REG(FLASH->KEYR1, FLASH_KEY1);
00510     WRITE_REG(FLASH->KEYR1, FLASH_KEY2);
00511   }
00512   else
00513   {
00514     return HAL_ERROR;
00515   }
00516
00517   return HAL_OK;
00518 }
00519
00520 /**
00521   * @brief  Locks the FLASH Bank1 control registers access
00522   * @retval HAL Status
00523   */
00524 HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void)
00525 {
00526   /* Set the LOCK Bit to lock the FLASH A Registers access */
00527   SET_BIT(FLASH->CR1, FLASH_CR_LOCK);
00528   return HAL_OK;
00529 }
00530
00531 /**
00532   * @brief  Unlock the FLASH Bank2 control registers access
00533   * @retval HAL Status
00534   */
00535 HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void)
00536 {
00537   if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != RESET)
00538   {
00539     /* Authorize the FLASH A Registers access */
00540     WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
00541     WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
00542   }
00543   else
00544   {
00545     return HAL_ERROR;
00546   }
00547
00548   return HAL_OK;
00549 }
00550
00551 /**
00552   * @brief  Locks the FLASH Bank2 control registers access
00553   * @retval HAL Status
00554   */
00555 HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void)
00556 {
00557   /* Set the LOCK Bit to lock the FLASH A Registers access */
00558   SET_BIT(FLASH->CR2, FLASH_CR_LOCK);
00559   return HAL_OK;
00560 }
00561
00562 /**
00563   * @brief  Full erase of FLASH memory sectors
00564   * @param  VoltageRange The device program/erase parallelism.
00565   *          This parameter can be one of the following values:
00566   *            @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits
00567   *            @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits
00568   *            @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits
00569   *            @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits
00570   *
00571   * @param  Banks Banks to be erased
00572   *          This parameter can be one of the following values:
00573   *            @arg FLASH_BANK_1: Bank1 to be erased
00574   *            @arg FLASH_BANK_2: Bank2 to be erased
00575   *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
00576   *
00577   * @retval HAL Status
00578   */
00579 static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks)
00580 {
00581   /* Check the parameters */
00582   assert_param(IS_FLASH_BANK(Banks));
00583   assert_param(IS_VOLTAGERANGE(VoltageRange));
00584
00585   /* proceed to erase all sectors */
00586   if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
00587   {
00588     /* reset Program/erase VoltageRange for Bank1 */
00589     FLASH->CR1 &= (~FLASH_CR_PSIZE);
00590
00591     /* Bank1 will be erased, and set voltage range*/
00592     FLASH->CR1 |= FLASH_CR_BER | VoltageRange;
00593     FLASH->CR1 |= FLASH_CR_START;
00594   }
00595   if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
00596   {
00597     /* reset Program/erase VoltageRange for Bank2 */
00598     FLASH->CR2 &= (~FLASH_CR_PSIZE);
00599
00600     /* Bank2 will be erased, and set voltage range*/
00601     FLASH->CR2 |= FLASH_CR_BER | VoltageRange;
00602     FLASH->CR2 |= FLASH_CR_START;
00603   }
00604 }
00605
00606 /**
00607   * @brief  Erase the specified FLASH memory sector
00608   * @param  Sector FLASH sector to erase
00609   * @param  Banks Banks to be erased
00610   *          This parameter can be one of the following values:
00611   *            @arg FLASH_BANK_1: Bank1 to be erased
00612   *            @arg FLASH_BANK_2: Bank2 to be erased
00613   *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
00614   * @param  VoltageRange The device program/erase parallelism.
00615   *          This parameter can be one of the following values:
00616   *            @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits
00617   *            @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits
00618   *            @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits
00619   *            @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 62 bits
00620   *
00621   * @retval None
00622   */
00623 void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange)
00624 {
00625   assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
00626   assert_param(IS_VOLTAGERANGE(VoltageRange));
00627   assert_param(IS_FLASH_SECTOR(Sector));
00628
00629   if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
00630   {
00631     /* reset Program/erase VoltageRange for Bank1 */
00632     FLASH->CR1 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
00633
00634     FLASH->CR1 |= (FLASH_CR_SER | VoltageRange | (Sector << POSITION_VAL(FLASH_CR_SNB)));
00635
00636     FLASH->CR1 |= FLASH_CR_START;
00637   }
00638
00639   if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
00640   {
00641     /* reset Program/erase VoltageRange for Bank2 */
00642     FLASH->CR2 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
00643
00644     FLASH->CR2 |= (FLASH_CR_SER | VoltageRange  | (Sector << POSITION_VAL(FLASH_CR_SNB)));
00645
00646     FLASH->CR2 |= FLASH_CR_START;
00647   }
00648 }
00649
00650 /**
00651   * @brief  Enable the write protection of the desired bank1 or bank 2 sectors
00652   * @param  WRPSector specifies the sector(s) to be write protected.
00653   *          This parameter can be one of the following values:
00654   *            @arg WRPSector:  A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_0 or OB_WRP_SECTOR_All
00655   *
00656   * @param  Banks the specific bank to apply WRP sectors
00657   *          This parameter can be one of the following values:
00658   *            @arg FLASH_BANK_1: WRP enable on specified bank1 sectors
00659   *            @arg FLASH_BANK_2: WRP enable on specified bank2 sectors
00660   *            @arg FLASH_BANK_BOTH: WRP enable bank1 and bank2 specified sectors
00661   *
00662   * @retval HAL FLASH State
00663   */
00664 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
00665 {
00666   HAL_StatusTypeDef status = HAL_OK;
00667
00668   /* Check the parameters */
00669   assert_param(IS_FLASH_BANK(Banks));
00670
00671   if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
00672   {
00673     assert_param(IS_OB_WRP_SECTOR(WRPSector));
00674
00675     /* Wait for last operation to be completed */
00676     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
00677
00678     if(status == HAL_OK)
00679     {
00680       FLASH->WPSN_PRG1 &= (~(WRPSector & FLASH_WPSN_WRPSN));
00681     }
00682   }
00683
00684   if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
00685   {
00686     assert_param(IS_OB_WRP_SECTOR(WRPSector));
00687
00688     /* Wait for last operation to be completed */
00689     status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
00690
00691     if(status == HAL_OK)
00692     {
00693       FLASH->WPSN_PRG2 &= (~(WRPSector & FLASH_WPSN_WRPSN));
00694     }
00695   }
00696
00697   if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
00698   {
00699     /* Wait for last operation to be completed */
00700     status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
00701   }
00702
00703   if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
00704   {
00705     /* Wait for last operation to be completed */
00706     status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
00707   }
00708
00709   return status;
00710 }
00711
00712 /**
00713   * @brief  Disable the write protection of the desired bank1 or bank 2 sectors
00714   * @param  WRPSector specifies the sector(s) to disable write protection.
00715   *          This parameter can be one of the following values:
00716   *            @arg WRPSector:  A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
00717   *
00718   * @param  Banks the specific bank to apply WRP sectors
00719   *          This parameter can be one of the following values:
00720   *            @arg FLASH_BANK_1: WRP disable on specified bank1 sectors
00721   *            @arg FLASH_BANK_2: WRP disable on specified bank2 sectors
00722   *            @arg FLASH_BANK_BOTH: WRP disable bank1 and bank2 specified sectors
00723   *
00724   * @retval HAL FLASH State
00725   */
00726 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
00727 {
00728   HAL_StatusTypeDef status = HAL_OK;
00729
00730   /* Check the parameters */
00731   assert_param(IS_FLASH_BANK(Banks));
00732   assert_param(IS_OB_WRP_SECTOR(WRPSector));
00733
00734   if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
00735   {
00736     /* Wait for last operation to be completed */
00737     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
00738
00739     if(status == HAL_OK)
00740     {
00741       FLASH->WPSN_PRG1 |= (WRPSector & FLASH_WPSN_WRPSN);
00742     }
00743   }
00744
00745   if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
00746   {
00747     /* Wait for last operation to be completed */
00748     status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
00749
00750     if(status == HAL_OK)
00751     {
00752       FLASH->WPSN_PRG2 |= (WRPSector & FLASH_WPSN_WRPSN);
00753     }
00754   }
00755
00756   if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
00757   {
00758     /* Wait for last operation to be completed */
00759     status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
00760   }
00761
00762   if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
00763   {
00764     /* Wait for last operation to be completed */
00765     status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
00766   }
00767
00768   return status;
00769 }
00770
00771 /**
00772   * @brief  Get the write protection of the given bank1 or bank 2 sectors
00773   * @param  WRPState gives the write protection state on the given bank .
00774   *          This parameter can be one of the following values:
00775   *          @arg WRPState: OB_WRPSTATE_DISABLE or OB_WRPSTATE_ENABLE
00776
00777   * @param  WRPSector gives the write protected sector(s) on the given bank .
00778   *          This parameter can be one of the following values:
00779   *          @arg WRPSector:  A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
00780   *
00781   * @param  Bank the specific bank to apply WRP sectors
00782   *          This parameter can be exclusively one of the following values:
00783   *            @arg FLASH_BANK_1: Get bank1 WRP sectors
00784   *            @arg FLASH_BANK_2: Get bank2 WRP sectors
00785   *            @arg FLASH_BANK_BOTH: note allowed in this functions
00786   *
00787   * @retval HAL FLASH State
00788   */
00789 static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank)
00790 {
00791   uint32_t regvalue = 0;
00792   /* Check the parameters */
00793   assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
00794
00795   if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
00796   {
00797     regvalue = FLASH->WPSN_CUR1;
00798   }
00799
00800   if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
00801   {
00802     regvalue = FLASH->WPSN_CUR2;
00803   }
00804
00805   (*WRPSector) = (~(regvalue & FLASH_WPSN_WRPSN)) & FLASH_WPSN_WRPSN;
00806   if(*WRPSector == 0)
00807   {
00808     (*WRPState) = OB_WRPSTATE_DISABLE;
00809   }
00810   else
00811   {
00812     (*WRPState) = OB_WRPSTATE_ENABLE;
00813   }
00814 }
00815
00816 /**
00817   * @brief  Set the read protection level.
00818   *
00819   * @note   To configure the RDP level, the option lock bit OPTLOCK must be
00820   *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
00821   * @note   To validate the RDP level, the option bytes must be reloaded
00822   *         through the call of the HAL_FLASH_OB_Launch() function.
00823   * @note   !!! Warning : When enabling OB_RDP level 2 it's no more possible
00824   *         to go back to level 1 or 0 !!!
00825   *
00826   * @param  RDPLevel specifies the read protection level.
00827   *         This parameter can be one of the following values:
00828   *            @arg OB_RDP_LEVEL_0: No protection
00829   *            @arg OB_RDP_LEVEL_1: Read protection of the memory
00830   *            @arg OB_RDP_LEVEL_2: Full chip protection
00831   *
00832   * @retval HAL status
00833   */
00834 static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel)
00835 {
00836   HAL_StatusTypeDef status = HAL_OK;
00837
00838   /* Check the parameters */
00839   assert_param(IS_OB_RDP_LEVEL(RDPLevel));
00840
00841   /* Wait for last operation to be completed */
00842   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
00843   status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
00844
00845   if(status == HAL_OK)
00846   {
00847     /* Configure the RDP level in the option bytes register */
00848     MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_RDP, RDPLevel);
00849
00850     /* Wait for last operation to be completed */
00851     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
00852     status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
00853   }
00854
00855   return status;
00856 }
00857
00858 /**
00859   * @brief  Get the read protection level.
00860   * @retval RDPLevel specifies the read protection level.
00861   *         This parameter can be one of the following values:
00862   *            @arg OB_RDP_LEVEL_0: No protection
00863   *            @arg OB_RDP_LEVEL_1: Read protection of the memory
00864   *            @arg OB_RDP_LEVEL_2: Full chip protection
00865   */
00866 static uint32_t FLASH_OB_GetRDP(void)
00867 {
00868   return (FLASH->OPTSR_CUR & FLASH_OPTSR_RDP);
00869 }
00870
00871 /**
00872   * @brief  Program the FLASH User Option Byte.
00873   *
00874   * @note   To configure the user option bytes, the option lock bit OPTLOCK must
00875   *         be cleared with the call of the HAL_FLASH_OB_Unlock() function.
00876   *
00877   * @note   To validate the user option bytes, the option bytes must be reloaded
00878   *         through the call of the HAL_FLASH_OB_Launch() function.
00879   *
00880   * @param  UserType The FLASH User Option Bytes to be modified :
00881   *                   a combination of @arg FLASH_OB_USER_Type
00882   *
00883   * @param  UserConfig The FLASH User Option Bytes values:
00884   *         IWDG_SW(Bit4), WWDG_SW(Bit 5), nRST_STOP(Bit 6), nRST_STDY(Bit 7),
00885   *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
00886   *         ePcROP_EN(Bit 21), SWAP_BANK_OPT(Bit 31) .
00887   *
00888   * @retval HAL status
00889   */
00890 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
00891 {
00892   uint32_t optr_reg_val = 0;
00893   uint32_t optr_reg_mask = 0;
00894   HAL_StatusTypeDef status = HAL_OK;
00895
00896   /* Check the parameters */
00897   assert_param(IS_OB_USER_TYPE(UserType));
00898
00899   /* Wait for OB change operation to be completed */
00900   status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00901
00902   if(status == HAL_OK)
00903   {
00904     if((UserType & OB_USER_IWDG1_SW) != RESET)
00905     {
00906       /* IWDG_HW option byte should be modified */
00907       assert_param(IS_OB_IWDG1_SOURCE(UserConfig & FLASH_OPTSR_IWDG1_SW));
00908
00909       /* Set value and mask for IWDG_HW option byte */
00910       optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG1_SW);
00911       optr_reg_mask |= FLASH_OPTSR_IWDG1_SW;
00912     }
00913     if((UserType & OB_USER_NRST_STOP_D1) != RESET)
00914     {
00915       /* NRST_STOP option byte should be modified */
00916       assert_param(IS_OB_STOP_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D1));
00917
00918       /* Set value and mask for NRST_STOP option byte */
00919       optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D1);
00920       optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D1;
00921     }
00922
00923     if((UserType & OB_USER_NRST_STDBY_D1) != RESET)
00924     {
00925       /* NRST_STDBY option byte should be modified */
00926       assert_param(IS_OB_STDBY_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D1));
00927
00928       /* Set value and mask for NRST_STDBY option byte */
00929       optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D1);
00930       optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D1;
00931     }
00932
00933     if((UserType & OB_USER_IWDG_STOP) != RESET)
00934     {
00935       /* IWDG_STOP option byte should be modified */
00936       assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTSR_FZ_IWDG_STOP));
00937
00938       /* Set value and mask for IWDG_STOP option byte */
00939       optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_STOP);
00940       optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_STOP;
00941     }
00942
00943     if((UserType & OB_USER_IWDG_STDBY) != RESET)
00944     {
00945       /* IWDG_STDBY option byte should be modified */
00946       assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY));
00947
00948       /* Set value and mask for IWDG_STDBY option byte */
00949       optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY);
00950       optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_SDBY;
00951     }
00952
00953     if((UserType & OB_USER_SECURITY) != RESET)
00954     {
00955       /* SECURITY option byte should be modified */
00956       assert_param(IS_OB_USER_SECURITY(UserConfig & FLASH_OPTSR_SECURITY));
00957
00958       /* Set value and mask for ePcROP_EN option byte */
00959       optr_reg_val |= (UserConfig & FLASH_OPTSR_SECURITY);
00960       optr_reg_mask |= FLASH_OPTSR_SECURITY;
00961     }
00962     if((UserType & OB_USER_SWAP_BANK) != RESET)
00963     {
00964       /* SWAP_BANK_OPT option byte should be modified */
00965       assert_param(IS_OB_USER_SWAP_BANK(UserConfig & FLASH_OPTSR_SWAP_BANK_OPT));
00966
00967       /* Set value and mask for SWAP_BANK_OPT option byte */
00968       optr_reg_val |= (UserConfig & FLASH_OPTSR_SWAP_BANK_OPT);
00969       optr_reg_mask |= FLASH_OPTSR_SWAP_BANK_OPT;
00970     }
00971
00972     if((UserType & OB_USER_IOHSLV) != RESET)
00973     {
00974       /* IOHSLV_OPT option byte should be modified */
00975       assert_param(IS_OB_USER_IOHSLV(UserConfig & FLASH_OPTSR_IO_HSLV));
00976
00977       /* Set value and mask for IOHSLV_OPT option byte */
00978       optr_reg_val |= (UserConfig & FLASH_OPTSR_IO_HSLV);
00979       optr_reg_mask |= FLASH_OPTSR_IO_HSLV;
00980     }
00981
00982     /* Configure the option bytes register */
00983     MODIFY_REG(FLASH->OPTSR_PRG, optr_reg_mask, optr_reg_val);
00984   }
00985
00986   return status;
00987 }
00988 /**
00989   * @brief  Return the FLASH User Option Byte value.
00990   * @retval The FLASH User Option Bytes values
00991   *         IWDG_SW(Bit4), WWDG_SW(Bit 5), nRST_STOP(Bit 6), nRST_STDY(Bit 7),
00992   *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
00993   *         ePcROP_EN(Bit 21), SWAP_BANK_OPT(Bit 31) .
00994   */
00995 static uint32_t FLASH_OB_GetUser(void)
00996 {
00997   uint32_t userConfig = READ_REG(FLASH->OPTSR_CUR);
00998   userConfig &= (~(FLASH_OPTSR_BOR_LEV | FLASH_OPTSR_RDP));
00999
01000   return userConfig;
01001 }
01002
01003 /**
01004   * @brief  Configure the Proprietary code readout protection of the desired addresses
01005   *
01006   * @note   To configure the PCROP options, the option lock bit OPTLOCK must be
01007   *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
01008   * @note   To validate the PCROP options, the option bytes must be reloaded
01009   *         through the call of the HAL_FLASH_OB_Launch() function.
01010   *
01011   * @param  PCROPConfig specifies if the PCROP area for the given Bank shall be erased or not
01012   *                        when RDP level  decreased from Level 1 to Level 0.
01013   *                        This parameter must be a value of @arg FLASH_OB_PCROP_RDP enumeration
01014   *
01015   * @param  PCROPStartAddr specifies the start address of the Proprietary code readout protection
01016   *          This parameter can be an address between begin and end of the bank
01017   *
01018   * @param  PCROPEndAddr specifies the end address of the Proprietary code readout protection
01019   *          This parameter can be an address between PCROPStartAddr and end of the bank
01020   *
01021   * @param  Banks the specific bank to apply PCROP sectors
01022   *          This parameter can be one of the following values:
01023   *            @arg FLASH_BANK_1: PCROP on specified bank1 area
01024   *            @arg FLASH_BANK_2: PCROP on specified bank2 area
01025   *            @arg FLASH_BANK_BOTH: PCROP on specified bank1 and bank2 area (same config will be applied on both banks)
01026   *
01027   * @retval HAL Status
01028   */
01029 static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks)
01030 {
01031   HAL_StatusTypeDef status = HAL_OK;
01032
01033   /* Check the parameters */
01034   assert_param(IS_FLASH_BANK(Banks));
01035   assert_param(IS_OB_PCROP_RDP(PCROPConfig));
01036   assert_param(IS_FLASH_PROGRAM_ADDRESS(PCROPStartAddr));
01037   assert_param(IS_FLASH_PROGRAM_ADDRESS(PCROPEndAddr));
01038
01039   if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
01040   {
01041     assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPStartAddr));
01042     assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPEndAddr));
01043
01044     /* Wait for last operation to be completed */
01045     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE,FLASH_BANK_1);
01046
01047     if(status == HAL_OK)
01048     {
01049       /* Configure the Proprietary code readout protection */
01050       FLASH->PRAR_PRG1 = ((PCROPStartAddr - FLASH_BANK1_BASE) >> 8);
01051
01052       FLASH->PRAR_PRG1 |= (((PCROPEndAddr - FLASH_BANK1_BASE) >> 8) << POSITION_VAL(FLASH_PRAR_PROT_AREA_END)) ;
01053
01054       FLASH->PRAR_PRG1 |= PCROPConfig;
01055
01056       /* Wait for last operation to be completed */
01057       status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
01058     }
01059   }
01060   if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
01061   {
01062     assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPStartAddr));
01063     assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPEndAddr));
01064
01065     /* Wait for last operation to be completed */
01066     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE,FLASH_BANK_2);
01067
01068     if(status == HAL_OK)
01069     {
01070       FLASH->PRAR_PRG2 = ((PCROPStartAddr - FLASH_BANK2_BASE) >> 8);
01071
01072       FLASH->PRAR_PRG2 |= (((PCROPEndAddr - FLASH_BANK2_BASE) >> 8) << POSITION_VAL(FLASH_PRAR_PROT_AREA_END)) ;
01073
01074       FLASH->PRAR_PRG2 |= PCROPConfig;
01075
01076       /* Wait for last operation to be completed */
01077       status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
01078     }
01079   }
01080
01081   return status;
01082 }
01083
01084 /**
01085   * @brief  Get the Proprietary code readout protection configuration on a given Bank
01086   *
01087   * @param  PCROPConfig gives if the PCROP area for the given Bank shall be erased or not
01088   *                        when RDP level decreased from Level 1 to Level 0 or during a mass erase.
01089   *
01090   * @param  PCROPStartAddr gives the start address of the Proprietary code readout protection of the bank
01091   *
01092   * @param  PCROPEndAddr gives the end address of the Proprietary code readout protection of the bank
01093   *
01094   * @param  Bank the specific bank to apply PCROP sectors
01095   *          This parameter can be exclusively one of the following values:
01096   *            @arg FLASH_BANK_1: PCROP on specified bank1 area
01097   *            @arg FLASH_BANK_2: PCROP on specified bank2 area
01098   *            @arg FLASH_BANK_BOTH: is  not allowed here
01099   *
01100   * @retval HAL Status
01101   */
01102 static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr,uint32_t *PCROPEndAddr, uint32_t Bank)
01103 {
01104   uint32_t regvalue = 0;
01105   uint32_t bankBase = 0;
01106
01107   /* Check the parameters */
01108   assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
01109
01110   if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
01111   {
01112     regvalue = FLASH->PRAR_CUR1;
01113     bankBase = FLASH_BANK1_BASE;
01114   }
01115
01116   if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
01117   {
01118     regvalue = FLASH->PRAR_CUR2;
01119     bankBase = FLASH_BANK2_BASE;
01120   }
01121
01122
01123   (*PCROPConfig) =  (regvalue & FLASH_PRAR_DMEP);
01124
01125   (*PCROPStartAddr) = ((regvalue & FLASH_PRAR_PROT_AREA_START) << 8) + bankBase;
01126   (*PCROPEndAddr) = (regvalue & FLASH_PRAR_PROT_AREA_END) >> POSITION_VAL(FLASH_PRAR_PROT_AREA_END) ;
01127   (*PCROPEndAddr) = ((*PCROPEndAddr) << 8) + bankBase;
01128 }
01129
01130 /**
01131   * @brief  Set the BOR Level.
01132   * @param  Level specifies the Option Bytes BOR Reset Level.
01133   *          This parameter can be one of the following values:
01134   *            @arg OB_BOR_LEVEL1: Supply voltage ranges from 1.69V - 1.8V
01135   *            @arg OB_BOR_LEVEL2: Supply voltage ranges from 1.94V - 2.1V
01136   *            @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.30V - 2.49V
01137   * @retval HAL Status
01138   */
01139 static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
01140 {
01141   HAL_StatusTypeDef status = HAL_OK;
01142
01143   assert_param(IS_OB_BOR_LEVEL(Level));
01144
01145   /* Wait for last operation to be completed */
01146   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
01147   status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
01148
01149   if(status == HAL_OK)
01150   {
01151     /* Configure BOR_LEV option byte */
01152     MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_BOR_LEV, Level );
01153
01154     /* Wait for last operation to be completed */
01155     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
01156     status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
01157   }
01158
01159   return status;
01160 }
01161
01162 /**
01163   * @brief  Get the BOR Level.
01164   * @retval The Option Bytes BOR Reset Level.
01165   *            This parameter can be one of the following values:
01166   *            @arg OB_BOR_LEVEL1: Supply voltage ranges from 1.69V - 1.8V
01167   *            @arg OB_BOR_LEVEL2: Supply voltage ranges from 1.94V - 2.1V
01168   *            @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.30V - 2.49V
01169   */
01170 static uint32_t FLASH_OB_GetBOR(void)
01171 {
01172   return (FLASH->OPTSR_CUR & FLASH_OPTSR_BOR_LEV);
01173 }
01174
01175 /**
01176   * @brief  Set Boot address
01177   * @param  BootOption Boot address option byte to be programmed,
01178   *                     This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION
01179                         (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH)
01180   *
01181   * @param  BootAddress0 Specifies the Boot Address 0
01182   * @param  BootAddress1 Specifies the Boot Address 1
01183   * @retval HAL Status
01184   */
01185 static HAL_StatusTypeDef FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1)
01186 {
01187   HAL_StatusTypeDef status = HAL_OK;
01188
01189   /* Check the parameters */
01190   assert_param(IS_OB_BOOT_ADD_OPTION(BootOption));
01191
01192   /* Wait for last operation to be completed */
01193   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
01194   status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
01195
01196   if(status == HAL_OK)
01197   {
01198     if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0)
01199     {
01200       /* Check the parameters */
01201       assert_param(IS_BOOT_ADDRESS(BootAddress0));
01202
01203       /* Configure CM7 BOOT ADD0 */
01204       MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD0, (BootAddress0 >> 16));
01205     }
01206
01207     if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1)
01208     {
01209       /* Check the parameters */
01210       assert_param(IS_BOOT_ADDRESS(BootAddress1));
01211
01212       /* Configure CM7 BOOT ADD1 */
01213       MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD1, BootAddress1 );
01214     }
01215
01216     /* Wait for last operation to be completed */
01217     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
01218     status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
01219   }
01220
01221   return status;
01222 }
01223
01224 /**
01225   * @brief  Get Boot address
01226   * @param  BootAddress0 Specifies the Boot Address 0.
01227   * @param  BootAddress1 Specifies the Boot Address 1.
01228   * @retval HAL Status
01229   */
01230 static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1)
01231 {
01232   uint32_t regvalue = 0;
01233
01234   regvalue = FLASH->BOOT_CUR;
01235
01236   (*BootAddress0) = (regvalue & FLASH_BOOT_ADD0) << 16;
01237
01238   (*BootAddress1) = (regvalue & FLASH_BOOT_ADD1);
01239
01240 }
01241
01242 /**
01243   * @brief  Set secure area configuration
01244   * @param  SecureAreaConfig specify if the secure area will be deleted or not during next mass-erase,
01245   *
01246   * @param  SecureAreaStartAddr Specifies the secure area start address
01247   * @param  SecureAreaEndAddr Specifies the secure area end address
01248   * @param  Banks Specifies the Bank
01249   * @retval HAL Status
01250   */
01251 static HAL_StatusTypeDef FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks)
01252 {
01253   HAL_StatusTypeDef status = HAL_OK;
01254
01255   /* Check the parameters */
01256   assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
01257   assert_param(IS_OB_SECURE_RDP(SecureAreaConfig));
01258
01259   if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
01260   {
01261     /* Check the parameters */
01262     assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaStartAddr));
01263     assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaEndAddr));
01264
01265     /* Wait for last operation to be completed */
01266     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
01267
01268     if(status == HAL_OK)
01269     {
01270       /* Configure the secure area */
01271       FLASH->SCAR_PRG1 = ((SecureAreaStartAddr - FLASH_BANK1_BASE) >> 8);
01272
01273       FLASH->SCAR_PRG1 |= (((SecureAreaEndAddr - FLASH_BANK1_BASE) >> 8) << POSITION_VAL(FLASH_SCAR_SEC_AREA_END)) ;
01274
01275       FLASH->SCAR_PRG1 |= (SecureAreaConfig & FLASH_SCAR_DMES);
01276
01277       status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
01278
01279     }
01280   }
01281   if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
01282   {
01283     /* Check the parameters */
01284     assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaStartAddr));
01285     assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaEndAddr));
01286
01287     /* Wait for last operation to be completed */
01288     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
01289
01290     if(status == HAL_OK)
01291     {
01292       /* Configure the secure area */
01293       FLASH->SCAR_PRG2 = ((SecureAreaStartAddr - FLASH_BANK2_BASE) >> 8);
01294
01295       FLASH->SCAR_PRG2 |= (((SecureAreaEndAddr - FLASH_BANK2_BASE) >> 8) << POSITION_VAL(FLASH_SCAR_SEC_AREA_END)) ;
01296
01297       FLASH->SCAR_PRG2 |= (SecureAreaConfig & FLASH_SCAR_DMES);
01298
01299       status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
01300     }
01301   }
01302
01303   return status;
01304 }
01305
01306 /**
01307   * @brief  Set secure area configuration
01308   * @param  SecureAreaConfig specify if the secure area will be deleted or not during next mass-erase,
01309   *
01310   * @param  SecureAreaStartAddr Specifies the secure area start address
01311   * @param  SecureAreaEndAddr Specifies the secure area end address
01312   * @param  Bank Specifies the Bank
01313   * @retval HAL Status
01314   */
01315 static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank)
01316 {
01317   uint32_t regvalue = 0;
01318   uint32_t bankBase = 0;
01319
01320   /* Check the parameters */
01321   assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
01322
01323   if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
01324   {
01325     regvalue = FLASH->SCAR_CUR1;
01326     bankBase = FLASH_BANK1_BASE;
01327   }
01328
01329   if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
01330   {
01331     regvalue = FLASH->SCAR_CUR2;
01332     bankBase = FLASH_BANK2_BASE;
01333   }
01334
01335   (*SecureAreaConfig) = (regvalue & FLASH_SCAR_DMES);
01336   (*SecureAreaStartAddr) = ((regvalue & FLASH_SCAR_SEC_AREA_START) << 8) + bankBase;
01337   (*SecureAreaEndAddr) = (regvalue & FLASH_SCAR_SEC_AREA_END) >> POSITION_VAL(FLASH_SCAR_SEC_AREA_END) ;
01338   (*SecureAreaEndAddr) = ((*SecureAreaEndAddr) << 8) + bankBase;
01339
01340 }
01341 /**
01342   * @}
01343   */
01344
01345 /**
01346   * @}
01347   */
01348 #endif /* HAL_FLASH_MODULE_ENABLED */
01349 /**
01350   * @}
01351   */
01352 /**
01353   * @}
01354   */
01355
01356 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_flash_ex.h Source File

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stm32h7xx_hal_flash_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32H7xx_hal_flash_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of FLASH HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_FLASH_EX_H
00040 #define __STM32H7xx_HAL_FLASH_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup FLASHEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup FLASHEx_Exported_Types FLASH Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  FLASH Erase structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t TypeErase;   /*!< Mass erase or sector Erase.
00068                              This parameter can be a value of @ref FLASHEx_Type_Erase */
00069
00070   uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.
00071                              This parameter must be a value of @ref FLASHEx_Banks */
00072
00073   uint32_t Sector;      /*!< Initial FLASH sector to erase when Mass erase is disabled
00074                              This parameter must be a value of @ref FLASH_Sectors */
00075
00076   uint32_t NbSectors;   /*!< Number of sectors to be erased.
00077                              This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
00078
00079   uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
00080                              This parameter must be a value of @ref FLASHEx_Voltage_Range */
00081
00082 } FLASH_EraseInitTypeDef;
00083
00084
00085 /**
00086   * @brief  FLASH Option Bytes Program structure definition
00087   */
00088 typedef struct
00089 {
00090   uint32_t OptionType;   /*!< Option byte to be configured.
00091                               This parameter can be a value of @ref FLASHEx_Option_Type */
00092
00093   uint32_t WRPState;     /*!< Write protection activation or deactivation.
00094                               This parameter can be a value of @ref FLASHEx_WRP_State */
00095
00096   uint32_t WRPSector;    /*!< Specifies the sector(s) to be write protected.
00097                               The value of this parameter depend on device used within the same series */
00098
00099   uint32_t RDPLevel;     /*!< Set the read protection level.
00100                               This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
00101
00102   uint32_t BORLevel;     /*!< Set the BOR Level.
00103                               This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
00104
00105   uint32_t USERType;       /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
00106                                 This parameter can be a combination of @ref FLASHEx_OB_USER_Type */
00107
00108   uint32_t USERConfig;   /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY /
00109                               IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY. */
00110   uint32_t Banks;          /*!< Select banks for WRP , PCROP and secure area config .
00111                                 This parameter must be a value of @ref FLASHEx_Banks */
00112   uint32_t PCROPConfig;    /*!< specifies if the PCROP area shall be erased or not
00113                                 when RDP level decreased from Level 1 to Level 0 or during a mass erase.
00114                                 This parameter must be a value of @ref FLASHEx_OB_PCROP_RDP enumeration */
00115
00116   uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
00117                                 This parameter must be a value between begin and end of a bank */
00118
00119   uint32_t PCROPEndAddr;   /*!< PCROP End address (used for OPTIONBYTE_PCROP).
00120                                 This parameter must be a value between PCROP Start address and end of a bank */
00121
00122   uint32_t BootConfig;  /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1
00123                                 or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */
00124
00125   uint32_t BootAddr0;   /*!< Boot Address 0.
00126                                 This parameter must be a value between begin and end of a bank */
00127
00128   uint32_t BootAddr1;   /*!< Boot Address 1.
00129                                 This parameter must be a value between begin and end of a bank */
00130
00131   uint32_t SecureAreaConfig;  /*!< specifies if the bank secured area shall be erased or not
00132                                    when RDP level decreased from Level 1 to Level 0 or during a mass erase.
00133                                    This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */
00134
00135   uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address.
00136                                      This parameter must be a value between begin and end of bank1 */
00137
00138   uint32_t SecureAreaEndAddr;   /*!< Bank Secure area End address .
00139                                      This parameter must be a value between Start address and end of a bank1 */
00140
00141 } FLASH_OBProgramInitTypeDef;
00142
00143 /**
00144   * @}
00145   */
00146 /* Exported constants --------------------------------------------------------*/
00147
00148 /** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
00149   * @{
00150   */
00151
00152 /** @defgroup FLASHEx_Type_Erase FLASH Type Erase
00153   * @{
00154   */
00155 #define FLASH_TYPEERASE_SECTORS         ((uint32_t)0x00U)  /*!< Sectors erase only          */
00156 #define FLASH_TYPEERASE_MASSERASE       ((uint32_t)0x01U)  /*!< Flash Mass erase activation */
00157 /**
00158   * @}
00159   */
00160
00161 /** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
00162   * @{
00163   */
00164 #define FLASH_VOLTAGE_RANGE_1        ((uint32_t)0x00U)             /*!< Flash program/erase by 8 bits    */
00165 #define FLASH_VOLTAGE_RANGE_2        ((uint32_t)FLASH_CR_PSIZE_0)  /*!< Flash program/erase by 16 bits   */
00166 #define FLASH_VOLTAGE_RANGE_3        ((uint32_t)FLASH_CR_PSIZE_1)  /*!< Flash program/erase by 32 bits   */
00167 #define FLASH_VOLTAGE_RANGE_4        ((uint32_t)FLASH_CR_PSIZE)    /*!< Flash program/erase by 64 bits   */
00168
00169 /**
00170   * @}
00171   */
00172
00173 /** @defgroup FLASHEx_WRP_State FLASH WRP State
00174   * @{
00175   */
00176 #define OB_WRPSTATE_DISABLE       ((uint32_t)0x00U)  /*!< Disable the write protection of the desired bank 1 sectors */
00177 #define OB_WRPSTATE_ENABLE        ((uint32_t)0x01U)  /*!< Enable the write protection of the desired bank 1 sectors  */
00178 /**
00179   * @}
00180   */
00181
00182 /** @defgroup FLASHEx_Option_Type FLASH Option Type
00183   * @{
00184   */
00185 #define OPTIONBYTE_WRP           ((uint32_t)0x01U)  /*!< WRP option byte configuration  */
00186 #define OPTIONBYTE_RDP           ((uint32_t)0x02U)  /*!< RDP option byte configuration  */
00187 #define OPTIONBYTE_USER          ((uint32_t)0x04U)  /*!< USER option byte configuration */
00188 #define OPTIONBYTE_PCROP         ((uint32_t)0x08U)  /*!< PCROP option byte configuration */
00189 #define OPTIONBYTE_BOR           ((uint32_t)0x10U)  /*!< BOR option byte configuration */
00190 #define OPTIONBYTE_SECURE_AREA   ((uint32_t)0x20U)  /*!< secure area option byte configuration */
00191 #define OPTIONBYTE_BOOTADD       ((uint32_t)0x40U)      /*!< BOOT ADD option byte configuration */
00192 /**
00193   * @}
00194   */
00195
00196 /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
00197   * @{
00198   */
00199 #define OB_RDP_LEVEL_0       ((uint32_t)0xAA00U)
00200 #define OB_RDP_LEVEL_1       ((uint32_t)0x5500U)
00201 #define OB_RDP_LEVEL_2       ((uint32_t)0xCC00U)   /*!< Warning: When enabling read protection level 2
00202                                                         it s no more possible to go back to level 1 or 0 */
00203 /**
00204   * @}
00205   */
00206
00207 /** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
00208   * @{
00209   */
00210 #define OB_WWDG_SW           ((uint32_t)0x10U)  /*!< Software WWDG selected */
00211 #define OB_WWDG_HW           ((uint32_t)0x00U)  /*!< Hardware WWDG selected */
00212 /**
00213   * @}
00214   */
00215
00216
00217 /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
00218   * @{
00219   */
00220 #define OB_IWDG_SW           ((uint32_t)0x20U)  /*!< Software IWDG selected */
00221 #define OB_IWDG_HW           ((uint32_t)0x00U)  /*!< Hardware IWDG selected */
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
00227   * @{
00228   */
00229 #define OB_STOP_NO_RST       ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */
00230 #define OB_STOP_RST          ((uint32_t)0x00U) /*!< Reset generated when entering in STOP    */
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
00236   * @{
00237   */
00238 #define OB_STDBY_NO_RST      ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */
00239 #define OB_STDBY_RST         ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY    */
00240 /**
00241   * @}
00242   */
00243
00244 /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
00245   * @{
00246   */
00247 #define OB_IWDG_STOP_FREEZE      ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */
00248 #define OB_IWDG_STOP_ACTIVE      ((uint32_t)FLASH_OPTSR_FZ_IWDG_STOP) /*!< IWDG counter active in STOP mode */
00249 /**
00250   * @}
00251   */
00252
00253 /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
00254   * @{
00255   */
00256 #define OB_IWDG_STDBY_FREEZE      ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */
00257 #define OB_IWDG_STDBY_ACTIVE      ((uint32_t)FLASH_OPTSR_FZ_IWDG_SDBY)  /*!< IWDG counter active in STANDBY mode */
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
00263   * @{
00264   */
00265 #define OB_BOR_LEVEL3          ((uint32_t)0x00U)  /*!< Supply voltage ranges from 2.70 to 3.60 V */
00266 #define OB_BOR_LEVEL2          ((uint32_t)0x04U)  /*!< Supply voltage ranges from 2.40 to 2.70 V */
00267 #define OB_BOR_LEVEL1          ((uint32_t)0x08U)  /*!< Supply voltage ranges from 2.10 to 2.40 V */
00268 #define OB_BOR_OFF             ((uint32_t)0x0CU)  /*!< Supply voltage ranges from 1.62 to 2.10 V */
00269 /**
00270   * @}
00271   */
00272
00273
00274
00275 /** @defgroup FLASHEx_Boot_Address FLASH Boot Address
00276   * @{
00277   */
00278 #define OB_BOOTADDR_ITCM_RAM         ((uint32_t)0x0000U)  /*!< Boot from ITCM RAM (0x00000000)                 */
00279 #define OB_BOOTADDR_SYSTEM           ((uint32_t)0x0040U)  /*!< Boot from System memory bootloader (0x00100000) */
00280 #define OB_BOOTADDR_ITCM_FLASH       ((uint32_t)0x0080U)  /*!< Boot from Flash on ITCM interface (0x00200000)  */
00281 #define OB_BOOTADDR_AXIM_FLASH       ((uint32_t)0x2000U)  /*!< Boot from Flash on AXIM interface (0x08000000)  */
00282 #define OB_BOOTADDR_DTCM_RAM         ((uint32_t)0x8000U)  /*!< Boot from DTCM RAM (0x20000000)                 */
00283 #define OB_BOOTADDR_SRAM1            ((uint32_t)0x8004U)  /*!< Boot from SRAM1 (0x20010000)                    */
00284 #define OB_BOOTADDR_SRAM2            ((uint32_t)0x8013U)  /*!< Boot from SRAM2 (0x2004C000)                    */
00285 /**
00286   * @}
00287   */
00288
00289 /** @defgroup FLASH_Latency FLASH Latency
00290   * @{
00291   */
00292 #define FLASH_LATENCY_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
00293 #define FLASH_LATENCY_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
00294 #define FLASH_LATENCY_2                FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
00295 #define FLASH_LATENCY_3                FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
00296 #define FLASH_LATENCY_4                FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
00297 #define FLASH_LATENCY_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
00298 #define FLASH_LATENCY_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
00299 #define FLASH_LATENCY_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
00300 /**
00301   * @}
00302   */
00303
00304
00305 /** @defgroup FLASHEx_Banks FLASH Banks
00306   * @{
00307   */
00308 #define FLASH_BANK_1                       ((uint32_t)0x01U)                          /*!< Bank 1   */
00309 #define FLASH_BANK_2                       ((uint32_t)0x02U)                          /*!< Bank 2   */
00310 #define FLASH_BANK_BOTH                    ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2  */
00311 /**
00312   * @}
00313   */
00314
00315
00316 /** @defgroup FLASHEx_OB_PCROP_RDP  FLASHEx OB PCROP RDP
00317   * @{
00318   */
00319 #define OB_PCROP_RDP_NOT_ERASE    ((uint32_t)0x00000000U) /*!< PCROP area is not erased when the RDP level
00320                                                               is decreased from Level 1 to Level 0 or during a mass erase */
00321 #define OB_PCROP_RDP_ERASE        ((uint32_t)FLASH_PRAR_DMEP) /*!< PCROP area is erased when the RDP level is
00322                                                               decreased from Level 1 to Level 0 (full mass erase) */
00323
00324 /**
00325   * @}
00326   */
00327
00328
00329
00330 /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
00331   * @{
00332   */
00333 #define OB_WRP_SECTOR_0       ((uint32_t)0x00000001U) /*!< Write protection of Sector0     */
00334 #define OB_WRP_SECTOR_1       ((uint32_t)0x00000002U) /*!< Write protection of Sector1     */
00335 #define OB_WRP_SECTOR_2       ((uint32_t)0x00000004U) /*!< Write protection of Sector2     */
00336 #define OB_WRP_SECTOR_3       ((uint32_t)0x00000008U) /*!< Write protection of Sector3     */
00337 #define OB_WRP_SECTOR_4       ((uint32_t)0x00000010U) /*!< Write protection of Sector4     */
00338 #define OB_WRP_SECTOR_5       ((uint32_t)0x00000020U) /*!< Write protection of Sector5     */
00339 #define OB_WRP_SECTOR_6       ((uint32_t)0x00000040U) /*!< Write protection of Sector6     */
00340 #define OB_WRP_SECTOR_7       ((uint32_t)0x00000080U) /*!< Write protection of Sector7     */
00341 #define OB_WRP_SECTOR_All     ((uint32_t)0x000000FFU) /*!< Write protection of all Sectors */
00342 /**
00343   * @}
00344   */
00345
00346
00347 /** @defgroup FLASHEx_OB_SECURITY  FLASHEx OB SECURITY
00348   * @{
00349   */
00350 #define OB_SECURITY_DISABLE   ((uint32_t)0x00000U)                    /*!< security enabled */
00351 #define OB_SECURITY_ENABLE    ((uint32_t)FLASH_OPTSR_SECURITY)    /*!< security disabled */
00352
00353 /**
00354   * @}
00355   */
00356
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup FLASHEx_OB_IWDG1_SW  FLASHEx OB IWDG1 SW
00362   * @{
00363   */
00364 #define OB_IWDG1_HW             ((uint32_t)FLASH_OPTSR_IWDG1_SW) /*!< Hardware independent watchdog 1 */
00365 #define OB_IWDG1_SW             ((uint32_t)0x00000U)             /*!< Software independent watchdog 1 */
00366 /**
00367   * @}
00368   */
00369 /** @defgroup FLASHEx_OB_NRST_STOP_D1  FLASHEx OB NRST STOP D1
00370   * @{
00371   */
00372 #define OB_STOP_RST_D1            ((uint32_t)0x0000U)                       /*!< Reset generated when entering the D1 to stop mode */
00373 #define OB_STOP_NO_RST_D1         ((uint32_t)FLASH_OPTSR_NRST_STOP_D1)     /*!< No reset generated when entering the D1 to stop mode */
00374
00375 /**
00376   * @}
00377   */
00378
00379 /** @defgroup FLASHEx_OB_NRST_STDBY_D1  FLASHEx OB NRST STDBY D1
00380   * @{
00381   */
00382 #define OB_STDBY_RST_D1           ((uint32_t)0x0000U)                        /*!< Reset generated when entering the D1 to standby mode */
00383 #define OB_STDBY_NO_RST_D1        ((uint32_t)FLASH_OPTSR_NRST_STBY_D1)      /*!< No reset generated when entering the D1 to standby mode */
00384
00385 /**
00386   * @}
00387   */
00388
00389 /** @defgroup FLASHEx_OB_SWAP_BANK  FLASHEx OB SWAP BANK
00390   * @{
00391   */
00392 #define OB_SWAP_BANK_DISABLE     ((uint32_t)0x00000U)                       /*!< Bank swap disabled */
00393 #define OB_SWAP_BANK_ENABLE      ((uint32_t)FLASH_OPTSR_SWAP_BANK_OPT)     /*!< Bank swap enabled */
00394
00395 /**
00396   * @}
00397   */
00398
00399 /** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV
00400   * @{
00401   */
00402 #define OB_IOHSLV_DISABLE     ((uint32_t)0x00000000U)          /*!< IOHSLV disabled */
00403 #define OB_IOHSLV_ENABLE      ((uint32_t)FLASH_OPTSR_IO_HSLV)  /*!< IOHSLV enabled */
00404
00405
00406 /**
00407   * @}
00408   */
00409
00410 /** @defgroup FLASHEx_OB_BOOT_OPTION  FLASHEx OB BOOT OPTION
00411   * @{
00412   */
00413 #define OB_BOOT_ADD0             ((uint32_t)0x01U)                       /*!< Select Boot Address 0 */
00414 #define OB_BOOT_ADD1             ((uint32_t)0x02U)                       /*!< Select Boot Address 1 */
00415 #define OB_BOOT_ADD_BOTH         ((uint32_t)0x03U)                       /*!< Select Boot Address 0 and 1 */
00416
00417
00418 /**
00419   * @}
00420   */
00421
00422  /** @defgroup FLASHEx_OB_USER_Type  FLASHEx OB USER Type
00423   * @{
00424   */
00425 #define OB_USER_NRST_STOP_D1      ((uint32_t)0x0001U) /*!< Reset when entering Stop mode selection*/
00426 #define OB_USER_NRST_STDBY_D1     ((uint32_t)0x0002U) /*!< Reset when entering standby mode selection*/
00427 #define OB_USER_IWDG_STOP         ((uint32_t)0x0004U) /*!< Independent watchdog counter freeze in stop mode */
00428 #define OB_USER_IWDG_STDBY        ((uint32_t)0x0008U) /*!< Independent watchdog counter freeze in standby mode */
00429 #define OB_USER_ST_RAM_SIZE       ((uint32_t)0x0010U) /*!< dedicated DTCM Ram size selection */
00430 #define OB_USER_SECURITY          ((uint32_t)0x0020U) /*!< security selection */
00431 #define OB_USER_SWAP_BANK         ((uint32_t)0x0100U) /*!< Bank swap selection */
00432 #define OB_USER_IOHSLV            ((uint32_t)0x0200U) /*!< IO HSLV selection */
00433 #define OB_USER_IWDG1_SW          ((uint32_t)0x0400U) /*!< Independent watchdog selection */
00434
00435 /**
00436   * @}
00437   */
00438
00439 /** @defgroup FLASHEx_OB_SECURE_RDP  FLASHEx OB SECURE RDP
00440   * @{
00441   */
00442 #define OB_SECURE_RDP_NOT_ERASE    ((uint32_t)0x00000000U)               /*!< Secure area is not erased when the RDP level
00443                                                                              is decreased from Level 1 to Level 0 or during a mass erase*/
00444 #define OB_SECURE_RDP_ERASE        ((uint32_t)FLASH_SCAR_DMES)          /*!< Secure area is erased when the RDP level is
00445                                                                              decreased from Level 1 to Level 0 (full mass erase) */
00446
00447 /**
00448   * @}
00449   */
00450
00451 /* Exported macro ------------------------------------------------------------*/
00452 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
00453   * @{
00454   */
00455 /**
00456   * @brief  Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)
00457   * @note   Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].
00458   * @param  __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)
00459   * @retval The FLASH Boot Base Adress
00460   */
00461 #define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14)
00462  /**
00463   * @}
00464   */
00465
00466 /* Exported functions --------------------------------------------------------*/
00467 /** @addtogroup FLASHEx_Exported_Functions
00468   * @{
00469   */
00470
00471 /** @addtogroup FLASHEx_Exported_Functions_Group1
00472   * @{
00473   */
00474 /* Extension Program operation functions  *************************************/
00475 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
00476 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
00477 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
00478 void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
00479
00480 HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void);
00481 HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void);
00482 HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void);
00483 HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void);
00484
00485 /**
00486   * @}
00487   */
00488
00489 /**
00490   * @}
00491   */
00492 /* Private types -------------------------------------------------------------*/
00493 /* Private variables ---------------------------------------------------------*/
00494 /* Private constants ---------------------------------------------------------*/
00495 /* Private macros ------------------------------------------------------------*/
00496 /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
00497   * @{
00498   */
00499
00500 /** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters
00501   * @{
00502   */
00503
00504 #define IS_FLASH_TYPEERASE(VALUE)    (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
00505                                       ((VALUE) == FLASH_TYPEERASE_MASSERASE))
00506
00507 #define IS_VOLTAGERANGE(RANGE)    (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
00508                                    ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
00509                                    ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
00510                                    ((RANGE) == FLASH_VOLTAGE_RANGE_4))
00511
00512 #define IS_WRPSTATE(VALUE)    (((VALUE) == OB_WRPSTATE_DISABLE) || \
00513                                ((VALUE) == OB_WRPSTATE_ENABLE))
00514 #define IS_OPTIONBYTE(VALUE)    ((VALUE) <= (OB_USER_IWDG1_SW | OB_USER_NRST_STDBY_D1 | OB_USER_NRST_STOP_D1  |\
00515                                              OB_USER_IWDG_STOP| OB_USER_IWDG_STDBY    | OB_USER_SWAP_BANK     |\
00516                                              OB_USER_ST_RAM_SIZE   | OB_USER_SECURITY))
00517
00518
00519 #define IS_OB_BOOT_ADDRESS(ADDRESS)     ((ADDRESS) <= 0x8013U)
00520
00521
00522 #define IS_OB_RDP_LEVEL(LEVEL)             (((LEVEL) == OB_RDP_LEVEL_0)   ||\
00523                                             ((LEVEL) == OB_RDP_LEVEL_1) ||\
00524                                             ((LEVEL) == OB_RDP_LEVEL_2))
00525
00526 #define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
00527
00528 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
00529
00530 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
00531
00532 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
00533
00534 #define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
00535
00536 #define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
00537
00538 #define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
00539                                 ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
00540
00541 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \
00542                                    ((LATENCY) == FLASH_LATENCY_1)  || \
00543                                    ((LATENCY) == FLASH_LATENCY_2)  || \
00544                                    ((LATENCY) == FLASH_LATENCY_3)  || \
00545                                    ((LATENCY) == FLASH_LATENCY_4)  || \
00546                                    ((LATENCY) == FLASH_LATENCY_5)  || \
00547                                    ((LATENCY) == FLASH_LATENCY_6)  || \
00548                                    ((LATENCY) == FLASH_LATENCY_7))
00549
00550 #define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
00551
00552 #define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
00553
00554 #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
00555                                  ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
00556                                  ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
00557                                  ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7))
00558
00559 #define IS_OB_WRP_SECTOR(SECTOR)  ((((SECTOR) & (uint32_t)0xFFFFFF00) == 0x00000000U) && ((SECTOR) != 0x00000000U))
00560
00561 #define IS_FLASH_BANK(BANK)        (((BANK) == FLASH_BANK_1)  || \
00562                                     ((BANK) == FLASH_BANK_2)  || \
00563                                     ((BANK) == FLASH_BANK_BOTH))
00564
00565 #define IS_OB_PCROP_RDP(CONFIG)         (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
00566                                              ((CONFIG) == OB_PCROP_RDP_ERASE))
00567
00568 #define IS_OB_SECURE_RDP(CONFIG)         (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \
00569                                              ((CONFIG) == OB_SECURE_RDP_ERASE))
00570
00571 #define IS_OB_USER_SWAP_BANK(VALUE)      (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))
00572
00573 #define IS_OB_USER_IOHSLV(VALUE)         (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
00574
00575 #define IS_OB_IWDG1_SOURCE(SOURCE)       (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
00576 #define IS_OB_STOP_D1_RESET(VALUE)       (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
00577
00578 #define IS_OB_STDBY_D1_RESET(VALUE)      (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
00579
00580 #define IS_OB_USER_IWDG_STOP(VALUE)      (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))
00581
00582 #define IS_OB_USER_IWDG_STDBY(VALUE)     (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))
00583
00584 #define IS_OB_USER_SECURITY(VALUE)       (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE))  /*User can only move the security bit from 0 to 1*/
00585 #define IS_OB_USER_TYPE(TYPE)            (((TYPE) <= (uint32_t)0x400U) && ((TYPE) != 0))
00586
00587 #define IS_OB_BOOT_ADD_OPTION(VALUE)     (((VALUE) == OB_BOOT_ADD0) || \
00588                                            ((VALUE) == OB_BOOT_ADD1)  || \
00589                                            ((VALUE) == OB_BOOT_ADD_BOTH))
00590
00591 /**
00592   * @}
00593   */
00594
00595 /**
00596   * @}
00597   */
00598
00599 /* Private functions ---------------------------------------------------------*/
00600 /** @defgroup FLASHEx_Private_Functions Extended FLASH Private functions
00601   * @{
00602   */
00603 void FLASH_Erase_Sector(uint32_t Sector, uint32_t Bank, uint32_t VoltageRange);
00604 /**
00605   * @}
00606   */
00607
00608 /**
00609   * @}
00610   */
00611
00612 /**
00613   * @}
00614   */
00615
00616 /**
00617   * @}
00618   */
00619
00620 #ifdef __cplusplus
00621 }
00622 #endif
00623
00624 #endif /* __STM32H7xx_HAL_FLASH_EX_H */
00625
00626 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_gpio.c Source File

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stm32h7xx_hal_gpio.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_gpio.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   GPIO HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                     ##### GPIO Peripheral features #####
00016   ==============================================================================
00017   [..]
00018   Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
00019   port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
00020   in several modes:
00021   (+) Input mode
00022   (+) Analog mode
00023   (+) Output mode
00024   (+) Alternate function mode
00025   (+) External interrupt/event lines
00026
00027   [..]
00028   During and just after reset, the alternate functions and external interrupt
00029         lines are not active and the I/O ports are configured in input floating mode.
00030
00031   [..]
00032   All GPIO pins have weak internal pull-up and pull-down resistors, which can be
00033         activated or not.
00034
00035   [..]
00036   In Output or Alternate mode, each IO can be configured on open-drain or push-pull
00037         type and the IO speed can be selected depending on the VDD value.
00038
00039   [..]
00040   All ports have external interrupt/event capability. To use external interrupt
00041         lines, the port must be configured in input mode. All available GPIO pins are
00042         connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
00043
00044   [..]
00045   The external interrupt/event controller consists of up to 23 edge detectors
00046         (16 lines are connected to GPIO) for generating event/interrupt requests (each
00047         input line can be independently configured to select the type (interrupt or event)
00048         and the corresponding trigger event (rising or falling or both). Each line can
00049         also be masked independently.
00050
00051                      ##### How to use this driver #####
00052   ==============================================================================
00053   [..]
00054     (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
00055
00056     (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
00057         (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
00058         (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
00059              structure.
00060         (++) In case of Output or alternate function mode selection: the speed is
00061              configured through "Speed" member from GPIO_InitTypeDef structure.
00062         (++) In alternate mode is selection, the alternate function connected to the IO
00063              is configured through "Alternate" member from GPIO_InitTypeDef structure.
00064         (++) Analog mode is required when a pin is to be used as ADC channel
00065              or DAC output.
00066         (++) In case of external interrupt/event selection the "Mode" member from
00067              GPIO_InitTypeDef structure select the type (interrupt or event) and
00068              the corresponding trigger event (rising or falling or both).
00069
00070     (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
00071         mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
00072         HAL_NVIC_EnableIRQ().
00073
00074     (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
00075
00076     (#) To set/reset the level of a pin configured in output mode use
00077         HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
00078
00079    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
00080
00081
00082     (#) During and just after reset, the alternate functions are not
00083         active and the GPIO pins are configured in input floating mode (except JTAG
00084         pins).
00085
00086     (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
00087         (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
00088         priority over the GPIO function.
00089
00090     (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
00091         general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
00092         The HSE has priority over the GPIO function.
00093
00094   @endverbatim
00095   ******************************************************************************
00096   * @attention
00097   *
00098   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00099   *
00100   * Redistribution and use in source and binary forms, with or without modification,
00101   * are permitted provided that the following conditions are met:
00102   *   1. Redistributions of source code must retain the above copyright notice,
00103   *      this list of conditions and the following disclaimer.
00104   *   2. Redistributions in binary form must reproduce the above copyright notice,
00105   *      this list of conditions and the following disclaimer in the documentation
00106   *      and/or other materials provided with the distribution.
00107   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00108   *      may be used to endorse or promote products derived from this software
00109   *      without specific prior written permission.
00110   *
00111   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00112   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00113   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00114   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00115   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00116   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00117   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00118   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00119   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00120   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00121   *
00122   ******************************************************************************
00123   */
00124
00125 /* Includes ------------------------------------------------------------------*/
00126 #include "stm32h7xx_hal.h"
00127
00128 /** @addtogroup STM32H7xx_HAL_Driver
00129   * @{
00130   */
00131
00132 /** @defgroup GPIO  GPIO
00133   * @brief GPIO HAL module driver
00134   * @{
00135   */
00136
00137 #ifdef HAL_GPIO_MODULE_ENABLED
00138
00139 /* Private typedef -----------------------------------------------------------*/
00140 /* Private defines ------------------------------------------------------------*/
00141 /** @addtogroup GPIO_Private_Constants GPIO Private Constants
00142   * @{
00143   */
00144 #define GPIO_MODE             ((uint32_t)0x00000003)
00145 #define ANALOG_MODE           ((uint32_t)0x00000008)
00146 #define EXTI_MODE             ((uint32_t)0x10000000)
00147 #define GPIO_MODE_IT          ((uint32_t)0x00010000)
00148 #define GPIO_MODE_EVT         ((uint32_t)0x00020000)
00149 #define RISING_EDGE           ((uint32_t)0x00100000)
00150 #define FALLING_EDGE          ((uint32_t)0x00200000)
00151 #define GPIO_OUTPUT_TYPE      ((uint32_t)0x00000010)
00152
00153 #define GPIO_NUMBER           ((uint32_t)16)
00154 /**
00155   * @}
00156   */
00157 /* Private macro -------------------------------------------------------------*/
00158 /* Private variables ---------------------------------------------------------*/
00159 /* Private function prototypes -----------------------------------------------*/
00160 /* Private functions ---------------------------------------------------------*/
00161 /* Exported functions --------------------------------------------------------*/
00162 /** @defgroup GPIO_Exported_Functions GPIO Exported Functions
00163   * @{
00164   */
00165
00166 /** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
00167  *  @brief    Initialization and Configuration functions
00168  *
00169 @verbatim
00170  ===============================================================================
00171               ##### Initialization and de-initialization functions #####
00172  ===============================================================================
00173   [..]
00174     This section provides functions allowing to initialize and de-initialize the GPIOs
00175     to be ready for use.
00176
00177 @endverbatim
00178   * @{
00179   */
00180
00181 /**
00182   * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
00183   * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
00184   * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
00185   *         the configuration information for the specified GPIO peripheral.
00186   * @retval None
00187   */
00188 void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
00189 {
00190   uint32_t position = 0x00;
00191   uint32_t ioposition = 0x00;
00192   uint32_t iocurrent = 0x00;
00193   uint32_t temp = 0x00;
00194
00195   /* Check the parameters */
00196   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00197   assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
00198   assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
00199   assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
00200
00201   /* Configure the port pins */
00202   for(position = 0; position < GPIO_NUMBER; position++)
00203   {
00204     /* Get the IO position */
00205     ioposition = ((uint32_t)0x01) << position;
00206     /* Get the current IO position */
00207     iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
00208
00209     if(iocurrent == ioposition)
00210     {
00211       /*--------------------- GPIO Mode Configuration ------------------------*/
00212       /* In case of Alternate function mode selection */
00213       if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
00214       {
00215         /* Check the Alternate function parameter */
00216         assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
00217
00218         /* Configure Alternate function mapped with the current IO */
00219         temp = GPIOx->AFR[position >> 3];
00220         temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
00221         temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
00222         GPIOx->AFR[position >> 3] = temp;
00223       }
00224
00225       /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
00226       temp = GPIOx->MODER;
00227       temp &= ~(GPIO_MODER_MODER0 << (position * 2));
00228       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
00229       GPIOx->MODER = temp;
00230
00231       /* In case of Output or Alternate function mode selection */
00232       if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
00233          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
00234       {
00235         /* Check the Speed parameter */
00236         assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
00237         /* Configure the IO Speed */
00238         temp = GPIOx->OSPEEDR;
00239         temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
00240         temp |= (GPIO_Init->Speed << (position * 2));
00241         GPIOx->OSPEEDR = temp;
00242
00243         /* Configure the IO Output Type */
00244         temp = GPIOx->OTYPER;
00245         temp &= ~(GPIO_OTYPER_OT_0 << position) ;
00246         temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
00247         GPIOx->OTYPER = temp;
00248       }
00249
00250       /* Activate the Pull-up or Pull down resistor for the current IO */
00251       temp = GPIOx->PUPDR;
00252       temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
00253       temp |= ((GPIO_Init->Pull) << (position * 2));
00254       GPIOx->PUPDR = temp;
00255
00256       /*--------------------- EXTI Mode Configuration ------------------------*/
00257       /* Configure the External Interrupt or event for the current IO */
00258
00259       if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
00260       {
00261         /* Enable SYSCFG Clock */
00262         __HAL_RCC_SYSCFG_CLK_ENABLE();
00263
00264         temp = SYSCFG->EXTICR[position >> 2];
00265         temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
00266         temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
00267         SYSCFG->EXTICR[position >> 2] = temp;
00268
00269         /* Clear EXTI line configuration */
00270         temp = EXTI_D1->IMR1;
00271         temp &= ~((uint32_t)iocurrent);
00272         if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
00273         {
00274           temp |= iocurrent;
00275         }
00276         EXTI_D1->IMR1 = temp;
00277
00278         temp = EXTI_D1->EMR1;
00279         temp &= ~((uint32_t)iocurrent);
00280         if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
00281         {
00282           temp |= iocurrent;
00283         }
00284         EXTI_D1->EMR1 = temp;
00285
00286         /* Clear Rising Falling edge configuration */
00287         temp = EXTI->RTSR1;
00288         temp &= ~((uint32_t)iocurrent);
00289         if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
00290         {
00291           temp |= iocurrent;
00292         }
00293         EXTI->RTSR1 = temp;
00294
00295         temp = EXTI->FTSR1;
00296         temp &= ~((uint32_t)iocurrent);
00297         if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
00298         {
00299           temp |= iocurrent;
00300         }
00301         EXTI->FTSR1 = temp;
00302       }
00303
00304
00305     }
00306   }
00307 }
00308
00309 /**
00310   * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
00311   * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
00312   * @param  GPIO_Pin: specifies the port bit to be written.
00313   *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
00314   * @retval None
00315   */
00316 void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
00317 {
00318   uint32_t position;
00319   uint32_t ioposition = 0x00;
00320   uint32_t iocurrent = 0x00;
00321   uint32_t tmp = 0x00;
00322
00323   /* Check the parameters */
00324   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00325
00326   /* Configure the port pins */
00327   for(position = 0; position < GPIO_NUMBER; position++)
00328   {
00329     /* Get the IO position */
00330     ioposition = ((uint32_t)0x01) << position;
00331     /* Get the current IO position */
00332     iocurrent = (GPIO_Pin) & ioposition;
00333
00334     if(iocurrent == ioposition)
00335     {
00336       /*------------------------- GPIO Mode Configuration --------------------*/
00337       /* Configure IO in Analog Mode */
00338       GPIOx->MODER |= (GPIO_MODER_MODER0 << (position * 2));
00339
00340       /* Configure the default Alternate Function in current IO */
00341       GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
00342
00343       /* Configure the default value for IO Speed */
00344       GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
00345
00346       /* Configure the default value IO Output Type */
00347       GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT_0 << position) ;
00348
00349       /* Deactivate the Pull-up and Pull-down resistor for the current IO */
00350       GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
00351
00352       /*------------------------- EXTI Mode Configuration --------------------*/
00353       tmp = SYSCFG->EXTICR[position >> 2];
00354       tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
00355       if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
00356       {
00357       /* Configure the External Interrupt or event for the current IO */
00358       tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
00359       SYSCFG->EXTICR[position >> 2] &= ~tmp;
00360
00361       /* Clear EXTI line configuration */
00362       EXTI_D1->IMR1 &= ~((uint32_t)iocurrent);
00363       EXTI_D1->EMR1 &= ~((uint32_t)iocurrent);
00364
00365       /* Clear Rising Falling edge configuration */
00366       EXTI->RTSR1 &= ~((uint32_t)iocurrent);
00367       EXTI->FTSR1 &= ~((uint32_t)iocurrent);
00368            }
00369     }
00370   }
00371 }
00372
00373 /**
00374   * @}
00375   */
00376
00377 /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
00378  *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
00379  *
00380 @verbatim
00381  ===============================================================================
00382                        ##### IO operation functions #####
00383  ===============================================================================
00384
00385 @endverbatim
00386   * @{
00387   */
00388
00389 /**
00390   * @brief  Reads the specified input port pin.
00391   * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
00392   * @param  GPIO_Pin: specifies the port bit to read.
00393   *         This parameter can be GPIO_PIN_x where x can be (0..15).
00394   * @retval The input port pin value.
00395   */
00396 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00397 {
00398   GPIO_PinState bitstatus;
00399
00400   /* Check the parameters */
00401   assert_param(IS_GPIO_PIN(GPIO_Pin));
00402
00403   if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
00404   {
00405     bitstatus = GPIO_PIN_SET;
00406   }
00407   else
00408   {
00409     bitstatus = GPIO_PIN_RESET;
00410   }
00411   return bitstatus;
00412 }
00413
00414 /**
00415   * @brief  Sets or clears the selected data port bit.
00416   *
00417   * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
00418   *         accesses. In this way, there is no risk of an IRQ occurring between
00419   *         the read and the modify access.
00420   *
00421   * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
00422   * @param  GPIO_Pin: specifies the port bit to be written.
00423   *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
00424   * @param  PinState: specifies the value to be written to the selected bit.
00425   *          This parameter can be one of the GPIO_PinState enum values:
00426   *            @arg GPIO_PIN_RESET: to clear the port pin
00427   *            @arg GPIO_PIN_SET: to set the port pin
00428   * @retval None
00429   */
00430 void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
00431 {
00432   /* Check the parameters */
00433   assert_param(IS_GPIO_PIN(GPIO_Pin));
00434   assert_param(IS_GPIO_PIN_ACTION(PinState));
00435
00436   if(PinState != GPIO_PIN_RESET)
00437   {
00438     GPIOx->BSRRL = GPIO_Pin;
00439   }
00440   else
00441   {
00442     GPIOx->BSRRH = GPIO_Pin ;
00443   }
00444 }
00445
00446 /**
00447   * @brief  Toggles the specified GPIO pins.
00448   * @param  GPIOx: Where x can be (A..K) to select the GPIO peripheral.
00449   * @param  GPIO_Pin: Specifies the pins to be toggled.
00450   * @retval None
00451   */
00452 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00453 {
00454   /* Check the parameters */
00455   assert_param(IS_GPIO_PIN(GPIO_Pin));
00456
00457   GPIOx->ODR ^= GPIO_Pin;
00458 }
00459
00460 /**
00461   * @brief  Locks GPIO Pins configuration registers.
00462   * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
00463   *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
00464   * @note   The configuration of the locked GPIO pins can no longer be modified
00465   *         until the next reset.
00466   * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32H7 family
00467   * @param  GPIO_Pin: specifies the port bit to be locked.
00468   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
00469   * @retval None
00470   */
00471 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00472 {
00473   __IO uint32_t tmp = GPIO_LCKR_LCKK;
00474
00475   /* Check the parameters */
00476   assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
00477   assert_param(IS_GPIO_PIN(GPIO_Pin));
00478
00479   /* Apply lock key write sequence */
00480   tmp |= GPIO_Pin;
00481   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
00482   GPIOx->LCKR = tmp;
00483   /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
00484   GPIOx->LCKR = GPIO_Pin;
00485   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
00486   GPIOx->LCKR = tmp;
00487   /* Read LCKK bit*/
00488   tmp = GPIOx->LCKR;
00489
00490  if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
00491   {
00492     return HAL_OK;
00493   }
00494   else
00495   {
00496     return HAL_ERROR;
00497   }
00498 }
00499
00500 /**
00501   * @brief  Handle EXTI interrupt request.
00502   * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
00503   * @retval None
00504   */
00505 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
00506 {
00507     /* EXTI line interrupt detected */
00508   if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
00509   {
00510     __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
00511     HAL_GPIO_EXTI_Callback(GPIO_Pin);
00512   }
00513
00514
00515 }
00516
00517 /**
00518   * @brief  EXTI line detection callback.
00519   * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
00520   * @retval None
00521   */
00522 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
00523 {
00524   /* Prevent unused argument(s) compilation warning */
00525   UNUSED(GPIO_Pin);
00526
00527   /* NOTE: This function Should not be modified, when the callback is needed,
00528            the HAL_GPIO_EXTI_Callback could be implemented in the user file
00529    */
00530 }
00531
00532 /**
00533   * @}
00534   */
00535
00536
00537 /**
00538   * @}
00539   */
00540
00541 #endif /* HAL_GPIO_MODULE_ENABLED */
00542 /**
00543   * @}
00544   */
00545
00546 /**
00547   * @}
00548   */
00549
00550 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_gpio.h Source File

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stm32h7xx_hal_gpio.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_gpio.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of GPIO HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_GPIO_H
00040 #define __STM32H7xx_HAL_GPIO_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup GPIO
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup GPIO_Exported_Types GPIO Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief   GPIO Init structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.
00068                            This parameter can be any value of @ref GPIO_pins_define */
00069
00070   uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
00071                            This parameter can be a value of @ref GPIO_mode_define */
00072
00073   uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
00074                            This parameter can be a value of @ref GPIO_pull_define */
00075
00076   uint32_t Speed;     /*!< Specifies the speed for the selected pins.
00077                            This parameter can be a value of @ref GPIO_speed_define */
00078
00079   uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins.
00080                             This parameter can be a value of @ref GPIO_Alternate_function_selection */
00081 }GPIO_InitTypeDef;
00082
00083 /**
00084   * @brief  GPIO Bit SET and Bit RESET enumeration
00085   */
00086 typedef enum
00087 {
00088   GPIO_PIN_RESET = 0,
00089   GPIO_PIN_SET
00090 }GPIO_PinState;
00091 /**
00092   * @}
00093   */
00094
00095 /* Exported constants --------------------------------------------------------*/
00096
00097 /** @defgroup GPIO_Exported_Constants  GPIO Exported Constants
00098   * @{
00099   */
00100
00101 /** @defgroup GPIO_pins_define  GPIO pins define
00102   * @{
00103   */
00104 #define GPIO_PIN_0                 ((uint16_t)0x0001U)  /* Pin 0 selected    */
00105 #define GPIO_PIN_1                 ((uint16_t)0x0002U)  /* Pin 1 selected    */
00106 #define GPIO_PIN_2                 ((uint16_t)0x0004U)  /* Pin 2 selected    */
00107 #define GPIO_PIN_3                 ((uint16_t)0x0008U)  /* Pin 3 selected    */
00108 #define GPIO_PIN_4                 ((uint16_t)0x0010U)  /* Pin 4 selected    */
00109 #define GPIO_PIN_5                 ((uint16_t)0x0020U)  /* Pin 5 selected    */
00110 #define GPIO_PIN_6                 ((uint16_t)0x0040U)  /* Pin 6 selected    */
00111 #define GPIO_PIN_7                 ((uint16_t)0x0080U)  /* Pin 7 selected    */
00112 #define GPIO_PIN_8                 ((uint16_t)0x0100U)  /* Pin 8 selected    */
00113 #define GPIO_PIN_9                 ((uint16_t)0x0200U)  /* Pin 9 selected    */
00114 #define GPIO_PIN_10                ((uint16_t)0x0400U)  /* Pin 10 selected   */
00115 #define GPIO_PIN_11                ((uint16_t)0x0800U)  /* Pin 11 selected   */
00116 #define GPIO_PIN_12                ((uint16_t)0x1000U)  /* Pin 12 selected   */
00117 #define GPIO_PIN_13                ((uint16_t)0x2000U)  /* Pin 13 selected   */
00118 #define GPIO_PIN_14                ((uint16_t)0x4000U)  /* Pin 14 selected   */
00119 #define GPIO_PIN_15                ((uint16_t)0x8000U)  /* Pin 15 selected   */
00120 #define GPIO_PIN_All               ((uint16_t)0xFFFFU)  /* All pins selected */
00121
00122 #define GPIO_PIN_MASK              ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */
00123 /**
00124   * @}
00125   */
00126
00127 /** @defgroup GPIO_mode_define  GPIO mode define
00128   * @brief GPIO Configuration Mode
00129   *        Elements values convention: 0xX0yz00YZ
00130   *           - X  : GPIO mode or EXTI Mode
00131   *           - y  : External IT or Event trigger detection
00132   *           - z  : IO configuration on External IT or Event
00133   *           - Y  : Output type (Push Pull or Open Drain)
00134   *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
00135   * @{
00136   */
00137 #define  GPIO_MODE_INPUT                        ((uint32_t)0x00000000U)   /*!< Input Floating Mode                   */
00138 #define  GPIO_MODE_OUTPUT_PP                    ((uint32_t)0x00000001U)   /*!< Output Push Pull Mode                 */
00139 #define  GPIO_MODE_OUTPUT_OD                    ((uint32_t)0x00000011U)   /*!< Output Open Drain Mode                */
00140 #define  GPIO_MODE_AF_PP                        ((uint32_t)0x00000002U)   /*!< Alternate Function Push Pull Mode     */
00141 #define  GPIO_MODE_AF_OD                        ((uint32_t)0x00000012U)   /*!< Alternate Function Open Drain Mode    */
00142
00143 #define  GPIO_MODE_ANALOG                       ((uint32_t)0x00000003U)   /*!< Analog Mode  */
00144
00145 #define  GPIO_MODE_IT_RISING                    ((uint32_t)0x11110000U)   /*!< External Interrupt Mode with Rising edge trigger detection          */
00146 #define  GPIO_MODE_IT_FALLING                   ((uint32_t)0x11210000U)   /*!< External Interrupt Mode with Falling edge trigger detection         */
00147 #define  GPIO_MODE_IT_RISING_FALLING            ((uint32_t)0x11310000U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
00148
00149 #define  GPIO_MODE_EVT_RISING                   ((uint32_t)0x11120000U)   /*!< External Event Mode with Rising edge trigger detection               */
00150 #define  GPIO_MODE_EVT_FALLING                  ((uint32_t)0x11220000U)   /*!< External Event Mode with Falling edge trigger detection              */
00151 #define  GPIO_MODE_EVT_RISING_FALLING           ((uint32_t)0x11320000U)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
00152
00153 /**
00154   * @}
00155   */
00156
00157 /** @defgroup GPIO_speed_define  GPIO speed define
00158   * @brief GPIO Output Maximum frequency
00159   * @{
00160   */
00161 #define  GPIO_SPEED_FREQ_LOW         ((uint32_t)0x00000000U)  /*!< Low speed     */
00162 #define  GPIO_SPEED_FREQ_MEDIUM      ((uint32_t)0x00000001U)  /*!< Medium speed  */
00163 #define  GPIO_SPEED_FREQ_HIGH        ((uint32_t)0x00000002U)  /*!< Fast speed    */
00164 #define  GPIO_SPEED_FREQ_VERY_HIGH   ((uint32_t)0x00000003U)  /*!< High speed    */
00165 /**
00166   * @}
00167   */
00168
00169  /** @defgroup GPIO_pull_define  GPIO pull define
00170    * @brief GPIO Pull-Up or Pull-Down Activation
00171    * @{
00172    */
00173 #define  GPIO_NOPULL        ((uint32_t)0x00000000U)   /*!< No Pull-up or Pull-down activation  */
00174 #define  GPIO_PULLUP        ((uint32_t)0x00000001U)   /*!< Pull-up activation                  */
00175 #define  GPIO_PULLDOWN      ((uint32_t)0x00000002U)   /*!< Pull-down activation                */
00176 /**
00177   * @}
00178   */
00179
00180 /**
00181   * @}
00182   */
00183
00184 /* Exported macro ------------------------------------------------------------*/
00185 /** @defgroup GPIO_Exported_Macros GPIO Exported Macros
00186   * @{
00187   */
00188
00189 /**
00190   * @brief  Checks whether the specified EXTI line flag is set or not.
00191   * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
00192   *         This parameter can be GPIO_PIN_x where x can be(0..15)
00193   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00194   */
00195 #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__))
00196
00197 /**
00198   * @brief  Clears the EXTI's line pending flags.
00199   * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
00200   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00201   * @retval None
00202   */
00203 #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__))
00204
00205 /**
00206   * @brief  Checks whether the specified EXTI line is asserted or not.
00207   * @param  __EXTI_LINE__: specifies the EXTI line to check.
00208   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00209   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00210   */
00211 #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__))
00212
00213 /**
00214   * @brief  Clears the EXTI's line pending bits.
00215   * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
00216   *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00217   * @retval None
00218   */
00219 #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__))
00220
00221 /**
00222   * @brief  Generates a Software interrupt on selected EXTI line.
00223   * @param  __EXTI_LINE__: specifies the EXTI line to check.
00224   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00225   * @retval None
00226   */
00227 #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
00228 /**
00229   * @}
00230   */
00231
00232 /* Include GPIO HAL Extension module */
00233 #include "stm32h7xx_hal_gpio_ex.h"
00234
00235 /* Exported functions --------------------------------------------------------*/
00236 /** @addtogroup GPIO_Exported_Functions
00237   * @{
00238   */
00239
00240 /** @addtogroup GPIO_Exported_Functions_Group1
00241   * @{
00242   */
00243 /* Initialization and de-initialization functions *****************************/
00244 void  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
00245 void  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
00246 /**
00247   * @}
00248   */
00249
00250 /** @addtogroup GPIO_Exported_Functions_Group2
00251   * @{
00252   */
00253 /* IO operation functions *****************************************************/
00254 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00255 void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
00256 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00257 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00258 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
00259 void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
00260
00261 /**
00262   * @}
00263   */
00264
00265 /**
00266   * @}
00267   */
00268 /* Private types -------------------------------------------------------------*/
00269 /* Private variables ---------------------------------------------------------*/
00270 /* Private constants ---------------------------------------------------------*/
00271 /** @defgroup GPIO_Private_Constants GPIO Private Constants
00272   * @{
00273   */
00274
00275 /**
00276   * @}
00277   */
00278
00279 /* Private macros ------------------------------------------------------------*/
00280 /** @defgroup GPIO_Private_Macros GPIO Private Macros
00281   * @{
00282   */
00283 #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
00284 #define IS_GPIO_PIN(__PIN__)           ((((__PIN__) & GPIO_PIN_MASK ) != (uint32_t)0x00))
00285 #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
00286                             ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
00287                             ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
00288                             ((MODE) == GPIO_MODE_AF_PP)              ||\
00289                             ((MODE) == GPIO_MODE_AF_OD)              ||\
00290                             ((MODE) == GPIO_MODE_IT_RISING)          ||\
00291                             ((MODE) == GPIO_MODE_IT_FALLING)         ||\
00292                             ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
00293                             ((MODE) == GPIO_MODE_EVT_RISING)         ||\
00294                             ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
00295                             ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
00296                             ((MODE) == GPIO_MODE_ANALOG))
00297 #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW)  || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
00298                               ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
00299
00300 #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
00301                             ((PULL) == GPIO_PULLDOWN))
00302 /**
00303   * @}
00304   */
00305
00306 /* Private functions ---------------------------------------------------------*/
00307 /** @defgroup GPIO_Private_Functions GPIO Private Functions
00308   * @{
00309   */
00310
00311 /**
00312   * @}
00313   */
00314
00315 /**
00316   * @}
00317   */
00318
00319 /**
00320   * @}
00321   */
00322
00323 #ifdef __cplusplus
00324 }
00325 #endif
00326
00327 #endif /* __STM32H7xx_HAL_GPIO_H */
00328
00329 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_gpio_ex.h Source File

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stm32h7xx_hal_gpio_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_gpio_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of GPIO HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_GPIO_EX_H
00040 #define __STM32H7xx_HAL_GPIO_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup GPIOEx GPIOEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /* Exported constants --------------------------------------------------------*/
00060 /** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
00061   * @{
00062   */
00063
00064 /** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
00065   * @{
00066   */
00067 /**
00068   * @brief   AF 0 selection
00069   */
00070 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
00071 #define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00072 #define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00073 #define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                          */
00074 #define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
00075
00076 /**
00077   * @brief   AF 1 selection
00078   */
00079 #define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
00080 #define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
00081 #define GPIO_AF1_TIM16         ((uint8_t)0x01)  /* TIM16 Alternate Function mapping */
00082 #define GPIO_AF1_TIM17         ((uint8_t)0x01)  /* TIM17 Alternate Function mapping */
00083 #define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
00084 #define GPIO_AF1_HRTIM1        ((uint8_t)0x01)  /* HRTIM1 Alternate Function mapping */
00085
00086 /**
00087   * @brief   AF 2 selection
00088   */
00089 #define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
00090 #define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
00091 #define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
00092 #define GPIO_AF2_TIM12         ((uint8_t)0x02)  /* TIM12 Alternate Function mapping */
00093 #define GPIO_AF2_HRTIM1        ((uint8_t)0x02)  /* HRTIM2 Alternate Function mapping */
00094 #define GPIO_AF2_SAI1          ((uint8_t)0x02)  /* SAI1 Alternate Function mapping */
00095
00096 /**
00097   * @brief   AF 3 selection
00098   */
00099 #define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping   */
00100 #define GPIO_AF3_LPTIM2        ((uint8_t)0x03)  /* LPTIM2 Alternate Function mapping */
00101 #define GPIO_AF3_DFSDM1        ((uint8_t)0x03)  /* DFSDM Alternate Function mapping  */
00102 #define GPIO_AF3_HRTIM1        ((uint8_t)0x03)  /* HRTIM3 Alternate Function mapping */
00103 #define GPIO_AF3_LPTIM3        ((uint8_t)0x03)  /* LPTIM3 Alternate Function mapping */
00104 #define GPIO_AF3_LPTIM4        ((uint8_t)0x03)  /* LPTIM4 Alternate Function mapping */
00105 #define GPIO_AF3_LPTIM5        ((uint8_t)0x03)  /* LPTIM5 Alternate Function mapping */
00106 #define GPIO_AF3_LPUART        ((uint8_t)0x03)  /* LPUART Alternate Function mapping */
00107
00108 /**
00109   * @brief   AF 4 selection
00110   */
00111 #define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */
00112 #define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */
00113 #define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */
00114 #define GPIO_AF4_I2C4          ((uint8_t)0x04)  /* I2C4 Alternate Function mapping   */
00115 #define GPIO_AF4_TIM15         ((uint8_t)0x04)  /* TIM15 Alternate Function mapping  */
00116 #define GPIO_AF4_CEC           ((uint8_t)0x04)  /* CEC Alternate Function mapping    */
00117 #define GPIO_AF4_LPTIM2        ((uint8_t)0x04)  /* LPTIM2 Alternate Function mapping */
00118 #define GPIO_AF4_USART1        ((uint8_t)0x04)  /* USART1 Alternate Function mapping */
00119 #define GPIO_AF4_DFSDM1        ((uint8_t)0x04)  /* DFSDM  Alternate Function mapping   */
00120
00121 /**
00122   * @brief   AF 5 selection
00123   */
00124 #define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */
00125 #define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */
00126 #define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3 Alternate Function mapping   */
00127 #define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping   */
00128 #define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping   */
00129 #define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping   */
00130 #define GPIO_AF5_CEC           ((uint8_t)0x05)  /* CEC  Alternate Function mapping   */
00131
00132
00133 /**
00134   * @brief   AF 6 selection
00135   */
00136 #define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* SPI2 Alternate Function mapping  */
00137 #define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping  */
00138 #define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping  */
00139 #define GPIO_AF6_SAI3          ((uint8_t)0x06)  /* SAI3 Alternate Function mapping  */
00140 #define GPIO_AF6_I2C4          ((uint8_t)0x06)  /* I2C4 Alternate Function mapping  */
00141 #define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM Alternate Function mapping */
00142 #define GPIO_AF6_UART4         ((uint8_t)0x06)  /* UART4 Alternate Function mapping */
00143
00144 /**
00145   * @brief   AF 7 selection
00146   */
00147 #define GPIO_AF7_SPI2          ((uint8_t)0x07)  /* SPI2 Alternate Function mapping   */
00148 #define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3 Alternate Function mapping   */
00149 #define GPIO_AF7_SPI6          ((uint8_t)0x07)  /* SPI6 Alternate Function mapping   */
00150 #define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping */
00151 #define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping */
00152 #define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping */
00153 #define GPIO_AF7_USART6        ((uint8_t)0x07)  /* USART6 Alternate Function mapping */
00154 #define GPIO_AF7_UART7         ((uint8_t)0x07)  /* UART7 Alternate Function mapping  */
00155 #define GPIO_AF7_DFSDM1        ((uint8_t)0x07)  /* DFSDM Alternate Function mapping  */
00156 #define GPIO_AF7_SDIO1         ((uint8_t)0x07)  /* SDIO1 Alternate Function mapping */
00157
00158 /**
00159   * @brief   AF 8 selection
00160   */
00161 #define GPIO_AF8_SPI6         ((uint8_t)0x08)  /* SPI6 Alternate Function mapping   */
00162 #define GPIO_AF8_SAI2         ((uint8_t)0x08)  /* SAI2 Alternate Function mapping   */
00163 #define GPIO_AF8_SAI4         ((uint8_t)0x08)  /* SAI4 Alternate Function mapping   */
00164 #define GPIO_AF8_UART4        ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
00165 #define GPIO_AF8_UART5        ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
00166 #define GPIO_AF8_UART8        ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
00167 #define GPIO_AF8_SPDIF        ((uint8_t)0x08)  /* SPDIF Alternate Function mapping  */
00168 #define GPIO_AF8_LPUART       ((uint8_t)0x08)  /* LPUART Alternate Function mapping */
00169 #define GPIO_AF8_SDIO1        ((uint8_t)0x08)  /* SDIO1 Alternate Function mapping */
00170
00171 /**
00172   * @brief   AF 9 selection
00173   */
00174 #define GPIO_AF9_FDCAN1        ((uint8_t)0x09)  /* FDCAN1 Alternate Function mapping    */
00175 #define GPIO_AF9_FDCAN2        ((uint8_t)0x09)  /* FDCAN2 Alternate Function mapping    */
00176 #define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping   */
00177 #define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping   */
00178 #define GPIO_AF9_QUADSPI       ((uint8_t)0x09)  /* QUADSPI Alternate Function mapping   */
00179 #define GPIO_AF9_SDIO2         ((uint8_t)0x09)  /* SDIO2 Alternate Function mapping   */
00180 #define GPIO_AF9_LTDC           ((uint8_t)0x09)  /* LTDC Alternate Function mapping   */
00181 #define GPIO_AF9_SPDIF         ((uint8_t)0x09)  /* SPDIF Alternate Function mapping   */
00182 #define GPIO_AF9_FMC           ((uint8_t)0x09)  /* FMC Alternate Function mapping     */
00183 #define GPIO_AF9_SAI4          ((uint8_t)0x09)  /* SAI4 Alternate Function mapping   */
00184
00185 /**
00186   * @brief   AF 10 selection
00187   */
00188 #define GPIO_AF10_QUADSPI       ((uint8_t)0xA)  /* QUADSPI Alternate Function mapping */
00189 #define GPIO_AF10_SAI2          ((uint8_t)0xA)  /* SAI2 Alternate Function mapping */
00190 #define GPIO_AF10_SAI4          ((uint8_t)0xA)  /* SAI4 Alternate Function mapping */
00191 #define GPIO_AF10_SDIO2         ((uint8_t)0xA)  /* SDIO2 Alternate Function mapping */
00192 #define GPIO_AF10_OTG2_HS       ((uint8_t)0xA)  /* OTG2_HS Alternate Function mapping */
00193 #define GPIO_AF10_OTG1_FS       ((uint8_t)0xA)  /* OTG1_FS Alternate Function mapping */
00194 #define GPIO_AF10_COMP1         ((uint8_t)0xA)  /* COMP1 Alternate Function mapping */
00195 #define GPIO_AF10_COMP2         ((uint8_t)0xA)  /* COMP2 Alternate Function mapping */
00196 #define GPIO_AF10_LTDC          ((uint8_t)0xA)  /* LTDC Alternate Function mapping   */
00197
00198 /**
00199   * @brief   AF 11 selection
00200   */
00201 #define GPIO_AF11_SWP           ((uint8_t)0x0B)  /* SWP Alternate Function mapping */
00202 #define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETH Alternate Function mapping */
00203 #define GPIO_AF11_MDIOS         ((uint8_t)0x0B)   /* MDIOS Alternate Function mapping   */
00204 #define GPIO_AF11_OTG1_HS       ((uint8_t)0x0B)  /* OTG1_HS Alternate Function mapping */
00205 #define GPIO_AF11_UART7         ((uint8_t)0x0B)  /* UART7 Alternate Function mapping */
00206 #define GPIO_AF11_SDIO2         ((uint8_t)0x0B)  /* SDIO2 Alternate Function mapping */
00207 #define GPIO_AF11_DFSDM1        ((uint8_t)0x0B)  /* DFSDM  Alternate Function mapping   */
00208 #define GPIO_AF11_COMP1         ((uint8_t)0x0B)  /* COMP1 Alternate Function mapping */
00209 #define GPIO_AF11_COMP2         ((uint8_t)0x0B)  /* COMP2 Alternate Function mapping */
00210 #define GPIO_AF11_I2C4          ((uint8_t)0x0B)  /* I2C4 Alternate Function mapping  */
00211
00212 /**
00213   * @brief   AF 12 selection
00214   */
00215 #define GPIO_AF12_FMC           ((uint8_t)0xC)  /* FMC Alternate Function mapping     */
00216 #define GPIO_AF12_SDIO1         ((uint8_t)0xC)  /* SDIO1 Alternate Function mapping  */
00217 #define GPIO_AF12_MDIOS         ((uint8_t)0xC)  /* MDIOS Alternate Function mapping   */
00218 #define GPIO_AF12_OTG2_FS       ((uint8_t)0xC)  /* OTG2_FS Alternate Function mapping   */
00219 #define GPIO_AF12_COMP1         ((uint8_t)0xC)  /* COMP1 Alternate Function mapping */
00220 #define GPIO_AF12_COMP2         ((uint8_t)0xC)  /* COMP2 Alternate Function mapping */
00221 #define GPIO_AF12_LTDC          ((uint8_t)0xC)  /* LTDC Alternate Function mapping   */
00222
00223 /**
00224   * @brief   AF 13 selection
00225   */
00226 #define GPIO_AF13_DCMI          ((uint8_t)0x0D)   /* DCMI Alternate Function mapping */
00227 #define GPIO_AF13_DSI           ((uint8_t)0x0D)   /* DSI Alternate Function mapping */
00228 #define GPIO_AF13_COMP1         ((uint8_t)0x0D)   /* COMP1 Alternate Function mapping */
00229 #define GPIO_AF13_COMP2         ((uint8_t)0x0D)   /* COMP2 Alternate Function mapping */
00230 #define GPIO_AF13_LTDC          ((uint8_t)0x0D)   /* LTDC Alternate Function mapping   */
00231
00232 /**
00233   * @brief   AF 14 selection
00234   */
00235 #define GPIO_AF14_LTDC         ((uint8_t)0x0E)   /* LTDC Alternate Function mapping   */
00236 #define GPIO_AF14_UART5        ((uint8_t)0x0E)   /* UART5 Alternate Function mapping */
00237
00238 /**
00239   * @brief   AF 15 selection
00240   */
00241 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
00242
00243 #define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
00244
00245
00246
00247 /**
00248   * @}
00249   */
00250
00251 /**
00252   * @}
00253   */
00254
00255 /* Exported macro ------------------------------------------------------------*/
00256 /** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
00257   * @{
00258   */
00259 /**
00260   * @}
00261   */
00262
00263 /* Exported functions --------------------------------------------------------*/
00264 /** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
00265   * @{
00266   */
00267 /**
00268   * @}
00269   */
00270 /* Private types -------------------------------------------------------------*/
00271 /* Private variables ---------------------------------------------------------*/
00272 /* Private constants ---------------------------------------------------------*/
00273 /** @defgroup GPIOEx_Private_Constants GPIO Private Constants
00274   * @{
00275   */
00276
00277 /**
00278   * @brief   GPIO pin available on the platform
00279   */
00280 /* Defines the available pins per GPIOs */
00281 #define GPIOA_PIN_AVAILABLE  GPIO_PIN_All
00282 #define GPIOB_PIN_AVAILABLE  GPIO_PIN_All
00283 #define GPIOC_PIN_AVAILABLE  GPIO_PIN_All
00284 #define GPIOD_PIN_AVAILABLE  GPIO_PIN_All
00285 #define GPIOE_PIN_AVAILABLE  GPIO_PIN_All
00286 #define GPIOF_PIN_AVAILABLE  GPIO_PIN_All
00287 #define GPIOG_PIN_AVAILABLE  GPIO_PIN_All
00288 #define GPIOI_PIN_AVAILABLE  GPIO_PIN_All
00289 #define GPIOJ_PIN_AVAILABLE  GPIO_PIN_All
00290 #define GPIOH_PIN_AVAILABLE  GPIO_PIN_All
00291 #define GPIOK_PIN_AVAILABLE  (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \
00292                               GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
00293
00294 /**
00295   * @}
00296   */
00297
00298 /* Private macros ------------------------------------------------------------*/
00299 /** @defgroup GPIOEx_Private_Macros GPIO Private Macros
00300   * @{
00301   */
00302 /** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
00303   * @{
00304   */
00305 #define GPIO_GET_INDEX(__GPIOx__)   (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
00306                                               ((__GPIOx__) == (GPIOB))? 1U :\
00307                                               ((__GPIOx__) == (GPIOC))? 2U :\
00308                                               ((__GPIOx__) == (GPIOD))? 3U :\
00309                                               ((__GPIOx__) == (GPIOE))? 4U :\
00310                                               ((__GPIOx__) == (GPIOF))? 5U :\
00311                                               ((__GPIOx__) == (GPIOG))? 6U :\
00312                                               ((__GPIOx__) == (GPIOH))? 7U :\
00313                                               ((__GPIOx__) == (GPIOI))? 8U :\
00314                                               ((__GPIOx__) == (GPIOJ))? 9U : 10U)
00315 /**
00316   * @}
00317   */
00318
00319 #define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__)  \
00320            ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
00321             (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \
00322             (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \
00323             (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \
00324             (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \
00325             (((__INSTANCE__) == GPIOF) && (((__PIN__) & (GPIOF_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOF_PIN_AVAILABLE)) == (GPIOF_PIN_AVAILABLE))) || \
00326             (((__INSTANCE__) == GPIOG) && (((__PIN__) & (GPIOG_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOG_PIN_AVAILABLE)) == (GPIOG_PIN_AVAILABLE))) || \
00327             (((__INSTANCE__) == GPIOI) && (((__PIN__) & (GPIOI_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOI_PIN_AVAILABLE)) == (GPIOI_PIN_AVAILABLE))) || \
00328             (((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || \
00329             (((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || \
00330             (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))
00331 /** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
00332   * @{
00333   */
00334 /**
00335   * @}
00336   */
00337
00338 /**
00339   * @}
00340   */
00341
00342 /* Private functions ---------------------------------------------------------*/
00343 /** @defgroup GPIOEx_Private_Functions GPIO Private Functions
00344   * @{
00345   */
00346
00347 /**
00348   * @}
00349   */
00350
00351 /**
00352   * @}
00353   */
00354
00355 /**
00356   * @}
00357   */
00358
00359 #ifdef __cplusplus
00360 }
00361 #endif
00362
00363 #endif /* __STM32H7xx_HAL_GPIO_EX_H */
00364
00365 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_hash.c Source File

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stm32h7xx_hal_hash.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32H7xx_hal_hash.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   HASH HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the HASH peripheral:
00010   *           + Initialization and de-initialization methods
00011   *           + HASH or HMAC processing in polling mode
00012   *           + HASH or HMAC processing in interrupt mode
00013   *           + HASH or HMAC processing in DMA mode
00014   *           + Peripheral State methods
00015   *           + HASH or HMAC processing suspension/resumption
00016   *
00017   @verbatim
00018  ===============================================================================
00019                      ##### How to use this driver #####
00020  ===============================================================================
00021     [..]
00022     The HASH HAL driver can be used as follows:
00023
00024     (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
00025         (##) Enable the HASH interface clock using __HASH_CLK_ENABLE()
00026         (##) When resorting to interrupt-based APIs (e.g. HAL_HASH_xxx_Start_IT())
00027             (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
00028             (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
00029             (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler() API
00030         (##) When resorting to DMA-based APIs  (e.g. HAL_HASH_xxx_Start_DMA())
00031             (+++) Enable the DMAx interface clock using
00032                    __DMAx_CLK_ENABLE()
00033             (+++) Configure and enable one DMA stream to manage data transfer from
00034                 memory to peripheral (input stream). Managing data transfer from
00035                 peripheral to memory can be performed only using CPU.
00036             (+++) Associate the initialized DMA handle to the HASH DMA handle
00037                 using  __HAL_LINKDMA()
00038             (+++) Configure the priority and enable the NVIC for the transfer complete
00039                 interrupt on the DMA Stream: use
00040                  HAL_NVIC_SetPriority() and
00041                  HAL_NVIC_EnableIRQ()
00042
00043     (#)Initialize the HASH HAL using HAL_HASH_Init(). This function:
00044         (##) resorts to HAL_HASH_MspInit() for low-level initialization,
00045         (##) configures the data type: 1-bit, 8-bit, 16-bit or 32-bit.
00046
00047     (#)Three processing schemes are available:
00048         (##) Polling mode: processing APIs are blocking functions
00049              i.e. they process the data and wait till the digest computation is finished,
00050              e.g. HAL_HASH_xxx_Start() for HASH or HAL_HMAC_xxx_Start() for HMAC
00051         (##) Interrupt mode: processing APIs are not blocking functions
00052                 i.e. they process the data under interrupt,
00053                 e.g. HAL_HASH_xxx_Start_IT() for HASH or HAL_HMAC_xxx_Start_IT() for HMAC
00054         (##) DMA mode: processing APIs are not blocking functions and the CPU is
00055              not used for data transfer i.e. the data transfer is ensured by DMA,
00056                 e.g. HAL_HASH_xxx_Start_DMA() for HASH or HAL_HMAC_xxx_Start_DMA()
00057                 for HMAC. Note that in DMA mode, a call to HAL_HASH_xxx_Finish()
00058                 is then required to retrieve the digest.
00059
00060     (#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is
00061        initialized and processes the buffer fed in input. When the input data have all been
00062        fed to the IP, the digest computation can start.
00063
00064     (#)Multi-buffer processing is possible in polling and DMA mode.
00065         (##) In polling mode, only multi-buffer HASH processing is possible.
00066              API HAL_HASH_xxx_Accumulate() must be called for each input buffer, except for the last one.
00067              User must resort to HAL_HASH_xxx_Start() to enter the last one and retrieve as
00068              well the computed digest.
00069
00070         (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
00071
00072               (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
00073              From that point, each buffer can be fed to the IP thru HAL_HASH_xxx_Start_DMA() API.
00074              Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
00075              macro then wrap-up the HASH processing in feeding the last input buffer thru the
00076              same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to
00077              API HAL_HASH_xxx_Finish().
00078
00079              (+++) HMAC processing (requires to resort to extended functions):
00080              after initialization, the key and the first input buffer are entered
00081              in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
00082              starts step 2.
00083              The following buffers are next entered with the API  HAL_HMACEx_xxx_Step2_DMA(). At this
00084              point, the HMAC processing is still carrying out step 2.
00085              Then, step 2 for the last input buffer and step 3 are carried out by a single call
00086              to HAL_HMACEx_xxx_Step2_3_DMA().
00087
00088              The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish().
00089
00090
00091     (#)Context swapping.
00092         (##) Two APIs are available to suspend HASH or HMAC processing:
00093              (+++) HAL_HASH_SwFeed_ProcessSuspend() when data are entered by software (polling or IT mode),
00094              (+++) HAL_HASH_DMAFeed_ProcessSuspend() when data are entered by DMA.
00095
00096         (##) When HASH or HMAC processing is suspended, HAL_HASH_ContextSaving() allows
00097             to save in memory the IP context. This context can be restored afterwards
00098             to resume the HASH processing thanks to HAL_HASH_ContextRestoring().
00099
00100         (##) Once the HASH IP has been restored to the same configuration as that at suspension
00101              time, processing can be restarted with the same API call (same API, same handle,
00102              same parameters) as done before the suspension. Relevant parameters to restart at
00103              the proper location are internally saved in the HASH handle.
00104
00105     (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
00106
00107   @endverbatim
00108   ******************************************************************************
00109   * @attention
00110   *
00111   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00112   *
00113   * Redistribution and use in source and binary forms, with or without modification,
00114   * are permitted provided that the following conditions are met:
00115   *   1. Redistributions of source code must retain the above copyright notice,
00116   *      this list of conditions and the following disclaimer.
00117   *   2. Redistributions in binary form must reproduce the above copyright notice,
00118   *      this list of conditions and the following disclaimer in the documentation
00119   *      and/or other materials provided with the distribution.
00120   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00121   *      may be used to endorse or promote products derived from this software
00122   *      without specific prior written permission.
00123   *
00124   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00125   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00126   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00127   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00128   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00129   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00130   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00131   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00132   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00133   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00134   *
00135   ******************************************************************************
00136   */
00137
00138 /* Includes ------------------------------------------------------------------*/
00139 #include "stm32h7xx_hal.h"
00140
00141 /** @addtogroup STM32H7xx_HAL_Driver
00142   * @{
00143   */
00144
00145 #if defined (HASH)
00146
00147 /** @defgroup HASH  HASH
00148   * @brief HASH HAL module driver.
00149   * @{
00150   */
00151
00152 #ifdef HAL_HASH_MODULE_ENABLED
00153
00154 /* Private typedef -----------------------------------------------------------*/
00155 /* Private define ------------------------------------------------------------*/
00156 /** @defgroup HASH_Private_Constants HASH Private Constants
00157   * @{
00158   */
00159
00160 /** @defgroup HASH_Digest_Calculation_Status HASH Digest Calculation Status
00161   * @{
00162   */
00163 #define HASH_DIGEST_CALCULATION_NOT_STARTED       ((uint32_t)0x00000000) /*!< DCAL not set after input data written in DIN register */
00164 #define HASH_DIGEST_CALCULATION_STARTED           ((uint32_t)0x00000001) /*!< DCAL set after input data written in DIN register     */
00165 /**
00166   * @}
00167   */
00168
00169 /** @defgroup HASH_Number_Of_CSR_Registers HASH Number of Context Swap Registers
00170   * @{
00171   */
00172 #define HASH_NUMBER_OF_CSR_REGISTERS              54     /*!< Number of Context Swap Registers */
00173 /**
00174   * @}
00175   */
00176
00177 /** @defgroup HASH_TimeOut_Value HASH TimeOut Value
00178   * @{
00179   */
00180 #define HASH_TIMEOUTVALUE                         1000   /*!< Time-out value  */
00181 /**
00182   * @}
00183   */
00184
00185 /**
00186   * @}
00187   */
00188
00189 /* Private macro -------------------------------------------------------------*/
00190 /* Private variables ---------------------------------------------------------*/
00191 /* Private function prototypes -----------------------------------------------*/
00192 /** @defgroup HASH_Private_Functions HASH Private Functions
00193   * @{
00194   */
00195 static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
00196 static void HASH_DMAError(DMA_HandleTypeDef *hdma);
00197 static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
00198 static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
00199 static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00200 static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash);
00201 static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash);
00202 static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout);
00203 /**
00204   * @}
00205   */
00206
00207 /** @defgroup HASH_Exported_Functions HASH Exported Functions
00208   * @{
00209   */
00210
00211 /** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
00212  *  @brief    HASH Initialization, configuration and call-back functions.
00213  *
00214 @verbatim
00215  ===============================================================================
00216               ##### Initialization and de-initialization functions #####
00217  ===============================================================================
00218     [..]  This section provides functions allowing to:
00219       (+) Initialize the HASH according to the specified parameters
00220           in the HASH_InitTypeDef and create the associated handle
00221       (+) DeInitialize the HASH peripheral
00222       (+) Initialize the HASH MCU Specific Package (MSP)
00223       (+) DeInitialize the HASH MSP
00224
00225     [..]  This section provides as well call back functions definitions for user
00226           code to manage:
00227       (+) Input data transfer to IP completion
00228       (+) Calculated digest retrieval completion
00229       (+) Error management
00230
00231
00232
00233 @endverbatim
00234   * @{
00235   */
00236
00237 /**
00238   * @brief  Initialize the HASH according to the specified parameters in the
00239             HASH_HandleTypeDef and create the associated handle.
00240   * @note   Only MDMAT and DATATYPE bits of HASH IP are set by HAL_HASH_Init(),
00241   *         other configuration bits are set by HASH or HMAC processing APIs.
00242   * @note   MDMAT bit is systematically reset by HAL_HASH_Init(). To set it for
00243   *         multi-buffer HASH processing, user needs to resort to
00244   *         __HAL_HASH_SET_MDMAT() macro. For HMAC multi-buffer processing, the
00245   *         relevant APIs manage themselves the MDMAT bit.
00246   * @param  hhash: HASH handle
00247   * @retval HAL status
00248   */
00249 HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
00250 {
00251   /* Check the hash handle allocation */
00252   if(hhash == NULL)
00253   {
00254     return HAL_ERROR;
00255   }
00256
00257   /* Check the parameters */
00258   assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
00259
00260   if(hhash->State == HAL_HASH_STATE_RESET)
00261   {
00262     /* Allocate lock resource and initialize it */
00263     hhash->Lock = HAL_UNLOCKED;
00264
00265     /* Init the low level hardware */
00266     HAL_HASH_MspInit(hhash);
00267   }
00268
00269     /* Change the HASH state */
00270   hhash->State = HAL_HASH_STATE_BUSY;
00271
00272   /* Reset HashInCount, HashITCounter and HashBuffSize */
00273   hhash->HashInCount = 0;
00274   hhash->HashBuffSize = 0;
00275   hhash->HashITCounter = 0;
00276   /* Reset digest calculation bridle (MDMAT bit control) */
00277   hhash->DigestCalculationDisable = RESET;
00278   /* Set phase to READY */
00279   hhash->Phase = HAL_HASH_PHASE_READY;
00280
00281   /* Set the data type and reset MDMAT bit */
00282   MODIFY_REG(HASH->CR, HASH_CR_DATATYPE|HASH_CR_MDMAT, hhash->Init.DataType);
00283
00284   /* Reset HASH handle status */
00285   hhash->Status = HAL_OK;
00286
00287   /* Set the HASH state to Ready */
00288   hhash->State = HAL_HASH_STATE_READY;
00289
00290   /* Return function status */
00291   return HAL_OK;
00292 }
00293
00294 /**
00295   * @brief  DeInitialize the HASH peripheral.
00296   * @param  hhash: HASH handle.
00297   * @retval HAL status
00298   */
00299 HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
00300 {
00301   /* Check the HASH handle allocation */
00302   if(hhash == NULL)
00303   {
00304     return HAL_ERROR;
00305   }
00306
00307   /* Change the HASH state */
00308   hhash->State = HAL_HASH_STATE_BUSY;
00309
00310   /* Set the default HASH phase */
00311   hhash->Phase = HAL_HASH_PHASE_READY;
00312
00313   /* Reset HashInCount, HashITCounter and HashBuffSize */
00314   hhash->HashInCount = 0;
00315   hhash->HashBuffSize = 0;
00316   hhash->HashITCounter = 0;
00317   /* Reset digest calculation bridle (MDMAT bit control) */
00318   hhash->DigestCalculationDisable = RESET;
00319
00320   /* DeInit the low level hardware: CLOCK, NVIC.*/
00321   HAL_HASH_MspDeInit(hhash);
00322
00323   /* Reset HASH handle status */
00324   hhash->Status = HAL_OK;
00325
00326   /* Set the HASH state to Ready */
00327   hhash->State = HAL_HASH_STATE_RESET;
00328
00329   /* Return function status */
00330   return HAL_OK;
00331 }
00332
00333 /**
00334   * @brief  Initialize the HASH MSP.
00335   * @param  hhash: HASH handle.
00336   * @retval None
00337   */
00338 __weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
00339 {
00340   /* Prevent unused argument(s) compilation warning */
00341   UNUSED(hhash);
00342
00343   /* NOTE : This function should not be modified; when the callback is needed,
00344             HAL_HASH_MspInit() can be implemented in the user file.
00345    */
00346 }
00347
00348 /**
00349   * @brief  DeInitialize the HASH MSP.
00350   * @param  hhash: HASH handle.
00351   * @retval None
00352   */
00353 __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
00354 {
00355   /* Prevent unused argument(s) compilation warning */
00356   UNUSED(hhash);
00357
00358   /* NOTE : This function should not be modified; when the callback is needed,
00359             HAL_HASH_MspDeInit() can be implemented in the user file.
00360    */
00361 }
00362
00363 /**
00364   * @brief  Input data transfer complete call back.
00365   * @note   HAL_HASH_InCpltCallback() is called when the complete input message
00366   *         has been fed to the IP. This API is invoked only when input data are
00367   *         entered under interruption or thru DMA.
00368   * @note   In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set),
00369   *         HAL_HASH_InCpltCallback() is called at the end of each buffer feeding
00370   *         to the IP.
00371   * @param  hhash: HASH handle.
00372   * @retval None
00373   */
00374 __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
00375 {
00376   /* Prevent unused argument(s) compilation warning */
00377   UNUSED(hhash);
00378
00379   /* NOTE : This function should not be modified; when the callback is needed,
00380             HAL_HASH_InCpltCallback() can be implemented in the user file.
00381    */
00382 }
00383
00384 /**
00385   * @brief  Digest computation complete call back.
00386   * @note   HAL_HASH_DgstCpltCallback() is used under interruption, is not
00387   *         relevant with DMA.
00388   * @param  hhash: HASH handle.
00389   * @retval None
00390   */
00391 __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
00392 {
00393   /* Prevent unused argument(s) compilation warning */
00394   UNUSED(hhash);
00395
00396   /* NOTE : This function should not be modified; when the callback is needed,
00397             HAL_HASH_DgstCpltCallback() can be implemented in the user file.
00398    */
00399 }
00400
00401 /**
00402   * @brief  Error callback.
00403   * @note   Code user can resort to hhash->Status (HAL_ERROR, HAL_TIMEOUT,...)
00404   *         to retrieve the error type.
00405   * @param  hhash: HASH handle.
00406   * @retval None
00407   */
00408 __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
00409 {
00410   /* Prevent unused argument(s) compilation warning */
00411   UNUSED(hhash);
00412
00413   /* NOTE : This function should not be modified; when the callback is needed,
00414             HAL_HASH_ErrorCallback() can be implemented in the user file.
00415    */
00416 }
00417
00418
00419 /**
00420   * @}
00421   */
00422
00423 /** @defgroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
00424  *  @brief   HASH processing functions using polling mode.
00425  *
00426 @verbatim
00427  ===============================================================================
00428                  ##### Polling mode HASH processing functions #####
00429  ===============================================================================
00430     [..]  This section provides functions allowing to calculate in polling mode
00431           the hash value using one of the following algorithms:
00432       (+) MD5
00433          (++) HAL_HASH_MD5_Start()
00434          (++) HAL_HASH_MD5_Accumulate()
00435       (+) SHA1
00436          (++) HAL_HASH_SHA1_Start()
00437          (++) HAL_HASH_SHA1_Accumulate()
00438
00439     [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
00440
00441     [..]  In case of multi-buffer HASH processing (a single digest is computed while
00442           several buffers are fed to the IP), the user can resort to successive calls
00443           to HAL_HASH_xxx_Accumulate() and wrap-up the digest computation by a call
00444           to HAL_HASH_xxx_Start().
00445
00446 @endverbatim
00447   * @{
00448   */
00449
00450 /**
00451   * @brief  Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
00452   *         read the computed digest.
00453   * @note   Digest is available in pOutBuffer.
00454   * @param  hhash: HASH handle.
00455   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00456   * @param  Size: length of the input buffer in bytes.
00457   * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
00458   * @param  Timeout: Timeout value
00459   * @retval HAL status
00460   */
00461 HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00462 {
00463   return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
00464 }
00465
00466 /**
00467   * @brief  If not already done, initialize the HASH peripheral in MD5 mode then
00468   *         processes pInBuffer.
00469   * @note   Consecutive calls to HAL_HASH_MD5_Accumulate() can be used to feed
00470   *         several input buffers back-to-back to the IP that will yield a single
00471   *         HASH signature once all buffers have been entered. Wrap-up of input
00472   *         buffers feeding and retrieval of digest is done by a call to
00473   *         HAL_HASH_MD5_Start().
00474   * @note   Field hhash->Phase of HASH handle is tested to check whether or not
00475   *         the IP has already been initialized.
00476   * @note   Digest is not retrieved by this API, user must resort to HAL_HASH_MD5_Start()
00477   *         to read it, feeding at the same time the last input buffer to the IP.
00478   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00479   *         HASH digest computation is corrupted. Only HAL_HASH_MD5_Start() is able
00480   *         to manage the ending buffer with a length in bytes not a multiple of 4.
00481   * @param  hhash: HASH handle.
00482   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00483   * @param  Size: length of the input buffer in bytes, must be a multiple of 4.
00484   * @retval HAL status
00485   */
00486 HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00487 {
00488   return  HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5);
00489 }
00490
00491 /**
00492   * @brief  Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
00493   *         read the computed digest.
00494   * @note   Digest is available in pOutBuffer.
00495   * @param  hhash: HASH handle.
00496   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00497   * @param  Size: length of the input buffer in bytes.
00498   * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
00499   * @param  Timeout: Timeout value
00500   * @retval HAL status
00501   */
00502 HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00503 {
00504   return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
00505 }
00506
00507 /**
00508   * @brief  If not already done, initialize the HASH peripheral in SHA1 mode then
00509   *         processes pInBuffer.
00510   * @note   Consecutive calls to HAL_HASH_SHA1_Accumulate() can be used to feed
00511   *         several input buffers back-to-back to the IP that will yield a single
00512   *         HASH signature once all buffers have been entered. Wrap-up of input
00513   *         buffers feeding and retrieval of digest is done by a call to
00514   *         HAL_HASH_SHA1_Start().
00515   * @note   Field hhash->Phase of HASH handle is tested to check whether or not
00516   *         the IP has already been initialized.
00517   * @note   Digest is not retrieved by this API, user must resort to HAL_HASH_SHA1_Start()
00518   *         to read it, feeding at the same time the last input buffer to the IP.
00519   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00520   *         HASH digest computation is corrupted. Only HAL_HASH_SHA1_Start() is able
00521   *         to manage the ending buffer with a length in bytes not a multiple of 4.
00522   * @param  hhash: HASH handle.
00523   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00524   * @param  Size: length of the input buffer in bytes, must be a multiple of 4.
00525   * @retval HAL status
00526   */
00527 HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00528 {
00529   return  HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1);
00530 }
00531
00532
00533 /**
00534   * @}
00535   */
00536
00537 /** @defgroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
00538  *  @brief   HASH processing functions using interrupt mode.
00539  *
00540 @verbatim
00541  ===============================================================================
00542                  ##### Interruption mode HASH processing functions #####
00543  ===============================================================================
00544     [..]  This section provides functions allowing to calculate in interrupt mode
00545           the hash value using one of the following algorithms:
00546       (+) MD5
00547          (++) HAL_HASH_MD5_Start_IT()
00548       (+) SHA1
00549          (++) HAL_HASH_SHA1_Start_IT()
00550
00551     [..]  API HAL_HASH_IRQHandler() manages each HASH interruption.
00552
00553     [..] Note that HAL_HASH_IRQHandler() manages as well HASH IP interruptions when in
00554          HMAC processing mode.
00555
00556
00557 @endverbatim
00558   * @{
00559   */
00560
00561 /**
00562   * @brief  Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
00563   *         read the computed digest in interruption mode.
00564   * @note   Digest is available in pOutBuffer.
00565   * @param  hhash: HASH handle.
00566   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00567   * @param  Size: length of the input buffer in bytes.
00568   * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
00569   * @retval HAL status
00570   */
00571 HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
00572 {
00573   return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5);
00574 }
00575
00576
00577 /**
00578   * @brief  Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
00579   *         read the computed digest in interruption mode.
00580   * @note   Digest is available in pOutBuffer.
00581   * @param  hhash: HASH handle.
00582   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00583   * @param  Size: length of the input buffer in bytes.
00584   * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
00585   * @retval HAL status
00586   */
00587 HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
00588 {
00589   return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1);
00590 }
00591
00592 /**
00593   * @brief Handle HASH interrupt request.
00594   * @param hhash: HASH handle.
00595   * @note  HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well.
00596   * @note  In case of error reported during the HASH interruption processing,
00597   *        HAL_HASH_ErrorCallback() API is called so that user code can
00598   *        manage the error. The error type is available in hhash->Status field.
00599   * @retval None
00600   */
00601 void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
00602 {
00603   hhash->Status = HASH_IT(hhash);
00604   if (hhash->Status != HAL_OK)
00605   {
00606     HAL_HASH_ErrorCallback(hhash);
00607     /* After error handling by code user, reset HASH handle HAL status */
00608     hhash->Status = HAL_OK;
00609   }
00610 }
00611
00612 /**
00613   * @}
00614   */
00615
00616 /** @defgroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
00617  *  @brief   HASH processing functions using DMA mode.
00618  *
00619 @verbatim
00620  ===============================================================================
00621                     ##### DMA mode HASH processing functions #####
00622  ===============================================================================
00623     [..]  This section provides functions allowing to calculate in DMA mode
00624           the hash value using one of the following algorithms:
00625       (+) MD5
00626          (++) HAL_HASH_MD5_Start_DMA()
00627          (++) HAL_HASH_MD5_Finish()
00628       (+) SHA1
00629          (++) HAL_HASH_SHA1_Start_DMA()
00630          (++) HAL_HASH_SHA1_Finish()
00631
00632     [..]  When resorting to DMA mode to enter the data in the IP, user must resort
00633           to  HAL_HASH_xxx_Start_DMA() then read the resulting digest with
00634           HAL_HASH_xxx_Finish().
00635
00636     [..]  In case of multi-buffer HASH processing, MDMAT bit must first be set before
00637           the successive calls to HAL_HASH_xxx_Start_DMA(). Then, MDMAT bit needs to be
00638           reset before the last call to HAL_HASH_xxx_Start_DMA(). Digest is finally
00639           retrieved thanks to HAL_HASH_xxx_Finish().
00640
00641
00642 @endverbatim
00643   * @{
00644   */
00645
00646 /**
00647   * @brief  Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer
00648   *         to feed the input buffer to the IP.
00649   * @note   Once the DMA transfer is finished, HAL_HASH_MD5_Finish() API must
00650   *         be called to retrieve the computed digest.
00651   * @param  hhash: HASH handle.
00652   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00653   * @param  Size: length of the input buffer in bytes.
00654   * @retval HAL status
00655   */
00656 HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00657 {
00658   return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
00659 }
00660
00661 /**
00662   * @brief  Return the computed digest in MD5 mode.
00663   * @note   The API waits for DCIS to be set then reads the computed digest.
00664   * @note   HAL_HASH_MD5_Finish() can be used as well to retrieve the digest in
00665   *         HMAC MD5 mode.
00666   * @param  hhash: HASH handle.
00667   * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
00668   * @param  Timeout: Timeout value.
00669   * @retval HAL status
00670   */
00671 HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
00672 {
00673    return HASH_Finish(hhash, pOutBuffer, Timeout);
00674 }
00675
00676 /**
00677   * @brief  Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer
00678   *         to feed the input buffer to the IP.
00679   * @note   Once the DMA transfer is finished, HAL_HASH_SHA1_Finish() API must
00680   *         be called to retrieve the computed digest.
00681   * @param  hhash: HASH handle.
00682   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00683   * @param  Size: length of the input buffer in bytes.
00684   * @retval HAL status
00685   */
00686 HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00687 {
00688   return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
00689 }
00690
00691
00692 /**
00693   * @brief  Return the computed digest in SHA1 mode.
00694   * @note   The API waits for DCIS to be set then reads the computed digest.
00695   * @note   HAL_HASH_SHA1_Finish() can be used as well to retrieve the digest in
00696   *         HMAC SHA1 mode.
00697   * @param  hhash: HASH handle.
00698   * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
00699   * @param  Timeout: Timeout value.
00700   * @retval HAL status
00701   */
00702 HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
00703 {
00704    return HASH_Finish(hhash, pOutBuffer, Timeout);
00705 }
00706
00707 /**
00708   * @}
00709   */
00710
00711 /** @defgroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
00712  *  @brief   HMAC processing functions using polling mode.
00713  *
00714 @verbatim
00715  ===============================================================================
00716                  ##### Polling mode HMAC processing functions #####
00717  ===============================================================================
00718     [..]  This section provides functions allowing to calculate in polling mode
00719           the HMAC value using one of the following algorithms:
00720       (+) MD5
00721          (++) HAL_HMAC_MD5_Start()
00722       (+) SHA1
00723          (++) HAL_HMAC_SHA1_Start()
00724
00725
00726 @endverbatim
00727   * @{
00728   */
00729
00730 /**
00731   * @brief  Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then
00732   *         read the computed digest.
00733   * @note   Digest is available in pOutBuffer.
00734   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00735   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00736   * @param  hhash: HASH handle.
00737   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00738   * @param  Size: length of the input buffer in bytes.
00739   * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
00740   * @param  Timeout: Timeout value.
00741   * @retval HAL status
00742   */
00743 HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00744 {
00745   return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
00746 }
00747
00748 /**
00749   * @brief  Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then
00750   *         read the computed digest.
00751   * @note   Digest is available in pOutBuffer.
00752   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00753   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00754   * @param  hhash: HASH handle.
00755   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00756   * @param  Size: length of the input buffer in bytes.
00757   * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
00758   * @param  Timeout: Timeout value.
00759   * @retval HAL status
00760   */
00761 HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00762 {
00763   return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
00764 }
00765
00766 /**
00767   * @}
00768   */
00769
00770
00771 /** @defgroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
00772  *  @brief   HMAC processing functions using interrupt mode.
00773  *
00774 @verbatim
00775  ===============================================================================
00776                  ##### Interrupt mode HMAC processing functions #####
00777  ===============================================================================
00778     [..]  This section provides functions allowing to calculate in interrupt mode
00779           the HMAC value using one of the following algorithms:
00780       (+) MD5
00781          (++) HAL_HMAC_MD5_Start_IT()
00782       (+) SHA1
00783          (++) HAL_HMAC_SHA1_Start_IT()
00784
00785 @endverbatim
00786   * @{
00787   */
00788
00789
00790 /**
00791   * @brief  Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then
00792   *         read the computed digest in interrupt mode.
00793   * @note   Digest is available in pOutBuffer.
00794   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00795   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00796   * @param  hhash: HASH handle.
00797   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00798   * @param  Size: length of the input buffer in bytes.
00799   * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
00800   * @retval HAL status
00801   */
00802 HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
00803 {
00804   return  HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
00805 }
00806
00807 /**
00808   * @brief  Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then
00809   *         read the computed digest in interrupt mode.
00810   * @note   Digest is available in pOutBuffer.
00811   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00812   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00813   * @param  hhash: HASH handle.
00814   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00815   * @param  Size: length of the input buffer in bytes.
00816   * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
00817   * @retval HAL status
00818   */
00819 HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
00820 {
00821   return  HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
00822 }
00823
00824 /**
00825   * @}
00826   */
00827
00828
00829
00830 /** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
00831  *  @brief   HMAC processing functions using DMA modes.
00832  *
00833 @verbatim
00834  ===============================================================================
00835                  ##### DMA mode HMAC processing functions #####
00836  ===============================================================================
00837     [..]  This section provides functions allowing to calculate in DMA mode
00838           the HMAC value using one of the following algorithms:
00839       (+) MD5
00840          (++) HAL_HMAC_MD5_Start_DMA()
00841       (+) SHA1
00842          (++) HAL_HMAC_SHA1_Start_DMA()
00843
00844     [..]  When resorting to DMA mode to enter the data in the IP for HMAC processing,
00845           user must resort to  HAL_HMAC_xxx_Start_DMA() then read the resulting digest
00846           with HAL_HASH_xxx_Finish().
00847
00848 @endverbatim
00849   * @{
00850   */
00851
00852
00853 /**
00854   * @brief  Initialize the HASH peripheral in HMAC MD5 mode then initiate the required
00855   *         DMA transfers to feed the key and the input buffer to the IP.
00856   * @note   Once the DMA transfers are finished (indicated by hhash->State set back
00857   *         to HAL_HASH_STATE_READY), HAL_HASH_MD5_Finish() API must be called to retrieve
00858   *         the computed digest.
00859   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00860   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00861   * @note   If MDMAT bit is set before calling this function (multi-buffer
00862   *          HASH processing case), the input buffer size (in bytes) must be
00863   *          a multiple of 4 otherwise, the HASH digest computation is corrupted.
00864   *          For the processing of the last buffer of the thread, MDMAT bit must
00865   *          be reset and the buffer length (in bytes) doesn't have to be a
00866   *          multiple of 4.
00867   * @param  hhash: HASH handle.
00868   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00869   * @param  Size: length of the input buffer in bytes.
00870   * @retval HAL status
00871   */
00872 HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00873 {
00874   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
00875 }
00876
00877
00878 /**
00879   * @brief  Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required
00880   *         DMA transfers to feed the key and the input buffer to the IP.
00881   * @note   Once the DMA transfers are finished (indicated by hhash->State set back
00882   *         to HAL_HASH_STATE_READY), HAL_HASH_SHA1_Finish() API must be called to retrieve
00883   *         the computed digest.
00884   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00885   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00886   * @note   If MDMAT bit is set before calling this function (multi-buffer
00887   *          HASH processing case), the input buffer size (in bytes) must be
00888   *          a multiple of 4 otherwise, the HASH digest computation is corrupted.
00889   *          For the processing of the last buffer of the thread, MDMAT bit must
00890   *          be reset and the buffer length (in bytes) doesn't have to be a
00891   *          multiple of 4.
00892   * @param  hhash: HASH handle.
00893   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00894   * @param  Size: length of the input buffer in bytes.
00895   * @retval HAL status
00896   */
00897 HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00898 {
00899   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
00900 }
00901
00902 /**
00903   * @}
00904   */
00905
00906 /** @defgroup HASH_Exported_Functions_Group8 Peripheral states functions
00907  *  @brief   Peripheral State functions.
00908  *
00909 @verbatim
00910  ===============================================================================
00911                       ##### Peripheral State methods #####
00912  ===============================================================================
00913     [..]
00914     This section permits to get in run-time the state and the peripheral handle
00915     status of the peripheral:
00916       (+) HAL_HASH_GetState()
00917       (+) HAL_HASH_GetStatus()
00918
00919     [..]
00920     Additionally, this subsection provides functions allowing to save and restore
00921     the HASH or HMAC processing context in case of calculation suspension:
00922       (+) HAL_HASH_ContextSaving()
00923       (+) HAL_HASH_ContextRestoring()
00924
00925     [..]
00926     This subsection provides functions allowing to suspend the HASH processing
00927       (+) when input are fed to the IP by software
00928           (++) HAL_HASH_SwFeed_ProcessSuspend()
00929       (+) when input are fed to the IP by DMA
00930           (++) HAL_HASH_DMAFeed_ProcessSuspend()
00931
00932
00933
00934 @endverbatim
00935   * @{
00936   */
00937
00938 /**
00939   * @brief  Return the HASH handle state.
00940   * @note   The API yields the current state of the handle (BUSY, READY,...).
00941   * @param  hhash: HASH handle.
00942   * @retval HAL HASH state
00943   */
00944 HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
00945 {
00946   return hhash->State;
00947 }
00948
00949
00950 /**
00951   * @brief Return the HASH HAL status.
00952   * @note  The API yields the HAL status of the handle: it is the result of the
00953   *        latest HASH processing and allows to report any issue (e.g. HAL_TIMEOUT).
00954   * @param  hhash: HASH handle.
00955   * @retval HAL status
00956   */
00957 HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash)
00958 {
00959   return hhash->Status;
00960 }
00961
00962 /**
00963   * @brief  Save the HASH context in case of processing suspension.
00964   * @param  hhash: HASH handle.
00965   * @param  pMemBuffer: pointer to the memory buffer where the HASH context
00966   *         is saved.
00967   * @note   The IMR, STR, CR then all the CSR registers are saved
00968   *         in that order. Only the r/w bits are read to be restored later on.
00969   * @note   By default, all the context swap registers (there are
00970   *         HASH_NUMBER_OF_CSR_REGISTERS of those) are saved.
00971   * @note   pMemBuffer points to a buffer allocated by the user. The buffer size
00972   *         must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long.
00973   * @retval None
00974   */
00975 void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
00976 {
00977   uint32_t mem_ptr = (uint32_t)pMemBuffer;
00978   uint32_t csr_ptr = (uint32_t)HASH->CSR;
00979   uint32_t i = 0;
00980
00981   /* Prevent unused argument(s) compilation warning */
00982   UNUSED(hhash);
00983
00984   /* Save IMR register content */
00985   *(uint32_t*)(mem_ptr) = READ_BIT(HASH->IMR,HASH_IT_DINI|HASH_IT_DCI);
00986   mem_ptr+=4;
00987   /* Save STR register content */
00988   *(uint32_t*)(mem_ptr) = READ_BIT(HASH->STR,HASH_STR_NBLW);
00989   mem_ptr+=4;
00990   /* Save CR register content */
00991   *(uint32_t*)(mem_ptr) = READ_BIT(HASH->CR,HASH_CR_DMAE|HASH_CR_DATATYPE|HASH_CR_MODE|HASH_CR_ALGO|HASH_CR_LKEY|HASH_CR_MDMAT);
00992   mem_ptr+=4;
00993   /* By default, save all CSRs registers */
00994   for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0; i--)
00995   {
00996     *(uint32_t*)(mem_ptr) = *(uint32_t*)(csr_ptr);
00997     mem_ptr+=4;
00998     csr_ptr+=4;
00999   }
01000 }
01001
01002
01003 /**
01004   * @brief  Restore the HASH context in case of processing resumption.
01005   * @param  hhash: HASH handle.
01006   * @param  pMemBuffer: pointer to the memory buffer where the HASH context
01007   *         is stored.
01008   * @note   The IMR, STR, CR then all the CSR registers are restored
01009   *         in that order. Only the r/w bits are restored.
01010   * @note   By default, all the context swap registers (HASH_NUMBER_OF_CSR_REGISTERS
01011   *         of those) are restored (all of them have been saved by default
01012   *         beforehand).
01013   * @retval None
01014   */
01015 void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
01016 {
01017   uint32_t mem_ptr = (uint32_t)pMemBuffer;
01018   uint32_t csr_ptr = (uint32_t)HASH->CSR;
01019   uint32_t i = 0;
01020
01021   /* Prevent unused argument(s) compilation warning */
01022   UNUSED(hhash);
01023
01024   /* Restore IMR register content */
01025   WRITE_REG(HASH->IMR, (*(uint32_t*)(mem_ptr)));
01026   mem_ptr+=4;
01027   /* Restore STR register content */
01028   WRITE_REG(HASH->STR, (*(uint32_t*)(mem_ptr)));
01029   mem_ptr+=4;
01030   /* Restore CR register content */
01031   WRITE_REG(HASH->CR, (*(uint32_t*)(mem_ptr)));
01032   mem_ptr+=4;
01033
01034   /* Reset the HASH processor before restoring the Context
01035   Swap Registers (CSR) */
01036   __HAL_HASH_INIT();
01037
01038   /* By default, restore all CSR registers */
01039   for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0; i--)
01040   {
01041     WRITE_REG((*(uint32_t*)(csr_ptr)), (*(uint32_t*)(mem_ptr)));
01042     mem_ptr+=4;
01043     csr_ptr+=4;
01044   }
01045 }
01046
01047
01048 /**
01049   * @brief  Initiate HASH processing suspension when in polling or interruption mode.
01050   * @param  hhash: HASH handle.
01051   * @note   Set the handle field SuspendRequest to the appropriate value so that
01052   *         the on-going HASH processing is suspended as soon as the required
01053   *         conditions are met. Note that the actual suspension is carried out
01054   *         by the functions HASH_WriteData() in polling mode and HASH_IT() in
01055   *         interruption mode.
01056   * @retval None
01057   */
01058 void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
01059 {
01060   /* Set Handle Suspend Request field */
01061   hhash->SuspendRequest = HAL_HASH_SUSPEND;
01062 }
01063
01064 /**
01065   * @brief  Suspend the HASH processing when in DMA mode.
01066   * @param  hhash: HASH handle.
01067   * @note   When suspension attempt occurs at the very end of a DMA transfer and
01068   *         all the data have already been entered in the IP, hhash->State is
01069   *         set to HAL_HASH_STATE_READY and the API returns HAL_ERROR. It is
01070   *         recommended to wrap-up the processing in reading the digest as usual.
01071   * @retval HAL status
01072   */
01073 HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
01074 {
01075   uint32_t tmp_remaining_DMATransferSize_inWords = 0x0;
01076   uint32_t tmp_initial_DMATransferSize_inWords = 0x0;
01077
01078   if (hhash->State == HAL_HASH_STATE_READY)
01079   {
01080     return HAL_ERROR;
01081   }
01082   else
01083   {
01084     /* Set State as suspended (it may be required to update it if suspension failed).
01085        The context saving operations must be carried out to be able to resume later on. */
01086     hhash->State = HAL_HASH_STATE_SUSPENDED;
01087
01088     /* Clear DMAE bit */
01089     CLEAR_BIT(HASH->CR,HASH_CR_DMAE);
01090
01091     /* Wait for DMAS to be reset */
01092     if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DMAS, SET, HASH_TIMEOUTVALUE) != HAL_OK)
01093     {
01094       return HAL_TIMEOUT;
01095     }
01096
01097     /* Disable DMA channel */
01098     HAL_DMA_Abort(hhash->hdmain);
01099
01100     /* At this point, DMA interface is disabled and no transfer is on-going */
01101     /* Retrieve from the DMA handle how many words remain to be written */
01102     tmp_remaining_DMATransferSize_inWords = ((DMA_Stream_TypeDef *)hhash->hdmain->Instance)->NDTR;
01103     if (tmp_remaining_DMATransferSize_inWords == 0)
01104     {
01105       /* All the DMA transfer is actually done. Suspension occurred at the very end
01106          of the transfer. Either the digest computation is about to start (HASH case)
01107          or processing is about to move from one step to another (HMAC case).
01108          In both cases, the processing can't be suspended at this point. It is
01109          safer to
01110          - retrieve the low priority block digest before starting the high
01111            priority block processing (HASH case)
01112          - re-attempt a new suspension (HMAC case)
01113          */
01114       hhash->State  = HAL_HASH_STATE_READY;
01115       return HAL_ERROR;
01116     }
01117     else
01118     {
01119
01120       if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
01121       {
01122         return HAL_TIMEOUT;
01123       }
01124
01125
01126       /* Compute how many words were supposed to be transferred by DMA */
01127       tmp_initial_DMATransferSize_inWords = (hhash->HashInCount%4 ?  (hhash->HashInCount+3)/4: hhash->HashInCount/4);
01128       /* Accordingly, update the input pointer that points at the next word to be transferred to the IP by DMA */
01129       hhash->pHashInBuffPtr +=  4 * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
01130       /* And store in HashInCount the remaining size to transfer (in bytes) */
01131       hhash->HashInCount = 4 * tmp_remaining_DMATransferSize_inWords;
01132
01133     }
01134
01135     return HAL_OK;
01136
01137   }
01138 }
01139
01140
01141 /**
01142   * @}
01143   */
01144
01145
01146 /**
01147   * @}
01148   */
01149
01150 /** @defgroup HASH_Private_Functions HASH Private Functions
01151   * @{
01152   */
01153
01154 /**
01155   * @brief DMA HASH Input Data transfer completion callback.
01156   * @param hdma: DMA handle.
01157   * @note  In case of HMAC processing, HASH_DMAXferCplt() initiates
01158   *        the next DMA transfer for the following HMAC step.
01159   * @retval None
01160   */
01161 static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
01162 {
01163   HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01164   uint32_t inputaddr = 0x0;
01165   uint32_t buffersize = 0x0;
01166
01167   if (hhash->State != HAL_HASH_STATE_SUSPENDED)
01168   {
01169
01170   /* Disable the DMA transfer */
01171   CLEAR_BIT(HASH->CR, HASH_CR_DMAE);
01172
01173   if (READ_BIT(HASH->CR, HASH_CR_MODE) == RESET)
01174   {
01175     /* If no HMAC processing, input data transfer is now over */
01176
01177     /* Change the HASH state to ready */
01178     hhash->State = HAL_HASH_STATE_READY;
01179
01180     /* Call Input data transfer complete call back */
01181     HAL_HASH_InCpltCallback(hhash);
01182   }
01183   else
01184   {
01185     /* HMAC processing: depending on the current HMAC step and whether or
01186       not multi-buffer processing is on-going, the next step is initiated
01187       and MDMAT bit is set.  */
01188
01189
01190     if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
01191     {
01192       /* This is the end of HMAC processing */
01193
01194       /* Change the HASH state to ready */
01195       hhash->State = HAL_HASH_STATE_READY;
01196
01197       /* Call Input data transfer complete call back
01198          (note that the last DMA transfer was that of the key
01199          for the outer HASH operation). */
01200       HAL_HASH_InCpltCallback(hhash);
01201
01202       return;
01203     }
01204     else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
01205     {
01206       inputaddr = (uint32_t)hhash->pHashMsgBuffPtr;     /* DMA transfer start address */
01207       buffersize = hhash->HashBuffSize;                 /* DMA transfer size (in bytes) */
01208       hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;        /* Move phase from Step 1 to Step 2 */
01209
01210       /* In case of suspension request, save the new starting parameters */
01211       hhash->HashInCount = hhash->HashBuffSize;         /* Initial DMA transfer size (in bytes) */
01212       hhash->pHashInBuffPtr  = hhash->pHashMsgBuffPtr ; /* DMA transfer start address           */
01213
01214       /* Check whether or not digest calculation must be disabled (in case of multi-buffer HMAC processing) */
01215       if (hhash->DigestCalculationDisable != RESET)
01216       {
01217         /* Digest calculation is disabled: Step 2 must start with MDMAT bit set,
01218            no digest calculation will be triggered at the end of the input buffer feeding to the IP */
01219         __HAL_HASH_SET_MDMAT();
01220       }
01221     }
01222     else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
01223     {
01224       if (hhash->DigestCalculationDisable != RESET)
01225       {
01226         /* No automatic move to Step 3 as a new message buffer will be fed to the IP
01227            (case of multi-buffer HMAC processing):
01228            DCAL must not be set.
01229            Phase remains in Step 2, MDMAT remains set at this point.
01230            Change the HASH state to ready and call Input data transfer complete call back. */
01231         hhash->State = HAL_HASH_STATE_READY;
01232         HAL_HASH_InCpltCallback(hhash);
01233         return ;
01234       }
01235       else
01236       {
01237         /* Digest calculation is not disabled (case of single buffer input or last buffer
01238           of multi-buffer HMAC processing) */
01239         inputaddr = (uint32_t)hhash->Init.pKey;       /* DMA transfer start address */
01240         buffersize = hhash->Init.KeySize;             /* DMA transfer size (in bytes) */
01241         hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3;    /* Move phase from Step 2 to Step 3 */
01242         /* In case of suspension request, save the new starting parameters */
01243         hhash->HashInCount = hhash->Init.KeySize;         /* Initial size for second DMA transfer (input data) */
01244         hhash->pHashInBuffPtr  = hhash->Init.pKey ; /* address passed to DMA, now entering data message */
01245       }
01246     }
01247     /* Configure the Number of valid bits in last word of the message */
01248     __HAL_HASH_SET_NBVALIDBITS(buffersize);
01249
01250
01251       /* Set the HASH DMA transfert completion call back */
01252       hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
01253
01254     /* Enable the DMA In DMA Stream */
01255     HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));
01256
01257     /* Enable DMA requests */
01258     SET_BIT(HASH->CR, HASH_CR_DMAE);
01259   }
01260   }
01261
01262   return;
01263 }
01264
01265 /**
01266   * @brief DMA HASH communication error callback.
01267   * @param hdma: DMA handle.
01268   * @note  HASH_DMAError() callback invokes HAL_HASH_ErrorCallback() that
01269   *        can contain user code to manage the error.
01270   * @retval None
01271   */
01272 static void HASH_DMAError(DMA_HandleTypeDef *hdma)
01273 {
01274   HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01275
01276     if (hhash->State != HAL_HASH_STATE_SUSPENDED)
01277   {
01278   /* Set HASH state to ready to prevent any blocking issue in user code
01279      present in HAL_HASH_ErrorCallback() */
01280   hhash->State= HAL_HASH_STATE_READY;
01281   /* Set HASH handle status to error */
01282   hhash->Status = HAL_ERROR;
01283   HAL_HASH_ErrorCallback(hhash);
01284   /* After error handling by code user, reset HASH handle HAL status */
01285   hhash->Status = HAL_OK;
01286
01287   }
01288 }
01289
01290 /**
01291   * @brief  Feed the input buffer to the HASH IP.
01292   * @param  hhash: HASH handle.
01293   * @param  pInBuffer: pointer to input buffer.
01294   * @param  Size: the size of input buffer in bytes.
01295   * @note   HASH_WriteData() regularly reads hhash->SuspendRequest to check whether
01296   *         or not the HASH processing must be suspended. If this is the case, the
01297   *         processing is suspended when possible and the IP feeding point reached at
01298   *         suspension time is stored in the handle for resumption later on.
01299   * @retval HAL status
01300   */
01301 static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
01302 {
01303   uint32_t buffercounter;
01304   __IO uint32_t inputaddr = (uint32_t) pInBuffer;
01305
01306   for(buffercounter = 0; buffercounter < Size; buffercounter+=4)
01307   {
01308     /* Write input data 4 bytes at a time */
01309     HASH->DIN = *(uint32_t*)inputaddr;
01310     inputaddr+=4;
01311
01312     /* If the suspension flag has been raised and if the processing is not about
01313        to end, suspend processing */
01314     if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size))
01315     {
01316       /* Wait for DINIS = 1, which occurs when 16 32-bit locations are free
01317          in the input buffer */
01318       if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
01319       {
01320         /* Reset SuspendRequest */
01321         hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
01322
01323         /* Depending whether the key or the input data were fed to the IP, the feeding point
01324            reached at suspension time is not saved in the same handle fields */
01325         if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2))
01326         {
01327           /* Save current reading and writing locations of Input and Output buffers */
01328           hhash->pHashInBuffPtr =  (uint8_t *)inputaddr;
01329           /* Save the number of bytes that remain to be processed at this point */
01330           hhash->HashInCount    =  Size - (buffercounter + 4);
01331         }
01332         else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
01333         {
01334           /* Save current reading and writing locations of Input and Output buffers */
01335           hhash->pHashKeyBuffPtr  =  (uint8_t *)inputaddr;
01336           /* Save the number of bytes that remain to be processed at this point */
01337           hhash->HashKeyCount  =  Size - (buffercounter + 4);
01338         }
01339         else
01340         {
01341           /* Unexpected phase: unlock process and report error */
01342           hhash->State = HAL_HASH_STATE_READY;
01343           __HAL_UNLOCK(hhash);
01344           return HAL_ERROR;
01345         }
01346
01347         /* Set the HASH state to Suspended and exit to stop entering data */
01348         hhash->State = HAL_HASH_STATE_SUSPENDED;
01349
01350         return HAL_OK;
01351       } /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))  */
01352     } /* if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size)) */
01353   }   /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4)                 */
01354
01355   /* At this point, all the data have been entered to the IP: exit */
01356   return  HAL_OK;
01357 }
01358
01359 /**
01360   * @brief  Retrieve the message digest.
01361   * @param  pMsgDigest: pointer to the computed digest.
01362   * @param  Size: message digest size in bytes.
01363   * @retval None
01364   */
01365 static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
01366 {
01367   uint32_t msgdigest = (uint32_t)pMsgDigest;
01368
01369   switch(Size)
01370   {
01371     /* Read the message digest */
01372     case 16:  /* MD5 */
01373       *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
01374       msgdigest+=4;
01375       *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
01376       msgdigest+=4;
01377       *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
01378       msgdigest+=4;
01379       *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
01380     break;
01381     case 20:  /* SHA1 */
01382       *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
01383       msgdigest+=4;
01384       *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
01385       msgdigest+=4;
01386       *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
01387       msgdigest+=4;
01388       *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
01389       msgdigest+=4;
01390       *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
01391     break;
01392   case 28:  /* SHA224 */
01393     *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
01394     msgdigest+=4;
01395     *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
01396     msgdigest+=4;
01397     *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
01398     msgdigest+=4;
01399     *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
01400     msgdigest+=4;
01401     *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
01402     msgdigest+=4;
01403     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
01404     msgdigest+=4;
01405     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
01406     break;
01407   case 32:   /* SHA256 */
01408     *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
01409     msgdigest+=4;
01410     *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
01411     msgdigest+=4;
01412     *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
01413     msgdigest+=4;
01414     *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
01415     msgdigest+=4;
01416     *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
01417     msgdigest+=4;
01418     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
01419     msgdigest+=4;
01420     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
01421     msgdigest+=4;
01422     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
01423     break;
01424     default:
01425     break;
01426   }
01427 }
01428
01429
01430
01431 /**
01432   * @brief  Handle HASH processing Timeout.
01433   * @param  hhash: HASH handle.
01434   * @param  Flag: specifies the HASH flag to check.
01435   * @param  Status: the Flag status (SET or RESET).
01436   * @param  Timeout: Timeout duration.
01437   * @retval HAL status
01438   */
01439 static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
01440 {
01441   uint32_t tickstart = HAL_GetTick();
01442
01443   /* Wait until flag is set */
01444   if(Status == RESET)
01445   {
01446     while(__HAL_HASH_GET_FLAG(Flag) == RESET)
01447     {
01448       /* Check for the Timeout */
01449       if(Timeout != HAL_MAX_DELAY)
01450       {
01451         if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
01452         {
01453           /* Set State to Ready to be able to restart later on */
01454           hhash->State  = HAL_HASH_STATE_READY;
01455           /* Store time out issue in handle status */
01456           hhash->Status = HAL_TIMEOUT;
01457
01458           /* Process Unlocked */
01459           __HAL_UNLOCK(hhash);
01460
01461           return HAL_TIMEOUT;
01462         }
01463       }
01464     }
01465   }
01466   else
01467   {
01468     while(__HAL_HASH_GET_FLAG(Flag) != RESET)
01469     {
01470       /* Check for the Timeout */
01471       if(Timeout != HAL_MAX_DELAY)
01472       {
01473         if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
01474         {
01475           /* Set State to Ready to be able to restart later on */
01476           hhash->State  = HAL_HASH_STATE_READY;
01477           /* Store time out issue in handle status */
01478           hhash->Status = HAL_TIMEOUT;
01479
01480           /* Process Unlocked */
01481           __HAL_UNLOCK(hhash);
01482
01483           return HAL_TIMEOUT;
01484         }
01485       }
01486     }
01487   }
01488   return HAL_OK;
01489 }
01490
01491
01492 /**
01493   * @brief  HASH processing in interruption mode.
01494   * @param  hhash: HASH handle.
01495   * @note   HASH_IT() regularly reads hhash->SuspendRequest to check whether
01496   *         or not the HASH processing must be suspended. If this is the case, the
01497   *         processing is suspended when possible and the IP feeding point reached at
01498   *         suspension time is stored in the handle for resumption later on.
01499   * @retval HAL status
01500   */
01501 static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash)
01502 {
01503   if (hhash->State == HAL_HASH_STATE_BUSY)
01504   {
01505     /* ITCounter must not be equal to 0 at this point. Report an error if this is the case. */
01506     if(hhash->HashITCounter == 0)
01507     {
01508       /* Disable Interrupts */
01509       __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
01510       /* HASH state set back to Ready to prevent any issue in user code
01511          present in HAL_HASH_ErrorCallback() */
01512       hhash->State = HAL_HASH_STATE_READY;
01513       return HAL_ERROR;
01514     }
01515     else if (hhash->HashITCounter == 1)
01516     {
01517      /* This is the first call to HASH_IT, the first input data are about to be
01518         entered in the IP. A specific processing is carried out at this point to
01519         start-up the processing. */
01520       hhash->HashITCounter = 2;
01521     }
01522     else
01523     {
01524       /* Cruise speed reached, HashITCounter remains equal to 3 until the end of
01525         the HASH processing or the end of the current step for HMAC processing. */
01526       hhash->HashITCounter = 3;
01527     }
01528
01529     /* If digest is ready */
01530     if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
01531     {
01532       /* Read the digest */
01533       HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
01534
01535       /* Disable Interrupts */
01536       __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
01537       /* Change the HASH state */
01538       hhash->State = HAL_HASH_STATE_READY;
01539       /* Call digest computation complete call back */
01540       HAL_HASH_DgstCpltCallback(hhash);
01541
01542       return HAL_OK;
01543     }
01544
01545     /* If IP ready to accept new data */
01546     if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
01547     {
01548
01549       /* If the suspension flag has been raised and if the processing is not about
01550          to end, suspend processing */
01551       if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && (hhash->HashInCount != 0))
01552       {
01553         /* Disable Interrupts */
01554         __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
01555
01556         /* Reset SuspendRequest */
01557         hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
01558
01559         /* Change the HASH state */
01560         hhash->State = HAL_HASH_STATE_SUSPENDED;
01561
01562         return HAL_OK;
01563       }
01564
01565       /* Enter input data in the IP thru HASH_Write_Block_Data() call and
01566         check whether the digest calculation has been triggered */
01567       if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED)
01568       {
01569         /* Call Input data transfer complete call back
01570            (called at the end of each step for HMAC) */
01571         HAL_HASH_InCpltCallback(hhash);
01572
01573         if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
01574         {
01575           /* Wait until IP is not busy anymore */
01576           if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
01577           {
01578             /* Disable Interrupts */
01579             __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
01580             return HAL_TIMEOUT;
01581           }
01582           /* Initialization start for HMAC STEP 2 */
01583           hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;        /* Move phase from Step 1 to Step 2 */
01584           __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize);  /* Set NBLW for the input message */
01585           hhash->HashInCount = hhash->HashBuffSize;         /* Set the input data size (in bytes) */
01586           hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr;   /* Set the input data address */
01587           hhash->HashITCounter = 1;                         /* Set ITCounter to 1 to indicate the start of a new phase */
01588           __HAL_HASH_ENABLE_IT(HASH_IT_DINI);               /* Enable IT (was disabled in HASH_Write_Block_Data) */
01589         }
01590         else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
01591         {
01592           /* Wait until IP is not busy anymore */
01593           if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
01594           {
01595             /* Disable Interrupts */
01596             __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
01597             return HAL_TIMEOUT;
01598           }
01599           /* Initialization start for HMAC STEP 3 */
01600           hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3;         /* Move phase from Step 2 to Step 3 */
01601           __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);   /* Set NBLW for the key */
01602           hhash->HashInCount = hhash->Init.KeySize;          /* Set the key size (in bytes) */
01603           hhash->pHashInBuffPtr = hhash->Init.pKey;          /* Set the key address */
01604           hhash->HashITCounter = 1;                          /* Set ITCounter to 1 to indicate the start of a new phase */
01605           __HAL_HASH_ENABLE_IT(HASH_IT_DINI);                /* Enable IT (was disabled in HASH_Write_Block_Data) */
01606         }
01607       } /* if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED) */
01608     }  /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))*/
01609
01610     /* Return function status */
01611     return HAL_OK;
01612   }
01613   else
01614   {
01615     return HAL_BUSY;
01616   }
01617 }
01618
01619
01620 /**
01621   * @brief  Write a block of data in HASH IP in interruption mode.
01622   * @param  hhash: HASH handle.
01623   * @note   HASH_Write_Block_Data() is called under interruption by HASH_IT().
01624   * @retval HAL status
01625   */
01626 static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash)
01627 {
01628   uint32_t inputaddr;
01629   uint32_t buffercounter;
01630   uint32_t inputcounter;
01631   uint32_t ret = HASH_DIGEST_CALCULATION_NOT_STARTED;
01632
01633   /* If there are more than 64 bytes remaining to be entered */
01634   if(hhash->HashInCount > 64)
01635   {
01636     inputaddr = (uint32_t)hhash->pHashInBuffPtr;
01637     /* Write the Input block in the Data IN register
01638       (16 32-bit words, or 64 bytes are entered) */
01639     for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
01640     {
01641       HASH->DIN = *(uint32_t*)inputaddr;
01642       inputaddr+=4;
01643     }
01644     /* If this is the start of input data entering, an additional word
01645       must be entered to start up the HASH processing */
01646     if(hhash->HashITCounter == 2)
01647     {
01648       HASH->DIN = *(uint32_t*)inputaddr;
01649       inputaddr+=4;
01650       if(hhash->HashInCount >= 68)
01651       {
01652         /* There are still data waiting to be entered in the IP.
01653            Decrement buffer counter and set pointer to the proper
01654            memory location for the next data entering round. */
01655         hhash->HashInCount -= 68;
01656         hhash->pHashInBuffPtr+= 68;
01657       }
01658       else
01659       {
01660         /* All the input buffer has been fed to the HW. */
01661         hhash->HashInCount = 0;
01662       }
01663     }
01664     else
01665     {
01666       /* 64 bytes have been entered and there are still some remaining:
01667          Decrement buffer counter and set pointer to the proper
01668         memory location for the next data entering round.*/
01669       hhash->HashInCount -= 64;
01670       hhash->pHashInBuffPtr+= 64;
01671     }
01672   }
01673   else
01674   {
01675     /* 64 or less bytes remain to be entered. This is the last
01676       data entering round. */
01677
01678     /* Get the buffer address */
01679     inputaddr = (uint32_t)hhash->pHashInBuffPtr;
01680     /* Get the buffer counter */
01681     inputcounter = hhash->HashInCount;
01682     /* Disable Interrupts */
01683     __HAL_HASH_DISABLE_IT(HASH_IT_DINI);
01684
01685     /* Write the Input block in the Data IN register */
01686     for(buffercounter = 0; buffercounter < (inputcounter+3)/4; buffercounter++)
01687     {
01688       HASH->DIN = *(uint32_t*)inputaddr;
01689       inputaddr+=4;
01690     }
01691     /* Start the Digest calculation */
01692     __HAL_HASH_START_DIGEST();
01693     /* Return indication that digest calculation has started:
01694        this return value triggers the call to Input data transfer
01695        complete call back as well as the proper transition from
01696        one step to another in HMAC mode. */
01697     ret = HASH_DIGEST_CALCULATION_STARTED;
01698     /* Reset buffer counter */
01699     hhash->HashInCount = 0;
01700   }
01701
01702   /* Return whether or digest calculation has started */
01703   return ret;
01704 }
01705
01706 /**
01707   * @brief  HMAC processing in polling mode.
01708   * @param  hhash: HASH handle.
01709   * @param  Timeout: Timeout value.
01710   * @retval HAL status
01711   */
01712 static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout)
01713 {
01714   /* Ensure first that Phase is correct */
01715   if ((hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_1) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_2) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_3))
01716   {
01717     /* Change the HASH state */
01718     hhash->State = HAL_HASH_STATE_READY;
01719
01720     /* Process Unlock */
01721     __HAL_UNLOCK(hhash);
01722
01723     /* Return function status */
01724     return HAL_ERROR;
01725   }
01726
01727   /* HMAC Step 1 processing */
01728   if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
01729   {
01730     /************************** STEP 1 ******************************************/
01731     /* Configure the Number of valid bits in last word of the message */
01732     __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
01733
01734     /* Write input buffer in Data register */
01735     if ((hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount)) != HAL_OK)
01736     {
01737       return hhash->Status;
01738     }
01739
01740     /* Check whether or not key entering process has been suspended */
01741     if (hhash->State == HAL_HASH_STATE_SUSPENDED)
01742     {
01743       /* Process Unlocked */
01744       __HAL_UNLOCK(hhash);
01745
01746       /* Stop right there and return function status */
01747       return HAL_OK;
01748     }
01749
01750     /* No processing suspension at this point: set DCAL bit. */
01751     __HAL_HASH_START_DIGEST();
01752
01753     /* Wait for BUSY flag to be cleared */
01754     if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
01755     {
01756       return HAL_TIMEOUT;
01757     }
01758
01759     /* Move from Step 1 to Step 2 */
01760     hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;
01761
01762   }
01763
01764   /* HMAC Step 2 processing.
01765      After phase check, HMAC_Processing() may
01766      - directly start up from this point in resumption case
01767        if the same Step 2 processing was suspended previously
01768     - or fall through from the Step 1 processing carried out hereabove */
01769   if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
01770   {
01771     /************************** STEP 2 ******************************************/
01772     /* Configure the Number of valid bits in last word of the message */
01773     __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize);
01774
01775     /* Write input buffer in Data register */
01776     if ((hhash->Status = HASH_WriteData(hhash, hhash->pHashInBuffPtr, hhash->HashInCount)) != HAL_OK)
01777     {
01778       return hhash->Status;
01779     }
01780
01781     /* Check whether or not data entering process has been suspended */
01782     if (hhash->State == HAL_HASH_STATE_SUSPENDED)
01783     {
01784       /* Process Unlocked */
01785       __HAL_UNLOCK(hhash);
01786
01787       /* Stop right there and return function status */
01788       return HAL_OK;
01789     }
01790
01791     /* No processing suspension at this point: set DCAL bit. */
01792     __HAL_HASH_START_DIGEST();
01793
01794     /* Wait for BUSY flag to be cleared */
01795     if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
01796     {
01797       return HAL_TIMEOUT;
01798     }
01799
01800     /* Move from Step 2 to Step 3 */
01801     hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3;
01802     /* In case Step 1 phase was suspended then resumed,
01803        set again Key input buffers and size before moving to
01804        next step */
01805     hhash->pHashKeyBuffPtr = hhash->Init.pKey;
01806     hhash->HashKeyCount    = hhash->Init.KeySize;
01807   }
01808
01809
01810  /* HMAC Step 3 processing.
01811      After phase check, HMAC_Processing() may
01812      - directly start up from this point in resumption case
01813        if the same Step 3 processing was suspended previously
01814     - or fall through from the Step 2 processing carried out hereabove */
01815   if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
01816   {
01817     /************************** STEP 3 ******************************************/
01818     /* Configure the Number of valid bits in last word of the message */
01819     __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
01820
01821     /* Write input buffer in Data register */
01822     if ((hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount)) != HAL_OK)
01823     {
01824       return hhash->Status;
01825     }
01826
01827     /* Check whether or not key entering process has been suspended */
01828     if (hhash->State == HAL_HASH_STATE_SUSPENDED)
01829     {
01830       /* Process Unlocked */
01831       __HAL_UNLOCK(hhash);
01832
01833       /* Stop right there and return function status */
01834       return HAL_OK;
01835     }
01836
01837     /* No processing suspension at this point: start the Digest calculation. */
01838     __HAL_HASH_START_DIGEST();
01839
01840     /* Wait for DCIS flag to be set */
01841      if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
01842     {
01843       return HAL_TIMEOUT;
01844     }
01845
01846     /* Read the message digest */
01847     HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
01848   }
01849
01850    /* Change the HASH state */
01851    hhash->State = HAL_HASH_STATE_READY;
01852
01853    /* Process Unlock */
01854    __HAL_UNLOCK(hhash);
01855
01856    /* Return function status */
01857    return HAL_OK;
01858 }
01859
01860
01861 /**
01862   * @brief  Initialize the HASH peripheral, next process pInBuffer then
01863   *         read the computed digest.
01864   * @note   Digest is available in pOutBuffer.
01865   * @param  hhash: HASH handle.
01866   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
01867   * @param  Size: length of the input buffer in bytes.
01868   * @param  pOutBuffer: pointer to the computed digest.
01869   * @param  Timeout: Timeout value.
01870   * @param  Algorithm: HASH algorithm.
01871   * @retval HAL status
01872   */
01873 HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
01874 {
01875   uint8_t *pInBuffer_tmp;  /* input data address, input parameter of HASH_WriteData()         */
01876   uint32_t Size_tmp = 0x0; /* input data size (in bytes), input parameter of HASH_WriteData() */
01877
01878   /* Initiate HASH processing in case of start or resumption */
01879   if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED))
01880   {
01881     /* Check input parameters */
01882     if ((pInBuffer == NULL) || (Size == 0) || (pOutBuffer == NULL))
01883     {
01884       hhash->State = HAL_HASH_STATE_READY;
01885       return  HAL_ERROR;
01886     }
01887
01888   /* Process Locked */
01889   __HAL_LOCK(hhash);
01890
01891   /* Check if initialization phase has not been already performed */
01892   if(hhash->Phase == HAL_HASH_PHASE_READY)
01893   {
01894     /* Change the HASH state */
01895     hhash->State = HAL_HASH_STATE_BUSY;
01896
01897     /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
01898     MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
01899
01900     /* Configure the number of valid bits in last word of the message */
01901     __HAL_HASH_SET_NBVALIDBITS(Size);
01902
01903     /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
01904        input parameters of HASH_WriteData() */
01905     pInBuffer_tmp = pInBuffer;   /* pInBuffer_tmp is set to the input data address */
01906     Size_tmp = Size;             /* Size_tmp contains the input data size in bytes */
01907
01908     /* Set the phase */
01909     hhash->Phase = HAL_HASH_PHASE_PROCESS;
01910   }
01911   else if (hhash->Phase == HAL_HASH_PHASE_PROCESS)
01912   {
01913     /* if the IP has already been initialized, two cases are possible */
01914
01915     /* Process resumption time ... */
01916     if (hhash->State == HAL_HASH_STATE_SUSPENDED)
01917     {
01918       /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
01919         to the API input parameters but to those saved beforehand by HASH_WriteData()
01920         when the processing was suspended */
01921       pInBuffer_tmp = hhash->pHashInBuffPtr;
01922       Size_tmp = hhash->HashInCount;
01923     }
01924     /* ... or multi-buffer HASH processing end */
01925     else
01926     {
01927       /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
01928          input parameters of HASH_WriteData() */
01929       pInBuffer_tmp = pInBuffer;
01930       Size_tmp = Size;
01931       /* Configure the number of valid bits in last word of the message */
01932       __HAL_HASH_SET_NBVALIDBITS(Size);
01933     }
01934     /* Change the HASH state */
01935     hhash->State = HAL_HASH_STATE_BUSY;
01936   }
01937   else
01938   {
01939     /* Phase error */
01940     hhash->State = HAL_HASH_STATE_READY;
01941
01942     /* Process Unlocked */
01943     __HAL_UNLOCK(hhash);
01944
01945     /* Return function status */
01946     return HAL_ERROR;
01947   }
01948
01949
01950   /* Write input buffer in Data register */
01951   if ((hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp)) != HAL_OK)
01952   {
01953     return hhash->Status;
01954   }
01955
01956   /* If the process has not been suspended, carry on to digest calculation */
01957   if (hhash->State != HAL_HASH_STATE_SUSPENDED)
01958   {
01959     /* Start the Digest calculation */
01960     __HAL_HASH_START_DIGEST();
01961
01962     /* Wait for DCIS flag to be set */
01963     if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
01964     {
01965       return HAL_TIMEOUT;
01966     }
01967
01968     /* Read the message digest */
01969     HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
01970
01971     /* Change the HASH state */
01972     hhash->State = HAL_HASH_STATE_READY;
01973
01974   }
01975
01976   /* Process Unlocked */
01977   __HAL_UNLOCK(hhash);
01978
01979   /* Return function status */
01980   return HAL_OK;
01981
01982   }
01983   else
01984   {
01985     return HAL_BUSY;
01986   }
01987 }
01988
01989
01990 /**
01991   * @brief  If not already done, initialize the HASH peripheral then
01992   *         processes pInBuffer.
01993   * @note   Field hhash->Phase of HASH handle is tested to check whether or not
01994   *         the IP has already been initialized.
01995   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
01996   *         HASH digest computation is corrupted.
01997   * @param  hhash: HASH handle.
01998   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
01999   * @param  Size: length of the input buffer in bytes, must be a multiple of 4.
02000   * @param  Algorithm: HASH algorithm.
02001   * @retval HAL status
02002   */
02003 HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
02004 {
02005   uint8_t *pInBuffer_tmp;   /* input data address, input parameter of HASH_WriteData()         */
02006   uint32_t Size_tmp = 0x0;  /* input data size (in bytes), input parameter of HASH_WriteData() */
02007
02008   /* Make sure the input buffer size (in bytes) is a multiple of 4 */
02009    assert_param(IS_HASH_POLLING_MULTIBUFFER_SIZE(Size));
02010
02011
02012   /* Initiate HASH processing in case of start or resumption */
02013   if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED))
02014   {
02015     /* Check input parameters */
02016     if ((pInBuffer == NULL) || (Size == 0))
02017     {
02018       hhash->State = HAL_HASH_STATE_READY;
02019       return  HAL_ERROR;
02020     }
02021
02022      /* Process Locked */
02023     __HAL_LOCK(hhash);
02024
02025     /* If resuming the HASH processing */
02026     if (hhash->State == HAL_HASH_STATE_SUSPENDED)
02027     {
02028       /* Change the HASH state */
02029       hhash->State = HAL_HASH_STATE_BUSY;
02030
02031       /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
02032          to the API input parameters but to those saved beforehand by HASH_WriteData()
02033          when the processing was suspended */
02034       pInBuffer_tmp = hhash->pHashInBuffPtr;  /* pInBuffer_tmp is set to the input data address */
02035       Size_tmp = hhash->HashInCount;          /* Size_tmp contains the input data size in bytes */
02036
02037     }
02038     else
02039     {
02040       /* Change the HASH state */
02041       hhash->State = HAL_HASH_STATE_BUSY;
02042
02043       /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
02044          input parameters of HASH_WriteData() */
02045       pInBuffer_tmp = pInBuffer;    /* pInBuffer_tmp is set to the input data address */
02046       Size_tmp = Size;              /* Size_tmp contains the input data size in bytes */
02047
02048       /* Check if initialization phase has already be performed */
02049       if(hhash->Phase == HAL_HASH_PHASE_READY)
02050       {
02051         /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
02052         MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
02053       }
02054
02055       /* Set the phase */
02056       hhash->Phase = HAL_HASH_PHASE_PROCESS;
02057
02058     }
02059
02060     /* Write input buffer in Data register */
02061     if ((hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp)) != HAL_OK)
02062     {
02063       return hhash->Status;
02064     }
02065
02066     /* If the process has not been suspended, move the state to Ready */
02067     if (hhash->State != HAL_HASH_STATE_SUSPENDED)
02068     {
02069       /* Change the HASH state */
02070       hhash->State = HAL_HASH_STATE_READY;
02071     }
02072
02073     /* Process Unlocked */
02074     __HAL_UNLOCK(hhash);
02075
02076     /* Return function status */
02077     return HAL_OK;
02078
02079   }
02080   else
02081   {
02082     return HAL_BUSY;
02083   }
02084
02085
02086 }
02087
02088
02089 /**
02090   * @brief  Initialize the HASH peripheral, next process pInBuffer then
02091   *         read the computed digest in interruption mode.
02092   * @note   Digest is available in pOutBuffer.
02093   * @param  hhash: HASH handle.
02094   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
02095   * @param  Size: length of the input buffer in bytes.
02096   * @param  pOutBuffer: pointer to the computed digest.
02097   * @param  Algorithm: HASH algorithm.
02098   * @retval HAL status
02099   */
02100 HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
02101 {
02102
02103   /* If State is ready or suspended, start or resume IT-based HASH processing */
02104   if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED))
02105   {
02106     /* Check input parameters */
02107     if ((pInBuffer == NULL) || (Size == 0) || (pOutBuffer == NULL))
02108     {
02109       hhash->State = HAL_HASH_STATE_READY;
02110       return  HAL_ERROR;
02111     }
02112
02113     /* Process Locked */
02114     __HAL_LOCK(hhash);
02115
02116     /* Change the HASH state */
02117     hhash->State = HAL_HASH_STATE_BUSY;
02118
02119     /* Initialize IT counter */
02120     hhash->HashITCounter = 1;
02121
02122     /* Check if initialization phase has already be performed */
02123     if(hhash->Phase == HAL_HASH_PHASE_READY)
02124     {
02125       /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
02126       MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
02127
02128       /* Configure the number of valid bits in last word of the message */
02129      __HAL_HASH_SET_NBVALIDBITS(Size);
02130
02131
02132       hhash->HashInCount = Size;               /* Counter used to keep track of number of data
02133                                                   to be fed to the IP */
02134       hhash->pHashInBuffPtr = pInBuffer;       /* Points at data which will be fed to the IP at
02135                                                   the next interruption */
02136      /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
02137         the information describing where the HASH process is stopped.
02138         These variables are used later on to resume the HASH processing at the
02139         correct location. */
02140
02141       hhash->pHashOutBuffPtr = pOutBuffer;     /* Points at the computed digest */
02142     }
02143
02144     /* Set the phase */
02145     hhash->Phase = HAL_HASH_PHASE_PROCESS;
02146
02147     /* Process Unlock */
02148     __HAL_UNLOCK(hhash);
02149
02150     /* Enable Interrupts */
02151     __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
02152
02153     /* Return function status */
02154     return HAL_OK;
02155   }
02156   else
02157   {
02158     return HAL_BUSY;
02159   }
02160
02161 }
02162
02163
02164 /**
02165   * @brief  Initialize the HASH peripheral then initiate a DMA transfer
02166   *         to feed the input buffer to the IP.
02167   * @note   If MDMAT bit is set before calling this function (multi-buffer
02168   *          HASH processing case), the input buffer size (in bytes) must be
02169   *          a multiple of 4 otherwise, the HASH digest computation is corrupted.
02170   *          For the processing of the last buffer of the thread, MDMAT bit must
02171   *          be reset and the buffer length (in bytes) doesn't have to be a
02172   *          multiple of 4.
02173   * @param  hhash: HASH handle.
02174   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
02175   * @param  Size: length of the input buffer in bytes.
02176   * @param  Algorithm: HASH algorithm.
02177   * @retval HAL status
02178   */
02179 HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
02180 {
02181   uint32_t inputaddr;
02182   uint32_t inputSize = 0x0;
02183
02184   /* Make sure the input buffer size (in bytes) is a multiple of 4 when MDMAT bit is set
02185      (case of multi-buffer HASH processing) */
02186   assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size));
02187
02188   /* If State is ready or suspended, start or resume DMA-based HASH processing */
02189   if ((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED))
02190   {
02191     /* Check input parameters */
02192     if ( (pInBuffer == NULL ) || (Size == 0) ||
02193     /* Check phase coherency. Phase must be
02194        either READY (fresh start)
02195        or PROCESS (multi-buffer HASH management) */
02196        ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash)))))
02197     {
02198       hhash->State = HAL_HASH_STATE_READY;
02199       return  HAL_ERROR;
02200     }
02201
02202
02203     /* Process Locked */
02204     __HAL_LOCK(hhash);
02205
02206     /* If not a resumption case */
02207     if (hhash->State == HAL_HASH_STATE_READY)
02208     {
02209       /* Change the HASH state */
02210       hhash->State = HAL_HASH_STATE_BUSY;
02211
02212       /* Check if initialization phase has already been performed.
02213          If Phase is already set to HAL_HASH_PHASE_PROCESS, this means the
02214          API is processing a new input data message in case of multi-buffer HASH
02215          computation. */
02216       if(hhash->Phase == HAL_HASH_PHASE_READY)
02217       {
02218         /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
02219         MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
02220
02221         /* Set the phase */
02222         hhash->Phase = HAL_HASH_PHASE_PROCESS;
02223       }
02224
02225       /* Configure the Number of valid bits in last word of the message */
02226       __HAL_HASH_SET_NBVALIDBITS(Size);
02227
02228       inputaddr = (uint32_t)pInBuffer;     /* DMA transfer start address   */
02229       inputSize = Size;                    /* DMA transfer size (in bytes) */
02230
02231       /* In case of suspension request, save the starting parameters */
02232       hhash->pHashInBuffPtr =  pInBuffer;  /* DMA transfer start address   */
02233       hhash->HashInCount = Size;           /* DMA transfer size (in bytes) */
02234
02235     }
02236     /* If resumption case */
02237     else
02238     {
02239       /* Change the HASH state */
02240       hhash->State = HAL_HASH_STATE_BUSY;
02241
02242       /* Resumption case, inputaddr and inputSize are not set to the API input parameters
02243          but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the
02244          processing was suspended */
02245       inputaddr = (uint32_t)hhash->pHashInBuffPtr;  /* DMA transfer start address   */
02246       inputSize = hhash->HashInCount;               /* DMA transfer size (in bytes) */
02247     }
02248
02249     /* Set the HASH DMA transfert complete callback */
02250     hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
02251     /* Set the DMA error callback */
02252     hhash->hdmain->XferErrorCallback = HASH_DMAError;
02253
02254     /* Enable the DMA In DMA Stream */
02255     HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (inputSize%4 ? (inputSize+3)/4:inputSize/4));
02256
02257     /* Enable DMA requests */
02258     SET_BIT(HASH->CR, HASH_CR_DMAE);
02259
02260     /* Process Unlock */
02261     __HAL_UNLOCK(hhash);
02262
02263     /* Return function status */
02264     return HAL_OK;
02265   }
02266   else
02267   {
02268     return HAL_BUSY;
02269   }
02270
02271 }
02272
02273 /**
02274   * @brief  Return the computed digest.
02275   * @note   The API waits for DCIS to be set then reads the computed digest.
02276   * @param  hhash: HASH handle.
02277   * @param  pOutBuffer: pointer to the computed digest.
02278   * @param  Timeout: Timeout value.
02279   * @retval HAL status
02280   */
02281 HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
02282 {
02283
02284   if(hhash->State == HAL_HASH_STATE_READY)
02285   {
02286     /* Check parameter */
02287     if (pOutBuffer == NULL)
02288     {
02289       return  HAL_ERROR;
02290     }
02291
02292     /* Process Locked */
02293     __HAL_LOCK(hhash);
02294
02295     /* Change the HASH state to busy */
02296     hhash->State = HAL_HASH_STATE_BUSY;
02297
02298     /* Wait for DCIS flag to be set */
02299     if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
02300     {
02301       return HAL_TIMEOUT;
02302     }
02303
02304     /* Read the message digest */
02305     HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
02306
02307     /* Change the HASH state to ready */
02308     hhash->State = HAL_HASH_STATE_READY;
02309
02310     /* Process UnLock */
02311     __HAL_UNLOCK(hhash);
02312
02313     /* Return function status */
02314     return HAL_OK;
02315
02316   }
02317   else
02318   {
02319     return HAL_BUSY;
02320   }
02321
02322 }
02323
02324
02325 /**
02326   * @brief  Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
02327   *         read the computed digest.
02328   * @note   Digest is available in pOutBuffer.
02329   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
02330   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
02331   * @param  hhash: HASH handle.
02332   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
02333   * @param  Size: length of the input buffer in bytes.
02334   * @param  pOutBuffer: pointer to the computed digest.
02335   * @param  Timeout: Timeout value.
02336   * @param  Algorithm: HASH algorithm.
02337   * @retval HAL status
02338   */
02339 HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
02340 {
02341
02342   /* If State is ready or suspended, start or resume polling-based HASH processing */
02343   if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED))
02344   {
02345     /* Check input parameters */
02346     if ((pInBuffer == NULL) || (Size == 0) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0) || (pOutBuffer == NULL))
02347     {
02348       hhash->State = HAL_HASH_STATE_READY;
02349       return  HAL_ERROR;
02350     }
02351
02352     /* Process Locked */
02353     __HAL_LOCK(hhash);
02354
02355     /* Change the HASH state */
02356     hhash->State = HAL_HASH_STATE_BUSY;
02357
02358     /* Check if initialization phase has already be performed */
02359     if(hhash->Phase == HAL_HASH_PHASE_READY)
02360     {
02361       /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
02362       if(hhash->Init.KeySize > 64)
02363       {
02364         MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
02365       }
02366       else
02367       {
02368         MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
02369       }
02370       /* Set the phase to Step 1 */
02371       hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
02372       /* Resort to hhash internal fields to feed the IP.
02373          Parameters will be updated in case of suspension to contain the proper
02374          information at resumption time. */
02375       hhash->pHashOutBuffPtr  = pOutBuffer;            /* Output digest address                                              */
02376       hhash->pHashInBuffPtr   = pInBuffer;             /* Input data address, HMAC_Processing input parameter for Step 2     */
02377       hhash->HashInCount      = Size;                  /* Input data size, HMAC_Processing input parameter for Step 2        */
02378       hhash->HashBuffSize     = Size;                  /* Store the input buffer size for the whole HMAC process             */
02379       hhash->pHashKeyBuffPtr  = hhash->Init.pKey;      /* Key address, HMAC_Processing input parameter for Step 1 and Step 3 */
02380       hhash->HashKeyCount     = hhash->Init.KeySize;   /* Key size, HMAC_Processing input parameter for Step 1 and Step 3    */
02381     }
02382
02383     /* Carry out HMAC processing */
02384     return HMAC_Processing(hhash, Timeout);
02385
02386   }
02387   else
02388   {
02389     return HAL_BUSY;
02390   }
02391 }
02392
02393
02394
02395 /**
02396   * @brief  Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
02397   *         read the computed digest in interruption mode.
02398   * @note   Digest is available in pOutBuffer.
02399   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
02400   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
02401   * @param  hhash: HASH handle.
02402   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
02403   * @param  Size: length of the input buffer in bytes.
02404   * @param  pOutBuffer: pointer to the computed digest.
02405   * @param  Algorithm: HASH algorithm.
02406   * @retval HAL status
02407   */
02408 HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
02409 {
02410   /* If State is ready or suspended, start or resume IT-based HASH processing */
02411   if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED))
02412   {
02413     /* Check input parameters */
02414     if ((pInBuffer == NULL) || (Size == 0) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0) || (pOutBuffer == NULL))
02415     {
02416       hhash->State = HAL_HASH_STATE_READY;
02417       return  HAL_ERROR;
02418     }
02419
02420     /* Process Locked */
02421     __HAL_LOCK(hhash);
02422
02423     /* Change the HASH state */
02424     hhash->State = HAL_HASH_STATE_BUSY;
02425
02426     /* Initialize IT counter */
02427     hhash->HashITCounter = 1;
02428
02429     /* Check if initialization phase has already be performed */
02430     if (hhash->Phase == HAL_HASH_PHASE_READY)
02431     {
02432       /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
02433       if(hhash->Init.KeySize > 64)
02434       {
02435         MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
02436       }
02437       else
02438       {
02439         MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
02440       }
02441
02442       /* Resort to hhash internal fields hhash->pHashInBuffPtr and hhash->HashInCount
02443          to feed the IP whatever the HMAC step.
02444          Lines below are set to start HMAC Step 1 processing where key is entered first. */
02445       hhash->HashInCount     = hhash->Init.KeySize; /* Key size                      */
02446       hhash->pHashInBuffPtr  = hhash->Init.pKey ;   /* Key address                   */
02447
02448       /* Store input and output parameters in handle fields to manage steps transition
02449          or possible HMAC suspension/resumption */
02450       hhash->pHashKeyBuffPtr = hhash->Init.pKey;    /* Key address                   */
02451       hhash->pHashMsgBuffPtr = pInBuffer;           /* Input message address         */
02452       hhash->HashBuffSize    = Size;                /* Input message size (in bytes) */
02453       hhash->pHashOutBuffPtr = pOutBuffer;          /* Output digest address         */
02454
02455       /* Configure the number of valid bits in last word of the key */
02456       __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
02457
02458       /* Set the phase to Step 1 */
02459       hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
02460     }
02461     else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
02462     {
02463       /* Restart IT-based HASH processing after Step 1 or Step 3 suspension */
02464
02465     }
02466     else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
02467     {
02468       /* Restart IT-based HASH processing after Step 2 suspension */
02469
02470     }
02471     else
02472     {
02473       /* Error report as phase incorrect */
02474       /* Process Unlock */
02475       __HAL_UNLOCK(hhash);
02476       hhash->State = HAL_HASH_STATE_READY;
02477       return HAL_ERROR;
02478     }
02479
02480     /* Process Unlock */
02481     __HAL_UNLOCK(hhash);
02482
02483     /* Enable Interrupts */
02484     __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
02485
02486     /* Return function status */
02487     return HAL_OK;
02488   }
02489   else
02490   {
02491     return HAL_BUSY;
02492   }
02493
02494 }
02495
02496
02497
02498 /**
02499   * @brief  Initialize the HASH peripheral in HMAC mode then initiate the required
02500   *         DMA transfers to feed the key and the input buffer to the IP.
02501   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
02502   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
02503   * @note   In case of multi-buffer HMAC processing, the input buffer size (in bytes) must
02504   *         be a multiple of 4 otherwise, the HASH digest computation is corrupted.
02505   *         Only the length of the last buffer of the thread doesn't have to be a
02506   *         multiple of 4.
02507   * @param  hhash: HASH handle.
02508   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
02509   * @param  Size: length of the input buffer in bytes.
02510   * @param  Algorithm: HASH algorithm.
02511   * @retval HAL status
02512   */
02513 HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
02514 {
02515   uint32_t inputaddr;
02516   uint32_t inputSize = 0x0;
02517
02518    /* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation
02519       is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */
02520    assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size));
02521
02522   /* If State is ready or suspended, start or resume DMA-based HASH processing */
02523   if ((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED))
02524   {
02525     /* Check input parameters */
02526     if ((pInBuffer == NULL ) || (Size == 0) || (hhash->Init.pKey == NULL ) || (hhash->Init.KeySize == 0) ||
02527    /* Check phase coherency. Phase must be
02528        either READY (fresh start)
02529        or one of HMAC PROCESS steps (multi-buffer HASH management) */
02530        ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash)))))
02531     {
02532       hhash->State = HAL_HASH_STATE_READY;
02533       return  HAL_ERROR;
02534     }
02535
02536
02537     /* Process Locked */
02538     __HAL_LOCK(hhash);
02539
02540     /* If not a case of resumption after suspension */
02541     if (hhash->State == HAL_HASH_STATE_READY)
02542     {
02543     /* Check whether or not initialization phase has already be performed */
02544     if(hhash->Phase == HAL_HASH_PHASE_READY)
02545     {
02546       /* Change the HASH state */
02547       hhash->State = HAL_HASH_STATE_BUSY;
02548
02549       /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits.
02550          At the same time, ensure MDMAT bit is cleared. */
02551       if(hhash->Init.KeySize > 64)
02552       {
02553         MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
02554       }
02555       else
02556       {
02557         MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
02558       }
02559
02560       /* Store input aparameters in handle fields to manage steps transition
02561          or possible HMAC suspension/resumption */
02562       hhash->HashInCount = hhash->Init.KeySize;   /* Initial size for first DMA transfer (key size)      */
02563       hhash->pHashKeyBuffPtr = hhash->Init.pKey;  /* Key address                                         */
02564       hhash->pHashInBuffPtr  = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */
02565       hhash->pHashMsgBuffPtr = pInBuffer;         /* Input data address                                  */
02566       hhash->HashBuffSize = Size;                 /* input data size (in bytes)                          */
02567
02568       /* Set DMA input parameters */
02569       inputaddr = (uint32_t)(hhash->Init.pKey);   /* Address passed to DMA (start by entering Key message) */
02570       inputSize = hhash->Init.KeySize;            /* Size for first DMA transfer (in bytes) */
02571
02572       /* Configure the number of valid bits in last word of the key */
02573       __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
02574
02575       /* Set the phase to Step 1 */
02576       hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
02577
02578     }
02579       else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
02580     {
02581       /* Process a new input data message in case of multi-buffer HMAC processing
02582         (this is not a resumption case) */
02583
02584       /* Change the HASH state */
02585       hhash->State = HAL_HASH_STATE_BUSY;
02586
02587       /* Save input parameters to be able to manage possible suspension/resumption */
02588         hhash->HashInCount = Size;                /* Input message address       */
02589         hhash->pHashInBuffPtr = pInBuffer;        /* Input message size in bytes */
02590
02591       /* Set DMA input parameters */
02592         inputaddr = (uint32_t)pInBuffer;           /* Input message address       */
02593         inputSize = Size;                          /* Input message size in bytes */
02594
02595       if (hhash->DigestCalculationDisable == RESET)
02596       {
02597         /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */
02598         __HAL_HASH_RESET_MDMAT();
02599         __HAL_HASH_SET_NBVALIDBITS(inputSize);
02600       }
02601     }
02602       else
02603       {
02604         /* Phase not aligned with handle READY state */
02605         __HAL_UNLOCK(hhash);
02606         /* Return function status */
02607         return HAL_ERROR;
02608       }
02609     }
02610     else
02611     {
02612        /* Resumption case (phase may be Step 1, 2 or 3) */
02613
02614       /* Change the HASH state */
02615       hhash->State = HAL_HASH_STATE_BUSY;
02616
02617       /* Set DMA input parameters at resumption location;
02618          inputaddr and inputSize are not set to the API input parameters
02619          but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the
02620          processing was suspended. */
02621       inputaddr = (uint32_t)(hhash->pHashInBuffPtr);  /* Input message address       */
02622       inputSize = hhash->HashInCount;                 /* Input message size in bytes */
02623     }
02624
02625
02626     /* Set the HASH DMA transfert complete callback */
02627     hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
02628     /* Set the DMA error callback */
02629     hhash->hdmain->XferErrorCallback = HASH_DMAError;
02630
02631     /* Enable the DMA In DMA Stream */
02632     HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (inputSize%4 ? (inputSize+3)/4:inputSize/4));
02633     /* Enable DMA requests */
02634     SET_BIT(HASH->CR, HASH_CR_DMAE);
02635
02636     /* Process Unlocked */
02637     __HAL_UNLOCK(hhash);
02638
02639     /* Return function status */
02640     return HAL_OK;
02641   }
02642   else
02643   {
02644     return HAL_BUSY;
02645   }
02646 }
02647 /**
02648   * @}
02649   */
02650
02651 /**
02652   * @}
02653   */
02654
02655 #endif /* HAL_HASH_MODULE_ENABLED */
02656 /**
02657   * @}
02658   */
02659 #endif /* HASH */
02660 /**
02661   * @}
02662   */
02663 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_hash.h Source File

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stm32h7xx_hal_hash.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_hash.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of HASH HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_HASH_H
00040 #define __STM32H7xx_HAL_HASH_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 #if defined (HASH)
00054
00055 /** @addtogroup HASH
00056   * @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060 /** @defgroup HASH_Exported_Types HASH Exported Types
00061   * @{
00062   */
00063
00064 /**
00065   * @brief  HASH Configuration Structure definition
00066   */
00067 typedef struct
00068 {
00069   uint32_t DataType;    /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit data.
00070                               This parameter can be a value of @ref HASH_Data_Type. */
00071
00072   uint32_t KeySize;     /*!< The key size is used only in HMAC operation. */
00073
00074   uint8_t* pKey;        /*!< The key is used only in HMAC operation. */
00075
00076 } HASH_InitTypeDef;
00077
00078 /**
00079   * @brief HAL State structures definition
00080   */
00081 typedef enum
00082 {
00083   HAL_HASH_STATE_RESET             = 0x00,    /*!< Peripheral is not initialized            */
00084   HAL_HASH_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
00085   HAL_HASH_STATE_BUSY              = 0x02,    /*!< Processing (hashing) is ongoing          */
00086   HAL_HASH_STATE_TIMEOUT           = 0x06,    /*!< Timeout state                            */
00087   HAL_HASH_STATE_ERROR             = 0x07,    /*!< Error state                              */
00088   HAL_HASH_STATE_SUSPENDED         = 0x08     /*!< Suspended state                          */
00089 }HAL_HASH_StateTypeDef;
00090
00091 /**
00092   * @brief HAL phase structures definition
00093   */
00094 typedef enum
00095 {
00096   HAL_HASH_PHASE_READY             = 0x01,    /*!< HASH peripheral is ready to start                    */
00097   HAL_HASH_PHASE_PROCESS           = 0x02,    /*!< HASH peripheral is in HASH processing phase          */
00098   HAL_HASH_PHASE_HMAC_STEP_1       = 0x03,    /*!< HASH peripheral is in HMAC step 1 processing phase
00099                                               (step 1 consists in entering the inner hash function key) */
00100   HAL_HASH_PHASE_HMAC_STEP_2       = 0x04,    /*!< HASH peripheral is in HMAC step 2 processing phase
00101                                               (step 2 consists in entering the message text) */
00102   HAL_HASH_PHASE_HMAC_STEP_3       = 0x05     /*!< HASH peripheral is in HMAC step 3 processing phase
00103                                               (step 3 consists in entering the outer hash function key) */
00104 }HAL_HASH_PhaseTypeDef;
00105
00106 /**
00107   * @brief HAL HASH mode suspend definitions
00108   */
00109 typedef enum
00110 {
00111   HAL_HASH_SUSPEND_NONE            = 0x00,    /*!< HASH peripheral suspension not requested */
00112   HAL_HASH_SUSPEND                 = 0x01     /*!< HASH peripheral suspension is requested  */
00113 }HAL_HASH_SuspendTypeDef;
00114
00115
00116 /**
00117   * @brief  HASH Handle Structure definition
00118   */
00119 typedef struct
00120 {
00121   HASH_InitTypeDef           Init;             /*!< HASH required parameters */
00122
00123   uint8_t                    *pHashInBuffPtr;  /*!< Pointer to input buffer */
00124
00125   uint8_t                    *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */
00126
00127   uint8_t                    *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */
00128
00129   uint8_t                    *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
00130
00131   uint32_t                    HashBuffSize;    /*!< Size of buffer to be processed */
00132
00133   __IO uint32_t               HashInCount;      /*!< Counter of inputted data */
00134
00135   __IO uint32_t               HashITCounter;    /*!< Counter of issued interrupts */
00136
00137   __IO uint32_t               HashKeyCount;     /*!< Counter for Key inputted data (HMAC only) */
00138
00139   HAL_StatusTypeDef          Status;           /*!< HASH peripheral status   */
00140
00141   HAL_HASH_PhaseTypeDef       Phase;            /*!< HASH peripheral phase   */
00142
00143   DMA_HandleTypeDef          *hdmain;          /*!< HASH In DMA Handle parameters */
00144
00145   HAL_LockTypeDef            Lock;             /*!< Locking object */
00146
00147   __IO HAL_HASH_StateTypeDef  State;            /*!< HASH peripheral state */
00148
00149   HAL_HASH_SuspendTypeDef      SuspendRequest;   /*!< HASH peripheral suspension request flag */
00150
00151   FlagStatus                 DigestCalculationDisable;   /*!< Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation */
00152
00153 } HASH_HandleTypeDef;
00154
00155 /**
00156   * @}
00157   */
00158
00159 /* Exported constants --------------------------------------------------------*/
00160
00161 /** @defgroup HASH_Exported_Constants  HASH Exported Constants
00162   * @{
00163   */
00164
00165 /** @defgroup HASH_Algo_Selection   HASH algorithm selection
00166   * @{
00167   */
00168 #define HASH_ALGOSELECTION_SHA1      ((uint32_t)0x0000) /*!< HASH function is SHA1   */
00169 #define HASH_ALGOSELECTION_SHA224    HASH_CR_ALGO_1     /*!< HASH function is SHA224 */
00170 #define HASH_ALGOSELECTION_SHA256    HASH_CR_ALGO       /*!< HASH function is SHA256 */
00171 #define HASH_ALGOSELECTION_MD5       HASH_CR_ALGO_0     /*!< HASH function is MD5    */
00172 /**
00173   * @}
00174   */
00175
00176 /** @defgroup HASH_Algorithm_Mode   HASH algorithm mode
00177   * @{
00178   */
00179 #define HASH_ALGOMODE_HASH         ((uint32_t)0x00000000) /*!< Algorithm is HASH */
00180 #define HASH_ALGOMODE_HMAC         HASH_CR_MODE           /*!< Algorithm is HMAC */
00181 /**
00182   * @}
00183   */
00184
00185 /** @defgroup HASH_Data_Type      HASH input data type
00186   * @{
00187   */
00188 #define HASH_DATATYPE_32B          ((uint32_t)0x0000) /*!< 32-bit data. No swapping                     */
00189 #define HASH_DATATYPE_16B          HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped       */
00190 #define HASH_DATATYPE_8B           HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped            */
00191 #define HASH_DATATYPE_1B           HASH_CR_DATATYPE   /*!< 1-bit data. In the word all bits are swapped */
00192 /**
00193   * @}
00194   */
00195
00196 /** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode   HMAC key length type
00197   * @{
00198   */
00199 #define HASH_HMAC_KEYTYPE_SHORTKEY      ((uint32_t)0x00000000) /*!< HMAC Key size is <= 64 bytes */
00200 #define HASH_HMAC_KEYTYPE_LONGKEY       HASH_CR_LKEY           /*!< HMAC Key size is > 64 bytes  */
00201 /**
00202   * @}
00203   */
00204
00205 /** @defgroup HASH_flags_definition  HASH flags definitions
00206   * @{
00207   */
00208 #define HASH_FLAG_DINIS            HASH_SR_DINIS  /*!< 16 locations are free in the DIN : a new block can be entered in the IP */
00209 #define HASH_FLAG_DCIS             HASH_SR_DCIS   /*!< Digest calculation complete                                             */
00210 #define HASH_FLAG_DMAS             HASH_SR_DMAS   /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing              */
00211 #define HASH_FLAG_BUSY             HASH_SR_BUSY   /*!< The hash core is Busy, processing a block of data                       */
00212 #define HASH_FLAG_DINNE            HASH_CR_DINNE  /*!< DIN not empty : the input buffer contains at least one word of data     */
00213
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup HASH_interrupts_definition   HASH interrupts definitions
00219   * @{
00220   */
00221 #define HASH_IT_DINI               HASH_IMR_DINIE  /*!< A new block can be entered into the input buffer (DIN) */
00222 #define HASH_IT_DCI                HASH_IMR_DCIE   /*!< Digest calculation complete                            */
00223
00224 /**
00225   * @}
00226   */
00227
00228 /** @defgroup HASH_alias HASH API alias
00229   * @{
00230   */
00231 #define HAL_HASHEx_IRQHandler   HAL_HASH_IRQHandler  /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */
00232 /**
00233   * @}
00234   */
00235
00236
00237
00238 /**
00239   * @}
00240   */
00241
00242 /* Exported macros -----------------------------------------------------------*/
00243 /** @defgroup HASH_Exported_Macros HASH Exported Macros
00244   * @{
00245   */
00246
00247 /** @brief  Check whether or not the specified HASH flag is set.
00248   * @param  __FLAG__: specifies the flag to check.
00249   *        This parameter can be one of the following values:
00250   *            @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
00251   *            @arg @ref HASH_FLAG_DCIS Digest calculation complete.
00252   *            @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
00253   *            @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
00254   *            @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
00255   * @retval The new state of __FLAG__ (TRUE or FALSE).
00256   */
00257 #define __HAL_HASH_GET_FLAG(__FLAG__)  (((__FLAG__) > 8U)  ?                    \
00258                                        ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
00259                                        ((HASH->SR & (__FLAG__)) == (__FLAG__)) )
00260
00261
00262 /** @brief  Clear the specified HASH flag.
00263   * @param  __FLAG__: specifies the flag to clear.
00264   *        This parameter can be one of the following values:
00265   *            @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
00266   *            @arg @ref HASH_FLAG_DCIS Digest calculation complete
00267   * @retval None
00268   */
00269 #define __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__))
00270
00271
00272 /** @brief  Enable the specified HASH interrupt.
00273   * @param  __INTERRUPT__: specifies the HASH interrupt source to enable.
00274   *          This parameter can be one of the following values:
00275   *            @arg @ref HASH_IT_DINI  A new block can be entered into the input buffer (DIN)
00276   *            @arg @ref HASH_IT_DCI   Digest calculation complete
00277   * @retval None
00278   */
00279 #define __HAL_HASH_ENABLE_IT(__INTERRUPT__)   SET_BIT(HASH->IMR, (__INTERRUPT__))
00280
00281 /** @brief  Disable the specified HASH interrupt.
00282   * @param  __INTERRUPT__: specifies the HASH interrupt source to disable.
00283   *          This parameter can be one of the following values:
00284   *            @arg @ref HASH_IT_DINI  A new block can be entered into the input buffer (DIN)
00285   *            @arg @ref HASH_IT_DCI   Digest calculation complete
00286   * @retval None
00287   */
00288 #define __HAL_HASH_DISABLE_IT(__INTERRUPT__)   CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
00289
00290 /** @brief Reset HASH handle state.
00291   * @param  __HANDLE__: HASH handle.
00292   * @retval None
00293   */
00294 #define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
00295
00296 /** @brief Reset HASH handle status.
00297   * @param  __HANDLE__: HASH handle.
00298   * @retval None
00299   */
00300 #define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
00301
00302 /**
00303   * @brief  Enable the multi-buffer DMA transfer mode.
00304   * @note   This bit is set when hashing large files when multiple DMA transfers are needed.
00305   * @retval None
00306   */
00307 #define __HAL_HASH_SET_MDMAT()          SET_BIT(HASH->CR, HASH_CR_MDMAT)
00308
00309 /**
00310   * @brief  Disable the multi-buffer DMA transfer mode.
00311   * @retval None
00312   */
00313 #define __HAL_HASH_RESET_MDMAT()        CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)
00314
00315
00316
00317 /**
00318   * @brief Start the digest computation.
00319   * @retval None
00320   */
00321 #define __HAL_HASH_START_DIGEST()       SET_BIT(HASH->STR, HASH_STR_DCAL)
00322
00323 /**
00324   * @brief Set the number of valid bits in the last word written in data register DIN.
00325   * @param  __SIZE__: size in bytes of last data written in Data register.
00326   * @retval None
00327 */
00328 #define  __HAL_HASH_SET_NBVALIDBITS(__SIZE__)    MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * ((__SIZE__) % 4))
00329
00330 /**
00331   * @brief Reset the HASH core.
00332   * @retval None
00333   */
00334 #define __HAL_HASH_INIT()       SET_BIT(HASH->CR, HASH_CR_INIT)
00335
00336 /**
00337   * @}
00338   */
00339
00340
00341 /* Private macros --------------------------------------------------------*/
00342 /** @defgroup HASH_Private_Macros   HASH Private Macros
00343   * @{
00344   */
00345
00346 /**
00347   * @brief  Return digest length in bytes.
00348   * @retval Digest length
00349   */
00350 #define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1)   ?  20 : \
00351                              ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ?  28 : \
00352                              ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ?  32 : 16 ) ) )
00353
00354 /**
00355   * @brief  Return number of words already pushed in the FIFO.
00356   * @retval Number of words already pushed in the FIFO
00357   */
00358 #define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8)
00359
00360 /**
00361   * @brief Ensure that HASH input data type is valid.
00362   * @param __DATATYPE__: HASH input data type.
00363   * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
00364   */
00365 #define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
00366                                         ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
00367                                         ((__DATATYPE__) == HASH_DATATYPE_8B) || \
00368                                         ((__DATATYPE__) == HASH_DATATYPE_1B))
00369
00370
00371
00372 /**
00373   * @brief Ensure that input data buffer size is valid for multi-buffer HASH
00374   *        processing in polling mode.
00375   * @note  This check is valid only for multi-buffer HASH processing in polling mode.
00376   * @param __SIZE__: input data buffer size.
00377   * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
00378   */
00379 #define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__)  (((__SIZE__) % 4) == 0)
00380
00381 /**
00382   * @brief Ensure that input data buffer size is valid for multi-buffer HASH
00383   *        processing in DMA mode.
00384   * @note  This check is valid only for multi-buffer HASH processing in DMA mode.
00385   * @param __SIZE__: input data buffer size.
00386   * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
00387   */
00388 #define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__)  ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == RESET) || (((__SIZE__) % 4) == 0))
00389
00390 /**
00391   * @brief Ensure that input data buffer size is valid for multi-buffer HMAC
00392   *        processing in DMA mode.
00393   * @note  This check is valid only for multi-buffer HMAC processing in DMA mode.
00394   * @param __HANDLE__: HASH handle.
00395   * @param __SIZE__: input data buffer size.
00396   * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
00397   */
00398 #define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__)  ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4) == 0))
00399
00400 /**
00401   * @brief Ensure that handle phase is set to HASH processing.
00402   * @param __HANDLE__: HASH handle.
00403   * @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)
00404   */
00405 #define IS_HASH_PROCESSING(__HANDLE__)  ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
00406
00407 /**
00408   * @brief Ensure that handle phase is set to HMAC processing.
00409   * @param __HANDLE__: HASH handle.
00410   * @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)
00411   */
00412 #define IS_HMAC_PROCESSING(__HANDLE__)  (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
00413                                          ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \
00414                                          ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
00415
00416 /**
00417   * @}
00418   */
00419
00420
00421 /* Include HASH HAL Extended module */
00422 #include "stm32h7xx_hal_hash_ex.h"
00423 /* Exported functions --------------------------------------------------------*/
00424
00425 /** @addtogroup HASH_Exported_Functions HASH Exported Functions
00426   * @{
00427   */
00428
00429 /** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
00430   * @{
00431   */
00432
00433 /* Initialization/de-initialization methods  **********************************/
00434 HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
00435 HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
00436 void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
00437 void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
00438 void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
00439 void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
00440 void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
00441
00442 /**
00443   * @}
00444   */
00445
00446 /** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
00447   * @{
00448   */
00449
00450
00451 /* HASH processing using polling  *********************************************/
00452 HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00453 HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00454 HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00455 HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00456
00457 /**
00458   * @}
00459   */
00460
00461 /** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
00462   * @{
00463   */
00464
00465 /* HASH processing using IT  **************************************************/
00466 HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00467 HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00468 void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
00469 /**
00470   * @}
00471   */
00472
00473 /** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
00474   * @{
00475   */
00476
00477 /* HASH processing using DMA  *************************************************/
00478 HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00479 HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
00480 HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00481 HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
00482
00483 /**
00484   * @}
00485   */
00486
00487 /** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
00488   * @{
00489   */
00490
00491 /* HASH-MAC processing using polling  *****************************************/
00492 HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00493 HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00494
00495 /**
00496   * @}
00497   */
00498
00499 /** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
00500   * @{
00501   */
00502
00503 HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00504 HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00505
00506 /**
00507   * @}
00508   */
00509
00510 /** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
00511   * @{
00512   */
00513
00514 /* HASH-HMAC processing using DMA  ********************************************/
00515 HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00516 HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00517
00518 /**
00519   * @}
00520   */
00521
00522 /** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions
00523   * @{
00524   */
00525
00526
00527 /* Peripheral State methods  **************************************************/
00528 HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
00529 HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
00530 void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
00531 void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
00532 void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
00533 HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
00534
00535 /**
00536   * @}
00537   */
00538
00539 /**
00540   * @}
00541   */
00542
00543 /* Private functions -----------------------------------------------------------*/
00544
00545 /** @addtogroup HASH_Private_Functions HASH Private Functions
00546   * @{
00547   */
00548
00549 /* Private functions */
00550 HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
00551 HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
00552 HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
00553 HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
00554 HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
00555 HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
00556 HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
00557 HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
00558
00559 /**
00560   * @}
00561   */
00562
00563 /**
00564   * @}
00565   */
00566 #endif /* HASH */
00567 /**
00568   * @}
00569   */
00570
00571
00572 #ifdef __cplusplus
00573 }
00574 #endif
00575
00576
00577 #endif /* __STM32H7xx_HAL_HASH_H */
00578
00579 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_hash_ex.c Source File

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stm32h7xx_hal_hash_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_hash_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Extended HASH HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the HASH peripheral for SHA-224 and SHA-256
00010   *          alogrithms:
00011   *           + HASH or HMAC processing in polling mode
00012   *           + HASH or HMAC processing in interrupt mode
00013   *           + HASH or HMAC processing in DMA mode
00014   *         Additionally, this file provides functions to manage HMAC
00015   *         multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224
00016   *         and SHA-256.
00017   *
00018   *
00019   @verbatim
00020  ===============================================================================
00021                      ##### HASH peripheral extended features  #####
00022  ===============================================================================
00023     [..]
00024     The SHA-224 and SHA-256 HASH and HMAC processing can be carried out exactly
00025     the same way as for SHA-1 or MD-5 algorithms.
00026     (#) Three modes are available.
00027         (##) Polling mode: processing APIs are blocking functions
00028              i.e. they process the data and wait till the digest computation is finished,
00029              e.g. HAL_HASHEx_xxx_Start()
00030         (##) Interrupt mode: processing APIs are not blocking functions
00031                 i.e. they process the data under interrupt,
00032                 e.g. HAL_HASHEx_xxx_Start_IT()
00033         (##) DMA mode: processing APIs are not blocking functions and the CPU is
00034              not used for data transfer i.e. the data transfer is ensured by DMA,
00035                 e.g. HAL_HASHEx_xxx_Start_DMA(). Note that in DMA mode, a call to
00036                 HAL_HASHEx_xxx_Finish() is then required to retrieve the digest.
00037
00038    (#)Multi-buffer processing is possible in polling and DMA mode.
00039         (##) In polling mode, only multi-buffer HASH processing is possible.
00040              API HAL_HASHEx_xxx_Accumulate() must be called for each input buffer, except for the last one.
00041              User must resort to HAL_HASHEx_xxx_Start() to enter the last one and retrieve as
00042              well the computed digest.
00043
00044         (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
00045
00046               (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
00047              From that point, each buffer can be fed to the IP thru HAL_HASHEx_xxx_Start_DMA() API.
00048              Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
00049              macro then wrap-up the HASH processing in feeding the last input buffer thru the
00050              same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to
00051              API HAL_HASHEx_xxx_Finish().
00052
00053              (+++) HMAC processing (MD-5, SHA-1, SHA-224 and SHA-256 must all resort to
00054              extended functions): after initialization, the key and the first input buffer are entered
00055              in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
00056              starts step 2.
00057              The following buffers are next entered with the API  HAL_HMACEx_xxx_Step2_DMA(). At this
00058              point, the HMAC processing is still carrying out step 2.
00059              Then, step 2 for the last input buffer and step 3 are carried out by a single call
00060              to HAL_HMACEx_xxx_Step2_3_DMA().
00061
00062              The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish() for
00063              MD-5 and SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 and SHA-256.
00064
00065
00066   @endverbatim
00067   ******************************************************************************
00068   * @attention
00069   *
00070   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00071   *
00072   * Redistribution and use in source and binary forms, with or without modification,
00073   * are permitted provided that the following conditions are met:
00074   *   1. Redistributions of source code must retain the above copyright notice,
00075   *      this list of conditions and the following disclaimer.
00076   *   2. Redistributions in binary form must reproduce the above copyright notice,
00077   *      this list of conditions and the following disclaimer in the documentation
00078   *      and/or other materials provided with the distribution.
00079   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00080   *      may be used to endorse or promote products derived from this software
00081   *      without specific prior written permission.
00082   *
00083   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00084   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00085   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00086   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00087   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00088   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00089   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00090   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00091   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00092   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00093   *
00094   ******************************************************************************
00095   */
00096
00097 /* Includes ------------------------------------------------------------------*/
00098 #include "stm32h7xx_hal.h"
00099
00100 /** @addtogroup STM32H7xx_HAL_Driver
00101   * @{
00102   */
00103
00104 #ifdef HAL_HASH_MODULE_ENABLED
00105
00106 #if defined (HASH)
00107
00108 /** @defgroup HASHEx HASHEx
00109   * @brief HASH HAL extended module driver.
00110   * @{
00111   */
00112
00113 /* Private typedef -----------------------------------------------------------*/
00114 /* Private define ------------------------------------------------------------*/
00115 /* Private functions ---------------------------------------------------------*/
00116
00117 /** @defgroup HASHEx_Exported_Functions HASH Extended Exported Functions
00118   * @{
00119   */
00120
00121
00122 /** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
00123  *  @brief   HASH extended processing functions using polling mode.
00124  *
00125 @verbatim
00126  ===============================================================================
00127                ##### Polling mode HASH extended processing functions #####
00128  ===============================================================================
00129     [..]  This section provides functions allowing to calculate in polling mode
00130           the hash value using one of the following algorithms:
00131       (+) SHA224
00132          (++) HAL_HASHEx_SHA224_Start()
00133          (++) HAL_HASHEx_SHA224_Accumulate()
00134       (+) SHA256
00135          (++) HAL_HASHEx_SHA256_Start()
00136          (++) HAL_HASHEx_SHA256_Accumulate()
00137
00138     [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
00139
00140     [..]  In case of multi-buffer HASH processing (a single digest is computed while
00141           several buffers are fed to the IP), the user can resort to successive calls
00142           to HAL_HASHEx_xxx_Accumulate() and wrap-up the digest computation by a call
00143           to HAL_HASHEx_xxx_Start().
00144
00145 @endverbatim
00146   * @{
00147   */
00148
00149
00150 /**
00151   * @brief  Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
00152   *         read the computed digest.
00153   * @note   Digest is available in pOutBuffer.
00154   * @param  hhash: HASH handle.
00155   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00156   * @param  Size: length of the input buffer in bytes.
00157   * @param  pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
00158   * @param  Timeout: Timeout value
00159   * @retval HAL status
00160   */
00161 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00162 {
00163   return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
00164 }
00165
00166 /**
00167   * @brief  If not already done, initialize the HASH peripheral in SHA224 mode then
00168   *         processes pInBuffer.
00169   * @note   Consecutive calls to HAL_HASHEx_SHA224_Accumulate() can be used to feed
00170   *         several input buffers back-to-back to the IP that will yield a single
00171   *         HASH signature once all buffers have been entered. Wrap-up of input
00172   *         buffers feeding and retrieval of digest is done by a call to
00173   *         HAL_HASHEx_SHA224_Start().
00174   * @note   Field hhash->Phase of HASH handle is tested to check whether or not
00175   *         the IP has already been initialized.
00176   * @note   Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Start()
00177   *         to read it, feeding at the same time the last input buffer to the IP.
00178   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00179   *         HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Start() is able
00180   *         to manage the ending buffer with a length in bytes not a multiple of 4.
00181   * @param  hhash: HASH handle.
00182   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00183   * @param  Size: length of the input buffer in bytes, must be a multiple of 4.
00184   * @retval HAL status
00185   */
00186 HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00187 {
00188   return  HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
00189 }
00190
00191 /**
00192   * @brief  Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
00193   *         read the computed digest.
00194   * @note   Digest is available in pOutBuffer.
00195   * @param  hhash: HASH handle.
00196   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00197   * @param  Size: length of the input buffer in bytes.
00198   * @param  pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
00199   * @param  Timeout: Timeout value
00200   * @retval HAL status
00201   */
00202 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00203 {
00204   return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
00205 }
00206
00207 /**
00208   * @brief  If not already done, initialize the HASH peripheral in SHA256 mode then
00209   *         processes pInBuffer.
00210   * @note   Consecutive calls to HAL_HASHEx_SHA256_Accumulate() can be used to feed
00211   *         several input buffers back-to-back to the IP that will yield a single
00212   *         HASH signature once all buffers have been entered. Wrap-up of input
00213   *         buffers feeding and retrieval of digest is done by a call to
00214   *         HAL_HASHEx_SHA256_Start().
00215   * @note   Field hhash->Phase of HASH handle is tested to check whether or not
00216   *         the IP has already been initialized.
00217   * @note   Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Start()
00218   *         to read it, feeding at the same time the last input buffer to the IP.
00219   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00220   *         HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Start() is able
00221   *         to manage the ending buffer with a length in bytes not a multiple of 4.
00222   * @param  hhash: HASH handle.
00223   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00224   * @param  Size: length of the input buffer in bytes, must be a multiple of 4.
00225   * @retval HAL status
00226   */
00227 HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00228 {
00229   return  HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
00230 }
00231
00232
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
00238  *  @brief   HASH extended processing functions using interrupt mode.
00239  *
00240 @verbatim
00241  ===============================================================================
00242           ##### Interruption mode HASH extended processing functions #####
00243  ===============================================================================
00244     [..]  This section provides functions allowing to calculate in interrupt mode
00245           the hash value using one of the following algorithms:
00246       (+) SHA224
00247          (++) HAL_HASHEx_SHA224_Start_IT()
00248       (+) SHA256
00249          (++) HAL_HASHEx_SHA256_Start_IT()
00250
00251 @endverbatim
00252   * @{
00253   */
00254
00255
00256 /**
00257   * @brief  Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
00258   *         read the computed digest in interruption mode.
00259   * @note   Digest is available in pOutBuffer.
00260   * @param  hhash: HASH handle.
00261   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00262   * @param  Size: length of the input buffer in bytes.
00263   * @param  pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
00264   * @retval HAL status
00265   */
00266 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
00267 {
00268   return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
00269 }
00270
00271 /**
00272   * @brief  Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
00273   *         read the computed digest in interruption mode.
00274   * @note   Digest is available in pOutBuffer.
00275   * @param  hhash: HASH handle.
00276   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00277   * @param  Size: length of the input buffer in bytes.
00278   * @param  pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
00279   * @retval HAL status
00280   */
00281 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
00282 {
00283   return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
00284 }
00285
00286 /**
00287   * @}
00288   */
00289
00290 /** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
00291  *  @brief   HASH extended processing functions using DMA mode.
00292  *
00293 @verbatim
00294  ===============================================================================
00295                 ##### DMA mode HASH extended  processing functionss #####
00296  ===============================================================================
00297     [..]  This section provides functions allowing to calculate in DMA mode
00298           the hash value using one of the following algorithms:
00299       (+) SHA224
00300          (++) HAL_HASHEx_SHA224_Start_DMA()
00301          (++) HAL_HASHEx_SHA224_Finish()
00302       (+) SHA256
00303          (++) HAL_HASHEx_SHA256_Start_DMA()
00304          (++) HAL_HASHEx_SHA256_Finish()
00305
00306     [..]  When resorting to DMA mode to enter the data in the IP, user must resort
00307           to  HAL_HASHEx_xxx_Start_DMA() then read the resulting digest with
00308           HAL_HASHEx_xxx_Finish().
00309
00310     [..]  In case of multi-buffer HASH processing, MDMAT bit must first be set before
00311           the successive calls to HAL_HASHEx_xxx_Start_DMA(). Then, MDMAT bit needs to be
00312           reset before the last call to HAL_HASHEx_xxx_Start_DMA(). Digest is finally
00313           retrieved thanks to HAL_HASHEx_xxx_Finish().
00314
00315 @endverbatim
00316   * @{
00317   */
00318
00319
00320
00321
00322 /**
00323   * @brief  Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer
00324   *         to feed the input buffer to the IP.
00325   * @note   Once the DMA transfer is finished, HAL_HASHEx_SHA224_Finish() API must
00326   *         be called to retrieve the computed digest.
00327   * @param  hhash: HASH handle.
00328   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00329   * @param  Size: length of the input buffer in bytes.
00330   * @retval HAL status
00331   */
00332 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00333 {
00334   return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
00335 }
00336
00337 /**
00338   * @brief  Return the computed digest in SHA224 mode.
00339   * @note   The API waits for DCIS to be set then reads the computed digest.
00340   * @note   HAL_HASHEx_SHA224_Finish() can be used as well to retrieve the digest in
00341   *         HMAC SHA224 mode.
00342   * @param  hhash: HASH handle.
00343   * @param  pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
00344   * @param  Timeout: Timeout value.
00345   * @retval HAL status
00346   */
00347 HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
00348 {
00349    return HASH_Finish(hhash, pOutBuffer, Timeout);
00350 }
00351
00352 /**
00353   * @brief  Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer
00354   *         to feed the input buffer to the IP.
00355   * @note   Once the DMA transfer is finished, HAL_HASHEx_SHA256_Finish() API must
00356   *         be called to retrieve the computed digest.
00357   * @param  hhash: HASH handle.
00358   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00359   * @param  Size: length of the input buffer in bytes.
00360   * @retval HAL status
00361   */
00362 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00363 {
00364   return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
00365 }
00366
00367 /**
00368   * @brief  Return the computed digest in SHA256 mode.
00369   * @note   The API waits for DCIS to be set then reads the computed digest.
00370   * @note   HAL_HASHEx_SHA256_Finish() can be used as well to retrieve the digest in
00371   *         HMAC SHA256 mode.
00372   * @param  hhash: HASH handle.
00373   * @param  pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
00374   * @param  Timeout: Timeout value.
00375   * @retval HAL status
00376   */
00377 HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
00378 {
00379    return HASH_Finish(hhash, pOutBuffer, Timeout);
00380 }
00381
00382 /**
00383   * @}
00384   */
00385
00386 /** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
00387  *  @brief   HMAC extended processing functions using polling mode.
00388  *
00389 @verbatim
00390  ===============================================================================
00391              ##### Polling mode HMAC extended processing functions #####
00392  ===============================================================================
00393     [..]  This section provides functions allowing to calculate in polling mode
00394           the HMAC value using one of the following algorithms:
00395       (+) SHA224
00396          (++) HAL_HMACEx_SHA224_Start()
00397       (+) SHA256
00398          (++) HAL_HMACEx_SHA256_Start()
00399
00400 @endverbatim
00401   * @{
00402   */
00403
00404
00405
00406 /**
00407   * @brief  Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
00408   *         read the computed digest.
00409   * @note   Digest is available in pOutBuffer.
00410   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00411   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00412   * @param  hhash: HASH handle.
00413   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00414   * @param  Size: length of the input buffer in bytes.
00415   * @param  pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
00416   * @param  Timeout: Timeout value.
00417   * @retval HAL status
00418   */
00419 HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00420 {
00421   return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
00422 }
00423
00424 /**
00425   * @brief  Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then
00426   *         read the computed digest.
00427   * @note   Digest is available in pOutBuffer.
00428   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00429   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00430   * @param  hhash: HASH handle.
00431   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00432   * @param  Size: length of the input buffer in bytes.
00433   * @param  pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
00434   * @param  Timeout: Timeout value.
00435   * @retval HAL status
00436   */
00437 HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00438 {
00439   return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
00440 }
00441
00442 /**
00443   * @}
00444   */
00445
00446
00447 /** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
00448  *  @brief   HMAC extended processing functions using interruption mode.
00449  *
00450 @verbatim
00451  ===============================================================================
00452              ##### Interrupt mode HMAC extended processing functions #####
00453  ===============================================================================
00454     [..]  This section provides functions allowing to calculate in interrupt mode
00455           the HMAC value using one of the following algorithms:
00456       (+) SHA224
00457          (++) HAL_HMACEx_SHA224_Start_IT()
00458       (+) SHA256
00459          (++) HAL_HMACEx_SHA256_Start_IT()
00460
00461 @endverbatim
00462   * @{
00463   */
00464
00465
00466
00467 /**
00468   * @brief  Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
00469   *         read the computed digest in interrupt mode.
00470   * @note   Digest is available in pOutBuffer.
00471   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00472   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00473   * @param  hhash: HASH handle.
00474   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00475   * @param  Size: length of the input buffer in bytes.
00476   * @param  pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
00477   * @retval HAL status
00478   */
00479 HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
00480 {
00481   return  HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
00482 }
00483
00484 /**
00485   * @brief  Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then
00486   *         read the computed digest in interrupt mode.
00487   * @note   Digest is available in pOutBuffer.
00488   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00489   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00490   * @param  hhash: HASH handle.
00491   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00492   * @param  Size: length of the input buffer in bytes.
00493   * @param  pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
00494   * @retval HAL status
00495   */
00496 HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
00497 {
00498   return  HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
00499 }
00500
00501
00502
00503
00504 /**
00505   * @}
00506   */
00507
00508
00509 /** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
00510  *  @brief   HMAC extended processing functions using DMA mode.
00511  *
00512 @verbatim
00513  ===============================================================================
00514               ##### DMA mode HMAC extended processing functions #####
00515  ===============================================================================
00516     [..]  This section provides functions allowing to calculate in DMA mode
00517           the HMAC value using one of the following algorithms:
00518       (+) SHA224
00519          (++) HAL_HMACEx_SHA224_Start_DMA()
00520       (+) SHA256
00521          (++) HAL_HMACEx_SHA256_Start_DMA()
00522
00523     [..]  When resorting to DMA mode to enter the data in the IP for HMAC processing,
00524           user must resort to  HAL_HMACEx_xxx_Start_DMA() then read the resulting digest
00525           with HAL_HASHEx_xxx_Finish().
00526
00527
00528 @endverbatim
00529   * @{
00530   */
00531
00532
00533
00534 /**
00535   * @brief  Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
00536   *         DMA transfers to feed the key and the input buffer to the IP.
00537   * @note   Once the DMA transfers are finished (indicated by hhash->State set back
00538   *         to HAL_HASH_STATE_READY), HAL_HASHEx_SHA224_Finish() API must be called to retrieve
00539   *         the computed digest.
00540   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00541   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00542   * @note   If MDMAT bit is set before calling this function (multi-buffer
00543   *          HASH processing case), the input buffer size (in bytes) must be
00544   *          a multiple of 4 otherwise, the HASH digest computation is corrupted.
00545   *          For the processing of the last buffer of the thread, MDMAT bit must
00546   *          be reset and the buffer length (in bytes) doesn't have to be a
00547   *          multiple of 4.
00548   * @param  hhash: HASH handle.
00549   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00550   * @param  Size: length of the input buffer in bytes.
00551   * @retval HAL status
00552   */
00553 HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00554 {
00555   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
00556 }
00557
00558 /**
00559   * @brief  Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
00560   *         DMA transfers to feed the key and the input buffer to the IP.
00561   * @note   Once the DMA transfers are finished (indicated by hhash->State set back
00562   *         to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
00563   *         the computed digest.
00564   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00565   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00566   * @note   If MDMAT bit is set before calling this function (multi-buffer
00567   *          HASH processing case), the input buffer size (in bytes) must be
00568   *          a multiple of 4 otherwise, the HASH digest computation is corrupted.
00569   *          For the processing of the last buffer of the thread, MDMAT bit must
00570   *          be reset and the buffer length (in bytes) doesn't have to be a
00571   *          multiple of 4.
00572   * @param  hhash: HASH handle.
00573   * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
00574   * @param  Size: length of the input buffer in bytes.
00575   * @retval HAL status
00576   */
00577 HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00578 {
00579   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
00580 }
00581
00582
00583 /**
00584   * @}
00585   */
00586
00587 /** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
00588  *  @brief   HMAC extended processing functions in multi-buffer DMA mode.
00589  *
00590 @verbatim
00591  ===============================================================================
00592       ##### Multi-buffer DMA mode HMAC extended processing functions #####
00593  ===============================================================================
00594     [..]  This section provides functions to manage HMAC multi-buffer
00595           DMA-based processing for MD5, SHA1, SHA224 and SHA256 algorithms.
00596       (+) MD5
00597          (++) HAL_HMACEx_MD5_Step1_2_DMA()
00598          (++) HAL_HMACEx_MD5_Step2_DMA()
00599          (++) HAL_HMACEx_MD5_Step2_3_DMA()
00600       (+) SHA1
00601          (++) HAL_HMACEx_SHA1_Step1_2_DMA()
00602          (++) HAL_HMACEx_SHA1_Step2_DMA()
00603          (++) HAL_HMACEx_SHA1_Step2_3_DMA()
00604       (+) SHA256
00605          (++) HAL_HMACEx_SHA224_Step1_2_DMA()
00606          (++) HAL_HMACEx_SHA224_Step2_DMA()
00607          (++) HAL_HMACEx_SHA224_Step2_3_DMA()
00608       (+) SHA256
00609          (++) HAL_HMACEx_SHA256_Step1_2_DMA()
00610          (++) HAL_HMACEx_SHA256_Step2_DMA()
00611          (++) HAL_HMACEx_SHA256_Step2_3_DMA()
00612
00613     [..]  User must first start-up the multi-buffer DMA-based HMAC computation in
00614           calling HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
00615           intiates step 2 with the first input buffer.
00616
00617     [..]  The following buffers are next fed to the IP with a call to the API
00618           HAL_HMACEx_xxx_Step2_DMA(). There may be several consecutive calls
00619           to this API.
00620
00621     [..]  Multi-buffer DMA-based HMAC computation is wrapped up by a call to
00622           HAL_HMACEx_xxx_Step2_3_DMA(). This finishes step 2 in feeding the last input
00623           buffer to the IP then carries out step 3.
00624
00625     [..]  Digest is retrieved by a call to HAL_HASH_xxx_Finish() for MD-5 or
00626           SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 or SHA-256.
00627
00628     [..]  If only two buffers need to be consecutively processed, a call to
00629           HAL_HMACEx_xxx_Step1_2_DMA() followed by a call to HAL_HMACEx_xxx_Step2_3_DMA()
00630           is sufficient.
00631
00632 @endverbatim
00633   * @{
00634   */
00635
00636 /**
00637   * @brief  MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
00638   * @note   Step 1 consists in writing the inner hash function key in the IP,
00639   *         step 2 consists in writing the message text.
00640   * @note   The API carries out the HMAC step 1 then starts step 2 with
00641   *         the first buffer entered to the IP. DCAL bit is not automatically set after
00642   *         the message buffer feeding, allowing other messages DMA transfers to occur.
00643   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00644   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00645   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00646   *         HASH digest computation is corrupted.
00647   * @param  hhash: HASH handle.
00648   * @param  pInBuffer: pointer to the input buffer (message buffer).
00649   * @param  Size: length of the input buffer in bytes.
00650   * @retval HAL status
00651   */
00652 HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00653 {
00654   hhash->DigestCalculationDisable = SET;
00655   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
00656 }
00657
00658 /**
00659   * @brief  MD5 HMAC step 2 in multi-buffer DMA mode.
00660   * @note   Step 2 consists in writing the message text in the IP.
00661   * @note   The API carries on the HMAC step 2, applied to the buffer entered as input
00662   *         parameter. DCAL bit is not automatically set after the message buffer feeding,
00663   *         allowing other messages DMA transfers to occur.
00664   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00665   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00666   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00667   *         HASH digest computation is corrupted.
00668   * @param  hhash: HASH handle.
00669   * @param  pInBuffer: pointer to the input buffer (message buffer).
00670   * @param  Size: length of the input buffer in bytes.
00671   * @retval HAL status
00672   */
00673 HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00674 {
00675   if (hhash->DigestCalculationDisable != SET)
00676   {
00677     return HAL_ERROR;
00678   }
00679   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
00680 }
00681
00682 /**
00683   * @brief  MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
00684   * @note   Step 2 consists in writing the message text in the IP,
00685   *         step 3 consists in writing the outer hash function key.
00686   * @note   The API wraps up the HMAC step 2 in processing the buffer entered as input
00687   *         parameter (the input buffer must be the last one of the multi-buffer thread)
00688   *         then carries out HMAC step 3.
00689   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00690   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00691   * @note   Once the DMA transfers are finished (indicated by hhash->State set back
00692   *         to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
00693   *         the computed digest.
00694   * @param  hhash: HASH handle.
00695   * @param  pInBuffer: pointer to the input buffer (message buffer).
00696   * @param  Size: length of the input buffer in bytes.
00697   * @retval HAL status
00698   */
00699 HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00700 {
00701   hhash->DigestCalculationDisable = RESET;
00702   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
00703 }
00704
00705
00706 /**
00707   * @brief  SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
00708   * @note   Step 1 consists in writing the inner hash function key in the IP,
00709   *         step 2 consists in writing the message text.
00710   * @note   The API carries out the HMAC step 1 then starts step 2 with
00711   *         the first buffer entered to the IP. DCAL bit is not automatically set after
00712   *         the message buffer feeding, allowing other messages DMA transfers to occur.
00713   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00714   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00715   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00716   *         HASH digest computation is corrupted.
00717   * @param  hhash: HASH handle.
00718   * @param  pInBuffer: pointer to the input buffer (message buffer).
00719   * @param  Size: length of the input buffer in bytes.
00720   * @retval HAL status
00721   */
00722 HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00723 {
00724   hhash->DigestCalculationDisable = SET;
00725   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
00726 }
00727
00728 /**
00729   * @brief  SHA1 HMAC step 2 in multi-buffer DMA mode.
00730   * @note   Step 2 consists in writing the message text in the IP.
00731   * @note   The API carries on the HMAC step 2, applied to the buffer entered as input
00732   *         parameter. DCAL bit is not automatically set after the message buffer feeding,
00733   *         allowing other messages DMA transfers to occur.
00734   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00735   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00736   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00737   *         HASH digest computation is corrupted.
00738   * @param  hhash: HASH handle.
00739   * @param  pInBuffer: pointer to the input buffer (message buffer).
00740   * @param  Size: length of the input buffer in bytes.
00741   * @retval HAL status
00742   */
00743 HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00744 {
00745   if (hhash->DigestCalculationDisable != SET)
00746   {
00747     return HAL_ERROR;
00748   }
00749   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
00750 }
00751
00752 /**
00753   * @brief  SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
00754   * @note   Step 2 consists in writing the message text in the IP,
00755   *         step 3 consists in writing the outer hash function key.
00756   * @note   The API wraps up the HMAC step 2 in processing the buffer entered as input
00757   *         parameter (the input buffer must be the last one of the multi-buffer thread)
00758   *         then carries out HMAC step 3.
00759   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00760   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00761   * @note   Once the DMA transfers are finished (indicated by hhash->State set back
00762   *         to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
00763   *         the computed digest.
00764   * @param  hhash: HASH handle.
00765   * @param  pInBuffer: pointer to the input buffer (message buffer).
00766   * @param  Size: length of the input buffer in bytes.
00767   * @retval HAL status
00768   */
00769 HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00770 {
00771   hhash->DigestCalculationDisable = RESET;
00772   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
00773 }
00774
00775 /**
00776   * @brief  SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
00777   * @note   Step 1 consists in writing the inner hash function key in the IP,
00778   *         step 2 consists in writing the message text.
00779   * @note   The API carries out the HMAC step 1 then starts step 2 with
00780   *         the first buffer entered to the IP. DCAL bit is not automatically set after
00781   *         the message buffer feeding, allowing other messages DMA transfers to occur.
00782   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00783   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00784   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00785   *         HASH digest computation is corrupted.
00786   * @param  hhash: HASH handle.
00787   * @param  pInBuffer: pointer to the input buffer (message buffer).
00788   * @param  Size: length of the input buffer in bytes.
00789   * @retval HAL status
00790   */
00791 HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00792 {
00793   hhash->DigestCalculationDisable = SET;
00794   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
00795 }
00796
00797 /**
00798   * @brief  SHA224 HMAC step 2 in multi-buffer DMA mode.
00799   * @note   Step 2 consists in writing the message text in the IP.
00800   * @note   The API carries on the HMAC step 2, applied to the buffer entered as input
00801   *         parameter. DCAL bit is not automatically set after the message buffer feeding,
00802   *         allowing other messages DMA transfers to occur.
00803   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00804   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00805   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00806   *         HASH digest computation is corrupted.
00807   * @param  hhash: HASH handle.
00808   * @param  pInBuffer: pointer to the input buffer (message buffer).
00809   * @param  Size: length of the input buffer in bytes.
00810   * @retval HAL status
00811   */
00812 HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00813 {
00814   if (hhash->DigestCalculationDisable != SET)
00815   {
00816     return HAL_ERROR;
00817   }
00818   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
00819 }
00820
00821 /**
00822   * @brief  SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
00823   * @note   Step 2 consists in writing the message text in the IP,
00824   *         step 3 consists in writing the outer hash function key.
00825   * @note   The API wraps up the HMAC step 2 in processing the buffer entered as input
00826   *         parameter (the input buffer must be the last one of the multi-buffer thread)
00827   *         then carries out HMAC step 3.
00828   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00829   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00830   * @note   Once the DMA transfers are finished (indicated by hhash->State set back
00831   *         to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
00832   *         the computed digest.
00833   * @param  hhash: HASH handle.
00834   * @param  pInBuffer: pointer to the input buffer (message buffer).
00835   * @param  Size: length of the input buffer in bytes.
00836   * @retval HAL status
00837   */
00838 HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00839 {
00840   hhash->DigestCalculationDisable = RESET;
00841   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
00842 }
00843
00844 /**
00845   * @brief  SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
00846   * @note   Step 1 consists in writing the inner hash function key in the IP,
00847   *         step 2 consists in writing the message text.
00848   * @note   The API carries out the HMAC step 1 then starts step 2 with
00849   *         the first buffer entered to the IP. DCAL bit is not automatically set after
00850   *         the message buffer feeding, allowing other messages DMA transfers to occur.
00851   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00852   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00853   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00854   *         HASH digest computation is corrupted.
00855   * @param  hhash: HASH handle.
00856   * @param  pInBuffer: pointer to the input buffer (message buffer).
00857   * @param  Size: length of the input buffer in bytes.
00858   * @retval HAL status
00859   */
00860 HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00861 {
00862   hhash->DigestCalculationDisable = SET;
00863   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
00864 }
00865
00866 /**
00867   * @brief  SHA256 HMAC step 2 in multi-buffer DMA mode.
00868   * @note   Step 2 consists in writing the message text in the IP.
00869   * @note   The API carries on the HMAC step 2, applied to the buffer entered as input
00870   *         parameter. DCAL bit is not automatically set after the message buffer feeding,
00871   *         allowing other messages DMA transfers to occur.
00872   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00873   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00874   * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
00875   *         HASH digest computation is corrupted.
00876   * @param  hhash: HASH handle.
00877   * @param  pInBuffer: pointer to the input buffer (message buffer).
00878   * @param  Size: length of the input buffer in bytes.
00879   * @retval HAL status
00880   */
00881 HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00882 {
00883   if (hhash->DigestCalculationDisable != SET)
00884   {
00885     return HAL_ERROR;
00886   }
00887   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
00888 }
00889
00890 /**
00891   * @brief  SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
00892   * @note   Step 2 consists in writing the message text in the IP,
00893   *         step 3 consists in writing the outer hash function key.
00894   * @note   The API wraps up the HMAC step 2 in processing the buffer entered as input
00895   *         parameter (the input buffer must be the last one of the multi-buffer thread)
00896   *         then carries out HMAC step 3.
00897   * @note   Same key is used for the inner and the outer hash functions; pointer to key and
00898   *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
00899   * @note   Once the DMA transfers are finished (indicated by hhash->State set back
00900   *         to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
00901   *         the computed digest.
00902   * @param  hhash: HASH handle.
00903   * @param  pInBuffer: pointer to the input buffer (message buffer).
00904   * @param  Size: length of the input buffer in bytes.
00905   * @retval HAL status
00906   */
00907 HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00908 {
00909   hhash->DigestCalculationDisable = RESET;
00910   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
00911 }
00912
00913 /**
00914   * @}
00915   */
00916
00917
00918 /**
00919   * @}
00920   */
00921
00922 /**
00923   * @}
00924   */
00925 #endif /* HASH */
00926
00927 #endif /* HAL_HASH_MODULE_ENABLED */
00928 /**
00929   * @}
00930   */
00931
00932 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_hash_ex.h Source File

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stm32h7xx_hal_hash_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_hash_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of HASH HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_HASH_EX_H
00040 #define __STM32H7xx_HAL_HASH_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053  #if defined (HASH)
00054
00055 /** @addtogroup HASHEx
00056   * @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060 /* Exported constants --------------------------------------------------------*/
00061 /* Exported macro ------------------------------------------------------------*/
00062
00063
00064 /* Exported functions --------------------------------------------------------*/
00065
00066 /** @addtogroup HASHEx_Exported_Functions HASH Extended Exported Functions
00067   * @{
00068   */
00069
00070 /** @addtogroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
00071   * @{
00072   */
00073
00074 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00075 HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00076 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00077 HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00078
00079 /**
00080   * @}
00081   */
00082
00083 /** @addtogroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
00084   * @{
00085   */
00086
00087 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00088 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00089
00090 /**
00091   * @}
00092   */
00093
00094 /** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
00095   * @{
00096   */
00097 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00098 HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
00099 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00100 HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
00101
00102 /**
00103   * @}
00104   */
00105
00106 /** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
00107   * @{
00108   */
00109 HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00110 HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00111 /**
00112   * @}
00113   */
00114
00115 /** @addtogroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
00116   * @{
00117   */
00118
00119 HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00120 HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00121
00122 /**
00123   * @}
00124   */
00125
00126 /** @addtogroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
00127   * @{
00128   */
00129
00130 HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00131 HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00132
00133 /**
00134   * @}
00135   */
00136
00137 /** @addtogroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
00138   * @{
00139   */
00140
00141 HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00142 HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00143 HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00144
00145 HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00146 HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00147 HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00148
00149 HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00150 HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00151 HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00152
00153 HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00154 HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00155 HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00156
00157 /**
00158   * @}
00159   */
00160
00161 /**
00162   * @}
00163   */
00164
00165 /**
00166   * @}
00167   */
00168 #endif /* HASH */
00169 /**
00170   * @}
00171   */
00172
00173 #ifdef __cplusplus
00174 }
00175 #endif
00176
00177 #endif /* __STM32H7xx_HAL_HASH_EX_H */
00178
00179 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_hcd.c Source File

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stm32h7xx_hal_hcd.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_hcd.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   HCD HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the USB Peripheral Controller:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                     ##### How to use this driver #####
00018   ==============================================================================
00019   [..]
00020     (#)Declare a HCD_HandleTypeDef handle structure, for example:
00021        HCD_HandleTypeDef  hhcd;
00022
00023     (#)Fill parameters of Init structure in HCD handle
00024
00025     (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
00026
00027     (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
00028         (##) Enable the HCD/USB Low Level interface clock using the following macros
00029              (+++) __OTGFS-OTG_CLK_ENABLE() or __OTGHS-OTG_CLK_ENABLE()
00030              (+++) __OTGHSULPI_CLK_ENABLE() For High Speed Mode
00031
00032         (##) Initialize the related GPIO clocks
00033         (##) Configure HCD pin-out
00034         (##) Configure HCD NVIC interrupt
00035
00036     (#)Associate the Upper USB Host stack to the HAL HCD Driver:
00037         (##) hhcd.pData = phost;
00038
00039     (#)Enable HCD transmission and reception:
00040         (##) HAL_HCD_Start();
00041
00042   @endverbatim
00043   ******************************************************************************
00044   * @attention
00045   *
00046   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00047   *
00048   * Redistribution and use in source and binary forms, with or without modification,
00049   * are permitted provided that the following conditions are met:
00050   *   1. Redistributions of source code must retain the above copyright notice,
00051   *      this list of conditions and the following disclaimer.
00052   *   2. Redistributions in binary form must reproduce the above copyright notice,
00053   *      this list of conditions and the following disclaimer in the documentation
00054   *      and/or other materials provided with the distribution.
00055   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00056   *      may be used to endorse or promote products derived from this software
00057   *      without specific prior written permission.
00058   *
00059   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00060   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00061   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00062   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00063   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00064   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00065   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00066   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00067   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00068   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00069   *
00070   ******************************************************************************
00071   */
00072
00073 /* Includes ------------------------------------------------------------------*/
00074 #include "stm32h7xx_hal.h"
00075
00076 /** @addtogroup STM32H7xx_HAL_Driver
00077   * @{
00078   */
00079
00080 /** @addtogroup HCD
00081   * @{
00082   */
00083
00084 #ifdef HAL_HCD_MODULE_ENABLED
00085
00086 /* Private typedef -----------------------------------------------------------*/
00087 /* Private define ------------------------------------------------------------*/
00088 /* Private macro -------------------------------------------------------------*/
00089 /* Private variables ---------------------------------------------------------*/
00090 /* Private function ----------------------------------------------------------*/
00091 /** @addtogroup HCD_Private_Functions
00092   * @{
00093   */
00094 static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00095 static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00096 static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);
00097 static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
00098 /**
00099   * @}
00100   */
00101
00102 /* Exported functions --------------------------------------------------------*/
00103 /** @addtogroup HCD_Exported_Functions
00104   * @{
00105   */
00106
00107 /** @addtogroup HCD_Exported_Functions_Group1
00108  *  @brief   Initialization and de-initialization functions
00109  *
00110 @verbatim
00111  ===============================================================================
00112           ##### Initialization and de-initialization functions #####
00113  ===============================================================================
00114     [..]  This section provides functions allowing to:
00115
00116 @endverbatim
00117   * @{
00118   */
00119
00120 /**
00121   * @brief  Initialize the host driver
00122   * @param  hhcd: HCD handle
00123   * @retval HAL status
00124   */
00125 HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
00126 {
00127   /* Check the HCD handle allocation */
00128   if(hhcd == NULL)
00129   {
00130     return HAL_ERROR;
00131   }
00132
00133   /* Check the parameters */
00134   assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
00135
00136   hhcd->State = HAL_HCD_STATE_BUSY;
00137
00138   /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00139   HAL_HCD_MspInit(hhcd);
00140
00141   /* Disable the Interrupts */
00142  __HAL_HCD_DISABLE(hhcd);
00143
00144  /*Init the Core (common init.) */
00145  USB_CoreInit(hhcd->Instance, hhcd->Init);
00146
00147  /* Force Host Mode*/
00148  USB_SetCurrentMode(hhcd->Instance , USB_OTG_HOST_MODE);
00149
00150  /* Init Host */
00151  USB_HostInit(hhcd->Instance, hhcd->Init);
00152
00153  hhcd->State= HAL_HCD_STATE_READY;
00154
00155  return HAL_OK;
00156 }
00157
00158 /**
00159   * @brief  Initialize a host channel
00160   * @param  hhcd: HCD handle
00161   * @param  ch_num: Channel number.
00162   *         This parameter can be a value from 1 to 15
00163   * @param  epnum: Endpoint number.
00164   *          This parameter can be a value from 1 to 15
00165   * @param  dev_address : Current device address
00166   *          This parameter can be a value from 0 to 255
00167   * @param  speed: Current device speed.
00168   *          This parameter can be one of these values:
00169   *            HCD_SPEED_HIGH: High speed mode,
00170   *            HCD_SPEED_FULL: Full speed mode,
00171   *            HCD_SPEED_LOW: Low speed mode
00172   * @param  ep_type: Endpoint Type.
00173   *          This parameter can be one of these values:
00174   *            EP_TYPE_CTRL: Control type,
00175   *            EP_TYPE_ISOC: Isochronous type,
00176   *            EP_TYPE_BULK: Bulk type,
00177   *            EP_TYPE_INTR: Interrupt type
00178   * @param  mps: Max Packet Size.
00179   *          This parameter can be a value from 0 to32K
00180   * @retval HAL status
00181   */
00182 HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
00183                                   uint8_t ch_num,
00184                                   uint8_t epnum,
00185                                   uint8_t dev_address,
00186                                   uint8_t speed,
00187                                   uint8_t ep_type,
00188                                   uint16_t mps)
00189 {
00190   HAL_StatusTypeDef status = HAL_OK;
00191
00192   __HAL_LOCK(hhcd);
00193
00194   hhcd->hc[ch_num].dev_addr = dev_address;
00195   hhcd->hc[ch_num].max_packet = mps;
00196   hhcd->hc[ch_num].ch_num = ch_num;
00197   hhcd->hc[ch_num].ep_type = ep_type;
00198   hhcd->hc[ch_num].ep_num = epnum & 0x7F;
00199   hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80);
00200   hhcd->hc[ch_num].speed = speed;
00201
00202   status =  USB_HC_Init(hhcd->Instance,
00203                         ch_num,
00204                         epnum,
00205                         dev_address,
00206                         speed,
00207                         ep_type,
00208                         mps);
00209   __HAL_UNLOCK(hhcd);
00210
00211   return status;
00212 }
00213
00214 /**
00215   * @brief  Halt a host channel
00216   * @param  hhcd: HCD handle
00217   * @param  ch_num: Channel number.
00218   *         This parameter can be a value from 1 to 15
00219   * @retval HAL status
00220   */
00221 HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
00222 {
00223   HAL_StatusTypeDef status = HAL_OK;
00224
00225   __HAL_LOCK(hhcd);
00226   USB_HC_Halt(hhcd->Instance, ch_num);
00227   __HAL_UNLOCK(hhcd);
00228
00229   return status;
00230 }
00231
00232 /**
00233   * @brief  DeInitialize the host driver
00234   * @param  hhcd: HCD handle
00235   * @retval HAL status
00236   */
00237 HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
00238 {
00239   /* Check the HCD handle allocation */
00240   if(hhcd == NULL)
00241   {
00242     return HAL_ERROR;
00243   }
00244
00245   hhcd->State = HAL_HCD_STATE_BUSY;
00246
00247   /* DeInit the low level hardware */
00248   HAL_HCD_MspDeInit(hhcd);
00249
00250    __HAL_HCD_DISABLE(hhcd);
00251
00252   hhcd->State = HAL_HCD_STATE_RESET;
00253
00254   return HAL_OK;
00255 }
00256
00257 /**
00258   * @brief  Initializes the HCD MSP.
00259   * @param  hhcd: HCD handle
00260   * @retval None
00261   */
00262 __weak void  HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
00263 {
00264   /* NOTE : This function Should not be modified, when the callback is needed,
00265             the HAL_HCD_MspInit could be implemented in the user file
00266    */
00267 }
00268
00269 /**
00270   * @brief  DeInitializes HCD MSP.
00271   * @param  hhcd: HCD handle
00272   * @retval None
00273   */
00274 __weak void  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
00275 {
00276   /* NOTE : This function Should not be modified, when the callback is needed,
00277             the HAL_HCD_MspDeInit could be implemented in the user file
00278    */
00279 }
00280
00281 /**
00282   * @}
00283   */
00284
00285 /** @addtogroup HCD_Exported_Functions_Group2
00286   *  @brief   HCD IO operation functions
00287   *
00288 @verbatim
00289  ===============================================================================
00290                       ##### IO operation functions #####
00291  ===============================================================================
00292     This subsection provides a set of functions allowing to manage the USB Host Data
00293     Transfer
00294
00295 @endverbatim
00296   * @{
00297   */
00298
00299 /**
00300   * @brief  Submit a new URB for processing
00301   * @param  hhcd: HCD handle
00302   * @param  ch_num: Channel number.
00303   *         This parameter can be a value from 1 to 15
00304   * @param  direction: Channel number.
00305   *          This parameter can be one of these values:
00306   *           0 : Output / 1 : Input
00307   * @param  ep_type: Endpoint Type.
00308   *          This parameter can be one of these values:
00309   *            EP_TYPE_CTRL: Control type/
00310   *            EP_TYPE_ISOC: Isochronous type/
00311   *            EP_TYPE_BULK: Bulk type/
00312   *            EP_TYPE_INTR: Interrupt type/
00313   * @param  token: Endpoint Type.
00314   *          This parameter can be one of these values:
00315   *            0: HC_PID_SETUP / 1: HC_PID_DATA1
00316   * @param  pbuff: pointer to URB data
00317   * @param  length: Length of URB data
00318   * @param  do_ping: activate do ping protocol (for high speed only).
00319   *          This parameter can be one of these values:
00320   *           0 : do ping inactive / 1 : do ping active
00321   * @retval HAL status
00322   */
00323 HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
00324                                             uint8_t ch_num,
00325                                             uint8_t direction ,
00326                                             uint8_t ep_type,
00327                                             uint8_t token,
00328                                             uint8_t* pbuff,
00329                                             uint16_t length,
00330                                             uint8_t do_ping)
00331 {
00332   hhcd->hc[ch_num].ep_is_in = direction;
00333   hhcd->hc[ch_num].ep_type  = ep_type;
00334
00335   if(token == 0)
00336   {
00337     hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
00338   }
00339   else
00340   {
00341     hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00342   }
00343
00344   /* Manage Data Toggle */
00345   switch(ep_type)
00346   {
00347   case EP_TYPE_CTRL:
00348     if((token == 1) && (direction == 0)) /*send data */
00349     {
00350       if ( length == 0 )
00351       { /* For Status OUT stage, Length==0, Status Out PID = 1 */
00352         hhcd->hc[ch_num].toggle_out = 1;
00353       }
00354
00355       /* Set the Data Toggle bit as per the Flag */
00356       if ( hhcd->hc[ch_num].toggle_out == 0)
00357       { /* Put the PID 0 */
00358         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00359       }
00360       else
00361       { /* Put the PID 1 */
00362         hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
00363       }
00364       if(hhcd->hc[ch_num].urb_state  != URB_NOTREADY)
00365       {
00366         hhcd->hc[ch_num].do_ping = do_ping;
00367       }
00368     }
00369     break;
00370
00371   case EP_TYPE_BULK:
00372     if(direction == 0)
00373     {
00374       /* Set the Data Toggle bit as per the Flag */
00375       if ( hhcd->hc[ch_num].toggle_out == 0)
00376       { /* Put the PID 0 */
00377         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00378       }
00379       else
00380       { /* Put the PID 1 */
00381         hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
00382       }
00383       if(hhcd->hc[ch_num].urb_state  != URB_NOTREADY)
00384       {
00385         hhcd->hc[ch_num].do_ping = do_ping;
00386       }
00387     }
00388     else
00389     {
00390       if( hhcd->hc[ch_num].toggle_in == 0)
00391       {
00392         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00393       }
00394       else
00395       {
00396         hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00397       }
00398     }
00399
00400     break;
00401   case EP_TYPE_INTR:
00402     if(direction == 0)
00403     {
00404       /* Set the Data Toggle bit as per the Flag */
00405       if ( hhcd->hc[ch_num].toggle_out == 0)
00406       { /* Put the PID 0 */
00407         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00408       }
00409       else
00410       { /* Put the PID 1 */
00411         hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
00412       }
00413     }
00414     else
00415     {
00416       if( hhcd->hc[ch_num].toggle_in == 0)
00417       {
00418         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00419       }
00420       else
00421       {
00422         hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00423       }
00424     }
00425     break;
00426
00427   case EP_TYPE_ISOC:
00428     hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00429     break;
00430   }
00431
00432   hhcd->hc[ch_num].xfer_buff = pbuff;
00433   hhcd->hc[ch_num].xfer_len  = length;
00434   hhcd->hc[ch_num].urb_state =   URB_IDLE;
00435   hhcd->hc[ch_num].xfer_count = 0 ;
00436   hhcd->hc[ch_num].ch_num = ch_num;
00437   hhcd->hc[ch_num].state = HC_IDLE;
00438
00439   return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]), hhcd->Init.dma_enable);
00440 }
00441
00442 /**
00443   * @brief  This function handles HCD interrupt request.
00444   * @param  hhcd: HCD handle
00445   * @retval None
00446   */
00447 void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
00448 {
00449   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
00450   uint32_t i = 0 , interrupt = 0;
00451
00452   /* ensure that we are in device mode */
00453   if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
00454   {
00455     /* avoid spurious interrupt */
00456     if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
00457     {
00458       return;
00459     }
00460
00461     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
00462     {
00463      /* incorrect mode, acknowledge the interrupt */
00464       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
00465     }
00466
00467     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
00468     {
00469      /* incorrect mode, acknowledge the interrupt */
00470       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
00471     }
00472
00473     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
00474     {
00475      /* incorrect mode, acknowledge the interrupt */
00476       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
00477     }
00478
00479     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
00480     {
00481      /* incorrect mode, acknowledge the interrupt */
00482       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
00483     }
00484
00485     /* Handle Host Disconnect Interrupts */
00486     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
00487     {
00488
00489       /* Cleanup HPRT */
00490       USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
00491         USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
00492
00493       /* Handle Host Port Interrupts */
00494       HAL_HCD_Disconnect_Callback(hhcd);
00495        USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
00496       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
00497     }
00498
00499     /* Handle Host Port Interrupts */
00500     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
00501     {
00502       HCD_Port_IRQHandler (hhcd);
00503     }
00504
00505     /* Handle Host SOF Interrupts */
00506     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
00507     {
00508       HAL_HCD_SOF_Callback(hhcd);
00509       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
00510     }
00511
00512     /* Handle Host channel Interrupts */
00513     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
00514     {
00515       interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
00516       for (i = 0; i < hhcd->Init.Host_channels ; i++)
00517       {
00518         if (interrupt & (1 << i))
00519         {
00520           if ((USBx_HC(i)->HCCHAR) &  USB_OTG_HCCHAR_EPDIR)
00521           {
00522             HCD_HC_IN_IRQHandler (hhcd, i);
00523           }
00524           else
00525           {
00526             HCD_HC_OUT_IRQHandler (hhcd, i);
00527           }
00528         }
00529       }
00530       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
00531     }
00532
00533         /* Handle Rx Queue Level Interrupts */
00534     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL))
00535     {
00536       USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00537
00538       HCD_RXQLVL_IRQHandler (hhcd);
00539
00540       USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00541     }
00542   }
00543 }
00544
00545 /**
00546   * @brief  SOF callback.
00547   * @param  hhcd: HCD handle
00548   * @retval None
00549   */
00550 __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
00551 {
00552   /* NOTE : This function Should not be modified, when the callback is needed,
00553             the HAL_HCD_SOF_Callback could be implemented in the user file
00554    */
00555 }
00556
00557 /**
00558   * @brief Connexion Event callback.
00559   * @param  hhcd: HCD handle
00560   * @retval None
00561   */
00562 __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
00563 {
00564   /* NOTE : This function Should not be modified, when the callback is needed,
00565             the HAL_HCD_Connect_Callback could be implemented in the user file
00566    */
00567 }
00568
00569 /**
00570   * @brief  Disconnexion Event callback.
00571   * @param  hhcd: HCD handle
00572   * @retval None
00573   */
00574 __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
00575 {
00576   /* NOTE : This function Should not be modified, when the callback is needed,
00577             the HAL_HCD_Disconnect_Callback could be implemented in the user file
00578    */
00579 }
00580
00581 /**
00582   * @brief  Notify URB state change callback.
00583   * @param  hhcd: HCD handle
00584   * @param  chnum: Channel number.
00585   *         This parameter can be a value from 1 to 15
00586   * @param  urb_state:
00587   *          This parameter can be one of these values:
00588   *            URB_IDLE/
00589   *            URB_DONE/
00590   *            URB_NOTREADY/
00591   *            URB_NYET/
00592   *            URB_ERROR/
00593   *            URB_STALL/
00594   * @retval None
00595   */
00596 __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
00597 {
00598   /* NOTE : This function Should not be modified, when the callback is needed,
00599             the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
00600    */
00601 }
00602
00603 /**
00604   * @}
00605   */
00606
00607 /** @addtogroup HCD_Exported_Functions_Group3
00608  *  @brief   Peripheral management functions
00609  *
00610 @verbatim
00611  ===============================================================================
00612                       ##### Peripheral Control functions #####
00613  ===============================================================================
00614     [..]
00615     This subsection provides a set of functions allowing to control the HCD data
00616     transfers.
00617
00618 @endverbatim
00619   * @{
00620   */
00621
00622 /**
00623   * @brief  Start the host driver
00624   * @param  hhcd: HCD handle
00625   * @retval HAL status
00626   */
00627 HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
00628 {
00629   __HAL_LOCK(hhcd);
00630   __HAL_HCD_ENABLE(hhcd);
00631   USB_DriveVbus(hhcd->Instance, 1);
00632   __HAL_UNLOCK(hhcd);
00633   return HAL_OK;
00634 }
00635
00636 /**
00637   * @brief  Stop the host driver
00638   * @param  hhcd: HCD handle
00639   * @retval HAL status
00640   */
00641
00642 HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
00643 {
00644   __HAL_LOCK(hhcd);
00645   USB_StopHost(hhcd->Instance);
00646   __HAL_UNLOCK(hhcd);
00647   return HAL_OK;
00648 }
00649
00650 /**
00651   * @brief  Reset the host port
00652   * @param  hhcd: HCD handle
00653   * @retval HAL status
00654   */
00655 HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
00656 {
00657   return (USB_ResetPort(hhcd->Instance));
00658 }
00659
00660 /**
00661   * @}
00662   */
00663
00664 /** @addtogroup HCD_Exported_Functions_Group4
00665  *  @brief   Peripheral State functions
00666  *
00667 @verbatim
00668  ===============================================================================
00669                       ##### Peripheral State functions #####
00670  ===============================================================================
00671     [..]
00672     This subsection permits to get in run-time the status of the peripheral
00673     and the data flow.
00674
00675 @endverbatim
00676   * @{
00677   */
00678
00679 /**
00680   * @brief  Return the HCD state
00681   * @param  hhcd: HCD handle
00682   * @retval HAL state
00683   */
00684 HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
00685 {
00686   return hhcd->State;
00687 }
00688
00689 /**
00690   * @brief  Return  URB state for a channel
00691   * @param  hhcd: HCD handle
00692   * @param  chnum: Channel number.
00693   *         This parameter can be a value from 1 to 15
00694   * @retval URB state.
00695   *          This parameter can be one of these values:
00696   *            URB_IDLE/
00697   *            URB_DONE/
00698   *            URB_NOTREADY/
00699   *            URB_NYET/
00700   *            URB_ERROR/
00701   *            URB_STALL/
00702   */
00703 HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
00704 {
00705   return hhcd->hc[chnum].urb_state;
00706 }
00707
00708
00709 /**
00710   * @brief  Return the last host transfer size
00711   * @param  hhcd: HCD handle
00712   * @param  chnum: Channel number.
00713   *         This parameter can be a value from 1 to 15
00714   * @retval last transfer size in byte
00715   */
00716 uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
00717 {
00718   return hhcd->hc[chnum].xfer_count;
00719 }
00720
00721 /**
00722   * @brief  Return the Host Channel state
00723   * @param  hhcd: HCD handle
00724   * @param  chnum: Channel number.
00725   *         This parameter can be a value from 1 to 15
00726   * @retval Host channel state
00727   *          This parameter can be one of the these values:
00728   *            HC_IDLE/
00729   *            HC_XFRC/
00730   *            HC_HALTED/
00731   *            HC_NYET/
00732   *            HC_NAK/
00733   *            HC_STALL/
00734   *            HC_XACTERR/
00735   *            HC_BBLERR/
00736   *            HC_DATATGLERR/
00737   */
00738 HCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
00739 {
00740   return hhcd->hc[chnum].state;
00741 }
00742
00743 /**
00744   * @brief  Return the current Host frame number
00745   * @param  hhcd: HCD handle
00746   * @retval Current Host frame number
00747   */
00748 uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
00749 {
00750   return (USB_GetCurrentFrame(hhcd->Instance));
00751 }
00752
00753 /**
00754   * @brief  Return the Host enumeration speed
00755   * @param  hhcd: HCD handle
00756   * @retval Enumeration speed
00757   */
00758 uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
00759 {
00760   return (USB_GetHostSpeed(hhcd->Instance));
00761 }
00762 /**
00763   * @}
00764   */
00765
00766 /**
00767   * @}
00768   */
00769
00770 /** @addtogroup HCD_Private_Functions
00771   * @{
00772   */
00773 /**
00774   * @brief  This function handles Host Channel IN interrupt requests.
00775   * @param  hhcd: HCD handle
00776   * @param  chnum: Channel number.
00777   *         This parameter can be a value from 1 to 15
00778   * @retval none
00779   */
00780 static void HCD_HC_IN_IRQHandler   (HCD_HandleTypeDef *hhcd, uint8_t chnum)
00781 {
00782   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
00783
00784   if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_AHBERR)
00785   {
00786     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
00787     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00788   }
00789   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_ACK)
00790   {
00791     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
00792   }
00793
00794   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_STALL)
00795   {
00796     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00797     hhcd->hc[chnum].state = HC_STALL;
00798     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00799     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
00800     USB_HC_Halt(hhcd->Instance, chnum);
00801   }
00802   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_DTERR)
00803   {
00804     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00805     USB_HC_Halt(hhcd->Instance, chnum);
00806     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00807     hhcd->hc[chnum].state = HC_DATATGLERR;
00808     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
00809   }
00810
00811   if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_FRMOR)
00812   {
00813     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00814     USB_HC_Halt(hhcd->Instance, chnum);
00815     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
00816   }
00817
00818   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_XFRC)
00819   {
00820
00821     if (hhcd->Init.dma_enable)
00822     {
00823       hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \
00824                                (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
00825     }
00826
00827     hhcd->hc[chnum].state = HC_XFRC;
00828     hhcd->hc[chnum].ErrCnt = 0;
00829     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
00830
00831
00832     if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
00833         (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
00834     {
00835       __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00836       USB_HC_Halt(hhcd->Instance, chnum);
00837       __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00838
00839     }
00840     else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
00841     {
00842       USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
00843       hhcd->hc[chnum].urb_state = URB_DONE;
00844       HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
00845     }
00846     hhcd->hc[chnum].toggle_in ^= 1;
00847
00848   }
00849   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_CHH)
00850   {
00851     __HAL_HCD_MASK_HALT_HC_INT(chnum);
00852
00853     if(hhcd->hc[chnum].state == HC_XFRC)
00854     {
00855       hhcd->hc[chnum].urb_state  = URB_DONE;
00856     }
00857
00858     else if (hhcd->hc[chnum].state == HC_STALL)
00859     {
00860       hhcd->hc[chnum].urb_state  = URB_STALL;
00861     }
00862
00863     else if((hhcd->hc[chnum].state == HC_XACTERR) ||
00864             (hhcd->hc[chnum].state == HC_DATATGLERR))
00865     {
00866       if(hhcd->hc[chnum].ErrCnt++ > 3)
00867       {
00868         hhcd->hc[chnum].ErrCnt = 0;
00869         hhcd->hc[chnum].urb_state = URB_ERROR;
00870       }
00871       else
00872       {
00873         hhcd->hc[chnum].urb_state = URB_NOTREADY;
00874       }
00875
00876       /* re-activate the channel  */
00877       USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
00878       USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
00879     }
00880     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
00881     HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
00882   }
00883
00884   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_TXERR)
00885   {
00886     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00887      hhcd->hc[chnum].ErrCnt++;
00888      hhcd->hc[chnum].state = HC_XACTERR;
00889      USB_HC_Halt(hhcd->Instance, chnum);
00890      __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
00891   }
00892   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NAK)
00893   {
00894     if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
00895     {
00896       __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00897       USB_HC_Halt(hhcd->Instance, chnum);
00898     }
00899
00900     hhcd->hc[chnum].state = HC_NAK;
00901     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00902
00903     if  ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
00904          (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
00905     {
00906       /* re-activate the channel  */
00907       USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
00908       USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
00909     }
00910   }
00911 }
00912
00913 /**
00914   * @brief  This function handles Host Channel OUT interrupt requests.
00915   * @param  hhcd: HCD handle
00916   * @param  chnum: Channel number.
00917   *         This parameter can be a value from 1 to 15
00918   * @retval none
00919   */
00920 static void HCD_HC_OUT_IRQHandler  (HCD_HandleTypeDef *hhcd, uint8_t chnum)
00921 {
00922   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
00923
00924   if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_AHBERR)
00925   {
00926     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
00927     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00928   }
00929   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_ACK)
00930   {
00931     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
00932
00933     if( hhcd->hc[chnum].do_ping == 1)
00934     {
00935       hhcd->hc[chnum].state = HC_NYET;
00936       __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00937       USB_HC_Halt(hhcd->Instance, chnum);
00938       hhcd->hc[chnum].urb_state  = URB_NOTREADY;
00939     }
00940   }
00941
00942   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NYET)
00943   {
00944     hhcd->hc[chnum].state = HC_NYET;
00945     hhcd->hc[chnum].ErrCnt= 0;
00946     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00947     USB_HC_Halt(hhcd->Instance, chnum);
00948     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
00949
00950   }
00951
00952   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_FRMOR)
00953   {
00954     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00955     USB_HC_Halt(hhcd->Instance, chnum);
00956     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
00957   }
00958
00959   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_XFRC)
00960   {
00961       hhcd->hc[chnum].ErrCnt = 0;
00962     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00963     USB_HC_Halt(hhcd->Instance, chnum);
00964     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
00965     hhcd->hc[chnum].state = HC_XFRC;
00966
00967   }
00968
00969   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_STALL)
00970   {
00971     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
00972     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00973     USB_HC_Halt(hhcd->Instance, chnum);
00974     hhcd->hc[chnum].state = HC_STALL;
00975   }
00976
00977   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NAK)
00978   {
00979     hhcd->hc[chnum].ErrCnt = 0;
00980     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00981     USB_HC_Halt(hhcd->Instance, chnum);
00982     hhcd->hc[chnum].state = HC_NAK;
00983     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00984   }
00985
00986   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_TXERR)
00987   {
00988     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00989     USB_HC_Halt(hhcd->Instance, chnum);
00990     hhcd->hc[chnum].state = HC_XACTERR;
00991      __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
00992   }
00993
00994   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_DTERR)
00995   {
00996     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00997     USB_HC_Halt(hhcd->Instance, chnum);
00998     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00999     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
01000     hhcd->hc[chnum].state = HC_DATATGLERR;
01001   }
01002
01003
01004   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_CHH)
01005   {
01006     __HAL_HCD_MASK_HALT_HC_INT(chnum);
01007
01008     if(hhcd->hc[chnum].state == HC_XFRC)
01009     {
01010       hhcd->hc[chnum].urb_state  = URB_DONE;
01011       if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)
01012       {
01013         hhcd->hc[chnum].toggle_out ^= 1;
01014       }
01015     }
01016     else if (hhcd->hc[chnum].state == HC_NAK)
01017     {
01018       hhcd->hc[chnum].urb_state  = URB_NOTREADY;
01019     }
01020
01021     else if (hhcd->hc[chnum].state == HC_NYET)
01022     {
01023       hhcd->hc[chnum].urb_state  = URB_NOTREADY;
01024       hhcd->hc[chnum].do_ping = 0;
01025     }
01026
01027     else if (hhcd->hc[chnum].state == HC_STALL)
01028     {
01029       hhcd->hc[chnum].urb_state  = URB_STALL;
01030     }
01031
01032     else if((hhcd->hc[chnum].state == HC_XACTERR) ||
01033             (hhcd->hc[chnum].state == HC_DATATGLERR))
01034     {
01035       if(hhcd->hc[chnum].ErrCnt++ > 3)
01036       {
01037         hhcd->hc[chnum].ErrCnt = 0;
01038         hhcd->hc[chnum].urb_state = URB_ERROR;
01039       }
01040       else
01041       {
01042         hhcd->hc[chnum].urb_state = URB_NOTREADY;
01043       }
01044
01045       /* re-activate the channel  */
01046       USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
01047       USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
01048     }
01049
01050     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
01051     HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
01052   }
01053 }
01054
01055 /**
01056   * @brief  This function handles Rx Queue Level interrupt requests.
01057   * @param  hhcd: HCD handle
01058   * @retval none
01059   */
01060 static void HCD_RXQLVL_IRQHandler  (HCD_HandleTypeDef *hhcd)
01061 {
01062   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
01063   uint8_t                       channelnum =0;
01064   uint32_t                      pktsts;
01065   uint32_t                      pktcnt;
01066   uint32_t                      temp = 0;
01067
01068   temp = hhcd->Instance->GRXSTSP ;
01069   channelnum = temp &  USB_OTG_GRXSTSP_EPNUM;
01070   pktsts = (temp &  USB_OTG_GRXSTSP_PKTSTS) >> 17;
01071   pktcnt = (temp &  USB_OTG_GRXSTSP_BCNT) >> 4;
01072
01073   switch (pktsts)
01074   {
01075   case GRXSTS_PKTSTS_IN:
01076     /* Read the data into the host buffer. */
01077     if ((pktcnt > 0) && (hhcd->hc[channelnum].xfer_buff != (void  *)0))
01078     {
01079
01080       USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt);
01081
01082       /*manage multiple Xfer */
01083       hhcd->hc[channelnum].xfer_buff += pktcnt;
01084       hhcd->hc[channelnum].xfer_count  += pktcnt;
01085
01086       if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0)
01087       {
01088         /* re-activate the channel when more packets are expected */
01089         USBx_HC(channelnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
01090         USBx_HC(channelnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
01091         hhcd->hc[channelnum].toggle_in ^= 1;
01092       }
01093     }
01094     break;
01095
01096   case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
01097     break;
01098   case GRXSTS_PKTSTS_IN_XFER_COMP:
01099   case GRXSTS_PKTSTS_CH_HALTED:
01100   default:
01101     break;
01102   }
01103 }
01104
01105 /**
01106   * @brief  This function handles Host Port interrupt requests.
01107   * @param  hhcd: HCD handle
01108   * @retval None
01109   */
01110 static void HCD_Port_IRQHandler  (HCD_HandleTypeDef *hhcd)
01111 {
01112   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
01113   __IO uint32_t hprt0, hprt0_dup;
01114
01115   /* Handle Host Port Interrupts */
01116   hprt0 = USBx_HPRT0;
01117   hprt0_dup = USBx_HPRT0;
01118
01119   hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
01120                  USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
01121
01122   /* Check whether Port Connect detected */
01123   if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
01124   {
01125     if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
01126     {
01127       USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
01128       HAL_HCD_Connect_Callback(hhcd);
01129     }
01130     hprt0_dup  |= USB_OTG_HPRT_PCDET;
01131
01132   }
01133
01134   /* Check whether Port Enable Changed */
01135   if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
01136   {
01137     hprt0_dup |= USB_OTG_HPRT_PENCHNG;
01138
01139     if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
01140     {
01141       if(hhcd->Init.phy_itface  == USB_OTG_EMBEDDED_PHY)
01142       {
01143         if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
01144         {
01145           USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ );
01146         }
01147         else
01148         {
01149           USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
01150         }
01151       }
01152       else
01153       {
01154         if(hhcd->Init.speed == HCD_SPEED_FULL)
01155         {
01156           USBx_HOST->HFIR = (uint32_t)60000;
01157         }
01158       }
01159       HAL_HCD_Connect_Callback(hhcd);
01160
01161       if(hhcd->Init.speed == HCD_SPEED_HIGH)
01162       {
01163         USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
01164       }
01165     }
01166     else
01167     {
01168       /* Cleanup HPRT */
01169       USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
01170         USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
01171
01172       USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
01173     }
01174   }
01175
01176   /* Check For an overcurrent */
01177   if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
01178   {
01179     hprt0_dup |= USB_OTG_HPRT_POCCHNG;
01180   }
01181
01182   /* Clear Port Interrupts */
01183   USBx_HPRT0 = hprt0_dup;
01184 }
01185
01186 /**
01187   * @}
01188   */
01189
01190 #endif /* HAL_HCD_MODULE_ENABLED */
01191 /**
01192   * @}
01193   */
01194
01195 /**
01196   * @}
01197   */
01198
01199 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_hcd.h Source File

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stm32h7xx_hal_hcd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_hcd.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of HCD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_HCD_H
00040 #define __STM32H7xx_HAL_HCD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_ll_usb.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup HCD HCD
00054   * @brief HCD HAL module driver
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup HCD_Exported_Types HCD Exported Types
00060   * @{
00061   */
00062
00063 /** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
00064   * @{
00065   */
00066 typedef enum
00067 {
00068   HAL_HCD_STATE_RESET    = 0x00,
00069   HAL_HCD_STATE_READY    = 0x01,
00070   HAL_HCD_STATE_ERROR    = 0x02,
00071   HAL_HCD_STATE_BUSY     = 0x03,
00072   HAL_HCD_STATE_TIMEOUT  = 0x04
00073 } HCD_StateTypeDef;
00074
00075 typedef USB_OTG_GlobalTypeDef   HCD_TypeDef;
00076 typedef USB_OTG_CfgTypeDef      HCD_InitTypeDef;
00077 typedef USB_OTG_HCTypeDef       HCD_HCTypeDef ;
00078 typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;
00079 typedef USB_OTG_HCStateTypeDef  HCD_HCStateTypeDef ;
00080 /**
00081   * @}
00082   */
00083
00084 /** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
00085   * @{
00086   */
00087 typedef struct
00088 {
00089   HCD_TypeDef               *Instance;  /*!< Register base address    */
00090   HCD_InitTypeDef           Init;       /*!< HCD required parameters  */
00091   HCD_HCTypeDef             hc[15];     /*!< Host channels parameters */
00092   HAL_LockTypeDef           Lock;       /*!< HCD peripheral status    */
00093   __IO HCD_StateTypeDef     State;      /*!< HCD communication state  */
00094   void                      *pData;     /*!< Pointer Stack Handler    */
00095 } HCD_HandleTypeDef;
00096 /**
00097   * @}
00098   */
00099
00100 /**
00101   * @}
00102   */
00103
00104 /* Exported constants --------------------------------------------------------*/
00105 /** @defgroup HCD_Exported_Constants HCD Exported Constants
00106   * @{
00107   */
00108 /** @defgroup HCD_Speed HCD Speed
00109   * @{
00110   */
00111 #define HCD_SPEED_HIGH               0
00112 #define HCD_SPEED_LOW                2
00113 #define HCD_SPEED_FULL               3
00114 /**
00115   * @}
00116   */
00117
00118 /** @defgroup HCD_PHY_Module HCD PHY Module
00119   * @{
00120   */
00121 #define HCD_PHY_ULPI                 1
00122 #define HCD_PHY_EMBEDDED             2
00123 /**
00124   * @}
00125   */
00126
00127 /**
00128   * @}
00129   */
00130
00131 /* Exported macro ------------------------------------------------------------*/
00132 /** @defgroup HCD_Exported_Macros HCD Exported Macros
00133  *  @brief macros to handle interrupts and specific clock configurations
00134  * @{
00135  */
00136 #define __HAL_HCD_ENABLE(__HANDLE__)                   USB_EnableGlobalInt ((__HANDLE__)->Instance)
00137 #define __HAL_HCD_DISABLE(__HANDLE__)                  USB_DisableGlobalInt ((__HANDLE__)->Instance)
00138
00139 #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
00140 #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
00141 #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
00142
00143 #define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__)  (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
00144 #define __HAL_HCD_MASK_HALT_HC_INT(chnum)             (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
00145 #define __HAL_HCD_UNMASK_HALT_HC_INT(chnum)           (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
00146 #define __HAL_HCD_MASK_ACK_HC_INT(chnum)              (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
00147 #define __HAL_HCD_UNMASK_ACK_HC_INT(chnum)            (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
00148 /**
00149   * @}
00150   */
00151
00152 /* Exported functions --------------------------------------------------------*/
00153 /** @defgroup HCD_Exported_Functions HCD Exported Functions
00154   * @{
00155   */
00156
00157 /** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
00158   * @{
00159   */
00160 HAL_StatusTypeDef      HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
00161 HAL_StatusTypeDef      HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);
00162 HAL_StatusTypeDef      HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
00163                                   uint8_t ch_num,
00164                                   uint8_t epnum,
00165                                   uint8_t dev_address,
00166                                   uint8_t speed,
00167                                   uint8_t ep_type,
00168                                   uint16_t mps);
00169
00170 HAL_StatusTypeDef   HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
00171 void                HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
00172 void                HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
00173 /**
00174   * @}
00175   */
00176
00177 /** @defgroup HCD_Exported_Functions_Group2 IO operation functions
00178   * @{
00179   */
00180 HAL_StatusTypeDef       HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
00181                                                  uint8_t pipe,
00182                                                  uint8_t direction ,
00183                                                  uint8_t ep_type,
00184                                                  uint8_t token,
00185                                                  uint8_t* pbuff,
00186                                                  uint16_t length,
00187                                                  uint8_t do_ping);
00188
00189  /* Non-Blocking mode: Interrupt */
00190 void                    HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
00191 void             HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
00192 void             HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
00193 void             HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
00194 void             HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
00195                                                             uint8_t chnum,
00196                                                             HCD_URBStateTypeDef urb_state);
00197 /**
00198   * @}
00199   */
00200
00201 /** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
00202   * @{
00203   */
00204 HAL_StatusTypeDef       HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
00205 HAL_StatusTypeDef       HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
00206 HAL_StatusTypeDef       HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
00212   * @{
00213   */
00214 HCD_StateTypeDef        HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
00215 HCD_URBStateTypeDef     HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00216 uint32_t                HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00217 HCD_HCStateTypeDef      HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00218 uint32_t                HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
00219 uint32_t                HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
00220 /**
00221   * @}
00222   */
00223
00224 /**
00225   * @}
00226   */
00227
00228 /* Private macros ------------------------------------------------------------*/
00229 /** @defgroup HCD_Private_Macros HCD Private Macros
00230  * @{
00231  */
00232 /** @defgroup HCD_Instance_definition HCD Instance definition
00233   * @{
00234   */
00235 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB2_OTG_FS) || \
00236                                        ((INSTANCE) == USB1_OTG_HS))
00237 /**
00238   * @}
00239   */
00240
00241 /**
00242   * @}
00243   */
00244
00245 /* Private functions prototypes ----------------------------------------------*/
00246 /** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes
00247   * @{
00248   */
00249
00250 /**
00251   * @}
00252   */
00253
00254 /* Private functions ---------------------------------------------------------*/
00255 /** @defgroup HCD_Private_Functions HCD Private Functions
00256   * @{
00257   */
00258
00259 /**
00260   * @}
00261   */
00262
00263 /**
00264   * @}
00265   */
00266
00267 /**
00268   * @}
00269   */
00270
00271 #ifdef __cplusplus
00272 }
00273 #endif
00274
00275 #endif /* __STM32H7xx_HAL_HCD_H */
00276
00277 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_hrtim.c Source File

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stm32h7xx_hal_hrtim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_hrtim.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   HRTIM HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the High Resolution Timer (HRTIM) peripheral:
00010   *           + HRTIM Initialization
00011   *           + Timer Time Base Unit Configuration
00012   *           + Simple Time Base Start/Stop
00013   *           + Simple Time Base Start/Stop Interrupt
00014   *           + Simple Time Base Start/Stop DMA Request
00015   *           + Simple Output Compare/PWM Channel Configuration
00016   *           + Simple Output Compare/PWM Channel Start/Stop Interrupt
00017   *           + Simple Output Compare/PWM Channel Start/Stop DMA Request
00018   *           + Simple Input Capture Channel Configuration
00019   *           + Simple Input Capture Channel Start/Stop Interrupt
00020   *           + Simple Input Capture Channel Start/Stop DMA Request
00021   *           + Simple One Pulse Channel Configuration
00022   *           + Simple One Pulse Channel Start/Stop Interrupt
00023   *           + HRTIM External Synchronization Configuration
00024   *           + HRTIM Burst Mode Controller Configuration
00025   *           + HRTIM Burst Mode Controller Enabling
00026   *           + HRTIM External Events Conditioning Configuration
00027   *           + HRTIM Faults Conditioning Configuration
00028   *           + HRTIM Faults Enabling
00029   *           + HRTIM ADC trigger Configuration
00030   *           + Waveform Timer Configuration
00031   *           + Waveform Event Filtering Configuration
00032   *           + Waveform Dead Time Insertion Configuration
00033   *           + Waveform Chopper Mode Configuration
00034   *           + Waveform Compare Unit Configuration
00035   *           + Waveform Capture Unit Configuration
00036   *           + Waveform Output Configuration
00037   *           + Waveform Counter Start/Stop
00038   *           + Waveform Counter Start/Stop Interrupt
00039   *           + Waveform Counter Start/Stop DMA Request
00040   *           + Waveform Output Enabling
00041   *           + Waveform Output Level Set/Get
00042   *           + Waveform Output State Get
00043   *           + Waveform Burst DMA Operation Configuration
00044   *           + Waveform Burst DMA Operation Start
00045   *           + Waveform Timer Counter Software Reset
00046   *           + Waveform Capture Software Trigger
00047   *           + Waveform Burst Mode Controller Software Trigger
00048   *           + Waveform Timer Pre-loadable Registers Update Enabling
00049   *           + Waveform Timer Pre-loadable Registers Software Update
00050   *           + Waveform Timer Delayed Protection Status Get
00051   *           + Waveform Timer Burst Status Get
00052   *           + Waveform Timer Push-Pull Status Get
00053   *           + Peripheral State Get
00054   @verbatim
00055   ==============================================================================
00056                       ##### Simple mode v.s. waveform mode #####
00057 ==============================================================================
00058   [..] The HRTIM HAL API is split into 2 categories:
00059     (#)Simple functions: these functions allow for using a HRTIM timer as a
00060         general purpose timer with high resolution capabilities.
00061        Following simple modes are proposed:
00062          (+)Output compare mode
00063          (+)PWM output mode
00064          (+)Input capture mode
00065          (+)One pulse mode
00066        HRTIM simple modes are managed through the set of functions named
00067        HAL_HRTIM_Simple<Function>. These functions are similar in name and usage
00068        to the one defined for the TIM peripheral. When a HRTIM timer operates in
00069        simple mode, only a very limited set of HRTIM features are used.
00070     (#)Waveform functions: These functions allow taking advantage of the HRTIM
00071        flexibility to produce numerous types of control signal. When a HRTIM timer
00072        operates in waveform mode, all the HRTIM features are accessible without
00073        any restriction.  HRTIM waveform modes are managed through the set of
00074        functions named HAL_HRTIM_Waveform<Function>
00075
00076 ==============================================================================
00077                       ##### How to use this driver #####
00078 ==============================================================================
00079     [..]
00080      (#)Initialize the HRTIM low level resources by implementing the
00081         HAL_HRTIM_MspInit() function:
00082         (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
00083         (##)Connect HRTIM pins to MCU I/Os
00084             (+++) Enable the clock for the HRTIM GPIOs using the following
00085                   function: __GPIOx_CLK_ENABLE()
00086             (+++) Configure these GPIO pins in Alternate Function mode using
00087                   HAL_GPIO_Init()
00088         (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
00089             (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
00090             (+++)Initialize the DMA handle
00091             (+++)Associate the initialized DMA handle to the appropriate DMA
00092                  handle of the HRTIM handle using  __HAL_LINKDMA()
00093             (+++)Initialize the DMA channel using HAL_DMA_Init()
00094             (+++)Configure the priority and enable the NVIC for the transfer
00095                  complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
00096                  and HAL_NVIC_EnableIRQ()
00097         (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
00098             (+++)Configure the priority and enable the NVIC for the concerned
00099                  HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
00100
00101     (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
00102        structure (field of the HRTIM handle) specifies which global interrupt of
00103        whole HRTIM must be enabled (Burst mode period, System fault, Faults).
00104        It also contains the HRTIM external synchronization configuration. HRTIM
00105        can act as a master (generating a synchronization signal) or as a slave
00106        (waiting for a trigger to be synchronized).
00107
00108      (#) Configure HRTIM resources shared by all HRTIM timers
00109         (##)Burst Mode Controller:
00110                 (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
00111                      controller: operating mode (continuous or -shot mode), clock
00112                      (source, prescaler) , trigger(s), period, idle duration.
00113         (##)External Events Conditionning:
00114                 (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
00115                      external event channel: source, polarity, edge-sensitivity.
00116                      External event can be used as triggers (timer reset, input
00117                      capture, burst mode, ADC triggers, delayed protection, …)
00118                      They can also be used to set or reset timer outputs. Up to
00119                      10 event channels are available.
00120                 (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
00121                      event sampling clock (used for digital filtering).
00122         (##)Fault Conditionning:
00123                 (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
00124                      fault channel: source, polarity, edge-sensitivity.  Fault
00125                      channels are used to disable the outputs in case of an
00126                      abnormal operation. Up to 5 fault channels are available.
00127                 (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
00128                      sampling clock (used for digital filtering).
00129                 (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
00130                      circuitry. By default all fault inputs are disabled.
00131         (##)ADC trigger:
00132                 (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
00133                      the update of the ADC trigger register and the ADC trigger.
00134                      4 independent triggers are available to start both the regular
00135                      and the injected sequencers of the 2 ADCs
00136
00137      (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
00138          function must be called whatever the HRTIM timer operating mode is
00139          (simple v.s. waveform). It  configures mainly:
00140         (##)The HRTIM  timer counter operating mode (continuous, one shot)
00141         (##)The HRTIM  timer clock prescaler
00142         (##)The HRTIM  timer period
00143         (##)The HRTIM  timer repetition counter
00144
00145      (#) If the HRTIM timer operates in simple mode:
00146         (##)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
00147                   HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
00148                   HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
00149         (##)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
00150                   HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
00151                   HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
00152                   HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
00153         (##)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
00154                   HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
00155                   HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
00156                   HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
00157         (##)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
00158                   HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
00159                   HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
00160                   HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
00161         (##)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
00162                   HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
00163                   HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().
00164
00165      (#) If the HRTIM timer operates in waveform mode:
00166         (##)Completes waveform timer configuration
00167                 (+++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM
00168                      timer operating in wave form mode mainly consists in:
00169                         - Enabling the HRTIM timer interrupts and DMA requests,
00170                         - Enabling the half mode for the HRTIM timer,
00171                         - Defining how the HRTIM timer reacts to external
00172                           synchronization input,
00173                         - Enabling the push-pull mode for the HRTIM timer,
00174                         - Enabling the fault channels for the HRTIM timer,
00175                         - Enabling the deadtime insertion for the HRTIM timer,
00176                         - Setting the delayed protection mode for the HRTIM timer
00177                           (source and outputs on which the delayed protection are applied),
00178                         - Specifying the HRTIM timer update and reset triggers,
00179                         - Specifying the HRTIM timer registers update policy (preload enabling, …).
00180                 (+++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
00181                      event blanking and windowingcircuitry of a HRTIM timer:
00182                         - Blanking:  to mask external events during a defined
00183                           time period
00184                         - Windowing:  to enable external events only during
00185                           a defined time period
00186                 (+++)HAL_HRTIM_DeadTimeConfig(): configures the deadtime insertion
00187                      unit for a HRTIM timer. Allows to generate a couple of
00188                      complementary signals from a single reference waveform,
00189                      with programmable delays between active state.
00190                 (+++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
00191                      the high-frequency carrier signal added on top of the timing
00192                      unit output. Chopper mode can be enabled or disabled for each
00193                      timer output separately (see  HAL_HRTIM_WaveformOutputConfig()).
00194                 (+++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
00195                      controller. Allows having multiple HRTIM registers updated
00196                      with a single DMA request. The burst DMA operation is started
00197                      by calling HAL_HRTIM_BurstDMATransfer().
00198                 (+++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
00199                      of a HRTIM timer. This operation consists in setting the
00200                      compare value and possibly specifying the auto delayed mode
00201                      for compare units 2 and 4 (allows to have compare events
00202                      generated relatively to capture events). Note that when auto
00203                      delayed mode is needed, the capture unit associated to the
00204                      compare unit must be configured separately.
00205                 (+++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
00206                      of a HRTIM timer. This operation consists in specifying the
00207                      source(s)  triggering the capture (timer register update event,
00208                      external event, timer output set/reset event, other HRTIM
00209                      timer related events).
00210                 (+++)HAL_HRTIM_WaveformOutputConfig(): configuration HRTIM timer
00211                      output manly consists in:
00212                         - Setting the output polarity (active high or active low),
00213                         - Defining the set/reset crossbar for the output,
00214                         - Specifying the fault level (active or inactive) in IDLE
00215                           and FAULT states.,
00216         (##)Set waveform timer output(s) level
00217                 (+++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
00218                      active or inactive level. For example, when deadtime insertion
00219                      is enabled it is necessary to force the output level by software
00220                      to have the outputs in a complementary state as soon as the RUN mode is entered.
00221         (##)Enable/Disable waveform timer output(s)
00222                 (+++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().
00223         (##)Start/Stop waveform HRTIM timer(s).
00224                 (+++)HAL_HRTIM_WaveformCounterStart(),HAL_HRTIM_WaveformCounterStop(),
00225                 (+++)HAL_HRTIM_WaveformCounterStart_IT(),HAL_HRTIM_WaveformCounterStop_IT(),
00226                 (+++)HAL_HRTIM_WaveformCounterStart()_DMA,HAL_HRTIM_WaveformCounterStop_DMA(),
00227
00228         (##)Burst mode controller enabling:
00229                 (+++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
00230                      burst mode controller.
00231
00232         (##)Some HRTIM operations can be triggered by software:
00233                 (+++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
00234                      trigs the burst operation.
00235                 (+++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
00236                      capture of the HRTIM timer counter.
00237                 (+++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
00238                      update of the pre-loadable registers of the HRTIM timer ()
00239                 (+++)HAL_HRTIM_SoftwareReset():calling this function resets the
00240                      HRTIM timer counter.
00241
00242         (##)Some functions can be used anytime to retrieve HRTIM timer related
00243             information
00244                 (+++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
00245                      capture register of the designated capture unit.
00246                 (+++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
00247                      (ACTIVE/INACTIVE) of the designated timer output.
00248                 (+++)HAL_HRTIM_WaveformGetOutputState():returns actual state
00249                      (IDLE/RUN/FAULT) of the designated timer output.
00250                 (+++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
00251                      (ACTIVE/INACTIVE) of the designated output when the delayed
00252                       protection was triggered.
00253                 (+++)HAL_HRTIM_GetBurstStatus(): returns the actual status
00254                      (ACTIVE/INACTIVE) of the burst mode controller.
00255                 (+++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
00256                      is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
00257                      the push-pull indicates on which output the signal is currently
00258                      active (e.g signal applied on output 1 and output 2 forced
00259                      inactive or vice versa).
00260                 (+++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
00261                      is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
00262                      the idle push-pull  status indicates during which period the
00263                      delayed protection request occurred (e.g. protection occurred
00264                      when the output 1 was active and output 2 forced inactive or
00265                      vice versa).
00266
00267         (##)Some functions can be used anytime to retrieve actual HRTIM status
00268                 (+++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.
00269
00270   @endverbatim
00271
00272   ******************************************************************************
00273   * @attention
00274   *
00275   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00276   *
00277   * Redistribution and use in source and binary forms, with or without modification,
00278   * are permitted provided that the following conditions are met:
00279   *   1. Redistributions of source code must retain the above copyright notice,
00280   *      this list of conditions and the following disclaimer.
00281   *   2. Redistributions in binary form must reproduce the above copyright notice,
00282   *      this list of conditions and the following disclaimer in the documentation
00283   *      and/or other materials provided with the distribution.
00284   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00285   *      may be used to endorse or promote products derived from this software
00286   *      without specific prior written permission.
00287   *
00288   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00289   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00290   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00291   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00292   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00293   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00294   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00295   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00296   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00297   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00298   *
00299   ******************************************************************************
00300   */
00301
00302 /* Includes ------------------------------------------------------------------*/
00303 #include "stm32h7xx_hal.h"
00304
00305 /** @addtogroup STM32H7xx_HAL_Driver
00306   * @{
00307   */
00308
00309 #ifdef HAL_HRTIM_MODULE_ENABLED
00310
00311 /** @defgroup HRTIM HRTIM
00312   * @brief HRTIM HAL module driver
00313   * @{
00314   */
00315
00316 /* Private typedef -----------------------------------------------------------*/
00317 /* Private define ------------------------------------------------------------*/
00318 /** @defgroup HRTIM_Private_Defines HRTIM Private Define
00319   * @{
00320   */
00321 #define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
00322                            HRTIM_FLTR_FLT2EN |\
00323                            HRTIM_FLTR_FLT3EN |\
00324                            HRTIM_FLTR_FLT4EN | \
00325                            HRTIM_FLTR_FLT5EN)
00326
00327 #define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER  |\
00328                                       HRTIM_TIMUPDATETRIGGER_TIMER_A |\
00329                                       HRTIM_TIMUPDATETRIGGER_TIMER_B |\
00330                                       HRTIM_TIMUPDATETRIGGER_TIMER_C |\
00331                                       HRTIM_TIMUPDATETRIGGER_TIMER_D |\
00332                                       HRTIM_TIMUPDATETRIGGER_TIMER_E)
00333 /**
00334   * @}
00335   */
00336
00337 /* Private macro -------------------------------------------------------------*/
00338 /* Private variables ---------------------------------------------------------*/
00339 /** @defgroup HRTIM_Private_Variables HRTIM Private Variables
00340   * @{
00341   */
00342 static uint32_t TimerIdxToTimerId[] =
00343 {
00344   HRTIM_TIMERID_TIMER_A,
00345   HRTIM_TIMERID_TIMER_B,
00346   HRTIM_TIMERID_TIMER_C,
00347   HRTIM_TIMERID_TIMER_D,
00348   HRTIM_TIMERID_TIMER_E,
00349   HRTIM_TIMERID_MASTER,
00350 };
00351 /**
00352   * @}
00353   */
00354
00355 /* Private function prototypes -----------------------------------------------*/
00356 /** @defgroup HRTIM_Private_Functions HRTIM Private Functions
00357   * @{
00358   */
00359 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
00360                                     HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
00361
00362 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
00363                                         uint32_t TimerIdx,
00364                                         HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
00365
00366 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
00367                                         HRTIM_TimerCfgTypeDef * pTimerCfg);
00368
00369 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
00370                                             uint32_t TimerIdx,
00371                                             HRTIM_TimerCfgTypeDef * pTimerCfg);
00372
00373 static void HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim,
00374                                     uint32_t TimerIdx,
00375                                     uint32_t CompareUnit,
00376                                     HRTIM_CompareCfgTypeDef * pCompareCfg);
00377
00378 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
00379                                     uint32_t TimerIdx,
00380                                     uint32_t CaptureUnit,
00381                                     uint32_t Event);
00382
00383 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
00384                                 uint32_t TimerIdx,
00385                                 uint32_t Output,
00386                                 HRTIM_OutputCfgTypeDef * pOutputCfg);
00387
00388 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
00389                               uint32_t Event,
00390                               HRTIM_EventCfgTypeDef * pEventCfg);
00391
00392 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
00393                                   uint32_t TimerIdx,
00394                                   uint32_t Event);
00395
00396 static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
00397                                       uint32_t TimerIdx,
00398                                       uint32_t OCChannel);
00399
00400 static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
00401                                        uint32_t TimerIdx,
00402                                        uint32_t OCChannel);
00403
00404 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
00405                                                           uint32_t TimerIdx);
00406
00407 static uint32_t GetTimerIdxFromDMAHandle(DMA_HandleTypeDef *hdma);
00408
00409 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
00410                                       uint32_t TimerIdx);
00411
00412 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim);
00413
00414 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim);
00415
00416 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
00417                                        uint32_t TimerIdx);
00418
00419 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma);
00420
00421 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma);
00422
00423 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma);
00424
00425 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma);
00426 /**
00427   * @}
00428   */
00429
00430 /* Exported functions ---------------------------------------------------------*/
00431 /** @defgroup HRTIM_Exported_Functions HRTIM Exported Functions
00432   * @{
00433   */
00434
00435 /** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
00436  *  @brief    Initialization and Configuration functions
00437  *
00438 @verbatim
00439  ===============================================================================
00440               ##### Initialization and Time Base Configuration functions #####
00441  ===============================================================================
00442     [..]  This section provides functions allowing to:
00443       (+) Initialize a HRTIM instance
00444       (+) De-initialize a HRTIM instance
00445       (+) Initialize the HRTIM MSP
00446       (+) De-initialize the HRTIM MSP
00447       (+) Configure the time base unit of a HRTIM timer
00448
00449 @endverbatim
00450   * @{
00451   */
00452
00453 /**
00454   * @brief  Initializes a HRTIM instance
00455   * @param  hhrtim: pointer to HAL HRTIM handle
00456   * @retval HAL status
00457   */
00458 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)
00459 {
00460   uint8_t timer_idx;
00461   uint32_t hrtim_mcr;
00462
00463   /* Check the HRTIM handle allocation */
00464   if(hhrtim == NULL)
00465   {
00466     return HAL_ERROR;
00467   }
00468
00469   /* Check the parameters */
00470   assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
00471   assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests));
00472
00473   /* Set the HRTIM state */
00474   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00475
00476   /* Initialize the DMA handles */
00477   hhrtim->hdmaMaster = (DMA_HandleTypeDef *)NULL;
00478   hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)NULL;
00479   hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)NULL;
00480   hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL;
00481   hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL;
00482   hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL;
00483
00484   /* HRTIM output synchronization configuration (if required) */
00485   if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != RESET)
00486   {
00487     /* Check parameters */
00488     assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(hhrtim->Init.SyncOutputSource));
00489     assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity));
00490
00491     /* The synchronization output initialization procedure must be done prior
00492        to the configuration of the MCU outputs (done within HAL_HRTIM_MspInit)
00493     */
00494     if (hhrtim->Instance == HRTIM1)
00495     {
00496       /* Enable the HRTIM peripheral clock */
00497       __HAL_RCC_HRTIM1_CLK_ENABLE();
00498     }
00499
00500     hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
00501
00502     /* Set the event to be sent on the synchronization output */
00503     hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC);
00504     hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC);
00505
00506     /* Set the polarity of the synchronization output */
00507     hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT);
00508     hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT);
00509
00510     /* Update the HRTIM registers */
00511     hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
00512   }
00513
00514   /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00515   HAL_HRTIM_MspInit(hhrtim);
00516
00517   /* HRTIM input synchronization configuration (if required) */
00518   if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != RESET)
00519   {
00520     /* Check parameters */
00521     assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource));
00522
00523     hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
00524
00525     /* Set the synchronization input source */
00526     hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN);
00527     hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN);
00528
00529     /* Update the HRTIM registers */
00530     hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
00531   }
00532
00533   /* Initialize the HRTIM state*/
00534   hhrtim->State = HAL_HRTIM_STATE_READY;
00535
00536   /* Initialize the lock status of the HRTIM HAL API */
00537   __HAL_UNLOCK(hhrtim);
00538
00539   /* Tnitialize timer related parameters */
00540   for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
00541        timer_idx <= HRTIM_TIMERINDEX_MASTER ;
00542        timer_idx++)
00543   {
00544     hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE;
00545     hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
00546     hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
00547     hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
00548     hhrtim->TimerParam[timer_idx].DMASrcAddress = 0;
00549     hhrtim->TimerParam[timer_idx].DMASize = 0;
00550   }
00551
00552   return HAL_OK;
00553 }
00554
00555 /**
00556   * @brief  De-initializes a HRTIM instance
00557   * @param  hhrtim: pointer to HAL HRTIM handle
00558   * @retval HAL status
00559   */
00560 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim)
00561 {
00562   /* Check the HRTIM handle allocation */
00563   if(hhrtim == NULL)
00564   {
00565     return HAL_ERROR;
00566   }
00567
00568   /* Check the parameters */
00569   assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
00570
00571   /* Set the HRTIM state */
00572   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00573
00574   /* DeInit the low level hardware */
00575   HAL_HRTIM_MspDeInit(hhrtim);
00576
00577   hhrtim->State = HAL_HRTIM_STATE_READY;
00578
00579   return HAL_OK;
00580 }
00581
00582 /**
00583   * @brief  MSP initialization for a HRTIM instance
00584   * @param  hhrtim: pointer to HAL HRTIM handle
00585   * @retval None
00586   */
00587 __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)
00588 {
00589   /* Prevent unused argument(s) compilation warning */
00590   UNUSED(hhrtim);
00591   /* NOTE: This function should not be modified, when the callback is needed,
00592            the HAL_HRTIM_MspInit could be implemented in the user file
00593    */
00594 }
00595
00596 /**
00597   * @brief  MSP initialization for a for a HRTIM instance
00598   * @param  hhrtim: pointer to HAL HRTIM handle
00599   * @retval None
00600   */
00601 __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)
00602 {
00603   /* Prevent unused argument(s) compilation warning */
00604   UNUSED(hhrtim);
00605
00606   /* NOTE: This function should not be modified, when the callback is needed,
00607            the HAL_HRTIM_MspDeInit could be implemented in the user file
00608    */
00609 }
00610
00611 /**
00612   * @brief  Configures the time base unit of a timer
00613   * @param  hhrtim: pointer to HAL HRTIM handle
00614   * @param  TimerIdx: Timer index
00615   *                   This parameter can be one of the following values:
00616   *                   @arg HRTIM_TIMERINDEX_MASTER for master timer
00617   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
00618   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
00619   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
00620   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
00621   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
00622   * @param  pTimeBaseCfg: pointer to the time base configuration structure
00623   * @note This function must be called prior starting the timer
00624   * @note   The time-base unit initialization parameters specify:
00625   *           The timer counter operating mode (continuous, one shot),
00626   *           The timer clock prescaler,
00627   *           The timer period,
00628   *           The timer repetition counter.
00629   * @retval HAL status
00630   */
00631 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
00632                                            uint32_t TimerIdx,
00633                                            HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
00634 {
00635   /* Check the parameters */
00636   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
00637   assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
00638   assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode));
00639
00640   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
00641   {
00642      return HAL_BUSY;
00643   }
00644
00645   /* Set the HRTIM state */
00646   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00647
00648   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
00649   {
00650     /* Configure master timer time base unit */
00651     HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg);
00652   }
00653   else
00654   {
00655     /* Configure timing unit time base unit */
00656     HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg);
00657   }
00658
00659   /* Set HRTIM state */
00660   hhrtim->State = HAL_HRTIM_STATE_READY;
00661
00662   return HAL_OK;
00663 }
00664
00665 /**
00666   * @}
00667   */
00668
00669 /** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
00670  *  @brief    Simple time base mode functions.
00671  *
00672 @verbatim
00673  ===============================================================================
00674               ##### Simple time base mode functions #####
00675  ===============================================================================
00676     [..]  This section provides functions allowing to:
00677       (+) Start simple time base
00678       (+) Stop simple time base
00679       (+) Start simple time base and enable interrupt
00680       (+) Stop simple time base and disable interrupt
00681       (+) Start simple time base and enable DMA transfer
00682       (+) Stop simple time base and disable DMA transfer
00683       -@-  When a HRTIM timer operates in simple time base mode, the timer
00684        counter counts from 0 to the period value.
00685
00686 @endverbatim
00687   * @{
00688   */
00689
00690 /**
00691   * @brief  Starts the counter of a timer operating in basic time base mode
00692   * @param  hhrtim: pointer to HAL HRTIM handle
00693   * @param  TimerIdx: Timer index
00694   *                   This parameter can be one of the following values:
00695   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
00696   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
00697   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
00698   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
00699   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
00700   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
00701   * @retval HAL status
00702   */
00703 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,
00704                                            uint32_t TimerIdx)
00705 {
00706    /* Check the parameters */
00707   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
00708
00709   /* Process Locked */
00710   __HAL_LOCK(hhrtim);
00711
00712   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00713
00714   /* Enable the timer counter */
00715   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
00716
00717   hhrtim->State = HAL_HRTIM_STATE_READY;
00718
00719   /* Process Unlocked */
00720   __HAL_UNLOCK(hhrtim);
00721
00722   return HAL_OK;
00723 }
00724
00725 /**
00726   * @brief  Stops the counter of a timer operating in basic time base mode
00727   * @param  hhrtim: pointer to HAL HRTIM handle
00728   * @param  TimerIdx: Timer index
00729   *                   This parameter can be one of the following values:
00730   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
00731   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
00732   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
00733   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
00734   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
00735   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
00736   * @retval HAL status
00737   */
00738 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,
00739                                           uint32_t TimerIdx)
00740 {
00741    /* Check the parameters */
00742   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
00743
00744   /* Process Locked */
00745   __HAL_LOCK(hhrtim);
00746
00747   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00748
00749   /* Disable the timer counter */
00750   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
00751
00752   hhrtim->State = HAL_HRTIM_STATE_READY;
00753
00754   /* Process Unlocked */
00755   __HAL_UNLOCK(hhrtim);
00756
00757   return HAL_OK;
00758 }
00759
00760 /**
00761   * @brief  Starts the counter of a timer operating in simple time base mode
00762   *         (Timer repetition interrupt is enabled).
00763   * @param  hhrtim: pointer to HAL HRTIM handle
00764   * @param  TimerIdx: Timer index
00765   *                   This parameter can be one of the following values:
00766   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
00767   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
00768   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
00769   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
00770   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
00771   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
00772   * @retval HAL status
00773   */
00774 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,
00775                                               uint32_t TimerIdx)
00776 {
00777    /* Check the parameters */
00778   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
00779
00780   /* Process Locked */
00781   __HAL_LOCK(hhrtim);
00782
00783   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00784
00785   /* Enable the repetition interrupt */
00786   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
00787   {
00788     __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
00789   }
00790   else
00791   {
00792     __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
00793   }
00794
00795   /* Enable the timer counter */
00796   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
00797
00798   hhrtim->State = HAL_HRTIM_STATE_READY;
00799
00800   /* Process Unlocked */
00801   __HAL_UNLOCK(hhrtim);
00802
00803   return HAL_OK;
00804 }
00805
00806 /**
00807   * @brief  Stops the counter of a timer operating in simple time base mode
00808   *         (Timer repetition interrupt is disabled).
00809   * @param  hhrtim: pointer to HAL HRTIM handle
00810   * @param  TimerIdx: Timer index
00811   *                   This parameter can be one of the following values:
00812   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
00813   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
00814   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
00815   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
00816   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
00817   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
00818   * @retval HAL status
00819   */
00820 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,
00821                                              uint32_t TimerIdx)
00822 {
00823    /* Check the parameters */
00824   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
00825
00826   /* Process Locked */
00827   __HAL_LOCK(hhrtim);
00828
00829   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00830
00831   /* Disable the repetition interrupt */
00832   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
00833   {
00834     __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
00835   }
00836   else
00837   {
00838     __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
00839   }
00840
00841   /* Disable the timer counter */
00842   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
00843
00844   hhrtim->State = HAL_HRTIM_STATE_READY;
00845
00846   /* Process Unlocked */
00847   __HAL_UNLOCK(hhrtim);
00848
00849   return HAL_OK;
00850 }
00851
00852 /**
00853   * @brief  Starts the counter of a timer operating in simple time base mode
00854   *         (Timer repetition DMA request is enabled).
00855   * @param  hhrtim: pointer to HAL HRTIM handle
00856   * @param  TimerIdx: Timer index
00857   *                   This parameter can be one of the following values:
00858   *                    @arg HRTIM_TIMERINDEX_MASTER  for master timer
00859   *                    @arg HRTIM_TIMERINDEX_TIMER_A for timer A
00860   *                    @arg HRTIM_TIMERINDEX_TIMER_B for timer B
00861   *                    @arg HRTIM_TIMERINDEX_TIMER_C for timer C
00862   *                    @arg HRTIM_TIMERINDEX_TIMER_D for timer D
00863   *                    @arg HRTIM_TIMERINDEX_TIMER_E for timer E
00864   * @param  SrcAddr: DMA transfer source address
00865   * @param  DestAddr: DMA transfer destination address
00866   * @param  Length: The length of data items (data size) to be transferred
00867   *                     from source to destination
00868   */
00869 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,
00870                                                uint32_t TimerIdx,
00871                                                uint32_t SrcAddr,
00872                                                uint32_t DestAddr,
00873                                                uint32_t Length)
00874 {
00875   DMA_HandleTypeDef * hdma;
00876
00877   /* Check the parameters */
00878   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
00879
00880   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
00881   {
00882      return HAL_BUSY;
00883   }
00884   if(hhrtim->State == HAL_HRTIM_STATE_READY)
00885   {
00886     if((SrcAddr == 0 ) || (DestAddr == 0 ) || (Length == 0))
00887     {
00888       return HAL_ERROR;
00889     }
00890     else
00891     {
00892       hhrtim->State = HAL_HRTIM_STATE_BUSY;
00893     }
00894   }
00895
00896   /* Process Locked */
00897   __HAL_LOCK(hhrtim);
00898
00899   /* Get the timer DMA handler */
00900   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
00901
00902   /* Set the DMA transfer completed callback */
00903   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
00904   {
00905     hdma->XferCpltCallback = HRTIM_DMAMasterCplt;
00906   }
00907   else
00908   {
00909     hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
00910   }
00911
00912   /* Set the DMA error callback */
00913   hdma->XferErrorCallback = HRTIM_DMAError ;
00914
00915   /* Enable the DMA channel */
00916   HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
00917
00918   /* Enable the timer repetition DMA request */
00919   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
00920   {
00921     __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
00922   }
00923   else
00924   {
00925     __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
00926   }
00927
00928   /* Enable the timer counter */
00929   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
00930
00931   hhrtim->State = HAL_HRTIM_STATE_READY;
00932
00933   /* Process Unlocked */
00934   __HAL_UNLOCK(hhrtim);
00935
00936   return HAL_OK;
00937 }
00938
00939 /**
00940   * @brief  Stops the counter of a timer operating in simple time base mode
00941   *         (Timer repetition DMA request is disabled).
00942   * @param  hhrtim: pointer to HAL HRTIM handle
00943   * @param  TimerIdx: Timer index
00944   *                   This parameter can be one of the following values:
00945   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
00946   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
00947   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
00948   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
00949   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
00950   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
00951   * @retval HAL status
00952   */
00953 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,
00954                                               uint32_t TimerIdx)
00955 {
00956   DMA_HandleTypeDef * hdma;
00957
00958   /* Check the parameters */
00959   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
00960
00961   /* Process Locked */
00962   __HAL_LOCK(hhrtim);
00963
00964   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
00965   {
00966     /* Disable the DMA */
00967     HAL_DMA_Abort(hhrtim->hdmaMaster);
00968
00969     /* Disable the timer repetition DMA request */
00970     __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
00971   }
00972   else
00973   {
00974     /* Get the timer DMA handler */
00975     hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
00976
00977     /* Disable the DMA */
00978     HAL_DMA_Abort(hdma);
00979
00980     /* Disable the timer repetition DMA request */
00981     __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
00982   }
00983
00984   /* Disable the timer counter */
00985   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
00986
00987   hhrtim->State = HAL_HRTIM_STATE_READY;
00988
00989   /* Process Unlocked */
00990   __HAL_UNLOCK(hhrtim);
00991
00992   return HAL_OK;
00993 }
00994
00995 /**
00996   * @}
00997   */
00998
00999 /** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
01000  *  @brief    Simple output compare functions
01001  *
01002 @verbatim
01003  ===============================================================================
01004               ##### Simple output compare functions #####
01005  ===============================================================================
01006     [..]  This section provides functions allowing to:
01007       (+) Configure simple output channel
01008       (+) Start simple output compare
01009       (+) Stop simple output compare
01010       (+) Start simple output compare and enable interrupt
01011       (+) Stop simple output compare and disable interrupt
01012       (+) Start simple output compare and enable DMA transfer
01013       (+) Stop simple output compare and disable DMA transfer
01014        -@- When a HRTIM timer operates in simple output compare mode
01015            the output level is set to a programmable value when a match
01016            is found between the compare register and the counter.
01017            Compare unit 1 is automatically associated to output 1
01018            Compare unit 2 is automatically associated to output 2
01019
01020 @endverbatim
01021   * @{
01022   */
01023
01024 /**
01025   * @brief  Configures an output in simple output compare mode
01026   * @param  hhrtim: pointer to HAL HRTIM handle
01027   * @param  TimerIdx: Timer index
01028   *                   This parameter can be one of the following values:
01029   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01030   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01031   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01032   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01033   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01034   * @param  OCChannel: Timer output
01035   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01036   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01037   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01038   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01039   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01040   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01041   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01042   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01043   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01044   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01045   * @param  pSimpleOCChannelCfg: pointer to the simple output compare output configuration structure
01046   * @note When the timer operates in simple output compare mode:
01047   *         Output 1 is implicitly controlled by the compare unit 1
01048   *         Output 2 is implicitly controlled by the compare unit 2
01049   *       Output Set/Reset crossbar is set according to the selected output compare mode:
01050   *         Toggle: SETxyR = RSTxyR = CMPy
01051   *         Active: SETxyR = CMPy, RSTxyR = 0
01052   *         Inactive: SETxy =0, RSTxy = CMPy
01053   * @retval HAL status
01054   */
01055 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
01056                                                  uint32_t TimerIdx,
01057                                                  uint32_t OCChannel,
01058                                                  HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg)
01059 {
01060   uint32_t CompareUnit = 0xFFFFFFFFU;
01061   HRTIM_CompareCfgTypeDef CompareCfg = {0};
01062   HRTIM_OutputCfgTypeDef OutputCfg = {0};
01063
01064   /* Check parameters */
01065   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01066   assert_param(IS_HRTIM_BASICOCMODE(pSimpleOCChannelCfg->Mode));
01067   assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity));
01068   assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel));
01069
01070   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
01071   {
01072      return HAL_BUSY;
01073   }
01074
01075   /* Set HRTIM state */
01076   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01077
01078   /* Configure timer compare unit */
01079   switch (OCChannel)
01080   {
01081   case HRTIM_OUTPUT_TA1:
01082   case HRTIM_OUTPUT_TB1:
01083   case HRTIM_OUTPUT_TC1:
01084   case HRTIM_OUTPUT_TD1:
01085   case HRTIM_OUTPUT_TE1:
01086     {
01087       CompareUnit = HRTIM_COMPAREUNIT_1;
01088     }
01089     break;
01090   case HRTIM_OUTPUT_TA2:
01091   case HRTIM_OUTPUT_TB2:
01092   case HRTIM_OUTPUT_TC2:
01093   case HRTIM_OUTPUT_TD2:
01094   case HRTIM_OUTPUT_TE2:
01095     {
01096       CompareUnit = HRTIM_COMPAREUNIT_2;
01097     }
01098     break;
01099   }
01100
01101   CompareCfg.CompareValue = pSimpleOCChannelCfg->Pulse;
01102   CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
01103   CompareCfg.AutoDelayedTimeout = 0;
01104
01105   HRTIM_CompareUnitConfig(hhrtim,
01106                           TimerIdx,
01107                           CompareUnit,
01108                           &CompareCfg);
01109
01110   /* Configure timer output */
01111   OutputCfg.Polarity = pSimpleOCChannelCfg->Polarity;
01112   OutputCfg.IdleLevel = pSimpleOCChannelCfg->IdleLevel;
01113   OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
01114   OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
01115   OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
01116   OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
01117
01118   switch (pSimpleOCChannelCfg->Mode)
01119   {
01120   case HRTIM_BASICOCMODE_TOGGLE:
01121     {
01122       if (CompareUnit == HRTIM_COMPAREUNIT_1)
01123       {
01124         OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
01125       }
01126       else
01127       {
01128         OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
01129       }
01130       OutputCfg.ResetSource = OutputCfg.SetSource;
01131     }
01132     break;
01133   case HRTIM_BASICOCMODE_ACTIVE:
01134     {
01135       if (CompareUnit == HRTIM_COMPAREUNIT_1)
01136       {
01137         OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
01138       }
01139       else
01140       {
01141         OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
01142       }
01143       OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
01144     }
01145     break;
01146   case HRTIM_BASICOCMODE_INACTIVE:
01147     {
01148       if (CompareUnit == HRTIM_COMPAREUNIT_1)
01149       {
01150         OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
01151       }
01152       else
01153       {
01154         OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
01155       }
01156       OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
01157     }
01158     break;
01159   }
01160
01161   HRTIM_OutputConfig(hhrtim,
01162                      TimerIdx,
01163                      OCChannel,
01164                      &OutputCfg);
01165
01166   /* Set HRTIM state */
01167   hhrtim->State = HAL_HRTIM_STATE_READY;
01168
01169   return HAL_OK;
01170 }
01171
01172 /**
01173   * @brief  Starts the output compare signal generation on the designed timer output
01174   * @param  hhrtim: pointer to HAL HRTIM handle
01175   * @param  TimerIdx: Timer index
01176   *                   This parameter can be one of the following values:
01177   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01178   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01179   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01180   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01181   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01182   * @param  OCChannel: Timer output
01183   *                    This parameter can be one of the following values:
01184   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01185   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01186   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01187   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01188   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01189   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01190   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01191   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01192   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01193   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01194   * @retval HAL status
01195   */
01196 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,
01197                                          uint32_t TimerIdx,
01198                                          uint32_t OCChannel)
01199 {
01200    /* Check the parameters */
01201   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01202
01203   /* Process Locked */
01204   __HAL_LOCK(hhrtim);
01205
01206   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01207
01208   /* Enable the timer output */
01209   hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
01210
01211   /* Enable the timer counter */
01212   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01213
01214   hhrtim->State = HAL_HRTIM_STATE_READY;
01215
01216   /* Process Unlocked */
01217   __HAL_UNLOCK(hhrtim);
01218
01219   return HAL_OK;
01220 }
01221
01222 /**
01223   * @brief  Stops the output compare signal generation on the designed timer output
01224   * @param  hhrtim: pointer to HAL HRTIM handle
01225   * @param  TimerIdx: Timer index
01226   *                   This parameter can be one of the following values:
01227   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01228   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01229   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01230   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01231   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01232   * @param  OCChannel: Timer output
01233   *                    This parameter can be one of the following values:
01234   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01235   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01236   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01237   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01238   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01239   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01240   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01241   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01242   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01243   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01244   * @retval HAL status
01245   */
01246 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,
01247                                         uint32_t TimerIdx,
01248                                         uint32_t OCChannel)
01249 {
01250    /* Check the parameters */
01251   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01252
01253   /* Process Locked */
01254   __HAL_LOCK(hhrtim);
01255
01256   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01257
01258   /* Disable the timer output */
01259   hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
01260
01261   /* Disable the timer counter */
01262   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01263
01264   hhrtim->State = HAL_HRTIM_STATE_READY;
01265
01266   /* Process Unlocked */
01267   __HAL_UNLOCK(hhrtim);
01268
01269   return HAL_OK;
01270 }
01271
01272 /**
01273   * @brief  Starts the output compare signal generation on the designed timer output
01274   *         (Interrupt is enabled (see note note below)).
01275   * @param  hhrtim: pointer to HAL HRTIM handle
01276   * @param  TimerIdx: Timer index
01277   *                   This parameter can be one of the following values:
01278   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01279   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01280   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01281   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01282   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01283   * @param  OCChannel: Timer output
01284   *                    This parameter can be one of the following values:
01285   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01286   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01287   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01288   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01289   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01290   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01291   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01292   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01293   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01294   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01295   * @note Interrupt enabling depends on the chosen output compare mode
01296   *          Output toggle: compare match interrupt is enabled
01297   *          Output set active:  output set interrupt is enabled
01298   *          Output set inactive:  output reset interrupt is enabled
01299   * @retval HAL status
01300   */
01301 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,
01302                                             uint32_t TimerIdx,
01303                                             uint32_t OCChannel)
01304 {
01305   uint32_t interrupt;
01306
01307    /* Check the parameters */
01308   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01309
01310   /* Process Locked */
01311   __HAL_LOCK(hhrtim);
01312
01313   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01314
01315   /* Get the interrupt to enable (depends on the output compare mode) */
01316   interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
01317
01318   /* Enable the timer output */
01319   hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
01320
01321   /* Enable the timer interrupt (depends on the output compare mode) */
01322   __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, interrupt);
01323
01324   /* Enable the timer counter */
01325   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01326
01327   hhrtim->State = HAL_HRTIM_STATE_READY;
01328
01329   /* Process Unlocked */
01330   __HAL_UNLOCK(hhrtim);
01331
01332   return HAL_OK;
01333 }
01334
01335 /**
01336   * @brief  Stops the output compare signal generation on the designed timer output
01337   *         (Interrupt is disabled).
01338   * @param  hhrtim: pointer to HAL HRTIM handle
01339   * @param  TimerIdx: Timer index
01340   *                   This parameter can be one of the following values:
01341   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01342   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01343   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01344   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01345   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01346   * @param  OCChannel: Timer output
01347   *                    This parameter can be one of the following values:
01348   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01349   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01350   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01351   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01352   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01353   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01354   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01355   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01356   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01357   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01358   * @retval HAL status
01359   */
01360 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,
01361                                            uint32_t TimerIdx,
01362                                            uint32_t OCChannel)
01363 {
01364   uint32_t interrupt;
01365
01366    /* Check the parameters */
01367   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01368
01369   /* Process Locked */
01370   __HAL_LOCK(hhrtim);
01371
01372   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01373
01374   /* Disable the timer output */
01375   hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
01376
01377   /* Get the interrupt to disable (depends on the output compare mode) */
01378   interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
01379
01380   /* Disable the timer interrupt */
01381   __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, interrupt);
01382
01383   /* Disable the timer counter */
01384   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01385
01386   hhrtim->State = HAL_HRTIM_STATE_READY;
01387
01388   /* Process Unlocked */
01389   __HAL_UNLOCK(hhrtim);
01390
01391   return HAL_OK;
01392 }
01393
01394 /**
01395   * @brief  Starts the output compare signal generation on the designed timer output
01396   *         (DMA request is enabled (see note below)).
01397   * @param  hhrtim: pointer to HAL HRTIM handle
01398   * @param  TimerIdx: Timer index
01399   *                   This parameter can be one of the following values:
01400   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01401   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01402   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01403   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01404   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01405   * @param  OCChannel: Timer output
01406   *                    This parameter can be one of the following values:
01407   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01408   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01409   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01410   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01411   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01412   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01413   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01414   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01415   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01416   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01417   * @param  SrcAddr: DMA transfer source address
01418   * @param  DestAddr: DMA transfer destination address
01419   * @param  Length: The length of data items (data size) to be transferred
01420   *                     from source to destination
01421   * @note  DMA request enabling depends on the chosen output compare mode
01422   *          Output toggle: compare match DMA request is enabled
01423   *          Output set active:  output set DMA request is enabled
01424   *          Output set inactive:  output reset DMA request is enabled
01425   * @retval HAL status
01426   */
01427 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,
01428                                              uint32_t TimerIdx,
01429                                              uint32_t OCChannel,
01430                                              uint32_t SrcAddr,
01431                                              uint32_t DestAddr,
01432                                              uint32_t Length)
01433 {
01434   DMA_HandleTypeDef * hdma;
01435   uint32_t dma_request;
01436
01437   /* Check the parameters */
01438   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01439
01440   if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
01441   {
01442      return HAL_BUSY;
01443   }
01444   if((hhrtim->State == HAL_HRTIM_STATE_READY))
01445   {
01446     if((SrcAddr == 0 ) || (DestAddr == 0 ) || (Length == 0))
01447     {
01448       return HAL_ERROR;
01449     }
01450     else
01451     {
01452       hhrtim->State = HAL_HRTIM_STATE_BUSY;
01453     }
01454   }
01455
01456   /* Process Locked */
01457   __HAL_LOCK(hhrtim);
01458
01459    /* Enable the timer output */
01460   hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
01461
01462   /* Get the DMA request to enable */
01463   dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
01464
01465   /* Get the timer DMA handler */
01466   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
01467
01468   /* Set the DMA error callback */
01469   hdma->XferErrorCallback = HRTIM_DMAError ;
01470
01471   /* Set the DMA transfer completed callback */
01472   hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
01473
01474   /* Enable the DMA channel */
01475   HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
01476
01477   /* Enable the timer DMA request */
01478   __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request);
01479
01480   /* Enable the timer counter */
01481   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01482
01483   hhrtim->State = HAL_HRTIM_STATE_READY;
01484
01485   /* Process Unlocked */
01486   __HAL_UNLOCK(hhrtim);
01487
01488   return HAL_OK;
01489 }
01490
01491 /**
01492   * @brief  Stops the output compare signal generation on the designed timer output
01493   *         (DMA request is disabled).
01494   * @param  hhrtim: pointer to HAL HRTIM handle
01495   * @param  TimerIdx: Timer index
01496   *                   This parameter can be one of the following values:
01497   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01498   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01499   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01500   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01501   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01502   * @param  OCChannel: Timer output
01503   *                    This parameter can be one of the following values:
01504   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01505   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01506   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01507   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01508   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01509   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01510   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01511   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01512   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01513   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01514   * @retval HAL status
01515   */
01516 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,
01517                                             uint32_t TimerIdx,
01518                                             uint32_t OCChannel)
01519 {
01520   DMA_HandleTypeDef * hdma;
01521   uint32_t dma_request;
01522
01523   /* Check the parameters */
01524   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01525
01526   /* Process Locked */
01527   __HAL_LOCK(hhrtim);
01528
01529   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01530
01531   /* Disable the timer output */
01532   hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
01533
01534   /* Get the timer DMA handler */
01535   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
01536
01537   /* Disable the DMA */
01538   HAL_DMA_Abort(hdma);
01539
01540   /* Get the DMA request to disable */
01541   dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
01542
01543   /* Disable the timer DMA request */
01544   __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, dma_request);
01545
01546   /* Disable the timer counter */
01547   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01548
01549   hhrtim->State = HAL_HRTIM_STATE_READY;
01550
01551   /* Process Unlocked */
01552   __HAL_UNLOCK(hhrtim);
01553
01554   return HAL_OK;
01555 }
01556
01557 /**
01558   * @}
01559   */
01560
01561 /** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
01562  *  @brief    Simple PWM output functions
01563
01564 @verbatim
01565  ===============================================================================
01566               ##### Simple PWM output functions #####
01567  ===============================================================================
01568     [..]  This section provides functions allowing to:
01569       (+) Configure simple PWM output channel
01570       (+) Start simple PWM output
01571       (+) Stop simple PWM output
01572       (+) Start simple PWM output and enable interrupt
01573       (+) Stop simple PWM output and disable interrupt
01574       (+) Start simple PWM output and enable DMA transfer
01575       (+) Stop simple PWM output and disable DMA transfer
01576       -@- When a HRTIM timer operates in simple PWM output mode
01577           the output level is set to a programmable value when a match is
01578           found between the compare register and the counter and reset when
01579           the timer period is reached. Duty cycle is determined by the
01580           comparison value.
01581           Compare unit 1 is automatically associated to output 1
01582           Compare unit 2 is automatically associated to output 2
01583
01584 @endverbatim
01585   * @{
01586   */
01587
01588 /**
01589   * @brief  Configures an output in simple PWM mode
01590   * @param  hhrtim: pointer to HAL HRTIM handle
01591   * @param  TimerIdx: Timer index
01592   *                   This parameter can be one of the following values:
01593   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01594   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01595   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01596   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01597   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01598   * @param  PWMChannel: Timer output
01599   *                    This parameter can be one of the following values:
01600   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01601   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01602   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01603   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01604   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01605   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01606   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01607   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01608   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01609   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01610   * @param  pSimplePWMChannelCfg: pointer to the simple PWM output configuration structure
01611   * @note When the timer operates in simple PWM output mode:
01612   *         Output 1 is implicitly controlled by the compare unit 1
01613   *         Output 2 is implicitly controlled by the compare unit 2
01614   *       Output Set/Reset crossbar is set as follows:
01615   *         Output 1: SETx1R = CMP1, RSTx1R = PER
01616   *         Output 2: SETx2R = CMP2, RST2R = PER
01617   * @note When Simple PWM mode is used the registers preload mechanism is
01618   *       enabled (otherwise the behavior is not guaranteed).
01619   * @retval HAL status
01620   */
01621 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,
01622                                                   uint32_t TimerIdx,
01623                                                   uint32_t PWMChannel,
01624                                                   HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg)
01625 {
01626   uint32_t CompareUnit = 0xFFFFFFFFU;
01627   HRTIM_CompareCfgTypeDef CompareCfg;
01628   HRTIM_OutputCfgTypeDef OutputCfg;
01629   uint32_t hrtim_timcr;
01630
01631   /* Check parameters */
01632   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
01633   assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimplePWMChannelCfg->Polarity));
01634   assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel));
01635
01636   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
01637   {
01638      return HAL_BUSY;
01639   }
01640
01641   /* Process Locked */
01642   __HAL_LOCK(hhrtim);  hhrtim->State = HAL_HRTIM_STATE_BUSY;
01643
01644   /* Configure timer compare unit */
01645   switch (PWMChannel)
01646   {
01647   case HRTIM_OUTPUT_TA1:
01648   case HRTIM_OUTPUT_TB1:
01649   case HRTIM_OUTPUT_TC1:
01650   case HRTIM_OUTPUT_TD1:
01651   case HRTIM_OUTPUT_TE1:
01652     {
01653       CompareUnit = HRTIM_COMPAREUNIT_1;
01654     }
01655     break;
01656   case HRTIM_OUTPUT_TA2:
01657   case HRTIM_OUTPUT_TB2:
01658   case HRTIM_OUTPUT_TC2:
01659   case HRTIM_OUTPUT_TD2:
01660   case HRTIM_OUTPUT_TE2:
01661     {
01662       CompareUnit = HRTIM_COMPAREUNIT_2;
01663     }
01664     break;
01665   }
01666
01667   CompareCfg.CompareValue = pSimplePWMChannelCfg->Pulse;
01668   CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
01669   CompareCfg.AutoDelayedTimeout = 0;
01670
01671   HRTIM_CompareUnitConfig(hhrtim,
01672                           TimerIdx,
01673                           CompareUnit,
01674                           &CompareCfg);
01675
01676   /* Configure timer output */
01677   OutputCfg.Polarity = pSimplePWMChannelCfg->Polarity;
01678   OutputCfg.IdleLevel = pSimplePWMChannelCfg->IdleLevel;
01679   OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
01680   OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
01681   OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
01682   OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
01683
01684   if (CompareUnit == HRTIM_COMPAREUNIT_1)
01685   {
01686     OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
01687   }
01688   else
01689   {
01690     OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
01691   }
01692   OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
01693
01694   HRTIM_OutputConfig(hhrtim,
01695                      TimerIdx,
01696                      PWMChannel,
01697                      &OutputCfg);
01698 /* Enable the registers preload mechanism */
01699   hrtim_timcr   = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
01700   hrtim_timcr |= HRTIM_TIMCR_PREEN;
01701   hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR  = hrtim_timcr;
01702
01703   hhrtim->State = HAL_HRTIM_STATE_READY;
01704
01705   /* Process Unlocked */
01706   __HAL_UNLOCK(hhrtim);
01707
01708   return HAL_OK;
01709 }
01710
01711 /**
01712   * @brief  Starts the PWM output signal generation on the designed timer output
01713   * @param  hhrtim: pointer to HAL HRTIM handle
01714   * @param  TimerIdx: Timer index
01715   *                   This parameter can be one of the following values:
01716   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01717   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01718   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01719   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01720   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01721   * @param  PWMChannel: Timer output
01722   *                    This parameter can be one of the following values:
01723   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01724   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01725   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01726   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01727   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01728   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01729   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01730   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01731   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01732   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01733   * @retval HAL status
01734   */
01735 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,
01736                                           uint32_t TimerIdx,
01737                                           uint32_t PWMChannel)
01738 {
01739    /* Check the parameters */
01740   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
01741
01742   /* Process Locked */
01743   __HAL_LOCK(hhrtim);
01744
01745   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01746
01747   /* Enable the timer output */
01748   hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
01749
01750   /* Enable the timer counter */
01751   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01752
01753   hhrtim->State = HAL_HRTIM_STATE_READY;
01754
01755   /* Process Unlocked */
01756   __HAL_UNLOCK(hhrtim);
01757
01758   return HAL_OK;
01759 }
01760
01761 /**
01762   * @brief  Stops the PWM output signal generation on the designed timer output
01763   * @param  hhrtim: pointer to HAL HRTIM handle
01764   * @param  TimerIdx: Timer index
01765   *                   This parameter can be one of the following values:
01766   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01767   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01768   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01769   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01770   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01771   * @param  PWMChannel: Timer output
01772   *                    This parameter can be one of the following values:
01773   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01774   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01775   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01776   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01777   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01778   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01779   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01780   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01781   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01782   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01783   * @retval HAL status
01784   */
01785 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,
01786                                          uint32_t TimerIdx,
01787                                          uint32_t PWMChannel)
01788 {
01789    /* Check the parameters */
01790   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
01791
01792   /* Process Locked */
01793   __HAL_LOCK(hhrtim);
01794
01795   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01796
01797   /* Disable the timer output */
01798   hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
01799
01800   /* Disable the timer counter */
01801   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01802
01803   hhrtim->State = HAL_HRTIM_STATE_READY;
01804
01805   /* Process Unlocked */
01806   __HAL_UNLOCK(hhrtim);
01807
01808   return HAL_OK;
01809 }
01810
01811 /**
01812   * @brief  Starts the PWM output signal generation on the designed timer output
01813   *         (The compare interrupt is enabled).
01814   * @param  hhrtim: pointer to HAL HRTIM handle
01815   * @param  TimerIdx: Timer index
01816   *                   This parameter can be one of the following values:
01817   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01818   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01819   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01820   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01821   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01822   * @param  PWMChannel: Timer output
01823   *                    This parameter can be one of the following values:
01824   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01825   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01826   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01827   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01828   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01829   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01830   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01831   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01832   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01833   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01834   * @retval HAL status
01835   */
01836 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,
01837                                              uint32_t TimerIdx,
01838                                              uint32_t PWMChannel)
01839 {
01840    /* Check the parameters */
01841   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
01842
01843   /* Process Locked */
01844   __HAL_LOCK(hhrtim);
01845
01846   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01847
01848   /* Enable the timer output */
01849   hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
01850
01851   /* Enable the timer interrupt (depends on the PWM output) */
01852   switch (PWMChannel)
01853   {
01854   case HRTIM_OUTPUT_TA1:
01855   case HRTIM_OUTPUT_TB1:
01856   case HRTIM_OUTPUT_TC1:
01857   case HRTIM_OUTPUT_TD1:
01858   case HRTIM_OUTPUT_TE1:
01859     {
01860       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
01861     }
01862     break;
01863   case HRTIM_OUTPUT_TA2:
01864   case HRTIM_OUTPUT_TB2:
01865   case HRTIM_OUTPUT_TC2:
01866   case HRTIM_OUTPUT_TD2:
01867   case HRTIM_OUTPUT_TE2:
01868     {
01869       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
01870     }
01871     break;
01872   }
01873
01874   /* Enable the timer counter */
01875   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01876
01877   hhrtim->State = HAL_HRTIM_STATE_READY;
01878
01879   /* Process Unlocked */
01880   __HAL_UNLOCK(hhrtim);
01881
01882   return HAL_OK;
01883 }
01884
01885 /**
01886   * @brief  Stops the PWM output signal generation on the designed timer output
01887   *         (The compare interrupt is disabled).
01888   * @param  hhrtim: pointer to HAL HRTIM handle
01889   * @param  TimerIdx: Timer index
01890   *                   This parameter can be one of the following values:
01891   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01892   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01893   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01894   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01895   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01896   * @param  PWMChannel: Timer output
01897   *                    This parameter can be one of the following values:
01898   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01899   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01900   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01901   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01902   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01903   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01904   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01905   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01906   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01907   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01908   * @retval HAL status
01909   */
01910 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,
01911                                             uint32_t TimerIdx,
01912                                             uint32_t PWMChannel)
01913 {
01914    /* Check the parameters */
01915   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
01916
01917   /* Process Locked */
01918   __HAL_LOCK(hhrtim);
01919
01920   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01921
01922   /* Disable the timer output */
01923   hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
01924
01925   /* Disable the timer interrupt (depends on the PWM output) */
01926   switch (PWMChannel)
01927   {
01928   case HRTIM_OUTPUT_TA1:
01929   case HRTIM_OUTPUT_TB1:
01930   case HRTIM_OUTPUT_TC1:
01931   case HRTIM_OUTPUT_TD1:
01932   case HRTIM_OUTPUT_TE1:
01933     {
01934       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
01935     }
01936     break;
01937   case HRTIM_OUTPUT_TA2:
01938   case HRTIM_OUTPUT_TB2:
01939   case HRTIM_OUTPUT_TC2:
01940   case HRTIM_OUTPUT_TD2:
01941   case HRTIM_OUTPUT_TE2:
01942     {
01943       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
01944     }
01945     break;
01946   }
01947
01948   /* Disable the timer counter */
01949   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01950
01951   hhrtim->State = HAL_HRTIM_STATE_READY;
01952
01953   /* Process Unlocked */
01954   __HAL_UNLOCK(hhrtim);
01955
01956   return HAL_OK;
01957 }
01958
01959 /**
01960   * @brief  Starts the PWM output signal generation on the designed timer output
01961   *         (The compare DMA request is enabled).
01962   * @param  hhrtim: pointer to HAL HRTIM handle
01963   * @param  TimerIdx: Timer index
01964   *                   This parameter can be one of the following values:
01965   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01966   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01967   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01968   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01969   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01970   * @param  PWMChannel: Timer output
01971   *                    This parameter can be one of the following values:
01972   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01973   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01974   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01975   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01976   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01977   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01978   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01979   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01980   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01981   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01982   * @param  SrcAddr: DMA transfer source address
01983   * @param  DestAddr: DMA transfer destination address
01984   * @param  Length: The length of data items (data size) to be transferred
01985   *                     from source to destination
01986   * @retval HAL status
01987   */
01988 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
01989                                               uint32_t TimerIdx,
01990                                               uint32_t PWMChannel,
01991                                               uint32_t SrcAddr,
01992                                               uint32_t DestAddr,
01993                                               uint32_t Length)
01994 {
01995   DMA_HandleTypeDef * hdma;
01996
01997   /* Check the parameters */
01998   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
01999
02000   if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
02001   {
02002      return HAL_BUSY;
02003   }
02004   if((hhrtim->State == HAL_HRTIM_STATE_READY))
02005   {
02006     if((SrcAddr == 0 ) || (DestAddr == 0 ) || (Length == 0))
02007     {
02008       return HAL_ERROR;
02009     }
02010     else
02011     {
02012       hhrtim->State = HAL_HRTIM_STATE_BUSY;
02013     }
02014   }
02015
02016   /* Process Locked */
02017   __HAL_LOCK(hhrtim);
02018
02019   /* Enable the timer output */
02020   hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
02021
02022   /* Get the timer DMA handler */
02023   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
02024
02025   /* Set the DMA error callback */
02026   hdma->XferErrorCallback = HRTIM_DMAError ;
02027
02028   /* Set the DMA transfer completed callback */
02029   hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
02030
02031   /* Enable the DMA channel */
02032   HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
02033
02034   /* Enable the timer DMA request */
02035   switch (PWMChannel)
02036   {
02037   case HRTIM_OUTPUT_TA1:
02038   case HRTIM_OUTPUT_TB1:
02039   case HRTIM_OUTPUT_TC1:
02040   case HRTIM_OUTPUT_TD1:
02041   case HRTIM_OUTPUT_TE1:
02042     {
02043       __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
02044     }
02045     break;
02046   case HRTIM_OUTPUT_TA2:
02047   case HRTIM_OUTPUT_TB2:
02048   case HRTIM_OUTPUT_TC2:
02049   case HRTIM_OUTPUT_TD2:
02050   case HRTIM_OUTPUT_TE2:
02051     {
02052       __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
02053     }
02054     break;
02055   }
02056
02057   /* Enable the timer counter */
02058   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02059
02060   hhrtim->State = HAL_HRTIM_STATE_READY;
02061
02062   /* Process Unlocked */
02063   __HAL_UNLOCK(hhrtim);
02064
02065   return HAL_OK;
02066 }
02067
02068 /**
02069   * @brief  Stops the PWM output signal generation on the designed timer output
02070   *         (The compare DMA request is disabled).
02071   * @param  hhrtim: pointer to HAL HRTIM handle
02072   * @param  TimerIdx: Timer index
02073   *                   This parameter can be one of the following values:
02074   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02075   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02076   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02077   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02078   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02079   * @param  PWMChannel: Timer output
02080   *                    This parameter can be one of the following values:
02081   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
02082   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
02083   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
02084   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
02085   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
02086   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
02087   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
02088   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
02089   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
02090   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
02091   * @retval HAL status
02092   */
02093 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,
02094                                              uint32_t TimerIdx,
02095                                              uint32_t PWMChannel)
02096 {
02097   DMA_HandleTypeDef * hdma;
02098
02099   /* Check the parameters */
02100   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
02101
02102   /* Process Locked */
02103   __HAL_LOCK(hhrtim);
02104
02105   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02106
02107   /* Disable the timer output */
02108   hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
02109
02110   /* Get the timer DMA handler */
02111   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
02112
02113   /* Disable the DMA */
02114   HAL_DMA_Abort(hdma);
02115
02116   /* Disable the timer DMA request */
02117   switch (PWMChannel)
02118   {
02119   case HRTIM_OUTPUT_TA1:
02120   case HRTIM_OUTPUT_TB1:
02121   case HRTIM_OUTPUT_TC1:
02122   case HRTIM_OUTPUT_TD1:
02123   case HRTIM_OUTPUT_TE1:
02124     {
02125       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
02126     }
02127     break;
02128   case HRTIM_OUTPUT_TA2:
02129   case HRTIM_OUTPUT_TB2:
02130   case HRTIM_OUTPUT_TC2:
02131   case HRTIM_OUTPUT_TD2:
02132   case HRTIM_OUTPUT_TE2:
02133     {
02134       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
02135     }
02136     break;
02137   }
02138
02139   /* Disable the timer counter */
02140   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02141
02142   hhrtim->State = HAL_HRTIM_STATE_READY;
02143
02144   /* Process Unlocked */
02145   __HAL_UNLOCK(hhrtim);
02146
02147   return HAL_OK;
02148 }
02149
02150 /**
02151   * @}
02152   */
02153
02154 /** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions
02155  *  @brief    Simple input capture functions
02156
02157 @verbatim
02158  ===============================================================================
02159               ##### Simple input capture functions #####
02160  ===============================================================================
02161     [..]  This section provides functions allowing to:
02162       (+) Configure simple input capture channel
02163       (+) Start simple input capture
02164       (+) Stop simple input capture
02165       (+) Start simple input capture and enable interrupt
02166       (+) Stop simple input capture and disable interrupt
02167       (+) Start simple input capture and enable DMA transfer
02168       (+) Stop simple input capture and disable DMA transfer
02169       -@- When a HRTIM timer operates in simple input capture mode
02170           the Capture Register (HRTIM_CPT1/2xR) is used to latch the
02171          value of the timer counter counter after a transition detected
02172          on a given external event input.
02173
02174 @endverbatim
02175   * @{
02176   */
02177
02178 /**
02179   * @brief  Configures a simple capture
02180   * @param  hhrtim: pointer to HAL HRTIM handle
02181   * @param  TimerIdx: Timer index
02182   *                   This parameter can be one of the following values:
02183   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02184   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02185   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02186   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02187   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02188   * @param  CaptureChannel: Capture unit
02189   *                    This parameter can be one of the following values:
02190   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02191   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02192   * @param  pSimpleCaptureChannelCfg: pointer to the simple capture configuration structure
02193   * @note When the timer operates in simple capture mode the capture is trigerred
02194   *       by the designated external event and GPIO input is implicitly used as event source.
02195   *       The cature can be triggered by a rising edge, a falling edge or both
02196   *       edges on event channel.
02197   * @retval HAL status
02198   */
02199 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,
02200                                                       uint32_t TimerIdx,
02201                                                       uint32_t CaptureChannel,
02202                                                       HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg)
02203 {
02204   HRTIM_EventCfgTypeDef EventCfg;
02205
02206   /* Check parameters */
02207   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02208   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02209   assert_param(IS_HRTIM_EVENT(pSimpleCaptureChannelCfg->Event));
02210   assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleCaptureChannelCfg->EventSensitivity,
02211                                       pSimpleCaptureChannelCfg->EventPolarity));
02212   assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleCaptureChannelCfg->EventSensitivity));
02213   assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event,
02214                                     pSimpleCaptureChannelCfg->EventFilter));
02215
02216   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
02217   {
02218      return HAL_BUSY;
02219   }
02220
02221   /* Process Locked */
02222   __HAL_LOCK(hhrtim);
02223
02224   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02225
02226   /* Configure external event channel */
02227   EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
02228   EventCfg.Filter = pSimpleCaptureChannelCfg->EventFilter;
02229   EventCfg.Polarity = pSimpleCaptureChannelCfg->EventPolarity;
02230   EventCfg.Sensitivity = pSimpleCaptureChannelCfg->EventSensitivity;
02231   EventCfg.Source = HRTIM_EVENTSRC_1;
02232
02233   HRTIM_EventConfig(hhrtim,
02234                     pSimpleCaptureChannelCfg->Event,
02235                     &EventCfg);
02236
02237   /* Memorize capture trigger (will be configured when the capture is started */
02238   HRTIM_CaptureUnitConfig(hhrtim,
02239                           TimerIdx,
02240                           CaptureChannel,
02241                           pSimpleCaptureChannelCfg->Event);
02242
02243   hhrtim->State = HAL_HRTIM_STATE_READY;
02244
02245   /* Process Unlocked */
02246   __HAL_UNLOCK(hhrtim);
02247
02248   return HAL_OK;
02249 }
02250
02251 /**
02252   * @brief  Enables a simple capture on the designed capture unit
02253   * @param  hhrtim: pointer to HAL HRTIM handle
02254   * @param  TimerIdx: Timer index
02255   *                   This parameter can be one of the following values:
02256   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02257   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02258   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02259   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02260   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02261   * @param  CaptureChannel: Timer output
02262   *                    This parameter can be one of the following values:
02263   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02264   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02265   * @retval HAL status
02266   * @note  The external event triggering the capture is available for all timing
02267   *        units. It can be used directly and is active as soon as the timing
02268   *        unit counter is enabled.
02269   */
02270 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,
02271                                               uint32_t TimerIdx,
02272                                               uint32_t CaptureChannel)
02273 {
02274    /* Check the parameters */
02275   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02276   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02277
02278   /* Process Locked */
02279   __HAL_LOCK(hhrtim);
02280
02281   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02282
02283   /* Set the capture unit trigger */
02284   switch (CaptureChannel)
02285   {
02286   case HRTIM_CAPTUREUNIT_1:
02287     {
02288       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
02289     }
02290     break;
02291   case HRTIM_CAPTUREUNIT_2:
02292     {
02293       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
02294     }
02295     break;
02296   }
02297
02298   /* Enable the timer counter */
02299   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02300
02301   hhrtim->State = HAL_HRTIM_STATE_READY;
02302
02303   /* Process Unlocked */
02304   __HAL_UNLOCK(hhrtim);
02305
02306   return HAL_OK;
02307 }
02308
02309 /**
02310   * @brief  Disables a simple capture on the designed capture unit
02311   * @param  hhrtim: pointer to HAL HRTIM handle
02312   * @param  TimerIdx: Timer index
02313   *                   This parameter can be one of the following values:
02314   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02315   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02316   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02317   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02318   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02319   * @param  CaptureChannel: Timer output
02320   *                    This parameter can be one of the following values:
02321   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02322   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02323   * @retval HAL status
02324   */
02325 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,
02326                                              uint32_t TimerIdx,
02327                                              uint32_t CaptureChannel)
02328 {
02329    /* Check the parameters */
02330   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02331   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02332
02333   /* Process Locked */
02334   __HAL_LOCK(hhrtim);
02335
02336   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02337
02338   /* Set the capture unit trigger */
02339   switch (CaptureChannel)
02340   {
02341   case HRTIM_CAPTUREUNIT_1:
02342     {
02343       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
02344     }
02345     break;
02346   case HRTIM_CAPTUREUNIT_2:
02347     {
02348       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
02349     }
02350     break;
02351   }
02352
02353   /* Disable the timer counter */
02354   if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
02355       (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
02356   {
02357     __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02358   }
02359
02360   hhrtim->State = HAL_HRTIM_STATE_READY;
02361
02362   /* Process Unlocked */
02363   __HAL_UNLOCK(hhrtim);
02364
02365   return HAL_OK;
02366 }
02367
02368 /**
02369   * @brief  Enables a basic capture on the designed capture unit
02370   *         (Capture interrupt is enabled).
02371   * @param  hhrtim: pointer to HAL HRTIM handle
02372   * @param  TimerIdx: Timer index
02373   *                   This parameter can be one of the following values:
02374   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02375   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02376   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02377   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02378   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02379   * @param  CaptureChannel: Timer output
02380   *                    This parameter can be one of the following values:
02381   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02382   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02383   * @retval HAL status
02384   */
02385 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,
02386                                                  uint32_t TimerIdx,
02387                                                  uint32_t CaptureChannel)
02388 {
02389    /* Check the parameters */
02390   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02391   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02392
02393   /* Process Locked */
02394   __HAL_LOCK(hhrtim);
02395
02396   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02397
02398   /* Set the capture unit trigger */
02399   switch (CaptureChannel)
02400   {
02401   case HRTIM_CAPTUREUNIT_1:
02402     {
02403       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
02404
02405       /* Enable the capture unit 1 interrupt */
02406       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
02407     }
02408     break;
02409   case HRTIM_CAPTUREUNIT_2:
02410     {
02411       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
02412
02413       /* Enable the capture unit 2 interrupt */
02414       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
02415     }
02416     break;
02417   }
02418
02419   /* Enable the timer counter */
02420   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02421
02422   hhrtim->State = HAL_HRTIM_STATE_READY;
02423
02424   /* Process Unlocked */
02425   __HAL_UNLOCK(hhrtim);
02426
02427   return HAL_OK;
02428 }
02429
02430 /**
02431   * @brief  Disables a basic capture on the designed capture unit
02432   *         (Capture interrupt is disabled).
02433   * @param  hhrtim: pointer to HAL HRTIM handle
02434   * @param  TimerIdx: Timer index
02435   *                   This parameter can be one of the following values:
02436   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02437   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02438   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02439   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02440   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02441   * @param  CaptureChannel: Timer output
02442   *                    This parameter can be one of the following values:
02443   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02444   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02445   * @retval HAL status
02446   */
02447 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,
02448                                                 uint32_t TimerIdx,
02449                                                 uint32_t CaptureChannel)
02450 {
02451    /* Check the parameters */
02452   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02453   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02454
02455   /* Process Locked */
02456   __HAL_LOCK(hhrtim);
02457
02458   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02459
02460   /* Set the capture unit trigger */
02461   switch (CaptureChannel)
02462   {
02463   case HRTIM_CAPTUREUNIT_1:
02464     {
02465       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
02466
02467       /* Disable the capture unit 1 interrupt */
02468       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
02469     }
02470     break;
02471   case HRTIM_CAPTUREUNIT_2:
02472     {
02473       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
02474
02475       /* Disable the capture unit 2 interrupt */
02476       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
02477     }
02478     break;
02479   }
02480
02481   /* Disable the timer counter */
02482   if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
02483       (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
02484   {
02485     __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02486   }
02487
02488   hhrtim->State = HAL_HRTIM_STATE_READY;
02489
02490   /* Process Unlocked */
02491   __HAL_UNLOCK(hhrtim);
02492
02493   return HAL_OK;
02494 }
02495
02496 /**
02497   * @brief  Enables a basic capture on the designed capture unit
02498   *         (Capture DMA request is enabled).
02499   * @param  hhrtim: pointer to HAL HRTIM handle
02500   * @param  TimerIdx: Timer index
02501   *                   This parameter can be one of the following values:
02502   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02503   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02504   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02505   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02506   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02507   * @param  CaptureChannel: Timer output
02508   *                    This parameter can be one of the following values:
02509   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02510   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02511   * @param  SrcAddr: DMA transfer source address
02512   * @param  DestAddr: DMA transfer destination address
02513   * @param  Length: The length of data items (data size) to be transferred
02514   *                     from source to destination
02515   * @retval HAL status
02516   */
02517 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,
02518                                                   uint32_t TimerIdx,
02519                                                   uint32_t CaptureChannel,
02520                                                   uint32_t SrcAddr,
02521                                                   uint32_t DestAddr,
02522                                                   uint32_t Length)
02523 {
02524   DMA_HandleTypeDef * hdma;
02525
02526    /* Check the parameters */
02527   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02528   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02529
02530   /* Process Locked */
02531   __HAL_LOCK(hhrtim);
02532
02533   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02534
02535   /* Get the timer DMA handler */
02536   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
02537
02538   /* Set the DMA error callback */
02539   hdma->XferErrorCallback = HRTIM_DMAError ;
02540
02541   /* Set the DMA transfer completed callback */
02542   hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
02543
02544   /* Enable the DMA channel */
02545   HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
02546
02547   switch (CaptureChannel)
02548   {
02549   case HRTIM_CAPTUREUNIT_1:
02550     {
02551       /* Set the capture unit trigger */
02552       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
02553
02554       __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
02555     }
02556     break;
02557   case HRTIM_CAPTUREUNIT_2:
02558     {
02559       /* Set the capture unit trigger */
02560       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
02561
02562       /* Enable the timer DMA request */
02563       __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
02564     }
02565     break;
02566   }
02567
02568   /* Enable the timer counter */
02569   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02570
02571   hhrtim->State = HAL_HRTIM_STATE_READY;
02572
02573   /* Process Unlocked */
02574   __HAL_UNLOCK(hhrtim);
02575
02576   return HAL_OK;
02577 }
02578
02579 /**
02580   * @brief  Disables a basic capture on the designed capture unit
02581   *         (Capture DMA request is disabled).
02582   * @param  hhrtim: pointer to HAL HRTIM handle
02583   * @param  TimerIdx: Timer index
02584   *                   This parameter can be one of the following values:
02585   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02586   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02587   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02588   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02589   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02590   * @param  CaptureChannel: Timer output
02591   *                    This parameter can be one of the following values:
02592   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02593   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02594   * @retval HAL status
02595   */
02596 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
02597                                                  uint32_t TimerIdx,
02598                                                  uint32_t CaptureChannel)
02599 {
02600   DMA_HandleTypeDef * hdma;
02601
02602   /* Check the parameters */
02603   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02604   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02605
02606   /* Process Locked */
02607   __HAL_LOCK(hhrtim);
02608
02609   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02610
02611   /* Get the timer DMA handler */
02612   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
02613
02614   /* Disable the DMA */
02615   HAL_DMA_Abort(hdma);
02616
02617   switch (CaptureChannel)
02618   {
02619   case HRTIM_CAPTUREUNIT_1:
02620     {
02621       /* Reset the capture unit trigger */
02622       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
02623
02624       /* Disable the capture unit 1 DMA request */
02625       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
02626     }
02627     break;
02628   case HRTIM_CAPTUREUNIT_2:
02629     {
02630       /* Reset the capture unit trigger */
02631       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
02632
02633       /* Disable the capture unit 2 DMA request */
02634       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
02635     }
02636     break;
02637   }
02638
02639   /* Disable the timer counter */
02640   if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
02641       (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
02642   {
02643     __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02644   }
02645
02646   hhrtim->State = HAL_HRTIM_STATE_READY;
02647
02648   /* Process Unlocked */
02649   __HAL_UNLOCK(hhrtim);
02650
02651   return HAL_OK;
02652 }
02653
02654 /**
02655   * @}
02656   */
02657
02658 /** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
02659  *  @brief    Simple one pulse functions
02660
02661 @verbatim
02662  ===============================================================================
02663               ##### Simple one pulse functions #####
02664  ===============================================================================
02665     [..]  This section provides functions allowing to:
02666       (+) Configure one pulse channel
02667       (+) Start one pulse generation
02668       (+) Stop one pulse generation
02669       (+) Start one pulse generation and enable interrupt
02670       (+) Stop one pulse generation and disable interrupt
02671       -@- When a HRTIM timer operates in simple one pulse mode
02672           the timer counter is started in response to transition detected
02673           on a given external event input to generate a pulse with a
02674           programmable length after a programmable delay.
02675
02676 @endverbatim
02677   * @{
02678   */
02679
02680 /**
02681   * @brief  Configures an output simple one pulse mode
02682   * @param  hhrtim: pointer to HAL HRTIM handle
02683   * @param  TimerIdx: Timer index
02684   *                   This parameter can be one of the following values:
02685   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02686   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02687   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02688   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02689   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02690   * @param  OnePulseChannel: Timer output
02691   *                    This parameter can be one of the following values:
02692   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
02693   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
02694   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
02695   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
02696   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
02697   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
02698   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
02699   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
02700   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
02701   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
02702   * @param  pSimpleOnePulseChannelCfg: pointer to the basic one pulse output configuration structure
02703   * @note When the timer operates in basic one pulse mode:
02704   *         the timer counter is implicitely started by the reset event,
02705   *         the reset of the timer counter is triggered by the designated external event
02706   *         GPIO input is implicitly used as event source,
02707   *         Output 1 is implicitly controlled by the compare unit 1,
02708   *         Output 2 is implicitly controlled by the compare unit 2.
02709   *       Output Set/Reset crossbar is set as follows:
02710   *         Output 1: SETx1R = CMP1, RSTx1R = PER
02711   *         Output 2: SETx2R = CMP2, RST2R = PER
02712   * @retval HAL status
02713   * @note If HAL_HRTIM_SimpleOnePulseChannelConfig is called for both timer
02714   *       outputs, the reset event related configuration data provided in the
02715   *       second call will override the reset event related configuration data
02716   *       provided in the first call.
02717   */
02718 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,
02719                                                        uint32_t TimerIdx,
02720                                                        uint32_t OnePulseChannel,
02721                                                        HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg)
02722 {
02723   uint32_t CompareUnit = 0xFFFFFFFFU;
02724   HRTIM_CompareCfgTypeDef CompareCfg;
02725   HRTIM_OutputCfgTypeDef OutputCfg;
02726   HRTIM_EventCfgTypeDef EventCfg;
02727
02728   /* Check parameters */
02729   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
02730   assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOnePulseChannelCfg->OutputPolarity));
02731   assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOnePulseChannelCfg->OutputIdleLevel));
02732   assert_param(IS_HRTIM_EVENT(pSimpleOnePulseChannelCfg->Event));
02733   assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleOnePulseChannelCfg->EventSensitivity,
02734                                       pSimpleOnePulseChannelCfg->EventPolarity));
02735   assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleOnePulseChannelCfg->EventSensitivity));
02736   assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event,
02737                                     pSimpleOnePulseChannelCfg->EventFilter));
02738
02739   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
02740   {
02741      return HAL_BUSY;
02742   }
02743
02744   /* Process Locked */
02745   __HAL_LOCK(hhrtim);
02746
02747   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02748
02749   /* Configure timer compare unit */
02750   switch (OnePulseChannel)
02751   {
02752   case HRTIM_OUTPUT_TA1:
02753   case HRTIM_OUTPUT_TB1:
02754   case HRTIM_OUTPUT_TC1:
02755   case HRTIM_OUTPUT_TD1:
02756   case HRTIM_OUTPUT_TE1:
02757     {
02758       CompareUnit = HRTIM_COMPAREUNIT_1;
02759     }
02760     break;
02761   case HRTIM_OUTPUT_TA2:
02762   case HRTIM_OUTPUT_TB2:
02763   case HRTIM_OUTPUT_TC2:
02764   case HRTIM_OUTPUT_TD2:
02765   case HRTIM_OUTPUT_TE2:
02766     {
02767       CompareUnit = HRTIM_COMPAREUNIT_2;
02768     }
02769     break;
02770   }
02771
02772   CompareCfg.CompareValue = pSimpleOnePulseChannelCfg->Pulse;
02773   CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
02774   CompareCfg.AutoDelayedTimeout = 0;
02775
02776   HRTIM_CompareUnitConfig(hhrtim,
02777                           TimerIdx,
02778                           CompareUnit,
02779                           &CompareCfg);
02780
02781   /* Configure timer output */
02782   OutputCfg.Polarity = pSimpleOnePulseChannelCfg->OutputPolarity;
02783   OutputCfg.IdleLevel = pSimpleOnePulseChannelCfg->OutputIdleLevel;
02784   OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
02785   OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
02786   OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
02787   OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
02788
02789   if (CompareUnit == HRTIM_COMPAREUNIT_1)
02790   {
02791     OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
02792   }
02793   else
02794   {
02795     OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
02796   }
02797   OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
02798
02799   HRTIM_OutputConfig(hhrtim,
02800                      TimerIdx,
02801                      OnePulseChannel,
02802                      &OutputCfg);
02803
02804   /* Configure external event channel */
02805   EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
02806   EventCfg.Filter = pSimpleOnePulseChannelCfg->EventFilter;
02807   EventCfg.Polarity = pSimpleOnePulseChannelCfg->EventPolarity;
02808   EventCfg.Sensitivity = pSimpleOnePulseChannelCfg->EventSensitivity;
02809   EventCfg.Source = HRTIM_EVENTSRC_1;
02810
02811   HRTIM_EventConfig(hhrtim,
02812                     pSimpleOnePulseChannelCfg->Event,
02813                     &EventCfg);
02814
02815   /* Configure the timer reset register */
02816   HRTIM_TIM_ResetConfig(hhrtim,
02817                         TimerIdx,
02818                         pSimpleOnePulseChannelCfg->Event);
02819
02820   hhrtim->State = HAL_HRTIM_STATE_READY;
02821
02822   /* Process Unlocked */
02823   __HAL_UNLOCK(hhrtim);
02824
02825   return HAL_OK;
02826 }
02827
02828 /**
02829   * @brief  Enables the simple one pulse signal generation on the designed output
02830   * @param  hhrtim: pointer to HAL HRTIM handle
02831   * @param  TimerIdx: Timer index
02832   *                   This parameter can be one of the following values:
02833   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02834   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02835   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02836   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02837   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02838   * @param  OnePulseChannel: Timer output
02839   *                    This parameter can be one of the following values:
02840   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
02841   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
02842   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
02843   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
02844   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
02845   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
02846   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
02847   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
02848   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
02849   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
02850   * @retval HAL status
02851   */
02852 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,
02853                                                 uint32_t TimerIdx,
02854                                                 uint32_t OnePulseChannel)
02855 {
02856    /* Check the parameters */
02857   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
02858
02859   /* Process Locked */
02860   __HAL_LOCK(hhrtim);
02861
02862   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02863
02864   /* Enable the timer output */
02865   hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
02866
02867   /* Enable the timer counter */
02868   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02869
02870   hhrtim->State = HAL_HRTIM_STATE_READY;
02871
02872   /* Process Unlocked */
02873   __HAL_UNLOCK(hhrtim);
02874
02875   return HAL_OK;
02876 }
02877
02878 /**
02879   * @brief  Disables the simple one pulse signal generation on the designed output
02880   * @param  hhrtim: pointer to HAL HRTIM handle
02881   * @param  TimerIdx: Timer index
02882   *                   This parameter can be one of the following values:
02883   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02884   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02885   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02886   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02887   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02888   * @param  OnePulseChannel: Timer output
02889   *                    This parameter can be one of the following values:
02890   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
02891   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
02892   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
02893   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
02894   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
02895   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
02896   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
02897   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
02898   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
02899   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
02900   * @retval HAL status
02901   */
02902 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,
02903                                               uint32_t TimerIdx,
02904                                               uint32_t OnePulseChannel)
02905 {
02906    /* Check the parameters */
02907   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
02908
02909   /* Process Locked */
02910   __HAL_LOCK(hhrtim);
02911
02912   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02913
02914   /* Disable the timer output */
02915   hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
02916
02917   /* Disable the timer counter */
02918   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02919
02920   hhrtim->State = HAL_HRTIM_STATE_READY;
02921
02922   /* Process Unlocked */
02923   __HAL_UNLOCK(hhrtim);
02924
02925   return HAL_OK;
02926 }
02927
02928 /**
02929   * @brief  Enables the simple one pulse signal generation on the designed output
02930   *         (The compare interrupt is enabled (pulse start)).
02931   * @param  hhrtim: pointer to HAL HRTIM handle
02932   * @param  TimerIdx: Timer index
02933   *                   This parameter can be one of the following values:
02934   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02935   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02936   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02937   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02938   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02939   * @param  OnePulseChannel: Timer output
02940   *                    This parameter can be one of the following values:
02941   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
02942   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
02943   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
02944   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
02945   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
02946   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
02947   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
02948   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
02949   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
02950   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
02951   * @retval HAL status
02952   */
02953 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,
02954                                                   uint32_t TimerIdx,
02955                                                   uint32_t OnePulseChannel)
02956 {
02957    /* Check the parameters */
02958   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
02959
02960   /* Process Locked */
02961   __HAL_LOCK(hhrtim);
02962
02963   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02964
02965   /* Enable the timer output */
02966   hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
02967
02968   /* Enable the timer interrupt (depends on the OnePulse output) */
02969   switch (OnePulseChannel)
02970   {
02971   case HRTIM_OUTPUT_TA1:
02972   case HRTIM_OUTPUT_TB1:
02973   case HRTIM_OUTPUT_TC1:
02974   case HRTIM_OUTPUT_TD1:
02975   case HRTIM_OUTPUT_TE1:
02976     {
02977       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
02978     }
02979     break;
02980   case HRTIM_OUTPUT_TA2:
02981   case HRTIM_OUTPUT_TB2:
02982   case HRTIM_OUTPUT_TC2:
02983   case HRTIM_OUTPUT_TD2:
02984   case HRTIM_OUTPUT_TE2:
02985     {
02986       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
02987     }
02988     break;
02989   }
02990
02991   /* Enable the timer counter */
02992   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02993
02994   hhrtim->State = HAL_HRTIM_STATE_READY;
02995
02996   /* Process Unlocked */
02997   __HAL_UNLOCK(hhrtim);
02998
02999   return HAL_OK;
03000 }
03001
03002 /**
03003   * @brief  Disables the simple one pulse signal generation on the designed output
03004   *         (The compare interrupt is disabled).
03005   * @param  hhrtim: pointer to HAL HRTIM handle
03006   * @param  TimerIdx: Timer index
03007   *                   This parameter can be one of the following values:
03008   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03009   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03010   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03011   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03012   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03013   * @param  OnePulseChannel: Timer output
03014   *                    This parameter can be one of the following values:
03015   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
03016   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
03017   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
03018   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
03019   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
03020   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
03021   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
03022   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
03023   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
03024   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
03025   * @retval HAL status
03026   */
03027 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,
03028                                                  uint32_t TimerIdx,
03029                                                  uint32_t OnePulseChannel)
03030 {
03031      /* Check the parameters */
03032   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
03033
03034   /* Process Locked */
03035   __HAL_LOCK(hhrtim);
03036
03037   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03038
03039   /* Disable the timer output */
03040   hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
03041
03042   /* Disable the timer interrupt (depends on the OnePulse output) */
03043   switch (OnePulseChannel)
03044   {
03045   case HRTIM_OUTPUT_TA1:
03046   case HRTIM_OUTPUT_TB1:
03047   case HRTIM_OUTPUT_TC1:
03048   case HRTIM_OUTPUT_TD1:
03049   case HRTIM_OUTPUT_TE1:
03050     {
03051       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
03052     }
03053     break;
03054   case HRTIM_OUTPUT_TA2:
03055   case HRTIM_OUTPUT_TB2:
03056   case HRTIM_OUTPUT_TC2:
03057   case HRTIM_OUTPUT_TD2:
03058   case HRTIM_OUTPUT_TE2:
03059     {
03060       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
03061     }
03062     break;
03063   }
03064
03065   /* Disable the timer counter */
03066   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
03067
03068   hhrtim->State = HAL_HRTIM_STATE_READY;
03069
03070   /* Process Unlocked */
03071   __HAL_UNLOCK(hhrtim);
03072
03073   return HAL_OK;
03074 }
03075
03076 /**
03077   * @}
03078   */
03079
03080 /** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions
03081  *  @brief    HRTIM configuration functions
03082
03083 @verbatim
03084  ===============================================================================
03085               ##### HRTIM configuration functions #####
03086  ===============================================================================
03087     [..]  This section provides functions allowing to configure the HRTIM
03088       resources shared by all the HRTIM timers operating in waveform mode:
03089       (+) Configure the burst mode controller
03090       (+) Configure an external event conditionning
03091       (+) Configure the external events sampling clock
03092       (+) Configure a fault conditionning
03093       (+) Enable or disable fault inputs
03094       (+) Configure the faults sampling clock
03095       (+) Configure an ADC trigger
03096
03097 @endverbatim
03098   * @{
03099   */
03100
03101 /**
03102   * @brief  Configures the burst mode feature of the HRTIM
03103   * @param  hhrtim: pointer to HAL HRTIM handle
03104   * @param  pBurstModeCfg: pointer to the burst mode configuration structure
03105   * @retval HAL status
03106   * @note This function must be called before starting the burst mode
03107   *       controller
03108   */
03109 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,
03110                                             HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
03111 {
03112   uint32_t hrtim_bmcr;
03113
03114   /* Check parameters */
03115   assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
03116   assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
03117   assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
03118   assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
03119   assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger));
03120
03121   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03122   {
03123      return HAL_BUSY;
03124   }
03125
03126   /* Process Locked */
03127   __HAL_LOCK(hhrtim);
03128
03129   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03130
03131   hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
03132
03133   /* Set the burst mode operating mode */
03134   hrtim_bmcr &= ~(HRTIM_BMCR_BMOM);
03135   hrtim_bmcr |= pBurstModeCfg->Mode;
03136
03137   /* Set the burst mode clock source */
03138   hrtim_bmcr &= ~(HRTIM_BMCR_BMCLK);
03139   hrtim_bmcr |= pBurstModeCfg->ClockSource;
03140
03141   /* Set the burst mode prescaler */
03142   hrtim_bmcr &= ~(HRTIM_BMCR_BMPRSC);
03143   hrtim_bmcr |= pBurstModeCfg->Prescaler;
03144
03145   /* Enable/disable burst mode registers preload */
03146   hrtim_bmcr &= ~(HRTIM_BMCR_BMPREN);
03147   hrtim_bmcr |= pBurstModeCfg->PreloadEnable;
03148
03149   /* Set the burst mode trigger */
03150   hhrtim->Instance->sCommonRegs.BMTRGR = pBurstModeCfg->Trigger;
03151
03152   /* Set the burst mode compare value */
03153   hhrtim->Instance->sCommonRegs.BMCMPR = pBurstModeCfg->IdleDuration;
03154
03155   /* Set the burst mode period */
03156   hhrtim->Instance->sCommonRegs.BMPER = pBurstModeCfg->Period;
03157
03158   /* Update the HRTIM registers */
03159   hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
03160
03161   hhrtim->State = HAL_HRTIM_STATE_READY;
03162
03163   /* Process Unlocked */
03164   __HAL_UNLOCK(hhrtim);
03165
03166   return HAL_OK;
03167 }
03168
03169 /**
03170   * @brief  Configures the conditioning of an external event
03171   * @param  hhrtim: pointer to HAL HRTIM handle
03172   * @param  Event: external event to configure
03173   *                    This parameter can be one of the following values:
03174   *                    @arg HRTIM_EVENT_1: External event 1
03175   *                    @arg HRTIM_EVENT_2: External event 2
03176   *                    @arg HRTIM_EVENT_3: External event 3
03177   *                    @arg HRTIM_EVENT_4: External event 4
03178   *                    @arg HRTIM_EVENT_5: External event 5
03179   *                    @arg HRTIM_EVENT_6: External event 6
03180   *                    @arg HRTIM_EVENT_7: External event 7
03181   *                    @arg HRTIM_EVENT_8: External event 8
03182   *                    @arg HRTIM_EVENT_9: External event 9
03183   *                    @arg HRTIM_EVENT_10: External event 10
03184   * @param  pEventCfg: pointer to the event conditioning configuration structure
03185   * @note This function must be called before starting the timer
03186   * @retval HAL status
03187   */
03188 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
03189                                         uint32_t Event,
03190                                         HRTIM_EventCfgTypeDef* pEventCfg)
03191 {
03192   /* Check parameters */
03193   assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
03194   assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
03195   assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
03196   assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
03197   assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter));
03198
03199   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03200   {
03201      return HAL_BUSY;
03202   }
03203
03204   /* Process Locked */
03205   __HAL_LOCK(hhrtim);
03206
03207   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03208
03209   /* Configure the event channel */
03210   HRTIM_EventConfig(hhrtim, Event, pEventCfg);
03211
03212   hhrtim->State = HAL_HRTIM_STATE_READY;
03213
03214   /* Process Unlocked */
03215   __HAL_UNLOCK(hhrtim);
03216
03217   return HAL_OK;
03218 }
03219
03220 /**
03221   * @brief  Configures the external event conditioning block prescaler
03222   * @param  hhrtim: pointer to HAL HRTIM handle
03223   * @param  Prescaler: Prescaler value
03224   *                    This parameter can be one of the following values:
03225   *                    @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIM
03226   *                    @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIM / 2
03227   *                    @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIM / 4
03228   *                    @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIM / 8
03229   * @note This function must be called before starting the timer
03230   * @retval HAL status
03231   */
03232 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
03233                                                  uint32_t Prescaler)
03234 {
03235   uint32_t hrtim_eecr3;
03236
03237   /* Check parameters */
03238   assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
03239
03240   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03241   {
03242      return HAL_BUSY;
03243   }
03244
03245   /* Process Locked */
03246   __HAL_LOCK(hhrtim);
03247
03248   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03249
03250   /* Set the external event prescaler */
03251   hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
03252   hrtim_eecr3 &= ~(HRTIM_EECR3_EEVSD);
03253   hrtim_eecr3 |= Prescaler;
03254
03255   /* Update the HRTIM registers */
03256   hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
03257
03258   hhrtim->State = HAL_HRTIM_STATE_READY;
03259
03260   /* Process Unlocked */
03261   __HAL_UNLOCK(hhrtim);
03262
03263   return HAL_OK;
03264 }
03265
03266 /**
03267   * @brief  Configures the conditioning of fault input
03268   * @param  hhrtim: pointer to HAL HRTIM handle
03269   * @param  Fault: fault input to configure
03270   *                    This parameter can be one of the following values:
03271   *                    @arg HRTIM_FAULT_1: Fault input 1
03272   *                    @arg HRTIM_FAULT_2: Fault input 2
03273   *                    @arg HRTIM_FAULT_3: Fault input 3
03274   *                    @arg HRTIM_FAULT_4: Fault input 4
03275   *                    @arg HRTIM_FAULT_5: Fault input 5
03276   * @param  pFaultCfg: pointer to the fault conditioning configuration structure
03277   * @note This function must be called before starting the timer and before
03278   *       enabling faults inputs
03279   * @retval HAL status
03280   */
03281 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,
03282                                         uint32_t Fault,
03283                                         HRTIM_FaultCfgTypeDef* pFaultCfg)
03284 {
03285   uint32_t hrtim_fltinr1;
03286   uint32_t hrtim_fltinr2;
03287
03288   /* Check parameters */
03289   assert_param(IS_HRTIM_FAULT(Fault));
03290   assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
03291   assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
03292   assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
03293   assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
03294
03295   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03296   {
03297      return HAL_BUSY;
03298   }
03299
03300   /* Process Locked */
03301   __HAL_LOCK(hhrtim);
03302
03303   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03304
03305   /* Configure fault channel */
03306   hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
03307   hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
03308
03309   switch (Fault)
03310   {
03311   case HRTIM_FAULT_1:
03312     {
03313       hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
03314       hrtim_fltinr1 |= pFaultCfg->Polarity;
03315       hrtim_fltinr1 |= pFaultCfg->Source;
03316       hrtim_fltinr1 |= pFaultCfg->Filter;
03317       hrtim_fltinr1 |= pFaultCfg->Lock;
03318     }
03319     break;
03320   case HRTIM_FAULT_2:
03321     {
03322       hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
03323       hrtim_fltinr1 |= (pFaultCfg->Polarity << 8);
03324       hrtim_fltinr1 |= (pFaultCfg->Source << 8);
03325       hrtim_fltinr1 |= (pFaultCfg->Filter << 8);
03326       hrtim_fltinr1 |= (pFaultCfg->Lock << 8);
03327     }
03328     break;
03329   case HRTIM_FAULT_3:
03330     {
03331       hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
03332       hrtim_fltinr1 |= (pFaultCfg->Polarity << 16);
03333       hrtim_fltinr1 |= (pFaultCfg->Source << 16);
03334       hrtim_fltinr1 |= (pFaultCfg->Filter << 16);
03335       hrtim_fltinr1 |= (pFaultCfg->Lock << 16);
03336     }
03337     break;
03338   case HRTIM_FAULT_4:
03339     {
03340       hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
03341       hrtim_fltinr1 |= (pFaultCfg->Polarity << 24);
03342       hrtim_fltinr1 |= (pFaultCfg->Source << 24);
03343       hrtim_fltinr1 |= (pFaultCfg->Filter << 24);
03344       hrtim_fltinr1 |= (pFaultCfg->Lock << 24);
03345     }
03346     break;
03347   case HRTIM_FAULT_5:
03348     {
03349       hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
03350       hrtim_fltinr2 |= pFaultCfg->Polarity;
03351       hrtim_fltinr2 |= pFaultCfg->Source;
03352       hrtim_fltinr2 |= pFaultCfg->Filter;
03353       hrtim_fltinr2 |= pFaultCfg->Lock;
03354     }
03355     break;
03356   default:
03357     break;
03358   }
03359
03360   /* Update the HRTIM registers */
03361   hhrtim->Instance->sCommonRegs.FLTINR1 = hrtim_fltinr1;
03362   hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
03363
03364   hhrtim->State = HAL_HRTIM_STATE_READY;
03365
03366   /* Process Unlocked */
03367   __HAL_UNLOCK(hhrtim);
03368
03369   return HAL_OK;
03370 }
03371
03372 /**
03373   * @brief  Configures the fault conditioning block prescaler
03374   * @param  hhrtim: pointer to HAL HRTIM handle
03375   * @param  Prescaler: Prescaler value
03376   *                    This parameter can be one of the following values:
03377   *                    @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIM
03378   *                    @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIM / 2
03379   *                    @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIM / 4
03380   *                    @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIM / 8
03381   * @retval HAL status
03382   * @note This function must be called before starting the timer and before
03383   *       enabling faults inputs
03384   */
03385 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
03386                                                  uint32_t Prescaler)
03387 {
03388   uint32_t hrtim_fltinr2;
03389
03390   /* Check parameters */
03391   assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
03392
03393   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03394   {
03395      return HAL_BUSY;
03396   }
03397
03398   /* Process Locked */
03399   __HAL_LOCK(hhrtim);
03400
03401   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03402
03403   /* Set the external event prescaler */
03404   hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
03405   hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLTSD);
03406   hrtim_fltinr2 |= Prescaler;
03407
03408   /* Update the HRTIM registers */
03409   hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
03410
03411   hhrtim->State = HAL_HRTIM_STATE_READY;
03412
03413   /* Process Unlocked */
03414   __HAL_UNLOCK(hhrtim);
03415
03416   return HAL_OK;
03417 }
03418
03419 /**
03420   * @brief  Enables or disables the HRTIMx Fault mode.
03421   * @param  hhrtim: pointer to HAL HRTIM handle
03422   * @param  Faults: fault input(s) to enable or disable
03423   *                   This parameter can be any combination of the following values:
03424   *                    @arg HRTIM_FAULT_1: Fault input 1
03425   *                    @arg HRTIM_FAULT_2: Fault input 2
03426   *                    @arg HRTIM_FAULT_3: Fault input 3
03427   *                    @arg HRTIM_FAULT_4: Fault input 4
03428   *                    @arg HRTIM_FAULT_5: Fault input 5
03429   * @param  Enable: Fault(s) enabling
03430   *                    This parameter can be one of the following values:
03431   *                    @arg HRTIM_FAULTMODECTL_ENABLED: Fault(s) enabled
03432   *                    @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled
03433   * @retval None
03434   */
03435 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
03436                         uint32_t Faults,
03437                         uint32_t Enable)
03438 {
03439   uint32_t hrtim_fltinr1;
03440   uint32_t hrtim_fltinr2;
03441
03442   /* Check parameters */
03443   assert_param(IS_HRTIM_FAULT(Faults));
03444   assert_param(IS_HRTIM_FAULTMODECTL(Enable));
03445
03446   /* Configure fault channel */
03447   hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
03448   hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
03449
03450   if ((Faults & HRTIM_FAULT_1) != RESET)
03451   {
03452     hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT1E;
03453     hrtim_fltinr1 |= Enable;
03454   }
03455   if ((Faults & HRTIM_FAULT_2) != RESET)
03456   {
03457     hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT2E;
03458     hrtim_fltinr1 |= (Enable << 8);
03459   }
03460   if ((Faults & HRTIM_FAULT_3) != RESET)
03461   {
03462     hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT3E;
03463     hrtim_fltinr1 |= (Enable << 16);
03464   }
03465   if ((Faults & HRTIM_FAULT_4) != RESET)
03466   {
03467     hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT4E;
03468     hrtim_fltinr1 |= (Enable << 24);
03469   }
03470   if ((Faults & HRTIM_FAULT_5) != RESET)
03471   {
03472     hrtim_fltinr2 &= ~HRTIM_FLTINR2_FLT5E;
03473     hrtim_fltinr2 |= Enable;
03474   }
03475
03476   /* Update the HRTIMx registers */
03477   hhrtim->Instance->sCommonRegs.FLTINR1 = hrtim_fltinr1;
03478   hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
03479 }
03480
03481 /**
03482   * @brief  Configures both the ADC trigger register update source and the ADC
03483   *         trigger source.
03484   * @param  hhrtim: pointer to HAL HRTIM handle
03485   * @param  ADCTrigger: ADC trigger to configure
03486   *                    This parameter can be one of the following values:
03487   *                    @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
03488   *                    @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
03489   *                    @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
03490   *                    @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
03491   * @param  pADCTriggerCfg: pointer to the ADC trigger configuration structure
03492   * @retval HAL status
03493   * @note This function must be called before starting the timer
03494   */
03495 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
03496                                              uint32_t ADCTrigger,
03497                                              HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
03498 {
03499   uint32_t hrtim_cr1;
03500
03501   /* Check parameters */
03502   assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
03503   assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
03504
03505   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03506   {
03507      return HAL_BUSY;
03508   }
03509
03510   /* Process Locked */
03511   __HAL_LOCK(hhrtim);
03512
03513   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03514
03515   /* Set the ADC trigger update source */
03516   hrtim_cr1 = hhrtim->Instance->sCommonRegs.CR1;
03517
03518   switch (ADCTrigger)
03519   {
03520   case HRTIM_ADCTRIGGER_1:
03521     {
03522       hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC);
03523       hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC);
03524
03525       /* Set the ADC trigger 1 source */
03526       hhrtim->Instance->sCommonRegs.ADC1R = pADCTriggerCfg->Trigger;
03527     }
03528     break;
03529   case HRTIM_ADCTRIGGER_2:
03530     {
03531       hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC);
03532       hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3) & HRTIM_CR1_ADC2USRC);
03533
03534       /* Set the ADC trigger 2 source */
03535       hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger;
03536     }
03537     break;
03538   case HRTIM_ADCTRIGGER_3:
03539     {
03540       hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC);
03541       hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6) & HRTIM_CR1_ADC3USRC);
03542
03543       /* Set the ADC trigger 3 source */
03544       hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger;
03545     }
03546     break;
03547   case HRTIM_ADCTRIGGER_4:
03548     {
03549       hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC);
03550       hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9) & HRTIM_CR1_ADC4USRC);
03551
03552       /* Set the ADC trigger 4 source */
03553       hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
03554     }
03555     break;
03556   }
03557
03558   /* Update the HRTIM registers */
03559   hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1;
03560
03561   hhrtim->State = HAL_HRTIM_STATE_READY;
03562
03563   /* Process Unlocked */
03564   __HAL_UNLOCK(hhrtim);
03565
03566   return HAL_OK;
03567 }
03568
03569 /**
03570   * @}
03571   */
03572
03573 /** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
03574  *  @brief    HRTIM timer configuration and control functions
03575
03576 @verbatim
03577  ===============================================================================
03578               ##### HRTIM timer configuration and control functions #####
03579  ===============================================================================
03580     [..]  This section provides functions used to configure and control a
03581         HRTIM timer operating in waveform mode:
03582       (+) Configure HRTIM timer general behavior
03583       (+) Configure HRTIM timer event filtering
03584       (+) Configure HRTIM timer deadtime insertion
03585       (+) Configure HRTIM timer chopper mode
03586       (+) Configure HRTIM timer burst DMA
03587       (+) Configure HRTIM timer compare unit
03588       (+) Configure HRTIM timer capture unit
03589       (+) Configure HRTIM timer output
03590       (+) Set HRTIM timer output level
03591       (+) Enable HRTIM timer output
03592       (+) Disable HRTIM timer output
03593       (+) Start HRTIM timer
03594       (+) Stop HRTIM timer
03595       (+) Start HRTIM timer and enable interrupt
03596       (+) Stop HRTIM timer and disable interrupt
03597       (+) Start HRTIM timer and enable DMA transfer
03598       (+) Stop HRTIM timer and disable DMA transfer
03599       (+) Enable or disable the burst mode controller
03600       (+) Start the burst mode controller (by software)
03601       (+) Trigger a Capture (by software)
03602       (+) Update the HRTIM timer preloadable registers (by software)
03603       (+) Reset the HRTIM timer counter (by software)
03604       (+) Start a burst DMA transfer
03605       (+) Enable timer register update
03606       (+) Disable timer register update
03607
03608 @endverbatim
03609   * @{
03610   */
03611
03612 /**
03613   * @brief  Configures the general behavior of a timer operating in waveform mode
03614   * @param  hhrtim: pointer to HAL HRTIM handle
03615   * @param  TimerIdx: Timer index
03616   *                   This parameter can be one of the following values:
03617   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
03618   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03619   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03620   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03621   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03622   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03623   * @param  pTimerCfg: pointer to the timer configuration structure
03624   * @note When the timer operates in waveform mode, all the features supported by
03625   *       the HRTIM are available without any limitation.
03626   * @retval HAL status
03627   * @note This function must be called before starting the timer
03628   */
03629 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,
03630                                                 uint32_t TimerIdx,
03631                                                 HRTIM_TimerCfgTypeDef * pTimerCfg)
03632 {
03633   /* Check parameters */
03634   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
03635
03636   /* Relevant for all HRTIM timers, including the master */
03637   assert_param(IS_HRTIM_HALFMODE(pTimerCfg->HalfModeEnable));
03638   assert_param(IS_HRTIM_SYNCSTART(pTimerCfg->StartOnSync));
03639   assert_param(IS_HRTIM_SYNCRESET(pTimerCfg->ResetOnSync));
03640   assert_param(IS_HHRTIM_DACSYNC(pTimerCfg->DACSynchro));
03641   assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable));
03642   assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode));
03643   assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate));
03644
03645   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03646   {
03647      return HAL_BUSY;
03648   }
03649
03650   /* Process Locked */
03651   __HAL_LOCK(hhrtim);
03652
03653   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03654
03655   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
03656   {
03657     /* Check parameters */
03658     assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating));
03659     assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests));
03660     assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests));
03661
03662     /* Configure master timer */
03663     HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg);
03664   }
03665   else
03666   {
03667     /* Check parameters */
03668     assert_param(IS_HRTIM_UPDATEGATING_TIM(pTimerCfg->UpdateGating));
03669     assert_param(IS_HRTIM_TIM_IT(pTimerCfg->InterruptRequests));
03670     assert_param(IS_HRTIM_TIM_DMA(pTimerCfg->DMARequests));
03671     assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
03672     assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
03673     assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
03674     assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->PushPull,
03675                                                pTimerCfg->DeadTimeInsertion));
03676     assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->PushPull,
03677                                                pTimerCfg->DelayedProtectionMode));
03678     assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
03679     assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
03680     assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
03681
03682     /* Configure timing unit */
03683     HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg);
03684   }
03685
03686   /* Update timer parameters */
03687   hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests;
03688   hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests;
03689   hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress;
03690   hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress;
03691   hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize;
03692
03693   /* Force a software update */
03694   HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
03695
03696   hhrtim->State = HAL_HRTIM_STATE_READY;
03697
03698   /* Process Unlocked */
03699   __HAL_UNLOCK(hhrtim);
03700
03701   return HAL_OK;
03702 }
03703
03704 /**
03705   * @brief  Configures the event filtering capabilities of a timer (blanking, windowing)
03706   * @param  hhrtim: pointer to HAL HRTIM handle
03707   * @param  TimerIdx: Timer index
03708   *                   This parameter can be one of the following values:
03709   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03710   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03711   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03712   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03713   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03714   * @param  Event: external event for which timer event filtering must be configured
03715   *                    This parameter can be one of the following values:
03716   *                    @arg HRTIM_EVENT_NONE: Reset timer event filtering configuration
03717   *                    @arg HRTIM_EVENT_1: External event 1
03718   *                    @arg HRTIM_EVENT_2: External event 2
03719   *                    @arg HRTIM_EVENT_3: External event 3
03720   *                    @arg HRTIM_EVENT_4: External event 4
03721   *                    @arg HRTIM_EVENT_5: External event 5
03722   *                    @arg HRTIM_EVENT_6: External event 6
03723   *                    @arg HRTIM_EVENT_7: External event 7
03724   *                    @arg HRTIM_EVENT_8: External event 8
03725   *                    @arg HRTIM_EVENT_9: External event 9
03726   *                    @arg HRTIM_EVENT_10: External event 10
03727   * @param  pTimerEventFilteringCfg: pointer to the timer event filtering configuration structure
03728   * @note This function must be called before starting the timer
03729   * @retval HAL status
03730   */
03731 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,
03732                                                       uint32_t TimerIdx,
03733                                                       uint32_t Event,
03734                                                       HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
03735 {
03736   uint32_t hrtim_eefr;
03737
03738   /* Check parameters */
03739   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
03740   assert_param(IS_HRTIM_EVENT(Event));
03741   assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter));
03742   assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
03743
03744   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03745   {
03746      return HAL_BUSY;
03747   }
03748
03749   /* Process Locked */
03750   __HAL_LOCK(hhrtim);
03751
03752   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03753
03754   /* Configure timer event filtering capabilities */
03755   switch (Event)
03756   {
03757   case HRTIM_EVENT_NONE:
03758     {
03759       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = 0;
03760       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = 0;
03761     }
03762     break;
03763   case HRTIM_EVENT_1:
03764     {
03765       hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
03766       hrtim_eefr &= ~(HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH);
03767       hrtim_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
03768       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
03769     }
03770     break;
03771   case HRTIM_EVENT_2:
03772     {
03773       hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
03774       hrtim_eefr &= ~(HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH);
03775       hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
03776       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
03777     }
03778     break;
03779   case HRTIM_EVENT_3:
03780     {
03781       hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
03782       hrtim_eefr &= ~(HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH);
03783       hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
03784       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
03785     }
03786     break;
03787   case HRTIM_EVENT_4:
03788     {
03789       hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
03790       hrtim_eefr &= ~(HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH);
03791       hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
03792       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
03793     }
03794     break;
03795   case HRTIM_EVENT_5:
03796     {
03797       hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
03798       hrtim_eefr &= ~(HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH);
03799       hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
03800       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
03801     }
03802     break;
03803   case HRTIM_EVENT_6:
03804     {
03805       hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
03806       hrtim_eefr &= ~(HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH);
03807       hrtim_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
03808       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
03809     }
03810     break;
03811   case HRTIM_EVENT_7:
03812     {
03813       hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
03814       hrtim_eefr &= ~(HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH);
03815       hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
03816       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
03817     }
03818     break;
03819   case HRTIM_EVENT_8:
03820     {
03821       hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
03822       hrtim_eefr &= ~(HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH);
03823       hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
03824       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
03825     }
03826     break;
03827   case HRTIM_EVENT_9:
03828     {
03829       hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
03830       hrtim_eefr &= ~(HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH);
03831       hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
03832       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
03833     }
03834     break;
03835   case HRTIM_EVENT_10:
03836     {
03837       hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
03838       hrtim_eefr &= ~(HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH);
03839       hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
03840       hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
03841     }
03842     break;
03843   }
03844
03845   hhrtim->State = HAL_HRTIM_STATE_READY;
03846
03847   /* Process Unlocked */
03848   __HAL_UNLOCK(hhrtim);
03849
03850   return HAL_OK;
03851 }
03852
03853 /**
03854   * @brief  Configures the deadtime insertion feature for a timer
03855   * @param  hhrtim: pointer to HAL HRTIM handle
03856   * @param  TimerIdx: Timer index
03857   *                   This parameter can be one of the following values:
03858   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03859   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03860   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03861   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03862   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03863   * @param  pDeadTimeCfg: pointer to the deadtime insertion configuration structure
03864   * @retval HAL status
03865   * @note This function must be called before starting the timer
03866   */
03867 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,
03868                                            uint32_t TimerIdx,
03869                                            HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
03870 {
03871   uint32_t hrtim_dtr;
03872
03873   /* Check parameters */
03874   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
03875   assert_param(IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(pDeadTimeCfg->Prescaler));
03876   assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
03877   assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
03878   assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
03879   assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
03880   assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
03881   assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
03882
03883   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03884   {
03885      return HAL_BUSY;
03886   }
03887
03888   /* Process Locked */
03889   __HAL_LOCK(hhrtim);
03890
03891   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03892
03893   hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
03894
03895   /* Clear timer deadtime configuration */
03896   hrtim_dtr &= ~(HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
03897                  HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF |
03898                  HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK);
03899
03900   /* Set timer deadtime configuration */
03901   hrtim_dtr |= pDeadTimeCfg->Prescaler;
03902   hrtim_dtr |= pDeadTimeCfg->RisingValue;
03903   hrtim_dtr |= pDeadTimeCfg->RisingSign;
03904   hrtim_dtr |= pDeadTimeCfg->RisingSignLock;
03905   hrtim_dtr |= pDeadTimeCfg->RisingLock;
03906   hrtim_dtr |= (pDeadTimeCfg->FallingValue << 16);
03907   hrtim_dtr |= pDeadTimeCfg->FallingSign;
03908   hrtim_dtr |= pDeadTimeCfg->FallingSignLock;
03909   hrtim_dtr |= pDeadTimeCfg->FallingLock;
03910
03911   /* Update the HRTIM registers */
03912   hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR = hrtim_dtr;
03913
03914   hhrtim->State = HAL_HRTIM_STATE_READY;
03915
03916   /* Process Unlocked */
03917   __HAL_UNLOCK(hhrtim);
03918
03919   return HAL_OK;
03920 }
03921
03922 /**
03923   * @brief  Configures the chopper mode feature for a timer
03924   * @param  hhrtim: pointer to HAL HRTIM handle
03925   * @param  TimerIdx: Timer index
03926   *                   This parameter can be one of the following values:
03927   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03928   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03929   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03930   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03931   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03932   * @param  pChopperModeCfg: pointer to the chopper mode configuration structure
03933   * @retval HAL status
03934   * @note This function must be called before configuring the timer output(s)
03935   */
03936 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,
03937                                               uint32_t TimerIdx,
03938                                               HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
03939 {
03940   uint32_t hrtim_chpr;
03941
03942   /* Check parameters */
03943   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
03944   assert_param(IS_HRTIM_CHOPPER_PRESCALERRATIO(pChopperModeCfg->CarrierFreq));
03945   assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle));
03946   assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse));
03947
03948   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03949   {
03950      return HAL_BUSY;
03951   }
03952
03953   /* Process Locked */
03954   __HAL_LOCK(hhrtim);
03955
03956   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03957
03958   hrtim_chpr = hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR;
03959
03960   /* Clear timer chopper mode configuration */
03961   hrtim_chpr &= ~(HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW);
03962
03963   /* Set timer choppe mode configuration */
03964   hrtim_chpr |= pChopperModeCfg->CarrierFreq;
03965   hrtim_chpr |= (pChopperModeCfg->DutyCycle);
03966   hrtim_chpr |= (pChopperModeCfg->StartPulse);
03967
03968   /* Update the HRTIM registers */
03969   hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR = hrtim_chpr;
03970
03971   hhrtim->State = HAL_HRTIM_STATE_READY;
03972
03973   /* Process Unlocked */
03974   __HAL_UNLOCK(hhrtim);
03975
03976   return HAL_OK;
03977 }
03978
03979 /**
03980   * @brief  Configures the burst DMA controller for a timer
03981   * @param  hhrtim: pointer to HAL HRTIM handle
03982   * @param  TimerIdx: Timer index
03983   *                  This parameter can be one of the following values:
03984   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
03985   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03986   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03987   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03988   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03989   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03990   * @param  RegistersToUpdate: registers to be written by DMA
03991   *                    This parameter can be any combination of the following values:
03992   *                    @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
03993   *                    @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
03994   *                    @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
03995   *                    @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
03996   *                    @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
03997   *                    @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
03998   *                    @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
03999   *                    @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
04000   *                    @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
04001   *                    @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
04002   *                    @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
04003   *                    @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
04004   *                    @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
04005   *                    @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
04006   *                    @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
04007   *                    @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
04008   *                    @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
04009   *                    @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
04010   *                    @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
04011   *                    @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
04012   *                    @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
04013   * @retval HAL status
04014   * @note This function must be called before starting the timer
04015   */
04016 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,
04017                                            uint32_t TimerIdx,
04018                                            uint32_t RegistersToUpdate)
04019 {
04020   /* Check parameters */
04021   assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
04022
04023   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04024   {
04025      return HAL_BUSY;
04026   }
04027
04028   /* Process Locked */
04029   __HAL_LOCK(hhrtim);
04030
04031   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04032
04033   /* Set the burst DMA timer update register */
04034   switch (TimerIdx)
04035   {
04036   case HRTIM_TIMERINDEX_TIMER_A:
04037     {
04038       hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate;
04039     }
04040     break;
04041   case HRTIM_TIMERINDEX_TIMER_B:
04042     {
04043       hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate;
04044     }
04045     break;
04046   case HRTIM_TIMERINDEX_TIMER_C:
04047     {
04048       hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate;
04049     }
04050     break;
04051   case HRTIM_TIMERINDEX_TIMER_D:
04052     {
04053       hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate;
04054     }
04055     break;
04056   case HRTIM_TIMERINDEX_TIMER_E:
04057     {
04058       hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate;
04059     }
04060     break;
04061   case HRTIM_TIMERINDEX_MASTER:
04062     {
04063       hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate;
04064     }
04065     break;
04066   }
04067
04068   hhrtim->State = HAL_HRTIM_STATE_READY;
04069
04070   /* Process Unlocked */
04071   __HAL_UNLOCK(hhrtim);
04072
04073   return HAL_OK;
04074 }
04075
04076 /**
04077   * @brief  Configures the compare unit of a timer operating in waveform mode
04078   * @param  hhrtim: pointer to HAL HRTIM handle
04079   * @param  TimerIdx: Timer index
04080   *                   This parameter can be one of the following values:
04081   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
04082   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04083   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04084   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04085   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04086   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04087   * @param  CompareUnit: Compare unit to configure
04088   *                    This parameter can be one of the following values:
04089   *                    @arg HRTIM_COMPAREUNIT_1: Compare unit 1
04090   *                    @arg HRTIM_COMPAREUNIT_2: Compare unit 2
04091   *                    @arg HRTIM_COMPAREUNIT_3: Compare unit 3
04092   *                    @arg HRTIM_COMPAREUNIT_4: Compare unit 4
04093   * @param  pCompareCfg: pointer to the compare unit configuration structure
04094   * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
04095   *       application has to configure separately the capture unit. Capture unit
04096   *       to configure in that case depends on the compare unit auto delayed mode
04097   *       is applied to (see below):
04098   *         Auto delayed on output compare 2: capture unit 1 must be configured
04099   *         Auto delayed on output compare 4: capture unit 2 must be configured
04100   * @retval HAL status
04101   * @note This function must be called before starting the timer
04102   */
04103 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
04104                                                   uint32_t TimerIdx,
04105                                                   uint32_t CompareUnit,
04106                                                   HRTIM_CompareCfgTypeDef* pCompareCfg)
04107 {
04108   /* Check parameters */
04109   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
04110
04111   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04112   {
04113      return HAL_BUSY;
04114   }
04115
04116   /* Process Locked */
04117   __HAL_LOCK(hhrtim);
04118
04119   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04120
04121   /* Configure the compare unit */
04122   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
04123   {
04124     switch (CompareUnit)
04125     {
04126       case HRTIM_COMPAREUNIT_1:
04127         {
04128         hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
04129         }
04130         break;
04131       case HRTIM_COMPAREUNIT_2:
04132         {
04133         hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
04134         }
04135         break;
04136       case HRTIM_COMPAREUNIT_3:
04137         {
04138         hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
04139         }
04140         break;
04141       case HRTIM_COMPAREUNIT_4:
04142         {
04143         hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
04144         }
04145         break;
04146     }
04147   }
04148   else
04149   {
04150     switch (CompareUnit)
04151     {
04152     case HRTIM_COMPAREUNIT_1:
04153       {
04154         /* Set the compare value */
04155         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
04156       }
04157       break;
04158     case HRTIM_COMPAREUNIT_2:
04159       {
04160         /* Check parameters */
04161         assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
04162
04163         /* Set the compare value */
04164         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
04165
04166         if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
04167         {
04168           /* Configure auto-delayed mode */
04169           /* DELCMP2 bitfield must be reset when reprogrammed from one value */
04170           /* to the other to reinitialize properly the auto-delayed mechanism */
04171           hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2;
04172           hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode;
04173
04174           /* Set the compare value for timeout compare unit (if any) */
04175           if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
04176           {
04177             hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
04178           }
04179           else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
04180           {
04181             hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
04182           }
04183         }
04184       }
04185       break;
04186     case HRTIM_COMPAREUNIT_3:
04187       {
04188         /* Set the compare value */
04189         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
04190       }
04191       break;
04192     case HRTIM_COMPAREUNIT_4:
04193       {
04194         /* Check parameters */
04195         assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
04196
04197         /* Set the compare value */
04198         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
04199
04200         if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
04201         {
04202           /* Configure auto-delayed mode */
04203           /* DELCMP4 bitfield must be reset when reprogrammed from one value */
04204           /* to the other to reinitialize properly the auto-delayed mechanism */
04205           hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
04206           hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2);
04207
04208           /* Set the compare value for timeout compare unit (if any) */
04209           if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
04210           {
04211             hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
04212           }
04213           else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
04214           {
04215             hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
04216           }
04217         }
04218       }
04219       break;
04220     }
04221   }
04222   hhrtim->State = HAL_HRTIM_STATE_READY;
04223
04224   /* Process Unlocked */
04225   __HAL_UNLOCK(hhrtim);
04226
04227   return HAL_OK;
04228 }
04229
04230 /**
04231   * @brief  Configures the capture unit of a timer operating in waveform mode
04232   * @param  hhrtim: pointer to HAL HRTIM handle
04233   * @param  TimerIdx: Timer index
04234   *                   This parameter can be one of the following values:
04235   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04236   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04237   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04238   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04239   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04240   * @param  CaptureUnit: Capture unit to configure
04241   *                    This parameter can be one of the following values:
04242   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
04243   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
04244   * @param  pCaptureCfg: pointer to the compare unit configuration structure
04245   * @retval HAL status
04246   * @note This function must be called before starting the timer
04247   */
04248 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
04249                                                   uint32_t TimerIdx,
04250                                                   uint32_t CaptureUnit,
04251                                                   HRTIM_CaptureCfgTypeDef* pCaptureCfg)
04252 {
04253   /* Check parameters */
04254   assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, pCaptureCfg->Trigger));
04255
04256   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04257   {
04258      return HAL_BUSY;
04259   }
04260
04261   /* Process Locked */
04262   __HAL_LOCK(hhrtim);
04263
04264   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04265
04266   /* Configure the capture unit */
04267   switch (CaptureUnit)
04268   {
04269   case HRTIM_CAPTUREUNIT_1:
04270     {
04271       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = pCaptureCfg->Trigger;
04272     }
04273     break;
04274   case HRTIM_CAPTUREUNIT_2:
04275     {
04276       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = pCaptureCfg->Trigger;
04277     }
04278     break;
04279   }
04280
04281   hhrtim->State = HAL_HRTIM_STATE_READY;
04282
04283   /* Process Unlocked */
04284   __HAL_UNLOCK(hhrtim);
04285
04286   return HAL_OK;
04287 }
04288
04289 /**
04290   * @brief  Configures the output of a timer operating in waveform mode
04291   * @param  hhrtim: pointer to HAL HRTIM handle
04292   * @param  TimerIdx: Timer index
04293   *                   This parameter can be one of the following values:
04294   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04295   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04296   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04297   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04298   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04299   * @param  Output: Timer output
04300   *                    This parameter can be one of the following values:
04301   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
04302   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
04303   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
04304   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
04305   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
04306   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
04307   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
04308   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
04309   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
04310   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
04311   * @param  pOutputCfg: pointer to the timer output configuration structure
04312   * @retval HAL status
04313   * @note This function must be called before configuring the timer and after
04314   *       configuring the deadtime insertion feature (if required).
04315   */
04316 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,
04317                                                 uint32_t TimerIdx,
04318                                                 uint32_t Output,
04319                                                 HRTIM_OutputCfgTypeDef * pOutputCfg)
04320 {
04321   /* Check parameters */
04322   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
04323   assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
04324   assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pOutputCfg->IdleLevel));
04325   assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
04326   assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel));
04327   assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
04328   assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
04329
04330   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04331   {
04332      return HAL_BUSY;
04333   }
04334
04335   /* Process Locked */
04336   __HAL_LOCK(hhrtim);
04337
04338   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04339
04340   /* Configure the timer output */
04341   HRTIM_OutputConfig(hhrtim,
04342                      TimerIdx,
04343                      Output,
04344                      pOutputCfg);
04345
04346   hhrtim->State = HAL_HRTIM_STATE_READY;
04347
04348   /* Process Unlocked */
04349   __HAL_UNLOCK(hhrtim);
04350
04351   return HAL_OK;
04352 }
04353
04354 /**
04355   * @brief  Forces the timer output to its active or inactive state
04356   * @param  hhrtim: pointer to HAL HRTIM handle
04357   * @param  TimerIdx: Timer index
04358   *                   This parameter can be one of the following values:
04359   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04360   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04361   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04362   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04363   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04364   * @param  Output: Timer output
04365   *                    This parameter can be one of the following values:
04366   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
04367   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
04368   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
04369   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
04370   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
04371   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
04372   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
04373   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
04374   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
04375   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
04376   * @param OutputLevel: indicates whether the output is forced to its active or inactive level
04377   *                    This parameter can be one of the following values:
04378   *                    @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active level
04379   *                    @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive level
04380   * @retval HAL status
04381   * @note The 'software set/reset trigger' bit in the output set/reset registers
04382   *       is automatically reset by hardware
04383   */
04384 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
04385                                                    uint32_t TimerIdx,
04386                                                    uint32_t Output,
04387                                                    uint32_t OutputLevel)
04388 {
04389   /* Check parameters */
04390   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
04391   assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
04392
04393   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04394   {
04395      return HAL_BUSY;
04396   }
04397
04398   /* Process Locked */
04399   __HAL_LOCK(hhrtim);
04400
04401   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04402
04403   /* Force timer output level */
04404   switch (Output)
04405   {
04406   case HRTIM_OUTPUT_TA1:
04407   case HRTIM_OUTPUT_TB1:
04408   case HRTIM_OUTPUT_TC1:
04409   case HRTIM_OUTPUT_TD1:
04410   case HRTIM_OUTPUT_TE1:
04411     {
04412       if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
04413       {
04414         /* Force output to its active state */
04415         hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R |= HRTIM_SET1R_SST;
04416       }
04417       else
04418       {
04419         /* Force output to its inactive state */
04420         hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R |= HRTIM_RST1R_SRT;
04421       }
04422     }
04423     break;
04424   case HRTIM_OUTPUT_TA2:
04425   case HRTIM_OUTPUT_TB2:
04426   case HRTIM_OUTPUT_TC2:
04427   case HRTIM_OUTPUT_TD2:
04428   case HRTIM_OUTPUT_TE2:
04429     {
04430       if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
04431       {
04432         /* Force output to its active state */
04433         hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R |= HRTIM_SET2R_SST;
04434       }
04435       else
04436       {
04437         /* Force output to its inactive state */
04438         hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R |= HRTIM_RST2R_SRT;
04439       }
04440     }
04441     break;
04442   }
04443
04444   hhrtim->State = HAL_HRTIM_STATE_READY;
04445
04446   /* Process Unlocked */
04447   __HAL_UNLOCK(hhrtim);
04448
04449   return HAL_OK;
04450 }
04451
04452 /**
04453   * @brief  Enables the generation of the waveform signal on the designated output(s)
04454   *         Outputs can be combined (ORed) to allow for simultaneous output enabling.
04455   * @param  hhrtim: pointer to HAL HRTIM handle
04456   * @param  OutputsToStart: Timer output(s) to enable
04457   *                    This parameter can be any combination of the following values:
04458   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
04459   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
04460   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
04461   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
04462   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
04463   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
04464   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
04465   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
04466   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
04467   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
04468   * @retval HAL status
04469   */
04470 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,
04471                                                 uint32_t OutputsToStart)
04472 {
04473    /* Check the parameters */
04474   assert_param(IS_HRTIM_OUTPUT(OutputsToStart));
04475
04476   /* Process Locked */
04477   __HAL_LOCK(hhrtim);
04478
04479   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04480
04481   /* Enable the HRTIM outputs */
04482   hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart);
04483
04484   hhrtim->State = HAL_HRTIM_STATE_READY;
04485
04486   /* Process Unlocked */
04487   __HAL_UNLOCK(hhrtim);
04488
04489   return HAL_OK;
04490 }
04491
04492 /**
04493   * @brief  Disables the generation of the waveform signal on the designated output(s)
04494   *         Outputs can be combined (ORed) to allow for simultaneous output disabling.
04495   * @param  hhrtim: pointer to HAL HRTIM handle
04496   * @param  OutputsToStop: Timer output(s) to disable
04497   *                    This parameter can be any combination of the following values:
04498   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
04499   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
04500   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
04501   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
04502   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
04503   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
04504   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
04505   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
04506   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
04507   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
04508   * @retval HAL status
04509   */
04510 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,
04511                                                uint32_t OutputsToStop)
04512 {
04513    /* Check the parameters */
04514   assert_param(IS_HRTIM_OUTPUT(OutputsToStop));
04515
04516   /* Process Locked */
04517   __HAL_LOCK(hhrtim);
04518
04519   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04520
04521   /* Enable the HRTIM outputs */
04522   hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop);
04523
04524   hhrtim->State = HAL_HRTIM_STATE_READY;
04525
04526   /* Process Unlocked */
04527   __HAL_UNLOCK(hhrtim);
04528
04529   return HAL_OK;
04530 }
04531
04532 /**
04533   * @brief  Starts the counter of the designated timer(s) operating in waveform mode
04534   *         Timers can be combined (ORed) to allow for simultaneous counter start.
04535   * @param  hhrtim: pointer to HAL HRTIM handle
04536   * @param  Timers: Timer counter(s) to start
04537   *                   This parameter can be any combination of the following values:
04538   *                   @arg HRTIM_TIMERID_MASTER
04539   *                   @arg HRTIM_TIMERID_TIMER_A
04540   *                   @arg HRTIM_TIMERID_TIMER_B
04541   *                   @arg HRTIM_TIMERID_TIMER_C
04542   *                   @arg HRTIM_TIMERID_TIMER_D
04543   *                   @arg HRTIM_TIMERID_TIMER_E
04544   * @retval HAL status
04545   */
04546 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef * hhrtim,
04547                                                  uint32_t Timers)
04548 {
04549    /* Check the parameters */
04550   assert_param(IS_HRTIM_TIMERID(Timers));
04551
04552   /* Process Locked */
04553   __HAL_LOCK(hhrtim);
04554
04555   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04556
04557   /* Enable timer(s) counter */
04558   hhrtim->Instance->sMasterRegs.MCR |= (Timers);
04559
04560   hhrtim->State = HAL_HRTIM_STATE_READY;
04561
04562   /* Process Unlocked */
04563   __HAL_UNLOCK(hhrtim);
04564
04565   return HAL_OK;
04566 }
04567
04568 /**
04569   * @brief  Stops the counter of the designated timer(s) operating in waveform mode
04570   *         Timers can be combined (ORed) to allow for simultaneous counter stop.
04571   * @param  hhrtim: pointer to HAL HRTIM handle
04572   * @param  Timers: Timer counter(s) to stop
04573   *                   This parameter can be any combination of the following values:
04574   *                   @arg HRTIM_TIMER_MASTER
04575   *                   @arg HRTIM_TIMER_A
04576   *                   @arg HRTIM_TIMER_B
04577   *                   @arg HRTIM_TIMER_C
04578   *                   @arg HRTIM_TIMER_D
04579   *                   @arg HRTIM_TIMER_E
04580   * @retval HAL status
04581   * @note The counter of a timer is stopped only if all timer outputs are disabled
04582   */
04583 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop(HRTIM_HandleTypeDef * hhrtim,
04584                                                 uint32_t Timers)
04585 {
04586    /* Check the parameters */
04587   assert_param(IS_HRTIM_TIMERID(Timers));
04588
04589   /* Process Locked */
04590   __HAL_LOCK(hhrtim);
04591
04592   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04593
04594   /* Disable timer(s) counter */
04595   hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
04596
04597   hhrtim->State = HAL_HRTIM_STATE_READY;
04598
04599   /* Process Unlocked */
04600   __HAL_UNLOCK(hhrtim);
04601
04602   return HAL_OK;
04603 }
04604
04605 /**
04606   * @brief  Starts the counter of the designated timer(s) operating in waveform mode
04607   *         Timers can be combined (ORed) to allow for simultaneous counter start.
04608   * @param  hhrtim: pointer to HAL HRTIM handle
04609   * @param  Timers: Timer counter(s) to start
04610   *                   This parameter can be any combination of the following values:
04611   *                   @arg HRTIM_TIMERID_MASTER
04612   *                   @arg HRTIM_TIMERID_A
04613   *                   @arg HRTIM_TIMERID_B
04614   *                   @arg HRTIM_TIMERID_C
04615   *                   @arg HRTIM_TIMERID_D
04616   *                   @arg HRTIM_TIMERID_E
04617   * @note HRTIM interrupts (e.g. faults interrupts) and interrupts related
04618   *       to the timers to start are enabled within this function.
04619   *       Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig
04620   *       function.
04621   * @retval HAL status
04622   */
04623 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef * hhrtim,
04624                                                     uint32_t Timers)
04625 {
04626   uint8_t timer_idx;
04627
04628    /* Check the parameters */
04629   assert_param(IS_HRTIM_TIMERID(Timers));
04630
04631   /* Process Locked */
04632   __HAL_LOCK(hhrtim);
04633
04634   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04635
04636   /* Enable HRTIM interrupts (if required) */
04637   __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
04638
04639   /* Enable master timer related interrupts (if required) */
04640   if ((Timers & HRTIM_TIMERID_MASTER) != RESET)
04641   {
04642     __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim,
04643                                  hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
04644   }
04645
04646   /* Enable timing unit related interrupts (if required) */
04647   for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
04648        timer_idx < HRTIM_TIMERINDEX_MASTER ;
04649        timer_idx++)
04650   {
04651     if ((Timers & TimerIdxToTimerId[timer_idx]) != RESET)
04652     {
04653       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim,
04654                                   timer_idx,
04655                                   hhrtim->TimerParam[timer_idx].InterruptRequests);
04656     }
04657   }
04658
04659   /* Enable timer(s) counter */
04660   hhrtim->Instance->sMasterRegs.MCR |= (Timers);
04661
04662   hhrtim->State = HAL_HRTIM_STATE_READY;
04663
04664   /* Process Unlocked */
04665   __HAL_UNLOCK(hhrtim);
04666
04667   return HAL_OK;}
04668
04669 /**
04670   * @brief  Stops the counter of the designated timer(s) operating in waveform mode
04671   *         Timers can be combined (ORed) to allow for simultaneous counter stop.
04672   * @param  hhrtim: pointer to HAL HRTIM handle
04673   * @param  Timers: Timer counter(s) to stop
04674   *                   This parameter can be any combination of the following values:
04675   *                   @arg HRTIM_TIMER_MASTER
04676   *                   @arg HRTIM_TIMER_A
04677   *                   @arg HRTIM_TIMER_B
04678   *                   @arg HRTIM_TIMER_C
04679   *                   @arg HRTIM_TIMER_D
04680   *                   @arg HRTIM_TIMER_E
04681   * @retval HAL status
04682   * @note The counter of a timer is stopped only if all timer outputs are disabled
04683   * @note All enabled timer related interrupts are disabled.
04684   */
04685 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef * hhrtim,
04686                                                    uint32_t Timers)
04687 {
04688   /* ++ WA */
04689   __IO uint32_t delai = (uint32_t)(0x17F);
04690   /* -- WA */
04691
04692   uint8_t timer_idx;
04693
04694   /* Check the parameters */
04695   assert_param(IS_HRTIM_TIMERID(Timers));
04696
04697   /* Process Locked */
04698   __HAL_LOCK(hhrtim);
04699
04700   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04701
04702   /* Disable HRTIM interrupts (if required) */
04703   __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
04704
04705   /* Disable master timer related interrupts (if required) */
04706   if ((Timers & HRTIM_TIMERID_MASTER) != RESET)
04707   {
04708     /* Interrupts enable flag must be cleared one by one */
04709     __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
04710   }
04711
04712   /* Disable timing unit related interrupts (if required) */
04713   for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
04714        timer_idx < HRTIM_TIMERINDEX_MASTER ;
04715        timer_idx++)
04716   {
04717     if ((Timers & TimerIdxToTimerId[timer_idx]) != RESET)
04718     {
04719       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, timer_idx, hhrtim->TimerParam[timer_idx].InterruptRequests);
04720     }
04721   }
04722
04723   /* ++ WA */
04724   do { delai--; } while (delai != 0);
04725   /* -- WA */
04726
04727   /* Disable timer(s) counter */
04728   hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
04729
04730   hhrtim->State = HAL_HRTIM_STATE_READY;
04731
04732   /* Process Unlocked */
04733   __HAL_UNLOCK(hhrtim);
04734
04735   return HAL_OK;
04736 }
04737
04738 /**
04739   * @brief  Starts the counter of the designated timer(s) operating in waveform mode
04740   *         Timers can be combined (ORed) to allow for simultaneous counter start.
04741   * @param  hhrtim: pointer to HAL HRTIM handle
04742   * @param  Timers: Timer counter(s) to start
04743   *                   This parameter can be any combination of the following values:
04744   *                   HRTIM_TIMER_MASTER
04745   *                   @arg HRTIM_TIMER_A
04746   *                   @arg HRTIM_TIMER_B
04747   *                   @arg HRTIM_TIMER_C
04748   *                   @arg HRTIM_TIMER_D
04749   *                   @arg HRTIM_TIMER_E
04750   * @retval HAL status
04751   * @note This function enables the dma request(s) mentionned in the timer
04752   *       configuration data structure for every timers to start.
04753   * @note The source memory address, the destination memory address and the
04754   *       size of each DMA transfer are specified at timer configuration time
04755   *       (see HAL_HRTIM_WaveformTimerConfig)
04756   */
04757 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef * hhrtim,
04758                                                      uint32_t Timers)
04759 {
04760   uint8_t timer_idx;
04761   DMA_HandleTypeDef * hdma;
04762
04763    /* Check the parameters */
04764   assert_param(IS_HRTIM_TIMERID(Timers));
04765
04766   if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
04767   {
04768      return HAL_BUSY;
04769   }
04770
04771   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04772
04773   /* Process Locked */
04774   __HAL_LOCK(hhrtim);
04775
04776   if (((Timers & HRTIM_TIMERID_MASTER) != RESET) &&
04777       (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0))
04778   {
04779       /* Set the DMA error callback */
04780       hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ;
04781
04782       /* Set the DMA transfer completed callback */
04783       hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt;
04784
04785       /* Enable the DMA channel */
04786       HAL_DMA_Start_IT(hhrtim->hdmaMaster,
04787                        hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress,
04788                        hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress,
04789                        hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize);
04790
04791       /* Enable the timer DMA request */
04792       __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim,
04793                                    hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
04794   }
04795
04796   for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
04797        timer_idx < HRTIM_TIMERINDEX_MASTER ;
04798        timer_idx++)
04799   {
04800     if (((Timers & TimerIdxToTimerId[timer_idx]) != RESET) &&
04801          (hhrtim->TimerParam[timer_idx].DMARequests != 0))
04802     {
04803       /* Get the timer DMA handler */
04804       hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
04805
04806       /* Set the DMA error callback */
04807       hdma->XferErrorCallback = HRTIM_DMAError ;
04808
04809       /* Set the DMA transfer completed callback */
04810       hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
04811
04812       /* Enable the DMA channel */
04813       HAL_DMA_Start_IT(hdma,
04814                        hhrtim->TimerParam[timer_idx].DMASrcAddress,
04815                        hhrtim->TimerParam[timer_idx].DMADstAddress,
04816                        hhrtim->TimerParam[timer_idx].DMASize);
04817
04818       /* Enable the timer DMA request */
04819       __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim,
04820                                    timer_idx,
04821                                    hhrtim->TimerParam[timer_idx].DMARequests);
04822     }
04823   }
04824
04825   /* Enable the timer counter */
04826   __HAL_HRTIM_ENABLE(hhrtim, Timers);
04827
04828   hhrtim->State = HAL_HRTIM_STATE_READY;
04829
04830   /* Process Unlocked */
04831   __HAL_UNLOCK(hhrtim);
04832
04833   return HAL_OK;
04834 }
04835
04836 /**
04837   * @brief  Stops the counter of the designated timer(s) operating in waveform mode
04838   *         Timers can be combined (ORed) to allow for simultaneous counter stop.
04839   * @param  hhrtim: pointer to HAL HRTIM handle
04840   * @param  Timers: Timer counter(s) to stop
04841   *                   This parameter can be any combination of the following values:
04842   *                   @arg HRTIM_TIMER_MASTER
04843   *                   @arg HRTIM_TIMER_A
04844   *                   @arg HRTIM_TIMER_B
04845   *                   @arg HRTIM_TIMER_C
04846   *                   @arg HRTIM_TIMER_D
04847   *                   @arg HRTIM_TIMER_E
04848   * @retval HAL status
04849   * @note  The counter of a timer is stopped only if all timer outputs are disabled
04850   * @note  All enabled timer related DMA requests are disabled.
04851   */
04852 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef * hhrtim,
04853                                                     uint32_t Timers)
04854 {
04855   uint8_t timer_idx;
04856   DMA_HandleTypeDef * hdma;
04857
04858   /* Check the parameters */
04859   assert_param(IS_HRTIM_TIMERID(Timers));
04860
04861   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04862
04863   if (((Timers & HRTIM_TIMERID_MASTER) != RESET) &&
04864       (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0))
04865   {
04866     /* Disable the DMA */
04867     HAL_DMA_Abort(hhrtim->hdmaMaster);
04868
04869     /* Disable the DMA request(s) */
04870     __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim,
04871                                    hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
04872   }
04873
04874   for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
04875        timer_idx < HRTIM_TIMERINDEX_MASTER ;
04876        timer_idx++)
04877   {
04878     if (((Timers & TimerIdxToTimerId[timer_idx]) != RESET) &&
04879         (hhrtim->TimerParam[timer_idx].DMARequests != 0))
04880     {
04881       /* Get the timer DMA handler */
04882       hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
04883
04884       /* Disable the DMA */
04885       HAL_DMA_Abort(hdma);
04886
04887     /* Disable the DMA request(s) */
04888       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
04889                                     timer_idx,
04890                                     hhrtim->TimerParam[timer_idx].DMARequests);
04891     }
04892   }
04893
04894   /* Disable the timer counter */
04895   __HAL_HRTIM_DISABLE(hhrtim, Timers);
04896
04897   hhrtim->State = HAL_HRTIM_STATE_READY;
04898
04899   return HAL_OK;
04900 }
04901
04902 /**
04903   * @brief  Enables or disables the HRTIM burst mode controller.
04904   * @param  hhrtim: pointer to HAL HRTIM handle
04905   * @param  Enable: Burst mode controller enabling
04906   *                    This parameter can be one of the following values:
04907   *                    @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
04908   *                    @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
04909   * @retval HAL status
04910   * @note This function must be called after starting the timer(s)
04911   */
04912 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,
04913                                          uint32_t Enable)
04914 {
04915   uint32_t hrtim_bmcr;
04916
04917   /* Check parameters */
04918   assert_param(IS_HRTIM_BURSTMODECTL(Enable));
04919
04920   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04921   {
04922      return HAL_BUSY;
04923   }
04924
04925   /* Process Locked */
04926   __HAL_LOCK(hhrtim);
04927
04928   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04929
04930   /* Enable/Disable the burst mode controller */
04931   hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
04932   hrtim_bmcr &= ~(HRTIM_BMCR_BME);
04933   hrtim_bmcr |= Enable;
04934
04935   /* Update the HRTIM registers */
04936   hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
04937
04938   hhrtim->State = HAL_HRTIM_STATE_READY;
04939
04940   /* Process Unlocked */
04941   __HAL_UNLOCK(hhrtim);
04942
04943   return HAL_OK;
04944 }
04945
04946 /**
04947   * @brief  Triggers the burst mode operation.
04948   * @param  hhrtim: pointer to HAL HRTIM handle
04949   * @retval HAL status
04950   */
04951 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim)
04952 {
04953   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04954   {
04955      return HAL_BUSY;
04956   }
04957
04958   /* Process Locked */
04959   __HAL_LOCK(hhrtim);
04960
04961   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04962
04963   /* Software trigger of the burst mode controller */
04964   hhrtim->Instance->sCommonRegs.BMTRGR |= HRTIM_BMTRGR_SW;
04965
04966   hhrtim->State = HAL_HRTIM_STATE_READY;
04967
04968   /* Process Unlocked */
04969   __HAL_UNLOCK(hhrtim);
04970
04971   return HAL_OK;
04972 }
04973
04974 /**
04975   * @brief  Triggers a software capture on the designed capture unit
04976   * @param  hhrtim: pointer to HAL HRTIM handle
04977   * @param  TimerIdx: Timer index
04978   *                   This parameter can be one of the following values:
04979   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04980   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04981   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04982   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04983   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04984   * @param  CaptureUnit: Capture unit to trig
04985   *                    This parameter can be one of the following values:
04986   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
04987   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
04988   * @retval HAL status
04989   * @note The 'software capture' bit in the capure configuration register is
04990   *       automatically reset by hardware
04991   */
04992 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,
04993                                             uint32_t TimerIdx,
04994                                             uint32_t CaptureUnit)
04995 {
04996   /* Check parameters */
04997   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
04998   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
04999
05000   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05001   {
05002      return HAL_BUSY;
05003   }
05004
05005   /* Process Locked */
05006   __HAL_LOCK(hhrtim);
05007
05008   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05009
05010   /* Force a software capture on concerned capture unit */
05011   switch (CaptureUnit)
05012   {
05013   case HRTIM_CAPTUREUNIT_1:
05014     {
05015       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR |= HRTIM_CPT1CR_SWCPT;
05016     }
05017     break;
05018   case HRTIM_CAPTUREUNIT_2:
05019     {
05020       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR |= HRTIM_CPT2CR_SWCPT;
05021     }
05022     break;
05023   }
05024
05025   hhrtim->State = HAL_HRTIM_STATE_READY;
05026
05027   /* Process Unlocked */
05028   __HAL_UNLOCK(hhrtim);
05029
05030   return HAL_OK;
05031 }
05032
05033 /**
05034   * @brief  Triggers the update of the registers of one or several timers
05035   * @param  hhrtim: pointer to HAL HRTIM handle
05036   * @param  Timers: timers concerned with the software register update
05037   *                   This parameter can be any combination of the following values:
05038   *                   @arg HRTIM_TIMERUPDATE_MASTER
05039   *                   @arg HRTIM_TIMERUPDATE_A
05040   *                   @arg HRTIM_TIMERUPDATE_B
05041   *                   @arg HRTIM_TIMERUPDATE_C
05042   *                   @arg HRTIM_TIMERUPDATE_D
05043   *                   @arg HRTIM_TIMERUPDATE_E
05044   * @retval HAL status
05045   * @note The 'software update' bits in the HRTIM conrol register 2 register are
05046   *       automatically reset by hardware
05047   */
05048 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,
05049                                            uint32_t Timers)
05050 {
05051   /* Check parameters */
05052   assert_param(IS_HRTIM_TIMERUPDATE(Timers));
05053
05054   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05055   {
05056      return HAL_BUSY;
05057   }
05058
05059   /* Process Locked */
05060   __HAL_LOCK(hhrtim);
05061
05062   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05063
05064   /* Force timer(s) registers update */
05065   hhrtim->Instance->sCommonRegs.CR2 |= Timers;
05066
05067   hhrtim->State = HAL_HRTIM_STATE_READY;
05068
05069   /* Process Unlocked */
05070   __HAL_UNLOCK(hhrtim);
05071
05072   return HAL_OK;
05073 }
05074
05075 /**
05076   * @brief  Triggers the reset of one or several timers
05077   * @param  hhrtim: pointer to HAL HRTIM handle
05078   * @param  Timers: timers concerned with the software counter reset
05079   *                   This parameter can be any combination of the following values:
05080   *                   @arg HRTIM_TIMERRESET_MASTER
05081   *                   @arg HRTIM_TIMERRESET_TIMER_A
05082   *                   @arg HRTIM_TIMERRESET_TIMER_B
05083   *                   @arg HRTIM_TIMERRESET_TIMER_C
05084   *                   @arg HRTIM_TIMERRESET_TIMER_D
05085   *                   @arg HRTIM_TIMERRESET_TIMER_E
05086   * @retval HAL status
05087   * @note The 'software reset' bits in the HRTIM conrol register 2  are
05088   *       automatically reset by hardware
05089   */
05090 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,
05091                                           uint32_t Timers)
05092 {
05093   /* Check parameters */
05094   assert_param(IS_HRTIM_TIMERRESET(Timers));
05095
05096   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05097   {
05098      return HAL_BUSY;
05099   }
05100
05101   /* Process Locked */
05102   __HAL_LOCK(hhrtim);
05103
05104   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05105
05106   /* Force timer(s) registers reset */
05107   hhrtim->Instance->sCommonRegs.CR2 = Timers;
05108
05109   hhrtim->State = HAL_HRTIM_STATE_READY;
05110
05111   /* Process Unlocked */
05112   __HAL_UNLOCK(hhrtim);
05113
05114   return HAL_OK;
05115 }
05116
05117 /**
05118   * @brief  Starts a burst DMA operation to update HRTIM control registers content
05119   * @param  hhrtim: pointer to HAL HRTIM handle
05120   * @param  TimerIdx: Timer index
05121   *                   This parameter can be one of the following values:
05122   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
05123   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05124   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05125   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05126   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05127   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05128   * @param  BurstBufferAddress: address of the buffer the HRTIM control registers
05129   *                             content will be updated from.
05130   * @param  BurstBufferLength: size (in WORDS) of the burst buffer.
05131   * @retval HAL status
05132   * @note The TimerIdx parameter determines the dma channel to be used by the
05133   *       DMA burst controller (see below)
05134   *       HRTIM_TIMERINDEX_MASTER: DMA channel 2 is used by the DMA burst controller
05135   *       HRTIM_TIMERINDEX_TIMER_A: DMA channel 3 is used by the DMA burst controller
05136   *       HRTIM_TIMERINDEX_TIMER_B: DMA channel 4 is used by the DMA burst controller
05137   *       HRTIM_TIMERINDEX_TIMER_C: DMA channel 5 is used by the DMA burst controller
05138   *       HRTIM_TIMERINDEX_TIMER_D: DMA channel 6 is used by the DMA burst controller
05139   *       HRTIM_TIMERINDEX_TIMER_E: DMA channel 7 is used by the DMA burst controller
05140   */
05141 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
05142                                              uint32_t TimerIdx,
05143                                              uint32_t BurstBufferAddress,
05144                                              uint32_t BurstBufferLength)
05145 {
05146   DMA_HandleTypeDef * hdma;
05147
05148   /* Check the parameters */
05149   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
05150
05151   if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
05152   {
05153      return HAL_BUSY;
05154   }
05155   if((hhrtim->State == HAL_HRTIM_STATE_READY))
05156   {
05157     if((BurstBufferAddress == 0 ) || (BurstBufferLength == 0))
05158     {
05159       return HAL_ERROR;
05160     }
05161     else
05162     {
05163       hhrtim->State = HAL_HRTIM_STATE_BUSY;
05164     }
05165   }
05166
05167   /* Process Locked */
05168   __HAL_LOCK(hhrtim);
05169
05170   /* Get the timer DMA handler */
05171   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
05172
05173   /* Set the DMA transfer completed callback */
05174   hdma->XferCpltCallback = HRTIM_BurstDMACplt;
05175
05176   /* Set the DMA error callback */
05177   hdma->XferErrorCallback = HRTIM_DMAError ;
05178
05179   /* Enable the DMA channel */
05180   HAL_DMA_Start_IT(hdma,
05181                    BurstBufferAddress,
05182                    (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR),
05183                    BurstBufferLength);
05184
05185   hhrtim->State = HAL_HRTIM_STATE_READY;
05186
05187   /* Process Unlocked */
05188   __HAL_UNLOCK(hhrtim);
05189
05190   return HAL_OK;
05191 }
05192
05193 /**
05194   * @brief  Enables the transfer from preload to active registers for one
05195   *         or several timing units (including master timer).
05196   * @param  hhrtim: pointer to HAL HRTIM handle
05197   * @param  Timers: Timer(s) concerned by the register preload enabling command
05198   *                   This parameter can be any combination of the following values:
05199   *                   @arg HRTIM_TIMERUPDATE_MASTER
05200   *                   @arg HRTIM_TIMERUPDATE_A
05201   *                   @arg HRTIM_TIMERUPDATE_B
05202   *                   @arg HRTIM_TIMERUPDATE_C
05203   *                   @arg HRTIM_TIMERUPDATE_D
05204   *                   @arg HRTIM_TIMERUPDATE_E
05205   * @retval HAL status
05206   */
05207 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
05208                                           uint32_t Timers)
05209 {
05210    /* Check the parameters */
05211   assert_param(IS_HRTIM_TIMERUPDATE(Timers));
05212
05213   /* Process Locked */
05214   __HAL_LOCK(hhrtim);
05215
05216   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05217
05218   /* Enable timer(s) registers update */
05219   hhrtim->Instance->sCommonRegs.CR1 &= ~(Timers);
05220
05221   hhrtim->State = HAL_HRTIM_STATE_READY;
05222
05223   /* Process Unlocked */
05224   __HAL_UNLOCK(hhrtim);
05225
05226   return HAL_OK;
05227   }
05228
05229 /**
05230   * @brief  Disables the transfer from preload to active registers for one
05231   *         or several timing units (including master timer).
05232   * @param  hhrtim: pointer to HAL HRTIM handle
05233   * @param  Timers: Timer(s) concerned by the register preload disabling command
05234   *                   This parameter can be any combination of the following values:
05235   *                   @arg HRTIM_TIMERUPDATE_MASTER
05236   *                   @arg HRTIM_TIMERUPDATE_A
05237   *                   @arg HRTIM_TIMERUPDATE_B
05238   *                   @arg HRTIM_TIMERUPDATE_C
05239   *                   @arg HRTIM_TIMERUPDATE_D
05240   *                   @arg HRTIM_TIMERUPDATE_E
05241   * @retval HAL status
05242   */
05243 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
05244                                           uint32_t Timers)
05245 {
05246    /* Check the parameters */
05247   assert_param(IS_HRTIM_TIMERUPDATE(Timers));
05248
05249   /* Process Locked */
05250   __HAL_LOCK(hhrtim);
05251
05252   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05253
05254   /* Enable timer(s) registers update */
05255   hhrtim->Instance->sCommonRegs.CR1 |= (Timers);
05256
05257   hhrtim->State = HAL_HRTIM_STATE_READY;
05258
05259   /* Process Unlocked */
05260   __HAL_UNLOCK(hhrtim);
05261
05262   return HAL_OK;
05263   }
05264
05265 /**
05266   * @}
05267   */
05268
05269 /** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions
05270  *  @brief    Peripheral State functions
05271
05272 @verbatim
05273  ===============================================================================
05274               ##### Peripheral State functions #####
05275  ===============================================================================
05276     [..]  This section provides functions used to get HRTIM or HRTIM timer
05277           specific information:
05278       (+) Get HRTIM HAL state
05279       (+) Get captured value
05280       (+) Get HRTIM timer output level
05281       (+) Get HRTIM timer output state
05282       (+) Get delayed protection status
05283       (+) Get burst status
05284       (+) Get current push-pull status
05285       (+) Get idle push-pull status
05286
05287 @endverbatim
05288   * @{
05289   */
05290
05291 /**
05292   * @brief  return the HRTIM HAL state
05293   * @param  hhrtim: pointer to HAL HRTIM handle
05294   * @retval HAL state
05295   */
05296 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim)
05297 {
05298   /* Return ADC state */
05299   return hhrtim->State;
05300 }
05301
05302 /**
05303   * @brief  Returns actual value of the capture register of the designated capture unit
05304   * @param  hhrtim: pointer to HAL HRTIM handle
05305   * @param  TimerIdx: Timer index
05306   *                   This parameter can be one of the following values:
05307   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05308   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05309   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05310   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05311   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05312   * @param  CaptureUnit: Capture unit to trig
05313   *                    This parameter can be one of the following values:
05314   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
05315   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
05316   * @retval Captured value
05317   */
05318 uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
05319                                     uint32_t TimerIdx,
05320                                     uint32_t CaptureUnit)
05321 {
05322   uint32_t captured_value = 0;
05323
05324   /* Check parameters */
05325   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
05326   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
05327
05328   /* Read captured value */
05329   switch (CaptureUnit)
05330   {
05331   case HRTIM_CAPTUREUNIT_1:
05332     {
05333       captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR;
05334     }
05335     break;
05336   case HRTIM_CAPTUREUNIT_2:
05337     {
05338       captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR;
05339     }
05340     break;
05341   }
05342
05343   return captured_value;
05344 }
05345
05346 /**
05347   * @brief  Returns actual level (active or inactive) of the designated output
05348   * @param  hhrtim: pointer to HAL HRTIM handle
05349   * @param  TimerIdx: Timer index
05350   *                   This parameter can be one of the following values:
05351   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05352   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05353   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05354   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05355   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05356   * @param  Output: Timer output
05357   *                    This parameter can be one of the following values:
05358   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
05359   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
05360   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
05361   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
05362   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
05363   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
05364   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
05365   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
05366   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
05367   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
05368   * @retval Output level
05369   * @note Returned output level is taken before the output stage (chopper,
05370   *        polarity).
05371   */
05372 uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
05373                                           uint32_t TimerIdx,
05374                                           uint32_t Output)
05375 {
05376   uint32_t output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
05377
05378   /* Check parameters */
05379   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
05380
05381   /* Read the output level */
05382   switch (Output)
05383   {
05384   case HRTIM_OUTPUT_TA1:
05385   case HRTIM_OUTPUT_TB1:
05386   case HRTIM_OUTPUT_TC1:
05387   case HRTIM_OUTPUT_TD1:
05388   case HRTIM_OUTPUT_TE1:
05389     {
05390       if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != RESET)
05391       {
05392         output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
05393       }
05394       else
05395       {
05396         output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
05397       }
05398     }
05399     break;
05400   case HRTIM_OUTPUT_TA2:
05401   case HRTIM_OUTPUT_TB2:
05402   case HRTIM_OUTPUT_TC2:
05403   case HRTIM_OUTPUT_TD2:
05404   case HRTIM_OUTPUT_TE2:
05405     {
05406       if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != RESET)
05407       {
05408         output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
05409       }
05410       else
05411       {
05412         output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
05413       }
05414     }
05415     break;
05416   }
05417
05418   return output_level;
05419 }
05420
05421 /**
05422   * @brief  Returns actual state (RUN, IDLE, FAULT) of the designated output
05423   * @param  hhrtim: pointer to HAL HRTIM handle
05424   * @param  TimerIdx: Timer index
05425   *                   This parameter can be one of the following values:
05426   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05427   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05428   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05429   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05430   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05431   * @param  Output: Timer output
05432   *                    This parameter can be one of the following values:
05433   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
05434   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
05435   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
05436   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
05437   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
05438   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
05439   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
05440   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
05441   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
05442   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
05443   * @retval Output state
05444   */
05445 uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
05446                                           uint32_t TimerIdx,
05447                                           uint32_t Output)
05448 {
05449   uint32_t output_bit = 0;
05450   uint32_t output_state = HRTIM_OUTPUTSTATE_IDLE;
05451
05452   /* Check parameters */
05453   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
05454
05455   /* Set output state according to output control status and output disable status */
05456   switch (Output)
05457   {
05458   case HRTIM_OUTPUT_TA1:
05459     {
05460       output_bit = HRTIM_OENR_TA1OEN;
05461     }
05462     break;
05463   case HRTIM_OUTPUT_TA2:
05464     {
05465       output_bit = HRTIM_OENR_TA2OEN;
05466     }
05467     break;
05468   case HRTIM_OUTPUT_TB1:
05469     {
05470       output_bit = HRTIM_OENR_TB1OEN;
05471     }
05472     break;
05473   case HRTIM_OUTPUT_TB2:
05474     {
05475       output_bit = HRTIM_OENR_TB2OEN;
05476     }
05477     break;
05478   case HRTIM_OUTPUT_TC1:
05479     {
05480       output_bit = HRTIM_OENR_TC1OEN;
05481     }
05482     break;
05483   case HRTIM_OUTPUT_TC2:
05484     {
05485       output_bit = HRTIM_OENR_TC2OEN;
05486     }
05487     break;
05488   case HRTIM_OUTPUT_TD1:
05489     {
05490       output_bit = HRTIM_OENR_TD1OEN;
05491     }
05492     break;
05493   case HRTIM_OUTPUT_TD2:
05494     {
05495       output_bit = HRTIM_OENR_TD2OEN;
05496     }
05497     break;
05498   case HRTIM_OUTPUT_TE1:
05499     {
05500       output_bit = HRTIM_OENR_TE1OEN;
05501     }
05502     break;
05503   case HRTIM_OUTPUT_TE2:
05504     {
05505       output_bit = HRTIM_OENR_TE2OEN;
05506     }
05507     break;
05508   }
05509
05510   if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != RESET)
05511   {
05512     /* Output is enabled: output in RUN state (whatever ouput disable status is)*/
05513     output_state = HRTIM_OUTPUTSTATE_RUN;
05514   }
05515   else
05516   {
05517     if ((hhrtim->Instance->sCommonRegs.ODSR & output_bit) != RESET)
05518     {
05519     /* Output is disabled: output in FAULT state */
05520       output_state = HRTIM_OUTPUTSTATE_FAULT;
05521     }
05522     else
05523     {
05524       /* Output is disabled: output in IDLE state */
05525       output_state = HRTIM_OUTPUTSTATE_IDLE;
05526     }
05527   }
05528
05529   return(output_state);
05530 }
05531
05532 /**
05533   * @brief  Returns the level (active or inactive) of the designated output
05534   *         when the delayed protection was triggered.
05535   * @param  hhrtim: pointer to HAL HRTIM handle
05536   * @param  TimerIdx: Timer index
05537   *                   This parameter can be one of the following values:
05538   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05539   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05540   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05541   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05542   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05543   * @param  Output: Timer output
05544   *                    This parameter can be one of the following values:
05545   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
05546   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
05547   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
05548   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
05549   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
05550   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
05551   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
05552   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
05553   *                    @arg HRTIM_OUTPUT_TD1: Timer E - Output 1
05554   *                    @arg HRTIM_OUTPUT_TD2: Timer E - Output 2
05555   * @retval Delayed protection status
05556   */
05557 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim,
05558                                               uint32_t TimerIdx,
05559                                               uint32_t Output)
05560 {
05561   uint32_t delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
05562
05563   /* Check parameters */
05564   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
05565
05566   /* Read the delayed protection status */
05567   switch (Output)
05568   {
05569   case HRTIM_OUTPUT_TA1:
05570   case HRTIM_OUTPUT_TB1:
05571   case HRTIM_OUTPUT_TC1:
05572   case HRTIM_OUTPUT_TD1:
05573   case HRTIM_OUTPUT_TE1:
05574     {
05575       if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != RESET)
05576       {
05577         /* Output 1 was active when the delayed idle protection was triggered */
05578         delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
05579       }
05580       else
05581       {
05582         /* Output 1 was inactive when the delayed idle protection was triggered */
05583         delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
05584       }
05585     }
05586     break;
05587   case HRTIM_OUTPUT_TA2:
05588   case HRTIM_OUTPUT_TB2:
05589   case HRTIM_OUTPUT_TC2:
05590   case HRTIM_OUTPUT_TD2:
05591   case HRTIM_OUTPUT_TE2:
05592     {
05593       if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != RESET)
05594       {
05595         /* Output 2 was active when the delayed idle protection was triggered */
05596         delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
05597       }
05598       else
05599       {
05600         /* Output 2 was inactive when the delayed idle protection was triggered */
05601         delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
05602       }
05603     }
05604     break;
05605   }
05606
05607   return delayed_protection_status;
05608 }
05609
05610 /**
05611   * @brief  Returns the actual status (active or inactive) of the burst mode controller
05612   * @param  hhrtim: pointer to HAL HRTIM handle
05613   * @retval Burst mode controller status
05614   */
05615 uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef * hhrtim)
05616 {
05617   uint32_t burst_mode_status;
05618
05619   /* Read burst mode status */
05620   burst_mode_status = (hhrtim->Instance->sCommonRegs.BMCR & HRTIM_BMCR_BMSTAT);
05621
05622   return burst_mode_status;
05623 }
05624
05625 /**
05626   * @brief  Indicates on which output the signal is currently active (when the
05627   *         push pull mode is enabled).
05628   * @param  hhrtim: pointer to HAL HRTIM handle
05629   * @param  TimerIdx: Timer index
05630   *                   This parameter can be one of the following values:
05631   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05632   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05633   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05634   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05635   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05636   * @retval Burst mode controller status
05637   */
05638 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef * hhrtim,
05639                                             uint32_t TimerIdx)
05640 {
05641   uint32_t current_pushpull_status;
05642
05643    /* Check the parameters */
05644   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
05645
05646   /* Read current push pull status */
05647   current_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
05648
05649   return current_pushpull_status;
05650 }
05651
05652
05653 /**
05654   * @brief  Indicates on which output the signal was applied, in push-pull mode,
05655             balanced fault mode or delayed idle mode, when the protection was triggered.
05656   * @param  hhrtim: pointer to HAL HRTIM handle
05657   * @param  TimerIdx: Timer index
05658   *                   This parameter can be one of the following values:
05659   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05660   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05661   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05662   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05663   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05664   * @retval Idle Push Pull Status
05665   */
05666 uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef * hhrtim,
05667                                          uint32_t TimerIdx)
05668 {
05669   uint32_t idle_pushpull_status;
05670
05671    /* Check the parameters */
05672   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
05673
05674   /* Read current push pull status */
05675   idle_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
05676
05677   return idle_pushpull_status;
05678 }
05679
05680 /**
05681   * @}
05682   */
05683
05684 /** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling
05685  *  @brief  Functions called when HRTIM generates an interrupt
05686  *          7 interrupts can be generated by the master timer:
05687  *            - Master timer registers update
05688  *            - Synchronization event received
05689  *            - Master timer repetition event
05690  *            - Master Compare 1 to 4 event
05691  *          14 interrupts can be generated by each timing unit:
05692  *            - Delayed protection triggered
05693  *            - Counter reset or roll-over event
05694  *            - Output 1 and output 2 reset (transition active to inactive)
05695  *            - Output 1 and output 2 set (transition inactive to active)
05696  *            - Capture 1 and 2 events
05697  *            - Timing unit registers update
05698  *            - Repetition event
05699  *            - Compare 1 to 4 event
05700  *          8 global interrupts are generated for the whole HRTIM:
05701  *            - System fault and Fault 1 to 5 (regardless of the timing unit attribution)
05702  *            - Burst mode period completed
05703  *
05704 @verbatim
05705  ===============================================================================
05706                       ##### HRTIM interrupts handling #####
05707  ===============================================================================
05708     [..]
05709     This subsection provides a set of functions allowing to manage the HRTIM
05710     interrupts:
05711       (+)  HRTIM interrupt handler
05712       (+)  Callback function called when Fault1 interrupt occurs
05713       (+)  Callback function called when Fault2 interrupt occurs
05714       (+)  Callback function called when Fault3 interrupt occurs
05715       (+)  Callback function called when Fault4 interrupt occurs
05716       (+)  Callback function called when Fault5 interrupt occurs
05717       (+)  Callback function called when system Fault interrupt occurs
05718       (+)  Callback function called when burst mode period interrupt occurs
05719       (+)  Callback function called when synchronization input interrupt occurs
05720       (+)  Callback function called when a timer register update interrupt occurs
05721       (+)  Callback function called when a timer repetition interrupt occurs
05722       (+)  Callback function called when a compare 1 match interrupt occurs
05723       (+)  Callback function called when a compare 2 match interrupt occurs
05724       (+)  Callback function called when a compare 3 match interrupt occurs
05725       (+)  Callback function called when a compare 4 match interrupt occurs
05726       (+)  Callback function called when a capture 1 interrupt occurs
05727       (+)  Callback function called when a capture 2 interrupt occurs
05728       (+)  Callback function called when a delayed protection interrupt occurs
05729       (+)  Callback function called when a timer counter reset interrupt occurs
05730       (+)  Callback function called when a timer output 1 set interrupt occurs
05731       (+)  Callback function called when a timer output 1 reset interrupt occurs
05732       (+)  Callback function called when a timer output 2 set interrupt occurs
05733       (+)  Callback function called when a timer output 2 reset interrupt occurs
05734       (+)  Callback function called when a timer output 2 reset interrupt occurs
05735       (+)  Callback function called upon completion of a burst DMA transfer
05736
05737 @endverbatim
05738   * @{
05739   */
05740
05741 /**
05742   * @brief  This function handles HRTIM interrupt request.
05743   * @param  hhrtim: pointer to HAL HRTIM handle
05744   * @param  TimerIdx: Timer index
05745   *                   This parameter can be any value of @ref HRTIM_Timer_Index
05746   * @retval None
05747   */
05748 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,
05749                           uint32_t TimerIdx)
05750 {
05751   /* HRTIM interrupts handling */
05752   if (TimerIdx == HRTIM_TIMERINDEX_COMMON)
05753   {
05754     HRTIM_HRTIM_ISR(hhrtim);
05755   }
05756   else if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
05757   {
05758     /* Master related interrupts handling */
05759       HRTIM_Master_ISR(hhrtim);
05760   }
05761   else
05762   {
05763     /* Timing unit related interrupts handling */
05764     HRTIM_Timer_ISR(hhrtim, TimerIdx);
05765   }
05766
05767 }
05768
05769 /**
05770   * @brief  Callback function invoked when a fault 1 interrupt occured
05771   * @param  hhrtim: pointer to HAL HRTIM handle  * @retval None
05772   * @retval None
05773   */
05774 __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)
05775 {
05776   /* Prevent unused argument(s) compilation warning */
05777   UNUSED(hhrtim);
05778
05779   /* NOTE : This function should not be modified, when the callback is needed,
05780             the HAL_HRTIM_Fault1Callback could be implenetd in the user file
05781    */
05782 }
05783
05784 /**
05785   * @brief  Callback function invoked when a fault 2 interrupt occured
05786   * @param  hhrtim: pointer to HAL HRTIM handle
05787   * @retval None
05788   */
05789 __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)
05790 {
05791   /* Prevent unused argument(s) compilation warning */
05792   UNUSED(hhrtim);
05793
05794   /* NOTE : This function should not be modified, when the callback is needed,
05795             the HAL_HRTIM_Fault2Callback could be implenetd in the user file
05796    */
05797 }
05798
05799 /**
05800   * @brief  Callback function invoked when a fault 3 interrupt occured
05801   * @param  hhrtim: pointer to HAL HRTIM handle
05802   * @retval None
05803   */
05804 __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)
05805 {
05806   /* Prevent unused argument(s) compilation warning */
05807   UNUSED(hhrtim);
05808
05809   /* NOTE : This function should not be modified, when the callback is needed,
05810             the HAL_HRTIM_Fault3Callback could be implenetd in the user file
05811    */
05812 }
05813
05814 /**
05815   * @brief  Callback function invoked when a fault 4 interrupt occured
05816   * @param  hhrtim: pointer to HAL HRTIM handle
05817   * @retval None
05818   */
05819 __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)
05820 {
05821   /* Prevent unused argument(s) compilation warning */
05822   UNUSED(hhrtim);
05823
05824   /* NOTE : This function should not be modified, when the callback is needed,
05825             the HAL_HRTIM_Fault4Callback could be implenetd in the user file
05826    */
05827 }
05828
05829 /**
05830   * @brief  Callback function invoked when a fault 5 interrupt occured
05831   * @param  hhrtim: pointer to HAL HRTIM handle
05832   * @retval None
05833   */
05834 __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)
05835 {
05836   /* Prevent unused argument(s) compilation warning */
05837   UNUSED(hhrtim);
05838
05839   /* NOTE : This function should not be modified, when the callback is needed,
05840             the HAL_HRTIM_Fault5Callback could be implenetd in the user file
05841    */
05842 }
05843
05844 /**
05845   * @brief  Callback function invoked when a system fault interrupt occured
05846   * @param  hhrtim: pointer to HAL HRTIM handle
05847   * @retval None
05848   */
05849 __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)
05850 {
05851   /* Prevent unused argument(s) compilation warning */
05852   UNUSED(hhrtim);
05853
05854   /* NOTE : This function should not be modified, when the callback is needed,
05855             the HAL_HRTIM_SystemFaultCallback could be implenetd in the user file
05856    */
05857 }
05858
05859 /**
05860   * @brief  Callback function invoked when the end of the burst mode period is reached
05861   * @param  hhrtim: pointer to HAL HRTIM handle
05862   * @retval None
05863   */
05864 __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)
05865 {
05866   /* Prevent unused argument(s) compilation warning */
05867   UNUSED(hhrtim);
05868
05869   /* NOTE : This function should not be modified, when the callback is needed,
05870             the HAL_HRTIM_BurstModeCallback could be implenetd in the user file
05871    */
05872 }
05873
05874 /**
05875   * @brief  Callback function invoked when a synchronization input event is received
05876   * @param  hhrtim: pointer to HAL HRTIM handle
05877   * @retval None
05878   */
05879 __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)
05880 {
05881   /* Prevent unused argument(s) compilation warning */
05882   UNUSED(hhrtim);
05883
05884   /* NOTE : This function should not be modified, when the callback is needed,
05885             the HAL_HRTIM_Master_SynchronizationEventCallback could be implenetd in the user file
05886    */
05887 }
05888
05889 /**
05890   * @brief  Callback function invoked when timer registers are updated
05891   * @param  hhrtim: pointer to HAL HRTIM handle
05892   * @param  TimerIdx: Timer index
05893   *                   This parameter can be one of the following values:
05894   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
05895   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05896   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05897   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05898   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05899   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05900   * @retval None
05901   */
05902 __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,
05903                                               uint32_t TimerIdx)
05904 {
05905   /* Prevent unused argument(s) compilation warning */
05906   UNUSED(hhrtim);
05907   UNUSED(TimerIdx);
05908
05909   /* NOTE : This function should not be modified, when the callback is needed,
05910             the HAL_HRTIM_Master_RegistersUpdateCallback could be implenetd in the user file
05911    */
05912 }
05913
05914 /**
05915   * @brief  Callback function invoked when timer repetition period has elapsed
05916   * @param  hhrtim: pointer to HAL HRTIM handle
05917   * @param  TimerIdx: Timer index
05918   *                   This parameter can be one of the following values:
05919   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
05920   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05921   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05922   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05923   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05924   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05925   * @retval None
05926   */
05927 __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,
05928                                               uint32_t TimerIdx)
05929 {
05930   /* Prevent unused argument(s) compilation warning */
05931   UNUSED(hhrtim);
05932   UNUSED(TimerIdx);
05933
05934   /* NOTE : This function should not be modified, when the callback is needed,
05935             the HAL_HRTIM_Master_RepetitionEventCallback could be implenetd in the user file
05936    */
05937 }
05938
05939 /**
05940   * @brief  Callback function invoked when the timer counter matches the value
05941   *         programmed in the compare 1 register
05942   * @param  hhrtim: pointer to HAL HRTIM handle
05943   * @param  TimerIdx: Timer index
05944   *                   This parameter can be one of the following values:
05945   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
05946   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05947   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05948   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05949   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05950   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05951   * @retval None
05952   */
05953 __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,
05954                                               uint32_t TimerIdx)
05955 {
05956   /* Prevent unused argument(s) compilation warning */
05957   UNUSED(hhrtim);
05958   UNUSED(TimerIdx);
05959
05960   /* NOTE : This function should not be modified, when the callback is needed,
05961             the HAL_HRTIM_Master_Compare1EventCallback could be implenetd in the user file
05962    */
05963 }
05964
05965 /**
05966   * @brief  Callback function invoked when the timer counter matches the value
05967   *         programmed in the compare 2 register
05968   * @param  hhrtim: pointer to HAL HRTIM handle
05969   * @retval None
05970   * @param  TimerIdx: Timer index
05971   *                   This parameter can be one of the following values:
05972   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
05973   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05974   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05975   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05976   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05977   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05978   */
05979 __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,
05980                                               uint32_t TimerIdx)
05981 {
05982   /* Prevent unused argument(s) compilation warning */
05983   UNUSED(hhrtim);
05984   UNUSED(TimerIdx);
05985
05986   /* NOTE : This function should not be modified, when the callback is needed,
05987             the HAL_HRTIM_Master_Compare2EventCallback could be implenetd in the user file
05988    */
05989 }
05990
05991 /**
05992   * @brief  Callback function invoked when the timer counter matches the value
05993   *         programmed in the compare 3 register
05994   * @param  hhrtim: pointer to HAL HRTIM handle
05995   * @param  TimerIdx: Timer index
05996   *                   This parameter can be one of the following values:
05997   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
05998   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05999   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06000   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06001   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06002   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06003   * @retval None
06004   */
06005 __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,
06006                                               uint32_t TimerIdx)
06007 {
06008   /* Prevent unused argument(s) compilation warning */
06009   UNUSED(hhrtim);
06010   UNUSED(TimerIdx);
06011
06012   /* NOTE : This function should not be modified, when the callback is needed,
06013             the HAL_HRTIM_Master_Compare3EventCallback could be implenetd in the user file
06014    */
06015 }
06016
06017 /**
06018   * @brief  Callback function invoked when the timer counter matches the value
06019   *         programmed in the compare 4 register
06020   * @param  hhrtim: pointer to HAL HRTIM handle
06021   * @param  TimerIdx: Timer index
06022   *                   This parameter can be one of the following values:
06023   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
06024   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06025   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06026   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06027   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06028   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06029   * @retval None
06030   */
06031 __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,
06032                                               uint32_t TimerIdx)
06033 {
06034   /* Prevent unused argument(s) compilation warning */
06035   UNUSED(hhrtim);
06036   UNUSED(TimerIdx);
06037
06038   /* NOTE : This function should not be modified, when the callback is needed,
06039             the HAL_HRTIM_Master_Compare4EventCallback could be implenetd in the user file
06040    */
06041 }
06042
06043 /**
06044   * @brief  Callback function invoked when the timer x capture 1 event occurs
06045   * @param  hhrtim: pointer to HAL HRTIM handle
06046   * @param  TimerIdx: Timer index
06047   *                   This parameter can be one of the following values:
06048   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06049   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06050   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06051   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06052   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06053   * @retval None
06054   */
06055 __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,
06056                                               uint32_t TimerIdx)
06057 {
06058   /* Prevent unused argument(s) compilation warning */
06059   UNUSED(hhrtim);
06060   UNUSED(TimerIdx);
06061
06062   /* NOTE : This function should not be modified, when the callback is needed,
06063             the HAL_HRTIM_Timer_Capture1EventCallback could be implenetd in the user file
06064    */
06065 }
06066
06067 /**
06068   * @brief  Callback function invoked when the timer x capture 2 event occurs
06069   * @param  hhrtim: pointer to HAL HRTIM handle
06070   * @param  TimerIdx: Timer index
06071   *                   This parameter can be one of the following values:
06072   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06073   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06074   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06075   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06076   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06077   * @retval None
06078   */
06079 __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,
06080                                               uint32_t TimerIdx)
06081 {
06082   /* Prevent unused argument(s) compilation warning */
06083   UNUSED(hhrtim);
06084   UNUSED(TimerIdx);
06085
06086   /* NOTE : This function should not be modified, when the callback is needed,
06087             the HAL_HRTIM_Timer_Capture2EventCallback could be implenetd in the user file
06088    */
06089 }
06090
06091 /**
06092   * @brief  Callback function invoked when the delayed idle or balanced idle mode is
06093   *         entered
06094   * @param  hhrtim: pointer to HAL HRTIM handle
06095   * @param  TimerIdx: Timer index
06096   *                   This parameter can be one of the following values:
06097   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06098   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06099   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06100   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06101   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06102   * @retval None
06103   */
06104 __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,
06105                                               uint32_t TimerIdx)
06106 {
06107   /* Prevent unused argument(s) compilation warning */
06108   UNUSED(hhrtim);
06109   UNUSED(TimerIdx);
06110
06111   /* NOTE : This function should not be modified, when the callback is needed,
06112             the HAL_HRTIM_Timer_DelayedProtectionCallback could be implenetd in the user file
06113    */
06114 }
06115
06116 /**
06117   * @brief  Callback function invoked when the timer x counter reset/roll-over
06118   *         event occurs
06119   * @param  hhrtim: pointer to HAL HRTIM handle
06120   * @param  TimerIdx: Timer index
06121   *                   This parameter can be one of the following values:
06122   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06123   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06124   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06125   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06126   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06127   * @retval None
06128   */
06129 __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,
06130                                               uint32_t TimerIdx)
06131 {
06132   /* Prevent unused argument(s) compilation warning */
06133   UNUSED(hhrtim);
06134   UNUSED(TimerIdx);
06135
06136   /* NOTE : This function should not be modified, when the callback is needed,
06137             the HAL_HRTIM_Timer_CounterResetCallback could be implenetd in the user file
06138    */
06139 }
06140
06141 /**
06142   * @brief  Callback function invoked when the timer x output 1 is set
06143   * @param  hhrtim: pointer to HAL HRTIM handle
06144   * @param  TimerIdx: Timer index
06145   *                   This parameter can be one of the following values:
06146   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06147   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06148   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06149   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06150   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06151   * @retval None
06152   */
06153 __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,
06154                                               uint32_t TimerIdx)
06155 {
06156   /* Prevent unused argument(s) compilation warning */
06157   UNUSED(hhrtim);
06158   UNUSED(TimerIdx);
06159
06160   /* NOTE : This function should not be modified, when the callback is needed,
06161             the HAL_HRTIM_Timer_Output1SetCallback could be implenetd in the user file
06162    */
06163 }
06164
06165 /**
06166   * @brief  Callback function invoked when the timer x output 1 is reset
06167   * @param  hhrtim: pointer to HAL HRTIM handle
06168   * @param  TimerIdx: Timer index
06169   *                   This parameter can be one of the following values:
06170   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06171   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06172   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06173   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06174   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06175   * @retval None
06176   */
06177 __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,
06178                                               uint32_t TimerIdx)
06179 {
06180   /* Prevent unused argument(s) compilation warning */
06181   UNUSED(hhrtim);
06182   UNUSED(TimerIdx);
06183
06184   /* NOTE : This function should not be modified, when the callback is needed,
06185             the HAL_HRTIM_Timer_Output1ResetCallback could be implenetd in the user file
06186    */
06187 }
06188
06189 /**
06190   * @brief  Callback function invoked when the timer x output 2 is set
06191   * @param  hhrtim: pointer to HAL HRTIM handle
06192   * @param  TimerIdx: Timer index
06193   *                   This parameter can be one of the following values:
06194   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06195   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06196   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06197   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06198   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06199   * @retval None
06200   */
06201 __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,
06202                                               uint32_t TimerIdx)
06203 {
06204   /* Prevent unused argument(s) compilation warning */
06205   UNUSED(hhrtim);
06206   UNUSED(TimerIdx);
06207
06208   /* NOTE : This function should not be modified, when the callback is needed,
06209             the HAL_HRTIM_Timer_Output2SetCallback could be implenetd in the user file
06210    */
06211 }
06212
06213 /**
06214   * @brief  Callback function invoked when the timer x output 2 is reset
06215   * @param  hhrtim: pointer to HAL HRTIM handle
06216   * @param  TimerIdx: Timer index
06217   *                   This parameter can be one of the following values:
06218   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06219   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06220   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06221   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06222   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06223  * @retval None
06224   */
06225 __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,
06226                                               uint32_t TimerIdx)
06227 {
06228   /* Prevent unused argument(s) compilation warning */
06229   UNUSED(hhrtim);
06230   UNUSED(TimerIdx);
06231
06232   /* NOTE : This function should not be modified, when the callback is needed,
06233             the HAL_HRTIM_Timer_Output2ResetCallback could be implenetd in the user file
06234    */
06235 }
06236
06237 /**
06238   * @brief  Callback function invoked when a DMA burst transfer is completed
06239   * @param  hhrtim: pointer to HAL HRTIM handle
06240   * @param  TimerIdx: Timer index
06241   *                   This parameter can be one of the following values:
06242   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
06243   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06244   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06245   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06246   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06247   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06248   * @retval None
06249   */
06250 __weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,
06251                                                uint32_t TimerIdx)
06252 {
06253   /* Prevent unused argument(s) compilation warning */
06254   UNUSED(hhrtim);
06255   UNUSED(TimerIdx);
06256
06257   /* NOTE : This function should not be modified, when the callback is needed,
06258             the HAL_HRTIM_BurstDMATransferCallback could be implenetd in the user file
06259    */
06260 }
06261
06262 /**
06263   * @brief  Callback function invoked when a DMA error occurs
06264   * @param  hhrtim: pointer to HAL HRTIM handle
06265   * @retval None
06266   */
06267 __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
06268 {
06269   /* Prevent unused argument(s) compilation warning */
06270   UNUSED(hhrtim);
06271
06272   /* NOTE : This function should not be modified, when the callback is needed,
06273             the HAL_HRTIM_ErrorCallback could be implenetd in the user file
06274    */
06275 }
06276
06277 /**
06278   * @}
06279   */
06280
06281 /**
06282   * @}
06283   */
06284
06285 /** @addtogroup HRTIM_Private_Functions HRTIM Private Functions
06286   * @{
06287   */
06288
06289 /**
06290   * @brief  Configures the master timer time base
06291   * @param  hhrtim: pointer to HAL HRTIM handle
06292   * @param  pTimeBaseCfg: pointer to the time base configuration structure
06293   * @retval None
06294   */
06295 static void  HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
06296                                      HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
06297 {
06298   uint32_t hrtim_mcr;
06299
06300   /* Configure master timer */
06301   hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
06302
06303   /* Set the prescaler ratio */
06304   hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
06305   hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
06306
06307   /* Set the operating mode */
06308   hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
06309   hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode;
06310
06311   /* Update the HRTIM registers */
06312   hhrtim->Instance->sMasterRegs.MCR  = hrtim_mcr;
06313   hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period;
06314   hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter;
06315 }
06316
06317 /**
06318   * @brief  Configures timing unit (timer A to timer E) time base
06319   * @param  hhrtim: pointer to HAL HRTIM handle
06320   * @param  TimerIdx: Timer index
06321   * @param  pTimeBaseCfg: pointer to the time base configuration structure
06322   * @retval None
06323   */
06324 static void  HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
06325                                          uint32_t TimerIdx ,
06326                                          HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
06327 {
06328   uint32_t hrtim_timcr;
06329
06330   /* Configure master timing unit */
06331   hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
06332
06333   /* Set the prescaler ratio */
06334   hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
06335   hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
06336
06337   /* Set the operating mode */
06338   hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
06339   hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode;
06340
06341   /* Update the HRTIM registers */
06342   hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR  = hrtim_timcr;
06343   hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period;
06344   hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter;
06345 }
06346
06347 /**
06348   * @brief  Configures the master timer in waveform mode
06349   * @param  hhrtim: pointer to HAL HRTIM handle
06350   * @param  pTimerCfg: pointer to the timer configuration data structure
06351   * @retval None
06352   */
06353 static void  HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
06354                                          HRTIM_TimerCfgTypeDef * pTimerCfg)
06355 {
06356   uint32_t hrtim_mcr;
06357   uint32_t hrtim_bmcr;
06358
06359   /* Configure master timer */
06360   hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
06361   hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
06362
06363   /* Enable/Disable the half mode */
06364   hrtim_mcr &= ~(HRTIM_MCR_HALF);
06365   hrtim_mcr |= pTimerCfg->HalfModeEnable;
06366
06367   /* Enable/Disable the timer start upon synchronization event reception */
06368   hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
06369   hrtim_mcr |= pTimerCfg->StartOnSync;
06370
06371   /* Enable/Disable the timer reset upon synchronization event reception */
06372   hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM);
06373   hrtim_mcr |= pTimerCfg->ResetOnSync;
06374
06375   /* Enable/Disable the DAC synchronization event generation */
06376   hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
06377   hrtim_mcr |= pTimerCfg->DACSynchro;
06378
06379   /* Enable/Disable preload meachanism for timer registers */
06380   hrtim_mcr &= ~(HRTIM_MCR_PREEN);
06381   hrtim_mcr |= pTimerCfg->PreloadEnable;
06382
06383   /* Master timer registers update handling */
06384   hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
06385   hrtim_mcr |= (pTimerCfg->UpdateGating << 2);
06386
06387   /* Enable/Disable registers update on repetition */
06388   hrtim_mcr &= ~(HRTIM_MCR_MREPU);
06389   hrtim_mcr |= pTimerCfg->RepetitionUpdate;
06390
06391   /* Set the timer burst mode */
06392   hrtim_bmcr &= ~(HRTIM_BMCR_MTBM);
06393   hrtim_bmcr |= pTimerCfg->BurstMode;
06394
06395   /* Update the HRTIM registers */
06396   hhrtim->Instance->sMasterRegs.MCR  = hrtim_mcr;
06397   hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
06398 }
06399
06400 /**
06401   * @brief  Configures timing unit (timer A to timer E) in waveform mode
06402   * @param  hhrtim: pointer to HAL HRTIM handle
06403   * @param  TimerIdx: Timer index
06404   * @param  pTimerCfg: pointer to the timer configuration data structure
06405   * @retval None
06406   */
06407 static void  HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
06408                                              uint32_t TimerIdx,
06409                                              HRTIM_TimerCfgTypeDef * pTimerCfg)
06410 {
06411   uint32_t hrtim_timcr;
06412   uint32_t hrtim_timfltr;
06413   uint32_t hrtim_timoutr;
06414   uint32_t hrtim_timrstr;
06415   uint32_t hrtim_bmcr;
06416
06417   /* UPDGAT bitfield must be reset before programming a new value */
06418   hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
06419
06420   /* Configure timing unit (Timer A to Timer E) */
06421   hrtim_timcr   = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
06422   hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR;
06423   hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
06424   hrtim_timrstr = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR;
06425   hrtim_bmcr    = hhrtim->Instance->sCommonRegs.BMCR;
06426
06427   /* Enable/Disable the half mode */
06428   hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
06429   hrtim_timcr |= pTimerCfg->HalfModeEnable;
06430
06431   /* Enable/Disable the timer start upon synchronization event reception */
06432   hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
06433   hrtim_timcr |= pTimerCfg->StartOnSync;
06434
06435   /* Enable/Disable the timer reset upon synchronization event reception */
06436   hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST);
06437   hrtim_timcr |= pTimerCfg->ResetOnSync;
06438
06439   /* Enable/Disable the DAC synchronization event generation */
06440   hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
06441   hrtim_timcr |= pTimerCfg->DACSynchro;
06442
06443   /* Enable/Disable preload meachanism for timer registers */
06444   hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
06445   hrtim_timcr |= pTimerCfg->PreloadEnable;
06446
06447   /* Timing unit registers update handling */
06448   hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT);
06449   hrtim_timcr |= pTimerCfg->UpdateGating;
06450
06451   /* Enable/Disable registers update on repetition */
06452   hrtim_timcr &= ~(HRTIM_TIMCR_TREPU);
06453   if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
06454   {
06455     hrtim_timcr |= HRTIM_TIMCR_TREPU;
06456   }
06457
06458   /* Set the push-pull mode */
06459   hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL);
06460   hrtim_timcr |= pTimerCfg->PushPull;
06461
06462   /* Enable/Disable registers update on timer counter reset */
06463   hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU);
06464   hrtim_timcr |= pTimerCfg->ResetUpdate;
06465
06466   /* Set the timer update trigger */
06467   hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
06468   hrtim_timcr |= pTimerCfg->UpdateTrigger;
06469
06470
06471   /* Enable/Disable the fault channel at timer level */
06472   hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN);
06473   hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
06474
06475   /* Lock/Unlock fault sources at timer level */
06476   hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK);
06477   hrtim_timfltr |= pTimerCfg->FaultLock;
06478
06479   /* The deadtime cannot be used simultaneously with the push-pull mode */
06480   if (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_DISABLED)
06481   {
06482     /* Enable/Disable dead time insertion at timer level */
06483     hrtim_timoutr &= ~(HRTIM_OUTR_DTEN);
06484     hrtim_timoutr |= pTimerCfg->DeadTimeInsertion;
06485   }
06486
06487   /* Enable/Disable delayed protection at timer level
06488      Delayed Idle is available whatever the timer operating mode (regular, push-pull)
06489      Balanced Idle is only available in push-pull mode
06490   */
06491   if (((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)
06492        && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))
06493        || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED))
06494   {
06495     hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
06496     hrtim_timoutr |= pTimerCfg->DelayedProtectionMode;
06497   }
06498
06499   /* Set the timer counter reset trigger */
06500   hrtim_timrstr = pTimerCfg->ResetTrigger;
06501
06502   /* Set the timer burst mode */
06503   switch (TimerIdx)
06504   {
06505   case HRTIM_TIMERINDEX_TIMER_A:
06506     {
06507       hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
06508       hrtim_bmcr |= ( pTimerCfg->BurstMode << 1);
06509     }
06510     break;
06511   case HRTIM_TIMERINDEX_TIMER_B:
06512     {
06513       hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
06514       hrtim_bmcr |= ( pTimerCfg->BurstMode << 2);
06515     }
06516     break;
06517   case HRTIM_TIMERINDEX_TIMER_C:
06518     {
06519       hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
06520       hrtim_bmcr |= ( pTimerCfg->BurstMode << 3);
06521     }
06522     break;
06523   case HRTIM_TIMERINDEX_TIMER_D:
06524     {
06525       hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
06526       hrtim_bmcr |= ( pTimerCfg->BurstMode << 4);
06527     }
06528     break;
06529   case HRTIM_TIMERINDEX_TIMER_E:
06530     {
06531       hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
06532       hrtim_bmcr |= ( pTimerCfg->BurstMode << 5);
06533     }
06534     break;
06535   }
06536
06537   /* Update the HRTIM registers */
06538   hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR  = hrtim_timcr;
06539   hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr;
06540   hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr;
06541   hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr;
06542   hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
06543 }
06544
06545 /**
06546   * @brief  Configures a compare unit
06547   * @param  hhrtim: pointer to HAL HRTIM handle
06548   * @param  TimerIdx: Timer index
06549   * @param  CompareUnit: Compare unit identifier
06550   * @param  pCompareCfg: pointer to the compare unit configuration data structure
06551   * @retval None
06552   */
06553 static void  HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim,
06554                                      uint32_t TimerIdx,
06555                                      uint32_t CompareUnit,
06556                                      HRTIM_CompareCfgTypeDef * pCompareCfg)
06557 {
06558   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
06559   {
06560     /* Configure the compare unit of the master timer */
06561     switch (CompareUnit)
06562     {
06563     case HRTIM_COMPAREUNIT_1:
06564       {
06565         hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
06566       }
06567       break;
06568     case HRTIM_COMPAREUNIT_2:
06569       {
06570         hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
06571       }
06572       break;
06573     case HRTIM_COMPAREUNIT_3:
06574       {
06575         hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
06576       }
06577       break;
06578     case HRTIM_COMPAREUNIT_4:
06579       {
06580         hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
06581       }
06582       break;
06583     }
06584   }
06585   else
06586   {
06587     /* Configure the compare unit of the timing unit */
06588     switch (CompareUnit)
06589     {
06590     case HRTIM_COMPAREUNIT_1:
06591       {
06592         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
06593       }
06594       break;
06595     case HRTIM_COMPAREUNIT_2:
06596       {
06597         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
06598       }
06599       break;
06600     case HRTIM_COMPAREUNIT_3:
06601       {
06602         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
06603       }
06604       break;
06605     case HRTIM_COMPAREUNIT_4:
06606       {
06607         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
06608       }
06609       break;
06610     }
06611   }
06612 }
06613
06614 /**
06615   * @brief  Configures a capture unit
06616   * @param  hhrtim: pointer to HAL HRTIM handle
06617   * @param  TimerIdx: Timer index
06618   * @param  CaptureUnit: Capture unit identifier
06619   * @param  Event: Event reference
06620   * @retval None
06621   */
06622 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
06623                                     uint32_t TimerIdx,
06624                                     uint32_t CaptureUnit,
06625                                     uint32_t Event)
06626 {
06627   uint32_t CaptureTrigger = 0xFFFFFFFFU;
06628
06629   switch (Event)
06630   {
06631   case HRTIM_EVENT_1:
06632     {
06633       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
06634     }
06635     break;
06636   case HRTIM_EVENT_2:
06637     {
06638       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
06639     }
06640     break;
06641   case HRTIM_EVENT_3:
06642     {
06643       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
06644     }
06645     break;
06646   case HRTIM_EVENT_4:
06647     {
06648       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
06649     }
06650     break;
06651   case HRTIM_EVENT_5:
06652     {
06653       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
06654     }
06655     break;
06656   case HRTIM_EVENT_6:
06657     {
06658       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
06659     }
06660     break;
06661   case HRTIM_EVENT_7:
06662     {
06663       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
06664     }
06665     break;
06666   case HRTIM_EVENT_8:
06667     {
06668       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
06669     }
06670     break;
06671   case HRTIM_EVENT_9:
06672     {
06673       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
06674     }
06675     break;
06676   case HRTIM_EVENT_10:
06677     {
06678       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
06679     }
06680     break;
06681   }
06682
06683   switch (CaptureUnit)
06684   {
06685   case HRTIM_CAPTUREUNIT_1:
06686     {
06687       hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger;
06688     }
06689     break;
06690   case HRTIM_CAPTUREUNIT_2:
06691     {
06692       hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger;
06693     }
06694     break;
06695   }
06696 }
06697
06698 /**
06699   * @brief  Configures the output of a timing unit
06700   * @param  hhrtim: pointer to HAL HRTIM handle
06701   * @param  TimerIdx: Timer index
06702   * @param  Output: timing unit output identifier
06703   * @param  pOutputCfg: pointer to the output configuration data structure
06704   * @retval None
06705   */
06706 static void  HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
06707                                 uint32_t TimerIdx,
06708                                 uint32_t Output,
06709                                 HRTIM_OutputCfgTypeDef * pOutputCfg)
06710 {
06711   uint32_t hrtim_outr;
06712   uint32_t hrtim_dtr;
06713
06714   uint32_t shift = 0xFFFFFFFFU;
06715
06716   hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
06717   hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
06718
06719   switch (Output)
06720   {
06721   case HRTIM_OUTPUT_TA1:
06722   case HRTIM_OUTPUT_TB1:
06723   case HRTIM_OUTPUT_TC1:
06724   case HRTIM_OUTPUT_TD1:
06725   case HRTIM_OUTPUT_TE1:
06726     {
06727       /* Set the output set/reset crossbar */
06728       hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
06729       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
06730
06731       shift = 0;
06732     }
06733     break;
06734   case HRTIM_OUTPUT_TA2:
06735   case HRTIM_OUTPUT_TB2:
06736   case HRTIM_OUTPUT_TC2:
06737   case HRTIM_OUTPUT_TD2:
06738   case HRTIM_OUTPUT_TE2:
06739     {
06740       /* Set the output set/reset crossbar */
06741       hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
06742       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
06743
06744       shift = 16;
06745     }
06746     break;
06747   }
06748
06749   /* Clear output config */
06750   hrtim_outr &= ~((HRTIM_OUTR_POL1 |
06751                    HRTIM_OUTR_IDLM1 |
06752                    HRTIM_OUTR_IDLES1|
06753                    HRTIM_OUTR_FAULT1|
06754                    HRTIM_OUTR_CHP1 |
06755                    HRTIM_OUTR_DIDL1)  << shift);
06756
06757   /* Set the polarity */
06758   hrtim_outr |= (pOutputCfg->Polarity << shift);
06759
06760   /* Set the IDLE mode */
06761   hrtim_outr |= (pOutputCfg->IdleMode << shift);
06762
06763   /* Set the IDLE state */
06764   hrtim_outr |= (pOutputCfg->IdleLevel << shift);
06765
06766   /* Set the FAULT state */
06767   hrtim_outr |= (pOutputCfg->FaultLevel << shift);
06768
06769   /* Set the chopper mode */
06770   hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift);
06771
06772   /* Set the burst mode entry mode : deadtime insertion when entering the idle
06773      state during a burst mode operation is allowed only under the following
06774      conditions:
06775      - the outputs is active during the burst mode (IDLES=1)
06776      - positive deadtimes (SDTR/SDTF set to 0)
06777   */
06778   if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
06779       ((hrtim_dtr & HRTIM_DTR_SDTR) == RESET) &&
06780       ((hrtim_dtr & HRTIM_DTR_SDTF) == RESET))
06781   {
06782     hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
06783   }
06784
06785   /* Update HRTIM register */
06786   hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr;
06787 }
06788
06789 /**
06790   * @brief  Configures an external event channel
06791   * @param  hhrtim: pointer to HAL HRTIM handle
06792   * @param  Event: Event channel identifier
06793   * @param  pEventCfg: pointer to the event channel configuration data structure
06794   * @retval None
06795   */
06796 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
06797                               uint32_t Event,
06798                               HRTIM_EventCfgTypeDef *pEventCfg)
06799 {
06800   uint32_t hrtim_eecr1;
06801   uint32_t hrtim_eecr2;
06802   uint32_t hrtim_eecr3;
06803
06804   /* Configure external event channel */
06805   hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1;
06806   hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2;
06807   hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
06808
06809   switch (Event)
06810   {
06811   case HRTIM_EVENT_1:
06812     {
06813       hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
06814       hrtim_eecr1 |= pEventCfg->Source;
06815       hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL);
06816       hrtim_eecr1 |= pEventCfg->Sensitivity;
06817       /* Update the HRTIM registers (all bitfields but EE1FAST bit) */
06818       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
06819       /* Update the HRTIM registers (EE1FAST bit) */
06820       hrtim_eecr1 |= pEventCfg->FastMode;
06821       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
06822     }
06823     break;
06824   case HRTIM_EVENT_2:
06825     {
06826       hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
06827       hrtim_eecr1 |= (pEventCfg->Source << 6);
06828       hrtim_eecr1 |= ((pEventCfg->Polarity << 6) & (HRTIM_EECR1_EE2POL));
06829       hrtim_eecr1 |= (pEventCfg->Sensitivity << 6);
06830       /* Update the HRTIM registers (all bitfields but EE2FAST bit) */
06831       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
06832       /* Update the HRTIM registers (EE2FAST bit) */
06833       hrtim_eecr1 |= (pEventCfg->FastMode << 6);
06834       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
06835     }
06836     break;
06837   case HRTIM_EVENT_3:
06838     {
06839       hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
06840       hrtim_eecr1 |= (pEventCfg->Source << 12);
06841       hrtim_eecr1 |= ((pEventCfg->Polarity << 12) & (HRTIM_EECR1_EE3POL));
06842       hrtim_eecr1 |= (pEventCfg->Sensitivity << 12);
06843       /* Update the HRTIM registers (all bitfields but EE3FAST bit) */
06844       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
06845       /* Update the HRTIM registers (EE3FAST bit) */
06846       hrtim_eecr1 |= (pEventCfg->FastMode << 12);
06847       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
06848     }
06849     break;
06850   case HRTIM_EVENT_4:
06851     {
06852       hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
06853       hrtim_eecr1 |= (pEventCfg->Source << 18);
06854       hrtim_eecr1 |= ((pEventCfg->Polarity << 18) & (HRTIM_EECR1_EE4POL));
06855       hrtim_eecr1 |= (pEventCfg->Sensitivity << 18);
06856       /* Update the HRTIM registers (all bitfields but EE4FAST bit) */
06857       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
06858       /* Update the HRTIM registers (EE4FAST bit) */
06859       hrtim_eecr1 |= (pEventCfg->FastMode << 18);
06860       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
06861     }
06862     break;
06863   case HRTIM_EVENT_5:
06864     {
06865       hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
06866       hrtim_eecr1 |= (pEventCfg->Source << 24);
06867       hrtim_eecr1 |= ((pEventCfg->Polarity << 24) & (HRTIM_EECR1_EE5POL));
06868       hrtim_eecr1 |= (pEventCfg->Sensitivity << 24);
06869       /* Update the HRTIM registers (all bitfields but EE5FAST bit) */
06870       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
06871       /* Update the HRTIM registers (EE5FAST bit) */
06872       hrtim_eecr1 |= (pEventCfg->FastMode << 24);
06873       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
06874     }
06875     break;
06876   case HRTIM_EVENT_6:
06877     {
06878       hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
06879       hrtim_eecr2 |= pEventCfg->Source;
06880       hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL);
06881       hrtim_eecr2 |= pEventCfg->Sensitivity;
06882       hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
06883       hrtim_eecr3 |= pEventCfg->Filter;
06884       /* Update the HRTIM registers */
06885       hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
06886       hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
06887     }
06888     break;
06889   case HRTIM_EVENT_7:
06890     {
06891       hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
06892       hrtim_eecr2 |= (pEventCfg->Source << 6);
06893       hrtim_eecr2 |= ((pEventCfg->Polarity << 6) & (HRTIM_EECR2_EE7POL));
06894       hrtim_eecr2 |= (pEventCfg->Sensitivity << 6);
06895       hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
06896       hrtim_eecr3 |= (pEventCfg->Filter << 6);
06897       /* Update the HRTIM registers */
06898       hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
06899       hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
06900     }
06901     break;
06902   case HRTIM_EVENT_8:
06903     {
06904       hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
06905       hrtim_eecr2 |= (pEventCfg->Source << 12);
06906       hrtim_eecr2 |= ((pEventCfg->Polarity << 12) & (HRTIM_EECR2_EE8POL));
06907       hrtim_eecr2 |= (pEventCfg->Sensitivity << 12);
06908       hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
06909       hrtim_eecr3 |= (pEventCfg->Filter << 12);
06910       /* Update the HRTIM registers */
06911       hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
06912       hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
06913     }
06914     break;
06915   case HRTIM_EVENT_9:
06916     {
06917       hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
06918       hrtim_eecr2 |= (pEventCfg->Source << 18);
06919       hrtim_eecr2 |= ((pEventCfg->Polarity << 18) & (HRTIM_EECR2_EE9POL));
06920       hrtim_eecr2 |= (pEventCfg->Sensitivity << 18);
06921       hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
06922       hrtim_eecr3 |= (pEventCfg->Filter << 18);
06923       /* Update the HRTIM registers */
06924       hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
06925       hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
06926     }
06927     break;
06928   case HRTIM_EVENT_10:
06929     {
06930       hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
06931       hrtim_eecr2 |= (pEventCfg->Source << 24);
06932       hrtim_eecr2 |= ((pEventCfg->Polarity << 24) & (HRTIM_EECR2_EE10POL));
06933       hrtim_eecr2 |= (pEventCfg->Sensitivity << 24);
06934       hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
06935       hrtim_eecr3 |= (pEventCfg->Filter << 24);
06936       /* Update the HRTIM registers */
06937       hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
06938       hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
06939     }
06940     break;
06941   default:
06942     break;
06943   }
06944 }
06945
06946 /**
06947   * @brief  Configures the timer counter reset
06948   * @param  hhrtim: pointer to HAL HRTIM handle
06949   * @param  TimerIdx: Timer index
06950   * @param  Event: Event channel identifier
06951   * @retval None
06952   */
06953 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
06954                                   uint32_t TimerIdx,
06955                                   uint32_t Event)
06956 {
06957   switch (Event)
06958   {
06959   case HRTIM_EVENT_1:
06960     {
06961       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
06962     }
06963     break;
06964   case HRTIM_EVENT_2:
06965     {
06966       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
06967     }
06968     break;
06969   case HRTIM_EVENT_3:
06970     {
06971       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
06972     }
06973     break;
06974   case HRTIM_EVENT_4:
06975     {
06976       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
06977     }
06978     break;
06979   case HRTIM_EVENT_5:
06980     {
06981       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
06982     }
06983     break;
06984   case HRTIM_EVENT_6:
06985     {
06986       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
06987     }
06988     break;
06989   case HRTIM_EVENT_7:
06990     {
06991       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
06992     }
06993     break;
06994   case HRTIM_EVENT_8:
06995     {
06996       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
06997     }
06998     break;
06999   case HRTIM_EVENT_9:
07000     {
07001       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
07002     }
07003     break;
07004   case HRTIM_EVENT_10:
07005     {
07006       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
07007     }
07008     break;
07009   }
07010 }
07011
07012 /**
07013   * @brief  Returns the interrupt to enable or disable according to the
07014   *         OC mode.
07015   * @param  hhrtim: pointer to HAL HRTIM handle
07016   * @param  TimerIdx: Timer index
07017   * @param  OCChannel: Timer output
07018   *                    This parameter can be one of the following values:
07019   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
07020   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
07021   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
07022   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
07023   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
07024   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
07025   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
07026   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
07027   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
07028   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
07029   * @retval Interrupt to enable or disable
07030   */
07031 static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
07032                                       uint32_t TimerIdx,
07033                                       uint32_t OCChannel)
07034 {
07035   uint32_t hrtim_set;
07036   uint32_t hrtim_reset;
07037   uint32_t interrupt = 0;
07038
07039   switch (OCChannel)
07040   {
07041   case HRTIM_OUTPUT_TA1:
07042   case HRTIM_OUTPUT_TB1:
07043   case HRTIM_OUTPUT_TC1:
07044   case HRTIM_OUTPUT_TD1:
07045   case HRTIM_OUTPUT_TE1:
07046     {
07047       /* Retreives actual OC mode and set interrupt accordingly */
07048       hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
07049       hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
07050
07051       if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
07052           ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
07053       {
07054         /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
07055         interrupt = HRTIM_TIM_IT_CMP1;
07056       }
07057       else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
07058                (hrtim_reset  == 0))
07059       {
07060          /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
07061         interrupt = HRTIM_TIM_IT_SET1;
07062       }
07063       else if ((hrtim_set == 0) &&
07064                ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
07065       {
07066          /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
07067         interrupt = HRTIM_TIM_IT_RST1;
07068       }
07069     }
07070     break;
07071   case HRTIM_OUTPUT_TA2:
07072   case HRTIM_OUTPUT_TB2:
07073   case HRTIM_OUTPUT_TC2:
07074   case HRTIM_OUTPUT_TD2:
07075   case HRTIM_OUTPUT_TE2:
07076     {
07077       /* Retreives actual OC mode and set interrupt accordingly */
07078       hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
07079       hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
07080
07081       if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
07082           ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
07083       {
07084         /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
07085         interrupt = HRTIM_TIM_IT_CMP2;
07086       }
07087       else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
07088                (hrtim_reset  == 0))
07089       {
07090          /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
07091         interrupt = HRTIM_TIM_IT_SET2;
07092       }
07093       else if ((hrtim_set == 0) &&
07094                ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
07095       {
07096          /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
07097         interrupt = HRTIM_TIM_IT_RST2;
07098       }
07099     }
07100     break;
07101   }
07102
07103   return interrupt;
07104 }
07105
07106 /**
07107   * @brief  Returns the DMA request to enable or disable according to the
07108   *         OC mode.
07109   * @param  hhrtim: pointer to HAL HRTIM handle
07110   * @param  TimerIdx: Timer index
07111   * @param  OCChannel: Timer output
07112   *                    This parameter can be one of the following values:
07113   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
07114   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
07115   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
07116   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
07117   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
07118   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
07119   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
07120   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
07121   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
07122   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
07123   * @retval DMA request to enable or disable
07124   */
07125 static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
07126                                        uint32_t TimerIdx,
07127                                        uint32_t OCChannel)
07128 {
07129   uint32_t hrtim_set;
07130   uint32_t hrtim_reset;
07131   uint32_t dma_request = 0;
07132
07133   switch (OCChannel)
07134   {
07135   case HRTIM_OUTPUT_TA1:
07136   case HRTIM_OUTPUT_TB1:
07137   case HRTIM_OUTPUT_TC1:
07138   case HRTIM_OUTPUT_TD1:
07139   case HRTIM_OUTPUT_TE1:
07140     {
07141       /* Retreives actual OC mode and set dma_request accordingly */
07142       hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
07143       hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
07144
07145       if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
07146           ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
07147       {
07148         /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
07149         dma_request = HRTIM_TIM_DMA_CMP1;
07150       }
07151       else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
07152                (hrtim_reset  == 0))
07153       {
07154          /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
07155         dma_request = HRTIM_TIM_DMA_SET1;
07156       }
07157       else if ((hrtim_set == 0) &&
07158                ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
07159       {
07160          /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
07161         dma_request = HRTIM_TIM_DMA_RST1;
07162       }
07163     }
07164     break;
07165   case HRTIM_OUTPUT_TA2:
07166   case HRTIM_OUTPUT_TB2:
07167   case HRTIM_OUTPUT_TC2:
07168   case HRTIM_OUTPUT_TD2:
07169   case HRTIM_OUTPUT_TE2:
07170     {
07171       /* Retreives actual OC mode and set dma_request accordingly */
07172       hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
07173       hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
07174
07175       if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
07176           ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
07177       {
07178         /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
07179         dma_request = HRTIM_TIM_DMA_CMP2;
07180       }
07181       else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
07182                (hrtim_reset  == 0))
07183       {
07184          /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
07185         dma_request = HRTIM_TIM_DMA_SET2;
07186       }
07187       else if ((hrtim_set == 0) &&
07188                ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
07189       {
07190          /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
07191         dma_request = HRTIM_TIM_DMA_RST2;
07192       }
07193     }
07194     break;
07195   }
07196
07197   return dma_request;
07198 }
07199
07200 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
07201                                                           uint32_t TimerIdx)
07202 {
07203   DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL;
07204
07205   switch (TimerIdx)
07206   {
07207   case HRTIM_TIMERINDEX_MASTER:
07208     {
07209       hdma = hhrtim->hdmaMaster;
07210     }
07211     break;
07212   case HRTIM_TIMERINDEX_TIMER_A:
07213     {
07214       hdma = hhrtim->hdmaTimerA;
07215     }
07216     break;
07217   case HRTIM_TIMERINDEX_TIMER_B:
07218     {
07219       hdma = hhrtim->hdmaTimerB;
07220     }
07221     break;
07222   case HRTIM_TIMERINDEX_TIMER_C:
07223     {
07224       hdma = hhrtim->hdmaTimerC;
07225     }
07226     break;
07227   case HRTIM_TIMERINDEX_TIMER_D:
07228     {
07229       hdma = hhrtim->hdmaTimerD;
07230     }
07231     break;
07232   case HRTIM_TIMERINDEX_TIMER_E:
07233     {
07234       hdma = hhrtim->hdmaTimerE;
07235     }
07236     break;
07237   }
07238
07239   return hdma;
07240 }
07241
07242 static uint32_t GetTimerIdxFromDMAHandle(DMA_HandleTypeDef *hdma)
07243 {
07244   uint32_t timed_idx = 0xFFFFFFFF;
07245
07246   if (hdma->Init.Request ==  DMA_REQUEST_HRTIM_MASTER)
07247   {
07248     timed_idx = HRTIM_TIMERINDEX_MASTER;
07249   }
07250   else if (hdma->Init.Request ==  DMA_REQUEST_HRTIM_TIMER_A)
07251   {
07252     timed_idx = HRTIM_TIMERINDEX_TIMER_A;
07253   }
07254   else if (hdma->Init.Request ==  DMA_REQUEST_HRTIM_TIMER_B)
07255   {
07256     timed_idx = HRTIM_TIMERINDEX_TIMER_B;
07257   }
07258   else if (hdma->Init.Request ==  DMA_REQUEST_HRTIM_TIMER_C)
07259   {
07260     timed_idx = HRTIM_TIMERINDEX_TIMER_C;
07261   }
07262   else if (hdma->Init.Request ==  DMA_REQUEST_HRTIM_TIMER_D)
07263   {
07264     timed_idx = HRTIM_TIMERINDEX_TIMER_D;
07265   }
07266   else if (hdma->Init.Request ==  DMA_REQUEST_HRTIM_TIMER_E)
07267   {
07268     timed_idx = HRTIM_TIMERINDEX_TIMER_E;
07269   }
07270
07271   return timed_idx;
07272 }
07273
07274 /**
07275   * @brief  Forces an immediate transfer from the preload to the active
07276   *         registers.
07277   * @param  hhrtim: pointer to HAL HRTIM handle
07278   * @param  TimerIdx: Timer index
07279   * @retval None
07280   */
07281 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
07282                                        uint32_t TimerIdx)
07283 {
07284   switch (TimerIdx)
07285   {
07286   case HRTIM_TIMERINDEX_MASTER:
07287     {
07288       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU;
07289     }
07290     break;
07291   case HRTIM_TIMERINDEX_TIMER_A:
07292     {
07293       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU;
07294     }
07295     break;
07296   case HRTIM_TIMERINDEX_TIMER_B:
07297     {
07298       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU;
07299     }
07300     break;
07301   case HRTIM_TIMERINDEX_TIMER_C:
07302     {
07303       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU;
07304     }
07305     break;
07306   case HRTIM_TIMERINDEX_TIMER_D:
07307     {
07308       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU;
07309     }
07310     break;
07311   case HRTIM_TIMERINDEX_TIMER_E:
07312     {
07313       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
07314     }
07315     break;
07316   }
07317 }
07318
07319
07320 /**
07321   * @brief  HRTIM interrupts service routine
07322   * @param  hhrtim: pointer to HAL HRTIM handle
07323   * @retval None
07324   */
07325 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)
07326 {
07327   /* Fault 1 event */
07328   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT1) != RESET)
07329   {
07330     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT1) != RESET)
07331     {
07332       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
07333
07334       /* Invoke Fault 1 event callback */
07335       HAL_HRTIM_Fault1Callback(hhrtim);
07336     }
07337   }
07338
07339   /* Fault 2 event */
07340   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT2) != RESET)
07341   {
07342     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT2) != RESET)
07343     {
07344       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
07345
07346       /* Invoke Fault 2 event callback */
07347       HAL_HRTIM_Fault2Callback(hhrtim);
07348     }
07349   }
07350
07351   /* Fault 3 event */
07352   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT3) != RESET)
07353   {
07354     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT3) != RESET)
07355     {
07356       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
07357
07358       /* Invoke Fault 3 event callback */
07359       HAL_HRTIM_Fault3Callback(hhrtim);
07360     }
07361   }
07362
07363   /* Fault 4 event */
07364   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT4) != RESET)
07365   {
07366     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT4) != RESET)
07367     {
07368       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
07369
07370       /* Invoke Fault 4 event callback */
07371       HAL_HRTIM_Fault4Callback(hhrtim);
07372     }
07373   }
07374
07375   /* Fault 5 event */
07376   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT5) != RESET)
07377   {
07378     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT5) != RESET)
07379     {
07380       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
07381
07382       /* Invoke Fault 5 event callback */
07383       HAL_HRTIM_Fault5Callback(hhrtim);
07384     }
07385   }
07386
07387   /* System fault event */
07388   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_SYSFLT) != RESET)
07389   {
07390     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_SYSFLT) != RESET)
07391     {
07392       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
07393
07394       /* Invoke System fault event callback */
07395       HAL_HRTIM_SystemFaultCallback(hhrtim);
07396     }
07397   }
07398 }
07399
07400 /**
07401 * @brief  Master timer interrupts service routine
07402 * @param  hhrtim: pointer to HAL HRTIM handle
07403 * @retval None
07404 */
07405 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)
07406 {
07407   /* Burst mode period event */
07408   if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_BMPER) != RESET)
07409   {
07410     if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_BMPER) != RESET)
07411     {
07412       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
07413
07414       /* Invoke Burst mode period event callback */
07415       HAL_HRTIM_BurstModePeriodCallback(hhrtim);
07416     }
07417   }
07418
07419   /* Master timer compare 1 event */
07420   if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP1) != RESET)
07421   {
07422     if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP1) != RESET)
07423     {
07424       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
07425
07426       /* Invoke compare 1 event callback */
07427       HAL_HRTIM_Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
07428     }
07429   }
07430
07431   /* Master timer compare 2 event */
07432   if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP2) != RESET)
07433   {
07434     if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP2) != RESET)
07435     {
07436       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
07437
07438       /* Invoke compare 2 event callback */
07439       HAL_HRTIM_Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
07440     }
07441   }
07442
07443   /* Master timer compare 3 event */
07444   if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP3) != RESET)
07445   {
07446     if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP3) != RESET)
07447     {
07448       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
07449
07450       /* Invoke compare 3 event callback */
07451       HAL_HRTIM_Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
07452     }
07453   }
07454
07455   /* Master timer compare 4 event */
07456   if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP4) != RESET)
07457   {
07458     if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP4) != RESET)
07459     {
07460       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
07461
07462       /* Invoke compare 4 event callback */
07463       HAL_HRTIM_Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
07464     }
07465   }
07466
07467   /* Master timer repetition event */
07468   if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MREP) != RESET)
07469   {
07470     if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MREP) != RESET)
07471     {
07472       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
07473
07474       /* Invoke repetition event callback */
07475       HAL_HRTIM_RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
07476     }
07477   }
07478
07479   /* Synchronization input event */
07480   if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_SYNC) != RESET)
07481   {
07482     if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_SYNC) != RESET)
07483     {
07484       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
07485
07486       /* Invoke synchronization event callback */
07487       HAL_HRTIM_SynchronizationEventCallback(hhrtim);
07488     }
07489   }
07490
07491   /* Master timer registers update event */
07492   if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MUPD) != RESET)
07493   {
07494     if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MUPD) != RESET)
07495     {
07496       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
07497
07498       /* Invoke registers update event callback */
07499       HAL_HRTIM_RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
07500     }
07501   }
07502 }
07503
07504 /**
07505   * @brief  Timer interrupts service routine
07506   * @param  hhrtim: pointer to HAL HRTIM handle
07507   * @param  TimerIdx: Timer index
07508   *                   This parameter can be one of the following values:
07509   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
07510   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
07511   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
07512   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
07513   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
07514   * @retval None
07515 */
07516 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
07517                      uint32_t TimerIdx)
07518 {
07519   /* Timer compare 1 event */
07520   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP1) != RESET)
07521   {
07522     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1) != RESET)
07523     {
07524       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
07525
07526       /* Invoke compare 1 event callback */
07527       HAL_HRTIM_Compare1EventCallback(hhrtim, TimerIdx);
07528     }
07529   }
07530
07531   /* Timer compare 2 event */
07532   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP2) != RESET)
07533   {
07534     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2) != RESET)
07535     {
07536       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
07537
07538       /* Invoke compare 2 event callback */
07539       HAL_HRTIM_Compare2EventCallback(hhrtim, TimerIdx);
07540     }
07541   }
07542
07543   /* Timer compare 3 event */
07544   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP3) != RESET)
07545   {
07546     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3) != RESET)
07547     {
07548       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
07549
07550       /* Invoke compare 3 event callback */
07551       HAL_HRTIM_Compare3EventCallback(hhrtim, TimerIdx);
07552     }
07553   }
07554
07555   /* Timer compare 4 event */
07556   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP4) != RESET)
07557   {
07558     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4) != RESET)
07559     {
07560       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
07561
07562       /* Invoke compare 4 event callback */
07563       HAL_HRTIM_Compare4EventCallback(hhrtim, TimerIdx);
07564     }
07565   }
07566
07567   /* Timer repetition event */
07568   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_REP) != RESET)
07569   {
07570     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_REP) != RESET)
07571     {
07572       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
07573
07574       /* Invoke repetition event callback */
07575       HAL_HRTIM_RepetitionEventCallback(hhrtim, TimerIdx);
07576     }
07577   }
07578
07579   /* Timer registers update event */
07580   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_UPD) != RESET)
07581   {
07582     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD) != RESET)
07583     {
07584       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
07585
07586       /* Invoke registers update event callback */
07587       HAL_HRTIM_RegistersUpdateCallback(hhrtim, TimerIdx);
07588     }
07589   }
07590
07591   /* Timer capture 1 event */
07592   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT1) != RESET)
07593   {
07594     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1) != RESET)
07595     {
07596       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
07597
07598       /* Invoke capture 1 event callback */
07599       HAL_HRTIM_Capture1EventCallback(hhrtim, TimerIdx);
07600     }
07601   }
07602
07603   /* Timer capture 2 event */
07604   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT2) != RESET)
07605   {
07606     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2) != RESET)
07607     {
07608       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
07609
07610       /* Invoke capture 2 event callback */
07611       HAL_HRTIM_Capture2EventCallback(hhrtim, TimerIdx);
07612     }
07613   }
07614
07615   /* Timer ouput 1 set event */
07616   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET1) != RESET)
07617   {
07618     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1) != RESET)
07619     {
07620       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
07621
07622       /* Invoke ouput 1 set event callback */
07623       HAL_HRTIM_Output1SetCallback(hhrtim, TimerIdx);
07624     }
07625   }
07626
07627   /* Timer ouput 1 reset event */
07628   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST1) != RESET)
07629   {
07630     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1) != RESET)
07631     {
07632       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
07633
07634       /* Invoke ouput 1 reset event callback */
07635       HAL_HRTIM_Output1ResetCallback(hhrtim, TimerIdx);
07636     }
07637   }
07638
07639   /* Timer ouput 2 set event */
07640   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET2) != RESET)
07641   {
07642     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2) != RESET)
07643     {
07644       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
07645
07646       /* Invoke ouput 2 set event callback */
07647       HAL_HRTIM_Output2SetCallback(hhrtim, TimerIdx);
07648     }
07649   }
07650
07651   /* Timer ouput 2 reset event */
07652   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST2) != RESET)
07653   {
07654     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2) != RESET)
07655     {
07656       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
07657
07658       /* Invoke ouput 2 reset event callback */
07659       HAL_HRTIM_Output2ResetCallback(hhrtim, TimerIdx);
07660     }
07661   }
07662
07663   /* Timer reset event */
07664   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST) != RESET)
07665   {
07666     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST) != RESET)
07667     {
07668       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
07669
07670       /* Invoke timer reset callback */
07671       HAL_HRTIM_CounterResetCallback(hhrtim, TimerIdx);
07672     }
07673   }
07674
07675   /* Delayed protection event */
07676   if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_DLYPRT) != RESET)
07677   {
07678     if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT) != RESET)
07679     {
07680       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
07681
07682       /* Invoke delayed protection callback */
07683       HAL_HRTIM_DelayedProtectionCallback(hhrtim, TimerIdx);
07684     }
07685   }
07686 }
07687
07688 /**
07689   * @brief  DMA callback invoked upon master timer related DMA request completion
07690   * @param  hdma: pointer to DMA handle.
07691   * @retval None
07692   */
07693 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
07694 {
07695   HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
07696
07697   if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != RESET)
07698   {
07699     HAL_HRTIM_Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
07700   }
07701   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != RESET)
07702   {
07703     HAL_HRTIM_Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
07704   }
07705   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != RESET)
07706   {
07707     HAL_HRTIM_Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
07708   }
07709   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != RESET)
07710   {
07711     HAL_HRTIM_Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
07712   }
07713   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != RESET)
07714   {
07715     HAL_HRTIM_RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
07716   }
07717   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != RESET)
07718   {
07719     HAL_HRTIM_SynchronizationEventCallback(hrtim);
07720   }
07721   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != RESET)
07722   {
07723     HAL_HRTIM_RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
07724   }
07725 }
07726
07727 /**
07728   * @brief  DMA callback invoked upon timer A..E related DMA request completion
07729   * @param  hdma: pointer to DMA handle.
07730   * @retval None
07731   */
07732 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
07733 {
07734   uint8_t timer_idx;
07735
07736   HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
07737
07738   timer_idx = GetTimerIdxFromDMAHandle(hdma);
07739
07740   if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != RESET)
07741   {
07742     HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
07743   }
07744   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != RESET)
07745   {
07746     HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
07747   }
07748   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != RESET)
07749   {
07750     HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
07751   }
07752   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != RESET)
07753   {
07754     HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
07755   }
07756   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != RESET)
07757   {
07758     HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
07759   }
07760   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != RESET)
07761   {
07762     HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
07763   }
07764   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != RESET)
07765   {
07766     HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
07767   }
07768   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != RESET)
07769   {
07770     HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
07771   }
07772   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != RESET)
07773   {
07774     HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
07775   }
07776   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != RESET)
07777   {
07778     HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
07779   }
07780   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != RESET)
07781   {
07782     HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
07783   }
07784   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != RESET)
07785   {
07786     HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
07787   }
07788   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != RESET)
07789   {
07790     HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
07791   }
07792   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != RESET)
07793   {
07794     HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
07795   }
07796 }
07797
07798 /**
07799 * @brief  DMA error callback
07800 * @param  hdma: pointer to DMA handle.
07801 * @retval None
07802 */
07803 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
07804 {
07805   HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
07806
07807   HAL_HRTIM_ErrorCallback(hrtim);
07808 }
07809
07810 /**
07811   * @brief  DMA callback invoked upon burst DMA transfer completion
07812   * @param  hdma: pointer to DMA handle.
07813   * @retval None
07814   */
07815 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
07816 {
07817   HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
07818
07819   HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hdma));
07820 }
07821
07822 /**
07823   * @}
07824   */
07825
07826 /**
07827   * @}
07828   */
07829 #endif /* HAL_HRTIM_MODULE_ENABLED */
07830
07831 /**
07832   * @}
07833   */
07834
07835 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
07836
07837
07838
Generated on Fri Apr 28 2017 15:42:38 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_hrtim.h Source File

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stm32h7xx_hal_hrtim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    STM32h7xx_hal_hrtim.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of HRTIM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_HRTIM_H
00040 #define __STM32H7xx_HAL_HRTIM_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup HRTIM HRTIM
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants
00059   * @{
00060   */
00061 /** @defgroup HRTIM_Max_Timer HRTIM Max Timer
00062   * @{
00063   */
00064 #define MAX_HRTIM_TIMER 6U
00065 /**
00066   * @}
00067   */
00068 /**
00069   * @}
00070   */
00071
00072 /** @defgroup HRTIM_Exported_Types HRTIM Exported Types
00073   * @{
00074   */
00075
00076 /**
00077   * @brief  HRTIM Configuration Structure definition - Time base related parameters
00078   */
00079 typedef struct
00080 {
00081   uint32_t HRTIMInterruptResquests;  /*!< Specifies which interrupts requests must enabled for the HRTIM instance
00082                                           This parameter can be any combination of  @ref HRTIM_Common_Interrupt_Enable */
00083   uint32_t SyncOptions;              /*!< Specifies how the HRTIM instance handles the external synchronization signals
00084                                           This parameter can be a combination of @ref HRTIM_Synchronization_Options */
00085   uint32_t SyncInputSource;          /*!< Specifies the external synchronization input source
00086                                           This parameter can be a value of @ref HRTIM_Synchronization_Input_Source */
00087   uint32_t SyncOutputSource;         /*!< Specifies the source and event to be sent on the external synchronization outputs
00088                                           This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */
00089   uint32_t SyncOutputPolarity;       /*!< Specifies the conditionning of the event to be sent on the external synchronization outputs
00090                                           This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */
00091 } HRTIM_InitTypeDef;
00092
00093 /**
00094   * @brief  HAL State structures definition
00095   */
00096 typedef enum
00097 {
00098   HAL_HRTIM_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */
00099   HAL_HRTIM_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */
00100   HAL_HRTIM_STATE_TIMEOUT    = 0x06U,    /*!< Timeout state                                      */
00101   HAL_HRTIM_STATE_ERROR      = 0x07U,    /*!< Error state                                        */
00102 } HAL_HRTIM_StateTypeDef;
00103
00104 /**
00105   * @brief HRTIM Timer Structure definition
00106   */
00107 typedef struct
00108 {
00109   uint32_t CaptureTrigger1;       /*!< Event(s) triggering capture unit 1.
00110                                        When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
00111                                        When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
00112   uint32_t CaptureTrigger2;       /*!< Event(s) triggering capture unit 2.
00113                                        When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
00114                                        When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
00115   uint32_t InterruptRequests;     /*!< Interrupts requests enabled for the timer. */
00116   uint32_t DMARequests;           /*!< DMA requests enabled for the timer. */
00117   uint32_t DMASrcAddress;          /*!< Address of the source address of the DMA transfer. */
00118   uint32_t DMADstAddress;          /*!< Address of the destination address of the DMA transfer. */
00119   uint32_t DMASize;                /*!< Size of the DMA transfer */
00120 } HRTIM_TimerParamTypeDef;
00121
00122 /**
00123   * @brief  HRTIM Handle Structure definition
00124   */
00125 typedef struct __HRTIM_HandleTypeDef
00126 {
00127   HRTIM_TypeDef *              Instance;                     /*!< Register base address */
00128
00129   HRTIM_InitTypeDef            Init;                         /*!< HRTIM required parameters */
00130
00131   HRTIM_TimerParamTypeDef      TimerParam[MAX_HRTIM_TIMER];  /*!< HRTIM timers - including the master - parameters */
00132
00133   HAL_LockTypeDef              Lock;                         /*!< Locking object          */
00134
00135   __IO HAL_HRTIM_StateTypeDef  State;                        /*!< HRTIM communication state */
00136
00137   DMA_HandleTypeDef *          hdmaMaster;                   /*!< Master timer DMA handle parameters */
00138   DMA_HandleTypeDef *          hdmaTimerA;                   /*!< Timer A DMA handle parameters */
00139   DMA_HandleTypeDef *          hdmaTimerB;                   /*!< Timer B DMA handle parameters */
00140   DMA_HandleTypeDef *          hdmaTimerC;                   /*!< Timer C DMA handle parameters */
00141   DMA_HandleTypeDef *          hdmaTimerD;                   /*!< Timer D DMA handle parameters */
00142   DMA_HandleTypeDef *          hdmaTimerE;                   /*!< Timer E DMA handle parameters */
00143 } HRTIM_HandleTypeDef;
00144
00145 /**
00146   * @brief  Simple output compare mode configuration definition
00147   */
00148 typedef struct {
00149   uint32_t Period;                   /*!< Specifies the timer period
00150                                           The period value must be above 3 periods of the fHRTIM clock.
00151                                           Maximum value is = 0xFFDF */
00152   uint32_t RepetitionCounter;        /*!< Specifies the timer repetition period
00153                                           This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00154   uint32_t PrescalerRatio;           /*!< Specifies the timer clock prescaler ratio.
00155                                           This parameter can be any value of @ref HRTIM_Prescaler_Ratio   */
00156   uint32_t Mode;                     /*!< Specifies the counter operating mode
00157                                           This parameter can be any value of @ref HRTIM_Mode   */
00158 } HRTIM_TimeBaseCfgTypeDef;
00159
00160 /**
00161   * @brief  Simple output compare mode configuration definition
00162   */
00163 typedef struct {
00164   uint32_t Mode;       /*!< Specifies the output compare mode (toggle, active, inactive)
00165                             This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */
00166   uint32_t Pulse;      /*!< Specifies the compare value to be loaded into the Compare Register.
00167                             The compare value must be above or equal to 3 periods of the fHRTIM clock */
00168   uint32_t Polarity;   /*!< Specifies the output polarity
00169                             This parameter can be any value of @ref HRTIM_Output_Polarity */
00170   uint32_t IdleLevel;  /*!< Specifies whether the output level is active or inactive when in IDLE state
00171                             This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
00172 } HRTIM_SimpleOCChannelCfgTypeDef;
00173
00174 /**
00175   * @brief  Simple PWM output mode configuration definition
00176   */
00177 typedef struct {
00178   uint32_t Pulse;            /*!< Specifies the compare value to be loaded into the Compare Register.
00179                                   The compare value must be above or equal to 3 periods of the fHRTIM clock */
00180   uint32_t Polarity;        /*!< Specifies the output polarity
00181                                  This parameter can be any value of @ref HRTIM_Output_Polarity */
00182   uint32_t IdleLevel;       /*!< Specifies whether the output level is active or inactive when in IDLE state
00183                                  This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
00184 } HRTIM_SimplePWMChannelCfgTypeDef;
00185
00186 /**
00187   * @brief  Simple capture mode configuration definition
00188   */
00189 typedef struct {
00190   uint32_t Event;             /*!< Specifies the external event triggering the capture
00191                                    This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
00192   uint32_t EventPolarity;     /*!< Specifies the polarity of the external event (in case of level sensitivity)
00193                                    This parameter can be a value of @ref HRTIM_External_Event_Polarity */
00194   uint32_t EventSensitivity;  /*!< Specifies the sensitivity of the external event
00195                                    This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
00196   uint32_t EventFilter;       /*!< Defines the frequency used to sample the External Event and the length of the digital filter
00197                                    This parameter can be a value of @ref HRTIM_External_Event_Filter */
00198 } HRTIM_SimpleCaptureChannelCfgTypeDef;
00199
00200 /**
00201   * @brief  Simple One Pulse mode configuration definition
00202   */
00203 typedef struct {
00204   uint32_t Pulse;             /*!< Specifies the compare value to be loaded into the Compare Register.
00205                                    The compare value must be above or equal to 3 periods of the fHRTIM clock */
00206   uint32_t OutputPolarity;    /*!< Specifies the output polarity
00207                                    This parameter can be any value of @ref HRTIM_Output_Polarity */
00208   uint32_t OutputIdleLevel;   /*!< Specifies whether the output level is active or inactive when in IDLE state
00209                                    This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
00210   uint32_t Event;             /*!< Specifies the external event triggering the pulse generation
00211                                    This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
00212   uint32_t EventPolarity;     /*!< Specifies the polarity of the external event (in case of level sensitivity)
00213                                    This parameter can be a value of @ref HRTIM_External_Event_Polarity */
00214   uint32_t EventSensitivity;  /*!< Specifies the sensitivity of the external event
00215                                    This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
00216   uint32_t EventFilter;       /*!< Defines the frequency used to sample the External Event and the length of the digital filter
00217                                    This parameter can be a value of @ref HRTIM_External_Event_Filter */
00218 } HRTIM_SimpleOnePulseChannelCfgTypeDef;
00219
00220 /**
00221   * @brief  Timer configuration definition
00222   */
00223 typedef struct {
00224   uint32_t InterruptRequests;      /*!< Relevant for all HRTIM timers, including the master
00225                                        Specifies which interrupts requests must enabled for the timer
00226                                        This parameter can be any combination of  @ref HRTIM_Master_Interrupt_Enable
00227                                        or HRTIM_Timing_Unit_Interrupt_Enable */
00228   uint32_t DMARequests;            /*!< Relevant for all HRTIM timers, including the master
00229                                        Specifies which DMA requests must be enabled for the timer
00230                                        This parameter can be any combination of  @ref HRTIM_Master_DMA_Request_Enable
00231                                        or HRTIM_Timing_Unit_DMA_Request_Enable */
00232   uint32_t DMASrcAddress;          /*!< Relevant for all HRTIM timers, including the master
00233                                        Specifies the address of the source address of the DMA transfer */
00234   uint32_t DMADstAddress;          /*!< Relevant for all HRTIM timers, including the master
00235                                        Specifies the address of the destination address of the DMA transfer */
00236   uint32_t DMASize;                /*!< Relevant for all HRTIM timers, including the master
00237                                        Specifies the size of the DMA transfer */
00238   uint32_t HalfModeEnable;         /*!< Relevant for all HRTIM timers, including the master
00239                                         Specifies whether or not hald mode is enabled
00240                                         This parameter can be any value of @ref HRTIM_Half_Mode_Enable  */
00241   uint32_t StartOnSync;            /*!< Relevant for all HRTIM timers, including the master
00242                                        Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
00243                                         This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event  */
00244   uint32_t ResetOnSync;            /*!< Relevant for all HRTIM timers, including the master
00245                                         Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
00246                                         This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event  */
00247   uint32_t DACSynchro;             /*!< Relevant for all HRTIM timers, including the master
00248                                         Indicates whether or not the a DAC synchronization event is generated
00249                                         This parameter can be any value of @ref HRTIM_DAC_Synchronization   */
00250   uint32_t PreloadEnable;          /*!< Relevant for all HRTIM timers, including the master
00251                                         Specifies whether or not register preload is enabled
00252                                         This parameter can be any value of @ref HRTIM_Register_Preload_Enable  */
00253   uint32_t UpdateGating;           /*!< Relevant for all HRTIM timers, including the master
00254                                         Specifies how the update occurs with respect to a burst DMA transaction or
00255                                         update enable inputs (Slave timers only)
00256                                         This parameter can be any value of @ref HRTIM_Update_Gating   */
00257   uint32_t BurstMode;              /*!< Relevant for all HRTIM timers, including the master
00258                                         Specifies how the timer behaves during a burst mode operation
00259                                         This parameter can be any value of @ref HRTIM_Timer_Burst_Mode  */
00260   uint32_t RepetitionUpdate;       /*!< Relevant for all HRTIM timers, including the master
00261                                         Specifies whether or not registers update is triggered by the repetition event
00262                                         This parameter can be any valuen of @ref HRTIM_Timer_Repetition_Update */
00263   uint32_t PushPull;               /*!< Relevant for Timer A to Timer E
00264                                         Specifies whether or not the push-pull mode is enabled
00265                                         This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */
00266   uint32_t FaultEnable;            /*!< Relevant for Timer A to Timer E
00267                                         Specifies which fault channels are enabled for the timer
00268                                         This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling  */
00269   uint32_t FaultLock;              /*!< Relevant for Timer A to Timer E
00270                                         Specifies whether or not fault enabling status is write protected
00271                                         This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */
00272   uint32_t DeadTimeInsertion;      /*!< Relevant for Timer A to Timer E
00273                                         Specifies whether or not deadtime insertion is enabled for the timer
00274                                         This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */
00275   uint32_t DelayedProtectionMode;  /*!< Relevant for Timer A to Timer E
00276                                         Specifies the delayed protection mode
00277                                         This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */
00278   uint32_t UpdateTrigger;          /*!< Relevant for Timer A to Timer E
00279                                         Specifies source(s) triggering the timer registers update
00280                                         This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */
00281   uint32_t ResetTrigger;           /*!< Relevant for Timer A to Timer E
00282                                         Specifies source(s) triggering the timer counter reset
00283                                         This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */
00284   uint32_t ResetUpdate;           /*!<  Relevant for Timer A to Timer E
00285                                         Specifies whether or not registers update is triggered when the timer counter is reset
00286                                         This parameter can be a value of @ref HRTIM_Timer_Reset_Update */
00287 } HRTIM_TimerCfgTypeDef;
00288
00289 /**
00290   * @brief  Compare unit configuration definition
00291   */
00292 typedef struct {
00293   uint32_t CompareValue;         /*!< Specifies the compare value of the timer compare unit
00294                                       the minimum value must be greater than or equal to 3 periods of the fHRTIM clock
00295                                       the maximum value must be less than or equal to 0xFFFF - 1 periods of the fHRTIM clock */
00296   uint32_t AutoDelayedMode;      /*!< Specifies the auto delayed mode for compare unit 2 or 4
00297                                       This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */
00298   uint32_t AutoDelayedTimeout;   /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected
00299                                       CompareValue +  AutoDelayedTimeout must be less than 0xFFFF */
00300 } HRTIM_CompareCfgTypeDef;
00301
00302 /**
00303   * @brief  Capture unit configuration definition
00304   */
00305 typedef struct {
00306   uint32_t Trigger;   /*!< Specifies source(s) triggering the capture
00307                            This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */
00308 } HRTIM_CaptureCfgTypeDef;
00309
00310 /**
00311   * @brief  Output configuration definition
00312   */
00313 typedef struct {
00314   uint32_t Polarity;              /*!< Specifies the output polarity.
00315                                        This parameter can be any value of @ref HRTIM_Output_Polarity */
00316   uint32_t SetSource;             /*!< Specifies the event(s) transitioning the output from its inactive level to its active level.
00317                                        This parameter can be a combination of @ref HRTIM_Output_Set_Source */
00318   uint32_t ResetSource;           /*!< Specifies the event(s) transitioning the output from its active level to its inactive level.
00319                                        This parameter can be a combination of @ref HRTIM_Output_Reset_Source */
00320   uint32_t IdleMode;              /*!< Specifies whether or not the output is affected by a burst mode operation.
00321                                        This parameter can be any value of @ref HRTIM_Output_Idle_Mode */
00322   uint32_t IdleLevel;             /*!< Specifies whether the output level is active or inactive when in IDLE state.
00323                                        This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
00324   uint32_t FaultLevel;            /*!< Specifies whether the output level is active or inactive when in FAULT state.
00325                                        This parameter can be any value of @ref HRTIM_Output_FAULT_Level */
00326   uint32_t ChopperModeEnable;     /*!< Indicates whether or not the chopper mode is enabled.
00327                                        This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */
00328   uint32_t BurstModeEntryDelayed;  /* !<Indicates whether or not deadtime is inserted when entering the IDLE state during a burst mode operation.
00329                                         This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */
00330 } HRTIM_OutputCfgTypeDef;
00331
00332 /**
00333   * @brief  External event filtering in timing units configuration definition
00334   */
00335 typedef struct {
00336   uint32_t Filter;       /*!< Specifies the type of event filtering within the timing unit
00337                              This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */
00338   uint32_t Latch;       /*!< Specifies whether or not the signal is latched
00339                              This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */
00340 } HRTIM_TimerEventFilteringCfgTypeDef;
00341
00342 /**
00343   * @brief  Dead time feature configuration definition
00344   */
00345 typedef struct {
00346   uint32_t Prescaler;        /*!< Specifies the Deadtime Prescaler
00347                                   This parameter can be a value of @ref  HRTIM_Deadtime_Prescaler_Ratio */
00348   uint32_t RisingValue;      /*!< Specifies the Deadtime following a rising edge
00349                                   This parameter can be a number between 0x0 and 0x1FF */
00350   uint32_t RisingSign;       /*!< Specifies whether the deadtime is positive or negative on rising edge
00351                                   This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */
00352   uint32_t RisingLock;       /*!< Specifies whether or not deadtime rising settings (value and sign) are write protected
00353                                   This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */
00354   uint32_t RisingSignLock;   /*!< Specifies whether or not deadtime rising sign is write protected
00355                                   This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */
00356   uint32_t FallingValue;     /*!< Specifies the Deadtime following a falling edge
00357                                  This parameter can be a number between 0x0 and 0x1FF */
00358   uint32_t FallingSign;      /*!< Specifies whether the deadtime is positive or negative on falling edge
00359                                  This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */
00360   uint32_t FallingLock;      /*!< Specifies whether or not deadtime falling settings (value and sign) are write protected
00361                                  This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */
00362   uint32_t FallingSignLock;  /*!< Specifies whether or not deadtime falling sign is write protected
00363                                  This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */
00364 } HRTIM_DeadTimeCfgTypeDef ;
00365
00366 /**
00367   * @brief  Chopper mode configuration definition
00368   */
00369 typedef struct {
00370   uint32_t CarrierFreq;  /*!< Specifies the Timer carrier frequency value.
00371                               This parameter can be a value of @ref HRTIM_Chopper_Frequency */
00372   uint32_t DutyCycle;   /*!< Specifies the Timer chopper duty cycle value.
00373                              This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */
00374   uint32_t StartPulse;  /*!< Specifies the Timer pulse width value.
00375                              This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */
00376 } HRTIM_ChopperModeCfgTypeDef;
00377
00378 /**
00379   * @brief  External event channel configuration definition
00380   */
00381 typedef struct {
00382   uint32_t Source;        /*!< Identifies the source of the external event
00383                                 This parameter can be a value of @ref HRTIM_External_Event_Sources */
00384   uint32_t Polarity;      /*!< Specifies the polarity of the external event (in case of level sensitivity)
00385                                This parameter can be a value of @ref HRTIM_External_Event_Polarity */
00386   uint32_t Sensitivity;   /*!< Specifies the sensitivity of the external event
00387                                This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
00388   uint32_t Filter;        /*!< Defines the frequency used to sample the External Event and the length of the digital filter
00389                                This parameter can be a value of @ref HRTIM_External_Event_Filter */
00390   uint32_t FastMode;     /*!< Indicates whether or not low latency mode is enabled for the external event
00391                               This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */
00392 } HRTIM_EventCfgTypeDef;
00393
00394 /**
00395   * @brief  Fault channel configuration definition
00396   */
00397 typedef struct {
00398   uint32_t Source;        /*!< Identifies the source of the fault
00399                                 This parameter can be a value of @ref HRTIM_Fault_Sources */
00400   uint32_t Polarity;      /*!< Specifies the polarity of the fault event
00401                                This parameter can be a value of @ref HRTIM_Fault_Polarity */
00402   uint32_t Filter;        /*!< Defines the frequency used to sample the Fault input and the length of the digital filter
00403                                This parameter can be a value of @ref HRTIM_Fault_Filter */
00404   uint32_t Lock;          /*!< Indicates whether or not fault programming bits are write protected
00405                               This parameter can be a value of @ref HRTIM_Fault_Lock */
00406 } HRTIM_FaultCfgTypeDef;
00407
00408 /**
00409   * @brief  Burst mode configuration definition
00410   */
00411 typedef struct {
00412   uint32_t Mode;           /*!< Specifies the burst mode operating mode
00413                                 This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */
00414   uint32_t ClockSource;    /*!< Specifies the burst mode clock source
00415                                 This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */
00416   uint32_t Prescaler;      /*!< Specifies the burst mode prescaler
00417                                 This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */
00418   uint32_t PreloadEnable;  /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER)
00419                                 This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable  */
00420   uint32_t Trigger;        /*!< Specifies the event(s) trigering the burst operation
00421                                 This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger  */
00422   uint32_t IdleDuration;   /*!< Specifies number of periods during which the selected timers are in idle state
00423                                 This parameter can be a number between 0x0 and 0xFFFF  */
00424   uint32_t Period;        /*!< Specifies burst mode repetition period
00425                                 This parameter can be a number between 0x1 and 0xFFFF  */
00426 } HRTIM_BurstModeCfgTypeDef;
00427
00428 /**
00429   * @brief  ADC trigger configuration definition
00430   */
00431 typedef struct {
00432   uint32_t UpdateSource;  /*!< Specifies the ADC trigger update source
00433                                This parameter can be a combination of @ref HRTIM_ADC_Trigger_Update_Source  */
00434   uint32_t Trigger;      /*!< Specifies the event(s) triggering the ADC conversion
00435                               This parameter can be a value of @ref HRTIM_ADC_Trigger_Event  */
00436 } HRTIM_ADCTriggerCfgTypeDef;
00437
00438 /**
00439   * @}
00440   */
00441
00442 /* Exported constants --------------------------------------------------------*/
00443 /** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants
00444   * @{
00445   */
00446
00447 /** @defgroup HRTIM_Timer_Index HRTIM Timer Index
00448   * @{
00449   * @brief Constants defining the timer indexes
00450   */
00451 #define HRTIM_TIMERINDEX_TIMER_A (uint32_t)0x0U   /*!< Index used to access timer A registers */
00452 #define HRTIM_TIMERINDEX_TIMER_B (uint32_t)0x1U   /*!< Index used to access timer B registers */
00453 #define HRTIM_TIMERINDEX_TIMER_C (uint32_t)0x2U   /*!< Index used to access timer C registers */
00454 #define HRTIM_TIMERINDEX_TIMER_D (uint32_t)0x3U   /*!< Index used to access timer D registers */
00455 #define HRTIM_TIMERINDEX_TIMER_E (uint32_t)0x4U   /*!< Index used to access timer E registers */
00456 #define HRTIM_TIMERINDEX_MASTER  (uint32_t)0x5U   /*!< Index used to access master registers */
00457 #define HRTIM_TIMERINDEX_COMMON  (uint32_t)0xFFU  /*!< Index used to access HRTIM common registers */
00458
00459 /**
00460   * @}
00461   */
00462
00463 /** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier
00464   * @{
00465   * @brief Constants defining timer identifiers
00466   */
00467 #define HRTIM_TIMERID_MASTER  (HRTIM_MCR_MCEN)   /*!< Master identifier*/
00468 #define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN)  /*!< Timer A identifier */
00469 #define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN)  /*!< Timer B identifier */
00470 #define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN)  /*!< Timer C identifier */
00471 #define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN)  /*!< Timer D identifier */
00472 #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN)  /*!< Timer E identifier */
00473
00474 #define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U)
00475
00476 /**
00477  * @}
00478  */
00479
00480 /** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit
00481   * @{
00482   * @brief Constants defining compare unit identifiers
00483   */
00484 #define HRTIM_COMPAREUNIT_1 (uint32_t)0x00000001U  /*!< Compare unit 1 identifier. */
00485 #define HRTIM_COMPAREUNIT_2 (uint32_t)0x00000002U  /*!< Compare unit 2 identifier. */
00486 #define HRTIM_COMPAREUNIT_3 (uint32_t)0x00000004U  /*!< Compare unit 3 identifier. */
00487 #define HRTIM_COMPAREUNIT_4 (uint32_t)0x00000008U  /*!< Compare unit 4 identifier. */
00488
00489  /**
00490   * @}
00491   */
00492
00493 /** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit
00494   * @{
00495   * @brief Constants defining capture unit identifiers
00496   */
00497 #define HRTIM_CAPTUREUNIT_1 (uint32_t)0x00000001U  /*!< Capture unit 1 identifier. */
00498 #define HRTIM_CAPTUREUNIT_2 (uint32_t)0x00000002U  /*!< Capture unit 2 identifier. */
00499
00500 /**
00501   * @}
00502   */
00503
00504 /** @defgroup HRTIM_Timer_Output HRTIM Timer Output
00505   * @{
00506   * @brief Constants defining timer output identifiers
00507   */
00508 #define HRTIM_OUTPUT_TA1  (uint32_t)0x00000001U  /*!< Timer A - Ouput 1 identifier. */
00509 #define HRTIM_OUTPUT_TA2  (uint32_t)0x00000002U  /*!< Timer A - Ouput 2 identifier. */
00510 #define HRTIM_OUTPUT_TB1  (uint32_t)0x00000004U  /*!< Timer B - Ouput 1 identifier. */
00511 #define HRTIM_OUTPUT_TB2  (uint32_t)0x00000008U  /*!< Timer B - Ouput 2 identifier. */
00512 #define HRTIM_OUTPUT_TC1  (uint32_t)0x00000010U  /*!< Timer C - Ouput 1 identifier. */
00513 #define HRTIM_OUTPUT_TC2  (uint32_t)0x00000020U  /*!< Timer C - Ouput 2 identifier. */
00514 #define HRTIM_OUTPUT_TD1  (uint32_t)0x00000040U  /*!< Timer D - Ouput 1 identifier. */
00515 #define HRTIM_OUTPUT_TD2  (uint32_t)0x00000080U  /*!< Timer D - Ouput 2 identifier. */
00516 #define HRTIM_OUTPUT_TE1  (uint32_t)0x00000100U  /*!< Timer E - Ouput 1 identifier. */
00517 #define HRTIM_OUTPUT_TE2  (uint32_t)0x00000200U  /*!< Timer E - Ouput 2 identifier. */
00518
00519 /**
00520   * @}
00521   */
00522
00523 /** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger
00524   * @{
00525   * @brief Constants defining ADC triggers identifiers
00526   */
00527 #define HRTIM_ADCTRIGGER_1  (uint32_t)0x00000001U  /*!< ADC trigger 1 identifier. */
00528 #define HRTIM_ADCTRIGGER_2  (uint32_t)0x00000002U  /*!< ADC trigger 2 identifier. */
00529 #define HRTIM_ADCTRIGGER_3  (uint32_t)0x00000004U  /*!< ADC trigger 3 identifier. */
00530 #define HRTIM_ADCTRIGGER_4  (uint32_t)0x00000008U  /*!< ADC trigger 4 identifier. */
00531
00532 /**
00533   * @}
00534   */
00535
00536 /** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels
00537   * @{
00538   * @brief Constants defining external event channel identifiers
00539   */
00540 #define HRTIM_EVENT_NONE     ((uint32_t)0x00000000U)     /*!< Undefined event channel. */
00541 #define HRTIM_EVENT_1        ((uint32_t)0x00000001U)     /*!< External event channel 1 identifier. */
00542 #define HRTIM_EVENT_2        ((uint32_t)0x00000002U)     /*!< External event channel 2 identifier. */
00543 #define HRTIM_EVENT_3        ((uint32_t)0x00000004U)     /*!< External event channel 3 identifier. */
00544 #define HRTIM_EVENT_4        ((uint32_t)0x00000008U)     /*!< External event channel 4 identifier. */
00545 #define HRTIM_EVENT_5        ((uint32_t)0x00000010U)     /*!< External event channel 5 identifier. */
00546 #define HRTIM_EVENT_6        ((uint32_t)0x00000020U)     /*!< External event channel 6 identifier. */
00547 #define HRTIM_EVENT_7        ((uint32_t)0x00000040U)     /*!< External event channel 7 identifier. */
00548 #define HRTIM_EVENT_8        ((uint32_t)0x00000080U)     /*!< External event channel 8 identifier. */
00549 #define HRTIM_EVENT_9        ((uint32_t)0x00000100U)     /*!< External event channel 9 identifier. */
00550 #define HRTIM_EVENT_10       ((uint32_t)0x00000200U)     /*!< External event channel 10 identifier. */
00551
00552 /**
00553   * @}
00554   */
00555
00556 /** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel
00557   * @{
00558   * @brief Constants defining fault channel identifiers
00559   */
00560 #define HRTIM_FAULT_1      ((uint32_t)0x01U)     /*!< Fault channel 1 identifier. */
00561 #define HRTIM_FAULT_2      ((uint32_t)0x02U)     /*!< Fault channel 2 identifier. */
00562 #define HRTIM_FAULT_3      ((uint32_t)0x04U)     /*!< Fault channel 3 identifier. */
00563 #define HRTIM_FAULT_4      ((uint32_t)0x08U)     /*!< Fault channel 4 identifier. */
00564 #define HRTIM_FAULT_5      ((uint32_t)0x10U)     /*!< Fault channel 5 identifier. */
00565
00566 /**
00567   * @}
00568   */
00569
00570
00571  /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio
00572   * @{
00573   * @brief Constants defining timer high-resolution clock prescaler ratio.
00574   */
00575 #define HRTIM_PRESCALERRATIO_MUL32    ((uint32_t)0x00000000U)  /*!< fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz). */
00576 #define HRTIM_PRESCALERRATIO_MUL16    ((uint32_t)0x00000001U)  /*!< fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz). */
00577 #define HRTIM_PRESCALERRATIO_MUL8     ((uint32_t)0x00000002U)  /*!< fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz). */
00578 #define HRTIM_PRESCALERRATIO_MUL4     ((uint32_t)0x00000003U)  /*!< fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz). */
00579 #define HRTIM_PRESCALERRATIO_MUL2     ((uint32_t)0x00000004U)  /*!< fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz). */
00580 #define HRTIM_PRESCALERRATIO_DIV1     ((uint32_t)0x00000005U)  /*!< fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz). */
00581 #define HRTIM_PRESCALERRATIO_DIV2     ((uint32_t)0x00000006U)  /*!< fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz). */
00582 #define HRTIM_PRESCALERRATIO_DIV4     ((uint32_t)0x00000007U)  /*!< fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz). */
00583
00584 /**
00585   * @}
00586   */
00587
00588 /** @defgroup HRTIM_Mode HRTIM Mode
00589   * @{
00590   * @brief Constants defining timer counter operating mode.
00591   */
00592 #define HRTIM_MODE_CONTINUOUS                ((uint32_t)0x00000008U)  /*!< The timer operates in continuous (free-running) mode. */
00593 #define HRTIM_MODE_SINGLESHOT               ((uint32_t)0x00000000U)  /*!< The timer operates in non retriggerable single-shot mode. */
00594 #define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE ((uint32_t)0x00000010U)  /*!< The timer operates in retriggerable single-shot mode. */
00595
00596 /**
00597   * @}
00598   */
00599
00600 /** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable
00601   * @{
00602   * @brief Constants defining half mode enabling status.
00603   */
00604 #define HRTIM_HALFMODE_DISABLED ((uint32_t)0x00000000U)  /*!< Half mode is disabled. */
00605 #define HRTIM_HALFMODE_ENABLED  ((uint32_t)0x00000020U)  /*!< Half mode is enabled. */
00606
00607 /**
00608   * @}
00609   */
00610
00611 /** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event
00612   * @{
00613   * @brief Constants defining the timer behavior following the synchronization event
00614   */
00615 #define HRTIM_SYNCSTART_DISABLED ((uint32_t)0x00000000U)  /*!< Synchronization input event has effect on the timer. */
00616 #define HRTIM_SYNCSTART_ENABLED  (HRTIM_MCR_SYNCSTRTM)   /*!< Synchronization input event starts the timer. */
00617
00618 /**
00619   * @}
00620   */
00621
00622 /** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event
00623   * @{
00624   * @brief Constants defining the timer behavior following the synchronization event
00625   */
00626 #define HRTIM_SYNCRESET_DISABLED ((uint32_t)0x00000000U)  /*!< Synchronization input event has effect on the timer. */
00627 #define HRTIM_SYNCRESET_ENABLED  (HRTIM_MCR_SYNCRSTM)    /*!< Synchronization input event resets the timer. */
00628
00629 /**
00630   * @}
00631   */
00632
00633 /** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization
00634   * @{
00635   * @brief Constants defining on which output the DAC synchronization event is sent
00636   */
00637 #define HRTIM_DACSYNC_NONE          ((uint32_t)0x00000000U)                     /*!< No DAC synchronization event generated. */
00638 #define HRTIM_DACSYNC_DACTRIGOUT_1  (HRTIM_MCR_DACSYNC_0)                       /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update. */
00639 #define HRTIM_DACSYNC_DACTRIGOUT_2  (HRTIM_MCR_DACSYNC_1)                       /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update. */
00640 #define HRTIM_DACSYNC_DACTRIGOUT_3  (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update. */
00641
00642 /**
00643   * @}
00644   */
00645
00646 /** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable
00647   * @{
00648   * @brief Constants defining whether a write access into a preloadable
00649   *        register is done into the active or the preload register.
00650   */
00651 #define HRTIM_PRELOAD_DISABLED  0x00000000U  /*!< Preload disabled: the write access is directly done into the active register. */
00652 #define HRTIM_PRELOAD_ENABLED  (HRTIM_MCR_PREEN)       /*!< Preload enabled: the write access is done into the preload register. */
00653
00654 /**
00655   * @}
00656   */
00657
00658 /** @defgroup HRTIM_Update_Gating HRTIM Update Gating
00659   * @{
00660   * @brief Constants defining how the update occurs relatively to the burst DMA
00661   *        transaction and the external update request on update enable inputs 1 to 3.
00662   */
00663 #define HRTIM_UPDATEGATING_INDEPENDENT     ((uint32_t)0x00000000U)                                                /*!< Update done independently from the DMA burst transfer completion. */
00664 #define HRTIM_UPDATEGATING_DMABURST        (HRTIM_TIMCR_UPDGAT_0)                                                /*!< Update done when the DMA burst transfer is completed. */
00665 #define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1)                                                /*!< Update done on timer roll-over following a DMA burst transfer completion. */
00666 #define HRTIM_UPDATEGATING_UPDEN1          (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1. */
00667 #define HRTIM_UPDATEGATING_UPDEN2          (HRTIM_TIMCR_UPDGAT_2)                                                /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2. */
00668 #define HRTIM_UPDATEGATING_UPDEN3          (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3. */
00669 #define HRTIM_UPDATEGATING_UPDEN1_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1)                         /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 1. */
00670 #define HRTIM_UPDATEGATING_UPDEN2_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)  /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 2. */
00671 #define HRTIM_UPDATEGATING_UPDEN3_UPDATE   (HRTIM_TIMCR_UPDGAT_3)                                                /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 3. */
00672
00673 /**
00674   * @}
00675   */
00676
00677 /** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode
00678   * @{
00679   * @brief Constants defining how the timer behaves during a burst
00680             mode operation.
00681   */
00682 #define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK ((uint32_t)0x000000U) /*!< Timer counter clock is maintained and the timer operates normally. */
00683 #define HRTIM_TIMERBURSTMODE_RESETCOUNTER  (HRTIM_BMCR_MTBM)     /*!< Timer counter clock is stopped and the counter is reset. */
00684
00685 /**
00686   * @}
00687   */
00688
00689 /** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update
00690   * @{
00691   * @brief Constants defining whether registers are updated when the timer
00692   *        repetition period is completed (either due to roll-over or
00693   *        reset events)
00694   */
00695 #define HRTIM_UPDATEONREPETITION_DISABLED ((uint32_t)0x00000000U) /*!< Update on repetition disabled. */
00696 #define HRTIM_UPDATEONREPETITION_ENABLED  (HRTIM_MCR_MREPU)      /*!< Update on repetition enabled. */
00697
00698 /**
00699   * @}
00700   */
00701
00702
00703 /** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode
00704   * @{
00705   * @brief Constants defining whether or not the puhs-pull mode is enabled for
00706   *        a timer.
00707   */
00708 #define HRTIM_TIMPUSHPULLMODE_DISABLED   ((uint32_t)0x00000000U)          /*!< Push-Pull mode disabled. */
00709 #define HRTIM_TIMPUSHPULLMODE_ENABLED    ((uint32_t)HRTIM_TIMCR_PSHPLL)   /*!< Push-Pull mode enabled. */
00710
00711 /**
00712   * @}
00713   */
00714
00715 /** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling
00716   * @{
00717   * @brief Constants defining whether a faut channel is enabled for a timer
00718   */
00719 #define HRTIM_TIMFAULTENABLE_NONE     ((uint32_t)0x00000000U)  /*!< No fault enabled. */
00720 #define HRTIM_TIMFAULTENABLE_FAULT1   (HRTIM_FLTR_FLT1EN)      /*!< Fault 1 enabled. */
00721 #define HRTIM_TIMFAULTENABLE_FAULT2   (HRTIM_FLTR_FLT2EN)      /*!< Fault 2 enabled. */
00722 #define HRTIM_TIMFAULTENABLE_FAULT3   (HRTIM_FLTR_FLT3EN)      /*!< Fault 3 enabled. */
00723 #define HRTIM_TIMFAULTENABLE_FAULT4   (HRTIM_FLTR_FLT4EN)      /*!< Fault 4 enabled. */
00724 #define HRTIM_TIMFAULTENABLE_FAULT5   (HRTIM_FLTR_FLT5EN)      /*!< Fault 5 enabled. */
00725
00726 /**
00727   * @}
00728   */
00729
00730 /** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock
00731   * @{
00732   * @brief Constants defining whether or not fault enabling bits are write
00733   *        protected for a timer
00734   */
00735 #define HRTIM_TIMFAULTLOCK_READWRITE ((uint32_t)0x00000000U)  /*!< Timer fault enabling bits are read/write. */
00736 #define HRTIM_TIMFAULTLOCK_READONLY  (HRTIM_FLTR_FLTLCK)      /*!< Timer fault enabling bits are read only. */
00737
00738 /**
00739   * @}
00740   */
00741
00742 /** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Deadtime Insertion
00743   * @{
00744   * @brief Constants defining whether or not fault the dead time insertion
00745   *        feature is enabled for a timer
00746   */
00747 #define HRTIM_TIMDEADTIMEINSERTION_DISABLED   ((uint32_t)0x00000000U)  /*!< Output 1 and output 2 signals are independent. */
00748 #define HRTIM_TIMDEADTIMEINSERTION_ENABLED    HRTIM_OUTR_DTEN          /*!< Deadtime is inserted between output 1 and output 2. */
00749
00750 /**
00751   * @}
00752   */
00753
00754 /** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode
00755   * @{
00756   * @brief Constants defining all possible delayed protection modes
00757   *        for a timer. Also definethe source and outputs on which the delayed
00758   *        protection schemes are applied
00759   */
00760 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED          ((uint32_t)0x00000000U)                                                                 /*!< No action. */
00761 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6  (HRTIM_OUTR_DLYPRTEN)                                                                   /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6. */
00762 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6  (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                                             /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6. */
00763 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6  (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                                             /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6. */
00764 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6     (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                       /*!< Timers A, B, C: Balanced Idle on external Event 6. */
00765 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)                                             /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7. */
00766 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                       /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7. */
00767 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                       /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7. */
00768 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7     (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 7. */
00769
00770 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED          ((uint32_t)0x00000000U)                                                                   /*!< No action. */
00771 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8  (HRTIM_OUTR_DLYPRTEN)                                                                     /*!< Timers D, E: Output 1 delayed Idle on external Event 6. */
00772 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8  (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers D, E: Output 2 delayed Idle on external Event 6. */
00773 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8  (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6. */
00774 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8     (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers D, E: Balanced Idle on external Event 6. */
00775 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers D, E: Output 1 delayed Idle on external Event 7. */
00776 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers D, E: Output 2 delayed Idle on external Event 7. */
00777 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7. */
00778 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9     (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)   /*!< Timers D, E: Balanced Idle on external Event 7. */
00779
00780 /**
00781   * @}
00782   */
00783
00784 /** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger
00785   * @{
00786   * @brief Constants defining whether the registers update is done synchronously
00787   *        with any other timer or master update
00788   */
00789 #define HRTIM_TIMUPDATETRIGGER_NONE     ((uint32_t)0x00000000U) /*!< Register update is disabled. */
00790 #define HRTIM_TIMUPDATETRIGGER_MASTER   (HRTIM_TIMCR_MSTU)      /*!< Register update is triggered by the master timer update. */
00791 #define HRTIM_TIMUPDATETRIGGER_TIMER_A  (HRTIM_TIMCR_TAU)       /*!< Register update is triggered by the timer A update. */
00792 #define HRTIM_TIMUPDATETRIGGER_TIMER_B  (HRTIM_TIMCR_TBU)       /*!< Register update is triggered by the timer B update. */
00793 #define HRTIM_TIMUPDATETRIGGER_TIMER_C  (HRTIM_TIMCR_TCU)       /*!< Register update is triggered by the timer C update. */
00794 #define HRTIM_TIMUPDATETRIGGER_TIMER_D  (HRTIM_TIMCR_TDU)       /*!< Register update is triggered by the timer D update. */
00795 #define HRTIM_TIMUPDATETRIGGER_TIMER_E  (HRTIM_TIMCR_TEU)       /*!< Register update is triggered by the timer E update. */
00796
00797 /**
00798   * @}
00799   */
00800
00801 /** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger
00802   * @{
00803   * @brief Constants defining the events that can be selected to trigger the reset
00804   *        of the timer counter
00805   */
00806 #define HRTIM_TIMRESETTRIGGER_NONE        ((uint32_t)0x00000000U)/*!< No counter reset trigger. */
00807 #define HRTIM_TIMRESETTRIGGER_UPDATE      (HRTIM_RSTR_UPDATE)    /*!< The timer counter is reset upon update event. */
00808 #define HRTIM_TIMRESETTRIGGER_CMP2        (HRTIM_RSTR_CMP2)      /*!< The timer counter is reset upon Timer Compare 2 event. */
00809 #define HRTIM_TIMRESETTRIGGER_CMP4        (HRTIM_RSTR_CMP4)      /*!< The timer counter is reset upon Timer Compare 4 event. */
00810 #define HRTIM_TIMRESETTRIGGER_MASTER_PER  (HRTIM_RSTR_MSTPER)    /*!< The timercounter is reset upon master timer period event. */
00811 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1)   /*!< The timer counter is reset upon master timer Compare 1 event. */
00812 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2)   /*!< The timer counter is reset upon master timer Compare 2 event. */
00813 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3)   /*!< The timer counter is reset upon master timer Compare 3 event. */
00814 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4)   /*!< The timer counter is reset upon master timer Compare 4 event. */
00815 #define HRTIM_TIMRESETTRIGGER_EEV_1       (HRTIM_RSTR_EXTEVNT1)  /*!< The timer counter is reset upon external event 1. */
00816 #define HRTIM_TIMRESETTRIGGER_EEV_2       (HRTIM_RSTR_EXTEVNT2)  /*!< The timer counter is reset upon external event 2. */
00817 #define HRTIM_TIMRESETTRIGGER_EEV_3       (HRTIM_RSTR_EXTEVNT3)  /*!< The timer counter is reset upon external event 3. */
00818 #define HRTIM_TIMRESETTRIGGER_EEV_4       (HRTIM_RSTR_EXTEVNT4)  /*!< The timer counter is reset upon external event 4. */
00819 #define HRTIM_TIMRESETTRIGGER_EEV_5       (HRTIM_RSTR_EXTEVNT5)  /*!< The timer counter is reset upon external event 5. */
00820 #define HRTIM_TIMRESETTRIGGER_EEV_6       (HRTIM_RSTR_EXTEVNT6)  /*!< The timer counter is reset upon external event 6. */
00821 #define HRTIM_TIMRESETTRIGGER_EEV_7       (HRTIM_RSTR_EXTEVNT7)  /*!< The timer counter is reset upon external event 7. */
00822 #define HRTIM_TIMRESETTRIGGER_EEV_8       (HRTIM_RSTR_EXTEVNT8)  /*!< The timer counter is reset upon external event 8. */
00823 #define HRTIM_TIMRESETTRIGGER_EEV_9       (HRTIM_RSTR_EXTEVNT9)  /*!< The timer counter is reset upon external event 9. */
00824 #define HRTIM_TIMRESETTRIGGER_EEV_10      (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10. */
00825 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event. */
00826 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event. */
00827 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4)  /*!< The timer counter is reset upon other timer Compare 4 event. */
00828 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event. */
00829 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event. */
00830 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4)  /*!< The timer counter is reset upon other timer Compare 4 event. */
00831 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event. */
00832 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event. */
00833 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4)  /*!< The timer counter is reset upon other timer Compare 4 event. */
00834 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1)  /*!< The timer counter is reset upon other timer Compare 1 event. */
00835 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2)  /*!< The timer counter is reset upon other timer Compare 2 event. */
00836 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4)  /*!< The timer counter is reset upon other timer Compare 4 event. */
00837
00838 /**
00839   * @}
00840   */
00841
00842 /** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update
00843   * @{
00844   * @brief Constants defining whether the register are updated upon Timerx
00845   *        counter reset or roll-over to 0 after reaching the period value
00846   *        in continuous mode
00847   */
00848 #define HRTIM_TIMUPDATEONRESET_DISABLED ((uint32_t)0x00000000U)  /*!< Update by timer x reset / roll-over disabled. */
00849 #define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU)    /*!< Update by timer x reset / roll-over enabled. */
00850
00851 /**
00852   * @}
00853   */
00854
00855 /** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode
00856   * @{
00857   * @brief Constants defining whether the compare register is behaving in
00858   *        regular mode (compare match issued as soon as counter equal compare),
00859   *        or in auto-delayed mode
00860   */
00861 #define HRTIM_AUTODELAYEDMODE_REGULAR                 ((uint32_t)0x00000000U)                         /*!< standard compare mode. */
00862 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT   (HRTIM_TIMCR_DELCMP2_0)                         /*!< Compare event generated only if a capture has occurred. */
00863 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1)                         /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing). */
00864 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing). */
00865
00866 /**
00867   * @}
00868   */
00869
00870 /** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode
00871   * @{
00872   * @brief Constants defining the behavior of the output signal when the timer
00873            operates in basic output compare mode
00874   */
00875 #define HRTIM_BASICOCMODE_TOGGLE    (0x00000001U)  /*!< Output toggles when the timer counter reaches the compare value. */
00876 #define HRTIM_BASICOCMODE_INACTIVE  (0x00000002U)  /*!< Output forced to active level when the timer counter reaches the compare value. */
00877 #define HRTIM_BASICOCMODE_ACTIVE    (0x00000003U)  /*!< Output forced to inactive level when the timer counter reaches the compare value. */
00878
00879 /**
00880   * @}
00881   */
00882
00883 /** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity
00884   * @{
00885   * @brief Constants defining the polarity of a timer output
00886   */
00887 #define HRTIM_OUTPUTPOLARITY_HIGH    ((uint32_t)0x00000000U)  /*!< Output is acitve HIGH. */
00888 #define HRTIM_OUTPUTPOLARITY_LOW     (HRTIM_OUTR_POL1)        /*!< Output is active LOW. */
00889
00890 /**
00891   * @}
00892   */
00893
00894 /** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source
00895   * @{
00896   * @brief Constants defining the events that can be selected to configure the
00897   *        set crossbar of a timer output
00898   */
00899 #define HRTIM_OUTPUTSET_NONE       ((uint32_t)0x00000000U) /*!< Reset the output set crossbar. */
00900 #define HRTIM_OUTPUTSET_RESYNC     (HRTIM_SET1R_RESYNC)    /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state. */
00901 #define HRTIM_OUTPUTSET_TIMPER     (HRTIM_SET1R_PER)       /*!< Timer period event forces the output to its active state. */
00902 #define HRTIM_OUTPUTSET_TIMCMP1    (HRTIM_SET1R_CMP1)      /*!< Timer compare 1 event forces the output to its active state. */
00903 #define HRTIM_OUTPUTSET_TIMCMP2    (HRTIM_SET1R_CMP2)      /*!< Timer compare 2 event forces the output to its active state. */
00904 #define HRTIM_OUTPUTSET_TIMCMP3    (HRTIM_SET1R_CMP3)      /*!< Timer compare 3 event forces the output to its active state. */
00905 #define HRTIM_OUTPUTSET_TIMCMP4    (HRTIM_SET1R_CMP4)      /*!< Timer compare 4 event forces the output to its active state. */
00906 #define HRTIM_OUTPUTSET_MASTERPER  (HRTIM_SET1R_MSTPER)    /*!< The master timer period event forces the output to its active state. */
00907 #define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1)   /*!< Master Timer compare 1 event forces the output to its active state. */
00908 #define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2)   /*!< Master Timer compare 2 event forces the output to its active state. */
00909 #define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3)   /*!< Master Timer compare 3 event forces the output to its active state. */
00910 #define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4)   /*!< Master Timer compare 4 event forces the output to its active state. */
00911 #define HRTIM_OUTPUTSET_TIMEV_1    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state. */
00912 #define HRTIM_OUTPUTSET_TIMEV_2    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state. */
00913 #define HRTIM_OUTPUTSET_TIMEV_3    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state. */
00914 #define HRTIM_OUTPUTSET_TIMEV_4    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state. */
00915 #define HRTIM_OUTPUTSET_TIMEV_5    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state. */
00916 #define HRTIM_OUTPUTSET_TIMEV_6    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state. */
00917 #define HRTIM_OUTPUTSET_TIMEV_7    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state. */
00918 #define HRTIM_OUTPUTSET_TIMEV_8    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state. */
00919 #define HRTIM_OUTPUTSET_TIMEV_9    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state. */
00920 #define HRTIM_OUTPUTSET_EEV_1      (HRTIM_SET1R_EXTVNT1)   /*!< External event 1 forces the output to its active state. */
00921 #define HRTIM_OUTPUTSET_EEV_2      (HRTIM_SET1R_EXTVNT2)   /*!< External event 2 forces the output to its active state. */
00922 #define HRTIM_OUTPUTSET_EEV_3      (HRTIM_SET1R_EXTVNT3)   /*!< External event 3 forces the output to its active state. */
00923 #define HRTIM_OUTPUTSET_EEV_4      (HRTIM_SET1R_EXTVNT4)   /*!< External event 4 forces the output to its active state. */
00924 #define HRTIM_OUTPUTSET_EEV_5      (HRTIM_SET1R_EXTVNT5)   /*!< External event 5 forces the output to its active state. */
00925 #define HRTIM_OUTPUTSET_EEV_6      (HRTIM_SET1R_EXTVNT6)   /*!< External event 6 forces the output to its active state. */
00926 #define HRTIM_OUTPUTSET_EEV_7      (HRTIM_SET1R_EXTVNT7)   /*!< External event 7 forces the output to its active state. */
00927 #define HRTIM_OUTPUTSET_EEV_8      (HRTIM_SET1R_EXTVNT8)   /*!< External event 8 forces the output to its active state. */
00928 #define HRTIM_OUTPUTSET_EEV_9      (HRTIM_SET1R_EXTVNT9)   /*!< External event 9 forces the output to its active state. */
00929 #define HRTIM_OUTPUTSET_EEV_10     (HRTIM_SET1R_EXTVNT10)  /*!< External event 10 forces the output to its active state. */
00930 #define HRTIM_OUTPUTSET_UPDATE     (HRTIM_SET1R_UPDATE)    /*!< Timer register update event forces the output to its active state. */
00931
00932 /**
00933   * @}
00934   */
00935
00936 /** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
00937   * @{
00938   * @brief Constants defining the events that can be selected to configure the
00939   *        set crossbar of a timer output
00940   */
00941 #define HRTIM_OUTPUTRESET_NONE       ((uint32_t)0x00000000U) /*!< Reset the output reset crossbar. */
00942 #define HRTIM_OUTPUTRESET_RESYNC     (HRTIM_RST1R_RESYNC)    /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state. */
00943 #define HRTIM_OUTPUTRESET_TIMPER     (HRTIM_RST1R_PER)       /*!< Timer period event forces the output to its inactive state. */
00944 #define HRTIM_OUTPUTRESET_TIMCMP1    (HRTIM_RST1R_CMP1)      /*!< Timer compare 1 event forces the output to its inactive state. */
00945 #define HRTIM_OUTPUTRESET_TIMCMP2    (HRTIM_RST1R_CMP2)      /*!< Timer compare 2 event forces the output to its inactive state. */
00946 #define HRTIM_OUTPUTRESET_TIMCMP3    (HRTIM_RST1R_CMP3)      /*!< Timer compare 3 event forces the output to its inactive state. */
00947 #define HRTIM_OUTPUTRESET_TIMCMP4    (HRTIM_RST1R_CMP4)      /*!< Timer compare 4 event forces the output to its inactive state. */
00948 #define HRTIM_OUTPUTRESET_MASTERPER  (HRTIM_RST1R_MSTPER)    /*!< The master timer period event forces the output to its inactive state. */
00949 #define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1)   /*!< Master Timer compare 1 event forces the output to its inactive state. */
00950 #define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2)   /*!< Master Timer compare 2 event forces the output to its inactive state. */
00951 #define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3)   /*!< Master Timer compare 3 event forces the output to its inactive state. */
00952 #define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4)   /*!< Master Timer compare 4 event forces the output to its inactive state. */
00953 #define HRTIM_OUTPUTRESET_TIMEV_1    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state. */
00954 #define HRTIM_OUTPUTRESET_TIMEV_2    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state. */
00955 #define HRTIM_OUTPUTRESET_TIMEV_3    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state. */
00956 #define HRTIM_OUTPUTRESET_TIMEV_4    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state. */
00957 #define HRTIM_OUTPUTRESET_TIMEV_5    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state. */
00958 #define HRTIM_OUTPUTRESET_TIMEV_6    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state. */
00959 #define HRTIM_OUTPUTRESET_TIMEV_7    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state. */
00960 #define HRTIM_OUTPUTRESET_TIMEV_8    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state. */
00961 #define HRTIM_OUTPUTRESET_TIMEV_9    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state. */
00962 #define HRTIM_OUTPUTRESET_EEV_1      (HRTIM_RST1R_EXTVNT1)   /*!< External event 1 forces the output to its inactive state. */
00963 #define HRTIM_OUTPUTRESET_EEV_2      (HRTIM_RST1R_EXTVNT2)   /*!< External event 2 forces the output to its inactive state. */
00964 #define HRTIM_OUTPUTRESET_EEV_3      (HRTIM_RST1R_EXTVNT3)   /*!< External event 3 forces the output to its inactive state. */
00965 #define HRTIM_OUTPUTRESET_EEV_4      (HRTIM_RST1R_EXTVNT4)   /*!< External event 4 forces the output to its inactive state. */
00966 #define HRTIM_OUTPUTRESET_EEV_5      (HRTIM_RST1R_EXTVNT5)   /*!< External event 5 forces the output to its inactive state. */
00967 #define HRTIM_OUTPUTRESET_EEV_6      (HRTIM_RST1R_EXTVNT6)   /*!< External event 6 forces the output to its inactive state. */
00968 #define HRTIM_OUTPUTRESET_EEV_7      (HRTIM_RST1R_EXTVNT7)   /*!< External event 7 forces the output to its inactive state. */
00969 #define HRTIM_OUTPUTRESET_EEV_8      (HRTIM_RST1R_EXTVNT8)   /*!< External event 8 forces the output to its inactive state. */
00970 #define HRTIM_OUTPUTRESET_EEV_9      (HRTIM_RST1R_EXTVNT9)   /*!< External event 9 forces the output to its inactive state. */
00971 #define HRTIM_OUTPUTRESET_EEV_10     (HRTIM_RST1R_EXTVNT10)  /*!< External event 10 forces the output to its inactive state. */
00972 #define HRTIM_OUTPUTRESET_UPDATE     (HRTIM_RST1R_UPDATE)    /*!< Timer register update event forces the output to its inactive state. */
00973
00974 /**
00975   * @}
00976   */
00977
00978 /** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode
00979   * @{
00980   * @brief Constants defining whether or not the timer output transition to its
00981            IDLE state when burst mode is entered
00982   */
00983 #define HRTIM_OUTPUTIDLEMODE_NONE     ((uint32_t)0x00000000U)  /*!< The output is not affected by the burst mode operation. */
00984 #define HRTIM_OUTPUTIDLEMODE_IDLE     (HRTIM_OUTR_IDLM1)       /*!< The output is in idle state when requested by the burst mode controller. */
00985
00986  /**
00987   * @}
00988   */
00989
00990 /** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level
00991   * @{
00992   * @brief Constants defining the output level when output is in IDLE state
00993   */
00994 #define HRTIM_OUTPUTIDLELEVEL_INACTIVE   ((uint32_t)0x00000000U)  /*!< Output at inactive level when in IDLE state. */
00995 #define HRTIM_OUTPUTIDLELEVEL_ACTIVE     (HRTIM_OUTR_IDLES1)      /*!< Output at active level when in IDLE state. */
00996
00997 /**
00998   * @}
00999   */
01000
01001 /** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level
01002   * @{
01003   * @brief Constants defining the output level when output is in FAULT state
01004   */
01005 #define HRTIM_OUTPUTFAULTLEVEL_NONE      ((uint32_t)0x00000000U)                      /*!< The output is not affected by the fault input. */
01006 #define HRTIM_OUTPUTFAULTLEVEL_ACTIVE    (HRTIM_OUTR_FAULT1_0)                        /*!< Output at active level when in FAULT state. */
01007 #define HRTIM_OUTPUTFAULTLEVEL_INACTIVE  (HRTIM_OUTR_FAULT1_1)                        /*!< Output at inactive level when in FAULT state. */
01008 #define HRTIM_OUTPUTFAULTLEVEL_HIGHZ     (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0)  /*!< Output is tri-stated when in FAULT state. */
01009
01010 /**
01011   * @}
01012   */
01013
01014 /** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable
01015   * @{
01016   * @brief Constants defining whether or not chopper mode is enabled for a timer
01017            output
01018   */
01019 #define HRTIM_OUTPUTCHOPPERMODE_DISABLED   ((uint32_t)0x00000000U)  /*!< Output signal is not altered.  */
01020 #define HRTIM_OUTPUTCHOPPERMODE_ENABLED    (HRTIM_OUTR_CHP1)        /*!< Output signal is chopped by a carrier signal.  */
01021
01022 /**
01023   * @}
01024   */
01025
01026 /** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed
01027   * @{
01028   * @brief Constants defining the idle mode entry is delayed by forcing a
01029            deadtime insertion before switching the outputs to their idle state
01030   */
01031 #define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR   ((uint32_t)0x00000000U)  /*!< The programmed Idle state is applied immediately to the Output. */
01032 #define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED   (HRTIM_OUTR_DIDL1)       /*!< Deadtime is inserted on output before entering the idle mode. */
01033
01034 /**
01035   * @}
01036   */
01037
01038 /** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger
01039   * @{
01040   * @brief Constants defining the events that can be selected to trigger the
01041   *        capture of the timing unit counter
01042   */
01043 #define HRTIM_CAPTURETRIGGER_NONE         ((uint32_t)0x00000000U)  /*!< Capture trigger is disabled. */
01044 #define HRTIM_CAPTURETRIGGER_UPDATE       (HRTIM_CPT1CR_UPDCPT)    /*!< The update event triggers the Capture. */
01045 #define HRTIM_CAPTURETRIGGER_EEV_1        (HRTIM_CPT1CR_EXEV1CPT)  /*!< The External event 1 triggers the Capture. */
01046 #define HRTIM_CAPTURETRIGGER_EEV_2        (HRTIM_CPT1CR_EXEV2CPT)  /*!< The External event 2 triggers the Capture. */
01047 #define HRTIM_CAPTURETRIGGER_EEV_3        (HRTIM_CPT1CR_EXEV3CPT)  /*!< The External event 3 triggers the Capture. */
01048 #define HRTIM_CAPTURETRIGGER_EEV_4        (HRTIM_CPT1CR_EXEV4CPT)  /*!< The External event 4 triggers the Capture. */
01049 #define HRTIM_CAPTURETRIGGER_EEV_5        (HRTIM_CPT1CR_EXEV5CPT)  /*!< The External event 5 triggers the Capture. */
01050 #define HRTIM_CAPTURETRIGGER_EEV_6        (HRTIM_CPT1CR_EXEV6CPT)  /*!< The External event 6 triggers the Capture. */
01051 #define HRTIM_CAPTURETRIGGER_EEV_7        (HRTIM_CPT1CR_EXEV7CPT)  /*!< The External event 7 triggers the Capture. */
01052 #define HRTIM_CAPTURETRIGGER_EEV_8        (HRTIM_CPT1CR_EXEV8CPT)  /*!< The External event 8 triggers the Capture. */
01053 #define HRTIM_CAPTURETRIGGER_EEV_9        (HRTIM_CPT1CR_EXEV9CPT)  /*!< The External event 9 triggers the Capture. */
01054 #define HRTIM_CAPTURETRIGGER_EEV_10       (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture. */
01055 #define HRTIM_CAPTURETRIGGER_TA1_SET      (HRTIM_CPT1CR_TA1SET)    /*!< Capture is triggered by TA1 output inactive to active transition. */
01056 #define HRTIM_CAPTURETRIGGER_TA1_RESET    (HRTIM_CPT1CR_TA1RST)    /*!< Capture is triggered by TA1 output active to inactive transition. */
01057 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP1  (HRTIM_CPT1CR_TIMACMP1)  /*!< Timer A Compare 1 triggers Capture. */
01058 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP2  (HRTIM_CPT1CR_TIMACMP2)  /*!< Timer A Compare 2 triggers Capture. */
01059 #define HRTIM_CAPTURETRIGGER_TB1_SET      (HRTIM_CPT1CR_TB1SET)    /*!< Capture is triggered by TB1 output inactive to active transition. */
01060 #define HRTIM_CAPTURETRIGGER_TB1_RESET    (HRTIM_CPT1CR_TB1RST)    /*!< Capture is triggered by TB1 output active to inactive transition. */
01061 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP1  (HRTIM_CPT1CR_TIMBCMP1)  /*!< Timer B Compare 1 triggers Capture. */
01062 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP2  (HRTIM_CPT1CR_TIMBCMP2)  /*!< Timer B Compare 2 triggers Capture. */
01063 #define HRTIM_CAPTURETRIGGER_TC1_SET      (HRTIM_CPT1CR_TC1SET)    /*!< Capture is triggered by TC1 output inactive to active transition. */
01064 #define HRTIM_CAPTURETRIGGER_TC1_RESET    (HRTIM_CPT1CR_TC1RST)    /*!< Capture is triggered by TC1 output active to inactive transition. */
01065 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP1  (HRTIM_CPT1CR_TIMCCMP1)  /*!< Timer C Compare 1 triggers Capture. */
01066 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP2  (HRTIM_CPT1CR_TIMCCMP2)  /*!< Timer C Compare 2 triggers Capture. */
01067 #define HRTIM_CAPTURETRIGGER_TD1_SET      (HRTIM_CPT1CR_TD1SET)    /*!< Capture is triggered by TD1 output inactive to active transition. */
01068 #define HRTIM_CAPTURETRIGGER_TD1_RESET    (HRTIM_CPT1CR_TD1RST)    /*!< Capture is triggered by TD1 output active to inactive transition. */
01069 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP1  (HRTIM_CPT1CR_TIMDCMP1)  /*!< Timer D Compare 1 triggers Capture. */
01070 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP2  (HRTIM_CPT1CR_TIMDCMP2)  /*!< Timer D Compare 2 triggers Capture. */
01071 #define HRTIM_CAPTURETRIGGER_TE1_SET      (HRTIM_CPT1CR_TE1SET)    /*!< Capture is triggered by TE1 output inactive to active transition. */
01072 #define HRTIM_CAPTURETRIGGER_TE1_RESET    (HRTIM_CPT1CR_TE1RST)    /*!< Capture is triggered by TE1 output active to inactive transition. */
01073 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP1  (HRTIM_CPT1CR_TIMECMP1)  /*!< Timer E Compare 1 triggers Capture. */
01074 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP2  (HRTIM_CPT1CR_TIMECMP2)  /*!< Timer E Compare 2 triggers Capture. */
01075
01076 /**
01077   * @}
01078   */
01079
01080 /** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter
01081   * @{
01082   * @brief Constants defining the event filtering apploed to external events
01083   *        by a timer
01084   */
01085 #define HRTIM_TIMEVENTFILTER_NONE             (0x00000000U)
01086 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)                                                                                                                           /*!< Blanking from counter reset/roll-over to Compare 1 */
01087 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)                                                                                                                           /*!< Blanking from counter reset/roll-over to Compare 2 */
01088 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                                                                   /*!< Blanking from counter reset/roll-over to Compare 3 */
01089 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)                                                                                                                           /*!< Blanking from counter reset/roll-over to Compare 4 */
01090 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR1 source */
01091 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR2 source */
01092 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                                           /*!< Blanking from another timing unit: TIMFLTR3 source */
01093 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)                                                                                                                           /*!< Blanking from another timing unit: TIMFLTR4 source */
01094 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR5 source */
01095 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR6 source */
01096 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                                           /*!< Blanking from another timing unit: TIMFLTR7 source */
01097 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR8 source */
01098 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                                                                           /*!< Windowing from counter reset/roll-over to Compare 2 */
01099 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                                                                           /*!< Windowing from counter reset/roll-over to Compare 3 */
01100 #define HRTIM_TIMEVENTFILTER_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)  /*!< Windowing from another timing unit: TIMWIN source */
01101
01102 /**
01103   * @}
01104   */
01105
01106 /** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch
01107   * @{
01108   * @brief Constants defining whether or not the external event is
01109   *        memorized (latched) and generated as soon as the blanking period
01110   *        is completed or the window ends
01111   */
01112 #define HRTIM_TIMEVENTLATCH_DISABLED    ((uint32_t)0x00000000U)  /*!< Event is ignored if it happens during a blank, or passed through during a window. */
01113 #define HRTIM_TIMEVENTLATCH_ENABLED     HRTIM_EEFR1_EE1LTCH      /*!< Event is latched and delayed till the end of the blanking or windowing period. */
01114
01115 /**
01116   * @}
01117   */
01118
01119 /** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Deadtime Prescaler Ratio
01120   * @{
01121   * @brief Constants defining division ratio between the timer clock frequency
01122   *        (fHRTIM) and the deadtime generator clock (fDTG)
01123   */
01124 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8    ((uint32_t)0x00000000U)                                         /*!< fDTG = fHRTIM * 8. */
01125 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4    (HRTIM_DTR_DTPRSC_0)                                            /*!< fDTG = fHRTIM * 4. */
01126 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2    (HRTIM_DTR_DTPRSC_1)                                            /*!< fDTG = fHRTIM * 2. */
01127 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1    (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM. */
01128 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2    (HRTIM_DTR_DTPRSC_2)                                            /*!< fDTG = fHRTIM / 2. */
01129 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM / 4. */
01130 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1)                       /*!< fDTG = fHRTIM / 8. */
01131 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16   (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)  /*!< fDTG = fHRTIM / 16. */
01132
01133 /**
01134   * @}
01135   */
01136
01137 /** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Deadtime Rising Sign
01138   * @{
01139   * @brief Constants defining whether the deadtime is positive or negative
01140   *        (overlapping signal) on rising edge
01141   */
01142 #define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE    ((uint32_t)0x00000000U)  /*!< Positive deadtime on rising edge. */
01143 #define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE    (HRTIM_DTR_SDTR)         /*!< Negative deadtime on rising edge. */
01144
01145 /**
01146   * @}
01147   */
01148
01149 /** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Deadtime Rising Lock
01150   * @{
01151   * @brief Constants defining whether or not the deadtime (rising sign and
01152   *        value) is write protected
01153   */
01154 #define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE    ((uint32_t)0x00000000U)  /*!< Deadtime rising value and sign is writeable. */
01155 #define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK)        /*!< Deadtime rising value and sign is read-only. */
01156
01157 /**
01158   * @}
01159   */
01160
01161 /** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Deadtime Rising Sign Lock
01162   * @{
01163   * @brief Constants defining whether or not the deadtime rising sign is write
01164   *        protected
01165   */
01166 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE    ((uint32_t)0x00000000U)  /*!< Deadtime rising sign is writable. */
01167 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK)       /*!< Deadtime rising sign is read-only. */
01168
01169 /**
01170   * @}
01171   */
01172
01173 /** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Deadtime Falling Sign
01174   * @{
01175   * @brief Constants defining whether the deadtime is positive or negative
01176   *        (overlapping signal) on falling edge
01177   */
01178 #define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE    ((uint32_t)0x00000000U)  /*!< Positive deadtime on falling edge. */
01179 #define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE    (HRTIM_DTR_SDTF)         /*!< Negative deadtime on falling edge. */
01180
01181 /**
01182   * @}
01183   */
01184
01185 /** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Deadtime Falling Lock
01186   * @{
01187   * @brief Constants defining whether or not the deadtime (falling sign and
01188   *        value) is write protected
01189   */
01190 #define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE    ((uint32_t)0x00000000U)  /*!< Deadtime falling value and sign is writeable. */
01191 #define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK)        /*!< Deadtime falling value and sign is read-only. */
01192
01193 /**
01194   * @}
01195   */
01196
01197 /** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Deadtime Falling Sign Lock
01198   * @{
01199   * @brief Constants defining whether or not the deadtime falling sign is write
01200   *        protected
01201   */
01202 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE    ((uint32_t)0x00000000U)  /*!< Deadtime falling sign is writeable. */
01203 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK)       /*!< Deadtime falling sign is read-only. */
01204
01205 /**
01206   * @}
01207   */
01208
01209 /** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency
01210   * @{
01211   * @brief Constants defining the frequency of the generated high frequency carrier
01212   */
01213 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV16  ((uint32_t)0x000000U)                                                                    /*!< fCHPFRQ = fHRTIM / 16.  */
01214 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV32  (HRTIM_CHPR_CARFRQ_0)                                                                    /*!< fCHPFRQ = fHRTIM / 32.  */
01215 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV48  (HRTIM_CHPR_CARFRQ_1)                                                                    /*!< fCHPFRQ = fHRTIM / 48.  */
01216 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV64  (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 64.  */
01217 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV80  (HRTIM_CHPR_CARFRQ_2)                                                                    /*!< fCHPFRQ = fHRTIM / 80.  */
01218 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV96  (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 96.  */
01219 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 112.  */
01220 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 128.  */
01221 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3)                                                                    /*!< fCHPFRQ = fHRTIM / 144.  */
01222 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 160.  */
01223 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 176.  */
01224 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 192.  */
01225 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2)                                              /*!< fCHPFRQ = fHRTIM / 208.  */
01226 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 224.  */
01227 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                        /*!< fCHPFRQ = fHRTIM / 240.  */
01228 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)  /*!< fCHPFRQ = fHRTIM / 256.  */
01229
01230  /**
01231   * @}
01232   */
01233
01234 /** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle
01235   * @{
01236   * @brief Constants defining the duty cycle of the generated high frequency carrier
01237   *        Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
01238   */
01239 #define HRTIM_CHOPPER_DUTYCYCLE_0    ((uint32_t)0x000000U)                                             /*!< Only 1st pulse is present. */
01240 #define HRTIM_CHOPPER_DUTYCYCLE_125  (HRTIM_CHPR_CARDTY_0)                                             /*!< Duty cycle of the carrier signal is 12.5 %. */
01241 #define HRTIM_CHOPPER_DUTYCYCLE_250  (HRTIM_CHPR_CARDTY_1)                                             /*!< Duty cycle of the carrier signal is 25 %. */
01242 #define HRTIM_CHOPPER_DUTYCYCLE_375  (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 37.5 %. */
01243 #define HRTIM_CHOPPER_DUTYCYCLE_500  (HRTIM_CHPR_CARDTY_2)                                             /*!< Duty cycle of the carrier signal is 50 %. */
01244 #define HRTIM_CHOPPER_DUTYCYCLE_625  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 62.5 %. */
01245 #define HRTIM_CHOPPER_DUTYCYCLE_750  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1)                       /*!< Duty cycle of the carrier signal is 75 %. */
01246 #define HRTIM_CHOPPER_DUTYCYCLE_875  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5 %. */
01247
01248 /**
01249   * @}
01250   */
01251
01252 /** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width
01253   * @{
01254   * @brief Constants defining the pulse width of the first pulse of the generated
01255   *        high frequency carrier
01256   */
01257 #define HRTIM_CHOPPER_PULSEWIDTH_16   ((uint32_t)0x000000U)                                                                /*!< tSTPW = tHRTIM x 16.  */
01258 #define HRTIM_CHOPPER_PULSEWIDTH_32   (HRTIM_CHPR_STRPW_0)                                                                 /*!< tSTPW = tHRTIM x 32.  */
01259 #define HRTIM_CHOPPER_PULSEWIDTH_48   (HRTIM_CHPR_STRPW_1)                                                                 /*!< tSTPW = tHRTIM x 48.  */
01260 #define HRTIM_CHOPPER_PULSEWIDTH_64   (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 64.  */
01261 #define HRTIM_CHOPPER_PULSEWIDTH_80   (HRTIM_CHPR_STRPW_2)                                                                 /*!< tSTPW = tHRTIM x 80.  */
01262 #define HRTIM_CHOPPER_PULSEWIDTH_96   (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 96.  */
01263 #define HRTIM_CHOPPER_PULSEWIDTH_112  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 112.  */
01264 #define HRTIM_CHOPPER_PULSEWIDTH_128  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 128.  */
01265 #define HRTIM_CHOPPER_PULSEWIDTH_144  (HRTIM_CHPR_STRPW_3)                                                                 /*!< tSTPW = tHRTIM x 144.  */
01266 #define HRTIM_CHOPPER_PULSEWIDTH_160  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 160.  */
01267 #define HRTIM_CHOPPER_PULSEWIDTH_176  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 176.  */
01268 #define HRTIM_CHOPPER_PULSEWIDTH_192  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 192.  */
01269 #define HRTIM_CHOPPER_PULSEWIDTH_208  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2)                                            /*!< tSTPW = tHRTIM x 208.  */
01270 #define HRTIM_CHOPPER_PULSEWIDTH_224  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 224.  */
01271 #define HRTIM_CHOPPER_PULSEWIDTH_240  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                       /*!< tSTPW = tHRTIM x 240.  */
01272 #define HRTIM_CHOPPER_PULSEWIDTH_256  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)  /*!< tSTPW = tHRTIM x 256.  */
01273
01274 /**
01275   * @}
01276   */
01277
01278 /** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options
01279   * @{
01280   * @brief Constants defining the options for synchronizing multiple HRTIM
01281   *        instances, as a master unit (generating a synchronization signal)
01282   *        or as a slave (waiting for a trigger to be synchronized)
01283   */
01284 #define HRTIM_SYNCOPTION_NONE   ((uint32_t)0x00000000U)   /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT). */
01285 #define HRTIM_SYNCOPTION_MASTER ((uint32_t)0x00000001U)   /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT).*/
01286 #define HRTIM_SYNCOPTION_SLAVE  ((uint32_t)0x00000002U)   /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN). */
01287 /**
01288   * @}
01289   */
01290
01291 /** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source
01292   * @{
01293   * @brief Constants defining defining the synchronization input source
01294   */
01295 #define HRTIM_SYNCINPUTSOURCE_NONE           ((uint32_t)0x00000000U)                      /*!< disabled. HRTIM is not synchronized and runs in standalone mode. */
01296 #define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT  HRTIM_MCR_SYNC_IN_1                          /*!< The HRTIM is synchronized with the on-chip timer. */
01297 #define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT  (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0)  /*!< A positive pulse on SYNCIN input triggers the HRTIM. */
01298
01299 /**
01300   * @}
01301   */
01302
01303 /** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source
01304   * @{
01305   * @brief Constants defining the source and event to be sent on the
01306   *        synchronization outputs
01307   */
01308 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_START ((uint32_t)0x00000000U)                        /*!< A pulse is sent on the SYNCOUT output upon master timer start event. */
01309 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1  (HRTIM_MCR_SYNC_SRC_0)                         /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event. */
01310 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_START   (HRTIM_MCR_SYNC_SRC_1)                         /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events. */
01311 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1    (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0)  /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event. */
01312
01313 /**
01314   * @}
01315   */
01316
01317 /** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity
01318   * @{
01319   * @brief Constants defining the routing and conditioning of the synchronization output event
01320   */
01321 #define HRTIM_SYNCOUTPUTPOLARITY_NONE      ((uint32_t)0x00000000U)                       /*!< Synchronization output event is disabled. */
01322 #define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE  (HRTIM_MCR_SYNC_OUT_1)                        /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization. */
01323 #define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE  (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization. */
01324
01325 /**
01326   * @}
01327   */
01328
01329 /** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources
01330   * @{
01331   * @brief Constants defining available sources associated to external events
01332   */
01333 #define HRTIM_EVENTSRC_1         ((uint32_t)0x00000000U)                        /*!< External event source 1. */
01334 #define HRTIM_EVENTSRC_2         (HRTIM_EECR1_EE1SRC_0)                         /*!< External event source 2. */
01335 #define HRTIM_EVENTSRC_3         (HRTIM_EECR1_EE1SRC_1)                         /*!< External event source 3. */
01336 #define HRTIM_EVENTSRC_4         (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)  /*!< External event source 4. */
01337
01338 /**
01339   * @}
01340   */
01341
01342 /** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity
01343   * @{
01344   * @brief Constants defining the polarity of an external event
01345   */
01346 #define HRTIM_EVENTPOLARITY_HIGH    ((uint32_t)0x00000000U)  /*!< External event is active high. */
01347 #define HRTIM_EVENTPOLARITY_LOW     (HRTIM_EECR1_EE1POL)     /*!< External event is active low. */
01348
01349 /**
01350   * @}
01351   */
01352
01353 /** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity
01354   * @{
01355   * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
01356   *        of an external event
01357   */
01358 #define HRTIM_EVENTSENSITIVITY_LEVEL          ((uint32_t)0x00000000U)                        /*!< External event is active on level. */
01359 #define HRTIM_EVENTSENSITIVITY_RISINGEDGE     (HRTIM_EECR1_EE1SNS_0)                         /*!< External event is active on Rising edge. */
01360 #define HRTIM_EVENTSENSITIVITY_FALLINGEDGE    (HRTIM_EECR1_EE1SNS_1)                         /*!< External event is active on Falling edge. */
01361 #define HRTIM_EVENTSENSITIVITY_BOTHEDGES      (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0)  /*!< External event is active on Rising and Falling edges. */
01362
01363 /**
01364   * @}
01365   */
01366
01367 /** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode
01368   * @{
01369   * @brief Constants defining whether or not an external event is programmed in
01370            fast mode
01371   */
01372 #define HRTIM_EVENTFASTMODE_DISABLE         ((uint32_t)0x00000000U)   /*!< External Event is acting asynchronously on outputs (low latency mode). */
01373 #define HRTIM_EVENTFASTMODE_ENABLE          (HRTIM_EECR1_EE1FAST)     /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs. */
01374
01375 /**
01376   * @}
01377   */
01378
01379 /** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter
01380   * @{
01381   * @brief Constants defining the frequency used to sample an external event 6
01382   *        input and the length (N) of the digital filter applied
01383   */
01384 #define HRTIM_EVENTFILTER_NONE      ((uint32_t)0x00000000U)                                                               /*!< Filter disabled. */
01385 #define HRTIM_EVENTFILTER_1         (HRTIM_EECR3_EE6F_0)                                                                  /*!< fSAMPLING= fHRTIM, N=2. */
01386 #define HRTIM_EVENTFILTER_2         (HRTIM_EECR3_EE6F_1)                                                                  /*!< fSAMPLING= fHRTIM, N=4. */
01387 #define HRTIM_EVENTFILTER_3         (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING= fHRTIM, N=8. */
01388 #define HRTIM_EVENTFILTER_4         (HRTIM_EECR3_EE6F_2)                                                                  /*!< fSAMPLING= fEEVS/2, N=6. */
01389 #define HRTIM_EVENTFILTER_5         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING= fEEVS/2, N=8. */
01390 #define HRTIM_EVENTFILTER_6         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING= fEEVS/4, N=6. */
01391 #define HRTIM_EVENTFILTER_7         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING= fEEVS/4, N=8. */
01392 #define HRTIM_EVENTFILTER_8         (HRTIM_EECR3_EE6F_3)                                                                  /*!< fSAMPLING= fEEVS/8, N=6. */
01393 #define HRTIM_EVENTFILTER_9         (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING= fEEVS/8, N=8. */
01394 #define HRTIM_EVENTFILTER_10        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING= fEEVS/16, N=5. */
01395 #define HRTIM_EVENTFILTER_11        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING= fEEVS/16, N=6. */
01396 #define HRTIM_EVENTFILTER_12        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2)                                             /*!< fSAMPLING= fEEVS/16, N=8. */
01397 #define HRTIM_EVENTFILTER_13        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_0)                       /*!< fSAMPLING= fEEVS/32, N=5. */
01398 #define HRTIM_EVENTFILTER_14        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1)                       /*!< fSAMPLING= fEEVS/32, N=6. */
01399 #define HRTIM_EVENTFILTER_15        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)  /*!< fSAMPLING= fEEVS/32, N=8. */
01400
01401 /**
01402   * @}
01403   */
01404
01405 /** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler
01406   * @{
01407   * @brief Constants defining division ratio between the timer clock frequency
01408   *        fHRTIM) and the external event signal sampling clock (fEEVS)
01409   *        used by the digital filters
01410   */
01411 #define HRTIM_EVENTPRESCALER_DIV1    ((uint32_t)0x00000000U)                         /*!< fEEVS=fHRTIM. */
01412 #define HRTIM_EVENTPRESCALER_DIV2    (HRTIM_EECR3_EEVSD_0)                           /*!< fEEVS=fHRTIM / 2. */
01413 #define HRTIM_EVENTPRESCALER_DIV4    (HRTIM_EECR3_EEVSD_1)                           /*!< fEEVS=fHRTIM / 4. */
01414 #define HRTIM_EVENTPRESCALER_DIV8    (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0)     /*!< fEEVS=fHRTIM / 8. */
01415
01416 /**
01417   * @}
01418   */
01419
01420 /** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources
01421   * @{
01422   * @brief Constants defining whether a faults is be triggered by any external
01423   *        or internal fault source
01424   */
01425 #define HRTIM_FAULTSOURCE_DIGITALINPUT      ((uint32_t)0x00000000U)     /*!< Fault input is FLT input pin. */
01426 #define HRTIM_FAULTSOURCE_INTERNAL          (HRTIM_FLTINR1_FLT1SRC)     /*!< Fault input is FLT_Int signal (e.g. internal comparator). */
01427
01428 /**
01429   * @}
01430   */
01431
01432 /** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity
01433   * @{
01434   * @brief Constants defining the polarity of a fault event
01435   */
01436 #define HRTIM_FAULTPOLARITY_LOW     ((uint32_t)0x00000000U)  /*!< Fault input is active low. */
01437 #define HRTIM_FAULTPOLARITY_HIGH    (HRTIM_FLTINR1_FLT1P)    /*!< Fault input is active high. */
01438
01439 /**
01440   * @}
01441   */
01442
01443 /** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter
01444   * @{
01445   * @ brief Constants defining the frequency used to sample the fault input and
01446   *         the length (N) of the digital filter applied
01447   */
01448 #define HRTIM_FAULTFILTER_NONE      ((uint32_t)0x00000000U)                                                                          /*!< Filter disabled. */
01449 #define HRTIM_FAULTFILTER_1         (HRTIM_FLTINR1_FLT1F_0)                                                                          /*!< fSAMPLING= fHRTIM, N=2. */
01450 #define HRTIM_FAULTFILTER_2         (HRTIM_FLTINR1_FLT1F_1)                                                                          /*!< fSAMPLING= fHRTIM, N=4. */
01451 #define HRTIM_FAULTFILTER_3         (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fHRTIM, N=8. */
01452 #define HRTIM_FAULTFILTER_4         (HRTIM_FLTINR1_FLT1F_2)                                                                          /*!< fSAMPLING= fFLTS/2, N=6. */
01453 #define HRTIM_FAULTFILTER_5         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/2, N=8. */
01454 #define HRTIM_FAULTFILTER_6         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/4, N=6. */
01455 #define HRTIM_FAULTFILTER_7         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/4, N=8. */
01456 #define HRTIM_FAULTFILTER_8         (HRTIM_FLTINR1_FLT1F_3)                                                                          /*!< fSAMPLING= fFLTS/8, N=6. */
01457 #define HRTIM_FAULTFILTER_9         (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/8, N=8. */
01458 #define HRTIM_FAULTFILTER_10        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/16, N=5. */
01459 #define HRTIM_FAULTFILTER_11        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/16, N=6. */
01460 #define HRTIM_FAULTFILTER_12        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2)                                                  /*!< fSAMPLING= fFLTS/16, N=8. */
01461 #define HRTIM_FAULTFILTER_13        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/32, N=5. */
01462 #define HRTIM_FAULTFILTER_14        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                          /*!< fSAMPLING= fFLTS/32, N=6. */
01463 #define HRTIM_FAULTFILTER_15        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)  /*!< fSAMPLING= fFLTS/32, N=8. */
01464
01465 /**
01466   * @}
01467   */
01468
01469 /** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock
01470   * @{
01471   * @brief Constants defining whether or not the fault programming bits are
01472            write protected
01473   */
01474 #define HRTIM_FAULTLOCK_READWRITE       ((uint32_t)0x00000000U)      /*!< Fault settings bits are read/write. */
01475 #define HRTIM_FAULTLOCK_READONLY        (HRTIM_FLTINR1_FLT1LCK)      /*!< Fault settings bits are read only. */
01476
01477 /**
01478   * @}
01479   */
01480
01481 /** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler
01482   * @{
01483   * @brief Constants defining the division ratio between the timer clock
01484   *        frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
01485   *        by the digital filters.
01486   */
01487 #define HRTIM_FAULTPRESCALER_DIV1    ((uint32_t)0x00000000U)                           /*!< fFLTS=fHRTIM. */
01488 #define HRTIM_FAULTPRESCALER_DIV2    (HRTIM_FLTINR2_FLTSD_0)                           /*!< fFLTS=fHRTIM / 2. */
01489 #define HRTIM_FAULTPRESCALER_DIV4    (HRTIM_FLTINR2_FLTSD_1)                           /*!< fFLTS=fHRTIM / 4. */
01490 #define HRTIM_FAULTPRESCALER_DIV8    (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0)   /*!< fFLTS=fHRTIM / 8. */
01491
01492 /**
01493   * @}
01494   */
01495
01496 /** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode
01497   * @{
01498   * @brief Constants defining if the burst mode is entered once or if it is
01499   *        continuously operating
01500   */
01501 #define HRTIM_BURSTMODE_SINGLESHOT ((uint32_t)0x00000000U)  /*!< Burst mode operates in single shot mode. */
01502 #define HRTIM_BURSTMODE_CONTINOUS   (HRTIM_BMCR_BMOM)       /*!< Burst mode operates in continuous mode. */
01503
01504 /**
01505   * @}
01506   */
01507
01508 /** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source
01509   * @{
01510   * @brief Constants defining the clock source for the burst mode counter
01511   */
01512 #define HRTIM_BURSTMODECLOCKSOURCE_MASTER     ((uint32_t)0x00000000U)                                           /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter. */
01513 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A    (HRTIM_BMCR_BMCLK_0)                                            /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter. */
01514 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B    (HRTIM_BMCR_BMCLK_1)                                            /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter. */
01515 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C    (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter. */
01516 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D    (HRTIM_BMCR_BMCLK_2)                                            /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter. */
01517 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E    (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter. */
01518 #define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1)                       /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock. */
01519 #define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)  /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock. */
01520 #define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO  (HRTIM_BMCR_BMCLK_3)                                            /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock. */
01521 #define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM     (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1)                       /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter. */
01522
01523 /**
01524   * @}
01525   */
01526
01527 /** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler
01528   * @{
01529   * @brief Constants defining the prescaling ratio of the fHRTIM clock
01530   *        for the burst mode controller
01531   */
01532 #define HRTIM_BURSTMODEPRESCALER_DIV1     ((uint32_t)0x00000000U)                                                                 /*!< fBRST = fHRTIM. */
01533 #define HRTIM_BURSTMODEPRESCALER_DIV2     (HRTIM_BMCR_BMPRSC_0)                                                                   /*!< fBRST = fHRTIM/2. */
01534 #define HRTIM_BURSTMODEPRESCALER_DIV4     (HRTIM_BMCR_BMPRSC_1)                                                                   /*!< fBRST = fHRTIM/4. */
01535 #define HRTIM_BURSTMODEPRESCALER_DIV8     (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/8. */
01536 #define HRTIM_BURSTMODEPRESCALER_DIV16    (HRTIM_BMCR_BMPRSC_2)                                                                   /*!< fBRST = fHRTIM/16. */
01537 #define HRTIM_BURSTMODEPRESCALER_DIV32    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/32. */
01538 #define HRTIM_BURSTMODEPRESCALER_DIV64    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/64. */
01539 #define HRTIM_BURSTMODEPRESCALER_DIV128   (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/128. */
01540 #define HRTIM_BURSTMODEPRESCALER_DIV256   (HRTIM_BMCR_BMPRSC_3)                                                                   /*!< fBRST = fHRTIM/256. */
01541 #define HRTIM_BURSTMODEPRESCALER_DIV512   (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/512. */
01542 #define HRTIM_BURSTMODEPRESCALER_DIV1024  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/1024. */
01543 #define HRTIM_BURSTMODEPRESCALER_DIV2048  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/2048. */
01544 #define HRTIM_BURSTMODEPRESCALER_DIV4096  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2)                                             /*!< fBRST = fHRTIM/4096. */
01545 #define HRTIM_BURSTMODEPRESCALER_DIV8192  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/8192. */
01546 #define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                       /*!< fBRST = fHRTIM/16384. */
01547 #define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768. */
01548
01549 /**
01550   * @}
01551   */
01552
01553 /** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable
01554   * @{
01555   * @brief Constants defining whether or not burst mode registers preload
01556            mechanism is enabled, i.e. a write access into a preloadable register
01557           (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
01558   */
01559 #define HRIM_BURSTMODEPRELOAD_DISABLED ((uint32_t)0x00000000U)  /*!< Preload disabled: the write access is directly done into active registers. */
01560 #define HRIM_BURSTMODEPRELOAD_ENABLED  (HRTIM_BMCR_BMPREN)      /*!< Preload enabled: the write access is done into preload registers. */
01561
01562 /**
01563   * @}
01564   */
01565
01566 /** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger
01567   * @{
01568   * @brief Constants defining the events that can be used tor trig the burst
01569   *        mode operation
01570   */
01571 #define HRTIM_BURSTMODETRIGGER_NONE               ((uint32_t)0x00000000U) /*!<  No trigger. */
01572 #define HRTIM_BURSTMODETRIGGER_MASTER_RESET       (HRTIM_BMTRGR_MSTRST)   /*!<  Master reset. */
01573 #define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION  (HRTIM_BMTRGR_MSTREP)   /*!<  Master repetition. */
01574 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP1        (HRTIM_BMTRGR_MSTCMP1)  /*!<  Master compare 1. */
01575 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP2        (HRTIM_BMTRGR_MSTCMP2)  /*!<  Master compare 2. */
01576 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP3        (HRTIM_BMTRGR_MSTCMP3)  /*!<  Master compare 3. */
01577 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP4        (HRTIM_BMTRGR_MSTCMP4)  /*!<  Master compare 4. */
01578 #define HRTIM_BURSTMODETRIGGER_TIMERA_RESET       (HRTIM_BMTRGR_TARST)    /*!< Timer A reset.  */
01579 #define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION  (HRTIM_BMTRGR_TAREP)    /*!< Timer A repetition.  */
01580 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1        (HRTIM_BMTRGR_TACMP1)   /*!< Timer A compare 1.  */
01581 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2        (HRTIM_BMTRGR_TACMP2)   /*!< Timer A compare 2.  */
01582 #define HRTIM_BURSTMODETRIGGER_TIMERB_RESET       (HRTIM_BMTRGR_TBRST)    /*!< Timer B reset.  */
01583 #define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION  (HRTIM_BMTRGR_TBREP)    /*!< Timer B repetition.  */
01584 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1        (HRTIM_BMTRGR_TBCMP1)   /*!< Timer B compare 1.  */
01585 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2        (HRTIM_BMTRGR_TBCMP2)   /*!< Timer B compare 2.  */
01586 #define HRTIM_BURSTMODETRIGGER_TIMERC_RESET       (HRTIM_BMTRGR_TCRST)    /*!< Timer C reset.  */
01587 #define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION  (HRTIM_BMTRGR_TCREP)    /*!< Timer C repetition.  */
01588 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1        (HRTIM_BMTRGR_TCCMP1)   /*!< Timer C compare 1.  */
01589 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2        (HRTIM_BMTRGR_TCCMP2)   /*!< Timer C compare 2.  */
01590 #define HRTIM_BURSTMODETRIGGER_TIMERD_RESET       (HRTIM_BMTRGR_TDRST)    /*!< Timer D reset.  */
01591 #define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION  (HRTIM_BMTRGR_TDREP)    /*!< Timer D repetition.  */
01592 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1        (HRTIM_BMTRGR_TDCMP1)   /*!< Timer D compare 1.  */
01593 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2        (HRTIM_BMTRGR_TDCMP2)   /*!< Timer D compare 2.  */
01594 #define HRTIM_BURSTMODETRIGGER_TIMERE_RESET       (HRTIM_BMTRGR_TERST)    /*!< Timer E reset.  */
01595 #define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION  (HRTIM_BMTRGR_TEREP)    /*!< Timer E repetition.  */
01596 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1        (HRTIM_BMTRGR_TECMP1)   /*!< Timer E compare 1.  */
01597 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2        (HRTIM_BMTRGR_TECMP2)   /*!< Timer E compare 2.  */
01598 #define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7      (HRTIM_BMTRGR_TAEEV7)   /*!< Timer A period following External Event 7.  */
01599 #define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8      (HRTIM_BMTRGR_TDEEV8)   /*!< Timer D period following External Event 8.  */
01600 #define HRTIM_BURSTMODETRIGGER_EVENT_7            (HRTIM_BMTRGR_EEV7)     /*!< External Event 7 (timer A filters applied). */
01601 #define HRTIM_BURSTMODETRIGGER_EVENT_8            (HRTIM_BMTRGR_EEV8)     /*!< External Event 8 (timer D filters applied). */
01602 #define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP       (HRTIM_BMTRGR_OCHPEV)   /*!< On-chip Event */
01603
01604 /**
01605   * @}
01606   */
01607
01608 /** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source
01609   * @{
01610   * @brief constants defining the source triggering the update of the
01611      HRTIM_ADCxR register (transfer from preload to active register).
01612   */
01613 #define HRTIM_ADCTRIGGERUPDATE_MASTER  ((uint32_t)0x00000000U)                       /*!< Master timer. */
01614 #define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0)                        /*!< Timer A. */
01615 #define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1)                        /*!< Timer B. */
01616 #define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C. */
01617 #define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2)                        /*!< Timer D. */
01618 #define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E. */
01619
01620 /**
01621   * @}
01622   */
01623
01624 /** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event
01625   * @{
01626   * @brief constants defining the events triggering ADC conversion.
01627   *        HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
01628   *        HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
01629   */
01630 #define HRTIM_ADCTRIGGEREVENT13_NONE           ((uint32_t)0x00000000U)  /*!< No ADC trigger event. */
01631 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1    (HRTIM_ADC1R_AD1MC1)     /*!< ADC Trigger on master compare 1. */
01632 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2    (HRTIM_ADC1R_AD1MC2)     /*!< ADC Trigger on master compare 2. */
01633 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3    (HRTIM_ADC1R_AD1MC3)     /*!< ADC Trigger on master compare 3. */
01634 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4    (HRTIM_ADC1R_AD1MC4)     /*!< ADC Trigger on master compare 4. */
01635 #define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD  (HRTIM_ADC1R_AD1MPER)    /*!< ADC Trigger on master period. */
01636 #define HRTIM_ADCTRIGGEREVENT13_EVENT_1        (HRTIM_ADC1R_AD1EEV1)    /*!< ADC Trigger on external event 1. */
01637 #define HRTIM_ADCTRIGGEREVENT13_EVENT_2        (HRTIM_ADC1R_AD1EEV2)    /*!< ADC Trigger on external event 2. */
01638 #define HRTIM_ADCTRIGGEREVENT13_EVENT_3        (HRTIM_ADC1R_AD1EEV3)    /*!< ADC Trigger on external event 3. */
01639 #define HRTIM_ADCTRIGGEREVENT13_EVENT_4        (HRTIM_ADC1R_AD1EEV4)    /*!< ADC Trigger on external event 4. */
01640 #define HRTIM_ADCTRIGGEREVENT13_EVENT_5        (HRTIM_ADC1R_AD1EEV5)    /*!< ADC Trigger on external event 5. */
01641 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2    (HRTIM_ADC1R_AD1TAC2)    /*!< ADC Trigger on Timer A compare 2. */
01642 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3    (HRTIM_ADC1R_AD1TAC3)    /*!< ADC Trigger on Timer A compare 3. */
01643 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4    (HRTIM_ADC1R_AD1TAC4)    /*!< ADC Trigger on Timer A compare 4. */
01644 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD  (HRTIM_ADC1R_AD1TAPER)   /*!< ADC Trigger on Timer A period. */
01645 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET   (HRTIM_ADC1R_AD1TARST)   /*!< ADC Trigger on Timer A reset. */
01646 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2    (HRTIM_ADC1R_AD1TBC2)    /*!< ADC Trigger on Timer B compare 2. */
01647 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3    (HRTIM_ADC1R_AD1TBC3)    /*!< ADC Trigger on Timer B compare 3. */
01648 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4    (HRTIM_ADC1R_AD1TBC4)    /*!< ADC Trigger on Timer B compare 4. */
01649 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD  (HRTIM_ADC1R_AD1TBPER)   /*!< ADC Trigger on Timer B period. */
01650 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET   (HRTIM_ADC1R_AD1TBRST)   /*!< ADC Trigger on Timer B reset. */
01651 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2    (HRTIM_ADC1R_AD1TCC2)    /*!< ADC Trigger on Timer C compare 2. */
01652 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3    (HRTIM_ADC1R_AD1TCC3)    /*!< ADC Trigger on Timer C compare 3. */
01653 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4    (HRTIM_ADC1R_AD1TCC4)    /*!< ADC Trigger on Timer C compare 4. */
01654 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD  (HRTIM_ADC1R_AD1TCPER)   /*!< ADC Trigger on Timer C period. */
01655 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2    (HRTIM_ADC1R_AD1TDC2)    /*!< ADC Trigger on Timer D compare 2. */
01656 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3    (HRTIM_ADC1R_AD1TDC3)    /*!< ADC Trigger on Timer D compare 3. */
01657 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4    (HRTIM_ADC1R_AD1TDC4)    /*!< ADC Trigger on Timer D compare 4. */
01658 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD  (HRTIM_ADC1R_AD1TDPER)   /*!< ADC Trigger on Timer D period. */
01659 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2    (HRTIM_ADC1R_AD1TEC2)    /*!< ADC Trigger on Timer E compare 2. */
01660 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3    (HRTIM_ADC1R_AD1TEC3)    /*!< ADC Trigger on Timer E compare 3. */
01661 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4    (HRTIM_ADC1R_AD1TEC4)    /*!< ADC Trigger on Timer E compare 4. */
01662 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD  (HRTIM_ADC1R_AD1TEPER)   /*!< ADC Trigger on Timer E period. */
01663
01664 #define HRTIM_ADCTRIGGEREVENT24_NONE           ((uint32_t)0x00000000U)  /*!< No ADC trigger event. */
01665 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1    (HRTIM_ADC2R_AD2MC1)     /*!< ADC Trigger on master compare 1. */
01666 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2    (HRTIM_ADC2R_AD2MC2)     /*!< ADC Trigger on master compare 2. */
01667 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3    (HRTIM_ADC2R_AD2MC3)     /*!< ADC Trigger on master compare 3. */
01668 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4    (HRTIM_ADC2R_AD2MC4)     /*!< ADC Trigger on master compare 4. */
01669 #define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD  (HRTIM_ADC2R_AD2MPER)    /*!< ADC Trigger on master period. */
01670 #define HRTIM_ADCTRIGGEREVENT24_EVENT_6        (HRTIM_ADC2R_AD2EEV6)    /*!< ADC Trigger on external event 6. */
01671 #define HRTIM_ADCTRIGGEREVENT24_EVENT_7        (HRTIM_ADC2R_AD2EEV7)    /*!< ADC Trigger on external event 7. */
01672 #define HRTIM_ADCTRIGGEREVENT24_EVENT_8        (HRTIM_ADC2R_AD2EEV8)    /*!< ADC Trigger on external event 8. */
01673 #define HRTIM_ADCTRIGGEREVENT24_EVENT_9        (HRTIM_ADC2R_AD2EEV9)    /*!< ADC Trigger on external event 9. */
01674 #define HRTIM_ADCTRIGGEREVENT24_EVENT_10       (HRTIM_ADC2R_AD2EEV10)   /*!< ADC Trigger on external event 10. */
01675 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2    (HRTIM_ADC2R_AD2TAC2)    /*!< ADC Trigger on Timer A compare 2. */
01676 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3    (HRTIM_ADC2R_AD2TAC3)    /*!< ADC Trigger on Timer A compare 3. */
01677 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4    (HRTIM_ADC2R_AD2TAC4)    /*!< ADC Trigger on Timer A compare 4. */
01678 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD  (HRTIM_ADC2R_AD2TAPER)   /*!< ADC Trigger on Timer A period. */
01679 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2    (HRTIM_ADC2R_AD2TBC2)    /*!< ADC Trigger on Timer B compare 2. */
01680 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3    (HRTIM_ADC2R_AD2TBC3)    /*!< ADC Trigger on Timer B compare 3. */
01681 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4    (HRTIM_ADC2R_AD2TBC4)    /*!< ADC Trigger on Timer B compare 4. */
01682 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD  (HRTIM_ADC2R_AD2TBPER)   /*!< ADC Trigger on Timer B period. */
01683 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2    (HRTIM_ADC2R_AD2TCC2)    /*!< ADC Trigger on Timer C compare 2. */
01684 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3    (HRTIM_ADC2R_AD2TCC3)    /*!< ADC Trigger on Timer C compare 3. */
01685 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4    (HRTIM_ADC2R_AD2TCC4)    /*!< ADC Trigger on Timer C compare 4. */
01686 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD  (HRTIM_ADC2R_AD2TCPER)   /*!< ADC Trigger on Timer C period. */
01687 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET   (HRTIM_ADC2R_AD2TCRST)   /*!< ADC Trigger on Timer C reset. */
01688 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2    (HRTIM_ADC2R_AD2TDC2)    /*!< ADC Trigger on Timer D compare 2. */
01689 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3    (HRTIM_ADC2R_AD2TDC3)    /*!< ADC Trigger on Timer D compare 3. */
01690 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4    (HRTIM_ADC2R_AD2TDC4)    /*!< ADC Trigger on Timer D compare 4. */
01691 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD  (HRTIM_ADC2R_AD2TDPER)   /*!< ADC Trigger on Timer D period. */
01692 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET   (HRTIM_ADC2R_AD2TDRST)   /*!< ADC Trigger on Timer D reset. */
01693 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2    (HRTIM_ADC2R_AD2TEC2)    /*!< ADC Trigger on Timer E compare 2 .*/
01694 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3    (HRTIM_ADC2R_AD2TEC3)    /*!< ADC Trigger on Timer E compare 3. */
01695 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4    (HRTIM_ADC2R_AD2TEC4)    /*!< ADC Trigger on Timer E compare 4. */
01696 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET   (HRTIM_ADC2R_AD2TERST)   /*!< ADC Trigger on Timer E reset. */
01697
01698 /**
01699   * @}
01700   */
01701
01702
01703 /** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update
01704   * @{
01705   * @brief Constants defining the registers that can be written during a burst
01706   *        DMA operation
01707   */
01708 #define HRTIM_BURSTDMA_NONE  ((uint32_t)0x00000000U)   /*!< No register is updated by Burst DMA accesses. */
01709 #define HRTIM_BURSTDMA_CR    (HRTIM_BDTUPR_TIMCR)      /*!< MCR or TIMxCR register is updated by Burst DMA accesses. */
01710 #define HRTIM_BURSTDMA_ICR   (HRTIM_BDTUPR_TIMICR)     /*!< MICR or TIMxICR register is updated by Burst DMA accesses. */
01711 #define HRTIM_BURSTDMA_DIER  (HRTIM_BDTUPR_TIMDIER)    /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses. */
01712 #define HRTIM_BURSTDMA_CNT   (HRTIM_BDTUPR_TIMCNT)     /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses. */
01713 #define HRTIM_BURSTDMA_PER   (HRTIM_BDTUPR_TIMPER)     /*!< MPER or PERxR register is updated by Burst DMA accesses. */
01714 #define HRTIM_BURSTDMA_REP   (HRTIM_BDTUPR_TIMREP)     /*!< MREPR or REPxR register is updated by Burst DMA accesses. */
01715 #define HRTIM_BURSTDMA_CMP1  (HRTIM_BDTUPR_TIMCMP1)    /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses. */
01716 #define HRTIM_BURSTDMA_CMP2  (HRTIM_BDTUPR_TIMCMP2)    /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses. */
01717 #define HRTIM_BURSTDMA_CMP3  (HRTIM_BDTUPR_TIMCMP3)    /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses. */
01718 #define HRTIM_BURSTDMA_CMP4  (HRTIM_BDTUPR_TIMCMP4)    /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses. */
01719 #define HRTIM_BURSTDMA_DTR   (HRTIM_BDTUPR_TIMDTR)     /*!< TDxR register is updated by Burst DMA accesses. */
01720 #define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R)   /*!< SET1R register is updated by Burst DMA accesses. */
01721 #define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R)   /*!< RST1R register is updated by Burst DMA accesses. */
01722 #define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R)   /*!< SET2R register is updated by Burst DMA accesses. */
01723 #define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R)   /*!< RST1R register is updated by Burst DMA accesses. */
01724 #define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1)   /*!< EEFxR1 register is updated by Burst DMA accesses. */
01725 #define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2)   /*!< EEFxR2 register is updated by Burst DMA accesses. */
01726 #define HRTIM_BURSTDMA_RSTR  (HRTIM_BDTUPR_TIMRSTR)    /*!< RSTxR register is updated by Burst DMA accesses. */
01727 #define HRTIM_BURSTDMA_CHPR  (HRTIM_BDTUPR_TIMCHPR)    /*!< CHPxR register is updated by Burst DMA accesses. */
01728 #define HRTIM_BURSTDMA_OUTR  (HRTIM_BDTUPR_TIMOUTR)    /*!< OUTxR register is updated by Burst DMA accesses. */
01729 #define HRTIM_BURSTDMA_FLTR  (HRTIM_BDTUPR_TIMFLTR)    /*!< FLTxR register is updated by Burst DMA accesses. */
01730
01731 /**
01732   * @}
01733   */
01734
01735 /** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control
01736   * @{
01737   * @brief Constants used to enable or disable the burst mode controller
01738   */
01739 #define HRTIM_BURSTMODECTL_DISABLED ((uint32_t)0x00000000U) /*!< Burst mode disabled. */
01740 #define HRTIM_BURSTMODECTL_ENABLED  (HRTIM_BMCR_BME)        /*!< Burst mode enabled. */
01741
01742 /**
01743   * @}
01744   */
01745
01746 /** @defgroup HRTIM_Fault_Mode_Control  HRTIM Fault Mode Control
01747   * @{
01748   * @brief Constants used to enable or disable a fault channel
01749   */
01750 #define HRTIM_FAULTMODECTL_DISABLED ((uint32_t)0x00000000U) /*!< Fault channel is disabled. */
01751 #define HRTIM_FAULTMODECTL_ENABLED  ((uint32_t)0x00000001U) /*!< Fault channel is  enabled. */
01752
01753 /**
01754   * @}
01755   */
01756
01757 /** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update
01758   * @{
01759   * @brief Constants used to force timer registers update
01760   */
01761 #define HRTIM_TIMERUPDATE_MASTER    (HRTIM_CR2_MSWU)     /*!< Forces an immediate transfer from the preload to the active register in the master timer. */
01762 #define HRTIM_TIMERUPDATE_A         (HRTIM_CR2_TASWU)    /*!< Forces an immediate transfer from the preload to the active register in the timer A. */
01763 #define HRTIM_TIMERUPDATE_B         (HRTIM_CR2_TBSWU)    /*!< Forces an immediate transfer from the preload to the active register in the timer B. */
01764 #define HRTIM_TIMERUPDATE_C         (HRTIM_CR2_TCSWU)    /*!< Forces an immediate transfer from the preload to the active register in the timer C. */
01765 #define HRTIM_TIMERUPDATE_D         (HRTIM_CR2_TDSWU)    /*!< Forces an immediate transfer from the preload to the active register in the timer D. */
01766 #define HRTIM_TIMERUPDATE_E         (HRTIM_CR2_TESWU)    /*!< Forces an immediate transfer from the preload to the active register in the timer E. */
01767
01768 /**
01769   * @}
01770   */
01771
01772 /** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset
01773   * @{
01774   * @brief Constants used to force timer counter reset
01775   */
01776 #define HRTIM_TIMERRESET_MASTER    (HRTIM_CR2_MRST)     /*!< Resets the master timer counter. */
01777 #define HRTIM_TIMERRESET_TIMER_A   (HRTIM_CR2_TARST)    /*!< Resets the timer A counter. */
01778 #define HRTIM_TIMERRESET_TIMER_B   (HRTIM_CR2_TBRST)    /*!< Resets the timer B counter. */
01779 #define HRTIM_TIMERRESET_TIMER_C   (HRTIM_CR2_TCRST)    /*!< Resets the timer C counter. */
01780 #define HRTIM_TIMERRESET_TIMER_D   (HRTIM_CR2_TDRST)    /*!< Resets the timer D counter. */
01781 #define HRTIM_TIMERRESET_TIMER_E   (HRTIM_CR2_TERST)    /*!< Resets the timer E counter. */
01782
01783 /**
01784   * @}
01785   */
01786
01787 /** @defgroup HRTIM_Output_Level HRTIM Output Level
01788   * @{
01789   * @brief Constants defining the level of a timer output
01790   */
01791 #define HRTIM_OUTPUTLEVEL_ACTIVE     ((uint32_t)0x00000001U) /*!< Forces the output to its active state. */
01792 #define HRTIM_OUTPUTLEVEL_INACTIVE   ((uint32_t)0x00000002U) /*!< Forces the output to its inactive state. */
01793
01794 /**
01795   * @}
01796   */
01797
01798 /** @defgroup HRTIM_Output_State HRTIM Output State
01799   * @{
01800   * @brief Constants defining the state of a timer output
01801   */
01802 #define HRTIM_OUTPUTSTATE_IDLE     ((uint32_t)0x00000001U)  /*!< Main operating mode, where the output can take the active or
01803                                                               inactive level as programmed in the crossbar unit. */
01804 #define HRTIM_OUTPUTSTATE_RUN      ((uint32_t)0x00000002U)  /*!< Default operating state (e.g. after an HRTIM reset, when the
01805                                                               outputs are disabled by software or during a burst mode operation. */
01806 #define HRTIM_OUTPUTSTATE_FAULT    ((uint32_t)0x00000003U)  /*!< Safety state, entered in case of a shut-down request on
01807                                                               FAULTx inputs. */
01808 /**
01809   * @}
01810   */
01811
01812 /** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status
01813   * @{
01814   * @brief Constants defining the operating state of the burst mode controller
01815   */
01816 #define HRTIM_BURSTMODESTATUS_NORMAL  ((uint32_t) 0x00000000U) /*!< Normal operation. */
01817 #define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT)      /*!< Burst operation on-going. */
01818 /**
01819   * @}
01820   */
01821
01822 /** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status
01823   * @{
01824   * @brief Constants defining on which output the signal is currently applied
01825   *        in push-pull mode
01826   */
01827 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1   ((uint32_t) 0x00000000U)   /*!< Signal applied on output 1 and output 2 forced inactive. */
01828 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2   (HRTIM_TIMISR_CPPSTAT)     /*!< Signal applied on output 2 and output 1 forced inactive. */
01829 /**
01830   * @}
01831   */
01832
01833 /** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status
01834   * @{
01835   * @brief Constants defining on which output the signal was applied, in
01836   *        push-pull mode balanced fault mode or delayed idle mode, when the
01837   *        protection was triggered
01838   */
01839 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1   ((uint32_t) 0x00000000U)      /*!< Protection occurred when the output 1 was active and output 2 forced inactive. */
01840 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2   (HRTIM_TIMISR_IPPSTAT)        /*!< Protection occurred when the output 2 was active and output 1 forced inactive. */
01841 /**
01842   * @}
01843   */
01844
01845 /** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable
01846   * @{
01847   */
01848 #define HRTIM_IT_NONE           ((uint32_t)0x00000000U) /*!< No interrupt enabled. */
01849 #define HRTIM_IT_FLT1           HRTIM_IER_FLT1          /*!< Fault 1 interrupt enable. */
01850 #define HRTIM_IT_FLT2           HRTIM_IER_FLT2          /*!< Fault 2 interrupt enable. */
01851 #define HRTIM_IT_FLT3           HRTIM_IER_FLT3          /*!< Fault 3 interrupt enable. */
01852 #define HRTIM_IT_FLT4           HRTIM_IER_FLT4          /*!< Fault 4 interrupt enable. */
01853 #define HRTIM_IT_FLT5           HRTIM_IER_FLT5          /*!< Fault 5 interrupt enable. */
01854 #define HRTIM_IT_SYSFLT         HRTIM_IER_SYSFLT        /*!< System Fault interrupt enable. */
01855 #define HRTIM_IT_BMPER          HRTIM_IER_BMPER         /*!<  Burst mode period interrupt enable. */
01856
01857 /**
01858   * @}
01859   */
01860
01861 /** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable
01862   * @{
01863   */
01864 #define HRTIM_MASTER_IT_NONE         ((uint32_t)0x00000000U) /*!< No interrupt enabled. */
01865 #define HRTIM_MASTER_IT_MCMP1        HRTIM_MDIER_MCMP1IE     /*!< Master compare 1 interrupt enable. */
01866 #define HRTIM_MASTER_IT_MCMP2        HRTIM_MDIER_MCMP2IE     /*!< Master compare 2 interrupt enable. */
01867 #define HRTIM_MASTER_IT_MCMP3        HRTIM_MDIER_MCMP3IE     /*!< Master compare 3 interrupt enable. */
01868 #define HRTIM_MASTER_IT_MCMP4        HRTIM_MDIER_MCMP4IE     /*!< Master compare 4 interrupt enable. */
01869 #define HRTIM_MASTER_IT_MREP         HRTIM_MDIER_MREPIE      /*!< Master Repetition interrupt enable. */
01870 #define HRTIM_MASTER_IT_SYNC         HRTIM_MDIER_SYNCIE      /*!< Synchronization input interrupt enable. */
01871 #define HRTIM_MASTER_IT_MUPD         HRTIM_MDIER_MUPDIE      /*!< Master update interrupt enable. */
01872
01873 /**
01874   * @}
01875   */
01876
01877 /** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable
01878   * @{
01879   */
01880 #define HRTIM_TIM_IT_NONE       ((uint32_t)0x00000000U)   /*!< No interrupt enabled. */
01881 #define HRTIM_TIM_IT_CMP1       HRTIM_TIMDIER_CMP1IE      /*!< Timer compare 1 interrupt enable. */
01882 #define HRTIM_TIM_IT_CMP2       HRTIM_TIMDIER_CMP2IE      /*!< Timer compare 2 interrupt enable. */
01883 #define HRTIM_TIM_IT_CMP3       HRTIM_TIMDIER_CMP3IE      /*!< Timer compare 3 interrupt enable. */
01884 #define HRTIM_TIM_IT_CMP4       HRTIM_TIMDIER_CMP4IE      /*!< Timer compare 4 interrupt enable. */
01885 #define HRTIM_TIM_IT_REP        HRTIM_TIMDIER_REPIE       /*!< Timer repetition interrupt enable. */
01886 #define HRTIM_TIM_IT_UPD        HRTIM_TIMDIER_UPDIE       /*!< Timer update interrupt enable. */
01887 #define HRTIM_TIM_IT_CPT1       HRTIM_TIMDIER_CPT1IE      /*!< Timer capture 1 interrupt enable. */
01888 #define HRTIM_TIM_IT_CPT2       HRTIM_TIMDIER_CPT2IE      /*!< Timer capture 2 interrupt enable. */
01889 #define HRTIM_TIM_IT_SET1       HRTIM_TIMDIER_SET1IE      /*!< Timer output 1 set interrupt enable. */
01890 #define HRTIM_TIM_IT_RST1       HRTIM_TIMDIER_RST1IE      /*!< Timer output 1 reset interrupt enable. */
01891 #define HRTIM_TIM_IT_SET2       HRTIM_TIMDIER_SET2IE      /*!< Timer output 2 set interrupt enable. */
01892 #define HRTIM_TIM_IT_RST2       HRTIM_TIMDIER_RST2IE      /*!< Timer output 2 reset interrupt enable. */
01893 #define HRTIM_TIM_IT_RST        HRTIM_TIMDIER_RSTIE       /*!< Timer reset interrupt enable. */
01894 #define HRTIM_TIM_IT_DLYPRT     HRTIM_TIMDIER_DLYPRTIE    /*!< Timer delay protection interrupt enable. */
01895
01896 /**
01897   * @}
01898   */
01899
01900 /** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag
01901   * @{
01902   */
01903 #define HRTIM_FLAG_FLT1           HRTIM_ISR_FLT1    /*!< Fault 1 interrupt flag. */
01904 #define HRTIM_FLAG_FLT2           HRTIM_ISR_FLT2    /*!< Fault 2 interrupt flag. */
01905 #define HRTIM_FLAG_FLT3           HRTIM_ISR_FLT3    /*!< Fault 3 interrupt flag. */
01906 #define HRTIM_FLAG_FLT4           HRTIM_ISR_FLT4    /*!< Fault 4 interrupt flag. */
01907 #define HRTIM_FLAG_FLT5           HRTIM_ISR_FLT5    /*!< Fault 5 interrupt flag. */
01908 #define HRTIM_FLAG_SYSFLT         HRTIM_ISR_SYSFLT  /*!< System Fault interrupt flag. */
01909 #define HRTIM_FLAG_BMPER          HRTIM_ISR_BMPER   /*!< Burst mode period interrupt flag. */
01910
01911 /**
01912   * @}
01913   */
01914
01915 /** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag
01916   * @{
01917   */
01918 #define HRTIM_MASTER_FLAG_MCMP1        HRTIM_MISR_MCMP1    /*!< Master compare 1 interrupt flag. */
01919 #define HRTIM_MASTER_FLAG_MCMP2        HRTIM_MISR_MCMP2    /*!< Master compare 2 interrupt flag. */
01920 #define HRTIM_MASTER_FLAG_MCMP3        HRTIM_MISR_MCMP3    /*!< Master compare 3 interrupt flag. */
01921 #define HRTIM_MASTER_FLAG_MCMP4        HRTIM_MISR_MCMP4   /*!< Master compare 4 interrupt flag. */
01922 #define HRTIM_MASTER_FLAG_MREP         HRTIM_MISR_MREP    /*!< Master Repetition interrupt flag. */
01923 #define HRTIM_MASTER_FLAG_SYNC         HRTIM_MISR_SYNC    /*!< Synchronization input interrupt flag. */
01924 #define HRTIM_MASTER_FLAG_MUPD         HRTIM_MISR_MUPD    /*!< Master update interrupt flag. */
01925
01926 /**
01927   * @}
01928   */
01929
01930 /** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag
01931   * @{
01932   */
01933 #define HRTIM_TIM_FLAG_CMP1       HRTIM_TIMISR_CMP1      /*!< Timer compare 1 interrupt flag. */
01934 #define HRTIM_TIM_FLAG_CMP2       HRTIM_TIMISR_CMP2      /*!< Timer compare 2 interrupt flag. */
01935 #define HRTIM_TIM_FLAG_CMP3       HRTIM_TIMISR_CMP3      /*!< Timer compare 3 interrupt flag. */
01936 #define HRTIM_TIM_FLAG_CMP4       HRTIM_TIMISR_CMP4      /*!< Timer compare 4 interrupt flag. */
01937 #define HRTIM_TIM_FLAG_REP        HRTIM_TIMISR_REP       /*!< Timer repetition interrupt flag. */
01938 #define HRTIM_TIM_FLAG_UPD        HRTIM_TIMISR_UPD       /*!< Timer update interrupt flag. */
01939 #define HRTIM_TIM_FLAG_CPT1       HRTIM_TIMISR_CPT1      /*!< Timer capture 1 interrupt flag. */
01940 #define HRTIM_TIM_FLAG_CPT2       HRTIM_TIMISR_CPT2      /*!< Timer capture 2 interrupt flag. */
01941 #define HRTIM_TIM_FLAG_SET1       HRTIM_TIMISR_SET1      /*!< Timer output 1 set interrupt flag. */
01942 #define HRTIM_TIM_FLAG_RST1       HRTIM_TIMISR_RST1      /*!< Timer output 1 reset interrupt flag. */
01943 #define HRTIM_TIM_FLAG_SET2       HRTIM_TIMISR_SET2      /*!< Timer output 2 set interrupt flag. */
01944 #define HRTIM_TIM_FLAG_RST2       HRTIM_TIMISR_RST2      /*!< Timer output 2 reset interrupt flag. */
01945 #define HRTIM_TIM_FLAG_RST        HRTIM_TIMISR_RST       /*!< Timer reset interrupt flag. */
01946 #define HRTIM_TIM_FLAG_DLYPRT     HRTIM_TIMISR_DLYPRT    /*!< Timer delay protection interrupt flag. */
01947
01948 /**
01949   * @}
01950   */
01951
01952 /** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable
01953   * @{
01954   */
01955 #define HRTIM_MASTER_DMA_NONE         ((uint32_t)0x00000000U) /*!< No DMA request enable. */
01956 #define HRTIM_MASTER_DMA_MCMP1        HRTIM_MDIER_MCMP1DE     /*!< Master compare 1 DMA request enable. */
01957 #define HRTIM_MASTER_DMA_MCMP2        HRTIM_MDIER_MCMP2DE     /*!< Master compare 2 DMA request enable. */
01958 #define HRTIM_MASTER_DMA_MCMP3        HRTIM_MDIER_MCMP3DE     /*!< Master compare 3 DMA request enable. */
01959 #define HRTIM_MASTER_DMA_MCMP4        HRTIM_MDIER_MCMP4DE     /*!< Master compare 4 DMA request enable. */
01960 #define HRTIM_MASTER_DMA_MREP         HRTIM_MDIER_MREPDE      /*!< Master Repetition DMA request enable. */
01961 #define HRTIM_MASTER_DMA_SYNC         HRTIM_MDIER_SYNCDE      /*!< Synchronization input DMA request enable. */
01962 #define HRTIM_MASTER_DMA_MUPD         HRTIM_MDIER_MUPDDE      /*!< Master update DMA request enable. */
01963
01964 /**
01965   * @}
01966   */
01967
01968 /** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable
01969   * @{
01970   */
01971 #define HRTIM_TIM_DMA_NONE      ((uint32_t)0x00000000U)    /*!< No DMA request enable. */
01972 #define HRTIM_TIM_DMA_CMP1       HRTIM_TIMDIER_CMP1DE      /*!< Timer compare 1 DMA request enable. */
01973 #define HRTIM_TIM_DMA_CMP2       HRTIM_TIMDIER_CMP2DE      /*!< Timer compare 2 DMA request enable. */
01974 #define HRTIM_TIM_DMA_CMP3       HRTIM_TIMDIER_CMP3DE      /*!< Timer compare 3 DMA request enable. */
01975 #define HRTIM_TIM_DMA_CMP4       HRTIM_TIMDIER_CMP4DE      /*!< Timer compare 4 DMA request enable. */
01976 #define HRTIM_TIM_DMA_REP        HRTIM_TIMDIER_REPDE       /*!< Timer repetition DMA request enable. */
01977 #define HRTIM_TIM_DMA_UPD        HRTIM_TIMDIER_UPDDE       /*!< Timer update DMA request enable. */
01978 #define HRTIM_TIM_DMA_CPT1       HRTIM_TIMDIER_CPT1DE      /*!< Timer capture 1 DMA request enable. */
01979 #define HRTIM_TIM_DMA_CPT2       HRTIM_TIMDIER_CPT2DE      /*!< Timer capture 2 DMA request enable. */
01980 #define HRTIM_TIM_DMA_SET1       HRTIM_TIMDIER_SET1DE      /*!< Timer output 1 set DMA request enable. */
01981 #define HRTIM_TIM_DMA_RST1       HRTIM_TIMDIER_RST1DE      /*!< Timer output 1 reset DMA request enable. */
01982 #define HRTIM_TIM_DMA_SET2       HRTIM_TIMDIER_SET2DE      /*!< Timer output 2 set DMA request enable. */
01983 #define HRTIM_TIM_DMA_RST2       HRTIM_TIMDIER_RST2DE      /*!< Timer output 2 reset DMA request enable. */
01984 #define HRTIM_TIM_DMA_RST        HRTIM_TIMDIER_RSTDE       /*!< Timer reset DMA request enable. */
01985 #define HRTIM_TIM_DMA_DLYPRT     HRTIM_TIMDIER_DLYPRTDE    /*!< Timer delay protection DMA request enable. */
01986
01987 /**
01988   * @}
01989   */
01990
01991 /**
01992   * @}
01993   */
01994
01995 /* Private macros --------------------------------------------------------*/
01996 /** @addtogroup HRTIM_Private_Macros HRTIM Private Macros
01997   * @{
01998   */
01999 #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
02000     (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER)   || \
02001      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A)  || \
02002      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B)  || \
02003      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C)  || \
02004      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D)  || \
02005      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
02006
02007 #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
02008      (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A)  || \
02009       ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B)  || \
02010       ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C)  || \
02011       ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D)  || \
02012       ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
02013 #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
02014     (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1)  || \
02015      ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2)  || \
02016      ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3)  || \
02017      ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
02018
02019 #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
02020     (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1)   || \
02021      ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
02022
02023 #define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U)
02024
02025 #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
02026     ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) &&   \
02027      (((OUTPUT) == HRTIM_OUTPUT_TA1) ||          \
02028       ((OUTPUT) == HRTIM_OUTPUT_TA2)))           \
02029     ||                                           \
02030     (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) &&    \
02031      (((OUTPUT) == HRTIM_OUTPUT_TB1) ||          \
02032       ((OUTPUT) == HRTIM_OUTPUT_TB2)))           \
02033     ||                                           \
02034     (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) &&    \
02035      (((OUTPUT) == HRTIM_OUTPUT_TC1) ||          \
02036       ((OUTPUT) == HRTIM_OUTPUT_TC2)))           \
02037     ||                                           \
02038     (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) &&    \
02039      (((OUTPUT) == HRTIM_OUTPUT_TD1) ||          \
02040       ((OUTPUT) == HRTIM_OUTPUT_TD2)))           \
02041     ||                                           \
02042     (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) &&    \
02043      (((OUTPUT) == HRTIM_OUTPUT_TE1) ||          \
02044       ((OUTPUT) == HRTIM_OUTPUT_TE2))))
02045
02046 #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
02047     (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1)   || \
02048      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2)   || \
02049      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3)   || \
02050      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))
02051
02052 #define IS_HRTIM_EVENT(EVENT)\
02053       (((EVENT) == HRTIM_EVENT_1)   || \
02054        ((EVENT) == HRTIM_EVENT_2)   || \
02055        ((EVENT) == HRTIM_EVENT_3)   || \
02056        ((EVENT) == HRTIM_EVENT_4)   || \
02057        ((EVENT) == HRTIM_EVENT_5)   || \
02058        ((EVENT) == HRTIM_EVENT_6)   || \
02059        ((EVENT) == HRTIM_EVENT_7)   || \
02060        ((EVENT) == HRTIM_EVENT_8)   || \
02061        ((EVENT) == HRTIM_EVENT_9)   || \
02062        ((EVENT) == HRTIM_EVENT_10))
02063
02064 #define IS_HRTIM_FAULT(FAULT)\
02065       (((FAULT) == HRTIM_FAULT_1)   || \
02066        ((FAULT) == HRTIM_FAULT_2)   || \
02067        ((FAULT) == HRTIM_FAULT_3)   || \
02068        ((FAULT) == HRTIM_FAULT_4)   || \
02069        ((FAULT) == HRTIM_FAULT_5))
02070
02071 #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
02072         (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
02073          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
02074          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8)  || \
02075          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4)  || \
02076          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2)  || \
02077          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1)  || \
02078          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2)  || \
02079          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
02080
02081 #define IS_HRTIM_MODE(MODE)\
02082           (((MODE) == HRTIM_MODE_CONTINUOUS)  ||  \
02083            ((MODE) == HRTIM_MODE_SINGLESHOT) || \
02084            ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
02085
02086 #define IS_HRTIM_MODE_ONEPULSE(MODE)\
02087           (((MODE) == HRTIM_MODE_SINGLESHOT) || \
02088            ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
02089
02090 #define IS_HRTIM_HALFMODE(HALFMODE)\
02091             (((HALFMODE) == HRTIM_HALFMODE_DISABLED)  ||  \
02092              ((HALFMODE) == HRTIM_HALFMODE_ENABLED))
02093
02094 #define IS_HRTIM_SYNCSTART(SYNCSTART)\
02095               (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED)  ||  \
02096                ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
02097
02098 #define IS_HRTIM_SYNCRESET(SYNCRESET)\
02099                 (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED)  ||  \
02100                  ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
02101
02102 #define IS_HHRTIM_DACSYNC(DACSYNC)\
02103                 (((DACSYNC) == HRTIM_DACSYNC_NONE)          ||  \
02104                  ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1)  ||  \
02105                  ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2)  ||  \
02106                  ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
02107
02108 #define IS_HRTIM_PRELOAD(PRELOAD)\
02109                 (((PRELOAD) == HRTIM_PRELOAD_DISABLED)  ||  \
02110                  ((PRELOAD) == HRTIM_PRELOAD_ENABLED))
02111
02112 #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
02113                 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT)      ||  \
02114                  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST)         ||  \
02115                  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
02116
02117 #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
02118                 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT)      ||  \
02119                  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST)         ||  \
02120                  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)  ||  \
02121                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1)           ||  \
02122                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2)           ||  \
02123                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3)           ||  \
02124                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE)    ||  \
02125                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE)    ||  \
02126                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
02127
02128 #define IS_HRTIM_TIMERBURSTMODE(TIMERBURSTMODE)                               \
02129                 (((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK)  || \
02130                  ((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
02131
02132 #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION)\
02133                 (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED)  || \
02134                  ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
02135
02136 #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
02137                   (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \
02138                    ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
02139
02140 #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U)
02141
02142 #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
02143       (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \
02144        ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
02145
02146 #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\
02147     ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) &&               \
02148         ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \
02149           ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED))))  \
02150       ||                                                                     \
02151         (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) &&             \
02152          ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED)))
02153
02154 #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\
02155           ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED)          || \
02156             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6)  || \
02157             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6)  || \
02158             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6)  || \
02159             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \
02160             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \
02161             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7))    \
02162             ||                                                                           \
02163             (((TIMPUSHPULLMODE) ==  HRTIM_TIMPUSHPULLMODE_ENABLED) &&                    \
02164              (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)     || \
02165               ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))))
02166
02167 #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U)
02168 #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U)
02169
02170 #define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001U) == 0x00000000U)
02171
02172 #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET)                       \
02173               (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \
02174                ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
02175
02176 #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
02177               (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                  || \
02178                ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)    || \
02179                ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)  || \
02180                ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
02181
02182 /* Auto delayed mode is only available for compare units 2 and 4 */
02183 #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE)     \
02184     ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) &&                                 \
02185      (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                 ||  \
02186       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)   ||  \
02187       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) ||  \
02188       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))   \
02189     ||                                                                         \
02190     (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) &&                                 \
02191      (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                 ||  \
02192       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)   ||  \
02193       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) ||  \
02194       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
02195
02196 #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
02197               (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE)   || \
02198                ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \
02199                ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
02200
02201
02202 #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
02203               (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \
02204                ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
02205
02206 #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
02207               (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE)       || \
02208                ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC)     || \
02209                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER)     || \
02210                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1)    || \
02211                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2)    || \
02212                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3)    || \
02213                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4)    || \
02214                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER)  || \
02215                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \
02216                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \
02217                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \
02218                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \
02219                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1)    || \
02220                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2)    || \
02221                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3)    || \
02222                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4)    || \
02223                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5)    || \
02224                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6)    || \
02225                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7)    || \
02226                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8)    || \
02227                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9)    || \
02228                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1)      || \
02229                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2)      || \
02230                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3)      || \
02231                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4)      || \
02232                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5)      || \
02233                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6)      || \
02234                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7)      || \
02235                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8)      || \
02236                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9)      || \
02237                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10)     || \
02238                ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
02239
02240 #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
02241               (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE)       || \
02242                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC)     || \
02243                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER)     || \
02244                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1)    || \
02245                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2)    || \
02246                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3)    || \
02247                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4)    || \
02248                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER)  || \
02249                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \
02250                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \
02251                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \
02252                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \
02253                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1)    || \
02254                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2)    || \
02255                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3)    || \
02256                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4)    || \
02257                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5)    || \
02258                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6)    || \
02259                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7)    || \
02260                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8)    || \
02261                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9)    || \
02262                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1)      || \
02263                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2)      || \
02264                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3)      || \
02265                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4)      || \
02266                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5)      || \
02267                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6)      || \
02268                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7)      || \
02269                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8)      || \
02270                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9)      || \
02271                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10)     || \
02272                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
02273
02274 #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
02275               (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \
02276                ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
02277
02278 #define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\
02279               (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \
02280                ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE))
02281
02282 #define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\
02283               (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE)     || \
02284                ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE)   || \
02285                ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \
02286                ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ))
02287
02288 #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
02289               (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED)  || \
02290                ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
02291
02292 #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
02293               (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR)  || \
02294                ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
02295
02296 #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER)    \
02297    (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE)          || \
02298    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE)         || \
02299    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1)          || \
02300    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2)          || \
02301    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3)          || \
02302    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4)          || \
02303    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5)          || \
02304    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6)          || \
02305    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7)          || \
02306    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8)          || \
02307    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9)          || \
02308    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10)            \
02309    ||                                                           \
02310    (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) &&                    \
02311      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
02312       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
02313       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
02314       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
02315       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
02316       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
02317       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
02318       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
02319       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
02320       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
02321       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
02322       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
02323       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
02324       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
02325       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
02326       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
02327     ||                                                          \
02328    (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) &&                    \
02329      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
02330       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
02331       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
02332       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
02333       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
02334       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
02335       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
02336       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
02337       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
02338       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
02339       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
02340       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
02341       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
02342       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
02343       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
02344       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
02345     ||                                                          \
02346    (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) &&                    \
02347      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
02348       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
02349       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
02350       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
02351       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
02352       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
02353       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
02354       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
02355       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
02356       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
02357       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
02358       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
02359       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
02360       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
02361       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
02362       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
02363     ||                                                          \
02364    (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) &&                    \
02365      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
02366       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
02367       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
02368       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
02369       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
02370       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
02371       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
02372       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
02373       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
02374       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
02375       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
02376       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
02377       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
02378       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
02379       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
02380       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
02381     ||                                                          \
02382    (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) &&                    \
02383      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
02384       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
02385       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
02386       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
02387       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
02388       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
02389       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
02390       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
02391       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
02392       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
02393       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
02394       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
02395       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
02396       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
02397       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
02398       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))))
02399
02400 #define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\
02401                 (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE)           || \
02402                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1)   || \
02403                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2)   || \
02404                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3)   || \
02405                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4)   || \
02406                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1)  || \
02407                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2)  || \
02408                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3)  || \
02409                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4)  || \
02410                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5)  || \
02411                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6)  || \
02412                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7)  || \
02413                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8)  || \
02414                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2)  || \
02415                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3)  || \
02416                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM))
02417
02418 #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
02419               (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \
02420                ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
02421
02422 #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\
02423                 (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \
02424                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \
02425                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \
02426                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \
02427                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \
02428                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \
02429                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \
02430                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16))
02431
02432 #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
02433                 (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE)    || \
02434                  ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
02435
02436 #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
02437                     (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE)    || \
02438                      ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
02439
02440 #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
02441                   (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE)    || \
02442                    ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
02443
02444 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
02445                       (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE)    || \
02446                        ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
02447
02448 #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
02449                           (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE)    || \
02450                            ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
02451
02452 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
02453                         (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE)    || \
02454                          ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
02455
02456 #define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\
02457                         (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16)    || \
02458                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32)    || \
02459                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48)    || \
02460                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64)    || \
02461                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80)    || \
02462                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96)    || \
02463                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112)   || \
02464                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128)   || \
02465                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144)   || \
02466                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160)   || \
02467                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176)   || \
02468                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192)   || \
02469                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208)   || \
02470                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224)   || \
02471                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240)   || \
02472                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256))
02473
02474 #define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\
02475                         (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0)    || \
02476                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125)  || \
02477                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250)  || \
02478                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375)  || \
02479                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500)  || \
02480                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625)  || \
02481                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750)  || \
02482                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875))
02483
02484 #define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\
02485                         (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16)   || \
02486                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32)   || \
02487                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48)   || \
02488                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64)   || \
02489                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80)   || \
02490                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96)   || \
02491                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112)  || \
02492                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128)  || \
02493                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144)  || \
02494                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160)  || \
02495                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176)  || \
02496                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192)  || \
02497                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208)  || \
02498                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224)  || \
02499                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240)  || \
02500                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256))
02501
02502 #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
02503               (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE)             || \
02504                ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT)    || \
02505                ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
02506
02507 #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
02508               (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START)  || \
02509                ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1)   || \
02510                ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START)    || \
02511                ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
02512
02513 #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
02514               (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE)  || \
02515                ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE)  || \
02516                ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
02517
02518 #define IS_HRTIM_EVENTSRC(EVENTSRC)\
02519                 (((EVENTSRC) == HRTIM_EVENTSRC_1)   || \
02520                  ((EVENTSRC) == HRTIM_EVENTSRC_2)   || \
02521                  ((EVENTSRC) == HRTIM_EVENTSRC_3)   || \
02522                  ((EVENTSRC) == HRTIM_EVENTSRC_4))
02523
02524 #define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\
02525     ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL)  &&      \
02526        (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH)  ||           \
02527         ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW)))              \
02528       ||                                                            \
02529       (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
02530        ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \
02531        ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)))
02532
02533 #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
02534                     (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL)       || \
02535                      ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE)  || \
02536                      ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \
02537                      ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
02538
02539 #define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\
02540     (((((EVENT) == HRTIM_EVENT_1) ||                 \
02541        ((EVENT) == HRTIM_EVENT_2) ||                 \
02542        ((EVENT) == HRTIM_EVENT_3) ||                 \
02543        ((EVENT) == HRTIM_EVENT_4) ||                 \
02544        ((EVENT) == HRTIM_EVENT_5)) &&                \
02545       (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \
02546        ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \
02547     ||                                               \
02548     (((EVENT) == HRTIM_EVENT_6) ||                   \
02549      ((EVENT) == HRTIM_EVENT_7) ||                   \
02550      ((EVENT) == HRTIM_EVENT_8) ||                   \
02551      ((EVENT) == HRTIM_EVENT_9) ||                   \
02552      ((EVENT) == HRTIM_EVENT_10)))
02553
02554 #define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\
02555       ((((EVENT) == HRTIM_EVENT_1) ||            \
02556         ((EVENT) == HRTIM_EVENT_2) ||            \
02557         ((EVENT) == HRTIM_EVENT_3) ||            \
02558         ((EVENT) == HRTIM_EVENT_4) ||            \
02559         ((EVENT) == HRTIM_EVENT_5))              \
02560        ||                                        \
02561       ((((EVENT) == HRTIM_EVENT_6) ||            \
02562         ((EVENT) == HRTIM_EVENT_7) ||            \
02563         ((EVENT) == HRTIM_EVENT_8) ||            \
02564         ((EVENT) == HRTIM_EVENT_9) ||            \
02565         ((EVENT) == HRTIM_EVENT_10)) &&          \
02566         (((FILTER) == HRTIM_EVENTFILTER_NONE) || \
02567         ((FILTER) == HRTIM_EVENTFILTER_1)     || \
02568         ((FILTER) == HRTIM_EVENTFILTER_2)     || \
02569         ((FILTER) == HRTIM_EVENTFILTER_3)     || \
02570         ((FILTER) == HRTIM_EVENTFILTER_4)     || \
02571         ((FILTER) == HRTIM_EVENTFILTER_5)     || \
02572         ((FILTER) == HRTIM_EVENTFILTER_6)     || \
02573         ((FILTER) == HRTIM_EVENTFILTER_7)     || \
02574         ((FILTER) == HRTIM_EVENTFILTER_8)     || \
02575         ((FILTER) == HRTIM_EVENTFILTER_9)     || \
02576         ((FILTER) == HRTIM_EVENTFILTER_10)    || \
02577         ((FILTER) == HRTIM_EVENTFILTER_11)    || \
02578         ((FILTER) == HRTIM_EVENTFILTER_12)    || \
02579         ((FILTER) == HRTIM_EVENTFILTER_13)    || \
02580         ((FILTER) == HRTIM_EVENTFILTER_14)    || \
02581         ((FILTER) == HRTIM_EVENTFILTER_15))))
02582
02583 #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
02584              (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1)  || \
02585               ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2)   || \
02586               ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4)   || \
02587               ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
02588
02589 #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
02590               (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \
02591                ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL))
02592
02593 #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
02594               (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \
02595                ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
02596
02597 #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
02598                 (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \
02599                  ((FAULTFILTER) == HRTIM_FAULTFILTER_1)    || \
02600                  ((FAULTFILTER) == HRTIM_FAULTFILTER_2)    || \
02601                  ((FAULTFILTER) == HRTIM_FAULTFILTER_3)    || \
02602                  ((FAULTFILTER) == HRTIM_FAULTFILTER_4)    || \
02603                  ((FAULTFILTER) == HRTIM_FAULTFILTER_5)    || \
02604                  ((FAULTFILTER) == HRTIM_FAULTFILTER_6)    || \
02605                  ((FAULTFILTER) == HRTIM_FAULTFILTER_7)    || \
02606                  ((FAULTFILTER) == HRTIM_FAULTFILTER_8)    || \
02607                  ((FAULTFILTER) == HRTIM_FAULTFILTER_9)    || \
02608                  ((FAULTFILTER) == HRTIM_FAULTFILTER_10)   || \
02609                  ((FAULTFILTER) == HRTIM_FAULTFILTER_11)   || \
02610                  ((FAULTFILTER) == HRTIM_FAULTFILTER_12)   || \
02611                  ((FAULTFILTER) == HRTIM_FAULTFILTER_13)   || \
02612                  ((FAULTFILTER) == HRTIM_FAULTFILTER_14)   || \
02613                  ((FAULTFILTER) == HRTIM_FAULTFILTER_15))
02614
02615 #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
02616               (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \
02617                ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
02618
02619 #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
02620              (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1)  || \
02621               ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2)   || \
02622               ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4)   || \
02623               ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
02624
02625 #define IS_HRTIM_BURSTMODE(BURSTMODE)\
02626               (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT)  || \
02627                ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
02628
02629 #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
02630               (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER)      || \
02631                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A)     || \
02632                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B)     || \
02633                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C)     || \
02634                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D)     || \
02635                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E)     || \
02636                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC)    || \
02637                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC)    || \
02638                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO)   || \
02639                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
02640
02641 #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
02642               (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1)     || \
02643                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2)     || \
02644                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4)     || \
02645                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8)     || \
02646                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16)    || \
02647                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32)    || \
02648                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64)    || \
02649                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128)   || \
02650                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256)   || \
02651                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512)   || \
02652                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024)  || \
02653                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048)  || \
02654                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096)  || \
02655                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192)  || \
02656                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \
02657                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
02658
02659 #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
02660               (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED)  || \
02661                ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
02662
02663 #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
02664               (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE)               || \
02665                ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET)       || \
02666                ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION)  || \
02667                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP1)       || \
02668                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP2)       || \
02669                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP3)       || \
02670                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP4)       || \
02671                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_RESET)      || \
02672                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \
02673                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_CMP1)       || \
02674                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_CMP2)       || \
02675                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_RESET)      || \
02676                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \
02677                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_CMP1)       || \
02678                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_CMP2)       || \
02679                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_RESET)      || \
02680                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \
02681                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_CMP1)       || \
02682                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_CMP2)       || \
02683                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_RESET)      || \
02684                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \
02685                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_CMP1)       || \
02686                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_CMP2)       || \
02687                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_RESET)      || \
02688                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \
02689                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_CMP1)       || \
02690                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_CMP2)       || \
02691                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7)     || \
02692                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8)     || \
02693                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_EVENT_7)           || \
02694                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_EVENT_8)           || \
02695                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
02696
02697 #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
02698              (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER)   || \
02699               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A)  || \
02700               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B)  || \
02701               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C)  || \
02702               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D)  || \
02703               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E))
02704
02705 #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA)                                       \
02706    ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000U) == 0x00000000U)) \
02707     ||                                                                                 \
02708     (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
02709     ||                                                                                 \
02710     (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
02711     ||                                                                                 \
02712     (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
02713     ||                                                                                 \
02714     (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
02715     ||                                                                                 \
02716     (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)))
02717
02718 #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
02719     (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED)  || \
02720      ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
02721
02722 #define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\
02723     (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED)  || \
02724      ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED))
02725
02726 #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U)
02727
02728 #define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FFU) == 0x00000000U)
02729
02730 #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
02731     (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE)  || \
02732      ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
02733
02734 #define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0U) == 0x00000000U)
02735
02736 #define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U)
02737
02738 #define IS_HRTIM_TIM_IT(IS_HRTIM_TIM_IT) (((IS_HRTIM_TIM_IT) & 0xFFFF8020U) == 0x00000000U)
02739
02740 #define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U)
02741
02742 #define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U)
02743 /**
02744   * @}
02745   */
02746
02747 /* Exported macros -----------------------------------------------------------*/
02748 /** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros
02749   * @{
02750   */
02751
02752 /** @brief Reset HRTIM handle state
02753   * @param  __HANDLE__: HRTIM handle.
02754   * @retval None
02755   */
02756 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)
02757
02758 /** @brief  Enables or disables the timer counter(s)
02759   * @param  __HANDLE__: specifies the HRTIM Handle.
02760   * @param  __TIMERS__: timersto enable/disable
02761   *        This parameter can be any combinations of the following values:
02762   *            @arg HRTIM_TIMERID_MASTER: Master timer identifier
02763   *            @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
02764   *            @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
02765   *            @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
02766   *            @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
02767   *            @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
02768   * @retval None
02769   */
02770 #define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__)   ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__))
02771
02772 /* The counter of a timing unit is disabled only if all the timer outputs */
02773 /* are disabled and no capture is configured                              */
02774 #define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
02775 #define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
02776 #define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
02777 #define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
02778 #define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
02779 #define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
02780   do {\
02781     if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
02782       {\
02783         ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\
02784       }\
02785     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
02786       {\
02787         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == RESET)\
02788           {\
02789             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\
02790           }\
02791       }\
02792     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
02793       {\
02794         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == RESET)\
02795           {\
02796             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\
02797           }\
02798       }\
02799     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
02800       {\
02801         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == RESET)\
02802           {\
02803             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\
02804           }\
02805       }\
02806     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
02807       {\
02808         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == RESET)\
02809           {\
02810             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\
02811           }\
02812       }\
02813     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
02814       {\
02815         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == RESET)\
02816           {\
02817             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\
02818           }\
02819       }\
02820   } while(0)
02821
02822 /** @brief  Enables or disables the specified HRTIM common interrupts.
02823   * @param  __HANDLE__: specifies the HRTIM Handle.
02824   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
02825   *        This parameter can be one of the following values:
02826   *            @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
02827   *            @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
02828   *            @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
02829   *            @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
02830   *            @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
02831   *            @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
02832   *            @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
02833   * @retval None
02834   */
02835 #define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
02836 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
02837
02838 /** @brief  Enables or disables the specified HRTIM Master timer interrupts.
02839   * @param  __HANDLE__: specifies the HRTIM Handle.
02840   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
02841   *        This parameter can be one of the following values:
02842   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
02843   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
02844   *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
02845   *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
02846   *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
02847   *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
02848   *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
02849   * @retval None
02850   */
02851 #define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__))
02852 #define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))
02853
02854 /** @brief  Enables or disables the specified HRTIM Timerx interrupts.
02855   * @param  __HANDLE__: specifies the HRTIM Handle.
02856   * @param  __TIMER__: specified the timing unit (Timer A to E)
02857   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
02858   *        This parameter can be one of the following values:
02859   *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
02860   *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
02861   *            @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
02862   *            @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
02863   *            @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
02864   *            @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
02865   *            @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
02866   *            @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
02867   *            @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
02868   *            @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
02869   *            @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
02870   *            @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
02871   *            @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
02872   *            @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
02873   * @retval None
02874   */
02875 #define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__)   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__))
02876 #define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))
02877
02878 /** @brief  Checks if the specified HRTIM common interrupt  source  is enabled or disabled.
02879   * @param  __HANDLE__: specifies the HRTIM Handle.
02880   * @param  __INTERRUPT__: specifies the interrupt source to check.
02881   *        This parameter can be one of the following values:
02882   *            @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
02883   *            @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
02884   *            @arg HRTIM_IT_FLT3: Fault 3 enable
02885   *            @arg HRTIM_IT_FLT4: Fault 4 enable
02886   *            @arg HRTIM_IT_FLT5: Fault 5 enable
02887   *            @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
02888   *            @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
02889   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
02890   */
02891 #define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
02892
02893 /** @brief  Checks if the specified HRTIM Master interrupt source  is enabled or disabled.
02894   * @param  __HANDLE__: specifies the HRTIM Handle.
02895   * @param  __INTERRUPT__: specifies the interrupt source to check.
02896   *        This parameter can be one of the following values:
02897   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
02898   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
02899   *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
02900   *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
02901   *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
02902   *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
02903   *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
02904   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
02905   */
02906 #define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
02907
02908 /** @brief  Checks if the specified HRTIM Timerx interrupt source  is enabled or disabled.
02909   * @param  __HANDLE__: specifies the HRTIM Handle.
02910   * @param  __TIMER__: specified the timing unit (Timer A to E)
02911   * @param  __INTERRUPT__: specifies the interrupt source to check.
02912   *        This parameter can be one of the following values:
02913   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
02914   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
02915   *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
02916   *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
02917   *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
02918   *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
02919   *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
02920   *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
02921   *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
02922   *            @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
02923   *            @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
02924   *            @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
02925   *            @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
02926   *            @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
02927   *            @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
02928   *            @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
02929   *            @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
02930   *            @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
02931   *            @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
02932   *            @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
02933   *            @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
02934   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
02935   */
02936 #define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
02937
02938 /** @brief  Clears the specified HRTIM common pending flag.
02939   * @param  __HANDLE__: specifies the HRTIM Handle.
02940   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
02941   *        This parameter can be one of the following values:
02942   *            @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag
02943   *            @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag
02944   *            @arg HRTIM_IT_FLT3: Fault 3 clear flag
02945   *            @arg HRTIM_IT_FLT4: Fault 4 clear flag
02946   *            @arg HRTIM_IT_FLT5: Fault 5 clear flag
02947   *            @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag
02948   *            @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag
02949   * @retval None
02950   */
02951 #define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))
02952
02953 /** @brief  Clears the specified HRTIM Master pending flag.
02954   * @param  __HANDLE__: specifies the HRTIM Handle.
02955   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
02956   *        This parameter can be one of the following values:
02957   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag
02958   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag
02959   *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag
02960   *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag
02961   *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag
02962   *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag
02963   *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag
02964   * @retval None
02965   */
02966 #define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__))
02967
02968 /** @brief  Clears the specified HRTIM Timerx pending flag.
02969   * @param  __HANDLE__: specifies the HRTIM Handle.
02970   * @param  __TIMER__: specified the timing unit (Timer A to E)
02971   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
02972   *        This parameter can be one of the following values:
02973   *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag
02974   *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag
02975   *            @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag
02976   *            @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag
02977   *            @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag
02978   *            @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag
02979   *            @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag
02980   *            @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag
02981   *            @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag
02982   *            @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag
02983   *            @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag
02984   *            @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag
02985   *            @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag
02986   *            @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag
02987   * @retval None
02988   */
02989 #define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__)   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__))
02990
02991 /* DMA HANDLING */
02992 /** @brief  Enables or disables the specified HRTIM common interrupts.
02993   * @param  __HANDLE__: specifies the HRTIM Handle.
02994   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
02995   *        This parameter can be one of the following values:
02996   *            @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
02997   *            @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
02998   *            @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
02999   *            @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
03000   *            @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
03001   *            @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
03002   *            @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
03003   * @retval None
03004   */
03005 #define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
03006 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
03007
03008 /** @brief  Enables or disables the specified HRTIM Master timer DMA requets.
03009   * @param  __HANDLE__: specifies the HRTIM Handle.
03010   * @param  __DMA__: specifies the DMA request to enable or disable.
03011   *        This parameter can be one of the following values:
03012   *            @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA resquest enable
03013   *            @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA resquest enable
03014   *            @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA resquest enable
03015   *            @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA resquest enable
03016   *            @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA resquest enable
03017   *            @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA resquest enable
03018   *            @arg HRTIM_MASTER_DMA_MUPD: Master update DMA resquest enable
03019   * @retval None
03020   */
03021 #define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__)   ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))
03022 #define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
03023
03024 /** @brief  Enables or disables the specified HRTIM Timerx DMA requests.
03025   * @param  __HANDLE__: specifies the HRTIM Handle.
03026   * @param  __TIMER__: specified the timing unit (Timer A to E)
03027   * @param  __DMA__: specifies the DMA request to enable or disable.
03028   *        This parameter can be one of the following values:
03029   *            @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA resquest enable
03030   *            @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA resquest enable
03031   *            @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA resquest enable
03032   *            @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA resquest enable
03033   *            @arg HRTIM_TIM_DMA_REP: Timer repetition DMA resquest enable
03034   *            @arg HRTIM_TIM_DMA_UPD: Timer update DMA resquest enable
03035   *            @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA resquest enable
03036   *            @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA resquest enable
03037   *            @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA resquest enable
03038   *            @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA resquest enable
03039   *            @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA resquest enable
03040   *            @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA resquest enable
03041   *            @arg HRTIM_TIM_DMA_RST: Timer reset DMA resquest enable
03042   *            @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA resquest enable
03043   * @retval None
03044   */
03045 #define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__)   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__))
03046 #define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))
03047
03048 #define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__)        (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__))
03049 #define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))
03050
03051 #define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__)        (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__))
03052 #define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))
03053
03054 #define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__,  __TIMER__, __FLAG__)        (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__))
03055 #define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__,  __TIMER__, __FLAG__)      ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))
03056
03057 /** @brief  Sets the HRTIM timer Counter Register value on runtime
03058   * @param  __HANDLE__: HRTIM Handle.
03059   * @param  __TIMER__: HRTIM timer
03060   *                   This parameter can be one of the following values:
03061   *                   @arg 0x5 for master timer
03062   *                   @arg 0x0 to 0x4 for timers A to E
03063   * @param  __COUNTER__: specifies the Counter Register new value.
03064   * @retval None
03065   */
03066 #define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \
03067   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\
03068    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__)))
03069
03070 /** @brief  Gets the HRTIM timer Counter Register value on runtime
03071   * @param  __HANDLE__: HRTIM Handle.
03072   * @param  __TIMER__: HRTIM timer
03073   *                   This parameter can be one of the following values:
03074   *                   @arg 0x5 for master timer
03075   *                   @arg 0x0 to 0x4 for timers A to E
03076   * @retval HRTIM timer Counter Register value
03077   */
03078 #define __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__) \
03079   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\
03080    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR))
03081
03082 /** @brief  Sets the HRTIM timer Period value on runtime
03083   * @param  __HANDLE__: HRTIM Handle.
03084   * @param  __TIMER__: HRTIM timer
03085   *                   This parameter can be one of the following values:
03086   *                   @arg 0x5 for master timer
03087   *                   @arg 0x0 to 0x4 for timers A to E
03088   * @param  __PERIOD__: specifies the Period Register new value.
03089   * @retval None
03090   */
03091 #define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \
03092   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\
03093    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__)))
03094
03095 /** @brief  Gets the HRTIM timer Period Register value on runtime
03096   * @param  __HANDLE__: HRTIM Handle.
03097   * @param  __TIMER__: HRTIM timer
03098   *                   This parameter can be one of the following values:
03099   *                   @arg 0x5 for master timer
03100   *                   @arg 0x0 to 0x4 for timers A to E
03101   * @retval timer Period Register
03102   */
03103 #define __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__) \
03104   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\
03105    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR))
03106
03107 /** @brief  Sets the HRTIM timer clock prescaler value on runtime
03108   * @param  __HANDLE__: HRTIM Handle.
03109   * @param  __TIMER__: HRTIM timer
03110   *                   This parameter can be one of the following values:
03111   *                   @arg 0x5 for master timer
03112   *                   @arg 0x0 to 0x4 for timers A to E
03113   * @param  __PRESCALER__: specifies the clock prescaler new value.
03114   *                   This parameter can be one of the following values:
03115   *                   @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
03116   *                   @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
03117   *                   @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
03118   *                   @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
03119   *                   @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
03120   *                   @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
03121   *                   @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
03122   *                   @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)
03123   * @retval None
03124   */
03125 #define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \
03126   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__PRESCALER__)) :\
03127    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR |= (__PRESCALER__)))
03128
03129 /** @brief  Gets the HRTIM timer clock prescaler value on runtime
03130   * @param  __HANDLE__: HRTIM Handle.
03131   * @param  __TIMER__: HRTIM timer
03132   *                   This parameter can be one of the following values:
03133   *                   @arg 0x5 for master timer
03134   *                   @arg 0x0 to 0x4 for timers A to E
03135   * @retval timer clock prescaler value
03136   */
03137 #define __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__) \
03138   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\
03139    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR  & HRTIM_TIMCR_CK_PSC))
03140
03141 /** @brief  Sets the HRTIM timer Compare Register value on runtime
03142   * @param  __HANDLE__: HRTIM Handle.
03143   * @param  __TIMER__: HRTIM timer
03144   *                   This parameter can be one of the following values:
03145   *                   @arg 0x0 to 0x4 for timers A to E
03146   * @param  __COMPAREUNIT__: timer compare unit
03147   *                   This parameter can be one of the following values:
03148   *                   @arg HRTIM_COMPAREUNIT_1: Compare unit 1
03149   *                   @arg HRTIM_COMPAREUNIT_2: Compare unit 2
03150   *                   @arg HRTIM_COMPAREUNIT_3: Compare unit 3
03151   *                   @arg HRTIM_COMPAREUNIT_4: Compare unit 4
03152   * @param  __COMPARE__: specifies the Compare new value.
03153   * @retval None
03154   */
03155 #define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \
03156       (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
03157         (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\
03158          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\
03159          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\
03160          ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \
03161          : \
03162         (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\
03163          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\
03164          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\
03165          ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__))))
03166
03167 /** @brief  Gets the HRTIM timer Compare Register value on runtime
03168   * @param  __HANDLE__: HRTIM Handle.
03169   * @param  __TIMER__: HRTIM timer
03170   *                   This parameter can be one of the following values:
03171   *                   @arg 0x0 to 0x4 for timers A to E
03172   * @param  __COMPAREUNIT__: timer compare unit
03173   *                   This parameter can be one of the following values:
03174   *                   @arg HRTIM_COMPAREUNIT_1: Compare unit 1
03175   *                   @arg HRTIM_COMPAREUNIT_2: Compare unit 2
03176   *                   @arg HRTIM_COMPAREUNIT_3: Compare unit 3
03177   *                   @arg HRTIM_COMPAREUNIT_4: Compare unit 4
03178   * @retval Compare value
03179   */
03180 #define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \
03181       (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
03182         (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\
03183          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\
03184          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\
03185          ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \
03186          : \
03187         (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\
03188          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\
03189          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\
03190          ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR)))
03191
03192 /**
03193   * @}
03194   */
03195
03196 /* Exported functions --------------------------------------------------------*/
03197 /** @addtogroup HRTIM_Exported_Functions HRTIM Exported Functions
03198 * @{
03199 */
03200
03201 /** @addtogroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
03202 * @{
03203 */
03204
03205 /* Initialization and Configuration functions  ********************************/
03206 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim);
03207
03208 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim);
03209
03210 void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim);
03211
03212 void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim);
03213
03214 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
03215                                            uint32_t TimerIdx,
03216                                            HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
03217
03218 /**
03219   * @}
03220   */
03221
03222 /** @addtogroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
03223 * @{
03224 */
03225
03226 /* Simple time base related functions  *****************************************/
03227 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim,
03228                                            uint32_t TimerIdx);
03229
03230 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim,
03231                                           uint32_t TimerIdx);
03232
03233 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim,
03234                                               uint32_t TimerIdx);
03235
03236 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim,
03237                                              uint32_t TimerIdx);
03238
03239 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim,
03240                                                uint32_t TimerIdx,
03241                                                uint32_t SrcAddr,
03242                                                uint32_t DestAddr,
03243                                                uint32_t Length);
03244
03245 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,
03246                                               uint32_t TimerIdx);
03247
03248 /**
03249   * @}
03250   */
03251
03252 /** @addtogroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
03253 * @{
03254 */
03255 /* Simple output compare related functions  ************************************/
03256 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,
03257                                                  uint32_t TimerIdx,
03258                                                  uint32_t OCChannel,
03259                                                  HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg);
03260
03261 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,
03262                                          uint32_t TimerIdx,
03263                                          uint32_t OCChannel);
03264
03265 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim,
03266                                         uint32_t TimerIdx,
03267                                         uint32_t OCChannel);
03268
03269 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim,
03270                                             uint32_t TimerIdx,
03271                                             uint32_t OCChannel);
03272
03273 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim,
03274                                            uint32_t TimerIdx,
03275                                            uint32_t OCChannel);
03276
03277 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim,
03278                                              uint32_t TimerIdx,
03279                                              uint32_t OCChannel,
03280                                              uint32_t SrcAddr,
03281                                              uint32_t DestAddr,
03282                                              uint32_t Length);
03283
03284 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,
03285                                             uint32_t TimerIdx,
03286                                             uint32_t OCChannel);
03287
03288 /**
03289   * @}
03290   */
03291
03292 /** @addtogroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
03293 * @{
03294 */
03295 /* Simple PWM output related functions  ****************************************/
03296 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,
03297                                                   uint32_t TimerIdx,
03298                                                   uint32_t PWMChannel,
03299                                                   HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg);
03300
03301 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,
03302                                           uint32_t TimerIdx,
03303                                           uint32_t PWMChannel);
03304
03305 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim,
03306                                          uint32_t TimerIdx,
03307                                          uint32_t PWMChannel);
03308
03309 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim,
03310                                              uint32_t TimerIdx,
03311                                              uint32_t PWMChannel);
03312
03313 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim,
03314                                             uint32_t TimerIdx,
03315                                             uint32_t PWMChannel);
03316
03317 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim,
03318                                               uint32_t TimerIdx,
03319                                               uint32_t PWMChannel,
03320                                               uint32_t SrcAddr,
03321                                               uint32_t DestAddr,
03322                                               uint32_t Length);
03323
03324 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,
03325                                              uint32_t TimerIdx,
03326                                              uint32_t PWMChannel);
03327
03328 /**
03329   * @}
03330   */
03331
03332 /** @addtogroup HRTIM_Exported_Functions_Group5 Simple input capture functions
03333 * @{
03334 */
03335 /* Simple capture related functions  *******************************************/
03336 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,
03337                                                       uint32_t TimerIdx,
03338                                                       uint32_t CaptureChannel,
03339                                                       HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg);
03340
03341 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,
03342                                               uint32_t TimerIdx,
03343                                               uint32_t CaptureChannel);
03344
03345 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim,
03346                                              uint32_t TimerIdx,
03347                                              uint32_t CaptureChannel);
03348
03349 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim,
03350                                                  uint32_t TimerIdx,
03351                                                  uint32_t CaptureChannel);
03352
03353 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim,
03354                                                 uint32_t TimerIdx,
03355                                                 uint32_t CaptureChannel);
03356
03357 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim,
03358                                                   uint32_t TimerIdx,
03359                                                   uint32_t CaptureChannel,
03360                                                   uint32_t SrcAddr,
03361                                                   uint32_t DestAddr,
03362                                                   uint32_t Length);
03363
03364 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,
03365                                                  uint32_t TimerIdx,
03366                                                  uint32_t CaptureChannel);
03367
03368 /**
03369   * @}
03370   */
03371
03372 /** @addtogroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
03373 * @{
03374 */
03375 /* Simple one pulse related functions  *****************************************/
03376 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,
03377                                                        uint32_t TimerIdx,
03378                                                        uint32_t OnePulseChannel,
03379                                                        HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg);
03380
03381 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,
03382                                                uint32_t TimerIdx,
03383                                                uint32_t OnePulseChannel);
03384
03385 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim,
03386                                               uint32_t TimerIdx,
03387                                              uint32_t OnePulseChannel);
03388
03389 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim,
03390                                                   uint32_t TimerIdx,
03391                                                   uint32_t OnePulseChannel);
03392
03393 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,
03394                                                  uint32_t TimerIdx,
03395                                                  uint32_t OnePulseChannel);
03396
03397 /**
03398   * @}
03399   */
03400
03401 /** @addtogroup HRTIM_Exported_Functions_Group7 Configuration functions
03402 * @{
03403 */
03404 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,
03405                                             HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
03406
03407 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
03408                                         uint32_t Event,
03409                                         HRTIM_EventCfgTypeDef* pEventCfg);
03410
03411 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
03412                                                  uint32_t Prescaler);
03413
03414 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,
03415                                         uint32_t Fault,
03416                                         HRTIM_FaultCfgTypeDef* pFaultCfg);
03417
03418 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
03419                                                  uint32_t Prescaler);
03420
03421 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
03422                             uint32_t Faults,
03423                             uint32_t Enable);
03424
03425 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
03426                                              uint32_t ADCTrigger,
03427                                              HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
03428
03429 /**
03430   * @}
03431   */
03432
03433 /** @addtogroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
03434 * @{
03435 */
03436 /* Waveform related functions *************************************************/
03437 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
03438                                                 uint32_t TimerIdx,
03439                                                 HRTIM_TimerCfgTypeDef * pTimerCfg);
03440
03441 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
03442                                                   uint32_t TimerIdx,
03443                                                   uint32_t CompareUnit,
03444                                                   HRTIM_CompareCfgTypeDef* pCompareCfg);
03445
03446 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,
03447                                                   uint32_t TimerIdx,
03448                                                   uint32_t CaptureUnit,
03449                                                   HRTIM_CaptureCfgTypeDef* pCaptureCfg);
03450
03451 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
03452                                                  uint32_t TimerIdx,
03453                                                  uint32_t Output,
03454                                                  HRTIM_OutputCfgTypeDef * pOutputCfg);
03455
03456 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
03457                                                    uint32_t TimerIdx,
03458                                                    uint32_t Output,
03459                                                    uint32_t OutputLevel);
03460
03461 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,
03462                                                       uint32_t TimerIdx,
03463                                                       uint32_t Event,
03464                                                       HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
03465
03466 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
03467                                            uint32_t TimerIdx,
03468                                            HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
03469
03470 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,
03471                                               uint32_t TimerIdx,
03472                                               HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
03473
03474 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,
03475                                            uint32_t TimerIdx,
03476                                            uint32_t RegistersToUpdate);
03477
03478
03479 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef *hhrtim,
03480                                                  uint32_t Timers);
03481
03482 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop(HRTIM_HandleTypeDef *hhrtim,
03483                                                  uint32_t Timers);
03484
03485
03486 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef *hhrtim,
03487                                                  uint32_t Timers);
03488
03489 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef *hhrtim,
03490                                                  uint32_t Timers);
03491
03492
03493 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef *hhrtim,
03494                                                      uint32_t Timers);
03495
03496 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef *hhrtim,
03497                                                     uint32_t Timers);
03498
03499 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,
03500                                                 uint32_t OutputsToStart);
03501
03502 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,
03503                                                uint32_t OutputsToStop);
03504
03505 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim,
03506                                          uint32_t Enable);
03507
03508 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim);
03509
03510 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim,
03511                                             uint32_t TimerIdx,
03512                                             uint32_t CaptureUnit);
03513
03514 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim,
03515                                            uint32_t Timers);
03516
03517 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim,
03518                                           uint32_t Timers);
03519
03520 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
03521                                              uint32_t TimerIdx,
03522                                              uint32_t BurstBufferAddress,
03523                                              uint32_t BurstBufferLength);
03524
03525 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
03526                                           uint32_t Timers);
03527
03528 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
03529                                           uint32_t Timers);
03530
03531 /**
03532   * @}
03533   */
03534
03535 /** @addtogroup HRTIM_Exported_Functions_Group9 Peripheral state functions
03536 * @{
03537 */
03538 /* HRTIM peripheral state functions */
03539 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim);
03540
03541 uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef *hhrtim,
03542                                     uint32_t TimerIdx,
03543                                     uint32_t CaptureUnit);
03544
03545 uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
03546                                           uint32_t TimerIdx,
03547                                           uint32_t Output);
03548
03549 uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
03550                                           uint32_t TimerIdx,
03551                                           uint32_t Output);
03552
03553 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef *hhrtim,
03554                                               uint32_t TimerIdx,
03555                                               uint32_t Output);
03556
03557 uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef *hhrtim);
03558
03559 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef *hhrtim,
03560                                             uint32_t TimerIdx);
03561
03562 uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef *hhrtim,
03563                                          uint32_t TimerIdx);
03564
03565 /**
03566   * @}
03567   */
03568
03569 /** @addtogroup HRTIM_Exported_Functions_Group10 Interrupts handling
03570 * @{
03571 */
03572 /* IRQ handler */
03573 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim,
03574                           uint32_t TimerIdx);
03575
03576 /* HRTIM events related callback functions */
03577 void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim);
03578 void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim);
03579 void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim);
03580 void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim);
03581 void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim);
03582 void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim);
03583 void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim);
03584 void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim);
03585
03586 /* Timer events related callback functions */
03587 void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim,
03588                                               uint32_t TimerIdx);
03589 void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim,
03590                                               uint32_t TimerIdx);
03591 void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim,
03592                                             uint32_t TimerIdx);
03593 void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim,
03594                                             uint32_t TimerIdx);
03595 void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim,
03596                                             uint32_t TimerIdx);
03597 void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim,
03598                                             uint32_t TimerIdx);
03599 void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim,
03600                                             uint32_t TimerIdx);
03601 void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim,
03602                                             uint32_t TimerIdx);
03603 void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim,
03604                                                 uint32_t TimerIdx);
03605 void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim,
03606                                            uint32_t TimerIdx);
03607 void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim,
03608                                          uint32_t TimerIdx);
03609 void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim,
03610                                            uint32_t TimerIdx);
03611 void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim,
03612                                          uint32_t TimerIdx);
03613 void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim,
03614                                            uint32_t TimerIdx);
03615 void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim,
03616                                                uint32_t TimerIdx);
03617 void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim);
03618
03619 /**
03620   * @}
03621   */
03622
03623 /**
03624   * @}
03625   */
03626
03627 /**
03628   * @}
03629   */
03630
03631 /**
03632   * @}
03633   */
03634
03635
03636 #ifdef __cplusplus
03637 }
03638 #endif
03639
03640 #endif /* __STM32H7xx_HAL_HRTIM_H */
03641
03642 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_hsem.c Source File

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  • STM32H7xx_HAL_Driver
  • Src
stm32h7xx_hal_hsem.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_hsem.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   HSEM HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the semaphore peripheral:
00010   *           + Semaphore Take function (2-Step Procedure) , non blocking
00011   *           + Semaphore FastTake function (1-Step Procedure) , non blocking
00012   *           + Semaphore Status check
00013   *           + Semaphore Clear Key Set and Get
00014   *           + Release and release all functions
00015   *           + Semaphore notification enabling and disabling and callnack functions
00016   *           + IRQ handler management
00017   *
00018   *
00019   @verbatim
00020   ==============================================================================
00021                      ##### How to use this driver #####
00022   ==============================================================================
00023   [..]
00024       (#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters :
00025            (++) the semaphore ID from 0 to 31
00026            (++) the process ID from 0 to 255
00027       (#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter :
00028            (++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero
00029       (#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter :
00030           (++) the semaphore ID from 0_ID to 31
00031           (++) It returns 1 if the given semaphore is taken otherwise (Free) zero.
00032       (#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters :
00033            (++) the semaphore ID from 0 to 31
00034            (++) the process ID from 0 to 255:
00035            (++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt
00036          may be generated when enabled (notification activated). If ProcessID or MasterID does not match,
00037          semaphore remains taken (locked).
00038
00039       (#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All
00040           This function takes as parameters :
00041            (++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by
00042               HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions
00043            (++) the Master ID:
00044            (++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds
00045            to MasterID  will be freed, and an interrupt may be generated when enabled (notification activated). If the
00046            Key or the MasterID doesn't match, semaphores remains taken (locked).
00047
00048       (#)Semaphores Release all key functions:
00049          (++)  HAL_HSEM_SetClearKey() to set semaphore release all Key
00050          (++)  HAL_HSEM_GetClearKey() to get release all Key
00051       (#)Semaphores notification functions :
00052          (++)  HAL_HSEM_ActivateNotification to activate a notification callback on
00053                a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released
00054                the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released
00055                semaphores (bitfield).
00056
00057          (++)  HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield).
00058          (++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask
00059                 Used by the notification functions
00060      *** HSEM HAL driver macros list ***
00061      =============================================
00062      [..] Below the list of most used macros in HSEM HAL driver.
00063
00064       (+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask.
00065       [..] Example of use :
00066       [..] mask = __HAL_HSEM_SEMID_TO_MASK(8)  |  __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25).
00067       [..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using  __HAL_HSEM_SEMID_TO_MASK as the above example.
00068       (+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts.
00069       (+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts.
00070       (+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not.
00071       (+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags.
00072       (+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags.
00073
00074   @endverbatim
00075   ******************************************************************************
00076   * @attention
00077   *
00078   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00079   *
00080   * Redistribution and use in source and binary forms, with or without modification,
00081   * are permitted provided that the following conditions are met:
00082   *   1. Redistributions of source code must retain the above copyright notice,
00083   *      this list of conditions and the following disclaimer.
00084   *   2. Redistributions in binary form must reproduce the above copyright notice,
00085   *      this list of conditions and the following disclaimer in the documentation
00086   *      and/or other materials provided with the distribution.
00087   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00088   *      may be used to endorse or promote products derived from this software
00089   *      without specific prior written permission.
00090   *
00091   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00092   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00093   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00094   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00095   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00096   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00097   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00098   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00099   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00100   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00101   *
00102   ******************************************************************************
00103   */
00104
00105 /* Includes ------------------------------------------------------------------*/
00106 #include "stm32h7xx_hal.h"
00107
00108 /** @addtogroup STM32H7xx_HAL_Driver
00109   * @{
00110   */
00111
00112 /** @defgroup HSEM HSEM
00113   * @brief HSEM HAL module driver
00114   * @{
00115   */
00116
00117 #ifdef HAL_HSEM_MODULE_ENABLED
00118
00119 /* Private typedef -----------------------------------------------------------*/
00120 /* Private define ------------------------------------------------------------*/
00121 /* Private macro -------------------------------------------------------------*/
00122 /* Private variables ---------------------------------------------------------*/
00123 /* Private function prototypes -----------------------------------------------*/
00124 /* Private functions ---------------------------------------------------------*/
00125 /* Exported functions --------------------------------------------------------*/
00126
00127 /** @defgroup HSEM_Exported_Functions  HSEM Exported Functions
00128   * @{
00129   */
00130
00131 /** @defgroup HSEM_Exported_Functions_Group1 Take and Release functions
00132  *  @brief    HSEM Take and Release functions
00133  *
00134 @verbatim
00135  ==============================================================================
00136               ##### HSEM Take and Release functions #####
00137  ==============================================================================
00138 [..] This section provides functions allowing to:
00139       (+) Take a semaphore with 2 Step method
00140       (+) Fast Take a semaphore with 1 Step method
00141       (+) Check semaphore state Taken or not
00142       (+) Release a semaphore
00143       (+) Release all semaphore at once
00144
00145 @endverbatim
00146   * @{
00147   */
00148
00149
00150 /**
00151   * @brief  Take a semaphore in 2 Step mode.
00152   * @param  SemID: semaphore ID from 0 to 31
00153   * @param  ProcessID: Process ID from 0 to 255
00154   * @retval HAL status
00155 */
00156 HAL_StatusTypeDef  HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID)
00157 {
00158   /* Check the parameters */
00159   assert_param(IS_HSEM_SEMID(SemID));
00160   assert_param(IS_HSEM_PROCESSID(ProcessID));
00161
00162   /* First step  write R register with MasterID, processID and take bit=1*/
00163   HSEM->R[SemID] = ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK);
00164
00165   /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
00166   if(HSEM->R[SemID] == ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK))
00167   {
00168     /*take success when MasterID and ProcessID match and take bit set*/
00169     return HAL_OK;
00170   }
00171
00172   /* Semaphore take fails*/
00173   return HAL_ERROR;
00174 }
00175
00176 /**
00177   * @brief  Fast Take a semaphore with 1 Step mode.
00178   * @param  SemID: semaphore ID from 0 to 31
00179   * @retval HAL status
00180 */
00181 HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID)
00182 {
00183   /* Check the parameters */
00184   assert_param(IS_HSEM_SEMID(SemID));
00185
00186   /* Read the RLR register to take the semaphore */
00187   if(HSEM->RLR[SemID] == (((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_RLR_MASTERID) | HSEM_RLR_LOCK))
00188   {
00189     /*take success when MasterID match and take bit set*/
00190     return HAL_OK;
00191   }
00192
00193   /* Semaphore take fails */
00194   return HAL_ERROR;
00195 }
00196
00197 /**
00198   * @brief  Check semaphore state Taken or not.
00199   * @param  SemID: semaphore ID
00200   * @retval HAL HSEM state
00201   */
00202 uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID)
00203 {
00204   return ((HSEM->R[SemID] & HSEM_R_LOCK) != 0U);
00205 }
00206
00207
00208 /**
00209   * @brief  Release a semaphore.
00210   * @param  SemID: semaphore ID from 0 to 31
00211   * @param  ProcessID: Process ID from 0 to 255
00212   * @retval None
00213 */
00214 void  HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID)
00215 {
00216   /* Check the parameters */
00217   assert_param(IS_HSEM_SEMID(SemID));
00218   assert_param(IS_HSEM_PROCESSID(ProcessID));
00219
00220   /* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = 0  */
00221   HSEM->R[SemID] = ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID));
00222
00223 }
00224
00225 /**
00226   * @brief  Release All semaphore used by a given Master .
00227   * @param  Key: Semaphore Key , value from 0 to 0xFFFF
00228   * @param  MasterID: MasterID of the CPU that is using semaphores to be Released
00229   * @retval None
00230 */
00231 void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t MasterID)
00232 {
00233   assert_param(IS_HSEM_KEY(Key));
00234   assert_param(IS_HSEM_MASTERID(MasterID));
00235
00236   HSEM->CR = (((Key << POSITION_VAL(HSEM_KEYR_KEY)) & HSEM_CR_KEY ) | ((MasterID << POSITION_VAL(HSEM_CR_MASTERID)) & HSEM_CR_MASTERID));
00237 }
00238
00239 /**
00240   * @}
00241   */
00242
00243 /** @defgroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
00244  *  @brief    HSEM Set and Get Key functions.
00245  *
00246 @verbatim
00247   ==============================================================================
00248               ##### HSEM Set and Get Key functions #####
00249   ==============================================================================
00250     [..]  This section provides functions allowing to:
00251       (+) Set semaphore Key
00252       (+) Get semaphore Key
00253 @endverbatim
00254
00255   * @{
00256   */
00257
00258 /**
00259   * @brief  Set semaphore Key .
00260   * @param  Key: Semaphore Key , value from 0 to 0xFFFF
00261   * @retval None
00262 */
00263 void  HAL_HSEM_SetClearKey(uint32_t Key)
00264 {
00265   assert_param(IS_HSEM_KEY(Key));
00266
00267   MODIFY_REG(HSEM->KEYR, HSEM_KEYR_KEY, (Key << POSITION_VAL(HSEM_KEYR_KEY)));
00268
00269 }
00270
00271 /**
00272   * @brief  Get semaphore Key .
00273   * @retval Semaphore Key , value from 0 to 0xFFFF
00274 */
00275 uint32_t HAL_HSEM_GetClearKey(void)
00276 {
00277   return (HSEM->KEYR >> POSITION_VAL(HSEM_KEYR_KEY));
00278 }
00279
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup HSEM_Exported_Functions_Group3 HSEM IRQ handler management
00285  *  @brief    HSEM Notification functions.
00286  *
00287 @verbatim
00288   ==============================================================================
00289       ##### HSEM IRQ handler management and Notification functions #####
00290   ==============================================================================
00291 [..]  This section provides HSEM IRQ handler and Notification function.
00292
00293 @endverbatim
00294   * @{
00295   */
00296
00297 /**
00298   * @brief  Activate Semaphore release Notification for a given Semaphores Mask .
00299   * @param  SemMask: Mask of Released semaphores
00300   * @retval Semaphore Key
00301 */
00302 void HAL_HSEM_ActivateNotification(uint32_t SemMask)
00303 {
00304   /*Activate interrupt for CM7 Master */
00305   HSEM->IER |= SemMask;
00306 }
00307
00308 /**
00309   * @brief  Deactivate Semaphore release Notification for a given Semaphores Mask .
00310   * @param  SemMask: Mask of Released semaphores
00311   * @retval Semaphore Key
00312 */
00313 void HAL_HSEM_DeactivateNotification(uint32_t SemMask)
00314 {
00315
00316   /*Deactivate interrupt  for CM7 Master */
00317   HSEM->IER &= ~SemMask;
00318 }
00319
00320 /**
00321   * @brief  This function handles HSEM interrupt request.
00322   * @retval None
00323 */
00324 void HAL_HSEM_IRQHandler(void)
00325 {
00326   uint32_t statusreg = 0U;
00327
00328   /* Get the list of masked freed semaphores*/
00329   statusreg = HSEM->MISR;
00330
00331   /*Disable Interrupts*/
00332   HSEM->IER &= ~((uint32_t)statusreg);
00333
00334   /*Clear Flags*/
00335   HSEM->ICR |=  ((uint32_t)statusreg);
00336
00337
00338   /* Call FreeCallback */
00339   HAL_HSEM_FreeCallback(statusreg);
00340 }
00341
00342 /**
00343   * @brief Semaphore Released Callback.
00344   * @param SemMask: Mask of Released semaphores
00345   * @retval None
00346   */
00347 __weak void HAL_HSEM_FreeCallback(uint32_t SemMask)
00348 {
00349   /* Prevent unused argument(s) compilation warning */
00350   UNUSED(SemMask);
00351
00352   /* NOTE : This function should not be modified, when the callback is needed,
00353   the HAL_HSEM_FreeCallback can be implemented in the user file
00354   */
00355 }
00356
00357 /**
00358   * @}
00359   */
00360
00361 /**
00362   * @}
00363   */
00364
00365 #endif /* HAL_HSEM_MODULE_ENABLED */
00366 /**
00367   * @}
00368   */
00369
00370 /**
00371   * @}
00372   */
00373
00374 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_hsem.h Source File

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stm32h7xx_hal_hsem.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_hsem.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of HSEM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_HSEM_H
00040 #define __STM32H7xx_HAL_HSEM_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049
00050 /** @addtogroup STM32H7xx_HAL_Driver
00051    * @{
00052    */
00053
00054 /** @addtogroup HSEM
00055    * @{
00056    */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059
00060 /** @defgroup HSEM_Exported_Types HSEM Exported Types
00061    * @{
00062    */
00063
00064
00065 /**
00066   * @}
00067   */
00068
00069 /* Exported constants --------------------------------------------------------*/
00070
00071 /** @defgroup HSEM_Exported_Constants HSEM Exported Constants
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /* Exported macro ------------------------------------------------------------*/
00080 /** @defgroup HSEM_Exported_Macros HSEM Exported Macros
00081   * @{
00082   */
00083
00084 /**
00085   * @brief  SemID to mask helper Macro.
00086   * @param  __SEMID__: semaphore ID from 0 to 31
00087   * @retval Semaphore Mask.
00088   */
00089 #define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))
00090
00091
00092 /**
00093   * @brief  Enables the specified HSEM interrupts.
00094   * @param  __SEM_MASK__: semaphores Mask
00095   * @retval None.
00096   */
00097 #define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER0 |= (__SEM_MASK__))
00098 /**
00099   * @brief  Disables the specified HSEM interrupts.
00100   * @param  __SEM_MASK__: semaphores Mask
00101   * @retval None.
00102   */
00103 #define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER0 &= ~(__SEM_MASK__))
00104
00105 /**
00106   * @brief  Checks whether interrupt has occurred or not for semaphores specified by a mask.
00107   * @param  __SEM_MASK__: semaphores Mask
00108 * @retval semaphores Mask : Semaphores where an interrupt occurred.
00109   */
00110 #define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR0)
00111
00112 /**
00113   * @brief  Get the semaphores release status flags.
00114   * @param  __SEM_MASK__: semaphores Mask
00115   * @retval semaphores Mask : Semaphores where Release flags rise.
00116   */
00117 #define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR0)
00118
00119 /**
00120   * @brief  Clears the HSEM Interrupt flags.
00121   * @param  __SEM_MASK__: semaphores Mask
00122   * @retval None.
00123   */
00124 #define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR0 |= (__SEM_MASK__))
00125
00126 /**
00127   * @}
00128   */
00129
00130 /* Exported functions --------------------------------------------------------*/
00131 /** @defgroup HSEM_Exported_Functions HSEM Exported Functions
00132   * @{
00133   */
00134
00135
00136 /** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions
00137   * @brief    HSEM Take and Release functions
00138   * @{
00139   */
00140
00141 /* HSEM semaphore take (lock) using 2-Step  method ****************************/
00142 HAL_StatusTypeDef  HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID);
00143 /* HSEM semaphore fast take (lock) using 1-Step  method ***********************/
00144 HAL_StatusTypeDef  HAL_HSEM_FastTake(uint32_t SemID);
00145 /* HSEM Check semaphore state Taken or not   **********************************/
00146 uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID);
00147 /* HSEM Release  **************************************************************/
00148 void  HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID);
00149 /* HSEM Release All************************************************************/
00150 void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t MasterID);
00151
00152 /**
00153   * @}
00154   */
00155
00156 /** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
00157   * @brief    HSEM Set and Get Key functions.
00158   * @{
00159   */
00160 /* HSEM Set Clear Key *********************************************************/
00161 void  HAL_HSEM_SetClearKey(uint32_t Key);
00162 /* HSEM Get Clear Key *********************************************************/
00163 uint32_t HAL_HSEM_GetClearKey(void);
00164 /**
00165   * @}
00166   */
00167
00168
00169 /** @addtogroup HSEM_Exported_Functions_Group3
00170   * @brief   HSEM Notification functions
00171   * @{
00172   */
00173 /* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/
00174 void HAL_HSEM_ActivateNotification(uint32_t SemMask);
00175 /* HSEM Deactivate HSEM Notification (When a semaphore is released)  ****************/
00176 void HAL_HSEM_DeactivateNotification(uint32_t SemMask);
00177 /* HSEM Free Callback (When a semaphore is released)  *******************************/
00178 void HAL_HSEM_FreeCallback(uint32_t SemMask);
00179 /* HSEM IRQ Handler  **********************************************************/
00180 void HAL_HSEM_IRQHandler(void);
00181
00182
00183 /**
00184   * @}
00185   */
00186
00187
00188 /**
00189   * @}
00190   */
00191
00192  /* Private types -------------------------------------------------------------*/
00193 /** @defgroup HSEM_Private_Types HSEM Private Types
00194   * @{
00195   */
00196
00197 /**
00198   * @}
00199   */
00200
00201 /* Private variables ---------------------------------------------------------*/
00202 /** @defgroup HSEM_Private_Variables HSEM Private Variables
00203   * @{
00204   */
00205
00206 /**
00207   * @}
00208   */
00209
00210 /* Private constants ---------------------------------------------------------*/
00211 /** @defgroup HSEM_Private_Constants HSEM Private Constants
00212   * @{
00213   */
00214
00215 /**
00216   * @}
00217   */
00218
00219 /* Private macros ------------------------------------------------------------*/
00220 /** @defgroup HSEM_Private_Macros HSEM Private Macros
00221   * @{
00222   */
00223
00224 #define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )
00225
00226 #define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )
00227
00228 #define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
00229
00230 #define IS_HSEM_MASTERID(__MASTERID__) (((__MASTERID__) == HSEM_CM7_MASTERID))
00231 /**
00232   * @}
00233   */
00234
00235 /**
00236   * @}
00237   */
00238
00239 /**
00240   * @}
00241   */
00242
00243 #ifdef __cplusplus
00244 }
00245 #endif
00246
00247 #endif /* __STM32H7xx_HAL_HSEM_H */
00248
00249 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_i2c.c Source File

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stm32h7xx_hal_i2c.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_i2c.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   I2C HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral State and Errors functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                         ##### How to use this driver #####
00017   ==============================================================================
00018     [..]
00019     The I2C HAL driver can be used as follows:
00020
00021     (#) Declare a I2C_HandleTypeDef handle structure, for example:
00022         I2C_HandleTypeDef  hi2c;
00023
00024     (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
00025         (##) Enable the I2Cx interface clock
00026         (##) I2C pins configuration
00027             (+++) Enable the clock for the I2C GPIOs
00028             (+++) Configure I2C pins as alternate function open-drain
00029         (##) NVIC configuration if you need to use interrupt process
00030             (+++) Configure the I2Cx interrupt priority
00031             (+++) Enable the NVIC I2C IRQ Channel
00032         (##) DMA Configuration if you need to use DMA process
00033             (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
00034             (+++) Enable the DMAx interface clock using
00035             (+++) Configure the DMA handle parameters
00036             (+++) Configure the DMA Tx or Rx stream
00037             (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
00038             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
00039                   the DMA Tx or Rx stream
00040
00041     (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
00042         Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
00043
00044     (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
00045         (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
00046
00047     (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
00048
00049     (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
00050
00051     *** Polling mode IO operation ***
00052     =================================
00053     [..]
00054       (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
00055       (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
00056       (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
00057       (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
00058
00059     *** Polling mode IO MEM operation ***
00060     =====================================
00061     [..]
00062       (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
00063       (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
00064
00065
00066     *** Interrupt mode IO operation ***
00067     ===================================
00068     [..]
00069       (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
00070       (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
00071            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
00072       (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
00073       (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
00074            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
00075       (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
00076       (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
00077            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
00078       (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
00079       (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
00080            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
00081       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00082            add his own code by customization of function pointer HAL_I2C_ErrorCallback()
00083       (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00084       (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
00085            add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00086       (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
00087            This action will inform Master to generate a Stop condition to discard the communication.
00088
00089
00090     *** Interrupt mode IO sequential operation ***
00091     ===================================
00092     [..]
00093       (@) These interfaces allow to manage a sequential transfer with a repeated start condition
00094           when a direction change during transfer
00095     [..]
00096       (+) A specific option field manage the different steps of a sequential transfer
00097       (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
00098       (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
00099       (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
00100                             and data to transfer without a final stop condition
00101       (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
00102                             and data to transfer without a final stop condition, an then permit a call the same master sequential interface
00103                             several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT())
00104       (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
00105                             and with new data to transfer if the direction change or manage only the new data to transfer
00106                             if no direction change and without a final stop condition in both cases
00107       (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
00108                             and with new data to transfer if the direction change or manage only the new data to transfer
00109                             if no direction change and with a final stop condition in both cases
00110
00111       (+) Differents sequential I2C interfaces are listed below:
00112       (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
00113       (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
00114            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
00115       (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
00116       (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
00117            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
00118       (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00119       (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
00120            add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00121       (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
00122       (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
00123            add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
00124       (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
00125            add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
00126       (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
00127       (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
00128            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
00129       (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
00130       (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
00131            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
00132       (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00133            add his own code by customization of function pointer HAL_I2C_ErrorCallback()
00134       (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00135       (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
00136            add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00137       (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
00138            This action will inform Master to generate a Stop condition to discard the communication.
00139
00140     *** Interrupt mode IO MEM operation ***
00141     =======================================
00142     [..]
00143       (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
00144           HAL_I2C_Mem_Write_IT()
00145       (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
00146            add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
00147       (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
00148           HAL_I2C_Mem_Read_IT()
00149       (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
00150            add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
00151       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00152            add his own code by customization of function pointer HAL_I2C_ErrorCallback()
00153
00154     *** DMA mode IO operation ***
00155     ==============================
00156     [..]
00157       (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
00158           HAL_I2C_Master_Transmit_DMA()
00159       (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
00160            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
00161       (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
00162           HAL_I2C_Master_Receive_DMA()
00163       (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
00164            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
00165       (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
00166           HAL_I2C_Slave_Transmit_DMA()
00167       (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
00168            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
00169       (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
00170           HAL_I2C_Slave_Receive_DMA()
00171       (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
00172            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
00173       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00174            add his own code by customization of function pointer HAL_I2C_ErrorCallback()
00175       (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00176       (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
00177            add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00178       (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
00179            This action will inform Master to generate a Stop condition to discard the communication.
00180
00181     *** DMA mode IO MEM operation ***
00182     =================================
00183     [..]
00184       (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
00185           HAL_I2C_Mem_Write_DMA()
00186       (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
00187            add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
00188       (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
00189           HAL_I2C_Mem_Read_DMA()
00190       (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
00191            add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
00192       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00193            add his own code by customization of function pointer HAL_I2C_ErrorCallback()
00194
00195
00196      *** I2C HAL driver macros list ***
00197      ==================================
00198      [..]
00199        Below the list of most used macros in I2C HAL driver.
00200
00201       (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
00202       (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
00203       (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
00204       (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
00205       (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
00206       (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
00207       (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
00208
00209      [..]
00210        (@) You can refer to the I2C HAL driver header file for more useful macros
00211
00212   @endverbatim
00213   ******************************************************************************
00214   * @attention
00215   *
00216   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00217   *
00218   * Redistribution and use in source and binary forms, with or without modification,
00219   * are permitted provided that the following conditions are met:
00220   *   1. Redistributions of source code must retain the above copyright notice,
00221   *      this list of conditions and the following disclaimer.
00222   *   2. Redistributions in binary form must reproduce the above copyright notice,
00223   *      this list of conditions and the following disclaimer in the documentation
00224   *      and/or other materials provided with the distribution.
00225   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00226   *      may be used to endorse or promote products derived from this software
00227   *      without specific prior written permission.
00228   *
00229   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00230   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00231   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00232   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00233   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00234   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00235   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00236   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00237   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00238   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00239   *
00240   ******************************************************************************
00241   */
00242
00243 /* Includes ------------------------------------------------------------------*/
00244 #include "stm32h7xx_hal.h"
00245
00246 /** @addtogroup STM32H7xx_HAL_Driver
00247   * @{
00248   */
00249
00250 /** @defgroup I2C I2C
00251   * @brief I2C HAL module driver
00252   * @{
00253   */
00254
00255 #ifdef HAL_I2C_MODULE_ENABLED
00256
00257 /* Private typedef -----------------------------------------------------------*/
00258 /* Private define ------------------------------------------------------------*/
00259
00260 /** @defgroup I2C_Private_Define I2C Private Define
00261   * @{
00262   */
00263 #define TIMING_CLEAR_MASK   ((uint32_t)0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */
00264 #define I2C_TIMEOUT_ADDR    ((uint32_t)10000U)       /*!< 10 s  */
00265 #define I2C_TIMEOUT_BUSY    ((uint32_t)25U)          /*!< 25 ms */
00266 #define I2C_TIMEOUT_DIR     ((uint32_t)25U)          /*!< 25 ms */
00267 #define I2C_TIMEOUT_RXNE    ((uint32_t)25U)          /*!< 25 ms */
00268 #define I2C_TIMEOUT_STOPF   ((uint32_t)25U)          /*!< 25 ms */
00269 #define I2C_TIMEOUT_TC      ((uint32_t)25U)          /*!< 25 ms */
00270 #define I2C_TIMEOUT_TCR     ((uint32_t)25U)          /*!< 25 ms */
00271 #define I2C_TIMEOUT_TXIS    ((uint32_t)25U)          /*!< 25 ms */
00272 #define I2C_TIMEOUT_FLAG    ((uint32_t)25U)          /*!< 25 ms */
00273
00274 #define MAX_NBYTE_SIZE      255U
00275 #define SlaveAddr_SHIFT     7U
00276 #define SlaveAddr_MSK       0x06U
00277
00278 /* Private define for @ref PreviousState usage */
00279 #define I2C_STATE_MSK             ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits            */
00280 #define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */
00281 #define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
00282 #define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
00283 #define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
00284 #define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
00285 #define I2C_STATE_MEM_BUSY_TX     ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))               /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
00286 #define I2C_STATE_MEM_BUSY_RX     ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))               /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
00287
00288
00289 /* Private define to centralize the enable/disable of Interrupts */
00290 #define I2C_XFER_TX_IT          ((uint32_t)0x00000001U)
00291 #define I2C_XFER_RX_IT          ((uint32_t)0x00000002U)
00292 #define I2C_XFER_LISTEN_IT      ((uint32_t)0x00000004U)
00293
00294 #define I2C_XFER_ERROR_IT       ((uint32_t)0x00000011U)
00295 #define I2C_XFER_CPLT_IT        ((uint32_t)0x00000012U)
00296 #define I2C_XFER_RELOAD_IT      ((uint32_t)0x00000012U)
00297 /**
00298   * @}
00299   */
00300
00301 /* Private macro -------------------------------------------------------------*/
00302 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) (((__HANDLE__)->Instance == I2C4)?                                                  \
00303                                              ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ?                                \
00304                                               ((uint32_t)(((BDMA_Channel_TypeDef *)(__HANDLE__)->hdmatx->Instance)->CNDTR)) :  \
00305                                               ((uint32_t)(((BDMA_Channel_TypeDef *)(__HANDLE__)->hdmarx->Instance)->CNDTR))) : \
00306                                              ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ?                                \
00307                                               ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmatx->Instance)->NDTR)) :   \
00308                                               ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmarx->Instance)->NDTR))))
00309
00310 /* Private variables ---------------------------------------------------------*/
00311 /* Private function prototypes -----------------------------------------------*/
00312
00313 /** @defgroup I2C_Private_Functions I2C Private Functions
00314   * @{
00315   */
00316 /* Private functions to handle DMA transfer */
00317 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
00318 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
00319 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
00320 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
00321 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
00322 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
00323
00324 /* Private functions to handle IT transfer */
00325 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00326 static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c);
00327 static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c);
00328 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00329 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00330 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00331 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
00332
00333 /* Private functions to handle IT transfer */
00334 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
00335 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
00336
00337 /* Private functions for I2C transfer IRQ handler */
00338 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00339 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00340 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00341 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00342
00343 /* Private functions to handle flags during polling transfer */
00344 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
00345 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00346 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00347 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00348 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00349
00350 /* Private functions to centralize the enable/disable of Interrupts */
00351 static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
00352 static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
00353
00354 /* Private functions to flush TXDR register */
00355 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
00356
00357 /* Private functions to handle  start, restart or stop a transfer */
00358 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
00359 /**
00360   * @}
00361   */
00362
00363 /* Exported functions --------------------------------------------------------*/
00364
00365 /** @defgroup I2C_Exported_Functions I2C Exported Functions
00366   * @{
00367   */
00368
00369 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
00370  *  @brief    Initialization and Configuration functions
00371  *
00372 @verbatim
00373  ===============================================================================
00374               ##### Initialization and de-initialization functions #####
00375  ===============================================================================
00376     [..]  This subsection provides a set of functions allowing to initialize and
00377           deinitialize the I2Cx peripheral:
00378
00379       (+) User must Implement HAL_I2C_MspInit() function in which he configures
00380           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00381
00382       (+) Call the function HAL_I2C_Init() to configure the selected device with
00383           the selected configuration:
00384         (++) Clock Timing
00385         (++) Own Address 1
00386         (++) Addressing mode (Master, Slave)
00387         (++) Dual Addressing mode
00388         (++) Own Address 2
00389         (++) Own Address 2 Mask
00390         (++) General call mode
00391         (++) Nostretch mode
00392
00393       (+) Call the function HAL_I2C_DeInit() to restore the default configuration
00394           of the selected I2Cx peripheral.
00395
00396 @endverbatim
00397   * @{
00398   */
00399
00400 /**
00401   * @brief  Initializes the I2C according to the specified parameters
00402   *         in the I2C_InitTypeDef and initialize the associated handle.
00403   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
00404   *               the configuration information for the specified I2C.
00405   * @retval HAL status
00406   */
00407 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
00408 {
00409   /* Check the I2C handle allocation */
00410   if(hi2c == NULL)
00411   {
00412     return HAL_ERROR;
00413   }
00414
00415   /* Check the parameters */
00416   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00417   assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
00418   assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
00419   assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
00420   assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
00421   assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
00422   assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
00423   assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
00424
00425   if(hi2c->State == HAL_I2C_STATE_RESET)
00426   {
00427     /* Allocate lock resource and initialize it */
00428     hi2c->Lock = HAL_UNLOCKED;
00429
00430     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00431     HAL_I2C_MspInit(hi2c);
00432   }
00433
00434   hi2c->State = HAL_I2C_STATE_BUSY;
00435
00436   /* Disable the selected I2C peripheral */
00437   __HAL_I2C_DISABLE(hi2c);
00438
00439   /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
00440   /* Configure I2Cx: Frequency range */
00441   hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
00442
00443   /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
00444   /* Disable Own Address1 before set the Own Address1 configuration */
00445   hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
00446
00447   /* Configure I2Cx: Own Address1 and ack own address1 mode */
00448   if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
00449   {
00450     hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
00451   }
00452   else /* I2C_ADDRESSINGMODE_10BIT */
00453   {
00454     hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
00455   }
00456
00457   /*---------------------------- I2Cx CR2 Configuration ----------------------*/
00458   /* Configure I2Cx: Addressing Master mode */
00459   if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
00460   {
00461     hi2c->Instance->CR2 = (I2C_CR2_ADD10);
00462   }
00463   /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
00464   hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
00465
00466   /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
00467   /* Disable Own Address2 before set the Own Address2 configuration */
00468   hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
00469
00470   /* Configure I2Cx: Dual mode and Own Address2 */
00471   hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
00472
00473   /*---------------------------- I2Cx CR1 Configuration ----------------------*/
00474   /* Configure I2Cx: Generalcall and NoStretch mode */
00475   hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
00476
00477   /* Enable the selected I2C peripheral */
00478   __HAL_I2C_ENABLE(hi2c);
00479
00480   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00481   hi2c->State = HAL_I2C_STATE_READY;
00482   hi2c->PreviousState = I2C_STATE_NONE;
00483   hi2c->Mode = HAL_I2C_MODE_NONE;
00484
00485   return HAL_OK;
00486 }
00487
00488 /**
00489   * @brief  DeInitialize the I2C peripheral.
00490   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
00491   *               the configuration information for the specified I2C.
00492   * @retval HAL status
00493   */
00494 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
00495 {
00496   /* Check the I2C handle allocation */
00497   if(hi2c == NULL)
00498   {
00499     return HAL_ERROR;
00500   }
00501
00502   /* Check the parameters */
00503   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00504
00505   hi2c->State = HAL_I2C_STATE_BUSY;
00506
00507   /* Disable the I2C Peripheral Clock */
00508   __HAL_I2C_DISABLE(hi2c);
00509
00510   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00511   HAL_I2C_MspDeInit(hi2c);
00512
00513   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00514   hi2c->State = HAL_I2C_STATE_RESET;
00515   hi2c->PreviousState = I2C_STATE_NONE;
00516   hi2c->Mode = HAL_I2C_MODE_NONE;
00517
00518   /* Release Lock */
00519   __HAL_UNLOCK(hi2c);
00520
00521   return HAL_OK;
00522 }
00523
00524 /**
00525   * @brief Initialize the I2C MSP.
00526   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
00527   *               the configuration information for the specified I2C.
00528   * @retval None
00529   */
00530 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
00531 {
00532   /* Prevent unused argument(s) compilation warning */
00533   UNUSED(hi2c);
00534
00535   /* NOTE : This function should not be modified, when the callback is needed,
00536             the HAL_I2C_MspInit could be implemented in the user file
00537    */
00538 }
00539
00540 /**
00541   * @brief DeInitialize the I2C MSP.
00542   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
00543   *               the configuration information for the specified I2C.
00544   * @retval None
00545   */
00546 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
00547 {
00548   /* Prevent unused argument(s) compilation warning */
00549   UNUSED(hi2c);
00550
00551   /* NOTE : This function should not be modified, when the callback is needed,
00552             the HAL_I2C_MspDeInit could be implemented in the user file
00553    */
00554 }
00555
00556 /**
00557   * @}
00558   */
00559
00560 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
00561  *  @brief   Data transfers functions
00562  *
00563 @verbatim
00564  ===============================================================================
00565                       ##### IO operation functions #####
00566  ===============================================================================
00567     [..]
00568     This subsection provides a set of functions allowing to manage the I2C data
00569     transfers.
00570
00571     (#) There are two modes of transfer:
00572        (++) Blocking mode : The communication is performed in the polling mode.
00573             The status of all data processing is returned by the same function
00574             after finishing transfer.
00575        (++) No-Blocking mode : The communication is performed using Interrupts
00576             or DMA. These functions return the status of the transfer startup.
00577             The end of the data processing will be indicated through the
00578             dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
00579             using DMA mode.
00580
00581     (#) Blocking mode functions are :
00582         (++) HAL_I2C_Master_Transmit()
00583         (++) HAL_I2C_Master_Receive()
00584         (++) HAL_I2C_Slave_Transmit()
00585         (++) HAL_I2C_Slave_Receive()
00586         (++) HAL_I2C_Mem_Write()
00587         (++) HAL_I2C_Mem_Read()
00588         (++) HAL_I2C_IsDeviceReady()
00589
00590     (#) No-Blocking mode functions with Interrupt are :
00591         (++) HAL_I2C_Master_Transmit_IT()
00592         (++) HAL_I2C_Master_Receive_IT()
00593         (++) HAL_I2C_Slave_Transmit_IT()
00594         (++) HAL_I2C_Slave_Receive_IT()
00595         (++) HAL_I2C_Mem_Write_IT()
00596         (++) HAL_I2C_Mem_Read_IT()
00597
00598     (#) No-Blocking mode functions with DMA are :
00599         (++) HAL_I2C_Master_Transmit_DMA()
00600         (++) HAL_I2C_Master_Receive_DMA()
00601         (++) HAL_I2C_Slave_Transmit_DMA()
00602         (++) HAL_I2C_Slave_Receive_DMA()
00603         (++) HAL_I2C_Mem_Write_DMA()
00604         (++) HAL_I2C_Mem_Read_DMA()
00605
00606     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00607         (++) HAL_I2C_MemTxCpltCallback()
00608         (++) HAL_I2C_MemRxCpltCallback()
00609         (++) HAL_I2C_MasterTxCpltCallback()
00610         (++) HAL_I2C_MasterRxCpltCallback()
00611         (++) HAL_I2C_SlaveTxCpltCallback()
00612         (++) HAL_I2C_SlaveRxCpltCallback()
00613         (++) HAL_I2C_ErrorCallback()
00614
00615 @endverbatim
00616   * @{
00617   */
00618
00619 /**
00620   * @brief  Transmits in master mode an amount of data in blocking mode.
00621   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
00622   *               the configuration information for the specified I2C.
00623   * @param  DevAddress: Target device address
00624   * @param  pData: Pointer to data buffer
00625   * @param  Size: Amount of data to be sent
00626   * @param  Timeout: Timeout duration
00627   * @retval HAL status
00628   */
00629 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00630 {
00631   uint32_t tickstart = 0U;
00632
00633   if(hi2c->State == HAL_I2C_STATE_READY)
00634   {
00635     /* Process Locked */
00636     __HAL_LOCK(hi2c);
00637
00638     /* Init tickstart for timeout management*/
00639     tickstart = HAL_GetTick();
00640
00641     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
00642     {
00643       return HAL_TIMEOUT;
00644     }
00645
00646     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
00647     hi2c->Mode      = HAL_I2C_MODE_MASTER;
00648     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00649
00650     /* Prepare transfer parameters */
00651     hi2c->pBuffPtr  = pData;
00652     hi2c->XferCount = Size;
00653     hi2c->XferISR   = NULL;
00654
00655     /* Send Slave Address */
00656     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
00657     if(hi2c->XferCount > MAX_NBYTE_SIZE)
00658     {
00659       hi2c->XferSize = MAX_NBYTE_SIZE;
00660       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
00661     }
00662     else
00663     {
00664       hi2c->XferSize = hi2c->XferCount;
00665       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
00666     }
00667
00668     while(hi2c->XferCount > 0U)
00669     {
00670       /* Wait until TXIS flag is set */
00671       if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00672       {
00673         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00674         {
00675           return HAL_ERROR;
00676         }
00677         else
00678         {
00679           return HAL_TIMEOUT;
00680         }
00681       }
00682       /* Write data to TXDR */
00683       hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
00684       hi2c->XferCount--;
00685       hi2c->XferSize--;
00686
00687       if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U))
00688       {
00689         /* Wait until TCR flag is set */
00690         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
00691         {
00692           return HAL_TIMEOUT;
00693         }
00694
00695         if(hi2c->XferCount > MAX_NBYTE_SIZE)
00696         {
00697           hi2c->XferSize = MAX_NBYTE_SIZE;
00698           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
00699         }
00700         else
00701         {
00702           hi2c->XferSize = hi2c->XferCount;
00703           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
00704         }
00705       }
00706     }
00707
00708     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
00709     /* Wait until STOPF flag is set */
00710     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00711     {
00712       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00713       {
00714         return HAL_ERROR;
00715       }
00716       else
00717       {
00718         return HAL_TIMEOUT;
00719       }
00720     }
00721
00722     /* Clear STOP Flag */
00723     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
00724
00725     /* Clear Configuration Register 2 */
00726     I2C_RESET_CR2(hi2c);
00727
00728     hi2c->State = HAL_I2C_STATE_READY;
00729     hi2c->Mode  = HAL_I2C_MODE_NONE;
00730
00731     /* Process Unlocked */
00732     __HAL_UNLOCK(hi2c);
00733
00734     return HAL_OK;
00735   }
00736   else
00737   {
00738     return HAL_BUSY;
00739   }
00740 }
00741
00742 /**
00743   * @brief  Receives in master mode an amount of data in blocking mode.
00744   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
00745   *               the configuration information for the specified I2C.
00746   * @param  DevAddress: Target device address
00747   * @param  pData: Pointer to data buffer
00748   * @param  Size: Amount of data to be sent
00749   * @param  Timeout: Timeout duration
00750   * @retval HAL status
00751   */
00752 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00753 {
00754   uint32_t tickstart = 0U;
00755
00756   if(hi2c->State == HAL_I2C_STATE_READY)
00757   {
00758     /* Process Locked */
00759     __HAL_LOCK(hi2c);
00760
00761     /* Init tickstart for timeout management*/
00762     tickstart = HAL_GetTick();
00763
00764     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
00765     {
00766       return HAL_TIMEOUT;
00767     }
00768
00769     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
00770     hi2c->Mode      = HAL_I2C_MODE_MASTER;
00771     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00772
00773     /* Prepare transfer parameters */
00774     hi2c->pBuffPtr  = pData;
00775     hi2c->XferCount = Size;
00776     hi2c->XferISR   = NULL;
00777
00778     /* Send Slave Address */
00779     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
00780     if(hi2c->XferCount > MAX_NBYTE_SIZE)
00781     {
00782       hi2c->XferSize = MAX_NBYTE_SIZE;
00783       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
00784     }
00785     else
00786     {
00787       hi2c->XferSize = hi2c->XferCount;
00788       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
00789     }
00790
00791     while(hi2c->XferCount > 0U)
00792     {
00793       /* Wait until RXNE flag is set */
00794       if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00795       {
00796         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00797         {
00798           return HAL_ERROR;
00799         }
00800         else
00801         {
00802           return HAL_TIMEOUT;
00803         }
00804       }
00805
00806       /* Read data from RXDR */
00807       (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
00808       hi2c->XferSize--;
00809       hi2c->XferCount--;
00810
00811       if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
00812       {
00813         /* Wait until TCR flag is set */
00814         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
00815         {
00816           return HAL_TIMEOUT;
00817         }
00818
00819         if(hi2c->XferCount > MAX_NBYTE_SIZE)
00820         {
00821           hi2c->XferSize = MAX_NBYTE_SIZE;
00822           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
00823         }
00824         else
00825         {
00826           hi2c->XferSize = hi2c->XferCount;
00827           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
00828         }
00829       }
00830     }
00831
00832     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
00833     /* Wait until STOPF flag is set */
00834     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00835     {
00836       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00837       {
00838         return HAL_ERROR;
00839       }
00840       else
00841       {
00842         return HAL_TIMEOUT;
00843       }
00844     }
00845
00846     /* Clear STOP Flag */
00847     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
00848
00849     /* Clear Configuration Register 2 */
00850     I2C_RESET_CR2(hi2c);
00851
00852     hi2c->State = HAL_I2C_STATE_READY;
00853     hi2c->Mode  = HAL_I2C_MODE_NONE;
00854
00855     /* Process Unlocked */
00856     __HAL_UNLOCK(hi2c);
00857
00858     return HAL_OK;
00859   }
00860   else
00861   {
00862     return HAL_BUSY;
00863   }
00864 }
00865
00866 /**
00867   * @brief  Transmits in slave mode an amount of data in blocking mode.
00868   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
00869   *               the configuration information for the specified I2C.
00870   * @param  pData: Pointer to data buffer
00871   * @param  Size: Amount of data to be sent
00872   * @param  Timeout: Timeout duration
00873   * @retval HAL status
00874   */
00875 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00876 {
00877   uint32_t tickstart = 0U;
00878
00879   if(hi2c->State == HAL_I2C_STATE_READY)
00880   {
00881     if((pData == NULL) || (Size == 0U))
00882     {
00883       return  HAL_ERROR;
00884     }
00885     /* Process Locked */
00886     __HAL_LOCK(hi2c);
00887
00888     /* Init tickstart for timeout management*/
00889     tickstart = HAL_GetTick();
00890
00891     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
00892     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
00893     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00894
00895     /* Prepare transfer parameters */
00896     hi2c->pBuffPtr  = pData;
00897     hi2c->XferCount = Size;
00898     hi2c->XferISR   = NULL;
00899
00900     /* Enable Address Acknowledge */
00901     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
00902
00903     /* Wait until ADDR flag is set */
00904     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
00905     {
00906       /* Disable Address Acknowledge */
00907       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00908       return HAL_TIMEOUT;
00909     }
00910
00911     /* Clear ADDR flag */
00912     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
00913
00914     /* If 10bit addressing mode is selected */
00915     if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
00916     {
00917       /* Wait until ADDR flag is set */
00918       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
00919       {
00920         /* Disable Address Acknowledge */
00921         hi2c->Instance->CR2 |= I2C_CR2_NACK;
00922         return HAL_TIMEOUT;
00923       }
00924
00925       /* Clear ADDR flag */
00926       __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
00927     }
00928
00929     /* Wait until DIR flag is set Transmitter mode */
00930     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
00931     {
00932       /* Disable Address Acknowledge */
00933       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00934       return HAL_TIMEOUT;
00935     }
00936
00937     while(hi2c->XferCount > 0U)
00938     {
00939       /* Wait until TXIS flag is set */
00940       if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00941       {
00942         /* Disable Address Acknowledge */
00943         hi2c->Instance->CR2 |= I2C_CR2_NACK;
00944
00945         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00946         {
00947           return HAL_ERROR;
00948         }
00949         else
00950         {
00951           return HAL_TIMEOUT;
00952         }
00953       }
00954
00955       /* Write data to TXDR */
00956       hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
00957       hi2c->XferCount--;
00958     }
00959
00960     /* Wait until STOP flag is set */
00961     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00962     {
00963       /* Disable Address Acknowledge */
00964       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00965
00966       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00967       {
00968         /* Normal use case for Transmitter mode */
00969         /* A NACK is generated to confirm the end of transfer */
00970         hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00971       }
00972       else
00973       {
00974         return HAL_TIMEOUT;
00975       }
00976     }
00977
00978     /* Clear STOP flag */
00979     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
00980
00981     /* Wait until BUSY flag is reset */
00982     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
00983     {
00984       /* Disable Address Acknowledge */
00985       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00986       return HAL_TIMEOUT;
00987     }
00988
00989     /* Disable Address Acknowledge */
00990     hi2c->Instance->CR2 |= I2C_CR2_NACK;
00991
00992     hi2c->State = HAL_I2C_STATE_READY;
00993     hi2c->Mode  = HAL_I2C_MODE_NONE;
00994
00995     /* Process Unlocked */
00996     __HAL_UNLOCK(hi2c);
00997
00998     return HAL_OK;
00999   }
01000   else
01001   {
01002     return HAL_BUSY;
01003   }
01004 }
01005
01006 /**
01007   * @brief  Receive in slave mode an amount of data in blocking mode
01008   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
01009   *               the configuration information for the specified I2C.
01010   * @param  pData: Pointer to data buffer
01011   * @param  Size: Amount of data to be sent
01012   * @param  Timeout: Timeout duration
01013   * @retval HAL status
01014   */
01015 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01016 {
01017   uint32_t tickstart = 0U;
01018
01019   if(hi2c->State == HAL_I2C_STATE_READY)
01020   {
01021     if((pData == NULL) || (Size == 0U))
01022     {
01023       return  HAL_ERROR;
01024     }
01025     /* Process Locked */
01026     __HAL_LOCK(hi2c);
01027
01028     /* Init tickstart for timeout management*/
01029     tickstart = HAL_GetTick();
01030
01031     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
01032     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
01033     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01034
01035     /* Prepare transfer parameters */
01036     hi2c->pBuffPtr  = pData;
01037     hi2c->XferCount = Size;
01038     hi2c->XferISR   = NULL;
01039
01040     /* Enable Address Acknowledge */
01041     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01042
01043     /* Wait until ADDR flag is set */
01044     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
01045     {
01046       /* Disable Address Acknowledge */
01047       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01048       return HAL_TIMEOUT;
01049     }
01050
01051     /* Clear ADDR flag */
01052     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
01053
01054     /* Wait until DIR flag is reset Receiver mode */
01055     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
01056     {
01057       /* Disable Address Acknowledge */
01058       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01059       return HAL_TIMEOUT;
01060     }
01061
01062     while(hi2c->XferCount > 0U)
01063     {
01064       /* Wait until RXNE flag is set */
01065       if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01066       {
01067         /* Disable Address Acknowledge */
01068         hi2c->Instance->CR2 |= I2C_CR2_NACK;
01069
01070         /* Store Last receive data if any */
01071         if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
01072         {
01073           /* Read data from RXDR */
01074           (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
01075           hi2c->XferCount--;
01076         }
01077
01078         if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
01079         {
01080           return HAL_TIMEOUT;
01081         }
01082         else
01083         {
01084           return HAL_ERROR;
01085         }
01086       }
01087
01088       /* Read data from RXDR */
01089       (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
01090       hi2c->XferCount--;
01091     }
01092
01093     /* Wait until STOP flag is set */
01094     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01095     {
01096       /* Disable Address Acknowledge */
01097       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01098
01099       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01100       {
01101         return HAL_ERROR;
01102       }
01103       else
01104       {
01105         return HAL_TIMEOUT;
01106       }
01107     }
01108
01109     /* Clear STOP flag */
01110     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
01111
01112     /* Wait until BUSY flag is reset */
01113     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
01114     {
01115       /* Disable Address Acknowledge */
01116       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01117       return HAL_TIMEOUT;
01118     }
01119
01120     /* Disable Address Acknowledge */
01121     hi2c->Instance->CR2 |= I2C_CR2_NACK;
01122
01123     hi2c->State = HAL_I2C_STATE_READY;
01124     hi2c->Mode  = HAL_I2C_MODE_NONE;
01125
01126     /* Process Unlocked */
01127     __HAL_UNLOCK(hi2c);
01128
01129     return HAL_OK;
01130   }
01131   else
01132   {
01133     return HAL_BUSY;
01134   }
01135 }
01136
01137 /**
01138   * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
01139   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
01140   *               the configuration information for the specified I2C.
01141   * @param  DevAddress: Target device address
01142   * @param  pData: Pointer to data buffer
01143   * @param  Size: Amount of data to be sent
01144   * @retval HAL status
01145   */
01146 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01147 {
01148   uint32_t xfermode = 0U;
01149
01150   if(hi2c->State == HAL_I2C_STATE_READY)
01151   {
01152     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01153     {
01154       return HAL_BUSY;
01155     }
01156
01157     /* Process Locked */
01158     __HAL_LOCK(hi2c);
01159
01160     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01161     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01162     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01163
01164     /* Prepare transfer parameters */
01165     hi2c->pBuffPtr    = pData;
01166     hi2c->XferCount   = Size;
01167     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01168     hi2c->XferISR     = I2C_Master_ISR_IT;
01169
01170     if(hi2c->XferCount > MAX_NBYTE_SIZE)
01171     {
01172       hi2c->XferSize = MAX_NBYTE_SIZE;
01173       xfermode = I2C_RELOAD_MODE;
01174     }
01175     else
01176     {
01177       hi2c->XferSize = hi2c->XferCount;
01178       xfermode = I2C_AUTOEND_MODE;
01179     }
01180
01181     /* Send Slave Address */
01182     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
01183     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
01184
01185     /* Process Unlocked */
01186     __HAL_UNLOCK(hi2c);
01187
01188     /* Note : The I2C interrupts must be enabled after unlocking current process
01189               to avoid the risk of I2C interrupt handle execution before current
01190               process unlock */
01191
01192     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01193     /* possible to enable all of these */
01194     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01195     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
01196
01197     return HAL_OK;
01198   }
01199   else
01200   {
01201     return HAL_BUSY;
01202   }
01203 }
01204
01205 /**
01206   * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
01207   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
01208   *               the configuration information for the specified I2C.
01209   * @param  DevAddress: Target device address
01210   * @param  pData: Pointer to data buffer
01211   * @param  Size: Amount of data to be sent
01212   * @retval HAL status
01213   */
01214 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01215 {
01216   uint32_t xfermode = 0U;
01217
01218   if(hi2c->State == HAL_I2C_STATE_READY)
01219   {
01220     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01221     {
01222       return HAL_BUSY;
01223     }
01224
01225     /* Process Locked */
01226     __HAL_LOCK(hi2c);
01227
01228     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01229     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01230     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01231
01232     /* Prepare transfer parameters */
01233     hi2c->pBuffPtr    = pData;
01234     hi2c->XferCount   = Size;
01235     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01236     hi2c->XferISR     = I2C_Master_ISR_IT;
01237
01238     if(hi2c->XferCount > MAX_NBYTE_SIZE)
01239     {
01240       hi2c->XferSize = MAX_NBYTE_SIZE;
01241       xfermode = I2C_RELOAD_MODE;
01242     }
01243     else
01244     {
01245       hi2c->XferSize = hi2c->XferCount;
01246       xfermode = I2C_AUTOEND_MODE;
01247     }
01248
01249     /* Send Slave Address */
01250     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
01251     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
01252
01253     /* Process Unlocked */
01254     __HAL_UNLOCK(hi2c);
01255
01256     /* Note : The I2C interrupts must be enabled after unlocking current process
01257               to avoid the risk of I2C interrupt handle execution before current
01258               process unlock */
01259
01260     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01261     /* possible to enable all of these */
01262     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01263     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
01264
01265     return HAL_OK;
01266   }
01267   else
01268   {
01269     return HAL_BUSY;
01270   }
01271 }
01272
01273 /**
01274   * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
01275   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
01276   *               the configuration information for the specified I2C.
01277   * @param  pData: Pointer to data buffer
01278   * @param  Size: Amount of data to be sent
01279   * @retval HAL status
01280   */
01281 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01282 {
01283   if(hi2c->State == HAL_I2C_STATE_READY)
01284   {
01285     /* Process Locked */
01286     __HAL_LOCK(hi2c);
01287
01288     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01289     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01290     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01291
01292     /* Enable Address Acknowledge */
01293     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01294
01295     /* Prepare transfer parameters */
01296     hi2c->pBuffPtr    = pData;
01297     hi2c->XferCount   = Size;
01298     hi2c->XferSize    = hi2c->XferCount;
01299     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01300     hi2c->XferISR     = I2C_Slave_ISR_IT;
01301
01302     /* Process Unlocked */
01303     __HAL_UNLOCK(hi2c);
01304
01305     /* Note : The I2C interrupts must be enabled after unlocking current process
01306               to avoid the risk of I2C interrupt handle execution before current
01307               process unlock */
01308
01309     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01310     /* possible to enable all of these */
01311     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01312     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
01313
01314     return HAL_OK;
01315   }
01316   else
01317   {
01318     return HAL_BUSY;
01319   }
01320 }
01321
01322 /**
01323   * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
01324   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
01325   *               the configuration information for the specified I2C.
01326   * @param  pData: Pointer to data buffer
01327   * @param  Size: Amount of data to be sent
01328   * @retval HAL status
01329   */
01330 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01331 {
01332   if(hi2c->State == HAL_I2C_STATE_READY)
01333   {
01334     /* Process Locked */
01335     __HAL_LOCK(hi2c);
01336
01337     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01338     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01339     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01340
01341     /* Enable Address Acknowledge */
01342     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01343
01344     /* Prepare transfer parameters */
01345     hi2c->pBuffPtr    = pData;
01346     hi2c->XferCount   = Size;
01347     hi2c->XferSize    = hi2c->XferCount;
01348     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01349     hi2c->XferISR     = I2C_Slave_ISR_IT;
01350
01351     /* Process Unlocked */
01352     __HAL_UNLOCK(hi2c);
01353
01354     /* Note : The I2C interrupts must be enabled after unlocking current process
01355               to avoid the risk of I2C interrupt handle execution before current
01356               process unlock */
01357
01358     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01359     /* possible to enable all of these */
01360     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01361     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
01362
01363     return HAL_OK;
01364   }
01365   else
01366   {
01367     return HAL_BUSY;
01368   }
01369 }
01370
01371 /**
01372   * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
01373   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
01374   *               the configuration information for the specified I2C.
01375   * @param  DevAddress: Target device address
01376   * @param  pData: Pointer to data buffer
01377   * @param  Size: Amount of data to be sent
01378   * @retval HAL status
01379   */
01380 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01381 {
01382   uint32_t xfermode = 0U;
01383
01384   if(hi2c->State == HAL_I2C_STATE_READY)
01385   {
01386     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01387     {
01388       return HAL_BUSY;
01389     }
01390
01391     /* Process Locked */
01392     __HAL_LOCK(hi2c);
01393
01394     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01395     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01396     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01397
01398     /* Prepare transfer parameters */
01399     hi2c->pBuffPtr    = pData;
01400     hi2c->XferCount   = Size;
01401     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01402     hi2c->XferISR     = I2C_Master_ISR_DMA;
01403
01404     if(hi2c->XferCount > MAX_NBYTE_SIZE)
01405     {
01406       hi2c->XferSize = MAX_NBYTE_SIZE;
01407       xfermode = I2C_RELOAD_MODE;
01408     }
01409     else
01410     {
01411       hi2c->XferSize = hi2c->XferCount;
01412       xfermode = I2C_AUTOEND_MODE;
01413     }
01414
01415     if(hi2c->XferSize > 0U)
01416     {
01417       /* Set the I2C DMA transfer complete callback */
01418       hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
01419
01420       /* Set the DMA error callback */
01421       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
01422
01423       /* Set the unused DMA callbacks to NULL */
01424       hi2c->hdmatx->XferHalfCpltCallback = NULL;
01425       hi2c->hdmatx->XferAbortCallback = NULL;
01426
01427       /* Enable the DMA channel */
01428       HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
01429
01430       /* Send Slave Address */
01431       /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01432       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
01433
01434       /* Update XferCount value */
01435       hi2c->XferCount -= hi2c->XferSize;
01436
01437       /* Process Unlocked */
01438       __HAL_UNLOCK(hi2c);
01439
01440       /* Note : The I2C interrupts must be enabled after unlocking current process
01441                 to avoid the risk of I2C interrupt handle execution before current
01442                 process unlock */
01443       /* Enable ERR and NACK interrupts */
01444       I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
01445
01446       /* Enable DMA Request */
01447       hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
01448     }
01449     else
01450     {
01451       /* Update Transfer ISR function pointer */
01452       hi2c->XferISR = I2C_Master_ISR_IT;
01453
01454       /* Send Slave Address */
01455       /* Set NBYTES to write and generate START condition */
01456       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
01457
01458       /* Process Unlocked */
01459       __HAL_UNLOCK(hi2c);
01460
01461       /* Note : The I2C interrupts must be enabled after unlocking current process
01462                 to avoid the risk of I2C interrupt handle execution before current
01463                 process unlock */
01464       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01465       /* possible to enable all of these */
01466       /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01467       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
01468     }
01469
01470     return HAL_OK;
01471   }
01472   else
01473   {
01474     return HAL_BUSY;
01475   }
01476 }
01477
01478 /**
01479   * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
01480   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
01481   *               the configuration information for the specified I2C.
01482   * @param  DevAddress: Target device address
01483   * @param  pData: Pointer to data buffer
01484   * @param  Size: Amount of data to be sent
01485   * @retval HAL status
01486   */
01487 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01488 {
01489   uint32_t xfermode = 0U;
01490
01491   if(hi2c->State == HAL_I2C_STATE_READY)
01492   {
01493     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01494     {
01495       return HAL_BUSY;
01496     }
01497
01498     /* Process Locked */
01499     __HAL_LOCK(hi2c);
01500
01501     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01502     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01503     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01504
01505     /* Prepare transfer parameters */
01506     hi2c->pBuffPtr    = pData;
01507     hi2c->XferCount   = Size;
01508     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01509     hi2c->XferISR     = I2C_Master_ISR_DMA;
01510
01511     if(hi2c->XferCount > MAX_NBYTE_SIZE)
01512     {
01513       hi2c->XferSize = MAX_NBYTE_SIZE;
01514       xfermode = I2C_RELOAD_MODE;
01515     }
01516     else
01517     {
01518       hi2c->XferSize = hi2c->XferCount;
01519       xfermode = I2C_AUTOEND_MODE;
01520     }
01521
01522     if(hi2c->XferSize > 0U)
01523     {
01524       /* Set the I2C DMA transfer complete callback */
01525       hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
01526
01527       /* Set the DMA error callback */
01528       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
01529
01530       /* Set the unused DMA callbacks to NULL */
01531       hi2c->hdmarx->XferHalfCpltCallback = NULL;
01532       hi2c->hdmarx->XferAbortCallback = NULL;
01533
01534       /* Enable the DMA channel */
01535       HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
01536
01537       /* Send Slave Address */
01538       /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01539       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
01540
01541       /* Update XferCount value */
01542       hi2c->XferCount -= hi2c->XferSize;
01543
01544       /* Process Unlocked */
01545       __HAL_UNLOCK(hi2c);
01546
01547       /* Note : The I2C interrupts must be enabled after unlocking current process
01548                 to avoid the risk of I2C interrupt handle execution before current
01549                 process unlock */
01550       /* Enable ERR and NACK interrupts */
01551       I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
01552
01553       /* Enable DMA Request */
01554       hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
01555     }
01556     else
01557     {
01558       /* Update Transfer ISR function pointer */
01559       hi2c->XferISR = I2C_Master_ISR_IT;
01560
01561       /* Send Slave Address */
01562       /* Set NBYTES to read and generate START condition */
01563       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
01564
01565       /* Process Unlocked */
01566       __HAL_UNLOCK(hi2c);
01567
01568       /* Note : The I2C interrupts must be enabled after unlocking current process
01569                 to avoid the risk of I2C interrupt handle execution before current
01570                 process unlock */
01571       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01572       /* possible to enable all of these */
01573       /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01574       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
01575     }
01576     return HAL_OK;
01577   }
01578   else
01579   {
01580     return HAL_BUSY;
01581   }
01582 }
01583
01584 /**
01585   * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
01586   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
01587   *               the configuration information for the specified I2C.
01588   * @param  pData: Pointer to data buffer
01589   * @param  Size: Amount of data to be sent
01590   * @retval HAL status
01591   */
01592 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01593 {
01594   if(hi2c->State == HAL_I2C_STATE_READY)
01595   {
01596     if((pData == NULL) || (Size == 0U))
01597     {
01598       return  HAL_ERROR;
01599     }
01600     /* Process Locked */
01601     __HAL_LOCK(hi2c);
01602
01603     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01604     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01605     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01606
01607     /* Prepare transfer parameters */
01608     hi2c->pBuffPtr    = pData;
01609     hi2c->XferCount   = Size;
01610     hi2c->XferSize    = hi2c->XferCount;
01611     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01612     hi2c->XferISR     = I2C_Slave_ISR_DMA;
01613
01614     /* Set the I2C DMA transfer complete callback */
01615     hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
01616
01617     /* Set the DMA error callback */
01618     hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
01619
01620     /* Set the unused DMA callbacks to NULL */
01621     hi2c->hdmatx->XferHalfCpltCallback = NULL;
01622     hi2c->hdmatx->XferAbortCallback = NULL;
01623
01624     /* Enable the DMA channel */
01625     HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
01626
01627     /* Enable Address Acknowledge */
01628     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01629
01630     /* Process Unlocked */
01631     __HAL_UNLOCK(hi2c);
01632
01633     /* Note : The I2C interrupts must be enabled after unlocking current process
01634               to avoid the risk of I2C interrupt handle execution before current
01635               process unlock */
01636     /* Enable ERR, STOP, NACK, ADDR interrupts */
01637     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
01638
01639     /* Enable DMA Request */
01640     hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
01641
01642     return HAL_OK;
01643   }
01644   else
01645   {
01646     return HAL_BUSY;
01647   }
01648 }
01649
01650 /**
01651   * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
01652   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
01653   *               the configuration information for the specified I2C.
01654   * @param  pData: Pointer to data buffer
01655   * @param  Size: Amount of data to be sent
01656   * @retval HAL status
01657   */
01658 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01659 {
01660   if(hi2c->State == HAL_I2C_STATE_READY)
01661   {
01662     if((pData == NULL) || (Size == 0U))
01663     {
01664       return  HAL_ERROR;
01665     }
01666     /* Process Locked */
01667     __HAL_LOCK(hi2c);
01668
01669     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01670     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01671     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01672
01673     /* Prepare transfer parameters */
01674     hi2c->pBuffPtr    = pData;
01675     hi2c->XferCount   = Size;
01676     hi2c->XferSize    = hi2c->XferCount;
01677     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01678     hi2c->XferISR     = I2C_Slave_ISR_DMA;
01679
01680     /* Set the I2C DMA transfer complete callback */
01681     hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
01682
01683     /* Set the DMA error callback */
01684     hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
01685
01686     /* Set the unused DMA callbacks to NULL */
01687     hi2c->hdmarx->XferHalfCpltCallback = NULL;
01688     hi2c->hdmarx->XferAbortCallback = NULL;
01689
01690     /* Enable the DMA channel */
01691     HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
01692
01693     /* Enable Address Acknowledge */
01694     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01695
01696     /* Process Unlocked */
01697     __HAL_UNLOCK(hi2c);
01698
01699     /* Note : The I2C interrupts must be enabled after unlocking current process
01700               to avoid the risk of I2C interrupt handle execution before current
01701               process unlock */
01702     /* Enable ERR, STOP, NACK, ADDR interrupts */
01703     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
01704
01705     /* Enable DMA Request */
01706     hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
01707
01708     return HAL_OK;
01709   }
01710   else
01711   {
01712     return HAL_BUSY;
01713   }
01714 }
01715 /**
01716   * @brief  Write an amount of data in blocking mode to a specific memory address
01717   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
01718   *               the configuration information for the specified I2C.
01719   * @param  DevAddress: Target device address
01720   * @param  MemAddress: Internal memory address
01721   * @param  MemAddSize: Size of internal memory address
01722   * @param  pData: Pointer to data buffer
01723   * @param  Size: Amount of data to be sent
01724   * @param  Timeout: Timeout duration
01725   * @retval HAL status
01726   */
01727 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01728 {
01729   uint32_t tickstart = 0U;
01730
01731   /* Check the parameters */
01732   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
01733
01734   if(hi2c->State == HAL_I2C_STATE_READY)
01735   {
01736     if((pData == NULL) || (Size == 0U))
01737     {
01738       return  HAL_ERROR;
01739     }
01740
01741     /* Process Locked */
01742     __HAL_LOCK(hi2c);
01743
01744     /* Init tickstart for timeout management*/
01745     tickstart = HAL_GetTick();
01746
01747     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
01748     {
01749       return HAL_TIMEOUT;
01750     }
01751
01752     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
01753     hi2c->Mode      = HAL_I2C_MODE_MEM;
01754     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01755
01756     /* Prepare transfer parameters */
01757     hi2c->pBuffPtr  = pData;
01758     hi2c->XferCount = Size;
01759     hi2c->XferISR   = NULL;
01760
01761     /* Send Slave Address and Memory Address */
01762     if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
01763     {
01764       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01765       {
01766         /* Process Unlocked */
01767         __HAL_UNLOCK(hi2c);
01768         return HAL_ERROR;
01769       }
01770       else
01771       {
01772         /* Process Unlocked */
01773         __HAL_UNLOCK(hi2c);
01774         return HAL_TIMEOUT;
01775       }
01776     }
01777
01778     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
01779     if(hi2c->XferCount > MAX_NBYTE_SIZE)
01780     {
01781       hi2c->XferSize = MAX_NBYTE_SIZE;
01782       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
01783     }
01784     else
01785     {
01786       hi2c->XferSize = hi2c->XferCount;
01787       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
01788     }
01789
01790     do
01791     {
01792       /* Wait until TXIS flag is set */
01793       if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01794       {
01795         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01796         {
01797           return HAL_ERROR;
01798         }
01799         else
01800         {
01801           return HAL_TIMEOUT;
01802         }
01803       }
01804
01805       /* Write data to TXDR */
01806       hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
01807       hi2c->XferCount--;
01808       hi2c->XferSize--;
01809
01810       if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U))
01811       {
01812         /* Wait until TCR flag is set */
01813         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
01814         {
01815           return HAL_TIMEOUT;
01816         }
01817
01818         if(hi2c->XferCount > MAX_NBYTE_SIZE)
01819         {
01820           hi2c->XferSize = MAX_NBYTE_SIZE;
01821           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
01822         }
01823         else
01824         {
01825           hi2c->XferSize = hi2c->XferCount;
01826           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
01827         }
01828       }
01829
01830     }while(hi2c->XferCount > 0U);
01831
01832     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01833     /* Wait until STOPF flag is reset */
01834     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01835     {
01836       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01837       {
01838         return HAL_ERROR;
01839       }
01840       else
01841       {
01842         return HAL_TIMEOUT;
01843       }
01844     }
01845
01846     /* Clear STOP Flag */
01847     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01848
01849     /* Clear Configuration Register 2 */
01850     I2C_RESET_CR2(hi2c);
01851
01852     hi2c->State = HAL_I2C_STATE_READY;
01853     hi2c->Mode  = HAL_I2C_MODE_NONE;
01854
01855     /* Process Unlocked */
01856     __HAL_UNLOCK(hi2c);
01857
01858     return HAL_OK;
01859   }
01860   else
01861   {
01862     return HAL_BUSY;
01863   }
01864 }
01865
01866 /**
01867   * @brief  Read an amount of data in blocking mode from a specific memory address
01868   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
01869   *               the configuration information for the specified I2C.
01870   * @param  DevAddress: Target device address
01871   * @param  MemAddress: Internal memory address
01872   * @param  MemAddSize: Size of internal memory address
01873   * @param  pData: Pointer to data buffer
01874   * @param  Size: Amount of data to be sent
01875   * @param  Timeout: Timeout duration
01876   * @retval HAL status
01877   */
01878 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01879 {
01880   uint32_t tickstart = 0U;
01881
01882   /* Check the parameters */
01883   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
01884
01885   if(hi2c->State == HAL_I2C_STATE_READY)
01886   {
01887     if((pData == NULL) || (Size == 0U))
01888     {
01889       return  HAL_ERROR;
01890     }
01891
01892     /* Process Locked */
01893     __HAL_LOCK(hi2c);
01894
01895     /* Init tickstart for timeout management*/
01896     tickstart = HAL_GetTick();
01897
01898     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
01899     {
01900       return HAL_TIMEOUT;
01901     }
01902
01903     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
01904     hi2c->Mode      = HAL_I2C_MODE_MEM;
01905     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01906
01907     /* Prepare transfer parameters */
01908     hi2c->pBuffPtr  = pData;
01909     hi2c->XferCount = Size;
01910     hi2c->XferISR   = NULL;
01911
01912     /* Send Slave Address and Memory Address */
01913     if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
01914     {
01915       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01916       {
01917         /* Process Unlocked */
01918         __HAL_UNLOCK(hi2c);
01919         return HAL_ERROR;
01920       }
01921       else
01922       {
01923         /* Process Unlocked */
01924         __HAL_UNLOCK(hi2c);
01925         return HAL_TIMEOUT;
01926       }
01927     }
01928
01929     /* Send Slave Address */
01930     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01931     if(hi2c->XferCount > MAX_NBYTE_SIZE)
01932     {
01933       hi2c->XferSize = MAX_NBYTE_SIZE;
01934       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
01935     }
01936     else
01937     {
01938       hi2c->XferSize = hi2c->XferCount;
01939       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
01940     }
01941
01942     do
01943     {
01944       /* Wait until RXNE flag is set */
01945       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
01946       {
01947         return HAL_TIMEOUT;
01948       }
01949
01950       /* Read data from RXDR */
01951       (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
01952       hi2c->XferSize--;
01953       hi2c->XferCount--;
01954
01955       if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
01956       {
01957         /* Wait until TCR flag is set */
01958         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
01959         {
01960           return HAL_TIMEOUT;
01961         }
01962
01963         if(hi2c->XferCount > MAX_NBYTE_SIZE)
01964         {
01965           hi2c->XferSize = MAX_NBYTE_SIZE;
01966           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
01967         }
01968         else
01969         {
01970           hi2c->XferSize = hi2c->XferCount;
01971           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
01972         }
01973       }
01974     }while(hi2c->XferCount > 0U);
01975
01976     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01977     /* Wait until STOPF flag is reset */
01978     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01979     {
01980       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01981       {
01982         return HAL_ERROR;
01983       }
01984       else
01985       {
01986         return HAL_TIMEOUT;
01987       }
01988     }
01989
01990     /* Clear STOP Flag */
01991     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01992
01993     /* Clear Configuration Register 2 */
01994     I2C_RESET_CR2(hi2c);
01995
01996     hi2c->State = HAL_I2C_STATE_READY;
01997     hi2c->Mode  = HAL_I2C_MODE_NONE;
01998
01999     /* Process Unlocked */
02000     __HAL_UNLOCK(hi2c);
02001
02002     return HAL_OK;
02003   }
02004   else
02005   {
02006     return HAL_BUSY;
02007   }
02008 }
02009 /**
02010   * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
02011   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
02012   *               the configuration information for the specified I2C.
02013   * @param  DevAddress: Target device address
02014   * @param  MemAddress: Internal memory address
02015   * @param  MemAddSize: Size of internal memory address
02016   * @param  pData: Pointer to data buffer
02017   * @param  Size: Amount of data to be sent
02018   * @retval HAL status
02019   */
02020 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02021 {
02022   uint32_t tickstart = 0U;
02023   uint32_t xfermode = 0U;
02024
02025   /* Check the parameters */
02026   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02027
02028   if(hi2c->State == HAL_I2C_STATE_READY)
02029   {
02030     if((pData == NULL) || (Size == 0U))
02031     {
02032       return  HAL_ERROR;
02033     }
02034
02035     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02036     {
02037       return HAL_BUSY;
02038     }
02039
02040     /* Process Locked */
02041     __HAL_LOCK(hi2c);
02042
02043     /* Init tickstart for timeout management*/
02044     tickstart = HAL_GetTick();
02045
02046     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
02047     hi2c->Mode        = HAL_I2C_MODE_MEM;
02048     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02049
02050     /* Prepare transfer parameters */
02051     hi2c->pBuffPtr    = pData;
02052     hi2c->XferCount   = Size;
02053     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02054     hi2c->XferISR     = I2C_Master_ISR_IT;
02055
02056     if(hi2c->XferCount > MAX_NBYTE_SIZE)
02057     {
02058       hi2c->XferSize = MAX_NBYTE_SIZE;
02059       xfermode = I2C_RELOAD_MODE;
02060     }
02061     else
02062     {
02063       hi2c->XferSize = hi2c->XferCount;
02064       xfermode = I2C_AUTOEND_MODE;
02065     }
02066
02067     /* Send Slave Address and Memory Address */
02068     if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02069     {
02070       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02071       {
02072         /* Process Unlocked */
02073         __HAL_UNLOCK(hi2c);
02074         return HAL_ERROR;
02075       }
02076       else
02077       {
02078         /* Process Unlocked */
02079         __HAL_UNLOCK(hi2c);
02080         return HAL_TIMEOUT;
02081       }
02082     }
02083
02084     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02085     I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
02086
02087     /* Process Unlocked */
02088     __HAL_UNLOCK(hi2c);
02089
02090     /* Note : The I2C interrupts must be enabled after unlocking current process
02091               to avoid the risk of I2C interrupt handle execution before current
02092               process unlock */
02093
02094     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
02095     /* possible to enable all of these */
02096     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02097     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
02098
02099     return HAL_OK;
02100   }
02101   else
02102   {
02103     return HAL_BUSY;
02104   }
02105 }
02106
02107 /**
02108   * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
02109   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
02110   *               the configuration information for the specified I2C.
02111   * @param  DevAddress: Target device address
02112   * @param  MemAddress: Internal memory address
02113   * @param  MemAddSize: Size of internal memory address
02114   * @param  pData: Pointer to data buffer
02115   * @param  Size: Amount of data to be sent
02116   * @retval HAL status
02117   */
02118 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02119 {
02120   uint32_t tickstart = 0U;
02121   uint32_t xfermode = 0U;
02122
02123   /* Check the parameters */
02124   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02125
02126   if(hi2c->State == HAL_I2C_STATE_READY)
02127   {
02128     if((pData == NULL) || (Size == 0U))
02129     {
02130       return  HAL_ERROR;
02131     }
02132
02133     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02134     {
02135       return HAL_BUSY;
02136     }
02137
02138     /* Process Locked */
02139     __HAL_LOCK(hi2c);
02140
02141     /* Init tickstart for timeout management*/
02142     tickstart = HAL_GetTick();
02143
02144     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
02145     hi2c->Mode        = HAL_I2C_MODE_MEM;
02146     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02147
02148     /* Prepare transfer parameters */
02149     hi2c->pBuffPtr    = pData;
02150     hi2c->XferCount   = Size;
02151     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02152     hi2c->XferISR     = I2C_Master_ISR_IT;
02153
02154     if(hi2c->XferCount > MAX_NBYTE_SIZE)
02155     {
02156       hi2c->XferSize = MAX_NBYTE_SIZE;
02157       xfermode = I2C_RELOAD_MODE;
02158     }
02159     else
02160     {
02161       hi2c->XferSize = hi2c->XferCount;
02162       xfermode = I2C_AUTOEND_MODE;
02163     }
02164
02165     /* Send Slave Address and Memory Address */
02166     if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02167     {
02168       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02169       {
02170         /* Process Unlocked */
02171         __HAL_UNLOCK(hi2c);
02172         return HAL_ERROR;
02173       }
02174       else
02175       {
02176         /* Process Unlocked */
02177         __HAL_UNLOCK(hi2c);
02178         return HAL_TIMEOUT;
02179       }
02180     }
02181
02182     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02183     I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
02184
02185     /* Process Unlocked */
02186     __HAL_UNLOCK(hi2c);
02187
02188     /* Note : The I2C interrupts must be enabled after unlocking current process
02189               to avoid the risk of I2C interrupt handle execution before current
02190               process unlock */
02191
02192     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
02193     /* possible to enable all of these */
02194     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02195     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
02196
02197     return HAL_OK;
02198   }
02199   else
02200   {
02201     return HAL_BUSY;
02202   }
02203 }
02204 /**
02205   * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
02206   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
02207   *               the configuration information for the specified I2C.
02208   * @param  DevAddress: Target device address
02209   * @param  MemAddress: Internal memory address
02210   * @param  MemAddSize: Size of internal memory address
02211   * @param  pData: Pointer to data buffer
02212   * @param  Size: Amount of data to be sent
02213   * @retval HAL status
02214   */
02215 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02216 {
02217   uint32_t tickstart = 0U;
02218   uint32_t xfermode = 0U;
02219
02220   /* Check the parameters */
02221   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02222
02223   if(hi2c->State == HAL_I2C_STATE_READY)
02224   {
02225     if((pData == NULL) || (Size == 0U))
02226     {
02227       return  HAL_ERROR;
02228     }
02229
02230     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02231     {
02232       return HAL_BUSY;
02233     }
02234
02235     /* Process Locked */
02236     __HAL_LOCK(hi2c);
02237
02238     /* Init tickstart for timeout management*/
02239     tickstart = HAL_GetTick();
02240
02241     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
02242     hi2c->Mode        = HAL_I2C_MODE_MEM;
02243     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02244
02245     /* Prepare transfer parameters */
02246     hi2c->pBuffPtr    = pData;
02247     hi2c->XferCount   = Size;
02248     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02249     hi2c->XferISR     = I2C_Master_ISR_DMA;
02250
02251     if(hi2c->XferCount > MAX_NBYTE_SIZE)
02252     {
02253       hi2c->XferSize = MAX_NBYTE_SIZE;
02254       xfermode = I2C_RELOAD_MODE;
02255     }
02256     else
02257     {
02258       hi2c->XferSize = hi2c->XferCount;
02259       xfermode = I2C_AUTOEND_MODE;
02260     }
02261
02262     /* Send Slave Address and Memory Address */
02263     if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02264     {
02265       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02266       {
02267         /* Process Unlocked */
02268         __HAL_UNLOCK(hi2c);
02269         return HAL_ERROR;
02270       }
02271       else
02272       {
02273         /* Process Unlocked */
02274         __HAL_UNLOCK(hi2c);
02275         return HAL_TIMEOUT;
02276       }
02277     }
02278
02279     /* Set the I2C DMA transfer complete callback */
02280     hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
02281
02282     /* Set the DMA error callback */
02283     hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
02284
02285     /* Set the unused DMA callbacks to NULL */
02286     hi2c->hdmatx->XferHalfCpltCallback = NULL;
02287     hi2c->hdmatx->XferAbortCallback = NULL;
02288
02289     /* Enable the DMA channel */
02290     HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
02291
02292     /* Send Slave Address */
02293     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02294     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
02295
02296     /* Update XferCount value */
02297     hi2c->XferCount -= hi2c->XferSize;
02298
02299     /* Process Unlocked */
02300     __HAL_UNLOCK(hi2c);
02301
02302     /* Note : The I2C interrupts must be enabled after unlocking current process
02303               to avoid the risk of I2C interrupt handle execution before current
02304               process unlock */
02305     /* Enable ERR and NACK interrupts */
02306     I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
02307
02308     /* Enable DMA Request */
02309     hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
02310
02311     return HAL_OK;
02312   }
02313   else
02314   {
02315     return HAL_BUSY;
02316   }
02317 }
02318
02319 /**
02320   * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
02321   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
02322   *               the configuration information for the specified I2C.
02323   * @param  DevAddress: Target device address
02324   * @param  MemAddress: Internal memory address
02325   * @param  MemAddSize: Size of internal memory address
02326   * @param  pData: Pointer to data buffer
02327   * @param  Size: Amount of data to be read
02328   * @retval HAL status
02329   */
02330 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02331 {
02332   uint32_t tickstart = 0U;
02333   uint32_t xfermode = 0U;
02334
02335   /* Check the parameters */
02336   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02337
02338   if(hi2c->State == HAL_I2C_STATE_READY)
02339   {
02340     if((pData == NULL) || (Size == 0U))
02341     {
02342       return  HAL_ERROR;
02343     }
02344
02345     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02346     {
02347       return HAL_BUSY;
02348     }
02349
02350     /* Process Locked */
02351     __HAL_LOCK(hi2c);
02352
02353     /* Init tickstart for timeout management*/
02354     tickstart = HAL_GetTick();
02355
02356     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
02357     hi2c->Mode        = HAL_I2C_MODE_MEM;
02358     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02359
02360     /* Prepare transfer parameters */
02361     hi2c->pBuffPtr    = pData;
02362     hi2c->XferCount   = Size;
02363     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02364     hi2c->XferISR     = I2C_Master_ISR_DMA;
02365
02366     if(hi2c->XferCount > MAX_NBYTE_SIZE)
02367     {
02368       hi2c->XferSize = MAX_NBYTE_SIZE;
02369       xfermode = I2C_RELOAD_MODE;
02370     }
02371     else
02372     {
02373       hi2c->XferSize = hi2c->XferCount;
02374       xfermode = I2C_AUTOEND_MODE;
02375     }
02376
02377     /* Send Slave Address and Memory Address */
02378     if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02379     {
02380       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02381       {
02382         /* Process Unlocked */
02383         __HAL_UNLOCK(hi2c);
02384         return HAL_ERROR;
02385       }
02386       else
02387       {
02388         /* Process Unlocked */
02389         __HAL_UNLOCK(hi2c);
02390         return HAL_TIMEOUT;
02391       }
02392     }
02393
02394     /* Set the I2C DMA transfer complete callback */
02395     hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
02396
02397     /* Set the DMA error callback */
02398     hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
02399
02400     /* Set the unused DMA callbacks to NULL */
02401     hi2c->hdmarx->XferHalfCpltCallback = NULL;
02402     hi2c->hdmarx->XferAbortCallback = NULL;
02403
02404     /* Enable the DMA channel */
02405     HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
02406
02407     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02408     I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
02409
02410     /* Update XferCount value */
02411     hi2c->XferCount -= hi2c->XferSize;
02412
02413     /* Process Unlocked */
02414     __HAL_UNLOCK(hi2c);
02415
02416     /* Enable DMA Request */
02417     hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
02418
02419     /* Note : The I2C interrupts must be enabled after unlocking current process
02420               to avoid the risk of I2C interrupt handle execution before current
02421               process unlock */
02422     /* Enable ERR and NACK interrupts */
02423     I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
02424
02425     return HAL_OK;
02426   }
02427   else
02428   {
02429     return HAL_BUSY;
02430   }
02431 }
02432
02433 /**
02434   * @brief  Checks if target device is ready for communication.
02435   * @note   This function is used with Memory devices
02436   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
02437   *               the configuration information for the specified I2C.
02438   * @param  DevAddress: Target device address
02439   * @param  Trials: Number of trials
02440   * @param  Timeout: Timeout duration
02441   * @retval HAL status
02442   */
02443 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
02444 {
02445   uint32_t tickstart = 0U;
02446
02447   __IO uint32_t I2C_Trials = 0U;
02448
02449   if(hi2c->State == HAL_I2C_STATE_READY)
02450   {
02451     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02452     {
02453       return HAL_BUSY;
02454     }
02455
02456     /* Process Locked */
02457     __HAL_LOCK(hi2c);
02458
02459     hi2c->State = HAL_I2C_STATE_BUSY;
02460     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02461
02462     do
02463     {
02464       /* Generate Start */
02465       hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);
02466
02467       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
02468       /* Wait until STOPF flag is set or a NACK flag is set*/
02469       tickstart = HAL_GetTick();
02470       while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
02471       {
02472         if(Timeout != HAL_MAX_DELAY)
02473         {
02474           if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
02475           {
02476             /* Device is ready */
02477             hi2c->State = HAL_I2C_STATE_READY;
02478             /* Process Unlocked */
02479             __HAL_UNLOCK(hi2c);
02480             return HAL_TIMEOUT;
02481           }
02482         }
02483       }
02484
02485       /* Check if the NACKF flag has not been set */
02486       if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
02487       {
02488         /* Wait until STOPF flag is reset */
02489         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
02490         {
02491           return HAL_TIMEOUT;
02492         }
02493
02494         /* Clear STOP Flag */
02495         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02496
02497         /* Device is ready */
02498         hi2c->State = HAL_I2C_STATE_READY;
02499
02500         /* Process Unlocked */
02501         __HAL_UNLOCK(hi2c);
02502
02503         return HAL_OK;
02504       }
02505       else
02506       {
02507         /* Wait until STOPF flag is reset */
02508         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
02509         {
02510           return HAL_TIMEOUT;
02511         }
02512
02513         /* Clear NACK Flag */
02514         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
02515
02516         /* Clear STOP Flag, auto generated with autoend*/
02517         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02518       }
02519
02520       /* Check if the maximum allowed number of trials has been reached */
02521       if (I2C_Trials++ == Trials)
02522       {
02523         /* Generate Stop */
02524         hi2c->Instance->CR2 |= I2C_CR2_STOP;
02525
02526         /* Wait until STOPF flag is reset */
02527         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
02528         {
02529           return HAL_TIMEOUT;
02530         }
02531
02532         /* Clear STOP Flag */
02533         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02534       }
02535     }while(I2C_Trials < Trials);
02536
02537     hi2c->State = HAL_I2C_STATE_READY;
02538
02539     /* Process Unlocked */
02540     __HAL_UNLOCK(hi2c);
02541
02542     return HAL_TIMEOUT;
02543   }
02544   else
02545   {
02546     return HAL_BUSY;
02547   }
02548 }
02549
02550 /**
02551   * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
02552   * @note   This interface allow to manage repeated start condition when a direction change during transfer
02553   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
02554   *               the configuration information for the specified I2C.
02555   * @param  DevAddress: Target device address
02556   * @param  pData: Pointer to data buffer
02557   * @param  Size: Amount of data to be sent
02558   * @param  XferOptions: Options of Transfer, value of @arg I2C_XferOptions_definition
02559   * @retval HAL status
02560   */
02561 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
02562 {
02563   uint32_t xfermode = 0U;
02564   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
02565
02566   /* Check the parameters */
02567   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
02568
02569   if(hi2c->State == HAL_I2C_STATE_READY)
02570   {
02571     /* Process Locked */
02572     __HAL_LOCK(hi2c);
02573
02574     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
02575     hi2c->Mode      = HAL_I2C_MODE_MASTER;
02576     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02577
02578     /* Prepare transfer parameters */
02579     hi2c->pBuffPtr    = pData;
02580     hi2c->XferCount   = Size;
02581     hi2c->XferOptions = XferOptions;
02582     hi2c->XferISR     = I2C_Master_ISR_IT;
02583
02584     /* If size > MAX_NBYTE_SIZE, use reload mode */
02585     if(hi2c->XferCount > MAX_NBYTE_SIZE)
02586     {
02587       hi2c->XferSize = MAX_NBYTE_SIZE;
02588       xfermode = I2C_RELOAD_MODE;
02589     }
02590     else
02591     {
02592       hi2c->XferSize = hi2c->XferCount;
02593       xfermode = hi2c->XferOptions;
02594     }
02595
02596     /* If transfer direction not change, do not generate Restart Condition */
02597     /* Mean Previous state is same as current state */
02598     if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
02599     {
02600       xferrequest = I2C_NO_STARTSTOP;
02601     }
02602
02603     /* Send Slave Address and set NBYTES to write */
02604     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
02605
02606     /* Process Unlocked */
02607     __HAL_UNLOCK(hi2c);
02608
02609     /* Note : The I2C interrupts must be enabled after unlocking current process
02610               to avoid the risk of I2C interrupt handle execution before current
02611               process unlock */
02612     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
02613
02614     return HAL_OK;
02615   }
02616   else
02617   {
02618     return HAL_BUSY;
02619   }
02620 }
02621
02622 /**
02623   * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
02624   * @note   This interface allow to manage repeated start condition when a direction change during transfer
02625   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
02626   *               the configuration information for the specified I2C.
02627   * @param  DevAddress: Target device address
02628   * @param  pData: Pointer to data buffer
02629   * @param  Size: Amount of data to be sent
02630   * @param  XferOptions: Options of Transfer, value of @arg I2C_XferOptions_definition
02631   * @retval HAL status
02632   */
02633 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
02634 {
02635   uint32_t xfermode = 0U;
02636   uint32_t xferrequest = I2C_GENERATE_START_READ;
02637
02638   /* Check the parameters */
02639   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
02640
02641   if(hi2c->State == HAL_I2C_STATE_READY)
02642   {
02643     /* Process Locked */
02644     __HAL_LOCK(hi2c);
02645
02646     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
02647     hi2c->Mode      = HAL_I2C_MODE_MASTER;
02648     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02649
02650     /* Prepare transfer parameters */
02651     hi2c->pBuffPtr    = pData;
02652     hi2c->XferCount   = Size;
02653     hi2c->XferOptions = XferOptions;
02654     hi2c->XferISR     = I2C_Master_ISR_IT;
02655
02656     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
02657     if(hi2c->XferCount > MAX_NBYTE_SIZE)
02658     {
02659       hi2c->XferSize = MAX_NBYTE_SIZE;
02660       xfermode = I2C_RELOAD_MODE;
02661     }
02662     else
02663     {
02664       hi2c->XferSize = hi2c->XferCount;
02665       xfermode = hi2c->XferOptions;
02666     }
02667
02668     /* If transfer direction not change, do not generate Restart Condition */
02669     /* Mean Previous state is same as current state */
02670     if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
02671     {
02672       xferrequest = I2C_NO_STARTSTOP;
02673     }
02674
02675     /* Send Slave Address and set NBYTES to read */
02676     I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest);
02677
02678     /* Process Unlocked */
02679     __HAL_UNLOCK(hi2c);
02680
02681     /* Note : The I2C interrupts must be enabled after unlocking current process
02682               to avoid the risk of I2C interrupt handle execution before current
02683               process unlock */
02684     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
02685
02686     return HAL_OK;
02687   }
02688   else
02689   {
02690     return HAL_BUSY;
02691   }
02692 }
02693
02694 /**
02695   * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
02696   * @note   This interface allow to manage repeated start condition when a direction change during transfer
02697   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
02698   *               the configuration information for the specified I2C.
02699   * @param  pData: Pointer to data buffer
02700   * @param  Size: Amount of data to be sent
02701   * @param  XferOptions: Options of Transfer, value of @arg I2C_XferOptions_definition
02702   * @retval HAL status
02703   */
02704 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
02705 {
02706   /* Check the parameters */
02707   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
02708
02709   if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
02710   {
02711     if((pData == NULL) || (Size == 0U))
02712     {
02713       return  HAL_ERROR;
02714     }
02715
02716     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
02717     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
02718
02719     /* Process Locked */
02720     __HAL_LOCK(hi2c);
02721
02722     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
02723     /* and then toggle the HAL slave RX state to TX state */
02724     if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
02725     {
02726       /* Disable associated Interrupts */
02727       I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
02728     }
02729
02730     hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
02731     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
02732     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02733
02734     /* Enable Address Acknowledge */
02735     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
02736
02737     /* Prepare transfer parameters */
02738     hi2c->pBuffPtr    = pData;
02739     hi2c->XferCount   = Size;
02740     hi2c->XferSize    = hi2c->XferCount;
02741     hi2c->XferOptions = XferOptions;
02742     hi2c->XferISR     = I2C_Slave_ISR_IT;
02743
02744     if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
02745     {
02746       /* Clear ADDR flag after prepare the transfer parameters */
02747       /* This action will generate an acknowledge to the Master */
02748       __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
02749     }
02750
02751     /* Process Unlocked */
02752     __HAL_UNLOCK(hi2c);
02753
02754     /* Note : The I2C interrupts must be enabled after unlocking current process
02755     to avoid the risk of I2C interrupt handle execution before current
02756     process unlock */
02757     /* REnable ADDR interrupt */
02758     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
02759
02760     return HAL_OK;
02761   }
02762   else
02763   {
02764     return HAL_ERROR;
02765   }
02766 }
02767
02768 /**
02769   * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
02770   * @note   This interface allow to manage repeated start condition when a direction change during transfer
02771   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
02772   *               the configuration information for the specified I2C.
02773   * @param  pData: Pointer to data buffer
02774   * @param  Size: Amount of data to be sent
02775   * @param  XferOptions: Options of Transfer, value of @arg I2C_XferOptions_definition
02776   * @retval HAL status
02777   */
02778 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
02779 {
02780   /* Check the parameters */
02781   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
02782
02783   if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
02784   {
02785     if((pData == NULL) || (Size == 0U))
02786     {
02787       return  HAL_ERROR;
02788     }
02789
02790     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
02791     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
02792
02793     /* Process Locked */
02794     __HAL_LOCK(hi2c);
02795
02796     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
02797     /* and then toggle the HAL slave TX state to RX state */
02798     if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
02799     {
02800       /* Disable associated Interrupts */
02801       I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
02802     }
02803
02804     hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
02805     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
02806     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02807
02808     /* Enable Address Acknowledge */
02809     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
02810
02811     /* Prepare transfer parameters */
02812     hi2c->pBuffPtr    = pData;
02813     hi2c->XferCount   = Size;
02814     hi2c->XferSize    = hi2c->XferCount;
02815     hi2c->XferOptions = XferOptions;
02816     hi2c->XferISR     = I2C_Slave_ISR_IT;
02817
02818     if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
02819     {
02820       /* Clear ADDR flag after prepare the transfer parameters */
02821       /* This action will generate an acknowledge to the Master */
02822       __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
02823     }
02824
02825     /* Process Unlocked */
02826     __HAL_UNLOCK(hi2c);
02827
02828     /* Note : The I2C interrupts must be enabled after unlocking current process
02829     to avoid the risk of I2C interrupt handle execution before current
02830     process unlock */
02831     /* REnable ADDR interrupt */
02832     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
02833
02834     return HAL_OK;
02835   }
02836   else
02837   {
02838     return HAL_ERROR;
02839   }
02840 }
02841
02842 /**
02843   * @brief  Enable the Address listen mode with Interrupt.
02844   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
02845   *               the configuration information for the specified I2C.
02846   * @retval HAL status
02847   */
02848 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
02849 {
02850   if(hi2c->State == HAL_I2C_STATE_READY)
02851   {
02852     hi2c->State = HAL_I2C_STATE_LISTEN;
02853     hi2c->XferISR = I2C_Slave_ISR_IT;
02854
02855     /* Enable the Address Match interrupt */
02856     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
02857
02858     return HAL_OK;
02859   }
02860   else
02861   {
02862     return HAL_BUSY;
02863   }
02864 }
02865
02866 /**
02867   * @brief  Disable the Address listen mode with Interrupt.
02868   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
02869   *               the configuration information for the specified I2C
02870   * @retval HAL status
02871   */
02872 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
02873 {
02874   /* Declaration of tmp to prevent undefined behavior of volatile usage */
02875   uint32_t tmp;
02876
02877   /* Disable Address listen mode only if a transfer is not ongoing */
02878   if(hi2c->State == HAL_I2C_STATE_LISTEN)
02879   {
02880     tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
02881     hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
02882     hi2c->State = HAL_I2C_STATE_READY;
02883     hi2c->Mode = HAL_I2C_MODE_NONE;
02884     hi2c->XferISR = NULL;
02885
02886     /* Disable the Address Match interrupt */
02887     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
02888
02889     return HAL_OK;
02890   }
02891   else
02892   {
02893     return HAL_BUSY;
02894   }
02895 }
02896
02897 /**
02898   * @brief  Abort a master/host I2C process communication with Interrupt.
02899   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
02900   *               the configuration information for the specified I2C.
02901   * @param  DevAddress: Target device address
02902   * @retval HAL status
02903   */
02904 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
02905 {
02906   if(hi2c->Mode == HAL_I2C_MODE_MASTER)
02907   {
02908     /* Process Locked */
02909     __HAL_LOCK(hi2c);
02910
02911     /* Disable Interrupts */
02912     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
02913     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
02914
02915     /* Set State at HAL_I2C_STATE_ABORT */
02916     hi2c->State = HAL_I2C_STATE_ABORT;
02917
02918     /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
02919     /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
02920     I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
02921
02922     /* Process Unlocked */
02923     __HAL_UNLOCK(hi2c);
02924
02925     /* Note : The I2C interrupts must be enabled after unlocking current process
02926               to avoid the risk of I2C interrupt handle execution before current
02927               process unlock */
02928     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
02929
02930     return HAL_OK;
02931   }
02932   else
02933   {
02934     /* Wrong usage of abort function */
02935     /* This function should be used only in case of abort monitored by master device */
02936     return HAL_ERROR;
02937   }
02938 }
02939
02940 /**
02941   * @}
02942   */
02943
02944 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
02945  * @{
02946  */
02947
02948 /**
02949   * @brief  This function handles I2C event interrupt request.
02950   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
02951   *               the configuration information for the specified I2C.
02952   * @retval None
02953   */
02954 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
02955 {
02956   /* Get current IT Flags and IT sources value */
02957   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
02958   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
02959
02960   /* I2C events treatment -------------------------------------*/
02961   if(hi2c->XferISR != NULL)
02962   {
02963     hi2c->XferISR(hi2c, itflags, itsources);
02964   }
02965 }
02966
02967 /**
02968   * @brief  This function handles I2C error interrupt request.
02969   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
02970   *               the configuration information for the specified I2C.
02971   * @retval None
02972   */
02973 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
02974 {
02975   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
02976   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
02977
02978   /* I2C Bus error interrupt occurred ------------------------------------*/
02979   if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
02980   {
02981     hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
02982
02983     /* Clear BERR flag */
02984     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
02985   }
02986
02987   /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
02988   if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
02989   {
02990     hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
02991
02992     /* Clear OVR flag */
02993     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
02994   }
02995
02996   /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
02997   if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
02998   {
02999     hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
03000
03001     /* Clear ARLO flag */
03002     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
03003   }
03004
03005   /* Call the Error Callback in case of Error detected */
03006   if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
03007   {
03008     I2C_ITError(hi2c, hi2c->ErrorCode);
03009   }
03010 }
03011
03012 /**
03013   * @brief  Master Tx Transfer completed callback.
03014   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
03015   *               the configuration information for the specified I2C.
03016   * @retval None
03017   */
03018 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
03019 {
03020   /* Prevent unused argument(s) compilation warning */
03021   UNUSED(hi2c);
03022
03023   /* NOTE : This function should not be modified, when the callback is needed,
03024             the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
03025    */
03026 }
03027
03028 /**
03029   * @brief  Master Rx Transfer completed callback.
03030   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
03031   *               the configuration information for the specified I2C.
03032   * @retval None
03033   */
03034 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
03035 {
03036   /* Prevent unused argument(s) compilation warning */
03037   UNUSED(hi2c);
03038
03039   /* NOTE : This function should not be modified, when the callback is needed,
03040             the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
03041    */
03042 }
03043
03044 /** @brief  Slave Tx Transfer completed callback.
03045   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
03046   *               the configuration information for the specified I2C.
03047   * @retval None
03048   */
03049 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
03050 {
03051   /* Prevent unused argument(s) compilation warning */
03052   UNUSED(hi2c);
03053
03054   /* NOTE : This function should not be modified, when the callback is needed,
03055             the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
03056    */
03057 }
03058
03059 /**
03060   * @brief  Slave Rx Transfer completed callback.
03061   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
03062   *               the configuration information for the specified I2C.
03063   * @retval None
03064   */
03065 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
03066 {
03067   /* Prevent unused argument(s) compilation warning */
03068   UNUSED(hi2c);
03069
03070   /* NOTE : This function should not be modified, when the callback is needed,
03071             the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
03072    */
03073 }
03074
03075 /**
03076   * @brief  Slave Address Match callback.
03077   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
03078   *               the configuration information for the specified I2C.
03079   * @param  TransferDirection: Master request Transfer Direction (Write/Read), value of @arg I2C_XferOptions_definition
03080   * @param  AddrMatchCode: Address Match Code
03081   * @retval None
03082   */
03083 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
03084 {
03085   /* Prevent unused argument(s) compilation warning */
03086   UNUSED(hi2c);
03087   UNUSED(TransferDirection);
03088   UNUSED(AddrMatchCode);
03089
03090   /* NOTE : This function should not be modified, when the callback is needed,
03091             the HAL_I2C_AddrCallback() could be implemented in the user file
03092    */
03093 }
03094
03095 /**
03096   * @brief  Listen Complete callback.
03097   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
03098   *               the configuration information for the specified I2C.
03099   * @retval None
03100   */
03101 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
03102 {
03103   /* Prevent unused argument(s) compilation warning */
03104   UNUSED(hi2c);
03105
03106   /* NOTE : This function should not be modified, when the callback is needed,
03107             the HAL_I2C_ListenCpltCallback() could be implemented in the user file
03108    */
03109 }
03110
03111 /**
03112   * @brief  Memory Tx Transfer completed callback.
03113   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
03114   *               the configuration information for the specified I2C.
03115   * @retval None
03116   */
03117 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
03118 {
03119   /* Prevent unused argument(s) compilation warning */
03120   UNUSED(hi2c);
03121
03122   /* NOTE : This function should not be modified, when the callback is needed,
03123             the HAL_I2C_MemTxCpltCallback could be implemented in the user file
03124    */
03125 }
03126
03127 /**
03128   * @brief  Memory Rx Transfer completed callback.
03129   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
03130   *               the configuration information for the specified I2C.
03131   * @retval None
03132   */
03133 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
03134 {
03135   /* Prevent unused argument(s) compilation warning */
03136   UNUSED(hi2c);
03137
03138   /* NOTE : This function should not be modified, when the callback is needed,
03139             the HAL_I2C_MemRxCpltCallback could be implemented in the user file
03140    */
03141 }
03142
03143 /**
03144   * @brief  I2C error callback.
03145   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
03146   *               the configuration information for the specified I2C.
03147   * @retval None
03148   */
03149 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
03150 {
03151   /* Prevent unused argument(s) compilation warning */
03152   UNUSED(hi2c);
03153
03154   /* NOTE : This function should not be modified, when the callback is needed,
03155             the HAL_I2C_ErrorCallback could be implemented in the user file
03156    */
03157 }
03158
03159 /**
03160   * @brief  I2C abort callback.
03161   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
03162   *               the configuration information for the specified I2C.
03163   * @retval None
03164   */
03165 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
03166 {
03167   /* Prevent unused argument(s) compilation warning */
03168   UNUSED(hi2c);
03169
03170   /* NOTE : This function should not be modified, when the callback is needed,
03171             the HAL_I2C_AbortCpltCallback could be implemented in the user file
03172    */
03173 }
03174
03175 /**
03176   * @}
03177   */
03178
03179 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
03180  *  @brief   Peripheral State, Mode and Error functions
03181  *
03182 @verbatim
03183  ===============================================================================
03184             ##### Peripheral State, Mode and Error functions #####
03185  ===============================================================================
03186     [..]
03187     This subsection permit to get in run-time the status of the peripheral
03188     and the data flow.
03189
03190 @endverbatim
03191   * @{
03192   */
03193
03194 /**
03195   * @brief  Return the I2C handle state.
03196   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
03197   *               the configuration information for the specified I2C.
03198   * @retval HAL state
03199   */
03200 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
03201 {
03202   /* Return I2C handle state */
03203   return hi2c->State;
03204 }
03205
03206 /**
03207   * @brief  Returns the I2C Master, Slave, Memory or no mode.
03208   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
03209   *         the configuration information for I2C module
03210   * @retval HAL mode
03211   */
03212 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
03213 {
03214   return hi2c->Mode;
03215 }
03216
03217 /**
03218 * @brief  Return the I2C error code.
03219   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
03220   *              the configuration information for the specified I2C.
03221 * @retval I2C Error Code
03222 */
03223 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
03224 {
03225   return hi2c->ErrorCode;
03226 }
03227
03228 /**
03229   * @}
03230   */
03231
03232 /**
03233   * @}
03234   */
03235
03236 /** @addtogroup I2C_Private_Functions
03237   * @{
03238   */
03239
03240 /**
03241   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
03242   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
03243   *               the configuration information for the specified I2C.
03244   * @param  ITFlags: Interrupt flags to handle.
03245   * @param  ITSources: Interrupt sources enabled.
03246   * @retval HAL status
03247   */
03248 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
03249 {
03250   uint16_t devaddress = 0U;
03251
03252   /* Process Locked */
03253   __HAL_LOCK(hi2c);
03254
03255   if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
03256   {
03257     /* Clear NACK Flag */
03258     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03259
03260     /* Set corresponding Error Code */
03261     /* No need to generate STOP, it is automatically done */
03262     /* Error callback will be send during stop flag treatment */
03263     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03264
03265     /* Flush TX register */
03266     I2C_Flush_TXDR(hi2c);
03267   }
03268   else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
03269   {
03270     /* Read data from RXDR */
03271     (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
03272     hi2c->XferSize--;
03273     hi2c->XferCount--;
03274   }
03275   else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
03276   {
03277     /* Write data to TXDR */
03278     hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
03279     hi2c->XferSize--;
03280     hi2c->XferCount--;
03281   }
03282   else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
03283   {
03284     if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
03285     {
03286       devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
03287
03288       if(hi2c->XferCount > MAX_NBYTE_SIZE)
03289       {
03290         hi2c->XferSize = MAX_NBYTE_SIZE;
03291         I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
03292       }
03293       else
03294       {
03295         hi2c->XferSize = hi2c->XferCount;
03296         if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
03297         {
03298           I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
03299         }
03300         else
03301         {
03302           I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
03303         }
03304       }
03305     }
03306     else
03307     {
03308       /* Call TxCpltCallback() if no stop mode is set */
03309       if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
03310       {
03311         /* Call I2C Master Sequential complete process */
03312         I2C_ITMasterSequentialCplt(hi2c);
03313       }
03314       else
03315       {
03316         /* Wrong size Status regarding TCR flag event */
03317         /* Call the corresponding callback to inform upper layer of End of Transfer */
03318         I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
03319       }
03320     }
03321   }
03322   else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
03323   {
03324     if(hi2c->XferCount == 0U)
03325     {
03326       if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
03327       {
03328         /* Generate a stop condition in case of no transfer option */
03329         if(hi2c->XferOptions == I2C_NO_OPTION_FRAME)
03330         {
03331           /* Generate Stop */
03332           hi2c->Instance->CR2 |= I2C_CR2_STOP;
03333         }
03334         else
03335         {
03336           /* Call I2C Master Sequential complete process */
03337           I2C_ITMasterSequentialCplt(hi2c);
03338         }
03339       }
03340     }
03341     else
03342     {
03343       /* Wrong size Status regarding TC flag event */
03344       /* Call the corresponding callback to inform upper layer of End of Transfer */
03345       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
03346     }
03347   }
03348
03349   if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
03350   {
03351     /* Call I2C Master complete process */
03352     I2C_ITMasterCplt(hi2c, ITFlags);
03353   }
03354
03355   /* Process Unlocked */
03356   __HAL_UNLOCK(hi2c);
03357
03358   return HAL_OK;
03359 }
03360
03361 /**
03362   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
03363   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
03364   *               the configuration information for the specified I2C.
03365   * @param  ITFlags: Interrupt flags to handle.
03366   * @param  ITSources: Interrupt sources enabled.
03367   * @retval HAL status
03368   */
03369 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
03370 {
03371   /* Process locked */
03372   __HAL_LOCK(hi2c);
03373
03374   if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
03375   {
03376     /* Check that I2C transfer finished */
03377     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
03378     /* Mean XferCount == 0*/
03379     /* So clear Flag NACKF only */
03380     if(hi2c->XferCount == 0U)
03381     {
03382       if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
03383         (hi2c->State == HAL_I2C_STATE_LISTEN))
03384       {
03385         /* Call I2C Listen complete process */
03386         I2C_ITListenCplt(hi2c, ITFlags);
03387       }
03388       else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
03389       {
03390         /* Clear NACK Flag */
03391         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03392
03393         /* Flush TX register */
03394         I2C_Flush_TXDR(hi2c);
03395
03396         /* Last Byte is Transmitted */
03397         /* Call I2C Slave Sequential complete process */
03398         I2C_ITSlaveSequentialCplt(hi2c);
03399       }
03400       else
03401       {
03402         /* Clear NACK Flag */
03403         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03404       }
03405     }
03406     else
03407     {
03408       /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
03409       /* Clear NACK Flag */
03410       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03411
03412       /* Set ErrorCode corresponding to a Non-Acknowledge */
03413       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03414     }
03415   }
03416   else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
03417   {
03418     if(hi2c->XferCount > 0U)
03419     {
03420       /* Read data from RXDR */
03421       (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
03422       hi2c->XferSize--;
03423       hi2c->XferCount--;
03424     }
03425
03426     if((hi2c->XferCount == 0U) && \
03427        (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
03428     {
03429       /* Call I2C Slave Sequential complete process */
03430       I2C_ITSlaveSequentialCplt(hi2c);
03431    }
03432   }
03433   else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
03434   {
03435     I2C_ITAddrCplt(hi2c, ITFlags);
03436   }
03437   else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
03438   {
03439     /* Write data to TXDR only if XferCount not reach "0" */
03440     /* A TXIS flag can be set, during STOP treatment      */
03441     /* Check if all Datas have already been sent */
03442     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
03443     if(hi2c->XferCount > 0U)
03444     {
03445       /* Write data to TXDR */
03446       hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
03447       hi2c->XferCount--;
03448       hi2c->XferSize--;
03449     }
03450     else
03451     {
03452       if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
03453       {
03454         /* Last Byte is Transmitted */
03455         /* Call I2C Slave Sequential complete process */
03456         I2C_ITSlaveSequentialCplt(hi2c);
03457       }
03458     }
03459   }
03460
03461   /* Check if STOPF is set */
03462   if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
03463   {
03464     /* Call I2C Slave complete process */
03465     I2C_ITSlaveCplt(hi2c, ITFlags);
03466   }
03467
03468   /* Process Unlocked */
03469   __HAL_UNLOCK(hi2c);
03470
03471   return HAL_OK;
03472 }
03473
03474 /**
03475   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
03476   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
03477   *               the configuration information for the specified I2C.
03478   * @param  ITFlags: Interrupt flags to handle.
03479   * @param  ITSources: Interrupt sources enabled.
03480   * @retval HAL status
03481   */
03482 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
03483 {
03484   uint16_t devaddress = 0U;
03485   uint32_t xfermode = 0U;
03486
03487   /* Process Locked */
03488   __HAL_LOCK(hi2c);
03489
03490   if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
03491   {
03492     /* Clear NACK Flag */
03493     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03494
03495     /* Set corresponding Error Code */
03496     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03497
03498     /* No need to generate STOP, it is automatically done */
03499     /* But enable STOP interrupt, to treat it */
03500     /* Error callback will be send during stop flag treatment */
03501     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
03502
03503     /* Flush TX register */
03504     I2C_Flush_TXDR(hi2c);
03505   }
03506   else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
03507   {
03508     /* Disable TC interrupt */
03509     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
03510
03511     if(hi2c->XferCount != 0U)
03512     {
03513       /* Recover Slave address */
03514       devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
03515
03516       /* Prepare the new XferSize to transfer */
03517       if(hi2c->XferCount > MAX_NBYTE_SIZE)
03518       {
03519         hi2c->XferSize = MAX_NBYTE_SIZE;
03520         xfermode = I2C_RELOAD_MODE;
03521       }
03522       else
03523       {
03524         hi2c->XferSize = hi2c->XferCount;
03525         xfermode = I2C_AUTOEND_MODE;
03526       }
03527
03528       /* Set the new XferSize in Nbytes register */
03529       I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
03530
03531       /* Update XferCount value */
03532       hi2c->XferCount -= hi2c->XferSize;
03533
03534       /* Enable DMA Request */
03535       if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
03536       {
03537         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
03538       }
03539       else
03540       {
03541         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
03542       }
03543     }
03544     else
03545     {
03546       /* Wrong size Status regarding TCR flag event */
03547       /* Call the corresponding callback to inform upper layer of End of Transfer */
03548       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
03549     }
03550   }
03551   else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
03552   {
03553     /* Call I2C Master complete process */
03554     I2C_ITMasterCplt(hi2c, ITFlags);
03555   }
03556
03557   /* Process Unlocked */
03558   __HAL_UNLOCK(hi2c);
03559
03560   return HAL_OK;
03561 }
03562
03563 /**
03564   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
03565   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
03566   *               the configuration information for the specified I2C.
03567   * @param  ITFlags: Interrupt flags to handle.
03568   * @param  ITSources: Interrupt sources enabled.
03569   * @retval HAL status
03570   */
03571 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
03572 {
03573   /* Process locked */
03574   __HAL_LOCK(hi2c);
03575
03576   if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
03577   {
03578     /* Check that I2C transfer finished */
03579     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
03580     /* Mean XferCount == 0 */
03581     /* So clear Flag NACKF only */
03582     if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U)
03583     {
03584       /* Clear NACK Flag */
03585       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03586     }
03587     else
03588     {
03589       /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
03590       /* Clear NACK Flag */
03591       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03592
03593       /* Set ErrorCode corresponding to a Non-Acknowledge */
03594       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03595     }
03596   }
03597   else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
03598   {
03599     /* Clear ADDR flag */
03600     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
03601   }
03602   else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
03603   {
03604     /* Call I2C Slave complete process */
03605     I2C_ITSlaveCplt(hi2c, ITFlags);
03606   }
03607
03608   /* Process Unlocked */
03609   __HAL_UNLOCK(hi2c);
03610
03611   return HAL_OK;
03612 }
03613
03614 /**
03615   * @brief  Master sends target device address followed by internal memory address for write request.
03616   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
03617   *               the configuration information for the specified I2C.
03618   * @param  DevAddress: Target device address
03619   * @param  MemAddress: Internal memory address
03620   * @param  MemAddSize: Size of internal memory address
03621   * @param  Timeout: Timeout duration
03622   * @param  Tickstart Tick start value
03623   * @retval HAL status
03624   */
03625 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
03626 {
03627   I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
03628
03629   /* Wait until TXIS flag is set */
03630   if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
03631   {
03632     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03633     {
03634       return HAL_ERROR;
03635     }
03636     else
03637     {
03638       return HAL_TIMEOUT;
03639     }
03640   }
03641
03642   /* If Memory address size is 8Bit */
03643   if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
03644   {
03645     /* Send Memory Address */
03646     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03647   }
03648   /* If Memory address size is 16Bit */
03649   else
03650   {
03651     /* Send MSB of Memory Address */
03652     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
03653
03654     /* Wait until TXIS flag is set */
03655     if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
03656     {
03657       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03658       {
03659         return HAL_ERROR;
03660       }
03661       else
03662       {
03663         return HAL_TIMEOUT;
03664       }
03665     }
03666
03667     /* Send LSB of Memory Address */
03668     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03669   }
03670
03671   /* Wait until TCR flag is set */
03672   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
03673   {
03674     return HAL_TIMEOUT;
03675   }
03676
03677 return HAL_OK;
03678 }
03679
03680 /**
03681   * @brief  Master sends target device address followed by internal memory address for read request.
03682   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
03683   *               the configuration information for the specified I2C.
03684   * @param  DevAddress: Target device address
03685   * @param  MemAddress: Internal memory address
03686   * @param  MemAddSize: Size of internal memory address
03687   * @param  Timeout: Timeout duration
03688   * @param  Tickstart Tick start value
03689   * @retval HAL status
03690   */
03691 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
03692 {
03693   I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
03694
03695   /* Wait until TXIS flag is set */
03696   if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
03697   {
03698     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03699     {
03700       return HAL_ERROR;
03701     }
03702     else
03703     {
03704       return HAL_TIMEOUT;
03705     }
03706   }
03707
03708   /* If Memory address size is 8Bit */
03709   if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
03710   {
03711     /* Send Memory Address */
03712     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03713   }
03714   /* If Memory address size is 16Bit */
03715   else
03716   {
03717     /* Send MSB of Memory Address */
03718     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
03719
03720     /* Wait until TXIS flag is set */
03721     if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
03722     {
03723       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03724       {
03725         return HAL_ERROR;
03726       }
03727       else
03728       {
03729         return HAL_TIMEOUT;
03730       }
03731     }
03732
03733     /* Send LSB of Memory Address */
03734     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03735   }
03736
03737   /* Wait until TC flag is set */
03738   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
03739   {
03740     return HAL_TIMEOUT;
03741   }
03742
03743   return HAL_OK;
03744 }
03745
03746 /**
03747   * @brief  I2C Address complete process callback.
03748   * @param  hi2c: I2C handle.
03749   * @param  ITFlags: Interrupt flags to handle.
03750   * @retval None
03751   */
03752 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
03753 {
03754   uint8_t transferdirection = 0U;
03755   uint16_t slaveaddrcode = 0U;
03756   uint16_t ownadd1code = 0U;
03757   uint16_t ownadd2code = 0U;
03758
03759   /* Prevent unused argument(s) compilation warning */
03760   UNUSED(ITFlags);
03761
03762   /* In case of Listen state, need to inform upper layer of address match code event */
03763   if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
03764   {
03765     transferdirection = I2C_GET_DIR(hi2c);
03766     slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
03767     ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
03768     ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
03769
03770     /* If 10bits addressing mode is selected */
03771     if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
03772     {
03773       if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
03774       {
03775         slaveaddrcode = ownadd1code;
03776         hi2c->AddrEventCount++;
03777         if(hi2c->AddrEventCount == 2U)
03778         {
03779           /* Reset Address Event counter */
03780           hi2c->AddrEventCount = 0U;
03781
03782           /* Clear ADDR flag */
03783           __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
03784
03785           /* Process Unlocked */
03786           __HAL_UNLOCK(hi2c);
03787
03788           /* Call Slave Addr callback */
03789           HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
03790         }
03791       }
03792       else
03793       {
03794         slaveaddrcode = ownadd2code;
03795
03796         /* Disable ADDR Interrupts */
03797         I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
03798
03799         /* Process Unlocked */
03800         __HAL_UNLOCK(hi2c);
03801
03802         /* Call Slave Addr callback */
03803         HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
03804       }
03805     }
03806     /* else 7 bits addressing mode is selected */
03807     else
03808     {
03809       /* Disable ADDR Interrupts */
03810       I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
03811
03812       /* Process Unlocked */
03813       __HAL_UNLOCK(hi2c);
03814
03815       /* Call Slave Addr callback */
03816       HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
03817     }
03818   }
03819   /* Else clear address flag only */
03820   else
03821   {
03822     /* Clear ADDR flag */
03823     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
03824
03825     /* Process Unlocked */
03826     __HAL_UNLOCK(hi2c);
03827   }
03828 }
03829
03830 /**
03831   * @brief  I2C Master sequential complete process.
03832   * @param  hi2c: I2C handle.
03833   * @retval None
03834   */
03835 static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)
03836 {
03837   /* Reset I2C handle mode */
03838   hi2c->Mode = HAL_I2C_MODE_NONE;
03839
03840   /* No Generate Stop, to permit restart mode */
03841   /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
03842   if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
03843   {
03844     hi2c->State         = HAL_I2C_STATE_READY;
03845     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
03846     hi2c->XferISR       = NULL;
03847
03848     /* Disable Interrupts */
03849     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
03850
03851     /* Process Unlocked */
03852     __HAL_UNLOCK(hi2c);
03853
03854     /* Call the corresponding callback to inform upper layer of End of Transfer */
03855     HAL_I2C_MasterTxCpltCallback(hi2c);
03856   }
03857   /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
03858   else
03859   {
03860     hi2c->State         = HAL_I2C_STATE_READY;
03861     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
03862     hi2c->XferISR       = NULL;
03863
03864     /* Disable Interrupts */
03865     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
03866
03867     /* Process Unlocked */
03868     __HAL_UNLOCK(hi2c);
03869
03870     /* Call the corresponding callback to inform upper layer of End of Transfer */
03871     HAL_I2C_MasterRxCpltCallback(hi2c);
03872   }
03873 }
03874
03875 /**
03876   * @brief  I2C Slave sequential complete process.
03877   * @param  hi2c: I2C handle.
03878   * @retval None
03879   */
03880 static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)
03881 {
03882   /* Reset I2C handle mode */
03883   hi2c->Mode = HAL_I2C_MODE_NONE;
03884
03885   if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
03886   {
03887     /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
03888     hi2c->State         = HAL_I2C_STATE_LISTEN;
03889     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
03890
03891     /* Disable Interrupts */
03892     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
03893
03894     /* Process Unlocked */
03895     __HAL_UNLOCK(hi2c);
03896
03897     /* Call the Tx complete callback to inform upper layer of the end of transmit process */
03898     HAL_I2C_SlaveTxCpltCallback(hi2c);
03899   }
03900
03901   else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
03902   {
03903     /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
03904     hi2c->State         = HAL_I2C_STATE_LISTEN;
03905     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
03906
03907     /* Disable Interrupts */
03908     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
03909
03910     /* Process Unlocked */
03911     __HAL_UNLOCK(hi2c);
03912
03913     /* Call the Rx complete callback to inform upper layer of the end of receive process */
03914     HAL_I2C_SlaveRxCpltCallback(hi2c);
03915   }
03916 }
03917
03918 /**
03919   * @brief  I2C Master complete process.
03920   * @param  hi2c: I2C handle.
03921   * @param  ITFlags: Interrupt flags to handle.
03922   * @retval None
03923   */
03924 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
03925 {
03926   /* Clear STOP Flag */
03927   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03928
03929   /* Clear Configuration Register 2 */
03930   I2C_RESET_CR2(hi2c);
03931
03932   /* Reset handle parameters */
03933   hi2c->PreviousState = I2C_STATE_NONE;
03934   hi2c->XferISR       = NULL;
03935   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
03936
03937   if((ITFlags & I2C_FLAG_AF) != RESET)
03938   {
03939     /* Clear NACK Flag */
03940     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03941
03942     /* Set acknowledge error code */
03943     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03944   }
03945
03946   /* Flush TX register */
03947   I2C_Flush_TXDR(hi2c);
03948
03949   /* Disable Interrupts */
03950   I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT);
03951
03952   /* Call the corresponding callback to inform upper layer of End of Transfer */
03953   if((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT))
03954   {
03955     /* Call the corresponding callback to inform upper layer of End of Transfer */
03956     I2C_ITError(hi2c, hi2c->ErrorCode);
03957   }
03958   /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
03959   else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
03960   {
03961     hi2c->State = HAL_I2C_STATE_READY;
03962
03963     if (hi2c->Mode == HAL_I2C_MODE_MEM)
03964     {
03965       hi2c->Mode = HAL_I2C_MODE_NONE;
03966
03967       /* Process Unlocked */
03968       __HAL_UNLOCK(hi2c);
03969
03970       /* Call the corresponding callback to inform upper layer of End of Transfer */
03971       HAL_I2C_MemTxCpltCallback(hi2c);
03972     }
03973     else
03974     {
03975       hi2c->Mode = HAL_I2C_MODE_NONE;
03976
03977       /* Process Unlocked */
03978       __HAL_UNLOCK(hi2c);
03979
03980       /* Call the corresponding callback to inform upper layer of End of Transfer */
03981       HAL_I2C_MasterTxCpltCallback(hi2c);
03982     }
03983   }
03984   /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
03985   else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
03986   {
03987     hi2c->State = HAL_I2C_STATE_READY;
03988
03989     if (hi2c->Mode == HAL_I2C_MODE_MEM)
03990     {
03991       hi2c->Mode = HAL_I2C_MODE_NONE;
03992
03993       /* Process Unlocked */
03994       __HAL_UNLOCK(hi2c);
03995
03996       HAL_I2C_MemRxCpltCallback(hi2c);
03997     }
03998     else
03999     {
04000       hi2c->Mode = HAL_I2C_MODE_NONE;
04001
04002       /* Process Unlocked */
04003       __HAL_UNLOCK(hi2c);
04004
04005       HAL_I2C_MasterRxCpltCallback(hi2c);
04006     }
04007   }
04008 }
04009
04010 /**
04011   * @brief  I2C Slave complete process.
04012   * @param  hi2c: I2C handle.
04013   * @param  ITFlags: Interrupt flags to handle.
04014   * @retval None
04015   */
04016 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
04017 {
04018   /* Clear STOP Flag */
04019   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
04020
04021   /* Clear ADDR flag */
04022   __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
04023
04024   /* Disable all interrupts */
04025   I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
04026
04027   /* Disable Address Acknowledge */
04028   hi2c->Instance->CR2 |= I2C_CR2_NACK;
04029
04030   /* Clear Configuration Register 2 */
04031   I2C_RESET_CR2(hi2c);
04032
04033   /* Flush TX register */
04034   I2C_Flush_TXDR(hi2c);
04035
04036   /* If a DMA is ongoing, Update handle size context */
04037   if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||
04038      ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
04039   {
04040     hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c);
04041   }
04042
04043   /* All data are not transferred, so set error code accordingly */
04044   if(hi2c->XferCount != 0U)
04045   {
04046     /* Set ErrorCode corresponding to a Non-Acknowledge */
04047     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04048   }
04049
04050   /* Store Last receive data if any */
04051   if(((ITFlags & I2C_FLAG_RXNE) != RESET))
04052   {
04053     /* Read data from RXDR */
04054     (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
04055
04056     if((hi2c->XferSize > 0U))
04057     {
04058       hi2c->XferSize--;
04059       hi2c->XferCount--;
04060
04061       /* Set ErrorCode corresponding to a Non-Acknowledge */
04062       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04063     }
04064   }
04065
04066   hi2c->PreviousState = I2C_STATE_NONE;
04067   hi2c->Mode = HAL_I2C_MODE_NONE;
04068   hi2c->XferISR = NULL;
04069
04070   if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
04071   {
04072     /* Call the corresponding callback to inform upper layer of End of Transfer */
04073     I2C_ITError(hi2c, hi2c->ErrorCode);
04074
04075     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
04076     if(hi2c->State == HAL_I2C_STATE_LISTEN)
04077     {
04078       /* Call I2C Listen complete process */
04079       I2C_ITListenCplt(hi2c, ITFlags);
04080     }
04081   }
04082   else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
04083   {
04084     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
04085     hi2c->State = HAL_I2C_STATE_READY;
04086
04087     /* Process Unlocked */
04088     __HAL_UNLOCK(hi2c);
04089
04090     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
04091     HAL_I2C_ListenCpltCallback(hi2c);
04092   }
04093   /* Call the corresponding callback to inform upper layer of End of Transfer */
04094   else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
04095   {
04096     hi2c->State = HAL_I2C_STATE_READY;
04097
04098     /* Process Unlocked */
04099     __HAL_UNLOCK(hi2c);
04100
04101     /* Call the Slave Rx Complete callback */
04102     HAL_I2C_SlaveRxCpltCallback(hi2c);
04103   }
04104   else
04105   {
04106     hi2c->State = HAL_I2C_STATE_READY;
04107
04108     /* Process Unlocked */
04109     __HAL_UNLOCK(hi2c);
04110
04111     /* Call the Slave Tx Complete callback */
04112     HAL_I2C_SlaveTxCpltCallback(hi2c);
04113   }
04114 }
04115
04116 /**
04117   * @brief  I2C Listen complete process.
04118   * @param  hi2c: I2C handle.
04119   * @param  ITFlags: Interrupt flags to handle.
04120   * @retval None
04121   */
04122 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
04123 {
04124   /* Reset handle parameters */
04125   hi2c->XferOptions = I2C_NO_OPTION_FRAME;
04126   hi2c->PreviousState = I2C_STATE_NONE;
04127   hi2c->State = HAL_I2C_STATE_READY;
04128   hi2c->Mode = HAL_I2C_MODE_NONE;
04129   hi2c->XferISR = NULL;
04130
04131   /* Store Last receive data if any */
04132   if(((ITFlags & I2C_FLAG_RXNE) != RESET))
04133   {
04134     /* Read data from RXDR */
04135     (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
04136
04137     if((hi2c->XferSize > 0U))
04138     {
04139       hi2c->XferSize--;
04140       hi2c->XferCount--;
04141
04142       /* Set ErrorCode corresponding to a Non-Acknowledge */
04143       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04144     }
04145   }
04146
04147   /* Disable all Interrupts*/
04148   I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
04149
04150   /* Clear NACK Flag */
04151   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04152
04153   /* Process Unlocked */
04154   __HAL_UNLOCK(hi2c);
04155
04156   /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
04157   HAL_I2C_ListenCpltCallback(hi2c);
04158 }
04159
04160 /**
04161   * @brief  I2C interrupts error process.
04162   * @param  hi2c: I2C handle.
04163   * @param  ErrorCode: Error code to handle.
04164   * @retval None
04165   */
04166 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
04167 {
04168   /* Reset handle parameters */
04169   hi2c->Mode          = HAL_I2C_MODE_NONE;
04170   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
04171   hi2c->XferCount     = 0U;
04172
04173   /* Set new error code */
04174   hi2c->ErrorCode |= ErrorCode;
04175
04176   /* Disable Interrupts */
04177   if((hi2c->State == HAL_I2C_STATE_LISTEN)         ||
04178      (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
04179      (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
04180   {
04181     /* Disable all interrupts, except interrupts related to LISTEN state */
04182     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
04183
04184     /* keep HAL_I2C_STATE_LISTEN if set */
04185     hi2c->State         = HAL_I2C_STATE_LISTEN;
04186     hi2c->PreviousState = I2C_STATE_NONE;
04187     hi2c->XferISR       = I2C_Slave_ISR_IT;
04188   }
04189   else
04190   {
04191     /* Disable all interrupts */
04192     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
04193
04194     /* If state is an abort treatment on goind, don't change state */
04195     /* This change will be do later */
04196     if(hi2c->State != HAL_I2C_STATE_ABORT)
04197     {
04198       /* Set HAL_I2C_STATE_READY */
04199       hi2c->State         = HAL_I2C_STATE_READY;
04200     }
04201     hi2c->PreviousState = I2C_STATE_NONE;
04202     hi2c->XferISR       = NULL;
04203   }
04204
04205   /* Abort DMA TX transfer if any */
04206   if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
04207   {
04208     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
04209
04210     /* Set the I2C DMA Abort callback :
04211        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04212     hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
04213
04214     /* Process Unlocked */
04215     __HAL_UNLOCK(hi2c);
04216
04217     /* Abort DMA TX */
04218     if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
04219     {
04220       /* Call Directly XferAbortCallback function in case of error */
04221       hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
04222     }
04223   }
04224   /* Abort DMA RX transfer if any */
04225   else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
04226   {
04227     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
04228
04229     /* Set the I2C DMA Abort callback :
04230        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04231     hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
04232
04233     /* Process Unlocked */
04234     __HAL_UNLOCK(hi2c);
04235
04236     /* Abort DMA RX */
04237     if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
04238     {
04239       /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
04240       hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
04241     }
04242   }
04243   else if(hi2c->State == HAL_I2C_STATE_ABORT)
04244   {
04245     hi2c->State = HAL_I2C_STATE_READY;
04246
04247     /* Process Unlocked */
04248     __HAL_UNLOCK(hi2c);
04249
04250     /* Call the corresponding callback to inform upper layer of End of Transfer */
04251     HAL_I2C_AbortCpltCallback(hi2c);
04252   }
04253   else
04254   {
04255     /* Process Unlocked */
04256     __HAL_UNLOCK(hi2c);
04257
04258     /* Call the corresponding callback to inform upper layer of End of Transfer */
04259     HAL_I2C_ErrorCallback(hi2c);
04260   }
04261 }
04262
04263 /**
04264   * @brief  I2C Tx data register flush process.
04265   * @param  hi2c: I2C handle.
04266   * @retval None
04267   */
04268 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
04269 {
04270   /* If a pending TXIS flag is set */
04271   /* Write a dummy data in TXDR to clear it */
04272   if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
04273   {
04274      hi2c->Instance->TXDR = 0x00U;
04275   }
04276
04277   /* Flush TX register if not empty */
04278   if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
04279   {
04280     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
04281   }
04282 }
04283
04284 /**
04285   * @brief  DMA I2C master transmit process complete callback.
04286   * @param  hdma: DMA handle
04287   * @retval None
04288   */
04289 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
04290 {
04291   I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
04292
04293   /* Disable DMA Request */
04294   hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
04295
04296   /* If last transfer, enable STOP interrupt */
04297   if(hi2c->XferCount == 0U)
04298   {
04299     /* Enable STOP interrupt */
04300     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
04301   }
04302   /* else prepare a new DMA transfer and enable TCReload interrupt */
04303   else
04304   {
04305     /* Update Buffer pointer */
04306     hi2c->pBuffPtr += hi2c->XferSize;
04307
04308     /* Set the XferSize to transfer */
04309     if(hi2c->XferCount > MAX_NBYTE_SIZE)
04310     {
04311       hi2c->XferSize = MAX_NBYTE_SIZE;
04312     }
04313     else
04314     {
04315       hi2c->XferSize = hi2c->XferCount;
04316     }
04317
04318     /* Enable the DMA channel */
04319     HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
04320
04321     /* Enable TC interrupts */
04322     I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
04323   }
04324 }
04325
04326 /**
04327   * @brief  DMA I2C slave transmit process complete callback.
04328   * @param  hdma: DMA handle
04329   * @retval None
04330   */
04331 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
04332 {
04333   /* Prevent unused argument(s) compilation warning */
04334   UNUSED(hdma);
04335
04336   /* No specific action, Master fully manage the generation of STOP condition */
04337   /* Mean that this generation can arrive at any time, at the end or during DMA process */
04338   /* So STOP condition should be manage through Interrupt treatment */
04339 }
04340
04341 /**
04342   * @brief DMA I2C master receive process complete callback.
04343   * @param  hdma: DMA handle
04344   * @retval None
04345   */
04346 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
04347 {
04348   I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
04349
04350   /* Disable DMA Request */
04351   hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
04352
04353   /* If last transfer, enable STOP interrupt */
04354   if(hi2c->XferCount == 0U)
04355   {
04356     /* Enable STOP interrupt */
04357     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
04358   }
04359   /* else prepare a new DMA transfer and enable TCReload interrupt */
04360   else
04361   {
04362     /* Update Buffer pointer */
04363     hi2c->pBuffPtr += hi2c->XferSize;
04364
04365     /* Set the XferSize to transfer */
04366     if(hi2c->XferCount > MAX_NBYTE_SIZE)
04367     {
04368       hi2c->XferSize = MAX_NBYTE_SIZE;
04369     }
04370     else
04371     {
04372       hi2c->XferSize = hi2c->XferCount;
04373     }
04374
04375     /* Enable the DMA channel */
04376     HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
04377
04378     /* Enable TC interrupts */
04379     I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
04380   }
04381 }
04382
04383 /**
04384   * @brief  DMA I2C slave receive process complete callback.
04385   * @param hdma: DMA handle
04386   * @retval None
04387   */
04388 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
04389 {
04390   /* Prevent unused argument(s) compilation warning */
04391   UNUSED(hdma);
04392
04393   /* No specific action, Master fully manage the generation of STOP condition */
04394   /* Mean that this generation can arrive at any time, at the end or during DMA process */
04395   /* So STOP condition should be manage through Interrupt treatment */
04396 }
04397
04398 /**
04399   * @brief  DMA I2C communication error callback.
04400   * @param hdma: DMA handle
04401   * @retval None
04402   */
04403 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
04404 {
04405   I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04406
04407   /* Disable Acknowledge */
04408   hi2c->Instance->CR2 |= I2C_CR2_NACK;
04409
04410   /* Call the corresponding callback to inform upper layer of End of Transfer */
04411   I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
04412 }
04413
04414 /**
04415   * @brief DMA I2C communication abort callback
04416   *        (To be called at end of DMA Abort procedure).
04417   * @param hdma: DMA handle.
04418   * @retval None
04419   */
04420 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
04421 {
04422   I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04423
04424   /* Disable Acknowledge */
04425   hi2c->Instance->CR2 |= I2C_CR2_NACK;
04426
04427   /* Reset AbortCpltCallback */
04428   hi2c->hdmatx->XferAbortCallback = NULL;
04429   hi2c->hdmarx->XferAbortCallback = NULL;
04430
04431   /* Check if come from abort from user */
04432   if(hi2c->State == HAL_I2C_STATE_ABORT)
04433   {
04434     hi2c->State = HAL_I2C_STATE_READY;
04435
04436     /* Call the corresponding callback to inform upper layer of End of Transfer */
04437     HAL_I2C_AbortCpltCallback(hi2c);
04438   }
04439   else
04440   {
04441     /* Call the corresponding callback to inform upper layer of End of Transfer */
04442     HAL_I2C_ErrorCallback(hi2c);
04443   }
04444 }
04445
04446 /**
04447   * @brief  This function handles I2C Communication Timeout.
04448   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
04449   *               the configuration information for the specified I2C.
04450   * @param  Flag: Specifies the I2C flag to check.
04451   * @param  Status: The new Flag status (SET or RESET).
04452   * @param  Timeout: Timeout duration
04453   * @param  Tickstart: Tick start value
04454   * @retval HAL status
04455   */
04456 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
04457 {
04458   while(__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
04459   {
04460     /* Check for the Timeout */
04461     if(Timeout != HAL_MAX_DELAY)
04462     {
04463       if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
04464       {
04465         hi2c->State= HAL_I2C_STATE_READY;
04466         hi2c->Mode = HAL_I2C_MODE_NONE;
04467
04468         /* Process Unlocked */
04469         __HAL_UNLOCK(hi2c);
04470         return HAL_TIMEOUT;
04471       }
04472     }
04473   }
04474   return HAL_OK;
04475 }
04476
04477 /**
04478   * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
04479   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
04480   *               the configuration information for the specified I2C.
04481   * @param  Timeout: Timeout duration
04482   * @param  Tickstart: Tick start value
04483   * @retval HAL status
04484   */
04485 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
04486 {
04487   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
04488   {
04489     /* Check if a NACK is detected */
04490     if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
04491     {
04492       return HAL_ERROR;
04493     }
04494
04495     /* Check for the Timeout */
04496     if(Timeout != HAL_MAX_DELAY)
04497     {
04498       if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
04499       {
04500         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04501         hi2c->State= HAL_I2C_STATE_READY;
04502         hi2c->Mode = HAL_I2C_MODE_NONE;
04503
04504         /* Process Unlocked */
04505         __HAL_UNLOCK(hi2c);
04506
04507         return HAL_TIMEOUT;
04508       }
04509     }
04510   }
04511   return HAL_OK;
04512 }
04513
04514 /**
04515   * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
04516   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
04517   *               the configuration information for the specified I2C.
04518   * @param  Timeout: Timeout duration
04519   * @param  Tickstart: Tick start value
04520   * @retval HAL status
04521   */
04522 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
04523 {
04524   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
04525   {
04526     /* Check if a NACK is detected */
04527     if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
04528     {
04529       return HAL_ERROR;
04530     }
04531
04532     /* Check for the Timeout */
04533     if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
04534     {
04535       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04536       hi2c->State= HAL_I2C_STATE_READY;
04537       hi2c->Mode = HAL_I2C_MODE_NONE;
04538
04539       /* Process Unlocked */
04540       __HAL_UNLOCK(hi2c);
04541
04542       return HAL_TIMEOUT;
04543     }
04544   }
04545   return HAL_OK;
04546 }
04547
04548 /**
04549   * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
04550   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
04551   *               the configuration information for the specified I2C.
04552   * @param  Timeout: Timeout duration
04553   * @param  Tickstart: Tick start value
04554   * @retval HAL status
04555   */
04556 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
04557 {
04558   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
04559   {
04560     /* Check if a NACK is detected */
04561     if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
04562     {
04563       return HAL_ERROR;
04564     }
04565
04566     /* Check if a STOPF is detected */
04567     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
04568     {
04569       /* Clear STOP Flag */
04570       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
04571
04572       /* Clear Configuration Register 2 */
04573       I2C_RESET_CR2(hi2c);
04574
04575       hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
04576       hi2c->State= HAL_I2C_STATE_READY;
04577       hi2c->Mode = HAL_I2C_MODE_NONE;
04578
04579       /* Process Unlocked */
04580       __HAL_UNLOCK(hi2c);
04581
04582       return HAL_ERROR;
04583     }
04584
04585     /* Check for the Timeout */
04586     if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
04587     {
04588       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04589       hi2c->State= HAL_I2C_STATE_READY;
04590
04591       /* Process Unlocked */
04592       __HAL_UNLOCK(hi2c);
04593
04594       return HAL_TIMEOUT;
04595     }
04596   }
04597   return HAL_OK;
04598 }
04599
04600 /**
04601   * @brief  This function handles Acknowledge failed detection during an I2C Communication.
04602   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
04603   *               the configuration information for the specified I2C.
04604   * @param  Timeout: Timeout duration
04605   * @param  Tickstart: Tick start value
04606   * @retval HAL status
04607   */
04608 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
04609 {
04610   if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
04611   {
04612     /* Wait until STOP Flag is reset */
04613     /* AutoEnd should be initiate after AF */
04614     while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
04615     {
04616       /* Check for the Timeout */
04617       if(Timeout != HAL_MAX_DELAY)
04618       {
04619       if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
04620         {
04621           hi2c->State= HAL_I2C_STATE_READY;
04622           hi2c->Mode = HAL_I2C_MODE_NONE;
04623
04624           /* Process Unlocked */
04625           __HAL_UNLOCK(hi2c);
04626           return HAL_TIMEOUT;
04627         }
04628       }
04629     }
04630
04631     /* Clear NACKF Flag */
04632     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04633
04634     /* Clear STOP Flag */
04635     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
04636
04637     /* Flush TX register */
04638     I2C_Flush_TXDR(hi2c);
04639
04640     /* Clear Configuration Register 2 */
04641     I2C_RESET_CR2(hi2c);
04642
04643     hi2c->ErrorCode = HAL_I2C_ERROR_AF;
04644     hi2c->State= HAL_I2C_STATE_READY;
04645     hi2c->Mode = HAL_I2C_MODE_NONE;
04646
04647     /* Process Unlocked */
04648     __HAL_UNLOCK(hi2c);
04649
04650     return HAL_ERROR;
04651   }
04652   return HAL_OK;
04653 }
04654
04655 /**
04656   * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
04657   * @param  hi2c: I2C handle.
04658   * @param  DevAddress: Specifies the slave address to be programmed.
04659   * @param  Size: Specifies the number of bytes to be programmed.
04660   *   This parameter must be a value between 0 and 255.
04661   * @param  Mode: New state of the I2C START condition generation.
04662   *   This parameter can be one of the following values:
04663   *     @arg I2C_RELOAD_MODE: Enable Reload mode .
04664   *     @arg I2C_AUTOEND_MODE: Enable Automatic end mode.
04665   *     @arg I2C_SOFTEND_MODE: Enable Software end mode.
04666   * @param  Request: New state of the I2C START condition generation.
04667   *   This parameter can be one of the following values:
04668   *     @arg I2C_NO_STARTSTOP: Don't Generate stop and start condition.
04669   *     @arg I2C_GENERATE_STOP: Generate stop condition (Size should be set to 0).
04670   *     @arg I2C_GENERATE_START_READ: Generate Restart for read request.
04671   *     @arg I2C_GENERATE_START_WRITE: Generate Restart for write request.
04672   * @retval None
04673   */
04674 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
04675 {
04676   uint32_t tmpreg = 0U;
04677
04678   /* Check the parameters */
04679   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
04680   assert_param(IS_TRANSFER_MODE(Mode));
04681   assert_param(IS_TRANSFER_REQUEST(Request));
04682
04683   /* Get the CR2 register value */
04684   tmpreg = hi2c->Instance->CR2;
04685
04686   /* clear tmpreg specific bits */
04687   tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
04688
04689   /* update tmpreg */
04690   tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
04691             (uint32_t)Mode | (uint32_t)Request);
04692
04693   /* update CR2 register */
04694   hi2c->Instance->CR2 = tmpreg;
04695 }
04696
04697 /**
04698   * @brief  Manage the enabling of Interrupts.
04699   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
04700   *               the configuration information for the specified I2C.
04701   * @param  InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition.
04702   * @retval HAL status
04703   */
04704 static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
04705 {
04706   uint32_t tmpisr = 0U;
04707
04708   if((hi2c->XferISR == I2C_Master_ISR_DMA) || \
04709      (hi2c->XferISR == I2C_Slave_ISR_DMA))
04710   {
04711     if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
04712     {
04713       /* Enable ERR, STOP, NACK and ADDR interrupts */
04714       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
04715     }
04716
04717     if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
04718     {
04719       /* Enable ERR and NACK interrupts */
04720       tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
04721     }
04722
04723     if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
04724     {
04725       /* Enable STOP interrupts */
04726       tmpisr |= I2C_IT_STOPI;
04727     }
04728
04729     if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
04730     {
04731       /* Enable TC interrupts */
04732       tmpisr |= I2C_IT_TCI;
04733     }
04734   }
04735   else
04736   {
04737     if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
04738     {
04739       /* Enable ERR, STOP, NACK, and ADDR interrupts */
04740       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
04741     }
04742
04743     if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
04744     {
04745       /* Enable ERR, TC, STOP, NACK and RXI interrupts */
04746       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
04747     }
04748
04749     if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
04750     {
04751       /* Enable ERR, TC, STOP, NACK and TXI interrupts */
04752       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
04753     }
04754
04755     if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
04756     {
04757       /* Enable STOP interrupts */
04758       tmpisr |= I2C_IT_STOPI;
04759     }
04760   }
04761
04762   /* Enable interrupts only at the end */
04763   /* to avoid the risk of I2C interrupt handle execution before */
04764   /* all interrupts requested done */
04765   __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
04766
04767   return HAL_OK;
04768 }
04769
04770 /**
04771   * @brief  Manage the disabling of Interrupts.
04772   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
04773   *               the configuration information for the specified I2C.
04774   * @param  InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition.
04775   * @retval HAL status
04776   */
04777 static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
04778 {
04779   uint32_t tmpisr = 0U;
04780
04781   if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
04782   {
04783     /* Disable TC and TXI interrupts */
04784     tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
04785
04786     if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
04787     {
04788       /* Disable NACK and STOP interrupts */
04789       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
04790     }
04791   }
04792
04793   if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
04794   {
04795     /* Disable TC and RXI interrupts */
04796     tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
04797
04798     if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
04799     {
04800       /* Disable NACK and STOP interrupts */
04801       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
04802     }
04803   }
04804
04805   if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
04806   {
04807     /* Disable ADDR, NACK and STOP interrupts */
04808     tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
04809   }
04810
04811   if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
04812   {
04813     /* Enable ERR and NACK interrupts */
04814     tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
04815   }
04816
04817   if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
04818   {
04819     /* Enable STOP interrupts */
04820     tmpisr |= I2C_IT_STOPI;
04821   }
04822
04823   if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
04824   {
04825     /* Enable TC interrupts */
04826     tmpisr |= I2C_IT_TCI;
04827   }
04828
04829   /* Disable interrupts only at the end */
04830   /* to avoid a breaking situation like at "t" time */
04831   /* all disable interrupts request are not done */
04832   __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
04833
04834   return HAL_OK;
04835 }
04836
04837 /**
04838   * @}
04839   */
04840
04841 #endif /* HAL_I2C_MODULE_ENABLED */
04842 /**
04843   * @}
04844   */
04845
04846 /**
04847   * @}
04848   */
04849
04850 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_i2c.h Source File

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stm32h7xx_hal_i2c.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_i2c.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of I2C HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_I2C_H
00040 #define __STM32H7xx_HAL_I2C_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup I2C
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup I2C_Exported_Types I2C Exported Types
00059   * @{
00060   */
00061
00062 /** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
00063   * @brief  I2C Configuration Structure definition
00064   * @{
00065   */
00066 typedef struct
00067 {
00068   uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
00069                                   This parameter calculated by referring to I2C initialization
00070                                          section in Reference manual */
00071
00072   uint32_t OwnAddress1;         /*!< Specifies the first device own address.
00073                                   This parameter can be a 7-bit or 10-bit address. */
00074
00075   uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
00076                                   This parameter can be a value of @ref I2C_ADDRESSING_MODE */
00077
00078   uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
00079                                   This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
00080
00081   uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
00082                                   This parameter can be a 7-bit address. */
00083
00084   uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
00085                                   This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
00086
00087   uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
00088                                   This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
00089
00090   uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
00091                                   This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
00092
00093 }I2C_InitTypeDef;
00094
00095 /**
00096   * @}
00097   */
00098
00099 /** @defgroup HAL_state_structure_definition HAL state structure definition
00100   * @brief  HAL State structure definition
00101   * @{
00102   */
00103
00104 typedef enum
00105 {
00106   HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
00107   HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
00108   HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
00109   HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
00110   HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
00111   HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
00112   HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
00113                                                   process is ongoing                        */
00114   HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
00115                                                   process is ongoing                        */
00116   HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
00117   HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
00118   HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
00119
00120 }HAL_I2C_StateTypeDef;
00121
00122 /**
00123   * @}
00124   */
00125
00126 /** @defgroup HAL_mode_structure_definition HAL mode structure definition
00127   * @brief  HAL Mode structure definition
00128   * @{
00129   */
00130 typedef enum
00131 {
00132   HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
00133   HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
00134   HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
00135   HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
00136
00137 }HAL_I2C_ModeTypeDef;
00138
00139 /**
00140   * @}
00141   */
00142
00143 /** @defgroup I2C_Error_Code_definition I2C Error Code definition
00144   * @brief  I2C Error Code definition
00145   * @{
00146   */
00147 #define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */
00148 #define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */
00149 #define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */
00150 #define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */
00151 #define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */
00152 #define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */
00153 #define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
00154 #define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */
00155 /**
00156   * @}
00157   */
00158
00159 /** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
00160   * @brief  I2C handle Structure definition
00161   * @{
00162   */
00163 typedef struct __I2C_HandleTypeDef
00164 {
00165   I2C_TypeDef                *Instance;      /*!< I2C registers base address                */
00166
00167   I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */
00168
00169   uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */
00170
00171   uint16_t                   XferSize;       /*!< I2C transfer size                         */
00172
00173   __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */
00174
00175   __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can
00176                                                   be a value of @ref I2C_XFEROPTIONS */
00177
00178   __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
00179
00180   HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
00181
00182   DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
00183
00184   DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */
00185
00186   HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */
00187
00188   __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */
00189
00190   __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */
00191
00192   __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */
00193
00194   __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
00195 }I2C_HandleTypeDef;
00196 /**
00197   * @}
00198   */
00199
00200 /**
00201   * @}
00202   */
00203 /* Exported constants --------------------------------------------------------*/
00204
00205 /** @defgroup I2C_Exported_Constants I2C Exported Constants
00206   * @{
00207   */
00208
00209 /** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options
00210   * @{
00211   */
00212 #define I2C_NO_OPTION_FRAME             (0xFFFF0000U)
00213 #define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
00214 #define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
00215 #define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
00216 #define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
00217 #define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
00218 /**
00219   * @}
00220   */
00221
00222 /** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
00223   * @{
00224   */
00225 #define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)
00226 #define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)
00227 /**
00228   * @}
00229   */
00230
00231 /** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
00232   * @{
00233   */
00234 #define I2C_DUALADDRESS_DISABLE         (0x00000000U)
00235 #define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
00241   * @{
00242   */
00243 #define I2C_OA2_NOMASK                  ((uint8_t)0x00U)
00244 #define I2C_OA2_MASK01                  ((uint8_t)0x01U)
00245 #define I2C_OA2_MASK02                  ((uint8_t)0x02U)
00246 #define I2C_OA2_MASK03                  ((uint8_t)0x03U)
00247 #define I2C_OA2_MASK04                  ((uint8_t)0x04U)
00248 #define I2C_OA2_MASK05                  ((uint8_t)0x05U)
00249 #define I2C_OA2_MASK06                  ((uint8_t)0x06U)
00250 #define I2C_OA2_MASK07                  ((uint8_t)0x07U)
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
00256   * @{
00257   */
00258 #define I2C_GENERALCALL_DISABLE         (0x00000000U)
00259 #define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
00265   * @{
00266   */
00267 #define I2C_NOSTRETCH_DISABLE           (0x00000000U)
00268 #define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
00274   * @{
00275   */
00276 #define I2C_MEMADD_SIZE_8BIT            (0x00000001U)
00277 #define I2C_MEMADD_SIZE_16BIT           (0x00000002U)
00278 /**
00279   * @}
00280   */
00281
00282 /** @defgroup I2C_XferDirection I2C Transfer Direction
00283   * @{
00284   */
00285 #define I2C_DIRECTION_TRANSMIT          (0x00000000U)
00286 #define I2C_DIRECTION_RECEIVE           (0x00000001U)
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
00292   * @{
00293   */
00294 #define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
00295 #define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
00296 #define  I2C_SOFTEND_MODE               (0x00000000U)
00297 /**
00298   * @}
00299   */
00300
00301 /** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
00302   * @{
00303   */
00304 #define  I2C_NO_STARTSTOP               (0x00000000U)
00305 #define  I2C_GENERATE_STOP              I2C_CR2_STOP
00306 #define  I2C_GENERATE_START_READ        (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
00307 #define  I2C_GENERATE_START_WRITE       I2C_CR2_START
00308 /**
00309   * @}
00310   */
00311
00312 /** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
00313   * @brief I2C Interrupt definition
00314   *        Elements values convention: 0xXXXXXXXX
00315   *           - XXXXXXXX  : Interrupt control mask
00316   * @{
00317   */
00318 #define I2C_IT_ERRI                     I2C_CR1_ERRIE
00319 #define I2C_IT_TCI                      I2C_CR1_TCIE
00320 #define I2C_IT_STOPI                    I2C_CR1_STOPIE
00321 #define I2C_IT_NACKI                    I2C_CR1_NACKIE
00322 #define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
00323 #define I2C_IT_RXI                      I2C_CR1_RXIE
00324 #define I2C_IT_TXI                      I2C_CR1_TXIE
00325 /**
00326   * @}
00327   */
00328
00329 /** @defgroup I2C_Flag_definition I2C Flag definition
00330   * @{
00331   */
00332 #define I2C_FLAG_TXE                    I2C_ISR_TXE
00333 #define I2C_FLAG_TXIS                   I2C_ISR_TXIS
00334 #define I2C_FLAG_RXNE                   I2C_ISR_RXNE
00335 #define I2C_FLAG_ADDR                   I2C_ISR_ADDR
00336 #define I2C_FLAG_AF                     I2C_ISR_NACKF
00337 #define I2C_FLAG_STOPF                  I2C_ISR_STOPF
00338 #define I2C_FLAG_TC                     I2C_ISR_TC
00339 #define I2C_FLAG_TCR                    I2C_ISR_TCR
00340 #define I2C_FLAG_BERR                   I2C_ISR_BERR
00341 #define I2C_FLAG_ARLO                   I2C_ISR_ARLO
00342 #define I2C_FLAG_OVR                    I2C_ISR_OVR
00343 #define I2C_FLAG_PECERR                 I2C_ISR_PECERR
00344 #define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
00345 #define I2C_FLAG_ALERT                  I2C_ISR_ALERT
00346 #define I2C_FLAG_BUSY                   I2C_ISR_BUSY
00347 #define I2C_FLAG_DIR                    I2C_ISR_DIR
00348 /**
00349   * @}
00350   */
00351
00352 /**
00353   * @}
00354   */
00355
00356 /* Exported macros -----------------------------------------------------------*/
00357
00358 /** @defgroup I2C_Exported_Macros I2C Exported Macros
00359   * @{
00360   */
00361
00362 /** @brief Reset I2C handle state.
00363   * @param  __HANDLE__ specifies the I2C Handle.
00364   * @retval None
00365   */
00366 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
00367
00368 /** @brief  Enable the specified I2C interrupt.
00369   * @param  __HANDLE__ specifies the I2C Handle.
00370   * @param  __INTERRUPT__ specifies the interrupt source to enable.
00371   *        This parameter can be one of the following values:
00372   *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
00373   *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
00374   *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
00375   *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
00376   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
00377   *            @arg @ref I2C_IT_RXI   RX interrupt enable
00378   *            @arg @ref I2C_IT_TXI   TX interrupt enable
00379   *
00380   * @retval None
00381   */
00382 #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
00383
00384 /** @brief  Disable the specified I2C interrupt.
00385   * @param  __HANDLE__ specifies the I2C Handle.
00386   * @param  __INTERRUPT__ specifies the interrupt source to disable.
00387   *        This parameter can be one of the following values:
00388   *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
00389   *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
00390   *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
00391   *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
00392   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
00393   *            @arg @ref I2C_IT_RXI   RX interrupt enable
00394   *            @arg @ref I2C_IT_TXI   TX interrupt enable
00395   *
00396   * @retval None
00397   */
00398 #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
00399
00400 /** @brief  Check whether the specified I2C interrupt source is enabled or not.
00401   * @param  __HANDLE__ specifies the I2C Handle.
00402   * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
00403   *          This parameter can be one of the following values:
00404   *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
00405   *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
00406   *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
00407   *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
00408   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
00409   *            @arg @ref I2C_IT_RXI   RX interrupt enable
00410   *            @arg @ref I2C_IT_TXI   TX interrupt enable
00411   *
00412   * @retval The new state of __INTERRUPT__ (SET or RESET).
00413   */
00414 #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00415
00416 /** @brief  Check whether the specified I2C flag is set or not.
00417   * @param  __HANDLE__ specifies the I2C Handle.
00418   * @param  __FLAG__ specifies the flag to check.
00419   *        This parameter can be one of the following values:
00420   *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
00421   *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status
00422   *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty
00423   *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
00424   *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
00425   *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
00426   *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)
00427   *            @arg @ref I2C_FLAG_TCR     Transfer complete reload
00428   *            @arg @ref I2C_FLAG_BERR    Bus error
00429   *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
00430   *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
00431   *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
00432   *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
00433   *            @arg @ref I2C_FLAG_ALERT   SMBus alert
00434   *            @arg @ref I2C_FLAG_BUSY    Bus busy
00435   *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
00436   *
00437   * @retval The new state of __FLAG__ (SET or RESET).
00438   */
00439 #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
00440
00441 /** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
00442   * @param  __HANDLE__ specifies the I2C Handle.
00443   * @param  __FLAG__ specifies the flag to clear.
00444   *          This parameter can be any combination of the following values:
00445   *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
00446   *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
00447   *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
00448   *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
00449   *            @arg @ref I2C_FLAG_BERR    Bus error
00450   *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
00451   *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
00452   *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
00453   *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
00454   *            @arg @ref I2C_FLAG_ALERT   SMBus alert
00455   *
00456   * @retval None
00457   */
00458 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
00459                                                                                  : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
00460
00461 /** @brief  Enable the specified I2C peripheral.
00462   * @param  __HANDLE__ specifies the I2C Handle.
00463   * @retval None
00464   */
00465 #define __HAL_I2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))
00466
00467 /** @brief  Disable the specified I2C peripheral.
00468   * @param  __HANDLE__ specifies the I2C Handle.
00469   * @retval None
00470   */
00471 #define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00472
00473 /** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
00474   * @param  __HANDLE__: specifies the I2C Handle.
00475   * @retval None
00476   */
00477 #define __HAL_I2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
00478 /**
00479   * @}
00480   */
00481
00482 /* Include I2C HAL Extended module */
00483 #include "stm32h7xx_hal_i2c_ex.h"
00484
00485 /* Exported functions --------------------------------------------------------*/
00486 /** @addtogroup I2C_Exported_Functions
00487   * @{
00488   */
00489
00490 /** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
00491   * @{
00492   */
00493 /* Initialization and de-initialization functions******************************/
00494 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
00495 HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
00496 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
00497 void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
00498 /**
00499   * @}
00500   */
00501
00502 /** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
00503   * @{
00504   */
00505 /* IO operation functions  ****************************************************/
00506  /******* Blocking mode: Polling */
00507 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00508 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00509 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00510 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00511 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00512 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00513 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
00514
00515  /******* Non-Blocking mode: Interrupt */
00516 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00517 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00518 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00519 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00520 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00521 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00522
00523 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00524 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00525 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00526 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00527 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
00528 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
00529 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
00530
00531  /******* Non-Blocking mode: DMA */
00532 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00533 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00534 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00535 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00536 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00537 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00538 /**
00539   * @}
00540   */
00541
00542 /** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00543  * @{
00544  */
00545 /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
00546 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
00547 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
00548 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
00549 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
00550 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
00551 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
00552 void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
00553 void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
00554 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
00555 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
00556 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
00557 void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
00558 /**
00559   * @}
00560   */
00561
00562 /** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
00563   * @{
00564   */
00565 /* Peripheral State, Mode and Error functions  *********************************/
00566 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
00567 HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
00568 uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
00569
00570 /**
00571   * @}
00572   */
00573
00574 /**
00575   * @}
00576   */
00577
00578 /* Private constants ---------------------------------------------------------*/
00579 /** @defgroup I2C_Private_Constants I2C Private Constants
00580   * @{
00581   */
00582
00583 /**
00584   * @}
00585   */
00586
00587 /* Private macros ------------------------------------------------------------*/
00588 /** @defgroup I2C_Private_Macro I2C Private Macros
00589   * @{
00590   */
00591
00592 #define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
00593                                          ((MODE) == I2C_ADDRESSINGMODE_10BIT))
00594
00595 #define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
00596                                          ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
00597
00598 #define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
00599                                          ((MASK) == I2C_OA2_MASK01) || \
00600                                          ((MASK) == I2C_OA2_MASK02) || \
00601                                          ((MASK) == I2C_OA2_MASK03) || \
00602                                          ((MASK) == I2C_OA2_MASK04) || \
00603                                          ((MASK) == I2C_OA2_MASK05) || \
00604                                          ((MASK) == I2C_OA2_MASK06) || \
00605                                          ((MASK) == I2C_OA2_MASK07))
00606
00607 #define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
00608                                          ((CALL) == I2C_GENERALCALL_ENABLE))
00609
00610 #define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
00611                                          ((STRETCH) == I2C_NOSTRETCH_ENABLE))
00612
00613 #define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
00614                                          ((SIZE) == I2C_MEMADD_SIZE_16BIT))
00615
00616 #define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
00617                                          ((MODE) == I2C_AUTOEND_MODE) || \
00618                                          ((MODE) == I2C_SOFTEND_MODE))
00619
00620 #define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \
00621                                          ((REQUEST) == I2C_GENERATE_START_READ)  || \
00622                                          ((REQUEST) == I2C_GENERATE_START_WRITE) || \
00623                                          ((REQUEST) == I2C_NO_STARTSTOP))
00624
00625 #define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
00626                                                    ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
00627                                                    ((REQUEST) == I2C_NEXT_FRAME)           || \
00628                                                    ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
00629                                                    ((REQUEST) == I2C_LAST_FRAME))
00630
00631 #define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
00632
00633 #define I2C_GET_ADDR_MATCH(__HANDLE__)            (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
00634 #define I2C_GET_DIR(__HANDLE__)                   (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
00635 #define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
00636 #define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
00637 #define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
00638
00639 #define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)
00640 #define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)
00641
00642 #define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
00643 #define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
00644
00645 #define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
00646                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
00647 /**
00648   * @}
00649   */
00650
00651 /* Private Functions ---------------------------------------------------------*/
00652 /** @defgroup I2C_Private_Functions I2C Private Functions
00653   * @{
00654   */
00655 /* Private functions are defined in stm32h7xx_hal_i2c.c file */
00656 /**
00657   * @}
00658   */
00659
00660 /**
00661   * @}
00662   */
00663
00664 /**
00665   * @}
00666   */
00667
00668 #ifdef __cplusplus
00669 }
00670 #endif
00671
00672
00673 #endif /* __STM32H7xx_HAL_I2C_H */
00674
00675 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_i2c_ex.c Source File

  • File List
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  • STM32H7xx_HAL_Driver
  • Src
stm32h7xx_hal_i2c_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_i2c_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   I2C Extended HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of I2C Extended peripheral:
00010   *           + Extended features functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                ##### I2C peripheral Extended features  #####
00015   ==============================================================================
00016
00017   [..] Comparing to other previous devices, the I2C interface for STM32H7XX
00018        devices contains the following additional features
00019
00020        (+) Possibility to disable or enable Analog Noise Filter
00021        (+) Use of a configured Digital Noise Filter
00022        (+) Disable or enable wakeup from Stop modes
00023        (+) Disable or enable Fast Mode Plus
00024
00025                      ##### How to use this driver #####
00026   ==============================================================================
00027   [..] This driver provides functions to configure Noise Filter and Wake Up Feature
00028     (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
00029     (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
00030     (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
00031           (++) HAL_I2CEx_EnableWakeUp()
00032           (++) HAL_I2CEx_DisableWakeUp()
00033     (#) Configure the enable or disable of fast mode plus driving capability using the functions :
00034           (++) HAL_I2CEx_EnableFastModePlus()
00035           (++) HAL_I2CEx_DisableFastModePlus()
00036   @endverbatim
00037   ******************************************************************************
00038   * @attention
00039   *
00040   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00041   *
00042   * Redistribution and use in source and binary forms, with or without modification,
00043   * are permitted provided that the following conditions are met:
00044   *   1. Redistributions of source code must retain the above copyright notice,
00045   *      this list of conditions and the following disclaimer.
00046   *   2. Redistributions in binary form must reproduce the above copyright notice,
00047   *      this list of conditions and the following disclaimer in the documentation
00048   *      and/or other materials provided with the distribution.
00049   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00050   *      may be used to endorse or promote products derived from this software
00051   *      without specific prior written permission.
00052   *
00053   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00054   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00055   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00056   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00057   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00058   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00059   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00060   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00061   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00062   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00063   *
00064   ******************************************************************************
00065   */
00066
00067 /* Includes ------------------------------------------------------------------*/
00068 #include "stm32h7xx_hal.h"
00069
00070 /** @addtogroup STM32H7xx_HAL_Driver
00071   * @{
00072   */
00073
00074 /** @defgroup I2CEx I2CEx
00075   * @brief I2C Extended HAL module driver
00076   * @{
00077   */
00078
00079 #ifdef HAL_I2C_MODULE_ENABLED
00080
00081 /* Private typedef -----------------------------------------------------------*/
00082 /* Private define ------------------------------------------------------------*/
00083 /* Private macro -------------------------------------------------------------*/
00084 /* Private variables ---------------------------------------------------------*/
00085 /* Private function prototypes -----------------------------------------------*/
00086 /* Private functions ---------------------------------------------------------*/
00087
00088 /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
00089   * @{
00090   */
00091
00092 /** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
00093   * @brief    Extended features functions
00094  *
00095 @verbatim
00096  ===============================================================================
00097                       ##### Extended features functions #####
00098  ===============================================================================
00099     [..] This section provides functions allowing to:
00100       (+) Configure Noise Filters
00101       (+) Configure Wake Up Feature
00102       (+) Configure Fast Mode Plus
00103
00104 @endverbatim
00105   * @{
00106   */
00107
00108 /**
00109   * @brief  Configure I2C Analog noise filter.
00110   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
00111   *               the configuration information for the specified I2Cx peripheral.
00112   * @param  AnalogFilter: New state of the Analog filter.
00113   * @retval HAL status
00114   */
00115 HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
00116 {
00117   /* Check the parameters */
00118   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00119   assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
00120
00121   if(hi2c->State == HAL_I2C_STATE_READY)
00122   {
00123     /* Process Locked */
00124     __HAL_LOCK(hi2c);
00125
00126     hi2c->State = HAL_I2C_STATE_BUSY;
00127
00128     /* Disable the selected I2C peripheral */
00129     __HAL_I2C_DISABLE(hi2c);
00130
00131     /* Reset I2Cx ANOFF bit */
00132     hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
00133
00134     /* Set analog filter bit*/
00135     hi2c->Instance->CR1 |= AnalogFilter;
00136
00137     __HAL_I2C_ENABLE(hi2c);
00138
00139     hi2c->State = HAL_I2C_STATE_READY;
00140
00141     /* Process Unlocked */
00142     __HAL_UNLOCK(hi2c);
00143
00144     return HAL_OK;
00145   }
00146   else
00147   {
00148     return HAL_BUSY;
00149   }
00150 }
00151
00152 /**
00153   * @brief  Configure I2C Digital noise filter.
00154   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
00155   *               the configuration information for the specified I2Cx peripheral.
00156   * @param  DigitalFilter: Coefficient of digital noise filter between 0x00 and 0x0F.
00157   * @retval HAL status
00158   */
00159 HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
00160 {
00161   uint32_t tmpreg = 0U;
00162
00163   /* Check the parameters */
00164   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00165   assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
00166
00167   if(hi2c->State == HAL_I2C_STATE_READY)
00168   {
00169     /* Process Locked */
00170     __HAL_LOCK(hi2c);
00171
00172     hi2c->State = HAL_I2C_STATE_BUSY;
00173
00174     /* Disable the selected I2C peripheral */
00175     __HAL_I2C_DISABLE(hi2c);
00176
00177     /* Get the old register value */
00178     tmpreg = hi2c->Instance->CR1;
00179
00180     /* Reset I2Cx DNF bits [11:8] */
00181     tmpreg &= ~(I2C_CR1_DNF);
00182
00183     /* Set I2Cx DNF coefficient */
00184     tmpreg |= DigitalFilter << 8U;
00185
00186     /* Store the new register value */
00187     hi2c->Instance->CR1 = tmpreg;
00188
00189     __HAL_I2C_ENABLE(hi2c);
00190
00191     hi2c->State = HAL_I2C_STATE_READY;
00192
00193     /* Process Unlocked */
00194     __HAL_UNLOCK(hi2c);
00195
00196     return HAL_OK;
00197   }
00198   else
00199   {
00200     return HAL_BUSY;
00201   }
00202 }
00203
00204 /**
00205   * @brief  Enable I2C wakeup from stop mode.
00206   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
00207   *               the configuration information for the specified I2Cx peripheral.
00208   * @retval HAL status
00209   */
00210 HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
00211 {
00212   /* Check the parameters */
00213   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
00214
00215   if(hi2c->State == HAL_I2C_STATE_READY)
00216   {
00217     /* Process Locked */
00218     __HAL_LOCK(hi2c);
00219
00220     hi2c->State = HAL_I2C_STATE_BUSY;
00221
00222     /* Disable the selected I2C peripheral */
00223     __HAL_I2C_DISABLE(hi2c);
00224
00225     /* Enable wakeup from stop mode */
00226     hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
00227
00228     __HAL_I2C_ENABLE(hi2c);
00229
00230     hi2c->State = HAL_I2C_STATE_READY;
00231
00232     /* Process Unlocked */
00233     __HAL_UNLOCK(hi2c);
00234
00235     return HAL_OK;
00236   }
00237   else
00238   {
00239     return HAL_BUSY;
00240   }
00241 }
00242
00243 /**
00244   * @brief  Disable I2C wakeup from stop mode.
00245   * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
00246   *               the configuration information for the specified I2Cx peripheral.
00247   * @retval HAL status
00248   */
00249 HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
00250 {
00251   /* Check the parameters */
00252   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
00253
00254   if(hi2c->State == HAL_I2C_STATE_READY)
00255   {
00256     /* Process Locked */
00257     __HAL_LOCK(hi2c);
00258
00259     hi2c->State = HAL_I2C_STATE_BUSY;
00260
00261     /* Disable the selected I2C peripheral */
00262     __HAL_I2C_DISABLE(hi2c);
00263
00264     /* Enable wakeup from stop mode */
00265     hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
00266
00267     __HAL_I2C_ENABLE(hi2c);
00268
00269     hi2c->State = HAL_I2C_STATE_READY;
00270
00271     /* Process Unlocked */
00272     __HAL_UNLOCK(hi2c);
00273
00274     return HAL_OK;
00275   }
00276   else
00277   {
00278     return HAL_BUSY;
00279   }
00280 }
00281
00282 /**
00283   * @brief Enable the I2C fast mode plus driving capability.
00284   * @param ConfigFastModePlus: Selects the pin.
00285   *   This parameter can be one of the @ref I2CEx_FastModePlus values
00286   * @retval None
00287   */
00288 void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
00289 {
00290   /* Check the parameter */
00291   assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
00292
00293   /* Enable SYSCFG clock */
00294   __HAL_RCC_SYSCFG_CLK_ENABLE();
00295
00296   /* Enable fast mode plus driving capability for selected pin */
00297   SET_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
00298 }
00299
00300 /**
00301   * @brief Disable the I2C fast mode plus driving capability.
00302   * @param ConfigFastModePlus: Selects the pin.
00303   *   This parameter can be one of the @ref I2CEx_FastModePlus values
00304   * @retval None
00305   */
00306 void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
00307 {
00308   /* Check the parameter */
00309   assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
00310
00311   /* Enable SYSCFG clock */
00312   __HAL_RCC_SYSCFG_CLK_ENABLE();
00313
00314   /* Disable fast mode plus driving capability for selected pin */
00315   CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
00316 }
00317
00318 /**
00319   * @}
00320   */
00321
00322 /**
00323   * @}
00324   */
00325
00326 #endif /* HAL_I2C_MODULE_ENABLED */
00327 /**
00328   * @}
00329   */
00330
00331 /**
00332   * @}
00333   */
00334
00335 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_i2c_ex.h Source File

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  • STM32H7xx_HAL_Driver
  • Inc
stm32h7xx_hal_i2c_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_i2c_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of I2C HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_I2C_EX_H
00040 #define __STM32H7xx_HAL_I2C_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup I2CEx I2CEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059
00060 /** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
00061   * @{
00062   */
00063
00064 /** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
00065   * @{
00066   */
00067 #define I2C_ANALOGFILTER_ENABLE        ((uint32_t)0x00000000U)
00068 #define I2C_ANALOGFILTER_DISABLE       I2C_CR1_ANFOFF
00069 /**
00070   * @}
00071   */
00072
00073 /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
00074   * @{
00075   */
00076 #define I2C_FASTMODEPLUS_PB6          SYSCFG_PMCR_I2C_PB6_FMP
00077 #define I2C_FASTMODEPLUS_PB7          SYSCFG_PMCR_I2C_PB7_FMP
00078 #define I2C_FASTMODEPLUS_PB8          SYSCFG_PMCR_I2C_PB8_FMP
00079 #define I2C_FASTMODEPLUS_PB9          SYSCFG_PMCR_I2C_PB9_FMP
00080
00081 #define I2C_FASTMODEPLUS_I2C1         SYSCFG_PMCR_I2C1_FMP
00082 #define I2C_FASTMODEPLUS_I2C2         SYSCFG_PMCR_I2C2_FMP
00083 #define I2C_FASTMODEPLUS_I2C3         SYSCFG_PMCR_I2C3_FMP
00084 #define I2C_FASTMODEPLUS_I2C4         SYSCFG_PMCR_I2C4_FMP
00085 /**
00086   * @}
00087   */
00088
00089 /**
00090   * @}
00091   */
00092
00093 /* Exported macro ------------------------------------------------------------*/
00094 /* Exported functions --------------------------------------------------------*/
00095
00096 /** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
00097   * @{
00098   */
00099
00100 /** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
00101   * @brief    Extended features functions
00102   * @{
00103   */
00104
00105 /* Peripheral Control functions  ************************************************/
00106 HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
00107 HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
00108 HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
00109 HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
00110 void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
00111 void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
00112
00113 /* Private constants ---------------------------------------------------------*/
00114 /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
00115   * @{
00116   */
00117
00118 /**
00119   * @}
00120   */
00121
00122 /* Private macros ------------------------------------------------------------*/
00123 /** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
00124   * @{
00125   */
00126 #define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
00127                                           ((FILTER) == I2C_ANALOGFILTER_DISABLE))
00128
00129 #define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
00130
00131 #if defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP) && defined(SYSCFG_PMCR_I2C4_FMP)
00132 #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
00133                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
00134                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
00135                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
00136                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
00137                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
00138                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \
00139                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))
00140 #elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP)
00141 #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
00142                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
00143                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
00144                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
00145                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
00146                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
00147                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))
00148 #elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP)
00149 #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
00150                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
00151                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
00152                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
00153                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
00154                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))
00155 #elif defined(SYSCFG_PMCR_I2C1_FMP)
00156 #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
00157                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
00158                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
00159                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
00160                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
00161 #endif /* SYSCFG_PMCR_I2C1_FMP && SYSCFG_PMCR_I2C2_FMP && SYSCFG_PMCR_I2C3_FMP && SYSCFG_PMCR_I2C4_FMP */
00162 /**
00163   * @}
00164   */
00165
00166 /* Private Functions ---------------------------------------------------------*/
00167 /** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
00168   * @{
00169   */
00170 /* Private functions are defined in stm32h7xx_hal_i2c_ex.c file */
00171 /**
00172   * @}
00173   */
00174
00175 /**
00176   * @}
00177   */
00178
00179 /**
00180   * @}
00181   */
00182
00183 /**
00184   * @}
00185   */
00186
00187 /**
00188   * @}
00189   */
00190
00191 #ifdef __cplusplus
00192 }
00193 #endif
00194
00195 #endif /* __STM32H7xx_HAL_I2C_EX_H */
00196
00197
00198 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_i2s.c Source File

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stm32h7xx_hal_i2s.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_i2s.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   I2S HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral State and Errors functions
00013   @verbatim
00014  ===============================================================================
00015                   ##### How to use this driver #####
00016  ===============================================================================
00017  [..]
00018     The I2S HAL driver can be used as follow:
00019
00020     (#) Declare a I2S_HandleTypeDef handle structure.
00021     (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
00022         (##) Enable the SPIx interface clock.
00023         (##) I2S pins configuration:
00024             (+++) Enable the clock for the I2S GPIOs.
00025             (+++) Configure these I2S pins as alternate function pull-up.
00026         (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
00027              and HAL_I2S_Receive_IT() APIs).
00028             (+++) Configure the I2Sx interrupt priority.
00029             (+++) Enable the NVIC I2S IRQ handle.
00030         (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
00031              and HAL_I2S_Receive_DMA() APIs:
00032             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00033             (+++) Enable the DMAx interface clock.
00034             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00035             (+++) Configure the DMA Tx/Rx Channel.
00036             (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
00037             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
00038                   DMA Tx/Rx Channel.
00039
00040    (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
00041        using HAL_I2S_Init() function.
00042
00043    -@- The specific I2S interrupts (Transmission complete interrupt,
00044        RXNE interrupt and Error Interrupts) will be managed using the macros
00045        __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
00046    -@- Make sure that either:
00047        (+@) External clock source is configured after setting correctly
00048             the define constant EXTERNAL_CLOCK_VALUE in the stm32h7xx_hal_conf.h file.
00049
00050    Three mode of operations are available within this driver :
00051
00052    *** Polling mode IO operation ***
00053    =================================
00054    [..]
00055      (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
00056      (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
00057
00058    *** Interrupt mode IO operation ***
00059    ===================================
00060    [..]
00061      (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
00062      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
00063          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
00064      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
00065          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
00066      (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
00067      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
00068          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
00069      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
00070          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
00071      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00072          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00073
00074    *** DMA mode IO operation ***
00075    ==============================
00076    [..]
00077      (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
00078      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
00079          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
00080      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
00081          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
00082      (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
00083      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
00084          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
00085      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
00086          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
00087      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00088          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00089      (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
00090      (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
00091      (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
00092
00093    *** I2S HAL driver macros list ***
00094    ===================================
00095    [..]
00096      Below the list of most used macros in I2S HAL driver.
00097
00098       (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
00099       (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
00100       (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
00101       (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
00102       (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
00103
00104     [..]
00105       (@) You can refer to the I2S HAL driver header file for more useful macros
00106
00107   @endverbatim
00108   ******************************************************************************
00109   * @attention
00110   *
00111   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00112   *
00113   * Redistribution and use in source and binary forms, with or without modification,
00114   * are permitted provided that the following conditions are met:
00115   *   1. Redistributions of source code must retain the above copyright notice,
00116   *      this list of conditions and the following disclaimer.
00117   *   2. Redistributions in binary form must reproduce the above copyright notice,
00118   *      this list of conditions and the following disclaimer in the documentation
00119   *      and/or other materials provided with the distribution.
00120   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00121   *      may be used to endorse or promote products derived from this software
00122   *      without specific prior written permission.
00123   *
00124   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00125   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00126   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00127   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00128   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00129   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00130   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00131   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00132   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00133   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00134   *
00135   ******************************************************************************
00136   */
00137
00138 /* Includes ------------------------------------------------------------------*/
00139 #include "stm32h7xx_hal.h"
00140
00141 /** @addtogroup STM32H7xx_HAL_Driver
00142   * @{
00143   */
00144
00145 #ifdef HAL_I2S_MODULE_ENABLED
00146
00147 /** @addtogroup I2S
00148   * @brief I2S HAL module driver
00149   * @{
00150   */
00151
00152
00153
00154 /* Private typedef -----------------------------------------------------------*/
00155 /* Private define ------------------------------------------------------------*/
00156 /* Private macro -------------------------------------------------------------*/
00157 /* Private variables ---------------------------------------------------------*/
00158 /* Private function prototypes -----------------------------------------------*/
00159 /** @addtogroup I2S_Private
00160   * @{
00161   */
00162 static void               I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
00163 static void               I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00164 static void               I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
00165 static void               I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00166 static void               I2S_DMAError(DMA_HandleTypeDef *hdma);
00167
00168 static void               I2S_TxISR_16BIT(struct __I2S_HandleTypeDef *hi2s);
00169 static void               I2S_TxISR_32BIT(struct __I2S_HandleTypeDef *hi2s);
00170 static void               I2S_RxISR_16BIT(struct __I2S_HandleTypeDef *hi2s);
00171 static void               I2S_RxISR_32BIT(struct __I2S_HandleTypeDef *hi2s);
00172 static void               I2S_CloseRx_ISR(I2S_HandleTypeDef *hi2s);
00173 static void               I2S_CloseTx_ISR(I2S_HandleTypeDef *hi2s);
00174
00175 static HAL_StatusTypeDef  I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
00176
00177 /**
00178   * @}
00179   */
00180
00181 /* Exported functions ---------------------------------------------------------*/
00182 /** @addtogroup I2S_Exported_Functions I2S Exported Functions
00183   * @{
00184   */
00185
00186 /** @addtogroup  I2S_Exported_Functions_Group1
00187   *  @brief    Initialization and Configuration functions
00188   *
00189 @verbatim
00190  ===============================================================================
00191               ##### Initialization and de-initialization functions #####
00192  ===============================================================================
00193     [..]  This subsection provides a set of functions allowing to initialize and
00194           de-initialiaze the I2Sx peripheral in simplex mode:
00195
00196       (+) User must Implement HAL_I2S_MspInit() function in which he configures
00197           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00198
00199       (+) Call the function HAL_I2S_Init() to configure the selected device with
00200           the selected configuration:
00201         (++) Mode
00202         (++) Standard
00203         (++) Data Format
00204         (++) MCLK Output
00205         (++) Audio frequency
00206         (++) Polarity
00207         (++) First Bit
00208         (++) WS Inversion
00209         (++) IO Swap
00210         (++) Data 24Bit Alignment
00211         (++) Fifo Threshold
00212         (++) Alternate function GPIOs state
00213         (++) Channel length in SLAVE
00214
00215      (+) Call the function HAL_I2S_DeInit() to restore the default configuration
00216          of the selected I2Sx periperal.
00217   @endverbatim
00218   * @{
00219   */
00220
00221 /**
00222   * @brief Initializes the I2S according to the specified parameters
00223   *         in the I2S_InitTypeDef and create the associated handle.
00224   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00225   *         the configuration information for I2S module
00226   * @retval HAL status
00227   */
00228 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
00229 {
00230   uint32_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
00231   uint32_t tmp = 0U, i2sclk = 0U;
00232
00233   /* Check the I2S handle allocation */
00234   if(hi2s == NULL)
00235   {
00236     return HAL_ERROR;
00237   }
00238
00239   /* Check the I2S parameters */
00240   assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
00241   assert_param(IS_I2S_MODE(hi2s->Init.Mode));
00242   assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
00243   assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
00244   assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
00245   assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
00246   assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
00247   assert_param(IS_I2S_FIRST_BIT(hi2s->Init.FirstBit));
00248   assert_param(IS_I2S_WS_INVERSION(hi2s->Init.WSInversion));
00249   assert_param(IS_I2S_IO_SWAP(hi2s->Init.IOSwap));
00250   assert_param(IS_I2S_DATA_24BIT_ALIGNMENT(hi2s->Init.Data24BitAlignment));
00251   assert_param(IS_I2S_FIFO_THRESHOLD(hi2s->Init.FifoThreshold));
00252   assert_param(IS_I2S_MASTER_KEEP_IO_STATE(hi2s->Init.MasterKeepIOState));
00253   assert_param(IS_I2S_SLAVE_EXTEND_FRE_DETECTION(hi2s->Init.SlaveExtendFREDetection));
00254
00255   if(hi2s->State == HAL_I2S_STATE_RESET)
00256   {
00257     /* Allocate lock resource and initialize it */
00258     hi2s->Lock = HAL_UNLOCKED;
00259
00260     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00261     HAL_I2S_MspInit(hi2s);
00262   }
00263
00264   hi2s->State = HAL_I2S_STATE_BUSY;
00265
00266   /* Clear I2S configuration register */
00267   CLEAR_REG(hi2s->Instance->I2SCFGR);
00268
00269   /* If the default value has to be written, reinitialize i2sdiv and i2sodd */
00270   if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
00271   {
00272     i2sodd = 0U;
00273     i2sdiv = 2U;
00274   }
00275   /* If the requested audio frequency is not the default, compute the prescaler */
00276   else
00277   {
00278     /* Check the frame length (For the Prescaler computing) *******************/
00279     /* Set I2S Packet Length value*/
00280     if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
00281     {
00282       /* Packet length is 32 bits */
00283       packetlength = 32U;
00284     }
00285     else
00286     {
00287       /* Packet length is 16 bits */
00288       packetlength = 16U;
00289     }
00290
00291     /* I2S standard */
00292     if(hi2s->Init.Standard <= I2S_STANDARD_LSB)
00293     {
00294       /* In I2S standard packet lenght is multiplied by 2 */
00295       packetlength = packetlength * 2U;
00296     }
00297
00298     /* Get the source clock value: based on System Clock value */
00299     /* SPI1,SPI2 and SPI3 share the same source clock */
00300     i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI1);
00301
00302     /* Compute the Real divider depending on the MCLK output state, with a floating point */
00303     if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
00304     {
00305       /* MCLK output is enabled */
00306       if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
00307       {
00308         tmp = (uint32_t)(((((i2sclk / (packetlength*4)) * 10) / hi2s->Init.AudioFreq)) + 5);
00309       }
00310       else
00311       {
00312         tmp = (uint32_t)(((((i2sclk / (packetlength*8)) * 10) / hi2s->Init.AudioFreq)) + 5);
00313       }
00314     }
00315     else
00316     {
00317       /* MCLK output is disabled */
00318       tmp = (uint32_t)(((((i2sclk / packetlength) *10 ) / hi2s->Init.AudioFreq)) + 5);
00319     }
00320
00321     /* Remove the flatting point */
00322     tmp = tmp / 10U;
00323
00324     /* Check the parity of the divider */
00325     i2sodd = (uint32_t)(tmp & (uint32_t)1U);
00326
00327     /* Compute the i2sdiv prescaler */
00328     i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
00329
00330     /* Get the Mask for the Odd bit I2SCFGR register */
00331     i2sodd = (uint32_t)(i2sodd << 24U);
00332   }
00333
00334   /* Test if the divider is 1 or 0 or greater than 0xFF */
00335   if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
00336   {
00337     /* Set the default values */
00338     i2sdiv = 2U;
00339     i2sodd = 0U;
00340     /* Set the error code */
00341     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
00342     return  HAL_ERROR;
00343   }
00344
00345   /* Check if the SPI2S is disabled to edit I2SCFGR and CFG1 register */
00346   if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE)
00347   {
00348     /* Disable SPI peripheral */
00349     __HAL_I2S_DISABLE(hi2s);
00350   }
00351
00352   /* Clear and configure SPI2S I2SCFGR register */
00353   MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_I2SMOD       | SPI_I2SCFGR_I2SCFG                 | \
00354                                        SPI_I2SCFGR_I2SSTD       | SPI_I2SCFGR_PCMSYNC                | \
00355                                        SPI_I2SCFGR_DATLEN       | SPI_I2SCFGR_CHLEN                  | \
00356                                        SPI_I2SCFGR_CKPOL        | SPI_I2SCFGR_FIXCH                  | \
00357                                        SPI_I2SCFGR_WSINV        | SPI_I2SCFGR_DATFMT                 | \
00358                                        SPI_I2SCFGR_I2SDIV       | SPI_I2SCFGR_ODD                    | \
00359                                        SPI_I2SCFGR_MCKOE),                                             \
00360                                       (SPI_I2SCFGR_I2SMOD       | hi2s->Init.Mode                    | \
00361                                        hi2s->Init.Standard      | hi2s->Init.DataFormat              | \
00362                                        hi2s->Init.CPOL          | hi2s->Init.SlaveExtendFREDetection | \
00363                                        hi2s->Init.WSInversion   | hi2s->Init.Data24BitAlignment      | \
00364                                       (uint32_t)(i2sdiv << 16U) | (uint32_t)(i2sodd)                 | \
00365                                        hi2s->Init.MCLKOutput));
00366
00367   /* Clear and configure SPI2S CFG1 register */
00368   MODIFY_REG(hi2s->Instance->CFG1, SPI_CFG1_FTHLV, (uint32_t)(hi2s->Init.FifoThreshold << 5U));
00369
00370   /* Unlock the AF configuration to configure CFG2 register*/
00371   CLEAR_BIT(hi2s->Instance->CR1 , SPI_CR1_IOLOCK);
00372
00373   /* Clear and configure SPI2S CFG2 register */
00374   MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_LSBFRST | SPI_CFG2_IOSWP , (hi2s->Init.FirstBit | hi2s->Init.IOSwap));
00375
00376   /* Insure that AFCNTR is managed only by Master */
00377   if (IS_I2S_MASTER(hi2s->Init.Mode))
00378   {
00379     /* Alternate function GPIOs control */
00380     MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_AFCNTR, (hi2s->Init.MasterKeepIOState));
00381   }
00382
00383   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00384   hi2s->State= HAL_I2S_STATE_READY;
00385
00386   return HAL_OK;
00387 }
00388
00389 /**
00390   * @brief  DeInitializes the I2S peripheral
00391   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00392   *         the configuration information for I2S module
00393   * @retval HAL status
00394   */
00395 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
00396 {
00397   /* Check the I2S handle allocation */
00398   if(hi2s == NULL)
00399   {
00400     return HAL_ERROR;
00401   }
00402
00403   /* Check the parameters */
00404   assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
00405
00406   hi2s->State = HAL_I2S_STATE_BUSY;
00407
00408   /* Disable the I2S Peripheral Clock */
00409   __HAL_I2S_DISABLE(hi2s);
00410
00411   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00412   HAL_I2S_MspDeInit(hi2s);
00413
00414   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00415   hi2s->State = HAL_I2S_STATE_RESET;
00416
00417   /* Release Lock */
00418   __HAL_UNLOCK(hi2s);
00419
00420   return HAL_OK;
00421 }
00422
00423 /**
00424   * @brief I2S MSP Init
00425   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00426   *         the configuration information for I2S module
00427   * @retval None
00428   */
00429  __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
00430 {
00431   /* Prevent unused argument(s) compilation warning */
00432   UNUSED(hi2s);
00433
00434   /* NOTE : This function Should not be modified, when the callback is needed,
00435             the HAL_I2S_MspInit could be implemented in the user file
00436    */
00437 }
00438
00439 /**
00440   * @brief I2S MSP DeInit
00441   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00442   *         the configuration information for I2S module
00443   * @retval None
00444   */
00445  __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
00446 {
00447   /* Prevent unused argument(s) compilation warning */
00448   UNUSED(hi2s);
00449
00450   /* NOTE : This function Should not be modified, when the callback is needed,
00451             the HAL_I2S_MspDeInit could be implemented in the user file
00452    */
00453 }
00454
00455 /**
00456   * @}
00457   */
00458
00459 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
00460   *  @brief Data transfers functions
00461   *
00462 @verbatim
00463  ===============================================================================
00464                       ##### IO operation functions #####
00465  ===============================================================================
00466     [..]
00467     This subsection provides a set of functions allowing to manage the I2S data
00468     transfers.
00469
00470     (#) There are two modes of transfer:
00471        (++) Blocking mode : The communication is performed in the polling mode.
00472             The status of all data processing is returned by the same function
00473             after finishing transfer.
00474        (++) No-Blocking mode : The communication is performed using Interrupts
00475             or DMA. These functions return the status of the transfer startup.
00476             The end of the data processing will be indicated through the
00477             dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
00478             using DMA mode.
00479
00480     (#) Blocking mode functions are :
00481         (++) HAL_I2S_Transmit()
00482         (++) HAL_I2S_Receive()
00483
00484     (#) No-Blocking mode functions with Interrupt are :
00485         (++) HAL_I2S_Transmit_IT()
00486         (++) HAL_I2S_Receive_IT()
00487
00488     (#) No-Blocking mode functions with DMA are :
00489         (++) HAL_I2S_Transmit_DMA()
00490         (++) HAL_I2S_Receive_DMA()
00491
00492     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00493         (++) HAL_I2S_TxCpltCallback()
00494         (++) HAL_I2S_TxHalfCpltCallback()
00495         (++) HAL_I2S_RxCpltCallback()
00496         (++) HAL_I2S_RxHalfCpltCallback()
00497         (++) HAL_I2S_ErrorCallback()
00498
00499 @endverbatim
00500   * @{
00501   */
00502
00503 /**
00504   * @brief  Transmit an amount of data in blocking mode
00505   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00506   *         the configuration information for I2S module
00507   * @param  pData: a 16-bit pointer to data buffer.
00508   * @param  Size: number of frames to be sent.
00509   * @param  Timeout: Timeout duration
00510   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00511   *         between Master and Slave(example: audio streaming).
00512   * @note   This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
00513   * @retval HAL status
00514   */
00515 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
00516 {
00517   uint32_t tickstart = 0U;
00518   uint32_t isDataFormat16B = 2U;
00519
00520   /* Check Mode parameter */
00521   assert_param(IS_I2S_TX_MODE(hi2s->Init.Mode));
00522
00523   if((pData == NULL ) || (Size == 0U))
00524   {
00525     return  HAL_ERROR;
00526   }
00527
00528   /* Process Locked */
00529   __HAL_LOCK(hi2s);
00530
00531   /* Init tickstart for timeout management*/
00532   tickstart = HAL_GetTick();
00533
00534   if(hi2s->State == HAL_I2S_STATE_READY)
00535   {
00536     /* Check the Data Format value */
00537     if (((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B) ||
00538         ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
00539     {
00540       isDataFormat16B = 0U;
00541     }
00542     else
00543     {
00544       isDataFormat16B = 1U;
00545     }
00546
00547     if(!isDataFormat16B)
00548     {
00549       hi2s->TxXferSize  = (Size << 1U);
00550       hi2s->TxXferCount = (Size << 1U);
00551     }
00552     else
00553     {
00554       hi2s->TxXferSize  = Size;
00555       hi2s->TxXferCount = Size;
00556     }
00557
00558     /* Set state and reset error code */
00559     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00560     hi2s->State = HAL_I2S_STATE_BUSY_TX;
00561     hi2s->pTxBuffPtr = pData;
00562
00563     /* Check if the SPI2S is already enabled */
00564     if((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00565     {
00566       /* Enable SPI peripheral */
00567       __HAL_I2S_ENABLE(hi2s);
00568     }
00569
00570     if(IS_I2S_MASTER(hi2s->Init.Mode))
00571     {
00572       hi2s->Instance->CR1 |= SPI_CR1_CSTART;
00573     }
00574
00575     /* Transmit data in 32 Bit mode */
00576     if (!isDataFormat16B)
00577     {
00578       while (hi2s->TxXferCount > 0U)
00579       {
00580         /* Wait until TXE flag is set to send data */
00581         if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE))
00582         {
00583           *((__IO uint32_t*)&hi2s->Instance->TXDR) = *((uint32_t*)hi2s->pTxBuffPtr);
00584           hi2s->pTxBuffPtr  += sizeof(uint32_t);
00585           hi2s->TxXferCount -= 2U;
00586         }
00587         else
00588         {
00589           /* Timeout management */
00590           if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
00591           {
00592             /* Set the error code and execute error callback*/
00593             SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00594             HAL_I2S_ErrorCallback(hi2s);
00595
00596             /* Set the I2S State ready */
00597             hi2s->State = HAL_I2S_STATE_READY;
00598
00599             /* Process Unlocked */
00600             __HAL_UNLOCK(hi2s);
00601             return HAL_ERROR;
00602           }
00603         }
00604       }
00605     }
00606     /* Transmit data in 16 Bit mode */
00607     else
00608     {
00609       while (hi2s->TxXferCount > 0U)
00610       {
00611         if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE))
00612         {
00613           if ((hi2s->TxXferCount > 1U) && (hi2s->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
00614           {
00615             *((__IO uint32_t*)&hi2s->Instance->TXDR) = *((uint32_t*)hi2s->pTxBuffPtr);
00616             hi2s->pTxBuffPtr  += sizeof(uint32_t);
00617             hi2s->TxXferCount -= 2U;
00618           }
00619           else
00620           {
00621             *((__IO uint16_t*)&hi2s->Instance->TXDR) = (*hi2s->pTxBuffPtr++);
00622             hi2s->TxXferCount--;
00623           }
00624         }
00625         else
00626         {
00627           /* Timeout management */
00628           if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
00629           {
00630             /* Set the error code and execute error callback*/
00631             SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00632             HAL_I2S_ErrorCallback(hi2s);
00633
00634             /* Set the I2S State ready */
00635             hi2s->State = HAL_I2S_STATE_READY;
00636
00637             /* Process Unlocked */
00638             __HAL_UNLOCK(hi2s);
00639             return HAL_ERROR;
00640           }
00641         }
00642       }
00643     }
00644
00645     /* Wait until TXE flag is set, to confirm the end of the transaction */
00646     if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
00647     {
00648       /* Set the error code and execute error callback*/
00649       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00650       HAL_I2S_ErrorCallback(hi2s);
00651
00652       /* Set the I2S State ready */
00653       hi2s->State = HAL_I2S_STATE_READY;
00654
00655       /* Process Unlocked */
00656       __HAL_UNLOCK(hi2s);
00657       return HAL_ERROR;
00658     }
00659
00660     hi2s->State = HAL_I2S_STATE_READY;
00661
00662     /* Process Unlocked */
00663     __HAL_UNLOCK(hi2s);
00664
00665     return HAL_OK;
00666   }
00667   else
00668   {
00669     /* Process Unlocked */
00670     __HAL_UNLOCK(hi2s);
00671     return HAL_BUSY;
00672   }
00673 }
00674
00675 /**
00676   * @brief  Receive an amount of data in blocking mode
00677   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00678   *         the configuration information for I2S module
00679   * @param  pData: a 16-bit pointer to data buffer.
00680   * @param  Size: number of frames to be sent.
00681   * @param  Timeout: Timeout duration
00682   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00683   *         between Master and Slave(example: audio streaming).
00684   * @note   In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
00685   *         in continuous way and as the I2S is not disabled at the end of the I2S transaction.
00686   * @note   This function can use an Audio Frequency up to 44KHz when I2S Clock Source is 32MHz
00687   * @retval HAL status
00688   */
00689 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
00690 {
00691   uint32_t tickstart = 0U;
00692   uint32_t isDataFormat16B = 2U;
00693
00694   /* Check Mode parameter */
00695   assert_param(IS_I2S_RX_MODE(hi2s->Init.Mode));
00696
00697   if((pData == NULL ) || (Size == 0U))
00698   {
00699     return  HAL_ERROR;
00700   }
00701
00702   /* Process Locked */
00703   __HAL_LOCK(hi2s);
00704
00705   /* Init tickstart for timeout management*/
00706   tickstart = HAL_GetTick();
00707
00708   if(hi2s->State == HAL_I2S_STATE_READY)
00709   {
00710     /* Check the Data Format value */
00711     if (((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B) ||
00712         ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
00713     {
00714       isDataFormat16B = 0U;
00715     }
00716     else
00717     {
00718       isDataFormat16B = 1U;
00719     }
00720
00721     if(!isDataFormat16B)
00722     {
00723       hi2s->RxXferSize = (Size << 1U);
00724       hi2s->RxXferCount = (Size << 1U);
00725     }
00726     else
00727     {
00728       hi2s->RxXferSize = Size;
00729       hi2s->RxXferCount = Size;
00730     }
00731
00732     /* Set state and reset error code */
00733     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00734     hi2s->State = HAL_I2S_STATE_BUSY_RX;
00735     hi2s->pRxBuffPtr = pData;
00736
00737     /* Check if the SPI2S is already enabled */
00738     if((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00739     {
00740       /* Enable SPI peripheral */
00741       __HAL_I2S_ENABLE(hi2s);
00742     }
00743
00744     if(IS_I2S_MASTER(hi2s->Init.Mode))
00745     {
00746       hi2s->Instance->CR1 |= SPI_CR1_CSTART;
00747     }
00748
00749     /* Check if Master Receiver mode is selected */
00750     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
00751     {
00752       /* Clear the Overrun Flag */
00753       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00754     }
00755
00756     /* Receive data in 32 Bit mode */
00757     if ((!isDataFormat16B))
00758     {
00759       /* Transfer loop */
00760       while (hi2s->RxXferCount > 0U)
00761       {
00762         /* Check the RXNE flag */
00763         if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE))
00764         {
00765           *((uint32_t *)hi2s->pRxBuffPtr) = *((__IO uint32_t *)&hi2s->Instance->RXDR);
00766           hi2s->pRxBuffPtr += sizeof(uint32_t);
00767           hi2s->RxXferCount--;
00768         }
00769         else
00770         {
00771           /* Timeout management */
00772           if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
00773           {
00774             /* Set the error code and execute error callback*/
00775             SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00776             HAL_I2S_ErrorCallback(hi2s);
00777
00778             /* Set the I2S State ready */
00779             hi2s->State = HAL_I2S_STATE_READY;
00780
00781             /* Process Unlocked */
00782             __HAL_UNLOCK(hi2s);
00783             return HAL_ERROR;
00784           }
00785         }
00786       }
00787     }
00788     /* Receive data in 16 Bit mode */
00789     else
00790     {
00791       /* Transfer loop */
00792       while (hi2s->RxXferCount > 0U)
00793       {
00794         /* Check the RXNE flag */
00795         if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE))
00796         {
00797           if (hi2s->Instance->SR & I2S_FLAG_RXWNE)
00798           {
00799             *((uint32_t *)hi2s->pRxBuffPtr) = *((__IO uint32_t *)&hi2s->Instance->RXDR);
00800             hi2s->pRxBuffPtr += sizeof(uint32_t);
00801             hi2s->RxXferCount-=2;
00802           }
00803           else
00804           {
00805             *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
00806             hi2s->pRxBuffPtr += sizeof(uint16_t);
00807             hi2s->RxXferCount--;
00808           }
00809         }
00810         else
00811         {
00812           /* Timeout management */
00813           if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
00814           {
00815             /* Set the error code and execute error callback*/
00816             SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00817             HAL_I2S_ErrorCallback(hi2s);
00818
00819             /* Set the I2S State ready */
00820             hi2s->State = HAL_I2S_STATE_READY;
00821
00822             /* Process Unlocked */
00823             __HAL_UNLOCK(hi2s);
00824             return HAL_ERROR;
00825           }
00826         }
00827       }
00828     }
00829
00830     hi2s->State = HAL_I2S_STATE_READY;
00831
00832     /* Process Unlocked */
00833     __HAL_UNLOCK(hi2s);
00834
00835     return HAL_OK;
00836   }
00837   else
00838   {
00839     /* Process Unlocked */
00840     __HAL_UNLOCK(hi2s);
00841     return HAL_BUSY;
00842   }
00843 }
00844
00845 /**
00846   * @brief  Transmit an amount of data in non-blocking mode with Interrupt
00847   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00848   *         the configuration information for I2S module
00849   * @param pData: a 16-bit pointer to data buffer.
00850   * @param Size: number of data sample to be sent:
00851   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00852   *       configuration phase, the Size parameter means the number of 16-bit data length
00853   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00854   *       the Size parameter means the number of 16-bit data length.
00855   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00856   *       between Master and Slave(example: audio streaming).
00857   * @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
00858   * @retval HAL status
00859   */
00860 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
00861 {
00862   /* Check Mode parameter */
00863   assert_param(IS_I2S_TX_MODE(hi2s->Init.Mode));
00864
00865   /* Process Locked */
00866   __HAL_LOCK(hi2s);
00867
00868   if((pData == NULL) || (Size == 0U))
00869   {
00870     __HAL_UNLOCK(hi2s);
00871     return  HAL_ERROR;
00872   }
00873
00874   if (hi2s->State == HAL_I2S_STATE_READY)
00875   {
00876     __HAL_UNLOCK(hi2s);
00877     return  HAL_BUSY;
00878   }
00879
00880   /* Set the transaction information */
00881   hi2s->State       = HAL_I2S_STATE_BUSY_TX;
00882   hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
00883   hi2s->pTxBuffPtr  = pData;
00884   hi2s->TxXferSize  = Size;
00885   hi2s->TxXferCount = Size;
00886
00887   /* Init field not used in handle to zero */
00888   hi2s->pRxBuffPtr  = NULL;
00889   hi2s->RxXferSize  = 0U;
00890   hi2s->RxXferCount = 0U;
00891   hi2s->RxISR       = NULL;
00892
00893   /* Set the function for IT treatment */
00894   if (hi2s->Init.DataFormat > I2S_DATAFORMAT_16B)
00895   {
00896     hi2s->TxISR = I2S_TxISR_32BIT;
00897   }
00898   else
00899   {
00900     hi2s->TxISR = I2S_TxISR_16BIT;
00901   }
00902
00903   /* Check if the I2S is already enabled */
00904   if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00905   {
00906     /* Enable SPI peripheral */
00907     __HAL_I2S_ENABLE(hi2s);
00908   }
00909
00910   if (IS_I2S_MASTER(hi2s->Init.Mode))
00911   {
00912     /* Master transfer start */
00913     SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
00914   }
00915
00916   /* Enable TXE and ERR interrupt */
00917   __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
00918
00919   /* Process Unlocked */
00920   __HAL_UNLOCK(hi2s);
00921
00922   return HAL_OK;
00923 }
00924
00925 /**
00926   * @brief  Receive an amount of data in non-blocking mode with Interrupt
00927   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00928   *         the configuration information for I2S module
00929   * @param pData: a 16-bit pointer to the Receive data buffer.
00930   * @param Size: number of data sample to be sent:
00931   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00932   *       configuration phase, the Size parameter means the number of 16-bit data length
00933   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00934   *       the Size parameter means the number of 16-bit data length.
00935   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00936   *       between Master and Slave(example: audio streaming).
00937   * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
00938   * between Master and Slave otherwise the I2S interrupt should be optimized.
00939   * @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
00940   * @retval HAL status
00941   */
00942 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
00943 {
00944   /* Check Mode parameter */
00945   assert_param(IS_I2S_RX_MODE(hi2s->Init.Mode));
00946
00947   /* Process Locked */
00948   __HAL_LOCK(hi2s);
00949
00950   /* Set the transaction information */
00951   hi2s->State       = HAL_I2S_STATE_BUSY_TX;
00952   hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
00953   hi2s->pRxBuffPtr  = pData;
00954   hi2s->RxXferSize  = Size;
00955   hi2s->RxXferCount = Size;
00956
00957   /* Init field not used in handle to zero */
00958   hi2s->pTxBuffPtr  = NULL;
00959   hi2s->TxXferSize  = 0U;
00960   hi2s->TxXferCount = 0U;
00961   hi2s->TxISR       = NULL;
00962
00963   /* Set the function for IT treatment */
00964   if (hi2s->Init.DataFormat > I2S_DATAFORMAT_16B)
00965   {
00966     hi2s->RxISR = I2S_RxISR_32BIT;
00967   }
00968   else
00969   {
00970     hi2s->RxISR = I2S_RxISR_16BIT;
00971   }
00972
00973   /* Check if the I2S is already enabled */
00974   if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00975   {
00976     /* Enable SPI peripheral */
00977     __HAL_I2S_ENABLE(hi2s);
00978   }
00979
00980   if (IS_I2S_MASTER(hi2s->Init.Mode))
00981   {
00982     /* Master transfer start */
00983     SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
00984   }
00985
00986   /* Enable TXE and ERR interrupt */
00987   __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
00988
00989   /* Process Unlocked */
00990   __HAL_UNLOCK(hi2s);
00991
00992   return HAL_OK;
00993 }
00994
00995 /**
00996   * @brief Transmit an amount of data in non-blocking mode with DMA
00997   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00998   *         the configuration information for I2S module
00999   * @param pData: a 16-bit pointer to the Transmit data buffer.
01000   * @param Size: number of data sample to be sent:
01001   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
01002   *       configuration phase, the Size parameter means the number of 16-bit data length
01003   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
01004   *       the Size parameter means the number of 16-bit data length.
01005   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
01006   *       between Master and Slave(example: audio streaming).
01007   * @retval HAL status
01008   */
01009 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
01010 {
01011   /* Check Mode parameter */
01012   assert_param(IS_I2S_TX_MODE(hi2s->Init.Mode));
01013
01014   if((pData == NULL) || (Size == 0U))
01015   {
01016     return  HAL_ERROR;
01017   }
01018
01019   /* Process Locked */
01020   __HAL_LOCK(hi2s);
01021
01022   if(hi2s->State == HAL_I2S_STATE_READY)
01023   {
01024     hi2s->pTxBuffPtr = pData;
01025     hi2s->State      = HAL_I2S_STATE_BUSY_TX;
01026     hi2s->ErrorCode  = HAL_I2S_ERROR_NONE;
01027
01028     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
01029       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
01030     {
01031       hi2s->TxXferSize  = (Size << 1U);
01032       hi2s->TxXferCount = (Size << 1U);
01033     }
01034     else
01035     {
01036       hi2s->TxXferSize  = Size;
01037       hi2s->TxXferCount = Size;
01038     }
01039
01040     /* Set the I2S Tx DMA Half transfert complete callback */
01041     hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
01042
01043     /* Set the I2S Tx DMA transfert complete callback */
01044     hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
01045
01046     /* Set the DMA error callback */
01047     hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
01048
01049     /* Enable the Tx DMA Channel */
01050     HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR, hi2s->TxXferSize);
01051
01052     /* Check if the I2S Tx request is already enabled */
01053     if(HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN))
01054     {
01055       /* Check if the SPI2S is disabled to edit CFG1 register */
01056       if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01057       {
01058         /* Enable Tx DMA Request */
01059         SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
01060       }
01061       else
01062       {
01063         /* Disable SPI peripheral */
01064         __HAL_I2S_DISABLE(hi2s);
01065
01066         /* Enable Tx DMA Request */
01067         SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
01068
01069         /* Enable SPI peripheral */
01070         __HAL_I2S_ENABLE(hi2s);
01071       }
01072     }
01073
01074     /* Process Unlocked */
01075     __HAL_UNLOCK(hi2s);
01076
01077     return HAL_OK;
01078   }
01079   else
01080   {
01081     /* Process Unlocked */
01082     __HAL_UNLOCK(hi2s);
01083     return HAL_BUSY;
01084   }
01085 }
01086
01087 /**
01088   * @brief Receive an amount of data in non-blocking mode with DMA
01089   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01090   *         the configuration information for I2S module
01091   * @param pData: a 16-bit pointer to the Receive data buffer.
01092   * @param Size: number of data sample to be sent:
01093   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
01094   *       configuration phase, the Size parameter means the number of 16-bit data length
01095   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
01096   *       the Size parameter means the number of 16-bit data length.
01097   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
01098   *       between Master and Slave(example: audio streaming).
01099   * @retval HAL status
01100   */
01101 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
01102 {
01103   /* Check Mode parameter */
01104   assert_param(IS_I2S_RX_MODE(hi2s->Init.Mode));
01105
01106   if((pData == NULL) || (Size == 0U))
01107   {
01108     return  HAL_ERROR;
01109   }
01110
01111   /* Process Locked */
01112   __HAL_LOCK(hi2s);
01113
01114   if(hi2s->State == HAL_I2S_STATE_READY)
01115   {
01116     hi2s->pRxBuffPtr = pData;
01117     hi2s->State = HAL_I2S_STATE_BUSY_RX;
01118     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
01119
01120     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
01121       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
01122     {
01123       hi2s->RxXferSize = (Size << 1U);
01124       hi2s->RxXferCount = (Size << 1U);
01125     }
01126     else
01127     {
01128       hi2s->RxXferSize = Size;
01129       hi2s->RxXferCount = Size;
01130     }
01131
01132     /* Set the I2S Rx DMA Half transfert complete callback */
01133     hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
01134
01135     /* Set the I2S Rx DMA transfert complete callback */
01136     hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
01137
01138     /* Set the DMA error callback */
01139     hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
01140
01141     /* Check if Master Receiver mode is selected */
01142     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
01143     {
01144       /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
01145       access to the SPI_SR register. */
01146       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
01147     }
01148
01149     /* Enable the Rx DMA Channel */
01150     HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize);
01151
01152     /* Check if the I2S Rx request is already enabled */
01153     if(HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN))
01154     {
01155       /* Check if the SPI2S is disabled to edit CFG1 register */
01156       if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01157       {
01158         /* Enable Rx DMA Request */
01159         SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
01160       }
01161       else
01162       {
01163         /* Disable SPI peripheral */
01164         __HAL_I2S_DISABLE(hi2s);
01165
01166         /* Enable Rx DMA Request */
01167         SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
01168
01169         /* Enable SPI peripheral */
01170         __HAL_I2S_ENABLE(hi2s);
01171       }
01172     }
01173
01174     /* Process Unlocked */
01175     __HAL_UNLOCK(hi2s);
01176
01177     return HAL_OK;
01178   }
01179   else
01180   {
01181     /* Process Unlocked */
01182     __HAL_UNLOCK(hi2s);
01183     return HAL_BUSY;
01184   }
01185 }
01186
01187 /**
01188   * @brief Pauses the audio stream playing from the Media.
01189   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01190   *         the configuration information for I2S module
01191   * @retval HAL status
01192   */
01193 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
01194 {
01195   /* Process Locked */
01196   __HAL_LOCK(hi2s);
01197
01198   /* Check if the SPI2S is disabled to edit CFG1 register */
01199   if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01200   {
01201     /* Disable the I2S DMA Tx & Rx requests */
01202     CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
01203   }
01204   else
01205   {
01206     /* Disable SPI peripheral */
01207     __HAL_I2S_DISABLE(hi2s);
01208
01209     /* Disable the I2S DMA Tx & Rx requests */
01210     CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
01211
01212     /* Enable SPI peripheral */
01213     __HAL_I2S_ENABLE(hi2s);
01214   }
01215
01216   /* Process Unlocked */
01217   __HAL_UNLOCK(hi2s);
01218
01219   return HAL_OK;
01220 }
01221
01222 /**
01223   * @brief Resumes the audio stream playing from the Media.
01224   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01225   *         the configuration information for I2S module
01226   * @retval HAL status
01227   */
01228 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
01229 {
01230   /* Process Locked */
01231   __HAL_LOCK(hi2s);
01232
01233   /* Check if the SPI2S is disabled to edit CFG1 register */
01234   if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01235   {
01236     /* Enable the I2S DMA Tx & Rx requests */
01237     SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
01238   }
01239   else
01240   {
01241     /* Disable SPI peripheral */
01242     __HAL_I2S_DISABLE(hi2s);
01243
01244     /*  Enable the I2S DMA Tx & Rx requests */
01245     SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
01246   }
01247
01248   /* Enable I2S peripheral */
01249   __HAL_I2S_ENABLE(hi2s);
01250
01251   /* Process Unlocked */
01252   __HAL_UNLOCK(hi2s);
01253
01254   return HAL_OK;
01255 }
01256
01257 /**
01258   * @brief Stops the audio stream playing from the Media.
01259   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01260   *         the configuration information for I2S module
01261   * @retval HAL status
01262   */
01263 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
01264 {
01265   /* Process Locked */
01266   __HAL_LOCK(hi2s);
01267
01268   /* Check if the SPI2S is disabled to edit CFG1 register */
01269   if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01270   {
01271     /* Disable the I2S Tx/Rx DMA requests */
01272     CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
01273     CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
01274   }
01275   else
01276   {
01277     /* Disable SPI peripheral */
01278     __HAL_I2S_DISABLE(hi2s);
01279
01280     /* Disable the I2S Tx/Rx DMA requests */
01281     CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
01282     CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
01283
01284     /* Enable SPI peripheral */
01285     __HAL_I2S_ENABLE(hi2s);
01286   }
01287
01288   /* Abort the I2S DMA Channel tx */
01289   if(hi2s->hdmatx != NULL)
01290   {
01291     /* Disable the I2S DMA channel */
01292     __HAL_DMA_DISABLE(hi2s->hdmatx);
01293     HAL_DMA_Abort(hi2s->hdmatx);
01294   }
01295   /* Abort the I2S DMA Channel rx */
01296   if(hi2s->hdmarx != NULL)
01297   {
01298     /* Disable the I2S DMA channel */
01299     __HAL_DMA_DISABLE(hi2s->hdmarx);
01300     HAL_DMA_Abort(hi2s->hdmarx);
01301   }
01302
01303   /* Disable I2S peripheral */
01304   __HAL_I2S_DISABLE(hi2s);
01305
01306   hi2s->State = HAL_I2S_STATE_READY;
01307
01308   /* Process Unlocked */
01309   __HAL_UNLOCK(hi2s);
01310
01311   return HAL_OK;
01312 }
01313
01314 /**
01315   * @brief  This function handles I2S interrupt request.
01316   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01317   *         the configuration information for I2S module
01318   * @retval None
01319   */
01320 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
01321 {
01322   uint32_t itsource = hi2s->Instance->IER;
01323   uint32_t i2ssr = hi2s->Instance->SR;
01324
01325   /* I2S in mode Receiver ------------------------------------------------*/
01326   if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) &&
01327      ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && ((itsource & I2S_IT_RXNE) != RESET))
01328   {
01329     hi2s->RxISR(hi2s);
01330     return;
01331   }
01332
01333   /* I2S in mode Transmitter ---------------------------------------------*/
01334   if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && ((itsource & I2S_IT_RXNE) != RESET))
01335   {
01336     hi2s->TxISR(hi2s);
01337     return;
01338   }
01339
01340   /* I2S interrupt error -------------------------------------------------*/
01341   if((itsource & I2S_IT_ERR) != RESET)
01342   {
01343     /* I2S Overrun error interrupt occured ---------------------------------*/
01344     if((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR)
01345     {
01346       /* Disable RXNE and ERR interrupt */
01347       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
01348
01349       /* Set the error code and execute error callback*/
01350       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
01351     }
01352
01353     /* I2S Underrun error interrupt occured --------------------------------*/
01354     if((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR)
01355     {
01356       /* Disable TXE and ERR interrupt */
01357       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
01358
01359       /* Set the error code and execute error callback*/
01360       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
01361     }
01362
01363     /* Set the I2S State ready */
01364     hi2s->State = HAL_I2S_STATE_READY;
01365     /* Call the Error Callback */
01366     HAL_I2S_ErrorCallback(hi2s);
01367   }
01368 }
01369
01370
01371 /**
01372   * @brief This function handles I2S Communication Timeout.
01373   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01374   *         the configuration information for I2S module
01375   * @param Flag: Flag checked
01376   * @param State: Value of the flag expected
01377   * @param Timeout: Duration of the timeout
01378   * @retval HAL status
01379   */
01380 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
01381 {
01382   uint32_t tickstart = 0U;
01383
01384   /* Get tick */
01385   tickstart = HAL_GetTick();
01386
01387   /* Wait until flag is set */
01388   while ((__HAL_I2S_GET_FLAG(hi2s, Flag) ? SET : RESET) != State)
01389   {
01390     if(Timeout != HAL_MAX_DELAY)
01391     {
01392       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01393       {
01394         /* Set the I2S State ready */
01395         hi2s->State= HAL_I2S_STATE_READY;
01396
01397         /* Process Unlocked */
01398         __HAL_UNLOCK(hi2s);
01399
01400         return HAL_TIMEOUT;
01401       }
01402     }
01403   }
01404
01405   return HAL_OK;
01406 }
01407
01408 /**
01409   * @brief Tx Transfer Half completed callbacks
01410   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01411   *         the configuration information for I2S module
01412   * @retval None
01413   */
01414  __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
01415 {
01416   /* Prevent unused argument(s) compilation warning */
01417   UNUSED(hi2s);
01418
01419   /* NOTE : This function Should not be modified, when the callback is needed,
01420             the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
01421    */
01422 }
01423
01424 /**
01425   * @brief  Tx Transfer completed callbacks
01426   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01427   *         the configuration information for I2S module
01428   * @retval None
01429   */
01430  __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
01431 {
01432   /* Prevent unused argument(s) compilation warning */
01433   UNUSED(hi2s);
01434
01435   /* NOTE : This function Should not be modified, when the callback is needed,
01436             the HAL_I2S_TxCpltCallback could be implemented in the user file
01437    */
01438 }
01439
01440 /**
01441   * @brief  Rx Transfer half completed callbacks
01442   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01443   *         the configuration information for I2S module
01444   * @retval None
01445   */
01446 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
01447 {
01448   /* Prevent unused argument(s) compilation warning */
01449   UNUSED(hi2s);
01450
01451   /* NOTE : This function Should not be modified, when the callback is needed,
01452             the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
01453    */
01454 }
01455
01456 /**
01457   * @brief Rx Transfer completed callbacks
01458   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01459   *         the configuration information for I2S module
01460   * @retval None
01461   */
01462 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
01463 {
01464   /* Prevent unused argument(s) compilation warning */
01465   UNUSED(hi2s);
01466
01467   /* NOTE : This function Should not be modified, when the callback is needed,
01468             the HAL_I2S_RxCpltCallback could be implemented in the user file
01469    */
01470 }
01471
01472 /**
01473   * @brief I2S error callbacks
01474   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01475   *         the configuration information for I2S module
01476   * @retval None
01477   */
01478  __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
01479 {
01480   /* Prevent unused argument(s) compilation warning */
01481   UNUSED(hi2s);
01482
01483   /* NOTE : This function Should not be modified, when the callback is needed,
01484             the HAL_I2S_ErrorCallback could be implemented in the user file
01485    */
01486 }
01487
01488 /**
01489   * @}
01490   */
01491
01492 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
01493   *  @brief   Peripheral State functions
01494   *
01495 @verbatim
01496  ===============================================================================
01497                       ##### Peripheral State and Errors functions #####
01498  ===============================================================================
01499     [..]
01500     This subsection permits to get in run-time the status of the peripheral
01501     and the data flow.
01502
01503 @endverbatim
01504   * @{
01505   */
01506
01507 /**
01508   * @brief  Return the I2S state
01509   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01510   *         the configuration information for I2S module
01511   * @retval HAL state
01512   */
01513 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
01514 {
01515   return hi2s->State;
01516 }
01517
01518 /**
01519   * @brief  Return the I2S error code
01520   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01521   *         the configuration information for I2S module
01522   * @retval I2S Error Code
01523   */
01524 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
01525 {
01526   return hi2s->ErrorCode;
01527 }
01528 /**
01529   * @}
01530   */
01531
01532 /**
01533   * @}
01534   */
01535
01536 /* Private functions ---------------------------------------------------------*/
01537 /** @addtogroup I2S_Private
01538   * @{
01539   */
01540 /**
01541   * @brief  DMA I2S transmit process complete callback
01542   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01543   *                the configuration information for the specified DMA module.
01544   * @retval None
01545   */
01546 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
01547 {
01548   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01549
01550   if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U)
01551   {
01552     /* Check if the SPI2S is disabled to edit CFG1 register */
01553     if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01554     {
01555       /* Disable Tx DMA Request */
01556       CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
01557     }
01558     else
01559     {
01560       /* Disable SPI peripheral */
01561       __HAL_I2S_DISABLE(hi2s);
01562
01563       /* Disable Tx DMA Request */
01564       CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
01565
01566       /* Enable SPI peripheral */
01567       __HAL_I2S_ENABLE(hi2s);
01568     }
01569
01570     hi2s->TxXferCount = 0U;
01571
01572     if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
01573     {
01574       if(hi2s->RxXferCount == 0U)
01575       {
01576         hi2s->State = HAL_I2S_STATE_READY;
01577       }
01578     }
01579     else
01580     {
01581       hi2s->State = HAL_I2S_STATE_READY;
01582     }
01583   }
01584   HAL_I2S_TxCpltCallback(hi2s);
01585 }
01586
01587 /**
01588   * @brief  DMA I2S transmit process half complete callback
01589   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01590                   the configuration information for the specified DMA module.
01591   * @retval None
01592   */
01593 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01594 {
01595   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01596
01597   HAL_I2S_TxHalfCpltCallback(hi2s);
01598 }
01599
01600 /**
01601   * @brief  DMA I2S receive process complete callback
01602   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01603   *                the configuration information for the specified DMA module.
01604   * @retval None
01605   */
01606 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
01607 {
01608   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01609
01610   if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U)
01611   {
01612     /* Check if the SPI2S is disabled to edit CFG1 register */
01613     if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01614     {
01615       /* Disable Rx DMA Request */
01616       CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
01617     }
01618     else
01619     {
01620       /* Disable SPI peripheral */
01621       __HAL_I2S_DISABLE(hi2s);
01622
01623       /* Disable Rx DMA Request */
01624       CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
01625
01626       /* Enable SPI peripheral */
01627       __HAL_I2S_ENABLE(hi2s);
01628     }
01629
01630     hi2s->RxXferCount = 0U;
01631     if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
01632     {
01633       if(hi2s->TxXferCount == 0U)
01634       {
01635         hi2s->State = HAL_I2S_STATE_READY;
01636       }
01637     }
01638     else
01639     {
01640       hi2s->State = HAL_I2S_STATE_READY;
01641     }
01642   }
01643   HAL_I2S_RxCpltCallback(hi2s);
01644 }
01645
01646 /**
01647   * @brief  DMA I2S receive process half complete callback
01648   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01649   *                the configuration information for the specified DMA module.
01650   * @retval None
01651   */
01652 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01653 {
01654   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01655
01656   HAL_I2S_RxHalfCpltCallback(hi2s);
01657 }
01658
01659 /**
01660   * @brief  DMA I2S communication error callback
01661   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01662   *               the configuration information for the specified DMA module.
01663   * @retval None
01664   */
01665 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
01666 {
01667   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01668
01669   /* Check if the SPI2S is disabled to edit CFG1 register */
01670   if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01671   {
01672     /* Disable Rx and Tx DMA Request */
01673     CLEAR_BIT(hi2s->Instance->CFG1, (SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN));
01674   }
01675   else
01676   {
01677     /* Disable SPI peripheral */
01678     __HAL_I2S_DISABLE(hi2s);
01679
01680     /* Disable Rx and Tx DMA Request */
01681     CLEAR_BIT(hi2s->Instance->CFG1, (SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN));
01682
01683     /* Enable SPI peripheral */
01684     __HAL_I2S_ENABLE(hi2s);
01685   }
01686
01687   hi2s->TxXferCount = 0U;
01688   hi2s->RxXferCount = 0U;
01689
01690   hi2s->State= HAL_I2S_STATE_READY;
01691
01692   /* Set the error code and execute error callback*/
01693   SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
01694   HAL_I2S_ErrorCallback(hi2s);
01695 }
01696
01697 /**
01698   * @brief  Manage the 16-bit receive in Interrupt context.
01699   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01700   *         the configuration information for I2S module
01701   * @retval None
01702   */
01703 static void I2S_RxISR_16BIT(struct __I2S_HandleTypeDef *hi2s)
01704 {
01705   *((uint16_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
01706   hi2s->pRxBuffPtr += sizeof(uint16_t);
01707   hi2s->RxXferCount--;
01708
01709   if (hi2s->RxXferCount == 0U)
01710   {
01711     I2S_CloseRx_ISR(hi2s);
01712   }
01713 }
01714
01715 /**
01716   * @brief  Manage the 32-bit receive in Interrupt context.
01717   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01718   *         the configuration information for I2S module
01719   * @retval None
01720   */
01721 static void I2S_RxISR_32BIT(struct __I2S_HandleTypeDef *hi2s)
01722 {
01723   *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
01724   hi2s->pRxBuffPtr += sizeof(uint32_t);
01725   hi2s->RxXferCount--;
01726
01727   if (hi2s->RxXferCount == 0U)
01728   {
01729     I2S_CloseRx_ISR(hi2s);
01730   }
01731 }
01732
01733 /**
01734   * @brief  Handle the data 16-bit transmit in Interrupt mode.
01735   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01736   *         the configuration information for I2S module
01737   * @retval None
01738   */
01739 static void I2S_TxISR_16BIT(struct __I2S_HandleTypeDef *hi2s)
01740 {
01741   /* Transmit data in 16 Bit mode */
01742   *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr);
01743   hi2s->pTxBuffPtr += sizeof(uint16_t);
01744   hi2s->TxXferCount--;
01745
01746   if (hi2s->TxXferCount == 0U)
01747   {
01748     I2S_CloseTx_ISR(hi2s);
01749   }
01750 }
01751
01752 /**
01753   * @brief  Handle the data 32-bit transmit in Interrupt mode.
01754   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01755   *         the configuration information for I2S module
01756   * @retval None
01757   */
01758 static void I2S_TxISR_32BIT(struct __I2S_HandleTypeDef *hi2s)
01759 {
01760   /* Transmit data in 16 Bit mode */
01761   *((__IO uint32_t *)&hi2s->Instance->TXDR) = *((uint32_t *)hi2s->pTxBuffPtr);
01762   hi2s->pTxBuffPtr += sizeof(uint32_t);
01763   hi2s->TxXferCount--;
01764
01765   if (hi2s->TxXferCount == 0U)
01766   {
01767     I2S_CloseTx_ISR(hi2s);
01768   }
01769 }
01770
01771 /**
01772   * @brief  Handle the end of the RX transaction.
01773   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01774   *         the configuration information for I2S module
01775   * @retval None
01776   */
01777 static void I2S_CloseRx_ISR(I2S_HandleTypeDef *hi2s)
01778 {
01779   /* Disable RXNE and ERR interrupt */
01780   __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
01781
01782   /* Clear underrun flag in 1 Line communication mode because transmitted is not feeded */
01783   if (IS_I2S_FD_MODE(hi2s->Init.Mode))
01784   {
01785     *((__IO uint8_t *)&hi2s->Instance->TXDR) = 0x01U;
01786     __HAL_I2S_CLEAR_UDRFLAG(hi2s);
01787   }
01788
01789   hi2s->State = HAL_I2S_STATE_READY;
01790
01791   if (hi2s->ErrorCode == HAL_I2S_ERROR_NONE)
01792   {
01793     HAL_I2S_RxCpltCallback(hi2s);
01794   }
01795   else
01796   {
01797     HAL_I2S_ErrorCallback(hi2s);
01798   }
01799 }
01800
01801 /**
01802   * @brief  Handle the end of the TX transaction.
01803   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01804   *         the configuration information for I2S module
01805   * @retval None
01806   */
01807 static void I2S_CloseTx_ISR(I2S_HandleTypeDef *hi2s)
01808 {
01809   /* Disable TXE and ERR interrupt */
01810   __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
01811
01812   /* Clear overrun flag in 2 Lines communication mode because received is not read */
01813   if (IS_I2S_FD_MODE(hi2s->Init.Mode))
01814   {
01815     __HAL_I2S_CLEAR_OVRFLAG(hi2s);
01816   }
01817
01818   hi2s->State = HAL_I2S_STATE_READY;
01819   if (hi2s->ErrorCode != HAL_SPI_ERROR_NONE)
01820   {
01821     HAL_I2S_ErrorCallback(hi2s);
01822   }
01823   else
01824   {
01825     HAL_I2S_TxCpltCallback(hi2s);
01826   }
01827 }
01828
01829 /**
01830   * @}
01831   */
01832 #endif /* HAL_I2S_MODULE_ENABLED */
01833
01834 /**
01835   * @}
01836   */
01837
01838 /**
01839   * @}
01840   */
01841
01842 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
01843
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_i2s.h Source File

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stm32h7xx_hal_i2s.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_i2s.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of I2S HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_I2S_H
00040 #define __STM32H7xx_HAL_I2S_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup I2S
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup I2S_Exported_Types I2S Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief I2S Init structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Mode;                            /*!< Specifies the I2S operating mode.
00068                                                  This parameter can be a value of @ref I2S_Mode                    */
00069
00070   uint32_t Standard;                        /*!< Specifies the standard used for the I2S communication.
00071                                                  This parameter can be a value of @ref I2S_Standard                */
00072
00073   uint32_t DataFormat;                      /*!< Specifies the data format for the I2S communication.
00074                                                  This parameter can be a value of @ref I2S_Data_Format             */
00075
00076   uint32_t MCLKOutput;                      /*!< Specifies whether the I2S MCLK output is enabled or not.
00077                                                  This parameter can be a value of @ref I2S_MCLK_Output             */
00078
00079   uint32_t AudioFreq;                       /*!< Specifies the frequency selected for the I2S communication.
00080                                                  This parameter can be a value of @ref I2S_Audio_Frequency         */
00081
00082   uint32_t CPOL;                            /*!< Specifies the idle state of the I2S clock.
00083                                                  This parameter can be a value of @ref I2S_Clock_Polarity          */
00084
00085   uint32_t FirstBit;                        /*!< Specifies whether data transfers start from MSB or LSB bit.
00086                                                  This parameter can be a value of @ref I2S_MSB_LSB_transmission    */
00087
00088   uint32_t WSInversion;                     /*!< Control the Word Select Inversion.
00089                                                  This parameter can be a value of @ref I2S_WSInversion             */
00090
00091   uint32_t IOSwap;                          /*!< Invert MISO/MOSI alternate functions
00092                                                  This parameter can be a value of @ref I2S_IO_Swap                 */
00093
00094   uint32_t Data24BitAlignment;              /*!< Specifies the Data Padding for 24 bits data lenght
00095                                                  This parameter can be a value of @ref I2S_Data_24Bit_Alignment    */
00096
00097   uint32_t FifoThreshold;                   /*!< Specifies the FIFO threshold level.
00098                                                  This parameter can be a value of @ref I2S_Fifo_Threshold          */
00099
00100   uint32_t MasterKeepIOState;               /*!< Control of Alternate function GPIOs state
00101                                                  This parameter can be a value of @ref I2S_Master_Keep_IO_State    */
00102
00103   uint32_t SlaveExtendFREDetection;         /*!< Control the channel length in SLAVE.
00104                                                  This parameter can be a value of @ref I2S_SlaveExtendFREDetection */
00105
00106
00107 }I2S_InitTypeDef;
00108
00109 /**
00110   * @brief  HAL State structures definition
00111   */
00112 typedef enum
00113 {
00114   HAL_I2S_STATE_RESET      = 0x00U,         /*!< I2S not yet initialized or disabled                */
00115   HAL_I2S_STATE_READY      = 0x01U,         /*!< I2S initialized and ready for use                  */
00116   HAL_I2S_STATE_BUSY       = 0x02U,         /*!< I2S internal process is ongoing                    */
00117   HAL_I2S_STATE_BUSY_TX    = 0x03U,         /*!< Data Transmission process is ongoing               */
00118   HAL_I2S_STATE_BUSY_RX    = 0x04U,         /*!< Data Reception process is ongoing                  */
00119   HAL_I2S_STATE_BUSY_TX_RX = 0x05U,         /*!< Data Transmission and Reception process is ongoing */
00120   HAL_I2S_STATE_TIMEOUT    = 0x06U,         /*!< I2S timeout state                                  */
00121   HAL_I2S_STATE_ERROR      = 0x07U          /*!< I2S error state                                    */
00122 }HAL_I2S_StateTypeDef;
00123
00124 /**
00125   * @brief I2S handle Structure definition
00126   */
00127 typedef struct __I2S_HandleTypeDef
00128 {
00129   SPI_TypeDef               *Instance;                 /*!< I2S registers base address              */
00130
00131   I2S_InitTypeDef            Init;                     /*!< I2S communication parameters            */
00132
00133   uint16_t                  *pTxBuffPtr;               /*!< Pointer to I2S Tx transfer buffer       */
00134
00135   __IO uint16_t              TxXferSize;               /*!< I2S Tx transfer size                    */
00136
00137   __IO uint16_t              TxXferCount;              /*!< I2S Tx transfer Counter                 */
00138
00139   uint16_t                  *pRxBuffPtr;               /*!< Pointer to I2S Rx transfer buffer       */
00140
00141   __IO uint16_t              RxXferSize;               /*!< I2S Rx transfer size                    */
00142
00143   __IO uint16_t              RxXferCount;              /*!< I2S Rx transfer counter                 */
00144
00145   void (*RxISR)(struct __I2S_HandleTypeDef *hi2s);     /*!< function pointer on Rx ISR              */
00146
00147   void (*TxISR)(struct __I2S_HandleTypeDef *hi2s);     /*!< function pointer on Tx ISR              */
00148
00149   DMA_HandleTypeDef         *hdmatx;                   /*!< I2S Tx DMA handle parameters            */
00150
00151   DMA_HandleTypeDef         *hdmarx;                   /*!< I2S Rx DMA handle parameters            */
00152
00153   __IO HAL_LockTypeDef       Lock;                     /*!< I2S locking object                      */
00154
00155   __IO HAL_I2S_StateTypeDef  State;                    /*!< I2S communication state                 */
00156
00157   __IO uint32_t              ErrorCode;                /*!< I2S Error code                          */
00158
00159 }I2S_HandleTypeDef;
00160 /**
00161   * @}
00162   */
00163
00164 /* Exported constants --------------------------------------------------------*/
00165 /** @defgroup I2S_Exported_Constants I2S Exported Constants
00166   * @{
00167   */
00168
00169 /**
00170   * @defgroup  I2S_Error_Defintion I2S Error Defintion
00171   * @brief     I2S Error Code
00172   * @{
00173   */
00174 #define HAL_I2S_ERROR_NONE                       (0x00000000U)    /*!< No error                    */
00175 #define HAL_I2S_ERROR_UDR                        (0x00000001U)    /*!< I2S Underrun error          */
00176 #define HAL_I2S_ERROR_OVR                        (0x00000002U)    /*!< I2S Overrun error           */
00177 #define HAL_I2S_ERROR_FRE                        (0x00000004U)    /*!< I2S Frame format error      */
00178 #define HAL_I2S_ERROR_DMA                        (0x00000008U)    /*!< DMA transfer error          */
00179 #define HAL_I2S_ERROR_DMA                        (0x00000008U)    /*!< DMA transfer error          */
00180 #define HAL_I2S_ERROR_TIMEOUT                    (0x00000010U)    /*!< Timeout error               */
00181 #define HAL_I2S_ERROR_PRESCALER                  (0x00000020U)    /*!< Prescaler error             */
00182   /**
00183     * @}
00184     */
00185
00186 /** @defgroup I2S_Mode I2S Mode
00187   * @{
00188   */
00189 #define I2S_MODE_SLAVE_TX                        (0x00000000U)
00190 #define I2S_MODE_SLAVE_RX                        (0x00000002U)
00191 #define I2S_MODE_MASTER_TX                       (0x00000004U)
00192 #define I2S_MODE_MASTER_RX                       (0x00000006U)
00193 #define I2S_MODE_SLAVE_FD                        (0x00000008U)
00194 #define I2S_MODE_MASTER_FD                       (0x0000000AU)
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup I2S_Standard I2S Standard
00200   * @{
00201   */
00202 #define I2S_STANDARD_PHILIPS                     (0x00000000U)
00203 #define I2S_STANDARD_MSB                         (0x00000010U)
00204 #define I2S_STANDARD_LSB                         (0x00000020U)
00205 #define I2S_STANDARD_PCM_SHORT                   (0x00000030U)
00206 #define I2S_STANDARD_PCM_LONG                    (0x000000B0U)
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup I2S_Data_Format I2S Data Format
00212   * @{
00213   */
00214 #define I2S_DATAFORMAT_16B                       (0x00000000U)
00215 #define I2S_DATAFORMAT_16B_EXTENDED              (0x00000400U)
00216 #define I2S_DATAFORMAT_24B                       (0x00000500U)
00217 #define I2S_DATAFORMAT_32B                       (0x00000600U)
00218 /**
00219   * @}
00220   */
00221
00222 /** @defgroup I2S_MCLK_Output I2S MCLK Output
00223   * @{
00224   */
00225 #define I2S_MCLKOUTPUT_ENABLE                    SPI_I2SCFGR_MCKOE
00226 #define I2S_MCLKOUTPUT_DISABLE                   (0x00000000U)
00227 /**
00228   * @}
00229   */
00230
00231 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency
00232   * @{
00233   */
00234 #define I2S_AUDIOFREQ_192K                       (192000U)
00235 #define I2S_AUDIOFREQ_96K                        (96000U)
00236 #define I2S_AUDIOFREQ_48K                        (48000U)
00237 #define I2S_AUDIOFREQ_44K                        (44100U)
00238 #define I2S_AUDIOFREQ_32K                        (32000U)
00239 #define I2S_AUDIOFREQ_22K                        (22050U)
00240 #define I2S_AUDIOFREQ_16K                        (16000U)
00241 #define I2S_AUDIOFREQ_11K                        (11025U)
00242 #define I2S_AUDIOFREQ_8K                         (8000U)
00243 #define I2S_AUDIOFREQ_DEFAULT                    (2U)
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup I2S_Clock_Polarity I2S Clock Polarity
00249   * @{
00250   */
00251 #define I2S_CPOL_LOW                            (0x00000000U)
00252 #define I2S_CPOL_HIGH                           SPI_I2SCFGR_CKPOL
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup I2S_MSB_LSB_transmission I2S MSB LSB Transmission
00258   * @{
00259   */
00260 #define I2S_FIRSTBIT_MSB                        (0x00000000U)
00261 #define I2S_FIRSTBIT_LSB                        SPI_CFG2_LSBFRST
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup I2S_WSInversion I2S Word Select Inversion
00267   * @{
00268   */
00269 #define I2S_WS_INVERSION_DISABLE                (0x00000000U)
00270 #define I2S_WS_INVERSION_ENABLE                 SPI_I2SCFGR_WSINV
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup I2S_IO_Swap Control I2S IO Swap
00276   * @{
00277   */
00278 #define I2S_IO_SWAP_DISABLE                     (0x00000000U)
00279 #define I2S_IO_SWAP_ENABLE                      SPI_CFG2_IOSWP
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup I2S_Data_24Bit_Alignment Data Padding 24Bit
00285   * @{
00286   */
00287 #define I2S_DATA_24BIT_ALIGNMENT_RIGHT         (0x00000000U)
00288 #define I2S_DATA_24BIT_ALIGNMENT_LEFT          SPI_I2SCFGR_DATFMT
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup I2S_Fifo_Threshold I2S Fifo Threshold
00294   * @{
00295   */
00296 #define I2S_FIFO_THRESHOLD_01DATA              (0x00000000U)
00297 #define I2S_FIFO_THRESHOLD_02DATA              (0x00000020U)
00298 #define I2S_FIFO_THRESHOLD_03DATA              (0x00000040U)
00299 #define I2S_FIFO_THRESHOLD_04DATA              (0x00000060U)
00300 #define I2S_FIFO_THRESHOLD_05DATA              (0x00000080U)
00301 #define I2S_FIFO_THRESHOLD_06DATA              (0x000000A0U)
00302 #define I2S_FIFO_THRESHOLD_07DATA              (0x000000C0U)
00303 #define I2S_FIFO_THRESHOLD_08DATA              (0x000000E0U)
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup I2S_Master_Keep_IO_State Keep IO State
00309   * @{
00310   */
00311 #define I2S_MASTER_KEEP_IO_STATE_DISABLE       (0x00000000U)
00312 #define I2S_MASTER_KEEP_IO_STATE_ENABLE        SPI_CFG2_AFCNTR
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup I2S_SlaveExtendFREDetection Slave Extend FRE Detection
00318   * @{
00319   */
00320 #define I2S_SLAVE_EXTEND_FRE_DETECTION_DISABLE (0x00000000U)
00321 #define I2S_SLAVE_EXTEND_FRE_DETECTION_ENABLE  SPI_I2SCFGR_FIXCH
00322 /**
00323   * @}
00324   */
00325
00326 /** @defgroup I2S_Interrupt_definition I2S Interrupt definition
00327   * @{
00328   */
00329 #define I2S_IT_TXE                             SPI_IER_TXPIE
00330 #define I2S_IT_RXNE                            SPI_IER_RXPIE
00331 #define I2S_IT_ERR                            (SPI_IER_OVRIE | SPI_IER_UDRIE | SPI_IER_TIFREIE)
00332
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup I2S_Flag_definition I2S Flag definition
00338   * @{
00339   */
00340 #define I2S_FLAG_TXE                           SPI_SR_TXP     /* I2S status flag: Tx buffer empty flag           */
00341 #define I2S_FLAG_RXNE                          SPI_SR_RXP     /* I2S status flag: Rx buffer not empty flag       */
00342 #define I2S_FLAG_UDR                           SPI_SR_UDR     /* I2S Error flag: Underrun flag                   */
00343 #define I2S_FLAG_RXWNE                         SPI_SR_RXWNE   /* I2S RxFIFO Word Not Empty                       */
00344 #define I2S_FLAG_OVR                           SPI_SR_OVR     /* I2S Error flag: Overrun flag                    */
00345 #define I2S_FLAG_FRE                           SPI_SR_TIFRE   /* I2S Error flag: TI mode frame format error flag */
00346 /**
00347   * @}
00348   */
00349
00350 /**
00351   * @}
00352   */
00353 /* Exported macro ------------------------------------------------------------*/
00354 /** @defgroup I2S_Exported_Macros I2S Exported Macros
00355   * @{
00356   */
00357
00358 /** @brief  Reset I2S handle state
00359   * @param  __HANDLE__: specifies the I2S Handle.
00360   * @retval None
00361   */
00362 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
00363
00364 /** @brief  Enable the specified SPI peripheral (in I2S mode).
00365   * @param  __HANDLE__: specifies the I2S Handle.
00366   * @retval None
00367   */
00368 #define __HAL_I2S_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
00369
00370 /** @brief  Disable the specified SPI peripheral (in I2S mode).
00371   * @param  __HANDLE__: specifies the I2S Handle.
00372   * @retval None
00373   */
00374 #define __HAL_I2S_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
00375
00376 /** @brief  Enable the specified I2S interrupts.
00377   * @param  __HANDLE__: specifies the I2S Handle.
00378   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
00379   *         This parameter can be one of the following values:
00380   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00381   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00382   *            @arg I2S_IT_ERR: Error interrupt enable
00383   * @retval None
00384   */
00385 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__)    (SET_BIT((__HANDLE__)->Instance->IER,(__INTERRUPT__)))
00386
00387 /** @brief  Disable the specified I2S interrupts.
00388   * @param  __HANDLE__: specifies the I2S Handle.
00389   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
00390   *         This parameter can be one of the following values:
00391   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00392   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00393   *            @arg I2S_IT_ERR: Error interrupt enable
00394   * @retval None
00395   */
00396 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->IER,(__INTERRUPT__)))
00397
00398 /** @brief  Checks if the specified I2S interrupt source is enabled or disabled.
00399   * @param  __HANDLE__: specifies the I2S Handle.
00400   *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
00401   * @param  __INTERRUPT__: specifies the I2S interrupt source to check.
00402   *          This parameter can be one of the following values:
00403   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00404   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00405   *            @arg I2S_IT_ERR: Error interrupt enable
00406   * @retval The new state of __IT__ (TRUE or FALSE).
00407   */
00408 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00409
00410 /** @brief  Checks whether the specified I2S flag is set or not.
00411   * @param  __HANDLE__: specifies the I2S Handle.
00412   * @param  __FLAG__: specifies the flag to check.
00413   *         This parameter can be one of the following values:
00414   *            @arg I2S_FLAG_TXE   : Tx buffer empty flag
00415   *            @arg I2S_FLAG_RXNE  : Rx buffer not empty flag
00416   *            @arg I2S_FLAG_UDR   : Underrun flag
00417   *            @arg I2S_FLAG_OVR   : Overrun flag
00418   *            @arg I2S_FLAG_FRE   : TI mode frame format error flag
00419   * @retval The new state of __FLAG__ (TRUE or FALSE).
00420   */
00421 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00422
00423 /** @brief Clears the I2S UDR pending flag.
00424   * @param  __HANDLE__: specifies the I2S Handle.
00425   * @retval None
00426   */
00427 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)   SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
00428
00429 /** @brief Clears the I2S OVR pending flag.
00430   * @param  __HANDLE__: specifies the I2S Handle.
00431   * @retval None
00432   */
00433 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__)   SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
00434
00435 /** @brief  Clear the I2S FRE pending flag.
00436   * @param  __HANDLE__: specifies the I2S Handle.
00437   * @retval None
00438   */
00439 #define __HAL_I2S_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
00440
00441 /* Include I2S HAL Extended module */
00442 #include "stm32h7xx_hal_i2s_ex.h"
00443
00444 /* Exported functions --------------------------------------------------------*/
00445 /** @defgroup I2S_Exported_Functions I2S Exported Functions
00446   * @{
00447   */
00448
00449 /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
00450   * @{
00451   */
00452 /* Initialization/de-initialization functions  ********************************/
00453 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
00454 HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
00455 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
00456 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
00457 /**
00458   * @}
00459   */
00460
00461 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
00462   * @{
00463   */
00464 /* I/O operation functions  ***************************************************/
00465  /* Blocking mode: Polling */
00466 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
00467 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
00468
00469  /* Non-Blocking mode: Interrupt */
00470 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00471 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00472
00473 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
00474
00475 /* Non-Blocking mode: DMA */
00476 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00477 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00478
00479 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
00480 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
00481 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
00482
00483 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
00484 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
00485 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
00486 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
00487 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
00488 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
00489 /**
00490   * @}
00491   */
00492
00493 /** @addtogroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
00494   * @{
00495   */
00496 /* Peripheral Control and State functions  ************************************/
00497 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
00498 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
00499 /**
00500   * @}
00501   */
00502
00503 /* Private macros ------------------------------------------------------------*/
00504 /** @defgroup I2S_Private I2S Private
00505   * @{
00506   */
00507 #define IS_I2S_MODE(MODE)         (((MODE) == I2S_MODE_SLAVE_TX)  || \
00508                                    ((MODE) == I2S_MODE_SLAVE_RX)  || \
00509                                    ((MODE) == I2S_MODE_MASTER_TX) || \
00510                                    ((MODE) == I2S_MODE_MASTER_RX) || \
00511                                    ((MODE) == I2S_MODE_SLAVE_FD)  || \
00512                                    ((MODE) == I2S_MODE_MASTER_FD))
00513
00514 #define IS_I2S_FD_MODE(MODE)      (((MODE) == I2S_MODE_SLAVE_FD)  || \
00515                                    ((MODE) == I2S_MODE_MASTER_FD))
00516
00517 #define IS_I2S_MASTER(MODE)       (((MODE) == I2S_MODE_MASTER_TX)  || \
00518                                    ((MODE) == I2S_MODE_MASTER_RX) || \
00519                                    ((MODE) == I2S_MODE_MASTER_FD))
00520
00521 #define IS_I2S_TX_MODE(MODE)      (((MODE) == I2S_MODE_SLAVE_TX)  || \
00522                                    ((MODE) == I2S_MODE_MASTER_TX) || \
00523                                    ((MODE) == I2S_MODE_SLAVE_FD)  || \
00524                                    ((MODE) == I2S_MODE_MASTER_FD))
00525
00526 #define IS_I2S_RX_MODE(MODE)      (((MODE) == I2S_MODE_SLAVE_RX)  || \
00527                                    ((MODE) == I2S_MODE_MASTER_RX) || \
00528                                    ((MODE) == I2S_MODE_SLAVE_FD)  || \
00529                                    ((MODE) == I2S_MODE_MASTER_FD))
00530
00531 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS)   || \
00532                                    ((STANDARD) == I2S_STANDARD_MSB)       || \
00533                                    ((STANDARD) == I2S_STANDARD_LSB)       || \
00534                                    ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
00535                                    ((STANDARD) == I2S_STANDARD_PCM_LONG))
00536
00537 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B)          || \
00538                                     ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
00539                                     ((FORMAT) == I2S_DATAFORMAT_24B)          || \
00540                                     ((FORMAT) == I2S_DATAFORMAT_32B))
00541
00542 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
00543                                     ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
00544
00545 #define IS_I2S_AUDIO_FREQ(FREQ)   ((((FREQ) >= I2S_AUDIOFREQ_8K)    && \
00546                                     ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
00547                                     ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
00548
00549 #define IS_I2S_CPOL(CPOL)          (((CPOL) == I2S_CPOL_LOW) || \
00550                                     ((CPOL) == I2S_CPOL_HIGH))
00551
00552 #define IS_I2S_FIRST_BIT(FIRSTBIT) (((FIRSTBIT) == I2S_FIRSTBIT_MSB) || \
00553                                     ((FIRSTBIT) == I2S_FIRSTBIT_LSB))
00554
00555 #define IS_I2S_WS_INVERSION(WSINV) (((WSINV) == I2S_WS_INVERSION_DISABLE) || \
00556                                     ((WSINV) == I2S_WS_INVERSION_ENABLE))
00557
00558 #define IS_I2S_IO_SWAP(IOSWAP)     (((IOSWAP) == I2S_IO_SWAP_DISABLE) || \
00559                                     ((IOSWAP) == I2S_IO_SWAP_ENABLE))
00560
00561 #define IS_I2S_DATA_24BIT_ALIGNMENT(ALIGNMENT)  (((ALIGNMENT) == I2S_DATA_24BIT_ALIGNMENT_RIGHT) || \
00562                                                  ((ALIGNMENT) == I2S_DATA_24BIT_ALIGNMENT_LEFT))
00563
00564 #define IS_I2S_FIFO_THRESHOLD(FTHLV) (((FTHLV) == I2S_FIFO_THRESHOLD_01DATA) || \
00565                                       ((FTHLV) == I2S_FIFO_THRESHOLD_02DATA) || \
00566                                       ((FTHLV) == I2S_FIFO_THRESHOLD_03DATA) || \
00567                                       ((FTHLV) == I2S_FIFO_THRESHOLD_04DATA) || \
00568                                       ((FTHLV) == I2S_FIFO_THRESHOLD_05DATA) || \
00569                                       ((FTHLV) == I2S_FIFO_THRESHOLD_06DATA) || \
00570                                       ((FTHLV) == I2S_FIFO_THRESHOLD_07DATA) || \
00571                                       ((FTHLV) == I2S_FIFO_THRESHOLD_08DATA))
00572
00573 #define IS_I2S_MASTER_KEEP_IO_STATE(AFCNTR)      (((AFCNTR) == I2S_MASTER_KEEP_IO_STATE_DISABLE) || \
00574                                                   ((AFCNTR) == I2S_MASTER_KEEP_IO_STATE_ENABLE))
00575
00576 #define IS_I2S_SLAVE_EXTEND_FRE_DETECTION(FIXCH) (((FIXCH) == I2S_SLAVE_EXTEND_FRE_DETECTION_DISABLE) || \
00577                                                   ((FIXCH) == I2S_SLAVE_EXTEND_FRE_DETECTION_ENABLE))
00578
00579 /**
00580   * @}
00581   */
00582
00583 /* Define the private group ***************************************************/
00584 /******************************************************************************/
00585 /** @defgroup I2S_Private I2S Private
00586   * @{
00587   */
00588 /**
00589   * @}
00590   */
00591 /******************************************************************************/
00592 /**
00593   * @}
00594   */
00595
00596 /**
00597   * @}
00598   */
00599
00600 /**
00601   * @}
00602   */
00603
00604 /**
00605   * @}
00606   */
00607
00608
00609 #ifdef __cplusplus
00610 }
00611 #endif
00612
00613
00614
00615 #endif /* __STM32H7xx_HAL_I2S_H */
00616
00617 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_i2s_ex.c Source File

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stm32h7xx_hal_i2s_ex.c
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00001   /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_i2s_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   I2S HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of I2S extension peripheral:
00010   *           + IO operation functions
00011   *           + Peripheral Control functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                   ##### I2S Extension features #####
00016   ==============================================================================
00017   [..]
00018      (+) In I2S full duplex mode, SPI2S peripheral is able to manage sending and receiving
00019          data simultaneously using two data lines.
00020   @endverbatim
00021
00022   @verbatim
00023  ===============================================================================
00024                   ##### How to use this driver #####
00025  ===============================================================================
00026  [..]
00027    Three operation modes are available within this driver :
00028
00029    *** Polling mode IO operation ***
00030    =================================
00031    [..]
00032      (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2SEx_TransmitReceive()
00033
00034    *** Interrupt mode IO operation ***
00035    ===================================
00036    [..]
00037      (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2SEx_TransmitReceive_IT()
00038      (+) At full duplex transfer end of half transfer HAL_I2SEx_TxRxHalfCpltCallback is executed and user can
00039          add his own code by customization of function pointer HAL_I2SEx_TxRxHalfCpltCallback
00040      (+) At full duplex transfer end of transfer HAL_I2SEx_TxRxCpltCallback is executed and user can
00041          add his own code by customization of function pointer HAL_I2SEx_TxRxCpltCallback
00042      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00043          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00044
00045    *** DMA mode IO operation ***
00046    ==============================
00047    [..]
00048      (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2SEx_TransmitReceive_DMA()
00049      (+) At the end of half transfer HAL_I2SEx_TxRxHalfCpltCallback is executed and user can
00050          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
00051      (+) At the end of transfer HAL_I2S_TxRxCpltCallback is executed and user can
00052          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
00053      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00054          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00055      (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
00056      (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
00057      (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
00058
00059   @endverbatim
00060   ******************************************************************************
00061   * @attention
00062   *
00063   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00064   *
00065   * Redistribution and use in source and binary forms, with or without modification,
00066   * are permitted provided that the following conditions are met:
00067   *   1. Redistributions of source code must retain the above copyright notice,
00068   *      this list of conditions and the following disclaimer.
00069   *   2. Redistributions in binary form must reproduce the above copyright notice,
00070   *      this list of conditions and the following disclaimer in the documentation
00071   *      and/or other materials provided with the distribution.
00072   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00073   *      may be used to endorse or promote products derived from this software
00074   *      without specific prior written permission.
00075   *
00076   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00077   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00078   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00079   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00080   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00081   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00082   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00083   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00084   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00085   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00086   *
00087   ******************************************************************************
00088   */
00089
00090 /* Includes ------------------------------------------------------------------*/
00091 #include "stm32h7xx_hal.h"
00092
00093 /** @addtogroup STM32H7xx_HAL_Driver
00094   * @{
00095   */
00096
00097 #ifdef HAL_I2S_MODULE_ENABLED
00098 /** @defgroup I2SEx I2SEx
00099   * @brief I2S Extended HAL module driver
00100   * @{
00101   */
00102
00103 /* Private typedef -----------------------------------------------------------*/
00104 /** @defgroup I2SEx_Private_Typedef I2S Extended Private Typedef
00105   * @{
00106   */
00107 typedef enum
00108 {
00109   I2S_USE_I2S      = 0x00U,   /*!< I2Sx should be used      */
00110   I2S_USE_I2SEXT   = 0x01U,   /*!< I2Sx_ext should be used  */
00111 }I2S_UseTypeDef;
00112 /**
00113   * @}
00114   */
00115 /* Private define ------------------------------------------------------------*/
00116 /* Private macro -------------------------------------------------------------*/
00117 /* Private variables ---------------------------------------------------------*/
00118 /* Private function prototypes -----------------------------------------------*/
00119 /** @defgroup I2SEx_Private_Functions I2S Extended Private Functions
00120   * @{
00121   */
00122 static void              I2SEx_DMATxRxCplt(DMA_HandleTypeDef *hdma);
00123 static void              I2SEx_DMATxRxHalfCplt(DMA_HandleTypeDef *hdma);
00124 static void              I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma);
00125
00126 static void              I2SEx_2linesTxISR_16BIT(struct __I2S_HandleTypeDef *hi2s);
00127 static void              I2SEx_2linesTxISR_32BIT(struct __I2S_HandleTypeDef *hi2s);
00128 static void              I2SEx_2linesRxISR_16BIT(struct __I2S_HandleTypeDef *hi2s);
00129 static void              I2SEx_2linesRxISR_32BIT(struct __I2S_HandleTypeDef *hi2s);
00130 static void              I2SEx_CloseRxTx_ISR(I2S_HandleTypeDef *hi2s);
00131
00132 static HAL_StatusTypeDef I2SEx_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
00133
00134 /**
00135   * @}
00136   */
00137
00138 /* Private functions ---------------------------------------------------------*/
00139 /* Exported functions --------------------------------------------------------*/
00140
00141 /** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions
00142   * @{
00143   */
00144
00145 /** @defgroup I2SEx_Exported_Functions_Group1 I2S Extended IO operation functions
00146   *  @brief   I2SEx IO operation functions
00147   *
00148 @verbatim
00149  ===============================================================================
00150                        ##### IO operation functions#####
00151  ===============================================================================
00152     [..]
00153     This subsection provides a set of functions allowing to manage the I2S data
00154     transfers.
00155
00156     (#) There are two modes of transfer:
00157        (++) Blocking mode : The communication is performed in the polling mode.
00158             The status of all data processing is returned by the same function
00159             after finishing transfer.
00160        (++) No-Blocking mode : The communication is performed using Interrupts
00161             or DMA. These functions return the status of the transfer startup.
00162             The end of the data processing will be indicated through the
00163             dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
00164             using DMA mode.
00165
00166     (#) Blocking mode functions are :
00167         (++) HAL_I2SEx_TransmitReceive()
00168
00169     (#) No-Blocking mode functions with Interrupt are :
00170         (++) HAL_I2SEx_TransmitReceive_IT()
00171
00172     (#) No-Blocking mode functions with DMA are :
00173         (++) HAL_I2SEx_TransmitReceive_DMA()
00174
00175     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00176         (++) HAL_I2SEx_TxRxCpltCallback()
00177         (++) HAL_I2SEx_TxRxErrorCallback()
00178
00179 @endverbatim
00180   * @{
00181   */
00182
00183 /**
00184   * @brief  Transmit and Receive an amount of data in blocking mode
00185   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00186   *         the configuration information for I2S module
00187   * @param  pTxData: a 16-bit pointer to the Transmit data buffer
00188   * @param  pRxData: a 16-bit pointer to the Receive data buffer
00189   * @param  Size: number of frames to be sent
00190   * @param  Timeout: Timeout duration
00191   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00192   *         between Master and Slave(example: audio streaming).
00193   * @note   This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
00194   * @retval HAL status
00195   */
00196 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
00197 {
00198   uint32_t tickstart = 0U;
00199   uint32_t isDataFormat16B = 2U;
00200
00201   /* Check Mode parameter */
00202   assert_param(IS_I2S_FD_MODE(hi2s->Init.Mode));
00203
00204   if((pTxData == NULL ) || (Size == 0U))
00205   {
00206     return  HAL_ERROR;
00207   }
00208
00209   /* Process Locked */
00210   __HAL_LOCK(hi2s);
00211
00212   /* Init tickstart for timeout management*/
00213   tickstart = HAL_GetTick();
00214
00215   if(hi2s->State == HAL_I2S_STATE_READY)
00216   {
00217     /* Check the Data Format value */
00218     if (((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B) ||
00219         ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
00220     {
00221       isDataFormat16B = 0U;
00222     }
00223     else
00224     {
00225       isDataFormat16B = 1U;
00226     }
00227
00228     if(!isDataFormat16B)
00229     {
00230       hi2s->TxXferSize  = (Size << 1U);
00231       hi2s->TxXferCount = (Size << 1U);
00232
00233       hi2s->RxXferSize  = (Size << 1U);
00234       hi2s->RxXferCount = (Size << 1U);
00235     }
00236     else
00237     {
00238       hi2s->TxXferSize  = Size;
00239       hi2s->TxXferCount = Size;
00240
00241       hi2s->RxXferSize  = Size;
00242       hi2s->RxXferCount = Size;
00243     }
00244
00245     /* Set state and reset error code */
00246     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00247     hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
00248     hi2s->pTxBuffPtr = pTxData;
00249     hi2s->pRxBuffPtr = pRxData;
00250
00251     /* Check if the SPI2S is already enabled */
00252     if((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00253     {
00254       /* Enable I2S peripheral */
00255       __HAL_I2S_ENABLE(hi2s);
00256     }
00257
00258     if(IS_I2S_MASTER(hi2s->Init.Mode))
00259     {
00260       hi2s->Instance->CR1 |= SPI_CR1_CSTART;
00261     }
00262
00263     /* Transmit and Receive data in 32 Bit mode */
00264     if (!isDataFormat16B)
00265     {
00266       while ((hi2s->TxXferCount > 0U) || (hi2s->RxXferCount > 0U))
00267       {
00268         /* Check TXE flag */
00269         if ((hi2s->TxXferCount > 0U) && (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE)))
00270         {
00271           *((__IO uint32_t *)&hi2s->Instance->TXDR) = *((uint32_t *)hi2s->pTxBuffPtr);
00272           hi2s->pTxBuffPtr += sizeof(uint32_t);
00273           hi2s->TxXferCount --;
00274         }
00275
00276         /* Check RXNE flag */
00277         if ((hi2s->RxXferCount > 0U) && (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE)))
00278         {
00279           *((uint32_t *)hi2s->pRxBuffPtr) = *((__IO uint32_t *)&hi2s->Instance->RXDR);
00280           hi2s->pRxBuffPtr += sizeof(uint32_t);
00281           hi2s->RxXferCount --;
00282         }
00283
00284         /* Timeout Management */
00285         if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout))
00286         {
00287           /* Set the error code and execute error callback*/
00288           SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00289           HAL_I2S_ErrorCallback(hi2s);
00290
00291           /* Set the I2S State ready */
00292           hi2s->State = HAL_I2S_STATE_READY;
00293
00294           /* Process Unlocked */
00295           __HAL_UNLOCK(hi2s);
00296           return HAL_ERROR;
00297         }
00298       }
00299     }
00300     /* Transmit and Receive data in 16 Bit mode */
00301     else
00302     {
00303       while ((hi2s->TxXferCount > 0U) || (hi2s->RxXferCount > 0U))
00304       {
00305         /* Check TXE flag */
00306         if ((hi2s->TxXferCount > 0U) && (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE)))
00307         {
00308           if ( (hi2s->TxXferCount > 1U) && (hi2s->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
00309           {
00310             *((__IO uint32_t *)&hi2s->Instance->TXDR) = *((uint32_t *)hi2s->pTxBuffPtr);
00311             hi2s->pTxBuffPtr += sizeof(uint32_t);
00312             hi2s->TxXferCount-=2;
00313           }
00314           else
00315           {
00316             *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr);
00317             hi2s->pTxBuffPtr += sizeof(uint16_t);
00318             hi2s->TxXferCount--;
00319           }
00320         }
00321
00322         /* Check RXNE flag */
00323         if ((hi2s->RxXferCount > 0U) && (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE)))
00324         {
00325           if (hi2s->Instance->SR & I2S_FLAG_RXWNE)
00326           {
00327             *((uint32_t *)hi2s->pRxBuffPtr) = *((__IO uint32_t *)&hi2s->Instance->RXDR);
00328             hi2s->pRxBuffPtr += sizeof(uint32_t);
00329             hi2s->RxXferCount-=2;
00330           }
00331           else
00332           {
00333             *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
00334             hi2s->pRxBuffPtr += sizeof(uint16_t);
00335             hi2s->RxXferCount--;
00336           }
00337         }
00338
00339         /* Timeout Management */
00340         if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout))
00341         {
00342           /* Set the error code and execute error callback*/
00343           SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00344           HAL_I2S_ErrorCallback(hi2s);
00345
00346           /* Set the I2S State ready */
00347           hi2s->State = HAL_I2S_STATE_READY;
00348
00349           /* Process Unlocked */
00350           __HAL_UNLOCK(hi2s);
00351           return HAL_ERROR;
00352         }
00353       }
00354     }
00355
00356     /* Wait until TXE flag is set, to confirm the end of the transaction */
00357     if (I2SEx_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
00358     {
00359       return HAL_TIMEOUT;
00360     }
00361
00362     hi2s->State = HAL_I2S_STATE_READY;
00363
00364     /* Process Unlocked */
00365     __HAL_UNLOCK(hi2s);
00366
00367     return HAL_OK;
00368   }
00369   else
00370   {
00371     /* Process Unlocked */
00372     __HAL_UNLOCK(hi2s);
00373     return HAL_BUSY;
00374   }
00375 }
00376
00377 /**
00378   * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt
00379   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00380   *         the configuration information for I2S module
00381   * @param pTxData: a 16-bit pointer to the Transmit data buffer.
00382   * @param pRxData: a 16-bit pointer to the Receive data buffer.
00383   * @param Size: number of data sample to be sent:
00384   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00385   *       configuration phase, the Size parameter means the number of 16-bit data length
00386   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00387   *       the Size parameter means the number of 16-bit data length.
00388   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00389   *       between Master and Slave(example: audio streaming).
00390   * @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
00391   * @retval HAL status
00392   */
00393 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
00394 {
00395   /* Check Mode parameter */
00396   assert_param(IS_I2S_FD_MODE(hi2s->Init.Mode));
00397
00398   /* Process Locked */
00399   __HAL_LOCK(hi2s);
00400
00401   if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
00402   {
00403     __HAL_UNLOCK(hi2s);
00404     return  HAL_ERROR;
00405   }
00406
00407   if (hi2s->State == HAL_I2S_STATE_READY)
00408   {
00409     __HAL_UNLOCK(hi2s);
00410     return  HAL_BUSY;
00411   }
00412
00413   /* Set the transaction information */
00414   hi2s->State       = HAL_I2S_STATE_BUSY_TX;
00415   hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
00416   hi2s->pTxBuffPtr  = pTxData;
00417   hi2s->TxXferSize  = Size;
00418   hi2s->TxXferCount = Size;
00419
00420   /* Init field not used in handle to zero */
00421   hi2s->pRxBuffPtr  = pRxData;
00422   hi2s->RxXferSize  = Size;
00423   hi2s->RxXferCount = Size;
00424
00425   /* Set the function for IT treatment */
00426   if (hi2s->Init.DataFormat > I2S_DATAFORMAT_16B)
00427   {
00428     hi2s->RxISR = I2SEx_2linesRxISR_32BIT;
00429     hi2s->TxISR = I2SEx_2linesTxISR_32BIT;
00430   }
00431   else
00432   {
00433     hi2s->RxISR = I2SEx_2linesRxISR_16BIT;
00434     hi2s->TxISR = I2SEx_2linesTxISR_16BIT;
00435   }
00436
00437   /* Check if the I2S is already enabled */
00438   if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00439   {
00440     /* Enable SPI peripheral */
00441     __HAL_I2S_ENABLE(hi2s);
00442   }
00443
00444   if (IS_I2S_MASTER(hi2s->Init.Mode))
00445   {
00446     /* Master transfer start */
00447     SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
00448   }
00449
00450   /* Enable TXE and ERR interrupt */
00451   __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_RXNE | I2S_IT_ERR));
00452
00453   /* Process Unlocked */
00454   __HAL_UNLOCK(hi2s);
00455
00456   return HAL_OK;
00457 }
00458
00459 /**
00460   * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA
00461   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00462   *         the configuration information for I2S module
00463   * @param  pTxData: a 16-bit pointer to the Transmit data buffer.
00464   * @param  pRxData: a 16-bit pointer to the Receive data buffer.
00465   * @param  Size: number of frames to be sent.
00466   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00467   *         between Master and Slave(example: audio streaming).
00468   * @retval HAL status
00469   */
00470 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
00471 {
00472   /* Check Mode parameter */
00473   assert_param(IS_I2S_FD_MODE(hi2s->Init.Mode));
00474
00475   if((pTxData == NULL) || (Size == 0U))
00476   {
00477     return  HAL_ERROR;
00478   }
00479
00480   /* Process Locked */
00481   __HAL_LOCK(hi2s);
00482
00483   if(hi2s->State == HAL_I2S_STATE_READY)
00484   {
00485     hi2s->pTxBuffPtr = pTxData;
00486     hi2s->pRxBuffPtr = pRxData;
00487     hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
00488     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00489
00490     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
00491       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
00492     {
00493       hi2s->TxXferSize  = (Size << 1U);
00494       hi2s->TxXferCount = (Size << 1U);
00495
00496       hi2s->RxXferSize  = (Size << 1U);
00497       hi2s->RxXferCount = (Size << 1U);
00498     }
00499     else
00500     {
00501       hi2s->TxXferSize  = Size;
00502       hi2s->TxXferCount = Size;
00503
00504       hi2s->RxXferSize  = Size;
00505       hi2s->RxXferCount = Size;
00506     }
00507
00508     /* Set the I2S Rx DMA Half transfert complete callback */
00509     hi2s->hdmarx->XferHalfCpltCallback = I2SEx_DMATxRxHalfCplt;
00510
00511     /* Set the I2S Rx DMA transfert complete callback */
00512     hi2s->hdmarx->XferCpltCallback = I2SEx_DMATxRxCplt;
00513
00514     /* Set the DMA error callback */
00515     hi2s->hdmarx->XferErrorCallback = I2SEx_TxRxDMAError;
00516
00517     /* Enable the Rx DMA Channel */
00518     HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize);
00519
00520     /* Check if the I2S Rx requests are already enabled */
00521     if(HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN))
00522     {
00523       /* Check if the SPI2S is disabled to edit CFG1 register */
00524       if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00525       {
00526         /* Enable Rx DMA Request */
00527         SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
00528       }
00529       else
00530       {
00531         /* Disable SPI peripheral */
00532         __HAL_I2S_DISABLE(hi2s);
00533
00534         /* Enable Rx DMA Request */
00535         SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
00536
00537         /* Enable SPI peripheral */
00538         __HAL_I2S_ENABLE(hi2s);
00539       }
00540     }
00541
00542     /* Set the I2S Tx DMA transfer callbacks as NULL because the communication closing
00543     is performed in DMA reception callbacks */
00544     hi2s->hdmatx->XferHalfCpltCallback = NULL;
00545     hi2s->hdmatx->XferCpltCallback     = NULL;
00546     hi2s->hdmatx->XferErrorCallback    = NULL;
00547
00548     /* Enable the Tx DMA Channel */
00549     HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR, hi2s->TxXferSize);
00550
00551     /* Check if the I2S Tx requests are already enabled */
00552     if(HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN))
00553     {
00554       /* Check if the SPI2S is disabled to edit CFG1 register */
00555       if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00556       {
00557         /* Enable Tx DMA Request */
00558         SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
00559       }
00560       else
00561       {
00562         /* Disable SPI peripheral */
00563         __HAL_I2S_DISABLE(hi2s);
00564
00565         /* Enable Tx/Rx DMA Request */
00566         SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
00567
00568         /* Enable SPI peripheral */
00569         __HAL_I2S_ENABLE(hi2s);
00570       }
00571     }
00572
00573     /* Process Unlocked */
00574     __HAL_UNLOCK(hi2s);
00575
00576     return HAL_OK;
00577   }
00578   else
00579   {
00580     /* Process Unlocked */
00581     __HAL_UNLOCK(hi2s);
00582     return HAL_BUSY;
00583   }
00584 }
00585
00586 /**
00587   * @brief  Tx/Rx Transfer half completed callbacks
00588   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00589   *         the configuration information for I2S module
00590   * @retval None
00591   */
00592 __weak void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
00593 {
00594   /* Prevent unused argument(s) compilation warning */
00595   UNUSED(hi2s);
00596
00597   /* NOTE : This function Should not be modified, when the callback is needed,
00598             the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
00599    */
00600 }
00601
00602 /**
00603   * @brief  Tx/Rx Transfer completed callbacks
00604   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00605   *         the configuration information for I2S module
00606   * @retval None
00607   */
00608 __weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
00609 {
00610   /* Prevent unused argument(s) compilation warning */
00611   UNUSED(hi2s);
00612
00613   /* NOTE : This function Should not be modified, when the callback is needed,
00614             the HAL_I2S_RxCpltCallback could be implemented in the user file
00615    */
00616 }
00617
00618 /**
00619   * @}
00620   */
00621
00622 /**
00623   * @}
00624   */
00625
00626 /** @addtogroup I2SEx_Private_Functions I2S Extended Private Functions
00627   * @{
00628   */
00629
00630 /**
00631   * @brief  DMA I2S transmit receive process complete callback
00632   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00633   *         the configuration information for the specified DMA module.
00634   * @retval None
00635   */
00636 static void I2SEx_DMATxRxCplt(DMA_HandleTypeDef *hdma)
00637 {
00638   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
00639
00640   if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U)
00641   {
00642     /* Check if the SPI2S is disabled to edit CFG1 register */
00643     if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00644     {
00645       /* Disable Tx/Rx DMA Request */
00646       CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN);
00647     }
00648     else
00649     {
00650       /* Disable SPI peripheral */
00651       __HAL_I2S_DISABLE(hi2s);
00652
00653       /* Disable Rx DMA Request */
00654       CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN);
00655
00656       /* Enable SPI peripheral */
00657       __HAL_I2S_ENABLE(hi2s);
00658     }
00659
00660     hi2s->TxXferCount = 0U;
00661     hi2s->RxXferCount = 0U;
00662     hi2s->State = HAL_I2S_STATE_READY;
00663
00664     if (hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
00665     {
00666       HAL_I2S_ErrorCallback(hi2s);
00667       return;
00668     }
00669   }
00670   HAL_I2SEx_TxRxCpltCallback(hi2s);
00671 }
00672
00673 /**
00674   * @brief  DMA I2S transmit receive process half complete callback
00675   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00676   *         the configuration information for the specified DMA module.
00677   * @retval None
00678   */
00679 static void I2SEx_DMATxRxHalfCplt(DMA_HandleTypeDef *hdma)
00680 {
00681   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
00682
00683   HAL_I2SEx_TxRxHalfCpltCallback(hi2s);
00684 }
00685
00686 /**
00687   * @brief  DMA I2S communication error callback
00688   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00689   *               the configuration information for the specified DMA module.
00690   * @retval None
00691   */
00692 static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma)
00693 {
00694   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
00695
00696   /* Check if the SPI2S is disabled to edit CFG1 register */
00697   if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00698   {
00699     /* Disable Rx and Tx DMA Request */
00700     CLEAR_BIT(hi2s->Instance->CFG1, (SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN));
00701   }
00702   else
00703   {
00704     /* Disable SPI peripheral */
00705     __HAL_I2S_DISABLE(hi2s);
00706
00707     /* Disable Rx and Tx DMA Request */
00708     CLEAR_BIT(hi2s->Instance->CFG1, (SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN));
00709
00710     /* Enable SPI peripheral */
00711     __HAL_I2S_ENABLE(hi2s);
00712   }
00713
00714   hi2s->TxXferCount = 0U;
00715   hi2s->RxXferCount = 0U;
00716
00717   hi2s->State= HAL_I2S_STATE_READY;
00718
00719   /* Set the error code and execute error callback*/
00720   SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
00721   HAL_I2S_ErrorCallback(hi2s);
00722 }
00723
00724 /**
00725   * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
00726   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00727   *         the configuration information for I2S module.
00728   * @retval None
00729   */
00730 static void I2SEx_2linesRxISR_16BIT(struct __I2S_HandleTypeDef *hi2s)
00731 {
00732   /* Receive data in 16 Bit mode */
00733   *((uint16_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
00734   hi2s->pRxBuffPtr += sizeof(uint16_t);
00735   hi2s->RxXferCount--;
00736
00737   if (hi2s->RxXferCount == 0U)
00738   {
00739     /* Disable RXNE interrupt */
00740     __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE);
00741
00742     if (hi2s->TxXferCount == 0U)
00743     {
00744       I2SEx_CloseRxTx_ISR(hi2s);
00745     }
00746   }
00747 }
00748
00749 /**
00750   * @brief  Rx 32-bit handler for Transmit and Receive in Interrupt mode.
00751   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00752   *         the configuration information for I2S module.
00753   * @retval None
00754   */
00755 static void I2SEx_2linesRxISR_32BIT(struct __I2S_HandleTypeDef *hi2s)
00756 {
00757   /* Receive data in 32 Bit mode */
00758   *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
00759   hi2s->pRxBuffPtr += sizeof(uint32_t);
00760   hi2s->RxXferCount--;
00761
00762   if (hi2s->RxXferCount == 0U)
00763   {
00764     /* Disable RXNE interrupt */
00765     __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE);
00766
00767     if (hi2s->TxXferCount == 0U)
00768     {
00769       I2SEx_CloseRxTx_ISR(hi2s);
00770     }
00771   }
00772 }
00773
00774 /**
00775   * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
00776   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00777   *         the configuration information for I2S module.
00778   * @retval None
00779   */
00780 static void I2SEx_2linesTxISR_16BIT(struct __I2S_HandleTypeDef *hi2s)
00781 {
00782   /* Transmit data in 16 Bit mode */
00783   *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr);
00784   hi2s->pTxBuffPtr += sizeof(uint16_t);
00785   hi2s->TxXferCount--;
00786
00787   /* Enable CRC Transmission */
00788   if (hi2s->TxXferCount == 0U)
00789   {
00790     /* Disable TXE interrupt */
00791     __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_TXE);
00792
00793     if (hi2s->RxXferCount == 0U)
00794     {
00795       I2SEx_CloseRxTx_ISR(hi2s);
00796     }
00797   }
00798 }
00799
00800 /**
00801   * @brief  Tx 32-bit handler for Transmit and Receive in Interrupt mode.
00802   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00803   *         the configuration information for I2S module.
00804   * @retval None
00805   */
00806 static void I2SEx_2linesTxISR_32BIT(struct __I2S_HandleTypeDef *hi2s)
00807 {
00808   /* Transmit data in 32 Bit mode */
00809   *((__IO uint32_t *)&hi2s->Instance->TXDR) = *((uint32_t *)hi2s->pTxBuffPtr);
00810   hi2s->pTxBuffPtr += sizeof(uint32_t);
00811   hi2s->TxXferCount--;
00812
00813   /* Enable CRC Transmission */
00814   if (hi2s->TxXferCount == 0U)
00815   {
00816     /* Disable TXE interrupt */
00817     __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_TXE);
00818
00819     if (hi2s->RxXferCount == 0U)
00820     {
00821       I2SEx_CloseRxTx_ISR(hi2s);
00822     }
00823   }
00824 }
00825
00826 /**
00827   * @brief  Handle the end of the RXTX transaction.
00828   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00829   *         the configuration information for I2S module.
00830   * @retval None
00831   */
00832 static void I2SEx_CloseRxTx_ISR(I2S_HandleTypeDef *hi2s)
00833 {
00834   /* Disable ERR interrupt */
00835   __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_TXE | I2S_IT_ERR));
00836
00837   if (hi2s->ErrorCode == HAL_I2S_ERROR_NONE)
00838   {
00839     if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
00840     {
00841       hi2s->State = HAL_I2S_STATE_READY;
00842       HAL_I2S_RxCpltCallback(hi2s);
00843     }
00844     else
00845     {
00846       hi2s->State = HAL_I2S_STATE_READY;
00847       HAL_I2SEx_TxRxCpltCallback(hi2s);
00848     }
00849   }
00850   else
00851   {
00852     hi2s->State = HAL_I2S_STATE_READY;
00853     HAL_I2S_ErrorCallback(hi2s);
00854   }
00855 }
00856
00857 /**
00858   * @brief This function handles I2S Communication Timeout.
00859   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00860   *         the configuration information for I2S module
00861   * @param Flag: Flag checked
00862   * @param State: Value of the flag expected
00863   * @param Timeout: Duration of the timeout
00864   * @retval HAL status
00865   */
00866 static HAL_StatusTypeDef I2SEx_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
00867 {
00868   uint32_t tickstart = 0U;
00869
00870   /* Get tick */
00871   tickstart = HAL_GetTick();
00872
00873   /* Wait until flag is set */
00874   if(State == RESET)
00875   {
00876     while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
00877     {
00878       if(Timeout != HAL_MAX_DELAY)
00879       {
00880         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00881         {
00882           /* Set the I2S State ready */
00883           hi2s->State= HAL_I2S_STATE_READY;
00884
00885           /* Process Unlocked */
00886           __HAL_UNLOCK(hi2s);
00887
00888           return HAL_TIMEOUT;
00889         }
00890       }
00891     }
00892   }
00893   else
00894   {
00895     while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
00896     {
00897       if(Timeout != HAL_MAX_DELAY)
00898       {
00899         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00900         {
00901           /* Set the I2S State ready */
00902           hi2s->State= HAL_I2S_STATE_READY;
00903
00904           /* Process Unlocked */
00905           __HAL_UNLOCK(hi2s);
00906
00907           return HAL_TIMEOUT;
00908         }
00909       }
00910     }
00911   }
00912   return HAL_OK;
00913 }
00914
00915 /**
00916   * @}
00917   */
00918 #endif /* HAL_I2S_MODULE_ENABLED */
00919
00920 /**
00921   * @}
00922   */
00923
00924 /**
00925   * @}
00926   */
00927
00928
00929 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_i2s_ex.h Source File

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  • STM32H7xx_HAL_Driver
  • Inc
stm32h7xx_hal_i2s_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_i2s_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of I2S HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_I2S_EX_H
00040 #define __STM32H7xx_HAL_I2S_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052 /** @addtogroup I2SEx I2SEx
00053   * @{
00054   */
00055
00056 /* Exported types ------------------------------------------------------------*/
00057 /* Exported constants --------------------------------------------------------*/
00058 /* Exported macros -----------------------------------------------------------*/
00059 /* Exported functions --------------------------------------------------------*/
00060 /** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions
00061   * @{
00062   */
00063
00064 /** @addtogroup I2SEx_Exported_Functions_Group1 I2S Extended IO operation functions
00065   * @{
00066   */
00067
00068 /* Extended features functions *************************************************/
00069 /* Blocking mode: Polling */
00070 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout);
00071 /* Non-Blocking mode: Interrupt */
00072 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
00073 /* Non-Blocking mode: DMA */
00074 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
00075 /* I2S Callbacks used in non blocking modes (Interrupt and DMA) */
00076 void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
00077 void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
00078 /**
00079   * @}
00080   */
00081
00082 /**
00083   * @}
00084   */
00085 /* Private types -------------------------------------------------------------*/
00086 /* Private variables ---------------------------------------------------------*/
00087 /* Private constants ---------------------------------------------------------*/
00088 /* Private macros ------------------------------------------------------------*/
00089
00090 /**
00091   * @}
00092   */
00093
00094 /* Private functions ---------------------------------------------------------*/
00095
00096 /**
00097   * @}
00098   */
00099
00100 #ifdef __cplusplus
00101 }
00102 #endif
00103
00104
00105 #endif /* __STM32H7xx_HAL_I2S_EX_H */
00106
00107 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_irda.c Source File

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stm32h7xx_hal_irda.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_irda.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   IRDA HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the IrDA (Infrared Data Association) Peripheral
00010   *          (IRDA)
00011   *           + Initialization and de-initialization functions
00012   *           + IO operation functions
00013   *           + Peripheral State and Errors functions
00014   *           + Peripheral Control functions
00015   *
00016   @verbatim
00017   ==============================================================================
00018                         ##### How to use this driver #####
00019   ==============================================================================
00020   [..]
00021     The IRDA HAL driver can be used as follows:
00022
00023     (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
00024     (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
00025         in setting the associated USART or UART in IRDA mode:
00026         (++) Enable the USARTx/UARTx interface clock.
00027         (++) USARTx/UARTx pins configuration:
00028             (+++) Enable the clock for the USARTx/UARTx GPIOs.
00029             (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
00030         (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
00031              and HAL_IRDA_Receive_IT() APIs):
00032             (+++) Configure the USARTx/UARTx interrupt priority.
00033             (+++) Enable the NVIC USARTx/UARTx IRQ handle.
00034             (+++) The specific IRDA interrupts (Transmission complete interrupt,
00035                   RXNE interrupt and Error Interrupts) will be managed using the macros
00036                   __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
00037
00038         (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
00039              and HAL_IRDA_Receive_DMA() APIs):
00040             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00041             (+++) Enable the DMAx interface clock.
00042             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00043             (+++) Configure the DMA Tx/Rx channel.
00044             (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
00045             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00046
00047     (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
00048         the normal or low power mode and the clock prescaler in the hirda handle Init structure.
00049
00050     (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
00051         (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00052              by calling the customized HAL_IRDA_MspInit() API.
00053
00054          -@@- The specific IRDA interrupts (Transmission complete interrupt,
00055              RXNE interrupt and Error Interrupts) will be managed using the macros
00056              __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
00057
00058     (#) Three operation modes are available within this driver :
00059
00060      *** Polling mode IO operation ***
00061      =================================
00062      [..]
00063        (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
00064        (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
00065
00066      *** Interrupt mode IO operation ***
00067      ===================================
00068      [..]
00069        (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
00070        (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
00071             add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
00072        (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
00073        (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
00074             add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
00075        (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
00076             add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
00077
00078      *** DMA mode IO operation ***
00079      ==============================
00080      [..]
00081        (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
00082        (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
00083             add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
00084        (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
00085             add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
00086        (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
00087        (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
00088             add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
00089        (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
00090             add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
00091        (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
00092             add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
00093
00094      *** IRDA HAL driver macros list ***
00095      ====================================
00096      [..]
00097        Below the list of most used macros in IRDA HAL driver.
00098
00099        (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
00100        (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
00101        (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
00102        (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
00103        (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
00104        (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
00105        (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
00106
00107      [..]
00108        (@) You can refer to the IRDA HAL driver header file for more useful macros
00109
00110   @endverbatim
00111   ******************************************************************************
00112   * @attention
00113   *
00114   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00115   *
00116   * Redistribution and use in source and binary forms, with or without modification,
00117   * are permitted provided that the following conditions are met:
00118   *   1. Redistributions of source code must retain the above copyright notice,
00119   *      this list of conditions and the following disclaimer.
00120   *   2. Redistributions in binary form must reproduce the above copyright notice,
00121   *      this list of conditions and the following disclaimer in the documentation
00122   *      and/or other materials provided with the distribution.
00123   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00124   *      may be used to endorse or promote products derived from this software
00125   *      without specific prior written permission.
00126   *
00127   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00128   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00129   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00130   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00131   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00132   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00133   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00134   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00135   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00136   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00137   *
00138   ******************************************************************************
00139   */
00140
00141 /* Includes ------------------------------------------------------------------*/
00142 #include "stm32h7xx_hal.h"
00143
00144 /** @addtogroup STM32H7xx_HAL_Driver
00145   * @{
00146   */
00147
00148 /** @defgroup IRDA IRDA
00149   * @brief HAL IRDA module driver
00150   * @{
00151   */
00152
00153 #ifdef HAL_IRDA_MODULE_ENABLED
00154
00155 /* Private typedef -----------------------------------------------------------*/
00156 /* Private define ------------------------------------------------------------*/
00157 /** @defgroup IRDA_Private_Constants IRDA Private Constants
00158   * @{
00159   */
00160 #define IRDA_TEACK_REACK_TIMEOUT            1000                                   /*!< IRDA TX or RX enable acknowledge time-out value  */
00161 #define IRDA_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
00162                                    | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))  /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
00163 /**
00164   * @}
00165   */
00166
00167 /* Private macros ------------------------------------------------------------*/
00168 /* Private variables ---------------------------------------------------------*/
00169 /* Private function prototypes -----------------------------------------------*/
00170 /** @addtogroup IRDA_Private_Functions
00171   * @{
00172   */
00173 static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
00174 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
00175 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
00176 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
00177 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
00178 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00179 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
00180 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00181 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
00182 static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
00183 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00184 static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00185 static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00186 static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00187 static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00188 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
00189 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
00190 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
00191 /**
00192   * @}
00193   */
00194
00195 /* Exported functions --------------------------------------------------------*/
00196
00197 /** @defgroup IRDA_Exported_Functions IRDA Exported Functions
00198   * @{
00199   */
00200
00201 /** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
00202   *  @brief    Initialization and Configuration functions
00203   *
00204 @verbatim
00205   ==============================================================================
00206               ##### Initialization and Configuration functions #####
00207   ==============================================================================
00208   [..]
00209   This subsection provides a set of functions allowing to initialize the USARTx
00210   in asynchronous IRDA mode.
00211   (+) For the asynchronous mode only these parameters can be configured:
00212       (++) Baud Rate
00213       (++) Word Length
00214       (++) Parity: If the parity is enabled, then the MSB bit of the data written
00215            in the data register is transmitted but is changed by the parity bit.
00216       (++) Power mode
00217       (++) Prescaler setting
00218       (++) Receiver/transmitter modes
00219
00220   [..]
00221   The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
00222   (details for the procedures are available in reference manual).
00223
00224 @endverbatim
00225
00226   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00227   8-bit or 9-bit), the possible IRDA frame formats are listed in the
00228   following table.
00229
00230     Table 1. IRDA frame format.
00231     +-----------------------------------------------------------------------+
00232     |  M1 bit |  M0 bit |  PCE bit  |             IRDA frame                |
00233     |---------|---------|-----------|---------------------------------------|
00234     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00235     |---------|---------|-----------|---------------------------------------|
00236     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00237     |---------|---------|-----------|---------------------------------------|
00238     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00239     |---------|---------|-----------|---------------------------------------|
00240     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00241     |---------|---------|-----------|---------------------------------------|
00242     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00243     |---------|---------|-----------|---------------------------------------|
00244     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00245     +-----------------------------------------------------------------------+
00246
00247   * @{
00248   */
00249
00250 /**
00251   * @brief Initialize the IRDA mode according to the specified
00252   *        parameters in the IRDA_InitTypeDef and initialize the associated handle.
00253   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00254   *               the configuration information for the specified IRDA module.
00255   * @retval HAL status
00256   */
00257 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
00258 {
00259   /* Check the IRDA handle allocation */
00260   if(hirda == NULL)
00261   {
00262     return HAL_ERROR;
00263   }
00264
00265   /* Check the USART/UART associated to the IRDA handle */
00266   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
00267
00268   if(hirda->gState == HAL_IRDA_STATE_RESET)
00269   {
00270     /* Allocate lock resource and initialize it */
00271     hirda->Lock = HAL_UNLOCKED;
00272
00273     /* Init the low level hardware : GPIO, CLOCK */
00274     HAL_IRDA_MspInit(hirda);
00275   }
00276
00277   hirda->gState = HAL_IRDA_STATE_BUSY;
00278
00279   /* Disable the Peripheral to update the configuration registers */
00280   __HAL_IRDA_DISABLE(hirda);
00281
00282   /* Set the IRDA Communication parameters */
00283   if (IRDA_SetConfig(hirda) == HAL_ERROR)
00284   {
00285     return HAL_ERROR;
00286   }
00287
00288   /* In IRDA mode, the following bits must be kept cleared:
00289   - LINEN, STOP and CLKEN bits in the USART_CR2 register,
00290   - SCEN and HDSEL bits in the USART_CR3 register.*/
00291   CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
00292   CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
00293
00294   /* set the UART/USART in IRDA mode */
00295   hirda->Instance->CR3 |= USART_CR3_IREN;
00296
00297   /* Enable the Peripheral */
00298   __HAL_IRDA_ENABLE(hirda);
00299
00300   /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
00301   return (IRDA_CheckIdleState(hirda));
00302 }
00303
00304 /**
00305   * @brief DeInitialize the IRDA peripheral.
00306   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00307   *               the configuration information for the specified IRDA module.
00308   * @retval HAL status
00309   */
00310 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
00311 {
00312   /* Check the IRDA handle allocation */
00313   if(hirda == NULL)
00314   {
00315     return HAL_ERROR;
00316   }
00317
00318   /* Check the USART/UART associated to the IRDA handle */
00319   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
00320
00321   hirda->gState = HAL_IRDA_STATE_BUSY;
00322
00323   /* DeInit the low level hardware */
00324   HAL_IRDA_MspDeInit(hirda);
00325   /* Disable the Peripheral */
00326   __HAL_IRDA_DISABLE(hirda);
00327
00328   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00329   hirda->gState = HAL_IRDA_STATE_RESET;
00330   hirda->RxState = HAL_IRDA_STATE_RESET;
00331
00332   /* Process Unlock */
00333   __HAL_UNLOCK(hirda);
00334
00335   return HAL_OK;
00336 }
00337
00338 /**
00339   * @brief Initialize the IRDA MSP.
00340   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00341   *               the configuration information for the specified IRDA module.
00342   * @retval None
00343   */
00344 __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
00345 {
00346   /* Prevent unused argument(s) compilation warning */
00347   UNUSED(hirda);
00348
00349   /* NOTE: This function should not be modified, when the callback is needed,
00350            the HAL_IRDA_MspInit can be implemented in the user file
00351    */
00352 }
00353
00354 /**
00355   * @brief DeInitialize the IRDA MSP.
00356   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00357   *               the configuration information for the specified IRDA module.
00358   * @retval None
00359   */
00360 __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
00361 {
00362   /* Prevent unused argument(s) compilation warning */
00363   UNUSED(hirda);
00364
00365   /* NOTE: This function should not be modified, when the callback is needed,
00366            the HAL_IRDA_MspDeInit can be implemented in the user file
00367    */
00368 }
00369
00370 /**
00371   * @}
00372   */
00373
00374 /** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
00375   *  @brief   IRDA Transmit and Receive functions
00376   *
00377 @verbatim
00378   ==============================================================================
00379                          ##### IO operation functions #####
00380   ==============================================================================
00381   [..]
00382     This subsection provides a set of functions allowing to manage the IRDA data transfers.
00383
00384   [..]
00385     IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
00386     on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
00387     is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
00388     While receiving data, transmission should be avoided as the data to be transmitted
00389     could be corrupted.
00390
00391     (#) There are two modes of transfer:
00392         (++) Blocking mode: the communication is performed in polling mode.
00393              The HAL status of all data processing is returned by the same function
00394              after finishing transfer.
00395         (++) Non-Blocking mode: the communication is performed using Interrupts
00396              or DMA, these API's return the HAL status.
00397              The end of the data processing will be indicated through the
00398              dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
00399              using DMA mode.
00400              The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
00401              will be executed respectively at the end of the Transmit or Receive process
00402              The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
00403
00404     (#) Blocking mode APIs are :
00405         (++) HAL_IRDA_Transmit()
00406         (++) HAL_IRDA_Receive()
00407
00408     (#) Non Blocking mode APIs with Interrupt are :
00409         (++) HAL_IRDA_Transmit_IT()
00410         (++) HAL_IRDA_Receive_IT()
00411         (++) HAL_IRDA_IRQHandler()
00412
00413     (#) Non Blocking mode functions with DMA are :
00414         (++) HAL_IRDA_Transmit_DMA()
00415         (++) HAL_IRDA_Receive_DMA()
00416         (++) HAL_IRDA_DMAPause()
00417         (++) HAL_IRDA_DMAResume()
00418         (++) HAL_IRDA_DMAStop()
00419
00420     (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
00421         (++) HAL_IRDA_TxHalfCpltCallback()
00422         (++) HAL_IRDA_TxCpltCallback()
00423         (++) HAL_IRDA_RxHalfCpltCallback()
00424         (++) HAL_IRDA_RxCpltCallback()
00425         (++) HAL_IRDA_ErrorCallback()
00426
00427     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00428         (+) HAL_IRDA_Abort()
00429         (+) HAL_IRDA_AbortTransmit()
00430         (+) HAL_IRDA_AbortReceive()
00431         (+) HAL_IRDA_Abort_IT()
00432         (+) HAL_IRDA_AbortTransmit_IT()
00433         (+) HAL_IRDA_AbortReceive_IT()
00434
00435     (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
00436         (+) HAL_IRDA_AbortCpltCallback()
00437         (+) HAL_IRDA_AbortTransmitCpltCallback()
00438         (+) HAL_IRDA_AbortReceiveCpltCallback()
00439
00440     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00441         Errors are handled as follows :
00442        (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00443            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
00444            Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
00445            and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
00446            If user wants to abort it, Abort services should be called by user.
00447        (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00448            This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
00449            Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
00450
00451 @endverbatim
00452   * @{
00453   */
00454
00455 /**
00456   * @brief Send an amount of data in blocking mode.
00457   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00458   *               the configuration information for the specified IRDA module.
00459   * @param pData: Pointer to data buffer.
00460   * @param Size: Amount of data to be sent.
00461   * @param  Timeout: Specify timeout value.
00462   * @retval HAL status
00463   */
00464 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00465 {
00466   uint16_t* tmp;
00467   uint32_t tickstart = 0U;
00468
00469   /* Check that a Tx process is not already ongoing */
00470   if(hirda->gState == HAL_IRDA_STATE_READY)
00471   {
00472     if((pData == NULL) || (Size == 0))
00473     {
00474       return  HAL_ERROR;
00475     }
00476
00477     /* Process Locked */
00478     __HAL_LOCK(hirda);
00479
00480     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00481
00482     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00483
00484     /* Init tickstart for timeout managment */
00485     tickstart = HAL_GetTick();
00486
00487     hirda->TxXferSize = Size;
00488     hirda->TxXferCount = Size;
00489     while(hirda->TxXferCount > 0)
00490     {
00491       hirda->TxXferCount--;
00492
00493       if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00494       {
00495         return HAL_TIMEOUT;
00496       }
00497       if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
00498       {
00499         tmp = (uint16_t*) pData;
00500         hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
00501         pData += 2;
00502       }
00503       else
00504       {
00505         hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF);
00506       }
00507     }
00508
00509     if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00510     {
00511       return HAL_TIMEOUT;
00512     }
00513
00514     /* At end of Tx process, restore hirda->gState to Ready */
00515     hirda->gState = HAL_IRDA_STATE_READY;
00516
00517     /* Process Unlocked */
00518     __HAL_UNLOCK(hirda);
00519
00520     return HAL_OK;
00521   }
00522   else
00523   {
00524     return HAL_BUSY;
00525   }
00526 }
00527
00528 /**
00529   * @brief Receive an amount of data in blocking mode.
00530   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00531   *                the configuration information for the specified IRDA module.
00532   * @param pData: Pointer to data buffer.
00533   * @param Size: Amount of data to be received.
00534   * @param  Timeout: Specify timeout value.
00535   * @retval HAL status
00536   */
00537 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00538 {
00539   uint16_t* tmp;
00540   uint16_t uhMask;
00541   uint32_t tickstart = 0U;
00542
00543   /* Check that a Rx process is not already ongoing */
00544   if(hirda->RxState == HAL_IRDA_STATE_READY)
00545   {
00546     if((pData == NULL) || (Size == 0))
00547     {
00548       return  HAL_ERROR;
00549     }
00550
00551     /* Process Locked */
00552     __HAL_LOCK(hirda);
00553
00554     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00555
00556     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
00557
00558     /* Init tickstart for timeout managment */
00559     tickstart = HAL_GetTick();
00560
00561     hirda->RxXferSize = Size;
00562     hirda->RxXferCount = Size;
00563
00564     /* Computation of the mask to apply to the RDR register
00565        of the UART associated to the IRDA */
00566     IRDA_MASK_COMPUTATION(hirda);
00567     uhMask = hirda->Mask;
00568
00569     /* Check data remaining to be received */
00570     while(hirda->RxXferCount > 0)
00571     {
00572       hirda->RxXferCount--;
00573
00574       if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00575       {
00576         return HAL_TIMEOUT;
00577       }
00578       if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
00579       {
00580         tmp = (uint16_t*) pData ;
00581         *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
00582         pData +=2;
00583       }
00584       else
00585       {
00586         *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
00587       }
00588     }
00589
00590     /* At end of Rx process, restore hirda->RxState to Ready */
00591     hirda->RxState = HAL_IRDA_STATE_READY;
00592
00593     /* Process Unlocked */
00594     __HAL_UNLOCK(hirda);
00595
00596     return HAL_OK;
00597   }
00598   else
00599   {
00600     return HAL_BUSY;
00601   }
00602 }
00603
00604 /**
00605   * @brief Send an amount of data in interrupt mode.
00606   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00607   *                the configuration information for the specified IRDA module.
00608   * @param pData: Pointer to data buffer.
00609   * @param Size: Amount of data to be sent.
00610   * @retval HAL status
00611   */
00612 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00613 {
00614   /* Check that a Tx process is not already ongoing */
00615   if(hirda->gState == HAL_IRDA_STATE_READY)
00616   {
00617     if((pData == NULL) || (Size == 0))
00618     {
00619       return HAL_ERROR;
00620     }
00621
00622     /* Process Locked */
00623     __HAL_LOCK(hirda);
00624
00625     hirda->pTxBuffPtr = pData;
00626     hirda->TxXferSize = Size;
00627     hirda->TxXferCount = Size;
00628
00629     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00630
00631     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00632
00633     /* Process Unlocked */
00634     __HAL_UNLOCK(hirda);
00635
00636     /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
00637     SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
00638
00639     /* Enable the IRDA Transmit Data Register Empty Interrupt */
00640     SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
00641
00642     return HAL_OK;
00643   }
00644   else
00645   {
00646     return HAL_BUSY;
00647   }
00648 }
00649
00650 /**
00651   * @brief Receive an amount of data in interrupt mode.
00652   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00653   *                the configuration information for the specified IRDA module.
00654   * @param pData: Pointer to data buffer.
00655   * @param Size: Amount of data to be received.
00656   * @retval HAL status
00657   */
00658 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00659 {
00660   /* Check that a Rx process is not already ongoing */
00661   if(hirda->RxState == HAL_IRDA_STATE_READY)
00662   {
00663     if((pData == NULL) || (Size == 0))
00664     {
00665       return HAL_ERROR;
00666     }
00667
00668     /* Process Locked */
00669     __HAL_LOCK(hirda);
00670
00671     hirda->pRxBuffPtr = pData;
00672     hirda->RxXferSize = Size;
00673     hirda->RxXferCount = Size;
00674
00675     /* Computation of the mask to apply to the RDR register
00676        of the UART associated to the IRDA */
00677     IRDA_MASK_COMPUTATION(hirda);
00678
00679     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00680
00681     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
00682
00683     /* Process Unlocked */
00684     __HAL_UNLOCK(hirda);
00685
00686     /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
00687     SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
00688
00689     /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
00690     SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
00691
00692     return HAL_OK;
00693   }
00694   else
00695   {
00696     return HAL_BUSY;
00697   }
00698 }
00699
00700 /**
00701   * @brief Send an amount of data in DMA mode.
00702   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00703   *               the configuration information for the specified IRDA module.
00704   * @param pData: pointer to data buffer.
00705   * @param Size: amount of data to be sent.
00706   * @retval HAL status
00707   */
00708 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00709 {
00710   /* Check that a Tx process is not already ongoing */
00711   if(hirda->gState == HAL_IRDA_STATE_READY)
00712   {
00713     if((pData == NULL) || (Size == 0))
00714     {
00715       return HAL_ERROR;
00716     }
00717
00718     /* Process Locked */
00719     __HAL_LOCK(hirda);
00720
00721     hirda->pTxBuffPtr = pData;
00722     hirda->TxXferSize = Size;
00723     hirda->TxXferCount = Size;
00724
00725     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00726
00727     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00728
00729     /* Set the IRDA DMA transfer complete callback */
00730     hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
00731
00732     /* Set the IRDA DMA half transfer complete callback */
00733     hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
00734
00735     /* Set the DMA error callback */
00736     hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
00737
00738     /* Set the DMA abort callback */
00739     hirda->hdmatx->XferAbortCallback = NULL;
00740
00741     /* Enable the IRDA transmit DMA channel */
00742     HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size);
00743
00744     /* Clear the TC flag in the ICR register */
00745     __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
00746
00747     /* Process Unlocked */
00748     __HAL_UNLOCK(hirda);
00749
00750     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00751        in the USART CR3 register */
00752     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
00753
00754     return HAL_OK;
00755   }
00756   else
00757   {
00758     return HAL_BUSY;
00759   }
00760 }
00761
00762 /**
00763   * @brief Receive an amount of data in DMA mode.
00764   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00765   *               the configuration information for the specified IRDA module.
00766   * @param pData: Pointer to data buffer.
00767   * @param Size: Amount of data to be received.
00768   * @note   When the IRDA parity is enabled (PCE = 1) the received data contains
00769   *         the parity bit (MSB position).
00770   * @retval HAL status
00771   */
00772 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00773 {
00774   /* Check that a Rx process is not already ongoing */
00775   if(hirda->RxState == HAL_IRDA_STATE_READY)
00776   {
00777     if((pData == NULL) || (Size == 0))
00778     {
00779       return HAL_ERROR;
00780     }
00781
00782     /* Process Locked */
00783     __HAL_LOCK(hirda);
00784
00785     hirda->pRxBuffPtr = pData;
00786     hirda->RxXferSize = Size;
00787
00788     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00789
00790     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
00791
00792     /* Set the IRDA DMA transfer complete callback */
00793     hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
00794
00795     /* Set the IRDA DMA half transfer complete callback */
00796     hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
00797
00798     /* Set the DMA error callback */
00799     hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
00800
00801     /* Set the DMA abort callback */
00802     hirda->hdmarx->XferAbortCallback = NULL;
00803
00804     /* Enable the DMA channel */
00805     HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size);
00806
00807     /* Process Unlocked */
00808     __HAL_UNLOCK(hirda);
00809
00810     /* Enable the IRDA Parity Error Interrupt */
00811     SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
00812
00813     /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
00814     SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
00815
00816     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
00817        in the USART CR3 register */
00818     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
00819
00820     return HAL_OK;
00821   }
00822   else
00823   {
00824     return HAL_BUSY;
00825   }
00826 }
00827
00828
00829 /**
00830   * @brief Pause the DMA Transfer.
00831   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00832   *                the configuration information for the specified IRDA module.
00833   * @retval HAL status
00834   */
00835 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
00836 {
00837   /* Process Locked */
00838   __HAL_LOCK(hirda);
00839
00840   if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
00841       (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
00842   {
00843     /* Disable the IRDA DMA Tx request */
00844     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
00845   }
00846   if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
00847       (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
00848   {
00849     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
00850     CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
00851     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
00852
00853     /* Disable the IRDA DMA Rx request */
00854     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
00855   }
00856
00857   /* Process Unlocked */
00858   __HAL_UNLOCK(hirda);
00859
00860   return HAL_OK;
00861 }
00862
00863 /**
00864   * @brief Resume the DMA Transfer.
00865   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00866   *                the configuration information for the specified IRDA module.
00867   * @retval HAL status
00868   */
00869 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
00870 {
00871   /* Process Locked */
00872   __HAL_LOCK(hirda);
00873
00874   if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
00875   {
00876     /* Enable the IRDA DMA Tx request */
00877     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
00878   }
00879   if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
00880   {
00881     /* Clear the Overrun flag before resuming the Rx transfer*/
00882     __HAL_IRDA_CLEAR_OREFLAG(hirda);
00883
00884     /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
00885     SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
00886     SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
00887
00888     /* Enable the IRDA DMA Rx request */
00889     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
00890   }
00891
00892   /* Process Unlocked */
00893   __HAL_UNLOCK(hirda);
00894
00895   return HAL_OK;
00896 }
00897
00898 /**
00899   * @brief Stop the DMA Transfer.
00900   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00901   *                the configuration information for the specified IRDA module.
00902   * @retval HAL status
00903   */
00904 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
00905 {
00906   /* The Lock is not implemented on this API to allow the user application
00907      to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
00908      HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:
00909      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
00910      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
00911      the stream and the corresponding call back is executed. */
00912
00913   /* Stop IRDA DMA Tx request if ongoing */
00914   if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
00915       (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
00916   {
00917     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
00918
00919     /* Abort the IRDA DMA Tx channel */
00920     if(hirda->hdmatx != NULL)
00921     {
00922       HAL_DMA_Abort(hirda->hdmatx);
00923     }
00924
00925     IRDA_EndTxTransfer(hirda);
00926   }
00927
00928   /* Stop IRDA DMA Rx request if ongoing */
00929   if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
00930       (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
00931   {
00932     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
00933
00934     /* Abort the IRDA DMA Rx channel */
00935     if(hirda->hdmarx != NULL)
00936     {
00937       HAL_DMA_Abort(hirda->hdmarx);
00938     }
00939
00940     IRDA_EndRxTransfer(hirda);
00941   }
00942
00943   return HAL_OK;
00944 }
00945
00946 /**
00947   * @brief  Abort ongoing transfers (blocking mode).
00948   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00949   *               the configuration information for the specified UART module.
00950   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
00951   *         This procedure performs following operations :
00952   *           - Disable IRDA Interrupts (Tx and Rx)
00953   *           - Disable the DMA transfer in the peripheral register (if enabled)
00954   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
00955   *           - Set handle State to READY
00956   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
00957   * @retval HAL status
00958 */
00959 HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
00960 {
00961   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
00962   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
00963   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
00964
00965   /* Disable the IRDA DMA Tx request if enabled */
00966   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
00967   {
00968     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
00969
00970     /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
00971     if(hirda->hdmatx != NULL)
00972     {
00973       /* Set the IRDA DMA Abort callback to Null.
00974          No call back execution at end of DMA abort procedure */
00975       hirda->hdmatx->XferAbortCallback = NULL;
00976
00977       HAL_DMA_Abort(hirda->hdmatx);
00978     }
00979   }
00980
00981   /* Disable the IRDA DMA Rx request if enabled */
00982   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
00983   {
00984     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
00985
00986     /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
00987     if(hirda->hdmarx != NULL)
00988     {
00989       /* Set the IRDA DMA Abort callback to Null.
00990          No call back execution at end of DMA abort procedure */
00991       hirda->hdmarx->XferAbortCallback = NULL;
00992
00993       HAL_DMA_Abort(hirda->hdmarx);
00994     }
00995   }
00996
00997   /* Reset Tx and Rx transfer counters */
00998   hirda->TxXferCount = 0;
00999   hirda->RxXferCount = 0;
01000
01001   /* Clear the Error flags in the ICR register */
01002   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01003
01004   /* Restore hirda->gState and hirda->RxState to Ready */
01005   hirda->gState  = HAL_IRDA_STATE_READY;
01006   hirda->RxState = HAL_IRDA_STATE_READY;
01007
01008   /* Reset Handle ErrorCode to No Error */
01009   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01010
01011   return HAL_OK;
01012 }
01013
01014 /**
01015   * @brief  Abort ongoing Transmit transfer (blocking mode).
01016   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01017   *               the configuration information for the specified UART module.
01018   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01019   *         This procedure performs following operations :
01020   *           - Disable IRDA Interrupts (Tx)
01021   *           - Disable the DMA transfer in the peripheral register (if enabled)
01022   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01023   *           - Set handle State to READY
01024   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01025   * @retval HAL status
01026 */
01027 HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
01028 {
01029   /* Disable TXEIE and TCIE interrupts */
01030   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
01031
01032   /* Disable the IRDA DMA Tx request if enabled */
01033   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01034   {
01035     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01036
01037     /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
01038     if(hirda->hdmatx != NULL)
01039     {
01040       /* Set the IRDA DMA Abort callback to Null.
01041          No call back execution at end of DMA abort procedure */
01042       hirda->hdmatx->XferAbortCallback = NULL;
01043
01044       HAL_DMA_Abort(hirda->hdmatx);
01045     }
01046   }
01047
01048   /* Reset Tx transfer counter */
01049   hirda->TxXferCount = 0;
01050
01051   /* Restore hirda->gState to Ready */
01052   hirda->gState = HAL_IRDA_STATE_READY;
01053
01054   return HAL_OK;
01055 }
01056
01057 /**
01058   * @brief  Abort ongoing Receive transfer (blocking mode).
01059   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01060   *               the configuration information for the specified UART module.
01061   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01062   *         This procedure performs following operations :
01063   *           - Disable IRDA Interrupts (Rx)
01064   *           - Disable the DMA transfer in the peripheral register (if enabled)
01065   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01066   *           - Set handle State to READY
01067   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01068   * @retval HAL status
01069 */
01070 HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
01071 {
01072   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01073   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01074   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01075
01076   /* Disable the IRDA DMA Rx request if enabled */
01077   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01078   {
01079     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01080
01081     /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
01082     if(hirda->hdmarx != NULL)
01083     {
01084       /* Set the IRDA DMA Abort callback to Null.
01085          No call back execution at end of DMA abort procedure */
01086       hirda->hdmarx->XferAbortCallback = NULL;
01087
01088       HAL_DMA_Abort(hirda->hdmarx);
01089     }
01090   }
01091
01092   /* Reset Rx transfer counter */
01093   hirda->RxXferCount = 0;
01094
01095   /* Clear the Error flags in the ICR register */
01096   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01097
01098   /* Restore hirda->RxState to Ready */
01099   hirda->RxState = HAL_IRDA_STATE_READY;
01100
01101   return HAL_OK;
01102 }
01103
01104 /**
01105   * @brief  Abort ongoing transfers (Interrupt mode).
01106   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01107   *               the configuration information for the specified UART module.
01108   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01109   *         This procedure performs following operations :
01110   *           - Disable IRDA Interrupts (Tx and Rx)
01111   *           - Disable the DMA transfer in the peripheral register (if enabled)
01112   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01113   *           - Set handle State to READY
01114   *           - At abort completion, call user abort complete callback
01115   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01116   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01117   * @retval HAL status
01118 */
01119 HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
01120 {
01121   uint32_t abortcplt = 1;
01122
01123   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01124   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
01125   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01126
01127   /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
01128      before any call to DMA Abort functions */
01129   /* DMA Tx Handle is valid */
01130   if(hirda->hdmatx != NULL)
01131   {
01132     /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
01133        Otherwise, set it to NULL */
01134     if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01135     {
01136       hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
01137     }
01138     else
01139     {
01140       hirda->hdmatx->XferAbortCallback = NULL;
01141     }
01142   }
01143   /* DMA Rx Handle is valid */
01144   if(hirda->hdmarx != NULL)
01145   {
01146     /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
01147        Otherwise, set it to NULL */
01148     if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01149     {
01150       hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
01151     }
01152     else
01153     {
01154       hirda->hdmarx->XferAbortCallback = NULL;
01155     }
01156   }
01157
01158   /* Disable the IRDA DMA Tx request if enabled */
01159   if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01160   {
01161     /* Disable DMA Tx at UART level */
01162     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01163
01164     /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
01165     if(hirda->hdmatx != NULL)
01166     {
01167       /* IRDA Tx DMA Abort callback has already been initialised :
01168          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01169
01170       /* Abort DMA TX */
01171       if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
01172       {
01173         hirda->hdmatx->XferAbortCallback = NULL;
01174       }
01175       else
01176       {
01177         abortcplt = 0;
01178       }
01179     }
01180   }
01181
01182   /* Disable the IRDA DMA Rx request if enabled */
01183   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01184   {
01185     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01186
01187     /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
01188     if(hirda->hdmarx != NULL)
01189     {
01190       /* IRDA Rx DMA Abort callback has already been initialised :
01191          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01192
01193       /* Abort DMA RX */
01194       if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
01195       {
01196         hirda->hdmarx->XferAbortCallback = NULL;
01197         abortcplt = 1;
01198       }
01199       else
01200       {
01201         abortcplt = 0;
01202       }
01203     }
01204   }
01205
01206   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01207   if (abortcplt == 1)
01208   {
01209     /* Reset Tx and Rx transfer counters */
01210     hirda->TxXferCount = 0;
01211     hirda->RxXferCount = 0;
01212
01213     /* Reset errorCode */
01214     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01215
01216     /* Clear the Error flags in the ICR register */
01217     __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01218
01219     /* Restore hirda->gState and hirda->RxState to Ready */
01220     hirda->gState  = HAL_IRDA_STATE_READY;
01221     hirda->RxState = HAL_IRDA_STATE_READY;
01222
01223     /* As no DMA to be aborted, call directly user Abort complete callback */
01224     HAL_IRDA_AbortCpltCallback(hirda);
01225   }
01226
01227   return HAL_OK;
01228 }
01229
01230 /**
01231   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
01232   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01233   *               the configuration information for the specified UART module.
01234   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01235   *         This procedure performs following operations :
01236   *           - Disable IRDA Interrupts (Tx)
01237   *           - Disable the DMA transfer in the peripheral register (if enabled)
01238   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01239   *           - Set handle State to READY
01240   *           - At abort completion, call user abort complete callback
01241   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01242   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01243   * @retval HAL status
01244 */
01245 HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
01246 {
01247   /* Disable TXEIE and TCIE interrupts */
01248   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
01249
01250   /* Disable the IRDA DMA Tx request if enabled */
01251   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01252   {
01253     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01254
01255     /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
01256     if(hirda->hdmatx != NULL)
01257     {
01258       /* Set the IRDA DMA Abort callback :
01259          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01260       hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
01261
01262       /* Abort DMA TX */
01263       if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
01264       {
01265         /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
01266         hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
01267       }
01268     }
01269     else
01270     {
01271       /* Reset Tx transfer counter */
01272       hirda->TxXferCount = 0;
01273
01274       /* Restore hirda->gState to Ready */
01275       hirda->gState = HAL_IRDA_STATE_READY;
01276
01277       /* As no DMA to be aborted, call directly user Abort complete callback */
01278       HAL_IRDA_AbortTransmitCpltCallback(hirda);
01279     }
01280   }
01281   else
01282   {
01283     /* Reset Tx transfer counter */
01284     hirda->TxXferCount = 0;
01285
01286     /* Restore hirda->gState to Ready */
01287     hirda->gState = HAL_IRDA_STATE_READY;
01288
01289     /* As no DMA to be aborted, call directly user Abort complete callback */
01290     HAL_IRDA_AbortTransmitCpltCallback(hirda);
01291   }
01292
01293   return HAL_OK;
01294 }
01295
01296 /**
01297   * @brief  Abort ongoing Receive transfer (Interrupt mode).
01298   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01299   *               the configuration information for the specified UART module.
01300   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01301   *         This procedure performs following operations :
01302   *           - Disable IRDA Interrupts (Rx)
01303   *           - Disable the DMA transfer in the peripheral register (if enabled)
01304   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01305   *           - Set handle State to READY
01306   *           - At abort completion, call user abort complete callback
01307   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01308   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01309   * @retval HAL status
01310 */
01311 HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
01312 {
01313   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01314   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01315   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01316
01317   /* Disable the IRDA DMA Rx request if enabled */
01318   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01319   {
01320     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01321
01322     /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
01323     if(hirda->hdmarx != NULL)
01324     {
01325       /* Set the IRDA DMA Abort callback :
01326          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01327       hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
01328
01329       /* Abort DMA RX */
01330       if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
01331       {
01332         /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
01333         hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
01334       }
01335     }
01336     else
01337     {
01338       /* Reset Rx transfer counter */
01339       hirda->RxXferCount = 0;
01340
01341       /* Clear the Error flags in the ICR register */
01342       __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01343
01344       /* Restore hirda->RxState to Ready */
01345       hirda->RxState = HAL_IRDA_STATE_READY;
01346
01347       /* As no DMA to be aborted, call directly user Abort complete callback */
01348       HAL_IRDA_AbortReceiveCpltCallback(hirda);
01349     }
01350   }
01351   else
01352   {
01353     /* Reset Rx transfer counter */
01354     hirda->RxXferCount = 0;
01355
01356     /* Clear the Error flags in the ICR register */
01357     __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01358
01359     /* Restore hirda->RxState to Ready */
01360     hirda->RxState = HAL_IRDA_STATE_READY;
01361
01362     /* As no DMA to be aborted, call directly user Abort complete callback */
01363     HAL_IRDA_AbortReceiveCpltCallback(hirda);
01364   }
01365
01366   return HAL_OK;
01367 }
01368
01369 /**
01370   * @brief  Handle IRDA interrupt request.
01371   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01372   *               the configuration information for the specified IRDA module.
01373   * @retval None
01374   */
01375 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
01376 {
01377   uint32_t isrflags   = READ_REG(hirda->Instance->ISR);
01378   uint32_t cr1its     = READ_REG(hirda->Instance->CR1);
01379   uint32_t cr3its;
01380   uint32_t errorflags;
01381
01382   /* If no error occurs */
01383   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
01384   if (errorflags == RESET)
01385   {
01386     /* IRDA in mode Receiver ---------------------------------------------------*/
01387     if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01388     {
01389       IRDA_Receive_IT(hirda);
01390       return;
01391     }
01392   }
01393
01394   /* If some errors occur */
01395   cr3its = READ_REG(hirda->Instance->CR3);
01396   if(   (errorflags != RESET)
01397      && (    ((cr3its & USART_CR3_EIE) != RESET)
01398           || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
01399   {
01400     /* IRDA parity error interrupt occurred -------------------------------------*/
01401     if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
01402     {
01403       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
01404
01405       hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
01406     }
01407
01408     /* IRDA frame error interrupt occurred --------------------------------------*/
01409     if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01410     {
01411       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
01412
01413       hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
01414     }
01415
01416     /* IRDA noise error interrupt occurred --------------------------------------*/
01417     if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01418     {
01419       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
01420
01421       hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
01422     }
01423
01424     /* IRDA Over-Run interrupt occurred -----------------------------------------*/
01425     if(((isrflags & USART_ISR_ORE) != RESET) &&
01426       (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
01427     {
01428       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
01429
01430       hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
01431     }
01432
01433     /* Call IRDA Error Call back function if need be --------------------------*/
01434     if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
01435     {
01436       /* IRDA in mode Receiver ---------------------------------------------------*/
01437       if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01438       {
01439         IRDA_Receive_IT(hirda);
01440       }
01441
01442       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
01443          consider error as blocking */
01444       if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) ||
01445           (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
01446       {
01447         /* Blocking error : transfer is aborted
01448            Set the IRDA state ready to be able to start again the process,
01449            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
01450         IRDA_EndRxTransfer(hirda);
01451
01452         /* Disable the IRDA DMA Rx request if enabled */
01453         if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01454         {
01455           CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01456
01457           /* Abort the IRDA DMA Rx channel */
01458           if(hirda->hdmarx != NULL)
01459           {
01460             /* Set the IRDA DMA Abort callback :
01461                will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
01462             hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
01463
01464             /* Abort DMA RX */
01465             if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
01466             {
01467               /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
01468               hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
01469             }
01470           }
01471           else
01472           {
01473             /* Call user error callback */
01474             HAL_IRDA_ErrorCallback(hirda);
01475           }
01476         }
01477         else
01478         {
01479           /* Call user error callback */
01480           HAL_IRDA_ErrorCallback(hirda);
01481         }
01482       }
01483       else
01484       {
01485         /* Non Blocking error : transfer could go on.
01486            Error is notified to user through user error callback */
01487         HAL_IRDA_ErrorCallback(hirda);
01488         hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01489       }
01490     }
01491     return;
01492
01493   } /* End if some error occurs */
01494
01495   /* IRDA in mode Transmitter ------------------------------------------------*/
01496   if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
01497   {
01498     IRDA_Transmit_IT(hirda);
01499     return;
01500   }
01501
01502   /* IRDA in mode Transmitter (transmission end) -----------------------------*/
01503   if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
01504   {
01505     IRDA_EndTransmit_IT(hirda);
01506     return;
01507   }
01508
01509 }
01510
01511 /**
01512   * @brief  Tx Transfer completed callback.
01513   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01514   *                the configuration information for the specified IRDA module.
01515   * @retval None
01516   */
01517 __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
01518 {
01519   /* Prevent unused argument(s) compilation warning */
01520   UNUSED(hirda);
01521
01522   /* NOTE: This function should not be modified, when the callback is needed,
01523            the HAL_IRDA_TxCpltCallback can be implemented in the user file.
01524    */
01525 }
01526
01527 /**
01528   * @brief  Tx Half Transfer completed callback.
01529   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01530   *                the configuration information for the specified USART module.
01531   * @retval None
01532   */
01533 __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
01534 {
01535   /* Prevent unused argument(s) compilation warning */
01536   UNUSED(hirda);
01537
01538   /* NOTE: This function should not be modified, when the callback is needed,
01539            the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
01540    */
01541 }
01542
01543 /**
01544   * @brief  Rx Transfer completed callback.
01545   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01546   *                the configuration information for the specified IRDA module.
01547   * @retval None
01548   */
01549 __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
01550 {
01551   /* Prevent unused argument(s) compilation warning */
01552   UNUSED(hirda);
01553
01554   /* NOTE: This function should not be modified, when the callback is needed,
01555            the HAL_IRDA_RxCpltCallback can be implemented in the user file.
01556    */
01557 }
01558
01559 /**
01560   * @brief  Rx Half Transfer complete callback.
01561   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01562   *                the configuration information for the specified IRDA module.
01563   * @retval None
01564   */
01565 __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
01566 {
01567   /* Prevent unused argument(s) compilation warning */
01568   UNUSED(hirda);
01569
01570   /* NOTE : This function should not be modified, when the callback is needed,
01571             the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
01572    */
01573 }
01574
01575 /**
01576   * @brief  IRDA error callback.
01577   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01578   *                the configuration information for the specified IRDA module.
01579   * @retval None
01580   */
01581  __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
01582 {
01583   /* Prevent unused argument(s) compilation warning */
01584   UNUSED(hirda);
01585
01586   /* NOTE: This function should not be modified, when the callback is needed,
01587            the HAL_IRDA_ErrorCallback can be implemented in the user file.
01588    */
01589 }
01590
01591 /**
01592   * @brief  IRDA Abort Complete callback.
01593   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01594   *               the configuration information for the specified IRDA module.
01595   * @retval None
01596   */
01597 __weak void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
01598 {
01599   /* Prevent unused argument(s) compilation warning */
01600   UNUSED(hirda);
01601
01602   /* NOTE : This function should not be modified, when the callback is needed,
01603             the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
01604    */
01605 }
01606
01607 /**
01608   * @brief  IRDA Abort Complete callback.
01609   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01610   *               the configuration information for the specified IRDA module.
01611   * @retval None
01612   */
01613 __weak void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
01614 {
01615   /* Prevent unused argument(s) compilation warning */
01616   UNUSED(hirda);
01617
01618   /* NOTE : This function should not be modified, when the callback is needed,
01619             the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
01620    */
01621 }
01622
01623 /**
01624   * @brief  IRDA Abort Receive Complete callback.
01625   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01626   *               the configuration information for the specified IRDA module.
01627   * @retval None
01628   */
01629 __weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
01630 {
01631   /* Prevent unused argument(s) compilation warning */
01632   UNUSED(hirda);
01633
01634   /* NOTE : This function should not be modified, when the callback is needed,
01635             the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
01636    */
01637 }
01638
01639 /**
01640   * @}
01641   */
01642
01643 /** @defgroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
01644   *  @brief   IRDA State and Errors functions
01645   *
01646 @verbatim
01647   ==============================================================================
01648                   ##### Peripheral State and Error functions #####
01649   ==============================================================================
01650   [..]
01651     This subsection provides a set of functions allowing to return the State of IrDA
01652     communication process and also return Peripheral Errors occurred during communication process
01653      (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
01654          of the IRDA peripheral handle.
01655      (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
01656          communication.
01657
01658 @endverbatim
01659   * @{
01660   */
01661
01662 /**
01663   * @brief Return the IRDA handle state.
01664   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01665   *                the configuration information for the specified IRDA module.
01666   * @retval HAL state
01667   */
01668 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
01669 {
01670   /* Return IRDA handle state */
01671   uint32_t temp1= 0x00, temp2 = 0x00;
01672   temp1 = hirda->gState;
01673   temp2 = hirda->RxState;
01674
01675   return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
01676 }
01677
01678 /**
01679   * @brief Return the IRDA handle error code.
01680   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01681   *               the configuration information for the specified IRDA module.
01682   * @retval IRDA Error Code
01683   */
01684 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
01685 {
01686   return hirda->ErrorCode;
01687 }
01688
01689 /**
01690   * @}
01691   */
01692
01693 /**
01694   * @}
01695   */
01696
01697 /** @defgroup IRDA_Private_Functions IRDA Private Functions
01698   * @{
01699   */
01700
01701 /**
01702   * @brief Configure the IRDA peripheral.
01703   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01704   *               the configuration information for the specified IRDA module.
01705   * @retval None
01706   */
01707 static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
01708 {
01709   uint32_t tmpreg                     = 0x00000000;
01710   IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED;
01711   HAL_StatusTypeDef ret               = HAL_OK;
01712   PLL2_ClocksTypeDef pll2_clocks;
01713   PLL3_ClocksTypeDef pll3_clocks;
01714
01715   /* Check the communication parameters */
01716   assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
01717   assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
01718   assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
01719   assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
01720   assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
01721   assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
01722
01723   /*-------------------------- USART CR1 Configuration -----------------------*/
01724   /* Configure the IRDA Word Length, Parity and transfer Mode:
01725      Set the M bits according to hirda->Init.WordLength value
01726      Set PCE and PS bits according to hirda->Init.Parity value
01727      Set TE and RE bits according to hirda->Init.Mode value */
01728   tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
01729
01730   MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
01731
01732   /*-------------------------- USART CR3 Configuration -----------------------*/
01733   MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
01734
01735   /*-------------------------- USART GTPR Configuration ----------------------*/
01736   MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
01737
01738   /*-------------------------- USART BRR Configuration -----------------------*/
01739   IRDA_GETCLOCKSOURCE(hirda, clocksource);
01740   switch (clocksource)
01741   {
01742     case IRDA_CLOCKSOURCE_D2PCLK1:
01743       hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
01744       break;
01745     case IRDA_CLOCKSOURCE_D2PCLK2:
01746       hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
01747       break;
01748     case IRDA_CLOCKSOURCE_PLL2Q:
01749         HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
01750         hirda->Instance->BRR = (uint16_t)((pll2_clocks.PLL2_Q_Frequency + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
01751       break;
01752     case IRDA_CLOCKSOURCE_PLL3Q:
01753         HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
01754         hirda->Instance->BRR = (uint16_t)((pll3_clocks.PLL3_Q_Frequency + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
01755       break;
01756     case IRDA_CLOCKSOURCE_HSI:
01757       hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
01758       break;
01759     case IRDA_CLOCKSOURCE_CSI:
01760       hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
01761       break;
01762     case IRDA_CLOCKSOURCE_LSE:
01763       hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
01764       break;
01765     case IRDA_CLOCKSOURCE_UNDEFINED:
01766     default:
01767       ret = HAL_ERROR;
01768       break;
01769   }
01770
01771   return ret;
01772 }
01773
01774 /**
01775   * @brief Check the IRDA Idle State.
01776   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01777   *               the configuration information for the specified IRDA module.
01778   * @retval HAL status
01779   */
01780 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
01781 {
01782   uint32_t tickstart = 0U;
01783
01784   /* Initialize the IRDA ErrorCode */
01785   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01786
01787   /* Init tickstart for timeout managment */
01788   tickstart = HAL_GetTick();
01789
01790   /* Check if the Transmitter is enabled */
01791   if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
01792   {
01793     /* Wait until TEACK flag is set */
01794     if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
01795     {
01796       /* Timeout occurred */
01797       return HAL_TIMEOUT;
01798     }
01799   }
01800   /* Check if the Receiver is enabled */
01801   if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
01802   {
01803     if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
01804     {
01805       /* Timeout occurred */
01806       return HAL_TIMEOUT;
01807     }
01808   }
01809
01810   /* Initialize the IRDA state*/
01811   hirda->gState= HAL_IRDA_STATE_READY;
01812   hirda->RxState= HAL_IRDA_STATE_READY;
01813
01814   /* Process Unlocked */
01815   __HAL_UNLOCK(hirda);
01816
01817   return HAL_OK;
01818 }
01819
01820 /**
01821   * @brief  Handle IRDA Communication Timeout.
01822   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01823   *                the configuration information for the specified IRDA module.
01824   * @param  Flag: specifies the IRDA flag to check.
01825   * @param  Status: the new flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status.
01826   * @param  Tickstart: tick start value.
01827   * @param  Timeout: Timeout duration.
01828   * @retval HAL status
01829   */
01830 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
01831 {
01832   /* Wait until flag is set */
01833   while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
01834   {
01835     /* Check for the Timeout */
01836     if(Timeout != HAL_MAX_DELAY)
01837     {
01838       if((Timeout == 0) || ((HAL_GetTick() - Tickstart) > Timeout))
01839       {
01840         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01841         CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
01842         CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01843
01844         hirda->gState  = HAL_IRDA_STATE_READY;
01845         hirda->RxState = HAL_IRDA_STATE_READY;
01846
01847         /* Process Unlocked */
01848         __HAL_UNLOCK(hirda);
01849         return HAL_TIMEOUT;
01850       }
01851     }
01852   }
01853   return HAL_OK;
01854 }
01855
01856 /**
01857   * @brief  End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
01858   * @param  hirda: IRDA handle.
01859   * @retval None
01860   */
01861 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
01862 {
01863   /* Disable TXEIE and TCIE interrupts */
01864   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
01865
01866   /* At end of Tx process, restore hirda->gState to Ready */
01867   hirda->gState = HAL_IRDA_STATE_READY;
01868 }
01869
01870 /**
01871   * @brief  End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).
01872   * @param  hirda: IRDA handle.
01873   * @retval None
01874   */
01875 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
01876 {
01877   /* Disable RXNE, PE and ERR interrupts */
01878   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01879   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01880
01881   /* At end of Rx process, restore hirda->RxState to Ready */
01882   hirda->RxState = HAL_IRDA_STATE_READY;
01883 }
01884
01885 /**
01886   * @brief  DMA IRDA transmit process complete callback.
01887   * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
01888   *               the configuration information for the specified DMA module.
01889   * @retval None
01890   */
01891 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01892 {
01893   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef*)hdma)->Parent;
01894
01895   /* DMA Normal mode */
01896   if (hdma->Init.Mode != DMA_CIRCULAR)
01897   {
01898     hirda->TxXferCount = 0;
01899
01900     /* Disable the DMA transfer for transmit request by resetting the DMAT bit
01901        in the IRDA CR3 register */
01902     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01903
01904     /* Enable the IRDA Transmit Complete Interrupt */
01905     SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
01906   }
01907   /* DMA Circular mode */
01908   else
01909   {
01910     HAL_IRDA_TxCpltCallback(hirda);
01911   }
01912 }
01913
01914 /**
01915   * @brief DMA IRDA receive process half complete callback.
01916   * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
01917   *               the configuration information for the specified DMA module.
01918   * @retval None
01919   */
01920 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
01921 {
01922   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef*)hdma)->Parent;
01923
01924   HAL_IRDA_TxHalfCpltCallback(hirda);
01925 }
01926
01927 /**
01928   * @brief  DMA IRDA receive process complete callback.
01929   * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
01930   *               the configuration information for the specified DMA module.
01931   * @retval None
01932   */
01933 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01934 {
01935   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef*)hdma)->Parent;
01936
01937   /* DMA Normal mode */
01938   if (hdma->Init.Mode != DMA_CIRCULAR)
01939   {
01940     hirda->RxXferCount = 0;
01941
01942     /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01943     CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01944     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01945
01946     /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
01947        in the IRDA CR3 register */
01948     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01949
01950     /* At end of Rx process, restore hirda->RxState to Ready */
01951     hirda->RxState = HAL_IRDA_STATE_READY;
01952   }
01953
01954   HAL_IRDA_RxCpltCallback(hirda);
01955 }
01956
01957 /**
01958   * @brief DMA IRDA receive process half complete callback.
01959   * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
01960   *              the configuration information for the specified DMA module.
01961   * @retval None
01962   */
01963 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
01964 {
01965   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef*)hdma)->Parent;
01966
01967   HAL_IRDA_RxHalfCpltCallback(hirda);
01968 }
01969
01970 /**
01971   * @brief DMA IRDA communication error callback.
01972   * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
01973   *              the configuration information for the specified DMA module.
01974   * @retval None
01975   */
01976 static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
01977 {
01978   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef*)hdma)->Parent;
01979
01980   hirda->RxXferCount = 0U;
01981   hirda->TxXferCount = 0U;
01982
01983   /* Stop IRDA DMA Tx request if ongoing */
01984   if((hirda->gState == HAL_IRDA_STATE_BUSY_TX)
01985       &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
01986   {
01987     IRDA_EndTxTransfer(hirda);
01988   }
01989
01990   /* Stop IRDA DMA Rx request if ongoing */
01991   if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
01992       &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
01993   {
01994     IRDA_EndRxTransfer(hirda);
01995   }
01996
01997   hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
01998
01999   HAL_IRDA_ErrorCallback(hirda);
02000 }
02001
02002 /**
02003   * @brief DMA IRDA communication abort callback
02004   *        (To be called at end of DMA Abort procedure).
02005   * @param hdma: DMA handle.
02006   * @retval None
02007   */
02008 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02009 {
02010   IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02011   hirda->RxXferCount = 0;
02012   hirda->TxXferCount = 0;
02013
02014   HAL_IRDA_ErrorCallback(hirda);
02015 }
02016
02017 /**
02018   * @brief  DMA IRDA Tx communication abort callback, when initiated by user
02019   *         (To be called at end of DMA Tx Abort procedure following user abort request).
02020   * @note   When this callback is executed, User Abort complete call back is called only if no
02021   *         Abort still ongoing for Rx DMA Handle.
02022   * @param  hdma DMA handle.
02023   * @retval None
02024   */
02025 static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
02026 {
02027   IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02028
02029   hirda->hdmatx->XferAbortCallback = NULL;
02030
02031   /* Check if an Abort process is still ongoing */
02032   if(hirda->hdmarx != NULL)
02033   {
02034     if(hirda->hdmarx->XferAbortCallback != NULL)
02035     {
02036       return;
02037     }
02038   }
02039
02040   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02041   hirda->TxXferCount = 0;
02042   hirda->RxXferCount = 0;
02043
02044   /* Reset errorCode */
02045   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
02046
02047   /* Clear the Error flags in the ICR register */
02048   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
02049
02050   /* Restore hirda->gState and hirda->RxState to Ready */
02051   hirda->gState  = HAL_IRDA_STATE_READY;
02052   hirda->RxState = HAL_IRDA_STATE_READY;
02053
02054   /* Call user Abort complete callback */
02055   HAL_IRDA_AbortCpltCallback(hirda);
02056 }
02057
02058
02059 /**
02060   * @brief  DMA IRDA Rx communication abort callback, when initiated by user
02061   *         (To be called at end of DMA Rx Abort procedure following user abort request).
02062   * @note   When this callback is executed, User Abort complete call back is called only if no
02063   *         Abort still ongoing for Tx DMA Handle.
02064   * @param  hdma DMA handle.
02065   * @retval None
02066   */
02067 static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
02068 {
02069   IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02070
02071   hirda->hdmarx->XferAbortCallback = NULL;
02072
02073   /* Check if an Abort process is still ongoing */
02074   if(hirda->hdmatx != NULL)
02075   {
02076     if(hirda->hdmatx->XferAbortCallback != NULL)
02077     {
02078       return;
02079     }
02080   }
02081
02082   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02083   hirda->TxXferCount = 0;
02084   hirda->RxXferCount = 0;
02085
02086   /* Reset errorCode */
02087   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
02088
02089   /* Clear the Error flags in the ICR register */
02090   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
02091
02092   /* Restore hirda->gState and hirda->RxState to Ready */
02093   hirda->gState  = HAL_IRDA_STATE_READY;
02094   hirda->RxState = HAL_IRDA_STATE_READY;
02095
02096   /* Call user Abort complete callback */
02097   HAL_IRDA_AbortCpltCallback(hirda);
02098 }
02099
02100
02101 /**
02102   * @brief  DMA IRDA Tx communication abort callback, when initiated by user by a call to
02103   *         HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
02104   *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
02105   *         and leads to user Tx Abort Complete callback execution).
02106   * @param  hdma DMA handle.
02107   * @retval None
02108   */
02109 static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02110 {
02111   IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02112
02113   hirda->TxXferCount = 0;
02114
02115   /* Restore hirda->gState to Ready */
02116   hirda->gState = HAL_IRDA_STATE_READY;
02117
02118   /* Call user Abort complete callback */
02119   HAL_IRDA_AbortTransmitCpltCallback(hirda);
02120 }
02121
02122 /**
02123   * @brief  DMA IRDA Rx communication abort callback, when initiated by user by a call to
02124   *         HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
02125   *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
02126   *         and leads to user Rx Abort Complete callback execution).
02127   * @param  hdma DMA handle.
02128   * @retval None
02129   */
02130 static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02131 {
02132   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef*)hdma)->Parent;
02133
02134   hirda->RxXferCount = 0;
02135
02136   /* Clear the Error flags in the ICR register */
02137   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
02138
02139   /* Restore hirda->RxState to Ready */
02140   hirda->RxState = HAL_IRDA_STATE_READY;
02141
02142   /* Call user Abort complete callback */
02143   HAL_IRDA_AbortReceiveCpltCallback(hirda);
02144 }
02145
02146 /**
02147   * @brief  Send an amount of data in non-blocking mode.
02148   * @note   Function is called under interruption only, once
02149   *         interruptions have been enabled by HAL_IRDA_Transmit_IT().
02150   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
02151   *                the configuration information for the specified IRDA module.
02152   * @retval HAL status
02153   */
02154 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
02155 {
02156   uint16_t* tmp;
02157
02158   /* Check that a Tx process is ongoing */
02159   if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
02160   {
02161     if(hirda->TxXferCount == 0)
02162     {
02163       /* Disable the IRDA Transmit Data Register Empty Interrupt */
02164       CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
02165
02166       /* Enable the IRDA Transmit Complete Interrupt */
02167       SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
02168
02169       return HAL_OK;
02170     }
02171     else
02172     {
02173       if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
02174       {
02175         tmp = (uint16_t*) hirda->pTxBuffPtr;
02176         hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
02177         hirda->pTxBuffPtr += 2;
02178       }
02179       else
02180       {
02181         hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF);
02182       }
02183       hirda->TxXferCount--;
02184
02185       return HAL_OK;
02186     }
02187   }
02188   else
02189   {
02190     return HAL_BUSY;
02191   }
02192 }
02193
02194 /**
02195   * @brief  Wrap up transmission in non-blocking mode.
02196   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
02197   *                the configuration information for the specified IRDA module.
02198   * @retval HAL status
02199   */
02200 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
02201 {
02202   /* Disable the IRDA Transmit Complete Interrupt */
02203   CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
02204
02205   /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
02206   __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
02207
02208   /* Tx process is ended, restore hirda->gState to Ready */
02209   hirda->gState = HAL_IRDA_STATE_READY;
02210
02211   HAL_IRDA_TxCpltCallback(hirda);
02212
02213   return HAL_OK;
02214 }
02215
02216
02217 /**
02218   * @brief Receive an amount of data in non-blocking mode.
02219   *         Function is called under interruption only, once
02220   *         interruptions have been enabled by HAL_IRDA_Receive_IT().
02221   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
02222   *                the configuration information for the specified IRDA module.
02223   * @retval HAL status
02224   */
02225 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
02226 {
02227   uint16_t* tmp;
02228   uint16_t uhMask = hirda->Mask;
02229
02230   /* Check that a Rx process is ongoing */
02231   if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
02232   {
02233
02234     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
02235     {
02236       tmp = (uint16_t*) hirda->pRxBuffPtr ;
02237       *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
02238       hirda->pRxBuffPtr  +=2;
02239     }
02240     else
02241     {
02242       *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
02243     }
02244
02245     if(--hirda->RxXferCount == 0)
02246     {
02247       /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
02248       CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
02249
02250       /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
02251       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
02252
02253       /* Rx process is completed, restore hirda->RxState to Ready */
02254       hirda->RxState = HAL_IRDA_STATE_READY;
02255
02256       HAL_IRDA_RxCpltCallback(hirda);
02257
02258       return HAL_OK;
02259     }
02260
02261     return HAL_OK;
02262   }
02263   else
02264   {
02265     /* Clear RXNE interrupt flag */
02266     __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
02267
02268     return HAL_BUSY;
02269   }
02270 }
02271
02272 /**
02273   * @}
02274   */
02275
02276 #endif /* HAL_IRDA_MODULE_ENABLED */
02277 /**
02278   * @}
02279   */
02280
02281 /**
02282   * @}
02283   */
02284
02285 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_irda.h Source File

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stm32h7xx_hal_irda.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_irda.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of IRDA HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_IRDA_H
00040 #define __STM32H7xx_HAL_IRDA_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup IRDA
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup IRDA_Exported_Types IRDA Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief IRDA Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
00068                                            The baud rate register is computed using the following formula:
00069                                               Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */
00070
00071   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00072                                            This parameter can be a value of @ref IRDA_Word_Length */
00073
00074   uint32_t Parity;                    /*!< Specifies the parity mode.
00075                                            This parameter can be a value of @ref IRDA_Parity
00076                                            @note When parity is enabled, the computed parity is inserted
00077                                                  at the MSB position of the transmitted data (9th bit when
00078                                                  the word length is set to 9 data bits; 8th bit when the
00079                                                  word length is set to 8 data bits). */
00080
00081   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00082                                            This parameter can be a value of @ref IRDA_Transfer_Mode */
00083
00084   uint8_t  Prescaler;                 /*!< Specifies the Prescaler value for dividing the UART/USART source clock
00085                                            to achieve low-power frequency.
00086                                            @note Prescaler value 0 is forbidden */
00087
00088   uint16_t PowerMode;                 /*!< Specifies the IRDA power mode.
00089                                            This parameter can be a value of @ref IRDA_Low_Power */
00090 }IRDA_InitTypeDef;
00091
00092 /**
00093   * @brief HAL IRDA State structures definition
00094   * @note  HAL IRDA State value is a combination of 2 different substates: gState and RxState.
00095   *        - gState contains IRDA state information related to global Handle management
00096   *          and also information related to Tx operations.
00097   *          gState value coding follow below described bitmap :
00098   *          b7-b6  Error information
00099   *             00 : No Error
00100   *             01 : (Not Used)
00101   *             10 : Timeout
00102   *             11 : Error
00103   *          b5     IP initilisation status
00104   *             0  : Reset (IP not initialized)
00105   *             1  : Init done (IP not initialized. HAL IRDA Init function already called)
00106   *          b4-b3  (not used)
00107   *             xx : Should be set to 00
00108   *          b2     Intrinsic process state
00109   *             0  : Ready
00110   *             1  : Busy (IP busy with some configuration or internal operations)
00111   *          b1     (not used)
00112   *             x  : Should be set to 0
00113   *          b0     Tx state
00114   *             0  : Ready (no Tx operation ongoing)
00115   *             1  : Busy (Tx operation ongoing)
00116   *        - RxState contains information related to Rx operations.
00117   *          RxState value coding follow below described bitmap :
00118   *          b7-b6  (not used)
00119   *             xx : Should be set to 00
00120   *          b5     IP initilisation status
00121   *             0  : Reset (IP not initialized)
00122   *             1  : Init done (IP not initialized)
00123   *          b4-b2  (not used)
00124   *            xxx : Should be set to 000
00125   *          b1     Rx state
00126   *             0  : Ready (no Rx operation ongoing)
00127   *             1  : Busy (Rx operation ongoing)
00128   *          b0     (not used)
00129   *             x  : Should be set to 0.
00130   */
00131 typedef enum
00132 {
00133   HAL_IRDA_STATE_RESET             = 0x00U,   /*!< Peripheral is not initialized
00134                                                    Value is allowed for gState and RxState */
00135   HAL_IRDA_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use
00136                                                    Value is allowed for gState and RxState */
00137   HAL_IRDA_STATE_BUSY              = 0x24U,   /*!< an internal process is ongoing
00138                                                    Value is allowed for gState only */
00139   HAL_IRDA_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing
00140                                                    Value is allowed for gState only */
00141   HAL_IRDA_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing
00142                                                    Value is allowed for RxState only */
00143   HAL_IRDA_STATE_BUSY_TX_RX        = 0x23U,   /*!< Data Transmission and Reception process is ongoing
00144                                                    Not to be used for neither gState nor RxState.
00145                                                    Value is result of combination (Or) between gState and RxState values */
00146   HAL_IRDA_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state
00147                                                    Value is allowed for gState only */
00148   HAL_IRDA_STATE_ERROR             = 0xE0U    /*!< Error
00149                                                    Value is allowed for gState only */
00150 }HAL_IRDA_StateTypeDef;
00151
00152 /**
00153   * @brief  HAL IRDA Error Code structure definition
00154   */
00155 typedef enum
00156 {
00157   HAL_IRDA_ERROR_NONE      = 0x00,    /*!< No error            */
00158   HAL_IRDA_ERROR_PE        = 0x01,    /*!< Parity error        */
00159   HAL_IRDA_ERROR_NE        = 0x02,    /*!< Noise error         */
00160   HAL_IRDA_ERROR_FE        = 0x04,    /*!< frame error         */
00161   HAL_IRDA_ERROR_ORE       = 0x08,    /*!< Overrun error       */
00162   HAL_IRDA_ERROR_DMA       = 0x10,    /*!< DMA transfer error  */
00163   HAL_IRDA_ERROR_BUSY      = 0x20     /*!< Busy Error          */
00164 }HAL_IRDA_ErrorTypeDef;
00165
00166 /**
00167   * @brief IRDA clock sources definition
00168   */
00169 typedef enum
00170 {
00171   IRDA_CLOCKSOURCE_D2PCLK1    = 0x00,    /*!< Domain2 PCLK1 clock source */
00172   IRDA_CLOCKSOURCE_D2PCLK2    = 0x01,    /*!< Domain2 PCLK2 clock source */
00173   IRDA_CLOCKSOURCE_D3PCLK1    = 0x02,    /*!< Domain3 PCLK1 clock source */
00174   IRDA_CLOCKSOURCE_PLL2Q      = 0x04,    /*!< PLL2Q clock source         */
00175   IRDA_CLOCKSOURCE_HSI        = 0x08,    /*!< HSI clock source           */
00176   IRDA_CLOCKSOURCE_CSI        = 0x10,    /*!< CSI clock source           */
00177   IRDA_CLOCKSOURCE_LSE        = 0x20,    /*!< LSE clock source           */
00178   IRDA_CLOCKSOURCE_PLL3Q      = 0x40,    /*!< PCLK2 clock source         */
00179   IRDA_CLOCKSOURCE_UNDEFINED  = 0x80     /*!< Undefined clock source     */
00180 }IRDA_ClockSourceTypeDef;
00181
00182 /**
00183   * @brief  IRDA handle Structure definition
00184   */
00185 typedef struct
00186 {
00187   USART_TypeDef            *Instance;        /*!< IRDA registers base address        */
00188
00189   IRDA_InitTypeDef         Init;             /*!< IRDA communication parameters      */
00190
00191   uint8_t                  *pTxBuffPtr;      /*!< Pointer to IRDA Tx transfer Buffer */
00192
00193   uint16_t                 TxXferSize;       /*!< IRDA Tx Transfer size              */
00194
00195   __IO uint16_t            TxXferCount;      /*!< IRDA Tx Transfer Counter           */
00196
00197   uint8_t                  *pRxBuffPtr;      /*!< Pointer to IRDA Rx transfer Buffer */
00198
00199   uint16_t                 RxXferSize;       /*!< IRDA Rx Transfer size              */
00200
00201   __IO uint16_t            RxXferCount;      /*!< IRDA Rx Transfer Counter           */
00202
00203   uint16_t                 Mask;             /*!< IRDA RX RDR register mask          */
00204
00205   DMA_HandleTypeDef        *hdmatx;          /*!< IRDA Tx DMA Handle parameters      */
00206
00207   DMA_HandleTypeDef        *hdmarx;          /*!< IRDA Rx DMA Handle parameters      */
00208
00209   HAL_LockTypeDef          Lock;             /*!< Locking object                     */
00210
00211   __IO HAL_IRDA_StateTypeDef    gState;      /*!< IRDA state information related to global Handle management
00212                                                   and also related to Tx operations.
00213                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
00214
00215   __IO HAL_IRDA_StateTypeDef    RxState;     /*!< IRDA state information related to Rx operations.
00216                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
00217
00218   uint32_t                 ErrorCode;        /*!< IRDA Error code                    */
00219
00220 }IRDA_HandleTypeDef;
00221
00222 /**
00223   * @brief  IRDA Configuration enumeration values definition
00224   */
00225 typedef enum
00226 {
00227   IRDA_BAUDRATE        = 0x00,     /*!< IRDA Baud rate          */
00228   IRDA_PARITY          = 0x01,     /*!< IRDA frame parity       */
00229   IRDA_WORDLENGTH      = 0x02,     /*!< IRDA frame length       */
00230   IRDA_MODE            = 0x03,     /*!< IRDA communication mode */
00231   IRDA_PRESCALER       = 0x04,     /*!< IRDA prescaling         */
00232   IRDA_POWERMODE       = 0x05      /*!< IRDA power mode         */
00233 }IRDA_ControlTypeDef;
00234
00235 /**
00236   * @}
00237   */
00238
00239 /* Exported constants --------------------------------------------------------*/
00240 /** @defgroup IRDA_Exported_Constants IRDA Exported Constants
00241   * @{
00242   */
00243
00244 /** @defgroup IRDA_Word_Length IRDA Word Length
00245   * @{
00246   */
00247 #define IRDA_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M1)   /*!< 7-bit long frame */
00248 #define IRDA_WORDLENGTH_8B                  ((uint32_t)0x00000000)     /*!< 8-bit long frame */
00249 #define IRDA_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M0)   /*!< 9-bit long frame */
00250 /**
00251   * @}
00252   */
00253
00254 /** @defgroup IRDA_Parity IRDA Parity
00255   * @{
00256   */
00257 #define IRDA_PARITY_NONE                    ((uint32_t)0x00000000)                      /*!< No parity   */
00258 #define IRDA_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)                   /*!< Even parity */
00259 #define IRDA_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))  /*!< Odd parity  */
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
00265   * @{
00266   */
00267 #define IRDA_MODE_RX                        ((uint32_t)USART_CR1_RE)                   /*!< RX mode        */
00268 #define IRDA_MODE_TX                        ((uint32_t)USART_CR1_TE)                   /*!< TX mode        */
00269 #define IRDA_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))   /*!< RX and TX mode */
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup IRDA_Low_Power IRDA Low Power
00275   * @{
00276   */
00277 #define IRDA_POWERMODE_NORMAL               ((uint32_t)0x00000000)       /*!< IRDA normal power mode */
00278 #define IRDA_POWERMODE_LOWPOWER             ((uint32_t)USART_CR3_IRLP)   /*!< IRDA low power mode    */
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup IRDA_State IRDA State
00284   * @{
00285   */
00286 #define IRDA_STATE_DISABLE                  ((uint32_t)0x00000000)     /*!< IRDA disabled  */
00287 #define IRDA_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)   /*!< IRDA enabled   */
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup IRDA_Mode  IRDA Mode
00293   * @{
00294   */
00295 #define IRDA_MODE_DISABLE                   ((uint32_t)0x00000000)      /*!< Associated UART disabled in IRDA mode */
00296 #define IRDA_MODE_ENABLE                    ((uint32_t)USART_CR3_IREN)  /*!< Associated UART enabled in IRDA mode  */
00297 /**
00298   * @}
00299   */
00300
00301 /** @defgroup IRDA_One_Bit  IRDA One Bit Sampling
00302   * @{
00303   */
00304 #define IRDA_ONE_BIT_SAMPLE_DISABLE         ((uint32_t)0x00000000)       /*!< One-bit sampling disabled */
00305 #define IRDA_ONE_BIT_SAMPLE_ENABLE          ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enabled  */
00306 /**
00307   * @}
00308   */
00309
00310 /** @defgroup IRDA_DMA_Tx IRDA DMA Tx
00311   * @{
00312   */
00313 #define IRDA_DMA_TX_DISABLE                 ((uint32_t)0x00000000)       /*!< IRDA DMA TX disabled */
00314 #define IRDA_DMA_TX_ENABLE                  ((uint32_t)USART_CR3_DMAT)   /*!< IRDA DMA TX enabled  */
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup IRDA_DMA_Rx  IRDA DMA Rx
00320   * @{
00321   */
00322 #define IRDA_DMA_RX_DISABLE                 ((uint32_t)0x00000000)       /*!< IRDA DMA RX disabled */
00323 #define IRDA_DMA_RX_ENABLE                  ((uint32_t)USART_CR3_DMAR)   /*!< IRDA DMA RX enabled  */
00324 /**
00325   * @}
00326   */
00327
00328 /** @defgroup IRDA_Request_Parameters IRDA Request Parameters
00329   * @{
00330   */
00331 #define IRDA_AUTOBAUD_REQUEST            ((uint16_t)USART_RQR_ABRRQ)        /*!< Auto-Baud Rate Request      */
00332 #define IRDA_RXDATA_FLUSH_REQUEST        ((uint16_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request  */
00333 #define IRDA_TXDATA_FLUSH_REQUEST        ((uint16_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */
00334 /**
00335   * @}
00336   */
00337
00338 /** @defgroup IRDA_Flags IRDA Flags
00339   *        Elements values convention: 0xXXXX
00340   *           - 0xXXXX  : Flag mask in the ISR register
00341   * @{
00342   */
00343 #define IRDA_FLAG_REACK                     ((uint32_t)0x00400000)    /*!< IRDA Receive enable acknowledge flag  */
00344 #define IRDA_FLAG_TEACK                     ((uint32_t)0x00200000)    /*!< IRDA Transmit enable acknowledge flag */
00345 #define IRDA_FLAG_BUSY                      ((uint32_t)0x00010000)    /*!< IRDA Busy flag                        */
00346 #define IRDA_FLAG_ABRF                      ((uint32_t)0x00008000)    /*!< IRDA Auto baud rate flag              */
00347 #define IRDA_FLAG_ABRE                      ((uint32_t)0x00004000)    /*!< IRDA Auto baud rate error             */
00348 #define IRDA_FLAG_TXE                       ((uint32_t)0x00000080)    /*!< IRDA Transmit data register empty     */
00349 #define IRDA_FLAG_TC                        ((uint32_t)0x00000040)    /*!< IRDA Transmission complete            */
00350 #define IRDA_FLAG_RXNE                      ((uint32_t)0x00000020)    /*!< IRDA Read data register not empty     */
00351 #define IRDA_FLAG_ORE                       ((uint32_t)0x00000008)    /*!< IRDA Overrun error                    */
00352 #define IRDA_FLAG_NE                        ((uint32_t)0x00000004)    /*!< IRDA Noise error                      */
00353 #define IRDA_FLAG_FE                        ((uint32_t)0x00000002)    /*!< IRDA Framing error                    */
00354 #define IRDA_FLAG_PE                        ((uint32_t)0x00000001)    /*!< IRDA Parity error                     */
00355 /**
00356   * @}
00357   */
00358
00359 /** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
00360   *        Elements values convention: 0000ZZZZ0XXYYYYYb
00361   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00362   *           - XX  : Interrupt source register (2bits)
00363   *                 - 01: CR1 register
00364   *                 - 10: CR2 register
00365   *                 - 11: CR3 register
00366   *           - ZZZZ  : Flag position in the ISR register(4bits)
00367   * @{
00368   */
00369 #define IRDA_IT_PE                          ((uint16_t)0x0028)      /*!< IRDA Parity error interruption                 */
00370 #define IRDA_IT_TXE                         ((uint16_t)0x0727)      /*!< IRDA Transmit data register empty interruption */
00371 #define IRDA_IT_TC                          ((uint16_t)0x0626)      /*!< IRDA Transmission complete interruption        */
00372 #define IRDA_IT_RXNE                        ((uint16_t)0x0525)      /*!< IRDA Read data register not empty interruption */
00373 #define IRDA_IT_IDLE                        ((uint16_t)0x0424)      /*!< IRDA Idle interruption                         */
00374 #define IRDA_IT_ERR                         ((uint16_t)0x0060)      /*!< IRDA Error interruption                        */
00375 #define IRDA_IT_ORE                         ((uint16_t)0x0300)      /*!< IRDA Overrun error interruption                */
00376 #define IRDA_IT_NE                          ((uint16_t)0x0200)      /*!< IRDA Noise error interruption                  */
00377 #define IRDA_IT_FE                          ((uint16_t)0x0100)      /*!< IRDA Frame error interruption                  */
00378 /**
00379   * @}
00380   */
00381
00382 /** @defgroup IRDA_IT_CLEAR_Flags   IRDA Interruption Clear Flags
00383   * @{
00384   */
00385 #define IRDA_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag          */
00386 #define IRDA_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag         */
00387 #define IRDA_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag        */
00388 #define IRDA_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag         */
00389 #define IRDA_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag    */
00390 #define IRDA_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
00391 /**
00392   * @}
00393   */
00394
00395 /** @defgroup IRDA_Interruption_Mask    IRDA interruptions flags mask
00396   * @{
00397   */
00398 #define IRDA_IT_MASK  ((uint16_t)0x001F)                             /*!< IRDA Interruptions flags mask */
00399 /**
00400   * @}
00401   */
00402
00403 /**
00404  * @}
00405  */
00406
00407
00408 /* Exported macros -----------------------------------------------------------*/
00409 /** @defgroup IRDA_Exported_Macros IRDA Exported Macros
00410   * @{
00411   */
00412
00413 /** @brief  Reset IRDA handle state.
00414   * @param  __HANDLE__: IRDA handle.
00415   * @retval None
00416   */
00417 #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00418                                                        (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
00419                                                        (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
00420                                                      } while(0)
00421
00422 /** @brief  Flush the IRDA DR register.
00423   * @param  __HANDLE__: specifies the IRDA Handle.
00424   * @retval None
00425   */
00426 #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)                            \
00427     do{                                                                    \
00428          SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
00429          SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
00430       } while(0)
00431
00432 /** @brief  Clear the specified IRDA pending flag.
00433   * @param  __HANDLE__: specifies the IRDA Handle.
00434   * @param  __FLAG__: specifies the flag to check.
00435   *          This parameter can be any combination of the following values:
00436   *            @arg @ref IRDA_CLEAR_PEF
00437   *            @arg @ref IRDA_CLEAR_FEF
00438   *            @arg @ref IRDA_CLEAR_NEF
00439   *            @arg @ref IRDA_CLEAR_OREF
00440   *            @arg @ref IRDA_CLEAR_TCF
00441   *            @arg @ref IRDA_CLEAR_IDLEF
00442   * @retval None
00443   */
00444 #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00445
00446 /** @brief  Clear the IRDA PE pending flag.
00447   * @param  __HANDLE__: specifies the IRDA Handle.
00448   * @retval None
00449   */
00450 #define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
00451
00452
00453 /** @brief  Clear the IRDA FE pending flag.
00454   * @param  __HANDLE__: specifies the IRDA Handle.
00455   * @retval None
00456   */
00457 #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
00458
00459 /** @brief  Clear the IRDA NE pending flag.
00460   * @param  __HANDLE__: specifies the IRDA Handle.
00461   * @retval None
00462   */
00463 #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
00464
00465 /** @brief  Clear the IRDA ORE pending flag.
00466   * @param  __HANDLE__: specifies the IRDA Handle.
00467   * @retval None
00468   */
00469 #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
00470
00471 /** @brief  Clear the IRDA IDLE pending flag.
00472   * @param  __HANDLE__: specifies the IRDA Handle.
00473   * @retval None
00474   */
00475 #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
00476
00477 /** @brief  Check whether the specified IRDA flag is set or not.
00478   * @param  __HANDLE__: specifies the IRDA Handle.
00479   * @param  __FLAG__: specifies the flag to check.
00480   *        This parameter can be one of the following values:
00481   *            @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
00482   *            @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
00483   *            @arg @ref IRDA_FLAG_BUSY  Busy flag
00484   *            @arg @ref IRDA_FLAG_ABRF  Auto Baud rate detection flag
00485   *            @arg @ref IRDA_FLAG_ABRE  Auto Baud rate detection error flag
00486   *            @arg @ref IRDA_FLAG_TXE   Transmit data register empty flag
00487   *            @arg @ref IRDA_FLAG_TC    Transmission Complete flag
00488   *            @arg @ref IRDA_FLAG_RXNE  Receive data register not empty flag
00489   *            @arg @ref IRDA_FLAG_ORE   OverRun Error flag
00490   *            @arg @ref IRDA_FLAG_NE    Noise Error flag
00491   *            @arg @ref IRDA_FLAG_FE    Framing Error flag
00492   *            @arg @ref IRDA_FLAG_PE    Parity Error flag
00493   * @retval The new state of __FLAG__ (TRUE or FALSE).
00494   */
00495 #define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00496
00497
00498 /** @brief  Enable the specified IRDA interrupt.
00499   * @param  __HANDLE__: specifies the IRDA Handle.
00500   * @param  __INTERRUPT__: specifies the IRDA interrupt source to enable.
00501   *          This parameter can be one of the following values:
00502   *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
00503   *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
00504   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00505   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00506   *            @arg @ref IRDA_IT_PE   Parity Error interrupt
00507   *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
00508   * @retval None
00509   */
00510 #define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00511                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00512                                                            ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
00513
00514 /** @brief  Disable the specified IRDA interrupt.
00515   * @param  __HANDLE__: specifies the IRDA Handle.
00516   * @param  __INTERRUPT__: specifies the IRDA interrupt source to disable.
00517   *          This parameter can be one of the following values:
00518   *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
00519   *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
00520   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00521   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00522   *            @arg @ref IRDA_IT_PE   Parity Error interrupt
00523   *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
00524   * @retval None
00525   */
00526 #define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00527                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00528                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
00529
00530
00531 /** @brief  Check whether the specified IRDA interrupt has occurred or not.
00532   * @param  __HANDLE__: specifies the IRDA Handle.
00533   * @param  __IT__: specifies the IRDA interrupt source to check.
00534   *          This parameter can be one of the following values:
00535   *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
00536   *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
00537   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00538   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00539   *            @arg @ref IRDA_IT_ORE OverRun Error interrupt
00540   *            @arg @ref IRDA_IT_NE Noise Error interrupt
00541   *            @arg @ref IRDA_IT_FE Framing Error interrupt
00542   *            @arg @ref IRDA_IT_PE Parity Error interrupt
00543   * @retval The new state of __IT__ (TRUE or FALSE).
00544   */
00545 #define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08)))
00546
00547 /** @brief  Check whether the specified IRDA interrupt source is enabled or not.
00548   * @param  __HANDLE__: specifies the IRDA Handle.
00549   * @param  __IT__: specifies the IRDA interrupt source to check.
00550   *          This parameter can be one of the following values:
00551   *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
00552   *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
00553   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00554   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00555   *            @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
00556   *            @arg @ref IRDA_IT_PE Parity Error interrupt
00557   * @retval The new state of __IT__ (TRUE or FALSE).
00558   */
00559 #define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
00560                                                        (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
00561
00562
00563 /** @brief  Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
00564   * @param  __HANDLE__: specifies the IRDA Handle.
00565   * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
00566   *                       to clear the corresponding interrupt
00567   *          This parameter can be one of the following values:
00568   *            @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
00569   *            @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
00570   *            @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
00571   *            @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
00572   *            @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
00573   * @retval None
00574   */
00575 #define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
00576
00577
00578 /** @brief  Set a specific IRDA request flag.
00579   * @param  __HANDLE__: specifies the IRDA Handle.
00580   * @param  __REQ__: specifies the request flag to set
00581   *          This parameter can be one of the following values:
00582   *            @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
00583   *            @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
00584   *            @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
00585   *
00586   * @retval None
00587   */
00588 #define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
00589
00590 /** @brief  Enable the IRDA one bit sample method.
00591   * @param  __HANDLE__: specifies the IRDA Handle.
00592   * @retval None
00593   */
00594 #define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00595
00596 /** @brief  Disable the IRDA one bit sample method.
00597   * @param  __HANDLE__: specifies the IRDA Handle.
00598   * @retval None
00599   */
00600 #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
00601
00602 /** @brief  Enable UART/USART associated to IRDA Handle.
00603   * @param  __HANDLE__: specifies the IRDA Handle.
00604   * @retval None
00605   */
00606 #define __HAL_IRDA_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00607
00608 /** @brief  Disable UART/USART associated to IRDA Handle.
00609   * @param  __HANDLE__: specifies the IRDA Handle.
00610   * @retval None
00611   */
00612 #define __HAL_IRDA_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00613
00614 /**
00615   * @}
00616   */
00617
00618 /* Private macros --------------------------------------------------------*/
00619 /** @defgroup IRDA_Private_Macros   IRDA Private Macros
00620   * @{
00621   */
00622
00623 /** @brief  Compute the mask to apply to retrieve the received data
00624   *         according to the word length and to the parity bits activation.
00625   * @param  __HANDLE__: specifies the IRDA Handle.
00626   * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
00627   */
00628 #define IRDA_MASK_COMPUTATION(__HANDLE__)                             \
00629   do {                                                                \
00630   if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B)            \
00631   {                                                                   \
00632      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
00633      {                                                                \
00634         (__HANDLE__)->Mask = 0x01FF ;                                 \
00635      }                                                                \
00636      else                                                             \
00637      {                                                                \
00638         (__HANDLE__)->Mask = 0x00FF ;                                 \
00639      }                                                                \
00640   }                                                                   \
00641   else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B)       \
00642   {                                                                   \
00643      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
00644      {                                                                \
00645         (__HANDLE__)->Mask = 0x00FF ;                                 \
00646      }                                                                \
00647      else                                                             \
00648      {                                                                \
00649         (__HANDLE__)->Mask = 0x007F ;                                 \
00650      }                                                                \
00651   }                                                                   \
00652   else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B)       \
00653   {                                                                   \
00654      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
00655      {                                                                \
00656         (__HANDLE__)->Mask = 0x007F ;                                 \
00657      }                                                                \
00658      else                                                             \
00659      {                                                                \
00660         (__HANDLE__)->Mask = 0x003F ;                                 \
00661      }                                                                \
00662   }                                                                   \
00663 } while(0)
00664
00665 /** @brief  Ensure that IRDA Baud rate is less or equal to maximum value.
00666   * @param  __BAUDRATE__: specifies the IRDA Baudrate set by the user.
00667   * @retval True or False
00668   */
00669 #define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
00670
00671 /** @brief  Ensure that IRDA prescaler value is strictly larger than 0.
00672   * @param  __PRESCALER__: specifies the IRDA prescaler value set by the user.
00673   * @retval True or False
00674   */
00675 #define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
00676
00677 /**
00678   * @brief Ensure that IRDA frame length is valid.
00679   * @param __LENGTH__: IRDA frame length.
00680   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00681   */
00682 #define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
00683                                          ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
00684                                          ((__LENGTH__) == IRDA_WORDLENGTH_9B))
00685
00686 /**
00687   * @brief Ensure that IRDA frame parity is valid.
00688   * @param __PARITY__: IRDA frame parity.
00689   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
00690   */
00691 #define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
00692                                     ((__PARITY__) == IRDA_PARITY_EVEN) || \
00693                                     ((__PARITY__) == IRDA_PARITY_ODD))
00694
00695 /**
00696   * @brief Ensure that IRDA communication mode is valid.
00697   * @param __MODE__: IRDA communication mode.
00698   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00699   */
00700 #define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
00701
00702 /**
00703   * @brief Ensure that IRDA power mode is valid.
00704   * @param __MODE__: IRDA power mode.
00705   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00706   */
00707 #define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
00708                                      ((__MODE__) == IRDA_POWERMODE_NORMAL))
00709
00710 /**
00711   * @brief Ensure that IRDA state is valid.
00712   * @param __STATE__: IRDA state mode.
00713   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00714   */
00715 #define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
00716                                   ((__STATE__) == IRDA_STATE_ENABLE))
00717
00718 /**
00719   * @brief Ensure that IRDA associated UART/USART mode is valid.
00720   * @param __MODE__: IRDA associated UART/USART mode.
00721   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00722   */
00723 #define IS_IRDA_MODE(__MODE__)  (((__MODE__) == IRDA_MODE_DISABLE) || \
00724                                  ((__MODE__) == IRDA_MODE_ENABLE))
00725
00726 /**
00727   * @brief Ensure that IRDA sampling rate is valid.
00728   * @param __ONEBIT__: IRDA sampling rate.
00729   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
00730   */
00731 #define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)      (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
00732                                                  ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
00733
00734 /**
00735   * @brief Ensure that IRDA DMA TX mode is valid.
00736   * @param __DMATX__: IRDA DMA TX mode.
00737   * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
00738   */
00739 #define IS_IRDA_DMA_TX(__DMATX__)     (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
00740                                        ((__DMATX__) == IRDA_DMA_TX_ENABLE))
00741
00742 /**
00743   * @brief Ensure that IRDA DMA RX mode is valid.
00744   * @param __DMARX__: IRDA DMA RX mode.
00745   * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
00746   */
00747 #define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
00748                                    ((__DMARX__) == IRDA_DMA_RX_ENABLE))
00749
00750 /**
00751   * @brief Ensure that IRDA request is valid.
00752   * @param __PARAM__: IRDA request.
00753   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
00754   */
00755 #define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
00756                                               ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
00757                                               ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
00758 /**
00759  * @}
00760  */
00761
00762 /* Include IRDA HAL Extended module */
00763 #include "stm32h7xx_hal_irda_ex.h"
00764
00765 /* Exported functions --------------------------------------------------------*/
00766 /** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
00767   * @{
00768   */
00769
00770 /** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
00771   * @{
00772   */
00773
00774 /* Initialization and de-initialization functions  ****************************/
00775 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
00776 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
00777 void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
00778 void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
00779
00780 /**
00781   * @}
00782   */
00783
00784 /** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
00785   * @{
00786   */
00787
00788 /* IO operation functions *****************************************************/
00789 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00790 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00791 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00792 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00793 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00794 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00795 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
00796 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
00797 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
00798 HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
00799 HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
00800 HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
00801 HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
00802 HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
00803 HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
00804 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
00805 void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
00806 void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
00807 void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
00808 void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
00809 void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
00810 void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda);
00811 void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda);
00812 void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda);
00813
00814 /**
00815   * @}
00816   */
00817
00818 /* Peripheral Control functions  ************************************************/
00819
00820 /** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
00821   * @{
00822   */
00823
00824 /* Peripheral State and Error functions ***************************************/
00825 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
00826 uint32_t              HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
00827
00828 /**
00829   * @}
00830   */
00831
00832 /**
00833   * @}
00834   */
00835
00836 /**
00837   * @}
00838   */
00839
00840 /**
00841   * @}
00842   */
00843
00844 #ifdef __cplusplus
00845 }
00846 #endif
00847
00848 #endif /* __STM32H7xx_HAL_IRDA_H */
00849
00850 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_irda_ex.h Source File

  • File List
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  • Drivers
  • STM32H7xx_HAL_Driver
  • Inc
stm32h7xx_hal_irda_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_irda_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of IRDA HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_IRDA_EX_H
00040 #define __STM32H7xx_HAL_IRDA_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup IRDAEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059 /* Exported macros -----------------------------------------------------------*/
00060 /* Exported functions --------------------------------------------------------*/
00061
00062 /* Private macros ------------------------------------------------------------*/
00063
00064 /** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
00065   * @{
00066   */
00067
00068 /** @brief  Report the IRDA clock source.
00069   * @param  __HANDLE__: specifies the IRDA Handle.
00070   * @param  __CLOCKSOURCE__: output variable.
00071   * @retval IRDA clocking source, written in __CLOCKSOURCE__.
00072   */
00073 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00074   do {                                                        \
00075     if((__HANDLE__)->Instance == USART1)                      \
00076     {                                                         \
00077        switch(__HAL_RCC_GET_USART1_SOURCE())                  \
00078        {                                                      \
00079         case RCC_USART1CLKSOURCE_D2PCLK2:                     \
00080           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2;       \
00081           break;                                              \
00082         case RCC_USART1CLKSOURCE_PLL2:                       \
00083           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00084           break;                                              \
00085         case RCC_USART1CLKSOURCE_PLL3:                       \
00086           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00087           break;                                              \
00088         case RCC_USART1CLKSOURCE_HSI:                         \
00089           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00090           break;                                              \
00091         case RCC_USART1CLKSOURCE_CSI:                         \
00092           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00093           break;                                              \
00094         case RCC_USART1CLKSOURCE_LSE:                         \
00095           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00096           break;                                              \
00097        }                                                      \
00098     }                                                         \
00099     else if((__HANDLE__)->Instance == USART2)                 \
00100     {                                                         \
00101        switch(__HAL_RCC_GET_USART2_SOURCE())                  \
00102        {                                                      \
00103         case RCC_USART2CLKSOURCE_D2PCLK1:                     \
00104           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
00105           break;                                              \
00106         case RCC_USART2CLKSOURCE_PLL2:                       \
00107           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00108           break;                                              \
00109         case RCC_USART2CLKSOURCE_PLL3:                       \
00110           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00111           break;                                              \
00112         case RCC_USART2CLKSOURCE_HSI:                         \
00113           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00114           break;                                              \
00115         case RCC_USART2CLKSOURCE_CSI:                         \
00116           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00117           break;                                              \
00118         case RCC_USART2CLKSOURCE_LSE:                         \
00119           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00120           break;                                              \
00121        }                                                      \
00122     }                                                         \
00123     else if((__HANDLE__)->Instance == USART3)                 \
00124     {                                                         \
00125        switch(__HAL_RCC_GET_USART3_SOURCE())                  \
00126        {                                                      \
00127         case RCC_USART3CLKSOURCE_D2PCLK1:                     \
00128           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
00129           break;                                              \
00130         case RCC_USART3CLKSOURCE_PLL2:                       \
00131           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00132           break;                                              \
00133         case RCC_USART3CLKSOURCE_PLL3:                       \
00134           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00135           break;                                              \
00136         case RCC_USART3CLKSOURCE_HSI:                         \
00137           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00138           break;                                              \
00139         case RCC_USART3CLKSOURCE_CSI:                         \
00140           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00141           break;                                              \
00142         case RCC_USART3CLKSOURCE_LSE:                         \
00143           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00144           break;                                              \
00145        }                                                      \
00146     }                                                         \
00147     else if((__HANDLE__)->Instance == UART4)                  \
00148     {                                                         \
00149        switch(__HAL_RCC_GET_UART4_SOURCE())                   \
00150        {                                                      \
00151         case RCC_UART4CLKSOURCE_D2PCLK1:                      \
00152           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
00153           break;                                              \
00154         case RCC_UART4CLKSOURCE_PLL2:                        \
00155           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00156           break;                                              \
00157         case RCC_UART4CLKSOURCE_PLL3:                        \
00158           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00159           break;                                              \
00160         case RCC_UART4CLKSOURCE_HSI:                          \
00161           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00162           break;                                              \
00163         case RCC_UART4CLKSOURCE_CSI:                          \
00164           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00165           break;                                              \
00166         case RCC_UART4CLKSOURCE_LSE:                          \
00167           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00168           break;                                              \
00169        }                                                      \
00170     }                                                         \
00171     else if ((__HANDLE__)->Instance == UART5)                 \
00172     {                                                         \
00173        switch(__HAL_RCC_GET_UART5_SOURCE())                   \
00174        {                                                      \
00175         case RCC_UART5CLKSOURCE_D2PCLK1:                      \
00176           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
00177           break;                                              \
00178         case RCC_UART5CLKSOURCE_PLL2:                        \
00179           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00180           break;                                              \
00181         case RCC_UART5CLKSOURCE_PLL3:                        \
00182           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00183           break;                                              \
00184         case RCC_UART5CLKSOURCE_HSI:                          \
00185           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00186           break;                                              \
00187         case RCC_UART5CLKSOURCE_CSI:                          \
00188           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00189           break;                                              \
00190         case RCC_UART5CLKSOURCE_LSE:                          \
00191           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00192           break;                                              \
00193        }                                                      \
00194     }                                                         \
00195     else if((__HANDLE__)->Instance == USART6)                 \
00196     {                                                         \
00197        switch(__HAL_RCC_GET_USART6_SOURCE())                  \
00198        {                                                      \
00199         case RCC_USART6CLKSOURCE_D2PCLK2:                     \
00200           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2;       \
00201           break;                                              \
00202         case RCC_USART6CLKSOURCE_PLL2:                       \
00203           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00204           break;                                              \
00205         case RCC_USART6CLKSOURCE_PLL3:                       \
00206           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00207           break;                                              \
00208         case RCC_USART6CLKSOURCE_HSI:                         \
00209           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00210           break;                                              \
00211         case RCC_USART6CLKSOURCE_CSI:                         \
00212           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00213           break;                                              \
00214         case RCC_USART6CLKSOURCE_LSE:                         \
00215           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00216           break;                                              \
00217        }                                                      \
00218     }                                                         \
00219     else if((__HANDLE__)->Instance == UART7)                  \
00220     {                                                         \
00221        switch(__HAL_RCC_GET_UART7_SOURCE())                   \
00222        {                                                      \
00223         case RCC_UART7CLKSOURCE_D2PCLK1:                      \
00224           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
00225           break;                                              \
00226         case RCC_UART7CLKSOURCE_PLL2:                        \
00227           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00228           break;                                              \
00229         case RCC_UART7CLKSOURCE_PLL3:                        \
00230           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00231           break;                                              \
00232         case RCC_UART7CLKSOURCE_HSI:                          \
00233           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00234           break;                                              \
00235         case RCC_UART7CLKSOURCE_CSI:                          \
00236           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00237           break;                                              \
00238         case RCC_UART7CLKSOURCE_LSE:                          \
00239           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00240           break;                                              \
00241        }                                                      \
00242     }                                                         \
00243     else if((__HANDLE__)->Instance == UART8)                 \
00244     {                                                         \
00245        switch(__HAL_RCC_GET_UART8_SOURCE())                   \
00246        {                                                      \
00247         case RCC_UART8CLKSOURCE_D2PCLK1:                      \
00248           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
00249           break;                                              \
00250         case RCC_UART8CLKSOURCE_PLL2:                        \
00251           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
00252           break;                                              \
00253         case RCC_UART8CLKSOURCE_PLL3:                        \
00254           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
00255           break;                                              \
00256         case RCC_UART8CLKSOURCE_HSI:                          \
00257           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00258           break;                                              \
00259         case RCC_UART8CLKSOURCE_CSI:                          \
00260           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
00261           break;                                              \
00262         case RCC_UART8CLKSOURCE_LSE:                          \
00263           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00264           break;                                              \
00265        }                                                      \
00266     }                                                         \
00267   } while(0)
00268
00269 /**
00270   * @}
00271   */
00272
00273 /* Exported functions --------------------------------------------------------*/
00274
00275 /**
00276   * @}
00277   */
00278
00279 /**
00280   * @}
00281   */
00282
00283 #ifdef __cplusplus
00284 }
00285 #endif
00286
00287 #endif /* __STM32H7xx_HAL_IRDA_EX_H */
00288
00289 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_iwdg.c Source File

  • File List
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  • STM32H7xx_HAL_Driver
  • Src
stm32h7xx_hal_iwdg.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_iwdg.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   IWDG HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Independent Watchdog (IWDG) peripheral:
00010   *           + Initialization and Start functions
00011   *           + IO operation functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                     ##### IWDG Generic features #####
00016   ==============================================================================
00017   [..]
00018     (+) The IWDG can be started by either software or hardware (configurable
00019         through option byte).
00020
00021     (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
00022         if the main clock fails.
00023
00024     (+) Once the IWDG is started, the LSI is forced ON and both can not be
00025         disabled. The counter starts counting down from the reset value (0xFFF).
00026         When it reaches the end of count value (0x000) a reset signal is
00027         generated (IWDG reset).
00028
00029     (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
00030         the IWDG_RLR value is reloaded in the counter and the watchdog reset is
00031         prevented.
00032
00033     (+) The IWDG is implemented in the VDD voltage domain that is still functional
00034         in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
00035         IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
00036         reset occurs.
00037
00038     (+) Debug mode : When the microcontroller enters debug mode (core halted),
00039         the IWDG counter either continues to work normally or stops, depending
00040         on DBG_IWDG_STOP configuration bit in DBG module, accessible through
00041         __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
00042
00043     [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
00044          The IWDG timeout may vary due to LSI frequency dispersion. STM32H7xx
00045          devices provide the capability to measure the LSI frequency (LSI clock
00046          connected internally to TIM16 CH1 input capture). The measured value
00047          can be used to have an IWDG timeout with an acceptable accuracy.
00048
00049                      ##### How to use this driver #####
00050   ==============================================================================
00051   [..]
00052     (#) Use IWDG using HAL_IWDG_Init() function to :
00053       (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
00054            clock is forced ON and IWDG counter starts downcounting.
00055       (++) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
00056            IWDG_WINR.
00057       (++) Configure the IWDG prescaler and counter reload value. This reload
00058            value will be loaded in the IWDG counter each time the watchdog is
00059            reloaded, then the IWDG will start counting down from this value.
00060       (++) Wait for status flags to be reset
00061       (++) Depending on window parameter:
00062          (+++) If Window Init parameter is same as Window register value,
00063                nothing more is done but reload counter value in order to exit
00064                function withy exact time base.
00065          (+++) Else modify Window register. This will automatically reload
00066                watchdog counter.
00067
00068     (#) Then the application program must refresh the IWDG counter at regular
00069         intervals during normal operation to prevent an MCU reset, using
00070         HAL_IWDG_Refresh() function.
00071
00072      *** IWDG HAL driver macros list ***
00073      ====================================
00074      [..]
00075        Below the list of most used macros in IWDG HAL driver:
00076       (+) __HAL_IWDG_START: Enable the IWDG peripheral
00077       (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
00078           the reload register
00079
00080   @endverbatim
00081   ******************************************************************************
00082   * @attention
00083   *
00084   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00085   *
00086   * Redistribution and use in source and binary forms, with or without modification,
00087   * are permitted provided that the following conditions are met:
00088   *   1. Redistributions of source code must retain the above copyright notice,
00089   *      this list of conditions and the following disclaimer.
00090   *   2. Redistributions in binary form must reproduce the above copyright notice,
00091   *      this list of conditions and the following disclaimer in the documentation
00092   *      and/or other materials provided with the distribution.
00093   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00094   *      may be used to endorse or promote products derived from this software
00095   *      without specific prior written permission.
00096   *
00097   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00098   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00099   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00100   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00101   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00102   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00103   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00104   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00105   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00106   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00107   *
00108   ******************************************************************************
00109   */
00110
00111 /* Includes ------------------------------------------------------------------*/
00112 #include "stm32h7xx_hal.h"
00113
00114 /** @addtogroup STM32H7xx_HAL_Driver
00115   * @{
00116   */
00117
00118 #ifdef HAL_IWDG_MODULE_ENABLED
00119 /** @addtogroup IWDG
00120   * @brief IWDG HAL module driver.
00121   * @{
00122   */
00123
00124 /* Private typedef -----------------------------------------------------------*/
00125 /* Private define ------------------------------------------------------------*/
00126 /** @defgroup IWDG_Private_Defines IWDG Private Defines
00127   * @{
00128   */
00129 /* Status register need 5 RC LSI divided by prescaler clock to be updated. With
00130    higher prescaler (256), and according to LSI variation, we need to wait at
00131    least 6 cycles so 48 ms. */
00132 #define HAL_IWDG_DEFAULT_TIMEOUT            48u
00133 /**
00134   * @}
00135   */
00136
00137 /* Private macro -------------------------------------------------------------*/
00138 /* Private variables ---------------------------------------------------------*/
00139 /* Private function prototypes -----------------------------------------------*/
00140 /* Exported functions --------------------------------------------------------*/
00141
00142 /** @addtogroup IWDG_Exported_Functions
00143   * @{
00144   */
00145
00146 /** @addtogroup IWDG_Exported_Functions_Group1
00147  *  @brief    Initialization and Start functions.
00148  *
00149 @verbatim
00150  ===============================================================================
00151           ##### Initialization and Start functions #####
00152  ===============================================================================
00153  [..]  This section provides functions allowing to:
00154       (+) Initialize the IWDG according to the specified parameters in the
00155           IWDG_InitTypeDef of associated handle.
00156       (+) Manage Window option.
00157       (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
00158           is reloaded in order to exit function with correct time base.
00159
00160 @endverbatim
00161   * @{
00162   */
00163
00164 /**
00165   * @brief  Initialize the IWDG according to the specified parameters in the
00166   *         IWDG_InitTypeDef and start watchdog. Before exiting function,
00167   *         watchdog is refreshed in order to have correct time base.
00168   * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
00169   *                the configuration information for the specified IWDG module.
00170   * @retval HAL status
00171   */
00172 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
00173 {
00174   uint32_t tickstart;
00175
00176   /* Check the IWDG handle allocation */
00177   if(hiwdg == NULL)
00178   {
00179     return HAL_ERROR;
00180   }
00181
00182   /* Check the parameters */
00183   assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
00184   assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
00185   assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
00186   assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
00187
00188   /* Enable IWDG. LSI is turned on automaticaly */
00189   __HAL_IWDG_START(hiwdg);
00190
00191   /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
00192   0x5555 in KR */
00193   IWDG_ENABLE_WRITE_ACCESS(hiwdg);
00194
00195   /* Write to IWDG registers the Prescaler & Reload values to work with */
00196   hiwdg->Instance->PR = hiwdg->Init.Prescaler;
00197   hiwdg->Instance->RLR = hiwdg->Init.Reload;
00198
00199   /* Check pending flag, if previous update not done, return timeout */
00200   tickstart = HAL_GetTick();
00201
00202    /* Wait for register to be updated */
00203   while(hiwdg->Instance->SR != RESET)
00204   {
00205     if((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
00206     {
00207       return HAL_TIMEOUT;
00208     }
00209   }
00210
00211   /* If window parameter is different than current value, modify window
00212   register */
00213   if(hiwdg->Instance->WINR != hiwdg->Init.Window)
00214   {
00215     /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
00216     even if window feature is disabled, Watchdog will be reloaded by writing
00217     windows register */
00218     hiwdg->Instance->WINR = hiwdg->Init.Window;
00219   }
00220   else
00221   {
00222     /* Reload IWDG counter with value defined in the reload register */
00223     __HAL_IWDG_RELOAD_COUNTER(hiwdg);
00224   }
00225
00226   /* Return function status */
00227   return HAL_OK;
00228 }
00229
00230 /**
00231   * @}
00232   */
00233
00234
00235 /** @addtogroup IWDG_Exported_Functions_Group2
00236  *  @brief   IO operation functions
00237  *
00238 @verbatim
00239  ===============================================================================
00240                       ##### IO operation functions #####
00241  ===============================================================================
00242  [..]  This section provides functions allowing to:
00243       (+) Refresh the IWDG.
00244
00245 @endverbatim
00246   * @{
00247   */
00248
00249
00250 /**
00251   * @brief  Refresh the IWDG.
00252   * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
00253   *                the configuration information for the specified IWDG module.
00254   * @retval HAL status
00255   */
00256 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
00257 {
00258   /* Reload IWDG counter with value defined in the reload register */
00259   __HAL_IWDG_RELOAD_COUNTER(hiwdg);
00260
00261   /* Return function status */
00262   return HAL_OK;
00263 }
00264
00265 /**
00266   * @}
00267   */
00268
00269 /**
00270   * @}
00271   */
00272
00273 #endif /* HAL_IWDG_MODULE_ENABLED */
00274 /**
00275   * @}
00276   */
00277
00278 /**
00279   * @}
00280   */
00281
00282 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_iwdg.h Source File

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stm32h7xx_hal_iwdg.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_iwdg.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of IWDG HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_IWDG_H
00040 #define __STM32H7xx_HAL_IWDG_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup IWDG IWDG
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup IWDG_Exported_Types IWDG Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  IWDG Init structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.
00068                             This parameter can be a value of @ref IWDG_Prescaler */
00069
00070   uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.
00071                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
00072
00073   uint32_t Window;     /*!< Specifies the window value to be compared to the down-counter.
00074                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
00075
00076 } IWDG_InitTypeDef;
00077
00078 /**
00079   * @brief  IWDG Handle Structure definition
00080   */
00081 typedef struct
00082 {
00083   IWDG_TypeDef                 *Instance;  /*!< Register base address    */
00084
00085   IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
00086
00087 }IWDG_HandleTypeDef;
00088
00089 /**
00090   * @}
00091   */
00092
00093 /* Exported constants --------------------------------------------------------*/
00094 /** @defgroup IWDG_Exported_Constants IWDG Exported Constants
00095   * @{
00096   */
00097
00098 /** @defgroup IWDG_Prescaler IWDG Prescaler
00099   * @{
00100   */
00101 #define IWDG_PRESCALER_4                0x00000000u                   /*!< IWDG prescaler set to 4   */
00102 #define IWDG_PRESCALER_8                IWDG_PR_PR_0                  /*!< IWDG prescaler set to 8   */
00103 #define IWDG_PRESCALER_16               IWDG_PR_PR_1                  /*!< IWDG prescaler set to 16  */
00104 #define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32  */
00105 #define IWDG_PRESCALER_64               IWDG_PR_PR_2                  /*!< IWDG prescaler set to 64  */
00106 #define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
00107 #define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
00108 /**
00109   * @}
00110   */
00111
00112 /** @defgroup IWDG_Window_option IWDG Window option
00113   * @{
00114   */
00115 #define IWDG_WINDOW_DISABLE             IWDG_WINR_WIN
00116 /**
00117   * @}
00118   */
00119
00120 /**
00121   * @}
00122   */
00123
00124 /* Exported macros -----------------------------------------------------------*/
00125 /** @defgroup IWDG_Exported_Macros IWDG Exported Macros
00126   * @{
00127   */
00128
00129 /**
00130   * @brief  Enable the IWDG peripheral.
00131   * @param  __HANDLE__: IWDG handle
00132   * @retval None
00133   */
00134 #define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
00135
00136 /**
00137   * @brief  Reload IWDG counter with value defined in the reload register
00138   *         (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
00139   * @param  __HANDLE__:  IWDG handle
00140   * @retval None
00141   */
00142 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
00143
00144 /**
00145   * @}
00146   */
00147
00148 /* Exported functions --------------------------------------------------------*/
00149 /** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
00150   * @{
00151   */
00152
00153 /** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
00154   * @{
00155   */
00156 /* Initialization/Start functions  ********************************************/
00157 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
00163   * @{
00164   */
00165 /* I/O operation functions ****************************************************/
00166 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
00167 /**
00168   * @}
00169   */
00170
00171 /**
00172   * @}
00173   */
00174
00175 /* Private constants ---------------------------------------------------------*/
00176 /** @defgroup IWDG_Private_Constants IWDG Private Constants
00177   * @{
00178   */
00179
00180 /**
00181   * @brief  IWDG Key Register BitMask
00182   */
00183 #define IWDG_KEY_RELOAD                 0x0000AAAAu  /*!< IWDG Reload Counter Enable   */
00184 #define IWDG_KEY_ENABLE                 0x0000CCCCu  /*!< IWDG Peripheral Enable       */
00185 #define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555u  /*!< IWDG KR Write Access Enable  */
00186 #define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000u  /*!< IWDG KR Write Access Disable */
00187
00188 /**
00189   * @}
00190   */
00191
00192 /* Private macros ------------------------------------------------------------*/
00193 /** @defgroup IWDG_Private_Macros IWDG Private Macros
00194   * @{
00195   */
00196
00197 /**
00198   * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
00199   * @param  __HANDLE__: IWDG handle
00200   * @retval None
00201   */
00202 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
00203
00204 /**
00205   * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
00206   * @param  __HANDLE__: IWDG handle
00207   * @retval None
00208   */
00209 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
00210
00211 /**
00212   * @brief  Check IWDG prescaler value.
00213   * @param  __PRESCALER__: IWDG prescaler value
00214   * @retval None
00215   */
00216 #define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
00217                                                ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
00218                                                ((__PRESCALER__) == IWDG_PRESCALER_16) || \
00219                                                ((__PRESCALER__) == IWDG_PRESCALER_32) || \
00220                                                ((__PRESCALER__) == IWDG_PRESCALER_64) || \
00221                                                ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
00222                                                ((__PRESCALER__) == IWDG_PRESCALER_256))
00223
00224 /**
00225   * @brief  Check IWDG reload value.
00226   * @param  __RELOAD__: IWDG reload value
00227   * @retval None
00228   */
00229 #define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)
00230
00231 /**
00232   * @brief  Check IWDG window value.
00233   * @param  __WINDOW__: IWDG window value
00234   * @retval None
00235   */
00236 #define IS_IWDG_WINDOW(__WINDOW__)            ((__WINDOW__) <= IWDG_WINR_WIN)
00237
00238 /**
00239   * @}
00240   */
00241
00242 /**
00243   * @}
00244   */
00245
00246 /**
00247   * @}
00248   */
00249
00250
00251 #ifdef __cplusplus
00252 }
00253 #endif
00254
00255 #endif /* __STM32H7xx_HAL_IWDG_H */
00256
00257 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_jpeg.c Source File

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stm32h7xx_hal_jpeg.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_jpeg.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   JPEG HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the JPEG encoder/decoder peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + JPEG processing functions encoding and decoding
00012   *           + JPEG decoding Getting Info and encoding configuration setting
00013   *           + JPEG enable/disable header parsing functions (for decoding)
00014   *           + JPEG Input/Output Buffer configuration.
00015   *           + JPEG callback functions
00016   *           + JPEG Abort/Pause/Resume functions
00017   *           + JPEG custom quantization tables setting functions
00018   *           + IRQ handler management
00019   *           + Peripheral State and Error functions
00020   *
00021   @verbatim
00022   ==============================================================================
00023                      ##### How to use this driver #####
00024   ==============================================================================
00025     [..]
00026      (#) Initialize the JPEG peripheral using HAL_JPEG_Init : No initialization parameters are required.
00027          Only the call to HAL_JPEG_Init is necessary to initialize the JPEG peripheral.
00028
00029      (#) If operation is JPEG encoding use function HAL_JPEG_ConfigEncoding to set
00030          the encoding parameters (mandatory before calling the encoding function).
00031          the application can change the encoding parameter "ImageQuality" from
00032          1 to 100 to obtain a more or less quality (visual quality vs the original row image),
00033          and inversely more or less jpg file size.
00034
00035      (#) Note that for decoding operation the JPEG peripheral output data are organized in
00036          YCbCr blocks called MCU (Minimum Coded Unit) as defioned in the JPEG specification
00037          ISO/IEC 10918-1 standard.
00038          It is up to the application to transform these YCbCr blocks to RGB data that can be display.
00039
00040          Respectively, for Encoding operation the JPEG peripheral input should be organized
00041          in YCbCr MCU blocks. It is up to the application to perform the necessary RGB to YCbCr
00042          MCU blocks transformation before feeding the JPEG peripheral with data.
00043
00044      (#) Use functions HAL_JPEG_Encode and HAL_JPEG_Decode to start respectively
00045          a JPEG encoding/decoding operation in polling method (blocking).
00046
00047      (#) Use functions HAL_JPEG_Encode_IT and HAL_JPEG_Decode_IT to start respectively
00048          a JPEG encoding/decoding operation with Interrupt method (not blocking).
00049
00050      (#) Use functions HAL_JPEG_Encode_DMA and HAL_JPEG_Decode_DMA to start respectively
00051          a JPEG encoding/decoding operation with DMA method (not blocking).
00052
00053      (#) Callback HAL_JPEG_InfoReadyCallback is asserted if the current operation
00054          is a JPEG decoding to provide the application with JPEG image  parameters.
00055          This callback is asserted when the JPEG peripheral successfully parse the
00056          JPEG header.
00057
00058      (#) Callback HAL_JPEG_GetDataCallback is asserted for both encoding and decoding
00059          operations to inform the application that the input buffer has been
00060          consumed by the peripheral and to ask for a new data chunk if the operation
00061          (encoding/decoding) has not been complete yet.
00062
00063         (++) This CallBack should be implemented in the application side. It should
00064              call the function HAL_JPEG_ConfigInputBuffer if new input data are available,
00065              or call HAL_JPEG_Pause with parameter XferSelection set to JPEG_PAUSE_RESUME_INPUT
00066              to inform the JPEG HAL driver that the ongoing operation shall pause waiting for the
00067              application to provide a new input data chunk.
00068              Once the application succeed getting new data and if the input has been paused,
00069              the application can call the function HAL_JPEG_ConfigInputBuffer to set the new
00070              input buffer and size, then resume the JPEG HAL input by calling new function HAL_JPEG_Resume.
00071              If the application has ended feeding the HAL JPEG with input data (no more input data), the application
00072              Should call the function HAL_JPEG_ConfigInputBuffer (within the callback HAL_JPEG_GetDataCallback)
00073              with the parameter InDataLength set to zero.
00074
00075          (++) The mechanism of HAL_JPEG_ConfigInputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows
00076               to the application to provide the input data (for encoding or decoding) by chunks.
00077               If the new input data chunk is not available (because data should be read from an input file
00078               for example) the application can pause the JPEG input (using function HAL_JPEG_Pause)
00079               Once the new input data chunk is available ( read from a file for example), the application
00080               can call the function HAL_JPEG_ConfigInputBuffer to provide the HAL with the new chunk
00081               then resume the JPEG HAL input by calling function HAL_JPEG_Resume.
00082
00083          (++) The application can call functions HAL_JPEG_ConfigInputBuffer then HAL_JPEG_Resume.
00084               any time (outside the HAL_JPEG_GetDataCallback)  Once the new input chunk data available.
00085               However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called
00086               (if necessary) within the callback HAL_JPEG_GetDataCallback, i.e when the HAL JPEG has ended
00087               Transferring the previous chunk buffer to the JPEG peripheral.
00088
00089      (#) Callback HAL_JPEG_DataReadyCallback is asserted when the HAL JPEG driver
00090          has filled the given output buffer with the given size.
00091
00092          (++) This CallBack should be implemented in the application side. It should
00093               call the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver
00094               with the new output buffer location and size to be used  to store next data chunk.
00095               if the application is not ready to provide the output chunk location then it can
00096               call the function HAL_JPEG_Pause with parameter XferSelection set to "JPEG_PAUSE_RESUME_OUTPUT"
00097               to inform the JPEG HAL driver that it shall pause output data. Once the application
00098               is ready to receive the new data chunk (output buffer location free or available) it should call
00099               the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver
00100               with the new output chunk buffer location and size, then call "HAL_JPEG_Resume"
00101               to inform the HAL that it shall resume outputting data in the given output buffer.
00102
00103          (++) The mechanism of HAL_JPEG_ConfigOutputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows
00104               the application to receive data from the JPEG peripheral by chunks. when a chunk
00105               is received, the application can pause the HAL JPEG output data to be able to process
00106               these received data (YCbCr to RGB conversion in case of decoding or data storage in case
00107               of encoding).
00108
00109          (++) The application can call  functions HAL_JPEG_ ConfigOutputBuffer then HAL_JPEG_Resume.
00110               any time (outside the HAL_JPEG_DataReadyCallback) Once the output data buffer is free to use.
00111               However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called
00112               (if necessary) within the callback HAL_JPEG_ DataReadyCallback, i.e when the HAL JPEG has ended
00113               Transferring the previous chunk buffer from the JPEG peripheral to the application.
00114
00115      (#) Callback HAL_JPEG_EncodeCpltCallback is asserted when the HAL JPEG driver has
00116          ended the current JPEG encoding operation, and all output data has been transmitted
00117          to the application.
00118
00119      (#) Callback HAL_JPEG_DecodeCpltCallback is asserted when the HAL JPEG driver has
00120          ended the current JPEG decoding operation. and all output data has been transmitted
00121          to the application.
00122
00123      (#) Callback HAL_JPEG_ErrorCallback is asserted when an error occurred during
00124          the current operation. the application can call the function "HAL_JPEG_GetError"
00125          to retrieve the error codes.
00126
00127      (#) By default the HAL JPEG driver uses the default quantization tables
00128          as provide in the JPEG specification (ISO/IEC 10918-1 standard) for encoding.
00129          User can change these default tables if necessary using the function HAL_JPEG_SetUserQuantTables
00130          Note that for decoding the quantization tables are automatically extracted from
00131          the JPEG header.
00132
00133       (#) To control JPEG state you can use the following function: HAL_JPEG_GetState()
00134
00135      *** JPEG HAL driver macros list ***
00136      =============================================
00137      [..]
00138        Below the list of most used macros in JPEG HAL driver.
00139
00140       (+) __HAL_JPEG_RESET_HANDLE_STATE : Reset JPEG handle state.
00141       (+) __HAL_JPEG_ENABLE             : Enable the JPEG peripheral.
00142       (+) __HAL_JPEG_DISABLE            : Disable the JPEG peripheral.
00143       (+) __HAL_JPEG_GET_FLAG           : Check the specified JPEG status flag.
00144       (+) __HAL_JPEG_CLEAR_FLAG         : Clear the specified JPEG status flag.
00145       (+) __HAL_JPEG_ENABLE_IT          : Enable the specified JPEG Interrupt.
00146       (+) __HAL_JPEG_DISABLE_IT         : Disable the specified JPEG Interrupt.
00147       (+) __HAL_JPEG_GET_IT_SOURCE      : returns the state of the specified JPEG Interrupt (Enabled or disabled).
00148
00149
00150   @endverbatim
00151   ******************************************************************************
00152   * @attention
00153   *
00154   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00155   *
00156   * Redistribution and use in source and binary forms, with or without modification,
00157   * are permitted provided that the following conditions are met:
00158   *   1. Redistributions of source code must retain the above copyright notice,
00159   *      this list of conditions and the following disclaimer.
00160   *   2. Redistributions in binary form must reproduce the above copyright notice,
00161   *      this list of conditions and the following disclaimer in the documentation
00162   *      and/or other materials provided with the distribution.
00163   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00164   *      may be used to endorse or promote products derived from this software
00165   *      without specific prior written permission.
00166   *
00167   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00168   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00169   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00170   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00171   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00172   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00173   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00174   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00175   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00176   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00177   *
00178   ******************************************************************************
00179   */
00180
00181 /* Includes ------------------------------------------------------------------*/
00182 #include "stm32h7xx_hal.h"
00183
00184 /** @addtogroup STM32H7xx_HAL_Driver
00185   * @{
00186   */
00187
00188 /** @defgroup JPEG JPEG
00189   * @brief JPEG HAL module driver.
00190   * @{
00191   */
00192
00193 #ifdef HAL_JPEG_MODULE_ENABLED
00194
00195 /* Private define ------------------------------------------------------------*/
00196 /** @addtogroup JPEG_Private_Constants
00197   * @{
00198   */
00199 #define JPEG_TIMEOUT_VALUE  ((uint32_t)1000U)     /* 1s */
00200 #define JPEG_AC_HUFF_TABLE_SIZE  ((uint32_t)162U) /* Huffman AC table size : 162 codes*/
00201 #define JPEG_DC_HUFF_TABLE_SIZE  ((uint32_t)12U)  /* Huffman AC table size : 12 codes*/
00202
00203 #define JPEG_FIFO_SIZE    ((uint32_t)16U)             /* JPEG Input/Output HW FIFO size in words*/
00204 #define JPEG_FIFO_TH_SIZE ((uint32_t)8U)              /* JPEG Input/Output HW FIFO Threshold in words*/
00205
00206 #define JPEG_INTERRUPT_MASK  ((uint32_t)0x0000007EU) /* JPEG Interrupt Mask*/
00207
00208 #define JPEG_CONTEXT_ENCODE          ((uint32_t)0x00000001U) /* JPEG context : operation is encoding*/
00209 #define JPEG_CONTEXT_DECODE          ((uint32_t)0x00000002U) /* JPEG context : operation is decoding*/
00210 #define JPEG_CONTEXT_OPERATION_MASK  ((uint32_t)0x00000003U) /* JPEG context : operation Mask */
00211
00212 #define JPEG_CONTEXT_POLLING        ((uint32_t)0x00000004U)  /* JPEG context : Transfer use Polling */
00213 #define JPEG_CONTEXT_IT             ((uint32_t)0x00000008U)  /* JPEG context : Transfer use Interrupt */
00214 #define JPEG_CONTEXT_DMA            ((uint32_t)0x0000000CU)  /* JPEG context : Transfer use DMA */
00215 #define JPEG_CONTEXT_METHOD_MASK    ((uint32_t)0x0000000CU)  /* JPEG context : Transfer Mask */
00216
00217
00218 #define JPEG_CONTEXT_CONF_ENCODING  ((uint32_t)0x00000100U)  /* JPEG context : encoding config done */
00219
00220 #define JPEG_CONTEXT_PAUSE_INPUT    ((uint32_t)0x00001000U)  /* JPEG context : Pause Input */
00221 #define JPEG_CONTEXT_PAUSE_OUTPUT   ((uint32_t)0x00002000U)  /* JPEG context : Pause Output */
00222
00223 #define JPEG_CONTEXT_CUSTOM_TABLES  ((uint32_t)0x00004000U)  /* JPEG context : Use custom quantization tables */
00224
00225 #define JPEG_CONTEXT_ENDING_DMA     ((uint32_t)0x00008000U)  /* JPEG context : ending with DMA in progress */
00226
00227 #define JPEG_PROCESS_ONGOING        ((uint32_t)0x00000000U)  /* Process is on going */
00228 #define JPEG_PROCESS_DONE           ((uint32_t)0x00000001U)  /* Process is done (ends) */
00229 /**
00230   * @}
00231   */
00232
00233 /* Private typedef -----------------------------------------------------------*/
00234 /** @addtogroup JPEG_Private_Types
00235   * @{
00236   */
00237
00238 /*
00239  JPEG Huffman Table Structure definition :
00240  This implementation of Huffman table structure is compliant with ISO/IEC 10918-1 standard , Annex C Huffman Table specification
00241  */
00242 typedef struct
00243 {
00244   /* These two fields directly represent the contents of a JPEG DHT marker */
00245   uint8_t Bits[16];        /*!< bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C */
00246
00247   uint8_t HuffVal[162];    /*!< The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C */
00248
00249
00250 }JPEG_ACHuffTableTypeDef;
00251
00252 typedef struct
00253 {
00254   /* These two fields directly represent the contents of a JPEG DHT marker */
00255   uint8_t Bits[16];        /*!< bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C */
00256
00257   uint8_t HuffVal[12];    /*!< The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C */
00258
00259
00260 }JPEG_DCHuffTableTypeDef;
00261
00262 typedef struct
00263 {
00264   uint8_t CodeLength[JPEG_AC_HUFF_TABLE_SIZE];      /*!< Code length  */
00265
00266   uint32_t HuffmanCode[JPEG_AC_HUFF_TABLE_SIZE];    /*!< HuffmanCode */
00267
00268 }JPEG_AC_HuffCodeTableTypeDef;
00269
00270 typedef struct
00271 {
00272   uint8_t CodeLength[JPEG_DC_HUFF_TABLE_SIZE];        /*!< Code length  */
00273
00274   uint32_t HuffmanCode[JPEG_DC_HUFF_TABLE_SIZE];    /*!< HuffmanCode */
00275
00276 }JPEG_DC_HuffCodeTableTypeDef;
00277 /**
00278   * @}
00279   */
00280
00281 /* Private macro -------------------------------------------------------------*/
00282 /* Private variables ---------------------------------------------------------*/
00283 /** @addtogroup JPEG_Private_Variables
00284   * @{
00285   */
00286
00287 static const JPEG_DCHuffTableTypeDef JPEG_DCLUM_HuffTable =
00288 {
00289   { 0, 1, 5, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },   /*Bits*/
00290
00291   { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb }           /*HUFFVAL */
00292
00293 };
00294
00295 static const JPEG_DCHuffTableTypeDef JPEG_DCCHROM_HuffTable =
00296 {
00297   { 0, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },  /*Bits*/
00298
00299   { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb }          /*HUFFVAL */
00300 };
00301
00302 static const JPEG_ACHuffTableTypeDef JPEG_ACLUM_HuffTable =
00303 {
00304   { 0, 2, 1, 3, 3, 2, 4, 3, 5, 5, 4, 4, 0, 0, 1, 0x7d },  /*Bits*/
00305
00306   {   0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12,     /*HUFFVAL */
00307       0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07,
00308       0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08,
00309       0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0,
00310       0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16,
00311       0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28,
00312       0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
00313       0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,
00314       0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59,
00315       0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69,
00316       0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79,
00317       0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89,
00318       0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98,
00319       0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
00320       0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6,
00321       0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5,
00322       0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4,
00323       0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2,
00324       0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea,
00325       0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
00326       0xf9, 0xfa }
00327 };
00328
00329 static const JPEG_ACHuffTableTypeDef JPEG_ACCHROM_HuffTable =
00330 {
00331   { 0, 2, 1, 2, 4, 4, 3, 4, 7, 5, 4, 4, 0, 1, 2, 0x77 },   /*Bits*/
00332
00333   {   0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21,      /*HUFFVAL */
00334       0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71,
00335       0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91,
00336       0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33, 0x52, 0xf0,
00337       0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24, 0x34,
00338       0xe1, 0x25, 0xf1, 0x17, 0x18, 0x19, 0x1a, 0x26,
00339       0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37, 0x38,
00340       0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48,
00341       0x49, 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,
00342       0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
00343       0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
00344       0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
00345       0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96,
00346       0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5,
00347       0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4,
00348       0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3,
00349       0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2,
00350       0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda,
00351       0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9,
00352       0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
00353       0xf9, 0xfa }
00354 };
00355
00356
00357 /*
00358   These are the sample quantization tables given in JPEG spec ISO/IEC 10918-1 standard , section K.1.
00359 */
00360 static const uint8_t JPEG_LUM_QuantTable[JPEG_QUANT_TABLE_SIZE] =
00361 {
00362   16,  11,  10,  16,  24,  40,  51,  61,
00363   12,  12,  14,  19,  26,  58,  60,  55,
00364   14,  13,  16,  24,  40,  57,  69,  56,
00365   14,  17,  22,  29,  51,  87,  80,  62,
00366   18,  22,  37,  56,  68, 109, 103,  77,
00367   24,  35,  55,  64,  81, 104, 113,  92,
00368   49,  64,  78,  87, 103, 121, 120, 101,
00369   72,  92,  95,  98, 112, 100, 103,  99
00370 };
00371 static const uint8_t JPEG_CHROM_QuantTable[JPEG_QUANT_TABLE_SIZE] =
00372 {
00373   17,  18,  24,  47,  99,  99,  99,  99,
00374   18,  21,  26,  66,  99,  99,  99,  99,
00375   24,  26,  56,  99,  99,  99,  99,  99,
00376   47,  66,  99,  99,  99,  99,  99,  99,
00377   99,  99,  99,  99,  99,  99,  99,  99,
00378   99,  99,  99,  99,  99,  99,  99,  99,
00379   99,  99,  99,  99,  99,  99,  99,  99,
00380   99,  99,  99,  99,  99,  99,  99,  99
00381 };
00382
00383 static const uint8_t JPEG_ZIGZAG_ORDER[JPEG_QUANT_TABLE_SIZE] =
00384 {
00385    0,   1,   8,  16,   9,   2,   3,  10,
00386   17,  24,  32,  25,  18,  11,   4,   5,
00387   12,  19,  26,  33,  40,  48,  41,  34,
00388   27,  20,  13,   6,   7,  14,  21,  28,
00389   35,  42,  49,  56,  57,  50,  43,  36,
00390   29,  22,  15,  23,  30,  37,  44,  51,
00391   58,  59,  52,  45,  38,  31,  39,  46,
00392   53,  60,  61,  54,  47,  55,  62,  63
00393 };
00394 /**
00395   * @}
00396   */
00397
00398 /* Private function prototypes -----------------------------------------------*/
00399 /** @addtogroup JPEG_Private_Functions_Prototypes
00400   * @{
00401   */
00402
00403 static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK);
00404 static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable);
00405 static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable);
00406 static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, __IO uint32_t *DCTableAddress);
00407 static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, __IO uint32_t *ACTableAddress);
00408 static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 ,  JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1);
00409 static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 ,  JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1);
00410 static HAL_StatusTypeDef  JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, __IO uint32_t *QTableAddress);
00411 static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg);
00412 static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg);
00413 static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg);
00414
00415 static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg);
00416 static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg);
00417 static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords);
00418 static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords);
00419 static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg);
00420
00421 static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg);
00422 static uint32_t JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg);
00423 static uint32_t JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg);
00424 static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg);
00425 static void JPEG_MDMAOutCpltCallback(MDMA_HandleTypeDef *hmdma);
00426 static void JPEG_MDMAInCpltCallback(MDMA_HandleTypeDef *hmdma);
00427 static void JPEG_MDMAErrorCallback(MDMA_HandleTypeDef *hmdma);
00428 static void JPEG_MDMAOutAbortCallback(MDMA_HandleTypeDef *hmdma);
00429 /**
00430   * @}
00431   */
00432
00433 /** @defgroup JPEG_Exported_Functions JPEG Exported Functions
00434   * @{
00435   */
00436
00437 /** @defgroup JPEG_Exported_Functions_Group1 Initialization and de-initialization functions
00438  *  @brief    Initialization and de-initialization functions.
00439  *
00440 @verbatim
00441   ==============================================================================
00442               ##### Initialization and de-initialization functions #####
00443   ==============================================================================
00444     [..]  This section provides functions allowing to:
00445       (+) Initialize the JPEG peripheral and creates the associated handle
00446       (+) DeInitialize the JPEG peripheral
00447
00448 @endverbatim
00449   * @{
00450   */
00451
00452 /**
00453   * @brief  Initializes the JPEG according to the specified
00454   *         parameters in the JPEG_InitTypeDef and creates the associated handle.
00455   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
00456   *         the configuration information for JPEG module
00457   * @retval HAL status
00458   */
00459 HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg)
00460 {
00461   /*Note : these intermediate variables are used to avoid MISRA warning
00462   regarding rule 11.5 */
00463   uint32_t acLum_huffmanTableAddr = (uint32_t)(&JPEG_ACLUM_HuffTable);
00464   uint32_t dcLum_huffmanTableAddr = (uint32_t)(&JPEG_DCLUM_HuffTable);
00465   uint32_t acChrom_huffmanTableAddr = (uint32_t)(&JPEG_ACCHROM_HuffTable);
00466   uint32_t dcChrom_huffmanTableAddr = (uint32_t)(&JPEG_DCCHROM_HuffTable);
00467
00468   /* Check the JPEG handle allocation */
00469   if(hjpeg == NULL)
00470   {
00471     return HAL_ERROR;
00472   }
00473
00474   if(hjpeg->State == HAL_JPEG_STATE_RESET)
00475   {
00476     /* Allocate lock resource and initialize it */
00477     hjpeg->Lock = HAL_UNLOCKED;
00478
00479     /* Init the low level hardware : GPIO, CLOCK */
00480     HAL_JPEG_MspInit(hjpeg);
00481   }
00482
00483   /* Change the JPEG state */
00484   hjpeg->State = HAL_JPEG_STATE_BUSY;
00485
00486   /* Start the JPEG Core*/
00487   __HAL_JPEG_ENABLE(hjpeg);
00488
00489   /* Stop the JPEG encoding/decoding process*/
00490   hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
00491
00492   /* Disable All Interrupts */
00493   __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
00494
00495   /* Flush input and output FIFOs*/
00496   hjpeg->Instance->CR |= JPEG_CR_IFF;
00497   hjpeg->Instance->CR |= JPEG_CR_OFF;
00498
00499   /* Clear all flags */
00500   __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);
00501
00502   /* init default quantization tables*/
00503   hjpeg->QuantTable0 = (uint8_t *)((uint32_t)JPEG_LUM_QuantTable);
00504   hjpeg->QuantTable1 = (uint8_t *)((uint32_t)JPEG_CHROM_QuantTable);
00505   hjpeg->QuantTable2 = NULL;
00506   hjpeg->QuantTable3 = NULL;
00507
00508   /* init the default Huffman tables*/
00509   if(JPEG_Set_HuffEnc_Mem(hjpeg, (JPEG_ACHuffTableTypeDef *)acLum_huffmanTableAddr, (JPEG_DCHuffTableTypeDef *)dcLum_huffmanTableAddr, (JPEG_ACHuffTableTypeDef *)acChrom_huffmanTableAddr, (JPEG_DCHuffTableTypeDef *)dcChrom_huffmanTableAddr) != HAL_OK)
00510   {
00511     hjpeg->ErrorCode = HAL_JPEG_ERROR_HUFF_TABLE;
00512
00513     return HAL_ERROR;
00514   }
00515
00516   /* Enable header processing*/
00517   hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR;
00518
00519   /* Reset JpegInCount and JpegOutCount */
00520   hjpeg->JpegInCount = 0;
00521   hjpeg->JpegOutCount = 0;
00522
00523   /* Change the JPEG state */
00524   hjpeg->State = HAL_JPEG_STATE_READY;
00525
00526   /* Reset the JPEG ErrorCode */
00527   hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE;
00528
00529   /*Clear the context filelds*/
00530   hjpeg->Context = 0;
00531
00532   /* Return function status */
00533   return HAL_OK;
00534 }
00535
00536 /**
00537   * @brief  DeInitializes the JPEG peripheral.
00538   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
00539   *         the configuration information for JPEG module
00540   * @retval HAL status
00541   */
00542 HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg)
00543 {
00544   /* Check the JPEG handle allocation */
00545   if(hjpeg == NULL)
00546   {
00547     return HAL_ERROR;
00548   }
00549
00550   /* DeInit the low level hardware: CLOCK, NVIC.*/
00551   HAL_JPEG_MspDeInit(hjpeg);
00552
00553   /* Change the JPEG state */
00554   hjpeg->State = HAL_JPEG_STATE_BUSY;
00555
00556   /* Reset the JPEG ErrorCode */
00557   hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE;
00558
00559   /* Reset JpegInCount and JpegOutCount */
00560   hjpeg->JpegInCount = 0;
00561   hjpeg->JpegOutCount = 0;
00562
00563   /* Change the JPEG state */
00564   hjpeg->State = HAL_JPEG_STATE_RESET;
00565
00566   /*Clear the context fields*/
00567   hjpeg->Context = 0;
00568
00569   /* Release Lock */
00570   __HAL_UNLOCK(hjpeg);
00571
00572   /* Return function status */
00573   return HAL_OK;
00574 }
00575
00576 /**
00577   * @brief  Initializes the JPEG MSP.
00578   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
00579   *         the configuration information for JPEG module
00580   * @retval None
00581   */
00582 __weak void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg)
00583 {
00584   /* Prevent unused argument(s) compilation warning */
00585   UNUSED(hjpeg);
00586
00587   /* NOTE : This function Should not be modified, when the callback is needed,
00588             the HAL_JPEG_MspInit could be implemented in the user file
00589    */
00590 }
00591
00592 /**
00593   * @brief  DeInitializes JPEG MSP.
00594   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
00595   *         the configuration information for JPEG module
00596   * @retval None
00597   */
00598 __weak void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg)
00599 {
00600   /* Prevent unused argument(s) compilation warning */
00601   UNUSED(hjpeg);
00602
00603   /* NOTE : This function Should not be modified, when the callback is needed,
00604             the HAL_JPEG_MspDeInit could be implemented in the user file
00605    */
00606 }
00607
00608 /**
00609   * @}
00610   */
00611
00612 /** @defgroup JPEG_Exported_Functions_Group2 Configuration functions
00613  *  @brief    JPEG Configuration functions.
00614  *
00615 @verbatim
00616   ==============================================================================
00617               ##### Configuration functions #####
00618   ==============================================================================
00619     [..]  This section provides functions allowing to:
00620       (+) HAL_JPEG_ConfigEncoding() : JPEG encoding configuration
00621       (+) HAL_JPEG_GetInfo() :  Extract the image configuration from the JPEG header during the decoding
00622       (+) HAL_JPEG_EnableHeaderParsing() :  Enable JPEG Header parsing for decoding
00623       (+) HAL_JPEG_DisableHeaderParsing() : Disable JPEG Header parsing for decoding
00624       (+) HAL_JPEG_SetUserQuantTables : Modify the default Quantization tables used for JPEG encoding.
00625
00626 @endverbatim
00627   * @{
00628   */
00629
00630 /**
00631   * @brief  Set the JPEG encoding configuration.
00632   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
00633   *         the configuration information for JPEG module
00634   * @param  pConf: pointer to a JPEG_ConfTypeDef structure that contains
00635   *         the encoding configuration
00636   * @retval HAL status
00637   */
00638 HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf)
00639 {
00640   uint32_t error = HAL_OK;
00641   uint32_t numberMCU, hfactor, vfactor,hMCU, vMCU;
00642
00643   /* Check the JPEG handle allocation */
00644   if( (hjpeg == NULL) || (pConf == NULL) )
00645   {
00646     return HAL_ERROR;
00647   }
00648   else
00649   {
00650     /* Check the parameters */
00651     assert_param(IS_JPEG_COLORSPACE(pConf->ColorSpace));
00652     assert_param(IS_JPEG_CHROMASUBSAMPLING(pConf->ChromaSubsampling));
00653     assert_param(IS_JPEG_IMAGE_QUALITY(pConf->ImageQuality));
00654
00655     /* Process Locked */
00656     __HAL_LOCK(hjpeg);
00657
00658     if(hjpeg->State == HAL_JPEG_STATE_READY)
00659     {
00660       hjpeg->State = HAL_JPEG_STATE_BUSY;
00661
00662       hjpeg->Conf.ColorSpace          =  pConf->ColorSpace;
00663       hjpeg->Conf.ChromaSubsampling   =  pConf->ChromaSubsampling;
00664       hjpeg->Conf.ImageHeight         =  pConf->ImageHeight;
00665       hjpeg->Conf.ImageWidth          =  pConf->ImageWidth;
00666       hjpeg->Conf.ImageQuality        =  pConf->ImageQuality;
00667
00668       /* Reset the Color Space : by default only one quantization table is used*/
00669       hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_COLORSPACE;
00670
00671       /* Set Number of color components*/
00672       if(hjpeg->Conf.ColorSpace == JPEG_GRAYSCALE_COLORSPACE)
00673       {
00674         /*Gray Scale is only one component 8x8 blocks i.e 4:4:4*/
00675         hjpeg->Conf.ChromaSubsampling = JPEG_444_SUBSAMPLING;
00676
00677         JPEG_SetColorGrayScale(hjpeg);
00678         /* Set quantization table 0*/
00679         error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0));
00680       }
00681       else if(hjpeg->Conf.ColorSpace == JPEG_YCBCR_COLORSPACE)
00682       {
00683         /*
00684            Set the Color Space for YCbCr : 2 quantization tables are used
00685            one for Luminance(Y) and one for both Chrominances (Cb & Cr)
00686         */
00687         hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_0;
00688
00689         JPEG_SetColorYCBCR(hjpeg);
00690
00691         /* Set quantization table 0*/
00692         error  = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0));
00693         /*By default quantization table 0 for component 0 and quantization table 1 for both components 1 and 2*/
00694         error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (hjpeg->Instance->QMEM1));
00695
00696         if((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0) /*Use user customized quantization tables , 1 table per component*/
00697         {
00698           /* use 3 quantization tables , one for each component*/
00699           hjpeg->Instance->CONFR1 &= (~JPEG_CONFR1_COLORSPACE);
00700           hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_1;
00701
00702           error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (hjpeg->Instance->QMEM2));
00703
00704           /*Use Quantization 1 table for component 1*/
00705           hjpeg->Instance->CONFR5 &=  (~JPEG_CONFR5_QT);
00706           hjpeg->Instance->CONFR5 |=  JPEG_CONFR5_QT_0;
00707
00708           /*Use Quantization 2 table for component 2*/
00709           hjpeg->Instance->CONFR6 &=  (~JPEG_CONFR6_QT);
00710           hjpeg->Instance->CONFR6 |=  JPEG_CONFR6_QT_1;
00711         }
00712       }
00713       else /* ColorSpace == JPEG_CMYK_COLORSPACE */
00714       {
00715         JPEG_SetColorCMYK(hjpeg);
00716
00717          /* Set quantization table 0*/
00718         error  = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0));
00719         /*By default quantization table 0 for All components*/
00720
00721         if((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0) /*Use user customized quantization tables , 1 table per component*/
00722         {
00723           /* use 4 quantization tables , one for each component*/
00724           hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE;
00725
00726           error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (hjpeg->Instance->QMEM1));
00727           error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (hjpeg->Instance->QMEM2));
00728           error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable3, (hjpeg->Instance->QMEM3));
00729
00730           /*Use Quantization 1 table for component 1*/
00731           hjpeg->Instance->CONFR5 |=  JPEG_CONFR5_QT_0;
00732
00733           /*Use Quantization 2 table for component 2*/
00734           hjpeg->Instance->CONFR6 |=  JPEG_CONFR6_QT_1;
00735
00736           /*Use Quantization 3 table for component 3*/
00737           hjpeg->Instance->CONFR7 |=  JPEG_CONFR7_QT;
00738         }
00739       }
00740
00741       if(error != HAL_OK)
00742       {
00743         hjpeg->ErrorCode = HAL_JPEG_ERROR_QUANT_TABLE;
00744
00745         /* Process Unlocked */
00746         __HAL_UNLOCK(hjpeg);
00747
00748         /* Set the JPEG State to ready */
00749         hjpeg->State = HAL_JPEG_STATE_READY;
00750
00751         return  HAL_ERROR;
00752       }
00753       /* Set the image size*/
00754       MODIFY_REG(hjpeg->Instance->CONFR1, JPEG_CONFR1_YSIZE, ((hjpeg->Conf.ImageHeight & 0x0000FFFF) << 16)); /* set the number of lines*/
00755       MODIFY_REG(hjpeg->Instance->CONFR3, JPEG_CONFR3_XSIZE, ((hjpeg->Conf.ImageWidth & 0x0000FFFF) << 16)); /* set the number of pixels per line*/
00756
00757
00758       if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING)  /* 4:2:0*/
00759       {
00760         hfactor = 16;
00761         vfactor = 16;
00762       }
00763       else if(hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) /* 4:2:2*/
00764       {
00765         hfactor = 16;
00766         vfactor = 8;
00767       }
00768       else /* Default is 8x8 MCU,  4:4:4*/
00769       {
00770         hfactor = 8;
00771         vfactor = 8;
00772       }
00773
00774       hMCU = (hjpeg->Conf.ImageWidth / hfactor);
00775       if((hjpeg->Conf.ImageWidth % hfactor) != 0)
00776       {
00777         hMCU++; /*+1 for horizontal incomplete MCU */
00778       }
00779
00780       vMCU = (hjpeg->Conf.ImageHeight / vfactor);
00781       if((hjpeg->Conf.ImageHeight % vfactor) != 0)
00782       {
00783         vMCU++; /*+1 for vertical incomplete MCU */
00784       }
00785
00786       numberMCU = (hMCU * vMCU) - 1; /* Bit Field JPEG_CONFR2_NMCU shall be set to NB_MCU - 1*/
00787       /* Set the number of MCU*/
00788       hjpeg->Instance->CONFR2 =  (numberMCU & JPEG_CONFR2_NMCU);
00789
00790       hjpeg->Context |= JPEG_CONTEXT_CONF_ENCODING;
00791
00792       /* Process Unlocked */
00793       __HAL_UNLOCK(hjpeg);
00794
00795        /* Set the JPEG State to ready */
00796       hjpeg->State = HAL_JPEG_STATE_READY;
00797
00798       /* Return function status */
00799       return HAL_OK;
00800     }
00801     else
00802     {
00803       /* Process Unlocked */
00804       __HAL_UNLOCK(hjpeg);
00805
00806       /* Return function status */
00807       return HAL_BUSY;
00808     }
00809   }
00810 }
00811
00812 /**
00813   * @brief  Extract the image configuration from the JPEG header during the decoding
00814   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
00815   *         the configuration information for JPEG module
00816   * @param  pInfo: pointer to a JPEG_ConfTypeDef structure that contains
00817   *         The JPEG decoded header informations
00818   * @retval HAL status
00819   */
00820 HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
00821 {
00822   uint32_t yblockNb, cBblockNb, cRblockNb;
00823
00824   /* Check the JPEG handle allocation */
00825   if((hjpeg == NULL) || (pInfo == NULL))
00826   {
00827     return HAL_ERROR;
00828   }
00829
00830   /*Read the conf parameters */
00831   if((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF_1)
00832   {
00833     pInfo->ColorSpace = JPEG_YCBCR_COLORSPACE;
00834   }
00835   else if((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == 0)
00836   {
00837     pInfo->ColorSpace = JPEG_GRAYSCALE_COLORSPACE;
00838   }
00839   else if((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF)
00840   {
00841     pInfo->ColorSpace = JPEG_CMYK_COLORSPACE;
00842   }
00843
00844   pInfo->ImageHeight = (hjpeg->Instance->CONFR1 & 0xFFFF0000U) >> 16;
00845   pInfo->ImageWidth  = (hjpeg->Instance->CONFR3 & 0xFFFF0000U) >> 16;
00846
00847   if((pInfo->ColorSpace == JPEG_YCBCR_COLORSPACE) || (pInfo->ColorSpace == JPEG_CMYK_COLORSPACE))
00848   {
00849     yblockNb  = (hjpeg->Instance->CONFR4 & JPEG_CONFR4_NB) >> 4;
00850     cBblockNb = (hjpeg->Instance->CONFR5 & JPEG_CONFR5_NB) >> 4;
00851     cRblockNb = (hjpeg->Instance->CONFR6 & JPEG_CONFR6_NB) >> 4;
00852
00853     if((yblockNb == 1) && (cBblockNb == 0) && (cRblockNb == 0))
00854     {
00855       pInfo->ChromaSubsampling = JPEG_422_SUBSAMPLING; /*16x8 block*/
00856     }
00857     else if((yblockNb == 0) && (cBblockNb == 0) && (cRblockNb == 0))
00858     {
00859       pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING;
00860     }
00861     else if((yblockNb == 3) && (cBblockNb == 0) && (cRblockNb == 0))
00862     {
00863       pInfo->ChromaSubsampling = JPEG_420_SUBSAMPLING;
00864     }
00865     else /*Default is 4:4:4*/
00866     {
00867       pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING;
00868     }
00869   }
00870   else
00871   {
00872     pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING;
00873   }
00874
00875   pInfo->ImageQuality = JPEG_GetQuality(hjpeg);
00876
00877   /* Return function status */
00878   return HAL_OK;
00879 }
00880
00881 /**
00882   * @brief  Enable JPEG Header parsing for decoding
00883   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
00884   *               the configuration information for the JPEG.
00885   * @retval HAL status
00886   */
00887 HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg)
00888 {
00889   /* Process locked */
00890   __HAL_LOCK(hjpeg);
00891
00892   if(hjpeg->State == HAL_JPEG_STATE_READY)
00893   {
00894     /* Change the JPEG state */
00895     hjpeg->State = HAL_JPEG_STATE_BUSY;
00896
00897     /* Enable header processing*/
00898     hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR;
00899
00900     /* Process unlocked */
00901     __HAL_UNLOCK(hjpeg);
00902
00903     /* Change the JPEG state */
00904     hjpeg->State = HAL_JPEG_STATE_READY;
00905
00906     return HAL_OK;
00907   }
00908   else
00909   {
00910     /* Process unlocked */
00911     __HAL_UNLOCK(hjpeg);
00912
00913     return HAL_BUSY;
00914   }
00915 }
00916
00917 /**
00918   * @brief  Disable JPEG Header parsing for decoding
00919   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
00920   *               the configuration information for the JPEG.
00921   * @retval HAL status
00922   */
00923 HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg)
00924 {
00925   /* Process locked */
00926   __HAL_LOCK(hjpeg);
00927
00928   if(hjpeg->State == HAL_JPEG_STATE_READY)
00929   {
00930     /* Change the JPEG state */
00931     hjpeg->State = HAL_JPEG_STATE_BUSY;
00932
00933     /* Disable header processing*/
00934     hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_HDR;
00935
00936     /* Process unlocked */
00937     __HAL_UNLOCK(hjpeg);
00938
00939     /* Change the JPEG state */
00940     hjpeg->State = HAL_JPEG_STATE_READY;
00941
00942     return HAL_OK;
00943   }
00944   else
00945   {
00946     /* Process unlocked */
00947     __HAL_UNLOCK(hjpeg);
00948
00949     return HAL_BUSY;
00950   }
00951 }
00952
00953 /**
00954   * @brief  Modify the default Quantization tables used for JPEG encoding.
00955   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
00956   *         the configuration information for JPEG module
00957   * @param  QTable0 : pointer to uint8_t , define the user quantification table for color component 1.
00958   *                   If NULL assume no need to update  the table and no error return
00959   * @param  QTable1 : pointer to uint8_t , define the user quantification table for color component 2.
00960   *                   If NULL assume no need to update  the table and no error return.
00961   * @param  QTable2 : pointer to uint8_t , define the user quantification table for color component 3,
00962   *                   If NULL assume no need to update  the table and no error return.
00963   * @param  QTable3 : pointer to uint8_t , define the user quantification table for color component 4.
00964   *                   If NULL assume no need to update  the table and no error return.
00965   *
00966   * @retval HAL status
00967   */
00968
00969
00970 HAL_StatusTypeDef  HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, uint8_t *QTable2, uint8_t *QTable3)
00971 {
00972   /* Process Locked */
00973   __HAL_LOCK(hjpeg);
00974
00975   if(hjpeg->State == HAL_JPEG_STATE_READY)
00976   {
00977     /* Change the DMA state */
00978     hjpeg->State = HAL_JPEG_STATE_BUSY;
00979
00980     hjpeg->Context |= JPEG_CONTEXT_CUSTOM_TABLES;
00981
00982     hjpeg->QuantTable0 = QTable0;
00983     hjpeg->QuantTable1 = QTable1;
00984     hjpeg->QuantTable2 = QTable2;
00985     hjpeg->QuantTable3 = QTable3;
00986
00987     /* Process Unlocked */
00988     __HAL_UNLOCK(hjpeg);
00989
00990     /* Change the DMA state */
00991     hjpeg->State = HAL_JPEG_STATE_READY;
00992
00993     /* Return function status */
00994     return HAL_OK;
00995   }
00996   else
00997   {
00998     /* Process Unlocked */
00999     __HAL_UNLOCK(hjpeg);
01000
01001     return HAL_BUSY;
01002   }
01003 }
01004
01005 /**
01006   * @}
01007   */
01008
01009 /** @defgroup JPEG_Exported_Functions_Group3 encoding/decoding processing functions
01010  *  @brief   processing functions.
01011  *
01012 @verbatim
01013   ==============================================================================
01014                       ##### JPEG processing functions #####
01015   ==============================================================================
01016     [..]  This section provides functions allowing to:
01017       (+) HAL_JPEG_Encode()     : JPEG encoding with polling process
01018       (+) HAL_JPEG_Decode()     : JPEG decoding with polling process
01019       (+) HAL_JPEG_Encode_IT()  : JPEG encoding with interrupt process
01020       (+) HAL_JPEG_Decode_IT()  : JPEG decoding with interrupt process
01021       (+) HAL_JPEG_Encode_DMA() : JPEG encoding with DMA process
01022       (+) HAL_JPEG_Decode_DMA() : JPEG decoding with DMA process
01023       (+) HAL_JPEG_Pause()      :   Pause the Input/Output processing
01024       (+) HAL_JPEG_Resume()     :  Resume the JPEG Input/Output processing
01025       (+) HAL_JPEG_ConfigInputBuffer()  : Config Encoding/Decoding Input Buffer
01026       (+) HAL_JPEG_ConfigOutputBuffer() : Config Encoding/Decoding Output Buffer
01027       (+) HAL_JPEG_Abort()              : Aborts the JPEG Encoding/Decoding
01028
01029 @endverbatim
01030   * @{
01031   */
01032
01033 /**
01034   * @brief  Starts JPEG encoding with polling processing
01035   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
01036   *         the configuration information for JPEG module
01037   * @param  pDataInMCU: Pointer to the Input buffer
01038   * @param  InDataLength: size in bytes Input buffer
01039   * @param  pDataOut: Pointer to the jpeg output data buffer
01040   * @param  OutDataLength: size in bytes of the Output buffer
01041   * @param  Timeout: Specify Timeout value
01042   * @retval HAL status
01043   */
01044 HAL_StatusTypeDef  HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout)
01045 {
01046   uint32_t tickstart = 0;
01047
01048   /* Check the parameters */
01049   assert_param((InDataLength >= 4));
01050   assert_param((OutDataLength >= 4));
01051
01052   /* Check In/out buffer allocation and size */
01053   if((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL))
01054   {
01055     return HAL_ERROR;
01056   }
01057   /* Process locked */
01058   __HAL_LOCK(hjpeg);
01059
01060   if(hjpeg->State != HAL_JPEG_STATE_READY)
01061   {
01062     /* Process Unlocked */
01063     __HAL_UNLOCK(hjpeg);
01064
01065     return HAL_BUSY;
01066   }
01067
01068   if(hjpeg->State == HAL_JPEG_STATE_READY)
01069   {
01070     if((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING )
01071     {
01072       /*Change JPEG state*/
01073       hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING;
01074
01075       /*Set the Context to Encode with Polling*/
01076       hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
01077       hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_POLLING);
01078
01079       /* Get tick */
01080       tickstart = HAL_GetTick();
01081       /*In/Out Data length must be multiple of 4 Bytes (1 word)*/
01082       InDataLength = InDataLength - (InDataLength % 4);
01083       OutDataLength = OutDataLength - (OutDataLength % 4);
01084
01085       /*Store In/out buffers pointers and size*/
01086       hjpeg->pJpegInBuffPtr = pDataInMCU;
01087       hjpeg->pJpegOutBuffPtr = pDataOut;
01088       hjpeg->InDataLength = InDataLength;
01089       hjpeg->OutDataLength = OutDataLength;
01090
01091       /*Reset In/out data counter */
01092       hjpeg->JpegInCount = 0;
01093       hjpeg->JpegOutCount = 0;
01094
01095       /*Init decoding process*/
01096       JPEG_Init_Process(hjpeg);
01097
01098       /*JPEG data processing : In/Out FIFO transfer*/
01099       while((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING))
01100       {
01101         if(Timeout != HAL_MAX_DELAY)
01102         {
01103           if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01104           {
01105
01106             /* Update error code */
01107             hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT;
01108
01109             /* Process Unlocked */
01110             __HAL_UNLOCK(hjpeg);
01111
01112            /*Change JPEG state*/
01113             hjpeg->State= HAL_JPEG_STATE_READY;
01114
01115             return HAL_TIMEOUT;
01116           }
01117         }
01118       }
01119
01120       /* Process Unlocked */
01121       __HAL_UNLOCK(hjpeg);
01122
01123       /*Change JPEG state*/
01124       hjpeg->State= HAL_JPEG_STATE_READY;
01125
01126     }else
01127     {
01128       /* Process Unlocked */
01129       __HAL_UNLOCK(hjpeg);
01130
01131       return HAL_ERROR;
01132     }
01133   }
01134   /* Return function status */
01135   return HAL_OK;
01136 }
01137
01138 /**
01139   * @brief  Starts JPEG decoding with polling processing
01140   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
01141   *         the configuration information for JPEG module
01142   * @param  pDataIn: Pointer to the input data buffer
01143   * @param  InDataLength: size in bytes Input buffer
01144   * @param  pDataOutMCU: Pointer to the Output data buffer
01145   * @param  OutDataLength: size in bytes of the Output buffer
01146   * @param  Timeout: Specify Timeout value
01147   * @retval HAL status
01148   */
01149 HAL_StatusTypeDef  HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength, uint32_t Timeout)
01150 {
01151   uint32_t tickstart = 0;
01152
01153   /* Check the parameters */
01154   assert_param((InDataLength >= 4));
01155   assert_param((OutDataLength >= 4));
01156
01157   /* Check In/out buffer allocation and size */
01158   if((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL))
01159   {
01160     return HAL_ERROR;
01161   }
01162
01163   /* Process Locked */
01164   __HAL_LOCK(hjpeg);
01165
01166   /* Get tick */
01167   tickstart = HAL_GetTick();
01168
01169   if(hjpeg->State == HAL_JPEG_STATE_READY)
01170   {
01171     /*Change JPEG state*/
01172     hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING;
01173
01174     /*Set the Context to Decode with Polling*/
01175     /*Set the Context to Encode with Polling*/
01176     hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
01177     hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_POLLING);
01178
01179     /*In/Out Data length must be multiple of 4 Bytes (1 word)*/
01180     InDataLength = InDataLength - (InDataLength % 4);
01181     OutDataLength = OutDataLength - (OutDataLength % 4);
01182
01183     /*Store In/out buffers pointers and size*/
01184     hjpeg->pJpegInBuffPtr = pDataIn;
01185     hjpeg->pJpegOutBuffPtr = pDataOutMCU;
01186     hjpeg->InDataLength = InDataLength;
01187     hjpeg->OutDataLength = OutDataLength;
01188
01189     /*Reset In/out data counter */
01190     hjpeg->JpegInCount = 0;
01191     hjpeg->JpegOutCount = 0;
01192
01193     /*Init decoding process*/
01194     JPEG_Init_Process(hjpeg);
01195
01196     /*JPEG data processing : In/Out FIFO transfer*/
01197     while((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING))
01198     {
01199       if(Timeout != HAL_MAX_DELAY)
01200       {
01201         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01202         {
01203
01204           /* Update error code */
01205           hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT;
01206
01207           /* Process Unlocked */
01208           __HAL_UNLOCK(hjpeg);
01209
01210           /*Change JPEG state*/
01211           hjpeg->State= HAL_JPEG_STATE_READY;
01212
01213           return HAL_TIMEOUT;
01214         }
01215       }
01216     }
01217
01218     /* Process Unlocked */
01219     __HAL_UNLOCK(hjpeg);
01220
01221     /*Change JPEG state*/
01222     hjpeg->State= HAL_JPEG_STATE_READY;
01223
01224   }else
01225   {
01226     /* Process Unlocked */
01227     __HAL_UNLOCK(hjpeg);
01228
01229     return HAL_BUSY;
01230   }
01231   /* Return function status */
01232   return HAL_OK;
01233 }
01234
01235 /**
01236   * @brief  Starts JPEG encoding with interrupt processing
01237   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
01238   *         the configuration information for JPEG module
01239   * @param  pDataInMCU: Pointer to the Input buffer
01240   * @param  InDataLength: size in bytes Input buffer
01241   * @param  pDataOut: Pointer to the jpeg output data buffer
01242   * @param  OutDataLength: size in bytes of the Output buffer
01243   * @retval HAL status
01244   */
01245 HAL_StatusTypeDef  HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)
01246 {
01247   /* Check the parameters */
01248   assert_param((InDataLength >= 4));
01249   assert_param((OutDataLength >= 4));
01250
01251   /* Check In/out buffer allocation and size */
01252   if((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL))
01253   {
01254     return HAL_ERROR;
01255   }
01256
01257   /* Process Locked */
01258   __HAL_LOCK(hjpeg);
01259
01260   if(hjpeg->State != HAL_JPEG_STATE_READY)
01261   {
01262     /* Process Unlocked */
01263     __HAL_UNLOCK(hjpeg);
01264
01265     return HAL_BUSY;
01266   }
01267   else
01268   {
01269     if((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING )
01270     {
01271       /*Change JPEG state*/
01272       hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING;
01273
01274       /*Set the Context to Encode with IT*/
01275       hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
01276       hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_IT);
01277
01278       /*In/Out Data length must be multiple of 4 Bytes (1 word)*/
01279       InDataLength = InDataLength - (InDataLength % 4);
01280       OutDataLength = OutDataLength - (OutDataLength % 4);
01281
01282       /*Store In/out buffers pointers and size*/
01283       hjpeg->pJpegInBuffPtr = pDataInMCU;
01284       hjpeg->pJpegOutBuffPtr = pDataOut;
01285       hjpeg->InDataLength = InDataLength;
01286       hjpeg->OutDataLength = OutDataLength;
01287
01288       /*Reset In/out data counter */
01289       hjpeg->JpegInCount = 0;
01290       hjpeg->JpegOutCount = 0;
01291
01292       /*Init decoding process*/
01293       JPEG_Init_Process(hjpeg);
01294
01295     }
01296     else
01297     {
01298       /* Process Unlocked */
01299       __HAL_UNLOCK(hjpeg);
01300
01301       return HAL_ERROR;
01302     }
01303   }
01304   /* Return function status */
01305   return HAL_OK;
01306 }
01307
01308 /**
01309   * @brief  Starts JPEG decoding with interrupt processing
01310   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
01311   *         the configuration information for JPEG module
01312   * @param  pDataIn: Pointer to the input data buffer
01313   * @param  InDataLength: size in bytes Input buffer
01314   * @param  pDataOutMCU: Pointer to the Output data buffer
01315   * @param  OutDataLength: size in bytes of the Output buffer
01316   * @retval HAL status
01317   */
01318 HAL_StatusTypeDef  HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength)
01319 {
01320   /* Check the parameters */
01321   assert_param((InDataLength >= 4));
01322   assert_param((OutDataLength >= 4));
01323
01324   /* Check In/out buffer allocation and size */
01325   if((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL))
01326   {
01327     return HAL_ERROR;
01328   }
01329
01330   /* Process Locked */
01331   __HAL_LOCK(hjpeg);
01332
01333   if(hjpeg->State == HAL_JPEG_STATE_READY)
01334   {
01335     /*Change JPEG state*/
01336     hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING;
01337
01338     /*Set the Context to Decode with IT*/
01339     hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
01340     hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_IT);
01341
01342     /*In/Out Data length must be multiple of 4 Bytes (1 word)*/
01343     InDataLength = InDataLength - (InDataLength % 4);
01344     OutDataLength = OutDataLength - (OutDataLength % 4);
01345
01346     /*Store In/out buffers pointers and size*/
01347     hjpeg->pJpegInBuffPtr = pDataIn;
01348     hjpeg->pJpegOutBuffPtr = pDataOutMCU;
01349     hjpeg->InDataLength = InDataLength;
01350     hjpeg->OutDataLength = OutDataLength;
01351
01352     /*Reset In/out data counter */
01353     hjpeg->JpegInCount = 0;
01354     hjpeg->JpegOutCount = 0;
01355
01356     /*Init decoding process*/
01357     JPEG_Init_Process(hjpeg);
01358
01359   }
01360   else
01361   {
01362     /* Process Unlocked */
01363     __HAL_UNLOCK(hjpeg);
01364
01365     return HAL_BUSY;
01366   }
01367   /* Return function status */
01368   return HAL_OK;
01369 }
01370
01371 /**
01372   * @brief  Starts JPEG encoding with DMA processing
01373   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
01374   *         the configuration information for JPEG module
01375   * @param  pDataInMCU: Pointer to the Input buffer
01376   * @param  InDataLength: size in bytes Input buffer
01377   * @param  pDataOut: Pointer to the jpeg output data buffer
01378   * @param  OutDataLength: size in bytes of the Output buffer
01379   * @retval HAL status
01380   */
01381 HAL_StatusTypeDef  HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)
01382 {
01383   /* Check the parameters */
01384   assert_param((InDataLength >= 4));
01385   assert_param((OutDataLength >= 4));
01386
01387   /* Check In/out buffer allocation and size */
01388   if((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL))
01389   {
01390     return HAL_ERROR;
01391   }
01392
01393   /* Process Locked */
01394   __HAL_LOCK(hjpeg);
01395
01396   if(hjpeg->State != HAL_JPEG_STATE_READY)
01397   {
01398     /* Process Unlocked */
01399     __HAL_UNLOCK(hjpeg);
01400
01401     return HAL_BUSY;
01402   }
01403   else
01404   {
01405     if((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING )
01406     {
01407       /*Change JPEG state*/
01408       hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING;
01409
01410       /*Set the Context to Encode with DMA*/
01411       hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
01412       hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_DMA);
01413
01414       /*Store In/out buffers pointers and size*/
01415       hjpeg->pJpegInBuffPtr = pDataInMCU;
01416       hjpeg->pJpegOutBuffPtr = pDataOut;
01417       hjpeg->InDataLength = InDataLength;
01418       hjpeg->OutDataLength = OutDataLength;
01419
01420       /*Reset In/out data counter */
01421       hjpeg->JpegInCount = 0;
01422       hjpeg->JpegOutCount = 0;
01423
01424       /*Init decoding process*/
01425       JPEG_Init_Process(hjpeg);
01426
01427       /* JPEG encoding process using DMA */
01428       JPEG_DMA_StartProcess(hjpeg);
01429
01430     }
01431     else
01432     {
01433       /* Process Unlocked */
01434       __HAL_UNLOCK(hjpeg);
01435
01436       return HAL_ERROR;
01437     }
01438   }
01439   /* Return function status */
01440   return HAL_OK;
01441 }
01442
01443 /**
01444   * @brief  Starts JPEG decoding with DMA processing
01445   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
01446   *         the configuration information for JPEG module
01447   * @param  pDataIn: Pointer to the input data buffer
01448   * @param  InDataLength: size in bytes Input buffer
01449   * @param  pDataOutMCU: Pointer to the Output data buffer
01450   * @param  OutDataLength: size in bytes of the Output buffer
01451   * @retval HAL status
01452   */
01453 HAL_StatusTypeDef  HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength)
01454 {
01455   /* Check the parameters */
01456   assert_param((InDataLength >= 4));
01457   assert_param((OutDataLength >= 4));
01458
01459   /* Check In/out buffer allocation and size */
01460   if((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL))
01461   {
01462     return HAL_ERROR;
01463   }
01464
01465   /* Process Locked */
01466   __HAL_LOCK(hjpeg);
01467
01468   if(hjpeg->State == HAL_JPEG_STATE_READY)
01469   {
01470     /*Change JPEG state*/
01471     hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING;
01472
01473     /*Set the Context to Decode with DMA*/
01474     hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
01475     hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_DMA);
01476
01477     /*Store In/out buffers pointers and size*/
01478     hjpeg->pJpegInBuffPtr = pDataIn;
01479     hjpeg->pJpegOutBuffPtr = pDataOutMCU;
01480     hjpeg->InDataLength = InDataLength;
01481     hjpeg->OutDataLength = OutDataLength;
01482
01483     /*Reset In/out data counter */
01484     hjpeg->JpegInCount = 0;
01485     hjpeg->JpegOutCount = 0;
01486
01487     /*Init decoding process*/
01488     JPEG_Init_Process(hjpeg);
01489
01490     /* JPEG decoding process using DMA */
01491     JPEG_DMA_StartProcess(hjpeg);
01492
01493   }
01494   else
01495   {
01496     /* Process Unlocked */
01497     __HAL_UNLOCK(hjpeg);
01498
01499     return HAL_BUSY;
01500   }
01501   /* Return function status */
01502   return HAL_OK;
01503 }
01504
01505 /**
01506   * @brief  Pause the JPEG Input/Output processing
01507   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
01508   *         the configuration information for JPEG module
01509   * @param  XferSelection: This parameter can be one of the following values :
01510   *                           JPEG_PAUSE_RESUME_INPUT : Pause Input processing
01511   *                           JPEG_PAUSE_RESUME_OUTPUT: Pause Output processing
01512   *                           JPEG_PAUSE_RESUME_INPUT_OUTPUT: Pause Input and Output processing
01513   * @retval HAL status
01514   */
01515 HAL_StatusTypeDef  HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)
01516 {
01517   uint32_t mask = 0;
01518
01519   assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection));
01520
01521   if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
01522   {
01523     if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
01524     {
01525       hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT;
01526     }
01527     if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
01528     {
01529       hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT;
01530     }
01531   }
01532   else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
01533   {
01534
01535     if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
01536     {
01537       hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT;
01538       mask |= (JPEG_IT_IFT | JPEG_IT_IFNF);
01539     }
01540     if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
01541     {
01542       hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT;
01543       mask |=  (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC);
01544     }
01545     __HAL_JPEG_DISABLE_IT(hjpeg,mask);
01546
01547   }
01548
01549   /* Return function status */
01550   return HAL_OK;
01551 }
01552
01553 /**
01554   * @brief  Resume the JPEG Input/Output processing
01555   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
01556   *         the configuration information for JPEG module
01557   * @param  XferSelection: This parameter can be one of the following values :
01558   *                           JPEG_PAUSE_RESUME_INPUT : Resume Input processing
01559   *                           JPEG_PAUSE_RESUME_OUTPUT: Resume Output processing
01560   *                           JPEG_PAUSE_RESUME_INPUT_OUTPUT: Resume Input and Output processing
01561   * @retval HAL status
01562   */
01563 HAL_StatusTypeDef  HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)
01564 {
01565   uint32_t mask = 0;
01566   uint32_t xfrSize = 0;
01567
01568   assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection));
01569
01570   if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
01571   {
01572
01573     if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
01574     {
01575       hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT);
01576
01577       /*if the MDMA In is triggred with JPEG In FIFO Threshold flag
01578         then MDMA In buffer size is 32 bytes
01579
01580         else (MDMA In is triggred with JPEG In FIFO not full flag)
01581         then MDMA In buffer size is 4 bytes
01582       */
01583       xfrSize = hjpeg->hdmain->Init.BufferTransferLength;
01584
01585       /*MDMA transfer size (BNDTR) must be a multiple of MDMA buffer size (TLEN)*/
01586       hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % xfrSize);
01587
01588       if(hjpeg->InDataLength > 0)
01589       {
01590         /* Start DMA FIFO In transfer */
01591         HAL_MDMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, hjpeg->InDataLength, 1);
01592       }
01593     }
01594     if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
01595     {
01596       hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT);
01597
01598       if((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0)
01599       {
01600         JPEG_DMA_PollResidualData(hjpeg);
01601       }
01602       else
01603       {
01604         /*if the MDMA Out is triggred with JPEG Out FIFO Threshold flag
01605           then MDMA out buffer size is 32 bytes
01606           else (MDMA Out is triggred with JPEG Out FIFO not empty flag)
01607           then MDMA buffer size is 4 bytes
01608         */
01609         xfrSize = hjpeg->hdmaout->Init.BufferTransferLength;
01610
01611         /*MDMA transfer size (BNDTR) must be a multiple of MDMA buffer size (TLEN)*/
01612         hjpeg->OutDataLength = hjpeg->OutDataLength - (hjpeg->OutDataLength % xfrSize);
01613
01614         /* Start DMA FIFO Out transfer */
01615         HAL_MDMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength, 1);
01616       }
01617     }
01618   }
01619   else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
01620   {
01621     if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
01622     {
01623       hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT);
01624       mask |= (JPEG_IT_IFT | JPEG_IT_IFNF);
01625     }
01626     if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
01627     {
01628       hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT);
01629       mask |=  (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC);
01630     }
01631     __HAL_JPEG_ENABLE_IT(hjpeg,mask);
01632
01633   }
01634
01635   /* Return function status */
01636   return HAL_OK;
01637 }
01638
01639 /**
01640   * @brief  Config Encoding/Decoding Input Buffer.
01641   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
01642   *         the configuration information for JPEG module.
01643   * @param  pNewInputBuffer: Pointer to the new input data buffer
01644   * @param  InDataLength: Size in bytes of the new Input data buffer
01645   * @retval HAL status
01646   */
01647 void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength)
01648 {
01649   hjpeg->pJpegInBuffPtr =  pNewInputBuffer;
01650   hjpeg->InDataLength = InDataLength;
01651 }
01652
01653 /**
01654   * @brief  Config Encoding/Decoding Output Buffer.
01655   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
01656   *         the configuration information for JPEG module.
01657   * @param  pNewOutputBuffer: Pointer to the new output data buffer
01658   * @param  OutDataLength: Size in bytes of the new Output data buffer
01659   * @retval HAL status
01660   */
01661 void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength)
01662 {
01663   hjpeg->pJpegOutBuffPtr = pNewOutputBuffer;
01664   hjpeg->OutDataLength = OutDataLength;
01665 }
01666
01667 /**
01668   * @brief  Aborts the JPEG Encoding/Decoding.
01669   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
01670   *         the configuration information for JPEG module
01671   * @retval HAL status
01672   */
01673 HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg)
01674 {
01675   uint32_t tickstart, tmpContext;
01676
01677   tmpContext = hjpeg->Context;
01678
01679   /*Reset the Context operation and method*/
01680   hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA);
01681
01682   if((tmpContext & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
01683   {
01684     /* Stop the DMA In/out Xfer*/
01685     HAL_MDMA_Abort(hjpeg->hdmaout);
01686     HAL_MDMA_Abort(hjpeg->hdmain);
01687   }
01688
01689   /* Stop the JPEG encoding/decoding process*/
01690   hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
01691
01692   /* Get tick */
01693   tickstart = HAL_GetTick();
01694
01695   /* Check if the JPEG Codec is effectively disabled */
01696   while(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_COF) != RESET)
01697   {
01698     /* Check for the Timeout */
01699     if((HAL_GetTick() - tickstart ) > JPEG_TIMEOUT_VALUE)
01700     {
01701       /* Update error code */
01702       hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT;
01703
01704       /* Change the DMA state */
01705       hjpeg->State = HAL_JPEG_STATE_TIMEOUT;
01706
01707       /* Process Unlocked */
01708       __HAL_UNLOCK(hjpeg);
01709
01710       return HAL_TIMEOUT;
01711     }
01712   }
01713
01714   /* Disable All Interrupts */
01715   __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
01716
01717   /* Flush input and output FIFOs*/
01718   hjpeg->Instance->CR |= JPEG_CR_IFF;
01719   hjpeg->Instance->CR |= JPEG_CR_OFF;
01720
01721   /* Clear all flags */
01722   __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);
01723
01724   /* Reset JpegInCount and JpegOutCount */
01725   hjpeg->JpegInCount = 0;
01726   hjpeg->JpegOutCount = 0;
01727
01728   /*Reset the Context Pause*/
01729   hjpeg->Context &= ~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT);
01730
01731   /* Change the DMA state*/
01732   hjpeg->State = HAL_JPEG_STATE_READY;
01733
01734   /* Process Unlocked */
01735   __HAL_UNLOCK(hjpeg);
01736
01737   /* Return function status */
01738   return HAL_OK;
01739 }
01740
01741
01742 /**
01743   * @}
01744   */
01745
01746 /** @defgroup JPEG_Exported_Functions_Group4 JPEG Decode/Encode callback functions
01747  *  @brief   JPEG process callback functions.
01748  *
01749 @verbatim
01750   ==============================================================================
01751               #####  JPEG Decode and Encode callback functions  #####
01752   ==============================================================================
01753     [..]  This section provides callback functions:
01754       (+) HAL_JPEG_InfoReadyCallback()  : Decoding JPEG Info ready callback
01755       (+) HAL_JPEG_EncodeCpltCallback() : Encoding complete callback.
01756       (+) HAL_JPEG_DecodeCpltCallback() : Decoding complete callback.
01757       (+) HAL_JPEG_ErrorCallback()      : JPEG error callback.
01758       (+) HAL_JPEG_GetDataCallback()    : Get New Data chunk callback.
01759       (+) HAL_JPEG_DataReadyCallback()  : Decoded/Encoded Data ready  callback.
01760
01761 @endverbatim
01762   * @{
01763   */
01764
01765 /**
01766   * @brief  Decoding JPEG Info ready callback.
01767   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
01768   *         the configuration information for JPEG module
01769   * @param  pInfo: pointer to a JPEG_ConfTypeDef structure that contains
01770   *         The JPEG decoded header informations
01771   * @retval None
01772   */
01773 __weak void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg,JPEG_ConfTypeDef *pInfo)
01774 {
01775   /* Prevent unused argument(s) compilation warning */
01776   UNUSED(hjpeg);
01777   UNUSED(pInfo);
01778
01779   /* NOTE : This function Should not be modified, when the callback is needed,
01780             the HAL_JPEG_HeaderParsingCpltCallback could be implemented in the user file
01781    */
01782 }
01783
01784 /**
01785   * @brief  Encoding complete callback.
01786   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
01787   *         the configuration information for JPEG module
01788   * @retval None
01789   */
01790 __weak void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg)
01791 {
01792   /* Prevent unused argument(s) compilation warning */
01793   UNUSED(hjpeg);
01794
01795   /* NOTE : This function Should not be modified, when the callback is needed,
01796             the HAL_JPEG_EncodeCpltCallback could be implemented in the user file
01797    */
01798 }
01799
01800 /**
01801   * @brief  Decoding complete callback.
01802   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
01803   *         the configuration information for JPEG module
01804   * @retval None
01805   */
01806 __weak void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg)
01807 {
01808   /* Prevent unused argument(s) compilation warning */
01809   UNUSED(hjpeg);
01810
01811   /* NOTE : This function Should not be modified, when the callback is needed,
01812             the HAL_JPEG_EncodeCpltCallback could be implemented in the user file
01813    */
01814 }
01815
01816 /**
01817   * @brief  JPEG error callback.
01818   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
01819   *         the configuration information for JPEG module
01820   * @retval None
01821   */
01822  __weak void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg)
01823 {
01824   /* Prevent unused argument(s) compilation warning */
01825   UNUSED(hjpeg);
01826
01827   /* NOTE : This function Should not be modified, when the callback is needed,
01828             the HAL_JPEG_ErrorCallback could be implemented in the user file
01829    */
01830 }
01831
01832 /**
01833   * @brief  Get New Data chunk callback.
01834   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
01835   *         the configuration information for JPEG module
01836   * @param  NbDecodedData: Number of consummed data in the previous chunk in bytes
01837   * @retval None
01838   */
01839  __weak void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData)
01840 {
01841   /* Prevent unused argument(s) compilation warning */
01842   UNUSED(hjpeg);
01843   UNUSED(NbDecodedData);
01844
01845   /* NOTE : This function Should not be modified, when the callback is needed,
01846             the HAL_JPEG_GetDataCallback could be implemented in the user file
01847    */
01848 }
01849
01850 /**
01851   * @brief  Decoded/Encoded Data ready  callback.
01852   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
01853   *         the configuration information for JPEG module
01854   * @param  pDataOut: pointer to the output data buffer
01855   * @param  OutDataLength: number in bytes of data available in the specified output buffer
01856   * @retval None
01857   */
01858 __weak void HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength)
01859 {
01860   /* Prevent unused argument(s) compilation warning */
01861   UNUSED(hjpeg);
01862   UNUSED(pDataOut);
01863   UNUSED(OutDataLength);
01864
01865   /* NOTE : This function Should not be modified, when the callback is needed,
01866             the HAL_JPEG_DataReadyCallback could be implemented in the user file
01867    */
01868 }
01869
01870 /**
01871   * @}
01872   */
01873
01874
01875 /** @defgroup JPEG_Exported_Functions_Group5 JPEG IRQ handler management
01876  *  @brief   JPEG IRQ handler.
01877  *
01878 @verbatim
01879   ==============================================================================
01880                 ##### JPEG IRQ handler management #####
01881   ==============================================================================
01882     [..]  This section provides JPEG IRQ handler function.
01883       (+) HAL_JPEG_IRQHandler()  : handles JPEG interrupt request
01884
01885 @endverbatim
01886   * @{
01887   */
01888
01889 /**
01890   * @brief  This function handles JPEG interrupt request.
01891   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
01892   *         the configuration information for JPEG module
01893   * @retval None
01894   */
01895 void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg)
01896 {
01897   switch(hjpeg->State)
01898   {
01899     case HAL_JPEG_STATE_BUSY_ENCODING:
01900     case HAL_JPEG_STATE_BUSY_DECODING:
01901       /* continue JPEG data encoding/Decoding*/
01902       /* JPEG data processing : In/Out FIFO transfer*/
01903       if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
01904       {
01905         JPEG_Process(hjpeg);
01906       }
01907       else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
01908       {
01909         JPEG_DMA_ContinueProcess(hjpeg);
01910
01911       }
01912
01913       break;
01914
01915     default:
01916       break;
01917   }
01918 }
01919
01920 /**
01921   * @}
01922   */
01923
01924 /** @defgroup JPEG_Exported_Functions_Group6 Peripheral State functions
01925  *  @brief   Peripheral State functions.
01926  *
01927 @verbatim
01928   ==============================================================================
01929                     ##### Peripheral State and Error functions #####
01930   ==============================================================================
01931     [..]  This section provides JPEG State and Errors function.
01932       (+) HAL_JPEG_GetState()  : permits to get in run-time the JPEG state.
01933       (+) HAL_JPEG_GetError()  : Returns the JPEG error code if any.
01934
01935 @endverbatim
01936   * @{
01937   */
01938
01939 /**
01940   * @brief  Returns the JPEG state.
01941   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
01942   *         the configuration information for JPEG module
01943   * @retval JPEG state
01944   */
01945 HAL_JPEG_STATETypeDef HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg)
01946 {
01947   return hjpeg->State;
01948 }
01949
01950 /**
01951 * @brief  Return the JPEG error code
01952 * @param  hjpeg : pointer to a JPEG_HandleTypeDef structure that contains
01953   *              the configuration information for the specified JPEG.
01954 * @retval JPEG Error Code
01955 */
01956 uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg)
01957 {
01958   return hjpeg->ErrorCode;
01959 }
01960
01961 /**
01962   * @}
01963   */
01964
01965 /**
01966   * @}
01967   */
01968
01969
01970 /** @addtogroup JPEG_Private_Functions
01971   * @{
01972   */
01973
01974 /**
01975   * @brief  Generates Huffman sizes/Codes Table from Bits/vals Table
01976   * @param  Bits: pointer to bits table
01977   * @param  Huffsize: pointer to sizes table
01978   * @param  Huffcode: pointer to codes table
01979   * @param  LastK: pointer to last Coeff (table dimmension)
01980   * @retval HAL status
01981   */
01982 static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK)
01983 {
01984   uint32_t i, p, l, code, si;
01985
01986   /* Figure C.1: Generation of table of Huffman code sizes */
01987   p = 0;
01988   for (l = 0; l < 16; l++)
01989   {
01990     i = (uint32_t)Bits[l];
01991     if ( (p + i) > 256)
01992     {  /* check for table overflow */
01993       return HAL_ERROR;
01994     }
01995     while (i != 0)
01996     {
01997       Huffsize[p++] = (uint8_t) l+1;
01998       i--;
01999     }
02000   }
02001   Huffsize[p] = 0;
02002   *LastK = p;
02003
02004   /* Figure C.2: Generation of table of Huffman codes */
02005   code = 0;
02006   si = Huffsize[0];
02007   p = 0;
02008   while (Huffsize[p] != 0)
02009   {
02010     while (((uint32_t) Huffsize[p]) == si)
02011     {
02012       Huffcode[p++] = code;
02013       code++;
02014     }
02015     /* code must fit in "size" bits (si), no code is allowed to be all ones*/
02016     if (((uint32_t) code) >= (((uint32_t) 1) << si))
02017     {
02018       return HAL_ERROR;
02019     }
02020     code <<= 1;
02021     si++;
02022   }
02023   /* Return function status */
02024   return HAL_OK;
02025 }
02026
02027 /**
02028   * @brief  Transform a Bits/Vals AC Huffman table to sizes/Codes huffman Table
02029   *         that can programmed to the JPEG encoder registers
02030   * @param  AC_BitsValsTable: pointer to AC huffman bits/vals table
02031   * @param  AC_SizeCodesTable: pointer to AC huffman Sizes/Codes table
02032   * @retval HAL status
02033   */
02034 static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable)
02035 {
02036   HAL_StatusTypeDef error;
02037   uint8_t huffsize[257];
02038   uint32_t huffcode[257];
02039   uint32_t k;
02040   uint32_t l,lsb, msb;
02041   uint32_t lastK;
02042
02043   error = JPEG_Bits_To_SizeCodes(AC_BitsValsTable->Bits, huffsize, huffcode, &lastK);
02044   if(error != HAL_OK)
02045   {
02046     return  error;
02047   }
02048
02049   /* Figure C.3: Ordering procedure for encoding procedure code tables */
02050   k=0;
02051
02052   while(k < lastK)
02053   {
02054     l = AC_BitsValsTable->HuffVal[k];
02055     if(l == 0)
02056     {
02057       l = 160; /*l = 0x00 EOB code*/
02058     }
02059     else if(l == 0xF0)/* l = 0xF0 ZRL code*/
02060     {
02061       l = 161;
02062     }
02063     else
02064     {
02065       msb = (l & 0xF0) >> 4;
02066       lsb = (l & 0x0F);
02067       l = (msb * 10) + lsb - 1;
02068     }
02069     if(l >= JPEG_AC_HUFF_TABLE_SIZE)
02070     {
02071       return HAL_ERROR; /* Huffman Table overflow error*/
02072     }
02073     else
02074     {
02075       AC_SizeCodesTable->HuffmanCode[l] = huffcode[k];
02076       AC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1;
02077       k++;
02078     }
02079   }
02080
02081   /* Return function status */
02082   return HAL_OK;
02083 }
02084
02085 /**
02086   * @brief  Transform a Bits/Vals DC Huffman table to sizes/Codes huffman Table
02087   *         that can programmed to the JPEG encoder registers
02088   * @param  DC_BitsValsTable: pointer to DC huffman bits/vals table
02089   * @param  DC_SizeCodesTable: pointer to DC huffman Sizes/Codes table
02090   * @retval HAL status
02091   */
02092 static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable)
02093 {
02094   HAL_StatusTypeDef error;
02095
02096   uint32_t k;
02097   uint32_t l;
02098   uint32_t lastK;
02099   uint8_t huffsize[257];
02100   uint32_t huffcode[257];
02101   error = JPEG_Bits_To_SizeCodes(DC_BitsValsTable->Bits, huffsize, huffcode, &lastK);
02102   if(error != HAL_OK)
02103   {
02104     return  error;
02105   }
02106   /* Figure C.3: ordering procedure for encoding procedure code tables */
02107   k=0;
02108
02109   while(k < lastK)
02110   {
02111     l = DC_BitsValsTable->HuffVal[k];
02112     if(l >= JPEG_DC_HUFF_TABLE_SIZE)
02113     {
02114       return HAL_ERROR; /* Huffman Table overflow error*/
02115     }
02116     else
02117     {
02118       DC_SizeCodesTable->HuffmanCode[l] = huffcode[k];
02119       DC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1;
02120       k++;
02121     }
02122   }
02123
02124   /* Return function status */
02125   return HAL_OK;
02126 }
02127
02128 /**
02129   * @brief  Set the JPEG register with an DC huffman table at the given DC table address
02130   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
02131   *         the configuration information for JPEG module
02132   * @param  HuffTableDC: pointer to DC huffman table
02133   * @param  DCTableAddress: Encoder DC huffman table address it could be HUFFENC_DC0 or HUFFENC_DC1.
02134   * @retval HAL status
02135   */
02136 static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, __IO uint32_t *DCTableAddress)
02137 {
02138   HAL_StatusTypeDef error = HAL_OK;
02139   JPEG_DC_HuffCodeTableTypeDef dcSizeCodesTable;
02140   uint32_t i, lsb, msb;
02141   __IO uint32_t *address, *addressDef;
02142
02143   if(DCTableAddress == (hjpeg->Instance->HUFFENC_DC0))
02144   {
02145     address = (hjpeg->Instance->HUFFENC_DC0 + (JPEG_DC_HUFF_TABLE_SIZE/2));
02146   }
02147   else if (DCTableAddress == (hjpeg->Instance->HUFFENC_DC1))
02148   {
02149     address = (hjpeg->Instance->HUFFENC_DC1 + (JPEG_DC_HUFF_TABLE_SIZE/2));
02150   }
02151   else
02152   {
02153     return HAL_ERROR;
02154   }
02155
02156   if(HuffTableDC != NULL)
02157   {
02158     error = JPEG_DCHuff_BitsVals_To_SizeCodes(HuffTableDC, &dcSizeCodesTable);
02159     if(error != HAL_OK)
02160     {
02161       return  error;
02162     }
02163     addressDef = address;
02164     *addressDef = 0x0FFF0FFF;
02165     addressDef++;
02166     *addressDef = 0x0FFF0FFF;
02167
02168     i = JPEG_DC_HUFF_TABLE_SIZE;
02169     while(i>0)
02170     {
02171       i--;
02172       address --;
02173       msb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & 0xFF);
02174       i--;
02175       lsb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & 0xFF);
02176
02177       *address = lsb | (msb << 16);
02178     }
02179   }
02180
02181   /* Return function status */
02182   return HAL_OK;
02183 }
02184
02185 /**
02186   * @brief  Set the JPEG register with an AC huffman table at the given AC table address
02187   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
02188   *         the configuration information for JPEG module
02189   * @param  HuffTableAC: pointer to AC huffman table
02190   * @param  ACTableAddress: Encoder AC huffman table address it could be HUFFENC_AC0 or HUFFENC_AC1.
02191   * @retval HAL status
02192   */
02193 static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, __IO uint32_t *ACTableAddress)
02194 {
02195   HAL_StatusTypeDef error = HAL_OK;
02196   JPEG_AC_HuffCodeTableTypeDef acSizeCodesTable;
02197   uint32_t i, lsb, msb;
02198   __IO uint32_t *address, *addressDef;
02199
02200   if(ACTableAddress == (hjpeg->Instance->HUFFENC_AC0))
02201   {
02202     address = (hjpeg->Instance->HUFFENC_AC0 + (JPEG_AC_HUFF_TABLE_SIZE/2));
02203   }
02204   else if (ACTableAddress == (hjpeg->Instance->HUFFENC_AC1))
02205   {
02206     address = (hjpeg->Instance->HUFFENC_AC1 + (JPEG_AC_HUFF_TABLE_SIZE/2));
02207   }
02208   else
02209   {
02210     return HAL_ERROR;
02211   }
02212
02213   if(HuffTableAC != NULL)
02214   {
02215     error = JPEG_ACHuff_BitsVals_To_SizeCodes(HuffTableAC, &acSizeCodesTable);
02216     if(error != HAL_OK)
02217     {
02218       return  error;
02219     }
02220     /* Default values settings: 162:167 FFFh , 168:175 FD0h_FD7h */
02221     /* Locations 162:175 of each AC table contain information used internally by the core */
02222
02223     addressDef = address;
02224     for(i=0; i<3; i++)
02225     {
02226       *addressDef = 0x0FFF0FFF;
02227       addressDef++;
02228     }
02229     *addressDef = 0x0FD10FD0;
02230     addressDef++;
02231     *addressDef = 0x0FD30FD2;
02232     addressDef++;
02233     *addressDef = 0x0FD50FD4;
02234     addressDef++;
02235     *addressDef = 0x0FD70FD6;
02236     /* end of Locations 162:175  */
02237
02238
02239     i = JPEG_AC_HUFF_TABLE_SIZE;
02240     while (i > 0)
02241     {
02242       i--;
02243       address--;
02244       msb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] & 0xFF);
02245       i--;
02246       lsb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] & 0xFF);
02247
02248       *address = lsb | (msb << 16);
02249     }
02250   }
02251
02252   /* Return function status */
02253   return HAL_OK;
02254 }
02255
02256 /**
02257   * @brief  Configure the JPEG encoder register huffman tables to used during
02258   *         the encdoing operation
02259   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
02260   *         the configuration information for JPEG module
02261   * @param  HuffTableAC0: AC0 huffman table
02262   * @param  HuffTableDC0: DC0 huffman table
02263   * @param  HuffTableAC1: AC1 huffman table
02264   * @param  HuffTableDC1: DC1 huffman table
02265   * @retval None
02266   */
02267 static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 ,  JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1)
02268 {
02269   HAL_StatusTypeDef error = HAL_OK;
02270
02271   JPEG_Set_Huff_DHTMem(hjpeg, HuffTableAC0, HuffTableDC0, HuffTableAC1, HuffTableDC1);
02272
02273   if(HuffTableAC0 != NULL)
02274   {
02275     error = JPEG_Set_HuffAC_Mem(hjpeg, HuffTableAC0, (hjpeg->Instance->HUFFENC_AC0));
02276     if(error != HAL_OK)
02277     {
02278       return  error;
02279     }
02280   }
02281
02282   if(HuffTableAC1 != NULL)
02283   {
02284     error = JPEG_Set_HuffAC_Mem(hjpeg, HuffTableAC1, (hjpeg->Instance->HUFFENC_AC1));
02285     if(error != HAL_OK)
02286     {
02287       return  error;
02288     }
02289   }
02290
02291   if(HuffTableDC0 != NULL)
02292   {
02293     error = JPEG_Set_HuffDC_Mem(hjpeg, HuffTableDC0, hjpeg->Instance->HUFFENC_DC0);
02294     if(error != HAL_OK)
02295     {
02296       return  error;
02297     }
02298   }
02299
02300   if(HuffTableDC1 != NULL)
02301   {
02302     error = JPEG_Set_HuffDC_Mem(hjpeg, HuffTableDC1, hjpeg->Instance->HUFFENC_DC1);
02303     if(error != HAL_OK)
02304     {
02305       return  error;
02306     }
02307   }
02308   /* Return function status */
02309   return HAL_OK;
02310 }
02311
02312 /**
02313   * @brief  Configure the JPEG register huffman tables to be included in the JPEG
02314   *         file header (used for encoding only)
02315   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
02316   *         the configuration information for JPEG module
02317   * @param  HuffTableAC0: AC0 huffman table
02318   * @param  HuffTableDC0: DC0 huffman table
02319   * @param  HuffTableAC1: AC1 huffman table
02320   * @param  HuffTableDC1: DC1 huffman table
02321   * @retval None
02322   */
02323 static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 ,  JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1)
02324 {
02325   uint32_t value, index;
02326   __IO uint32_t *address;
02327   if(HuffTableDC0 != NULL)
02328   {
02329     /* DC0 Huffman Table : BITS*/
02330     /* DC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address to DHTMEM + 3*/
02331     address = (hjpeg->Instance->DHTMEM + 3);
02332     index = 16;
02333     while(index > 0)
02334     {
02335
02336       *address = (((uint32_t)HuffTableDC0->Bits[index-1] & 0xFF) << 24)|
02337                  (((uint32_t)HuffTableDC0->Bits[index-2] & 0xFF) << 16)|
02338                  (((uint32_t)HuffTableDC0->Bits[index-3] & 0xFF) << 8) |
02339                  ((uint32_t)HuffTableDC0->Bits[index-4] & 0xFF);
02340       address--;
02341       index -=4;
02342
02343     }
02344     /* DC0 Huffman Table : Val*/
02345     /* DC0 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +4 to DHTMEM + 6 */
02346     address = (hjpeg->Instance->DHTMEM + 6);
02347     index = 12;
02348     while(index > 0)
02349     {
02350       *address = (((uint32_t)HuffTableDC0->HuffVal[index-1] & 0xFF) << 24)|
02351                  (((uint32_t)HuffTableDC0->HuffVal[index-2] & 0xFF) << 16)|
02352                  (((uint32_t)HuffTableDC0->HuffVal[index-3] & 0xFF) << 8) |
02353                  ((uint32_t)HuffTableDC0->HuffVal[index-4] & 0xFF);
02354       address--;
02355       index -=4;
02356     }
02357   }
02358
02359   if(HuffTableAC0 != NULL)
02360   {
02361     /* AC0 Huffman Table : BITS*/
02362     /* AC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 7 to DHTMEM + 10*/
02363     address = (hjpeg->Instance->DHTMEM + 10);
02364     index = 16;
02365     while(index > 0)
02366     {
02367
02368       *address = (((uint32_t)HuffTableAC0->Bits[index-1] & 0xFF) << 24)|
02369                  (((uint32_t)HuffTableAC0->Bits[index-2] & 0xFF) << 16)|
02370                  (((uint32_t)HuffTableAC0->Bits[index-3] & 0xFF) << 8) |
02371                  ((uint32_t)HuffTableAC0->Bits[index-4] & 0xFF);
02372       address--;
02373       index -=4;
02374
02375     }
02376     /* AC0 Huffman Table : Val*/
02377     /* AC0 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 11 to DHTMEM + 51 */
02378     /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 51) belong to AC0 VALS table */
02379     address = (hjpeg->Instance->DHTMEM + 51);
02380     value = *address & 0xFFFF0000U;
02381     value = value | (((uint32_t)HuffTableAC0->HuffVal[161] & 0xFF) << 8) | ((uint32_t)HuffTableAC0->HuffVal[160] & 0xFF);
02382     *address = value;
02383
02384     /*continue setting 160 AC0 huffman values */
02385     address--; /* address = hjpeg->Instance->DHTMEM + 50*/
02386     index = 160;
02387     while(index > 0)
02388     {
02389       *address = (((uint32_t)HuffTableAC0->HuffVal[index-1] & 0xFF) << 24)|
02390                  (((uint32_t)HuffTableAC0->HuffVal[index-2] & 0xFF) << 16)|
02391                  (((uint32_t)HuffTableAC0->HuffVal[index-3] & 0xFF) << 8) |
02392                  ((uint32_t)HuffTableAC0->HuffVal[index-4] & 0xFF);
02393       address--;
02394       index -=4;
02395     }
02396   }
02397
02398   if(HuffTableDC1 != NULL)
02399   {
02400     /* DC1 Huffman Table : BITS*/
02401     /* DC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM + 51 base address to DHTMEM + 55*/
02402     /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 51) belong to DC1 Bits table */
02403     address = (hjpeg->Instance->DHTMEM + 51);
02404     value = *address & 0x0000FFFFU;
02405     value = value | (((uint32_t)HuffTableDC1->Bits[1] & 0xFF) << 24) | (((uint32_t)HuffTableDC1->Bits[0] & 0xFF) << 16);
02406     *address = value;
02407
02408     /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 55) belong to DC1 Bits table */
02409     address = (hjpeg->Instance->DHTMEM + 55);
02410     value = *address & 0xFFFF0000U;
02411     value = value | (((uint32_t)HuffTableDC1->Bits[15] & 0xFF) << 8) | ((uint32_t)HuffTableDC1->Bits[14] & 0xFF);
02412     *address = value;
02413
02414     /*continue setting 12 DC1 huffman Bits from DHTMEM + 54 down to DHTMEM + 52*/
02415     address--;
02416     index = 12;
02417     while(index > 0)
02418     {
02419
02420       *address = (((uint32_t)HuffTableDC1->Bits[index+1] & 0xFF) << 24)|
02421                  (((uint32_t)HuffTableDC1->Bits[index] & 0xFF) << 16)|
02422                  (((uint32_t)HuffTableDC1->Bits[index-1] & 0xFF) << 8) |
02423                  ((uint32_t)HuffTableDC1->Bits[index-2] & 0xFF);
02424       address--;
02425       index -=4;
02426
02427     }
02428     /* DC1 Huffman Table : Val*/
02429     /* DC1 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +55 to DHTMEM + 58 */
02430     /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 55) belong to DC1 Val table */
02431     address = (hjpeg->Instance->DHTMEM + 55);
02432     value = *address & 0x0000FFFF;
02433     value = value | (((uint32_t)HuffTableDC1->HuffVal[1] & 0xFF) << 24) | (((uint32_t)HuffTableDC1->HuffVal[0] & 0xFF) << 16);
02434     *address = value;
02435
02436     /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 58) belong to DC1 Val table */
02437     address = (hjpeg->Instance->DHTMEM + 58);
02438     value = *address & 0xFFFF0000U;
02439     value = value | (((uint32_t)HuffTableDC1->HuffVal[11] & 0xFF) << 8) | ((uint32_t)HuffTableDC1->HuffVal[10] & 0xFF);
02440     *address = value;
02441
02442     /*continue setting 8 DC1 huffman val from DHTMEM + 57 down to DHTMEM + 56*/
02443     address--;
02444     index = 8;
02445     while(index > 0)
02446     {
02447       *address = (((uint32_t)HuffTableDC1->HuffVal[index+1] & 0xFF) << 24)|
02448                  (((uint32_t)HuffTableDC1->HuffVal[index] & 0xFF) << 16)|
02449                  (((uint32_t)HuffTableDC1->HuffVal[index-1] & 0xFF) << 8) |
02450                  ((uint32_t)HuffTableDC1->HuffVal[index-2] & 0xFF);
02451       address--;
02452       index -=4;
02453     }
02454   }
02455
02456   if(HuffTableAC1 != NULL)
02457   {
02458     /* AC1 Huffman Table : BITS*/
02459     /* AC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 58 to DHTMEM + 62*/
02460     /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 58) belong to AC1 Bits table */
02461     address = (hjpeg->Instance->DHTMEM + 58);
02462     value = *address & 0x0000FFFFU;
02463     value = value | (((uint32_t)HuffTableAC1->Bits[1] & 0xFF) << 24) | (((uint32_t)HuffTableAC1->Bits[0] & 0xFF) << 16);
02464     *address = value;
02465
02466     /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 62) belong to Bits Val table */
02467     address = (hjpeg->Instance->DHTMEM + 62);
02468     value = *address & 0xFFFF0000U;
02469     value = value | (((uint32_t)HuffTableAC1->Bits[15] & 0xFF) << 8) | ((uint32_t)HuffTableAC1->Bits[14] & 0xFF);
02470     *address = value;
02471
02472     /*continue setting 12 AC1 huffman Bits from DHTMEM + 61 down to DHTMEM + 59*/
02473     address--;
02474     index = 12;
02475     while(index > 0)
02476     {
02477
02478       *address = (((uint32_t)HuffTableAC1->Bits[index+1] & 0xFF) << 24)|
02479                  (((uint32_t)HuffTableAC1->Bits[index] & 0xFF) << 16)|
02480                  (((uint32_t)HuffTableAC1->Bits[index-1] & 0xFF) << 8) |
02481                  ((uint32_t)HuffTableAC1->Bits[index-2] & 0xFF);
02482       address--;
02483       index -=4;
02484
02485     }
02486     /* AC1 Huffman Table : Val*/
02487     /* AC1 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 62 to DHTMEM + 102 */
02488     /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 62) belong to AC1 VALS table */
02489     address = (hjpeg->Instance->DHTMEM + 62);
02490     value = *address & 0x0000FFFF;
02491     value = value | (((uint32_t)HuffTableAC1->HuffVal[1] & 0xFF) << 24) | (((uint32_t)HuffTableAC1->HuffVal[0] & 0xFF) << 16);
02492     *address = value;
02493
02494     /*continue setting 160 AC1 huffman values from DHTMEM + 63 to DHTMEM+102 */
02495     address = (hjpeg->Instance->DHTMEM + 102);
02496     index = 160;
02497     while(index > 0)
02498     {
02499       *address = (((uint32_t)HuffTableAC1->HuffVal[index+1] & 0xFF) << 24)|
02500                  (((uint32_t)HuffTableAC1->HuffVal[index] & 0xFF) << 16)|
02501                  (((uint32_t)HuffTableAC1->HuffVal[index-1] & 0xFF) << 8) |
02502                  ((uint32_t)HuffTableAC1->HuffVal[index-2] & 0xFF);
02503       address--;
02504       index -=4;
02505     }
02506   }
02507 }
02508
02509 /**
02510   * @brief  Configure the JPEG registers with a given quantization table
02511   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
02512   *         the configuration information for JPEG module
02513   * @param  QTable: pointer to an array of 64 bytes giving the quantization table
02514   * @param  QTableAddress: destination quantization address in the JPEG peripheral
02515   *         it could be QMEM0, QMEM1, QMEM2 or QMEM3
02516   * @retval None
02517   */
02518 static HAL_StatusTypeDef  JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, __IO uint32_t *QTableAddress)
02519 {
02520   uint32_t i, j, quantRow, quantVal, ScaleFactor;
02521   __IO uint32_t *tableAddress;
02522
02523   if((QTableAddress == ((hjpeg->Instance->QMEM0))) ||
02524      (QTableAddress == ((hjpeg->Instance->QMEM1))) ||
02525      (QTableAddress == ((hjpeg->Instance->QMEM2))) ||
02526      (QTableAddress == ((hjpeg->Instance->QMEM3))))
02527   {
02528     tableAddress = QTableAddress;
02529   }
02530   else
02531   {
02532     return HAL_ERROR;
02533   }
02534
02535   if ((hjpeg->Conf.ImageQuality >= 50) && (hjpeg->Conf.ImageQuality <= 100))
02536   {
02537     ScaleFactor = 200 - (hjpeg->Conf.ImageQuality * 2);
02538   }
02539   else if (hjpeg->Conf.ImageQuality > 0)
02540   {
02541     ScaleFactor = ((uint32_t) 5000) / ((uint32_t) hjpeg->Conf.ImageQuality);
02542   }
02543   else
02544   {
02545     return HAL_ERROR;
02546   }
02547
02548   /*Quantization_table = (Standard_quanization_table * ScaleFactor + 50) / 100*/
02549   i = 0;
02550   while( i < JPEG_QUANT_TABLE_SIZE)
02551   {
02552     quantRow = 0;
02553     for(j=0; j<4; j++)
02554     {
02555       /* Note that the quantization coefficients must be specified in the table in zigzag order */
02556       quantVal = ((((uint32_t) QTable[JPEG_ZIGZAG_ORDER[i+j]]) * ScaleFactor) + 50) / 100;
02557
02558       if(quantVal == 0)
02559       {
02560         quantVal = 1;
02561       }
02562       else if (quantVal > 255)
02563       {
02564         quantVal = 255;
02565       }
02566
02567       quantRow |= ((quantVal & 0xFF) << (8 * j));
02568     }
02569
02570     i += 4;
02571     *tableAddress = quantRow;
02572     tableAddress ++;
02573   }
02574
02575   /* Return function status */
02576   return HAL_OK;
02577 }
02578
02579 /**
02580   * @brief  Configure the JPEG registers for YCbCr color space
02581   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
02582   *         the configuration information for JPEG module
02583   * @retval None
02584   */
02585 static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg)
02586 {
02587   uint32_t ySamplingH;
02588   uint32_t ySamplingV;
02589   uint32_t yblockNb;
02590
02591   /*Set Number of color components to 3*/
02592   hjpeg->Instance->CONFR1 &=  ~JPEG_CONFR1_NF;
02593   hjpeg->Instance->CONFR1 |=  JPEG_CONFR1_NF_1;
02594
02595   /* compute MCU block size and Y, Cb ,Cr sampling factors*/
02596   if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING)
02597   {
02598     ySamplingH  = JPEG_CONFR4_HSF_1;   /* Hs = 2*/
02599     ySamplingV  = JPEG_CONFR4_VSF_1;   /* Vs = 2*/
02600
02601     yblockNb  = 0x30; /* 4 blocks of 8x8*/
02602   }
02603   else if(hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING)
02604   {
02605     ySamplingH  = JPEG_CONFR4_HSF_1;   /* Hs = 2*/
02606     ySamplingV  = JPEG_CONFR4_VSF_0;   /* Vs = 1*/
02607
02608     yblockNb  = 0x10; /* 2 blocks of 8x8*/
02609   }
02610   else /*JPEG_444_SUBSAMPLING and default*/
02611   {
02612     ySamplingH  = JPEG_CONFR4_HSF_0;   /* Hs = 1*/
02613     ySamplingV  = JPEG_CONFR4_VSF_0;   /* Vs = 1*/
02614
02615     yblockNb  = 0; /* 1 block of 8x8*/
02616   }
02617
02618   hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS);
02619   hjpeg->Instance->CONFR1 |=  (JPEG_CONFR1_NF_1 | JPEG_CONFR1_NS_1);
02620
02621   /*Reset CONFR4 register*/
02622   hjpeg->Instance->CONFR4 =  0;
02623   /*Set Horizental and Vertical  sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/
02624   hjpeg->Instance->CONFR4 |=  (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB) );
02625
02626   /*Reset CONFR5 register*/
02627   hjpeg->Instance->CONFR5 =  0;
02628   /*Set Horizental and Vertical  sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 1*/
02629   hjpeg->Instance->CONFR5 |=  (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0 | JPEG_CONFR5_QT_0 | JPEG_CONFR5_HA | JPEG_CONFR5_HD);
02630
02631   /*Reset CONFR6 register*/
02632   hjpeg->Instance->CONFR6 =  0;
02633   /*Set Horizental and Vertical  sampling factor and number of blocks for component 2*/
02634   /* In YCBCR , by default, both chrominance components (component 1 and component 2) use the same Quantization table (table 1) */
02635   /* In YCBCR , both chrominance components (component 1 and component 2) use the same Huffman tables (table 1) */
02636   hjpeg->Instance->CONFR6 |=  (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0 | JPEG_CONFR6_QT_0 | JPEG_CONFR6_HA | JPEG_CONFR6_HD);
02637
02638 }
02639
02640 /**
02641   * @brief  Configure the JPEG registers for GrayScale color space
02642   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
02643   *         the configuration information for JPEG module
02644   * @retval None
02645   */
02646 static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg)
02647 {
02648   /*Set Number of color components to 1*/
02649   hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS);
02650
02651   /*in GrayScale use 1 single Quantization table (Table 0)*/
02652   /*in GrayScale use only one couple of AC/DC huffman table (table 0)*/
02653
02654   /*Reset CONFR4 register*/
02655   hjpeg->Instance->CONFR4 =  0;
02656   /*Set Horizental and Vertical  sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/
02657   hjpeg->Instance->CONFR4 |=  JPEG_CONFR4_HSF_0 | JPEG_CONFR4_VSF_0 ;
02658 }
02659
02660 /**
02661   * @brief  Configure the JPEG registers for CMYK color space
02662   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
02663   *         the configuration information for JPEG module
02664   * @retval None
02665   */
02666 static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg)
02667 {
02668   uint32_t ySamplingH;
02669   uint32_t ySamplingV;
02670   uint32_t yblockNb;
02671
02672   /*Set Number of color components to 4*/
02673   hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF | JPEG_CONFR1_NS);
02674
02675   /* compute MCU block size and Y, Cb ,Cr sampling factors*/
02676   if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING)
02677   {
02678     ySamplingH  = JPEG_CONFR4_HSF_1;   /* Hs = 2*/
02679     ySamplingV  = JPEG_CONFR4_VSF_1;   /* Vs = 2*/
02680
02681     yblockNb  = 0x30; /* 4 blocks of 8x8*/
02682   }
02683   else if(hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING)
02684   {
02685     ySamplingH  = JPEG_CONFR4_HSF_1;   /* Hs = 2*/
02686     ySamplingV  = JPEG_CONFR4_VSF_0;   /* Vs = 1*/
02687
02688     yblockNb  = 0x10; /* 2 blocks of 8x8*/
02689   }
02690   else /*JPEG_444_SUBSAMPLING and default*/
02691   {
02692     ySamplingH  = JPEG_CONFR4_HSF_0;   /* Hs = 1*/
02693     ySamplingV  = JPEG_CONFR4_VSF_0;   /* Vs = 1*/
02694
02695     yblockNb  = 0; /* 1 block of 8x8*/
02696   }
02697
02698   /*Reset CONFR4 register*/
02699   hjpeg->Instance->CONFR4 =  0;
02700   /*Set Horizental and Vertical  sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/
02701   hjpeg->Instance->CONFR4 |=  (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB) );
02702
02703   /*Reset CONFR5 register*/
02704   hjpeg->Instance->CONFR5 =  0;
02705   /*Set Horizental and Vertical  sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 1*/
02706   hjpeg->Instance->CONFR5 |=  (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0);
02707
02708   /*Reset CONFR6 register*/
02709   hjpeg->Instance->CONFR6 =  0;
02710   /*Set Horizental and Vertical  sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 2*/
02711   hjpeg->Instance->CONFR6 |=  (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0);
02712
02713   /*Reset CONFR7 register*/
02714   hjpeg->Instance->CONFR7 =  0;
02715   /*Set Horizental and Vertical  sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 3*/
02716   hjpeg->Instance->CONFR7 |=  (JPEG_CONFR7_HSF_0 | JPEG_CONFR7_VSF_0);
02717 }
02718
02719 /**
02720   * @brief  Init the JPEG encoding/decoding process in case of Polling or Interrupt and DMA
02721   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
02722   *         the configuration information for JPEG module
02723   * @retval None
02724   */
02725 static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg)
02726 {
02727   /*Reset pause*/
02728   hjpeg->Context &= (~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT));
02729
02730   if((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
02731   {
02732     /*Set JPEG Codec to Decoding mode */
02733     hjpeg->Instance->CONFR1 |= JPEG_CONFR1_DE;
02734   }
02735   else if((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE)
02736   {
02737     /*Set JPEG Codec to Encoding mode */
02738     hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_DE;
02739   }
02740
02741   /*Stop JPEG processing */
02742   hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
02743
02744   /* Disable All Interrupts */
02745   __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
02746
02747   /* Flush input and output FIFOs*/
02748   hjpeg->Instance->CR |= JPEG_CR_IFF;
02749   hjpeg->Instance->CR |= JPEG_CR_OFF;
02750
02751   /* Clear all flags */
02752   __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);
02753
02754   /*Start Encoding/Decoding*/
02755   hjpeg->Instance->CONFR0 |=  JPEG_CONFR0_START;
02756
02757   if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
02758   {
02759     /*Enable IN/OUT, end of Conversation, and end of header parsing interruptions*/
02760     __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_IFT | JPEG_IT_IFNF | JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC |JPEG_IT_HPD);
02761   }
02762   else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
02763   {
02764     /*Enable End Of Conversation, and End Of Header parsing interruptions*/
02765     __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC |JPEG_IT_HPD);
02766
02767   }
02768 }
02769
02770 /**
02771   * @brief  JPEG encoding/decoding process in case of Polling or Interrupt
02772   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
02773   *         the configuration information for JPEG module
02774   * @retval JPEG_PROCESS_DONE if the process has ends else JPEG_PROCESS_ONGOING
02775   */
02776 static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg)
02777 {
02778   uint32_t tmpContext;
02779
02780   /*End of header processing flag rised*/
02781   if(((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) && (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != RESET))
02782   {
02783     /*Call Header parsing complet callback */
02784     HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf);
02785     /* Reset the ImageQuality */
02786     hjpeg->Conf.ImageQuality = 0;
02787     /* Note : the image quality is only available at the end of the decoding operation */
02788     /* at the current stage the calculated image quality is not correct so reset it */
02789
02790     /*Call Info Ready callback */
02791     HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf);
02792
02793     __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_IT_HPD);
02794
02795     /* Clear header processing done flag */
02796     __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_HPDF);
02797   }
02798
02799   /*Input FIFO status handling*/
02800   if((hjpeg->Context &  JPEG_CONTEXT_PAUSE_INPUT) == 0)
02801   {
02802     if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFTF) != RESET)
02803     {
02804       /*Input FIFO threshold flag rised*/
02805       /*4 words (16 bytes) can be written in */
02806       JPEG_ReadInputData(hjpeg,JPEG_FIFO_TH_SIZE);
02807     }
02808     else if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFNFF) != RESET)
02809     {
02810       /*Input FIFO Not Full flag rised*/
02811       /*32-bit value can be written in */
02812       JPEG_ReadInputData(hjpeg,1);
02813     }
02814   }
02815
02816
02817   /*Output FIFO flag handling*/
02818   if((hjpeg->Context &  JPEG_CONTEXT_PAUSE_OUTPUT) == 0)
02819   {
02820     if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFTF) != RESET)
02821     {
02822       /*Output FIFO threshold flag rised*/
02823       /*4 words (16 bytes) can be read out */
02824       JPEG_StoreOutputData(hjpeg, JPEG_FIFO_TH_SIZE);
02825     }
02826     else if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != RESET)
02827     {
02828       /*Output FIFO Not Empty flag rised*/
02829       /*32-bit value can be read out */
02830       JPEG_StoreOutputData(hjpeg, 1);
02831     }
02832   }
02833
02834   /*End of Conversion handling :i.e EOC flag is high and OFTF low and OFNEF low*/
02835   if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF | JPEG_FLAG_OFTF | JPEG_FLAG_OFNEF) == JPEG_FLAG_EOCF)
02836   {
02837     /*Stop Encoding/Decoding*/
02838     hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
02839
02840     if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
02841     {
02842       /* Disable All Interrupts */
02843       __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
02844     }
02845
02846     /* Clear all flags */
02847     __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);
02848
02849     /*Call End of conversion callback */
02850     if(hjpeg->JpegOutCount > 0)
02851     {
02852       /*Output Buffer is not empty, call DecodedDataReadyCallback*/
02853       HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
02854       hjpeg->JpegOutCount = 0;
02855     }
02856
02857     /*Reset Context Operation*/
02858     tmpContext = hjpeg->Context;
02859     /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
02860     hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);
02861
02862     /* Process Unlocked */
02863     __HAL_UNLOCK(hjpeg);
02864
02865     /* Change the JPEG state */
02866     hjpeg->State = HAL_JPEG_STATE_READY;
02867
02868     /*Call End of Encoding/Decoding callback */
02869     if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
02870     {
02871       HAL_JPEG_DecodeCpltCallback(hjpeg);
02872     }
02873     else if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE)
02874     {
02875       HAL_JPEG_EncodeCpltCallback(hjpeg);
02876     }
02877
02878     return JPEG_PROCESS_DONE;
02879   }
02880
02881
02882   return JPEG_PROCESS_ONGOING;
02883 }
02884
02885 /**
02886   * @brief  Store some output data from the JPEG peripheral to the output buffer.
02887   *         This function is used when the JPEG peripheral has new data to output
02888   *         in case of Polling or Interrupt process
02889   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
02890   *         the configuration information for JPEG module
02891   * @param  nbOutputWords: Number of output words (of 32 bits) ready from the JPEG peripheral
02892   * @retval None
02893   */
02894 static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords)
02895 {
02896   uint32_t index, nBwords, nbBytes , dataword;
02897
02898   if(hjpeg->OutDataLength >= (hjpeg->JpegOutCount + (nbOutputWords*4)))
02899   {
02900     for(index = 0; index < nbOutputWords; index++)
02901     {
02902       /*Transfer 32 bits from the JPEG output FIFO*/
02903       dataword = hjpeg->Instance->DOR;
02904       hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = dataword & 0x000000FF;
02905       hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1] = (dataword & 0x0000FF00) >> 8;
02906       hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2] = (dataword & 0x00FF0000) >> 16;
02907       hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3] = (dataword & 0xFF000000) >> 24;
02908       hjpeg->JpegOutCount += 4;
02909     }
02910     if(hjpeg->OutDataLength == hjpeg->JpegOutCount)
02911     {
02912       /*Output Buffer is full, call DecodedDataReadyCallback*/
02913       HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
02914       hjpeg->JpegOutCount = 0;
02915     }
02916   }
02917   else if(hjpeg->OutDataLength > hjpeg->JpegOutCount)
02918   {
02919     nBwords = (hjpeg->OutDataLength - hjpeg->JpegOutCount)/4;
02920     for(index = 0; index < nBwords; index++)
02921     {
02922       /*Transfer 32 bits from the JPEG output FIFO*/
02923       dataword = hjpeg->Instance->DOR;
02924       hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = dataword & 0x000000FF;
02925       hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1] = (dataword & 0x0000FF00) >> 8;
02926       hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2] = (dataword & 0x00FF0000) >> 16;
02927       hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3] = (dataword & 0xFF000000) >> 24;
02928       hjpeg->JpegOutCount += 4;
02929     }
02930     if(hjpeg->OutDataLength == hjpeg->JpegOutCount)
02931     {
02932       /*Output Buffer is full, call DecodedDataReadyCallback*/
02933       HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
02934       hjpeg->JpegOutCount = 0;
02935     }
02936     else
02937     {
02938       nbBytes = hjpeg->OutDataLength - hjpeg->JpegOutCount;
02939       dataword = hjpeg->Instance->DOR;
02940       for(index = 0; index < nbBytes; index++)
02941       {
02942         hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (dataword >> (8*index)) & 0xFF;
02943         hjpeg->JpegOutCount++;
02944       }
02945       /*Output Buffer is full, call DecodedDataReadyCallback*/
02946       HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
02947       hjpeg->JpegOutCount = 0;
02948
02949       nbBytes = 4 - nbBytes;
02950       for(index = nbBytes; index < 4; index++)
02951       {
02952         hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (dataword >> (8*index)) & 0xFF;
02953         hjpeg->JpegOutCount++;
02954       }
02955     }
02956   }
02957 }
02958
02959 /**
02960   * @brief  Read some input Data from the input buffer.
02961   *         This function is used when the JPEG peripheral needs new data
02962   *         in case of Polling or Interrupt process
02963   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
02964   *         the configuration information for JPEG module
02965   * @param  nbRequestWords: Number of input words (of 32 bits) that the JPE peripheral request
02966   * @retval None
02967   */
02968 static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords)
02969 {
02970   uint32_t nbBytes = 0, nBwords = 0, index = 0, Dataword = 0, inputCount = 0;
02971
02972   if((hjpeg->InDataLength == 0) || (nbRequestWords == 0))
02973   {
02974     /* No more Input data : nothing to do*/
02975     HAL_JPEG_Pause(hjpeg, JPEG_PAUSE_RESUME_INPUT);
02976   }
02977   else if(hjpeg->InDataLength > hjpeg->JpegInCount)
02978   {
02979     nbBytes = hjpeg->InDataLength - hjpeg->JpegInCount;
02980   }
02981   else if(hjpeg->InDataLength == hjpeg->JpegInCount)
02982   {
02983     /*Call HAL_JPEG_GetDataCallback to get new data */
02984     HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount);
02985     if(hjpeg->InDataLength > 4)
02986     {
02987       hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4);
02988     }
02989     hjpeg->JpegInCount = 0;
02990     nbBytes = hjpeg->InDataLength;
02991   }
02992   if((nbBytes > 0) && ((hjpeg->Context &  JPEG_CONTEXT_PAUSE_INPUT) == 0))
02993   {
02994     nBwords = nbBytes / 4;
02995     if(nBwords >= nbRequestWords)
02996     {
02997       for(index = 0; index < nbRequestWords; index++)
02998       {
02999         inputCount = hjpeg->JpegInCount;
03000         hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount])) | (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 1])) << 8) |\
03001           (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 2])) << 16) | (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 3])) << 24));
03002
03003         hjpeg->JpegInCount += 4;
03004       }
03005     }
03006     else /*nBwords < nbRequestWords*/
03007     {
03008       if(nBwords > 0)
03009       {
03010         for(index = 0; index < nBwords; index++)
03011         {
03012           inputCount = hjpeg->JpegInCount;
03013           hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount])) | (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 1])) << 8) |\
03014           (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 2])) << 16) | (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 3])) << 24));
03015
03016           hjpeg->JpegInCount += 4;
03017         }
03018       }
03019       else
03020       {
03021         /* end of file*/
03022         Dataword = 0;
03023         for(index=0; index< nbBytes; index++)
03024         {
03025           Dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8 * index);
03026           hjpeg->JpegInCount++;
03027         }
03028         hjpeg->Instance->DIR = Dataword;
03029       }
03030     }
03031   }
03032 }
03033
03034 /**
03035   * @brief  Start the JPEG DMA process (encoding/decoding)
03036   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
03037   *         the configuration information for JPEG module
03038   * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING
03039   */
03040 static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg)
03041 {
03042   uint32_t inXfrSize, outXfrSize;
03043
03044   /*if the MDMA In is triggred with JPEG In FIFO Threshold flag
03045       then MDMA In buffer size is 32 bytes
03046     else (MDMA In is triggred with JPEG In FIFO not full flag)
03047       then MDMA In buffer size is 4 bytes
03048   */
03049   inXfrSize = hjpeg->hdmain->Init.BufferTransferLength;
03050
03051   /*if the MDMA Out is triggred with JPEG Out FIFO Threshold flag
03052       then MDMA out buffer size is 32 bytes
03053     else (MDMA Out is triggred with JPEG Out FIFO not empty flag)
03054       then MDMA buffer size is 4 bytes
03055   */
03056   outXfrSize = hjpeg->hdmaout->Init.BufferTransferLength;
03057
03058   if((hjpeg->InDataLength < inXfrSize) || (hjpeg->OutDataLength < outXfrSize))
03059   {
03060     return HAL_ERROR;
03061   }
03062   /* Set the JPEG MDMA In transfer complete callback */
03063   hjpeg->hdmain->XferCpltCallback = JPEG_MDMAInCpltCallback;
03064   /* Set the MDMA In error callback */
03065   hjpeg->hdmain->XferErrorCallback = JPEG_MDMAErrorCallback;
03066
03067   /* Set the JPEG MDMA Out transfer complete callback */
03068   hjpeg->hdmaout->XferCpltCallback = JPEG_MDMAOutCpltCallback;
03069   /* Set the MDMA In error callback */
03070   hjpeg->hdmaout->XferErrorCallback = JPEG_MDMAErrorCallback;
03071   /* Set the MDMA Out Abort callback */
03072   hjpeg->hdmaout->XferAbortCallback = JPEG_MDMAOutAbortCallback;
03073
03074   /*MDMA transfer size (BNDTR) must be a multiple of MDMA buffer size (TLEN)*/
03075   hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % inXfrSize);
03076
03077   /*MDMA transfer size (BNDTR) must be a multiple of MDMA buffer size (TLEN)*/
03078   hjpeg->OutDataLength = hjpeg->OutDataLength - (hjpeg->OutDataLength % outXfrSize);
03079
03080
03081   /* Start MDMA FIFO Out transfer */
03082   HAL_MDMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength, 1);
03083
03084   /* Start DMA FIFO In transfer */
03085   HAL_MDMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, hjpeg->InDataLength, 1);
03086
03087   return HAL_OK;
03088 }
03089
03090 /**
03091   * @brief  Continue the current JPEG DMA process (encoding/decoding)
03092   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
03093   *         the configuration information for JPEG module
03094   * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING
03095   */
03096 static uint32_t JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg)
03097 {
03098   /*End of header processing flag rises*/
03099   if(((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) && (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != RESET))
03100   {
03101     /*Call Header parsing complete callback */
03102     HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf);
03103
03104     /* Reset the ImageQuality */
03105     hjpeg->Conf.ImageQuality = 0;
03106     /* Note : the image quality is only available at the end of the decoding operation */
03107     /* at the current stage the calculated image quality is not correct so reset it */
03108
03109     /*Call Info Ready callback */
03110     HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf);
03111
03112     __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_IT_HPD);
03113
03114     /* Clear header processing done flag */
03115     __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_HPDF);
03116   }
03117
03118   /*End of Conversion handling*/
03119   if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) != RESET)
03120   {
03121     hjpeg->Context |= JPEG_CONTEXT_ENDING_DMA;
03122
03123     /*Stop Encoding/Decoding*/
03124     hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
03125
03126     __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
03127
03128     /* Clear all flags */
03129     __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);
03130
03131
03132     if(hjpeg->hdmain->State == HAL_MDMA_STATE_BUSY)
03133     {
03134       /* Stop the MDMA In Xfer*/
03135       HAL_MDMA_Abort_IT(hjpeg->hdmain);
03136     }
03137
03138     if(hjpeg->hdmaout->State == HAL_MDMA_STATE_BUSY)
03139     {
03140       /* Stop the MDMA out Xfer*/
03141       HAL_MDMA_Abort_IT(hjpeg->hdmaout);
03142     }
03143     else
03144     {
03145       return JPEG_DMA_EndProcess(hjpeg);
03146     }
03147   }
03148
03149   return JPEG_PROCESS_ONGOING;
03150 }
03151
03152 /**
03153   * @brief  Finalize the current JPEG DMA process (encoding/decoding)
03154   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
03155   *         the configuration information for JPEG module
03156   * @retval JPEG_PROCESS_DONE
03157   */
03158 static uint32_t JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg)
03159 {
03160   uint32_t tmpContext;
03161   hjpeg->JpegOutCount = hjpeg->OutDataLength - (hjpeg->hdmaout->Instance->CBNDTR & MDMA_CBNDTR_BNDT);
03162
03163   /*if Output Buffer is full, call HAL_JPEG_DataReadyCallback*/
03164   if(hjpeg->JpegOutCount == hjpeg->OutDataLength)
03165   {
03166     HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
03167     hjpeg->JpegOutCount = 0;
03168   }
03169
03170   /*Check if remaining data in the output FIFO*/
03171   if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) == 0)
03172   {
03173     if(hjpeg->JpegOutCount > 0)
03174     {
03175       /*Output Buffer is not empty, call DecodedDataReadyCallback*/
03176       HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
03177       hjpeg->JpegOutCount = 0;
03178     }
03179
03180     /*Stop Encoding/Decoding*/
03181     hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
03182
03183     tmpContext = hjpeg->Context;
03184     /*Clear all context fileds execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
03185     hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);
03186
03187     /* Process Unlocked */
03188     __HAL_UNLOCK(hjpeg);
03189
03190     /* Change the JPEG state */
03191     hjpeg->State = HAL_JPEG_STATE_READY;
03192
03193     /*Call End of Encoding/Decoding callback */
03194     if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
03195     {
03196       HAL_JPEG_DecodeCpltCallback(hjpeg);
03197     }
03198     else if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE)
03199     {
03200       HAL_JPEG_EncodeCpltCallback(hjpeg);
03201     }
03202   }
03203   else if((hjpeg->Context &  JPEG_CONTEXT_PAUSE_OUTPUT) == 0)
03204   {
03205     JPEG_DMA_PollResidualData(hjpeg);
03206
03207     return JPEG_PROCESS_DONE;
03208   }
03209
03210   return JPEG_PROCESS_ONGOING;
03211 }
03212
03213 /**
03214   * @brief  Poll residual output data when DMA process (encoding/decoding)
03215   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
03216   *         the configuration information for JPEG module
03217   * @retval None.
03218   */
03219 static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg)
03220 {
03221   uint32_t tmpContext, count = JPEG_FIFO_SIZE, dataOut;
03222
03223   while((__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0) && (count > 0) && ((hjpeg->Context &  JPEG_CONTEXT_PAUSE_OUTPUT) == 0))
03224   {
03225     count--;
03226
03227     dataOut = hjpeg->Instance->DOR;
03228     hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = dataOut & 0x000000FF;
03229     hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1] = (dataOut & 0x0000FF00) >> 8;
03230     hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2] = (dataOut & 0x00FF0000) >> 16;
03231     hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3] = (dataOut & 0xFF000000) >> 24;
03232     hjpeg->JpegOutCount += 4;
03233
03234     if(hjpeg->JpegOutCount == hjpeg->OutDataLength)
03235     {
03236       /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/
03237       HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
03238       hjpeg->JpegOutCount = 0;
03239     }
03240   }
03241
03242   if((hjpeg->Context &  JPEG_CONTEXT_PAUSE_OUTPUT) == 0)
03243   {
03244     /*Stop Encoding/Decoding*/
03245     hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
03246
03247     if(hjpeg->JpegOutCount > 0)
03248     {
03249       /*Output Buffer is not empty, call DecodedDataReadyCallback*/
03250       HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
03251       hjpeg->JpegOutCount = 0;
03252     }
03253
03254     tmpContext = hjpeg->Context;
03255     /*Clear all context fileds execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
03256     hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);
03257
03258     /* Process Unlocked */
03259     __HAL_UNLOCK(hjpeg);
03260
03261     /* Change the JPEG state */
03262     hjpeg->State = HAL_JPEG_STATE_READY;
03263
03264     /*Call End of Encoding/Decoding callback */
03265     if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
03266     {
03267       HAL_JPEG_DecodeCpltCallback(hjpeg);
03268     }
03269     else if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE)
03270     {
03271       HAL_JPEG_EncodeCpltCallback(hjpeg);
03272     }
03273   }
03274 }
03275
03276 /**
03277   * @brief  DMA input transfer complete callback
03278   * @param  hmdma: pointer to a DMA_HandleTypeDef structure.
03279   * @retval None
03280   */
03281 static void JPEG_MDMAInCpltCallback(MDMA_HandleTypeDef *hmdma)
03282 {
03283   uint32_t inXfrSize;
03284
03285   JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((MDMA_HandleTypeDef*)hmdma)->Parent;
03286
03287   /* Disable The JPEG IT so the DMA Input Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */
03288   __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
03289
03290   if(((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) && ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) == 0))
03291   {
03292
03293     /*if the MDMA In is triggred with JPEG In FIFO Threshold flag
03294       then MDMA In buffer size is 32 bytes
03295       else (MDMA In is triggred with JPEG In FIFO not full flag)
03296       then MDMA In buffer size is 4 bytes
03297     */
03298     inXfrSize = hjpeg->hdmain->Init.BufferTransferLength;
03299
03300     hjpeg->JpegInCount = hjpeg->InDataLength - (hmdma->Instance->CBNDTR & MDMA_CBNDTR_BNDT);
03301
03302     /*Call HAL_JPEG_GetDataCallback to get new data */
03303     HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount);
03304
03305
03306     if(hjpeg->InDataLength >= inXfrSize)
03307     {
03308       /*JPEG Input DMA transfer data number must be multiple of MDMA buffer size
03309         as the destination is a 32 bits register */
03310       hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % inXfrSize);
03311
03312     }
03313     else if(hjpeg->InDataLength > 0)
03314     {
03315       /* Transfer the remaining Data, must be multiple of source data size (byte) and destination data size (word) */
03316       if((hjpeg->InDataLength % 4) != 0)
03317       {
03318         hjpeg->InDataLength = ((hjpeg->InDataLength / 4) + 1) * 4;
03319       }
03320     }
03321
03322     if(((hjpeg->Context &  JPEG_CONTEXT_PAUSE_INPUT) == 0) && (hjpeg->InDataLength > 0))
03323     {
03324       /* Start MDMA FIFO In transfer */
03325       HAL_MDMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, hjpeg->InDataLength, 1);
03326     }
03327
03328     /* JPEG Conversion still on going : Enable the JPEG IT */
03329     __HAL_JPEG_ENABLE_IT(hjpeg,JPEG_IT_EOC |JPEG_IT_HPD);
03330   }
03331 }
03332
03333 /**
03334   * @brief  DMA output transfer complete callback
03335   * @param  hmdma: pointer to a DMA_HandleTypeDef structure.
03336   * @retval None
03337   */
03338 static void JPEG_MDMAOutCpltCallback(MDMA_HandleTypeDef *hmdma)
03339 {
03340   JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((MDMA_HandleTypeDef*)hmdma)->Parent;
03341
03342
03343   /* Disable The JPEG IT so the DMA Output Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */
03344   __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
03345
03346   if(((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) && ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) == 0))
03347   {
03348     if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) == 0)
03349     {
03350       hjpeg->JpegOutCount = hjpeg->OutDataLength - (hmdma->Instance->CBNDTR & MDMA_CBNDTR_BNDT);
03351
03352       /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/
03353       HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
03354
03355       if((hjpeg->Context &  JPEG_CONTEXT_PAUSE_OUTPUT) == 0)
03356       {
03357         /* Start MDMA FIFO Out transfer */
03358         HAL_MDMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength, 1);
03359       }
03360     }
03361
03362     /* JPEG Conversion still on going : Enable the JPEG IT */
03363     __HAL_JPEG_ENABLE_IT(hjpeg,JPEG_IT_EOC |JPEG_IT_HPD);
03364   }
03365 }
03366
03367 /**
03368   * @brief  DMA Transfer error callback
03369   * @param  hmdma: pointer to a DMA_HandleTypeDef structure.
03370   * @retval None
03371   */
03372 static void JPEG_MDMAErrorCallback(MDMA_HandleTypeDef *hmdma)
03373 {
03374   JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((MDMA_HandleTypeDef*)hmdma)->Parent;
03375
03376   /*Stop Encoding/Decoding*/
03377   hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
03378
03379   /* Disable All Interrupts */
03380   __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
03381
03382   hjpeg->State= HAL_JPEG_STATE_READY;
03383   hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
03384   HAL_JPEG_ErrorCallback(hjpeg);
03385 }
03386
03387 /**
03388   * @brief  DMA output Abort callback
03389   * @param  hmdma: pointer to a DMA_HandleTypeDef structure.
03390   * @retval None
03391   */
03392 static void JPEG_MDMAOutAbortCallback(MDMA_HandleTypeDef *hmdma)
03393 {
03394   JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((MDMA_HandleTypeDef*)hmdma)->Parent;
03395
03396   if((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0)
03397   {
03398     JPEG_DMA_EndProcess(hjpeg);
03399   }
03400 }
03401
03402 /**
03403   * @brief  Calculate the decoded image quality (from 1 to 100)
03404   * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
03405   *         the configuration information for JPEG module
03406   * @retval JPEG image quality from 1 to 100.
03407   */
03408 static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg)
03409 {
03410   uint32_t quality = 0;
03411   uint32_t quantRow, quantVal,scale, i, j;
03412   __IO uint32_t *tableAddress = hjpeg->Instance->QMEM0;
03413
03414   i = 0;
03415   while( i < JPEG_QUANT_TABLE_SIZE)
03416   {
03417     quantRow = *tableAddress;
03418     for(j=0; j<4; j++)
03419     {
03420       quantVal = (quantRow >> (8 * j)) & 0xFF;
03421       if(quantVal == 1)
03422       {
03423         /* if Quantization value = 1 then quality is 100%*/
03424         quality += 100;
03425       }
03426       else
03427       {
03428         /* Note that the quantization coefficients must be specified in the table in zigzag order */
03429         scale = (quantVal*100)/((uint32_t) JPEG_LUM_QuantTable[JPEG_ZIGZAG_ORDER[i+j]]);
03430
03431         if(scale <= 100)
03432         {
03433           quality += (200 - scale)/2;
03434         }
03435         else
03436         {
03437           quality += 5000/scale;
03438         }
03439       }
03440     }
03441
03442     i += 4;
03443     tableAddress ++;
03444   }
03445
03446   return (quality/((uint32_t)64));
03447 }
03448 /**
03449   * @}
03450   */
03451
03452 #endif /* HAL_JPEG_MODULE_ENABLED */
03453 /**
03454   * @}
03455   */
03456
03457 /**
03458   * @}
03459   */
03460
03461 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_jpeg.h Source File

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stm32h7xx_hal_jpeg.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_jpeg.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of JPEG HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_JPEG_H
00040 #define __STM32H7xx_HAL_JPEG_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048 #include "stm32h7xx_hal_mdma.h"
00049
00050 /** @addtogroup STM32H7xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup JPEG
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup JPEG_Exported_Types JPEG Exported Types
00060   * @{
00061   */
00062
00063 /** @defgroup JPEG_Configuration_Structure_definition JPEG Configuration for encoding Structure definition
00064   * @brief  JPEG encoding configuration Structure definition
00065   * @{
00066   */
00067 typedef struct
00068 {
00069   uint8_t  ColorSpace;                /*!< Image Color space : gray-scale, YCBCR, RGB or CMYK
00070                                            This parameter can be a value of @ref JPEG_ColorSpace */
00071
00072   uint8_t  ChromaSubsampling;         /*!< Chroma Subsampling in case of YCBCR or CMYK color space, 0-> 4:4:4 , 1-> 4:2:2, 2 -> 4:1:1, 3 -> 4:2:0
00073                                            This parameter can be a value of @ref JPEG_ChromaSubsampling */
00074
00075   uint32_t ImageHeight;               /*!< Image height : number of lines */
00076
00077   uint32_t ImageWidth;                /*!< Image width : number of pixels per line */
00078
00079   uint8_t  ImageQuality;               /*!< Quality of the JPEG encoding : from 1 to 100 */
00080
00081 }JPEG_ConfTypeDef;
00082 /**
00083   * @}
00084   */
00085
00086 /** @defgroup HAL_JPEG_state_structure_definition HAL JPEG state structure definition
00087   * @brief  HAL JPEG State structure definition
00088   * @{
00089   */
00090 typedef enum
00091 {
00092   HAL_JPEG_STATE_RESET              = 0x00U,  /*!< JPEG not yet initialized or disabled  */
00093   HAL_JPEG_STATE_READY              = 0x01U,  /*!< JPEG initialized and ready for use    */
00094   HAL_JPEG_STATE_BUSY               = 0x02U,  /*!< JPEG internal processing is ongoing   */
00095   HAL_JPEG_STATE_BUSY_ENCODING      = 0x03U,  /*!< JPEG encoding processing is ongoing   */
00096   HAL_JPEG_STATE_BUSY_DECODING      = 0x04U,  /*!< JPEG decoding processing is ongoing   */
00097   HAL_JPEG_STATE_TIMEOUT            = 0x05U,  /*!< JPEG timeout state                    */
00098   HAL_JPEG_STATE_ERROR              = 0x06U   /*!< JPEG error state                      */
00099 }HAL_JPEG_STATETypeDef;
00100
00101 /**
00102   * @}
00103   */
00104
00105
00106 /** @defgroup JPEG_handle_Structure_definition JPEG handle Structure definition
00107   * @brief  JPEG handle Structure definition
00108   * @{
00109   */
00110 typedef struct
00111 {
00112   JPEG_TypeDef             *Instance;        /*!< JPEG peripheral register base address */
00113
00114   JPEG_ConfTypeDef         Conf;             /*!< Current JPEG encoding/decoding parameters */
00115
00116   uint8_t                  *pJpegInBuffPtr;  /*!< Pointer to JPEG processing (encoding, decoding,...) input buffer */
00117
00118   uint8_t                  *pJpegOutBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) output buffer */
00119
00120   __IO uint32_t            JpegInCount;      /*!< Internal Counter of input data */
00121
00122   __IO uint32_t            JpegOutCount;     /*!< Internal Counter of output data */
00123
00124   uint32_t                 InDataLength;     /*!< Input Buffer Length in Bytes */
00125
00126   uint32_t                 OutDataLength;    /*!< Output Buffer Length in Bytes */
00127
00128   MDMA_HandleTypeDef        *hdmain;          /*!< JPEG In MDMA handle parameters */
00129
00130   MDMA_HandleTypeDef        *hdmaout;         /*!< JPEG Out MDMA handle parameters */
00131
00132   uint8_t                  CustomQuanTable;  /*!< If set to 1 specify that user customized quantization tables are used */
00133
00134   uint8_t                  *QuantTable0;     /*!< Basic Quantization Table for component 0 */
00135
00136   uint8_t                  *QuantTable1;     /*!< Basic Quantization Table for component 1 */
00137
00138   uint8_t                  *QuantTable2;     /*!< Basic Quantization Table for component 2 */
00139
00140   uint8_t                  *QuantTable3;     /*!< Basic Quantization Table for component 3 */
00141
00142   HAL_LockTypeDef          Lock;             /*!< JPEG locking object */
00143
00144   __IO  HAL_JPEG_STATETypeDef State;         /*!< JPEG peripheral state */
00145
00146   __IO  uint32_t           ErrorCode;        /*!< JPEG Error code */
00147
00148   __IO uint32_t Context;                     /*!< JPEG Internal context */
00149
00150 }JPEG_HandleTypeDef;
00151
00152 /**
00153   * @}
00154   */
00155
00156 /**
00157   * @}
00158   */
00159
00160 /* Exported constants --------------------------------------------------------*/
00161
00162 /** @defgroup JPEG_Exported_Constants JPEG Exported Constants
00163   * @{
00164   */
00165
00166 /** @defgroup JPEG_Error_Code_definition JPEG Error Code definition
00167   * @brief  JPEG Error Code definition
00168   * @{
00169   */
00170
00171 #define  HAL_JPEG_ERROR_NONE        ((uint32_t)0x00000000U)    /*!< No error             */
00172 #define  HAL_JPEG_ERROR_HUFF_TABLE  ((uint32_t)0x00000001U)    /*!< HUffman Table programming error */
00173 #define  HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U)    /*!< Quantization Table programming error */
00174 #define  HAL_JPEG_ERROR_DMA         ((uint32_t)0x00000004U)    /*!< DMA transfer error   */
00175 #define  HAL_JPEG_ERROR_TIMEOUT     ((uint32_t)0x00000008U)    /*!< Timeout error        */
00176
00177 /**
00178   * @}
00179   */
00180
00181 /** @defgroup JPEG_Quantization_Table_Size JPEG Quantization Table Size
00182   * @brief  JPEG Quantization Table Size
00183   * @{
00184   */
00185 #define JPEG_QUANT_TABLE_SIZE  ((uint32_t)64U) /*!< JPEG Quantization Table Size in bytes  */
00186 /**
00187   * @}
00188   */
00189
00190
00191 /** @defgroup JPEG_ColorSpace JPEG ColorSpace
00192   * @brief  JPEG Color Space
00193   * @{
00194   */
00195 #define JPEG_GRAYSCALE_COLORSPACE     ((uint32_t)0x00000000U)
00196 #define JPEG_YCBCR_COLORSPACE         JPEG_CONFR1_COLORSPACE_0
00197 #define JPEG_CMYK_COLORSPACE          JPEG_CONFR1_COLORSPACE
00198
00199
00200 /**
00201   * @}
00202   */
00203
00204
00205 /** @defgroup JPEG_ChromaSubsampling JPEG Chrominance Sampling
00206   * @brief  JPEG Chrominance Sampling
00207   * @{
00208   */
00209 #define JPEG_444_SUBSAMPLING     ((uint32_t)0x00000000U)   /*!< Chroma Subsampling 4:4:4 */
00210 #define JPEG_420_SUBSAMPLING     ((uint32_t)0x00000001U)   /*!< Chroma Subsampling 4:2:0 */
00211 #define JPEG_422_SUBSAMPLING     ((uint32_t)0x00000002U)   /*!< Chroma Subsampling 4:2:2 */
00212
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup JPEG_ImageQuality JPEG Image Quality
00218   * @brief  JPEG Min and Max Image Quality
00219   * @{
00220   */
00221 #define JPEG_IMAGE_QUALITY_MIN     ((uint32_t)1U)     /*!< Minimum JPEG quality */
00222 #define JPEG_IMAGE_QUALITY_MAX     ((uint32_t)100U)   /*!< Maximum JPEG quality */
00223
00224 /**
00225   * @}
00226   */
00227
00228 /** @defgroup JPEG_Interrupt_configuration_definition JPEG Interrupt configuration definition
00229   * @brief JPEG Interrupt definition
00230   * @{
00231   */
00232 #define JPEG_IT_IFT     ((uint32_t)JPEG_CR_IFTIE)   /*!< Input FIFO Threshold Interrupt */
00233 #define JPEG_IT_IFNF    ((uint32_t)JPEG_CR_IFNFIE)  /*!< Input FIFO Not Full Interrupt */
00234 #define JPEG_IT_OFT     ((uint32_t)JPEG_CR_OFTIE)   /*!< Output FIFO Threshold Interrupt */
00235 #define JPEG_IT_OFNE    ((uint32_t)JPEG_CR_OFTIE)   /*!< Output FIFO Not Empty Interrupt */
00236 #define JPEG_IT_EOC     ((uint32_t)JPEG_CR_EOCIE)   /*!< End of Conversion Interrupt */
00237 #define JPEG_IT_HPD     ((uint32_t)JPEG_CR_HPDIE)   /*!< Header Parsing Done Interrupt */
00238 /**
00239   * @}
00240   */
00241
00242 /** @defgroup JPEG_Flag_definition JPEG Flag definition
00243   * @brief JPEG Flags definition
00244   * @{
00245   */
00246 #define JPEG_FLAG_IFTF     ((uint32_t)JPEG_SR_IFTF)   /*!< Input FIFO is not full and is bellow its threshold flag */
00247 #define JPEG_FLAG_IFNFF    ((uint32_t)JPEG_SR_IFNFF)  /*!< Input FIFO Not Full Flag, a data can be written */
00248 #define JPEG_FLAG_OFTF     ((uint32_t)JPEG_SR_OFTF)   /*!< Output FIFO is not empty and has reach its threshold */
00249 #define JPEG_FLAG_OFNEF    ((uint32_t)JPEG_SR_OFNEF)  /*!< Output FIFO is not empty, a data is available  */
00250 #define JPEG_FLAG_EOCF     ((uint32_t)JPEG_SR_EOCF)   /*!< JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO  */
00251 #define JPEG_FLAG_HPDF     ((uint32_t)JPEG_SR_HPDF)   /*!< JPEG Codec has finished the parsing of the headers and the internal registers have been updated  */
00252 #define JPEG_FLAG_COF      ((uint32_t)JPEG_SR_COF)    /*!< JPEG Codec operation on going  flag*/
00253
00254 #define JPEG_FLAG_ALL      ((uint32_t)0x000000FEU)     /*!< JPEG Codec All previous flag*/
00255 /**
00256   * @}
00257   */
00258
00259 /** @defgroup JPEG_PROCESS_PAUSE_RESUME_definition JPEG Process Pause Resume definition
00260   * @brief JPEG process pause, resume definition
00261   * @{
00262   */
00263 #define JPEG_PAUSE_RESUME_INPUT          ((uint32_t)0x00000001U)     /*!< Pause/Resume Input FIFO Xfer*/
00264 #define JPEG_PAUSE_RESUME_OUTPUT         ((uint32_t)0x00000002U)     /*!< Pause/Resume Output FIFO Xfer*/
00265 #define JPEG_PAUSE_RESUME_INPUT_OUTPUT   ((uint32_t)0x00000003U)     /*!< Pause/Resume Input and Output FIFO Xfer*/
00266 /**
00267   * @}
00268   */
00269
00270 /**
00271   * @}
00272   */
00273 /* Exported macro ------------------------------------------------------------*/
00274
00275 /** @defgroup JPEG_Exported_Macros JPEG Exported Macros
00276   * @{
00277   */
00278
00279 /** @brief Reset JPEG handle state
00280   * @param  __HANDLE__: specifies the JPEG handle.
00281   * @retval None
00282   */
00283 #define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_JPEG_STATE_RESET)
00284
00285
00286 /**
00287   * @brief  Enable the JPEG peripheral.
00288   * @param  __HANDLE__: specifies the JPEG handle.
00289   * @retval None
00290   */
00291 #define __HAL_JPEG_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  JPEG_CR_JCEN)
00292
00293 /**
00294   * @brief Disable the JPEG peripheral.
00295   * @param  __HANDLE__: specifies the JPEG handle.
00296   * @retval None
00297   */
00298 #define __HAL_JPEG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~JPEG_CR_JCEN)
00299
00300
00301 /**
00302   * @brief  Check the specified JPEG status flag.
00303   * @param  __HANDLE__: specifies the JPEG handle.
00304   * @param  __FLAG__ : specifies the flag to check
00305   *         This parameter can be one of the following values:
00306   *         @arg JPEG_FLAG_IFTF  : The input FIFO is not full and is bellow its threshold flag
00307   *         @arg JPEG_FLAG_IFNFF : The input FIFO Not Full Flag, a data can be written
00308   *         @arg JPEG_FLAG_OFTF  : The output FIFO is not empty and has reach its threshold
00309   *         @arg JPEG_FLAG_OFNEF : The output FIFO is not empty, a data is available
00310   *         @arg JPEG_FLAG_EOCF  : JPEG Codec core has finished the encoding or the decoding process
00311   *                                and than last data has been sent to the output FIFO
00312   *         @arg JPEG_FLAG_HPDF  : JPEG Codec has finished the parsing of the headers
00313   *                                and the internal registers have been updated
00314   *         @arg JPEG_FLAG_COF   : JPEG Codec operation on going  flag
00315   *
00316   * @retval : __HAL_JPEG_GET_FLAG : returns The new state of __FLAG__ (TRUE or FALSE)
00317   */
00318
00319 #define __HAL_JPEG_GET_FLAG(__HANDLE__,__FLAG__)  (((__HANDLE__)->Instance->SR & (__FLAG__)))
00320
00321 /**
00322   * @brief  Clear the specified JPEG status flag.
00323   * @param  __HANDLE__: specifies the JPEG handle.
00324   * @param  __FLAG__ : specifies the flag to clear
00325   *         This parameter can be one of the following values:
00326   *         @arg JPEG_FLAG_EOCF  : JPEG Codec core has finished the encoding or the decoding process
00327   *                                and than last data has been sent to the output FIFO
00328   *         @arg JPEG_FLAG_HPDF  : JPEG Codec has finished the parsing of the headers
00329   * @retval : None
00330   */
00331
00332 #define __HAL_JPEG_CLEAR_FLAG(__HANDLE__,__FLAG__)  (((__HANDLE__)->Instance->CFR |= ((__FLAG__) & (JPEG_FLAG_EOCF | JPEG_FLAG_HPDF))))
00333
00334
00335 /**
00336   * @brief  Enable Interrupt.
00337   * @param   __HANDLE__: specifies the JPEG handle.
00338   * @param  __INTERRUPT__ : specifies the interrupt to enable
00339   *         This parameter can be one of the following values:
00340   *         @arg JPEG_IT_IFT   : Input FIFO Threshold Interrupt
00341   *         @arg JPEG_IT_IFNF  : Input FIFO Not Full Interrupt
00342   *         @arg JPEG_IT_OFT   : Output FIFO Threshold Interrupt
00343   *         @arg JPEG_IT_OFNE  : Output FIFO Not empty Interrupt
00344   *         @arg JPEG_IT_EOC   : End of Conversion Interrupt
00345   *         @arg JPEG_IT_HPD   : Header Parsing Done Interrupt
00346   *
00347   * @retval : No retrun
00348   */
00349 #define __HAL_JPEG_ENABLE_IT(__HANDLE__,__INTERRUPT__)  ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) )
00350
00351 /**
00352   * @brief  Disable Interrupt.
00353   * @param   __HANDLE__: specifies the JPEG handle.
00354   * @param  __INTERRUPT__ : specifies the interrupt to disable
00355   *         This parameter can be one of the following values:
00356   *         @arg JPEG_IT_IFT   : Input FIFO Threshold Interrupt
00357   *         @arg JPEG_IT_IFNF  : Input FIFO Not Full Interrupt
00358   *         @arg JPEG_IT_OFT   : Output FIFO Threshold Interrupt
00359   *         @arg JPEG_IT_OFNE  : Output FIFO Not empty Interrupt
00360   *         @arg JPEG_IT_EOC   : End of Conversion Interrupt
00361   *         @arg JPEG_IT_HPD   : Header Parsing Done Interrupt
00362   *
00363   * @note  : To disable an IT we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits
00364   *          located in the same IT enable register (CR register).
00365   * @retval : No retrun
00366   */
00367 #define __HAL_JPEG_DISABLE_IT(__HANDLE__,__INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0)
00368
00369
00370 /**
00371   * @brief  Get Interrupt state.
00372   * @param   __HANDLE__: specifies the JPEG handle.
00373   * @param  __INTERRUPT__ : specifies the interrupt to check
00374   *         This parameter can be one of the following values:
00375   *         @arg JPEG_IT_IFT   : Input FIFO Threshold Interrupt
00376   *         @arg JPEG_IT_IFNF  : Input FIFO Not Full Interrupt
00377   *         @arg JPEG_IT_OFT   : Output FIFO Threshold Interrupt
00378   *         @arg JPEG_IT_OFNE  : Output FIFO Not empty Interrupt
00379   *         @arg JPEG_IT_EOC   : End of Conversion Interrupt
00380   *         @arg JPEG_IT_HPD   : Header Parsing Done Interrupt
00381   *
00382   * @retval : returns The new state of __INTERRUPT__ (Enabled or disabled)
00383   */
00384 #define __HAL_JPEG_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__)     ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
00385
00386 /**
00387   * @}
00388   */
00389
00390 /* Exported functions --------------------------------------------------------*/
00391 /** @addtogroup JPEG_Exported_Functions
00392   * @{
00393   */
00394
00395 /** @addtogroup JPEG_Exported_Functions_Group1
00396   * @{
00397   */
00398 /* Initialization/de-initialization functions  ********************************/
00399 HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg);
00400 HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg);
00401 void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg);
00402 void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg);
00403
00404 /**
00405   * @}
00406   */
00407
00408 /** @addtogroup JPEG_Exported_Functions_Group2
00409   * @{
00410   */
00411 /* Encoding/Decoding Configuration functions  ********************************/
00412 HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf);
00413 HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo);
00414 HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg);
00415 HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg);
00416 HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, uint8_t *QTable2, uint8_t *QTable3);
00417
00418 /**
00419   * @}
00420   */
00421
00422 /** @addtogroup JPEG_Exported_Functions_Group3
00423   * @{
00424   */
00425 /* JPEG processing functions  **************************************/
00426 HAL_StatusTypeDef  HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout);
00427 HAL_StatusTypeDef  HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength, uint32_t Timeout);
00428 HAL_StatusTypeDef  HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength);
00429 HAL_StatusTypeDef  HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength);
00430 HAL_StatusTypeDef  HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength);
00431 HAL_StatusTypeDef  HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength);
00432 HAL_StatusTypeDef  HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);
00433 HAL_StatusTypeDef  HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);
00434 void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength);
00435 void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength);
00436 HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg);
00437
00438 /**
00439   * @}
00440   */
00441
00442 /** @addtogroup JPEG_Exported_Functions_Group4
00443   * @{
00444   */
00445 /* JPEG Decode/Encode callback functions  ********************************************************/
00446 void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg,JPEG_ConfTypeDef *pInfo);
00447 void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg);
00448 void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg);
00449 void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg);
00450 void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData);
00451 void HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength);
00452
00453 /**
00454   * @}
00455   */
00456
00457 /** @addtogroup JPEG_Exported_Functions_Group5
00458   * @{
00459   */
00460 /* JPEG IRQ handler management  ******************************************************/
00461 void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg);
00462
00463 /**
00464   * @}
00465   */
00466
00467 /** @addtogroup JPEG_Exported_Functions_Group6
00468   * @{
00469   */
00470 /* Peripheral State and Error functions  ************************************************/
00471 HAL_JPEG_STATETypeDef  HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg);
00472 uint32_t              HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg);
00473
00474 /**
00475   * @}
00476   */
00477
00478 /**
00479   * @}
00480   */
00481
00482 /* Private types -------------------------------------------------------------*/
00483 /** @defgroup JPEG_Private_Types JPEG Private Types
00484   * @{
00485   */
00486
00487 /**
00488   * @}
00489   */
00490
00491 /* Private defines -----------------------------------------------------------*/
00492 /** @defgroup JPEG_Private_Defines JPEG Private Defines
00493   * @{
00494   */
00495
00496 /**
00497   * @}
00498   */
00499
00500 /* Private variables ---------------------------------------------------------*/
00501 /** @defgroup JPEG_Private_Variables JPEG Private Variables
00502   * @{
00503   */
00504
00505 /**
00506   * @}
00507   */
00508
00509 /* Private constants ---------------------------------------------------------*/
00510 /** @defgroup JPEG_Private_Constants JPEG Private Constants
00511   * @{
00512   */
00513
00514 /**
00515   * @}
00516   */
00517
00518 /* Private macros ------------------------------------------------------------*/
00519 /** @defgroup JPEG_Private_Macros JPEG Private Macros
00520   * @{
00521   */
00522
00523 #define IS_JPEG_CHROMASUBSAMPLING(SUBSAMPLING) (((SUBSAMPLING) == JPEG_444_SUBSAMPLING) || \
00524                                                 ((SUBSAMPLING) == JPEG_420_SUBSAMPLING) || \
00525                                                 ((SUBSAMPLING) == JPEG_422_SUBSAMPLING))
00526
00527 #define IS_JPEG_IMAGE_QUALITY(NUMBER) (((NUMBER) >= JPEG_IMAGE_QUALITY_MIN) && ((NUMBER) <= JPEG_IMAGE_QUALITY_MAX))
00528
00529 #define IS_JPEG_COLORSPACE(COLORSPACE) (((COLORSPACE) == JPEG_GRAYSCALE_COLORSPACE) || \
00530                                         ((COLORSPACE) == JPEG_YCBCR_COLORSPACE)     || \
00531                                         ((COLORSPACE) == JPEG_CMYK_COLORSPACE))
00532
00533 #define IS_JPEG_PAUSE_RESUME_STATE(VALUE) (((VALUE) == JPEG_PAUSE_RESUME_INPUT) || \
00534                                            ((VALUE) == JPEG_PAUSE_RESUME_OUTPUT)|| \
00535                                            ((VALUE) == JPEG_PAUSE_RESUME_INPUT_OUTPUT))
00536
00537 /**
00538   * @}
00539   */
00540
00541 /* Private functions prototypes ----------------------------------------------*/
00542 /** @defgroup JPEG_Private_Functions_Prototypes JPEG Private Functions Prototypes
00543   * @{
00544   */
00545
00546 /**
00547   * @}
00548   */
00549
00550 /* Private functions ---------------------------------------------------------*/
00551 /** @defgroup JPEG_Private_Functions JPEG Private Functions
00552   * @{
00553   */
00554
00555 /**
00556   * @}
00557   */
00558
00559 /**
00560   * @}
00561   */
00562
00563 /**
00564   * @}
00565   */
00566 #ifdef __cplusplus
00567 }
00568 #endif
00569
00570 #endif /* __STM32H7xx_HAL_JPEG_H */
00571
00572 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_lptim.c Source File

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stm32h7xx_hal_lptim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_lptim.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   LPTIM HAL module driver.
00008   *
00009   *          This file provides firmware functions to manage the following
00010   *          functionalities of the Low Power Timer (LPTIM) peripheral:
00011   *           + Initialization and de-initialization functions.
00012   *           + Start/Stop operation functions in polling mode.
00013   *           + Start/Stop operation functions in interrupt mode.
00014   *           + Reading operation functions.
00015   *           + Peripheral State functions.
00016   *
00017   @verbatim
00018   ==============================================================================
00019                      ##### How to use this driver #####
00020   ==============================================================================
00021     [..]
00022       The LPTIM HAL driver can be used as follows:
00023
00024       (#)Initialize the LPTIM low level resources by implementing the
00025         HAL_LPTIM_MspInit():
00026          (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
00027          (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
00028              (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
00029              (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
00030              (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
00031
00032       (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
00033          configures mainly:
00034          (++) The instance: LPTIM1 or LPTIM2.
00035          (++) Clock: the counter clock.
00036                  (+++) Source   : it can be either the ULPTIM input (IN1) or one of
00037                               the internal clock; (APB, LSE, LSI or MSI).
00038                  (+++) Prescaler: select the clock divider.
00039          (++)  UltraLowPowerClock : To be used only if the ULPTIM is selected
00040                as counter clock source.
00041                  (+++) Polarity:   polarity of the active edge for the counter unit
00042                                if the ULPTIM input is selected.
00043                  (+++) SampleTime: clock sampling time to configure the clock glitch
00044                                filter.
00045          (++) Trigger: How the counter start.
00046                  (+++) Source: trigger can be software or one of the hardware triggers.
00047                  (+++) ActiveEdge : only for hardware trigger.
00048                  (+++) SampleTime : trigger sampling time to configure the trigger
00049                                 glitch filter.
00050          (++) OutputPolarity : 2 opposite polarities are possibles.
00051          (++) UpdateMode: specifies whether the update of the autoreload and
00052               the compare values is done immediately or after the end of current
00053               period.
00054          (++) Input1Source: Source selected for input1 (GPIO or comparator output).
00055          (++) Input2Source: Source selected for input2 (GPIO or comparator output).
00056               Input2 is used only for encoder feature so is used only for LPTIM1 instance.
00057
00058       (#)Six modes are available:
00059
00060          (++) PWM Mode: To generate a PWM signal with specified period and pulse,
00061          call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
00062          mode.
00063
00064          (++) One Pulse Mode: To generate pulse with specified width in response
00065          to a stimulus, call HAL_LPTIM_OnePulse_Start() or
00066          HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
00067
00068          (++) Set once Mode: In this mode, the output changes the level (from
00069          low level to high level if the output polarity is configured high, else
00070          the opposite) when a compare match occurs. To start this mode, call
00071          HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
00072          interruption mode.
00073
00074          (++) Encoder Mode: To use the encoder interface call
00075          HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
00076          interruption mode. Only available for LPTIM1 instance.
00077
00078          (++) Time out Mode: an active edge on one selected trigger input rests
00079          the counter. The first trigger event will start the timer, any
00080          successive trigger event will reset the counter and the timer will
00081          restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
00082          HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
00083
00084          (++) Counter Mode: counter can be used to count external events on
00085          the LPTIM Input1 or it can be used to count internal clock cycles.
00086          To start this mode, call HAL_LPTIM_Counter_Start() or
00087          HAL_LPTIM_Counter_Start_IT() for interruption mode.
00088
00089
00090       (#) User can stop any process by calling the corresponding API:
00091           HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
00092           already started in interruption mode.
00093
00094        (#)De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
00095
00096   @endverbatim
00097   ******************************************************************************
00098   * @attention
00099   *
00100   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00101   *
00102   * Redistribution and use in source and binary forms, with or without modification,
00103   * are permitted provided that the following conditions are met:
00104   *   1. Redistributions of source code must retain the above copyright notice,
00105   *      this list of conditions and the following disclaimer.
00106   *   2. Redistributions in binary form must reproduce the above copyright notice,
00107   *      this list of conditions and the following disclaimer in the documentation
00108   *      and/or other materials provided with the distribution.
00109   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00110   *      may be used to endorse or promote products derived from this software
00111   *      without specific prior written permission.
00112   *
00113   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00114   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00115   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00116   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00117   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00118   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00119   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00120   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00121   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00122   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00123   *
00124   ******************************************************************************
00125   */
00126
00127 /* Includes ------------------------------------------------------------------*/
00128 #include "stm32h7xx_hal.h"
00129
00130 /** @addtogroup STM32H7xx_HAL_Driver
00131   * @{
00132   */
00133
00134 /** @defgroup LPTIM LPTIM
00135   * @brief LPTIM HAL module driver.
00136   * @{
00137   */
00138
00139 #ifdef HAL_LPTIM_MODULE_ENABLED
00140 /* Private typedef -----------------------------------------------------------*/
00141 /* Private define ------------------------------------------------------------*/
00142 /* Private macro -------------------------------------------------------------*/
00143 /* Private variables ---------------------------------------------------------*/
00144 /* Private function prototypes -----------------------------------------------*/
00145 /* Exported functions --------------------------------------------------------*/
00146
00147 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
00148   * @{
00149   */
00150
00151 /** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
00152  *  @brief    Initialization and Configuration functions.
00153  *
00154 @verbatim
00155   ==============================================================================
00156               ##### Initialization and de-initialization functions #####
00157   ==============================================================================
00158     [..]  This section provides functions allowing to:
00159       (+) Initialize the LPTIM according to the specified parameters in the
00160           LPTIM_InitTypeDef and initialize the associated handle.
00161       (+) DeInitialize the LPTIM peripheral.
00162       (+) Initialize the LPTIM MSP.
00163       (+) DeInitialize the LPTIM MSP.
00164
00165 @endverbatim
00166   * @{
00167   */
00168
00169 /**
00170   * @brief  Initialize the LPTIM according to the specified parameters in the
00171   *         LPTIM_InitTypeDef and creates the associated handle.
00172   * @param  hlptim: LPTIM handle
00173   * @retval HAL status
00174   */
00175 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
00176 {
00177   uint32_t tmpcfgr = 0;
00178
00179   /* Check the LPTIM handle allocation */
00180   if(hlptim == NULL)
00181   {
00182     return HAL_ERROR;
00183   }
00184
00185   /* Check the parameters */
00186   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00187
00188   assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
00189   assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
00190   if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)
00191   {
00192     assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
00193     assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
00194   }
00195   assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
00196   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00197   {
00198     assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
00199     assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
00200   }
00201   assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
00202   assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
00203   assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
00204
00205   if(hlptim->State == HAL_LPTIM_STATE_RESET)
00206   {
00207     /* Allocate lock resource and initialize it */
00208     hlptim->Lock = HAL_UNLOCKED;
00209
00210     /* Init the low level hardware */
00211     HAL_LPTIM_MspInit(hlptim);
00212   }
00213
00214   /* Change the LPTIM state */
00215   hlptim->State = HAL_LPTIM_STATE_BUSY;
00216
00217   /* Get the LPTIMx CFGR value */
00218   tmpcfgr = hlptim->Instance->CFGR;
00219
00220   if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)
00221   {
00222     tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
00223   }
00224   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00225   {
00226     tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
00227   }
00228
00229   /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
00230   tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
00231                           LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE ));
00232
00233   /* Set initialization parameters */
00234   tmpcfgr |= (hlptim->Init.Clock.Source    |
00235               hlptim->Init.Clock.Prescaler |
00236               hlptim->Init.OutputPolarity  |
00237               hlptim->Init.UpdateMode      |
00238               hlptim->Init.CounterSource);
00239
00240   if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)
00241   {
00242     tmpcfgr |=  (hlptim->Init.UltraLowPowerClock.Polarity |
00243                 hlptim->Init.UltraLowPowerClock.SampleTime);
00244   }
00245
00246   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00247   {
00248     /* Enable External trigger and set the trigger source */
00249     tmpcfgr |= (hlptim->Init.Trigger.Source     |
00250                 hlptim->Init.Trigger.ActiveEdge |
00251                 hlptim->Init.Trigger.SampleTime);
00252   }
00253
00254   /* Write to LPTIMx CFGR */
00255   hlptim->Instance->CFGR = tmpcfgr;
00256
00257  /* Configure LPTIM input sources */
00258   if((hlptim->Instance == LPTIM1) || (hlptim->Instance == LPTIM2))
00259   {
00260     /* Check LPTIM1/2 Input1 and Input2 sources */
00261     assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance,hlptim->Init.Input1Source));
00262     assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance,hlptim->Init.Input2Source));
00263
00264     /* Configure LPTIM1/2 Input1 and Input2 sources */
00265     hlptim->Instance->CFGR2 = (hlptim->Init.Input1Source | hlptim->Init.Input2Source);
00266   }
00267   else
00268   {
00269   if(hlptim->Instance == LPTIM3)
00270     {
00271       /* Check LPTIM2 Input1 source */
00272       assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance,hlptim->Init.Input1Source));
00273
00274       /* Configure LPTIM2 Input1 source */
00275       hlptim->Instance->CFGR2 = hlptim->Init.Input1Source;
00276     }
00277   }
00278   /* Change the LPTIM state */
00279   hlptim->State = HAL_LPTIM_STATE_READY;
00280
00281   /* Return function status */
00282   return HAL_OK;
00283 }
00284
00285 /**
00286   * @brief  DeInitialize the LPTIM peripheral.
00287   * @param  hlptim: LPTIM handle
00288   * @retval HAL status
00289   */
00290 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
00291 {
00292   /* Check the LPTIM handle allocation */
00293   if(hlptim == NULL)
00294   {
00295     return HAL_ERROR;
00296   }
00297
00298   /* Change the LPTIM state */
00299   hlptim->State = HAL_LPTIM_STATE_BUSY;
00300
00301   /* Disable the LPTIM Peripheral Clock */
00302   __HAL_LPTIM_DISABLE(hlptim);
00303
00304   /* DeInit the low level hardware: CLOCK, NVIC.*/
00305   HAL_LPTIM_MspDeInit(hlptim);
00306
00307   /* Change the LPTIM state */
00308   hlptim->State = HAL_LPTIM_STATE_RESET;
00309
00310   /* Release Lock */
00311   __HAL_UNLOCK(hlptim);
00312
00313   /* Return function status */
00314   return HAL_OK;
00315 }
00316
00317 /**
00318   * @brief  Initialize the LPTIM MSP.
00319   * @param  hlptim: LPTIM handle
00320   * @retval None
00321   */
00322 __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
00323 {
00324   /* Prevent unused argument(s) compilation warning */
00325   UNUSED(hlptim);
00326
00327   /* NOTE : This function Should not be modified, when the callback is needed,
00328             the HAL_LPTIM_MspInit could be implemented in the user file
00329    */
00330 }
00331
00332 /**
00333   * @brief  DeInitialize LPTIM MSP.
00334   * @param  hlptim: LPTIM handle
00335   * @retval None
00336   */
00337 __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
00338 {
00339   /* Prevent unused argument(s) compilation warning */
00340   UNUSED(hlptim);
00341
00342   /* NOTE : This function Should not be modified, when the callback is needed,
00343             the HAL_LPTIM_MspDeInit could be implemented in the user file
00344    */
00345 }
00346
00347 /**
00348   * @}
00349   */
00350
00351 /** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
00352  *  @brief   Start-Stop operation functions.
00353  *
00354 @verbatim
00355   ==============================================================================
00356                 ##### LPTIM Start Stop operation functions #####
00357   ==============================================================================
00358     [..]  This section provides functions allowing to:
00359       (+) Start the PWM mode.
00360       (+) Stop the PWM mode.
00361       (+) Start the One pulse mode.
00362       (+) Stop the One pulse mode.
00363       (+) Start the Set once mode.
00364       (+) Stop the Set once mode.
00365       (+) Start the Encoder mode.
00366       (+) Stop the Encoder mode.
00367       (+) Start the Timeout mode.
00368       (+) Stop the Timeout mode.
00369       (+) Start the Counter mode.
00370       (+) Stop the Counter mode.
00371
00372
00373 @endverbatim
00374   * @{
00375   */
00376
00377 /**
00378   * @brief  Start the LPTIM PWM generation.
00379   * @param  hlptim : LPTIM handle
00380   * @param  Period : Specifies the Autoreload value.
00381   *         This parameter must be a value between 0x0000 and 0xFFFF.
00382   * @param  Pulse : Specifies the compare value.
00383   *         This parameter must be a value between 0x0000 and 0xFFFF.
00384   * @retval HAL status
00385   */
00386 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00387 {
00388   /* Check the parameters */
00389   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00390   assert_param(IS_LPTIM_PERIOD(Period));
00391   assert_param(IS_LPTIM_PULSE(Pulse));
00392
00393   /* Set the LPTIM state */
00394   hlptim->State= HAL_LPTIM_STATE_BUSY;
00395
00396   /* Reset WAVE bit to set PWM mode */
00397   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00398
00399   /* Enable the Peripheral */
00400   __HAL_LPTIM_ENABLE(hlptim);
00401
00402   /* Load the period value in the autoreload register */
00403   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00404
00405   /* Load the pulse value in the compare register */
00406   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00407
00408   /* Start timer in continuous mode */
00409   __HAL_LPTIM_START_CONTINUOUS(hlptim);
00410
00411   /* Change the TIM state*/
00412   hlptim->State= HAL_LPTIM_STATE_READY;
00413
00414   /* Return function status */
00415   return HAL_OK;
00416 }
00417
00418 /**
00419   * @brief  Stop the LPTIM PWM generation.
00420   * @param  hlptim : LPTIM handle
00421   * @retval HAL status
00422   */
00423 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
00424 {
00425   /* Check the parameters */
00426   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00427
00428   /* Set the LPTIM state */
00429   hlptim->State= HAL_LPTIM_STATE_BUSY;
00430
00431   /* Disable the Peripheral */
00432   __HAL_LPTIM_DISABLE(hlptim);
00433
00434   /* Change the TIM state*/
00435   hlptim->State= HAL_LPTIM_STATE_READY;
00436
00437   /* Return function status */
00438   return HAL_OK;
00439 }
00440
00441 /**
00442   * @brief  Start the LPTIM PWM generation in interrupt mode.
00443   * @param  hlptim : LPTIM handle
00444   * @param  Period : Specifies the Autoreload value.
00445   *         This parameter must be a value between 0x0000 and 0xFFFF
00446   * @param  Pulse : Specifies the compare value.
00447   *         This parameter must be a value between 0x0000 and 0xFFFF
00448   * @retval HAL status
00449   */
00450 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00451 {
00452   /* Check the parameters */
00453   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00454   assert_param(IS_LPTIM_PERIOD(Period));
00455   assert_param(IS_LPTIM_PULSE(Pulse));
00456
00457   /* Set the LPTIM state */
00458   hlptim->State= HAL_LPTIM_STATE_BUSY;
00459
00460   /* Reset WAVE bit to set PWM mode */
00461   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00462
00463   /* Enable Autoreload write complete interrupt */
00464   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
00465
00466   /* Enable Compare write complete interrupt */
00467   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
00468
00469   /* Enable Autoreload match interrupt */
00470   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
00471
00472   /* Enable Compare match interrupt */
00473   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
00474
00475   /* If external trigger source is used, then enable external trigger interrupt */
00476   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00477   {
00478     /* Enable external trigger interrupt */
00479     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00480   }
00481
00482   /* Enable the Peripheral */
00483   __HAL_LPTIM_ENABLE(hlptim);
00484
00485   /* Load the period value in the autoreload register */
00486   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00487
00488   /* Load the pulse value in the compare register */
00489   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00490
00491   /* Start timer in continuous mode */
00492   __HAL_LPTIM_START_CONTINUOUS(hlptim);
00493
00494   /* Change the TIM state*/
00495   hlptim->State= HAL_LPTIM_STATE_READY;
00496
00497   /* Return function status */
00498   return HAL_OK;
00499 }
00500
00501 /**
00502   * @brief  Stop the LPTIM PWM generation in interrupt mode.
00503   * @param  hlptim : LPTIM handle
00504   * @retval HAL status
00505   */
00506 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
00507 {
00508   /* Check the parameters */
00509   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00510
00511   /* Set the LPTIM state */
00512   hlptim->State= HAL_LPTIM_STATE_BUSY;
00513
00514   /* Disable the Peripheral */
00515   __HAL_LPTIM_DISABLE(hlptim);
00516
00517     /* Disable Autoreload write complete interrupt */
00518   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
00519
00520   /* Disable Compare write complete interrupt */
00521   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
00522
00523   /* Disable Autoreload match interrupt */
00524   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
00525
00526   /* Disable Compare match interrupt */
00527   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
00528
00529   /* If external trigger source is used, then disable external trigger interrupt */
00530   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00531   {
00532     /* Disable external trigger interrupt */
00533     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00534   }
00535
00536   /* Change the TIM state*/
00537   hlptim->State= HAL_LPTIM_STATE_READY;
00538
00539   /* Return function status */
00540   return HAL_OK;
00541 }
00542
00543 /**
00544   * @brief  Start the LPTIM One pulse generation.
00545   * @param  hlptim : LPTIM handle
00546   * @param  Period : Specifies the Autoreload value.
00547   *         This parameter must be a value between 0x0000 and 0xFFFF.
00548   * @param  Pulse : Specifies the compare value.
00549   *         This parameter must be a value between 0x0000 and 0xFFFF.
00550   * @retval HAL status
00551   */
00552 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00553 {
00554   /* Check the parameters */
00555   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00556   assert_param(IS_LPTIM_PERIOD(Period));
00557   assert_param(IS_LPTIM_PULSE(Pulse));
00558
00559   /* Set the LPTIM state */
00560   hlptim->State= HAL_LPTIM_STATE_BUSY;
00561
00562   /* Reset WAVE bit to set one pulse mode */
00563   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00564
00565   /* Enable the Peripheral */
00566   __HAL_LPTIM_ENABLE(hlptim);
00567
00568   /* Load the period value in the autoreload register */
00569   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00570
00571   /* Load the pulse value in the compare register */
00572   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00573
00574   /* Start timer in continuous mode */
00575   __HAL_LPTIM_START_SINGLE(hlptim);
00576
00577   /* Change the TIM state*/
00578   hlptim->State= HAL_LPTIM_STATE_READY;
00579
00580   /* Return function status */
00581   return HAL_OK;
00582 }
00583
00584 /**
00585   * @brief  Stop the LPTIM One pulse generation.
00586   * @param  hlptim : LPTIM handle
00587   * @retval HAL status
00588   */
00589 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
00590 {
00591   /* Check the parameters */
00592   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00593
00594   /* Set the LPTIM state */
00595   hlptim->State= HAL_LPTIM_STATE_BUSY;
00596
00597   /* Disable the Peripheral */
00598   __HAL_LPTIM_DISABLE(hlptim);
00599
00600   /* Change the TIM state*/
00601   hlptim->State= HAL_LPTIM_STATE_READY;
00602
00603   /* Return function status */
00604   return HAL_OK;
00605 }
00606
00607 /**
00608   * @brief  Start the LPTIM One pulse generation in interrupt mode.
00609   * @param  hlptim : LPTIM handle
00610   * @param  Period : Specifies the Autoreload value.
00611   *         This parameter must be a value between 0x0000 and 0xFFFF.
00612   * @param  Pulse : Specifies the compare value.
00613   *         This parameter must be a value between 0x0000 and 0xFFFF.
00614   * @retval HAL status
00615   */
00616 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00617 {
00618   /* Check the parameters */
00619   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00620   assert_param(IS_LPTIM_PERIOD(Period));
00621   assert_param(IS_LPTIM_PULSE(Pulse));
00622
00623   /* Set the LPTIM state */
00624   hlptim->State= HAL_LPTIM_STATE_BUSY;
00625
00626   /* Reset WAVE bit to set one pulse mode */
00627   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00628
00629   /* Enable Autoreload write complete interrupt */
00630   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
00631
00632   /* Enable Compare write complete interrupt */
00633   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
00634
00635   /* Enable Autoreload match interrupt */
00636   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
00637
00638   /* Enable Compare match interrupt */
00639   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
00640
00641   /* If external trigger source is used, then enable external trigger interrupt */
00642   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00643   {
00644     /* Enable external trigger interrupt */
00645     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00646   }
00647
00648   /* Enable the Peripheral */
00649   __HAL_LPTIM_ENABLE(hlptim);
00650
00651   /* Load the period value in the autoreload register */
00652   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00653
00654   /* Load the pulse value in the compare register */
00655   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00656
00657   /* Start timer in continuous mode */
00658   __HAL_LPTIM_START_SINGLE(hlptim);
00659
00660   /* Change the TIM state*/
00661   hlptim->State= HAL_LPTIM_STATE_READY;
00662
00663   /* Return function status */
00664   return HAL_OK;
00665 }
00666
00667 /**
00668   * @brief  Stop the LPTIM One pulse generation in interrupt mode.
00669   * @param  hlptim : LPTIM handle
00670   * @retval HAL status
00671   */
00672 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
00673 {
00674   /* Check the parameters */
00675   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00676
00677   /* Set the LPTIM state */
00678   hlptim->State= HAL_LPTIM_STATE_BUSY;
00679
00680   /* Disable the Peripheral */
00681   __HAL_LPTIM_DISABLE(hlptim);
00682
00683   /* Disable Autoreload write complete interrupt */
00684   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
00685
00686   /* Disable Compare write complete interrupt */
00687   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
00688
00689   /* Disable Autoreload match interrupt */
00690   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
00691
00692   /* Disable Compare match interrupt */
00693   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
00694
00695   /* If external trigger source is used, then disable external trigger interrupt */
00696   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00697   {
00698     /* Disable external trigger interrupt */
00699     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00700   }
00701
00702   /* Change the TIM state*/
00703   hlptim->State= HAL_LPTIM_STATE_READY;
00704
00705   /* Return function status */
00706   return HAL_OK;
00707 }
00708
00709 /**
00710   * @brief  Start the LPTIM in Set once mode.
00711   * @param  hlptim : LPTIM handle
00712   * @param  Period : Specifies the Autoreload value.
00713   *         This parameter must be a value between 0x0000 and 0xFFFF.
00714   * @param  Pulse : Specifies the compare value.
00715   *         This parameter must be a value between 0x0000 and 0xFFFF.
00716   * @retval HAL status
00717   */
00718 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00719 {
00720   /* Check the parameters */
00721   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00722   assert_param(IS_LPTIM_PERIOD(Period));
00723   assert_param(IS_LPTIM_PULSE(Pulse));
00724
00725   /* Set the LPTIM state */
00726   hlptim->State= HAL_LPTIM_STATE_BUSY;
00727
00728   /* Set WAVE bit to enable the set once mode */
00729   hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
00730
00731   /* Enable the Peripheral */
00732   __HAL_LPTIM_ENABLE(hlptim);
00733
00734   /* Load the period value in the autoreload register */
00735   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00736
00737   /* Load the pulse value in the compare register */
00738   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00739
00740   /* Start timer in continuous mode */
00741   __HAL_LPTIM_START_SINGLE(hlptim);
00742
00743   /* Change the TIM state*/
00744   hlptim->State= HAL_LPTIM_STATE_READY;
00745
00746   /* Return function status */
00747   return HAL_OK;
00748 }
00749
00750 /**
00751   * @brief  Stop the LPTIM Set once mode.
00752   * @param  hlptim : LPTIM handle
00753   * @retval HAL status
00754   */
00755 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
00756 {
00757   /* Check the parameters */
00758   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00759
00760   /* Set the LPTIM state */
00761   hlptim->State= HAL_LPTIM_STATE_BUSY;
00762
00763   /* Disable the Peripheral */
00764   __HAL_LPTIM_DISABLE(hlptim);
00765
00766   /* Change the TIM state*/
00767   hlptim->State= HAL_LPTIM_STATE_READY;
00768
00769   /* Return function status */
00770   return HAL_OK;
00771 }
00772
00773 /**
00774   * @brief  Start the LPTIM Set once mode in interrupt mode.
00775   * @param  hlptim : LPTIM handle
00776   * @param  Period : Specifies the Autoreload value.
00777   *         This parameter must be a value between 0x0000 and 0xFFFF.
00778   * @param  Pulse : Specifies the compare value.
00779   *         This parameter must be a value between 0x0000 and 0xFFFF.
00780   * @retval HAL status
00781   */
00782 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00783 {
00784   /* Check the parameters */
00785   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00786   assert_param(IS_LPTIM_PERIOD(Period));
00787   assert_param(IS_LPTIM_PULSE(Pulse));
00788
00789   /* Set the LPTIM state */
00790   hlptim->State= HAL_LPTIM_STATE_BUSY;
00791
00792   /* Set WAVE bit to enable the set once mode */
00793   hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
00794
00795   /* Enable Autoreload write complete interrupt */
00796   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
00797
00798   /* Enable Compare write complete interrupt */
00799   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
00800
00801   /* Enable Autoreload match interrupt */
00802   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
00803
00804   /* Enable Compare match interrupt */
00805   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
00806
00807   /* If external trigger source is used, then enable external trigger interrupt */
00808   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00809   {
00810     /* Enable external trigger interrupt */
00811     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00812   }
00813
00814   /* Enable the Peripheral */
00815   __HAL_LPTIM_ENABLE(hlptim);
00816
00817   /* Load the period value in the autoreload register */
00818   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00819
00820   /* Load the pulse value in the compare register */
00821   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00822
00823   /* Start timer in continuous mode */
00824   __HAL_LPTIM_START_SINGLE(hlptim);
00825
00826   /* Change the TIM state*/
00827   hlptim->State= HAL_LPTIM_STATE_READY;
00828
00829   /* Return function status */
00830   return HAL_OK;
00831 }
00832
00833 /**
00834   * @brief  Stop the LPTIM Set once mode in interrupt mode.
00835   * @param  hlptim : LPTIM handle
00836   * @retval HAL status
00837   */
00838 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
00839 {
00840   /* Check the parameters */
00841   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00842
00843   /* Set the LPTIM state */
00844   hlptim->State= HAL_LPTIM_STATE_BUSY;
00845
00846   /* Disable the Peripheral */
00847   __HAL_LPTIM_DISABLE(hlptim);
00848
00849   /* Disable Autoreload write complete interrupt */
00850   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
00851
00852   /* Disable Compare write complete interrupt */
00853   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
00854
00855   /* Disable Autoreload match interrupt */
00856   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
00857
00858   /* Disable Compare match interrupt */
00859   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
00860
00861   /* If external trigger source is used, then disable external trigger interrupt */
00862   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00863   {
00864     /* Disable external trigger interrupt */
00865     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00866   }
00867
00868   /* Change the TIM state*/
00869   hlptim->State= HAL_LPTIM_STATE_READY;
00870
00871   /* Return function status */
00872   return HAL_OK;
00873 }
00874
00875 /**
00876   * @brief  Starts the Encoder interface.
00877   * @param  hlptim : LPTIM handle
00878   * @param  Period : Specifies the Autoreload value.
00879   *         This parameter must be a value between 0x0000 and 0xFFFF.
00880   * @retval HAL status
00881   */
00882 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
00883 {
00884   HAL_StatusTypeDef status = HAL_OK;
00885   uint32_t          tmpcfgr;
00886
00887   /* Check the parameters */
00888   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00889   assert_param(IS_LPTIM_PERIOD(Period));
00890   assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
00891   assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
00892   assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
00893
00894   /* Encoder feature is only available for LPTIM1 instance */
00895   if ((hlptim->Instance == LPTIM1) || (hlptim->Instance == LPTIM2))
00896   {
00897     /* Set the LPTIM state */
00898     hlptim->State= HAL_LPTIM_STATE_BUSY;
00899
00900     /* Get the LPTIMx CFGR value */
00901     tmpcfgr = hlptim->Instance->CFGR;
00902
00903     /* Clear CKPOL bits */
00904     tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
00905
00906     /* Set Input polarity */
00907     tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
00908
00909     /* Write to LPTIMx CFGR */
00910     hlptim->Instance->CFGR = tmpcfgr;
00911
00912     /* Set ENC bit to enable the encoder interface */
00913     hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
00914
00915     /* Enable the Peripheral */
00916     __HAL_LPTIM_ENABLE(hlptim);
00917
00918     /* Load the period value in the autoreload register */
00919     __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00920
00921     /* Start timer in continuous mode */
00922     __HAL_LPTIM_START_CONTINUOUS(hlptim);
00923
00924     /* Change the TIM state*/
00925     hlptim->State= HAL_LPTIM_STATE_READY;
00926   }
00927   else
00928   {
00929     status = HAL_ERROR;
00930   }
00931
00932   /* Return function status */
00933   return status;
00934 }
00935
00936 /**
00937   * @brief  Stop the Encoder interface.
00938   * @param  hlptim : LPTIM handle
00939   * @retval HAL status
00940   */
00941 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
00942 {
00943   /* Check the parameters */
00944   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00945
00946   /* Set the LPTIM state */
00947   hlptim->State= HAL_LPTIM_STATE_BUSY;
00948
00949   /* Disable the Peripheral */
00950   __HAL_LPTIM_DISABLE(hlptim);
00951
00952   /* Reset ENC bit to disable the encoder interface */
00953   hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
00954
00955   /* Change the TIM state*/
00956   hlptim->State= HAL_LPTIM_STATE_READY;
00957
00958   /* Return function status */
00959   return HAL_OK;
00960 }
00961
00962 /**
00963   * @brief  Start the Encoder interface in interrupt mode.
00964   * @param  hlptim : LPTIM handle
00965   * @param  Period : Specifies the Autoreload value.
00966   *         This parameter must be a value between 0x0000 and 0xFFFF.
00967   * @retval HAL status
00968   */
00969 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
00970 {
00971   HAL_StatusTypeDef status = HAL_OK;
00972   uint32_t          tmpcfgr;
00973
00974   /* Check the parameters */
00975   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00976   assert_param(IS_LPTIM_PERIOD(Period));
00977   assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
00978   assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
00979   assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
00980
00981   /* Encoder feature is only available for LPTIM1 instance */
00982   if (hlptim->Instance == LPTIM1)
00983   {
00984     /* Set the LPTIM state */
00985     hlptim->State= HAL_LPTIM_STATE_BUSY;
00986
00987     /* Configure edge sensitivity for encoder mode */
00988     /* Get the LPTIMx CFGR value */
00989     tmpcfgr = hlptim->Instance->CFGR;
00990
00991     /* Clear CKPOL bits */
00992     tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
00993
00994     /* Set Input polarity */
00995     tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
00996
00997     /* Write to LPTIMx CFGR */
00998     hlptim->Instance->CFGR = tmpcfgr;
00999
01000     /* Set ENC bit to enable the encoder interface */
01001     hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
01002
01003     /* Enable "switch to down direction" interrupt */
01004     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
01005
01006     /* Enable "switch to up direction" interrupt */
01007     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP);
01008
01009     /* Enable the Peripheral */
01010     __HAL_LPTIM_ENABLE(hlptim);
01011
01012     /* Load the period value in the autoreload register */
01013     __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01014
01015     /* Start timer in continuous mode */
01016     __HAL_LPTIM_START_CONTINUOUS(hlptim);
01017
01018     /* Change the TIM state*/
01019     hlptim->State= HAL_LPTIM_STATE_READY;
01020   }
01021   else
01022   {
01023     status = HAL_ERROR;
01024   }
01025
01026   /* Return function status */
01027   return status;
01028 }
01029
01030 /**
01031   * @brief  Stop the Encoder interface in nterrupt mode.
01032   * @param  hlptim : LPTIM handle
01033   * @retval HAL status
01034   */
01035 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01036 {
01037   /* Check the parameters */
01038   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01039
01040   /* Set the LPTIM state */
01041   hlptim->State= HAL_LPTIM_STATE_BUSY;
01042
01043   /* Disable the Peripheral */
01044   __HAL_LPTIM_DISABLE(hlptim);
01045
01046   /* Reset ENC bit to disable the encoder interface */
01047   hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
01048
01049   /* Disable "switch to down direction" interrupt */
01050   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);
01051
01052   /* Disable "switch to up direction" interrupt */
01053   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP);
01054
01055   /* Change the TIM state*/
01056   hlptim->State= HAL_LPTIM_STATE_READY;
01057
01058   /* Return function status */
01059   return HAL_OK;
01060 }
01061
01062 /**
01063   * @brief  Start the Timeout function.
01064   * @note   The first trigger event will start the timer, any successive
01065   *         trigger event will reset the counter and the timer restarts.
01066   * @param  hlptim : LPTIM handle
01067   * @param  Period : Specifies the Autoreload value.
01068   *         This parameter must be a value between 0x0000 and 0xFFFF.
01069   * @param  Timeout : Specifies the TimeOut value to rest the counter.
01070   *         This parameter must be a value between 0x0000 and 0xFFFF.
01071   * @retval HAL status
01072   */
01073 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
01074 {
01075   /* Check the parameters */
01076   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01077   assert_param(IS_LPTIM_PERIOD(Period));
01078   assert_param(IS_LPTIM_PULSE(Timeout));
01079
01080   /* Set the LPTIM state */
01081   hlptim->State= HAL_LPTIM_STATE_BUSY;
01082
01083   /* Set TIMOUT bit to enable the timeout function */
01084   hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
01085
01086   /* Enable the Peripheral */
01087   __HAL_LPTIM_ENABLE(hlptim);
01088
01089   /* Load the period value in the autoreload register */
01090   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01091
01092   /* Load the Timeout value in the compare register */
01093   __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
01094
01095   /* Start timer in continuous mode */
01096   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01097
01098   /* Change the TIM state*/
01099   hlptim->State= HAL_LPTIM_STATE_READY;
01100
01101   /* Return function status */
01102   return HAL_OK;
01103 }
01104
01105 /**
01106   * @brief  Stop the Timeout function.
01107   * @param  hlptim : LPTIM handle
01108   * @retval HAL status
01109   */
01110 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
01111 {
01112   /* Check the parameters */
01113   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01114
01115   /* Set the LPTIM state */
01116   hlptim->State= HAL_LPTIM_STATE_BUSY;
01117
01118   /* Disable the Peripheral */
01119   __HAL_LPTIM_DISABLE(hlptim);
01120
01121   /* Reset TIMOUT bit to enable the timeout function */
01122   hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
01123
01124   /* Change the TIM state*/
01125   hlptim->State= HAL_LPTIM_STATE_READY;
01126
01127   /* Return function status */
01128   return HAL_OK;
01129 }
01130
01131 /**
01132   * @brief  Start the Timeout function in interrupt mode.
01133   * @note   The first trigger event will start the timer, any successive
01134   *         trigger event will reset the counter and the timer restarts.
01135   * @param  hlptim : LPTIM handle
01136   * @param  Period : Specifies the Autoreload value.
01137   *         This parameter must be a value between 0x0000 and 0xFFFF.
01138   * @param  Timeout : Specifies the TimeOut value to rest the counter.
01139   *         This parameter must be a value between 0x0000 and 0xFFFF.
01140   * @retval HAL status
01141   */
01142 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
01143 {
01144   /* Check the parameters */
01145   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01146   assert_param(IS_LPTIM_PERIOD(Period));
01147   assert_param(IS_LPTIM_PULSE(Timeout));
01148
01149   /* Set the LPTIM state */
01150   hlptim->State= HAL_LPTIM_STATE_BUSY;
01151
01152   /* Set TIMOUT bit to enable the timeout function */
01153   hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
01154
01155   /* Enable Compare match interrupt */
01156   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
01157
01158   /* Enable the Peripheral */
01159   __HAL_LPTIM_ENABLE(hlptim);
01160
01161   /* Load the period value in the autoreload register */
01162   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01163
01164   /* Load the Timeout value in the compare register */
01165   __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
01166
01167   /* Start timer in continuous mode */
01168   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01169
01170   /* Change the TIM state*/
01171   hlptim->State= HAL_LPTIM_STATE_READY;
01172
01173   /* Return function status */
01174   return HAL_OK;
01175 }
01176
01177 /**
01178   * @brief  Stop the Timeout function in interrupt mode.
01179   * @param  hlptim : LPTIM handle
01180   * @retval HAL status
01181   */
01182 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01183 {
01184   /* Check the parameters */
01185   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01186
01187   /* Set the LPTIM state */
01188   hlptim->State= HAL_LPTIM_STATE_BUSY;
01189
01190   /* Disable the Peripheral */
01191   __HAL_LPTIM_DISABLE(hlptim);
01192
01193   /* Reset TIMOUT bit to enable the timeout function */
01194   hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
01195
01196   /* Disable Compare match interrupt */
01197   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
01198
01199   /* Change the TIM state*/
01200   hlptim->State= HAL_LPTIM_STATE_READY;
01201
01202   /* Return function status */
01203   return HAL_OK;
01204 }
01205
01206 /**
01207   * @brief  Start the Counter mode.
01208   * @param  hlptim : LPTIM handle
01209   * @param  Period : Specifies the Autoreload value.
01210   *         This parameter must be a value between 0x0000 and 0xFFFF.
01211   * @retval HAL status
01212   */
01213 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01214 {
01215   /* Check the parameters */
01216   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01217   assert_param(IS_LPTIM_PERIOD(Period));
01218
01219   /* Set the LPTIM state */
01220   hlptim->State= HAL_LPTIM_STATE_BUSY;
01221
01222   /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
01223   if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
01224   {
01225     /* Check if clock is prescaled */
01226     assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
01227     /* Set clock prescaler to 0 */
01228     hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
01229   }
01230
01231   /* Enable the Peripheral */
01232   __HAL_LPTIM_ENABLE(hlptim);
01233
01234   /* Load the period value in the autoreload register */
01235   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01236
01237   /* Start timer in continuous mode */
01238   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01239
01240   /* Change the TIM state*/
01241   hlptim->State= HAL_LPTIM_STATE_READY;
01242
01243   /* Return function status */
01244   return HAL_OK;
01245 }
01246
01247 /**
01248   * @brief  Stop the Counter mode.
01249   * @param  hlptim : LPTIM handle
01250   * @retval HAL status
01251   */
01252 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
01253 {
01254   /* Check the parameters */
01255   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01256
01257   /* Set the LPTIM state */
01258   hlptim->State= HAL_LPTIM_STATE_BUSY;
01259
01260   /* Disable the Peripheral */
01261   __HAL_LPTIM_DISABLE(hlptim);
01262
01263   /* Change the TIM state*/
01264   hlptim->State= HAL_LPTIM_STATE_READY;
01265
01266   /* Return function status */
01267   return HAL_OK;
01268 }
01269
01270 /**
01271   * @brief  Start the Counter mode in interrupt mode.
01272   * @param  hlptim : LPTIM handle
01273   * @param  Period : Specifies the Autoreload value.
01274   *         This parameter must be a value between 0x0000 and 0xFFFF.
01275   * @retval HAL status
01276   */
01277 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01278 {
01279   /* Check the parameters */
01280   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01281   assert_param(IS_LPTIM_PERIOD(Period));
01282
01283   /* Set the LPTIM state */
01284   hlptim->State= HAL_LPTIM_STATE_BUSY;
01285
01286   /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
01287   if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
01288   {
01289     /* Check if clock is prescaled */
01290     assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
01291     /* Set clock prescaler to 0 */
01292     hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
01293   }
01294
01295   /* Enable Autoreload write complete interrupt */
01296   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
01297
01298   /* Enable Autoreload match interrupt */
01299   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
01300
01301   /* Enable the Peripheral */
01302   __HAL_LPTIM_ENABLE(hlptim);
01303
01304   /* Load the period value in the autoreload register */
01305   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01306
01307   /* Start timer in continuous mode */
01308   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01309
01310   /* Change the TIM state*/
01311   hlptim->State= HAL_LPTIM_STATE_READY;
01312
01313   /* Return function status */
01314   return HAL_OK;
01315 }
01316
01317 /**
01318   * @brief  Stop the Counter mode in interrupt mode.
01319   * @param  hlptim : LPTIM handle
01320   * @retval HAL status
01321   */
01322 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01323 {
01324   /* Check the parameters */
01325   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01326
01327   /* Set the LPTIM state */
01328   hlptim->State= HAL_LPTIM_STATE_BUSY;
01329
01330   /* Disable the Peripheral */
01331   __HAL_LPTIM_DISABLE(hlptim);
01332
01333   /* Disable Autoreload write complete interrupt */
01334   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
01335
01336   /* Disable Autoreload match interrupt */
01337   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
01338
01339   /* Change the TIM state*/
01340   hlptim->State= HAL_LPTIM_STATE_READY;
01341
01342   /* Return function status */
01343   return HAL_OK;
01344 }
01345
01346 /**
01347   * @}
01348   */
01349
01350 /** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
01351  *  @brief  Read operation functions.
01352  *
01353 @verbatim
01354   ==============================================================================
01355                   ##### LPTIM Read operation functions #####
01356   ==============================================================================
01357 [..]  This section provides LPTIM Reading functions.
01358       (+) Read the counter value.
01359       (+) Read the period (Auto-reload) value.
01360       (+) Read the pulse (Compare)value.
01361 @endverbatim
01362   * @{
01363   */
01364
01365 /**
01366   * @brief  Return the current counter value.
01367   * @param  hlptim: LPTIM handle
01368   * @retval Counter value.
01369   */
01370 uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
01371 {
01372     /* Check the parameters */
01373   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01374
01375   return (hlptim->Instance->CNT);
01376 }
01377
01378 /**
01379   * @brief  Return the current Autoreload (Period) value.
01380   * @param  hlptim: LPTIM handle
01381   * @retval Autoreload value.
01382   */
01383 uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
01384 {
01385     /* Check the parameters */
01386   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01387
01388   return (hlptim->Instance->ARR);
01389 }
01390
01391 /**
01392   * @brief  Return the current Compare (Pulse) value.
01393   * @param  hlptim: LPTIM handle
01394   * @retval Compare value.
01395   */
01396 uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
01397 {
01398     /* Check the parameters */
01399   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01400
01401   return (hlptim->Instance->CMP);
01402 }
01403
01404 /**
01405   * @}
01406   */
01407
01408
01409
01410 /** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
01411  *  @brief  LPTIM  IRQ handler.
01412  *
01413 @verbatim
01414   ==============================================================================
01415                       ##### LPTIM IRQ handler and callbacks  #####
01416   ==============================================================================
01417 [..]  This section provides LPTIM IRQ handler and callback functions called within
01418       the IRQ handler.
01419
01420 @endverbatim
01421   * @{
01422   */
01423
01424 /**
01425   * @brief  Handle LPTIM interrupt request.
01426   * @param  hlptim: LPTIM handle
01427   * @retval None
01428   */
01429 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
01430 {
01431   /* Compare match interrupt */
01432   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
01433   {
01434     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) != RESET)
01435     {
01436       /* Clear Compare match flag */
01437       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);
01438
01439       /* Compare match Callback */
01440       HAL_LPTIM_CompareMatchCallback(hlptim);
01441     }
01442   }
01443
01444   /* Autoreload match interrupt */
01445   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
01446   {
01447     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
01448     {
01449       /* Clear Autoreload match flag */
01450       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
01451
01452       /* Autoreload match Callback */
01453       HAL_LPTIM_AutoReloadMatchCallback(hlptim);
01454     }
01455   }
01456
01457   /* Trigger detected interrupt */
01458   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
01459   {
01460     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
01461     {
01462       /* Clear Trigger detected flag */
01463       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
01464
01465       /* Trigger detected callback */
01466       HAL_LPTIM_TriggerCallback(hlptim);
01467     }
01468   }
01469
01470   /* Compare write interrupt */
01471   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
01472   {
01473     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPOK) != RESET)
01474     {
01475       /* Clear Compare write flag */
01476       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
01477
01478       /* Compare write Callback */
01479       HAL_LPTIM_CompareWriteCallback(hlptim);
01480     }
01481   }
01482
01483   /* Autoreload write interrupt */
01484   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
01485   {
01486     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
01487     {
01488       /* Clear Autoreload write flag */
01489       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01490
01491       /* Autoreload write Callback */
01492       HAL_LPTIM_AutoReloadWriteCallback(hlptim);
01493     }
01494   }
01495
01496   /* Direction counter changed from Down to Up interrupt */
01497   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
01498   {
01499     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
01500     {
01501       /* Clear Direction counter changed from Down to Up flag */
01502       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
01503
01504       /* Direction counter changed from Down to Up Callback */
01505       HAL_LPTIM_DirectionUpCallback(hlptim);
01506     }
01507   }
01508
01509   /* Direction counter changed from Up to Down interrupt */
01510   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
01511   {
01512     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
01513     {
01514       /* Clear Direction counter changed from Up to Down flag */
01515       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
01516
01517       /* Direction counter changed from Up to Down Callback */
01518       HAL_LPTIM_DirectionDownCallback(hlptim);
01519     }
01520   }
01521 }
01522
01523 /**
01524   * @brief  Compare match callback in non-blocking mode
01525   * @param  hlptim : LPTIM handle
01526   * @retval None
01527   */
01528 __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
01529 {
01530   /* Prevent unused argument(s) compilation warning */
01531   UNUSED(hlptim);
01532
01533   /* NOTE : This function Should not be modified, when the callback is needed,
01534             the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
01535    */
01536 }
01537
01538 /**
01539   * @brief  Autoreload match callback in non-blocking mode
01540   * @param  hlptim : LPTIM handle
01541   * @retval None
01542   */
01543 __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
01544 {
01545   /* Prevent unused argument(s) compilation warning */
01546   UNUSED(hlptim);
01547
01548   /* NOTE : This function Should not be modified, when the callback is needed,
01549             the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
01550    */
01551 }
01552
01553 /**
01554   * @brief  Trigger detected callback in non-blocking mode
01555   * @param  hlptim : LPTIM handle
01556   * @retval None
01557   */
01558 __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
01559 {
01560   /* Prevent unused argument(s) compilation warning */
01561   UNUSED(hlptim);
01562
01563   /* NOTE : This function Should not be modified, when the callback is needed,
01564             the HAL_LPTIM_TriggerCallback could be implemented in the user file
01565    */
01566 }
01567
01568 /**
01569   * @brief  Compare write callback in non-blocking mode
01570   * @param  hlptim : LPTIM handle
01571   * @retval None
01572   */
01573 __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
01574 {
01575   /* Prevent unused argument(s) compilation warning */
01576   UNUSED(hlptim);
01577
01578   /* NOTE : This function Should not be modified, when the callback is needed,
01579             the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
01580    */
01581 }
01582
01583 /**
01584   * @brief  Autoreload write callback in non-blocking mode
01585   * @param  hlptim : LPTIM handle
01586   * @retval None
01587   */
01588 __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
01589 {
01590   /* Prevent unused argument(s) compilation warning */
01591   UNUSED(hlptim);
01592
01593   /* NOTE : This function Should not be modified, when the callback is needed,
01594             the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
01595    */
01596 }
01597
01598 /**
01599   * @brief  Direction counter changed from Down to Up callback in non-blocking mode
01600   * @param  hlptim : LPTIM handle
01601   * @retval None
01602   */
01603 __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
01604 {
01605   /* Prevent unused argument(s) compilation warning */
01606   UNUSED(hlptim);
01607
01608   /* NOTE : This function Should not be modified, when the callback is needed,
01609             the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
01610    */
01611 }
01612
01613 /**
01614   * @brief  Direction counter changed from Up to Down callback in non-blocking mode
01615   * @param  hlptim : LPTIM handle
01616   * @retval None
01617   */
01618 __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
01619 {
01620   /* Prevent unused argument(s) compilation warning */
01621   UNUSED(hlptim);
01622
01623   /* NOTE : This function Should not be modified, when the callback is needed,
01624             the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
01625    */
01626 }
01627
01628 /**
01629   * @}
01630   */
01631
01632 /** @defgroup LPTIM_Exported_Functions_Group5 Peripheral State functions
01633  *  @brief   Peripheral State functions.
01634  *
01635 @verbatim
01636   ==============================================================================
01637                       ##### Peripheral State functions #####
01638   ==============================================================================
01639     [..]
01640     This subsection permits to get in run-time the status of the peripheral.
01641
01642 @endverbatim
01643   * @{
01644   */
01645
01646 /**
01647   * @brief  Returns the LPTIM state.
01648   * @param  hlptim: LPTIM handle
01649   * @retval HAL state
01650   */
01651 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
01652 {
01653   /* Return LPTIM handle state */
01654   return hlptim->State;
01655 }
01656
01657 /**
01658   * @}
01659   */
01660
01661
01662 /**
01663   * @}
01664   */
01665
01666 #endif /* HAL_LPTIM_MODULE_ENABLED */
01667 /**
01668   * @}
01669   */
01670
01671 /**
01672   * @}
01673   */
01674
01675 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_lptim.h Source File

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stm32h7xx_hal_lptim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_lptim.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of LPTIM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_LPTIM_H
00040 #define __STM32H7xx_HAL_LPTIM_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup LPTIM
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup LPTIM_Exported_Types LPTIM Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  LPTIM Clock configuration definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Source;         /*!< Selects the clock source.
00068                            This parameter can be a value of @ref LPTIM_Clock_Source   */
00069
00070   uint32_t Prescaler;      /*!< Specifies the counter clock Prescaler.
00071                            This parameter can be a value of @ref LPTIM_Clock_Prescaler */
00072
00073 }LPTIM_ClockConfigTypeDef;
00074
00075 /**
00076   * @brief  LPTIM Clock configuration definition
00077   */
00078 typedef struct
00079 {
00080   uint32_t Polarity;      /*!< Selects the polarity of the active edge for the counter unit
00081                            if the ULPTIM input is selected.
00082                            Note: This parameter is used only when Ultra low power clock source is used.
00083                            Note: If the polarity is configured on 'both edges', an auxiliary clock
00084                            (one of the Low power oscillator) must be active.
00085                            This parameter can be a value of @ref LPTIM_Clock_Polarity */
00086
00087   uint32_t SampleTime;     /*!< Selects the clock sampling time to configure the clock glitch filter.
00088                            Note: This parameter is used only when Ultra low power clock source is used.
00089                            This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
00090
00091 }LPTIM_ULPClockConfigTypeDef;
00092
00093 /**
00094   * @brief  LPTIM Trigger configuration definition
00095   */
00096 typedef struct
00097 {
00098   uint32_t Source;        /*!< Selects the Trigger source.
00099                           This parameter can be a value of @ref LPTIM_Trigger_Source */
00100
00101   uint32_t ActiveEdge;    /*!< Selects the Trigger active edge.
00102                           Note: This parameter is used only when an external trigger is used.
00103                           This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
00104
00105   uint32_t SampleTime;    /*!< Selects the trigger sampling time to configure the clock glitch filter.
00106                           Note: This parameter is used only when an external trigger is used.
00107                           This parameter can be a value of @ref LPTIM_Trigger_Sample_Time  */
00108 }LPTIM_TriggerConfigTypeDef;
00109
00110 /**
00111   * @brief  LPTIM Initialization Structure definition
00112   */
00113 typedef struct
00114 {
00115   LPTIM_ClockConfigTypeDef     Clock;               /*!< Specifies the clock parameters */
00116
00117   LPTIM_ULPClockConfigTypeDef  UltraLowPowerClock;  /*!< Specifies the Ultra Low Power clock parameters */
00118
00119   LPTIM_TriggerConfigTypeDef   Trigger;             /*!< Specifies the Trigger parameters */
00120
00121   uint32_t                     OutputPolarity;      /*!< Specifies the Output polarity.
00122                                                     This parameter can be a value of @ref LPTIM_Output_Polarity */
00123
00124   uint32_t                     UpdateMode;          /*!< Specifies whether the update of the autorelaod and the compare
00125                                                     values is done immediately or after the end of current period.
00126                                                     This parameter can be a value of @ref LPTIM_Updating_Mode */
00127
00128   uint32_t                     CounterSource;       /*!< Specifies whether the counter is incremented each internal event
00129                                                     or each external event.
00130                                                     This parameter can be a value of @ref LPTIM_Counter_Source */
00131
00132   uint32_t                     Input1Source;        /*!< Specifies source selected for input1 (GPIO or comparator output).
00133                                                     This parameter can be a value of @ref LPTIM_Input1_Source */
00134
00135   uint32_t                     Input2Source;        /*!< Specifies source selected for input2 (GPIO or comparator output).
00136                                                     Note: This parameter is used only for encoder feature so is used only
00137                                                     for LPTIM1 instance.
00138                                                     This parameter can be a value of @ref LPTIM_Input2_Source */
00139
00140 }LPTIM_InitTypeDef;
00141
00142 /**
00143   * @brief  HAL LPTIM State structure definition
00144   */
00145 typedef enum __HAL_LPTIM_StateTypeDef
00146 {
00147   HAL_LPTIM_STATE_RESET            = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
00148   HAL_LPTIM_STATE_READY            = 0x01U,    /*!< Peripheral Initialized and ready for use    */
00149   HAL_LPTIM_STATE_BUSY             = 0x02U,    /*!< An internal process is ongoing              */
00150   HAL_LPTIM_STATE_TIMEOUT          = 0x03U,    /*!< Timeout state                               */
00151   HAL_LPTIM_STATE_ERROR            = 0x04U     /*!< Internal Process is ongoing                */
00152 }HAL_LPTIM_StateTypeDef;
00153
00154 /**
00155   * @brief  LPTIM handle Structure definition
00156   */
00157 typedef struct
00158 {
00159       LPTIM_TypeDef              *Instance;         /*!< Register base address     */
00160
00161       LPTIM_InitTypeDef           Init;             /*!< LPTIM required parameters */
00162
00163       HAL_StatusTypeDef           Status;           /*!< LPTIM peripheral status   */
00164
00165       HAL_LockTypeDef             Lock;             /*!< LPTIM locking object      */
00166
00167    __IO  HAL_LPTIM_StateTypeDef   State;            /*!< LPTIM peripheral state    */
00168
00169 }LPTIM_HandleTypeDef;
00170
00171 /**
00172   * @}
00173   */
00174
00175 /* Exported constants --------------------------------------------------------*/
00176 /** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
00177   * @{
00178   */
00179
00180 /** @defgroup LPTIM_Clock_Source LPTIM Clock Source
00181   * @{
00182   */
00183 #define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC        ((uint32_t)0x00U)
00184 #define LPTIM_CLOCKSOURCE_ULPTIM                LPTIM_CFGR_CKSEL
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
00190   * @{
00191   */
00192 #define LPTIM_PRESCALER_DIV1                    ((uint32_t)0x000000U)
00193 #define LPTIM_PRESCALER_DIV2                    LPTIM_CFGR_PRESC_0
00194 #define LPTIM_PRESCALER_DIV4                    LPTIM_CFGR_PRESC_1
00195 #define LPTIM_PRESCALER_DIV8                    ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
00196 #define LPTIM_PRESCALER_DIV16                   LPTIM_CFGR_PRESC_2
00197 #define LPTIM_PRESCALER_DIV32                   ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
00198 #define LPTIM_PRESCALER_DIV64                   ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
00199 #define LPTIM_PRESCALER_DIV128                  ((uint32_t)LPTIM_CFGR_PRESC)
00200 /**
00201   * @}
00202   */
00203
00204 /** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
00205   * @{
00206   */
00207
00208 #define LPTIM_OUTPUTPOLARITY_HIGH               ((uint32_t)0x00000000U)
00209 #define LPTIM_OUTPUTPOLARITY_LOW                (LPTIM_CFGR_WAVPOL)
00210 /**
00211   * @}
00212   */
00213
00214 /** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
00215   * @{
00216   */
00217 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION  ((uint32_t)0x00000000U)
00218 #define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_CKFLT_0
00219 #define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_CKFLT_1
00220 #define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_CKFLT
00221 /**
00222   * @}
00223   */
00224
00225 /** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
00226   * @{
00227   */
00228
00229 #define LPTIM_CLOCKPOLARITY_RISING              ((uint32_t)0x00000000U)
00230 #define LPTIM_CLOCKPOLARITY_FALLING             LPTIM_CFGR_CKPOL_0
00231 #define LPTIM_CLOCKPOLARITY_RISING_FALLING      LPTIM_CFGR_CKPOL_1
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
00237   * @{
00238   */
00239 #define LPTIM_TRIGSOURCE_SOFTWARE               ((uint32_t)0x0000FFFFU)
00240 #define LPTIM_TRIGSOURCE_0                      ((uint32_t)0x00000000U)
00241 #define LPTIM_TRIGSOURCE_1                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
00242 #define LPTIM_TRIGSOURCE_2                      LPTIM_CFGR_TRIGSEL_1
00243 #define LPTIM_TRIGSOURCE_3                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
00244 #define LPTIM_TRIGSOURCE_4                      LPTIM_CFGR_TRIGSEL_2
00245 #define LPTIM_TRIGSOURCE_5                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
00246 #define LPTIM_TRIGSOURCE_6                      ((uint32_t)LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
00247 #define LPTIM_TRIGSOURCE_7                      LPTIM_CFGR_TRIGSEL
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
00253   * @{
00254   */
00255 #define LPTIM_ACTIVEEDGE_RISING                LPTIM_CFGR_TRIGEN_0
00256 #define LPTIM_ACTIVEEDGE_FALLING               LPTIM_CFGR_TRIGEN_1
00257 #define LPTIM_ACTIVEEDGE_RISING_FALLING        LPTIM_CFGR_TRIGEN
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
00263   * @{
00264   */
00265 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION  ((uint32_t)0x00000000)
00266 #define LPTIM_TRIGSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_TRGFLT_0
00267 #define LPTIM_TRIGSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_TRGFLT_1
00268 #define LPTIM_TRIGSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_TRGFLT
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
00274   * @{
00275   */
00276
00277 #define LPTIM_UPDATE_IMMEDIATE                  ((uint32_t)0x00000000U)
00278 #define LPTIM_UPDATE_ENDOFPERIOD                LPTIM_CFGR_PRELOAD
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup LPTIM_Counter_Source LPTIM Counter Source
00284   * @{
00285   */
00286
00287 #define LPTIM_COUNTERSOURCE_INTERNAL            ((uint32_t)0x00000000U)
00288 #define LPTIM_COUNTERSOURCE_EXTERNAL            LPTIM_CFGR_COUNTMODE
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup LPTIM_Input1_Source LPTIM Input1 Source
00294   * @{
00295   */
00296
00297 #define LPTIM_INPUT1SOURCE_GPIO         ((uint32_t)0x00000000U)                       /*!< For LPTIM1, LPTIM2 and LPTIM3 */
00298 #define LPTIM_INPUT1SOURCE_COMP1        LPTIM_CFGR2_IN1_SEL0                         /*!< For LPTIM1 and LPTIM2 */
00299 #define LPTIM_INPUT1SOURCE_COMP2        LPTIM_CFGR2_IN1_SEL1                         /*!< For LPTIM2 and LPTIM2 */
00300 #define LPTIM_INPUT1SOURCE_COMP1_COMP2  (LPTIM_CFGR2_IN1_SEL0|LPTIM_CFGR2_IN1_SEL1)  /*!< For LPTIM2 */
00301 #define LPTIM_INPUT1SOURCE_SAI1_FSA     LPTIM_CFGR2_IN1_SEL0                        /*!< For LPTIM3 */
00302 #define LPTIM_INPUT1SOURCE_SAI1_FSB     LPTIM_CFGR2_IN1_SEL1                        /*!< For LPTIM3 */
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup LPTIM_Input2_Source LPTIM Input2 Source
00308   * @{
00309   */
00310
00311 #define LPTIM_INPUT2SOURCE_GPIO         ((uint32_t)0x00000000U)        /*!< For LPTIM1 and LPTIM2 */
00312 #define LPTIM_INPUT2SOURCE_COMP2        LPTIM_CFGR2_IN2_SEL0          /*!< For LPTIM1 and LPTIM2 */
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
00318   * @{
00319   */
00320
00321 #define LPTIM_FLAG_DOWN                          LPTIM_ISR_DOWN
00322 #define LPTIM_FLAG_UP                            LPTIM_ISR_UP
00323 #define LPTIM_FLAG_ARROK                         LPTIM_ISR_ARROK
00324 #define LPTIM_FLAG_CMPOK                         LPTIM_ISR_CMPOK
00325 #define LPTIM_FLAG_EXTTRIG                       LPTIM_ISR_EXTTRIG
00326 #define LPTIM_FLAG_ARRM                          LPTIM_ISR_ARRM
00327 #define LPTIM_FLAG_CMPM                          LPTIM_ISR_CMPM
00328 /**
00329   * @}
00330   */
00331
00332 /** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
00333   * @{
00334   */
00335
00336 #define LPTIM_IT_DOWN                            LPTIM_IER_DOWNIE
00337 #define LPTIM_IT_UP                              LPTIM_IER_UPIE
00338 #define LPTIM_IT_ARROK                           LPTIM_IER_ARROKIE
00339 #define LPTIM_IT_CMPOK                           LPTIM_IER_CMPOKIE
00340 #define LPTIM_IT_EXTTRIG                         LPTIM_IER_EXTTRIGIE
00341 #define LPTIM_IT_ARRM                            LPTIM_IER_ARRMIE
00342 #define LPTIM_IT_CMPM                            LPTIM_IER_CMPMIE
00343 /**
00344   * @}
00345   */
00346
00347 /**
00348   * @}
00349   */
00350
00351 /* Exported macros -----------------------------------------------------------*/
00352 /** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
00353   * @{
00354   */
00355
00356 /** @brief Reset LPTIM handle state
00357   * @param  __HANDLE__: LPTIM handle
00358   * @retval None
00359   */
00360 #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
00361
00362 /**
00363   * @brief  Enable the LPTIM peripheral.
00364   * @param  __HANDLE__: LPTIM handle
00365   * @retval None
00366   */
00367 #define __HAL_LPTIM_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |=  (LPTIM_CR_ENABLE))
00368
00369 /**
00370   * @brief  Disable the LPTIM peripheral.
00371   * @param  __HANDLE__: LPTIM handle
00372   * @retval None
00373   */
00374 #define __HAL_LPTIM_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR &=  ~(LPTIM_CR_ENABLE))
00375
00376 /**
00377   * @brief  Start the LPTIM peripheral in Continuous mode.
00378   * @param  __HANDLE__: LPTIM handle
00379   * @retval None
00380   */
00381 #define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  LPTIM_CR_CNTSTRT)
00382 /**
00383   * @brief  Start the LPTIM peripheral in single mode.
00384   * @param  __HANDLE__: LPTIM handle
00385   * @retval None
00386   */
00387 #define __HAL_LPTIM_START_SINGLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_SNGSTRT)
00388
00389 /**
00390   * @brief  Reset the LPTIM Counter register in synchronous mode.
00391   * @param  __HANDLE__: LPTIM handle
00392   * @retval None
00393   */
00394 #define __HAL_LPTIM_RESET_COUNTER(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_COUNTRST)
00395
00396 /**
00397   * @brief  Reset after read of the LPTIM Counter register in asynchronous mode.
00398   * @param  __HANDLE__: LPTIM handle
00399   * @retval None
00400   */
00401 #define __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_RSTARE)
00402
00403 /**
00404   * @brief  Write the passed parameter in the Autoreload register.
00405   * @param  __HANDLE__: LPTIM handle
00406   * @param  __VALUE__ : Autoreload value
00407   * @retval None
00408   */
00409 #define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__)  ((__HANDLE__)->Instance->ARR =  (__VALUE__))
00410
00411 /**
00412   * @brief  Write the passed parameter in the Compare register.
00413   * @param  __HANDLE__: LPTIM handle
00414   * @param  __VALUE__ : Compare value
00415   * @retval None
00416   */
00417 #define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__)     ((__HANDLE__)->Instance->CMP =  (__VALUE__))
00418
00419 /**
00420   * @brief  Check whether the specified LPTIM flag is set or not.
00421   * @param  __HANDLE__: LPTIM handle
00422   * @param  __FLAG__  : LPTIM flag to check
00423   *            This parameter can be a value of:
00424   *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
00425   *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
00426   *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
00427   *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
00428   *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
00429   *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
00430   *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
00431   * @retval The state of the specified flag (SET or RESET).
00432   */
00433 #define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
00434
00435 /**
00436   * @brief  Clear the specified LPTIM flag.
00437   * @param  __HANDLE__: LPTIM handle.
00438   * @param  __FLAG__  : LPTIM flag to clear.
00439   *            This parameter can be a value of:
00440   *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
00441   *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
00442   *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
00443   *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
00444   *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
00445   *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
00446   *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
00447   * @retval None.
00448   */
00449 #define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ICR  = (__FLAG__))
00450
00451 /**
00452   * @brief  Enable the specified LPTIM interrupt.
00453   * @param  __HANDLE__    : LPTIM handle.
00454   * @param  __INTERRUPT__ : LPTIM interrupt to set.
00455   *            This parameter can be a value of:
00456   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00457   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00458   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00459   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00460   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00461   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00462   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00463   * @retval None.
00464   */
00465 #define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER  |= (__INTERRUPT__))
00466
00467  /**
00468   * @brief  Disable the specified LPTIM interrupt.
00469   * @param  __HANDLE__    : LPTIM handle.
00470   * @param  __INTERRUPT__ : LPTIM interrupt to set.
00471   *            This parameter can be a value of:
00472   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00473   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00474   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00475   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00476   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00477   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00478   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00479   * @retval None.
00480   */
00481 #define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IER  &= (~(__INTERRUPT__)))
00482
00483     /**
00484   * @brief  Check whether the specified LPTIM interrupt is set or not.
00485   * @param  __HANDLE__    : LPTIM handle.
00486   * @param  __INTERRUPT__ : LPTIM interrupt to check.
00487   *            This parameter can be a value of:
00488   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00489   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00490   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00491   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00492   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00493   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00494   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00495   * @retval Interrupt status.
00496   */
00497
00498 #define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00499
00500 /**
00501   * @}
00502   */
00503 /* End of exported macros ----------------------------------------------------*/
00504
00505 /* Private constants ---------------------------------------------------------*/
00506 /** @defgroup LPTIM_Private_Constants LPTIM Private Constants
00507   * @{
00508   */
00509
00510 /**
00511   * @}
00512   */
00513 /* End of private constants --------------------------------------------------*/
00514 /* Private macros ------------------------------------------------------------*/
00515 /** @defgroup LPTIM_Private_Macros LPTIM Private Macros
00516   * @{
00517   */
00518
00519 #define IS_LPTIM_CLOCK_SOURCE(__SOURCE__)       (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
00520                                                  ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
00521
00522
00523 #define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
00524                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
00525                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
00526                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
00527                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
00528                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
00529                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
00530                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))
00531
00532 #define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1)
00533
00534 #define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)  (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
00535                                                  ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
00536
00537 #define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
00538                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
00539                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
00540                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
00541
00542 #define IS_LPTIM_CLOCK_POLARITY(__POLARITY__)   (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
00543                                                  ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
00544                                                  ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
00545
00546 #define IS_LPTIM_TRG_SOURCE(__TRIG__)           (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
00547                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
00548                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
00549                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
00550                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
00551                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
00552                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
00553                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
00554                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_7))
00555
00556 #define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING         ) || \
00557                                                  ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
00558                                                  ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
00559
00560 #define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
00561                                                    ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
00562                                                    ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
00563                                                    ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))
00564
00565 #define IS_LPTIM_UPDATE_MODE(__MODE__)          (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
00566                                                  ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
00567
00568 #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__)     (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
00569                                                  ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
00570
00571 #define IS_LPTIM_AUTORELOAD(__AUTORELOAD__)     ((__AUTORELOAD__) <= 0x0000FFFF)
00572
00573 #define IS_LPTIM_COMPARE(__COMPARE__)           ((__COMPARE__) <= 0x0000FFFF)
00574
00575 #define IS_LPTIM_PERIOD(__PERIOD__)             ((__PERIOD__) <= 0x0000FFFF)
00576
00577 #define IS_LPTIM_PULSE(__PULSE__)               ((__PULSE__) <= 0x0000FFFF)
00578
00579 #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)  \
00580     ((((__INSTANCE__) == LPTIM1) &&                       \
00581      (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
00582       ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1)))        \
00583      ||                                                   \
00584      (((__INSTANCE__) == LPTIM2) &&                       \
00585      (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
00586       ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) ||       \
00587       ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) ||       \
00588       ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2)))  \
00589      ||                                                   \
00590      (((__INSTANCE__) == LPTIM3) &&                       \
00591      (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
00592       ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI1_FSA) ||    \
00593       ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI1_FSB))))
00594
00595 #define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)  \
00596      (((__INSTANCE__) == LPTIM1) &&                       \
00597      (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) ||        \
00598       ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2))         \
00599       ||                                                  \
00600       ((__INSTANCE__) == LPTIM2) &&                       \
00601      (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) ||        \
00602       ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
00603 /**
00604   * @}
00605   */
00606 /* Exported functions --------------------------------------------------------*/
00607 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
00608   * @{
00609   */
00610
00611 /* Initialization/de-initialization functions  ********************************/
00612 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
00613 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
00614
00615 /* MSP functions  *************************************************************/
00616 void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
00617 void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
00618
00619 /* Start/Stop operation functions  *********************************************/
00620 /* ################################# PWM Mode ################################*/
00621 /* Blocking mode: Polling */
00622 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00623 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
00624 /* Non-Blocking mode: Interrupt */
00625 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00626 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00627
00628 /* ############################# One Pulse Mode ##############################*/
00629 /* Blocking mode: Polling */
00630 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00631 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
00632 /* Non-Blocking mode: Interrupt */
00633 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00634 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00635
00636 /* ############################## Set once Mode ##############################*/
00637 /* Blocking mode: Polling */
00638 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00639 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
00640 /* Non-Blocking mode: Interrupt */
00641 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00642 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00643
00644 /* ############################### Encoder Mode ##############################*/
00645 /* Blocking mode: Polling */
00646 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00647 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
00648 /* Non-Blocking mode: Interrupt */
00649 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00650 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00651
00652 /* ############################# Time out  Mode ##############################*/
00653 /* Blocking mode: Polling */
00654 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
00655 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
00656 /* Non-Blocking mode: Interrupt */
00657 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
00658 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00659
00660 /* ############################## Counter Mode ###############################*/
00661 /* Blocking mode: Polling */
00662 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00663 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
00664 /* Non-Blocking mode: Interrupt */
00665 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00666 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00667
00668 /* Reading operation functions ************************************************/
00669 uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
00670 uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
00671 uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
00672
00673 /* LPTIM IRQ functions  *******************************************************/
00674 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
00675
00676 /* CallBack functions  ********************************************************/
00677 void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
00678 void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
00679 void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
00680 void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
00681 void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
00682 void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
00683 void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
00684
00685 /* Peripheral State functions  ************************************************/
00686 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
00687
00688 /**
00689   * @}
00690   */
00691
00692 /* Private functions ---------------------------------------------------------*/
00693 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
00694   * @{
00695   */
00696
00697 /**
00698   * @}
00699   */
00700 /**
00701   * @}
00702   */
00703 /**
00704   * @}
00705   */
00706 #ifdef __cplusplus
00707 }
00708 #endif
00709
00710 #endif /* __STM32H7xx_HAL_LPTIM_H */
00711
00712 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_ltdc.c Source File

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stm32h7xx_hal_ltdc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_ltdc.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   LTDC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the LTDC peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Errors functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020      (#) Program the required configuration through the following parameters:
00021          the LTDC timing, the horizontal and vertical polarity,
00022          the pixel clock polarity, Data Enable polarity and the LTDC background color value
00023          using HAL_LTDC_Init() function
00024
00025      (#) Program the required configuration through the following parameters:
00026          the pixel format, the blending factors, input alpha value, the window size
00027          and the image size using HAL_LTDC_ConfigLayer() function for foreground
00028          or/and background layer.
00029
00030      (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and
00031          HAL_LTDC_EnableCLUT functions.
00032
00033      (#) Optionally, enable the Dither using HAL_LTDC_EnableDither().
00034
00035      (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying()
00036          and HAL_LTDC_EnableColorKeying functions.
00037
00038      (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent()
00039          function
00040
00041      (#) If needed, reconfigure and change the pixel format value, the alpha value
00042          value, the window size, the window position and the layer start address
00043          for foreground or/and background layer using respectively the following
00044          functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),
00045          HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetAddress.
00046
00047      (#) Variant functions with _NoReload post fix allows to set the LTDC configuration/settings without immediate reload.
00048          This is useful in case when the program requires to modify serval LTDC settings (on one or both layers)
00049          then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload
00050
00051          After calling the _NoReload functions to set different color/format/layer settings,
00052          the program can call the function  HAL_LTDC_Reload To apply(Reload) these settings.
00053          Function HAL_LTDC_Reload can be called with the parameter  ReloadType
00054          set to LTDC_RELOAD_IMMEDIATE if an immediate reload is required.
00055          Function HAL_LTDC_Reload can be called with the parameter  ReloadType
00056          set to LTDC_RELOAD_VERTICAL_BLANKING if the reload should be done in the next vertical blanking period,
00057          this option allows to avoid display flicker by applying the new settings during the vertical blanking period.
00058
00059
00060      (#) To control LTDC state you can use the following function: HAL_LTDC_GetState()
00061
00062      *** LTDC HAL driver macros list ***
00063      =============================================
00064      [..]
00065        Below the list of most used macros in LTDC HAL driver.
00066
00067       (+) __HAL_LTDC_ENABLE: Enable the LTDC.
00068       (+) __HAL_LTDC_DISABLE: Disable the LTDC.
00069       (+) __HAL_LTDC_LAYER_ENABLE: Enable an LTDC Layer.
00070       (+) __HAL_LTDC_LAYER_DISABLE: Disable an LTDC Layer.
00071       (+) __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG: Reload  Layer Configuration.
00072       (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags.
00073       (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags.
00074       (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts.
00075       (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.
00076       (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.
00077
00078      [..]
00079        (@) You can refer to the LTDC HAL driver header file for more useful macros
00080
00081   @endverbatim
00082   ******************************************************************************
00083   * @attention
00084   *
00085   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00086   *
00087   * Redistribution and use in source and binary forms, with or without modification,
00088   * are permitted provided that the following conditions are met:
00089   *   1. Redistributions of source code must retain the above copyright notice,
00090   *      this list of conditions and the following disclaimer.
00091   *   2. Redistributions in binary form must reproduce the above copyright notice,
00092   *      this list of conditions and the following disclaimer in the documentation
00093   *      and/or other materials provided with the distribution.
00094   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00095   *      may be used to endorse or promote products derived from this software
00096   *      without specific prior written permission.
00097   *
00098   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00099   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00100   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00101   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00102   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00103   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00104   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00105   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00106   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00107   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00108   *
00109   ******************************************************************************
00110   */
00111
00112 /* Includes ------------------------------------------------------------------*/
00113 #include "stm32h7xx_hal.h"
00114
00115 /** @addtogroup STM32H7xx_HAL_Driver
00116   * @{
00117   */
00118 /** @defgroup LTDC  LTDC
00119   * @brief LTDC HAL module driver
00120   * @{
00121   */
00122
00123 #ifdef HAL_LTDC_MODULE_ENABLED
00124
00125 /* Private typedef -----------------------------------------------------------*/
00126 /* Private define ------------------------------------------------------------*/
00127 /* Private macro -------------------------------------------------------------*/
00128 /* Private variables ---------------------------------------------------------*/
00129 /* Private function prototypes -----------------------------------------------*/
00130 static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
00131 /* Private functions ---------------------------------------------------------*/
00132
00133 /** @defgroup LTDC_Exported_Functions LTDC Exported Functions
00134   * @{
00135   */
00136
00137 /** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions
00138  *  @brief   Initialization and Configuration functions
00139  *
00140 @verbatim
00141  ===============================================================================
00142                 ##### Initialization and Configuration functions #####
00143  ===============================================================================
00144     [..]  This section provides functions allowing to:
00145       (+) Initialize and configure the LTDC
00146       (+) De-initialize the LTDC
00147
00148 @endverbatim
00149   * @{
00150   */
00151
00152 /**
00153   * @brief  Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef.
00154   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
00155   *                the configuration information for the LTDC.
00156   * @retval HAL status
00157   */
00158 HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
00159 {
00160   uint32_t tmp = 0, tmp1 = 0;
00161
00162   /* Check the LTDC peripheral state */
00163   if(hltdc == NULL)
00164   {
00165     return HAL_ERROR;
00166   }
00167
00168   /* Check function parameters */
00169   assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance));
00170   assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync));
00171   assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync));
00172   assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP));
00173   assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP));
00174   assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH));
00175   assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW));
00176   assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh));
00177   assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth));
00178   assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity));
00179   assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity));
00180   assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity));
00181   assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity));
00182
00183   if(hltdc->State == HAL_LTDC_STATE_RESET)
00184   {
00185     /* Allocate lock resource and initialize it */
00186     hltdc->Lock = HAL_UNLOCKED;
00187     /* Init the low level hardware */
00188     HAL_LTDC_MspInit(hltdc);
00189   }
00190
00191   /* Change LTDC peripheral state */
00192   hltdc->State = HAL_LTDC_STATE_BUSY;
00193
00194   /* Configure the HS, VS, DE and PC polarity */
00195   hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
00196   hltdc->Instance->GCR |=  (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
00197   hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
00198
00199   /* Set Synchronization size */
00200   hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
00201   tmp = (hltdc->Init.HorizontalSync << 16);
00202   hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);
00203
00204   /* Set Accumulated Back porch */
00205   hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
00206   tmp = (hltdc->Init.AccumulatedHBP << 16);
00207   hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);
00208
00209   /* Set Accumulated Active Width */
00210   hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
00211   tmp = (hltdc->Init.AccumulatedActiveW << 16);
00212   hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);
00213
00214   /* Set Total Width */
00215   hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
00216   tmp = (hltdc->Init.TotalWidth << 16);
00217   hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);
00218
00219   /* Set the background color value */
00220   tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8);
00221   tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16);
00222   hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
00223   hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);
00224
00225   /* Enable the Transfer Error and FIFO underrun interrupts */
00226   __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU);
00227
00228   /* Enable LTDC by setting LTDCEN bit */
00229   __HAL_LTDC_ENABLE(hltdc);
00230
00231   /* Initialize the error code */
00232   hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
00233
00234   /* Initialize the LTDC state*/
00235   hltdc->State = HAL_LTDC_STATE_READY;
00236
00237   return HAL_OK;
00238 }
00239
00240 /**
00241   * @brief  De-initialize the LTDC peripheral.
00242   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
00243   *                the configuration information for the LTDC.
00244   * @retval None
00245   */
00246
00247 HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)
00248 {
00249   /* DeInit the low level hardware */
00250   HAL_LTDC_MspDeInit(hltdc);
00251
00252   /* Initialize the error code */
00253   hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
00254
00255   /* Initialize the LTDC state*/
00256   hltdc->State = HAL_LTDC_STATE_RESET;
00257
00258   /* Release Lock */
00259   __HAL_UNLOCK(hltdc);
00260
00261   return HAL_OK;
00262 }
00263
00264 /**
00265   * @brief  Initialize the LTDC MSP.
00266   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
00267   *                the configuration information for the LTDC.
00268   * @retval None
00269   */
00270 __weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
00271 {
00272   /* Prevent unused argument(s) compilation warning */
00273   UNUSED(hltdc);
00274
00275   /* NOTE : This function should not be modified, when the callback is needed,
00276             the HAL_LTDC_MspInit could be implemented in the user file
00277    */
00278 }
00279
00280 /**
00281   * @brief  De-initialize the LTDC MSP.
00282   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
00283   *                the configuration information for the LTDC.
00284   * @retval None
00285   */
00286 __weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)
00287 {
00288   /* Prevent unused argument(s) compilation warning */
00289   UNUSED(hltdc);
00290
00291   /* NOTE : This function should not be modified, when the callback is needed,
00292             the HAL_LTDC_MspDeInit could be implemented in the user file
00293    */
00294 }
00295
00296 /**
00297   * @}
00298   */
00299
00300 /** @defgroup LTDC_Exported_Functions_Group2 IO operation functions
00301  *  @brief   IO operation functions
00302  *
00303 @verbatim
00304  ===============================================================================
00305                       #####  IO operation functions  #####
00306  ===============================================================================
00307     [..]  This section provides function allowing to:
00308       (+) Handle LTDC interrupt request
00309
00310 @endverbatim
00311   * @{
00312   */
00313 /**
00314   * @brief  Handle LTDC interrupt request.
00315   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
00316   *                the configuration information for the LTDC.
00317   * @retval HAL status
00318   */
00319 void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
00320 {
00321   /* Transfer Error Interrupt management ***************************************/
00322   if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_TE) != RESET)
00323   {
00324     if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_TE) != RESET)
00325     {
00326       /* Disable the transfer Error interrupt */
00327       __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
00328
00329       /* Clear the transfer error flag */
00330       __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);
00331
00332       /* Update error code */
00333       hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;
00334
00335       /* Change LTDC state */
00336       hltdc->State = HAL_LTDC_STATE_ERROR;
00337
00338       /* Process unlocked */
00339       __HAL_UNLOCK(hltdc);
00340
00341       /* Transfer error Callback */
00342       HAL_LTDC_ErrorCallback(hltdc);
00343     }
00344   }
00345   /* FIFO underrun Interrupt management ***************************************/
00346   if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_FU) != RESET)
00347   {
00348     if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_FU) != RESET)
00349     {
00350       /* Disable the FIFO underrun interrupt */
00351       __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
00352
00353       /* Clear the FIFO underrun flag */
00354       __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
00355
00356       /* Update error code */
00357       hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
00358
00359       /* Change LTDC state */
00360       hltdc->State = HAL_LTDC_STATE_ERROR;
00361
00362       /* Process unlocked */
00363       __HAL_UNLOCK(hltdc);
00364
00365       /* Transfer error Callback */
00366       HAL_LTDC_ErrorCallback(hltdc);
00367     }
00368   }
00369   /* Line Interrupt management ************************************************/
00370   if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_LI) != RESET)
00371   {
00372     if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_LI) != RESET)
00373     {
00374       /* Disable the Line interrupt */
00375       __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
00376
00377       /* Clear the Line interrupt flag */
00378       __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);
00379
00380       /* Change LTDC state */
00381       hltdc->State = HAL_LTDC_STATE_READY;
00382
00383       /* Process unlocked */
00384       __HAL_UNLOCK(hltdc);
00385
00386       /* Line interrupt Callback */
00387       HAL_LTDC_LineEventCallback(hltdc);
00388     }
00389   }
00390   /* Register reload Interrupt management ***************************************/
00391   if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_RR) != RESET)
00392   {
00393     if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_RR) != RESET)
00394     {
00395       /* Disable the register reload interrupt */
00396       __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);
00397
00398       /* Clear the register reload flag */
00399       __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);
00400
00401       /* Change LTDC state */
00402       hltdc->State = HAL_LTDC_STATE_READY;
00403
00404       /* Process unlocked */
00405       __HAL_UNLOCK(hltdc);
00406
00407       /* Register reload interrupt Callback */
00408       HAL_LTDC_ReloadEventCallback(hltdc);
00409     }
00410   }
00411 }
00412
00413 /**
00414   * @brief  Error LTDC callback.
00415   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
00416   *                the configuration information for the LTDC.
00417   * @retval None
00418   */
00419 __weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
00420 {
00421   /* Prevent unused argument(s) compilation warning */
00422   UNUSED(hltdc);
00423
00424   /* NOTE : This function should not be modified, when the callback is needed,
00425             the HAL_LTDC_ErrorCallback could be implemented in the user file
00426    */
00427 }
00428
00429 /**
00430   * @brief  Line Event callback.
00431   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
00432   *                the configuration information for the LTDC.
00433   * @retval None
00434   */
00435 __weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
00436 {
00437   /* Prevent unused argument(s) compilation warning */
00438   UNUSED(hltdc);
00439
00440   /* NOTE : This function should not be modified, when the callback is needed,
00441             the HAL_LTDC_LineEventCallback could be implemented in the user file
00442    */
00443 }
00444
00445 /**
00446   * @brief  Reload Event callback.
00447   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
00448   *                the configuration information for the LTDC.
00449   * @retval None
00450   */
00451 __weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
00452 {
00453   /* Prevent unused argument(s) compilation warning */
00454   UNUSED(hltdc);
00455
00456   /* NOTE : This function should not be modified, when the callback is needed,
00457             the HAL_LTDC_ReloadEvenCallback could be implemented in the user file
00458    */
00459 }
00460
00461 /**
00462   * @}
00463   */
00464
00465 /** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions
00466  *  @brief    Peripheral Control functions
00467  *
00468 @verbatim
00469  ===============================================================================
00470                     ##### Peripheral Control functions #####
00471  ===============================================================================
00472     [..]  This section provides functions allowing to:
00473       (+) Configure the LTDC foreground or/and background parameters.
00474       (+) Set the active layer.
00475       (+) Configure the color keying.
00476       (+) Configure the C-LUT.
00477       (+) Enable / Disable the color keying.
00478       (+) Enable / Disable the C-LUT.
00479       (+) Update the layer position.
00480       (+) Update the layer size.
00481       (+) Update pixel format on the fly.
00482       (+) Update transparency on the fly.
00483       (+) Update address on the fly.
00484
00485 @endverbatim
00486   * @{
00487   */
00488
00489 /**
00490   * @brief  Configure the LTDC Layer according to the specified
00491   *         parameters in the LTDC_InitTypeDef and create the associated handle.
00492   * @param  hltdc      pointer to a LTDC_HandleTypeDef structure that contains
00493   *                    the configuration information for the LTDC.
00494   * @param  pLayerCfg  pointer to a LTDC_LayerCfgTypeDef structure that contains
00495   *                    the configuration information for the Layer.
00496   * @param  LayerIdx  LTDC Layer index.
00497   *                    This parameter can be one of the following values:
00498   *                    LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
00499   * @retval HAL status
00500   */
00501 HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
00502 {
00503   /* Check the parameters */
00504   assert_param(IS_LTDC_LAYER(LayerIdx));
00505   assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
00506   assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
00507   assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
00508   assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
00509   assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
00510   assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha));
00511   assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
00512   assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
00513   assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
00514   assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
00515   assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
00516
00517   /* Process locked */
00518   __HAL_LOCK(hltdc);
00519
00520   /* Change LTDC peripheral state */
00521   hltdc->State = HAL_LTDC_STATE_BUSY;
00522
00523   /* Copy new layer configuration into handle structure */
00524   hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
00525
00526   /* Configure the LTDC Layer */
00527   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
00528
00529   /* Set the Immediate Reload type */
00530   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00531
00532   /* Initialize the LTDC state*/
00533   hltdc->State  = HAL_LTDC_STATE_READY;
00534
00535   /* Process unlocked */
00536   __HAL_UNLOCK(hltdc);
00537
00538   return HAL_OK;
00539 }
00540
00541 /**
00542   * @brief  Configure the color keying.
00543   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
00544   *                   the configuration information for the LTDC.
00545   * @param  RGBValue  the color key value
00546   * @param  LayerIdx  LTDC Layer index.
00547   *                   This parameter can be one of the following values:
00548   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
00549   * @retval HAL status
00550   */
00551 HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
00552 {
00553   /* Check the parameters */
00554   assert_param(IS_LTDC_LAYER(LayerIdx));
00555
00556   /* Process locked */
00557   __HAL_LOCK(hltdc);
00558
00559   /* Change LTDC peripheral state */
00560   hltdc->State = HAL_LTDC_STATE_BUSY;
00561
00562   /* Configure the default color values */
00563   LTDC_LAYER(hltdc, LayerIdx)->CKCR &=  ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
00564   LTDC_LAYER(hltdc, LayerIdx)->CKCR  = RGBValue;
00565
00566   /* Set the Immediate Reload type */
00567   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00568
00569   /* Change the LTDC state*/
00570   hltdc->State = HAL_LTDC_STATE_READY;
00571
00572   /* Process unlocked */
00573   __HAL_UNLOCK(hltdc);
00574
00575   return HAL_OK;
00576 }
00577
00578 /**
00579   * @brief  Load the color lookup table.
00580   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
00581   *                   the configuration information for the LTDC.
00582   * @param  pCLUT     pointer to the color lookup table address.
00583   * @param  CLUTSize  the color lookup table size.
00584   * @param  LayerIdx  LTDC Layer index.
00585   *                   This parameter can be one of the following values:
00586   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
00587   * @retval HAL status
00588   */
00589 HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)
00590 {
00591   uint32_t tmp = 0;
00592   uint32_t counter = 0;
00593   uint32_t pcounter = 0;
00594
00595   /* Check the parameters */
00596   assert_param(IS_LTDC_LAYER(LayerIdx));
00597
00598   /* Process locked */
00599   __HAL_LOCK(hltdc);
00600
00601   /* Change LTDC peripheral state */
00602   hltdc->State = HAL_LTDC_STATE_BUSY;
00603
00604   for(counter = 0; (counter < CLUTSize); counter++)
00605   {
00606     if(hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44)
00607     {
00608       tmp  = (((counter + 16*counter) << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000));
00609     }
00610     else
00611     {
00612       tmp  = ((counter << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000));
00613     }
00614     pcounter = (uint32_t)pCLUT + sizeof(*pCLUT);
00615     pCLUT = (uint32_t *)pcounter;
00616
00617     /* Specifies the C-LUT address and RGB value */
00618     LTDC_LAYER(hltdc, LayerIdx)->CLUTWR  = tmp;
00619   }
00620
00621   /* Change the LTDC state*/
00622   hltdc->State = HAL_LTDC_STATE_READY;
00623
00624   /* Process unlocked */
00625   __HAL_UNLOCK(hltdc);
00626
00627   return HAL_OK;
00628 }
00629
00630 /**
00631   * @brief  Enable the color keying.
00632   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
00633   *                   the configuration information for the LTDC.
00634   * @param  LayerIdx  LTDC Layer index.
00635   *                   This parameter can be one of the following values:
00636   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
00637   * @retval  HAL status
00638   */
00639 HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
00640 {
00641   /* Check the parameters */
00642   assert_param(IS_LTDC_LAYER(LayerIdx));
00643
00644   /* Process locked */
00645   __HAL_LOCK(hltdc);
00646
00647   /* Change LTDC peripheral state */
00648   hltdc->State = HAL_LTDC_STATE_BUSY;
00649
00650   /* Enable LTDC color keying by setting COLKEN bit */
00651   LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
00652
00653   /* Set the Immediate Reload type */
00654   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00655
00656   /* Change the LTDC state*/
00657   hltdc->State = HAL_LTDC_STATE_READY;
00658
00659   /* Process unlocked */
00660   __HAL_UNLOCK(hltdc);
00661
00662   return HAL_OK;
00663 }
00664
00665 /**
00666   * @brief  Disable the color keying.
00667   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
00668   *                   the configuration information for the LTDC.
00669   * @param  LayerIdx  LTDC Layer index.
00670   *                   This parameter can be one of the following values:
00671   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
00672   * @retval  HAL status
00673   */
00674 HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
00675 {
00676   /* Check the parameters */
00677   assert_param(IS_LTDC_LAYER(LayerIdx));
00678
00679   /* Process locked */
00680   __HAL_LOCK(hltdc);
00681
00682   /* Change LTDC peripheral state */
00683   hltdc->State = HAL_LTDC_STATE_BUSY;
00684
00685   /* Disable LTDC color keying by setting COLKEN bit */
00686   LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
00687
00688   /* Set the Immediate Reload type */
00689   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00690
00691   /* Change the LTDC state*/
00692   hltdc->State = HAL_LTDC_STATE_READY;
00693
00694   /* Process unlocked */
00695   __HAL_UNLOCK(hltdc);
00696
00697   return HAL_OK;
00698 }
00699
00700 /**
00701   * @brief  Enable the color lookup table.
00702   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
00703   *                   the configuration information for the LTDC.
00704   * @param  LayerIdx  LTDC Layer index.
00705   *                   This parameter can be one of the following values:
00706   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
00707   * @retval  HAL status
00708   */
00709 HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
00710 {
00711   /* Check the parameters */
00712   assert_param(IS_LTDC_LAYER(LayerIdx));
00713
00714   /* Process locked */
00715   __HAL_LOCK(hltdc);
00716
00717   /* Change LTDC peripheral state */
00718   hltdc->State = HAL_LTDC_STATE_BUSY;
00719
00720   /* Enable LTDC color lookup table by setting CLUTEN bit */
00721   LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
00722
00723   /* Set the Immediate Reload type */
00724   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00725
00726   /* Change the LTDC state*/
00727   hltdc->State = HAL_LTDC_STATE_READY;
00728
00729   /* Process unlocked */
00730   __HAL_UNLOCK(hltdc);
00731
00732   return HAL_OK;
00733 }
00734
00735 /**
00736   * @brief  Disable the color lookup table.
00737   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
00738   *                   the configuration information for the LTDC.
00739   * @param  LayerIdx  LTDC Layer index.
00740   *                   This parameter can be one of the following values:
00741   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
00742   * @retval  HAL status
00743   */
00744 HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
00745 {
00746   /* Check the parameters */
00747   assert_param(IS_LTDC_LAYER(LayerIdx));
00748
00749   /* Process locked */
00750   __HAL_LOCK(hltdc);
00751
00752   /* Change LTDC peripheral state */
00753   hltdc->State = HAL_LTDC_STATE_BUSY;
00754
00755   /* Disable LTDC color lookup table by setting CLUTEN bit */
00756   LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
00757
00758   /* Set the Immediate Reload type */
00759   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00760
00761   /* Change the LTDC state*/
00762   hltdc->State = HAL_LTDC_STATE_READY;
00763
00764   /* Process unlocked */
00765   __HAL_UNLOCK(hltdc);
00766
00767   return HAL_OK;
00768 }
00769
00770 /**
00771   * @brief  Enable Dither.
00772   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
00773   *                the configuration information for the LTDC.
00774   * @retval  HAL status
00775   */
00776
00777 HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc)
00778 {
00779   /* Process locked */
00780   __HAL_LOCK(hltdc);
00781
00782   /* Change LTDC peripheral state */
00783   hltdc->State = HAL_LTDC_STATE_BUSY;
00784
00785   /* Enable Dither by setting DTEN bit */
00786   LTDC->GCR |= (uint32_t)LTDC_GCR_DEN;
00787
00788   /* Change the LTDC state*/
00789   hltdc->State = HAL_LTDC_STATE_READY;
00790
00791   /* Process unlocked */
00792   __HAL_UNLOCK(hltdc);
00793
00794   return HAL_OK;
00795 }
00796
00797 /**
00798   * @brief  Disable Dither.
00799   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
00800   *                the configuration information for the LTDC.
00801   * @retval  HAL status
00802   */
00803
00804 HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc)
00805 {
00806   /* Process locked */
00807   __HAL_LOCK(hltdc);
00808
00809   /* Change LTDC peripheral state */
00810   hltdc->State = HAL_LTDC_STATE_BUSY;
00811
00812   /* Disable Dither by setting DTEN bit */
00813   LTDC->GCR &= ~(uint32_t)LTDC_GCR_DEN;
00814
00815   /* Change the LTDC state*/
00816   hltdc->State = HAL_LTDC_STATE_READY;
00817
00818   /* Process unlocked */
00819   __HAL_UNLOCK(hltdc);
00820
00821   return HAL_OK;
00822 }
00823
00824 /**
00825   * @brief  Set the LTDC window size.
00826   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
00827   *                   the configuration information for the LTDC.
00828   * @param  XSize     LTDC Pixel per line
00829   * @param  YSize     LTDC Line number
00830   * @param  LayerIdx  LTDC Layer index.
00831   *                   This parameter can be one of the following values:
00832   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
00833   * @retval  HAL status
00834   */
00835 HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
00836 {
00837   LTDC_LayerCfgTypeDef *pLayerCfg;
00838
00839   /* Check the parameters (Layers parameters)*/
00840   assert_param(IS_LTDC_LAYER(LayerIdx));
00841   assert_param(IS_LTDC_CFBLL(XSize));
00842   assert_param(IS_LTDC_CFBLNBR(YSize));
00843
00844   /* Process locked */
00845   __HAL_LOCK(hltdc);
00846
00847   /* Change LTDC peripheral state */
00848   hltdc->State = HAL_LTDC_STATE_BUSY;
00849
00850   /* Get layer configuration from handle structure */
00851   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
00852
00853   /* update horizontal stop */
00854   pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;
00855
00856   /* update vertical stop */
00857   pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;
00858
00859   /* Reconfigures the color frame buffer pitch in byte */
00860   pLayerCfg->ImageWidth = XSize;
00861
00862   /* Reconfigures the frame buffer line number */
00863   pLayerCfg->ImageHeight = YSize;
00864
00865   /* Set LTDC parameters */
00866   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
00867
00868   /* Set the Immediate Reload type */
00869   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00870
00871   /* Change the LTDC state*/
00872   hltdc->State = HAL_LTDC_STATE_READY;
00873
00874   /* Process unlocked */
00875   __HAL_UNLOCK(hltdc);
00876
00877   return HAL_OK;
00878 }
00879
00880 /**
00881   * @brief  Set the LTDC window position.
00882   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
00883   *                   the configuration information for the LTDC.
00884   * @param  X0        LTDC window X offset
00885   * @param  Y0        LTDC window Y offset
00886   * @param  LayerIdx  LTDC Layer index.
00887   *                         This parameter can be one of the following values:
00888   *                         LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
00889   * @retval  HAL status
00890   */
00891 HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
00892 {
00893   LTDC_LayerCfgTypeDef *pLayerCfg;
00894
00895   /* Check the parameters */
00896   assert_param(IS_LTDC_LAYER(LayerIdx));
00897   assert_param(IS_LTDC_CFBLL(X0));
00898   assert_param(IS_LTDC_CFBLNBR(Y0));
00899
00900   /* Process locked */
00901   __HAL_LOCK(hltdc);
00902
00903   /* Change LTDC peripheral state */
00904   hltdc->State = HAL_LTDC_STATE_BUSY;
00905
00906   /* Get layer configuration from handle structure */
00907   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
00908
00909   /* update horizontal start/stop */
00910   pLayerCfg->WindowX0 = X0;
00911   pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;
00912
00913   /* update vertical start/stop */
00914   pLayerCfg->WindowY0 = Y0;
00915   pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;
00916
00917   /* Set LTDC parameters */
00918   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
00919
00920   /* Set the Immediate Reload type */
00921   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00922
00923   /* Change the LTDC state*/
00924   hltdc->State = HAL_LTDC_STATE_READY;
00925
00926   /* Process unlocked */
00927   __HAL_UNLOCK(hltdc);
00928
00929   return HAL_OK;
00930 }
00931
00932 /**
00933   * @brief  Reconfigure the pixel format.
00934   * @param  hltdc        pointer to a LTDC_HandleTypeDef structure that contains
00935   *                      the configuration information for the LTDC.
00936   * @param  Pixelformat  new pixel format value.
00937   * @param  LayerIdx     LTDC Layer index.
00938   *                      This parameter can be one of the following values:
00939   *                      LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
00940   * @retval  HAL status
00941   */
00942 HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
00943 {
00944   LTDC_LayerCfgTypeDef *pLayerCfg;
00945
00946   /* Check the parameters */
00947   assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
00948   assert_param(IS_LTDC_LAYER(LayerIdx));
00949
00950   /* Process locked */
00951   __HAL_LOCK(hltdc);
00952
00953   /* Change LTDC peripheral state */
00954   hltdc->State = HAL_LTDC_STATE_BUSY;
00955
00956   /* Get layer configuration from handle structure */
00957   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
00958
00959   /* Reconfigure the pixel format */
00960   pLayerCfg->PixelFormat = Pixelformat;
00961
00962   /* Set LTDC parameters */
00963   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
00964
00965   /* Set the Immediate Reload type */
00966   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00967
00968   /* Change the LTDC state*/
00969   hltdc->State = HAL_LTDC_STATE_READY;
00970
00971   /* Process unlocked */
00972   __HAL_UNLOCK(hltdc);
00973
00974   return HAL_OK;
00975 }
00976
00977 /**
00978   * @brief  Reconfigure the layer alpha value.
00979   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
00980   *                   the configuration information for the LTDC.
00981   * @param  Alpha     new alpha value.
00982   * @param  LayerIdx  LTDC Layer index.
00983   *                   This parameter can be one of the following values:
00984   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
00985   * @retval  HAL status
00986   */
00987 HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
00988 {
00989   LTDC_LayerCfgTypeDef *pLayerCfg;
00990
00991   /* Check the parameters */
00992   assert_param(IS_LTDC_ALPHA(Alpha));
00993   assert_param(IS_LTDC_LAYER(LayerIdx));
00994
00995   /* Process locked */
00996   __HAL_LOCK(hltdc);
00997
00998   /* Change LTDC peripheral state */
00999   hltdc->State = HAL_LTDC_STATE_BUSY;
01000
01001   /* Get layer configuration from handle structure */
01002   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
01003
01004   /* Reconfigure the Alpha value */
01005   pLayerCfg->Alpha = Alpha;
01006
01007   /* Set LTDC parameters */
01008   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
01009
01010   /* Set the Immediate Reload type */
01011   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
01012
01013   /* Change the LTDC state*/
01014   hltdc->State = HAL_LTDC_STATE_READY;
01015
01016   /* Process unlocked */
01017   __HAL_UNLOCK(hltdc);
01018
01019   return HAL_OK;
01020 }
01021 /**
01022   * @brief  Reconfigure the frame buffer Address.
01023   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01024   *                   the configuration information for the LTDC.
01025   * @param  Address   new address value.
01026   * @param  LayerIdx  LTDC Layer index.
01027   *                   This parameter can be one of the following values:
01028   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
01029   * @retval  HAL status
01030   */
01031 HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
01032 {
01033   LTDC_LayerCfgTypeDef *pLayerCfg;
01034
01035   /* Check the parameters */
01036   assert_param(IS_LTDC_LAYER(LayerIdx));
01037
01038   /* Process locked */
01039   __HAL_LOCK(hltdc);
01040
01041   /* Change LTDC peripheral state */
01042   hltdc->State = HAL_LTDC_STATE_BUSY;
01043
01044   /* Get layer configuration from handle structure */
01045   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
01046
01047   /* Reconfigure the Address */
01048   pLayerCfg->FBStartAdress = Address;
01049
01050   /* Set LTDC parameters */
01051   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
01052
01053   /* Set the Immediate Reload type */
01054   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
01055
01056   /* Change the LTDC state*/
01057   hltdc->State = HAL_LTDC_STATE_READY;
01058
01059   /* Process unlocked */
01060   __HAL_UNLOCK(hltdc);
01061
01062   return HAL_OK;
01063 }
01064
01065 /**
01066   * @brief  Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is
01067   *         larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we
01068   *         want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels
01069   *         will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().
01070   * @note   This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
01071   *         configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
01072   * @param  hltdc              pointer to a LTDC_HandleTypeDef structure that contains
01073   *                            the configuration information for the LTDC.
01074   * @param  LinePitchInPixels  New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
01075   * @param  LayerIdx           LTDC layer index concerned by the modification of line pitch.
01076   * @retval HAL status
01077   */
01078 HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
01079 {
01080   uint32_t tmp = 0;
01081   uint32_t pitchUpdate = 0;
01082   uint32_t pixelFormat = 0;
01083
01084   /* Check the parameters */
01085   assert_param(IS_LTDC_LAYER(LayerIdx));
01086
01087   /* Process locked */
01088   __HAL_LOCK(hltdc);
01089
01090   /* Change LTDC peripheral state */
01091   hltdc->State = HAL_LTDC_STATE_BUSY;
01092
01093   /* get LayerIdx used pixel format */
01094   pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
01095
01096   if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
01097   {
01098     tmp = 4;
01099   }
01100   else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)
01101   {
01102     tmp = 3;
01103   }
01104   else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
01105           (pixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \
01106           (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
01107          (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
01108   {
01109     tmp = 2;
01110   }
01111   else
01112   {
01113     tmp = 1;
01114   }
01115
01116   pitchUpdate = ((LinePitchInPixels * tmp) << 16);
01117
01118   /* Clear previously set standard pitch */
01119   LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;
01120
01121   /* Set the Reload type as immediate update of LTDC pitch configured above */
01122   LTDC->SRCR |= LTDC_SRCR_IMR;
01123
01124   /* Set new line pitch value */
01125   LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
01126
01127   /* Set the Reload type as immediate update of LTDC pitch configured above */
01128   LTDC->SRCR |= LTDC_SRCR_IMR;
01129
01130   /* Change the LTDC state*/
01131   hltdc->State = HAL_LTDC_STATE_READY;
01132
01133   /* Process unlocked */
01134   __HAL_UNLOCK(hltdc);
01135
01136   return HAL_OK;
01137 }
01138
01139 /**
01140   * @brief  Define the position of the line interrupt.
01141   * @param  hltdc   pointer to a LTDC_HandleTypeDef structure that contains
01142   *                 the configuration information for the LTDC.
01143   * @param  Line    Line Interrupt Position.
01144   * @note   User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation.
01145   * @retval  HAL status
01146   */
01147 HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line)
01148 {
01149   /* Check the parameters */
01150   assert_param(IS_LTDC_LIPOS(Line));
01151
01152   /* Process locked */
01153   __HAL_LOCK(hltdc);
01154
01155   /* Change LTDC peripheral state */
01156   hltdc->State = HAL_LTDC_STATE_BUSY;
01157
01158   /* Disable the Line interrupt */
01159   __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
01160
01161   /* Set the Line Interrupt position */
01162   LTDC->LIPCR = (uint32_t)Line;
01163
01164   /* Enable the Line interrupt */
01165   __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI);
01166
01167   /* Change the LTDC state*/
01168   hltdc->State = HAL_LTDC_STATE_READY;
01169
01170   /* Process unlocked */
01171   __HAL_UNLOCK(hltdc);
01172
01173   return HAL_OK;
01174 }
01175
01176 /**
01177   * @brief  Reload LTDC Layers configuration.
01178   * @param  hltdc      pointer to a LTDC_HandleTypeDef structure that contains
01179   *                    the configuration information for the LTDC.
01180   * @param  ReloadType This parameter can be one of the following values :
01181   *                      LTDC_RELOAD_IMMEDIATE : Immediate Reload
01182   *                      LTDC_RELOAD_VERTICAL_BLANKING  : Reload in the next Vertical Blanking
01183   * @note   User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation.
01184   * @retval  HAL status
01185   */
01186 HAL_StatusTypeDef  HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType)
01187 {
01188   /* Check the parameters */
01189   assert_param(IS_LTDC_RELOAD(ReloadType));
01190
01191   /* Process locked */
01192   __HAL_LOCK(hltdc);
01193
01194   /* Change LTDC peripheral state */
01195   hltdc->State = HAL_LTDC_STATE_BUSY;
01196
01197   /* Enable the Reload interrupt */
01198   __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR);
01199
01200   /* Apply Reload type */
01201   hltdc->Instance->SRCR = ReloadType;
01202
01203   /* Change the LTDC state*/
01204   hltdc->State = HAL_LTDC_STATE_READY;
01205
01206   /* Process unlocked */
01207   __HAL_UNLOCK(hltdc);
01208
01209   return HAL_OK;
01210 }
01211
01212 /**
01213   * @brief  Configure the LTDC Layer according to the specified without reloading
01214   *         parameters in the LTDC_InitTypeDef and create the associated handle.
01215   *         Variant of the function HAL_LTDC_ConfigLayer without immediate reload.
01216   * @param  hltdc      pointer to a LTDC_HandleTypeDef structure that contains
01217   *                    the configuration information for the LTDC.
01218   * @param  pLayerCfg  pointer to a LTDC_LayerCfgTypeDef structure that contains
01219   *                    the configuration information for the Layer.
01220   * @param  LayerIdx   LTDC Layer index.
01221   *                    This parameter can be one of the following values:
01222   *                    LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01223   * @retval HAL status
01224   */
01225 HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
01226 {
01227   /* Check the parameters */
01228   assert_param(IS_LTDC_LAYER(LayerIdx));
01229   assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
01230   assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
01231   assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
01232   assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
01233   assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
01234   assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha));
01235   assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
01236   assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
01237   assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
01238   assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
01239   assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
01240
01241   /* Process locked */
01242   __HAL_LOCK(hltdc);
01243
01244   /* Change LTDC peripheral state */
01245   hltdc->State = HAL_LTDC_STATE_BUSY;
01246
01247   /* Copy new layer configuration into handle structure */
01248   hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
01249
01250   /* Configure the LTDC Layer */
01251   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
01252
01253   /* Do not set the Immediate Reload  */
01254
01255   /* Initialize the LTDC state*/
01256   hltdc->State  = HAL_LTDC_STATE_READY;
01257
01258   /* Process unlocked */
01259   __HAL_UNLOCK(hltdc);
01260
01261   return HAL_OK;
01262 }
01263
01264 /**
01265   * @brief  Set the LTDC window size without reloading.
01266   *         Variant of the function HAL_LTDC_SetWindowSize without immediate reload.
01267   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01268   *                   the configuration information for the LTDC.
01269   * @param  XSize     LTDC Pixel per line
01270   * @param  YSize     LTDC Line number
01271   * @param  LayerIdx  LTDC Layer index.
01272   *                   This parameter can be one of the following values:
01273   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01274   * @retval  HAL status
01275   */
01276 HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
01277 {
01278   LTDC_LayerCfgTypeDef *pLayerCfg;
01279
01280   /* Check the parameters (Layers parameters)*/
01281   assert_param(IS_LTDC_LAYER(LayerIdx));
01282   assert_param(IS_LTDC_CFBLL(XSize));
01283   assert_param(IS_LTDC_CFBLNBR(YSize));
01284
01285   /* Process locked */
01286   __HAL_LOCK(hltdc);
01287
01288   /* Change LTDC peripheral state */
01289   hltdc->State = HAL_LTDC_STATE_BUSY;
01290
01291   /* Get layer configuration from handle structure */
01292   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
01293
01294   /* update horizontal stop */
01295   pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;
01296
01297   /* update vertical stop */
01298   pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;
01299
01300   /* Reconfigures the color frame buffer pitch in byte */
01301   pLayerCfg->ImageWidth = XSize;
01302
01303   /* Reconfigures the frame buffer line number */
01304   pLayerCfg->ImageHeight = YSize;
01305
01306   /* Set LTDC parameters */
01307   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
01308
01309   /* Do not set the Immediate Reload  */
01310
01311   /* Change the LTDC state*/
01312   hltdc->State = HAL_LTDC_STATE_READY;
01313
01314   /* Process unlocked */
01315   __HAL_UNLOCK(hltdc);
01316
01317   return HAL_OK;
01318 }
01319
01320 /**
01321   * @brief  Set the LTDC window position without reloading.
01322   *         Variant of the function HAL_LTDC_SetWindowPosition without immediate reload.
01323   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01324   *                   the configuration information for the LTDC.
01325   * @param  X0        LTDC window X offset
01326   * @param  Y0        LTDC window Y offset
01327   * @param  LayerIdx  LTDC Layer index.
01328   *                         This parameter can be one of the following values:
01329   *                         LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01330   * @retval  HAL status
01331   */
01332 HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
01333 {
01334   LTDC_LayerCfgTypeDef *pLayerCfg;
01335
01336   /* Check the parameters */
01337   assert_param(IS_LTDC_LAYER(LayerIdx));
01338   assert_param(IS_LTDC_CFBLL(X0));
01339   assert_param(IS_LTDC_CFBLNBR(Y0));
01340
01341   /* Process locked */
01342   __HAL_LOCK(hltdc);
01343
01344   /* Change LTDC peripheral state */
01345   hltdc->State = HAL_LTDC_STATE_BUSY;
01346
01347   /* Get layer configuration from handle structure */
01348   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
01349
01350   /* update horizontal start/stop */
01351   pLayerCfg->WindowX0 = X0;
01352   pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;
01353
01354   /* update vertical start/stop */
01355   pLayerCfg->WindowY0 = Y0;
01356   pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;
01357
01358   /* Set LTDC parameters */
01359   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
01360
01361   /* Do not set the Immediate Reload  */
01362
01363   /* Change the LTDC state*/
01364   hltdc->State = HAL_LTDC_STATE_READY;
01365
01366   /* Process unlocked */
01367   __HAL_UNLOCK(hltdc);
01368
01369   return HAL_OK;
01370 }
01371
01372 /**
01373   * @brief  Reconfigure the pixel format without reloading.
01374   *         Variant of the function HAL_LTDC_SetPixelFormat without immediate reload.
01375   * @param  hltdc        pointer to a LTDC_HandleTypeDfef structure that contains
01376   *                      the configuration information for the LTDC.
01377   * @param  Pixelformat  new pixel format value.
01378   * @param  LayerIdx     LTDC Layer index.
01379   *                      This parameter can be one of the following values:
01380   *                      LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
01381   * @retval  HAL status
01382   */
01383 HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
01384 {
01385   LTDC_LayerCfgTypeDef *pLayerCfg;
01386
01387   /* Check the parameters */
01388   assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
01389   assert_param(IS_LTDC_LAYER(LayerIdx));
01390
01391   /* Process locked */
01392   __HAL_LOCK(hltdc);
01393
01394   /* Change LTDC peripheral state */
01395   hltdc->State = HAL_LTDC_STATE_BUSY;
01396
01397   /* Get layer configuration from handle structure */
01398   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
01399
01400   /* Reconfigure the pixel format */
01401   pLayerCfg->PixelFormat = Pixelformat;
01402
01403   /* Set LTDC parameters */
01404   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
01405
01406   /* Do not set the Immediate Reload  */
01407
01408   /* Change the LTDC state*/
01409   hltdc->State = HAL_LTDC_STATE_READY;
01410
01411   /* Process unlocked */
01412   __HAL_UNLOCK(hltdc);
01413
01414   return HAL_OK;
01415 }
01416
01417 /**
01418   * @brief  Reconfigure the layer alpha value without reloading.
01419   *         Variant of the function HAL_LTDC_SetAlpha without immediate reload.
01420   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01421   *                   the configuration information for the LTDC.
01422   * @param  Alpha     new alpha value.
01423   * @param  LayerIdx  LTDC Layer index.
01424   *                   This parameter can be one of the following values:
01425   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01426   * @retval  HAL status
01427   */
01428 HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
01429 {
01430   LTDC_LayerCfgTypeDef *pLayerCfg;
01431
01432   /* Check the parameters */
01433   assert_param(IS_LTDC_ALPHA(Alpha));
01434   assert_param(IS_LTDC_LAYER(LayerIdx));
01435
01436   /* Process locked */
01437   __HAL_LOCK(hltdc);
01438
01439   /* Change LTDC peripheral state */
01440   hltdc->State = HAL_LTDC_STATE_BUSY;
01441
01442   /* Get layer configuration from handle structure */
01443   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
01444
01445   /* Reconfigure the Alpha value */
01446   pLayerCfg->Alpha = Alpha;
01447
01448   /* Set LTDC parameters */
01449   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
01450
01451   /* Do not set the Immediate Reload  */
01452
01453   /* Change the LTDC state*/
01454   hltdc->State = HAL_LTDC_STATE_READY;
01455
01456   /* Process unlocked */
01457   __HAL_UNLOCK(hltdc);
01458
01459   return HAL_OK;
01460 }
01461
01462 /**
01463   * @brief  Reconfigure the frame buffer Address without reloading.
01464   *         Variant of the function HAL_LTDC_SetAddress without immediate reload.
01465   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01466   *                   the configuration information for the LTDC.
01467   * @param  Address   new address value.
01468   * @param  LayerIdx  LTDC Layer index.
01469   *                   This parameter can be one of the following values:
01470   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
01471   * @retval  HAL status
01472   */
01473 HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
01474 {
01475   LTDC_LayerCfgTypeDef *pLayerCfg;
01476
01477   /* Check the parameters */
01478   assert_param(IS_LTDC_LAYER(LayerIdx));
01479
01480   /* Process locked */
01481   __HAL_LOCK(hltdc);
01482
01483   /* Change LTDC peripheral state */
01484   hltdc->State = HAL_LTDC_STATE_BUSY;
01485
01486   /* Get layer configuration from handle structure */
01487   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
01488
01489   /* Reconfigure the Address */
01490   pLayerCfg->FBStartAdress = Address;
01491
01492   /* Set LTDC parameters */
01493   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
01494
01495   /* Do not set the Immediate Reload  */
01496
01497   /* Change the LTDC state*/
01498   hltdc->State = HAL_LTDC_STATE_READY;
01499
01500   /* Process unlocked */
01501   __HAL_UNLOCK(hltdc);
01502
01503   return HAL_OK;
01504 }
01505
01506 /**
01507   * @brief  Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is
01508   *         larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we
01509   *         want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels
01510   *         will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().
01511   * @note   This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
01512   *         configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
01513   *         Variant of the function HAL_LTDC_SetPitch without immediate reload.
01514   * @param  hltdc              pointer to a LTDC_HandleTypeDef structure that contains
01515   *                            the configuration information for the LTDC.
01516   * @param  LinePitchInPixels  New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
01517   * @param  LayerIdx           LTDC layer index concerned by the modification of line pitch.
01518   * @retval HAL status
01519   */
01520 HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
01521 {
01522   uint32_t tmp = 0;
01523   uint32_t pitchUpdate = 0;
01524   uint32_t pixelFormat = 0;
01525
01526   /* Check the parameters */
01527   assert_param(IS_LTDC_LAYER(LayerIdx));
01528
01529   /* Process locked */
01530   __HAL_LOCK(hltdc);
01531
01532   /* Change LTDC peripheral state */
01533   hltdc->State = HAL_LTDC_STATE_BUSY;
01534
01535   /* get LayerIdx used pixel format */
01536   pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
01537
01538   if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
01539   {
01540     tmp = 4;
01541   }
01542   else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)
01543   {
01544     tmp = 3;
01545   }
01546   else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
01547           (pixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \
01548           (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
01549          (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
01550   {
01551     tmp = 2;
01552   }
01553   else
01554   {
01555     tmp = 1;
01556   }
01557
01558   pitchUpdate = ((LinePitchInPixels * tmp) << 16);
01559
01560   /* Clear previously set standard pitch */
01561   LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;
01562
01563   /* Set new line pitch value */
01564   LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
01565
01566   /* Do not set the Immediate Reload  */
01567
01568   /* Change the LTDC state*/
01569   hltdc->State = HAL_LTDC_STATE_READY;
01570
01571   /* Process unlocked */
01572   __HAL_UNLOCK(hltdc);
01573
01574   return HAL_OK;
01575 }
01576
01577
01578 /**
01579   * @brief  Configure the color keying without reloading.
01580   *         Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload.
01581   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01582   *                   the configuration information for the LTDC.
01583   * @param  RGBValue the color key value
01584   * @param  LayerIdx  LTDC Layer index.
01585   *                   This parameter can be one of the following values:
01586   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01587   * @retval HAL status
01588   */
01589 HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
01590 {
01591   /* Check the parameters */
01592   assert_param(IS_LTDC_LAYER(LayerIdx));
01593
01594   /* Process locked */
01595   __HAL_LOCK(hltdc);
01596
01597   /* Change LTDC peripheral state */
01598   hltdc->State = HAL_LTDC_STATE_BUSY;
01599
01600   /* Configure the default color values */
01601   LTDC_LAYER(hltdc, LayerIdx)->CKCR &=  ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
01602   LTDC_LAYER(hltdc, LayerIdx)->CKCR  = RGBValue;
01603
01604   /* Do not set the Immediate Reload  */
01605
01606   /* Change the LTDC state*/
01607   hltdc->State = HAL_LTDC_STATE_READY;
01608
01609   /* Process unlocked */
01610   __HAL_UNLOCK(hltdc);
01611
01612   return HAL_OK;
01613 }
01614
01615 /**
01616   * @brief  Enable the color keying without reloading.
01617   *         Variant of the function HAL_LTDC_EnableColorKeying without immediate reload.
01618   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01619   *                   the configuration information for the LTDC.
01620   * @param  LayerIdx  LTDC Layer index.
01621   *                   This parameter can be one of the following values:
01622   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01623   * @retval  HAL status
01624   */
01625 HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
01626 {
01627   /* Check the parameters */
01628   assert_param(IS_LTDC_LAYER(LayerIdx));
01629
01630   /* Process locked */
01631   __HAL_LOCK(hltdc);
01632
01633   /* Change LTDC peripheral state */
01634   hltdc->State = HAL_LTDC_STATE_BUSY;
01635
01636   /* Enable LTDC color keying by setting COLKEN bit */
01637   LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
01638
01639   /* Do not set the Immediate Reload  */
01640
01641   /* Change the LTDC state*/
01642   hltdc->State = HAL_LTDC_STATE_READY;
01643
01644   /* Process unlocked */
01645   __HAL_UNLOCK(hltdc);
01646
01647   return HAL_OK;
01648 }
01649
01650 /**
01651   * @brief  Disable the color keying without reloading.
01652   *         Variant of the function HAL_LTDC_DisableColorKeying without immediate reload.
01653   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01654   *                   the configuration information for the LTDC.
01655   * @param  LayerIdx  LTDC Layer index.
01656   *                   This parameter can be one of the following values:
01657   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01658   * @retval  HAL status
01659   */
01660 HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
01661 {
01662   /* Check the parameters */
01663   assert_param(IS_LTDC_LAYER(LayerIdx));
01664
01665   /* Process locked */
01666   __HAL_LOCK(hltdc);
01667
01668   /* Change LTDC peripheral state */
01669   hltdc->State = HAL_LTDC_STATE_BUSY;
01670
01671   /* Disable LTDC color keying by setting COLKEN bit */
01672   LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
01673
01674   /* Do not set the Immediate Reload  */
01675
01676   /* Change the LTDC state*/
01677   hltdc->State = HAL_LTDC_STATE_READY;
01678
01679   /* Process unlocked */
01680   __HAL_UNLOCK(hltdc);
01681
01682   return HAL_OK;
01683 }
01684
01685 /**
01686   * @brief  Enable the color lookup table without reloading.
01687   *         Variant of the function HAL_LTDC_EnableCLUT without immediate reload.
01688   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01689   *                   the configuration information for the LTDC.
01690   * @param  LayerIdx  LTDC Layer index.
01691   *                   This parameter can be one of the following values:
01692   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01693   * @retval  HAL status
01694   */
01695 HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
01696 {
01697   /* Check the parameters */
01698   assert_param(IS_LTDC_LAYER(LayerIdx));
01699
01700   /* Process locked */
01701   __HAL_LOCK(hltdc);
01702
01703   /* Change LTDC peripheral state */
01704   hltdc->State = HAL_LTDC_STATE_BUSY;
01705
01706   /* Disable LTDC color lookup table by setting CLUTEN bit */
01707   LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
01708
01709   /* Do not set the Immediate Reload  */
01710
01711   /* Change the LTDC state*/
01712   hltdc->State = HAL_LTDC_STATE_READY;
01713
01714   /* Process unlocked */
01715   __HAL_UNLOCK(hltdc);
01716
01717   return HAL_OK;
01718 }
01719
01720 /**
01721   * @brief  Disable the color lookup table without reloading.
01722   *         Variant of the function HAL_LTDC_DisableCLUT without immediate reload.
01723   * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
01724   *                   the configuration information for the LTDC.
01725   * @param  LayerIdx  LTDC Layer index.
01726   *                   This parameter can be one of the following values:
01727   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01728   * @retval  HAL status
01729   */
01730 HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
01731 {
01732   /* Check the parameters */
01733   assert_param(IS_LTDC_LAYER(LayerIdx));
01734
01735   /* Process locked */
01736   __HAL_LOCK(hltdc);
01737
01738   /* Change LTDC peripheral state */
01739   hltdc->State = HAL_LTDC_STATE_BUSY;
01740
01741   /* Disable LTDC color lookup table by setting CLUTEN bit */
01742   LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
01743
01744   /* Do not set the Immediate Reload  */
01745
01746   /* Change the LTDC state*/
01747   hltdc->State = HAL_LTDC_STATE_READY;
01748
01749   /* Process unlocked */
01750   __HAL_UNLOCK(hltdc);
01751
01752   return HAL_OK;
01753 }
01754
01755 /**
01756   * @}
01757   */
01758
01759 /** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions
01760  *  @brief    Peripheral State and Errors functions
01761  *
01762 @verbatim
01763  ===============================================================================
01764                   ##### Peripheral State and Errors functions #####
01765  ===============================================================================
01766     [..]
01767     This subsection provides functions allowing to
01768       (+) Check the LTDC handle state.
01769       (+) Get the LTDC handle error code.
01770
01771 @endverbatim
01772   * @{
01773   */
01774
01775 /**
01776   * @brief  Return the LTDC handle state.
01777   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
01778   *                the configuration information for the LTDC.
01779   * @retval HAL state
01780   */
01781 HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)
01782 {
01783   return hltdc->State;
01784 }
01785
01786 /**
01787   * @brief  Return the LTDC handle error code.
01788   * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
01789   *               the configuration information for the LTDC.
01790 * @retval LTDC Error Code
01791 */
01792 uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc)
01793 {
01794   return hltdc->ErrorCode;
01795 }
01796
01797 /**
01798   * @}
01799   */
01800
01801 /**
01802   * @brief  Configures the LTDC peripheral
01803   * @param  hltdc   :  Pointer to a LTDC_HandleTypeDef structure that contains
01804   *                   the configuration information for the LTDC.
01805   * @param  pLayerCfg Pointer LTDC Layer Configuration structure
01806   * @param  LayerIdx  LTDC Layer index.
01807   *                   This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
01808   * @retval None
01809   */
01810 static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
01811 {
01812   uint32_t tmp = 0;
01813   uint32_t tmp1 = 0;
01814   uint32_t tmp2 = 0;
01815
01816   /* Configure the horizontal start and stop position */
01817   tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16)) << 16);
01818   LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
01819   LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16) + 1) | tmp);
01820
01821   /* Configure the vertical start and stop position */
01822   tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16);
01823   LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
01824   LTDC_LAYER(hltdc, LayerIdx)->WVPCR  = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1) | tmp);
01825
01826   /* Specifies the pixel format */
01827   LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);
01828   LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);
01829
01830   /* Configure the default color values */
01831   tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8);
01832   tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16);
01833   tmp2 = (pLayerCfg->Alpha0 << 24);
01834   LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
01835   LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2);
01836
01837   /* Specifies the constant alpha value */
01838   LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
01839   LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);
01840
01841   /* Specifies the blending factors */
01842   LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
01843   LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
01844
01845   /* Configure the color frame buffer start address */
01846   LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
01847   LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);
01848
01849   if(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
01850   {
01851     tmp = 4;
01852   }
01853   else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)
01854   {
01855     tmp = 3;
01856   }
01857   else if((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
01858     (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \
01859       (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
01860         (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
01861   {
01862     tmp = 2;
01863   }
01864   else
01865   {
01866     tmp = 1;
01867   }
01868
01869   /* Configure the color frame buffer pitch in byte */
01870   LTDC_LAYER(hltdc, LayerIdx)->CFBLR  &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
01871   LTDC_LAYER(hltdc, LayerIdx)->CFBLR  = (((pLayerCfg->ImageWidth * tmp) << 16) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp)  + 7));
01872
01873   /* Configure the frame buffer line number */
01874   LTDC_LAYER(hltdc, LayerIdx)->CFBLNR  &= ~(LTDC_LxCFBLNR_CFBLNBR);
01875   LTDC_LAYER(hltdc, LayerIdx)->CFBLNR  = (pLayerCfg->ImageHeight);
01876
01877   /* Enable LTDC_Layer by setting LEN bit */
01878   LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;
01879 }
01880
01881 /**
01882   * @}
01883   */
01884
01885 #endif /* HAL_LTDC_MODULE_ENABLED */
01886
01887 /**
01888   * @}
01889   */
01890
01891 /**
01892   * @}
01893   */
01894
01895 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_ltdc.h Source File

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stm32h7xx_hal_ltdc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_ltdc.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of LTDC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_LTDC_H
00040 #define __STM32H7xx_HAL_LTDC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049
00050 /** @addtogroup STM32H7xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup LTDC LTDC
00055   * @brief LTDC HAL module driver
00056   * @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060 /** @defgroup LTDC_Exported_Types LTDC Exported Types
00061   * @{
00062   */
00063 #define MAX_LAYER  2U
00064
00065 /**
00066   * @brief  LTDC color structure definition
00067   */
00068 typedef struct
00069 {
00070   uint8_t Blue;                    /*!< Configures the blue value.
00071                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00072
00073   uint8_t Green;                   /*!< Configures the green value.
00074                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00075
00076   uint8_t Red;                     /*!< Configures the red value.
00077                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00078
00079   uint8_t Reserved;                /*!< Reserved 0xFF */
00080 } LTDC_ColorTypeDef;
00081
00082 /**
00083   * @brief  LTDC Init structure definition
00084   */
00085 typedef struct
00086 {
00087   uint32_t            HSPolarity;                /*!< configures the horizontal synchronization polarity.
00088                                                       This parameter can be one value of @ref LTDC_HS_POLARITY */
00089
00090   uint32_t            VSPolarity;                /*!< configures the vertical synchronization polarity.
00091                                                       This parameter can be one value of @ref LTDC_VS_POLARITY */
00092
00093   uint32_t            DEPolarity;                /*!< configures the data enable polarity.
00094                                                       This parameter can be one of value of @ref LTDC_DE_POLARITY */
00095
00096   uint32_t            PCPolarity;                /*!< configures the pixel clock polarity.
00097                                                       This parameter can be one of value of @ref LTDC_PC_POLARITY */
00098
00099   uint32_t            HorizontalSync;            /*!< configures the number of Horizontal synchronization width.
00100                                                       This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
00101
00102   uint32_t            VerticalSync;              /*!< configures the number of Vertical synchronization height.
00103                                                       This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
00104
00105   uint32_t            AccumulatedHBP;            /*!< configures the accumulated horizontal back porch width.
00106                                                       This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
00107
00108   uint32_t            AccumulatedVBP;            /*!< configures the accumulated vertical back porch height.
00109                                                       This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
00110
00111   uint32_t            AccumulatedActiveW;        /*!< configures the accumulated active width.
00112                                                       This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
00113
00114   uint32_t            AccumulatedActiveH;        /*!< configures the accumulated active height.
00115                                                       This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
00116
00117   uint32_t            TotalWidth;                /*!< configures the total width.
00118                                                       This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
00119
00120   uint32_t            TotalHeigh;                /*!< configures the total height.
00121                                                       This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
00122
00123   LTDC_ColorTypeDef   Backcolor;                 /*!< Configures the background color. */
00124 } LTDC_InitTypeDef;
00125
00126 /**
00127   * @brief  LTDC Layer structure definition
00128   */
00129 typedef struct
00130 {
00131   uint32_t WindowX0;                   /*!< Configures the Window Horizontal Start Position.
00132                                             This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
00133
00134   uint32_t WindowX1;                   /*!< Configures the Window Horizontal Stop Position.
00135                                             This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
00136
00137   uint32_t WindowY0;                   /*!< Configures the Window vertical Start Position.
00138                                             This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
00139
00140   uint32_t WindowY1;                   /*!< Configures the Window vertical Stop Position.
00141                                             This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */
00142
00143   uint32_t PixelFormat;                /*!< Specifies the pixel format.
00144                                             This parameter can be one of value of @ref LTDC_Pixelformat */
00145
00146   uint32_t Alpha;                      /*!< Specifies the constant alpha used for blending.
00147                                             This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00148
00149   uint32_t Alpha0;                     /*!< Configures the default alpha value.
00150                                             This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00151
00152   uint32_t BlendingFactor1;            /*!< Select the blending factor 1.
00153                                             This parameter can be one of value of @ref LTDC_BlendingFactor1 */
00154
00155   uint32_t BlendingFactor2;            /*!< Select the blending factor 2.
00156                                             This parameter can be one of value of @ref LTDC_BlendingFactor2 */
00157
00158   uint32_t FBStartAdress;              /*!< Configures the color frame buffer address */
00159
00160   uint32_t ImageWidth;                 /*!< Configures the color frame buffer line length.
00161                                             This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */
00162
00163   uint32_t ImageHeight;                /*!< Specifies the number of line in frame buffer.
00164                                             This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
00165
00166   LTDC_ColorTypeDef   Backcolor;       /*!< Configures the layer background color. */
00167 } LTDC_LayerCfgTypeDef;
00168
00169 /**
00170   * @brief  HAL LTDC State enumeration definition
00171   */
00172 typedef enum
00173 {
00174   HAL_LTDC_STATE_RESET             = 0x00U,    /*!< LTDC not yet initialized or disabled */
00175   HAL_LTDC_STATE_READY             = 0x01U,    /*!< LTDC initialized and ready for use   */
00176   HAL_LTDC_STATE_BUSY              = 0x02U,    /*!< LTDC internal process is ongoing     */
00177   HAL_LTDC_STATE_TIMEOUT           = 0x03U,    /*!< LTDC Timeout state                   */
00178   HAL_LTDC_STATE_ERROR             = 0x04U     /*!< LTDC state error                     */
00179 }HAL_LTDC_StateTypeDef;
00180
00181 /**
00182   * @brief  LTDC handle Structure definition
00183   */
00184 typedef struct
00185 {
00186   LTDC_TypeDef                *Instance;                /*!< LTDC Register base address                */
00187
00188   LTDC_InitTypeDef            Init;                     /*!< LTDC parameters                           */
00189
00190   LTDC_LayerCfgTypeDef        LayerCfg[MAX_LAYER];      /*!< LTDC Layers parameters                    */
00191
00192   HAL_LockTypeDef             Lock;                     /*!< LTDC Lock                                 */
00193
00194   __IO HAL_LTDC_StateTypeDef  State;                    /*!< LTDC state                                */
00195
00196   __IO uint32_t               ErrorCode;                /*!< LTDC Error code                           */
00197
00198 } LTDC_HandleTypeDef;
00199 /**
00200   * @}
00201   */
00202
00203 /* Exported constants --------------------------------------------------------*/
00204 /** @defgroup LTDC_Exported_Constants LTDC Exported Constants
00205   * @{
00206   */
00207
00208 /** @defgroup LTDC_Error_Code LTDC Error Code
00209   * @{
00210   */
00211 #define HAL_LTDC_ERROR_NONE      (0x00000000U)    /*!< LTDC No error             */
00212 #define HAL_LTDC_ERROR_TE        (0x00000001U)    /*!< LTDC Transfer error       */
00213 #define HAL_LTDC_ERROR_FU        (0x00000002U)    /*!< LTDC FIFO Underrun        */
00214 #define HAL_LTDC_ERROR_TIMEOUT   (0x00000020U)    /*!< LTDC Timeout error        */
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup LTDC_Layer LTDC Layer
00220   * @{
00221   */
00222 #define LTDC_LAYER_1                      (0x00000000U)   /*!< LTDC Layer 1 */
00223 #define LTDC_LAYER_2                      (0x00000001U)   /*!< LTDC Layer 2 */
00224 /**
00225   * @}
00226   */
00227
00228
00229 /** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY
00230   * @{
00231   */
00232 #define LTDC_HSPOLARITY_AL                (0x00000000U)                /*!< Horizontal Synchronization is active low. */
00233 #define LTDC_HSPOLARITY_AH                LTDC_GCR_HSPOL               /*!< Horizontal Synchronization is active high. */
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY
00239   * @{
00240   */
00241 #define LTDC_VSPOLARITY_AL                (0x00000000U)                /*!< Vertical Synchronization is active low. */
00242 #define LTDC_VSPOLARITY_AH                LTDC_GCR_VSPOL               /*!< Vertical Synchronization is active high. */
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY
00248   * @{
00249   */
00250 #define LTDC_DEPOLARITY_AL                (0x00000000U)                /*!< Data Enable, is active low. */
00251 #define LTDC_DEPOLARITY_AH                LTDC_GCR_DEPOL               /*!< Data Enable, is active high. */
00252 /**
00253   * @}
00254   */
00255
00256 /** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY
00257   * @{
00258   */
00259 #define LTDC_PCPOLARITY_IPC               (0x00000000U)                /*!< input pixel clock. */
00260 #define LTDC_PCPOLARITY_IIPC              LTDC_GCR_PCPOL               /*!< inverted input pixel clock. */
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup LTDC_SYNC LTDC SYNC
00266   * @{
00267   */
00268 #define LTDC_HORIZONTALSYNC               (LTDC_SSCR_HSW >> 16)                 /*!< Horizontal synchronization width. */
00269 #define LTDC_VERTICALSYNC                 LTDC_SSCR_VSH                         /*!< Vertical synchronization height. */
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR
00275   * @{
00276   */
00277 #define LTDC_COLOR                   (0x000000FFU)                     /*!< Color mask */
00278 /**
00279   * @}
00280   */
00281
00282 /** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1
00283   * @{
00284   */
00285 #define LTDC_BLENDING_FACTOR1_CA                       (0x00000400U)   /*!< Blending factor : Cte Alpha */
00286 #define LTDC_BLENDING_FACTOR1_PAxCA                    (0x00000600U)   /*!< Blending factor : Cte Alpha x Pixel Alpha*/
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2
00292   * @{
00293   */
00294 #define LTDC_BLENDING_FACTOR2_CA                       (0x00000005U)   /*!< Blending factor : Cte Alpha */
00295 #define LTDC_BLENDING_FACTOR2_PAxCA                    (0x00000007U)   /*!< Blending factor : Cte Alpha x Pixel Alpha*/
00296 /**
00297   * @}
00298   */
00299
00300 /** @defgroup LTDC_Pixelformat LTDC Pixel format
00301   * @{
00302   */
00303 #define LTDC_PIXEL_FORMAT_ARGB8888                  (0x00000000U)      /*!< ARGB8888 LTDC pixel format */
00304 #define LTDC_PIXEL_FORMAT_RGB888                    (0x00000001U)      /*!< RGB888 LTDC pixel format   */
00305 #define LTDC_PIXEL_FORMAT_RGB565                    (0x00000002U)      /*!< RGB565 LTDC pixel format   */
00306 #define LTDC_PIXEL_FORMAT_ARGB1555                  (0x00000003U)      /*!< ARGB1555 LTDC pixel format */
00307 #define LTDC_PIXEL_FORMAT_ARGB4444                  (0x00000004U)      /*!< ARGB4444 LTDC pixel format */
00308 #define LTDC_PIXEL_FORMAT_L8                        (0x00000005U)      /*!< L8 LTDC pixel format       */
00309 #define LTDC_PIXEL_FORMAT_AL44                      (0x00000006U)      /*!< AL44 LTDC pixel format     */
00310 #define LTDC_PIXEL_FORMAT_AL88                      (0x00000007U)      /*!< AL88 LTDC pixel format     */
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup LTDC_Alpha LTDC Alpha
00316   * @{
00317   */
00318 #define LTDC_ALPHA               LTDC_LxCACR_CONSTA                    /*!< LTDC Cte Alpha mask */
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup LTDC_LAYER_Config LTDC LAYER Config
00324   * @{
00325   */
00326 #define LTDC_STOPPOSITION                 (LTDC_LxWHPCR_WHSPPOS >> 16)          /*!< LTDC Layer stop position  */
00327 #define LTDC_STARTPOSITION                LTDC_LxWHPCR_WHSTPOS                  /*!< LTDC Layer start position */
00328
00329 #define LTDC_COLOR_FRAME_BUFFER           LTDC_LxCFBLR_CFBLL                    /*!< LTDC Layer Line length    */
00330 #define LTDC_LINE_NUMBER                  LTDC_LxCFBLNR_CFBLNBR                 /*!< LTDC Layer Line number    */
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup LTDC_Interrupts LTDC Interrupts
00336   * @{
00337   */
00338 #define LTDC_IT_LI                      LTDC_IER_LIE
00339 #define LTDC_IT_FU                      LTDC_IER_FUIE
00340 #define LTDC_IT_TE                      LTDC_IER_TERRIE
00341 #define LTDC_IT_RR                      LTDC_IER_RRIE
00342 /**
00343   * @}
00344   */
00345
00346 /** @defgroup LTDC_Flags LTDC Flags
00347   * @{
00348   */
00349 #define LTDC_FLAG_LI                     LTDC_ISR_LIF
00350 #define LTDC_FLAG_FU                     LTDC_ISR_FUIF
00351 #define LTDC_FLAG_TE                     LTDC_ISR_TERRIF
00352 #define LTDC_FLAG_RR                     LTDC_ISR_RRIF
00353 /**
00354   * @}
00355   */
00356
00357 /** @defgroup LTDC_Reload_Type LTDC Reload Type
00358   * @{
00359   */
00360 #define LTDC_RELOAD_IMMEDIATE            LTDC_SRCR_IMR       /*!< Immediate Reload */
00361 #define LTDC_RELOAD_VERTICAL_BLANKING    LTDC_SRCR_VBR       /*!< Vertical Blanking Reload */
00362 /**
00363   * @}
00364   */
00365
00366 /**
00367   * @}
00368   */
00369
00370 /* Exported macro ------------------------------------------------------------*/
00371 /** @defgroup LTDC_Exported_Macros LTDC Exported Macros
00372   * @{
00373   */
00374
00375 /** @brief Reset LTDC handle state.
00376   * @param  __HANDLE__  LTDC handle
00377   * @retval None
00378   */
00379 #define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
00380
00381 /**
00382   * @brief  Enable the LTDC.
00383   * @param  __HANDLE__: LTDC handle
00384   * @retval None.
00385   */
00386 #define __HAL_LTDC_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
00387
00388 /**
00389   * @brief  Disable the LTDC.
00390   * @param  __HANDLE__: LTDC handle
00391   * @retval None.
00392   */
00393 #define __HAL_LTDC_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
00394
00395 /**
00396   * @brief  Enable the LTDC Layer.
00397   * @param  __HANDLE__  LTDC handle
00398   * @param  __LAYER__   Specify the layer to be enabled.
00399   *                     This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
00400   * @retval None.
00401   */
00402 #define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__)  ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
00403
00404 /**
00405   * @brief  Disable the LTDC Layer.
00406   * @param  __HANDLE__  LTDC handle
00407   * @param  __LAYER__   Specify the layer to be disabled.
00408   *                     This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
00409   * @retval None.
00410   */
00411 #define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
00412
00413 /**
00414   * @brief  Reload immediately all LTDC Layers.
00415   * @param  __HANDLE__  LTDC handle
00416   * @retval None.
00417   */
00418 #define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__)  ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
00419
00420 /**
00421   * @brief  Reload during vertical blanking period all LTDC Layers.
00422   * @param  __HANDLE__  LTDC handle
00423   * @retval None.
00424   */
00425 #define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__)  ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR)
00426
00427 /* Interrupt & Flag management */
00428 /**
00429   * @brief  Get the LTDC pending flags.
00430   * @param  __HANDLE__: LTDC handle
00431   * @param  __FLAG__: Get the specified flag.
00432   *          This parameter can be any combination of the following values:
00433   *            @arg LTDC_FLAG_LI: Line Interrupt flag
00434   *            @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
00435   *            @arg LTDC_FLAG_TE: Transfer Error interrupt flag
00436   *            @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
00437   * @retval The state of FLAG (SET or RESET).
00438   */
00439 #define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
00440
00441 /**
00442   * @brief  Clears the LTDC pending flags.
00443   * @param  __HANDLE__: LTDC handle
00444   * @param  __FLAG__: specifies the flag to clear.
00445   *          This parameter can be any combination of the following values:
00446   *            @arg LTDC_FLAG_LI: Line Interrupt flag
00447   *            @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
00448   *            @arg LTDC_FLAG_TE: Transfer Error interrupt flag
00449   *            @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
00450   * @retval None
00451   */
00452 #define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00453
00454 /**
00455   * @brief  Enables the specified LTDC interrupts.
00456   * @param  __HANDLE__: LTDC handle
00457   * @param __INTERRUPT__: specifies the LTDC interrupt sources to be enabled.
00458   *          This parameter can be any combination of the following values:
00459   *            @arg LTDC_IT_LI: Line Interrupt flag
00460   *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
00461   *            @arg LTDC_IT_TE: Transfer Error interrupt flag
00462   *            @arg LTDC_IT_RR: Register Reload Interrupt Flag
00463   * @retval None
00464   */
00465 #define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
00466
00467 /**
00468   * @brief  Disables the specified LTDC interrupts.
00469   * @param  __HANDLE__: LTDC handle
00470   * @param __INTERRUPT__: specifies the LTDC interrupt sources to be disabled.
00471   *          This parameter can be any combination of the following values:
00472   *            @arg LTDC_IT_LI: Line Interrupt flag
00473   *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
00474   *            @arg LTDC_IT_TE: Transfer Error interrupt flag
00475   *            @arg LTDC_IT_RR: Register Reload Interrupt Flag
00476   * @retval None
00477   */
00478 #define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
00479
00480 /**
00481   * @brief  Checks whether the specified LTDC interrupt has occurred or not.
00482   * @param  __HANDLE__: LTDC handle
00483   * @param  __INTERRUPT__: specifies the LTDC interrupt source to check.
00484   *          This parameter can be one of the following values:
00485   *            @arg LTDC_IT_LI: Line Interrupt flag
00486   *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
00487   *            @arg LTDC_IT_TE: Transfer Error interrupt flag
00488   *            @arg LTDC_IT_RR: Register Reload Interrupt Flag
00489   * @retval The state of INTERRUPT (SET or RESET).
00490   */
00491 #define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
00492 /**
00493   * @}
00494   */
00495
00496 #if defined(DSI)
00497 /* Include LTDC HAL Extension module */
00498 #include "stm32h7xx_hal_ltdc_ex.h"
00499
00500 #endif /*DSI*/
00501
00502 /* Exported functions --------------------------------------------------------*/
00503 /** @addtogroup LTDC_Exported_Functions
00504   * @{
00505   */
00506 /** @addtogroup LTDC_Exported_Functions_Group1
00507   * @{
00508   */
00509 /* Initialization and de-initialization functions *****************************/
00510 HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);
00511 HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
00512 void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc);
00513 void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc);
00514 void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
00515 void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc);
00516 void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);
00517 /**
00518   * @}
00519   */
00520
00521 /** @addtogroup LTDC_Exported_Functions_Group2
00522   * @{
00523   */
00524 /* IO operation functions *****************************************************/
00525 void  HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);
00526 /**
00527   * @}
00528   */
00529
00530 /** @addtogroup LTDC_Exported_Functions_Group3
00531   * @{
00532   */
00533 /* Peripheral Control functions ***********************************************/
00534 HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
00535 HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
00536 HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
00537 HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
00538 HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
00539 HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
00540 HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
00541 HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
00542 HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);
00543 HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00544 HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00545 HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00546 HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00547 HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);
00548 HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
00549 HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
00550 HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType);
00551 HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
00552 HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
00553 HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
00554 HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
00555 HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
00556 HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
00557 HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
00558 HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
00559 HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00560 HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00561 HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00562 HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00563
00564 /**
00565   * @}
00566   */
00567
00568 /** @addtogroup LTDC_Exported_Functions_Group4
00569   * @{
00570   */
00571 /* Peripheral State functions *************************************************/
00572 HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);
00573 uint32_t              HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
00574 /**
00575   * @}
00576   */
00577
00578 /**
00579   * @}
00580   */
00581 /* Private types -------------------------------------------------------------*/
00582 /** @defgroup LTDC_Private_Types LTDC Private Types
00583   * @{
00584   */
00585
00586 /**
00587   * @}
00588   */
00589
00590 /* Private variables ---------------------------------------------------------*/
00591 /** @defgroup LTDC_Private_Variables LTDC Private Variables
00592   * @{
00593   */
00594
00595 /**
00596   * @}
00597   */
00598
00599 /* Private constants ---------------------------------------------------------*/
00600 /** @defgroup LTDC_Private_Constants LTDC Private Constants
00601   * @{
00602   */
00603
00604 /**
00605   * @}
00606   */
00607
00608 /* Private macros ------------------------------------------------------------*/
00609 /** @defgroup LTDC_Private_Macros LTDC Private Macros
00610   * @{
00611   */
00612 #define LTDC_LAYER(__HANDLE__, __LAYER__)              ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__)))))
00613 #define IS_LTDC_LAYER(__LAYER__)                       ((__LAYER__) < MAX_LAYER)
00614 #define IS_LTDC_HSPOL(__HSPOL__)                       (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
00615 #define IS_LTDC_VSPOL(__VSPOL__)                       (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
00616 #define IS_LTDC_DEPOL(__DEPOL__)                       (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) ==  LTDC_DEPOLARITY_AH))
00617 #define IS_LTDC_PCPOL(__PCPOL__)                       (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) ==  LTDC_PCPOLARITY_IIPC))
00618 #define IS_LTDC_HSYNC(__HSYNC__)                       ((__HSYNC__)  <= LTDC_HORIZONTALSYNC)
00619 #define IS_LTDC_VSYNC(__VSYNC__)                       ((__VSYNC__)  <= LTDC_VERTICALSYNC)
00620 #define IS_LTDC_AHBP(__AHBP__)                         ((__AHBP__)   <= LTDC_HORIZONTALSYNC)
00621 #define IS_LTDC_AVBP(__AVBP__)                         ((__AVBP__)   <= LTDC_VERTICALSYNC)
00622 #define IS_LTDC_AAW(__AAW__)                           ((__AAW__)    <= LTDC_HORIZONTALSYNC)
00623 #define IS_LTDC_AAH(__AAH__)                           ((__AAH__)    <= LTDC_VERTICALSYNC)
00624 #define IS_LTDC_TOTALW(__TOTALW__)                     ((__TOTALW__) <= LTDC_HORIZONTALSYNC)
00625 #define IS_LTDC_TOTALH(__TOTALH__)                     ((__TOTALH__) <= LTDC_VERTICALSYNC)
00626 #define IS_LTDC_BLUEVALUE(__BBLUE__)                   ((__BBLUE__)  <= LTDC_COLOR)
00627 #define IS_LTDC_GREENVALUE(__BGREEN__)                 ((__BGREEN__) <= LTDC_COLOR)
00628 #define IS_LTDC_REDVALUE(__BRED__)                     ((__BRED__)   <= LTDC_COLOR)
00629 #define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \
00630                                                         ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA))
00631 #define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR2__) (((__BLENDING_FACTOR2__) == LTDC_BLENDING_FACTOR2_CA) || \
00632                                                         ((__BLENDING_FACTOR2__) == LTDC_BLENDING_FACTOR2_PAxCA))
00633
00634 #define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__)         (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888)   || \
00635                                                         ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565)   || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \
00636                                                         ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8)       || \
00637                                                         ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44)     || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))
00638
00639 #define IS_LTDC_ALPHA(__ALPHA__)                       ((__ALPHA__) <= LTDC_ALPHA)
00640 #define IS_LTDC_HCONFIGST(__HCONFIGST__)               ((__HCONFIGST__) <= LTDC_STARTPOSITION)
00641 #define IS_LTDC_HCONFIGSP(__HCONFIGSP__)               ((__HCONFIGSP__) <= LTDC_STOPPOSITION)
00642 #define IS_LTDC_VCONFIGST(__VCONFIGST__)               ((__VCONFIGST__) <= LTDC_STARTPOSITION)
00643 #define IS_LTDC_VCONFIGSP(__VCONFIGSP__)               ((__VCONFIGSP__) <= LTDC_STOPPOSITION)
00644 #define IS_LTDC_CFBP(__CFBP__)                         ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER)
00645 #define IS_LTDC_CFBLL(__CFBLL__)                       ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)
00646 #define IS_LTDC_CFBLNBR(__CFBLNBR__)                   ((__CFBLNBR__) <= LTDC_LINE_NUMBER)
00647 #define IS_LTDC_LIPOS(__LIPOS__)                       ((__LIPOS__) <= 0x7FFU)
00648 #define IS_LTDC_RELOAD(__RELOADTYPE__)                 (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))
00649 /**
00650   * @}
00651   */
00652
00653 /* Private functions ---------------------------------------------------------*/
00654 /** @defgroup LTDC_Private_Functions LTDC Private Functions
00655   * @{
00656   */
00657
00658 /**
00659   * @}
00660   */
00661
00662 /**
00663   * @}
00664   */
00665
00666 /**
00667   * @}
00668   */
00669
00670 #ifdef __cplusplus
00671 }
00672 #endif
00673
00674 #endif /* __STM32H7xx_HAL_LTDC_H */
00675
00676 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_mdios.c Source File

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stm32h7xx_hal_mdios.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_mdios.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   MDIOS HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the MDIOS Peripheral.
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *
00014   *
00015   @verbatim
00016  ===============================================================================
00017                         ##### How to use this driver #####
00018  ===============================================================================
00019     [..]
00020     The MDIOS HAL driver can be used as follow:
00021
00022     (#) Declare a MDIOS_HandleTypeDef handle structure.
00023
00024     (#) Initialize the MDIOS low level resources by implementing the HAL_MDIOS_MspInit() API:
00025         (##) Enable the MDIOS interface clock.
00026         (##) MDIOS pins configuration:
00027             (+++) Enable clocks for the MDIOS GPIOs.
00028             (+++) Configure the MDIOS pins as alternate function.
00029         (##) NVIC configuration if you need to use interrupt process:
00030             (+++) Configure the MDIOS interrupt priority.
00031             (+++) Enable the NVIC MDIOS IRQ handle.
00032
00033     (#) Program the Port Address and the Preamble Check in the Init structure.
00034
00035     (#) Initialize the MDIOS registers by calling the HAL_MDIOS_Init() API.
00036
00037     (#) Perform direct slave read/write operations using the following APIs:
00038         (##) Read the value of a DINn register: HAL_MDIOS_ReadReg()
00039         (##) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()
00040
00041     (#) Get the Master read/write operations flags using the following APIs:
00042         (##) Bit map of DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()
00043         (##) Bit map of DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()
00044
00045     (#) Clear the read/write flags using the following APIs:
00046         (##) Clear read flags of a set of registers: HAL_MDIOS_ClearReadRegAddress()
00047         (##) Clear write flags of a set of registers: HAL_MDIOS_ClearWriteRegAddress()
00048
00049     (#) Enable interrupts on events using HAL_MDIOS_EnableEvents(), when called
00050         the MDIOS will generate an interrupt in the following cases:
00051         (##) a DINn register written by the Master
00052         (##) a DOUTn register read by the Master
00053         (##) an error occur
00054
00055         (@) A callback is executed for each genereted interrupt, so the driver provide the following
00056             HAL_MDIOS_WriteCpltCallback(), HAL_MDIOS_ReadCpltCallback() and HAL_MDIOS_ErrorCallback()
00057         (@) HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt
00058             and execute the previous callbacks
00059
00060     (#) Reset the MDIOS peripheral and all related ressources by calling the HAL_MDIOS_DeInit() API.
00061         (##) HAL_MDIOS_MspDeInit() must be implemented to reset low level ressources
00062             (GPIO, Clocks, NVIC configuration ...)
00063
00064
00065   @endverbatim
00066   ******************************************************************************
00067   * @attention
00068   *
00069   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00070   *
00071   * Redistribution and use in source and binary forms, with or without modification,
00072   * are permitted provided that the following conditions are met:
00073   *   1. Redistributions of source code must retain the above copyright notice,
00074   *      this list of conditions and the following disclaimer.
00075   *   2. Redistributions in binary form must reproduce the above copyright notice,
00076   *      this list of conditions and the following disclaimer in the documentation
00077   *      and/or other materials provided with the distribution.
00078   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00079   *      may be used to endorse or promote products derived from this software
00080   *      without specific prior written permission.
00081   *
00082   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00083   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00084   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00085   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00086   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00087   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00088   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00089   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00090   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00091   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00092   *
00093   ******************************************************************************
00094   */
00095
00096 /* Includes ------------------------------------------------------------------*/
00097 #include "stm32h7xx_hal.h"
00098
00099 /** @addtogroup STM32H7xx_HAL_Driver
00100   * @{
00101   */
00102 /** @defgroup MDIOS  MDIOS
00103   * @brief HAL MDIOS module driver
00104   * @{
00105   */
00106 #ifdef HAL_MDIOS_MODULE_ENABLED
00107
00108
00109
00110 /* Private typedef -----------------------------------------------------------*/
00111 /* Private define ------------------------------------------------------------*/
00112 #define MDIOS_PORT_ADDRESS_SHIFT        ((uint32_t)8)
00113 #define MDIOS_ALL_REG_FLAG              ((uint32_t)0xFFFFFFFFU)
00114 #define MDIOS_ALL_ERRORS_FLAG           ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF))
00115
00116 #define MDIOS_DIN_BASE_ADDR             (MDIOS_BASE + 0x100)
00117 #define MDIOS_DOUT_BASE_ADDR            (MDIOS_BASE + 0x180)
00118
00119 /* Private macro -------------------------------------------------------------*/
00120 /* Private variables ---------------------------------------------------------*/
00121 /* Private function prototypes -----------------------------------------------*/
00122 /* Private functions ---------------------------------------------------------*/
00123 /* Exported functions --------------------------------------------------------*/
00124 /** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions
00125   * @{
00126   */
00127
00128 /** @defgroup MDIOS_Exported_Functions_Group1 Initialization/de-initialization functions
00129   *  @brief    Initialization and Configuration functions
00130   *
00131 @verbatim
00132 ===============================================================================
00133             ##### Initialization and Configuration functions #####
00134  ===============================================================================
00135     [..]
00136     This subsection provides a set of functions allowing to initialize the MDIOS
00137       (+) The following parameters can be configured:
00138         (++) Port Address
00139         (++) Preamble Check
00140
00141 @endverbatim
00142   * @{
00143   */
00144
00145 /**
00146   * @brief  Initializes the MDIOS according to the specified parameters in
00147   *         the MDIOS_InitTypeDef and creates the associated handle .
00148   * @param  hmdios: pointer to a MDIOS_HandleTypeDef structure that contains
00149   *         the configuration information for MDIOS module
00150   * @retval HAL status
00151   */
00152 HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios)
00153 {
00154   uint32_t tmpcr = 0;
00155
00156   /* Check the MDIOS handle allocation */
00157   if(hmdios == NULL)
00158   {
00159     return HAL_ERROR;
00160   }
00161
00162   /* Check the parameters */
00163   assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance));
00164   assert_param(IS_MDIOS_PORTADDRESS(hmdios->Init.PortAddress));
00165   assert_param(IS_MDIOS_PREAMBLECHECK(hmdios->Init.PreambleCheck));
00166
00167   /* Process Locked */
00168   __HAL_LOCK(hmdios);
00169
00170   if(hmdios->State == HAL_MDIOS_STATE_RESET)
00171   {
00172     /* Init the low level hardware */
00173     HAL_MDIOS_MspInit(hmdios);
00174   }
00175
00176   /* Change the MDIOS state */
00177   hmdios->State = HAL_MDIOS_STATE_BUSY;
00178
00179   /* Get the MDIOS CR value */
00180   tmpcr = hmdios->Instance->CR;
00181
00182   /* Clear PORT_ADDRESS, DPC and EN bits */
00183   tmpcr &= ((uint32_t)~(MDIOS_CR_EN | MDIOS_CR_DPC | MDIOS_CR_PORT_ADDRESS));
00184
00185   /* Set MDIOS control parametrs and enable the peripheral */
00186   tmpcr |=  (uint32_t)(((hmdios->Init.PortAddress) << MDIOS_PORT_ADDRESS_SHIFT)    |\
00187                         (hmdios->Init.PreambleCheck) | \
00188                         (MDIOS_CR_EN));
00189
00190   /* Write the MDIOS CR */
00191   hmdios->Instance->CR = tmpcr;
00192
00193   /* Change the MDIOS state */
00194   hmdios->State = HAL_MDIOS_STATE_READY;
00195
00196   /* Release Lock */
00197   __HAL_UNLOCK(hmdios);
00198
00199   /* Return function status */
00200   return HAL_OK;
00201
00202 }
00203
00204 /**
00205   * @brief  DeInitializes the MDIOS peripheral.
00206   * @param  hmdios: MDIOS handle
00207   * @retval HAL status
00208   */
00209 HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios)
00210 {
00211   /* Check the MDIOS handle allocation */
00212   if(hmdios == NULL)
00213   {
00214     return HAL_ERROR;
00215   }
00216
00217   /* Check the parameters */
00218   assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance));
00219
00220   /* Change the MDIOS state */
00221   hmdios->State = HAL_MDIOS_STATE_BUSY;
00222
00223   /* Disable the Peripheral */
00224   __HAL_MDIOS_DISABLE(hmdios);
00225
00226   /* DeInit the low level hardware */
00227   HAL_MDIOS_MspDeInit(hmdios);
00228
00229   /* Change the MDIOS state */
00230   hmdios->State = HAL_MDIOS_STATE_RESET;
00231
00232   /* Release Lock */
00233   __HAL_UNLOCK(hmdios);
00234
00235   /* Return function status */
00236   return HAL_OK;
00237 }
00238
00239 /**
00240   * @brief  MDIOS MSP Init
00241   * @param  hmdios: mdios handle
00242   * @retval None
00243   */
00244  __weak void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios)
00245 {
00246   /* Prevent unused argument(s) compilation warning */
00247   UNUSED(hmdios);
00248
00249   /* NOTE : This function should not be modified, when the callback is needed,
00250             the HAL_MDIOS_MspInit can be implemented in the user file
00251    */
00252 }
00253
00254 /**
00255   * @brief  MDIOS MSP DeInit
00256   * @param  hmdios: mdios handle
00257   * @retval None
00258   */
00259  __weak void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios)
00260 {
00261   /* Prevent unused argument(s) compilation warning */
00262   UNUSED(hmdios);
00263
00264   /* NOTE : This function should not be modified, when the callback is needed,
00265             the HAL_MDIOS_MspDeInit can be implemented in the user file
00266    */
00267 }
00268
00269 /** @defgroup MDIOS_Exported_Functions_Group2 IO operation functions
00270   *  @brief MDIOS Read/Write functions
00271   *
00272 @verbatim
00273  ===============================================================================
00274                       ##### IO operation functions #####
00275  ===============================================================================
00276     This subsection provides a set of functions allowing to manage the MDIOS
00277     read and write operations.
00278
00279     (#) APIs that allow to the MDIOS to read/write from/to the
00280         values of one of the DINn/DOUTn registers:
00281         (+) Read the value of a DINn register: HAL_MDIOS_ReadReg()
00282         (+) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()
00283
00284     (#) APIs that provide if there are some Slave registres have been
00285         read or written by the Master:
00286         (+) DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()
00287         (+) DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()
00288
00289     (#) APIs that Clear the read/write flags:
00290         (+) Clear read registers flags: HAL_MDIOS_ClearReadRegAddress()
00291         (+) Clear write registers flags: HAL_MDIOS_ClearWriteRegAddress()
00292
00293     (#) A set of Callbacks are provided:
00294         (+) HAL_MDIOS_WriteCpltCallback()
00295         (+) HAL_MDIOS_ReadCpltCallback()
00296         (+) HAL_MDIOS_ErrorCallback()
00297
00298 @endverbatim
00299   * @{
00300   */
00301
00302 /**
00303   * @brief  Writes to an MDIOS output register
00304   * @param  hmdios: mdios handle
00305   * @param  RegNum: MDIOS output register address
00306   * @param  Data: Data to write
00307   * @retval HAL status
00308   */
00309 HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data)
00310 {
00311   uint32_t tmpreg;
00312
00313   /* Check the parameters */
00314   assert_param(IS_MDIOS_REGISTER(RegNum));
00315
00316   /* Process Locked */
00317   __HAL_LOCK(hmdios);
00318
00319   /* Get the addr of output register to be written by the MDIOS */
00320   tmpreg = MDIOS_DOUT_BASE_ADDR + (4 * RegNum);
00321
00322   /* Write to DOUTn register */
00323   *((uint32_t *)tmpreg) = Data;
00324
00325     /* Process Unlocked */
00326   __HAL_UNLOCK(hmdios);
00327
00328   return HAL_OK;
00329 }
00330
00331 /**
00332   * @brief  Reads an MDIOS input register
00333   * @param  hmdios: mdios handle
00334   * @param  RegNum: MDIOS input register address
00335   * @param  pData: pointer to Data
00336   * @retval HAL status
00337   */
00338 HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData)
00339 {
00340   uint32_t tmpreg;
00341
00342   /* Check the parameters */
00343   assert_param(IS_MDIOS_REGISTER(RegNum));
00344
00345   /* Process Locked */
00346   __HAL_LOCK(hmdios);
00347
00348   /* Get the addr of input register to be read by the MDIOS */
00349   tmpreg = MDIOS_DIN_BASE_ADDR + (4 * RegNum);
00350
00351   /* Read DINn register */
00352   *pData = (uint16_t)(*((uint32_t *)tmpreg));
00353
00354   /* Process Unlocked */
00355   __HAL_UNLOCK(hmdios);
00356
00357   return HAL_OK;
00358 }
00359
00360 /**
00361   * @brief  Gets Written registers by MDIO master
00362   * @param  hmdios: mdios handle
00363   * @retval bit map of written registers addresses
00364   */
00365 uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios)
00366 {
00367   return hmdios->Instance->WRFR;
00368 }
00369
00370 /**
00371   * @brief  Gets Read registers by MDIO master
00372   * @param  hmdios: mdios handle
00373   * @retval bit map of read registers addresses
00374   */
00375 uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios)
00376 {
00377   return hmdios->Instance->RDFR;
00378 }
00379
00380 /**
00381   * @brief  Clears Write registers flag
00382   * @param  hmdios: mdios handle
00383   * @param  RegNum: registers addresses to be cleared
00384   * @retval HAL status
00385   */
00386 HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
00387 {
00388   /* Check the parameters */
00389   assert_param(IS_MDIOS_REGISTER(RegNum));
00390
00391   /* Process Locked */
00392   __HAL_LOCK(hmdios);
00393
00394   /* Clear write registers flags */
00395   hmdios->Instance->CWRFR |= (RegNum);
00396
00397   /* Release Lock */
00398   __HAL_UNLOCK(hmdios);
00399
00400   return HAL_OK;
00401 }
00402
00403 /**
00404   * @brief  Clears Read register flag
00405   * @param  hmdios: mdios handle
00406   * @param  RegNum: registers addresses to be cleared
00407   * @retval HAL status
00408   */
00409 HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
00410 {
00411   /* Check the parameters */
00412   assert_param(IS_MDIOS_REGISTER(RegNum));
00413
00414   /* Process Locked */
00415   __HAL_LOCK(hmdios);
00416
00417   /* Clear read registers flags */
00418   hmdios->Instance->CRDFR |= (RegNum);
00419
00420   /* Release Lock */
00421   __HAL_UNLOCK(hmdios);
00422
00423   return HAL_OK;
00424 }
00425
00426 /**
00427   * @brief  Enables Events for MDIOS peripheral
00428   * @param  hmdios: mdios handle
00429   * @retval HAL status
00430   */
00431 HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios)
00432 {
00433   /* Process Locked */
00434   __HAL_LOCK(hmdios);
00435
00436   /* Enable MDIOS interrupts: Register Write, Register Read and Error ITs */
00437   __HAL_MDIOS_ENABLE_IT(hmdios, (MDIOS_IT_WRITE | MDIOS_IT_READ | MDIOS_IT_ERROR));
00438
00439   /* Process Unlocked */
00440   __HAL_UNLOCK(hmdios);
00441
00442   return HAL_OK;
00443 }
00444
00445 /**
00446   * @brief This function handles MDIOS interrupt request.
00447   * @param hmdios: MDIOS handle
00448   * @retval None
00449   */
00450 void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios)
00451 {
00452   /* Write Register Interrupt enabled ? */
00453   if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_WRITE) != RESET)
00454   {
00455     /* Write register flag */
00456     if(HAL_MDIOS_GetWrittenRegAddress(hmdios) != RESET)
00457     {
00458       /* Write callback function */
00459       HAL_MDIOS_WriteCpltCallback(hmdios);
00460
00461       /* Clear write register flag */
00462       HAL_MDIOS_ClearWriteRegAddress(hmdios, MDIOS_ALL_REG_FLAG);
00463     }
00464   }
00465
00466   /* Read Register Interrupt enabled ? */
00467   if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_READ) != RESET)
00468   {
00469     /* Read register flag */
00470     if(HAL_MDIOS_GetReadRegAddress(hmdios) != RESET)
00471     {
00472       /* Read callback function  */
00473       HAL_MDIOS_ReadCpltCallback(hmdios);
00474
00475       /* Clear read register flag */
00476       HAL_MDIOS_ClearReadRegAddress(hmdios, MDIOS_ALL_REG_FLAG);
00477     }
00478   }
00479
00480   /* Error Interrupt enabled ? */
00481   if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_ERROR) != RESET)
00482   {
00483     /* All Errors Flag */
00484     if(__HAL_MDIOS_GET_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG) !=RESET)
00485     {
00486       /* Error Callback */
00487       HAL_MDIOS_ErrorCallback(hmdios);
00488
00489       /* Clear errors flag */
00490       __HAL_MDIOS_CLEAR_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG);
00491     }
00492   }
00493   /* check MDIOS WAKEUP exti flag */
00494   if(__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(MDIOS_WAKEUP_EXTI_LINE) != RESET)
00495   {
00496     /* Clear MDIOS WAKEUP Exti pending bit */
00497     __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(MDIOS_WAKEUP_EXTI_LINE);
00498                 /* MDIOS WAKEUP interrupt user callback */
00499     HAL_MDIOS_WakeUpCallback(hmdios);
00500   }
00501 }
00502
00503 /**
00504   * @brief  Write Complete Callback
00505   * @param  hmdios: mdios handle
00506   * @retval None
00507   */
00508  __weak void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios)
00509 {
00510   /* Prevent unused argument(s) compilation warning */
00511   UNUSED(hmdios);
00512
00513   /* NOTE : This function should not be modified, when the callback is needed,
00514             the HAL_MDIOS_WriteCpltCallback can be implemented in the user file
00515    */
00516 }
00517
00518 /**
00519   * @brief  Read Complete Callback
00520   * @param  hmdios: mdios handle
00521   * @retval None
00522   */
00523  __weak void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios)
00524 {
00525   /* Prevent unused argument(s) compilation warning */
00526   UNUSED(hmdios);
00527
00528   /* NOTE : This function should not be modified, when the callback is needed,
00529             the HAL_MDIOS_ReadCpltCallback can be implemented in the user file
00530    */
00531 }
00532
00533 /**
00534   * @brief Error Callback
00535   * @param hmdios: mdios handle
00536   * @retval None
00537   */
00538  __weak void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios)
00539 {
00540   /* Prevent unused argument(s) compilation warning */
00541   UNUSED(hmdios);
00542
00543   /* NOTE : This function should not be modified, when the callback is needed,
00544             the HAL_MDIOS_ErrorCallback can be implemented in the user file
00545    */
00546 }
00547
00548 /**
00549   * @brief  MDIOS WAKEUP interrupt callback
00550   * @param hmdios: mdios handle
00551   * @retval None
00552   */
00553 __weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios)
00554 {
00555   /* Prevent unused argument(s) compilation warning */
00556   UNUSED(hmdios);
00557
00558   /* NOTE : This function Should not be modified, when the callback is needed,
00559             the HAL_MDIOS_WakeUpCallback could be implemented in the user file
00560    */
00561 }
00562
00563 /**
00564   * @}
00565   */
00566
00567 /** @defgroup MDIOS_Exported_Functions_Group3 Peripheral Control functions
00568   *  @brief   MDIOS control functions
00569   *
00570 @verbatim
00571  ===============================================================================
00572                       ##### Peripheral Control functions #####
00573  ===============================================================================
00574     [..]
00575     This subsection provides a set of functions allowing to control the MDIOS.
00576      (+) HAL_MDIOS_GetState() API, helpful to check in run-time the state.
00577      (+) HAL_MDIOS_GetError() API, returns the errors occured during data transfer.
00578
00579 @endverbatim
00580   * @{
00581   */
00582
00583 /**
00584   * @brief  Gets MDIOS error flags
00585   * @param  hmdios: mdios handle
00586   * @retval bit map of occured errors
00587   */
00588 uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios)
00589 {
00590   /* return errors flags on status register */
00591   return hmdios->Instance->SR;
00592 }
00593
00594 /**
00595   * @brief  Return the MDIOS HAL state
00596   * @param  hmdios: mdios handle
00597   * @retval HAL state
00598   */
00599 HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios)
00600 {
00601   /* Return MDIOS state */
00602   return hmdios->State;
00603 }
00604
00605 /**
00606   * @}
00607   */
00608
00609 /**
00610   * @}
00611   */
00612
00613
00614 /**
00615   * @}
00616   */
00617 #endif /* MDIOS */
00618 /**
00619   * @}
00620   */
00621
00622 /**
00623   * @}
00624   */
00625 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_mdios.h Source File

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stm32h7xx_hal_mdios.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_mdios.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of MDIOS HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_MDIOS_H
00040 #define __STM32H7xx_HAL_MDIOS_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32h7xx_hal_def.h"
00049
00050 /** @addtogroup STM32H7xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup MDIOS
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup MDIOS_Exported_Types MDIOS Exported Types
00060   * @{
00061   */
00062
00063 /** @defgroup MDIOS_Exported_Types_Group1 MDIOS State structures definition
00064   * @{
00065   */
00066
00067 typedef enum
00068 {
00069   HAL_MDIOS_STATE_RESET             = 0x00U,    /*!< Peripheral not yet Initialized or disabled         */
00070   HAL_MDIOS_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use           */
00071   HAL_MDIOS_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                     */
00072   HAL_MDIOS_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                       */
00073 }HAL_MDIOS_StateTypeDef;
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @defgroup MDIOS_Exported_Types_Group2 MDIOS Init Structure definition
00080   * @{
00081   */
00082
00083 typedef struct
00084 {
00085   uint32_t PortAddress;           /*!< Specifies the MDIOS port address.
00086                                        This parameter can be a value from 0 to 31 */
00087   uint32_t PreambleCheck;         /*!< Specifies whether the preamble check is enabled or disabled.
00088                                        This parameter can be a value of @ref MDIOS_Preamble_Check */
00089 }MDIOS_InitTypeDef;
00090
00091 /**
00092   * @}
00093   */
00094
00095 /** @defgroup MDIOS_Exported_Types_Group4 MDIOS handle Structure definition
00096   * @{
00097   */
00098
00099 typedef struct
00100 {
00101   MDIOS_TypeDef                *Instance;     /*!< Register base address       */
00102
00103   MDIOS_InitTypeDef            Init;          /*!< MDIOS Init Structure        */
00104
00105   __IO HAL_MDIOS_StateTypeDef  State;         /*!< MDIOS communication state   */
00106
00107   HAL_LockTypeDef              Lock;          /*!< MDIOS Lock                  */
00108 }MDIOS_HandleTypeDef;
00109
00110 /**
00111   * @}
00112   */
00113
00114 /**
00115   * @}
00116   */
00117
00118 /* Exported constants --------------------------------------------------------*/
00119 /** @defgroup MDIOS_Exported_Constants MDIOS Exported Constants
00120   * @{
00121   */
00122
00123 /** @defgroup MDIOS_Preamble_Check  MDIOS Preamble Check
00124   * @{
00125   */
00126 #define MDIOS_PREAMBLE_CHECK_ENABLE      ((uint32_t)0x00000000U)
00127 #define MDIOS_PREAMBLE_CHECK_DISABLE     MDIOS_CR_DPC
00128 /**
00129   * @}
00130   */
00131
00132 /** @defgroup MDIOS_Input_Output_Registers_Definitions MDIOS Input Output Registers Definitions
00133   * @{
00134   */
00135 #define MDIOS_REG0                      ((uint32_t)0x00000000U)
00136 #define MDIOS_REG1                      ((uint32_t)0x00000001U)
00137 #define MDIOS_REG2                      ((uint32_t)0x00000002U)
00138 #define MDIOS_REG3                      ((uint32_t)0x00000003U)
00139 #define MDIOS_REG4                      ((uint32_t)0x00000004U)
00140 #define MDIOS_REG5                      ((uint32_t)0x00000005U)
00141 #define MDIOS_REG6                      ((uint32_t)0x00000006U)
00142 #define MDIOS_REG7                      ((uint32_t)0x00000007U)
00143 #define MDIOS_REG8                      ((uint32_t)0x00000008U)
00144 #define MDIOS_REG9                      ((uint32_t)0x00000009U)
00145 #define MDIOS_REG10                     ((uint32_t)0x0000000AU)
00146 #define MDIOS_REG11                     ((uint32_t)0x0000000BU)
00147 #define MDIOS_REG12                     ((uint32_t)0x0000000CU)
00148 #define MDIOS_REG13                     ((uint32_t)0x0000000DU)
00149 #define MDIOS_REG14                     ((uint32_t)0x0000000EU)
00150 #define MDIOS_REG15                     ((uint32_t)0x0000000FU)
00151 #define MDIOS_REG16                     ((uint32_t)0x00000010U)
00152 #define MDIOS_REG17                     ((uint32_t)0x00000011U)
00153 #define MDIOS_REG18                     ((uint32_t)0x00000012U)
00154 #define MDIOS_REG19                     ((uint32_t)0x00000013U)
00155 #define MDIOS_REG20                     ((uint32_t)0x00000014U)
00156 #define MDIOS_REG21                     ((uint32_t)0x00000015U)
00157 #define MDIOS_REG22                     ((uint32_t)0x00000016U)
00158 #define MDIOS_REG23                     ((uint32_t)0x00000017U)
00159 #define MDIOS_REG24                     ((uint32_t)0x00000018U)
00160 #define MDIOS_REG25                     ((uint32_t)0x00000019U)
00161 #define MDIOS_REG26                     ((uint32_t)0x0000001AU)
00162 #define MDIOS_REG27                     ((uint32_t)0x0000001BU)
00163 #define MDIOS_REG28                     ((uint32_t)0x0000001CU)
00164 #define MDIOS_REG29                     ((uint32_t)0x0000001DU)
00165 #define MDIOS_REG30                     ((uint32_t)0x0000001EU)
00166 #define MDIOS_REG31                     ((uint32_t)0x0000001FU)
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup MDIOS_Registers_Flags  MDIOS Registers Flags
00172   * @{
00173   */
00174 #define MDIOS_REG0_FLAG                 ((uint32_t)0x00000001U)
00175 #define MDIOS_REG1_FLAG                 ((uint32_t)0x00000002U)
00176 #define MDIOS_REG2_FLAG                 ((uint32_t)0x00000004U)
00177 #define MDIOS_REG3_FLAG                 ((uint32_t)0x00000008U)
00178 #define MDIOS_REG4_FLAG                 ((uint32_t)0x00000010U)
00179 #define MDIOS_REG5_FLAG                 ((uint32_t)0x00000020U)
00180 #define MDIOS_REG6_FLAG                 ((uint32_t)0x00000040U)
00181 #define MDIOS_REG7_FLAG                 ((uint32_t)0x00000080U)
00182 #define MDIOS_REG8_FLAG                 ((uint32_t)0x00000100U)
00183 #define MDIOS_REG9_FLAG                 ((uint32_t)0x00000200U)
00184 #define MDIOS_REG10_FLAG                ((uint32_t)0x00000400U)
00185 #define MDIOS_REG11_FLAG                ((uint32_t)0x00000800U)
00186 #define MDIOS_REG12_FLAG                ((uint32_t)0x00001000U)
00187 #define MDIOS_REG13_FLAG                ((uint32_t)0x00002000U)
00188 #define MDIOS_REG14_FLAG                ((uint32_t)0x00004000U)
00189 #define MDIOS_REG15_FLAG                ((uint32_t)0x00008000U)
00190 #define MDIOS_REG16_FLAG                ((uint32_t)0x00010000U)
00191 #define MDIOS_REG17_FLAG                ((uint32_t)0x00020000U)
00192 #define MDIOS_REG18_FLAG                ((uint32_t)0x00040000U)
00193 #define MDIOS_REG19_FLAG                ((uint32_t)0x00080000U)
00194 #define MDIOS_REG20_FLAG                ((uint32_t)0x00100000U)
00195 #define MDIOS_REG21_FLAG                ((uint32_t)0x00200000U)
00196 #define MDIOS_REG22_FLAG                ((uint32_t)0x00400000U)
00197 #define MDIOS_REG23_FLAG                ((uint32_t)0x00800000U)
00198 #define MDIOS_REG24_FLAG                ((uint32_t)0x01000000U)
00199 #define MDIOS_REG25_FLAG                ((uint32_t)0x02000000U)
00200 #define MDIOS_REG26_FLAG                ((uint32_t)0x04000000U)
00201 #define MDIOS_REG27_FLAG                ((uint32_t)0x08000000U)
00202 #define MDIOS_REG28_FLAG                ((uint32_t)0x10000000U)
00203 #define MDIOS_REG29_FLAG                ((uint32_t)0x20000000U)
00204 #define MDIOS_REG30_FLAG                ((uint32_t)0x40000000U)
00205 #define MDIOS_REG31_FLAG                ((uint32_t)0x80000000U)
00206 #define MDIOS_ALLREG_FLAG               ((uint32_t)0xFFFFFFFFU)
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup MDIOS_Interrupt_sources Interrupt Sources
00212   * @{
00213   */
00214 #define MDIOS_IT_WRITE                   MDIOS_CR_WRIE
00215 #define MDIOS_IT_READ                    MDIOS_CR_RDIE
00216 #define MDIOS_IT_ERROR                   MDIOS_CR_EIE
00217 /**
00218   * @}
00219   */
00220
00221 /** @defgroup MDIOS_Interrupt_Flags  MDIOS Interrupt Flags
00222   * @{
00223   */
00224 #define MDIOS_TURNAROUND_ERROR_FLAG       MDIOS_SR_TERF
00225 #define MDIOS_START_ERROR_FLAG            MDIOS_SR_SERF
00226 #define MDIOS_PREAMBLE_ERROR_FLAG         MDIOS_SR_PERF
00227 /**
00228   * @}
00229   */
00230
00231  /** @defgroup MDIOS_Wakeup_Line  MDIOS Wakeup Line
00232   * @{
00233   */
00234 #define MDIOS_WAKEUP_EXTI_LINE  ((uint32_t)0x00000400)  /* !<  42 - 32 = 10 */
00235 /**
00236   * @}
00237   */
00238
00239 /**
00240   * @}
00241   */
00242 /* Exported macros -----------------------------------------------------------*/
00243 /** @defgroup MDIOS_Exported_Macros MDIOS Exported Macros
00244   * @{
00245   */
00246
00247 /** @brief Reset MDIOS handle state
00248   * @param  __HANDLE__: MDIOS handle.
00249   * @retval None
00250   */
00251 #define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDIOS_STATE_RESET)
00252
00253 /**
00254   * @brief  Enable/Disable the MDIOS peripheral.
00255   * @param  __HANDLE__: specifies the MDIOS handle.
00256   * @retval None
00257   */
00258 #define __HAL_MDIOS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN)
00259 #define __HAL_MDIOS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~MDIOS_CR_EN)
00260
00261
00262 /**
00263   * @brief  Enable the MDIOS device interrupt.
00264   * @param  __HANDLE__: specifies the MDIOS handle.
00265   * @param  __INTERRUPT__ : specifies the MDIOS interrupt sources to be enabled.
00266   *         This parameter can be one or a combination of the following values:
00267   *            @arg MDIOS_IT_WRITE: Register write interrupt
00268   *            @arg MDIOS_IT_READ: Register read interrupt
00269   *            @arg MDIOS_IT_ERROR: Error interrupt
00270   * @retval None
00271   */
00272 #define __HAL_MDIOS_ENABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00273
00274 /**
00275   * @brief  Disable the MDIOS device interrupt.
00276   * @param  __HANDLE__: specifies the MDIOS handle.
00277   * @param  __INTERRUPT__ : specifies the MDIOS interrupt sources to be disabled.
00278   *         This parameter can be one or a combination of the following values:
00279   *            @arg MDIOS_IT_WRITE: Register write interrupt
00280   *            @arg MDIOS_IT_READ: Register read interrupt
00281   *            @arg MDIOS_IT_ERROR: Error interrupt
00282   * @retval None
00283   */
00284 #define __HAL_MDIOS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00285
00286 /** @brief Set MDIOS slave get write register flag
00287   * @param  __HANDLE__: specifies the MDIOS handle.
00288   * @param  __FLAG__: specifies the write register flag
00289   * @retval The state of write flag
00290   */
00291 #define __HAL_MDIOS_GET_WRITE_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->WRFR &  (__FLAG__))
00292
00293 /** @brief MDIOS slave get read register flag
00294   * @param  __HANDLE__: specifies the MDIOS handle.
00295   * @param  __FLAG__: specifies the read register flag
00296   * @retval The state of read flag
00297   */
00298 #define __HAL_MDIOS_GET_READ_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->RDFR &  (__FLAG__))
00299
00300 /** @brief MDIOS slave get interrupt
00301   * @param  __HANDLE__: specifies the MDIOS handle.
00302   * @param  __FLAG__ : specifies the Error flag.
00303   *         This parameter can be one or a combination of the following values:
00304   *            @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
00305   *            @arg MDIOS_START_ERROR_FLAG: Register read interrupt
00306   *            @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
00307   * @retval The state of the error flag
00308   */
00309 #define __HAL_MDIOS_GET_ERROR_FLAG(__HANDLE__, __FLAG__)       ((__HANDLE__)->Instance->SR &  (__FLAG__))
00310
00311 /** @brief  MDIOS slave clear interrupt
00312   * @param  __HANDLE__: specifies the MDIOS handle.
00313   * @param  __FLAG__ : specifies the Error flag.
00314   *         This parameter can be one or a combination of the following values:
00315   *            @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
00316   *            @arg MDIOS_START_ERROR_FLAG: Register read interrupt
00317   *            @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
00318   * @retval none
00319   */
00320 #define __HAL_MDIOS_CLEAR_ERROR_FLAG(__HANDLE__, __FLAG__)       ((__HANDLE__)->Instance->CLRFR) |= (__FLAG__)
00321
00322 /**
00323   * @brief  Checks whether the specified MDIOS interrupt is set or not.
00324   * @param  __HANDLE__: specifies the MDIOS handle.
00325   * @param  __INTERRUPT__ : specifies the MDIOS interrupt sources
00326   *            This parameter can be one or a combination of the following values:
00327   *            @arg MDIOS_IT_WRITE: Register write interrupt
00328   *            @arg MDIOS_IT_READ: Register read interrupt
00329   *            @arg MDIOS_IT_ERROR: Error interrupt
00330   * @retval The state of the interrupt source
00331   */
00332 #define __HAL_MDIOS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
00333
00334 /**
00335   * @brief Enable the MDIOS WAKEUP Exti Line.
00336   * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be enabled.
00337   * This parameter can be:
00338   *   @arg MDIOS_WAKEUP_EXTI_LINE
00339   * @retval None.
00340   */
00341 #define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__)   (EXTI_D1->IMR2 |= (__EXTI_LINE__))
00342
00343 /**
00344   * @brief checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not.
00345   * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.
00346   * This parameter can be:
00347   *   @arg MDIOS_WAKEUP_EXTI_LINE
00348   * @retval EXTI MDIOS WAKEUP Line Status.
00349   */
00350 #define __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__)  (EXTI_D1->PR2 & (__EXTI_LINE__))
00351
00352 /**
00353   * @brief Clear the MDIOS WAKEUP Exti flag.
00354   * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.
00355   * This parameter can be:
00356   *   @arg MDIOS_WAKEUP_EXTI_LINE
00357   * @retval None.
00358   */
00359 #define __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR2 = (__EXTI_LINE__))
00360
00361 /**
00362   * @brief  enable rising edge interrupt on selected EXTI line.
00363   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
00364   * This parameter can be:
00365   *  @arg ETH_WAKEUP_EXTI_LINE
00366   * @retval None
00367   */
00368 #define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR2 &= ~(__EXTI_LINE__)); \
00369                                                                    (EXTI->RTSR2 |= (__EXTI_LINE__))
00370
00371 /**
00372   * @brief  enable falling edge interrupt on selected EXTI line.
00373   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
00374   * This parameter can be:
00375   *  @arg ETH_WAKEUP_EXTI_LINE
00376   * @retval None
00377   */
00378 #define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR2 &= ~(__EXTI_LINE__));\
00379                                                                  (EXTI->FTSR2 |= (__EXTI_LINE__))
00380
00381 /**
00382   * @brief  enable falling edge interrupt on selected EXTI line.
00383   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
00384   * This parameter can be:
00385   *  @arg ETH_WAKEUP_EXTI_LINE
00386   * @retval None
00387   */
00388 #define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR2 |= (__EXTI_LINE__));\
00389                                                                           (EXTI->FTSR2 |= (__EXTI_LINE__))
00390
00391 /**
00392   * @brief  Generates a Software interrupt on selected EXTI line.
00393   * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP EXTI sources to be disabled.
00394   * This parameter can be:
00395   *  @arg MDIOS_WAKEUP_EXTI_LINE
00396   * @retval None
00397   */
00398 #define __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER2 |= (__EXTI_LINE__))
00399
00400 /**
00401   * @}
00402   */
00403
00404 /* Exported functions --------------------------------------------------------*/
00405 /** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions
00406   * @{
00407   */
00408
00409 /** @addtogroup MDIOS_Exported_Functions_Group1
00410   * @{
00411   */
00412 HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios);
00413 HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios);
00414 void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios);
00415 void  HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios);
00416 /**
00417   * @}
00418   */
00419
00420 /** @addtogroup MDIOS_Exported_Functions_Group2
00421   * @{
00422   */
00423 HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios,  uint32_t RegNum, uint16_t Data);
00424 HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios,  uint32_t RegNum, uint16_t *pData);
00425
00426 uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios);
00427 uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios);
00428 HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum);
00429 HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum);
00430
00431 HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios);
00432 void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios);
00433 void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios);
00434 void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios);
00435 void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios);
00436 void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios);
00437 /**
00438   * @}
00439   */
00440
00441 /** @addtogroup MDIOS_Exported_Functions_Group3
00442   * @{
00443   */
00444 uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios);
00445 HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios);
00446 /**
00447   * @}
00448   */
00449
00450 /**
00451   * @}
00452   */
00453
00454 /* Private types -------------------------------------------------------------*/
00455 /** @defgroup MDIOS_Private_Types MDIOS Private Types
00456   * @{
00457   */
00458
00459 /**
00460   * @}
00461   */
00462
00463 /* Private variables ---------------------------------------------------------*/
00464 /** @defgroup MDIOS_Private_Variables MDIOS Private Variables
00465   * @{
00466   */
00467
00468 /**
00469   * @}
00470   */
00471
00472 /* Private constants ---------------------------------------------------------*/
00473 /** @defgroup MDIOS_Private_Constants MDIOS Private Constants
00474   * @{
00475   */
00476
00477 /**
00478   * @}
00479   */
00480
00481 /* Private macros ------------------------------------------------------------*/
00482 /** @defgroup MDIOS_Private_Macros MDIOS Private Macros
00483   * @{
00484   */
00485
00486 #define IS_MDIOS_PORTADDRESS(__ADDR__) ((__ADDR__) < 32)
00487
00488 #define IS_MDIOS_REGISTER(__REGISTER__) ((__REGISTER__) < 32)
00489
00490 #define IS_MDIOS_PREAMBLECHECK(__PREAMBLECHECK__) (((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_ENABLE) || \
00491                                                    ((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_DISABLE))
00492
00493  /**
00494   * @}
00495   */
00496
00497 /* Private functions ---------------------------------------------------------*/
00498 /** @defgroup MDIOS_Private_Functions MDIOS Private Functions
00499   * @{
00500   */
00501
00502 /**
00503   * @}
00504   */
00505
00506
00507 /**
00508   * @}
00509   */
00510
00511 /**
00512   * @}
00513   */
00514
00515
00516 #ifdef __cplusplus
00517 }
00518 #endif
00519
00520 #endif /* __STM32H7xx_HAL_MDIOS_H */
00521
00522 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_mdma.c Source File

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stm32h7xx_hal_mdma.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_mdma.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief  This file provides firmware functions to manage the following
00008   *         functionalities of the Master Direct Memory Access (MDMA) peripheral:
00009   *           + Initialization/de-initialization functions
00010   *           + I/O operation functions
00011   *           + Peripheral State and errors functions
00012   @verbatim
00013   ==============================================================================
00014                         ##### How to use this driver #####
00015   ==============================================================================
00016   [..]
00017    (#) Enable and configure the peripheral to be connected to the MDMA Channel
00018        (except for internal SRAM/FLASH memories: no initialization is
00019        necessary) please refer to Reference manual for connection between peripherals
00020        and MDMA requests.
00021
00022    (#)
00023        For a given Channel use HAL_MDMA_Init function to program the required configuration through the following parameters:
00024        transfer request , channel priority, data endianness, Source increment, destination increment ,
00025        source data size, destination data size, data alignment, source Burst, destination Burst ,
00026        buffer Transfer Length, Transfer Trigger Mode (buffer transfer, block transfer, repeated block transfer
00027        or full transfer) source and destination block address offset, mask address and data.
00028
00029        If using the MDMA in linked list mode then use function HAL_MDMA_LinkedList_CreateNode to fill a transfer node.
00030        Note that parameters given to the function HAL_MDMA_Init corresponds always to the node zero.
00031        Use function HAL_MDMA_LinkedList_AddNode to connect the created node to the linked list at a given position.
00032        User can make a linked list circular using function HAL_MDMA_LinkedList_EnableCircularMode , this function will automatically connect the
00033        last node of the list to the first one in order to make the list circular.
00034        In this case the linked list will loop on node 1 : first node connected after the initial transfer defined by the HAL_MDMA_Init
00035
00036       -@-   The initial transfer itself (node 0 corresponding to the Init).
00037             User can disable the circular mode using function HAL_MDMA_LinkedList_DisableCircularMode, this function will then remove
00038             the connection between last node and first one.
00039
00040        Function HAL_MDMA_LinkedList_RemoveNode can be used to remove (disconnect) a node from the transfer linked list.
00041        When a linked list is circular (last node connected to first one), if removing node1  (node where the linked list loops),
00042        the linked list remains circular and node 2 becomes the first one.
00043        Note that if the linked list is made circular the transfer will loop infinitely (or until aborted by the user).
00044
00045     [..]
00046        (+) User can select the transfer trigger mode (parameter TransferTriggerMode) to define the amount of data to be
00047            transfer upon a request :
00048              (++) MDMA_BUFFER_TRANSFER : each request triggers a transfer of BufferTransferLength data
00049                with BufferTransferLength defined within the HAL_MDMA_Init.
00050              (++) MDMA_BLOCK_TRANSFER : each request triggers a transfer of a block
00051                with block size defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT
00052                or within the current linked list node parameters.
00053              (++) MDMA_REPEAT_BLOCK_TRANSFER : each request triggers a transfer of a number of blocks
00054                with block size and number of blocks defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT
00055                or within the current linked list node parameters.
00056              (++) MDMA_FULL_TRANSFER : each request triggers a full transfer
00057               all blocks and all nodes(if a linked list has been created using HAL_MDMA_LinkedList_CreateNode \ HAL_MDMA_LinkedList_AddNode).
00058
00059      *** Polling mode IO operation ***
00060      =================================
00061     [..]
00062           (+) Use HAL_MDMA_Start() to start MDMA transfer after the configuration of Source
00063               address and destination address and the Length of data to be transferred.
00064           (+) Use HAL_MDMA_PollForTransfer() to poll for the end of current transfer or a transfer level
00065              In this case a fixed Timeout can be configured by User depending from his application.
00066           (+) Use HAL_MDMA_Abort() function to abort the current transfer : blocking method this API returns
00067               when the abort ends or timeout (should not be called from an interrupt service routine).
00068
00069      *** Interrupt mode IO operation ***
00070      ===================================
00071     [..]
00072           (+) Configure the MDMA interrupt priority using HAL_NVIC_SetPriority()
00073           (+) Enable the MDMA IRQ handler using HAL_NVIC_EnableIRQ()
00074           (+) Use HAL_MDMA_Start_IT() to start MDMA transfer after the configuration of
00075               Source address and destination address and the Length of data to be transferred. In this
00076               case the MDMA interrupt is configured.
00077           (+) Use HAL_MDMA_IRQHandler() called under MDMA_IRQHandler() Interrupt subroutine
00078           (+) At the end of data transfer HAL_MDMA_IRQHandler() function is executed and user can
00079               add his own function by customization of function pointer XferCpltCallback and
00080               XferErrorCallback (i.e a member of MDMA handle structure).
00081
00082           (+) Use HAL_MDMA_Abort_IT() function to abort the current transfer : non-blocking method. This API returns immediately
00083               then the callback XferAbortCallback (if specified  by the user) is asserted once the MDMA channel hase effectively aborted.
00084               (could be called from an interrupt service routine).
00085
00086           (+) Use functions HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback respectevely to register unregister user callbacks
00087               from the following list :
00088               (++) XferCpltCallback            : transfer complete callback.
00089               (++) XferBufferCpltCallback      : buffer transfer complete callback.
00090               (++) XferBlockCpltCallback       : block transfer complete callback.
00091               (++) XferRepeatBlockCpltCallback : repeated block transfer complete callback.
00092               (++) XferErrorCallback           : transfer error callback.
00093               (++) XferAbortCallback           : transfer abort complete callback.
00094
00095     [..]
00096          (+)  If the transfer Request corresponds to SW request (MDMA_REQUEST_SW) User can use function HAL_MDMA_GenerateSWRequest to
00097               trigger requests manually. Function HAL_MDMA_GenerateSWRequest must be used with the following precautions:
00098               (++) This function returns an error if used while the Transfer hase ends or not started.
00099               (++) If used while the current request hase not been served yet (current request transfer on going)
00100                 this function returns an error and the new request is ignored.
00101
00102               Generally this function should be used in conjunctions with the MDMA callbacks:
00103               (++) example 1:
00104                  (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BUFFER_TRANSFER
00105                  (+++) Register a callback for buffer transfer complete (using callback ID set to HAL_MDMA_XFER_BUFFERCPLT_CB_ID)
00106                  (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first BufferTransferLength data.
00107                  (+++) When the buffer transfer complete callback is asserted first buffer hase been transferred and user can ask for a new buffer transfer
00108                    request using HAL_MDMA_GenerateSWRequest.
00109
00110               (++) example 2:
00111                  (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BLOCK_TRANSFER
00112                  (+++) Register a callback for block transfer complete (using callback ID HAL_MDMA_XFER_BLOCKCPLT_CB_ID)
00113                  (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first block of data.
00114                  (+++) When the block transfer complete callback is asserted the fisrt block hase been transferred and user can ask
00115                    for a new block transfer request using HAL_MDMA_GenerateSWRequest.
00116
00117     [..]  Use HAL_MDMA_GetState() function to return the MDMA state and HAL_MDMA_GetError() in case of error detection.
00118
00119      *** MDMA HAL driver macros list ***
00120      =============================================
00121      [..]
00122        Below the list of most used macros in MDMA HAL driver.
00123
00124       (+) __HAL_MDMA_ENABLE: Enable the specified MDMA Stream.
00125       (+) __HAL_MDMA_DISABLE: Disable the specified MDMA Stream.
00126       (+) __HAL_MDMA_GET_FLAG: Get the MDMA Stream pending flags.
00127       (+) __HAL_MDMA_CLEAR_FLAG: Clear the MDMA Stream pending flags.
00128       (+) __HAL_MDMA_ENABLE_IT: Enable the specified MDMA Stream interrupts.
00129       (+) __HAL_MDMA_DISABLE_IT: Disable the specified MDMA Stream interrupts.
00130       (+) __HAL_MDMA_GET_IT_SOURCE: Check whether the specified MDMA Stream interrupt has occurred or not.
00131
00132      [..]
00133       (@) You can refer to the header file of the MDMA HAL driver for more useful macros.
00134
00135     [..]
00136
00137     @endverbatim
00138   ******************************************************************************
00139   * @attention
00140   *
00141   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00142   *
00143   * Redistribution and use in source and binary forms, with or without modification,
00144   * are permitted provided that the following conditions are met:
00145   *   1. Redistributions of source code must retain the above copyright notice,
00146   *      this list of conditions and the following disclaimer.
00147   *   2. Redistributions in binary form must reproduce the above copyright notice,
00148   *      this list of conditions and the following disclaimer in the documentation
00149   *      and/or other materials provided with the distribution.
00150   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00151   *      may be used to endorse or promote products derived from this software
00152   *      without specific prior written permission.
00153   *
00154   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00155   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00156   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00157   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00158   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00159   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00160   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00161   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00162   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00163   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00164   *
00165   ******************************************************************************
00166   */
00167
00168 /* Includes ------------------------------------------------------------------*/
00169 #include "stm32h7xx_hal.h"
00170
00171 /** @addtogroup STM32H7xx_HAL_Driver
00172   * @{
00173   */
00174
00175 /** @defgroup MDMA  MDMA
00176   * @brief MDMA HAL module driver
00177   * @{
00178   */
00179
00180 #ifdef HAL_MDMA_MODULE_ENABLED
00181
00182 /* Private typedef -----------------------------------------------------------*/
00183 /* Private constants ---------------------------------------------------------*/
00184 /** @addtogroup MDMA_Private_Constants
00185  * @{
00186  */
00187 #define HAL_TIMEOUT_MDMA_ABORT    ((uint32_t)5U)    /* 5 ms */
00188 #define HAL_MDMA_CHANNEL_SIZE     ((uint32_t)0x40U) /* an MDMA instance channel size is 64 byte  */
00189 /**
00190   * @}
00191   */
00192 /* Private macro -------------------------------------------------------------*/
00193 /* Private variables ---------------------------------------------------------*/
00194 /* Private function prototypes -----------------------------------------------*/
00195 /** @addtogroup MDMA_Private_Functions_Prototypes
00196   * @{
00197   */
00198 static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
00199 static void MDMA_Init(MDMA_HandleTypeDef *hmdma);
00200
00201 /**
00202   * @}
00203   */
00204
00205 /** @addtogroup MDMA_Exported_Functions MDMA Exported Functions
00206   * @{
00207   */
00208
00209 /** @addtogroup MDMA_Exported_Functions_Group1
00210   *
00211 @verbatim
00212  ===============================================================================
00213              ##### Initialization and de-initialization functions  #####
00214  ===============================================================================
00215     [..]
00216     This section provides functions allowing to :
00217       Initialize and de-initialize the MDMA channel.
00218       Register and Unregister MDMA callbacks
00219     [..]
00220     The HAL_MDMA_Init() function follows the MDMA channel configuration procedures as described in
00221     reference manual.
00222     The HAL_MDMA_DeInit function allows to deinitialize the MDMA channel.
00223     HAL_MDMA_RegisterCallback and  HAL_MDMA_UnRegisterCallback functions allows
00224     respectevely to register/unregister an MDMA callback function.
00225
00226 @endverbatim
00227   * @{
00228   */
00229
00230 /**
00231   * @brief  Initializes the MDMA according to the specified
00232   *         parameters in the MDMA_InitTypeDef and create the associated handle.
00233   * @param  hmdma: Pointer to a MDMA_HandleTypeDef structure that contains
00234   *               the configuration information for the specified MDMA Stream.
00235   * @retval HAL status
00236   */
00237 HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma)
00238 {
00239   uint32_t tickstart = HAL_GetTick();
00240
00241   /* Check the MDMA peripheral handle */
00242   if(hmdma == NULL)
00243   {
00244     return HAL_ERROR;
00245   }
00246
00247   /* Check the parameters */
00248   assert_param(IS_MDMA_STREAM_ALL_INSTANCE(hmdma->Instance));
00249   assert_param(IS_MDMA_PRIORITY(hmdma->Init.Priority));
00250   assert_param(IS_MDMA_ENDIANNESS_MODE(hmdma->Init.Endianness));
00251   assert_param(IS_MDMA_REQUEST(hmdma->Init.Request));
00252   assert_param(IS_MDMA_SOURCE_INC(hmdma->Init.SourceInc));
00253   assert_param(IS_MDMA_DESTINATION_INC(hmdma->Init.DestinationInc));
00254   assert_param(IS_MDMA_SOURCE_DATASIZE(hmdma->Init.SourceDataSize));
00255   assert_param(IS_MDMA_DESTINATION_DATASIZE(hmdma->Init.DestDataSize));
00256   assert_param(IS_MDMA_DATA_ALIGNMENT(hmdma->Init.DataAlignment));
00257   assert_param(IS_MDMA_SOURCE_BURST(hmdma->Init.SourceBurst));
00258   assert_param(IS_MDMA_DESTINATION_BURST(hmdma->Init.DestBurst));
00259   assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(hmdma->Init.BufferTransferLength));
00260   assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(hmdma->Init.TransferTriggerMode));
00261   assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.SourceBlockAddressOffset));
00262   assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.DestBlockAddressOffset));
00263
00264
00265   /* Allocate lock resource */
00266   __HAL_UNLOCK(hmdma);
00267
00268   /* Change MDMA peripheral state */
00269   hmdma->State = HAL_MDMA_STATE_BUSY;
00270
00271   /* Disable the MDMA channel */
00272   __HAL_MDMA_DISABLE(hmdma);
00273
00274   /* Check if the MDMA channel is effectively disabled */
00275   while((hmdma->Instance->CCR & MDMA_CCR_EN) != RESET)
00276   {
00277     /* Check for the Timeout */
00278     if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT)
00279     {
00280       /* Update error code */
00281       hmdma->ErrorCode = HAL_MDMA_ERROR_TIMEOUT;
00282
00283       /* Change the MDMA state */
00284       hmdma->State = HAL_MDMA_STATE_ERROR;
00285
00286       return HAL_ERROR;
00287     }
00288   }
00289
00290   /* Init MDMA channel registers */
00291   MDMA_Init(hmdma);
00292
00293   /* Reset the  MDMA first/last linkedlist node addresses and node counter */
00294   hmdma->FirstLinkedListNodeAddress  = 0;
00295   hmdma->LastLinkedListNodeAddress   = 0;
00296   hmdma->LinkedListNodeCounter  = 0;
00297
00298   /* Initialise the error code */
00299   hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
00300
00301   /* Initialize the MDMA state */
00302   hmdma->State = HAL_MDMA_STATE_READY;
00303
00304   return HAL_OK;
00305 }
00306
00307 /**
00308   * @brief  DeInitializes the MDMA peripheral
00309   * @param  hmdma: pointer to a MDMA_HandleTypeDef structure that contains
00310   *               the configuration information for the specified MDMA Stream.
00311   * @retval HAL status
00312   */
00313 HAL_StatusTypeDef HAL_MDMA_DeInit(MDMA_HandleTypeDef *hmdma)
00314 {
00315
00316   /* Check the MDMA peripheral handle */
00317   if(hmdma == NULL)
00318   {
00319     return HAL_ERROR;
00320   }
00321
00322   /* Check the MDMA peripheral state */
00323   if(hmdma->State == HAL_MDMA_STATE_BUSY)
00324   {
00325     hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY;
00326     return HAL_ERROR;
00327   }
00328
00329   /* Disable the selected MDMA Channelx */
00330   __HAL_MDMA_DISABLE(hmdma);
00331
00332   /* Reset MDMA Channel control register */
00333   hmdma->Instance->CCR  = 0;
00334   hmdma->Instance->CTCR = 0;
00335   hmdma->Instance->CBNDTR = 0;
00336   hmdma->Instance->CSAR = 0;
00337   hmdma->Instance->CDAR = 0;
00338   hmdma->Instance->CBRUR = 0;
00339   hmdma->Instance->CLAR = 0;
00340   hmdma->Instance->CTBR = 0;
00341   hmdma->Instance->CMAR = 0;
00342   hmdma->Instance->CMDR = 0;
00343
00344   /* Clear all flags */
00345   __HAL_MDMA_CLEAR_FLAG(hmdma,(MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC));
00346
00347   /* Reset the  MDMA first/last linkedlist node addresses and node counter */
00348   hmdma->FirstLinkedListNodeAddress  = 0;
00349   hmdma->LastLinkedListNodeAddress   = 0;
00350   hmdma->LinkedListNodeCounter  = 0;
00351
00352   /* Initialise the error code */
00353   hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
00354
00355   /* Initialize the MDMA state */
00356   hmdma->State = HAL_MDMA_STATE_RESET;
00357
00358   /* Release Lock */
00359   __HAL_UNLOCK(hmdma);
00360
00361   return HAL_OK;
00362 }
00363
00364 /**
00365   * @brief  Config the Post request Mask address and Mask data
00366   * @param  hmdma      : pointer to a MDMA_HandleTypeDef structure that contains
00367   *                               the configuration information for the specified MDMA Channel.
00368   * @param  MaskAddress: specifies the address to be updated (written) with MaskData after a request is served.
00369   * @param  MaskData:    specifies the value to be written to MaskAddress after a request is served.
00370   *                      MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served.
00371   * @retval HAL status
00372   */
00373 HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData)
00374 {
00375   HAL_StatusTypeDef  status = HAL_OK;
00376
00377   /* Check the MDMA peripheral handle */
00378   if(hmdma == NULL)
00379   {
00380     return HAL_ERROR;
00381   }
00382
00383   /* Process locked */
00384   __HAL_LOCK(hmdma);
00385
00386   if(HAL_MDMA_STATE_READY == hmdma->State)
00387   {
00388     /* if HW request set Post Request MaskAddress and MaskData,  */
00389     if((hmdma->Instance->CTCR & MDMA_CTCR_SWRM) == 0)
00390     {
00391       /* Set the HW request clear Mask and Data */
00392       hmdma->Instance->CMAR = MaskAddress;
00393       hmdma->Instance->CMDR = MaskData;
00394
00395       /*
00396       -If the request is done by SW : BWM could be set to 1 or 0.
00397       -If the request is done by a peripheral :
00398          If mask address not set (0) => BWM must be set to 0
00399          If mask address set (different than 0) => BWM could be set to 1 or 0
00400       */
00401       if(MaskAddress == 0)
00402       {
00403         hmdma->Instance->CTCR &=  ~MDMA_CTCR_BWM;
00404       }
00405       else
00406       {
00407         hmdma->Instance->CTCR |=  MDMA_CTCR_BWM;
00408       }
00409     }
00410     else
00411     {
00412       /* Return error status */
00413       status =  HAL_ERROR;
00414     }
00415   }
00416   else
00417   {
00418     /* Return error status */
00419     status =  HAL_ERROR;
00420   }
00421   /* Release Lock */
00422   __HAL_UNLOCK(hmdma);
00423
00424   return status;
00425 }
00426
00427 /**
00428   * @brief  Register callbacks
00429   * @param  hmdma:                pointer to a MDMA_HandleTypeDef structure that contains
00430   *                               the configuration information for the specified MDMA Channel.
00431   * @param  CallbackID:           User Callback identifier
00432   * @param  pCallback:            pointer to callbacsk function.
00433   * @retval HAL status
00434   */
00435 HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma))
00436 {
00437   HAL_StatusTypeDef status = HAL_OK;
00438
00439   /* Check the MDMA peripheral handle */
00440   if(hmdma == NULL)
00441   {
00442     return HAL_ERROR;
00443   }
00444
00445   /* Process locked */
00446   __HAL_LOCK(hmdma);
00447
00448   if(HAL_MDMA_STATE_READY == hmdma->State)
00449   {
00450     switch (CallbackID)
00451     {
00452     case  HAL_MDMA_XFER_CPLT_CB_ID:
00453       hmdma->XferCpltCallback = pCallback;
00454       break;
00455
00456     case  HAL_MDMA_XFER_BUFFERCPLT_CB_ID:
00457       hmdma->XferBufferCpltCallback = pCallback;
00458       break;
00459
00460     case  HAL_MDMA_XFER_BLOCKCPLT_CB_ID:
00461       hmdma->XferBlockCpltCallback = pCallback;
00462       break;
00463
00464     case  HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID:
00465       hmdma->XferRepeatBlockCpltCallback = pCallback;
00466       break;
00467
00468     case  HAL_MDMA_XFER_ERROR_CB_ID:
00469       hmdma->XferErrorCallback = pCallback;
00470       break;
00471
00472     case  HAL_MDMA_XFER_ABORT_CB_ID:
00473       hmdma->XferAbortCallback = pCallback;
00474       break;
00475
00476     default:
00477       break;
00478     }
00479   }
00480   else
00481   {
00482     /* Return error status */
00483     status =  HAL_ERROR;
00484   }
00485
00486   /* Release Lock */
00487   __HAL_UNLOCK(hmdma);
00488
00489   return status;
00490 }
00491
00492 /**
00493   * @brief  UnRegister callbacks
00494   * @param  hmdma:                 pointer to a MDMA_HandleTypeDef structure that contains
00495   *                               the configuration information for the specified MDMA Channel.
00496   * @param  CallbackID:           User Callback identifier
00497   *                               a HAL_MDMA_CallbackIDTypeDef ENUM as parameter.
00498   * @retval HAL status
00499   */
00500 HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID)
00501 {
00502   HAL_StatusTypeDef status = HAL_OK;
00503
00504   /* Check the MDMA peripheral handle */
00505   if(hmdma == NULL)
00506   {
00507     return HAL_ERROR;
00508   }
00509
00510   /* Process locked */
00511   __HAL_LOCK(hmdma);
00512
00513   if(HAL_MDMA_STATE_READY == hmdma->State)
00514   {
00515     switch (CallbackID)
00516     {
00517     case  HAL_MDMA_XFER_CPLT_CB_ID:
00518       hmdma->XferCpltCallback = NULL;
00519       break;
00520
00521     case  HAL_MDMA_XFER_BUFFERCPLT_CB_ID:
00522       hmdma->XferBufferCpltCallback = NULL;
00523       break;
00524
00525     case  HAL_MDMA_XFER_BLOCKCPLT_CB_ID:
00526       hmdma->XferBlockCpltCallback = NULL;
00527       break;
00528
00529     case  HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID:
00530       hmdma->XferRepeatBlockCpltCallback = NULL;
00531       break;
00532
00533     case  HAL_MDMA_XFER_ERROR_CB_ID:
00534       hmdma->XferErrorCallback = NULL;
00535       break;
00536
00537     case  HAL_MDMA_XFER_ABORT_CB_ID:
00538       hmdma->XferAbortCallback = NULL;
00539       break;
00540
00541     case   HAL_MDMA_XFER_ALL_CB_ID:
00542       hmdma->XferCpltCallback = NULL;
00543       hmdma->XferBufferCpltCallback = NULL;
00544       hmdma->XferBlockCpltCallback = NULL;
00545       hmdma->XferRepeatBlockCpltCallback = NULL;
00546       hmdma->XferErrorCallback = NULL;
00547       hmdma->XferAbortCallback = NULL;
00548       break;
00549
00550     default:
00551       status = HAL_ERROR;
00552       break;
00553     }
00554   }
00555   else
00556   {
00557     status = HAL_ERROR;
00558   }
00559
00560   /* Release Lock */
00561   __HAL_UNLOCK(hmdma);
00562
00563   return status;
00564 }
00565
00566 /**
00567   * @}
00568   */
00569
00570 /** @addtogroup MDMA_Exported_Functions_Group2
00571  *
00572 @verbatim
00573  ===============================================================================
00574                       #####  Linked list operation functions  #####
00575  ===============================================================================
00576     [..]  This section provides functions allowing to:
00577       (+) Create a linked list node
00578       (+) Add a node to the MDMA linked list
00579       (+) Remove a node from the MDMA linked list
00580       (+) Enable/Disable linked list circular mode
00581 @endverbatim
00582   * @{
00583   */
00584
00585 /**
00586   * @brief  Initializes an MDMA Link Node according to the specified
00587   *         parameters in the pMDMA_LinkedListNodeConfig .
00588   * @param  pNode: Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
00589   *         registers configurations.
00590   * @param  pNodeConfig: Pointer to a MDMA_LinkNodeConfTypeDef structure that contains
00591   *               the configuration information for the specified MDMA Linked List Node.
00592   * @retval HAL status
00593   */
00594 HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig)
00595 {
00596   uint32_t addressMask = 0;
00597   uint32_t blockoffset = 0;
00598
00599   /* Check the MDMA peripheral state */
00600   if((pNode == NULL) || (pNodeConfig == NULL))
00601   {
00602     return HAL_ERROR;
00603   }
00604
00605   /* Check the parameters */
00606   assert_param(IS_MDMA_PRIORITY(pNodeConfig->Init.Priority));
00607   assert_param(IS_MDMA_ENDIANNESS_MODE(pNodeConfig->Init.Endianness));
00608   assert_param(IS_MDMA_REQUEST(pNodeConfig->Init.Request));
00609   assert_param(IS_MDMA_SOURCE_INC(pNodeConfig->Init.SourceInc));
00610   assert_param(IS_MDMA_DESTINATION_INC(pNodeConfig->Init.DestinationInc));
00611   assert_param(IS_MDMA_SOURCE_DATASIZE(pNodeConfig->Init.SourceDataSize));
00612   assert_param(IS_MDMA_DESTINATION_DATASIZE(pNodeConfig->Init.DestDataSize));
00613   assert_param(IS_MDMA_DATA_ALIGNMENT(pNodeConfig->Init.DataAlignment));
00614   assert_param(IS_MDMA_SOURCE_BURST(pNodeConfig->Init.SourceBurst));
00615   assert_param(IS_MDMA_DESTINATION_BURST(pNodeConfig->Init.DestBurst));
00616   assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(pNodeConfig->Init.BufferTransferLength));
00617   assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(pNodeConfig->Init.TransferTriggerMode));
00618   assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.SourceBlockAddressOffset));
00619   assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.DestBlockAddressOffset));
00620
00621   assert_param(IS_MDMA_TRANSFER_LENGTH(pNodeConfig->BlockDataLength));
00622   assert_param(IS_MDMA_BLOCK_COUNT(pNodeConfig->BlockCount));
00623
00624
00625   /*configure next Link node Address Register to zero */
00626   pNode->CLAR =  0;
00627
00628   /*Configure the Link Node registers*/
00629   pNode->CTBR   = 0;
00630   pNode->CMAR   = 0;
00631   pNode->CMDR   = 0;
00632   pNode->Reserved = 0;
00633
00634   /* write new CTCR Register value */
00635   pNode->CTCR =  pNodeConfig->Init.SourceInc | pNodeConfig->Init.DestinationInc  | \
00636     pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize  | \
00637       pNodeConfig->Init.DataAlignment| pNodeConfig->Init.SourceBurst   | \
00638         pNodeConfig->Init.DestBurst  | \
00639           ((pNodeConfig->Init.BufferTransferLength - 1) << POSITION_VAL(MDMA_CTCR_TLEN)) | \
00640             pNodeConfig->Init.TransferTriggerMode;
00641
00642   /* If SW request set the CTCR register to SW Request Mode*/
00643   if(pNodeConfig->Init.Request == MDMA_REQUEST_SW)
00644   {
00645     pNode->CTCR |= MDMA_CTCR_SWRM;
00646   }
00647
00648   /*
00649   -If the request is done by SW : BWM could be set to 1 or 0.
00650   -If the request is done by a peripheral :
00651      If mask address not set (0) => BWM must be set to 0
00652      If mask address set (different than 0) => BWM could be set to 1 or 0
00653   */
00654   if((pNodeConfig->Init.Request == MDMA_REQUEST_SW) || (pNodeConfig->PostRequestMaskAddress != 0))
00655   {
00656     pNode->CTCR |=  MDMA_CTCR_BWM;
00657   }
00658
00659   /* Set the new CBNDTR Register value */
00660   pNode->CBNDTR = ((pNodeConfig->BlockCount - 1) << POSITION_VAL(MDMA_CBNDTR_BRC)) & MDMA_CBNDTR_BRC;
00661
00662   /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */
00663   if(pNodeConfig->Init.SourceBlockAddressOffset < 0)
00664   {
00665     pNode->CBNDTR |= MDMA_CBNDTR_BRSUM;
00666     /*write new CBRUR Register value : source repeat block offset */
00667     blockoffset = (-1 * pNodeConfig->Init.SourceBlockAddressOffset);
00668     pNode->CBRUR = blockoffset & 0x0000FFFFU;
00669   }
00670   else
00671   {
00672     /*write new CBRUR Register value : source repeat block offset */
00673     pNode->CBRUR = (((uint32_t) pNodeConfig->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
00674   }
00675
00676   /* if block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */
00677   if(pNodeConfig->Init.DestBlockAddressOffset < 0)
00678   {
00679     pNode->CBNDTR |= MDMA_CBNDTR_BRDUM;
00680     /*write new CBRUR Register value : destination repeat block offset */
00681     blockoffset = (-1 * pNodeConfig->Init.DestBlockAddressOffset);
00682     pNode->CBRUR |= ((blockoffset & 0x0000FFFFU) << POSITION_VAL(MDMA_CBRUR_DUV));
00683   }
00684   else
00685   {
00686     /*write new CBRUR Register value : destination repeat block offset */
00687     pNode->CBRUR |= (((uint32_t)pNodeConfig->Init.DestBlockAddressOffset) & 0x0000FFFFU) << POSITION_VAL(MDMA_CBRUR_DUV);
00688   }
00689
00690   /* Configure MDMA Link Node data length */
00691   pNode->CBNDTR |=  pNodeConfig->BlockDataLength;
00692
00693   /* Configure MDMA Link Node destination address */
00694   pNode->CDAR = pNodeConfig->DstAddress;
00695
00696   /* Configure MDMA Link Node Source address */
00697   pNode->CSAR = pNodeConfig->SrcAddress;
00698
00699   /* if HW request set the HW request and the requet CleraMask and ClearData MaskData,  */
00700   if(pNodeConfig->Init.Request != MDMA_REQUEST_SW)
00701   {
00702     /* Set the HW request in CTBR register  */
00703     pNode->CTBR = pNodeConfig->Init.Request & MDMA_CTBR_TSEL;
00704     /* Set the HW request clear Mask and Data */
00705     pNode->CMAR = pNodeConfig->PostRequestMaskAddress;
00706     pNode->CMDR = pNodeConfig->PostRequestMaskData;
00707   }
00708
00709   addressMask = pNodeConfig->SrcAddress & 0xFF000000U;
00710   if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
00711   {
00712     /*The AHBSbus is used as source (read operation) on channel x */
00713     pNode->CTBR |= MDMA_CTBR_SBUS;
00714   }
00715
00716   addressMask = pNodeConfig->DstAddress & 0xFF000000U;
00717   if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
00718   {
00719     /*The AHB bus is used as destination (write operation) on channel x */
00720     pNode->CTBR |= MDMA_CTBR_DBUS;
00721   }
00722
00723   return HAL_OK;
00724 }
00725
00726 /**
00727   * @brief  Connect a node to the linked list.
00728   * @param  hmdma    : Pointer to a MDMA_HandleTypeDef structure that contains
00729   *                    the configuration information for the specified MDMA Channel.
00730   * @param  pNewNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
00731   *                    to be add to the list.
00732   * @param pPrevNode : Pointer to the new node position in the linked list or zero to insert the new node
00733   *                    at the end of the list
00734   *
00735   * @retval HAL status
00736   */
00737 HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode)
00738 {
00739   MDMA_LinkNodeTypeDef *pNode = 0;
00740   uint32_t counter = 0, nodeInserted = 0;
00741   HAL_StatusTypeDef hal_status = HAL_OK;
00742
00743   /* Check the MDMA peripheral handle */
00744   if((hmdma == NULL) || (pNewNode == NULL))
00745   {
00746     return HAL_ERROR;
00747   }
00748
00749   /* Process locked */
00750   __HAL_LOCK(hmdma);
00751
00752   if(HAL_MDMA_STATE_READY == hmdma->State)
00753   {
00754     /* Change MDMA peripheral state */
00755     hmdma->State = HAL_MDMA_STATE_BUSY;
00756
00757     /* Check if this is the first node (after the Inititlization node) */
00758     if((uint32_t)hmdma->FirstLinkedListNodeAddress == 0)
00759     {
00760       if(pPrevNode == NULL)
00761       {
00762         /* if this is the first node after the initialization
00763         connect this node to the node 0 by updating
00764         the MDMA channel CLAR register to this node address */
00765         hmdma->Instance->CLAR = (uint32_t)pNewNode;
00766         /* Set the MDMA handle First linked List node*/
00767         hmdma->FirstLinkedListNodeAddress = pNewNode;
00768
00769         /*reset New node link */
00770         pNewNode->CLAR = 0;
00771
00772         /* Update the Handle last node address */
00773         hmdma->LastLinkedListNodeAddress = pNewNode;
00774
00775         hmdma->LinkedListNodeCounter = 1;
00776       }
00777       else
00778       {
00779         hal_status = HAL_ERROR;
00780       }
00781     }
00782     else if(hmdma->FirstLinkedListNodeAddress != pNewNode)
00783     {
00784       /* Check if the node to insert already exists*/
00785       pNode = hmdma->FirstLinkedListNodeAddress;
00786       while((counter < hmdma->LinkedListNodeCounter) && (hal_status == HAL_OK))
00787       {
00788         if(pNode->CLAR == (uint32_t)pNewNode)
00789         {
00790           hal_status = HAL_ERROR; /* error this node already exist in the linked list and it is not first node */
00791         }
00792         pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
00793         counter++;
00794       }
00795
00796       if(hal_status == HAL_OK)
00797       {
00798         /* Check if the previous node is the last one in the current list or zero */
00799         if((pPrevNode == hmdma->LastLinkedListNodeAddress) || (pPrevNode == 0))
00800         {
00801           /* insert the new node at the end of the list. */
00802           pNewNode->CLAR = hmdma->LastLinkedListNodeAddress->CLAR;
00803           hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)pNewNode;
00804           /* Update the Handle last node address */
00805           hmdma->LastLinkedListNodeAddress = pNewNode;
00806           /* Increment the linked list node counter */
00807           hmdma->LinkedListNodeCounter++;
00808         }
00809         else
00810         {
00811           /*insert the new node after the pPreviousNode node */
00812           pNode = hmdma->FirstLinkedListNodeAddress;
00813           counter = 0;
00814           while((counter < hmdma->LinkedListNodeCounter) && (nodeInserted == 0))
00815           {
00816             counter++;
00817             if(pNode == pPrevNode)
00818             {
00819               /*Insert the new node after the previous one */
00820               pNewNode->CLAR = pNode->CLAR;
00821               pNode->CLAR = (uint32_t)pNewNode;
00822               /* Increment the linked list node counter */
00823               hmdma->LinkedListNodeCounter++;
00824               nodeInserted = 1;
00825             }
00826             else
00827             {
00828               pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
00829             }
00830           }
00831
00832           if(nodeInserted == 0)
00833           {
00834             hal_status = HAL_ERROR;
00835           }
00836         }
00837       }
00838     }
00839     else
00840     {
00841       hal_status = HAL_ERROR;
00842     }
00843
00844     /* Process unlocked */
00845     __HAL_UNLOCK(hmdma);
00846
00847     hmdma->State = HAL_MDMA_STATE_READY;
00848
00849     return hal_status;
00850   }
00851   else
00852   {
00853     /* Process unlocked */
00854     __HAL_UNLOCK(hmdma);
00855
00856     /* Return error status */
00857     return HAL_BUSY;
00858   }
00859 }
00860
00861 /**
00862   * @brief  Disconnect/Remove a node from the transfer linked list.
00863   * @param  hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
00864   *                 the configuration information for the specified MDMA Channel.
00865   * @param  pNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
00866   *                 to be removed from the list.
00867   *
00868   * @retval HAL status
00869   */
00870 HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode)
00871 {
00872   MDMA_LinkNodeTypeDef *ptmpNode = 0;
00873   uint32_t counter = 0, nodeDeleted = 0;
00874   HAL_StatusTypeDef hal_status = HAL_OK;
00875
00876   /* Check the MDMA peripheral handle */
00877   if((hmdma == NULL) || (pNode == NULL))
00878   {
00879     return HAL_ERROR;
00880   }
00881
00882   /* Process locked */
00883   __HAL_LOCK(hmdma);
00884
00885   if(HAL_MDMA_STATE_READY == hmdma->State)
00886   {
00887     /* Change MDMA peripheral state */
00888     hmdma->State = HAL_MDMA_STATE_BUSY;
00889
00890     /* If first and last node are null (no nodes in the list) : return error*/
00891     if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0) || (hmdma->LinkedListNodeCounter == 0))
00892     {
00893       hal_status = HAL_ERROR;
00894     }
00895     else if(hmdma->FirstLinkedListNodeAddress == pNode) /* Deleting first node */
00896     {
00897       /* Delete 1st node */
00898       if(hmdma->LastLinkedListNodeAddress == pNode)
00899       {
00900         /*if the last node is at the same time the first one (1 single node after the init node 0)
00901         then update the last node too */
00902
00903         hmdma->FirstLinkedListNodeAddress = 0;
00904         hmdma->LastLinkedListNodeAddress  = 0;
00905         hmdma->LinkedListNodeCounter = 0;
00906
00907         hmdma->Instance->CLAR = 0;
00908       }
00909       else
00910       {
00911         if((uint32_t)hmdma->FirstLinkedListNodeAddress == hmdma->LastLinkedListNodeAddress->CLAR)
00912         {
00913           /* if last node is looping to first (circular list) one update the last node connection */
00914           hmdma->LastLinkedListNodeAddress->CLAR = pNode->CLAR;
00915         }
00916
00917         /* if deleting the first node after the initialization
00918         connect the next node to the node 0 by updating
00919         the MDMA channel CLAR register to this node address */
00920         hmdma->Instance->CLAR = pNode->CLAR;
00921         hmdma->FirstLinkedListNodeAddress = (MDMA_LinkNodeTypeDef *)hmdma->Instance->CLAR;
00922         /* Update the Handle node counter */
00923         hmdma->LinkedListNodeCounter--;
00924       }
00925     }
00926     else /* Deleting any other node */
00927     {
00928       /*Deleted node is not the first one : find it  */
00929       ptmpNode = hmdma->FirstLinkedListNodeAddress;
00930       while((counter < hmdma->LinkedListNodeCounter) && (nodeDeleted == 0))
00931       {
00932         counter++;
00933         if(ptmpNode->CLAR == ((uint32_t)pNode))
00934         {
00935           /* if deleting the last node */
00936           if(pNode == hmdma->LastLinkedListNodeAddress)
00937           {
00938             /*Update the linked list last node address in the handle*/
00939             hmdma->LastLinkedListNodeAddress = ptmpNode;
00940           }
00941           /* update the next node link after deleting pMDMA_LinkedListNode */
00942           ptmpNode->CLAR = pNode->CLAR;
00943           nodeDeleted = 1;
00944           /* Update the Handle node counter */
00945           hmdma->LinkedListNodeCounter--;
00946         }
00947         else
00948         {
00949           ptmpNode = (MDMA_LinkNodeTypeDef *)ptmpNode->CLAR;
00950         }
00951       }
00952
00953       if(nodeDeleted == 0)
00954       {
00955         /* last node reashed without finding the node to delete : return error */
00956         hal_status = HAL_ERROR;
00957       }
00958     }
00959
00960     /* Process unlocked */
00961     __HAL_UNLOCK(hmdma);
00962
00963     hmdma->State = HAL_MDMA_STATE_READY;
00964
00965     return hal_status;
00966   }
00967   else
00968   {
00969     /* Process unlocked */
00970     __HAL_UNLOCK(hmdma);
00971
00972     /* Return error status */
00973     return HAL_BUSY;
00974   }
00975 }
00976
00977 /**
00978   * @brief  Make the linked list circular by connecting the last node to the first.
00979   * @param  hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
00980   *                 the configuration information for the specified MDMA Channel.
00981   * @retval HAL status
00982   */
00983 HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma)
00984 {
00985   HAL_StatusTypeDef hal_status = HAL_OK;
00986
00987   /* Check the MDMA peripheral handle */
00988   if(hmdma == NULL)
00989   {
00990     return HAL_ERROR;
00991   }
00992
00993   /* Process locked */
00994   __HAL_LOCK(hmdma);
00995
00996   if(HAL_MDMA_STATE_READY == hmdma->State)
00997   {
00998     /* Change MDMA peripheral state */
00999     hmdma->State = HAL_MDMA_STATE_BUSY;
01000
01001     /* If first and last node are null (no nodes in the list) : return error*/
01002     if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0) || (hmdma->LinkedListNodeCounter == 0))
01003     {
01004       hal_status = HAL_ERROR;
01005     }
01006     else
01007     {
01008       /* to enable circular mode Last Node should be connected to first node */
01009       hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress;
01010     }
01011
01012   }
01013   /* Process unlocked */
01014   __HAL_UNLOCK(hmdma);
01015
01016   hmdma->State = HAL_MDMA_STATE_READY;
01017
01018   return hal_status;
01019 }
01020
01021 /**
01022   * @brief  Disable the linked list circular mode by setting the last node connection to null
01023   * @param  hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
01024   *                 the configuration information for the specified MDMA Channel.
01025   * @retval HAL status
01026   */
01027 HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma)
01028 {
01029   HAL_StatusTypeDef hal_status = HAL_OK;
01030
01031   /* Check the MDMA peripheral handle */
01032   if(hmdma == NULL)
01033   {
01034     return HAL_ERROR;
01035   }
01036
01037   /* Process locked */
01038   __HAL_LOCK(hmdma);
01039
01040   if(HAL_MDMA_STATE_READY == hmdma->State)
01041   {
01042     /* Change MDMA peripheral state */
01043     hmdma->State = HAL_MDMA_STATE_BUSY;
01044
01045     /* If first and last node are null (no nodes in the list) : return error*/
01046     if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0) || (hmdma->LinkedListNodeCounter == 0))
01047     {
01048       hal_status = HAL_ERROR;
01049     }
01050     else
01051     {
01052       /* to disable circular mode Last Node should be connected to NULL */
01053       hmdma->LastLinkedListNodeAddress->CLAR = 0;
01054     }
01055
01056   }
01057   /* Process unlocked */
01058   __HAL_UNLOCK(hmdma);
01059
01060   hmdma->State = HAL_MDMA_STATE_READY;
01061
01062   return hal_status;
01063 }
01064
01065 /**
01066   * @}
01067   */
01068
01069 /** @addtogroup MDMA_Exported_Functions_Group3
01070  *
01071 @verbatim
01072  ===============================================================================
01073                       #####  IO operation functions  #####
01074  ===============================================================================
01075     [..]  This section provides functions allowing to:
01076       (+) Configure the source, destination address and data length and Start MDMA transfer
01077       (+) Configure the source, destination address and data length and
01078           Start MDMA transfer with interrupt
01079       (+) Abort MDMA transfer
01080       (+) Poll for transfer complete
01081       (+) Generate a SW request (when Request is set to MDMA_REQUEST_SW)
01082       (+) Handle MDMA interrupt request
01083
01084 @endverbatim
01085   * @{
01086   */
01087
01088 /**
01089   * @brief  Starts the MDMA Transfer.
01090   * @param  hmdma           : pointer to a MDMA_HandleTypeDef structure that contains
01091   *                           the configuration information for the specified MDMA Stream.
01092   * @param  SrcAddress      : The source memory Buffer address
01093   * @param  DstAddress      : The destination memory Buffer address
01094   * @param  BlockDataLength : The length of a block transfer in bytes
01095   * @param  BlockCount      : The number of a blocks to be transfer
01096   * @retval HAL status
01097   */
01098 HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
01099 {
01100   /* Check the parameters */
01101   assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength));
01102   assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
01103
01104   /* Check the MDMA peripheral handle */
01105   if(hmdma == NULL)
01106   {
01107     return HAL_ERROR;
01108   }
01109
01110   /* Process locked */
01111   __HAL_LOCK(hmdma);
01112
01113   if(HAL_MDMA_STATE_READY == hmdma->State)
01114   {
01115     /* Change MDMA peripheral state */
01116     hmdma->State = HAL_MDMA_STATE_BUSY;
01117
01118     /* Initialize the error code */
01119     hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
01120
01121     /* Disable the peripheral */
01122     __HAL_MDMA_DISABLE(hmdma);
01123
01124     /* Configure the source, destination address and the data length */
01125     MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount);
01126
01127
01128     /* Enable the Peripheral */
01129     __HAL_MDMA_ENABLE(hmdma);
01130
01131
01132     if(hmdma->Init.Request == MDMA_REQUEST_SW)
01133     {
01134       /* activate If SW request mode*/
01135       hmdma->Instance->CCR |=  MDMA_CCR_SWRQ;
01136     }
01137   }
01138   else
01139   {
01140     /* Process unlocked */
01141     __HAL_UNLOCK(hmdma);
01142
01143     /* Return error status */
01144     return HAL_BUSY;
01145   }
01146
01147   return HAL_OK;
01148 }
01149
01150 /**
01151   * @brief  Starts the MDMA Transfer with interrupts enabled.
01152   * @param  hmdma           : pointer to a MDMA_HandleTypeDef structure that contains
01153   *                           the configuration information for the specified MDMA Stream.
01154   * @param  SrcAddress      : The source memory Buffer address
01155   * @param  DstAddress      : The destination memory Buffer address
01156   * @param  BlockDataLength : The length of a block transfer in bytes
01157   * @param  BlockCount      : The number of a blocks to be transfer
01158   * @retval HAL status
01159   */
01160 HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
01161 {
01162   /* Check the parameters */
01163   assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength));
01164   assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
01165
01166   /* Check the MDMA peripheral handle */
01167   if(hmdma == NULL)
01168   {
01169     return HAL_ERROR;
01170   }
01171
01172   /* Process locked */
01173   __HAL_LOCK(hmdma);
01174
01175   if(HAL_MDMA_STATE_READY == hmdma->State)
01176   {
01177     /* Change MDMA peripheral state */
01178     hmdma->State = HAL_MDMA_STATE_BUSY;
01179
01180     /* Initialize the error code */
01181     hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
01182
01183     /* Disable the peripheral */
01184     __HAL_MDMA_DISABLE(hmdma);
01185
01186     /* Configure the source, destination address and the data length */
01187     MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount);
01188
01189     /* Enable Common interrupts i.e Transfer Error IT and Channel Transfer Complete IT*/
01190     __HAL_MDMA_ENABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC));
01191
01192     if(hmdma->XferBlockCpltCallback != NULL)
01193     {
01194       /* if Block transfer complete Callback is set enable the corresponding IT*/
01195       __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BT);
01196     }
01197
01198     if(hmdma->XferRepeatBlockCpltCallback != NULL)
01199     {
01200       /* if Repeated Block transfer complete Callback is set enable the corresponding IT*/
01201       __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BRT);
01202     }
01203
01204     if(hmdma->XferBufferCpltCallback != NULL)
01205     {
01206       /* if buffer transfer complete Callback is set enable the corresponding IT*/
01207       __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BFTC);
01208     }
01209
01210     /* Enable the Peripheral */
01211     __HAL_MDMA_ENABLE(hmdma);
01212
01213     if(hmdma->Init.Request == MDMA_REQUEST_SW)
01214     {
01215       /* activate If SW request mode*/
01216       hmdma->Instance->CCR |=  MDMA_CCR_SWRQ;
01217     }
01218   }
01219   else
01220   {
01221     /* Process unlocked */
01222     __HAL_UNLOCK(hmdma);
01223
01224     /* Return error status */
01225     return HAL_BUSY;
01226   }
01227
01228   return HAL_OK;
01229 }
01230
01231 /**
01232   * @brief  Aborts the MDMA Transfer.
01233   * @param  hmdma  : pointer to a MDMA_HandleTypeDef structure that contains
01234   *                 the configuration information for the specified MDMA Channel.
01235   *
01236   * @note  After disabling a MDMA Stream, a check for wait until the MDMA Channel is
01237   *        effectively disabled is added. If a Stream is disabled
01238   *        while a data transfer is ongoing, the current data will be transferred
01239   *        and the Stream will be effectively disabled only after the transfer of
01240   *        this single data is finished.
01241   * @retval HAL status
01242   */
01243 HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma)
01244 {
01245   uint32_t tickstart =  HAL_GetTick();
01246
01247   /* Check the MDMA peripheral handle */
01248   if(hmdma == NULL)
01249   {
01250     return HAL_ERROR;
01251   }
01252
01253   if(HAL_MDMA_STATE_BUSY != hmdma->State)
01254   {
01255     hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
01256
01257     /* Process Unlocked */
01258     __HAL_UNLOCK(hmdma);
01259
01260     return HAL_ERROR;
01261   }
01262   else
01263   {
01264     /* Disable all the transfer interrupts */
01265     __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC));
01266
01267     /* Disable the channel */
01268     __HAL_MDMA_DISABLE(hmdma);
01269
01270     /* Check if the MDMA Channel is effectively disabled */
01271     while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0)
01272     {
01273       /* Check for the Timeout */
01274       if( (HAL_GetTick()  - tickstart ) > HAL_TIMEOUT_MDMA_ABORT)
01275       {
01276         /* Update error code */
01277         hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT;
01278
01279         /* Process Unlocked */
01280         __HAL_UNLOCK(hmdma);
01281
01282         /* Change the MDMA state */
01283         hmdma->State = HAL_MDMA_STATE_ERROR;
01284
01285         return HAL_ERROR;
01286       }
01287     }
01288
01289     /* Clear all interrupt flags */
01290     __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BT | MDMA_FLAG_BRT | MDMA_FLAG_BFTC));
01291
01292     /* Process Unlocked */
01293     __HAL_UNLOCK(hmdma);
01294
01295     /* Change the MDMA state*/
01296     hmdma->State = HAL_MDMA_STATE_READY;
01297   }
01298
01299   return HAL_OK;
01300 }
01301
01302 /**
01303   * @brief  Aborts the MDMA Transfer in Interrupt mode.
01304   * @param  hmdma  : pointer to a MDMA_HandleTypeDef structure that contains
01305   *                 the configuration information for the specified MDMA Channel.
01306   * @retval HAL status
01307   */
01308 HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma)
01309 {
01310   /* Check the MDMA peripheral handle */
01311   if(hmdma == NULL)
01312   {
01313     return HAL_ERROR;
01314   }
01315
01316   if(HAL_MDMA_STATE_BUSY != hmdma->State)
01317   {
01318     hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
01319     return HAL_ERROR;
01320   }
01321   else
01322   {
01323     /* Set Abort State  */
01324     hmdma->State = HAL_MDMA_STATE_ABORT;
01325
01326     /* Disable the stream */
01327     __HAL_MDMA_DISABLE(hmdma);
01328   }
01329
01330   return HAL_OK;
01331 }
01332
01333 /**
01334   * @brief  Polling for transfer complete.
01335   * @param  hmdma:          pointer to a MDMA_HandleTypeDef structure that contains
01336   *                        the configuration information for the specified MDMA Channel.
01337   * @param  CompleteLevel: Specifies the MDMA level complete.
01338   * @param  Timeout:       Timeout duration.
01339   * @retval HAL status
01340   */
01341 HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, uint32_t CompleteLevel, uint32_t Timeout)
01342 {
01343   uint32_t levelFlag = 0, errorFlag = 0;
01344   uint32_t tickstart = 0;
01345
01346   /* Check the parameters */
01347   assert_param(IS_MDMA_LEVEL_COMPLETE(CompleteLevel));
01348
01349   /* Check the MDMA peripheral handle */
01350   if(hmdma == NULL)
01351   {
01352     return HAL_ERROR;
01353   }
01354
01355   if(HAL_MDMA_STATE_BUSY != hmdma->State)
01356   {
01357     /* No transfer ongoing */
01358     hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
01359
01360     return HAL_ERROR;
01361   }
01362
01363   /* Get the level transfer complete flag */
01364   levelFlag = ((CompleteLevel == HAL_MDMA_FULL_TRANSFER) ? MDMA_FLAG_CTC   :\
01365     (CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)? MDMA_FLAG_BFTC :\
01366       (CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) ? MDMA_FLAG_BT   :\
01367         MDMA_FLAG_BRT);
01368
01369
01370   /* Get timeout */
01371   tickstart = HAL_GetTick();
01372
01373   while(__HAL_MDMA_GET_FLAG(hmdma, levelFlag) == RESET)
01374   {
01375     if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != RESET))
01376     {
01377       /* Get the transfer error source flag */
01378       errorFlag = hmdma->Instance->CESR;
01379
01380       if((errorFlag & MDMA_CESR_TED) == 0)
01381       {
01382         /* Update error code : Read Transfer error  */
01383         hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER;
01384       }
01385       else
01386       {
01387         /* Update error code : Write Transfer error */
01388         hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
01389       }
01390
01391       if((errorFlag & MDMA_CESR_TEMD) != 0)
01392       {
01393         /* Update error code : Error Mask Data */
01394         hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA;
01395       }
01396
01397       if((errorFlag & MDMA_CESR_TELD) != 0)
01398       {
01399         /* Update error code : Error Linked list */
01400         hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST;
01401       }
01402
01403       if((errorFlag & MDMA_CESR_ASE) != 0)
01404       {
01405         /* Update error code : Address/Size alignment error */
01406         hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT;
01407       }
01408
01409       if((errorFlag & MDMA_CESR_BSE) != 0)
01410       {
01411         /* Update error code : Block Size error */
01412         hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE;
01413       }
01414
01415       HAL_MDMA_Abort(hmdma); /* if error then abort the current transfer */
01416
01417       /*
01418         Note that the Abort function will
01419           - Clear the transfer error flags
01420           - Unlock
01421           - Set the State
01422       */
01423
01424       return HAL_ERROR;
01425
01426     }
01427
01428     /* Check for the Timeout */
01429     if(Timeout != HAL_MAX_DELAY)
01430     {
01431       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01432       {
01433         /* Update error code */
01434         hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT;
01435
01436         HAL_MDMA_Abort(hmdma); /* if timeout then abort the current transfer */
01437
01438         /*
01439           Note that the Abort function will
01440             - Clear the transfer error flags
01441             - Unlock
01442             - Set the State
01443         */
01444
01445         return HAL_ERROR;
01446       }
01447     }
01448   }
01449
01450   /* Clear the transfer level flag */
01451   if(CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)
01452   {
01453     __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC);
01454
01455   }
01456   else if(CompleteLevel == HAL_MDMA_BLOCK_TRANSFER)
01457   {
01458     __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT));
01459
01460   }
01461   else if(CompleteLevel == HAL_MDMA_REPEAT_BLOCK_TRANSFER)
01462   {
01463     __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT | MDMA_FLAG_BRT));
01464   }
01465   else if(CompleteLevel == HAL_MDMA_FULL_TRANSFER)
01466   {
01467     __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC | MDMA_FLAG_CTC));
01468
01469     /* Process unlocked */
01470     __HAL_UNLOCK(hmdma);
01471
01472     hmdma->State = HAL_MDMA_STATE_READY;
01473   }
01474
01475   return HAL_OK;
01476 }
01477
01478 /**
01479   * @brief  Generate an MDMA SW request trigger to activate the request on the given Channel.
01480   * @param  hmdma:       pointer to a MDMA_HandleTypeDef structure that contains
01481   *                     the configuration information for the specified MDMA Stream.
01482   * @retval HAL status
01483   */
01484 HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma)
01485 {
01486   /* Check the MDMA peripheral handle */
01487   if(hmdma == NULL)
01488   {
01489     return HAL_ERROR;
01490   }
01491
01492   if((hmdma->Instance->CCR &  MDMA_CCR_EN) == RESET)
01493   {
01494     /* if no Transfer on going (MDMA enable bit not set) retrun error */
01495     hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
01496     return HAL_ERROR;
01497   }
01498   else if(((hmdma->Instance->CISR &  MDMA_CISR_CRQA) != RESET) || ((hmdma->Instance->CTCR & MDMA_CTCR_SWRM) == RESET))
01499   {
01500     /* if an MDMA ongoing request hase not yet ends or if request mode is not SW request retrun error */
01501     hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY;
01502     return HAL_ERROR;
01503   }
01504   else
01505   {
01506     /* Set the SW request bit to activate the request on the Channel */
01507     hmdma->Instance->CCR |= MDMA_CCR_SWRQ;
01508
01509     return HAL_OK;
01510   }
01511 }
01512
01513 /**
01514   * @brief  Handles MDMA interrupt request.
01515   * @param  hmdma: pointer to a MDMA_HandleTypeDef structure that contains
01516   *               the configuration information for the specified MDMA Stream.
01517   * @retval None
01518   */
01519 void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma)
01520 {
01521   __IO uint32_t count = 0;
01522   uint32_t timeout = SystemCoreClock / 9600;
01523
01524   uint32_t generalIntFlag, errorFlag;
01525
01526   /* General Interrupt Flag management ****************************************/
01527   generalIntFlag =  1 << (((uint32_t)hmdma->Instance - (uint32_t)(MDMA_Channel0))/HAL_MDMA_CHANNEL_SIZE);
01528   if((MDMA->GISR0 & generalIntFlag) == RESET)
01529   {
01530     return; /* the  General interrupt flag for the current channel is down , nothing to do */
01531   }
01532
01533   /* Transfer Error Interrupt management ***************************************/
01534   if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != RESET))
01535   {
01536     if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_TE) != RESET)
01537     {
01538       /* Disable the transfer error interrupt */
01539       __HAL_MDMA_DISABLE_IT(hmdma, MDMA_IT_TE);
01540
01541       /* Get the transfer error source flag */
01542       errorFlag = hmdma->Instance->CESR;
01543
01544       if((errorFlag & MDMA_CESR_TED) == 0)
01545       {
01546         /* Update error code : Read Transfer error  */
01547         hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER;
01548       }
01549       else
01550       {
01551         /* Update error code : Write Transfer error */
01552         hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
01553       }
01554
01555       if((errorFlag & MDMA_CESR_TEMD) != 0)
01556       {
01557         /* Update error code : Error Mask Data */
01558         hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA;
01559       }
01560
01561       if((errorFlag & MDMA_CESR_TELD) != 0)
01562       {
01563         /* Update error code : Error Linked list */
01564         hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST;
01565       }
01566
01567       if((errorFlag & MDMA_CESR_ASE) != 0)
01568       {
01569         /* Update error code : Address/Size alignment error */
01570         hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT;
01571       }
01572
01573       if((errorFlag & MDMA_CESR_BSE) != 0)
01574       {
01575         /* Update error code : Block Size error error */
01576         hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE;
01577       }
01578
01579       /* Clear the transfer error flags */
01580       __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE);
01581     }
01582   }
01583
01584   /* Buffer Transfer Complete Interrupt management ******************************/
01585   if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BFTC) != RESET))
01586   {
01587     if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BFTC) != RESET)
01588     {
01589       /* Clear the buffer transfer complete flag */
01590       __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC);
01591
01592       if(hmdma->XferBufferCpltCallback != NULL)
01593       {
01594         /* Buffer transfer callback */
01595         hmdma->XferBufferCpltCallback(hmdma);
01596       }
01597     }
01598   }
01599
01600   /* Block Transfer Complete Interrupt management ******************************/
01601   if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BT) != RESET))
01602   {
01603     if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BT) != RESET)
01604     {
01605       /* Clear the block transfer complete flag */
01606       __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BT);
01607
01608       if(hmdma->XferBlockCpltCallback != NULL)
01609       {
01610         /* Block transfer callback */
01611         hmdma->XferBlockCpltCallback(hmdma);
01612       }
01613     }
01614   }
01615
01616   /* Repeated Block Transfer Complete Interrupt management ******************************/
01617   if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BRT) != RESET))
01618   {
01619     if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BRT) != RESET)
01620     {
01621       /* Clear the repeat block transfer complete flag */
01622       __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BRT);
01623
01624       if(hmdma->XferRepeatBlockCpltCallback != NULL)
01625       {
01626         /* Repeated Block transfer callback */
01627         hmdma->XferRepeatBlockCpltCallback(hmdma);
01628       }
01629     }
01630   }
01631
01632   /* Channel Transfer Complete Interrupt management ***********************************/
01633   if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_CTC) != RESET))
01634   {
01635     if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_CTC) != RESET)
01636     {
01637       /* Disable all the transfer interrupts */
01638       __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC));
01639
01640       if(HAL_MDMA_STATE_ABORT == hmdma->State)
01641       {
01642         /* Process Unlocked */
01643         __HAL_UNLOCK(hmdma);
01644
01645         /* Change the DMA state */
01646         hmdma->State = HAL_MDMA_STATE_READY;
01647
01648         if(hmdma->XferAbortCallback != NULL)
01649         {
01650           hmdma->XferAbortCallback(hmdma);
01651         }
01652         return;
01653
01654       }
01655       /* Clear the Channel Transfer Complete flag */
01656       __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_CTC);
01657
01658       /* Process Unlocked */
01659       __HAL_UNLOCK(hmdma);
01660
01661       /* Change MDMA peripheral state */
01662       hmdma->State = HAL_MDMA_STATE_READY;
01663
01664       if(hmdma->XferCpltCallback != NULL)
01665       {
01666         /* Channel Transfer Complete callback */
01667         hmdma->XferCpltCallback(hmdma);
01668       }
01669     }
01670   }
01671
01672   /* manage error case */
01673   if(hmdma->ErrorCode != HAL_MDMA_ERROR_NONE)
01674   {
01675     hmdma->State = HAL_MDMA_STATE_ABORT;
01676
01677     /* Disable the channel */
01678     __HAL_MDMA_DISABLE(hmdma);
01679
01680     do
01681     {
01682       if (++count > timeout)
01683       {
01684         break;
01685       }
01686     }
01687     while((hmdma->Instance->CCR & MDMA_CCR_EN) != RESET);
01688
01689     /* Process Unlocked */
01690     __HAL_UNLOCK(hmdma);
01691
01692     if((hmdma->Instance->CCR & MDMA_CCR_EN) != RESET)
01693     {
01694       /* Change the MDMA state to error if MDMA disable fails */
01695       hmdma->State = HAL_MDMA_STATE_ERROR;
01696     }
01697     else
01698     {
01699       /* Change the MDMA state to Ready if MDMA disable success */
01700       hmdma->State = HAL_MDMA_STATE_READY;
01701     }
01702
01703
01704     if (hmdma->XferErrorCallback != NULL)
01705     {
01706       /* Transfer error callback */
01707       hmdma->XferErrorCallback(hmdma);
01708     }
01709   }
01710
01711 }
01712
01713 /**
01714   * @}
01715   */
01716
01717 /** @addtogroup MDMA_Exported_Functions_Group4
01718  *
01719 @verbatim
01720  ===============================================================================
01721                     ##### State and Errors functions #####
01722  ===============================================================================
01723     [..]
01724     This subsection provides functions allowing to
01725       (+) Check the MDMA state
01726       (+) Get error code
01727
01728 @endverbatim
01729   * @{
01730   */
01731
01732 /**
01733   * @brief  Returns the MDMA state.
01734   * @param  hmdma: pointer to a MDMA_HandleTypeDef structure that contains
01735   *               the configuration information for the specified MDMA Stream.
01736   * @retval HAL state
01737   */
01738 HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma)
01739 {
01740   return hmdma->State;
01741 }
01742
01743 /**
01744   * @brief  Return the MDMA error code
01745   * @param  hmdma : pointer to a MDMA_HandleTypeDef structure that contains
01746   *              the configuration information for the specified MDMA Stream.
01747   * @retval MDMA Error Code
01748   */
01749 uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma)
01750 {
01751   return hmdma->ErrorCode;
01752 }
01753
01754 /**
01755   * @}
01756   */
01757
01758 /**
01759   * @}
01760   */
01761
01762 /** @addtogroup JPEG_Private_Functions
01763   * @{
01764   */
01765
01766 /**
01767   * @brief  Sets the MDMA Transfer parameter.
01768   * @param  hmdma:       pointer to a MDMA_HandleTypeDef structure that contains
01769   *                     the configuration information for the specified MDMA Stream.
01770   * @param  SrcAddress: The source memory Buffer address
01771   * @param  DstAddress: The destination memory Buffer address
01772   * @param  BlockDataLength : The length of a block transfer in bytes
01773   * @param  BlockCount: The number of a blocks to be transfer
01774   * @retval HAL status
01775   */
01776 static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
01777 {
01778   uint32_t addressMask;
01779   /* Configure MDMA Channel data length */
01780   MODIFY_REG(hmdma->Instance->CBNDTR ,MDMA_CBNDTR_BNDT, (BlockDataLength & MDMA_CBNDTR_BNDT));
01781
01782   /*Configure the MDMA block repeat count*/
01783   MODIFY_REG( hmdma->Instance->CBNDTR , MDMA_CBNDTR_BRC , ((BlockCount - 1) << POSITION_VAL(MDMA_CBNDTR_BRC)) & MDMA_CBNDTR_BRC);
01784
01785   /* Clear all interrupt flags */
01786   __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_CISR_BRTIF | MDMA_CISR_BTIF | MDMA_CISR_TCIF);
01787
01788   /* Configure MDMA Channel destination address */
01789   hmdma->Instance->CDAR = DstAddress;
01790
01791   /* Configure MDMA Channel Source address */
01792   hmdma->Instance->CSAR = SrcAddress;
01793
01794   addressMask = SrcAddress & 0xFF000000U;
01795   if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
01796   {
01797     /*The AHBSbus is used as source (read operation) on channel x */
01798     hmdma->Instance->CTBR |= MDMA_CTBR_SBUS;
01799   }
01800   else
01801   {
01802     /*The AXI bus is used as source (read operation) on channel x */
01803     hmdma->Instance->CTBR &= (~MDMA_CTBR_SBUS);
01804   }
01805
01806   addressMask = DstAddress & 0xFF000000U;
01807   if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
01808   {
01809     /*The AHB bus is used as destination (write operation) on channel x */
01810     hmdma->Instance->CTBR |= MDMA_CTBR_DBUS;
01811   }
01812   else
01813   {
01814     /*The AXI bus is used as destination (write operation) on channel x */
01815     hmdma->Instance->CTBR &= (~MDMA_CTBR_DBUS);
01816   }
01817
01818   /* Set the linked list rgeitser to the first node of the list */
01819   hmdma->Instance->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress;
01820 }
01821
01822 static void MDMA_Init(MDMA_HandleTypeDef *hmdma)
01823 {
01824   uint32_t blockoffset = 0;
01825
01826   /* Prepare the MDMA Channel configuration */
01827   hmdma->Instance->CCR = hmdma->Init.Priority  | hmdma->Init.Endianness;
01828
01829   /* write new CTCR Register value */
01830   hmdma->Instance->CTCR =  hmdma->Init.SourceInc      | hmdma->Init.DestinationInc  | \
01831                    hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize  | \
01832                    hmdma->Init.DataAlignment  | hmdma->Init.SourceBurst   | \
01833                    hmdma->Init.DestBurst      | \
01834                    ((hmdma->Init.BufferTransferLength - 1) << POSITION_VAL(MDMA_CTCR_TLEN)) | \
01835                    hmdma->Init.TransferTriggerMode;
01836
01837   /* If SW request set the CTCR register to SW Request Mode*/
01838   if(hmdma->Init.Request == MDMA_REQUEST_SW)
01839   {
01840     /*
01841     -If the request is done by SW : BWM could be set to 1 or 0.
01842     -If the request is done by a peripheral :
01843     If mask address not set (0) => BWM must be set to 0
01844     If mask address set (different than 0) => BWM could be set to 1 or 0
01845     */
01846     hmdma->Instance->CTCR |= (MDMA_CTCR_SWRM | MDMA_CTCR_BWM);
01847   }
01848
01849   /* Reset CBNDTR Register */
01850   hmdma->Instance->CBNDTR = 0;
01851
01852   /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */
01853   if(hmdma->Init.SourceBlockAddressOffset < 0)
01854   {
01855     hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRSUM;
01856     /*write new CBRUR Register value : source repeat block offset */
01857     blockoffset = (-1 * hmdma->Init.SourceBlockAddressOffset);
01858     hmdma->Instance->CBRUR = (blockoffset & 0x0000FFFFU);
01859   }
01860   else
01861   {
01862     /*write new CBRUR Register value : source repeat block offset */
01863     hmdma->Instance->CBRUR = (((uint32_t)hmdma->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
01864   }
01865
01866   /* if block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */
01867   if(hmdma->Init.DestBlockAddressOffset < 0)
01868   {
01869     hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRDUM;
01870     /*write new CBRUR Register value : destination repeat block offset */
01871     blockoffset = (-1 * hmdma->Init.DestBlockAddressOffset);
01872     hmdma->Instance->CBRUR |= ((blockoffset & 0x0000FFFFU) << POSITION_VAL(MDMA_CBRUR_DUV));
01873   }
01874   else
01875   {
01876     /*write new CBRUR Register value : destination repeat block offset */
01877     hmdma->Instance->CBRUR |= (((uint32_t)hmdma->Init.DestBlockAddressOffset) & 0x0000FFFFU) << POSITION_VAL(MDMA_CBRUR_DUV);
01878   }
01879
01880   /* if HW request set the HW request and the requet CleraMask and ClearData MaskData,  */
01881   if(hmdma->Init.Request != MDMA_REQUEST_SW)
01882   {
01883     /* Set the HW request in CTRB register  */
01884     hmdma->Instance->CTBR = hmdma->Init.Request & MDMA_CTBR_TSEL;
01885   }
01886   else /* SW request : reset the CTBR register */
01887   {
01888     hmdma->Instance->CTBR = 0;
01889   }
01890
01891   /*Write Link Address Register*/
01892   hmdma->Instance->CLAR =  0;
01893 }
01894
01895 /**
01896   * @}
01897   */
01898
01899 #endif /* HAL_MDMA_MODULE_ENABLED */
01900 /**
01901   * @}
01902   */
01903
01904 /**
01905   * @}
01906   */
01907
01908 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_mdma.h Source File

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stm32h7xx_hal_mdma.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_mdma.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of DMA HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_MDMA_H
00040 #define __STM32H7xx_HAL_MDMA_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup MDMA
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup MDMA_Exported_Types MDMA Exported Types
00060   * @brief    MDMA Exported Types
00061   * @{
00062   */
00063
00064 /**
00065   * @brief  MDMA Configuration Structure definition
00066   */
00067 typedef struct
00068 {
00069
00070   uint32_t Request;                 /*!< Specifies the MDMA request.
00071                                         This parameter can be a value of @ref MDMA_Request_selection*/
00072
00073   uint32_t TransferTriggerMode;     /*!< Specifies the Trigger Transfer mode : each request triggers a :
00074                                          a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer
00075                                          This parameter can be a value of @ref MDMA_Transfer_TriggerMode  */
00076
00077   uint32_t Priority;                 /*!< Specifies the software priority for the MDMAy channelx.
00078                                          This parameter can be a value of @ref MDMA_Priority_level */
00079
00080   uint32_t Endianness;                /*!< Specifies if the MDMA transactions preserve the Little endianness.
00081                                          This parameter can be a value of @ref MDMA_Endianness */
00082
00083   uint32_t SourceInc;                /*!< Specifies if the Source increment mode .
00084                                          This parameter can be a value of @ref MDMA_Source_increment_mode */
00085
00086   uint32_t DestinationInc;           /*!< Specifies if the Destination increment mode .
00087                                          This parameter can be a value of @ref MDMA_Destination_increment_mode */
00088
00089   uint32_t SourceDataSize;           /*!< Specifies the source data size.
00090                                          This parameter can be a value of @ref MDMA_Source_data_size */
00091
00092   uint32_t DestDataSize;             /*!< Specifies the destination data size.
00093                                           This parameter can be a value of @ref MDMA_Destination_data_size */
00094
00095
00096   uint32_t DataAlignment;            /*!< Specifies the source to destination Memory data packing/padding mode.
00097                                             This parameter can be a value of @ref MDMA_data_Alignment */
00098
00099   uint32_t BufferTransferLength;      /*!< Specifies the buffer Transfer Length (number of bytes),
00100                                           this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)*/
00101
00102   uint32_t SourceBurst;              /*!< Specifies the Burst transfer configuration for the source memory transfers.
00103                                          It specifies the amount of data to be transferred in a single non interruptable
00104                                          transaction.
00105                                          This parameter can be a value of @ref MDMA_Source_burst
00106                                          @note : the burst may be FIXED/INCR based on SourceInc value ,
00107                                          the BURST must be programmed as to ensure that the burst size will be lower than than
00108                                          BufferTransferLength */
00109
00110   uint32_t DestBurst;                 /*!< Specifies the Burst transfer configuration for the destination memory transfers.
00111                                            It specifies the amount of data to be transferred in a single non interruptable
00112                                            transaction.
00113                                            This parameter can be a value of @ref MDMA_Destination_burst
00114                                            @note : the burst may be FIXED/INCR based on DestinationInc value ,
00115                                            the BURST must be programmed as to ensure that the burst size will be lower than than
00116                                            BufferTransferLength */
00117
00118   int32_t SourceBlockAddressOffset;   /*!< this field specifies the Next block source address offset
00119                                            signed value : if > 0 then  increment the next block source Address by offset from where the last block ends
00120                                                           if < 0 then  decrement the next block source Address by offset from where the last block ends
00121                                                           if == 0, the next block source address starts from where the last block ends
00122                                        */
00123
00124
00125   int32_t DestBlockAddressOffset;      /*!< this field specifies the Next block destination address offset
00126                                            signed value : if > 0 then  increment the next block destination Address by offset from where the last block ends
00127                                                           if < 0 then  decrement the next block destination Address by offset from where the last block ends
00128                                                           if == 0, the next block destination address starts from where the last block ends
00129                                        */
00130
00131 }MDMA_InitTypeDef;
00132
00133 /**
00134   * @brief  HAL MDMA linked list node structure definition
00135   * @note   The Linked list node allows to define a new MDMA configuration
00136   *         (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers).
00137   *         When CLAR register is configured to a non NULL value , each time a transfer ends,
00138   *         a new configuration (linked list node) is automatically loaded from the address given in CLAR register.
00139   */
00140 typedef struct
00141 {
00142   __IO uint32_t CTCR;     /*!< New CTCR register configuration for the given MDMA linked list node   */
00143   __IO uint32_t CBNDTR;   /*!< New CBNDTR register configuration for the given MDMA linked list node */
00144   __IO uint32_t CSAR;     /*!< New CSAR register configuration for the given MDMA linked list node   */
00145   __IO uint32_t CDAR;     /*!< New CDAR register configuration for the given MDMA linked list node   */
00146   __IO uint32_t CBRUR;    /*!< New CBRUR register configuration for the given MDMA linked list node  */
00147   __IO uint32_t CLAR;     /*!< New CLAR register configuration for the given MDMA linked list node   */
00148   __IO uint32_t CTBR;     /*!< New CTBR register configuration for the given MDMA linked list node   */
00149   __IO uint32_t Reserved; /*!< Reserved register*/
00150   __IO uint32_t CMAR;     /*!< New CMAR register configuration for the given MDMA linked list node   */
00151   __IO uint32_t CMDR;     /*!< New CMDR register configuration for the given MDMA linked list node   */
00152
00153 }MDMA_LinkNodeTypeDef;
00154
00155 /**
00156   * @brief  HAL MDMA linked list node configuration structure definition
00157   * @note   used with HAL_MDMA_LinkedList_CreateNode function
00158   */
00159 typedef struct
00160 {
00161   MDMA_InitTypeDef Init;            /*!< configuration of the specified MDMA Linked List Node    */
00162   uint32_t         SrcAddress;      /*!< The source memory address for the Linked list Node      */
00163   uint32_t         DstAddress;      /*!< The destination memory address for the Linked list Node */
00164   uint32_t         BlockDataLength; /*!< The length of a block transfer in bytes                 */
00165   uint32_t         BlockCount;      /*!< The number of a blocks to be transfer                   */
00166
00167   uint32_t PostRequestMaskAddress;  /*!< specifies the address to be updated (written) with PostRequestMaskData after a request is served.
00168                                          PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served  */
00169
00170   uint32_t PostRequestMaskData;     /*!< specifies the value to be written to PostRequestMaskAddress after a request is served.
00171                                          PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served  */
00172
00173
00174 }MDMA_LinkNodeConfTypeDef;
00175
00176
00177 /**
00178   * @brief  HAL MDMA State structure definition
00179   */
00180 typedef enum
00181 {
00182   HAL_MDMA_STATE_RESET               = 0x00U,  /*!< MDMA not yet initialized or disabled */
00183   HAL_MDMA_STATE_READY               = 0x01U,  /*!< MDMA initialized and ready for use   */
00184   HAL_MDMA_STATE_BUSY                = 0x02U,  /*!< MDMA process is ongoing              */
00185   HAL_MDMA_STATE_ERROR               = 0x03U,  /*!< MDMA error state                     */
00186   HAL_MDMA_STATE_ABORT               = 0x04U,  /*!< DMA Abort state                      */
00187
00188 }HAL_MDMA_StateTypeDef;
00189
00190 /**
00191   * @brief  HAL MDMA Level Complete structure definition
00192   */
00193 typedef enum
00194 {
00195   HAL_MDMA_FULL_TRANSFER         = 0x00U,   /*!< Full transfer         */
00196   HAL_MDMA_BUFFER_TRANSFER       = 0x01U,   /*!< Buffer Transfer       */
00197   HAL_MDMA_BLOCK_TRANSFER        = 0x02U,   /*!< Block Transfer        */
00198   HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U    /*!< repeat block Transfer */
00199
00200 }HAL_MDMA_LevelCompleteTypeDef;
00201
00202 /**
00203   * @brief  HAL MDMA Callbacks IDs structure definition
00204   */
00205 typedef enum
00206 {
00207   HAL_MDMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer           */
00208   HAL_MDMA_XFER_BUFFERCPLT_CB_ID    = 0x01U,    /*!< Buffer Transfer         */
00209   HAL_MDMA_XFER_BLOCKCPLT_CB_ID     = 0x02U,    /*!< Block Transfer          */
00210   HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID  = 0x03U,    /*!< Repeated Block Transfer */
00211   HAL_MDMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error                   */
00212   HAL_MDMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort                   */
00213   HAL_MDMA_XFER_ALL_CB_ID           = 0x06U     /*!< All                     */
00214
00215 }HAL_MDMA_CallbackIDTypeDef;
00216
00217
00218 /**
00219   * @brief  MDMA handle Structure definition
00220   */
00221 typedef struct __MDMA_HandleTypeDef
00222 {
00223   MDMA_Channel_TypeDef *Instance;                                                              /*!< Register base address                  */
00224
00225   MDMA_InitTypeDef      Init;                                                                  /*!< MDMA communication parameters          */
00226
00227
00228   HAL_LockTypeDef       Lock;                                                                  /*!< MDMA locking object                    */
00229
00230   __IO HAL_MDMA_StateTypeDef  State;                                                           /*!< MDMA transfer state                    */
00231
00232   void                  *Parent;                                                               /*!< Parent object state                    */
00233
00234   void                  (* XferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);            /*!< MDMA transfer complete callback        */
00235
00236   void                  (* XferBufferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);      /*!< MDMA buffer transfer complete callback */
00237
00238   void                  (* XferBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);       /*!< MDMA block transfer complete callback  */
00239
00240   void                  (* XferRepeatBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer repeat callback    */
00241
00242   void                  (* XferErrorCallback)( struct __MDMA_HandleTypeDef * hmdma);           /*!< MDMA transfer error callback           */
00243
00244   void                  (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma);           /*!< MDMA transfer Abort callback           */
00245
00246
00247   MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress;                                             /*!< specifies the first node address of the transfer list
00248                                                                                                      (after the initial node defined by the Init struct)
00249                                                                                                     this parameter is used internally by the MDMA driver
00250                                                                                                      to construct the liked list node
00251                                                                                                 */
00252
00253   MDMA_LinkNodeTypeDef *LastLinkedListNodeAddress;                                             /*!< specifies the last node address of the transfer list
00254                                                                                                     this parameter is used internally by the MDMA driver
00255                                                                                                      to construct the liked list node
00256                                                                                                 */
00257   uint32_t LinkedListNodeCounter;                                                               /*!< Number of nodes in the MDMA linked list */
00258
00259   __IO uint32_t          ErrorCode;                                                            /*!< MDMA Error code                        */
00260
00261 } MDMA_HandleTypeDef;
00262
00263 /**
00264   * @}
00265   */
00266
00267 /* Exported constants --------------------------------------------------------*/
00268
00269 /** @defgroup MDMA_Exported_Constants MDMA Exported Constants
00270   * @brief    MDMA Exported constants
00271   * @{
00272   */
00273
00274 /** @defgroup MDMA_Error_Codes MDMA Error Codes
00275   * @brief    MDMA Error Codes
00276   * @{
00277   */
00278 #define HAL_MDMA_ERROR_NONE        ((uint32_t)0x00000000U)   /*!< No error                               */
00279 #define HAL_MDMA_ERROR_READ_XFER   ((uint32_t)0x00000001U)   /*!< Read Transfer error                    */
00280 #define HAL_MDMA_ERROR_WRITE_XFER  ((uint32_t)0x00000002U)   /*!< Write Transfer error                   */
00281 #define HAL_MDMA_ERROR_MASK_DATA   ((uint32_t)0x00000004U)   /*!< Error Mask Data error                  */
00282 #define HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U)   /*!< Linked list Data error                 */
00283 #define HAL_MDMA_ERROR_ALIGNMENT   ((uint32_t)0x00000010U)   /*!< Address/Size alignment  error          */
00284 #define HAL_MDMA_ERROR_BLOCK_SIZE  ((uint32_t)0x00000020U)   /*!< Block Size error                       */
00285 #define HAL_MDMA_ERROR_TIMEOUT     ((uint32_t)0x00000040U)   /*!< Timeout error                          */
00286 #define HAL_MDMA_ERROR_NO_XFER     ((uint32_t)0x00000080U)   /*!< Abort or SW trigger requested with no Xfer ongoing   */
00287 #define HAL_MDMA_ERROR_BUSY        ((uint32_t)0x00000100U)   /*!< DeInit or SW trigger requested with Xfer ongoing   */
00288
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup MDMA_Request_selection MDMA Request selection
00294   * @brief    MDMA_Request_selection
00295   * @{
00296   */
00297
00298 #define MDMA_REQUEST_DMA1_Stream0_TC      ((uint32_t)0x00000000U)  /*!< MDMA HW request is DMA1 Stream 0 Transfer Complete Flag   */
00299 #define MDMA_REQUEST_DMA1_Stream1_TC      ((uint32_t)0x00000001U)  /*!< MDMA HW request is DMA1 Stream 1 Transfer Complete Flag   */
00300 #define MDMA_REQUEST_DMA1_Stream2_TC      ((uint32_t)0x00000002U)  /*!< MDMA HW request is DMA1 Stream 2 Transfer Complete Flag   */
00301 #define MDMA_REQUEST_DMA1_Stream3_TC      ((uint32_t)0x00000003U)  /*!< MDMA HW request is DMA1 Stream 3 Transfer Complete Flag   */
00302 #define MDMA_REQUEST_DMA1_Stream4_TC      ((uint32_t)0x00000004U)  /*!< MDMA HW request is DMA1 Stream 4 Transfer Complete Flag   */
00303 #define MDMA_REQUEST_DMA1_Stream5_TC      ((uint32_t)0x00000005U)  /*!< MDMA HW request is DMA1 Stream 5 Transfer Complete Flag   */
00304 #define MDMA_REQUEST_DMA1_Stream6_TC      ((uint32_t)0x00000006U)  /*!< MDMA HW request is DMA1 Stream 6 Transfer Complete Flag   */
00305 #define MDMA_REQUEST_DMA1_Stream7_TC      ((uint32_t)0x00000007U)  /*!< MDMA HW request is DMA1 Stream 7 Transfer Complete Flag   */
00306 #define MDMA_REQUEST_DMA2_Stream0_TC      ((uint32_t)0x00000008U)  /*!< MDMA HW request is DMA2 Stream 0 Transfer Complete Flag   */
00307 #define MDMA_REQUEST_DMA2_Stream1_TC      ((uint32_t)0x00000009U)  /*!< MDMA HW request is DMA2 Stream 1 Transfer Complete Flag   */
00308 #define MDMA_REQUEST_DMA2_Stream2_TC      ((uint32_t)0x0000000AU)  /*!< MDMA HW request is DMA2 Stream 2 Transfer Complete Flag   */
00309 #define MDMA_REQUEST_DMA2_Stream3_TC      ((uint32_t)0x0000000BU)  /*!< MDMA HW request is DMA2 Stream 3 Transfer Complete Flag   */
00310 #define MDMA_REQUEST_DMA2_Stream4_TC      ((uint32_t)0x0000000CU)  /*!< MDMA HW request is DMA2 Stream 4 Transfer Complete Flag   */
00311 #define MDMA_REQUEST_DMA2_Stream5_TC      ((uint32_t)0x0000000DU)  /*!< MDMA HW request is DMA2 Stream 5 Transfer Complete Flag   */
00312 #define MDMA_REQUEST_DMA2_Stream6_TC      ((uint32_t)0x0000000EU)  /*!< MDMA HW request is DMA2 Stream 6 Transfer Complete Flag   */
00313 #define MDMA_REQUEST_DMA2_Stream7_TC      ((uint32_t)0x0000000FU)  /*!< MDMA HW request is DMA2 Stream 7 Transfer Complete Flag   */
00314 #define MDMA_REQUEST_LTDC_LINE_IT         ((uint32_t)0x00000010U)  /*!< MDMA HW request is LTDC Line interrupt Flag               */
00315 #define MDMA_REQUEST_JPEG_INFIFO_TH       ((uint32_t)0x00000011U)  /*!< MDMA HW request is JPEG Input FIFO threshold Flag         */
00316 #define MDMA_REQUEST_JPEG_INFIFO_NF       ((uint32_t)0x00000012U)  /*!< MDMA HW request is JPEG Input FIFO not full Flag          */
00317 #define MDMA_REQUEST_JPEG_OUTFIFO_TH      ((uint32_t)0x00000013U)  /*!< MDMA HW request is JPEG Output FIFO threshold Flag        */
00318 #define MDMA_REQUEST_JPEG_OUTFIFO_NE      ((uint32_t)0x00000014U)  /*!< MDMA HW request is JPEG Output FIFO not empty Flag        */
00319 #define MDMA_REQUEST_JPEG_END_CONVERSION  ((uint32_t)0x00000015U)  /*!< MDMA HW request is JPEG End of conversion Flag            */
00320 #define MDMA_REQUEST_QUADSPI_FIFO_TH      ((uint32_t)0x00000016U)  /*!< MDMA HW request is QSPI FIFO threshold Flag               */
00321 #define MDMA_REQUEST_QUADSPI_TC           ((uint32_t)0x00000017U)  /*!< MDMA HW request is QSPI Transfer complete Flag            */
00322 #define MDMA_REQUEST_DMA2D_CLUT_TC        ((uint32_t)0x00000018U)  /*!< MDMA HW request is DMA2D CLUT Transfer Complete Flag      */
00323 #define MDMA_REQUEST_DMA2D_TC             ((uint32_t)0x00000019U)  /*!< MDMA HW request is DMA2D Transfer Complete Flag           */
00324 #define MDMA_REQUEST_DMA2D_TW             ((uint32_t)0x0000001AU)  /*!< MDMA HW request is DMA2D Transfer Watermark Flag          */
00325
00326 #if defined(DSI)
00327 #define MDMA_REQUEST_DSI_TEARINGE_FFECT   ((uint32_t)0x0000001BU)  /*!< MDMA HW request is DSI Tearing Effect Flag                */
00328 #define MDMA_REQUEST_DSI_END_REFRESH      ((uint32_t)0x0000001CU)  /*!< MDMA HW request is DSI End of refresh  Flag               */
00329 #endif /* DSI */
00330
00331 #define MDMA_REQUEST_SDMMC1_END_DATA      ((uint32_t)0x0000001DU)  /*!< MDMA HW request is SDMMC1 End of Data Flag                */
00332
00333 #define MDMA_REQUEST_SW                   ((uint32_t)0x40000000U) /*!< MDMA SW request   */
00334
00335 /**
00336   * @}
00337   */
00338
00339 /** @defgroup MDMA_Transfer_TriggerMode MDMA Transfer Trigger  Mode
00340   * @brief    MDMA Transfer Trigger Mode
00341   * @{
00342   */
00343 #define MDMA_BUFFER_TRANSFER          ((uint32_t)0x00000000U)        /*!< Each MDMA request (SW or HW) triggers a buffer transfer */
00344 #define MDMA_BLOCK_TRANSFER           ((uint32_t)MDMA_CTCR_TRGM_0)   /*!< Each MDMA request (SW or HW) triggers a block transfer */
00345 #define MDMA_REPEAT_BLOCK_TRANSFER    ((uint32_t)MDMA_CTCR_TRGM_1)   /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */
00346 #define MDMA_FULL_TRANSFER            ((uint32_t)MDMA_CTCR_TRGM)     /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */
00347
00348 /**
00349   * @}
00350   */
00351
00352 /** @defgroup MDMA_Priority_level MDMA Priority level
00353   * @brief    MDMA Priority level
00354   * @{
00355   */
00356 #define MDMA_PRIORITY_LOW             ((uint32_t)0x00000000U)     /*!< Priority level: Low      */
00357 #define MDMA_PRIORITY_MEDIUM          ((uint32_t)MDMA_CCR_PL_0)  /*!< Priority level: Medium    */
00358 #define MDMA_PRIORITY_HIGH            ((uint32_t)MDMA_CCR_PL_1)  /*!< Priority level: High      */
00359 #define MDMA_PRIORITY_VERY_HIGH       ((uint32_t)MDMA_CCR_PL)    /*!< Priority level: Very High */
00360
00361 /**
00362   * @}
00363   */
00364
00365
00366 /** @defgroup MDMA_Endianness MDMA Endianness
00367   * @brief    MDMA Endianness
00368   * @{
00369   */
00370 #define MDMA_LITTLE_ENDIANNESS_PRESERVE          ((uint32_t)0x00000000U)   /*!< little endianness preserve    */
00371 #define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE     ((uint32_t)MDMA_CCR_BEX)  /*!< BYTEs endianness exchange when destination data size is > Byte  */
00372 #define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX)  /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD*/
00373 #define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE     ((uint32_t)MDMA_CCR_WEX)  /*!< WORDs endianness exchange  when destination data size is > DOUBLE WORD */
00374
00375 /**
00376   * @}
00377   */
00378
00379 /** @defgroup MDMA_Source_increment_mode MDMA Source increment mode
00380   * @brief    MDMA Source increment mode
00381   * @{
00382   */
00383 #define MDMA_SRC_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed */
00384 #define MDMA_SRC_INC_BYTE         ((uint32_t)MDMA_CTCR_SINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)*/
00385 #define MDMA_SRC_INC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
00386 #define MDMA_SRC_INC_WORD         ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)*/
00387 #define MDMA_SRC_INC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS)   /*!< Source address pointer is incremented by a double Word (64 bits)) */
00388 #define MDMA_SRC_DEC_BYTE         ((uint32_t)MDMA_CTCR_SINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)*/
00389 #define MDMA_SRC_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits) */
00390 #define MDMA_SRC_DEC_WORD         ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)*/
00391 #define MDMA_SRC_DEC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS)     /*!< Source address pointer is decremented by a double Word (64 bits)) */
00392
00393 /**
00394   * @}
00395   */
00396
00397 /** @defgroup MDMA_Destination_increment_mode MDMA Destination increment mode
00398   * @brief    MDMA Destination increment mode
00399   * @{
00400   */
00401 #define MDMA_DEST_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed */
00402 #define MDMA_DEST_INC_BYTE         ((uint32_t)MDMA_CTCR_DINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)*/
00403 #define MDMA_DEST_INC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
00404 #define MDMA_DEST_INC_WORD         ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)*/
00405 #define MDMA_DEST_INC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS)   /*!< Source address pointer is incremented by a double Word (64 bits)) */
00406 #define MDMA_DEST_DEC_BYTE         ((uint32_t)MDMA_CTCR_DINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)*/
00407 #define MDMA_DEST_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits) */
00408 #define MDMA_DEST_DEC_WORD         ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)*/
00409 #define MDMA_DEST_DEC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS)     /*!< Source address pointer is decremented by a double Word (64 bits)) */
00410
00411 /**
00412   * @}
00413   */
00414
00415 /** @defgroup MDMA_Source_data_size MDMA Source data size
00416   * @brief    MDMA Source data size
00417   * @{
00418   */
00419 #define MDMA_SRC_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Source data size is Byte */
00420 #define MDMA_SRC_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_SSIZE_0)   /*!< Source data size is half word */
00421 #define MDMA_SRC_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_SSIZE_1)   /*!< Source data size is word */
00422 #define MDMA_SRC_DATASIZE_DOUBLEWORD  ((uint32_t)MDMA_CTCR_SSIZE)     /*!< Source data size is double word */
00423
00424 /**
00425   * @}
00426   */
00427
00428 /** @defgroup MDMA_Destination_data_size MDMA Destination data size
00429   * @brief    MDMA Destination data size
00430   * @{
00431   */
00432 #define MDMA_DEST_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Destination data size is Byte */
00433 #define MDMA_DEST_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_DSIZE_0)   /*!< Destination data size is half word */
00434 #define MDMA_DEST_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_DSIZE_1)   /*!< Destination data size is word */
00435 #define MDMA_DEST_DATASIZE_DOUBLEWORD  ((uint32_t)MDMA_CTCR_DSIZE)     /*!< Destination data size is double word */
00436
00437 /**
00438   * @}
00439   */
00440
00441 /** @defgroup MDMA_data_Alignment MDMA data alignment
00442   * @brief    MDMA MDMA data alignment
00443   * @{
00444   */
00445 #define MDMA_DATAALIGN_PACKENABLE        ((uint32_t)MDMA_CTCR_PKE)     /*!< The source data is packed/un-packed into the destination data size
00446                                                                             All data are right aligned, in Little Endien mode. */
00447 #define MDMA_DATAALIGN_RIGHT            ((uint32_t)0x00000000U)        /*!< Right Aligned, padded w/ 0s (default) */
00448 #define MDMA_DATAALIGN_RIGHT_SIGNED     ((uint32_t)MDMA_CTCR_PAM_0)    /*!< Right Aligned, Sign extended ,
00449                                                                             Note : this mode is allowed only if the Source data size smaller than Destination data size  */
00450 #define MDMA_DATAALIGN_LEFT             ((uint32_t)MDMA_CTCR_PAM_1)    /*!< Left Aligned (padded with 0s) */
00451
00452 /**
00453   * @}
00454   */
00455
00456 /** @defgroup MDMA_Source_burst MDMA Source burst
00457   * @brief    MDMA Source burst
00458   * @{
00459   */
00460 #define MDMA_SOURCE_BURST_SINGLE        ((uint32_t)0x00000000U)                                       /*!< single transfer */
00461 #define MDMA_SOURCE_BURST_2BEATS        ((uint32_t)MDMA_CTCR_SBURST_0)                                /*!< Burst 2 beats */
00462 #define MDMA_SOURCE_BURST_4BEATS        ((uint32_t)MDMA_CTCR_SBURST_1)                                /*!< Burst 4 beats */
00463 #define MDMA_SOURCE_BURST_8BEATS        ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats */
00464 #define MDMA_SOURCE_BURST_16BEATS       ((uint32_t)MDMA_CTCR_SBURST_2)                                /*!< Burst 16 beats */
00465 #define MDMA_SOURCE_BURST_32BEATS       ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats */
00466 #define MDMA_SOURCE_BURST_64BEATS       ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats */
00467 #define MDMA_SOURCE_BURST_128BEATS      ((uint32_t)MDMA_CTCR_SBURST)                                  /*!< Burst 128 beats */
00468
00469 /**
00470   * @}
00471   */
00472
00473 /** @defgroup MDMA_Destination_burst MDMA Destination burst
00474   * @brief    MDMA Destination burst
00475   * @{
00476   */
00477 #define MDMA_DEST_BURST_SINGLE        ((uint32_t)0x00000000U)                                        /*!< single transfer */
00478 #define MDMA_DEST_BURST_2BEATS        ((uint32_t)MDMA_CTCR_DBURST_0)                                 /*!< Burst 2 beats */
00479 #define MDMA_DEST_BURST_4BEATS        ((uint32_t)MDMA_CTCR_DBURST_1)                                 /*!< Burst 4 beats */
00480 #define MDMA_DEST_BURST_8BEATS        ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1)  /*!< Burst 8 beats */
00481 #define MDMA_DEST_BURST_16BEATS       ((uint32_t)MDMA_CTCR_DBURST_2)                                 /*!< Burst 16 beats */
00482 #define MDMA_DEST_BURST_32BEATS       ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 32 beats */
00483 #define MDMA_DEST_BURST_64BEATS       ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 64 beats */
00484 #define MDMA_DEST_BURST_128BEATS      ((uint32_t)MDMA_CTCR_DBURST)                                   /*!< Burst 128 beats */
00485
00486 /**
00487   * @}
00488   */
00489
00490 /** @defgroup MDMA_interrupt_enable_definitions MDMA interrupt enable definitions
00491   * @brief    MDMA interrupt enable definitions
00492   * @{
00493   */
00494 #define MDMA_IT_TE   ((uint32_t)MDMA_CCR_TEIE)   /*!< Transfer Error interrupt */
00495 #define MDMA_IT_CTC  ((uint32_t)MDMA_CCR_CTCIE)  /*!< Channel Transfer Complete interrupt */
00496 #define MDMA_IT_BRT  ((uint32_t)MDMA_CCR_BRTIE)  /*!< Block Repeat Transfer interrupt */
00497 #define MDMA_IT_BT   ((uint32_t)MDMA_CCR_BTIE)   /*!< Block Transfer interrupt */
00498 #define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE)   /*!< Buffer Transfer Complete interrupt */
00499
00500 /**
00501   * @}
00502   */
00503
00504 /** @defgroup MDMA_flag_definitions MDMA flag definitions
00505   * @brief    MDMA flag definitions
00506   * @{
00507   */
00508 #define MDMA_FLAG_TE    ((uint32_t)MDMA_CISR_TEIF)  /*!< Transfer Error flag    */
00509 #define MDMA_FLAG_CTC   ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag */
00510 #define MDMA_FLAG_BRT   ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */
00511 #define MDMA_FLAG_BT    ((uint32_t)MDMA_CISR_BTIF)  /*!< Block Transfer complete flag */
00512 #define MDMA_FLAG_BFTC  ((uint32_t)MDMA_CISR_TCIF)  /*!< BuFfer Transfer complete flag */
00513 #define MDMA_FLAG_CRQA  ((uint32_t)MDMA_CISR_CRQA)  /*!< Channel ReQest Active flag */
00514
00515 /**
00516   * @}
00517   */
00518
00519 /**
00520   * @}
00521   */
00522
00523 /* Exported macro ------------------------------------------------------------*/
00524
00525 /** @defgroup MDMA_Exported_Macros MDMA Exported Macros
00526   * @{
00527   */
00528
00529 /**
00530   * @brief  Enable the specified MDMA Channel.
00531   * @param  __HANDLE__: MDMA handle
00532   * @retval None
00533   */
00534 #define __HAL_MDMA_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CCR |=  MDMA_CCR_EN)
00535
00536 /**
00537   * @brief  Disable the specified DMA Channel.
00538   * @param  __HANDLE__: MDMA handle
00539   * @retval None
00540   */
00541 #define __HAL_MDMA_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CCR &=  ~MDMA_CCR_EN)
00542
00543 /**
00544   * @brief  Get the MDMA Channel pending flags.
00545   * @param  __HANDLE__: MDMA handle
00546   * @param  __FLAG__: Get the specified flag.
00547   *          This parameter can be any combination of the following values:
00548   *            @arg MDMA_FLAG_TE   : Transfer Error flag.
00549   *            @arg MDMA_FLAG_CTC  : Channel Transfer Complete flag.
00550   *            @arg MDMA_FLAG_BRT  : Block Repeat Transfer flag.
00551   *            @arg MDMA_FLAG_BT   : Block Transfer complete flag.
00552   *            @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
00553   *            @arg MDMA_FLAG_CRQA : Channel ReQest Active flag.
00554   * @retval The state of FLAG (SET or RESET).
00555   */
00556 #define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->CISR & (__FLAG__))
00557
00558 /**
00559   * @brief  Clear the MDMA Stream pending flags.
00560   * @param  __HANDLE__: MDMA handle
00561   * @param  __FLAG__: specifies the flag to clear.
00562   *          This parameter can be any combination of the following values:
00563   *            @arg MDMA_FLAG_TE   : Transfer Error flag.
00564   *            @arg MDMA_FLAG_CTC  : Channel Transfer Complete flag.
00565   *            @arg MDMA_FLAG_BRT  : Block Repeat Transfer flag.
00566   *            @arg MDMA_FLAG_BT   : Block Transfer complete flag.
00567   *            @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
00568   * @retval None
00569   */
00570 #define __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__))
00571
00572 /**
00573   * @brief  Enables the specified DMA Channel interrupts.
00574   * @param  __HANDLE__: MDMA handle
00575   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
00576   *          This parameter can be any combination of the following values:
00577   *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask
00578   *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask
00579   *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask
00580   *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask
00581   *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask
00582   * @retval None
00583   */
00584 #define __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
00585
00586 /**
00587   * @brief  Disables the specified MDMA Channel interrupts.
00588   * @param  __HANDLE__: MDMA handle
00589   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
00590   *          This parameter can be any combination of the following values:
00591   *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask
00592   *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask
00593   *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask
00594   *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask
00595   *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask
00596   * @retval None
00597   */
00598 #define __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
00599
00600 /**
00601   * @brief  Checks whether the specified MDMA Channel interrupt is enabled or not.
00602   * @param  __HANDLE__: DMA handle
00603   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
00604   *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask
00605   *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask
00606   *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask
00607   *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask
00608   *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask
00609   * @retval The state of MDMA_IT (SET or RESET).
00610   */
00611 #define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
00612
00613 /**
00614   * @}
00615   */
00616
00617 /* Exported functions --------------------------------------------------------*/
00618 /** @defgroup MDMA_Exported_Functions  MDMA Exported Functions
00619   * @{
00620   */
00621
00622 /* Initialization and de-initialization functions *****************************/
00623 /** @defgroup MDMA_Exported_Functions_Group1 Initialization and de-initialization functions
00624   * @brief   Initialization and de-initialization functions
00625   * @{
00626   */
00627 HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma);
00628 HAL_StatusTypeDef HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma);
00629 HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData);
00630
00631 HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma));
00632 HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID);
00633
00634 /**
00635   * @}
00636   */
00637
00638 /* Linked list operation functions ********************************************/
00639 /** @defgroup MDMA_Exported_Functions_Group2 Linked List operation functions
00640   * @brief   Linked list operation functions
00641   * @{
00642   */
00643
00644 HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig);
00645 HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode);
00646 HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode);
00647 HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma);
00648 HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma);
00649
00650
00651 /**
00652   * @}
00653   */
00654
00655 /* IO operation functions *****************************************************/
00656 /** @defgroup MDMA_Exported_Functions_Group3 I/O operation functions
00657   * @brief   I/O operation functions
00658   * @{
00659   */
00660 HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
00661 HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
00662 HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma);
00663 HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma);
00664 HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, uint32_t CompleteLevel, uint32_t Timeout);
00665 HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma);
00666 void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma);
00667
00668 /**
00669   * @}
00670   */
00671
00672 /* Peripheral State and Error functions ***************************************/
00673 /** @defgroup MDMA_Exported_Functions_Group4 Peripheral State functions
00674   * @brief    Peripheral State functions
00675   * @{
00676   */
00677 HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma);
00678 uint32_t              HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma);
00679
00680 /**
00681   * @}
00682   */
00683
00684 /**
00685   * @}
00686   */
00687
00688 /* Private types -------------------------------------------------------------*/
00689 /** @defgroup MDMA_Private_Types MDMA Private Types
00690   * @{
00691   */
00692
00693 /**
00694   * @}
00695   */
00696
00697 /* Private defines -----------------------------------------------------------*/
00698 /** @defgroup MDMA_Private_Defines MDMA Private Defines
00699   * @{
00700   */
00701
00702 /**
00703   * @}
00704   */
00705
00706 /* Private variables ---------------------------------------------------------*/
00707 /** @defgroup MDMA_Private_Variables MDMA Private Variables
00708   * @{
00709   */
00710
00711 /**
00712   * @}
00713   */
00714
00715 /* Private constants ---------------------------------------------------------*/
00716 /** @defgroup MDMA_Private_Constants MDMA Private Constants
00717   * @{
00718   */
00719
00720 /**
00721   * @}
00722   */
00723
00724 /* Private macros ------------------------------------------------------------*/
00725 /** @defgroup MDMA_Private_Macros MDMA Private Macros
00726   * @{
00727   */
00728
00729 #define IS_MDMA_LEVEL_COMPLETE(__LEVEL__) (((__LEVEL__) == HAL_MDMA_FULL_TRANSFER )  || \
00730                                            ((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| \
00731                                            ((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || \
00732                                            ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER ))
00733
00734
00735 #define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW )  || \
00736                                        ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \
00737                                        ((__PRIORITY__) == MDMA_PRIORITY_HIGH)   || \
00738                                        ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH))
00739
00740 #define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE )        || \
00741                                               ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE)     || \
00742                                               ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \
00743                                               ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE))
00744
00745
00746 #define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_END_DATA))
00747
00748 #define IS_MDMA_SOURCE_INC(__INC__) (((__INC__) == MDMA_SRC_INC_DISABLE )   || \
00749                                      ((__INC__) == MDMA_SRC_INC_BYTE )      || \
00750                                      ((__INC__) == MDMA_SRC_INC_HALFWORD )  || \
00751                                      ((__INC__) == MDMA_SRC_INC_WORD )      || \
00752                                      ((__INC__) == MDMA_SRC_INC_DOUBLEWORD) || \
00753                                      ((__INC__) == MDMA_SRC_DEC_BYTE)       || \
00754                                      ((__INC__) == MDMA_SRC_DEC_HALFWORD)   || \
00755                                      ((__INC__) == MDMA_SRC_DEC_WORD)       || \
00756                                      ((__INC__) == MDMA_SRC_DEC_DOUBLEWORD))
00757
00758 #define IS_MDMA_DESTINATION_INC(__INC__) (((__INC__) == MDMA_DEST_INC_DISABLE )   || \
00759                                           ((__INC__) == MDMA_DEST_INC_BYTE )      || \
00760                                           ((__INC__) == MDMA_DEST_INC_HALFWORD )  || \
00761                                           ((__INC__) == MDMA_DEST_INC_WORD )      || \
00762                                           ((__INC__) == MDMA_DEST_INC_DOUBLEWORD) || \
00763                                           ((__INC__) == MDMA_DEST_DEC_BYTE)       || \
00764                                           ((__INC__) == MDMA_DEST_DEC_HALFWORD)   || \
00765                                           ((__INC__) == MDMA_DEST_DEC_WORD)       || \
00766                                           ((__INC__) == MDMA_DEST_DEC_DOUBLEWORD))
00767
00768 #define IS_MDMA_SOURCE_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_SRC_DATASIZE_BYTE )     || \
00769                                            ((__SIZE__) == MDMA_SRC_DATASIZE_HALFWORD ) || \
00770                                            ((__SIZE__) == MDMA_SRC_DATASIZE_WORD )     || \
00771                                            ((__SIZE__) == MDMA_SRC_DATASIZE_DOUBLEWORD))
00772
00773 #define IS_MDMA_DESTINATION_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_DEST_DATASIZE_BYTE )     || \
00774                                                 ((__SIZE__) == MDMA_DEST_DATASIZE_HALFWORD ) || \
00775                                                 ((__SIZE__) == MDMA_DEST_DATASIZE_WORD )     || \
00776                                                 ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD))
00777
00778 #define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE )    || \
00779                                                  ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT )         || \
00780                                                  ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED )  || \
00781                                                  ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT))
00782
00783
00784 #define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \
00785                                          ((__BURST__) == MDMA_SOURCE_BURST_2BEATS ) || \
00786                                          ((__BURST__) == MDMA_SOURCE_BURST_4BEATS ) || \
00787                                          ((__BURST__) == MDMA_SOURCE_BURST_8BEATS)  || \
00788                                          ((__BURST__) == MDMA_SOURCE_BURST_16BEATS) || \
00789                                          ((__BURST__) == MDMA_SOURCE_BURST_32BEATS) || \
00790                                          ((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || \
00791                                          ((__BURST__) == MDMA_SOURCE_BURST_128BEATS))
00792
00793
00794 #define IS_MDMA_DESTINATION_BURST(__BURST__) (((__BURST__) == MDMA_DEST_BURST_SINGLE ) || \
00795                                               ((__BURST__) == MDMA_DEST_BURST_2BEATS ) || \
00796                                               ((__BURST__) == MDMA_DEST_BURST_4BEATS ) || \
00797                                               ((__BURST__) == MDMA_DEST_BURST_8BEATS)  || \
00798                                               ((__BURST__) == MDMA_DEST_BURST_16BEATS) || \
00799                                               ((__BURST__) == MDMA_DEST_BURST_32BEATS) || \
00800                                               ((__BURST__) == MDMA_DEST_BURST_64BEATS) || \
00801                                               ((__BURST__) == MDMA_DEST_BURST_128BEATS))
00802
00803  #define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER )      || \
00804                                          ((__MODE__) == MDMA_BLOCK_TRANSFER )        || \
00805                                          ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \
00806                                          ((__MODE__) == MDMA_FULL_TRANSFER))
00807
00808 #define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001) && ((__LENGTH__) < 0x000000FF))
00809
00810 #define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0 ) && ((__COUNT__) <= 4096))
00811
00812 #define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0) && ((SIZE) <= 65536))
00813
00814 #define IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536))
00815
00816 /**
00817   * @}
00818   */
00819
00820 /* Private functions prototypes ----------------------------------------------*/
00821 /** @defgroup MDMA_Private_Functions_Prototypes MDMA Private Functions Prototypes
00822   * @{
00823   */
00824
00825 /**
00826   * @}
00827   */
00828
00829 /* Private functions ---------------------------------------------------------*/
00830 /** @defgroup MDMA_Private_Functions MDMA Private Functions
00831   * @{
00832   */
00833
00834 /**
00835   * @}
00836   */
00837
00838 /**
00839   * @}
00840   */
00841
00842 /**
00843   * @}
00844   */
00845
00846 #ifdef __cplusplus
00847 }
00848 #endif
00849
00850 #endif /* __STM32H7xx_HAL_MDMA_H */
00851
00852 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_mmc.c Source File

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stm32h7xx_hal_mmc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_mmc.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   MMC card HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Secure Digital (MMC) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + MMC card Control functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019   [..]
00020     This driver implements a high level communication layer for read and write from/to
00021     this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
00022     the user in HAL_MMC_MspInit() function (MSP layer).
00023     Basically, the MSP layer configuration should be the same as we provide in the
00024     examples.
00025     You can easily tailor this configuration according to hardware resources.
00026
00027   [..]
00028     This driver is a generic layered driver for SDMMC memories which uses the HAL
00029     SDMMC driver functions to interface with MMC and eMMC cards devices.
00030     It is used as follows:
00031
00032     (#)Initialize the SDMMC low level resources by implement the HAL_MMC_MspInit() API:
00033         (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
00034         (##) SDMMC pins configuration for MMC card
00035             (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
00036             (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
00037                   and according to your pin assignment;
00038         (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
00039             (+++) Configure the SDMMC interrupt priorities using functions HAL_NVIC_SetPriority();
00040             (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
00041             (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
00042                   and __HAL_MMC_DISABLE_IT() inside the communication process.
00043             (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT()
00044                   and __HAL_MMC_CLEAR_IT()
00045         (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC IP are used.
00046
00047     (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization
00048
00049
00050   *** MMC Card Initialization and configuration ***
00051   ================================================
00052   [..]
00053     To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes
00054     SDMMC IP (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer).
00055     This function provide the following operations:
00056
00057     (#) Initialize the SDMMC peripheral interface with defaullt configuration.
00058         The initialization process is done at 400KHz. You can change or adapt
00059         this frequency by adjusting the "ClockDiv" field.
00060         The MMC Card frequency (SDMMC_CK) is computed as follows:
00061
00062            SDMMC_CK = SDMMCCLK / (2 * ClockDiv)
00063
00064         In initialization mode and according to the MMC Card standard,
00065         make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
00066
00067         This phase of initialization is done through SDMMC_Init() and
00068         SDMMC_PowerState_ON() SDMMC low level APIs.
00069
00070     (#) Initialize the MMC card. The API used is HAL_MMC_InitCard().
00071         This phase allows the card initialization and identification
00072         and check the MMC Card type (Standard Capacity or High Capacity)
00073         The initialization flow is compatible with MMC standard.
00074
00075         This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case
00076         of plug-off plug-in.
00077
00078     (#) Configure the MMC Card Data transfer frequency. By Default, the card transfer
00079         frequency by adjusting the "ClockDiv" field.
00080         In transfer mode and according to the MMC Card standard, make sure that the
00081         SDMMC_CK frequency doesn't exceed 25MHz and 100MHz in High-speed mode switch.
00082
00083     (#) Select the corresponding MMC Card according to the address read with the step 2.
00084
00085     (#) Configure the MMC Card in wide bus mode: 4-bits data.
00086
00087   *** MMC Card Read operation ***
00088   ==============================
00089   [..]
00090     (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks().
00091         This function support only 512-bytes block length (the block size should be
00092         chosen as 512 bytes).
00093         You can choose either one block read operation or multiple block read operation
00094         by adjusting the "NumberOfBlocks" parameter.
00095         After this, you have to ensure that the transfer is done correctly. The check is done
00096         through HAL_MMC_GetCardState() function for MMC card state.
00097
00098     (+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA().
00099         This function support only 512-bytes block length (the block size should be
00100         chosen as 512 bytes).
00101         You can choose either one block read operation or multiple block read operation
00102         by adjusting the "NumberOfBlocks" parameter.
00103
00104   *** MMC Card Write operation ***
00105   ===============================
00106   [..]
00107     (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks().
00108         This function support only 512-bytes block length (the block size should be
00109         chosen as 512 bytes).
00110         You can choose either one block read operation or multiple block read operation
00111         by adjusting the "NumberOfBlocks" parameter.
00112
00113     (+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA().
00114         This function support only 512-bytes block length (the block size should be
00115         chosen as 512 byte).
00116         You can choose either one block read operation or multiple block read operation
00117         by adjusting the "NumberOfBlocks" parameter.
00118
00119   *** MMC card CID register ***
00120   ============================
00121   [..]
00122     (+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register.
00123         Some of the CID parameters are useful for card initialization and identification.
00124
00125   *** MMC HAL driver macros list ***
00126   ==================================
00127   [..]
00128     Below the list of most used macros in MMC HAL driver.
00129
00130     (+) __HAL_MMC_ENABLE_IT: Enable the MMC device interrupt
00131     (+) __HAL_MMC_DISABLE_IT: Disable the MMC device interrupt
00132     (+) __HAL_MMC_GET_FLAG:Check whether the specified MMC flag is set or not
00133     (+) __HAL_MMC_CLEAR_FLAG: Clear the MMC's pending flags
00134
00135   [..]
00136     (@) You can refer to the MMC HAL driver header file for more useful macros
00137
00138   @endverbatim
00139   ******************************************************************************
00140   * @attention
00141   *
00142   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00143   *
00144   * Redistribution and use in source and binary forms, with or without modification,
00145   * are permitted provided that the following conditions are met:
00146   *   1. Redistributions of source code must retain the above copyright notice,
00147   *      this list of conditions and the following disclaimer.
00148   *   2. Redistributions in binary form must reproduce the above copyright notice,
00149   *      this list of conditions and the following disclaimer in the documentation
00150   *      and/or other materials provided with the distribution.
00151   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00152   *      may be used to endorse or promote products derived from this software
00153   *      without specific prior written permission.
00154   *
00155   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00156   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00157   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00158   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00159   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00160   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00161   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00162   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00163   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00164   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00165   *
00166   ******************************************************************************
00167   */
00168
00169 /* Includes ------------------------------------------------------------------*/
00170 #include "stm32h7xx_hal.h"
00171
00172 /** @addtogroup STM32H7xx_HAL_Driver
00173   * @{
00174   */
00175
00176 /** @defgroup MMC MMC
00177   * @brief MMC HAL module driver
00178   * @{
00179   */
00180
00181 #ifdef HAL_MMC_MODULE_ENABLED
00182
00183 /* Private typedef -----------------------------------------------------------*/
00184 /* Private define ------------------------------------------------------------*/
00185 /** @addtogroup MMC_Private_Defines
00186   * @{
00187   */
00188
00189 /**
00190   * @}
00191   */
00192
00193 /* Private macro -------------------------------------------------------------*/
00194 /* Private variables ---------------------------------------------------------*/
00195 /* Private function prototypes -----------------------------------------------*/
00196 /* Private functions ---------------------------------------------------------*/
00197 /** @defgroup MMC_Private_Functions MMC Private Functions
00198   * @{
00199   */
00200 static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc);
00201 static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc);
00202 static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus);
00203 static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc);
00204 static HAL_StatusTypeDef MMC_Write_IT(MMC_HandleTypeDef *hmmc);
00205 static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc);
00206 static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pBlockNbr, uint32_t Timeout);
00207
00208
00209 /**
00210   * @}
00211   */
00212 /* Exported functions --------------------------------------------------------*/
00213 /** @addtogroup MMC_Exported_Functions
00214   * @{
00215   */
00216
00217 /** @addtogroup MMC_Exported_Functions_Group1
00218  *  @brief   Initialization and de-initialization functions
00219  *
00220 @verbatim
00221   ==============================================================================
00222           ##### Initialization and de-initialization functions #####
00223   ==============================================================================
00224   [..]
00225     This section provides functions allowing to initialize/de-initialize the MMC
00226     card device to be ready for use.
00227
00228 @endverbatim
00229   * @{
00230   */
00231
00232 /**
00233   * @brief  Initializes the MMC according to the specified parameters in the
00234             MMC_HandleTypeDef and create the associated handle.
00235   * @param  hmmc: Pointer to the MMC handle
00236   * @retval HAL status
00237   */
00238 HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc)
00239 {
00240   /* Check the MMC handle allocation */
00241   if(hmmc == NULL)
00242   {
00243     return HAL_ERROR;
00244   }
00245
00246   /* Check the parameters */
00247   assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance));
00248   assert_param(IS_SDMMC_CLOCK_EDGE(hmmc->Init.ClockEdge));
00249   assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hmmc->Init.ClockPowerSave));
00250   assert_param(IS_SDMMC_BUS_WIDE(hmmc->Init.BusWide));
00251   assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hmmc->Init.HardwareFlowControl));
00252   assert_param(IS_SDMMC_CLKDIV(hmmc->Init.ClockDiv));
00253
00254   if(hmmc->State == HAL_MMC_STATE_RESET)
00255   {
00256     /* Allocate lock resource and initialize it */
00257     hmmc->Lock = HAL_UNLOCKED;
00258     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00259     HAL_MMC_MspInit(hmmc);
00260   }
00261
00262   hmmc->State = HAL_MMC_STATE_BUSY;
00263
00264   /* Initialize the Card parameters */
00265   if(HAL_MMC_InitCard(hmmc) == HAL_ERROR)
00266   {
00267     return HAL_ERROR;
00268   }
00269
00270   /* Initialize the error code */
00271   hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
00272
00273   /* Initialize the MMC operation */
00274   hmmc->Context = MMC_CONTEXT_NONE;
00275
00276   /* Initialize the MMC state */
00277   hmmc->State = HAL_MMC_STATE_READY;
00278
00279   return HAL_OK;
00280 }
00281
00282 /**
00283   * @brief  Initializes the MMC Card.
00284   * @param  hmmc: Pointer to MMC handle
00285   * @note   This function initializes the MMC card. It could be used when a card
00286             re-initialization is needed.
00287   * @retval HAL status
00288   */
00289 HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
00290 {
00291   uint32_t errorstate = HAL_MMC_ERROR_NONE;
00292   MMC_InitTypeDef Init;
00293   HAL_StatusTypeDef status;
00294
00295   /* Default SDMMC peripheral configuration for MMC card initialization */
00296   Init.ClockEdge           = SDMMC_CLOCK_EDGE_RISING;
00297   Init.ClockPowerSave      = SDMMC_CLOCK_POWER_SAVE_DISABLE;
00298   Init.BusWide             = SDMMC_BUS_WIDE_1B;
00299   Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
00300   Init.ClockDiv            = SDMMC_INIT_CLK_DIV;
00301
00302   /* Initialize SDMMC peripheral interface with default configuration */
00303   status = SDMMC_Init(hmmc->Instance, Init);
00304   if(status == HAL_ERROR)
00305   {
00306     return HAL_ERROR;
00307   }
00308
00309   /* Set Power State to ON */
00310   status = SDMMC_PowerState_ON(hmmc->Instance);
00311   if(status == HAL_ERROR)
00312   {
00313     return HAL_ERROR;
00314   }
00315
00316   /* Identify card operating voltage */
00317   errorstate = MMC_PowerON(hmmc);
00318   if(errorstate != HAL_MMC_ERROR_NONE)
00319   {
00320     hmmc->State = HAL_MMC_STATE_READY;
00321     hmmc->ErrorCode |= errorstate;
00322     return HAL_ERROR;
00323   }
00324
00325   /* Card initialization */
00326   errorstate = MMC_InitCard(hmmc);
00327   if(errorstate != HAL_MMC_ERROR_NONE)
00328   {
00329     hmmc->State = HAL_MMC_STATE_READY;
00330     hmmc->ErrorCode |= errorstate;
00331     return HAL_ERROR;
00332   }
00333
00334   return HAL_OK;
00335 }
00336
00337 /**
00338   * @brief  De-Initializes the MMC card.
00339   * @param  hmmc: Pointer to MMC handle
00340   * @retval HAL status
00341   */
00342 HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
00343 {
00344   /* Check the MMC handle allocation */
00345   if(hmmc == NULL)
00346   {
00347     return HAL_ERROR;
00348   }
00349
00350   /* Check the parameters */
00351   assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance));
00352
00353   hmmc->State = HAL_MMC_STATE_BUSY;
00354
00355   /* Set MMC power state to off */
00356   MMC_PowerOFF(hmmc);
00357
00358   /* De-Initialize the MSP layer */
00359   HAL_MMC_MspDeInit(hmmc);
00360
00361   hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
00362   hmmc->State = HAL_MMC_STATE_RESET;
00363
00364   return HAL_OK;
00365 }
00366
00367
00368 /**
00369   * @brief  Initializes the MMC MSP.
00370   * @param  hmmc: Pointer to MMC handle
00371   * @retval None
00372   */
00373 __weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc)
00374 {
00375   /* Prevent unused argument(s) compilation warning */
00376   UNUSED(hmmc);
00377
00378   /* NOTE : This function Should not be modified, when the callback is needed,
00379             the HAL_MMC_MspInit could be implemented in the user file
00380    */
00381 }
00382
00383 /**
00384   * @brief  De-Initialize MMC MSP.
00385   * @param  hmmc: Pointer to MMC handle
00386   * @retval None
00387   */
00388 __weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc)
00389 {
00390   /* Prevent unused argument(s) compilation warning */
00391   UNUSED(hmmc);
00392
00393   /* NOTE : This function Should not be modified, when the callback is needed,
00394             the HAL_MMC_MspDeInit could be implemented in the user file
00395    */
00396 }
00397
00398 /**
00399   * @}
00400   */
00401
00402 /** @addtogroup MMC_Exported_Functions_Group2
00403  *  @brief   Data transfer functions
00404  *
00405 @verbatim
00406   ==============================================================================
00407                         ##### IO operation functions #####
00408   ==============================================================================
00409   [..]
00410     This subsection provides a set of functions allowing to manage the data
00411     transfer from/to MMC card.
00412
00413 @endverbatim
00414   * @{
00415   */
00416
00417 /**
00418   * @brief  Reads block(s) from a specified address in a card. The Data transfer
00419   *         is managed by polling mode.
00420   * @note   This API should be followed by a check on the card state through
00421   *         HAL_MMC_GetCardState().
00422   * @param  hmmc: Pointer to MMC handle
00423   * @param  pData: pointer to the buffer that will contain the received data
00424   * @param  BlockAdd: Block Address from where data is to be read
00425   * @param  NumberOfBlocks: Number of MMC blocks to read
00426   * @param  Timeout: Specify timeout value
00427   * @retval HAL status
00428   */
00429 HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
00430 {
00431   SDMMC_DataInitTypeDef config;
00432   uint32_t errorstate = HAL_MMC_ERROR_NONE;
00433   uint32_t tickstart = HAL_GetTick();
00434   uint32_t count = 0, *tempbuff = (uint32_t *)pData;
00435
00436   if(NULL == pData)
00437   {
00438     hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
00439     return HAL_ERROR;
00440   }
00441
00442   if(hmmc->State == HAL_MMC_STATE_READY)
00443   {
00444     hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
00445
00446     if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
00447     {
00448       hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
00449       return HAL_ERROR;
00450     }
00451
00452     hmmc->State = HAL_MMC_STATE_BUSY;
00453
00454     /* Initialize data control register */
00455     hmmc->Instance->DCTRL = 0;
00456
00457     if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
00458     {
00459       BlockAdd *= 512;
00460     }
00461
00462     /* Set Block Size for Card */
00463     errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
00464     if(errorstate != HAL_MMC_ERROR_NONE)
00465     {
00466       /* Clear all the static flags */
00467       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00468       hmmc->ErrorCode |= errorstate;
00469       hmmc->State = HAL_MMC_STATE_READY;
00470       return HAL_ERROR;
00471     }
00472
00473     /* Configure the MMC DPSM (Data Path State Machine) */
00474     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00475     config.DataLength    = NumberOfBlocks * BLOCKSIZE;
00476     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00477     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
00478     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00479     config.DPSM          = SDMMC_DPSM_ENABLE;
00480     SDMMC_ConfigData(hmmc->Instance, &config);
00481
00482     /* Read block(s) in polling mode */
00483     if(NumberOfBlocks > 1)
00484     {
00485       hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
00486
00487       /* Read Multi Block command */
00488       errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd);
00489     }
00490     else
00491     {
00492       hmmc->Context = MMC_CONTEXT_READ_SINGLE_BLOCK;
00493
00494       /* Read Single Block command */
00495       errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd);
00496     }
00497     if(errorstate != HAL_MMC_ERROR_NONE)
00498     {
00499       /* Clear all the static flags */
00500       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00501       hmmc->ErrorCode |= errorstate;
00502       hmmc->State = HAL_MMC_STATE_READY;
00503       return HAL_ERROR;
00504     }
00505
00506     /* Poll on SDMMC flags */
00507     while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
00508     {
00509       if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
00510       {
00511         /* Read data from SDMMC Rx FIFO */
00512         for(count = 0U; count < 8U; count++)
00513         {
00514           *(tempbuff + count) = SDMMC_ReadFIFO(hmmc->Instance);
00515         }
00516         tempbuff += 8U;
00517       }
00518
00519       if((Timeout == 0U)||((HAL_GetTick()-tickstart) >=  Timeout))
00520       {
00521         /* Clear all the static flags */
00522         __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00523         hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
00524         hmmc->State= HAL_MMC_STATE_READY;
00525         return HAL_TIMEOUT;
00526       }
00527     }
00528
00529     /* Send stop transmission command in case of multiblock read */
00530     if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
00531     {
00532       /* Send stop transmission command */
00533       errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
00534       if(errorstate != HAL_MMC_ERROR_NONE)
00535       {
00536           /* Clear all the static flags */
00537         __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00538         hmmc->ErrorCode |= errorstate;
00539         hmmc->State = HAL_MMC_STATE_READY;
00540         return HAL_ERROR;
00541       }
00542     }
00543
00544     /* Get error state */
00545     if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
00546     {
00547       /* Clear all the static flags */
00548       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00549       hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
00550       hmmc->State = HAL_MMC_STATE_READY;
00551       return HAL_ERROR;
00552     }
00553     else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
00554     {
00555       /* Clear all the static flags */
00556       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00557       hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
00558       hmmc->State = HAL_MMC_STATE_READY;
00559       return HAL_ERROR;
00560     }
00561     else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
00562     {
00563       /* Clear all the static flags */
00564       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00565       hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
00566       hmmc->State = HAL_MMC_STATE_READY;
00567       return HAL_ERROR;
00568     }
00569
00570     /* Clear all the static flags */
00571     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00572
00573     hmmc->State = HAL_MMC_STATE_READY;
00574
00575     return HAL_OK;
00576   }
00577   else
00578   {
00579     hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
00580     return HAL_ERROR;
00581   }
00582 }
00583
00584 /**
00585   * @brief  Allows to write block(s) to a specified address in a card. The Data
00586   *         transfer is managed by polling mode.
00587   * @note   This API should be followed by a check on the card state through
00588   *         HAL_MMC_GetCardState().
00589   * @param  hmmc: Pointer to MMC handle
00590   * @param  pData: pointer to the buffer that will contain the data to transmit
00591   * @param  BlockAdd: Block Address where data will be written
00592   * @param  NumberOfBlocks: Number of MMC blocks to write
00593   * @param  Timeout: Specify timeout value
00594   * @retval HAL status
00595   */
00596 HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
00597 {
00598   SDMMC_DataInitTypeDef config;
00599   uint32_t errorstate = HAL_MMC_ERROR_NONE;
00600   uint32_t tickstart = HAL_GetTick();
00601   uint32_t count = 0;
00602   uint32_t *tempbuff = (uint32_t *)pData;
00603
00604   if(NULL == pData)
00605   {
00606     hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
00607     return HAL_ERROR;
00608   }
00609
00610   if(hmmc->State == HAL_MMC_STATE_READY)
00611   {
00612     hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
00613
00614     if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
00615     {
00616       hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
00617       return HAL_ERROR;
00618     }
00619
00620     hmmc->State = HAL_MMC_STATE_BUSY;
00621
00622     /* Initialize data control register */
00623     hmmc->Instance->DCTRL = 0;
00624
00625     if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
00626     {
00627       BlockAdd *= 512;
00628     }
00629
00630     /* Set Block Size for Card */
00631     errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
00632     if(errorstate != HAL_MMC_ERROR_NONE)
00633     {
00634       /* Clear all the static flags */
00635       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00636       hmmc->ErrorCode |= errorstate;
00637       hmmc->State = HAL_MMC_STATE_READY;
00638       return HAL_ERROR;
00639     }
00640
00641     /* Write Blocks in Polling mode */
00642     if(NumberOfBlocks > 1U)
00643     {
00644       hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
00645
00646       /* Write Multi Block command */
00647       errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd);
00648     }
00649     else
00650     {
00651       hmmc->Context = MMC_CONTEXT_WRITE_SINGLE_BLOCK;
00652
00653       /* Write Single Block command */
00654       errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd);
00655     }
00656     if(errorstate != HAL_MMC_ERROR_NONE)
00657     {
00658       /* Clear all the static flags */
00659       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00660       hmmc->ErrorCode |= errorstate;
00661       hmmc->State = HAL_MMC_STATE_READY;
00662       return HAL_ERROR;
00663     }
00664
00665     /* Configure the MMC DPSM (Data Path State Machine) */
00666     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00667     config.DataLength    = NumberOfBlocks * BLOCKSIZE;
00668     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00669     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
00670     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00671     config.DPSM          = SDMMC_DPSM_ENABLE;
00672     SDMMC_ConfigData(hmmc->Instance, &config);
00673
00674     /* Write block(s) in polling mode */
00675     while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
00676     {
00677       if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE))
00678       {
00679           /* Write data to SDMMC Tx FIFO */
00680         for(count = 0U; count < 8U; count++)
00681         {
00682           SDMMC_WriteFIFO(hmmc->Instance, (tempbuff + count));
00683         }
00684         tempbuff += 8U;
00685       }
00686
00687       if((Timeout == 0U)||((HAL_GetTick()-tickstart) >=  Timeout))
00688       {
00689         /* Clear all the static flags */
00690         __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00691         hmmc->ErrorCode |= errorstate;
00692         hmmc->State = HAL_MMC_STATE_READY;
00693         return HAL_TIMEOUT;
00694       }
00695     }
00696
00697     /* Send stop transmission command in case of multiblock write */
00698     if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
00699     {
00700         /* Send stop transmission command */
00701       errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
00702       if(errorstate != HAL_MMC_ERROR_NONE)
00703       {
00704         /* Clear all the static flags */
00705         __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00706         hmmc->ErrorCode |= errorstate;
00707         hmmc->State = HAL_MMC_STATE_READY;
00708         return HAL_ERROR;
00709       }
00710     }
00711
00712     /* Get error state */
00713     if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
00714     {
00715       /* Clear all the static flags */
00716       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00717       hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
00718       hmmc->State = HAL_MMC_STATE_READY;
00719       return HAL_ERROR;
00720     }
00721     else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
00722     {
00723       /* Clear all the static flags */
00724       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00725       hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
00726       hmmc->State = HAL_MMC_STATE_READY;
00727       return HAL_ERROR;
00728     }
00729     else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR))
00730     {
00731       /* Clear all the static flags */
00732       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00733       hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
00734       hmmc->State = HAL_MMC_STATE_READY;
00735       return HAL_ERROR;
00736     }
00737
00738     /* Clear all the static flags */
00739     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00740
00741     hmmc->State = HAL_MMC_STATE_READY;
00742
00743     return HAL_OK;
00744   }
00745   else
00746   {
00747     hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
00748     return HAL_ERROR;
00749   }
00750 }
00751
00752
00753 /**
00754   * @brief  Reads block(s) from a specified address in a card. The Data transfer
00755   *         is managed in interrupt mode.
00756   * @note   This API should be followed by a check on the card state through
00757   *         HAL_MMC_GetCardState().
00758   * @note   You could also check the IT transfer process through the MMC Rx
00759   *         interrupt event.
00760   * @param  hmmc: Pointer to MMC handle
00761   * @param  pData: Pointer to the buffer that will contain the received data
00762   * @param  BlockAdd: Block Address from where data is to be read
00763   * @param  NumberOfBlocks: Number of blocks to read.
00764   * @retval HAL status
00765   */
00766 HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
00767 {
00768   SDMMC_DataInitTypeDef config;
00769   uint32_t errorstate = HAL_MMC_ERROR_NONE;
00770
00771   if(NULL == pData)
00772   {
00773     hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
00774     return HAL_ERROR;
00775   }
00776
00777   if(hmmc->State == HAL_MMC_STATE_READY)
00778   {
00779     hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
00780
00781     if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
00782     {
00783       hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
00784       return HAL_ERROR;
00785     }
00786
00787     hmmc->State = HAL_MMC_STATE_BUSY;
00788
00789     /* Initialize data control register */
00790     hmmc->Instance->DCTRL = 0U;
00791
00792     hmmc->pRxBuffPtr = (uint32_t *)pData;
00793     hmmc->RxXferSize = BLOCKSIZE * NumberOfBlocks;
00794
00795     if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
00796     {
00797       BlockAdd *= 512U;
00798     }
00799
00800     /* Configure the MMC DPSM (Data Path State Machine) */
00801     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00802     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
00803     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00804     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
00805     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00806     config.DPSM          = SDMMC_DPSM_ENABLE;
00807     SDMMC_ConfigData(hmmc->Instance, &config);
00808
00809    /* Set Block Size for Card */
00810     errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
00811     if(errorstate != HAL_MMC_ERROR_NONE)
00812     {
00813      /* Clear all the static flags */
00814      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00815      hmmc->ErrorCode |= errorstate;
00816      hmmc->State = HAL_MMC_STATE_READY;
00817      return HAL_ERROR;
00818    }
00819
00820     /* Read Blocks in IT mode */
00821    if(NumberOfBlocks > 1U)
00822    {
00823     hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT);
00824
00825       /* Read Multi Block command */
00826     errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd);
00827   }
00828   else
00829   {
00830     hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_IT);
00831
00832     /* Read Single Block command */
00833     errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd);
00834   }
00835
00836   if(errorstate != HAL_MMC_ERROR_NONE)
00837   {
00838     /* Clear all the static flags */
00839     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00840     hmmc->ErrorCode |= errorstate;
00841     hmmc->State = HAL_MMC_STATE_READY;
00842     return HAL_ERROR;
00843   }
00844
00845
00846   __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF));
00847
00848   return HAL_OK;
00849 }
00850 else
00851 {
00852   return HAL_BUSY;
00853 }
00854 }
00855
00856 /**
00857   * @brief  Writes block(s) to a specified address in a card. The Data transfer
00858   *         is managed in interrupt mode.
00859   * @note   This API should be followed by a check on the card state through
00860   *         HAL_MMC_GetCardState().
00861   * @note   You could also check the IT transfer process through the MMC Tx
00862   *         interrupt event.
00863   * @param  hmmc: Pointer to MMC handle
00864   * @param  pData: Pointer to the buffer that will contain the data to transmit
00865   * @param  BlockAdd: Block Address where data will be written
00866   * @param  NumberOfBlocks: Number of blocks to write
00867   * @retval HAL status
00868   */
00869 HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
00870 {
00871   SDMMC_DataInitTypeDef config;
00872   uint32_t errorstate = HAL_MMC_ERROR_NONE;
00873
00874   if(NULL == pData)
00875   {
00876     hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
00877     return HAL_ERROR;
00878   }
00879
00880   if(hmmc->State == HAL_MMC_STATE_READY)
00881   {
00882     hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
00883
00884     if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
00885     {
00886       hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
00887       return HAL_ERROR;
00888     }
00889
00890     hmmc->State = HAL_MMC_STATE_BUSY;
00891
00892     /* Initialize data control register */
00893     hmmc->Instance->DCTRL = 0U;
00894
00895     hmmc->pTxBuffPtr = (uint32_t *)pData;
00896     hmmc->TxXferSize = BLOCKSIZE * NumberOfBlocks;
00897
00898     /* Enable transfer interrupts */
00899     __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE));
00900
00901     if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
00902     {
00903       BlockAdd *= 512U;
00904     }
00905
00906     /* Set Block Size for Card */
00907     errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
00908     if(errorstate != HAL_MMC_ERROR_NONE)
00909     {
00910       /* Clear all the static flags */
00911       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00912       hmmc->ErrorCode |= errorstate;
00913       hmmc->State = HAL_MMC_STATE_READY;
00914       return HAL_ERROR;
00915     }
00916
00917     /* Write Blocks in Polling mode */
00918     if(NumberOfBlocks > 1U)
00919     {
00920       hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK| MMC_CONTEXT_IT);
00921
00922       /* Write Multi Block command */
00923       errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd);
00924     }
00925     else
00926     {
00927       hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_IT);
00928
00929       /* Write Single Block command */
00930       errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd);
00931     }
00932     if(errorstate != HAL_MMC_ERROR_NONE)
00933     {
00934       /* Clear all the static flags */
00935       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
00936       hmmc->ErrorCode |= errorstate;
00937       hmmc->State = HAL_MMC_STATE_READY;
00938       return HAL_ERROR;
00939     }
00940
00941     /* Configure the MMC DPSM (Data Path State Machine) */
00942     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00943     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
00944     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00945     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
00946     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00947     config.DPSM          = SDMMC_DPSM_ENABLE;
00948     SDMMC_ConfigData(hmmc->Instance, &config);
00949
00950     return HAL_OK;
00951   }
00952   else
00953   {
00954     return HAL_BUSY;
00955   }
00956 }
00957
00958 /**
00959   * @brief  Reads block(s) from a specified address in a card. The Data transfer
00960   *         is managed by DMA mode.
00961   * @note   This API should be followed by a check on the card state through
00962   *         HAL_MMC_GetCardState().
00963   * @note   You could also check the DMA transfer process through the MMC Rx
00964   *         interrupt event.
00965   * @param  hmmc: Pointer MMC handle
00966   * @param  pData: Pointer to the buffer that will contain the received data
00967   * @param  BlockAdd: Block Address from where data is to be read
00968   * @param  NumberOfBlocks: Number of blocks to read.
00969   * @retval HAL status
00970   */
00971 HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
00972 {
00973   SDMMC_DataInitTypeDef config;
00974   uint32_t errorstate = HAL_MMC_ERROR_NONE;
00975
00976   if(NULL == pData)
00977   {
00978     hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
00979     return HAL_ERROR;
00980   }
00981
00982   if(hmmc->State == HAL_MMC_STATE_READY)
00983   {
00984     hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
00985
00986     if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
00987     {
00988       hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
00989       return HAL_ERROR;
00990     }
00991
00992     hmmc->State = HAL_MMC_STATE_BUSY;
00993
00994     /* Initialize data control register */
00995     hmmc->Instance->DCTRL = 0U;
00996
00997     hmmc->pRxBuffPtr = (uint32_t*)pData;
00998     hmmc->RxXferSize = BLOCKSIZE * NumberOfBlocks;
00999
01000     hmmc->State = HAL_MMC_STATE_BUSY;
01001
01002     if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
01003     {
01004       BlockAdd *= 512U;
01005     }
01006
01007     /* Configure the MMC DPSM (Data Path State Machine) */
01008     config.DataTimeOut   = SDMMC_DATATIMEOUT;
01009     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
01010     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
01011     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
01012     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
01013     config.DPSM          = SDMMC_DPSM_DISABLE;
01014     SDMMC_ConfigData(hmmc->Instance, &config);
01015
01016     /* Set Block Size for Card */
01017     errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
01018     if(errorstate != HAL_MMC_ERROR_NONE)
01019     {
01020       /* Clear all the static flags */
01021       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01022       hmmc->ErrorCode = errorstate;
01023       hmmc->State = HAL_MMC_STATE_READY;
01024       return HAL_ERROR;
01025     }
01026
01027     /* Enable transfer interrupts */
01028     __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
01029
01030     __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
01031     hmmc->Instance->IDMACTRL  = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
01032     hmmc->Instance->IDMABASE0 = (uint32_t) pData ;
01033
01034     /* Read Blocks in DMA mode */
01035     if(NumberOfBlocks > 1U)
01036     {
01037       hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
01038
01039       /* Read Multi Block command */
01040       errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd);
01041     }
01042     else
01043     {
01044       hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA);
01045
01046       /* Read Single Block command */
01047       errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd);
01048     }
01049     if(errorstate != HAL_MMC_ERROR_NONE)
01050     {
01051       /* Clear all the static flags */
01052       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01053       __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
01054       hmmc->ErrorCode = errorstate;
01055       hmmc->State = HAL_MMC_STATE_READY;
01056       return HAL_ERROR;
01057     }
01058
01059     return HAL_OK;
01060   }
01061   else
01062   {
01063     return HAL_BUSY;
01064   }
01065 }
01066
01067 /**
01068   * @brief  Writes block(s) to a specified address in a card. The Data transfer
01069   *         is managed by DMA mode.
01070   * @note   This API should be followed by a check on the card state through
01071   *         HAL_MMC_GetCardState().
01072   * @note   You could also check the DMA transfer process through the MMC Tx
01073   *         interrupt event.
01074   * @param  hmmc: Pointer to MMC handle
01075   * @param  pData: pointer to the buffer that will contain the data to transmit
01076   * @param  BlockAdd: Block Address where data will be written
01077   * @param  NumberOfBlocks: Number of blocks to write
01078   * @retval HAL status
01079   */
01080 HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
01081 {
01082   SDMMC_DataInitTypeDef config;
01083   uint32_t errorstate = HAL_MMC_ERROR_NONE;
01084
01085   if(NULL == pData)
01086   {
01087     hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
01088     return HAL_ERROR;
01089   }
01090
01091   if(hmmc->State == HAL_MMC_STATE_READY)
01092   {
01093     hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
01094
01095     if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
01096     {
01097       hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
01098       return HAL_ERROR;
01099     }
01100
01101     hmmc->State = HAL_MMC_STATE_BUSY;
01102
01103     /* Initialize data control register */
01104     hmmc->Instance->DCTRL = 0U;
01105
01106     hmmc->pTxBuffPtr = (uint32_t*)pData;
01107     hmmc->TxXferSize = BLOCKSIZE * NumberOfBlocks;
01108
01109     if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
01110     {
01111       BlockAdd *= 512U;
01112     }
01113
01114     /* Set Block Size for Card */
01115     errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
01116     if(errorstate != HAL_MMC_ERROR_NONE)
01117     {
01118       /* Clear all the static flags */
01119       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01120       hmmc->ErrorCode |= errorstate;
01121       hmmc->State = HAL_MMC_STATE_READY;
01122       return HAL_ERROR;
01123     }
01124     /* Configure the MMC DPSM (Data Path State Machine) */
01125     config.DataTimeOut   = SDMMC_DATATIMEOUT;
01126     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
01127     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
01128     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
01129     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
01130     config.DPSM          = SDMMC_DPSM_DISABLE;
01131     SDMMC_ConfigData(hmmc->Instance, &config);
01132
01133     /* Enable transfer interrupts */
01134     __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
01135
01136     __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
01137
01138     hmmc->Instance->IDMACTRL  = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
01139     hmmc->Instance->IDMABASE0 = (uint32_t) pData ;
01140
01141     /* Write Blocks in Polling mode */
01142     if(NumberOfBlocks > 1U)
01143     {
01144       hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
01145
01146       /* Write Multi Block command */
01147       errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd);
01148     }
01149     else
01150     {
01151       hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_DMA);
01152
01153       /* Write Single Block command */
01154       errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd);
01155     }
01156     if(errorstate != HAL_MMC_ERROR_NONE)
01157     {
01158       /* Clear all the static flags */
01159       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01160       __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
01161       hmmc->ErrorCode |= errorstate;
01162       hmmc->State = HAL_MMC_STATE_READY;
01163       return HAL_ERROR;
01164     }
01165
01166     return (HAL_StatusTypeDef)errorstate;
01167   }
01168   else
01169   {
01170     return HAL_BUSY;
01171   }
01172
01173 }
01174
01175 /**
01176   * @brief  Erases the specified memory area of the given MMC card.
01177   * @note   This API should be followed by a check on the card state through
01178   *         HAL_MMC_GetCardState().
01179   * @param  hmmc: Pointer to MMC handle
01180   * @param  BlockStartAdd: Start Block address
01181   * @param  BlockEndAdd: End Block address
01182   * @retval HAL status
01183   */
01184 HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
01185 {
01186   uint32_t errorstate = HAL_MMC_ERROR_NONE;
01187
01188   if(hmmc->State == HAL_MMC_STATE_READY)
01189   {
01190     hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
01191
01192     if(BlockEndAdd < BlockStartAdd)
01193     {
01194       hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
01195       return HAL_ERROR;
01196     }
01197
01198     if(BlockEndAdd > (hmmc->MmcCard.LogBlockNbr))
01199     {
01200       hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
01201       return HAL_ERROR;
01202     }
01203
01204     hmmc->State = HAL_MMC_STATE_BUSY;
01205
01206     /* Check if the card command class supports erase command */
01207     if(((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U)
01208     {
01209       /* Clear all the static flags */
01210       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01211       hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
01212       hmmc->State = HAL_MMC_STATE_READY;
01213       return HAL_ERROR;
01214     }
01215
01216     if((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
01217     {
01218       /* Clear all the static flags */
01219       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01220       hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED;
01221       hmmc->State = HAL_MMC_STATE_READY;
01222       return HAL_ERROR;
01223     }
01224
01225     if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
01226     {
01227       BlockStartAdd *= 512U;
01228       BlockEndAdd   *= 512U;
01229     }
01230
01231
01232     /* Send CMD35 MMC_ERASE_GRP_START with argument as addr  */
01233     errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, BlockStartAdd);
01234     if(errorstate != HAL_MMC_ERROR_NONE)
01235     {
01236         /* Clear all the static flags */
01237       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01238       hmmc->ErrorCode |= errorstate;
01239       hmmc->State = HAL_MMC_STATE_READY;
01240       return HAL_ERROR;
01241     }
01242
01243     /* Send CMD36 MMC_ERASE_GRP_END with argument as addr  */
01244     errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, BlockEndAdd);
01245     if(errorstate != HAL_MMC_ERROR_NONE)
01246     {
01247         /* Clear all the static flags */
01248       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01249       hmmc->ErrorCode |= errorstate;
01250       hmmc->State = HAL_MMC_STATE_READY;
01251       return HAL_ERROR;
01252     }
01253
01254     /* Send CMD38 ERASE */
01255     errorstate = SDMMC_CmdErase(hmmc->Instance);
01256     if(errorstate != HAL_MMC_ERROR_NONE)
01257     {
01258       /* Clear all the static flags */
01259       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01260       hmmc->ErrorCode |= errorstate;
01261       hmmc->State = HAL_MMC_STATE_READY;
01262       return HAL_ERROR;
01263     }
01264
01265     hmmc->State = HAL_MMC_STATE_READY;
01266
01267     return HAL_OK;
01268   }
01269   else
01270   {
01271     return HAL_BUSY;
01272   }
01273 }
01274
01275 /**
01276   * @brief  This function handles MMC card interrupt request.
01277   * @param  hmmc: Pointer to MMC handle
01278   * @retval None
01279   */
01280 void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
01281 {
01282   uint32_t errorstate = HAL_MMC_ERROR_NONE;
01283   uint32_t tickstart = HAL_GetTick();
01284
01285   /* Check for SDMMC interrupt flags */
01286   if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DATAEND) != RESET)
01287   {
01288     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DATAEND);
01289
01290     __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR\
01291                            | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE\
01292                            | SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_RXFIFOHF);
01293
01294     if((hmmc->Context & MMC_CONTEXT_DMA) != RESET)
01295     {
01296
01297       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01298       __SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
01299
01300       hmmc->Instance->DLEN = 0;
01301       hmmc->Instance->DCTRL = 0;
01302       hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA ;
01303
01304       /* Stop Transfer for Write Multi blocks or Read Multi blocks */
01305       if(((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET))
01306       {
01307         errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
01308         if(errorstate != HAL_MMC_ERROR_NONE)
01309         {
01310           hmmc->ErrorCode = errorstate;
01311           HAL_MMC_ErrorCallback(hmmc);
01312         }
01313       }
01314
01315       if(((hmmc->Context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET))
01316       {
01317         while((HAL_MMC_GetCardState(hmmc) != HAL_MMC_CARD_TRANSFER) && ((HAL_GetTick() - tickstart) <=  SDMMC_MAX_TRIAL))
01318         {
01319           /* Wait until SD CARD Status goes to TRANSFER STATE or Timeout */
01320         }
01321
01322         HAL_MMC_TxCpltCallback(hmmc);
01323       }
01324       if(((hmmc->Context & MMC_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != RESET))
01325       {
01326         HAL_MMC_RxCpltCallback(hmmc);
01327       }
01328
01329
01330       hmmc->State = HAL_MMC_STATE_READY;
01331
01332     }
01333
01334     if ((hmmc->Context & MMC_CONTEXT_IT) != RESET)
01335     {
01336       if ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != RESET)
01337       {
01338         errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
01339         if(errorstate != HAL_MMC_ERROR_NONE)
01340         {
01341           hmmc->ErrorCode = errorstate;
01342           HAL_MMC_ErrorCallback(hmmc);
01343         }
01344
01345         hmmc->State = HAL_MMC_STATE_READY;
01346
01347         HAL_MMC_RxCpltCallback(hmmc);
01348       }
01349       else if (((hmmc->Context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET))
01350       {
01351         if((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)
01352         {
01353           errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
01354           if(errorstate != HAL_MMC_ERROR_NONE)
01355           {
01356             hmmc->ErrorCode = errorstate;
01357             HAL_MMC_ErrorCallback(hmmc);
01358           }
01359         }
01360
01361
01362         /* Clear all the static flags */
01363         __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01364
01365         hmmc->State = HAL_MMC_STATE_READY;
01366
01367         HAL_MMC_TxCpltCallback(hmmc);
01368       }
01369     }
01370   }
01371
01372   else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXFIFOHE) != RESET)
01373   {
01374     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE);
01375
01376     MMC_Write_IT(hmmc);
01377   }
01378
01379   else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXFIFOHF) != RESET)
01380   {
01381     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF);
01382
01383     MMC_Read_IT(hmmc);
01384   }
01385
01386   else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET)
01387   {
01388     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL);
01389
01390     __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DCRCFAIL);
01391
01392     HAL_MMC_ErrorCallback(hmmc);
01393   }
01394
01395   else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DTIMEOUT) != RESET)
01396   {
01397     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT);
01398
01399     __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DTIMEOUT);
01400
01401     HAL_MMC_ErrorCallback(hmmc);
01402   }
01403
01404   else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXOVERR) != RESET)
01405   {
01406     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_RXOVERR);
01407
01408     __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_RXOVERR);
01409
01410     HAL_MMC_ErrorCallback(hmmc);
01411   }
01412
01413   else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXUNDERR) != RESET)
01414   {
01415     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_TXUNDERR);
01416
01417     __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_TXUNDERR);
01418
01419     HAL_MMC_ErrorCallback(hmmc);
01420   }
01421
01422   else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_IDMATE) != RESET)
01423   {
01424     __SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
01425     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_IDMATE);
01426
01427     __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMATE);
01428
01429     HAL_MMC_ErrorCallback(hmmc);
01430   }
01431   else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_IDMABTC) != RESET)
01432   {
01433     if(READ_BIT(hmmc->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == MMC_DMA_BUFFER0)
01434     {
01435       /* Current buffer is buffer0, Transfer complete for buffer1 */
01436       if((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)
01437       {
01438         HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback(hmmc);
01439       }
01440       else /* MMC_CONTEXT_READ_MULTIPLE_BLOCK */
01441       {
01442         HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback(hmmc);
01443       }
01444     }
01445     else /* MMC_DMA_BUFFER1 */
01446     {
01447       /* Current buffer is buffer1, Transfer complete for buffer0 */
01448       if((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)
01449       {
01450         HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback(hmmc);
01451       }
01452       else /* MMC_CONTEXT_READ_MULTIPLE_BLOCK */
01453       {
01454         HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback(hmmc);
01455       }
01456     }
01457     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_IT_IDMABTC);
01458   }
01459
01460 }
01461
01462 /**
01463   * @brief return the MMC state
01464   * @param hmmc: Pointer to mmc handle
01465   * @retval HAL state
01466   */
01467 HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc)
01468 {
01469   return hmmc->State;
01470 }
01471
01472 /**
01473 * @brief  Return the MMC error code
01474 * @param  hmmc : pointer to a MMC_HandleTypeDef structure that contains
01475   *              the configuration information.
01476 * @retval MMC Error Code
01477 */
01478 uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc)
01479 {
01480   return hmmc->ErrorCode;
01481 }
01482
01483 /**
01484   * @brief Tx Transfer completed callbacks
01485   * @param hmmc: Pointer to MMC handle
01486   * @retval None
01487   */
01488 __weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc)
01489 {
01490   /* Prevent unused argument(s) compilation warning */
01491   UNUSED(hmmc);
01492
01493   /* NOTE : This function should not be modified, when the callback is needed,
01494             the HAL_MMC_TxCpltCallback can be implemented in the user file
01495    */
01496 }
01497
01498 /**
01499   * @brief Rx Transfer completed callbacks
01500   * @param hmmc: Pointer MMC handle
01501   * @retval None
01502   */
01503 __weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc)
01504 {
01505   /* Prevent unused argument(s) compilation warning */
01506   UNUSED(hmmc);
01507
01508   /* NOTE : This function should not be modified, when the callback is needed,
01509             the HAL_MMC_ErrorCallback can be implemented in the user file
01510    */
01511 }
01512
01513 /**
01514   * @brief MMC error callbacks
01515   * @param hmmc: Pointer MMC handle
01516   * @retval None
01517   */
01518 __weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc)
01519 {
01520   /* Prevent unused argument(s) compilation warning */
01521   UNUSED(hmmc);
01522
01523   /* NOTE : This function should not be modified, when the callback is needed,
01524             the HAL_MMC_ErrorCallback can be implemented in the user file
01525    */
01526 }
01527
01528 /**
01529   * @brief MMC Abort callbacks
01530   * @param hmmc: Pointer MMC handle
01531   * @retval None
01532   */
01533 __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
01534 {
01535   /* Prevent unused argument(s) compilation warning */
01536   UNUSED(hmmc);
01537
01538   /* NOTE : This function should not be modified, when the callback is needed,
01539             the HAL_MMC_ErrorCallback can be implemented in the user file
01540    */
01541 }
01542
01543
01544 /**
01545   * @}
01546   */
01547
01548 /** @addtogroup MMC_Exported_Functions_Group3
01549  *  @brief   management functions
01550  *
01551 @verbatim
01552   ==============================================================================
01553                       ##### Peripheral Control functions #####
01554   ==============================================================================
01555   [..]
01556     This subsection provides a set of functions allowing to control the MMC card
01557     operations and get the related information
01558
01559 @endverbatim
01560   * @{
01561   */
01562
01563 /**
01564   * @brief  Returns information the information of the card which are stored on
01565   *         the CID register.
01566   * @param  hmmc: Pointer to MMC handle
01567   * @param  pCID: Pointer to a HAL_MMC_CIDTypedef structure that
01568   *         contains all CID register parameters
01569   * @retval HAL status
01570   */
01571 HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypedef *pCID)
01572 {
01573   uint32_t tmp = 0;
01574
01575   /* Byte 0 */
01576   tmp = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24);
01577   pCID->ManufacturerID = tmp;
01578
01579   /* Byte 1 */
01580   tmp = (uint8_t)((hmmc->CID[0] & 0x00FF0000) >> 16);
01581   pCID->OEM_AppliID = tmp << 8;
01582
01583   /* Byte 2 */
01584   tmp = (uint8_t)((hmmc->CID[0] & 0x000000FF00) >> 8);
01585   pCID->OEM_AppliID |= tmp;
01586
01587   /* Byte 3 */
01588   tmp = (uint8_t)(hmmc->CID[0] & 0x000000FF);
01589   pCID->ProdName1 = tmp << 24;
01590
01591   /* Byte 4 */
01592   tmp = (uint8_t)((hmmc->CID[1] & 0xFF000000U) >> 24);
01593   pCID->ProdName1 |= tmp << 16;
01594
01595   /* Byte 5 */
01596   tmp = (uint8_t)((hmmc->CID[1] & 0x00FF0000) >> 16);
01597   pCID->ProdName1 |= tmp << 8;
01598
01599   /* Byte 6 */
01600   tmp = (uint8_t)((hmmc->CID[1] & 0x0000FF00) >> 8);
01601   pCID->ProdName1 |= tmp;
01602
01603   /* Byte 7 */
01604   tmp = (uint8_t)(hmmc->CID[1] & 0x000000FF);
01605   pCID->ProdName2 = tmp;
01606
01607   /* Byte 8 */
01608   tmp = (uint8_t)((hmmc->CID[2] & 0xFF000000U) >> 24);
01609   pCID->ProdRev = tmp;
01610
01611   /* Byte 9 */
01612   tmp = (uint8_t)((hmmc->CID[2] & 0x00FF0000) >> 16);
01613   pCID->ProdSN = tmp << 24;
01614
01615   /* Byte 10 */
01616   tmp = (uint8_t)((hmmc->CID[2] & 0x0000FF00) >> 8);
01617   pCID->ProdSN |= tmp << 16;
01618
01619   /* Byte 11 */
01620   tmp = (uint8_t)(hmmc->CID[2] & 0x000000FF);
01621   pCID->ProdSN |= tmp << 8;
01622
01623   /* Byte 12 */
01624   tmp = (uint8_t)((hmmc->CID[3] & 0xFF000000U) >> 24);
01625   pCID->ProdSN |= tmp;
01626
01627   /* Byte 13 */
01628   tmp = (uint8_t)((hmmc->CID[3] & 0x00FF0000) >> 16);
01629   pCID->Reserved1   |= (tmp & 0xF0) >> 4;
01630   pCID->ManufactDate = (tmp & 0x0F) << 8;
01631
01632   /* Byte 14 */
01633   tmp = (uint8_t)((hmmc->CID[3] & 0x0000FF00) >> 8);
01634   pCID->ManufactDate |= tmp;
01635
01636   /* Byte 15 */
01637   tmp = (uint8_t)(hmmc->CID[3] & 0x000000FF);
01638   pCID->CID_CRC   = (tmp & 0xFE) >> 1;
01639   pCID->Reserved2 = 1;
01640
01641   return HAL_OK;
01642 }
01643
01644 /**
01645   * @brief  Returns information the information of the card which are stored on
01646   *         the CSD register.
01647   * @param  hmmc: Pointer to MMC handle
01648   * @param  pCSD: Pointer to a HAL_MMC_CardInfoTypedef structure that
01649   *         contains all CSD register parameters
01650   * @retval HAL status
01651   */
01652 HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
01653 {
01654   uint32_t block_nbr = 0;
01655   uint32_t tmp = 0;
01656
01657   /* Byte 0 */
01658   tmp = (hmmc->CSD[0] & 0xFF000000U) >> 24;
01659   pCSD->CSDStruct      = (uint8_t)((tmp & 0xC0) >> 6);
01660   pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2);
01661   pCSD->Reserved1      = tmp & 0x03;
01662
01663   /* Byte 1 */
01664   tmp = (hmmc->CSD[0] & 0x00FF0000) >> 16;
01665   pCSD->TAAC = (uint8_t)tmp;
01666
01667   /* Byte 2 */
01668   tmp = (hmmc->CSD[0] & 0x0000FF00) >> 8;
01669   pCSD->NSAC = (uint8_t)tmp;
01670
01671   /* Byte 3 */
01672   tmp = hmmc->CSD[0] & 0x000000FF;
01673   pCSD->MaxBusClkFrec = (uint8_t)tmp;
01674
01675   /* Byte 4 */
01676   tmp = (hmmc->CSD[1] & 0xFF000000U) >> 24;
01677   pCSD->CardComdClasses = (uint16_t)(tmp << 4);
01678
01679   /* Byte 5 */
01680   tmp = (hmmc->CSD[1] & 0x00FF0000U) >> 16;
01681   pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4);
01682   pCSD->RdBlockLen       = (uint8_t)(tmp & 0x0F);
01683
01684   /* Byte 6 */
01685   tmp = (hmmc->CSD[1] & 0x0000FF00U) >> 8;
01686   pCSD->PartBlockRead   = (uint8_t)((tmp & 0x80) >> 7);
01687   pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6);
01688   pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5);
01689   pCSD->DSRImpl         = (uint8_t)((tmp & 0x10) >> 4);
01690   pCSD->Reserved2       = 0; /*!< Reserved */
01691
01692   MMC_ReadExtCSD(hmmc, &block_nbr, 0x0FFFFFFFU);
01693
01694   if(hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD)
01695   {
01696     pCSD->DeviceSize = (tmp & 0x03) << 10;
01697
01698     /* Byte 7 */
01699     tmp = (uint8_t)(hmmc->CSD[1] & 0x000000FFU);
01700     pCSD->DeviceSize |= (tmp) << 2;
01701
01702     /* Byte 8 */
01703     tmp = (uint8_t)((hmmc->CSD[2] & 0xFF000000U) >> 24);
01704     pCSD->DeviceSize |= (tmp & 0xC0) >> 6;
01705
01706     pCSD->MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;
01707     pCSD->MaxRdCurrentVDDMax = (tmp & 0x07);
01708
01709     /* Byte 9 */
01710     tmp = (uint8_t)((hmmc->CSD[2] & 0x00FF0000U) >> 16);
01711     pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;
01712     pCSD->MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;
01713     pCSD->DeviceSizeMul      = (tmp & 0x03) << 1;
01714     /* Byte 10 */
01715     tmp = (uint8_t)((hmmc->CSD[2] & 0x0000FF00U) >> 8);
01716     pCSD->DeviceSizeMul |= (tmp & 0x80) >> 7;
01717
01718     hmmc->MmcCard.BlockNbr  = (pCSD->DeviceSize + 1) ;
01719     hmmc->MmcCard.BlockNbr *= (1 << (pCSD->DeviceSizeMul + 2));
01720     hmmc->MmcCard.BlockSize = 1 << (pCSD->RdBlockLen);
01721
01722     hmmc->MmcCard.LogBlockNbr =  (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512);
01723     hmmc->MmcCard.LogBlockSize = 512;
01724   }
01725   else if(hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD)
01726   {
01727     hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr = block_nbr;
01728     hmmc->MmcCard.LogBlockSize = hmmc->MmcCard.BlockSize = 512;
01729   }
01730
01731   pCSD->EraseGrSize = (tmp & 0x40) >> 6;
01732   pCSD->EraseGrMul  = (tmp & 0x3F) << 1;
01733
01734   /* Byte 11 */
01735   tmp = (uint8_t)(hmmc->CSD[2] & 0x000000FF);
01736   pCSD->EraseGrMul     |= (tmp & 0x80) >> 7;
01737   pCSD->WrProtectGrSize = (tmp & 0x7F);
01738
01739   /* Byte 12 */
01740   tmp = (uint8_t)((hmmc->CSD[3] & 0xFF000000U) >> 24);
01741   pCSD->WrProtectGrEnable = (tmp & 0x80) >> 7;
01742   pCSD->ManDeflECC        = (tmp & 0x60) >> 5;
01743   pCSD->WrSpeedFact       = (tmp & 0x1C) >> 2;
01744   pCSD->MaxWrBlockLen     = (tmp & 0x03) << 2;
01745
01746   /* Byte 13 */
01747   tmp = (uint8_t)((hmmc->CSD[3] & 0x00FF0000) >> 16);
01748   pCSD->MaxWrBlockLen      |= (tmp & 0xC0) >> 6;
01749   pCSD->WriteBlockPaPartial = (tmp & 0x20) >> 5;
01750   pCSD->Reserved3           = 0;
01751   pCSD->ContentProtectAppli = (tmp & 0x01);
01752
01753   /* Byte 14 */
01754   tmp = (uint8_t)((hmmc->CSD[3] & 0x0000FF00) >> 8);
01755   pCSD->FileFormatGrouop = (tmp & 0x80) >> 7;
01756   pCSD->CopyFlag         = (tmp & 0x40) >> 6;
01757   pCSD->PermWrProtect    = (tmp & 0x20) >> 5;
01758   pCSD->TempWrProtect    = (tmp & 0x10) >> 4;
01759   pCSD->FileFormat       = (tmp & 0x0C) >> 2;
01760   pCSD->ECC              = (tmp & 0x03);
01761
01762   /* Byte 15 */
01763   tmp = (uint8_t)(hmmc->CSD[3] & 0x000000FF);
01764   pCSD->CSD_CRC   = (tmp & 0xFE) >> 1;
01765   pCSD->Reserved4 = 1;
01766
01767   return HAL_OK;
01768 }
01769
01770 /**
01771   * @brief  Gets the MMC card info.
01772   * @param  hmmc: Pointer to MMC handle
01773   * @param  pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that
01774   *         will contain the MMC card status information
01775   * @retval HAL status
01776   */
01777 HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
01778 {
01779   pCardInfo->CardType     = (uint32_t)(hmmc->MmcCard.CardType);
01780   pCardInfo->Class        = (uint32_t)(hmmc->MmcCard.Class);
01781   pCardInfo->RelCardAdd   = (uint32_t)(hmmc->MmcCard.RelCardAdd);
01782   pCardInfo->BlockNbr     = (uint32_t)(hmmc->MmcCard.BlockNbr);
01783   pCardInfo->BlockSize    = (uint32_t)(hmmc->MmcCard.BlockSize);
01784   pCardInfo->LogBlockNbr  = (uint32_t)(hmmc->MmcCard.LogBlockNbr);
01785   pCardInfo->LogBlockSize = (uint32_t)(hmmc->MmcCard.LogBlockSize);
01786
01787   return HAL_OK;
01788 }
01789
01790 /**
01791   * @brief  Enables wide bus operation for the requested card if supported by
01792   *         card.
01793   * @param  hmmc: Pointer to MMC handle
01794   * @param  WideMode: Specifies the MMC card wide bus mode
01795   *          This parameter can be one of the following values:
01796   *            @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
01797   *            @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
01798   *            @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
01799   * @retval HAL status
01800   */
01801 HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode)
01802 {
01803   __IO uint32_t count = 0;
01804   uint32_t errorstate = HAL_MMC_ERROR_NONE;
01805   uint32_t response = 0, busy = 0;
01806   MMC_InitTypeDef Init;
01807
01808   /* Check the parameters */
01809   assert_param(IS_SDMMC_BUS_WIDE(WideMode));
01810
01811   /* Chnage Satte */
01812   hmmc->State = HAL_MMC_STATE_BUSY;
01813
01814   if(WideMode == SDMMC_BUS_WIDE_8B)
01815   {
01816     errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200);
01817     if(errorstate != HAL_MMC_ERROR_NONE)
01818     {
01819       hmmc->ErrorCode |= errorstate;
01820     }
01821   }
01822   else if(WideMode == SDMMC_BUS_WIDE_4B)
01823   {
01824     errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100);
01825     if(errorstate != HAL_MMC_ERROR_NONE)
01826     {
01827       hmmc->ErrorCode |= errorstate;
01828     }
01829   }
01830   else if(WideMode == SDMMC_BUS_WIDE_1B)
01831   {
01832     errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000);
01833     if(errorstate != HAL_MMC_ERROR_NONE)
01834     {
01835       hmmc->ErrorCode |= errorstate;
01836     }
01837   }
01838   else
01839   {
01840     /* WideMode is not a valid argument*/
01841     hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
01842   }
01843 /* Check for switch error and violation of the trial number of sending CMD 13 */
01844   while(busy == 0)
01845   {
01846     if(count++ == SDMMC_MAX_TRIAL)
01847     {
01848       hmmc->State = HAL_MMC_STATE_READY;
01849       hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
01850       return HAL_ERROR;
01851     }
01852
01853     /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
01854     errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
01855     if(errorstate != HAL_MMC_ERROR_NONE)
01856     {
01857       hmmc->ErrorCode |= errorstate;
01858     }
01859
01860     /* Get command response */
01861     response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
01862
01863     /* Get operating voltage*/
01864     busy = (((response >> 7) == 1) ? 0 : 1);
01865   }
01866
01867   /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
01868   count = SDMMC_DATATIMEOUT;
01869   while((response & 0x00000100) == 0)
01870   {
01871     if(count-- == 0)
01872     {
01873       hmmc->State = HAL_MMC_STATE_READY;
01874       hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
01875       return HAL_ERROR;
01876     }
01877
01878     /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
01879     errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
01880     if(errorstate != HAL_MMC_ERROR_NONE)
01881     {
01882       hmmc->ErrorCode |= errorstate;
01883     }
01884
01885     /* Get command response */
01886     response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
01887   }
01888
01889   if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
01890   {
01891     /* Clear all the static flags */
01892     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01893     hmmc->State = HAL_MMC_STATE_READY;
01894     return HAL_ERROR;
01895   }
01896   else
01897   {
01898     /* Configure the SDMMC peripheral */
01899     Init.ClockEdge           = hmmc->Init.ClockEdge;
01900     Init.ClockPowerSave      = hmmc->Init.ClockPowerSave;
01901     Init.BusWide             = WideMode;
01902     Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
01903     Init.ClockDiv            = hmmc->Init.ClockDiv;
01904     SDMMC_Init(hmmc->Instance, Init);
01905   }
01906
01907   /* Change State */
01908   hmmc->State = HAL_MMC_STATE_READY;
01909
01910   return HAL_OK;
01911 }
01912
01913 /**
01914   * @brief  Gets the current mmc card data state.
01915   * @param  hmmc: pointer to MMC handle
01916   * @retval Card state
01917   */
01918 HAL_MMC_CardStateTypedef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc)
01919 {
01920   HAL_MMC_CardStateTypedef cardstate =  HAL_MMC_CARD_TRANSFER;
01921   uint32_t errorstate = HAL_MMC_ERROR_NONE;
01922   uint32_t resp1 = 0;
01923
01924   errorstate = MMC_SendStatus(hmmc, &resp1);
01925   if(errorstate != HAL_OK)
01926   {
01927     hmmc->ErrorCode |= errorstate;
01928   }
01929
01930   cardstate = (HAL_MMC_CardStateTypedef)((resp1 >> 9) & 0x0F);
01931
01932   /* Clear all the static flags */
01933   __SDMMC_CLEAR_FLAG(hmmc->Instance, SDMMC_STATIC_FLAGS);
01934   return cardstate;
01935 }
01936
01937 /**
01938   * @brief  Abort the current transfer and disable the MMC.
01939   * @param  hmmc: pointer to a MMC_HandleTypeDef structure that contains
01940   *                the configuration information for MMC module.
01941   * @retval HAL status
01942   */
01943 HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc)
01944 {
01945   HAL_MMC_CardStateTypedef CardState;
01946
01947   /* DIsable All interrupts */
01948   __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
01949                            SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
01950
01951   /* Clear All flags */
01952   __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01953
01954   /* If IDMA Context, disable Internal DMA */
01955   hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
01956
01957   hmmc->State = HAL_MMC_STATE_READY;
01958   CardState = HAL_MMC_GetCardState(hmmc);
01959   if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
01960   {
01961     hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
01962   }
01963   if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
01964   {
01965     return HAL_ERROR;
01966   }
01967   return HAL_OK;
01968 }
01969
01970
01971 /**
01972   * @brief  Abort the current transfer and disable the MMC (IT mode).
01973   * @param  hmmc: pointer to a MMC_HandleTypeDef structure that contains
01974   *                the configuration information for MMC module.
01975   * @retval HAL status
01976   */
01977 HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc)
01978 {
01979   HAL_MMC_CardStateTypedef CardState;
01980
01981   /* DIsable All interrupts */
01982   __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
01983                            SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
01984
01985   /* Clear All flags */
01986   __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
01987
01988   CardState = HAL_MMC_GetCardState(hmmc);
01989   hmmc->State = HAL_MMC_STATE_READY;
01990   if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
01991   {
01992     hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
01993   }
01994   if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
01995   {
01996     return HAL_ERROR;
01997   }
01998   else
01999   {
02000     HAL_MMC_AbortCallback(hmmc);
02001   }
02002
02003   return HAL_OK;
02004 }
02005
02006
02007 /**
02008   * @}
02009   */
02010
02011 /**
02012   * @}
02013   */
02014
02015 /* Private function ----------------------------------------------------------*/
02016 /** @addtogroup MMC_Private_Functions
02017   * @{
02018   */
02019
02020
02021 /**
02022   * @brief  Initializes the mmc card.
02023   * @param  hmmc: Pointer to MMC handle
02024   * @retval MMC Card error state
02025   */
02026 static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
02027 {
02028   HAL_MMC_CardCSDTypeDef CSD;
02029   uint32_t errorstate = HAL_MMC_ERROR_NONE;
02030   uint16_t mmc_rca = 1;
02031   MMC_InitTypeDef Init;
02032
02033   /* Check the power State */
02034   if(SDMMC_GetPowerState(hmmc->Instance) == 0)
02035   {
02036     /* Power off */
02037     return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
02038   }
02039
02040       /* Send CMD2 ALL_SEND_CID */
02041   errorstate = SDMMC_CmdSendCID(hmmc->Instance);
02042   if(errorstate != HAL_MMC_ERROR_NONE)
02043   {
02044     return errorstate;
02045   }
02046   else
02047   {
02048       /* Get Card identification number data */
02049     hmmc->CID[0] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
02050     hmmc->CID[1] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2);
02051     hmmc->CID[2] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3);
02052     hmmc->CID[3] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4);
02053   }
02054
02055   /* Send CMD3 SET_REL_ADDR with argument 0 */
02056   /* MMC Card publishes its RCA. */
02057   errorstate = SDMMC_CmdSetRelAdd(hmmc->Instance, &mmc_rca);
02058   if(errorstate != HAL_MMC_ERROR_NONE)
02059   {
02060     return errorstate;
02061   }
02062
02063   /* Get the MMC card RCA */
02064   hmmc->MmcCard.RelCardAdd = mmc_rca;
02065
02066   /* Send CMD9 SEND_CSD with argument as card's RCA */
02067   errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
02068   if(errorstate != HAL_MMC_ERROR_NONE)
02069   {
02070     return errorstate;
02071   }
02072   else
02073   {
02074   /* Get Card Specific Data */
02075     hmmc->CSD[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
02076     hmmc->CSD[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2);
02077     hmmc->CSD[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3);
02078     hmmc->CSD[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4);
02079   }
02080
02081   /* Get the Card Class */
02082   hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20);
02083
02084    /* Select the Card */
02085   errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
02086   if(errorstate != HAL_MMC_ERROR_NONE)
02087   {
02088     return errorstate;
02089   }
02090
02091
02092   /* Get CSD parameters */
02093   HAL_MMC_GetCardCSD(hmmc, &CSD);
02094
02095   /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
02096   errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
02097   if(errorstate != HAL_MMC_ERROR_NONE)
02098   {
02099     hmmc->ErrorCode |= errorstate;
02100   }
02101
02102   /* Configure the SDMMC peripheral */
02103   Init.ClockEdge           = hmmc->Init.ClockEdge;
02104   Init.ClockPowerSave      = hmmc->Init.ClockPowerSave;
02105   Init.BusWide             = SDMMC_BUS_WIDE_1B;
02106   Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
02107   Init.ClockDiv            = hmmc->Init.ClockDiv;
02108   SDMMC_Init(hmmc->Instance, Init);
02109
02110   /* All cards are initialized */
02111   return HAL_MMC_ERROR_NONE;
02112 }
02113
02114 /**
02115   * @brief  Enquires cards about their operating voltage and configures clock
02116   *         controls and stores MMC information that will be needed in future
02117   *         in the MMC handle.
02118   * @param  hmmc: Pointer to MMC handle
02119   * @retval error state
02120   */
02121 static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc)
02122 {
02123   __IO uint32_t count = 0;
02124   uint32_t response = 0, validvoltage = 0;
02125   uint32_t errorstate = HAL_MMC_ERROR_NONE;
02126
02127   /* CMD0: GO_IDLE_STATE */
02128   errorstate = SDMMC_CmdGoIdleState(hmmc->Instance);
02129   if(errorstate != HAL_MMC_ERROR_NONE)
02130   {
02131     return errorstate;
02132   }
02133
02134   while(validvoltage == 0)
02135   {
02136     if(count++ == SDMMC_MAX_VOLT_TRIAL)
02137     {
02138       return HAL_MMC_ERROR_INVALID_VOLTRANGE;
02139     }
02140
02141     /* SEND CMD1 APP_CMD with MMC_HIGH_VOLTAGE_RANGE(0xC0FF8000) as argument */
02142     errorstate = SDMMC_CmdOpCondition(hmmc->Instance, eMMC_HIGH_VOLTAGE_RANGE);
02143     if(errorstate != HAL_MMC_ERROR_NONE)
02144     {
02145       return HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
02146     }
02147
02148     /* Get command response */
02149     response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
02150
02151     /* Get operating voltage*/
02152     validvoltage = (((response >> 31) == 1) ? 1 : 0);
02153   }
02154
02155   /* When power routine is finished and command returns valid voltage */
02156   if (((response & (0xFF000000U)) >> 24) == 0xC0U)
02157   {
02158     hmmc->MmcCard.CardType = MMC_HIGH_CAPACITY_CARD;
02159   }
02160   else
02161   {
02162     hmmc->MmcCard.CardType = MMC_LOW_CAPACITY_CARD;
02163   }
02164
02165   return HAL_MMC_ERROR_NONE;
02166 }
02167
02168 /**
02169   * @brief  Turns the SDMMC output signals off.
02170   * @param  hmmc: Pointer to MMC handle
02171   * @retval HAL status
02172   */
02173 static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc)
02174 {
02175   /* Set Power State to OFF */
02176   SDMMC_PowerState_OFF(hmmc->Instance);
02177
02178   return HAL_OK;
02179 }
02180
02181
02182 /**
02183   * @brief  Returns the current card's status.
02184   * @param  hmmc: pointer to MMC handle
02185   * @param  pCardStatus: pointer to the buffer that will contain the MMC card
02186   *         status (Card Status register)
02187   * @retval error state
02188   */
02189 static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
02190 {
02191   uint32_t errorstate = HAL_MMC_ERROR_NONE;
02192
02193   if(pCardStatus == NULL)
02194   {
02195     return HAL_MMC_ERROR_PARAM;
02196   }
02197
02198   /* Send Status command */
02199   errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16));
02200   if(errorstate != HAL_OK)
02201   {
02202     return errorstate;
02203   }
02204
02205   /* Get MMC card status */
02206   *pCardStatus = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
02207
02208   return HAL_MMC_ERROR_NONE;
02209 }
02210
02211 /**
02212   * @brief  Reads extended CSD register to get the sectors number of the device
02213   * @param  hmmc: Pointer to MMC handle
02214   * @param  pBlockNbr: Pointer to the read buffer
02215   * @param  Timeout: Specify timeout value
02216   * @retval HAL status
02217   */
02218 HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pBlockNbr, uint32_t Timeout)
02219 {
02220   SDMMC_DataInitTypeDef config;
02221   uint32_t errorstate = HAL_MMC_ERROR_NONE;
02222   uint32_t tickstart = HAL_GetTick();
02223   uint32_t count = 0;
02224   uint32_t i = 0;
02225   uint32_t tmp_data = 0;
02226
02227   hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
02228
02229   /* Initialize data control register */
02230   hmmc->Instance->DCTRL = 0;
02231
02232   /* Configure the MMC DPSM (Data Path State Machine) */
02233   config.DataTimeOut   = SDMMC_DATATIMEOUT;
02234   config.DataLength    = 0;
02235   config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B;
02236   config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
02237   config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
02238   config.DPSM          = SDMMC_DPSM_DISABLE;
02239   SDMMC_ConfigData(hmmc->Instance, &config);
02240
02241   /* Set Block Size for Card */
02242   errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
02243   if(errorstate != HAL_MMC_ERROR_NONE)
02244   {
02245     /* Clear all the static flags */
02246     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
02247     hmmc->ErrorCode |= errorstate;
02248     hmmc->State = HAL_MMC_STATE_READY;
02249     return HAL_ERROR;
02250   }
02251
02252   /* Configure the MMC DPSM (Data Path State Machine) */
02253   config.DataTimeOut   = SDMMC_DATATIMEOUT;
02254   config.DataLength    = 512;
02255   config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
02256   config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
02257   config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
02258   config.DPSM          = SDMMC_DPSM_ENABLE;
02259   SDMMC_ConfigData(hmmc->Instance, &config);
02260
02261   /* Set Block Size for Card */
02262   errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0);
02263   if(errorstate != HAL_MMC_ERROR_NONE)
02264   {
02265     /* Clear all the static flags */
02266     __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
02267     hmmc->ErrorCode |= errorstate;
02268     hmmc->State = HAL_MMC_STATE_READY;
02269     return HAL_ERROR;
02270   }
02271
02272   /* Poll on SDMMC flags */
02273   while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
02274   {
02275     if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
02276     {
02277       /* Read data from SDMMC Rx FIFO */
02278       for(count = 0U; count < 8U; count++)
02279       {
02280         tmp_data = SDMMC_ReadFIFO(hmmc->Instance);
02281         if ((i == 48) && (count == 5))
02282         {
02283           *pBlockNbr = tmp_data;
02284         }
02285       }
02286       i += 8U;
02287     }
02288
02289     if((Timeout == 0U)||((HAL_GetTick()-tickstart) >=  Timeout))
02290     {
02291       /* Clear all the static flags */
02292       __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
02293       hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
02294       hmmc->State= HAL_MMC_STATE_READY;
02295       return HAL_TIMEOUT;
02296     }
02297   }
02298
02299   /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
02300   errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
02301   if(errorstate != HAL_MMC_ERROR_NONE)
02302   {
02303     hmmc->ErrorCode |= errorstate;
02304   }
02305
02306   /* Clear all the static flags */
02307   __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
02308
02309   hmmc->State = HAL_MMC_STATE_READY;
02310
02311   return HAL_OK;
02312 }
02313
02314 /**
02315   * @brief  Wrap up reading in non-blocking mode.
02316   * @param  hmmc: pointer to a MMC_HandleTypeDef structure that contains
02317   *              the configuration information.
02318   * @retval HAL status
02319   */
02320 static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc)
02321 {
02322   uint32_t count = 0;
02323   uint32_t* tmp;
02324
02325   tmp = (uint32_t*)hmmc->pRxBuffPtr;
02326
02327   /* Read data from SDMMC Rx FIFO */
02328   for(count = 0; count < 8; count++)
02329   {
02330     *(tmp + count) = SDMMC_ReadFIFO(hmmc->Instance);
02331   }
02332
02333   hmmc->pRxBuffPtr += 8;
02334
02335   return HAL_OK;
02336 }
02337
02338 /**
02339   * @brief  Wrap up writing in non-blocking mode.
02340   * @param  hmmc: pointer to a MMC_HandleTypeDef structure that contains
02341   *              the configuration information.
02342   * @retval HAL status
02343   */
02344 static HAL_StatusTypeDef MMC_Write_IT(MMC_HandleTypeDef *hmmc)
02345 {
02346   uint32_t count = 0;
02347   uint32_t* tmp;
02348
02349   tmp = (uint32_t*)hmmc->pTxBuffPtr;
02350
02351   /* Write data to SDMMC Tx FIFO */
02352   for(count = 0; count < 8; count++)
02353   {
02354     SDMMC_WriteFIFO(hmmc->Instance, (tmp + count));
02355   }
02356
02357   hmmc->pTxBuffPtr += 8;
02358
02359   return HAL_OK;
02360 }
02361
02362 /**
02363   * @brief Read DMA Buffer 0 Transfer completed callbacks
02364   * @param hmmc: MMC handle
02365   * @retval None
02366   */
02367 __weak void HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback(MMC_HandleTypeDef *hmmc)
02368 {
02369   /* Prevent unused argument(s) compilation warning */
02370   UNUSED(hmmc);
02371
02372   /* NOTE : This function should not be modified, when the callback is needed,
02373             the HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback can be implemented in the user file
02374    */
02375 }
02376
02377 /**
02378   * @brief Read DMA Buffer 1 Transfer completed callbacks
02379   * @param hmmc: MMC handle
02380   * @retval None
02381   */
02382 __weak void HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc)
02383 {
02384   /* Prevent unused argument(s) compilation warning */
02385   UNUSED(hmmc);
02386
02387   /* NOTE : This function should not be modified, when the callback is needed,
02388             the HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback can be implemented in the user file
02389    */
02390 }
02391
02392 /**
02393   * @brief Write DMA Buffer 0 Transfer completed callbacks
02394   * @param hmmc: MMC handle
02395   * @retval None
02396   */
02397 __weak void HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback(MMC_HandleTypeDef *hmmc)
02398 {
02399   /* Prevent unused argument(s) compilation warning */
02400   UNUSED(hmmc);
02401
02402   /* NOTE : This function should not be modified, when the callback is needed,
02403             the HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file
02404    */
02405 }
02406
02407 /**
02408   * @brief Write DMA Buffer 1 Transfer completed callbacks
02409   * @param hmmc: MMC handle
02410   * @retval None
02411   */
02412 __weak void HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc)
02413 {
02414   /* Prevent unused argument(s) compilation warning */
02415   UNUSED(hmmc);
02416
02417   /* NOTE : This function should not be modified, when the callback is needed,
02418             the HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file
02419    */
02420 }
02421
02422
02423 /**
02424   * @}
02425   */
02426
02427 #endif /* HAL_MMC_MODULE_ENABLED */
02428
02429 /**
02430   * @}
02431   */
02432
02433 /**
02434   * @}
02435   */
02436
02437 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_mmc.h Source File

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stm32h7xx_hal_mmc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_mmc.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of MMC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_MMC_H
00040 #define __STM32H7xx_HAL_MMC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_ll_sdmmc.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup MMC
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup MMC_Exported_Types MMC Exported Types
00059   * @{
00060   */
00061
00062 /** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
00063   * @{
00064   */
00065 typedef enum
00066 {
00067   HAL_MMC_STATE_RESET                  = ((uint32_t)0x00000000U),  /*!< MMC not yet initialized or disabled  */
00068   HAL_MMC_STATE_READY                  = ((uint32_t)0x00000001U),  /*!< MMC initialized and ready for use    */
00069   HAL_MMC_STATE_TIMEOUT                = ((uint32_t)0x00000002U),  /*!< MMC Timeout state                    */
00070   HAL_MMC_STATE_BUSY                   = ((uint32_t)0x00000003U),  /*!< MMC process ongoing                  */
00071   HAL_MMC_STATE_PROGRAMMING            = ((uint32_t)0x00000004U),  /*!< MMC Programming State                */
00072   HAL_MMC_STATE_RECEIVING              = ((uint32_t)0x00000005U),  /*!< MMC Receinving State                 */
00073   HAL_MMC_STATE_TRANSFER               = ((uint32_t)0x00000006U),  /*!< MMC Transfert State                  */
00074   HAL_MMC_STATE_ERROR                  = ((uint32_t)0x0000000FU)   /*!< MMC is in error state                */
00075 }HAL_MMC_StateTypeDef;
00076 /**
00077   * @}
00078   */
00079
00080 /** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
00081   * @{
00082   */
00083 typedef enum
00084 {
00085   HAL_MMC_CARD_READY                  = ((uint32_t)0x00000001U),  /*!< Card state is ready                     */
00086   HAL_MMC_CARD_IDENTIFICATION         = ((uint32_t)0x00000002U),  /*!< Card is in identification state         */
00087   HAL_MMC_CARD_STANDBY                = ((uint32_t)0x00000003U),  /*!< Card is in standby state                */
00088   HAL_MMC_CARD_TRANSFER               = ((uint32_t)0x00000004U),  /*!< Card is in transfer state               */
00089   HAL_MMC_CARD_SENDING                = ((uint32_t)0x00000005U),  /*!< Card is sending an operation            */
00090   HAL_MMC_CARD_RECEIVING              = ((uint32_t)0x00000006U),  /*!< Card is receiving operation information */
00091   HAL_MMC_CARD_PROGRAMMING            = ((uint32_t)0x00000007U),  /*!< Card is in programming state            */
00092   HAL_MMC_CARD_DISCONNECTED           = ((uint32_t)0x00000008U),  /*!< Card is disconnected                    */
00093   HAL_MMC_CARD_ERROR                  = ((uint32_t)0x000000FFU)   /*!< Card response Error                     */
00094 }HAL_MMC_CardStateTypedef;
00095 /**
00096   * @}
00097   */
00098
00099 /** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition
00100   * @{
00101   */
00102 #define MMC_InitTypeDef      SDMMC_InitTypeDef
00103 #define MMC_TypeDef          SDMMC_TypeDef
00104
00105 /**
00106   * @brief  MMC Card Information Structure definition
00107   */
00108 typedef struct
00109 {
00110   uint32_t CardType;                     /*!< Specifies the card Type                         */
00111
00112   uint32_t Class;                        /*!< Specifies the class of the card class           */
00113
00114   uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address            */
00115
00116   uint32_t BlockNbr;                     /*!< Specifies the Card Capacity in blocks           */
00117
00118   uint32_t BlockSize;                    /*!< Specifies one block size in bytes               */
00119
00120   uint32_t LogBlockNbr;                  /*!< Specifies the Card logical Capacity in blocks   */
00121
00122   uint32_t LogBlockSize;                 /*!< Specifies logical block size in bytes           */
00123
00124 }HAL_MMC_CardInfoTypeDef;
00125
00126 /**
00127   * @brief  MMC handle Structure definition
00128   */
00129
00130 typedef struct
00131 {
00132   MMC_TypeDef                   *Instance;        /*!< MMC registers base address           */
00133
00134   MMC_InitTypeDef               Init;             /*!< MMC required parameters                         */
00135
00136   HAL_LockTypeDef              Lock;             /*!< MMC locking object                              */
00137
00138   uint32_t                     *pTxBuffPtr;      /*!< Pointer to MMC Tx transfer Buffer              */
00139
00140   uint32_t                     TxXferSize;       /*!< MMC Tx Transfer size                           */
00141
00142   uint32_t                     *pRxBuffPtr;      /*!< Pointer to MMC Rx transfer Buffer              */
00143
00144   uint32_t                     RxXferSize;       /*!< MMC Rx Transfer size                           */
00145
00146   __IO uint32_t                Context;          /*!< MMC transfer context                           */
00147
00148   __IO HAL_MMC_StateTypeDef     State;           /*!< MMC card State                                   */
00149
00150   __IO uint32_t                ErrorCode;       /*!< MMC Card Error codes                              */
00151
00152   HAL_MMC_CardInfoTypeDef       MmcCard;           /*!< MMC Card information                 */
00153
00154   uint32_t                     CSD[4];           /*!< MMC card specific data table         */
00155
00156   uint32_t                     CID[4];           /*!< MMC card identification number table */
00157
00158 }MMC_HandleTypeDef;
00159
00160
00161 /**
00162   * @}
00163   */
00164
00165 /** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register
00166   * @{
00167   */
00168 typedef struct
00169 {
00170   __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
00171   __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
00172   __IO uint8_t  Reserved1;            /*!< Reserved                              */
00173   __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
00174   __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
00175   __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
00176   __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
00177   __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
00178   __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
00179   __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
00180   __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
00181   __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
00182   __IO uint8_t  Reserved2;            /*!< Reserved                              */
00183   __IO uint32_t DeviceSize;           /*!< Device Size                           */
00184   __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
00185   __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
00186   __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
00187   __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
00188   __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
00189   __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
00190   __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
00191   __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
00192   __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
00193   __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
00194   __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
00195   __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
00196   __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
00197   __IO uint8_t  Reserved3;            /*!< Reserved                              */
00198   __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
00199   __IO uint8_t  FileFormatGrouop;     /*!< File format group                     */
00200   __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
00201   __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
00202   __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
00203   __IO uint8_t  FileFormat;           /*!< File format                           */
00204   __IO uint8_t  ECC;                  /*!< ECC code                              */
00205   __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
00206   __IO uint8_t  Reserved4;            /*!< Always 1                              */
00207
00208 }HAL_MMC_CardCSDTypeDef;
00209 /**
00210   * @}
00211   */
00212
00213 /** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
00214   * @{
00215   */
00216 typedef struct
00217 {
00218   __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
00219   __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
00220   __IO uint32_t ProdName1;       /*!< Product Name part1    */
00221   __IO uint8_t  ProdName2;       /*!< Product Name part2    */
00222   __IO uint8_t  ProdRev;         /*!< Product Revision      */
00223   __IO uint32_t ProdSN;          /*!< Product Serial Number */
00224   __IO uint8_t  Reserved1;       /*!< Reserved1             */
00225   __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
00226   __IO uint8_t  CID_CRC;         /*!< CID CRC               */
00227   __IO uint8_t  Reserved2;       /*!< Always 1              */
00228
00229 }HAL_MMC_CardCIDTypedef;
00230 /**
00231   * @}
00232   */
00233
00234 /**
00235   * @}
00236   */
00237
00238 /* Exported constants --------------------------------------------------------*/
00239 /** @defgroup MMC_Exported_Constants Exported Constants
00240   * @{
00241   */
00242
00243 #define BLOCKSIZE   ((uint32_t)512U) /*!< Block size is 512 bytes */
00244
00245 /** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
00246   * @{
00247   */
00248 #define HAL_MMC_ERROR_NONE                     SDMMC_ERROR_NONE                    /*!< No error                                                      */
00249 #define HAL_MMC_ERROR_CMD_CRC_FAIL             SDMMC_ERROR_CMD_CRC_FAIL            /*!< Command response received (but CRC check failed)              */
00250 #define HAL_MMC_ERROR_DATA_CRC_FAIL            SDMMC_ERROR_DATA_CRC_FAIL           /*!< Data block sent/received (CRC check failed)                   */
00251 #define HAL_MMC_ERROR_CMD_RSP_TIMEOUT          SDMMC_ERROR_CMD_RSP_TIMEOUT         /*!< Command response timeout                                      */
00252 #define HAL_MMC_ERROR_DATA_TIMEOUT             SDMMC_ERROR_DATA_TIMEOUT            /*!< Data timeout                                                  */
00253 #define HAL_MMC_ERROR_TX_UNDERRUN              SDMMC_ERROR_TX_UNDERRUN             /*!< Transmit FIFO underrun                                        */
00254 #define HAL_MMC_ERROR_RX_OVERRUN               SDMMC_ERROR_RX_OVERRUN              /*!< Receive FIFO overrun                                          */
00255 #define HAL_MMC_ERROR_ADDR_MISALIGNED          SDMMC_ERROR_ADDR_MISALIGNED         /*!< Misaligned address                                            */
00256 #define HAL_MMC_ERROR_BLOCK_LEN_ERR            SDMMC_ERROR_BLOCK_LEN_ERR           /*!< Transferred block length is not allowed for the card or the
00257                                                                                           number of transferred bytes does not match the block length   */
00258 #define HAL_MMC_ERROR_ERASE_SEQ_ERR            SDMMC_ERROR_ERASE_SEQ_ERR           /*!< An error in the sequence of erase command occurs              */
00259 #define HAL_MMC_ERROR_BAD_ERASE_PARAM          SDMMC_ERROR_BAD_ERASE_PARAM         /*!< An invalid selection for erase groups                         */
00260 #define HAL_MMC_ERROR_WRITE_PROT_VIOLATION     SDMMC_ERROR_WRITE_PROT_VIOLATION    /*!< Attempt to program a write protect block                      */
00261 #define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED       SDMMC_ERROR_LOCK_UNLOCK_FAILED      /*!< Sequence or password error has been detected in unlock
00262                                                                                            command or if there was an attempt to access a locked card   */
00263 #define HAL_MMC_ERROR_COM_CRC_FAILED           SDMMC_ERROR_COM_CRC_FAILED          /*!< CRC check of the previous command failed                      */
00264 #define HAL_MMC_ERROR_ILLEGAL_CMD              SDMMC_ERROR_ILLEGAL_CMD             /*!< Command is not legal for the card state                       */
00265 #define HAL_MMC_ERROR_CARD_ECC_FAILED          SDMMC_ERROR_CARD_ECC_FAILED         /*!< Card internal ECC was applied but failed to correct the data  */
00266 #define HAL_MMC_ERROR_CC_ERR                   SDMMC_ERROR_CC_ERR                  /*!< Internal card controller error                                */
00267 #define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR      SDMMC_ERROR_GENERAL_UNKNOWN_ERR     /*!< General or unknown error                                      */
00268 #define HAL_MMC_ERROR_STREAM_READ_UNDERRUN     SDMMC_ERROR_STREAM_READ_UNDERRUN    /*!< The card could not sustain data reading in stream rmode       */
00269 #define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN     SDMMC_ERROR_STREAM_WRITE_OVERRUN    /*!< The card could not sustain data programming in stream mode    */
00270 #define HAL_MMC_ERROR_CID_CSD_OVERWRITE        SDMMC_ERROR_CID_CSD_OVERWRITE       /*!< CID/CSD overwrite error                                       */
00271 #define HAL_MMC_ERROR_WP_ERASE_SKIP            SDMMC_ERROR_WP_ERASE_SKIP           /*!< Only partial address space was erased                         */
00272 #define HAL_MMC_ERROR_CARD_ECC_DISABLED        SDMMC_ERROR_CARD_ECC_DISABLED       /*!< Command has been executed without using internal ECC          */
00273 #define HAL_MMC_ERROR_ERASE_RESET              SDMMC_ERROR_ERASE_RESET             /*!< Erase sequence was cleared before executing because an out
00274                                                                                            of erase sequence command was received                       */
00275 #define HAL_MMC_ERROR_AKE_SEQ_ERR              SDMMC_ERROR_AKE_SEQ_ERR             /*!< Error in sequence of authentication                           */
00276 #define HAL_MMC_ERROR_INVALID_VOLTRANGE        SDMMC_ERROR_INVALID_VOLTRANGE       /*!< Error in case of invalid voltage range                        */
00277 #define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE        SDMMC_ERROR_ADDR_OUT_OF_RANGE       /*!< Error when addressed block is out of range                    */
00278 #define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE   SDMMC_ERROR_REQUEST_NOT_APPLICABLE  /*!< Error when command request is not applicable                  */
00279 #define HAL_MMC_ERROR_PARAM                    SDMMC_ERROR_INVALID_PARAMETER       /*!< the used parameter is not valid                               */
00280 #define HAL_MMC_ERROR_UNSUPPORTED_FEATURE      SDMMC_ERROR_UNSUPPORTED_FEATURE     /*!< Error when feature is not insupported                         */
00281 #define HAL_MMC_ERROR_BUSY                     SDMMC_ERROR_BUSY                    /*!< Error when transfer process is busy                           */
00282 #define HAL_MMC_ERROR_DMA                      SDMMC_ERROR_DMA                     /*!< Error while DMA transfer                                      */
00283 #define HAL_MMC_ERROR_TIMEOUT                  SDMMC_ERROR_TIMEOUT                 /*!< Timeout error                                                 */
00284
00285 /**
00286   * @}
00287   */
00288
00289 /** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
00290   * @{
00291   */
00292 #define   MMC_CONTEXT_NONE                 ((uint32_t)0x00000000U)  /*!< None                             */
00293 #define   MMC_CONTEXT_READ_SINGLE_BLOCK    ((uint32_t)0x00000001U)  /*!< Read single block operation      */
00294 #define   MMC_CONTEXT_READ_MULTIPLE_BLOCK  ((uint32_t)0x00000002U)  /*!< Read multiple blocks operation   */
00295 #define   MMC_CONTEXT_WRITE_SINGLE_BLOCK   ((uint32_t)0x00000010U)  /*!< Write single block operation     */
00296 #define   MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)  /*!< Write multiple blocks operation  */
00297 #define   MMC_CONTEXT_IT                   ((uint32_t)0x00000008U)  /*!< Process in Interrupt mode        */
00298 #define   MMC_CONTEXT_DMA                  ((uint32_t)0x00000080U)  /*!< Process in DMA mode              */
00299
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
00305   * @{
00306   */
00307 /**
00308   * @brief
00309   */
00310 #define MMC_HIGH_VOLTAGE_RANGE         0x80FF8000U  /*!< VALUE OF ARGUMENT            */
00311 #define MMC_DUAL_VOLTAGE_RANGE         0x80FF8080U  /*!< VALUE OF ARGUMENT            */
00312 #define eMMC_HIGH_VOLTAGE_RANGE        0xC0FF8000U  /*!< for eMMC > 2Gb sector mode   */
00313 #define eMMC_DUAL_VOLTAGE_RANGE        0xC0FF8080U  /*!< for eMMC > 2Gb sector mode   */
00314 #define MMC_INVALID_VOLTAGE_RANGE      0x0001FF01U
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
00320   * @{
00321   */
00322 #define  MMC_LOW_CAPACITY_CARD     ((uint32_t)0x00000000U)   /*!< MMC Card Capacity <=2Gbytes   */
00323 #define  MMC_HIGH_CAPACITY_CARD     ((uint32_t)0x00000001U)  /*!< MMC Card Capacity >2Gbytes and <2Tbytes   */
00324
00325 /**
00326   * @}
00327   */
00328
00329 /**
00330   * @}
00331   */
00332
00333 /* Exported macro ------------------------------------------------------------*/
00334 /** @defgroup MMC_Exported_macros MMC Exported Macros
00335  *  @brief macros to handle interrupts and specific clock configurations
00336  * @{
00337  */
00338
00339 /**
00340   * @brief  Enable the MMC device interrupt.
00341   * @param  __HANDLE__: MMC Handle
00342   * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
00343   *         This parameter can be one or a combination of the following values:
00344   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
00345   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
00346   *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
00347   *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
00348   *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
00349   *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
00350   *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
00351   *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
00352   *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
00353   *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
00354   *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
00355   *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
00356   *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
00357   *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
00358   *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
00359   *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
00360   *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
00361   *            @arg SDMMC_IT_SDIOIT:     SD I/O interrupt received interrupt
00362   *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
00363   *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
00364   *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
00365   *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
00366   *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
00367   * @retval None
00368   */
00369 #define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00370
00371 /**
00372   * @brief  Disable the MMC device interrupt.
00373   * @param  __HANDLE__: MMC Handle
00374   * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
00375   *          This parameter can be one or a combination of the following values:
00376   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
00377   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
00378   *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
00379   *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
00380   *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
00381   *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
00382   *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
00383   *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
00384   *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
00385   *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
00386   *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
00387   *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
00388   *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
00389   *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
00390   *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
00391   *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
00392   *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
00393   *            @arg SDMMC_IT_SDIOIT:     SD I/O interrupt received interrupt
00394   *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
00395   *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
00396   *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
00397   *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
00398   *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
00399   * @retval None
00400   */
00401 #define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00402
00403 /**
00404   * @brief  Check whether the specified MMC flag is set or not.
00405   * @param  __HANDLE__: MMC Handle
00406   * @param  __FLAG__: specifies the flag to check.
00407   *          This parameter can be one of the following values:
00408   *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
00409   *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
00410   *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout
00411   *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout
00412   *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error
00413   *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error
00414   *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)
00415   *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)
00416   *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)
00417   *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
00418   *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)
00419   *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
00420   *            @arg SDMMC_FLAG_CPSMACT:    Command path state machine active
00421   *            @arg SDMMC_FLAG_DPSMACT:    Data path state machine active
00422   *            @arg SDMMC_FLAG_TXFIFOHE:   Transmit FIFO Half Empty
00423   *            @arg SDMMC_FLAG_RXFIFOHF:   Receive FIFO Half Full
00424   *            @arg SDMMC_FLAG_TXFIFOF:    Transmit FIFO full
00425   *            @arg SDMMC_FLAG_RXFIFOF:    Receive FIFO full
00426   *            @arg SDMMC_FLAG_TXFIFOE:    Transmit FIFO empty
00427   *            @arg SDMMC_FLAG_RXFIFOE:    Receive FIFO empty
00428   *            @arg SDMMC_FLAG_BUSYD0:     Inverted value of SDMMC_D0 line (Busy)
00429   *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
00430   *            @arg SDMMC_FLAG_SDIOIT:     SD I/O interrupt received
00431   *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
00432   *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
00433   *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
00434   *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
00435   *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
00436   *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
00437   * @retval The new state of MMC FLAG (SET or RESET).
00438   */
00439 #define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
00440
00441 /**
00442   * @brief  Clear the MMC's pending flags.
00443   * @param  __HANDLE__: MMC Handle
00444   * @param  __FLAG__: specifies the flag to clear.
00445   *          This parameter can be one or a combination of the following values:
00446   *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
00447   *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
00448   *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout
00449   *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout
00450   *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error
00451   *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error
00452   *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)
00453   *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)
00454   *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)
00455   *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
00456   *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)
00457   *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
00458   *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
00459   *            @arg SDMMC_FLAG_SDIOIT:     SD I/O interrupt received
00460   *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
00461   *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
00462   *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
00463   *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
00464   *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
00465   *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
00466   * @retval None
00467   */
00468 #define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
00469
00470 /**
00471   * @brief  Check whether the specified MMC interrupt has occurred or not.
00472   * @param  __HANDLE__: MMC Handle
00473   * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check.
00474   *          This parameter can be one of the following values:
00475   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
00476   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
00477   *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
00478   *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
00479   *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
00480   *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
00481   *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
00482   *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
00483   *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
00484   *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
00485   *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
00486   *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
00487   *            @arg SDMMC_IT_DPSMACT:    Data path state machine active interrupt
00488   *            @arg SDMMC_IT_CPSMACT:    Command path state machine active interrupt
00489   *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
00490   *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
00491   *            @arg SDMMC_IT_TXFIFOF:    Transmit FIFO full interrupt
00492   *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
00493   *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
00494   *            @arg SDMMC_IT_RXFIFOE:    Receive FIFO empty interrupt
00495   *            @arg SDMMC_IT_BUSYD0:     Inverted value of SDMMC_D0 line (Busy)
00496   *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
00497   *            @arg SDMMC_IT_SDIOIT:     SD I/O interrupt received interrupt
00498   *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
00499   *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
00500   *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
00501   *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
00502   *            @arg SDMMC_IT_IDMATE:     IDMA transfer error interrupt
00503   *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
00504   * @retval The new state of MMC IT (SET or RESET).
00505   */
00506 #define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00507
00508 /**
00509   * @brief  Clear the MMC's interrupt pending bits.
00510   * @param  __HANDLE__: MMC Handle
00511   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
00512   *          This parameter can be one or a combination of the following values:
00513   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
00514   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
00515   *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
00516   *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
00517   *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
00518   *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
00519   *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
00520   *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
00521   *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
00522   *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
00523   *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
00524   *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
00525   *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
00526   *            @arg SDMMC_IT_SDIOIT:     SD I/O interrupt received interrupt
00527   *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
00528   *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
00529   *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
00530   *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
00531   *            @arg SDMMC_IT_IDMATE:     IDMA transfer error interrupt
00532   *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
00533   * @retval None
00534   */
00535 #define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00536
00537 /**
00538   * @}
00539   */
00540
00541   /* Include MMC HAL Extension module */
00542 #include "stm32h7xx_hal_mmc_ex.h"
00543
00544 /* Exported functions --------------------------------------------------------*/
00545 /** @defgroup MMC_Exported_Functions MMC Exported Functions
00546   * @{
00547   */
00548
00549 /** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions
00550   * @{
00551   */
00552 HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
00553 HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
00554 HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
00555 void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
00556 void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
00557
00558 /**
00559   * @}
00560   */
00561
00562 /** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
00563   * @{
00564   */
00565 /* Blocking mode: Polling */
00566 HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
00567 HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
00568 HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
00569 /* Non-Blocking mode: IT */
00570 HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00571 HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00572 /* Non-Blocking mode: DMA */
00573 HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00574 HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00575
00576 void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
00577
00578 /* Callback in non blocking modes (DMA) */
00579 void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
00580 void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
00581 void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
00582 void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
00583 /**
00584   * @}
00585   */
00586
00587 /** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
00588   * @{
00589   */
00590 HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
00591 /**
00592   * @}
00593   */
00594
00595 /** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
00596   * @{
00597   */
00598 HAL_MMC_CardStateTypedef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
00599 HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypedef *pCID);
00600 HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
00601 HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
00602 /**
00603   * @}
00604   */
00605
00606 /** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
00607   * @{
00608   */
00609 HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc);
00610 uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc);
00611 /**
00612   * @}
00613   */
00614
00615 /** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management
00616   * @{
00617   */
00618 HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
00619 HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
00620 /**
00621   * @}
00622   */
00623
00624 /* Private types -------------------------------------------------------------*/
00625 /** @defgroup MMC_Private_Types MMC Private Types
00626   * @{
00627   */
00628
00629 /**
00630   * @}
00631   */
00632
00633 /* Private defines -----------------------------------------------------------*/
00634 /** @defgroup MMC_Private_Defines MMC Private Defines
00635   * @{
00636   */
00637
00638 /**
00639   * @}
00640   */
00641
00642 /* Private variables ---------------------------------------------------------*/
00643 /** @defgroup MMC_Private_Variables MMC Private Variables
00644   * @{
00645   */
00646
00647 /**
00648   * @}
00649   */
00650
00651 /* Private constants ---------------------------------------------------------*/
00652 /** @defgroup MMC_Private_Constants MMC Private Constants
00653   * @{
00654   */
00655
00656 /**
00657   * @}
00658   */
00659
00660 /* Private macros ------------------------------------------------------------*/
00661 /** @defgroup MMC_Private_Macros MMC Private Macros
00662   * @{
00663   */
00664
00665 /**
00666   * @}
00667   */
00668
00669 /* Private functions prototypes ----------------------------------------------*/
00670 /** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
00671   * @{
00672   */
00673
00674 /**
00675   * @}
00676   */
00677
00678 /* Private functions ---------------------------------------------------------*/
00679 /** @defgroup MMC_Private_Functions MMC Private Functions
00680   * @{
00681   */
00682
00683 /**
00684   * @}
00685   */
00686
00687
00688 /**
00689   * @}
00690   */
00691
00692 /**
00693   * @}
00694   */
00695
00696 /**
00697   * @}
00698   */
00699
00700 #ifdef __cplusplus
00701 }
00702 #endif
00703
00704
00705 #endif /* __STM32H7xx_HAL_MMC_H */
00706
00707 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_mmc_ex.c Source File

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stm32h7xx_hal_mmc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_mmc_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   MMC card Extended HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Secure Digital (MMC) peripheral:
00010   *           + Extended features functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                         ##### How to use this driver #####
00015   ==============================================================================
00016   [..]
00017    The MMC Extension HAL driver can be used as follows:
00018    (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_MMCEx_ConfigDMAMultiBuffer() function.
00019
00020    (+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions.
00021
00022   @endverbatim
00023   ******************************************************************************
00024   * @attention
00025   *
00026   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00027   *
00028   * Redistribution and use in source and binary forms, with or without modification,
00029   * are permitted provided that the following conditions are met:
00030   *   1. Redistributions of source code must retain the above copyright notice,
00031   *      this list of conditions and the following disclaimer.
00032   *   2. Redistributions in binary form must reproduce the above copyright notice,
00033   *      this list of conditions and the following disclaimer in the documentation
00034   *      and/or other materials provided with the distribution.
00035   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00036   *      may be used to endorse or promote products derived from this software
00037   *      without specific prior written permission.
00038   *
00039   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00040   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00041   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00042   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00043   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00044   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00045   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00046   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00047   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00048   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00049   *
00050   ******************************************************************************
00051   */
00052
00053 /* Includes ------------------------------------------------------------------*/
00054 #include "stm32h7xx_hal.h"
00055
00056 /** @addtogroup STM32H7xx_HAL_Driver
00057   * @{
00058   */
00059
00060 /** @defgroup MMCEx MMCEx
00061   * @brief MMC Extended HAL module driver
00062   * @{
00063   */
00064
00065 #ifdef HAL_MMC_MODULE_ENABLED
00066
00067 /* Private typedef -----------------------------------------------------------*/
00068 /* Private define ------------------------------------------------------------*/
00069 /* Private macro -------------------------------------------------------------*/
00070 /* Private variables ---------------------------------------------------------*/
00071 /* Private function prototypes -----------------------------------------------*/
00072 /* Private functions ---------------------------------------------------------*/
00073 /* Exported functions --------------------------------------------------------*/
00074 /** @addtogroup MMCEx_Exported_Functions
00075   * @{
00076   */
00077
00078 /** @addtogroup MMCEx_Exported_Functions_Group1
00079  *  @brief   Multibuffer functions
00080  *
00081 @verbatim
00082   ==============================================================================
00083           ##### Multibuffer functions #####
00084   ==============================================================================
00085   [..]
00086     This section provides functions allowing to configure the multibuffer mode and start read and write
00087     multibuffer mode for MMC HAL driver.
00088
00089 @endverbatim
00090   * @{
00091   */
00092
00093 /**
00094   * @brief  Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA.
00095   * @param  hmmc: MMC handle
00096   * @param  pDataBuffer0: Pointer to the buffer0 that will contain/receive the transfered data
00097   * @param  pDataBuffer1: Pointer to the buffer1 that will contain/receive the transfered data
00098   * @param  BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
00099   * @retval HAL status
00100   */
00101 HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize)
00102 {
00103   if(hmmc->State == HAL_MMC_STATE_READY)
00104   {
00105     hmmc->Instance->IDMABASE0= (uint32_t) pDataBuffer0 ;
00106     hmmc->Instance->IDMABASE1= (uint32_t) pDataBuffer1 ;
00107     hmmc->Instance->IDMABSIZE= (uint32_t) BufferSize;
00108
00109     return HAL_OK;
00110   }
00111   else
00112   {
00113     return HAL_BUSY;
00114   }
00115 }
00116
00117 /**
00118   * @brief  Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1.
00119   *         Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.
00120   * @param  hmmc: MMC handle
00121   * @param  BlockAdd: Block Address from where data is to be read
00122   * @param  NumberOfBlocks: Total number of blocks to read
00123   * @retval HAL status
00124   */
00125 HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
00126 {
00127   SDMMC_DataInitTypeDef config;
00128   uint32_t errorstate = HAL_MMC_ERROR_NONE;
00129
00130   if(hmmc->State == HAL_MMC_STATE_READY)
00131   {
00132     if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
00133     {
00134       hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
00135       return HAL_ERROR;
00136     }
00137
00138     if ((hmmc->Instance->IDMABASE0 == 0) || (hmmc->Instance->IDMABASE1 == 0) || (hmmc->Instance->IDMABSIZE == 0))
00139     {
00140       hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
00141       return HAL_ERROR;
00142     }
00143
00144     /* Initialize data control register */
00145     hmmc->Instance->DCTRL = 0;
00146
00147     hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
00148     hmmc->State = HAL_MMC_STATE_BUSY;
00149
00150     if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
00151     {
00152       BlockAdd *= 512;
00153     }
00154
00155     /* Configure the MMC DPSM (Data Path State Machine) */
00156     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00157     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
00158     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00159     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
00160     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00161     config.DPSM          = SDMMC_DPSM_DISABLE;
00162     SDMMC_ConfigData(hmmc->Instance, &config);
00163
00164     hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
00165
00166     __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
00167
00168     hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
00169
00170      __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
00171
00172     /* Read Blocks in DMA mode */
00173     hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
00174
00175     /* Read Multi Block command */
00176     errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd);
00177     if(errorstate != HAL_MMC_ERROR_NONE)
00178     {
00179       hmmc->State = HAL_MMC_STATE_READY;
00180       hmmc->ErrorCode |= errorstate;
00181       return HAL_ERROR;
00182     }
00183
00184     return HAL_OK;
00185   }
00186   else
00187   {
00188     return HAL_BUSY;
00189   }
00190
00191 }
00192
00193 /**
00194   * @brief  Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1.
00195   *         Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.
00196   * @param  hmmc: MMC handle
00197   * @param  BlockAdd: Block Address from where data is to be read
00198   * @param  NumberOfBlocks: Total number of blocks to read
00199   * @retval HAL status
00200 */
00201 HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
00202 {
00203   SDMMC_DataInitTypeDef config;
00204   uint32_t errorstate = HAL_MMC_ERROR_NONE;
00205
00206   if(hmmc->State == HAL_MMC_STATE_READY)
00207   {
00208     if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
00209     {
00210       hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
00211       return HAL_ERROR;
00212     }
00213
00214     if ((hmmc->Instance->IDMABASE0 == 0) || (hmmc->Instance->IDMABASE1 == 0) || (hmmc->Instance->IDMABSIZE == 0))
00215     {
00216       hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
00217       return HAL_ERROR;
00218     }
00219
00220     /* Initialize data control register */
00221     hmmc->Instance->DCTRL = 0;
00222
00223     hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
00224
00225     hmmc->State = HAL_MMC_STATE_BUSY;
00226
00227     if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
00228     {
00229       BlockAdd *= 512;
00230     }
00231
00232     /* Configure the MMC DPSM (Data Path State Machine) */
00233     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00234     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
00235     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00236     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
00237     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00238     config.DPSM          = SDMMC_DPSM_DISABLE;
00239     SDMMC_ConfigData(hmmc->Instance, &config);
00240
00241     __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
00242
00243     hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
00244
00245     __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
00246
00247     /* Write Blocks in DMA mode */
00248     hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
00249
00250     /* Write Multi Block command */
00251     errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd);
00252     if(errorstate != HAL_MMC_ERROR_NONE)
00253     {
00254       hmmc->State = HAL_MMC_STATE_READY;
00255       hmmc->ErrorCode |= errorstate;
00256       return HAL_ERROR;
00257     }
00258
00259     return HAL_OK;
00260   }
00261   else
00262   {
00263     return HAL_BUSY;
00264   }
00265 }
00266
00267
00268 /**
00269   * @brief  Change the DMA Buffer0 or Buffer1 address on the fly.
00270   * @param  hmmc:           pointer to a MMC_HandleTypeDef structure.
00271   * @param  Buffer:        the buffer to be changed, This parameter can be one of
00272   *                        the following values: MMC_DMA_BUFFER0 or MMC_DMA_BUFFER1
00273   * @param  pDataBuffer:   The new address
00274   * @note   The BUFFER0 address can be changed only when the current transfer use
00275   *         BUFFER1 and the BUFFER1 address can be changed only when the current
00276   *         transfer use BUFFER0.
00277   * @retval HAL status
00278   */
00279 HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
00280 {
00281   if(Buffer == MMC_DMA_BUFFER0)
00282   {
00283     /* change the buffer0 address */
00284     hmmc->Instance->IDMABASE0 = (uint32_t)pDataBuffer;
00285   }
00286   else
00287   {
00288     /* change the memory1 address */
00289     hmmc->Instance->IDMABASE1 = (uint32_t)pDataBuffer;
00290   }
00291
00292   return HAL_OK;
00293 }
00294
00295
00296 /**
00297   * @}
00298   */
00299
00300
00301 /**
00302   * @}
00303   */
00304 #endif /* HAL_MMC_MODULE_ENABLED */
00305 /**
00306   * @}
00307   */
00308
00309 /**
00310   * @}
00311   */
00312
00313 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_mmc_ex.h Source File

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  • Drivers
  • STM32H7xx_HAL_Driver
  • Inc
stm32h7xx_hal_mmc_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_mmc_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of MMC HAL extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_MMC_EX_H
00040 #define __STM32H7xx_HAL_MMC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup MMCEx
00054   * @brief MMC HAL extended module driver
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup MMCEx_Exported_Types MMCEx Exported Types
00060   * @{
00061   */
00062
00063 /** @defgroup MMCEx_Exported_Types_Group1 MMC Internal DMA Buffer structure
00064   * @{
00065   */
00066 typedef enum
00067 {
00068   MMC_DMA_BUFFER0      = 0x00U,    /*!< selects MMC internal DMA Buffer 0     */
00069   MMC_DMA_BUFFER1      = 0x01U,    /*!< selects MMC internal DMA Buffer 1     */
00070
00071 }HAL_MMCEx_DMABuffer_MemoryTypeDef;
00072
00073
00074 /**
00075   * @}
00076   */
00077
00078 /**
00079   * @}
00080   */
00081 /* Exported constants --------------------------------------------------------*/
00082 /* Exported macro ------------------------------------------------------------*/
00083 /* Exported functions --------------------------------------------------------*/
00084 /** @defgroup MMCEx_Exported_Functions MMCEx Exported Functions
00085   * @{
00086   */
00087
00088 /** @defgroup MMCEx_Exported_Functions_Group1 MultiBuffer functions
00089   * @{
00090   */
00091 HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize);
00092 HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00093 HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00094 HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer);
00095
00096 void HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback(MMC_HandleTypeDef *hmmc);
00097 void HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc);
00098 void HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback(MMC_HandleTypeDef *hmmc);
00099 void HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc);
00100
00101 /**
00102   * @}
00103   */
00104
00105 /**
00106   * @}
00107   */
00108
00109 /* Private types -------------------------------------------------------------*/
00110 /* Private defines -----------------------------------------------------------*/
00111 /* Private variables ---------------------------------------------------------*/
00112 /* Private constants ---------------------------------------------------------*/
00113 /* Private macros ------------------------------------------------------------*/
00114 /* Private functions prototypes ----------------------------------------------*/
00115 /* Private functions ---------------------------------------------------------*/
00116
00117 /**
00118   * @}
00119   */
00120
00121 /**
00122   * @}
00123   */
00124 #ifdef __cplusplus
00125 }
00126 #endif
00127
00128
00129 #endif /* __STM32H7xx_HAL_MMCEx_H */
00130
00131 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_nand.c Source File

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  • STM32H7xx_HAL_Driver
  • Src
stm32h7xx_hal_nand.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_nand.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   NAND HAL module driver.
00008   *          This file provides a generic firmware to drive NAND memories mounted
00009   *          as external device.
00010   *
00011   @verbatim
00012   ==============================================================================
00013                          ##### How to use this driver #####
00014   ==============================================================================
00015     [..]
00016       This driver is a generic layered driver which contains a set of APIs used to
00017       control NAND flash memories. It uses the FMC/FSMC layer functions to interface
00018       with NAND devices. This driver is used as follows:
00019
00020       (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
00021           with control and timing parameters for both common and attribute spaces.
00022
00023       (+) Read NAND flash memory maker and device IDs using the function
00024           HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
00025           structure declared by the function caller.
00026
00027       (+) Access NAND flash memory by read/write operations using the functions
00028           HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
00029           HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
00030           HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
00031           HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
00032           to read/write page(s)/spare area(s). These functions use specific device
00033           information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
00034           structure. The read/write address information is contained by the Nand_Address_Typedef
00035           structure passed as parameter.
00036
00037       (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
00038
00039       (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
00040           The erase block address information is contained in the Nand_Address_Typedef
00041           structure passed as parameter.
00042
00043       (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
00044
00045       (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
00046           HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
00047           feature or the function HAL_NAND_GetECC() to get the ECC correction code.
00048
00049       (+) You can monitor the NAND device HAL state by calling the function
00050           HAL_NAND_GetState()
00051
00052     [..]
00053       (@) This driver is a set of generic APIs which handle standard NAND flash operations.
00054           If a NAND flash device contains different operations and/or implementations,
00055           it should be implemented separately.
00056
00057   @endverbatim
00058   ******************************************************************************
00059   * @attention
00060   *
00061   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00062   *
00063   * Redistribution and use in source and binary forms, with or without modification,
00064   * are permitted provided that the following conditions are met:
00065   *   1. Redistributions of source code must retain the above copyright notice,
00066   *      this list of conditions and the following disclaimer.
00067   *   2. Redistributions in binary form must reproduce the above copyright notice,
00068   *      this list of conditions and the following disclaimer in the documentation
00069   *      and/or other materials provided with the distribution.
00070   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00071   *      may be used to endorse or promote products derived from this software
00072   *      without specific prior written permission.
00073   *
00074   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00075   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00076   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00077   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00078   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00079   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00080   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00081   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00082   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00083   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00084   *
00085   ******************************************************************************
00086   */
00087
00088 /* Includes ------------------------------------------------------------------*/
00089 #include "stm32h7xx_hal.h"
00090
00091 /** @addtogroup STM32H7xx_HAL_Driver
00092   * @{
00093   */
00094
00095
00096 #ifdef HAL_NAND_MODULE_ENABLED
00097
00098 /** @defgroup NAND NAND
00099   * @brief NAND HAL module driver
00100   * @{
00101   */
00102
00103 /* Private typedef -----------------------------------------------------------*/
00104 /* Private Constants ------------------------------------------------------------*/
00105 /* Private macro -------------------------------------------------------------*/
00106 /* Private variables ---------------------------------------------------------*/
00107 /* Private function prototypes -----------------------------------------------*/
00108 /* Exported functions ---------------------------------------------------------*/
00109
00110 /** @defgroup NAND_Exported_Functions NAND Exported Functions
00111   * @{
00112   */
00113
00114 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
00115   * @brief    Initialization and Configuration functions
00116   *
00117   @verbatim
00118   ==============================================================================
00119             ##### NAND Initialization and de-initialization functions #####
00120   ==============================================================================
00121   [..]
00122     This section provides functions allowing to initialize/de-initialize
00123     the NAND memory
00124
00125 @endverbatim
00126   * @{
00127   */
00128
00129 /**
00130   * @brief  Perform NAND memory Initialization sequence
00131   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00132   *                the configuration information for NAND module.
00133   * @param  ComSpace_Timing: pointer to Common space timing structure
00134   * @param  AttSpace_Timing: pointer to Attribute space timing structure
00135   * @retval HAL status
00136   */
00137 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
00138 {
00139   /* Check the NAND handle state */
00140   if(hnand == NULL)
00141   {
00142      return HAL_ERROR;
00143   }
00144
00145   if(hnand->State == HAL_NAND_STATE_RESET)
00146   {
00147     /* Allocate lock resource and initialize it */
00148     hnand->Lock = HAL_UNLOCKED;
00149     /* Initialize the low level hardware (MSP) */
00150     HAL_NAND_MspInit(hnand);
00151   }
00152
00153   /* Initialize NAND control Interface */
00154   FMC_NAND_Init(hnand->Instance, &(hnand->Init));
00155
00156   /* Initialize NAND common space timing Interface */
00157   FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
00158
00159   /* Initialize NAND attribute space timing Interface */
00160   FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
00161
00162   /* Enable the NAND device */
00163   __FMC_NAND_ENABLE(hnand->Instance);
00164
00165   /* Enable FMC IP */
00166   __FMC_ENABLE();
00167
00168   /* Update the NAND controller state */
00169   hnand->State = HAL_NAND_STATE_READY;
00170
00171   return HAL_OK;
00172 }
00173
00174 /**
00175   * @brief  Perform NAND memory De-Initialization sequence
00176   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00177   *                the configuration information for NAND module.
00178   * @retval HAL status
00179   */
00180 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
00181 {
00182   /* Initialize the low level hardware (MSP) */
00183   HAL_NAND_MspDeInit(hnand);
00184
00185   /* Configure the NAND registers with their reset values */
00186   FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
00187
00188   /* Reset the NAND controller state */
00189   hnand->State = HAL_NAND_STATE_RESET;
00190
00191   /* Release Lock */
00192   __HAL_UNLOCK(hnand);
00193
00194   return HAL_OK;
00195 }
00196
00197 /**
00198   * @brief  NAND MSP Init
00199   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00200   *                the configuration information for NAND module.
00201   * @retval None
00202   */
00203 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
00204 {
00205   /* Prevent unused argument(s) compilation warning */
00206   UNUSED(hnand);
00207
00208   /* NOTE : This function Should not be modified, when the callback is needed,
00209             the HAL_NAND_MspInit could be implemented in the user file
00210    */
00211 }
00212
00213 /**
00214   * @brief  NAND MSP DeInit
00215   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00216   *                the configuration information for NAND module.
00217   * @retval None
00218   */
00219 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
00220 {
00221   /* Prevent unused argument(s) compilation warning */
00222   UNUSED(hnand);
00223
00224   /* NOTE : This function Should not be modified, when the callback is needed,
00225             the HAL_NAND_MspDeInit could be implemented in the user file
00226    */
00227 }
00228
00229
00230 /**
00231   * @brief  This function handles NAND device interrupt request.
00232   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00233   *                the configuration information for NAND module.
00234   * @retval HAL status
00235 */
00236 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
00237 {
00238   /* Check NAND interrupt Rising edge flag */
00239   if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
00240   {
00241     /* NAND interrupt callback*/
00242     HAL_NAND_ITCallback(hnand);
00243
00244     /* Clear NAND interrupt Rising edge pending bit */
00245     __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);
00246   }
00247
00248   /* Check NAND interrupt Level flag */
00249   if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
00250   {
00251     /* NAND interrupt callback*/
00252     HAL_NAND_ITCallback(hnand);
00253
00254     /* Clear NAND interrupt Level pending bit */
00255     __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);
00256   }
00257
00258   /* Check NAND interrupt Falling edge flag */
00259   if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
00260   {
00261     /* NAND interrupt callback*/
00262     HAL_NAND_ITCallback(hnand);
00263
00264     /* Clear NAND interrupt Falling edge pending bit */
00265     __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);
00266   }
00267
00268   /* Check NAND interrupt FIFO empty flag */
00269   if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
00270   {
00271     /* NAND interrupt callback*/
00272     HAL_NAND_ITCallback(hnand);
00273
00274     /* Clear NAND interrupt FIFO empty pending bit */
00275     __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);
00276   }
00277
00278 }
00279
00280 /**
00281   * @brief  NAND interrupt feature callback
00282   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00283   *                the configuration information for NAND module.
00284   * @retval None
00285   */
00286 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
00287 {
00288   /* Prevent unused argument(s) compilation warning */
00289   UNUSED(hnand);
00290
00291   /* NOTE : This function Should not be modified, when the callback is needed,
00292             the HAL_NAND_ITCallback could be implemented in the user file
00293    */
00294 }
00295
00296 /**
00297   * @}
00298   */
00299
00300 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
00301   * @brief    Input Output and memory control functions
00302   *
00303   @verbatim
00304   ==============================================================================
00305                     ##### NAND Input and Output functions #####
00306   ==============================================================================
00307   [..]
00308     This section provides functions allowing to use and control the NAND
00309     memory
00310
00311 @endverbatim
00312   * @{
00313   */
00314
00315 /**
00316   * @brief  Read the NAND memory electronic signature
00317   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00318   *                the configuration information for NAND module.
00319   * @param  pNAND_ID: NAND ID structure
00320   * @retval HAL status
00321   */
00322 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
00323 {
00324   __IO uint32_t data = 0;
00325   __IO uint32_t data1 = 0;
00326   uint32_t deviceAddress = 0;
00327
00328   /* Process Locked */
00329   __HAL_LOCK(hnand);
00330
00331   /* Check the NAND controller state */
00332   if(hnand->State == HAL_NAND_STATE_BUSY)
00333   {
00334     return HAL_BUSY;
00335   }
00336
00337   /* Identify the device address */
00338   deviceAddress = NAND_DEVICE;
00339
00340   /* Update the NAND controller state */
00341   hnand->State = HAL_NAND_STATE_BUSY;
00342
00343   /* Send Read ID command sequence */
00344   *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA))  = NAND_CMD_READID;
00345   __DSB();
00346   *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00347   __DSB();
00348
00349   /* Read the electronic signature from NAND flash */
00350   if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
00351   {
00352     data = *(__IO uint32_t *)deviceAddress;
00353
00354     /* Return the data read */
00355     pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
00356     pNAND_ID->Device_Id  = ADDR_2ND_CYCLE(data);
00357     pNAND_ID->Third_Id   = ADDR_3RD_CYCLE(data);
00358     pNAND_ID->Fourth_Id  = ADDR_4TH_CYCLE(data);
00359   }
00360   else
00361   {
00362     data = *(__IO uint32_t *)deviceAddress;
00363     data1 = *((__IO uint32_t *)deviceAddress + 4);
00364
00365     /* Return the data read */
00366     pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
00367     pNAND_ID->Device_Id  = ADDR_3RD_CYCLE(data);
00368     pNAND_ID->Third_Id   = ADDR_1ST_CYCLE(data1);
00369     pNAND_ID->Fourth_Id  = ADDR_3RD_CYCLE(data1);
00370   }
00371
00372   /* Update the NAND controller state */
00373   hnand->State = HAL_NAND_STATE_READY;
00374
00375   /* Process unlocked */
00376   __HAL_UNLOCK(hnand);
00377
00378   return HAL_OK;
00379 }
00380
00381 /**
00382   * @brief  NAND memory reset
00383   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00384   *                the configuration information for NAND module.
00385   * @retval HAL status
00386   */
00387 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
00388 {
00389   uint32_t deviceAddress = 0;
00390
00391   /* Process Locked */
00392   __HAL_LOCK(hnand);
00393
00394   /* Check the NAND controller state */
00395   if(hnand->State == HAL_NAND_STATE_BUSY)
00396   {
00397      return HAL_BUSY;
00398   }
00399
00400   /* Identify the device address */
00401   deviceAddress = NAND_DEVICE;
00402
00403   /* Update the NAND controller state */
00404   hnand->State = HAL_NAND_STATE_BUSY;
00405
00406   /* Send NAND reset command */
00407   *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;
00408
00409   /* Update the NAND controller state */
00410   hnand->State = HAL_NAND_STATE_READY;
00411
00412   /* Process unlocked */
00413   __HAL_UNLOCK(hnand);
00414
00415   return HAL_OK;
00416
00417 }
00418
00419 /**
00420   * @brief  Configure the device: Enter the physical parameters of the device
00421   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00422   *                the configuration information for NAND module.
00423   * @param  pDeviceConfig : pointer to NAND_DeviceConfigTypeDef structure
00424   * @retval HAL status
00425   */
00426 HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
00427 {
00428   hnand->Config.PageSize           = pDeviceConfig->PageSize;
00429   hnand->Config.SpareAreaSize      = pDeviceConfig->SpareAreaSize;
00430   hnand->Config.BlockSize          = pDeviceConfig->BlockSize;
00431   hnand->Config.BlockNbr           = pDeviceConfig->BlockNbr;
00432   hnand->Config.PlaneSize          = pDeviceConfig->PlaneSize;
00433   hnand->Config.PlaneNbr           = pDeviceConfig->BlockNbr;
00434   hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
00435
00436   return HAL_OK;
00437 }
00438
00439
00440 /**
00441   * @brief  Read Page(s) from NAND memory block (8-bits addressing)
00442   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00443   *                the configuration information for NAND module.
00444   * @param  pAddress : pointer to NAND address structure
00445   * @param  pBuffer : pointer to destination read buffer
00446   * @param  NumPageToRead : number of pages to read from block
00447   * @retval HAL status
00448   */
00449 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
00450 {
00451   __IO uint32_t index  = 0;
00452   uint32_t tickstart = 0U;
00453   uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;
00454
00455   /* Process Locked */
00456   __HAL_LOCK(hnand);
00457
00458   /* Check the NAND controller state */
00459   if(hnand->State == HAL_NAND_STATE_BUSY)
00460   {
00461      return HAL_BUSY;
00462   }
00463
00464   /* Identify the device address */
00465   deviceAddress = NAND_DEVICE;
00466
00467   /* Update the NAND controller state */
00468   hnand->State = HAL_NAND_STATE_BUSY;
00469
00470   /* NAND raw address calculation */
00471   nandAddress = ARRAY_ADDRESS(pAddress, hnand);
00472
00473   /* Page(s) read loop */
00474   while((NumPageToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
00475   {
00476     /* update the buffer size */
00477     size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
00478
00479     /* Send read page command sequence */
00480     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
00481     __DSB();
00482
00483     /* Cards with page size <= 512 bytes */
00484     if((hnand->Config.PageSize) <= 512)
00485     {
00486       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
00487       {
00488         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00489         __DSB();
00490         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00491         __DSB();
00492         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00493         __DSB();
00494       }
00495       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00496       {
00497         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00498         __DSB();
00499         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00500         __DSB();
00501         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00502         __DSB();
00503         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
00504         __DSB();
00505       }
00506     }
00507     else /* (hnand->Config.PageSize) > 512 */
00508     {
00509       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
00510       {
00511         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00512         __DSB();
00513         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00514         __DSB();
00515         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00516         __DSB();
00517         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00518         __DSB();
00519       }
00520       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00521       {
00522         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00523         __DSB();
00524         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00525         __DSB();
00526         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00527         __DSB();
00528         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00529         __DSB();
00530         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
00531         __DSB();
00532       }
00533     }
00534
00535     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
00536     __DSB();
00537
00538
00539     if(hnand->Config.ExtraCommandEnable == ENABLE)
00540     {
00541       /* Get tick */
00542       tickstart = HAL_GetTick();
00543
00544       /* Read status until NAND is ready */
00545       while(HAL_NAND_Read_Status(hnand) != NAND_READY)
00546       {
00547         if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
00548         {
00549           return HAL_TIMEOUT;
00550         }
00551       }
00552
00553       /* Go back to read mode */
00554       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
00555       __DSB();
00556     }
00557
00558     /* Get Data into Buffer */
00559     for(; index < size; index++)
00560     {
00561       *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
00562     }
00563
00564     /* Increment read pages number */
00565     numPagesRead++;
00566
00567     /* Decrement pages to read */
00568     NumPageToRead--;
00569
00570     /* Increment the NAND address */
00571     nandAddress = (uint32_t)(nandAddress + 1);
00572   }
00573
00574   /* Update the NAND controller state */
00575   hnand->State = HAL_NAND_STATE_READY;
00576
00577   /* Process unlocked */
00578   __HAL_UNLOCK(hnand);
00579
00580   return HAL_OK;
00581
00582 }
00583
00584 /**
00585   * @brief  Read Page(s) from NAND memory block (16-bits addressing)
00586   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00587   *                the configuration information for NAND module.
00588   * @param  pAddress : pointer to NAND address structure
00589   * @param  pBuffer : pointer to destination read buffer. pBuffer should be 16bits aligned
00590   * @param  NumPageToRead : number of pages to read from block
00591   * @retval HAL status
00592   */
00593 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
00594 {
00595   __IO uint32_t index  = 0;
00596   uint32_t tickstart = 0;
00597   uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;
00598
00599   /* Process Locked */
00600   __HAL_LOCK(hnand);
00601
00602   /* Check the NAND controller state */
00603   if(hnand->State == HAL_NAND_STATE_BUSY)
00604   {
00605      return HAL_BUSY;
00606   }
00607
00608   /* Identify the device address */
00609   deviceAddress = NAND_DEVICE;
00610
00611   /* Update the NAND controller state */
00612   hnand->State = HAL_NAND_STATE_BUSY;
00613
00614   /* NAND raw address calculation */
00615   nandAddress = ARRAY_ADDRESS(pAddress, hnand);
00616
00617   /* Page(s) read loop */
00618   while((NumPageToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
00619   {
00620     /* update the buffer size */
00621     size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
00622
00623     /* Send read page command sequence */
00624     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
00625     __DSB();
00626
00627     /* Cards with page size <= 512 bytes */
00628     if((hnand->Config.PageSize) <= 512)
00629     {
00630       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
00631       {
00632         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00633         __DSB();
00634         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00635         __DSB();
00636         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00637         __DSB();
00638       }
00639       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00640       {
00641         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00642         __DSB();
00643         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00644         __DSB();
00645         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00646         __DSB();
00647         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
00648         __DSB();
00649       }
00650     }
00651     else /* (hnand->Config.PageSize) > 512 */
00652     {
00653       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
00654       {
00655         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00656         __DSB();
00657         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00658         __DSB();
00659         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00660         __DSB();
00661         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00662         __DSB();
00663       }
00664       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00665       {
00666         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00667         __DSB();
00668         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00669         __DSB();
00670         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00671         __DSB();
00672         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00673         __DSB();
00674         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
00675         __DSB();
00676       }
00677     }
00678
00679     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
00680     __DSB();
00681
00682     if(hnand->Config.ExtraCommandEnable == ENABLE)
00683     {
00684       /* Get tick */
00685       tickstart = HAL_GetTick();
00686
00687       /* Read status until NAND is ready */
00688       while(HAL_NAND_Read_Status(hnand) != NAND_READY)
00689       {
00690         if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
00691         {
00692           return HAL_TIMEOUT;
00693         }
00694       }
00695
00696       /* Go back to read mode */
00697       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
00698       __DSB();
00699     }
00700
00701     /* Get Data into Buffer */
00702     for(; index < size; index++)
00703     {
00704       *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress;
00705     }
00706
00707     /* Increment read pages number */
00708     numPagesRead++;
00709
00710     /* Decrement pages to read */
00711     NumPageToRead--;
00712
00713     /* Increment the NAND address */
00714     nandAddress = (uint32_t)(nandAddress + 1);
00715   }
00716
00717   /* Update the NAND controller state */
00718   hnand->State = HAL_NAND_STATE_READY;
00719
00720   /* Process unlocked */
00721   __HAL_UNLOCK(hnand);
00722
00723   return HAL_OK;
00724 }
00725
00726 /**
00727   * @brief  Write Page(s) to NAND memory block (8-bits addressing)
00728   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00729   *                the configuration information for NAND module.
00730   * @param  pAddress : pointer to NAND address structure
00731   * @param  pBuffer : pointer to source buffer to write
00732   * @param  NumPageToWrite  : number of pages to write to block
00733   * @retval HAL status
00734   */
00735 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
00736 {
00737   __IO uint32_t index = 0;
00738   uint32_t tickstart = 0;
00739   uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0;
00740
00741   /* Process Locked */
00742   __HAL_LOCK(hnand);
00743
00744   /* Check the NAND controller state */
00745   if(hnand->State == HAL_NAND_STATE_BUSY)
00746   {
00747      return HAL_BUSY;
00748   }
00749
00750   /* Identify the device address */
00751   deviceAddress = NAND_DEVICE;
00752
00753   /* Update the NAND controller state */
00754   hnand->State = HAL_NAND_STATE_BUSY;
00755
00756   /* NAND raw address calculation */
00757   nandAddress = ARRAY_ADDRESS(pAddress, hnand);
00758
00759   /* Page(s) write loop */
00760   while((NumPageToWrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
00761   {
00762     /* update the buffer size */
00763     size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten);
00764
00765     /* Send write page command sequence */
00766     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
00767     __DSB();
00768     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
00769     __DSB();
00770
00771     /* Cards with page size <= 512 bytes */
00772     if((hnand->Config.PageSize) <= 512)
00773     {
00774       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
00775       {
00776         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00777         __DSB();
00778         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00779         __DSB();
00780         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00781         __DSB();
00782       }
00783       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00784       {
00785         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00786         __DSB();
00787         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00788         __DSB();
00789         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00790         __DSB();
00791         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
00792         __DSB();
00793       }
00794     }
00795     else /* (hnand->Config.PageSize) > 512 */
00796     {
00797       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
00798       {
00799         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00800         __DSB();
00801         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00802         __DSB();
00803         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00804         __DSB();
00805         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00806         __DSB();
00807       }
00808       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00809       {
00810         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00811         __DSB();
00812         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00813         __DSB();
00814         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00815         __DSB();
00816         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00817         __DSB();
00818         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
00819         __DSB();
00820       }
00821     }
00822
00823     /* Write data to memory */
00824     for(; index < size; index++)
00825     {
00826       *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
00827       __DSB();
00828     }
00829
00830     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
00831     __DSB();
00832
00833     /* Read status until NAND is ready */
00834     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
00835     {
00836       /* Get tick */
00837       tickstart = HAL_GetTick();
00838
00839       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
00840       {
00841         return HAL_TIMEOUT;
00842       }
00843     }
00844
00845     /* Increment written pages number */
00846     numPagesWritten++;
00847
00848     /* Decrement pages to write */
00849     NumPageToWrite--;
00850
00851     /* Increment the NAND address */
00852     nandAddress = (uint32_t)(nandAddress + 1);
00853   }
00854
00855   /* Update the NAND controller state */
00856   hnand->State = HAL_NAND_STATE_READY;
00857
00858   /* Process unlocked */
00859   __HAL_UNLOCK(hnand);
00860
00861   return HAL_OK;
00862 }
00863
00864 /**
00865   * @brief  Write Page(s) to NAND memory block (16-bits addressing)
00866   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00867   *                the configuration information for NAND module.
00868   * @param  pAddress : pointer to NAND address structure
00869   * @param  pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned
00870   * @param  NumPageToWrite  : number of pages to write to block
00871   * @retval HAL status
00872   */
00873 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
00874 {
00875   __IO uint32_t index = 0;
00876   uint32_t tickstart = 0;
00877   uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0;
00878
00879   /* Process Locked */
00880   __HAL_LOCK(hnand);
00881
00882   /* Check the NAND controller state */
00883   if(hnand->State == HAL_NAND_STATE_BUSY)
00884   {
00885      return HAL_BUSY;
00886   }
00887
00888   /* Identify the device address */
00889   deviceAddress = NAND_DEVICE;
00890
00891   /* Update the NAND controller state */
00892   hnand->State = HAL_NAND_STATE_BUSY;
00893
00894   /* NAND raw address calculation */
00895   nandAddress = ARRAY_ADDRESS(pAddress, hnand);
00896
00897   /* Page(s) write loop */
00898   while((NumPageToWrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
00899   {
00900     /* update the buffer size */
00901     size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten);
00902
00903     /* Send write page command sequence */
00904     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
00905     __DSB();
00906     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
00907     __DSB();
00908
00909     /* Cards with page size <= 512 bytes */
00910     if((hnand->Config.PageSize) <= 512)
00911     {
00912       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
00913       {
00914         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00915         __DSB();
00916         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00917         __DSB();
00918         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00919         __DSB();
00920       }
00921       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00922       {
00923         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00924         __DSB();
00925         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00926         __DSB();
00927         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00928         __DSB();
00929         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
00930         __DSB();
00931       }
00932     }
00933     else /* (hnand->Config.PageSize) > 512 */
00934     {
00935       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
00936       {
00937         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00938         __DSB();
00939         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00940         __DSB();
00941         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00942         __DSB();
00943         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00944         __DSB();
00945       }
00946       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00947       {
00948         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00949         __DSB();
00950         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00951         __DSB();
00952         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00953         __DSB();
00954         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00955         __DSB();
00956         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
00957         __DSB();
00958       }
00959     }
00960
00961     /* Write data to memory */
00962     for(; index < size; index++)
00963     {
00964       *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++;
00965       __DSB();
00966     }
00967
00968     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
00969     __DSB();
00970
00971     /* Read status until NAND is ready */
00972     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
00973     {
00974       /* Get tick */
00975       tickstart = HAL_GetTick();
00976
00977       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
00978       {
00979         return HAL_TIMEOUT;
00980       }
00981     }
00982
00983     /* Increment written pages number */
00984     numPagesWritten++;
00985
00986     /* Decrement pages to write */
00987     NumPageToWrite--;
00988
00989     /* Increment the NAND address */
00990     nandAddress = (uint32_t)(nandAddress + 1);
00991   }
00992
00993   /* Update the NAND controller state */
00994   hnand->State = HAL_NAND_STATE_READY;
00995
00996   /* Process unlocked */
00997   __HAL_UNLOCK(hnand);
00998
00999   return HAL_OK;
01000 }
01001
01002 /**
01003   * @brief  Read Spare area(s) from NAND memory (8-bits addressing)
01004   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01005   *                the configuration information for NAND module.
01006   * @param  pAddress : pointer to NAND address structure
01007   * @param  pBuffer: pointer to source buffer to write
01008   * @param  NumSpareAreaToRead: Number of spare area to read
01009   * @retval HAL status
01010 */
01011 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
01012 {
01013   __IO uint32_t index = 0;
01014   uint32_t tickstart = 0U;
01015   uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0, columnAddress = 0;
01016
01017   /* Process Locked */
01018   __HAL_LOCK(hnand);
01019
01020   /* Check the NAND controller state */
01021   if(hnand->State == HAL_NAND_STATE_BUSY)
01022   {
01023      return HAL_BUSY;
01024   }
01025
01026   /* Identify the device address */
01027   deviceAddress = NAND_DEVICE;
01028
01029   /* Update the NAND controller state */
01030   hnand->State = HAL_NAND_STATE_BUSY;
01031
01032   /* NAND raw address calculation */
01033   nandAddress = ARRAY_ADDRESS(pAddress, hnand);
01034
01035   /* Column in page address */
01036   columnAddress = COLUMN_ADDRESS(hnand);
01037
01038   /* Spare area(s) read loop */
01039   while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01040   {
01041     /* update the buffer size */
01042     size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
01043
01044     /* Cards with page size <= 512 bytes */
01045     if((hnand->Config.PageSize) <= 512)
01046     {
01047       /* Send read spare area command sequence */
01048       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
01049       __DSB();
01050
01051       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
01052       {
01053         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
01054         __DSB();
01055         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01056         __DSB();
01057         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01058         __DSB();
01059       }
01060       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01061       {
01062         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
01063         __DSB();
01064         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01065         __DSB();
01066         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01067         __DSB();
01068         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
01069         __DSB();
01070       }
01071     }
01072     else /* (hnand->Config.PageSize) > 512 */
01073     {
01074       /* Send read spare area command sequence */
01075       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
01076       __DSB();
01077
01078       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
01079       {
01080         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
01081         __DSB();
01082         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
01083         __DSB();
01084         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01085         __DSB();
01086         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01087         __DSB();
01088       }
01089       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01090       {
01091         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
01092         __DSB();
01093         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
01094         __DSB();
01095         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01096         __DSB();
01097         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01098         __DSB();
01099         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
01100         __DSB();
01101       }
01102     }
01103
01104     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
01105     __DSB();
01106
01107     if(hnand->Config.ExtraCommandEnable == ENABLE)
01108     {
01109       /* Get tick */
01110       tickstart = HAL_GetTick();
01111
01112       /* Read status until NAND is ready */
01113       while(HAL_NAND_Read_Status(hnand) != NAND_READY)
01114       {
01115         if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
01116         {
01117           return HAL_TIMEOUT;
01118         }
01119       }
01120
01121       /* Go back to read mode */
01122       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
01123       __DSB();
01124     }
01125
01126     /* Get Data into Buffer */
01127     for(; index < size; index++)
01128     {
01129       *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
01130     }
01131
01132     /* Increment read spare areas number */
01133     numSpareAreaRead++;
01134
01135     /* Decrement spare areas to read */
01136     NumSpareAreaToRead--;
01137
01138     /* Increment the NAND address */
01139     nandAddress = (uint32_t)(nandAddress + 1);
01140   }
01141
01142   /* Update the NAND controller state */
01143   hnand->State = HAL_NAND_STATE_READY;
01144
01145   /* Process unlocked */
01146   __HAL_UNLOCK(hnand);
01147
01148   return HAL_OK;
01149 }
01150
01151 /**
01152   * @brief  Read Spare area(s) from NAND memory (16-bits addressing)
01153   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01154   *                the configuration information for NAND module.
01155   * @param  pAddress : pointer to NAND address structure
01156   * @param  pBuffer: pointer to source buffer to write. pBuffer should be 16bits aligned.
01157   * @param  NumSpareAreaToRead: Number of spare area to read
01158   * @retval HAL status
01159 */
01160 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
01161 {
01162   __IO uint32_t index = 0;
01163   uint32_t tickstart = 0U;
01164   uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0, columnAddress = 0;
01165
01166   /* Process Locked */
01167   __HAL_LOCK(hnand);
01168
01169   /* Check the NAND controller state */
01170   if(hnand->State == HAL_NAND_STATE_BUSY)
01171   {
01172      return HAL_BUSY;
01173   }
01174
01175   /* Identify the device address */
01176   deviceAddress = NAND_DEVICE;
01177
01178   /* Update the NAND controller state */
01179   hnand->State = HAL_NAND_STATE_BUSY;
01180
01181   /* NAND raw address calculation */
01182   nandAddress = ARRAY_ADDRESS(pAddress, hnand);
01183
01184   /* Column in page address */
01185   columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2);
01186
01187   /* Spare area(s) read loop */
01188   while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01189   {
01190     /* update the buffer size */
01191     size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
01192
01193     /* Cards with page size <= 512 bytes */
01194     if((hnand->Config.PageSize) <= 512)
01195     {
01196       /* Send read spare area command sequence */
01197       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
01198       __DSB();
01199
01200       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
01201       {
01202         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
01203         __DSB();
01204         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01205         __DSB();
01206         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01207         __DSB();
01208       }
01209       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01210       {
01211         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
01212         __DSB();
01213         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01214         __DSB();
01215         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01216         __DSB();
01217         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
01218         __DSB();
01219       }
01220     }
01221     else /* (hnand->Config.PageSize) > 512 */
01222     {
01223       /* Send read spare area command sequence */
01224       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
01225       __DSB();
01226
01227       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
01228       {
01229         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
01230         __DSB();
01231         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
01232         __DSB();
01233         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01234         __DSB();
01235         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01236         __DSB();
01237       }
01238       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01239       {
01240         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
01241         __DSB();
01242         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
01243         __DSB();
01244         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01245         __DSB();
01246         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01247         __DSB();
01248         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
01249         __DSB();
01250       }
01251     }
01252
01253     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
01254     __DSB();
01255
01256     if(hnand->Config.ExtraCommandEnable == ENABLE)
01257     {
01258       /* Get tick */
01259       tickstart = HAL_GetTick();
01260
01261       /* Read status until NAND is ready */
01262       while(HAL_NAND_Read_Status(hnand) != NAND_READY)
01263       {
01264         if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
01265         {
01266           return HAL_TIMEOUT;
01267         }
01268       }
01269
01270       /* Go back to read mode */
01271       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
01272       __DSB();
01273     }
01274
01275     /* Get Data into Buffer */
01276     for(; index < size; index++)
01277     {
01278       *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress;
01279     }
01280
01281     /* Increment read spare areas number */
01282     numSpareAreaRead++;
01283
01284     /* Decrement spare areas to read */
01285     NumSpareAreaToRead--;
01286
01287     /* Increment the NAND address */
01288     nandAddress = (uint32_t)(nandAddress + 1);
01289   }
01290
01291   /* Update the NAND controller state */
01292   hnand->State = HAL_NAND_STATE_READY;
01293
01294   /* Process unlocked */
01295   __HAL_UNLOCK(hnand);
01296
01297   return HAL_OK;
01298 }
01299
01300 /**
01301   * @brief  Write Spare area(s) to NAND memory (8-bits addressing)
01302   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01303   *                the configuration information for NAND module.
01304   * @param  pAddress : pointer to NAND address structure
01305   * @param  pBuffer : pointer to source buffer to write
01306   * @param  NumSpareAreaTowrite  : number of spare areas to write to block
01307   * @retval HAL status
01308   */
01309 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
01310 {
01311   __IO uint32_t index = 0;
01312   uint32_t tickstart = 0;
01313   uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0, columnAddress =0;
01314
01315   /* Process Locked */
01316   __HAL_LOCK(hnand);
01317
01318   /* Check the NAND controller state */
01319   if(hnand->State == HAL_NAND_STATE_BUSY)
01320   {
01321      return HAL_BUSY;
01322   }
01323
01324   /* Identify the device address */
01325   deviceAddress = NAND_DEVICE;
01326
01327   /* Update the FMC_NAND controller state */
01328   hnand->State = HAL_NAND_STATE_BUSY;
01329
01330   /* Page address calculation */
01331   nandAddress = ARRAY_ADDRESS(pAddress, hnand);
01332
01333   /* Column in page address */
01334   columnAddress = COLUMN_ADDRESS(hnand);
01335
01336   /* Spare area(s) write loop */
01337   while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01338   {
01339     /* update the buffer size */
01340     size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
01341
01342     /* Cards with page size <= 512 bytes */
01343     if((hnand->Config.PageSize) <= 512)
01344     {
01345       /* Send write Spare area command sequence */
01346       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
01347       __DSB();
01348       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
01349       __DSB();
01350
01351       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
01352       {
01353         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
01354         __DSB();
01355         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01356         __DSB();
01357         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01358         __DSB();
01359       }
01360       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01361       {
01362         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
01363         __DSB();
01364         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01365         __DSB();
01366         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01367         __DSB();
01368         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
01369         __DSB();
01370       }
01371     }
01372     else /* (hnand->Config.PageSize) > 512 */
01373     {
01374       /* Send write Spare area command sequence */
01375       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
01376       __DSB();
01377       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
01378       __DSB();
01379
01380       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
01381       {
01382         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
01383         __DSB();
01384         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
01385         __DSB();
01386         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01387         __DSB();
01388         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01389         __DSB();
01390       }
01391       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01392       {
01393         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
01394         __DSB();
01395         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
01396         __DSB();
01397         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01398         __DSB();
01399         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01400         __DSB();
01401         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
01402         __DSB();
01403       }
01404     }
01405
01406     /* Write data to memory */
01407     for(; index < size; index++)
01408     {
01409       *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
01410       __DSB();
01411     }
01412
01413     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
01414     __DSB();
01415
01416     /* Read status until NAND is ready */
01417     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
01418     {
01419       /* Get tick */
01420       tickstart = HAL_GetTick();
01421
01422       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
01423       {
01424         return HAL_TIMEOUT;
01425       }
01426     }
01427
01428     /* Increment written spare areas number */
01429     numSpareAreaWritten++;
01430
01431     /* Decrement spare areas to write */
01432     NumSpareAreaTowrite--;
01433
01434     /* Increment the NAND address */
01435     nandAddress = (uint32_t)(nandAddress + 1);
01436   }
01437
01438   /* Update the NAND controller state */
01439   hnand->State = HAL_NAND_STATE_READY;
01440
01441   /* Process unlocked */
01442   __HAL_UNLOCK(hnand);
01443
01444   return HAL_OK;
01445 }
01446
01447 /**
01448   * @brief  Write Spare area(s) to NAND memory (16-bits addressing)
01449   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01450   *                the configuration information for NAND module.
01451   * @param  pAddress : pointer to NAND address structure
01452   * @param  pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned.
01453   * @param  NumSpareAreaTowrite  : number of spare areas to write to block
01454   * @retval HAL status
01455   */
01456 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
01457 {
01458   __IO uint32_t index = 0;
01459   uint32_t tickstart = 0;
01460   uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0, columnAddress = 0;
01461
01462   /* Process Locked */
01463   __HAL_LOCK(hnand);
01464
01465   /* Check the NAND controller state */
01466   if(hnand->State == HAL_NAND_STATE_BUSY)
01467   {
01468      return HAL_BUSY;
01469   }
01470
01471   /* Identify the device address */
01472   deviceAddress = NAND_DEVICE;
01473
01474   /* Update the FMC_NAND controller state */
01475   hnand->State = HAL_NAND_STATE_BUSY;
01476
01477   /* NAND raw address calculation */
01478   nandAddress = ARRAY_ADDRESS(pAddress, hnand);
01479
01480   /* Column in page address */
01481   columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2);
01482
01483   /* Spare area(s) write loop */
01484   while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01485   {
01486     /* update the buffer size */
01487     size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
01488
01489     /* Cards with page size <= 512 bytes */
01490     if((hnand->Config.PageSize) <= 512)
01491     {
01492       /* Send write Spare area command sequence */
01493       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
01494       __DSB();
01495       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
01496       __DSB();
01497
01498       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
01499       {
01500         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
01501         __DSB();
01502         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01503         __DSB();
01504         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01505         __DSB();
01506       }
01507       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01508       {
01509         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
01510         __DSB();
01511         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01512         __DSB();
01513         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01514         __DSB();
01515         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
01516         __DSB();
01517       }
01518     }
01519     else /* (hnand->Config.PageSize) > 512 */
01520     {
01521       /* Send write Spare area command sequence */
01522       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
01523       __DSB();
01524       *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
01525       __DSB();
01526
01527       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
01528       {
01529         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
01530         __DSB();
01531         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
01532         __DSB();
01533         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01534         __DSB();
01535         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01536         __DSB();
01537       }
01538       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01539       {
01540         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
01541         __DSB();
01542         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
01543         __DSB();
01544         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
01545         __DSB();
01546         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
01547         __DSB();
01548         *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
01549         __DSB();
01550       }
01551     }
01552
01553     /* Write data to memory */
01554     for(; index < size; index++)
01555     {
01556       *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++;
01557       __DSB();
01558     }
01559
01560     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
01561     __DSB();
01562
01563     /* Read status until NAND is ready */
01564     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
01565     {
01566       /* Get tick */
01567       tickstart = HAL_GetTick();
01568
01569       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
01570       {
01571         return HAL_TIMEOUT;
01572       }
01573     }
01574
01575     /* Increment written spare areas number */
01576     numSpareAreaWritten++;
01577
01578     /* Decrement spare areas to write */
01579     NumSpareAreaTowrite--;
01580
01581     /* Increment the NAND address */
01582     nandAddress = (uint32_t)(nandAddress + 1);
01583   }
01584
01585   /* Update the NAND controller state */
01586   hnand->State = HAL_NAND_STATE_READY;
01587
01588   /* Process unlocked */
01589   __HAL_UNLOCK(hnand);
01590
01591   return HAL_OK;
01592 }
01593
01594 /**
01595   * @brief  NAND memory Block erase
01596   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01597   *                the configuration information for NAND module.
01598   * @param  pAddress : pointer to NAND address structure
01599   * @retval HAL status
01600   */
01601 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
01602 {
01603   uint32_t DeviceAddress = 0;
01604
01605   /* Process Locked */
01606   __HAL_LOCK(hnand);
01607
01608   /* Check the NAND controller state */
01609   if(hnand->State == HAL_NAND_STATE_BUSY)
01610   {
01611      return HAL_BUSY;
01612   }
01613
01614   /* Identify the device address */
01615   DeviceAddress = NAND_DEVICE;
01616
01617   /* Update the NAND controller state */
01618   hnand->State = HAL_NAND_STATE_BUSY;
01619
01620   /* Send Erase block command sequence */
01621   *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;
01622   __DSB();
01623   *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
01624     __DSB();
01625   *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
01626     __DSB();
01627   *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
01628   __DSB();
01629
01630   *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1;
01631   __DSB();
01632
01633   /* Update the NAND controller state */
01634   hnand->State = HAL_NAND_STATE_READY;
01635
01636   /* Process unlocked */
01637   __HAL_UNLOCK(hnand);
01638
01639   return HAL_OK;
01640 }
01641
01642 /**
01643   * @brief  Increment the NAND memory address
01644   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01645   *                the configuration information for NAND module.
01646   * @param pAddress: pointer to NAND address structure
01647   * @retval The new status of the increment address operation. It can be:
01648   *           - NAND_VALID_ADDRESS: When the new address is valid address
01649   *           - NAND_INVALID_ADDRESS: When the new address is invalid address
01650   */
01651 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
01652 {
01653   uint32_t status = NAND_VALID_ADDRESS;
01654
01655   /* Increment page address */
01656   pAddress->Page++;
01657
01658   /* Check NAND address is valid */
01659   if(pAddress->Page == hnand->Config.BlockSize)
01660   {
01661     pAddress->Page = 0;
01662     pAddress->Block++;
01663
01664     if(pAddress->Block == hnand->Config.PlaneSize)
01665     {
01666       pAddress->Block = 0;
01667       pAddress->Plane++;
01668
01669       if(pAddress->Plane == (hnand->Config.PlaneSize/ hnand->Config.BlockNbr))
01670       {
01671         status = NAND_INVALID_ADDRESS;
01672       }
01673     }
01674   }
01675
01676   return (status);
01677 }
01678 /**
01679   * @}
01680   */
01681
01682 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
01683  *  @brief   management functions
01684  *
01685 @verbatim
01686   ==============================================================================
01687                          ##### NAND Control functions #####
01688   ==============================================================================
01689   [..]
01690     This subsection provides a set of functions allowing to control dynamically
01691     the NAND interface.
01692
01693 @endverbatim
01694   * @{
01695   */
01696
01697
01698 /**
01699   * @brief  Enables dynamically NAND ECC feature.
01700   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01701   *                the configuration information for NAND module.
01702   * @retval HAL status
01703   */
01704 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
01705 {
01706   /* Check the NAND controller state */
01707   if(hnand->State == HAL_NAND_STATE_BUSY)
01708   {
01709      return HAL_BUSY;
01710   }
01711
01712   /* Update the NAND state */
01713   hnand->State = HAL_NAND_STATE_BUSY;
01714
01715   /* Enable ECC feature */
01716   FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
01717
01718   /* Update the NAND state */
01719   hnand->State = HAL_NAND_STATE_READY;
01720
01721   return HAL_OK;
01722 }
01723
01724 /**
01725   * @brief  Disables dynamically FMC_NAND ECC feature.
01726   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01727   *                the configuration information for NAND module.
01728   * @retval HAL status
01729   */
01730 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
01731 {
01732   /* Check the NAND controller state */
01733   if(hnand->State == HAL_NAND_STATE_BUSY)
01734   {
01735      return HAL_BUSY;
01736   }
01737
01738   /* Update the NAND state */
01739   hnand->State = HAL_NAND_STATE_BUSY;
01740
01741   /* Disable ECC feature */
01742   FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
01743
01744   /* Update the NAND state */
01745   hnand->State = HAL_NAND_STATE_READY;
01746
01747   return HAL_OK;
01748 }
01749
01750 /**
01751   * @brief  Disables dynamically NAND ECC feature.
01752   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01753   *                the configuration information for NAND module.
01754   * @param  ECCval: pointer to ECC value
01755   * @param  Timeout: maximum timeout to wait
01756   * @retval HAL status
01757   */
01758 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
01759 {
01760   HAL_StatusTypeDef status = HAL_OK;
01761
01762   /* Check the NAND controller state */
01763   if(hnand->State == HAL_NAND_STATE_BUSY)
01764   {
01765      return HAL_BUSY;
01766   }
01767
01768   /* Update the NAND state */
01769   hnand->State = HAL_NAND_STATE_BUSY;
01770
01771   /* Get NAND ECC value */
01772   status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
01773
01774   /* Update the NAND state */
01775   hnand->State = HAL_NAND_STATE_READY;
01776
01777   return status;
01778 }
01779
01780 /**
01781   * @}
01782   */
01783
01784
01785 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
01786  *  @brief   Peripheral State functions
01787  *
01788 @verbatim
01789   ==============================================================================
01790                          ##### NAND State functions #####
01791   ==============================================================================
01792   [..]
01793     This subsection permits to get in run-time the status of the NAND controller
01794     and the data flow.
01795
01796 @endverbatim
01797   * @{
01798   */
01799
01800 /**
01801   * @brief  return the NAND state
01802   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01803   *                the configuration information for NAND module.
01804   * @retval HAL state
01805   */
01806 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
01807 {
01808   return hnand->State;
01809 }
01810
01811 /**
01812   * @brief  NAND memory read status
01813   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01814   *                the configuration information for NAND module.
01815   * @retval NAND status
01816   */
01817 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
01818 {
01819   uint32_t data = 0;
01820   uint32_t DeviceAddress = 0;
01821
01822   /* Identify the device address */
01823    DeviceAddress = NAND_DEVICE;
01824
01825   /* Send Read status operation command */
01826   *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS;
01827
01828   /* Read status register data */
01829   data = *(__IO uint8_t *)DeviceAddress;
01830
01831   /* Return the status */
01832   if((data & NAND_ERROR) == NAND_ERROR)
01833   {
01834     return NAND_ERROR;
01835   }
01836   else if((data & NAND_READY) == NAND_READY)
01837   {
01838     return NAND_READY;
01839   }
01840
01841   return NAND_BUSY;
01842 }
01843
01844 /**
01845   * @}
01846   */
01847
01848 /**
01849   * @}
01850   */
01851
01852 #endif /* HAL_NAND_MODULE_ENABLED  */
01853
01854 /**
01855   * @}
01856   */
01857
01858 /**
01859   * @}
01860   */
01861
01862 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_nand.h Source File

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stm32h7xx_hal_nand.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_nand.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of NAND HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_NAND_H
00040 #define __STM32H7xx_HAL_NAND_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_ll_fmc.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup NAND
00054   * @{
00055   */
00056
00057 /* Exported typedef ----------------------------------------------------------*/
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup NAND_Exported_Types NAND Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  HAL NAND State structures definition
00065   */
00066 typedef enum
00067 {
00068   HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */
00069   HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */
00070   HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */
00071   HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */
00072 }HAL_NAND_StateTypeDef;
00073
00074 /**
00075   * @brief  NAND Memory electronic signature Structure definition
00076   */
00077 typedef struct
00078 {
00079   /*<! NAND memory electronic signature maker and device IDs */
00080
00081   uint8_t Maker_Id;
00082
00083   uint8_t Device_Id;
00084
00085   uint8_t Third_Id;
00086
00087   uint8_t Fourth_Id;
00088 }NAND_IDTypeDef;
00089
00090 /**
00091   * @brief  NAND Memory address Structure definition
00092   */
00093 typedef struct
00094 {
00095   uint16_t Page;   /*!< NAND memory Page address  */
00096
00097   uint16_t Plane;   /*!< NAND memory Zone address  */
00098
00099   uint16_t Block;  /*!< NAND memory Block address */
00100
00101 }NAND_AddressTypeDef;
00102
00103 /**
00104   * @brief  NAND Memory info Structure definition
00105   */
00106 typedef struct
00107 {
00108   uint32_t        PageSize;              /*!< NAND memory page (without spare area) size measured in bytes
00109                                               for 8 bits adressing or words for 16 bits addressing             */
00110
00111   uint32_t        SpareAreaSize;         /*!< NAND memory spare area size measured in bytes
00112                                               for 8 bits adressing or words for 16 bits addressing             */
00113
00114   uint32_t        BlockSize;             /*!< NAND memory block size measured in number of pages               */
00115
00116   uint32_t        BlockNbr;              /*!< NAND memory number of total blocks                               */
00117
00118   uint32_t        PlaneNbr;              /*!< NAND memory number of planes                                     */
00119
00120   uint32_t        PlaneSize;             /*!< NAND memory zone size measured in number of blocks               */
00121
00122   FunctionalState ExtraCommandEnable;    /*!< NAND extra command needed for Page reading mode. This
00123                                               parameter is mandatory for some NAND parts after the read
00124                                               command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
00125                                               Example: Toshiba THTH58BYG3S0HBAI6.
00126                                               This parameter could be ENABLE or DISABLE
00127                                               Please check the Read Mode sequnece in the NAND device datasheet */
00128 }NAND_DeviceConfigTypeDef;
00129
00130 /**
00131   * @brief  NAND handle Structure definition
00132   */
00133 typedef struct
00134 {
00135   FMC_NAND_TypeDef               *Instance;  /*!< Register base address                                 */
00136
00137   FMC_NAND_InitTypeDef           Init;       /*!< NAND device control configuration parameters          */
00138
00139   HAL_LockTypeDef                Lock;       /*!< NAND locking object                                   */
00140
00141   __IO HAL_NAND_StateTypeDef     State;      /*!< NAND device access state                              */
00142
00143   NAND_DeviceConfigTypeDef       Config;     /*!< NAND phusical characteristic information structure    */
00144
00145 }NAND_HandleTypeDef;
00146 /**
00147   * @}
00148   */
00149
00150 /* Exported constants --------------------------------------------------------*/
00151 /* Exported macro ------------------------------------------------------------*/
00152 /** @defgroup NAND_Exported_Macros NAND Exported Macros
00153  * @{
00154  */
00155
00156 /** @brief Reset NAND handle state
00157   * @param  __HANDLE__: specifies the NAND handle.
00158   * @retval None
00159   */
00160 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
00161
00162 /**
00163   * @}
00164   */
00165
00166 /* Exported functions --------------------------------------------------------*/
00167 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
00168   * @{
00169   */
00170
00171 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
00172   * @{
00173   */
00174
00175 /* Initialization/de-initialization functions  ********************************/
00176 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
00177 HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
00178
00179 void               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
00180 void               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
00181 void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
00182 void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
00183
00184 /**
00185   * @}
00186   */
00187
00188 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
00189   * @{
00190   */
00191
00192 /* IO operation functions  ****************************************************/
00193
00194 HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
00195 HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
00196
00197 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
00198
00199 HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
00200 HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
00201 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
00202 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
00203
00204 HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
00205 HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
00206 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
00207 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
00208
00209 HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
00210
00211 uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
00212
00213 /**
00214   * @}
00215   */
00216
00217 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
00218   * @{
00219   */
00220
00221 /* NAND Control functions  ****************************************************/
00222 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
00223 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
00224 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
00225
00226 /**
00227   * @}
00228   */
00229
00230 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
00231   * @{
00232   */
00233 /* NAND State functions *******************************************************/
00234 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
00235 uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
00236 /**
00237   * @}
00238   */
00239
00240 /**
00241   * @}
00242   */
00243 /* Private types -------------------------------------------------------------*/
00244 /* Private variables ---------------------------------------------------------*/
00245 /* Private constants ---------------------------------------------------------*/
00246 /** @defgroup NAND_Private_Constants NAND Private Constants
00247   * @{
00248   */
00249 #define NAND_DEVICE                ((uint32_t)0x80000000U)
00250 #define NAND_WRITE_TIMEOUT         ((uint32_t)0x01000000U)
00251
00252 #define CMD_AREA                   ((uint32_t)(1<<16))  /* A16 = CLE high */
00253 #define ADDR_AREA                  ((uint32_t)(1<<17))  /* A17 = ALE high */
00254
00255 #define NAND_CMD_AREA_A            ((uint8_t)0x00U)
00256 #define NAND_CMD_AREA_B            ((uint8_t)0x01U)
00257 #define NAND_CMD_AREA_C            ((uint8_t)0x50U)
00258 #define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30U)
00259
00260 #define NAND_CMD_WRITE0            ((uint8_t)0x80U)
00261 #define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10U)
00262 #define NAND_CMD_ERASE0            ((uint8_t)0x60U)
00263 #define NAND_CMD_ERASE1            ((uint8_t)0xD0U)
00264 #define NAND_CMD_READID            ((uint8_t)0x90U)
00265 #define NAND_CMD_STATUS            ((uint8_t)0x70U)
00266 #define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7AU)
00267 #define NAND_CMD_RESET             ((uint8_t)0xFFU)
00268
00269 /* NAND memory status */
00270 #define NAND_VALID_ADDRESS         ((uint32_t)0x00000100U)
00271 #define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200U)
00272 #define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400U)
00273 #define NAND_BUSY                  ((uint32_t)0x00000000U)
00274 #define NAND_ERROR                 ((uint32_t)0x00000001U)
00275 #define NAND_READY                 ((uint32_t)0x00000040U)
00276 /**
00277   * @}
00278   */
00279
00280 /* Private macros ------------------------------------------------------------*/
00281 /** @defgroup NAND_Private_Macros NAND Private Macros
00282   * @{
00283   */
00284
00285 /**
00286   * @brief  NAND memory address computation.
00287   * @param  __ADDRESS__: NAND memory address.
00288   * @param  __HANDLE__ : NAND handle.
00289   * @retval NAND Raw address value
00290   */
00291 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
00292                          (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
00293
00294 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
00295
00296 /**
00297   * @brief  NAND memory address cycling.
00298   * @param  __ADDRESS__: NAND memory address.
00299   * @retval NAND address cycling value.
00300   */
00301 #define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
00302 #define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
00303 #define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
00304 #define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
00305
00306 /**
00307   * @brief  NAND memory Columns cycling.
00308   * @param  __ADDRESS__: NAND memory address.
00309   * @retval NAND Column address cycling value.
00310   */
00311 #define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st Column addressing cycle */
00312 #define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd Column addressing cycle */
00313
00314 /**
00315   * @}
00316   */
00317
00318 /**
00319   * @}
00320   */
00321 /**
00322   * @}
00323   */
00324
00325 /**
00326   * @}
00327   */
00328
00329 #ifdef __cplusplus
00330 }
00331 #endif
00332
00333 #endif /* __STM32H7xx_HAL_NAND_H */
00334
00335 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_nor.c Source File

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stm32h7xx_hal_nor.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_nor.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   NOR HAL module driver.
00008   *          This file provides a generic firmware to drive NOR memories mounted
00009   *          as external device.
00010   *
00011   @verbatim
00012   ==============================================================================
00013                      ##### How to use this driver #####
00014   ==============================================================================
00015     [..]
00016       This driver is a generic layered driver which contains a set of APIs used to
00017       control NOR flash memories. It uses the FMC layer functions to interface
00018       with NOR devices. This driver is used as follows:
00019
00020       (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
00021           with control and timing parameters for both normal and extended mode.
00022
00023       (+) Read NOR flash memory manufacturer code and device IDs using the function
00024           HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
00025           structure declared by the function caller.
00026
00027       (+) Access NOR flash memory by read/write data unit operations using the functions
00028           HAL_NOR_Read(), HAL_NOR_Program().
00029
00030       (+) Perform NOR flash erase block/chip operations using the functions
00031           HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
00032
00033       (+) Read the NOR flash CFI (common flash interface) IDs using the function
00034           HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
00035           structure declared by the function caller.
00036
00037       (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
00038           HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
00039
00040       (+) You can monitor the NOR device HAL state by calling the function
00041           HAL_NOR_GetState()
00042     [..]
00043      (@) This driver is a set of generic APIs which handle standard NOR flash operations.
00044          If a NOR flash device contains different operations and/or implementations,
00045          it should be implemented separately.
00046
00047      *** NOR HAL driver macros list ***
00048      =============================================
00049      [..]
00050        Below the list of most used macros in NOR HAL driver.
00051
00052       (+) NOR_WRITE : NOR memory write data to specified address
00053
00054   @endverbatim
00055   ******************************************************************************
00056   * @attention
00057   *
00058   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00059   *
00060   * Redistribution and use in source and binary forms, with or without modification,
00061   * are permitted provided that the following conditions are met:
00062   *   1. Redistributions of source code must retain the above copyright notice,
00063   *      this list of conditions and the following disclaimer.
00064   *   2. Redistributions in binary form must reproduce the above copyright notice,
00065   *      this list of conditions and the following disclaimer in the documentation
00066   *      and/or other materials provided with the distribution.
00067   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00068   *      may be used to endorse or promote products derived from this software
00069   *      without specific prior written permission.
00070   *
00071   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00072   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00073   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00074   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00075   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00076   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00077   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00078   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00079   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00080   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00081   *
00082   ******************************************************************************
00083   */
00084
00085 /* Includes ------------------------------------------------------------------*/
00086 #include "stm32h7xx_hal.h"
00087
00088 /** @addtogroup STM32H7xx_HAL_Driver
00089   * @{
00090   */
00091
00092 /** @defgroup NOR NOR
00093   * @brief NOR driver modules
00094   * @{
00095   */
00096 #ifdef HAL_NOR_MODULE_ENABLED
00097
00098 /* Private typedef -----------------------------------------------------------*/
00099 /* Private define ------------------------------------------------------------*/
00100
00101 /** @defgroup NOR_Private_Defines NOR Private Defines
00102   * @{
00103   */
00104
00105 /* Constants to define address to set to write a command */
00106 #define NOR_CMD_ADDRESS_FIRST                 (uint16_t)0x0555
00107 #define NOR_CMD_ADDRESS_FIRST_CFI             (uint16_t)0x0055
00108 #define NOR_CMD_ADDRESS_SECOND                (uint16_t)0x02AA
00109 #define NOR_CMD_ADDRESS_THIRD                 (uint16_t)0x0555
00110 #define NOR_CMD_ADDRESS_FOURTH                (uint16_t)0x0555
00111 #define NOR_CMD_ADDRESS_FIFTH                 (uint16_t)0x02AA
00112 #define NOR_CMD_ADDRESS_SIXTH                 (uint16_t)0x0555
00113
00114 /* Constants to define data to program a command */
00115 #define NOR_CMD_DATA_READ_RESET               (uint16_t)0x00F0
00116 #define NOR_CMD_DATA_FIRST                    (uint16_t)0x00AA
00117 #define NOR_CMD_DATA_SECOND                   (uint16_t)0x0055
00118 #define NOR_CMD_DATA_AUTO_SELECT              (uint16_t)0x0090
00119 #define NOR_CMD_DATA_PROGRAM                  (uint16_t)0x00A0
00120 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD   (uint16_t)0x0080
00121 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH  (uint16_t)0x00AA
00122 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH   (uint16_t)0x0055
00123 #define NOR_CMD_DATA_CHIP_ERASE               (uint16_t)0x0010
00124 #define NOR_CMD_DATA_CFI                      (uint16_t)0x0098
00125
00126 #define NOR_CMD_DATA_BUFFER_AND_PROG          (uint8_t)0x25
00127 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM  (uint8_t)0x29
00128 #define NOR_CMD_DATA_BLOCK_ERASE              (uint8_t)0x30
00129
00130 /* Mask on NOR STATUS REGISTER */
00131 #define NOR_MASK_STATUS_DQ5                   (uint16_t)0x0020
00132 #define NOR_MASK_STATUS_DQ6                   (uint16_t)0x0040
00133
00134 /**
00135   * @}
00136   */
00137
00138 /* Private macro -------------------------------------------------------------*/
00139 /* Private variables ---------------------------------------------------------*/
00140 /** @defgroup NOR_Private_Variables NOR Private Variables
00141   * @{
00142   */
00143
00144 static uint32_t uwNORMemoryDataWidth  = NOR_MEMORY_8B;
00145
00146 /**
00147   * @}
00148   */
00149
00150 /* Private functions ---------------------------------------------------------*/
00151 /* Exported functions --------------------------------------------------------*/
00152 /** @defgroup NOR_Exported_Functions NOR Exported Functions
00153   * @{
00154   */
00155
00156 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
00157   * @brief    Initialization and Configuration functions
00158   *
00159   @verbatim
00160   ==============================================================================
00161            ##### NOR Initialization and de_initialization functions #####
00162   ==============================================================================
00163   [..]
00164     This section provides functions allowing to initialize/de-initialize
00165     the NOR memory
00166
00167 @endverbatim
00168   * @{
00169   */
00170
00171 /**
00172   * @brief  Perform the NOR memory Initialization sequence
00173   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00174   *                the configuration information for NOR module.
00175   * @param  Timing: pointer to NOR control timing structure
00176   * @param  ExtTiming: pointer to NOR extended mode timing structure
00177   * @retval HAL status
00178   */
00179 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
00180 {
00181   /* Check the NOR handle parameter */
00182   if(hnor == NULL)
00183   {
00184      return HAL_ERROR;
00185   }
00186
00187   if(hnor->State == HAL_NOR_STATE_RESET)
00188   {
00189     /* Allocate lock resource and initialize it */
00190     hnor->Lock = HAL_UNLOCKED;
00191     /* Initialize the low level hardware (MSP) */
00192     HAL_NOR_MspInit(hnor);
00193   }
00194
00195   /* Initialize NOR control Interface */
00196   FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
00197
00198   /* Initialize NOR timing Interface */
00199   FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
00200
00201   /* Initialize NOR extended mode timing Interface */
00202   FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
00203
00204   /* Enable the NORSRAM device */
00205   __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
00206
00207   /* Initialize NOR Memory Data Width*/
00208   if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
00209   {
00210     uwNORMemoryDataWidth = NOR_MEMORY_8B;
00211   }
00212   else
00213   {
00214     uwNORMemoryDataWidth = NOR_MEMORY_16B;
00215   }
00216
00217   /* Enable FMC IP */
00218   __FMC_ENABLE();
00219
00220   /* Check the NOR controller state */
00221   hnor->State = HAL_NOR_STATE_READY;
00222
00223   return HAL_OK;
00224 }
00225
00226 /**
00227   * @brief  Perform NOR memory De-Initialization sequence
00228   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00229   *                the configuration information for NOR module.
00230   * @retval HAL status
00231   */
00232 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
00233 {
00234   /* De-Initialize the low level hardware (MSP) */
00235   HAL_NOR_MspDeInit(hnor);
00236
00237   /* Configure the NOR registers with their reset values */
00238   FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
00239
00240   /* Update the NOR controller state */
00241   hnor->State = HAL_NOR_STATE_RESET;
00242
00243   /* Release Lock */
00244   __HAL_UNLOCK(hnor);
00245
00246   return HAL_OK;
00247 }
00248
00249 /**
00250   * @brief  NOR MSP Init
00251   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00252   *                the configuration information for NOR module.
00253   * @retval None
00254   */
00255 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
00256 {
00257   /* Prevent unused argument(s) compilation warning */
00258   UNUSED(hnor);
00259
00260   /* NOTE : This function Should not be modified, when the callback is needed,
00261             the HAL_NOR_MspInit could be implemented in the user file
00262    */
00263 }
00264
00265 /**
00266   * @brief  NOR MSP DeInit
00267   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00268   *                the configuration information for NOR module.
00269   * @retval None
00270   */
00271 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
00272 {
00273   /* Prevent unused argument(s) compilation warning */
00274   UNUSED(hnor);
00275
00276   /* NOTE : This function Should not be modified, when the callback is needed,
00277             the HAL_NOR_MspDeInit could be implemented in the user file
00278    */
00279 }
00280
00281 /**
00282   * @brief  NOR MSP Wait for Ready/Busy signal
00283   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00284   *                the configuration information for NOR module.
00285   * @param  Timeout: Maximum timeout value
00286   * @retval None
00287   */
00288 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
00289 {
00290   /* Prevent unused argument(s) compilation warning */
00291   UNUSED(hnor);
00292   UNUSED(Timeout);
00293
00294   /* NOTE : This function Should not be modified, when the callback is needed,
00295             the HAL_NOR_MspWait could be implemented in the user file
00296    */
00297 }
00298
00299 /**
00300   * @}
00301   */
00302
00303 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
00304   * @brief    Input Output and memory control functions
00305   *
00306   @verbatim
00307   ==============================================================================
00308                 ##### NOR Input and Output functions #####
00309   ==============================================================================
00310   [..]
00311     This section provides functions allowing to use and control the NOR memory
00312
00313 @endverbatim
00314   * @{
00315   */
00316
00317 /**
00318   * @brief  Read NOR flash IDs
00319   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00320   *                the configuration information for NOR module.
00321   * @param  pNOR_ID : pointer to NOR ID structure
00322   * @retval HAL status
00323   */
00324 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
00325 {
00326   uint32_t deviceaddress = 0;
00327
00328   /* Process Locked */
00329   __HAL_LOCK(hnor);
00330
00331   /* Check the NOR controller state */
00332   if(hnor->State == HAL_NOR_STATE_BUSY)
00333   {
00334      return HAL_BUSY;
00335   }
00336
00337   /* Select the NOR device address */
00338   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00339   {
00340     deviceaddress = NOR_MEMORY_ADRESS1;
00341   }
00342   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00343   {
00344     deviceaddress = NOR_MEMORY_ADRESS2;
00345   }
00346   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00347   {
00348     deviceaddress = NOR_MEMORY_ADRESS3;
00349   }
00350   else /* FMC_NORSRAM_BANK4 */
00351   {
00352     deviceaddress = NOR_MEMORY_ADRESS4;
00353   }
00354
00355   /* Update the NOR controller state */
00356   hnor->State = HAL_NOR_STATE_BUSY;
00357
00358   /* Send read ID command */
00359   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00360   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00361   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
00362
00363   /* Read the NOR IDs */
00364   pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
00365   pNOR_ID->Device_Code1      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
00366   pNOR_ID->Device_Code2      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
00367   pNOR_ID->Device_Code3      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
00368
00369   /* Check the NOR controller state */
00370   hnor->State = HAL_NOR_STATE_READY;
00371
00372   /* Process unlocked */
00373   __HAL_UNLOCK(hnor);
00374
00375   return HAL_OK;
00376 }
00377
00378 /**
00379   * @brief  Returns the NOR memory to Read mode.
00380   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00381   *                the configuration information for NOR module.
00382   * @retval HAL status
00383   */
00384 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
00385 {
00386   uint32_t deviceaddress = 0;
00387
00388   /* Process Locked */
00389   __HAL_LOCK(hnor);
00390
00391   /* Check the NOR controller state */
00392   if(hnor->State == HAL_NOR_STATE_BUSY)
00393   {
00394      return HAL_BUSY;
00395   }
00396
00397   /* Select the NOR device address */
00398   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00399   {
00400     deviceaddress = NOR_MEMORY_ADRESS1;
00401   }
00402   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00403   {
00404     deviceaddress = NOR_MEMORY_ADRESS2;
00405   }
00406   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00407   {
00408     deviceaddress = NOR_MEMORY_ADRESS3;
00409   }
00410   else /* FMC_NORSRAM_BANK4 */
00411   {
00412     deviceaddress = NOR_MEMORY_ADRESS4;
00413   }
00414
00415   NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
00416
00417   /* Check the NOR controller state */
00418   hnor->State = HAL_NOR_STATE_READY;
00419
00420   /* Process unlocked */
00421   __HAL_UNLOCK(hnor);
00422
00423   return HAL_OK;
00424 }
00425
00426 /**
00427   * @brief  Read data from NOR memory
00428   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00429   *                the configuration information for NOR module.
00430   * @param  pAddress: pointer to Device address
00431   * @param  pData : pointer to read data
00432   * @retval HAL status
00433   */
00434 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
00435 {
00436   uint32_t deviceaddress = 0;
00437
00438   /* Process Locked */
00439   __HAL_LOCK(hnor);
00440
00441   /* Check the NOR controller state */
00442   if(hnor->State == HAL_NOR_STATE_BUSY)
00443   {
00444      return HAL_BUSY;
00445   }
00446
00447   /* Select the NOR device address */
00448   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00449   {
00450     deviceaddress = NOR_MEMORY_ADRESS1;
00451   }
00452   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00453   {
00454     deviceaddress = NOR_MEMORY_ADRESS2;
00455   }
00456   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00457   {
00458     deviceaddress = NOR_MEMORY_ADRESS3;
00459   }
00460   else /* FMC_NORSRAM_BANK4 */
00461   {
00462     deviceaddress = NOR_MEMORY_ADRESS4;
00463   }
00464
00465   /* Update the NOR controller state */
00466   hnor->State = HAL_NOR_STATE_BUSY;
00467
00468   /* Send read data command */
00469   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00470   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00471   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
00472
00473   /* Read the data */
00474   *pData = *(__IO uint32_t *)(uint32_t)pAddress;
00475
00476   /* Check the NOR controller state */
00477   hnor->State = HAL_NOR_STATE_READY;
00478
00479   /* Process unlocked */
00480   __HAL_UNLOCK(hnor);
00481
00482   return HAL_OK;
00483 }
00484
00485 /**
00486   * @brief  Program data to NOR memory
00487   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00488   *                the configuration information for NOR module.
00489   * @param  pAddress: Device address
00490   * @param  pData : pointer to the data to write
00491   * @retval HAL status
00492   */
00493 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
00494 {
00495   uint32_t deviceaddress = 0;
00496
00497   /* Process Locked */
00498   __HAL_LOCK(hnor);
00499
00500   /* Check the NOR controller state */
00501   if(hnor->State == HAL_NOR_STATE_BUSY)
00502   {
00503      return HAL_BUSY;
00504   }
00505
00506   /* Select the NOR device address */
00507   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00508   {
00509     deviceaddress = NOR_MEMORY_ADRESS1;
00510   }
00511   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00512   {
00513     deviceaddress = NOR_MEMORY_ADRESS2;
00514   }
00515   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00516   {
00517     deviceaddress = NOR_MEMORY_ADRESS3;
00518   }
00519   else /* FMC_NORSRAM_BANK4 */
00520   {
00521     deviceaddress = NOR_MEMORY_ADRESS4;
00522   }
00523
00524   /* Update the NOR controller state */
00525   hnor->State = HAL_NOR_STATE_BUSY;
00526
00527   /* Send program data command */
00528   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00529   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00530   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
00531
00532   /* Write the data */
00533   NOR_WRITE(pAddress, *pData);
00534
00535   /* Check the NOR controller state */
00536   hnor->State = HAL_NOR_STATE_READY;
00537
00538   /* Process unlocked */
00539   __HAL_UNLOCK(hnor);
00540
00541   return HAL_OK;
00542 }
00543
00544 /**
00545   * @brief  Reads a half-word buffer from the NOR memory.
00546   * @param  hnor: pointer to the NOR handle
00547   * @param  uwAddress: NOR memory internal address to read from.
00548   * @param  pData: pointer to the buffer that receives the data read from the
00549   *         NOR memory.
00550   * @param  uwBufferSize : number of Half word to read.
00551   * @retval HAL status
00552   */
00553 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
00554 {
00555   uint32_t deviceaddress = 0;
00556
00557   /* Process Locked */
00558   __HAL_LOCK(hnor);
00559
00560   /* Check the NOR controller state */
00561   if(hnor->State == HAL_NOR_STATE_BUSY)
00562   {
00563      return HAL_BUSY;
00564   }
00565
00566   /* Select the NOR device address */
00567   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00568   {
00569     deviceaddress = NOR_MEMORY_ADRESS1;
00570   }
00571   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00572   {
00573     deviceaddress = NOR_MEMORY_ADRESS2;
00574   }
00575   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00576   {
00577     deviceaddress = NOR_MEMORY_ADRESS3;
00578   }
00579   else /* FMC_NORSRAM_BANK4 */
00580   {
00581     deviceaddress = NOR_MEMORY_ADRESS4;
00582   }
00583
00584   /* Update the NOR controller state */
00585   hnor->State = HAL_NOR_STATE_BUSY;
00586
00587   /* Send read data command */
00588   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00589   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00590   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
00591
00592   /* Read buffer */
00593   while( uwBufferSize > 0)
00594   {
00595     *pData++ = *(__IO uint16_t *)uwAddress;
00596     uwAddress += 2;
00597     uwBufferSize--;
00598   }
00599
00600   /* Check the NOR controller state */
00601   hnor->State = HAL_NOR_STATE_READY;
00602
00603   /* Process unlocked */
00604   __HAL_UNLOCK(hnor);
00605
00606   return HAL_OK;
00607 }
00608
00609 /**
00610   * @brief  Writes a half-word buffer to the NOR memory. This function must be used
00611             only with S29GL128P NOR memory.
00612   * @param  hnor: pointer to the NOR handle
00613   * @param  uwAddress: NOR memory internal start write address
00614   * @param  pData: pointer to source data buffer.
00615   * @param  uwBufferSize: Size of the buffer to write
00616   * @retval HAL status
00617   */
00618 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
00619 {
00620   uint16_t * p_currentaddress = (uint16_t *)NULL;
00621   uint16_t * p_endaddress = (uint16_t *)NULL;
00622   uint32_t lastloadedaddress = 0, deviceaddress = 0;
00623
00624   /* Process Locked */
00625   __HAL_LOCK(hnor);
00626
00627   /* Check the NOR controller state */
00628   if(hnor->State == HAL_NOR_STATE_BUSY)
00629   {
00630      return HAL_BUSY;
00631   }
00632
00633   /* Select the NOR device address */
00634   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00635   {
00636     deviceaddress = NOR_MEMORY_ADRESS1;
00637   }
00638   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00639   {
00640     deviceaddress = NOR_MEMORY_ADRESS2;
00641   }
00642   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00643   {
00644     deviceaddress = NOR_MEMORY_ADRESS3;
00645   }
00646   else /* FMC_NORSRAM_BANK4 */
00647   {
00648     deviceaddress = NOR_MEMORY_ADRESS4;
00649   }
00650
00651   /* Update the NOR controller state */
00652   hnor->State = HAL_NOR_STATE_BUSY;
00653
00654   /* Initialize variables */
00655   p_currentaddress  = (uint16_t*)((uint32_t)(uwAddress));
00656   p_endaddress      = p_currentaddress + (uwBufferSize-1);
00657   lastloadedaddress = (uint32_t)(uwAddress);
00658
00659   /* Issue unlock command sequence */
00660   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00661   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00662
00663   /* Write Buffer Load Command */
00664   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
00665   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uwBufferSize - 1));
00666
00667   /* Load Data into NOR Buffer */
00668   while(p_currentaddress <= p_endaddress)
00669   {
00670     /* Store last loaded address & data value (for polling) */
00671      lastloadedaddress = (uint32_t)p_currentaddress;
00672
00673     NOR_WRITE(p_currentaddress, *pData++);
00674
00675     p_currentaddress ++;
00676   }
00677
00678   NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
00679
00680   /* Check the NOR controller state */
00681   hnor->State = HAL_NOR_STATE_READY;
00682
00683   /* Process unlocked */
00684   __HAL_UNLOCK(hnor);
00685
00686   return HAL_OK;
00687
00688 }
00689
00690 /**
00691   * @brief  Erase the specified block of the NOR memory
00692   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00693   *                the configuration information for NOR module.
00694   * @param  BlockAddress : Block to erase address
00695   * @param  Address: Device address
00696   * @retval HAL status
00697   */
00698 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
00699 {
00700   uint32_t deviceaddress = 0;
00701
00702   /* Process Locked */
00703   __HAL_LOCK(hnor);
00704
00705   /* Check the NOR controller state */
00706   if(hnor->State == HAL_NOR_STATE_BUSY)
00707   {
00708      return HAL_BUSY;
00709   }
00710
00711   /* Select the NOR device address */
00712   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00713   {
00714     deviceaddress = NOR_MEMORY_ADRESS1;
00715   }
00716   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00717   {
00718     deviceaddress = NOR_MEMORY_ADRESS2;
00719   }
00720   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00721   {
00722     deviceaddress = NOR_MEMORY_ADRESS3;
00723   }
00724   else /* FMC_NORSRAM_BANK4 */
00725   {
00726     deviceaddress = NOR_MEMORY_ADRESS4;
00727   }
00728
00729   /* Update the NOR controller state */
00730   hnor->State = HAL_NOR_STATE_BUSY;
00731
00732   /* Send block erase command sequence */
00733   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00734   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00735   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
00736   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
00737   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
00738   NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
00739
00740   /* Check the NOR memory status and update the controller state */
00741   hnor->State = HAL_NOR_STATE_READY;
00742
00743   /* Process unlocked */
00744   __HAL_UNLOCK(hnor);
00745
00746   return HAL_OK;
00747
00748 }
00749
00750 /**
00751   * @brief  Erase the entire NOR chip.
00752   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00753   *                the configuration information for NOR module.
00754   * @param  Address : Device address
00755   * @retval HAL status
00756   */
00757 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
00758 {
00759   uint32_t deviceaddress = 0;
00760
00761   /* Process Locked */
00762   __HAL_LOCK(hnor);
00763
00764   /* Check the NOR controller state */
00765   if(hnor->State == HAL_NOR_STATE_BUSY)
00766   {
00767      return HAL_BUSY;
00768   }
00769
00770   /* Select the NOR device address */
00771   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00772   {
00773     deviceaddress = NOR_MEMORY_ADRESS1;
00774   }
00775   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00776   {
00777     deviceaddress = NOR_MEMORY_ADRESS2;
00778   }
00779   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00780   {
00781     deviceaddress = NOR_MEMORY_ADRESS3;
00782   }
00783   else /* FMC_NORSRAM_BANK4 */
00784   {
00785     deviceaddress = NOR_MEMORY_ADRESS4;
00786   }
00787
00788   /* Update the NOR controller state */
00789   hnor->State = HAL_NOR_STATE_BUSY;
00790
00791   /* Send NOR chip erase command sequence */
00792   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00793   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00794   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
00795   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
00796   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
00797   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
00798
00799   /* Check the NOR memory status and update the controller state */
00800   hnor->State = HAL_NOR_STATE_READY;
00801
00802   /* Process unlocked */
00803   __HAL_UNLOCK(hnor);
00804
00805   return HAL_OK;
00806 }
00807
00808 /**
00809   * @brief  Read NOR flash CFI IDs
00810   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00811   *                the configuration information for NOR module.
00812   * @param  pNOR_CFI : pointer to NOR CFI IDs structure
00813   * @retval HAL status
00814   */
00815 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
00816 {
00817   uint32_t deviceaddress = 0;
00818
00819   /* Process Locked */
00820   __HAL_LOCK(hnor);
00821
00822   /* Check the NOR controller state */
00823   if(hnor->State == HAL_NOR_STATE_BUSY)
00824   {
00825      return HAL_BUSY;
00826   }
00827
00828   /* Select the NOR device address */
00829   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00830   {
00831     deviceaddress = NOR_MEMORY_ADRESS1;
00832   }
00833   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00834   {
00835     deviceaddress = NOR_MEMORY_ADRESS2;
00836   }
00837   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00838   {
00839     deviceaddress = NOR_MEMORY_ADRESS3;
00840   }
00841   else /* FMC_NORSRAM_BANK4 */
00842   {
00843     deviceaddress = NOR_MEMORY_ADRESS4;
00844   }
00845
00846   /* Update the NOR controller state */
00847   hnor->State = HAL_NOR_STATE_BUSY;
00848
00849   /* Send read CFI query command */
00850   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
00851
00852   /* read the NOR CFI information */
00853   pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
00854   pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
00855   pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
00856   pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
00857
00858   /* Check the NOR controller state */
00859   hnor->State = HAL_NOR_STATE_READY;
00860
00861   /* Process unlocked */
00862   __HAL_UNLOCK(hnor);
00863
00864   return HAL_OK;
00865 }
00866
00867 /**
00868   * @}
00869   */
00870
00871 /** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
00872  *  @brief   management functions
00873  *
00874 @verbatim
00875   ==============================================================================
00876                         ##### NOR Control functions #####
00877   ==============================================================================
00878   [..]
00879     This subsection provides a set of functions allowing to control dynamically
00880     the NOR interface.
00881
00882 @endverbatim
00883   * @{
00884   */
00885
00886 /**
00887   * @brief  Enables dynamically NOR write operation.
00888   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00889   *                the configuration information for NOR module.
00890   * @retval HAL status
00891   */
00892 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
00893 {
00894   /* Process Locked */
00895   __HAL_LOCK(hnor);
00896
00897   /* Enable write operation */
00898   FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
00899
00900   /* Update the NOR controller state */
00901   hnor->State = HAL_NOR_STATE_READY;
00902
00903   /* Process unlocked */
00904   __HAL_UNLOCK(hnor);
00905
00906   return HAL_OK;
00907 }
00908
00909 /**
00910   * @brief  Disables dynamically NOR write operation.
00911   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00912   *                the configuration information for NOR module.
00913   * @retval HAL status
00914   */
00915 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
00916 {
00917   /* Process Locked */
00918   __HAL_LOCK(hnor);
00919
00920   /* Update the SRAM controller state */
00921   hnor->State = HAL_NOR_STATE_BUSY;
00922
00923   /* Disable write operation */
00924   FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
00925
00926   /* Update the NOR controller state */
00927   hnor->State = HAL_NOR_STATE_PROTECTED;
00928
00929   /* Process unlocked */
00930   __HAL_UNLOCK(hnor);
00931
00932   return HAL_OK;
00933 }
00934
00935 /**
00936   * @}
00937   */
00938
00939 /** @defgroup NOR_Exported_Functions_Group4 NOR State functions
00940  *  @brief   Peripheral State functions
00941  *
00942 @verbatim
00943   ==============================================================================
00944                       ##### NOR State functions #####
00945   ==============================================================================
00946   [..]
00947     This subsection permits to get in run-time the status of the NOR controller
00948     and the data flow.
00949
00950 @endverbatim
00951   * @{
00952   */
00953
00954 /**
00955   * @brief  return the NOR controller state
00956   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00957   *                the configuration information for NOR module.
00958   * @retval NOR controller state
00959   */
00960 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
00961 {
00962   return hnor->State;
00963 }
00964
00965 /**
00966   * @brief  Returns the NOR operation status.
00967   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00968   *                the configuration information for NOR module.
00969   * @param  Address: Device address
00970   * @param  Timeout: NOR programming Timeout
00971   * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
00972   *         or HAL_NOR_STATUS_TIMEOUT
00973   */
00974 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
00975 {
00976   HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
00977   uint16_t tmpSR1 = 0, tmpSR2 = 0;
00978   uint32_t tickstart = 0;
00979
00980   /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
00981   HAL_NOR_MspWait(hnor, Timeout);
00982
00983   /* Get the NOR memory operation status -------------------------------------*/
00984
00985   /* Get tick */
00986   tickstart = HAL_GetTick();
00987   while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))
00988   {
00989     /* Check for the Timeout */
00990     if(Timeout != HAL_MAX_DELAY)
00991     {
00992       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00993       {
00994         status = HAL_NOR_STATUS_TIMEOUT;
00995       }
00996     }
00997
00998     /* Read NOR status register (DQ6 and DQ5) */
00999     tmpSR1 = *(__IO uint16_t *)Address;
01000     tmpSR2 = *(__IO uint16_t *)Address;
01001
01002     /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS  */
01003     if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
01004     {
01005       return HAL_NOR_STATUS_SUCCESS ;
01006     }
01007
01008     if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
01009     {
01010       status = HAL_NOR_STATUS_ONGOING;
01011     }
01012
01013     tmpSR1 = *(__IO uint16_t *)Address;
01014     tmpSR2 = *(__IO uint16_t *)Address;
01015
01016     /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS  */
01017     if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
01018     {
01019       return HAL_NOR_STATUS_SUCCESS;
01020     }
01021     if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
01022     {
01023       return HAL_NOR_STATUS_ERROR;
01024     }
01025   }
01026
01027   /* Return the operation status */
01028   return status;
01029 }
01030
01031 /**
01032   * @}
01033   */
01034
01035 /**
01036   * @}
01037   */
01038 #endif /* HAL_NOR_MODULE_ENABLED */
01039 /**
01040   * @}
01041   */
01042
01043 /**
01044   * @}
01045   */
01046
01047 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_nor.h Source File

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stm32h7xx_hal_nor.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_nor.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of NOR HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_NOR_H
00040 #define __STM32H7xx_HAL_NOR_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_ll_fmc.h"
00048
00049
00050 /** @addtogroup STM32H7xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup NOR
00055   * @{
00056   */
00057
00058 /* Exported typedef ----------------------------------------------------------*/
00059 /** @defgroup NOR_Exported_Types NOR Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  HAL SRAM State structures definition
00065   */
00066 typedef enum
00067 {
00068   HAL_NOR_STATE_RESET             = 0x00U,  /*!< NOR not yet initialized or disabled  */
00069   HAL_NOR_STATE_READY             = 0x01U,  /*!< NOR initialized and ready for use    */
00070   HAL_NOR_STATE_BUSY              = 0x02U,  /*!< NOR internal processing is ongoing   */
00071   HAL_NOR_STATE_ERROR             = 0x03U,  /*!< NOR error state                      */
00072   HAL_NOR_STATE_PROTECTED         = 0x04U   /*!< NOR NORSRAM device write protected   */
00073 }HAL_NOR_StateTypeDef;
00074
00075 /**
00076   * @brief  FMC NOR Status typedef
00077   */
00078 typedef enum
00079 {
00080   HAL_NOR_STATUS_SUCCESS  = 0U,
00081   HAL_NOR_STATUS_ONGOING,
00082   HAL_NOR_STATUS_ERROR,
00083   HAL_NOR_STATUS_TIMEOUT
00084 }HAL_NOR_StatusTypeDef;
00085
00086 /**
00087   * @brief  FMC NOR ID typedef
00088   */
00089 typedef struct
00090 {
00091   uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory.       */
00092
00093   uint16_t Device_Code1;
00094
00095   uint16_t Device_Code2;
00096
00097   uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory.
00098                                     These codes can be accessed by performing read operations with specific
00099                                     control signals and addresses set.They can also be accessed by issuing
00100                                     an Auto Select command.                                                   */
00101 }NOR_IDTypeDef;
00102
00103 /**
00104   * @brief  FMC NOR CFI typedef
00105   */
00106 typedef struct
00107 {
00108   /*!< Defines the information stored in the memory's Common flash interface
00109        which contains a description of various electrical and timing parameters,
00110        density information and functions supported by the memory                   */
00111
00112   uint16_t CFI_1;
00113
00114   uint16_t CFI_2;
00115
00116   uint16_t CFI_3;
00117
00118   uint16_t CFI_4;
00119 }NOR_CFITypeDef;
00120
00121 /**
00122   * @brief  NOR handle Structure definition
00123   */
00124 typedef struct
00125 {
00126   FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
00127
00128   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */
00129
00130   FMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */
00131
00132   HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
00133
00134   __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
00135
00136 }NOR_HandleTypeDef;
00137 /**
00138   * @}
00139   */
00140
00141 /* Exported constants --------------------------------------------------------*/
00142 /* Exported macro ------------------------------------------------------------*/
00143 /** @defgroup NOR_Exported_Macros NOR Exported Macros
00144   * @{
00145   */
00146 /** @brief Reset NOR handle state
00147   * @param  __HANDLE__: specifies the NOR handle.
00148   * @retval None
00149   */
00150 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
00151 /**
00152   * @}
00153   */
00154
00155 /* Exported functions --------------------------------------------------------*/
00156 /** @addtogroup NOR_Exported_Functions NOR Exported Functions
00157   * @{
00158   */
00159
00160 /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
00161   * @{
00162   */
00163
00164 /* Initialization/de-initialization functions  ********************************/
00165 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
00166 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
00167 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
00168 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
00169 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
00170 /**
00171   * @}
00172   */
00173
00174 /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
00175   * @{
00176   */
00177
00178 /* I/O operation functions  ***************************************************/
00179 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
00180 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
00181 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
00182 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
00183
00184 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
00185 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
00186
00187 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
00188 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
00189 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
00190 /**
00191   * @}
00192   */
00193
00194 /** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
00195   * @{
00196   */
00197
00198 /* NOR Control functions  *****************************************************/
00199 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
00200 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
00201 /**
00202   * @}
00203   */
00204
00205 /** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
00206   * @{
00207   */
00208
00209 /* NOR State functions ********************************************************/
00210 HAL_NOR_StateTypeDef  HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
00211 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
00212 /**
00213   * @}
00214   */
00215
00216 /**
00217   * @}
00218   */
00219
00220 /* Private types -------------------------------------------------------------*/
00221 /* Private variables ---------------------------------------------------------*/
00222 /* Private constants ---------------------------------------------------------*/
00223 /** @defgroup NOR_Private_Constants NOR Private Constants
00224   * @{
00225   */
00226 /* NOR device IDs addresses */
00227 #define MC_ADDRESS               ((uint16_t)0x0000U)
00228 #define DEVICE_CODE1_ADDR        ((uint16_t)0x0001U)
00229 #define DEVICE_CODE2_ADDR        ((uint16_t)0x000EU)
00230 #define DEVICE_CODE3_ADDR        ((uint16_t)0x000FU)
00231
00232 /* NOR CFI IDs addresses */
00233 #define CFI1_ADDRESS             ((uint16_t)0x61U)
00234 #define CFI2_ADDRESS             ((uint16_t)0x62U)
00235 #define CFI3_ADDRESS             ((uint16_t)0x63U)
00236 #define CFI4_ADDRESS             ((uint16_t)0x64U)
00237
00238 /* NOR operation wait timeout */
00239 #define NOR_TMEOUT               ((uint16_t)0xFFFFU)
00240
00241 /* NOR memory data width */
00242 #define NOR_MEMORY_8B            ((uint8_t)0x0U)
00243 #define NOR_MEMORY_16B           ((uint8_t)0x1U)
00244
00245 /* NOR memory device read/write start address */
00246 #define NOR_MEMORY_ADRESS1       ((uint32_t)0x60000000U)
00247 #define NOR_MEMORY_ADRESS2       ((uint32_t)0x64000000U)
00248 #define NOR_MEMORY_ADRESS3       ((uint32_t)0x68000000U)
00249 #define NOR_MEMORY_ADRESS4       ((uint32_t)0x6C000000U)
00250 /**
00251   * @}
00252   */
00253
00254 /* Private macros ------------------------------------------------------------*/
00255 /** @defgroup NOR_Private_Macros NOR Private Macros
00256   * @{
00257   */
00258 /**
00259   * @brief  NOR memory address shifting.
00260   * @param  __NOR_ADDRESS: NOR base address
00261   * @param  __NOR_MEMORY_WIDTH_: NOR memory width
00262   * @param  __ADDRESS__: NOR memory address
00263   * @retval NOR shifted address value
00264   */
00265 #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)       \
00266             ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?              \
00267               ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))):              \
00268               ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
00269
00270 /**
00271   * @brief  NOR memory write data to specified address.
00272   * @param  __ADDRESS__: NOR memory address
00273   * @param  __DATA__: Data to write
00274   * @retval None
00275   */
00276 #define NOR_WRITE(__ADDRESS__, __DATA__)   do{                                                             \
00277                                                  (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
00278                                                  __DSB();                                                    \
00279                                                } while(0)
00280
00281 /**
00282   * @}
00283   */
00284
00285 /**
00286   * @}
00287   */
00288
00289 /**
00290   * @}
00291   */
00292
00293 #ifdef __cplusplus
00294 }
00295 #endif
00296
00297 #endif /* __STM32H7xx_HAL_NOR_H */
00298
00299 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_opamp.c Source File

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stm32h7xx_hal_opamp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_opamp.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   OPAMP HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the operational amplifier(s) peripheral:
00010   *           + OPAMP configuration
00011   *           + OPAMP calibration
00012   *          Thanks to
00013   *           + Initialization and de-initialization functions
00014   *           + IO operation functions
00015   *           + Peripheral Control functions
00016   *           + Peripheral State functions
00017   *
00018   @verbatim
00019 ================================================================================
00020           ##### OPAMP Peripheral Features #####
00021 ================================================================================
00022
00023   [..] The device integrates 2 operational amplifiers OPAMP1 & OPAMP2
00024
00025        (#) The OPAMP(s) provides several exclusive running modes.
00026        (++) Standalone mode
00027        (++) Programmable Gain Amplifier (PGA) modes
00028        (++) Follower mode
00029
00030        (#) Each OPAMP(s) can be configured in normal and high speed mode.
00031
00032        (#) The OPAMP(s) provide(s) calibration capabilities.
00033        (++) Calibration aims at correcting some offset for running mode.
00034        (++) The OPAMP uses either factory calibration settings OR user defined
00035            calibration (trimming) settings (i.e. trimming mode).
00036        (++) The user defined settings can be figured out using self calibration
00037            handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
00038        (++) HAL_OPAMP_SelfCalibrate:
00039        (+++) Runs automatically the calibration in 2 steps.
00040             (90% of VDDA for NMOS transistors, 10% of VDDA for PMOS transistors).
00041             (As OPAMP is Rail-to-rail input/output, these 2 steps calibration is
00042              appropriate and enough in most cases).
00043        (+++) Runs automatically the calibration.
00044        (+++) Enables the user trimming mode
00045        (+++) Updates the init structure with trimming values with fresh calibration
00046             results.
00047             The user may store the calibration results for larger
00048             (ex monitoring the trimming as a function of temperature
00049             for instance)
00050        (+++) HAL_OPAMPEx_SelfCalibrateAll
00051             runs calibration of all OPAMPs in parallel to save search time.
00052
00053        (#) Running mode: Standalone mode
00054        (++) Gain is set externally (gain depends on external loads).
00055        (++) Follower mode also possible externally by connecting the inverting input to
00056            the output.
00057
00058        (#) Running mode: Follower mode
00059        (++) No Inverting Input is connected.
00060
00061        (#) Running mode: Programmable Gain Amplifier (PGA) mode
00062            (Resistor feedback output)
00063        (#) The OPAMP(s) output(s) can be internally connected to resistor feedback
00064            output.
00065        (#) OPAMP gain can be selected as :
00066
00067       (##) Gain of x2, x4, x8 or x16 for non inverting mode with:
00068       (+++) VREF- referenced.
00069       (+++) Filtering on VINM0, VREF- referenced.
00070       (+++) VINM0 node for bias voltage and VINP0 for input signal.
00071       (+++) VINM0 node for bias voltage and VINP0 for input signal, VINM1 node for filtering.
00072
00073       (##) Gain of x-1, x-3, x-7 or x-15 for inverting mode with:
00074       (+++) VINM0 node for input signal and VINP0 for bias.
00075       (+++) VINM0 node for input signal and VINP0 for bias voltage, VINM1 node for filtering.
00076
00077        (#) The OPAMPs inverting input can be selected according to the Reference Manual
00078            "OPAMP functional description" chapter.
00079
00080        (#) The OPAMPs non inverting input can be selected according to the Reference Manual
00081            "OPAMP functional description" chapter.
00082
00083
00084             ##### How to use this driver #####
00085 ================================================================================
00086   [..]
00087
00088     *** High speed / normal power mode ***
00089     ============================================
00090     [..]  To run in high speed mode:
00091
00092       (#) Configure the OPAMP using HAL_OPAMP_Init() function:
00093       (++) Select OPAMP_POWERMODE_HIGHSPEED
00094       (++) Otherwise select OPAMP_POWERMODE_NORMAL
00095
00096     *** Calibration ***
00097     ============================================
00098     [..]  To run the OPAMP calibration self calibration:
00099
00100       (#) Start calibration using HAL_OPAMP_SelfCalibrate.
00101            Store the calibration results.
00102
00103     *** Running mode ***
00104     ============================================
00105
00106     [..]  To use the OPAMP, perform the following steps:
00107
00108       (#) Fill in the HAL_OPAMP_MspInit() to
00109       (++) Enable the OPAMP Peripheral clock using macro __HAL_RCC_OPAMP_CLK_ENABLE()
00110       (++) Configure the OPAMP input AND output in analog mode using
00111            HAL_GPIO_Init() to map the OPAMP output to the GPIO pin.
00112
00113       (#) Configure the OPAMP using HAL_OPAMP_Init() function:
00114       (++) Select the mode
00115       (++) Select the inverting input
00116       (++) Select the non-inverting input
00117       (++) If PGA mode is enabled, Select if inverting input is connected.
00118       (++) Select either factory or user defined trimming mode.
00119       (++) If the user-defined trimming mode is enabled, select PMOS & NMOS trimming values
00120           (typically values set by HAL_OPAMP_SelfCalibrate function).
00121
00122       (#) Enable the OPAMP using HAL_OPAMP_Start() function.
00123
00124       (#) Disable the OPAMP using HAL_OPAMP_Stop() function.
00125
00126       (#) Lock the OPAMP in running mode using HAL_OPAMP_Lock() function.
00127           Caution: On STM32H7, HAL OPAMP lock is software lock only (not
00128           hardware lock as on some other STM32 devices)
00129
00130       (#) If needed, unlock the OPAMP using HAL_OPAMPEx_Unlock() function.
00131
00132     *** Running mode: change of configuration while OPAMP ON  ***
00133     ============================================
00134     [..] To Re-configure OPAMP when OPAMP is ON (change on the fly)
00135       (#) If needed, fill in the HAL_OPAMP_MspInit()
00136       (++) This is the case for instance if you wish to use new OPAMP I/O
00137
00138       (#) Configure the OPAMP using HAL_OPAMP_Init() function:
00139       (++) As in configure case, select first the parameters you wish to modify.
00140
00141       (#) Change from high speed mode to normal power mode (& vice versa) requires
00142           first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init().
00143           In other words, of OPAMP is ON, HAL_OPAMP_Init can NOT change power mode
00144           alone.
00145
00146   @endverbatim
00147   ******************************************************************************
00148     Table 1.  OPAMPs inverting/non-inverting inputs for the STM32H7 devices:
00149
00150     +------------------------------------------------------------------------|
00151     |                 |         | OPAMP1               | OPAMP2              |
00152     |-----------------|---------|----------------------|---------------------|
00153     | Inverting Input | VM_SEL  |   VINM0-> PC5        |    VINM0-> PE8      |
00154     |                 |         |   VINM1-> PA7        |    VINM1-> PG1      |
00155     |                 |         |   Internal:          |    Internal:        |
00156     |                 |         |     ADC1_IN9         |      OPAMP2_OUT     |
00157     |                 |         |     ADC2_IN9         |     PGA mode        |
00158     |                 |         |     OPAMP1_OUT       |                     |
00159     |                 |         |     PGA mode         |                     |
00160     |-----------------|---------|----------------------|---------------------|
00161     |  Non Inverting  | VP_SEL  |                      |                     |
00162     |                 |         |  VP0 -> PB0 (GPIO)   |  VP0 -> PE9 (GPIO)  |
00163     |                 |         |  Internal:           |  Internal:          |
00164     |    Input        |         |    DAC1_int          |   DAC2_int          |
00165     |                 |         |    ADC1_IN8          |    COMP2_INP        |
00166     |                 |         |    ADC2_IN8          |                     |
00167     |                 |         |    COMP1_INP         |                     |
00168     +------------------------------------------------------------------------|
00169
00170
00171    [..] Table 2.  OPAMPs outputs for the STM32H7 devices:
00172
00173     +-------------------------------------------------------------------------
00174     |                 |        | OPAMP1                | OPAMP2              |
00175     |-----------------|--------|-----------------------|---------------------|
00176     | Output          |  VOUT  |  PC4                  |  PE7                |
00177     |                 |        |  & ADC1_IN4|          | & COMP2_INN7 if     |
00178     |                 |        |    ADC2_IN4           |connected internally |
00179     |                 |        |   COMP1_INN7 if       |                     |
00180     |                 |        |  connected internally |                     |
00181     |-----------------|--------|-----------------------|---------------------|
00182   ******************************************************************************
00183   * @attention
00184   *
00185   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00186   *
00187   * Redistribution and use in source and binary forms, with or without modification,
00188   * are permitted provided that the following conditions are met:
00189   *   1. Redistributions of source code must retain the above copyright notice,
00190   *      this list of conditions and the following disclaimer.
00191   *   2. Redistributions in binary form must reproduce the above copyright notice,
00192   *      this list of conditions and the following disclaimer in the documentation
00193   *      and/or other materials provided with the distribution.
00194   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00195   *      may be used to endorse or promote products derived from this software
00196   *      without specific prior written permission.
00197   *
00198   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00199   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00200   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00201   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00202   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00203   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00204   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00205   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00206   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00207   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00208   *
00209   ******************************************************************************
00210   */
00211
00212 /* Includes ------------------------------------------------------------------*/
00213 #include "stm32h7xx_hal.h"
00214
00215 /** @addtogroup STM32H7xx_HAL_Driver
00216   * @{
00217   */
00218
00219 /** @defgroup OPAMP OPAMP
00220   * @brief OPAMP module driver
00221   * @{
00222   */
00223
00224 #ifdef HAL_OPAMP_MODULE_ENABLED
00225
00226 /* Private types -------------------------------------------------------------*/
00227 /* Private variables ---------------------------------------------------------*/
00228 /* Private constants ---------------------------------------------------------*/
00229 /** @addtogroup OPAMP_Private_Constants
00230   * @{
00231   */
00232
00233 /* CSR register reset value */
00234 #define OPAMP_CSR_RESET_VALUE             ((uint32_t)0x00000000)
00235
00236
00237 #define OPAMP_CSR_RESET_BITS    (OPAMP_CSR_OPAMPxEN | OPAMP_CSR_OPAHSM  | OPAMP_CSR_VMSEL  \
00238                                  | OPAMP_CSR_PGGAIN | OPAMP_CSR_VMSEL | OPAMP_CSR_VPSEL  \
00239                                  | OPAMP_CSR_CALON  | OPAMP_CSR_USERTRIM)
00240 /* CSR Init masks */
00241
00242 #define OPAMP_CSR_INIT_MASK_PGA (OPAMP_CSR_OPAHSM | OPAMP_CSR_VMSEL | OPAMP_CSR_PGGAIN | OPAMP_CSR_PGGAIN  \
00243                                 | OPAMP_CSR_VPSEL | OPAMP_CSR_USERTRIM)
00244
00245
00246 #define OPAMP_CSR_INIT_MASK_FOLLOWER (OPAMP_CSR_OPAHSM | OPAMP_CSR_VMSEL| OPAMP_CSR_VPSEL \
00247                                     | OPAMP_CSR_USERTRIM)
00248
00249
00250 #define OPAMP_CSR_INIT_MASK_STANDALONE (OPAMP_CSR_OPAHSM | OPAMP_CSR_VMSEL | OPAMP_CSR_VPSEL  \
00251                                        | OPAMP_CSR_VMSEL | OPAMP_CSR_USERTRIM)
00252 /**
00253   * @}
00254   */
00255
00256 /* Private macros ------------------------------------------------------------*/
00257 /* Private functions ---------------------------------------------------------*/
00258 /* Exported functions --------------------------------------------------------*/
00259
00260 /** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
00261   * @{
00262   */
00263
00264 /** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
00265  *  @brief    Initialization and Configuration functions
00266  *
00267 @verbatim
00268   ==============================================================================
00269               ##### Initialization and de-initialization functions #####
00270   ==============================================================================
00271
00272 @endverbatim
00273   * @{
00274   */
00275
00276 /**
00277   * @brief  Initialize the OPAMP according to the specified
00278   *         parameters in the OPAMP_InitTypeDef and initialize the associated handle.
00279   * @note   If the selected opamp is locked, initialization can't be performed.
00280   *         To unlock the configuration, perform a system reset.
00281   * @param  hopamp: OPAMP handle
00282   * @retval HAL status
00283   */
00284 HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
00285 {
00286   HAL_StatusTypeDef status = HAL_OK;
00287   uint32_t updateotrlpotr = 0;
00288
00289   /* Check the OPAMP handle allocation and lock status */
00290   /* Init not allowed if calibration is ongoing */
00291   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
00292                       || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
00293   {
00294     return HAL_ERROR;
00295   }
00296   else
00297   {
00298     /* Check the parameter */
00299     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00300
00301     /* Set OPAMP parameters */
00302     assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
00303     assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode));
00304     assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput));
00305
00306     if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE)
00307     {
00308       assert_param(IS_OPAMP_INVERTING_INPUT_STANDALONE(hopamp->Init.InvertingInput));
00309     }
00310
00311     if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)
00312     {
00313       assert_param(IS_OPAMP_PGA_GAIN(hopamp->Init.PgaGain));
00314       assert_param(IS_OPAMP_PGACONNECT(hopamp->Init.PgaConnect));
00315     }
00316
00317
00318     assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming));
00319
00320     if ((hopamp->Init.UserTrimming) == OPAMP_TRIMMING_USER)
00321     {
00322       if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
00323       {
00324         assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueP));
00325         assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueN));
00326       }
00327     else
00328       {
00329         assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValuePHighSpeed));
00330         assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueNHighSpeed));
00331       }
00332     }
00333
00334     if(hopamp->State == HAL_OPAMP_STATE_RESET)
00335     {
00336       /* Allocate lock resource and initialize it */
00337       hopamp->Lock = HAL_UNLOCKED;
00338     }
00339
00340     /* Call MSP init function */
00341     HAL_OPAMP_MspInit(hopamp);
00342
00343     /* Set operating mode */
00344     CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALON);
00345     /* In PGA mode InvertingInput is Not Applicable  */
00346     if (hopamp->Init.Mode == OPAMP_PGA_MODE)
00347     {
00348       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_PGA, \
00349                                         hopamp->Init.PowerMode | \
00350                                         hopamp->Init.Mode | \
00351                                         hopamp->Init.PgaGain | \
00352                                         hopamp->Init.PgaConnect | \
00353                                         hopamp->Init.NonInvertingInput | \
00354                                         hopamp->Init.UserTrimming);
00355     }
00356
00357     if (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE)
00358     {
00359   /* In Follower mode InvertingInput is Not Applicable  */
00360     MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_FOLLOWER, \
00361                                               hopamp->Init.PowerMode | \
00362                                               hopamp->Init.Mode | \
00363                                               hopamp->Init.NonInvertingInput | \
00364                                               hopamp->Init.UserTrimming);
00365     }
00366
00367     if (hopamp->Init.Mode == OPAMP_STANDALONE_MODE)
00368     {
00369       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_STANDALONE, \
00370                                         hopamp->Init.PowerMode | \
00371                                         hopamp->Init.Mode | \
00372                                         hopamp->Init.InvertingInput    | \
00373                                         hopamp->Init.NonInvertingInput | \
00374                                         hopamp->Init.UserTrimming);
00375     }
00376
00377     if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER)
00378     {
00379       /* Set power mode and associated calibration parameters */
00380       if (hopamp->Init.PowerMode != OPAMP_POWERMODE_HIGHSPEED)
00381       {
00382         /* OPAMP_POWERMODE_NORMAL */
00383         /* Set calibration mode (factory or user) and values for            */
00384         /* transistors differential pair high (PMOS) and low (NMOS) for     */
00385         /* normal mode.                                                     */
00386         updateotrlpotr = (((hopamp->Init.TrimmingValueP) << (OPAMP_INPUT_NONINVERTING)) \
00387                          | (hopamp->Init.TrimmingValueN));
00388         MODIFY_REG(hopamp->Instance->OTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr);
00389       }
00390       else
00391       {
00392         /* OPAMP_POWERMODE_HIGHSPEED*/
00393         /* transistors differential pair high (PMOS) and low (NMOS) for     */
00394         /* high speed mode.                                                     */
00395         updateotrlpotr = (((hopamp->Init.TrimmingValuePHighSpeed) << (OPAMP_INPUT_NONINVERTING)) \
00396                          | (hopamp->Init.TrimmingValueNHighSpeed));
00397         MODIFY_REG(hopamp->Instance->HSOTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr);
00398       }
00399     }
00400
00401     /* Update the OPAMP state*/
00402     if (hopamp->State == HAL_OPAMP_STATE_RESET)
00403     {
00404       /* From RESET state to READY State */
00405       hopamp->State = HAL_OPAMP_STATE_READY;
00406     }
00407     /* else: remain in READY or BUSY state (no update) */
00408     return status;
00409   }
00410 }
00411
00412 /**
00413   * @brief  DeInitialize the OPAMP peripheral
00414   * @note   Deinitialization can be performed if the OPAMP configuration is locked.
00415   *         (the lock is SW in H7)
00416   * @param  hopamp: OPAMP handle
00417   * @retval HAL status
00418   */
00419 HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
00420 {
00421   HAL_StatusTypeDef status = HAL_OK;
00422
00423   /* Check the OPAMP handle allocation */
00424   /* DeInit not allowed if calibration is on going */
00425   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
00426   {
00427     status = HAL_ERROR;
00428   }
00429   else
00430   {
00431     /* Check the parameter */
00432     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00433
00434     /* Set OPAMP_CSR register to reset value */
00435     /* OPAMP shall be disabled first separately */
00436
00437     CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00438     MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_RESET_BITS, OPAMP_CSR_RESET_VALUE);
00439
00440     /* DeInit the low level hardware: GPIO, CLOCK and NVIC */
00441     HAL_OPAMP_MspDeInit(hopamp);
00442
00443     /* Update the OPAMP state*/
00444     hopamp->State = HAL_OPAMP_STATE_RESET;
00445     /* Process unlocked */
00446     __HAL_UNLOCK(hopamp);
00447
00448   }
00449
00450   return status;
00451 }
00452
00453
00454 /**
00455   * @brief  Initialize the OPAMP MSP.
00456   * @param  hopamp: OPAMP handle
00457   * @retval None
00458   */
00459 __weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp)
00460 {
00461   /* Prevent unused argument(s) compilation warning */
00462   UNUSED(hopamp);
00463
00464   /* NOTE : This function should not be modified, when the callback is needed,
00465             the function "HAL_OPAMP_MspInit()" must be implemented in the user file.
00466    */
00467 }
00468
00469 /**
00470   * @brief  DeInitialize OPAMP MSP.
00471   * @param  hopamp: OPAMP handle
00472   * @retval None
00473   */
00474 __weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp)
00475 {
00476   /* Prevent unused argument(s) compilation warning */
00477   UNUSED(hopamp);
00478   /* NOTE : This function should not be modified, when the callback is needed,
00479             the function "HAL_OPAMP_MspDeInit()" must be implemented in the user file.
00480    */
00481 }
00482
00483 /**
00484   * @}
00485   */
00486
00487
00488 /** @defgroup OPAMP_Exported_Functions_Group2 IO operation functions
00489  *  @brief   IO operation functions
00490  *
00491 @verbatim
00492  ===============================================================================
00493                         ##### IO operation functions #####
00494  ===============================================================================
00495     [..]
00496     This subsection provides a set of functions allowing to manage the OPAMP
00497     start, stop and calibration actions.
00498
00499 @endverbatim
00500   * @{
00501   */
00502
00503 /**
00504   * @brief  Start the OPAMP.
00505   * @param  hopamp: OPAMP handle
00506   * @retval HAL status
00507   */
00508
00509 HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp)
00510 {
00511   HAL_StatusTypeDef status = HAL_OK;
00512
00513   /* Check the OPAMP handle allocation */
00514   /* Check if OPAMP locked */
00515   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
00516   {
00517     status = HAL_ERROR;
00518   }
00519   else
00520   {
00521     /* Check the parameter */
00522     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00523
00524     if(hopamp->State == HAL_OPAMP_STATE_READY)
00525     {
00526       /* Enable the selected opamp */
00527       SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00528
00529       /* Update the OPAMP state*/
00530       /* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */
00531       hopamp->State = HAL_OPAMP_STATE_BUSY;
00532     }
00533     else
00534     {
00535       status = HAL_ERROR;
00536     }
00537
00538    }
00539   return status;
00540 }
00541
00542 /**
00543   * @brief  Stop the OPAMP.
00544   * @param  hopamp: OPAMP handle
00545   * @retval HAL status
00546   */
00547 HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp)
00548 {
00549   HAL_StatusTypeDef status = HAL_OK;
00550
00551   /* Check the OPAMP handle allocation */
00552   /* Check if OPAMP locked */
00553   /* Check if OPAMP calibration ongoing */
00554   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \
00555                       || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
00556   {
00557     status = HAL_ERROR;
00558   }
00559   else
00560   {
00561     /* Check the parameter */
00562     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00563
00564     if(hopamp->State == HAL_OPAMP_STATE_BUSY)
00565     {
00566       /* Disable the selected opamp */
00567       CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00568
00569       /* Update the OPAMP state*/
00570       /* From  HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/
00571       hopamp->State = HAL_OPAMP_STATE_READY;
00572     }
00573     else
00574     {
00575       status = HAL_ERROR;
00576     }
00577   }
00578   return status;
00579 }
00580
00581 /**
00582   * @brief  Run the self calibration of one OPAMP.
00583   * @note   Calibration is performed in the mode specified in OPAMP init
00584   *         structure (mode normal or high-speed). To perform calibration for
00585   *         both modes, repeat this function twice after OPAMP init structure
00586   *         accordingly updated.
00587   * @param  hopamp handle
00588   * @retval Updated offset trimming values (PMOS & NMOS), user trimming is enabled
00589   * @retval HAL status
00590   */
00591
00592 HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
00593 {
00594
00595   HAL_StatusTypeDef status = HAL_OK;
00596
00597   uint32_t trimmingvaluen = 0;
00598   uint32_t trimmingvaluep = 0;
00599   uint32_t delta;
00600   uint32_t opampmode;
00601
00602   __IO uint32_t* tmp_opamp_reg_trimming;   /* Selection of register of trimming depending on power mode: OTR or HSOTR */
00603
00604   /* Check the OPAMP handle allocation */
00605   /* Check if OPAMP locked */
00606   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
00607   {
00608     status = HAL_ERROR;
00609   }
00610   else
00611   {
00612
00613     /* Check if OPAMP in calibration mode and calibration not yet enable */
00614     if(hopamp->State ==  HAL_OPAMP_STATE_READY)
00615     {
00616       /* Check the parameter */
00617       assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00618       assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
00619
00620       opampmode = READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_VMSEL);
00621
00622       /* Use of standalone mode */
00623       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_VMSEL, OPAMP_STANDALONE_MODE);
00624       /*  user trimming values are used for offset calibration */
00625       SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
00626
00627       /* Select trimming settings depending on power mode */
00628       if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
00629       {
00630         tmp_opamp_reg_trimming = &hopamp->Instance->OTR;
00631
00632       }
00633       else
00634       {
00635         /* high speed Mode */
00636         tmp_opamp_reg_trimming = &hopamp->Instance->HSOTR;
00637       }
00638
00639
00640       /* Enable calibration */
00641       SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
00642
00643       /* Force internal reference on VP */
00644       SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_FORCEVP);
00645
00646       /* 1st calibration - N */
00647       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
00648
00649       /* Enable the selected opamp */
00650       SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00651
00652       /* Init trimming counter */
00653       /* Medium value */
00654       trimmingvaluen = 16;
00655       delta = 8;
00656
00657       while (delta != 0)
00658       {
00659         /* Set candidate trimming */
00660         /* OPAMP_POWERMODE_NORMAL */
00661         MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
00662
00663         /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00664         /* Offset trim time: during calibration, minimum time needed between */
00665         /* two steps to have 1 mV accuracy */
00666         HAL_Delay(OPAMP_TRIMMING_DELAY);
00667
00668         if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != RESET)
00669         {
00670           /* OPAMP_CSR_CALOUT is HIGH try higher trimming */
00671           trimmingvaluen += delta;
00672         }
00673         else
00674         {
00675           /* OPAMP_CSR_CALOUT is LOW try lower trimming */
00676           trimmingvaluen -= delta;
00677         }
00678         /* Divide range by 2 to continue dichotomy sweep */
00679         delta >>= 1;
00680       }
00681
00682       /* Still need to check if right calibration is current value or one step below */
00683       /* Indeed the first value that causes the OUTCAL bit to change from 1  to 0  */
00684
00685       MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
00686
00687       /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00688       /* Offset trim time: during calibration, minimum time needed between */
00689       /* two steps to have 1 mV accuracy */
00690       HAL_Delay(OPAMP_TRIMMING_DELAY);
00691
00692       if ((READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT)) != 0)
00693       {
00694         /* Trimming value is actually one value more */
00695         trimmingvaluen++;
00696         /* Set right trimming */
00697         MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
00698       }
00699
00700       /* 2nd calibration - P */
00701       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
00702
00703       /* Init trimming counter */
00704       /* Medium value */
00705       trimmingvaluep = 16;
00706       delta = 8;
00707
00708       while (delta != 0)
00709       {
00710         /* Set candidate trimming */
00711         /* OPAMP_POWERMODE_NORMAL */
00712         MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<<OPAMP_INPUT_NONINVERTING));
00713
00714         /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00715         /* Offset trim time: during calibration, minimum time needed between */
00716         /* two steps to have 1 mV accuracy */
00717         HAL_Delay(OPAMP_TRIMMING_DELAY);
00718
00719         if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT)!= RESET)
00720         {
00721           /* OPAMP_CSR_CALOUT is HIGH try higher trimming */
00722           trimmingvaluep += delta;
00723         }
00724         else
00725         {
00726           /* OPAMP_CSR_CALOUT  is LOW try lower trimming */
00727           trimmingvaluep -= delta;
00728         }
00729
00730         /* Divide range by 2 to continue dichotomy sweep */
00731         delta >>= 1;
00732       }
00733
00734       /* Still need to check if right calibration is current value or one step below */
00735       /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0  */
00736       /* Set candidate trimming */
00737       MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<<OPAMP_INPUT_NONINVERTING));
00738
00739       /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00740       /* Offset trim time: during calibration, minimum time needed between */
00741       /* two steps to have 1 mV accuracy */
00742       HAL_Delay(OPAMP_TRIMMING_DELAY);
00743
00744       if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != RESET)
00745       {
00746         /* Trimming value is actually one value more */
00747         trimmingvaluep++;
00748         MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<<OPAMP_INPUT_NONINVERTING));
00749       }
00750
00751       /* Disable calibration & set normal mode (operating mode) */
00752       CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
00753
00754       /* Disable the OPAMP */
00755       CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00756
00757       /* Set operating mode back */
00758       CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_FORCEVP);
00759
00760       /* Self calibration is successful  */
00761       /* Store calibration(user trimming) results in init structure. */
00762
00763       /* Set user trimming mode */
00764       hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER;
00765
00766       /* Affect calibration parameters depending on mode normal/high speed */
00767       if (hopamp->Init.PowerMode != OPAMP_POWERMODE_HIGHSPEED)
00768       {
00769         /* Write calibration result N */
00770         hopamp->Init.TrimmingValueN = trimmingvaluen;
00771         /* Write calibration result P */
00772         hopamp->Init.TrimmingValueP = trimmingvaluep;
00773       }
00774       else
00775       {
00776         /* Write calibration result N */
00777         hopamp->Init.TrimmingValueNHighSpeed = trimmingvaluen;
00778         /* Write calibration result P */
00779         hopamp->Init.TrimmingValuePHighSpeed = trimmingvaluep;
00780       }
00781     /* Restore OPAMP mode after calibration */
00782     MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_VMSEL, opampmode);
00783     }
00784
00785     else
00786     {
00787       /* OPAMP can not be calibrated from this mode */
00788       status = HAL_ERROR;
00789     }
00790   }
00791   return status;
00792 }
00793
00794 /**
00795   * @}
00796   */
00797
00798 /** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions
00799  *  @brief   Peripheral Control functions
00800  *
00801 @verbatim
00802  ===============================================================================
00803                       ##### Peripheral Control functions #####
00804  ===============================================================================
00805     [..]
00806     This subsection provides a set of functions allowing to control the OPAMP data
00807     transfers.
00808
00809
00810
00811 @endverbatim
00812   * @{
00813   */
00814
00815 /**
00816   * @brief  Lock the selected OPAMP configuration.
00817   * @note   On STM32H7, HAL OPAMP lock is software lock only (in
00818   *         contrast of hardware lock available on some other STM32
00819   *         devices)
00820   * @param  hopamp: OPAMP handle
00821   * @retval HAL status
00822   */
00823 HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp)
00824 {
00825   HAL_StatusTypeDef status = HAL_OK;
00826
00827   /* Check the OPAMP handle allocation */
00828   /* Check if OPAMP locked */
00829   /* OPAMP can be locked when enabled and running in normal mode */
00830   /*   It is meaningless otherwise */
00831   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \
00832                       || (hopamp->State == HAL_OPAMP_STATE_READY) \
00833                       || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\
00834                       || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
00835
00836   {
00837     status = HAL_ERROR;
00838   }
00839
00840   else
00841   {
00842     /* Check the parameter */
00843     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00844
00845    /* OPAMP state changed to locked */
00846     hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED;
00847   }
00848   return status;
00849 }
00850
00851 /**
00852   * @brief  Return the OPAMP factory trimming value.
00853   * @note            On STM32H7 OPAMP, user can retrieve factory trimming if
00854   *                  OPAMP has never been set to user trimming before.
00855   *                  Therefore, this function must be called when OPAMP init
00856   *                  parameter "UserTrimming" is set to trimming factory,
00857   *                  and before OPAMP  calibration (function
00858   *                  "HAL_OPAMP_SelfCalibrate()").
00859   *                  Otherwise, factory trimming value cannot be retrieved and
00860   *                  error status is returned.
00861   * @param  hopamp : OPAMP handle
00862   * @param  trimmingoffset : Trimming offset (P or N)
00863   *         This parameter must be a value of @ref OPAMP_FactoryTrimming
00864   * @note   Calibration parameter retrieved is corresponding to the mode
00865   *         specified in OPAMP init structure (mode normal or high-speed).
00866   *         To retrieve calibration parameters for both modes, repeat this
00867   *         function after OPAMP init structure accordingly updated.
00868   * @retval Trimming value (P or N): range: 0->31
00869   *         or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available
00870   *
00871   */
00872
00873 HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
00874 {
00875   HAL_OPAMP_TrimmingValueTypeDef trimmingvalue;
00876   __IO uint32_t* tmp_opamp_reg_trimming;  /* Selection of register of trimming depending on power mode: OTR or LPOTR */
00877
00878   /* Check the OPAMP handle allocation */
00879   /* Value can be retrieved in HAL_OPAMP_STATE_READY state */
00880   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \
00881                       || (hopamp->State == HAL_OPAMP_STATE_BUSY) \
00882                       || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\
00883                       || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
00884   {
00885     return OPAMP_FACTORYTRIMMING_DUMMY;
00886   }
00887   else
00888   {
00889     /* Check the parameter */
00890     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00891     assert_param(IS_OPAMP_FACTORYTRIMMING(trimmingoffset));
00892     assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
00893
00894     /* Check the trimming mode */
00895     if (READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_USERTRIM)!= RESET)
00896     {
00897       /* This function must called when OPAMP init parameter "UserTrimming"   */
00898       /* is set to trimming factory, and before OPAMP calibration (function   */
00899       /* "HAL_OPAMP_SelfCalibrate()").                                        */
00900       /* Otherwise, factory trimming value cannot be retrieved and error       */
00901       /* status is returned.                                                  */
00902       trimmingvalue = OPAMP_FACTORYTRIMMING_DUMMY;
00903     }
00904     else
00905     {
00906       /* Select trimming settings depending on power mode */
00907       if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
00908       {
00909         tmp_opamp_reg_trimming = &hopamp->Instance->OTR;
00910       }
00911       else
00912       {
00913         tmp_opamp_reg_trimming = &hopamp->Instance->HSOTR;
00914       }
00915
00916       /* Get factory trimming  */
00917       if (trimmingoffset == OPAMP_FACTORYTRIMMING_P)
00918       {
00919         /* OPAMP_FACTORYTRIMMING_P */
00920         trimmingvalue = ((*tmp_opamp_reg_trimming) & OPAMP_OTR_TRIMOFFSETP) >> OPAMP_INPUT_NONINVERTING;
00921       }
00922       else
00923       {
00924         /* OPAMP_FACTORYTRIMMING_N */
00925         trimmingvalue = (*tmp_opamp_reg_trimming) & OPAMP_OTR_TRIMOFFSETN;
00926       }
00927     }
00928   }
00929   return trimmingvalue;
00930 }
00931
00932 /**
00933   * @}
00934   */
00935
00936
00937 /** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions
00938  *  @brief   Peripheral State functions
00939  *
00940 @verbatim
00941  ===============================================================================
00942                       ##### Peripheral State functions #####
00943  ===============================================================================
00944     [..]
00945     This subsection permits to get in run-time the status of the peripheral.
00946
00947 @endverbatim
00948   * @{
00949   */
00950
00951 /**
00952   * @brief  Return the OPAMP handle state.
00953   * @param  hopamp : OPAMP handle
00954   * @retval HAL state
00955   */
00956 HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp)
00957 {
00958   /* Check the OPAMP handle allocation */
00959   if(hopamp == NULL)
00960   {
00961     return HAL_OPAMP_STATE_RESET;
00962   }
00963
00964   /* Check the parameter */
00965   assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00966
00967  /* Return OPAMP handle state */
00968   return hopamp->State;
00969 }
00970
00971 /**
00972   * @}
00973   */
00974
00975 /**
00976   * @}
00977   */
00978
00979   /**
00980   * @}
00981   */
00982
00983 #endif /* HAL_OPAMP_MODULE_ENABLED */
00984 /**
00985   * @}
00986   */
00987
00988 /**
00989   * @}
00990   */
00991
00992 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_opamp.h Source File

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stm32h7xx_hal_opamp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_opamp.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of OPAMP HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_OPAMP_H
00040 #define __STM32H7xx_HAL_OPAMP_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup OPAMP
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup OPAMP_Exported_Types OPAMP Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  OPAMP Init structure definition
00065   */
00066
00067 typedef struct
00068 {
00069
00070   uint32_t PowerMode;                   /*!< Specifies the power mode Normal or High Speed.
00071                                              This parameter must be a value of @ref OPAMP_PowerMode */
00072
00073   uint32_t Mode;                        /*!< Specifies the OPAMP mode
00074                                              This parameter must be a value of @ref OPAMP_Mode
00075                                              mode is either Standalone, - Follower or PGA */
00076
00077   uint32_t InvertingInput;              /*!< Specifies the inverting input in Standalone & PGA modes
00078                                              - In Standalone mode i.e when mode is OPAMP_STANDALONE_MODE
00079                                                  This parameter must be a value of @ref OPAMP_InvertingInput
00080                                              - In Follower mode i.e when mode is OPAMP_FOLLOWER_MODE
00081                                            & In PGA mode i.e when mode is OPAMP_PGA_MODE
00082                                                  This parameter is Not Applicable */
00083
00084   uint32_t NonInvertingInput;           /*!< Specifies the non inverting input of the opamp:
00085                                              This parameter must be a value of @ref OPAMP_NonInvertingInput */
00086
00087   uint32_t PgaGain;                     /*!< Specifies the gain in PGA mode
00088                                              i.e. when mode is OPAMP_PGA_MODE.
00089                                              This parameter must be a value of @ref OPAMP_PgaGain */
00090
00091   uint32_t PgaConnect;                  /*!< Specifies the inverting pin in PGA mode
00092                                              i.e. when mode is OPAMP_PGA_MODE
00093                                              This parameter must be a value of @ref OPAMP_PgaConnect
00094                                              Either: not connected, connected to VINM0, connected to VINM1
00095                                              (VINM0 or VINM1 are typically used for external filtering) */
00096
00097   uint32_t UserTrimming;                /*!< Specifies the trimming mode
00098                                              This parameter must be a value of @ref OPAMP_UserTrimming
00099                                              UserTrimming is either factory or user trimming.*/
00100
00101   uint32_t TrimmingValueP;              /*!< Specifies the offset trimming value (PMOS) in Normal Mode
00102
00103                                              i.e. when UserTrimming is OPAMP_TRIMMING_USER.
00104                                              This parameter must be a number between Min_Data = 0 and Max_Data = 31.
00105                                              16 is typical default value */
00106
00107   uint32_t TrimmingValueN;              /*!< Specifies the offset trimming value (NMOS) in Normal Mode
00108                                              i.e. when UserTrimming is OPAMP_TRIMMING_USER.
00109                                              This parameter must be a number between Min_Data = 0 and Max_Data = 31.
00110                                              16 is typical default value */
00111
00112   uint32_t TrimmingValuePHighSpeed;      /*!< Specifies the offset trimming value (PMOS) in High Speed Mode
00113                                              i.e. when UserTrimming is OPAMP_TRIMMING_USER.
00114                                              This parameter must be a number between Min_Data = 0 and Max_Data = 31.
00115                                              16 is typical default value */
00116
00117   uint32_t TrimmingValueNHighSpeed;      /*!< Specifies the offset trimming value (NMOS) in High Speed Mode
00118                                              i.e. when UserTrimming is OPAMP_TRIMMING_USER.
00119                                              This parameter must be a number between Min_Data = 0 and Max_Data = 31.
00120                                              16 is typical default value */
00121
00122 }OPAMP_InitTypeDef;
00123
00124 /**
00125   * @brief  HAL State structures definition
00126   */
00127
00128 typedef enum
00129 {
00130   HAL_OPAMP_STATE_RESET               = 0x00000000, /*!< OPAMP is not yet Initialized          */
00131
00132   HAL_OPAMP_STATE_READY               = 0x00000001, /*!< OPAMP is initialized and ready for use */
00133   HAL_OPAMP_STATE_CALIBBUSY           = 0x00000002, /*!< OPAMP is enabled in auto calibration mode */
00134
00135   HAL_OPAMP_STATE_BUSY                = 0x00000004, /*!< OPAMP is enabled and running in normal mode */
00136   HAL_OPAMP_STATE_BUSYLOCKED          = 0x00000005  /*!< OPAMP is locked
00137                                                          only system reset allows reconfiguring the opamp. */
00138
00139 }HAL_OPAMP_StateTypeDef;
00140
00141 /**
00142   * @brief OPAMP Handle Structure definition
00143   */
00144 typedef struct
00145 {
00146   OPAMP_TypeDef                 *Instance;                    /*!< OPAMP instance's registers base address   */
00147   OPAMP_InitTypeDef              Init;                         /*!< OPAMP required parameters */
00148   HAL_StatusTypeDef              Status;                       /*!< OPAMP peripheral status   */
00149   HAL_LockTypeDef                Lock;                         /*!< Locking object          */
00150   __IO HAL_OPAMP_StateTypeDef    State;                        /*!< OPAMP communication state */
00151
00152 } OPAMP_HandleTypeDef;
00153
00154 /**
00155   * @brief HAl_OPAMP_TrimmingValueTypeDef definition
00156   */
00157
00158 typedef  uint32_t HAL_OPAMP_TrimmingValueTypeDef;
00159
00160 /**
00161   * @}
00162   */
00163
00164 /* Exported constants --------------------------------------------------------*/
00165
00166 /** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants
00167   * @{
00168   */
00169
00170 /** @defgroup OPAMP_Mode OPAMP Mode
00171   * @{
00172   */
00173 #define OPAMP_STANDALONE_MODE            ((uint32_t)0x00000000)                       /*!< standalone mode */
00174 #define OPAMP_PGA_MODE                     OPAMP_CSR_VMSEL_1                           /*!< PGA mode */
00175 #define OPAMP_FOLLOWER_MODE              (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0)      /*!< follower mode */
00176
00177 /**
00178   * @}
00179   */
00180
00181 /** @defgroup OPAMP_NonInvertingInput OPAMP Non Inverting Input
00182   * @{
00183   */
00184
00185 #define OPAMP_NONINVERTINGINPUT_IO0        ((uint32_t)0x00000000)     /*!< OPAMP non-inverting input connected to dedicated IO pin */
00186 #define OPAMP_NONINVERTINGINPUT_DAC_CH      OPAMP_CSR_VPSEL_0         /*!< OPAMP non-inverting input connected internally to DAC channel */
00187
00188 /**
00189   * @}
00190   */
00191
00192 /** @defgroup OPAMP_InvertingInput OPAMP Inverting Input
00193   * @{
00194   */
00195
00196 #define OPAMP_INVERTINGINPUT_IO0              ((uint32_t)0x00000000)                         /*!< OPAMP inverting input connected to dedicated IO pin */
00197 #define OPAMP_INVERTINGINPUT_IO1               OPAMP_CSR_VMSEL_0                             /*!< OPAMP inverting input connected to dedicated IO pin */
00198
00199 /**
00200   * @}
00201   */
00202
00203 /** @defgroup OPAMP_PgaConnect OPAMP Pga Connect
00204   * @{
00205   */
00206
00207 #define OPAMP_PGA_CONNECT_INVERTINGINPUT_NO               ((uint32_t)0x00000000)                     /*!< In PGA mode, the inverting input is not connected */
00208 #define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0               OPAMP_CSR_PGGAIN_2                        /*!< In PGA mode, the inverting input is connected to VINM0 */
00209 #define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS          OPAMP_CSR_PGGAIN_3                        /*!< In PGA mode, the inverting input is connected to VINM0 or bias */
00210 #define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS     (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_3)  /*!< In PGA mode, the inverting input is connected to VINM0 or bias , VINM1 connected for filtering */
00211
00212
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup OPAMP_PgaGain OPAMP Pga Gain
00218   * @{
00219   */
00220
00221 #define OPAMP_PGA_GAIN_2_OR_MINUS_1              ((uint32_t)0x00000000)                       /*!< PGA gain could be 2 or -1   */
00222 #define OPAMP_PGA_GAIN_4_OR_MINUS_3               OPAMP_CSR_PGGAIN_0                          /*!< PGA gain could be 4 or -3   */
00223 #define OPAMP_PGA_GAIN_8_OR_MINUS_7               OPAMP_CSR_PGGAIN_1                          /*!< PGA gain could be 8 or -7   */
00224 #define OPAMP_PGA_GAIN_16_OR_MINUS_15            (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1)    /*!< PGA gain could be 16 or -15 */
00225
00226 /**
00227   * @}
00228   */
00229
00230 /** @defgroup OPAMP_PowerMode OPAMP PowerMode
00231   * @{
00232   */
00233 #define OPAMP_POWERMODE_NORMAL        ((uint32_t)0x00000000)
00234 #define OPAMP_POWERMODE_HIGHSPEED      OPAMP_CSR_OPAHSM
00235
00236 /**
00237   * @}
00238   */
00239
00240
00241 /** @defgroup OPAMP_VREF OPAMP VREF
00242   * @{
00243   */
00244
00245 #define OPAMP_VREF_3VDDA                    ((uint32_t)0x00000000)       /*!< OPAMP Vref = 3.3% VDDA */
00246 #define OPAMP_VREF_10VDDA                    OPAMP_CSR_CALSEL_0          /*!< OPAMP Vref = 10% VDDA  */
00247 #define OPAMP_VREF_50VDDA                    OPAMP_CSR_CALSEL_1          /*!< OPAMP Vref = 50% VDDA  */
00248 #define OPAMP_VREF_90VDDA                    OPAMP_CSR_CALSEL            /*!< OPAMP Vref = 90% VDDA  */
00249
00250 /**
00251   * @}
00252   */
00253
00254 /** @defgroup OPAMP_UserTrimming OPAMP User Trimming
00255   * @{
00256   */
00257 #define OPAMP_TRIMMING_FACTORY        ((uint32_t)0x00000000)                          /*!< Factory trimming */
00258 #define OPAMP_TRIMMING_USER            OPAMP_CSR_USERTRIM                             /*!< User trimming */
00259
00260
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup OPAMP_FactoryTrimming OPAMP Factory Trimming
00266   * @{
00267   */
00268 #define OPAMP_FACTORYTRIMMING_DUMMY    ((uint32_t)0xFFFFFFFF)                           /*!< Dummy value if trimming value could not be retrieved */
00269
00270 #define OPAMP_FACTORYTRIMMING_N        ((uint32_t)0x00000000)                          /*!< Offset trimming N */
00271 #define OPAMP_FACTORYTRIMMING_P        ((uint32_t)0x00000001)                          /*!< Offset trimming P */
00272
00273 /**
00274   * @}
00275   */
00276
00277  /**
00278   * @}
00279   */
00280
00281 /* Private constants ---------------------------------------------------------*/
00282 /** @defgroup OPAMP_Private_Constants OPAMP Private Constants
00283   * @brief   OPAMP Private constants and defines
00284   * @{
00285   */
00286
00287 /* NONINVERTING bit position in OTR & HSOTR */
00288 #define OPAMP_INPUT_NONINVERTING              ((uint32_t) 8) /*!< Non inverting input */
00289
00290 /* Offset trimming time: during calibration, minimum time needed between two  */
00291 /* steps to have 1 mV accuracy.                                               */
00292 /* Refer to datasheet, electrical characteristics: parameter tOFFTRIM Typ=2ms.*/
00293 /* Unit: ms.                                                                  */
00294 #define OPAMP_TRIMMING_DELAY               ((uint32_t) 2)
00295
00296 /**
00297   * @}
00298   */
00299
00300 /* Exported macros -----------------------------------------------------------*/
00301 /** @defgroup OPAMP_Exported_Macros OPAMP Exported Macros
00302   * @{
00303   */
00304
00305 /** @brief Reset OPAMP handle state.
00306   * @param  __HANDLE__: OPAMP handle.
00307   * @retval None
00308   */
00309 #define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
00310
00311 /**
00312   * @}
00313   */
00314
00315 /* Private macro -------------------------------------------------------------*/
00316
00317 /** @defgroup OPAMP_Private_Macros OPAMP Private Macros
00318   * @{
00319   */
00320
00321 #define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \
00322                                                ((INPUT) == OPAMP_PGA_MODE) || \
00323                                                ((INPUT) == OPAMP_FOLLOWER_MODE))
00324
00325 #define IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
00326                                                     ((INPUT) == OPAMP_INVERTINGINPUT_IO1))
00327
00328
00329 #define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
00330                                             ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH))
00331
00332 #define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_NO)  || \
00333                                       ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0) || \
00334                                       ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS) || \
00335                                       ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS))
00336
00337 #define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2_OR_MINUS_1) || \
00338                                  ((GAIN) == OPAMP_PGA_GAIN_4_OR_MINUS_3) || \
00339                                  ((GAIN) == OPAMP_PGA_GAIN_8_OR_MINUS_7) || \
00340                                  ((GAIN) == OPAMP_PGA_GAIN_16_OR_MINUS_15))
00341
00342
00343 #define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_VREF_3VDDA)  || \
00344                              ((VREF) == OPAMP_VREF_10VDDA) || \
00345                              ((VREF) == OPAMP_VREF_50VDDA) || \
00346                              ((VREF) == OPAMP_VREF_90VDDA))
00347
00348 #define IS_OPAMP_POWERMODE(TRIMMING) (((TRIMMING) == OPAMP_POWERMODE_NORMAL) || \
00349                                       ((TRIMMING) == OPAMP_POWERMODE_HIGHSPEED) )
00350
00351
00352 #define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
00353                                      ((TRIMMING) == OPAMP_TRIMMING_USER))
00354
00355
00356 #define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
00357
00358 #define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
00359                                              ((TRIMMING) == OPAMP_FACTORYTRIMMING_P))
00360
00361 /**
00362   * @}
00363   */
00364
00365 /* Include OPAMP HAL Extended module */
00366 #include "stm32h7xx_hal_opamp_ex.h"
00367
00368 /* Exported functions --------------------------------------------------------*/
00369 /** @addtogroup OPAMP_Exported_Functions
00370   * @{
00371   */
00372
00373 /** @addtogroup OPAMP_Exported_Functions_Group1
00374   * @{
00375   */
00376 /* Initialization/de-initialization functions  **********************************/
00377 HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp);
00378 HAL_StatusTypeDef HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp);
00379 void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp);
00380 void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp);
00381 /**
00382   * @}
00383   */
00384
00385 /** @addtogroup OPAMP_Exported_Functions_Group2
00386   * @{
00387   */
00388
00389 /* I/O operation functions  *****************************************************/
00390 HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp);
00391 HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp);
00392 HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp);
00393
00394 /**
00395   * @}
00396   */
00397
00398 /** @addtogroup OPAMP_Exported_Functions_Group3
00399   * @{
00400   */
00401
00402 /* Peripheral Control functions  ************************************************/
00403 HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp);
00404 HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);
00405
00406 /**
00407   * @}
00408   */
00409
00410 /** @addtogroup OPAMP_Exported_Functions_Group4
00411   * @{
00412   */
00413
00414 /* Peripheral State functions  **************************************************/
00415 HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);
00416
00417 /**
00418   * @}
00419   */
00420
00421 /**
00422   * @}
00423   */
00424
00425 /**
00426   * @}
00427   */
00428
00429 /**
00430   * @}
00431   */
00432
00433 #ifdef __cplusplus
00434 }
00435 #endif
00436
00437 #endif /* __STM32H7xx_HAL_OPAMP_H */
00438
00439 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_opamp_ex.c Source File

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stm32h7xx_hal_opamp_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_opamp_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Extended OPAMP HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc)
00010   *          peripheral:
00011   *           + Extended Initialization and de-initialization functions
00012   *           + Extended Peripheral Control functions
00013   *
00014   @verbatim
00015   ******************************************************************************
00016   * @attention
00017   *
00018   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00019   *
00020   * Redistribution and use in source and binary forms, with or without modification,
00021   * are permitted provided that the following conditions are met:
00022   *   1. Redistributions of source code must retain the above copyright notice,
00023   *      this list of conditions and the following disclaimer.
00024   *   2. Redistributions in binary form must reproduce the above copyright notice,
00025   *      this list of conditions and the following disclaimer in the documentation
00026   *      and/or other materials provided with the distribution.
00027   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00028   *      may be used to endorse or promote products derived from this software
00029   *      without specific prior written permission.
00030   *
00031   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00032   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00033   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00034   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00035   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00036   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00037   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00038   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00039   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00040   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00041   *
00042   ******************************************************************************
00043   */
00044
00045 /* Includes ------------------------------------------------------------------*/
00046 #include "stm32h7xx_hal.h"
00047
00048 /** @addtogroup STM32H7xx_HAL_Driver
00049   * @{
00050   */
00051
00052 /** @defgroup OPAMPEx OPAMPEx
00053   * @brief OPAMP Extended HAL module driver
00054   * @{
00055   */
00056
00057 #ifdef HAL_OPAMP_MODULE_ENABLED
00058
00059 /* Private typedef -----------------------------------------------------------*/
00060 /* Private define ------------------------------------------------------------*/
00061 /* Private macro -------------------------------------------------------------*/
00062 /* Private variables ---------------------------------------------------------*/
00063 /* Private function prototypes -----------------------------------------------*/
00064 /* Exported functions --------------------------------------------------------*/
00065
00066 /** @defgroup OPAMPEx_Exported_Functions OPAMP Extended Exported Functions
00067   * @{
00068   */
00069
00070 /** @defgroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
00071   * @brief    Extended operation functions
00072   *
00073 @verbatim
00074  ===============================================================================
00075               ##### Extended IO operation functions #####
00076  ===============================================================================
00077   [..]
00078       (+) OPAMP Self calibration.
00079
00080 @endverbatim
00081   * @{
00082   */
00083
00084 /**
00085   * @brief  Run the self calibration of 2 OPAMPs in parallel.
00086   * @note   Trimming values (PMOS & NMOS) are updated and user trimming is
00087   *         enabled is calibration is successful.
00088   * @note   Calibration is performed in the mode specified in OPAMP init
00089   *         structure (mode normal or low power). To perform calibration for
00090   *         both modes, repeat this function twice after OPAMP init structure
00091   *         accordingly updated.
00092   * @param  hopamp1 handle
00093   * @param  hopamp2 handle
00094   * @retval HAL status
00095   */
00096
00097 HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
00098 {
00099   HAL_StatusTypeDef status = HAL_OK;
00100
00101   uint32_t trimmingvaluen1 = 0;
00102   uint32_t trimmingvaluep1 = 0;
00103   uint32_t trimmingvaluen2 = 0;
00104   uint32_t trimmingvaluep2 = 0;
00105
00106 /* Selection of register of trimming depending on power mode: OTR or HSOTR */
00107   __IO uint32_t* tmp_opamp1_reg_trimming;
00108   __IO uint32_t* tmp_opamp2_reg_trimming;
00109
00110   uint32_t delta;
00111   uint32_t opampmode1;
00112   uint32_t opampmode2;
00113
00114   if((hopamp1 == NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) || \
00115      (hopamp2 == NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED))
00116   {
00117     status = HAL_ERROR;
00118   }
00119   else
00120   {
00121     /* Check if OPAMP in calibration mode and calibration not yet enable */
00122     if((hopamp1->State ==  HAL_OPAMP_STATE_READY) && (hopamp2->State ==  HAL_OPAMP_STATE_READY))
00123     {
00124       /* Check the parameter */
00125       assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
00126       assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
00127
00128       assert_param(IS_OPAMP_POWERMODE(hopamp1->Init.PowerMode));
00129       assert_param(IS_OPAMP_POWERMODE(hopamp2->Init.PowerMode));
00130
00131       /* Set Calibration mode */
00132       /* Non-inverting input connected to calibration reference voltage. */
00133       SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
00134       SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
00135
00136       /* Save OPAMP mode  */
00137       opampmode1 = READ_BIT(hopamp1->Instance->CSR,OPAMP_CSR_VMSEL);
00138       opampmode2 = READ_BIT(hopamp2->Instance->CSR,OPAMP_CSR_VMSEL);
00139
00140       /* Use of standalone mode */
00141       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_VMSEL, OPAMP_STANDALONE_MODE);
00142       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_VMSEL, OPAMP_STANDALONE_MODE);
00143
00144       /*  user trimming values are used for offset calibration */
00145       SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM);
00146       SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM);
00147
00148       /* Select trimming settings depending on power mode */
00149       if (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
00150       {
00151         tmp_opamp1_reg_trimming = &OPAMP1->OTR;
00152       }
00153       else
00154       {
00155         tmp_opamp1_reg_trimming = &OPAMP1->HSOTR;
00156       }
00157
00158       if (hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
00159       {
00160         tmp_opamp2_reg_trimming = &OPAMP2->OTR;
00161       }
00162       else
00163       {
00164         tmp_opamp2_reg_trimming = &OPAMP2->HSOTR;
00165       }
00166
00167       /* Enable calibration */
00168       SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
00169       SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
00170
00171       /* 1st calibration - N */
00172       /* Select 90U% VREF */
00173       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
00174       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
00175
00176       /* Enable the selected opamp */
00177       SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00178       SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00179
00180       /* Init trimming counter */
00181       /* Medium value */
00182       trimmingvaluen1 = 16;
00183       trimmingvaluen2 = 16;
00184       delta = 8;
00185
00186       while (delta != 0)
00187       {
00188         /* Set candidate trimming */
00189         /* OPAMP_POWERMODE_NORMAL */
00190         MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
00191         MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
00192
00193         /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00194         /* Offset trim time: during calibration, minimum time needed between */
00195         /* two steps to have 1 mV accuracy */
00196         HAL_Delay(OPAMP_TRIMMING_DELAY);
00197
00198         if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)!= RESET)
00199         {
00200           /* OPAMP_CSR_CALOUT is Low try higher trimming */
00201           trimmingvaluen1 += delta;
00202         }
00203         else
00204         {
00205           /* OPAMP_CSR_CALOUT is High try lower trimming */
00206           trimmingvaluen1 -= delta;
00207         }
00208
00209         if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)!= RESET)
00210         {
00211           /* OPAMP_CSR_CALOUT is Low try higher trimming */
00212           trimmingvaluen2 += delta;
00213         }
00214         else
00215         {
00216           /* OPAMP_CSR_CALOUT is High try lower trimming */
00217           trimmingvaluen2 -= delta;
00218         }
00219         /* Divide range by 2 to continue dichotomy sweep */
00220         delta >>= 1;
00221       }
00222
00223       /* Still need to check if right calibration is current value or one step below */
00224       /* Indeed the first value that causes the OUTCAL bit to change from 0 to 1  */
00225       /* Set candidate trimming */
00226       MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
00227       MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
00228
00229       /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00230       /* Offset trim time: during calibration, minimum time needed between */
00231       /* two steps to have 1 mV accuracy */
00232       HAL_Delay(OPAMP_TRIMMING_DELAY);
00233
00234       if ((READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)) != 0)
00235       {
00236         /* Trimming value is actually one value more */
00237         trimmingvaluen1++;
00238         MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
00239       }
00240
00241       if ((READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)) != 0)
00242       {
00243         /* Trimming value is actually one value more */
00244         trimmingvaluen2++;
00245         MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
00246       }
00247
00248       /* 2nd calibration - P */
00249       /* Select 10U% VREF */
00250       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
00251       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
00252
00253       /* Init trimming counter */
00254       /* Medium value */
00255       trimmingvaluep1 = 16;
00256       trimmingvaluep2 = 16;
00257       delta = 8;
00258
00259       while (delta != 0)
00260       {
00261         /* Set candidate trimming */
00262         /* OPAMP_POWERMODE_NORMAL */
00263         MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<<OPAMP_INPUT_NONINVERTING));
00264         MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<<OPAMP_INPUT_NONINVERTING));
00265
00266         /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00267         /* Offset trim time: during calibration, minimum time needed between */
00268         /* two steps to have 1 mV accuracy */
00269         HAL_Delay(OPAMP_TRIMMING_DELAY);
00270
00271         if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)!= RESET)
00272         {
00273           /* OPAMP_CSR_CALOUT is Low try higher trimming */
00274           trimmingvaluep1 += delta;
00275         }
00276         else
00277         {
00278           /* OPAMP_CSR_CALOUT is HIGH try lower trimming */
00279           trimmingvaluep1 -= delta;
00280         }
00281
00282         if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)!= RESET)
00283         {
00284           /* OPAMP_CSR_CALOUT is Low try higher trimming */
00285           trimmingvaluep2 += delta;
00286         }
00287         else
00288         {
00289           /* OPAMP_CSR_CALOUT is High try lower trimming */
00290           trimmingvaluep2 -= delta;
00291         }
00292         /* Divide range by 2 to continue dichotomy sweep */
00293         delta >>= 1;
00294       }
00295
00296       /* Still need to check if right calibration is current value or one step below */
00297       /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0  */
00298       /* Set candidate trimming */
00299       MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<<OPAMP_INPUT_NONINVERTING));
00300       MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<<OPAMP_INPUT_NONINVERTING));
00301
00302       /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00303       /* Offset trim time: during calibration, minimum time needed between */
00304       /* two steps to have 1 mV accuracy */
00305       HAL_Delay(OPAMP_TRIMMING_DELAY);
00306
00307       if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)!= RESET)
00308       {
00309         /* Trimming value is actually one value more */
00310         trimmingvaluep1++;
00311         MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<<OPAMP_INPUT_NONINVERTING));
00312       }
00313
00314       if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)!= RESET)
00315       {
00316         /* Trimming value is actually one value more */
00317         trimmingvaluep2++;
00318         MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<<OPAMP_INPUT_NONINVERTING));
00319       }
00320
00321       /* Disable calibration & set normal mode (operating mode) */
00322       CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
00323       CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
00324
00325      /* Disable the OPAMPs */
00326       CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00327       CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00328
00329       /* Self calibration is successful */
00330       /* Store calibration (user trimming) results in init structure. */
00331
00332       /* Set user trimming mode */
00333       hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
00334       hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
00335
00336       /* Affect calibration parameters depending on mode normal/high speed */
00337       if (hopamp1->Init.PowerMode != OPAMP_POWERMODE_HIGHSPEED)
00338       {
00339         /* Write calibration result N */
00340         hopamp1->Init.TrimmingValueN = trimmingvaluen1;
00341         /* Write calibration result P */
00342         hopamp1->Init.TrimmingValueP = trimmingvaluep1;
00343       }
00344       else
00345       {
00346         /* Write calibration result N */
00347         hopamp1->Init.TrimmingValueNHighSpeed = trimmingvaluen1;
00348         /* Write calibration result P */
00349         hopamp1->Init.TrimmingValuePHighSpeed = trimmingvaluep1;
00350       }
00351
00352       if (hopamp2->Init.PowerMode != OPAMP_POWERMODE_HIGHSPEED)
00353       {
00354         /* Write calibration result N */
00355         hopamp2->Init.TrimmingValueN = trimmingvaluen2;
00356         /* Write calibration result P */
00357         hopamp2->Init.TrimmingValueP = trimmingvaluep2;
00358       }
00359       else
00360       {
00361         /* Write calibration result N */
00362         hopamp2->Init.TrimmingValueNHighSpeed = trimmingvaluen2;
00363         /* Write calibration result P */
00364         hopamp2->Init.TrimmingValuePHighSpeed = trimmingvaluep2;
00365
00366        }
00367       /* Update OPAMP state */
00368       hopamp1->State = HAL_OPAMP_STATE_READY;
00369       hopamp2->State = HAL_OPAMP_STATE_READY;
00370
00371       /* Restore OPAMP mode after calibration */
00372       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_VMSEL, opampmode1);
00373       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_VMSEL, opampmode2);
00374   }
00375     else
00376     {
00377       /* At least one OPAMP can not be calibrated */
00378       status = HAL_ERROR;
00379     }
00380   }
00381   return status;
00382 }
00383
00384 /**
00385   * @}
00386   */
00387
00388 /** @defgroup OPAMPEx_Exported_Functions_Group2 Peripheral Control functions
00389  *  @brief   Peripheral Control functions
00390  *
00391 @verbatim
00392  ===============================================================================
00393              ##### Peripheral Control functions #####
00394  ===============================================================================
00395     [..]
00396       (+) OPAMP unlock.
00397
00398 @endverbatim
00399   * @{
00400   */
00401
00402 /**
00403   * @brief  Unlock the selected OPAMP configuration.
00404   * @note   This function must be called only when OPAMP is in state "locked".
00405   * @param  hopamp: OPAMP handle
00406   * @retval HAL status
00407   */
00408 HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef* hopamp)
00409 {
00410   HAL_StatusTypeDef status = HAL_OK;
00411
00412   /* Check the OPAMP handle allocation */
00413   /* Check if OPAMP locked */
00414   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET)
00415                       || (hopamp->State == HAL_OPAMP_STATE_READY)
00416                       || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
00417                       || (hopamp->State == HAL_OPAMP_STATE_BUSY))
00418
00419   {
00420     status = HAL_ERROR;
00421   }
00422   else
00423   {
00424     /* Check the parameter */
00425     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00426
00427    /* OPAMP state changed to locked */
00428     hopamp->State = HAL_OPAMP_STATE_BUSY;
00429   }
00430   return status;
00431 }
00432
00433 /**
00434   * @}
00435   */
00436
00437 /**
00438   * @}
00439   */
00440
00441 /**
00442   * @}
00443   */
00444
00445 /**
00446   * @}
00447   */
00448
00449 #endif /* HAL_OPAMP_MODULE_ENABLED */
00450 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_opamp_ex.h Source File

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stm32h7xx_hal_opamp_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_opamp_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of OPAMP HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_OPAMP_EX_H
00040 #define __STM32H7xx_HAL_OPAMP_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup OPAMPEx
00054   * @{
00055   */
00056 /* Exported types ------------------------------------------------------------*/
00057 /* Exported constants --------------------------------------------------------*/
00058 /* Exported macro ------------------------------------------------------------*/
00059 /* Exported functions --------------------------------------------------------*/
00060 /** @addtogroup OPAMPEx_Exported_Functions OPAMPEx Exported Functions
00061   * @{
00062   */
00063
00064 /* Extended IO operation functions  *****************************************************/
00065 /** @addtogroup OPAMPEx_Exported_Functions_Group1
00066   * @{
00067   */
00068 HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2);
00069
00070 /**
00071   * @}
00072   */
00073 /* Peripheral Control functions  ************************************************/
00074 /** @addtogroup OPAMPEx_Exported_Functions_Group2
00075   * @{
00076   */
00077 HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp);
00078 /**
00079   * @}
00080   */
00081
00082 /**
00083   * @}
00084   */
00085
00086 /**
00087   * @}
00088   */
00089
00090 /**
00091   * @}
00092   */
00093
00094 #ifdef __cplusplus
00095 }
00096 #endif
00097
00098
00099 #endif /* __STM32H7xx_HAL_OPAMP_EX_H */
00100
00101 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_pcd.c Source File

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stm32h7xx_hal_pcd.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_pcd.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   PCD HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the USB Peripheral Controller:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                     ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020       The PCD HAL driver can be used as follows:
00021
00022      (#) Declare a PCD_HandleTypeDef handle structure, for example:
00023          PCD_HandleTypeDef  hpcd;
00024
00025      (#) Fill parameters of Init structure in HCD handle
00026
00027      (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...)
00028
00029      (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
00030          (##) Enable the PCD/USB Low Level interface clock using
00031               (+++) __OTGFS-OTG_CLK_ENABLE()/__OTGHS-OTG_CLK_ENABLE();
00032               (+++) __OTGHSULPI_CLK_ENABLE(); (For High Speed Mode)
00033
00034          (##) Initialize the related GPIO clocks
00035          (##) Configure PCD pin-out
00036          (##) Configure PCD NVIC interrupt
00037
00038      (#)Associate the Upper USB device stack to the HAL PCD Driver:
00039          (##) hpcd.pData = pdev;
00040
00041      (#)Enable HCD transmission and reception:
00042          (##) HAL_PCD_Start();
00043
00044   @endverbatim
00045   ******************************************************************************
00046   * @attention
00047   *
00048   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00049   *
00050   * Redistribution and use in source and binary forms, with or without modification,
00051   * are permitted provided that the following conditions are met:
00052   *   1. Redistributions of source code must retain the above copyright notice,
00053   *      this list of conditions and the following disclaimer.
00054   *   2. Redistributions in binary form must reproduce the above copyright notice,
00055   *      this list of conditions and the following disclaimer in the documentation
00056   *      and/or other materials provided with the distribution.
00057   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00058   *      may be used to endorse or promote products derived from this software
00059   *      without specific prior written permission.
00060   *
00061   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00062   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00063   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00064   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00065   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00066   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00067   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00068   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00069   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00070   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00071   *
00072   ******************************************************************************
00073   */
00074
00075 /* Includes ------------------------------------------------------------------*/
00076 #include "stm32h7xx_hal.h"
00077
00078 /** @addtogroup STM32H7xx_HAL_Driver
00079   * @{
00080   */
00081
00082 /** @defgroup PCD PCD
00083   * @brief PCD HAL module driver
00084   * @{
00085   */
00086
00087 #ifdef HAL_PCD_MODULE_ENABLED
00088
00089 /* Private types -------------------------------------------------------------*/
00090 /* Private variables ---------------------------------------------------------*/
00091 /* Private constants ---------------------------------------------------------*/
00092 /* Private macros ------------------------------------------------------------*/
00093 /** @defgroup PCD_Private_Macros PCD Private Macros
00094   * @{
00095   */
00096 #define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
00097 #define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
00098 /**
00099   * @}
00100   */
00101
00102 /* Private functions prototypes ----------------------------------------------*/
00103 /** @defgroup PCD_Private_Functions PCD Private Functions
00104   * @{
00105   */
00106 static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
00107 /**
00108   * @}
00109   */
00110
00111 /* Exported functions --------------------------------------------------------*/
00112 /** @defgroup PCD_Exported_Functions PCD Exported Functions
00113   * @{
00114   */
00115
00116 /** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
00117  *  @brief    Initialization and Configuration functions
00118  *
00119 @verbatim
00120  ===============================================================================
00121             ##### Initialization and de-initialization functions #####
00122  ===============================================================================
00123     [..]  This section provides functions allowing to:
00124
00125 @endverbatim
00126   * @{
00127   */
00128
00129 /**
00130   * @brief  Initializes the PCD according to the specified
00131   *         parameters in the PCD_InitTypeDef and create the associated handle.
00132   * @param  hpcd: PCD handle
00133   * @retval HAL status
00134   */
00135 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
00136 {
00137   uint32_t i = 0;
00138
00139   /* Check the PCD handle allocation */
00140   if(hpcd == NULL)
00141   {
00142     return HAL_ERROR;
00143   }
00144
00145   /* Check the parameters */
00146   assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
00147
00148   hpcd->State = HAL_PCD_STATE_BUSY;
00149
00150   /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00151   HAL_PCD_MspInit(hpcd);
00152
00153   /* Disable the Interrupts */
00154  __HAL_PCD_DISABLE(hpcd);
00155
00156  /*Init the Core (common init.) */
00157  USB_CoreInit(hpcd->Instance, hpcd->Init);
00158
00159  /* Force Device Mode*/
00160  USB_SetCurrentMode(hpcd->Instance , USB_OTG_DEVICE_MODE);
00161
00162  /* Init endpoints structures */
00163  for (i = 0; i < 15 ; i++)
00164  {
00165    /* Init ep structure */
00166    hpcd->IN_ep[i].is_in = 1;
00167    hpcd->IN_ep[i].num = i;
00168    hpcd->IN_ep[i].tx_fifo_num = i;
00169    /* Control until ep is activated */
00170    hpcd->IN_ep[i].type = EP_TYPE_CTRL;
00171    hpcd->IN_ep[i].maxpacket =  0;
00172    hpcd->IN_ep[i].xfer_buff = 0;
00173    hpcd->IN_ep[i].xfer_len = 0;
00174  }
00175
00176  for (i = 0; i < 15 ; i++)
00177  {
00178    hpcd->OUT_ep[i].is_in = 0;
00179    hpcd->OUT_ep[i].num = i;
00180    hpcd->IN_ep[i].tx_fifo_num = i;
00181    /* Control until ep is activated */
00182    hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
00183    hpcd->OUT_ep[i].maxpacket = 0;
00184    hpcd->OUT_ep[i].xfer_buff = 0;
00185    hpcd->OUT_ep[i].xfer_len = 0;
00186
00187    hpcd->Instance->DIEPTXF[i] = 0;
00188  }
00189
00190  /* Init Device */
00191  USB_DevInit(hpcd->Instance, hpcd->Init);
00192
00193  hpcd->State= HAL_PCD_STATE_READY;
00194
00195  /* Activate LPM */
00196  if (hpcd->Init.lpm_enable == 1)
00197  {
00198    HAL_PCDEx_ActivateLPM(hpcd);
00199  }
00200
00201  /* Activate Battery charging */
00202  if (hpcd->Init.battery_charging_enable ==1)
00203  {
00204    HAL_PCDEx_ActivateBCD(hpcd);
00205  }
00206
00207  USB_DevDisconnect (hpcd->Instance);
00208  return HAL_OK;
00209 }
00210
00211 /**
00212   * @brief  DeInitializes the PCD peripheral
00213   * @param  hpcd: PCD handle
00214   * @retval HAL status
00215   */
00216 HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
00217 {
00218   /* Check the PCD handle allocation */
00219   if(hpcd == NULL)
00220   {
00221     return HAL_ERROR;
00222   }
00223
00224   hpcd->State = HAL_PCD_STATE_BUSY;
00225
00226   /* Stop Device */
00227   HAL_PCD_Stop(hpcd);
00228
00229   /* DeInit the low level hardware */
00230   HAL_PCD_MspDeInit(hpcd);
00231
00232   hpcd->State = HAL_PCD_STATE_RESET;
00233
00234   return HAL_OK;
00235 }
00236
00237 /**
00238   * @brief  Initializes the PCD MSP.
00239   * @param  hpcd: PCD handle
00240   * @retval None
00241   */
00242 __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
00243 {
00244   /* NOTE : This function Should not be modified, when the callback is needed,
00245             the HAL_PCD_MspInit could be implemented in the user file
00246    */
00247 }
00248
00249 /**
00250   * @brief  DeInitializes PCD MSP.
00251   * @param  hpcd: PCD handle
00252   * @retval None
00253   */
00254 __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
00255 {
00256   /* NOTE : This function Should not be modified, when the callback is needed,
00257             the HAL_PCD_MspDeInit could be implemented in the user file
00258    */
00259 }
00260
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup PCD_Exported_Functions_Group2 IO operation functions
00266  *  @brief   Data transfers functions
00267  *
00268 @verbatim
00269  ===============================================================================
00270                       ##### IO operation functions #####
00271  ===============================================================================
00272     [..]
00273     This subsection provides a set of functions allowing to manage the PCD data
00274     transfers.
00275
00276 @endverbatim
00277   * @{
00278   */
00279
00280 /**
00281   * @brief  Start The USB OTG Device.
00282   * @param  hpcd: PCD handle
00283   * @retval HAL status
00284   */
00285 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
00286 {
00287
00288   USB_DevConnect (hpcd->Instance);
00289   __HAL_PCD_ENABLE(hpcd);
00290
00291   return HAL_OK;
00292 }
00293
00294 /**
00295   * @brief  Stop The USB OTG Device.
00296   * @param  hpcd: PCD handle
00297   * @retval HAL status
00298   */
00299 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
00300 {
00301   __HAL_LOCK(hpcd);
00302   __HAL_PCD_DISABLE(hpcd);
00303   USB_StopDevice(hpcd->Instance);
00304   USB_DevDisconnect (hpcd->Instance);
00305   __HAL_UNLOCK(hpcd);
00306   return HAL_OK;
00307 }
00308
00309 /**
00310   * @brief  This function handles PCD interrupt request.
00311   * @param  hpcd: PCD handle
00312   * @retval HAL status
00313   */
00314 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
00315 {
00316   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00317   uint32_t i = 0, ep_intr = 0, epint = 0, epnum = 0;
00318   uint32_t fifoemptymsk = 0, temp = 0;
00319   USB_OTG_EPTypeDef *ep;
00320
00321   /* ensure that we are in device mode */
00322   if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
00323   {
00324     /* avoid spurious interrupt */
00325     if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
00326     {
00327       return;
00328     }
00329
00330     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
00331     {
00332      /* incorrect mode, acknowledge the interrupt */
00333       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
00334     }
00335
00336     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
00337     {
00338       epnum = 0;
00339
00340       /* Read in the device interrupt bits */
00341       ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
00342
00343       while ( ep_intr )
00344       {
00345         if (ep_intr & 0x1)
00346         {
00347           epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);
00348
00349           if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
00350           {
00351             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
00352
00353             if(hpcd->Init.dma_enable == 1)
00354             {
00355               hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
00356               hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
00357             }
00358
00359             HAL_PCD_DataOutStageCallback(hpcd, epnum);
00360             if(hpcd->Init.dma_enable == 1)
00361             {
00362               if((epnum == 0) && (hpcd->OUT_ep[epnum].xfer_len == 0))
00363               {
00364                  /* this is ZLP, so prepare EP0 for next setup */
00365                 USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
00366               }
00367             }
00368           }
00369
00370           if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
00371           {
00372             /* Inform the upper layer that a setup packet is available */
00373             HAL_PCD_SetupStageCallback(hpcd);
00374             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
00375           }
00376
00377           if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
00378           {
00379             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
00380           }
00381         }
00382         epnum++;
00383         ep_intr >>= 1;
00384       }
00385     }
00386
00387     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
00388     {
00389       /* Read in the device interrupt bits */
00390       ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
00391
00392       epnum = 0;
00393
00394       while ( ep_intr )
00395       {
00396         if (ep_intr & 0x1) /* In ITR */
00397         {
00398           epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum);
00399
00400            if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
00401           {
00402             fifoemptymsk = 0x1 << epnum;
00403             USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
00404
00405             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
00406
00407             if (hpcd->Init.dma_enable == 1)
00408             {
00409               hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
00410             }
00411
00412             HAL_PCD_DataInStageCallback(hpcd, epnum);
00413
00414             if (hpcd->Init.dma_enable == 1)
00415             {
00416               /* this is ZLP, so prepare EP0 for next setup */
00417               if((epnum == 0) && (hpcd->IN_ep[epnum].xfer_len == 0))
00418               {
00419                 /* prepare to rx more setup packets */
00420                 USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
00421               }
00422             }
00423           }
00424            if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
00425           {
00426             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
00427           }
00428           if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
00429           {
00430             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
00431           }
00432           if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
00433           {
00434             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
00435           }
00436           if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
00437           {
00438             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
00439           }
00440           if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
00441           {
00442             PCD_WriteEmptyTxFifo(hpcd , epnum);
00443           }
00444         }
00445         epnum++;
00446         ep_intr >>= 1;
00447       }
00448     }
00449
00450     /* Handle Resume Interrupt */
00451     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
00452     {
00453       /* Clear the Remote Wake-up Signaling */
00454       USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
00455
00456       if(hpcd->LPM_State == LPM_L1)
00457       {
00458         hpcd->LPM_State = LPM_L0;
00459         HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
00460       }
00461       else
00462       {
00463         HAL_PCD_ResumeCallback(hpcd);
00464       }
00465       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
00466     }
00467
00468     /* Handle Suspend Interrupt */
00469     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
00470     {
00471
00472       if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
00473       {
00474
00475         HAL_PCD_SuspendCallback(hpcd);
00476       }
00477       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
00478     }
00479
00480     /* Handle LPM Interrupt */
00481     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
00482     {
00483       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
00484       if( hpcd->LPM_State == LPM_L0)
00485       {
00486         hpcd->LPM_State = LPM_L1;
00487         hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ;
00488         HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
00489       }
00490       else
00491       {
00492         HAL_PCD_SuspendCallback(hpcd);
00493       }
00494     }
00495
00496     /* Handle Reset Interrupt */
00497     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
00498     {
00499       USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
00500       USB_FlushTxFifo(hpcd->Instance, 0x10);
00501
00502       for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
00503       {
00504         USBx_INEP(i)->DIEPINT = 0xFF;
00505         USBx_OUTEP(i)->DOEPINT = 0xFF;
00506       }
00507       USBx_DEVICE->DAINT = 0xFFFFFFFF;
00508       USBx_DEVICE->DAINTMSK |= 0x10001;
00509
00510       if(hpcd->Init.use_dedicated_ep1)
00511       {
00512         USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
00513         USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
00514       }
00515       else
00516       {
00517         USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
00518         USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
00519       }
00520
00521       /* Set Default Address to 0 */
00522       USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
00523
00524       /* setup EP0 to receive SETUP packets */
00525       USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
00526
00527       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
00528     }
00529
00530     /* Handle Enumeration done Interrupt */
00531     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
00532     {
00533       USB_ActivateSetup(hpcd->Instance);
00534       hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
00535
00536       if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)
00537       {
00538         hpcd->Init.speed            = USB_OTG_SPEED_HIGH;
00539         hpcd->Init.ep0_mps          = USB_OTG_HS_MAX_PACKET_SIZE ;
00540         hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);
00541       }
00542       else
00543       {
00544         hpcd->Init.speed            = USB_OTG_SPEED_FULL;
00545         hpcd->Init.ep0_mps          = USB_OTG_FS_MAX_PACKET_SIZE ;
00546         hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);
00547       }
00548
00549       HAL_PCD_ResetCallback(hpcd);
00550
00551       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
00552     }
00553
00554     /* Handle RxQLevel Interrupt */
00555     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
00556     {
00557       USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00558       temp = USBx->GRXSTSP;
00559       ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
00560
00561       if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_DATA_UPDT)
00562       {
00563         if((temp & USB_OTG_GRXSTSP_BCNT) != 0)
00564         {
00565           USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4);
00566           ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
00567           ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
00568         }
00569       }
00570       else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_SETUP_UPDT)
00571       {
00572         USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8);
00573         ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
00574       }
00575       USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00576     }
00577
00578     /* Handle SOF Interrupt */
00579     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
00580     {
00581       HAL_PCD_SOFCallback(hpcd);
00582       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
00583     }
00584
00585     /* Handle Incomplete ISO IN Interrupt */
00586     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
00587     {
00588       HAL_PCD_ISOINIncompleteCallback(hpcd, epnum);
00589       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
00590     }
00591
00592     /* Handle Incomplete ISO OUT Interrupt */
00593     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
00594     {
00595       HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum);
00596       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
00597     }
00598
00599     /* Handle Connection event Interrupt */
00600     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
00601     {
00602       HAL_PCD_ConnectCallback(hpcd);
00603       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
00604     }
00605
00606     /* Handle Disconnection event Interrupt */
00607     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
00608     {
00609       temp = hpcd->Instance->GOTGINT;
00610
00611       if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
00612       {
00613         HAL_PCD_DisconnectCallback(hpcd);
00614       }
00615       hpcd->Instance->GOTGINT |= temp;
00616     }
00617   }
00618 }
00619
00620 /**
00621   * @brief  Data out stage callbacks
00622   * @param  hpcd: PCD handle
00623   * @param  epnum: endpoint number
00624   * @retval None
00625   */
00626  __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00627 {
00628   /* NOTE : This function Should not be modified, when the callback is needed,
00629             the HAL_PCD_DataOutStageCallback could be implemented in the user file
00630    */
00631 }
00632
00633 /**
00634   * @brief  Data IN stage callbacks
00635   * @param  hpcd: PCD handle
00636   * @param  epnum: endpoint number
00637   * @retval None
00638   */
00639  __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00640 {
00641   /* NOTE : This function Should not be modified, when the callback is needed,
00642             the HAL_PCD_DataInStageCallback could be implemented in the user file
00643    */
00644 }
00645 /**
00646   * @brief  Setup stage callback
00647   * @param  hpcd: PCD handle
00648   * @retval None
00649   */
00650  __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
00651 {
00652   /* NOTE : This function Should not be modified, when the callback is needed,
00653             the HAL_PCD_SetupStageCallback could be implemented in the user file
00654    */
00655 }
00656
00657 /**
00658   * @brief  USB Start Of Frame callbacks
00659   * @param  hpcd: PCD handle
00660   * @retval None
00661   */
00662  __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
00663 {
00664   /* NOTE : This function Should not be modified, when the callback is needed,
00665             the HAL_PCD_SOFCallback could be implemented in the user file
00666    */
00667 }
00668
00669 /**
00670   * @brief  USB Reset callbacks
00671   * @param  hpcd: PCD handle
00672   * @retval None
00673   */
00674  __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
00675 {
00676   /* NOTE : This function Should not be modified, when the callback is needed,
00677             the HAL_PCD_ResetCallback could be implemented in the user file
00678    */
00679 }
00680
00681
00682 /**
00683   * @brief  Suspend event callbacks
00684   * @param  hpcd: PCD handle
00685   * @retval None
00686   */
00687  __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
00688 {
00689   /* NOTE : This function Should not be modified, when the callback is needed,
00690             the HAL_PCD_SuspendCallback could be implemented in the user file
00691    */
00692 }
00693
00694 /**
00695   * @brief  Resume event callbacks
00696   * @param  hpcd: PCD handle
00697   * @retval None
00698   */
00699  __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
00700 {
00701   /* NOTE : This function Should not be modified, when the callback is needed,
00702             the HAL_PCD_ResumeCallback could be implemented in the user file
00703    */
00704 }
00705
00706 /**
00707   * @brief  Incomplete ISO OUT callbacks
00708   * @param  hpcd: PCD handle
00709   * @param  epnum: endpoint number
00710   * @retval None
00711   */
00712  __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00713 {
00714   /* NOTE : This function Should not be modified, when the callback is needed,
00715             the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
00716    */
00717 }
00718
00719 /**
00720   * @brief  Incomplete ISO IN  callbacks
00721   * @param  hpcd: PCD handle
00722   * @param  epnum: endpoint number
00723   * @retval None
00724   */
00725  __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00726 {
00727   /* NOTE : This function Should not be modified, when the callback is needed,
00728             the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
00729    */
00730 }
00731
00732 /**
00733   * @brief  Connection event callbacks
00734   * @param  hpcd: PCD handle
00735   * @retval None
00736   */
00737  __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
00738 {
00739   /* NOTE : This function Should not be modified, when the callback is needed,
00740             the HAL_PCD_ConnectCallback could be implemented in the user file
00741    */
00742 }
00743
00744 /**
00745   * @brief  Disconnection event callbacks
00746   * @param  hpcd: PCD handle
00747   * @retval None
00748   */
00749  __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
00750 {
00751   /* NOTE : This function Should not be modified, when the callback is needed,
00752             the HAL_PCD_DisconnectCallback could be implemented in the user file
00753    */
00754 }
00755
00756 /**
00757   * @}
00758   */
00759
00760 /** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
00761  *  @brief   management functions
00762  *
00763 @verbatim
00764  ===============================================================================
00765                       ##### Peripheral Control functions #####
00766  ===============================================================================
00767     [..]
00768     This subsection provides a set of functions allowing to control the PCD data
00769     transfers.
00770
00771 @endverbatim
00772   * @{
00773   */
00774
00775 /**
00776   * @brief  Connect the USB device
00777   * @param  hpcd: PCD handle
00778   * @retval HAL status
00779   */
00780 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
00781 {
00782   __HAL_LOCK(hpcd);
00783   USB_DevConnect(hpcd->Instance);
00784   __HAL_UNLOCK(hpcd);
00785   return HAL_OK;
00786 }
00787
00788 /**
00789   * @brief  Disconnect the USB device
00790   * @param  hpcd: PCD handle
00791   * @retval HAL status
00792   */
00793 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
00794 {
00795   __HAL_LOCK(hpcd);
00796   USB_DevDisconnect(hpcd->Instance);
00797   __HAL_UNLOCK(hpcd);
00798   return HAL_OK;
00799 }
00800
00801 /**
00802   * @brief  Set the USB Device address
00803   * @param  hpcd: PCD handle
00804   * @param  address: new device address
00805   * @retval HAL status
00806   */
00807 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
00808 {
00809   __HAL_LOCK(hpcd);
00810   USB_SetDevAddress(hpcd->Instance, address);
00811   __HAL_UNLOCK(hpcd);
00812   return HAL_OK;
00813 }
00814 /**
00815   * @brief  Open and configure an endpoint
00816   * @param  hpcd: PCD handle
00817   * @param  ep_addr: endpoint address
00818   * @param  ep_mps: endpoint max packet size
00819   * @param  ep_type: endpoint type
00820   * @retval HAL status
00821   */
00822 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
00823 {
00824   HAL_StatusTypeDef  ret = HAL_OK;
00825   USB_OTG_EPTypeDef *ep;
00826
00827   if ((ep_addr & 0x80) == 0x80)
00828   {
00829     ep = &hpcd->IN_ep[ep_addr & 0x7F];
00830   }
00831   else
00832   {
00833     ep = &hpcd->OUT_ep[ep_addr & 0x7F];
00834   }
00835   ep->num   = ep_addr & 0x7F;
00836
00837   ep->is_in = (0x80 & ep_addr) != 0;
00838   ep->maxpacket = ep_mps;
00839   ep->type = ep_type;
00840   if (ep->is_in)
00841   {
00842     /* Assign a Tx FIFO */
00843     ep->tx_fifo_num = ep->num;
00844   }
00845   /* Set initial data PID. */
00846   if (ep_type == EP_TYPE_BULK )
00847   {
00848     ep->data_pid_start = 0;
00849   }
00850
00851   __HAL_LOCK(hpcd);
00852   USB_ActivateEndpoint(hpcd->Instance , ep);
00853   __HAL_UNLOCK(hpcd);
00854   return ret;
00855 }
00856
00857
00858 /**
00859   * @brief  Deactivate an endpoint
00860   * @param  hpcd: PCD handle
00861   * @param  ep_addr: endpoint address
00862   * @retval HAL status
00863   */
00864 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
00865 {
00866   USB_OTG_EPTypeDef *ep;
00867
00868   if ((ep_addr & 0x80) == 0x80)
00869   {
00870     ep = &hpcd->IN_ep[ep_addr & 0x7F];
00871   }
00872   else
00873   {
00874     ep = &hpcd->OUT_ep[ep_addr & 0x7F];
00875   }
00876   ep->num   = ep_addr & 0x7F;
00877
00878   ep->is_in = (0x80 & ep_addr) != 0;
00879
00880   __HAL_LOCK(hpcd);
00881   USB_DeactivateEndpoint(hpcd->Instance , ep);
00882   __HAL_UNLOCK(hpcd);
00883   return HAL_OK;
00884 }
00885
00886
00887 /**
00888   * @brief  Receive an amount of data
00889   * @param  hpcd: PCD handle
00890   * @param  ep_addr: endpoint address
00891   * @param  pBuf: pointer to the reception buffer
00892   * @param  len: amount of data to be received
00893   * @retval HAL status
00894   */
00895 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
00896 {
00897   USB_OTG_EPTypeDef *ep;
00898
00899   ep = &hpcd->OUT_ep[ep_addr & 0x7F];
00900
00901   /*setup and start the Xfer */
00902   ep->xfer_buff = pBuf;
00903   ep->xfer_len = len;
00904   ep->xfer_count = 0;
00905   ep->is_in = 0;
00906   ep->num = ep_addr & 0x7F;
00907
00908   if (hpcd->Init.dma_enable == 1)
00909   {
00910     ep->dma_addr = (uint32_t)pBuf;
00911   }
00912
00913   if ((ep_addr & 0x7F) == 0 )
00914   {
00915     USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
00916   }
00917   else
00918   {
00919     USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
00920   }
00921
00922   return HAL_OK;
00923 }
00924
00925 /**
00926   * @brief  Get Received Data Size
00927   * @param  hpcd: PCD handle
00928   * @param  ep_addr: endpoint address
00929   * @retval Data Size
00930   */
00931 uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
00932 {
00933   return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
00934 }
00935 /**
00936   * @brief  Send an amount of data
00937   * @param  hpcd: PCD handle
00938   * @param  ep_addr: endpoint address
00939   * @param  pBuf: pointer to the transmission buffer
00940   * @param  len: amount of data to be sent
00941   * @retval HAL status
00942   */
00943 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
00944 {
00945   USB_OTG_EPTypeDef *ep;
00946
00947   ep = &hpcd->IN_ep[ep_addr & 0x7F];
00948
00949   /*setup and start the Xfer */
00950   ep->xfer_buff = pBuf;
00951   ep->xfer_len = len;
00952   ep->xfer_count = 0;
00953   ep->is_in = 1;
00954   ep->num = ep_addr & 0x7F;
00955
00956   if (hpcd->Init.dma_enable == 1)
00957   {
00958     ep->dma_addr = (uint32_t)pBuf;
00959   }
00960
00961   if ((ep_addr & 0x7F) == 0 )
00962   {
00963     USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
00964   }
00965   else
00966   {
00967     USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
00968   }
00969
00970   return HAL_OK;
00971 }
00972
00973 /**
00974   * @brief  Set a STALL condition over an endpoint
00975   * @param  hpcd: PCD handle
00976   * @param  ep_addr: endpoint address
00977   * @retval HAL status
00978   */
00979 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
00980 {
00981   USB_OTG_EPTypeDef *ep;
00982
00983   if ((0x80 & ep_addr) == 0x80)
00984   {
00985     ep = &hpcd->IN_ep[ep_addr & 0x7F];
00986   }
00987   else
00988   {
00989     ep = &hpcd->OUT_ep[ep_addr];
00990   }
00991
00992   ep->is_stall = 1;
00993   ep->num   = ep_addr & 0x7F;
00994   ep->is_in = ((ep_addr & 0x80) == 0x80);
00995
00996
00997   __HAL_LOCK(hpcd);
00998   USB_EPSetStall(hpcd->Instance , ep);
00999   if((ep_addr & 0x7F) == 0)
01000   {
01001     USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
01002   }
01003   __HAL_UNLOCK(hpcd);
01004
01005   return HAL_OK;
01006 }
01007
01008 /**
01009   * @brief  Clear a STALL condition over in an endpoint
01010   * @param  hpcd: PCD handle
01011   * @param  ep_addr: endpoint address
01012   * @retval HAL status
01013   */
01014 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01015 {
01016   USB_OTG_EPTypeDef *ep;
01017
01018   if ((0x80 & ep_addr) == 0x80)
01019   {
01020     ep = &hpcd->IN_ep[ep_addr & 0x7F];
01021   }
01022   else
01023   {
01024     ep = &hpcd->OUT_ep[ep_addr];
01025   }
01026
01027   ep->is_stall = 0;
01028   ep->num   = ep_addr & 0x7F;
01029   ep->is_in = ((ep_addr & 0x80) == 0x80);
01030
01031   __HAL_LOCK(hpcd);
01032   USB_EPClearStall(hpcd->Instance , ep);
01033   __HAL_UNLOCK(hpcd);
01034
01035   return HAL_OK;
01036 }
01037
01038 /**
01039   * @brief  Flush an endpoint
01040   * @param  hpcd: PCD handle
01041   * @param  ep_addr: endpoint address
01042   * @retval HAL status
01043   */
01044 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01045 {
01046   __HAL_LOCK(hpcd);
01047
01048   if ((ep_addr & 0x80) == 0x80)
01049   {
01050     USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);
01051   }
01052   else
01053   {
01054     USB_FlushRxFifo(hpcd->Instance);
01055   }
01056
01057   __HAL_UNLOCK(hpcd);
01058
01059   return HAL_OK;
01060 }
01061
01062 /**
01063   * @brief  HAL_PCD_ActivateRemoteWakeup : Active remote wake-up signalling
01064   * @param  hpcd: PCD handle
01065   * @retval HAL status
01066   */
01067 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
01068 {
01069   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
01070
01071   if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
01072   {
01073     /* Activate Remote wake-up signaling */
01074     USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
01075   }
01076   return HAL_OK;
01077 }
01078
01079 /**
01080   * @brief  HAL_PCD_DeActivateRemoteWakeup : de-active remote wake-up signalling
01081   * @param  hpcd: PCD handle
01082   * @retval HAL status
01083   */
01084 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
01085 {
01086   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
01087
01088   /* De-activate Remote wake-up signaling */
01089    USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
01090   return HAL_OK;
01091 }
01092 /**
01093   * @}
01094   */
01095
01096 /** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
01097  *  @brief   Peripheral State functions
01098  *
01099 @verbatim
01100  ===============================================================================
01101                       ##### Peripheral State functions #####
01102  ===============================================================================
01103     [..]
01104     This subsection permits to get in run-time the status of the peripheral
01105     and the data flow.
01106
01107 @endverbatim
01108   * @{
01109   */
01110
01111 /**
01112   * @brief  Return the PCD state
01113   * @param  hpcd: PCD handle
01114   * @retval HAL state
01115   */
01116 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
01117 {
01118   return hpcd->State;
01119 }
01120 /**
01121   * @}
01122   */
01123
01124 /**
01125   * @}
01126   */
01127
01128 /* Private functions ---------------------------------------------------------*/
01129 /** @addtogroup PCD_Private_Functions
01130   * @{
01131   */
01132
01133 /**
01134   * @brief  DCD_WriteEmptyTxFifo
01135   *         check FIFO for the next packet to be loaded
01136   * @param  hpcd: PCD handle
01137   * @param  epnum : endpoint number
01138   * @retval HAL status
01139   */
01140 static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
01141 {
01142   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
01143   USB_OTG_EPTypeDef *ep;
01144   int32_t len = 0;
01145   uint32_t len32b;
01146   uint32_t fifoemptymsk = 0;
01147
01148   ep = &hpcd->IN_ep[epnum];
01149   len = ep->xfer_len - ep->xfer_count;
01150
01151   if (len > ep->maxpacket)
01152   {
01153     len = ep->maxpacket;
01154   }
01155
01156
01157   len32b = (len + 3) / 4;
01158
01159   while  ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&
01160           ep->xfer_count < ep->xfer_len &&
01161             ep->xfer_len != 0)
01162   {
01163     /* Write the FIFO */
01164     len = ep->xfer_len - ep->xfer_count;
01165
01166     if (len > ep->maxpacket)
01167     {
01168       len = ep->maxpacket;
01169     }
01170     len32b = (len + 3) / 4;
01171
01172     USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable);
01173
01174     ep->xfer_buff  += len;
01175     ep->xfer_count += len;
01176   }
01177
01178   if(len <= 0)
01179   {
01180     fifoemptymsk = 0x1 << epnum;
01181     USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
01182
01183   }
01184
01185   return HAL_OK;
01186 }
01187
01188 /**
01189   * @}
01190   */
01191
01192 #endif /* HAL_PCD_MODULE_ENABLED */
01193 /**
01194   * @}
01195   */
01196
01197 /**
01198   * @}
01199   */
01200
01201 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_pcd.h Source File

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stm32h7xx_hal_pcd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_pcd.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of PCD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_PCD_H
00040 #define __STM32H7xx_HAL_PCD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_ll_usb.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup PCD
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup PCD_Exported_Types PCD Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  PCD State structure definition
00064   */
00065 typedef enum
00066 {
00067   HAL_PCD_STATE_RESET   = 0x00,
00068   HAL_PCD_STATE_READY   = 0x01,
00069   HAL_PCD_STATE_ERROR   = 0x02,
00070   HAL_PCD_STATE_BUSY    = 0x03,
00071   HAL_PCD_STATE_TIMEOUT = 0x04
00072 } PCD_StateTypeDef;
00073
00074 /* Device LPM suspend state */
00075 typedef enum
00076 {
00077   LPM_L0 = 0x00, /* on */
00078   LPM_L1 = 0x01, /* LPM L1 sleep */
00079   LPM_L2 = 0x02, /* suspend */
00080   LPM_L3 = 0x03, /* off */
00081 }PCD_LPM_StateTypeDef;
00082
00083 typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;
00084 typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;
00085 typedef USB_OTG_EPTypeDef      PCD_EPTypeDef ;
00086
00087 /**
00088   * @brief  PCD Handle Structure definition
00089   */
00090 typedef struct
00091 {
00092   PCD_TypeDef             *Instance;   /*!< Register base address              */
00093   PCD_InitTypeDef         Init;       /*!< PCD required parameters            */
00094   PCD_EPTypeDef           IN_ep[15];  /*!< IN endpoint parameters             */
00095   PCD_EPTypeDef           OUT_ep[15]; /*!< OUT endpoint parameters            */
00096   HAL_LockTypeDef         Lock;       /*!< PCD peripheral status              */
00097   __IO PCD_StateTypeDef   State;      /*!< PCD communication state            */
00098   uint32_t                Setup[12];  /*!< Setup packet buffer                */
00099   PCD_LPM_StateTypeDef    LPM_State;    /*!< LPM State                          */
00100   uint32_t                BESL;
00101   uint32_t                lpm_active;   /*!< Enable or disable the Link Power Management .
00102                                         This parameter can be set to ENABLE or DISABLE */
00103    uint32_t battery_charging_active;     /*!< Enable or disable Battery charging.
00104                                         This parameter can be set to ENABLE or DISABLE                      */
00105
00106   void                    *pData;       /*!< Pointer to upper stack Handler */
00107 } PCD_HandleTypeDef;
00108
00109 /**
00110   * @}
00111   */
00112
00113 /* Include PCD HAL Extension module */
00114 #include "stm32h7xx_hal_pcd_ex.h"
00115
00116 /* Exported constants --------------------------------------------------------*/
00117 /** @defgroup PCD_Exported_Constants PCD Exported Constants
00118   * @{
00119   */
00120
00121 /** @defgroup PCD_Speed PCD Speed
00122   * @{
00123   */
00124 #define PCD_SPEED_HIGH               0
00125 #define PCD_SPEED_HIGH_IN_FULL       1
00126 #define PCD_SPEED_FULL               2
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup PCD_PHY_Module PCD PHY Module
00132   * @{
00133   */
00134 #define PCD_PHY_ULPI                 1
00135 #define PCD_PHY_EMBEDDED             2
00136 /**
00137   * @}
00138   */
00139
00140 /** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
00141   * @{
00142   */
00143 #ifndef USBD_HS_TRDT_VALUE
00144  #define USBD_HS_TRDT_VALUE           9
00145 #endif /* USBD_HS_TRDT_VALUE */
00146 #ifndef USBD_FS_TRDT_VALUE
00147  #define USBD_FS_TRDT_VALUE           5
00148 #endif /* USBD_HS_TRDT_VALUE */
00149
00150 /**
00151   * @}
00152   */
00153
00154 /**
00155   * @}
00156   */
00157
00158 /* Exported macros -----------------------------------------------------------*/
00159 /** @defgroup PCD_Exported_Macros PCD Exported Macros
00160  *  @brief macros to handle interrupts and specific clock configurations
00161  * @{
00162  */
00163 #define __HAL_PCD_ENABLE(__HANDLE__)                   USB_EnableGlobalInt ((__HANDLE__)->Instance)
00164 #define __HAL_PCD_DISABLE(__HANDLE__)                  USB_DisableGlobalInt ((__HANDLE__)->Instance)
00165
00166 #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
00167 #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
00168 #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
00169
00170
00171 #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)             *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
00172                                                        ~(USB_OTG_PCGCCTL_STOPCLK)
00173
00174 #define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)               *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
00175
00176 #define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
00177
00178 #define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE      ((uint32_t)0x08)
00179 #define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE     ((uint32_t)0x0C)
00180 #define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE        ((uint32_t)0x10)
00181
00182 #define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE      ((uint32_t)0x08)
00183 #define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE     ((uint32_t)0x0C)
00184 #define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE        ((uint32_t)0x10)
00185
00186 #define USB_OTG_HS_WAKEUP_EXTI_LINE              ((uint32_t)EXTI_IMR2_IM43)  /*!< External interrupt line 43 Connected to the USB HS EXTI Line */
00187
00188
00189 #define USB_OTG_FS_WAKEUP_EXTI_LINE              ((uint32_t)EXTI_IMR2_IM44)  /*!< External interrupt line 44 Connected to the USB FS EXTI Line */
00190
00191
00192 /* HS */
00193 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT()    EXTI_D1->IMR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
00194 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT()   EXTI_D1->IMR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
00195 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG()     EXTI_D1->PR2 & (USB_OTG_HS_WAKEUP_EXTI_LINE)
00196 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI_D1->PR2 = (USB_OTG_HS_WAKEUP_EXTI_LINE)
00197
00198 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
00199                                                           EXTI->RTSR2 |= USB_OTG_HS_WAKEUP_EXTI_LINE
00200
00201 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()  EXTI->FTSR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
00202                                                             EXTI->RTSR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
00203
00204 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()   EXTI->RTSR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
00205                                                                     EXTI->FTSR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE;)\
00206                                                                     EXTI->RTSR2 |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
00207                                                                     EXTI->FTSR2 |= USB_OTG_HS_WAKEUP_EXTI_LINE
00208
00209 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT()   (EXTI->SWIER2 |= USB_OTG_HS_WAKEUP_EXTI_LINE)
00210
00211
00212
00213
00214 /* FS */
00215 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()    EXTI_D1->IMR2 |= USB_OTG_FS_WAKEUP_EXTI_LINE
00216 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()   EXTI_D1->IMR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
00217 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG()     EXTI_D1->PR2 & (USB_OTG_FS_WAKEUP_EXTI_LINE)
00218 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI_D1->PR2 = USB_OTG_FS_WAKEUP_EXTI_LINE
00219 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
00220                                                           EXTI->RTSR2 |= USB_OTG_FS_WAKEUP_EXTI_LINE
00221
00222 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()  EXTI->FTSR2 |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
00223                                                             EXTI->RTSR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
00224
00225 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()  EXTI->RTSR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
00226                                                                    EXTI->FTSR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
00227                                                                    EXTI->RTSR2 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
00228                                                                    EXTI->FTSR2 |= USB_OTG_FS_WAKEUP_EXTI_LINE
00229
00230 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT()  (EXTI->SWIER2 |= USB_OTG_FS_WAKEUP_EXTI_LINE)
00231
00232 /* Exported functions --------------------------------------------------------*/
00233 /** @addtogroup PCD_Exported_Functions PCD Exported Functions
00234   * @{
00235   */
00236
00237 /* Initialization/de-initialization functions  ********************************/
00238 /** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
00239   * @{
00240   */
00241 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
00242 HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
00243 void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
00244 void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
00245 /**
00246   * @}
00247   */
00248
00249 /* I/O operation functions  ***************************************************/
00250 /* Non-Blocking mode: Interrupt */
00251 /** @addtogroup PCD_Exported_Functions_Group2 IO operation functions
00252   * @{
00253   */
00254 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
00255 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
00256 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
00257
00258 void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00259 void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00260 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
00261 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
00262 void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
00263 void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
00264 void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
00265 void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00266 void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00267 void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
00268 void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
00269 /**
00270   * @}
00271   */
00272
00273 /* Peripheral Control functions  **********************************************/
00274 /** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
00275   * @{
00276   */
00277 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
00278 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
00279 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
00280 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
00281 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00282 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00283 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00284 uint16_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00285 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00286 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00287 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00288 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
00289 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
00290 /**
00291   * @}
00292   */
00293
00294 /* Peripheral State functions  ************************************************/
00295 /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
00296   * @{
00297   */
00298 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
00299 /**
00300   * @}
00301   */
00302
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup PCD_Instance_definition PCD Instance definition
00308   * @{
00309   */
00310 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS) || \
00311                                        ((INSTANCE) == USB2_OTG_FS))
00312 /**
00313   * @}
00314   */
00315
00316 /**
00317   * @}
00318   */
00319
00320 /**
00321   * @}
00322   */
00323
00324 /**
00325   * @}
00326   */
00327
00328 #ifdef __cplusplus
00329 }
00330 #endif
00331
00332
00333 #endif /* __STM32H7xx_HAL_PCD_H */
00334
00335 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_pcd_ex.c Source File

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stm32h7xx_hal_pcd_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_pcd_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   PCD HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the USB Peripheral Controller:
00010   *           + Extended features functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00016   *
00017   * Redistribution and use in source and binary forms, with or without modification,
00018   * are permitted provided that the following conditions are met:
00019   *   1. Redistributions of source code must retain the above copyright notice,
00020   *      this list of conditions and the following disclaimer.
00021   *   2. Redistributions in binary form must reproduce the above copyright notice,
00022   *      this list of conditions and the following disclaimer in the documentation
00023   *      and/or other materials provided with the distribution.
00024   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00025   *      may be used to endorse or promote products derived from this software
00026   *      without specific prior written permission.
00027   *
00028   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00029   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00030   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00031   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00032   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00033   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00034   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00035   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00036   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00037   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00038   *
00039   ******************************************************************************
00040   */
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32h7xx_hal.h"
00044
00045 /** @addtogroup STM32H7xx_HAL_Driver
00046   * @{
00047   */
00048
00049 /** @defgroup PCDEx PCDEx
00050   * @brief PCD Extended HAL module driver
00051   * @{
00052   */
00053 #ifdef HAL_PCD_MODULE_ENABLED
00054
00055 /* Private types -------------------------------------------------------------*/
00056 /* Private variables ---------------------------------------------------------*/
00057 /* Private constants ---------------------------------------------------------*/
00058 /* Private macros ------------------------------------------------------------*/
00059 /* Private functions ---------------------------------------------------------*/
00060 /* Exported functions --------------------------------------------------------*/
00061
00062 /** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
00063   * @{
00064   */
00065
00066 /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
00067   * @brief    PCDEx control functions
00068  *
00069 @verbatim
00070  ===============================================================================
00071                  ##### Extended features functions #####
00072  ===============================================================================
00073     [..]  This section provides functions allowing to:
00074       (+) Update FIFO configuration
00075
00076 @endverbatim
00077   * @{
00078   */
00079
00080 /**
00081   * @brief  Set Tx FIFO
00082   * @param  hpcd: PCD handle
00083   * @param  fifo: The number of Tx fifo
00084   * @param  size: Fifo size
00085   * @retval HAL status
00086   */
00087 HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
00088 {
00089   uint8_t i = 0;
00090   uint32_t Tx_Offset = 0;
00091
00092   /*  TXn min size = 16 words. (n  : Transmit FIFO index)
00093       When a TxFIFO is not used, the Configuration should be as follows:
00094           case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)
00095          --> Txm can use the space allocated for Txn.
00096          case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)
00097          --> Txn should be configured with the minimum space of 16 words
00098      The FIFO is used optimally when used TxFIFOs are allocated in the top
00099          of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
00100      When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
00101
00102   Tx_Offset = hpcd->Instance->GRXFSIZ;
00103
00104   if(fifo == 0)
00105   {
00106     hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset;
00107   }
00108   else
00109   {
00110     Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
00111     for (i = 0; i < (fifo - 1); i++)
00112     {
00113       Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
00114     }
00115
00116     /* Multiply Tx_Size by 2 to get higher performance */
00117     hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset;
00118
00119   }
00120
00121   return HAL_OK;
00122 }
00123
00124 /**
00125   * @brief  Set Rx FIFO
00126   * @param  hpcd: PCD handle
00127   * @param  size: Size of Rx fifo
00128   * @retval HAL status
00129   */
00130 HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
00131 {
00132   hpcd->Instance->GRXFSIZ = size;
00133
00134   return HAL_OK;
00135 }
00136
00137 /**
00138   * @brief  HAL_PCDEx_ActivateLPM : active LPM Feature
00139   * @param  hpcd: PCD handle
00140   * @retval HAL status
00141   */
00142 HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
00143 {
00144   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00145
00146   hpcd->lpm_active = ENABLE;
00147   hpcd->LPM_State = LPM_L0;
00148   USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
00149   USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
00150
00151   return HAL_OK;
00152 }
00153
00154 /**
00155   * @brief  HAL_PCDEx_DeActivateLPM : de-active LPM feature
00156   * @param  hpcd: PCD handle
00157   * @retval HAL status
00158   */
00159 HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
00160 {
00161   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00162
00163   hpcd->lpm_active = DISABLE;
00164   USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
00165   USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
00166
00167   return HAL_OK;
00168 }
00169
00170 /**
00171   * @brief  Handle BatteryCharging Process.
00172   * @param  hpcd: PCD handle
00173   * @retval HAL status
00174   */
00175 void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
00176 {
00177   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00178   uint32_t tickstart = HAL_GetTick();
00179
00180   /* Start BCD When device is connected */
00181   if (USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS)
00182   {
00183     /* Enable DCD : Data Contact Detect */
00184     USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
00185
00186     /* Wait Detect flag or a timeout is happen*/
00187     while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0)
00188     {
00189       /* Check for the Timeout */
00190       if((HAL_GetTick() - tickstart ) > 1000)
00191       {
00192         HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
00193         return;
00194       }
00195     }
00196
00197     /* Right response got */
00198     HAL_Delay(100);
00199
00200       HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
00201
00202     /*Primary detection: checks if connected to Standard Downstream Port
00203     (without charging capability) */
00204     USBx->GCCFG &=~ USB_OTG_GCCFG_DCDEN;
00205     USBx->GCCFG |=  USB_OTG_GCCFG_PDEN;
00206     HAL_Delay(100);
00207
00208     if (!(USBx->GCCFG & USB_OTG_GCCFG_PDET))
00209     {
00210       /* Case of Standard Downstream Port */
00211       HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
00212     }
00213     else
00214     {
00215       /* start secondary detection to check connection to Charging Downstream
00216       Port or Dedicated Charging Port */
00217       USBx->GCCFG &=~ USB_OTG_GCCFG_PDEN;
00218       USBx->GCCFG |=  USB_OTG_GCCFG_SDEN;
00219       HAL_Delay(100);
00220
00221       if ((USBx->GCCFG) & USB_OTG_GCCFG_SDET)
00222       {
00223         /* case Dedicated Charging Port  */
00224         HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
00225       }
00226       else
00227       {
00228         /* case Charging Downstream Port  */
00229         HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
00230       }
00231     }
00232     /* Battery Charging capability discovery finished */
00233     HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
00234   }
00235 }
00236
00237 /**
00238   * @brief  Activate BatteryCharging feature.
00239   * @param  hpcd: PCD handle
00240   * @retval HAL status
00241   */
00242 HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
00243 {
00244   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00245
00246   hpcd->battery_charging_active = ENABLE;
00247   USBx->GCCFG |= (USB_OTG_GCCFG_BCDEN);
00248       /* Enable DCD : Data Contact Detect */
00249   USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
00250
00251   return HAL_OK;
00252 }
00253
00254 /**
00255   * @brief  Deactivate BatteryCharging feature.
00256   * @param  hpcd: PCD handle
00257   * @retval HAL status
00258   */
00259 HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
00260 {
00261   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00262   hpcd->battery_charging_active = DISABLE;
00263   USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
00264   return HAL_OK;
00265 }
00266
00267
00268 /**
00269   * @brief  Send LPM message to user layer callback.
00270   * @param  hpcd: PCD handle
00271   * @param  msg: LPM message
00272   * @retval HAL status
00273   */
00274 __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
00275 {
00276   /* Prevent unused argument(s) compilation warning */
00277   UNUSED(hpcd);
00278   UNUSED(msg);
00279
00280   /* NOTE : This function should not be modified, when the callback is needed,
00281             the HAL_PCDEx_LPM_Callback could be implemented in the user file
00282    */
00283 }
00284
00285 /**
00286   * @brief  Send BatteryCharging message to user layer callback.
00287   * @param  hpcd: PCD handle
00288   * @param  msg: LPM message
00289   * @retval HAL status
00290   */
00291 __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
00292 {
00293   /* Prevent unused argument(s) compilation warning */
00294   UNUSED(hpcd);
00295   UNUSED(msg);
00296
00297   /* NOTE : This function should not be modified, when the callback is needed,
00298             the HAL_PCDEx_BCD_Callback could be implemented in the user file
00299    */
00300 }
00301
00302 /**
00303   * @}
00304   */
00305
00306 /**
00307   * @}
00308   */
00309
00310 #endif /* HAL_PCD_MODULE_ENABLED */
00311 /**
00312   * @}
00313   */
00314
00315 /**
00316   * @}
00317   */
00318
00319 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_pcd_ex.h Source File

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stm32h7xx_hal_pcd_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_pcd_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of PCD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_PCD_EX_H
00040 #define __STM32H7xx_HAL_PCD_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup PCDEx
00054   * @{
00055   */
00056 /* Exported types ------------------------------------------------------------*/
00057 typedef enum
00058 {
00059   PCD_LPM_L0_ACTIVE = 0x00, /* on */
00060   PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
00061 }PCD_LPM_MsgTypeDef;
00062
00063
00064 typedef enum
00065 {
00066   PCD_BCD_ERROR                     = 0xFF,
00067   PCD_BCD_CONTACT_DETECTION         = 0xFE,
00068   PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,
00069   PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,
00070   PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,
00071   PCD_BCD_DISCOVERY_COMPLETED       = 0x00,
00072
00073 }PCD_BCD_MsgTypeDef;
00074
00075
00076 /* Exported constants --------------------------------------------------------*/
00077 /* Exported macros -----------------------------------------------------------*/
00078 /* Exported functions --------------------------------------------------------*/
00079 /** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
00080   * @{
00081   */
00082 /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
00083   * @{
00084   */
00085 HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
00086 HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
00087 HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
00088 HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
00089 HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
00090 HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
00091 void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
00092 void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
00093 void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
00094
00095 /**
00096   * @}
00097   */
00098
00099 /**
00100   * @}
00101   */
00102
00103 /**
00104   * @}
00105   */
00106
00107 /**
00108   * @}
00109   */
00110
00111 #ifdef __cplusplus
00112 }
00113 #endif
00114
00115
00116 #endif /* __STM32H7xx_HAL_PCD_EX_H */
00117
00118 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_pwr.c Source File

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stm32h7xx_hal_pwr.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_pwr.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   PWR HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Power Controller (PWR) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + Peripheral Control functions
00012   *
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00017   *
00018   * Redistribution and use in source and binary forms, with or without modification,
00019   * are permitted provided that the following conditions are met:
00020   *   1. Redistributions of source code must retain the above copyright notice,
00021   *      this list of conditions and the following disclaimer.
00022   *   2. Redistributions in binary form must reproduce the above copyright notice,
00023   *      this list of conditions and the following disclaimer in the documentation
00024   *      and/or other materials provided with the distribution.
00025   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00026   *      may be used to endorse or promote products derived from this software
00027   *      without specific prior written permission.
00028   *
00029   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00030   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00031   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00032   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00033   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00034   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00035   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00036   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00037   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00038   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00039   *
00040   ******************************************************************************
00041   */
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32h7xx_hal.h"
00045
00046 /** @addtogroup STM32H7xx_HAL_Driver
00047   * @{
00048   */
00049
00050 /** @defgroup PWR PWR
00051   * @brief PWR HAL module driver
00052   * @{
00053   */
00054
00055 #ifdef HAL_PWR_MODULE_ENABLED
00056
00057 /* Private typedef -----------------------------------------------------------*/
00058 /* Private define ------------------------------------------------------------*/
00059 /** @addtogroup PWR_Private_Constants PWR Private Constants
00060   * @{
00061   */
00062
00063 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
00064   * @{
00065   */
00066 #define PVD_MODE_IT              ((uint32_t)0x00010000U)
00067 #define PVD_MODE_EVT             ((uint32_t)0x00020000U)
00068 #define PVD_RISING_EDGE          ((uint32_t)0x00000001U)
00069 #define PVD_FALLING_EDGE         ((uint32_t)0x00000002U)
00070 #define PVD_RISING_FALLING_EDGE  ((uint32_t)0x00000003U)
00071 /**
00072   * @}
00073   */
00074
00075 /**
00076   * @}
00077   */
00078 /* Private macro -------------------------------------------------------------*/
00079 /* Private variables ---------------------------------------------------------*/
00080 /* Private function prototypes -----------------------------------------------*/
00081 /* Private functions ---------------------------------------------------------*/
00082
00083 /** @defgroup PWR_Exported_Functions PWR Exported Functions
00084   * @{
00085   */
00086
00087 /** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions
00088   *  @brief    Initialization and De-Initialization functions
00089   *
00090 @verbatim
00091  ===============================================================================
00092               ##### Initialization and De-Initialization functions #####
00093  ===============================================================================
00094     [..]
00095       After reset, the backup domain (RTC registers, RTC backup data
00096       registers and backup SRAM) is protected against possible unwanted
00097       write accesses.
00098       To enable access to the RTC Domain and RTC registers, proceed as follows:
00099         (+) Enable the Power Controller (PWR) APB1 interface clock using the
00100             __HAL_RCC_PWR_CLK_ENABLE() macro.
00101         (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
00102
00103 @endverbatim
00104   * @{
00105   */
00106
00107 /**
00108   * @brief  Deinitialize the HAL PWR peripheral registers to their default reset values.
00109   * @note   This functionality is not available in this product.
00110   *         The prototype is kept just to maintain compatibility with other products.
00111   * @retval None
00112   */
00113 void HAL_PWR_DeInit(void)
00114 {
00115 }
00116
00117 /**
00118   * @brief  Enable access to the backup domain (RTC registers, RTC
00119   *         backup data registers and backup SRAM).
00120   * @note   If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
00121   *         Backup Domain Access should be kept enabled.
00122   * @retval None
00123   */
00124 void HAL_PWR_EnableBkUpAccess(void)
00125 {
00126   /* Enable access to RTC and backup registers */
00127   SET_BIT(PWR->CR1, PWR_CR1_DBP);
00128 }
00129
00130 /**
00131   * @brief  Disable access to the backup domain (RTC registers, RTC
00132   *         backup data registers and backup SRAM).
00133   * @note   If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
00134   *         Backup Domain Access should be kept enabled.
00135   * @retval None
00136   */
00137 void HAL_PWR_DisableBkUpAccess(void)
00138 {
00139   /* Disable access to RTC and backup registers */
00140   CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
00141 }
00142
00143 /**
00144   * @}
00145   */
00146
00147 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
00148   *  @brief   Low Power modes configuration functions
00149   *
00150 @verbatim
00151
00152  ===============================================================================
00153                  ##### Peripheral Control functions #####
00154  ===============================================================================
00155
00156     *** PVD configuration ***
00157     =========================
00158     [..]
00159       (+) The PVD is used to monitor the VDD power supply by comparing it to a
00160           threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1 register).
00161       (+) A PVDO flag is available to indicate if VDD is higher or lower
00162           than the PVD threshold. This event is internally connected to the EXTI
00163           line 16 to generate an interrupt if enabled.
00164           It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
00165       (+) The PVD is stopped in Standby mode.
00166
00167     *** Wake-up pin configuration ***
00168     ================================
00169     [..]
00170       (+) Wake-up pin is used to wake up the system from Standby mode.
00171           The pin pull is configurable through the WKUPEPR register to be in No pull-up, Pull-up and Pull-down.
00172           The pin polarity is configurable through the WKUPEPR register to be active on rising or falling edges.
00173       (+) There are up to six Wake-up pin in the STM32H7 devices family.
00174
00175     *** Low Power modes configuration ***
00176     =====================================
00177     [..]
00178      The device present 3 principles low-power modes features:
00179       (+) SLEEP mode: Cortex-M7 core stopped and D1, D2 and D3 peripherals kept running.
00180       (+) STOP mode: all clocks are stoppedand the regulator running in main or low power mode.
00181       (+) STANDBY mode: D1, D2 and D3 domains enter DSTANDBY mode and the VCORE supply
00182                         regulator is powered off.
00183
00184    *** SLEEP mode ***
00185    ==================
00186     [..]
00187       (+) Entry:
00188         The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, SLEEPEntry)
00189         function.
00190
00191           (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
00192           (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
00193
00194       -@@- The Regulator parameter is not used for the STM32H7 family
00195               and is kept as parameter just to maintain compatibility with the
00196               lower power families (STM32L).
00197       (+) Exit:
00198         Any peripheral interrupt acknowledged by the nested vectored interrupt
00199         controller (NVIC) can wake up the device from Sleep mode.
00200
00201    *** STOP mode ***
00202    =================
00203     [..]
00204       In system Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
00205       and the HSE RC oscillators are disabled. Internal SRAM and register contents
00206       are preserved.
00207       The voltage regulator can be configured either in normal or low-power mode.
00208       To minimize the consumption In Stop mode, FLASH can be powered off before
00209       entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
00210       It can be switched on again by software after exiting the Stop mode using
00211       the HAL_PWREx_DisableFlashPowerDown() function.
00212
00213       (+) Entry:
00214          The Stop mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, STOPEntry)
00215          function with:
00216          (++) Regulator:
00217           (+++) PWR_MAINREGULATOR_ON: Main regulator ON.
00218           (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
00219          (++) STOPEntry:
00220           (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction
00221           (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
00222       (+) Exit:
00223         Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
00224
00225    *** STANDBY mode ***
00226    ====================
00227     [..]
00228     (+)
00229       The system Standby mode allows to achieve the lowest power consumption. It is based
00230       on the Cortex-M7 deep sleep mode, with the voltage regulator disabled.
00231       The system is consequently powered off. The PLL, the HSI oscillator and
00232       the HSE oscillator are also switched off. SRAM and register contents are lost
00233       except for the RTC registers, RTC backup registers, backup SRAM and Standby
00234       circuitry.
00235     [..]
00236       The voltage regulator is OFF.
00237       (++) Entry:
00238         (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
00239       (++) Exit:
00240         (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
00241               wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.
00242
00243    *** Auto-wakeup (AWU) from low-power mode ***
00244    =============================================
00245     [..]
00246      (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
00247       Wakeup event, a tamper event or a time-stamp event, without depending on
00248       an external interrupt (Auto-wakeup mode).
00249      (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes
00250        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
00251             configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
00252        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
00253             is necessary to configure the RTC to detect the tamper or time stamp event using the
00254             HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
00255        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
00256             configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
00257
00258 @endverbatim
00259   * @{
00260   */
00261
00262 /**
00263   * @brief  Configure the voltage threshold detected by the Power Voltage Detector(PVD).
00264   * @param  sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
00265   *         information for the PVD.
00266   * @note   Refer to the electrical characteristics of your device datasheet for
00267   *         more details about the voltage threshold corresponding to each
00268   *         detection level.
00269   * @retval None
00270   */
00271 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
00272 {
00273   /* Check the parameters */
00274   assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
00275   assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
00276
00277   /* Set PLS[7:5] bits according to PVDLevel value */
00278   MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
00279
00280   /* Clear any previous config. Keep it clear if no event or IT mode is selected */
00281   __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
00282   __HAL_PWR_PVD_EXTI_DISABLE_IT();
00283   __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
00284   __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
00285
00286   /* Configure interrupt mode */
00287   if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
00288   {
00289     __HAL_PWR_PVD_EXTI_ENABLE_IT();
00290   }
00291
00292   /* Configure event mode */
00293   if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
00294   {
00295     __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
00296   }
00297
00298   /* Configure the edge */
00299   if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
00300   {
00301     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
00302   }
00303
00304   if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
00305   {
00306     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
00307   }
00308 }
00309
00310 /**
00311   * @brief  Enable the Power Voltage Detector(PVD).
00312   * @retval None
00313   */
00314 void HAL_PWR_EnablePVD(void)
00315 {
00316   /* Enable the power voltage detector */
00317   SET_BIT(PWR->CR1, PWR_CR1_PVDEN);
00318 }
00319
00320 /**
00321   * @brief  Disable the Power Voltage Detector(PVD).
00322   * @retval None
00323   */
00324 void HAL_PWR_DisablePVD(void)
00325 {
00326   /* Disable the power voltage detector */
00327   CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN);
00328 }
00329
00330 /**
00331   * @brief  Enable the WakeUp PINx functionality.
00332   * @param  WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
00333   *          This parameter can be one of the following legacy values, which sets the default:
00334   *          polarity detection on high level (rising edge):
00335   *            @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4,
00336   *                 PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6 or one of the following values where
00337   *                 the user can explicitly states the enabled pin and the chosen polarity.
00338   *            @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
00339   *            @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
00340   *            @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
00341   *            @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
00342   *            @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
00343   *            @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW
00344   * @note   PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
00345   * @retval None
00346   */
00347 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
00348 {
00349   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
00350
00351   /* Enable and Specify the Wake-Up pin polarity and the pull configuration
00352      for the event detection (rising or falling edge) */
00353   MODIFY_REG(PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity);
00354 }
00355
00356 /**
00357   * @brief  Disable the WakeUp PINx functionality.
00358   * @param  WakeUpPinx: Specifies the Power Wake-Up pin to disable.
00359   *          This parameter can be one of the following values:
00360   *            @arg PWR_WAKEUP_PIN1
00361   *            @arg PWR_WAKEUP_PIN2
00362   *            @arg PWR_WAKEUP_PIN3
00363   *            @arg PWR_WAKEUP_PIN4
00364   *            @arg PWR_WAKEUP_PIN5
00365   *            @arg PWR_WAKEUP_PIN6
00366   * @retval None
00367   */
00368 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
00369 {
00370   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
00371
00372   CLEAR_BIT(PWR->WKUPEPR, WakeUpPinx);
00373 }
00374
00375 /**
00376   * @brief  Enter CM7 core to Sleep mode.
00377   * @param  Regulator: Specifies the regulator state in SLEEP mode.
00378   *          This parameter can be one of the following values:
00379   *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
00380   *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
00381   * @note   This parameter is not used for the STM32H7 family and is kept as parameter
00382   *         just to maintain compatibility with the lower power families.
00383   * @param  SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.
00384   *          This parameter can be one of the following values:
00385   *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
00386   *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
00387   * @retval None
00388   */
00389 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
00390 {
00391   /* Check the parameters */
00392   assert_param(IS_PWR_REGULATOR(Regulator));
00393   assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
00394
00395   /* Clear SLEEPDEEP bit of Cortex System Control Register */
00396   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00397
00398   /* Select SLEEP mode entry */
00399   if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
00400   {
00401     /* Request Wait For Interrupt */
00402     __WFI();
00403   }
00404   else
00405   {
00406     /* Request Wait For Event */
00407     __SEV();
00408     __WFE();
00409     __WFE();
00410   }
00411 }
00412
00413 /**
00414   * @brief  Enter the system to STOP mode.
00415   * @note   In System Stop mode, all I/O pins keep the same state as in Run mode.
00416   * @note   When exiting System Stop mode by issuing an interrupt or a wakeup event,
00417   *         the HSI RC oscillator is selected as default system wakeup clock.
00418   * @note   In System STOP mode, when the voltage regulator operates in low power mode,
00419   *         an additional startup delay is incurred when the system is waking up.
00420   *         By keeping the internal regulator ON during Stop mode, the consumption
00421   *         is higher although the startup time is reduced.
00422   * @param  Regulator: Specifies the regulator state in Stop mode.
00423   *          This parameter can be one of the following values:
00424   *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
00425   *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
00426   * @param  STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
00427   *          This parameter can be one of the following values:
00428   *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
00429   *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
00430   * @retval None
00431   */
00432 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
00433 {
00434   uint32_t tmpreg = 0;
00435
00436   /* Check the parameters */
00437   assert_param(IS_PWR_REGULATOR(Regulator));
00438   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
00439
00440   /* Select the regulator state in Stop mode */
00441   tmpreg = PWR->CR1;
00442   /* Clear PDDS and LPDS bits */
00443   tmpreg &= (uint32_t)~(PWR_CR1_LPDS);
00444
00445   /* Set LPDS bit according to Regulator value */
00446   tmpreg |= Regulator;
00447
00448   /* Store the new value */
00449   PWR->CR1 = tmpreg;
00450
00451   /* Keep DSTOP mode when D1 domain enters Deepsleep */
00452   CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);
00453
00454   /* Keep DSTOP mode when D2 domain enters Deepsleep */
00455   CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2);
00456
00457   /* Keep DSTOP mode when D3 domain enters Deepsleep */
00458   CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3);
00459
00460   /* Set SLEEPDEEP bit of Cortex System Control Register */
00461   SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
00462
00463   /* Ensure that all instructions done before entering STOP mode */
00464   __DSB();
00465   __ISB();
00466
00467   /* Select Stop mode entry */
00468   if(STOPEntry == PWR_STOPENTRY_WFI)
00469   {
00470     /* Request Wait For Interrupt */
00471     __WFI();
00472   }
00473   else
00474   {
00475     /* Request Wait For Event */
00476     __SEV();
00477     __WFE();
00478     __WFE();
00479   }
00480   /* Reset SLEEPDEEP bit of Cortex System Control Register */
00481   SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
00482 }
00483
00484 /**
00485   * @brief  Enter the system to STANDBY mode.
00486   * @note   The system enters Standby mode only when the D1, D2 and D3 domains are in DStandby.
00487   * @note   When the System exit STANDBY mode by issuing an interrupt or a wakeup event,
00488   *         the HSI RC oscillator is selected as system clock.
00489   * @retval None.
00490   */
00491 void HAL_PWR_EnterSTANDBYMode(void)
00492 {
00493   /* Keep DSTANDBY mode when D1 domain enters Deepsleep */
00494   SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);
00495
00496   /* Keep DSTANDBY mode when D2 domain enters Deepsleep */
00497   SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2);
00498
00499   /* Keep DSTANDBY mode when D3 domain enters Deepsleep */
00500   SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3);
00501
00502   /* Set SLEEPDEEP bit of Cortex System Control Register */
00503   SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
00504
00505   /* This option is used to ensure that store operations are completed */
00506 #if defined ( __CC_ARM)
00507   __force_stores();
00508 #endif
00509   /* Request Wait For Interrupt */
00510   __WFI();
00511 }
00512
00513 /**
00514   * @brief  Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
00515   * @note   Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
00516   *         re-enters SLEEP mode when an interruption handling is over.
00517   *         Setting this bit is useful when the processor is expected to run only on
00518   *         interruptions handling.
00519   * @retval None
00520   */
00521 void HAL_PWR_EnableSleepOnExit(void)
00522 {
00523   /* Set SLEEPONEXIT bit of Cortex System Control Register */
00524   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00525 }
00526
00527
00528 /**
00529   * @brief  Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
00530   * @note   Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
00531   *         re-enters SLEEP mode when an interruption handling is over.
00532   * @retval None
00533   */
00534 void HAL_PWR_DisableSleepOnExit(void)
00535 {
00536   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
00537   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00538 }
00539
00540 /**
00541   * @brief  Enable CORTEX SEVONPEND bit.
00542   * @note   Sets SEVONPEND bit of SCR register. When this bit is set, this causes
00543   *         WFE to wake up when an interrupt moves from inactive to pended.
00544   * @retval None
00545   */
00546 void HAL_PWR_EnableSEVOnPend(void)
00547 {
00548   /* Set SEVONPEND bit of Cortex System Control Register */
00549   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00550 }
00551
00552 /**
00553   * @brief  Disable CORTEX SEVONPEND bit.
00554   * @note   Clears SEVONPEND bit of SCR register. When this bit is set, this causes
00555   *         WFE to wake up when an interrupt moves from inactive to pended.
00556   * @retval None
00557   */
00558 void HAL_PWR_DisableSEVOnPend(void)
00559 {
00560   /* Clear SEVONPEND bit of Cortex System Control Register */
00561   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00562 }
00563
00564 /**
00565   * @brief  This function handles the PWR PVD interrupt request.
00566   * @note   This API should be called under the PVD_IRQHandler().
00567   * @retval None
00568   */
00569 void HAL_PWR_PVD_IRQHandler(void)
00570 {
00571   /* PVD EXTI line interrupt detected */
00572   if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
00573   {
00574     /* PWR PVD interrupt user callback */
00575     HAL_PWR_PVDCallback();
00576
00577     /* Clear PWR EXTI pending bit */
00578     __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
00579   }
00580 }
00581
00582 /**
00583   * @brief  PWR PVD interrupt callback
00584   * @retval None
00585   */
00586 __weak void HAL_PWR_PVDCallback(void)
00587 {
00588   /* NOTE : This function Should not be modified, when the callback is needed,
00589             the HAL_PWR_PVDCallback could be implemented in the user file
00590   */
00591 }
00592
00593 /**
00594   * @}
00595   */
00596
00597 /**
00598   * @}
00599   */
00600
00601 #endif /* HAL_PWR_MODULE_ENABLED */
00602 /**
00603   * @}
00604   */
00605
00606 /**
00607   * @}
00608   */
00609
00610 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_pwr.h Source File

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stm32h7xx_hal_pwr.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_pwr.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of PWR HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_PWR_H
00040 #define __STM32H7xx_HAL_PWR_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup PWR
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup PWR_Exported_Types PWR Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  PWR PVD configuration structure definition
00065   */
00066 typedef struct
00067 {
00068   uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
00069                             This parameter can be a value of @ref PWR_PVD_detection_level */
00070
00071   uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
00072                            This parameter can be a value of @ref PWR_PVD_Mode */
00073 }PWR_PVDTypeDef;
00074
00075 /**
00076   * @}
00077   */
00078
00079 /* Exported constants --------------------------------------------------------*/
00080 /** @defgroup PWR_Exported_Constants PWR Exported Constants
00081   * @{
00082   */
00083
00084 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
00085   * @{
00086   */
00087 #define PWR_PVDLEVEL_0  PWR_CR1_PLS_LEV0
00088 #define PWR_PVDLEVEL_1  PWR_CR1_PLS_LEV1
00089 #define PWR_PVDLEVEL_2  PWR_CR1_PLS_LEV2
00090 #define PWR_PVDLEVEL_3  PWR_CR1_PLS_LEV3
00091 #define PWR_PVDLEVEL_4  PWR_CR1_PLS_LEV4
00092 #define PWR_PVDLEVEL_5  PWR_CR1_PLS_LEV5
00093 #define PWR_PVDLEVEL_6  PWR_CR1_PLS_LEV6
00094 #define PWR_PVDLEVEL_7  PWR_CR1_PLS_LEV7/* External input analog voltage (Compare internally to VREFINT) */
00095 /**
00096   * @}
00097   */
00098
00099 /** @defgroup PWR_PVD_Mode PWR PVD Mode
00100   * @{
00101   */
00102 #define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000U)   /*!< Basic mode is used */
00103 #define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection */
00104 #define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection */
00105 #define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
00106 #define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001U)   /*!< Event Mode with Rising edge trigger detection */
00107 #define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002U)   /*!< Event Mode with Falling edge trigger detection */
00108 #define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection */
00109 /**
00110   * @}
00111   */
00112
00113 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
00114   * @{
00115   */
00116 #define PWR_MAINREGULATOR_ON      ((uint32_t)0x00000000U)
00117 #define PWR_LOWPOWERREGULATOR_ON  PWR_CR1_LPDS
00118 /**
00119   * @}
00120   */
00121
00122 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
00123   * @{
00124   */
00125 #define PWR_SLEEPENTRY_WFI  ((uint8_t)0x01U)
00126 #define PWR_SLEEPENTRY_WFE  ((uint8_t)0x02U)
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
00132   * @{
00133   */
00134 #define PWR_STOPENTRY_WFI  ((uint8_t)0x01U)
00135 #define PWR_STOPENTRY_WFE  ((uint8_t)0x02U)
00136 /**
00137   * @}
00138   */
00139
00140 /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
00141   * @{
00142   */
00143 #define PWR_REGULATOR_VOLTAGE_SCALE1  (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
00144 #define PWR_REGULATOR_VOLTAGE_SCALE2  (PWR_D3CR_VOS_1)
00145 #define PWR_REGULATOR_VOLTAGE_SCALE3  (PWR_D3CR_VOS_0)
00146 /**
00147   * @}
00148   */
00149
00150 /** @defgroup PWR_Flag PWR Flag
00151   * @{
00152   */
00153 #define PWR_FLAG_STOP       ((uint8_t)0x01U)
00154 #define PWR_FLAG_SB_D1      ((uint8_t)0x02U)
00155 #define PWR_FLAG_SB_D2      ((uint8_t)0x03U)
00156 #define PWR_FLAG_SB         ((uint8_t)0x04U)
00157 #define PWR_FLAG_PVDO       ((uint8_t)0x07U)
00158 #define PWR_FLAG_AVDO       ((uint8_t)0x08U)
00159 #define PWR_FLAG_ACTVOSRDY  ((uint8_t)0x09U)
00160 #define PWR_FLAG_ACTVOS     ((uint8_t)0x0AU)
00161 #define PWR_FLAG_BRR        ((uint8_t)0x0BU)
00162 #define PWR_FLAG_VOSRDY     ((uint8_t)0x0CU)
00163 #define PWR_FLAG_SCUEN       ((uint8_t)0x0DU)
00164 /**
00165   * @}
00166   */
00167
00168 /** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
00169   * @{
00170   */
00171 #define  PWR_EWUP_MASK  ((uint32_t)0x0FFF3F3FU)
00172 /**
00173   * @}
00174   */
00175
00176 /**
00177   * @}
00178   */
00179 /* Exported macro ------------------------------------------------------------*/
00180 /** @defgroup PWR_Exported_Macro PWR Exported Macro
00181   * @{
00182   */
00183
00184 /** @brief  macros configure the main internal regulator output voltage.
00185   * @param  __REGULATOR__: specifies the regulator output voltage to achieve
00186   *         a tradeoff between performance and power consumption when the device does
00187   *         not operate at the maximum frequency (refer to the datasheets for more details).
00188   *          This parameter can be one of the following values:
00189   *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
00190   *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
00191   *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
00192   * @retval None
00193   */
00194 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)  \
00195 do { \
00196       __IO uint32_t tmpreg = 0x00; \
00197       MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \
00198       /* Delay after an RCC peripheral clock enabling */  \
00199       tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
00200       UNUSED(tmpreg); \
00201 } while(0)
00202
00203 /** @brief  Check PWR PVD/AVD and VOSflags are set or not.
00204   * @param  __FLAG__: specifies the flag to check.
00205   *           This parameter can be one of the following values:
00206   *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
00207   *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
00208   *                  For this reason, this bit is equal to 0 after Standby or reset
00209   *                  until the PVDE bit is set.
00210   *            @arg PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled
00211   *                  by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode
00212   *                  For this reason, this bit is equal to 0 after Standby or reset
00213   *                  until the AVDE bit is set.
00214   *            @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the Regulator voltage
00215   *                 scaling output selection is ready.
00216   *            @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
00217   *                 scaling output selection is ready.
00218   *            @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
00219   *                  when the device wakes up from Standby mode or by a system reset
00220   *                  or power reset.
00221   *            @arg PWR_FLAG_SB: StandBy flag
00222   *            @arg PWR_FLAG_STOP: STOP flag
00223   *            @arg PWR_FLAG_SB_D1: StandBy D1 flag
00224   *            @arg PWR_FLAG_SB_D2: StandBy D2 flag
00225   * @retval The new state of __FLAG__ (TRUE or FALSE).
00226   */
00227 #define __HAL_PWR_GET_FLAG(__FLAG__) ( \
00228 ((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \
00229 ((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \
00230 ((__FLAG__) == PWR_FLAG_ACTVOSRDY)?((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) : \
00231 ((__FLAG__) == PWR_FLAG_VOSRDY)?((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) : \
00232 ((__FLAG__) == PWR_FLAG_SCUEN)?((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) : \
00233 ((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \
00234 ((__FLAG__) == PWR_FLAG_SB)?((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) : \
00235 ((__FLAG__) == PWR_FLAG_STOP)?((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : \
00236 ((__FLAG__) == PWR_FLAG_SB_D1)?((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) : \
00237 ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2))
00238
00239
00240 /** @brief  Clear the PWR's flags.
00241   * @param  __FLAG__: specifies the flag to clear.
00242   *           This parameter can be one of the following values:
00243   *            @arg PWR_FLAG_SB: StandBy flag.
00244   *            @arg PWR_CPU_FLAGS: Clear STOPF, SBF, SBF_D1, and SBF_D2 CPU flags.
00245   * @retval None.
00246   */
00247 #define __HAL_PWR_CLEAR_FLAG(__FLAG__)  SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
00248
00249 /**
00250   * @brief Enable the PVD EXTI Line 16.
00251   * @retval None.
00252   */
00253 #define __HAL_PWR_PVD_EXTI_ENABLE_IT()  SET_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_PVD)
00254
00255
00256 /**
00257   * @brief Disable the PVD EXTI Line 16.
00258   * @retval None.
00259   */
00260 #define __HAL_PWR_PVD_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_PVD)
00261
00262
00263 /**
00264   * @brief   Enable event on PVD EXTI Line 16.
00265   * @retval None.
00266   */
00267 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()  SET_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_PVD)
00268
00269
00270 /**
00271   * @brief   Disable event on PVD EXTI Line 16.
00272   * @retval None.
00273   */
00274 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_PVD)
00275
00276
00277 /**
00278   * @brief Enable the PVD Extended Interrupt Rising Trigger.
00279   * @retval None.
00280   */
00281 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()  SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
00282
00283 /**
00284   * @brief Disable the PVD Extended Interrupt Rising Trigger.
00285   * @retval None.
00286   */
00287 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
00288
00289 /**
00290   * @brief Enable the PVD Extended Interrupt Falling Trigger.
00291   * @retval None.
00292   */
00293 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
00294
00295
00296 /**
00297   * @brief Disable the PVD Extended Interrupt Falling Trigger.
00298   * @retval None.
00299   */
00300 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
00301
00302
00303 /**
00304   * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
00305   * @retval None.
00306   */
00307 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
00308 do { \
00309       __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
00310       __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
00311 } while(0);
00312
00313 /**
00314   * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
00315   * @retval None.
00316   */
00317 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
00318 do { \
00319       __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
00320       __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
00321 } while(0);
00322
00323 /**
00324   * @brief  Check whether the specified PVD EXTI interrupt flag is set or not.
00325   * @retval EXTI PVD Line Status.
00326   */
00327 #define __HAL_PWR_PVD_EXTI_GET_FLAG()  READ_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_PVD)
00328
00329
00330 /**
00331   * @brief Clear the PVD EXTI flag.
00332   * @retval None.
00333   */
00334 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  SET_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_PVD)
00335
00336
00337 /**
00338   * @brief  Generates a Software interrupt on PVD EXTI line.
00339   * @retval None.
00340   */
00341 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT()    SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
00342 /**
00343   * @}
00344   */
00345
00346
00347 /* Include PWR HAL Extension module */
00348 #include "stm32h7xx_hal_pwr_ex.h"
00349
00350 /* Exported functions --------------------------------------------------------*/
00351 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
00352   * @{
00353   */
00354
00355 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions
00356   * @{
00357   */
00358 /* Initialization and de-initialization functions *****************************/
00359 void HAL_PWR_DeInit(void);
00360 void HAL_PWR_EnableBkUpAccess(void);
00361 void HAL_PWR_DisableBkUpAccess(void);
00362 /**
00363   * @}
00364   */
00365
00366 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
00367   * @{
00368   */
00369 /* Peripheral Control functions  **********************************************/
00370 /* PVD configuration */
00371 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
00372 void HAL_PWR_EnablePVD(void);
00373 void HAL_PWR_DisablePVD(void);
00374
00375 /* WakeUp pins configuration */
00376 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
00377 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
00378
00379 /* Low Power modes entry */
00380 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
00381 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
00382 void HAL_PWR_EnterSTANDBYMode(void);
00383
00384 /* Power PVD IRQ Handler */
00385 void HAL_PWR_PVD_IRQHandler(void);
00386 void HAL_PWR_PVDCallback(void);
00387
00388 /* Cortex System Control functions  *******************************************/
00389 void HAL_PWR_EnableSleepOnExit(void);
00390 void HAL_PWR_DisableSleepOnExit(void);
00391 void HAL_PWR_EnableSEVOnPend(void);
00392 void HAL_PWR_DisableSEVOnPend(void);
00393 /**
00394   * @}
00395   */
00396
00397 /**
00398   * @}
00399   */
00400
00401 /* Private types -------------------------------------------------------------*/
00402 /* Private variables ---------------------------------------------------------*/
00403 /* Private constants ---------------------------------------------------------*/
00404 /** @defgroup PWR_Private_Constants PWR Private Constants
00405   * @{
00406   */
00407
00408 /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
00409   * @{
00410   */
00411 /*!< External interrupt line 16 Connected to the PVD EXTI Line */
00412 #define PWR_EXTI_LINE_PVD      ((uint32_t)EXTI_IMR1_IM16)
00413 /**
00414   * @}
00415   */
00416
00417 /**
00418   * @}
00419   */
00420 /* Private macros ------------------------------------------------------------*/
00421 /** @defgroup PWR_Private_Macros PWR Private Macros
00422   * @{
00423   */
00424
00425 /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
00426   * @{
00427   */
00428 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
00429                                  ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
00430                                  ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
00431                                  ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
00432 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
00433                               ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
00434                               ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
00435                               ((MODE) == PWR_PVD_MODE_NORMAL))
00436 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
00437                                      ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
00438 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
00439 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
00440 #define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
00441                                            ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
00442                                            ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
00443
00444 /**
00445   * @}
00446   */
00447
00448 /**
00449   * @}
00450   */
00451
00452 /**
00453   * @}
00454   */
00455
00456 /**
00457   * @}
00458   */
00459
00460 #ifdef __cplusplus
00461 }
00462 #endif
00463
00464
00465 #endif /* __STM32H7xx_HAL_PWR_H */
00466
00467 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_pwr_ex.c Source File

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stm32h7xx_hal_pwr_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_pwr_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Extended PWR HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of PWR extension peripheral:
00010   *           + Peripheral Extended features functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00016   *
00017   * Redistribution and use in source and binary forms, with or without modification,
00018   * are permitted provided that the following conditions are met:
00019   *   1. Redistributions of source code must retain the above copyright notice,
00020   *      this list of conditions and the following disclaimer.
00021   *   2. Redistributions in binary form must reproduce the above copyright notice,
00022   *      this list of conditions and the following disclaimer in the documentation
00023   *      and/or other materials provided with the distribution.
00024   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00025   *      may be used to endorse or promote products derived from this software
00026   *      without specific prior written permission.
00027   *
00028   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00029   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00030   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00031   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00032   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00033   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00034   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00035   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00036   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00037   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00038   *
00039   ******************************************************************************
00040   */
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32h7xx_hal.h"
00044
00045 /** @addtogroup STM32H7xx_HAL_Driver
00046   * @{
00047   */
00048
00049 /** @defgroup PWREx PWREx
00050   * @brief PWR Extended HAL module driver
00051   * @{
00052   */
00053
00054 #ifdef HAL_PWR_MODULE_ENABLED
00055
00056 /* Private typedef -----------------------------------------------------------*/
00057 /* Private define ------------------------------------------------------------*/
00058 /** @addtogroup PWREx_Private_Constants
00059   * @{
00060   */
00061
00062 /** @defgroup PWREx_AVD_Mode_Mask PWR Extended AVD Mode Mask
00063   * @{
00064   */
00065 #define AVD_MODE_IT              ((uint32_t)0x00010000U)
00066 #define AVD_MODE_EVT             ((uint32_t)0x00020000U)
00067 #define AVD_RISING_EDGE          ((uint32_t)0x00000001U)
00068 #define AVD_FALLING_EDGE         ((uint32_t)0x00000002U)
00069 #define AVD_RISING_FALLING_EDGE  ((uint32_t)0x00000003U)
00070 /**
00071   * @}
00072   */
00073
00074 /** @defgroup PWREx_REG_SET_TIMEOUT PWR Extended Flag Setting Time Out Value
00075   * @{
00076   */
00077 #define PWR_FLAG_SETTING_DELAY_US  ((uint32_t)1000U)
00078 /**
00079   * @}
00080   */
00081
00082
00083 /**
00084   * @}
00085   */
00086
00087 /* Private macro -------------------------------------------------------------*/
00088 /* Private variables ---------------------------------------------------------*/
00089 /* Private function prototypes -----------------------------------------------*/
00090 /* Private functions ---------------------------------------------------------*/
00091 /* Exported types ------------------------------------------------------------*/
00092
00093 /* Exported functions --------------------------------------------------------*/
00094 /** @defgroup PWREx_Exported_Functions PWREx Exported Functions
00095   * @{
00096   */
00097
00098 /** @defgroup PWREx_Exported_Functions_Group1 Power supply control functions
00099   * @brief    Power supply control functions
00100   *
00101 @verbatim
00102
00103  ===============================================================================
00104                  ##### Power supply control functions #####
00105  ===============================================================================
00106
00107     *** Power supply configuration ***
00108     ==================================
00109     [..]
00110       When the system is powered on, the POR monitors VDD supply. Once VDD is above the
00111       POR threshold level, the voltage regulator is enabled in the default supply
00112       configuration:
00113       (+) The Voltage converter output level is set at 1.0 V in accordance with the VOS3
00114           level configured in PWR D3 domain control register (PWR_D3CR).
00115       (+) The system is kept in reset mode as long as VCORE is not ok.
00116       (+) Once VCORE is ok, the system is taken out of reset and the HSI oscillator is enabled.
00117       (+) Once the oscillator is stable, the system is initialized: Flash memory and option
00118           bytes are loaded and the CPU starts in Run* mode.
00119       (+) The software shall then initialize the system including supply configuration
00120           programming using the HAL_PWREx_ConfigSupply(SupplySource) with:
00121        (++) SupplySource:
00122         (+++) PWR_LDO_SUPPLY: VCORE Power Domains are supplied from the LDO according to
00123                               VOS. LDO power mode (Main, LP, Off) will follow system low-power
00124                               modes.
00125         (+++) PWR_EXTERNAL_SOURCE_SUPPLY: VCORE supplied from external source and LDO bypassed,
00126                                           voltage monitoring still active.
00127       (+) Once the supply configuration  has been configured, the HAL_PWREx_ConfigSupply
00128           function checks the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1)
00129           to guarantee a valid voltage levels:
00130        (++) As long as ACTVOSRDY indicates that voltage levels are invalid, the system is in
00131             limited Run* mode, write accesses to the RAMs are not permitted and VOS shall
00132             not be changed.
00133        (++) Once ACTVOSRDY indicates that voltage levels are valid, the system is in normal
00134             Run mode, write accesses to RAMs are allowed and VOS can be changed.
00135
00136 @endverbatim
00137   * @{
00138   */
00139
00140 /**
00141   * @brief  Configure the system Power Supply.
00142   * @param  SupplySource: Specifies the Power Supply source.
00143   *          This parameter can be one of the following values:
00144   *            @arg PWR_LDO_SUPPLY: The LDO supplies the Vcore Power Domains.
00145   *            @arg PWR_EXTERNAL_SOURCE_SUPPLY: The Vcore Power Domains are supplied from external power source.
00146   *                                               The LDO is Bypassed.
00147   * @retval HAL status.
00148   */
00149 HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource)
00150 {
00151   uint32_t tickstart = 0;
00152
00153   /* Check the parameters */
00154   assert_param(IS_PWR_SUPPLY(SupplySource));
00155
00156   /* Set the power supply configuration */
00157   MODIFY_REG(PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);
00158
00159   /* Get tick */
00160   tickstart = HAL_GetTick();
00161
00162   /* Wait till voltage level flag is set and supply configuration update flag is reset */
00163   while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ACTVOSRDY) && __HAL_PWR_GET_FLAG(PWR_FLAG_SCUEN))
00164   {
00165     if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)
00166     {
00167       return HAL_TIMEOUT;
00168     }
00169   }
00170
00171   return HAL_OK;
00172 }
00173
00174
00175 /**
00176   * @brief  Get the power supply configuration.
00177   * @retval The supply configuration.
00178   */
00179 uint32_t  HAL_PWREx_GetSupplyConfig(void)
00180 {
00181   return (PWR->CR3 & PWR_SUPPLY_CONFIG_MASK);
00182 }
00183
00184
00185 /**
00186   * @brief  Configure the main internal regulator output voltage.
00187   * @param  VoltageScaling: Specifies the regulator output voltage to achieve
00188   *         a tradeoff between performance and power consumption.
00189   *          This parameter can be one of the following values:
00190   *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode.
00191   *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode.
00192   *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode.
00193   * @note   When moving from Range 1 to Range 2, the system frequency must be decreased
00194   *         before calling HAL_PWREx_ControlVoltageScaling() API.
00195   *         When moving from Range 2 to Range 1, the system frequency can be increased
00196   *         after calling HAL_PWREx_ControlVoltageScaling() API.
00197   * @note   When moving from a Range to an other one, the API waits for VOSRDY flag to be
00198   *         set before returning the status. If the flag is not set within 1000 microseconds,
00199   *         HAL_TIMEOUT status is reported.
00200   * @retval HAL Status
00201   */
00202 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
00203 {
00204   uint32_t tickstart = 0;
00205
00206   assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));
00207
00208   /* Set the voltage range */
00209   MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
00210
00211   /* Get tick */
00212   tickstart = HAL_GetTick();
00213
00214   /* Wait until the VOSRDY flag is set */
00215   while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY))
00216   {
00217     if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)
00218     {
00219       return HAL_TIMEOUT;
00220     }
00221   }
00222
00223   return HAL_OK;
00224 }
00225
00226 /**
00227   * @brief  Get the main internal regulator output voltage.
00228   *         Reflecting the last VOS value applied to the PMU.
00229   * @retval The actual applied VOS for VDD11 Voltage Scaling selection.
00230   */
00231 uint32_t  HAL_PWREx_GetVoltageRange(void)
00232 {
00233   return (PWR->CSR1 & PWR_CSR1_ACTVOS);
00234 }
00235
00236 /**
00237   * @brief  Configure the main internal regulator output voltage in STOP mode.
00238   * @param  VoltageScaling: Specifies the regulator output voltage when the system enters
00239   *         STOP mode to achieve a tradeoff between performance and power consumption.
00240   *          This parameter can be one of the following values:
00241   *            @arg PWR_REGULATOR_SVOS_SCALE3: Regulator voltage output range 3 mode.
00242   *            @arg PWR_REGULATOR_SVOS_SCALE4: Regulator voltage output range 4 mode.
00243   *            @arg PWR_REGULATOR_SVOS_SCALE5: Regulator voltage output range 5 mode.
00244   * @note   The Stop mode voltage scaling for SVOS4 and SVOS5 sets the voltage regulator
00245   *         in Low-power (LP) mode to further reduce power consumption.
00246   *         When preselecting SVOS3, the use of the voltage regulator low-power mode (LP)
00247   *         can be selected by LPDS register bit.
00248   * @note   The selected SVOS4 and SVOS5 levels add an additional startup delay when exiting
00249   *         from system Stop mode.
00250   * @retval HAL Status
00251   */
00252 HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling)
00253 {
00254   assert_param(IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VoltageScaling));
00255
00256   /* Set the stop mode voltage range */
00257   MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
00258
00259   return HAL_OK;
00260 }
00261
00262 /**
00263   * @brief  Get the main internal regulator output voltage in STOP mode.
00264   * @retval The actual applied VOS for VDD11 Voltage Scaling selection.
00265   */
00266 uint32_t  HAL_PWREx_GetStopModeVoltageRange(void)
00267 {
00268   return (PWR->CR1 & PWR_CR1_SVOS);
00269 }
00270
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup PWREx_Exported_Functions_Group2 Low power control functions
00276   * @brief    Low power control functions
00277   *
00278 @verbatim
00279
00280  ===============================================================================
00281                  ##### Low power control functions #####
00282  ===============================================================================
00283
00284     *** Domains Low Power modes configuration ***
00285     =============================================
00286     [..]
00287       The system present 3 principles domains (D1, D2 and D3) that can be operated
00288       in low-power modes (DSTOP or DSTANDBY mode):
00289
00290       (+) DSTOP mode to enters a domain to STOP mode:
00291        (++) D1 domain and/or D2 domain enters DSTOP mode only when the CPU
00292             subsystem is in CSTOP mode and has allocated peripheral in the domain.
00293             In DSTOP mode the domain bus matrix clock is stopped.
00294        (++) The system enters STOP mode using one of the following scenarios:
00295         (+++) D1 domain enters DSTANDBY mode (powered off) and D2, D3 domains enter DSTOP mode.
00296         (+++) D2 domain enters DSTANDBY mode (powered off) and D1, D3 domains enter DSTOP mode.
00297         (+++) D3 domain enters DSTANDBY mode (powered off) and D1, D2 domains enter DSTOP mode.
00298         (+++) D1 and D2 domains enter DSTANDBY mode (powered off) and D3 domain enters DSTOP mode.
00299         (+++) D1 and D3 domains enter DSTANDBY mode (powered off) and D2 domain enters DSTOP mode.
00300         (+++) D2 and D3 domains enter DSTANDBY mode (powered off) and D1 domain enters DSTOP mode.
00301         (+++) D1, D2 and D3 domains enter DSTOP mode.
00302        (++) When the system enters STOP mode, the clocks are stopped and the regulator is running
00303             in main or low power mode.
00304        (++) D3 domain can be kept in Run mode regardless of the CPU status when enter
00305             STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function.
00306
00307       (+) DSTANDBY mode to enters a domain to STANDBY mode:
00308        (++) The DSTANDBY mode is entered when the PDDS_Dn bit in PWR CPU control register
00309             (PWR_CPUCR) for the Dn domain selects Standby mode.
00310        (++) The system enters STANDBY mode only when D1, D2 and D3 domains enter DSTANDBY mode.
00311             Consequently the VCORE supply regulator is powered off.
00312
00313    *** DSTOP mode ***
00314    ==================
00315     [..]
00316       In DStop mode the domain bus matrix clock is stopped.
00317       The Flash memory can enter low-power Stop mode when it is enabled through FLPS in
00318       PWR_CR1 register. This allows a trade-off between domain DStop restart time and low
00319       power consumption.
00320     [..]
00321       In DStop mode domain peripherals using the LSI or LSE clock and peripherals having a
00322       kernel clock request are still able to operate.
00323     [..]
00324       Before entering DSTOP mode it is recommended to call SCB_CleanDCache function
00325       in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.
00326
00327       (+) Entry:
00328          The DSTOP mode is entered using the HAL_PWREx_EnterSTOPMode(Regulator, STOPEntry, Domain)
00329          function with:
00330          (++) Regulator:
00331           (+++) PWR_MAINREGULATOR_ON: Main regulator ON.
00332           (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
00333          (++) STOPEntry:
00334           (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction
00335           (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
00336          (++) Domain:
00337           (+++) PWR_D1_DOMAIN: Enters D1 domain to DSTOP mode.
00338           (+++) PWR_D2_DOMAIN: Enters D2 domain to DSTOP mode.
00339           (+++) PWR_D3_DOMAIN: Enters D3 domain to DSTOP mode.
00340
00341       (+) Exit:
00342         Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
00343
00344    *** DSTANDBY mode ***
00345    ====================
00346     [..]
00347       In DStandby mode:
00348         (+) The domain bus matrix clock is stopped.
00349         (+) The domain is powered down and the domain RAM and register contents are lost.
00350     [..]
00351       Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache function
00352       in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.
00353
00354       (+) Entry:
00355          The DSTANDBY mode is entered using the HAL_PWREx_EnterSTANDBYMode(Domain) function with:
00356        (++) Domain:
00357         (+++) PWR_D1_DOMAIN: Enters D1 domain to DSTANDBY mode.
00358         (+++) PWR_D2_DOMAIN: Enters D2 domain to DSTANDBY mode.
00359         (+++) PWR_D3_DOMAIN: Enters D3 domain to DSTANDBY mode.
00360
00361       (+) Exit:
00362         WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
00363         wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.
00364
00365    *** Keep D3 in RUN mode ***
00366    ===========================
00367     [..]
00368       D3 domain can be kept in Run mode regardless of the CPU status when enter
00369       STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function with:
00370        (+) D3State:
00371         (++) PWR_D3_DOMAIN_STOP: D3 domain will follow the CPU sub-system mode.
00372         (++) PWR_D3_DOMAIN_RUN: D3 domain remains in Run mode regardless of CPU subsystem mode.
00373
00374     *** FLASH Power Down configuration ****
00375     =======================================
00376     [..]
00377       By setting the FLPS bit in the PWR_CR1 register using the HAL_PWREx_EnableFlashPowerDown()
00378       function, the Flash memory also enters power down mode when the device enters Stop mode.
00379       When the Flash memory is in power down mode, an additional startup delay is incurred when
00380       waking up from Stop mode.
00381
00382     *** Wakeup Pins configuration ****
00383     ===================================
00384     [..]
00385       Wakeup pins allow the system to exit from Standby mode. The configuration of
00386       wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams) function with:
00387        (+) sPinParams: structure to enable and configure a wakeup pin:
00388         (++) WakeUpPin: Wakeup pin to be enabled.
00389         (++) PinPolarity: Wakeup pin polarity (rising or falling edge).
00390         (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down).
00391     [..]
00392       The wakeup pins are internally connected to the EXTI lines [55-60] to generate an interrupt
00393       if enabled. The EXTI lines configuration is done in the HAL_PWREx_EnableWakeUpPin() function.
00394     [..]
00395       When a wakeup pin event is received the HAL_PWREx_WAKEUP_PIN_IRQHandler is called
00396       and the appropriate flag is set in the PWR_WKUPFR register. Then in the HAL_PWREx_WAKEUP_PIN_IRQHandler
00397       function the wakeup pin flag will be cleared and the appropriate user callback will be called.
00398       The user can add his own code by customization of function pointer HAL_PWREx_WKUPx_Callback.
00399
00400 @endverbatim
00401   * @{
00402   */
00403
00404 /**
00405   * @brief  Enter a Domain to DSTOP mode.
00406   * @note   In DStop mode the domain bus matrix clock is stopped.
00407   * @note   The system D3 domain enters Stop mode only when the CPU subsystem is in CStop mode,
00408   *         the EXTI wakeup sources are inactive and at least one PDDS_Dn bit in PWR CPU
00409   *         control register (PWR_CPUCR) for any domain request Stop.
00410   * @note   In system D3 domain Stop mode, D1 domain and D2 domain are either in DStop and/or
00411   *         DStandby mode.
00412   * @note   Before entering DSTOP mode it is recommended to call SCB_CleanDCache function
00413   *         in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.
00414   * @note   In System Stop mode, the domain peripherals that use the LSI or LSE clock, and the
00415   *         peripherals that have a kernel clock request to select HSI or CSI as source,
00416   *         are still able to operate.
00417   * @param  Regulator: Specifies the regulator state in Stop mode.
00418   *          This parameter can be one of the following values:
00419   *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
00420   *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
00421   * @param  STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
00422   *          This parameter can be one of the following values:
00423   *            @arg PWR_STOPENTRY_WFI: Enter DStop mode with WFI instruction
00424   *            @arg PWR_STOPENTRY_WFE: Enter DStop mode with WFE instruction
00425   * @param  Domain: Specifies the Domain to enter STOP mode.
00426   *          This parameter can be one of the following values:
00427   *            @arg PWR_D1_DOMAIN: Enter D1 Domain to DSTOP mode.
00428   *            @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTOP mode.
00429   *            @arg PWR_D3_DOMAIN: Enter D3 Domain to DSTOP mode.
00430   * @retval None
00431   */
00432 void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain)
00433 {
00434   /* Check the parameters */
00435   assert_param(IS_PWR_REGULATOR(Regulator));
00436   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
00437   assert_param(IS_PWR_DOMAIN(Domain));
00438
00439   /* Select the regulator state in Stop mode */
00440   MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, Regulator);
00441
00442   /* Select the domain Power Down DeepSleep */
00443   if (Domain == PWR_D1_DOMAIN)
00444   {
00445     /* Keep DSTOP mode when D1 domain enters Deepsleep */
00446     CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);
00447
00448
00449     /* Set SLEEPDEEP bit of Cortex System Control Register */
00450     SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
00451
00452     /* Ensure that all instructions done before entering STOP mode */
00453     __DSB();
00454     __ISB();
00455
00456     /* Select Stop mode entry */
00457     if(STOPEntry == PWR_STOPENTRY_WFI)
00458     {
00459       /* Request Wait For Interrupt */
00460       __WFI();
00461     }
00462     else
00463     {
00464       /* Request Wait For Event */
00465       __SEV();
00466       __WFE();
00467       __WFE();
00468     }
00469
00470     /* Reset SLEEPDEEP bit of Cortex System Control Register */
00471     SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
00472   }
00473   else if (Domain == PWR_D2_DOMAIN)
00474   {
00475     /* Keep DSTOP mode when D2 domain enters Deepsleep */
00476     CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2);
00477
00478   }
00479   else
00480   {
00481     /* Keep DSTOP mode when D3 domain enters Deepsleep */
00482     CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3);
00483
00484   }
00485 }
00486
00487 /**
00488   * @brief  Enter a Domain to DSTANDBY mode.
00489   * @note   The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for the Dn domain
00490   *         select Standby mode. When the system enters Standby mode, the voltage regulator
00491   *         is disabled.
00492   * @note   When D2 or D3 domain is in DStandby mode and the CPU sets the domain PDDS_Dn
00493   *         bit to select Stop mode, the domain remains in DStandby mode. The domain will only
00494   *         exit DStandby when the CPU allocates a peripheral in the domain.
00495   * @note   The system D3 domain enters Standby mode only when the D1 and D2 domain are in
00496   *         DStandby.
00497   * @note   Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache function
00498   *         in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.
00499   * @param  Domain: Specifies the Domain to enter to STANDBY mode.
00500   *          This parameter can be one of the following values:
00501   *            @arg PWR_D1_DOMAIN: Enter D1 Domain to DSTANDBY mode.
00502   *            @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode.
00503   *            @arg PWR_D3_DOMAIN: Enter D3 Domain to DSTANDBY mode.
00504   * @retval None
00505   */
00506 void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain)
00507 {
00508   /* Check the parameters */
00509   assert_param(IS_PWR_DOMAIN(Domain));
00510
00511   /* Select the domain Power Down DeepSleep */
00512   if (Domain == PWR_D1_DOMAIN)
00513   {
00514     /* Allow DSTANDBY mode when D1 domain enters to Deepsleep */
00515     SET_BIT(PWR-> CPUCR, PWR_CPUCR_PDDS_D1);
00516
00517
00518     /* Set SLEEPDEEP bit of Cortex System Control Register */
00519     SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
00520
00521     /* This option is used to ensure that store operations are completed */
00522 #if defined ( __CC_ARM)
00523     __force_stores();
00524 #endif
00525
00526     /* Request Wait For Interrupt */
00527     __WFI();
00528   }
00529   else if (Domain == PWR_D2_DOMAIN)
00530   {
00531     /* Allow DSTANDBY mode when D2 domain enters to Deepsleep */
00532     SET_BIT(PWR-> CPUCR, PWR_CPUCR_PDDS_D2);
00533
00534   }
00535   else
00536   {
00537     /* Allow DSTANDBY mode when D3 domain enters to Deepsleep */
00538     SET_BIT(PWR-> CPUCR, PWR_CPUCR_PDDS_D3);
00539
00540   }
00541 }
00542
00543 /**
00544   * @brief  Configure the D3 Domain state when the CPU is in low power mode.
00545   * @param  D3State: Specifies the D3 state.
00546   *          This parameter can be one of the following values:
00547   *            @arg PWR_D3_DOMAIN_STOP: D3 domain will follow the CPU sub-system mode.
00548   *            @arg PWR_D3_DOMAIN_RUN : D3 domain will stay in RUN mode regardless of the
00549   *                                     CPU sub-system mode.
00550   * @retval None
00551   */
00552 void HAL_PWREx_ConfigD3Domain(uint32_t D3State)
00553 {
00554   /* Check the parameters */
00555   assert_param(IS_D3_STATE(D3State));
00556
00557   /* Keep D3 in run mode */
00558   MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RUN_D3, D3State);
00559 }
00560
00561
00562
00563
00564
00565 /**
00566   * @brief  Enable the Flash Power Down in Stop mode.
00567   * @retval None
00568   */
00569 void HAL_PWREx_EnableFlashPowerDown(void)
00570 {
00571   /* Enable the Flash Power Down */
00572   SET_BIT(PWR->CR1, PWR_CR1_FLPS);
00573 }
00574
00575 /**
00576   * @brief  Disable the Flash Power Down in Stop mode.
00577   * @retval None
00578   */
00579 void HAL_PWREx_DisableFlashPowerDown(void)
00580 {
00581   /* Disable the Flash Power Down */
00582   CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS);
00583 }
00584
00585 /**
00586   * @brief  Enable the Wake-up PINx functionality.
00587   * @param  sPinParams: pointer to an PWREx_WakeupPinTypeDef structure that contains
00588   *                     the configuration informations for the wake-up Pin.
00589   * @retval None
00590   */
00591 void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams)
00592 {
00593   uint32_t pinConfig;
00594
00595   /* Check the parameters */
00596   assert_param(IS_PWR_WAKEUP_PIN(sPinParams->WakeUpPin));
00597   assert_param(IS_PWR_WAKEUP_PIN_POLARITY(sPinParams->PinPolarity));
00598   assert_param(IS_PWR_WAKEUP_PIN_PULL(sPinParams->PinPull));
00599
00600   pinConfig = (sPinParams->WakeUpPin | \
00601               (sPinParams->PinPolarity << (POSITION_VAL(sPinParams->WakeUpPin) + 8)) | \
00602               (sPinParams->PinPull << (POSITION_VAL(sPinParams->WakeUpPin) + 16)));
00603
00604   /* Enable and Specify the Wake-Up pin polarity and the pull configuration
00605      for the event detection (rising or falling edge) */
00606   MODIFY_REG(PWR->WKUPEPR, PWR_EWUP_MASK, pinConfig);
00607
00608   /* Configure the Wakeup Pin EXTI Line */
00609   MODIFY_REG(EXTI_D1->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << 23));
00610 }
00611
00612 /**
00613   * @brief Disable the Wake-up PINx functionality.
00614   * @param WakeUpPin: Specifies the Wake-Up pin to be disabled.
00615   *          This parameter can be one of the following values:
00616   *           @arg PWR_WAKEUP_PIN1: Disable PA0  wake-up PIN.
00617   *           @arg PWR_WAKEUP_PIN2: Disable PA2  wake-up PIN..
00618   *           @arg PWR_WAKEUP_PIN3: Disable PI8  wake-up PIN..
00619   *           @arg PWR_WAKEUP_PIN4: Disable PC13 wake-up PIN..
00620   *           @arg PWR_WAKEUP_PIN5: Disable PI11 wake-up PIN..
00621   *           @arg PWR_WAKEUP_PIN6: Disable PC1  wake-up PIN..
00622   * @retval None
00623   */
00624 void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin)
00625 {
00626   /* Check the parameters */
00627   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPin));
00628
00629   /* Disable the WakeUpPin */
00630   CLEAR_BIT(PWR->WKUPEPR, WakeUpPin);
00631 }
00632
00633 /**
00634   * @brief  Get the Wake-Up Pin flag.
00635   * @param  WakeUpFlag: Specifies the Wake-Up PIN flag to check.
00636   *          This parameter can be one of the following values:
00637   *            @arg PWR_WAKEUP_FLAG1: A wakeup event was received from PA0.
00638   *            @arg PWR_WAKEUP_FLAG2: A wakeup event was received from PA2.
00639   *            @arg PWR_WAKEUP_FLAG3: A wakeup event was received from PC1.
00640   *            @arg PWR_WAKEUP_FLAG4: A wakeup event was received from PC13.
00641   *            @arg PWR_WAKEUP_FLAG5: A wakeup event was received from PI8.
00642   *            @arg PWR_WAKEUP_FLAG6: A wakeup event was received from PI11.
00643   * @retval The Wake-Up pin flag.
00644   */
00645 uint32_t  HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag)
00646 {
00647   /* Check the parameters */
00648   assert_param(IS_PWR_WAKEUP_FLAG(WakeUpFlag));
00649
00650   return (PWR->WKUPFR & WakeUpFlag);
00651 }
00652
00653 /**
00654   * @brief  Clear the Wake-Up pin flag.
00655   * @param  WakeUpFlag: Specifies the Wake-Up PIN flag to clear.
00656   *          This parameter can be one of the following values:
00657   *            @arg PWR_WAKEUP_FLAG1: Clear the wakeup event received from PA0.
00658   *            @arg PWR_WAKEUP_FLAG2: Clear the wakeup event received from PA2.
00659   *            @arg PWR_WAKEUP_FLAG3: Clear the wakeup event received from PC1.
00660   *            @arg PWR_WAKEUP_FLAG4: Clear the wakeup event received from PC13.
00661   *            @arg PWR_WAKEUP_FLAG5: Clear the wakeup event received from PI8.
00662   *            @arg PWR_WAKEUP_FLAG6: Clear the wakeup event received from PI11.
00663   * @retval HAL status.
00664   */
00665 HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag)
00666 {
00667   /* Check the parameters */
00668   assert_param(IS_PWR_WAKEUP_FLAG(WakeUpFlag));
00669
00670   SET_BIT(PWR->WKUPCR, WakeUpFlag);
00671
00672   if((PWR->WKUPFR & WakeUpFlag) != RESET)
00673   {
00674     return HAL_ERROR;
00675   }
00676
00677   return HAL_OK;
00678 }
00679
00680 /**
00681   * @brief  This function handles the PWR WAKEUP PIN interrupt request.
00682   * @note   This API should be called under the WAKEUP_PIN_IRQHandler().
00683   * @retval None
00684   */
00685 void HAL_PWREx_WAKEUP_PIN_IRQHandler(void)
00686 {
00687   /* Wakeup pin EXTI line interrupt detected */
00688   if(READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) != RESET)
00689   {
00690     /* Clear PWR WKUPF1 flag */
00691     SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC1);
00692
00693     /* PWR WKUP1 interrupt user callback */
00694     HAL_PWREx_WKUP1_Callback();
00695   }
00696   else if(READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) != RESET)
00697   {
00698     /* Clear PWR WKUPF2 flag */
00699     SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC2);
00700
00701     /* PWR WKUP2 interrupt user callback */
00702     HAL_PWREx_WKUP2_Callback();
00703   }
00704   else if(READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) != RESET)
00705   {
00706     /* Clear PWR WKUPF3 flag */
00707     SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);
00708
00709     /* PWR WKUP3 interrupt user callback */
00710     HAL_PWREx_WKUP3_Callback();
00711   }
00712   else if(READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) != RESET)
00713   {
00714     /* Clear PWR WKUPF4 flag */
00715     SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);
00716
00717     /* PWR WKUP4 interrupt user callback */
00718     HAL_PWREx_WKUP4_Callback();
00719   }
00720   else if(READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) != RESET)
00721   {
00722     /* Clear PWR WKUPF5 flag */
00723     SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC5);
00724
00725     /* PWR WKUP5 interrupt user callback */
00726     HAL_PWREx_WKUP5_Callback();
00727   }
00728   else
00729   {
00730     /* Clear PWR WKUPF6 flag */
00731     SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC6);
00732
00733     /* PWR WKUP6 interrupt user callback */
00734     HAL_PWREx_WKUP6_Callback();
00735   }
00736 }
00737
00738 /**
00739   * @brief  PWR WKUP1 interrupt callback
00740   * @retval None
00741   */
00742 __weak void HAL_PWREx_WKUP1_Callback(void)
00743 {
00744   /* NOTE : This function Should not be modified, when the callback is needed,
00745             the HAL_PWREx_WKUP1Callback could be implemented in the user file
00746   */
00747 }
00748
00749 /**
00750   * @brief  PWR WKUP2 interrupt callback
00751   * @retval None
00752   */
00753 __weak void HAL_PWREx_WKUP2_Callback(void)
00754 {
00755   /* NOTE : This function Should not be modified, when the callback is needed,
00756             the HAL_PWREx_WKUP2Callback could be implemented in the user file
00757   */
00758 }
00759
00760 /**
00761   * @brief  PWR WKUP3 interrupt callback
00762   * @retval None
00763   */
00764 __weak void HAL_PWREx_WKUP3_Callback(void)
00765 {
00766   /* NOTE : This function Should not be modified, when the callback is needed,
00767             the HAL_PWREx_WKUP3Callback could be implemented in the user file
00768   */
00769 }
00770
00771 /**
00772   * @brief  PWR WKUP4 interrupt callback
00773   * @retval None
00774   */
00775 __weak void HAL_PWREx_WKUP4_Callback(void)
00776 {
00777   /* NOTE : This function Should not be modified, when the callback is needed,
00778             the HAL_PWREx_WKUP4Callback could be implemented in the user file
00779   */
00780 }
00781
00782 /**
00783   * @brief  PWR WKUP5 interrupt callback
00784   * @retval None
00785   */
00786 __weak void HAL_PWREx_WKUP5_Callback(void)
00787 {
00788   /* NOTE : This function Should not be modified, when the callback is needed,
00789             the HAL_PWREx_WKUP5Callback could be implemented in the user file
00790   */
00791 }
00792
00793 /**
00794   * @brief  PWR WKUP6 interrupt callback
00795   * @retval None
00796   */
00797 __weak void HAL_PWREx_WKUP6_Callback(void)
00798 {
00799   /* NOTE : This function Should not be modified, when the callback is needed,
00800             the HAL_PWREx_WKUP6Callback could be implemented in the user file
00801   */
00802 }
00803
00804 /**
00805   * @}
00806   */
00807
00808 /** @defgroup PWREx_Exported_Functions_Group3 Peripherals control functions
00809   * @brief    Peripherals control functions
00810   *
00811 @verbatim
00812
00813  ===============================================================================
00814                  ##### Peripherals control functions #####
00815  ===============================================================================
00816
00817     *** Main and Backup Regulators configuration ***
00818     ================================================
00819     [..]
00820       (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
00821           the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
00822           retained even in Standby or VBAT mode when the low power backup regulator
00823           is enabled. It can be considered as an internal EEPROM when VBAT is
00824           always present. You can use the HAL_PWREx_EnableBkUpReg() function to
00825           enable the low power backup regulator.
00826       (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
00827           the backup SRAM is powered from VDD which replaces the VBAT power supply to
00828           save battery life.
00829       (+) The backup SRAM is not mass erased by a tamper event. It is read
00830           protected to prevent confidential data, such as cryptographic private
00831           key, from being accessed. The backup SRAM can be erased only through
00832           the Flash interface when a protection level change from level 1 to
00833           level 0 is requested.
00834       -@- Refer to the description of Read protection (RDP) in the Flash
00835           programming manual.
00836       (+) The main internal regulator can be configured to have a tradeoff between
00837           performance and power consumption when the device does not operate at
00838           the maximum frequency. This is done through HAL_PWREx_ControlVoltageScaling(VOS)
00839           function which configure the VOS bit in PWR_D3CR register.
00840       (+) The main internal regulator can be configured to operate in Low Power mode
00841           when the system enter STOP mode to further reduce power consumption.
00842           This is done through HAL_PWREx_ControlStopModeVoltageScaling(SVOS)
00843           function which configure the SVOS bit in PWR_CR1 register.
00844           The selected SVOS4 and SVOS5 levels add an additional startup delay when exiting from
00845           system Stop mode.
00846     -@- Refer to the product datasheets for more details.
00847
00848     *** USB Regulator configuration ***
00849     ===================================
00850     [..]
00851       (+) The USB transceivers are supplied from a dedicated VDD33USB supply that can be
00852           provided either by the integrated USB regulator, or by an external USB supply.
00853       (+) The USB regulator is enabled by HAL_PWREx_EnableUSBReg() function, the VDD33USB
00854           is then provided from the USB regulator.
00855       (+) When the USB regulator is enabled, the VDD33USB supply level detector shall
00856           be enabled through  HAL_PWREx_EnableUSBVoltageDetector() function.
00857       (+) The USB regulator is disabled through HAL_PWREx_DisableUSBReg() function and VDD33USB
00858           can be provided from an external supply. In this case VDD33USB and VDD50USB shall
00859           be connected together
00860
00861     *** VBAT battery charging ***
00862     =============================
00863     [..]
00864       (+) When VDD is present, the external battery connected to VBAT can be charged through an
00865           internal resistance. VBAT charging can be performed either through a 5 KOhm resistor
00866           or through a 1.5 KOhm resistor.
00867       (+) VBAT charging is enabled by HAL_PWREx_EnableBatteryCharging(ResistorValue) function
00868           with:
00869        (++) ResistorValue:
00870         (+++) PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor.
00871         (+++) PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor.
00872       (+) VBAT charging is disabled by HAL_PWREx_DisableBatteryCharging() function.
00873
00874 @endverbatim
00875   * @{
00876   */
00877
00878 /**
00879   * @brief  Enable the Backup Regulator.
00880   * @retval HAL status
00881   */
00882 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
00883 {
00884   uint32_t tickstart = 0;
00885
00886   /* Enable the Backup regulator */
00887   SET_BIT(PWR->CR2, PWR_CR2_BREN);
00888
00889   /* Get tick */
00890   tickstart = HAL_GetTick();
00891
00892   /* Wait till Backup regulator ready flag is set */
00893   while(!__HAL_PWR_GET_FLAG(PWR_FLAG_BRR))
00894   {
00895     if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)
00896     {
00897       return HAL_TIMEOUT;
00898     }
00899   }
00900   return HAL_OK;
00901 }
00902
00903 /**
00904   * @brief  Disable the Backup Regulator.
00905   * @retval HAL status
00906   */
00907 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
00908 {
00909   uint32_t tickstart = 0;
00910
00911   /* Disable the Backup regulator */
00912   CLEAR_BIT(PWR->CR2, PWR_CR2_BREN);
00913
00914   /* Get tick */
00915   tickstart = HAL_GetTick();
00916
00917   /* Wait till Backup regulator ready flag is reset */
00918   while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
00919   {
00920     if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)
00921     {
00922       return HAL_TIMEOUT;
00923     }
00924   }
00925   return HAL_OK;
00926 }
00927
00928 /**
00929   * @brief  Enable the USB Regulator.
00930   * @retval HAL status
00931   */
00932 HAL_StatusTypeDef HAL_PWREx_EnableUSBReg(void)
00933 {
00934   uint32_t tickstart = 0;
00935
00936   /* Enable the USB regulator */
00937   SET_BIT(PWR->CR3, PWR_CR3_USBREGEN);
00938
00939   /* Get tick */
00940   tickstart = HAL_GetTick();
00941
00942   /* Wait till the USB regulator ready flag is set */
00943   while(READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == RESET)
00944   {
00945     if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)
00946     {
00947       return HAL_TIMEOUT;
00948     }
00949   }
00950
00951   return HAL_OK;
00952 }
00953
00954 /**
00955   * @brief  Disable the USB Regulator.
00956   * @retval HAL status
00957   */
00958 HAL_StatusTypeDef HAL_PWREx_DisableUSBReg(void)
00959 {
00960   uint32_t tickstart = 0;
00961
00962   /* Disable the USB regulator */
00963   CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN);
00964
00965   /* Get tick */
00966   tickstart = HAL_GetTick();
00967
00968   /* Wait till the USB regulator ready flag is reset */
00969   while(READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) != RESET)
00970   {
00971     if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)
00972     {
00973       return HAL_TIMEOUT;
00974     }
00975   }
00976   return HAL_OK;
00977 }
00978
00979 /**
00980   * @brief  Enable the USB voltage level detector.
00981   * @retval None
00982   */
00983 void HAL_PWREx_EnableUSBVoltageDetector(void)
00984 {
00985   /* Enable the USB voltage detector */
00986   SET_BIT(PWR->CR3, PWR_CR3_USB33DEN);
00987 }
00988
00989 /**
00990   * @brief  Disable the USB voltage level detector.
00991   * @retval None
00992   */
00993 void HAL_PWREx_DisableUSBVoltageDetector(void)
00994 {
00995   /* Disable the USB voltage detector */
00996   CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN);
00997 }
00998
00999
01000 /**
01001   * @brief  Enable the Battery charging.
01002   *         When VDD is present, charge the external battery through an internal resistor.
01003   * @param  ResistorValue: Specifies the charging resistor.
01004   *          This parameter can be one of the following values:
01005   *            @arg PWR_BATTERY_CHARGING_RESISTOR_5:   5 KOhm resistor.
01006   *            @arg PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor.
01007   * @retval None
01008   */
01009 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue)
01010 {
01011   assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorValue));
01012
01013   /* Specify the charging resistor */
01014   MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, ResistorValue);
01015
01016   /* Enable the Battery charging */
01017   SET_BIT(PWR->CR3, PWR_CR3_VBE);
01018 }
01019
01020
01021 /**
01022   * @brief  Disable the Battery charging.
01023   * @retval None
01024   */
01025 void HAL_PWREx_DisableBatteryCharging(void)
01026 {
01027   /* Disable the Battery charging */
01028   CLEAR_BIT(PWR->CR3, PWR_CR3_VBE);
01029 }
01030
01031 /**
01032   * @}
01033   */
01034
01035 /** @defgroup PWREx_Exported_Functions_Group4 Power Monitoring functions
01036   * @brief    Power Monitoring functions
01037   *
01038 @verbatim
01039
01040  ===============================================================================
01041                  ##### Power Monitoring functions #####
01042  ===============================================================================
01043
01044     *** VBAT and Temperature supervision ***
01045     ========================================
01046     [..]
01047       (+) The VBAT battery voltage supply can be monitored by comparing it with two threshold
01048           levels: VBAThigh and VBATlow. VBATH flag and VBATL flags in the PWR control register 2
01049           (PWR_CR2), indicate if VBAT is higher or lower than the threshold.
01050       (+) The temperature can be monitored by comparing it with two threshold levels, TEMPhigh
01051           and TEMPlow. TEMPH and TEMPL flags, in the PWR control register 2 (PWR_CR2),
01052           indicate whether the device temperature is higher or lower than the threshold.
01053       (+) The VBAT and the temperature monitoring is enabled by HAL_PWREx_EnableMonitoring()
01054           function and disabled by HAL_PWREx_DisableMonitoring() function.
01055       (+) The HAL_PWREx_GetVBATLevel() function return the VBAT level which can be:
01056           PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or
01057           PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD.
01058       (+) The HAL_PWREx_GetTemperatureLevel() function return the Temperature level which
01059           can be: PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or
01060           PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD.
01061
01062     *** AVD configuration ***
01063     =========================
01064     [..]
01065       (+) The AVD is used to monitor the VDDA power supply by comparing it to a
01066           threshold selected by the AVD Level (ALS[3:0] bits in the PWR_CR1 register).
01067       (+) A AVDO flag is available to indicate if VDDA is higher or lower
01068           than the AVD threshold. This event is internally connected to the EXTI
01069           line 16 to generate an interrupt if enabled.
01070           It is configurable through __HAL_PWR_AVD_EXTI_ENABLE_IT() macro.
01071       (+) The AVD is stopped in System Standby mode.
01072
01073 @endverbatim
01074   * @{
01075   */
01076
01077 /**
01078   * @brief  Enable the VBAT and temperature monitoring.
01079   * @retval HAL status
01080   */
01081 void HAL_PWREx_EnableMonitoring(void)
01082 {
01083   /* Enable the VBAT and Temperature monitoring */
01084   SET_BIT(PWR->CR2, PWR_CR2_MONEN);
01085 }
01086
01087 /**
01088   * @brief  Disable the VBAT and temperature monitoring.
01089   * @retval HAL status
01090   */
01091 void HAL_PWREx_DisableMonitoring(void)
01092 {
01093   /* Disable the VBAT and Temperature monitoring */
01094   CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN);
01095 }
01096
01097 /**
01098   * @brief  Indicate whether the junction temperature is between, above or below the threshold.
01099   * @retval Temperature level.
01100   */
01101 uint32_t HAL_PWREx_GetTemperatureLevel(void)
01102 {
01103   uint32_t tempLevel;
01104   uint32_t regValue;
01105
01106   /* Read the temperature flags */
01107   regValue = PWR->CR2 & (PWR_CR2_TEMPH | PWR_CR2_TEMPL);
01108
01109   /* Compare the read value to the temperature threshold */
01110   if(regValue == PWR_CR2_TEMPL)
01111   {
01112     tempLevel = PWR_TEMP_BELOW_LOW_THRESHOLD;
01113   }
01114   else if(regValue == PWR_CR2_TEMPH)
01115   {
01116     tempLevel = PWR_TEMP_ABOVE_HIGH_THRESHOLD;
01117   }
01118   else
01119   {
01120     tempLevel = PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD;
01121   }
01122
01123   return tempLevel;
01124 }
01125
01126 /**
01127   * @brief  Indicate whether the Battery voltage level is between, above or below the threshold.
01128   * @retval VBAT level.
01129   */
01130 uint32_t HAL_PWREx_GetVBATLevel(void)
01131 {
01132   uint32_t VBATLevel;
01133   uint32_t regValue;
01134
01135   /* Read the VBAT flags */
01136   regValue = PWR->CR2 & (PWR_CR2_VBATH | PWR_CR2_VBATL);
01137
01138   /* Compare the read value to the VBAT threshold */
01139   if(regValue == PWR_CR2_VBATL)
01140   {
01141     VBATLevel = PWR_VBAT_BELOW_LOW_THRESHOLD;
01142   }
01143   else if(regValue == PWR_CR2_VBATH)
01144   {
01145     VBATLevel = PWR_VBAT_ABOVE_HIGH_THRESHOLD;
01146   }
01147   else
01148   {
01149     VBATLevel = PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD;
01150   }
01151
01152   return VBATLevel;
01153 }
01154
01155 /**
01156   * @brief  Configure the analog voltage threshold detected by the Analog Voltage Detector(AVD).
01157   * @param  sConfigAVD: pointer to an PWR_AVDTypeDef structure that contains the configuration
01158   *                     information for the AVD.
01159   * @note   Refer to the electrical characteristics of your device datasheet for more details
01160   *         about the voltage threshold corresponding to each detection level.
01161   * @retval None
01162   */
01163 void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD)
01164 {
01165   /* Check the parameters */
01166   assert_param(IS_PWR_AVD_LEVEL(sConfigAVD->AVDLevel));
01167   assert_param(IS_PWR_AVD_MODE(sConfigAVD->Mode));
01168
01169   /* Set the ALS[18:17] bits according to AVDLevel value */
01170   MODIFY_REG(PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel);
01171
01172   /* Clear any previous config. Keep it clear if no event or IT mode is selected */
01173   __HAL_PWR_AVD_EXTI_DISABLE_EVENT();
01174   __HAL_PWR_AVD_EXTI_DISABLE_IT();
01175   __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE();
01176   __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE();
01177
01178   /* Configure the interrupt mode */
01179   if(AVD_MODE_IT == (sConfigAVD->Mode & AVD_MODE_IT))
01180   {
01181     __HAL_PWR_AVD_EXTI_ENABLE_IT();
01182   }
01183
01184   /* Configure the event mode */
01185   if(AVD_MODE_EVT == (sConfigAVD->Mode & AVD_MODE_EVT))
01186   {
01187     __HAL_PWR_AVD_EXTI_ENABLE_EVENT();
01188   }
01189
01190   /* Configure the edge */
01191   if(AVD_RISING_EDGE == (sConfigAVD->Mode & AVD_RISING_EDGE))
01192   {
01193     __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE();
01194   }
01195
01196   if(AVD_FALLING_EDGE == (sConfigAVD->Mode & AVD_FALLING_EDGE))
01197   {
01198     __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE();
01199   }
01200 }
01201
01202 /**
01203   * @brief  Enable the Analog Voltage Detector(AVD).
01204   * @retval None
01205   */
01206 void HAL_PWREx_EnableAVD(void)
01207 {
01208   /* Enable the Analog Voltage Detector */
01209   SET_BIT(PWR->CR1, PWR_CR1_AVDEN);
01210 }
01211
01212 /**
01213   * @brief  Disable the Analog Voltage Detector(AVD).
01214   * @retval None
01215   */
01216 void HAL_PWREx_DisableAVD(void)
01217 {
01218   /* Disable the Analog Voltage Detector */
01219   CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN);
01220 }
01221
01222 /**
01223   * @brief  This function handles the PWR PVD/AVD interrupt request.
01224   * @note   This API should be called under the PVD_AVD_IRQHandler().
01225   * @retval None
01226   */
01227 void HAL_PWREx_PVD_AVD_IRQHandler(void)
01228 {
01229   /* PVD EXTI line interrupt detected */
01230   if(READ_BIT(PWR->CR1, PWR_CR1_PVDEN) != RESET)
01231   {
01232     /* Check PWR EXTI flag */
01233     if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
01234     {
01235       /* PWR PVD interrupt user callback */
01236       HAL_PWR_PVDCallback();
01237
01238       /* Clear PWR EXTI pending bit */
01239       __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
01240     }
01241   }
01242
01243   /* AVD EXTI line interrupt detected */
01244   if(READ_BIT(PWR->CR1, PWR_CR1_AVDEN) != RESET)
01245   {
01246     /* Check PWR EXTI flag */
01247     if(__HAL_PWR_AVD_EXTI_GET_FLAG() != RESET)
01248     {
01249       /* PWR AVD interrupt user callback */
01250       HAL_PWREx_AVDCallback();
01251
01252       /* Clear PWR EXTI pending bit */
01253       __HAL_PWR_AVD_EXTI_CLEAR_FLAG();
01254     }
01255   }
01256 }
01257
01258 /**
01259   * @brief  PWR AVD interrupt callback
01260   * @retval None
01261   */
01262 __weak void HAL_PWREx_AVDCallback(void)
01263 {
01264   /* NOTE : This function Should not be modified, when the callback is needed,
01265             the HAL_PWR_AVDCallback could be implemented in the user file
01266    */
01267 }
01268
01269 /**
01270   * @}
01271   */
01272
01273 /**
01274   * @}
01275   */
01276
01277 #endif /* HAL_PWR_MODULE_ENABLED */
01278
01279 /**
01280   * @}
01281   */
01282
01283 /**
01284   * @}
01285   */
01286
01287 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_pwr_ex.h Source File

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stm32h7xx_hal_pwr_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_pwr_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of PWR HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_PWR_EX_H
00040 #define __STM32H7xx_HAL_PWR_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup PWREx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup PWREx_Exported_Types PWREx Exported Types
00059   * @{
00060   */
00061 /**
00062   * @brief  PWREx AVD configuration structure definition
00063   */
00064 typedef struct
00065 {
00066   uint32_t AVDLevel;       /*!< AVDLevel: Specifies the AVD detection level.
00067                                  This parameter can be a value of @ref PWREx_AVD_detection_level */
00068
00069   uint32_t Mode;            /*!< Mode: Specifies the operating mode for the selected pins.
00070                                   This parameter can be a value of @ref PWREx_AVD_Mode */
00071 }PWREx_AVDTypeDef;
00072
00073 /**
00074   * @brief  PWREx Wakeup pin configuration structure definition
00075   */
00076 typedef struct
00077 {
00078   uint32_t WakeUpPin;     /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled.
00079                                 This parameter can be a value of @ref PWREx_WakeUp_Pins */
00080
00081   uint32_t PinPolarity;   /*!< PinPolarity: Specifies the Wake-Up pin polarity.
00082                                 This parameter can be a value of @ref PWREx_PIN_Polarity */
00083
00084   uint32_t PinPull;       /*!< PinPull: Specifies the Wake-Up pin pull.
00085                                 This parameter can be a value of @ref PWREx_PIN_Pull */
00086 }PWREx_WakeupPinTypeDef;
00087
00088 /**
00089   * @}
00090   */
00091 /* Exported constants --------------------------------------------------------*/
00092
00093 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants
00094   * @{
00095   */
00096 /** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins
00097   * @{
00098   */
00099 #define PWR_WAKEUP_PIN6  PWR_WKUPEPR_WKUPEN_6
00100 #define PWR_WAKEUP_PIN5  PWR_WKUPEPR_WKUPEN_5
00101 #define PWR_WAKEUP_PIN4  PWR_WKUPEPR_WKUPEN_4
00102 #define PWR_WAKEUP_PIN3  PWR_WKUPEPR_WKUPEN_3
00103 #define PWR_WAKEUP_PIN2  PWR_WKUPEPR_WKUPEN_2
00104 #define PWR_WAKEUP_PIN1  PWR_WKUPEPR_WKUPEN_1
00105 /* High level and No pull */
00106 #define PWR_WAKEUP_PIN6_HIGH  PWR_WKUPEPR_WKUPEN_6
00107 #define PWR_WAKEUP_PIN5_HIGH  PWR_WKUPEPR_WKUPEN_5
00108 #define PWR_WAKEUP_PIN4_HIGH  PWR_WKUPEPR_WKUPEN_4
00109 #define PWR_WAKEUP_PIN3_HIGH  PWR_WKUPEPR_WKUPEN_3
00110 #define PWR_WAKEUP_PIN2_HIGH  PWR_WKUPEPR_WKUPEN_2
00111 #define PWR_WAKEUP_PIN1_HIGH  PWR_WKUPEPR_WKUPEN_1
00112 /* Low level and No pull */
00113 #define PWR_WAKEUP_PIN6_LOW  (uint32_t)(PWR_WKUPEPR_WKUPP_6 | PWR_WKUPEPR_WKUPEN_6)
00114 #define PWR_WAKEUP_PIN5_LOW  (uint32_t)(PWR_WKUPEPR_WKUPP_5 | PWR_WKUPEPR_WKUPEN_5)
00115 #define PWR_WAKEUP_PIN4_LOW  (uint32_t)(PWR_WKUPEPR_WKUPP_4 | PWR_WKUPEPR_WKUPEN_4)
00116 #define PWR_WAKEUP_PIN3_LOW  (uint32_t)(PWR_WKUPEPR_WKUPP_3 | PWR_WKUPEPR_WKUPEN_3)
00117 #define PWR_WAKEUP_PIN2_LOW  (uint32_t)(PWR_WKUPEPR_WKUPP_2 | PWR_WKUPEPR_WKUPEN_2)
00118 #define PWR_WAKEUP_PIN1_LOW  (uint32_t)(PWR_WKUPEPR_WKUPP_1 | PWR_WKUPEPR_WKUPEN_1)
00119
00120 /* WakeUp Pins mask */
00121 #define PWR_EXTI_WAKEUP_PINS_MASK  (uint32_t)(EXTI_IMR2_IM55 | EXTI_IMR2_IM56 | \
00122                                               EXTI_IMR2_IM57 | EXTI_IMR2_IM58 | \
00123                                               EXTI_IMR2_IM59 | EXTI_IMR2_IM60)
00124 /**
00125   * @}
00126   */
00127
00128 /** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration
00129   * @{
00130   */
00131 #define PWR_PIN_POLARITY_HIGH  ((uint32_t)0x00000000U)
00132 #define PWR_PIN_POLARITY_LOW   ((uint32_t)0x00000001U)
00133 /**
00134   * @}
00135   */
00136
00137 /** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration
00138   * @{
00139   */
00140 #define PWR_PIN_NO_PULL    ((uint32_t)0x00000000U)
00141 #define PWR_PIN_PULL_UP    ((uint32_t)0x00000001U)
00142 #define PWR_PIN_PULL_DOWN  ((uint32_t)0x00000002U)
00143 /**
00144   * @}
00145   */
00146
00147
00148 /** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags.
00149   * @{
00150   */
00151 #define PWR_WAKEUP_FLAG1  PWR_WKUPFR_WKUPF1 /*!< Wakeup event on pin 1 */
00152 #define PWR_WAKEUP_FLAG2  PWR_WKUPFR_WKUPF2 /*!< Wakeup event on pin 2 */
00153 #define PWR_WAKEUP_FLAG3  PWR_WKUPFR_WKUPF3 /*!< Wakeup event on pin 3 */
00154 #define PWR_WAKEUP_FLAG4  PWR_WKUPFR_WKUPF4 /*!< Wakeup event on pin 4 */
00155 #define PWR_WAKEUP_FLAG5  PWR_WKUPFR_WKUPF5 /*!< Wakeup event on pin 5 */
00156 #define PWR_WAKEUP_FLAG6  PWR_WKUPFR_WKUPF6 /*!< Wakeup event on pin 6 */
00157 /**
00158   * @}
00159   */
00160
00161
00162 /** @defgroup PWREx_Domains PWREx Domains definition
00163   * @{
00164   */
00165 #define PWR_D1_DOMAIN  ((uint32_t)0x00000000U)
00166 #define PWR_D2_DOMAIN  ((uint32_t)0x00000001U)
00167 #define PWR_D3_DOMAIN  ((uint32_t)0x00000002U)
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition
00173   * @{
00174   */
00175 #define PWR_CPU_FLAGS        ((uint32_t)0x00000000U)
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup PWREx_D3_State PWREx D3 Domain State
00181   * @{
00182   */
00183 #define PWR_D3_DOMAIN_STOP  ((uint32_t)0x00000000U)
00184 #define PWR_D3_DOMAIN_RUN   ((uint32_t)0x00000800U)
00185
00186 /**
00187   * @}
00188   */
00189
00190 /** @defgroup PWREx_Supply_configuration PWREx Supply configuration
00191   * @{
00192   */
00193 #define PWR_LDO_SUPPLY                       PWR_CR3_LDOEN /* Core domains are suppplied from the LDO */
00194
00195 #define PWR_EXTERNAL_SOURCE_SUPPLY           PWR_CR3_BYPASS /* The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source */
00196
00197 #define PWR_SUPPLY_CONFIG_MASK               (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
00198 /**
00199   * @}
00200   */
00201
00202
00203 /** @defgroup PWREx_AVD_detection_level PWREx AVD detection level
00204   * @{
00205   */
00206 #define PWR_AVDLEVEL_0  PWR_CR1_ALS_LEV0
00207 #define PWR_AVDLEVEL_1  PWR_CR1_ALS_LEV1
00208 #define PWR_AVDLEVEL_2  PWR_CR1_ALS_LEV2
00209 #define PWR_AVDLEVEL_3  PWR_CR1_ALS_LEV3
00210 /**
00211   * @}
00212   */
00213
00214 /** @defgroup PWREx_AVD_Mode PWREx AVD Mode
00215   * @{
00216   */
00217 #define PWR_AVD_MODE_NORMAL                ((uint32_t)0x00000000U)   /*!< Basic mode is used */
00218 #define PWR_AVD_MODE_IT_RISING             ((uint32_t)0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection */
00219 #define PWR_AVD_MODE_IT_FALLING            ((uint32_t)0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection */
00220 #define PWR_AVD_MODE_IT_RISING_FALLING     ((uint32_t)0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
00221 #define PWR_AVD_MODE_EVENT_RISING          ((uint32_t)0x00020001U)   /*!< Event Mode with Rising edge trigger detection */
00222 #define PWR_AVD_MODE_EVENT_FALLING         ((uint32_t)0x00020002U)   /*!< Event Mode with Falling edge trigger detection */
00223 #define PWR_AVD_MODE_EVENT_RISING_FALLING  ((uint32_t)0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection */
00224 /**
00225   * @}
00226   */
00227
00228 /** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
00229   * @{
00230   */
00231 #define PWR_REGULATOR_SVOS_SCALE5  (PWR_CR1_SVOS_0)
00232 #define PWR_REGULATOR_SVOS_SCALE4  (PWR_CR1_SVOS_1)
00233 #define PWR_REGULATOR_SVOS_SCALE3  (uint32_t)(PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection
00239   * @{
00240   */
00241 #define PWR_BATTERY_CHARGING_RESISTOR_5    ((uint32_t)0x00000000U) /*!< VBAT charging through a 5 kOhms resistor   */
00242 #define PWR_BATTERY_CHARGING_RESISTOR_1_5  PWR_CR3_VBRS           /*!< VBAT charging through a 1.5 kOhms resistor */
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds
00248   * @{
00249   */
00250 #define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD  ((uint32_t)0x00000000U)
00251 #define PWR_VBAT_BELOW_LOW_THRESHOLD         PWR_CR2_VBATL
00252 #define PWR_VBAT_ABOVE_HIGH_THRESHOLD        PWR_CR2_VBATH
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds
00258   * @{
00259   */
00260 #define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD  ((uint32_t)0x00000000U)
00261 #define PWR_TEMP_BELOW_LOW_THRESHOLD         PWR_CR2_TEMPL
00262 #define PWR_TEMP_ABOVE_HIGH_THRESHOLD        PWR_CR2_TEMPH
00263 /**
00264   * @}
00265   */
00266 /** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16
00267   * @{
00268   */
00269 #define PWR_EXTI_LINE_AVD  ((uint32_t)EXTI_IMR1_IM16) /*!< External interrupt line 16 Connected to the AVD EXTI Line */
00270 /**
00271   * @}
00272   */
00273 /**
00274   * @}
00275   */
00276 /* Exported macro ------------------------------------------------------------*/
00277 /** @defgroup PWREx_Exported_Macro PWREx Exported Macro
00278   *  @{
00279   */
00280
00281 /**
00282   * @brief Enable the AVD EXTI Line 16.
00283   * @retval None.
00284   */
00285 #define __HAL_PWR_AVD_EXTI_ENABLE_IT()  SET_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_AVD)
00286
00287
00288 /**
00289   * @brief Disable the AVD EXTI Line 16
00290   * @retval None.
00291   */
00292 #define __HAL_PWR_AVD_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_AVD)
00293
00294
00295 /**
00296   * @brief   Enable event on AVD EXTI Line 16.
00297   * @retval None.
00298   */
00299 #define __HAL_PWR_AVD_EXTI_ENABLE_EVENT()  SET_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_AVD)
00300
00301
00302 /**
00303   * @brief   Disable event on AVD EXTI Line 16.
00304   * @retval None.
00305   */
00306 #define __HAL_PWR_AVD_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_AVD)
00307
00308
00309 /**
00310   * @brief  Enable the AVD Extended Interrupt Rising Trigger.
00311   * @retval None.
00312   */
00313 #define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE()  SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
00314
00315 /**
00316   * @brief  Disable the AVD Extended Interrupt Rising Trigger.
00317   * @retval None.
00318   */
00319 #define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
00320
00321 /**
00322   * @brief  Enable the AVD Extended Interrupt Falling Trigger.
00323   * @retval None.
00324   */
00325 #define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
00326
00327
00328 /**
00329   * @brief  Disable the AVD Extended Interrupt Falling Trigger.
00330   * @retval None.
00331   */
00332 #define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
00333
00334
00335 /**
00336   * @brief  AVD EXTI line configuration: set rising & falling edge trigger.
00337   * @retval None.
00338   */
00339 #define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
00340   __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \
00341   __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \
00342 } while(0);
00343
00344 /**
00345   * @brief  Disable the AVD Extended Interrupt Rising & Falling Trigger.
00346   * @retval None.
00347   */
00348 #define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE()  \
00349 do { \
00350   __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \
00351   __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \
00352 } while(0);
00353
00354 /**
00355   * @brief  Check whether the specified AVD EXTI interrupt flag is set or not.
00356   * @retval EXTI AVD Line Status.
00357   */
00358 #define __HAL_PWR_AVD_EXTI_GET_FLAG()  READ_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_AVD)
00359
00360
00361 /**
00362   * @brief  Clear the AVD EXTI flag.
00363   * @retval None.
00364   */
00365 #define __HAL_PWR_AVD_EXTI_CLEAR_FLAG()  SET_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_AVD)
00366
00367
00368 /**
00369   * @}
00370   */
00371
00372 /* Exported functions --------------------------------------------------------*/
00373 /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
00374   * @{
00375   */
00376
00377 /** @addtogroup PWREx_Exported_Functions_Group1 Power supply control functions
00378   * @{
00379   */
00380 /* Power supply control functions */
00381 HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource);
00382 uint32_t HAL_PWREx_GetSupplyConfig(void);
00383 /* Power volatge scaling functions */
00384 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
00385 uint32_t HAL_PWREx_GetVoltageRange(void);
00386 HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling);
00387 uint32_t HAL_PWREx_GetStopModeVoltageRange(void);
00388 /**
00389   * @}
00390   */
00391
00392 /** @addtogroup PWREx_Exported_Functions_Group2 Low power control functions
00393   * @{
00394   */
00395 /* System low power control functions */
00396 void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain);
00397 void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain);
00398 void HAL_PWREx_ConfigD3Domain(uint32_t D3State);
00399
00400
00401 /* Flash low power control functions */
00402 void HAL_PWREx_EnableFlashPowerDown(void);
00403 void HAL_PWREx_DisableFlashPowerDown(void);
00404 /* Wakeup Pins control functions */
00405 void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams);
00406 void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin);
00407 uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag);
00408 HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag);
00409 /* Power Wakeup PIN IRQ Handler */
00410 void HAL_PWREx_WAKEUP_PIN_IRQHandler(void);
00411 void HAL_PWREx_WKUP1_Callback(void);
00412 void HAL_PWREx_WKUP2_Callback(void);
00413 void HAL_PWREx_WKUP3_Callback(void);
00414 void HAL_PWREx_WKUP4_Callback(void);
00415 void HAL_PWREx_WKUP5_Callback(void);
00416 void HAL_PWREx_WKUP6_Callback(void);
00417 /**
00418   * @}
00419   */
00420
00421 /** @addtogroup PWREx_Exported_Functions_Group3 Peripherals control functions
00422   * @{
00423   */
00424 /* Backup regulator control functions */
00425 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
00426 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
00427 /* USB regulator control functions */
00428 HAL_StatusTypeDef HAL_PWREx_EnableUSBReg(void);
00429 HAL_StatusTypeDef HAL_PWREx_DisableUSBReg(void);
00430 void HAL_PWREx_EnableUSBVoltageDetector(void);
00431 void HAL_PWREx_DisableUSBVoltageDetector(void);
00432 /* Battery control functions */
00433 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue);
00434 void HAL_PWREx_DisableBatteryCharging(void);
00435 /**
00436   * @}
00437   */
00438
00439 /** @addtogroup PWREx_Exported_Functions_Group4 Power Monitoring functions
00440   * @{
00441   */
00442 /* Power VBAT/Temperature monitoring functions */
00443 void HAL_PWREx_EnableMonitoring(void);
00444 void HAL_PWREx_DisableMonitoring(void);
00445 uint32_t HAL_PWREx_GetTemperatureLevel(void);
00446 uint32_t HAL_PWREx_GetVBATLevel(void);
00447
00448 /* Power AVD configuration functions */
00449 void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD);
00450 void HAL_PWREx_EnableAVD(void);
00451 void HAL_PWREx_DisableAVD(void);
00452
00453 /* Power PVD/AVD IRQ Handler */
00454 void HAL_PWREx_PVD_AVD_IRQHandler(void);
00455 void HAL_PWREx_AVDCallback(void);
00456
00457 /**
00458   * @}
00459   */
00460
00461 /**
00462   * @}
00463   */
00464 /* Private types -------------------------------------------------------------*/
00465 /* Private variables ---------------------------------------------------------*/
00466 /* Private constants ---------------------------------------------------------*/
00467 /* Private macros ------------------------------------------------------------*/
00468 /** @defgroup PWREx_Private_Macros PWREx Private Macros
00469   * @{
00470   */
00471
00472 /** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
00473   * @{
00474   */
00475 #define IS_PWR_SUPPLY(PWR_SOURCE)  (((PWR_SOURCE) == PWR_LDO_SUPPLY) || \
00476                                     ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
00477
00478 #define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE)  (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3)  || \
00479                                                       ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4)  || \
00480                                                       ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5))
00481
00482 #define IS_PWR_DOMAIN(DOMAIN)  (((DOMAIN) == PWR_D1_DOMAIN) || \
00483                                 ((DOMAIN) == PWR_D2_DOMAIN) || \
00484                                 ((DOMAIN) == PWR_D3_DOMAIN))
00485
00486 #define IS_D3_STATE(STATE)  (((STATE) == PWR_D3_DOMAIN_STOP) || ((STATE) == PWR_D3_DOMAIN_RUN))
00487
00488 #define IS_PWR_WAKEUP_PIN(PIN)  (((PIN) == PWR_WAKEUP_PIN1)       || \
00489                                  ((PIN) == PWR_WAKEUP_PIN2)       || \
00490                                  ((PIN) == PWR_WAKEUP_PIN3)       || \
00491                                  ((PIN) == PWR_WAKEUP_PIN4)       || \
00492                                  ((PIN) == PWR_WAKEUP_PIN5)       || \
00493                                  ((PIN) == PWR_WAKEUP_PIN6)       || \
00494                                  ((PIN) == PWR_WAKEUP_PIN1_HIGH)  || \
00495                                  ((PIN) == PWR_WAKEUP_PIN2_HIGH)  || \
00496                                  ((PIN) == PWR_WAKEUP_PIN3_HIGH)  || \
00497                                  ((PIN) == PWR_WAKEUP_PIN4_HIGH)  || \
00498                                  ((PIN) == PWR_WAKEUP_PIN5_HIGH)  || \
00499                                  ((PIN) == PWR_WAKEUP_PIN6_HIGH)  || \
00500                                  ((PIN) == PWR_WAKEUP_PIN1_LOW)   || \
00501                                  ((PIN) == PWR_WAKEUP_PIN2_LOW)   || \
00502                                  ((PIN) == PWR_WAKEUP_PIN3_LOW)   || \
00503                                  ((PIN) == PWR_WAKEUP_PIN4_LOW)   || \
00504                                  ((PIN) == PWR_WAKEUP_PIN5_LOW)    || \
00505                                  ((PIN) == PWR_WAKEUP_PIN6_LOW))
00506
00507 #define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY)  (((POLARITY) == PWR_PIN_POLARITY_HIGH) || \
00508                                                ((POLARITY) == PWR_PIN_POLARITY_LOW))
00509
00510 #define IS_PWR_WAKEUP_PIN_PULL(PULL)  (((PULL) == PWR_PIN_NO_PULL)  || \
00511                                        ((PULL) == PWR_PIN_PULL_UP)  || \
00512                                        ((PULL) == PWR_PIN_PULL_DOWN))
00513
00514 #define IS_PWR_WAKEUP_FLAG(FLAG)  (((FLAG) == PWR_WAKEUP_FLAG1)  || \
00515                                    ((FLAG) == PWR_WAKEUP_FLAG2)  || \
00516                                    ((FLAG) == PWR_WAKEUP_FLAG3)  || \
00517                                    ((FLAG) == PWR_WAKEUP_FLAG4)  || \
00518                                    ((FLAG) == PWR_WAKEUP_FLAG5)  || \
00519                                    ((FLAG) == PWR_WAKEUP_FLAG6))
00520
00521 #define IS_PWR_AVD_LEVEL(LEVEL)  (((LEVEL) == PWR_AVDLEVEL_0) || ((LEVEL) == PWR_AVDLEVEL_1) || \
00522                                   ((LEVEL) == PWR_AVDLEVEL_2) || ((LEVEL) == PWR_AVDLEVEL_3))
00523
00524 #define IS_PWR_AVD_MODE(MODE)  (((MODE) == PWR_AVD_MODE_IT_RISING)|| ((MODE) == PWR_AVD_MODE_IT_FALLING) || \
00525                                 ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_AVD_MODE_EVENT_RISING) || \
00526                                 ((MODE) == PWR_AVD_MODE_EVENT_FALLING) || ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING) || \
00527                                 ((MODE) == PWR_AVD_MODE_NORMAL))
00528
00529 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR)  (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
00530                                                    ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
00531
00532
00533 /**
00534   * @}
00535   */
00536 /**
00537   * @}
00538   */
00539
00540 /**
00541   * @}
00542   */
00543
00544 /**
00545   * @}
00546   */
00547 #ifdef __cplusplus
00548 }
00549 #endif
00550
00551
00552 #endif /* __STM32H7xx_HAL_PWR_EX_H */
00553
00554 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_qspi.c Source File

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stm32h7xx_hal_qspi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_qspi.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   QSPI HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the QuadSPI interface (QSPI).
00010   *           + Initialization and de-initialization functions
00011   *           + Indirect functional mode management
00012   *           + Memory-mapped functional mode management
00013   *           + Auto-polling functional mode management
00014   *           + Interrupts and flags management
00015   *           + MDMA channel configuration for indirect functional mode
00016   *           + Errors management and abort functionality
00017   *
00018   *
00019   @verbatim
00020  ===============================================================================
00021                         ##### How to use this driver #####
00022  ===============================================================================
00023   [..]
00024     *** Initialization ***
00025     ======================
00026     [..]
00027       (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
00028         (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
00029         (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
00030         (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
00031         (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
00032         (++) If interrupt mode is used, enable and configure QuadSPI global
00033             interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00034         (++) If DMA mode is used, enable the clocks for the QuadSPI MDMA
00035             with __HAL_RCC_MDMA_CLK_ENABLE(), configure MDMA with HAL_MDMA_Init(),
00036             link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
00037             MDMA global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00038       (#) Configure the flash size, the clock prescaler, the fifo threshold, the
00039           clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
00040
00041     *** Indirect functional mode ***
00042     ================================
00043     [..]
00044       (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
00045           functions :
00046          (++) Instruction phase : the mode used and if present the instruction opcode.
00047          (++) Address phase : the mode used and if present the size and the address value.
00048          (++) Alternate-bytes phase : the mode used and if present the size and the alternate
00049              bytes values.
00050          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00051          (++) Data phase : the mode used and if present the number of bytes.
00052          (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
00053              if activated.
00054          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00055       (#) If no data is required for the command, it is sent directly to the memory :
00056          (++) In polling mode, the output of the function is done when the transfer is complete.
00057          (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
00058       (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
00059           HAL_QSPI_Transmit_IT() after the command configuration :
00060          (++) In polling mode, the output of the function is done when the transfer is complete.
00061          (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
00062              is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
00063          (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
00064              HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
00065       (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
00066           HAL_QSPI_Receive_IT() after the command configuration :
00067          (++) In polling mode, the output of the function is done when the transfer is complete.
00068          (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
00069              is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
00070          (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
00071              HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
00072
00073     *** Auto-polling functional mode ***
00074     ====================================
00075     [..]
00076       (#) Configure the command sequence and the auto-polling functional mode using the
00077           HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
00078          (++) Instruction phase : the mode used and if present the instruction opcode.
00079          (++) Address phase : the mode used and if present the size and the address value.
00080          (++) Alternate-bytes phase : the mode used and if present the size and the alternate
00081              bytes values.
00082          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00083          (++) Data phase : the mode used.
00084          (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
00085              if activated.
00086          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00087          (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
00088              the polling interval and the automatic stop activation.
00089       (#) After the configuration :
00090          (++) In polling mode, the output of the function is done when the status match is reached. The
00091              automatic stop is activated to avoid an infinite loop.
00092          (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
00093
00094     *** Memory-mapped functional mode ***
00095     =====================================
00096     [..]
00097       (#) Configure the command sequence and the memory-mapped functional mode using the
00098           HAL_QSPI_MemoryMapped() functions :
00099          (++) Instruction phase : the mode used and if present the instruction opcode.
00100          (++) Address phase : the mode used and the size.
00101          (++) Alternate-bytes phase : the mode used and if present the size and the alternate
00102              bytes values.
00103          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00104          (++) Data phase : the mode used.
00105          (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
00106              if activated.
00107          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00108          (++) The timeout activation and the timeout period.
00109       (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
00110           the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
00111
00112     *** Errors management and abort functionality ***
00113     =================================================
00114     [..]
00115       (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
00116       (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
00117           flushes the fifo :
00118          (++) In polling mode, the output of the function is done when the transfer
00119               complete bit is set and the busy bit cleared.
00120          (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
00121               the transfer complete bi is set.
00122
00123     *** Control functions ***
00124     =========================
00125     [..]
00126       (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
00127       (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
00128       (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
00129       (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
00130
00131     *** Workarounds linked to Silicon Limitation ***
00132     ====================================================
00133     [..]
00134       (#) Workarounds Implemented inside HAL Driver
00135          (++) Extra data written in the FIFO at the end of a read transfer
00136
00137   @endverbatim
00138   ******************************************************************************
00139   * @attention
00140   *
00141   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00142   *
00143   * Redistribution and use in source and binary forms, with or without modification,
00144   * are permitted provided that the following conditions are met:
00145   *   1. Redistributions of source code must retain the above copyright notice,
00146   *      this list of conditions and the following disclaimer.
00147   *   2. Redistributions in binary form must reproduce the above copyright notice,
00148   *      this list of conditions and the following disclaimer in the documentation
00149   *      and/or other materials provided with the distribution.
00150   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00151   *      may be used to endorse or promote products derived from this software
00152   *      without specific prior written permission.
00153   *
00154   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00155   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00156   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00157   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00158   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00159   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00160   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00161   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00162   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00163   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00164   *
00165   ******************************************************************************
00166   */
00167
00168 /* Includes ------------------------------------------------------------------*/
00169 #include "stm32h7xx_hal.h"
00170
00171 /** @addtogroup STM32H7xx_HAL_Driver
00172   * @{
00173   */
00174
00175 /** @defgroup QSPI QSPI
00176   * @brief QSPI HAL module driver
00177   * @{
00178   */
00179 #ifdef HAL_QSPI_MODULE_ENABLED
00180
00181 /* Private typedef -----------------------------------------------------------*/
00182
00183 /* Private define ------------------------------------------------------------*/
00184 /** @defgroup QSPI_Private_Constants QSPI Private Constants
00185   * @{
00186   */
00187 #define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000)          /*!<Indirect write mode*/
00188 #define QSPI_FUNCTIONAL_MODE_INDIRECT_READ  ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
00189 #define QSPI_FUNCTIONAL_MODE_AUTO_POLLING   ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
00190 #define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED  ((uint32_t)QUADSPI_CCR_FMODE)   /*!<Memory-mapped mode*/
00191 /**
00192   * @}
00193   */
00194
00195 /* Private macro -------------------------------------------------------------*/
00196 /** @defgroup QSPI_Private_Macros QSPI Private Macros
00197   * @{
00198   */
00199 #define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
00200                                        ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \
00201                                        ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \
00202                                        ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
00203 /**
00204   * @}
00205   */
00206
00207 /* Private variables ---------------------------------------------------------*/
00208
00209 /* Private function prototypes -----------------------------------------------*/
00210 static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma);
00211 static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma);
00212 static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma);
00213 static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma);
00214 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t tickstart, uint32_t Timeout);
00215 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
00216
00217 /* Exported functions --------------------------------------------------------*/
00218
00219 /** @defgroup QSPI_Exported_Functions QSPI Exported Functions
00220   * @{
00221   */
00222
00223 /** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
00224   *  @brief    Initialization and Configuration functions
00225   *
00226 @verbatim
00227 ===============================================================================
00228             ##### Initialization and Configuration functions #####
00229  ===============================================================================
00230     [..]
00231     This subsection provides a set of functions allowing to :
00232       (+) Initialize the QuadSPI.
00233       (+) De-initialize the QuadSPI.
00234
00235 @endverbatim
00236   * @{
00237   */
00238
00239 /**
00240   * @brief Initialize the QSPI mode according to the specified parameters
00241   *        in the QSPI_InitTypeDef and initialize the associated handle.
00242   * @param hqspi: QSPI handle
00243   * @retval HAL status
00244   */
00245 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
00246 {
00247   HAL_StatusTypeDef status = HAL_ERROR;
00248   uint32_t tickstart = HAL_GetTick();
00249
00250   /* Check the QSPI handle allocation */
00251   if(hqspi == NULL)
00252   {
00253     return HAL_ERROR;
00254   }
00255
00256   /* Check the parameters */
00257   assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
00258   assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
00259   assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
00260   assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
00261   assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
00262   assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
00263   assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
00264   assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
00265
00266   if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
00267   {
00268     assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
00269   }
00270
00271   /* Process locked */
00272   __HAL_LOCK(hqspi);
00273
00274   if(hqspi->State == HAL_QSPI_STATE_RESET)
00275   {
00276     /* Allocate lock resource and initialize it */
00277     hqspi->Lock = HAL_UNLOCKED;
00278
00279     /* Init the low level hardware : GPIO, CLOCK */
00280     HAL_QSPI_MspInit(hqspi);
00281
00282     /* Configure the default timeout for the QSPI memory access */
00283     HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
00284   }
00285
00286   /* Configure QSPI FIFO Threshold */
00287   MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
00288              ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES)));
00289
00290   /* Wait till BUSY flag reset */
00291   status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
00292
00293   if(status == HAL_OK)
00294   {
00295     /* Configure QSPI Clock Prescaler and Sample Shift */
00296     MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
00297                ((hqspi->Init.ClockPrescaler << POSITION_VAL(QUADSPI_CR_PRESCALER)) |
00298                 hqspi->Init.SampleShifting  | hqspi->Init.FlashID | hqspi->Init.DualFlash));
00299
00300     /* Configure QSPI Flash Size, CS High Time and Clock Mode */
00301     MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
00302                ((hqspi->Init.FlashSize << POSITION_VAL(QUADSPI_DCR_FSIZE)) |
00303                 hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
00304
00305     /* Enable the QSPI peripheral */
00306     __HAL_QSPI_ENABLE(hqspi);
00307
00308     /* Set QSPI error code to none */
00309     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00310
00311     /* Initialize the QSPI state */
00312     hqspi->State = HAL_QSPI_STATE_READY;
00313   }
00314
00315   /* Release Lock */
00316   __HAL_UNLOCK(hqspi);
00317
00318   /* Return function status */
00319   return status;
00320 }
00321
00322 /**
00323   * @brief De-Initialize the QSPI peripheral.
00324   * @param hqspi: QSPI handle
00325   * @retval HAL status
00326   */
00327 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
00328 {
00329   /* Check the QSPI handle allocation */
00330   if(hqspi == NULL)
00331   {
00332     return HAL_ERROR;
00333   }
00334
00335   /* Process locked */
00336   __HAL_LOCK(hqspi);
00337
00338   /* Disable the QSPI Peripheral Clock */
00339   __HAL_QSPI_DISABLE(hqspi);
00340
00341   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00342   HAL_QSPI_MspDeInit(hqspi);
00343
00344   /* Set QSPI error code to none */
00345   hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00346
00347   /* Initialize the QSPI state */
00348   hqspi->State = HAL_QSPI_STATE_RESET;
00349
00350   /* Release Lock */
00351   __HAL_UNLOCK(hqspi);
00352
00353   return HAL_OK;
00354 }
00355
00356 /**
00357   * @brief Initialize the QSPI MSP.
00358   * @param hqspi: QSPI handle
00359   * @retval None
00360   */
00361 __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
00362 {
00363   /* Prevent unused argument(s) compilation warning */
00364   UNUSED(hqspi);
00365
00366   /* NOTE : This function should not be modified, when the callback is needed,
00367             the HAL_QSPI_MspInit can be implemented in the user file
00368    */
00369 }
00370
00371 /**
00372   * @brief DeInitialize the QSPI MSP.
00373   * @param hqspi: QSPI handle
00374   * @retval None
00375   */
00376 __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
00377 {
00378   /* Prevent unused argument(s) compilation warning */
00379   UNUSED(hqspi);
00380
00381   /* NOTE : This function should not be modified, when the callback is needed,
00382             the HAL_QSPI_MspDeInit can be implemented in the user file
00383    */
00384 }
00385
00386 /**
00387   * @}
00388   */
00389
00390 /** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions
00391   *  @brief QSPI Transmit/Receive functions
00392   *
00393 @verbatim
00394  ===============================================================================
00395                       ##### IO operation functions #####
00396  ===============================================================================
00397     [..]
00398     This subsection provides a set of functions allowing to :
00399       (+) Handle the interrupts.
00400       (+) Handle the command sequence.
00401       (+) Transmit data in blocking, interrupt or DMA mode.
00402       (+) Receive data in blocking, interrupt or DMA mode.
00403       (+) Manage the auto-polling functional mode.
00404       (+) Manage the memory-mapped functional mode.
00405
00406 @endverbatim
00407   * @{
00408   */
00409
00410 /**
00411   * @brief Handle QSPI interrupt request.
00412   * @param hqspi: QSPI handle
00413   * @retval None
00414   */
00415 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
00416 {
00417   __IO uint32_t *data_reg;
00418   uint32_t flag = READ_REG(hqspi->Instance->SR);
00419   uint32_t itsource = READ_REG(hqspi->Instance->CR);
00420
00421   /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
00422   if((flag & QSPI_FLAG_FT) && (itsource & QSPI_IT_FT))
00423   {
00424     data_reg = &hqspi->Instance->DR;
00425
00426     if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
00427     {
00428       /* Transmission process */
00429       while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
00430       {
00431         if (hqspi->TxXferCount > 0)
00432         {
00433           /* Fill the FIFO until the threshold is reached */
00434           *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
00435           hqspi->TxXferCount--;
00436         }
00437         else
00438         {
00439           /* No more data available for the transfer */
00440           /* Disable the QSPI FIFO Threshold Interrupt */
00441           __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
00442           break;
00443         }
00444       }
00445     }
00446     else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
00447     {
00448       /* Receiving Process */
00449       while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
00450       {
00451         if (hqspi->RxXferCount > 0)
00452         {
00453           /* Read the FIFO until the threshold is reached */
00454           *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
00455           hqspi->RxXferCount--;
00456         }
00457         else
00458         {
00459           /* All data have been received for the transfer */
00460           /* Disable the QSPI FIFO Threshold Interrupt */
00461           __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
00462           break;
00463         }
00464       }
00465     }
00466
00467     /* FIFO Threshold callback */
00468     HAL_QSPI_FifoThresholdCallback(hqspi);
00469   }
00470
00471   /* QSPI Transfer Complete interrupt occurred -------------------------------*/
00472   else if((flag & QSPI_FLAG_TC) && (itsource & QSPI_IT_TC))
00473   {
00474     /* Clear interrupt */
00475     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
00476
00477     /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
00478     __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
00479
00480     /* Transfer complete callback */
00481     if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
00482     {
00483       if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
00484       {
00485         /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
00486         CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
00487
00488         /* Disable the MDMA channel */
00489         __HAL_MDMA_DISABLE(hqspi->hmdma);
00490       }
00491
00492       /* Change state of QSPI */
00493       hqspi->State = HAL_QSPI_STATE_READY;
00494
00495       /* TX Complete callback */
00496       HAL_QSPI_TxCpltCallback(hqspi);
00497     }
00498     else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
00499     {
00500       if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
00501       {
00502         /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
00503         CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
00504
00505         /* Disable the MDMA channel */
00506         __HAL_MDMA_DISABLE(hqspi->hmdma);
00507       }
00508       else
00509       {
00510         data_reg = &hqspi->Instance->DR;
00511         while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
00512         {
00513           if (hqspi->RxXferCount > 0)
00514           {
00515             /* Read the last data received in the FIFO until it is empty */
00516             *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
00517             hqspi->RxXferCount--;
00518           }
00519           else
00520           {
00521             /* All data have been received for the transfer */
00522             break;
00523           }
00524         }
00525       }
00526
00527       /* Change state of QSPI */
00528       hqspi->State = HAL_QSPI_STATE_READY;
00529
00530       /* RX Complete callback */
00531       HAL_QSPI_RxCpltCallback(hqspi);
00532     }
00533     else if(hqspi->State == HAL_QSPI_STATE_BUSY)
00534     {
00535       /* Change state of QSPI */
00536       hqspi->State = HAL_QSPI_STATE_READY;
00537
00538       /* Command Complete callback */
00539       HAL_QSPI_CmdCpltCallback(hqspi);
00540     }
00541     else if(hqspi->State == HAL_QSPI_STATE_ABORT)
00542     {
00543       /* Change state of QSPI */
00544       hqspi->State = HAL_QSPI_STATE_READY;
00545
00546       if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
00547       {
00548         /* Abort called by the user */
00549
00550         /* Abort Complete callback */
00551         HAL_QSPI_AbortCpltCallback(hqspi);
00552       }
00553       else
00554       {
00555         /* Abort due to an error (eg :  MDMA error) */
00556
00557         /* Error callback */
00558         HAL_QSPI_ErrorCallback(hqspi);
00559       }
00560     }
00561   }
00562
00563   /* QSPI Status Match interrupt occurred ------------------------------------*/
00564   else if((flag & QSPI_FLAG_SM) && (itsource & QSPI_IT_SM))
00565   {
00566     /* Clear interrupt */
00567     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
00568
00569     /* Check if the automatic poll mode stop is activated */
00570     if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
00571     {
00572       /* Disable the QSPI Transfer Error and Status Match Interrupts */
00573       __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
00574
00575       /* Change state of QSPI */
00576       hqspi->State = HAL_QSPI_STATE_READY;
00577     }
00578
00579     /* Status match callback */
00580     HAL_QSPI_StatusMatchCallback(hqspi);
00581   }
00582
00583   /* QSPI Transfer Error interrupt occurred ----------------------------------*/
00584   else if((flag & QSPI_FLAG_TE) && (itsource & QSPI_IT_TE))
00585   {
00586     /* Clear interrupt */
00587     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
00588
00589     /* Disable all the QSPI Interrupts */
00590     __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
00591
00592     /* Set error code */
00593     hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
00594
00595     if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
00596     {
00597       /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
00598       CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
00599
00600       /* Disable the MDMA channel */
00601       hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt;
00602       HAL_MDMA_Abort_IT(hqspi->hmdma);
00603
00604     }
00605     else
00606     {
00607       /* Change state of QSPI */
00608       hqspi->State = HAL_QSPI_STATE_READY;
00609
00610       /* Error callback */
00611       HAL_QSPI_ErrorCallback(hqspi);
00612     }
00613   }
00614
00615   /* QSPI Timeout interrupt occurred -----------------------------------------*/
00616   else if((flag & QSPI_FLAG_TO) && (itsource & QSPI_IT_TO))
00617   {
00618     /* Clear interrupt */
00619     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
00620
00621     /* Timeout callback */
00622     HAL_QSPI_TimeOutCallback(hqspi);
00623   }
00624 }
00625
00626 /**
00627   * @brief Set the command configuration.
00628   * @param hqspi: QSPI handle
00629   * @param cmd : structure that contains the command configuration information
00630   * @param Timeout : Timeout duration
00631   * @note   This function is used only in Indirect Read or Write Modes
00632   * @retval HAL status
00633   */
00634 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
00635 {
00636   HAL_StatusTypeDef status = HAL_ERROR;
00637   uint32_t tickstart = HAL_GetTick();
00638
00639   /* Check the parameters */
00640   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
00641   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
00642   {
00643     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
00644   }
00645
00646   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
00647   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
00648   {
00649     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
00650   }
00651
00652   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
00653   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
00654   {
00655     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
00656   }
00657
00658   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
00659   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
00660
00661   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
00662   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
00663   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
00664
00665   /* Process locked */
00666   __HAL_LOCK(hqspi);
00667
00668   if(hqspi->State == HAL_QSPI_STATE_READY)
00669   {
00670     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00671
00672     /* Update QSPI state */
00673     hqspi->State = HAL_QSPI_STATE_BUSY;
00674
00675     /* Wait till BUSY flag reset */
00676     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
00677
00678     if (status == HAL_OK)
00679     {
00680       /* Call the configuration function */
00681       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00682
00683       if (cmd->DataMode == QSPI_DATA_NONE)
00684       {
00685         /* When there is no data phase, the transfer start as soon as the configuration is done
00686         so wait until TC flag is set to go back in idle state */
00687         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
00688
00689         if (status == HAL_OK)
00690         {
00691           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
00692
00693           /* Update QSPI state */
00694           hqspi->State = HAL_QSPI_STATE_READY;
00695         }
00696
00697       }
00698       else
00699       {
00700         /* Update QSPI state */
00701         hqspi->State = HAL_QSPI_STATE_READY;
00702       }
00703     }
00704   }
00705   else
00706   {
00707     status = HAL_BUSY;
00708   }
00709
00710   /* Process unlocked */
00711   __HAL_UNLOCK(hqspi);
00712
00713   /* Return function status */
00714   return status;
00715 }
00716
00717 /**
00718   * @brief Set the command configuration in interrupt mode.
00719   * @param hqspi: QSPI handle
00720   * @param cmd : structure that contains the command configuration information
00721   * @note   This function is used only in Indirect Read or Write Modes
00722   * @retval HAL status
00723   */
00724 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
00725 {
00726   HAL_StatusTypeDef status = HAL_ERROR;
00727   uint32_t tickstart = HAL_GetTick();
00728
00729   /* Check the parameters */
00730   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
00731   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
00732   {
00733     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
00734   }
00735
00736   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
00737   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
00738   {
00739     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
00740   }
00741
00742   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
00743   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
00744   {
00745     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
00746   }
00747
00748   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
00749   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
00750
00751   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
00752   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
00753   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
00754
00755   /* Process locked */
00756   __HAL_LOCK(hqspi);
00757
00758   if(hqspi->State == HAL_QSPI_STATE_READY)
00759   {
00760     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00761
00762     /* Update QSPI state */
00763     hqspi->State = HAL_QSPI_STATE_BUSY;
00764
00765     /* Wait till BUSY flag reset */
00766     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
00767
00768     if (status == HAL_OK)
00769     {
00770       if (cmd->DataMode == QSPI_DATA_NONE)
00771       {
00772         /* Clear interrupt */
00773         __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
00774       }
00775
00776       /* Call the configuration function */
00777       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00778
00779       if (cmd->DataMode == QSPI_DATA_NONE)
00780       {
00781         /* When there is no data phase, the transfer start as soon as the configuration is done
00782         so activate TC and TE interrupts */
00783         /* Process unlocked */
00784         __HAL_UNLOCK(hqspi);
00785
00786         /* Enable the QSPI Transfer Error Interrupt */
00787         __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
00788       }
00789       else
00790       {
00791         /* Update QSPI state */
00792         hqspi->State = HAL_QSPI_STATE_READY;
00793
00794         /* Process unlocked */
00795         __HAL_UNLOCK(hqspi);
00796       }
00797     }
00798     else
00799     {
00800       /* Process unlocked */
00801       __HAL_UNLOCK(hqspi);
00802     }
00803   }
00804   else
00805   {
00806     status = HAL_BUSY;
00807
00808     /* Process unlocked */
00809     __HAL_UNLOCK(hqspi);
00810   }
00811
00812   /* Return function status */
00813   return status;
00814 }
00815
00816 /**
00817   * @brief Transmit an amount of data in blocking mode.
00818   * @param hqspi: QSPI handle
00819   * @param pData: pointer to data buffer
00820   * @param Timeout : Timeout duration
00821   * @note   This function is used only in Indirect Write Mode
00822   * @retval HAL status
00823   */
00824 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
00825 {
00826   HAL_StatusTypeDef status = HAL_OK;
00827   uint32_t tickstart = HAL_GetTick();
00828   __IO uint32_t *data_reg = &hqspi->Instance->DR;
00829
00830   /* Process locked */
00831   __HAL_LOCK(hqspi);
00832
00833   if(hqspi->State == HAL_QSPI_STATE_READY)
00834   {
00835     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00836
00837     if(pData != NULL )
00838     {
00839       /* Update state */
00840       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
00841
00842       /* Configure counters and size of the handle */
00843       hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
00844       hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
00845       hqspi->pTxBuffPtr = pData;
00846
00847       /* Configure QSPI: CCR register with functional as indirect write */
00848       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00849
00850       while(hqspi->TxXferCount > 0)
00851       {
00852         /* Wait until FT flag is set to send data */
00853         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
00854
00855         if (status != HAL_OK)
00856         {
00857           break;
00858         }
00859
00860         *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
00861         hqspi->TxXferCount--;
00862       }
00863
00864       if (status == HAL_OK)
00865       {
00866         /* Wait until TC flag is set to go back in idle state */
00867         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
00868
00869         if (status == HAL_OK)
00870         {
00871           /* Clear Transfer Complete bit */
00872           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
00873
00874         }
00875       }
00876
00877       /* Update QSPI state */
00878       hqspi->State = HAL_QSPI_STATE_READY;
00879     }
00880     else
00881     {
00882       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
00883       status = HAL_ERROR;
00884     }
00885   }
00886   else
00887   {
00888     status = HAL_BUSY;
00889   }
00890
00891   /* Process unlocked */
00892   __HAL_UNLOCK(hqspi);
00893
00894   return status;
00895 }
00896
00897
00898 /**
00899   * @brief Receive an amount of data in blocking mode.
00900   * @param hqspi: QSPI handle
00901   * @param pData: pointer to data buffer
00902   * @param Timeout : Timeout duration
00903   * @note   This function is used only in Indirect Read Mode
00904   * @retval HAL status
00905   */
00906 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
00907 {
00908   HAL_StatusTypeDef status = HAL_OK;
00909   uint32_t tickstart = HAL_GetTick();
00910   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
00911   __IO uint32_t *data_reg = &hqspi->Instance->DR;
00912
00913   /* Process locked */
00914   __HAL_LOCK(hqspi);
00915
00916   if(hqspi->State == HAL_QSPI_STATE_READY)
00917   {
00918     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00919
00920     if(pData != NULL )
00921     {
00922       /* Update state */
00923       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
00924
00925       /* Configure counters and size of the handle */
00926       hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
00927       hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
00928       hqspi->pRxBuffPtr = pData;
00929
00930       /* Configure QSPI: CCR register with functional as indirect read */
00931       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
00932
00933       /* Start the transfer by re-writing the address in AR register */
00934       WRITE_REG(hqspi->Instance->AR, addr_reg);
00935
00936       while(hqspi->RxXferCount > 0)
00937       {
00938         /* Wait until FT or TC flag is set to read received data */
00939         status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
00940
00941         if  (status != HAL_OK)
00942         {
00943           break;
00944         }
00945
00946         *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
00947         hqspi->RxXferCount--;
00948       }
00949
00950       if (status == HAL_OK)
00951       {
00952         /* Wait until TC flag is set to go back in idle state */
00953         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
00954
00955         if  (status == HAL_OK)
00956         {
00957           /* Clear Transfer Complete bit */
00958           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
00959         }
00960       }
00961
00962       /* Update QSPI state */
00963       hqspi->State = HAL_QSPI_STATE_READY;
00964     }
00965     else
00966     {
00967       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
00968       status = HAL_ERROR;
00969     }
00970   }
00971   else
00972   {
00973     status = HAL_BUSY;
00974   }
00975
00976   /* Process unlocked */
00977   __HAL_UNLOCK(hqspi);
00978
00979   return status;
00980 }
00981
00982 /**
00983   * @brief  Send an amount of data in non-blocking mode with interrupt.
00984   * @param  hqspi: QSPI handle
00985   * @param  pData: pointer to data buffer
00986   * @note   This function is used only in Indirect Write Mode
00987   * @retval HAL status
00988   */
00989 HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
00990 {
00991   HAL_StatusTypeDef status = HAL_OK;
00992
00993   /* Process locked */
00994   __HAL_LOCK(hqspi);
00995
00996   if(hqspi->State == HAL_QSPI_STATE_READY)
00997   {
00998     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00999
01000     if(pData != NULL )
01001     {
01002       /* Update state */
01003       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
01004
01005       /* Configure counters and size of the handle */
01006       hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
01007       hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
01008       hqspi->pTxBuffPtr = pData;
01009
01010       /* Configure QSPI: CCR register with functional as indirect write */
01011       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
01012
01013       /* Clear interrupt */
01014       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
01015
01016       /* Process unlocked */
01017       __HAL_UNLOCK(hqspi);
01018
01019       /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
01020       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
01021     }
01022     else
01023     {
01024       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01025       status = HAL_ERROR;
01026
01027       /* Process unlocked */
01028       __HAL_UNLOCK(hqspi);
01029     }
01030   }
01031   else
01032   {
01033     status = HAL_BUSY;
01034
01035     /* Process unlocked */
01036     __HAL_UNLOCK(hqspi);
01037   }
01038
01039   return status;
01040 }
01041
01042 /**
01043   * @brief  Receive an amount of data in non-blocking mode with interrupt.
01044   * @param  hqspi: QSPI handle
01045   * @param  pData: pointer to data buffer
01046   * @note   This function is used only in Indirect Read Mode
01047   * @retval HAL status
01048   */
01049 HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01050 {
01051   HAL_StatusTypeDef status = HAL_OK;
01052   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
01053
01054   /* Process locked */
01055   __HAL_LOCK(hqspi);
01056
01057   if(hqspi->State == HAL_QSPI_STATE_READY)
01058   {
01059     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01060
01061     if(pData != NULL )
01062     {
01063       /* Update state */
01064       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
01065
01066       /* Configure counters and size of the handle */
01067       hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
01068       hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
01069       hqspi->pRxBuffPtr = pData;
01070
01071       /* Configure QSPI: CCR register with functional as indirect read */
01072       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
01073
01074       /* Start the transfer by re-writing the address in AR register */
01075       WRITE_REG(hqspi->Instance->AR, addr_reg);
01076
01077       /* Clear interrupt */
01078       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
01079
01080       /* Process unlocked */
01081       __HAL_UNLOCK(hqspi);
01082
01083       /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
01084       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
01085     }
01086     else
01087     {
01088       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01089       status = HAL_ERROR;
01090
01091       /* Process unlocked */
01092       __HAL_UNLOCK(hqspi);
01093     }
01094   }
01095   else
01096   {
01097     status = HAL_BUSY;
01098
01099     /* Process unlocked */
01100     __HAL_UNLOCK(hqspi);
01101   }
01102
01103   return status;
01104 }
01105
01106 /**
01107   * @brief  Send an amount of data in non-blocking mode with DMA.
01108   * @param  hqspi: QSPI handle
01109   * @param  pData: pointer to data buffer
01110   * @note   This function is used only in Indirect Write Mode
01111   * @note   If MDMA peripheral access is configured as halfword, the number
01112   *         of data and the fifo threshold should be aligned on halfword
01113   * @note   If MDMA peripheral access is configured as word, the number
01114   *         of data and the fifo threshold should be aligned on word
01115   * @retval HAL status
01116   */
01117 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01118 {
01119   HAL_StatusTypeDef status = HAL_OK;
01120   uint32_t *tmp;
01121
01122   /* Process locked */
01123   __HAL_LOCK(hqspi);
01124
01125   if(hqspi->State == HAL_QSPI_STATE_READY)
01126   {
01127     /* Clear the error code */
01128     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01129
01130     if(pData != NULL )
01131     {
01132
01133       /* Update state */
01134       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
01135
01136       /* Clear interrupt */
01137       __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
01138
01139       /* Configure counters and size of the handle */
01140       hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
01141       hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
01142       hqspi->pTxBuffPtr = pData;
01143
01144       /* Configure QSPI: CCR register with functional mode as indirect write */
01145       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
01146
01147       /* Set the QSPI MDMA transfer complete callback */
01148       hqspi->hmdma->XferCpltCallback = QSPI_DMATxCplt;
01149
01150       /* Set the MDMA error callback */
01151       hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
01152
01153       /* Clear the MDMA abort callback */
01154       hqspi->hmdma->XferAbortCallback = NULL;
01155
01156       if(hqspi->hmdma->Init.DestinationInc != MDMA_DEST_INC_DISABLE)
01157       {
01158         /* Update MDMA handle with the correct DestinationInc and SourceInc field for Write operation */
01159         hqspi->hmdma->Init.DestinationInc = MDMA_DEST_INC_DISABLE;
01160         hqspi->hmdma->Init.SourceInc = MDMA_SRC_INC_BYTE;
01161         HAL_MDMA_Init(hqspi->hmdma);
01162       }
01163
01164       /* Enable the QSPI transmit MDMA */
01165       tmp = (uint32_t*)&pData;
01166       HAL_MDMA_Start_IT(hqspi->hmdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize, 1);
01167
01168       /* Process unlocked */
01169       __HAL_UNLOCK(hqspi);
01170
01171       /* Enable the QSPI transfer error Interrupt */
01172       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
01173
01174       /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
01175     }
01176     else
01177     {
01178       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01179       status = HAL_ERROR;
01180
01181       /* Process unlocked */
01182       __HAL_UNLOCK(hqspi);
01183     }
01184   }
01185   else
01186   {
01187     status = HAL_BUSY;
01188
01189     /* Process unlocked */
01190     __HAL_UNLOCK(hqspi);
01191   }
01192
01193   return status;
01194 }
01195
01196 /**
01197   * @brief  Receive an amount of data in non-blocking mode with DMA.
01198   * @param  hqspi: QSPI handle
01199   * @param  pData: pointer to data buffer.
01200   * @note   This function is used only in Indirect Read Mode
01201   * @retval HAL status
01202   */
01203 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01204 {
01205   HAL_StatusTypeDef status = HAL_OK;
01206   uint32_t *tmp;
01207   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
01208
01209   /* Process locked */
01210   __HAL_LOCK(hqspi);
01211
01212   if(hqspi->State == HAL_QSPI_STATE_READY)
01213   {
01214     /* Clear the error code */
01215     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01216
01217     if(pData != NULL )
01218     {
01219
01220       /* Update state */
01221       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
01222
01223       /* Clear interrupt */
01224       __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
01225
01226       /* Configure counters and size of the handle */
01227       hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
01228       hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
01229       hqspi->pRxBuffPtr = pData;
01230
01231       /* Set the QSPI DMA transfer complete callback */
01232       hqspi->hmdma->XferCpltCallback = QSPI_DMARxCplt;
01233
01234       /* Set the MDMA error callback */
01235       hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
01236
01237       /* Clear the MDMA abort callback */
01238       hqspi->hmdma->XferAbortCallback = NULL;
01239
01240
01241       /* QSPI need to be configured to indirect mode before starting
01242          the MDMA to avoid primatury triggering for the MDMA transfert */
01243       /* Configure QSPI: CCR register with functional as indirect read */
01244       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
01245
01246
01247       /* Start the transfer by re-writing the address in AR register */
01248       WRITE_REG(hqspi->Instance->AR, addr_reg);
01249
01250       if(hqspi->hmdma->Init.DestinationInc != MDMA_DEST_INC_BYTE)
01251       {
01252         /* Update MDMA handle with the correct DestinationInc and SourceInc field for Read operation */
01253         hqspi->hmdma->Init.DestinationInc = MDMA_DEST_INC_BYTE;
01254         hqspi->hmdma->Init.SourceInc = MDMA_SRC_INC_DISABLE;
01255         HAL_MDMA_Init(hqspi->hmdma);
01256       }
01257
01258       /* Enable the MDMA */
01259       tmp = (uint32_t*)&pData;
01260       HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize, 1);
01261
01262
01263       /* Process unlocked */
01264       __HAL_UNLOCK(hqspi);
01265
01266       /* Enable the QSPI transfer error Interrupt */
01267       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
01268
01269       /* Enable the MDMA transfer by setting the DMAEN bit in the QSPI CR register */
01270       SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
01271     }
01272     else
01273     {
01274       status = HAL_ERROR;
01275
01276       /* Process unlocked */
01277       __HAL_UNLOCK(hqspi);
01278     }
01279   }
01280   else
01281   {
01282     status = HAL_BUSY;
01283
01284     /* Process unlocked */
01285     __HAL_UNLOCK(hqspi);
01286   }
01287
01288   return status;
01289 }
01290
01291 /**
01292   * @brief  Configure the QSPI Automatic Polling Mode in blocking mode.
01293   * @param  hqspi: QSPI handle
01294   * @param  cmd: structure that contains the command configuration information.
01295   * @param  cfg: structure that contains the polling configuration information.
01296   * @param  Timeout : Timeout duration
01297   * @note   This function is used only in Automatic Polling Mode
01298   * @retval HAL status
01299   */
01300 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
01301 {
01302   HAL_StatusTypeDef status = HAL_ERROR;
01303   uint32_t tickstart = HAL_GetTick();
01304
01305   /* Check the parameters */
01306   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
01307   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01308   {
01309     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
01310   }
01311
01312   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
01313   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01314   {
01315     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
01316   }
01317
01318   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
01319   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01320   {
01321     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
01322   }
01323
01324   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
01325   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
01326
01327   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
01328   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
01329   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
01330
01331   assert_param(IS_QSPI_INTERVAL(cfg->Interval));
01332   assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
01333   assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
01334
01335   /* Process locked */
01336   __HAL_LOCK(hqspi);
01337
01338   if(hqspi->State == HAL_QSPI_STATE_READY)
01339   {
01340     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01341
01342     /* Update state */
01343     hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
01344
01345     /* Wait till BUSY flag reset */
01346     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
01347
01348     if (status == HAL_OK)
01349     {
01350       /* Configure QSPI: PSMAR register with the status match value */
01351       WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
01352
01353       /* Configure QSPI: PSMKR register with the status mask value */
01354       WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
01355
01356       /* Configure QSPI: PIR register with the interval value */
01357       WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
01358
01359       /* Configure QSPI: CR register with Match mode and Automatic stop enabled
01360       (otherwise there will be an infinite loop in blocking mode) */
01361       MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
01362                (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
01363
01364       /* Call the configuration function */
01365       cmd->NbData = cfg->StatusBytesSize;
01366       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
01367
01368       /* Wait until SM flag is set to go back in idle state */
01369       status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
01370
01371       if (status == HAL_OK)
01372       {
01373         __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
01374
01375         /* Update state */
01376         hqspi->State = HAL_QSPI_STATE_READY;
01377       }
01378     }
01379   }
01380   else
01381   {
01382     status = HAL_BUSY;
01383   }
01384
01385   /* Process unlocked */
01386   __HAL_UNLOCK(hqspi);
01387
01388   /* Return function status */
01389   return status;
01390 }
01391
01392 /**
01393   * @brief  Configure the QSPI Automatic Polling Mode in non-blocking mode.
01394   * @param  hqspi: QSPI handle
01395   * @param  cmd: structure that contains the command configuration information.
01396   * @param  cfg: structure that contains the polling configuration information.
01397   * @note   This function is used only in Automatic Polling Mode
01398   * @retval HAL status
01399   */
01400 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
01401 {
01402   HAL_StatusTypeDef status = HAL_ERROR;
01403   uint32_t tickstart = HAL_GetTick();
01404
01405   /* Check the parameters */
01406   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
01407   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01408   {
01409     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
01410   }
01411
01412   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
01413   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01414   {
01415     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
01416   }
01417
01418   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
01419   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01420   {
01421     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
01422   }
01423
01424   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
01425   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
01426
01427   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
01428   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
01429   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
01430
01431   assert_param(IS_QSPI_INTERVAL(cfg->Interval));
01432   assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
01433   assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
01434   assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
01435
01436   /* Process locked */
01437   __HAL_LOCK(hqspi);
01438
01439   if(hqspi->State == HAL_QSPI_STATE_READY)
01440   {
01441     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01442
01443     /* Update state */
01444     hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
01445
01446     /* Wait till BUSY flag reset */
01447     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
01448
01449     if (status == HAL_OK)
01450     {
01451       /* Configure QSPI: PSMAR register with the status match value */
01452       WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
01453
01454       /* Configure QSPI: PSMKR register with the status mask value */
01455       WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
01456
01457       /* Configure QSPI: PIR register with the interval value */
01458       WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
01459
01460       /* Configure QSPI: CR register with Match mode and Automatic stop mode */
01461       MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
01462                (cfg->MatchMode | cfg->AutomaticStop));
01463
01464       /* Clear interrupt */
01465       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
01466
01467       /* Call the configuration function */
01468       cmd->NbData = cfg->StatusBytesSize;
01469       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
01470
01471       /* Process unlocked */
01472       __HAL_UNLOCK(hqspi);
01473
01474       /* Enable the QSPI Transfer Error and status match Interrupt */
01475       __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
01476
01477     }
01478     else
01479     {
01480       /* Process unlocked */
01481       __HAL_UNLOCK(hqspi);
01482     }
01483   }
01484   else
01485   {
01486     status = HAL_BUSY;
01487
01488     /* Process unlocked */
01489     __HAL_UNLOCK(hqspi);
01490   }
01491
01492   /* Return function status */
01493   return status;
01494 }
01495
01496 /**
01497   * @brief  Configure the Memory Mapped mode.
01498   * @param  hqspi: QSPI handle
01499   * @param  cmd: structure that contains the command configuration information.
01500   * @param  cfg: structure that contains the memory mapped configuration information.
01501   * @note   This function is used only in Memory mapped Mode
01502   * @retval HAL status
01503   */
01504 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
01505 {
01506   HAL_StatusTypeDef status = HAL_ERROR;
01507   uint32_t tickstart = HAL_GetTick();
01508
01509   /* Check the parameters */
01510   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
01511   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01512   {
01513   assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
01514   }
01515
01516   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
01517   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01518   {
01519     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
01520   }
01521
01522   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
01523   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01524   {
01525     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
01526   }
01527
01528   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
01529   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
01530
01531   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
01532   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
01533   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
01534
01535   assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
01536
01537   /* Process locked */
01538   __HAL_LOCK(hqspi);
01539
01540   if(hqspi->State == HAL_QSPI_STATE_READY)
01541   {
01542     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01543
01544     /* Update state */
01545     hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
01546
01547     /* Wait till BUSY flag reset */
01548     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
01549
01550     if (status == HAL_OK)
01551     {
01552       /* Configure QSPI: CR register with timeout counter enable */
01553       MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
01554
01555       if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
01556       {
01557         assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
01558
01559         /* Configure QSPI: LPTR register with the low-power timeout value */
01560         WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
01561
01562         /* Clear interrupt */
01563         __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
01564
01565         /* Enable the QSPI TimeOut Interrupt */
01566         __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
01567       }
01568
01569       /* Call the configuration function */
01570       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
01571     }
01572   }
01573   else
01574   {
01575     status = HAL_BUSY;
01576   }
01577
01578   /* Process unlocked */
01579   __HAL_UNLOCK(hqspi);
01580
01581   /* Return function status */
01582   return status;
01583 }
01584
01585 /**
01586   * @brief  Transfer Error callback.
01587   * @param  hqspi: QSPI handle
01588   * @retval None
01589   */
01590 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
01591 {
01592   /* Prevent unused argument(s) compilation warning */
01593   UNUSED(hqspi);
01594
01595   /* NOTE : This function should not be modified, when the callback is needed,
01596             the HAL_QSPI_ErrorCallback could be implemented in the user file
01597    */
01598 }
01599
01600 /**
01601   * @brief  Abort completed callback.
01602   * @param  hqspi: QSPI handle
01603   * @retval None
01604   */
01605 __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
01606 {
01607   /* Prevent unused argument(s) compilation warning */
01608   UNUSED(hqspi);
01609
01610   /* NOTE: This function should not be modified, when the callback is needed,
01611            the HAL_QSPI_AbortCpltCallback could be implemented in the user file
01612    */
01613 }
01614
01615 /**
01616   * @brief  Command completed callback.
01617   * @param  hqspi: QSPI handle
01618   * @retval None
01619   */
01620 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
01621 {
01622   /* Prevent unused argument(s) compilation warning */
01623   UNUSED(hqspi);
01624
01625   /* NOTE: This function should not be modified, when the callback is needed,
01626            the HAL_QSPI_CmdCpltCallback could be implemented in the user file
01627    */
01628 }
01629
01630 /**
01631   * @brief  Rx Transfer completed callback.
01632   * @param  hqspi: QSPI handle
01633   * @retval None
01634   */
01635 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
01636 {
01637   /* Prevent unused argument(s) compilation warning */
01638   UNUSED(hqspi);
01639
01640   /* NOTE: This function should not be modified, when the callback is needed,
01641            the HAL_QSPI_RxCpltCallback could be implemented in the user file
01642    */
01643 }
01644
01645 /**
01646   * @brief  Tx Transfer completed callback.
01647   * @param  hqspi: QSPI handle
01648   * @retval None
01649   */
01650  __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
01651 {
01652   /* Prevent unused argument(s) compilation warning */
01653   UNUSED(hqspi);
01654
01655   /* NOTE: This function should not be modified, when the callback is needed,
01656            the HAL_QSPI_TxCpltCallback could be implemented in the user file
01657    */
01658 }
01659
01660 /**
01661   * @brief  Rx Half Transfer completed callback.
01662   * @param  hqspi: QSPI handle
01663   * @retval None
01664   */
01665 __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
01666 {
01667   /* Prevent unused argument(s) compilation warning */
01668   UNUSED(hqspi);
01669
01670   /* NOTE: This function should not be modified, when the callback is needed,
01671            the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
01672    */
01673 }
01674
01675 /**
01676   * @brief  Tx Half Transfer completed callback.
01677   * @param  hqspi: QSPI handle
01678   * @retval None
01679   */
01680 __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
01681 {
01682   /* Prevent unused argument(s) compilation warning */
01683   UNUSED(hqspi);
01684
01685   /* NOTE: This function should not be modified, when the callback is needed,
01686            the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
01687    */
01688 }
01689
01690 /**
01691   * @brief  FIFO Threshold callback.
01692   * @param  hqspi: QSPI handle
01693   * @retval None
01694   */
01695 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
01696 {
01697   /* Prevent unused argument(s) compilation warning */
01698   UNUSED(hqspi);
01699
01700   /* NOTE : This function should not be modified, when the callback is needed,
01701             the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
01702    */
01703 }
01704
01705 /**
01706   * @brief  Status Match callback.
01707   * @param  hqspi: QSPI handle
01708   * @retval None
01709   */
01710 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
01711 {
01712   /* Prevent unused argument(s) compilation warning */
01713   UNUSED(hqspi);
01714
01715   /* NOTE : This function should not be modified, when the callback is needed,
01716             the HAL_QSPI_StatusMatchCallback could be implemented in the user file
01717    */
01718 }
01719
01720 /**
01721   * @brief  Timeout callback.
01722   * @param  hqspi: QSPI handle
01723   * @retval None
01724   */
01725 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
01726 {
01727   /* Prevent unused argument(s) compilation warning */
01728   UNUSED(hqspi);
01729
01730   /* NOTE : This function should not be modified, when the callback is needed,
01731             the HAL_QSPI_TimeOutCallback could be implemented in the user file
01732    */
01733 }
01734
01735 /**
01736   * @}
01737   */
01738
01739 /** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
01740   *  @brief   QSPI control and State functions
01741   *
01742 @verbatim
01743  ===============================================================================
01744                   ##### Peripheral Control and State functions #####
01745  ===============================================================================
01746     [..]
01747     This subsection provides a set of functions allowing to :
01748       (+) Check in run-time the state of the driver.
01749       (+) Check the error code set during last operation.
01750       (+) Abort any operation.
01751
01752
01753 @endverbatim
01754   * @{
01755   */
01756
01757 /**
01758   * @brief  Return the QSPI handle state.
01759   * @param  hqspi: QSPI handle
01760   * @retval HAL state
01761   */
01762 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
01763 {
01764   /* Return QSPI handle state */
01765   return hqspi->State;
01766 }
01767
01768 /**
01769 * @brief  Return the QSPI error code.
01770 * @param  hqspi: QSPI handle
01771 * @retval QSPI Error Code
01772 */
01773 uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
01774 {
01775   return hqspi->ErrorCode;
01776 }
01777
01778 /**
01779 * @brief  Abort the current transmission.
01780 * @param  hqspi: QSPI handle
01781 * @retval HAL status
01782 */
01783 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
01784 {
01785   HAL_StatusTypeDef status = HAL_OK;
01786   uint32_t tickstart = HAL_GetTick();
01787
01788   /* Check if the state is in one of the busy states */
01789   if ((hqspi->State & 0x2) != 0)
01790   {
01791     /* Process unlocked */
01792     __HAL_UNLOCK(hqspi);
01793
01794     if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
01795     {
01796       /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
01797       CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
01798
01799       /* Abort MDMA */
01800       status = HAL_MDMA_Abort(hqspi->hmdma);
01801       if(status != HAL_OK)
01802       {
01803         hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
01804       }
01805     }
01806
01807     /* Configure QSPI: CR register with Abort request */
01808     SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
01809
01810     /* Wait until TC flag is set to go back in idle state */
01811     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
01812
01813     if(status == HAL_OK)
01814     {
01815       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
01816
01817       /* Wait until BUSY flag is reset */
01818       status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
01819     }
01820
01821     if (status == HAL_OK)
01822     {
01823       /* Update state */
01824       hqspi->State = HAL_QSPI_STATE_READY;
01825     }
01826   }
01827
01828   return status;
01829 }
01830
01831 /**
01832 * @brief  Abort the current transmission (non-blocking function)
01833 * @param  hqspi: QSPI handle
01834 * @retval HAL status
01835 */
01836 HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
01837 {
01838   HAL_StatusTypeDef status = HAL_OK;
01839
01840   /* Check if the state is in one of the busy states */
01841   if ((hqspi->State & 0x2) != 0)
01842   {
01843     /* Process unlocked */
01844     __HAL_UNLOCK(hqspi);
01845
01846     /* Update QSPI state */
01847     hqspi->State = HAL_QSPI_STATE_ABORT;
01848
01849     /* Disable all interrupts */
01850     __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
01851
01852     if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
01853     {
01854       /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
01855       CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
01856
01857       /* Abort MDMA channel */
01858       hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt;
01859       HAL_MDMA_Abort_IT(hqspi->hmdma);
01860     }
01861     else
01862     {
01863       /* Clear interrupt */
01864       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
01865
01866       /* Enable the QSPI Transfer Complete Interrupt */
01867       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
01868
01869       /* Configure QSPI: CR register with Abort request */
01870       SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
01871     }
01872   }
01873   return status;
01874 }
01875
01876 /** @brief Set QSPI timeout.
01877   * @param  hqspi: QSPI handle.
01878   * @param  Timeout: Timeout for the QSPI memory access.
01879   * @retval None
01880   */
01881 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
01882 {
01883   hqspi->Timeout = Timeout;
01884 }
01885
01886 /** @brief Set QSPI Fifo threshold.
01887   * @param  hqspi: QSPI handle.
01888   * @param  Threshold: Threshold of the Fifo (value between 1 and 16).
01889   * @retval HAL status
01890   */
01891 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
01892 {
01893   HAL_StatusTypeDef status = HAL_OK;
01894
01895   /* Process locked */
01896   __HAL_LOCK(hqspi);
01897
01898   if(hqspi->State == HAL_QSPI_STATE_READY)
01899   {
01900     /* Synchronize init structure with new FIFO threshold value */
01901     hqspi->Init.FifoThreshold = Threshold;
01902
01903     /* Configure QSPI FIFO Threshold */
01904     MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
01905                ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES)));
01906   }
01907   else
01908   {
01909     status = HAL_BUSY;
01910   }
01911
01912   /* Process unlocked */
01913   __HAL_UNLOCK(hqspi);
01914
01915   /* Return function status */
01916   return status;
01917 }
01918
01919 /** @brief Get QSPI Fifo threshold.
01920   * @param  hqspi: QSPI handle.
01921   * @retval Fifo threshold (value between 1 and 16)
01922   */
01923 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
01924 {
01925   return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> POSITION_VAL(QUADSPI_CR_FTHRES)) + 1);
01926 }
01927
01928 /**
01929   * @}
01930   */
01931
01932 /**
01933   * @brief  DMA QSPI receive process complete callback.
01934   * @param  hmdma: MDMA handle
01935   * @retval None
01936   */
01937 static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma)
01938 {
01939   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
01940   hqspi->RxXferCount = 0;
01941
01942   /* Enable the QSPI transfer complete Interrupt */
01943   __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
01944 }
01945
01946 /**
01947   * @brief  DMA QSPI transmit process complete callback.
01948   * @param  hmdma: MDMA handle
01949   * @retval None
01950   */
01951 static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma)
01952 {
01953   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
01954   hqspi->TxXferCount = 0;
01955
01956   /* Enable the QSPI transfer complete Interrupt */
01957   __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
01958 }
01959
01960 /**
01961   * @brief  DMA QSPI communication error callback.
01962   * @param  hmdma: MDMA handle
01963   * @retval None
01964   */
01965 static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma)
01966 {
01967   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
01968
01969   hqspi->RxXferCount = 0;
01970   hqspi->TxXferCount = 0;
01971   hqspi->ErrorCode   |= HAL_QSPI_ERROR_DMA;
01972
01973   /* Disable the MDMA transfer by clearing the DMAEN bit in the QSPI CR register */
01974   CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
01975
01976   /* Abort the QSPI */
01977   HAL_QSPI_Abort_IT(hqspi);
01978 }
01979
01980 /**
01981   * @brief  MDMA QSPI abort complete callback.
01982   * @param  hmdma: MDMA handle
01983   * @retval None
01984   */
01985 static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma)
01986 {
01987   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
01988
01989   hqspi->RxXferCount = 0;
01990   hqspi->TxXferCount = 0;
01991
01992   if(hqspi->State == HAL_QSPI_STATE_ABORT)
01993   {
01994     /* MDMA Abort called by QSPI abort */
01995     /* Clear interrupt */
01996     __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
01997
01998     /* Enable the QSPI Transfer Complete Interrupt */
01999     __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
02000
02001     /* Configure QSPI: CR register with Abort request */
02002     SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
02003   }
02004   else
02005   {
02006     /* MDMA Abort called due to a transfer error interrupt */
02007     /* Change state of QSPI */
02008     hqspi->State = HAL_QSPI_STATE_READY;
02009
02010     /* Error callback */
02011     HAL_QSPI_ErrorCallback(hqspi);
02012   }
02013 }
02014 /**
02015   * @brief  Wait for a flag state until timeout.
02016   * @param  hqspi: QSPI handle
02017   * @param  Flag: Flag checked
02018   * @param  State: Value of the flag expected
02019   * @param  tickstart: Tick start value
02020   * @param  Timeout: Duration of the timeout
02021   * @retval HAL status
02022   */
02023 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
02024                                                         FlagStatus State, uint32_t tickstart, uint32_t Timeout)
02025 {
02026   /* Wait until flag is in expected state */
02027   while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
02028   {
02029     /* Check for the Timeout */
02030     if (Timeout != HAL_MAX_DELAY)
02031     {
02032       if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
02033       {
02034         hqspi->State     = HAL_QSPI_STATE_ERROR;
02035         hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
02036
02037         return HAL_ERROR;
02038       }
02039     }
02040   }
02041   return HAL_OK;
02042 }
02043
02044 /**
02045   * @brief  Configure the communication registers.
02046   * @param  hqspi: QSPI handle
02047   * @param  cmd: structure that contains the command configuration information
02048   * @param  FunctionalMode: functional mode to configured
02049   *           This parameter can be one of the following values:
02050   *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
02051   *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
02052   *            @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
02053   *            @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
02054   * @retval None
02055   */
02056 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
02057 {
02058   assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
02059
02060   if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
02061   {
02062     /* Configure QSPI: DLR register with the number of data to read or write */
02063     WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
02064   }
02065
02066   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
02067   {
02068     if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
02069     {
02070       /* Configure QSPI: ABR register with alternate bytes value */
02071       WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
02072
02073       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
02074       {
02075         /*---- Command with instruction, address and alternate bytes ----*/
02076         /* Configure QSPI: CCR register with all communications parameters */
02077         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02078                                          cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
02079                                          cmd->AlternateBytesSize | cmd->AlternateByteMode |
02080                                          cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
02081                                          cmd->Instruction | FunctionalMode));
02082
02083         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
02084         {
02085           /* Configure QSPI: AR register with address value */
02086           WRITE_REG(hqspi->Instance->AR, cmd->Address);
02087         }
02088       }
02089       else
02090       {
02091         /*---- Command with instruction and alternate bytes ----*/
02092         /* Configure QSPI: CCR register with all communications parameters */
02093         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02094                                          cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
02095                                          cmd->AlternateBytesSize | cmd->AlternateByteMode |
02096                                          cmd->AddressMode | cmd->InstructionMode |
02097                                          cmd->Instruction | FunctionalMode));
02098       }
02099     }
02100     else
02101     {
02102       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
02103       {
02104         /*---- Command with instruction and address ----*/
02105         /* Configure QSPI: CCR register with all communications parameters */
02106         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02107                                          cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
02108                                          cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
02109                                          cmd->InstructionMode | cmd->Instruction | FunctionalMode));
02110
02111         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
02112         {
02113           /* Configure QSPI: AR register with address value */
02114           WRITE_REG(hqspi->Instance->AR, cmd->Address);
02115         }
02116       }
02117       else
02118       {
02119         /*---- Command with only instruction ----*/
02120         /* Configure QSPI: CCR register with all communications parameters */
02121         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02122                                          cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
02123                                          cmd->AlternateByteMode | cmd->AddressMode |
02124                                          cmd->InstructionMode | cmd->Instruction | FunctionalMode));
02125       }
02126     }
02127   }
02128   else
02129   {
02130     if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
02131     {
02132       /* Configure QSPI: ABR register with alternate bytes value */
02133       WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
02134
02135       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
02136       {
02137         /*---- Command with address and alternate bytes ----*/
02138         /* Configure QSPI: CCR register with all communications parameters */
02139         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02140                                          cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
02141                                          cmd->AlternateBytesSize | cmd->AlternateByteMode |
02142                                          cmd->AddressSize | cmd->AddressMode |
02143                                          cmd->InstructionMode | FunctionalMode));
02144
02145         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
02146         {
02147           /* Configure QSPI: AR register with address value */
02148           WRITE_REG(hqspi->Instance->AR, cmd->Address);
02149         }
02150       }
02151       else
02152       {
02153         /*---- Command with only alternate bytes ----*/
02154         /* Configure QSPI: CCR register with all communications parameters */
02155         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02156                                          cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
02157                                          cmd->AlternateBytesSize | cmd->AlternateByteMode |
02158                                          cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
02159       }
02160     }
02161     else
02162     {
02163       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
02164       {
02165         /*---- Command with only address ----*/
02166         /* Configure QSPI: CCR register with all communications parameters */
02167         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02168                                          cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
02169                                          cmd->AlternateByteMode | cmd->AddressSize |
02170                                          cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
02171
02172         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
02173         {
02174           /* Configure QSPI: AR register with address value */
02175           WRITE_REG(hqspi->Instance->AR, cmd->Address);
02176         }
02177       }
02178       else
02179       {
02180         /*---- Command with only data phase ----*/
02181         if (cmd->DataMode != QSPI_DATA_NONE)
02182         {
02183           /* Configure QSPI: CCR register with all communications parameters */
02184           WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02185                                            cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
02186                                            cmd->AlternateByteMode | cmd->AddressMode |
02187                                            cmd->InstructionMode | FunctionalMode));
02188         }
02189       }
02190     }
02191   }
02192 }
02193
02194 /**
02195   * @}
02196   */
02197
02198 #endif /* HAL_QSPI_MODULE_ENABLED */
02199 /**
02200   * @}
02201   */
02202
02203 /**
02204   * @}
02205   */
02206
02207 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_qspi.h Source File

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stm32h7xx_hal_qspi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_qspi.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of QSPI HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_QSPI_H
00040 #define __STM32H7xx_HAL_QSPI_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048 #include "stm32h7xx_hal_mdma.h"
00049
00050 /** @addtogroup STM32H7xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup QSPI
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup QSPI_Exported_Types QSPI Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  QSPI Init structure definition
00065   */
00066
00067 typedef struct
00068 {
00069   uint32_t ClockPrescaler;     /* Specifies the prescaler factor for generating clock based on the AHB clock.
00070                                   This parameter can be a number between 0 and 255 */
00071
00072   uint32_t FifoThreshold;      /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
00073                                   This parameter can be a value between 1 and 32 */
00074
00075   uint32_t SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
00076                                   take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
00077                                   This parameter can be a value of @ref QSPI_SampleShifting */
00078
00079   uint32_t FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
00080                                   required to address the flash memory. The flash capacity can be up to 4GB
00081                                   (addressed using 32 bits) in indirect mode, but the addressable space in
00082                                   memory-mapped mode is limited to 256MB
00083                                   This parameter can be a number between 0 and 31 */
00084
00085   uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
00086                                   of clock cycles which the chip select must remain high between commands.
00087                                   This parameter can be a value of @ref QSPI_ChipSelectHighTime */
00088
00089   uint32_t ClockMode;          /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
00090                                   This parameter can be a value of @ref QSPI_ClockMode */
00091
00092   uint32_t FlashID;            /* Specifies the Flash which will be used,
00093                                   This parameter can be a value of @ref QSPI_Flash_Select */
00094
00095   uint32_t DualFlash;          /* Specifies the Dual Flash Mode State
00096                                   This parameter can be a value of @ref QSPI_DualFlash_Mode */
00097 }QSPI_InitTypeDef;
00098
00099 /**
00100   * @brief HAL QSPI State structures definition
00101   */
00102 typedef enum
00103 {
00104   HAL_QSPI_STATE_RESET             = 0x00U,    /*!< Peripheral not initialized                            */
00105   HAL_QSPI_STATE_READY             = 0x01U,    /*!< Peripheral initialized and ready for use              */
00106   HAL_QSPI_STATE_BUSY              = 0x02U,    /*!< Peripheral in indirect mode and busy                  */
00107   HAL_QSPI_STATE_BUSY_INDIRECT_TX  = 0x12U,    /*!< Peripheral in indirect mode with transmission ongoing */
00108   HAL_QSPI_STATE_BUSY_INDIRECT_RX  = 0x22U,    /*!< Peripheral in indirect mode with reception ongoing    */
00109   HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U,    /*!< Peripheral in auto polling mode ongoing               */
00110   HAL_QSPI_STATE_BUSY_MEM_MAPPED   = 0x82U,    /*!< Peripheral in memory mapped mode ongoing              */
00111   HAL_QSPI_STATE_ABORT             = 0x08U,    /*!< Peripheral with abort request ongoing                 */
00112   HAL_QSPI_STATE_ERROR             = 0x04U     /*!< Peripheral in error                                   */
00113 }HAL_QSPI_StateTypeDef;
00114
00115 /**
00116   * @brief  QSPI Handle Structure definition
00117   */
00118 typedef struct
00119 {
00120   QUADSPI_TypeDef            *Instance;        /* QSPI registers base address        */
00121   QSPI_InitTypeDef           Init;             /* QSPI communication parameters      */
00122   uint8_t                    *pTxBuffPtr;      /* Pointer to QSPI Tx transfer Buffer */
00123   __IO uint32_t              TxXferSize;       /* QSPI Tx Transfer size              */
00124   __IO uint32_t              TxXferCount;      /* QSPI Tx Transfer Counter           */
00125   uint8_t                    *pRxBuffPtr;      /* Pointer to QSPI Rx transfer Buffer */
00126   __IO uint32_t              RxXferSize;       /* QSPI Rx Transfer size              */
00127   __IO uint32_t              RxXferCount;      /* QSPI Rx Transfer Counter           */
00128   MDMA_HandleTypeDef         *hmdma;           /* QSPI Rx/Tx MDMA Handle parameters  */
00129   __IO HAL_LockTypeDef       Lock;             /* Locking object                     */
00130   __IO HAL_QSPI_StateTypeDef State;            /* QSPI communication state           */
00131   __IO uint32_t              ErrorCode;        /* QSPI Error code                    */
00132   uint32_t                   Timeout;          /* Timeout for the QSPI memory access */
00133 }QSPI_HandleTypeDef;
00134
00135 /**
00136   * @brief  QSPI Command structure definition
00137   */
00138 typedef struct
00139 {
00140   uint32_t Instruction;        /* Specifies the Instruction to be sent
00141                                   This parameter can be a value (8-bit) between 0x00 and 0xFF */
00142   uint32_t Address;            /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
00143                                   This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
00144   uint32_t AlternateBytes;     /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
00145                                   This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
00146   uint32_t AddressSize;        /* Specifies the Address Size
00147                                   This parameter can be a value of @ref QSPI_AddressSize */
00148   uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
00149                                   This parameter can be a value of @ref QSPI_AlternateBytesSize */
00150   uint32_t DummyCycles;        /* Specifies the Number of Dummy Cycles.
00151                                   This parameter can be a number between 0 and 31 */
00152   uint32_t InstructionMode;    /* Specifies the Instruction Mode
00153                                   This parameter can be a value of @ref QSPI_InstructionMode */
00154   uint32_t AddressMode;        /* Specifies the Address Mode
00155                                   This parameter can be a value of @ref QSPI_AddressMode */
00156   uint32_t AlternateByteMode;  /* Specifies the Alternate Bytes Mode
00157                                   This parameter can be a value of @ref QSPI_AlternateBytesMode */
00158   uint32_t DataMode;           /* Specifies the Data Mode (used for dummy cycles and data phases)
00159                                   This parameter can be a value of @ref QSPI_DataMode */
00160   uint32_t NbData;             /* Specifies the number of data to transfer.
00161                                   This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
00162                                   until end of memory)*/
00163   uint32_t DdrMode;            /* Specifies the double data rate mode for address, alternate byte and data phase
00164                                   This parameter can be a value of @ref QSPI_DdrMode */
00165   uint32_t DdrHoldHalfCycle;   /* Specifies the DDR hold half cycle. It delays the data output by one half of
00166                                   system clock in DDR mode.
00167                                   This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
00168   uint32_t SIOOMode;           /* Specifies the send instruction only once mode
00169                                   This parameter can be a value of @ref QSPI_SIOOMode */
00170 }QSPI_CommandTypeDef;
00171
00172 /**
00173   * @brief  QSPI Auto Polling mode configuration structure definition
00174   */
00175 typedef struct
00176 {
00177   uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.
00178                                   This parameter can be any value between 0 and 0xFFFFFFFF */
00179   uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received.
00180                                   This parameter can be any value between 0 and 0xFFFFFFFF */
00181   uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.
00182                                   This parameter can be any value between 0 and 0xFFFF */
00183   uint32_t StatusBytesSize;    /* Specifies the size of the status bytes received.
00184                                   This parameter can be any value between 1 and 4 */
00185   uint32_t MatchMode;          /* Specifies the method used for determining a match.
00186                                   This parameter can be a value of @ref QSPI_MatchMode */
00187   uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.
00188                                   This parameter can be a value of @ref QSPI_AutomaticStop */
00189 }QSPI_AutoPollingTypeDef;
00190
00191 /**
00192   * @brief  QSPI Memory Mapped mode configuration structure definition
00193   */
00194 typedef struct
00195 {
00196   uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
00197                                   This parameter can be any value between 0 and 0xFFFF */
00198   uint32_t TimeOutActivation;  /* Specifies if the time out counter is enabled to release the chip select.
00199                                   This parameter can be a value of @ref QSPI_TimeOutActivation */
00200 }QSPI_MemoryMappedTypeDef;
00201
00202 /**
00203   * @}
00204   */
00205
00206 /* Exported constants --------------------------------------------------------*/
00207 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants
00208   * @{
00209   */
00210
00211 /** @defgroup QSPI_ErrorCode QSPI Error Code
00212   * @{
00213   */
00214 #define HAL_QSPI_ERROR_NONE            ((uint32_t)0x00000000U) /*!< No error           */
00215 #define HAL_QSPI_ERROR_TIMEOUT         ((uint32_t)0x00000001U) /*!< Timeout error      */
00216 #define HAL_QSPI_ERROR_TRANSFER        ((uint32_t)0x00000002U) /*!< Transfer error     */
00217 #define HAL_QSPI_ERROR_DMA             ((uint32_t)0x00000004U) /*!< DMA transfer error */
00218 #define HAL_QSPI_ERROR_INVALID_PARAM   ((uint32_t)0x00000008U) /*!< Invalid parameters error */
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting
00224   * @{
00225   */
00226 #define QSPI_SAMPLE_SHIFTING_NONE      ((uint32_t)0x00000000U)        /*!<No clock cycle shift to sample data*/
00227 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
00233   * @{
00234   */
00235 #define QSPI_CS_HIGH_TIME_1_CYCLE      ((uint32_t)0x00000000U)                              /*!<nCS stay high for at least 1 clock cycle between commands*/
00236 #define QSPI_CS_HIGH_TIME_2_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0)                      /*!<nCS stay high for at least 2 clock cycles between commands*/
00237 #define QSPI_CS_HIGH_TIME_3_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_1)                      /*!<nCS stay high for at least 3 clock cycles between commands*/
00238 #define QSPI_CS_HIGH_TIME_4_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
00239 #define QSPI_CS_HIGH_TIME_5_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2)                      /*!<nCS stay high for at least 5 clock cycles between commands*/
00240 #define QSPI_CS_HIGH_TIME_6_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
00241 #define QSPI_CS_HIGH_TIME_7_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
00242 #define QSPI_CS_HIGH_TIME_8_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT)                        /*!<nCS stay high for at least 8 clock cycles between commands*/
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup QSPI_ClockMode QSPI Clock Mode
00248   * @{
00249   */
00250 #define QSPI_CLOCK_MODE_0              ((uint32_t)0x00000000)         /*!<Clk stays low while nCS is released*/
00251 #define QSPI_CLOCK_MODE_3              ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
00252 /**
00253   * @}
00254   */
00255
00256 /** @defgroup QSPI_Flash_Select QSPI Flash Select
00257   * @{
00258   */
00259 #define QSPI_FLASH_ID_1                ((uint32_t)0x00000000)      /*!<FLASH 1 selected*/
00260 #define QSPI_FLASH_ID_2                ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
00261 /**
00262   * @}
00263   */
00264
00265   /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
00266   * @{
00267   */
00268 #define QSPI_DUALFLASH_ENABLE          ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
00269 #define QSPI_DUALFLASH_DISABLE         ((uint32_t)0x00000000)     /*!<Dual-flash mode disabled*/
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup QSPI_AddressSize QSPI Address Size
00275   * @{
00276   */
00277 #define QSPI_ADDRESS_8_BITS            ((uint32_t)0x00000000)           /*!<8-bit address*/
00278 #define QSPI_ADDRESS_16_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
00279 #define QSPI_ADDRESS_24_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
00280 #define QSPI_ADDRESS_32_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE)   /*!<32-bit address*/
00281 /**
00282   * @}
00283   */
00284
00285 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
00286   * @{
00287   */
00288 #define QSPI_ALTERNATE_BYTES_8_BITS    ((uint32_t)0x00000000)           /*!<8-bit alternate bytes*/
00289 #define QSPI_ALTERNATE_BYTES_16_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
00290 #define QSPI_ALTERNATE_BYTES_24_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
00291 #define QSPI_ALTERNATE_BYTES_32_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE)   /*!<32-bit alternate bytes*/
00292 /**
00293   * @}
00294   */
00295
00296 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode
00297 * @{
00298 */
00299 #define QSPI_INSTRUCTION_NONE          ((uint32_t)0x00000000)          /*!<No instruction*/
00300 #define QSPI_INSTRUCTION_1_LINE        ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
00301 #define QSPI_INSTRUCTION_2_LINES       ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
00302 #define QSPI_INSTRUCTION_4_LINES       ((uint32_t)QUADSPI_CCR_IMODE)   /*!<Instruction on four lines*/
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup QSPI_AddressMode QSPI Address Mode
00308 * @{
00309 */
00310 #define QSPI_ADDRESS_NONE              ((uint32_t)0x00000000)           /*!<No address*/
00311 #define QSPI_ADDRESS_1_LINE            ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
00312 #define QSPI_ADDRESS_2_LINES           ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
00313 #define QSPI_ADDRESS_4_LINES           ((uint32_t)QUADSPI_CCR_ADMODE)   /*!<Address on four lines*/
00314 /**
00315   * @}
00316   */
00317
00318 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
00319 * @{
00320 */
00321 #define QSPI_ALTERNATE_BYTES_NONE      ((uint32_t)0x00000000)           /*!<No alternate bytes*/
00322 #define QSPI_ALTERNATE_BYTES_1_LINE    ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
00323 #define QSPI_ALTERNATE_BYTES_2_LINES   ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
00324 #define QSPI_ALTERNATE_BYTES_4_LINES   ((uint32_t)QUADSPI_CCR_ABMODE)   /*!<Alternate bytes on four lines*/
00325 /**
00326   * @}
00327   */
00328
00329 /** @defgroup QSPI_DataMode QSPI Data Mode
00330   * @{
00331   */
00332 #define QSPI_DATA_NONE                 ((uint32_t)0X00000000)           /*!<No data*/
00333 #define QSPI_DATA_1_LINE               ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
00334 #define QSPI_DATA_2_LINES              ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
00335 #define QSPI_DATA_4_LINES              ((uint32_t)QUADSPI_CCR_DMODE)   /*!<Data on four lines*/
00336 /**
00337   * @}
00338   */
00339
00340 /** @defgroup QSPI_DdrMode QSPI DDR Mode
00341   * @{
00342   */
00343 #define QSPI_DDR_MODE_DISABLE          ((uint32_t)0x00000000)       /*!<Double data rate mode disabled*/
00344 #define QSPI_DDR_MODE_ENABLE           ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
00350   * @{
00351   */
00352 #define QSPI_DDR_HHC_ANALOG_DELAY      ((uint32_t)0x00000000)       /*!<Delay the data output using analog delay in DDR mode*/
00353 #define QSPI_DDR_HHC_HALF_CLK_DELAY    ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
00354 /**
00355   * @}
00356   */
00357
00358 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
00359   * @{
00360   */
00361 #define QSPI_SIOO_INST_EVERY_CMD       ((uint32_t)0x00000000)       /*!<Send instruction on every transaction*/
00362 #define QSPI_SIOO_INST_ONLY_FIRST_CMD  ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
00363 /**
00364   * @}
00365   */
00366
00367 /** @defgroup QSPI_MatchMode QSPI Match Mode
00368   * @{
00369   */
00370 #define QSPI_MATCH_MODE_AND            ((uint32_t)0x00000000)     /*!<AND match mode between unmasked bits*/
00371 #define QSPI_MATCH_MODE_OR             ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
00372 /**
00373   * @}
00374   */
00375
00376 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
00377   * @{
00378   */
00379 #define QSPI_AUTOMATIC_STOP_DISABLE    ((uint32_t)0x00000000)      /*!<AutoPolling stops only with abort or QSPI disabling*/
00380 #define QSPI_AUTOMATIC_STOP_ENABLE     ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
00386   * @{
00387   */
00388 #define QSPI_TIMEOUT_COUNTER_DISABLE   ((uint32_t)0x00000000)      /*!<Timeout counter disabled, nCS remains active*/
00389 #define QSPI_TIMEOUT_COUNTER_ENABLE    ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
00390 /**
00391   * @}
00392   */
00393
00394 /** @defgroup QSPI_Flags QSPI Flags
00395   * @{
00396   */
00397 #define QSPI_FLAG_BUSY                 QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
00398 #define QSPI_FLAG_TO                   QUADSPI_SR_TOF  /*!<Timeout flag: timeout occurs in memory-mapped mode*/
00399 #define QSPI_FLAG_SM                   QUADSPI_SR_SMF  /*!<Status match flag: received data matches in autopolling mode*/
00400 #define QSPI_FLAG_FT                   QUADSPI_SR_FTF  /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
00401 #define QSPI_FLAG_TC                   QUADSPI_SR_TCF  /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
00402 #define QSPI_FLAG_TE                   QUADSPI_SR_TEF  /*!<Transfer error flag: invalid address is being accessed*/
00403 /**
00404   * @}
00405   */
00406
00407 /** @defgroup QSPI_Interrupts QSPI Interrupts
00408   * @{
00409   */
00410 #define QSPI_IT_TO                     QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
00411 #define QSPI_IT_SM                     QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
00412 #define QSPI_IT_FT                     QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
00413 #define QSPI_IT_TC                     QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
00414 #define QSPI_IT_TE                     QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
00415 /**
00416   * @}
00417   */
00418
00419 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition
00420   * @brief QSPI Timeout definition
00421   * @{
00422   */
00423 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
00424 /**
00425   * @}
00426   */
00427
00428 /**
00429   * @}
00430   */
00431
00432 /* Exported macros -----------------------------------------------------------*/
00433 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros
00434   * @{
00435   */
00436 /** @brief Reset QSPI handle state.
00437   * @param  __HANDLE__: QSPI handle.
00438   * @retval None
00439   */
00440 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
00441
00442 /** @brief  Enable the QSPI peripheral.
00443   * @param  __HANDLE__: specifies the QSPI Handle.
00444   * @retval None
00445   */
00446 #define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
00447
00448 /** @brief  Disable the QSPI peripheral.
00449   * @param  __HANDLE__: specifies the QSPI Handle.
00450   * @retval None
00451   */
00452 #define __HAL_QSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
00453
00454 /** @brief  Enable the specified QSPI interrupt.
00455   * @param  __HANDLE__: specifies the QSPI Handle.
00456   * @param  __INTERRUPT__: specifies the QSPI interrupt source to enable.
00457   *          This parameter can be one of the following values:
00458   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
00459   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00460   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00461   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00462   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00463   * @retval None
00464   */
00465 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
00466
00467
00468 /** @brief  Disable the specified QSPI interrupt.
00469   * @param  __HANDLE__: specifies the QSPI Handle.
00470   * @param  __INTERRUPT__: specifies the QSPI interrupt source to disable.
00471   *          This parameter can be one of the following values:
00472   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
00473   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00474   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00475   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00476   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00477   * @retval None
00478   */
00479 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
00480
00481 /** @brief  Check whether the specified QSPI interrupt source is enabled or not.
00482   * @param  __HANDLE__: specifies the QSPI Handle.
00483   * @param  __INTERRUPT__: specifies the QSPI interrupt source to check.
00484   *          This parameter can be one of the following values:
00485   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
00486   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00487   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00488   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00489   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00490   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00491   */
00492 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
00493
00494 /**
00495   * @brief  Check whether the selected QSPI flag is set or not.
00496   * @param  __HANDLE__: specifies the QSPI Handle.
00497   * @param  __FLAG__: specifies the QSPI flag to check.
00498   *          This parameter can be one of the following values:
00499   *            @arg QSPI_FLAG_BUSY: QSPI Busy flag
00500   *            @arg QSPI_FLAG_TO:   QSPI Timeout flag
00501   *            @arg QSPI_FLAG_SM:   QSPI Status match flag
00502   *            @arg QSPI_FLAG_FT:   QSPI FIFO threshold flag
00503   *            @arg QSPI_FLAG_TC:   QSPI Transfer complete flag
00504   *            @arg QSPI_FLAG_TE:   QSPI Transfer error flag
00505   * @retval None
00506   */
00507 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__)           (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
00508
00509 /** @brief  Clears the specified QSPI's flag status.
00510   * @param  __HANDLE__: specifies the QSPI Handle.
00511   * @param  __FLAG__: specifies the QSPI clear register flag that needs to be set
00512   *          This parameter can be one of the following values:
00513   *            @arg QSPI_FLAG_TO: QSPI Timeout flag
00514   *            @arg QSPI_FLAG_SM: QSPI Status match flag
00515   *            @arg QSPI_FLAG_TC: QSPI Transfer complete flag
00516   *            @arg QSPI_FLAG_TE: QSPI Transfer error flag
00517   * @retval None
00518   */
00519 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
00520 /**
00521   * @}
00522   */
00523
00524 /* Exported functions --------------------------------------------------------*/
00525 /** @addtogroup QSPI_Exported_Functions
00526   * @{
00527   */
00528 /* Initialization/de-initialization functions  ********************************/
00529 HAL_StatusTypeDef     HAL_QSPI_Init     (QSPI_HandleTypeDef *hqspi);
00530 HAL_StatusTypeDef     HAL_QSPI_DeInit   (QSPI_HandleTypeDef *hqspi);
00531 void                  HAL_QSPI_MspInit  (QSPI_HandleTypeDef *hqspi);
00532 void                  HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
00533
00534 /* IO operation functions *****************************************************/
00535 /* QSPI IRQ handler method */
00536 void                  HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
00537
00538 /* QSPI indirect mode */
00539 HAL_StatusTypeDef     HAL_QSPI_Command      (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
00540 HAL_StatusTypeDef     HAL_QSPI_Transmit     (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
00541 HAL_StatusTypeDef     HAL_QSPI_Receive      (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
00542 HAL_StatusTypeDef     HAL_QSPI_Command_IT   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
00543 HAL_StatusTypeDef     HAL_QSPI_Transmit_IT  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00544 HAL_StatusTypeDef     HAL_QSPI_Receive_IT   (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00545 HAL_StatusTypeDef     HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00546 HAL_StatusTypeDef     HAL_QSPI_Receive_DMA  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00547
00548 /* QSPI status flag polling mode */
00549 HAL_StatusTypeDef     HAL_QSPI_AutoPolling   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
00550 HAL_StatusTypeDef     HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
00551
00552 /* QSPI memory-mapped mode */
00553 HAL_StatusTypeDef     HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
00554
00555 /* Callback functions in non-blocking modes ***********************************/
00556 void                  HAL_QSPI_ErrorCallback        (QSPI_HandleTypeDef *hqspi);
00557 void                  HAL_QSPI_AbortCpltCallback    (QSPI_HandleTypeDef *hqspi);
00558 void                  HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
00559
00560 /* QSPI indirect mode */
00561 void                  HAL_QSPI_CmdCpltCallback      (QSPI_HandleTypeDef *hqspi);
00562 void                  HAL_QSPI_RxCpltCallback       (QSPI_HandleTypeDef *hqspi);
00563 void                  HAL_QSPI_TxCpltCallback       (QSPI_HandleTypeDef *hqspi);
00564 void                  HAL_QSPI_RxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
00565 void                  HAL_QSPI_TxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
00566
00567 /* QSPI status flag polling mode */
00568 void                  HAL_QSPI_StatusMatchCallback  (QSPI_HandleTypeDef *hqspi);
00569
00570 /* QSPI memory-mapped mode */
00571 void                  HAL_QSPI_TimeOutCallback      (QSPI_HandleTypeDef *hqspi);
00572
00573 /* Peripheral Control and State functions  ************************************/
00574 HAL_QSPI_StateTypeDef HAL_QSPI_GetState        (QSPI_HandleTypeDef *hqspi);
00575 uint32_t              HAL_QSPI_GetError        (QSPI_HandleTypeDef *hqspi);
00576 HAL_StatusTypeDef     HAL_QSPI_Abort           (QSPI_HandleTypeDef *hqspi);
00577 HAL_StatusTypeDef     HAL_QSPI_Abort_IT        (QSPI_HandleTypeDef *hqspi);
00578 void                  HAL_QSPI_SetTimeout      (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
00579 HAL_StatusTypeDef     HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
00580 uint32_t              HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
00581 /**
00582   * @}
00583   */
00584 /* End of exported functions -------------------------------------------------*/
00585
00586 /* Private macros ------------------------------------------------------------*/
00587 /** @defgroup QSPI_Private_Macros QSPI Private Macros
00588 * @{
00589 */
00590 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
00591
00592 #define IS_QSPI_FIFO_THRESHOLD(THR)        (((THR) > 0) && ((THR) <= 32))
00593
00594 #define IS_QSPI_SSHIFT(SSHIFT)             (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
00595                                             ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
00596
00597 #define IS_QSPI_FLASH_SIZE(FSIZE)          (((FSIZE) <= 31))
00598
00599 #define IS_QSPI_CS_HIGH_TIME(CSHTIME)      (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
00600                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
00601                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
00602                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
00603                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
00604                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
00605                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
00606                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
00607
00608 #define IS_QSPI_CLOCK_MODE(CLKMODE)        (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
00609                                             ((CLKMODE) == QSPI_CLOCK_MODE_3))
00610
00611
00612 #define IS_QSPI_FLASH_ID(FLASH)            (((FLASH) == QSPI_FLASH_ID_1) || \
00613                                             ((FLASH) == QSPI_FLASH_ID_2))
00614
00615 #define IS_QSPI_DUAL_FLASH_MODE(MODE)      (((MODE) == QSPI_DUALFLASH_ENABLE) || \
00616                                             ((MODE) == QSPI_DUALFLASH_DISABLE))
00617
00618 #define IS_QSPI_INSTRUCTION(INSTRUCTION)   ((INSTRUCTION) <= 0xFF)
00619
00620 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)    (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \
00621                                             ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
00622                                             ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
00623                                             ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
00624
00625 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \
00626                                             ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
00627                                             ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
00628                                             ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
00629
00630 #define IS_QSPI_DUMMY_CYCLES(DCY)          ((DCY) <= 31)
00631
00632 #define IS_QSPI_INSTRUCTION_MODE(MODE)     (((MODE) == QSPI_INSTRUCTION_NONE)    || \
00633                                             ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \
00634                                             ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
00635                                             ((MODE) == QSPI_INSTRUCTION_4_LINES))
00636
00637 #define IS_QSPI_ADDRESS_MODE(MODE)         (((MODE) == QSPI_ADDRESS_NONE)    || \
00638                                             ((MODE) == QSPI_ADDRESS_1_LINE)  || \
00639                                             ((MODE) == QSPI_ADDRESS_2_LINES) || \
00640                                             ((MODE) == QSPI_ADDRESS_4_LINES))
00641
00642 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \
00643                                             ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \
00644                                             ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
00645                                             ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
00646
00647 #define IS_QSPI_DATA_MODE(MODE)            (((MODE) == QSPI_DATA_NONE)    || \
00648                                             ((MODE) == QSPI_DATA_1_LINE)  || \
00649                                             ((MODE) == QSPI_DATA_2_LINES) || \
00650                                             ((MODE) == QSPI_DATA_4_LINES))
00651
00652 #define IS_QSPI_DDR_MODE(DDR_MODE)         (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
00653                                             ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
00654
00655 #define IS_QSPI_DDR_HHC(DDR_HHC)           (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
00656                                             ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
00657
00658 #define IS_QSPI_SIOO_MODE(SIOO_MODE)       (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
00659                                             ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
00660
00661 #define IS_QSPI_INTERVAL(INTERVAL)         ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
00662
00663 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE)    (((SIZE) >= 1) && ((SIZE) <= 4))
00664
00665 #define IS_QSPI_MATCH_MODE(MODE)           (((MODE) == QSPI_MATCH_MODE_AND) || \
00666                                             ((MODE) == QSPI_MATCH_MODE_OR))
00667
00668 #define IS_QSPI_AUTOMATIC_STOP(APMS)       (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
00669                                             ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
00670
00671 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN)   (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
00672                                             ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
00673
00674 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD)     ((PERIOD) <= 0xFFFF)
00675 /**
00676 * @}
00677 */
00678 /* End of private macros -----------------------------------------------------*/
00679
00680 /**
00681   * @}
00682   */
00683
00684 /**
00685   * @}
00686   */
00687
00688 #ifdef __cplusplus
00689 }
00690 #endif
00691
00692 #endif /* __STM32H7xx_HAL_QSPI_H */
00693
00694 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_rcc.c Source File

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stm32h7xx_hal_rcc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rcc.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   RCC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Reset and Clock Control (RCC) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + Peripheral Control functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                       ##### RCC specific features #####
00016   ==============================================================================
00017     [..]
00018       After reset the device is running from Internal High Speed oscillator
00019       (HSI 64MHz) with Flash 0 wait state,and all peripherals are off except
00020       internal SRAM, Flash, JTAG and PWR
00021       (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses;
00022           all peripherals mapped on these buses are running at HSI speed.
00023       (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
00024       (+) All GPIOs are in analogue mode , except the JTAG pins which
00025           are assigned to be used for debug purpose.
00026
00027     [..]
00028       Once the device started from reset, the user application has to:
00029       (+) Configure the clock source to be used to drive the System clock
00030           (if the application needs higher frequency/performance)
00031       (+) Configure the System clock frequency and Flash settings
00032       (+) Configure the AHB and APB buses pre-scalers
00033       (+) Enable the clock for the peripheral(s) to be used
00034       (+) Configure the clock kernel source(s) for peripherals which clocks are not
00035           derived from the System clock through :RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R
00036           and RCC_D3CCIPR registers
00037
00038                       ##### RCC Limitations #####
00039   ==============================================================================
00040     [..]
00041       A delay between an RCC peripheral clock enable and the effective peripheral
00042       enabling should be taken into account in order to manage the peripheral read/write
00043       from/to registers.
00044       (+) This delay depends on the peripheral mapping.
00045       (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
00046           after the clock enable bit is set on the hardware register
00047       (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
00048           after the clock enable bit is set on the hardware register
00049
00050     [..]
00051       Implemented Workaround:
00052       (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
00053           inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
00054
00055   @endverbatim
00056   ******************************************************************************
00057   * @attention
00058   *
00059   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00060   *
00061   * Redistribution and use in source and binary forms, with or without modification,
00062   * are permitted provided that the following conditions are met:
00063   *   1. Redistributions of source code must retain the above copyright notice,
00064   *      this list of conditions and the following disclaimer.
00065   *   2. Redistributions in binary form must reproduce the above copyright notice,
00066   *      this list of conditions and the following disclaimer in the documentation
00067   *      and/or other materials provided with the distribution.
00068   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00069   *      may be used to endorse or promote products derived from this software
00070   *      without specific prior written permission.
00071   *
00072   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00073   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00074   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00075   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00076   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00077   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00078   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00079   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00080   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00081   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00082   *
00083   ******************************************************************************
00084   */
00085
00086 /* Includes ------------------------------------------------------------------*/
00087 #include "stm32h7xx_hal.h"
00088
00089 /** @addtogroup STM32H7xx_HAL_Driver
00090   * @{
00091   */
00092
00093 /** @defgroup RCC  RCC
00094   * @brief RCC HAL module driver
00095   * @{
00096   */
00097
00098 #ifdef HAL_RCC_MODULE_ENABLED
00099
00100 /* Private typedef -----------------------------------------------------------*/
00101 /* Private define ------------------------------------------------------------*/
00102 /* Private macro -------------------------------------------------------------*/
00103 /** @defgroup RCC_Private_Macros RCC Private Macros
00104   * @{
00105   */
00106 #define __MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()
00107 #define MCO1_GPIO_PORT        GPIOA
00108 #define MCO1_PIN              GPIO_PIN_8
00109
00110 #define __MCO2_CLK_ENABLE()   __HAL_RCC_GPIOC_CLK_ENABLE()
00111 #define MCO2_GPIO_PORT         GPIOC
00112 #define MCO2_PIN               GPIO_PIN_9
00113
00114 /**
00115   * @}
00116   */
00117 /* Private variables ---------------------------------------------------------*/
00118 /** @defgroup RCC_Private_Variables RCC Private Variables
00119   * @{
00120   */
00121
00122 /**
00123   * @}
00124   */
00125 /* Private function prototypes -----------------------------------------------*/
00126 /* Exported functions --------------------------------------------------------*/
00127
00128 /** @defgroup RCC_Exported_Functions RCC Exported Functions
00129   * @{
00130   */
00131
00132 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
00133  *  @brief    Initialization and Configuration functions
00134  *
00135 @verbatim
00136  ===============================================================================
00137            ##### Initialization and de-initialization functions #####
00138  ===============================================================================
00139     [..]
00140       This section provides functions allowing to configure the internal/external oscillators
00141       (HSE, HSI, LSE,CSI, LSI,HSI48, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB3, AHB1
00142        AHB2,AHB4,APB3, APB1L, APB1H, APB2, and APB4).
00143
00144     [..] Internal/external clock and PLL configuration
00145          (#) HSI (high-speed internal), 64 MHz factory-trimmed RC used directly or through
00146              the PLL as System clock source.
00147          (#) CSI is a low-power RC oscillator which can be used directly as system clock, peripheral
00148              clock, or PLL input.But even with frequency calibration, is less accurate than an
00149              external crystal oscillator or ceramic resonator.
00150          (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
00151              clock source.
00152
00153          (#) HSE (high-speed external), 4 to 48 MHz crystal oscillator used directly or
00154              through the PLL as System clock source. Can be used also as RTC clock source.
00155
00156          (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
00157
00158          (#) PLL , The RCC features three independent PLLs (clocked by HSI , HSE or CSI),
00159              featuring three different output clocks and able  to work either in integer or Fractional mode.
00160            (++) A main PLL, PLL1, which is generally used to provide clocks to the CPU
00161                 and to some peripherals.
00162            (++) Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for peripherals.
00163
00164
00165          (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
00166             (HSE used directly or through PLL as System clock source), the System clock
00167              is automatically switched to HSI and an interrupt is generated if enabled.
00168              The interrupt is linked to the Cortex-M NMI (Non-Mask-able Interrupt)
00169              exception vector.
00170
00171          (#) MCO1 (micro controller clock output), used to output HSI, LSE, HSE, PLL1(PLL1_Q)
00172              or HSI48 clock (through a configurable pre-scaler) on PA8 pin.
00173
00174          (#) MCO2 (micro controller clock output), used to output HSE, PLL2(PLL2_P), SYSCLK,
00175              LSI, CSI, or PLL1(PLL1_P) clock (through a configurable pre-scaler) on PC9 pin.
00176
00177     [..] System, AHB and APB buses clocks configuration
00178          (#) Several clock sources can be used to drive the System clock (SYSCLK): CSI,HSI,
00179              HSE and PLL.
00180              The AHB clock (HCLK) is derived from System core clock through configurable
00181              pre-scaler and used to clock the CPU, memory and peripherals mapped
00182              on AHB and APB bus of the 3 Domains (D1, D2, D3) through configurable pre-scalers
00183              and used to clock the peripherals mapped on these buses. You can use
00184              "HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency.
00185
00186          -@- All the peripheral clocks are derived from the System clock (SYSCLK) except those
00187              with dual clock domain where kernel source clock could be selected through
00188              RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R and RCC_D3CCIPR registers.
00189 @endverbatim
00190   * @{
00191   */
00192
00193 /**
00194   * @brief  Resets the RCC clock configuration to the default reset state.
00195   * @note   The default reset state of the clock configuration is given below:
00196   *            - HSI ON and used as system clock source
00197   *            - HSE, PLL1, PLL2 and PLL3 OFF
00198   *            - AHB, APB Bus pre-scaler set to 1.
00199   *            - CSS, MCO1 and MCO2 OFF
00200   *            - All interrupts disabled
00201   * @note   This function doesn't modify the configuration of the
00202   *            - Peripheral clocks
00203   *            - LSI, LSE and RTC clocks
00204   * @retval None
00205   */
00206 void HAL_RCC_DeInit(void)
00207 {
00208   /* Set HSION bit */
00209   SET_BIT(RCC->CR, RCC_CR_HSION);
00210
00211   /* Reset CFGR register */
00212   CLEAR_REG(RCC->CFGR);
00213
00214   /* Reset CSION , CSIKERON, HSEON, HSI48ON, HSECSSON,HSIDIV, PLL1ON, PLL2ON, PLL3ON bits */
00215   CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | RCC_CR_CSIKERON |  RCC_CR_HSI48ON  \
00216   |RCC_CR_CSSHSEON | RCC_CR_PLL1ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
00217
00218   /* Reset D1CFGR register */
00219   CLEAR_REG(RCC->D1CFGR);
00220
00221   /* Reset D2CFGR register */
00222   CLEAR_REG(RCC->D2CFGR);
00223
00224   /* Reset D3CFGR register */
00225   CLEAR_REG(RCC->D3CFGR);
00226
00227   /* Reset PLLCKSELR register */
00228   CLEAR_REG(RCC->PLLCKSELR);
00229
00230   /* Reset PLLCFGR register */
00231   CLEAR_REG(RCC->PLLCFGR);
00232
00233   /* Reset PLL1DIVR register */
00234   CLEAR_REG(RCC->PLL1DIVR);
00235
00236   /* Reset PLL1FRACR register */
00237   CLEAR_REG(RCC->PLL1FRACR);
00238
00239   /* Reset PLL2DIVR register */
00240   CLEAR_REG(RCC->PLL2DIVR);
00241
00242   /* Reset PLL2FRACR register */
00243   CLEAR_REG(RCC->PLL2FRACR);
00244
00245   /* Reset PLL3DIVR register */
00246   CLEAR_REG(RCC->PLL3DIVR);
00247
00248   /* Reset PLL3FRACR register */
00249   CLEAR_REG(RCC->PLL3FRACR);
00250
00251   /* Reset HSEBYP bit */
00252   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
00253
00254   /* Disable all interrupts */
00255   CLEAR_REG(RCC->CICR);
00256 }
00257
00258 /**
00259   * @brief  Initializes the RCC Oscillators according to the specified parameters in the
00260   *         RCC_OscInitTypeDef.
00261   * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
00262   *         contains the configuration information for the RCC Oscillators.
00263   * @note   The PLL is not disabled when used as system clock.
00264   * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
00265   *         supported by this function. User should request a transition to LSE Off
00266   *         first and then LSE On or LSE Bypass.
00267   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
00268   *         supported by this function. User should request a transition to HSE Off
00269   *         first and then HSE On or HSE Bypass.
00270   * @retval HAL status
00271   */
00272 __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
00273 {
00274   uint32_t tickstart = 0;
00275
00276   /* Check the parameters */
00277   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
00278   /*------------------------------- HSE Configuration ------------------------*/
00279   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
00280   {
00281     /* Check the parameters */
00282     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
00283     /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
00284     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL1) && ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
00285     {
00286       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
00287       {
00288         return HAL_ERROR;
00289       }
00290     }
00291     else
00292     {
00293       /* Set the new HSE configuration ---------------------------------------*/
00294       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
00295
00296       /* Check the HSE State */
00297       if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
00298       {
00299         /* Get Start Tick*/
00300         tickstart = HAL_GetTick();
00301
00302         /* Wait till HSE is ready */
00303         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
00304         {
00305           if((int32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
00306           {
00307             return HAL_TIMEOUT;
00308           }
00309         }
00310       }
00311       else
00312       {
00313         /* Get Start Tick*/
00314         tickstart = HAL_GetTick();
00315
00316         /* Wait till HSE is bypassed or disabled */
00317         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
00318         {
00319           if((int32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
00320           {
00321             return HAL_TIMEOUT;
00322           }
00323         }
00324       }
00325     }
00326   }
00327   /*----------------------------- HSI Configuration --------------------------*/
00328   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
00329   {
00330     /* Check the parameters */
00331     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
00332     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
00333
00334     /* When the HSI is used as system clock it will not disabled */
00335     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL1) && ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
00336     {
00337       /* When HSI is used as system clock it will not disabled */
00338       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
00339       {
00340         return HAL_ERROR;
00341       }
00342       /* Otherwise, just the calibration is allowed */
00343       else
00344       {
00345       /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */
00346         __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
00347
00348         /* Get Start Tick*/
00349         tickstart = HAL_GetTick();
00350
00351         /* Wait till HSI is ready */
00352         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
00353         {
00354           if((int32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
00355           {
00356             return HAL_TIMEOUT;
00357           }
00358         }
00359         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
00360         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00361       }
00362     }
00363
00364     else
00365     {
00366       /* Check the HSI State */
00367       if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
00368       {
00369      /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */
00370         __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
00371
00372         /* Get Start Tick*/
00373         tickstart = HAL_GetTick();
00374
00375         /* Wait till HSI is ready */
00376         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
00377         {
00378           if((int32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
00379           {
00380             return HAL_TIMEOUT;
00381           }
00382         }
00383
00384         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
00385         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00386       }
00387       else
00388       {
00389         /* Disable the Internal High Speed oscillator (HSI). */
00390         __HAL_RCC_HSI_DISABLE();
00391
00392         /* Get Start Tick*/
00393         tickstart = HAL_GetTick();
00394
00395         /* Wait till HSI is ready */
00396         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
00397         {
00398           if((int32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
00399           {
00400             return HAL_TIMEOUT;
00401           }
00402         }
00403       }
00404     }
00405   }
00406   /*----------------------------- CSI Configuration --------------------------*/
00407   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
00408   {
00409     /* Check the parameters */
00410     assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState));
00411     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue));
00412
00413     /* When the CSI is used as system clock it will not disabled */
00414     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_CSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL1) && ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
00415     {
00416       /* When CSI is used as system clock it will not disabled */
00417       if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != RESET) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
00418       {
00419         return HAL_ERROR;
00420       }
00421       /* Otherwise, just the calibration is allowed */
00422       else
00423       {
00424         /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
00425         __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
00426       }
00427     }
00428     else
00429     {
00430       /* Check the CSI State */
00431       if((RCC_OscInitStruct->CSIState)!= RCC_CSI_OFF)
00432       {
00433         /* Enable the Internal High Speed oscillator (CSI). */
00434         __HAL_RCC_CSI_ENABLE();
00435
00436         /* Get Start Tick*/
00437         tickstart = HAL_GetTick();
00438
00439         /* Wait till CSI is ready */
00440         while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == RESET)
00441         {
00442           if((int32_t) (HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE)
00443           {
00444             return HAL_TIMEOUT;
00445           }
00446         }
00447
00448         /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
00449         __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
00450       }
00451       else
00452       {
00453         /* Disable the Internal High Speed oscillator (CSI). */
00454         __HAL_RCC_CSI_DISABLE();
00455
00456         /* Get Start Tick*/
00457         tickstart = HAL_GetTick();
00458
00459         /* Wait till CSI is ready */
00460         while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != RESET)
00461         {
00462           if((int32_t) (HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE)
00463           {
00464             return HAL_TIMEOUT;
00465           }
00466         }
00467       }
00468     }
00469   }
00470   /*------------------------------ LSI Configuration -------------------------*/
00471   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
00472   {
00473     /* Check the parameters */
00474     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
00475
00476     /* Check the LSI State */
00477     if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
00478     {
00479       /* Enable the Internal Low Speed oscillator (LSI). */
00480       __HAL_RCC_LSI_ENABLE();
00481
00482       /* Get Start Tick*/
00483       tickstart = HAL_GetTick();
00484
00485       /* Wait till LSI is ready */
00486       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
00487       {
00488         if((int32_t) (HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
00489         {
00490           return HAL_TIMEOUT;
00491         }
00492       }
00493     }
00494     else
00495     {
00496       /* Disable the Internal Low Speed oscillator (LSI). */
00497       __HAL_RCC_LSI_DISABLE();
00498
00499       /* Get Start Tick*/
00500       tickstart = HAL_GetTick();
00501
00502       /* Wait till LSI is ready */
00503       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
00504       {
00505         if((int32_t) (HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
00506         {
00507           return HAL_TIMEOUT;
00508         }
00509       }
00510     }
00511   }
00512
00513   /*------------------------------ HSI48 Configuration -------------------------*/
00514   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
00515   {
00516     /* Check the parameters */
00517     assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
00518
00519     /* Check the HSI48 State */
00520     if((RCC_OscInitStruct->HSI48State)!= RCC_HSI48_OFF)
00521     {
00522       /* Enable the Internal Low Speed oscillator (HSI48). */
00523       __HAL_RCC_HSI48_ENABLE();
00524
00525       /* Get time-out */
00526       tickstart = HAL_GetTick();
00527
00528       /* Wait till HSI48 is ready */
00529       while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
00530       {
00531         if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)
00532         {
00533           return HAL_TIMEOUT;
00534         }
00535       }
00536     }
00537     else
00538     {
00539       /* Disable the Internal Low Speed oscillator (HSI48). */
00540       __HAL_RCC_HSI48_DISABLE();
00541
00542       /* Get time-out */
00543       tickstart = HAL_GetTick();
00544
00545       /* Wait till HSI48 is ready */
00546       while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET)
00547       {
00548         if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)
00549         {
00550           return HAL_TIMEOUT;
00551         }
00552       }
00553     }
00554   }
00555   /*------------------------------ LSE Configuration -------------------------*/
00556   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
00557   {
00558     /* Check the parameters */
00559     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
00560
00561     /* Enable write access to Backup domain */
00562     PWR->CR1 |= PWR_CR1_DBP;
00563
00564     /* Wait for Backup domain Write protection disable */
00565     tickstart = HAL_GetTick();
00566
00567     while((PWR->CR1 & PWR_CR1_DBP) == RESET)
00568     {
00569       if((int32_t) (HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
00570       {
00571         return HAL_TIMEOUT;
00572       }
00573     }
00574
00575     /* Set the new LSE configuration -----------------------------------------*/
00576     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
00577     /* Check the LSE State */
00578     if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
00579     {
00580       /* Get Start Tick*/
00581       tickstart = HAL_GetTick();
00582
00583       /* Wait till LSE is ready */
00584       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
00585       {
00586         if((int32_t) (HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
00587         {
00588           return HAL_TIMEOUT;
00589         }
00590       }
00591     }
00592     else
00593     {
00594       /* Get Start Tick*/
00595       tickstart = HAL_GetTick();
00596
00597       /* Wait till LSE is ready */
00598       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
00599       {
00600         if((int32_t) (HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
00601         {
00602           return HAL_TIMEOUT;
00603         }
00604       }
00605     }
00606   }
00607   /*-------------------------------- PLL Configuration -----------------------*/
00608   /* Check the parameters */
00609   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
00610   if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
00611   {
00612     /* Check if the PLL is used as system clock or not */
00613     if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
00614     {
00615       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
00616       {
00617         /* Check the parameters */
00618         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
00619         assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
00620         assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
00621         assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
00622         assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
00623         assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLR));
00624
00625         /* Disable the main PLL. */
00626         __HAL_RCC_PLL_DISABLE();
00627
00628         /* Get Start Tick*/
00629         tickstart = HAL_GetTick();
00630
00631         /* Wait till PLL is ready */
00632         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
00633         {
00634           if((int32_t) (HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00635           {
00636             return HAL_TIMEOUT;
00637           }
00638         }
00639
00640         /* Configure the main PLL clock source, multiplication and division factors. */
00641         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
00642                              RCC_OscInitStruct->PLL.PLLM,
00643                              RCC_OscInitStruct->PLL.PLLN,
00644                              RCC_OscInitStruct->PLL.PLLP,
00645                              RCC_OscInitStruct->PLL.PLLQ,
00646                              RCC_OscInitStruct->PLL.PLLR);
00647
00648          /* Configure PLL  PLL1FRACN */
00649          __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
00650
00651         /* Select PLL1 input reference frequency range: VCI */
00652         __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ;
00653
00654         /* Select PLL1 output frequency range : VCO */
00655         __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ;
00656
00657         /* Enable PLL System Clock output. */
00658          __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
00659
00660         /* Enable PLL1Q Clock output. */
00661          __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00662
00663         /* Enable PLL1R  Clock output. */
00664          __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
00665
00666         /* Enable PLL1FRACN . */
00667          __HAL_RCC_PLLFRACN_ENABLE();
00668
00669         /* Enable the main PLL. */
00670         __HAL_RCC_PLL_ENABLE();
00671
00672         /* Get Start Tick*/
00673         tickstart = HAL_GetTick();
00674
00675         /* Wait till PLL is ready */
00676         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
00677         {
00678           if((int32_t) (HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00679           {
00680             return HAL_TIMEOUT;
00681           }
00682         }
00683       }
00684       else
00685       {
00686         /* Disable the main PLL. */
00687         __HAL_RCC_PLL_DISABLE();
00688
00689         /* Get Start Tick*/
00690         tickstart = HAL_GetTick();
00691
00692         /* Wait till PLL is ready */
00693         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
00694         {
00695           if((int32_t) (HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00696           {
00697             return HAL_TIMEOUT;
00698           }
00699         }
00700       }
00701     }
00702     else
00703     {
00704       return HAL_ERROR;
00705     }
00706   }
00707   return HAL_OK;
00708 }
00709
00710 /**
00711   * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified
00712   *         parameters in the RCC_ClkInitStruct.
00713   * @param  RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
00714   *         contains the configuration information for the RCC peripheral.
00715   * @param  FLatency: FLASH Latency, this parameter depend on device selected
00716   *
00717   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
00718   *         and updated by HAL_InitTick() function called within this function
00719   *
00720   * @note   The HSI is used (enabled by hardware) as system clock source after
00721   *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case
00722   *         of failure of the HSE used directly or indirectly as system clock
00723   *         (if the Clock Security System CSS is enabled).
00724   *
00725   * @note   A switch from one clock source to another occurs only if the target
00726   *         clock source is ready (clock stable after start-up delay or PLL locked).
00727   *         If a clock source which is not yet ready is selected, the switch will
00728   *         occur when the clock source will be ready.
00729   *         You can use HAL_RCC_GetClockConfig() function to know which clock is
00730   *         currently used as system clock source.
00731   * @note   Depending on the device voltage range, the software has to set correctly
00732   *         D1CPRE[3:0] bits to ensure that  Domain1 core clock not exceed the maximum allowed frequency
00733   *         (for more details refer to section above "Initialization/de-initialization functions")
00734   * @retval None
00735   */
00736 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
00737 {
00738   uint32_t tickstart = 0;
00739
00740   /* Check the parameters */
00741   assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
00742   assert_param(IS_FLASH_LATENCY(FLatency));
00743
00744   /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
00745     must be correctly programmed according to the frequency of the CPU clock
00746     (HCLK) and the supply voltage of the device. */
00747
00748   /* Increasing the CPU frequency */
00749   if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
00750   {
00751     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
00752     __HAL_FLASH_SET_LATENCY(FLatency);
00753
00754     /* Check that the new number of wait states is taken into account to access the Flash
00755     memory by reading the FLASH_ACR register */
00756     if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
00757     {
00758       return HAL_ERROR;
00759     }
00760
00761   }
00762    /*-------------------------- HCLK Configuration --------------------------*/
00763     if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
00764     {
00765       assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
00766       MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
00767     }
00768
00769     /*------------------------- SYSCLK Configuration -------------------------*/
00770     if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
00771     {
00772       assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));
00773       assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
00774       MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
00775       /* HSE is selected as System Clock Source */
00776       if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
00777       {
00778         /* Check the HSE ready flag */
00779         if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
00780         {
00781           return HAL_ERROR;
00782         }
00783       }
00784       /* PLL is selected as System Clock Source */
00785       else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
00786       {
00787         /* Check the PLL ready flag */
00788         if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
00789         {
00790           return HAL_ERROR;
00791         }
00792       }
00793       /* CSI is selected as System Clock Source */
00794       else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
00795       {
00796         /* Check the PLL ready flag */
00797         if(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == RESET)
00798         {
00799           return HAL_ERROR;
00800         }
00801       }
00802       /* HSI is selected as System Clock Source */
00803       else
00804       {
00805         /* Check the HSI ready flag */
00806         if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
00807         {
00808           return HAL_ERROR;
00809         }
00810       }
00811       MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
00812
00813       /* Get Start Tick*/
00814       tickstart = HAL_GetTick();
00815
00816       if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
00817       {
00818         while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
00819         {
00820           if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
00821           {
00822             return HAL_TIMEOUT;
00823           }
00824         }
00825       }
00826       else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
00827       {
00828         while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
00829         {
00830           if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
00831           {
00832             return HAL_TIMEOUT;
00833           }
00834         }
00835       }
00836       else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
00837       {
00838         while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_CSI)
00839         {
00840           if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
00841           {
00842             return HAL_TIMEOUT;
00843           }
00844         }
00845       }
00846       else
00847       {
00848         while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
00849         {
00850           if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
00851           {
00852             return HAL_TIMEOUT;
00853           }
00854         }
00855       }
00856     }
00857
00858   /* Decreasing the number of wait states because of lower CPU frequency */
00859   if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
00860   {
00861     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
00862     __HAL_FLASH_SET_LATENCY(FLatency);
00863
00864     /* Check that the new number of wait states is taken into account to access the Flash
00865     memory by reading the FLASH_ACR register */
00866     if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
00867     {
00868       return HAL_ERROR;
00869     }
00870  }
00871
00872   /*-------------------------- D1PCLK1 Configuration ---------------------------*/
00873   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
00874   {
00875     assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
00876     MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
00877   }
00878
00879   /*-------------------------- PCLK1 Configuration ---------------------------*/
00880   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
00881   {
00882     assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
00883     MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
00884   }
00885
00886   /*-------------------------- PCLK2 Configuration ---------------------------*/
00887   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
00888   {
00889     assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
00890     MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
00891   }
00892
00893
00894   /*-------------------------- D3PCLK1 Configuration ---------------------------*/
00895   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
00896   {
00897     assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
00898     MODIFY_REG(RCC->D3CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB4CLKDivider) );
00899   }
00900
00901   /* Update the SystemCoreClock global variable */
00902   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> POSITION_VAL(RCC_D1CFGR_D1CPRE_0)];
00903
00904   /* Configure the source of time base considering new system clocks settings*/
00905   HAL_InitTick (TICK_INT_PRIORITY);
00906
00907   return HAL_OK;
00908 }
00909
00910 /**
00911   * @}
00912   */
00913
00914 /** @defgroup RCC_Group2 Peripheral Control functions
00915  *  @brief   RCC clocks control functions
00916  *
00917 @verbatim
00918  ===============================================================================
00919                       ##### Peripheral Control functions #####
00920  ===============================================================================
00921     [..]
00922     This subsection provides a set of functions allowing to control the RCC Clocks
00923     frequencies.
00924
00925 @endverbatim
00926   * @{
00927   */
00928
00929 /**
00930   * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
00931   * @note   PA8/PC9 should be configured in alternate function mode.
00932   * @param  RCC_MCOx: specifies the output direction for the clock source.
00933   *          This parameter can be one of the following values:
00934   *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
00935   *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
00936   * @param  RCC_MCOSource: specifies the clock source to output.
00937   *          This parameter can be one of the following values:
00938   *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
00939   *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
00940   *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
00941   *            @arg RCC_MCO1SOURCE_PLL1QCLK:  PLL1Q clock selected as MCO1 source
00942   *            @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source
00943   *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
00944   *            @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source
00945   *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
00946   *            @arg RCC_MCO2SOURCE_PLLCLK:  PLL1P clock selected as MCO2 source
00947   *            @arg RCC_MCO2SOURCE_CSICLK:  CSI clock selected as MCO2 source
00948   *            @arg RCC_MCO2SOURCE_LSICLK:  LSI clock selected as MCO2 source
00949   * @param  RCC_MCODiv: specifies the MCOx pre-scaler.
00950   *          This parameter can be one of the following values:
00951   *            @arg RCC_MCODIV_1 up to RCC_MCODIV_15  : divider applied to MCOx clock
00952   * @retval None
00953   */
00954 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
00955 {
00956   GPIO_InitTypeDef GPIO_InitStruct;
00957   /* Check the parameters */
00958   assert_param(IS_RCC_MCO(RCC_MCOx));
00959   assert_param(IS_RCC_MCODIV(RCC_MCODiv));
00960   /* RCC_MCO1 */
00961   if(RCC_MCOx == RCC_MCO1)
00962   {
00963     assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
00964
00965     /* MCO1 Clock Enable */
00966     __MCO1_CLK_ENABLE();
00967
00968     /* Configure the MCO1 pin in alternate function mode */
00969     GPIO_InitStruct.Pin = MCO1_PIN;
00970     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
00971     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
00972     GPIO_InitStruct.Pull = GPIO_NOPULL;
00973     GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
00974     HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
00975
00976     /* Mask MCO1 and MCO1PRE[3:0] bits then Select MCO1 clock source and pre-scaler */
00977     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
00978   }
00979   else
00980   {
00981     assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
00982
00983     /* MCO2 Clock Enable */
00984     __MCO2_CLK_ENABLE();
00985
00986     /* Configure the MCO2 pin in alternate function mode */
00987     GPIO_InitStruct.Pin = MCO2_PIN;
00988     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
00989     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
00990     GPIO_InitStruct.Pull = GPIO_NOPULL;
00991     GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
00992     HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
00993
00994     /* Mask MCO2 and MCO2PRE[3:0] bits then Select MCO2 clock source and pre-scaler */
00995     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 7)));
00996   }
00997 }
00998
00999 /**
01000   * @brief  Enables the Clock Security System.
01001   * @note   If a failure is detected on the HSE oscillator clock, this oscillator
01002   *         is automatically disabled and an interrupt is generated to inform the
01003   *         software about the failure (Clock Security System Interrupt, CSSI),
01004   *         allowing the MCU to perform rescue operations. The CSSI is linked to
01005   *         the Cortex-M NMI (Non-Mask-able Interrupt) exception vector.
01006   * @retval None
01007   */
01008 void HAL_RCC_EnableCSS(void)
01009 {
01010   SET_BIT(RCC->CR, RCC_CR_CSSHSEON) ;
01011 }
01012
01013 /**
01014   * @brief  Returns the SYSCLK frequency
01015   *
01016   * @note   The system frequency computed by this function is not the real
01017   *         frequency in the chip. It is calculated based on the predefined
01018   *         constant and the selected clock source:
01019   * @note     If SYSCLK source is CSI, function returns values based on CSI_VALUE(*)
01020   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
01021   * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
01022   * @note     If SYSCLK source is PLL, function returns values based on CSI_VALUE(*),
01023   *           HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
01024   * @note     (*) CSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
01025   *               4 MHz) but the real value may vary depending on the variations
01026   *               in voltage and temperature.
01027   * @note     (**) HSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
01028   *               64 MHz) but the real value may vary depending on the variations
01029   *               in voltage and temperature.
01030   * @note     (***) HSE_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
01031   *                25 MHz), user has to ensure that HSE_VALUE is same as the real
01032   *                frequency of the crystal used. Otherwise, this function may
01033   *                have wrong result.
01034   *
01035   * @note   The result of this function could be not correct when using fractional
01036   *         value for HSE crystal.
01037   *
01038   * @note   This function can be used by the user application to compute the
01039   *         baud rate for the communication peripherals or configure other parameters.
01040   *
01041   * @note   Each time SYSCLK changes, this function must be called to update the
01042   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
01043   *
01044   *
01045   * @retval SYSCLK frequency
01046   */
01047 uint32_t HAL_RCC_GetSysClockFreq(void)
01048 {
01049  uint32_t pllp = 1, pllsource = 0, pllm = 1 ,pllfracen =0 , hsivalue = 0;
01050  float fracn1=0, pllvco = 0;
01051  uint32_t sysclockfreq = 0;
01052   /* Get SYSCLK source -------------------------------------------------------*/
01053
01054   switch (RCC->CFGR & RCC_CFGR_SWS)
01055   {
01056   case 0x00:  /* HSI used as system clock source */
01057
01058    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
01059       {
01060         sysclockfreq = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
01061       }
01062       else
01063       {
01064         sysclockfreq = (uint32_t) HSI_VALUE;
01065       }
01066
01067     break;
01068
01069   case 0x08:  /* CSI used as system clock  source */
01070     sysclockfreq = CSI_VALUE;
01071     break;
01072
01073   case 0x10:  /* HSE used as system clock  source */
01074     sysclockfreq = HSE_VALUE;
01075     break;
01076
01077   case 0x18:  /* PLL1 used as system clock  source */
01078
01079     /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
01080     SYSCLK = PLL_VCO / PLLR
01081     */
01082     pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
01083     pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
01084     pllfracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
01085     fracn1 = (pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
01086
01087     switch (pllsource)
01088     {
01089     case 0x00:  /* HSI used as PLL clock source */
01090
01091      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
01092       {
01093         hsivalue= (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
01094         pllvco = ( hsivalue / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x1FFF) +1 );
01095       }
01096       else
01097       {
01098         pllvco = (HSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x1FFF) +1 );
01099       }
01100       break;
01101
01102     case 0x01:  /* CSI used as PLL clock source */
01103       pllvco = (CSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x1FFF) +1 );
01104       break;
01105
01106     case 0x02:  /* HSE used as PLL clock source */
01107       pllvco = (HSE_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x1FFF) +1 );
01108       break;
01109
01110     default:
01111       pllvco = (CSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x1FFF) +1 );
01112       break;
01113     }
01114     pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1 ) ;
01115     sysclockfreq =  (uint32_t)(pllvco/pllp);
01116     break;
01117
01118   default:
01119     sysclockfreq = CSI_VALUE;
01120     break;
01121   }
01122
01123   return sysclockfreq;
01124 }
01125
01126
01127 /**
01128   * @brief  Returns the HCLK frequency
01129   * @note   Each time HCLK changes, this function must be called to update the
01130   *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
01131   *
01132   * @note   The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency
01133   *         and updated within this function
01134   * @retval HCLK frequency
01135   */
01136 uint32_t HAL_RCC_GetHCLKFreq(void)
01137 {
01138   SystemD2Clock = (HAL_RCCEx_GetD1SysClockFreq() >> D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> POSITION_VAL(RCC_D1CFGR_HPRE_0)]);
01139   return SystemD2Clock;
01140 }
01141
01142
01143 /**
01144   * @brief  Returns the PCLK1 frequency
01145   * @note   Each time PCLK1 changes, this function must be called to update the
01146   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
01147   * @retval PCLK1 frequency
01148   */
01149 uint32_t HAL_RCC_GetPCLK1Freq(void)
01150 {
01151   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
01152   return (HAL_RCC_GetHCLKFreq() >> D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)>> POSITION_VAL(RCC_D2CFGR_D2PPRE1_0)]);
01153 }
01154
01155
01156 /**
01157   * @brief  Returns the PCLK2 frequency
01158   * @note   Each time PCLK2 changes, this function must be called to update the
01159   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
01160   * @retval PCLK1 frequency
01161   */
01162 uint32_t HAL_RCC_GetPCLK2Freq(void)
01163 {
01164   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
01165   return (HAL_RCC_GetHCLKFreq() >> D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)>> POSITION_VAL(RCC_D2CFGR_D2PPRE2_0)]);
01166 }
01167
01168 /**
01169   * @brief  Configures the RCC_OscInitStruct according to the internal
01170   * RCC configuration registers.
01171   * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
01172   * will be configured.
01173   * @retval None
01174   */
01175 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
01176 {
01177   /* Set all possible values for the Oscillator type parameter ---------------*/
01178   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_CSI | \
01179                                       RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI| RCC_OSCILLATORTYPE_HSI48;
01180
01181   /* Get the HSE configuration -----------------------------------------------*/
01182   if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
01183   {
01184     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
01185   }
01186   else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
01187   {
01188     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
01189   }
01190   else
01191   {
01192     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
01193   }
01194
01195    /* Get the CSI configuration -----------------------------------------------*/
01196   if((RCC->CR &RCC_CR_CSION) == RCC_CR_CSION)
01197   {
01198     RCC_OscInitStruct->CSIState = RCC_CSI_ON;
01199   }
01200   else
01201   {
01202     RCC_OscInitStruct->CSIState = RCC_CSI_OFF;
01203   }
01204
01205   RCC_OscInitStruct->CSICalibrationValue = (uint32_t)((RCC->ICSCR &RCC_ICSCR_CSITRIM) >> POSITION_VAL(RCC_ICSCR_CSITRIM));
01206
01207   /* Get the HSI configuration -----------------------------------------------*/
01208   if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
01209   {
01210     RCC_OscInitStruct->HSIState = RCC_HSI_ON;
01211   }
01212   else
01213   {
01214     RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
01215   }
01216
01217   RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR &RCC_ICSCR_HSITRIM) >> POSITION_VAL(RCC_ICSCR_HSITRIM));
01218
01219   /* Get the LSE configuration -----------------------------------------------*/
01220   if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
01221   {
01222     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
01223   }
01224   else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
01225   {
01226     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
01227   }
01228   else
01229   {
01230     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
01231   }
01232
01233   /* Get the LSI configuration -----------------------------------------------*/
01234   if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
01235   {
01236     RCC_OscInitStruct->LSIState = RCC_LSI_ON;
01237   }
01238   else
01239   {
01240     RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
01241   }
01242
01243   /* Get the HSI48 configuration ---------------------------------------------*/
01244   if((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON)
01245   {
01246     RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
01247   }
01248   else
01249   {
01250     RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
01251   }
01252
01253   /* Get the PLL configuration -----------------------------------------------*/
01254   if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
01255   {
01256     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
01257   }
01258   else
01259   {
01260     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
01261   }
01262   RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
01263   RCC_OscInitStruct->PLL.PLLM = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> POSITION_VAL(RCC_PLLCKSELR_DIVM1));
01264   RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) >> POSITION_VAL(RCC_PLL1DIVR_N1))+ 1;
01265   RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> POSITION_VAL(RCC_PLL1DIVR_R1))+ 1;
01266   RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> POSITION_VAL(RCC_PLL1DIVR_P1))+ 1;
01267   RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> POSITION_VAL(RCC_PLL1DIVR_Q1))+ 1;
01268   RCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1RGE) >> POSITION_VAL(RCC_PLLCFGR_PLL1RGE_1));
01269   RCC_OscInitStruct->PLL.PLLVCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1VCOSEL) >> POSITION_VAL(RCC_PLLCFGR_PLL1VCOSEL));
01270 }
01271
01272 /**
01273   * @brief  Configures the RCC_ClkInitStruct according to the internal
01274   * RCC configuration registers.
01275   * @param  RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
01276   * will be configured.
01277   * @param  pFLatency: Pointer on the Flash Latency.
01278   * @retval None
01279   */
01280 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
01281 {
01282   /* Set all possible values for the Clock type parameter --------------------*/
01283   RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 |
01284                                  RCC_CLOCKTYPE_PCLK2 |  RCC_CLOCKTYPE_D3PCLK1  ;
01285
01286   /* Get the SYSCLK configuration --------------------------------------------*/
01287   RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
01288
01289   /* Get the SYSCLK configuration ----------------------------------------------*/
01290   RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE);
01291
01292   /* Get the D1HCLK configuration ----------------------------------------------*/
01293   RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE);
01294
01295   /* Get the APB3 configuration ----------------------------------------------*/
01296   RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE);
01297
01298   /* Get the APB1 configuration ----------------------------------------------*/
01299   RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1);
01300
01301   /* Get the APB2 configuration ----------------------------------------------*/
01302   RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2);
01303
01304   /* Get the APB4 configuration ----------------------------------------------*/
01305   RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE);
01306
01307
01308   /* Get the Flash Wait State (Latency) configuration ------------------------*/
01309   *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
01310 }
01311
01312 /**
01313   * @brief This function handles the RCC CSS interrupt request.
01314   * @note This API should be called under the NMI_Handler().
01315   * @retval None
01316   */
01317 void HAL_RCC_NMI_IRQHandler(void)
01318 {
01319   /* Check RCC CSSF flag  */
01320   if(__HAL_RCC_GET_IT(RCC_IT_CSS))
01321   {
01322     /* RCC Clock Security System interrupt user callback */
01323     HAL_RCC_CCSCallback();
01324
01325     /* Clear RCC CSS pending bit */
01326     __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
01327   }
01328 }
01329
01330 /**
01331   * @brief  RCC Clock Security System interrupt callback
01332   * @retval none
01333   */
01334 __weak void HAL_RCC_CCSCallback(void)
01335 {
01336   /* NOTE : This function Should not be modified, when the callback is needed,
01337             the HAL_RCC_CCSCallback could be implemented in the user file
01338    */
01339 }
01340
01341 /**
01342   * @}
01343   */
01344
01345 /**
01346   * @}
01347   */
01348
01349 #endif /* HAL_RCC_MODULE_ENABLED */
01350 /**
01351   * @}
01352   */
01353
01354 /**
01355   * @}
01356   */
01357
01358 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_rcc.h Source File

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stm32h7xx_hal_rcc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rcc.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of RCC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_RCC_H
00040 #define __STM32H7xx_HAL_RCC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup RCC
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup RCC_Exported_Types RCC Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  RCC PLL configuration structure definition
00065   */
00066 typedef struct
00067 {
00068   uint32_t PLLState;   /*!< The new state of the PLL.
00069                             This parameter can be a value of @ref RCC_PLL_Config                      */
00070
00071   uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
00072                             This parameter must be a value of @ref RCC_PLL_Clock_Source               */
00073
00074   uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
00075                             This parameter must be a number between Min_Data = 1 and Max_Data = 63    */
00076
00077   uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
00078                             This parameter must be a number between Min_Data = 4 and Max_Data = 512   */
00079
00080   uint32_t PLLP;       /*!< PLLP: Division factor for system clock.
00081                             This parameter must be a number between Min_Data = 2 and Max_Data = 128
00082                           odd division factors are not allowed                                        */
00083
00084   uint32_t PLLQ;       /*!< PLLQ: Division factor for peripheral clocks.
00085                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
00086
00087   uint32_t PLLR;       /*!< PLLR: Division factor for peripheral clocks.
00088                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
00089   uint32_t PLLRGE;     /*!<PLLRGE: PLL1 clock Input range
00090                          This parameter must be a value of @ref RCC_PLL1_VCI_Range                    */
00091   uint32_t PLLVCOSEL;  /*!<PLLVCOSEL: PLL1 clock Output range
00092                          This parameter must be a value of @ref RCC_PLL1_VCO_Range                    */
00093
00094   uint32_t PLLFRACN;   /*!<PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for
00095                         PLL1 VCO It should be a value between 0 and 8191                              */
00096
00097 }RCC_PLLInitTypeDef;
00098
00099
00100 /**
00101   * @brief  RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition
00102   */
00103 typedef struct
00104 {
00105   uint32_t OscillatorType;       /*!< The oscillators to be configured.
00106                                       This parameter can be a value of @ref RCC_Oscillator_Type                   */
00107
00108   uint32_t HSEState;             /*!< The new state of the HSE.
00109                                       This parameter can be a value of @ref RCC_HSE_Config                        */
00110
00111   uint32_t LSEState;             /*!< The new state of the LSE.
00112                                       This parameter can be a value of @ref RCC_LSE_Config                        */
00113
00114   uint32_t HSIState;             /*!< The new state of the HSI.
00115                                       This parameter can be a value of @ref RCC_HSI_Config                        */
00116
00117   uint32_t HSICalibrationValue;  /*!< The calibration trimming value.
00118                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F */
00119
00120   uint32_t LSIState;             /*!< The new state of the LSI.
00121                                       This parameter can be a value of @ref RCC_LSI_Config                        */
00122
00123  uint32_t HSI48State;            /*!< The new state of the HSI48.
00124                                       This parameter can be a value of @ref RCC_HSI48_Config                      */
00125
00126   uint32_t CSIState;             /*!< The new state of the CSI.
00127                                       This parameter can be a value of @ref RCC_CSI_Config */
00128
00129   uint32_t CSICalibrationValue;  /*!< The calibration trimming value.
00130                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
00131
00132   RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */
00133
00134 }RCC_OscInitTypeDef;
00135
00136 /**
00137   * @brief  RCC System, AHB and APB busses clock configuration structure definition
00138   */
00139 typedef struct
00140 {
00141   uint32_t ClockType;             /*!< The clock to be configured.
00142                                        This parameter can be a value of @ref RCC_System_Clock_Type                          */
00143
00144   uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
00145                                        This parameter can be a value of @ref RCC_System_Clock_Source                        */
00146
00147   uint32_t SYSCLKDivider;         /*!< The system clock  divider. This parameter can be
00148                                        a value of @ref RCC_SYS_Clock_Source                                                 */
00149
00150   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
00151                                        This parameter can be a value of @ref RCC_HCLK_Clock_Source                          */
00152
00153   uint32_t APB3CLKDivider;        /*!< The APB3 clock (D1PCLK1) divider. This clock is derived from the AHB clock (HCLK).
00154                                        This parameter can be a value of @ref RCC_APB3_Clock_Source                        */
00155
00156   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
00157                                        This parameter can be a value of @ref RCC_APB1_Clock_Source                        */
00158   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
00159                                        This parameter can be a value of @ref RCC_APB2_Clock_Source                        */
00160   uint32_t APB4CLKDivider;      /*!< The APB4 clock (D3PCLK1) divider. This clock is derived from the AHB clock (HCLK).
00161                                        This parameter can be a value of @ref RCC_APB4_Clock_Source                        */
00162 }RCC_ClkInitTypeDef;
00163
00164 /**
00165   * @}
00166   */
00167
00168 /* Exported constants --------------------------------------------------------*/
00169
00170 /** @defgroup RCC_Exported_Constants RCC Exported Constants
00171   * @{
00172   */
00173
00174 /** @defgroup RCC_Oscillator_Type  RCC Oscillator Type
00175   * @{
00176   */
00177 #define RCC_OSCILLATORTYPE_NONE        ((uint32_t)0x00000000)
00178 #define RCC_OSCILLATORTYPE_HSE         ((uint32_t)0x00000001)
00179 #define RCC_OSCILLATORTYPE_HSI         ((uint32_t)0x00000002)
00180 #define RCC_OSCILLATORTYPE_LSE         ((uint32_t)0x00000004)
00181 #define RCC_OSCILLATORTYPE_LSI         ((uint32_t)0x00000008)
00182 #define RCC_OSCILLATORTYPE_CSI         ((uint32_t)0x00000010)
00183 #define RCC_OSCILLATORTYPE_HSI48       ((uint32_t)0x00000020)
00184
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup RCC_HSE_Config  RCC HSE Config
00190   * @{
00191   */
00192 #define RCC_HSE_OFF                    ((uint32_t)0x00000000)
00193 #define RCC_HSE_ON                     RCC_CR_HSEON
00194 #define RCC_HSE_BYPASS                 ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @defgroup RCC_LSE_Config  RCC LSE Config
00201   * @{
00202   */
00203 #define RCC_LSE_OFF                    ((uint32_t)0x00000000)
00204 #define RCC_LSE_ON                     RCC_BDCR_LSEON
00205 #define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
00206
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup RCC_HSI_Config  RCC HSI Config
00212   * @{
00213   */
00214 #define RCC_HSI_OFF                      ((uint32_t)0x00000000)           /*!< HSI clock deactivation */
00215 #define RCC_HSI_ON                       RCC_CR_HSION                     /*!< HSI clock activation */
00216
00217 #define RCC_HSI_DIV1                     (RCC_CR_HSIDIV_1 | RCC_CR_HSION) /*!< HSI_DIV1 clock activation */
00218 #define RCC_HSI_DIV2                     (RCC_CR_HSIDIV_2 | RCC_CR_HSION) /*!< HSI_DIV2 clock activation */
00219 #define RCC_HSI_DIV4                     (RCC_CR_HSIDIV_4 | RCC_CR_HSION) /*!< HSI_DIV4 clock activation */
00220 #define RCC_HSI_DIV8                     (RCC_CR_HSIDIV | RCC_CR_HSION)   /*!< HSI_DIV8 clock activation */
00221
00222
00223
00224 #define RCC_HSICALIBRATION_DEFAULT     ((uint32_t)0x20U)         /* Default HSI calibration trimming value */
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup RCC_HSI48_Config  RCC HSI48 Config
00230   * @{
00231   */
00232 #define RCC_HSI48_OFF                      ((uint8_t)0x00)
00233 #define RCC_HSI48_ON                       ((uint8_t)0x01)
00234
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup RCC_LSI_Config  RCC LSI Config
00240   * @{
00241   */
00242 #define RCC_LSI_OFF                    ((uint32_t)0x00000000)
00243 #define RCC_LSI_ON                     RCC_CSR_LSION
00244
00245 /**
00246   * @}
00247   */
00248
00249 /** @defgroup RCC_CSI_Config  RCC CSI Config
00250   * @{
00251   */
00252 #define RCC_CSI_OFF                    ((uint32_t)0x00000000)
00253 #define RCC_CSI_ON                     RCC_CR_CSION
00254
00255 #define RCC_CSICALIBRATION_DEFAULT     ((uint32_t)0x10U)         /* Default CSI calibration trimming value */
00256
00257 /**
00258   * @}
00259   */
00260
00261 /** @defgroup RCC_PLL_Config  RCC PLL Config
00262   * @{
00263   */
00264 #define RCC_PLL_NONE                   ((uint32_t)0x00000000)
00265 #define RCC_PLL_OFF                    ((uint32_t)0x00000001)
00266 #define RCC_PLL_ON                     ((uint32_t)0x00000002)
00267
00268 /**
00269   * @}
00270   */
00271
00272
00273 /** @defgroup RCC_PLL_Clock_Source  RCC PLL Clock Source
00274   * @{
00275   */
00276 #define RCC_PLLSOURCE_HSI              ((uint32_t)0x00000000)
00277 #define RCC_PLLSOURCE_CSI              ((uint32_t)0x00000001)
00278 #define RCC_PLLSOURCE_HSE              ((uint32_t)0x00000002)
00279 #define RCC_PLLSOURCE_NONE             ((uint32_t)0x00000003)
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup RCC_PLL_Clock_Output  RCC PLL Clock Output
00285   * @{
00286   */
00287 #define RCC_PLL1_DIVP                RCC_PLLCFGR_DIVP1EN
00288 #define RCC_PLL1_DIVQ                RCC_PLLCFGR_DIVQ1EN
00289 #define RCC_PLL1_DIVR                RCC_PLLCFGR_DIVR1EN
00290
00291 /**
00292   * @}
00293   */
00294
00295
00296
00297 /** @defgroup RCC_PLL1_VCI_Range  RCC PLL1 VCI Range
00298   * @{
00299   */
00300 #define RCC_PLL1VCIRANGE_0                RCC_PLLCFGR_PLL1RGE_0
00301 #define RCC_PLL1VCIRANGE_1                RCC_PLLCFGR_PLL1RGE_1
00302 #define RCC_PLL1VCIRANGE_2                RCC_PLLCFGR_PLL1RGE_2
00303 #define RCC_PLL1VCIRANGE_3                RCC_PLLCFGR_PLL1RGE_3
00304
00305
00306 /**
00307   * @}
00308   */
00309
00310
00311 /** @defgroup RCC_PLL1_VCO_Range  RCC PLL1 VCO Range
00312   * @{
00313   */
00314 #define RCC_PLL1VCOWIDE                 ((uint32_t)0x00000000)
00315 #define RCC_PLL1VCOMEDIUM               RCC_PLLCFGR_PLL1VCOSEL
00316
00317 /**
00318   * @}
00319   */
00320
00321
00322 /** @defgroup RCC_System_Clock_Type  RCC System Clock Type
00323   * @{
00324   */
00325 #define RCC_CLOCKTYPE_SYSCLK           ((uint32_t)0x00000001)
00326 #define RCC_CLOCKTYPE_HCLK             ((uint32_t)0x00000002)
00327 #define RCC_CLOCKTYPE_D1PCLK1          ((uint32_t)0x00000004)
00328 #define RCC_CLOCKTYPE_PCLK1            ((uint32_t)0x00000008)
00329 #define RCC_CLOCKTYPE_PCLK2            ((uint32_t)0x00000010)
00330 #define RCC_CLOCKTYPE_D3PCLK1          ((uint32_t)0x00000020)
00331
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup RCC_System_Clock_Source  RCC System Clock Source
00337   * @{
00338   */
00339 #define RCC_SYSCLKSOURCE_CSI           RCC_CFGR_SW_CSI
00340 #define RCC_SYSCLKSOURCE_HSI           RCC_CFGR_SW_HSI
00341 #define RCC_SYSCLKSOURCE_HSE           RCC_CFGR_SW_HSE
00342 #define RCC_SYSCLKSOURCE_PLLCLK        RCC_CFGR_SW_PLL1
00343
00344 /**
00345   * @}
00346   */
00347
00348 /** @defgroup RCC_SYS_Clock_Source  RCC SYS Clock Source
00349   * @{
00350   */
00351 #define RCC_SYSCLK_DIV1                RCC_D1CFGR_D1CPRE_DIV1
00352 #define RCC_SYSCLK_DIV2                RCC_D1CFGR_D1CPRE_DIV2
00353 #define RCC_SYSCLK_DIV4                RCC_D1CFGR_D1CPRE_DIV4
00354 #define RCC_SYSCLK_DIV8                RCC_D1CFGR_D1CPRE_DIV8
00355 #define RCC_SYSCLK_DIV16               RCC_D1CFGR_D1CPRE_DIV16
00356 #define RCC_SYSCLK_DIV64               RCC_D1CFGR_D1CPRE_DIV64
00357 #define RCC_SYSCLK_DIV128              RCC_D1CFGR_D1CPRE_DIV128
00358 #define RCC_SYSCLK_DIV256              RCC_D1CFGR_D1CPRE_DIV256
00359 #define RCC_SYSCLK_DIV512              RCC_D1CFGR_D1CPRE_DIV512
00360
00361 /**
00362   * @}
00363   */
00364
00365
00366 /** @defgroup RCC_HCLK_Clock_Source  RCC HCLK Clock Source
00367   * @{
00368   */
00369 #define RCC_HCLK_DIV1                RCC_D1CFGR_HPRE_DIV1
00370 #define RCC_HCLK_DIV2                RCC_D1CFGR_HPRE_DIV2
00371 #define RCC_HCLK_DIV4                RCC_D1CFGR_HPRE_DIV4
00372 #define RCC_HCLK_DIV8                RCC_D1CFGR_HPRE_DIV8
00373 #define RCC_HCLK_DIV16               RCC_D1CFGR_HPRE_DIV16
00374 #define RCC_HCLK_DIV64               RCC_D1CFGR_HPRE_DIV64
00375 #define RCC_HCLK_DIV128              RCC_D1CFGR_HPRE_DIV128
00376 #define RCC_HCLK_DIV256              RCC_D1CFGR_HPRE_DIV256
00377 #define RCC_HCLK_DIV512              RCC_D1CFGR_HPRE_DIV512
00378
00379 /**
00380   * @}
00381   */
00382
00383 /** @defgroup RCC_APB3_Clock_Source  RCC APB3 Clock Source
00384   * @{
00385   */
00386 #define RCC_APB3_DIV1                  RCC_D1CFGR_D1PPRE_DIV1
00387 #define RCC_APB3_DIV2                  RCC_D1CFGR_D1PPRE_DIV2
00388 #define RCC_APB3_DIV4                  RCC_D1CFGR_D1PPRE_DIV4
00389 #define RCC_APB3_DIV8                  RCC_D1CFGR_D1PPRE_DIV8
00390 #define RCC_APB3_DIV16                 RCC_D1CFGR_D1PPRE_DIV16
00391
00392 /**
00393   * @}
00394   */
00395
00396 /** @defgroup RCC_APB1_Clock_Source  RCC APB1 Clock Source
00397   * @{
00398   */
00399 #define RCC_APB1_DIV1                  RCC_D2CFGR_D2PPRE1_DIV1
00400 #define RCC_APB1_DIV2                  RCC_D2CFGR_D2PPRE1_DIV2
00401 #define RCC_APB1_DIV4                  RCC_D2CFGR_D2PPRE1_DIV4
00402 #define RCC_APB1_DIV8                  RCC_D2CFGR_D2PPRE1_DIV8
00403 #define RCC_APB1_DIV16                 RCC_D2CFGR_D2PPRE1_DIV16
00404
00405 /**
00406   * @}
00407   */
00408
00409 /** @defgroup RCC_APB2_Clock_Source  RCC APB2 Clock Source
00410   * @{
00411   */
00412 #define RCC_APB2_DIV1                  RCC_D2CFGR_D2PPRE2_DIV1
00413 #define RCC_APB2_DIV2                  RCC_D2CFGR_D2PPRE2_DIV2
00414 #define RCC_APB2_DIV4                  RCC_D2CFGR_D2PPRE2_DIV4
00415 #define RCC_APB2_DIV8                  RCC_D2CFGR_D2PPRE2_DIV8
00416 #define RCC_APB2_DIV16                 RCC_D2CFGR_D2PPRE2_DIV16
00417
00418 /**
00419   * @}
00420   */
00421
00422 /** @defgroup RCC_APB4_Clock_Source  RCC APB4 Clock Source
00423   * @{
00424   */
00425 #define RCC_APB4_DIV1                  RCC_D3CFGR_D3PPRE_DIV1
00426 #define RCC_APB4_DIV2                  RCC_D3CFGR_D3PPRE_DIV2
00427 #define RCC_APB4_DIV4                  RCC_D3CFGR_D3PPRE_DIV4
00428 #define RCC_APB4_DIV8                  RCC_D3CFGR_D3PPRE_DIV8
00429 #define RCC_APB4_DIV16                 RCC_D3CFGR_D3PPRE_DIV16
00430
00431 /**
00432   * @}
00433   */
00434
00435 /** @defgroup RCC_RTC_Clock_Source  RCC RTC Clock Source
00436   * @{
00437   */
00438 #define RCC_RTCCLKSOURCE_LSE             ((uint32_t)0x00000100U)
00439 #define RCC_RTCCLKSOURCE_LSI             ((uint32_t)0x00000200U)
00440 #define RCC_RTCCLKSOURCE_HSE_DIV2        ((uint32_t)0x00002300U)
00441 #define RCC_RTCCLKSOURCE_HSE_DIV3        ((uint32_t)0x00003300U)
00442 #define RCC_RTCCLKSOURCE_HSE_DIV4        ((uint32_t)0x00004300U)
00443 #define RCC_RTCCLKSOURCE_HSE_DIV5        ((uint32_t)0x00005300U)
00444 #define RCC_RTCCLKSOURCE_HSE_DIV6        ((uint32_t)0x00006300U)
00445 #define RCC_RTCCLKSOURCE_HSE_DIV7        ((uint32_t)0x00007300U)
00446 #define RCC_RTCCLKSOURCE_HSE_DIV8        ((uint32_t)0x00008300U)
00447 #define RCC_RTCCLKSOURCE_HSE_DIV9        ((uint32_t)0x00009300U)
00448 #define RCC_RTCCLKSOURCE_HSE_DIV10       ((uint32_t)0x0000A300U)
00449 #define RCC_RTCCLKSOURCE_HSE_DIV11       ((uint32_t)0x0000B300U)
00450 #define RCC_RTCCLKSOURCE_HSE_DIV12       ((uint32_t)0x0000C300U)
00451 #define RCC_RTCCLKSOURCE_HSE_DIV13       ((uint32_t)0x0000D300U)
00452 #define RCC_RTCCLKSOURCE_HSE_DIV14       ((uint32_t)0x0000E300U)
00453 #define RCC_RTCCLKSOURCE_HSE_DIV15       ((uint32_t)0x0000F300U)
00454 #define RCC_RTCCLKSOURCE_HSE_DIV16       ((uint32_t)0x00010300U)
00455 #define RCC_RTCCLKSOURCE_HSE_DIV17       ((uint32_t)0x00011300U)
00456 #define RCC_RTCCLKSOURCE_HSE_DIV18       ((uint32_t)0x00012300U)
00457 #define RCC_RTCCLKSOURCE_HSE_DIV19       ((uint32_t)0x00013300U)
00458 #define RCC_RTCCLKSOURCE_HSE_DIV20       ((uint32_t)0x00014300U)
00459 #define RCC_RTCCLKSOURCE_HSE_DIV21       ((uint32_t)0x00015300U)
00460 #define RCC_RTCCLKSOURCE_HSE_DIV22       ((uint32_t)0x00016300U)
00461 #define RCC_RTCCLKSOURCE_HSE_DIV23       ((uint32_t)0x00017300U)
00462 #define RCC_RTCCLKSOURCE_HSE_DIV24       ((uint32_t)0x00018300U)
00463 #define RCC_RTCCLKSOURCE_HSE_DIV25       ((uint32_t)0x00019300U)
00464 #define RCC_RTCCLKSOURCE_HSE_DIV26       ((uint32_t)0x0001A300U)
00465 #define RCC_RTCCLKSOURCE_HSE_DIV27       ((uint32_t)0x0001B300U)
00466 #define RCC_RTCCLKSOURCE_HSE_DIV28       ((uint32_t)0x0001C300U)
00467 #define RCC_RTCCLKSOURCE_HSE_DIV29       ((uint32_t)0x0001D300U)
00468 #define RCC_RTCCLKSOURCE_HSE_DIV30       ((uint32_t)0x0001E300U)
00469 #define RCC_RTCCLKSOURCE_HSE_DIV31       ((uint32_t)0x0001F300U)
00470 #define RCC_RTCCLKSOURCE_HSE_DIV32       ((uint32_t)0x00020300U)
00471 #define RCC_RTCCLKSOURCE_HSE_DIV33       ((uint32_t)0x00021300U)
00472 #define RCC_RTCCLKSOURCE_HSE_DIV34       ((uint32_t)0x00022300U)
00473 #define RCC_RTCCLKSOURCE_HSE_DIV35       ((uint32_t)0x00023300U)
00474 #define RCC_RTCCLKSOURCE_HSE_DIV36       ((uint32_t)0x00024300U)
00475 #define RCC_RTCCLKSOURCE_HSE_DIV37       ((uint32_t)0x00025300U)
00476 #define RCC_RTCCLKSOURCE_HSE_DIV38       ((uint32_t)0x00026300U)
00477 #define RCC_RTCCLKSOURCE_HSE_DIV39       ((uint32_t)0x00027300U)
00478 #define RCC_RTCCLKSOURCE_HSE_DIV40       ((uint32_t)0x00028300U)
00479 #define RCC_RTCCLKSOURCE_HSE_DIV41       ((uint32_t)0x00029300U)
00480 #define RCC_RTCCLKSOURCE_HSE_DIV42       ((uint32_t)0x0002A300U)
00481 #define RCC_RTCCLKSOURCE_HSE_DIV43       ((uint32_t)0x0002B300U)
00482 #define RCC_RTCCLKSOURCE_HSE_DIV44       ((uint32_t)0x0002C300U)
00483 #define RCC_RTCCLKSOURCE_HSE_DIV45       ((uint32_t)0x0002D300U)
00484 #define RCC_RTCCLKSOURCE_HSE_DIV46       ((uint32_t)0x0002E300U)
00485 #define RCC_RTCCLKSOURCE_HSE_DIV47       ((uint32_t)0x0002F300U)
00486 #define RCC_RTCCLKSOURCE_HSE_DIV48       ((uint32_t)0x00030300U)
00487 #define RCC_RTCCLKSOURCE_HSE_DIV49       ((uint32_t)0x00031300U)
00488 #define RCC_RTCCLKSOURCE_HSE_DIV50       ((uint32_t)0x00032300U)
00489 #define RCC_RTCCLKSOURCE_HSE_DIV51       ((uint32_t)0x00033300U)
00490 #define RCC_RTCCLKSOURCE_HSE_DIV52       ((uint32_t)0x00034300U)
00491 #define RCC_RTCCLKSOURCE_HSE_DIV53       ((uint32_t)0x00035300U)
00492 #define RCC_RTCCLKSOURCE_HSE_DIV54       ((uint32_t)0x00036300U)
00493 #define RCC_RTCCLKSOURCE_HSE_DIV55       ((uint32_t)0x00037300U)
00494 #define RCC_RTCCLKSOURCE_HSE_DIV56       ((uint32_t)0x00038300U)
00495 #define RCC_RTCCLKSOURCE_HSE_DIV57       ((uint32_t)0x00039300U)
00496 #define RCC_RTCCLKSOURCE_HSE_DIV58       ((uint32_t)0x0003A300U)
00497 #define RCC_RTCCLKSOURCE_HSE_DIV59       ((uint32_t)0x0003B300U)
00498 #define RCC_RTCCLKSOURCE_HSE_DIV60       ((uint32_t)0x0003C300U)
00499 #define RCC_RTCCLKSOURCE_HSE_DIV61       ((uint32_t)0x0003D300U)
00500 #define RCC_RTCCLKSOURCE_HSE_DIV62       ((uint32_t)0x0003E300U)
00501 #define RCC_RTCCLKSOURCE_HSE_DIV63       ((uint32_t)0x0003F300U)
00502
00503
00504 /**
00505   * @}
00506   */
00507
00508
00509 /** @defgroup RCC_MCO_Index  RCC MCO Index
00510   * @{
00511   */
00512 #define RCC_MCO1                         ((uint32_t)0x00000000)
00513 #define RCC_MCO2                         ((uint32_t)0x00000001)
00514
00515 /**
00516   * @}
00517   */
00518
00519 /** @defgroup RCC_MCO1_Clock_Source  RCC MCO1 Clock Source
00520   * @{
00521   */
00522 #define RCC_MCO1SOURCE_HSI               ((uint32_t)0x00000000)
00523 #define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO1_0
00524 #define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO1_1
00525 #define RCC_MCO1SOURCE_PLL1QCLK          ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1)
00526 #define RCC_MCO1SOURCE_HSI48              RCC_CFGR_MCO1_2
00527
00528 /**
00529   * @}
00530   */
00531
00532 /** @defgroup RCC_MCO2_Clock_Source  RCC MCO2 Clock Source
00533   * @{
00534   */
00535 #define RCC_MCO2SOURCE_SYSCLK            ((uint32_t)0x00000000)
00536 #define RCC_MCO2SOURCE_PLL2PCLK          RCC_CFGR_MCO2_0
00537 #define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1
00538 #define RCC_MCO2SOURCE_PLLCLK          ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1)
00539 #define RCC_MCO2SOURCE_CSICLK            RCC_CFGR_MCO2_2
00540 #define RCC_MCO2SOURCE_LSICLK            ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2)
00541
00542 /**
00543   * @}
00544   */
00545
00546 /** @defgroup RCC_MCOx_Clock_Prescaler  RCC MCOx Clock Prescaler
00547   * @{
00548   */
00549 #define RCC_MCODIV_1                    RCC_CFGR_MCO1PRE_0
00550 #define RCC_MCODIV_2                    RCC_CFGR_MCO1PRE_1
00551 #define RCC_MCODIV_3                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
00552 #define RCC_MCODIV_4                    RCC_CFGR_MCO1PRE_2
00553 #define RCC_MCODIV_5                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
00554 #define RCC_MCODIV_6                    ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
00555 #define RCC_MCODIV_7                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
00556 #define RCC_MCODIV_8                    RCC_CFGR_MCO1PRE_3
00557 #define RCC_MCODIV_9                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
00558 #define RCC_MCODIV_10                   ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
00559 #define RCC_MCODIV_11                   ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
00560 #define RCC_MCODIV_12                   ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
00561 #define RCC_MCODIV_13                   ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
00562 #define RCC_MCODIV_14                   ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
00563 #define RCC_MCODIV_15                   RCC_CFGR_MCO1PRE
00564
00565
00566 /**
00567   * @}
00568   */
00569
00570 /** @defgroup RCC_Interrupt  RCC Interrupt
00571   * @{
00572   */
00573 #define RCC_IT_LSIRDY                  ((uint32_t)0x00000001)
00574 #define RCC_IT_LSERDY                  ((uint32_t)0x00000002)
00575 #define RCC_IT_HSIRDY                  ((uint32_t)0x00000004)
00576 #define RCC_IT_HSERDY                  ((uint32_t)0x00000008)
00577 #define RCC_IT_CSIRDY                  ((uint32_t)0x00000010)
00578 #define RCC_IT_HSI48RDY                ((uint32_t)0x00000020)
00579 #define RCC_IT_PLLRDY                  ((uint32_t)0x00000040)
00580 #define RCC_IT_PLL2RDY                 ((uint32_t)0x00000080)
00581 #define RCC_IT_PLL3RDY                 ((uint32_t)0x00000100)
00582 #define RCC_IT_LSECSS                  ((uint32_t)0x00000200)
00583 #define RCC_IT_CSS                     ((uint32_t)0x00000400)
00584 /**
00585   * @}
00586   */
00587
00588 /** @defgroup RCC_Flag  RCC Flag
00589   *        Elements values convention: 0XXYYYYYb
00590   *           - YYYYY  : Flag position in the register
00591   *           - 0XX  : Register index
00592   *                 - 01: CR register
00593   *                 - 10: BDCR register
00594   *                 - 11: CSR register
00595   * @{
00596   */
00597 /* Flags in the CR register */
00598 #define RCC_FLAG_HSIRDY                ((uint8_t)0x22)
00599 #define RCC_FLAG_HSIDIV                ((uint8_t)0x25)
00600 #define RCC_FLAG_CSIRDY                ((uint8_t)0x28)
00601 #define RCC_FLAG_HSI48RDY              ((uint8_t)0x2D)
00602 #define RCC_FLAG_D1CKRDY               ((uint8_t)0x2E)
00603 #define RCC_FLAG_D2CKRDY               ((uint8_t)0x2F)
00604 #define RCC_FLAG_HSERDY                ((uint8_t)0x31)
00605 #define RCC_FLAG_PLLRDY                ((uint8_t)0x39)
00606 #define RCC_FLAG_PLL2RDY               ((uint8_t)0x3B)
00607 #define RCC_FLAG_PLL3RDY               ((uint8_t)0x3D)
00608 /* Flags in the BDCR register */
00609 #define RCC_FLAG_LSERDY                ((uint8_t)0x41)
00610
00611 /* Flags in the CSR register */
00612 #define RCC_FLAG_LSIRDY                ((uint8_t)0x61)
00613
00614 /* Flags in the RSR register */
00615 #define RCC_FLAG_RMVF                  ((uint8_t)0x90)
00616 #define RCC_FLAG_CPURST                ((uint8_t)0x91)
00617
00618
00619 #define RCC_FLAG_D1RST                 ((uint8_t)0x93)
00620 #define RCC_FLAG_D2RST                 ((uint8_t)0x94)
00621 #define RCC_FLAG_BORRST                ((uint8_t)0x95)
00622 #define RCC_FLAG_PINRST                ((uint8_t)0x96)
00623 #define RCC_FLAG_PORRST                ((uint8_t)0x97)
00624 #define RCC_FLAG_SFTRST                ((uint8_t)0x98)
00625 #define RCC_FLAG_IWDG1RST              ((uint8_t)0x9A)
00626 #define RCC_FLAG_WWDG1RST              ((uint8_t)0x9C)
00627 #define RCC_FLAG_LPWR1RST              ((uint8_t)0x9E)
00628 #define RCC_FLAG_LPWR2RST              ((uint8_t)0x9F)
00629
00630
00631 /**
00632   * @}
00633   */
00634
00635 /** @defgroup RCC_LSEDrive_Config LSE Drive Config
00636   * @{
00637   */
00638 #define RCC_LSEDRIVE_LOW                 ((uint32_t)0x00000000) /*!< LSE low drive capability */
00639 #define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_0      /*!< LSE medium low drive capability */
00640                                                                 /* Workaround implementation on medium low */
00641 #define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_1      /*!< LSE medium high drive capability */
00642                                                                 /* Workaround implementation on medium high */
00643 #define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV        /*!< LSE high drive capability */
00644 /**
00645   * @}
00646   */
00647
00648 /** @defgroup RCC_Stop_WakeUpClock  RCC Stop WakeUpClock
00649   * @{
00650   */
00651 #define RCC_STOP_WAKEUPCLOCK_HSI       ((uint32_t)0x00000000)
00652 #define RCC_STOP_WAKEUPCLOCK_CSI       RCC_CFGR_STOPWUCK
00653
00654 /**
00655   * @}
00656   */
00657
00658 /** @defgroup RCC_Stop_KernelWakeUpClock  RCC Stop KernelWakeUpClock
00659   * @{
00660   */
00661 #define RCC_STOP_KERWAKEUPCLOCK_HSI       ((uint32_t)0x00000000)
00662 #define RCC_STOP_KERWAKEUPCLOCK_CSI        RCC_CFGR_STOPKERWUCK
00663
00664
00665 /**
00666   * @}
00667   */
00668 /**
00669   * @}
00670   */
00671
00672 /* Exported macros -----------------------------------------------------------*/
00673
00674 /** @defgroup RCC_Exported_Macros RCC Exported Macros
00675   * @{
00676   */
00677
00678 /** @brief  Enable or disable the AHB3 peripheral clock.
00679   * @note   After reset, the peripheral clock (used for registers read/write access)
00680   *         is disabled and the application software has to enable this clock before
00681   *         using it.
00682   */
00683 #define __HAL_RCC_MDMA_CLK_ENABLE()   do { \
00684                                         __IO uint32_t tmpreg; \
00685                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
00686                                         /* Delay after an RCC peripheral clock enabling */ \
00687                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
00688                                         UNUSED(tmpreg); \
00689                                        } while(0)
00690
00691 #define __HAL_RCC_DMA2D_CLK_ENABLE()   do { \
00692                                         __IO uint32_t tmpreg; \
00693                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
00694                                         /* Delay after an RCC peripheral clock enabling */ \
00695                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
00696                                         UNUSED(tmpreg); \
00697                                        } while(0)
00698
00699 #define __HAL_RCC_JPGDECEN_CLK_ENABLE()   do { \
00700                                         __IO uint32_t tmpreg; \
00701                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
00702                                         /* Delay after an RCC peripheral clock enabling */ \
00703                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
00704                                         UNUSED(tmpreg); \
00705                                        } while(0)
00706
00707 #define __HAL_RCC_FLASH_CLK_ENABLE()   do { \
00708                                         __IO uint32_t tmpreg; \
00709                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FLASHEN);\
00710                                         /* Delay after an RCC peripheral clock enabling */ \
00711                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FLASHEN);\
00712                                         UNUSED(tmpreg); \
00713                                        } while(0)
00714
00715 #define __HAL_RCC_FMC_CLK_ENABLE()   do { \
00716                                         __IO uint32_t tmpreg; \
00717                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
00718                                         /* Delay after an RCC peripheral clock enabling */ \
00719                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
00720                                         UNUSED(tmpreg); \
00721                                        } while(0)
00722
00723 #define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
00724                                         __IO uint32_t tmpreg; \
00725                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
00726                                         /* Delay after an RCC peripheral clock enabling */ \
00727                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
00728                                         UNUSED(tmpreg); \
00729                                        } while(0)
00730
00731 #define __HAL_RCC_SDMMC1_CLK_ENABLE()   do { \
00732                                         __IO uint32_t tmpreg; \
00733                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
00734                                         /* Delay after an RCC peripheral clock enabling */ \
00735                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
00736                                         UNUSED(tmpreg); \
00737                                        } while(0)
00738
00739
00740 #define __HAL_RCC_MDMA_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
00741 #define __HAL_RCC_DMA2D_CLK_DISABLE()           (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
00742 #define __HAL_RCC_JPGDECEN_CLK_DISABLE()        (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
00743 #define __HAL_RCC_FLASH_CLK_DISABLE()           (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FLASHEN))
00744 #define __HAL_RCC_FMC_CLK_DISABLE()             (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
00745 #define __HAL_RCC_QSPI_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
00746 #define __HAL_RCC_SDMMC1_CLK_DISABLE()          (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
00747
00748
00749 /** @brief  Enable or disable the AHB1 peripheral clock.
00750   * @note   After reset, the peripheral clock (used for registers read/write access)
00751   *         is disabled and the application software has to enable this clock before
00752   *         using it.
00753   */
00754
00755 #define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
00756                                         __IO uint32_t tmpreg; \
00757                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
00758                                         /* Delay after an RCC peripheral clock enabling */ \
00759                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
00760                                         UNUSED(tmpreg); \
00761                                        } while(0)
00762
00763 #define __HAL_RCC_DMA2_CLK_ENABLE()   do { \
00764                                         __IO uint32_t tmpreg; \
00765                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
00766                                         /* Delay after an RCC peripheral clock enabling */ \
00767                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
00768                                         UNUSED(tmpreg); \
00769                                        } while(0)
00770
00771 #define __HAL_RCC_ADC12_CLK_ENABLE()   do { \
00772                                         __IO uint32_t tmpreg; \
00773                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
00774                                         /* Delay after an RCC peripheral clock enabling */ \
00775                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
00776                                         UNUSED(tmpreg); \
00777                                        } while(0)
00778
00779 #define __HAL_RCC_ETH1MAC_CLK_ENABLE()   do { \
00780                                         __IO uint32_t tmpreg; \
00781                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
00782                                         /* Delay after an RCC peripheral clock enabling */ \
00783                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
00784                                         UNUSED(tmpreg); \
00785                                        } while(0)
00786
00787 #define __HAL_RCC_ETH1TX_CLK_ENABLE()   do { \
00788                                         __IO uint32_t tmpreg; \
00789                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
00790                                         /* Delay after an RCC peripheral clock enabling */ \
00791                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
00792                                         UNUSED(tmpreg); \
00793                                        } while(0)
00794
00795 #define __HAL_RCC_ETH1RX_CLK_ENABLE()   do { \
00796                                         __IO uint32_t tmpreg; \
00797                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
00798                                         /* Delay after an RCC peripheral clock enabling */ \
00799                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
00800                                         UNUSED(tmpreg); \
00801                                        } while(0)
00802
00803 #define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()   do { \
00804                                         __IO uint32_t tmpreg; \
00805                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
00806                                         /* Delay after an RCC peripheral clock enabling */ \
00807                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
00808                                         UNUSED(tmpreg); \
00809                                        } while(0)
00810
00811 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \
00812                                         __IO uint32_t tmpreg; \
00813                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
00814                                         /* Delay after an RCC peripheral clock enabling */ \
00815                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
00816                                         UNUSED(tmpreg); \
00817                                        } while(0)
00818
00819 #define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()   do { \
00820                                         __IO uint32_t tmpreg; \
00821                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
00822                                         /* Delay after an RCC peripheral clock enabling */ \
00823                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
00824                                         UNUSED(tmpreg); \
00825                                        } while(0)
00826
00827 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \
00828                                         __IO uint32_t tmpreg; \
00829                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
00830                                         /* Delay after an RCC peripheral clock enabling */ \
00831                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
00832                                         UNUSED(tmpreg); \
00833                                        } while(0)
00834
00835 #define __HAL_RCC_DMA1_CLK_DISABLE()             (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
00836 #define __HAL_RCC_DMA2_CLK_DISABLE()             (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
00837 #define __HAL_RCC_ADC12_CLK_DISABLE()            (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
00838 #define __HAL_RCC_ETH1MAC_CLK_DISABLE()          (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
00839 #define __HAL_RCC_ETH1TX_CLK_DISABLE()           (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
00840 #define __HAL_RCC_ETH1RX_CLK_DISABLE()           (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
00841 #define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
00842 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
00843 #define __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()      (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
00844 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
00845
00846 /** @brief  Enable or disable the AHB2 peripheral clock.
00847   * @note   After reset, the peripheral clock (used for registers read/write access)
00848   *         is disabled and the application software has to enable this clock before
00849   *         using it.
00850   */
00851
00852 #define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
00853                                         __IO uint32_t tmpreg; \
00854                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
00855                                         /* Delay after an RCC peripheral clock enabling */ \
00856                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
00857                                         UNUSED(tmpreg); \
00858                                        } while(0)
00859
00860 #define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
00861                                         __IO uint32_t tmpreg; \
00862                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
00863                                         /* Delay after an RCC peripheral clock enabling */ \
00864                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
00865                                         UNUSED(tmpreg); \
00866                                        } while(0)
00867
00868 #define __HAL_RCC_HASH_CLK_ENABLE()   do { \
00869                                         __IO uint32_t tmpreg; \
00870                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
00871                                         /* Delay after an RCC peripheral clock enabling */ \
00872                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
00873                                         UNUSED(tmpreg); \
00874                                        } while(0)
00875
00876 #define __HAL_RCC_RNG_CLK_ENABLE()   do { \
00877                                         __IO uint32_t tmpreg; \
00878                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
00879                                         /* Delay after an RCC peripheral clock enabling */ \
00880                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
00881                                         UNUSED(tmpreg); \
00882                                        } while(0)
00883
00884 #define __HAL_RCC_SDMMC2_CLK_ENABLE()   do { \
00885                                         __IO uint32_t tmpreg; \
00886                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
00887                                         /* Delay after an RCC peripheral clock enabling */ \
00888                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
00889                                         UNUSED(tmpreg); \
00890                                        } while(0)
00891
00892 #define __HAL_RCC_D2SRAM1_CLK_ENABLE()   do { \
00893                                         __IO uint32_t tmpreg; \
00894                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
00895                                         /* Delay after an RCC peripheral clock enabling */ \
00896                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
00897                                         UNUSED(tmpreg); \
00898                                        } while(0)
00899
00900 #define __HAL_RCC_D2SRAM2_CLK_ENABLE()   do { \
00901                                         __IO uint32_t tmpreg; \
00902                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
00903                                         /* Delay after an RCC peripheral clock enabling */ \
00904                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
00905                                         UNUSED(tmpreg); \
00906                                        } while(0)
00907
00908 #define __HAL_RCC_D2SRAM3_CLK_ENABLE()   do { \
00909                                         __IO uint32_t tmpreg; \
00910                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
00911                                         /* Delay after an RCC peripheral clock enabling */ \
00912                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
00913                                         UNUSED(tmpreg); \
00914                                        } while(0)
00915
00916 #define __HAL_RCC_DCMI_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
00917 #define __HAL_RCC_CRYP_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
00918 #define __HAL_RCC_HASH_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
00919 #define __HAL_RCC_RNG_CLK_DISABLE()              (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
00920 #define __HAL_RCC_SDMMC2_CLK_DISABLE()           (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
00921 #define __HAL_RCC_D2SRAM1_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
00922 #define __HAL_RCC_D2SRAM2_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
00923 #define __HAL_RCC_D2SRAM3_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
00924
00925 /** @brief  Enable or disable the AHB4 peripheral clock.
00926   * @note   After reset, the peripheral clock (used for registers read/write access)
00927   *         is disabled and the application software has to enable this clock before
00928   *         using it.
00929   */
00930
00931 #define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
00932                                         __IO uint32_t tmpreg; \
00933                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
00934                                         /* Delay after an RCC peripheral clock enabling */ \
00935                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
00936                                         UNUSED(tmpreg); \
00937                                        } while(0)
00938
00939 #define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
00940                                         __IO uint32_t tmpreg; \
00941                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
00942                                         /* Delay after an RCC peripheral clock enabling */ \
00943                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
00944                                         UNUSED(tmpreg); \
00945                                        } while(0)
00946
00947 #define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
00948                                         __IO uint32_t tmpreg; \
00949                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
00950                                         /* Delay after an RCC peripheral clock enabling */ \
00951                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
00952                                         UNUSED(tmpreg); \
00953                                        } while(0)
00954
00955 #define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
00956                                         __IO uint32_t tmpreg; \
00957                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
00958                                         /* Delay after an RCC peripheral clock enabling */ \
00959                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
00960                                         UNUSED(tmpreg); \
00961                                        } while(0)
00962
00963 #define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
00964                                         __IO uint32_t tmpreg; \
00965                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
00966                                         /* Delay after an RCC peripheral clock enabling */ \
00967                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
00968                                         UNUSED(tmpreg); \
00969                                        } while(0)
00970
00971 #define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
00972                                         __IO uint32_t tmpreg; \
00973                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
00974                                         /* Delay after an RCC peripheral clock enabling */ \
00975                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
00976                                         UNUSED(tmpreg); \
00977                                        } while(0)
00978
00979 #define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
00980                                         __IO uint32_t tmpreg; \
00981                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
00982                                         /* Delay after an RCC peripheral clock enabling */ \
00983                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
00984                                         UNUSED(tmpreg); \
00985                                        } while(0)
00986
00987 #define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \
00988                                         __IO uint32_t tmpreg; \
00989                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
00990                                         /* Delay after an RCC peripheral clock enabling */ \
00991                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
00992                                         UNUSED(tmpreg); \
00993                                        } while(0)
00994
00995 #define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \
00996                                         __IO uint32_t tmpreg; \
00997                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
00998                                         /* Delay after an RCC peripheral clock enabling */ \
00999                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
01000                                         UNUSED(tmpreg); \
01001                                        } while(0)
01002
01003 #define __HAL_RCC_GPIOJ_CLK_ENABLE()   do { \
01004                                         __IO uint32_t tmpreg; \
01005                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
01006                                         /* Delay after an RCC peripheral clock enabling */ \
01007                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
01008                                         UNUSED(tmpreg); \
01009                                        } while(0)
01010
01011 #define __HAL_RCC_GPIOK_CLK_ENABLE()   do { \
01012                                         __IO uint32_t tmpreg; \
01013                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
01014                                         /* Delay after an RCC peripheral clock enabling */ \
01015                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
01016                                         UNUSED(tmpreg); \
01017                                        } while(0)
01018
01019 #define __HAL_RCC_CRC_CLK_ENABLE()   do { \
01020                                         __IO uint32_t tmpreg; \
01021                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
01022                                         /* Delay after an RCC peripheral clock enabling */ \
01023                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
01024                                         UNUSED(tmpreg); \
01025                                        } while(0)
01026
01027 #define __HAL_RCC_BDMA_CLK_ENABLE()   do { \
01028                                         __IO uint32_t tmpreg; \
01029                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
01030                                         /* Delay after an RCC peripheral clock enabling */ \
01031                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
01032                                         UNUSED(tmpreg); \
01033                                        } while(0)
01034
01035 #define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
01036                                         __IO uint32_t tmpreg; \
01037                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
01038                                         /* Delay after an RCC peripheral clock enabling */ \
01039                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
01040                                         UNUSED(tmpreg); \
01041                                        } while(0)
01042
01043 #define __HAL_RCC_HSEM_CLK_ENABLE()   do { \
01044                                         __IO uint32_t tmpreg; \
01045                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
01046                                         /* Delay after an RCC peripheral clock enabling */ \
01047                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
01048                                         UNUSED(tmpreg); \
01049                                        } while(0)
01050
01051 #define __HAL_RCC_BKPRAM_CLK_ENABLE()   do { \
01052                                         __IO uint32_t tmpreg; \
01053                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
01054                                         /* Delay after an RCC peripheral clock enabling */ \
01055                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
01056                                         UNUSED(tmpreg); \
01057                                        } while(0)
01058
01059
01060 #define __HAL_RCC_GPIOA_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
01061 #define __HAL_RCC_GPIOB_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
01062 #define __HAL_RCC_GPIOC_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
01063 #define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
01064 #define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
01065 #define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
01066 #define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
01067 #define __HAL_RCC_GPIOH_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
01068 #define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
01069 #define __HAL_RCC_GPIOJ_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
01070 #define __HAL_RCC_GPIOK_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
01071 #define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
01072 #define __HAL_RCC_BDMA_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
01073 #define __HAL_RCC_ADC3_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
01074 #define __HAL_RCC_HSEM_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
01075 #define __HAL_RCC_BKPRAM_CLK_DISABLE()          (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
01076
01077
01078 /** @brief  Enable or disable the APB3 peripheral clock.
01079   * @note   After reset, the peripheral clock (used for registers read/write access)
01080   *         is disabled and the application software has to enable this clock before
01081   *         using it.
01082   */
01083
01084 #define __HAL_RCC_LTDC_CLK_ENABLE()   do { \
01085                                         __IO uint32_t tmpreg; \
01086                                         SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
01087                                         /* Delay after an RCC peripheral clock enabling */ \
01088                                         tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
01089                                         UNUSED(tmpreg); \
01090                                        } while(0)
01091
01092
01093 #define __HAL_RCC_WWDG1_CLK_ENABLE()   do { \
01094                                         __IO uint32_t tmpreg; \
01095                                         SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
01096                                         /* Delay after an RCC peripheral clock enabling */ \
01097                                         tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
01098                                         UNUSED(tmpreg); \
01099                                        } while(0)
01100
01101 #define __HAL_RCC_LTDC_CLK_DISABLE()           (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
01102 #define __HAL_RCC_WWDG1_CLK_DISABLE()          (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
01103
01104 /** @brief  Enable or disable the APB1 peripheral clock.
01105   * @note   After reset, the peripheral clock (used for registers read/write access)
01106   *         is disabled and the application software has to enable this clock before
01107   *         using it.
01108   */
01109
01110 #define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
01111                                         __IO uint32_t tmpreg; \
01112                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
01113                                         /* Delay after an RCC peripheral clock enabling */ \
01114                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
01115                                         UNUSED(tmpreg); \
01116                                        } while(0)
01117
01118 #define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
01119                                         __IO uint32_t tmpreg; \
01120                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
01121                                         /* Delay after an RCC peripheral clock enabling */ \
01122                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
01123                                         UNUSED(tmpreg); \
01124                                        } while(0)
01125
01126 #define __HAL_RCC_TIM4_CLK_ENABLE()   do { \
01127                                         __IO uint32_t tmpreg; \
01128                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
01129                                         /* Delay after an RCC peripheral clock enabling */ \
01130                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
01131                                         UNUSED(tmpreg); \
01132                                        } while(0)
01133
01134 #define __HAL_RCC_TIM5_CLK_ENABLE()   do { \
01135                                         __IO uint32_t tmpreg; \
01136                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
01137                                         /* Delay after an RCC peripheral clock enabling */ \
01138                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
01139                                         UNUSED(tmpreg); \
01140                                        } while(0)
01141
01142 #define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
01143                                         __IO uint32_t tmpreg; \
01144                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
01145                                         /* Delay after an RCC peripheral clock enabling */ \
01146                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
01147                                         UNUSED(tmpreg); \
01148                                        } while(0)
01149
01150 #define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
01151                                         __IO uint32_t tmpreg; \
01152                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
01153                                         /* Delay after an RCC peripheral clock enabling */ \
01154                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
01155                                         UNUSED(tmpreg); \
01156                                        } while(0)
01157
01158 #define __HAL_RCC_TIM12_CLK_ENABLE()   do { \
01159                                         __IO uint32_t tmpreg; \
01160                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
01161                                         /* Delay after an RCC peripheral clock enabling */ \
01162                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
01163                                         UNUSED(tmpreg); \
01164                                        } while(0)
01165
01166 #define __HAL_RCC_TIM13_CLK_ENABLE()   do { \
01167                                         __IO uint32_t tmpreg; \
01168                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
01169                                         /* Delay after an RCC peripheral clock enabling */ \
01170                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
01171                                         UNUSED(tmpreg); \
01172                                        } while(0)
01173
01174 #define __HAL_RCC_TIM14_CLK_ENABLE()   do { \
01175                                         __IO uint32_t tmpreg; \
01176                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
01177                                         /* Delay after an RCC peripheral clock enabling */ \
01178                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
01179                                         UNUSED(tmpreg); \
01180                                        } while(0)
01181
01182 #define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \
01183                                         __IO uint32_t tmpreg; \
01184                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
01185                                         /* Delay after an RCC peripheral clock enabling */ \
01186                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
01187                                         UNUSED(tmpreg); \
01188                                        } while(0)
01189
01190
01191 #define __HAL_RCC_SPI2_CLK_ENABLE()   do { \
01192                                         __IO uint32_t tmpreg; \
01193                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
01194                                         /* Delay after an RCC peripheral clock enabling */ \
01195                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
01196                                         UNUSED(tmpreg); \
01197                                        } while(0)
01198
01199 #define __HAL_RCC_SPI3_CLK_ENABLE()   do { \
01200                                         __IO uint32_t tmpreg; \
01201                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
01202                                         /* Delay after an RCC peripheral clock enabling */ \
01203                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
01204                                         UNUSED(tmpreg); \
01205                                        } while(0)
01206
01207 #define __HAL_RCC_SPDIFRX_CLK_ENABLE()   do { \
01208                                         __IO uint32_t tmpreg; \
01209                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
01210                                         /* Delay after an RCC peripheral clock enabling */ \
01211                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
01212                                         UNUSED(tmpreg); \
01213                                        } while(0)
01214
01215 #define __HAL_RCC_USART2_CLK_ENABLE()   do { \
01216                                         __IO uint32_t tmpreg; \
01217                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
01218                                         /* Delay after an RCC peripheral clock enabling */ \
01219                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
01220                                         UNUSED(tmpreg); \
01221                                        } while(0)
01222
01223 #define __HAL_RCC_USART3_CLK_ENABLE()   do { \
01224                                         __IO uint32_t tmpreg; \
01225                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
01226                                         /* Delay after an RCC peripheral clock enabling */ \
01227                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
01228                                         UNUSED(tmpreg); \
01229                                        } while(0)
01230
01231 #define __HAL_RCC_UART4_CLK_ENABLE()   do { \
01232                                         __IO uint32_t tmpreg; \
01233                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
01234                                         /* Delay after an RCC peripheral clock enabling */ \
01235                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
01236                                         UNUSED(tmpreg); \
01237                                        } while(0)
01238
01239 #define __HAL_RCC_UART5_CLK_ENABLE()   do { \
01240                                         __IO uint32_t tmpreg; \
01241                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
01242                                         /* Delay after an RCC peripheral clock enabling */ \
01243                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
01244                                         UNUSED(tmpreg); \
01245                                        } while(0)
01246
01247 #define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
01248                                         __IO uint32_t tmpreg; \
01249                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
01250                                         /* Delay after an RCC peripheral clock enabling */ \
01251                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
01252                                         UNUSED(tmpreg); \
01253                                        } while(0)
01254
01255 #define __HAL_RCC_I2C2_CLK_ENABLE()   do { \
01256                                         __IO uint32_t tmpreg; \
01257                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
01258                                         /* Delay after an RCC peripheral clock enabling */ \
01259                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
01260                                         UNUSED(tmpreg); \
01261                                        } while(0)
01262
01263 #define __HAL_RCC_I2C3_CLK_ENABLE()   do { \
01264                                         __IO uint32_t tmpreg; \
01265                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
01266                                         /* Delay after an RCC peripheral clock enabling */ \
01267                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
01268                                         UNUSED(tmpreg); \
01269                                        } while(0)
01270
01271 #define __HAL_RCC_CEC_CLK_ENABLE()   do { \
01272                                         __IO uint32_t tmpreg; \
01273                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
01274                                         /* Delay after an RCC peripheral clock enabling */ \
01275                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
01276                                         UNUSED(tmpreg); \
01277                                        } while(0)
01278
01279 #define __HAL_RCC_DAC12_CLK_ENABLE()   do { \
01280                                         __IO uint32_t tmpreg; \
01281                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
01282                                         /* Delay after an RCC peripheral clock enabling */ \
01283                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
01284                                         UNUSED(tmpreg); \
01285                                        } while(0)
01286
01287 #define __HAL_RCC_UART7_CLK_ENABLE()   do { \
01288                                         __IO uint32_t tmpreg; \
01289                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
01290                                         /* Delay after an RCC peripheral clock enabling */ \
01291                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
01292                                         UNUSED(tmpreg); \
01293                                        } while(0)
01294
01295 #define __HAL_RCC_UART8_CLK_ENABLE()   do { \
01296                                         __IO uint32_t tmpreg; \
01297                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
01298                                         /* Delay after an RCC peripheral clock enabling */ \
01299                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
01300                                         UNUSED(tmpreg); \
01301                                        } while(0)
01302
01303 #define __HAL_RCC_CRS_CLK_ENABLE()   do { \
01304                                         __IO uint32_t tmpreg; \
01305                                         SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
01306                                         /* Delay after an RCC peripheral clock enabling */ \
01307                                         tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
01308                                         UNUSED(tmpreg); \
01309                                        } while(0)
01310
01311 #define __HAL_RCC_SWPMI1_CLK_ENABLE()   do { \
01312                                         __IO uint32_t tmpreg; \
01313                                         SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
01314                                         /* Delay after an RCC peripheral clock enabling */ \
01315                                         tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
01316                                         UNUSED(tmpreg); \
01317                                        } while(0)
01318
01319 #define __HAL_RCC_OPAMP_CLK_ENABLE()   do { \
01320                                         __IO uint32_t tmpreg; \
01321                                         SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
01322                                         /* Delay after an RCC peripheral clock enabling */ \
01323                                         tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
01324                                         UNUSED(tmpreg); \
01325                                        } while(0)
01326
01327 #define __HAL_RCC_MDIOS_CLK_ENABLE()   do { \
01328                                         __IO uint32_t tmpreg; \
01329                                         SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
01330                                         /* Delay after an RCC peripheral clock enabling */ \
01331                                         tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
01332                                         UNUSED(tmpreg); \
01333                                        } while(0)
01334
01335 #define __HAL_RCC_FDCAN_CLK_ENABLE()   do { \
01336                                         __IO uint32_t tmpreg; \
01337                                         SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
01338                                         /* Delay after an RCC peripheral clock enabling */ \
01339                                         tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
01340                                         UNUSED(tmpreg); \
01341                                        } while(0)
01342
01343
01344 #define __HAL_RCC_TIM2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
01345 #define __HAL_RCC_TIM3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
01346 #define __HAL_RCC_TIM4_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
01347 #define __HAL_RCC_TIM5_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
01348 #define __HAL_RCC_TIM6_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
01349 #define __HAL_RCC_TIM7_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
01350 #define __HAL_RCC_TIM12_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
01351 #define __HAL_RCC_TIM13_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
01352 #define __HAL_RCC_TIM14_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
01353 #define __HAL_RCC_LPTIM1_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
01354
01355
01356 #define __HAL_RCC_SPI2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
01357 #define __HAL_RCC_SPI3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
01358 #define __HAL_RCC_SPDIFRX_CLK_DISABLE()        (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
01359 #define __HAL_RCC_USART2_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
01360 #define __HAL_RCC_USART3_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
01361 #define __HAL_RCC_UART4_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
01362 #define __HAL_RCC_UART5_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
01363 #define __HAL_RCC_I2C1_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
01364 #define __HAL_RCC_I2C2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
01365 #define __HAL_RCC_I2C3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
01366 #define __HAL_RCC_CEC_CLK_DISABLE()            (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
01367 #define __HAL_RCC_DAC12_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
01368 #define __HAL_RCC_UART7_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
01369 #define __HAL_RCC_UART8_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
01370 #define __HAL_RCC_CRS_CLK_DISABLE()            (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
01371 #define __HAL_RCC_SWPMI1_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
01372 #define __HAL_RCC_OPAMP_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
01373 #define __HAL_RCC_MDIOS_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
01374 #define __HAL_RCC_FDCAN_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
01375
01376 /** @brief  Enable or disable the APB2 peripheral clock.
01377   * @note   After reset, the peripheral clock (used for registers read/write access)
01378   *         is disabled and the application software has to enable this clock before
01379   *         using it.
01380   */
01381
01382 #define __HAL_RCC_TIM1_CLK_ENABLE()   do { \
01383                                         __IO uint32_t tmpreg; \
01384                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
01385                                         /* Delay after an RCC peripheral clock enabling */ \
01386                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
01387                                         UNUSED(tmpreg); \
01388                                        } while(0)
01389
01390 #define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
01391                                         __IO uint32_t tmpreg; \
01392                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
01393                                         /* Delay after an RCC peripheral clock enabling */ \
01394                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
01395                                         UNUSED(tmpreg); \
01396                                        } while(0)
01397
01398 #define __HAL_RCC_USART1_CLK_ENABLE()   do { \
01399                                         __IO uint32_t tmpreg; \
01400                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
01401                                         /* Delay after an RCC peripheral clock enabling */ \
01402                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
01403                                         UNUSED(tmpreg); \
01404                                        } while(0)
01405
01406 #define __HAL_RCC_USART6_CLK_ENABLE()   do { \
01407                                         __IO uint32_t tmpreg; \
01408                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
01409                                         /* Delay after an RCC peripheral clock enabling */ \
01410                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
01411                                         UNUSED(tmpreg); \
01412                                        } while(0)
01413
01414 #define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
01415                                         __IO uint32_t tmpreg; \
01416                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
01417                                         /* Delay after an RCC peripheral clock enabling */ \
01418                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
01419                                         UNUSED(tmpreg); \
01420                                        } while(0)
01421
01422 #define __HAL_RCC_SPI4_CLK_ENABLE()   do { \
01423                                         __IO uint32_t tmpreg; \
01424                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
01425                                         /* Delay after an RCC peripheral clock enabling */ \
01426                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
01427                                         UNUSED(tmpreg); \
01428                                        } while(0)
01429
01430 #define __HAL_RCC_TIM15_CLK_ENABLE()   do { \
01431                                         __IO uint32_t tmpreg; \
01432                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
01433                                         /* Delay after an RCC peripheral clock enabling */ \
01434                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
01435                                         UNUSED(tmpreg); \
01436                                        } while(0)
01437
01438 #define __HAL_RCC_TIM16_CLK_ENABLE()   do { \
01439                                         __IO uint32_t tmpreg; \
01440                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
01441                                         /* Delay after an RCC peripheral clock enabling */ \
01442                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
01443                                         UNUSED(tmpreg); \
01444                                        } while(0)
01445
01446 #define __HAL_RCC_TIM17_CLK_ENABLE()   do { \
01447                                         __IO uint32_t tmpreg; \
01448                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
01449                                         /* Delay after an RCC peripheral clock enabling */ \
01450                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
01451                                         UNUSED(tmpreg); \
01452                                        } while(0)
01453
01454 #define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
01455                                         __IO uint32_t tmpreg; \
01456                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
01457                                         /* Delay after an RCC peripheral clock enabling */ \
01458                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
01459                                         UNUSED(tmpreg); \
01460                                        } while(0)
01461
01462 #define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
01463                                         __IO uint32_t tmpreg; \
01464                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
01465                                         /* Delay after an RCC peripheral clock enabling */ \
01466                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
01467                                         UNUSED(tmpreg); \
01468                                        } while(0)
01469
01470 #define __HAL_RCC_SAI2_CLK_ENABLE()   do { \
01471                                         __IO uint32_t tmpreg; \
01472                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
01473                                         /* Delay after an RCC peripheral clock enabling */ \
01474                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
01475                                         UNUSED(tmpreg); \
01476                                        } while(0)
01477
01478 #define __HAL_RCC_SAI3_CLK_ENABLE()   do { \
01479                                         __IO uint32_t tmpreg; \
01480                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
01481                                         /* Delay after an RCC peripheral clock enabling */ \
01482                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
01483                                         UNUSED(tmpreg); \
01484                                        } while(0)
01485
01486 #define __HAL_RCC_DFSDM1_CLK_ENABLE()   do { \
01487                                         __IO uint32_t tmpreg; \
01488                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
01489                                         /* Delay after an RCC peripheral clock enabling */ \
01490                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
01491                                         UNUSED(tmpreg); \
01492                                        } while(0)
01493
01494 #define __HAL_RCC_HRTIM1_CLK_ENABLE()   do { \
01495                                         __IO uint32_t tmpreg; \
01496                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
01497                                         /* Delay after an RCC peripheral clock enabling */ \
01498                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
01499                                         UNUSED(tmpreg); \
01500                                        } while(0)
01501
01502 #define __HAL_RCC_TIM1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
01503 #define __HAL_RCC_TIM8_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
01504 #define __HAL_RCC_USART1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
01505 #define __HAL_RCC_USART6_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
01506 #define __HAL_RCC_SPI1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
01507 #define __HAL_RCC_SPI4_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
01508 #define __HAL_RCC_TIM15_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
01509 #define __HAL_RCC_TIM16_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
01510 #define __HAL_RCC_TIM17_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
01511 #define __HAL_RCC_SPI5_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
01512 #define __HAL_RCC_SAI1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
01513 #define __HAL_RCC_SAI2_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
01514 #define __HAL_RCC_SAI3_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
01515 #define __HAL_RCC_DFSDM1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
01516 #define __HAL_RCC_HRTIM1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
01517
01518 /** @brief  Enable or disable the APB4 peripheral clock.
01519   * @note   After reset, the peripheral clock (used for registers read/write access)
01520   *         is disabled and the application software has to enable this clock before
01521   *         using it.
01522   */
01523
01524 #define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
01525                                         __IO uint32_t tmpreg; \
01526                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
01527                                         /* Delay after an RCC peripheral clock enabling */ \
01528                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
01529                                         UNUSED(tmpreg); \
01530                                        } while(0)
01531
01532 #define __HAL_RCC_LPUART1_CLK_ENABLE()   do { \
01533                                         __IO uint32_t tmpreg; \
01534                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
01535                                         /* Delay after an RCC peripheral clock enabling */ \
01536                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
01537                                         UNUSED(tmpreg); \
01538                                        } while(0)
01539
01540 #define __HAL_RCC_SPI6_CLK_ENABLE()   do { \
01541                                         __IO uint32_t tmpreg; \
01542                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
01543                                         /* Delay after an RCC peripheral clock enabling */ \
01544                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
01545                                         UNUSED(tmpreg); \
01546                                        } while(0)
01547
01548 #define __HAL_RCC_I2C4_CLK_ENABLE()   do { \
01549                                         __IO uint32_t tmpreg; \
01550                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
01551                                         /* Delay after an RCC peripheral clock enabling */ \
01552                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
01553                                         UNUSED(tmpreg); \
01554                                        } while(0)
01555
01556 #define __HAL_RCC_LPTIM2_CLK_ENABLE()   do { \
01557                                         __IO uint32_t tmpreg; \
01558                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
01559                                         /* Delay after an RCC peripheral clock enabling */ \
01560                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
01561                                         UNUSED(tmpreg); \
01562                                        } while(0)
01563
01564 #define __HAL_RCC_LPTIM3_CLK_ENABLE()   do { \
01565                                         __IO uint32_t tmpreg; \
01566                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
01567                                         /* Delay after an RCC peripheral clock enabling */ \
01568                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
01569                                         UNUSED(tmpreg); \
01570                                        } while(0)
01571
01572 #define __HAL_RCC_LPTIM4_CLK_ENABLE()   do { \
01573                                         __IO uint32_t tmpreg; \
01574                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
01575                                         /* Delay after an RCC peripheral clock enabling */ \
01576                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
01577                                         UNUSED(tmpreg); \
01578                                        } while(0)
01579
01580 #define __HAL_RCC_LPTIM5_CLK_ENABLE()   do { \
01581                                         __IO uint32_t tmpreg; \
01582                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
01583                                         /* Delay after an RCC peripheral clock enabling */ \
01584                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
01585                                         UNUSED(tmpreg); \
01586                                        } while(0)
01587
01588 #define __HAL_RCC_COMP12_CLK_ENABLE()   do { \
01589                                         __IO uint32_t tmpreg; \
01590                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
01591                                         /* Delay after an RCC peripheral clock enabling */ \
01592                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
01593                                         UNUSED(tmpreg); \
01594                                        } while(0)
01595
01596 #define __HAL_RCC_VREF_CLK_ENABLE()   do { \
01597                                         __IO uint32_t tmpreg; \
01598                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
01599                                         /* Delay after an RCC peripheral clock enabling */ \
01600                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
01601                                         UNUSED(tmpreg); \
01602                                        } while(0)
01603
01604 #define __HAL_RCC_SAI4_CLK_ENABLE()   do { \
01605                                         __IO uint32_t tmpreg; \
01606                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
01607                                         /* Delay after an RCC peripheral clock enabling */ \
01608                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
01609                                         UNUSED(tmpreg); \
01610                                        } while(0)
01611
01612 #define __HAL_RCC_RTC_CLK_ENABLE()   do { \
01613                                         __IO uint32_t tmpreg; \
01614                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
01615                                         /* Delay after an RCC peripheral clock enabling */ \
01616                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
01617                                         UNUSED(tmpreg); \
01618                                        } while(0)
01619
01620
01621 #define __HAL_RCC_SYSCFG_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
01622 #define __HAL_RCC_LPUART1_CLK_DISABLE()          (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
01623 #define __HAL_RCC_SPI6_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
01624 #define __HAL_RCC_I2C4_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
01625 #define __HAL_RCC_LPTIM2_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
01626 #define __HAL_RCC_LPTIM3_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
01627 #define __HAL_RCC_LPTIM4_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
01628 #define __HAL_RCC_LPTIM5_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
01629 #define __HAL_RCC_COMP12_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
01630 #define __HAL_RCC_VREF_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
01631 #define __HAL_RCC_RTC_CLK_DISABLE()              (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
01632 #define __HAL_RCC_SAI4_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
01633
01634
01635
01636 /** @brief  Enable or disable the AHB3 peripheral reset.
01637   */
01638
01639 #define __HAL_RCC_AHB3_FORCE_RESET()          (RCC->AHB3RSTR = 0xFFFFFFFF)
01640 #define __HAL_RCC_MDMA_FORCE_RESET()            (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))
01641 #define __HAL_RCC_DMA2D_FORCE_RESET()           (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))
01642 #define __HAL_RCC_JPGDECRST_FORCE_RESET()       (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST))
01643 #define __HAL_RCC_FMC_FORCE_RESET()             (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
01644 #define __HAL_RCC_QSPI_FORCE_RESET()            (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
01645 #define __HAL_RCC_SDMMC1_FORCE_RESET()          (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST))
01646 #define __HAL_RCC_CPU_FORCE_RESET()            (RCC->AHB3RSTR |= (RCC_AHB3RSTR_CPURST))
01647
01648
01649 #define __HAL_RCC_AHB3_RELEASE_RESET()        (RCC->AHB3RSTR = 0x00)
01650 #define __HAL_RCC_MDMA_RELEASE_RESET()          (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))
01651 #define __HAL_RCC_DMA2D_RELEASE_RESET()         (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))
01652 #define __HAL_RCC_JPGDECRST_RELEASE_RESET()     (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST))
01653 #define __HAL_RCC_FMC_RELEASE_RESET()           (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))
01654 #define __HAL_RCC_QSPI_RELEASE_RESET()          (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST))
01655 #define __HAL_RCC_SDMMC1_RELEASE_RESET()        (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))
01656 #define __HAL_RCC_CPU_RELEASE_RESET()          (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_CPURST))
01657
01658
01659
01660 /** @brief  Force or release the AHB1 peripheral reset.
01661   */
01662 #define __HAL_RCC_AHB1_FORCE_RESET()           (RCC->AHB1RSTR = 0xFFFFFFFF)
01663 #define __HAL_RCC_DMA1_FORCE_RESET()             (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
01664 #define __HAL_RCC_DMA2_FORCE_RESET()             (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
01665 #define __HAL_RCC_ADC12_FORCE_RESET()            (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST))
01666 #define __HAL_RCC_ETH1MAC_FORCE_RESET()          (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST))
01667 #define __HAL_RCC_USB1_OTG_HS_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST))
01668 #define __HAL_RCC_USB2_OTG_FS_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST))
01669
01670
01671 #define __HAL_RCC_AHB1_RELEASE_RESET()           (RCC->AHB1RSTR = 0x00)
01672 #define __HAL_RCC_DMA1_RELEASE_RESET()             (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST))
01673 #define __HAL_RCC_DMA2_RELEASE_RESET()             (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST))
01674 #define __HAL_RCC_ADC12_RELEASE_RESET()            (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST))
01675 #define __HAL_RCC_ETH1MAC_RELEASE_RESET()          (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST))
01676 #define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()      (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST))
01677 #define __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()      (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST))
01678
01679
01680 /** @brief  Force or release the AHB2 peripheral reset.
01681   */
01682 #define __HAL_RCC_AHB2_FORCE_RESET()           (RCC->AHB2RSTR = 0xFFFFFFFF)
01683 #define __HAL_RCC_DCMI_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
01684 #define __HAL_RCC_CRYP_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
01685 #define __HAL_RCC_HASH_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
01686 #define __HAL_RCC_RNG_FORCE_RESET()              (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
01687 #define __HAL_RCC_SDMMC2_FORCE_RESET()           (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))
01688
01689 #define __HAL_RCC_AHB2_RELEASE_RESET()           (RCC->AHB2RSTR = 0x00)
01690 #define __HAL_RCC_DCMI_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST))
01691 #define __HAL_RCC_CRYP_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST))
01692 #define __HAL_RCC_HASH_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST))
01693 #define __HAL_RCC_RNG_RELEASE_RESET()              (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))
01694 #define __HAL_RCC_SDMMC2_RELEASE_RESET()           (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))
01695
01696
01697 /** @brief  Force or release the AHB4 peripheral reset.
01698   */
01699
01700 #define __HAL_RCC_AHB4_FORCE_RESET()          (RCC->AHB4RSTR = 0xFFFFFFFF)
01701 #define __HAL_RCC_GPIOA_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST)
01702 #define __HAL_RCC_GPIOB_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST)
01703 #define __HAL_RCC_GPIOC_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST)
01704 #define __HAL_RCC_GPIOD_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST)
01705 #define __HAL_RCC_GPIOE_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST)
01706 #define __HAL_RCC_GPIOF_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST)
01707 #define __HAL_RCC_GPIOG_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST)
01708 #define __HAL_RCC_GPIOH_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST)
01709 #define __HAL_RCC_GPIOI_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST)
01710 #define __HAL_RCC_GPIOJ_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST)
01711 #define __HAL_RCC_GPIOK_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST)
01712 #define __HAL_RCC_PWR_FORCE_RESET()             (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_PWRRST)
01713 #define __HAL_RCC_CRC_FORCE_RESET()             (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST)
01714 #define __HAL_RCC_BDMA_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST)
01715 #define __HAL_RCC_ADC3_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST)
01716 #define __HAL_RCC_HSEM_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST)
01717
01718 #define __HAL_RCC_AHB4_RELEASE_RESET()          (RCC->AHB4RSTR = 0x00)
01719 #define __HAL_RCC_GPIOA_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST)
01720 #define __HAL_RCC_GPIOB_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST)
01721 #define __HAL_RCC_GPIOC_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST)
01722 #define __HAL_RCC_GPIOD_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST)
01723 #define __HAL_RCC_GPIOE_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST)
01724 #define __HAL_RCC_GPIOF_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)
01725 #define __HAL_RCC_GPIOG_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)
01726 #define __HAL_RCC_GPIOH_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)
01727 #define __HAL_RCC_GPIOI_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST)
01728 #define __HAL_RCC_GPIOJ_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)
01729 #define __HAL_RCC_GPIOK_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)
01730 #define __HAL_RCC_PWR_RELEASE_RESET()             (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_PWRRST)
01731 #define __HAL_RCC_CRC_RELEASE_RESET()             (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST)
01732 #define __HAL_RCC_BDMA_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST)
01733 #define __HAL_RCC_ADC3_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST)
01734 #define __HAL_RCC_HSEM_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST)
01735
01736
01737 /** @brief  Force or release the APB3 peripheral reset.
01738   */
01739 #define __HAL_RCC_APB3_FORCE_RESET()         (RCC->APB3RSTR = 0xFFFFFFFF)
01740 #define __HAL_RCC_LTDC_FORCE_RESET()           (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST)
01741
01742 #define __HAL_RCC_APB3_RELEASE_RESET()         (RCC->APB3RSTR = 0x00)
01743 #define __HAL_RCC_LTDC_RELEASE_RESET()           (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST)
01744
01745
01746 /** @brief  Force or release the APB1 peripheral reset.
01747   */
01748 #define __HAL_RCC_APB1L_FORCE_RESET()        (RCC->APB1LRSTR = 0xFFFFFFFF)
01749 #define __HAL_RCC_APB1H_FORCE_RESET()        (RCC->APB1HRSTR = 0xFFFFFFFF)
01750 #define __HAL_RCC_TIM2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST)
01751 #define __HAL_RCC_TIM3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST)
01752 #define __HAL_RCC_TIM4_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST)
01753 #define __HAL_RCC_TIM5_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST)
01754 #define __HAL_RCC_TIM6_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST)
01755 #define __HAL_RCC_TIM7_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST)
01756 #define __HAL_RCC_TIM12_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST)
01757 #define __HAL_RCC_TIM13_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST)
01758 #define __HAL_RCC_TIM14_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST)
01759 #define __HAL_RCC_LPTIM1_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST)
01760 #define __HAL_RCC_SPI2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST)
01761 #define __HAL_RCC_SPI3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST)
01762 #define __HAL_RCC_SPDIFRX_FORCE_RESET()        (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST)
01763 #define __HAL_RCC_USART2_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST)
01764 #define __HAL_RCC_USART3_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST)
01765 #define __HAL_RCC_UART4_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST)
01766 #define __HAL_RCC_UART5_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST)
01767 #define __HAL_RCC_I2C1_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST)
01768 #define __HAL_RCC_I2C2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST)
01769 #define __HAL_RCC_I2C3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST)
01770 #define __HAL_RCC_CEC_FORCE_RESET()            (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST)
01771 #define __HAL_RCC_DAC12_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST)
01772 #define __HAL_RCC_UART7_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST)
01773 #define __HAL_RCC_UART8_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST)
01774 #define __HAL_RCC_CRS_FORCE_RESET()            (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST)
01775 #define __HAL_RCC_SWPMI1_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST)
01776 #define __HAL_RCC_OPAMP_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST)
01777 #define __HAL_RCC_MDIOS_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST)
01778 #define __HAL_RCC_FDCAN_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST)
01779
01780 #define __HAL_RCC_APB1L_RELEASE_RESET()       (RCC->APB1LRSTR = 0x00)
01781 #define __HAL_RCC_APB1H_RELEASE_RESET()       (RCC->APB1HRSTR = 0x00)
01782 #define __HAL_RCC_TIM2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST)
01783 #define __HAL_RCC_TIM3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST)
01784 #define __HAL_RCC_TIM4_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST)
01785 #define __HAL_RCC_TIM5_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST)
01786 #define __HAL_RCC_TIM6_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST)
01787 #define __HAL_RCC_TIM7_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST)
01788 #define __HAL_RCC_TIM12_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST)
01789 #define __HAL_RCC_TIM13_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST)
01790 #define __HAL_RCC_TIM14_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST)
01791 #define __HAL_RCC_LPTIM1_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST)
01792 #define __HAL_RCC_SPI2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST)
01793 #define __HAL_RCC_SPI3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST)
01794 #define __HAL_RCC_SPDIFRX_RELEASE_RESET()        (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST)
01795 #define __HAL_RCC_USART2_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)
01796 #define __HAL_RCC_USART3_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST)
01797 #define __HAL_RCC_UART4_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST)
01798 #define __HAL_RCC_UART5_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST)
01799 #define __HAL_RCC_I2C1_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)
01800 #define __HAL_RCC_I2C2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)
01801 #define __HAL_RCC_I2C3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)
01802 #define __HAL_RCC_CEC_RELEASE_RESET()            (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)
01803 #define __HAL_RCC_DAC12_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)
01804 #define __HAL_RCC_UART7_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)
01805 #define __HAL_RCC_UART8_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST)
01806 #define __HAL_RCC_CRS_RELEASE_RESET()            (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST)
01807 #define __HAL_RCC_SWPMI1_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST)
01808 #define __HAL_RCC_OPAMP_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)
01809 #define __HAL_RCC_MDIOS_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)
01810 #define __HAL_RCC_FDCAN_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)
01811
01812 /** @brief  Force or release the APB2 peripheral reset.
01813   */
01814 #define __HAL_RCC_APB2_FORCE_RESET()         (RCC->APB2RSTR = 0xFFFFFFFF)
01815 #define __HAL_RCC_TIM1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST)
01816 #define __HAL_RCC_TIM8_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST)
01817 #define __HAL_RCC_USART1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST)
01818 #define __HAL_RCC_USART6_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST)
01819 #define __HAL_RCC_SPI1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST)
01820 #define __HAL_RCC_SPI4_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST)
01821 #define __HAL_RCC_TIM15_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST)
01822 #define __HAL_RCC_TIM16_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST)
01823 #define __HAL_RCC_TIM17_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST)
01824 #define __HAL_RCC_SPI5_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST)
01825 #define __HAL_RCC_SAI1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST)
01826 #define __HAL_RCC_SAI2_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST)
01827 #define __HAL_RCC_SAI3_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST)
01828 #define __HAL_RCC_DFSDM1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST)
01829 #define __HAL_RCC_HRTIM1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST)
01830
01831 #define __HAL_RCC_APB2_RELEASE_RESET()         (RCC->APB2RSTR = 0x00)
01832 #define __HAL_RCC_TIM1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST)
01833 #define __HAL_RCC_TIM8_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST)
01834 #define __HAL_RCC_USART1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST)
01835 #define __HAL_RCC_USART6_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST)
01836 #define __HAL_RCC_SPI1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST)
01837 #define __HAL_RCC_SPI4_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST)
01838 #define __HAL_RCC_TIM15_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST)
01839 #define __HAL_RCC_TIM16_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST)
01840 #define __HAL_RCC_TIM17_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)
01841 #define __HAL_RCC_SPI5_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)
01842 #define __HAL_RCC_SAI1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)
01843 #define __HAL_RCC_SAI2_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST)
01844 #define __HAL_RCC_SAI3_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST)
01845 #define __HAL_RCC_DFSDM1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST)
01846 #define __HAL_RCC_HRTIM1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST)
01847
01848 /** @brief  Force or release the APB4 peripheral reset.
01849   */
01850
01851 #define __HAL_RCC_APB4_FORCE_RESET()           (RCC->APB4RSTR = 0xFFFFFFFF)
01852 #define __HAL_RCC_SYSCFG_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST)
01853 #define __HAL_RCC_LPUART1_FORCE_RESET()          (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST)
01854 #define __HAL_RCC_SPI6_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST)
01855 #define __HAL_RCC_I2C4_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST)
01856 #define __HAL_RCC_LPTIM2_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST)
01857 #define __HAL_RCC_LPTIM3_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST)
01858 #define __HAL_RCC_LPTIM4_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST)
01859 #define __HAL_RCC_LPTIM5_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST)
01860 #define __HAL_RCC_COMP12_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST)
01861 #define __HAL_RCC_VREF_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST)
01862 #define __HAL_RCC_SAI4_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST)
01863
01864
01865 #define __HAL_RCC_APB4_RELEASE_RESET()           (RCC->APB4RSTR = 0x00)
01866 #define __HAL_RCC_SYSCFG_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST)
01867 #define __HAL_RCC_LPUART1_RELEASE_RESET()          (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST)
01868 #define __HAL_RCC_SPI6_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST)
01869 #define __HAL_RCC_I2C4_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST)
01870 #define __HAL_RCC_LPTIM2_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST)
01871 #define __HAL_RCC_LPTIM3_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST)
01872 #define __HAL_RCC_LPTIM4_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST)
01873 #define __HAL_RCC_LPTIM5_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST)
01874 #define __HAL_RCC_COMP12_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST)
01875 #define __HAL_RCC_VREF_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST)
01876 #define __HAL_RCC_SAI4_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST)
01877
01878
01879 /** @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
01880   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01881   *         power consumption.
01882   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01883   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01884   */
01885
01886
01887 #define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
01888 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
01889 #define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
01890 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
01891 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()             (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
01892 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
01893 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
01894 #define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
01895 #define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
01896 #define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
01897 #define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
01898
01899
01900 #define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
01901 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
01902 #define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
01903 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
01904 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()             (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
01905 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
01906 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
01907 #define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
01908 #define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
01909 #define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
01910 #define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
01911
01912
01913
01914 /** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
01915   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01916   *         power consumption.
01917   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
01918   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
01919   */
01920
01921 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()             (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
01922 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()             (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
01923 #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE()            (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
01924 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
01925 #define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE()           (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
01926 #define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE()           (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
01927 #define __HAL_RCC_ETH1PTP_CLK_SLEEP_ENABLE()          (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1PTPLPEN))
01928 #define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
01929 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
01930 #define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
01931 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
01932
01933 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()             (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
01934 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()             (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
01935 #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE()            (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
01936 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
01937 #define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE()           (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
01938 #define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE()           (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
01939 #define __HAL_RCC_ETH1PTP_CLK_SLEEP_DISABLE()          (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1PTPLPEN))
01940 #define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
01941 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
01942 #define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
01943 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
01944
01945 /** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
01946   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01947   *         power consumption.
01948   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
01949   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
01950   */
01951
01952 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
01953 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
01954 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
01955 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()              (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
01956 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE()           (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
01957 #define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
01958 #define __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
01959 #define __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
01960
01961 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
01962 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
01963 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
01964 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()              (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
01965 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE()           (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
01966 #define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
01967 #define __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
01968 #define __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
01969
01970 /** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
01971   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01972   *         power consumption.
01973   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
01974   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
01975   */
01976
01977 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
01978 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
01979 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
01980 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
01981 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
01982 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
01983 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
01984 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
01985 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
01986 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
01987 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
01988 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()             (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_PWRLPEN)
01989 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()             (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
01990 #define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
01991 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
01992 #define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE()          (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
01993 #define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))
01994
01995 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
01996 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
01997 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
01998 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
01999 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
02000 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
02001 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
02002 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
02003 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
02004 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
02005 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
02006 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()             (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_PWRLPEN)
02007 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()             (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
02008 #define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
02009 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
02010 #define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE()          (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
02011 #define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
02012
02013 /** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
02014   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02015   *         power consumption.
02016   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
02017   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
02018   */
02019
02020 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE()           (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
02021 #define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE()          (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
02022
02023 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE()           (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
02024
02025 #define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE()          (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
02026
02027 /** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
02028   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02029   *         power consumption.
02030   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
02031   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
02032   */
02033
02034 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
02035 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
02036 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
02037 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
02038 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
02039 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
02040 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
02041 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
02042 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
02043 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
02044
02045
02046 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
02047 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
02048 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
02049 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
02050 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
02051 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
02052 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
02053 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
02054 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
02055 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
02056 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE()            (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
02057 #define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
02058 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
02059 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
02060 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE()            (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
02061 #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
02062 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
02063 #define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
02064 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
02065
02066
02067 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
02068 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
02069 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
02070 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
02071 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
02072 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
02073 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
02074 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
02075 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
02076 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
02077
02078
02079 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
02080 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
02081 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
02082 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
02083 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
02084 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
02085 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
02086 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
02087 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
02088 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
02089 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()            (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
02090 #define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
02091 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
02092 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
02093 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE()            (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
02094 #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
02095 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
02096 #define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
02097 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
02098
02099 /** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
02100   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02101   *         power consumption.
02102   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
02103   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
02104   */
02105
02106 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
02107 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
02108 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
02109 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
02110 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
02111 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
02112 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
02113 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
02114 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
02115 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
02116 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
02117 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
02118 #define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
02119 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
02120 #define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
02121
02122 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
02123 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
02124 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
02125 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
02126 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
02127 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
02128 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
02129 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
02130 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
02131 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
02132 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
02133 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
02134 #define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
02135 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
02136 #define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
02137
02138 /** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
02139   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02140   *         power consumption.
02141   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
02142   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
02143   */
02144
02145 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
02146 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()          (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
02147 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
02148 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
02149 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
02150 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
02151 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
02152 #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
02153 #define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
02154 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
02155 #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE()              (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
02156 #define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
02157
02158
02159 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
02160 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE()          (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
02161 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
02162 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
02163 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
02164 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
02165 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
02166 #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
02167 #define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
02168 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
02169 #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE()              (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
02170 #define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
02171
02172
02173
02174 /** @brief  Enable or disable peripheral bus clock  when D3 domain is in DRUN
02175   * @note   After reset, peripheral  clock is disabled when CPU is in CSTOP
02176   */
02177
02178 #define __HAL_RCC_BDMA_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN)
02179 #define __HAL_RCC_LPUART1_CLKAM_ENABLE()          (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN)
02180 #define __HAL_RCC_SPI6_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN)
02181 #define __HAL_RCC_I2C4_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN)
02182 #define __HAL_RCC_LPTIM2_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN)
02183 #define __HAL_RCC_LPTIM3_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN)
02184 #define __HAL_RCC_LPTIM4_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN)
02185 #define __HAL_RCC_LPTIM5_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN)
02186 #define __HAL_RCC_COMP12_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN)
02187 #define __HAL_RCC_VREF_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN)
02188 #define __HAL_RCC_RTC_CLKAM_ENABLE()              (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN)
02189 #define __HAL_RCC_CRC_CLKAM_ENABLE()              (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN)
02190 #define __HAL_RCC_SAI4_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN)
02191 #define __HAL_RCC_ADC3_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN)
02192
02193
02194 #define __HAL_RCC_BKPRAM_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN)
02195 #define __HAL_RCC_D3SRAM1_CLKAM_ENABLE()          (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN)
02196
02197 #define __HAL_RCC_BDMA_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN)
02198 #define __HAL_RCC_LPUART1_CLKAM_DISABLE()          (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN)
02199 #define __HAL_RCC_SPI6_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN)
02200 #define __HAL_RCC_I2C4_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN)
02201 #define __HAL_RCC_LPTIM2_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN)
02202 #define __HAL_RCC_LPTIM3_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN)
02203 #define __HAL_RCC_LPTIM4_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN)
02204 #define __HAL_RCC_LPTIM5_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN)
02205 #define __HAL_RCC_COMP12_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN)
02206 #define __HAL_RCC_VREF_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN)
02207 #define __HAL_RCC_RTC_CLKAM_DISABLE()              (RCC->D3AMR) &= ~(RCC_D3AMR_RTCAMEN)
02208 #define __HAL_RCC_CRC_CLKAM_DISABLE()              (RCC->D3AMR) &= ~(RCC_D3AMR_CRCAMEN)
02209 #define __HAL_RCC_SAI4_CLKAM_DISABLE()             (RCC->D3AMR) &= ~(RCC_D3AMR_SAI4AMEN)
02210 #define __HAL_RCC_ADC3_CLKAM_DISABLE()             (RCC->D3AMR) &= ~(RCC_D3AMR_ADC3AMEN)
02211
02212
02213 #define __HAL_RCC_BKPRAM_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN)
02214 #define __HAL_RCC_D3SRAM1_CLKAM_DISABLE()          (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN)
02215
02216
02217 /** @brief  Macro to enable or disable the Internal High Speed oscillator (HSI).
02218   * @note     After enabling the HSI, the application software should wait on
02219   *           HSIRDY flag to be set indicating that HSI clock is stable and can
02220   *           be used to clock the PLL and/or system clock.
02221   * @note     HSI can not be stopped if it is used directly or through the PLL
02222   *           as system clock. In this case, you have to select another source
02223   *           of the system clock then stop the HSI.
02224   * @note     The HSI is stopped by hardware when entering STOP and STANDBY modes.
02225   * @param    __STATE__ specifies the new state of the HSI.
02226   *           This parameter can be one of the following values:
02227   *            @arg RCC_HSI_OFF turn OFF the HSI oscillator
02228   *            @arg RCC_HSI_ON turn ON the HSI oscillator
02229   *            @arg RCC_HSI_DIV1 turn ON the HSI oscillator and divide it by 1 (default after reset)
02230   *            @arg RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2
02231   *            @arg RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4
02232   *            @arg RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8
02233   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
02234   *         clock cycles.
02235   */
02236 #define __HAL_RCC_HSI_CONFIG(__STATE__) \
02237                   MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__))
02238
02239
02240 /** @brief  Macro to get the HSI divider.
02241   * @retval The HSI divider. The returned value can be one
02242   *         of the following:
02243   *            - RCC_CR_HSIDIV_1  HSI oscillator divided by 1 (default after reset)
02244   *            - RCC_CR_HSIDIV_2  HSI oscillator divided by 2
02245   *            - RCC_CR_HSIDIV_4  HSI oscillator divided by 4
02246   *            - RCC_CR_HSIDIV_8  HSI oscillator divided by 8
02247   */
02248 #define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))
02249
02250 /** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
02251   * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
02252   *         It is used (enabled by hardware) as system clock source after start-up
02253   *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
02254   *         of the HSE used directly or indirectly as system clock (if the Clock
02255   *         Security System CSS is enabled).
02256   * @note   HSI can not be stopped if it is used as system clock source. In this case,
02257   *         you have to select another source of the system clock then stop the HSI.
02258   * @note   After enabling the HSI, the application software should wait on HSIRDY
02259   *         flag to be set indicating that HSI clock is stable and can be used as
02260   *         system clock source.
02261   *         This parameter can be: ENABLE or DISABLE.
02262   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
02263   *         clock cycles.
02264   */
02265 #define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)
02266 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
02267
02268
02269 /** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
02270   * @note   The calibration is used to compensate for the variations in voltage
02271   *         and temperature that influence the frequency of the internal HSI RC.
02272   * @param  __HSICalibrationValue__: specifies the calibration trimming value.
02273   *         This parameter must be a number between 0 and 0x3F.
02274   */
02275 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
02276                   MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_ICSCR_HSITRIM))
02277
02278 /**
02279   * @brief    Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
02280   *           in STOP mode to be quickly available as kernel clock for some peripherals.
02281   * @note     Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
02282   *           speed because of the HSI start-up time.
02283   * @note     The enable of this function has not effect on the HSION bit.
02284   *           This parameter can be: ENABLE or DISABLE.
02285   * @retval None
02286   */
02287 #define __HAL_RCC_HSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_HSIKERON)
02288 #define __HAL_RCC_HSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
02289
02290
02291 /**
02292   * @brief  Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
02293   * @note   After enabling the HSI48, the application software should wait on
02294   *         HSI48RDY flag to be set indicating that HSI48 clock is stable and can
02295   *         be used to clock the USB.
02296   * @note   The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
02297   */
02298 #define __HAL_RCC_HSI48_ENABLE()    SET_BIT(RCC->CR, RCC_CR_HSI48ON);
02299
02300 #define __HAL_RCC_HSI48_DISABLE()   CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
02301
02302 /**
02303   * @brief  Macros to enable or disable the Internal  oscillator (CSI).
02304   * @note     The CSI is stopped by hardware when entering STOP and STANDBY modes.
02305   *           It is used (enabled by hardware) as system clock source after
02306   *           start-up from Reset, wakeup from STOP and STANDBY mode, or in case
02307   *           of failure of the HSE used directly or indirectly as system clock
02308   *           (if the Clock Security System CSS is enabled).
02309   * @note     CSI can not be stopped if it is used as system clock source.
02310   *           In this case, you have to select another source of the system
02311   *           clock then stop the CSI.
02312   * @note     After enabling the CSI, the application software should wait on
02313   *           CSIRDY flag to be set indicating that CSI clock is stable and can
02314   *           be used as system clock source.
02315   * @note     When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator
02316   *           clock cycles.
02317   */
02318 #define __HAL_RCC_CSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_CSION)
02319 #define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION)
02320
02321 /** @brief  Macro Adjusts the Internal  oscillator (CSI) calibration value.
02322   * @note   The calibration is used to compensate for the variations in voltage
02323   *         and temperature that influence the frequency of the internal CSI RC.
02324   * @param  __CSICalibrationValue__: specifies the calibration trimming value.
02325   *         This parameter must be a number between 0 and 0x1F.
02326   */
02327 #define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \
02328                   MODIFY_REG(RCC->ICSCR, RCC_ICSCR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << POSITION_VAL(RCC_ICSCR_CSITRIM))
02329
02330 /**
02331   * @brief    Macros to enable or disable the force of the Low-power Internal oscillator (CSI)
02332   *           in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
02333   * @note     Keeping the CSI ON in STOP mode allows to avoid slowing down the communication
02334   *           speed because of the CSI start-up time.
02335   * @note     The enable of this function has not effect on the CSION bit.
02336   *           This parameter can be: ENABLE or DISABLE.
02337   * @retval None
02338   */
02339 #define __HAL_RCC_CSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_CSIKERON)
02340 #define __HAL_RCC_CSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)
02341
02342
02343 /** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
02344   * @note   After enabling the LSI, the application software should wait on
02345   *         LSIRDY flag to be set indicating that LSI clock is stable and can
02346   *         be used to clock the IWDG and/or the RTC.
02347   * @note   LSI can not be disabled if the IWDG is running.
02348   * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
02349   *         clock cycles.
02350   */
02351 #define __HAL_RCC_LSI_ENABLE()         SET_BIT(RCC->CSR, RCC_CSR_LSION)
02352 #define __HAL_RCC_LSI_DISABLE()        CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
02353
02354 /**
02355   * @brief  Macro to configure the External High Speed oscillator (__HSE__).
02356   * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
02357   *         software should wait on HSERDY flag to be set indicating that HSE clock
02358   *         is stable and can be used to clock the PLL and/or system clock.
02359   * @note   HSE state can not be changed if it is used directly or through the
02360   *         PLL as system clock. In this case, you have to select another source
02361   *         of the system clock then change the HSE state (ex. disable it).
02362   * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
02363   * @note   This function reset the CSSON bit, so if the clock security system(CSS)
02364   *         was previously enabled you have to enable it again after calling this
02365   *         function.
02366   * @param  __STATE__: specifies the new state of the HSE.
02367   *         This parameter can be one of the following values:
02368   *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
02369   *                              6 HSE oscillator clock cycles.
02370   *            @arg RCC_HSE_ON: turn ON the HSE oscillator.
02371   *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
02372   */
02373 #define __HAL_RCC_HSE_CONFIG(__STATE__)                         \
02374                     do {                                        \
02375                       if ((__STATE__) == RCC_HSE_ON)            \
02376                       {                                         \
02377                         SET_BIT(RCC->CR, RCC_CR_HSEON);         \
02378                       }                                         \
02379                       else if ((__STATE__) == RCC_HSE_OFF)      \
02380                       {                                         \
02381                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
02382                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
02383                       }                                         \
02384                       else if ((__STATE__) == RCC_HSE_BYPASS)   \
02385                       {                                         \
02386                         SET_BIT(RCC->CR, RCC_CR_HSEBYP);        \
02387                         SET_BIT(RCC->CR, RCC_CR_HSEON);         \
02388                       }                                         \
02389                       else                                      \
02390                       {                                         \
02391                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
02392                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
02393                       }                                         \
02394                     } while(0)
02395
02396 /** @defgroup RCC_LSE_Configuration LSE Configuration
02397   * @{
02398   */
02399
02400 /**
02401   * @brief  Macro to configure the External Low Speed oscillator (LSE).
02402   * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
02403   *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.
02404   * @note   As the LSE is in the Backup domain and write access is denied to
02405   *         this domain after reset, you have to enable write access using
02406   *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
02407   *         (to be done once after reset).
02408   * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
02409   *         software should wait on LSERDY flag to be set indicating that LSE clock
02410   *         is stable and can be used to clock the RTC.
02411   * @param  __STATE__: specifies the new state of the LSE.
02412   *         This parameter can be one of the following values:
02413   *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
02414   *                              6 LSE oscillator clock cycles.
02415   *            @arg RCC_LSE_ON: turn ON the LSE oscillator.
02416   *            @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
02417   */
02418 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
02419                     do {                                       \
02420                       if((__STATE__) == RCC_LSE_ON)            \
02421                       {                                        \
02422                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
02423                       }                                        \
02424                       else if((__STATE__) == RCC_LSE_OFF)      \
02425                       {                                        \
02426                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
02427                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
02428                       }                                        \
02429                       else if((__STATE__) == RCC_LSE_BYPASS)   \
02430                       {                                        \
02431                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \
02432                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
02433                       }                                        \
02434                       else                                     \
02435                       {                                        \
02436                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
02437                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
02438                       }                                        \
02439                     } while(0)
02440 /**
02441   * @}
02442   */
02443
02444 /** @brief  Macros to enable or disable the the RTC clock.
02445   * @note   These macros must be used only after the RTC clock source was selected.
02446   */
02447 #define __HAL_RCC_RTC_ENABLE()         SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
02448 #define __HAL_RCC_RTC_DISABLE()        CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
02449
02450 /** @brief  Macros to configure the RTC clock (RTCCLK).
02451   * @note   As the RTC clock configuration bits are in the Backup domain and write
02452   *         access is denied to this domain after reset, you have to enable write
02453   *         access using the Power Backup Access macro before to configure
02454   *         the RTC clock source (to be done once after reset).
02455   * @note   Once the RTC clock is configured it can't be changed unless the
02456   *         Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
02457   *         a Power On Reset (POR).
02458   * @param  __RTCCLKSource__: specifies the RTC clock source.
02459   *         This parameter can be one of the following values:
02460   *            @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
02461   *            @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
02462   *            @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
02463   *                                            as RTC clock, where x:[2,31]
02464   * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
02465   *         work in STOP and STANDBY modes, and can be used as wakeup source.
02466   *         However, when the HSE clock is used as RTC clock source, the RTC
02467   *         cannot be used in STOP and STANDBY modes.
02468   * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
02469   *         RTC clock source).
02470   */
02471 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \
02472                                                  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFF) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
02473
02474 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
02475                                                     RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF);  \
02476                                                    } while (0)
02477
02478 #define  __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
02479
02480
02481 /** @brief  Macros to force or release the Backup domain reset.
02482   * @note   This function resets the RTC peripheral (including the backup registers)
02483   *         and the RTC clock source selection in RCC_CSR register.
02484   * @note   The BKPSRAM is not affected by this reset.
02485   */
02486 #define __HAL_RCC_BACKUPRESET_FORCE()   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
02487 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
02488
02489 /** @brief  Macros to enable or disable the main PLL.
02490   * @note   After enabling the main PLL, the application software should wait on
02491   *         PLLRDY flag to be set indicating that PLL clock is stable and can
02492   *         be used as system clock source.
02493   * @note   The main PLL can not be disabled if it is used as system clock source
02494   * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
02495   */
02496 #define __HAL_RCC_PLL_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL1ON)
02497 #define __HAL_RCC_PLL_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)
02498
02499 /**
02500   * @brief  Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)
02501   * @note   Enabling/disabling  Those Clocks can be any time  without the need to stop the PLL,
02502   *        (except the ck_pll_p of the System PLL that cannot be stopped if used as System
02503   *         Clock.This is mainly used to save Power.
02504   * @param  __RCC_PLL1ClockOut__: specifies the PLL clock to be outputted
02505   *          This parameter can be one of the following values:
02506   *            @arg RCC_PLL1_DIVP: This clock is used to generate system clock (up to 400MHZ)
02507   *            @arg RCC_PLL1_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ)
02508   *            @arg RCC_PLL1_DIVR: This clock is used to generate peripherals clock (up to 400MHZ)
02509   * @retval None
02510   */
02511 #define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
02512
02513 #define __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
02514
02515
02516 /**
02517   * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO
02518   * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL1
02519   * @retval None
02520   */
02521 #define __HAL_RCC_PLLFRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
02522
02523 #define __HAL_RCC_PLLFRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
02524
02525
02526 /**
02527   * @brief  Macro to configures the main PLL clock source, multiplication and division factors.
02528   * @note   This function must be used only when the main PLL is disabled.
02529   *
02530   * @param  __RCC_PLLSOURCE__: specifies the PLL entry clock source.
02531   *          This parameter can be one of the following values:
02532   *            @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
02533   *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
02534   *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
02535   * @note   This clock source (__RCC_PLLSource__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 .
02536   *
02537   * @param  __PLLM1__: specifies the division factor for PLL VCO input clock
02538   *          This parameter must be a number between 1 and 63.
02539   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
02540   *         frequency ranges from 1 to 16 MHz.
02541   *
02542   * @param  __PLLN1__: specifies the multiplication factor for PLL VCO output clock
02543   *          This parameter must be a number between 4 and 512.
02544   * @note   You have to set the PLLN parameter correctly to ensure that the VCO
02545   *         output frequency is between 150 and 420 MHz (when in medium VCO range) or
02546   *         between 192 and 836 MHZ (when in wide VCO range)
02547   *
02548   * @param  __PLLP1__: specifies the division factor for system  clock.
02549   *          This parameter must be a number between 2 and 128 (where odd numbers not allowed)
02550   *
02551   * @param  __PLLQ1__: specifies the division factor for peripheral kernel clocks
02552   *          This parameter must be a number between 1 and 128
02553   *
02554   * @param  __PLLR1__: specifies the division factor for peripheral kernel clocks
02555   *          This parameter must be a number between 1 and 128
02556   *
02557   * @retval None
02558   */
02559
02560
02561 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \
02562                   do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U)));  \
02563                       WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \
02564                                 ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \
02565                     } while(0)
02566
02567
02568 /** @brief  Macro to configure the PLLs clock source.
02569   * @note   This function must be used only when all PLLs are disabled.
02570   * @param  __PLLSOURCE__: specifies the PLLs entry clock source.
02571   *         This parameter can be one of the following values:
02572   *            @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
02573   *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
02574   *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
02575   *
02576   */
02577 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))
02578
02579
02580 /**
02581   * @brief  Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor
02582   *
02583   * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO
02584   *
02585   * @param  __RCC_PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO
02586   *                            It should be a value between 0 and 8191
02587   * @note   Warning: The software has to set correctly these bits to insure that the VCO
02588   *                  output frequency is between its valid frequency range, which is:
02589   *                   192 to 836 MHz if PLL1VCOSEL = 0
02590   *                   150 to 420 MHz if PLL1VCOSEL = 1.
02591   *
02592   *
02593   * @retval None
02594   */
02595  #define  __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << POSITION_VAL(RCC_PLL1FRACR_FRACN1))
02596
02597
02598 /** @brief  Macro to select  the PLL1  reference frequency range.
02599   * @param  __RCC_PLL1VCIRange__: specifies the PLL1 input frequency range
02600   *         This parameter can be one of the following values:
02601   *            @arg RCC_PLL1VCIRANGE_0: Range frequency is between 1 and 2 MHz
02602   *            @arg RCC_PLL1VCIRANGE_1: Range frequency is between 2 and 4 MHz
02603   *            @arg RCC_PLL1VCIRANGE_2: Range frequency is between 4 and 8 MHz
02604   *            @arg RCC_PLL1VCIRANGE_3: Range frequency is between 8 and 16 MHz
02605   * @retval None
02606   */
02607 #define __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) \
02608                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))
02609
02610
02611 /** @brief  Macro to select  the PLL1  reference frequency range.
02612   * @param  __RCC_PLL1VCORange__: specifies the PLL1 input frequency range
02613   *         This parameter can be one of the following values:
02614   *            @arg RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz
02615   *            @arg RCC_PLL1VCOMEDIUM: Range frequency is between 150 and 420 MHz
02616   * @retval None
02617   */
02618 #define __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) \
02619                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))
02620
02621
02622
02623 /** @brief  Macro to get the clock source used as system clock.
02624   * @retval The clock source used as system clock. The returned value can be one
02625   *         of the following:
02626   *              - RCC_CFGR_SWS_CSI: CSI used as system clock.
02627   *              - RCC_CFGR_SWS_HSI: HSI used as system clock.
02628   *              - RCC_CFGR_SWS_HSE: HSE used as system clock.
02629   *              - RCC_CFGR_SWS_PLL: PLL used as system clock.
02630   */
02631 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
02632
02633
02634 /**
02635   * @brief Macro to configure the system clock source.
02636   * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
02637   * This parameter can be one of the following values:
02638   *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
02639   *              - RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source.
02640   *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
02641   *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
02642   */
02643 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
02644
02645 /** @brief  Macro to get the oscillator used as PLL clock source.
02646   * @retval The oscillator used as PLL clock source. The returned value can be one
02647   *         of the following:
02648   *              - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
02649   *              - RCC_PLLSOURCE_CSI: CSI oscillator is used as PLL clock source.
02650   *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
02651   *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
02652   */
02653 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))
02654
02655 /**
02656   * @brief  Macro to configure the External Low Speed oscillator (LSE) drive capability.
02657   * @note   As the LSE is in the Backup domain and write access is denied to
02658   *         this domain after reset, you have to enable write access using
02659   *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
02660   *         (to be done once after reset).
02661   * @param  __LSEDRIVE__: specifies the new state of the LSE drive capability.
02662   *          This parameter can be one of the following values:
02663   *            @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
02664   *            @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
02665   *            @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
02666   *            @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
02667   * @retval None
02668   */
02669 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
02670                   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
02671 /**
02672   * @brief  Macro to configure the wake up from stop clock.
02673   * @param  __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop
02674   *         This parameter can be one of the following values:
02675   *            @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI selected as system clock source
02676   *            @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
02677   * @retval None
02678   */
02679 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) \
02680                   MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))
02681
02682 /**
02683   * @brief  Macro to configure the Kernel wake up from stop clock.
02684   * @param  __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop
02685   *         This parameter can be one of the following values:
02686   *            @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source
02687   *            @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source
02688   * @retval None
02689   */
02690 #define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \
02691                   MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))
02692
02693 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
02694   * @brief macros to manage the specified RCC Flags and interrupts.
02695   * @{
02696   */
02697 /** @brief  Enable RCC interrupt.
02698   * @param  __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
02699   *         This parameter can be any combination of the following values:
02700   *            @arg RCC_IT_LSIRDY: LSI ready interrupt
02701   *            @arg RCC_IT_LSERDY: LSE ready interrupt
02702   *            @arg RCC_IT_CSIRDY: HSI ready interrupt
02703   *            @arg RCC_IT_HSIRDY: HSI ready interrupt
02704   *            @arg RCC_IT_HSERDY: HSE ready interrupt
02705   *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
02706   *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
02707   *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
02708   *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
02709   *            @arg RCC_IT_LSECSS: Clock security system interrupt
02710   */
02711 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
02712
02713 /** @brief Disable RCC interrupt
02714   * @param  __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
02715   *         This parameter can be any combination of the following values:
02716   *            @arg RCC_IT_LSIRDY: LSI ready interrupt
02717   *            @arg RCC_IT_LSERDY: LSE ready interrupt
02718   *            @arg RCC_IT_CSIRDY: HSI ready interrupt
02719   *            @arg RCC_IT_HSIRDY: HSI ready interrupt
02720   *            @arg RCC_IT_HSERDY: HSE ready interrupt
02721   *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
02722   *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
02723   *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
02724   *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
02725   *            @arg RCC_IT_LSECSS: Clock security system interrupt
02726   */
02727 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
02728
02729 /** @brief  Clear the RCC's interrupt pending bits
02730   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
02731   *         This parameter can be any combination of the following values:
02732   *            @arg RCC_IT_LSIRDY: LSI ready interrupt
02733   *            @arg RCC_IT_LSERDY: LSE ready interrupt
02734   *            @arg RCC_IT_CSIRDY: CSI ready interrupt
02735   *            @arg RCC_IT_HSIRDY: HSI ready interrupt
02736   *            @arg RCC_IT_HSERDY: HSE ready interrupt
02737   *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
02738   *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
02739   *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
02740   *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
02741   *            @arg RCC_IT_HSECSS: HSE Clock Security interrupt
02742   *            @arg RCC_IT_LSECSS: Clock security system interrupt
02743   */
02744 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
02745
02746 /** @brief  Check the RCC's interrupt has occurred or not.
02747   * @param  __INTERRUPT__: specifies the RCC interrupt source to check.
02748   *         This parameter can be any combination of the following values:
02749   *            @arg RCC_IT_LSIRDY: LSI ready interrupt
02750   *            @arg RCC_IT_LSERDY: LSE ready interrupt
02751   *            @arg RCC_IT_CSIRDY: CSI ready interrupt
02752   *            @arg RCC_IT_HSIRDY: HSI ready interrupt
02753   *            @arg RCC_IT_HSERDY: HSE ready interrupt
02754   *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
02755   *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
02756   *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
02757   *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
02758   *            @arg RCC_IT_HSECSS: HSE Clock Security interrupt
02759   *            @arg RCC_IT_LSECSS: Clock security system interrupt
02760   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
02761   */
02762 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
02763
02764 /** @brief Set RMVF bit to clear the reset flags.
02765   */
02766 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF)
02767
02768
02769
02770 /** @brief  Check RCC flag is set or not.
02771   * @param  __FLAG__: specifies the flag to check.
02772   *         This parameter can be one of the following values:
02773   *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
02774   *            @arg RCC_FLAG_HSIDIV: HSI divider flag
02775   *            @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready
02776   *            @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready
02777   *            @arg RCC_FLAG_HSERDY:  HSE oscillator clock ready
02778   *            @arg RCC_FLAG_D1CKRDY:  Domain1 clock ready
02779   *            @arg RCC_FLAG_D2CKRDY:  Domain2 clock ready
02780   *            @arg RCC_FLAG_PLLRDY:  PLL1 clock ready
02781   *            @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
02782   *            @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
02783   *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
02784   *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
02785   *            @arg RCC_FLAG_RMVF:   Remove  reset Flag
02786   *            @arg RCC_FLAG_CPURST: CPU reset flag
02787   *            @arg RCC_FLAG_D1RST:  D1 domain power switch reset flag
02788   *            @arg RCC_FLAG_D2RST:  D2 domain power switch reset flag
02789   *            @arg RCC_FLAG_BORRST: BOR reset flag
02790   *            @arg RCC_FLAG_PINRST: Pin reset
02791   *            @arg RCC_FLAG_PORRST: POR/PDR  reset
02792   *            @arg RCC_FLAG_SFTRST: System reset from CPU reset flag
02793   *            @arg RCC_FLAG_BORRST:   D2 domain power switch reset flag
02794   *            @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset
02795   *            @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset
02796   *            @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag
02797   *            @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY flag
02798   * @retval The new state of __FLAG__ (TRUE or FALSE).
02799   */
02800 #define RCC_FLAG_MASK  ((uint8_t)0x1F)
02801 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR : \
02802 ((((__FLAG__) >> 5) == 3)? RCC->CSR : ((((__FLAG__) >> 5) == 4)? RCC->RSR :RCC->CIFR))))  & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
02803
02804
02805 /**
02806   * @}
02807   */
02808
02809 #define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> POSITION_VAL(RCC_PLLCKSELR_PLLSRC))
02810
02811 /**
02812   * @}
02813   */
02814
02815 /* Include RCC HAL Extension module */
02816 #include "stm32h7xx_hal_rcc_ex.h"
02817
02818 /* Exported functions --------------------------------------------------------*/
02819  /** @addtogroup RCC_Exported_Functions
02820   * @{
02821   */
02822
02823 /** @addtogroup RCC_Exported_Functions_Group1
02824   * @{
02825   */
02826 /* Initialization and de-initialization functions  ******************************/
02827 void HAL_RCC_DeInit(void);
02828 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
02829 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
02830
02831 /**
02832   * @}
02833   */
02834
02835 /** @addtogroup RCC_Exported_Functions_Group2
02836   * @{
02837   */
02838 /* Peripheral Control functions  ************************************************/
02839 void     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
02840 void     HAL_RCC_EnableCSS(void);
02841 void     HAL_RCC_DisableCSS(void);
02842 uint32_t HAL_RCC_GetSysClockFreq(void);
02843 uint32_t HAL_RCC_GetHCLKFreq(void);
02844 uint32_t HAL_RCC_GetPCLK1Freq(void);
02845 uint32_t HAL_RCC_GetPCLK2Freq(void);
02846 void     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
02847 void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
02848 /* CSS NMI IRQ handler */
02849 void     HAL_RCC_NMI_IRQHandler(void);
02850 /* User Callbacks in non blocking mode (IT mode) */
02851 void     HAL_RCC_CCSCallback(void);
02852
02853 /**
02854   * @}
02855   */
02856
02857 /**
02858   * @}
02859   */
02860
02861 /* Private types -------------------------------------------------------------*/
02862 /* Private variables ---------------------------------------------------------*/
02863 /* Private constants ---------------------------------------------------------*/
02864 /** @defgroup RCC_Private_Constants RCC Private Constants
02865   * @{
02866   */
02867
02868 #define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
02869 #define HSI_TIMEOUT_VALUE          ((uint32_t)2)    /* 2 ms */
02870 #define HSI48_TIMEOUT_VALUE        ((uint32_t)2)    /* 2 ms */
02871 #define CSI_TIMEOUT_VALUE          ((uint32_t)2)    /* 2 ms */
02872 #define LSI_TIMEOUT_VALUE          ((uint32_t)2)    /* 2 ms */
02873 #define PLL_TIMEOUT_VALUE          ((uint32_t)2)    /* 2 ms */
02874 #define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000) /* 5 s  */
02875 #define RCC_DBP_TIMEOUT_VALUE      ((uint32_t)100)
02876 #define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
02877
02878 /**
02879   * @}
02880   */
02881
02882 /* Private macros ------------------------------------------------------------*/
02883 /** @addtogroup RCC_Private_Macros RCC Private Macros
02884   * @{
02885   */
02886
02887 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
02888   * @{
02889   */
02890
02891 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE)                           || \
02892                                            (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
02893                                            (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
02894                                            (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \
02895                                            (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
02896                                            (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
02897                                            (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
02898
02899 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
02900                          ((HSE) == RCC_HSE_BYPASS))
02901
02902 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
02903                          ((LSE) == RCC_LSE_BYPASS))
02904
02905 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)    || \
02906                          ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \
02907                          ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8))
02908
02909 #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
02910
02911 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
02912
02913 #define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON))
02914
02915 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \
02916                          ((PLL) == RCC_PLL_ON))
02917
02918 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_CSI)  || \
02919                                   ((SOURCE) == RCC_PLLSOURCE_HSI)  || \
02920                                   ((SOURCE) == RCC_PLLSOURCE_NONE) || \
02921                                   ((SOURCE) == RCC_PLLSOURCE_HSE))
02922 #define IS_RCC_PLLM_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 63))
02923 #define IS_RCC_PLLN_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512))
02924 #define IS_RCC_PLLP_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
02925 #define IS_RCC_PLLQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
02926 #define IS_RCC_PLLR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
02927
02928 #define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \
02929                                          ((VALUE) == RCC_PLL1_DIVQ) || \
02930                                          ((VALUE) == RCC_PLL1_DIVR))
02931
02932 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 0x3F))
02933
02934 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \
02935                                      ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
02936                                      ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
02937                                      ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
02938
02939 #define IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1)   || ((SYSCLK) == RCC_SYSCLK_DIV2)   || \
02940                                ((SYSCLK) == RCC_SYSCLK_DIV4)   || ((SYSCLK) == RCC_SYSCLK_DIV8)   || \
02941                                ((SYSCLK) == RCC_SYSCLK_DIV16)  || ((SYSCLK) == RCC_SYSCLK_DIV64)  || \
02942                                ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \
02943                                ((SYSCLK) == RCC_SYSCLK_DIV512))
02944
02945
02946 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1)   || ((HCLK) == RCC_HCLK_DIV2)   || \
02947                            ((HCLK) == RCC_HCLK_DIV4)   || ((HCLK) == RCC_HCLK_DIV8)   || \
02948                            ((HCLK) == RCC_HCLK_DIV16)  || ((HCLK) == RCC_HCLK_DIV64)  || \
02949                            ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \
02950                            ((HCLK) == RCC_HCLK_DIV512))
02951
02952 #define IS_RCC_D1PCLK1(D1PCLK1) (((D1PCLK1) == RCC_APB3_DIV1) || ((D1PCLK1) == RCC_APB3_DIV2) || \
02953                                  ((D1PCLK1) == RCC_APB3_DIV4) || ((D1PCLK1) == RCC_APB3_DIV8) || \
02954                                  ((D1PCLK1) == RCC_APB3_DIV16))
02955
02956 #define IS_RCC_PCLK1(PCLK1) (((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \
02957                              ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \
02958                             ((PCLK1) == RCC_APB1_DIV16))
02959
02960 #define IS_RCC_PCLK2(PCLK2) (((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \
02961                              ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \
02962                              ((PCLK2) == RCC_APB2_DIV16))
02963
02964 #define IS_RCC_D3PCLK1(D3PCLK1) (((D3PCLK1) == RCC_APB4_DIV1) || ((D3PCLK1) == RCC_APB4_DIV2) || \
02965                                  ((D3PCLK1) == RCC_APB4_DIV4) || ((D3PCLK1) == RCC_APB4_DIV8) || \
02966                                  ((D3PCLK1) == RCC_APB4_DIV16))
02967
02968 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE)       || ((SOURCE) == RCC_RTCCLKSOURCE_LSI)       || \
02969                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3)  || \
02970                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5)  || \
02971                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7)  || \
02972                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9)  || \
02973                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
02974                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
02975                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
02976                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
02977                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
02978                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
02979                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
02980                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
02981                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
02982                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
02983                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \
02984                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \
02985                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \
02986                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \
02987                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \
02988                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \
02989                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \
02990                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \
02991                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \
02992                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \
02993                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \
02994                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \
02995                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \
02996                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \
02997                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \
02998                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \
02999                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63))
03000
03001 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
03002
03003 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE)       || \
03004                                    ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK)  || \
03005                                    ((SOURCE) == RCC_MCO1SOURCE_HSI48))
03006
03007 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK)    || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \
03008                                    ((SOURCE) == RCC_MCO2SOURCE_HSE)       || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)   || \
03009                                    ((SOURCE) == RCC_MCO2SOURCE_CSICLK)    || ((SOURCE) == RCC_MCO2SOURCE_LSICLK))
03010
03011 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2)   || \
03012                             ((DIV) == RCC_MCODIV_3)  || ((DIV) == RCC_MCODIV_4)   || \
03013                             ((DIV) == RCC_MCODIV_5)  || ((DIV) == RCC_MCODIV_6)   || \
03014                             ((DIV) == RCC_MCODIV_7)  || ((DIV) == RCC_MCODIV_8)   || \
03015                             ((DIV) == RCC_MCODIV_9)  || ((DIV) == RCC_MCODIV_10)  || \
03016                             ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12)  || \
03017                             ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14)  || \
03018                             ((DIV) == RCC_MCODIV_15))
03019
03020
03021 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \
03022                            ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
03023                            ((FLAG) == RCC_FLAG_D1CKRDY)   || ((FLAG) == RCC_FLAG_D2CKRDY) || \
03024                            ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \
03025                            ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \
03026                            ((FLAG) == RCC_FLAG_LSIRDY)    || ((FLAG) == RCC_FLAG_RMVF)    || \
03027                            ((FLAG) == RCC_FLAG_CPURST)    || ((FLAG) == RCC_FLAG_D1RST)   || \
03028                            ((FLAG) == RCC_FLAG_D2RST)     || ((FLAG) == RCC_FLAG_BORRST)  || \
03029                            ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \
03030                            ((FLAG) == RCC_FLAG_SFTRST)    || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
03031                            ((FLAG) == RCC_FLAG_WWDGR1ST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
03032                            ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV ))
03033
03034
03035 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0xFFF)
03036 #define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
03037
03038 #define IS_RCC_STOP_WAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \
03039                                          ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI))
03040
03041 #define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \
03042                                           ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI))
03043 /**
03044   * @}
03045   */
03046
03047 /**
03048   * @}
03049   */
03050
03051 /**
03052   * @}
03053   */
03054
03055 /**
03056   * @}
03057   */
03058 #ifdef __cplusplus
03059 }
03060 #endif
03061
03062 #endif /* __STM32H7xx_HAL_RCC_H */
03063
03064 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:39 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_rcc_ex.c Source File

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stm32h7xx_hal_rcc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rcc_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Extended RCC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities RCC extension peripheral:
00010   *           + Extended Peripheral Control functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00016   *
00017   * Redistribution and use in source and binary forms, with or without modification,
00018   * are permitted provided that the following conditions are met:
00019   *   1. Redistributions of source code must retain the above copyright notice,
00020   *      this list of conditions and the following disclaimer.
00021   *   2. Redistributions in binary form must reproduce the above copyright notice,
00022   *      this list of conditions and the following disclaimer in the documentation
00023   *      and/or other materials provided with the distribution.
00024   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00025   *      may be used to endorse or promote products derived from this software
00026   *      without specific prior written permission.
00027   *
00028   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00029   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00030   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00031   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00032   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00033   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00034   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00035   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00036   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00037   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00038   *
00039   ******************************************************************************
00040   */
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32h7xx_hal.h"
00044
00045 /** @addtogroup STM32H7xx_HAL_Driver
00046   * @{
00047   */
00048
00049 /** @defgroup RCCEx  RCCEx
00050   * @brief RCC HAL module driver
00051   * @{
00052   */
00053
00054 #ifdef HAL_RCC_MODULE_ENABLED
00055
00056 /* Private typedef -----------------------------------------------------------*/
00057 /* Private defines -----------------------------------------------------------*/
00058 /** @defgroup RCCEx_Private_defines Private Defines
00059  * @{
00060  */
00061 #define PLL2_TIMEOUT_VALUE         ((uint32_t)2)    /* 2 ms */
00062 #define PLL3_TIMEOUT_VALUE         ((uint32_t)2)    /* 2 ms */
00063 #define PLL_TIMEOUT_VALUE          ((uint32_t)2)    /* 2 ms */
00064
00065
00066 /**
00067   * @}
00068   */
00069
00070 /* Private macros ------------------------------------------------------------*/
00071 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
00072  * @{
00073  */
00074 /**
00075   * @}
00076   */
00077
00078 /* Private variables ---------------------------------------------------------*/
00079 /* Private function prototypes -----------------------------------------------*/
00080 static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2);
00081 static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3);
00082
00083
00084 /* Exported functions --------------------------------------------------------*/
00085
00086 /** @defgroup RCCEx_Exported_Functions Exported Functions
00087   * @{
00088   */
00089
00090 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
00091  *  @brief  Extended Peripheral Control functions
00092  *
00093 @verbatim
00094  ===============================================================================
00095                 ##### Extended Peripheral Control functions  #####
00096  ===============================================================================
00097     [..]
00098     This subsection provides a set of functions allowing to control the RCC Clocks
00099     frequencies.
00100     [..]
00101     (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
00102         select the RTC clock source; in this case the Backup domain will be reset in
00103         order to modify the RTC Clock source, as consequence RTC registers (including
00104         the backup registers) and RCC_BDCR register are set to their reset values.
00105
00106 @endverbatim
00107   * @{
00108   */
00109 /**
00110   * @brief  Initializes the RCC extended peripherals clocks according to the specified
00111   *         parameters in the RCC_PeriphCLKInitTypeDef.
00112   * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
00113   *         contains the configuration information for the Extended Peripherals
00114   *         clocks(SDMMC, CKPER, FMC, QSPI, DSI, SPI45, SPDIF, DFSDM1, FDCAN, SWPMI,SAI23, SAI1, SPI123,
00115   *         USART234578, USART16, RNG, HRTIM1, I2C123, USB,CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC,
00116   *         SAI4A,SAI4B,SPI6,RTC).
00117   * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
00118   *         the RTC clock source; in this case the Backup domain will be reset in
00119   *         order to modify the RTC Clock source, as consequence RTC registers (including
00120   *         the backup registers) are set to their reset values.
00121   *
00122   * @retval HAL status
00123   */
00124 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
00125 {
00126   uint32_t tmpreg = 0;
00127   uint32_t tickstart = 0;
00128   HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
00129   HAL_StatusTypeDef status = HAL_OK;   /* Final status */
00130
00131   /* Check the parameters */
00132   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
00133
00134   /*---------------------------- SPDIFRX configuration -------------------------------*/
00135
00136   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_SPDIFRX)
00137   {
00138
00139     switch(PeriphClkInit->SpdifrxClockSelection)
00140     {
00141     case RCC_SPDIFRXCLKSOURCE_PLL:      /* PLL is used as clock source for SPDIFRX*/
00142       /* Enable SAI Clock output generated form System PLL . */
00143       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00144
00145       /* SAI1 clock source configuration done later after clock selection check */
00146       break;
00147
00148     case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/
00149
00150       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
00151       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
00152
00153       /* SAI1 clock source configuration done later after clock selection check */
00154       break;
00155
00156     case RCC_SPDIFRXCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPDIFRX*/
00157       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
00158       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
00159
00160       /* SAI1 clock source configuration done later after clock selection check */
00161       break;
00162
00163     case RCC_SPDIFRXCLKSOURCE_HSI:
00164       /* Internal OSC clock is used as source of SPDIFRX clock*/
00165       /* SPDIFRX clock source configuration done later after clock selection check */
00166       break;
00167
00168     default:
00169       ret = HAL_ERROR;
00170       break;
00171     }
00172
00173     if(ret == HAL_OK)
00174     {
00175       /* Set the source of SPDIFRX clock*/
00176       __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
00177     }
00178     else
00179     {
00180       /* set overall return value */
00181       status = ret;
00182     }
00183   }
00184
00185   /*---------------------------- SAI1 configuration -------------------------------*/
00186   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_SAI1)
00187   {
00188     switch(PeriphClkInit->Sai1ClockSelection)
00189     {
00190     case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/
00191       /* Enable SAI Clock output generated form System PLL . */
00192       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00193
00194       /* SAI1 clock source configuration done later after clock selection check */
00195       break;
00196
00197     case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
00198
00199       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
00200       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
00201
00202       /* SAI1 clock source configuration done later after clock selection check */
00203       break;
00204
00205     case RCC_SAI1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI1*/
00206       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
00207       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
00208
00209       /* SAI1 clock source configuration done later after clock selection check */
00210       break;
00211
00212     case RCC_SAI1CLKSOURCE_PIN:
00213       /* External clock is used as source of SAI1 clock*/
00214       /* SAI1 clock source configuration done later after clock selection check */
00215       break;
00216
00217     case RCC_SAI1CLKSOURCE_CLKP:
00218       /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */
00219       /* SAI1 clock source configuration done later after clock selection check */
00220       break;
00221
00222     default:
00223       ret = HAL_ERROR;
00224       break;
00225     }
00226
00227     if(ret == HAL_OK)
00228     {
00229       /* Set the source of SAI1 clock*/
00230       __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
00231     }
00232     else
00233     {
00234       /* set overall return value */
00235       status = ret;
00236     }
00237   }
00238
00239   /*---------------------------- SAI2 configuration -------------------------------*/
00240   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_SAI2)
00241   {
00242     switch(PeriphClkInit->Sai2ClockSelection)
00243     {
00244     case RCC_SAI2CLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
00245       /* Enable SAI Clock output generated form System PLL . */
00246       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00247
00248       /* SAI1 clock source configuration done later after clock selection check */
00249       break;
00250
00251     case RCC_SAI2CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
00252
00253       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
00254       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
00255
00256       /* SAI2 clock source configuration done later after clock selection check */
00257       break;
00258
00259     case RCC_SAI2CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
00260       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
00261       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
00262
00263       /* SAI1 clock source configuration done later after clock selection check */
00264       break;
00265
00266     case RCC_SAI2CLKSOURCE_PIN:
00267       /* External clock is used as source of SAI2 clock*/
00268       /* SAI2 clock source configuration done later after clock selection check */
00269       break;
00270
00271     case RCC_SAI2CLKSOURCE_CLKP:
00272       /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
00273       /* SAI1 clock source configuration done later after clock selection check */
00274       break;
00275
00276     default:
00277       ret = HAL_ERROR;
00278       break;
00279     }
00280
00281     if(ret == HAL_OK)
00282     {
00283       /* Set the source of SAI2 clock*/
00284       __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
00285     }
00286     else
00287     {
00288       /* set overall return value */
00289       status = ret;
00290     }
00291   }
00292
00293   /*---------------------------- SAI3 configuration -------------------------------*/
00294   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_SAI3)
00295   {
00296     switch(PeriphClkInit->Sai3ClockSelection)
00297     {
00298     case RCC_SAI3CLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
00299       /* Enable SAI Clock output generated form System PLL . */
00300       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00301
00302       /* SAI1 clock source configuration done later after clock selection check */
00303       break;
00304
00305     case RCC_SAI3CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
00306
00307       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
00308       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
00309
00310       /* SAI2 clock source configuration done later after clock selection check */
00311       break;
00312
00313     case RCC_SAI3CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
00314       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
00315       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
00316
00317       /* SAI1 clock source configuration done later after clock selection check */
00318       break;
00319
00320     case RCC_SAI3CLKSOURCE_PIN:
00321       /* External clock is used as source of SAI2 clock*/
00322       /* SAI2 clock source configuration done later after clock selection check */
00323       break;
00324
00325     case RCC_SAI3CLKSOURCE_CLKP:
00326       /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
00327       /* SAI1 clock source configuration done later after clock selection check */
00328       break;
00329
00330     default:
00331       ret = HAL_ERROR;
00332       break;
00333     }
00334
00335     if(ret == HAL_OK)
00336     {
00337       /* Set the source of SAI2 clock*/
00338       __HAL_RCC_SAI3_CONFIG(PeriphClkInit->Sai3ClockSelection);
00339     }
00340     else
00341     {
00342       /* set overall return value */
00343       status = ret;
00344     }
00345   }
00346
00347   /*---------------------------- SAI4A configuration -------------------------------*/
00348   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_SAI4A)
00349   {
00350     switch(PeriphClkInit->Sai4AClockSelection)
00351     {
00352     case RCC_SAI4ACLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
00353       /* Enable SAI Clock output generated form System PLL . */
00354       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00355
00356       /* SAI1 clock source configuration done later after clock selection check */
00357       break;
00358
00359     case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
00360
00361       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
00362       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
00363
00364       /* SAI2 clock source configuration done later after clock selection check */
00365       break;
00366
00367     case RCC_SAI4ACLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
00368       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
00369       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
00370
00371       /* SAI1 clock source configuration done later after clock selection check */
00372       break;
00373
00374     case RCC_SAI4ACLKSOURCE_PIN:
00375       /* External clock is used as source of SAI2 clock*/
00376       /* SAI2 clock source configuration done later after clock selection check */
00377       break;
00378
00379     case RCC_SAI4ACLKSOURCE_CLKP:
00380       /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
00381       /* SAI1 clock source configuration done later after clock selection check */
00382       break;
00383
00384     default:
00385       ret = HAL_ERROR;
00386       break;
00387     }
00388
00389     if(ret == HAL_OK)
00390     {
00391       /* Set the source of SAI2 clock*/
00392       __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);
00393     }
00394     else
00395     {
00396       /* set overall return value */
00397       status = ret;
00398     }
00399   }
00400   /*---------------------------- SAI4B configuration -------------------------------*/
00401   if((PeriphClkInit->PeriphClockSelection)  == RCC_PERIPHCLK_SAI4B)
00402   {
00403     switch(PeriphClkInit->Sai4BClockSelection)
00404     {
00405     case RCC_SAI4BCLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
00406       /* Enable SAI Clock output generated form System PLL . */
00407       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00408
00409       /* SAI1 clock source configuration done later after clock selection check */
00410       break;
00411
00412     case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
00413
00414       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
00415       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
00416
00417       /* SAI2 clock source configuration done later after clock selection check */
00418       break;
00419
00420     case RCC_SAI4BCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
00421       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
00422       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
00423
00424       /* SAI1 clock source configuration done later after clock selection check */
00425       break;
00426
00427     case RCC_SAI4BCLKSOURCE_PIN:
00428       /* External clock is used as source of SAI2 clock*/
00429       /* SAI2 clock source configuration done later after clock selection check */
00430       break;
00431
00432     case RCC_SAI4BCLKSOURCE_CLKP:
00433       /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
00434       /* SAI1 clock source configuration done later after clock selection check */
00435       break;
00436
00437     default:
00438       ret = HAL_ERROR;
00439       break;
00440     }
00441
00442     if(ret == HAL_OK)
00443     {
00444       /* Set the source of SAI2 clock*/
00445       __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);
00446     }
00447     else
00448     {
00449       /* set overall return value */
00450       status = ret;
00451     }
00452   }
00453   /*---------------------------- QSPI configuration -------------------------------*/
00454   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_QSPI)
00455   {
00456     switch(PeriphClkInit->QspiClockSelection)
00457     {
00458     case RCC_QSPICLKSOURCE_PLL:      /* PLL is used as clock source for QSPI*/
00459       /* Enable QSPI Clock output generated form System PLL . */
00460       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00461
00462       /* QSPI clock source configuration done later after clock selection check */
00463       break;
00464
00465     case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/
00466
00467       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
00468       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
00469
00470       /* QSPI clock source configuration done later after clock selection check */
00471       break;
00472
00473
00474     case RCC_QSPICLKSOURCE_CLKP:
00475       /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */
00476       /* QSPI clock source configuration done later after clock selection check */
00477       break;
00478
00479     case RCC_QSPICLKSOURCE_D1HCLK:
00480       /* Domain1 HCLK  clock selected as QSPI kernel peripheral clock */
00481       break;
00482
00483     default:
00484       ret = HAL_ERROR;
00485       break;
00486     }
00487
00488     if(ret == HAL_OK)
00489     {
00490       /* Set the source of QSPI clock*/
00491       __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
00492     }
00493     else
00494     {
00495       /* set overall return value */
00496       status = ret;
00497     }
00498   }
00499
00500   /*---------------------------- SPI1 configuration -------------------------------*/
00501   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_SPI1)
00502   {
00503     switch(PeriphClkInit->Spi1ClockSelection)
00504     {
00505     case RCC_SPI1CLKSOURCE_PLL:      /* PLL is used as clock source for SPI1*/
00506       /* Enable SPI Clock output generated form System PLL . */
00507       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00508
00509       /* SPI1 clock source configuration done later after clock selection check */
00510       break;
00511
00512     case RCC_SPI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1*/
00513
00514       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
00515       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
00516
00517       /* SPI1 clock source configuration done later after clock selection check */
00518       break;
00519
00520     case RCC_SPI1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI1*/
00521       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
00522       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
00523
00524       /* SPI1 clock source configuration done later after clock selection check */
00525       break;
00526
00527     case RCC_SPI1CLKSOURCE_PIN:
00528       /* External clock is used as source of SPI1 clock*/
00529       /* SPI1 clock source configuration done later after clock selection check */
00530       break;
00531
00532     case RCC_SPI1CLKSOURCE_CLKP:
00533       /* HSI, HSE, or CSI oscillator is used as source of SPI1 clock */
00534       /* SPI1 clock source configuration done later after clock selection check */
00535       break;
00536
00537     default:
00538       ret = HAL_ERROR;
00539       break;
00540     }
00541
00542     if(ret == HAL_OK)
00543     {
00544       /* Set the source of SPI1 clock*/
00545       __HAL_RCC_SPI1_CONFIG(PeriphClkInit->Spi1ClockSelection);
00546     }
00547     else
00548     {
00549       /* set overall return value */
00550       status = ret;
00551     }
00552   }
00553
00554   /*---------------------------- SPI2 configuration -------------------------------*/
00555   if((PeriphClkInit->PeriphClockSelection)== RCC_PERIPHCLK_SPI2)
00556   {
00557     switch(PeriphClkInit->Spi2ClockSelection)
00558     {
00559     case RCC_SPI2CLKSOURCE_PLL:      /* PLL is used as clock source for SPI2*/
00560       /* Enable SPI2 Clock output generated form System PLL . */
00561       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00562
00563       /* SPI2 clock source configuration done later after clock selection check */
00564       break;
00565
00566     case RCC_SPI2CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI2*/
00567
00568       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
00569       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
00570
00571       /* SPI2 clock source configuration done later after clock selection check */
00572       break;
00573
00574     case RCC_SPI2CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI2*/
00575       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
00576       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
00577
00578       /* SPI2 clock source configuration done later after clock selection check */
00579       break;
00580
00581     case RCC_SPI2CLKSOURCE_PIN:
00582       /* External clock is used as source of SPI2 clock*/
00583       /* SPI2 clock source configuration done later after clock selection check */
00584       break;
00585
00586     case RCC_SPI2CLKSOURCE_CLKP:
00587       /* HSI, HSE, or CSI oscillator is used as source of SPI2 clock */
00588       /* SPI2 clock source configuration done later after clock selection check */
00589       break;
00590
00591     default:
00592       ret = HAL_ERROR;
00593       break;
00594     }
00595
00596     if(ret == HAL_OK)
00597     {
00598       /* Set the source of SPI2 clock*/
00599       __HAL_RCC_SPI2_CONFIG(PeriphClkInit->Spi2ClockSelection);
00600     }
00601     else
00602     {
00603       /* set overall return value */
00604       status = ret;
00605     }
00606   }
00607
00608   /*---------------------------- SPI3 configuration -------------------------------*/
00609   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_SPI3)
00610   {
00611     switch(PeriphClkInit->Spi3ClockSelection)
00612     {
00613     case RCC_SPI3CLKSOURCE_PLL:      /* PLL is used as clock source for SPI3*/
00614       /* Enable SPI3 Clock output generated form System PLL . */
00615       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00616
00617       /* SPI3 clock source configuration done later after clock selection check */
00618       break;
00619
00620     case RCC_SPI3CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI3*/
00621
00622       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
00623       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
00624
00625       /* SPI3 clock source configuration done later after clock selection check */
00626       break;
00627
00628     case RCC_SPI3CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI3*/
00629       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
00630       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
00631
00632       /* SPI3 clock source configuration done later after clock selection check */
00633       break;
00634
00635     case RCC_SPI3CLKSOURCE_PIN:
00636       /* External clock is used as source of SPI3 clock*/
00637       /* SPI3 clock source configuration done later after clock selection check */
00638       break;
00639
00640     case RCC_SPI3CLKSOURCE_CLKP:
00641       /* HSI, HSE, or CSI oscillator is used as source of SPI3 clock */
00642       /* SPI3 clock source configuration done later after clock selection check */
00643       break;
00644
00645     default:
00646       ret = HAL_ERROR;
00647       break;
00648     }
00649
00650     if(ret == HAL_OK)
00651     {
00652       /* Set the source of SPI3 clock*/
00653       __HAL_RCC_SPI3_CONFIG(PeriphClkInit->Spi3ClockSelection);
00654     }
00655     else
00656     {
00657       /* set overall return value */
00658       status = ret;
00659     }
00660   }
00661
00662   /*---------------------------- SPI4 configuration -------------------------------*/
00663   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_SPI4)
00664   {
00665     switch(PeriphClkInit->Spi4ClockSelection)
00666     {
00667     case RCC_SPI4CLKSOURCE_D2PCLK1:      /* D2PCLK1 as clock source for SPI4*/
00668       /* SPI4 clock source configuration done later after clock selection check */
00669       break;
00670
00671     case RCC_SPI4CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4*/
00672
00673       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
00674       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
00675
00676       /* SPI4 clock source configuration done later after clock selection check */
00677       break;
00678     case RCC_SPI4CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI4*/
00679       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
00680       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
00681       /* SPI4 clock source configuration done later after clock selection check */
00682       break;
00683
00684     case RCC_SPI4CLKSOURCE_HSI:
00685       /* HSI oscillator clock is used as source of SPI4 clock*/
00686       /* SPI4 clock source configuration done later after clock selection check */
00687       break;
00688
00689     case RCC_SPI4CLKSOURCE_CSI:
00690       /*  CSI oscillator clock is used as source of SPI4 clock */
00691       /* SPI4 clock source configuration done later after clock selection check */
00692       break;
00693
00694     case RCC_SPI4CLKSOURCE_HSE:
00695       /* HSE,  oscillator is used as source of SPI4 clock */
00696       /* SPI4 clock source configuration done later after clock selection check */
00697       break;
00698
00699     default:
00700       ret = HAL_ERROR;
00701       break;
00702     }
00703
00704     if(ret == HAL_OK)
00705     {
00706       /* Set the source of SPI4 clock*/
00707       __HAL_RCC_SPI4_CONFIG(PeriphClkInit->Spi4ClockSelection);
00708     }
00709     else
00710     {
00711       /* set overall return value */
00712       status = ret;
00713     }
00714   }
00715
00716   /*---------------------------- SPI5 configuration -------------------------------*/
00717   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_SPI5)
00718   {
00719     switch(PeriphClkInit->Spi5ClockSelection)
00720     {
00721     case RCC_SPI5CLKSOURCE_D2PCLK1:      /* D2PCLK1 as clock source for SPI5*/
00722       /* SPI5 clock source configuration done later after clock selection check */
00723       break;
00724
00725     case RCC_SPI5CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI5*/
00726
00727       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
00728       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
00729
00730       /* SPI5 clock source configuration done later after clock selection check */
00731       break;
00732     case RCC_SPI5CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI5*/
00733       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
00734       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
00735       /* SPI5 clock source configuration done later after clock selection check */
00736       break;
00737
00738     case RCC_SPI5CLKSOURCE_HSI:
00739       /* HSI oscillator clock is used as source of SPI5 clock*/
00740       /* SPI5 clock source configuration done later after clock selection check */
00741       break;
00742
00743     case RCC_SPI5CLKSOURCE_CSI:
00744       /*  CSI oscillator clock is used as source of SPI5 clock */
00745       /* SPI5 clock source configuration done later after clock selection check */
00746       break;
00747
00748     case RCC_SPI5CLKSOURCE_HSE:
00749       /* HSE,  oscillator is used as source of SPI5 clock */
00750       /* SPI5 clock source configuration done later after clock selection check */
00751       break;
00752
00753     default:
00754       ret = HAL_ERROR;
00755       break;
00756     }
00757
00758     if(ret == HAL_OK)
00759     {
00760       /* Set the source of SPI5 clock*/
00761       __HAL_RCC_SPI5_CONFIG(PeriphClkInit->Spi5ClockSelection);
00762     }
00763     else
00764     {
00765       /* set overall return value */
00766       status = ret;
00767     }
00768   }
00769
00770   /*---------------------------- SPI6 configuration -------------------------------*/
00771   if((PeriphClkInit->PeriphClockSelection)== RCC_PERIPHCLK_SPI6)
00772   {
00773     switch(PeriphClkInit->Spi6ClockSelection)
00774     {
00775     case RCC_SPI6CLKSOURCE_D3PCLK1:      /* D3PCLK1 as clock source for SPI6*/
00776       /* SPI6 clock source configuration done later after clock selection check */
00777       break;
00778
00779     case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/
00780
00781       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
00782       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
00783
00784       /* SPI6 clock source configuration done later after clock selection check */
00785       break;
00786     case RCC_SPI6CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI6*/
00787       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
00788       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
00789       /* SPI6 clock source configuration done later after clock selection check */
00790       break;
00791
00792     case RCC_SPI6CLKSOURCE_HSI:
00793       /* HSI oscillator clock is used as source of SPI6 clock*/
00794       /* SPI6 clock source configuration done later after clock selection check */
00795       break;
00796
00797     case RCC_SPI6CLKSOURCE_CSI:
00798       /*  CSI oscillator clock is used as source of SPI6 clock */
00799       /* SPI6 clock source configuration done later after clock selection check */
00800       break;
00801
00802     case RCC_SPI6CLKSOURCE_HSE:
00803       /* HSE,  oscillator is used as source of SPI6 clock */
00804       /* SPI6 clock source configuration done later after clock selection check */
00805       break;
00806
00807     default:
00808       ret = HAL_ERROR;
00809       break;
00810     }
00811
00812     if(ret == HAL_OK)
00813     {
00814       /* Set the source of SPI6 clock*/
00815       __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
00816     }
00817     else
00818     {
00819       /* set overall return value */
00820       status = ret;
00821     }
00822   }
00823
00824
00825 #if defined(FDCAN1) || defined(FDCAN2)
00826   /*---------------------------- FDCAN configuration -------------------------------*/
00827   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_FDCAN)
00828   {
00829     switch(PeriphClkInit->FdcanClockSelection)
00830     {
00831     case RCC_FDCANCLKSOURCE_PLL:      /* PLL is used as clock source for FDCAN*/
00832       /* Enable FDCAN Clock output generated form System PLL . */
00833       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00834
00835       /* FDCAN clock source configuration done later after clock selection check */
00836       break;
00837
00838     case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/
00839
00840       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
00841       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
00842
00843       /* FDCAN clock source configuration done later after clock selection check */
00844       break;
00845
00846     case RCC_FDCANCLKSOURCE_HSE:
00847       /* HSE is used as clock source for FDCAN*/
00848       /* FDCAN clock source configuration done later after clock selection check */
00849       break;
00850
00851     default:
00852       ret = HAL_ERROR;
00853       break;
00854     }
00855
00856     if(ret == HAL_OK)
00857     {
00858       /* Set the source of FDCAN clock*/
00859       __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
00860     }
00861     else
00862     {
00863       /* set overall return value */
00864       status = ret;
00865     }
00866   }
00867
00868 #endif /*FDCAN1 || FDCAN2*/
00869   /*---------------------------- FMC configuration -------------------------------*/
00870   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_FMC)
00871   {
00872     switch(PeriphClkInit->FmcClockSelection)
00873     {
00874     case RCC_FMCCLKSOURCE_PLL:      /* PLL is used as clock source for FMC*/
00875       /* Enable FMC Clock output generated form System PLL . */
00876       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
00877
00878       /* FMC clock source configuration done later after clock selection check */
00879       break;
00880
00881     case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/
00882
00883       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
00884       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
00885
00886       /* FMC clock source configuration done later after clock selection check */
00887       break;
00888
00889
00890     case RCC_FMCCLKSOURCE_CLKP:
00891       /* HSI, HSE, or CSI oscillator is used as source of FMC clock */
00892       /* FMC clock source configuration done later after clock selection check */
00893       break;
00894
00895     case RCC_FMCCLKSOURCE_D1HCLK:
00896       /* Domain1 HCLK  clock selected as QSPI kernel peripheral clock */
00897       break;
00898
00899     default:
00900       ret = HAL_ERROR;
00901       break;
00902     }
00903
00904     if(ret == HAL_OK)
00905     {
00906       /* Set the source of FMC clock*/
00907       __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
00908     }
00909     else
00910     {
00911       /* set overall return value */
00912       status = ret;
00913     }
00914   }
00915
00916   /*---------------------------- RTC configuration -------------------------------*/
00917   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_RTC)
00918   {
00919     /* check for RTC Parameters used to output RTCCLK */
00920     assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
00921
00922     /* Enable write access to Backup domain */
00923     SET_BIT(PWR->CR1, PWR_CR1_DBP);
00924
00925     /* Wait for Backup domain Write protection disable */
00926     tickstart = HAL_GetTick();
00927
00928     while((PWR->CR1 & PWR_CR1_DBP) == RESET)
00929     {
00930       if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
00931       {
00932         ret = HAL_TIMEOUT;
00933         break;
00934       }
00935     }
00936
00937     if(ret == HAL_OK)
00938     {
00939       /* Reset the Backup domain only if the RTC Clock source selection is modified */
00940       if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
00941       {
00942         /* Store the content of BDCR register before the reset of Backup Domain */
00943         tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
00944         /* RTC Clock selection can be changed only if the Backup Domain is reset */
00945         __HAL_RCC_BACKUPRESET_FORCE();
00946         __HAL_RCC_BACKUPRESET_RELEASE();
00947         /* Restore the Content of BDCR register */
00948         RCC->BDCR = tmpreg;
00949       }
00950
00951       /* If LSE is selected as RTC clock source, wait for LSE reactivation */
00952       if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
00953       {
00954         /* Get Start Tick*/
00955         tickstart = HAL_GetTick();
00956
00957         /* Wait till LSE is ready */
00958         while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
00959         {
00960           if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
00961           {
00962             ret = HAL_TIMEOUT;
00963             break;
00964           }
00965         }
00966       }
00967
00968       if(ret == HAL_OK)
00969       {
00970         __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
00971       }
00972       else
00973       {
00974         /* set overall return value */
00975         status = ret;
00976       }
00977     }
00978     else
00979     {
00980       /* set overall return value */
00981       status = ret;
00982     }
00983   }
00984
00985
00986   /*-------------------------- USART1 configuration --------------------------*/
00987   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_USART1)
00988   {
00989     switch(PeriphClkInit->Usart1ClockSelection)
00990     {
00991     case RCC_USART1CLKSOURCE_D2PCLK2: /* D2PCLK2 as clock source for USART1 */
00992       /* USART1 clock source configuration done later after clock selection check */
00993       break;
00994
00995     case RCC_USART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1 */
00996       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
00997       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
00998       /* USART1 clock source configuration done later after clock selection check */
00999       break;
01000
01001     case RCC_USART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1 */
01002       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
01003       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
01004       /* USART1 clock source configuration done later after clock selection check */
01005       break;
01006
01007     case RCC_USART1CLKSOURCE_HSI:
01008       /* HSI oscillator clock is used as source of USART1 clock */
01009       /* USART1 clock source configuration done later after clock selection check */
01010       break;
01011
01012     case RCC_USART1CLKSOURCE_CSI:
01013       /* CSI oscillator clock is used as source of USART1 clock */
01014       /* USART1 clock source configuration done later after clock selection check */
01015       break;
01016
01017     case RCC_USART1CLKSOURCE_LSE:
01018       /* LSE,  oscillator is used as source of USART1 clock */
01019       /* USART1 clock source configuration done later after clock selection check */
01020       break;
01021
01022     default:
01023       ret = HAL_ERROR;
01024       break;
01025     }
01026
01027     if(ret == HAL_OK)
01028     {
01029       /* Set the source of USART1 clock */
01030       __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
01031     }
01032     else
01033     {
01034       /* set overall return value */
01035       status = ret;
01036     }
01037   }
01038
01039   /*-------------------------- USART2 Configuration --------------------------*/
01040   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_USART2)
01041   {
01042     switch(PeriphClkInit->Usart2ClockSelection)
01043     {
01044     case RCC_USART2CLKSOURCE_D2PCLK1: /* D2PCLK1 as clock source for USART2 */
01045       /* USART2 clock source configuration done later after clock selection check */
01046       break;
01047
01048     case RCC_USART2CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2 */
01049       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
01050       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
01051       /* USART2 clock source configuration done later after clock selection check */
01052       break;
01053
01054     case RCC_USART2CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2 */
01055       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
01056       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
01057       /* USART2 clock source configuration done later after clock selection check */
01058       break;
01059
01060     case RCC_USART2CLKSOURCE_HSI:
01061       /* HSI oscillator clock is used as source of USART2 clock */
01062       /* USART2 clock source configuration done later after clock selection check */
01063       break;
01064
01065     case RCC_USART2CLKSOURCE_CSI:
01066       /* CSI oscillator clock is used as source of USART2 clock */
01067       /* USART2 clock source configuration done later after clock selection check */
01068       break;
01069
01070     case RCC_USART2CLKSOURCE_LSE:
01071       /* LSE,  oscillator is used as source of USART2 clock */
01072       /* USART2 clock source configuration done later after clock selection check */
01073       break;
01074
01075     default:
01076       ret = HAL_ERROR;
01077       break;
01078     }
01079
01080     if(ret == HAL_OK)
01081     {
01082       /* Set the source of USART2 clock */
01083       __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
01084     }
01085     else
01086     {
01087       /* set overall return value */
01088       status = ret;
01089     }
01090   }
01091
01092   /*-------------------------- USART3 Configuration --------------------------*/
01093   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_USART3)
01094   {
01095     switch(PeriphClkInit->Usart3ClockSelection)
01096     {
01097     case RCC_USART3CLKSOURCE_D2PCLK1: /* D2PCLK1 as clock source for USART3 */
01098       /* USART3 clock source configuration done later after clock selection check */
01099       break;
01100
01101     case RCC_USART3CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART3 */
01102       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
01103       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
01104       /* USART3 clock source configuration done later after clock selection check */
01105       break;
01106
01107     case RCC_USART3CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART3 */
01108       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
01109       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
01110       /* USART3 clock source configuration done later after clock selection check */
01111       break;
01112
01113     case RCC_USART3CLKSOURCE_HSI:
01114       /* HSI oscillator clock is used as source of USART3 clock */
01115       /* USART3 clock source configuration done later after clock selection check */
01116       break;
01117
01118     case RCC_USART3CLKSOURCE_CSI:
01119       /* CSI oscillator clock is used as source of USART3 clock */
01120       /* USART3 clock source configuration done later after clock selection check */
01121       break;
01122
01123     case RCC_USART3CLKSOURCE_LSE:
01124       /* LSE,  oscillator is used as source of USART3 clock */
01125       /* USART3 clock source configuration done later after clock selection check */
01126       break;
01127
01128     default:
01129       ret = HAL_ERROR;
01130       break;
01131     }
01132
01133     if(ret == HAL_OK)
01134     {
01135       /* Set the source of USART3 clock */
01136       __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
01137     }
01138     else
01139     {
01140       /* set overall return value */
01141       status = ret;
01142     }
01143   }
01144
01145   /*-------------------------- UART4 Configuration ---------------------------*/
01146   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_UART4)
01147   {
01148     switch(PeriphClkInit->Uart4ClockSelection)
01149     {
01150     case RCC_UART4CLKSOURCE_D2PCLK1: /* D2PCLK1 as clock source for UART4 */
01151       /* UART4 clock source configuration done later after clock selection check */
01152       break;
01153
01154     case RCC_UART4CLKSOURCE_PLL2: /* PLL2 is used as clock source for UART4 */
01155       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
01156       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
01157       /* UART4 clock source configuration done later after clock selection check */
01158       break;
01159
01160     case RCC_UART4CLKSOURCE_PLL3: /* PLL3 is used as clock source for UART4 */
01161       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
01162       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
01163       /* UART4 clock source configuration done later after clock selection check */
01164       break;
01165
01166     case RCC_UART4CLKSOURCE_HSI:
01167       /* HSI oscillator clock is used as source of UART4 clock */
01168       /* UART4 clock source configuration done later after clock selection check */
01169       break;
01170
01171     case RCC_UART4CLKSOURCE_CSI:
01172       /* CSI oscillator clock is used as source of UART4 clock */
01173       /* UART4 clock source configuration done later after clock selection check */
01174       break;
01175
01176     case RCC_UART4CLKSOURCE_LSE:
01177       /* LSE,  oscillator is used as source of UART4 clock */
01178       /* UART4 clock source configuration done later after clock selection check */
01179       break;
01180
01181     default:
01182       ret = HAL_ERROR;
01183       break;
01184     }
01185
01186     if(ret == HAL_OK)
01187     {
01188       /* Set the source of UART4 clock */
01189       __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
01190     }
01191     else
01192     {
01193       /* set overall return value */
01194       status = ret;
01195     }
01196   }
01197
01198   /*-------------------------- UART5 Configuration ---------------------------*/
01199   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_UART5)
01200   {
01201     switch(PeriphClkInit->Uart5ClockSelection)
01202     {
01203     case RCC_UART5CLKSOURCE_D2PCLK1: /* D2PCLK1 as clock source for UART5 */
01204       /* UART5 clock source configuration done later after clock selection check */
01205       break;
01206
01207     case RCC_UART5CLKSOURCE_PLL2: /* PLL2 is used as clock source for UART5 */
01208       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
01209       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
01210       /* UART5 clock source configuration done later after clock selection check */
01211       break;
01212
01213     case RCC_UART5CLKSOURCE_PLL3: /* PLL3 is used as clock source for UART5 */
01214       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
01215       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
01216       /* UART5 clock source configuration done later after clock selection check */
01217       break;
01218
01219     case RCC_UART5CLKSOURCE_HSI:
01220       /* HSI oscillator clock is used as source of UART5 clock */
01221       /* UART5 clock source configuration done later after clock selection check */
01222       break;
01223
01224     case RCC_UART5CLKSOURCE_CSI:
01225       /* CSI oscillator clock is used as source of UART5 clock */
01226       /* UART5 clock source configuration done later after clock selection check */
01227       break;
01228
01229     case RCC_UART5CLKSOURCE_LSE:
01230       /* LSE,  oscillator is used as source of UART5 clock */
01231       /* UART5 clock source configuration done later after clock selection check */
01232       break;
01233
01234     default:
01235       ret = HAL_ERROR;
01236       break;
01237     }
01238
01239     if(ret == HAL_OK)
01240     {
01241       /* Set the source of UART5 clock */
01242       __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
01243     }
01244     else
01245     {
01246       /* set overall return value */
01247       status = ret;
01248     }
01249   }
01250
01251   /*-------------------------- USART6 Configuration --------------------------*/
01252   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_USART6)
01253   {
01254     switch(PeriphClkInit->Usart6ClockSelection)
01255     {
01256     case RCC_USART6CLKSOURCE_D2PCLK2: /* D2PCLK2 as clock source for USART6 */
01257       /* USART6 clock source configuration done later after clock selection check */
01258       break;
01259
01260     case RCC_USART6CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART6 */
01261       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
01262       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
01263       /* USART6 clock source configuration done later after clock selection check */
01264       break;
01265
01266     case RCC_USART6CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART6 */
01267       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
01268       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
01269       /* USART6 clock source configuration done later after clock selection check */
01270       break;
01271
01272     case RCC_USART6CLKSOURCE_HSI:
01273       /* HSI oscillator clock is used as source of USART6 clock */
01274       /* USART6 clock source configuration done later after clock selection check */
01275       break;
01276
01277     case RCC_USART6CLKSOURCE_CSI:
01278       /* CSI oscillator clock is used as source of USART6 clock */
01279       /* USART6 clock source configuration done later after clock selection check */
01280       break;
01281
01282     case RCC_USART6CLKSOURCE_LSE:
01283       /* LSE,  oscillator is used as source of USART6 clock */
01284       /* USART6 clock source configuration done later after clock selection check */
01285       break;
01286
01287     default:
01288       ret = HAL_ERROR;
01289       break;
01290     }
01291
01292     if(ret == HAL_OK)
01293     {
01294       /* Set the source of USART6 clock */
01295       __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
01296     }
01297     else
01298     {
01299       /* set overall return value */
01300       status = ret;
01301     }
01302   }
01303
01304   /*-------------------------- UART7 Configuration ---------------------------*/
01305   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_UART7)
01306   {
01307     switch(PeriphClkInit->UART7ClockSelection)
01308     {
01309     case RCC_UART7CLKSOURCE_D2PCLK1: /* D2PCLK1 as clock source for UART7 */
01310       /* UART7 clock source configuration done later after clock selection check */
01311       break;
01312
01313     case RCC_UART7CLKSOURCE_PLL2: /* PLL2 is used as clock source for UART7 */
01314       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
01315       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
01316       /* UART7 clock source configuration done later after clock selection check */
01317       break;
01318
01319     case RCC_UART7CLKSOURCE_PLL3: /* PLL3 is used as clock source for UART7 */
01320       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
01321       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
01322       /* UART7 clock source configuration done later after clock selection check */
01323       break;
01324
01325     case RCC_UART7CLKSOURCE_HSI:
01326       /* HSI oscillator clock is used as source of UART7 clock */
01327       /* UART7 clock source configuration done later after clock selection check */
01328       break;
01329
01330     case RCC_UART7CLKSOURCE_CSI:
01331       /* CSI oscillator clock is used as source of UART7 clock */
01332       /* UART7 clock source configuration done later after clock selection check */
01333       break;
01334
01335     case RCC_UART7CLKSOURCE_LSE:
01336       /* LSE,  oscillator is used as source of UART7 clock */
01337       /* UART7 clock source configuration done later after clock selection check */
01338       break;
01339
01340     default:
01341       ret = HAL_ERROR;
01342       break;
01343     }
01344
01345     if(ret == HAL_OK)
01346     {
01347       /* Set the source of UART7 clock */
01348       __HAL_RCC_UART7_CONFIG(PeriphClkInit->UART7ClockSelection);
01349     }
01350     else
01351     {
01352       /* set overall return value */
01353       status = ret;
01354     }
01355   }
01356
01357   /*-------------------------- UART8 Configuration ---------------------------*/
01358   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_UART8)
01359   {
01360     switch(PeriphClkInit->UART8ClockSelection)
01361     {
01362     case RCC_UART8CLKSOURCE_D2PCLK1: /* D2PCLK1 as clock source for UART8 */
01363       /* UART8 clock source configuration done later after clock selection check */
01364       break;
01365
01366     case RCC_UART8CLKSOURCE_PLL2: /* PLL2 is used as clock source for UART8 */
01367       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
01368       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
01369       /* UART8 clock source configuration done later after clock selection check */
01370       break;
01371
01372     case RCC_UART8CLKSOURCE_PLL3: /* PLL3 is used as clock source for UART8 */
01373       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
01374       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
01375       /* UART8 clock source configuration done later after clock selection check */
01376       break;
01377
01378     case RCC_UART8CLKSOURCE_HSI:
01379       /* HSI oscillator clock is used as source of UART8 clock */
01380       /* UART8 clock source configuration done later after clock selection check */
01381       break;
01382
01383     case RCC_UART8CLKSOURCE_CSI:
01384       /* CSI oscillator clock is used as source of UART8 clock */
01385       /* UART8 clock source configuration done later after clock selection check */
01386       break;
01387
01388     case RCC_UART8CLKSOURCE_LSE:
01389       /* LSE,  oscillator is used as source of UART8 clock */
01390       /* UART8 clock source configuration done later after clock selection check */
01391       break;
01392
01393     default:
01394       ret = HAL_ERROR;
01395       break;
01396     }
01397
01398     if(ret == HAL_OK)
01399     {
01400       /* Set the source of UART8 clock */
01401       __HAL_RCC_UART8_CONFIG(PeriphClkInit->UART8ClockSelection);
01402     }
01403     else
01404     {
01405       /* set overall return value */
01406       status = ret;
01407     }
01408   }
01409
01410   /*-------------------------- LPUART1 Configuration -------------------------*/
01411   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_LPUART1)
01412   {
01413     switch(PeriphClkInit->Lpuart1ClockSelection)
01414     {
01415     case RCC_LPUART1CLKSOURCE_D3PCLK1: /* D3PCLK1 as clock source for LPUART1 */
01416       /* LPUART1 clock source configuration done later after clock selection check */
01417       break;
01418
01419     case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */
01420       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
01421       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
01422       /* LPUART1 clock source configuration done later after clock selection check */
01423       break;
01424
01425     case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */
01426       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
01427       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
01428       /* LPUART1 clock source configuration done later after clock selection check */
01429       break;
01430
01431     case RCC_LPUART1CLKSOURCE_HSI:
01432       /* HSI oscillator clock is used as source of LPUART1 clock */
01433       /* LPUART1 clock source configuration done later after clock selection check */
01434       break;
01435
01436     case RCC_LPUART1CLKSOURCE_CSI:
01437       /* CSI oscillator clock is used as source of LPUART1 clock */
01438       /* LPUART1 clock source configuration done later after clock selection check */
01439       break;
01440
01441     case RCC_LPUART1CLKSOURCE_LSE:
01442       /* LSE,  oscillator is used as source of LPUART1 clock */
01443       /* LPUART1 clock source configuration done later after clock selection check */
01444       break;
01445
01446     default:
01447       ret = HAL_ERROR;
01448       break;
01449     }
01450
01451     if(ret == HAL_OK)
01452     {
01453       /* Set the source of LPUART1 clock */
01454       __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
01455     }
01456     else
01457     {
01458       /* set overall return value */
01459       status = ret;
01460     }
01461   }
01462
01463   /*---------------------------- LPTIM1 configuration -------------------------------*/
01464   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_LPTIM1)
01465   {
01466     switch(PeriphClkInit->Lptim1ClockSelection)
01467     {
01468     case RCC_LPTIM1CLKSOURCE_D2PCLK1:      /* D2PCLK1 as clock source for LPTIM1*/
01469       /* LPTIM1 clock source configuration done later after clock selection check */
01470       break;
01471
01472     case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/
01473
01474       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
01475       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
01476
01477       /* LPTIM1 clock source configuration done later after clock selection check */
01478       break;
01479
01480     case RCC_LPTIM1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM1*/
01481       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
01482       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
01483
01484       /* LPTIM1 clock source configuration done later after clock selection check */
01485       break;
01486
01487     case RCC_LPTIM1CLKSOURCE_LSE:
01488       /* External low speed OSC clock is used as source of LPTIM1 clock*/
01489       /* LPTIM1 clock source configuration done later after clock selection check */
01490       break;
01491
01492     case RCC_LPTIM1CLKSOURCE_LSI:
01493       /* Internal  low speed OSC clock is used  as source of LPTIM1 clock*/
01494       /* LPTIM1 clock source configuration done later after clock selection check */
01495       break;
01496     case RCC_LPTIM1CLKSOURCE_CLKP:
01497       /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */
01498       /* LPTIM1 clock source configuration done later after clock selection check */
01499       break;
01500
01501     default:
01502       ret = HAL_ERROR;
01503       break;
01504     }
01505
01506     if(ret == HAL_OK)
01507     {
01508       /* Set the source of LPTIM1 clock*/
01509       __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
01510     }
01511     else
01512     {
01513       /* set overall return value */
01514       status = ret;
01515     }
01516   }
01517
01518   /*---------------------------- LPTIM2 configuration -------------------------------*/
01519   if((PeriphClkInit->PeriphClockSelection)  == RCC_PERIPHCLK_LPTIM2)
01520   {
01521     switch(PeriphClkInit->Lptim2ClockSelection)
01522     {
01523     case RCC_LPTIM2CLKSOURCE_D3PCLK1:      /* D3PCLK1 as clock source for LPTIM2*/
01524       /* LPTIM2 clock source configuration done later after clock selection check */
01525       break;
01526
01527     case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/
01528
01529       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
01530       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
01531
01532       /* LPTIM2 clock source configuration done later after clock selection check */
01533       break;
01534
01535     case RCC_LPTIM2CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM2*/
01536       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
01537       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
01538
01539       /* LPTIM2 clock source configuration done later after clock selection check */
01540       break;
01541
01542     case RCC_LPTIM2CLKSOURCE_LSE:
01543       /* External low speed OSC clock is used as source of LPTIM2 clock*/
01544       /* LPTIM2 clock source configuration done later after clock selection check */
01545       break;
01546
01547     case RCC_LPTIM2CLKSOURCE_LSI:
01548       /* Internal  low speed OSC clock is used  as source of LPTIM2 clock*/
01549       /* LPTIM2 clock source configuration done later after clock selection check */
01550       break;
01551     case RCC_LPTIM2CLKSOURCE_CLKP:
01552       /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */
01553       /* LPTIM2 clock source configuration done later after clock selection check */
01554       break;
01555
01556     default:
01557       ret = HAL_ERROR;
01558       break;
01559     }
01560
01561     if(ret == HAL_OK)
01562     {
01563       /* Set the source of LPTIM2 clock*/
01564       __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
01565     }
01566     else
01567     {
01568       /* set overall return value */
01569       status = ret;
01570     }
01571   }
01572
01573   /*---------------------------- LPTIM3 configuration -------------------------------*/
01574   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_LPTIM3)
01575   {
01576     switch(PeriphClkInit->Lptim3ClockSelection)
01577     {
01578
01579     case RCC_LPTIM3CLKSOURCE_D3PCLK1:      /* D3PCLK1 as clock source for LPTIM3*/
01580       /* LPTIM3 clock source configuration done later after clock selection check */
01581       break;
01582
01583     case RCC_LPTIM3CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3*/
01584
01585       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
01586       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
01587
01588       /* LPTIM3 clock source configuration done later after clock selection check */
01589       break;
01590
01591     case RCC_LPTIM3CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM3*/
01592       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
01593       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
01594
01595       /* LPTIM3 clock source configuration done later after clock selection check */
01596       break;
01597
01598     case RCC_LPTIM3CLKSOURCE_LSE:
01599       /* External low speed OSC clock is used as source of LPTIM3 clock*/
01600       /* LPTIM3 clock source configuration done later after clock selection check */
01601       break;
01602
01603     case RCC_LPTIM3CLKSOURCE_LSI:
01604       /* Internal  low speed OSC clock is used  as source of LPTIM3 clock*/
01605       /* LPTIM3 clock source configuration done later after clock selection check */
01606       break;
01607     case RCC_LPTIM3CLKSOURCE_CLKP:
01608       /* HSI, HSE, or CSI oscillator is used as source of LPTIM3 clock */
01609       /* LPTIM3 clock source configuration done later after clock selection check */
01610       break;
01611
01612     default:
01613       ret = HAL_ERROR;
01614       break;
01615     }
01616
01617     if(ret == HAL_OK)
01618     {
01619       /* Set the source of LPTIM3 clock*/
01620       __HAL_RCC_LPTIM3_CONFIG(PeriphClkInit->Lptim3ClockSelection);
01621     }
01622     else
01623     {
01624       /* set overall return value */
01625       status = ret;
01626     }
01627   }
01628
01629   /*---------------------------- LPTIM4 configuration -------------------------------*/
01630   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_LPTIM4)
01631   {
01632     switch(PeriphClkInit->Lptim4ClockSelection)
01633     {
01634     case RCC_LPTIM4CLKSOURCE_D3PCLK1:      /* D3PCLK1 as clock source for LPTIM4*/
01635       /* LPTIM4 clock source configuration done later after clock selection check */
01636       break;
01637
01638     case RCC_LPTIM4CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM4*/
01639
01640       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
01641       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
01642
01643       /* LPTIM4 clock source configuration done later after clock selection check */
01644       break;
01645
01646     case RCC_LPTIM4CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM4*/
01647       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
01648       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
01649
01650       /* LPTIM4 clock source configuration done later after clock selection check */
01651       break;
01652
01653     case RCC_LPTIM4CLKSOURCE_LSE:
01654       /* External low speed OSC clock is used as source of LPTIM4 clock*/
01655       /* LPTIM4 clock source configuration done later after clock selection check */
01656       break;
01657
01658     case RCC_LPTIM4CLKSOURCE_LSI:
01659       /* Internal  low speed OSC clock is used  as source of LPTIM4 clock*/
01660       /* LPTIM4 clock source configuration done later after clock selection check */
01661       break;
01662     case RCC_LPTIM4CLKSOURCE_CLKP:
01663       /* HSI, HSE, or CSI oscillator is used as source of LPTIM4 clock */
01664       /* LPTIM4 clock source configuration done later after clock selection check */
01665       break;
01666
01667     default:
01668       ret = HAL_ERROR;
01669       break;
01670     }
01671
01672     if(ret == HAL_OK)
01673     {
01674       /* Set the source of LPTIM4 clock*/
01675       __HAL_RCC_LPTIM4_CONFIG(PeriphClkInit->Lptim4ClockSelection);
01676     }
01677     else
01678     {
01679       /* set overall return value */
01680       status = ret;
01681     }
01682   }
01683
01684   /*---------------------------- LPTIM5 configuration -------------------------------*/
01685   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_LPTIM5)
01686   {
01687     switch(PeriphClkInit->Lptim5ClockSelection)
01688     {
01689
01690     case RCC_LPTIM5CLKSOURCE_D3PCLK1:      /* D3PCLK1 as clock source for LPTIM5*/
01691       /* LPTIM5 clock source configuration done later after clock selection check */
01692       break;
01693
01694     case RCC_LPTIM5CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM5*/
01695
01696       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
01697       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
01698
01699       /* LPTIM5 clock source configuration done later after clock selection check */
01700       break;
01701
01702     case RCC_LPTIM5CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM5*/
01703       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
01704       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
01705
01706       /* LPTIM5 clock source configuration done later after clock selection check */
01707       break;
01708
01709     case RCC_LPTIM5CLKSOURCE_LSE:
01710       /* External low speed OSC clock is used as source of LPTIM5 clock*/
01711       /* LPTIM5 clock source configuration done later after clock selection check */
01712       break;
01713
01714     case RCC_LPTIM5CLKSOURCE_LSI:
01715       /* Internal  low speed OSC clock is used  as source of LPTIM5 clock*/
01716       /* LPTIM5 clock source configuration done later after clock selection check */
01717       break;
01718     case RCC_LPTIM5CLKSOURCE_CLKP:
01719       /* HSI, HSE, or CSI oscillator is used as source of LPTIM5 clock */
01720       /* LPTIM5 clock source configuration done later after clock selection check */
01721       break;
01722
01723     default:
01724       ret = HAL_ERROR;
01725       break;
01726     }
01727
01728     if(ret == HAL_OK)
01729     {
01730       /* Set the source of LPTIM5 clock*/
01731       __HAL_RCC_LPTIM5_CONFIG(PeriphClkInit->Lptim5ClockSelection);
01732     }
01733     else
01734     {
01735       /* set overall return value */
01736       status = ret;
01737     }
01738   }
01739   /*------------------------------ I2C1 Configuration ------------------------*/
01740   if((PeriphClkInit->PeriphClockSelection)== RCC_PERIPHCLK_I2C1)
01741   {
01742     /* Check the parameters */
01743     assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
01744
01745     if ((PeriphClkInit->I2c1ClockSelection )== RCC_I2C1CLKSOURCE_PLL3 )
01746     {
01747       RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
01748       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
01749     }
01750
01751     else
01752     {
01753       __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
01754     }
01755
01756   }
01757
01758   /*------------------------------ I2C2 Configuration ------------------------*/
01759   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_I2C2)
01760   {
01761     /* Check the parameters */
01762     assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
01763
01764     if ((PeriphClkInit->I2c2ClockSelection )== RCC_I2C2CLKSOURCE_PLL3 )
01765     {
01766       RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
01767       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
01768     }
01769
01770     else
01771     {
01772       __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
01773     }
01774   }
01775
01776   /*------------------------------ I2C3 Configuration ------------------------*/
01777   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_I2C3)
01778   {
01779     /* Check the parameters */
01780     assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
01781
01782     if ((PeriphClkInit->I2c3ClockSelection )== RCC_I2C3CLKSOURCE_PLL3 )
01783     {
01784       RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
01785       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
01786     }
01787
01788     else
01789     {
01790       __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
01791     }
01792   }
01793
01794   /*------------------------------ I2C4 Configuration ------------------------*/
01795   if((PeriphClkInit->PeriphClockSelection)  == RCC_PERIPHCLK_I2C4)
01796   {
01797     /* Check the parameters */
01798     assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
01799
01800     if ((PeriphClkInit->I2c4ClockSelection )== RCC_I2C4CLKSOURCE_PLL3 )
01801     {
01802       RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
01803       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
01804     }
01805
01806     else
01807     {
01808       __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
01809     }
01810   }
01811
01812   /*---------------------------- ADC configuration -------------------------------*/
01813   if((PeriphClkInit->PeriphClockSelection)  == RCC_PERIPHCLK_ADC)
01814   {
01815     switch(PeriphClkInit->AdcClockSelection)
01816     {
01817
01818     case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/
01819
01820       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
01821       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
01822
01823       /* ADC clock source configuration done later after clock selection check */
01824       break;
01825
01826     case RCC_ADCCLKSOURCE_PLL3:  /* PLL3 is used as clock source for ADC*/
01827       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
01828       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
01829
01830       /* ADC clock source configuration done later after clock selection check */
01831       break;
01832
01833     case RCC_ADCCLKSOURCE_CLKP:
01834       /* HSI, HSE, or CSI oscillator is used as source of ADC clock */
01835       /* ADC clock source configuration done later after clock selection check */
01836       break;
01837
01838     default:
01839       ret = HAL_ERROR;
01840       break;
01841     }
01842
01843     if(ret == HAL_OK)
01844     {
01845       /* Set the source of ADC clock*/
01846       __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
01847     }
01848     else
01849     {
01850       /* set overall return value */
01851       status = ret;
01852     }
01853   }
01854
01855   /*------------------------------ USB Configuration -------------------------*/
01856   if((PeriphClkInit->PeriphClockSelection)  == RCC_PERIPHCLK_USB)
01857   {
01858
01859     switch(PeriphClkInit->UsbClockSelection)
01860     {
01861     case RCC_USBCLKSOURCE_PLL:      /* PLL is used as clock source for USB*/
01862       /* Enable USB Clock output generated form System USB . */
01863       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
01864
01865       /* USB clock source configuration done later after clock selection check */
01866       break;
01867
01868     case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/
01869
01870       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
01871       ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
01872
01873       /* USB clock source configuration done later after clock selection check */
01874       break;
01875
01876     case RCC_USBCLKSOURCE_HSI48:
01877       /* HSI48 oscillator is used as source of USB clock */
01878       /* USB clock source configuration done later after clock selection check */
01879       break;
01880
01881     default:
01882       ret = HAL_ERROR;
01883       break;
01884     }
01885
01886     if(ret == HAL_OK)
01887     {
01888       /* Set the source of USB clock*/
01889       __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
01890     }
01891     else
01892     {
01893       /* set overall return value */
01894       status = ret;
01895     }
01896
01897   }
01898
01899   /*------------------------------------- SDMMC Configuration ------------------------------------*/
01900   if((PeriphClkInit->PeriphClockSelection)  == RCC_PERIPHCLK_SDMMC)
01901   {
01902     /* Check the parameters */
01903     assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection));
01904
01905     switch(PeriphClkInit->SdmmcClockSelection)
01906     {
01907     case RCC_SDMMCCLKSOURCE_PLL:      /* PLL is used as clock source for SDMMC*/
01908       /* Enable SDMMC Clock output generated form System PLL . */
01909       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
01910
01911       /* SDMMC clock source configuration done later after clock selection check */
01912       break;
01913
01914     case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/
01915
01916       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
01917       ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2));
01918
01919       /* SDMMC clock source configuration done later after clock selection check */
01920       break;
01921
01922     default:
01923       ret = HAL_ERROR;
01924       break;
01925     }
01926
01927     if(ret == HAL_OK)
01928     {
01929       /* Set the source of SDMMC clock*/
01930       __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection);
01931     }
01932     else
01933     {
01934       /* set overall return value */
01935       status = ret;
01936     }
01937   }
01938
01939
01940   /*-------------------------------------- LTDC Configuration -----------------------------------*/
01941   if((PeriphClkInit->PeriphClockSelection)  == RCC_PERIPHCLK_LTDC)
01942   {
01943     __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
01944     status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
01945   }
01946
01947
01948   /*------------------------------ RNG Configuration -------------------------*/
01949   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_RNG)
01950   {
01951
01952     switch(PeriphClkInit->RngClockSelection)
01953     {
01954     case RCC_RNGCLKSOURCE_PLL:     /* PLL is used as clock source for RNG*/
01955       /* Enable RNG Clock output generated form System RNG . */
01956       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
01957
01958       /* RNG clock source configuration done later after clock selection check */
01959       break;
01960
01961     case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/
01962
01963       /* RNG clock source configuration done later after clock selection check */
01964       break;
01965
01966     case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/
01967
01968       /* RNG clock source configuration done later after clock selection check */
01969       break;
01970     case RCC_USBCLKSOURCE_HSI48:
01971       /* HSI48 oscillator is used as source of RNG clock */
01972       /* RNG clock source configuration done later after clock selection check */
01973       break;
01974
01975     default:
01976       ret = HAL_ERROR;
01977       break;
01978     }
01979
01980     if(ret == HAL_OK)
01981     {
01982       /* Set the source of RNG clock*/
01983       __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
01984     }
01985     else
01986     {
01987       /* set overall return value */
01988       status = ret;
01989     }
01990
01991   }
01992
01993   /*------------------------------ SWPMI1 Configuration ------------------------*/
01994   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_SWPMI1)
01995   {
01996     /* Check the parameters */
01997     assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
01998
01999     /* Configure the SWPMI1 interface clock source */
02000     __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
02001   }
02002
02003   /*------------------------------ HRTIM1 clock Configuration ----------------*/
02004   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_HRTIM1)
02005   {
02006     /* Check the parameters */
02007     assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
02008
02009     /* Configure the HRTIM1 clock source */
02010     __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
02011   }
02012
02013   /*------------------------------ DFSDM1 Configuration ------------------------*/
02014   if((PeriphClkInit->PeriphClockSelection) == RCC_PERIPHCLK_DFSDM1)
02015   {
02016     /* Check the parameters */
02017     assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
02018
02019     /* Configure the DFSDM1 interface clock source */
02020     __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
02021   }
02022
02023   /*------------------------------------ TIM configuration --------------------------------------*/
02024   if((PeriphClkInit->PeriphClockSelection) == (RCC_PERIPHCLK_TIM))
02025   {
02026     /* Check the parameters */
02027     assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
02028
02029     /* Configure Timer Prescaler */
02030     __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
02031   }
02032   return status;
02033 }
02034
02035 /**
02036   * @brief  Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
02037   * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
02038 *         returns the configuration information for the Extended Peripherals clocks :
02039   *         (SDMMC, CKPER, FMC, QSPI, DSI, SPI45, SPDIF, DFSDM1, FDCAN, SWPMI,SAI23, SAI1, SPI123,
02040   *         USART234578, USART16, RNG,HRTIM1, I2C123, USB,CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC,
02041 *         SAI4A,SAI4B,SPI6,RTC,TIM).
02042   * @retval None
02043   */
02044 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
02045 {
02046   /* Set all possible values for the extended clock type parameter------------*/
02047   PeriphClkInit->PeriphClockSelection =  RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |
02048                                 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 |
02049                                  RCC_PERIPHCLK_I2C2  |  RCC_PERIPHCLK_I2C3 |  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 |
02050                                 RCC_PERIPHCLK_SAI1 |  RCC_PERIPHCLK_SAI2 |  RCC_PERIPHCLK_USB |  RCC_PERIPHCLK_ADC |
02051                                 RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_RTC |  RCC_PERIPHCLK_CEC |
02052                                 RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 | RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_I2C4 |
02053                                 RCC_PERIPHCLK_LPTIM3 | RCC_PERIPHCLK_LPTIM4 | RCC_PERIPHCLK_LPTIM5 | RCC_PERIPHCLK_SAI3 |
02054                                 RCC_PERIPHCLK_SAI4A | RCC_PERIPHCLK_SAI4B | RCC_PERIPHCLK_FMC |  RCC_PERIPHCLK_QSPI |
02055                                 RCC_PERIPHCLK_DSI | RCC_PERIPHCLK_CKPER | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_FDCAN |
02056                                 RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4 |
02057                                 RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6 | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_LTDC |
02058                                 RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_HRTIM1 | RCC_PERIPHCLK_TIM  ;
02059
02060   /* Get the PLL3 Clock configuration -----------------------------------------------*/
02061   PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> POSITION_VAL(RCC_PLLCKSELR_DIVM3));
02062   PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> POSITION_VAL(RCC_PLL3DIVR_N3))+ 1;
02063   PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> POSITION_VAL(RCC_PLL3DIVR_R3))+ 1;
02064   PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> POSITION_VAL(RCC_PLL3DIVR_P3))+ 1;
02065   PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> POSITION_VAL(RCC_PLL3DIVR_Q3))+ 1;
02066   PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> POSITION_VAL(RCC_PLLCFGR_PLL3RGE_1));
02067   PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> POSITION_VAL(RCC_PLLCFGR_PLL3VCOSEL));
02068
02069   /* Get the PLL2 Clock configuration -----------------------------------------------*/
02070   PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> POSITION_VAL(RCC_PLLCKSELR_DIVM2));
02071   PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> POSITION_VAL(RCC_PLL2DIVR_N2))+ 1;
02072   PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> POSITION_VAL(RCC_PLL2DIVR_R2))+ 1;
02073   PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> POSITION_VAL(RCC_PLL2DIVR_P2))+ 1;
02074   PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> POSITION_VAL(RCC_PLL2DIVR_Q2))+ 1;
02075   PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> POSITION_VAL(RCC_PLLCFGR_PLL2RGE_1));
02076   PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> POSITION_VAL(RCC_PLLCFGR_PLL2VCOSEL));
02077
02078   /* Get the USART1 configuration --------------------------------------------*/
02079   PeriphClkInit->Usart1ClockSelection  = __HAL_RCC_GET_USART1_SOURCE();
02080   /* Get the USART2 clock source ---------------------------------------------*/
02081   PeriphClkInit->Usart2ClockSelection  = __HAL_RCC_GET_USART2_SOURCE();
02082   /* Get the USART3 clock source ---------------------------------------------*/
02083   PeriphClkInit->Usart3ClockSelection  = __HAL_RCC_GET_USART3_SOURCE();
02084   /* Get the UART4 clock source ----------------------------------------------*/
02085   PeriphClkInit->Uart4ClockSelection   = __HAL_RCC_GET_UART4_SOURCE();
02086   /* Get the UART5 clock source ----------------------------------------------*/
02087   PeriphClkInit->Uart5ClockSelection   = __HAL_RCC_GET_UART5_SOURCE();
02088   /* Get the USART6 clock source ---------------------------------------------*/
02089   PeriphClkInit->Usart6ClockSelection   = __HAL_RCC_GET_USART6_SOURCE();
02090   /* Get the UART7 clock source ----------------------------------------------*/
02091   PeriphClkInit->UART7ClockSelection   = __HAL_RCC_GET_UART7_SOURCE();
02092   /* Get the UART8 clock source -----------------------------------------------*/
02093   PeriphClkInit->UART8ClockSelection   = __HAL_RCC_GET_UART8_SOURCE();
02094   /* Get the LPUART1 clock source --------------------------------------------*/
02095   PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
02096   /* Get the I2C1 clock source -----------------------------------------------*/
02097   PeriphClkInit->I2c1ClockSelection    = __HAL_RCC_GET_I2C1_SOURCE();
02098   /* Get the I2C2 clock source ----------------------------------------------*/
02099   PeriphClkInit->I2c2ClockSelection    = __HAL_RCC_GET_I2C2_SOURCE();
02100   /* Get the I2C3 clock source -----------------------------------------------*/
02101   PeriphClkInit->I2c3ClockSelection    = __HAL_RCC_GET_I2C3_SOURCE();
02102   /* Get the LPTIM1 clock source ---------------------------------------------*/
02103   PeriphClkInit->Lptim1ClockSelection  = __HAL_RCC_GET_LPTIM1_SOURCE();
02104   /* Get the LPTIM2 clock source ---------------------------------------------*/
02105   PeriphClkInit->Lptim2ClockSelection  = __HAL_RCC_GET_LPTIM2_SOURCE();
02106   /* Get the LPTIM3 clock source ---------------------------------------------*/
02107   PeriphClkInit->Lptim3ClockSelection  = __HAL_RCC_GET_LPTIM3_SOURCE();
02108   /* Get the LPTIM4 clock source ---------------------------------------------*/
02109   PeriphClkInit->Lptim4ClockSelection  = __HAL_RCC_GET_LPTIM4_SOURCE();
02110   /* Get the LPTIM5 clock source ---------------------------------------------*/
02111   PeriphClkInit->Lptim5ClockSelection  = __HAL_RCC_GET_LPTIM5_SOURCE();
02112   /* Get the SAI1 clock source -----------------------------------------------*/
02113   PeriphClkInit->Sai1ClockSelection    = __HAL_RCC_GET_SAI1_SOURCE();
02114   /* Get the SAI2 clock source -----------------------------------------------*/
02115   PeriphClkInit->Sai2ClockSelection    = __HAL_RCC_GET_SAI2_SOURCE();
02116   /* Get the SAI3 clock source -----------------------------------------------*/
02117   PeriphClkInit->Sai3ClockSelection    = __HAL_RCC_GET_SAI3_SOURCE();
02118   /* Get the SAI4A clock source ----------------------------------------------*/
02119   PeriphClkInit->Sai4AClockSelection    = __HAL_RCC_GET_SAI4A_SOURCE();
02120   /* Get the SAI4B clock source ----------------------------------------------*/
02121   PeriphClkInit->Sai4BClockSelection    = __HAL_RCC_GET_SAI4B_SOURCE();
02122   /* Get the RTC clock source ------------------------------------------------*/
02123   PeriphClkInit->RTCClockSelection     = __HAL_RCC_GET_RTC_SOURCE();
02124   /* Get the USB clock source ------------------------------------------------*/
02125   PeriphClkInit->UsbClockSelection   = __HAL_RCC_GET_USB_SOURCE();
02126   /* Get the SDMMC clock source ----------------------------------------------*/
02127   PeriphClkInit->SdmmcClockSelection   = __HAL_RCC_GET_SDMMC_SOURCE();
02128   /* Get the RNG clock source ------------------------------------------------*/
02129   PeriphClkInit->RngClockSelection   = __HAL_RCC_GET_RNG_SOURCE();
02130   /* Get the HRTIM1 clock source ---------------------------------------------*/
02131   PeriphClkInit->Hrtim1ClockSelection   = __HAL_RCC_GET_HRTIM1_SOURCE();
02132   /* Get the ADC clock source ------------------------------------------------*/
02133   PeriphClkInit->AdcClockSelection     = __HAL_RCC_GET_ADC_SOURCE();
02134   /* Get the SWPMI1 clock source ---------------------------------------------*/
02135   PeriphClkInit->Swpmi1ClockSelection  = __HAL_RCC_GET_SWPMI1_SOURCE();
02136   /* Get the DFSDM1 clock source ----------------------------------------------*/
02137   PeriphClkInit->Dfsdm1ClockSelection   = __HAL_RCC_GET_DFSDM1_SOURCE();
02138   /* Get the SPDIFRX clock source --------------------------------------------*/
02139   PeriphClkInit->SpdifrxClockSelection   = __HAL_RCC_GET_SPDIFRX_SOURCE();
02140   /* Get the SP1 clock source ------------------------------------------------*/
02141   PeriphClkInit->Spi1ClockSelection   = __HAL_RCC_GET_SPI1_SOURCE();
02142   /* Get the SP2 clock source ------------------------------------------------*/
02143   PeriphClkInit->Spi2ClockSelection   = __HAL_RCC_GET_SPI2_SOURCE();
02144   /* Get the SP3 clock source ------------------------------------------------*/
02145   PeriphClkInit->Spi3ClockSelection   = __HAL_RCC_GET_SPI3_SOURCE();
02146   /* Get the SP4 clock source ------------------------------------------------*/
02147   PeriphClkInit->Spi4ClockSelection   = __HAL_RCC_GET_SPI4_SOURCE();
02148   /* Get the SP5 clock source ------------------------------------------------*/
02149   PeriphClkInit->Spi5ClockSelection   = __HAL_RCC_GET_SPI5_SOURCE();
02150   /* Get the SP6 clock source ------------------------------------------------*/
02151   PeriphClkInit->Spi6ClockSelection   = __HAL_RCC_GET_SPI6_SOURCE();
02152   /* Get the FDCAN clock source ----------------------------------------------*/
02153   PeriphClkInit->FdcanClockSelection   = __HAL_RCC_GET_FDCAN_SOURCE();
02154   /* Get the CEC clock source ------------------------------------------------*/
02155   PeriphClkInit->CecClockSelection   = __HAL_RCC_GET_CEC_SOURCE();
02156   /* Get the FMC clock source ------------------------------------------------*/
02157   PeriphClkInit->FmcClockSelection   = __HAL_RCC_GET_FMC_SOURCE();
02158   /* Get the QSPI clock source -----------------------------------------------*/
02159   PeriphClkInit->QspiClockSelection   = __HAL_RCC_GET_QSPI_SOURCE();
02160
02161
02162   /* Get the CKPER clock source ----------------------------------------------*/
02163   PeriphClkInit->CkperClockSelection   = __HAL_RCC_GET_CLKP_SOURCE();
02164
02165   /* Get the TIM Prescaler configuration --------------------------------------------*/
02166   if ((RCC->CFGR & RCC_CFGR_TIMPRE) == RESET)
02167   {
02168     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
02169   }
02170   else
02171   {
02172     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
02173   }
02174 }
02175
02176 /**
02177   * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
02178   * @note   Return 0 if peripheral clock identifier not managed by this API
02179   * @param  PeriphClk: Peripheral clock identifier
02180   *         This parameter can be one of the following values:
02181   *            @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
02182   *            @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
02183   *            @arg RCC_PERIPHCLK_SAI3: SAI3 peripheral clock
02184   *            @arg RCC_PERIPHCLK_SAI4: SAI4 peripheral clock
02185   *            @arg RCC_PERIPHCLK_SPI1: SPI1 peripheral clock
02186   *            @arg RCC_PERIPHCLK_SPI2: SPI2 peripheral clock
02187   *            @arg RCC_PERIPHCLK_SPI3: SPI3 peripheral clock
02188   * @retval Frequency in KHz
02189   */
02190 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
02191 {
02192   PLL1_ClocksTypeDef pll1_clocks;
02193   PLL2_ClocksTypeDef pll2_clocks;
02194   PLL3_ClocksTypeDef pll3_clocks;
02195
02196   /* This variable is used to store the SAI clock frequency (value in Hz) */
02197   uint32_t frequency = 0;
02198   /* This variable is used to store the SAI and CKP clock source */
02199   uint32_t saiclocksource = 0;
02200   uint32_t ckpclocksource = 0;
02201   uint32_t srcclk = 0U;
02202   switch (PeriphClk)
02203   {
02204   case RCC_PERIPHCLK_SAI1:
02205     {
02206
02207       saiclocksource= __HAL_RCC_GET_SAI1_SOURCE();
02208
02209       switch (saiclocksource)
02210       {
02211       case 0: /* PLL1 is the clock source for SAI1 */
02212         {
02213           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
02214           frequency = pll1_clocks.PLL1_Q_Frequency;
02215           break;
02216         }
02217       case RCC_D2CCIP1R_SAI1SEL_0: /* PLLI2 is the clock source for SAI1 */
02218         {
02219           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02220           frequency = pll2_clocks.PLL2_P_Frequency;
02221           break;
02222         }
02223
02224       case RCC_D2CCIP1R_SAI1SEL_1: /* PLLI3 is the clock source for SAI1 */
02225         {
02226           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
02227           frequency = pll3_clocks.PLL3_P_Frequency;
02228           break;
02229         }
02230
02231       case RCC_D2CCIP1R_SAI1SEL_2: /* CKPER is the clock source for SAI1*/
02232         {
02233
02234           ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
02235
02236           if(ckpclocksource== 0)
02237           {
02238             /* In Case the main PLL Source is HSI */
02239             frequency = HSI_VALUE;
02240           }
02241
02242           else if(ckpclocksource== RCC_D1CCIPR_CKPERSEL_0)
02243           {
02244             /* In Case the main PLL Source is CSI */
02245             frequency = CSI_VALUE;
02246           }
02247
02248           else if (ckpclocksource== RCC_D1CCIPR_CKPERSEL_1)
02249           {
02250             /* In Case the main PLL Source is HSE */
02251             frequency = HSE_VALUE;
02252           }
02253
02254           break;
02255         }
02256
02257       case (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1 ): /* External clock is the clock source for SAI1 */
02258         {
02259           frequency = EXTERNAL_CLOCK_VALUE;
02260           break;
02261         }
02262       default :
02263         {
02264           break;
02265         }
02266       }
02267       break;
02268     }
02269
02270   case RCC_PERIPHCLK_SAI2:
02271     {
02272
02273       saiclocksource= __HAL_RCC_GET_SAI2_SOURCE();
02274
02275       switch (saiclocksource)
02276       {
02277       case 0: /* PLL1 is the clock source for SAI2 */
02278         {
02279           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
02280           frequency = pll1_clocks.PLL1_Q_Frequency;
02281           break;
02282         }
02283       case RCC_D2CCIP1R_SAI23SEL_0: /* PLLI2 is the clock source for SAI2 */
02284         {
02285           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02286           frequency = pll2_clocks.PLL2_P_Frequency;
02287           break;
02288         }
02289
02290       case RCC_D2CCIP1R_SAI23SEL_1: /* PLLI3 is the clock source for SAI2 */
02291         {
02292           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
02293           frequency = pll3_clocks.PLL3_P_Frequency;
02294           break;
02295         }
02296
02297       case RCC_D2CCIP1R_SAI23SEL_2: /* CKPER is the clock source for SAI2*/
02298         {
02299
02300           ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
02301
02302           if(ckpclocksource== 0)
02303           {
02304             /* In Case the main PLL Source is HSI */
02305             frequency = HSI_VALUE;
02306           }
02307
02308           else if(ckpclocksource== RCC_D1CCIPR_CKPERSEL_0)
02309           {
02310             /* In Case the main PLL Source is CSI */
02311             frequency = CSI_VALUE;
02312           }
02313
02314           else if (ckpclocksource== RCC_D1CCIPR_CKPERSEL_1)
02315           {
02316             /* In Case the main PLL Source is HSE */
02317             frequency = HSE_VALUE;
02318           }
02319
02320           break;
02321         }
02322
02323       case (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1 ): /* External clock is the clock source for SAI2 */
02324         {
02325           frequency = EXTERNAL_CLOCK_VALUE;
02326           break;
02327         }
02328       default :
02329         {
02330           break;
02331         }
02332       }
02333       break;
02334     }
02335
02336   case RCC_PERIPHCLK_SAI3:
02337     {
02338
02339       saiclocksource= __HAL_RCC_GET_SAI3_SOURCE();
02340
02341       switch (saiclocksource)
02342       {
02343       case 0: /* PLL1 is the clock source for SAI3 */
02344         {
02345           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
02346           frequency = pll1_clocks.PLL1_Q_Frequency;
02347           break;
02348         }
02349       case RCC_D2CCIP1R_SAI23SEL_0: /* PLLI2 is the clock source for SAI3 */
02350         {
02351           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02352           frequency = pll2_clocks.PLL2_P_Frequency;
02353           break;
02354         }
02355
02356       case RCC_D2CCIP1R_SAI23SEL_1: /* PLLI3 is the clock source for SAI3 */
02357         {
02358           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
02359           frequency = pll3_clocks.PLL3_P_Frequency;
02360           break;
02361         }
02362
02363       case RCC_D2CCIP1R_SAI23SEL_2: /* CKPER is the clock source for SAI3*/
02364         {
02365
02366           ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
02367
02368           if(ckpclocksource== 0)
02369           {
02370             /* In Case the main PLL Source is HSI */
02371             frequency = HSI_VALUE;
02372           }
02373
02374           else if(ckpclocksource== RCC_D1CCIPR_CKPERSEL_0)
02375           {
02376             /* In Case the main PLL Source is CSI */
02377             frequency = CSI_VALUE;
02378           }
02379
02380           else if (ckpclocksource== RCC_D1CCIPR_CKPERSEL_1)
02381           {
02382             /* In Case the main PLL Source is HSE */
02383             frequency = HSE_VALUE;
02384           }
02385
02386           break;
02387         }
02388
02389       case (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1 ): /* External clock is the clock source for SAI3 */
02390         {
02391           frequency = EXTERNAL_CLOCK_VALUE;
02392           break;
02393         }
02394       default :
02395         {
02396           break;
02397         }
02398       }
02399       break;
02400     }
02401
02402   case RCC_PERIPHCLK_SAI4A:
02403     {
02404
02405       saiclocksource= __HAL_RCC_GET_SAI4A_SOURCE();
02406
02407       switch (saiclocksource)
02408       {
02409       case 0: /* PLL1 is the clock source for SAI4A */
02410         {
02411           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
02412           frequency = pll1_clocks.PLL1_Q_Frequency;
02413           break;
02414         }
02415       case RCC_D3CCIPR_SAI4ASEL_0: /* PLLI2 is the clock source for SAI4A */
02416         {
02417           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02418           frequency = pll2_clocks.PLL2_P_Frequency;
02419           break;
02420         }
02421
02422       case RCC_D3CCIPR_SAI4ASEL_1: /* PLLI3 is the clock source for SAI4A */
02423         {
02424           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
02425           frequency = pll3_clocks.PLL3_P_Frequency;
02426           break;
02427         }
02428
02429       case RCC_D3CCIPR_SAI4ASEL_2: /* CKPER is the clock source for SAI4A*/
02430         {
02431
02432           ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
02433
02434           if(ckpclocksource== 0)
02435           {
02436             /* In Case the main PLL Source is HSI */
02437             frequency = HSI_VALUE;
02438           }
02439
02440           else if(ckpclocksource== RCC_D1CCIPR_CKPERSEL_0)
02441           {
02442             /* In Case the main PLL Source is CSI */
02443             frequency = CSI_VALUE;
02444           }
02445
02446           else if (ckpclocksource== RCC_D1CCIPR_CKPERSEL_1)
02447           {
02448             /* In Case the main PLL Source is HSE */
02449             frequency = HSE_VALUE;
02450           }
02451
02452           break;
02453         }
02454
02455       case (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1 ): /* External clock is the clock source for SAI4A */
02456         {
02457           frequency = EXTERNAL_CLOCK_VALUE;
02458           break;
02459         }
02460
02461       default :
02462         {
02463           break;
02464         }
02465       }
02466       break;
02467     }
02468
02469   case RCC_PERIPHCLK_SAI4B:
02470     {
02471
02472       saiclocksource= __HAL_RCC_GET_SAI4B_SOURCE();
02473
02474       switch (saiclocksource)
02475       {
02476       case 0: /* PLL1 is the clock source for SAI4B */
02477         {
02478           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
02479           frequency = pll1_clocks.PLL1_Q_Frequency;
02480           break;
02481         }
02482       case RCC_D3CCIPR_SAI4BSEL_0: /* PLLI2 is the clock source for SAI4B */
02483         {
02484           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02485           frequency = pll2_clocks.PLL2_P_Frequency;
02486           break;
02487         }
02488
02489       case RCC_D3CCIPR_SAI4BSEL_1: /* PLLI3 is the clock source for SAI4B */
02490         {
02491           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
02492           frequency = pll3_clocks.PLL3_P_Frequency;
02493           break;
02494         }
02495
02496       case RCC_D3CCIPR_SAI4BSEL_2: /* CKPER is the clock source for SAI4B*/
02497         {
02498
02499           ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
02500
02501           if(ckpclocksource== 0)
02502           {
02503             /* In Case the main PLL Source is HSI */
02504             frequency = HSI_VALUE;
02505           }
02506
02507           else if(ckpclocksource== RCC_D1CCIPR_CKPERSEL_0)
02508           {
02509             /* In Case the main PLL Source is CSI */
02510             frequency = CSI_VALUE;
02511           }
02512
02513           else if (ckpclocksource== RCC_D1CCIPR_CKPERSEL_1)
02514           {
02515             /* In Case the main PLL Source is HSE */
02516             frequency = HSE_VALUE;
02517           }
02518
02519           break;
02520         }
02521
02522       case (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1 ): /* External clock is the clock source for SAI4B */
02523         {
02524           frequency = EXTERNAL_CLOCK_VALUE;
02525           break;
02526         }
02527
02528       default :
02529         {
02530           break;
02531         }
02532       }
02533       break;
02534     }
02535   case RCC_PERIPHCLK_SPI1:
02536   case RCC_PERIPHCLK_SPI2:
02537   case RCC_PERIPHCLK_SPI3:
02538     {
02539       /* SPI1, SPI2, SPI3 have the same clock source */
02540       srcclk= __HAL_RCC_GET_SPI3_SOURCE();
02541
02542       switch (srcclk)
02543       {
02544       case 0: /* PLL1 is the clock source for I2S */
02545         {
02546           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
02547           frequency = pll1_clocks.PLL1_Q_Frequency;
02548           break;
02549         }
02550       case RCC_D2CCIP1R_SPI123SEL_0: /* PLL2 is the clock source for I2S */
02551         {
02552           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02553           frequency = pll2_clocks.PLL2_P_Frequency;
02554           break;
02555         }
02556
02557       case RCC_D2CCIP1R_SPI123SEL_1: /* PLL3 is the clock source for I2S */
02558         {
02559           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
02560           frequency = pll3_clocks.PLL3_P_Frequency;
02561           break;
02562         }
02563
02564       case RCC_D2CCIP1R_SPI123SEL_2: /* CKPER is the clock source for I2S*/
02565         {
02566
02567           ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
02568
02569           if(ckpclocksource== RCC_CLKPSOURCE_HSI)
02570           {
02571             /* In Case the main PLL Source is HSI */
02572             frequency = HSI_VALUE;
02573           }
02574
02575           else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
02576           {
02577             /* In Case the main PLL Source is CSI */
02578             frequency = CSI_VALUE;
02579           }
02580
02581           else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
02582           {
02583             /* In Case the main PLL Source is HSE */
02584             frequency = HSE_VALUE;
02585           }
02586
02587           break;
02588         }
02589
02590       case (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1): /* External clock is the clock source for I2S */
02591         {
02592           frequency = EXTERNAL_CLOCK_VALUE;
02593           break;
02594         }
02595       default :
02596         {
02597           break;
02598         }
02599       }
02600       break;
02601     }
02602
02603   }
02604   return frequency;
02605 }
02606
02607
02608 /**
02609   * @brief  Returns the D1PCLK1 frequency
02610   * @note   Each time D1PCLK1 changes, this function must be called to update the
02611   *         right D1PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
02612   * @retval D1PCLK1 frequency
02613   */
02614 uint32_t HAL_RCCEx_GetD1PCLK1Freq(void)
02615 {
02616   /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
02617   return (HAL_RCC_GetHCLKFreq() >> D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE)>> POSITION_VAL(RCC_D1CFGR_D1PPRE_0)]);
02618 }
02619
02620 /**
02621   * @brief  Returns the D3PCLK1 frequency
02622   * @note   Each time D3PCLK1 changes, this function must be called to update the
02623   *         right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
02624   * @retval D3PCLK1 frequency
02625   */
02626 uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
02627 {
02628   /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
02629   return (HAL_RCC_GetHCLKFreq() >> D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE)>> POSITION_VAL(RCC_D3CFGR_D3PPRE_0)]);
02630 }
02631 /**
02632 * @brief  Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency
02633   * @note   The PLL2 clock frequencies computed by this function is not the real
02634   *         frequency in the chip. It is calculated based on the predefined
02635   *         constant and the selected clock source:
02636   * @note     The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
02637   * @note   This function can be used by the user application to compute the
02638   *         baud-rate for the communication peripherals or configure other parameters.
02639   *
02640   * @note   Each time PLL2CLK changes, this function must be called to update the
02641   *         right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
02642   * @param  PLL2_Clocks structure.
02643   * @retval None
02644   */
02645 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks)
02646 {
02647   uint32_t  pllsource = 0, pll2m = 1 ,  pll2fracen = 0, hsivalue = 0;
02648   float fracn2 =0 ,pll2vco = 0;
02649
02650   /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
02651      PLL2xCLK = PLL2_VCO / PLL2x
02652   */
02653   pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
02654   pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> 12)  ;
02655   pll2fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN;
02656   fracn2 =(pll2fracen* ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2)>> 3));
02657
02658   switch (pllsource)
02659   {
02660
02661   case 0x00:  /* HSI used as PLL clock source */
02662
02663     if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
02664     {
02665       hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
02666       pll2vco = ( hsivalue / pll2m) * ((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/0x1FFF) +1 );
02667     }
02668     else
02669     {
02670       pll2vco = (HSI_VALUE / pll2m) * ((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/0x1FFF) +1 );
02671     }
02672     break;
02673
02674   case 0x01:  /* HSI used as PLL clock source */
02675     pll2vco = (CSI_VALUE / pll2m) * ((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/0x1FFF) +1 );
02676     break;
02677
02678   case 0x02:  /* HSE used as PLL clock source */
02679     pll2vco = (HSE_VALUE / pll2m) * ((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/0x1FFF) +1 );
02680     break;
02681
02682   default:
02683     pll2vco = (CSI_VALUE / pll2m) * ((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/0x1FFF) +1 );
02684     break;
02685   }
02686   PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(pll2vco/(((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >>9) + 1  )) ;
02687   PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(pll2vco/(((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >>16) + 1 )) ;
02688   PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(pll2vco/(((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >>24) + 1 )) ;
02689
02690
02691 }
02692
02693 /**
02694 * @brief  Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency
02695   * @note   The PLL3 clock frequencies computed by this function is not the real
02696   *         frequency in the chip. It is calculated based on the predefined
02697   *         constant and the selected clock source:
02698   * @note     The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
02699   * @note   This function can be used by the user application to compute the
02700   *         baud-rate for the communication peripherals or configure other parameters.
02701   *
02702   * @note   Each time PLL3CLK changes, this function must be called to update the
02703   *         right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
02704   * @param  PLL3_Clocks structure.
02705   * @retval None
02706   */
02707 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks)
02708 {
02709   uint32_t pllsource = 0, pll3m = 1, pll3fracen = 0 , hsivalue =0;
02710   float fracn3 =0 , pll3vco = 0;
02711   /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
02712      PLL3xCLK = PLL3_VCO / PLLxR
02713   */
02714   pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
02715   pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> 20)  ;
02716   pll3fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN;
02717   fracn3 = (pll3fracen* ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3)>> 3));
02718   switch (pllsource)
02719   {
02720   case 0x00:  /* HSI used as PLL clock source */
02721
02722     if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
02723     {
02724       hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
02725       pll3vco = (hsivalue / pll3m) * ((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/0x1FFF) +1 );
02726     }
02727     else
02728     {
02729       pll3vco = (HSI_VALUE / pll3m) * ((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/0x1FFF) +1 );
02730     }
02731     break;
02732   case 0x01:  /* HSI used as PLL clock source */
02733     pll3vco = (CSI_VALUE / pll3m) * ((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/0x1FFF) +1 );
02734     break;
02735
02736   case 0x02:  /* HSE used as PLL clock source */
02737     pll3vco = (HSE_VALUE / pll3m) * ((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/0x1FFF) +1 );
02738     break;
02739
02740   default:
02741     pll3vco = (CSI_VALUE / pll3m) * ((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/0x1FFF) +1 );
02742     break;
02743   }
02744   PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(pll3vco/(((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >>9)  + 1 )) ;
02745   PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(pll3vco/(((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >>16) + 1 )) ;
02746   PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(pll3vco/(((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >>24) + 1 )) ;
02747
02748 }
02749
02750 /**
02751 * @brief  Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency
02752   * @note   The PLL1 clock frequencies computed by this function is not the real
02753   *         frequency in the chip. It is calculated based on the predefined
02754   *         constant and the selected clock source:
02755   * @note     The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
02756   * @note   This function can be used by the user application to compute the
02757   *         baud-rate for the communication peripherals or configure other parameters.
02758   *
02759   * @note   Each time PLL1CLK changes, this function must be called to update the
02760   *         right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
02761   * @param  PLL1_Clocks structure.
02762   * @retval None
02763   */
02764 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks)
02765 {
02766   uint32_t   pllsource = 0, pll1m = 1, pll1fracen = 0, hsivalue=0;
02767   float fracn1, pll1vco =0;
02768
02769   pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
02770   pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4);
02771   pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
02772   fracn1 = (pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
02773   switch (pllsource)
02774   {
02775
02776   case 0x00:  /* HSI used as PLL clock source */
02777
02778     if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
02779     {
02780       hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
02781       pll1vco = (hsivalue / pll1m) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x1FFF) +1 );
02782     }
02783     else
02784     {
02785       pll1vco = (HSI_VALUE / pll1m) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x1FFF) +1 );
02786     }
02787     break;
02788   case 0x01:  /* CSI used as PLL clock source */
02789     pll1vco = (CSI_VALUE / pll1m) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x1FFF) +1 );
02790     break;
02791
02792   case 0x02:  /* HSE used as PLL clock source */
02793     pll1vco = (HSE_VALUE / pll1m) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x1FFF) +1 );
02794     break;
02795
02796   default:
02797     pll1vco = (CSI_VALUE / pll1m) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x1FFF) +1 );
02798     break;
02799   }
02800
02801   PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(pll1vco/(((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9)  + 1 )) ;
02802   PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(pll1vco/(((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >>16) + 1 )) ;
02803   PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(pll1vco/(((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >>24) + 1 )) ;
02804
02805 }
02806
02807 /**
02808   * @brief  Returns the main Core frequency
02809   * @note   Each time core clock changes, this function must be called to update the
02810   *         right system core clock value. Otherwise, any configuration based on this function will be incorrect.
02811   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
02812   *         and updated within this function
02813   * @retval HCLK frequency
02814   */
02815 uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
02816 {
02817   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> POSITION_VAL(RCC_D1CFGR_D1CPRE_0)];
02818   return SystemCoreClock;
02819 }
02820
02821 /**
02822   * @brief  Enables the LSE Clock Security System.
02823   * @note   Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
02824   *         with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
02825   *         clock with HAL_RCCEx_PeriphCLKConfig().
02826   * @retval None
02827   */
02828 void HAL_RCCEx_EnableLSECSS(void)
02829 {
02830   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
02831 }
02832
02833 /**
02834   * @brief  Disables the LSE Clock Security System.
02835   * @note   LSE Clock Security System can only be disabled after a LSE failure detection.
02836   * @retval None
02837   */
02838 void HAL_RCCEx_DisableLSECSS(void)
02839 {
02840   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
02841   /* Disable LSE CSS IT if any */
02842   __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
02843 }
02844
02845 /**
02846   * @brief  Configure the oscillator clock source for wakeup from Stop and CSS backup clock
02847   * @param  WakeUpClk: Wakeup clock
02848   *         This parameter can be one of the following values:
02849   *            @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection
02850   *            @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection
02851   * @note   This function shall not be called after the Clock Security System on HSE has been
02852   *         enabled.
02853   * @retval None
02854   */
02855 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
02856 {
02857   assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
02858
02859   __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
02860 }
02861
02862 /**
02863   * @brief  Configure the oscillator Kernel clock source for wakeup from Stop
02864   * @param  WakeUpClk: Kernel Wakeup clock
02865   *         This parameter can be one of the following values:
02866   *            @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection
02867   *            @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection
02868   * @retval None
02869   */
02870 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
02871 {
02872   assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk));
02873
02874   __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk);
02875 }
02876
02877
02878
02879 /**
02880   * @brief  Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs
02881   * @param  RCC_WWDGx: WWDGx to be configured
02882   *         This parameter can be one of the following values:
02883   *            @arg RCC_WWDG1: WWDG1 generates system reset
02884   * @note   This bit can be set by software but is cleared by hardware during a system reset
02885   *
02886   * @retval None
02887   */
02888 void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
02889 {
02890   assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));
02891   SET_BIT(RCC->GCR, RCC_WWDGx) ;
02892 }
02893
02894
02895
02896 /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
02897  *  @brief  Extended Clock Recovery System Control functions
02898  *
02899 @verbatim
02900  ===============================================================================
02901                 ##### Extended Clock Recovery System Control functions  #####
02902  ===============================================================================
02903     [..]
02904       For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
02905
02906       (#) In System clock config, HSI48 needs to be enabled
02907
02908       (#) Enable CRS clock in IP MSP init which will use CRS functions
02909
02910       (#) Call CRS functions as follows:
02911           (##) Prepare synchronization configuration necessary for HSI48 calibration
02912               (+++) Default values can be set for frequency Error Measurement (reload and error limit)
02913                         and also HSI48 oscillator smooth trimming.
02914               (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
02915                         directly reload value with target and synchronization frequencies values
02916           (##) Call function HAL_RCCEx_CRSConfig which
02917               (+++) Resets CRS registers to their default values.
02918               (+++) Configures CRS registers with synchronization configuration
02919               (+++) Enables automatic calibration and frequency error counter feature
02920            Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
02921            periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
02922            provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
02923            precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
02924            should be used as SYNC signal.
02925
02926           (##) A polling function is provided to wait for complete synchronization
02927               (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
02928               (+++) According to CRS status, user can decide to adjust again the calibration or continue
02929                         application if synchronization is OK
02930
02931       (#) User can retrieve information related to synchronization in calling function
02932             HAL_RCCEx_CRSGetSynchronizationInfo()
02933
02934       (#) Regarding synchronization status and synchronization information, user can try a new calibration
02935            in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
02936            Note: When the SYNC event is detected during the down-counting phase (before reaching the zero value),
02937            it means that the actual frequency is lower than the target (and so, that the TRIM value should be
02938            incremented), while when it is detected during the up-counting phase it means that the actual frequency
02939            is higher (and that the TRIM value should be decremented).
02940
02941       (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
02942           through CRS Handler (CRS_IRQn/CRS_IRQHandler)
02943               (++) Call function HAL_RCCEx_CRSConfig()
02944               (++) Enable CRS_IRQn (thanks to NVIC functions)
02945               (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
02946               (++) Implement CRS status management in the following user callbacks called from
02947                    HAL_RCCEx_CRS_IRQHandler():
02948                    (+++) HAL_RCCEx_CRS_SyncOkCallback()
02949                    (+++) HAL_RCCEx_CRS_SyncWarnCallback()
02950                    (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
02951                    (+++) HAL_RCCEx_CRS_ErrorCallback()
02952
02953       (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
02954           This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
02955
02956 @endverbatim
02957  * @{
02958  */
02959
02960 /**
02961   * @brief  Start automatic synchronization for polling mode
02962   * @param  pInit Pointer on RCC_CRSInitTypeDef structure
02963   * @retval None
02964   */
02965 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
02966 {
02967   uint32_t value = 0;
02968
02969   /* Check the parameters */
02970   assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
02971   assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
02972   assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
02973   assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
02974   assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
02975   assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
02976
02977   /* CONFIGURATION */
02978
02979   /* Before configuration, reset CRS registers to their default values*/
02980   __HAL_RCC_CRS_FORCE_RESET();
02981   __HAL_RCC_CRS_RELEASE_RESET();
02982
02983   /* Set the SYNCDIV[2:0] bits according to Pre-scaler value */
02984   /* Set the SYNCSRC[1:0] bits according to Source value */
02985   /* Set the SYNCSPOL bit according to Polarity value */
02986   value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
02987   /* Set the RELOAD[15:0] bits according to ReloadValue value */
02988   value |= pInit->ReloadValue;
02989   /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
02990   value |= (pInit->ErrorLimitValue << POSITION_VAL(CRS_CFGR_FELIM));
02991   WRITE_REG(CRS->CFGR, value);
02992
02993   /* Adjust HSI48 oscillator smooth trimming */
02994   /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
02995   MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << POSITION_VAL(CRS_CR_TRIM)));
02996
02997   /* START AUTOMATIC SYNCHRONIZATION*/
02998
02999   /* Enable Automatic trimming & Frequency error counter */
03000   SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
03001 }
03002
03003 /**
03004   * @brief  Generate the software synchronization event
03005   * @retval None
03006   */
03007 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
03008 {
03009   SET_BIT(CRS->CR, CRS_CR_SWSYNC);
03010 }
03011
03012 /**
03013   * @brief  Return synchronization info
03014   * @param  pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
03015   * @retval None
03016   */
03017 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
03018 {
03019   /* Check the parameter */
03020   assert_param(pSynchroInfo != NULL);
03021
03022   /* Get the reload value */
03023   pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
03024
03025   /* Get HSI48 oscillator smooth trimming */
03026   pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> POSITION_VAL(CRS_CR_TRIM));
03027
03028   /* Get Frequency error capture */
03029   pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> POSITION_VAL(CRS_ISR_FECAP));
03030
03031   /* Get Frequency error direction */
03032   pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
03033 }
03034
03035 /**
03036 * @brief Wait for CRS Synchronization status.
03037 * @param Timeout  Duration of the time-out
03038 * @note  Timeout is based on the maximum time to receive a SYNC event based on synchronization
03039 *        frequency.
03040 * @note    If Time-out set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
03041 * @retval Combination of Synchronization status
03042 *          This parameter can be a combination of the following values:
03043 *            @arg @ref RCC_CRS_TIMEOUT
03044 *            @arg @ref RCC_CRS_SYNCOK
03045 *            @arg @ref RCC_CRS_SYNCWARN
03046 *            @arg @ref RCC_CRS_SYNCERR
03047 *            @arg @ref RCC_CRS_SYNCMISS
03048 *            @arg @ref RCC_CRS_TRIMOVF
03049 */
03050 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
03051 {
03052   uint32_t crsstatus = RCC_CRS_NONE;
03053   uint32_t tickstart = 0U;
03054
03055   /* Get time-out */
03056   tickstart = HAL_GetTick();
03057
03058   /* Wait for CRS flag or time-out detection */
03059   do
03060   {
03061     if(Timeout != HAL_MAX_DELAY)
03062     {
03063       if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
03064       {
03065         crsstatus = RCC_CRS_TIMEOUT;
03066       }
03067     }
03068     /* Check CRS SYNCOK flag  */
03069     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
03070     {
03071       /* CRS SYNC event OK */
03072       crsstatus |= RCC_CRS_SYNCOK;
03073
03074       /* Clear CRS SYNC event OK bit */
03075       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
03076     }
03077
03078     /* Check CRS SYNCWARN flag  */
03079     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
03080     {
03081       /* CRS SYNC warning */
03082       crsstatus |= RCC_CRS_SYNCWARN;
03083
03084       /* Clear CRS SYNCWARN bit */
03085       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
03086     }
03087
03088     /* Check CRS TRIM overflow flag  */
03089     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
03090     {
03091       /* CRS SYNC Error */
03092       crsstatus |= RCC_CRS_TRIMOVF;
03093
03094       /* Clear CRS Error bit */
03095       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
03096     }
03097
03098     /* Check CRS Error flag  */
03099     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
03100     {
03101       /* CRS SYNC Error */
03102       crsstatus |= RCC_CRS_SYNCERR;
03103
03104       /* Clear CRS Error bit */
03105       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
03106     }
03107
03108     /* Check CRS SYNC Missed flag  */
03109     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
03110     {
03111       /* CRS SYNC Missed */
03112       crsstatus |= RCC_CRS_SYNCMISS;
03113
03114       /* Clear CRS SYNC Missed bit */
03115       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
03116     }
03117
03118     /* Check CRS Expected SYNC flag  */
03119     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
03120     {
03121       /* frequency error counter reached a zero value */
03122       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
03123     }
03124   } while(RCC_CRS_NONE == crsstatus);
03125
03126   return crsstatus;
03127 }
03128
03129 /**
03130   * @brief Handle the Clock Recovery System interrupt request.
03131   * @retval None
03132   */
03133 void HAL_RCCEx_CRS_IRQHandler(void)
03134 {
03135   uint32_t crserror = RCC_CRS_NONE;
03136   /* Get current IT flags and IT sources values */
03137   uint32_t itflags = READ_REG(CRS->ISR);
03138   uint32_t itsources = READ_REG(CRS->CR);
03139
03140   /* Check CRS SYNCOK flag  */
03141   if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET))
03142   {
03143     /* Clear CRS SYNC event OK flag */
03144     WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
03145
03146     /* user callback */
03147     HAL_RCCEx_CRS_SyncOkCallback();
03148   }
03149   /* Check CRS SYNCWARN flag  */
03150   else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RESET))
03151   {
03152     /* Clear CRS SYNCWARN flag */
03153     WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
03154
03155     /* user callback */
03156     HAL_RCCEx_CRS_SyncWarnCallback();
03157   }
03158   /* Check CRS Expected SYNC flag  */
03159   else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET))
03160   {
03161     /* frequency error counter reached a zero value */
03162     WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
03163
03164     /* user callback */
03165     HAL_RCCEx_CRS_ExpectedSyncCallback();
03166   }
03167   /* Check CRS Error flags  */
03168   else
03169   {
03170     if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET))
03171     {
03172       if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET)
03173       {
03174         crserror |= RCC_CRS_SYNCERR;
03175       }
03176       if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET)
03177       {
03178         crserror |= RCC_CRS_SYNCMISS;
03179       }
03180       if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET)
03181       {
03182         crserror |= RCC_CRS_TRIMOVF;
03183       }
03184
03185       /* Clear CRS Error flags */
03186       WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
03187
03188       /* user error callback */
03189       HAL_RCCEx_CRS_ErrorCallback(crserror);
03190     }
03191   }
03192 }
03193
03194 /**
03195   * @brief  RCCEx Clock Recovery System SYNCOK interrupt callback.
03196   * @retval none
03197   */
03198 __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
03199 {
03200   /* NOTE : This function should not be modified, when the callback is needed,
03201             the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
03202    */
03203 }
03204
03205 /**
03206   * @brief  RCCEx Clock Recovery System SYNCWARN interrupt callback.
03207   * @retval none
03208   */
03209 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
03210 {
03211   /* NOTE : This function should not be modified, when the callback is needed,
03212             the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
03213    */
03214 }
03215
03216 /**
03217   * @brief  RCCEx Clock Recovery System Expected SYNC interrupt callback.
03218   * @retval none
03219   */
03220 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
03221 {
03222   /* NOTE : This function should not be modified, when the callback is needed,
03223             the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
03224    */
03225 }
03226
03227 /**
03228   * @brief  RCCEx Clock Recovery System Error interrupt callback.
03229   * @param  Error Combination of Error status.
03230   *         This parameter can be a combination of the following values:
03231   *           @arg @ref RCC_CRS_SYNCERR
03232   *           @arg @ref RCC_CRS_SYNCMISS
03233   *           @arg @ref RCC_CRS_TRIMOVF
03234   * @retval none
03235   */
03236 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
03237 {
03238   /* Prevent unused argument(s) compilation warning */
03239   UNUSED(Error);
03240
03241   /* NOTE : This function should not be modified, when the callback is needed,
03242             the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
03243    */
03244 }
03245
03246
03247 /**
03248   * @}
03249   */
03250
03251 /**
03252   * @}
03253   */
03254
03255 /** @defgroup RCCEx_Private_functions Private Functions
03256  * @{
03257  */
03258
03259
03260
03261 /**
03262   * @brief  Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it
03263   * @param  pll2: Pointer to an RCC_PLL2InitTypeDef structure that
03264   *         contains the configuration parameters  as well as VCI, VCO clock ranges.
03265   * @note   PLL2 is temporary disable to apply new parameters
03266   *
03267   * @retval HAL status
03268   */
03269 static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2)
03270 {
03271
03272   uint32_t tickstart = 0;
03273   HAL_StatusTypeDef status = HAL_OK;
03274   assert_param(IS_RCC_PLL2M_VALUE(pll2->PLL2M));
03275   assert_param(IS_RCC_PLL2N_VALUE(pll2->PLL2N));
03276   assert_param(IS_RCC_PLL2P_VALUE(pll2->PLL2P));
03277   assert_param(IS_RCC_PLL2R_VALUE(pll2->PLL2R));
03278   assert_param(IS_RCC_PLL2Q_VALUE(pll2->PLL2Q));
03279
03280   /* Check that PLL2 OSC clock source is already set */
03281   if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
03282   {
03283     return HAL_ERROR;
03284   }
03285
03286
03287   else
03288   {
03289     /* Disable  PLL2. */
03290     __HAL_RCC_PLL2_DISABLE();
03291
03292     /* Get Start Tick*/
03293     tickstart = HAL_GetTick();
03294
03295     /* Wait till PLL is ready */
03296     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
03297     {
03298       if((int32_t) (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
03299       {
03300         return HAL_TIMEOUT;
03301       }
03302     }
03303
03304     /* Configure PLL2 multiplication and division factors. */
03305     __HAL_RCC_PLL2_CONFIG(pll2->PLL2M,
03306                           pll2->PLL2N,
03307                           pll2->PLL2P,
03308                           pll2->PLL2Q,
03309                           pll2->PLL2R);
03310
03311     /* Select PLL2 input reference frequency range: VCI */
03312     __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ;
03313
03314     /* Select PLL2 output frequency range : VCO */
03315     __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ;
03316
03317
03318     /* Enable  PLL2. */
03319     __HAL_RCC_PLL2_ENABLE();
03320
03321     /* Get Start Tick*/
03322     tickstart = HAL_GetTick();
03323
03324     /* Wait till PLL2 is ready */
03325     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
03326     {
03327       if((int32_t) (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
03328       {
03329         return HAL_TIMEOUT;
03330       }
03331     }
03332
03333   }
03334
03335
03336   return status;
03337 }
03338
03339
03340 /**
03341   * @brief  Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it
03342   * @param  pll3: Pointer to an RCC_PLL3InitTypeDef structure that
03343   *         contains the configuration parameters  as well as VCI, VCO clock ranges.
03344   * @note   PLL3 is temporary disable to apply new parameters
03345   *
03346   * @retval HAL status
03347   */
03348 static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3)
03349 {
03350
03351   uint32_t tickstart = 0;
03352   HAL_StatusTypeDef status = HAL_OK;
03353   assert_param(IS_RCC_PLL3M_VALUE(pll3->PLL3M));
03354   assert_param(IS_RCC_PLL3N_VALUE(pll3->PLL3N));
03355   assert_param(IS_RCC_PLL3P_VALUE(pll3->PLL3P));
03356   assert_param(IS_RCC_PLL3R_VALUE(pll3->PLL3R));
03357   assert_param(IS_RCC_PLL3Q_VALUE(pll3->PLL3Q));
03358
03359   /* Check that PLL3 OSC clock source is already set */
03360   if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
03361   {
03362     return HAL_ERROR;
03363   }
03364
03365
03366   else
03367   {
03368     /* Disable  PLL3. */
03369     __HAL_RCC_PLL3_DISABLE();
03370
03371     /* Get Start Tick*/
03372     tickstart = HAL_GetTick();
03373     /* Wait till PLL3 is ready */
03374     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != RESET)
03375     {
03376       if((int32_t) (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
03377       {
03378         return HAL_TIMEOUT;
03379       }
03380     }
03381
03382     /* Configure the PLL3  multiplication and division factors. */
03383     __HAL_RCC_PLL3_CONFIG(pll3->PLL3M,
03384                           pll3->PLL3N,
03385                           pll3->PLL3P,
03386                           pll3->PLL3Q,
03387                           pll3->PLL3R);
03388
03389     /* Select PLL3 input reference frequency range: VCI */
03390     __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
03391
03392     /* Select PLL3 output frequency range : VCO */
03393     __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ;
03394
03395
03396     /* Enable  PLL3. */
03397     __HAL_RCC_PLL3_ENABLE();
03398
03399     /* Get Start Tick*/
03400     tickstart = HAL_GetTick();
03401
03402     /* Wait till PLL3 is ready */
03403     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == RESET)
03404     {
03405       if((int32_t) (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
03406       {
03407         return HAL_TIMEOUT;
03408       }
03409     }
03410
03411   }
03412
03413
03414   return status;
03415 }
03416
03417
03418
03419
03420 /**
03421   * @}
03422   */
03423
03424 /**
03425   * @}
03426   */
03427
03428 #endif /* HAL_RCC_MODULE_ENABLED */
03429 /**
03430   * @}
03431   */
03432
03433 /**
03434   * @}
03435   */
03436
03437 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
03438
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_rcc_ex.h Source File

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stm32h7xx_hal_rcc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rcc_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of RCC HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_RCC_EX_H
00040 #define __STM32H7xx_HAL_RCC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup RCCEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  PLL2 Clock structure definition
00064   */
00065 typedef struct
00066 {
00067
00068   uint32_t PLL2M;       /*!< PLL2M: Division factor for PLL2 VCO input clock.
00069                              This parameter must be a number between Min_Data = 1 and Max_Data = 63    */
00070
00071   uint32_t PLL2N;       /*!< PLL2N: Multiplication factor for PLL2 VCO output clock.
00072                              This parameter must be a number between Min_Data = 4 and Max_Data = 512   */
00073
00074   uint32_t PLL2P;       /*!< PLL2P: Division factor for system clock.
00075                              This parameter must be a number between Min_Data = 2 and Max_Data = 128
00076                              odd division factors are not allowed                                      */
00077
00078   uint32_t PLL2Q;        /*!< PLL2Q: Division factor for peripheral clocks.
00079                              This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
00080
00081   uint32_t PLL2R;        /*!< PLL2R: Division factor for peripheral clocks.
00082                              This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
00083   uint32_t PLL2RGE;      /*!<PLL2RGE: PLL2 clock Input range
00084                           This parameter must be a value of @ref RCC_PLL2_VCI_Range                    */
00085   uint32_t PLL2VCOSEL;   /*!<PLL2VCOSEL: PLL2 clock Output range
00086                           This parameter must be a value of @ref RCC_PLL2_VCO_Range                    */
00087
00088   uint32_t PLL2FRACN;    /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for
00089                             PLL2 VCO It should be a value between 0 and 8191                           */
00090 }RCC_PLL2InitTypeDef;
00091
00092
00093 /**
00094   * @brief  PLL3 Clock structure definition
00095   */
00096 typedef struct
00097 {
00098
00099   uint32_t PLL3M;       /*!< PLL3M: Division factor for PLL3 VCO input clock.
00100                              This parameter must be a number between Min_Data = 1 and Max_Data = 63    */
00101
00102   uint32_t PLL3N;       /*!< PLL3N: Multiplication factor for PLL3 VCO output clock.
00103                              This parameter must be a number between Min_Data = 4 and Max_Data = 512   */
00104
00105   uint32_t PLL3P;       /*!< PLL3P: Division factor for system clock.
00106                              This parameter must be a number between Min_Data = 2 and Max_Data = 128
00107                              odd division factors are not allowed                                      */
00108
00109   uint32_t PLL3Q;        /*!< PLL3Q: Division factor for peripheral clocks.
00110                              This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
00111
00112   uint32_t PLL3R;        /*!< PLL3R: Division factor for peripheral clocks.
00113                              This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
00114   uint32_t PLL3RGE;      /*!<PLL3RGE: PLL3 clock Input range
00115                           This parameter must be a value of @ref RCC_PLL3_VCI_Range                    */
00116   uint32_t PLL3VCOSEL;   /*!<PLL3VCOSEL: PLL3 clock Output range
00117                           This parameter must be a value of @ref RCC_PLL3_VCO_Range                    */
00118
00119   uint32_t PLL3FRACN;    /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for
00120                             PLL3 VCO It should be a value between 0 and 8191                           */
00121 }RCC_PLL3InitTypeDef;
00122
00123 /**
00124   * @brief  RCC PLL1 Clocks structure definition
00125   */
00126 typedef struct
00127 {
00128   uint32_t PLL1_P_Frequency;
00129   uint32_t PLL1_Q_Frequency;
00130   uint32_t PLL1_R_Frequency;
00131 }PLL1_ClocksTypeDef;
00132
00133 /**
00134   * @brief  RCC PLL2 Clocks structure definition
00135   */
00136 typedef struct
00137 {
00138   uint32_t PLL2_P_Frequency;
00139   uint32_t PLL2_Q_Frequency;
00140   uint32_t PLL2_R_Frequency;
00141 }PLL2_ClocksTypeDef;
00142
00143 /**
00144   * @brief  RCC PLL3 Clocks structure definition
00145   */
00146 typedef struct
00147 {
00148   uint32_t PLL3_P_Frequency;
00149   uint32_t PLL3_Q_Frequency;
00150   uint32_t PLL3_R_Frequency;
00151 }PLL3_ClocksTypeDef;
00152
00153
00154 /**
00155   * @brief  RCC extended clocks structure definition
00156   */
00157 typedef struct
00158 {
00159   uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
00160                                         This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00161
00162   RCC_PLL2InitTypeDef PLL2;        /*!< PLL2structure parameters.
00163                                         This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */
00164
00165   RCC_PLL3InitTypeDef PLL3;        /*!< PLL3 structure parameters.
00166                                         This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */
00167
00168   uint32_t FmcClockSelection;     /*!< Specifies FMC clock source
00169                                         This parameter can be a value of @ref RCCEx_FMC_Clock_Source     */
00170
00171   uint32_t QspiClockSelection;    /*!< Specifies QSPI clock source
00172                                         This parameter can be a value of @ref RCCEx_QSPI_Clock_Source    */
00173
00174   uint32_t SdmmcClockSelection;    /*!< Specifies SDMMC clock source
00175                                         This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source   */
00176
00177   uint32_t CkperClockSelection;   /*!< Specifies CKPER clock source
00178                                         This parameter can be a value of @ref RCCEx_CLKP_Clock_Source   */
00179
00180   uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 clock source
00181                                         This parameter can be a value of @ref RCCEx_SAI1_Clock_Source    */
00182
00183   uint32_t Sai2ClockSelection;     /*!< Specifies SAI2 clock source
00184                                         This parameter can be a value of @ref RCCEx_SAI2_Clock_Source    */
00185
00186   uint32_t Sai3ClockSelection;     /*!< Specifies SAI3 clock source
00187                                         This parameter can be a value of @ref RCCEx_SAI3_Clock_Source    */
00188
00189   uint32_t Spi1ClockSelection;     /*!< Specifies SPI1 clock source
00190                                         This parameter can be a value of @ref RCCEx_SPI1_Clock_Source    */
00191
00192   uint32_t Spi2ClockSelection;     /*!< Specifies SPI2 clock source
00193                                         This parameter can be a value of @ref RCCEx_SPI2_Clock_Source    */
00194
00195   uint32_t Spi3ClockSelection;     /*!< Specifies SPI3 clock source
00196                                         This parameter can be a value of @ref RCCEx_SPI3_Clock_Source    */
00197
00198   uint32_t Spi4ClockSelection;     /*!< Specifies SPI4 clock source
00199                                         This parameter can be a value of @ref RCCEx_SPI4_Clock_Source    */
00200
00201   uint32_t Spi5ClockSelection;     /*!< Specifies SPI5 clock source
00202                                         This parameter can be a value of @ref RCCEx_SPI5_Clock_Source    */
00203
00204   uint32_t SpdifrxClockSelection;   /*!< Specifies SPDIFRX Clock clock source
00205                                         This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
00206
00207   uint32_t Dfsdm1ClockSelection;    /*!< Specifies DFSDM1 Clock clock source
00208                                         This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source  */
00209 #if defined(FDCAN1) || defined(FDCAN2)
00210   uint32_t FdcanClockSelection;   /*!< Specifies FDCAN Clock clock source
00211                                         This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source   */
00212 #endif /*FDCAN1 || FDCAN2*/
00213
00214   uint32_t Swpmi1ClockSelection;   /*!< Specifies SWPMI1 Clock clock source
00215                                         This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source  */
00216
00217   uint32_t Usart2ClockSelection;   /*!< Specifies USART2 clock source
00218                                         This parameter can be a value of @ref RCCEx_USART2_Clock_Source  */
00219
00220   uint32_t Usart3ClockSelection;   /*!< Specifies USART3 clock source
00221                                         This parameter can be a value of @ref RCCEx_USART3_Clock_Source  */
00222
00223   uint32_t Uart4ClockSelection;    /*!< Specifies UART4 clock source
00224                                         This parameter can be a value of @ref RCCEx_UART4_Clock_Source   */
00225
00226   uint32_t Uart5ClockSelection;    /*!< Specifies UART5 clock source
00227                                         This parameter can be a value of @ref RCCEx_UART5_Clock_Source   */
00228
00229   uint32_t UART7ClockSelection;    /*!< Specifies UART7 clock source
00230                                         This parameter can be a value of @ref RCCEx_UART7_Clock_Source   */
00231
00232   uint32_t UART8ClockSelection;    /*!< Specifies UART8 clock source
00233                                         This parameter can be a value of @ref RCCEx_UART8_Clock_Source   */
00234
00235   uint32_t Usart1ClockSelection;   /*!< Specifies USART1 clock source
00236                                         This parameter can be a value of @ref RCCEx_USART1_Clock_Source  */
00237
00238    uint32_t Usart6ClockSelection;    /*!< Specifies USART6 clock source
00239                                         This parameter can be a value of @ref RCCEx_USART6_Clock_Source  */
00240
00241    uint32_t RngClockSelection;      /*!< Specifies RNG clock source
00242                                         This parameter can be a value of @ref RCCEx_RNG_Clock_Source     */
00243
00244   uint32_t I2c1ClockSelection;     /*!< Specifies I2C1 clock source
00245                                         This parameter can be a value of @ref RCCEx_I2C1_Clock_Source    */
00246
00247   uint32_t I2c2ClockSelection;     /*!< Specifies I2C2 clock source
00248                                         This parameter can be a value of @ref RCCEx_I2C2_Clock_Source    */
00249
00250   uint32_t I2c3ClockSelection;     /*!< Specifies I2C3 clock source
00251                                         This parameter can be a value of @ref RCCEx_I2C3_Clock_Source    */
00252
00253   uint32_t UsbClockSelection;      /*!< Specifies USB clock source
00254                                         This parameter can be a value of @ref RCCEx_USB_Clock_Source     */
00255
00256   uint32_t CecClockSelection;     /*!< Specifies CEC clock source
00257                                         This parameter can be a value of @ref RCCEx_CEC_Clock_Source     */
00258
00259   uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source
00260                                         This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source  */
00261
00262   uint32_t Lpuart1ClockSelection;  /*!< Specifies LPUART1 clock source
00263                                         This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
00264
00265   uint32_t I2c4ClockSelection;     /*!< Specifies I2C4 clock source
00266                                         This parameter can be a value of @ref RCCEx_I2C4_Clock_Source    */
00267
00268   uint32_t Lptim2ClockSelection;   /*!< Specifies LPTIM2 clock source
00269                                         This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source  */
00270
00271   uint32_t Lptim3ClockSelection;   /*!< Specifies LPTIM3 clock source
00272                                         This parameter can be a value of @ref RCCEx_LPTIM3_Clock_Source  */
00273
00274   uint32_t Lptim4ClockSelection;   /*!< Specifies LPTIM4 clock source
00275                                         This parameter can be a value of @ref RCCEx_LPTIM4_Clock_Source  */
00276
00277   uint32_t Lptim5ClockSelection;   /*!< Specifies LPTIM5 clock source
00278                                         This parameter can be a value of @ref RCCEx_LPTIM5_Clock_Source  */
00279
00280   uint32_t AdcClockSelection;      /*!< Specifies ADC interface clock source
00281                                         This parameter can be a value of @ref RCCEx_ADC_Clock_Source     */
00282   uint32_t Sai4AClockSelection;     /*!< Specifies SAI4A clock source
00283                                         This parameter can be a value of @ref RCCEx_SAI4A_Clock_Source   */
00284
00285   uint32_t Sai4BClockSelection;     /*!< Specifies SAI4B clock source
00286                                         This parameter can be a value of @ref RCCEx_SAI4B_Clock_Source   */
00287
00288   uint32_t Spi6ClockSelection;     /*!< Specifies SPI6 clock source
00289                                         This parameter can be a value of @ref RCCEx_SPI6_Clock_Source    */
00290
00291   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock clock source
00292                                         This parameter can be a value of @ref RCC_RTC_Clock_Source       */
00293
00294   uint32_t Hrtim1ClockSelection;      /*!< Specifies HRTIM1 Clock clock source
00295                                         This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source   */
00296   uint32_t TIMPresSelection;       /*!< Specifies TIM Clock Prescalers Selection.
00297                                        This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
00298 }RCC_PeriphCLKInitTypeDef;
00299
00300
00301 /**
00302   * @brief RCC_CRS Init structure definition
00303   */
00304 typedef struct
00305 {
00306   uint32_t Prescaler;             /*!< Specifies the division factor of the SYNC signal.
00307                                      This parameter can be a value of @ref RCCEx_CRS_SynchroDivider  */
00308
00309   uint32_t Source;                /*!< Specifies the SYNC signal source.
00310                                      This parameter can be a value of @ref RCCEx_CRS_SynchroSource   */
00311
00312   uint32_t Polarity;              /*!< Specifies the input polarity for the SYNC signal source.
00313                                      This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
00314
00315   uint32_t ReloadValue;           /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
00316                                       It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
00317                                      This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
00318
00319   uint32_t ErrorLimitValue;       /*!< Specifies the value to be used to evaluate the captured frequency error value.
00320                                      This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
00321
00322   uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
00323                                      This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
00324
00325 }RCC_CRSInitTypeDef;
00326
00327 /**
00328   * @brief RCC_CRS Synchronization structure definition
00329   */
00330 typedef struct
00331 {
00332   uint32_t ReloadValue;           /*!< Specifies the value loaded in the Counter reload value.
00333                                      This parameter must be a number between 0 and 0xFFFF */
00334
00335   uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
00336                                      This parameter must be a number between 0 and 0x3F */
00337
00338   uint32_t FreqErrorCapture;      /*!< Specifies the value loaded in the .FECAP, the frequency error counter
00339                                                                     value latched in the time of the last SYNC event.
00340                                     This parameter must be a number between 0 and 0xFFFF */
00341
00342   uint32_t FreqErrorDirection;    /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
00343                                                                     frequency error counter latched in the time of the last SYNC event.
00344                                                                     It shows whether the actual frequency is below or above the target.
00345                                     This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
00346
00347 }RCC_CRSSynchroInfoTypeDef;
00348
00349 /**
00350   * @}
00351   */
00352
00353
00354 /* Exported constants --------------------------------------------------------*/
00355 /** @defgroup RCCEx_Exported_Constants  RCCEx Exported Constants
00356   * @{
00357   */
00358
00359 /** @defgroup RCCEx_Periph_Clock_Selection  RCCEx Periph Clock Selection
00360   * @{
00361   */
00362
00363 #define RCC_PERIPHCLK_USART1           ((uint32_t)0x00000001)
00364 #define RCC_PERIPHCLK_USART2           ((uint32_t)0x00000002)
00365 #define RCC_PERIPHCLK_USART3           ((uint32_t)0x00000004)
00366 #define RCC_PERIPHCLK_UART4            ((uint32_t)0x00000008)
00367 #define RCC_PERIPHCLK_UART5            ((uint32_t)0x00000010)
00368 #define RCC_PERIPHCLK_LPUART1          ((uint32_t)0x00000020)
00369 #define RCC_PERIPHCLK_I2C1             ((uint32_t)0x00000040)
00370 #define RCC_PERIPHCLK_I2C2             ((uint32_t)0x00000080)
00371 #define RCC_PERIPHCLK_I2C3             ((uint32_t)0x00000100)
00372 #define RCC_PERIPHCLK_LPTIM1           ((uint32_t)0x00000200)
00373 #define RCC_PERIPHCLK_LPTIM2           ((uint32_t)0x00000400)
00374 #define RCC_PERIPHCLK_SAI1             ((uint32_t)0x00000800)
00375 #define RCC_PERIPHCLK_SAI2             ((uint32_t)0x00001000)
00376 #define RCC_PERIPHCLK_USB              ((uint32_t)0x00002000)
00377 #define RCC_PERIPHCLK_ADC              ((uint32_t)0x00004000)
00378 #define RCC_PERIPHCLK_SWPMI1           ((uint32_t)0x00008000)
00379 #define RCC_PERIPHCLK_DFSDM1           ((uint32_t)0x00010000)
00380 #define RCC_PERIPHCLK_RTC              ((uint32_t)0x00020000)
00381 #define RCC_PERIPHCLK_CEC              ((uint32_t)0x00040000)
00382 #define RCC_PERIPHCLK_USART6           ((uint32_t)0x00080000)
00383 #define RCC_PERIPHCLK_UART7            ((uint32_t)0x00100000)
00384 #define RCC_PERIPHCLK_UART8            ((uint32_t)0x00200000)
00385 #define RCC_PERIPHCLK_I2C4             ((uint32_t)0x00400000)
00386 #define RCC_PERIPHCLK_LPTIM3           ((uint32_t)0x00800000)
00387 #define RCC_PERIPHCLK_LPTIM4           ((uint32_t)0x01000000)
00388 #define RCC_PERIPHCLK_LPTIM5           ((uint32_t)0x02000000)
00389 #define RCC_PERIPHCLK_SAI3             ((uint32_t)0x04000000)
00390 #define RCC_PERIPHCLK_SAI4A            ((uint32_t)0x08000000)
00391 #define RCC_PERIPHCLK_SAI4B            ((uint32_t)0x10000000)
00392 #define RCC_PERIPHCLK_FMC              ((uint32_t)0x20000000)
00393 #define RCC_PERIPHCLK_QSPI             ((uint32_t)0x40000000)
00394 #define RCC_PERIPHCLK_DSI              ((uint32_t)0x80000000)
00395 #define RCC_PERIPHCLK_CKPER            ((uint32_t)0x80000001)
00396 #define RCC_PERIPHCLK_SPDIFRX          ((uint32_t)0x80000002)
00397 #define RCC_PERIPHCLK_FDCAN            ((uint32_t)0x80000004)
00398 #define RCC_PERIPHCLK_SPI1             ((uint32_t)0x80000008)
00399 #define RCC_PERIPHCLK_SPI2             ((uint32_t)0x80000010)
00400 #define RCC_PERIPHCLK_SPI3             ((uint32_t)0x80000020)
00401 #define RCC_PERIPHCLK_SPI4             ((uint32_t)0x80000040)
00402 #define RCC_PERIPHCLK_SPI5             ((uint32_t)0x80000080)
00403 #define RCC_PERIPHCLK_SPI6             ((uint32_t)0x80000100)
00404 #define RCC_PERIPHCLK_SDMMC            ((uint32_t)0x80000200)
00405 #define RCC_PERIPHCLK_LTDC             ((uint32_t)0x80000400)
00406 #define RCC_PERIPHCLK_RNG              ((uint32_t)0x80000800)
00407 #define RCC_PERIPHCLK_HRTIM1           ((uint32_t)0x80001000)
00408 #define RCC_PERIPHCLK_TIM              ((uint32_t)0x80002000)
00409
00410
00411 /**
00412   * @}
00413   */
00414
00415
00416 /** @defgroup RCC_PLL2_Clock_Output  RCC PLL2 Clock Output
00417   * @{
00418   */
00419 #define RCC_PLL2_DIVP                RCC_PLLCFGR_DIVP2EN
00420 #define RCC_PLL2_DIVQ                RCC_PLLCFGR_DIVQ2EN
00421 #define RCC_PLL2_DIVR                RCC_PLLCFGR_DIVR2EN
00422
00423 /**
00424   * @}
00425   */
00426
00427 /** @defgroup RCC_PLL3_Clock_Output  RCC PLL3 Clock Output
00428   * @{
00429   */
00430 #define RCC_PLL3_DIVP                RCC_PLLCFGR_DIVP3EN
00431 #define RCC_PLL3_DIVQ                RCC_PLLCFGR_DIVQ3EN
00432 #define RCC_PLL3_DIVR                RCC_PLLCFGR_DIVR3EN
00433
00434 /**
00435   * @}
00436   */
00437
00438 /** @defgroup RCC_PLL2_VCI_Range  RCC PLL2 VCI Range
00439   * @{
00440   */
00441 #define RCC_PLL2VCIRANGE_0                RCC_PLLCFGR_PLL2RGE_0
00442 #define RCC_PLL2VCIRANGE_1                RCC_PLLCFGR_PLL2RGE_1
00443 #define RCC_PLL2VCIRANGE_2                RCC_PLLCFGR_PLL2RGE_2
00444 #define RCC_PLL2VCIRANGE_3                RCC_PLLCFGR_PLL2RGE_3
00445
00446 /**
00447   * @}
00448   */
00449
00450
00451 /** @defgroup RCC_PLL2_VCO_Range  RCC PLL2 VCO Range
00452   * @{
00453   */
00454 #define RCC_PLL2VCOWIDE                 ((uint32_t)0x00000000)
00455 #define RCC_PLL2VCOMEDIUM               RCC_PLLCFGR_PLL2VCOSEL
00456
00457 /**
00458   * @}
00459   */
00460
00461 /** @defgroup RCC_PLL3_VCI_Range  RCC PLL3 VCI Range
00462   * @{
00463   */
00464 #define RCC_PLL3VCIRANGE_0                RCC_PLLCFGR_PLL3RGE_0
00465 #define RCC_PLL3VCIRANGE_1                RCC_PLLCFGR_PLL3RGE_1
00466 #define RCC_PLL3VCIRANGE_2                RCC_PLLCFGR_PLL3RGE_2
00467 #define RCC_PLL3VCIRANGE_3                RCC_PLLCFGR_PLL3RGE_3
00468
00469 /**
00470   * @}
00471   */
00472
00473
00474 /** @defgroup RCC_PLL3_VCO_Range  RCC PLL3 VCO Range
00475   * @{
00476   */
00477 #define RCC_PLL3VCOWIDE                 ((uint32_t)0x00000000)
00478 #define RCC_PLL3VCOMEDIUM               RCC_PLLCFGR_PLL3VCOSEL
00479
00480 /**
00481   * @}
00482   */
00483
00484 /** @defgroup RCCEx_USART1_Clock_Source  RCCEx USART1 Clock Source
00485   * @{
00486   */
00487 #define RCC_USART1CLKSOURCE_D2PCLK2    ((uint32_t)0x00000000)
00488 #define RCC_USART1CLKSOURCE_PLL2      RCC_D2CCIP2R_USART16SEL_0
00489 #define RCC_USART1CLKSOURCE_PLL3      RCC_D2CCIP2R_USART16SEL_1
00490 #define RCC_USART1CLKSOURCE_HSI       (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
00491 #define RCC_USART1CLKSOURCE_CSI        RCC_D2CCIP2R_USART16SEL_2
00492 #define RCC_USART1CLKSOURCE_LSE       (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
00493
00494 /**
00495   * @}
00496   */
00497
00498 /** @defgroup RCCEx_USART2_Clock_Source  RCCEx USART2 Clock Source
00499   * @{
00500   */
00501 #define RCC_USART2CLKSOURCE_D2PCLK1    ((uint32_t)0x00000000)
00502 #define RCC_USART2CLKSOURCE_PLL2      RCC_D2CCIP2R_USART28SEL_0
00503 #define RCC_USART2CLKSOURCE_PLL3      RCC_D2CCIP2R_USART28SEL_1
00504 #define RCC_USART2CLKSOURCE_HSI       (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
00505 #define RCC_USART2CLKSOURCE_CSI        RCC_D2CCIP2R_USART28SEL_2
00506 #define RCC_USART2CLKSOURCE_LSE       (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
00507
00508
00509 /**
00510   * @}
00511   */
00512
00513 /** @defgroup RCCEx_USART3_Clock_Source  RCCEx USART3 Clock Source
00514   * @{
00515   */
00516 #define RCC_USART3CLKSOURCE_D2PCLK1    ((uint32_t)0x00000000)
00517 #define RCC_USART3CLKSOURCE_PLL2      RCC_D2CCIP2R_USART28SEL_0
00518 #define RCC_USART3CLKSOURCE_PLL3      RCC_D2CCIP2R_USART28SEL_1
00519 #define RCC_USART3CLKSOURCE_HSI       (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
00520 #define RCC_USART3CLKSOURCE_CSI        RCC_D2CCIP2R_USART28SEL_2
00521 #define RCC_USART3CLKSOURCE_LSE       (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
00522
00523
00524 /**
00525   * @}
00526   */
00527
00528 /** @defgroup RCCEx_UART4_Clock_Source  RCCEx UART4 Clock Source
00529   * @{
00530   */
00531 #define RCC_UART4CLKSOURCE_D2PCLK1    ((uint32_t)0x00000000)
00532 #define RCC_UART4CLKSOURCE_PLL2      RCC_D2CCIP2R_USART28SEL_0
00533 #define RCC_UART4CLKSOURCE_PLL3      RCC_D2CCIP2R_USART28SEL_1
00534 #define RCC_UART4CLKSOURCE_HSI       (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
00535 #define RCC_UART4CLKSOURCE_CSI        RCC_D2CCIP2R_USART28SEL_2
00536 #define RCC_UART4CLKSOURCE_LSE       (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
00537
00538 /**
00539   * @}
00540   */
00541
00542 /** @defgroup RCCEx_UART5_Clock_Source  RCCEx UART5 Clock Source
00543   * @{
00544   */
00545 #define RCC_UART5CLKSOURCE_D2PCLK1    ((uint32_t)0x00000000)
00546 #define RCC_UART5CLKSOURCE_PLL2      RCC_D2CCIP2R_USART28SEL_0
00547 #define RCC_UART5CLKSOURCE_PLL3      RCC_D2CCIP2R_USART28SEL_1
00548 #define RCC_UART5CLKSOURCE_HSI       (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
00549 #define RCC_UART5CLKSOURCE_CSI        RCC_D2CCIP2R_USART28SEL_2
00550 #define RCC_UART5CLKSOURCE_LSE       (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
00551
00552
00553 /**
00554   * @}
00555   */
00556
00557 /** @defgroup RCCEx_USART6_Clock_Source  RCCEx USART6 Clock Source
00558   * @{
00559   */
00560 #define RCC_USART6CLKSOURCE_D2PCLK2    ((uint32_t)0x00000000)
00561 #define RCC_USART6CLKSOURCE_PLL2      RCC_D2CCIP2R_USART16SEL_0
00562 #define RCC_USART6CLKSOURCE_PLL3      RCC_D2CCIP2R_USART16SEL_1
00563 #define RCC_USART6CLKSOURCE_HSI       (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
00564 #define RCC_USART6CLKSOURCE_CSI        RCC_D2CCIP2R_USART16SEL_2
00565 #define RCC_USART6CLKSOURCE_LSE       (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
00566
00567
00568 /**
00569   * @}
00570   */
00571
00572 /** @defgroup RCCEx_UART7_Clock_Source  RCCEx UART7 Clock Source
00573   * @{
00574   */
00575 #define RCC_UART7CLKSOURCE_D2PCLK1    ((uint32_t)0x00000000)
00576 #define RCC_UART7CLKSOURCE_PLL2      RCC_D2CCIP2R_USART28SEL_0
00577 #define RCC_UART7CLKSOURCE_PLL3      RCC_D2CCIP2R_USART28SEL_1
00578 #define RCC_UART7CLKSOURCE_HSI       (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
00579 #define RCC_UART7CLKSOURCE_CSI        RCC_D2CCIP2R_USART28SEL_2
00580 #define RCC_UART7CLKSOURCE_LSE       (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
00581
00582
00583 /**
00584   * @}
00585   */
00586 /** @defgroup RCCEx_UART8_Clock_Source  RCCEx UART8 Clock Source
00587   * @{
00588   */
00589 #define RCC_UART8CLKSOURCE_D2PCLK1    ((uint32_t)0x00000000)
00590 #define RCC_UART8CLKSOURCE_PLL2      RCC_D2CCIP2R_USART28SEL_0
00591 #define RCC_UART8CLKSOURCE_PLL3      RCC_D2CCIP2R_USART28SEL_1
00592 #define RCC_UART8CLKSOURCE_HSI       (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
00593 #define RCC_UART8CLKSOURCE_CSI        RCC_D2CCIP2R_USART28SEL_2
00594 #define RCC_UART8CLKSOURCE_LSE       (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
00595
00596
00597 /**
00598   * @}
00599   */
00600
00601
00602 /** @defgroup RCCEx_LPUART1_Clock_Source  RCCEx LPUART1 Clock Source
00603   * @{
00604   */
00605 #define RCC_LPUART1CLKSOURCE_D3PCLK1    ((uint32_t)0x00000000)
00606 #define RCC_LPUART1CLKSOURCE_PLL2      RCC_D3CCIPR_LPUART1SEL_0
00607 #define RCC_LPUART1CLKSOURCE_PLL3      RCC_D3CCIPR_LPUART1SEL_1
00608 #define RCC_LPUART1CLKSOURCE_HSI       (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)
00609 #define RCC_LPUART1CLKSOURCE_CSI        RCC_D3CCIPR_LPUART1SEL_2
00610 #define RCC_LPUART1CLKSOURCE_LSE       (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0)
00611
00612
00613 /**
00614   * @}
00615   */
00616
00617 /** @defgroup RCCEx_I2C1_Clock_Source  RCCEx I2C1 Clock Source
00618   * @{
00619   */
00620 #define RCC_I2C1CLKSOURCE_D2PCLK1      ((uint32_t)0x00000000)
00621 #define RCC_I2C1CLKSOURCE_PLL3         RCC_D2CCIP2R_I2C123SEL_0
00622 #define RCC_I2C1CLKSOURCE_HSI          RCC_D2CCIP2R_I2C123SEL_1
00623 #define RCC_I2C1CLKSOURCE_CSI         (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
00624
00625
00626 /**
00627   * @}
00628   */
00629
00630
00631 /** @defgroup RCCEx_I2C2_Clock_Source  RCCEx I2C2 Clock Source
00632   * @{
00633   */
00634 #define RCC_I2C2CLKSOURCE_D2PCLK1      ((uint32_t)0x00000000)
00635 #define RCC_I2C2CLKSOURCE_PLL3         RCC_D2CCIP2R_I2C123SEL_0
00636 #define RCC_I2C2CLKSOURCE_HSI          RCC_D2CCIP2R_I2C123SEL_1
00637 #define RCC_I2C2CLKSOURCE_CSI         (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
00638
00639
00640 /**
00641   * @}
00642   */
00643
00644
00645 /** @defgroup RCCEx_I2C3_Clock_Source  RCCEx I2C3 Clock Source
00646   * @{
00647   */
00648 #define RCC_I2C3CLKSOURCE_D2PCLK1      ((uint32_t)0x00000000)
00649 #define RCC_I2C3CLKSOURCE_PLL3         RCC_D2CCIP2R_I2C123SEL_0
00650 #define RCC_I2C3CLKSOURCE_HSI          RCC_D2CCIP2R_I2C123SEL_1
00651 #define RCC_I2C3CLKSOURCE_CSI         (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
00652
00653
00654 /**
00655   * @}
00656   */
00657
00658
00659 /** @defgroup RCCEx_I2C4_Clock_Source  RCCEx I2C4 Clock Source
00660   * @{
00661   */
00662 #define RCC_I2C4CLKSOURCE_D3PCLK1      ((uint32_t)0x00000000)
00663 #define RCC_I2C4CLKSOURCE_PLL3         RCC_D3CCIPR_I2C4SEL_0
00664 #define RCC_I2C4CLKSOURCE_HSI          RCC_D3CCIPR_I2C4SEL_1
00665 #define RCC_I2C4CLKSOURCE_CSI         (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)
00666
00667
00668 /**
00669   * @}
00670   */
00671
00672 /** @defgroup RCCEx_RNG_Clock_Source  RCCEx RNG Clock Source
00673   * @{
00674   */
00675 #define RCC_RNGCLKSOURCE_HSI48        ((uint32_t)0x00000000)
00676 #define RCC_RNGCLKSOURCE_PLL           RCC_D2CCIP2R_RNGSEL_0
00677 #define RCC_RNGCLKSOURCE_LSE           RCC_D2CCIP2R_RNGSEL_1
00678 #define RCC_RNGCLKSOURCE_LSI           RCC_D2CCIP2R_RNGSEL
00679
00680
00681 /**
00682   * @}
00683   */
00684
00685 /** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
00686   * @{
00687   */
00688 #define RCC_HRTIM1CLK_TIMCLK                ((uint32_t)0x00000000)
00689 #define RCC_HRTIM1CLK_CPUCLK                RCC_CFGR_HRTIMSEL
00690
00691 /**
00692   * @}
00693   */
00694
00695
00696 #define RCC_USBCLKSOURCE_PLL                  RCC_D2CCIP2R_USBSEL_0
00697 #define RCC_USBCLKSOURCE_PLL3                 RCC_D2CCIP2R_USBSEL_1
00698 #define RCC_USBCLKSOURCE_HSI48                RCC_D2CCIP2R_USBSEL
00699
00700
00701 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
00702   * @{
00703   */
00704 #define RCC_SAI1CLKSOURCE_PLL         ((uint32_t)0x00000000)
00705 #define RCC_SAI1CLKSOURCE_PLL2         RCC_D2CCIP1R_SAI1SEL_0
00706 #define RCC_SAI1CLKSOURCE_PLL3         RCC_D2CCIP1R_SAI1SEL_1
00707 #define RCC_SAI1CLKSOURCE_PIN         (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)
00708 #define RCC_SAI1CLKSOURCE_CLKP         RCC_D2CCIP1R_SAI1SEL_2
00709
00710 /**
00711   * @}
00712   */
00713
00714
00715
00716 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
00717   * @{
00718   */
00719 #define RCC_SAI2CLKSOURCE_PLL         ((uint32_t)0x00000000)
00720 #define RCC_SAI2CLKSOURCE_PLL2         RCC_D2CCIP1R_SAI23SEL_0
00721 #define RCC_SAI2CLKSOURCE_PLL3         RCC_D2CCIP1R_SAI23SEL_1
00722 #define RCC_SAI2CLKSOURCE_PIN         (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
00723 #define RCC_SAI2CLKSOURCE_CLKP         RCC_D2CCIP1R_SAI23SEL_2
00724
00725
00726 /**
00727   * @}
00728   */
00729
00730 /** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source
00731   * @{
00732   */
00733 #define RCC_SPI1CLKSOURCE_PLL         ((uint32_t)0x00000000)
00734 #define RCC_SPI1CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI123SEL_0
00735 #define RCC_SPI1CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI123SEL_1
00736 #define RCC_SPI1CLKSOURCE_PIN         (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
00737 #define RCC_SPI1CLKSOURCE_CLKP         RCC_D2CCIP1R_SPI123SEL_2
00738
00739 /**
00740   * @}
00741   */
00742
00743 /** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source
00744   * @{
00745   */
00746 #define RCC_SPI2CLKSOURCE_PLL         ((uint32_t)0x00000000)
00747 #define RCC_SPI2CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI123SEL
00748 #define RCC_SPI2CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI123SEL_1
00749 #define RCC_SPI2CLKSOURCE_PIN         (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
00750 #define RCC_SPI2CLKSOURCE_CLKP         RCC_D2CCIP1R_SPI123SEL_2
00751
00752
00753 /**
00754   * @}
00755   */
00756
00757 /** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source
00758   * @{
00759   */
00760 #define RCC_SPI3CLKSOURCE_PLL         ((uint32_t)0x00000000)
00761 #define RCC_SPI3CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI123SEL
00762 #define RCC_SPI3CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI123SEL_1
00763 #define RCC_SPI3CLKSOURCE_PIN         (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
00764 #define RCC_SPI3CLKSOURCE_CLKP         RCC_D2CCIP1R_SPI123SEL_2
00765
00766 /**
00767   * @}
00768   */
00769
00770 /** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source
00771   * @{
00772   */
00773 #define RCC_SPI4CLKSOURCE_D2PCLK1     ((uint32_t)0x00000000)
00774 #define RCC_SPI4CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI45SEL_0
00775 #define RCC_SPI4CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI45SEL_1
00776 #define RCC_SPI4CLKSOURCE_HSI         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
00777 #define RCC_SPI4CLKSOURCE_CSI          RCC_D2CCIP1R_SPI45SEL_2
00778 #define RCC_SPI4CLKSOURCE_HSE         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
00779
00780 /**
00781   * @}
00782   */
00783
00784 /** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source
00785   * @{
00786   */
00787 #define RCC_SPI5CLKSOURCE_D2PCLK1     ((uint32_t)0x00000000)
00788 #define RCC_SPI5CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI45SEL_0
00789 #define RCC_SPI5CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI45SEL_1
00790 #define RCC_SPI5CLKSOURCE_HSI         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
00791 #define RCC_SPI5CLKSOURCE_CSI          RCC_D2CCIP1R_SPI45SEL_2
00792 #define RCC_SPI5CLKSOURCE_HSE         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
00793
00794
00795 /**
00796   * @}
00797   */
00798
00799 /** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source
00800   * @{
00801   */
00802 #define RCC_SPI6CLKSOURCE_D3PCLK1     ((uint32_t)0x00000000)
00803 #define RCC_SPI6CLKSOURCE_PLL2         RCC_D3CCIPR_SPI6SEL_0
00804 #define RCC_SPI6CLKSOURCE_PLL3         RCC_D3CCIPR_SPI6SEL_1
00805 #define RCC_SPI6CLKSOURCE_HSI         (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)
00806 #define RCC_SPI6CLKSOURCE_CSI          RCC_D3CCIPR_SPI6SEL_2
00807 #define RCC_SPI6CLKSOURCE_HSE         (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)
00808
00809
00810 /**
00811   * @}
00812   */
00813
00814
00815
00816
00817
00818 /** @defgroup RCCEx_SAI3_Clock_Source SAI3 Clock Source
00819   * @{
00820   */
00821 #define RCC_SAI3CLKSOURCE_PLL         ((uint32_t)0x00000000)
00822 #define RCC_SAI3CLKSOURCE_PLL2         RCC_D2CCIP1R_SAI23SEL_0
00823 #define RCC_SAI3CLKSOURCE_PLL3         RCC_D2CCIP1R_SAI23SEL_1
00824 #define RCC_SAI3CLKSOURCE_PIN         (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
00825 #define RCC_SAI3CLKSOURCE_CLKP         RCC_D2CCIP1R_SAI23SEL_2
00826
00827
00828 /**
00829   * @}
00830   */
00831
00832
00833 /** @defgroup RCCEx_SAI4A_Clock_Source SAI4A Clock Source
00834   * @{
00835   */
00836 #define RCC_SAI4ACLKSOURCE_PLL         ((uint32_t)0x00000000)
00837 #define RCC_SAI4ACLKSOURCE_PLL2         RCC_D3CCIPR_SAI4ASEL_0
00838 #define RCC_SAI4ACLKSOURCE_PLL3         RCC_D3CCIPR_SAI4ASEL_1
00839 #define RCC_SAI4ACLKSOURCE_PIN         (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
00840 #define RCC_SAI4ACLKSOURCE_CLKP         RCC_D3CCIPR_SAI4ASEL_2
00841
00842
00843 /**
00844   * @}
00845   */
00846
00847
00848 /** @defgroup RCCEx_SAI4B_Clock_Source SAI4B Clock Source
00849   * @{
00850   */
00851 #define RCC_SAI4BCLKSOURCE_PLL         ((uint32_t)0x00000000)
00852 #define RCC_SAI4BCLKSOURCE_PLL2         RCC_D3CCIPR_SAI4BSEL_0
00853 #define RCC_SAI4BCLKSOURCE_PLL3         RCC_D3CCIPR_SAI4BSEL_1
00854 #define RCC_SAI4BCLKSOURCE_PIN         (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
00855 #define RCC_SAI4BCLKSOURCE_CLKP         RCC_D3CCIPR_SAI4BSEL_2
00856
00857 /**
00858   * @}
00859   */
00860
00861
00862 /** @defgroup RCCEx_LPTIM1_Clock_Source  RCCEx LPTIM1 Clock Source
00863   * @{
00864   */
00865 #define RCC_LPTIM1CLKSOURCE_D2PCLK1        ((uint32_t)0x00000000)
00866 #define RCC_LPTIM1CLKSOURCE_PLL2          RCC_D2CCIP2R_LPTIM1SEL_0
00867 #define RCC_LPTIM1CLKSOURCE_PLL3          RCC_D2CCIP2R_LPTIM1SEL_1
00868 #define RCC_LPTIM1CLKSOURCE_LSE           (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)
00869 #define RCC_LPTIM1CLKSOURCE_LSI            RCC_D2CCIP2R_LPTIM1SEL_2
00870 #define RCC_LPTIM1CLKSOURCE_CLKP          (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)
00871
00872
00873 /**
00874   * @}
00875   */
00876
00877 /** @defgroup RCCEx_LPTIM2_Clock_Source  RCCEx LPTIM2 Clock Source
00878   * @{
00879   */
00880 #define RCC_LPTIM2CLKSOURCE_D3PCLK1        ((uint32_t)0x00000000)
00881 #define RCC_LPTIM2CLKSOURCE_PLL2          RCC_D3CCIPR_LPTIM2SEL_0
00882 #define RCC_LPTIM2CLKSOURCE_PLL3          RCC_D3CCIPR_LPTIM2SEL_1
00883 #define RCC_LPTIM2CLKSOURCE_LSE           (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)
00884 #define RCC_LPTIM2CLKSOURCE_LSI            RCC_D3CCIPR_LPTIM2SEL_2
00885 #define RCC_LPTIM2CLKSOURCE_CLKP          (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)
00886
00887
00888 /**
00889   * @}
00890   */
00891
00892 /** @defgroup RCCEx_LPTIM3_Clock_Source  RCCEx LPTIM3 Clock Source
00893   * @{
00894   */
00895 #define RCC_LPTIM3CLKSOURCE_D3PCLK1        ((uint32_t)0x00000000)
00896 #define RCC_LPTIM3CLKSOURCE_PLL2          RCC_D3CCIPR_LPTIM345SEL_0
00897 #define RCC_LPTIM3CLKSOURCE_PLL3          RCC_D3CCIPR_LPTIM345SEL_1
00898 #define RCC_LPTIM3CLKSOURCE_LSE           (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
00899 #define RCC_LPTIM3CLKSOURCE_LSI            RCC_D3CCIPR_LPTIM345SEL_2
00900 #define RCC_LPTIM3CLKSOURCE_CLKP          (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
00901
00902
00903 /**
00904   * @}
00905   */
00906
00907 /** @defgroup RCCEx_LPTIM4_Clock_Source  RCCEx LPTIM4 Clock Source
00908   * @{
00909   */
00910 #define RCC_LPTIM4CLKSOURCE_D3PCLK1        ((uint32_t)0x00000000)
00911 #define RCC_LPTIM4CLKSOURCE_PLL2          RCC_D3CCIPR_LPTIM345SEL_0
00912 #define RCC_LPTIM4CLKSOURCE_PLL3          RCC_D3CCIPR_LPTIM345SEL_1
00913 #define RCC_LPTIM4CLKSOURCE_LSE           (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
00914 #define RCC_LPTIM4CLKSOURCE_LSI           RCC_D3CCIPR_LPTIM345SEL_2
00915 #define RCC_LPTIM4CLKSOURCE_CLKP          (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
00916
00917
00918 /**
00919   * @}
00920   */
00921
00922 /** @defgroup RCCEx_LPTIM5_Clock_Source  RCCEx LPTIM5 Clock Source
00923   * @{
00924   */
00925 #define RCC_LPTIM5CLKSOURCE_D3PCLK1        ((uint32_t)0x00000000)
00926 #define RCC_LPTIM5CLKSOURCE_PLL2          RCC_D3CCIPR_LPTIM345SEL_0
00927 #define RCC_LPTIM5CLKSOURCE_PLL3          RCC_D3CCIPR_LPTIM345SEL_1
00928 #define RCC_LPTIM5CLKSOURCE_LSE           (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
00929 #define RCC_LPTIM5CLKSOURCE_LSI            RCC_D3CCIPR_LPTIM345SEL_2
00930 #define RCC_LPTIM5CLKSOURCE_CLKP          (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
00931
00932 /**
00933   * @}
00934   */
00935
00936
00937 /** @defgroup RCCEx_QSPI_Clock_Source  RCCEx QSPI Clock Source
00938   * @{
00939   */
00940 #define RCC_QSPICLKSOURCE_D1HCLK       ((uint32_t)0x00000000)
00941 #define RCC_QSPICLKSOURCE_PLL          RCC_D1CCIPR_QSPISEL_0
00942 #define RCC_QSPICLKSOURCE_PLL2         RCC_D1CCIPR_QSPISEL_1
00943 #define RCC_QSPICLKSOURCE_CLKP         RCC_D1CCIPR_QSPISEL
00944
00945
00946
00947 /**
00948   * @}
00949   */
00950
00951 /** @defgroup RCCEx_FMC_Clock_Source  RCCEx FMC Clock Source
00952   * @{
00953   */
00954 #define RCC_FMCCLKSOURCE_D1HCLK       ((uint32_t)0x00000000)
00955 #define RCC_FMCCLKSOURCE_PLL          RCC_D1CCIPR_FMCSEL_0
00956 #define RCC_FMCCLKSOURCE_PLL2         RCC_D1CCIPR_FMCSEL_1
00957 #define RCC_FMCCLKSOURCE_CLKP         RCC_D1CCIPR_FMCSEL
00958
00959 /**
00960   * @}
00961   */
00962
00963 #if defined(FDCAN1) || defined(FDCAN2)
00964 /** @defgroup RCCEx_FDCAN_Clock_Source  RCCEx FDCAN Clock Source
00965   * @{
00966   */
00967
00968 #define RCC_FDCANCLKSOURCE_HSE         ((uint32_t)0x00000000)
00969 #define RCC_FDCANCLKSOURCE_PLL          RCC_D2CCIP1R_FDCANSEL_0
00970 #define RCC_FDCANCLKSOURCE_PLL2         RCC_D2CCIP1R_FDCANSEL_1
00971
00972 /**
00973   * @}
00974   */
00975 #endif /*FDCAN1 || FDCAN2*/
00976
00977
00978 /** @defgroup RCCEx_SDMMC_Clock_Source  RCCEx SDMMC Clock Source
00979   * @{
00980   */
00981
00982 #define RCC_SDMMCCLKSOURCE_PLL           ((uint32_t)0x00000000)
00983 #define RCC_SDMMCCLKSOURCE_PLL2           RCC_D1CCIPR_SDMMCSEL
00984
00985 /**
00986   * @}
00987   */
00988
00989
00990
00991 /** @defgroup RCCEx_USB_Clock_Source  RCCEx USB Clock Source
00992   * @{
00993   */
00994 #define RCC_USBCLKSOURCE_PLL                  RCC_D2CCIP2R_USBSEL_0
00995 #define RCC_USBCLKSOURCE_PLL3                 RCC_D2CCIP2R_USBSEL_1
00996 #define RCC_USBCLKSOURCE_HSI48                RCC_D2CCIP2R_USBSEL
00997
00998 /**
00999   * @}
01000   */
01001
01002 /** @defgroup RCCEx_ADC_Clock_Source  RCCEx ADC Clock Source
01003   * @{
01004   */
01005 #define RCC_ADCCLKSOURCE_PLL2       ((uint32_t)0x00000000)
01006 #define RCC_ADCCLKSOURCE_PLL3       RCC_D3CCIPR_ADCSEL_0
01007 #define RCC_ADCCLKSOURCE_CLKP       RCC_D3CCIPR_ADCSEL_1
01008
01009 /**
01010   * @}
01011   */
01012
01013
01014
01015
01016
01017 /** @defgroup RCCEx_SWPMI1_Clock_Source  RCCEx SWPMI1 Clock Source
01018   * @{
01019   */
01020 #define RCC_SWPMI1CLKSOURCE_D2PCLK1       ((uint32_t)0x00000000)
01021 #define RCC_SWPMI1CLKSOURCE_HSI            RCC_D2CCIP1R_SWPSEL
01022
01023 /**
01024   * @}
01025   */
01026
01027 /** @defgroup RCCEx_DFSDM1_Clock_Source  RCCEx DFSDM1 Clock Source
01028   * @{
01029   */
01030 #define RCC_DFSDM1CLKSOURCE_D2PCLK1        ((uint32_t)0x00000000)
01031 #define RCC_DFSDM1CLKSOURCE_SYS            RCC_D2CCIP1R_DFSDM1SEL
01032
01033
01034 /**
01035   * @}
01036   */
01037
01038 /** @defgroup RCCEx_SPDIFRX_Clock_Source  RCCEx SPDIFRX Clock Source
01039   * @{
01040   */
01041 #define RCC_SPDIFRXCLKSOURCE_PLL        ((uint32_t)0x00000000)
01042 #define RCC_SPDIFRXCLKSOURCE_PLL2       RCC_D2CCIP1R_SPDIFSEL_0
01043 #define RCC_SPDIFRXCLKSOURCE_PLL3       RCC_D2CCIP1R_SPDIFSEL_1
01044 #define RCC_SPDIFRXCLKSOURCE_HSI        RCC_D2CCIP1R_SPDIFSEL
01045
01046 /**
01047   * @}
01048   */
01049
01050 /** @defgroup RCCEx_CEC_Clock_Source  RCCEx CEC Clock Source
01051   * @{
01052   */
01053 #define RCC_CECCLKSOURCE_LSE        ((uint32_t)0x00000000)
01054 #define RCC_CECCLKSOURCE_LSI         RCC_D2CCIP2R_CECSEL_0
01055 #define RCC_CECCLKSOURCE_CSI         RCC_D2CCIP2R_CECSEL_1
01056
01057 /**
01058   * @}
01059   */
01060
01061
01062 /** @defgroup RCCEx_CLKP_Clock_Source  RCCEx CLKP Clock Source
01063   * @{
01064   */
01065 #define RCC_CLKPSOURCE_HSI        ((uint32_t)0x00000000)
01066 #define RCC_CLKPSOURCE_CSI         RCC_D1CCIPR_CKPERSEL_0
01067 #define RCC_CLKPSOURCE_HSE         RCC_D1CCIPR_CKPERSEL_1
01068
01069 /**
01070   * @}
01071   */
01072
01073 /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
01074   * @{
01075   */
01076 #define RCC_TIMPRES_DESACTIVATED        ((uint32_t)0x00000000U)
01077 #define RCC_TIMPRES_ACTIVATED            RCC_CFGR_TIMPRE
01078
01079 /**
01080   * @}
01081   */
01082
01083
01084
01085 /** @defgroup RCCEx_RCC_WWDGx  RCCEx RCC WWDGx
01086   * @{
01087   */
01088 #define RCC_WWDG1        RCC_GCR_WW1RSC
01089
01090 /**
01091   * @}
01092   */
01093
01094
01095 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status
01096   * @{
01097   */
01098 #define RCC_CRS_NONE                   ((uint32_t)0x00000000U)
01099 #define RCC_CRS_TIMEOUT                ((uint32_t)0x00000001U)
01100 #define RCC_CRS_SYNCOK                 ((uint32_t)0x00000002U)
01101 #define RCC_CRS_SYNCWARN               ((uint32_t)0x00000004U)
01102 #define RCC_CRS_SYNCERR                ((uint32_t)0x00000008U)
01103 #define RCC_CRS_SYNCMISS               ((uint32_t)0x00000010U)
01104 #define RCC_CRS_TRIMOVF                ((uint32_t)0x00000020U)
01105 /**
01106   * @}
01107   */
01108
01109 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
01110   * @{
01111   */
01112 #define RCC_CRS_SYNC_SOURCE_USB2 ((uint32_t)0x00000000U) /*!< Synchro Signal source USB2 SOF */
01113 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
01114 #define RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB1 SOF (default) */
01115
01116
01117 /**
01118   * @}
01119   */
01120
01121 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
01122   * @{
01123   */
01124 #define RCC_CRS_SYNC_DIV1        ((uint32_t)0x00000000U)           /*!< Synchro Signal not divided (default) */
01125 #define RCC_CRS_SYNC_DIV2        CRS_CFGR_SYNCDIV_0                         /*!< Synchro Signal divided by 2 */
01126 #define RCC_CRS_SYNC_DIV4        CRS_CFGR_SYNCDIV_1                         /*!< Synchro Signal divided by 4 */
01127 #define RCC_CRS_SYNC_DIV8        (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)  /*!< Synchro Signal divided by 8 */
01128 #define RCC_CRS_SYNC_DIV16       CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
01129 #define RCC_CRS_SYNC_DIV32       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
01130 #define RCC_CRS_SYNC_DIV64       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
01131 #define RCC_CRS_SYNC_DIV128      CRS_CFGR_SYNCDIV                         /*!< Synchro Signal divided by 128 */
01132 /**
01133   * @}
01134   */
01135
01136 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
01137   * @{
01138   */
01139 #define RCC_CRS_SYNC_POLARITY_RISING   ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */
01140 #define RCC_CRS_SYNC_POLARITY_FALLING  CRS_CFGR_SYNCPOL        /*!< Synchro Active on falling edge */
01141 /**
01142   * @}
01143   */
01144
01145 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
01146   * @{
01147   */
01148 #define RCC_CRS_RELOADVALUE_DEFAULT    ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
01149                                                                     to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
01150 /**
01151   * @}
01152   */
01153
01154 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
01155   * @{
01156   */
01157 #define RCC_CRS_ERRORLIMIT_DEFAULT     ((uint32_t)0x00000022U) /*!< Default Frequency error limit */
01158 /**
01159   * @}
01160   */
01161
01162 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
01163   * @{
01164   */
01165 #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
01166                                                                       The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
01167                                                                       corresponds to a higher output frequency */
01168 /**
01169   * @}
01170   */
01171
01172 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
01173   * @{
01174   */
01175 #define RCC_CRS_FREQERRORDIR_UP        ((uint32_t)0x00000000U)   /*!< Upcounting direction, the actual frequency is above the target */
01176 #define RCC_CRS_FREQERRORDIR_DOWN      ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
01177 /**
01178   * @}
01179   */
01180
01181 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
01182   * @{
01183   */
01184 #define RCC_CRS_IT_SYNCOK              CRS_CR_SYNCOKIE       /*!< SYNC event OK */
01185 #define RCC_CRS_IT_SYNCWARN            CRS_CR_SYNCWARNIE     /*!< SYNC warning */
01186 #define RCC_CRS_IT_ERR                 CRS_CR_ERRIE          /*!< Error */
01187 #define RCC_CRS_IT_ESYNC               CRS_CR_ESYNCIE        /*!< Expected SYNC */
01188 #define RCC_CRS_IT_SYNCERR             CRS_CR_ERRIE          /*!< SYNC error */
01189 #define RCC_CRS_IT_SYNCMISS            CRS_CR_ERRIE          /*!< SYNC missed */
01190 #define RCC_CRS_IT_TRIMOVF             CRS_CR_ERRIE          /*!< Trimming overflow or underflow */
01191
01192 /**
01193   * @}
01194   */
01195
01196 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
01197   * @{
01198   */
01199 #define RCC_CRS_FLAG_SYNCOK            CRS_ISR_SYNCOKF       /*!< SYNC event OK flag     */
01200 #define RCC_CRS_FLAG_SYNCWARN          CRS_ISR_SYNCWARNF     /*!< SYNC warning flag      */
01201 #define RCC_CRS_FLAG_ERR               CRS_ISR_ERRF          /*!< Error flag        */
01202 #define RCC_CRS_FLAG_ESYNC             CRS_ISR_ESYNCF        /*!< Expected SYNC flag     */
01203 #define RCC_CRS_FLAG_SYNCERR           CRS_ISR_SYNCERR       /*!< SYNC error */
01204 #define RCC_CRS_FLAG_SYNCMISS          CRS_ISR_SYNCMISS      /*!< SYNC missed*/
01205 #define RCC_CRS_FLAG_TRIMOVF           CRS_ISR_TRIMOVF       /*!< Trimming overflow or underflow */
01206
01207 /**
01208   * @}
01209   */
01210
01211 /**
01212   * @}
01213   */
01214
01215
01216
01217 /* Exported macro ------------------------------------------------------------*/
01218 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
01219   * @{
01220   */
01221
01222 /** @brief  Macros to enable or disable PLL2.
01223   * @note   After enabling PLL2, the application software should wait on
01224   *         PLL2RDY flag to be set indicating that PLL2 clock is stable and can
01225   *         be used as kernel clock source.
01226   * @note   PLL2 is disabled by hardware when entering STOP and STANDBY modes.
01227   */
01228 #define __HAL_RCC_PLL2_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL2ON)
01229 #define __HAL_RCC_PLL2_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)
01230
01231 /**
01232   * @brief  Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)
01233   * @note   Enabling/disabling  Those Clocks can be any time  without the need to stop the PLL2,
01234   *         This is mainly used to save Power.
01235   * @param  __RCC_PLL2ClockOut__: Specifies the PLL2 clock to be outputted
01236   *          This parameter can be one of the following values:
01237   *            @arg RCC_PLL2_DIVP: This clock is used to generate system clock (up to 400MHZ)
01238   *            @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ)
01239   *            @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock (up to 400MHZ)
01240   * @retval None
01241   */
01242 #define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
01243
01244 #define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
01245
01246 /**
01247   * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO
01248   * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL2
01249   * @retval None
01250   */
01251 #define __HAL_RCC_PLL2FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
01252
01253 #define __HAL_RCC_PLL2FRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
01254
01255 /**
01256   * @brief  Macro to configures the PLL2  multiplication and division factors.
01257   * @note   This function must be used only when PLL2 is disabled.
01258   *
01259   * @param  __PLL2M__: specifies the division factor for PLL2 VCO input clock
01260   *          This parameter must be a number between 1 and 63.
01261   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
01262   *         frequency ranges from 1 to 16 MHz.
01263   *
01264   * @param  __PLL2N__: specifies the multiplication factor for PLL2 VCO output clock
01265   *          This parameter must be a number between 4 and 512.
01266   * @note   You have to set the PLL2N parameter correctly to ensure that the VCO
01267   *         output frequency is between 150 and 420 MHz (when in medium VCO range) or
01268   *         between 192 and 836 MHZ (when in wide VCO range)
01269   *
01270   * @param  __PLL2P__: specifies the division factor for peripheral kernel clocks
01271   *          This parameter must be a number between 2 and 128 (where odd numbers not allowed)
01272   *
01273   * @param  __PLL2Q__: specifies the division factor for peripheral kernel clocks
01274   *          This parameter must be a number between 1 and 128
01275   *
01276   * @param  __PLL2R__: specifies the division factor for peripheral kernel clocks
01277   *          This parameter must be a number between 1 and 128
01278   *
01279   * @retval None
01280   */
01281
01282
01283 #define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \
01284                   do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U));  \
01285                          WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \
01286                                    ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \
01287                        } while(0)
01288 /**
01289   * @brief  Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor
01290   *
01291   * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO
01292   *
01293   * @param  __RCC_PLL2FRACN__: Specifies Fractional Part Of The Multiplication factor for PLL2 VCO
01294   *                           It should be a value between 0 and 8191
01295   * @note   Warning: the software has to set correctly these bits to insure that the VCO
01296   *                  output frequency is between its valid frequency range, which is:
01297   *                  192 to 836 MHz if PLL2VCOSEL = 0
01298   *                  150 to 420 MHz if PLL2VCOSEL = 1.
01299   *
01300   *
01301   * @retval None
01302   */
01303   #define  __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,(uint32_t)(__RCC_PLL2FRACN__) << POSITION_VAL(RCC_PLL2FRACR_FRACN2))
01304
01305 /** @brief  Macro to select  the PLL2  reference frequency range.
01306   * @param  __RCC_PLL2VCIRange__: specifies the PLL2 input frequency range
01307   *         This parameter can be one of the following values:
01308   *            @arg RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz
01309   *            @arg RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz
01310   *            @arg RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz
01311   *            @arg RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz
01312   * @retval None
01313   */
01314 #define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \
01315                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))
01316
01317
01318 /** @brief  Macro to select  the PLL2  reference frequency range.
01319   * @param  __RCC_PLL2VCORange__: Specifies the PLL2 input frequency range
01320   *         This parameter can be one of the following values:
01321   *            @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz
01322   *            @arg RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz
01323   * @retval None
01324   */
01325 #define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \
01326                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))
01327
01328 /** @brief  Macros to enable or disable the main PLL3.
01329   * @note   After enabling  PLL3, the application software should wait on
01330   *         PLL3RDY flag to be set indicating that PLL3 clock is stable and can
01331   *         be used as kernel clock source.
01332   * @note   PLL3 is disabled by hardware when entering STOP and STANDBY modes.
01333   */
01334 #define __HAL_RCC_PLL3_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL3ON)
01335 #define __HAL_RCC_PLL3_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)
01336
01337 /**
01338   * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO
01339   * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL3
01340   * @retval None
01341   */
01342 #define __HAL_RCC_PLL3FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
01343
01344 #define __HAL_RCC_PLL3FRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
01345
01346 /**
01347   * @brief  Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)
01348   * @note   Enabling/disabling  Those Clocks can be any time  without the need to stop the PLL3,
01349   *         This is mainly used to save Power.
01350   * @param  __RCC_PLL3ClockOut__: specifies the PLL3 clock to be outputted
01351   *          This parameter can be one of the following values:
01352   *            @arg RCC_PLL3_DIVP: This clock is used to generate system clock (up to 400MHZ)
01353   *            @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ)
01354   *            @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock (up to 400MHZ)
01355   * @retval None
01356   */
01357 #define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
01358
01359 #define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
01360
01361 /**
01362   * @brief  Macro to configures the PLL3  multiplication and division factors.
01363   * @note   This function must be used only when PLL3 is disabled.
01364   *
01365   * @param  __PLL3M__: specifies the division factor for PLL3 VCO input clock
01366   *          This parameter must be a number between 1 and 63.
01367   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
01368   *         frequency ranges from 1 to 16 MHz.
01369   *
01370   * @param  __PLL3N__: specifies the multiplication factor for PLL3 VCO output clock
01371   *          This parameter must be a number between 4 and 512.
01372   * @note   You have to set the PLL3N parameter correctly to ensure that the VCO
01373   *         output frequency is between 150 and 420 MHz (when in medium VCO range) or
01374   *         between 192 and 836 MHZ (when in wide VCO range)
01375   *
01376   * @param  __PLL3P__: specifies the division factor for peripheral kernel clocks
01377   *          This parameter must be a number between 2 and 128 (where odd numbers not allowed)
01378   *
01379   * @param  __PLL3Q__: specifies the division factor for peripheral kernel clocks
01380   *          This parameter must be a number between 1 and 128
01381   *
01382   * @param  __PLL3R__: specifies the division factor for peripheral kernel clocks
01383   *          This parameter must be a number between 1 and 128
01384   *
01385   * @retval None
01386   */
01387
01388 #define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \
01389                   do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U));  \
01390                          WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \
01391                                    ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \
01392                        } while(0)
01393
01394
01395
01396 /**
01397   * @brief  Macro to configures  PLL3 clock Fractional Part of The Multiplication Factor
01398   *
01399   * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO
01400   *
01401   * @param  __RCC_PLL3FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL3 VCO
01402   *                            It should be a value between 0 and 8191
01403   * @note   Warning: the software has to set correctly these bits to insure that the VCO
01404   *                  output frequency is between its valid frequency range, which is:
01405   *                  192 to 836 MHz if PLL3VCOSEL = 0
01406   *                  150 to 420 MHz if PLL3VCOSEL = 1.
01407   *
01408   *
01409   * @retval None
01410   */
01411  #define  __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << POSITION_VAL(RCC_PLL3FRACR_FRACN3))
01412
01413 /** @brief  Macro to select  the PLL3  reference frequency range.
01414   * @param  __RCC_PLL3VCIRange__: specifies the PLL1 input frequency range
01415   *         This parameter can be one of the following values:
01416   *            @arg RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz
01417   *            @arg RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz
01418   *            @arg RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz
01419   *            @arg RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz
01420   * @retval None
01421   */
01422 #define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \
01423                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))
01424
01425
01426 /** @brief  Macro to select  the PLL3  reference frequency range.
01427   * @param  __RCC_PLL3VCORange__: specifies the PLL1 input frequency range
01428   *         This parameter can be one of the following values:
01429   *            @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz
01430   *            @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz
01431   * @retval None
01432   */
01433 #define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \
01434                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))
01435 /**
01436   * @brief  Macro to Configure the SAI1 clock source.
01437   * @param  __RCC_SAI1CLKSource__: defines the SAI1 clock source. This clock is derived
01438   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
01439   *          This parameter can be one of the following values:
01440   *             @arg RCC_SAI1CLK_PLL: SAI1 clock = PLL
01441   *             @arg RCC_SAI1CLK_PLL2: SAI1 clock = PLL2
01442   *             @arg RCC_SAI1CLK_PLL3: SAI1 clock = PLL3
01443   *             @arg RCC_SAI1CLK_OSC: SAI1 clock  = OSC
01444   *             @arg RCC_SAI1CLK_PIN: SAI1 clock = External Clock
01445   * @retval None
01446   */
01447 #define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\
01448                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
01449
01450 /** @brief  Macro to get the SAI1 clock source.
01451   * @retval The clock source can be one of the following values:
01452   *             @arg RCC_SAI1CLK_PLL: SAI1 clock = PLL
01453   *             @arg RCC_SAI1CLK_PLL2: SAI1 clock = PLL2
01454   *             @arg RCC_SAI1CLK_PLL3: SAI1 clock = PLL3
01455   *             @arg RCC_SAI1CLK_CLKP: SAI1 clock  = CLKP
01456   *             @arg RCC_SAI1CLK_PIN: SAI1 clock = External Clock
01457   */
01458 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL)))
01459
01460 /**
01461   * @brief  Macro to Configure the SPDIFRX clock source.
01462   * @param  __RCC_SPDIFCLKSource__: defines the SPDIFRX clock source. This clock is derived
01463   *         from system PLL, PLL2, PLL3,  or internal OSC clock
01464   *          This parameter can be one of the following values:
01465   *             @arg RCC_SPDIFRXCLKSOURCE_PLL:  SPDIFRX clock = PLL
01466   *             @arg RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2
01467   *             @arg RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3
01468   *             @arg RCC_SPDIFRXCLKSOURCE_HSI:  SPDIFRX clock  = HSI
01469   * @retval None
01470   */
01471 #define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\
01472                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
01473 /**
01474   * @brief  Macro to get the SPDIFRX clock source.
01475   * @retval None
01476   */
01477 #define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)))
01478
01479 /**
01480   * @brief  Macro to Configure the SAI2 clock source.
01481   * @param  __RCC_SAI2CLKSource__: defines the SAI2 clock source. This clock is derived
01482   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
01483   *          This parameter can be one of the following values:
01484   *             @arg RCC_SAI2CLK_PLL: SAI2 clock = PLL
01485   *             @arg RCC_SAI2CLK_PLL2: SAI2 clock = PLL2
01486   *             @arg RCC_SAI2CLK_PLL3: SAI2 clock = PLL3
01487   *             @arg RCC_SAI2CLK_CLKP: SAI2 clock  = CLKP
01488   *             @arg RCC_SAI2CLK_PIN: SAI2 clock = External Clock
01489   * @retval None
01490   */
01491 #define __HAL_RCC_SAI2_CONFIG(__RCC_SAI2CLKSource__ )\
01492                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI2CLKSource__))
01493
01494 /** @brief  Macro to get the SAI2 clock source.
01495   * @retval The clock source can be one of the following values:
01496   *             @arg RCC_SAI2CLK_PLL: SAI2 clock = PLL
01497   *             @arg RCC_SAI2CLK_PLL2: SAI2 clock = PLL2
01498   *             @arg RCC_SAI2CLK_PLL3: SAI2 clock = PLL3
01499   *             @arg RCC_SAI2CLK_CLKP: SAI2 clock  = CLKP
01500   *             @arg RCC_SAI2CLK_PIN: SAI2 clock = External Clock
01501   */
01502 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
01503
01504 /**
01505   * @brief  Macro to Configure the SAI3 clock source.
01506   * @param  __RCC_SAI3CLKSource__: defines the SAI3 clock source. This clock is derived
01507   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
01508   *          This parameter can be one of the following values:
01509   *             @arg RCC_SAI3CLK_PLL: SAI3 clock = PLL
01510   *             @arg RCC_SAI3CLK_PLL2: SAI3 clock = PLL2
01511   *             @arg RCC_SAI3CLK_PLL3: SAI3 clock = PLL3
01512   *             @arg RCC_SAI3CLK_CLKP: SAI3 clock  = CLKP
01513   *             @arg RCC_SAI3CLK_PIN: SAI3 clock = External Clock
01514   * @retval None
01515   */
01516 #define __HAL_RCC_SAI3_CONFIG(__RCC_SAI3CLKSource__ )\
01517                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI3CLKSource__))
01518
01519 /** @brief  Macro to get the SAI3 clock source.
01520   * @retval The clock source can be one of the following values:
01521   *             @arg RCC_SAI3CLK_PLL: SAI3 clock = PLL
01522   *             @arg RCC_SAI3CLK_PLL2: SAI3 clock = PLL2
01523   *             @arg RCC_SAI3CLK_PLL3: SAI3 clock = PLL3
01524   *             @arg RCC_SAI3CLK_CLKP: SAI3 clock  = CLKP
01525   *             @arg RCC_SAI3CLK_PIN: SAI3 clock = External Clock
01526   */
01527 #define __HAL_RCC_GET_SAI3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
01528
01529 /**
01530   * @brief  Macro to Configure the SAI4A clock source.
01531   * @param  __RCC_SAI4ACLKSource__: defines the SAI4A clock source. This clock is derived
01532   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
01533   *          This parameter can be one of the following values:
01534   *             @arg RCC_SAI4ACLK_PLL: SAI4A clock = PLL
01535   *             @arg RCC_SAI4ACLK_PLL2: SAI4A clock = PLL2
01536   *             @arg RCC_SAI4ACLK_PLL3: SAI4A clock = PLL3
01537   *             @arg RCC_SAI4ACLK_CLKP: SAI4A clock  = CLKP
01538   *             @arg RCC_SAI4ACLK_PIN: SAI4A clock = External Clock
01539   * @retval None
01540   */
01541 #define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\
01542                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))
01543
01544 /** @brief  Macro to get the SAI4A clock source.
01545   * @retval The clock source can be one of the following values:
01546   *             @arg RCC_SAI4ACLK_PLL: SAI4B clock = PLL
01547   *             @arg RCC_SAI4ACLK_PLL2: SAI4B clock = PLL2
01548   *             @arg RCC_SAI4ACLK_PLL3: SAI4B clock = PLL3
01549   *             @arg RCC_SAI4ACLK_CLKP: SAI4B clock  = CLKP
01550   *             @arg RCC_SAI4ACLK_PIN: SAI4B clock = External Clock
01551   */
01552 #define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL)))
01553
01554 /**
01555   * @brief  Macro to Configure the SAI4B clock source.
01556   * @param  __RCC_SAI4BCLKSource__: defines the SAI4B clock source. This clock is derived
01557   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
01558   *          This parameter can be one of the following values:
01559   *             @arg RCC_SAI4BCLK_PLL: SAI4B clock = PLL
01560   *             @arg RCC_SAI4BCLK_PLL2: SAI4B clock = PLL2
01561   *             @arg RCC_SAI4BCLK_PLL3: SAI4B clock = PLL3
01562   *             @arg RCC_SAI4BCLK_CLKP: SAI4B clock  = CLKP
01563   *             @arg RCC_SAI4BCLK_PIN: SAI4B clock = External Clock
01564   * @retval None
01565   */
01566 #define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\
01567                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))
01568
01569 /** @brief  Macro to get the SAI4B clock source.
01570   * @retval The clock source can be one of the following values:
01571   *             @arg RCC_SAI4BCLK_PLL: SAI4B clock = PLL
01572   *             @arg RCC_SAI4BCLK_PLL2: SAI4B clock = PLL2
01573   *             @arg RCC_SAI4BCLK_PLL3: SAI4B clock = PLL3
01574   *             @arg RCC_SAI4BCLK_CLKP: SAI4B clock  = CLKP
01575   *             @arg RCC_SAI4BCLK_PIN: SAI4B clock = External Clock
01576   */
01577 #define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))
01578
01579 /** @brief macro to configure the I2C1 clock (I2C1CLK).
01580   *
01581   * @param  __I2C1CLKSource__: specifies the I2C1 clock source.
01582   *          This parameter can be one of the following values:
01583   *            @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
01584   *            @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
01585   *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
01586   *            @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
01587   */
01588 #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
01589                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1CLKSource__))
01590
01591 /** @brief  macro to get the I2C1 clock source.
01592   * @retval The clock source can be one of the following values:
01593 *            @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
01594   *            @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
01595   *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
01596   *            @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
01597   */
01598 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
01599
01600 /** @brief macro to configure the I2C2 clock (I2C2CLK).
01601   *
01602   * @param  __I2C2CLKSource__: specifies the I2C2 clock source.
01603   *          This parameter can be one of the following values:
01604   *            @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
01605   *            @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
01606   *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
01607   *            @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
01608   */
01609 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
01610                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C2CLKSource__))
01611
01612 /** @brief  macro to get the I2C2 clock source.
01613   * @retval The clock source can be one of the following values:
01614   *            @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
01615   *            @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
01616   *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
01617   *            @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
01618   */
01619 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
01620
01621 /** @brief macro to configure the I2C3 clock (I2C3CLK).
01622   *
01623   * @param  __I2C3CLKSource__: specifies the I2C3 clock source.
01624   *          This parameter can be one of the following values:
01625   *            @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
01626   *            @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
01627   *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
01628   *            @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
01629   */
01630 #define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
01631                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C3CLKSource__))
01632
01633 /** @brief  macro to get the I2C3 clock source.
01634   * @retval The clock source can be one of the following values:
01635   *            @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
01636   *            @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
01637   *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
01638   *            @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
01639   */
01640 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
01641
01642 /** @brief macro to configure the I2C4 clock (I2C4CLK).
01643   *
01644   * @param  __I2C4CLKSource__: specifies the I2C4 clock source.
01645   *          This parameter can be one of the following values:
01646   *            @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
01647   *            @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
01648   *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
01649   *            @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
01650   */
01651 #define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \
01652                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
01653
01654 /** @brief  macro to get the I2C4 clock source.
01655   * @retval The clock source can be one of the following values:
01656   *            @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
01657   *            @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
01658   *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
01659   *            @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
01660   */
01661 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))
01662
01663 /** @brief macro to configure the USART1 clock (USART1CLK).
01664   *
01665   * @param  __USART1CLKSource__: specifies the USART1 clock source.
01666   *          This parameter can be one of the following values:
01667   *            @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
01668   *            @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
01669   *            @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
01670   *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
01671   *            @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
01672   *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
01673   */
01674 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
01675                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART1CLKSource__))
01676
01677 /** @brief  macro to get the USART1 clock source.
01678   * @retval The clock source can be one of the following values:
01679   *            @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
01680   *            @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
01681   *            @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
01682   *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
01683   *            @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
01684   *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
01685   */
01686 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
01687
01688 /** @brief macro to configure the USART2 clock (USART2CLK).
01689   *
01690   * @param  __USART2CLKSource__: specifies the USART2 clock source.
01691   *          This parameter can be one of the following values:
01692   *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
01693   *            @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
01694   *            @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
01695   *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
01696   *            @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
01697   *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
01698   */
01699 #define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
01700                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART2CLKSource__))
01701
01702 /** @brief  macro to get the USART2 clock source.
01703   * @retval The clock source can be one of the following values:
01704   *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
01705   *            @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
01706   *            @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
01707   *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
01708   *            @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
01709   *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
01710   */
01711 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
01712
01713 /** @brief macro to configure the USART3 clock (USART3CLK).
01714   *
01715   * @param  __USART3CLKSource__: specifies the USART3 clock source.
01716   *          This parameter can be one of the following values:
01717   *            @arg RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
01718   *            @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
01719   *            @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
01720   *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
01721   *            @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
01722   *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
01723   */
01724 #define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
01725                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART3CLKSource__))
01726
01727 /** @brief  macro to get the USART3 clock source.
01728   * @retval The clock source can be one of the following values:
01729   *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
01730   *            @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
01731   *            @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
01732   *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
01733   *            @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
01734   *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
01735   */
01736 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
01737
01738 /** @brief macro to configure the UART4 clock (UART4CLK).
01739   *
01740   * @param  __UART4CLKSource__: specifies the UART4 clock source.
01741   *          This parameter can be one of the following values:
01742   *            @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
01743   *            @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
01744   *            @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
01745   *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
01746   *            @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
01747   *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
01748   */
01749 #define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \
01750                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART4CLKSource__))
01751
01752 /** @brief  macro to get the UART4 clock source.
01753   * @retval The clock source can be one of the following values:
01754   *            @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
01755   *            @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
01756   *            @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
01757   *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
01758   *            @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
01759   *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
01760   */
01761 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
01762
01763 /** @brief macro to configure the UART5 clock (UART5CLK).
01764   *
01765   * @param  __UART5CLKSource__: specifies the UART5 clock source.
01766   *          This parameter can be one of the following values:
01767   *            @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
01768   *            @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
01769   *            @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
01770   *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
01771   *            @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
01772   *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
01773   */
01774 #define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \
01775                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART5CLKSource__))
01776
01777 /** @brief  macro to get the UART5 clock source.
01778   * @retval The clock source can be one of the following values:
01779   *            @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
01780   *            @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
01781   *            @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
01782   *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
01783   *            @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
01784   *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
01785   */
01786 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
01787
01788 /** @brief macro to configure the USART6 clock (USART6CLK).
01789   *
01790   * @param  __USART6CLKSource__: specifies the USART6 clock source.
01791   *          This parameter can be one of the following values:
01792   *            @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
01793   *            @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
01794   *            @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
01795   *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
01796   *            @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
01797   *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
01798   */
01799 #define __HAL_RCC_USART6_CONFIG(__USART6CLKSource__) \
01800                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART6CLKSource__))
01801
01802 /** @brief  macro to get the USART6 clock source.
01803   * @retval The clock source can be one of the following values:
01804   *            @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
01805   *            @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
01806   *            @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
01807   *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
01808   *            @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
01809   *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
01810   */
01811 #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
01812
01813 /** @brief macro to configure the UART5 clock (UART7CLK).
01814   *
01815   * @param  __UART7CLKSource__: specifies the UART7 clock source.
01816   *          This parameter can be one of the following values:
01817   *            @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
01818   *            @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
01819   *            @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
01820   *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
01821   *            @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
01822   *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
01823   */
01824 #define __HAL_RCC_UART7_CONFIG(__UART7CLKSource__) \
01825                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART7CLKSource__))
01826
01827 /** @brief  macro to get the UART7 clock source.
01828   * @retval The clock source can be one of the following values:
01829   *            @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
01830   *            @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
01831   *            @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
01832   *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
01833   *            @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
01834   *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
01835   */
01836 #define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
01837
01838 /** @brief macro to configure the UART8 clock (UART8CLK).
01839   *
01840   * @param  __UART8CLKSource__: specifies the UART8 clock source.
01841   *          This parameter can be one of the following values:
01842   *            @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
01843   *            @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
01844   *            @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
01845   *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
01846   *            @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
01847   *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
01848   */
01849 #define __HAL_RCC_UART8_CONFIG(__UART8CLKSource__) \
01850                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART8CLKSource__))
01851
01852 /** @brief  macro to get the UART8 clock source.
01853   * @retval The clock source can be one of the following values:
01854   *            @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
01855   *            @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
01856   *            @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
01857   *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
01858   *            @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
01859   *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
01860   */
01861 #define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
01862
01863 /** @brief macro to configure the LPUART1 clock (LPUART1CLK).
01864   *
01865   * @param  __LPUART1CLKSource__: specifies the LPUART1 clock source.
01866   *          This parameter can be one of the following values:
01867   *            @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
01868   *            @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
01869   *            @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
01870   *            @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
01871   *            @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
01872   *            @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
01873   */
01874 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
01875                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
01876
01877 /** @brief  macro to get the LPUART1 clock source.
01878   * @retval The clock source can be one of the following values:
01879   *            @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
01880   *            @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
01881   *            @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
01882   *            @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
01883   *            @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
01884   *            @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
01885   */
01886 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))
01887
01888 /** @brief  macro to get the LPTIM1 clock source.
01889   * @retval The clock source can be one of the following values:
01890   *            @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
01891   *            @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
01892   *            @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
01893   *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
01894   *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
01895   *            @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
01896   */
01897 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
01898                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
01899
01900
01901 /** @brief  macro to get the LPTIM1 clock source.
01902   * @retval The clock source can be one of the following values:
01903   *            @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
01904   *            @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
01905   *            @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
01906   *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
01907   *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
01908   *            @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
01909   */
01910 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))
01911
01912 /** @brief  macro to get the LPTIM2 clock source.
01913   * @retval The clock source can be one of the following values:
01914   *            @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
01915   *            @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
01916   *            @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
01917   *            @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
01918   *            @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
01919   *            @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
01920   */
01921 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \
01922                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
01923
01924
01925 /** @brief  macro to get the LPTIM2 clock source.
01926   * @retval The clock source can be one of the following values:
01927   *            @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
01928   *            @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
01929   *            @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
01930   *            @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
01931   *            @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
01932   *            @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
01933   */
01934 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))
01935
01936 /** @brief  macro to get the LPTIM3 clock source.
01937   * @retval The clock source can be one of the following values:
01938   *            @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
01939   *            @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
01940   *            @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
01941   *            @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
01942   *            @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
01943   *            @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
01944   */
01945 #define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3CLKSource__) \
01946                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM3CLKSource__))
01947
01948
01949 /** @brief  macro to get the LPTIM3 clock source.
01950   * @retval The clock source can be one of the following values:
01951   *            @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
01952   *            @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
01953   *            @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
01954   *            @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
01955   *            @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
01956   *            @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
01957   */
01958 #define __HAL_RCC_GET_LPTIM3_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
01959
01960 /** @brief  macro to get the LPTIM4 clock source.
01961   * @retval The clock source can be one of the following values:
01962   *            @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
01963   *            @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
01964   *            @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
01965   *            @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
01966   *            @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
01967   *            @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock
01968   */
01969 #define __HAL_RCC_LPTIM4_CONFIG(__LPTIM4CLKSource__) \
01970                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM4CLKSource__))
01971
01972
01973 /** @brief  macro to get the LPTIM4 clock source.
01974   * @retval The clock source can be one of the following values:
01975   *            @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
01976   *            @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
01977   *            @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
01978   *            @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
01979   *            @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
01980   *            @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock
01981   */
01982 #define __HAL_RCC_GET_LPTIM4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
01983
01984 /** @brief  macro to configure the LPTIM5 clock source.
01985   * @retval The clock source can be one of the following values:
01986   *            @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
01987   *            @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
01988   *            @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
01989   *            @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
01990   *            @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
01991   *            @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock
01992   */
01993 #define __HAL_RCC_LPTIM5_CONFIG(__LPTIM5CLKSource__) \
01994                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM5CLKSource__))
01995
01996
01997 /** @brief  macro to get the LPTIM5 clock source.
01998   * @retval The clock source can be one of the following values:
01999   *            @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
02000   *            @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
02001   *            @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
02002   *            @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
02003   *            @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
02004   *            @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock
02005   */
02006 #define __HAL_RCC_GET_LPTIM5_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
02007
02008 /** @brief  macro to configure the QSPI clock source.
02009   * @retval The clock source can be one of the following values:
02010   *            @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock
02011   *            @arg RCC_RCC_QSPICLKSOURCE_PLL   : PLL1_Q Clock selected as QSPI clock
02012   *            @arg RCC_RCC_QSPICLKSOURCE_PLL2  : PLL2_R Clock selected as QSPI clock
02013   *            @arg RCC_RCC_QSPICLKSOURCE_CLKP    CLKP selected as QSPI clock
02014   */
02015 #define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \
02016                   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__))
02017
02018
02019 /** @brief  macro to get the QSPI clock source.
02020   * @retval The clock source can be one of the following values:
02021   *            @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock
02022   *            @arg RCC_RCC_QSPICLKSOURCE_PLL   : PLL1_Q Clock selected as QSPI clock
02023   *            @arg RCC_RCC_QSPICLKSOURCE_PLL2  : PLL2_R Clock selected as QSPI clock
02024   *            @arg RCC_RCC_QSPICLKSOURCE_CLKP    CLKP selected as QSPI clock
02025   */
02026 #define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)))
02027
02028
02029 /** @brief  macro to configure the FMC clock source.
02030   * @retval The clock source can be one of the following values:
02031   *            @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
02032   *            @arg RCC_RCC_FMCCLKSOURCE_PLL   : PLL1_Q Clock selected as FMC clock
02033   *            @arg RCC_RCC_FMCCLKSOURCE_PLL2  : PLL2_R Clock selected as FMC clock
02034   *            @arg RCC_RCC_FMCCLKSOURCE_CLKP    CLKP selected as FMC clock
02035   */
02036 #define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \
02037                   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
02038
02039
02040 /** @brief  macro to get the FMC clock source.
02041   * @retval The clock source can be one of the following values:
02042   *            @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
02043   *            @arg RCC_RCC_FMCCLKSOURCE_PLL   : PLL1_Q Clock selected as FMC clock
02044   *            @arg RCC_RCC_FMCCLKSOURCE_PLL2  : PLL2_R Clock selected as FMC clock
02045   *            @arg RCC_RCC_FMCCLKSOURCE_CLKP    CLKP selected as FMC clock
02046   */
02047 #define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))
02048
02049 /** @brief  Macro to configure the USB clock (USBCLK).
02050   * @param  __USBCLKSource__: specifies the USB clock source.
02051   *         This parameter can be one of the following values:
02052   *            @arg RCC_USBCLKSOURCE_PLL:   PLL1Q selected as USB clock
02053   *            @arg RCC_USBCLKSOURCE_PLL3:  PLL3Q Clock selected as USB clock
02054   *            @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
02055   */
02056 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
02057                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
02058
02059 /** @brief  Macro to get the USB clock source.
02060   * @retval The clock source can be one of the following values:
02061   *            @arg RCC_USBCLKSOURCE_PLL:   PLL1Q selected as USB clock
02062   *            @arg RCC_USBCLKSOURCE_PLL3:  PLL3Q Clock selected as USB clock
02063   *            @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
02064   */
02065 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)))
02066
02067
02068 /** @brief  Macro to configure the ADC clock
02069   * @param  __ADCCLKSource__: specifies the ADC digital interface clock source.
02070   *         This parameter can be one of the following values:
02071   *            @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
02072   *            @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
02073   *            @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
02074   */
02075 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \
02076                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
02077
02078 /** @brief  Macro to get the ADC clock source.
02079   * @retval The clock source can be one of the following values:
02080   *            @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
02081   *            @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
02082   *            @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
02083   */
02084 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))
02085
02086  /** @brief  Macro to configure the SWPMI1 clock
02087   * @param  __SWPMI1CLKSource__: specifies the SWPMI1  clock source.
02088   *         This parameter can be one of the following values:
02089   *            @arg RCC_SWPMI1CLKSOURCE_D2PCLK1:  D2PCLK1 Clock selected as SWPMI1 clock
02090   *            @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
02091   */
02092 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
02093                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
02094
02095 /** @brief  Macro to get the SWPMI1 clock source.
02096   * @retval The clock source can be one of the following values:
02097   *            @arg RCC_SWPMI1CLKSOURCE_D2PCLK1:  D2PCLK1 Clock selected as SWPMI1 clock
02098   *            @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
02099   */
02100 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))
02101
02102  /** @brief  Macro to configure the DFSDM1 clock
02103   * @param  __DFSDM1CLKSource__: specifies the DFSDM1  clock source.
02104   *         This parameter can be one of the following values:
02105   *            @arg RCC_DFSDM1CLKSOURCE_D2PCLK:  D2PCLK Clock selected as DFSDM1 clock
02106   *            @arg RCC_DFSDM1CLKSOURCE_SYS:     System Clock selected as DFSDM1 clock
02107   */
02108 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
02109                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
02110
02111 /** @brief  Macro to get the DFSDM1 clock source.
02112   * @retval The clock source can be one of the following values:
02113   *            @arg RCC_DFSDM1CLKSOURCE_D2PCLK:  D2PCLK Clock selected as DFSDM1 clock
02114   *            @arg RCC_DFSDM1CLKSOURCE_SYS:   System Clock selected as DFSDM1 clock
02115   */
02116 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)))
02117
02118 /** @brief macro to configure the CEC clock (CECCLK).
02119   *
02120   * @param  __CECCLKSource__: specifies the CEC clock source.
02121   *          This parameter can be one of the following values:
02122   *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
02123   *            @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
02124   *            @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
02125   */
02126 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
02127                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
02128
02129 /** @brief  macro to get the CEC clock source.
02130   * @retval The clock source can be one of the following values:
02131   *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
02132   *            @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
02133   *            @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
02134   */
02135 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)))
02136
02137
02138 /** @brief  Macro to configure the CLKP : Oscillator clock for peripheral
02139   * @param  __CLKPSource__: specifies Oscillator clock for peripheral
02140   *         This parameter can be one of the following values:
02141   *            @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
02142   *            @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
02143   *            @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
02144   */
02145 #define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \
02146                   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
02147
02148 /** @brief  Macro to get the Oscillator clock for peripheral  source.
02149   * @retval The clock source can be one of the following values:
02150   *            @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
02151   *            @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
02152   *            @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
02153   */
02154 #define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)))
02155
02156 #if defined(FDCAN1) || defined(FDCAN2)
02157 /** @brief  Macro to configure the FDCAN clock
02158   * @param  __FDCANCLKSource__: specifies  clock source  for FDCAN
02159   *         This parameter can be one of the following values:
02160   *            @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
02161   *            @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
02162   *            @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock
02163   */
02164 #define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \
02165                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
02166
02167 /** @brief  Macro to get the FDCAN clock
02168   * @retval The clock source can be one of the following values:
02169   *            @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
02170   *            @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
02171   *            @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock
02172   */
02173 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)))
02174 #endif /*FDCAN1 || FDCAN2*/
02175 /**
02176   * @brief  Macro to Configure the SPI1 clock source.
02177   * @param  __RCC_SPI1CLKSource__: defines the SPI1 clock source. This clock is derived
02178   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
02179   *          This parameter can be one of the following values:
02180   *             @arg RCC_SPI1CLK_PLL: SPI1 clock = PLL
02181   *             @arg RCC_SPI1CLK_PLL2: SPI1 clock = PLL2
02182   *             @arg RCC_SPI1CLK_PLL3: SPI1 clock = PLL3
02183   *             @arg RCC_SPI1CLK_CLKP: SPI1 clock  = CLKP
02184   *             @arg RCC_SPI1CLK_PIN: SPI1 clock = External Clock
02185   * @retval None
02186   */
02187 #define __HAL_RCC_SPI1_CONFIG(__RCC_SPI1CLKSource__ )\
02188                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI1CLKSource__))
02189
02190 /** @brief  Macro to get the SPI1 clock source.
02191   * @retval The clock source can be one of the following values:
02192   *             @arg RCC_SPI1CLK_PLL: SPI1 clock = PLL
02193   *             @arg RCC_SPI1CLK_PLL2: SPI1 clock = PLL2
02194   *             @arg RCC_SPI1CLK_PLL3: SPI1 clock = PLL3
02195   *             @arg RCC_SPI1CLK_CLKP: SPI1 clock  = CLKP
02196   *             @arg RCC_SPI1CLK_PIN: SPI1 clock = External Clock
02197   */
02198 #define __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
02199
02200 /**
02201   * @brief  Macro to Configure the SPI2 clock source.
02202   * @param  __RCC_SPI2CLKSource__: defines the SPI2 clock source. This clock is derived
02203   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
02204   *          This parameter can be one of the following values:
02205   *             @arg RCC_SPI2CLK_PLL: SPI2 clock = PLL
02206   *             @arg RCC_SPI2CLK_PLL2: SPI2 clock = PLL2
02207   *             @arg RCC_SPI2CLK_PLL3: SPI2 clock = PLL3
02208   *             @arg RCC_SPI2CLK_CLKP: SPI2 clock  = CLKP
02209   *             @arg RCC_SPI2CLK_PIN: SPI2 clock = External Clock
02210   * @retval None
02211   */
02212 #define __HAL_RCC_SPI2_CONFIG(__RCC_SPI2CLKSource__ )\
02213                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI2CLKSource__))
02214
02215 /** @brief  Macro to get the SPI2 clock source.
02216   * @retval The clock source can be one of the following values:
02217   *             @arg RCC_SPI2CLK_PLL: SPI2 clock = PLL
02218   *             @arg RCC_SPI2CLK_PLL2: SPI2 clock = PLL2
02219   *             @arg RCC_SPI2CLK_PLL3: SPI2 clock = PLL3
02220   *             @arg RCC_SPI2CLK_CLKP: SPI2 clock  = CLKP
02221   *             @arg RCC_SPI2CLK_PIN: SPI2 clock = External Clock
02222   */
02223 #define __HAL_RCC_GET_SPI2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
02224
02225 /**
02226   * @brief  Macro to Configure the SPI3 clock source.
02227   * @param  __RCC_SPI3CLKSource__: defines the SPI3 clock source. This clock is derived
02228   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
02229   *          This parameter can be one of the following values:
02230   *             @arg RCC_SPI3CLK_PLL: SPI3 clock = PLL
02231   *             @arg RCC_SPI3CLK_PLL2: SPI3 clock = PLL2
02232   *             @arg RCC_SPI3CLK_PLL3: SPI3 clock = PLL3
02233   *             @arg RCC_SPI3CLK_CLKP: SPI3 clock  = CLKP
02234   *             @arg RCC_SPI3CLK_PIN: SPI3 clock = External Clock
02235   * @retval None
02236   */
02237 #define __HAL_RCC_SPI3_CONFIG(__RCC_SPI3CLKSource__ )\
02238                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI3CLKSource__))
02239
02240 /** @brief  Macro to get the SPI3 clock source.
02241   * @retval The clock source can be one of the following values:
02242   *             @arg RCC_SPI3CLK_PLL: SPI3 clock = PLL
02243   *             @arg RCC_SPI3CLK_PLL2: SPI3 clock = PLL2
02244   *             @arg RCC_SPI3CLK_PLL3: SPI3 clock = PLL3
02245   *             @arg RCC_SPI3CLK_CLKP: SPI3 clock  = CLKP
02246   *             @arg RCC_SPI3CLK_PIN: SPI3 clock = External Clock
02247   */
02248 #define __HAL_RCC_GET_SPI3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
02249
02250
02251 /**
02252   * @brief  Macro to Configure the SPI4 clock source.
02253   * @param  __RCC_SPI4CLKSource__: defines the SPI4 clock source. This clock is derived
02254   *         from system PCLK, PLL2, PLL3, OSC
02255   *          This parameter can be one of the following values:
02256   *             @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
02257   *             @arg RCC_SPI4CLKSOURCE_PLL2:   SPI4 clock = PLL2
02258   *             @arg RCC_SPI4CLKSOURCE_PLL3:   SPI4 clock = PLL3
02259   *             @arg RCC_SPI4CLKSOURCE_HSI:    SPI4 clock = HSI
02260   *             @arg RCC_SPI4CLKSOURCE_CSI:    SPI4 clock = CSI
02261   *             @arg RCC_SPI4CLKSOURCE_HSE:    SPI4 clock = HSE
02262   * @retval None
02263   */
02264 #define __HAL_RCC_SPI4_CONFIG(__RCC_SPI4CLKSource__ )\
02265                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI4CLKSource__))
02266
02267 /** @brief  Macro to get the SPI4 clock source.
02268   * @retval The clock source can be one of the following values:
02269   *             @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
02270   *             @arg RCC_SPI4CLKSOURCE_PLL2:   SPI4 clock = PLL2
02271   *             @arg RCC_SPI4CLKSOURCE_PLL3:   SPI4 clock = PLL3
02272   *             @arg RCC_SPI4CLKSOURCE_HSI:    SPI4 clock = HSI
02273   *             @arg RCC_SPI4CLKSOURCE_CSI:    SPI4 clock = CSI
02274   *             @arg RCC_SPI4CLKSOURCE_HSE:    SPI4 clock = HSE
02275 */
02276 #define __HAL_RCC_GET_SPI4_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
02277
02278
02279 /**
02280   * @brief  Macro to Configure the SPI5 clock source.
02281   * @param  __RCC_SPI5CLKSource__: defines the SPI5 clock source. This clock is derived
02282   *         from system PCLK, PLL2, PLL3, OSC
02283   *          This parameter can be one of the following values:
02284   *             @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
02285   *             @arg RCC_SPI5CLKSOURCE_PLL2:   SPI5 clock = PLL2
02286   *             @arg RCC_SPI5CLKSOURCE_PLL3:   SPI5 clock = PLL3
02287   *             @arg RCC_SPI5CLKSOURCE_HSI:    SPI5 clock = HSI
02288   *             @arg RCC_SPI5CLKSOURCE_CSI:    SPI5 clock = CSI
02289   *             @arg RCC_SPI5CLKSOURCE_HSE:    SPI5 clock = HSE
02290   * @retval None
02291   */
02292 #define __HAL_RCC_SPI5_CONFIG(__RCC_SPI5CLKSource__ )\
02293                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI5CLKSource__))
02294
02295 /** @brief  Macro to get the SPI5 clock source.
02296   * @retval The clock source can be one of the following values:
02297   *             @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
02298   *             @arg RCC_SPI5CLKSOURCE_PLL2:   SPI5 clock = PLL2
02299   *             @arg RCC_SPI5CLKSOURCE_PLL3:   SPI5 clock = PLL3
02300   *             @arg RCC_SPI5CLKSOURCE_HSI:    SPI5 clock = HSI
02301   *             @arg RCC_SPI5CLKSOURCE_CSI:    SPI5 clock = CSI
02302   *             @arg RCC_SPI5CLKSOURCE_HSE:    SPI5 clock = HSE
02303 */
02304 #define __HAL_RCC_GET_SPI5_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
02305
02306 /**
02307   * @brief  Macro to Configure the SPI6 clock source.
02308   * @param  __RCC_SPI6CLKSource__: defines the SPI6 clock source. This clock is derived
02309   *         from system PCLK, PLL2, PLL3, OSC
02310   *          This parameter can be one of the following values:
02311   *             @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
02312   *             @arg RCC_SPI6CLKSOURCE_PLL2:   SPI6 clock = PLL2
02313   *             @arg RCC_SPI6CLKSOURCE_PLL3:   SPI6 clock = PLL3
02314   *             @arg RCC_SPI6CLKSOURCE_HSI:    SPI6 clock = HSI
02315   *             @arg RCC_SPI6CLKSOURCE_CSI:    SPI6 clock = CSI
02316   *             @arg RCC_SPI6CLKSOURCE_HSE:    SPI6 clock = HSE
02317   * @retval None
02318   */
02319 #define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\
02320                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
02321
02322 /** @brief  Macro to get the SPI6 clock source.
02323   * @retval The clock source can be one of the following values:
02324   *             @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
02325   *             @arg RCC_SPI6CLKSOURCE_PLL2:   SPI6 clock = PLL2
02326   *             @arg RCC_SPI6CLKSOURCE_PLL3:   SPI6 clock = PLL3
02327   *             @arg RCC_SPI6CLKSOURCE_HSI:    SPI6 clock = HSI
02328   *             @arg RCC_SPI6CLKSOURCE_CSI:    SPI6 clock = CSI
02329   *             @arg RCC_SPI6CLKSOURCE_HSE:    SPI6 clock = HSE
02330 */
02331 #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))
02332
02333 /** @brief  Macro to configure the SDMMC clock
02334   * @param  __SDMMCCLKSource__: specifies  clock source  for SDMMC
02335   *         This parameter can be one of the following values:
02336   *            @arg RCC_SDMMCCLKSOURCE_PLL:  PLLQ selected as SDMMC clock
02337   *            @arg RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock
02338   */
02339 #define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \
02340                   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
02341
02342 /** @brief  Macro to get the SDMMC clock
02343   */
02344 #define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)))
02345
02346 /** @brief macro to configure the RNG clock (RNGCLK).
02347   *
02348   * @param  __RNGCLKSource__: specifies the RNG clock source.
02349   *          This parameter can be one of the following values:
02350   *            @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
02351   *            @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
02352   *            @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
02353   *            @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
02354   */
02355 #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
02356                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
02357
02358 /** @brief  macro to get the RNG clock source.
02359   * @retval The clock source can be one of the following values:
02360   *            @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
02361   *            @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
02362   *            @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
02363   *            @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
02364   */
02365 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)))
02366
02367
02368 /** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
02369   * @{
02370   */
02371 /** @brief  Macro to configure the HRTIM1 prescaler clock source.
02372   * @param  __HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source.
02373   *         This parameter can be one of the following values:
02374   *            @arg @ref RCC_HRTIM1CLK_TIMCLK    Timers  clock  selected as HRTIM1 prescaler clock
02375   *            @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock
02376   */
02377 #define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
02378                   MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__))
02379
02380 /** @brief  Macro to get the HRTIM1 clock source.
02381   * @retval The clock source can be one of the following values:
02382   *            @arg @ref RCC_HRTIM1CLK_TIMCLK   Timers  clock  selected as HRTIM1 prescaler clock
02383   *            @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock
02384   */
02385 #define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)))
02386
02387 /** @brief  Macro to configure the Timers clocks prescalers
02388   * @param  __PRESC__ : specifies the Timers clocks prescalers selection
02389   *         This parameter can be one of the following values:
02390   *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
02391   *                 equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2,
02392   *                 else it is equal to 2 x Frcc_pclkx_d2 (default after reset)
02393   *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
02394   *                 equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4,
02395   *                 else it is equal to 4 x Frcc_pclkx_d2
02396   */
02397 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\
02398                                                  RCC->CFGR |= (__PRESC__);       \
02399                                                 }while(0)
02400
02401 /**
02402   * @}
02403   */
02404 /**
02405   * @brief  Enable the specified CRS interrupts.
02406   * @param  __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
02407   *          This parameter can be any combination of the following values:
02408   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
02409   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
02410   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
02411   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
02412   * @retval None
02413   */
02414 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   SET_BIT(CRS->CR, (__INTERRUPT__))
02415
02416 /**
02417   * @brief  Disable the specified CRS interrupts.
02418   * @param  __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
02419   *          This parameter can be any combination of the following values:
02420   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
02421   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
02422   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
02423   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
02424   * @retval None
02425   */
02426 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT(CRS->CR, (__INTERRUPT__))
02427
02428 /** @brief  Check whether the CRS interrupt has occurred or not.
02429   * @param  __INTERRUPT__ specifies the CRS interrupt source to check.
02430   *         This parameter can be one of the following values:
02431   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
02432   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
02433   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
02434   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
02435   * @retval The new state of __INTERRUPT__ (SET or RESET).
02436   */
02437 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__)  ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
02438
02439 /** @brief  Clear the CRS interrupt pending bits
02440   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
02441   *         This parameter can be any combination of the following values:
02442   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
02443   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
02444   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
02445   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
02446   *              @arg @ref RCC_CRS_IT_TRIMOVF  Trimming overflow or underflow interrupt
02447   *              @arg @ref RCC_CRS_IT_SYNCERR  SYNC error interrupt
02448   *              @arg @ref RCC_CRS_IT_SYNCMISS  SYNC missed interrupt
02449   */
02450 /* CRS IT Error Mask */
02451 #define  RCC_CRS_IT_ERROR_MASK                 ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
02452
02453 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)  do { \
02454                                                  if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
02455                                                  { \
02456                                                    WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
02457                                                  } \
02458                                                  else \
02459                                                  { \
02460                                                    WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
02461                                                  } \
02462                                                } while(0)
02463
02464 /**
02465   * @brief  Check whether the specified CRS flag is set or not.
02466   * @param  __FLAG__ specifies the flag to check.
02467   *          This parameter can be one of the following values:
02468   *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
02469   *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
02470   *              @arg @ref RCC_CRS_FLAG_ERR  Error
02471   *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
02472   *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
02473   *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
02474   *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
02475   * @retval The new state of _FLAG_ (TRUE or FALSE).
02476   */
02477 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__)  (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
02478
02479 /**
02480   * @brief  Clear the CRS specified FLAG.
02481   * @param __FLAG__ specifies the flag to clear.
02482   *          This parameter can be one of the following values:
02483   *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
02484   *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
02485   *              @arg @ref RCC_CRS_FLAG_ERR  Error
02486   *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
02487   *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
02488   *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
02489   *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
02490   * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
02491   * @retval None
02492   */
02493
02494 /* CRS Flag Error Mask */
02495 #define RCC_CRS_FLAG_ERROR_MASK                ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
02496
02497 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)     do { \
02498                                                  if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \
02499                                                  { \
02500                                                    WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
02501                                                  } \
02502                                                  else \
02503                                                  { \
02504                                                    WRITE_REG(CRS->ICR, (__FLAG__)); \
02505                                                  } \
02506                                                } while(0)
02507
02508  /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
02509   * @{
02510   */
02511 /**
02512   * @brief  Enable the oscillator clock for frequency error counter.
02513   * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.
02514   * @retval None
02515   */
02516 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE()  SET_BIT(CRS->CR, CRS_CR_CEN)
02517
02518 /**
02519   * @brief  Disable the oscillator clock for frequency error counter.
02520   * @retval None
02521   */
02522 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
02523
02524 /**
02525   * @brief  Enable the automatic hardware adjustment of TRIM bits.
02526   * @note   When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
02527   * @retval None
02528   */
02529 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE()     SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
02530
02531 /**
02532   * @brief  Enable or disable the automatic hardware adjustment of TRIM bits.
02533   * @retval None
02534   */
02535 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE()    CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
02536
02537 /**
02538   * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
02539   * @note   The RELOAD value should be selected according to the ratio between the target frequency and the frequency
02540   *             of the synchronization source after pre-scaling. It is then decreased by one in order to
02541   *             reach the expected synchronization on the zero value. The formula is the following:
02542   *             RELOAD = (fTARGET / fSYNC) -1
02543   * @param  __FTARGET__ Target frequency (value in Hz)
02544   * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
02545   * @retval None
02546   */
02547 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)  (((__FTARGET__) / (__FSYNC__)) - 1U)
02548
02549
02550 /**
02551   * @}
02552   */
02553
02554
02555 /**
02556   * @}
02557   */
02558
02559
02560 /* Exported functions --------------------------------------------------------*/
02561 /** @addtogroup RCCEx_Exported_Functions_Group1
02562   * @{
02563   */
02564 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
02565 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
02566 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
02567 uint32_t HAL_RCCEx_GetD1PCLK1Freq(void);
02568 uint32_t HAL_RCCEx_GetD3PCLK1Freq(void);
02569 uint32_t HAL_RCCEx_GetD1SysClockFreq(void);
02570 void     HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks);
02571 void     HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks);
02572 void     HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks);
02573 /**
02574   * @}
02575   */
02576
02577 /** @addtogroup RCCEx_Exported_Functions_Group2
02578   * @{
02579   */
02580 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
02581 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk);
02582 void HAL_RCCEx_EnableLSECSS(void);
02583 void HAL_RCCEx_DisableLSECSS(void);
02584 void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx);
02585 /**
02586   * @}
02587   */
02588
02589
02590 /** @addtogroup RCCEx_Exported_Functions_Group3
02591   * @{
02592   */
02593
02594 void     HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
02595 void     HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
02596 void     HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
02597 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
02598 void     HAL_RCCEx_CRS_IRQHandler(void);
02599 void     HAL_RCCEx_CRS_SyncOkCallback(void);
02600 void     HAL_RCCEx_CRS_SyncWarnCallback(void);
02601 void     HAL_RCCEx_CRS_ExpectedSyncCallback(void);
02602 void     HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
02603
02604 /**
02605   * @}
02606   */
02607
02608  /* Private macros ------------------------------------------------------------*/
02609 /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
02610   * @{
02611   */
02612 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
02613   * @{
02614   */
02615
02616
02617 #define IS_RCC_PERIPHCLOCK(SELECTION)  (((SELECTION) == RCC_PERIPHCLK_USART1)  || \
02618                                         ((SELECTION) == RCC_PERIPHCLK_USART2)  || \
02619                                         ((SELECTION) == RCC_PERIPHCLK_USART3)  || \
02620                                         ((SELECTION) == RCC_PERIPHCLK_UART4)   || \
02621                                         ((SELECTION) == RCC_PERIPHCLK_UART5)   || \
02622                                         ((SELECTION) == RCC_PERIPHCLK_LPUART1) || \
02623                                         ((SELECTION) == RCC_PERIPHCLK_I2C1)    || \
02624                                         ((SELECTION) == RCC_PERIPHCLK_I2C2)    || \
02625                                         ((SELECTION) == RCC_PERIPHCLK_I2C3)    || \
02626                                         ((SELECTION) == RCC_PERIPHCLK_LPTIM1)  || \
02627                                         ((SELECTION) == RCC_PERIPHCLK_LPTIM2)  || \
02628                                         ((SELECTION) == RCC_PERIPHCLK_SAI1)    || \
02629                                         ((SELECTION) == RCC_PERIPHCLK_SAI2)    || \
02630                                         ((SELECTION) == RCC_PERIPHCLK_USB)     || \
02631                                         ((SELECTION) == RCC_PERIPHCLK_ADC)     || \
02632                                         ((SELECTION) == RCC_PERIPHCLK_SWPMI1)  || \
02633                                         ((SELECTION) == RCC_PERIPHCLK_DFSDM1)  || \
02634                                         ((SELECTION) == RCC_PERIPHCLK_RTC)     || \
02635                                         ((SELECTION) == RCC_PERIPHCLK_CEC)     || \
02636                                         ((SELECTION) == RCC_PERIPHCLK_USART6)  || \
02637                                         ((SELECTION) == RCC_PERIPHCLK_UART7)   || \
02638                                         ((SELECTION) == RCC_PERIPHCLK_UART8)   || \
02639                                         ((SELECTION) == RCC_PERIPHCLK_I2C4)    || \
02640                                         ((SELECTION) == RCC_PERIPHCLK_LPTIM3)  || \
02641                                         ((SELECTION) == RCC_PERIPHCLK_LPTIM4)  || \
02642                                         ((SELECTION) == RCC_PERIPHCLK_LPTIM5)  || \
02643                                         ((SELECTION) == RCC_PERIPHCLK_SAI3)    || \
02644                                         ((SELECTION) == RCC_PERIPHCLK_SAI4A)   || \
02645                                         ((SELECTION) == RCC_PERIPHCLK_SAI4B)   || \
02646                                         ((SELECTION) == RCC_PERIPHCLK_FMC)     || \
02647                                         ((SELECTION) == RCC_PERIPHCLK_QSPI)    || \
02648                                         ((SELECTION) == RCC_PERIPHCLK_DSI)     || \
02649                                         ((SELECTION) == RCC_PERIPHCLK_CKPER)   || \
02650                                         ((SELECTION) == RCC_PERIPHCLK_SPDIFRX) || \
02651                                         ((SELECTION) == RCC_PERIPHCLK_FDCAN)   || \
02652                                         ((SELECTION) == RCC_PERIPHCLK_SPI1)    || \
02653                                         ((SELECTION) == RCC_PERIPHCLK_SPI2)    || \
02654                                         ((SELECTION) == RCC_PERIPHCLK_SPI3)    || \
02655                                         ((SELECTION) == RCC_PERIPHCLK_SPI4)    || \
02656                                         ((SELECTION) == RCC_PERIPHCLK_SPI5)    || \
02657                                         ((SELECTION) == RCC_PERIPHCLK_SPI6)    || \
02658                                         ((SELECTION) == RCC_PERIPHCLK_SDMMC)   || \
02659                                         ((SELECTION) == RCC_PERIPHCLK_LTDC)    || \
02660                                         ((SELECTION) == RCC_PERIPHCLK_RNG))
02661
02662 #define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \
02663                                          ((VALUE) == RCC_PLL2_DIVQ)  || \
02664                                          ((VALUE) == RCC_PLL2_DIVR))
02665
02666 #define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \
02667                                           ((VALUE) == RCC_PLL3_DIVQ) || \
02668                                           ((VALUE) == RCC_PLL3_DIVR))
02669
02670 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \
02671                                         ((SOURCE) == RCC_USART1CLKSOURCE_PLL2)   || \
02672                                         ((SOURCE) == RCC_USART1CLKSOURCE_PLL3)   || \
02673                                         ((SOURCE) == RCC_USART1CLKSOURCE_CSI)    || \
02674                                         ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \
02675                                         ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
02676
02677 #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \
02678                                         ((SOURCE) == RCC_USART2CLKSOURCE_PLL2)   || \
02679                                         ((SOURCE) == RCC_USART2CLKSOURCE_PLL3)   || \
02680                                         ((SOURCE) == RCC_USART2CLKSOURCE_CSI)    || \
02681                                         ((SOURCE) == RCC_USART2CLKSOURCE_LSE)    || \
02682                                         ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
02683
02684 #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \
02685                                         ((SOURCE) == RCC_USART3CLKSOURCE_PLL2)   || \
02686                                         ((SOURCE) == RCC_USART3CLKSOURCE_PLL3)   || \
02687                                         ((SOURCE) == RCC_USART3CLKSOURCE_CSI)    || \
02688                                         ((SOURCE) == RCC_USART3CLKSOURCE_LSE)    || \
02689                                         ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
02690
02691 #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \
02692                                         ((SOURCE) == RCC_UART4CLKSOURCE_PLL2)   || \
02693                                         ((SOURCE) == RCC_UART4CLKSOURCE_PLL3)   || \
02694                                         ((SOURCE) == RCC_UART4CLKSOURCE_CSI)    || \
02695                                         ((SOURCE) == RCC_UART4CLKSOURCE_LSE)    || \
02696                                         ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
02697
02698 #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \
02699                                         ((SOURCE) == RCC_UART5CLKSOURCE_PLL2)   || \
02700                                         ((SOURCE) == RCC_UART5CLKSOURCE_PLL3)   || \
02701                                         ((SOURCE) == RCC_UART5CLKSOURCE_CSI)    || \
02702                                         ((SOURCE) == RCC_UART5CLKSOURCE_LSE)    || \
02703                                         ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
02704
02705 #define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \
02706                                         ((SOURCE) == RCC_USART6CLKSOURCE_PLL2)   || \
02707                                         ((SOURCE) == RCC_USART6CLKSOURCE_PLL3)   || \
02708                                         ((SOURCE) == RCC_USART6CLKSOURCE_CSI)    || \
02709                                         ((SOURCE) == RCC_USART6CLKSOURCE_LSE)    || \
02710                                         ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
02711
02712 #define IS_RCC_UART7CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1)|| \
02713                                         ((SOURCE) == RCC_UART7CLKSOURCE_PLL2)  || \
02714                                         ((SOURCE) == RCC_UART7CLKSOURCE_PLL3)  || \
02715                                         ((SOURCE) == RCC_UART7CLKSOURCE_CSI)   || \
02716                                         ((SOURCE) == RCC_UART7CLKSOURCE_LSE)   || \
02717                                         ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
02718
02719 #define IS_RCC_UART8CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1)|| \
02720                                         ((SOURCE) == RCC_UART8CLKSOURCE_PLL2)  || \
02721                                         ((SOURCE) == RCC_UART8CLKSOURCE_PLL3)  || \
02722                                         ((SOURCE) == RCC_UART8CLKSOURCE_CSI)   || \
02723                                         ((SOURCE) == RCC_UART8CLKSOURCE_LSE)   || \
02724                                         ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
02725
02726 #define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \
02727                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2)     || \
02728                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3)     || \
02729                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI)      || \
02730                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE)      || \
02731                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))
02732
02733 #define IS_RCC_I2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3)   || \
02734                                         ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)    || \
02735                                         ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \
02736                                         ((SOURCE) == RCC_I2C1CLKSOURCE_CSI))
02737
02738 #define IS_RCC_I2C2CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3)   || \
02739                                         ((SOURCE) == RCC_I2C2CLKSOURCE_HSI)    || \
02740                                         ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \
02741                                         ((SOURCE) == RCC_I2C2CLKSOURCE_CSI))
02742
02743 #define IS_RCC_I2C3CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3)   || \
02744                                         ((SOURCE) == RCC_I2C3CLKSOURCE_HSI)    || \
02745                                         ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \
02746                                         ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
02747
02748 #define IS_RCC_I2C4CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3)   || \
02749                                         ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)    || \
02750                                         ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \
02751                                         ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
02752
02753 #define IS_RCC_RNGCLKSOURCE(SOURCE)    (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \
02754                                         ((SOURCE) == RCC_RNGCLKSOURCE_PLL)  || \
02755                                         ((SOURCE) == RCC_RNGCLKSOURCE_LSE)  || \
02756                                         ((SOURCE) == RCC_RNGCLKSOURCE_LSI))
02757
02758 #define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \
02759                                         ((SOURCE) == RCC_HRTIM1CLK_CPUCLK))
02760
02761 #define IS_RCC_USBCLKSOURCE(SOURCE)    (((SOURCE) == RCC_USBCLKSOURCE_PLL)  || \
02762                                         ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \
02763                                         ((SOURCE) == RCC_USBCLKSOURCE_HSI48))
02764
02765 #define IS_RCC_SAI1CLK(__SOURCE__)   \
02766                (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)  || \
02767                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \
02768                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \
02769                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \
02770                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
02771
02772 #define IS_RCC_SAI2CLK(__SOURCE__)   \
02773                (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL)  || \
02774                 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \
02775                 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \
02776                 ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \
02777                 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
02778
02779 #define IS_RCC_SPI1CLK(__SOURCE__)   \
02780                (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL)  || \
02781                 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \
02782                 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \
02783                 ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \
02784                 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN))
02785
02786 #define IS_RCC_SPI2CLK(__SOURCE__)   \
02787                (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL)  || \
02788                 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \
02789                 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \
02790                 ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \
02791                 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN))
02792
02793 #define IS_RCC_SPI3CLK(__SOURCE__)   \
02794                (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL)  || \
02795                 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \
02796                 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \
02797                 ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \
02798                 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))
02799
02800 #define IS_RCC_SPI4CLK(__SOURCE__)   \
02801                (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1)  || \
02802                 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2)     || \
02803                 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3)     || \
02804                 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI)      || \
02805                 ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI)      || \
02806                 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))
02807
02808 #define IS_RCC_SPI5CLK(__SOURCE__)   \
02809                (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)|| \
02810                 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2)   || \
02811                 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3)   || \
02812                 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI)    || \
02813                 ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI)    || \
02814                 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE))
02815
02816 #define IS_RCC_SPI6CLK(__SOURCE__)   \
02817                (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \
02818                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2)    || \
02819                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3)    || \
02820                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI)     || \
02821                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI)     || \
02822                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE))
02823
02824 #define IS_RCC_SAI3CLK(__SOURCE__)   \
02825                (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL)  || \
02826                 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \
02827                 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \
02828                 ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \
02829                 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN))
02830
02831 #define IS_RCC_SAI4ACLK(__SOURCE__)   \
02832                (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL)  || \
02833                 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \
02834                 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \
02835                 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \
02836                 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN))
02837
02838 #define IS_RCC_SAI4BCLK(__SOURCE__)   \
02839                (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL)  || \
02840                 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \
02841                 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \
02842                 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \
02843                 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN))
02844
02845 #define IS_RCC_PLL3M_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 63))
02846 #define IS_RCC_PLL3N_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512))
02847 #define IS_RCC_PLL3P_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
02848 #define IS_RCC_PLL3Q_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
02849 #define IS_RCC_PLL3R_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
02850
02851 #define IS_RCC_PLL2M_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 63))
02852 #define IS_RCC_PLL2N_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512))
02853 #define IS_RCC_PLL2P_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
02854 #define IS_RCC_PLL2Q_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
02855 #define IS_RCC_PLL2R_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
02856
02857 #define IS_RCC_LPTIM1CLK(SOURCE)       (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \
02858                                         ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2)   || \
02859                                         ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3)   || \
02860                                         ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)    || \
02861                                         ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI)    || \
02862                                         ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP))
02863
02864 #define IS_RCC_LPTIM2CLK(SOURCE)       (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \
02865                                         ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2)   || \
02866                                         ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3)   || \
02867                                         ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE)    || \
02868                                         ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI)    || \
02869                                         ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP))
02870
02871 #define IS_RCC_LPTIM3CLK(SOURCE)       (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1)|| \
02872                                         ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2)   || \
02873                                         ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3)   || \
02874                                         ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE)    || \
02875                                         ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI)    || \
02876                                         ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP))
02877
02878 #define IS_RCC_LPTIM4CLK(SOURCE)       (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \
02879                                         ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2)   || \
02880                                         ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3)   || \
02881                                         ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE)    || \
02882                                         ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI)    || \
02883                                         ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP))
02884
02885 #define IS_RCC_LPTIM5CLK(SOURCE)       (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \
02886                                         ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2)   || \
02887                                         ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3)   || \
02888                                         ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE)    || \
02889                                         ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI)    || \
02890                                         ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP))
02891
02892 #define IS_RCC_QSPICLK(__SOURCE__)   \
02893                (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK)  || \
02894                 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL)     || \
02895                 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2)    || \
02896                 ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP))
02897
02898
02899 #define IS_RCC_FMCCLK(__SOURCE__)   \
02900                (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK)  || \
02901                 ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL)     || \
02902                 ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2)    || \
02903                 ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP))
02904
02905 #if defined(FDCAN1) || defined(FDCAN2)
02906 #define IS_RCC_FDCANCLK(__SOURCE__)   \
02907                (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)  || \
02908                 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL)  || \
02909                 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2))
02910 #endif /*FDCAN1 || FDCAN2*/
02911
02912 #define IS_RCC_SDMMC(__SOURCE__)   \
02913                 (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL)  || \
02914                 ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2))
02915
02916 #define IS_RCC_USBCLKSOURCE(SOURCE)    (((SOURCE) == RCC_USBCLKSOURCE_PLL)  || \
02917                                         ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \
02918                                         ((SOURCE) == RCC_USBCLKSOURCE_HSI48))
02919
02920 #define IS_RCC_ADCCLKSOURCE(SOURCE)    (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \
02921                                         ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \
02922                                         ((SOURCE) == RCC_ADCCLKSOURCE_CLKP))
02923
02924 #define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \
02925                                         ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI))
02926
02927 #define IS_RCC_DFSDM1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \
02928                                         ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS))
02929
02930 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL)  || \
02931                                         ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \
02932                                         ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \
02933                                         ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI))
02934
02935 #define IS_RCC_CECCLKSOURCE(SOURCE)  (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \
02936                                       ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \
02937                                       ((SOURCE) == RCC_CECCLKSOURCE_CSI))
02938
02939 #define IS_RCC_CLKPSOURCE(SOURCE)   (((SOURCE) == RCC_CLKPSOURCE_HSI)  || \
02940                                       ((SOURCE) == RCC_CLKPSOURCE_CSI) || \
02941                                       ((SOURCE) == RCC_CLKPSOURCE_HSE))
02942 #define IS_RCC_TIMPRES(VALUE)  \
02943                (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
02944                 ((VALUE) == RCC_TIMPRES_ACTIVATED))
02945
02946
02947 #define IS_RCC_SCOPE_WWDG(WWDG)   ((WWDG) == RCC_WWDG1)
02948
02949
02950 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \
02951                                             ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
02952                                             ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1))
02953
02954 #define IS_RCC_CRS_SYNC_DIV(__DIV__)       (((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \
02955                                             ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \
02956                                             ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
02957                                             ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
02958
02959 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
02960                                                 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
02961
02962 #define IS_RCC_CRS_RELOADVALUE(__VALUE__)  (((__VALUE__) <= 0xFFFFU))
02963
02964 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__)   (((__VALUE__) <= 0xFFU))
02965
02966 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
02967
02968 #define IS_RCC_CRS_FREQERRORDIR(__DIR__)   (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
02969                                             ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
02970 /**
02971   * @}
02972   */
02973
02974 /**
02975   * @}
02976   */
02977 /**
02978   * @}
02979   */
02980
02981 /**
02982   * @}
02983   */
02984
02985 #ifdef __cplusplus
02986 }
02987 #endif
02988
02989 #endif /* __STM32H7xx_HAL_RCC_EX_H */
02990
02991 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_rng.c Source File

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stm32h7xx_hal_rng.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rng.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   RNG HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Random Number Generator (RNG) peripheral:
00010   *           + Initialization/de-initialization functions
00011   *           + Peripheral Control functions
00012   *           + Peripheral State functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                      ##### How to use this driver #####
00017   ==============================================================================
00018   [..]
00019       The RNG HAL driver can be used as follows:
00020
00021       (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
00022           in HAL_RNG_MspInit().
00023       (#) Activate the RNG peripheral using HAL_RNG_Init() function.
00024       (#) Wait until the 32 bit Random Number Generator contains a valid
00025           random data using (polling/interrupt) mode.
00026       (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
00027
00028   @endverbatim
00029   ******************************************************************************
00030   * @attention
00031   *
00032   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00033   *
00034   * Redistribution and use in source and binary forms, with or without modification,
00035   * are permitted provided that the following conditions are met:
00036   *   1. Redistributions of source code must retain the above copyright notice,
00037   *      this list of conditions and the following disclaimer.
00038   *   2. Redistributions in binary form must reproduce the above copyright notice,
00039   *      this list of conditions and the following disclaimer in the documentation
00040   *      and/or other materials provided with the distribution.
00041   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00042   *      may be used to endorse or promote products derived from this software
00043   *      without specific prior written permission.
00044   *
00045   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00046   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00047   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00048   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00049   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00050   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00051   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00052   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00053   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00054   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00055   *
00056   ******************************************************************************
00057   */
00058
00059 /* Includes ------------------------------------------------------------------*/
00060 #include "stm32h7xx_hal.h"
00061
00062 /** @addtogroup STM32H7xx_HAL_Driver
00063   * @{
00064   */
00065
00066 /** @addtogroup RNG
00067   * @{
00068   */
00069
00070 #ifdef HAL_RNG_MODULE_ENABLED
00071
00072
00073 /* Private types -------------------------------------------------------------*/
00074 /* Private defines -----------------------------------------------------------*/
00075 /* Private variables ---------------------------------------------------------*/
00076 /* Private constants ---------------------------------------------------------*/
00077 /** @addtogroup RNG_Private_Constants
00078   * @{
00079   */
00080 #define RNG_TIMEOUT_VALUE     2U
00081 /**
00082   * @}
00083   */
00084 /* Private macros ------------------------------------------------------------*/
00085 /* Private functions prototypes ----------------------------------------------*/
00086 /* Private functions ---------------------------------------------------------*/
00087 /* Exported functions --------------------------------------------------------*/
00088
00089 /** @addtogroup RNG_Exported_Functions
00090   * @{
00091   */
00092
00093 /** @addtogroup RNG_Exported_Functions_Group1
00094  *  @brief   Initialization and de-initialization functions
00095  *
00096 @verbatim
00097  ===============================================================================
00098           ##### Initialization and de-initialization functions #####
00099  ===============================================================================
00100     [..]  This section provides functions allowing to:
00101       (+) Initialize the RNG according to the specified parameters
00102           in the RNG_InitTypeDef and create the associated handle
00103       (+) DeInitialize the RNG peripheral
00104       (+) Initialize the RNG MSP
00105       (+) DeInitialize RNG MSP
00106
00107 @endverbatim
00108   * @{
00109   */
00110
00111 /**
00112   * @brief  Initializes the RNG peripheral and creates the associated handle.
00113   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00114   *                the configuration information for RNG.
00115   * @retval HAL status
00116   */
00117 HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
00118 {
00119   /* Check the RNG handle allocation */
00120   if(hrng == NULL)
00121   {
00122     return HAL_ERROR;
00123   }
00124   /* Check the parameters */
00125   assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
00126   assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection));
00127
00128   __HAL_LOCK(hrng);
00129
00130   if(hrng->State == HAL_RNG_STATE_RESET)
00131   {
00132     /* Allocate lock resource and initialize it */
00133     hrng->Lock = HAL_UNLOCKED;
00134     /* Init the low level hardware */
00135     HAL_RNG_MspInit(hrng);
00136   }
00137
00138   /* Change RNG peripheral state */
00139   hrng->State = HAL_RNG_STATE_BUSY;
00140
00141   /* CED Configuration */
00142   MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection);
00143
00144   /* Enable the RNG Peripheral */
00145   __HAL_RNG_ENABLE(hrng);
00146
00147   /* Initialize the RNG state */
00148   hrng->State = HAL_RNG_STATE_READY;
00149
00150   __HAL_UNLOCK(hrng);
00151
00152   /* Return function status */
00153   return HAL_OK;
00154 }
00155
00156 /**
00157   * @brief  DeInitializes the RNG peripheral.
00158   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00159   *                the configuration information for RNG.
00160   * @retval HAL status
00161   */
00162 HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
00163 {
00164   /* Check the RNG handle allocation */
00165   if(hrng == NULL)
00166   {
00167     return HAL_ERROR;
00168   }
00169   /* Disable the RNG Peripheral */
00170   CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN |RNG_CR_CED);
00171
00172   /* Clear RNG interrupt status flags */
00173   CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
00174
00175   /* DeInit the low level hardware */
00176   HAL_RNG_MspDeInit(hrng);
00177
00178   /* Update the RNG state */
00179   hrng->State = HAL_RNG_STATE_RESET;
00180
00181   /* Release Lock */
00182   __HAL_UNLOCK(hrng);
00183
00184   /* Return the function status */
00185   return HAL_OK;
00186 }
00187
00188 /**
00189   * @brief  Initializes the RNG MSP.
00190   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00191   *                the configuration information for RNG.
00192   * @retval None
00193   */
00194 __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
00195 {
00196   /* Prevent unused argument(s) compilation warning */
00197   UNUSED(hrng);
00198   /* NOTE : This function should not be modified. When the callback is needed,
00199             function HAL_RNG_MspInit must be implemented in the user file.
00200    */
00201 }
00202
00203 /**
00204   * @brief  DeInitializes the RNG MSP.
00205   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00206   *                the configuration information for RNG.
00207   * @retval None
00208   */
00209 __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
00210 {
00211   /* Prevent unused argument(s) compilation warning */
00212   UNUSED(hrng);
00213   /* NOTE : This function should not be modified. When the callback is needed,
00214             function HAL_RNG_MspDeInit must be implemented in the user file.
00215    */
00216 }
00217
00218 /**
00219   * @}
00220   */
00221
00222 /** @addtogroup RNG_Exported_Functions_Group2
00223  *  @brief   Peripheral Control functions
00224  *
00225 @verbatim
00226  ===============================================================================
00227                       ##### Peripheral Control functions #####
00228  ===============================================================================
00229     [..]  This section provides functions allowing to:
00230       (+) Get the 32 bit Random number
00231       (+) Get the 32 bit Random number with interrupt enabled
00232       (+) Handle RNG interrupt request
00233
00234 @endverbatim
00235   * @{
00236   */
00237
00238 /**
00239   * @brief  Generates a 32-bit random number.
00240   * @note   Each time the random number data is read the RNG_FLAG_DRDY flag
00241   *         is automatically cleared.
00242   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00243   *                the configuration information for RNG.
00244   * @param  random32bit: pointer to generated random number variable if successful.
00245   * @retval HAL status
00246   */
00247
00248 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
00249 {
00250   uint32_t tickstart = 0U;
00251   HAL_StatusTypeDef status = HAL_OK;
00252
00253   /* Process Locked */
00254   __HAL_LOCK(hrng);
00255
00256   /* Check RNG peripheral state */
00257   if(hrng->State == HAL_RNG_STATE_READY)
00258   {
00259     /* Change RNG peripheral state */
00260     hrng->State = HAL_RNG_STATE_BUSY;
00261
00262     /* Get tick */
00263     tickstart = HAL_GetTick();
00264
00265     /* Check if data register contains valid random data */
00266     while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
00267     {
00268       if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
00269       {
00270         hrng->State = HAL_RNG_STATE_ERROR;
00271
00272         /* Process Unlocked */
00273         __HAL_UNLOCK(hrng);
00274
00275         return HAL_TIMEOUT;
00276       }
00277     }
00278
00279     /* Get a 32bit Random number */
00280     hrng->RandomNumber = hrng->Instance->DR;
00281     *random32bit = hrng->RandomNumber;
00282
00283     hrng->State = HAL_RNG_STATE_READY;
00284   }
00285   else
00286   {
00287     status = HAL_ERROR;
00288   }
00289
00290   /* Process Unlocked */
00291   __HAL_UNLOCK(hrng);
00292
00293   return status;
00294 }
00295
00296 /**
00297   * @brief  Generates a 32-bit random number in interrupt mode.
00298   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00299   *                the configuration information for RNG.
00300   * @retval HAL status
00301   */
00302 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
00303 {
00304   HAL_StatusTypeDef status = HAL_OK;
00305
00306   /* Process Locked */
00307   __HAL_LOCK(hrng);
00308
00309   /* Check RNG peripheral state */
00310   if(hrng->State == HAL_RNG_STATE_READY)
00311   {
00312     /* Change RNG peripheral state */
00313     hrng->State = HAL_RNG_STATE_BUSY;
00314
00315     /* Process Unlocked */
00316     __HAL_UNLOCK(hrng);
00317
00318     /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
00319     __HAL_RNG_ENABLE_IT(hrng);
00320   }
00321   else
00322   {
00323     /* Process Unlocked */
00324     __HAL_UNLOCK(hrng);
00325
00326     status = HAL_ERROR;
00327   }
00328
00329   return status;
00330 }
00331
00332 /**
00333   * @brief  Handles RNG interrupt request.
00334   * @note   In the case of a clock error, the RNG is no more able to generate
00335   *         random numbers because the PLL48CLK clock is not correct. User has
00336   *         to check that the clock controller is correctly configured to provide
00337   *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
00338   *         The clock error has no impact on the previously generated
00339   *         random numbers, and the RNG_DR register contents can be used.
00340   * @note   In the case of a seed error, the generation of random numbers is
00341   *         interrupted as long as the SECS bit is '1'. If a number is
00342   *         available in the RNG_DR register, it must not be used because it may
00343   *         not have enough entropy. In this case, it is recommended to clear the
00344   *         SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
00345   *         the RNG peripheral to reinitialize and restart the RNG.
00346   * @note   User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
00347   *         or CEIS are set.
00348   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00349   *                the configuration information for RNG.
00350   * @retval None
00351
00352   */
00353 void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
00354 {
00355   /* RNG clock error interrupt occurred */
00356   if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) ||  (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))
00357   {
00358     /* Change RNG peripheral state */
00359     hrng->State = HAL_RNG_STATE_ERROR;
00360
00361     HAL_RNG_ErrorCallback(hrng);
00362
00363     /* Clear the clock error flag */
00364     __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);
00365
00366   }
00367
00368   /* Check RNG data ready interrupt occurred */
00369   if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
00370   {
00371     /* Generate random number once, so disable the IT */
00372     __HAL_RNG_DISABLE_IT(hrng);
00373
00374     /* Get the 32bit Random number (DRDY flag automatically cleared) */
00375     hrng->RandomNumber = hrng->Instance->DR;
00376
00377     if(hrng->State != HAL_RNG_STATE_ERROR)
00378     {
00379       /* Change RNG peripheral state */
00380       hrng->State = HAL_RNG_STATE_READY;
00381
00382       /* Data Ready callback */
00383       HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
00384     }
00385   }
00386 }
00387
00388 /**
00389   * @brief  Read latest generated random number.
00390   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00391   *                the configuration information for RNG.
00392   * @retval random value
00393   */
00394 uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
00395 {
00396   return(hrng->RandomNumber);
00397 }
00398
00399 /**
00400   * @brief  Data Ready callback in non-blocking mode.
00401   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00402   *                the configuration information for RNG.
00403   * @param  random32bit: generated random number.
00404   * @retval None
00405   */
00406 __weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
00407 {
00408   /* Prevent unused argument(s) compilation warning */
00409   UNUSED(hrng);
00410   UNUSED(random32bit);
00411   /* NOTE : This function should not be modified. When the callback is needed,
00412             function HAL_RNG_ReadyDataCallback must be implemented in the user file.
00413    */
00414 }
00415
00416 /**
00417   * @brief  RNG error callbacks.
00418   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00419   *                the configuration information for RNG.
00420   * @retval None
00421   */
00422 __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
00423 {
00424   /* Prevent unused argument(s) compilation warning */
00425   UNUSED(hrng);
00426   /* NOTE : This function should not be modified. When the callback is needed,
00427             function HAL_RNG_ErrorCallback must be implemented in the user file.
00428    */
00429 }
00430 /**
00431   * @}
00432   */
00433
00434
00435 /** @addtogroup RNG_Exported_Functions_Group3
00436  *  @brief   Peripheral State functions
00437  *
00438 @verbatim
00439  ===============================================================================
00440                       ##### Peripheral State functions #####
00441  ===============================================================================
00442     [..]
00443     This subsection permits to get in run-time the status of the peripheral
00444     and the data flow.
00445
00446 @endverbatim
00447   * @{
00448   */
00449
00450 /**
00451   * @brief  Returns the RNG state.
00452   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00453   *                the configuration information for RNG.
00454   * @retval HAL state
00455   */
00456 HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
00457 {
00458   return hrng->State;
00459 }
00460
00461 /**
00462   * @}
00463   */
00464
00465 /**
00466   * @}
00467   */
00468
00469 #endif /* HAL_RNG_MODULE_ENABLED */
00470
00471 /**
00472   * @}
00473   */
00474
00475 /**
00476   * @}
00477   */
00478
00479 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_rng.h Source File

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stm32h7xx_hal_rng.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rng.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of RNG HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_RNG_H
00040 #define __STM32H7xx_HAL_RNG_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup RNG RNG
00054   * @brief RNG HAL module driver
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059
00060 /** @defgroup RNG_Exported_Types RNG Exported Types
00061   * @{
00062   */
00063
00064 /** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition
00065   * @{
00066   */
00067 typedef struct
00068 {
00069   uint32_t                    ClockErrorDetection; /*!< CED Clock error detection */
00070
00071 }RNG_InitTypeDef;
00072
00073 /** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition
00074   * @{
00075   */
00076 typedef enum
00077 {
00078   HAL_RNG_STATE_RESET     = 0x00U,  /*!< RNG not yet initialized or disabled */
00079   HAL_RNG_STATE_READY     = 0x01U,  /*!< RNG initialized and ready for use   */
00080   HAL_RNG_STATE_BUSY      = 0x02U,  /*!< RNG internal process is ongoing     */
00081   HAL_RNG_STATE_TIMEOUT   = 0x03U,  /*!< RNG timeout state                   */
00082   HAL_RNG_STATE_ERROR     = 0x04U   /*!< RNG error state                     */
00083
00084 }HAL_RNG_StateTypeDef;
00085
00086 /**
00087   * @}
00088   */
00089
00090 /** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
00091   * @{
00092   */
00093 typedef struct
00094 {
00095   RNG_TypeDef                 *Instance;    /*!< Register base address   */
00096
00097   RNG_InitTypeDef             Init;         /*!< RNG  parameters     */
00098
00099   HAL_LockTypeDef             Lock;         /*!< RNG locking object      */
00100
00101   __IO HAL_RNG_StateTypeDef   State;        /*!< RNG communication state */
00102
00103   uint32_t                    RandomNumber; /*!< Last Generated RNG Data */
00104
00105 }RNG_HandleTypeDef;
00106
00107 /**
00108   * @}
00109   */
00110
00111 /**
00112   * @}
00113   */
00114
00115 /* Exported constants --------------------------------------------------------*/
00116
00117 /** @defgroup RNG_Exported_Constants RNG Exported Constants
00118   * @{
00119   */
00120
00121 /** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
00122   * @{
00123   */
00124 #define RNG_IT_DRDY  RNG_SR_DRDY  /*!< Data Ready interrupt  */
00125 #define RNG_IT_CEI   RNG_SR_CEIS  /*!< Clock error interrupt */
00126 #define RNG_IT_SEI   RNG_SR_SEIS  /*!< Seed error interrupt  */
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
00132   * @{
00133   */
00134 #define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */
00135 #define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */
00136 #define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */
00137
00138 /**
00139   * @}
00140   */
00141
00142 /** @defgroup RNG_Exported_Constants_Group3 RNG Clock Error Detection
00143   * @{
00144   */
00145 #define RNG_CED_ENABLE         ((uint32_t)0x00000000) /*!< Clock error detection Enabled*/
00146 #define RNG_CED_DISABLE         RNG_CR_CED  /*!< Clock error detection Disabled*/
00147
00148 /**
00149   * @}
00150   */
00151
00152 /**
00153   * @}
00154   */
00155
00156 /* Exported macros -----------------------------------------------------------*/
00157
00158 /** @defgroup RNG_Exported_Macros RNG Exported Macros
00159   * @{
00160   */
00161
00162 /** @brief Reset RNG handle state
00163   * @param  __HANDLE__: RNG Handle
00164   * @retval None
00165   */
00166 #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
00167
00168 /**
00169   * @brief  Enables the RNG peripheral.
00170   * @param  __HANDLE__: RNG Handle
00171   * @retval None
00172   */
00173 #define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)
00174
00175 /**
00176   * @brief  Disables the RNG peripheral.
00177   * @param  __HANDLE__: RNG Handle
00178   * @retval None
00179   */
00180 #define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
00181
00182 /**
00183   * @brief  Check the selected RNG flag status.
00184   * @param  __HANDLE__: RNG Handle
00185   * @param  __FLAG__: RNG flag
00186   *          This parameter can be one of the following values:
00187   *            @arg RNG_FLAG_DRDY: Data ready
00188   *            @arg RNG_FLAG_CECS: Clock error current status
00189   *            @arg RNG_FLAG_SECS: Seed error current status
00190   * @retval The new state of __FLAG__ (SET or RESET).
00191   */
00192 #define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00193
00194 /**
00195   * @brief  Clears the selected RNG flag status.
00196   * @param  __HANDLE__: RNG handle
00197   * @param  __FLAG__: RNG flag to clear
00198   * @note   WARNING: This is a dummy macro for HAL code alignment,
00199   *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
00200   * @retval None
00201   */
00202 #define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__)                      /* dummy  macro */
00203
00204
00205
00206 /**
00207   * @brief  Enables the RNG interrupts.
00208   * @param  __HANDLE__: RNG Handle
00209   * @retval None
00210   */
00211 #define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)
00212
00213 /**
00214   * @brief  Disables the RNG interrupts.
00215   * @param  __HANDLE__: RNG Handle
00216   * @retval None
00217   */
00218 #define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
00219
00220 /**
00221   * @brief  Checks whether the specified RNG interrupt has occurred or not.
00222   * @param  __HANDLE__: RNG Handle
00223   * @param  __INTERRUPT__: specifies the RNG interrupt status flag to check.
00224   *         This parameter can be one of the following values:
00225   *            @arg RNG_IT_DRDY: Data ready interrupt
00226   *            @arg RNG_IT_CEI: Clock error interrupt
00227   *            @arg RNG_IT_SEI: Seed error interrupt
00228   * @retval The new state of __INTERRUPT__ (SET or RESET).
00229   */
00230 #define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
00231
00232 /**
00233   * @brief  Clear the RNG interrupt status flags.
00234   * @param  __HANDLE__: RNG Handle
00235   * @param  __INTERRUPT__: specifies the RNG interrupt status flag to clear.
00236   *          This parameter can be one of the following values:
00237   *            @arg RNG_IT_CEI: Clock error interrupt
00238   *            @arg RNG_IT_SEI: Seed error interrupt
00239   * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
00240   * @retval None
00241   */
00242 #define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
00243
00244 /**
00245   * @}
00246   */
00247
00248 /* Exported functions --------------------------------------------------------*/
00249 /** @defgroup RNG_Exported_Functions RNG Exported Functions
00250   * @{
00251   */
00252
00253 /** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
00254   * @{
00255   */
00256 HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
00257 HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
00258 void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
00259 void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
00260
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
00266   * @{
00267   */
00268
00269 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
00270 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
00271 uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
00272
00273 void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
00274 void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
00275 void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
00276
00277 /**
00278   * @}
00279   */
00280
00281 /** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
00282   * @{
00283   */
00284 HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
00285
00286 /**
00287   * @}
00288   */
00289
00290 /**
00291   * @}
00292   */
00293
00294 /* Private types -------------------------------------------------------------*/
00295 /** @defgroup RNG_Private_Types RNG Private Types
00296   * @{
00297   */
00298
00299 /**
00300   * @}
00301   */
00302
00303 /* Private defines -----------------------------------------------------------*/
00304 /** @defgroup RNG_Private_Defines RNG Private Defines
00305   * @{
00306   */
00307
00308 /**
00309   * @}
00310   */
00311
00312 /* Private variables ---------------------------------------------------------*/
00313 /** @defgroup RNG_Private_Variables RNG Private Variables
00314   * @{
00315   */
00316
00317 /**
00318   * @}
00319   */
00320
00321 /* Private constants ---------------------------------------------------------*/
00322 /** @defgroup RNG_Private_Constants RNG Private Constants
00323   * @{
00324   */
00325
00326 /**
00327   * @}
00328   */
00329
00330 /* Private macros ------------------------------------------------------------*/
00331 /** @defgroup RNG_Private_Macros RNG Private Macros
00332   * @{
00333   */
00334 #define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
00335                        ((IT) == RNG_IT_SEI))
00336
00337 #define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
00338                            ((FLAG) == RNG_FLAG_CECS) || \
00339                            ((FLAG) == RNG_FLAG_SECS))
00340
00341 #define IS_RNG_CED(CED)   (((CED) == RNG_CED_ENABLE) || \
00342                            ((CED) == RNG_CED_DISABLE))
00343 /**
00344   * @}
00345   */
00346
00347 /* Private functions prototypes ----------------------------------------------*/
00348 /** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes
00349   * @{
00350   */
00351
00352 /**
00353   * @}
00354   */
00355
00356 /* Private functions ---------------------------------------------------------*/
00357 /** @defgroup RNG_Private_Functions RNG Private Functions
00358   * @{
00359   */
00360
00361 /**
00362   * @}
00363   */
00364
00365 /**
00366   * @}
00367   */
00368
00369 /**
00370   * @}
00371   */
00372
00373 /**
00374   * @}
00375   */
00376 #ifdef __cplusplus
00377 }
00378 #endif
00379
00380
00381 #endif /* __STM32H7xx_HAL_RNG_H */
00382
00383 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_rtc.c Source File

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stm32h7xx_hal_rtc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rtc.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   RTC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Real-Time Clock (RTC) peripheral:
00010   *           + Initialization
00011   *           + Calendar (Time and Date) configuration
00012   *           + Alarms (Alarm A and Alarm B) configuration
00013   *           + WakeUp Timer configuration
00014   *           + TimeStamp configuration
00015   *           + Tampers configuration
00016   *           + Backup Data Registers configuration
00017   *           + RTC Tamper and TimeStamp Pins Selection
00018   *           + Interrupts and flags management
00019   *
00020   @verbatim
00021  ===============================================================================
00022                           ##### RTC Operating Condition #####
00023  ===============================================================================
00024   [..] The real-time clock (RTC) and the RTC backup registers can be powered
00025        from the VBAT voltage when the main VDD supply is powered off.
00026        To retain the content of the RTC backup registers and supply the RTC
00027        when VDD is turned off, VBAT pin can be connected to an optional
00028        standby voltage supplied by a battery or by another source.
00029
00030                    ##### Backup Domain Reset #####
00031  ===============================================================================
00032   [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
00033        to their reset values.
00034        A backup domain reset is generated when one of the following events occurs:
00035     (#) Software reset, triggered by setting the BDRST bit in the
00036         RCC Backup domain control register (RCC_BDCR).
00037     (#) VDD or VBAT power on, if both supplies have previously been powered off.
00038     (#) Tamper detection event resets all data backup registers.
00039
00040                    ##### Backup Domain Access #####
00041  ===================================================================
00042   [..] After reset, the backup domain (RTC registers, RTC backup data
00043        registers and backup SRAM) is protected against possible unwanted write
00044        accesses.
00045
00046   [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
00047     (#) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for
00048         PeriphClockSelection and select RTCClockSelection (LSE, LSI or any HSE divider)
00049     (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro.
00050
00051                   ##### How to use RTC Driver #####
00052  ===================================================================
00053   [..]
00054     (#) Enable the RTC domain access (see description in the section above).
00055     (#) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
00056         format using the HAL_RTC_Init() function.
00057
00058   *** Time and Date configuration ***
00059   ===================================
00060   [..]
00061     (#) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
00062         and HAL_RTC_SetDate() functions.
00063     (#) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
00064
00065   *** Alarm configuration ***
00066   ===========================
00067   [..]
00068     (#) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
00069             You can also configure the RTC Alarm with interrupt mode using the
00070             HAL_RTC_SetAlarm_IT() function.
00071     (#) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
00072
00073                   ##### RTC and low power modes #####
00074  ===================================================================
00075   [..] The MCU can be woken up from a low power mode by an RTC alternate
00076        function.
00077   [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
00078        RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
00079        These RTC alternate functions can wake up the system from the Stop and Standby low power
00080        modes.
00081   [..] The system can also wake up from low power modes without depending
00082        on an external interrupt (Auto-wakeup mode), by using the RTC alarm
00083        or the RTC wakeup events.
00084   [..] The RTC provides a programmable time base for waking up from the
00085        Stop or Standby mode at regular intervals.
00086        Wakeup from STOP and Standby modes is possible only when the RTC clock source
00087        is LSE or LSI.
00088
00089    @endverbatim
00090
00091   ******************************************************************************
00092   * @attention
00093   *
00094   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00095   *
00096   * Redistribution and use in source and binary forms, with or without modification,
00097   * are permitted provided that the following conditions are met:
00098   *   1. Redistributions of source code must retain the above copyright notice,
00099   *      this list of conditions and the following disclaimer.
00100   *   2. Redistributions in binary form must reproduce the above copyright notice,
00101   *      this list of conditions and the following disclaimer in the documentation
00102   *      and/or other materials provided with the distribution.
00103   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00104   *      may be used to endorse or promote products derived from this software
00105   *      without specific prior written permission.
00106   *
00107   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00108   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00109   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00110   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00111   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00112   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00113   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00114   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00115   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00116   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00117   *
00118   ******************************************************************************
00119   */
00120
00121 /* Includes ------------------------------------------------------------------*/
00122 #include "stm32h7xx_hal.h"
00123
00124 /** @addtogroup STM32H7xx_HAL_Driver
00125   * @{
00126   */
00127
00128 /** @defgroup RTC RTC
00129   * @brief RTC HAL module driver
00130   * @{
00131   */
00132
00133 #ifdef HAL_RTC_MODULE_ENABLED
00134
00135 /* Private typedef -----------------------------------------------------------*/
00136 /* Private define ------------------------------------------------------------*/
00137 /* Private macro -------------------------------------------------------------*/
00138 /* Private variables ---------------------------------------------------------*/
00139 /* Private function prototypes -----------------------------------------------*/
00140 /* Exported functions --------------------------------------------------------*/
00141
00142 /** @defgroup RTC_Exported_Functions RTC Exported Functions
00143   * @{
00144   */
00145
00146 /** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
00147  *  @brief    Initialization and Configuration functions
00148  *
00149 @verbatim
00150  ===============================================================================
00151               ##### Initialization and de-initialization functions #####
00152  ===============================================================================
00153    [..] This section provide functions allowing to initialize and configure the
00154          RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
00155          RTC registers Write protection, enter and exit the RTC initialization mode,
00156          RTC registers synchronization check and reference clock detection enable.
00157          (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
00158              It is split into 2 programmable prescalers to minimize power consumption.
00159              (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
00160              (++) When both prescalers are used, it is recommended to configure the
00161                  asynchronous prescaler to a high value to minimize power consumption.
00162          (#) All RTC registers are Write protected. Writing to the RTC registers
00163              is enabled by writing a key into the Write Protection register, RTC_WPR.
00164          (#) To configure the RTC Calendar, user application should enter
00165              initialization mode. In this mode, the calendar counter is stopped
00166              and its value can be updated. When the initialization sequence is
00167              complete, the calendar restarts counting after 4 RTCCLK cycles.
00168          (#) To read the calendar through the shadow registers after Calendar
00169              initialization, calendar update or after wakeup from low power modes
00170              the software must first clear the RSF flag. The software must then
00171              wait until it is set again before reading the calendar, which means
00172              that the calendar registers have been correctly copied into the
00173              RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
00174              implements the above software sequence (RSF clear and RSF check).
00175
00176 @endverbatim
00177   * @{
00178   */
00179
00180 /**
00181   * @brief  Initialize the RTC according to the specified parameters
00182   *         in the RTC_InitTypeDef structure and initialize the associated handle.
00183   * @param  hrtc: RTC handle
00184   * @retval HAL status
00185   */
00186 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
00187 {
00188   /* Check the RTC peripheral state */
00189   if(hrtc == NULL)
00190   {
00191      return HAL_ERROR;
00192   }
00193
00194   /* Check the parameters */
00195   assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
00196   assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
00197   assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
00198   assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
00199   assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
00200   assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap));
00201   assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
00202   assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
00203
00204   if(hrtc->State == HAL_RTC_STATE_RESET)
00205   {
00206     /* Allocate lock resource and initialize it */
00207     hrtc->Lock = HAL_UNLOCKED;
00208     /* Initialize RTC MSP */
00209     HAL_RTC_MspInit(hrtc);
00210   }
00211
00212   /* Set RTC state */
00213   hrtc->State = HAL_RTC_STATE_BUSY;
00214
00215   /* Disable the write protection for RTC registers */
00216   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00217
00218   /* Set Initialization mode */
00219   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00220   {
00221     /* Enable the write protection for RTC registers */
00222     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00223
00224     /* Set RTC state */
00225     hrtc->State = HAL_RTC_STATE_ERROR;
00226
00227     return HAL_ERROR;
00228   }
00229   else
00230   {
00231     /* Clear RTC_CR FMT, OSEL and POL Bits */
00232     hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
00233     /* Set RTC_CR register */
00234     hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
00235
00236     /* Configure the RTC PRER */
00237     hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
00238     hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);
00239
00240     /* Exit Initialization mode */
00241     hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
00242
00243     hrtc->Instance->OR &= (uint32_t)~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP);
00244     hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
00245
00246     /* Enable the write protection for RTC registers */
00247     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00248
00249     /* Set RTC state */
00250     hrtc->State = HAL_RTC_STATE_READY;
00251
00252     return HAL_OK;
00253   }
00254 }
00255
00256 /**
00257   * @brief  DeInitialize the RTC peripheral.
00258   * @param  hrtc: RTC handle
00259   * @note   This function doesn't reset the RTC Backup Data registers.
00260   * @retval HAL status
00261   */
00262 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
00263 {
00264   uint32_t tickstart = 0;
00265
00266   /* Check the parameters */
00267   assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
00268
00269   /* Set RTC state */
00270   hrtc->State = HAL_RTC_STATE_BUSY;
00271
00272   /* Disable the write protection for RTC registers */
00273   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00274
00275   /* Set Initialization mode */
00276   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00277   {
00278     /* Enable the write protection for RTC registers */
00279     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00280
00281     /* Set RTC state */
00282     hrtc->State = HAL_RTC_STATE_ERROR;
00283
00284     return HAL_ERROR;
00285   }
00286   else
00287   {
00288     /* Reset TR, DR and CR registers */
00289     hrtc->Instance->TR = (uint32_t)0x00000000;
00290     hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
00291     /* Reset All CR bits except CR[2:0] */
00292     hrtc->Instance->CR &= RTC_CR_WUCKSEL;
00293
00294     tickstart = HAL_GetTick();
00295
00296     /* Wait till WUTWF flag is set and if Time out is reached exit */
00297     while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
00298     {
00299       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00300       {
00301         /* Enable the write protection for RTC registers */
00302         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00303
00304         /* Set RTC state */
00305         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00306
00307         return HAL_TIMEOUT;
00308       }
00309     }
00310
00311     /* Reset all RTC CR register bits */
00312     hrtc->Instance->CR &= (uint32_t)0x00000000;
00313     hrtc->Instance->WUTR = RTC_WUTR_WUT;
00314     hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FF));
00315     hrtc->Instance->ALRMAR = (uint32_t)0x00000000;
00316     hrtc->Instance->ALRMBR = (uint32_t)0x00000000;
00317     hrtc->Instance->SHIFTR = (uint32_t)0x00000000;
00318     hrtc->Instance->CALR = (uint32_t)0x00000000;
00319     hrtc->Instance->ALRMASSR = (uint32_t)0x00000000;
00320     hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000;
00321
00322     /* Reset ISR register and exit initialization mode */
00323     hrtc->Instance->ISR = (uint32_t)0x00000000;
00324
00325     /* Reset Tamper configuration register */
00326     hrtc->Instance->TAMPCR = 0x00000000;
00327
00328     /* Reset Option register */
00329     hrtc->Instance->OR = 0x00000000;
00330
00331     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00332     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
00333     {
00334       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00335       {
00336         /* Enable the write protection for RTC registers */
00337         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00338
00339         hrtc->State = HAL_RTC_STATE_ERROR;
00340
00341         return HAL_ERROR;
00342       }
00343     }
00344   }
00345
00346   /* Enable the write protection for RTC registers */
00347   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00348
00349   /* De-Initialize RTC MSP */
00350   HAL_RTC_MspDeInit(hrtc);
00351
00352   hrtc->State = HAL_RTC_STATE_RESET;
00353
00354   /* Release Lock */
00355   __HAL_UNLOCK(hrtc);
00356
00357   return HAL_OK;
00358 }
00359
00360 /**
00361   * @brief  Initialize the RTC MSP.
00362   * @param  hrtc: RTC handle
00363   * @retval None
00364   */
00365 __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
00366 {
00367   /* Prevent unused argument(s) compilation warning */
00368   UNUSED(hrtc);
00369
00370   /* NOTE : This function should not be modified, when the callback is needed,
00371             the HAL_RTC_MspInit could be implemented in the user file
00372    */
00373 }
00374
00375 /**
00376   * @brief  DeInitialize the RTC MSP.
00377   * @param  hrtc: RTC handle
00378   * @retval None
00379   */
00380 __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
00381 {
00382   /* Prevent unused argument(s) compilation warning */
00383   UNUSED(hrtc);
00384
00385   /* NOTE : This function should not be modified, when the callback is needed,
00386             the HAL_RTC_MspDeInit could be implemented in the user file
00387    */
00388 }
00389
00390 /**
00391   * @}
00392   */
00393
00394 /** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
00395  *  @brief   RTC Time and Date functions
00396  *
00397 @verbatim
00398  ===============================================================================
00399                  ##### RTC Time and Date functions #####
00400  ===============================================================================
00401
00402  [..] This section provides functions allowing to configure Time and Date features
00403
00404 @endverbatim
00405   * @{
00406   */
00407
00408 /**
00409   * @brief  Set RTC current time.
00410   * @param  hrtc: RTC handle
00411   * @param  sTime: Pointer to Time structure
00412   * @param  Format: Specifies the format of the entered parameters.
00413   *          This parameter can be one of the following values:
00414   *            @arg RTC_FORMAT_BIN: Binary data format
00415   *            @arg RTC_FORMAT_BCD: BCD data format
00416   * @retval HAL status
00417   */
00418 HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
00419 {
00420   uint32_t tmpreg = 0;
00421
00422  /* Check the parameters */
00423   assert_param(IS_RTC_FORMAT(Format));
00424   assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
00425   assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
00426
00427   /* Process Locked */
00428   __HAL_LOCK(hrtc);
00429
00430   hrtc->State = HAL_RTC_STATE_BUSY;
00431
00432   if(Format == RTC_FORMAT_BIN)
00433   {
00434     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00435     {
00436       assert_param(IS_RTC_HOUR12(sTime->Hours));
00437       assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
00438     }
00439     else
00440     {
00441       sTime->TimeFormat = 0x00;
00442       assert_param(IS_RTC_HOUR24(sTime->Hours));
00443     }
00444     assert_param(IS_RTC_MINUTES(sTime->Minutes));
00445     assert_param(IS_RTC_SECONDS(sTime->Seconds));
00446
00447     tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \
00448                         ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \
00449                         ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
00450                         (((uint32_t)sTime->TimeFormat) << 16));
00451   }
00452   else
00453   {
00454     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00455     {
00456       tmpreg = RTC_Bcd2ToByte(sTime->Hours);
00457       assert_param(IS_RTC_HOUR12(tmpreg));
00458       assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
00459     }
00460     else
00461     {
00462       sTime->TimeFormat = 0x00;
00463       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
00464     }
00465     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
00466     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
00467     tmpreg = (((uint32_t)(sTime->Hours) << 16) | \
00468               ((uint32_t)(sTime->Minutes) << 8) | \
00469               ((uint32_t)sTime->Seconds) | \
00470               ((uint32_t)(sTime->TimeFormat) << 16));
00471   }
00472
00473   /* Disable the write protection for RTC registers */
00474   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00475
00476   /* Set Initialization mode */
00477   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00478   {
00479     /* Enable the write protection for RTC registers */
00480     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00481
00482     /* Set RTC state */
00483     hrtc->State = HAL_RTC_STATE_ERROR;
00484
00485     /* Process Unlocked */
00486     __HAL_UNLOCK(hrtc);
00487
00488     return HAL_ERROR;
00489   }
00490   else
00491   {
00492     /* Set the RTC_TR register */
00493     hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
00494
00495     /* Clear the bits to be configured */
00496     hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK);
00497
00498     /* Configure the RTC_CR register */
00499     hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
00500
00501     /* Exit Initialization mode */
00502     hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
00503
00504     /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00505     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
00506     {
00507       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00508       {
00509         /* Enable the write protection for RTC registers */
00510         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00511
00512         hrtc->State = HAL_RTC_STATE_ERROR;
00513
00514         /* Process Unlocked */
00515         __HAL_UNLOCK(hrtc);
00516
00517         return HAL_ERROR;
00518       }
00519     }
00520
00521     /* Enable the write protection for RTC registers */
00522     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00523
00524    hrtc->State = HAL_RTC_STATE_READY;
00525
00526    __HAL_UNLOCK(hrtc);
00527
00528    return HAL_OK;
00529   }
00530 }
00531
00532 /**
00533   * @brief  Get RTC current time.
00534   * @param  hrtc: RTC handle
00535   * @param  sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned
00536   *                with input format (BIN or BCD), also SubSeconds field returning the
00537   *                RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
00538   *                factor to be used for second fraction ratio computation.
00539   * @param  Format: Specifies the format of the entered parameters.
00540   *          This parameter can be one of the following values:
00541   *            @arg RTC_FORMAT_BIN: Binary data format
00542   *            @arg RTC_FORMAT_BCD: BCD data format
00543   * @note  You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
00544   *        value in second fraction ratio with time unit following generic formula:
00545   *        Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
00546   *        This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
00547   * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
00548   *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
00549   *        Reading RTC current time locks the values in calendar shadow registers until Current date is read
00550   *        to ensure consistency between the time and date values.
00551   * @retval HAL status
00552   */
00553 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
00554 {
00555   uint32_t tmpreg = 0;
00556
00557   /* Check the parameters */
00558   assert_param(IS_RTC_FORMAT(Format));
00559
00560    /* Get subseconds structure field from the corresponding register*/
00561   sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
00562
00563   /* Get SecondFraction structure field from the corresponding register field*/
00564   sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
00565
00566   /* Get the TR register */
00567   tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
00568
00569   /* Fill the structure fields with the read parameters */
00570   sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
00571   sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
00572   sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
00573   sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
00574
00575   /* Check the input parameters format */
00576   if(Format == RTC_FORMAT_BIN)
00577   {
00578     /* Convert the time structure parameters to Binary format */
00579     sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
00580     sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
00581     sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
00582   }
00583
00584   return HAL_OK;
00585 }
00586
00587 /**
00588   * @brief  Set RTC current date.
00589   * @param  hrtc: RTC handle
00590   * @param  sDate: Pointer to date structure
00591   * @param  Format: specifies the format of the entered parameters.
00592   *          This parameter can be one of the following values:
00593   *            @arg RTC_FORMAT_BIN: Binary data format
00594   *            @arg RTC_FORMAT_BCD: BCD data format
00595   * @retval HAL status
00596   */
00597 HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
00598 {
00599   uint32_t datetmpreg = 0;
00600
00601  /* Check the parameters */
00602   assert_param(IS_RTC_FORMAT(Format));
00603
00604  /* Process Locked */
00605  __HAL_LOCK(hrtc);
00606
00607   hrtc->State = HAL_RTC_STATE_BUSY;
00608
00609   if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
00610   {
00611     sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
00612   }
00613
00614   assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
00615
00616   if(Format == RTC_FORMAT_BIN)
00617   {
00618     assert_param(IS_RTC_YEAR(sDate->Year));
00619     assert_param(IS_RTC_MONTH(sDate->Month));
00620     assert_param(IS_RTC_DATE(sDate->Date));
00621
00622    datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \
00623                  ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \
00624                  ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
00625                  ((uint32_t)sDate->WeekDay << 13));
00626   }
00627   else
00628   {
00629     assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
00630     datetmpreg = RTC_Bcd2ToByte(sDate->Month);
00631     assert_param(IS_RTC_MONTH(datetmpreg));
00632     datetmpreg = RTC_Bcd2ToByte(sDate->Date);
00633     assert_param(IS_RTC_DATE(datetmpreg));
00634
00635     datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
00636                   (((uint32_t)sDate->Month) << 8) | \
00637                   ((uint32_t)sDate->Date) | \
00638                   (((uint32_t)sDate->WeekDay) << 13));
00639   }
00640
00641   /* Disable the write protection for RTC registers */
00642   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00643
00644   /* Set Initialization mode */
00645   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00646   {
00647     /* Enable the write protection for RTC registers */
00648     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00649
00650     /* Set RTC state*/
00651     hrtc->State = HAL_RTC_STATE_ERROR;
00652
00653     /* Process Unlocked */
00654     __HAL_UNLOCK(hrtc);
00655
00656     return HAL_ERROR;
00657   }
00658   else
00659   {
00660     /* Set the RTC_DR register */
00661     hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
00662
00663     /* Exit Initialization mode */
00664     hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
00665
00666     /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00667     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
00668     {
00669       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00670       {
00671         /* Enable the write protection for RTC registers */
00672         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00673
00674         hrtc->State = HAL_RTC_STATE_ERROR;
00675
00676         /* Process Unlocked */
00677         __HAL_UNLOCK(hrtc);
00678
00679         return HAL_ERROR;
00680       }
00681     }
00682
00683     /* Enable the write protection for RTC registers */
00684     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00685
00686     hrtc->State = HAL_RTC_STATE_READY ;
00687
00688     /* Process Unlocked */
00689     __HAL_UNLOCK(hrtc);
00690
00691     return HAL_OK;
00692   }
00693 }
00694
00695 /**
00696   * @brief  Get RTC current date.
00697   * @param  hrtc: RTC handle
00698   * @param  sDate: Pointer to Date structure
00699   * @param  Format: Specifies the format of the entered parameters.
00700   *          This parameter can be one of the following values:
00701   *            @arg RTC_FORMAT_BIN:  Binary data format
00702   *            @arg RTC_FORMAT_BCD:  BCD data format
00703   * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
00704   *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
00705   *        Reading RTC current time locks the values in calendar shadow registers until Current date is read.
00706   * @retval HAL status
00707   */
00708 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
00709 {
00710   uint32_t datetmpreg = 0;
00711
00712   /* Check the parameters */
00713   assert_param(IS_RTC_FORMAT(Format));
00714
00715   /* Get the DR register */
00716   datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
00717
00718   /* Fill the structure fields with the read parameters */
00719   sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
00720   sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
00721   sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
00722   sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13);
00723
00724   /* Check the input parameters format */
00725   if(Format == RTC_FORMAT_BIN)
00726   {
00727     /* Convert the date structure parameters to Binary format */
00728     sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
00729     sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
00730     sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
00731   }
00732   return HAL_OK;
00733 }
00734
00735 /**
00736   * @}
00737   */
00738
00739 /** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
00740  *  @brief   RTC Alarm functions
00741  *
00742 @verbatim
00743  ===============================================================================
00744                  ##### RTC Alarm functions #####
00745  ===============================================================================
00746
00747  [..] This section provides functions allowing to configure Alarm feature
00748
00749 @endverbatim
00750   * @{
00751   */
00752 /**
00753   * @brief  Set the specified RTC Alarm.
00754   * @param  hrtc: RTC handle
00755   * @param  sAlarm: Pointer to Alarm structure
00756   * @param  Format: Specifies the format of the entered parameters.
00757   *          This parameter can be one of the following values:
00758   *             @arg RTC_FORMAT_BIN: Binary data format
00759   *             @arg RTC_FORMAT_BCD: BCD data format
00760   * @retval HAL status
00761   */
00762 HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
00763 {
00764   uint32_t tickstart = 0;
00765   uint32_t tmpreg = 0, subsecondtmpreg = 0;
00766
00767   /* Check the parameters */
00768   assert_param(IS_RTC_FORMAT(Format));
00769   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
00770   assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
00771   assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
00772   assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
00773   assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
00774
00775   /* Process Locked */
00776   __HAL_LOCK(hrtc);
00777
00778   hrtc->State = HAL_RTC_STATE_BUSY;
00779
00780   if(Format == RTC_FORMAT_BIN)
00781   {
00782     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00783     {
00784       assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
00785       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
00786     }
00787     else
00788     {
00789       sAlarm->AlarmTime.TimeFormat = 0x00;
00790       assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
00791     }
00792     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
00793     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
00794
00795     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
00796     {
00797       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
00798     }
00799     else
00800     {
00801       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
00802     }
00803
00804     tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
00805               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
00806               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
00807               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
00808               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
00809               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
00810               ((uint32_t)sAlarm->AlarmMask));
00811   }
00812   else
00813   {
00814     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00815     {
00816       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
00817       assert_param(IS_RTC_HOUR12(tmpreg));
00818       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
00819     }
00820     else
00821     {
00822       sAlarm->AlarmTime.TimeFormat = 0x00;
00823       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
00824     }
00825
00826     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
00827     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
00828
00829     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
00830     {
00831       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
00832       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
00833     }
00834     else
00835     {
00836       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
00837       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
00838     }
00839
00840     tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
00841               ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
00842               ((uint32_t) sAlarm->AlarmTime.Seconds) | \
00843               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
00844               ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
00845               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
00846               ((uint32_t)sAlarm->AlarmMask));
00847   }
00848
00849   /* Configure the Alarm A or Alarm B Sub Second registers */
00850   subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
00851
00852   /* Disable the write protection for RTC registers */
00853   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00854
00855   /* Configure the Alarm register */
00856   if(sAlarm->Alarm == RTC_ALARM_A)
00857   {
00858     /* Disable the Alarm A interrupt */
00859     __HAL_RTC_ALARMA_DISABLE(hrtc);
00860
00861     /* In case of interrupt mode is used, the interrupt source must disabled */
00862     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
00863
00864     tickstart = HAL_GetTick();
00865     /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
00866     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
00867     {
00868       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00869       {
00870         /* Enable the write protection for RTC registers */
00871         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00872
00873         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00874
00875         /* Process Unlocked */
00876         __HAL_UNLOCK(hrtc);
00877
00878         return HAL_TIMEOUT;
00879       }
00880     }
00881
00882     hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
00883     /* Configure the Alarm A Sub Second register */
00884     hrtc->Instance->ALRMASSR = subsecondtmpreg;
00885     /* Configure the Alarm state: Enable Alarm */
00886     __HAL_RTC_ALARMA_ENABLE(hrtc);
00887   }
00888   else
00889   {
00890     /* Disable the Alarm B interrupt */
00891     __HAL_RTC_ALARMB_DISABLE(hrtc);
00892
00893     /* In case of interrupt mode is used, the interrupt source must disabled */
00894     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
00895
00896     tickstart = HAL_GetTick();
00897     /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
00898     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
00899     {
00900       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00901       {
00902         /* Enable the write protection for RTC registers */
00903         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00904
00905         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00906
00907         /* Process Unlocked */
00908         __HAL_UNLOCK(hrtc);
00909
00910         return HAL_TIMEOUT;
00911       }
00912     }
00913
00914     hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
00915     /* Configure the Alarm B Sub Second register */
00916     hrtc->Instance->ALRMBSSR = subsecondtmpreg;
00917     /* Configure the Alarm state: Enable Alarm */
00918     __HAL_RTC_ALARMB_ENABLE(hrtc);
00919   }
00920
00921   /* Enable the write protection for RTC registers */
00922   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00923
00924   /* Change RTC state */
00925   hrtc->State = HAL_RTC_STATE_READY;
00926
00927   /* Process Unlocked */
00928   __HAL_UNLOCK(hrtc);
00929
00930   return HAL_OK;
00931 }
00932
00933 /**
00934   * @brief  Set the specified RTC Alarm with Interrupt.
00935   * @param  hrtc: RTC handle
00936   * @param  sAlarm: Pointer to Alarm structure
00937   * @param  Format: Specifies the format of the entered parameters.
00938   *          This parameter can be one of the following values:
00939   *             @arg RTC_FORMAT_BIN: Binary data format
00940   *             @arg RTC_FORMAT_BCD: BCD data format
00941   * @note   The Alarm register can only be written when the corresponding Alarm
00942   *         is disabled (Use the HAL_RTC_DeactivateAlarm()).
00943   * @note   The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
00944   * @retval HAL status
00945   */
00946 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
00947 {
00948   uint32_t tickstart = 0;
00949   uint32_t tmpreg = 0, subsecondtmpreg = 0;
00950
00951   /* Check the parameters */
00952   assert_param(IS_RTC_FORMAT(Format));
00953   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
00954   assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
00955   assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
00956   assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
00957   assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
00958
00959   /* Process Locked */
00960   __HAL_LOCK(hrtc);
00961
00962   hrtc->State = HAL_RTC_STATE_BUSY;
00963
00964   if(Format == RTC_FORMAT_BIN)
00965   {
00966     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00967     {
00968       assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
00969       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
00970     }
00971     else
00972     {
00973       sAlarm->AlarmTime.TimeFormat = 0x00;
00974       assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
00975     }
00976     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
00977     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
00978
00979     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
00980     {
00981       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
00982     }
00983     else
00984     {
00985       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
00986     }
00987     tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
00988               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
00989               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
00990               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
00991               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
00992               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
00993               ((uint32_t)sAlarm->AlarmMask));
00994   }
00995   else
00996   {
00997     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00998     {
00999       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
01000       assert_param(IS_RTC_HOUR12(tmpreg));
01001       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01002     }
01003     else
01004     {
01005       sAlarm->AlarmTime.TimeFormat = 0x00;
01006       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01007     }
01008
01009     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
01010     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
01011
01012     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01013     {
01014       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
01015       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
01016     }
01017     else
01018     {
01019       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
01020       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
01021     }
01022     tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
01023               ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
01024               ((uint32_t) sAlarm->AlarmTime.Seconds) | \
01025               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
01026               ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
01027               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
01028               ((uint32_t)sAlarm->AlarmMask));
01029   }
01030   /* Configure the Alarm A or Alarm B Sub Second registers */
01031   subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
01032
01033   /* Disable the write protection for RTC registers */
01034   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01035
01036   /* Configure the Alarm register */
01037   if(sAlarm->Alarm == RTC_ALARM_A)
01038   {
01039     /* Disable the Alarm A interrupt */
01040     __HAL_RTC_ALARMA_DISABLE(hrtc);
01041
01042     /* Clear flag alarm A */
01043     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01044
01045     tickstart = HAL_GetTick();
01046     /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
01047     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
01048     {
01049       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01050       {
01051         /* Enable the write protection for RTC registers */
01052         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01053
01054         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01055
01056         /* Process Unlocked */
01057         __HAL_UNLOCK(hrtc);
01058
01059         return HAL_TIMEOUT;
01060       }
01061     }
01062
01063     hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
01064     /* Configure the Alarm A Sub Second register */
01065     hrtc->Instance->ALRMASSR = subsecondtmpreg;
01066     /* Configure the Alarm state: Enable Alarm */
01067     __HAL_RTC_ALARMA_ENABLE(hrtc);
01068     /* Configure the Alarm interrupt */
01069     __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
01070   }
01071   else
01072   {
01073     /* Disable the Alarm B interrupt */
01074     __HAL_RTC_ALARMB_DISABLE(hrtc);
01075
01076     /* Clear flag alarm B */
01077     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
01078
01079     tickstart = HAL_GetTick();
01080     /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
01081     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
01082     {
01083       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01084       {
01085         /* Enable the write protection for RTC registers */
01086         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01087
01088         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01089
01090         /* Process Unlocked */
01091         __HAL_UNLOCK(hrtc);
01092
01093         return HAL_TIMEOUT;
01094       }
01095     }
01096
01097     hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
01098     /* Configure the Alarm B Sub Second register */
01099     hrtc->Instance->ALRMBSSR = subsecondtmpreg;
01100     /* Configure the Alarm state: Enable Alarm */
01101     __HAL_RTC_ALARMB_ENABLE(hrtc);
01102     /* Configure the Alarm interrupt */
01103     __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
01104   }
01105
01106   /* RTC Alarm Interrupt Configuration: EXTI configuration */
01107      __HAL_RTC_ALARM_EXTI_ENABLE_IT();
01108
01109
01110   __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
01111   /*  Enable the write protection for RTC registers */
01112   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01113
01114   hrtc->State = HAL_RTC_STATE_READY;
01115
01116   /* Process Unlocked */
01117   __HAL_UNLOCK(hrtc);
01118
01119   return HAL_OK;
01120 }
01121
01122 /**
01123   * @brief  Deactivate the specified RTC Alarm.
01124   * @param  hrtc: RTC handle
01125   * @param  Alarm: Specifies the Alarm.
01126   *          This parameter can be one of the following values:
01127   *            @arg RTC_ALARM_A:  AlarmA
01128   *            @arg RTC_ALARM_B:  AlarmB
01129   * @retval HAL status
01130   */
01131 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
01132 {
01133   uint32_t tickstart = 0;
01134
01135   /* Check the parameters */
01136   assert_param(IS_RTC_ALARM(Alarm));
01137
01138   /* Process Locked */
01139   __HAL_LOCK(hrtc);
01140
01141   hrtc->State = HAL_RTC_STATE_BUSY;
01142
01143   /* Disable the write protection for RTC registers */
01144   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01145
01146   if(Alarm == RTC_ALARM_A)
01147   {
01148     /* AlarmA */
01149     __HAL_RTC_ALARMA_DISABLE(hrtc);
01150
01151     /* In case of interrupt mode is used, the interrupt source must disabled */
01152     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
01153
01154     tickstart = HAL_GetTick();
01155
01156     /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
01157     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
01158     {
01159       if( (HAL_GetTick()  - tickstart ) > RTC_TIMEOUT_VALUE)
01160       {
01161         /* Enable the write protection for RTC registers */
01162         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01163
01164         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01165
01166         /* Process Unlocked */
01167         __HAL_UNLOCK(hrtc);
01168
01169         return HAL_TIMEOUT;
01170       }
01171     }
01172   }
01173   else
01174   {
01175     /* AlarmB */
01176     __HAL_RTC_ALARMB_DISABLE(hrtc);
01177
01178     /* In case of interrupt mode is used, the interrupt source must disabled */
01179     __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);
01180
01181     tickstart = HAL_GetTick();
01182
01183     /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
01184     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
01185     {
01186       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01187       {
01188         /* Enable the write protection for RTC registers */
01189         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01190
01191         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01192
01193         /* Process Unlocked */
01194         __HAL_UNLOCK(hrtc);
01195
01196         return HAL_TIMEOUT;
01197       }
01198     }
01199   }
01200   /* Enable the write protection for RTC registers */
01201   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01202
01203   hrtc->State = HAL_RTC_STATE_READY;
01204
01205   /* Process Unlocked */
01206   __HAL_UNLOCK(hrtc);
01207
01208   return HAL_OK;
01209 }
01210
01211 /**
01212   * @brief  Get the RTC Alarm value and masks.
01213   * @param  hrtc: RTC handle
01214   * @param  sAlarm: Pointer to Date structure
01215   * @param  Alarm: Specifies the Alarm.
01216   *          This parameter can be one of the following values:
01217   *             @arg RTC_ALARM_A: AlarmA
01218   *             @arg RTC_ALARM_B: AlarmB
01219   * @param  Format: Specifies the format of the entered parameters.
01220   *          This parameter can be one of the following values:
01221   *             @arg RTC_FORMAT_BIN: Binary data format
01222   *             @arg RTC_FORMAT_BCD: BCD data format
01223   * @retval HAL status
01224   */
01225 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
01226 {
01227   uint32_t tmpreg = 0, subsecondtmpreg = 0;
01228
01229   /* Check the parameters */
01230   assert_param(IS_RTC_FORMAT(Format));
01231   assert_param(IS_RTC_ALARM(Alarm));
01232
01233   if(Alarm == RTC_ALARM_A)
01234   {
01235     /* AlarmA */
01236     sAlarm->Alarm = RTC_ALARM_A;
01237
01238     tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
01239     subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);
01240   }
01241   else
01242   {
01243     sAlarm->Alarm = RTC_ALARM_B;
01244
01245     tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
01246     subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
01247   }
01248
01249   /* Fill the structure with the read parameters */
01250   /* ALRMAR/ALRMBR registers have same mapping)  */
01251   sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16);
01252   sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8);
01253   sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
01254   sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
01255   sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
01256   sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
01257   sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
01258   sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
01259
01260   if(Format == RTC_FORMAT_BIN)
01261   {
01262     sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
01263     sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
01264     sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
01265     sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
01266   }
01267
01268   return HAL_OK;
01269 }
01270
01271 /**
01272   * @brief  Handle Alarm interrupt request.
01273   * @param  hrtc: RTC handle
01274   * @retval None
01275   */
01276 void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
01277 {
01278
01279   /* Clear the EXTI's line Flag for RTC Alarm */
01280     __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
01281
01282   /* Get the AlarmA interrupt source enable status */
01283   if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET)
01284   {
01285     /* Get the pending status of the AlarmA Interrupt */
01286     if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)
01287     {
01288
01289       /* Clear the AlarmA interrupt pending bit */
01290       __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01291
01292       /* AlarmA callback */
01293       HAL_RTC_AlarmAEventCallback(hrtc);
01294     }
01295   }
01296
01297   /* Get the AlarmB interrupt source enable status */
01298   if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET)
01299   {
01300     /* Get the pending status of the AlarmB Interrupt */
01301     if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET)
01302     {
01303
01304       /* Clear the AlarmB interrupt pending bit */
01305       __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
01306
01307       /* AlarmB callback */
01308       HAL_RTCEx_AlarmBEventCallback(hrtc);
01309     }
01310   }
01311
01312   /* Change RTC state */
01313   hrtc->State = HAL_RTC_STATE_READY;
01314 }
01315
01316 /**
01317   * @brief  Alarm A callback.
01318   * @param  hrtc: RTC handle
01319   * @retval None
01320   */
01321 __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
01322 {
01323   /* Prevent unused argument(s) compilation warning */
01324   UNUSED(hrtc);
01325
01326   /* NOTE : This function should not be modified, when the callback is needed,
01327             the HAL_RTC_AlarmAEventCallback could be implemented in the user file
01328    */
01329 }
01330
01331 /**
01332   * @brief  Handle AlarmA Polling request.
01333   * @param  hrtc: RTC handle
01334   * @param  Timeout: Timeout duration
01335   * @retval HAL status
01336   */
01337 HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01338 {
01339
01340   uint32_t tickstart = HAL_GetTick();
01341
01342   while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
01343   {
01344     if(Timeout != HAL_MAX_DELAY)
01345     {
01346       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01347       {
01348         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01349         return HAL_TIMEOUT;
01350       }
01351     }
01352   }
01353
01354   /* Clear the Alarm interrupt pending bit */
01355   __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01356
01357   /* Change RTC state */
01358   hrtc->State = HAL_RTC_STATE_READY;
01359
01360   return HAL_OK;
01361 }
01362
01363 /**
01364   * @}
01365   */
01366
01367 /** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
01368  *  @brief   Peripheral Control functions
01369  *
01370 @verbatim
01371  ===============================================================================
01372                      ##### Peripheral Control functions #####
01373  ===============================================================================
01374     [..]
01375     This subsection provides functions allowing to
01376       (+) Wait for RTC Time and Date Synchronization
01377
01378 @endverbatim
01379   * @{
01380   */
01381
01382 /**
01383   * @brief  Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
01384   *         synchronized with RTC APB clock.
01385   * @note   The RTC Resynchronization mode is write protected, use the
01386   *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
01387   * @note   To read the calendar through the shadow registers after Calendar
01388   *         initialization, calendar update or after wakeup from low power modes
01389   *         the software must first clear the RSF flag.
01390   *         The software must then wait until it is set again before reading
01391   *         the calendar, which means that the calendar registers have been
01392   *         correctly copied into the RTC_TR and RTC_DR shadow registers.
01393   * @param  hrtc: RTC handle
01394   * @retval HAL status
01395   */
01396 HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
01397 {
01398   uint32_t tickstart = 0;
01399
01400   /* Clear RSF flag */
01401   hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
01402
01403   tickstart = HAL_GetTick();
01404
01405   /* Wait the registers to be synchronised */
01406   while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
01407   {
01408     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01409     {
01410       return HAL_TIMEOUT;
01411     }
01412   }
01413
01414   return HAL_OK;
01415 }
01416
01417 /**
01418   * @}
01419   */
01420
01421 /** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
01422  *  @brief   Peripheral State functions
01423  *
01424 @verbatim
01425  ===============================================================================
01426                      ##### Peripheral State functions #####
01427  ===============================================================================
01428     [..]
01429     This subsection provides functions allowing to
01430       (+) Get RTC state
01431
01432 @endverbatim
01433   * @{
01434   */
01435 /**
01436   * @brief  Return the RTC handle state.
01437   * @param  hrtc: RTC handle
01438   * @retval HAL state
01439   */
01440 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
01441 {
01442   /* Return RTC handle state */
01443   return hrtc->State;
01444 }
01445
01446 /**
01447   * @}
01448   */
01449
01450 /**
01451   * @}
01452   */
01453
01454 /** @defgroup RTC_Private_Functions RTC Private functions
01455   * @{
01456   */
01457 /**
01458   * @brief  Enter the RTC Initialization mode.
01459   * @note   The RTC Initialization mode is write protected, use the
01460   *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
01461   * @param  hrtc: RTC handle
01462   * @retval HAL status
01463   */
01464 HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
01465 {
01466   uint32_t tickstart = 0;
01467
01468   /* Check if the Initialization mode is set */
01469   if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
01470   {
01471     /* Set the Initialization mode */
01472     hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
01473
01474     tickstart = HAL_GetTick();
01475     /* Wait till RTC is in INIT state and if Time out is reached exit */
01476     while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
01477     {
01478       if((HAL_GetTick()  - tickstart ) > RTC_TIMEOUT_VALUE)
01479       {
01480         return HAL_TIMEOUT;
01481       }
01482     }
01483   }
01484
01485   return HAL_OK;
01486 }
01487
01488
01489 /**
01490   * @brief  Convert a 2 digit decimal to BCD format.
01491   * @param  Value: Byte to be converted
01492   * @retval Converted byte
01493   */
01494 uint8_t RTC_ByteToBcd2(uint8_t Value)
01495 {
01496   uint32_t bcdhigh = 0;
01497
01498   while(Value >= 10)
01499   {
01500     bcdhigh++;
01501     Value -= 10;
01502   }
01503
01504   return  ((uint8_t)(bcdhigh << 4) | Value);
01505 }
01506
01507 /**
01508   * @brief  Convert from 2 digit BCD to Binary.
01509   * @param  Value: BCD value to be converted
01510   * @retval Converted word
01511   */
01512 uint8_t RTC_Bcd2ToByte(uint8_t Value)
01513 {
01514   uint32_t tmp = 0;
01515   tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
01516   return (tmp + (Value & (uint8_t)0x0F));
01517 }
01518
01519 /**
01520   * @}
01521   */
01522
01523 #endif /* HAL_RTC_MODULE_ENABLED */
01524 /**
01525   * @}
01526   */
01527
01528 /**
01529   * @}
01530   */
01531
01532 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_rtc.h Source File

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stm32h7xx_hal_rtc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rtc.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of RTC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_RTC_H
00040 #define __STM32H7xx_HAL_RTC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup RTC
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup RTC_Exported_Types RTC Exported Types
00059   * @{
00060   */
00061 /**
00062   * @brief  HAL State structures definition
00063   */
00064 typedef enum
00065 {
00066   HAL_RTC_STATE_RESET             = 0x00,  /*!< RTC not yet initialized or disabled */
00067   HAL_RTC_STATE_READY             = 0x01,  /*!< RTC initialized and ready for use   */
00068   HAL_RTC_STATE_BUSY              = 0x02,  /*!< RTC process is ongoing              */
00069   HAL_RTC_STATE_TIMEOUT           = 0x03,  /*!< RTC timeout state                   */
00070   HAL_RTC_STATE_ERROR             = 0x04   /*!< RTC error state                     */
00071
00072 }HAL_RTCStateTypeDef;
00073
00074 /**
00075   * @brief  RTC Configuration Structure definition
00076   */
00077 typedef struct
00078 {
00079   uint32_t HourFormat;      /*!< Specifies the RTC Hour Format.
00080                                  This parameter can be a value of @ref RTC_Hour_Formats */
00081
00082   uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.
00083                                  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
00084
00085   uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.
00086                                  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
00087
00088   uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.
00089                                  This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
00090
00091   uint32_t OutPutRemap;    /*!< Specifies the remap for RTC output.
00092                                  This parameter can be a value of @ref  RTC_Output_ALARM_OUT_Remap */
00093
00094   uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.
00095                                  This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
00096
00097   uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.
00098                                  This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
00099
00100 }RTC_InitTypeDef;
00101
00102 /**
00103   * @brief  RTC Time structure definition
00104   */
00105 typedef struct
00106 {
00107   uint8_t Hours;            /*!< Specifies the RTC Time Hour.
00108                                  This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
00109                                  This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
00110
00111   uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
00112                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
00113
00114   uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
00115                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
00116
00117   uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
00118                                  This parameter can be a value of @ref RTC_AM_PM_Definitions */
00119
00120   uint32_t SubSeconds;     /*!< Specifies the RTC_SSR RTC Sub Second register content.
00121                                  This parameter corresponds to a time unit range between [0-1] Second
00122                                  with [1 Sec / SecondFraction +1] granularity */
00123
00124   uint32_t SecondFraction;  /*!< Specifies the range or granularity of Sub Second register content
00125                                  corresponding to Synchronous pre-scaler factor value (PREDIV_S)
00126                                  This parameter corresponds to a time unit range between [0-1] Second
00127                                  with [1 Sec / SecondFraction +1] granularity.
00128                                  This field will be used only by HAL_RTC_GetTime function */
00129
00130   uint32_t DayLightSaving;  /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
00131                                  This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
00132
00133   uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
00134                                  in CR register to store the operation.
00135                                  This parameter can be a value of @ref RTC_StoreOperation_Definitions */
00136 }RTC_TimeTypeDef;
00137
00138 /**
00139   * @brief  RTC Date structure definition
00140   */
00141 typedef struct
00142 {
00143   uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
00144                          This parameter can be a value of @ref RTC_WeekDay_Definitions */
00145
00146   uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
00147                          This parameter can be a value of @ref RTC_Month_Date_Definitions */
00148
00149   uint8_t Date;     /*!< Specifies the RTC Date.
00150                          This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
00151
00152   uint8_t Year;     /*!< Specifies the RTC Date Year.
00153                          This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
00154
00155 }RTC_DateTypeDef;
00156
00157 /**
00158   * @brief  RTC Alarm structure definition
00159   */
00160 typedef struct
00161 {
00162   RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
00163
00164   uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
00165                                       This parameter can be a value of @ref RTC_AlarmMask_Definitions */
00166
00167   uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.
00168                                       This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
00169
00170   uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
00171                                      This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
00172
00173   uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
00174                                       If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
00175                                       If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
00176
00177   uint32_t Alarm;                /*!< Specifies the alarm .
00178                                       This parameter can be a value of @ref RTC_Alarms_Definitions */
00179 }RTC_AlarmTypeDef;
00180
00181 /**
00182   * @brief  Time Handle Structure definition
00183   */
00184 typedef struct
00185 {
00186   RTC_TypeDef               *Instance;  /*!< Register base address    */
00187
00188   RTC_InitTypeDef           Init;       /*!< RTC required parameters  */
00189
00190   HAL_LockTypeDef           Lock;       /*!< RTC locking object       */
00191
00192   __IO HAL_RTCStateTypeDef  State;      /*!< Time communication state */
00193
00194 }RTC_HandleTypeDef;
00195
00196 /**
00197   * @}
00198   */
00199
00200 /* Exported constants --------------------------------------------------------*/
00201 /** @defgroup RTC_Exported_Constants RTC Exported Constants
00202   * @{
00203   */
00204
00205 /** @defgroup RTC_Hour_Formats RTC Hour Formats
00206   * @{
00207   */
00208 #define RTC_HOURFORMAT_24              ((uint32_t)0x00000000)
00209 #define RTC_HOURFORMAT_12              ((uint32_t)0x00000040)
00210 /**
00211   * @}
00212   */
00213
00214 /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
00215   * @{
00216   */
00217 #define RTC_OUTPUT_POLARITY_HIGH       ((uint32_t)0x00000000)
00218 #define RTC_OUTPUT_POLARITY_LOW        ((uint32_t)0x00100000)
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
00224   * @{
00225   */
00226 #define RTC_OUTPUT_TYPE_OPENDRAIN      ((uint32_t)0x00000000)
00227 #define RTC_OUTPUT_TYPE_PUSHPULL       ((uint32_t)RTC_OR_ALARMOUTTYPE)
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
00233   * @{
00234   */
00235 #define RTC_OUTPUT_REMAP_NONE               ((uint32_t)0x00000000)
00236 #define RTC_OUTPUT_REMAP_POS1               ((uint32_t)RTC_OR_OUT_RMP)
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
00242   * @{
00243   */
00244 #define RTC_HOURFORMAT12_AM            ((uint8_t)0x00)
00245 #define RTC_HOURFORMAT12_PM            ((uint8_t)0x40)
00246 /**
00247   * @}
00248   */
00249
00250 /** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
00251   * @{
00252   */
00253 #define RTC_DAYLIGHTSAVING_SUB1H       ((uint32_t)0x00020000)
00254 #define RTC_DAYLIGHTSAVING_ADD1H       ((uint32_t)0x00010000)
00255 #define RTC_DAYLIGHTSAVING_NONE        ((uint32_t)0x00000000)
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
00261   * @{
00262   */
00263 #define RTC_STOREOPERATION_RESET        ((uint32_t)0x00000000)
00264 #define RTC_STOREOPERATION_SET          ((uint32_t)0x00040000)
00265 /**
00266   * @}
00267   */
00268
00269 /** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
00270   * @{
00271   */
00272 #define RTC_FORMAT_BIN                  ((uint32_t)0x000000000)
00273 #define RTC_FORMAT_BCD                  ((uint32_t)0x000000001)
00274 /**
00275   * @}
00276   */
00277
00278 /** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
00279   * @{
00280   */
00281
00282 /* Coded in BCD format */
00283 #define RTC_MONTH_JANUARY              ((uint8_t)0x01)
00284 #define RTC_MONTH_FEBRUARY             ((uint8_t)0x02)
00285 #define RTC_MONTH_MARCH                ((uint8_t)0x03)
00286 #define RTC_MONTH_APRIL                ((uint8_t)0x04)
00287 #define RTC_MONTH_MAY                  ((uint8_t)0x05)
00288 #define RTC_MONTH_JUNE                 ((uint8_t)0x06)
00289 #define RTC_MONTH_JULY                 ((uint8_t)0x07)
00290 #define RTC_MONTH_AUGUST               ((uint8_t)0x08)
00291 #define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09)
00292 #define RTC_MONTH_OCTOBER              ((uint8_t)0x10)
00293 #define RTC_MONTH_NOVEMBER             ((uint8_t)0x11)
00294 #define RTC_MONTH_DECEMBER             ((uint8_t)0x12)
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
00300   * @{
00301   */
00302 #define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01)
00303 #define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02)
00304 #define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03)
00305 #define RTC_WEEKDAY_THURSDAY           ((uint8_t)0x04)
00306 #define RTC_WEEKDAY_FRIDAY             ((uint8_t)0x05)
00307 #define RTC_WEEKDAY_SATURDAY           ((uint8_t)0x06)
00308 #define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x07)
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
00314   * @{
00315   */
00316 #define RTC_ALARMDATEWEEKDAYSEL_DATE      ((uint32_t)0x00000000)
00317 #define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   ((uint32_t)0x40000000)
00318 /**
00319   * @}
00320   */
00321
00322
00323 /** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
00324   * @{
00325   */
00326 #define RTC_ALARMMASK_NONE                ((uint32_t)0x00000000)
00327 #define RTC_ALARMMASK_DATEWEEKDAY         RTC_ALRMAR_MSK4
00328 #define RTC_ALARMMASK_HOURS               RTC_ALRMAR_MSK3
00329 #define RTC_ALARMMASK_MINUTES             RTC_ALRMAR_MSK2
00330 #define RTC_ALARMMASK_SECONDS             RTC_ALRMAR_MSK1
00331 #define RTC_ALARMMASK_ALL                 ((uint32_t)0x80808080)
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
00337   * @{
00338   */
00339 #define RTC_ALARM_A                       RTC_CR_ALRAE
00340 #define RTC_ALARM_B                       RTC_CR_ALRBE
00341 /**
00342   * @}
00343   */
00344
00345 /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
00346   * @{
00347   */
00348 #define RTC_ALARMSUBSECONDMASK_ALL         ((uint32_t)0x00000000)  /*!< All Alarm SS fields are masked.
00349                                                                         There is no comparison on sub seconds
00350                                                                         for Alarm */
00351 #define RTC_ALARMSUBSECONDMASK_SS14_1      ((uint32_t)0x01000000)  /*!< SS[14:1] are don't care in Alarm
00352                                                                         comparison. Only SS[0] is compared.    */
00353 #define RTC_ALARMSUBSECONDMASK_SS14_2      ((uint32_t)0x02000000)  /*!< SS[14:2] are don't care in Alarm
00354                                                                         comparison. Only SS[1:0] are compared  */
00355 #define RTC_ALARMSUBSECONDMASK_SS14_3      ((uint32_t)0x03000000)  /*!< SS[14:3] are don't care in Alarm
00356                                                                         comparison. Only SS[2:0] are compared  */
00357 #define RTC_ALARMSUBSECONDMASK_SS14_4      ((uint32_t)0x04000000)  /*!< SS[14:4] are don't care in Alarm
00358                                                                         comparison. Only SS[3:0] are compared  */
00359 #define RTC_ALARMSUBSECONDMASK_SS14_5      ((uint32_t)0x05000000)  /*!< SS[14:5] are don't care in Alarm
00360                                                                         comparison. Only SS[4:0] are compared  */
00361 #define RTC_ALARMSUBSECONDMASK_SS14_6      ((uint32_t)0x06000000)  /*!< SS[14:6] are don't care in Alarm
00362                                                                         comparison. Only SS[5:0] are compared  */
00363 #define RTC_ALARMSUBSECONDMASK_SS14_7      ((uint32_t)0x07000000)  /*!< SS[14:7] are don't care in Alarm
00364                                                                         comparison. Only SS[6:0] are compared  */
00365 #define RTC_ALARMSUBSECONDMASK_SS14_8      ((uint32_t)0x08000000)  /*!< SS[14:8] are don't care in Alarm
00366                                                                         comparison. Only SS[7:0] are compared  */
00367 #define RTC_ALARMSUBSECONDMASK_SS14_9      ((uint32_t)0x09000000)  /*!< SS[14:9] are don't care in Alarm
00368                                                                         comparison. Only SS[8:0] are compared  */
00369 #define RTC_ALARMSUBSECONDMASK_SS14_10     ((uint32_t)0x0A000000)  /*!< SS[14:10] are don't care in Alarm
00370                                                                         comparison. Only SS[9:0] are compared  */
00371 #define RTC_ALARMSUBSECONDMASK_SS14_11     ((uint32_t)0x0B000000)  /*!< SS[14:11] are don't care in Alarm
00372                                                                         comparison. Only SS[10:0] are compared */
00373 #define RTC_ALARMSUBSECONDMASK_SS14_12     ((uint32_t)0x0C000000)  /*!< SS[14:12] are don't care in Alarm
00374                                                                         comparison.Only SS[11:0] are compared  */
00375 #define RTC_ALARMSUBSECONDMASK_SS14_13     ((uint32_t)0x0D000000)  /*!< SS[14:13] are don't care in Alarm
00376                                                                         comparison. Only SS[12:0] are compared */
00377 #define RTC_ALARMSUBSECONDMASK_SS14        ((uint32_t)0x0E000000)  /*!< SS[14] is don't care in Alarm
00378                                                                         comparison.Only SS[13:0] are compared  */
00379 #define RTC_ALARMSUBSECONDMASK_NONE        ((uint32_t)0x0F000000)  /*!< SS[14:0] are compared and must match
00380                                                                         to activate alarm. */
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
00386   * @{
00387   */
00388 #define RTC_IT_TS                         ((uint32_t)RTC_CR_TSIE)         /*!< Enable Timestamp Interrupt               */
00389 #define RTC_IT_WUT                        ((uint32_t)RTC_CR_WUTIE)        /*!< Enable Wakeup timer Interrupt            */
00390 #define RTC_IT_ALRA                       ((uint32_t)RTC_CR_ALRAIE)       /*!< Enable Alarm A Interrupt                 */
00391 #define RTC_IT_ALRB                       ((uint32_t)RTC_CR_ALRBIE)       /*!< Enable Alarm B Interrupt                 */
00392 #define RTC_IT_TAMP                       ((uint32_t)RTC_TAMPCR_TAMPIE)   /*!< Enable all Tamper Interrupt              */
00393 #define RTC_IT_TAMP1                      ((uint32_t)RTC_TAMPCR_TAMP1IE)  /*!< Enable Tamper 1 Interrupt                */
00394 #define RTC_IT_TAMP2                      ((uint32_t)RTC_TAMPCR_TAMP2IE)  /*!< Enable Tamper 2 Interrupt                */
00395 #define RTC_IT_TAMP3                      ((uint32_t)RTC_TAMPCR_TAMP3IE)  /*!< Enable Tamper 3 Interrupt                */
00396 /**
00397   * @}
00398   */
00399
00400 /** @defgroup RTC_Flags_Definitions RTC Flags Definitions
00401   * @{
00402   */
00403 #define RTC_FLAG_RECALPF                  ((uint32_t)RTC_ISR_RECALPF)
00404 #define RTC_FLAG_TAMP3F                   ((uint32_t)RTC_ISR_TAMP3F)
00405 #define RTC_FLAG_TAMP2F                   ((uint32_t)RTC_ISR_TAMP2F)
00406 #define RTC_FLAG_TAMP1F                   ((uint32_t)RTC_ISR_TAMP1F)
00407 #define RTC_FLAG_TSOVF                    ((uint32_t)RTC_ISR_TSOVF)
00408 #define RTC_FLAG_TSF                      ((uint32_t)RTC_ISR_TSF)
00409 #define RTC_FLAG_ITSF                     ((uint32_t)RTC_ISR_ITSF)
00410 #define RTC_FLAG_WUTF                     ((uint32_t)RTC_ISR_WUTF)
00411 #define RTC_FLAG_ALRBF                    ((uint32_t)RTC_ISR_ALRBF)
00412 #define RTC_FLAG_ALRAF                    ((uint32_t)RTC_ISR_ALRAF)
00413 #define RTC_FLAG_INITF                    ((uint32_t)RTC_ISR_INITF)
00414 #define RTC_FLAG_RSF                      ((uint32_t)RTC_ISR_RSF)
00415 #define RTC_FLAG_INITS                    ((uint32_t)RTC_ISR_INITS)
00416 #define RTC_FLAG_SHPF                     ((uint32_t)RTC_ISR_SHPF)
00417 #define RTC_FLAG_WUTWF                    ((uint32_t)RTC_ISR_WUTWF)
00418 #define RTC_FLAG_ALRBWF                   ((uint32_t)RTC_ISR_ALRBWF)
00419 #define RTC_FLAG_ALRAWF                   ((uint32_t)RTC_ISR_ALRAWF)
00420 /**
00421   * @}
00422   */
00423
00424 /**
00425   * @}
00426   */
00427
00428 /* Exported macros -----------------------------------------------------------*/
00429 /** @defgroup RTC_Exported_Macros RTC Exported Macros
00430   * @{
00431   */
00432
00433 /** @brief Reset RTC handle state
00434   * @param  __HANDLE__: RTC handle.
00435   * @retval None
00436   */
00437 #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
00438
00439 /**
00440   * @brief  Disable the write protection for RTC registers.
00441   * @param  __HANDLE__: specifies the RTC handle.
00442   * @retval None
00443   */
00444 #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
00445                         do{                                       \
00446                             (__HANDLE__)->Instance->WPR = 0xCA;   \
00447                             (__HANDLE__)->Instance->WPR = 0x53;   \
00448                           } while(0)
00449
00450 /**
00451   * @brief  Enable the write protection for RTC registers.
00452   * @param  __HANDLE__: specifies the RTC handle.
00453   * @retval None
00454   */
00455 #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
00456                         do{                                       \
00457                             (__HANDLE__)->Instance->WPR = 0xFF;   \
00458                           } while(0)
00459
00460
00461 /**
00462   * @brief  Enable the RTC ALARMA peripheral.
00463   * @param  __HANDLE__: specifies the RTC handle.
00464   * @retval None
00465   */
00466 #define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
00467
00468 /**
00469   * @brief  Disable the RTC ALARMA peripheral.
00470   * @param  __HANDLE__: specifies the RTC handle.
00471   * @retval None
00472   */
00473 #define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)                         ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
00474
00475 /**
00476   * @brief  Enable the RTC ALARMB peripheral.
00477   * @param  __HANDLE__: specifies the RTC handle.
00478   * @retval None
00479   */
00480 #define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
00481
00482 /**
00483   * @brief  Disable the RTC ALARMB peripheral.
00484   * @param  __HANDLE__: specifies the RTC handle.
00485   * @retval None
00486   */
00487 #define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)                         ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
00488
00489 /**
00490   * @brief  Enable the RTC Alarm interrupt.
00491   * @param  __HANDLE__: specifies the RTC handle.
00492   * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
00493   *          This parameter can be any combination of the following values:
00494   *             @arg RTC_IT_ALRA: Alarm A interrupt
00495   *             @arg RTC_IT_ALRB: Alarm B interrupt
00496   * @retval None
00497   */
00498 #define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00499
00500 /**
00501   * @brief  Disable the RTC Alarm interrupt.
00502   * @param  __HANDLE__: specifies the RTC handle.
00503   * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
00504   *         This parameter can be any combination of the following values:
00505   *            @arg RTC_IT_ALRA: Alarm A interrupt
00506   *            @arg RTC_IT_ALRB: Alarm B interrupt
00507   * @retval None
00508   */
00509 #define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00510
00511 /**
00512   * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
00513   * @param  __HANDLE__: specifies the RTC handle.
00514   * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
00515   *         This parameter can be:
00516   *            @arg RTC_IT_ALRA: Alarm A interrupt
00517   *            @arg RTC_IT_ALRB: Alarm B interrupt
00518   * @retval None
00519   */
00520 #define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)            (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
00521
00522 /**
00523   * @brief  Get the selected RTC Alarm's flag status.
00524   * @param  __HANDLE__: specifies the RTC handle.
00525   * @param  __FLAG__: specifies the RTC Alarm Flag sources to check.
00526   *         This parameter can be:
00527   *            @arg RTC_FLAG_ALRAF
00528   *            @arg RTC_FLAG_ALRBF
00529   *            @arg RTC_FLAG_ALRAWF
00530   *            @arg RTC_FLAG_ALRBWF
00531   * @retval None
00532   */
00533 #define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
00534
00535 /**
00536   * @brief  Clear the RTC Alarm's pending flags.
00537   * @param  __HANDLE__: specifies the RTC handle.
00538   * @param  __FLAG__: specifies the RTC Alarm Flag sources to clear.
00539   *          This parameter can be:
00540   *             @arg RTC_FLAG_ALRAF
00541   *             @arg RTC_FLAG_ALRBF
00542   * @retval None
00543   */
00544 #define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00545
00546 /**
00547   * @brief  Check whether the specified RTC Alarm interrupt is enabled or not.
00548   * @param  __HANDLE__: specifies the RTC handle.
00549   * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
00550   *         This parameter can be:
00551   *            @arg RTC_IT_ALRA: Alarm A interrupt
00552   *            @arg RTC_IT_ALRB: Alarm B interrupt
00553   * @retval None
00554   */
00555 #define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
00556
00557 /**
00558   * @brief  Enable interrupt on the RTC Alarm associated Exti line.
00559   * @retval None
00560   */
00561 #define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI_D1->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00562
00563 /**
00564   * @brief  Disable interrupt on the RTC Alarm associated Exti line.
00565   * @retval None
00566   */
00567 #define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00568
00569 /**
00570   * @brief  Enable event on the RTC Alarm associated Exti line.
00571   * @retval None.
00572   */
00573 #define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI_D1->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00574
00575 /**
00576   * @brief  Disable event on the RTC Alarm associated Exti line.
00577   * @retval None.
00578   */
00579 #define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00580
00581 /**
00582   * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.
00583   * @retval None
00584   */
00585 #define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00586
00587 /**
00588   * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.
00589   * @retval None
00590   */
00591 #define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00592
00593 /**
00594   * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.
00595   * @retval None
00596   */
00597 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00598
00599 /**
00600   * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.
00601   * @retval None
00602   */
00603 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00604
00605 /**
00606   * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
00607   * @retval None
00608   */
00609 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
00610                                                              __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();  \
00611                                                              __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
00612                                                            } while(0)
00613 /**
00614   * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
00615   * @retval None
00616   */
00617 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
00618                                                              __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();  \
00619                                                              __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
00620                                                            } while(0)
00621 /**
00622   * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
00623   * @retval Line Status.
00624   */
00625 #define __HAL_RTC_ALARM_EXTI_GET_FLAG()              (EXTI_D1->PR1 & RTC_EXTI_LINE_ALARM_EVENT)
00626
00627 /**
00628   * @brief Clear the RTC Alarm associated Exti line flag.
00629   * @retval None.
00630   */
00631 #define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()            (EXTI_D1->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))
00632
00633 /**
00634   * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
00635   * @retval None
00636   */
00637 #define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()         (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)
00638
00639 /**
00640   * @}
00641   */
00642
00643 /* Include RTC HAL Extended module */
00644 #include "stm32h7xx_hal_rtc_ex.h"
00645
00646 /* Exported functions --------------------------------------------------------*/
00647 /** @addtogroup RTC_Exported_Functions
00648   * @{
00649   */
00650
00651 /** @addtogroup RTC_Exported_Functions_Group1
00652   * @{
00653   */
00654 /* Initialization and de-initialization functions  ****************************/
00655 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
00656 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
00657 void              HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
00658 void              HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
00659 /**
00660   * @}
00661   */
00662
00663 /** @addtogroup RTC_Exported_Functions_Group2
00664   * @{
00665   */
00666 /* RTC Time and Date functions ************************************************/
00667 HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
00668 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
00669 HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
00670 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
00671 /**
00672   * @}
00673   */
00674
00675 /** @addtogroup RTC_Exported_Functions_Group3
00676   * @{
00677   */
00678 /* RTC Alarm functions ********************************************************/
00679 HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
00680 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
00681 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
00682 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
00683 void              HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
00684 HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00685 void              HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
00686 /**
00687   * @}
00688   */
00689
00690 /** @addtogroup RTC_Exported_Functions_Group4
00691   * @{
00692   */
00693 /* Peripheral Control functions ***********************************************/
00694 HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
00695 /**
00696   * @}
00697   */
00698
00699 /** @addtogroup RTC_Exported_Functions_Group5
00700   * @{
00701   */
00702 /* Peripheral State functions *************************************************/
00703 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
00704
00705 /**
00706   * @}
00707   */
00708
00709 /**
00710   * @}
00711   */
00712
00713 /* Private types -------------------------------------------------------------*/
00714 /* Private variables ---------------------------------------------------------*/
00715 /* Private constants ---------------------------------------------------------*/
00716 /** @defgroup RTC_Private_Constants RTC Private Constants
00717   * @{
00718   */
00719 /* Masks Definition */
00720 #define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7F)
00721 #define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3F)
00722 #define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFFU)
00723 #define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5FU)
00724
00725 #define RTC_TIMEOUT_VALUE  1000
00726
00727 #define RTC_EXTI_LINE_ALARM_EVENT             ((uint32_t)0x00020000)  /*!< External interrupt line 17 Connected to the RTC Alarm event */
00728
00729 /**
00730   * @}
00731   */
00732
00733 /* Private macros ------------------------------------------------------------*/
00734 /** @defgroup RTC_Private_Macros RTC Private Macros
00735   * @{
00736   */
00737
00738 /** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
00739   * @{
00740   */
00741
00742 #define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \
00743                                         ((FORMAT) == RTC_HOURFORMAT_24))
00744
00745 #define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
00746                                 ((POL) == RTC_OUTPUT_POLARITY_LOW))
00747
00748 #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
00749                                   ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
00750
00751 #define IS_RTC_OUTPUT_REMAP(REMAP)     (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
00752                                         ((REMAP) == RTC_OUTPUT_REMAP_POS1))
00753
00754 #define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
00755
00756 #define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
00757                                       ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
00758                                       ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
00759
00760 #define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
00761                                            ((OPERATION) == RTC_STOREOPERATION_SET))
00762
00763 #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
00764
00765 #define IS_RTC_YEAR(YEAR)              ((YEAR) <= (uint32_t)99)
00766
00767 #define IS_RTC_MONTH(MONTH)            (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
00768
00769 #define IS_RTC_DATE(DATE)              (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
00770
00771 #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
00772                                  ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
00773                                  ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
00774                                  ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
00775                                  ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
00776                                  ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
00777                                  ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
00778
00779 #define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
00780
00781 #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
00782                                                     ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
00783                                                     ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
00784                                                     ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
00785                                                     ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
00786                                                     ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
00787                                                     ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
00788
00789 #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
00790                                             ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
00791
00792 #define IS_RTC_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
00793
00794 #define IS_RTC_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
00795
00796 #define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
00797
00798 #define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
00799                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
00800                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
00801                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
00802                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
00803                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
00804                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
00805                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
00806                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
00807                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
00808                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
00809                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
00810                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
00811                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
00812                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
00813                                               ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
00814
00815 #define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= (uint32_t)0x7F)
00816
00817 #define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= (uint32_t)0x7FFF)
00818
00819 #define IS_RTC_HOUR12(HOUR)            (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
00820
00821 #define IS_RTC_HOUR24(HOUR)            ((HOUR) <= (uint32_t)23)
00822
00823 #define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= (uint32_t)59)
00824
00825 #define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= (uint32_t)59)
00826
00827 /**
00828   * @}
00829   */
00830
00831 /**
00832   * @}
00833   */
00834
00835 /* Private functions ---------------------------------------------------------*/
00836 /** @addtogroup RTC_Private_Functions
00837   * @{
00838   */
00839
00840 HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
00841 uint8_t            RTC_ByteToBcd2(uint8_t Value);
00842 uint8_t            RTC_Bcd2ToByte(uint8_t Value);
00843
00844 /**
00845   * @}
00846   */
00847
00848 /**
00849   * @}
00850   */
00851
00852 /**
00853   * @}
00854   */
00855
00856 #ifdef __cplusplus
00857 }
00858 #endif
00859
00860 #endif /* __STM32H7xx_HAL_RTC_H */
00861
00862 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_rtc_ex.c Source File

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stm32h7xx_hal_rtc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rtc_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Extended RTC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Real Time Clock (RTC) Extended peripheral:
00010   *           + RTC Time Stamp functions
00011   *           + RTC Tamper functions
00012   *           + RTC Wake-up functions
00013   *           + Extended Control functions
00014   *           + Extended RTC features functions
00015   *
00016   @verbatim
00017   ==============================================================================
00018                   ##### How to use this driver #####
00019   ==============================================================================
00020   [..]
00021     (+) Enable the RTC domain access.
00022     (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
00023         format using the HAL_RTC_Init() function.
00024
00025   *** RTC Wakeup configuration ***
00026   ================================
00027   [..]
00028     (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
00029         function. You can also configure the RTC Wakeup timer with interrupt mode
00030         using the HAL_RTCEx_SetWakeUpTimer_IT() function.
00031     (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
00032         function.
00033
00034   *** Outputs configuration ***
00035   =============================
00036   [..]  The RTC has 2 different outputs:
00037     (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B
00038         and WaKeUp signals.
00039         To output the selected RTC signal, use the HAL_RTC_Init() function.
00040     (+) RTC_CALIB: this output is 512Hz signal or 1Hz.
00041         To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
00042     (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on
00043         the RTC_OR register.
00044     (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
00045         automatically configured in output alternate function.
00046
00047   *** Smooth digital Calibration configuration ***
00048   ================================================
00049   [..]
00050     (+) Configure the RTC Original Digital Calibration Value and the corresponding
00051         calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib()
00052         function.
00053
00054   *** TimeStamp configuration ***
00055   ===============================
00056   [..]
00057     (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function.
00058         You can also configure the RTC TimeStamp with interrupt mode using the
00059         HAL_RTCEx_SetTimeStamp_IT() function.
00060     (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
00061         function.
00062
00063   *** Internal TimeStamp configuration ***
00064   ===============================
00065   [..]
00066     (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function.
00067         User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG.
00068     (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
00069         function.
00070
00071   *** Tamper configuration ***
00072   ============================
00073   [..]
00074     (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
00075         or Level according to the Tamper filter (if equal to 0 Edge else Level)
00076         value, sampling frequency, NoErase, MaskFlag,  precharge or discharge and
00077         Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper
00078         with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
00079     (+) The default configuration of the Tamper erases the backup registers. To avoid
00080         erase, enable the NoErase field on the RTC_TAMPCR register.
00081
00082   *** Backup Data Registers configuration ***
00083   ===========================================
00084   [..]
00085     (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
00086         function.
00087     (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
00088         function.
00089
00090    @endverbatim
00091   ******************************************************************************
00092   * @attention
00093   *
00094   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00095   *
00096   * Redistribution and use in source and binary forms, with or without modification,
00097   * are permitted provided that the following conditions are met:
00098   *   1. Redistributions of source code must retain the above copyright notice,
00099   *      this list of conditions and the following disclaimer.
00100   *   2. Redistributions in binary form must reproduce the above copyright notice,
00101   *      this list of conditions and the following disclaimer in the documentation
00102   *      and/or other materials provided with the distribution.
00103   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00104   *      may be used to endorse or promote products derived from this software
00105   *      without specific prior written permission.
00106   *
00107   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00108   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00109   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00110   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00111   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00112   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00113   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00114   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00115   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00116   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00117   *
00118   ******************************************************************************
00119   */
00120
00121 /* Includes ------------------------------------------------------------------*/
00122 #include "stm32h7xx_hal.h"
00123
00124 /** @addtogroup STM32H7xx_HAL_Driver
00125   * @{
00126   */
00127
00128 /** @defgroup RTCEx RTCEx
00129   * @brief RTC Extended HAL module driver
00130   * @{
00131   */
00132
00133 #ifdef HAL_RTC_MODULE_ENABLED
00134
00135 /* Private typedef -----------------------------------------------------------*/
00136 /* Private define ------------------------------------------------------------*/
00137 /* Private macro -------------------------------------------------------------*/
00138 /* Private variables ---------------------------------------------------------*/
00139 /* Private function prototypes -----------------------------------------------*/
00140 /* Exported functions --------------------------------------------------------*/
00141
00142 /** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
00143   * @{
00144   */
00145
00146
00147 /** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions
00148  *  @brief   RTC TimeStamp and Tamper functions
00149   *
00150 @verbatim
00151  ===============================================================================
00152                  ##### RTC TimeStamp and Tamper functions #####
00153  ===============================================================================
00154
00155  [..] This section provide functions allowing to configure TimeStamp feature
00156
00157 @endverbatim
00158   * @{
00159   */
00160
00161 /**
00162   * @brief  Set TimeStamp.
00163   * @note   This API must be called before enabling the TimeStamp feature.
00164   * @param  hrtc: RTC handle
00165   * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is
00166   *         activated.
00167   *          This parameter can be one of the following values:
00168   *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
00169   *                                        rising edge of the related pin.
00170   *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
00171   *                                         falling edge of the related pin.
00172   * @param  RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
00173   *          This parameter can be one of the following values:
00174   *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
00175   *               The RTC TimeStamp Pin is per default PC13, but for reasons of
00176   *               compatibility, this parameter is required.
00177   * @retval HAL status
00178   */
00179 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
00180 {
00181   uint32_t tmpreg = 0;
00182
00183   /* Check the parameters */
00184   assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
00185   assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
00186
00187   /* Process Locked */
00188   __HAL_LOCK(hrtc);
00189
00190   hrtc->State = HAL_RTC_STATE_BUSY;
00191
00192   /* Get the RTC_CR register and clear the bits to be configured */
00193   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00194
00195   tmpreg|= TimeStampEdge;
00196
00197   /* Disable the write protection for RTC registers */
00198   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00199
00200   /* Configure the Time Stamp TSEDGE and Enable bits */
00201   hrtc->Instance->CR = (uint32_t)tmpreg;
00202
00203   __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
00204
00205   /* Enable the write protection for RTC registers */
00206   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00207
00208   /* Change RTC state */
00209   hrtc->State = HAL_RTC_STATE_READY;
00210
00211   /* Process Unlocked */
00212   __HAL_UNLOCK(hrtc);
00213
00214   return HAL_OK;
00215 }
00216
00217 /**
00218   * @brief  Set TimeStamp with Interrupt.
00219   * @param  hrtc: RTC handle
00220   * @note   This API must be called before enabling the TimeStamp feature.
00221   * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is
00222   *         activated.
00223   *          This parameter can be one of the following values:
00224   *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
00225   *                                        rising edge of the related pin.
00226   *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
00227   *                                         falling edge of the related pin.
00228   * @param  RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
00229   *          This parameter can be one of the following values:
00230   *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
00231   *               The RTC TimeStamp Pin is per default PC13, but for reasons of
00232   *               compatibility, this parameter is required.
00233   * @retval HAL status
00234   */
00235 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
00236 {
00237   uint32_t tmpreg = 0;
00238
00239   /* Check the parameters */
00240   assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
00241   assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
00242
00243   /* Process Locked */
00244   __HAL_LOCK(hrtc);
00245
00246   hrtc->State = HAL_RTC_STATE_BUSY;
00247
00248   /* Get the RTC_CR register and clear the bits to be configured */
00249   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00250
00251   tmpreg |= TimeStampEdge;
00252
00253   /* Disable the write protection for RTC registers */
00254   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00255
00256   /* Configure the Time Stamp TSEDGE and Enable bits */
00257   hrtc->Instance->CR = (uint32_t)tmpreg;
00258
00259   __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
00260
00261   /* Enable IT timestamp */
00262   __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
00263
00264   /* RTC timestamp Interrupt Configuration: EXTI configuration */
00265
00266     __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
00267
00268
00269   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
00270
00271   /* Enable the write protection for RTC registers */
00272   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00273
00274   hrtc->State = HAL_RTC_STATE_READY;
00275
00276   /* Process Unlocked */
00277   __HAL_UNLOCK(hrtc);
00278
00279   return HAL_OK;
00280 }
00281
00282 /**
00283   * @brief  Deactivate TimeStamp.
00284   * @param  hrtc: RTC handle
00285   * @retval HAL status
00286   */
00287 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
00288 {
00289   uint32_t tmpreg = 0;
00290
00291   /* Process Locked */
00292   __HAL_LOCK(hrtc);
00293
00294   hrtc->State = HAL_RTC_STATE_BUSY;
00295
00296   /* Disable the write protection for RTC registers */
00297   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00298
00299   /* In case of interrupt mode is used, the interrupt source must disabled */
00300   __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
00301
00302   /* Get the RTC_CR register and clear the bits to be configured */
00303   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00304
00305   /* Configure the Time Stamp TSEDGE and Enable bits */
00306   hrtc->Instance->CR = (uint32_t)tmpreg;
00307
00308   /* Enable the write protection for RTC registers */
00309   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00310
00311   hrtc->State = HAL_RTC_STATE_READY;
00312
00313   /* Process Unlocked */
00314   __HAL_UNLOCK(hrtc);
00315
00316   return HAL_OK;
00317 }
00318
00319 /**
00320   * @brief  Set Internal TimeStamp.
00321   * @note   This API must be called before enabling the internal TimeStamp feature.
00322   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00323   *                the configuration information for RTC.
00324   * @retval HAL status
00325   */
00326 HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc)
00327 {
00328   /* Process Locked */
00329   __HAL_LOCK(hrtc);
00330
00331   hrtc->State = HAL_RTC_STATE_BUSY;
00332
00333   /* Disable the write protection for RTC registers */
00334   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00335
00336   /* Configure the internal Time Stamp Enable bits */
00337   __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(hrtc);
00338
00339   /* Enable the write protection for RTC registers */
00340   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00341
00342   /* Change RTC state */
00343   hrtc->State = HAL_RTC_STATE_READY;
00344
00345   /* Process Unlocked */
00346   __HAL_UNLOCK(hrtc);
00347
00348   return HAL_OK;
00349 }
00350
00351
00352 /**
00353   * @brief  Deactivate Internal TimeStamp.
00354   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00355   *                the configuration information for RTC.
00356   * @retval HAL status
00357   */
00358 HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc)
00359 {
00360   /* Process Locked */
00361   __HAL_LOCK(hrtc);
00362
00363   hrtc->State = HAL_RTC_STATE_BUSY;
00364
00365   /* Disable the write protection for RTC registers */
00366   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00367
00368
00369   /* Configure the internal Time Stamp Enable bits */
00370   __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(hrtc);
00371
00372   /* Enable the write protection for RTC registers */
00373   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00374
00375   hrtc->State = HAL_RTC_STATE_READY;
00376
00377   /* Process Unlocked */
00378   __HAL_UNLOCK(hrtc);
00379
00380   return HAL_OK;
00381 }
00382
00383 /**
00384   * @brief  Get the RTC TimeStamp value.
00385   * @param  hrtc: RTC handle
00386   * @param  sTimeStamp: Pointer to Time structure
00387   * @param  sTimeStampDate: Pointer to Date structure
00388   * @param  Format: specifies the format of the entered parameters.
00389   *          This parameter can be one of the following values:
00390   *             @arg RTC_FORMAT_BIN: Binary data format
00391   *             @arg RTC_FORMAT_BCD: BCD data format
00392   * @retval HAL status
00393   */
00394 HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
00395 {
00396   uint32_t tmptime = 0, tmpdate = 0;
00397
00398   /* Check the parameters */
00399   assert_param(IS_RTC_FORMAT(Format));
00400
00401   /* Get the TimeStamp time and date registers values */
00402   tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
00403   tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
00404
00405   /* Fill the Time structure fields with the read parameters */
00406   sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
00407   sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
00408   sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
00409   sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
00410   sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
00411
00412   /* Fill the Date structure fields with the read parameters */
00413   sTimeStampDate->Year = 0;
00414   sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
00415   sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
00416   sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
00417
00418   /* Check the input parameters format */
00419   if(Format == RTC_FORMAT_BIN)
00420   {
00421     /* Convert the TimeStamp structure parameters to Binary format */
00422     sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
00423     sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
00424     sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
00425
00426     /* Convert the DateTimeStamp structure parameters to Binary format */
00427     sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
00428     sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
00429     sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
00430   }
00431
00432   /* Clear the TIMESTAMP Flags */
00433   __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_ITSF);
00434   __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
00435
00436   return HAL_OK;
00437 }
00438
00439 /**
00440   * @brief  Set Tamper.
00441   * @note   By calling this API we disable the tamper interrupt for all tampers.
00442   * @param  hrtc: RTC handle
00443   * @param  sTamper: Pointer to Tamper Structure.
00444   * @retval HAL status
00445   */
00446 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
00447 {
00448   uint32_t tmpreg = 0;
00449
00450   /* Check the parameters */
00451   assert_param(IS_RTC_TAMPER(sTamper->Tamper));
00452   assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
00453   assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
00454   assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
00455   assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
00456   assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
00457   assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
00458   assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
00459   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
00460
00461   /* Process Locked */
00462   __HAL_LOCK(hrtc);
00463
00464   hrtc->State = HAL_RTC_STATE_BUSY;
00465
00466   /* Configure the tamper trigger */
00467   if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
00468   {
00469     sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
00470   }
00471
00472   if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
00473   {
00474     sTamper->NoErase = 0;
00475     if((sTamper->Tamper & RTC_TAMPER_1) != 0)
00476     {
00477       sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
00478     }
00479     if((sTamper->Tamper & RTC_TAMPER_2) != 0)
00480     {
00481       sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
00482     }
00483     if((sTamper->Tamper & RTC_TAMPER_3) != 0)
00484     {
00485       sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
00486     }
00487   }
00488
00489   if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
00490   {
00491     sTamper->MaskFlag = 0;
00492     if((sTamper->Tamper & RTC_TAMPER_1) != 0)
00493     {
00494       sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
00495     }
00496     if((sTamper->Tamper & RTC_TAMPER_2) != 0)
00497     {
00498       sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
00499     }
00500     if((sTamper->Tamper & RTC_TAMPER_3) != 0)
00501     {
00502       sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
00503     }
00504   }
00505
00506   tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger  | (uint32_t)sTamper->NoErase |\
00507             (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\
00508             (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
00509
00510   hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\
00511                                        (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
00512                                        (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\
00513                                        (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE |\
00514                                        (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\
00515                                        (uint32_t)RTC_TAMPCR_TAMP2MF | (uint32_t)RTC_TAMPCR_TAMP3MF);
00516
00517   hrtc->Instance->TAMPCR |= tmpreg;
00518
00519   hrtc->State = HAL_RTC_STATE_READY;
00520
00521   /* Process Unlocked */
00522   __HAL_UNLOCK(hrtc);
00523
00524   return HAL_OK;
00525 }
00526
00527 /**
00528   * @brief  Set Tamper with interrupt.
00529   * @note   By calling this API we force the tamper interrupt for all tampers.
00530   * @param  hrtc: RTC handle
00531   * @param  sTamper: Pointer to RTC Tamper.
00532   * @retval HAL status
00533   */
00534 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
00535 {
00536   uint32_t tmpreg = 0;
00537
00538   /* Check the parameters */
00539   assert_param(IS_RTC_TAMPER(sTamper->Tamper));
00540   assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt));
00541   assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
00542   assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
00543   assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
00544   assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
00545   assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
00546   assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
00547   assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
00548   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
00549
00550   /* Process Locked */
00551   __HAL_LOCK(hrtc);
00552
00553   hrtc->State = HAL_RTC_STATE_BUSY;
00554
00555   /* Configure the tamper trigger */
00556   if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
00557   {
00558     sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
00559   }
00560
00561   if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
00562   {
00563     sTamper->NoErase = 0;
00564     if((sTamper->Tamper & RTC_TAMPER_1) != 0)
00565     {
00566       sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
00567     }
00568     if((sTamper->Tamper & RTC_TAMPER_2) != 0)
00569     {
00570       sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
00571     }
00572     if((sTamper->Tamper & RTC_TAMPER_3) != 0)
00573     {
00574       sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
00575     }
00576   }
00577
00578   if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
00579   {
00580     sTamper->MaskFlag = 0;
00581     if((sTamper->Tamper & RTC_TAMPER_1) != 0)
00582     {
00583       sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
00584     }
00585     if((sTamper->Tamper & RTC_TAMPER_2) != 0)
00586     {
00587       sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
00588     }
00589     if((sTamper->Tamper & RTC_TAMPER_3) != 0)
00590     {
00591       sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
00592     }
00593   }
00594
00595   tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger  | (uint32_t)sTamper->NoErase |\
00596             (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\
00597             (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
00598
00599   hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\
00600                                        (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
00601                                        (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\
00602                                        (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE |\
00603                                        (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\
00604                                        (uint32_t)RTC_TAMPCR_TAMP2MF | (uint32_t)RTC_TAMPCR_TAMP3MF);
00605
00606   hrtc->Instance->TAMPCR |= tmpreg;
00607
00608   /* RTC Tamper Interrupt Configuration: EXTI configuration */
00609
00610      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
00611
00612
00613   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
00614
00615   hrtc->State = HAL_RTC_STATE_READY;
00616
00617   /* Process Unlocked */
00618   __HAL_UNLOCK(hrtc);
00619
00620   return HAL_OK;
00621 }
00622
00623 /**
00624   * @brief  Deactivate Tamper.
00625   * @param  hrtc: RTC handle
00626   * @param  Tamper: Selected tamper pin.
00627   *          This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3.
00628   * @retval HAL status
00629   */
00630 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
00631 {
00632   assert_param(IS_RTC_TAMPER(Tamper));
00633
00634   /* Process Locked */
00635   __HAL_LOCK(hrtc);
00636
00637   hrtc->State = HAL_RTC_STATE_BUSY;
00638
00639   /* Disable the selected Tamper pin */
00640   hrtc->Instance->TAMPCR &= ((uint32_t)~Tamper);
00641
00642   if ((Tamper & RTC_TAMPER_1) != 0)
00643   {
00644     /* Disable the Tamper1 interrupt */
00645     hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1));
00646   }
00647   if ((Tamper & RTC_TAMPER_2) != 0)
00648   {
00649     /* Disable the Tamper2 interrupt */
00650     hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2));
00651   }
00652   if ((Tamper & RTC_TAMPER_3) != 0)
00653   {
00654     /* Disable the Tamper3 interrupt */
00655     hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3));
00656   }
00657
00658   hrtc->State = HAL_RTC_STATE_READY;
00659
00660   /* Process Unlocked */
00661   __HAL_UNLOCK(hrtc);
00662
00663   return HAL_OK;
00664 }
00665
00666 /**
00667   * @brief  Handle TimeStamp interrupt request.
00668   * @param  hrtc: RTC handle
00669   * @retval None
00670   */
00671 void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
00672 {
00673   /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
00674     __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
00675
00676   /* Get the TimeStamp interrupt source enable status */
00677   if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET)
00678   {
00679     /* Get the pending status of the TIMESTAMP Interrupt */
00680     if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)
00681     {
00682
00683        /* TIMESTAMP callback */
00684        HAL_RTCEx_TimeStampEventCallback(hrtc);
00685
00686       /* Clear the TIMESTAMP interrupt pending bit */
00687       __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
00688     }
00689   }
00690
00691   /* Get the Tamper1 interrupts source enable status */
00692   if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != RESET)
00693   {
00694     /* Get the pending status of the Tamper1 Interrupt */
00695     if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET)
00696     {
00697       /* Tamper1 callback */
00698       HAL_RTCEx_Tamper1EventCallback(hrtc);
00699
00700       /* Clear the Tamper1 interrupt pending bit */
00701       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
00702     }
00703   }
00704
00705   /* Get the Tamper2 interrupts source enable status */
00706   if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != RESET)
00707   {
00708     /* Get the pending status of the Tamper2 Interrupt */
00709     if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET)
00710     {
00711       /* Tamper2 callback */
00712       HAL_RTCEx_Tamper2EventCallback(hrtc);
00713
00714       /* Clear the Tamper2 interrupt pending bit */
00715       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
00716     }
00717   }
00718
00719   /* Get the Tamper3 interrupts source enable status */
00720   if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != RESET)
00721   {
00722     /* Get the pending status of the Tamper3 Interrupt */
00723     if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET)
00724     {
00725       /* Tamper3 callback */
00726       HAL_RTCEx_Tamper3EventCallback(hrtc);
00727
00728       /* Clear the Tamper3 interrupt pending bit */
00729       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
00730     }
00731   }
00732
00733
00734   /* Change RTC state */
00735   hrtc->State = HAL_RTC_STATE_READY;
00736 }
00737
00738 /**
00739   * @brief  TimeStamp callback.
00740   * @param  hrtc: RTC handle
00741   * @retval None
00742   */
00743 __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
00744 {
00745   /* Prevent unused argument(s) compilation warning */
00746   UNUSED(hrtc);
00747   /* NOTE : This function should not be modified, when the callback is needed,
00748             the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
00749   */
00750 }
00751
00752 /**
00753   * @brief  Tamper 1 callback.
00754   * @param  hrtc: RTC handle
00755   * @retval None
00756   */
00757 __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
00758 {
00759   /* Prevent unused argument(s) compilation warning */
00760   UNUSED(hrtc);
00761   /* NOTE : This function should not be modified, when the callback is needed,
00762             the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
00763    */
00764 }
00765
00766 /**
00767   * @brief  Tamper 2 callback.
00768   * @param  hrtc: RTC handle
00769   * @retval None
00770   */
00771 __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
00772 {
00773   /* Prevent unused argument(s) compilation warning */
00774   UNUSED(hrtc);
00775   /* NOTE : This function should not be modified, when the callback is needed,
00776             the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
00777    */
00778 }
00779
00780 /**
00781   * @brief  Tamper 3 callback.
00782   * @param  hrtc: RTC handle
00783   * @retval None
00784   */
00785 __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
00786 {
00787   /* Prevent unused argument(s) compilation warning */
00788   UNUSED(hrtc);
00789   /* NOTE : This function should not be modified, when the callback is needed,
00790             the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
00791    */
00792 }
00793
00794 /**
00795   * @brief  Handle TimeStamp polling request.
00796   * @param  hrtc: RTC handle
00797   * @param  Timeout: Timeout duration
00798   * @retval HAL status
00799   */
00800 HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00801 {
00802   uint32_t tickstart = HAL_GetTick();
00803
00804   while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
00805   {
00806     if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
00807     {
00808       /* Clear the TIMESTAMP OverRun Flag */
00809       __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
00810
00811       /* Change TIMESTAMP state */
00812       hrtc->State = HAL_RTC_STATE_ERROR;
00813
00814       return HAL_ERROR;
00815     }
00816
00817     if(Timeout != HAL_MAX_DELAY)
00818     {
00819       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00820       {
00821         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00822         return HAL_TIMEOUT;
00823       }
00824     }
00825   }
00826
00827   /* Change RTC state */
00828   hrtc->State = HAL_RTC_STATE_READY;
00829
00830   return HAL_OK;
00831 }
00832
00833 /**
00834   * @brief  Handle Tamper1 Polling.
00835   * @param  hrtc: RTC handle
00836   * @param  Timeout: Timeout duration
00837   * @retval HAL status
00838   */
00839 HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00840 {
00841   uint32_t tickstart = HAL_GetTick();
00842
00843   /* Get the status of the Interrupt */
00844   while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET)
00845   {
00846     if(Timeout != HAL_MAX_DELAY)
00847     {
00848       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00849       {
00850         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00851         return HAL_TIMEOUT;
00852       }
00853     }
00854   }
00855
00856   /* Clear the Tamper Flag */
00857   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
00858
00859   /* Change RTC state */
00860   hrtc->State = HAL_RTC_STATE_READY;
00861
00862   return HAL_OK;
00863 }
00864
00865 /**
00866   * @brief  Handle Tamper2 Polling.
00867   * @param  hrtc: RTC handle
00868   * @param  Timeout: Timeout duration
00869   * @retval HAL status
00870   */
00871 HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00872 {
00873   uint32_t tickstart = HAL_GetTick();
00874
00875   /* Get the status of the Interrupt */
00876   while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET)
00877   {
00878     if(Timeout != HAL_MAX_DELAY)
00879     {
00880       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00881       {
00882         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00883         return HAL_TIMEOUT;
00884       }
00885     }
00886   }
00887
00888   /* Clear the Tamper Flag */
00889   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
00890
00891   /* Change RTC state */
00892   hrtc->State = HAL_RTC_STATE_READY;
00893
00894   return HAL_OK;
00895 }
00896
00897 /**
00898   * @brief  Handle Tamper3 Polling.
00899   * @param  hrtc: RTC handle
00900   * @param  Timeout: Timeout duration
00901   * @retval HAL status
00902   */
00903 HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00904 {
00905   uint32_t tickstart = HAL_GetTick();
00906
00907   /* Get the status of the Interrupt */
00908   while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == RESET)
00909   {
00910     if(Timeout != HAL_MAX_DELAY)
00911     {
00912       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00913       {
00914         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00915         return HAL_TIMEOUT;
00916       }
00917     }
00918   }
00919
00920   /* Clear the Tamper Flag */
00921   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
00922
00923   /* Change RTC state */
00924   hrtc->State = HAL_RTC_STATE_READY;
00925
00926   return HAL_OK;
00927 }
00928
00929 /**
00930   * @}
00931   */
00932
00933 /** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions
00934   * @brief    RTC Wake-up functions
00935   *
00936 @verbatim
00937  ===============================================================================
00938                         ##### RTC Wake-up functions #####
00939  ===============================================================================
00940
00941  [..] This section provide functions allowing to configure Wake-up feature
00942
00943 @endverbatim
00944   * @{
00945   */
00946
00947 /**
00948   * @brief  Set wake up timer.
00949   * @param  hrtc: RTC handle
00950   * @param  WakeUpCounter: Wake up counter
00951   * @param  WakeUpClock: Wake up clock
00952   * @retval HAL status
00953   */
00954 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
00955 {
00956   uint32_t tickstart = 0;
00957
00958   /* Check the parameters */
00959   assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
00960   assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
00961
00962   /* Process Locked */
00963   __HAL_LOCK(hrtc);
00964
00965   hrtc->State = HAL_RTC_STATE_BUSY;
00966
00967   /* Disable the write protection for RTC registers */
00968   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00969
00970   /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
00971   if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
00972   {
00973     tickstart = HAL_GetTick();
00974
00975     /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
00976     while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
00977     {
00978       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00979       {
00980         /* Enable the write protection for RTC registers */
00981         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00982
00983         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00984
00985         /* Process Unlocked */
00986         __HAL_UNLOCK(hrtc);
00987
00988         return HAL_TIMEOUT;
00989       }
00990     }
00991   }
00992   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
00993
00994   tickstart = HAL_GetTick();
00995
00996   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
00997   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
00998   {
00999     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01000     {
01001       /* Enable the write protection for RTC registers */
01002       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01003
01004       hrtc->State = HAL_RTC_STATE_TIMEOUT;
01005
01006       /* Process Unlocked */
01007       __HAL_UNLOCK(hrtc);
01008
01009       return HAL_TIMEOUT;
01010     }
01011   }
01012
01013   /* Clear the Wakeup Timer clock source bits in CR register */
01014   hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
01015
01016   /* Configure the clock source */
01017   hrtc->Instance->CR |= (uint32_t)WakeUpClock;
01018
01019   /* Configure the Wakeup Timer counter */
01020   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
01021
01022    /* Enable the Wakeup Timer */
01023   __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
01024
01025   /* Enable the write protection for RTC registers */
01026   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01027
01028   hrtc->State = HAL_RTC_STATE_READY;
01029
01030   /* Process Unlocked */
01031   __HAL_UNLOCK(hrtc);
01032
01033   return HAL_OK;
01034 }
01035
01036 /**
01037   * @brief  Set wake up timer with interrupt.
01038   * @param  hrtc: RTC handle
01039   * @param  WakeUpCounter: Wake up counter
01040   * @param  WakeUpClock: Wake up clock
01041   * @retval HAL status
01042   */
01043 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
01044 {
01045   uint32_t tickstart = 0;
01046
01047   /* Check the parameters */
01048   assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
01049   assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
01050
01051   /* Process Locked */
01052   __HAL_LOCK(hrtc);
01053
01054   hrtc->State = HAL_RTC_STATE_BUSY;
01055
01056   /* Disable the write protection for RTC registers */
01057   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01058
01059   /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
01060   if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
01061   {
01062     tickstart = HAL_GetTick();
01063
01064     /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
01065     while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
01066     {
01067       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01068       {
01069         /* Enable the write protection for RTC registers */
01070         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01071
01072         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01073
01074         /* Process Unlocked */
01075         __HAL_UNLOCK(hrtc);
01076
01077         return HAL_TIMEOUT;
01078       }
01079     }
01080   }
01081   /* Disable the Wake-Up timer */
01082   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
01083
01084   /* Clear flag Wake-Up */
01085   __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
01086
01087   tickstart = HAL_GetTick();
01088
01089   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
01090   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
01091   {
01092     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01093     {
01094       /* Enable the write protection for RTC registers */
01095       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01096
01097       hrtc->State = HAL_RTC_STATE_TIMEOUT;
01098
01099       /* Process Unlocked */
01100       __HAL_UNLOCK(hrtc);
01101
01102       return HAL_TIMEOUT;
01103     }
01104   }
01105
01106   /* Configure the Wakeup Timer counter */
01107   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
01108
01109   /* Clear the Wakeup Timer clock source bits in CR register */
01110   hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
01111
01112   /* Configure the clock source */
01113   hrtc->Instance->CR |= (uint32_t)WakeUpClock;
01114
01115   /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
01116
01117     __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
01118
01119    __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
01120   /* Configure the Interrupt in the RTC_CR register */
01121   __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
01122
01123   /* Enable the Wakeup Timer */
01124   __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
01125
01126   /* Enable the write protection for RTC registers */
01127   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01128
01129   hrtc->State = HAL_RTC_STATE_READY;
01130
01131   /* Process Unlocked */
01132   __HAL_UNLOCK(hrtc);
01133
01134   return HAL_OK;
01135 }
01136
01137 /**
01138   * @brief  Deactivate wake up timer counter.
01139   * @param  hrtc: RTC handle
01140   * @retval HAL status
01141   */
01142 uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
01143 {
01144   uint32_t tickstart = 0;
01145
01146   /* Process Locked */
01147   __HAL_LOCK(hrtc);
01148
01149   hrtc->State = HAL_RTC_STATE_BUSY;
01150
01151   /* Disable the write protection for RTC registers */
01152   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01153
01154   /* Disable the Wakeup Timer */
01155   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
01156
01157   /* In case of interrupt mode is used, the interrupt source must disabled */
01158   __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
01159
01160   tickstart = HAL_GetTick();
01161   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
01162   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
01163   {
01164     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01165     {
01166       /* Enable the write protection for RTC registers */
01167       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01168
01169       hrtc->State = HAL_RTC_STATE_TIMEOUT;
01170
01171       /* Process Unlocked */
01172       __HAL_UNLOCK(hrtc);
01173
01174       return HAL_TIMEOUT;
01175     }
01176   }
01177
01178   /* Enable the write protection for RTC registers */
01179   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01180
01181   hrtc->State = HAL_RTC_STATE_READY;
01182
01183   /* Process Unlocked */
01184   __HAL_UNLOCK(hrtc);
01185
01186   return HAL_OK;
01187 }
01188
01189 /**
01190   * @brief  Get wake up timer counter.
01191   * @param  hrtc: RTC handle
01192   * @retval Counter value
01193   */
01194 uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
01195 {
01196   /* Get the counter value */
01197   return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
01198 }
01199
01200 /**
01201   * @brief  Handle Wake Up Timer interrupt request.
01202   * @param  hrtc: RTC handle
01203   * @retval None
01204   */
01205 void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
01206 {
01207       /* Clear the EXTI's line Flag for RTC WakeUpTimer */
01208      __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
01209     /* Get the pending status of the WAKEUPTIMER Interrupt */
01210     if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != RESET)
01211     {
01212       /* Clear the WAKEUPTIMER interrupt pending bit */
01213       __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
01214
01215     /* WAKEUPTIMER callback */
01216       HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
01217     }
01218
01219   /* Change RTC state */
01220   hrtc->State = HAL_RTC_STATE_READY;
01221 }
01222
01223 /**
01224   * @brief  Wake Up Timer callback.
01225   * @param  hrtc: RTC handle
01226   * @retval None
01227   */
01228 __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
01229 {
01230   /* Prevent unused argument(s) compilation warning */
01231   UNUSED(hrtc);
01232
01233   /* NOTE : This function should not be modified, when the callback is needed,
01234             the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
01235    */
01236 }
01237
01238 /**
01239   * @brief  Handle Wake Up Timer Polling.
01240   * @param  hrtc: RTC handle
01241   * @param  Timeout: Timeout duration
01242   * @retval HAL status
01243   */
01244 HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01245 {
01246   uint32_t tickstart = HAL_GetTick();
01247
01248   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
01249   {
01250     if(Timeout != HAL_MAX_DELAY)
01251     {
01252       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01253       {
01254         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01255
01256         return HAL_TIMEOUT;
01257       }
01258     }
01259   }
01260
01261   /* Clear the WAKEUPTIMER Flag */
01262   __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
01263
01264   /* Change RTC state */
01265   hrtc->State = HAL_RTC_STATE_READY;
01266
01267   return HAL_OK;
01268 }
01269
01270 /**
01271   * @}
01272   */
01273
01274
01275 /** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
01276   * @brief    Extended Peripheral Control functions
01277   *
01278 @verbatim
01279  ===============================================================================
01280               ##### Extended Peripheral Control functions #####
01281  ===============================================================================
01282     [..]
01283     This subsection provides functions allowing to
01284       (+) Write a data in a specified RTC Backup data register
01285       (+) Read a data in a specified RTC Backup data register
01286       (+) Set the Coarse calibration parameters.
01287       (+) Deactivate the Coarse calibration parameters
01288       (+) Set the Smooth calibration parameters.
01289       (+) Configure the Synchronization Shift Control Settings.
01290       (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01291       (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01292       (+) Enable the RTC reference clock detection.
01293       (+) Disable the RTC reference clock detection.
01294       (+) Enable the Bypass Shadow feature.
01295       (+) Disable the Bypass Shadow feature.
01296
01297 @endverbatim
01298   * @{
01299   */
01300
01301 /**
01302   * @brief  Write a data in a specified RTC Backup data register.
01303   * @param  hrtc: RTC handle
01304   * @param  BackupRegister: RTC Backup data Register number.
01305   *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
01306   *                                 specify the register.
01307   * @param  Data: Data to be written in the specified RTC Backup data register.
01308   * @retval None
01309   */
01310 void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
01311 {
01312   uint32_t tmp = 0;
01313
01314   /* Check the parameters */
01315   assert_param(IS_RTC_BKP(BackupRegister));
01316
01317   tmp = (uint32_t)&(hrtc->Instance->BKP0R);
01318   tmp += (BackupRegister * 4);
01319
01320   /* Write the specified register */
01321   *(__IO uint32_t *)tmp = (uint32_t)Data;
01322 }
01323
01324 /**
01325   * @brief  Read data from the specified RTC Backup data Register.
01326   * @param  hrtc: RTC handle
01327   * @param  BackupRegister: RTC Backup data Register number.
01328   *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
01329   *                                 specify the register.
01330   * @retval Read value
01331   */
01332 uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
01333 {
01334   uint32_t tmp = 0;
01335
01336   /* Check the parameters */
01337   assert_param(IS_RTC_BKP(BackupRegister));
01338
01339   tmp = (uint32_t)&(hrtc->Instance->BKP0R);
01340   tmp += (BackupRegister * 4);
01341
01342   /* Read the specified register */
01343   return (*(__IO uint32_t *)tmp);
01344 }
01345
01346 /**
01347   * @brief  Set the Smooth calibration parameters.
01348   * @param  hrtc: RTC handle
01349   * @param  SmoothCalibPeriod: Select the Smooth Calibration Period.
01350   *          This parameter can be can be one of the following values :
01351   *             @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
01352   *             @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
01353   *             @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
01354   * @param  SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
01355   *          This parameter can be one of the following values:
01356   *             @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
01357   *             @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
01358   * @param  SmoothCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
01359   *          This parameter can be one any value from 0 to 0x000001FF.
01360   * @note   To deactivate the smooth calibration, the field SmoothCalibPlusPulses
01361   *         must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
01362   *         SmoothCalibMinusPulsesValue must be equal to 0.
01363   * @retval HAL status
01364   */
01365 HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
01366 {
01367   uint32_t tickstart = 0;
01368
01369   /* Check the parameters */
01370   assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
01371   assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
01372   assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue));
01373
01374   /* Process Locked */
01375   __HAL_LOCK(hrtc);
01376
01377   hrtc->State = HAL_RTC_STATE_BUSY;
01378
01379   /* Disable the write protection for RTC registers */
01380   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01381
01382   /* check if a calibration is pending*/
01383   if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
01384   {
01385     tickstart = HAL_GetTick();
01386
01387     /* check if a calibration is pending*/
01388     while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
01389     {
01390       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01391       {
01392         /* Enable the write protection for RTC registers */
01393         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01394
01395         /* Change RTC state */
01396         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01397
01398         /* Process Unlocked */
01399         __HAL_UNLOCK(hrtc);
01400
01401         return HAL_TIMEOUT;
01402       }
01403     }
01404   }
01405
01406   /* Configure the Smooth calibration settings */
01407   hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue);
01408
01409   /* Enable the write protection for RTC registers */
01410   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01411
01412   /* Change RTC state */
01413   hrtc->State = HAL_RTC_STATE_READY;
01414
01415   /* Process Unlocked */
01416   __HAL_UNLOCK(hrtc);
01417
01418   return HAL_OK;
01419 }
01420
01421 /**
01422   * @brief  Configure the Synchronization Shift Control Settings.
01423   * @note   When REFCKON is set, firmware must not write to Shift control register.
01424   * @param  hrtc: RTC handle
01425   * @param  ShiftAdd1S: Select to add or not 1 second to the time calendar.
01426   *          This parameter can be one of the following values :
01427   *             @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
01428   *             @arg RTC_SHIFTADD1S_RESET: No effect.
01429   * @param  ShiftSubFS: Select the number of Second Fractions to substitute.
01430   *          This parameter can be one any value from 0 to 0x7FFF.
01431   * @retval HAL status
01432   */
01433 HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
01434 {
01435   uint32_t tickstart = 0;
01436
01437   /* Check the parameters */
01438   assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
01439   assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
01440
01441   /* Process Locked */
01442   __HAL_LOCK(hrtc);
01443
01444   hrtc->State = HAL_RTC_STATE_BUSY;
01445
01446   /* Disable the write protection for RTC registers */
01447   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01448
01449     tickstart = HAL_GetTick();
01450
01451     /* Wait until the shift is completed*/
01452     while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
01453     {
01454       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01455       {
01456         /* Enable the write protection for RTC registers */
01457         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01458
01459         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01460
01461         /* Process Unlocked */
01462         __HAL_UNLOCK(hrtc);
01463
01464         return HAL_TIMEOUT;
01465       }
01466     }
01467
01468     /* Check if the reference clock detection is disabled */
01469     if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
01470     {
01471       /* Configure the Shift settings */
01472       hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
01473
01474       /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
01475       if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
01476       {
01477         if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
01478         {
01479           /* Enable the write protection for RTC registers */
01480           __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01481
01482           hrtc->State = HAL_RTC_STATE_ERROR;
01483
01484           /* Process Unlocked */
01485           __HAL_UNLOCK(hrtc);
01486
01487           return HAL_ERROR;
01488         }
01489       }
01490     }
01491     else
01492     {
01493       /* Enable the write protection for RTC registers */
01494       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01495
01496       /* Change RTC state */
01497       hrtc->State = HAL_RTC_STATE_ERROR;
01498
01499       /* Process Unlocked */
01500       __HAL_UNLOCK(hrtc);
01501
01502       return HAL_ERROR;
01503     }
01504
01505   /* Enable the write protection for RTC registers */
01506   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01507
01508   /* Change RTC state */
01509   hrtc->State = HAL_RTC_STATE_READY;
01510
01511   /* Process Unlocked */
01512   __HAL_UNLOCK(hrtc);
01513
01514   return HAL_OK;
01515 }
01516
01517 /**
01518   * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01519   * @param  hrtc: RTC handle
01520   * @param  CalibOutput : Select the Calibration output Selection .
01521   *          This parameter can be one of the following values:
01522   *             @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
01523   *             @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
01524   * @retval HAL status
01525   */
01526 HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)
01527 {
01528   /* Check the parameters */
01529   assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
01530
01531   /* Process Locked */
01532   __HAL_LOCK(hrtc);
01533
01534   hrtc->State = HAL_RTC_STATE_BUSY;
01535
01536   /* Disable the write protection for RTC registers */
01537   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01538
01539   /* Clear flags before config */
01540   hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
01541
01542   /* Configure the RTC_CR register */
01543   hrtc->Instance->CR |= (uint32_t)CalibOutput;
01544
01545   __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
01546
01547   /* Enable the write protection for RTC registers */
01548   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01549
01550   /* Change RTC state */
01551   hrtc->State = HAL_RTC_STATE_READY;
01552
01553   /* Process Unlocked */
01554   __HAL_UNLOCK(hrtc);
01555
01556   return HAL_OK;
01557 }
01558
01559 /**
01560   * @brief  Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01561   * @param  hrtc: RTC handle
01562   * @retval HAL status
01563   */
01564 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
01565 {
01566   /* Process Locked */
01567   __HAL_LOCK(hrtc);
01568
01569   hrtc->State = HAL_RTC_STATE_BUSY;
01570
01571   /* Disable the write protection for RTC registers */
01572   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01573
01574   __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
01575
01576   /* Enable the write protection for RTC registers */
01577   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01578
01579   /* Change RTC state */
01580   hrtc->State = HAL_RTC_STATE_READY;
01581
01582   /* Process Unlocked */
01583   __HAL_UNLOCK(hrtc);
01584
01585   return HAL_OK;
01586 }
01587
01588 /**
01589   * @brief  Enable the RTC reference clock detection.
01590   * @param  hrtc: RTC handle
01591   * @retval HAL status
01592   */
01593 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
01594 {
01595   /* Process Locked */
01596   __HAL_LOCK(hrtc);
01597
01598   hrtc->State = HAL_RTC_STATE_BUSY;
01599
01600   /* Disable the write protection for RTC registers */
01601   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01602
01603   /* Set Initialization mode */
01604   if(RTC_EnterInitMode(hrtc) != HAL_OK)
01605   {
01606     /* Enable the write protection for RTC registers */
01607     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01608
01609     /* Set RTC state*/
01610     hrtc->State = HAL_RTC_STATE_ERROR;
01611
01612     /* Process Unlocked */
01613     __HAL_UNLOCK(hrtc);
01614
01615     return HAL_ERROR;
01616   }
01617   else
01618   {
01619     __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
01620
01621     /* Exit Initialization mode */
01622     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
01623   }
01624
01625   /* Enable the write protection for RTC registers */
01626   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01627
01628    /* Change RTC state */
01629   hrtc->State = HAL_RTC_STATE_READY;
01630
01631   /* Process Unlocked */
01632   __HAL_UNLOCK(hrtc);
01633
01634   return HAL_OK;
01635 }
01636
01637 /**
01638   * @brief  Disable the RTC reference clock detection.
01639   * @param  hrtc: RTC handle
01640   * @retval HAL status
01641   */
01642 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
01643 {
01644   /* Process Locked */
01645   __HAL_LOCK(hrtc);
01646
01647   hrtc->State = HAL_RTC_STATE_BUSY;
01648
01649   /* Disable the write protection for RTC registers */
01650   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01651
01652   /* Set Initialization mode */
01653   if(RTC_EnterInitMode(hrtc) != HAL_OK)
01654   {
01655     /* Enable the write protection for RTC registers */
01656     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01657
01658     /* Set RTC state*/
01659     hrtc->State = HAL_RTC_STATE_ERROR;
01660
01661     /* Process Unlocked */
01662     __HAL_UNLOCK(hrtc);
01663
01664     return HAL_ERROR;
01665   }
01666   else
01667   {
01668     __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
01669
01670     /* Exit Initialization mode */
01671     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
01672   }
01673
01674   /* Enable the write protection for RTC registers */
01675   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01676
01677   /* Change RTC state */
01678   hrtc->State = HAL_RTC_STATE_READY;
01679
01680   /* Process Unlocked */
01681   __HAL_UNLOCK(hrtc);
01682
01683   return HAL_OK;
01684 }
01685
01686 /**
01687   * @brief  Enable the Bypass Shadow feature.
01688   * @param  hrtc: RTC handle
01689   * @note   When the Bypass Shadow is enabled the calendar value are taken
01690   *         directly from the Calendar counter.
01691   * @retval HAL status
01692   */
01693 HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
01694 {
01695   /* Process Locked */
01696   __HAL_LOCK(hrtc);
01697
01698   hrtc->State = HAL_RTC_STATE_BUSY;
01699
01700   /* Disable the write protection for RTC registers */
01701   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01702
01703   /* Set the BYPSHAD bit */
01704   hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
01705
01706   /* Enable the write protection for RTC registers */
01707   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01708
01709   /* Change RTC state */
01710   hrtc->State = HAL_RTC_STATE_READY;
01711
01712   /* Process Unlocked */
01713   __HAL_UNLOCK(hrtc);
01714
01715   return HAL_OK;
01716 }
01717
01718 /**
01719   * @brief  Disable the Bypass Shadow feature.
01720   * @param  hrtc: RTC handle
01721   * @note   When the Bypass Shadow is enabled the calendar value are taken
01722   *         directly from the Calendar counter.
01723   * @retval HAL status
01724   */
01725 HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
01726 {
01727   /* Process Locked */
01728   __HAL_LOCK(hrtc);
01729
01730   hrtc->State = HAL_RTC_STATE_BUSY;
01731
01732   /* Disable the write protection for RTC registers */
01733   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01734
01735   /* Reset the BYPSHAD bit */
01736   hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD);
01737
01738   /* Enable the write protection for RTC registers */
01739   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01740
01741   /* Change RTC state */
01742   hrtc->State = HAL_RTC_STATE_READY;
01743
01744   /* Process Unlocked */
01745   __HAL_UNLOCK(hrtc);
01746
01747   return HAL_OK;
01748 }
01749
01750 /**
01751   * @}
01752   */
01753
01754 /** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
01755   * @brief    Extended features functions
01756   *
01757 @verbatim
01758  ===============================================================================
01759                  ##### Extended features functions #####
01760  ===============================================================================
01761     [..]  This section provides functions allowing to:
01762       (+) RTC Alarm B callback
01763       (+) RTC Poll for Alarm B request
01764
01765 @endverbatim
01766   * @{
01767   */
01768
01769 /**
01770   * @brief  Alarm B callback.
01771   * @param  hrtc: RTC handle
01772   * @retval None
01773   */
01774 __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
01775 {
01776   /* Prevent unused argument(s) compilation warning */
01777   UNUSED(hrtc);
01778
01779   /* NOTE : This function should not be modified, when the callback is needed,
01780             the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
01781    */
01782 }
01783
01784 /**
01785   * @brief  Handle Alarm B Polling request.
01786   * @param  hrtc: RTC handle
01787   * @param  Timeout: Timeout duration
01788   * @retval HAL status
01789   */
01790 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01791 {
01792   uint32_t tickstart = HAL_GetTick();
01793
01794   while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)
01795   {
01796     if(Timeout != HAL_MAX_DELAY)
01797     {
01798       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01799       {
01800         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01801         return HAL_TIMEOUT;
01802       }
01803     }
01804   }
01805
01806   /* Clear the Alarm Flag */
01807   __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
01808
01809   /* Change RTC state */
01810   hrtc->State = HAL_RTC_STATE_READY;
01811
01812   return HAL_OK;
01813 }
01814
01815 /**
01816   * @}
01817   */
01818
01819 /**
01820   * @}
01821   */
01822
01823 #endif /* HAL_RTC_MODULE_ENABLED */
01824 /**
01825   * @}
01826   */
01827
01828 /**
01829   * @}
01830   */
01831
01832 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_rtc_ex.h Source File

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stm32h7xx_hal_rtc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_rtc_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of RTC HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_RTC_EX_H
00040 #define __STM32H7xx_HAL_RTC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup RTCEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup RTCEx_Exported_Types RTCEx Exported Types
00059   * @{
00060   */
00061 /**
00062   * @brief  RTC Tamper structure definition
00063   */
00064 typedef struct
00065 {
00066   uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
00067                                              This parameter can be a value of @ref  RTCEx_Tamper_Pins_Definitions */
00068
00069   uint32_t Interrupt;                   /*!< Specifies the Tamper Interrupt.
00070                                              This parameter can be a value of @ref  RTCEx_Tamper_Interrupt_Definitions */
00071
00072   uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
00073                                              This parameter can be a value of @ref  RTCEx_Tamper_Trigger_Definitions */
00074
00075   uint32_t NoErase;                     /*!< Specifies the Tamper no erase mode.
00076                                              This parameter can be a value of @ref  RTCEx_Tamper_EraseBackUp_Definitions */
00077
00078   uint32_t MaskFlag;                     /*!< Specifies the Tamper Flag masking.
00079                                              This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions   */
00080
00081   uint32_t Filter;                      /*!< Specifies the RTC Filter Tamper.
00082                                              This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
00083
00084   uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.
00085                                              This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
00086
00087   uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration .
00088                                              This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
00089
00090   uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp .
00091                                              This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
00092
00093   uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
00094                                              This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
00095 }RTC_TamperTypeDef;
00096
00097 /**
00098   * @}
00099   */
00100
00101 /* Exported constants --------------------------------------------------------*/
00102 /** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
00103   * @{
00104   */
00105
00106 /** @defgroup RTCEx_Output_selection_Definitions RTC Output Selection Definitions
00107   * @{
00108   */
00109 #define RTC_OUTPUT_DISABLE             ((uint32_t)0x00000000)
00110 #define RTC_OUTPUT_ALARMA              ((uint32_t)0x00200000)
00111 #define RTC_OUTPUT_ALARMB              ((uint32_t)0x00400000)
00112 #define RTC_OUTPUT_WAKEUP              ((uint32_t)0x00600000)
00113
00114 /**
00115   * @}
00116   */
00117
00118 /** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions
00119   * @{
00120   */
00121 #define RTC_BKP_DR0                       ((uint32_t)0x00000000)
00122 #define RTC_BKP_DR1                       ((uint32_t)0x00000001)
00123 #define RTC_BKP_DR2                       ((uint32_t)0x00000002)
00124 #define RTC_BKP_DR3                       ((uint32_t)0x00000003)
00125 #define RTC_BKP_DR4                       ((uint32_t)0x00000004)
00126 #define RTC_BKP_DR5                       ((uint32_t)0x00000005)
00127 #define RTC_BKP_DR6                       ((uint32_t)0x00000006)
00128 #define RTC_BKP_DR7                       ((uint32_t)0x00000007)
00129 #define RTC_BKP_DR8                       ((uint32_t)0x00000008)
00130 #define RTC_BKP_DR9                       ((uint32_t)0x00000009)
00131 #define RTC_BKP_DR10                      ((uint32_t)0x0000000A)
00132 #define RTC_BKP_DR11                      ((uint32_t)0x0000000B)
00133 #define RTC_BKP_DR12                      ((uint32_t)0x0000000C)
00134 #define RTC_BKP_DR13                      ((uint32_t)0x0000000D)
00135 #define RTC_BKP_DR14                      ((uint32_t)0x0000000E)
00136 #define RTC_BKP_DR15                      ((uint32_t)0x0000000F)
00137 #define RTC_BKP_DR16                      ((uint32_t)0x00000010)
00138 #define RTC_BKP_DR17                      ((uint32_t)0x00000011)
00139 #define RTC_BKP_DR18                      ((uint32_t)0x00000012)
00140 #define RTC_BKP_DR19                      ((uint32_t)0x00000013)
00141 #define RTC_BKP_DR20                      ((uint32_t)0x00000014)
00142 #define RTC_BKP_DR21                      ((uint32_t)0x00000015)
00143 #define RTC_BKP_DR22                      ((uint32_t)0x00000016)
00144 #define RTC_BKP_DR23                      ((uint32_t)0x00000017)
00145 #define RTC_BKP_DR24                      ((uint32_t)0x00000018)
00146 #define RTC_BKP_DR25                      ((uint32_t)0x00000019)
00147 #define RTC_BKP_DR26                      ((uint32_t)0x0000001A)
00148 #define RTC_BKP_DR27                      ((uint32_t)0x0000001B)
00149 #define RTC_BKP_DR28                      ((uint32_t)0x0000001C)
00150 #define RTC_BKP_DR29                      ((uint32_t)0x0000001D)
00151 #define RTC_BKP_DR30                      ((uint32_t)0x0000001E)
00152 #define RTC_BKP_DR31                      ((uint32_t)0x0000001F)
00153 /**
00154   * @}
00155   */
00156
00157 /** @defgroup RTCEx_TimeStamp_Edges_definitions RTC TimeStamp Edges Definitions
00158   *
00159   * @{
00160   */
00161 #define RTC_TIMESTAMPEDGE_RISING            ((uint32_t)0x00000000)
00162 #define RTC_TIMESTAMPEDGE_FALLING           ((uint32_t)0x00000008)
00163
00164 /**
00165   * @}
00166   */
00167
00168 /** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection
00169   * @{
00170   */
00171 #define RTC_TIMESTAMPPIN_DEFAULT              ((uint32_t)0x00000000)
00172 /**
00173   * @}
00174   */
00175
00176 /** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions
00177   * @{
00178   */
00179 #define RTC_TAMPER_1                       RTC_TAMPCR_TAMP1E
00180 #define RTC_TAMPER_2                       RTC_TAMPCR_TAMP2E
00181 #define RTC_TAMPER_3                       RTC_TAMPCR_TAMP3E
00182 /**
00183   * @}
00184   */
00185
00186 /** @defgroup RTCEx_Tamper_Interrupt_Definitions RTC Tamper Interrupts Definitions
00187   * @{
00188   */
00189 #define RTC_TAMPER1_INTERRUPT              RTC_TAMPCR_TAMP1IE
00190 #define RTC_TAMPER2_INTERRUPT              RTC_TAMPCR_TAMP2IE
00191 #define RTC_TAMPER3_INTERRUPT              RTC_TAMPCR_TAMP3IE
00192 #define RTC_ALL_TAMPER_INTERRUPT           RTC_TAMPCR_TAMPIE
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions
00198   * @{
00199   */
00200 #define RTC_TAMPERTRIGGER_RISINGEDGE          ((uint32_t)0x00000000)
00201 #define RTC_TAMPERTRIGGER_FALLINGEDGE         ((uint32_t)0x00000002)
00202 #define RTC_TAMPERTRIGGER_LOWLEVEL            RTC_TAMPERTRIGGER_RISINGEDGE
00203 #define RTC_TAMPERTRIGGER_HIGHLEVEL           RTC_TAMPERTRIGGER_FALLINGEDGE
00204
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTC Tamper EraseBackUp Definitions
00210 * @{
00211 */
00212 #define RTC_TAMPER_ERASE_BACKUP_ENABLE     ((uint32_t)0x00000000)
00213 #define RTC_TAMPER_ERASE_BACKUP_DISABLE    ((uint32_t)0x00020000)
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTC Tamper Mask Flag Definitions
00219 * @{
00220 */
00221 #define RTC_TAMPERMASK_FLAG_DISABLE        ((uint32_t)0x00000000)
00222 #define RTC_TAMPERMASK_FLAG_ENABLE         ((uint32_t)0x00040000)
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup RTCEx_Tamper_Filter_Definitions RTC Tamper Filter Definitions
00228   * @{
00229   */
00230 #define RTC_TAMPERFILTER_DISABLE   ((uint32_t)0x00000000)  /*!< Tamper filter is disabled */
00231
00232 #define RTC_TAMPERFILTER_2SAMPLE   ((uint32_t)0x00000800)  /*!< Tamper is activated after 2
00233                                                                 consecutive samples at the active level */
00234 #define RTC_TAMPERFILTER_4SAMPLE   ((uint32_t)0x00001000)  /*!< Tamper is activated after 4
00235                                                                 consecutive samples at the active level */
00236 #define RTC_TAMPERFILTER_8SAMPLE   ((uint32_t)0x00001800)  /*!< Tamper is activated after 8
00237                                                                 consecutive samples at the active level. */
00238 /**
00239   * @}
00240   */
00241
00242 /** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Tamper Sampling Frequencies Definitions
00243   * @{
00244   */
00245 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  ((uint32_t)0x00000000)  /*!< Each of the tamper inputs are sampled
00246                                                                              with a frequency =  RTCCLK / 32768 */
00247 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  ((uint32_t)0x00000100)  /*!< Each of the tamper inputs are sampled
00248                                                                              with a frequency =  RTCCLK / 16384 */
00249 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   ((uint32_t)0x00000200)  /*!< Each of the tamper inputs are sampled
00250                                                                              with a frequency =  RTCCLK / 8192  */
00251 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   ((uint32_t)0x00000300)  /*!< Each of the tamper inputs are sampled
00252                                                                              with a frequency =  RTCCLK / 4096  */
00253 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   ((uint32_t)0x00000400)  /*!< Each of the tamper inputs are sampled
00254                                                                              with a frequency =  RTCCLK / 2048  */
00255 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   ((uint32_t)0x00000500)  /*!< Each of the tamper inputs are sampled
00256                                                                              with a frequency =  RTCCLK / 1024  */
00257 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    ((uint32_t)0x00000600)  /*!< Each of the tamper inputs are sampled
00258                                                                              with a frequency =  RTCCLK / 512   */
00259 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    ((uint32_t)0x00000700)  /*!< Each of the tamper inputs are sampled
00260                                                                              with a frequency =  RTCCLK / 256   */
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Tamper Pin Precharge Duration Definitions
00266   * @{
00267   */
00268 #define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000)  /*!< Tamper pins are pre-charged before
00269                                                                          sampling during 1 RTCCLK cycle  */
00270 #define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000)  /*!< Tamper pins are pre-charged before
00271                                                                          sampling during 2 RTCCLK cycles */
00272 #define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000)  /*!< Tamper pins are pre-charged before
00273                                                                          sampling during 4 RTCCLK cycles */
00274 #define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000)  /*!< Tamper pins are pre-charged before
00275                                                                          sampling during 8 RTCCLK cycles */
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Tamper TimeStamp On Tamper Detection Definitions
00281   * @{
00282   */
00283 #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE  ((uint32_t)RTC_TAMPCR_TAMPTS)  /*!< TimeStamp on Tamper Detection event saved        */
00284 #define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000)         /*!< TimeStamp on Tamper Detection event is not saved */
00285 /**
00286   * @}
00287   */
00288
00289 /** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Tamper Pull Up Definitions
00290   * @{
00291   */
00292 #define RTC_TAMPER_PULLUP_ENABLE  ((uint32_t)0x00000000)              /*!< TimeStamp on Tamper Detection event saved        */
00293 #define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS)    /*!< TimeStamp on Tamper Detection event is not saved */
00294 /**
00295   * @}
00296   */
00297
00298 /** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wakeup Timer Definitions
00299   * @{
00300   */
00301 #define RTC_WAKEUPCLOCK_RTCCLK_DIV16        ((uint32_t)0x00000000)
00302 #define RTC_WAKEUPCLOCK_RTCCLK_DIV8         ((uint32_t)0x00000001)
00303 #define RTC_WAKEUPCLOCK_RTCCLK_DIV4         ((uint32_t)0x00000002)
00304 #define RTC_WAKEUPCLOCK_RTCCLK_DIV2         ((uint32_t)0x00000003)
00305 #define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      ((uint32_t)0x00000004)
00306 #define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      ((uint32_t)0x00000006)
00307 /**
00308   * @}
00309   */
00310
00311 /** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Smooth Calib Period Definitions
00312   * @{
00313   */
00314 #define RTC_SMOOTHCALIB_PERIOD_32SEC   ((uint32_t)0x00000000)  /*!< If RTCCLK = 32768 Hz, Smooth calibration
00315                                                                     period is 32s,  else 2exp20 RTCCLK seconds */
00316 #define RTC_SMOOTHCALIB_PERIOD_16SEC   ((uint32_t)0x00002000)  /*!< If RTCCLK = 32768 Hz, Smooth calibration
00317                                                                     period is 16s, else 2exp19 RTCCLK seconds */
00318 #define RTC_SMOOTHCALIB_PERIOD_8SEC    ((uint32_t)0x00004000)  /*!< If RTCCLK = 32768 Hz, Smooth calibration
00319                                                                     period is 8s, else 2exp18 RTCCLK seconds */
00320 /**
00321   * @}
00322   */
00323
00324 /** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Smooth Calib Plus Pulses Definitions
00325   * @{
00326   */
00327 #define RTC_SMOOTHCALIB_PLUSPULSES_SET    ((uint32_t)0x00008000)  /*!< The number of RTCCLK pulses added
00328                                                                        during a X -second window = Y - CALM[8:0]
00329                                                                        with Y = 512, 256, 128 when X = 32, 16, 8 */
00330 #define RTC_SMOOTHCALIB_PLUSPULSES_RESET  ((uint32_t)0x00000000)  /*!< The number of RTCCLK pulses subbstited
00331                                                                        during a 32-second window = CALM[8:0] */
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Calib Output Selection Definitions
00337   * @{
00338   */
00339 #define RTC_CALIBOUTPUT_512HZ            ((uint32_t)0x00000000)
00340 #define RTC_CALIBOUTPUT_1HZ              ((uint32_t)0x00080000)
00341 /**
00342   * @}
00343   */
00344
00345 /** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTC Add 1 Second Parameter Definitions
00346   * @{
00347   */
00348 #define RTC_SHIFTADD1S_RESET      ((uint32_t)0x00000000)
00349 #define RTC_SHIFTADD1S_SET        ((uint32_t)0x80000000)
00350 /**
00351   * @}
00352   */
00353
00354 /**
00355   * @}
00356   */
00357
00358 /* Exported macros -----------------------------------------------------------*/
00359 /** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
00360   * @{
00361   */
00362
00363 /**
00364   * @brief  Enable the RTC WakeUp Timer peripheral.
00365   * @param  __HANDLE__: specifies the RTC handle.
00366   * @retval None
00367   */
00368 #define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
00369
00370 /**
00371   * @brief  Disable the RTC WakeUp Timer peripheral.
00372   * @param  __HANDLE__: specifies the RTC handle.
00373   * @retval None
00374   */
00375 #define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                    ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
00376
00377 /**
00378   * @brief  Enable the RTC WakeUpTimer interrupt.
00379   * @param  __HANDLE__: specifies the RTC handle.
00380   * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled.
00381   *         This parameter can be:
00382   *            @arg RTC_IT_WUT: WakeUpTimer interrupt
00383   * @retval None
00384   */
00385 #define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00386
00387 /**
00388   * @brief  Disable the RTC WakeUpTimer interrupt.
00389   * @param  __HANDLE__: specifies the RTC handle.
00390   * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be disabled.
00391   *         This parameter can be:
00392   *            @arg RTC_IT_WUT: WakeUpTimer interrupt
00393   * @retval None
00394   */
00395 #define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00396
00397 /**
00398   * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
00399   * @param  __HANDLE__: specifies the RTC handle.
00400   * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to check.
00401   *         This parameter can be:
00402   *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
00403   * @retval None
00404   */
00405 #define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
00406
00407 /**
00408   * @brief  Check whether the specified RTC Wake Up timer interrupt is enabled or not.
00409   * @param  __HANDLE__: specifies the RTC handle.
00410   * @param  __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check.
00411   *         This parameter can be:
00412   *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
00413   * @retval None
00414   */
00415 #define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
00416
00417 /**
00418   * @brief  Get the selected RTC WakeUpTimer's flag status.
00419   * @param  __HANDLE__: specifies the RTC handle.
00420   * @param  __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not.
00421   *          This parameter can be:
00422   *             @arg RTC_FLAG_WUTF
00423   *             @arg RTC_FLAG_WUTWF
00424   * @retval None
00425   */
00426 #define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
00427
00428 /**
00429   * @brief  Clear the RTC Wake Up timer's pending flags.
00430   * @param  __HANDLE__: specifies the RTC handle.
00431   * @param  __FLAG__: specifies the RTC WakeUpTimer Flag to clear.
00432   *         This parameter can be:
00433   *            @arg RTC_FLAG_WUTF
00434   * @retval None
00435   */
00436 #define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00437
00438 /**
00439   * @brief  Enable the RTC Tamper1 input detection.
00440   * @param  __HANDLE__: specifies the RTC handle.
00441   * @retval None
00442   */
00443 #define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))
00444
00445 /**
00446   * @brief  Disable the RTC Tamper1 input detection.
00447   * @param  __HANDLE__: specifies the RTC handle.
00448   * @retval None
00449   */
00450 #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
00451
00452 /**
00453   * @brief  Enable the RTC Tamper2 input detection.
00454   * @param  __HANDLE__: specifies the RTC handle.
00455   * @retval None
00456   */
00457 #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))
00458
00459 /**
00460   * @brief  Disable the RTC Tamper2 input detection.
00461   * @param  __HANDLE__: specifies the RTC handle.
00462   * @retval None
00463   */
00464 #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
00465
00466 /**
00467   * @brief  Enable the RTC Tamper3 input detection.
00468   * @param  __HANDLE__: specifies the RTC handle.
00469   * @retval None
00470   */
00471 #define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))
00472
00473 /**
00474   * @brief  Disable the RTC Tamper3 input detection.
00475   * @param  __HANDLE__: specifies the RTC handle.
00476   * @retval None
00477   */
00478 #define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
00479
00480 /**
00481   * @brief  Enable the RTC Tamper interrupt.
00482   * @param  __HANDLE__: specifies the RTC handle.
00483   * @param  __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled.
00484   *          This parameter can be any combination of the following values:
00485   *             @arg  RTC_IT_TAMP: All tampers interrupts
00486   *             @arg  RTC_IT_TAMP1: Tamper1 interrupt
00487   *             @arg  RTC_IT_TAMP2: Tamper2 interrupt
00488   *             @arg  RTC_IT_TAMP3: Tamper3 interrupt
00489   * @retval None
00490   */
00491 #define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
00492
00493 /**
00494   * @brief  Disable the RTC Tamper interrupt.
00495   * @param  __HANDLE__: specifies the RTC handle.
00496   * @param  __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled.
00497   *         This parameter can be any combination of the following values:
00498   *            @arg  RTC_IT_TAMP: All tampers interrupts
00499   *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
00500   *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
00501   *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
00502   * @retval None
00503   */
00504 #define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)       ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
00505
00506 /**
00507   * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
00508   * @param  __HANDLE__: specifies the RTC handle.
00509   * @param  __INTERRUPT__: specifies the RTC Tamper interrupt to check.
00510   *         This parameter can be:
00511   *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
00512   *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
00513   *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
00514   * @retval None
00515   */
00516 #define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)           (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \
00517                                                                       ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \
00518                                                                       (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))
00519
00520 /**
00521   * @brief  Check whether the specified RTC Tamper interrupt is enabled or not.
00522   * @param  __HANDLE__: specifies the RTC handle.
00523   * @param  __INTERRUPT__: specifies the RTC Tamper interrupt source to check.
00524   *         This parameter can be:
00525   *            @arg  RTC_IT_TAMP: All tampers interrupts
00526   *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
00527   *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
00528   *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
00529   * @retval None
00530   */
00531 #define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
00532
00533 /**
00534   * @brief  Get the selected RTC Tamper's flag status.
00535   * @param  __HANDLE__: specifies the RTC handle.
00536   * @param  __FLAG__: specifies the RTC Tamper Flag is pending or not.
00537   *          This parameter can be:
00538   *             @arg RTC_FLAG_TAMP1F: Tamper1 flag
00539   *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
00540   *             @arg RTC_FLAG_TAMP3F: Tamper3 flag
00541   * @retval None
00542   */
00543 #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)        (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
00544
00545 /**
00546   * @brief  Clear the RTC Tamper's pending flags.
00547   * @param  __HANDLE__: specifies the RTC handle.
00548   * @param  __FLAG__: specifies the RTC Tamper Flag sources to clear.
00549   *          This parameter can be:
00550   *             @arg RTC_FLAG_TAMP1F: Tamper1 flag
00551   *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
00552   *             @arg RTC_FLAG_TAMP3F: Tamper3 flag
00553   * @retval None
00554   */
00555 #define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00556
00557 /**
00558   * @brief  Enable the RTC TimeStamp peripheral.
00559   * @param  __HANDLE__: specifies the RTC handle.
00560   * @retval None
00561   */
00562 #define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
00563
00564 /**
00565   * @brief  Disable the RTC TimeStamp peripheral.
00566   * @param  __HANDLE__: specifies the RTC handle.
00567   * @retval None
00568   */
00569 #define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
00570
00571 /**
00572   * @brief  Enable the RTC TimeStamp interrupt.
00573   * @param  __HANDLE__: specifies the RTC handle.
00574   * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be enabled.
00575   *         This parameter can be:
00576   *            @arg RTC_IT_TS: TimeStamp interrupt
00577   * @retval None
00578   */
00579 #define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00580
00581 /**
00582   * @brief  Disable the RTC TimeStamp interrupt.
00583   * @param  __HANDLE__: specifies the RTC handle.
00584   * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be disabled.
00585   *         This parameter can be:
00586   *            @arg RTC_IT_TS: TimeStamp interrupt
00587   * @retval None
00588   */
00589 #define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00590
00591 /**
00592   * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
00593   * @param  __HANDLE__: specifies the RTC handle.
00594   * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt source to check.
00595   *         This parameter can be:
00596   *            @arg RTC_IT_TS: TimeStamp interrupt
00597   * @retval None
00598   */
00599 #define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)        (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
00600
00601 /**
00602   * @brief  Check whether the specified RTC Time Stamp interrupt is enabled or not.
00603   * @param  __HANDLE__: specifies the RTC handle.
00604   * @param  __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check.
00605   *         This parameter can be:
00606   *            @arg RTC_IT_TS: TimeStamp interrupt
00607   * @retval None
00608   */
00609 #define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
00610
00611 /**
00612   * @brief  Get the selected RTC TimeStamp's flag status.
00613   * @param  __HANDLE__: specifies the RTC handle.
00614   * @param  __FLAG__: specifies the RTC TimeStamp Flag is pending or not.
00615   *         This parameter can be:
00616   *            @arg RTC_FLAG_TSF
00617   *            @arg RTC_FLAG_TSOVF
00618   * @retval None
00619   */
00620 #define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)     (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
00621
00622 /**
00623   * @brief  Clear the RTC Time Stamp's pending flags.
00624   * @param  __HANDLE__: specifies the RTC handle.
00625   * @param  __FLAG__: specifies the RTC Alarm Flag sources to clear.
00626   *          This parameter can be:
00627   *             @arg RTC_FLAG_TSF
00628   *             @arg RTC_FLAG_TSOVF
00629   * @retval None
00630   */
00631 #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00632
00633 /**
00634   * @brief  Enable the RTC internal TimeStamp peripheral.
00635   * @param  __HANDLE__: specifies the RTC handle.
00636   * @retval None
00637   */
00638 #define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
00639
00640 /**
00641   * @brief  Disable the RTC internal TimeStamp peripheral.
00642   * @param  __HANDLE__: specifies the RTC handle.
00643   * @retval None
00644   */
00645 #define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
00646
00647 /**
00648   * @brief  Get the selected RTC Internal Time Stamp's flag status.
00649   * @param  __HANDLE__: specifies the RTC handle.
00650   * @param  __FLAG__: specifies the RTC Internal Time Stamp Flag is pending or not.
00651   *         This parameter can be:
00652   *            @arg RTC_FLAG_ITSF
00653   * @retval None
00654   */
00655 #define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)    (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
00656
00657 /**
00658   * @brief  Clear the RTC Internal Time Stamp's pending flags.
00659   * @param  __HANDLE__: specifies the RTC handle.
00660   * @param  __FLAG__: specifies the RTC Internal Time Stamp Flag source to clear.
00661   *          This parameter can be:
00662   *             @arg RTC_FLAG_ITSF
00663   * @retval None
00664   */
00665 #define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00666
00667 /**
00668   * @brief  Enable the RTC calibration output.
00669   * @param  __HANDLE__: specifies the RTC handle.
00670   * @retval None
00671   */
00672 #define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
00673
00674 /**
00675   * @brief  Disable the calibration output.
00676   * @param  __HANDLE__: specifies the RTC handle.
00677   * @retval None
00678   */
00679 #define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
00680
00681 /**
00682   * @brief  Enable the clock reference detection.
00683   * @param  __HANDLE__: specifies the RTC handle.
00684   * @retval None
00685   */
00686 #define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
00687
00688 /**
00689   * @brief  Disable the clock reference detection.
00690   * @param  __HANDLE__: specifies the RTC handle.
00691   * @retval None
00692   */
00693 #define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
00694
00695 /**
00696   * @brief  Get the selected RTC shift operation's flag status.
00697   * @param  __HANDLE__: specifies the RTC handle.
00698   * @param  __FLAG__: specifies the RTC shift operation Flag is pending or not.
00699   *          This parameter can be:
00700   *             @arg RTC_FLAG_SHPF
00701   * @retval None
00702   */
00703 #define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)         (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
00704
00705 /**
00706   * @brief  Enable interrupt on the RTC WakeUp Timer associated Exti line.
00707   * @retval None
00708   */
00709 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI_D1->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00710
00711 /**
00712   * @brief  Disable interrupt on the RTC WakeUp Timer associated Exti line.
00713   * @retval None
00714   */
00715 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00716
00717 /**
00718   * @brief  Enable event on the RTC WakeUp Timer associated Exti line.
00719   * @retval None
00720   */
00721 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI_D1->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00722
00723 /**
00724   * @brief  Disable event on the RTC WakeUp Timer associated Exti line.
00725   * @retval None
00726   */
00727 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00728 /**
00729   * @brief  Enable event on the RTC WakeUp Timer associated D3 Exti line.
00730   * @retval None
00731   */
00732 #define __HAL_RTC_WAKEUPTIMER_EXTID3_ENABLE_EVENT()    (EXTI->D3PMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00733
00734 /**
00735   * @brief  Disable event on the RTC WakeUp Timer associated D3 Exti line.
00736   * @retval None
00737   */
00738 #define __HAL_RTC_WAKEUPTIMER_EXTID3_DISABLE_EVENT()   (EXTI->D3PMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00739
00740 /**
00741   * @brief  Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
00742   * @retval None
00743   */
00744 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00745
00746 /**
00747   * @brief  Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
00748   * @retval None
00749   */
00750 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00751
00752 /**
00753   * @brief  Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
00754   * @retval None
00755   */
00756 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00757
00758 /**
00759   * @brief  Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
00760   * @retval None
00761   */
00762 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00763
00764 /**
00765   * @brief  Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
00766   * @retval None
00767   */
00768 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
00769                                                                    __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();  \
00770                                                                    __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \
00771                                                                  } while(0)
00772 /**
00773   * @brief  Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
00774   * This parameter can be:
00775   * @retval None
00776   */
00777 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
00778                                                                    __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();  \
00779                                                                    __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \
00780                                                                   } while(0)
00781 /**
00782   * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
00783   * @retval Line Status.
00784   */
00785 #define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI_D1->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00786
00787 /**
00788   * @brief Clear the RTC WakeUp Timer associated Exti line flag.
00789   * @retval None
00790   */
00791 #define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI_D1->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00792
00793 /**
00794   * @brief  Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
00795   * @retval None
00796   */
00797 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI_D1->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00798
00799 /**
00800   * @brief  Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
00801   * @retval None
00802   */
00803 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00804
00805 /**
00806   * @brief  Enable event on the RTC Tamper and Timestamp associated Exti line.
00807   * @retval None
00808   */
00809 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT()    (EXTI_D1->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00810
00811 /**
00812   * @brief  Disable event on the RTC Tamper and Timestamp associated Exti line.
00813   * @retval None
00814   */
00815 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00816
00817 /**
00818   * @brief Check whether the RTC WakeUp Timer associated D3 Exti line interrupt flag is set or not.
00819   * @retval Line Status
00820   */
00821 #define __HAL_RTC_WAKEUPTIMER_EXTID3_GET_FLAG()            (EXTI_D3->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00822
00823 /**
00824   * @brief Clear the RTC WakeUp Timer associated D3 Exti line flag.
00825   * @retval None.
00826   */
00827 #define __HAL_RTC_WAKEUPTIMER_EXTID3_CLEAR_FLAG()          (EXTI_D3->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00828
00829 /**
00830   * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
00831   * @retval None.
00832   */
00833 #define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT()         (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00834
00835
00836 /**
00837   * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00838   * @retval None
00839   */
00840 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00841
00842 /**
00843   * @brief  Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00844   * @retval None
00845   */
00846 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00847
00848 /**
00849   * @brief  Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
00850   * @retval None
00851   */
00852 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00853
00854 /**
00855   * @brief  Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
00856   * @retval None
00857   */
00858 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00859
00860 /**
00861   * @brief  Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00862   * @retval None
00863   */
00864 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
00865                                                                         __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();  \
00866                                                                         __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
00867                                                                       } while(0)
00868 /**
00869   * @brief  Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00870   * @retval None
00871   */
00872 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
00873                                                                         __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();  \
00874                                                                         __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \
00875                                                                        } while(0)
00876 /**
00877   * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
00878   * @retval Line Status
00879   */
00880 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()         (EXTI_D1->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00881
00882 /**
00883   * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
00884   * @retval None
00885   */
00886 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()       (EXTI_D1->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00887
00888 /**
00889   * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
00890   * @retval None
00891   */
00892 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()    (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00893
00894 /**
00895   * @}
00896   */
00897
00898 /* Exported functions --------------------------------------------------------*/
00899 /** @addtogroup RTCEx_Exported_Functions
00900   * @{
00901   */
00902
00903 /* RTC TimeStamp and Tamper functions *****************************************/
00904 /** @addtogroup RTCEx_Exported_Functions_Group1
00905   * @{
00906   */
00907 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
00908 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
00909 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
00910 HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc);
00911 HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc);
00912 HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
00913 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
00914 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
00915 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
00916
00917 void              HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
00918 void              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
00919 void              HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
00920 void              HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
00921 void              HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
00922
00923
00924 HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00925 HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00926 HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00927 HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00928 /**
00929   * @}
00930   */
00931
00932 /* RTC Wake-up functions ******************************************************/
00933 /** @addtogroup RTCEx_Exported_Functions_Group2
00934   * @{
00935   */
00936 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
00937 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
00938 uint32_t          HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
00939 uint32_t          HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
00940 void              HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
00941 void              HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
00942 HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00943 /**
00944   * @}
00945   */
00946
00947 /* Extended Control functions ************************************************/
00948 /** @addtogroup RTCEx_Exported_Functions_Group3
00949   * @{
00950   */
00951 void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
00952 uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
00953
00954 HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
00955 HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
00956 HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
00957 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
00958 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
00959 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
00960 HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
00961 HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
00962 /**
00963   * @}
00964   */
00965
00966 /* Extended RTC features functions *******************************************/
00967 /** @addtogroup RTCEx_Exported_Functions_Group4
00968   * @{
00969   */
00970 void              HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
00971 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00972 /**
00973   * @}
00974   */
00975
00976 /**
00977   * @}
00978   */
00979
00980 /* Private types -------------------------------------------------------------*/
00981 /* Private variables ---------------------------------------------------------*/
00982 /* Private constants ---------------------------------------------------------*/
00983 /** @defgroup RTCEx_Private_Constants RTCEx Private Constants
00984   * @{
00985   */
00986 #define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  ((uint32_t)0x00040000)  /*!< External interrupt line 18 Connected to the RTC Tamper and Time Stamp events */
00987 #define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       ((uint32_t)0x00080000)  /*!< External interrupt line 19 Connected to the RTC Wakeup event */
00988
00989 /* Masks Definition */
00990 #define RTC_TAMPCR_TAMPXE     ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))
00991 #define RTC_TAMPCR_TAMPXIE    ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))
00992
00993 /**
00994   * @}
00995   */
00996
00997 /* Private macros ------------------------------------------------------------*/
00998 /** @defgroup RTCEx_Private_Macros RTCEx Private Macros
00999   * @{
01000   */
01001
01002 /** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
01003   * @{
01004   */
01005
01006 #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE)     || \
01007                                ((OUTPUT) == RTC_OUTPUT_ALARMA)      || \
01008                                ((OUTPUT) == RTC_OUTPUT_ALARMB)      || \
01009                                ((OUTPUT) == RTC_OUTPUT_WAKEUP))
01010
01011 #define IS_RTC_BKP(BKP)                   ((BKP) < (uint32_t) RTC_BKP_NUMBER)
01012
01013 #define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
01014                                  ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
01015
01016 #define IS_RTC_TAMPER(__TAMPER__)   ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXE))) == 0x00U) && ((__TAMPER__) != (uint32_t)RESET))
01017
01018 #define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__)  ((((__INTERRUPT__) & (uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXIE)) == 0x00U) && ((__INTERRUPT__) != (uint32_t)RESET))
01019
01020 #define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
01021
01022 #define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE)    || \
01023                                         ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE)   || \
01024                                         ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL)      || \
01025                                         ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
01026
01027 #define IS_RTC_TAMPER_ERASE_MODE(MODE)             (((MODE) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
01028                                                     ((MODE) == RTC_TAMPER_ERASE_BACKUP_DISABLE))
01029
01030 #define IS_RTC_TAMPER_MASKFLAG_STATE(STATE)        (((STATE) == RTC_TAMPERMASK_FLAG_ENABLE) || \
01031                                                     ((STATE) == RTC_TAMPERMASK_FLAG_DISABLE))
01032
01033 #define IS_RTC_TAMPER_FILTER(FILTER)  (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
01034                                        ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
01035                                        ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
01036                                        ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
01037
01038 #define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
01039                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
01040                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
01041                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
01042                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
01043                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
01044                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
01045                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
01046
01047 #define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
01048                                                     ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
01049                                                     ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
01050                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
01051
01052 #define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
01053                                                               ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
01054
01055 #define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
01056                                            ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
01057
01058 #define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)       || \
01059                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
01060                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
01061                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
01062                                     ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
01063                                     ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
01064
01065 #define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFF)
01066
01067 #define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
01068                                             ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
01069                                             ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
01070
01071 #define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
01072                                         ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
01073
01074 #define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
01075
01076 #define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
01077                                  ((SEL) == RTC_SHIFTADD1S_SET))
01078
01079 #define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
01080
01081 #define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
01082                                       ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
01083
01084 /**
01085   * @}
01086   */
01087
01088 /**
01089   * @}
01090   */
01091
01092 /**
01093   * @}
01094   */
01095
01096 /**
01097   * @}
01098   */
01099
01100 #ifdef __cplusplus
01101 }
01102 #endif
01103
01104 #endif /* __STM32H7xx_HAL_RTC_EX_H */
01105
01106 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sai.c Source File

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stm32h7xx_hal_sai.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sai.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   SAI HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Serial Audio Interface (SAI) peripheral:
00010   *           + Initialization/de-initialization functions
00011   *           + I/O operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                   ##### How to use this driver #####
00018   ==============================================================================
00019
00020   [..]
00021     The SAI HAL driver can be used as follows:
00022
00023     (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai).
00024     (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
00025         (##) Enable the SAI interface clock.
00026         (##) SAI pins configuration:
00027             (+++) Enable the clock for the SAI GPIOs.
00028             (+++) Configure these SAI pins as alternate function pull-up.
00029         (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()
00030              and HAL_SAI_Receive_IT() APIs):
00031             (+++) Configure the SAI interrupt priority.
00032             (+++) Enable the NVIC SAI IRQ handle.
00033
00034         (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()
00035              and HAL_SAI_Receive_DMA() APIs):
00036             (+++) Declare a DMA handle structure for the Tx/Rx stream.
00037             (+++) Enable the DMAx interface clock.
00038             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00039             (+++) Configure the DMA Tx/Rx Stream.
00040             (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
00041             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
00042                 DMA Tx/Rx Stream.
00043
00044     (#) The initialization can be done by two ways
00045         (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init().
00046         (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol().
00047
00048   [..]
00049     (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
00050         will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT()
00051         inside the transmit and receive process.
00052   [..]
00053     (@) Make sure that either:
00054         (+@) PLLSAI1CLK output is configured or
00055         (+@) PLLSAI2CLK output is configured or
00056         (+@) PLLSAI3CLK output is configured or
00057     (+@) PLLSAI4ACLK output is configured or
00058     (+@) PLLSAI4BCLK output is configured or
00059     (+@) External clock source is configured after setting correctly
00060              the define constant EXTERNAL_CLOCK_VALUE in the stm32h7xx_hal_conf.h file.
00061
00062   [..]
00063     (@) In master Tx mode: enabling the audio block immediately generates the bit clock
00064         for the external slaves even if there is no data in the FIFO, However FS signal
00065         generation is conditioned by the presence of data in the FIFO.
00066
00067   [..]
00068     (@) In master Rx mode: enabling the audio block immediately generates the bit clock
00069         and FS signal for the external slaves.
00070
00071   [..]
00072     (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
00073         (+@) First bit Offset <= (SLOT size - Data size)
00074         (+@) Data size <= SLOT size
00075         (+@) Number of SLOT x SLOT size = Frame length
00076         (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.
00077
00078   [..]
00079     (@) PDM interface can be activated through HAL_SAI_Init function.
00080         Please note that PDM interface is only available for SAIx sub-block A.
00081         PDM microphone delays can be tuned with HAL_SAIEx_ConfigPdmMicDelay function.
00082
00083   [..]
00084     Three operation modes are available within this driver :
00085
00086     *** Polling mode IO operation ***
00087     =================================
00088     [..]
00089       (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()
00090       (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()
00091
00092     *** Interrupt mode IO operation ***
00093     ===================================
00094     [..]
00095       (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT()
00096       (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
00097           add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
00098       (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT()
00099       (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
00100           add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
00101       (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
00102           add his own code by customization of function pointer HAL_SAI_ErrorCallback()
00103
00104     *** DMA mode IO operation ***
00105     =============================
00106     [..]
00107       (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA()
00108       (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
00109           add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
00110       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA()
00111       (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
00112           add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
00113       (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
00114           add his own code by customization of function pointer HAL_SAI_ErrorCallback()
00115       (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
00116       (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
00117       (+) Stop the DMA Transfer using HAL_SAI_DMAStop()
00118
00119     *** SAI HAL driver additional function list ***
00120     ===============================================
00121     [..]
00122       Below the list the others API available SAI HAL driver :
00123
00124       (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode
00125       (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode
00126       (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode
00127       (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode
00128       (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo.
00129       (+) HAL_SAI_Abort(): Abort the current transfer
00130
00131     *** SAI HAL driver macros list ***
00132     ==================================
00133     [..]
00134       Below the list of most used macros in SAI HAL driver :
00135
00136       (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral
00137       (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral
00138       (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts
00139       (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts
00140       (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is
00141           enabled or disabled
00142       (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not
00143
00144   @endverbatim
00145   ******************************************************************************
00146   * @attention
00147   *
00148   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00149   *
00150   * Redistribution and use in source and binary forms, with or without modification,
00151   * are permitted provided that the following conditions are met:
00152   *   1. Redistributions of source code must retain the above copyright notice,
00153   *      this list of conditions and the following disclaimer.
00154   *   2. Redistributions in binary form must reproduce the above copyright notice,
00155   *      this list of conditions and the following disclaimer in the documentation
00156   *      and/or other materials provided with the distribution.
00157   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00158   *      may be used to endorse or promote products derived from this software
00159   *      without specific prior written permission.
00160   *
00161   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00162   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00163   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00164   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00165   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00166   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00167   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00168   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00169   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00170   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00171   *
00172   ******************************************************************************
00173   */
00174
00175 /* Includes ------------------------------------------------------------------*/
00176 #include "stm32h7xx_hal.h"
00177
00178 /** @addtogroup STM32H7xx_HAL_Driver
00179   * @{
00180   */
00181
00182 /** @defgroup SAI SAI
00183   * @brief SAI HAL module driver
00184   * @{
00185   */
00186
00187 #ifdef HAL_SAI_MODULE_ENABLED
00188
00189 /* Private typedef -----------------------------------------------------------*/
00190
00191 /** @defgroup SAI_Private_Typedefs  SAI Private Typedefs
00192   * @{
00193   */
00194 typedef enum {
00195   SAI_MODE_DMA,
00196   SAI_MODE_IT
00197 } SAI_ModeTypedef;
00198 /**
00199   * @}
00200   */
00201
00202 /* Private define ------------------------------------------------------------*/
00203
00204 /** @defgroup SAI_Private_Constants  SAI Private Constants
00205   * @{
00206   */
00207 #define SAI_FIFO_SIZE            8U
00208 #define SAI_DEFAULT_TIMEOUT      4U /* 4ms */
00209 #define SAI_LONG_TIMEOUT         1000U
00210 #define SAI_xCR2_MUTECNT_OFFSET  POSITION_VAL(SAI_xCR2_MUTECNT)
00211 #define SAI_PDMCR_MICNBR_OFFSET  POSITION_VAL(SAI_PDMCR_MICNBR)
00212 /**
00213   * @}
00214   */
00215
00216 /* Private macro -------------------------------------------------------------*/
00217 /* Private variables ---------------------------------------------------------*/
00218 /* Private function prototypes -----------------------------------------------*/
00219
00220 /** @defgroup SAI_Private_Functions  SAI Private Functions
00221   * @{
00222   */
00223 static void SAI_FillFifo(SAI_HandleTypeDef *hsai);
00224 static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode);
00225 static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
00226 static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
00227
00228 static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai);
00229 static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai);
00230 static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai);
00231 static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai);
00232 static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai);
00233 static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai);
00234 static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai);
00235
00236 static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma);
00237 static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00238 static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma);
00239 static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00240 static void SAI_DMAError(DMA_HandleTypeDef *hdma);
00241 static void SAI_DMAAbort(DMA_HandleTypeDef *hdma);
00242 /**
00243   * @}
00244   */
00245
00246 /* Exported functions ---------------------------------------------------------*/
00247
00248 /** @defgroup SAI_Exported_Functions SAI Exported Functions
00249   * @{
00250   */
00251
00252 /** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions
00253  *  @brief    Initialization and Configuration functions
00254  *
00255 @verbatim
00256  ===============================================================================
00257              ##### Initialization and de-initialization functions #####
00258  ===============================================================================
00259   [..]  This subsection provides a set of functions allowing to initialize and
00260         de-initialize the SAIx peripheral:
00261
00262       (+) User must implement HAL_SAI_MspInit() function in which he configures
00263           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00264
00265       (+) Call the function HAL_SAI_Init() to configure the selected device with
00266           the selected configuration:
00267         (++) Mode (Master/slave TX/RX)
00268         (++) Protocol
00269         (++) Data Size
00270         (++) MCLK Output
00271         (++) Audio frequency
00272         (++) FIFO Threshold
00273         (++) Frame Config
00274         (++) Slot Config
00275     (++) PDM Config
00276
00277       (+) Call the function HAL_SAI_DeInit() to restore the default configuration
00278           of the selected SAI peripheral.
00279
00280 @endverbatim
00281   * @{
00282   */
00283
00284 /**
00285   * @brief  Initialize the structure FrameInit, SlotInit and the low part of
00286   *         Init according to the specified parameters and call the function
00287   *         HAL_SAI_Init to initialize the SAI block.
00288   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00289   *               the configuration information for SAI module.
00290   * @param  protocol: one of the supported protocol @ref SAI_Protocol
00291   * @param  datasize: one of the supported datasize @ref SAI_Protocol_DataSize
00292   *                   the configuration information for SAI module.
00293   * @param  nbslot: Number of slot.
00294   * @retval HAL status
00295   */
00296 HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
00297 {
00298   HAL_StatusTypeDef status = HAL_OK;
00299
00300   /* Check the parameters */
00301   assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
00302   assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
00303
00304   switch(protocol)
00305   {
00306     case SAI_I2S_STANDARD :
00307     case SAI_I2S_MSBJUSTIFIED :
00308     case SAI_I2S_LSBJUSTIFIED :
00309       status = SAI_InitI2S(hsai, protocol, datasize, nbslot);
00310       break;
00311     case SAI_PCM_LONG :
00312     case SAI_PCM_SHORT :
00313       status = SAI_InitPCM(hsai, protocol, datasize, nbslot);
00314       break;
00315     default :
00316       status = HAL_ERROR;
00317       break;
00318   }
00319
00320   if(status == HAL_OK)
00321   {
00322     status = HAL_SAI_Init(hsai);
00323   }
00324
00325   return status;
00326 }
00327
00328 /**
00329   * @brief  Initialize the SAI according to the specified parameters.
00330   *         in the SAI_InitTypeDef structure and initialize the associated handle.
00331   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00332   *                the configuration information for SAI module.
00333   * @retval HAL status
00334   */
00335 HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
00336 {
00337   uint32_t tmpregisterGCR = 0;
00338   uint32_t ckstr_bits  = 0;
00339   uint32_t syncen_bits = 0;
00340   SAI_TypeDef *SaiBaseAddress;
00341
00342   /* Check the SAI handle allocation */
00343   if(hsai == NULL)
00344   {
00345     return HAL_ERROR;
00346   }
00347
00348   /* check the instance */
00349   assert_param(IS_SAI_ALL_INSTANCE(hsai->Instance));
00350
00351   /* Check the SAI Block parameters */
00352   assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));
00353   assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol));
00354   assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode));
00355   assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize));
00356   assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit));
00357   assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing));
00358   assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro));
00359   assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive));
00360   assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider));
00361   assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold));
00362   assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode));
00363   assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode));
00364   assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState));
00365   assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt));
00366   assert_param(IS_SAI_BLOCK_MCK_OVERSAMPLING(hsai->Init.MckOverSampling));
00367
00368   /* Check the SAI Block Frame parameters */
00369   assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength));
00370   assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength));
00371   assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition));
00372   assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity));
00373   assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset));
00374
00375   /* Check the SAI Block Slot parameters */
00376   assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset));
00377   assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize));
00378   assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber));
00379   assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive));
00380
00381   /* Check the SAI PDM parameters */
00382   assert_param(IS_FUNCTIONAL_STATE(hsai->Init.PdmInit.Activation));
00383
00384   if(hsai->Init.PdmInit.Activation == ENABLE)
00385   {
00386     /* Check the SAI PDM Microphone pairs number parameter */
00387     assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(hsai->Init.PdmInit.MicPairsNbr));
00388
00389     /* Check the SAI PDM clock enable paramater */
00390     assert_param(IS_SAI_PDM_CLOCK_ENABLE(hsai->Init.PdmInit.ClockEnable));
00391
00392     /* The PDM function is intended to be used in conjunction with SAI_A sub-block
00393        configured in TDM MASTER mode. It cannot be used with SAI_B sub-block.
00394        Make sure that the SAI is already operating in TDM master mode before
00395        enabling the PDM interface */
00396     if(((hsai->Instance != SAI1_Block_A) && (hsai->Instance != SAI2_Block_A) && \
00397         (hsai->Instance != SAI3_Block_A) && (hsai->Instance != SAI4_Block_A)) || \
00398         (hsai->Init.AudioMode != SAI_MODEMASTER_RX) ||  \
00399         (hsai->Init.Protocol != SAI_FREE_PROTOCOL))
00400     {
00401       return HAL_ERROR;
00402     }
00403   }
00404
00405   /* Get the SAI base address according to the SAI handle */
00406   if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
00407   {
00408     SaiBaseAddress = SAI1;
00409   }
00410   else if((hsai->Instance == SAI2_Block_A) || (hsai->Instance == SAI2_Block_B))
00411   {
00412     SaiBaseAddress = SAI2;
00413   }
00414   else if((hsai->Instance == SAI3_Block_A) || (hsai->Instance == SAI3_Block_B))
00415   {
00416     SaiBaseAddress = SAI3;
00417   }
00418   else
00419   {
00420     SaiBaseAddress = SAI4;
00421   }
00422
00423   if(hsai->State == HAL_SAI_STATE_RESET)
00424   {
00425     /* Allocate lock resource and initialize it */
00426     hsai->Lock = HAL_UNLOCKED;
00427
00428     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00429     HAL_SAI_MspInit(hsai);
00430   }
00431
00432   hsai->State = HAL_SAI_STATE_BUSY;
00433
00434   /* Disable the selected SAI peripheral */
00435   SAI_Disable(hsai);
00436
00437   /* SAI PDM Configuration -----------------------------------------*/
00438   /* Disable PDM interface */
00439   CLEAR_BIT(SaiBaseAddress->PDMCR, SAI_PDMCR_PDMEN);
00440
00441   if(hsai->Init.PdmInit.Activation == ENABLE)
00442   {
00443     /* Configure and enable the PDM interface */
00444     SaiBaseAddress->PDMCR = (hsai->Init.PdmInit.ClockEnable |
00445                            ((hsai->Init.PdmInit.MicPairsNbr - 1) << SAI_PDMCR_MICNBR_OFFSET));
00446     SET_BIT(SaiBaseAddress->PDMCR, SAI_PDMCR_PDMEN);
00447   }
00448
00449   /* SAI Block Synchro Configuration -----------------------------------------*/
00450   /* This setting must be done with both audio block (A & B) disabled         */
00451   switch(hsai->Init.SynchroExt)
00452   {
00453     case SAI_SYNCEXT_DISABLE :
00454       tmpregisterGCR = 0;
00455       break;
00456     case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
00457       tmpregisterGCR = SAI_GCR_SYNCOUT_0;
00458       break;
00459     case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
00460       tmpregisterGCR = SAI_GCR_SYNCOUT_1;
00461       break;
00462     default:
00463       break;
00464   }
00465
00466   switch(hsai->Init.Synchro)
00467   {
00468     case SAI_ASYNCHRONOUS :
00469       {
00470         syncen_bits = 0;
00471       }
00472       break;
00473     case SAI_SYNCHRONOUS :
00474       {
00475         syncen_bits = SAI_xCR1_SYNCEN_0;
00476       }
00477       break;
00478     case SAI_SYNCHRONOUS_EXT_SAI1 :
00479       {
00480         syncen_bits = SAI_xCR1_SYNCEN_1;
00481       }
00482       break;
00483     case SAI_SYNCHRONOUS_EXT_SAI2 :
00484       {
00485         syncen_bits = SAI_xCR1_SYNCEN_1;
00486         tmpregisterGCR |= SAI_GCR_SYNCIN_0;
00487       }
00488       break;
00489     default:
00490       break;
00491   }
00492
00493   /* Set the SAI Block Synchro Configuration */
00494   SaiBaseAddress->GCR = tmpregisterGCR;
00495
00496   if(hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV)
00497   {
00498     uint32_t freq = 0;
00499     uint32_t tmpval;
00500
00501     if((hsai->Instance == SAI1_Block_A ) || (hsai->Instance == SAI1_Block_B ))
00502     {
00503       freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);
00504     }
00505     if((hsai->Instance == SAI2_Block_A ) || (hsai->Instance == SAI2_Block_B ))
00506     {
00507       freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2);
00508     }
00509     if((hsai->Instance == SAI3_Block_A ) || (hsai->Instance == SAI3_Block_B ))
00510     {
00511       freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI3);
00512     }
00513     if(hsai->Instance == SAI4_Block_A)
00514     {
00515       freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI4A);
00516     }
00517     if(hsai->Instance == SAI4_Block_B)
00518     {
00519       freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI4B);
00520     }
00521
00522     /* Configure Master Clock using the following formula :
00523        If NOMCK = 1
00524        MCKDIV[5:0] = SAI_CK_x / (FS * (FRL + 1))
00525        If NOMCK = 0
00526        MCKDIV[5:0] = SAI_CK_x / (FS * (OSR + 1) * 256) */
00527     if(hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE)
00528     {
00529       /* (freq x 10) to keep Significant digits */
00530       tmpval = (freq * 10) / (hsai->Init.AudioFrequency * hsai->FrameInit.FrameLength);
00531     }
00532     else
00533     {
00534       /* NOMCK = 0 */
00535       uint32_t tmposr;
00536
00537       tmposr = (hsai->Init.MckOverSampling == SAI_MCK_OVERSAMPLING_ENABLE)? 2 : 1;
00538
00539       /* (freq x 10) to keep Significant digits */
00540       tmpval = (freq * 10) / (hsai->Init.AudioFrequency * tmposr * 256);
00541     }
00542
00543     hsai->Init.Mckdiv = tmpval / 10;
00544
00545     /* Round result to the nearest integer */
00546     if((tmpval % 10) > 8)
00547     {
00548       hsai->Init.Mckdiv += 1;
00549     }
00550   }
00551
00552   /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */
00553   if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
00554   { /* Transmit */
00555     ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0 : SAI_xCR1_CKSTR;
00556   }
00557   else
00558   { /* Receive */
00559     ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0;
00560   }
00561
00562   /* SAI Block Configuration -------------------------------------------------*/
00563   /* SAI CR1 Configuration */
00564   hsai->Instance->CR1 &=~ (SAI_xCR1_MODE | SAI_xCR1_PRTCFG |  SAI_xCR1_DS |      \
00565                            SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\
00566                            SAI_xCR1_MONO | SAI_xCR1_OUTDRIV  | SAI_xCR1_DMAEN |  \
00567                            SAI_xCR1_NOMCK | SAI_xCR1_MCKDIV);
00568
00569   hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol |           \
00570                           hsai->Init.DataSize | hsai->Init.FirstBit  |           \
00571                           ckstr_bits | syncen_bits |                             \
00572                           hsai->Init.MonoStereoMode | hsai->Init.OutputDrive |   \
00573                           hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) |     \
00574                         hsai->Init.MckOverSampling);
00575
00576   /* SAI CR2 Configuration */
00577   hsai->Instance->CR2 &= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL);
00578   hsai->Instance->CR2 |=  (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState);
00579
00580   /* SAI Frame Configuration -----------------------------------------*/
00581   hsai->Instance->FRCR &= (~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \
00582                             SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF));
00583   hsai->Instance->FRCR |= ((hsai->FrameInit.FrameLength - 1) | \
00584                             hsai->FrameInit.FSOffset |         \
00585                             hsai->FrameInit.FSDefinition |     \
00586                             hsai->FrameInit.FSPolarity   |     \
00587                             ((hsai->FrameInit.ActiveFrameLength - 1) << 8));
00588
00589   /* SAI Block_x SLOT Configuration ------------------------------------------*/
00590   /* This register has no meaning in AC 97 and SPDIF audio protocol */
00591   hsai->Instance->SLOTR &= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ |  \
00592                              SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN ));
00593
00594   hsai->Instance->SLOTR |=  hsai->SlotInit.FirstBitOffset |  hsai->SlotInit.SlotSize | \
00595                             (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1) <<  8);
00596
00597   /* Initialize the error code */
00598   hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00599
00600   /* Initialize the SAI state */
00601   hsai->State= HAL_SAI_STATE_READY;
00602
00603   /* Release Lock */
00604   __HAL_UNLOCK(hsai);
00605
00606   return HAL_OK;
00607 }
00608
00609 /**
00610   * @brief  DeInitialize the SAI peripheral.
00611   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00612   *                the configuration information for SAI module.
00613   * @retval HAL status
00614   */
00615 HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
00616 {
00617   SAI_TypeDef *SaiBaseAddress;
00618
00619   /* Check the SAI handle allocation */
00620   if(hsai == NULL)
00621   {
00622     return HAL_ERROR;
00623   }
00624
00625   hsai->State = HAL_SAI_STATE_BUSY;
00626
00627   /* Disabled All interrupt and clear all the flag */
00628   hsai->Instance->IMR = 0;
00629   hsai->Instance->CLRFR = 0xFFFFFFFFU;
00630
00631   /* Disable the SAI PDM interface */
00632   if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI2_Block_A) || \
00633      (hsai->Instance == SAI3_Block_A) || (hsai->Instance == SAI4_Block_A))
00634   {
00635     /* Get the SAI base address according to the SAI handle */
00636     SaiBaseAddress = (hsai->Instance == SAI1_Block_A)   ? SAI1 : \
00637                       ((hsai->Instance == SAI2_Block_A) ? SAI2 : \
00638                       ((hsai->Instance == SAI3_Block_A) ? SAI3 : SAI4));
00639
00640     /* Disable PDM interface */
00641     CLEAR_BIT(SaiBaseAddress->PDMCR, SAI_PDMCR_PDMEN);
00642   }
00643
00644   /* Disable the SAI */
00645   SAI_Disable(hsai);
00646
00647   /* Flush the fifo */
00648   SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
00649
00650   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
00651   HAL_SAI_MspDeInit(hsai);
00652
00653   /* Initialize the error code */
00654   hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00655
00656   /* Initialize the SAI state */
00657   hsai->State = HAL_SAI_STATE_RESET;
00658
00659   /* Release Lock */
00660   __HAL_UNLOCK(hsai);
00661
00662   return HAL_OK;
00663 }
00664
00665 /**
00666   * @brief Initialize the SAI MSP.
00667   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00668   *                the configuration information for SAI module.
00669   * @retval None
00670   */
00671 __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai)
00672 {
00673   /* Prevent unused argument(s) compilation warning */
00674   UNUSED(hsai);
00675
00676   /* NOTE : This function should not be modified, when the callback is needed,
00677             the HAL_SAI_MspInit could be implemented in the user file
00678    */
00679 }
00680
00681 /**
00682   * @brief DeInitialize the SAI MSP.
00683   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00684   *                the configuration information for SAI module.
00685   * @retval None
00686   */
00687 __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
00688 {
00689   /* Prevent unused argument(s) compilation warning */
00690   UNUSED(hsai);
00691
00692   /* NOTE : This function should not be modified, when the callback is needed,
00693             the HAL_SAI_MspDeInit could be implemented in the user file
00694    */
00695 }
00696
00697 /**
00698   * @}
00699   */
00700
00701 /** @defgroup SAI_Exported_Functions_Group2 IO operation functions
00702  *  @brief    Data transfers functions
00703  *
00704 @verbatim
00705   ==============================================================================
00706                       ##### IO operation functions #####
00707   ==============================================================================
00708   [..]
00709     This subsection provides a set of functions allowing to manage the SAI data
00710     transfers.
00711
00712     (+) There are two modes of transfer:
00713       (++) Blocking mode : The communication is performed in the polling mode.
00714            The status of all data processing is returned by the same function
00715            after finishing transfer.
00716       (++) No-Blocking mode : The communication is performed using Interrupts
00717            or DMA. These functions return the status of the transfer startup.
00718            The end of the data processing will be indicated through the
00719            dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when
00720            using DMA mode.
00721
00722     (+) Blocking mode functions are :
00723       (++) HAL_SAI_Transmit()
00724       (++) HAL_SAI_Receive()
00725       (++) HAL_SAI_TransmitReceive()
00726
00727     (+) Non Blocking mode functions with Interrupt are :
00728       (++) HAL_SAI_Transmit_IT()
00729       (++) HAL_SAI_Receive_IT()
00730       (++) HAL_SAI_TransmitReceive_IT()
00731
00732     (+) Non Blocking mode functions with DMA are :
00733       (++) HAL_SAI_Transmit_DMA()
00734       (++) HAL_SAI_Receive_DMA()
00735       (++) HAL_SAI_TransmitReceive_DMA()
00736
00737     (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00738       (++) HAL_SAI_TxCpltCallback()
00739       (++) HAL_SAI_RxCpltCallback()
00740       (++) HAL_SAI_ErrorCallback()
00741
00742 @endverbatim
00743   * @{
00744   */
00745
00746 /**
00747   * @brief  Transmit an amount of data in blocking mode.
00748   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00749   *                the configuration information for SAI module.
00750   * @param  pData: Pointer to data buffer
00751   * @param  Size: Amount of data to be sent
00752   * @param  Timeout: Timeout duration
00753   * @retval HAL status
00754   */
00755 HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout)
00756 {
00757   uint32_t tickstart = HAL_GetTick();
00758
00759   if((pData == NULL ) || (Size == 0))
00760   {
00761     return  HAL_ERROR;
00762   }
00763
00764   if(hsai->State == HAL_SAI_STATE_READY)
00765   {
00766     /* Process Locked */
00767     __HAL_LOCK(hsai);
00768
00769     hsai->XferSize = Size;
00770     hsai->XferCount = Size;
00771     hsai->pBuffPtr = pData;
00772     hsai->State = HAL_SAI_STATE_BUSY_TX;
00773     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00774
00775     /* Check if the SAI is already enabled */
00776     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
00777     {
00778       /* fill the fifo with data before to enabled the SAI */
00779       SAI_FillFifo(hsai);
00780       /* Enable SAI peripheral */
00781       __HAL_SAI_ENABLE(hsai);
00782     }
00783
00784     while(hsai->XferCount > 0)
00785     {
00786       /* Write data if the FIFO is not full */
00787       if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)
00788       {
00789         if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
00790         {
00791           hsai->Instance->DR = (*hsai->pBuffPtr++);
00792         }
00793         else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
00794         {
00795           hsai->Instance->DR = *((uint16_t *)hsai->pBuffPtr);
00796           hsai->pBuffPtr+= 2;
00797         }
00798         else
00799         {
00800           hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
00801           hsai->pBuffPtr+= 4;
00802         }
00803         hsai->XferCount--;
00804       }
00805       else
00806       {
00807         /* Check for the Timeout */
00808         if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)))
00809         {
00810           /* Update error code */
00811           hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
00812
00813           /* Clear all the flags */
00814           hsai->Instance->CLRFR = 0xFFFFFFFFU;
00815
00816           /* Disable SAI peripheral */
00817           SAI_Disable(hsai);
00818
00819           /* Flush the fifo */
00820           SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
00821
00822           /* Change the SAI state */
00823           hsai->State = HAL_SAI_STATE_READY;
00824
00825           /* Process Unlocked */
00826           __HAL_UNLOCK(hsai);
00827
00828           return HAL_ERROR;
00829         }
00830       }
00831     }
00832
00833     hsai->State = HAL_SAI_STATE_READY;
00834
00835     /* Process Unlocked */
00836     __HAL_UNLOCK(hsai);
00837
00838     return HAL_OK;
00839   }
00840   else
00841   {
00842     return HAL_BUSY;
00843   }
00844 }
00845
00846 /**
00847   * @brief  Receive an amount of data in blocking mode.
00848   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00849   *                the configuration information for SAI module.
00850   * @param  pData: Pointer to data buffer
00851   * @param  Size: Amount of data to be received
00852   * @param  Timeout: Timeout duration
00853   * @retval HAL status
00854   */
00855 HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00856 {
00857   uint32_t tickstart = HAL_GetTick();
00858
00859   if((pData == NULL ) || (Size == 0))
00860   {
00861     return  HAL_ERROR;
00862   }
00863
00864   if(hsai->State == HAL_SAI_STATE_READY)
00865   {
00866     /* Process Locked */
00867     __HAL_LOCK(hsai);
00868
00869     hsai->pBuffPtr = pData;
00870     hsai->XferSize = Size;
00871     hsai->XferCount = Size;
00872     hsai->State = HAL_SAI_STATE_BUSY_RX;
00873     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00874
00875     /* Check if the SAI is already enabled */
00876     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
00877     {
00878       /* Enable SAI peripheral */
00879       __HAL_SAI_ENABLE(hsai);
00880     }
00881
00882     /* Receive data */
00883     while(hsai->XferCount > 0)
00884     {
00885       if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY)
00886       {
00887         if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
00888         {
00889           (*hsai->pBuffPtr++) = hsai->Instance->DR;
00890         }
00891         else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
00892         {
00893           *((uint16_t*)hsai->pBuffPtr) = hsai->Instance->DR;
00894           hsai->pBuffPtr+= 2;
00895         }
00896         else
00897         {
00898           *((uint32_t*)hsai->pBuffPtr) = hsai->Instance->DR;
00899           hsai->pBuffPtr+= 4;
00900         }
00901         hsai->XferCount--;
00902       }
00903       else
00904       {
00905         /* Check for the Timeout */
00906         if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)))
00907         {
00908           /* Update error code */
00909           hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
00910
00911           /* Clear all the flags */
00912           hsai->Instance->CLRFR = 0xFFFFFFFFU;
00913
00914           /* Disable SAI peripheral */
00915           SAI_Disable(hsai);
00916
00917           /* Flush the fifo */
00918           SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
00919
00920           /* Change the SAI state */
00921           hsai->State = HAL_SAI_STATE_READY;
00922
00923           /* Process Unlocked */
00924           __HAL_UNLOCK(hsai);
00925
00926           return HAL_ERROR;
00927         }
00928       }
00929     }
00930
00931     hsai->State = HAL_SAI_STATE_READY;
00932
00933     /* Process Unlocked */
00934     __HAL_UNLOCK(hsai);
00935
00936     return HAL_OK;
00937   }
00938   else
00939   {
00940     return HAL_BUSY;
00941   }
00942 }
00943
00944 /**
00945   * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
00946   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00947   *                the configuration information for SAI module.
00948   * @param  pData: Pointer to data buffer
00949   * @param  Size: Amount of data to be sent
00950   * @retval HAL status
00951   */
00952 HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
00953 {
00954   if((pData == NULL) || (Size == 0))
00955   {
00956     return  HAL_ERROR;
00957   }
00958
00959   if(hsai->State == HAL_SAI_STATE_READY)
00960   {
00961     /* Process Locked */
00962     __HAL_LOCK(hsai);
00963
00964     hsai->pBuffPtr = pData;
00965     hsai->XferSize = Size;
00966     hsai->XferCount = Size;
00967     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00968     hsai->State = HAL_SAI_STATE_BUSY_TX;
00969
00970     if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
00971     {
00972       hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit;
00973     }
00974     else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
00975     {
00976       hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit;
00977     }
00978     else
00979     {
00980       hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit;
00981     }
00982
00983     /* Fill the fifo before starting the communication */
00984     SAI_FillFifo(hsai);
00985
00986     /* Enable FRQ and OVRUDR interrupts */
00987     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
00988
00989     /* Check if the SAI is already enabled */
00990     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
00991     {
00992       /* Enable SAI peripheral */
00993       __HAL_SAI_ENABLE(hsai);
00994     }
00995     /* Process Unlocked */
00996     __HAL_UNLOCK(hsai);
00997
00998     return HAL_OK;
00999   }
01000   else
01001   {
01002     return HAL_BUSY;
01003   }
01004 }
01005
01006 /**
01007   * @brief  Receive an amount of data in non-blocking mode with Interrupt.
01008   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01009   *                the configuration information for SAI module.
01010   * @param  pData: Pointer to data buffer
01011   * @param  Size: Amount of data to be received
01012   * @retval HAL status
01013   */
01014 HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
01015 {
01016   if((pData == NULL) || (Size == 0))
01017   {
01018     return  HAL_ERROR;
01019   }
01020
01021   if(hsai->State == HAL_SAI_STATE_READY)
01022   {
01023     /* Process Locked */
01024     __HAL_LOCK(hsai);
01025
01026     hsai->pBuffPtr = pData;
01027     hsai->XferSize = Size;
01028     hsai->XferCount = Size;
01029     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01030     hsai->State = HAL_SAI_STATE_BUSY_RX;
01031
01032     if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
01033     {
01034       hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit;
01035     }
01036     else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
01037     {
01038       hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit;
01039     }
01040     else
01041     {
01042       hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit;
01043     }
01044
01045     /* Enable TXE and OVRUDR interrupts */
01046     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01047
01048     /* Check if the SAI is already enabled */
01049     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
01050     {
01051       /* Enable SAI peripheral */
01052       __HAL_SAI_ENABLE(hsai);
01053     }
01054
01055     /* Process Unlocked */
01056     __HAL_UNLOCK(hsai);
01057
01058     return HAL_OK;
01059   }
01060   else
01061   {
01062     return HAL_BUSY;
01063   }
01064 }
01065
01066 /**
01067   * @brief Pause the audio stream playing from the Media.
01068   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01069   *                the configuration information for SAI module.
01070   * @retval HAL status
01071   */
01072 HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)
01073 {
01074   /* Process Locked */
01075   __HAL_LOCK(hsai);
01076
01077   /* Pause the audio file playing by disabling the SAI DMA requests */
01078   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
01079
01080   /* Process Unlocked */
01081   __HAL_UNLOCK(hsai);
01082
01083   return HAL_OK;
01084 }
01085
01086 /**
01087   * @brief Resume the audio stream playing from the Media.
01088   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01089   *                the configuration information for SAI module.
01090   * @retval HAL status
01091   */
01092 HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)
01093 {
01094   /* Process Locked */
01095   __HAL_LOCK(hsai);
01096
01097   /* Enable the SAI DMA requests */
01098   hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
01099
01100   /* If the SAI peripheral is still not enabled, enable it */
01101   if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
01102   {
01103     /* Enable SAI peripheral */
01104     __HAL_SAI_ENABLE(hsai);
01105   }
01106
01107   /* Process Unlocked */
01108   __HAL_UNLOCK(hsai);
01109
01110   return HAL_OK;
01111 }
01112
01113 /**
01114   * @brief  Stop the audio stream playing from the Media.
01115   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01116   *               the configuration information for SAI module.
01117   * @retval HAL status
01118   */
01119 HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
01120 {
01121   HAL_StatusTypeDef status = HAL_OK;
01122
01123   /* Process Locked */
01124   __HAL_LOCK(hsai);
01125
01126   /* Disable the SAI DMA request */
01127   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
01128
01129   /* Abort the SAI Tx DMA Stream */
01130   if((hsai->hdmatx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_TX))
01131   {
01132     if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
01133     {
01134       /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */
01135       if(hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
01136       {
01137         status = HAL_ERROR;
01138       }
01139     }
01140   }
01141
01142   /* Abort the SAI Rx DMA Stream */
01143   if((hsai->hdmarx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_RX))
01144   {
01145     if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
01146     {
01147       /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */
01148       if(hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
01149       {
01150         status = HAL_ERROR;
01151       }
01152     }
01153   }
01154
01155   /* Disable SAI peripheral */
01156   SAI_Disable(hsai);
01157
01158   /* Set hsai state to ready */
01159   hsai->State = HAL_SAI_STATE_READY;
01160
01161   /* Process Unlocked */
01162   __HAL_UNLOCK(hsai);
01163
01164   return status;
01165 }
01166
01167 /**
01168   * @brief Abort the current transfer and disable the SAI.
01169   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01170   *                the configuration information for SAI module.
01171   * @retval HAL status
01172   */
01173 HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
01174 {
01175   /* Process Locked */
01176   __HAL_LOCK(hsai);
01177
01178   /* Check SAI DMA is enabled or not */
01179   if((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
01180   {
01181     /* Disable the SAI DMA request */
01182     hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
01183
01184     /* Abort the SAI DMA Streams */
01185     if(hsai->hdmatx != NULL)
01186     {
01187       if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
01188       {
01189         return HAL_ERROR;
01190       }
01191     }
01192
01193     if(hsai->hdmarx != NULL)
01194     {
01195       if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
01196       {
01197         return HAL_ERROR;
01198       }
01199     }
01200   }
01201
01202   /* Disabled All interrupt and clear all the flag */
01203   hsai->Instance->IMR = 0;
01204   hsai->Instance->CLRFR = 0xFFFFFFFFU;
01205
01206   /* Disable SAI peripheral */
01207   SAI_Disable(hsai);
01208
01209   /* Flush the fifo */
01210   SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
01211
01212   hsai->State = HAL_SAI_STATE_READY;
01213
01214   /* Process Unlocked */
01215   __HAL_UNLOCK(hsai);
01216
01217   return HAL_OK;
01218 }
01219
01220 /**
01221   * @brief  Transmit an amount of data in non-blocking mode with DMA.
01222   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01223   *                the configuration information for SAI module.
01224   * @param  pData: Pointer to data buffer
01225   * @param  Size: Amount of data to be sent
01226   * @retval HAL status
01227   */
01228 HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
01229 {
01230   uint32_t tickstart = HAL_GetTick();
01231
01232   if((pData == NULL) || (Size == 0))
01233   {
01234     return  HAL_ERROR;
01235   }
01236
01237   if(hsai->State == HAL_SAI_STATE_READY)
01238   {
01239     /* Process Locked */
01240     __HAL_LOCK(hsai);
01241
01242     hsai->pBuffPtr = pData;
01243     hsai->XferSize = Size;
01244     hsai->XferCount = Size;
01245     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01246     hsai->State = HAL_SAI_STATE_BUSY_TX;
01247
01248     /* Set the SAI Tx DMA Half transfer complete callback */
01249     hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt;
01250
01251     /* Set the SAI TxDMA transfer complete callback */
01252     hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt;
01253
01254     /* Set the DMA error callback */
01255     hsai->hdmatx->XferErrorCallback = SAI_DMAError;
01256
01257     /* Set the DMA Tx abort callback */
01258     hsai->hdmatx->XferAbortCallback = NULL;
01259
01260     /* Enable the Tx DMA Stream */
01261     if(HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, hsai->XferSize) != HAL_OK)
01262     {
01263       __HAL_UNLOCK(hsai);
01264       return  HAL_ERROR;
01265     }
01266
01267     /* Enable the interrupts for error handling */
01268     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
01269
01270     /* Enable SAI Tx DMA Request */
01271     hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
01272
01273     /* Wait untill FIFO is not empty */
01274     while((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY)
01275     {
01276       /* Check for the Timeout */
01277       if((HAL_GetTick() - tickstart) > SAI_LONG_TIMEOUT)
01278       {
01279         /* Update error code */
01280         hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
01281
01282         /* Process Unlocked */
01283         __HAL_UNLOCK(hsai);
01284
01285         return HAL_TIMEOUT;
01286       }
01287     }
01288
01289     /* Check if the SAI is already enabled */
01290     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
01291     {
01292       /* Enable SAI peripheral */
01293       __HAL_SAI_ENABLE(hsai);
01294     }
01295
01296     /* Process Unlocked */
01297     __HAL_UNLOCK(hsai);
01298
01299     return HAL_OK;
01300   }
01301   else
01302   {
01303     return HAL_BUSY;
01304   }
01305 }
01306
01307 /**
01308   * @brief  Receive an amount of data in non-blocking mode with DMA.
01309   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01310   *                the configuration information for SAI module.
01311   * @param  pData: Pointer to data buffer
01312   * @param  Size: Amount of data to be received
01313   * @retval HAL status
01314   */
01315 HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
01316 {
01317
01318   if((pData == NULL) || (Size == 0))
01319   {
01320     return  HAL_ERROR;
01321   }
01322
01323   if(hsai->State == HAL_SAI_STATE_READY)
01324   {
01325     /* Process Locked */
01326     __HAL_LOCK(hsai);
01327
01328     hsai->pBuffPtr = pData;
01329     hsai->XferSize = Size;
01330     hsai->XferCount = Size;
01331     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01332     hsai->State = HAL_SAI_STATE_BUSY_RX;
01333
01334     /* Set the SAI Rx DMA Half transfer complete callback */
01335     hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt;
01336
01337     /* Set the SAI Rx DMA transfer complete callback */
01338     hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt;
01339
01340     /* Set the DMA error callback */
01341     hsai->hdmarx->XferErrorCallback = SAI_DMAError;
01342
01343     /* Set the DMA Rx abort callback */
01344     hsai->hdmarx->XferAbortCallback = NULL;
01345
01346     /* Enable the Rx DMA Stream */
01347     if(HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, hsai->XferSize) != HAL_OK)
01348     {
01349       __HAL_UNLOCK(hsai);
01350       return  HAL_ERROR;
01351     }
01352
01353     /* Check if the SAI is already enabled */
01354     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
01355     {
01356       /* Enable SAI peripheral */
01357       __HAL_SAI_ENABLE(hsai);
01358     }
01359
01360     /* Enable the interrupts for error handling */
01361     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
01362
01363     /* Enable SAI Rx DMA Request */
01364     hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
01365
01366     /* Process Unlocked */
01367     __HAL_UNLOCK(hsai);
01368
01369     return HAL_OK;
01370   }
01371   else
01372   {
01373     return HAL_BUSY;
01374   }
01375 }
01376
01377 /**
01378   * @brief  Enable the Tx mute mode.
01379   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01380   *                the configuration information for SAI module.
01381   * @param  val:  value sent during the mute @ref SAI_Block_Mute_Value
01382   * @retval HAL status
01383   */
01384 HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val)
01385 {
01386   assert_param(IS_SAI_BLOCK_MUTE_VALUE(val));
01387
01388   if(hsai->State != HAL_SAI_STATE_RESET)
01389   {
01390     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
01391     SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | val);
01392     return HAL_OK;
01393   }
01394   return HAL_ERROR;
01395 }
01396
01397 /**
01398   * @brief  Disable the Tx mute mode.
01399   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01400   *                the configuration information for SAI module.
01401   * @retval HAL status
01402   */
01403 HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai)
01404 {
01405   if(hsai->State != HAL_SAI_STATE_RESET)
01406   {
01407     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
01408     return HAL_OK;
01409   }
01410   return HAL_ERROR;
01411 }
01412
01413 /**
01414   * @brief  Enable the Rx mute detection.
01415   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01416   *                the configuration information for SAI module.
01417   * @param  callback: function called when the mute is detected.
01418   * @param  counter: number a data before mute detection max 63.
01419   * @retval HAL status
01420   */
01421 HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
01422 {
01423   assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter));
01424
01425   if(hsai->State != HAL_SAI_STATE_RESET)
01426   {
01427     /* set the mute counter */
01428     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT);
01429     SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_OFFSET));
01430     hsai->mutecallback = callback;
01431     /* enable the IT interrupt */
01432     __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET);
01433     return HAL_OK;
01434   }
01435   return HAL_ERROR;
01436 }
01437
01438 /**
01439   * @brief  Disable the Rx mute detection.
01440   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01441   *                the configuration information for SAI module.
01442   * @retval HAL status
01443   */
01444 HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai)
01445 {
01446   if(hsai->State != HAL_SAI_STATE_RESET)
01447   {
01448     /* set the mutecallback to NULL */
01449     hsai->mutecallback = (SAIcallback)NULL;
01450     /* enable the IT interrupt */
01451     __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET);
01452     return HAL_OK;
01453   }
01454   return HAL_ERROR;
01455 }
01456
01457 /**
01458   * @brief  Handle SAI interrupt request.
01459   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01460   *                the configuration information for SAI module.
01461   * @retval None
01462   */
01463 void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
01464 {
01465   if(hsai->State != HAL_SAI_STATE_RESET)
01466   {
01467     uint32_t itflags = hsai->Instance->SR;
01468     uint32_t itsources = hsai->Instance->IMR;
01469     uint32_t cr1config = hsai->Instance->CR1;
01470     uint32_t tmperror;
01471
01472     /* SAI Fifo request interrupt occured ------------------------------------*/
01473     if(((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ))
01474     {
01475       hsai->InterruptServiceRoutine(hsai);
01476     }
01477     /* SAI Overrun error interrupt occurred ----------------------------------*/
01478     else if(((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR))
01479     {
01480       /* Clear the SAI Overrun flag */
01481       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
01482       /* Get the SAI error code */
01483       tmperror = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR);
01484       /* Change the SAI error code */
01485       hsai->ErrorCode |= tmperror;
01486       /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
01487       HAL_SAI_ErrorCallback(hsai);
01488     }
01489     /* SAI mutedet interrupt occurred ----------------------------------*/
01490     else if(((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))
01491     {
01492       /* Clear the SAI mutedet flag */
01493       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET);
01494       /* call the call back function */
01495       if(hsai->mutecallback != (SAIcallback)NULL)
01496       {
01497         /* inform the user that an RX mute event has been detected */
01498         hsai->mutecallback();
01499       }
01500     }
01501     /* SAI AFSDET interrupt occurred ----------------------------------*/
01502     else if(((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET))
01503     {
01504       /* Change the SAI error code */
01505       hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET;
01506
01507       /* Check SAI DMA is enabled or not */
01508       if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
01509       {
01510         /* Abort the SAI DMA Streams */
01511         if(hsai->hdmatx != NULL)
01512         {
01513           /* Set the DMA Tx abort callback */
01514           hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
01515
01516           /* Abort DMA in IT mode */
01517           HAL_DMA_Abort_IT(hsai->hdmatx);
01518         }
01519         else if(hsai->hdmarx != NULL)
01520         {
01521           /* Set the DMA Rx abort callback */
01522           hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
01523
01524           /* Abort DMA in IT mode */
01525           HAL_DMA_Abort_IT(hsai->hdmarx);
01526         }
01527       }
01528       else
01529       {
01530         /* Abort SAI */
01531         HAL_SAI_Abort(hsai);
01532
01533         /* Set error callback */
01534         HAL_SAI_ErrorCallback(hsai);
01535       }
01536     }
01537     /* SAI LFSDET interrupt occurred ----------------------------------*/
01538     else if(((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET))
01539     {
01540       /* Change the SAI error code */
01541       hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET;
01542
01543       /* Check SAI DMA is enabled or not */
01544       if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
01545       {
01546         /* Abort the SAI DMA Streams */
01547         if(hsai->hdmatx != NULL)
01548         {
01549           /* Set the DMA Tx abort callback */
01550           hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
01551
01552           /* Abort DMA in IT mode */
01553           HAL_DMA_Abort_IT(hsai->hdmatx);
01554         }
01555         else if(hsai->hdmarx != NULL)
01556         {
01557           /* Set the DMA Rx abort callback */
01558           hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
01559
01560           /* Abort DMA in IT mode */
01561           HAL_DMA_Abort_IT(hsai->hdmarx);
01562         }
01563       }
01564       else
01565       {
01566         /* Abort SAI */
01567         HAL_SAI_Abort(hsai);
01568
01569         /* Set error callback */
01570         HAL_SAI_ErrorCallback(hsai);
01571       }
01572     }
01573     /* SAI WCKCFG interrupt occurred ----------------------------------*/
01574     else if(((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))
01575     {
01576       /* Change the SAI error code */
01577       hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG;
01578
01579       /* Check SAI DMA is enabled or not */
01580       if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
01581       {
01582         /* Abort the SAI DMA Streams */
01583         if(hsai->hdmatx != NULL)
01584         {
01585           /* Set the DMA Tx abort callback */
01586           hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
01587
01588           /* Abort DMA in IT mode */
01589           HAL_DMA_Abort_IT(hsai->hdmatx);
01590         }
01591         else if(hsai->hdmarx != NULL)
01592         {
01593           /* Set the DMA Rx abort callback */
01594           hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
01595
01596           /* Abort DMA in IT mode */
01597           HAL_DMA_Abort_IT(hsai->hdmarx);
01598         }
01599       }
01600       else
01601       {
01602         /* If WCKCFG occurs, SAI audio block is automatically disabled */
01603         /* Disable all interrupts and clear all flags */
01604         hsai->Instance->IMR = 0U;
01605         hsai->Instance->CLRFR = 0xFFFFFFFFU;
01606         /* Set the SAI state to ready to be able to start again the process */
01607         hsai->State = HAL_SAI_STATE_READY;
01608
01609         /* Initialize XferCount */
01610         hsai->XferCount = 0U;
01611
01612         /* SAI error Callback */
01613         HAL_SAI_ErrorCallback(hsai);
01614       }
01615     }
01616     /* SAI CNRDY interrupt occurred ----------------------------------*/
01617     else if(((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY))
01618     {
01619       /* Clear the SAI CNRDY flag */
01620       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY);
01621       /* Change the SAI error code */
01622       hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY;
01623       /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
01624       HAL_SAI_ErrorCallback(hsai);
01625     }
01626     else
01627     {
01628       /* Nothing to do */
01629     }
01630   }
01631 }
01632
01633 /**
01634   * @brief Tx Transfer completed callback.
01635   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01636   *                the configuration information for SAI module.
01637   * @retval None
01638   */
01639 __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
01640 {
01641   /* Prevent unused argument(s) compilation warning */
01642   UNUSED(hsai);
01643
01644   /* NOTE : This function should not be modified, when the callback is needed,
01645             the HAL_SAI_TxCpltCallback could be implemented in the user file
01646    */
01647 }
01648
01649 /**
01650   * @brief Tx Transfer Half completed callback.
01651   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01652   *                the configuration information for SAI module.
01653   * @retval None
01654   */
01655 __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
01656 {
01657   /* Prevent unused argument(s) compilation warning */
01658   UNUSED(hsai);
01659
01660   /* NOTE : This function should not be modified, when the callback is needed,
01661             the HAL_SAI_TxHalfCpltCallback could be implemented in the user file
01662    */
01663 }
01664
01665 /**
01666   * @brief Rx Transfer completed callback.
01667   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01668   *                the configuration information for SAI module.
01669   * @retval None
01670   */
01671 __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)
01672 {
01673   /* Prevent unused argument(s) compilation warning */
01674   UNUSED(hsai);
01675
01676   /* NOTE : This function should not be modified, when the callback is needed,
01677             the HAL_SAI_RxCpltCallback could be implemented in the user file
01678    */
01679 }
01680
01681 /**
01682   * @brief Rx Transfer half completed callback.
01683   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01684   *                the configuration information for SAI module.
01685   * @retval None
01686   */
01687 __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)
01688 {
01689   /* Prevent unused argument(s) compilation warning */
01690   UNUSED(hsai);
01691
01692   /* NOTE : This function should not be modified, when the callback is needed,
01693             the HAL_SAI_RxHalfCpltCallback could be implemented in the user file
01694    */
01695 }
01696
01697 /**
01698   * @brief SAI error callback.
01699   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01700   *                the configuration information for SAI module.
01701   * @retval None
01702   */
01703 __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
01704 {
01705   /* Prevent unused argument(s) compilation warning */
01706   UNUSED(hsai);
01707
01708   /* NOTE : This function should not be modified, when the callback is needed,
01709             the HAL_SAI_ErrorCallback could be implemented in the user file
01710    */
01711 }
01712
01713 /**
01714   * @}
01715   */
01716
01717
01718 /** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions
01719  *  @brief    Peripheral State functions
01720  *
01721 @verbatim
01722   ===============================================================================
01723                 ##### Peripheral State and Errors functions #####
01724   ===============================================================================
01725   [..]
01726     This subsection permits to get in run-time the status of the peripheral
01727     and the data flow.
01728
01729 @endverbatim
01730   * @{
01731   */
01732
01733 /**
01734   * @brief  Return the SAI handle state.
01735   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01736   *                the configuration information for SAI module.
01737   * @retval HAL state
01738   */
01739 HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)
01740 {
01741   return hsai->State;
01742 }
01743
01744 /**
01745 * @brief  Return the SAI error code.
01746 * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01747   *              the configuration information for the specified SAI Block.
01748 * @retval SAI Error Code
01749 */
01750 uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
01751 {
01752   return hsai->ErrorCode;
01753 }
01754 /**
01755   * @}
01756   */
01757
01758 /**
01759   * @}
01760   */
01761
01762 /** @addtogroup SAI_Private_Functions
01763  *  @brief      Private functions
01764   * @{
01765   */
01766
01767 /**
01768   * @brief  Initialize the SAI I2S protocol according to the specified parameters
01769   *         in the SAI_InitTypeDef and create the associated handle.
01770   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01771   *                the configuration information for SAI module.
01772   * @param  protocol: one of the supported protocol.
01773   * @param  datasize: one of the supported datasize @ref SAI_Protocol_DataSize
01774   *                the configuration information for SAI module.
01775   * @param  nbslot: number of slot minimum value is 2 and max is 16.
01776   *                    the value must be a multiple of 2.
01777   * @retval HAL status
01778   */
01779 static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
01780 {
01781   hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
01782   hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
01783   /* Compute ClockStrobing according AudioMode */
01784   if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
01785   { /* Transmit */
01786     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;
01787   }
01788   else
01789   { /* Receive */
01790     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;
01791   }
01792   hsai->FrameInit.FSDefinition   = SAI_FS_CHANNEL_IDENTIFICATION;
01793   hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;
01794   hsai->SlotInit.FirstBitOffset  = 0;
01795   hsai->SlotInit.SlotNumber      = nbslot;
01796
01797   /* in IS2 the number of slot must be even */
01798   if((nbslot & 0x1) != 0 )
01799   {
01800     return HAL_ERROR;
01801   }
01802
01803   switch(protocol)
01804   {
01805     case SAI_I2S_STANDARD :
01806       hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
01807       hsai->FrameInit.FSOffset   = SAI_FS_BEFOREFIRSTBIT;
01808       break;
01809     case SAI_I2S_MSBJUSTIFIED :
01810     case SAI_I2S_LSBJUSTIFIED :
01811       hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
01812       hsai->FrameInit.FSOffset   = SAI_FS_FIRSTBIT;
01813       break;
01814     default :
01815       return HAL_ERROR;
01816   }
01817
01818   /* Frame definition */
01819   switch(datasize)
01820   {
01821     case SAI_PROTOCOL_DATASIZE_16BIT:
01822       hsai->Init.DataSize = SAI_DATASIZE_16;
01823       hsai->FrameInit.FrameLength = 32*(nbslot/2);
01824       hsai->FrameInit.ActiveFrameLength = 16*(nbslot/2);
01825       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
01826       break;
01827     case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
01828       hsai->Init.DataSize = SAI_DATASIZE_16;
01829       hsai->FrameInit.FrameLength = 64*(nbslot/2);
01830       hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);
01831       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01832       break;
01833     case SAI_PROTOCOL_DATASIZE_24BIT:
01834       hsai->Init.DataSize = SAI_DATASIZE_24;
01835       hsai->FrameInit.FrameLength = 64*(nbslot/2);
01836       hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);
01837       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01838       break;
01839     case SAI_PROTOCOL_DATASIZE_32BIT:
01840       hsai->Init.DataSize = SAI_DATASIZE_32;
01841       hsai->FrameInit.FrameLength = 64*(nbslot/2);
01842       hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);
01843       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01844       break;
01845     default :
01846       return HAL_ERROR;
01847   }
01848   if(protocol == SAI_I2S_LSBJUSTIFIED)
01849   {
01850     if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED)
01851     {
01852       hsai->SlotInit.FirstBitOffset = 16;
01853     }
01854     if (datasize == SAI_PROTOCOL_DATASIZE_24BIT)
01855     {
01856       hsai->SlotInit.FirstBitOffset = 8;
01857     }
01858   }
01859   return HAL_OK;
01860 }
01861
01862 /**
01863   * @brief  Initialize the SAI PCM protocol according to the specified parameters
01864   *         in the SAI_InitTypeDef and create the associated handle.
01865   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01866   *                the configuration information for SAI module.
01867   * @param  protocol: one of the supported protocol
01868   * @param  datasize: one of the supported datasize @ref SAI_Protocol_DataSize
01869   * @param  nbslot: number of slot minimum value is 1 and the max is 16.
01870   * @retval HAL status
01871   */
01872 static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
01873 {
01874   hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
01875   hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
01876   /* Compute ClockStrobing according AudioMode */
01877   if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
01878   { /* Transmit */
01879     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;
01880   }
01881   else
01882   { /* Receive */
01883     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;
01884   }
01885   hsai->FrameInit.FSDefinition   = SAI_FS_STARTFRAME;
01886   hsai->FrameInit.FSPolarity     = SAI_FS_ACTIVE_HIGH;
01887   hsai->FrameInit.FSOffset       = SAI_FS_BEFOREFIRSTBIT;
01888   hsai->SlotInit.FirstBitOffset  = 0;
01889   hsai->SlotInit.SlotNumber      = nbslot;
01890   hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;
01891
01892   switch(protocol)
01893   {
01894     case SAI_PCM_SHORT :
01895       hsai->FrameInit.ActiveFrameLength = 1;
01896       break;
01897     case SAI_PCM_LONG :
01898       hsai->FrameInit.ActiveFrameLength = 13;
01899       break;
01900     default :
01901       return HAL_ERROR;
01902   }
01903
01904   switch(datasize)
01905   {
01906     case SAI_PROTOCOL_DATASIZE_16BIT:
01907       hsai->Init.DataSize = SAI_DATASIZE_16;
01908       hsai->FrameInit.FrameLength = 16 * nbslot;
01909       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
01910       break;
01911     case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
01912       hsai->Init.DataSize = SAI_DATASIZE_16;
01913       hsai->FrameInit.FrameLength = 32 * nbslot;
01914       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01915       break;
01916     case SAI_PROTOCOL_DATASIZE_24BIT :
01917       hsai->Init.DataSize = SAI_DATASIZE_24;
01918       hsai->FrameInit.FrameLength = 32 * nbslot;
01919       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01920       break;
01921     case SAI_PROTOCOL_DATASIZE_32BIT:
01922       hsai->Init.DataSize = SAI_DATASIZE_32;
01923       hsai->FrameInit.FrameLength = 32 * nbslot;
01924       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01925       break;
01926     default :
01927       return HAL_ERROR;
01928   }
01929
01930   return HAL_OK;
01931 }
01932
01933 /**
01934   * @brief  Fill the fifo.
01935   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01936   *                the configuration information for SAI module.
01937   * @retval None
01938   */
01939 static void SAI_FillFifo(SAI_HandleTypeDef *hsai)
01940 {
01941   /* fill the fifo with data before to enabled the SAI */
01942   while(((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0))
01943   {
01944     if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
01945     {
01946       hsai->Instance->DR = (*hsai->pBuffPtr++);
01947     }
01948     else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
01949     {
01950       hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
01951       hsai->pBuffPtr+= 2;
01952     }
01953     else
01954     {
01955       hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
01956       hsai->pBuffPtr+= 4;
01957     }
01958     hsai->XferCount--;
01959   }
01960 }
01961
01962 /**
01963   * @brief  Return the interrupt flag to set according the SAI setup.
01964   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01965   *                the configuration information for SAI module.
01966   * @param  mode: SAI_MODE_DMA or SAI_MODE_IT
01967   * @retval the list of the IT flag to enable
01968  */
01969 static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode)
01970 {
01971   uint32_t tmpIT = SAI_IT_OVRUDR;
01972
01973   if(mode == SAI_MODE_IT)
01974   {
01975     tmpIT|= SAI_IT_FREQ;
01976   }
01977
01978   if((hsai->Init.Protocol == SAI_AC97_PROTOCOL) &&
01979     ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX)))
01980   {
01981     tmpIT|= SAI_IT_CNRDY;
01982   }
01983
01984   if((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
01985   {
01986     tmpIT|= SAI_IT_AFSDET | SAI_IT_LFSDET;
01987   }
01988   else
01989   {
01990     /* hsai has been configured in master mode */
01991     tmpIT|= SAI_IT_WCKCFG;
01992   }
01993   return tmpIT;
01994 }
01995
01996 /**
01997   * @brief  Disable the SAI and wait for the disabling.
01998   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01999   *                the configuration information for SAI module.
02000   * @retval None
02001   */
02002 static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
02003 {
02004   register uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock /7/1000);
02005   HAL_StatusTypeDef status = HAL_OK;
02006
02007   /* Disable the SAI instance */
02008   __HAL_SAI_DISABLE(hsai);
02009
02010   do
02011   {
02012     /* Check for the Timeout */
02013     if (count-- == 0)
02014     {
02015       /* Update error code */
02016       hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
02017       status = HAL_TIMEOUT;
02018       break;
02019     }
02020   } while((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET);
02021
02022   return status;
02023 }
02024
02025 /**
02026   * @brief  Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
02027   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
02028   *                the configuration information for SAI module.
02029   * @retval None
02030   */
02031 static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
02032 {
02033   if(hsai->XferCount == 0)
02034   {
02035     /* Handle the end of the transmission */
02036     /* Disable FREQ and OVRUDR interrupts */
02037     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02038     hsai->State = HAL_SAI_STATE_READY;
02039     HAL_SAI_TxCpltCallback(hsai);
02040   }
02041   else
02042   {
02043     /* Write data on DR register */
02044     hsai->Instance->DR = (*hsai->pBuffPtr++);
02045     hsai->XferCount--;
02046   }
02047 }
02048
02049 /**
02050   * @brief  Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
02051   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
02052   *                the configuration information for SAI module.
02053   * @retval None
02054   */
02055 static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
02056 {
02057   if(hsai->XferCount == 0)
02058   {
02059     /* Handle the end of the transmission */
02060     /* Disable FREQ and OVRUDR interrupts */
02061     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02062     hsai->State = HAL_SAI_STATE_READY;
02063     HAL_SAI_TxCpltCallback(hsai);
02064   }
02065   else
02066   {
02067     /* Write data on DR register */
02068     hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr;
02069     hsai->pBuffPtr+=2;
02070     hsai->XferCount--;
02071   }
02072 }
02073
02074 /**
02075   * @brief  Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
02076   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
02077   *                the configuration information for SAI module.
02078   * @retval None
02079   */
02080 static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
02081 {
02082   if(hsai->XferCount == 0)
02083   {
02084     /* Handle the end of the transmission */
02085     /* Disable FREQ and OVRUDR interrupts */
02086     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02087     hsai->State = HAL_SAI_STATE_READY;
02088     HAL_SAI_TxCpltCallback(hsai);
02089   }
02090   else
02091   {
02092     /* Write data on DR register */
02093     hsai->Instance->DR = *(uint32_t *)hsai->pBuffPtr;
02094     hsai->pBuffPtr+=4;
02095     hsai->XferCount--;
02096   }
02097 }
02098
02099 /**
02100   * @brief  Rx Handler for Receive in Interrupt mode 8-Bit transfer.
02101   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
02102   *                the configuration information for SAI module.
02103   * @retval None
02104   */
02105 static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)
02106 {
02107   /* Receive data */
02108   (*hsai->pBuffPtr++) = hsai->Instance->DR;
02109   hsai->XferCount--;
02110
02111   /* Check end of the transfer */
02112   if(hsai->XferCount == 0)
02113   {
02114     /* Disable TXE and OVRUDR interrupts */
02115     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02116
02117     /* Clear the SAI Overrun flag */
02118     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
02119
02120     hsai->State = HAL_SAI_STATE_READY;
02121     HAL_SAI_RxCpltCallback(hsai);
02122   }
02123 }
02124
02125 /**
02126   * @brief  Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
02127   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
02128   *                the configuration information for SAI module.
02129   * @retval None
02130   */
02131 static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)
02132 {
02133   /* Receive data */
02134   *(uint16_t*)hsai->pBuffPtr = hsai->Instance->DR;
02135   hsai->pBuffPtr+=2;
02136   hsai->XferCount--;
02137
02138   /* Check end of the transfer */
02139   if(hsai->XferCount == 0)
02140   {
02141     /* Disable TXE and OVRUDR interrupts */
02142     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02143
02144     /* Clear the SAI Overrun flag */
02145     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
02146
02147     hsai->State = HAL_SAI_STATE_READY;
02148     HAL_SAI_RxCpltCallback(hsai);
02149   }
02150 }
02151 /**
02152   * @brief  Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
02153   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
02154   *                the configuration information for SAI module.
02155   * @retval None
02156   */
02157 static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)
02158 {
02159   /* Receive data */
02160   *(uint32_t*)hsai->pBuffPtr = hsai->Instance->DR;
02161   hsai->pBuffPtr+=4;
02162   hsai->XferCount--;
02163
02164   /* Check end of the transfer */
02165   if(hsai->XferCount == 0)
02166   {
02167     /* Disable TXE and OVRUDR interrupts */
02168     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02169
02170     /* Clear the SAI Overrun flag */
02171     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
02172
02173     hsai->State = HAL_SAI_STATE_READY;
02174     HAL_SAI_RxCpltCallback(hsai);
02175   }
02176 }
02177
02178 /**
02179   * @brief  DMA SAI transmit process complete callback.
02180   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02181   *                the configuration information for the specified DMA module.
02182   * @retval None
02183   */
02184 static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
02185 {
02186   SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent;
02187
02188   if(hdma->Init.Mode != DMA_CIRCULAR)
02189   {
02190     hsai->XferCount = 0;
02191
02192     /* Disable SAI Tx DMA Request */
02193     hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
02194
02195     /* Stop the interrupts error handling */
02196     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
02197
02198     hsai->State= HAL_SAI_STATE_READY;
02199   }
02200   HAL_SAI_TxCpltCallback(hsai);
02201 }
02202
02203 /**
02204   * @brief  DMA SAI transmit process half complete callback.
02205   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02206   *                the configuration information for the specified DMA module.
02207   * @retval None
02208   */
02209 static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
02210 {
02211   SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02212
02213   HAL_SAI_TxHalfCpltCallback(hsai);
02214 }
02215
02216 /**
02217   * @brief  DMA SAI receive process complete callback.
02218   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02219   *                the configuration information for the specified DMA module.
02220   * @retval None
02221   */
02222 static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
02223 {
02224   SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02225
02226   if(hdma->Init.Mode != DMA_CIRCULAR)
02227   {
02228     /* Disable Rx DMA Request */
02229     hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
02230     hsai->XferCount = 0;
02231
02232     /* Stop the interrupts error handling */
02233     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
02234
02235     hsai->State = HAL_SAI_STATE_READY;
02236   }
02237   HAL_SAI_RxCpltCallback(hsai);
02238 }
02239
02240 /**
02241   * @brief  DMA SAI receive process half complete callback
02242   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02243   *                the configuration information for the specified DMA module.
02244   * @retval None
02245   */
02246 static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
02247 {
02248   SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02249
02250   HAL_SAI_RxHalfCpltCallback(hsai);
02251 }
02252 /**
02253   * @brief  DMA SAI communication error callback.
02254   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02255   *                the configuration information for the specified DMA module.
02256   * @retval None
02257   */
02258 static void SAI_DMAError(DMA_HandleTypeDef *hdma)
02259 {
02260   SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02261
02262   if((hsai->hdmatx->ErrorCode == HAL_DMA_ERROR_TE) || (hsai->hdmarx->ErrorCode == HAL_DMA_ERROR_TE))
02263   {
02264     /* Disable the SAI DMA request */
02265     hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
02266
02267     /* Disable SAI peripheral */
02268     SAI_Disable(hsai);
02269
02270     /* Set the SAI state ready to be able to start again the process */
02271     hsai->State = HAL_SAI_STATE_READY;
02272
02273     /* Initialize XferCount */
02274     hsai->XferCount = 0U;
02275   }
02276
02277   /* Ignore DMA FIFO error */
02278   if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
02279   {
02280     /* Set SAI error code */
02281     hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
02282
02283     /* SAI error Callback */
02284     HAL_SAI_ErrorCallback(hsai);
02285   }
02286 }
02287
02288 /**
02289   * @brief  DMA SAI Abort callback.
02290   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02291   *               the configuration information for the specified DMA module.
02292   * @retval None
02293   */
02294 static void SAI_DMAAbort(DMA_HandleTypeDef *hdma)
02295 {
02296   SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02297
02298   /* Disable DMA request */
02299   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
02300
02301   /* Disable all interrupts and clear all flags */
02302   hsai->Instance->IMR = 0U;
02303   hsai->Instance->CLRFR = 0xFFFFFFFFU;
02304
02305   if(hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG)
02306   {
02307     /* Disable SAI peripheral */
02308     SAI_Disable(hsai);
02309
02310     /* Flush the fifo */
02311     SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
02312   }
02313   /* Set the SAI state to ready to be able to start again the process */
02314   hsai->State = HAL_SAI_STATE_READY;
02315
02316   /* Initialize XferCount */
02317   hsai->XferCount = 0U;
02318
02319   /* SAI error Callback */
02320   HAL_SAI_ErrorCallback(hsai);
02321 }
02322
02323 /**
02324   * @}
02325   */
02326
02327 #endif /* HAL_SAI_MODULE_ENABLED */
02328 /**
02329   * @}
02330   */
02331
02332 /**
02333   * @}
02334   */
02335
02336 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sai.h Source File

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stm32h7xx_hal_sai.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sai.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of SAI HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_SAI_H
00040 #define __STM32H7xx_HAL_SAI_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32h7xx_hal_def.h"
00049
00050 /** @addtogroup STM32H7xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup SAI
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup SAI_Exported_Types SAI Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  HAL State structures definition
00065   */
00066 typedef enum
00067 {
00068   HAL_SAI_STATE_RESET   = 0x00U, /*!< SAI not yet initialized or disabled  */
00069   HAL_SAI_STATE_READY   = 0x01U, /*!< SAI initialized and ready for use    */
00070   HAL_SAI_STATE_BUSY    = 0x02U, /*!< SAI internal process is ongoing      */
00071   HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */
00072   HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing    */
00073 } HAL_SAI_StateTypeDef;
00074
00075 /**
00076   * @brief  SAI Callback prototype
00077   */
00078 typedef void (*SAIcallback)(void);
00079
00080 /** @defgroup SAI_PDM_Structure_definition SAI PDM Structure definition
00081   * @brief  SAI PDM Init structure definition
00082   * @{
00083   */
00084 typedef struct
00085 {
00086   FunctionalState  Activation;  /*!< Enable/Disable PDM interface */
00087   uint32_t         MicPairsNbr; /*!< Specifies the number of microphone pairs used.
00088                                      This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
00089   uint32_t         ClockEnable; /*!< Specifies which clock must be enabled.
00090                                      This parameter can be a values combination of @ref SAI_PDM_ClockEnable */
00091 } SAI_PdmInitTypeDef;
00092 /**
00093   * @}
00094   */
00095
00096
00097 /** @defgroup SAI_Init_Structure_definition SAI Init Structure definition
00098   * @brief  SAI Init Structure definition
00099   * @{
00100   */
00101 typedef struct
00102 {
00103   uint32_t AudioMode;           /*!< Specifies the SAI Block audio Mode.
00104                                      This parameter can be a value of @ref SAI_Block_Mode */
00105
00106   uint32_t Synchro;             /*!< Specifies SAI Block synchronization
00107                                      This parameter can be a value of @ref SAI_Block_Synchronization */
00108
00109   uint32_t SynchroExt;          /*!< Specifies SAI external output synchronization, this setup is common
00110                                      for BlockA and BlockB
00111                                      This parameter can be a value of @ref SAI_Block_SyncExt
00112                                      @note: If both audio blocks of same SAI are used, this parameter has
00113                                             to be set to the same value for each audio block */
00114
00115   uint32_t OutputDrive;         /*!< Specifies when SAI Block outputs are driven.
00116                                      This parameter can be a value of @ref SAI_Block_Output_Drive
00117                                      @note this value has to be set before enabling the audio block
00118                                      but after the audio block configuration. */
00119
00120   uint32_t NoDivider;           /*!< Specifies whether master clock will be divided or not.
00121                                      This parameter can be a value of @ref SAI_Block_NoDivider
00122                                      @note: If bit NOMCK in the SAI_xCR1 register is cleared, the frame length
00123                                             should be aligned to a number equal to a power of 2, from 8 to 256.
00124                                             If bit NOMCK in the SAI_xCR1 register is set, the frame length can
00125                                             take any of the values without constraint since the input clock of
00126                                             the audio block should be equal to the bit clock.
00127                                             There is no MCLK_x clock which can be output. */
00128
00129   uint32_t FIFOThreshold;       /*!< Specifies SAI Block FIFO threshold.
00130                                      This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
00131
00132   uint32_t AudioFrequency;      /*!< Specifies the audio frequency sampling.
00133                                      This parameter can be a value of @ref SAI_Audio_Frequency */
00134
00135   uint32_t Mckdiv;              /*!< Specifies the master clock divider, the parameter will be used if for
00136                                      AudioFrequency the user choice
00137                                      This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
00138
00139   uint32_t MckOverSampling;     /*!< Specifies the master clock oversampling.
00140                                      This parameter can be a value of @ref SAI_Block_Mck_OverSampling */
00141
00142   uint32_t MonoStereoMode;      /*!< Specifies if the mono or stereo mode is selected.
00143                                      This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
00144
00145   uint32_t CompandingMode;      /*!< Specifies the companding mode type.
00146                                      This parameter can be a value of @ref SAI_Block_Companding_Mode */
00147
00148   uint32_t TriState;            /*!< Specifies the companding mode type.
00149                                      This parameter can be a value of @ref SAI_TRIState_Management */
00150
00151   SAI_PdmInitTypeDef PdmInit;   /*!< Specifies the PDM configuration. */
00152
00153   /* This part of the structure is automatically filled if your are using the high level initialisation
00154      function HAL_SAI_InitProtocol */
00155
00156   uint32_t Protocol;        /*!< Specifies the SAI Block protocol.
00157                                  This parameter can be a value of @ref SAI_Block_Protocol */
00158
00159   uint32_t DataSize;        /*!< Specifies the SAI Block data size.
00160                                  This parameter can be a value of @ref SAI_Block_Data_Size */
00161
00162   uint32_t FirstBit;        /*!< Specifies whether data transfers start from MSB or LSB bit.
00163                                  This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
00164
00165   uint32_t ClockStrobing;   /*!< Specifies the SAI Block clock strobing edge sensitivity.
00166                                  This parameter can be a value of @ref SAI_Block_Clock_Strobing */
00167 } SAI_InitTypeDef;
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
00173   * @brief  SAI Frame Init structure definition
00174   * @{
00175   */
00176 typedef struct
00177 {
00178
00179   uint32_t FrameLength;        /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
00180                                     This parameter must be a number between Min_Data = 8 and Max_Data = 256.
00181                                     @note: If master clock MCLK_x pin is declared as an output, the frame length
00182                                            should be aligned to a number equal to power of 2 in order to keep
00183                                            in an audio frame, an integer number of MCLK pulses by bit Clock. */
00184
00185   uint32_t ActiveFrameLength;  /*!< Specifies the Frame synchronization active level length.
00186                                     This Parameter specifies the length in number of bit clock (SCK + 1)
00187                                     of the active level of FS signal in audio frame.
00188                                     This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
00189
00190   uint32_t FSDefinition;       /*!< Specifies the Frame synchronization definition.
00191                                     This parameter can be a value of @ref SAI_Block_FS_Definition */
00192
00193   uint32_t FSPolarity;         /*!< Specifies the Frame synchronization Polarity.
00194                                     This parameter can be a value of @ref SAI_Block_FS_Polarity */
00195
00196   uint32_t FSOffset;           /*!< Specifies the Frame synchronization Offset.
00197                                     This parameter can be a value of @ref SAI_Block_FS_Offset */
00198
00199 } SAI_FrameInitTypeDef;
00200 /**
00201   * @}
00202   */
00203
00204 /** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
00205   * @brief   SAI Block Slot Init Structure definition
00206   * @{
00207   */
00208 typedef struct
00209 {
00210   uint32_t FirstBitOffset;  /*!< Specifies the position of first data transfer bit in the slot.
00211                                  This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
00212
00213   uint32_t SlotSize;        /*!< Specifies the Slot Size.
00214                                  This parameter can be a value of @ref SAI_Block_Slot_Size */
00215
00216   uint32_t SlotNumber;      /*!< Specifies the number of slot in the audio frame.
00217                                  This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
00218
00219   uint32_t SlotActive;      /*!< Specifies the slots in audio frame that will be activated.
00220                                  This parameter can be a value of @ref SAI_Block_Slot_Active */
00221 } SAI_SlotInitTypeDef;
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition
00227   * @brief  SAI handle Structure definition
00228   * @{
00229   */
00230 typedef struct __SAI_HandleTypeDef
00231 {
00232   SAI_Block_TypeDef         *Instance;    /*!< SAI Blockx registers base address */
00233
00234   SAI_InitTypeDef           Init;         /*!< SAI communication parameters */
00235
00236   SAI_FrameInitTypeDef      FrameInit;    /*!< SAI Frame configuration parameters */
00237
00238   SAI_SlotInitTypeDef       SlotInit;     /*!< SAI Slot configuration parameters */
00239
00240   uint8_t                  *pBuffPtr;     /*!< Pointer to SAI transfer Buffer */
00241
00242   uint16_t                  XferSize;     /*!< SAI transfer size */
00243
00244   uint16_t                  XferCount;    /*!< SAI transfer counter */
00245
00246   DMA_HandleTypeDef         *hdmatx;      /*!< SAI Tx DMA handle parameters */
00247
00248   DMA_HandleTypeDef         *hdmarx;      /*!< SAI Rx DMA handle parameters */
00249
00250   SAIcallback               mutecallback; /*!< SAI mute callback */
00251
00252   void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */
00253
00254   HAL_LockTypeDef           Lock;         /*!< SAI locking object */
00255
00256   __IO HAL_SAI_StateTypeDef State;        /*!< SAI communication state */
00257
00258   __IO uint32_t             ErrorCode;    /*!< SAI Error code */
00259 } SAI_HandleTypeDef;
00260 /**
00261   * @}
00262   */
00263
00264 /**
00265   * @}
00266   */
00267
00268 /* Exported constants --------------------------------------------------------*/
00269
00270 /** @defgroup SAI_Exported_Constants SAI Exported Constants
00271   * @{
00272   */
00273
00274 /** @defgroup SAI_Error_Code SAI Error Code
00275   * @{
00276   */
00277 #define HAL_SAI_ERROR_NONE    ((uint32_t)0x00000000U)  /*!< No error */
00278 #define HAL_SAI_ERROR_OVR     ((uint32_t)0x00000001U)  /*!< Overrun Error */
00279 #define HAL_SAI_ERROR_UDR     ((uint32_t)0x00000002U)  /*!< Underrun error */
00280 #define HAL_SAI_ERROR_AFSDET  ((uint32_t)0x00000004U)  /*!< Anticipated Frame synchronisation detection */
00281 #define HAL_SAI_ERROR_LFSDET  ((uint32_t)0x00000008U)  /*!< Late Frame synchronisation detection */
00282 #define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U)  /*!< codec not ready */
00283 #define HAL_SAI_ERROR_WCKCFG  ((uint32_t)0x00000020U)  /*!< Wrong clock configuration */
00284 #define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U)  /*!< Timeout error */
00285 #define HAL_SAI_ERROR_DMA     ((uint32_t)0x00000080U)  /*!< DMA error */
00286 /**
00287   * @}
00288   */
00289
00290 /** @defgroup SAI_Block_SyncExt SAI External synchronisation
00291   * @{
00292   */
00293 #define SAI_SYNCEXT_DISABLE          0
00294 #define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1
00295 #define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2
00296 /**
00297   * @}
00298   */
00299
00300 /** @defgroup SAI_Protocol SAI Supported protocol
00301   * @{
00302   */
00303 #define SAI_I2S_STANDARD      0
00304 #define SAI_I2S_MSBJUSTIFIED  1
00305 #define SAI_I2S_LSBJUSTIFIED  2
00306 #define SAI_PCM_LONG          3
00307 #define SAI_PCM_SHORT         4
00308 /**
00309   * @}
00310   */
00311
00312 /** @defgroup SAI_Protocol_DataSize SAI protocol data size
00313   * @{
00314   */
00315 #define SAI_PROTOCOL_DATASIZE_16BIT         0
00316 #define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1
00317 #define SAI_PROTOCOL_DATASIZE_24BIT         2
00318 #define SAI_PROTOCOL_DATASIZE_32BIT         3
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup SAI_Audio_Frequency SAI Audio Frequency
00324   * @{
00325   */
00326 #define SAI_AUDIO_FREQUENCY_192K          ((uint32_t)192000U)
00327 #define SAI_AUDIO_FREQUENCY_96K           ((uint32_t)96000U)
00328 #define SAI_AUDIO_FREQUENCY_48K           ((uint32_t)48000U)
00329 #define SAI_AUDIO_FREQUENCY_44K           ((uint32_t)44100U)
00330 #define SAI_AUDIO_FREQUENCY_32K           ((uint32_t)32000U)
00331 #define SAI_AUDIO_FREQUENCY_22K           ((uint32_t)22050U)
00332 #define SAI_AUDIO_FREQUENCY_16K           ((uint32_t)16000U)
00333 #define SAI_AUDIO_FREQUENCY_11K           ((uint32_t)11025U)
00334 #define SAI_AUDIO_FREQUENCY_8K            ((uint32_t)8000U)
00335 #define SAI_AUDIO_FREQUENCY_MCKDIV        ((uint32_t)0U)
00336 /**
00337   * @}
00338   */
00339
00340 /** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling
00341   * @{
00342   */
00343 #define SAI_MCK_OVERSAMPLING_DISABLE  ((uint32_t)0x00000000U)
00344 #define SAI_MCK_OVERSAMPLING_ENABLE   ((uint32_t)SAI_xCR1_OSR)
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable
00350   * @{
00351   */
00352 #define SAI_PDM_CLOCK1_ENABLE  ((uint32_t)SAI_PDMCR_CKEN1)
00353 #define SAI_PDM_CLOCK2_ENABLE  ((uint32_t)SAI_PDMCR_CKEN2)
00354 #define SAI_PDM_CLOCK3_ENABLE  ((uint32_t)SAI_PDMCR_CKEN3)
00355 #define SAI_PDM_CLOCK4_ENABLE  ((uint32_t)SAI_PDMCR_CKEN4)
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup SAI_Block_Mode SAI Block Mode
00361   * @{
00362   */
00363 #define SAI_MODEMASTER_TX         ((uint32_t)0x00000000U)
00364 #define SAI_MODEMASTER_RX         ((uint32_t)SAI_xCR1_MODE_0)
00365 #define SAI_MODESLAVE_TX          ((uint32_t)SAI_xCR1_MODE_1)
00366 #define SAI_MODESLAVE_RX          ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))
00367
00368 /**
00369   * @}
00370   */
00371
00372 /** @defgroup SAI_Block_Protocol SAI Block Protocol
00373   * @{
00374   */
00375 #define SAI_FREE_PROTOCOL                 ((uint32_t)0x00000000U)
00376 #define SAI_SPDIF_PROTOCOL                ((uint32_t)SAI_xCR1_PRTCFG_0)
00377 #define SAI_AC97_PROTOCOL                 ((uint32_t)SAI_xCR1_PRTCFG_1)
00378 /**
00379   * @}
00380   */
00381
00382 /** @defgroup SAI_Block_Data_Size SAI Block Data Size
00383   * @{
00384   */
00385 #define SAI_DATASIZE_8     ((uint32_t)SAI_xCR1_DS_1)
00386 #define SAI_DATASIZE_10    ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
00387 #define SAI_DATASIZE_16    ((uint32_t)SAI_xCR1_DS_2)
00388 #define SAI_DATASIZE_20    ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
00389 #define SAI_DATASIZE_24    ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
00390 #define SAI_DATASIZE_32    ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
00391 /**
00392   * @}
00393   */
00394
00395 /** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
00396   * @{
00397   */
00398 #define SAI_FIRSTBIT_MSB                  ((uint32_t)0x00000000U)
00399 #define SAI_FIRSTBIT_LSB                  ((uint32_t)SAI_xCR1_LSBFIRST)
00400 /**
00401   * @}
00402   */
00403
00404 /** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
00405   * @{
00406   */
00407 #define SAI_CLOCKSTROBING_FALLINGEDGE     0
00408 #define SAI_CLOCKSTROBING_RISINGEDGE      1
00409 /**
00410   * @}
00411   */
00412
00413 /** @defgroup SAI_Block_Synchronization SAI Block Synchronization
00414   * @{
00415   */
00416 #define SAI_ASYNCHRONOUS                  0 /*!< Asynchronous */
00417 #define SAI_SYNCHRONOUS                   1 /*!< Synchronous with other block of same SAI */
00418 #define SAI_SYNCHRONOUS_EXT_SAI1          2 /*!< Synchronous with other SAI, SAI1 */
00419 #define SAI_SYNCHRONOUS_EXT_SAI2          3 /*!< Synchronous with other SAI, SAI2 */
00420 /**
00421   * @}
00422   */
00423
00424 /** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
00425   * @{
00426   */
00427 #define SAI_OUTPUTDRIVE_DISABLE          ((uint32_t)0x00000000U)
00428 #define SAI_OUTPUTDRIVE_ENABLE           ((uint32_t)SAI_xCR1_OUTDRIV)
00429 /**
00430   * @}
00431   */
00432
00433 /** @defgroup SAI_Block_NoDivider SAI Block NoDivider
00434   * @{
00435   */
00436 #define SAI_MASTERDIVIDER_ENABLE         ((uint32_t)0x00000000U)
00437 #define SAI_MASTERDIVIDER_DISABLE        ((uint32_t)SAI_xCR1_NOMCK)
00438 /**
00439   * @}
00440   */
00441
00442
00443 /** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
00444   * @{
00445   */
00446 #define SAI_FS_STARTFRAME                 ((uint32_t)0x00000000U)
00447 #define SAI_FS_CHANNEL_IDENTIFICATION     ((uint32_t)SAI_xFRCR_FSDEF)
00448 /**
00449   * @}
00450   */
00451
00452 /** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
00453   * @{
00454   */
00455 #define SAI_FS_ACTIVE_LOW                  ((uint32_t)0x00000000U)
00456 #define SAI_FS_ACTIVE_HIGH                 ((uint32_t)SAI_xFRCR_FSPOL)
00457 /**
00458   * @}
00459   */
00460
00461 /** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
00462   * @{
00463   */
00464 #define SAI_FS_FIRSTBIT                   ((uint32_t)0x00000000U)
00465 #define SAI_FS_BEFOREFIRSTBIT             ((uint32_t)SAI_xFRCR_FSOFF)
00466 /**
00467   * @}
00468   */
00469
00470
00471   /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
00472   * @{
00473   */
00474 #define SAI_SLOTSIZE_DATASIZE             ((uint32_t)0x00000000U)
00475 #define SAI_SLOTSIZE_16B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
00476 #define SAI_SLOTSIZE_32B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
00477 /**
00478   * @}
00479   */
00480
00481 /** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
00482   * @{
00483   */
00484 #define SAI_SLOT_NOTACTIVE           ((uint32_t)0x00000000U)
00485 #define SAI_SLOTACTIVE_0             ((uint32_t)0x00000001U)
00486 #define SAI_SLOTACTIVE_1             ((uint32_t)0x00000002U)
00487 #define SAI_SLOTACTIVE_2             ((uint32_t)0x00000004U)
00488 #define SAI_SLOTACTIVE_3             ((uint32_t)0x00000008U)
00489 #define SAI_SLOTACTIVE_4             ((uint32_t)0x00000010U)
00490 #define SAI_SLOTACTIVE_5             ((uint32_t)0x00000020U)
00491 #define SAI_SLOTACTIVE_6             ((uint32_t)0x00000040U)
00492 #define SAI_SLOTACTIVE_7             ((uint32_t)0x00000080U)
00493 #define SAI_SLOTACTIVE_8             ((uint32_t)0x00000100U)
00494 #define SAI_SLOTACTIVE_9             ((uint32_t)0x00000200U)
00495 #define SAI_SLOTACTIVE_10            ((uint32_t)0x00000400U)
00496 #define SAI_SLOTACTIVE_11            ((uint32_t)0x00000800U)
00497 #define SAI_SLOTACTIVE_12            ((uint32_t)0x00001000U)
00498 #define SAI_SLOTACTIVE_13            ((uint32_t)0x00002000U)
00499 #define SAI_SLOTACTIVE_14            ((uint32_t)0x00004000U)
00500 #define SAI_SLOTACTIVE_15            ((uint32_t)0x00008000U)
00501 #define SAI_SLOTACTIVE_ALL           ((uint32_t)0x0000FFFFU)
00502 /**
00503   * @}
00504   */
00505
00506 /** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
00507   * @{
00508   */
00509 #define SAI_STEREOMODE               ((uint32_t)0x00000000U)
00510 #define SAI_MONOMODE                 ((uint32_t)SAI_xCR1_MONO)
00511 /**
00512   * @}
00513   */
00514
00515 /** @defgroup SAI_TRIState_Management SAI TRIState Management
00516   * @{
00517   */
00518 #define SAI_OUTPUT_NOTRELEASED    ((uint32_t)0x00000000U)
00519 #define SAI_OUTPUT_RELEASED       ((uint32_t)SAI_xCR2_TRIS)
00520 /**
00521   * @}
00522   */
00523
00524 /** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
00525   * @{
00526   */
00527 #define SAI_FIFOTHRESHOLD_EMPTY  ((uint32_t)0x00000000U)
00528 #define SAI_FIFOTHRESHOLD_1QF    ((uint32_t)(SAI_xCR2_FTH_0))
00529 #define SAI_FIFOTHRESHOLD_HF     ((uint32_t)(SAI_xCR2_FTH_1))
00530 #define SAI_FIFOTHRESHOLD_3QF    ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
00531 #define SAI_FIFOTHRESHOLD_FULL   ((uint32_t)(SAI_xCR2_FTH_2))
00532 /**
00533   * @}
00534   */
00535
00536 /** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
00537   * @{
00538   */
00539 #define SAI_NOCOMPANDING                 ((uint32_t)0x00000000U)
00540 #define SAI_ULAW_1CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1))
00541 #define SAI_ALAW_1CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
00542 #define SAI_ULAW_2CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
00543 #define SAI_ALAW_2CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))
00544 /**
00545   * @}
00546   */
00547
00548 /** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
00549   * @{
00550   */
00551 #define SAI_ZERO_VALUE                     ((uint32_t)0x00000000U)
00552 #define SAI_LAST_SENT_VALUE                ((uint32_t)SAI_xCR2_MUTEVAL)
00553 /**
00554   * @}
00555   */
00556
00557 /** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
00558   * @{
00559   */
00560 #define SAI_IT_OVRUDR                     ((uint32_t)SAI_xIMR_OVRUDRIE)
00561 #define SAI_IT_MUTEDET                    ((uint32_t)SAI_xIMR_MUTEDETIE)
00562 #define SAI_IT_WCKCFG                     ((uint32_t)SAI_xIMR_WCKCFGIE)
00563 #define SAI_IT_FREQ                       ((uint32_t)SAI_xIMR_FREQIE)
00564 #define SAI_IT_CNRDY                      ((uint32_t)SAI_xIMR_CNRDYIE)
00565 #define SAI_IT_AFSDET                     ((uint32_t)SAI_xIMR_AFSDETIE)
00566 #define SAI_IT_LFSDET                     ((uint32_t)SAI_xIMR_LFSDETIE)
00567 /**
00568   * @}
00569   */
00570
00571 /** @defgroup SAI_Block_Flags_Definition  SAI Block Flags Definition
00572   * @{
00573   */
00574 #define SAI_FLAG_OVRUDR                   ((uint32_t)SAI_xSR_OVRUDR)
00575 #define SAI_FLAG_MUTEDET                  ((uint32_t)SAI_xSR_MUTEDET)
00576 #define SAI_FLAG_WCKCFG                   ((uint32_t)SAI_xSR_WCKCFG)
00577 #define SAI_FLAG_FREQ                     ((uint32_t)SAI_xSR_FREQ)
00578 #define SAI_FLAG_CNRDY                    ((uint32_t)SAI_xSR_CNRDY)
00579 #define SAI_FLAG_AFSDET                   ((uint32_t)SAI_xSR_AFSDET)
00580 #define SAI_FLAG_LFSDET                   ((uint32_t)SAI_xSR_LFSDET)
00581 /**
00582   * @}
00583   */
00584
00585 /** @defgroup SAI_Block_Fifo_Status_Level   SAI Block Fifo Status Level
00586   * @{
00587   */
00588 #define SAI_FIFOSTATUS_EMPTY              ((uint32_t)0x00000000U)
00589 #define SAI_FIFOSTATUS_LESS1QUARTERFULL   ((uint32_t)0x00010000U)
00590 #define SAI_FIFOSTATUS_1QUARTERFULL       ((uint32_t)0x00020000U)
00591 #define SAI_FIFOSTATUS_HALFFULL           ((uint32_t)0x00030000U)
00592 #define SAI_FIFOSTATUS_3QUARTERFULL       ((uint32_t)0x00040000U)
00593 #define SAI_FIFOSTATUS_FULL               ((uint32_t)0x00050000U)
00594 /**
00595   * @}
00596   */
00597
00598 /**
00599   * @}
00600   */
00601
00602 /* Exported macro ------------------------------------------------------------*/
00603
00604 /** @defgroup SAI_Exported_Macros SAI Exported Macros
00605  *  @brief macros to handle interrupts and specific configurations
00606  * @{
00607  */
00608
00609 /** @brief Reset SAI handle state.
00610   * @param  __HANDLE__: specifies the SAI Handle.
00611   * @retval None
00612   */
00613 #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
00614
00615 /** @brief  Enable or disable the specified SAI interrupts.
00616   * @param  __HANDLE__: specifies the SAI Handle.
00617   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
00618   *         This parameter can be one of the following values:
00619   *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
00620   *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
00621   *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
00622   *            @arg SAI_IT_FREQ: FIFO request interrupt enable
00623   *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
00624   *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
00625   *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
00626   * @retval None
00627   */
00628 #define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
00629 #define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
00630
00631 /** @brief  Check whether the specified SAI interrupt source is enabled or not.
00632   * @param  __HANDLE__: specifies the SAI Handle.
00633   * @param  __INTERRUPT__: specifies the SAI interrupt source to check.
00634   *         This parameter can be one of the following values:
00635   *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
00636   *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
00637   *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
00638   *            @arg SAI_IT_FREQ: FIFO request interrupt enable
00639   *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
00640   *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
00641   *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
00642   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00643   */
00644 #define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00645
00646 /** @brief  Check whether the specified SAI flag is set or not.
00647   * @param  __HANDLE__: specifies the SAI Handle.
00648   * @param  __FLAG__: specifies the flag to check.
00649   *         This parameter can be one of the following values:
00650   *            @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
00651   *            @arg SAI_FLAG_MUTEDET: Mute detection flag.
00652   *            @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
00653   *            @arg SAI_FLAG_FREQ: FIFO request flag.
00654   *            @arg SAI_FLAG_CNRDY: Codec not ready flag.
00655   *            @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
00656   *            @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
00657   * @retval The new state of __FLAG__ (TRUE or FALSE).
00658   */
00659 #define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00660
00661 /** @brief  Clear the specified SAI pending flag.
00662   * @param  __HANDLE__: specifies the SAI Handle.
00663   * @param  __FLAG__: specifies the flag to check.
00664   *          This parameter can be any combination of the following values:
00665   *            @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
00666   *            @arg SAI_FLAG_MUTEDET: Clear Mute detection
00667   *            @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
00668   *            @arg SAI_FLAG_FREQ: Clear FIFO request
00669   *            @arg SAI_FLAG_CNRDY: Clear Codec not ready
00670   *            @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
00671   *            @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
00672   *
00673   * @retval None
00674   */
00675 #define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
00676
00677 #define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SAI_xCR1_SAIEN)
00678 #define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &=  ~SAI_xCR1_SAIEN)
00679
00680  /**
00681   * @}
00682   */
00683
00684 /* Include SAI HAL Extension module */
00685 #include "stm32h7xx_hal_sai_ex.h"
00686
00687 /* Exported functions --------------------------------------------------------*/
00688
00689 /** @addtogroup SAI_Exported_Functions
00690   * @{
00691   */
00692
00693 /* Initialization/de-initialization functions  ********************************/
00694
00695 /** @addtogroup SAI_Exported_Functions_Group1
00696   * @{
00697   */
00698 HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
00699 HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
00700 HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);
00701 void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
00702 void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
00703
00704 /**
00705   * @}
00706   */
00707
00708 /* I/O operation functions  ***************************************************/
00709
00710 /** @addtogroup SAI_Exported_Functions_Group2
00711   * @{
00712   */
00713 /* Blocking mode: Polling */
00714 HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00715 HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00716
00717 /* Non-Blocking mode: Interrupt */
00718 HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00719 HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00720
00721 /* Non-Blocking mode: DMA */
00722 HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00723 HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00724 HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
00725 HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
00726 HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
00727
00728 /* Abort function */
00729 HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
00730
00731 /* Mute management */
00732 HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
00733 HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
00734 HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
00735 HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
00736
00737 /* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
00738 void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
00739 void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
00740 void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
00741 void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
00742 void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
00743 void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
00744 /**
00745   * @}
00746   */
00747
00748 /** @addtogroup SAI_Exported_Functions_Group3
00749   * @{
00750   */
00751 /* Peripheral State functions  ************************************************/
00752 HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
00753 uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
00754 /**
00755   * @}
00756   */
00757
00758 /**
00759   * @}
00760   */
00761
00762 /* Private macros ------------------------------------------------------------*/
00763 /** @addtogroup SAI_Private_Macros
00764   * @{
00765   */
00766 #define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\
00767                                      ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
00768                                      ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
00769
00770 #define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)   (((PROTOCOL) == SAI_I2S_STANDARD)     ||\
00771                                                ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
00772                                                ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
00773                                                ((PROTOCOL) == SAI_PCM_LONG)         ||\
00774                                                ((PROTOCOL) == SAI_PCM_SHORT))
00775
00776 #define IS_SAI_PROTOCOL_DATASIZE(DATASIZE)   (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT)         ||\
00777                                               ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
00778                                               ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT)         ||\
00779                                               ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
00780
00781 #define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
00782                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_48K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
00783                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_32K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
00784                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_16K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
00785                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_8K)   || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
00786
00787 #define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \
00788                                               ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE))
00789
00790 #define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE)   ((1U <= (VALUE)) && ((VALUE) <= 4U))
00791
00792 #define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \
00793                                        (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE | \
00794                                                      SAI_PDM_CLOCK3_ENABLE | SAI_PDM_CLOCK4_ENABLE)) == 0U))
00795
00796 #define IS_SAI_BLOCK_MODE(MODE)  (((MODE) == SAI_MODEMASTER_TX) || \
00797                                   ((MODE) == SAI_MODEMASTER_RX) || \
00798                                   ((MODE) == SAI_MODESLAVE_TX)  || \
00799                                   ((MODE) == SAI_MODESLAVE_RX))
00800
00801 #define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL)  || \
00802                                          ((PROTOCOL) == SAI_AC97_PROTOCOL)  || \
00803                                          ((PROTOCOL) == SAI_SPDIF_PROTOCOL))
00804
00805 #define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8)  || \
00806                                          ((DATASIZE) == SAI_DATASIZE_10) || \
00807                                          ((DATASIZE) == SAI_DATASIZE_16) || \
00808                                          ((DATASIZE) == SAI_DATASIZE_20) || \
00809                                          ((DATASIZE) == SAI_DATASIZE_24) || \
00810                                          ((DATASIZE) == SAI_DATASIZE_32))
00811
00812 #define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
00813                                      ((BIT) == SAI_FIRSTBIT_LSB))
00814
00815 #define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
00816                                             ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
00817
00818 #define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)         || \
00819                                        ((SYNCHRO) == SAI_SYNCHRONOUS)          || \
00820                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \
00821                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
00822
00823 #define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
00824                                           ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
00825
00826 #define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
00827                                            ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
00828
00829 #define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
00830
00831 #define IS_SAI_BLOCK_MUTE_VALUE(VALUE)    (((VALUE) == SAI_ZERO_VALUE)     || \
00832                                            ((VALUE) == SAI_LAST_SENT_VALUE))
00833
00834 #define IS_SAI_BLOCK_COMPANDING_MODE(MODE)    (((MODE) == SAI_NOCOMPANDING)         || \
00835                                                ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
00836                                                ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
00837                                                ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
00838                                                ((MODE) == SAI_ALAW_2CPL_COMPANDING))
00839
00840 #define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY)   || \
00841                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF)     || \
00842                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF)      || \
00843                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF)     || \
00844                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
00845
00846 #define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
00847                                                  ((STATE) == SAI_OUTPUT_RELEASED))
00848
00849 #define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
00850                                        ((MODE) == SAI_STEREOMODE))
00851
00852 #define IS_SAI_SLOT_ACTIVE(ACTIVE)  ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
00853
00854 #define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
00855
00856 #define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
00857                                       ((SIZE) == SAI_SLOTSIZE_16B)      || \
00858                                       ((SIZE) == SAI_SLOTSIZE_32B))
00859
00860 #define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
00861
00862 #define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
00863                                         ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
00864
00865 #define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
00866                                             ((POLARITY) == SAI_FS_ACTIVE_HIGH))
00867
00868 #define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
00869                                                 ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
00870
00871 #define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
00872
00873 #define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
00874
00875 #define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))
00876
00877 /**
00878   * @}
00879   */
00880
00881 /* Private functions ---------------------------------------------------------*/
00882 /** @defgroup SAI_Private_Functions SAI Private Functions
00883   * @{
00884   */
00885
00886 /**
00887   * @}
00888   */
00889
00890 /**
00891   * @}
00892   */
00893
00894 /**
00895   * @}
00896   */
00897
00898 #ifdef __cplusplus
00899 }
00900 #endif
00901
00902 #endif /* __STM32H7xx_HAL_SAI_H */
00903
00904 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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STM32H753xx HAL User Manual: stm32h7xx_hal_sai_ex.c Source File

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stm32h7xx_hal_sai_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sai_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   SAI Extended HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionality of the SAI Peripheral Controller:
00010   *           + Modify PDM microphone delays.
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00016   *
00017   * Redistribution and use in source and binary forms, with or without modification,
00018   * are permitted provided that the following conditions are met:
00019   *   1. Redistributions of source code must retain the above copyright notice,
00020   *      this list of conditions and the following disclaimer.
00021   *   2. Redistributions in binary form must reproduce the above copyright notice,
00022   *      this list of conditions and the following disclaimer in the documentation
00023   *      and/or other materials provided with the distribution.
00024   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00025   *      may be used to endorse or promote products derived from this software
00026   *      without specific prior written permission.
00027   *
00028   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00029   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00030   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00031   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00032   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00033   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00034   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00035   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00036   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00037   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00038   *
00039   ******************************************************************************
00040   */
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32h7xx_hal.h"
00044
00045 /** @addtogroup STM32H7xx_HAL_Driver
00046   * @{
00047   */
00048 #ifdef HAL_SAI_MODULE_ENABLED
00049
00050 /** @defgroup SAIEx SAIEx
00051   * @brief SAI Extended HAL module driver
00052   * @{
00053   */
00054
00055 /* Private types -------------------------------------------------------------*/
00056 /* Private variables ---------------------------------------------------------*/
00057 /* Private constants ---------------------------------------------------------*/
00058
00059 #define SAI_PDM_DELAY_MASK          0x77U
00060 #define SAI_PDM_DELAY_OFFSET        8U
00061 #define SAI_PDM_RIGHT_DELAY_OFFSET  4U
00062
00063 /* Private macros ------------------------------------------------------------*/
00064 /* Private functions ---------------------------------------------------------*/
00065 /* Exported functions --------------------------------------------------------*/
00066
00067 /** @defgroup SAIEx_Exported_Functions SAIEx Extended Exported Functions
00068   * @{
00069   */
00070
00071 /** @defgroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
00072   * @brief    SAIEx control functions
00073  *
00074 @verbatim
00075  ===============================================================================
00076                  ##### Extended features functions #####
00077  ===============================================================================
00078     [..]  This section provides functions allowing to:
00079       (+) Modify PDM microphone delays
00080
00081 @endverbatim
00082   * @{
00083   */
00084
00085 /**
00086   * @brief  Configure PDM microphone delays.
00087   * @param  hsai: SAI handle.
00088   * @param  pdmMicDelay: Microphone delays configuration.
00089   * @retval HAL status
00090   */
00091 HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
00092 {
00093   HAL_StatusTypeDef status = HAL_OK;
00094   SAI_TypeDef *SaiBaseAddress = NULL;
00095
00096   /* Get the SAI base address according to the SAI handle */
00097   SaiBaseAddress = (hsai->Instance == SAI1_Block_A)  ? SAI1 : \
00098                    ((hsai->Instance == SAI2_Block_A) ? SAI2 : \
00099                    ((hsai->Instance == SAI3_Block_A) ? SAI3 : \
00100                    ((hsai->Instance == SAI4_Block_A) ? SAI4 : \
00101                      NULL)));
00102   if((SaiBaseAddress != NULL) && (hsai->State != HAL_SAI_STATE_RESET))
00103   {
00104     /* Check microphone delay parameters */
00105     assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(pdmMicDelay->MicPair));
00106     assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->LeftDelay));
00107     assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->RightDelay));
00108
00109     /* Reset current delays for specified microphone */
00110     SaiBaseAddress->PDMDLY &= ~(SAI_PDM_DELAY_MASK << (SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1)));
00111
00112     /* Apply new microphone delays */
00113     SaiBaseAddress->PDMDLY |= (((pdmMicDelay->RightDelay << SAI_PDM_RIGHT_DELAY_OFFSET) | pdmMicDelay->LeftDelay) << \
00114                                 (SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1)));
00115   }
00116   else
00117   {
00118     status = HAL_ERROR;
00119   }
00120   return status;
00121 }
00122
00123 /**
00124   * @}
00125   */
00126
00127 /**
00128   * @}
00129   */
00130
00131 /**
00132   * @}
00133   */
00134
00135 #endif /* HAL_SAI_MODULE_ENABLED */
00136 /**
00137   * @}
00138   */
00139
00140 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sai_ex.h Source File

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stm32h7xx_hal_sai_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sai_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of SAI HAL extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_SAI_EX_H
00040 #define __STM32H7xx_HAL_SAI_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SAIEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup SAIEx_Exported_Types SAIEx Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  PDM microphone delay structure definition
00065   */
00066 typedef struct
00067 {
00068   uint32_t MicPair;     /*!< Specifies which pair of microphones is selected.
00069                              This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
00070
00071   uint32_t LeftDelay;   /*!< Specifies the delay in PDM clock unit to apply on left microphone.
00072                              This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
00073
00074   uint32_t RightDelay;  /*!< Specifies the delay in PDM clock unit to apply on right microphone.
00075                              This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
00076 }SAIEx_PdmMicDelayParamTypeDef;
00077
00078 /**
00079   * @}
00080   */
00081
00082 /* Exported constants --------------------------------------------------------*/
00083 /* Exported macros -----------------------------------------------------------*/
00084 /* Exported functions --------------------------------------------------------*/
00085
00086 /** @addtogroup SAIEx_Exported_Functions SAIEx Extended Exported Functions
00087   * @{
00088   */
00089
00090 /** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
00091   * @{
00092   */
00093
00094 HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay);
00095
00096 /**
00097   * @}
00098   */
00099
00100 /**
00101   * @}
00102   */
00103
00104 /* Private macros ------------------------------------------------------------*/
00105
00106 /** @addtogroup SAIEx_Private_Macros SAIEx Extended Private Macros
00107   * @{
00108   */
00109
00110 #define IS_SAI_PDM_MIC_DELAY(VALUE)   ((VALUE) <= 7U)
00111
00112 /**
00113   * @}
00114   */
00115
00116 /**
00117   * @}
00118   */
00119
00120 /**
00121   * @}
00122   */
00123
00124 #ifdef __cplusplus
00125 }
00126 #endif
00127
00128 #endif /* __STM32H7xx_HAL_SAI_EX_H */
00129
00130 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sd.c Source File

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stm32h7xx_hal_sd.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sd.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   SD card HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Secure Digital (SD) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019   [..]
00020     This driver implements a high level communication layer for read and write from/to
00021     this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
00022     the user in HAL_SD_MspInit() function (MSP layer).
00023     Basically, the MSP layer configuration should be the same as we provide in the
00024     examples.
00025     You can easily tailor this configuration according to hardware resources.
00026
00027   [..]
00028     This driver is a generic layered driver for SDMMC memories which uses the HAL
00029     SDMMC driver functions to interface with SD and uSD cards devices.
00030     It is used as follows:
00031
00032     (#)Initialize the SDMMC low level resources by implement the HAL_SD_MspInit() API:
00033         (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
00034         (##) SDMMC pins configuration for SD card
00035             (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
00036             (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
00037                   and according to your pin assignment;
00038         (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
00039             (+++) Configure the SDMMC interrupt priorities using functions HAL_NVIC_SetPriority();
00040             (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
00041             (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT()
00042                   and __HAL_SD_DISABLE_IT() inside the communication process.
00043             (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
00044                   and __HAL_SD_CLEAR_IT()
00045         (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC IP are used.
00046
00047     (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
00048
00049
00050   *** SD Card Initialization and configuration ***
00051   ================================================
00052   [..]
00053     To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
00054     the SD Card and put it into StandBy State (Ready for data transfer).
00055     This function provide the following operations:
00056
00057     (#) Apply the SD Card initialization process at 400KHz and check the SD Card
00058         type (Standard Capacity or High Capacity). You can change or adapt this
00059         frequency by adjusting the "ClockDiv" field.
00060         The SD Card frequency (SDMMC_CK) is computed as follows:
00061
00062            SDMMC_CK = SDMMCCLK / (2 * ClockDiv)
00063
00064         In initialization mode and according to the SD Card standard,
00065         make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
00066
00067     (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo
00068         structure. This structure provide also ready computed SD Card capacity
00069         and Block size.
00070
00071         -@- These information are stored in SD handle structure in case of future use.
00072
00073     (#) Configure the SD Card Data transfer frequency. You can change or adapt this
00074         frequency by adjusting the "ClockDiv" field.
00075         In transfer mode and according to the SD Card standard, make sure that the
00076         SDMMC_CK frequency doesn't exceed 25MHz and 100MHz in High-speed mode switch.
00077
00078     (#) Select the corresponding SD Card according to the address read with the step 2.
00079
00080     (#) Configure the SD Card in wide bus mode: 4-bits data.
00081
00082   *** SD Card Read operation ***
00083   ==============================
00084   [..]
00085     (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
00086         This function support only 512-bytes block length (the block size should be
00087         chosen as 512 bytes).
00088         You can choose either one block read operation or multiple block read operation
00089         by adjusting the "NumberOfBlocks" parameter.
00090
00091     (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
00092         This function support only 512-bytes block length (the block size should be
00093         chosen as 512 bytes).
00094         You can choose either one block read operation or multiple block read operation
00095         by adjusting the "NumberOfBlocks" parameter.
00096
00097   *** SD Card Write operation ***
00098   ===============================
00099   [..]
00100     (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
00101         This function support only 512-bytes block length (the block size should be
00102         chosen as 512 bytes).
00103         You can choose either one block read operation or multiple block read operation
00104         by adjusting the "NumberOfBlocks" parameter.
00105
00106     (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
00107         This function support only 512-bytes block length (the block size should be
00108         chosen as 512 byte).
00109         You can choose either one block read operation or multiple block read operation
00110         by adjusting the "NumberOfBlocks" parameter.
00111
00112   *** SD card status ***
00113   ======================
00114   [..]
00115     (+) At any time, you can check the SD Card status and get the SD card state
00116         by using the HAL_SD_GetStatusInfo() function. This function checks first if the
00117         SD card is still connected and then get the internal SD Card transfer state.
00118
00119   *** SD HAL driver macros list ***
00120   ==================================
00121   [..]
00122     Below the list of most used macros in SD HAL driver.
00123
00124     (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt
00125     (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt
00126     (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
00127     (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags
00128
00129     (@) You can refer to the SD HAL driver header file for more useful macros
00130
00131   @endverbatim
00132   ******************************************************************************
00133   * @attention
00134   *
00135   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00136   *
00137   * Redistribution and use in source and binary forms, with or without modification,
00138   * are permitted provided that the following conditions are met:
00139   *   1. Redistributions of source code must retain the above copyright notice,
00140   *      this list of conditions and the following disclaimer.
00141   *   2. Redistributions in binary form must reproduce the above copyright notice,
00142   *      this list of conditions and the following disclaimer in the documentation
00143   *      and/or other materials provided with the distribution.
00144   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00145   *      may be used to endorse or promote products derived from this software
00146   *      without specific prior written permission.
00147   *
00148   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00149   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00150   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00151   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00152   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00153   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00154   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00155   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00156   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00157   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00158   *
00159   ******************************************************************************
00160   */
00161
00162 /* Includes ------------------------------------------------------------------*/
00163 #include "stm32h7xx_hal.h"
00164
00165 /** @addtogroup STM32H7xx_HAL_Driver
00166   * @{
00167   */
00168
00169 /** @addtogroup SD
00170   * @{
00171   */
00172
00173 #ifdef HAL_SD_MODULE_ENABLED
00174
00175 /* Private typedef -----------------------------------------------------------*/
00176 /* Private define ------------------------------------------------------------*/
00177 /** @addtogroup SD_Private_Defines
00178   * @{
00179   */
00180
00181 /**
00182   * @}
00183   */
00184
00185
00186 /* Private macro -------------------------------------------------------------*/
00187 /* Private variables ---------------------------------------------------------*/
00188 /* Private function prototypes -----------------------------------------------*/
00189 /* Private functions ---------------------------------------------------------*/
00190 /** @defgroup SD_Private_Functions SD Private Functions
00191   * @{
00192   */
00193 static uint32_t SD_InitCard(SD_HandleTypeDef *hsd);
00194 static uint32_t SD_PowerON(SD_HandleTypeDef *hsd);
00195 static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
00196 static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
00197 static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd);
00198 static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);
00199 static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
00200 static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd);
00201 static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd);
00202 static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd);
00203 #if (USE_SD_TRANSCEIVER != 0U)
00204 static uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd);
00205 #endif /* USE_SD_TRANSCEIVER */
00206
00207 /**
00208   * @}
00209   */
00210 /* Exported functions --------------------------------------------------------*/
00211 /** @addtogroup SD_Exported_Functions
00212   * @{
00213   */
00214
00215 /** @addtogroup SD_Exported_Functions_Group1
00216  *  @brief   Initialization and de-initialization functions
00217  *
00218 @verbatim
00219   ==============================================================================
00220           ##### Initialization and de-initialization functions #####
00221   ==============================================================================
00222   [..]
00223     This section provides functions allowing to initialize/de-initialize the SD
00224     card device to be ready for use.
00225
00226 @endverbatim
00227   * @{
00228   */
00229
00230 /**
00231   * @brief  Initializes the SD according to the specified parameters in the
00232             SD_HandleTypeDef and create the associated handle.
00233   * @param  hsd: Pointer to the SD handle
00234   * @retval HAL status
00235   */
00236 HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
00237 {
00238   /* Check the SD handle allocation */
00239   if(hsd == NULL)
00240   {
00241     return HAL_ERROR;
00242   }
00243
00244   /* Check the parameters */
00245   assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));
00246   assert_param(IS_SDMMC_CLOCK_EDGE(hsd->Init.ClockEdge));
00247   assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));
00248   assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide));
00249   assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
00250   assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv));
00251
00252   if(hsd->State == HAL_SD_STATE_RESET)
00253   {
00254     /* Allocate lock resource and initialize it */
00255     hsd->Lock = HAL_UNLOCKED;
00256     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00257     HAL_SD_MspInit(hsd);
00258   }
00259
00260   hsd->State = HAL_SD_STATE_BUSY;
00261
00262   /* Initialize the Card parameters */
00263   if(HAL_SD_InitCard(hsd) == HAL_ERROR)
00264   {
00265     return HAL_ERROR;
00266   }
00267
00268   /* Configure the bus wide */
00269   if(HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) == HAL_ERROR)
00270   {
00271     return HAL_ERROR;
00272   }
00273 #if (USE_SD_TRANSCEIVER != 0U)
00274     if((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
00275        (hsd->SdCard.CardType == CARD_SDHC_SDXC))
00276     {
00277       hsd->Instance->CLKCR |= 0x00100000;
00278       /* Enable High Speed */
00279       if(SD_HighSpeed(hsd) == HAL_ERROR)
00280       {
00281         return HAL_ERROR;
00282       }
00283     }
00284 #endif /* USE_SD_TRANSCEIVER */
00285
00286   /* Initialize the error code */
00287   hsd->ErrorCode = HAL_DMA_ERROR_NONE;
00288
00289   /* Initialize the SD operation */
00290   hsd->Context = SD_CONTEXT_NONE;
00291
00292   /* Initialize the SD state */
00293   hsd->State = HAL_SD_STATE_READY;
00294
00295   return HAL_OK;
00296 }
00297
00298 /**
00299   * @brief  Initializes the SD Card according to the specified parameters in the
00300   * @brief  Initializes the SD Card.
00301   * @param  hsd: Pointer to SD handle
00302   * @note   This function initializes the SD card. It could be used when a card
00303             re-initialization is needed.
00304   * @retval HAL status
00305   */
00306 HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
00307 {
00308   uint32_t errorstate = HAL_SD_ERROR_NONE;
00309   SD_InitTypeDef Init;
00310
00311   /* Default SDMMC peripheral configuration for SD card initialization */
00312   Init.ClockEdge           = SDMMC_CLOCK_EDGE_RISING;
00313   Init.ClockPowerSave      = SDMMC_CLOCK_POWER_SAVE_DISABLE;
00314   Init.BusWide             = SDMMC_BUS_WIDE_1B;
00315   Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
00316   Init.ClockDiv            = SDMMC_INIT_CLK_DIV;
00317
00318 #if (USE_SD_TRANSCEIVER != 0U)
00319     /* Set Transceiver polarity */
00320     hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
00321 #endif /* USE_SD_TRANSCEIVER  */
00322
00323   /* Initialize SDMMC peripheral interface with default configuration */
00324   SDMMC_Init(hsd->Instance, Init);
00325
00326   /* Set Power State to ON */
00327   SDMMC_PowerState_ON(hsd->Instance);
00328
00329
00330   /* Identify card operating voltage */
00331   errorstate = SD_PowerON(hsd);
00332   if(errorstate != HAL_SD_ERROR_NONE)
00333   {
00334     hsd->State = HAL_SD_STATE_READY;
00335     hsd->ErrorCode |= errorstate;
00336     return HAL_ERROR;
00337   }
00338
00339   /* Card initialization */
00340   errorstate = SD_InitCard(hsd);
00341   if(errorstate != HAL_SD_ERROR_NONE)
00342   {
00343     hsd->State = HAL_SD_STATE_READY;
00344     hsd->ErrorCode |= errorstate;
00345     return HAL_ERROR;
00346   }
00347
00348   return HAL_OK;
00349 }
00350
00351 /**
00352   * @brief  De-Initializes the SD card.
00353   * @param  hsd: Pointer to SD handle
00354   * @retval HAL status
00355   */
00356 HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
00357 {
00358   /* Check the SD handle allocation */
00359   if(hsd == NULL)
00360   {
00361     return HAL_ERROR;
00362   }
00363
00364   /* Check the parameters */
00365   assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));
00366
00367   hsd->State = HAL_SD_STATE_BUSY;
00368
00369 #if (USE_SD_TRANSCEIVER != 0U)
00370   /* Desactivate the 1.8V Mode */
00371   HAL_SD_DriveTransciver_1_8V_Callback(RESET);
00372 #endif /* USE_SD_TRANSCEIVER   */
00373
00374   /* Set SD power state to off */
00375   SD_PowerOFF(hsd);
00376
00377   /* De-Initialize the MSP layer */
00378   HAL_SD_MspDeInit(hsd);
00379
00380   hsd->ErrorCode = HAL_SD_ERROR_NONE;
00381   hsd->State = HAL_SD_STATE_RESET;
00382
00383   return HAL_OK;
00384 }
00385
00386
00387 /**
00388   * @brief  Initializes the SD MSP.
00389   * @param  hsd: Pointer to SD handle
00390   * @retval None
00391   */
00392 __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
00393 {
00394   /* Prevent unused argument(s) compilation warning */
00395   UNUSED(hsd);
00396
00397   /* NOTE : This function Should not be modified, when the callback is needed,
00398             the HAL_SD_MspInit could be implemented in the user file
00399    */
00400 }
00401
00402 /**
00403   * @brief  De-Initialize SD MSP.
00404   * @param  hsd: Pointer to SD handle
00405   * @retval None
00406   */
00407 __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
00408 {
00409   /* Prevent unused argument(s) compilation warning */
00410   UNUSED(hsd);
00411
00412   /* NOTE : This function Should not be modified, when the callback is needed,
00413             the HAL_SD_MspDeInit could be implemented in the user file
00414    */
00415 }
00416
00417 /**
00418   * @}
00419   */
00420
00421 /** @addtogroup SD_Exported_Functions_Group2
00422  *  @brief   Data transfer functions
00423  *
00424 @verbatim
00425   ==============================================================================
00426                         ##### IO operation functions #####
00427   ==============================================================================
00428   [..]
00429     This subsection provides a set of functions allowing to manage the data
00430     transfer from/to SD card.
00431
00432 @endverbatim
00433   * @{
00434   */
00435
00436 /**
00437   * @brief  Reads block(s) from a specified address in a card. The Data transfer
00438   *         is managed by polling mode.
00439   * @note   This API should be followed by a check on the card state through
00440   *         HAL_SD_GetCardState().
00441   * @param  hsd: Pointer to SD handle
00442   * @param  pData: pointer to the buffer that will contain the received data
00443   * @param  BlockAdd: Block Address from where data is to be read
00444   * @param  NumberOfBlocks: Number of SD blocks to read
00445   * @param  Timeout
00446   * @retval HAL status
00447   */
00448 HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
00449 {
00450   SDMMC_DataInitTypeDef config;
00451   uint32_t errorstate = HAL_SD_ERROR_NONE;
00452   uint32_t tickstart = HAL_GetTick();
00453   uint32_t count = 0, *tempbuff = (uint32_t *)pData;
00454
00455   if(NULL == pData)
00456   {
00457     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
00458     return HAL_ERROR;
00459   }
00460
00461   if(hsd->State == HAL_SD_STATE_READY)
00462   {
00463     hsd->ErrorCode = HAL_DMA_ERROR_NONE;
00464
00465     if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
00466     {
00467       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
00468       return HAL_ERROR;
00469     }
00470
00471     hsd->State = HAL_SD_STATE_BUSY;
00472
00473     /* Initialize data control register */
00474     hsd->Instance->DCTRL = 0;
00475
00476     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
00477     {
00478       BlockAdd *= 512;
00479     }
00480
00481     /* Set Block Size for Card */
00482     errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
00483     if(errorstate != HAL_SD_ERROR_NONE)
00484     {
00485       /* Clear all the static flags */
00486       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00487       hsd->ErrorCode |= errorstate;
00488       hsd->State = HAL_SD_STATE_READY;
00489       return HAL_ERROR;
00490     }
00491
00492     /* Configure the SD DPSM (Data Path State Machine) */
00493     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00494     config.DataLength    = NumberOfBlocks * BLOCKSIZE;
00495     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00496     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
00497     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00498     config.DPSM          = SDMMC_DPSM_ENABLE;
00499     SDMMC_ConfigData(hsd->Instance, &config);
00500
00501     /* Read block(s) in polling mode */
00502     if(NumberOfBlocks > 1)
00503     {
00504       hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
00505
00506       /* Read Multi Block command */
00507       errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
00508     }
00509     else
00510     {
00511       hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
00512
00513       /* Read Single Block command */
00514       errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
00515     }
00516     if(errorstate != HAL_SD_ERROR_NONE)
00517     {
00518       /* Clear all the static flags */
00519       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00520       hsd->ErrorCode |= errorstate;
00521       hsd->State = HAL_SD_STATE_READY;
00522       return HAL_ERROR;
00523     }
00524
00525     /* Poll on SDMMC flags */
00526     while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
00527     {
00528       if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
00529       {
00530         /* Read data from SDMMC Rx FIFO */
00531         for(count = 0U; count < 8U; count++)
00532         {
00533           *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);
00534         }
00535         tempbuff += 8U;
00536       }
00537
00538       if((Timeout == 0U)||((HAL_GetTick()-tickstart) >=  Timeout))
00539       {
00540         /* Clear all the static flags */
00541         __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00542         hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
00543         hsd->State= HAL_SD_STATE_READY;
00544         return HAL_TIMEOUT;
00545       }
00546     }
00547
00548     /* Send stop transmission command in case of multiblock read */
00549     if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
00550     {
00551       if(hsd->SdCard.CardType != CARD_SECURED)
00552       {
00553       /* Send stop transmission command */
00554       errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
00555       if(errorstate != HAL_SD_ERROR_NONE)
00556       {
00557           /* Clear all the static flags */
00558           __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00559         hsd->ErrorCode |= errorstate;
00560           hsd->State = HAL_SD_STATE_READY;
00561         return HAL_ERROR;
00562       }
00563     }
00564     }
00565
00566     /* Get error state */
00567     if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
00568     {
00569       /* Clear all the static flags */
00570       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00571       hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
00572       hsd->State = HAL_SD_STATE_READY;
00573       return HAL_ERROR;
00574     }
00575     else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
00576     {
00577       /* Clear all the static flags */
00578       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00579       hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
00580       hsd->State = HAL_SD_STATE_READY;
00581       return HAL_ERROR;
00582     }
00583     else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
00584     {
00585       /* Clear all the static flags */
00586       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00587       hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
00588       hsd->State = HAL_SD_STATE_READY;
00589       return HAL_ERROR;
00590     }
00591
00592     /* Clear all the static flags */
00593     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00594
00595     hsd->State = HAL_SD_STATE_READY;
00596
00597     return HAL_OK;
00598   }
00599   else
00600   {
00601     hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
00602     return HAL_ERROR;
00603   }
00604 }
00605
00606 /**
00607   * @brief  Allows to write block(s) to a specified address in a card. The Data
00608   *         transfer is managed by polling mode.
00609   * @note   This API should be followed by a check on the card state through
00610   *         HAL_SD_GetCardState().
00611   * @param  hsd: Pointer to SD handle
00612   * @param  pData: pointer to the buffer that will contain the data to transmit
00613   * @param  BlockAdd: Block Address where data will be written
00614   * @param  NumberOfBlocks: Number of SD blocks to write
00615   * @param  Timeout
00616   * @retval HAL status
00617   */
00618 HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
00619 {
00620   SDMMC_DataInitTypeDef config;
00621   uint32_t errorstate = HAL_SD_ERROR_NONE;
00622   uint32_t count = 0;
00623   uint32_t tickstart = HAL_GetTick();
00624   uint32_t *tempbuff = (uint32_t *)pData;
00625
00626   if(NULL == pData)
00627   {
00628     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
00629     return HAL_ERROR;
00630   }
00631
00632   if(hsd->State == HAL_SD_STATE_READY)
00633   {
00634     hsd->ErrorCode = HAL_DMA_ERROR_NONE;
00635
00636     if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
00637     {
00638       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
00639       return HAL_ERROR;
00640     }
00641
00642     hsd->State = HAL_SD_STATE_BUSY;
00643
00644     /* Initialize data control register */
00645     hsd->Instance->DCTRL = 0;
00646
00647     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
00648     {
00649       BlockAdd *= 512;
00650     }
00651
00652     /* Set Block Size for Card */
00653     errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
00654     if(errorstate != HAL_SD_ERROR_NONE)
00655     {
00656       /* Clear all the static flags */
00657       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00658       hsd->ErrorCode |= errorstate;
00659       hsd->State = HAL_SD_STATE_READY;
00660       return HAL_ERROR;
00661     }
00662
00663     /* Write Blocks in Polling mode */
00664     if(NumberOfBlocks > 1U)
00665     {
00666       hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
00667
00668       /* Write Multi Block command */
00669       errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
00670     }
00671     else
00672     {
00673       hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
00674
00675       /* Write Single Block command */
00676       errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
00677     }
00678       if(errorstate != HAL_SD_ERROR_NONE)
00679       {
00680       /* Clear all the static flags */
00681       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00682         hsd->ErrorCode |= errorstate;
00683       hsd->State = HAL_SD_STATE_READY;
00684         return HAL_ERROR;
00685       }
00686
00687     /* Configure the SD DPSM (Data Path State Machine) */
00688     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00689     config.DataLength    = NumberOfBlocks * BLOCKSIZE;
00690     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00691     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
00692     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00693     config.DPSM          = SDMMC_DPSM_ENABLE;
00694     SDMMC_ConfigData(hsd->Instance, &config);
00695
00696     /* Write block(s) in polling mode */
00697     while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
00698     {
00699       if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE))
00700       {
00701           /* Write data to SDMMC Tx FIFO */
00702         for(count = 0U; count < 8U; count++)
00703           {
00704             SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count));
00705           }
00706         tempbuff += 8U;
00707       }
00708
00709       if((Timeout == 0U)||((HAL_GetTick()-tickstart) >=  Timeout))
00710       {
00711         /* Clear all the static flags */
00712         __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00713         hsd->ErrorCode |= errorstate;
00714         hsd->State= HAL_SD_STATE_READY;
00715         return HAL_TIMEOUT;
00716       }
00717     }
00718
00719     /* Send stop transmission command in case of multiblock write */
00720     if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
00721     {
00722       if(hsd->SdCard.CardType != CARD_SECURED)
00723       {
00724         /* Send stop transmission command */
00725         errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
00726         if(errorstate != HAL_SD_ERROR_NONE)
00727         {
00728           /* Clear all the static flags */
00729           __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00730           hsd->ErrorCode |= errorstate;
00731           hsd->State = HAL_SD_STATE_READY;
00732           return HAL_ERROR;
00733         }
00734       }
00735     }
00736
00737     /* Get error state */
00738     if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
00739     {
00740       /* Clear all the static flags */
00741       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00742       hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
00743       hsd->State = HAL_SD_STATE_READY;
00744       return HAL_ERROR;
00745     }
00746     else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
00747     {
00748       /* Clear all the static flags */
00749       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00750       hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
00751       hsd->State = HAL_SD_STATE_READY;
00752       return HAL_ERROR;
00753     }
00754     else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))
00755     {
00756       /* Clear all the static flags */
00757       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00758       hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
00759       hsd->State = HAL_SD_STATE_READY;
00760       return HAL_ERROR;
00761     }
00762
00763     /* Clear all the static flags */
00764     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00765
00766     hsd->State = HAL_SD_STATE_READY;
00767
00768     return HAL_OK;
00769   }
00770   else
00771   {
00772     hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
00773     return HAL_ERROR;
00774   }
00775 }
00776
00777
00778 /**
00779   * @brief  Reads block(s) from a specified address in a card. The Data transfer
00780   *         is managed in interrupt mode.
00781   * @note   This API should be followed by a check on the card state through
00782   *         HAL_SD_GetCardState().
00783   * @note   You could also check the IT transfer process through the SD Rx
00784   *         interrupt event.
00785   * @param  hsd: Pointer to SD handle
00786   * @param  pData: Pointer to the buffer that will contain the received data
00787   * @param  BlockAdd: Block Address from where data is to be read
00788   * @param  NumberOfBlocks: Number of blocks to read.
00789   * @retval HAL status
00790   */
00791 HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
00792 {
00793   SDMMC_DataInitTypeDef config;
00794   uint32_t errorstate = HAL_SD_ERROR_NONE;
00795
00796   if(NULL == pData)
00797   {
00798     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
00799     return HAL_ERROR;
00800   }
00801
00802   if(hsd->State == HAL_SD_STATE_READY)
00803   {
00804     hsd->ErrorCode = HAL_DMA_ERROR_NONE;
00805
00806     if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
00807     {
00808       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
00809       return HAL_ERROR;
00810     }
00811
00812     hsd->State = HAL_SD_STATE_BUSY;
00813
00814     /* Initialize data control register */
00815     hsd->Instance->DCTRL = 0U;
00816
00817     hsd->pRxBuffPtr = (uint32_t *)pData;
00818     hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
00819
00820     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
00821     {
00822       BlockAdd *= 512U;
00823     }
00824
00825     /* Set Block Size for Card */
00826     errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
00827     if(errorstate != HAL_SD_ERROR_NONE)
00828     {
00829       /* Clear all the static flags */
00830       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00831       hsd->ErrorCode |= errorstate;
00832       hsd->State = HAL_SD_STATE_READY;
00833       return HAL_ERROR;
00834     }
00835
00836         /* Configure the SD DPSM (Data Path State Machine) */
00837     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00838     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
00839     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00840     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
00841     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00842     config.DPSM          = SDMMC_DPSM_ENABLE;
00843     SDMMC_ConfigData(hsd->Instance, &config);
00844
00845     /* Read Blocks in IT mode */
00846     if(NumberOfBlocks > 1U)
00847     {
00848       hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
00849
00850       /* Read Multi Block command */
00851       errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
00852     }
00853     else
00854     {
00855       hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);
00856
00857       /* Read Single Block command */
00858       errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
00859     }
00860
00861     if(errorstate != HAL_SD_ERROR_NONE)
00862     {
00863       /* Clear all the static flags */
00864       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00865       hsd->ErrorCode |= errorstate;
00866       hsd->State = HAL_SD_STATE_READY;
00867       return HAL_ERROR;
00868     }
00869
00870
00871     __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF));
00872
00873     return HAL_OK;
00874   }
00875   else
00876   {
00877     return HAL_BUSY;
00878   }
00879 }
00880
00881 /**
00882   * @brief  Writes block(s) to a specified address in a card. The Data transfer
00883   *         is managed in interrupt mode.
00884   * @note   This API should be followed by a check on the card state through
00885   *         HAL_SD_GetCardState().
00886   * @note   You could also check the IT transfer process through the SD Tx
00887   *         interrupt event.
00888   * @param  hsd: Pointer to SD handle
00889   * @param  pData: Pointer to the buffer that will contain the data to transmit
00890   * @param  BlockAdd: Block Address where data will be written
00891   * @param  NumberOfBlocks: Number of blocks to write
00892   * @retval HAL status
00893   */
00894 HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
00895 {
00896   SDMMC_DataInitTypeDef config;
00897   uint32_t errorstate = HAL_SD_ERROR_NONE;
00898
00899   if(NULL == pData)
00900   {
00901     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
00902     return HAL_ERROR;
00903   }
00904
00905   if(hsd->State == HAL_SD_STATE_READY)
00906   {
00907     hsd->ErrorCode = HAL_DMA_ERROR_NONE;
00908
00909     if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
00910     {
00911       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
00912       return HAL_ERROR;
00913     }
00914
00915     hsd->State = HAL_SD_STATE_BUSY;
00916
00917     /* Initialize data control register */
00918     hsd->Instance->DCTRL = 0U;
00919
00920     hsd->pTxBuffPtr = (uint32_t *)pData;
00921     hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
00922
00923     /* Enable transfer interrupts */
00924     __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE));
00925
00926     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
00927     {
00928       BlockAdd *= 512U;
00929     }
00930
00931     /* Set Block Size for Card */
00932     errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
00933     if(errorstate != HAL_SD_ERROR_NONE)
00934     {
00935       /* Clear all the static flags */
00936       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00937       hsd->ErrorCode |= errorstate;
00938       hsd->State = HAL_SD_STATE_READY;
00939       return HAL_ERROR;
00940     }
00941
00942     /* Write Blocks in Polling mode */
00943     if(NumberOfBlocks > 1U)
00944     {
00945       hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT);
00946
00947       /* Write Multi Block command */
00948       errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
00949     }
00950     else
00951     {
00952       hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);
00953
00954       /* Write Single Block command */
00955       errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
00956     }
00957     if(errorstate != HAL_SD_ERROR_NONE)
00958     {
00959       /* Clear all the static flags */
00960       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00961       hsd->ErrorCode |= errorstate;
00962       hsd->State = HAL_SD_STATE_READY;
00963       return HAL_ERROR;
00964     }
00965
00966     /* Configure the SD DPSM (Data Path State Machine) */
00967     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00968     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
00969     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00970     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
00971     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00972     config.DPSM          = SDMMC_DPSM_ENABLE;
00973     SDMMC_ConfigData(hsd->Instance, &config);
00974
00975     return HAL_OK;
00976   }
00977   else
00978   {
00979     return HAL_BUSY;
00980   }
00981 }
00982
00983 /**
00984   * @brief  Reads block(s) from a specified address in a card. The Data transfer
00985   *         is managed by DMA mode.
00986   * @note   This API should be followed by a check on the card state through
00987   *         HAL_SD_GetCardState().
00988   * @note   You could also check the DMA transfer process through the SD Rx
00989   *         interrupt event.
00990   * @param  hsd: Pointer SD handle
00991   * @param  pData: Pointer to the buffer that will contain the received data
00992   * @param  BlockAdd: Block Address from where data is to be read
00993   * @param  NumberOfBlocks: Number of blocks to read.
00994   * @retval HAL status
00995   */
00996 HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
00997 {
00998   SDMMC_DataInitTypeDef config;
00999   uint32_t errorstate = HAL_SD_ERROR_NONE;
01000
01001   if(NULL == pData)
01002   {
01003     hsd->ErrorCode = HAL_SD_ERROR_PARAM;
01004     return HAL_ERROR;
01005   }
01006
01007   if(hsd->State == HAL_SD_STATE_READY)
01008   {
01009     hsd->ErrorCode = HAL_DMA_ERROR_NONE;
01010
01011     if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
01012     {
01013       hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
01014       return HAL_ERROR;
01015     }
01016
01017     hsd->State = HAL_SD_STATE_BUSY;
01018
01019     /* Initialize data control register */
01020     hsd->Instance->DCTRL = 0U;
01021
01022     hsd->pRxBuffPtr = (uint32_t*)pData;
01023     hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
01024
01025     hsd->State = HAL_SD_STATE_BUSY;
01026
01027     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
01028     {
01029       BlockAdd *= 512U;
01030     }
01031
01032     /* Configure the SD DPSM (Data Path State Machine) */
01033     config.DataTimeOut   = SDMMC_DATATIMEOUT;
01034     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
01035     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
01036     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
01037     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
01038     config.DPSM          = SDMMC_DPSM_DISABLE;
01039     SDMMC_ConfigData(hsd->Instance, &config);
01040
01041     /* Set Block Size for Card */
01042     errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
01043     if(errorstate != HAL_SD_ERROR_NONE)
01044     {
01045       /* Clear all the static flags */
01046       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01047       hsd->ErrorCode = errorstate;
01048       hsd->State = HAL_SD_STATE_READY;
01049       return HAL_ERROR;
01050     }
01051
01052     /* Enable transfer interrupts */
01053     __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
01054
01055     __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
01056     hsd->Instance->IDMACTRL  = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
01057     hsd->Instance->IDMABASE0 = (uint32_t) pData ;
01058
01059     /* Read Blocks in DMA mode */
01060     if(NumberOfBlocks > 1U)
01061     {
01062       hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
01063
01064       /* Read Multi Block command */
01065       errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
01066     }
01067     else
01068     {
01069       hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
01070
01071       /* Read Single Block command */
01072       errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
01073     }
01074     if(errorstate != HAL_SD_ERROR_NONE)
01075     {
01076       /* Clear all the static flags */
01077       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01078       __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
01079       hsd->ErrorCode = errorstate;
01080       hsd->State = HAL_SD_STATE_READY;
01081       return HAL_ERROR;
01082     }
01083
01084     return HAL_OK;
01085   }
01086   else
01087   {
01088     return HAL_BUSY;
01089   }
01090 }
01091
01092 /**
01093   * @brief  Writes block(s) to a specified address in a card. The Data transfer
01094   *         is managed by DMA mode.
01095   * @note   This API should be followed by a check on the card state through
01096   *         HAL_SD_GetCardState().
01097   * @note   You could also check the DMA transfer process through the SD Tx
01098   *         interrupt event.
01099   * @param  hsd: Pointer to SD handle
01100   * @param  pData: pointer to the buffer that will contain the data to transmit
01101   * @param  BlockAdd: Block Address where data will be written
01102   * @param  NumberOfBlocks: Number of blocks to write
01103   * @retval HAL status
01104   */
01105 HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
01106 {
01107   SDMMC_DataInitTypeDef config;
01108   uint32_t errorstate = HAL_SD_ERROR_NONE;
01109
01110   if(NULL == pData)
01111   {
01112     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
01113     return HAL_ERROR;
01114   }
01115
01116   if(hsd->State == HAL_SD_STATE_READY)
01117   {
01118     hsd->ErrorCode = HAL_DMA_ERROR_NONE;
01119
01120     if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
01121     {
01122       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
01123       return HAL_ERROR;
01124     }
01125
01126     hsd->State = HAL_SD_STATE_BUSY;
01127
01128     /* Initialize data control register */
01129     hsd->Instance->DCTRL = 0U;
01130
01131     hsd->pTxBuffPtr = (uint32_t*)pData;
01132     hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
01133
01134     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
01135     {
01136       BlockAdd *= 512U;
01137     }
01138
01139     /* Set Block Size for Card */
01140     errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
01141     if(errorstate != HAL_SD_ERROR_NONE)
01142     {
01143       /* Clear all the static flags */
01144       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01145       hsd->ErrorCode |= errorstate;
01146       hsd->State = HAL_SD_STATE_READY;
01147       return HAL_ERROR;
01148     }
01149     /* Configure the SD DPSM (Data Path State Machine) */
01150     config.DataTimeOut   = SDMMC_DATATIMEOUT;
01151     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
01152     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
01153     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
01154     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
01155     config.DPSM          = SDMMC_DPSM_DISABLE;
01156     SDMMC_ConfigData(hsd->Instance, &config);
01157
01158     /* Enable transfer interrupts */
01159     __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
01160
01161     __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
01162
01163     hsd->Instance->IDMACTRL  = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
01164     hsd->Instance->IDMABASE0 = (uint32_t) pData ;
01165
01166     /* Write Blocks in Polling mode */
01167     if(NumberOfBlocks > 1U)
01168     {
01169       hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
01170
01171       /* Write Multi Block command */
01172       errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
01173     }
01174     else
01175     {
01176       hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
01177
01178       /* Write Single Block command */
01179       errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
01180     }
01181     if(errorstate != HAL_SD_ERROR_NONE)
01182     {
01183       /* Clear all the static flags */
01184       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01185       __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
01186       hsd->ErrorCode |= errorstate;
01187       hsd->State = HAL_SD_STATE_READY;
01188       return HAL_ERROR;
01189     }
01190
01191     return (HAL_StatusTypeDef)errorstate;
01192   }
01193   else
01194   {
01195     return HAL_BUSY;
01196   }
01197
01198 }
01199
01200 /**
01201   * @brief  Erases the specified memory area of the given SD card.
01202   * @note   This API should be followed by a check on the card state through
01203   *         HAL_SD_GetCardState().
01204   * @param  hsd: Pointer to SD handle
01205   * @param  BlockStartAdd: Start Block address
01206   * @param  BlockEndAdd: End Block address
01207   * @retval HAL status
01208   */
01209 HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
01210 {
01211   uint32_t errorstate = HAL_SD_ERROR_NONE;
01212
01213   if(hsd->State == HAL_SD_STATE_READY)
01214   {
01215     hsd->ErrorCode = HAL_DMA_ERROR_NONE;
01216
01217     if(BlockEndAdd < BlockStartAdd)
01218     {
01219       hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
01220       return HAL_ERROR;
01221     }
01222
01223     if(BlockEndAdd > (hsd->SdCard.LogBlockNbr))
01224     {
01225       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
01226       return HAL_ERROR;
01227     }
01228
01229     hsd->State = HAL_SD_STATE_BUSY;
01230
01231     /* Check if the card command class supports erase command */
01232     if(((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U)
01233     {
01234       /* Clear all the static flags */
01235       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01236       hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
01237       hsd->State = HAL_SD_STATE_READY;
01238       return HAL_ERROR;
01239     }
01240
01241     if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
01242     {
01243       /* Clear all the static flags */
01244       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01245       hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
01246       hsd->State = HAL_SD_STATE_READY;
01247       return HAL_ERROR;
01248     }
01249
01250     /* Get start and end block for high capacity cards */
01251     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
01252     {
01253       BlockStartAdd *= 512U;
01254       BlockEndAdd   *= 512U;
01255     }
01256
01257     /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
01258     if(hsd->SdCard.CardType != CARD_SECURED)
01259     {
01260     /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */
01261       errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, BlockStartAdd);
01262     if(errorstate != HAL_SD_ERROR_NONE)
01263     {
01264         /* Clear all the static flags */
01265         __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01266         hsd->ErrorCode |= errorstate;
01267       hsd->State = HAL_SD_STATE_READY;
01268       return HAL_ERROR;
01269     }
01270
01271     /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */
01272       errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, BlockEndAdd);
01273     if(errorstate != HAL_SD_ERROR_NONE)
01274     {
01275         /* Clear all the static flags */
01276         __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01277         hsd->ErrorCode |= errorstate;
01278       hsd->State = HAL_SD_STATE_READY;
01279       return HAL_ERROR;
01280     }
01281     }
01282
01283     /* Send CMD38 ERASE */
01284     errorstate = SDMMC_CmdErase(hsd->Instance);
01285     if(errorstate != HAL_SD_ERROR_NONE)
01286     {
01287       /* Clear all the static flags */
01288       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01289       hsd->ErrorCode |= errorstate;
01290       hsd->State = HAL_SD_STATE_READY;
01291       return HAL_ERROR;
01292     }
01293
01294     hsd->State = HAL_SD_STATE_READY;
01295
01296     return HAL_OK;
01297   }
01298   else
01299   {
01300     return HAL_BUSY;
01301   }
01302 }
01303
01304 /**
01305   * @brief  This function handles SD card interrupt request.
01306   * @param  hsd: Pointer to SD handle
01307   * @retval None
01308   */
01309 void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
01310 {
01311   uint32_t errorstate = HAL_SD_ERROR_NONE;
01312   uint32_t tickstart = HAL_GetTick();
01313
01314   /* Check for SDMMC interrupt flags */
01315   if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DATAEND) != RESET)
01316   {
01317     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND);
01318
01319     __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR\
01320                            | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE\
01321                            | SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_RXFIFOHF);
01322
01323     if((hsd->Context & SD_CONTEXT_DMA) != RESET)
01324     {
01325
01326       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01327       __SDMMC_CMDTRANS_DISABLE( hsd->Instance);
01328
01329       hsd->Instance->DLEN = 0;
01330       hsd->Instance->DCTRL = 0;
01331       hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA ;
01332
01333       /* Stop Transfer for Write Multi blocks or Read Multi blocks */
01334       if(((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET))
01335       {
01336         errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
01337         if(errorstate != HAL_SD_ERROR_NONE)
01338         {
01339           hsd->ErrorCode = errorstate;
01340           HAL_SD_ErrorCallback(hsd);
01341         }
01342       }
01343
01344       if(((hsd->Context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET))
01345       {
01346         while((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER) && ((HAL_GetTick() - tickstart) <=  SDMMC_MAX_TRIAL))
01347         {
01348           /* Wait until SD CARD Status goes to TRANSFER STATE or Timeout */
01349         }
01350
01351         HAL_SD_TxCpltCallback(hsd);
01352       }
01353       if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET))
01354       {
01355         HAL_SD_RxCpltCallback(hsd);
01356       }
01357
01358
01359       hsd->State = HAL_SD_STATE_READY;
01360
01361     }
01362
01363     if ((hsd->Context & SD_CONTEXT_IT) != RESET)
01364     {
01365       if ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET)
01366       {
01367         errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
01368         if(errorstate != HAL_SD_ERROR_NONE)
01369         {
01370           hsd->ErrorCode = errorstate;
01371           HAL_SD_ErrorCallback(hsd);
01372         }
01373
01374         hsd->State = HAL_SD_STATE_READY;
01375
01376         HAL_SD_RxCpltCallback(hsd);
01377       }
01378       else if (((hsd->Context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET))
01379       {
01380         if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)
01381         {
01382           errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
01383           if(errorstate != HAL_SD_ERROR_NONE)
01384           {
01385             hsd->ErrorCode = errorstate;
01386             HAL_SD_ErrorCallback(hsd);
01387           }
01388         }
01389
01390
01391         /* Clear all the static flags */
01392         __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01393
01394         hsd->State = HAL_SD_STATE_READY;
01395
01396         HAL_SD_TxCpltCallback(hsd);
01397       }
01398     }
01399   }
01400
01401   else if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXFIFOHE) != RESET)
01402   {
01403     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_TXFIFOHE);
01404
01405     SD_Write_IT(hsd);
01406   }
01407
01408   else if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXFIFOHF) != RESET)
01409   {
01410     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXFIFOHF);
01411
01412     SD_Read_IT(hsd);
01413   }
01414
01415   else if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET)
01416   {
01417     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
01418
01419     __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DCRCFAIL);
01420
01421     HAL_SD_ErrorCallback(hsd);
01422   }
01423
01424   else if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET)
01425   {
01426     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
01427
01428     __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DTIMEOUT);
01429
01430     HAL_SD_ErrorCallback(hsd);
01431   }
01432
01433   else if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET)
01434   {
01435     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
01436
01437     __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_RXOVERR);
01438
01439     HAL_SD_ErrorCallback(hsd);
01440   }
01441
01442   else if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET)
01443   {
01444     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_TXUNDERR);
01445
01446     __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_TXUNDERR);
01447
01448     HAL_SD_ErrorCallback(hsd);
01449   }
01450
01451   else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_IDMATE) != RESET)
01452   {
01453     __SDMMC_CMDTRANS_DISABLE( hsd->Instance);
01454     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMATE);
01455
01456     __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMATE);
01457
01458     HAL_SD_ErrorCallback(hsd);
01459   }
01460   else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_IDMABTC) != RESET)
01461   {
01462     if(READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == SD_DMA_BUFFER0)
01463     {
01464       /* Current buffer is buffer0, Transfer complete for buffer1 */
01465       if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)
01466       {
01467         HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(hsd);
01468       }
01469       else /* SD_CONTEXT_READ_MULTIPLE_BLOCK */
01470       {
01471         HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(hsd);
01472       }
01473     }
01474     else /* SD_DMA_BUFFER1 */
01475     {
01476       /* Current buffer is buffer1, Transfer complete for buffer0 */
01477       if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)
01478       {
01479         HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(hsd);
01480       }
01481       else /* SD_CONTEXT_READ_MULTIPLE_BLOCK */
01482       {
01483         HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(hsd);
01484       }
01485     }
01486     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_IT_IDMABTC);
01487   }
01488
01489 }
01490
01491 /**
01492   * @brief return the SD state
01493   * @param hsd: Pointer to sd handle
01494   * @retval HAL state
01495   */
01496 HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
01497 {
01498   return hsd->State;
01499 }
01500
01501 /**
01502 * @brief  Return the SD error code
01503 * @param  hsd : pointer to a SD_HandleTypeDef structure that contains
01504   *              the configuration information.
01505 * @retval SD Error Code
01506 */
01507 uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd)
01508 {
01509   return hsd->ErrorCode;
01510 }
01511
01512 /**
01513   * @brief Tx Transfer completed callbacks
01514   * @param hsd: Pointer to SD handle
01515   * @retval None
01516   */
01517  __weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
01518 {
01519   /* Prevent unused argument(s) compilation warning */
01520   UNUSED(hsd);
01521
01522   /* NOTE : This function should not be modified, when the callback is needed,
01523             the HAL_SD_TxCpltCallback can be implemented in the user file
01524    */
01525 }
01526
01527 /**
01528   * @brief Rx Transfer completed callbacks
01529   * @param hsd: Pointer SD handle
01530   * @retval None
01531   */
01532 __weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
01533 {
01534   /* Prevent unused argument(s) compilation warning */
01535   UNUSED(hsd);
01536
01537   /* NOTE : This function should not be modified, when the callback is needed,
01538             the HAL_SD_RxCpltCallback can be implemented in the user file
01539    */
01540 }
01541
01542 /**
01543   * @brief SD error callbacks
01544   * @param hsd: Pointer SD handle
01545   * @retval None
01546   */
01547 __weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
01548 {
01549   /* Prevent unused argument(s) compilation warning */
01550   UNUSED(hsd);
01551
01552   /* NOTE : This function should not be modified, when the callback is needed,
01553             the HAL_SD_ErrorCallback can be implemented in the user file
01554    */
01555 }
01556
01557 /**
01558   * @brief SD Abort callbacks
01559   * @param hsd: Pointer SD handle
01560   * @retval None
01561   */
01562 __weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
01563 {
01564   /* Prevent unused argument(s) compilation warning */
01565   UNUSED(hsd);
01566
01567   /* NOTE : This function should not be modified, when the callback is needed,
01568             the HAL_SD_ErrorCallback can be implemented in the user file
01569    */
01570 }
01571
01572 #if (USE_SD_TRANSCEIVER != 0U)
01573 /**
01574   * @brief  Enable/Disable the SD Transciver 1.8V Mode Callback.
01575   * @param  status: Voltage Switch State
01576   * @retval None
01577   */
01578 __weak  void HAL_SD_DriveTransciver_1_8V_Callback(FlagStatus status)
01579 {
01580
01581   /* NOTE : This function Should not be modified, when the callback is needed,
01582             the HAL_SD_EnableTransciver could be implemented in the user file
01583    */
01584 }
01585 #endif /* USE_SD_TRANSCEIVER  */
01586
01587 /** @addtogroup SD_Exported_Functions_Group3
01588  *  @brief   management functions
01589  *
01590 @verbatim
01591   ==============================================================================
01592                       ##### Peripheral Control functions #####
01593   ==============================================================================
01594   [..]
01595     This subsection provides a set of functions allowing to control the SD card
01596     operations and get the related information
01597
01598 @endverbatim
01599   * @{
01600   */
01601
01602 /**
01603   * @brief  Returns information the information of the card which are stored on
01604   *         the CID register.
01605   * @param  hsd: Pointer to SD handle
01606   * @param  pCID: Pointer to a HAL_SD_CIDTypedef structure that
01607   *         contains all CID register parameters
01608   * @retval HAL status
01609   */
01610 HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef *pCID)
01611 {
01612   uint32_t tmp = 0;
01613
01614   /* Byte 0 */
01615   tmp = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24);
01616   pCID->ManufacturerID = tmp;
01617
01618   /* Byte 1 */
01619   tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16);
01620   pCID->OEM_AppliID = tmp << 8;
01621
01622   /* Byte 2 */
01623   tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8);
01624   pCID->OEM_AppliID |= tmp;
01625
01626   /* Byte 3 */
01627   tmp = (uint8_t)(hsd->CID[0] & 0x000000FF);
01628   pCID->ProdName1 = tmp << 24;
01629
01630   /* Byte 4 */
01631   tmp = (uint8_t)((hsd->CID[1] & 0xFF000000U) >> 24);
01632   pCID->ProdName1 |= tmp << 16;
01633
01634   /* Byte 5 */
01635   tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16);
01636   pCID->ProdName1 |= tmp << 8;
01637
01638   /* Byte 6 */
01639   tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8);
01640   pCID->ProdName1 |= tmp;
01641
01642   /* Byte 7 */
01643   tmp = (uint8_t)(hsd->CID[1] & 0x000000FF);
01644   pCID->ProdName2 = tmp;
01645
01646   /* Byte 8 */
01647   tmp = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24);
01648   pCID->ProdRev = tmp;
01649
01650   /* Byte 9 */
01651   tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16);
01652   pCID->ProdSN = tmp << 24;
01653
01654   /* Byte 10 */
01655   tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8);
01656   pCID->ProdSN |= tmp << 16;
01657
01658   /* Byte 11 */
01659   tmp = (uint8_t)(hsd->CID[2] & 0x000000FF);
01660   pCID->ProdSN |= tmp << 8;
01661
01662   /* Byte 12 */
01663   tmp = (uint8_t)((hsd->CID[3] & 0xFF000000U) >> 24);
01664   pCID->ProdSN |= tmp;
01665
01666   /* Byte 13 */
01667   tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16);
01668   pCID->Reserved1   |= (tmp & 0xF0) >> 4;
01669   pCID->ManufactDate = (tmp & 0x0F) << 8;
01670
01671   /* Byte 14 */
01672   tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8);
01673   pCID->ManufactDate |= tmp;
01674
01675   /* Byte 15 */
01676   tmp = (uint8_t)(hsd->CID[3] & 0x000000FF);
01677   pCID->CID_CRC   = (tmp & 0xFE) >> 1;
01678   pCID->Reserved2 = 1;
01679
01680   return HAL_OK;
01681 }
01682
01683 /**
01684   * @brief  Returns information the information of the card which are stored on
01685   *         the CSD register.
01686   * @param  hsd: Pointer to SD handle
01687   * @param  pCSD: Pointer to a HAL_SD_CardInfoTypedef structure that
01688   *         contains all CSD register parameters
01689   * @retval HAL status
01690   */
01691 HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef *pCSD)
01692 {
01693   uint32_t tmp = 0;
01694
01695   /* Byte 0 */
01696   tmp = (hsd->CSD[0] & 0xFF000000U) >> 24;
01697   pCSD->CSDStruct      = (uint8_t)((tmp & 0xC0) >> 6);
01698   pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2);
01699   pCSD->Reserved1      = tmp & 0x03;
01700
01701   /* Byte 1 */
01702   tmp = (hsd->CSD[0] & 0x00FF0000) >> 16;
01703   pCSD->TAAC = (uint8_t)tmp;
01704
01705   /* Byte 2 */
01706   tmp = (hsd->CSD[0] & 0x0000FF00) >> 8;
01707   pCSD->NSAC = (uint8_t)tmp;
01708
01709   /* Byte 3 */
01710   tmp = hsd->CSD[0] & 0x000000FF;
01711   pCSD->MaxBusClkFrec = (uint8_t)tmp;
01712
01713   /* Byte 4 */
01714   tmp = (hsd->CSD[1] & 0xFF000000U) >> 24;
01715   pCSD->CardComdClasses = (uint16_t)(tmp << 4);
01716
01717   /* Byte 5 */
01718   tmp = (hsd->CSD[1] & 0x00FF0000U) >> 16;
01719   pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4);
01720   pCSD->RdBlockLen       = (uint8_t)(tmp & 0x0F);
01721
01722   /* Byte 6 */
01723   tmp = (hsd->CSD[1] & 0x0000FF00U) >> 8;
01724   pCSD->PartBlockRead   = (uint8_t)((tmp & 0x80) >> 7);
01725   pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6);
01726   pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5);
01727   pCSD->DSRImpl         = (uint8_t)((tmp & 0x10) >> 4);
01728   pCSD->Reserved2       = 0; /*!< Reserved */
01729
01730   if(hsd->SdCard.CardType == CARD_SDSC)
01731   {
01732     pCSD->DeviceSize = (tmp & 0x03) << 10;
01733
01734     /* Byte 7 */
01735     tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU);
01736     pCSD->DeviceSize |= (tmp) << 2;
01737
01738     /* Byte 8 */
01739     tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24);
01740     pCSD->DeviceSize |= (tmp & 0xC0) >> 6;
01741
01742     pCSD->MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;
01743     pCSD->MaxRdCurrentVDDMax = (tmp & 0x07);
01744
01745     /* Byte 9 */
01746     tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16);
01747     pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;
01748     pCSD->MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;
01749     pCSD->DeviceSizeMul      = (tmp & 0x03) << 1;
01750     /* Byte 10 */
01751     tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8);
01752     pCSD->DeviceSizeMul |= (tmp & 0x80) >> 7;
01753
01754     hsd->SdCard.BlockNbr  = (pCSD->DeviceSize + 1) ;
01755     hsd->SdCard.BlockNbr *= (1 << (pCSD->DeviceSizeMul + 2));
01756     hsd->SdCard.BlockSize = 1 << (pCSD->RdBlockLen);
01757
01758     hsd->SdCard.LogBlockNbr =  (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512);
01759     hsd->SdCard.LogBlockSize = 512;
01760   }
01761   else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)
01762   {
01763     /* Byte 7 */
01764     tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU);
01765     pCSD->DeviceSize = (tmp & 0x3F) << 16;
01766
01767     /* Byte 8 */
01768     tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24);
01769
01770     pCSD->DeviceSize |= (tmp << 8);
01771
01772     /* Byte 9 */
01773     tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16);
01774
01775     pCSD->DeviceSize |= (tmp);
01776
01777     /* Byte 10 */
01778     tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8);
01779
01780     hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr = (((uint64_t)pCSD->DeviceSize + 1) * 1024);
01781     hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize = 512;
01782   }
01783   else
01784   {
01785     /* Clear all the static flags */
01786     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01787     hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
01788     hsd->State = HAL_SD_STATE_READY;
01789     return HAL_ERROR;
01790   }
01791
01792   pCSD->EraseGrSize = (tmp & 0x40) >> 6;
01793   pCSD->EraseGrMul  = (tmp & 0x3F) << 1;
01794
01795   /* Byte 11 */
01796   tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF);
01797   pCSD->EraseGrMul     |= (tmp & 0x80) >> 7;
01798   pCSD->WrProtectGrSize = (tmp & 0x7F);
01799
01800   /* Byte 12 */
01801   tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000U) >> 24);
01802   pCSD->WrProtectGrEnable = (tmp & 0x80) >> 7;
01803   pCSD->ManDeflECC        = (tmp & 0x60) >> 5;
01804   pCSD->WrSpeedFact       = (tmp & 0x1C) >> 2;
01805   pCSD->MaxWrBlockLen     = (tmp & 0x03) << 2;
01806
01807   /* Byte 13 */
01808   tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16);
01809   pCSD->MaxWrBlockLen      |= (tmp & 0xC0) >> 6;
01810   pCSD->WriteBlockPaPartial = (tmp & 0x20) >> 5;
01811   pCSD->Reserved3           = 0;
01812   pCSD->ContentProtectAppli = (tmp & 0x01);
01813
01814   /* Byte 14 */
01815   tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8);
01816   pCSD->FileFormatGrouop = (tmp & 0x80) >> 7;
01817   pCSD->CopyFlag         = (tmp & 0x40) >> 6;
01818   pCSD->PermWrProtect    = (tmp & 0x20) >> 5;
01819   pCSD->TempWrProtect    = (tmp & 0x10) >> 4;
01820   pCSD->FileFormat       = (tmp & 0x0C) >> 2;
01821   pCSD->ECC              = (tmp & 0x03);
01822
01823   /* Byte 15 */
01824   tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF);
01825   pCSD->CSD_CRC   = (tmp & 0xFE) >> 1;
01826   pCSD->Reserved4 = 1;
01827
01828   return HAL_OK;
01829 }
01830
01831
01832 /**
01833   * @brief  Gets the SD status info.
01834   * @param  hsd: Pointer to SD handle
01835   * @param  pStatus: Pointer to the HAL_SD_CardStatusTypedef structure that
01836   *         will contain the SD card status information
01837   * @retval HAL status
01838   */
01839 HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pStatus)
01840 {
01841   uint32_t tmp = 0;
01842   uint32_t sd_status[16];
01843   uint32_t errorstate = HAL_SD_ERROR_NONE;
01844
01845   errorstate = SD_SendSDStatus(hsd, sd_status);
01846   if(errorstate != HAL_OK)
01847   {
01848     /* Clear all the static flags */
01849     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01850     hsd->ErrorCode |= errorstate;
01851     hsd->State = HAL_SD_STATE_READY;
01852     return HAL_ERROR;
01853   }
01854   else
01855   {
01856     /* Byte 0 */
01857     tmp = (sd_status[0] & 0xC0) >> 6;
01858     pStatus->DataBusWidth = (uint8_t)tmp;
01859
01860     /* Byte 0 */
01861     tmp = (sd_status[0] & 0x20) >> 5;
01862     pStatus->SecuredMode = (uint8_t)tmp;
01863
01864     /* Byte 2 */
01865     tmp = (sd_status[0] & 0x00FF0000U) >> 16;
01866     pStatus->CardType = (uint16_t)(tmp << 8);
01867
01868     /* Byte 3 */
01869     tmp = (sd_status[0] & 0xFF000000U) >> 24;
01870     pStatus->CardType |= (uint16_t)tmp;
01871
01872     /* Byte 4 */
01873     tmp = (sd_status[1] & 0xFF);
01874     pStatus->ProtectedAreaSize = (uint32_t)(tmp << 24);
01875
01876     /* Byte 5 */
01877     tmp = (sd_status[1] & 0xFF00) >> 8;
01878     pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 16);
01879
01880     /* Byte 6 */
01881     tmp = (sd_status[1] & 0xFF0000) >> 16;
01882     pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 8);
01883
01884     /* Byte 7 */
01885     tmp = (sd_status[1] & 0xFF000000U) >> 24;
01886     pStatus->ProtectedAreaSize |= (uint32_t)tmp;
01887
01888     /* Byte 8 */
01889     tmp = (sd_status[2] & 0xFF);
01890     pStatus->SpeedClass = (uint8_t)tmp;
01891
01892     /* Byte 9 */
01893     tmp = (sd_status[2] & 0xFF00) >> 8;
01894     pStatus->PerformanceMove = (uint8_t)tmp;
01895
01896     /* Byte 10 */
01897     tmp = (sd_status[2] & 0xF00000) >> 20;
01898     pStatus->AllocationUnitSize = (uint8_t)tmp;
01899
01900     /* Byte 11 */
01901     tmp = (sd_status[2] & 0xFF000000U) >> 24;
01902     pStatus->EraseSize = (uint16_t)(tmp << 8);
01903
01904     /* Byte 12 */
01905     tmp = (sd_status[3] & 0xFF);
01906     pStatus->EraseSize |= (uint16_t)tmp;
01907
01908     /* Byte 13 */
01909     tmp = (sd_status[3] & 0xFC00) >> 10;
01910     pStatus->EraseTimeout = (uint8_t)tmp;
01911
01912     /* Byte 13 */
01913     tmp = (sd_status[3] & 0x0300) >> 8;
01914     pStatus->EraseOffset = (uint8_t)tmp;
01915   }
01916
01917   return HAL_OK;
01918 }
01919
01920
01921 /**
01922   * @brief  Gets the SD card info.
01923   * @param  hsd: Pointer to SD handle
01924   * @param  pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
01925   *         will contain the SD card status information
01926   * @retval HAL status
01927   */
01928 HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
01929 {
01930   pCardInfo->CardType     = (uint32_t)(hsd->SdCard.CardType);
01931   pCardInfo->CardVersion  = (uint32_t)(hsd->SdCard.CardVersion);
01932   pCardInfo->Class        = (uint32_t)(hsd->SdCard.Class);
01933   pCardInfo->RelCardAdd   = (uint32_t)(hsd->SdCard.RelCardAdd);
01934   pCardInfo->BlockNbr     = (uint32_t)(hsd->SdCard.BlockNbr);
01935   pCardInfo->BlockSize    = (uint32_t)(hsd->SdCard.BlockSize);
01936   pCardInfo->LogBlockNbr  = (uint32_t)(hsd->SdCard.LogBlockNbr);
01937   pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
01938
01939   return HAL_OK;
01940 }
01941
01942 /**
01943   * @brief  Enables wide bus operation for the requested card if supported by
01944   *         card.
01945   * @param  hsd: Pointer to SD handle
01946   * @param  WideMode: Specifies the SD card wide bus mode
01947   *          This parameter can be one of the following values:
01948   *            @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
01949   *            @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
01950   *            @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
01951   * @retval HAL status
01952   */
01953 HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)
01954 {
01955   SDMMC_InitTypeDef Init;
01956   uint32_t errorstate = HAL_SD_ERROR_NONE;
01957
01958   /* Check the parameters */
01959   assert_param(IS_SDMMC_BUS_WIDE(WideMode));
01960
01961   /* Change State */
01962   hsd->State = HAL_SD_STATE_BUSY;
01963
01964   if(hsd->SdCard.CardType != CARD_SECURED)
01965   {
01966     if (WideMode == SDMMC_BUS_WIDE_8B)
01967     {
01968       hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
01969     }
01970     else if(WideMode == SDMMC_BUS_WIDE_4B)
01971     {
01972       errorstate = SD_WideBus_Enable(hsd);
01973       hsd->ErrorCode |= errorstate;
01974     }
01975     else if (WideMode == SDMMC_BUS_WIDE_1B)
01976     {
01977       errorstate = SD_WideBus_Disable(hsd);
01978       hsd->ErrorCode |= errorstate;
01979     }
01980     else
01981     {
01982       /* WideMode is not a valid argument*/
01983       hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
01984     }
01985   }
01986   else
01987   {
01988     /* MMC Card does not support this feature */
01989     hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
01990   }
01991
01992   if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
01993   {
01994     /* Clear all the static flags */
01995     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01996     hsd->State = HAL_SD_STATE_READY;
01997     return HAL_ERROR;
01998   }
01999   else
02000   {
02001     /* Configure the SDMMC peripheral */
02002     Init.ClockEdge           = hsd->Init.ClockEdge;
02003     Init.ClockPowerSave      = hsd->Init.ClockPowerSave;
02004     Init.BusWide             = WideMode;
02005     Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
02006
02007     /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */
02008     if(hsd->Init.ClockDiv >= SDMMC_NSpeed_CLK_DIV)
02009     {
02010       Init.ClockDiv = hsd->Init.ClockDiv;
02011     }
02012     else
02013     {
02014       if(hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
02015       {
02016         Init.ClockDiv = hsd->Init.ClockDiv;
02017       }
02018       else
02019       {
02020         /* No High speed SD card */
02021         Init.ClockDiv = SDMMC_NSpeed_CLK_DIV;
02022       }
02023     }
02024
02025     SDMMC_Init(hsd->Instance, Init);
02026   }
02027
02028   /* Change State */
02029   hsd->State = HAL_SD_STATE_READY;
02030
02031   return HAL_OK;
02032 }
02033
02034 /**
02035   * @brief  Gets the current sd card data state.
02036   * @param  hsd: pointer to SD handle
02037   * @retval Card state
02038   */
02039 HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
02040 {
02041   HAL_SD_CardStateTypedef cardstate =  HAL_SD_CARD_TRANSFER;
02042   uint32_t errorstate = HAL_SD_ERROR_NONE;
02043   uint32_t resp1 = 0;
02044
02045   errorstate = SD_SendStatus(hsd, &resp1);
02046
02047   if (errorstate != HAL_OK)
02048   {
02049     hsd->ErrorCode |= errorstate;
02050   }
02051
02052   cardstate = (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F);
02053
02054   /* Clear all the static flags */
02055   __SDMMC_CLEAR_FLAG(hsd->Instance, SDMMC_STATIC_FLAGS);
02056   return cardstate;
02057 }
02058
02059 /**
02060   * @brief  Abort the current transfer and disable the SD.
02061   * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
02062   *                the configuration information for SD module.
02063   * @retval HAL status
02064   */
02065 HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
02066 {
02067   HAL_SD_CardStateTypedef CardState;
02068
02069   /* DIsable All interrupts */
02070   __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
02071                            SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
02072
02073   /* Clear All flags */
02074   __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
02075
02076   /* If IDMA Context, disable Internal DMA */
02077   hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
02078
02079   hsd->State = HAL_SD_STATE_READY;
02080   CardState = HAL_SD_GetCardState(hsd);
02081   if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
02082   {
02083     hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
02084   }
02085   if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
02086   {
02087     return HAL_ERROR;
02088   }
02089   return HAL_OK;
02090 }
02091
02092
02093 /**
02094   * @brief  Abort the current transfer and disable the SD (IT mode).
02095   * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
02096   *                the configuration information for SD module.
02097   * @retval HAL status
02098   */
02099 HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
02100 {
02101   HAL_SD_CardStateTypedef CardState;
02102
02103   /* DIsable All interrupts */
02104   __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
02105                            SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
02106
02107   /* Clear All flags */
02108   __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
02109
02110   CardState = HAL_SD_GetCardState(hsd);
02111   hsd->State = HAL_SD_STATE_READY;
02112   if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
02113   {
02114     hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
02115   }
02116   if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
02117   {
02118     return HAL_ERROR;
02119   }
02120   else
02121   {
02122     HAL_SD_AbortCallback(hsd);
02123   }
02124
02125   return HAL_OK;
02126 }
02127
02128
02129 /**
02130   * @}
02131   */
02132
02133 /**
02134   * @}
02135   */
02136
02137 /* Private function ----------------------------------------------------------*/
02138 /** @addtogroup SD_Private_Functions
02139   * @{
02140   */
02141
02142
02143 /**
02144   * @brief  Initializes the sd card.
02145   * @param  hsd: Pointer to SD handle
02146   * @retval SD Card error state
02147   */
02148 static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
02149 {
02150   HAL_SD_CardCSDTypedef CSD;
02151   uint32_t errorstate = HAL_SD_ERROR_NONE;
02152   uint16_t sd_rca = 1;
02153
02154   /* Check the power State */
02155   if(SDMMC_GetPowerState(hsd->Instance) == 0)
02156   {
02157     /* Power off */
02158     return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
02159   }
02160
02161   if(hsd->SdCard.CardType != CARD_SECURED)
02162   {
02163
02164       /* Send CMD2 ALL_SEND_CID */
02165       errorstate = SDMMC_CmdSendCID(hsd->Instance);
02166       if(errorstate != HAL_SD_ERROR_NONE)
02167       {
02168         return errorstate;
02169       }
02170
02171
02172       /* Get Card identification number data */
02173       hsd->CID[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
02174       hsd->CID[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
02175       hsd->CID[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
02176       hsd->CID[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
02177
02178   }
02179
02180   if(hsd->SdCard.CardType != CARD_SECURED)
02181   {
02182   /* Send CMD3 SET_REL_ADDR with argument 0 */
02183   /* SD Card publishes its RCA. */
02184   errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
02185   if(errorstate != HAL_SD_ERROR_NONE)
02186   {
02187     return errorstate;
02188   }
02189   }
02190   if(hsd->SdCard.CardType != CARD_SECURED)
02191   {
02192   /* Get the SD card RCA */
02193   hsd->SdCard.RelCardAdd = sd_rca;
02194
02195   /* Send CMD9 SEND_CSD with argument as card's RCA */
02196     errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
02197   if(errorstate != HAL_SD_ERROR_NONE)
02198   {
02199       return errorstate;
02200   }
02201     else
02202     {
02203   /* Get Card Specific Data */
02204       hsd->CSD[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
02205       hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
02206       hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
02207       hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
02208     }
02209   }
02210
02211   /* Get the Card Class */
02212   hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20);
02213
02214   /* Get CSD parameters */
02215   HAL_SD_GetCardCSD(hsd, &CSD);
02216
02217    /* Select the Card */
02218   errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16));
02219   if(errorstate != HAL_SD_ERROR_NONE)
02220   {
02221     return errorstate;
02222   }
02223
02224   /* All cards are initialized */
02225   return HAL_SD_ERROR_NONE;
02226 }
02227
02228 /**
02229   * @brief  Enquires cards about their operating voltage and configures clock
02230   *         controls and stores SD information that will be needed in future
02231   *         in the SD handle.
02232   * @param  hsd: Pointer to SD handle
02233   * @retval error state
02234   */
02235 static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
02236 {
02237   __IO uint32_t count = 0;
02238   uint32_t response = 0, validvoltage = 0;
02239   uint32_t errorstate = HAL_SD_ERROR_NONE;
02240 #if (USE_SD_TRANSCEIVER != 0U)
02241   uint32_t tickstart = HAL_GetTick();
02242 #endif
02243
02244   /* CMD0: GO_IDLE_STATE */
02245   errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
02246   if(errorstate != HAL_SD_ERROR_NONE)
02247   {
02248     return errorstate;
02249   }
02250
02251   /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
02252   errorstate = SDMMC_CmdOperCond(hsd->Instance);
02253   if(errorstate != HAL_SD_ERROR_NONE)
02254   {
02255     hsd->SdCard.CardVersion = CARD_V1_X;
02256   }
02257   else
02258   {
02259     hsd->SdCard.CardVersion = CARD_V2_X;
02260   }
02261
02262   /* SEND CMD55 APP_CMD with RCA as 0 */
02263   errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
02264   if(errorstate != HAL_SD_ERROR_NONE)
02265   {
02266     return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02267   }
02268   else
02269   {
02270     /* SD CARD */
02271     /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
02272     while((!validvoltage) && (count < SDMMC_MAX_VOLT_TRIAL))
02273     {
02274       /* SEND CMD55 APP_CMD with RCA as 0 */
02275       errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
02276       if(errorstate != HAL_SD_ERROR_NONE)
02277       {
02278         return errorstate;
02279       }
02280
02281       /* Send CMD41 */
02282       errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY);
02283       if(errorstate != HAL_SD_ERROR_NONE)
02284       {
02285         return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02286       }
02287
02288       /* Get command response */
02289       response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
02290
02291       /* Get operating voltage*/
02292       validvoltage = (((response >> 31) == 1) ? 1 : 0);
02293
02294       count++;
02295     }
02296
02297     if(count >= SDMMC_MAX_VOLT_TRIAL)
02298     {
02299       return HAL_SD_ERROR_INVALID_VOLTRANGE;
02300     }
02301
02302     if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
02303     {
02304       hsd->SdCard.CardType = CARD_SDHC_SDXC;
02305 #if (USE_SD_TRANSCEIVER != 0U)
02306       if((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY)
02307       {
02308            hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
02309
02310         /* Start switching procedue */
02311         hsd->Instance->POWER |= SDMMC_POWER_VSWITCHEN;
02312
02313         /* Send CMD11 to switch 1.8V mode */
02314         errorstate = SDMMC_CmdVoltageSwitch(hsd->Instance);
02315         if(errorstate != HAL_SD_ERROR_NONE)
02316         {
02317           MODIFY_REG(hsd->Instance->POWER, SDMMC_POWER_VSWITCHEN, 0);
02318           return HAL_SD_ERROR_NONE;
02319         }
02320
02321         /* Check to BusyD0 and CKSTOP */
02322         while(( hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP)
02323         {
02324           if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
02325           {
02326             return HAL_SD_ERROR_TIMEOUT;
02327           }
02328         }
02329
02330         if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0)
02331         {
02332           /* Error when activate Voltage Switch in SDMMC IP */
02333           return SDMMC_ERROR_UNSUPPORTED_FEATURE;
02334         }
02335         else
02336         {
02337           /* Enable Trasciver Switch PIN */
02338           HAL_SD_DriveTransciver_1_8V_Callback(SET);
02339
02340           /* Switch ready */
02341           hsd->Instance->POWER |= SDMMC_POWER_VSWITCH;
02342
02343           /* Check VSWEND Flag */
02344           while(( hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND)
02345           {
02346             if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
02347             {
02348               return HAL_SD_ERROR_TIMEOUT;
02349             }
02350           }
02351           /* Check BusyD0 status */
02352           if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0)
02353           {
02354             /* Error when enabling 1.8V mode */
02355             return HAL_SD_ERROR_INVALID_VOLTRANGE;
02356           }
02357           /* Switch to 1.8V OK */
02358
02359           /* Disable VSWITCH FLAG from SDMMC IP */
02360           hsd->Instance->POWER = 0x13;
02361           /* Clean Status flags */
02362           hsd->Instance->ICR = 0xFFFFFFFF;
02363         }
02364
02365         hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
02366
02367       }
02368 #endif /* USE_SD_TRANSCEIVER  */
02369     }
02370
02371   }
02372
02373   return HAL_SD_ERROR_NONE;
02374 }
02375
02376 /**
02377   * @brief  Turns the SDMMC output signals off.
02378   * @param  hsd: Pointer to SD handle
02379   * @retval HAL status
02380   */
02381 static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd)
02382 {
02383   /* Set Power State to OFF */
02384   SDMMC_PowerState_OFF(hsd->Instance);
02385
02386   return HAL_OK;
02387 }
02388
02389
02390 /**
02391   * @brief  Send Status info command.
02392   * @param  hsd: pointer to SD handle
02393   * @param  pSDstatus: Pointer to the buffer that will contain the SD card status
02394   *         SD Status register)
02395   * @retval error state
02396   */
02397 static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
02398 {
02399   SDMMC_DataInitTypeDef config;
02400   uint32_t errorstate = HAL_SD_ERROR_NONE;
02401   uint32_t tickstart = HAL_GetTick();
02402   uint32_t count = 0;
02403
02404   /* Check SD response */
02405   if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
02406   {
02407     return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
02408   }
02409
02410   /* Set block size for card if it is not equal to current block size for card */
02411   errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
02412   if(errorstate != HAL_SD_ERROR_NONE)
02413   {
02414     hsd->ErrorCode |= HAL_SD_ERROR_NONE;
02415     return errorstate;
02416   }
02417
02418   /* Send CMD55 */
02419   errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
02420   if(errorstate != HAL_SD_ERROR_NONE)
02421   {
02422     hsd->ErrorCode |= HAL_SD_ERROR_NONE;
02423     return errorstate;
02424   }
02425
02426   /* Configure the SD DPSM (Data Path State Machine) */
02427   config.DataTimeOut   = SDMMC_DATATIMEOUT;
02428   config.DataLength    = 64;
02429   config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;
02430   config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
02431   config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
02432   config.DPSM          = SDMMC_DPSM_ENABLE;
02433   SDMMC_ConfigData(hsd->Instance, &config);
02434
02435   /* Send ACMD13 (SD_APP_STAUS)  with argument as card's RCA */
02436   errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
02437   if(errorstate != HAL_SD_ERROR_NONE)
02438   {
02439     hsd->ErrorCode |= HAL_SD_ERROR_NONE;
02440     return errorstate;
02441   }
02442
02443   /* Get status data */
02444   while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
02445   {
02446     if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
02447     {
02448       for(count = 0; count < 8; count++)
02449       {
02450         *(pSDstatus + count) = SDMMC_ReadFIFO(hsd->Instance);
02451       }
02452
02453       pSDstatus += 8;
02454     }
02455
02456     if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
02457     {
02458       return HAL_SD_ERROR_TIMEOUT;
02459     }
02460   }
02461
02462   if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
02463   {
02464     return HAL_SD_ERROR_DATA_TIMEOUT;
02465   }
02466   else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
02467   {
02468     return HAL_SD_ERROR_DATA_CRC_FAIL;
02469   }
02470   else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
02471   {
02472     return HAL_SD_ERROR_RX_OVERRUN;
02473   }
02474
02475   while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)))
02476   {
02477     *pSDstatus = SDMMC_ReadFIFO(hsd->Instance);
02478     pSDstatus++;
02479
02480     if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
02481     {
02482       return HAL_SD_ERROR_TIMEOUT;
02483     }
02484   }
02485
02486   /* Clear all the static status flags*/
02487   __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
02488
02489   return HAL_SD_ERROR_NONE;
02490 }
02491
02492 /**
02493   * @brief  Returns the current card's status.
02494   * @param  hsd: Pointer to SD handle
02495   * @param  pCardStatus: pointer to the buffer that will contain the SD card
02496   *         status (Card Status register)
02497   * @retval error state
02498   */
02499 static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
02500 {
02501   uint32_t errorstate = HAL_SD_ERROR_NONE;
02502
02503   if(pCardStatus == NULL)
02504   {
02505     return HAL_SD_ERROR_PARAM;
02506   }
02507
02508   /* Send Status command */
02509   errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
02510   if(errorstate != HAL_OK)
02511   {
02512     return errorstate;
02513   }
02514
02515   /* Get SD card status */
02516   *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
02517
02518   return HAL_SD_ERROR_NONE;
02519 }
02520
02521 /**
02522   * @brief  Enables the SDMMC wide bus mode.
02523   * @param  hsd: pointer to SD handle
02524   * @retval error state
02525   */
02526 static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
02527 {
02528   uint32_t scr[2] = {0, 0};
02529   uint32_t errorstate = HAL_SD_ERROR_NONE;
02530
02531   if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
02532   {
02533     return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
02534   }
02535
02536   /* Get SCR Register */
02537   errorstate = SD_FindSCR(hsd, scr);
02538   if(errorstate != HAL_OK)
02539   {
02540     return errorstate;
02541   }
02542
02543   /* If requested card supports wide bus operation */
02544   if((scr[1] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
02545   {
02546   /* Send CMD55 APP_CMD with argument as card's RCA.*/
02547   errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
02548   if(errorstate != HAL_OK)
02549   {
02550     return errorstate;
02551   }
02552
02553   /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
02554   errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2);
02555   if(errorstate != HAL_OK)
02556   {
02557     return errorstate;
02558   }
02559
02560   return HAL_SD_ERROR_NONE;
02561 }
02562   else
02563   {
02564     return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
02565   }
02566 }
02567
02568 /**
02569   * @brief  Disables the SDMMC wide bus mode.
02570   * @param  hsd: Pointer to SD handle
02571   * @retval error state
02572   */
02573 static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
02574 {
02575   uint32_t scr[2] = {0, 0};
02576   uint32_t errorstate = HAL_SD_ERROR_NONE;
02577
02578   if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
02579   {
02580     return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
02581   }
02582
02583   /* Get SCR Register */
02584   errorstate = SD_FindSCR(hsd, scr);
02585   if(errorstate != HAL_OK)
02586   {
02587     return errorstate;
02588   }
02589
02590   /* If requested card supports 1 bit mode operation */
02591   if((scr[1] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
02592   {
02593     /* Send CMD55 APP_CMD with argument as card's RCA */
02594     errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
02595     if(errorstate != HAL_OK)
02596     {
02597       return errorstate;
02598     }
02599
02600     /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
02601     errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0);
02602     if(errorstate != HAL_OK)
02603     {
02604       return errorstate;
02605     }
02606   }
02607
02608   return HAL_SD_ERROR_NONE;
02609 }
02610
02611
02612
02613 /**
02614   * @brief  Finds the SD card SCR register value.
02615   * @param  hsd: Pointer to SD handle
02616   * @param  pSCR: pointer to the buffer that will contain the SCR value
02617   * @retval error state
02618   */
02619 static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
02620 {
02621   SDMMC_DataInitTypeDef config;
02622   uint32_t errorstate = HAL_SD_ERROR_NONE;
02623   uint32_t tickstart = HAL_GetTick();
02624   uint32_t tempscr[2] = {0, 0};
02625
02626   /* Set Block Size To 8 Bytes */
02627   errorstate = SDMMC_CmdBlockLength(hsd->Instance, (uint32_t)8);
02628   if(errorstate != HAL_OK)
02629   {
02630     return errorstate;
02631   }
02632
02633   /* Send CMD55 APP_CMD with argument as card's RCA */
02634   errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16));
02635   if(errorstate != HAL_OK)
02636   {
02637     return errorstate;
02638   }
02639
02640   config.DataTimeOut   = SDMMC_DATATIMEOUT;
02641   config.DataLength    = 8;
02642   config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;
02643   config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
02644   config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
02645   config.DPSM          = SDMMC_DPSM_ENABLE;
02646   SDMMC_ConfigData(hsd->Instance, &config);
02647
02648   /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
02649   errorstate = SDMMC_CmdSendSCR(hsd->Instance);
02650   if(errorstate != HAL_OK)
02651   {
02652     return errorstate;
02653   }
02654
02655   while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DATAEND))
02656   {
02657     if(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE))
02658     {
02659       tempscr[0] = SDMMC_ReadFIFO(hsd->Instance);
02660       tempscr[1] = SDMMC_ReadFIFO(hsd->Instance);
02661       break;
02662     }
02663
02664     if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
02665     {
02666       return HAL_SD_ERROR_TIMEOUT;
02667     }
02668   }
02669
02670   if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
02671   {
02672     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
02673
02674     return HAL_SD_ERROR_DATA_TIMEOUT;
02675   }
02676   else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
02677   {
02678     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
02679
02680     return HAL_SD_ERROR_DATA_CRC_FAIL;
02681   }
02682   else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
02683   {
02684     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
02685
02686     return HAL_SD_ERROR_RX_OVERRUN;
02687   }
02688   else
02689   {
02690     /* No error flag set */
02691     /* Clear all the static flags */
02692     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
02693
02694     *(pSCR + 1) = ((tempscr[0] & SDMMC_0TO7BITS) << 24)  | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\
02695       ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24);
02696
02697     *(pSCR) = ((tempscr[1] & SDMMC_0TO7BITS) << 24)  | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\
02698       ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24);
02699   }
02700
02701   return HAL_SD_ERROR_NONE;
02702 }
02703
02704 /**
02705   * @brief  Wrap up writing in non-blocking mode.
02706   * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
02707   *              the configuration information.
02708   * @retval HAL status
02709   */
02710 static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd)
02711 {
02712   uint32_t count = 0;
02713   uint32_t* tmp;
02714
02715   tmp = (uint32_t*)hsd->pRxBuffPtr;
02716
02717   /* Read data from SDMMC Rx FIFO */
02718   for(count = 0; count < 8; count++)
02719   {
02720     *(tmp + count) = SDMMC_ReadFIFO(hsd->Instance);
02721   }
02722
02723   hsd->pRxBuffPtr += 8;
02724
02725   return HAL_OK;
02726 }
02727
02728
02729 /**
02730   * @brief  Wrap up writing in non-blocking mode.
02731   * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
02732   *              the configuration information.
02733   * @retval HAL status
02734   */
02735 static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd)
02736 {
02737   uint32_t count = 0;
02738   uint32_t* tmp;
02739
02740   tmp = (uint32_t*)hsd->pTxBuffPtr;
02741
02742   /* Write data to SDMMC Tx FIFO */
02743   for(count = 0; count < 8; count++)
02744   {
02745     SDMMC_WriteFIFO(hsd->Instance, (tmp + count));
02746   }
02747
02748   hsd->pTxBuffPtr += 8;
02749
02750   return HAL_OK;
02751 }
02752
02753 #if (USE_SD_TRANSCEIVER != 0U)
02754 /**
02755   * @brief  Switches the SD card to High Speed mode.
02756   *         This API must be used after "Transfer State"
02757   * @note   This operation should be followed by the configuration
02758   *         of PLL to have SDMMCCK clock between 50 and 120 MHz
02759   * @param  hsd: SD handle
02760   * @retval SD Card error state
02761   */
02762 static uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd)
02763 {
02764   uint32_t errorstate = HAL_OK;
02765   SDMMC_DataInitTypeDef sdmmc_datainitstructure;
02766   uint8_t SD_hs[64]  = {0};
02767   uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs;
02768   uint32_t Timeout = HAL_GetTick();
02769
02770   if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
02771   {
02772      /* Standard Speed Card <= 12.5Mhz  */
02773      return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
02774   }
02775
02776   if(hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
02777   {
02778     /* Initialize the Data control register */
02779     hsd->Instance->DCTRL = 0;
02780     errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
02781
02782     if (errorstate != HAL_OK)
02783     {
02784       return errorstate;
02785     }
02786
02787     /* Configure the SD DPSM (Data Path State Machine) */
02788     sdmmc_datainitstructure.DataTimeOut   = SDMMC_DATATIMEOUT;
02789     sdmmc_datainitstructure.DataLength    = 64;
02790     sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
02791     sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
02792     sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
02793     sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
02794     SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure);
02795
02796     errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR104_SWITCH_PATTERN);
02797     if(errorstate != HAL_OK)
02798     {
02799       return errorstate;
02800     }
02801
02802     while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND ))
02803     {
02804       if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
02805       {
02806         for (count = 0; count < 8; count++)
02807         {
02808           *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);
02809         }
02810
02811         tempbuff += 8;
02812       }
02813
02814       if((HAL_GetTick()-Timeout) >=  SDMMC_DATATIMEOUT)
02815       {
02816         hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
02817         hsd->State= HAL_SD_STATE_READY;
02818         return HAL_TIMEOUT;
02819       }
02820     }
02821
02822     if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
02823     {
02824       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
02825
02826       errorstate = 0;
02827
02828       return errorstate;
02829     }
02830     else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
02831     {
02832       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
02833
02834       errorstate = SDMMC_ERROR_DATA_CRC_FAIL;
02835
02836       return errorstate;
02837     }
02838     else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
02839     {
02840       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
02841
02842       errorstate = SDMMC_ERROR_RX_OVERRUN;
02843
02844       return errorstate;
02845     }
02846     else
02847     {
02848       /* No error flag set */
02849     }
02850
02851     /* Clear all the static flags */
02852     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
02853
02854     /* Test if the switch mode HS is ok */
02855     if ((SD_hs[13]& 2) != 2)
02856     {
02857       errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
02858     }
02859     else
02860     {
02861
02862       /* Enable DelayBlock IP */
02863       /* SDMMC_FB_CLK tuned feedback clock selected as receive clock, for SDR104 */
02864       MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX, SDMMC_CLKCR_SELCLKRX /*SDMMC_CLKCR_SELCLKRX_1*/);
02865       DelayBlock_Enable(DLYB_SDMMC1);
02866
02867     }
02868   }
02869
02870   return errorstate;
02871 }
02872 #endif /* USE_SD_TRANSCEIVER */
02873
02874 /**
02875   * @brief Read DMA Buffer 0 Transfer completed callbacks
02876   * @param hsd: SD handle
02877   * @retval None
02878   */
02879 __weak void HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd)
02880 {
02881   /* Prevent unused argument(s) compilation warning */
02882   UNUSED(hsd);
02883
02884   /* NOTE : This function should not be modified, when the callback is needed,
02885             the HAL_SDEx_Read_DMADoubleBuffer0CpltCallback can be implemented in the user file
02886    */
02887 }
02888
02889 /**
02890   * @brief Read DMA Buffer 1 Transfer completed callbacks
02891   * @param hsd: SD handle
02892   * @retval None
02893   */
02894 __weak void HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd)
02895 {
02896   /* Prevent unused argument(s) compilation warning */
02897   UNUSED(hsd);
02898
02899   /* NOTE : This function should not be modified, when the callback is needed,
02900             the HAL_SDEx_Read_DMADoubleBuffer1CpltCallback can be implemented in the user file
02901    */
02902 }
02903
02904 /**
02905   * @brief Write DMA Buffer 0 Transfer completed callbacks
02906   * @param hsd: SD handle
02907   * @retval None
02908   */
02909 __weak void HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd)
02910 {
02911   /* Prevent unused argument(s) compilation warning */
02912   UNUSED(hsd);
02913
02914   /* NOTE : This function should not be modified, when the callback is needed,
02915             the HAL_SDEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file
02916    */
02917 }
02918
02919 /**
02920   * @brief Write DMA Buffer 1 Transfer completed callbacks
02921   * @param hsd: SD handle
02922   * @retval None
02923   */
02924 __weak void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd)
02925 {
02926   /* Prevent unused argument(s) compilation warning */
02927   UNUSED(hsd);
02928
02929   /* NOTE : This function should not be modified, when the callback is needed,
02930             the HAL_SDEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file
02931    */
02932 }
02933
02934
02935 /**
02936   * @}
02937   */
02938
02939
02940 /**
02941   * @}
02942   */
02943 #endif /* HAL_SD_MODULE_ENABLED */
02944 /**
02945   * @}
02946   */
02947
02948 /**
02949   * @}
02950   */
02951
02952 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sd.h Source File

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stm32h7xx_hal_sd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sd.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of SD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_SD_H
00040 #define __STM32H7xx_HAL_SD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_ll_sdmmc.h"
00048 #if (USE_SD_TRANSCEIVER != 0U)
00049 #include "stm32h7xx_ll_delayblock.h"
00050 #endif /* USE_SD_TRANSCEIVER */
00051
00052 /** @addtogroup STM32H7xx_HAL_Driver
00053   * @{
00054   */
00055
00056 /** @addtogroup SD
00057   * @brief SD HAL module driver
00058   * @{
00059   */
00060
00061 /* Exported types ------------------------------------------------------------*/
00062 /** @defgroup SD_Exported_Types SD Exported Types
00063   * @{
00064   */
00065
00066 /** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
00067   * @{
00068   */
00069 typedef enum
00070 {
00071   HAL_SD_STATE_RESET                  = ((uint32_t)0x00000000U),  /*!< SD not yet initialized or disabled  */
00072   HAL_SD_STATE_READY                  = ((uint32_t)0x00000001U),  /*!< SD initialized and ready for use    */
00073   HAL_SD_STATE_TIMEOUT                = ((uint32_t)0x00000002U),  /*!< SD Timeout state                    */
00074   HAL_SD_STATE_BUSY                   = ((uint32_t)0x00000003U),  /*!< SD process ongoing                  */
00075   HAL_SD_STATE_PROGRAMMING            = ((uint32_t)0x00000004U),  /*!< SD Programming State                */
00076   HAL_SD_STATE_RECEIVING              = ((uint32_t)0x00000005U),  /*!< SD Receinving State                 */
00077   HAL_SD_STATE_TRANSFER               = ((uint32_t)0x00000006U),  /*!< SD Transfert State                  */
00078   HAL_SD_STATE_ERROR                  = ((uint32_t)0x0000000FU)   /*!< SD is in error state                */
00079 }HAL_SD_StateTypeDef;
00080 /**
00081   * @}
00082   */
00083
00084 /** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
00085   * @{
00086   */
00087 typedef enum
00088 {
00089   HAL_SD_CARD_READY                  = ((uint32_t)0x00000001U),  /*!< Card state is ready                     */
00090   HAL_SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002U),  /*!< Card is in identification state         */
00091   HAL_SD_CARD_STANDBY                = ((uint32_t)0x00000003U),  /*!< Card is in standby state                */
00092   HAL_SD_CARD_TRANSFER               = ((uint32_t)0x00000004U),  /*!< Card is in transfer state               */
00093   HAL_SD_CARD_SENDING                = ((uint32_t)0x00000005U),  /*!< Card is sending an operation            */
00094   HAL_SD_CARD_RECEIVING              = ((uint32_t)0x00000006U),  /*!< Card is receiving operation information */
00095   HAL_SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007U),  /*!< Card is in programming state            */
00096   HAL_SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008U),  /*!< Card is disconnected                    */
00097   HAL_SD_CARD_ERROR                  = ((uint32_t)0x000000FFU)   /*!< Card response Error                     */
00098 }HAL_SD_CardStateTypedef;
00099 /**
00100   * @}
00101   */
00102
00103 /** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
00104   * @{
00105   */
00106 #define SD_InitTypeDef      SDMMC_InitTypeDef
00107 #define SD_TypeDef          SDMMC_TypeDef
00108
00109 /**
00110   * @brief  SD Card Information Structure definition
00111   */
00112 typedef struct
00113 {
00114   uint32_t CardType;                     /*!< Specifies the card Type                         */
00115
00116   uint32_t CardVersion;                  /*!< Specifies the card version                      */
00117
00118   uint32_t Class;                        /*!< Specifies the class of the card class           */
00119
00120   uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address            */
00121
00122   uint32_t BlockNbr;                     /*!< Specifies the Card Capacity in blocks           */
00123
00124   uint32_t BlockSize;                    /*!< Specifies one block size in bytes               */
00125
00126   uint32_t LogBlockNbr;                  /*!< Specifies the Card logical Capacity in blocks   */
00127
00128   uint32_t LogBlockSize;                 /*!< Specifies logical block size in bytes           */
00129
00130   uint32_t CardSpeed;                    /*!< Specifies the card Speed                        */
00131
00132 }HAL_SD_CardInfoTypeDef;
00133
00134 /**
00135   * @brief  SD handle Structure definition
00136   */
00137
00138 typedef struct
00139 {
00140   SD_TypeDef                   *Instance;        /*!< SD registers base address           */
00141
00142   SD_InitTypeDef               Init;             /*!< SD required parameters                         */
00143
00144   HAL_LockTypeDef              Lock;             /*!< SD locking object                              */
00145
00146   uint32_t                     *pTxBuffPtr;      /*!< Pointer to SD Tx transfer Buffer              */
00147
00148   uint32_t                     TxXferSize;       /*!< SD Tx Transfer size                           */
00149
00150   uint32_t                     *pRxBuffPtr;      /*!< Pointer to SD Rx transfer Buffer              */
00151
00152   uint32_t                     RxXferSize;       /*!< SD Rx Transfer size                           */
00153
00154   __IO uint32_t                Context;          /*!< SD transfer context                           */
00155
00156   __IO HAL_SD_StateTypeDef     State;           /*!< SD card State                                   */
00157
00158   __IO uint32_t                ErrorCode;       /*!< SD Card Error codes                              */
00159
00160   HAL_SD_CardInfoTypeDef       SdCard;           /*!< SD Card information                 */
00161
00162   uint32_t                     CSD[4];           /*!< SD card specific data table         */
00163
00164   uint32_t                     CID[4];           /*!< SD card identification number table */
00165
00166 }SD_HandleTypeDef;
00167
00168
00169 /**
00170   * @}
00171   */
00172
00173 /** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
00174   * @{
00175   */
00176 typedef struct
00177 {
00178   __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
00179   __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
00180   __IO uint8_t  Reserved1;            /*!< Reserved                              */
00181   __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
00182   __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
00183   __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
00184   __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
00185   __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
00186   __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
00187   __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
00188   __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
00189   __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
00190   __IO uint8_t  Reserved2;            /*!< Reserved                              */
00191   __IO uint32_t DeviceSize;           /*!< Device Size                           */
00192   __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
00193   __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
00194   __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
00195   __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
00196   __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
00197   __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
00198   __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
00199   __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
00200   __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
00201   __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
00202   __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
00203   __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
00204   __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
00205   __IO uint8_t  Reserved3;            /*!< Reserved                              */
00206   __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
00207   __IO uint8_t  FileFormatGrouop;     /*!< File format group                     */
00208   __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
00209   __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
00210   __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
00211   __IO uint8_t  FileFormat;           /*!< File format                           */
00212   __IO uint8_t  ECC;                  /*!< ECC code                              */
00213   __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
00214   __IO uint8_t  Reserved4;            /*!< Always 1                              */
00215 }HAL_SD_CardCSDTypedef;
00216 /**
00217   * @}
00218   */
00219
00220 /** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
00221   * @{
00222   */
00223 typedef struct
00224 {
00225   __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
00226   __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
00227   __IO uint32_t ProdName1;       /*!< Product Name part1    */
00228   __IO uint8_t  ProdName2;       /*!< Product Name part2    */
00229   __IO uint8_t  ProdRev;         /*!< Product Revision      */
00230   __IO uint32_t ProdSN;          /*!< Product Serial Number */
00231   __IO uint8_t  Reserved1;       /*!< Reserved1             */
00232   __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
00233   __IO uint8_t  CID_CRC;         /*!< CID CRC               */
00234   __IO uint8_t  Reserved2;       /*!< Always 1              */
00235
00236 }HAL_SD_CardCIDTypedef;
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
00242   * @{
00243   */
00244 typedef struct
00245 {
00246   __IO uint8_t  DataBusWidth;           /*!< Shows the currently defined data bus width                 */
00247   __IO uint8_t  SecuredMode;            /*!< Card is in secured mode of operation                       */
00248   __IO uint16_t CardType;               /*!< Carries information about card type                        */
00249   __IO uint32_t ProtectedAreaSize;      /*!< Carries information about the capacity of protected area   */
00250   __IO uint8_t  SpeedClass;             /*!< Carries information about the speed class of the card      */
00251   __IO uint8_t  PerformanceMove;        /*!< Carries information about the card's performance move      */
00252   __IO uint8_t  AllocationUnitSize;     /*!< Carries information about the card's allocation unit size  */
00253   __IO uint16_t EraseSize;              /*!< Determines the number of AUs to be erased in one operation */
00254   __IO uint8_t  EraseTimeout;           /*!< Determines the timeout for any number of AU erase          */
00255   __IO uint8_t  EraseOffset;            /*!< Carries information about the erase offset                 */
00256
00257 }HAL_SD_CardStatusTypedef;
00258 /**
00259   * @}
00260   */
00261
00262 /**
00263   * @}
00264   */
00265
00266 /* Exported constants --------------------------------------------------------*/
00267 /** @defgroup SD_Exported_Constants Exported Constants
00268   * @{
00269   */
00270
00271 #define BLOCKSIZE   ((uint32_t)512U) /*!< Block size is 512 bytes */
00272
00273 /** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
00274   * @{
00275   */
00276 #define HAL_SD_ERROR_NONE                     SDMMC_ERROR_NONE                        /*!< No error                                                     */
00277 #define HAL_SD_ERROR_CMD_CRC_FAIL             SDMMC_ERROR_CMD_CRC_FAIL                /*!< Command response received (but CRC check failed)             */
00278 #define HAL_SD_ERROR_DATA_CRC_FAIL            SDMMC_ERROR_DATA_CRC_FAIL               /*!< Data block sent/received (CRC check failed)                  */
00279 #define HAL_SD_ERROR_CMD_RSP_TIMEOUT          SDMMC_ERROR_CMD_RSP_TIMEOUT             /*!< Command response timeout                                     */
00280 #define HAL_SD_ERROR_DATA_TIMEOUT             SDMMC_ERROR_DATA_TIMEOUT                /*!< Data timeout                                                 */
00281 #define HAL_SD_ERROR_TX_UNDERRUN              SDMMC_ERROR_TX_UNDERRUN                 /*!< Transmit FIFO underrun                                       */
00282 #define HAL_SD_ERROR_RX_OVERRUN               SDMMC_ERROR_RX_OVERRUN                  /*!< Receive FIFO overrun                                         */
00283 #define HAL_SD_ERROR_ADDR_MISALIGNED          SDMMC_ERROR_ADDR_MISALIGNED             /*!< Misaligned address                                           */
00284 #define HAL_SD_ERROR_BLOCK_LEN_ERR            SDMMC_ERROR_BLOCK_LEN_ERR               /*!< Transferred block length is not allowed for the card or the
00285                                                                                           number of transferred bytes does not match the block length   */
00286 #define HAL_SD_ERROR_ERASE_SEQ_ERR            SDMMC_ERROR_ERASE_SEQ_ERR               /*!< An error in the sequence of erase command occurs             */
00287 #define HAL_SD_ERROR_BAD_ERASE_PARAM          SDMMC_ERROR_BAD_ERASE_PARAM             /*!< An invalid selection for erase groups                        */
00288 #define HAL_SD_ERROR_WRITE_PROT_VIOLATION     SDMMC_ERROR_WRITE_PROT_VIOLATION        /*!< Attempt to program a write protect block                     */
00289 #define HAL_SD_ERROR_LOCK_UNLOCK_FAILED       SDMMC_ERROR_LOCK_UNLOCK_FAILED          /*!< Sequence or password error has been detected in unlock
00290                                                                                            command or if there was an attempt to access a locked card   */
00291 #define HAL_SD_ERROR_COM_CRC_FAILED           SDMMC_ERROR_COM_CRC_FAILED              /*!< CRC check of the previous command failed                     */
00292 #define HAL_SD_ERROR_ILLEGAL_CMD              SDMMC_ERROR_ILLEGAL_CMD                 /*!< Command is not legal for the card state                      */
00293 #define HAL_SD_ERROR_CARD_ECC_FAILED          SDMMC_ERROR_CARD_ECC_FAILED             /*!< Card internal ECC was applied but failed to correct the data */
00294 #define HAL_SD_ERROR_CC_ERR                   SDMMC_ERROR_CC_ERR                      /*!< Internal card controller error                               */
00295 #define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR      SDMMC_ERROR_GENERAL_UNKNOWN_ERR         /*!< General or unknown error                                     */
00296 #define HAL_SD_ERROR_STREAM_READ_UNDERRUN     SDMMC_ERROR_STREAM_READ_UNDERRUN        /*!< The card could not sustain data reading in stream rmode      */
00297 #define HAL_SD_ERROR_STREAM_WRITE_OVERRUN     SDMMC_ERROR_STREAM_WRITE_OVERRUN        /*!< The card could not sustain data programming in stream mode   */
00298 #define HAL_SD_ERROR_CID_CSD_OVERWRITE        SDMMC_ERROR_CID_CSD_OVERWRITE           /*!< CID/CSD overwrite error                                      */
00299 #define HAL_SD_ERROR_WP_ERASE_SKIP            SDMMC_ERROR_WP_ERASE_SKIP               /*!< Only partial address space was erased                        */
00300 #define HAL_SD_ERROR_CARD_ECC_DISABLED        SDMMC_ERROR_CARD_ECC_DISABLED           /*!< Command has been executed without using internal ECC         */
00301 #define HAL_SD_ERROR_ERASE_RESET              SDMMC_ERROR_ERASE_RESET                 /*!< Erase sequence was cleared before executing because an out
00302                                                                                            of erase sequence command was received                       */
00303 #define HAL_SD_ERROR_AKE_SEQ_ERR              SDMMC_ERROR_AKE_SEQ_ERR                 /*!< Error in sequence of authentication                          */
00304 #define HAL_SD_ERROR_INVALID_VOLTRANGE        SDMMC_ERROR_INVALID_VOLTRANGE           /*!< Error in case of invalid voltage range                       */
00305 #define HAL_SD_ERROR_ADDR_OUT_OF_RANGE        SDMMC_ERROR_ADDR_OUT_OF_RANGE           /*!< Error when addressed block is out of range                   */
00306 #define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE   SDMMC_ERROR_REQUEST_NOT_APPLICABLE      /*!< Error when command request is not applicable                 */
00307 #define HAL_SD_ERROR_PARAM                    SDMMC_ERROR_INVALID_PARAMETER           /*!< the used parameter is not valid                              */
00308 #define HAL_SD_ERROR_UNSUPPORTED_FEATURE      SDMMC_ERROR_UNSUPPORTED_FEATURE         /*!< Error when feature is not insupported                        */
00309 #define HAL_SD_ERROR_BUSY                     SDMMC_ERROR_BUSY                        /*!< Error when transfer process is busy                          */
00310 #define HAL_SD_ERROR_DMA                      SDMMC_ERROR_DMA                         /*!< Error while DMA transfer                                     */
00311 #define HAL_SD_ERROR_TIMEOUT                  SDMMC_ERROR_TIMEOUT                     /*!< Timeout Error                                                */
00312
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
00318   * @{
00319   */
00320 #define   SD_CONTEXT_NONE                 ((uint32_t)0x00000000U)  /*!< None                             */
00321 #define   SD_CONTEXT_READ_SINGLE_BLOCK    ((uint32_t)0x00000001U)  /*!< Read single block operation      */
00322 #define   SD_CONTEXT_READ_MULTIPLE_BLOCK  ((uint32_t)0x00000002U)  /*!< Read multiple blocks operation   */
00323 #define   SD_CONTEXT_WRITE_SINGLE_BLOCK   ((uint32_t)0x00000010U)  /*!< Write single block operation     */
00324 #define   SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)  /*!< Write multiple blocks operation  */
00325 #define   SD_CONTEXT_IT                   ((uint32_t)0x00000008U)  /*!< Process in Interrupt mode        */
00326 #define   SD_CONTEXT_DMA                  ((uint32_t)0x00000080U)  /*!< Process in DMA mode              */
00327
00328 /**
00329   * @}
00330   */
00331
00332 /** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
00333   * @{
00334   */
00335 #define CARD_NORMAL_SPEED        ((uint32_t)0x00000000U)    /*!< Normal Speed Card <12.5Mo/s , Spec Version 1.01    */
00336 #define CARD_HIGH_SPEED          ((uint32_t)0x00000100U)    /*!< High Speed Card <25Mo/s , Spec version 2.00        */
00337 #define CARD_ULTRA_HIGH_SPEED    ((uint32_t)0x00000200U)    /*!< UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards
00338                                                                 and <104Mo/s for SDR104, Spec version 3.01          */
00339
00340 #define CARD_SDSC                  ((uint32_t)0x00000000U)  /*!< SD Standard Capacity <2Go                          */
00341 #define CARD_SDHC_SDXC             ((uint32_t)0x00000001U)  /*!< SD High Capacity <32Go, SD Extended Capacity <2To  */
00342 #define CARD_SECURED               ((uint32_t)0x00000003U)
00343
00344 /**
00345   * @}
00346   */
00347
00348 /** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
00349   * @{
00350   */
00351 #define CARD_V1_X                  ((uint32_t)0x00000000U)
00352 #define CARD_V2_X                  ((uint32_t)0x00000001U)
00353 /**
00354   * @}
00355   */
00356
00357 /**
00358   * @}
00359   */
00360
00361 /* Exported macro ------------------------------------------------------------*/
00362 /** @defgroup SD_Exported_macros SD Exported Macros
00363  *  @brief macros to handle interrupts and specific clock configurations
00364  * @{
00365  */
00366
00367 /**
00368   * @brief  Enable the SD device interrupt.
00369   * @param  __HANDLE__: SD Handle
00370   * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
00371   *         This parameter can be one or a combination of the following values:
00372   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
00373   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
00374   *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
00375   *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
00376   *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
00377   *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
00378   *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
00379   *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
00380   *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
00381   *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
00382   *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
00383   *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
00384   *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
00385   *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
00386   *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
00387   *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
00388   *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
00389   *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
00390   *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
00391   *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
00392   *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
00393   *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
00394   *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
00395   * @retval None
00396   */
00397 #define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00398
00399 /**
00400   * @brief  Disable the SD device interrupt.
00401   * @param  __HANDLE__: SD Handle
00402   * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
00403   *          This parameter can be one or a combination of the following values:
00404   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
00405   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
00406   *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
00407   *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
00408   *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
00409   *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
00410   *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
00411   *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
00412   *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
00413   *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
00414   *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
00415   *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
00416   *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
00417   *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
00418   *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
00419   *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
00420   *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
00421   *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
00422   *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
00423   *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
00424   *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
00425   *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
00426   *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
00427   * @retval None
00428   */
00429 #define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00430
00431 /**
00432   * @brief  Check whether the specified SD flag is set or not.
00433   * @param  __HANDLE__: SD Handle
00434   * @param  __FLAG__: specifies the flag to check.
00435   *          This parameter can be one of the following values:
00436   *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
00437   *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
00438   *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout
00439   *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout
00440   *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error
00441   *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error
00442   *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)
00443   *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)
00444   *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)
00445   *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
00446   *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)
00447   *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
00448   *            @arg SDMMC_FLAG_CPSMACT:    Command path state machine active
00449   *            @arg SDMMC_FLAG_DPSMACT:    Data path state machine active
00450   *            @arg SDMMC_FLAG_TXFIFOHE:   Transmit FIFO Half Empty
00451   *            @arg SDMMC_FLAG_RXFIFOHF:   Receive FIFO Half Full
00452   *            @arg SDMMC_FLAG_TXFIFOF:    Transmit FIFO full
00453   *            @arg SDMMC_FLAG_RXFIFOF:    Receive FIFO full
00454   *            @arg SDMMC_FLAG_TXFIFOE:    Transmit FIFO empty
00455   *            @arg SDMMC_FLAG_RXFIFOE:    Receive FIFO empty
00456   *            @arg SDMMC_FLAG_BUSYD0:     Inverted value of SDMMC_D0 line (Busy)
00457   *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
00458   *            @arg SDMMC_FLAG_SDIOIT:     SDIO interrupt received
00459   *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
00460   *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
00461   *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
00462   *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
00463   *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
00464   *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
00465   * @retval The new state of SD FLAG (SET or RESET).
00466   */
00467 #define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
00468
00469 /**
00470   * @brief  Clear the SD's pending flags.
00471   * @param  __HANDLE__: SD Handle
00472   * @param  __FLAG__: specifies the flag to clear.
00473   *          This parameter can be one or a combination of the following values:
00474   *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
00475   *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
00476   *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout
00477   *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout
00478   *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error
00479   *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error
00480   *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)
00481   *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)
00482   *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)
00483   *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
00484   *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)
00485   *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
00486   *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
00487   *            @arg SDMMC_FLAG_SDIOIT:     SDIO interrupt received
00488   *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
00489   *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
00490   *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
00491   *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
00492   *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
00493   *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
00494   * @retval None
00495   */
00496 #define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
00497
00498 /**
00499   * @brief  Check whether the specified SD interrupt has occurred or not.
00500   * @param  __HANDLE__: SD Handle
00501   * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check.
00502   *          This parameter can be one of the following values:
00503   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
00504   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
00505   *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
00506   *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
00507   *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
00508   *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
00509   *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
00510   *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
00511   *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
00512   *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
00513   *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
00514   *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
00515   *            @arg SDMMC_IT_DPSMACT:    Data path state machine active interrupt
00516   *            @arg SDMMC_IT_CPSMACT:    Command path state machine active interrupt
00517   *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
00518   *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
00519   *            @arg SDMMC_IT_TXFIFOF:    Transmit FIFO full interrupt
00520   *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
00521   *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
00522   *            @arg SDMMC_IT_RXFIFOE:    Receive FIFO empty interrupt
00523   *            @arg SDMMC_IT_BUSYD0:     Inverted value of SDMMC_D0 line (Busy)
00524   *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
00525   *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
00526   *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
00527   *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
00528   *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
00529   *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
00530   *            @arg SDMMC_IT_IDMATE:     IDMA transfer error interrupt
00531   *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
00532   * @retval The new state of SD IT (SET or RESET).
00533   */
00534 #define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00535
00536 /**
00537   * @brief  Clear the SD's interrupt pending bits.
00538   * @param  __HANDLE__: SD Handle
00539   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
00540   *          This parameter can be one or a combination of the following values:
00541   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
00542   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
00543   *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
00544   *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
00545   *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
00546   *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
00547   *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
00548   *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
00549   *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
00550   *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
00551   *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
00552   *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
00553   *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
00554   *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
00555   *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
00556   *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
00557   *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
00558   *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
00559   *            @arg SDMMC_IT_IDMATE:     IDMA transfer error interrupt
00560   *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
00561   * @retval None
00562   */
00563 #define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00564
00565 /**
00566   * @}
00567   */
00568
00569   /* Include SD HAL Extension module */
00570 #include "stm32h7xx_hal_sd_ex.h"
00571
00572 /* Exported functions --------------------------------------------------------*/
00573 /** @defgroup SD_Exported_Functions SD Exported Functions
00574   * @{
00575   */
00576
00577 /** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
00578   * @{
00579   */
00580 HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
00581 HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
00582 HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
00583 void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
00584 void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
00585
00586 /**
00587   * @}
00588   */
00589
00590 /** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
00591   * @{
00592   */
00593 /* Blocking mode: Polling */
00594 HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
00595 HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
00596 HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
00597 /* Non-Blocking mode: IT */
00598 HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00599 HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00600 /* Non-Blocking mode: DMA */
00601 HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00602 HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00603
00604 void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
00605
00606 /* Callback in non blocking modes (DMA) */
00607 void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
00608 void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
00609 void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
00610 void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
00611
00612 /* Callback to switch in 1.8V mode */
00613 void HAL_SD_DriveTransciver_1_8V_Callback(FlagStatus status);
00614
00615 /**
00616   * @}
00617   */
00618
00619 /** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
00620   * @{
00621   */
00622 HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
00623 /**
00624   * @}
00625   */
00626
00627 /** @defgroup SD_Exported_Functions_Group4 SD card related functions
00628   * @{
00629   */
00630 HAL_StatusTypeDef       HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
00631 HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
00632 HAL_StatusTypeDef       HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef *pCID);
00633 HAL_StatusTypeDef       HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef *pCSD);
00634 HAL_StatusTypeDef       HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pStatus);
00635 HAL_StatusTypeDef       HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
00636 /**
00637   * @}
00638   */
00639
00640 /** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
00641   * @{
00642   */
00643 HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
00644 uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
00645 /**
00646   * @}
00647   */
00648
00649 /** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
00650   * @{
00651   */
00652 HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
00653 HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
00654 /**
00655   * @}
00656   */
00657
00658 /* Private types -------------------------------------------------------------*/
00659 /** @defgroup SD_Private_Types SD Private Types
00660   * @{
00661   */
00662
00663 /**
00664   * @}
00665   */
00666
00667 /* Private defines -----------------------------------------------------------*/
00668 /** @defgroup SD_Private_Defines SD Private Defines
00669   * @{
00670   */
00671
00672 /**
00673   * @}
00674   */
00675
00676 /* Private variables ---------------------------------------------------------*/
00677 /** @defgroup SD_Private_Variables SD Private Variables
00678   * @{
00679   */
00680
00681 /**
00682   * @}
00683   */
00684
00685 /* Private constants ---------------------------------------------------------*/
00686 /** @defgroup SD_Private_Constants SD Private Constants
00687   * @{
00688   */
00689
00690 /**
00691   * @}
00692   */
00693
00694 /* Private macros ------------------------------------------------------------*/
00695 /** @defgroup SD_Private_Macros SD Private Macros
00696   * @{
00697   */
00698
00699 /**
00700   * @}
00701   */
00702
00703 /* Private functions prototypes ----------------------------------------------*/
00704 /** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
00705   * @{
00706   */
00707
00708 /**
00709   * @}
00710   */
00711
00712 /* Private functions ---------------------------------------------------------*/
00713 /** @defgroup SD_Private_Functions SD Private Functions
00714   * @{
00715   */
00716
00717 /**
00718   * @}
00719   */
00720
00721
00722 /**
00723   * @}
00724   */
00725
00726 /**
00727   * @}
00728   */
00729
00730 /**
00731   * @}
00732   */
00733
00734 #ifdef __cplusplus
00735 }
00736 #endif
00737
00738
00739 #endif /* __STM32H7xx_HAL_SD_H */
00740
00741 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sd_ex.c Source File

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stm32h7xx_hal_sd_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sd_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   SD card Extended HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Secure Digital (SD) peripheral:
00010   *           + Extended features functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                         ##### How to use this driver #####
00015   ==============================================================================
00016   [..]
00017    The SD Extension HAL driver can be used as follows:
00018    (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_SDEx_ConfigDMAMultiBuffer() function.
00019
00020    (+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer() and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions.
00021
00022   @endverbatim
00023   ******************************************************************************
00024   * @attention
00025   *
00026   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00027   *
00028   * Redistribution and use in source and binary forms, with or without modification,
00029   * are permitted provided that the following conditions are met:
00030   *   1. Redistributions of source code must retain the above copyright notice,
00031   *      this list of conditions and the following disclaimer.
00032   *   2. Redistributions in binary form must reproduce the above copyright notice,
00033   *      this list of conditions and the following disclaimer in the documentation
00034   *      and/or other materials provided with the distribution.
00035   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00036   *      may be used to endorse or promote products derived from this software
00037   *      without specific prior written permission.
00038   *
00039   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00040   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00041   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00042   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00043   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00044   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00045   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00046   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00047   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00048   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00049   *
00050   ******************************************************************************
00051   */
00052
00053 /* Includes ------------------------------------------------------------------*/
00054 #include "stm32h7xx_hal.h"
00055
00056 /** @addtogroup STM32H7xx_HAL_Driver
00057   * @{
00058   */
00059
00060 /** @defgroup SDEx SDEx
00061   * @brief SD Extended HAL module driver
00062   * @{
00063   */
00064
00065 #ifdef HAL_SD_MODULE_ENABLED
00066
00067 /* Private typedef -----------------------------------------------------------*/
00068 /* Private define ------------------------------------------------------------*/
00069 /* Private macro -------------------------------------------------------------*/
00070 /* Private variables ---------------------------------------------------------*/
00071 /* Private function prototypes -----------------------------------------------*/
00072 /* Private functions ---------------------------------------------------------*/
00073 /* Exported functions --------------------------------------------------------*/
00074 /** @addtogroup SDEx_Exported_Functions
00075   * @{
00076   */
00077
00078 /** @addtogroup SDEx_Exported_Functions_Group1
00079  *  @brief   Multibuffer functions
00080  *
00081 @verbatim
00082   ==============================================================================
00083           ##### Multibuffer functions #####
00084   ==============================================================================
00085   [..]
00086     This section provides functions allowing to configure the multibuffer mode and start read and write
00087     multibuffer mode for SD HAL driver.
00088
00089 @endverbatim
00090   * @{
00091   */
00092
00093 /**
00094   * @brief  Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA.
00095   * @param  hsd: SD handle
00096   * @param  pDataBuffer0: Pointer to the buffer0 that will contain/receive the transfered data
00097   * @param  pDataBuffer1: Pointer to the buffer1 that will contain/receive the transfered data
00098   * @param  BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
00099   * @retval HAL status
00100   */
00101 HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize)
00102 {
00103   if(hsd->State == HAL_SD_STATE_READY)
00104   {
00105     hsd->Instance->IDMABASE0= (uint32_t) pDataBuffer0 ;
00106     hsd->Instance->IDMABASE1= (uint32_t) pDataBuffer1 ;
00107     hsd->Instance->IDMABSIZE= (uint32_t) BufferSize;
00108
00109     return HAL_OK;
00110   }
00111   else
00112   {
00113     return HAL_BUSY;
00114   }
00115 }
00116
00117 /**
00118   * @brief  Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1.
00119   *         Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function.
00120   * @param  hsd: SD handle
00121   * @param  BlockAdd: Block Address from where data is to be read
00122   * @param  NumberOfBlocks: Total number of blocks to read
00123   * @retval HAL status
00124   */
00125 HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
00126 {
00127   SDMMC_DataInitTypeDef config;
00128   uint32_t errorstate = HAL_SD_ERROR_NONE;
00129
00130   if(hsd->State == HAL_SD_STATE_READY)
00131   {
00132     if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
00133     {
00134       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
00135       return HAL_ERROR;
00136     }
00137
00138     if ((hsd->Instance->IDMABASE0 == 0) || (hsd->Instance->IDMABASE1 == 0) || (hsd->Instance->IDMABSIZE == 0))
00139     {
00140       hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
00141       return HAL_ERROR;
00142     }
00143
00144     /* Initialize data control register */
00145     hsd->Instance->DCTRL = 0;
00146
00147     hsd->ErrorCode = HAL_SD_ERROR_NONE;
00148     hsd->State = HAL_SD_STATE_BUSY;
00149
00150     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
00151     {
00152       BlockAdd *= 512;
00153     }
00154
00155     /* Configure the SD DPSM (Data Path State Machine) */
00156     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00157     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
00158     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00159     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
00160     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00161     config.DPSM          = SDMMC_DPSM_DISABLE;
00162     SDMMC_ConfigData(hsd->Instance, &config);
00163
00164     hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
00165
00166     __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
00167
00168     hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
00169
00170      __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
00171
00172     /* Read Blocks in DMA mode */
00173     hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
00174
00175     /* Read Multi Block command */
00176     errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
00177     if(errorstate != HAL_SD_ERROR_NONE)
00178     {
00179       hsd->State = HAL_SD_STATE_READY;
00180       hsd->ErrorCode |= errorstate;
00181       return HAL_ERROR;
00182     }
00183
00184     return HAL_OK;
00185   }
00186   else
00187   {
00188     return HAL_BUSY;
00189   }
00190
00191 }
00192
00193 /**
00194   * @brief  Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1.
00195   *         Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function.
00196   * @param  hsd: SD handle
00197   * @param  BlockAdd: Block Address from where data is to be read
00198   * @param  NumberOfBlocks: Total number of blocks to read
00199   * @retval HAL status
00200 */
00201 HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
00202 {
00203   SDMMC_DataInitTypeDef config;
00204   uint32_t errorstate = HAL_SD_ERROR_NONE;
00205
00206   if(hsd->State == HAL_SD_STATE_READY)
00207   {
00208     if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
00209     {
00210       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
00211       return HAL_ERROR;
00212     }
00213
00214     if ((hsd->Instance->IDMABASE0 == 0) || (hsd->Instance->IDMABASE1 == 0) || (hsd->Instance->IDMABSIZE == 0))
00215     {
00216       hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
00217       return HAL_ERROR;
00218     }
00219
00220     /* Initialize data control register */
00221     hsd->Instance->DCTRL = 0;
00222
00223     hsd->ErrorCode = HAL_SD_ERROR_NONE;
00224
00225     hsd->State = HAL_SD_STATE_BUSY;
00226
00227     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
00228     {
00229       BlockAdd *= 512;
00230     }
00231
00232     /* Configure the SD DPSM (Data Path State Machine) */
00233     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00234     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
00235     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00236     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
00237     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00238     config.DPSM          = SDMMC_DPSM_DISABLE;
00239     SDMMC_ConfigData(hsd->Instance, &config);
00240
00241     __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
00242
00243     hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
00244
00245     __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
00246
00247     /* Write Blocks in DMA mode */
00248     hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
00249
00250     /* Write Multi Block command */
00251     errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
00252     if(errorstate != HAL_SD_ERROR_NONE)
00253     {
00254       hsd->State = HAL_SD_STATE_READY;
00255       hsd->ErrorCode |= errorstate;
00256       return HAL_ERROR;
00257     }
00258
00259     return HAL_OK;
00260   }
00261   else
00262   {
00263     return HAL_BUSY;
00264   }
00265 }
00266
00267
00268 /**
00269   * @brief  Change the DMA Buffer0 or Buffer1 address on the fly.
00270   * @param  hsd:           pointer to a SD_HandleTypeDef structure.
00271   * @param  Buffer:        the buffer to be changed, This parameter can be one of
00272   *                        the following values: SD_DMA_BUFFER0 or SD_DMA_BUFFER1
00273   * @param  pDataBuffer:   The new address
00274   * @note   The BUFFER0 address can be changed only when the current transfer use
00275   *         BUFFER1 and the BUFFER1 address can be changed only when the current
00276   *         transfer use BUFFER0.
00277   * @retval HAL status
00278   */
00279 HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
00280 {
00281   if(Buffer == SD_DMA_BUFFER0)
00282   {
00283     /* change the buffer0 address */
00284     hsd->Instance->IDMABASE0 = (uint32_t)pDataBuffer;
00285   }
00286   else
00287   {
00288     /* change the memory1 address */
00289     hsd->Instance->IDMABASE1 = (uint32_t)pDataBuffer;
00290   }
00291
00292   return HAL_OK;
00293 }
00294
00295
00296 /**
00297   * @}
00298   */
00299
00300
00301
00302 /**
00303   * @}
00304   */
00305 #endif /* HAL_SD_MODULE_ENABLED */
00306 /**
00307   * @}
00308   */
00309 /**
00310   * @}
00311   */
00312
00313 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sd_ex.h Source File

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  • Inc
stm32h7xx_hal_sd_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sd_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of SD HAL extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_SD_EX_H
00040 #define __STM32H7xx_HAL_SD_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SDEx
00054   * @brief SD HAL extended module driver
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup SDEx_Exported_Types SDEx Exported Types
00060   * @{
00061   */
00062
00063 /** @defgroup SDEx_Exported_Types_Group1 SD Card Internal DMA Buffer structure
00064   * @{
00065   */
00066 typedef enum
00067 {
00068   SD_DMA_BUFFER0      = 0x00U,    /*!< selects SD internal DMA Buffer 0     */
00069   SD_DMA_BUFFER1      = 0x01U,    /*!< selects SD internal DMA Buffer 1     */
00070
00071 }HAL_SDEx_DMABuffer_MemoryTypeDef;
00072
00073
00074 /**
00075   * @}
00076   */
00077
00078 /**
00079   * @}
00080   */
00081 /* Exported constants --------------------------------------------------------*/
00082 /* Exported macro ------------------------------------------------------------*/
00083 /* Exported functions --------------------------------------------------------*/
00084 /** @defgroup SDEx_Exported_Functions SDEx Exported Functions
00085   * @{
00086   */
00087
00088 /** @defgroup SDEx_Exported_Functions_Group1 MultiBuffer functions
00089   * @{
00090   */
00091 HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize);
00092 HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00093 HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00094 HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer);
00095
00096 void HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd);
00097 void HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd);
00098 void HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd);
00099 void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd);
00100
00101 /**
00102   * @}
00103   */
00104
00105 /**
00106   * @}
00107   */
00108
00109 /* Private types -------------------------------------------------------------*/
00110 /* Private defines -----------------------------------------------------------*/
00111 /* Private variables ---------------------------------------------------------*/
00112 /* Private constants ---------------------------------------------------------*/
00113 /* Private macros ------------------------------------------------------------*/
00114 /* Private functions prototypes ----------------------------------------------*/
00115 /* Private functions ---------------------------------------------------------*/
00116
00117 /**
00118   * @}
00119   */
00120
00121 /**
00122   * @}
00123   */
00124 #ifdef __cplusplus
00125 }
00126 #endif
00127
00128
00129 #endif /* __STM32H7xx_HAL_SDEx_H */
00130
00131 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sdram.c Source File

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  • STM32H7xx_HAL_Driver
  • Src
stm32h7xx_hal_sdram.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sdram.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   SDRAM HAL module driver.
00008   *          This file provides a generic firmware to drive SDRAM memories mounted
00009   *          as external device.
00010   *
00011   @verbatim
00012   ==============================================================================
00013                        ##### How to use this driver #####
00014   ==============================================================================
00015   [..]
00016     This driver is a generic layered driver which contains a set of APIs used to
00017     control SDRAM memories. It uses the FMC layer functions to interface
00018     with SDRAM devices.
00019     The following sequence should be followed to configure the FMC to interface
00020     with SDRAM memories:
00021
00022    (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
00023           SDRAM_HandleTypeDef  hdsram
00024
00025        (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
00026             values of the structure member.
00027
00028        (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
00029             base register instance for NOR or SDRAM device
00030
00031    (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
00032           FMC_SDRAM_TimingTypeDef  Timing;
00033       and fill its fields with the allowed values of the structure member.
00034
00035    (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
00036        performs the following sequence:
00037
00038        (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
00039        (##) Control register configuration using the FMC SDRAM interface function
00040             FMC_SDRAM_Init()
00041        (##) Timing register configuration using the FMC SDRAM interface function
00042             FMC_SDRAM_Timing_Init()
00043        (##) Program the SDRAM external device by applying its initialization sequence
00044             according to the device plugged in your hardware. This step is mandatory
00045             for accessing the SDRAM device.
00046
00047    (#) At this stage you can perform read/write accesses from/to the memory connected
00048        to the SDRAM Bank. You can perform either polling or DMA transfer using the
00049        following APIs:
00050        (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
00051        (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
00052
00053    (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
00054        HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
00055        the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
00056        device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
00057        structure.
00058
00059    (#) You can continuously monitor the SDRAM device HAL state by calling the function
00060        HAL_SDRAM_GetState()
00061
00062   @endverbatim
00063   ******************************************************************************
00064   * @attention
00065   *
00066   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00067   *
00068   * Redistribution and use in source and binary forms, with or without modification,
00069   * are permitted provided that the following conditions are met:
00070   *   1. Redistributions of source code must retain the above copyright notice,
00071   *      this list of conditions and the following disclaimer.
00072   *   2. Redistributions in binary form must reproduce the above copyright notice,
00073   *      this list of conditions and the following disclaimer in the documentation
00074   *      and/or other materials provided with the distribution.
00075   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00076   *      may be used to endorse or promote products derived from this software
00077   *      without specific prior written permission.
00078   *
00079   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00080   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00081   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00082   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00083   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00084   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00085   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00086   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00087   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00088   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00089   *
00090   ******************************************************************************
00091   */
00092
00093 /* Includes ------------------------------------------------------------------*/
00094 #include "stm32h7xx_hal.h"
00095
00096 /** @addtogroup STM32H7xx_HAL_Driver
00097   * @{
00098   */
00099
00100 /** @defgroup SDRAM SDRAM
00101   * @brief SDRAM driver modules
00102   * @{
00103   */
00104 #ifdef HAL_SDRAM_MODULE_ENABLED
00105
00106 /* Private typedef -----------------------------------------------------------*/
00107 /* Private define ------------------------------------------------------------*/
00108 /* Private macro -------------------------------------------------------------*/
00109 /* Private variables ---------------------------------------------------------*/
00110 /* Private functions ---------------------------------------------------------*/
00111 /* Exported functions --------------------------------------------------------*/
00112 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
00113   * @{
00114   */
00115
00116 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
00117   * @brief    Initialization and Configuration functions
00118   *
00119   @verbatim
00120   ==============================================================================
00121            ##### SDRAM Initialization and de_initialization functions #####
00122   ==============================================================================
00123   [..]
00124     This section provides functions allowing to initialize/de-initialize
00125     the SDRAM memory
00126
00127 @endverbatim
00128   * @{
00129   */
00130
00131 /**
00132   * @brief  Performs the SDRAM device initialization sequence.
00133   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00134   *                the configuration information for SDRAM module.
00135   * @param  Timing: Pointer to SDRAM control timing structure
00136   * @retval HAL status
00137   */
00138 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
00139 {
00140   /* Check the SDRAM handle parameter */
00141   if(hsdram == NULL)
00142   {
00143     return HAL_ERROR;
00144   }
00145
00146   if(hsdram->State == HAL_SDRAM_STATE_RESET)
00147   {
00148     /* Allocate lock resource and initialize it */
00149     hsdram->Lock = HAL_UNLOCKED;
00150     /* Initialize the low level hardware (MSP) */
00151     HAL_SDRAM_MspInit(hsdram);
00152   }
00153
00154   /* Initialize the SDRAM controller state */
00155   hsdram->State = HAL_SDRAM_STATE_BUSY;
00156
00157   /* Initialize SDRAM control Interface */
00158   FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
00159
00160   /* Initialize SDRAM timing Interface */
00161   FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
00162
00163   /* Enable FMC IP */
00164   __FMC_ENABLE();
00165
00166   /* Update the SDRAM controller state */
00167   hsdram->State = HAL_SDRAM_STATE_READY;
00168
00169   return HAL_OK;
00170 }
00171
00172 /**
00173   * @brief  Perform the SDRAM device initialization sequence.
00174   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00175   *                the configuration information for SDRAM module.
00176   * @retval HAL status
00177   */
00178 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
00179 {
00180   /* Initialize the low level hardware (MSP) */
00181   HAL_SDRAM_MspDeInit(hsdram);
00182
00183   /* Configure the SDRAM registers with their reset values */
00184   FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
00185
00186   /* Reset the SDRAM controller state */
00187   hsdram->State = HAL_SDRAM_STATE_RESET;
00188
00189   /* Release Lock */
00190   __HAL_UNLOCK(hsdram);
00191
00192   return HAL_OK;
00193 }
00194
00195 /**
00196   * @brief  SDRAM MSP Init.
00197   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00198   *                the configuration information for SDRAM module.
00199   * @retval None
00200   */
00201 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
00202 {
00203   /* Prevent unused argument(s) compilation warning */
00204   UNUSED(hsdram);
00205
00206   /* NOTE: This function Should not be modified, when the callback is needed,
00207             the HAL_SDRAM_MspInit could be implemented in the user file
00208    */
00209 }
00210
00211 /**
00212   * @brief  SDRAM MSP DeInit.
00213   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00214   *                the configuration information for SDRAM module.
00215   * @retval None
00216   */
00217 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
00218 {
00219   /* Prevent unused argument(s) compilation warning */
00220   UNUSED(hsdram);
00221
00222   /* NOTE: This function Should not be modified, when the callback is needed,
00223             the HAL_SDRAM_MspDeInit could be implemented in the user file
00224    */
00225 }
00226
00227 /**
00228   * @brief  This function handles SDRAM refresh error interrupt request.
00229   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00230   *                the configuration information for SDRAM module.
00231   * @retval HAL status
00232 */
00233 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
00234 {
00235   /* Check SDRAM interrupt Rising edge flag */
00236   if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
00237   {
00238     /* SDRAM refresh error interrupt callback */
00239     HAL_SDRAM_RefreshErrorCallback(hsdram);
00240
00241     /* Clear SDRAM refresh error interrupt pending bit */
00242     __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
00243   }
00244 }
00245
00246 /**
00247   * @brief  SDRAM Refresh error callback.
00248   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00249   *                the configuration information for SDRAM module.
00250   * @retval None
00251   */
00252 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
00253 {
00254   /* Prevent unused argument(s) compilation warning */
00255   UNUSED(hsdram);
00256
00257   /* NOTE: This function Should not be modified, when the callback is needed,
00258             the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
00259    */
00260 }
00261
00262 /**
00263   * @brief  DMA transfer complete callback.
00264   * @param  hmdma: pointer to a MDMA_HandleTypeDef structure that contains
00265   *                the configuration information for the specified DMA module.
00266   * @retval None
00267   */
00268 __weak void HAL_SDRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma)
00269 {
00270   /* Prevent unused argument(s) compilation warning */
00271   UNUSED(hmdma);
00272
00273   /* NOTE: This function Should not be modified, when the callback is needed,
00274             the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
00275    */
00276 }
00277
00278 /**
00279   * @brief  DMA transfer complete error callback.
00280   * @param  hmdma: DMA handle
00281   * @retval None
00282   */
00283 __weak void HAL_SDRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma)
00284 {
00285   /* Prevent unused argument(s) compilation warning */
00286   UNUSED(hmdma);
00287
00288   /* NOTE: This function Should not be modified, when the callback is needed,
00289             the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
00290    */
00291 }
00292
00293 /**
00294   * @}
00295   */
00296
00297 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
00298   * @brief    Input Output and memory control functions
00299   *
00300   @verbatim
00301   ==============================================================================
00302                     ##### SDRAM Input and Output functions #####
00303   ==============================================================================
00304   [..]
00305     This section provides functions allowing to use and control the SDRAM memory
00306
00307 @endverbatim
00308   * @{
00309   */
00310
00311 /**
00312   * @brief  Reads 8-bit data buffer from the SDRAM memory.
00313   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00314   *                the configuration information for SDRAM module.
00315   * @param  pAddress: Pointer to read start address
00316   * @param  pDstBuffer: Pointer to destination buffer
00317   * @param  BufferSize: Size of the buffer to read from memory
00318   * @retval HAL status
00319   */
00320 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
00321 {
00322   __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
00323
00324   /* Process Locked */
00325   __HAL_LOCK(hsdram);
00326
00327   /* Check the SDRAM controller state */
00328   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00329   {
00330     return HAL_BUSY;
00331   }
00332   else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
00333   {
00334     return  HAL_ERROR;
00335   }
00336
00337   /* Read data from source */
00338   for(; BufferSize != 0; BufferSize--)
00339   {
00340     *pDstBuffer = *(__IO uint8_t *)pSdramAddress;
00341     pDstBuffer++;
00342     pSdramAddress++;
00343   }
00344
00345   /* Process Unlocked */
00346   __HAL_UNLOCK(hsdram);
00347
00348   return HAL_OK;
00349 }
00350
00351
00352 /**
00353   * @brief  Writes 8-bit data buffer to SDRAM memory.
00354   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00355   *                the configuration information for SDRAM module.
00356   * @param  pAddress: Pointer to write start address
00357   * @param  pSrcBuffer: Pointer to source buffer to write
00358   * @param  BufferSize: Size of the buffer to write to memory
00359   * @retval HAL status
00360   */
00361 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
00362 {
00363   __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
00364   uint32_t tmp = 0;
00365
00366   /* Process Locked */
00367   __HAL_LOCK(hsdram);
00368
00369   /* Check the SDRAM controller state */
00370   tmp = hsdram->State;
00371
00372   if(tmp == HAL_SDRAM_STATE_BUSY)
00373   {
00374     return HAL_BUSY;
00375   }
00376   else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
00377   {
00378     return  HAL_ERROR;
00379   }
00380
00381   /* Write data to memory */
00382   for(; BufferSize != 0; BufferSize--)
00383   {
00384     *(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
00385     pSrcBuffer++;
00386     pSdramAddress++;
00387   }
00388
00389   /* Process Unlocked */
00390   __HAL_UNLOCK(hsdram);
00391
00392   return HAL_OK;
00393 }
00394
00395
00396 /**
00397   * @brief  Reads 16-bit data buffer from the SDRAM memory.
00398   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00399   *                the configuration information for SDRAM module.
00400   * @param  pAddress: Pointer to read start address
00401   * @param  pDstBuffer: Pointer to destination buffer
00402   * @param  BufferSize: Size of the buffer to read from memory
00403   * @retval HAL status
00404   */
00405 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
00406 {
00407   __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
00408
00409   /* Process Locked */
00410   __HAL_LOCK(hsdram);
00411
00412   /* Check the SDRAM controller state */
00413   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00414   {
00415     return HAL_BUSY;
00416   }
00417   else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
00418   {
00419     return  HAL_ERROR;
00420   }
00421
00422   /* Read data from source */
00423   for(; BufferSize != 0; BufferSize--)
00424   {
00425     *pDstBuffer = *(__IO uint16_t *)pSdramAddress;
00426     pDstBuffer++;
00427     pSdramAddress++;
00428   }
00429
00430   /* Process Unlocked */
00431   __HAL_UNLOCK(hsdram);
00432
00433   return HAL_OK;
00434 }
00435
00436 /**
00437   * @brief  Writes 16-bit data buffer to SDRAM memory.
00438   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00439   *                the configuration information for SDRAM module.
00440   * @param  pAddress: Pointer to write start address
00441   * @param  pSrcBuffer: Pointer to source buffer to write
00442   * @param  BufferSize: Size of the buffer to write to memory
00443   * @retval HAL status
00444   */
00445 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
00446 {
00447   __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
00448   uint32_t tmp = 0;
00449
00450   /* Process Locked */
00451   __HAL_LOCK(hsdram);
00452
00453   /* Check the SDRAM controller state */
00454   tmp = hsdram->State;
00455
00456   if(tmp == HAL_SDRAM_STATE_BUSY)
00457   {
00458     return HAL_BUSY;
00459   }
00460   else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
00461   {
00462     return  HAL_ERROR;
00463   }
00464
00465   /* Write data to memory */
00466   for(; BufferSize != 0; BufferSize--)
00467   {
00468     *(__IO uint16_t *)pSdramAddress = *pSrcBuffer;
00469     pSrcBuffer++;
00470     pSdramAddress++;
00471   }
00472
00473   /* Process Unlocked */
00474   __HAL_UNLOCK(hsdram);
00475
00476   return HAL_OK;
00477 }
00478
00479 /**
00480   * @brief  Reads 32-bit data buffer from the SDRAM memory.
00481   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00482   *                the configuration information for SDRAM module.
00483   * @param  pAddress: Pointer to read start address
00484   * @param  pDstBuffer: Pointer to destination buffer
00485   * @param  BufferSize: Size of the buffer to read from memory
00486   * @retval HAL status
00487   */
00488 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00489 {
00490   __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
00491
00492   /* Process Locked */
00493   __HAL_LOCK(hsdram);
00494
00495   /* Check the SDRAM controller state */
00496   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00497   {
00498     return HAL_BUSY;
00499   }
00500   else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
00501   {
00502     return  HAL_ERROR;
00503   }
00504
00505   /* Read data from source */
00506   for(; BufferSize != 0; BufferSize--)
00507   {
00508     *pDstBuffer = *(__IO uint32_t *)pSdramAddress;
00509     pDstBuffer++;
00510     pSdramAddress++;
00511   }
00512
00513   /* Process Unlocked */
00514   __HAL_UNLOCK(hsdram);
00515
00516   return HAL_OK;
00517 }
00518
00519 /**
00520   * @brief  Writes 32-bit data buffer to SDRAM memory.
00521   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00522   *                the configuration information for SDRAM module.
00523   * @param  pAddress: Pointer to write start address
00524   * @param  pSrcBuffer: Pointer to source buffer to write
00525   * @param  BufferSize: Size of the buffer to write to memory
00526   * @retval HAL status
00527   */
00528 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00529 {
00530   __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
00531   uint32_t tmp = 0;
00532
00533   /* Process Locked */
00534   __HAL_LOCK(hsdram);
00535
00536   /* Check the SDRAM controller state */
00537   tmp = hsdram->State;
00538
00539   if(tmp == HAL_SDRAM_STATE_BUSY)
00540   {
00541     return HAL_BUSY;
00542   }
00543   else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
00544   {
00545     return  HAL_ERROR;
00546   }
00547
00548   /* Write data to memory */
00549   for(; BufferSize != 0; BufferSize--)
00550   {
00551     *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
00552     pSrcBuffer++;
00553     pSdramAddress++;
00554   }
00555
00556   /* Process Unlocked */
00557   __HAL_UNLOCK(hsdram);
00558
00559   return HAL_OK;
00560 }
00561
00562 /**
00563   * @brief  Reads a Words data from the SDRAM memory using DMA transfer.
00564   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00565   *                the configuration information for SDRAM module.
00566   * @param  pAddress: Pointer to read start address
00567   * @param  pDstBuffer: Pointer to destination buffer
00568   * @param  BufferSize: Size of the buffer to read from memory
00569   * @retval HAL status
00570   */
00571 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00572 {
00573   uint32_t tmp = 0;
00574
00575   /* Process Locked */
00576   __HAL_LOCK(hsdram);
00577
00578   /* Check the SDRAM controller state */
00579   tmp = hsdram->State;
00580
00581   if(tmp == HAL_SDRAM_STATE_BUSY)
00582   {
00583     return HAL_BUSY;
00584   }
00585   else if(tmp == HAL_SDRAM_STATE_PRECHARGED)
00586   {
00587     return  HAL_ERROR;
00588   }
00589
00590   /* Configure DMA user callbacks */
00591   hsdram->hmdma->XferCpltCallback  = HAL_SDRAM_DMA_XferCpltCallback;
00592   hsdram->hmdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
00593
00594   /* Enable the DMA Stream */
00595   HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)(BufferSize * 4), 1);
00596
00597   /* Process Unlocked */
00598   __HAL_UNLOCK(hsdram);
00599
00600   return HAL_OK;
00601 }
00602
00603 /**
00604   * @brief  Writes a Words data buffer to SDRAM memory using DMA transfer.
00605   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00606   *                the configuration information for SDRAM module.
00607   * @param  pAddress: Pointer to write start address
00608   * @param  pSrcBuffer: Pointer to source buffer to write
00609   * @param  BufferSize: Size of the buffer to write to memory
00610   * @retval HAL status
00611   */
00612 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00613 {
00614   uint32_t tmp = 0;
00615
00616   /* Process Locked */
00617   __HAL_LOCK(hsdram);
00618
00619   /* Check the SDRAM controller state */
00620   tmp = hsdram->State;
00621
00622   if(tmp == HAL_SDRAM_STATE_BUSY)
00623   {
00624     return HAL_BUSY;
00625   }
00626   else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
00627   {
00628     return  HAL_ERROR;
00629   }
00630
00631   /* Configure DMA user callbacks */
00632   hsdram->hmdma->XferCpltCallback  = HAL_SDRAM_DMA_XferCpltCallback;
00633   hsdram->hmdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
00634
00635   /* Enable the DMA Stream */
00636   HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)(BufferSize * 4), 1);
00637
00638   /* Process Unlocked */
00639   __HAL_UNLOCK(hsdram);
00640
00641   return HAL_OK;
00642 }
00643
00644 /**
00645   * @}
00646   */
00647
00648 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
00649  *  @brief   management functions
00650  *
00651 @verbatim
00652   ==============================================================================
00653                          ##### SDRAM Control functions #####
00654   ==============================================================================
00655   [..]
00656     This subsection provides a set of functions allowing to control dynamically
00657     the SDRAM interface.
00658
00659 @endverbatim
00660   * @{
00661   */
00662
00663 /**
00664   * @brief  Enables dynamically SDRAM write protection.
00665   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00666   *                the configuration information for SDRAM module.
00667   * @retval HAL status
00668   */
00669 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
00670 {
00671   /* Check the SDRAM controller state */
00672   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00673   {
00674     return HAL_BUSY;
00675   }
00676
00677   /* Update the SDRAM state */
00678   hsdram->State = HAL_SDRAM_STATE_BUSY;
00679
00680   /* Enable write protection */
00681   FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
00682
00683   /* Update the SDRAM state */
00684   hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
00685
00686   return HAL_OK;
00687 }
00688
00689 /**
00690   * @brief  Disables dynamically SDRAM write protection.
00691   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00692   *                the configuration information for SDRAM module.
00693   * @retval HAL status
00694   */
00695 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
00696 {
00697   /* Check the SDRAM controller state */
00698   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00699   {
00700     return HAL_BUSY;
00701   }
00702
00703   /* Update the SDRAM state */
00704   hsdram->State = HAL_SDRAM_STATE_BUSY;
00705
00706   /* Disable write protection */
00707   FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
00708
00709   /* Update the SDRAM state */
00710   hsdram->State = HAL_SDRAM_STATE_READY;
00711
00712   return HAL_OK;
00713 }
00714
00715 /**
00716   * @brief  Sends Command to the SDRAM bank.
00717   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00718   *                the configuration information for SDRAM module.
00719   * @param  Command: SDRAM command structure
00720   * @param  Timeout: Timeout duration
00721   * @retval HAL status
00722   */
00723 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
00724 {
00725   /* Check the SDRAM controller state */
00726   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00727   {
00728     return HAL_BUSY;
00729   }
00730
00731   /* Update the SDRAM state */
00732   hsdram->State = HAL_SDRAM_STATE_BUSY;
00733
00734   /* Send SDRAM command */
00735   FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
00736
00737   /* Update the SDRAM controller state state */
00738   if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
00739   {
00740     hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
00741   }
00742   else
00743   {
00744     hsdram->State = HAL_SDRAM_STATE_READY;
00745   }
00746
00747   return HAL_OK;
00748 }
00749
00750 /**
00751   * @brief  Programs the SDRAM Memory Refresh rate.
00752   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00753   *                the configuration information for SDRAM module.
00754   * @param  RefreshRate: The SDRAM refresh rate value
00755   * @retval HAL status
00756   */
00757 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
00758 {
00759   /* Check the SDRAM controller state */
00760   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00761   {
00762     return HAL_BUSY;
00763   }
00764
00765   /* Update the SDRAM state */
00766   hsdram->State = HAL_SDRAM_STATE_BUSY;
00767
00768   /* Program the refresh rate */
00769   FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
00770
00771   /* Update the SDRAM state */
00772   hsdram->State = HAL_SDRAM_STATE_READY;
00773
00774   return HAL_OK;
00775 }
00776
00777 /**
00778   * @brief  Sets the Number of consecutive SDRAM Memory auto Refresh commands.
00779   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00780   *                the configuration information for SDRAM module.
00781   * @param  AutoRefreshNumber: The SDRAM auto Refresh number
00782   * @retval HAL status
00783   */
00784 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
00785 {
00786   /* Check the SDRAM controller state */
00787   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00788   {
00789     return HAL_BUSY;
00790   }
00791
00792   /* Update the SDRAM state */
00793   hsdram->State = HAL_SDRAM_STATE_BUSY;
00794
00795   /* Set the Auto-Refresh number */
00796   FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);
00797
00798   /* Update the SDRAM state */
00799   hsdram->State = HAL_SDRAM_STATE_READY;
00800
00801   return HAL_OK;
00802 }
00803
00804 /**
00805   * @brief  Returns the SDRAM memory current mode.
00806   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00807   *                the configuration information for SDRAM module.
00808   * @retval The SDRAM memory mode.
00809   */
00810 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
00811 {
00812   /* Return the SDRAM memory current mode */
00813   return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
00814 }
00815
00816 /**
00817   * @}
00818   */
00819
00820 /** @defgroup SDRAM_Exported_Functions_Group4 State functions
00821  *  @brief   Peripheral State functions
00822  *
00823 @verbatim
00824   ==============================================================================
00825                       ##### SDRAM State functions #####
00826   ==============================================================================
00827   [..]
00828     This subsection permits to get in run-time the status of the SDRAM controller
00829     and the data flow.
00830
00831 @endverbatim
00832   * @{
00833   */
00834
00835 /**
00836   * @brief  Returns the SDRAM state.
00837   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00838   *                the configuration information for SDRAM module.
00839   * @retval HAL state
00840   */
00841 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
00842 {
00843   return hsdram->State;
00844 }
00845
00846 /**
00847   * @}
00848   */
00849
00850 /**
00851   * @}
00852   */
00853 #endif /* HAL_SDRAM_MODULE_ENABLED */
00854 /**
00855   * @}
00856   */
00857
00858 /**
00859   * @}
00860   */
00861
00862 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sdram.h Source File

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stm32h7xx_hal_sdram.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sdram.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of SDRAM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_SDRAM_H
00040 #define __STM32H7xx_HAL_SDRAM_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_ll_fmc.h"
00048 #include "stm32h7xx_hal_mdma.h"
00049
00050 /** @addtogroup STM32H7xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup SDRAM
00055   * @{
00056   */
00057
00058 /* Exported typedef ----------------------------------------------------------*/
00059
00060 /** @defgroup SDRAM_Exported_Types SDRAM Exported Types
00061   * @{
00062   */
00063
00064 /**
00065   * @brief  HAL SDRAM State structure definition
00066   */
00067 typedef enum
00068 {
00069   HAL_SDRAM_STATE_RESET             = 0x00U,  /*!< SDRAM not yet initialized or disabled */
00070   HAL_SDRAM_STATE_READY             = 0x01U,  /*!< SDRAM initialized and ready for use   */
00071   HAL_SDRAM_STATE_BUSY              = 0x02U,  /*!< SDRAM internal process is ongoing     */
00072   HAL_SDRAM_STATE_ERROR             = 0x03U,  /*!< SDRAM error state                     */
00073   HAL_SDRAM_STATE_WRITE_PROTECTED   = 0x04U,  /*!< SDRAM device write protected          */
00074   HAL_SDRAM_STATE_PRECHARGED        = 0x05U   /*!< SDRAM device precharged               */
00075
00076 }HAL_SDRAM_StateTypeDef;
00077
00078 /**
00079   * @brief  SDRAM handle Structure definition
00080   */
00081 typedef struct
00082 {
00083   FMC_SDRAM_TypeDef             *Instance;  /*!< Register base address                 */
00084
00085   FMC_SDRAM_InitTypeDef         Init;       /*!< SDRAM device configuration parameters */
00086
00087   __IO HAL_SDRAM_StateTypeDef   State;      /*!< SDRAM access state                    */
00088
00089   HAL_LockTypeDef               Lock;       /*!< SDRAM locking object                  */
00090
00091   MDMA_HandleTypeDef           *hmdma;      /*!< Pointer MDMA handler                   */
00092
00093 }SDRAM_HandleTypeDef;
00094 /**
00095   * @}
00096   */
00097
00098 /* Exported constants --------------------------------------------------------*/
00099 /* Exported macro ------------------------------------------------------------*/
00100
00101 /** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros
00102   * @{
00103   */
00104
00105 /** @brief Reset SDRAM handle state
00106   * @param  __HANDLE__: specifies the SDRAM handle.
00107   * @retval None
00108   */
00109 #define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
00110
00111 /**
00112   * @}
00113   */
00114
00115 /* Exported functions --------------------------------------------------------*/
00116
00117 /** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions
00118   * @{
00119   */
00120
00121 /** @addtogroup SDRAM_Exported_Functions_Group1
00122   * @{
00123   */
00124
00125 /* Initialization/de-initialization functions *********************************/
00126 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
00127 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
00128 void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
00129 void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
00130
00131 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
00132 void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
00133 void HAL_SDRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma);
00134 void HAL_SDRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma);
00135
00136 /**
00137   * @}
00138   */
00139
00140 /** @addtogroup SDRAM_Exported_Functions_Group2
00141   * @{
00142   */
00143 /* I/O operation functions ****************************************************/
00144 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
00145 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
00146 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
00147 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
00148 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00149 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00150 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00151 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00152
00153 /**
00154   * @}
00155   */
00156
00157 /** @addtogroup SDRAM_Exported_Functions_Group3
00158   * @{
00159   */
00160 /* SDRAM Control functions  *****************************************************/
00161 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
00162 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
00163 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
00164 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
00165 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
00166 uint32_t          HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
00167
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup SDRAM_Exported_Functions_Group4
00173   * @{
00174   */
00175 /* SDRAM State functions ********************************************************/
00176 HAL_SDRAM_StateTypeDef  HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
00177 /**
00178   * @}
00179   */
00180
00181 /**
00182   * @}
00183   */
00184
00185 /**
00186   * @}
00187   */
00188
00189 /**
00190   * @}
00191   */
00192
00193 #ifdef __cplusplus
00194 }
00195 #endif
00196
00197 #endif /* __STM32H7xx_HAL_SDRAM_H */
00198
00199 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_smartcard.c Source File

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stm32h7xx_hal_smartcard.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_smartcard.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   SMARTCARD HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the SMARTCARD peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Error functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019   [..]
00020     The SMARTCARD HAL driver can be used as follows:
00021
00022     (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
00023     (#) Associate a USART to the SMARTCARD handle hsmartcard.
00024     (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
00025         (++) Enable the USARTx interface clock.
00026         (++) USART pins configuration:
00027             (+++) Enable the clock for the USART GPIOs.
00028             (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
00029         (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
00030              and HAL_SMARTCARD_Receive_IT() APIs):
00031             (+++) Configure the USARTx interrupt priority.
00032             (+++) Enable the NVIC USART IRQ handle.
00033         (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
00034              and HAL_SMARTCARD_Receive_DMA() APIs):
00035             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00036             (+++) Enable the DMAx interface clock.
00037             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00038             (+++) Configure the DMA Tx/Rx channel.
00039             (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
00040             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00041
00042     (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
00043         the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
00044         error enabling or disabling in the hsmartcard handle Init structure.
00045
00046     (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
00047         in the hsmartcard handle AdvancedInit structure.
00048
00049     (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
00050         (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00051              by calling the customized HAL_SMARTCARD_MspInit() API.
00052         [..]
00053         (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
00054              RXNE interrupt and Error Interrupts) will be managed using the macros
00055              __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
00056
00057     [..]
00058     [..] Three operation modes are available within this driver :
00059
00060      *** Polling mode IO operation ***
00061      =================================
00062      [..]
00063        (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
00064        (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
00065
00066      *** Interrupt mode IO operation ***
00067      ===================================
00068      [..]
00069        (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
00070        (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
00071             add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
00072        (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
00073        (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
00074             add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
00075        (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
00076             add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
00077
00078      *** DMA mode IO operation ***
00079      ==============================
00080      [..]
00081        (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
00082        (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
00083             add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
00084        (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
00085        (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
00086             add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
00087        (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
00088             add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
00089
00090      *** SMARTCARD HAL driver macros list ***
00091      ========================================
00092      [..]
00093        Below the list of most used macros in SMARTCARD HAL driver.
00094
00095        (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
00096        (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
00097        (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
00098        (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
00099        (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled
00100
00101      [..]
00102        (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
00103
00104   @endverbatim
00105   ******************************************************************************
00106   * @attention
00107   *
00108   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00109   *
00110   * Redistribution and use in source and binary forms, with or without modification,
00111   * are permitted provided that the following conditions are met:
00112   *   1. Redistributions of source code must retain the above copyright notice,
00113   *      this list of conditions and the following disclaimer.
00114   *   2. Redistributions in binary form must reproduce the above copyright notice,
00115   *      this list of conditions and the following disclaimer in the documentation
00116   *      and/or other materials provided with the distribution.
00117   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00118   *      may be used to endorse or promote products derived from this software
00119   *      without specific prior written permission.
00120   *
00121   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00122   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00123   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00124   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00125   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00126   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00127   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00128   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00129   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00130   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00131   *
00132   ******************************************************************************
00133   */
00134
00135 /* Includes ------------------------------------------------------------------*/
00136 #include "stm32h7xx_hal.h"
00137
00138 /** @addtogroup STM32H7xx_HAL_Driver
00139   * @{
00140   */
00141
00142 /** @defgroup SMARTCARD SMARTCARD
00143   * @brief HAL SMARTCARD module driver
00144   * @{
00145   */
00146
00147 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00148
00149 /* Private typedef -----------------------------------------------------------*/
00150 /* Private define ------------------------------------------------------------*/
00151 /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
00152  * @{
00153  */
00154 #define SMARTCARD_TEACK_REACK_TIMEOUT               1000      /*!< SMARTCARD TX or RX enable acknowledge time-out value  */
00155
00156 #define USART_CR1_FIELDS      ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
00157                                           USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 | \
00158                                           USART_CR1_FIFOEN)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
00159 #define USART_CR2_CLK_FIELDS  ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
00160 #define USART_CR2_FIELDS      ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
00161 #define USART_CR3_FIELDS      ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT|\
00162                                           USART_CR3_TXFTCFG|USART_CR3_RXFTCFG))   /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
00163 /**
00164   * @}
00165   */
00166
00167 /* Private macros ------------------------------------------------------------*/
00168 /* Private variables ---------------------------------------------------------*/
00169 /* Private function prototypes -----------------------------------------------*/
00170 /** @addtogroup SMARTCARD_Private_Functions
00171   * @{
00172   */
00173 static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
00174 static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
00175 static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
00176 static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
00177 static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
00178 static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
00179 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00180 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00181 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
00182 static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00183 static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00184 static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00185 static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00186 static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00187 static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
00188 static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
00189 static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
00190 /**
00191   * @}
00192   */
00193
00194 /* Exported functions --------------------------------------------------------*/
00195
00196 /** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
00197   * @{
00198   */
00199
00200 /** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
00201   *  @brief    Initialization and Configuration functions
00202   *
00203 @verbatim
00204   ==============================================================================
00205               ##### Initialization and Configuration functions #####
00206   ==============================================================================
00207   [..]
00208   This subsection provides a set of functions allowing to initialize the USARTx
00209   associated to the SmartCard.
00210   (+) These parameters can be configured:
00211       (++) Baud Rate
00212       (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
00213       (++) Receiver/transmitter modes
00214       (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
00215       (++) Prescaler value
00216       (++) Guard bit time
00217       (++) NACK enabling or disabling on transmission error
00218
00219   (+) The following advanced features can be configured as well:
00220       (++) TX and/or RX pin level inversion
00221       (++) data logical level inversion
00222       (++) RX and TX pins swap
00223       (++) RX overrun detection disabling
00224       (++) DMA disabling on RX error
00225       (++) MSB first on communication line
00226       (++) Time out enabling (and if activated, timeout value)
00227       (++) Block length
00228       (++) Auto-retry counter
00229   [..]
00230   The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
00231   (details for the procedures are available in reference manual).
00232
00233 @endverbatim
00234
00235   The USART frame format is given in the following table:
00236
00237     Table 1. USART frame format.
00238     +---------------------------------------------------------------+
00239     | M1M0 bits |  PCE bit  |            USART frame                |
00240     |-----------------------|---------------------------------------|
00241     |     01    |    1      |    | SB | 8 bit data | PB | STB |     |
00242     +---------------------------------------------------------------+
00243
00244
00245   * @{
00246   */
00247
00248 /**
00249   * @brief  Initialize the SMARTCARD mode according to the specified
00250   *         parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
00251   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00252   *                    the configuration information for the specified SMARTCARD module.
00253   * @retval HAL status
00254   */
00255 HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
00256 {
00257   /* Check the SMARTCARD handle allocation */
00258   if(hsmartcard == NULL)
00259   {
00260     return HAL_ERROR;
00261   }
00262
00263   /* Check the USART associated to the SMARTCARD handle */
00264   assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
00265
00266   if(hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
00267   {
00268     /* Allocate lock resource and initialize it */
00269     hsmartcard->Lock = HAL_UNLOCKED;
00270
00271     /* Init the low level hardware : GPIO, CLOCK */
00272     HAL_SMARTCARD_MspInit(hsmartcard);
00273   }
00274
00275   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00276
00277   /* Disable the Peripheral to set smartcard mode */
00278   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00279
00280   /* In SmartCard mode, the following bits must be kept cleared:
00281   - LINEN in the USART_CR2 register,
00282   - HDSEL and IREN  bits in the USART_CR3 register.*/
00283   CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN);
00284   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
00285
00286   /* set the USART in SMARTCARD mode */
00287   SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN);
00288
00289   /* Set the SMARTCARD Communication parameters */
00290   if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
00291   {
00292     return HAL_ERROR;
00293   }
00294
00295   /* Set the SMARTCARD transmission completion indication */
00296   SMARTCARD_TRANSMISSION_COMPLETION_SETTING(hsmartcard);
00297
00298   if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
00299   {
00300     SMARTCARD_AdvFeatureConfig(hsmartcard);
00301   }
00302
00303   /* Enable the Peripheral */
00304   SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00305
00306   /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */
00307   return (SMARTCARD_CheckIdleState(hsmartcard));
00308 }
00309
00310 /**
00311   * @brief  DeInitialize the SMARTCARD peripheral.
00312   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00313   *                    the configuration information for the specified SMARTCARD module.
00314   * @retval HAL status
00315   */
00316 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
00317 {
00318   /* Check the SMARTCARD handle allocation */
00319   if(hsmartcard == NULL)
00320   {
00321     return HAL_ERROR;
00322   }
00323
00324   /* Check the USART/UART associated to the SMARTCARD handle */
00325   assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
00326
00327   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00328
00329   /* Disable the Peripheral */
00330   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00331
00332   WRITE_REG(hsmartcard->Instance->CR1, 0x0);
00333   WRITE_REG(hsmartcard->Instance->CR2, 0x0);
00334   WRITE_REG(hsmartcard->Instance->CR3, 0x0);
00335   WRITE_REG(hsmartcard->Instance->RTOR, 0x0);
00336   WRITE_REG(hsmartcard->Instance->GTPR, 0x0);
00337
00338   /* DeInit the low level hardware */
00339   HAL_SMARTCARD_MspDeInit(hsmartcard);
00340
00341   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00342   hsmartcard->gState    = HAL_SMARTCARD_STATE_RESET;
00343   hsmartcard->RxState   = HAL_SMARTCARD_STATE_RESET;
00344
00345   /* Process Unlock */
00346   __HAL_UNLOCK(hsmartcard);
00347
00348   return HAL_OK;
00349 }
00350
00351 /**
00352   * @brief  Initialize the SMARTCARD MSP.
00353   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00354   *                    the configuration information for the specified SMARTCARD module.
00355   * @retval None
00356   */
00357 __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
00358 {
00359   /* Prevent unused argument(s) compilation warning */
00360   UNUSED(hsmartcard);
00361
00362   /* NOTE : This function should not be modified, when the callback is needed,
00363             the HAL_SMARTCARD_MspInit can be implemented in the user file
00364    */
00365 }
00366
00367 /**
00368   * @brief  DeInitialize the SMARTCARD MSP.
00369   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00370   *                    the configuration information for the specified SMARTCARD module.
00371   * @retval None
00372   */
00373 __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
00374 {
00375   /* Prevent unused argument(s) compilation warning */
00376   UNUSED(hsmartcard);
00377
00378   /* NOTE : This function should not be modified, when the callback is needed,
00379             the HAL_SMARTCARD_MspDeInit can be implemented in the user file
00380    */
00381 }
00382
00383 /**
00384   * @}
00385   */
00386
00387 /** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
00388   *  @brief   SMARTCARD Transmit and Receive functions
00389   *
00390 @verbatim
00391   ==============================================================================
00392                          ##### IO operation functions #####
00393   ==============================================================================
00394   [..]
00395     This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
00396
00397   [..]
00398     Smartcard is a single wire half duplex communication protocol.
00399     The Smartcard interface is designed to support asynchronous protocol Smartcards as
00400     defined in the ISO 7816-3 standard. The USART should be configured as:
00401     (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
00402     (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
00403
00404   [..]
00405     (+) There are two modes of transfer:
00406         (++) Blocking mode: The communication is performed in polling mode.
00407              The HAL status of all data processing is returned by the same function
00408              after finishing transfer.
00409         (++) Non-Blocking mode: The communication is performed using Interrupts
00410              or DMA, the relevant API's return the HAL status.
00411              The end of the data processing will be indicated through the
00412              dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
00413              using DMA mode.
00414         (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
00415              will be executed respectively at the end of the Transmit or Receive process
00416              The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
00417              error is detected.
00418
00419     (+) Blocking mode APIs are :
00420         (++) HAL_SMARTCARD_Transmit()
00421         (++) HAL_SMARTCARD_Receive()
00422
00423     (+) Non Blocking mode APIs with Interrupt are :
00424         (++) HAL_SMARTCARD_Transmit_IT()
00425         (++) HAL_SMARTCARD_Receive_IT()
00426         (++) HAL_SMARTCARD_IRQHandler()
00427
00428     (+) Non Blocking mode functions with DMA are :
00429         (++) HAL_SMARTCARD_Transmit_DMA()
00430         (++) HAL_SMARTCARD_Receive_DMA()
00431
00432     (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00433         (++) HAL_SMARTCARD_TxCpltCallback()
00434         (++) HAL_SMARTCARD_RxCpltCallback()
00435         (++) HAL_SMARTCARD_ErrorCallback()
00436
00437     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00438         (+) HAL_SMARTCARD_Abort()
00439         (+) HAL_SMARTCARD_AbortTransmit()
00440         (+) HAL_SMARTCARD_AbortReceive()
00441         (+) HAL_SMARTCARD_Abort_IT()
00442         (+) HAL_SMARTCARD_AbortTransmit_IT()
00443         (+) HAL_SMARTCARD_AbortReceive_IT()
00444
00445     (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
00446         (+) HAL_SMARTCARD_AbortCpltCallback()
00447         (+) HAL_SMARTCARD_AbortTransmitCpltCallback()
00448         (+) HAL_SMARTCARD_AbortReceiveCpltCallback()
00449
00450     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00451         Errors are handled as follows :
00452        (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00453            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
00454            Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
00455            and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
00456            If user wants to abort it, Abort services should be called by user.
00457        (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00458            This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
00459            Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
00460
00461 @endverbatim
00462   * @{
00463   */
00464
00465 /**
00466   * @brief  Send an amount of data in blocking mode.
00467   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00468   *                    the configuration information for the specified SMARTCARD module.
00469   * @param  pData pointer to data buffer.
00470   * @param  Size amount of data to be sent.
00471   * @param  Timeout  Timeout duration.
00472   * @retval HAL status
00473   */
00474 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00475 {
00476   uint32_t tickstart = 0U;
00477
00478   /* Check that a Tx process is not already ongoing */
00479   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00480   {
00481     if((pData == NULL) || (Size == 0))
00482     {
00483       return  HAL_ERROR;
00484     }
00485
00486     /* Process Locked */
00487     __HAL_LOCK(hsmartcard);
00488
00489     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00490
00491     /* Disable the Peripheral first to update mode for TX master */
00492     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00493
00494     /* Disable Rx, enable Tx */
00495     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00496     SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
00497     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
00498
00499     /* Enable the Peripheral */
00500     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00501
00502     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00503
00504     /* Init tickstart for timeout managment */
00505     tickstart = HAL_GetTick();
00506
00507     hsmartcard->TxXferSize = Size;
00508     hsmartcard->TxXferCount = Size;
00509
00510     while(hsmartcard->TxXferCount > 0)
00511     {
00512       hsmartcard->TxXferCount--;
00513       if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00514       {
00515         return HAL_TIMEOUT;
00516       }
00517       hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFF);
00518     }
00519     if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, Timeout) != HAL_OK)
00520     {
00521       return HAL_TIMEOUT;
00522     }
00523     /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
00524     if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
00525     {
00526       /* Disable the Peripheral first to update modes */
00527       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00528       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00529       /* Enable the Peripheral */
00530       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00531     }
00532
00533     /* At end of Tx process, restore hsmartcard->gState to Ready */
00534     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00535
00536     /* Process Unlocked */
00537     __HAL_UNLOCK(hsmartcard);
00538
00539     return HAL_OK;
00540   }
00541   else
00542   {
00543     return HAL_BUSY;
00544   }
00545 }
00546
00547 /**
00548   * @brief  Receive an amount of data in blocking mode.
00549   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00550   *                    the configuration information for the specified SMARTCARD module.
00551   * @param  pData pointer to data buffer.
00552   * @param  Size amount of data to be received.
00553   * @param  Timeout Timeout duration.
00554   * @retval HAL status
00555   */
00556 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00557 {
00558   uint32_t tickstart = 0U;
00559
00560   /* Check that a Rx process is not already ongoing */
00561   if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
00562   {
00563     if((pData == NULL) || (Size == 0))
00564     {
00565       return  HAL_ERROR;
00566     }
00567
00568     /* Process Locked */
00569     __HAL_LOCK(hsmartcard);
00570
00571     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00572     hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
00573
00574     /* Init tickstart for timeout managment*/
00575     tickstart = HAL_GetTick();
00576
00577     hsmartcard->RxXferSize = Size;
00578     hsmartcard->RxXferCount = Size;
00579
00580     /* Check the remain data to be received */
00581     while(hsmartcard->RxXferCount > 0)
00582     {
00583       hsmartcard->RxXferCount--;
00584
00585       if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00586       {
00587         return HAL_TIMEOUT;
00588       }
00589       *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
00590     }
00591
00592     /* At end of Rx process, restore hsmartcard->RxState to Ready */
00593     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
00594
00595     /* Process Unlocked */
00596     __HAL_UNLOCK(hsmartcard);
00597
00598     return HAL_OK;
00599   }
00600   else
00601   {
00602     return HAL_BUSY;
00603   }
00604 }
00605
00606 /**
00607   * @brief  Send an amount of data in interrupt mode.
00608   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00609   *                    the configuration information for the specified SMARTCARD module.
00610   * @param  pData pointer to data buffer.
00611   * @param  Size amount of data to be sent.
00612   * @retval HAL status
00613   */
00614 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
00615 {
00616   /* Check that a Tx process is not already ongoing */
00617   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00618   {
00619     if((pData == NULL) || (Size == 0))
00620     {
00621       return HAL_ERROR;
00622     }
00623
00624     /* Process Locked */
00625     __HAL_LOCK(hsmartcard);
00626
00627     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00628     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00629
00630     hsmartcard->pTxBuffPtr = pData;
00631     hsmartcard->TxXferSize = Size;
00632     hsmartcard->TxXferCount = Size;
00633
00634     /* Disable the Peripheral first to update mode for TX master */
00635     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00636
00637     /* Disable Rx, enable Tx */
00638     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00639     SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
00640     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
00641
00642     /* Enable the Peripheral */
00643     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00644
00645     /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
00646     SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
00647
00648     /* Process Unlocked */
00649     __HAL_UNLOCK(hsmartcard);
00650
00651     /* Enable the TX FIFO threshold interrupt (if FIFO mode is enabled) or
00652        Transmit Data Register Empty interrupt (if FIFO mode is Disabled).
00653     */
00654     if (READ_BIT(hsmartcard->Instance->CR1, USART_CR1_FIFOEN) != RESET)
00655     {
00656       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
00657     }
00658     else
00659     {
00660       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
00661     }
00662
00663     return HAL_OK;
00664   }
00665   else
00666   {
00667     return HAL_BUSY;
00668   }
00669 }
00670
00671 /**
00672   * @brief  Receive an amount of data in interrupt mode.
00673   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00674   *                    the configuration information for the specified SMARTCARD module.
00675   * @param  pData pointer to data buffer.
00676   * @param  Size amount of data to be received.
00677   * @retval HAL status
00678   */
00679 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
00680 {
00681   /* Check that a Rx process is not already ongoing */
00682   if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
00683   {
00684     if((pData == NULL) || (Size == 0))
00685     {
00686       return HAL_ERROR;
00687     }
00688
00689     /* Process Locked */
00690     __HAL_LOCK(hsmartcard);
00691
00692     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00693     hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
00694
00695     hsmartcard->pRxBuffPtr = pData;
00696     hsmartcard->RxXferSize = Size;
00697     hsmartcard->RxXferCount = Size;
00698
00699     /* Process Unlocked */
00700     __HAL_UNLOCK(hsmartcard);
00701
00702     /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
00703     SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
00704
00705     /* Enable the SMARTCARD Parity Error interupt and RX FIFO Threshold interrupt
00706        (if FIFO mode is enabled) or Data Register Not Empty interrupt
00707        (if FIFO mode is disabled).
00708     */
00709     if (READ_BIT(hsmartcard->Instance->CR1, USART_CR1_FIFOEN) != RESET)
00710     {
00711       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
00712       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE);
00713     }
00714     else
00715     {
00716       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
00717     }
00718
00719     return HAL_OK;
00720   }
00721   else
00722   {
00723     return HAL_BUSY;
00724   }
00725 }
00726
00727 /**
00728   * @brief  Send an amount of data in DMA mode.
00729   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00730   *                    the configuration information for the specified SMARTCARD module.
00731   * @param  pData pointer to data buffer.
00732   * @param  Size amount of data to be sent.
00733   * @retval HAL status
00734   */
00735 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
00736 {
00737   /* Check that a Tx process is not already ongoing */
00738   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00739   {
00740     if((pData == NULL) || (Size == 0))
00741     {
00742       return HAL_ERROR;
00743     }
00744
00745     /* Process Locked */
00746     __HAL_LOCK(hsmartcard);
00747
00748     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00749
00750     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00751     hsmartcard->pTxBuffPtr = pData;
00752     hsmartcard->TxXferSize = Size;
00753     hsmartcard->TxXferCount = Size;
00754
00755     /* Disable the Peripheral first to update mode for TX master */
00756     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00757
00758     /* Disable Rx, enable Tx */
00759     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00760     SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
00761     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
00762
00763     /* Enable the Peripheral */
00764     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00765
00766     /* Set the SMARTCARD DMA transfer complete callback */
00767     hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
00768
00769     /* Set the SMARTCARD error callback */
00770     hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
00771
00772     /* Set the DMA abort callback */
00773     hsmartcard->hdmatx->XferAbortCallback = NULL;
00774
00775     /* Enable the SMARTCARD transmit DMA channel */
00776     HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size);
00777
00778     /* Clear the TC flag in the ICR register */
00779     CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
00780
00781     /* Process Unlocked */
00782     __HAL_UNLOCK(hsmartcard);
00783
00784     /* Enable the UART Error Interrupt: (Frame error) */
00785     SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
00786
00787     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00788        in the SMARTCARD associated USART CR3 register */
00789     SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
00790
00791     return HAL_OK;
00792   }
00793   else
00794   {
00795     return HAL_BUSY;
00796   }
00797 }
00798
00799 /**
00800   * @brief  Receive an amount of data in DMA mode.
00801   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00802   *                    the configuration information for the specified SMARTCARD module.
00803   * @param  pData pointer to data buffer.
00804   * @param  Size amount of data to be received.
00805   * @note   The SMARTCARD-associated USART parity is enabled (PCE = 1),
00806   *         the received data contain the parity bit (MSB position).
00807   * @retval HAL status
00808   */
00809 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
00810 {
00811   /* Check that a Rx process is not already ongoing */
00812   if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
00813   {
00814     if((pData == NULL) || (Size == 0))
00815     {
00816       return HAL_ERROR;
00817     }
00818
00819     /* Process Locked */
00820     __HAL_LOCK(hsmartcard);
00821
00822     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00823     hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
00824
00825     hsmartcard->pRxBuffPtr = pData;
00826     hsmartcard->RxXferSize = Size;
00827
00828     /* Set the SMARTCARD DMA transfer complete callback */
00829     hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
00830
00831     /* Set the SMARTCARD DMA error callback */
00832     hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
00833
00834     /* Set the DMA abort callback */
00835     hsmartcard->hdmarx->XferAbortCallback = NULL;
00836
00837     /* Enable the DMA channel */
00838     HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size);
00839
00840     /* Process Unlocked */
00841     __HAL_UNLOCK(hsmartcard);
00842
00843     /* Enable the SMARTCARD Parity Error Interrupt */
00844     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
00845
00846     /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
00847     SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
00848
00849     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
00850        in the SMARTCARD associated USART CR3 register */
00851     SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
00852
00853     return HAL_OK;
00854   }
00855   else
00856   {
00857     return HAL_BUSY;
00858   }
00859 }
00860
00861 /**
00862   * @brief  Abort ongoing transfers (blocking mode).
00863   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00864   *                    the configuration information for the specified SMARTCARD module.
00865   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
00866   *         This procedure performs following operations :
00867   *           - Disable SMARTCARD Interrupts (Tx and Rx)
00868   *           - Disable the DMA transfer in the peripheral register (if enabled)
00869   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
00870   *           - Set handle State to READY
00871   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
00872   * @retval HAL status
00873 */
00874 HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
00875 {
00876   /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
00877   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
00878   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
00879
00880   /* Disable the SMARTCARD DMA Tx request if enabled */
00881   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
00882   {
00883     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
00884
00885     /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
00886     if(hsmartcard->hdmatx != NULL)
00887     {
00888       /* Set the SMARTCARD DMA Abort callback to Null.
00889          No call back execution at end of DMA abort procedure */
00890       hsmartcard->hdmatx->XferAbortCallback = NULL;
00891
00892       HAL_DMA_Abort(hsmartcard->hdmatx);
00893     }
00894   }
00895
00896   /* Disable the SMARTCARD DMA Rx request if enabled */
00897   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
00898   {
00899     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
00900
00901     /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
00902     if(hsmartcard->hdmarx != NULL)
00903     {
00904       /* Set the SMARTCARD DMA Abort callback to Null.
00905          No call back execution at end of DMA abort procedure */
00906       hsmartcard->hdmarx->XferAbortCallback = NULL;
00907
00908       HAL_DMA_Abort(hsmartcard->hdmarx);
00909     }
00910   }
00911
00912   /* Reset Tx and Rx transfer counters */
00913   hsmartcard->TxXferCount = 0;
00914   hsmartcard->RxXferCount = 0;
00915
00916   /* Clear the Error flags in the ICR register */
00917   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
00918
00919   /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
00920   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
00921   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
00922
00923   /* Reset Handle ErrorCode to No Error */
00924   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00925
00926   return HAL_OK;
00927 }
00928
00929 /**
00930   * @brief  Abort ongoing Transmit transfer (blocking mode).
00931   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00932   *                    the configuration information for the specified SMARTCARD module.
00933   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
00934   *         This procedure performs following operations :
00935   *           - Disable SMARTCARD Interrupts (Tx)
00936   *           - Disable the DMA transfer in the peripheral register (if enabled)
00937   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
00938   *           - Set handle State to READY
00939   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
00940   * @retval HAL status
00941 */
00942 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard)
00943 {
00944   /* Disable TXEIE, TXFTIE and TCIE interrupts */
00945   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
00946   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
00947
00948   /* Check if a receive process is ongoing or not. If not disable ERR IT */
00949   if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
00950   {
00951     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
00952     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
00953   }
00954
00955   /* Disable the SMARTCARD DMA Tx request if enabled */
00956   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
00957   {
00958     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
00959
00960     /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
00961     if(hsmartcard->hdmatx != NULL)
00962     {
00963       /* Set the SMARTCARD DMA Abort callback to Null.
00964          No call back execution at end of DMA abort procedure */
00965       hsmartcard->hdmatx->XferAbortCallback = NULL;
00966
00967       HAL_DMA_Abort(hsmartcard->hdmatx);
00968     }
00969   }
00970
00971   /* Reset Tx transfer counter */
00972   hsmartcard->TxXferCount = 0;
00973
00974   /* Clear the Error flags in the ICR register */
00975   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
00976
00977   /* Restore hsmartcard->gState to Ready */
00978   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00979
00980   return HAL_OK;
00981 }
00982
00983 /**
00984   * @brief  Abort ongoing Receive transfer (blocking mode).
00985   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00986   *                    the configuration information for the specified SMARTCARD module.
00987   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
00988   *         This procedure performs following operations :
00989   *           - Disable SMARTCARD Interrupts (Rx)
00990   *           - Disable the DMA transfer in the peripheral register (if enabled)
00991   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
00992   *           - Set handle State to READY
00993   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
00994   * @retval HAL status
00995 */
00996 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
00997 {
00998   /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
00999   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
01000   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
01001
01002   /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
01003   if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
01004   {
01005     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
01006     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01007   }
01008
01009   /* Disable the SMARTCARD DMA Rx request if enabled */
01010   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01011   {
01012     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01013
01014     /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
01015     if(hsmartcard->hdmarx != NULL)
01016     {
01017       /* Set the SMARTCARD DMA Abort callback to Null.
01018          No call back execution at end of DMA abort procedure */
01019       hsmartcard->hdmarx->XferAbortCallback = NULL;
01020
01021       HAL_DMA_Abort(hsmartcard->hdmarx);
01022     }
01023   }
01024
01025   /* Reset Rx transfer counter */
01026   hsmartcard->RxXferCount = 0;
01027
01028   /* Clear the Error flags in the ICR register */
01029   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01030
01031   /* Restore hsmartcard->RxState to Ready */
01032   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01033
01034   return HAL_OK;
01035 }
01036
01037 /**
01038   * @brief  Abort ongoing transfers (Interrupt mode).
01039   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01040   *                    the configuration information for the specified SMARTCARD module.
01041   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01042   *         This procedure performs following operations :
01043   *           - Disable SMARTCARD Interrupts (Tx and Rx)
01044   *           - Disable the DMA transfer in the peripheral register (if enabled)
01045   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01046   *           - Set handle State to READY
01047   *           - At abort completion, call user abort complete callback
01048   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01049   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01050   * @retval HAL status
01051 */
01052 HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01053 {
01054   uint32_t abortcplt = 1;
01055
01056   /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01057   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
01058   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
01059
01060   /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
01061      before any call to DMA Abort functions */
01062   /* DMA Tx Handle is valid */
01063   if(hsmartcard->hdmatx != NULL)
01064   {
01065     /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
01066        Otherwise, set it to NULL */
01067     if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01068     {
01069       hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
01070     }
01071     else
01072     {
01073       hsmartcard->hdmatx->XferAbortCallback = NULL;
01074     }
01075   }
01076   /* DMA Rx Handle is valid */
01077   if(hsmartcard->hdmarx != NULL)
01078   {
01079     /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
01080        Otherwise, set it to NULL */
01081     if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01082     {
01083       hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
01084     }
01085     else
01086     {
01087       hsmartcard->hdmarx->XferAbortCallback = NULL;
01088     }
01089   }
01090
01091   /* Disable the SMARTCARD DMA Tx request if enabled */
01092   if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01093   {
01094     /* Disable DMA Tx at UART level */
01095     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01096
01097     /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
01098     if(hsmartcard->hdmatx != NULL)
01099     {
01100       /* SMARTCARD Tx DMA Abort callback has already been initialised :
01101          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01102
01103       /* Abort DMA TX */
01104       if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
01105       {
01106         hsmartcard->hdmatx->XferAbortCallback = NULL;
01107       }
01108       else
01109       {
01110         abortcplt = 0;
01111       }
01112     }
01113   }
01114
01115   /* Disable the SMARTCARD DMA Rx request if enabled */
01116   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01117   {
01118     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01119
01120     /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
01121     if(hsmartcard->hdmarx != NULL)
01122     {
01123       /* SMARTCARD Rx DMA Abort callback has already been initialised :
01124          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01125
01126       /* Abort DMA RX */
01127       if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
01128       {
01129         hsmartcard->hdmarx->XferAbortCallback = NULL;
01130         abortcplt = 1;
01131       }
01132       else
01133       {
01134         abortcplt = 0;
01135       }
01136     }
01137   }
01138
01139   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01140   if (abortcplt == 1)
01141   {
01142     /* Reset Tx and Rx transfer counters */
01143     hsmartcard->TxXferCount = 0;
01144     hsmartcard->RxXferCount = 0;
01145
01146     /* Reset errorCode */
01147     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01148
01149     /* Clear the Error flags in the ICR register */
01150     __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01151
01152     /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
01153     hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
01154     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01155
01156     /* As no DMA to be aborted, call directly user Abort complete callback */
01157     HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
01158   }
01159
01160   return HAL_OK;
01161 }
01162
01163 /**
01164   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
01165   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01166   *                    the configuration information for the specified SMARTCARD module.
01167   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01168   *         This procedure performs following operations :
01169   *           - Disable SMARTCARD Interrupts (Tx)
01170   *           - Disable the DMA transfer in the peripheral register (if enabled)
01171   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01172   *           - Set handle State to READY
01173   *           - At abort completion, call user abort complete callback
01174   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01175   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01176   * @retval HAL status
01177 */
01178 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01179 {
01180   /* Disable TXEIE, TXFTIE and TCIE interrupts */
01181   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
01182   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
01183
01184   /* Check if a receive process is ongoing or not. If not disable ERR IT */
01185   if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
01186   {
01187     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
01188     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01189   }
01190
01191   /* Disable the SMARTCARD DMA Tx request if enabled */
01192   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01193   {
01194     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01195
01196     /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
01197     if(hsmartcard->hdmatx != NULL)
01198     {
01199       /* Set the SMARTCARD DMA Abort callback :
01200          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01201       hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
01202
01203       /* Abort DMA TX */
01204       if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
01205       {
01206         /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
01207         hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
01208       }
01209     }
01210     else
01211     {
01212       /* Reset Tx transfer counter */
01213       hsmartcard->TxXferCount = 0;
01214
01215       /* Restore hsmartcard->gState to Ready */
01216       hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01217
01218       /* As no DMA to be aborted, call directly user Abort complete callback */
01219       HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
01220     }
01221   }
01222   else
01223   {
01224     /* Reset Tx transfer counter */
01225     hsmartcard->TxXferCount = 0;
01226
01227     /* Clear the Error flags in the ICR register */
01228     __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
01229
01230     /* Restore hsmartcard->gState to Ready */
01231     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01232
01233     /* As no DMA to be aborted, call directly user Abort complete callback */
01234     HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
01235   }
01236
01237   return HAL_OK;
01238 }
01239
01240 /**
01241   * @brief  Abort ongoing Receive transfer (Interrupt mode).
01242   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01243   *                    the configuration information for the specified SMARTCARD module.
01244   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01245   *         This procedure performs following operations :
01246   *           - Disable SMARTCARD Interrupts (Rx)
01247   *           - Disable the DMA transfer in the peripheral register (if enabled)
01248   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01249   *           - Set handle State to READY
01250   *           - At abort completion, call user abort complete callback
01251   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01252   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01253   * @retval HAL status
01254 */
01255 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01256 {
01257   /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01258   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
01259   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
01260
01261   /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
01262   if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
01263   {
01264     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
01265     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01266   }
01267
01268   /* Disable the SMARTCARD DMA Rx request if enabled */
01269   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01270   {
01271     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01272
01273     /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
01274     if(hsmartcard->hdmarx != NULL)
01275     {
01276       /* Set the SMARTCARD DMA Abort callback :
01277          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01278       hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
01279
01280       /* Abort DMA RX */
01281       if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
01282       {
01283         /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
01284         hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
01285       }
01286     }
01287     else
01288     {
01289       /* Reset Rx transfer counter */
01290       hsmartcard->RxXferCount = 0;
01291
01292       /* Clear the Error flags in the ICR register */
01293       __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01294
01295       /* Restore hsmartcard->RxState to Ready */
01296       hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01297
01298       /* As no DMA to be aborted, call directly user Abort complete callback */
01299       HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
01300     }
01301   }
01302   else
01303   {
01304     /* Reset Rx transfer counter */
01305     hsmartcard->RxXferCount = 0;
01306
01307     /* Clear the Error flags in the ICR register */
01308     __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01309
01310     /* Restore hsmartcard->RxState to Ready */
01311     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01312
01313     /* As no DMA to be aborted, call directly user Abort complete callback */
01314     HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
01315   }
01316
01317   return HAL_OK;
01318 }
01319
01320 /**
01321   * @brief Handle SMARTCARD interrupt requests.
01322   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
01323   *                    the configuration information for the specified SMARTCARD module.
01324   * @retval None
01325   */
01326 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
01327 {
01328   uint32_t isrflags   = READ_REG(hsmartcard->Instance->ISR);
01329   uint32_t cr1its     = READ_REG(hsmartcard->Instance->CR1);
01330   uint32_t cr3its;
01331   uint32_t errorflags;
01332
01333   /* If no error occurs */
01334   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
01335   if (errorflags == RESET)
01336   {
01337     /* SMARTCARD in mode Receiver ---------------------------------------------------*/
01338     if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01339     {
01340       SMARTCARD_Receive_IT(hsmartcard);
01341       /* Clear RXNE interrupt flag done by reading RDR in SMARTCARD_Receive_IT() */
01342       return;
01343     }
01344   }
01345
01346   /* If some errors occur */
01347   cr3its = READ_REG(hsmartcard->Instance->CR3);
01348   if(   (errorflags != RESET)
01349      && (    ((cr3its & USART_CR3_EIE) != RESET)
01350           || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != RESET)) )
01351   {
01352     /* SMARTCARD parity error interrupt occurred -------------------------------------*/
01353     if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
01354     {
01355       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
01356
01357       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
01358     }
01359
01360     /* SMARTCARD frame error interrupt occurred --------------------------------------*/
01361     if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01362     {
01363       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
01364
01365       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
01366     }
01367
01368     /* SMARTCARD noise error interrupt occurred --------------------------------------*/
01369     if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01370     {
01371       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
01372
01373       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
01374     }
01375
01376     /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
01377     if(((isrflags & USART_ISR_ORE) != RESET) &&
01378        (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
01379     {
01380       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
01381
01382       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
01383     }
01384
01385     /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
01386     if(((isrflags & USART_ISR_RTOF) != RESET) && ((cr1its & USART_CR1_RTOIE) != RESET))
01387     {
01388       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
01389
01390       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
01391     }
01392
01393     /* Call SMARTCARD Error Call back function if need be --------------------------*/
01394     if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
01395     {
01396       /* SMARTCARD in mode Receiver ---------------------------------------------------*/
01397       if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01398       {
01399         SMARTCARD_Receive_IT(hsmartcard);
01400       }
01401
01402       /* If Error is to be considered as blocking :
01403           - Receiver Timeout error in Reception
01404           - Overrun error in Reception
01405           - any error occurs in DMA mode reception
01406       */
01407       if (   ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != RESET)
01408           || (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)))
01409       {
01410         /* Blocking error : transfer is aborted
01411            Set the SMARTCARD state ready to be able to start again the process,
01412            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
01413         SMARTCARD_EndRxTransfer(hsmartcard);
01414
01415         /* Disable the SMARTCARD DMA Rx request if enabled */
01416         if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01417         {
01418           CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01419
01420           /* Abort the SMARTCARD DMA Rx channel */
01421           if(hsmartcard->hdmarx != NULL)
01422           {
01423             /* Set the SMARTCARD DMA Abort callback :
01424                will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
01425             hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
01426
01427             /* Abort DMA RX */
01428             if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
01429             {
01430               /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
01431               hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
01432             }
01433           }
01434           else
01435           {
01436             /* Call user error callback */
01437             HAL_SMARTCARD_ErrorCallback(hsmartcard);
01438           }
01439         }
01440         else
01441         {
01442           /* Call user error callback */
01443           HAL_SMARTCARD_ErrorCallback(hsmartcard);
01444         }
01445       }
01446       /* other error type to be considered as blocking :
01447           - Frame error in Transmission
01448       */
01449       else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != RESET))
01450       {
01451         /* Blocking error : transfer is aborted
01452            Set the SMARTCARD state ready to be able to start again the process,
01453            Disable Tx Interrupts, and disable Tx DMA request, if ongoing */
01454         SMARTCARD_EndTxTransfer(hsmartcard);
01455
01456         /* Disable the SMARTCARD DMA Tx request if enabled */
01457         if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01458         {
01459           CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01460
01461           /* Abort the SMARTCARD DMA Tx channel */
01462           if(hsmartcard->hdmatx != NULL)
01463           {
01464             /* Set the SMARTCARD DMA Abort callback :
01465                will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
01466             hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
01467
01468             /* Abort DMA TX */
01469             if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
01470             {
01471               /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
01472               hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
01473             }
01474           }
01475           else
01476           {
01477             /* Call user error callback */
01478             HAL_SMARTCARD_ErrorCallback(hsmartcard);
01479           }
01480         }
01481         else
01482         {
01483           /* Call user error callback */
01484           HAL_SMARTCARD_ErrorCallback(hsmartcard);
01485         }
01486       }
01487       else
01488       {
01489         /* Non Blocking error : transfer could go on.
01490            Error is notified to user through user error callback */
01491         HAL_SMARTCARD_ErrorCallback(hsmartcard);
01492         hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01493       }
01494     }
01495     return;
01496
01497   } /* End if some error occurs */
01498
01499   /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
01500   if(((isrflags & USART_ISR_EOBF) != RESET) && ((cr1its & USART_CR1_EOBIE) != RESET))
01501   {
01502     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01503     __HAL_UNLOCK(hsmartcard);
01504     HAL_SMARTCARD_RxCpltCallback(hsmartcard);
01505     /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
01506      * to be available during HAL_SMARTCARD_RxCpltCallback() processing */
01507     __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
01508     return;
01509   }
01510
01511   /* SMARTCARD in mode Transmitter ------------------------------------------------*/
01512   if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
01513   {
01514     SMARTCARD_Transmit_IT(hsmartcard);
01515     return;
01516   }
01517
01518   /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
01519   if((__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET))
01520   {
01521     SMARTCARD_EndTransmit_IT(hsmartcard);
01522     return;
01523   }
01524 }
01525
01526 /**
01527   * @brief  Tx Transfer completed callback.
01528   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01529   *                    the configuration information for the specified SMARTCARD module.
01530   * @retval None
01531   */
01532 __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
01533 {
01534   /* Prevent unused argument(s) compilation warning */
01535   UNUSED(hsmartcard);
01536
01537   /* NOTE : This function should not be modified, when the callback is needed,
01538             the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
01539    */
01540 }
01541
01542 /**
01543   * @brief  Rx Transfer completed callback.
01544   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01545   *                    the configuration information for the specified SMARTCARD module.
01546   * @retval None
01547   */
01548 __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
01549 {
01550   /* Prevent unused argument(s) compilation warning */
01551   UNUSED(hsmartcard);
01552
01553   /* NOTE : This function should not be modified, when the callback is needed,
01554             the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
01555    */
01556 }
01557
01558 /**
01559   * @brief  SMARTCARD error callback.
01560   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01561   *                    the configuration information for the specified SMARTCARD module.
01562   * @retval None
01563   */
01564 __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
01565 {
01566   /* Prevent unused argument(s) compilation warning */
01567   UNUSED(hsmartcard);
01568
01569   /* NOTE : This function should not be modified, when the callback is needed,
01570             the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
01571    */
01572 }
01573
01574 /**
01575   * @brief  SMARTCARD Abort Complete callback.
01576   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01577   *                    the configuration information for the specified SMARTCARD module.
01578   * @retval None
01579   */
01580 __weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
01581 {
01582   /* Prevent unused argument(s) compilation warning */
01583   UNUSED(hsmartcard);
01584
01585   /* NOTE : This function should not be modified, when the callback is needed,
01586             the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
01587    */
01588 }
01589
01590 /**
01591   * @brief  SMARTCARD Abort Complete callback.
01592   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01593   *                    the configuration information for the specified SMARTCARD module.
01594   * @retval None
01595   */
01596 __weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
01597 {
01598   /* Prevent unused argument(s) compilation warning */
01599   UNUSED(hsmartcard);
01600
01601   /* NOTE : This function should not be modified, when the callback is needed,
01602             the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
01603    */
01604 }
01605
01606 /**
01607   * @brief  SMARTCARD Abort Receive Complete callback.
01608   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01609   *                    the configuration information for the specified SMARTCARD module.
01610   * @retval None
01611   */
01612 __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
01613 {
01614   /* Prevent unused argument(s) compilation warning */
01615   UNUSED(hsmartcard);
01616
01617   /* NOTE : This function should not be modified, when the callback is needed,
01618             the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
01619    */
01620 }
01621
01622 /**
01623   * @}
01624   */
01625
01626 /** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions
01627   *  @brief   SMARTCARD State and Errors functions
01628   *
01629 @verbatim
01630   ==============================================================================
01631                   ##### Peripheral State and Errors functions #####
01632   ==============================================================================
01633   [..]
01634     This subsection provides a set of functions allowing to return the State of SmartCard
01635     handle and also return Peripheral Errors occurred during communication process
01636      (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
01637          of the SMARTCARD peripheral.
01638      (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
01639          communication.
01640
01641 @endverbatim
01642   * @{
01643   */
01644
01645 /**
01646   * @brief  Return the SMARTCARD handle state.
01647   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01648   *                    the configuration information for the specified SMARTCARD module.
01649   * @retval SMARTCARD handle state
01650   */
01651 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
01652 {
01653   /* Return SMARTCARD handle state */
01654   uint32_t temp1= 0x00, temp2 = 0x00;
01655   temp1 = hsmartcard->gState;
01656   temp2 = hsmartcard->RxState;
01657
01658   return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
01659 }
01660
01661 /**
01662   * @brief  Return the SMARTCARD handle error code.
01663   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01664   *                    the configuration information for the specified SMARTCARD module.
01665   * @retval SMARTCARD handle Error Code
01666 */
01667 uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
01668 {
01669   return hsmartcard->ErrorCode;
01670 }
01671
01672 /**
01673   * @}
01674   */
01675
01676 /**
01677   * @}
01678   */
01679
01680 /** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
01681   * @{
01682   */
01683
01684 /**
01685   * @brief Configure the SMARTCARD associated USART peripheral.
01686   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
01687   *                    the configuration information for the specified SMARTCARD module.
01688   * @retval HAL status
01689   */
01690 static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
01691 {
01692   uint32_t tmpreg                          = 0x0U;
01693   SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED;
01694   HAL_StatusTypeDef ret                    = HAL_OK;
01695   PLL2_ClocksTypeDef pll2_clocks;
01696   PLL3_ClocksTypeDef pll3_clocks;
01697
01698   /* Check the parameters */
01699   assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
01700   assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
01701   assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
01702   assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
01703   assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
01704   assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
01705   assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
01706   assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
01707   assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
01708   assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling));
01709   assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
01710   assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
01711   assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
01712   assert_param(IS_SMARTCARD_FIFO_MODE_STATE(hsmartcard->Init.FIFOMode));
01713   if (hsmartcard->Init.FIFOMode == UART_FIFOMODE_ENABLE)
01714   {
01715     assert_param(IS_SMARTCARD_TXFIFO_THRESHOLD(hsmartcard->Init.TXFIFOThreshold));
01716     assert_param(IS_SMARTCARD_RXFIFO_THRESHOLD(hsmartcard->Init.RXFIFOThreshold));
01717   }
01718
01719   /*-------------------------- USART CR1 Configuration -----------------------*/
01720   /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
01721    * Oversampling is forced to 16 (OVER8 = 0).
01722    * Configure the Parity and Mode:
01723    *  set PS bit according to hsmartcard->Init.Parity value
01724    *  set TE and RE bits according to hsmartcard->Init.Mode value */
01725   tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
01726   tmpreg |= (uint32_t) hsmartcard->Init.WordLength;
01727   tmpreg |= (uint32_t) hsmartcard->Init.FIFOMode;
01728   MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
01729
01730   /*-------------------------- USART CR2 Configuration -----------------------*/
01731   tmpreg = hsmartcard->Init.StopBits;
01732   /* Synchronous mode is activated by default */
01733   tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
01734   tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
01735   tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
01736   MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
01737
01738   /*-------------------------- USART CR3 Configuration -----------------------*/
01739   /* Configure
01740    * - one-bit sampling method versus three samples' majority rule
01741    *   according to hsmartcard->Init.OneBitSampling
01742    * - NACK transmission in case of parity error according
01743    *   to hsmartcard->Init.NACKEnable
01744    * - autoretry counter according to hsmartcard->Init.AutoRetryCount
01745    * - set TXFTCFG bit according to hsmartcard->Init.TXFIFOThreshold value
01746    * - set RXFTCFG bit according to hsmartcard->Init.RXFIFOThreshold value   */
01747   tmpreg =  (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
01748   tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS);
01749   tmpreg |= ((uint32_t)hsmartcard->Init.TXFIFOThreshold | (uint32_t)hsmartcard->Init.RXFIFOThreshold );
01750   MODIFY_REG(hsmartcard->Instance-> CR3,USART_CR3_FIELDS, tmpreg);
01751
01752   /*-------------------------- USART GTPR Configuration ----------------------*/
01753   tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS));
01754   MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg);
01755
01756   /*-------------------------- USART RTOR Configuration ----------------------*/
01757   tmpreg =   ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);
01758   if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
01759   {
01760     assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
01761     tmpreg |=  (uint32_t) hsmartcard->Init.TimeOutValue;
01762   }
01763   MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg);
01764
01765   /*-------------------------- USART BRR Configuration -----------------------*/
01766   SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
01767   switch (clocksource)
01768   {
01769     case SMARTCARD_CLOCKSOURCE_D2PCLK1:
01770       hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
01771       break;
01772     case SMARTCARD_CLOCKSOURCE_D2PCLK2:
01773       hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
01774       break;
01775     case SMARTCARD_CLOCKSOURCE_PLL2Q:
01776       HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
01777       hsmartcard->Instance->BRR = (uint16_t)((pll2_clocks.PLL2_Q_Frequency + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
01778       break;
01779     case SMARTCARD_CLOCKSOURCE_PLL3Q:
01780       HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
01781       hsmartcard->Instance->BRR = (uint16_t)((pll3_clocks.PLL3_Q_Frequency + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
01782       break;
01783     case SMARTCARD_CLOCKSOURCE_HSI:
01784       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
01785       {
01786         hsmartcard->Instance->BRR = (uint16_t)(((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)) + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
01787       }
01788       else
01789       {
01790         hsmartcard->Instance->BRR = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
01791       }
01792       break;
01793     case SMARTCARD_CLOCKSOURCE_CSI:
01794       hsmartcard->Instance->BRR = (uint16_t)((CSI_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
01795       break;
01796     case SMARTCARD_CLOCKSOURCE_LSE:
01797       hsmartcard->Instance->BRR = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
01798       break;
01799     case SMARTCARD_CLOCKSOURCE_UNDEFINED:
01800     default:
01801       ret = HAL_ERROR;
01802       break;
01803   }
01804
01805   return ret;
01806 }
01807
01808
01809 /**
01810   * @brief Configure the SMARTCARD associated USART peripheral advanced features.
01811   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
01812   *                    the configuration information for the specified SMARTCARD module.
01813   * @retval None
01814   */
01815 static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
01816 {
01817   /* Check whether the set of advanced features to configure is properly set */
01818   assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
01819
01820   /* if required, configure TX pin active level inversion */
01821   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
01822   {
01823     assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
01824     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
01825   }
01826
01827   /* if required, configure RX pin active level inversion */
01828   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
01829   {
01830     assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
01831     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
01832   }
01833
01834   /* if required, configure data inversion */
01835   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
01836   {
01837     assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
01838     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
01839   }
01840
01841   /* if required, configure RX/TX pins swap */
01842   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
01843   {
01844     assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
01845     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
01846   }
01847
01848   /* if required, configure RX overrun detection disabling */
01849   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
01850   {
01851     assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
01852     MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
01853   }
01854
01855   /* if required, configure DMA disabling on reception error */
01856   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
01857   {
01858     assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
01859     MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
01860   }
01861
01862   /* if required, configure MSB first on communication line */
01863   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
01864   {
01865     assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
01866     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
01867   }
01868
01869 }
01870
01871 /**
01872   * @brief Check the SMARTCARD Idle State.
01873   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
01874   *                    the configuration information for the specified SMARTCARD module.
01875   * @retval HAL status
01876   */
01877 static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
01878 {
01879   uint32_t tickstart = 0;
01880
01881   /* Initialize the SMARTCARD ErrorCode */
01882   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01883
01884   /* Init tickstart for timeout managment*/
01885   tickstart = HAL_GetTick();
01886
01887   /* Check if the Transmitter is enabled */
01888   if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
01889   {
01890     /* Wait until TEACK flag is set */
01891     if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
01892     {
01893       /* Timeout occurred */
01894       return HAL_TIMEOUT;
01895     }
01896   }
01897   /* Check if the Receiver is enabled */
01898   if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
01899   {
01900     /* Wait until REACK flag is set */
01901     if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
01902     {
01903       /* Timeout occurred */
01904       return HAL_TIMEOUT;
01905     }
01906   }
01907
01908   /* Initialize the SMARTCARD states */
01909   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
01910   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01911
01912   /* Process Unlocked */
01913   __HAL_UNLOCK(hsmartcard);
01914
01915   return HAL_OK;
01916 }
01917
01918 /**
01919   * @brief  Handle SMARTCARD Communication Timeout.
01920   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01921   *                    the configuration information for the specified SMARTCARD module.
01922   * @param  Flag Specifies the SMARTCARD flag to check.
01923   * @param  Status The new Flag status (SET or RESET).
01924   * @param  Tickstart Tick start value
01925   * @param  Timeout Timeout duration.
01926   * @retval HAL status
01927   */
01928 static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
01929 {
01930   /* Wait until flag is set */
01931   while((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
01932   {
01933     /* Check for the Timeout */
01934     if(Timeout != HAL_MAX_DELAY)
01935     {
01936       if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
01937       {
01938         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01939         CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
01940         CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01941
01942         hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
01943         hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01944
01945         /* Process Unlocked */
01946         __HAL_UNLOCK(hsmartcard);
01947         return HAL_TIMEOUT;
01948       }
01949     }
01950   }
01951   return HAL_OK;
01952 }
01953
01954
01955 /**
01956   * @brief  End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
01957   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01958   *               the configuration information for the specified SMARTCARD module.
01959   * @retval None
01960   */
01961 static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
01962 {
01963   /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */
01964   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
01965   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01966
01967   /* At end of Tx process, restore hsmartcard->gState to Ready */
01968   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01969 }
01970
01971
01972 /**
01973   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
01974   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01975   *               the configuration information for the specified SMARTCARD module.
01976   * @retval None
01977   */
01978 static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
01979 {
01980   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01981   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01982   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01983
01984   /* At end of Rx process, restore hsmartcard->RxState to Ready */
01985   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01986 }
01987
01988
01989 /**
01990   * @brief  DMA SMARTCARD transmit process complete callback.
01991   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
01992   *              the configuration information for the specified DMA module.
01993   * @retval None
01994   */
01995 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01996 {
01997   SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
01998   hsmartcard->TxXferCount = 0;
01999
02000   /* Disable the DMA transfer for transmit request by resetting the DMAT bit
02001   in the SMARTCARD associated USART CR3 register */
02002   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
02003
02004   /* Enable the SMARTCARD Transmit Complete Interrupt */
02005   __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
02006 }
02007
02008 /**
02009   * @brief  DMA SMARTCARD receive process complete callback.
02010   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02011   *              the configuration information for the specified DMA module.
02012   * @retval None
02013   */
02014 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
02015 {
02016   SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
02017   hsmartcard->RxXferCount = 0;
02018
02019   /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
02020   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
02021   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02022
02023   /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
02024      in the SMARTCARD associated USART CR3 register */
02025   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
02026
02027   /* At end of Rx process, restore hsmartcard->RxState to Ready */
02028   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02029
02030   HAL_SMARTCARD_RxCpltCallback(hsmartcard);
02031 }
02032
02033 /**
02034   * @brief  DMA SMARTCARD communication error callback.
02035   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02036   *              the configuration information for the specified DMA module.
02037   * @retval None
02038   */
02039 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
02040 {
02041   SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
02042
02043   /* Stop SMARTCARD DMA Tx request if ongoing */
02044   if (  (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
02045       &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) )
02046   {
02047     hsmartcard->TxXferCount = 0;
02048     SMARTCARD_EndTxTransfer(hsmartcard);
02049   }
02050
02051   /* Stop SMARTCARD DMA Rx request if ongoing */
02052   if (  (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
02053       &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) )
02054   {
02055     hsmartcard->RxXferCount = 0;
02056     SMARTCARD_EndRxTransfer(hsmartcard);
02057   }
02058
02059   hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
02060   HAL_SMARTCARD_ErrorCallback(hsmartcard);
02061 }
02062
02063 /**
02064   * @brief  DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
02065   *         (To be called at end of DMA Abort procedure following error occurrence).
02066   * @param  hdma DMA handle.
02067   * @retval None
02068   */
02069 static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02070 {
02071   SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
02072   hsmartcard->RxXferCount = 0;
02073   hsmartcard->TxXferCount = 0;
02074
02075   HAL_SMARTCARD_ErrorCallback(hsmartcard);
02076 }
02077
02078 /**
02079   * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user
02080   *         (To be called at end of DMA Tx Abort procedure following user abort request).
02081   * @note   When this callback is executed, User Abort complete call back is called only if no
02082   *         Abort still ongoing for Rx DMA Handle.
02083   * @param  hdma DMA handle.
02084   * @retval None
02085   */
02086 static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
02087 {
02088   SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
02089
02090   hsmartcard->hdmatx->XferAbortCallback = NULL;
02091
02092   /* Check if an Abort process is still ongoing */
02093   if(hsmartcard->hdmarx != NULL)
02094   {
02095     if(hsmartcard->hdmarx->XferAbortCallback != NULL)
02096     {
02097       return;
02098     }
02099   }
02100
02101   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02102   hsmartcard->TxXferCount = 0;
02103   hsmartcard->RxXferCount = 0;
02104
02105   /* Reset errorCode */
02106   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
02107
02108   /* Clear the Error flags in the ICR register */
02109   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
02110
02111   /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
02112   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
02113   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02114
02115   /* Call user Abort complete callback */
02116   HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
02117 }
02118
02119
02120 /**
02121   * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user
02122   *         (To be called at end of DMA Rx Abort procedure following user abort request).
02123   * @note   When this callback is executed, User Abort complete call back is called only if no
02124   *         Abort still ongoing for Tx DMA Handle.
02125   * @param  hdma DMA handle.
02126   * @retval None
02127   */
02128 static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
02129 {
02130   SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
02131
02132   hsmartcard->hdmarx->XferAbortCallback = NULL;
02133
02134   /* Check if an Abort process is still ongoing */
02135   if(hsmartcard->hdmatx != NULL)
02136   {
02137     if(hsmartcard->hdmatx->XferAbortCallback != NULL)
02138     {
02139       return;
02140     }
02141   }
02142
02143   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02144   hsmartcard->TxXferCount = 0;
02145   hsmartcard->RxXferCount = 0;
02146
02147   /* Reset errorCode */
02148   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
02149
02150   /* Clear the Error flags in the ICR register */
02151   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
02152
02153   /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
02154   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
02155   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02156
02157   /* Call user Abort complete callback */
02158   HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
02159 }
02160
02161
02162 /**
02163   * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
02164   *         HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
02165   *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
02166   *         and leads to user Tx Abort Complete callback execution).
02167   * @param  hdma DMA handle.
02168   * @retval None
02169   */
02170 static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02171 {
02172   SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
02173
02174   hsmartcard->TxXferCount = 0;
02175
02176   /* Clear the Error flags in the ICR register */
02177   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
02178
02179   /* Restore hsmartcard->gState to Ready */
02180   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
02181
02182   /* Call user Abort complete callback */
02183   HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
02184 }
02185
02186 /**
02187   * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
02188   *         HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
02189   *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
02190   *         and leads to user Rx Abort Complete callback execution).
02191   * @param  hdma DMA handle.
02192   * @retval None
02193   */
02194 static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02195 {
02196   SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )(hdma->Parent);
02197
02198   hsmartcard->RxXferCount = 0;
02199
02200   /* Clear the Error flags in the ICR register */
02201   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
02202
02203   /* Restore hsmartcard->RxState to Ready */
02204   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02205
02206   /* Call user Abort complete callback */
02207   HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
02208 }
02209
02210 /**
02211   * @brief Send an amount of data in non-blocking mode.
02212   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
02213   *                the configuration information for the specified SMARTCARD module.
02214   *         Function called under interruption only, once
02215   *         interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
02216   * @retval HAL status
02217   */
02218 static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
02219 {
02220   /* Check that a Tx process is ongoing */
02221   if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
02222   {
02223     if(hsmartcard->TxXferCount == 0)
02224     {
02225       /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
02226       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
02227
02228       /* Enable the SMARTCARD Transmit Complete Interrupt */
02229       __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
02230
02231       return HAL_OK;
02232     }
02233     else
02234     {
02235       hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF);
02236       hsmartcard->TxXferCount--;
02237
02238       return HAL_OK;
02239     }
02240   }
02241   else
02242   {
02243     return HAL_BUSY;
02244   }
02245 }
02246
02247 /**
02248   * @brief  Wrap up transmission in non-blocking mode.
02249   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02250   *                    the configuration information for the specified SMARTCARD module.
02251   * @retval HAL status
02252   */
02253 static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
02254 {
02255   /* Disable the SMARTCARD Transmit Complete Interrupt */
02256   __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
02257
02258   /* Check if a receive process is ongoing or not. If not disable ERR IT */
02259   if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
02260   {
02261     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
02262     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02263   }
02264
02265   /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
02266   if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
02267   {
02268     /* Disable the Peripheral first to update modes */
02269     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
02270     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
02271     /* Enable the Peripheral */
02272     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
02273   }
02274
02275   /* Tx process is ended, restore hsmartcard->gState to Ready */
02276   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
02277
02278   HAL_SMARTCARD_TxCpltCallback(hsmartcard);
02279
02280   return HAL_OK;
02281 }
02282
02283 /**
02284   * @brief Receive an amount of data in non-blocking mode.
02285   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
02286   *                the configuration information for the specified SMARTCARD module.
02287   *         Function called under interruption only, once
02288   *         interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
02289   * @retval HAL status
02290   */
02291 static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
02292 {
02293   /* Check that a Rx process is ongoing */
02294   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
02295   {
02296     *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
02297
02298     if(--hsmartcard->RxXferCount == 0)
02299     {
02300       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE);
02301
02302       /* Check if a transmit process is ongoing or not. If not disable ERR IT */
02303       if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
02304       {
02305         /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
02306         CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02307       }
02308
02309       /* Disable the SMARTCARD Parity Error Interrupt */
02310       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
02311
02312       hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02313
02314       HAL_SMARTCARD_RxCpltCallback(hsmartcard);
02315
02316       return HAL_OK;
02317     }
02318
02319     return HAL_OK;
02320   }
02321   else
02322   {
02323     /* Clear RXNE interrupt flag */
02324     __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
02325
02326     return HAL_BUSY;
02327   }
02328 }
02329
02330 /**
02331   * @}
02332   */
02333
02334 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
02335 /**
02336   * @}
02337   */
02338
02339 /**
02340   * @}
02341   */
02342
02343 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_smartcard.h Source File

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stm32h7xx_hal_smartcard.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_smartcard.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of SMARTCARD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_SMARTCARD_H
00040 #define __STM32H7xx_HAL_SMARTCARD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SMARTCARD
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief SMARTCARD Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t BaudRate;                  /*!< Configures the SmartCard communication baud rate.
00068                                            The baud rate register is computed using the following formula:
00069                                               Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */
00070
00071   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00072                                            This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
00073
00074   uint32_t StopBits;                  /*!< Specifies the number of stop bits.
00075                                            This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
00076
00077   uint16_t Parity;                    /*!< Specifies the parity mode.
00078                                            This parameter can be a value of @ref SMARTCARD_Parity
00079                                            @note The parity is enabled by default (PCE is forced to 1).
00080                                                  Since the WordLength is forced to 8 bits + parity, M is
00081                                                  forced to 1 and the parity bit is the 9th bit. */
00082
00083   uint16_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00084                                            This parameter can be a value of @ref SMARTCARD_Mode */
00085
00086   uint16_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
00087                                            This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
00088
00089   uint16_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
00090                                            This parameter can be a value of @ref SMARTCARD_Clock_Phase */
00091
00092   uint16_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
00093                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00094                                            This parameter can be a value of @ref SMARTCARD_Last_Bit */
00095
00096   uint16_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.
00097                                            Selecting the single sample method increases the receiver tolerance to clock
00098                                            deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
00099
00100   uint8_t  Prescaler;                 /*!< Specifies the SmartCard Prescaler. */
00101
00102   uint8_t  GuardTime;                 /*!< Specifies the SmartCard Guard Time applied after stop bits. */
00103
00104   uint16_t NACKEnable;                /*!< Specifies whether the SmartCard NACK transmission is enabled
00105                                            in case of parity error.
00106                                            This parameter can be a value of @ref SMARTCARD_NACK_Enable */
00107
00108   uint32_t TimeOutEnable;             /*!< Specifies whether the receiver timeout is enabled.
00109                                             This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
00110
00111   uint32_t TimeOutValue;              /*!< Specifies the receiver time out value in number of baud blocks:
00112                                            it is used to implement the Character Wait Time (CWT) and
00113                                            Block Wait Time (BWT). It is coded over 24 bits. */
00114
00115   uint8_t BlockLength;                /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
00116                                            This parameter can be any value from 0x0 to 0xFF */
00117
00118   uint8_t AutoRetryCount;             /*!< Specifies the SmartCard auto-retry count (number of retries in
00119                                             receive and transmit mode). When set to 0, retransmission is
00120                                             disabled. Otherwise, its maximum value is 7 (before signalling
00121                                             an error) */
00122
00123   uint32_t FIFOMode;                  /*!< Specifies if the FIFO mode will be used. This parameter can be a value
00124                                            of @ref SMARTCARD_FIFO_mode */
00125
00126   uint32_t TXFIFOThreshold;           /*!< Specifies the TXFIFO threshold level.
00127                                            This parameter can be a value of @ref SMARTCARD_TXFIFO_threshold_level */
00128
00129   uint32_t RXFIFOThreshold;           /*!< Specifies the RXFIFO threshold level.
00130                                            This parameter can be a value of @ref SMARTCARD_RXFIFO_threshold_level */
00131
00132 }SMARTCARD_InitTypeDef;
00133
00134 /**
00135   * @brief  SMARTCARD advanced features initalization structure definition
00136   */
00137 typedef struct
00138 {
00139   uint32_t AdvFeatureInit;            /*!< Specifies which advanced SMARTCARD features is initialized. Several
00140                                            advanced features may be initialized at the same time. This parameter
00141                                            can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */
00142
00143   uint32_t TxPinLevelInvert;          /*!< Specifies whether the TX pin active level is inverted.
00144                                            This parameter can be a value of @ref SMARTCARD_Tx_Inv  */
00145
00146   uint32_t RxPinLevelInvert;          /*!< Specifies whether the RX pin active level is inverted.
00147                                            This parameter can be a value of @ref SMARTCARD_Rx_Inv  */
00148
00149   uint32_t DataInvert;                /*!< Specifies whether data are inverted (positive/direct logic
00150                                            vs negative/inverted logic).
00151                                            This parameter can be a value of @ref SMARTCARD_Data_Inv */
00152
00153   uint32_t Swap;                      /*!< Specifies whether TX and RX pins are swapped.
00154                                            This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
00155
00156   uint32_t OverrunDisable;            /*!< Specifies whether the reception overrun detection is disabled.
00157                                            This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
00158
00159   uint32_t DMADisableonRxError;       /*!< Specifies whether the DMA is disabled in case of reception error.
00160                                            This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
00161
00162   uint32_t MSBFirst;                  /*!< Specifies whether MSB is sent first on UART line.
00163                                            This parameter can be a value of @ref SMARTCARD_MSB_First */
00164
00165   uint16_t TxCompletionIndication;     /*!< Specifies which transmission completion indication is used: before (when
00166                                             relevant flag is available) or once guard time period has elapsed.
00167                                            This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */
00168 }SMARTCARD_AdvFeatureInitTypeDef;
00169
00170 /**
00171   * @brief HAL SMARTCARD State structures definition
00172   * @note  HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
00173   *        - gState contains SMARTCARD state information related to global Handle management
00174   *          and also information related to Tx operations.
00175   *          gState value coding follow below described bitmap :
00176   *          b7-b6  Error information
00177   *             00 : No Error
00178   *             01 : (Not Used)
00179   *             10 : Timeout
00180   *             11 : Error
00181   *          b5     IP initilisation status
00182   *             0  : Reset (IP not initialized)
00183   *             1  : Init done (IP not initialized. HAL SMARTCARD Init function already called)
00184   *          b4-b3  (not used)
00185   *             xx : Should be set to 00
00186   *          b2     Intrinsic process state
00187   *             0  : Ready
00188   *             1  : Busy (IP busy with some configuration or internal operations)
00189   *          b1     (not used)
00190   *             x  : Should be set to 0
00191   *          b0     Tx state
00192   *             0  : Ready (no Tx operation ongoing)
00193   *             1  : Busy (Tx operation ongoing)
00194   *        - RxState contains information related to Rx operations.
00195   *          RxState value coding follow below described bitmap :
00196   *          b7-b6  (not used)
00197   *             xx : Should be set to 00
00198   *          b5     IP initilisation status
00199   *             0  : Reset (IP not initialized)
00200   *             1  : Init done (IP not initialized)
00201   *          b4-b2  (not used)
00202   *            xxx : Should be set to 000
00203   *          b1     Rx state
00204   *             0  : Ready (no Rx operation ongoing)
00205   *             1  : Busy (Rx operation ongoing)
00206   *          b0     (not used)
00207   *             x  : Should be set to 0.
00208   */
00209 typedef enum
00210 {
00211   HAL_SMARTCARD_STATE_RESET             = 0x00U,   /*!< Peripheral is not initialized
00212                                                         Value is allowed for gState and RxState */
00213   HAL_SMARTCARD_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use
00214                                                         Value is allowed for gState and RxState */
00215   HAL_SMARTCARD_STATE_BUSY              = 0x24U,   /*!< an internal process is ongoing
00216                                                         Value is allowed for gState only */
00217   HAL_SMARTCARD_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing
00218                                                         Value is allowed for gState only */
00219   HAL_SMARTCARD_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing
00220                                                         Value is allowed for RxState only */
00221   HAL_SMARTCARD_STATE_BUSY_TX_RX        = 0x23U,   /*!< Data Transmission and Reception process is ongoing
00222                                                         Not to be used for neither gState nor RxState.
00223                                                         Value is result of combination (Or) between gState and RxState values */
00224   HAL_SMARTCARD_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state
00225                                                         Value is allowed for gState only */
00226   HAL_SMARTCARD_STATE_ERROR             = 0xE0U    /*!< Error
00227                                                         Value is allowed for gState only */
00228 }HAL_SMARTCARD_StateTypeDef;
00229
00230 /**
00231   * @brief  HAL SMARTCARD Error Code structure definition
00232   */
00233 typedef enum
00234 {
00235   HAL_SMARTCARD_ERROR_NONE      = 0x00,    /*!< No error                */
00236   HAL_SMARTCARD_ERROR_PE        = 0x01,    /*!< Parity error            */
00237   HAL_SMARTCARD_ERROR_NE        = 0x02,    /*!< Noise error             */
00238   HAL_SMARTCARD_ERROR_FE        = 0x04,    /*!< frame error             */
00239   HAL_SMARTCARD_ERROR_ORE       = 0x08,    /*!< Overrun error           */
00240   HAL_SMARTCARD_ERROR_DMA       = 0x10,    /*!< DMA transfer error      */
00241   HAL_SMARTCARD_ERROR_UDR       = 0x11,    /*!< SPI UnderRun error      */
00242   HAL_SMARTCARD_ERROR_RTO       = 0x20     /*!< Receiver TimeOut error  */
00243 }HAL_SMARTCARD_ErrorTypeDef;
00244
00245 /**
00246   * @brief  SMARTCARD handle Structure definition
00247   */
00248 typedef struct
00249 {
00250   USART_TypeDef                   *Instance;        /*!< USART registers base address                          */
00251
00252   SMARTCARD_InitTypeDef           Init;             /*!< SmartCard communication parameters                    */
00253
00254   SMARTCARD_AdvFeatureInitTypeDef AdvancedInit;     /*!< SmartCard advanced features initialization parameters */
00255
00256   uint8_t                         *pTxBuffPtr;      /*!< Pointer to SmartCard Tx transfer Buffer               */
00257
00258   uint16_t                        TxXferSize;       /*!< SmartCard Tx Transfer size                            */
00259
00260   __IO uint16_t                   TxXferCount;      /*!< SmartCard Tx Transfer Counter                         */
00261
00262   uint8_t                         *pRxBuffPtr;      /*!< Pointer to SmartCard Rx transfer Buffer               */
00263
00264   uint16_t                        RxXferSize;       /*!< SmartCard Rx Transfer size                            */
00265
00266   __IO uint16_t                   RxXferCount;      /*!< SmartCard Rx Transfer Counter                         */
00267
00268   DMA_HandleTypeDef               *hdmatx;          /*!< SmartCard Tx DMA Handle parameters                    */
00269
00270   DMA_HandleTypeDef               *hdmarx;          /*!< SmartCard Rx DMA Handle parameters                    */
00271
00272   HAL_LockTypeDef                 Lock;             /*!< Locking object                                        */
00273
00274   __IO HAL_SMARTCARD_StateTypeDef    gState;        /*!< SmartCard state information related to global Handle management
00275                                                          and also related to Tx operations.
00276                                                          This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
00277
00278   __IO HAL_SMARTCARD_StateTypeDef    RxState;       /*!< SmartCard state information related to Rx operations.
00279                                                          This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
00280
00281   uint32_t                        ErrorCode;        /*!< SmartCard Error code                                  */
00282
00283 }SMARTCARD_HandleTypeDef;
00284
00285 /**
00286   * @brief  SMARTCARD clock sources
00287   */
00288 typedef enum
00289 {
00290   SMARTCARD_CLOCKSOURCE_D2PCLK1    = 0x00,    /*!< Domain2 PCLK1 clock source */
00291   SMARTCARD_CLOCKSOURCE_D2PCLK2    = 0x01,    /*!< Domain2 PCLK2 clock source */
00292   SMARTCARD_CLOCKSOURCE_D3PCLK1    = 0x02,    /*!< Domain3 PCLK1 clock source */
00293   SMARTCARD_CLOCKSOURCE_PLL2Q      = 0x04,    /*!< PLL2Q clock source         */
00294   SMARTCARD_CLOCKSOURCE_HSI        = 0x08,    /*!< HSI clock source           */
00295   SMARTCARD_CLOCKSOURCE_CSI        = 0x10,    /*!< CSI clock source           */
00296   SMARTCARD_CLOCKSOURCE_LSE        = 0x20,    /*!< LSE clock source           */
00297   SMARTCARD_CLOCKSOURCE_PLL3Q      = 0x40,    /*!< PCLK2 clock source         */
00298   SMARTCARD_CLOCKSOURCE_UNDEFINED  = 0x80     /*!< Undefined clock source     */
00299 }SMARTCARD_ClockSourceTypeDef;
00300
00301 /**
00302   * @}
00303   */
00304
00305 /* Exported constants --------------------------------------------------------*/
00306 /** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported Constants
00307   * @{
00308   */
00309
00310 /** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
00311   * @{
00312   */
00313 #define SMARTCARD_WORDLENGTH_9B             ((uint32_t)USART_CR1_M0)              /*!< SMARTCARD frame length */
00314 /**
00315   * @}
00316   */
00317
00318 /** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
00319   * @{
00320   */
00321 #define SMARTCARD_STOPBITS_0_5              ((uint32_t)USART_CR2_STOP_0)                      /*!< SMARTCARD frame with 0.5 stop bit  */
00322 #define SMARTCARD_STOPBITS_1_5              ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< SMARTCARD frame with 1.5 stop bits */
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup SMARTCARD_Parity SMARTCARD Parity
00328   * @{
00329   */
00330 #define SMARTCARD_PARITY_EVEN               ((uint32_t)USART_CR1_PCE)                  /*!< SMARTCARD frame even parity */
00331 #define SMARTCARD_PARITY_ODD                ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< SMARTCARD frame odd parity  */
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
00337   * @{
00338   */
00339 #define SMARTCARD_MODE_RX                   ((uint32_t)USART_CR1_RE)                  /*!< SMARTCARD RX mode        */
00340 #define SMARTCARD_MODE_TX                   ((uint32_t)USART_CR1_TE)                  /*!< SMARTCARD TX mode        */
00341 #define SMARTCARD_MODE_TX_RX                ((uint32_t)(USART_CR1_TE |USART_CR1_RE))  /*!< SMARTCARD RX and TX mode */
00342 /**
00343   * @}
00344   */
00345
00346 /** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
00347   * @{
00348   */
00349 #define SMARTCARD_POLARITY_LOW              ((uint32_t)0x00000000)                   /*!< SMARTCARD frame low polarity  */
00350 #define SMARTCARD_POLARITY_HIGH             ((uint32_t)USART_CR2_CPOL)               /*!< SMARTCARD frame high polarity */
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
00356   * @{
00357   */
00358 #define SMARTCARD_PHASE_1EDGE               ((uint32_t)0x00000000)                  /*!< SMARTCARD frame phase on first clock transition  */
00359 #define SMARTCARD_PHASE_2EDGE               ((uint32_t)USART_CR2_CPHA)              /*!< SMARTCARD frame phase on second clock transition */
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
00365   * @{
00366   */
00367 #define SMARTCARD_LASTBIT_DISABLE           ((uint32_t)0x00000000)                 /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
00368 #define SMARTCARD_LASTBIT_ENABLE            ((uint32_t)USART_CR2_LBCL)             /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin     */
00369 /**
00370   * @}
00371   */
00372
00373 /** @defgroup SMARTCARD_FIFO_mode SMARTCARD FIFO  mode
00374   * @brief    SMARTCARD FIFO  mode
00375   * @{
00376   */
00377 #define SMARTCARD_FIFOMODE_DISABLE        ((uint32_t)0x00000000)        /*!< FIFO mode disable */
00378 #define SMARTCARD_FIFOMODE_ENABLE         ((uint32_t)USART_CR1_FIFOEN)  /*!< FIFO mode enable  */
00379 /**
00380   * @}
00381   */
00382
00383 /** @defgroup SMARTCARD_TXFIFO_threshold_level SMARTCARD TXFIFO threshold level
00384   * @brief    SMARTCARD TXFIFO level
00385   * @{
00386   */
00387 #define SMARTCARD_TXFIFO_THRESHOLD_1_8    ((uint32_t)0x00000000)                                /*!< TXFIFO threshold 1 eighth full configuration  */
00388 #define SMARTCARD_TXFIFO_THRESHOLD_1_4    ((uint32_t)USART_CR3_TXFTCFG_0)                       /*!< TXFIFO threshold 1 quart full configuration   */
00389 #define SMARTCARD_TXFIFO_THRESHOLD_1_2    ((uint32_t)USART_CR3_TXFTCFG_1)                       /*!< TXFIFO threshold half full configuration      */
00390 #define SMARTCARD_TXFIFO_THRESHOLD_3_4    ((uint32_t)(USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)) /*!< TXFIFO threshold 3 quarts full configuration  */
00391 #define SMARTCARD_TXFIFO_THRESHOLD_7_8    ((uint32_t)USART_CR3_TXFTCFG_2)                       /*!< TXFIFO threshold 7 eighth full configuration  */
00392 #define SMARTCARD_TXFIFO_THRESHOLD_8_8    ((uint32_t)(USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)) /*!< TXFIFO becomes empty                          */
00393 /**
00394   * @}
00395   */
00396
00397 /** @defgroup SMARTCARD_RXFIFO_threshold_level SMARTCARD RXFIFO threshold level
00398   * @brief    SMARTCARD RXFIFO level
00399   * @{
00400   */
00401 #define SMARTCARD_RXFIFO_THRESHOLD_1_8    ((uint32_t)0x00000000)                              /*!< RXFIFO threshold 1 eighth full configuration   */
00402 #define SMARTCARD_RXFIFO_THRESHOLD_1_4    ((uint32_t)USART_CR3_RXFTCFG_0)                     /*!< RXFIFO threshold 1 quart full configuration    */
00403 #define SMARTCARD_RXFIFO_THRESHOLD_1_2    ((uint32_t)USART_CR3_RXFTCFG_1)                     /*!< RXFIFO threshold half full configuration       */
00404 #define SMARTCARD_RXFIFO_THRESHOLD_3_4    ((uint32_t)(USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)) /*!< RXFIFO threshold 3 quarts full configuration */
00405 #define SMARTCARD_RXFIFO_THRESHOLD_7_8    ((uint32_t)USART_CR3_RXFTCFG_2)                     /*!< RXFIFO threshold 7 eighth full configuration   */
00406 #define SMARTCARD_RXFIFO_THRESHOLD_8_8    ((uint32_t)(USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)) /*!< RXFIFO becomes Full                          */
00407 /**
00408   * @}
00409   */
00410
00411 /** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
00412   * @{
00413   */
00414 #define SMARTCARD_ONE_BIT_SAMPLE_DISABLE    ((uint32_t)0x00000000)                 /*!< SMARTCARD frame one-bit sample disabled */
00415 #define SMARTCARD_ONE_BIT_SAMPLE_ENABLE     ((uint32_t)USART_CR3_ONEBIT)           /*!< SMARTCARD frame one-bit sample enabled  */
00416 /**
00417   * @}
00418   */
00419
00420
00421 /** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
00422   * @{
00423   */
00424 #define SMARTCARD_NACK_ENABLE               ((uint32_t)USART_CR3_NACK)            /*!< SMARTCARD NACK transmission disabled */
00425 #define SMARTCARD_NACK_DISABLE              ((uint32_t)0x00000000)                /*!< SMARTCARD NACK transmission enabled  */
00426 /**
00427   * @}
00428   */
00429
00430 /** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
00431   * @{
00432   */
00433 #define SMARTCARD_TIMEOUT_DISABLE           ((uint32_t)0x00000000)                /*!< SMARTCARD receiver timeout disabled */
00434 #define SMARTCARD_TIMEOUT_ENABLE            ((uint32_t)USART_CR2_RTOEN)           /*!< SMARTCARD receiver timeout enabled  */
00435 /**
00436   * @}
00437   */
00438
00439 /** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
00440   * @{
00441   */
00442 #define SMARTCARD_ADVFEATURE_TXINV_DISABLE  ((uint32_t)0x00000000)                /*!< TX pin active level inversion disable */
00443 #define SMARTCARD_ADVFEATURE_TXINV_ENABLE   ((uint32_t)USART_CR2_TXINV)           /*!< TX pin active level inversion enable  */
00444 /**
00445   * @}
00446   */
00447
00448 /** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
00449   * @{
00450   */
00451 #define SMARTCARD_ADVFEATURE_RXINV_DISABLE  ((uint32_t)0x00000000)                /*!< RX pin active level inversion disable */
00452 #define SMARTCARD_ADVFEATURE_RXINV_ENABLE   ((uint32_t)USART_CR2_RXINV)           /*!< RX pin active level inversion enable  */
00453 /**
00454   * @}
00455   */
00456
00457 /** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
00458   * @{
00459   */
00460 #define SMARTCARD_ADVFEATURE_DATAINV_DISABLE  ((uint32_t)0x00000000)              /*!< Binary data inversion disable */
00461 #define SMARTCARD_ADVFEATURE_DATAINV_ENABLE   ((uint32_t)USART_CR2_DATAINV)       /*!< Binary data inversion enable  */
00462 /**
00463   * @}
00464   */
00465
00466 /** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
00467   * @{
00468   */
00469 #define SMARTCARD_ADVFEATURE_SWAP_DISABLE   ((uint32_t)0x00000000)                /*!< TX/RX pins swap disable */
00470 #define SMARTCARD_ADVFEATURE_SWAP_ENABLE    ((uint32_t)USART_CR2_SWAP)            /*!< TX/RX pins swap enable  */
00471 /**
00472   * @}
00473   */
00474
00475 /** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
00476   * @{
00477   */
00478 #define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE   ((uint32_t)0x00000000)              /*!< RX overrun enable  */
00479 #define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE  ((uint32_t)USART_CR3_OVRDIS)        /*!< RX overrun disable */
00480 /**
00481   * @}
00482   */
00483
00484 /** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
00485   * @{
00486   */
00487 #define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR   ((uint32_t)0x00000000)         /*!< DMA enable on Reception Error  */
00488 #define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR  ((uint32_t)USART_CR3_DDRE)     /*!< DMA disable on Reception Error */
00489 /**
00490   * @}
00491   */
00492
00493 /** @defgroup SMARTCARD_MSB_First   SMARTCARD advanced feature MSB first
00494   * @{
00495   */
00496 #define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE      ((uint32_t)0x00000000)           /*!< Most significant bit sent/received first disable */
00497 #define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE       ((uint32_t)USART_CR2_MSBFIRST)   /*!< Most significant bit sent/received first enable  */
00498 /**
00499   * @}
00500   */
00501
00502 /** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
00503   * @{
00504   */
00505 #define SMARTCARD_RXDATA_FLUSH_REQUEST      ((uint16_t)USART_RQR_RXFRQ)        /*!< Receive data flush request */
00506 #define SMARTCARD_TXDATA_FLUSH_REQUEST      ((uint16_t)USART_RQR_TXFRQ)        /*!< Transmit data flush request */
00507 /**
00508   * @}
00509   */
00510
00511 /** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register
00512   * @{
00513   */
00514 #define SMARTCARD_CR3_SCARCNT_LSB_POS       ((uint32_t) 17)   /*!< SMARTCARD auto retry counter LSB position in CR3 register */
00515 /**
00516   * @}
00517   */
00518
00519 /** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register
00520   * @{
00521   */
00522 #define SMARTCARD_GTPR_GT_LSB_POS           ((uint32_t) 8)   /*!<  SMARTCARD guard time value LSB position in GTPR register */
00523 /**
00524   * @}
00525   */
00526
00527 /** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register
00528   * @{
00529   */
00530 #define SMARTCARD_RTOR_BLEN_LSB_POS         ((uint32_t) 24)  /*!< SMARTCARD block length LSB position in RTOR register */
00531 /**
00532   * @}
00533   */
00534
00535 /** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
00536   * @{
00537   */
00538 #define SMARTCARD_IT_MASK                   ((uint16_t)0x001F)   /*!< SMARTCARD interruptions flags mask */
00539 /**
00540   * @}
00541   */
00542
00543 /**
00544   * @}
00545   */
00546
00547 /* Exported macros -----------------------------------------------------------*/
00548 /** @defgroup SMARTCARD_Exported_Macros  SMARTCARD Exported Macros
00549   * @{
00550   */
00551
00552 /** @brief  Reset SMARTCARD handle state.
00553   * @param  __HANDLE__: SMARTCARD handle.
00554   * @retval None
00555   */
00556 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
00557                                                            (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
00558                                                            (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
00559                                                           } while(0)
00560
00561 /** @brief  Flush the Smartcard Data registers.
00562   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00563   * @retval None
00564   */
00565 #define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)                                 \
00566     do{                                                                              \
00567       SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
00568       SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
00569       } while(0)
00570
00571 /** @brief  Clear the specified SMARTCARD pending flag.
00572   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00573   * @param  __FLAG__: specifies the flag to check.
00574   *          This parameter can be any combination of the following values:
00575   *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
00576   *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
00577   *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
00578   *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
00579   *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detected clear flag
00580   *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
00581   *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag
00582   *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
00583   *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
00584   * @retval None
00585   */
00586 #define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00587
00588 /** @brief  Clear the SMARTCARD PE pending flag.
00589   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00590   * @retval None
00591   */
00592 #define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
00593
00594
00595 /** @brief  Clear the SMARTCARD FE pending flag.
00596   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00597   * @retval None
00598   */
00599 #define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
00600
00601 /** @brief  Clear the SMARTCARD NE pending flag.
00602   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00603   * @retval None
00604   */
00605 #define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
00606
00607 /** @brief  Clear the SMARTCARD ORE pending flag.
00608   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00609   * @retval None
00610   */
00611 #define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
00612
00613 /** @brief  Clear the SMARTCARD IDLE pending flag.
00614   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00615   * @retval None
00616   */
00617 #define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
00618
00619 /** @brief  Check whether the specified Smartcard flag is set or not.
00620   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00621   * @param  __FLAG__: specifies the flag to check.
00622   *        This parameter can be one of the following values:
00623   *            @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag
00624   *            @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
00625   *            @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
00626   *            @arg @ref SMARTCARD_FLAG_BUSY  Busy flag
00627   *            @arg @ref SMARTCARD_FLAG_EOBF  End of block flag
00628   *            @arg @ref SMARTCARD_FLAG_RTOF  Receiver timeout flag
00629   *            @arg @ref SMARTCARD_FLAG_TXE   Transmit data register empty flag
00630   *            @arg @ref SMARTCARD_FLAG_TC    Transmission complete flag
00631   *            @arg @ref SMARTCARD_FLAG_RXNE  Receive data register not empty flag
00632   *            @arg @ref SMARTCARD_FLAG_IDLE  Idle line detection flag
00633   *            @arg @ref SMARTCARD_FLAG_ORE   Overrun error flag
00634   *            @arg @ref SMARTCARD_FLAG_NE    Noise error flag
00635   *            @arg @ref SMARTCARD_FLAG_FE    Framing error flag
00636   *            @arg @ref SMARTCARD_FLAG_PE    Parity error flag
00637   * @retval The new state of __FLAG__ (TRUE or FALSE).
00638   */
00639 #define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00640
00641
00642 /** @brief  Enable the specified SmartCard interrupt.
00643   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00644   * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
00645   *          This parameter can be one of the following values:
00646   *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
00647   *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
00648   *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
00649   *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
00650   *            @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
00651   *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
00652   *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt
00653   *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
00654   *            @arg @ref SMARTCARD_IT_ERR   Error interrupt(frame error, noise error, overrun error)
00655   * @retval None
00656   */
00657 #define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00658                                                                 ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00659                                                                 ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
00660
00661 /** @brief  Disable the specified SmartCard interrupt.
00662   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00663   * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to disable.
00664   *          This parameter can be one of the following values:
00665   *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
00666   *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
00667   *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
00668   *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
00669   *            @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
00670   *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
00671   *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt
00672   *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
00673   *            @arg @ref SMARTCARD_IT_ERR   Error interrupt(frame error, noise error, overrun error)
00674   * @retval None
00675   */
00676 #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00677                                                                 ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00678                                                                 ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
00679
00680
00681 /** @brief  Check whether the specified SmartCard interrupt has occurred or not.
00682   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00683   * @param  __IT__: specifies the SMARTCARD interrupt to check.
00684   *          This parameter can be one of the following values:
00685   *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
00686   *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
00687   *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
00688   *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
00689   *            @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
00690   *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
00691   *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt
00692   *            @arg @ref SMARTCARD_IT_ORE   Overrun error interrupt
00693   *            @arg @ref SMARTCARD_IT_NE    Noise error interrupt
00694   *            @arg @ref SMARTCARD_IT_FE    Framing error interrupt
00695   *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
00696   * @retval The new state of __IT__ (TRUE or FALSE).
00697   */
00698 #define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
00699
00700 /** @brief  Check whether the specified SmartCard interrupt source is enabled or not.
00701   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00702   * @param  __IT__: specifies the SMARTCARD interrupt source to check.
00703   *          This parameter can be one of the following values:
00704   *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
00705   *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
00706   *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
00707   *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
00708   *            @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
00709   *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
00710   *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt
00711   *            @arg @ref SMARTCARD_IT_ERR   Framing, overrun or noise error interrupt
00712   *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
00713   * @retval The new state of __IT__ (TRUE or FALSE).
00714   */
00715 #define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1 : \
00716                                                            (((((uint8_t)(__IT__)) >> 5U) == 2)? (__HANDLE__)->Instance->CR2 : \
00717                                                            (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))
00718
00719
00720 /** @brief  Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
00721   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00722   * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
00723   *                       to clear the corresponding interrupt.
00724   *          This parameter can be one of the following values:
00725   *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
00726   *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
00727   *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
00728   *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
00729   *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detection clear flag
00730   *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
00731   *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
00732   *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
00733   *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
00734   * @retval None
00735   */
00736 #define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
00737
00738 /** @brief  Clear the SMARTCARD TX FIFO empty clear flag.
00739   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00740   * @retval None
00741   */
00742 #define __HAL_SMARTCARD_CLEAR_TXFECF(__HANDLE__)   __HAL_SMARTCARD_CLEAR_IT((__HANDLE__), SMARTCARD_CLEAR_TXFECF)
00743
00744 /** @brief  Set a specific SMARTCARD request flag.
00745   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00746   * @param  __REQ__: specifies the request flag to set
00747   *          This parameter can be one of the following values:
00748   *            @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
00749   *            @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
00750   *
00751   * @retval None
00752   */
00753 #define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
00754
00755 /** @brief  Enable the SMARTCARD one bit sample method.
00756   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00757   * @retval None
00758   */
00759 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00760
00761 /** @brief  Disable the SMARTCARD one bit sample method.
00762   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00763   * @retval None
00764   */
00765 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
00766
00767 /** @brief  Enable the USART associated to the SMARTCARD Handle.
00768   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00769   * @retval None
00770   */
00771 #define __HAL_SMARTCARD_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00772
00773 /** @brief  Disable the USART associated to the SMARTCARD Handle
00774   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00775   * @retval None
00776   */
00777 #define __HAL_SMARTCARD_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00778
00779 /**
00780   * @}
00781   */
00782
00783 /* Private macros -------------------------------------------------------------*/
00784 /** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
00785   * @{
00786   */
00787
00788 /** @brief  Check the Baud rate range.
00789   * @param  __BAUDRATE__: Baudrate specified by the user.
00790   *         The maximum Baud Rate is derived from the maximum clock on H7 (i.e. 100 MHz)
00791   *         divided by the smallest oversampling used on the SMARTCARD (i.e. 8).
00792   * @retval Test result (TRUE or FALSE).
00793   */
00794 #define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
00795
00796 /** @brief  Check the block length range.
00797   * @note   The maximum SMARTCARD block length is 0xFF.
00798   * @param  __LENGTH__: block length.
00799   * @retval Test result (TRUE or FALSE)
00800   */
00801 #define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)
00802
00803 /** @brief  Check the receiver timeout value.
00804   * @note   The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
00805   * @param  __TIMEOUTVALUE__: receiver timeout value.
00806   * @retval Test result (TRUE or FALSE)
00807   */
00808 #define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__)    ((__TIMEOUTVALUE__) <= 0xFFFFFF)
00809
00810 /** @brief  Check the SMARTCARD autoretry counter value.
00811   * @note   The maximum number of retransmissions is 0x7.
00812   * @param  __COUNT__: number of retransmissions.
00813   * @retval Test result (TRUE or FALSE)
00814   */
00815 #define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__)         ((__COUNT__) <= 0x7)
00816
00817 /**
00818   * @brief Ensure that SMARTCARD frame length is valid.
00819   * @param __LENGTH__: SMARTCARD frame length.
00820   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00821   */
00822 #define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
00823
00824 /**
00825   * @brief Ensure that SMARTCARD frame number of stop bits is valid.
00826   * @param __STOPBITS__: SMARTCARD frame number of stop bits.
00827   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
00828   */
00829 #define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
00830                                              ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
00831
00832 /**
00833   * @brief Ensure that SMARTCARD frame parity is valid.
00834   * @param __PARITY__: SMARTCARD frame parity.
00835   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
00836   */
00837 #define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
00838                                          ((__PARITY__) == SMARTCARD_PARITY_ODD))
00839
00840 /**
00841   * @brief Ensure that SMARTCARD communication mode is valid.
00842   * @param __MODE__: SMARTCARD communication mode.
00843   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00844   */
00845 #define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3) == 0x00) && ((__MODE__) != (uint16_t)0x00))
00846
00847 /**
00848   * @brief Ensure that SMARTCARD frame polarity is valid.
00849   * @param __CPOL__: SMARTCARD frame polarity.
00850   * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
00851   */
00852 #define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
00853
00854 /**
00855   * @brief Ensure that SMARTCARD frame phase is valid.
00856   * @param __CPHA__: SMARTCARD frame phase.
00857   * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
00858   */
00859 #define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
00860
00861 /**
00862   * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
00863   * @param __LASTBIT__: SMARTCARD frame last bit clock pulse setting.
00864   * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
00865   */
00866 #define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
00867                                            ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
00868
00869 /**
00870   * @brief Ensure that SMARTCARD frame sampling is valid.
00871   * @param __ONEBIT__: SMARTCARD frame sampling.
00872   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
00873   */
00874 #define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
00875                                                  ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
00876
00877 /**
00878   * @brief Ensure that SMARTCARD NACK transmission setting is valid.
00879   * @param __NACK__: SMARTCARD NACK transmission setting.
00880   * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
00881   */
00882 #define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
00883                                      ((__NACK__) == SMARTCARD_NACK_DISABLE))
00884
00885 /**
00886   * @brief Ensure that SMARTCARD receiver timeout setting is valid.
00887   * @param __TIMEOUT__: SMARTCARD receiver timeout setting.
00888   * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
00889   */
00890 #define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
00891                                            ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
00892
00893 /**
00894   * @brief Ensure that SMARTCARD advanced features initialization is valid.
00895   * @param __INIT__: SMARTCARD advanced features initialization.
00896   * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
00897   */
00898 #define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \
00899                                                                SMARTCARD_ADVFEATURE_TXINVERT_INIT          | \
00900                                                                SMARTCARD_ADVFEATURE_RXINVERT_INIT          | \
00901                                                                SMARTCARD_ADVFEATURE_DATAINVERT_INIT        | \
00902                                                                SMARTCARD_ADVFEATURE_SWAP_INIT              | \
00903                                                                SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
00904                                                                SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
00905                                                                SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
00906
00907 /**
00908   * @brief Ensure that SMARTCARD frame TX inversion setting is valid.
00909   * @param __TXINV__: SMARTCARD frame TX inversion setting.
00910   * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
00911   */
00912 #define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
00913                                                   ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
00914
00915 /**
00916   * @brief Ensure that SMARTCARD frame RX inversion setting is valid.
00917   * @param __RXINV__: SMARTCARD frame RX inversion setting.
00918   * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
00919   */
00920 #define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
00921                                                   ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
00922
00923 /**
00924   * @brief Ensure that SMARTCARD frame data inversion setting is valid.
00925   * @param __DATAINV__: SMARTCARD frame data inversion setting.
00926   * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
00927   */
00928 #define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
00929                                                       ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
00930
00931 /**
00932   * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
00933   * @param __SWAP__: SMARTCARD frame RX/TX pins swap setting.
00934   * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
00935   */
00936 #define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
00937                                                 ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
00938
00939 /**
00940   * @brief Ensure that SMARTCARD frame overrun setting is valid.
00941   * @param __OVERRUN__: SMARTCARD frame overrun setting.
00942   * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
00943   */
00944 #define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
00945                                            ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
00946
00947 /**
00948   * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
00949   * @param __DMA__: SMARTCARD DMA enabling or disabling on error setting.
00950   * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
00951   */
00952 #define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
00953                                                        ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
00954
00955 /**
00956   * @brief Ensure that SMARTCARD frame MSB first setting is valid.
00957   * @param __MSBFIRST__: SMARTCARD frame MSB first setting.
00958   * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
00959   */
00960 #define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
00961                                                         ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
00962
00963 /**
00964   * @brief Ensure that SMARTCARD request parameter is valid.
00965   * @param __PARAM__: SMARTCARD request parameter.
00966   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
00967   */
00968 #define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
00969                                                    ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
00970
00971 /**
00972   * @brief Ensure that SMARTCARD FIFO mode is valid.
00973   * @param __STATE__: SMARTCARD FIFO mode.
00974   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00975   */
00976 #define IS_SMARTCARD_FIFO_MODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
00977                                                  ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))
00978
00979 /**
00980   * @brief Ensure that SMARTCARD TXFIFO threshold level is valid.
00981   * @param __THRESHOLD__: SMARTCARD TXFIFO threshold level.
00982   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00983   */
00984 #define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
00985                                                       ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
00986                                                       ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
00987                                                       ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
00988                                                       ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
00989                                                       ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))
00990
00991 /**
00992   * @brief Ensure that SMARTCARD RXFIFO threshold level is valid.
00993   * @param __THRESHOLD__: SMARTCARD RXFIFO threshold level.
00994   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00995   */
00996 #define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
00997                                                       ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
00998                                                       ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
00999                                                       ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
01000                                                       ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
01001                                                       ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))
01002
01003 /**
01004   * @}
01005   */
01006
01007 /* Include SMARTCARD HAL Extended module */
01008 #include "stm32h7xx_hal_smartcard_ex.h"
01009
01010
01011 /* Exported functions --------------------------------------------------------*/
01012 /** @addtogroup SMARTCARD_Exported_Functions
01013   * @{
01014   */
01015
01016 /* Initialization and de-initialization functions  ****************************/
01017 /** @addtogroup SMARTCARD_Exported_Functions_Group1
01018   * @{
01019   */
01020
01021 HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
01022 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
01023 void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
01024 void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
01025
01026 /**
01027   * @}
01028   */
01029
01030 /* IO operation functions *****************************************************/
01031 /** @addtogroup SMARTCARD_Exported_Functions_Group2
01032   * @{
01033   */
01034
01035 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
01036 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
01037 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
01038 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
01039 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
01040 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
01041 HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
01042 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);
01043 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);
01044 HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);
01045 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
01046 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
01047 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
01048 void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01049 void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01050 void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01051 void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
01052 void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
01053 void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
01054
01055 /**
01056   * @}
01057   */
01058
01059 /* Peripheral Control functions ***********************************************/
01060 /* Peripheral State and Error functions ***************************************/
01061 /** @addtogroup SMARTCARD_Exported_Functions_Group4
01062   * @{
01063   */
01064
01065 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
01066 uint32_t                   HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
01067
01068 /**
01069   * @}
01070   */
01071
01072 /**
01073   * @}
01074   */
01075
01076 /**
01077   * @}
01078   */
01079
01080 /**
01081   * @}
01082   */
01083
01084 #ifdef __cplusplus
01085 }
01086 #endif
01087
01088 #endif /* __STM32H7xx_HAL_SMARTCARD_H */
01089
01090 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_smartcard_ex.c Source File

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stm32h7xx_hal_smartcard_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_smartcard_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   SMARTCARD HAL module driver.
00008   *          This file provides extended firmware functions to manage the following
00009   *          functionalities of the SmartCard.
00010   *           + Initialization and de-initialization functions
00011   *           + Peripheral Control functions
00012   *
00013   *
00014   @verbatim
00015   =============================================================================
00016                ##### SMARTCARD peripheral extended features  #####
00017   =============================================================================
00018   [..]
00019   The Extended SMARTCARD HAL driver can be used as follows:
00020
00021     (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
00022         then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
00023         auto-retry counter,...) in the hsmartcard AdvancedInit structure.
00024
00025
00026
00027   @endverbatim
00028   ******************************************************************************
00029   * @attention
00030   *
00031   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00032   *
00033   * Redistribution and use in source and binary forms, with or without modification,
00034   * are permitted provided that the following conditions are met:
00035   *   1. Redistributions of source code must retain the above copyright notice,
00036   *      this list of conditions and the following disclaimer.
00037   *   2. Redistributions in binary form must reproduce the above copyright notice,
00038   *      this list of conditions and the following disclaimer in the documentation
00039   *      and/or other materials provided with the distribution.
00040   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00041   *      may be used to endorse or promote products derived from this software
00042   *      without specific prior written permission.
00043   *
00044   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00045   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00046   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00047   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00048   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00049   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00050   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00051   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00052   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00053   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00054   *
00055   ******************************************************************************
00056   */
00057
00058 /* Includes ------------------------------------------------------------------*/
00059 #include "stm32h7xx_hal.h"
00060
00061 /** @addtogroup STM32H7xx_HAL_Driver
00062   * @{
00063   */
00064
00065 /** @defgroup SMARTCARDEx SMARTCARDEx
00066   * @brief SMARTCARD Extended HAL module driver
00067   * @{
00068   */
00069 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00070
00071 /* Private typedef -----------------------------------------------------------*/
00072 /* Private define ------------------------------------------------------------*/
00073 /* Private macros ------------------------------------------------------------*/
00074 /* Private variables ---------------------------------------------------------*/
00075 /* Private function prototypes -----------------------------------------------*/
00076
00077 /* Exported functions --------------------------------------------------------*/
00078 /** @defgroup SMARTCARDEx_Exported_Functions  SMARTCARD Extended Exported Functions
00079   * @{
00080   */
00081
00082 /** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
00083   * @brief    Extended control functions
00084   *
00085 @verbatim
00086   ===============================================================================
00087                       ##### Peripheral Control functions #####
00088   ===============================================================================
00089   [..]
00090   This subsection provides a set of functions allowing to initialize the SMARTCARD.
00091      (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
00092      (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
00093      (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
00094      (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
00095
00096 @endverbatim
00097   * @{
00098   */
00099
00100 /**
00101   * @brief Update on the fly the SMARTCARD block length in RTOR register.
00102   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00103   *                    the configuration information for the specified SMARTCARD module.
00104   * @param BlockLength: SMARTCARD block length (8-bit long at most)
00105   * @retval None
00106   */
00107 void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
00108 {
00109   MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS));
00110 }
00111
00112 /**
00113   * @brief Update on the fly the receiver timeout value in RTOR register.
00114   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00115   *                    the configuration information for the specified SMARTCARD module.
00116   * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout
00117   *                     value must be less or equal to 0x0FFFFFFFF.
00118   * @retval None
00119   */
00120 void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
00121 {
00122   assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
00123   MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
00124 }
00125
00126 /**
00127   * @brief Enable the SMARTCARD receiver timeout feature.
00128   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00129   *                    the configuration information for the specified SMARTCARD module.
00130   * @retval HAL status
00131   */
00132 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
00133 {
00134
00135   if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00136   {
00137     /* Process Locked */
00138     __HAL_LOCK(hsmartcard);
00139
00140     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00141
00142     /* Set the USART RTOEN bit */
00143     SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
00144
00145     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00146
00147     /* Process Unlocked */
00148     __HAL_UNLOCK(hsmartcard);
00149
00150     return HAL_OK;
00151   }
00152   else
00153   {
00154     return HAL_BUSY;
00155   }
00156 }
00157
00158 /**
00159   * @brief Disable the SMARTCARD receiver timeout feature.
00160   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00161   *                    the configuration information for the specified SMARTCARD module.
00162   * @retval HAL status
00163   */
00164 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
00165 {
00166
00167   if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00168   {
00169     /* Process Locked */
00170     __HAL_LOCK(hsmartcard);
00171
00172     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00173
00174     /* Clear the USART RTOEN bit */
00175     CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
00176
00177     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00178
00179     /* Process Unlocked */
00180     __HAL_UNLOCK(hsmartcard);
00181
00182     return HAL_OK;
00183   }
00184   else
00185   {
00186     return HAL_BUSY;
00187   }
00188 }
00189
00190 /**
00191   * @}
00192   */
00193
00194 /**
00195   * @}
00196   */
00197
00198 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
00199
00200 /**
00201   * @}
00202   */
00203
00204 /**
00205   * @}
00206   */
00207
00208 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_smartcard_ex.h Source File

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stm32h7xx_hal_smartcard_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_smartcard_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of SMARTCARD HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_SMARTCARD_EX_H
00040 #define __STM32H7xx_HAL_SMARTCARD_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SMARTCARDEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059
00060 /** @addtogroup SMARTCARDEx_Exported_Constants  SMARTCARD Extended Exported Constants
00061   * @{
00062   */
00063
00064 /** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
00065   * @{
00066   */
00067 #define SMARTCARD_TCBGT      SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
00068 #define SMARTCARD_TC         SMARTCARD_IT_TC    /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
00069 /**
00070   * @}
00071   */
00072
00073 /** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
00074   * @{
00075   */
00076 #define SMARTCARD_ADVFEATURE_NO_INIT                 ((uint32_t)0x00000000)    /*!< No advanced feature initialization                  */
00077 #define SMARTCARD_ADVFEATURE_TXINVERT_INIT           ((uint32_t)0x00000001)    /*!< TX pin active level inversion                       */
00078 #define SMARTCARD_ADVFEATURE_RXINVERT_INIT           ((uint32_t)0x00000002)    /*!< RX pin active level inversion                       */
00079 #define SMARTCARD_ADVFEATURE_DATAINVERT_INIT         ((uint32_t)0x00000004)    /*!< Binary data inversion                               */
00080 #define SMARTCARD_ADVFEATURE_SWAP_INIT               ((uint32_t)0x00000008)    /*!< TX/RX pins swap                                     */
00081 #define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT   ((uint32_t)0x00000010)    /*!< RX overrun disable                                  */
00082 #define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT  ((uint32_t)0x00000020)    /*!< DMA disable on Reception Error                      */
00083 #define SMARTCARD_ADVFEATURE_MSBFIRST_INIT           ((uint32_t)0x00000080)    /*!< Most significant bit sent/received first            */
00084 #define SMARTCARD_ADVFEATURE_TXCOMPLETION            ((uint32_t)0x00000100)    /*!< TX completion indication before of after guard time */
00085 /**
00086   * @}
00087   */
00088
00089
00090
00091
00092 /** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
00093   *        Elements values convention: 0xXXXX
00094   *           - 0xXXXX  : Flag mask in the ISR register
00095   * @{
00096   */
00097 #define SMARTCARD_FLAG_TCBGT          USART_ISR_TCBGT      /*!< SMARTCARD transmission complete before guard time completion */
00098 #define SMARTCARD_FLAG_REACK          USART_ISR_REACK      /*!< SMARTCARD receive enable acknowledge flag  */
00099 #define SMARTCARD_FLAG_TEACK          USART_ISR_TEACK      /*!< SMARTCARD transmit enable acknowledge flag */
00100 #define SMARTCARD_FLAG_BUSY           USART_ISR_BUSY       /*!< SMARTCARD busy flag                        */
00101 #define SMARTCARD_FLAG_EOBF           USART_ISR_EOBF       /*!< SMARTCARD end of block flag                */
00102 #define SMARTCARD_FLAG_RTOF           USART_ISR_RTOF       /*!< SMARTCARD receiver timeout flag            */
00103 #define SMARTCARD_FLAG_TXE            USART_ISR_TXE        /*!< SMARTCARD transmit data register empty     */
00104 #define SMARTCARD_FLAG_TC             USART_ISR_TC         /*!< SMARTCARD transmission complete            */
00105 #define SMARTCARD_FLAG_RXNE           USART_ISR_RXNE       /*!< SMARTCARD read data register not empty     */
00106 #define SMARTCARD_FLAG_IDLE           USART_ISR_IDLE       /*!< SMARTCARD idle line detection              */
00107 #define SMARTCARD_FLAG_ORE            USART_ISR_ORE        /*!< SMARTCARD overrun error                    */
00108 #define SMARTCARD_FLAG_NE             USART_ISR_NE         /*!< SMARTCARD noise error                      */
00109 #define SMARTCARD_FLAG_FE             USART_ISR_FE         /*!< SMARTCARD frame error                      */
00110 #define SMARTCARD_FLAG_PE             USART_ISR_PE         /*!< SMARTCARD parity error                     */
00111 #define SMARTCARD_FLAG_TXFT           USART_ISR_TXFT       /*!< SMARTCARD TXFIFO threshold flag            */
00112 #define SMARTCARD_FLAG_RXFT           USART_ISR_RXFT       /*!< SMARTCARD RXFIFO threshold flag            */
00113 #define SMARTCARD_FLAG_RXFF           USART_ISR_RXFF       /*!< SMARTCARD RXFIFO Fullflag                  */
00114 #define SMARTCARD_FLAG_TXFE           USART_ISR_TXFE       /*!< SMARTCARD TXFIFO Empty flag                */
00115
00116 /**
00117   * @}
00118   */
00119
00120 /** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
00121   *        Elements values convention: 000ZZZZZ0XXYYYYYb
00122   *           - YYYYY  : Interrupt source position in the XX register (5 bits)
00123   *           - XX  : Interrupt source register (2 bits)
00124   *                 - 01: CR1 register
00125   *                 - 10: CR2 register
00126   *                 - 11: CR3 register
00127   *           - ZZZZZ  : Flag position in the ISR register(5 bits)
00128   * @{
00129   */
00130 #define SMARTCARD_IT_PE                     ((uint16_t)0x0028)        /*!< SMARTCARD parity error interruption                 */
00131 #define SMARTCARD_IT_TXE                    ((uint16_t)0x0727)        /*!< SMARTCARD transmit data register empty interruption */
00132 #define SMARTCARD_IT_TC                     ((uint16_t)0x0626)        /*!< SMARTCARD transmission complete interruption        */
00133 #define SMARTCARD_IT_RXNE                   ((uint16_t)0x0525)        /*!< SMARTCARD read data register not empty interruption */
00134 #define SMARTCARD_IT_IDLE                   ((uint16_t)0x0424)        /*!< SMARTCARD idle line detection interruption          */
00135
00136 #define SMARTCARD_IT_ERR                    ((uint16_t)0x0060)        /*!< SMARTCARD error interruption         */
00137 #define SMARTCARD_IT_ORE                    ((uint16_t)0x0300)        /*!< SMARTCARD overrun error interruption */
00138 #define SMARTCARD_IT_NE                     ((uint16_t)0x0200)        /*!< SMARTCARD noise error interruption   */
00139 #define SMARTCARD_IT_FE                     ((uint16_t)0x0100)        /*!< SMARTCARD frame error interruption   */
00140
00141 #define SMARTCARD_IT_EOB                    ((uint16_t)0x0C3B)        /*!< SMARTCARD end of block interruption     */
00142 #define SMARTCARD_IT_RTO                    ((uint16_t)0x0B3A)        /*!< SMARTCARD receiver timeout interruption */
00143
00144 #define SMARTCARD_IT_RXFF                   ((uint16_t)0x183F)
00145 #define SMARTCARD_IT_TXFE                   ((uint16_t)0x173E)
00146 #define SMARTCARD_IT_RXFT                   ((uint16_t)0x187C)
00147 #define SMARTCARD_IT_TXFT                   ((uint16_t)0x1B77)
00148 #define SMARTCARD_IT_TCBGT                  ((uint16_t)0x1978)        /*!< SMARTCARD transmission complete before guard time completion interruption */
00149 /**
00150   * @}
00151   */
00152
00153 /** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
00154   * @{
00155   */
00156 #define SMARTCARD_CLEAR_PEF                 USART_ICR_PECF    /*!< SMARTCARD parity error clear flag          */
00157 #define SMARTCARD_CLEAR_FEF                 USART_ICR_FECF    /*!< SMARTCARD framing error clear flag         */
00158 #define SMARTCARD_CLEAR_NEF                 USART_ICR_NCF     /*!< SMARTCARD noise detected clear flag        */
00159 #define SMARTCARD_CLEAR_OREF                USART_ICR_ORECF   /*!< SMARTCARD overrun error clear flag         */
00160 #define SMARTCARD_CLEAR_IDLEF               USART_ICR_IDLECF  /*!< SMARTCARD idle line detected clear flag    */
00161 #define SMARTCARD_CLEAR_TCF                 USART_ICR_TCCF    /*!< SMARTCARD transmission complete clear flag */
00162 #define SMARTCARD_CLEAR_TCBGTF              USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
00163 #define SMARTCARD_CLEAR_RTOF                USART_ICR_RTOCF   /*!< SMARTCARD receiver time out clear flag     */
00164 #define SMARTCARD_CLEAR_EOBF                USART_ICR_EOBCF   /*!< SMARTCARD end of block clear flag          */
00165 #define SMARTCARD_CLEAR_TXFECF              USART_ICR_TXFECF  /*!< SMARTCARD TXFIFO empty clear flag          */
00166 #define SMARTCARD_CLEAR_UDRCF               USART_ICR_UDRCF   /*!< SMARTCARD UnderRun Error Clear Flag        */
00167 /**
00168   * @}
00169   */
00170
00171 /**
00172   * @}
00173   */
00174 /* Exported macros -----------------------------------------------------------*/
00175 /* Private macros ------------------------------------------------------------*/
00176 /** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
00177   * @{
00178   */
00179
00180 /** @brief  Report the SMARTCARD clock source.
00181   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00182   * @param  __CLOCKSOURCE__: output variable.
00183   * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
00184   */
00185 #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00186   do {                                                         \
00187     if((__HANDLE__)->Instance == USART1)                       \
00188     {                                                          \
00189        switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00190        {                                                       \
00191         case RCC_USART1CLKSOURCE_D2PCLK2:                      \
00192           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2;       \
00193           break;                                               \
00194         case RCC_USART1CLKSOURCE_PLL2:                        \
00195           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;         \
00196           break;                                               \
00197         case RCC_USART1CLKSOURCE_PLL3:                        \
00198           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;         \
00199           break;                                               \
00200         case RCC_USART1CLKSOURCE_HSI:                          \
00201           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;           \
00202           break;                                               \
00203         case RCC_USART1CLKSOURCE_CSI:                          \
00204           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;           \
00205           break;                                               \
00206         case RCC_USART1CLKSOURCE_LSE:                          \
00207           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;           \
00208           break;                                               \
00209        }                                                       \
00210     }                                                          \
00211     else if((__HANDLE__)->Instance == USART2)                  \
00212     {                                                          \
00213        switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00214        {                                                       \
00215         case RCC_USART2CLKSOURCE_D2PCLK1:                      \
00216           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1;       \
00217           break;                                               \
00218         case RCC_USART2CLKSOURCE_PLL2:                        \
00219            (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;        \
00220           break;                                               \
00221         case RCC_USART2CLKSOURCE_PLL3:                        \
00222           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;         \
00223           break;                                               \
00224         case RCC_USART2CLKSOURCE_HSI:                          \
00225           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;           \
00226           break;                                               \
00227         case RCC_USART2CLKSOURCE_CSI:                          \
00228           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;           \
00229           break;                                               \
00230         case RCC_USART2CLKSOURCE_LSE:                          \
00231           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;           \
00232           break;                                               \
00233        }                                                       \
00234     }                                                          \
00235     else if((__HANDLE__)->Instance == USART3)                  \
00236     {                                                          \
00237        switch(__HAL_RCC_GET_USART3_SOURCE())                   \
00238        {                                                       \
00239         case RCC_USART3CLKSOURCE_D2PCLK1:                      \
00240           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1;       \
00241           break;                                               \
00242         case RCC_USART3CLKSOURCE_PLL2:                        \
00243           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;         \
00244           break;                                               \
00245         case RCC_USART3CLKSOURCE_PLL3:                        \
00246           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;         \
00247           break;                                               \
00248         case RCC_USART3CLKSOURCE_HSI:                          \
00249           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;           \
00250           break;                                               \
00251         case RCC_USART3CLKSOURCE_CSI:                          \
00252           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;           \
00253           break;                                               \
00254         case RCC_USART3CLKSOURCE_LSE:                          \
00255           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;           \
00256           break;                                               \
00257        }                                                       \
00258     }                                                          \
00259     else if((__HANDLE__)->Instance == USART6)                  \
00260     {                                                          \
00261        switch(__HAL_RCC_GET_USART6_SOURCE())                   \
00262        {                                                       \
00263         case RCC_USART6CLKSOURCE_D2PCLK2:                      \
00264           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2;       \
00265           break;                                               \
00266         case RCC_USART6CLKSOURCE_PLL2:                        \
00267           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;         \
00268           break;                                               \
00269         case RCC_USART6CLKSOURCE_PLL3:                        \
00270           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;         \
00271           break;                                               \
00272         case RCC_USART6CLKSOURCE_HSI:                          \
00273           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;           \
00274           break;                                               \
00275         case RCC_USART6CLKSOURCE_CSI:                          \
00276           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;           \
00277           break;                                               \
00278         case RCC_USART6CLKSOURCE_LSE:                          \
00279           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;           \
00280           break;                                               \
00281        }                                                       \
00282     }                                                          \
00283   } while(0)
00284
00285 /** @brief  Set the Transmission Completion flag
00286   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00287   * @retval None
00288   */
00289 #define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)                                                \
00290   do {                                                                                                       \
00291     if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION))        \
00292     {                                                                                                        \
00293      (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC;                                       \
00294     }                                                                                                        \
00295     else                                                                                                     \
00296     {                                                                                                        \
00297       assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
00298     }                                                                                                        \
00299   } while(0)
00300
00301 /** @brief  Return the transmission completion flag.
00302   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00303   * @note  Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
00304   * @retval Transmission completion flag
00305   */
00306 #define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \
00307   (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) :  (SMARTCARD_FLAG_TCBGT))
00308
00309 /**
00310   * @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
00311   * @param __TXCOMPLETE__: SMARTCARD frame transmission completion used flag.
00312   * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
00313   */
00314 #define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) ||\
00315                                                               ((__TXCOMPLETE__) == SMARTCARD_TC))
00316
00317 /**
00318   * @}
00319   */
00320
00321 /* Exported functions --------------------------------------------------------*/
00322 /** @addtogroup SMARTCARDEx_Exported_Functions
00323   * @{
00324   */
00325
00326 /* Initialization and de-initialization functions  ****************************/
00327 /* IO operation methods *******************************************************/
00328
00329 /** @addtogroup SMARTCARDEx_Exported_Functions_Group1
00330   * @{
00331   */
00332
00333 /* Peripheral Control functions ***********************************************/
00334 void              HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
00335 void              HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
00336 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
00337 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
00338
00339 /**
00340   * @}
00341   */
00342
00343 /**
00344   * @}
00345   */
00346
00347 /**
00348   * @}
00349   */
00350
00351 /**
00352   * @}
00353   */
00354
00355 #ifdef __cplusplus
00356 }
00357 #endif
00358
00359 #endif /* __STM32H7xx_HAL_SMARTCARD_EX_H */
00360
00361 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_smbus.c Source File

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stm32h7xx_hal_smbus.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_smbus.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   SMBUS HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the System Management Bus (SMBus) peripheral,
00010   *          based on I2C principles of operation :
00011   *           + Initialization and de-initialization functions
00012   *           + IO operation functions
00013   *           + Peripheral State and Errors functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020     The SMBUS HAL driver can be used as follows:
00021
00022     (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
00023         SMBUS_HandleTypeDef  hsmbus;
00024
00025     (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
00026         (++) Enable the SMBUSx interface clock
00027         (++) SMBUS pins configuration
00028             (+++) Enable the clock for the SMBUS GPIOs
00029             (+++) Configure SMBUS pins as alternate function open-drain
00030         (++) NVIC configuration if you need to use interrupt process
00031             (+++) Configure the SMBUSx interrupt priority
00032             (+++) Enable the NVIC SMBUS IRQ Channel
00033
00034     (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing Mode,
00035         Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
00036         Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
00037
00038     (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
00039         (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00040              by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
00041
00042     (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
00043
00044     (#) For SMBUS IO operations, only one mode of operations is available within this driver
00045
00046     *** Interrupt mode IO operation ***
00047     ===================================
00048     [..]
00049       (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT()
00050       (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can
00051            add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
00052       (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT()
00053       (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can
00054            add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
00055       (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
00056       (++) The associated previous transfer callback is called at the end of abort process
00057       (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
00058       (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
00059       (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
00060            using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
00061       (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can
00062            add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
00063       (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can
00064            add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
00065       (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT()
00066       (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
00067            add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
00068       (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT()
00069       (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
00070            add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
00071       (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
00072       (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
00073            add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
00074            to check the Alert Error Code using function HAL_SMBUS_GetError()
00075       (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
00076       (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
00077            add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
00078            to check the Error Code using function HAL_SMBUS_GetError()
00079
00080      *** SMBUS HAL driver macros list ***
00081      ==================================
00082      [..]
00083        Below the list of most used macros in SMBUS HAL driver.
00084
00085       (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
00086       (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
00087       (+) __HAL_SMBUS_GET_FLAG : Checks whether the specified SMBUS flag is set or not
00088       (+) __HAL_SMBUS_CLEAR_FLAG : Clears the specified SMBUS pending flag
00089       (+) __HAL_SMBUS_ENABLE_IT: Enables the specified SMBUS interrupt
00090       (+) __HAL_SMBUS_DISABLE_IT: Disables the specified SMBUS interrupt
00091
00092      [..]
00093        (@) You can refer to the SMBUS HAL driver header file for more useful macros
00094
00095
00096   @endverbatim
00097   ******************************************************************************
00098   * @attention
00099   *
00100   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00101   *
00102   * Redistribution and use in source and binary forms, with or without modification,
00103   * are permitted provided that the following conditions are met:
00104   *   1. Redistributions of source code must retain the above copyright notice,
00105   *      this list of conditions and the following disclaimer.
00106   *   2. Redistributions in binary form must reproduce the above copyright notice,
00107   *      this list of conditions and the following disclaimer in the documentation
00108   *      and/or other materials provided with the distribution.
00109   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00110   *      may be used to endorse or promote products derived from this software
00111   *      without specific prior written permission.
00112   *
00113   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00114   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00115   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00116   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00117   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00118   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00119   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00120   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00121   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00122   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00123   *
00124   ******************************************************************************
00125   */
00126
00127 /* Includes ------------------------------------------------------------------*/
00128 #include "stm32h7xx_hal.h"
00129
00130 /** @addtogroup STM32H7xx_HAL_Driver
00131   * @{
00132   */
00133
00134 /** @defgroup SMBUS SMBUS
00135   * @brief SMBUS HAL module driver
00136   * @{
00137   */
00138
00139 #ifdef HAL_SMBUS_MODULE_ENABLED
00140
00141 /* Private typedef -----------------------------------------------------------*/
00142 /* Private constants ---------------------------------------------------------*/
00143 /** @defgroup SMBUS_Private_Define SMBUS Private Constants
00144  * @{
00145  */
00146 #define TIMING_CLEAR_MASK   ((uint32_t)0xF0FFFFFF)      /*<! SMBUS TIMING clear register Mask */
00147 #define HAL_TIMEOUT_ADDR    ((uint32_t)10000)           /* 10 s  */
00148 #define HAL_TIMEOUT_BUSY    ((uint32_t)25)              /* 25 ms */
00149 #define HAL_TIMEOUT_DIR     ((uint32_t)25)              /* 25 ms */
00150 #define HAL_TIMEOUT_RXNE    ((uint32_t)25)              /* 25 ms */
00151 #define HAL_TIMEOUT_STOPF   ((uint32_t)25)              /* 25 ms */
00152 #define HAL_TIMEOUT_TC      ((uint32_t)25)              /* 25 ms */
00153 #define HAL_TIMEOUT_TCR     ((uint32_t)25)              /* 25 ms */
00154 #define HAL_TIMEOUT_TXIS    ((uint32_t)25)              /* 25 ms */
00155 #define MAX_NBYTE_SIZE      255
00156 /**
00157   * @}
00158   */
00159
00160 /* Private macro -------------------------------------------------------------*/
00161 /* Private variables ---------------------------------------------------------*/
00162 /* Private function prototypes -----------------------------------------------*/
00163 /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
00164   * @{
00165   */
00166 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
00167
00168 static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
00169 static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
00170 static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus);
00171 static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus);
00172
00173 static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
00174
00175 static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
00176 /**
00177   * @}
00178   */
00179
00180 /* Exported functions --------------------------------------------------------*/
00181
00182 /** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
00183   * @{
00184   */
00185
00186 /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
00187  *  @brief    Initialization and Configuration functions
00188  *
00189 @verbatim
00190  ===============================================================================
00191               ##### Initialization and de-initialization functions #####
00192  ===============================================================================
00193     [..]  This subsection provides a set of functions allowing to initialize and
00194           de-initialize the SMBUSx peripheral:
00195
00196       (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
00197           all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
00198
00199       (+) Call the function HAL_SMBUS_Init() to configure the selected device with
00200           the selected configuration:
00201         (++) Clock Timing
00202         (++) Bus Timeout
00203         (++) Analog Filer mode
00204         (++) Own Address 1
00205         (++) Addressing mode (Master, Slave)
00206         (++) Dual Addressing mode
00207         (++) Own Address 2
00208         (++) Own Address 2 Mask
00209         (++) General call mode
00210         (++) Nostretch mode
00211         (++) Packet Error Check mode
00212         (++) Peripheral mode
00213
00214
00215       (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
00216           of the selected SMBUSx peripheral.
00217
00218 @endverbatim
00219   * @{
00220   */
00221
00222 /**
00223   * @brief  Initialize the SMBUS according to the specified parameters
00224   *         in the SMBUS_InitTypeDef and initialize the associated handle.
00225   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00226   *                the configuration information for the specified SMBUS.
00227   * @retval HAL status
00228   */
00229 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
00230 {
00231   /* Check the SMBUS handle allocation */
00232   if(hsmbus == NULL)
00233   {
00234     return HAL_ERROR;
00235   }
00236
00237   /* Check the parameters */
00238   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00239   assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
00240   assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
00241   assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
00242   assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
00243   assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
00244   assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
00245   assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
00246   assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
00247   assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
00248   assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
00249
00250   if(hsmbus->State == HAL_SMBUS_STATE_RESET)
00251   {
00252     /* Allocate lock resource and initialize it */
00253     hsmbus->Lock = HAL_UNLOCKED;
00254
00255     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00256     HAL_SMBUS_MspInit(hsmbus);
00257   }
00258
00259   hsmbus->State = HAL_SMBUS_STATE_BUSY;
00260
00261   /* Disable the selected SMBUS peripheral */
00262   __HAL_SMBUS_DISABLE(hsmbus);
00263
00264   /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
00265   /* Configure SMBUSx: Frequency range */
00266   hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
00267
00268   /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
00269   /* Configure SMBUSx: Bus Timeout  */
00270   hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
00271   hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
00272   hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
00273
00274   /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
00275   /* Configure SMBUSx: Own Address1 and ack own address1 mode */
00276   hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
00277
00278   if(hsmbus->Init.OwnAddress1 != 0U)
00279   {
00280     if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
00281     {
00282       hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
00283     }
00284     else /* SMBUS_ADDRESSINGMODE_10BIT */
00285     {
00286       hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
00287     }
00288   }
00289
00290   /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
00291   /* Configure SMBUSx: Addressing Master mode */
00292   if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
00293   {
00294     hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
00295   }
00296   /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
00297   /* AUTOEND and NACK bit will be manage during Transfer process */
00298   hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
00299
00300   /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
00301   /* Configure SMBUSx: Dual mode and Own Address2 */
00302   hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U));
00303
00304   /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
00305   /* Configure SMBUSx: Generalcall and NoStretch mode */
00306   hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
00307
00308   /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
00309   if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
00310      && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) )
00311   {
00312     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
00313   }
00314
00315   /* Enable the selected SMBUS peripheral */
00316   __HAL_SMBUS_ENABLE(hsmbus);
00317
00318   hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00319   hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
00320   hsmbus->State = HAL_SMBUS_STATE_READY;
00321
00322   return HAL_OK;
00323 }
00324
00325 /**
00326   * @brief  DeInitialize the SMBUS peripheral.
00327   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00328   *                the configuration information for the specified SMBUS.
00329   * @retval HAL status
00330   */
00331 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
00332 {
00333   /* Check the SMBUS handle allocation */
00334   if(hsmbus == NULL)
00335   {
00336     return HAL_ERROR;
00337   }
00338
00339   /* Check the parameters */
00340   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00341
00342   hsmbus->State = HAL_SMBUS_STATE_BUSY;
00343
00344   /* Disable the SMBUS Peripheral Clock */
00345   __HAL_SMBUS_DISABLE(hsmbus);
00346
00347   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00348   HAL_SMBUS_MspDeInit(hsmbus);
00349
00350   hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00351   hsmbus->PreviousState =  HAL_SMBUS_STATE_RESET;
00352   hsmbus->State = HAL_SMBUS_STATE_RESET;
00353
00354    /* Release Lock */
00355   __HAL_UNLOCK(hsmbus);
00356
00357   return HAL_OK;
00358 }
00359
00360 /**
00361   * @brief Initialize the SMBUS MSP.
00362   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00363   *                the configuration information for the specified SMBUS.
00364   * @retval None
00365   */
00366 __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
00367 {
00368   /* Prevent unused argument(s) compilation warning */
00369   UNUSED(hsmbus);
00370
00371   /* NOTE : This function should not be modified, when the callback is needed,
00372             the HAL_SMBUS_MspInit could be implemented in the user file
00373    */
00374 }
00375
00376 /**
00377   * @brief DeInitialize the SMBUS MSP.
00378   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00379   *                the configuration information for the specified SMBUS.
00380   * @retval None
00381   */
00382 __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
00383 {
00384   /* Prevent unused argument(s) compilation warning */
00385   UNUSED(hsmbus);
00386
00387   /* NOTE : This function should not be modified, when the callback is needed,
00388             the HAL_SMBUS_MspDeInit could be implemented in the user file
00389    */
00390 }
00391
00392 /**
00393   * @}
00394   */
00395
00396 /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
00397  *  @brief   Data transfers functions
00398  *
00399 @verbatim
00400  ===============================================================================
00401                       ##### IO operation functions #####
00402  ===============================================================================
00403     [..]
00404     This subsection provides a set of functions allowing to manage the SMBUS data
00405     transfers.
00406
00407     (#) Blocking mode function to check if device is ready for usage is :
00408         (++) HAL_SMBUS_IsDeviceReady()
00409
00410     (#) There is only one mode of transfer:
00411        (++) Non-Blocking mode : The communication is performed using Interrupts.
00412             These functions return the status of the transfer startup.
00413             The end of the data processing will be indicated through the
00414             dedicated SMBUS IRQ when using Interrupt mode.
00415
00416     (#) Non-Blocking mode functions with Interrupt are :
00417         (++) HAL_SMBUS_Master_Transmit_IT()
00418         (++) HAL_SMBUS_Master_Receive_IT()
00419         (++) HAL_SMBUS_Slave_Transmit_IT()
00420         (++) HAL_SMBUS_Slave_Receive_IT()
00421         (++) HAL_SMBUS_EnableListen_IT()
00422         (++) HAL_SMBUS_DisableListen_IT()
00423         (++) HAL_SMBUS_EnableAlert_IT()
00424         (++) HAL_SMBUS_DisableAlert_IT()
00425
00426     (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
00427         (++) HAL_SMBUS_MasterTxCpltCallback()
00428         (++) HAL_SMBUS_MasterRxCpltCallback()
00429         (++) HAL_SMBUS_SlaveTxCpltCallback()
00430         (++) HAL_SMBUS_SlaveRxCpltCallback()
00431         (++) HAL_SMBUS_AddrCallback()
00432         (++) HAL_SMBUS_ListenCpltCallback()
00433         (++) HAL_SMBUS_ErrorCallback()
00434
00435 @endverbatim
00436   * @{
00437   */
00438
00439 /**
00440   * @brief  Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
00441   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00442   *                the configuration information for the specified SMBUS.
00443   * @param  DevAddress: Target device address
00444   * @param  pData: Pointer to data buffer
00445   * @param  Size: Amount of data to be sent
00446   * @param  XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
00447   * @retval HAL status
00448   */
00449 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
00450 {
00451   /* Check the parameters */
00452   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
00453
00454   if(hsmbus->State == HAL_SMBUS_STATE_READY)
00455   {
00456     /* Process Locked */
00457     __HAL_LOCK(hsmbus);
00458
00459     hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
00460     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00461     /* Prepare transfer parameters */
00462     hsmbus->pBuffPtr = pData;
00463     hsmbus->XferCount = Size;
00464     hsmbus->XferOptions = XferOptions;
00465
00466     /* In case of Quick command, remove autoend mode */
00467     /* Manage the stop generation by software */
00468     if(hsmbus->pBuffPtr == NULL)
00469     {
00470       hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
00471     }
00472
00473     if(Size > MAX_NBYTE_SIZE)
00474     {
00475       hsmbus->XferSize = MAX_NBYTE_SIZE;
00476     }
00477     else
00478     {
00479       hsmbus->XferSize = Size;
00480     }
00481
00482     /* Send Slave Address */
00483     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
00484     if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
00485     {
00486       SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
00487     }
00488     else
00489     {
00490       /* If transfer direction not change, do not generate Restart Condition */
00491       /* Mean Previous state is same as current state */
00492       if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
00493       {
00494         SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
00495       }
00496       /* Else transfer direction change, so generate Restart with new transfer direction */
00497       else
00498       {
00499         /* Convert OTHER_xxx XferOptions if any */
00500         SMBUS_ConvertOtherXferOptions(hsmbus);
00501
00502         /* Handle Transfer */
00503         SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
00504       }
00505
00506       /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
00507       /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
00508       if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
00509       {
00510         hsmbus->XferSize--;
00511         hsmbus->XferCount--;
00512       }
00513     }
00514
00515     /* Process Unlocked */
00516     __HAL_UNLOCK(hsmbus);
00517
00518     /* Note : The SMBUS interrupts must be enabled after unlocking current process
00519               to avoid the risk of SMBUS interrupt handle execution before current
00520               process unlock */
00521     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
00522
00523     return HAL_OK;
00524   }
00525   else
00526   {
00527     return HAL_BUSY;
00528   }
00529 }
00530
00531 /**
00532   * @brief  Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
00533   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00534   *                the configuration information for the specified SMBUS.
00535   * @param  DevAddress: Target device address
00536   * @param  pData: Pointer to data buffer
00537   * @param  Size: Amount of data to be sent
00538   * @param  XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
00539   * @retval HAL status
00540   */
00541 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
00542 {
00543   /* Check the parameters */
00544   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
00545
00546   if(hsmbus->State == HAL_SMBUS_STATE_READY)
00547   {
00548     /* Process Locked */
00549     __HAL_LOCK(hsmbus);
00550
00551     hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
00552     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00553
00554     /* Prepare transfer parameters */
00555     hsmbus->pBuffPtr = pData;
00556     hsmbus->XferCount = Size;
00557     hsmbus->XferOptions = XferOptions;
00558
00559     /* In case of Quick command, remove autoend mode */
00560     /* Manage the stop generation by software */
00561     if(hsmbus->pBuffPtr == NULL)
00562     {
00563       hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
00564     }
00565
00566     if(Size > MAX_NBYTE_SIZE)
00567     {
00568       hsmbus->XferSize = MAX_NBYTE_SIZE;
00569     }
00570     else
00571     {
00572       hsmbus->XferSize = Size;
00573     }
00574
00575     /* Send Slave Address */
00576     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
00577     if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
00578     {
00579       SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
00580     }
00581     else
00582     {
00583       /* If transfer direction not change, do not generate Restart Condition */
00584       /* Mean Previous state is same as current state */
00585       if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
00586       {
00587         SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
00588       }
00589       /* Else transfer direction change, so generate Restart with new transfer direction */
00590       else
00591       {
00592         /* Convert OTHER_xxx XferOptions if any */
00593         SMBUS_ConvertOtherXferOptions(hsmbus);
00594
00595         /* Handle Transfer */
00596         SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
00597       }
00598     }
00599
00600     /* Process Unlocked */
00601     __HAL_UNLOCK(hsmbus);
00602
00603     /* Note : The SMBUS interrupts must be enabled after unlocking current process
00604               to avoid the risk of SMBUS interrupt handle execution before current
00605               process unlock */
00606     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
00607
00608     return HAL_OK;
00609   }
00610   else
00611   {
00612     return HAL_BUSY;
00613   }
00614 }
00615
00616 /**
00617   * @brief  Abort a master/host SMBUS process communication with Interrupt.
00618   * @note   This abort can be called only if state is ready
00619   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00620   *                the configuration information for the specified SMBUS.
00621   * @param  DevAddress: Target device address
00622   * @retval HAL status
00623   */
00624 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
00625 {
00626   if(hsmbus->State == HAL_SMBUS_STATE_READY)
00627   {
00628     /* Process Locked */
00629     __HAL_LOCK(hsmbus);
00630
00631     /* Keep the same state as previous */
00632     /* to perform as well the call of the corresponding end of transfer callback */
00633     if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
00634     {
00635       hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
00636     }
00637     else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
00638     {
00639       hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
00640     }
00641     else
00642     {
00643       /* Wrong usage of abort function */
00644       /* This function should be used only in case of abort monitored by master device */
00645       return HAL_ERROR;
00646     }
00647     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00648
00649     /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
00650     /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
00651     SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
00652
00653     /* Process Unlocked */
00654     __HAL_UNLOCK(hsmbus);
00655
00656     /* Note : The SMBUS interrupts must be enabled after unlocking current process
00657               to avoid the risk of SMBUS interrupt handle execution before current
00658               process unlock */
00659     if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
00660     {
00661       SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
00662     }
00663     else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
00664     {
00665       SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
00666     }
00667
00668     return HAL_OK;
00669   }
00670   else
00671   {
00672     return HAL_BUSY;
00673   }
00674 }
00675
00676 /**
00677   * @brief  Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
00678   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00679   *                the configuration information for the specified SMBUS.
00680   * @param  pData: Pointer to data buffer
00681   * @param  Size: Amount of data to be sent
00682   * @param  XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
00683   * @retval HAL status
00684   */
00685 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
00686 {
00687   /* Check the parameters */
00688   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
00689
00690   if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
00691   {
00692     if((pData == NULL) || (Size == 0U))
00693     {
00694       return  HAL_ERROR;
00695     }
00696
00697     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
00698     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
00699
00700     /* Process Locked */
00701     __HAL_LOCK(hsmbus);
00702
00703     hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX;
00704     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00705
00706     /* Set SBC bit to manage Acknowledge at each bit */
00707     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
00708
00709     /* Enable Address Acknowledge */
00710     hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
00711
00712     /* Prepare transfer parameters */
00713     hsmbus->pBuffPtr = pData;
00714     hsmbus->XferCount = Size;
00715     hsmbus->XferOptions = XferOptions;
00716
00717     /* Convert OTHER_xxx XferOptions if any */
00718     SMBUS_ConvertOtherXferOptions(hsmbus);
00719
00720     if(Size > MAX_NBYTE_SIZE)
00721     {
00722       hsmbus->XferSize = MAX_NBYTE_SIZE;
00723     }
00724     else
00725     {
00726       hsmbus->XferSize = Size;
00727     }
00728
00729     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
00730     if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
00731     {
00732       SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
00733     }
00734     else
00735     {
00736       /* Set NBYTE to transmit */
00737       SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
00738
00739       /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
00740       /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
00741       if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
00742       {
00743         hsmbus->XferSize--;
00744         hsmbus->XferCount--;
00745       }
00746     }
00747
00748     /* Clear ADDR flag after prepare the transfer parameters */
00749     /* This action will generate an acknowledge to the HOST */
00750     __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
00751
00752     /* Process Unlocked */
00753     __HAL_UNLOCK(hsmbus);
00754
00755     /* Note : The SMBUS interrupts must be enabled after unlocking current process
00756               to avoid the risk of SMBUS interrupt handle execution before current
00757               process unlock */
00758     /* REnable ADDR interrupt */
00759     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
00760
00761     return HAL_OK;
00762   }
00763   else
00764   {
00765     return HAL_ERROR;
00766   }
00767 }
00768
00769 /**
00770   * @brief  Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
00771   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00772   *                the configuration information for the specified SMBUS.
00773   * @param  pData: Pointer to data buffer
00774   * @param  Size: Amount of data to be sent
00775   * @param  XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
00776   * @retval HAL status
00777   */
00778 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
00779 {
00780   /* Check the parameters */
00781   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
00782
00783   if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
00784   {
00785     if((pData == NULL) || (Size == 0U))
00786     {
00787       return  HAL_ERROR;
00788     }
00789
00790     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
00791     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
00792
00793     /* Process Locked */
00794     __HAL_LOCK(hsmbus);
00795
00796     hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX;
00797     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00798
00799     /* Set SBC bit to manage Acknowledge at each bit */
00800     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
00801
00802     /* Enable Address Acknowledge */
00803     hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
00804
00805     /* Prepare transfer parameters */
00806     hsmbus->pBuffPtr = pData;
00807     hsmbus->XferSize = Size;
00808     hsmbus->XferCount = Size;
00809     hsmbus->XferOptions = XferOptions;
00810
00811     /* Convert OTHER_xxx XferOptions if any */
00812     SMBUS_ConvertOtherXferOptions(hsmbus);
00813
00814     /* Set NBYTE to receive */
00815     /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
00816     /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
00817     /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
00818     /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
00819     if((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
00820     {
00821       SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
00822     }
00823     else
00824     {
00825       SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
00826     }
00827
00828     /* Clear ADDR flag after prepare the transfer parameters */
00829     /* This action will generate an acknowledge to the HOST */
00830     __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
00831
00832     /* Process Unlocked */
00833     __HAL_UNLOCK(hsmbus);
00834
00835     /* Note : The SMBUS interrupts must be enabled after unlocking current process
00836               to avoid the risk of SMBUS interrupt handle execution before current
00837               process unlock */
00838     /* REnable ADDR interrupt */
00839     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
00840
00841     return HAL_OK;
00842   }
00843   else
00844   {
00845     return HAL_ERROR;
00846   }
00847 }
00848
00849 /**
00850   * @brief  Enable the Address listen mode with Interrupt.
00851   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00852   *                the configuration information for the specified SMBUS.
00853   * @retval HAL status
00854   */
00855 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
00856 {
00857   hsmbus->State = HAL_SMBUS_STATE_LISTEN;
00858
00859   /* Enable the Address Match interrupt */
00860   SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
00861
00862   return HAL_OK;
00863 }
00864
00865 /**
00866   * @brief  Disable the Address listen mode with Interrupt.
00867   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00868   *                the configuration information for the specified SMBUS.
00869   * @retval HAL status
00870   */
00871 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
00872 {
00873   /* Disable Address listen mode only if a transfer is not ongoing */
00874   if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
00875   {
00876     hsmbus->State = HAL_SMBUS_STATE_READY;
00877
00878     /* Disable the Address Match interrupt */
00879     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
00880
00881     return HAL_OK;
00882   }
00883   else
00884   {
00885     return HAL_BUSY;
00886   }
00887 }
00888
00889 /**
00890   * @brief  Enable the SMBUS alert mode with Interrupt.
00891   * @param  hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
00892   *                the configuration information for the specified SMBUSx peripheral.
00893   * @retval HAL status
00894   */
00895 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
00896 {
00897   /* Enable SMBus alert */
00898   hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
00899
00900   /* Clear ALERT flag */
00901   __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
00902
00903   /* Enable Alert Interrupt */
00904   SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
00905
00906   return HAL_OK;
00907 }
00908 /**
00909   * @brief  Disable the SMBUS alert mode with Interrupt.
00910   * @param  hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
00911   *                the configuration information for the specified SMBUSx peripheral.
00912   * @retval HAL status
00913   */
00914 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
00915 {
00916   /* Enable SMBus alert */
00917   hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
00918
00919   /* Disable Alert Interrupt */
00920   SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
00921
00922   return HAL_OK;
00923 }
00924
00925 /**
00926   * @brief  Check if target device is ready for communication.
00927   * @note   This function is used with Memory devices
00928   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00929   *                the configuration information for the specified SMBUS.
00930   * @param  DevAddress: Target device address
00931   * @param  Trials: Number of trials
00932   * @param  Timeout: Timeout duration
00933   * @retval HAL status
00934   */
00935 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
00936 {
00937   uint32_t tickstart = 0U;
00938
00939   __IO uint32_t SMBUS_Trials = 0U;
00940
00941   if(hsmbus->State == HAL_SMBUS_STATE_READY)
00942   {
00943     if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
00944     {
00945       return HAL_BUSY;
00946     }
00947
00948     /* Process Locked */
00949     __HAL_LOCK(hsmbus);
00950
00951     hsmbus->State = HAL_SMBUS_STATE_BUSY;
00952     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00953
00954     do
00955     {
00956       /* Generate Start */
00957       hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress);
00958
00959       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
00960       /* Wait until STOPF flag is set or a NACK flag is set*/
00961       tickstart = HAL_GetTick();
00962       while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
00963       {
00964         if(Timeout != HAL_MAX_DELAY)
00965         {
00966           if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
00967           {
00968             /* Device is ready */
00969             hsmbus->State = HAL_SMBUS_STATE_READY;
00970
00971             /* Process Unlocked */
00972             __HAL_UNLOCK(hsmbus);
00973             return HAL_TIMEOUT;
00974           }
00975         }
00976       }
00977
00978       /* Check if the NACKF flag has not been set */
00979       if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
00980       {
00981         /* Wait until STOPF flag is reset */
00982         if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
00983         {
00984           return HAL_TIMEOUT;
00985         }
00986
00987         /* Clear STOP Flag */
00988         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
00989
00990         /* Device is ready */
00991         hsmbus->State = HAL_SMBUS_STATE_READY;
00992
00993         /* Process Unlocked */
00994         __HAL_UNLOCK(hsmbus);
00995
00996         return HAL_OK;
00997       }
00998       else
00999       {
01000         /* Wait until STOPF flag is reset */
01001         if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
01002         {
01003           return HAL_TIMEOUT;
01004         }
01005
01006         /* Clear NACK Flag */
01007         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
01008
01009         /* Clear STOP Flag, auto generated with autoend*/
01010         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01011       }
01012
01013       /* Check if the maximum allowed number of trials has been reached */
01014       if (SMBUS_Trials++ == Trials)
01015       {
01016         /* Generate Stop */
01017         hsmbus->Instance->CR2 |= I2C_CR2_STOP;
01018
01019         /* Wait until STOPF flag is reset */
01020         if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
01021         {
01022           return HAL_TIMEOUT;
01023         }
01024
01025         /* Clear STOP Flag */
01026         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01027       }
01028     }while(SMBUS_Trials < Trials);
01029
01030     hsmbus->State = HAL_SMBUS_STATE_READY;
01031
01032     /* Process Unlocked */
01033     __HAL_UNLOCK(hsmbus);
01034
01035     return HAL_TIMEOUT;
01036   }
01037   else
01038   {
01039     return HAL_BUSY;
01040   }
01041 }
01042 /**
01043   * @}
01044   */
01045
01046 /** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
01047  * @{
01048  */
01049
01050 /**
01051   * @brief  Handle SMBUS event interrupt request.
01052   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01053   *                the configuration information for the specified SMBUS.
01054   * @retval None
01055   */
01056 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
01057 {
01058   uint32_t tmpisrvalue = 0U;
01059
01060   /* Use a local variable to store the current ISR flags */
01061   /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
01062   tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus);
01063
01064   /* SMBUS in mode Transmitter ---------------------------------------------------*/
01065   if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
01066   {
01067     /* Slave mode selected */
01068     if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
01069     {
01070       SMBUS_Slave_ISR(hsmbus);
01071     }
01072     /* Master mode selected */
01073     else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01074     {
01075       SMBUS_Master_ISR(hsmbus);
01076     }
01077   }
01078
01079   /* SMBUS in mode Receiver ----------------------------------------------------*/
01080   if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
01081   {
01082     /* Slave mode selected */
01083     if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
01084     {
01085       SMBUS_Slave_ISR(hsmbus);
01086     }
01087     /* Master mode selected */
01088     else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01089     {
01090       SMBUS_Master_ISR(hsmbus);
01091     }
01092   }
01093
01094    /* SMBUS in mode Listener Only --------------------------------------------------*/
01095   if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
01096      && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
01097   {
01098     if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
01099     {
01100       SMBUS_Slave_ISR(hsmbus);
01101     }
01102   }
01103 }
01104
01105 /**
01106   * @brief  Handle SMBUS error interrupt request.
01107   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01108   *                the configuration information for the specified SMBUS.
01109   * @retval None
01110   */
01111 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
01112 {
01113   /* SMBUS Bus error interrupt occurred ------------------------------------*/
01114   if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
01115   {
01116     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
01117
01118     /* Clear BERR flag */
01119     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
01120   }
01121
01122   /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
01123   if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
01124   {
01125     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
01126
01127     /* Clear OVR flag */
01128     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
01129   }
01130
01131   /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
01132   if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
01133   {
01134     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
01135
01136     /* Clear ARLO flag */
01137     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
01138   }
01139
01140   /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
01141   if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
01142   {
01143     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
01144
01145     /* Clear TIMEOUT flag */
01146     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
01147   }
01148
01149   /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
01150   if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
01151   {
01152     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
01153
01154     /* Clear ALERT flag */
01155     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
01156   }
01157
01158   /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
01159   if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
01160   {
01161     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
01162
01163     /* Clear PEC error flag */
01164     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
01165   }
01166
01167   /* Call the Error Callback in case of Error detected */
01168   if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
01169   {
01170     /* Do not Reset the HAL state in case of ALERT error */
01171     if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
01172     {
01173       if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
01174          || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
01175       {
01176         /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
01177         /* keep HAL_SMBUS_STATE_LISTEN if set */
01178         hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
01179         hsmbus->State = HAL_SMBUS_STATE_LISTEN;
01180       }
01181     }
01182
01183     /* Call the Error callback to prevent upper layer */
01184     HAL_SMBUS_ErrorCallback(hsmbus);
01185   }
01186 }
01187
01188 /**
01189   * @brief  Master Tx Transfer completed callback.
01190   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01191   *                the configuration information for the specified SMBUS.
01192   * @retval None
01193   */
01194 __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01195 {
01196   /* Prevent unused argument(s) compilation warning */
01197   UNUSED(hsmbus);
01198
01199   /* NOTE : This function should not be modified, when the callback is needed,
01200             the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
01201    */
01202 }
01203
01204 /**
01205   * @brief  Master Rx Transfer completed callback.
01206   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01207   *                the configuration information for the specified SMBUS.
01208   * @retval None
01209   */
01210 __weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01211 {
01212   /* Prevent unused argument(s) compilation warning */
01213   UNUSED(hsmbus);
01214
01215   /* NOTE : This function should not be modified, when the callback is needed,
01216             the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file
01217    */
01218 }
01219
01220 /** @brief  Slave Tx Transfer completed callback.
01221   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01222   *                the configuration information for the specified SMBUS.
01223   * @retval None
01224   */
01225 __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01226 {
01227   /* Prevent unused argument(s) compilation warning */
01228   UNUSED(hsmbus);
01229
01230   /* NOTE : This function should not be modified, when the callback is needed,
01231             the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
01232    */
01233 }
01234
01235 /**
01236   * @brief  Slave Rx Transfer completed callback.
01237   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01238   *                the configuration information for the specified SMBUS.
01239   * @retval None
01240   */
01241 __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01242 {
01243   /* Prevent unused argument(s) compilation warning */
01244   UNUSED(hsmbus);
01245
01246   /* NOTE : This function should not be modified, when the callback is needed,
01247             the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file
01248    */
01249 }
01250
01251 /**
01252   * @brief  Slave Address Match callback.
01253   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01254   *                the configuration information for the specified SMBUS.
01255   * @param  TransferDirection: Master request Transfer Direction (Write/Read)
01256   * @param  AddrMatchCode: Address Match Code
01257   * @retval None
01258   */
01259 __weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
01260 {
01261   /* Prevent unused argument(s) compilation warning */
01262   UNUSED(hsmbus);
01263   UNUSED(TransferDirection);
01264   UNUSED(AddrMatchCode);
01265
01266   /* NOTE : This function should not be modified, when the callback is needed,
01267             the HAL_SMBUS_AddrCallback() could be implemented in the user file
01268    */
01269 }
01270
01271 /**
01272   * @brief  Listen Complete callback.
01273   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01274   *                the configuration information for the specified SMBUS.
01275   * @retval None
01276   */
01277 __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01278 {
01279   /* Prevent unused argument(s) compilation warning */
01280   UNUSED(hsmbus);
01281
01282   /* NOTE : This function should not be modified, when the callback is needed,
01283             the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
01284    */
01285 }
01286
01287 /**
01288   * @brief  SMBUS error callback.
01289   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01290   *                the configuration information for the specified SMBUS.
01291   * @retval None
01292   */
01293 __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
01294 {
01295   /* Prevent unused argument(s) compilation warning */
01296   UNUSED(hsmbus);
01297
01298   /* NOTE : This function should not be modified, when the callback is needed,
01299             the HAL_SMBUS_ErrorCallback() could be implemented in the user file
01300    */
01301 }
01302
01303 /**
01304   * @}
01305   */
01306
01307 /** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
01308  *  @brief   Peripheral State and Errors functions
01309  *
01310 @verbatim
01311  ===============================================================================
01312             ##### Peripheral State and Errors functions #####
01313  ===============================================================================
01314     [..]
01315     This subsection permits to get in run-time the status of the peripheral
01316     and the data flow.
01317
01318 @endverbatim
01319   * @{
01320   */
01321
01322 /**
01323   * @brief  Return the SMBUS handle state.
01324   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01325   *                the configuration information for the specified SMBUS.
01326   * @retval HAL state
01327   */
01328 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
01329 {
01330   /* Return SMBUS handle state */
01331   return hsmbus->State;
01332 }
01333
01334 /**
01335 * @brief  Return the SMBUS error code.
01336 * @param  hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
01337   *              the configuration information for the specified SMBUS.
01338 * @retval SMBUS Error Code
01339 */
01340 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
01341 {
01342   return hsmbus->ErrorCode;
01343 }
01344
01345 /**
01346   * @}
01347   */
01348
01349 /**
01350   * @}
01351   */
01352
01353 /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
01354  *  @brief   Data transfers Private functions
01355   * @{
01356   */
01357
01358 /**
01359   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
01360   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01361   *                the configuration information for the specified SMBUS.
01362   * @retval HAL status
01363   */
01364 static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
01365 {
01366   uint16_t DevAddress;
01367
01368   /* Process Locked */
01369   __HAL_LOCK(hsmbus);
01370
01371   if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
01372   {
01373     /* Clear NACK Flag */
01374     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
01375
01376     /* Set corresponding Error Code */
01377     /* No need to generate STOP, it is automatically done */
01378     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
01379
01380     /* Process Unlocked */
01381     __HAL_UNLOCK(hsmbus);
01382
01383     /* Call the Error callback to prevent upper layer */
01384     HAL_SMBUS_ErrorCallback(hsmbus);
01385   }
01386   else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
01387   {
01388     /* Call the corresponding callback to inform upper layer of End of Transfer */
01389     if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01390     {
01391       /* Disable Interrupt */
01392       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
01393
01394       /* Clear STOP Flag */
01395       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01396
01397       /* Clear Configuration Register 2 */
01398       SMBUS_RESET_CR2(hsmbus);
01399
01400       /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
01401       /* Disable the selected SMBUS peripheral */
01402       __HAL_SMBUS_DISABLE(hsmbus);
01403
01404       hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
01405       hsmbus->State = HAL_SMBUS_STATE_READY;
01406
01407       /* Process Unlocked */
01408       __HAL_UNLOCK(hsmbus);
01409
01410       /* REenable the selected SMBUS peripheral */
01411       __HAL_SMBUS_ENABLE(hsmbus);
01412
01413       HAL_SMBUS_MasterTxCpltCallback(hsmbus);
01414     }
01415     else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01416     {
01417       /* Store Last receive data if any */
01418       if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
01419       {
01420         /* Read data from RXDR */
01421         (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
01422
01423         if((hsmbus->XferSize > 0U))
01424         {
01425           hsmbus->XferSize--;
01426           hsmbus->XferCount--;
01427         }
01428       }
01429
01430       /* Disable Interrupt */
01431       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
01432
01433       /* Clear STOP Flag */
01434       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01435
01436       /* Clear Configuration Register 2 */
01437       SMBUS_RESET_CR2(hsmbus);
01438
01439       hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
01440       hsmbus->State = HAL_SMBUS_STATE_READY;
01441
01442       /* Process Unlocked */
01443       __HAL_UNLOCK(hsmbus);
01444
01445       HAL_SMBUS_MasterRxCpltCallback(hsmbus);
01446     }
01447   }
01448   else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
01449   {
01450     /* Read data from RXDR */
01451     (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
01452     hsmbus->XferSize--;
01453     hsmbus->XferCount--;
01454   }
01455   else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
01456   {
01457     /* Write data to TXDR */
01458     hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
01459     hsmbus->XferSize--;
01460     hsmbus->XferCount--;
01461   }
01462   else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
01463   {
01464     if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U))
01465     {
01466       DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
01467
01468       if(hsmbus->XferCount > MAX_NBYTE_SIZE)
01469       {
01470         SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
01471         hsmbus->XferSize = MAX_NBYTE_SIZE;
01472       }
01473       else
01474       {
01475         hsmbus->XferSize = hsmbus->XferCount;
01476         SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
01477         /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
01478         /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
01479         if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
01480         {
01481           hsmbus->XferSize--;
01482           hsmbus->XferCount--;
01483         }
01484       }
01485     }
01486     else if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount == 0U))
01487     {
01488       /* Call TxCpltCallback() if no stop mode is set */
01489       if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
01490       {
01491         /* Call the corresponding callback to inform upper layer of End of Transfer */
01492         if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01493         {
01494           /* Disable Interrupt */
01495           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
01496           hsmbus->PreviousState = hsmbus->State;
01497           hsmbus->State = HAL_SMBUS_STATE_READY;
01498
01499           /* Process Unlocked */
01500           __HAL_UNLOCK(hsmbus);
01501
01502           HAL_SMBUS_MasterTxCpltCallback(hsmbus);
01503         }
01504         else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01505         {
01506           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
01507           hsmbus->PreviousState = hsmbus->State;
01508           hsmbus->State = HAL_SMBUS_STATE_READY;
01509
01510           /* Process Unlocked */
01511           __HAL_UNLOCK(hsmbus);
01512
01513           HAL_SMBUS_MasterRxCpltCallback(hsmbus);
01514         }
01515       }
01516     }
01517   }
01518   else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
01519   {
01520     if(hsmbus->XferCount == 0U)
01521     {
01522       /* Specific use case for Quick command */
01523       if(hsmbus->pBuffPtr == NULL)
01524       {
01525         /* Generate a Stop command */
01526         hsmbus->Instance->CR2 |= I2C_CR2_STOP;
01527       }
01528       /* Call TxCpltCallback() if no stop mode is set */
01529       else if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
01530       {
01531         /* No Generate Stop, to permit restart mode */
01532         /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
01533
01534         /* Call the corresponding callback to inform upper layer of End of Transfer */
01535         if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01536         {
01537           /* Disable Interrupt */
01538           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
01539           hsmbus->PreviousState = hsmbus->State;
01540           hsmbus->State = HAL_SMBUS_STATE_READY;
01541
01542           /* Process Unlocked */
01543           __HAL_UNLOCK(hsmbus);
01544
01545           HAL_SMBUS_MasterTxCpltCallback(hsmbus);
01546         }
01547         else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01548         {
01549           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
01550           hsmbus->PreviousState = hsmbus->State;
01551           hsmbus->State = HAL_SMBUS_STATE_READY;
01552
01553           /* Process Unlocked */
01554           __HAL_UNLOCK(hsmbus);
01555
01556           HAL_SMBUS_MasterRxCpltCallback(hsmbus);
01557         }
01558       }
01559     }
01560   }
01561
01562   /* Process Unlocked */
01563   __HAL_UNLOCK(hsmbus);
01564
01565   return HAL_OK;
01566 }
01567 /**
01568   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
01569   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01570   *                the configuration information for the specified SMBUS.
01571   * @retval HAL status
01572   */
01573 static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
01574 {
01575   uint8_t TransferDirection = 0U;
01576   uint16_t SlaveAddrCode = 0U;
01577
01578   /* Process Locked */
01579   __HAL_LOCK(hsmbus);
01580
01581   if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
01582   {
01583     /* Check that SMBUS transfer finished */
01584     /* if yes, normal use case, a NACK is sent by the HOST when Transfer is finished */
01585     /* Mean XferCount == 0*/
01586     /* So clear Flag NACKF only */
01587     if(hsmbus->XferCount == 0U)
01588     {
01589       /* Clear NACK Flag */
01590       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
01591
01592       /* Process Unlocked */
01593       __HAL_UNLOCK(hsmbus);
01594     }
01595     else
01596     {
01597       /* if no, error use case, a Non-Acknowledge of last Data is generated by the HOST*/
01598       /* Clear NACK Flag */
01599       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
01600
01601       /* Set HAL State to "Idle" State, mean to LISTEN state */
01602       /* So reset Slave Busy state */
01603       hsmbus->PreviousState = hsmbus->State;
01604       hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
01605       hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
01606
01607       /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
01608       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
01609
01610       /* Set ErrorCode corresponding to a Non-Acknowledge */
01611       hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
01612
01613       /* Process Unlocked */
01614       __HAL_UNLOCK(hsmbus);
01615
01616       /* Call the Error callback to prevent upper layer */
01617       HAL_SMBUS_ErrorCallback(hsmbus);
01618     }
01619   }
01620   else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
01621   {
01622     TransferDirection = SMBUS_GET_DIR(hsmbus);
01623     SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus);
01624
01625     /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
01626     /* Other ADDRInterrupt will be treat in next Listen use case */
01627     __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
01628
01629     /* Process Unlocked */
01630     __HAL_UNLOCK(hsmbus);
01631
01632     /* Call Slave Addr callback */
01633     HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
01634   }
01635   else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
01636   {
01637     if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
01638     {
01639       /* Read data from RXDR */
01640       (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
01641       hsmbus->XferSize--;
01642       hsmbus->XferCount--;
01643
01644       if(hsmbus->XferCount == 1U)
01645       {
01646         /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
01647         /* or only the last Byte of Transfer */
01648         /* So reset the RELOAD bit mode */
01649         hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
01650         SMBUS_TransferConfig(hsmbus, 0U ,1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
01651       }
01652       else if(hsmbus->XferCount == 0U)
01653       {
01654         /* Last Byte is received, disable Interrupt */
01655         SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
01656
01657         /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
01658         hsmbus->PreviousState = hsmbus->State;
01659         hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
01660
01661         /* Process Unlocked */
01662         __HAL_UNLOCK(hsmbus);
01663
01664         /* Call the Rx complete callback to inform upper layer of the end of receive process */
01665         HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
01666       }
01667       else
01668       {
01669         /* Set Reload for next Bytes */
01670         SMBUS_TransferConfig(hsmbus, 0U, 1U, SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
01671
01672         /* Ack last Byte Read */
01673         hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
01674       }
01675     }
01676     else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
01677     {
01678       if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U))
01679       {
01680         if(hsmbus->XferCount > MAX_NBYTE_SIZE)
01681         {
01682           SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
01683           hsmbus->XferSize = MAX_NBYTE_SIZE;
01684         }
01685         else
01686         {
01687           hsmbus->XferSize = hsmbus->XferCount;
01688           SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
01689           /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
01690           /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
01691           if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
01692           {
01693             hsmbus->XferSize--;
01694             hsmbus->XferCount--;
01695           }
01696         }
01697       }
01698     }
01699   }
01700   else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
01701   {
01702     /* Write data to TXDR only if XferCount not reach "0" */
01703     /* A TXIS flag can be set, during STOP treatment      */
01704     /* Check if all Data have already been sent */
01705     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
01706     if(hsmbus->XferCount > 0U)
01707     {
01708       /* Write data to TXDR */
01709       hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
01710       hsmbus->XferCount--;
01711       hsmbus->XferSize--;
01712     }
01713
01714     if(hsmbus->XferCount == 0U)
01715     {
01716       /* Last Byte is Transmitted */
01717       /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
01718       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
01719       hsmbus->PreviousState = hsmbus->State;
01720       hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
01721
01722       /* Process Unlocked */
01723       __HAL_UNLOCK(hsmbus);
01724
01725       /* Call the Tx complete callback to inform upper layer of the end of transmit process */
01726       HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
01727     }
01728   }
01729
01730   /* Check if STOPF is set */
01731   if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
01732   {
01733     if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
01734     {
01735       /* Store Last receive data if any */
01736       if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
01737       {
01738         /* Read data from RXDR */
01739         (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
01740
01741         if((hsmbus->XferSize > 0U))
01742         {
01743           hsmbus->XferSize--;
01744           hsmbus->XferCount--;
01745         }
01746       }
01747
01748       /* Disable RX and TX Interrupts */
01749       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
01750
01751       /* Disable ADDR Interrupt */
01752       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
01753
01754       /* Disable Address Acknowledge */
01755       hsmbus->Instance->CR2 |= I2C_CR2_NACK;
01756
01757       /* Clear Configuration Register 2 */
01758       SMBUS_RESET_CR2(hsmbus);
01759
01760       /* Clear STOP Flag */
01761       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01762
01763      /* Clear ADDR flag */
01764      __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
01765
01766       hsmbus->XferOptions = 0U;
01767       hsmbus->PreviousState = hsmbus->State;
01768       hsmbus->State = HAL_SMBUS_STATE_READY;
01769
01770       /* Process Unlocked */
01771       __HAL_UNLOCK(hsmbus);
01772
01773       /* Call the Listen Complete callback, to prevent upper layer of the end of Listen use case */
01774       HAL_SMBUS_ListenCpltCallback(hsmbus);
01775     }
01776   }
01777
01778   /* Process Unlocked */
01779   __HAL_UNLOCK(hsmbus);
01780
01781   return HAL_OK;
01782 }
01783 /**
01784   * @brief  Manage the enabling of Interrupts.
01785   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01786   *                the configuration information for the specified SMBUS.
01787   * @param  InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition.
01788   * @retval HAL status
01789   */
01790 static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
01791 {
01792   uint32_t tmpisr = 0U;
01793
01794   if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
01795   {
01796     /* Enable ERR interrupt */
01797     tmpisr |= SMBUS_IT_ERRI;
01798   }
01799
01800   if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
01801   {
01802     /* Enable ADDR, STOP interrupt */
01803     tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
01804   }
01805
01806   if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
01807   {
01808     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01809     tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
01810   }
01811
01812   if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
01813   {
01814     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01815     tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
01816   }
01817
01818   /* Enable interrupts only at the end */
01819   /* to avoid the risk of SMBUS interrupt handle execution before */
01820   /* all interrupts requested done */
01821   __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
01822
01823   return HAL_OK;
01824 }
01825 /**
01826   * @brief  Manage the disabling of Interrupts.
01827   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01828   *                the configuration information for the specified SMBUS.
01829   * @param  InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition.
01830   * @retval HAL status
01831   */
01832 static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
01833 {
01834   uint32_t tmpisr = 0U;
01835
01836   if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) )
01837   {
01838     /* Disable ERR interrupt */
01839     tmpisr |= SMBUS_IT_ERRI;
01840   }
01841
01842   if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
01843   {
01844     /* Disable TC, STOP, NACK, TXI interrupt */
01845     tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
01846
01847     if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
01848        && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
01849     {
01850       /* Disable ERR interrupt */
01851       tmpisr |= SMBUS_IT_ERRI;
01852     }
01853
01854     if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
01855     {
01856       /* Disable STOPI, NACKI */
01857       tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
01858     }
01859   }
01860
01861   if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
01862   {
01863     /* Disable TC, STOP, NACK, RXI interrupt */
01864     tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
01865
01866     if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
01867        && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
01868     {
01869       /* Disable ERR interrupt */
01870       tmpisr |= SMBUS_IT_ERRI;
01871     }
01872
01873     if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
01874     {
01875       /* Disable STOPI, NACKI */
01876       tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
01877     }
01878   }
01879
01880   if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
01881   {
01882     /* Enable ADDR, STOP interrupt */
01883     tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
01884
01885     if(SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
01886     {
01887       /* Disable ERR interrupt */
01888       tmpisr |= SMBUS_IT_ERRI;
01889     }
01890   }
01891
01892   /* Disable interrupts only at the end */
01893   /* to avoid a breaking situation like at "t" time */
01894   /* all disable interrupts request are not done */
01895   __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
01896
01897   return HAL_OK;
01898 }
01899 /**
01900   * @brief  Handle SMBUS Communication Timeout.
01901   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01902   *                the configuration information for the specified SMBUS.
01903   * @param  Flag: specifies the SMBUS flag to check.
01904   * @param  Status: The new Flag status (SET or RESET).
01905   * @param  Timeout: Timeout duration
01906   * @retval HAL status
01907   */
01908 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
01909 {
01910   uint32_t tickstart = HAL_GetTick();
01911
01912   /* Wait until flag is set */
01913   if(Status == RESET)
01914   {
01915     while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
01916     {
01917       /* Check for the Timeout */
01918       if(Timeout != HAL_MAX_DELAY)
01919       {
01920         if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
01921         {
01922           hsmbus->PreviousState = hsmbus->State;
01923           hsmbus->State= HAL_SMBUS_STATE_READY;
01924
01925           /* Process Unlocked */
01926           __HAL_UNLOCK(hsmbus);
01927
01928           return HAL_TIMEOUT;
01929         }
01930       }
01931     }
01932   }
01933   else
01934   {
01935     while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
01936     {
01937       /* Check for the Timeout */
01938       if(Timeout != HAL_MAX_DELAY)
01939       {
01940         if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
01941         {
01942           hsmbus->PreviousState = hsmbus->State;
01943           hsmbus->State= HAL_SMBUS_STATE_READY;
01944
01945           /* Process Unlocked */
01946           __HAL_UNLOCK(hsmbus);
01947
01948           return HAL_TIMEOUT;
01949         }
01950       }
01951     }
01952   }
01953   return HAL_OK;
01954 }
01955
01956 /**
01957   * @brief  Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
01958   * @param  hsmbus: SMBUS handle.
01959   * @param  DevAddress: specifies the slave address to be programmed.
01960   * @param  Size: specifies the number of bytes to be programmed.
01961   *   This parameter must be a value between 0 and 255.
01962   * @param  Mode: new state of the SMBUS START condition generation.
01963   *   This parameter can be one or a combination  of the following values:
01964   *     @arg SMBUS_NO_MODE: No specific mode enabled.
01965   *     @arg SMBUS_RELOAD_MODE: Enable Reload mode.
01966   *     @arg SMBUS_AUTOEND_MODE: Enable Automatic end mode.
01967   *     @arg SMBUS_SOFTEND_MODE: Enable Software end mode and Reload mode.
01968   * @param  Request: new state of the SMBUS START condition generation.
01969   *   This parameter can be one of the following values:
01970   *     @arg SMBUS_NO_STARTSTOP: Don't Generate stop and start condition.
01971   *     @arg SMBUS_GENERATE_STOP: Generate stop condition (Size should be set to 0).
01972   *     @arg SMBUS_GENERATE_START_READ: Generate Restart for read request.
01973   *     @arg SMBUS_GENERATE_START_WRITE: Generate Restart for write request.
01974   * @retval None
01975   */
01976 static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
01977 {
01978   uint32_t tmpreg = 0U;
01979
01980   /* Check the parameters */
01981   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
01982   assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
01983   assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
01984
01985   /* Get the CR2 register value */
01986   tmpreg = hsmbus->Instance->CR2;
01987
01988   /* clear tmpreg specific bits */
01989   tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE));
01990
01991   /* update tmpreg */
01992   tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U ) & I2C_CR2_NBYTES) | \
01993               (uint32_t)Mode | (uint32_t)Request);
01994
01995   /* update CR2 register */
01996   hsmbus->Instance->CR2 = tmpreg;
01997 }
01998
01999 /**
02000   * @brief  Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
02001   * @param  hsmbus SMBUS handle.
02002   * @retval None
02003   */
02004 static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
02005 {
02006   /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC   */
02007   /* it request implicitly to generate a restart condition */
02008   /* set XferOptions to SMBUS_FIRST_FRAME                  */
02009   if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
02010   {
02011     hsmbus->XferOptions = SMBUS_FIRST_FRAME;
02012   }
02013   /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */
02014   /* it request implicitly to generate a restart condition      */
02015   /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE  */
02016   else if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
02017   {
02018     hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE;
02019   }
02020   /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */
02021   /* it request implicitly to generate a restart condition             */
02022   /* then generate a stop condition at the end of transfer             */
02023   /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC              */
02024   else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
02025   {
02026     hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
02027   }
02028   /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */
02029   /* it request implicitly to generate a restart condition               */
02030   /* then generate a stop condition at the end of transfer               */
02031   /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC              */
02032   else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
02033   {
02034     hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
02035   }
02036 }
02037 /**
02038   * @}
02039   */
02040
02041 #endif /* HAL_SMBUS_MODULE_ENABLED */
02042 /**
02043   * @}
02044   */
02045
02046 /**
02047   * @}
02048   */
02049
02050 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_smbus.h Source File

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stm32h7xx_hal_smbus.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_smbus.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of SMBUS HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_SMBUS_H
00040 #define __STM32H7xx_HAL_SMBUS_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SMBUS
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types
00059   * @{
00060   */
00061
00062 /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
00063   * @brief  SMBUS Configuration Structure definition
00064   * @{
00065   */
00066 typedef struct
00067 {
00068   uint32_t Timing;                 /*!< Specifies the SMBUS_TIMINGR_register value.
00069                                      This parameter calculated by referring to SMBUS initialization
00070                                             section in Reference manual */
00071   uint32_t AnalogFilter;           /*!< Specifies if Analog Filter is enable or not.
00072                                      This parameter can be a value of @ref SMBUS_Analog_Filter */
00073
00074   uint32_t OwnAddress1;            /*!< Specifies the first device own address.
00075                                      This parameter can be a 7-bit or 10-bit address. */
00076
00077   uint32_t AddressingMode;         /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
00078                                      This parameter can be a value of @ref SMBUS_addressing_mode */
00079
00080   uint32_t DualAddressMode;        /*!< Specifies if dual addressing mode is selected.
00081                                      This parameter can be a value of @ref SMBUS_dual_addressing_mode */
00082
00083   uint32_t OwnAddress2;            /*!< Specifies the second device own address if dual addressing mode is selected
00084                                      This parameter can be a 7-bit address. */
00085
00086   uint32_t OwnAddress2Masks;       /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
00087                                      This parameter can be a value of @ref SMBUS_own_address2_masks. */
00088
00089   uint32_t GeneralCallMode;        /*!< Specifies if general call mode is selected.
00090                                      This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
00091
00092   uint32_t NoStretchMode;          /*!< Specifies if nostretch mode is selected.
00093                                      This parameter can be a value of @ref SMBUS_nostretch_mode */
00094
00095   uint32_t PacketErrorCheckMode;   /*!< Specifies if Packet Error Check mode is selected.
00096                                      This parameter can be a value of @ref SMBUS_packet_error_check_mode */
00097
00098   uint32_t PeripheralMode;         /*!< Specifies which mode of Periphal is selected.
00099                                      This parameter can be a value of @ref SMBUS_peripheral_mode */
00100
00101   uint32_t SMBusTimeout;           /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
00102                                      (Enable bits and different timeout values)
00103                                      This parameter calculated by referring to SMBUS initialization
00104                                          section in Reference manual */
00105 } SMBUS_InitTypeDef;
00106 /**
00107   * @}
00108   */
00109
00110 /** @defgroup HAL_state_definition HAL state definition
00111   * @brief  HAL State definition
00112   * @{
00113   */
00114 #define HAL_SMBUS_STATE_RESET           (0x00000000U)  /*!< SMBUS not yet initialized or disabled         */
00115 #define HAL_SMBUS_STATE_READY           (0x00000001U)  /*!< SMBUS initialized and ready for use           */
00116 #define HAL_SMBUS_STATE_BUSY            (0x00000002U)  /*!< SMBUS internal process is ongoing             */
00117 #define HAL_SMBUS_STATE_MASTER_BUSY_TX  (0x00000012U)  /*!< Master Data Transmission process is ongoing   */
00118 #define HAL_SMBUS_STATE_MASTER_BUSY_RX  (0x00000022U)  /*!< Master Data Reception process is ongoing      */
00119 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX   (0x00000032U)  /*!< Slave Data Transmission process is ongoing    */
00120 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX   (0x00000042U)  /*!< Slave Data Reception process is ongoing       */
00121 #define HAL_SMBUS_STATE_TIMEOUT         (0x00000003U)  /*!< Timeout state                                 */
00122 #define HAL_SMBUS_STATE_ERROR           (0x00000004U)  /*!< Reception process is ongoing                  */
00123 #define HAL_SMBUS_STATE_LISTEN          (0x00000008U)   /*!< Address Listen Mode is ongoing                */
00124 /**
00125   * @}
00126   */
00127
00128 /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
00129   * @brief  SMBUS Error Code definition
00130   * @{
00131   */
00132 #define HAL_SMBUS_ERROR_NONE            (0x00000000U)    /*!< No error             */
00133 #define HAL_SMBUS_ERROR_BERR            (0x00000001U)    /*!< BERR error           */
00134 #define HAL_SMBUS_ERROR_ARLO            (0x00000002U)    /*!< ARLO error           */
00135 #define HAL_SMBUS_ERROR_ACKF            (0x00000004U)    /*!< ACKF error           */
00136 #define HAL_SMBUS_ERROR_OVR             (0x00000008U)    /*!< OVR error            */
00137 #define HAL_SMBUS_ERROR_HALTIMEOUT      (0x00000010U)    /*!< Timeout error        */
00138 #define HAL_SMBUS_ERROR_BUSTIMEOUT      (0x00000020U)    /*!< Bus Timeout error    */
00139 #define HAL_SMBUS_ERROR_ALERT           (0x00000040U)    /*!< Alert error          */
00140 #define HAL_SMBUS_ERROR_PECERR          (0x00000080U)    /*!< PEC error            */
00141 /**
00142   * @}
00143   */
00144
00145 /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
00146   * @brief  SMBUS handle Structure definition
00147   * @{
00148   */
00149 typedef struct
00150 {
00151   I2C_TypeDef                  *Instance;       /*!< SMBUS registers base address       */
00152
00153   SMBUS_InitTypeDef            Init;            /*!< SMBUS communication parameters     */
00154
00155   uint8_t                      *pBuffPtr;       /*!< Pointer to SMBUS transfer buffer   */
00156
00157   uint16_t                     XferSize;        /*!< SMBUS transfer size                */
00158
00159   __IO uint16_t                XferCount;       /*!< SMBUS transfer counter             */
00160
00161   __IO uint32_t                XferOptions;     /*!< SMBUS transfer options             */
00162
00163   __IO uint32_t                PreviousState;   /*!< SMBUS communication Previous state */
00164
00165   HAL_LockTypeDef              Lock;            /*!< SMBUS locking object               */
00166
00167   __IO uint32_t                State;           /*!< SMBUS communication state          */
00168
00169   __IO uint32_t                ErrorCode;       /*!< SMBUS Error code                   */
00170
00171 }SMBUS_HandleTypeDef;
00172 /**
00173   * @}
00174   */
00175
00176 /**
00177   * @}
00178   */
00179 /* Exported constants --------------------------------------------------------*/
00180
00181 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
00182   * @{
00183   */
00184
00185 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
00186   * @{
00187   */
00188 #define SMBUS_ANALOGFILTER_ENABLE               (0x00000000U)
00189 #define SMBUS_ANALOGFILTER_DISABLE              I2C_CR1_ANFOFF
00190 /**
00191   * @}
00192   */
00193
00194 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode
00195   * @{
00196   */
00197 #define SMBUS_ADDRESSINGMODE_7BIT               (0x00000001U)
00198 #define SMBUS_ADDRESSINGMODE_10BIT              (0x00000002U)
00199 /**
00200   * @}
00201   */
00202
00203 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
00204   * @{
00205   */
00206
00207 #define SMBUS_DUALADDRESS_DISABLE               (0x00000000U)
00208 #define SMBUS_DUALADDRESS_ENABLE                I2C_OAR2_OA2EN
00209 /**
00210   * @}
00211   */
00212
00213 /** @defgroup SMBUS_own_address2_masks SMBUS own address2 masks
00214   * @{
00215   */
00216
00217 #define SMBUS_OA2_NOMASK                        ((uint8_t)0x00U)
00218 #define SMBUS_OA2_MASK01                        ((uint8_t)0x01U)
00219 #define SMBUS_OA2_MASK02                        ((uint8_t)0x02U)
00220 #define SMBUS_OA2_MASK03                        ((uint8_t)0x03U)
00221 #define SMBUS_OA2_MASK04                        ((uint8_t)0x04U)
00222 #define SMBUS_OA2_MASK05                        ((uint8_t)0x05U)
00223 #define SMBUS_OA2_MASK06                        ((uint8_t)0x06U)
00224 #define SMBUS_OA2_MASK07                        ((uint8_t)0x07U)
00225 /**
00226   * @}
00227   */
00228
00229
00230 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
00231   * @{
00232   */
00233 #define SMBUS_GENERALCALL_DISABLE               (0x00000000U)
00234 #define SMBUS_GENERALCALL_ENABLE                I2C_CR1_GCEN
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
00240   * @{
00241   */
00242 #define SMBUS_NOSTRETCH_DISABLE                 (0x00000000U)
00243 #define SMBUS_NOSTRETCH_ENABLE                  I2C_CR1_NOSTRETCH
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
00249   * @{
00250   */
00251 #define SMBUS_PEC_DISABLE                       (0x00000000U)
00252 #define SMBUS_PEC_ENABLE                        I2C_CR1_PECEN
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
00258   * @{
00259   */
00260 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST        I2C_CR1_SMBHEN
00261 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE       (0x00000000U)
00262 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP   I2C_CR1_SMBDEN
00263 /**
00264   * @}
00265   */
00266
00267 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
00268   * @{
00269   */
00270
00271 #define  SMBUS_SOFTEND_MODE                     (0x00000000U)
00272 #define  SMBUS_RELOAD_MODE                      I2C_CR2_RELOAD
00273 #define  SMBUS_AUTOEND_MODE                     I2C_CR2_AUTOEND
00274 #define  SMBUS_SENDPEC_MODE                     I2C_CR2_PECBYTE
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
00280   * @{
00281   */
00282
00283 #define  SMBUS_NO_STARTSTOP                     (0x00000000U)
00284 #define  SMBUS_GENERATE_STOP                    I2C_CR2_STOP
00285 #define  SMBUS_GENERATE_START_READ              (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
00286 #define  SMBUS_GENERATE_START_WRITE             I2C_CR2_START
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
00292   * @{
00293   */
00294
00295 /* List of XferOptions in usage of :
00296  * 1- Restart condition when direction change
00297  * 2- No Restart condition in other use cases
00298  */
00299 #define  SMBUS_FIRST_FRAME                      SMBUS_SOFTEND_MODE
00300 #define  SMBUS_NEXT_FRAME                       ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
00301 #define  SMBUS_FIRST_AND_LAST_FRAME_NO_PEC      SMBUS_AUTOEND_MODE
00302 #define  SMBUS_LAST_FRAME_NO_PEC                SMBUS_AUTOEND_MODE
00303 #define  SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC    ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
00304 #define  SMBUS_LAST_FRAME_WITH_PEC              ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
00305
00306 /* List of XferOptions in usage of :
00307  * 1- Restart condition in all use cases (direction change or not)
00308  */
00309 #define  SMBUS_OTHER_FRAME_NO_PEC               (0x000000AAU)
00310 #define  SMBUS_OTHER_FRAME_WITH_PEC             (0x0000AA00U)
00311 #define  SMBUS_OTHER_AND_LAST_FRAME_NO_PEC      (0x00AA0000U)
00312 #define  SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC    (0xAA000000U)
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
00318   * @brief SMBUS Interrupt definition
00319   *        Elements values convention: 0xXXXXXXXX
00320   *           - XXXXXXXX  : Interrupt control mask
00321   * @{
00322   */
00323 #define SMBUS_IT_ERRI                           I2C_CR1_ERRIE
00324 #define SMBUS_IT_TCI                            I2C_CR1_TCIE
00325 #define SMBUS_IT_STOPI                          I2C_CR1_STOPIE
00326 #define SMBUS_IT_NACKI                          I2C_CR1_NACKIE
00327 #define SMBUS_IT_ADDRI                          I2C_CR1_ADDRIE
00328 #define SMBUS_IT_RXI                            I2C_CR1_RXIE
00329 #define SMBUS_IT_TXI                            I2C_CR1_TXIE
00330 #define SMBUS_IT_TX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
00331 #define SMBUS_IT_RX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
00332 #define SMBUS_IT_ALERT                          (SMBUS_IT_ERRI)
00333 #define SMBUS_IT_ADDR                           (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
00334 /**
00335   * @}
00336   */
00337
00338 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition
00339   * @brief Flag definition
00340   *        Elements values convention: 0xXXXXYYYY
00341   *           - XXXXXXXX  : Flag mask
00342   * @{
00343   */
00344
00345 #define  SMBUS_FLAG_TXE                         I2C_ISR_TXE
00346 #define  SMBUS_FLAG_TXIS                        I2C_ISR_TXIS
00347 #define  SMBUS_FLAG_RXNE                        I2C_ISR_RXNE
00348 #define  SMBUS_FLAG_ADDR                        I2C_ISR_ADDR
00349 #define  SMBUS_FLAG_AF                          I2C_ISR_NACKF
00350 #define  SMBUS_FLAG_STOPF                       I2C_ISR_STOPF
00351 #define  SMBUS_FLAG_TC                          I2C_ISR_TC
00352 #define  SMBUS_FLAG_TCR                         I2C_ISR_TCR
00353 #define  SMBUS_FLAG_BERR                        I2C_ISR_BERR
00354 #define  SMBUS_FLAG_ARLO                        I2C_ISR_ARLO
00355 #define  SMBUS_FLAG_OVR                         I2C_ISR_OVR
00356 #define  SMBUS_FLAG_PECERR                      I2C_ISR_PECERR
00357 #define  SMBUS_FLAG_TIMEOUT                     I2C_ISR_TIMEOUT
00358 #define  SMBUS_FLAG_ALERT                       I2C_ISR_ALERT
00359 #define  SMBUS_FLAG_BUSY                        I2C_ISR_BUSY
00360 #define  SMBUS_FLAG_DIR                         I2C_ISR_DIR
00361 /**
00362   * @}
00363   */
00364
00365 /**
00366   * @}
00367   */
00368
00369 /* Exported macros ------------------------------------------------------------*/
00370 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
00371   * @{
00372   */
00373
00374 /** @brief  Reset SMBUS handle state.
00375   * @param  __HANDLE__: specifies the SMBUS Handle.
00376   * @retval None
00377   */
00378 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)      ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
00379
00380 /** @brief  Enable the specified SMBUS interrupts.
00381   * @param  __HANDLE__: specifies the SMBUS Handle.
00382   * @param  __INTERRUPT__: specifies the interrupt source to enable.
00383   *        This parameter can be one of the following values:
00384   *            @arg SMBUS_IT_ERRI: Errors interrupt enable
00385   *            @arg SMBUS_IT_TCI: Transfer complete interrupt enable
00386   *            @arg SMBUS_IT_STOPI: STOP detection interrupt enable
00387   *            @arg SMBUS_IT_NACKI: NACK received interrupt enable
00388   *            @arg SMBUS_IT_ADDRI: Address match interrupt enable
00389   *            @arg SMBUS_IT_RXI: RX interrupt enable
00390   *            @arg SMBUS_IT_TXI: TX interrupt enable
00391   *
00392   * @retval None
00393   */
00394 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
00395
00396 /** @brief  Disable the specified SMBUS interrupts.
00397   * @param  __HANDLE__: specifies the SMBUS Handle.
00398   * @param  __INTERRUPT__: specifies the interrupt source to disable.
00399   *        This parameter can be one of the following values:
00400   *            @arg SMBUS_IT_ERRI: Errors interrupt enable
00401   *            @arg SMBUS_IT_TCI: Transfer complete interrupt enable
00402   *            @arg SMBUS_IT_STOPI: STOP detection interrupt enable
00403   *            @arg SMBUS_IT_NACKI: NACK received interrupt enable
00404   *            @arg SMBUS_IT_ADDRI: Address match interrupt enable
00405   *            @arg SMBUS_IT_RXI: RX interrupt enable
00406   *            @arg SMBUS_IT_TXI: TX interrupt enable
00407   *
00408   * @retval None
00409   */
00410 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
00411
00412 /** @brief  Check whether the specified SMBUS interrupt source is enabled or not.
00413   * @param  __HANDLE__: specifies the SMBUS Handle.
00414   * @param  __INTERRUPT__: specifies the SMBUS interrupt source to check.
00415   *          This parameter can be one of the following values:
00416   *            @arg SMBUS_IT_ERRI: Errors interrupt enable
00417   *            @arg SMBUS_IT_TCI: Transfer complete interrupt enable
00418   *            @arg SMBUS_IT_STOPI: STOP detection interrupt enable
00419   *            @arg SMBUS_IT_NACKI: NACK received interrupt enable
00420   *            @arg SMBUS_IT_ADDRI: Address match interrupt enable
00421   *            @arg SMBUS_IT_RXI: RX interrupt enable
00422   *            @arg SMBUS_IT_TXI: TX interrupt enable
00423   *
00424   * @retval The new state of __IT__ (TRUE or FALSE).
00425   */
00426 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00427
00428 /** @brief  Check whether the specified SMBUS flag is set or not.
00429   * @param  __HANDLE__: specifies the SMBUS Handle.
00430   * @param  __FLAG__: specifies the flag to check.
00431   *        This parameter can be one of the following values:
00432   *            @arg SMBUS_FLAG_TXE:     Transmit data register empty
00433   *            @arg SMBUS_FLAG_TXIS:    Transmit interrupt status
00434   *            @arg SMBUS_FLAG_RXNE:    Receive data register not empty
00435   *            @arg SMBUS_FLAG_ADDR:    Address matched (slave mode)
00436   *            @arg SMBUS_FLAG_AF:      NACK received flag
00437   *            @arg SMBUS_FLAG_STOPF:   STOP detection flag
00438   *            @arg SMBUS_FLAG_TC:      Transfer complete (master mode)
00439   *            @arg SMBUS_FLAG_TCR:     Transfer complete reload
00440   *            @arg SMBUS_FLAG_BERR:    Bus error
00441   *            @arg SMBUS_FLAG_ARLO:    Arbitration lost
00442   *            @arg SMBUS_FLAG_OVR:     Overrun/Underrun
00443   *            @arg SMBUS_FLAG_PECERR:  PEC error in reception
00444   *            @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag
00445   *            @arg SMBUS_FLAG_ALERT:   SMBus alert
00446   *            @arg SMBUS_FLAG_BUSY:    Bus busy
00447   *            @arg SMBUS_FLAG_DIR:     Transfer direction (slave mode)
00448   *
00449   * @retval The new state of __FLAG__ (TRUE or FALSE).
00450   */
00451 #define SMBUS_FLAG_MASK  (0x0001FFFFU)
00452 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
00453
00454 /** @brief  Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
00455   * @param  __HANDLE__: specifies the SMBUS Handle.
00456   * @param  __FLAG__: specifies the flag to clear.
00457   *          This parameter can be any combination of the following values:
00458   *            @arg SMBUS_FLAG_ADDR:    Address matched (slave mode)
00459   *            @arg SMBUS_FLAG_AF:      NACK received flag
00460   *            @arg SMBUS_FLAG_STOPF:   STOP detection flag
00461   *            @arg SMBUS_FLAG_BERR:    Bus error
00462   *            @arg SMBUS_FLAG_ARLO:    Arbitration lost
00463   *            @arg SMBUS_FLAG_OVR:     Overrun/Underrun
00464   *            @arg SMBUS_FLAG_PECERR:  PEC error in reception
00465   *            @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag
00466   *            @arg SMBUS_FLAG_ALERT:   SMBus alert
00467   *
00468   * @retval None
00469   */
00470 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00471
00472 /** @brief  Enable the specified SMBUS peripheral.
00473   * @param  __HANDLE__: specifies the SMBUS Handle.
00474   * @retval None
00475   */
00476 #define __HAL_SMBUS_ENABLE(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00477
00478 /** @brief  Disable the specified SMBUS peripheral.
00479   * @param  __HANDLE__: specifies the SMBUS Handle.
00480   * @retval None
00481   */
00482 #define __HAL_SMBUS_DISABLE(__HANDLE__)                 (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00483
00484 /** @brief  Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
00485   * @param  __HANDLE__: specifies the SMBUS Handle.
00486   * @retval None
00487   */
00488 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__)           (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
00489
00490 /**
00491   * @}
00492   */
00493
00494
00495 /* Private constants ---------------------------------------------------------*/
00496
00497 /* Private macros ------------------------------------------------------------*/
00498 /** @defgroup SMBUS_Private_Macro SMBUS Private Macros
00499   * @{
00500   */
00501
00502 #define IS_SMBUS_ANALOG_FILTER(FILTER)                  (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
00503                                                           ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
00504
00505 #define IS_SMBUS_ADDRESSING_MODE(MODE)                  (((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
00506                                                           ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
00507
00508 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS)                  (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
00509                                                           ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
00510
00511 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK)                (((MASK) == SMBUS_OA2_NOMASK)    || \
00512                                                          ((MASK) == SMBUS_OA2_MASK01)    || \
00513                                                          ((MASK) == SMBUS_OA2_MASK02)    || \
00514                                                          ((MASK) == SMBUS_OA2_MASK03)    || \
00515                                                          ((MASK) == SMBUS_OA2_MASK04)    || \
00516                                                          ((MASK) == SMBUS_OA2_MASK05)    || \
00517                                                          ((MASK) == SMBUS_OA2_MASK06)    || \
00518                                                          ((MASK) == SMBUS_OA2_MASK07))
00519
00520 #define IS_SMBUS_GENERAL_CALL(CALL)                     (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
00521                                                          ((CALL) == SMBUS_GENERALCALL_ENABLE))
00522
00523 #define IS_SMBUS_NO_STRETCH(STRETCH)                    (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
00524                                                          ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
00525
00526 #define IS_SMBUS_PEC(PEC)                               (((PEC) == SMBUS_PEC_DISABLE) || \
00527                                                           ((PEC) == SMBUS_PEC_ENABLE))
00528
00529 #define IS_SMBUS_PERIPHERAL_MODE(MODE)                  (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)    || \
00530                                                           ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
00531                                                           ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
00532
00533 #define IS_SMBUS_TRANSFER_MODE(MODE)                    (((MODE) == SMBUS_RELOAD_MODE)                           || \
00534                                                           ((MODE) == SMBUS_AUTOEND_MODE)                         || \
00535                                                           ((MODE) == SMBUS_SOFTEND_MODE)                         || \
00536                                                           ((MODE) == SMBUS_SENDPEC_MODE)                         || \
00537                                                           ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
00538                                                           ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
00539                                                           ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
00540                                                           ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
00541
00542
00543 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST)              (((REQUEST) == SMBUS_GENERATE_STOP)              || \
00544                                                           ((REQUEST) == SMBUS_GENERATE_START_READ)       || \
00545                                                           ((REQUEST) == SMBUS_GENERATE_START_WRITE)      || \
00546                                                           ((REQUEST) == SMBUS_NO_STARTSTOP))
00547
00548
00549 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)      (((REQUEST) == SMBUS_FIRST_FRAME)                        || \
00550                                                           ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
00551                                                           ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
00552                                                           ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
00553                                                           ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
00554                                                           ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)               || \
00555                                                           IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
00556
00557 #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)                || \
00558                                                           ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)       || \
00559                                                           ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)              || \
00560                                                           ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
00561
00562 #define SMBUS_RESET_CR1(__HANDLE__)                       ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
00563 #define SMBUS_RESET_CR2(__HANDLE__)                       ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
00564
00565 #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__)     (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
00566                                                                   (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
00567
00568 #define SMBUS_GET_ADDR_MATCH(__HANDLE__)                (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)
00569 #define SMBUS_GET_DIR(__HANDLE__)                       (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
00570 #define SMBUS_GET_STOP_MODE(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
00571 #define SMBUS_GET_PEC_MODE(__HANDLE__)                  ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
00572 #define SMBUS_GET_ALERT_ENABLED(__HANDLE__)             ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
00573
00574 #define SMBUS_GET_ISR_REG(__HANDLE__)                   ((__HANDLE__)->Instance->ISR)
00575 #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__)             ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
00576
00577 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1)                         ((ADDRESS1) <= 0x000003FFU)
00578 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2)                         ((ADDRESS2) <= (uint16_t)0x00FFU)
00579
00580 /**
00581   * @}
00582   */
00583
00584 /* Exported functions --------------------------------------------------------*/
00585 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
00586   * @{
00587   */
00588
00589 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
00590  * @{
00591  */
00592
00593 /* Initialization and de-initialization functions  **********************************/
00594 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
00595 HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
00596 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
00597 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
00598
00599 /**
00600   * @}
00601   */
00602
00603 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
00604  * @{
00605  */
00606
00607 /* IO operation functions  *****************************************************/
00608 /** @addtogroup Blocking_mode_Polling Blocking mode Polling
00609  * @{
00610  */
00611 /******* Blocking mode: Polling */
00612 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
00613 /**
00614   * @}
00615   */
00616
00617 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
00618  * @{
00619  */
00620 /******* Non-Blocking mode: Interrupt */
00621 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00622 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00623 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
00624 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00625 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00626
00627 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
00628 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
00629 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
00630 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
00631 /**
00632   * @}
00633   */
00634
00635 /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00636  * @{
00637  */
00638 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
00639 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
00640 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
00641 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00642 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00643 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00644 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00645 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
00646 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00647 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
00648
00649 /**
00650   * @}
00651   */
00652
00653 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
00654  *  @{
00655  */
00656
00657 /* Peripheral State and Errors functions  **************************************************/
00658 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
00659 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
00660
00661 /**
00662   * @}
00663   */
00664
00665 /**
00666   * @}
00667   */
00668
00669 /* Private Functions ---------------------------------------------------------*/
00670 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions
00671   * @{
00672   */
00673 /* Private functions are defined in stm32h7xx_hal_smbus.c file */
00674 /**
00675   * @}
00676   */
00677
00678 /**
00679   * @}
00680   */
00681
00682 /**
00683   * @}
00684   */
00685
00686 /**
00687   * @}
00688   */
00689 #ifdef __cplusplus
00690 }
00691 #endif
00692
00693
00694 #endif /* __STM32H7xx_HAL_SMBUS_H */
00695
00696 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_spdifrx.c Source File

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stm32h7xx_hal_spdifrx.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_spdifrx.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the SPDIFRX audio interface:
00009   *           + Initialization and Configuration
00010   *           + Data transfers functions
00011   *           + DMA transfers management
00012   *           + Interrupts and flags management
00013   @verbatim
00014  ===============================================================================
00015                   ##### How to use this driver #####
00016  ===============================================================================
00017  [..]
00018     The SPDIFRX HAL driver can be used as follow:
00019
00020     (#) Declare SPDIFRX_HandleTypeDef handle structure.
00021     (#) Initialize the SPDIFRX low level resources by implement the HAL_SPDIFRX_MspInit() API:
00022         (##) Enable the SPDIFRX interface clock.
00023         (##) SPDIFRX pins configuration:
00024             (+++) Enable the clock for the SPDIFRX GPIOs.
00025             (+++) Configure these SPDIFRX pins as alternate function pull-up.
00026         (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveControlFlow_IT() and HAL_SPDIFRX_ReceiveDataFlow_IT() API's).
00027             (+++) Configure the SPDIFRX interrupt priority.
00028             (+++) Enable the NVIC SPDIFRX IRQ handle.
00029         (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveControlFlow_DMA() API's).
00030             (+++) Declare a DMA handle structure for the reception of the Data Flow channel.
00031             (+++) Declare a DMA handle structure for the reception of the Control Flow channel.
00032             (+++) Enable the DMAx interface clock.
00033             (+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters.
00034             (+++) Configure the DMA Channel.
00035             (+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle.
00036             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
00037                 DMA CtrlRx/DataRx channel.
00038
00039    (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits
00040        using HAL_SPDIFRX_Init() function.
00041
00042    -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros
00043        __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process.
00044    -@- Make sure that ck_spdif clock is configured.
00045
00046    (#) Three operation modes are available within this driver :
00047
00048    *** Polling mode for reception operation (for debug purpose) ***
00049    ================================================================
00050    [..]
00051      (+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow()
00052          (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveControlFlow()
00053
00054    *** Interrupt mode for reception operation ***
00055    =========================================
00056    [..]
00057      (+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT()
00058          (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveControlFlow_IT()
00059      (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
00060          add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
00061      (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
00062          add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
00063      (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
00064          add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
00065
00066    *** DMA mode for reception operation ***
00067    ========================================
00068    [..]
00069      (+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA()
00070          (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveControlFlow_DMA()
00071      (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
00072          add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
00073      (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
00074          add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
00075      (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
00076          add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
00077      (+) Stop the DMA Transfer using HAL_SPDIFRX_DMAStop()
00078
00079    *** SPDIFRX HAL driver macros list ***
00080    =============================================
00081    [..]
00082      Below the list of most used macros in USART HAL driver.
00083       (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State)
00084       (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State)
00085       (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State)
00086       (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts
00087       (+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts
00088       (+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not.
00089
00090     [..]
00091       (@) You can refer to the SPDIFRX HAL driver header file for more useful macros
00092
00093   @endverbatim
00094   ******************************************************************************
00095   * @attention
00096   *
00097   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00098   *
00099   * Redistribution and use in source and binary forms, with or without modification,
00100   * are permitted provided that the following conditions are met:
00101   *   1. Redistributions of source code must retain the above copyright notice,
00102   *      this list of conditions and the following disclaimer.
00103   *   2. Redistributions in binary form must reproduce the above copyright notice,
00104   *      this list of conditions and the following disclaimer in the documentation
00105   *      and/or other materials provided with the distribution.
00106   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00107   *      may be used to endorse or promote products derived from this software
00108   *      without specific prior written permission.
00109   *
00110   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00111   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00112   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00113   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00114   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00115   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00116   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00117   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00118   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00119   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00120   *
00121   ******************************************************************************
00122   */
00123
00124 /* Includes ------------------------------------------------------------------*/
00125 #include "stm32h7xx_hal.h"
00126
00127 /** @addtogroup STM32H7xx_HAL_Driver
00128   * @{
00129   */
00130 #if defined (SPDIFRX)
00131
00132 /** @defgroup SPDIFRX SPDIFRX
00133   * @brief SPDIFRX HAL module driver
00134   * @{
00135   */
00136
00137 #ifdef HAL_SPDIFRX_MODULE_ENABLED
00138
00139 /* Private typedef -----------------------------------------------------------*/
00140 /* Private define ------------------------------------------------------------*/
00141 #define SPDIFRX_TIMEOUT_VALUE  0xFFFFU
00142
00143 /* Private macro -------------------------------------------------------------*/
00144 /* Private variables ---------------------------------------------------------*/
00145 /* Private function prototypes -----------------------------------------------*/
00146 /** @addtogroup SPDIFRX_Private_Functions
00147   * @{
00148   */
00149 static void  SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma);
00150 static void  SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00151 static void  SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma);
00152 static void  SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma);
00153 static void  SPDIFRX_DMAError(DMA_HandleTypeDef *hdma);
00154 static void  SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
00155 static void  SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
00156 static HAL_StatusTypeDef  SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart);
00157 /**
00158   * @}
00159   */
00160 /* Exported functions ---------------------------------------------------------*/
00161
00162 /** @defgroup SPDIFRX_Exported_Functions SPDIFRX Exported Functions
00163   * @{
00164   */
00165
00166 /** @defgroup  SPDIFRX_Exported_Functions_Group1 Initialization and de-initialization functions
00167   *  @brief    Initialization and Configuration functions
00168   *
00169   @verbatim
00170   ===============================================================================
00171   ##### Initialization and de-initialization functions #####
00172   ===============================================================================
00173   [..]  This subsection provides a set of functions allowing to initialize and
00174         de-initialize the SPDIFRX peripheral:
00175
00176   (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures
00177       all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00178
00179   (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with
00180       the selected configuration:
00181   (++) Input Selection (IN0, IN1,...)
00182   (++) Maximum allowed re-tries during synchronization phase
00183   (++) Wait for activity on SPDIF selected input
00184   (++) Channel status selection (from channel A or B)
00185   (++) Data format (LSB, MSB, ...)
00186   (++) Stereo mode
00187   (++) User bits masking (PT,C,U,V,...)
00188
00189   (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration
00190       of the selected SPDIFRXx peripheral.
00191   @endverbatim
00192   * @{
00193   */
00194
00195 /**
00196   * @brief Initializes the SPDIFRX according to the specified parameters
00197   *        in the SPDIFRX_InitTypeDef and create the associated handle.
00198   * @param hspdif: SPDIFRX handle
00199   * @retval HAL status
00200   */
00201 HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
00202 {
00203   uint32_t tmpreg = 0;
00204
00205   /* Check the SPDIFRX handle allocation */
00206   if(hspdif == NULL)
00207   {
00208     return HAL_ERROR;
00209   }
00210
00211   /* Check the SPDIFRX parameters */
00212   assert_param(IS_STEREO_MODE(hspdif->Init.StereoMode));
00213   assert_param(IS_SPDIFRX_INPUT_SELECT(hspdif->Init.InputSelection));
00214   assert_param(IS_SPDIFRX_MAX_RETRIES(hspdif->Init.Retries));
00215   assert_param(IS_SPDIFRX_WAIT_FOR_ACTIVITY(hspdif->Init.WaitForActivity));
00216   assert_param(IS_SPDIFRX_CHANNEL(hspdif->Init.ChannelSelection));
00217   assert_param(IS_SPDIFRX_DATA_FORMAT(hspdif->Init.DataFormat));
00218   assert_param(IS_PREAMBLE_TYPE_MASK(hspdif->Init.PreambleTypeMask));
00219   assert_param(IS_CHANNEL_STATUS_MASK(hspdif->Init.ChannelStatusMask));
00220   assert_param(IS_VALIDITY_MASK(hspdif->Init.ValidityBitMask));
00221   assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask));
00222
00223   if(hspdif->State == HAL_SPDIFRX_STATE_RESET)
00224   {
00225     /* Allocate lock resource and initialize it */
00226     hspdif->Lock = HAL_UNLOCKED;
00227     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00228     HAL_SPDIFRX_MspInit(hspdif);
00229   }
00230
00231   /* SPDIFRX peripheral state is BUSY*/
00232   hspdif->State = HAL_SPDIFRX_STATE_BUSY;
00233
00234   /* Disable SPDIFRX interface (IDLE State) */
00235   __HAL_SPDIFRX_IDLE(hspdif);
00236
00237   /* Reset the old SPDIFRX CR configuration */
00238   tmpreg = hspdif->Instance->CR;
00239
00240   tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO  | SPDIFRX_CR_DRFMT  | SPDIFRX_CR_PMSK |
00241               SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK  |
00242               SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA | SPDIFRX_CR_INSEL);
00243
00244   /* Sets the new configuration of the SPDIFRX peripheral */
00245   tmpreg |= ((uint16_t) hspdif->Init.StereoMode |
00246              hspdif->Init.InputSelection |
00247              hspdif->Init.Retries |
00248              hspdif->Init.WaitForActivity |
00249              hspdif->Init.ChannelSelection |
00250              hspdif->Init.DataFormat |
00251              hspdif->Init.PreambleTypeMask |
00252              hspdif->Init.ChannelStatusMask |
00253              hspdif->Init.ValidityBitMask |
00254              hspdif->Init.ParityErrorMask);
00255
00256   hspdif->Instance->CR = tmpreg;
00257
00258   hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00259
00260   /* SPDIFRX peripheral state is READY*/
00261   hspdif->State = HAL_SPDIFRX_STATE_READY;
00262
00263   return HAL_OK;
00264 }
00265
00266 /**
00267   * @brief DeInitializes the SPDIFRX peripheral
00268   * @param hspdif: SPDIFRX handle
00269   * @retval HAL status
00270   */
00271 HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif)
00272 {
00273   /* Check the SPDIFRX handle allocation */
00274   if(hspdif == NULL)
00275   {
00276     return HAL_ERROR;
00277   }
00278
00279   /* Check the parameters */
00280   assert_param(IS_SPDIFRX_ALL_INSTANCE(hspdif->Instance));
00281
00282   hspdif->State = HAL_SPDIFRX_STATE_BUSY;
00283
00284   /* Disable SPDIFRX interface (IDLE state) */
00285   __HAL_SPDIFRX_IDLE(hspdif);
00286
00287   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00288   HAL_SPDIFRX_MspDeInit(hspdif);
00289
00290   hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00291
00292   /* SPDIFRX peripheral state is RESET*/
00293   hspdif->State = HAL_SPDIFRX_STATE_RESET;
00294
00295   /* Release Lock */
00296   __HAL_UNLOCK(hspdif);
00297
00298   return HAL_OK;
00299 }
00300
00301 /**
00302   * @brief SPDIFRX MSP Init
00303   * @param hspdif: SPDIFRX handle
00304   * @retval None
00305   */
00306 __weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif)
00307 {
00308   /* Prevent unused argument(s) compilation warning */
00309   UNUSED(hspdif);
00310
00311   /* NOTE : This function Should not be modified, when the callback is needed,
00312   the HAL_SPDIFRX_MspInit could be implemented in the user file
00313   */
00314 }
00315
00316 /**
00317   * @brief SPDIFRX MSP DeInit
00318   * @param hspdif: SPDIFRX handle
00319   * @retval None
00320   */
00321 __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif)
00322 {
00323   /* Prevent unused argument(s) compilation warning */
00324   UNUSED(hspdif);
00325
00326   /* NOTE : This function Should not be modified, when the callback is needed,
00327   the HAL_SPDIFRX_MspDeInit could be implemented in the user file
00328   */
00329 }
00330
00331 /**
00332   * @brief Sets the SPDIFRX  dtat format according to the specified parameters
00333   *        in the SPDIFRX_InitTypeDef.
00334   * @param hspdif: SPDIFRX handle
00335   * @param sDataFormat: SPDIFRX data format
00336   * @retval HAL status
00337   */
00338 HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef  sDataFormat)
00339 {
00340   uint32_t tmpreg = 0;
00341
00342   /* Check the SPDIFRX handle allocation */
00343   if(hspdif == NULL)
00344   {
00345     return HAL_ERROR;
00346   }
00347
00348   /* Check the SPDIFRX parameters */
00349   assert_param(IS_STEREO_MODE(sDataFormat.StereoMode));
00350   assert_param(IS_SPDIFRX_DATA_FORMAT(sDataFormat.DataFormat));
00351   assert_param(IS_PREAMBLE_TYPE_MASK(sDataFormat.PreambleTypeMask));
00352   assert_param(IS_CHANNEL_STATUS_MASK(sDataFormat.ChannelStatusMask));
00353   assert_param(IS_VALIDITY_MASK(sDataFormat.ValidityBitMask));
00354   assert_param(IS_PARITY_ERROR_MASK(sDataFormat.ParityErrorMask));
00355
00356   /* Reset the old SPDIFRX CR configuration */
00357   tmpreg = hspdif->Instance->CR;
00358
00359   if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) &&
00360      (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) ||
00361       ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode)))
00362   {
00363     return HAL_ERROR;
00364   }
00365
00366   tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO  | SPDIFRX_CR_DRFMT  | SPDIFRX_CR_PMSK |
00367               SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK);
00368
00369   /* Sets the new configuration of the SPDIFRX peripheral */
00370   tmpreg |= ((uint16_t) sDataFormat.StereoMode |
00371              sDataFormat.DataFormat |
00372              sDataFormat.PreambleTypeMask |
00373              sDataFormat.ChannelStatusMask |
00374              sDataFormat.ValidityBitMask |
00375              sDataFormat.ParityErrorMask);
00376
00377   hspdif->Instance->CR = tmpreg;
00378
00379   return HAL_OK;
00380 }
00381
00382 /**
00383   * @}
00384   */
00385
00386 /** @defgroup SPDIFRX_Exported_Functions_Group2 IO operation functions
00387   *  @brief Data transfers functions
00388   *
00389 @verbatim
00390 ===============================================================================
00391                      ##### IO operation functions #####
00392 ===============================================================================
00393     [..]
00394     This subsection provides a set of functions allowing to manage the SPDIFRX data
00395     transfers.
00396
00397     (#) There is two mode of transfer:
00398         (++) Blocking mode : The communication is performed in the polling mode.
00399              The status of all data processing is returned by the same function
00400              after finishing transfer.
00401         (++) No-Blocking mode : The communication is performed using Interrupts
00402              or DMA. These functions return the status of the transfer start-up.
00403              The end of the data processing will be indicated through the
00404              dedicated SPDIFRX IRQ when using Interrupt mode or the DMA IRQ when
00405              using DMA mode.
00406
00407     (#) Blocking mode functions are :
00408         (++) HAL_SPDIFRX_ReceiveDataFlow()
00409         (++) HAL_SPDIFRX_ReceiveControlFlow()
00410                 (+@) Do not use blocking mode to receive both control and data flow at the same time.
00411
00412     (#) No-Blocking mode functions with Interrupt are :
00413         (++) HAL_SPDIFRX_ReceiveControlFlow_IT()
00414         (++) HAL_SPDIFRX_ReceiveDataFlow_IT()
00415
00416     (#) No-Blocking mode functions with DMA are :
00417         (++) HAL_SPDIFRX_ReceiveControlFlow_DMA()
00418         (++) HAL_SPDIFRX_ReceiveDataFlow_DMA()
00419
00420     (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
00421         (++) HAL_SPDIFRX_RxCpltCallback()
00422         (++) HAL_SPDIFRX_ErrorCallback()
00423
00424 @endverbatim
00425 * @{
00426 */
00427
00428
00429 /**
00430   * @brief  Receives an amount of data (Data Flow) in blocking mode.
00431   * @param  hspdif: pointer to SPDIFRX_HandleTypeDef structure that contains
00432   *                 the configuration information for SPDIFRX module.
00433   * @param  pData: Pointer to data buffer
00434   * @param  Size: Amount of data to be received
00435   * @param  Timeout: Timeout duration
00436   * @retval HAL status
00437   */
00438 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
00439 {
00440   uint32_t tickstart = 0U;
00441
00442   if((pData == NULL ) || (Size == 0U))
00443   {
00444     return  HAL_ERROR;
00445   }
00446
00447   if(hspdif->State == HAL_SPDIFRX_STATE_READY)
00448   {
00449     /* Process Locked */
00450     __HAL_LOCK(hspdif);
00451
00452     hspdif->State = HAL_SPDIFRX_STATE_BUSY;
00453
00454     /* Start synchronisation */
00455     __HAL_SPDIFRX_SYNC(hspdif);
00456
00457     /* Get tick */
00458     tickstart = HAL_GetTick();
00459
00460     /* Wait until SYNCD flag is set */
00461     if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)
00462     {
00463       return HAL_TIMEOUT;
00464     }
00465
00466     /* Start reception */
00467     __HAL_SPDIFRX_RCV(hspdif);
00468
00469     /* Receive data flow */
00470     while(Size > 0U)
00471     {
00472       /* Get tick */
00473       tickstart = HAL_GetTick();
00474
00475       /* Wait until RXNE flag is set */
00476       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
00477       {
00478         return HAL_TIMEOUT;
00479       }
00480
00481       (*pData++) = hspdif->Instance->DR;
00482       Size--;
00483     }
00484
00485     /* SPDIFRX ready */
00486     hspdif->State = HAL_SPDIFRX_STATE_READY;
00487
00488     /* Process Unlocked */
00489     __HAL_UNLOCK(hspdif);
00490
00491     return HAL_OK;
00492   }
00493   else
00494   {
00495     return HAL_BUSY;
00496   }
00497 }
00498
00499 /**
00500   * @brief  Receives an amount of data (Control Flow) in blocking mode.
00501   * @param  hspdif: pointer to a SPDIFRX_HandleTypeDef structure that contains
00502   *                 the configuration information for SPDIFRX module.
00503   * @param  pData: Pointer to data buffer
00504   * @param  Size: Amount of data to be received
00505   * @param  Timeout: Timeout duration
00506   * @retval HAL status
00507   */
00508 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
00509 {
00510   uint32_t tickstart = 0U;
00511
00512   if((pData == NULL ) || (Size == 0U))
00513   {
00514     return  HAL_ERROR;
00515   }
00516
00517   if(hspdif->State == HAL_SPDIFRX_STATE_READY)
00518   {
00519     /* Process Locked */
00520     __HAL_LOCK(hspdif);
00521
00522     hspdif->State = HAL_SPDIFRX_STATE_BUSY;
00523
00524     /* Start synchronization */
00525     __HAL_SPDIFRX_SYNC(hspdif);
00526
00527     /* Get tick */
00528     tickstart = HAL_GetTick();
00529
00530     /* Wait until SYNCD flag is set */
00531     if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)
00532     {
00533       return HAL_TIMEOUT;
00534     }
00535
00536     /* Start reception */
00537     __HAL_SPDIFRX_RCV(hspdif);
00538
00539     /* Receive control flow */
00540     while(Size > 0U)
00541     {
00542       /* Get tick */
00543       tickstart = HAL_GetTick();
00544
00545       /* Wait until CSRNE flag is set */
00546       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK)
00547       {
00548         return HAL_TIMEOUT;
00549       }
00550
00551       (*pData++) = hspdif->Instance->CSR;
00552       Size--;
00553     }
00554
00555     /* SPDIFRX ready */
00556     hspdif->State = HAL_SPDIFRX_STATE_READY;
00557
00558     /* Process Unlocked */
00559     __HAL_UNLOCK(hspdif);
00560
00561     return HAL_OK;
00562   }
00563   else
00564   {
00565     return HAL_BUSY;
00566   }
00567 }
00568
00569 /**
00570   * @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt
00571   * @param hspdif: SPDIFRX handle
00572   * @param pData: a 32-bit pointer to the Receive data buffer.
00573   * @param Size: number of data sample to be received .
00574   * @retval HAL status
00575   */
00576 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
00577 {
00578   uint32_t tickstart = 0U;
00579
00580   if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))
00581   {
00582     if((pData == NULL) || (Size == 0U))
00583     {
00584       return HAL_ERROR;
00585     }
00586
00587     /* Process Locked */
00588     __HAL_LOCK(hspdif);
00589
00590     hspdif->pRxBuffPtr = pData;
00591     hspdif->RxXferSize = Size;
00592     hspdif->RxXferCount = Size;
00593
00594     hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00595
00596     /* Check if a receive process is ongoing or not */
00597     hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
00598
00599
00600     /* Enable the SPDIFRX  PE Error Interrupt */
00601     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
00602
00603     /* Enable the SPDIFRX  OVR Error Interrupt */
00604     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
00605
00606     /* Process Unlocked */
00607     __HAL_UNLOCK(hspdif);
00608
00609     /* Enable the SPDIFRX RXNE interrupt */
00610     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE);
00611
00612     if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U))
00613     {
00614       /* Start synchronization */
00615       __HAL_SPDIFRX_SYNC(hspdif);
00616
00617       /* Get tick */
00618       tickstart = HAL_GetTick();
00619
00620       /* Wait until SYNCD flag is set */
00621       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)
00622       {
00623         return HAL_TIMEOUT;
00624       }
00625
00626       /* Start reception */
00627       __HAL_SPDIFRX_RCV(hspdif);
00628     }
00629
00630     return HAL_OK;
00631   }
00632   else
00633   {
00634     return HAL_BUSY;
00635   }
00636 }
00637
00638 /**
00639   * @brief Receive an amount of data (Control Flow) with Interrupt
00640   * @param hspdif: SPDIFRX handle
00641   * @param pData: a 32-bit pointer to the Receive data buffer.
00642   * @param Size: number of data sample (Control Flow) to be received :
00643   * @retval HAL status
00644   */
00645 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
00646 {
00647   uint32_t tickstart = 0U;
00648
00649   if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
00650   {
00651     if((pData == NULL ) || (Size == 0U))
00652     {
00653       return HAL_ERROR;
00654     }
00655
00656     /* Process Locked */
00657     __HAL_LOCK(hspdif);
00658
00659     hspdif->pCsBuffPtr = pData;
00660     hspdif->CsXferSize = Size;
00661     hspdif->CsXferCount = Size;
00662
00663     hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00664
00665     /* Check if a receive process is ongoing or not */
00666     hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
00667
00668
00669     /* Enable the SPDIFRX PE Error Interrupt */
00670     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
00671
00672     /* Enable the SPDIFRX OVR Error Interrupt */
00673     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
00674
00675     /* Process Unlocked */
00676     __HAL_UNLOCK(hspdif);
00677
00678     /* Enable the SPDIFRX CSRNE interrupt */
00679     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
00680
00681     if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U))
00682     {
00683       /* Start synchronization */
00684       __HAL_SPDIFRX_SYNC(hspdif);
00685
00686       /* Get tick */
00687       tickstart = HAL_GetTick();
00688
00689       /* Wait until SYNCD flag is set */
00690       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)
00691       {
00692         return HAL_TIMEOUT;
00693       }
00694
00695       /* Start reception */
00696       __HAL_SPDIFRX_RCV(hspdif);
00697     }
00698
00699     return HAL_OK;
00700   }
00701   else
00702   {
00703     return HAL_BUSY;
00704   }
00705 }
00706
00707 /**
00708   * @brief Receive an amount of data (Data Flow) mode with DMA
00709   * @param hspdif: SPDIFRX handle
00710   * @param pData: a 32-bit pointer to the Receive data buffer.
00711   * @param Size: number of data sample to be received :
00712   * @retval HAL status
00713   */
00714 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
00715 {
00716   uint32_t tickstart = 0U;
00717
00718   if((pData == NULL) || (Size == 0U))
00719   {
00720     return  HAL_ERROR;
00721   }
00722
00723   if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))
00724   {
00725     hspdif->pRxBuffPtr = pData;
00726     hspdif->RxXferSize = Size;
00727     hspdif->RxXferCount = Size;
00728
00729     /* Process Locked */
00730     __HAL_LOCK(hspdif);
00731
00732     hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00733     hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
00734
00735     /* Set the SPDIFRX Rx DMA Half transfer complete callback */
00736     hspdif->hdmaDrRx->XferHalfCpltCallback = SPDIFRX_DMARxHalfCplt;
00737
00738     /* Set the SPDIFRX Rx DMA transfer complete callback */
00739     hspdif->hdmaDrRx->XferCpltCallback = SPDIFRX_DMARxCplt;
00740
00741     /* Set the DMA error callback */
00742     hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError;
00743
00744     /* Enable the DMA request */
00745     HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size);
00746
00747     /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/
00748     hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN;
00749
00750     if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U))
00751     {
00752       /* Start synchronization */
00753       __HAL_SPDIFRX_SYNC(hspdif);
00754
00755       /* Get tick */
00756       tickstart = HAL_GetTick();
00757
00758       /* Wait until SYNCD flag is set */
00759       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)
00760       {
00761         return HAL_TIMEOUT;
00762       }
00763
00764       /* Start reception */
00765       __HAL_SPDIFRX_RCV(hspdif);
00766     }
00767
00768     /* Process Unlocked */
00769     __HAL_UNLOCK(hspdif);
00770
00771     return HAL_OK;
00772   }
00773   else
00774   {
00775     return HAL_BUSY;
00776   }
00777 }
00778
00779 /**
00780   * @brief Receive an amount of data (Control Flow) with DMA
00781   * @param hspdif: SPDIFRX handle
00782   * @param pData: a 32-bit pointer to the Receive data buffer.
00783   * @param Size: number of data (Control Flow) sample to be received :
00784   * @retval HAL status
00785   */
00786 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
00787 {
00788   uint32_t tickstart = 0U;
00789
00790   if((pData == NULL) || (Size == 0U))
00791   {
00792     return  HAL_ERROR;
00793   }
00794
00795   if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
00796   {
00797     hspdif->pCsBuffPtr = pData;
00798     hspdif->CsXferSize = Size;
00799     hspdif->CsXferCount = Size;
00800
00801     /* Process Locked */
00802     __HAL_LOCK(hspdif);
00803
00804     hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00805     hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
00806
00807     /* Set the SPDIFRX Rx DMA Half transfer complete callback */
00808     hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt;
00809
00810     /* Set the SPDIFRX Rx DMA transfer complete callback */
00811     hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt;
00812
00813     /* Set the DMA error callback */
00814     hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError;
00815
00816     /* Enable the DMA request */
00817     HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size);
00818
00819     /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/
00820     hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN;
00821
00822     if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U))
00823     {
00824       /* Start synchronization */
00825       __HAL_SPDIFRX_SYNC(hspdif);
00826
00827       /* Get tick */
00828       tickstart = HAL_GetTick();
00829
00830       /* Wait until SYNCD flag is set */
00831       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)
00832       {
00833         return HAL_TIMEOUT;
00834       }
00835
00836       /* Start reception */
00837       __HAL_SPDIFRX_RCV(hspdif);
00838     }
00839
00840     /* Process Unlocked */
00841     __HAL_UNLOCK(hspdif);
00842
00843     return HAL_OK;
00844   }
00845   else
00846   {
00847     return HAL_BUSY;
00848   }
00849 }
00850
00851 /**
00852   * @brief stop the audio stream receive from the Media.
00853   * @param hspdif: SPDIFRX handle
00854   * @retval None
00855   */
00856 HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif)
00857 {
00858   /* Process Locked */
00859   __HAL_LOCK(hspdif);
00860
00861   /* Disable the SPDIFRX DMA requests */
00862   hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
00863   hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
00864
00865   /* Disable the SPDIFRX DMA channel */
00866   __HAL_DMA_DISABLE(hspdif->hdmaDrRx);
00867   __HAL_DMA_DISABLE(hspdif->hdmaCsRx);
00868
00869   /* Disable SPDIFRX peripheral */
00870   __HAL_SPDIFRX_IDLE(hspdif);
00871
00872   hspdif->State = HAL_SPDIFRX_STATE_READY;
00873
00874   /* Process Unlocked */
00875   __HAL_UNLOCK(hspdif);
00876
00877   return HAL_OK;
00878 }
00879
00880 /**
00881   * @brief  This function handles SPDIFRX interrupt request.
00882   * @param  hspdif: SPDIFRX handle
00883   * @retval HAL status
00884   */
00885 void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)
00886 {
00887   /* SPDIFRX in mode Data Flow Reception ------------------------------------------------*/
00888   if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_RXNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_RXNE) != RESET))
00889   {
00890     __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE);
00891     SPDIFRX_ReceiveDataFlow_IT(hspdif);
00892   }
00893
00894   /* SPDIFRX in mode Control Flow Reception ------------------------------------------------*/
00895   if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_CSRNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_CSRNE) != RESET))
00896   {
00897     __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE);
00898     SPDIFRX_ReceiveControlFlow_IT(hspdif);
00899   }
00900
00901   /* SPDIFRX Overrun error interrupt occurred ---------------------------------*/
00902   if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_OVR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_OVRIE) != RESET))
00903   {
00904     __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_OVR);
00905
00906     /* Change the SPDIFRX error code */
00907     hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_OVR;
00908
00909     /* the transfer is not stopped */
00910     HAL_SPDIFRX_ErrorCallback(hspdif);
00911   }
00912
00913   /* SPDIFRX Parity error interrupt occurred ---------------------------------*/
00914   if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_PERR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_PERRIE) != RESET))
00915   {
00916     __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_PERR);
00917
00918     /* Change the SPDIFRX error code */
00919     hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_PE;
00920
00921     /* the transfer is not stopped */
00922     HAL_SPDIFRX_ErrorCallback(hspdif);
00923   }
00924 }
00925
00926 /**
00927   * @brief Rx Transfer (Data flow) half completed callbacks
00928   * @param hspdif: SPDIFRX handle
00929   * @retval None
00930   */
00931 __weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
00932 {
00933   /* Prevent unused argument(s) compilation warning */
00934   UNUSED(hspdif);
00935
00936   /* NOTE : This function Should not be modified, when the callback is needed,
00937             the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
00938   */
00939 }
00940
00941 /**
00942   * @brief Rx Transfer (Data flow) completed callbacks
00943   * @param hspdif: SPDIFRX handle
00944   * @retval None
00945   */
00946 __weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
00947 {
00948   /* Prevent unused argument(s) compilation warning */
00949   UNUSED(hspdif);
00950
00951   /* NOTE : This function Should not be modified, when the callback is needed,
00952             the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
00953   */
00954 }
00955
00956 /**
00957   * @brief Rx (Control flow) Transfer half completed callbacks
00958   * @param hspdif: SPDIFRX handle
00959   * @retval None
00960   */
00961 __weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
00962 {
00963   /* Prevent unused argument(s) compilation warning */
00964   UNUSED(hspdif);
00965
00966   /* NOTE : This function Should not be modified, when the callback is needed,
00967             the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
00968   */
00969 }
00970
00971 /**
00972   * @brief Rx Transfer (Control flow) completed callbacks
00973   * @param hspdif: SPDIFRX handle
00974   * @retval None
00975   */
00976 __weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
00977 {
00978   /* Prevent unused argument(s) compilation warning */
00979   UNUSED(hspdif);
00980
00981   /* NOTE : This function Should not be modified, when the callback is needed,
00982             the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
00983   */
00984 }
00985
00986 /**
00987   * @brief SPDIFRX error callbacks
00988   * @param hspdif: SPDIFRX handle
00989   * @retval None
00990   */
00991 __weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif)
00992 {
00993   /* Prevent unused argument(s) compilation warning */
00994   UNUSED(hspdif);
00995
00996   /* NOTE : This function Should not be modified, when the callback is needed,
00997             the HAL_SPDIFRX_ErrorCallback could be implemented in the user file
00998   */
00999 }
01000
01001 /**
01002   * @}
01003   */
01004
01005 /** @defgroup SPDIFRX_Exported_Functions_Group3 Peripheral State and Errors functions
01006   *  @brief   Peripheral State functions
01007   *
01008 @verbatim
01009 ===============================================================================
01010 ##### Peripheral State and Errors functions #####
01011 ===============================================================================
01012 [..]
01013 This subsection permit to get in run-time the status of the peripheral
01014 and the data flow.
01015
01016 @endverbatim
01017   * @{
01018   */
01019
01020 /**
01021   * @brief  Return the SPDIFRX state
01022   * @param  hspdif : SPDIFRX handle
01023   * @retval HAL state
01024   */
01025 HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif)
01026 {
01027   return hspdif->State;
01028 }
01029
01030 /**
01031   * @brief  Return the SPDIFRX error code
01032   * @param  hspdif : SPDIFRX handle
01033   * @retval SPDIFRX Error Code
01034   */
01035 uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif)
01036 {
01037   return hspdif->ErrorCode;
01038 }
01039
01040 /**
01041   * @}
01042   */
01043
01044 /**
01045   * @brief DMA SPDIFRX receive process (Data flow) complete callback
01046   * @param hdma : DMA handle
01047   * @retval None
01048   */
01049 static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)
01050 {
01051   SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01052
01053   /* Disable Rx DMA Request */
01054   if(hdma->Init.Mode != DMA_CIRCULAR)
01055   {
01056     hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
01057     hspdif->RxXferCount = 0;
01058     hspdif->State = HAL_SPDIFRX_STATE_READY;
01059   }
01060   HAL_SPDIFRX_RxCpltCallback(hspdif);
01061 }
01062
01063 /**
01064   * @brief DMA SPDIFRX receive process (Data flow) half complete callback
01065   * @param hdma : DMA handle
01066   * @retval None
01067   */
01068 static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01069 {
01070   SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01071
01072   HAL_SPDIFRX_RxHalfCpltCallback(hspdif);
01073 }
01074
01075
01076 /**
01077   * @brief DMA SPDIFRX receive process (Control flow) complete callback
01078   * @param hdma : DMA handle
01079   * @retval None
01080   */
01081 static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma)
01082 {
01083   SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01084
01085   /* Disable Cb DMA Request */
01086   hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
01087   hspdif->CsXferCount = 0;
01088
01089   hspdif->State = HAL_SPDIFRX_STATE_READY;
01090   HAL_SPDIFRX_CxCpltCallback(hspdif);
01091 }
01092
01093 /**
01094   * @brief DMA SPDIFRX receive process (Control flow) half complete callback
01095   * @param hdma : DMA handle
01096   * @retval None
01097   */
01098 static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma)
01099 {
01100   SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01101
01102   HAL_SPDIFRX_CxHalfCpltCallback(hspdif);
01103 }
01104
01105 /**
01106   * @brief DMA SPDIFRX communication error callback
01107   * @param hdma : DMA handle
01108   * @retval None
01109   */
01110 static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)
01111 {
01112   SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01113
01114   /* Disable Rx and Cb DMA Request */
01115   hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN));
01116   hspdif->RxXferCount = 0;
01117
01118   hspdif->State= HAL_SPDIFRX_STATE_READY;
01119
01120   /* Set the error code and execute error callback*/
01121   hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA;
01122   HAL_SPDIFRX_ErrorCallback(hspdif);
01123 }
01124
01125 /**
01126   * @brief Receive an amount of data (Data Flow) with Interrupt
01127   * @param hspdif: SPDIFRX handle
01128   * @retval None
01129   */
01130 static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
01131 {
01132   /* Receive data */
01133   (*hspdif->pRxBuffPtr++) = hspdif->Instance->DR;
01134   hspdif->RxXferCount--;
01135
01136   if(hspdif->RxXferCount == 0)
01137   {
01138     /* Disable RXNE/PE and OVR interrupts */
01139     __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE);
01140
01141     hspdif->State = HAL_SPDIFRX_STATE_READY;
01142
01143     /* Process Unlocked */
01144     __HAL_UNLOCK(hspdif);
01145
01146     HAL_SPDIFRX_RxCpltCallback(hspdif);
01147   }
01148 }
01149
01150 /**
01151   * @brief Receive an amount of data (Control Flow) with Interrupt
01152   * @param hspdif: SPDIFRX handle
01153   * @retval None
01154   */
01155 static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
01156 {
01157   /* Receive data */
01158   (*hspdif->pCsBuffPtr++) = hspdif->Instance->CSR;
01159   hspdif->CsXferCount--;
01160
01161   if(hspdif->CsXferCount == 0)
01162   {
01163     /* Disable CSRNE interrupt */
01164     __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
01165
01166     hspdif->State = HAL_SPDIFRX_STATE_READY;
01167
01168     /* Process Unlocked */
01169     __HAL_UNLOCK(hspdif);
01170
01171     HAL_SPDIFRX_CxCpltCallback(hspdif);
01172   }
01173 }
01174
01175 /**
01176   * @brief This function handles SPDIFRX Communication Timeout.
01177   * @param hspdif: SPDIFRX handle
01178   * @param Flag: Flag checked
01179   * @param Status: Value of the flag expected
01180   * @param Timeout: Duration of the timeout
01181   * @param tickstart: Tick start value
01182   * @retval HAL status
01183   */
01184 static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart)
01185 {
01186   /* Wait until flag is set */
01187   if(Status == RESET)
01188   {
01189     while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == RESET)
01190     {
01191       /* Check for the Timeout */
01192       if(Timeout != HAL_MAX_DELAY)
01193       {
01194         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01195         {
01196           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01197           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
01198           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
01199           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
01200           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
01201           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
01202           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
01203           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
01204
01205           hspdif->State= HAL_SPDIFRX_STATE_READY;
01206
01207           /* Process Unlocked */
01208           __HAL_UNLOCK(hspdif);
01209
01210           return HAL_TIMEOUT;
01211         }
01212       }
01213     }
01214   }
01215   else
01216   {
01217     while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) != RESET)
01218     {
01219       /* Check for the Timeout */
01220       if(Timeout != HAL_MAX_DELAY)
01221       {
01222         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01223         {
01224           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01225           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
01226           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
01227           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
01228           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
01229           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
01230           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
01231           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
01232
01233           hspdif->State= HAL_SPDIFRX_STATE_READY;
01234
01235           /* Process Unlocked */
01236           __HAL_UNLOCK(hspdif);
01237
01238           return HAL_TIMEOUT;
01239         }
01240       }
01241     }
01242   }
01243   return HAL_OK;
01244 }
01245
01246 /**
01247   * @}
01248   */
01249 #endif /* SPDIFRX */
01250 #endif /* HAL_SPDIFRX_MODULE_ENABLED */
01251 /**
01252   * @}
01253   */
01254
01255 /**
01256   * @}
01257   */
01258
01259 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_spdifrx.h Source File

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stm32h7xx_hal_spdifrx.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_spdifrx.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of SPDIFRX HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_SPDIFRX_H
00040 #define __STM32H7xx_HAL_SPDIFRX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052 #if defined (SPDIFRX)
00053
00054 /** @addtogroup SPDIFRX
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup SPDIFRX_Exported_Types SPDIFRX Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief SPDIFRX Init structure definition
00065   */
00066 typedef struct
00067 {
00068   uint32_t InputSelection;           /*!< Specifies the SPDIF input selection.
00069                                           This parameter can be a value of @ref SPDIFRX_Input_Selection */
00070
00071   uint32_t Retries;                  /*!< Specifies the Maximum allowed re-tries during synchronization phase.
00072                                           This parameter can be a value of @ref SPDIFRX_Max_Retries */
00073
00074   uint32_t WaitForActivity;          /*!< Specifies the wait for activity on SPDIF selected input.
00075                                           This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */
00076
00077   uint32_t ChannelSelection;         /*!< Specifies whether the control flow will take the channel status from channel A or B.
00078                                           This parameter can be a value of @ref SPDIFRX_Channel_Selection */
00079
00080   uint32_t DataFormat;               /*!< Specifies the Data samples format (LSB, MSB, ...).
00081                                           This parameter can be a value of @ref SPDIFRX_Data_Format */
00082
00083   uint32_t StereoMode;               /*!< Specifies whether the peripheral is in stereo or mono mode.
00084                                           This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
00085
00086   uint32_t PreambleTypeMask;          /*!< Specifies whether The preamble type bits are copied or not into the received frame.
00087                                                                                    This parameter can be a value of @ref SPDIFRX_PT_Mask */
00088
00089   uint32_t ChannelStatusMask;        /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
00090                                                                                   This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
00091
00092   uint32_t ValidityBitMask;          /*!< Specifies whether the validity bit is copied or not into the received frame.
00093                                                                                   This parameter can be a value of @ref SPDIFRX_V_Mask */
00094
00095   uint32_t ParityErrorMask;          /*!< Specifies whether the parity error bit is copied or not into the received frame.
00096                                                                                   This parameter can be a value of @ref SPDIFRX_PE_Mask */
00097
00098 } SPDIFRX_InitTypeDef;
00099
00100 /**
00101   * @brief SPDIFRX SetDataFormat structure definition
00102   */
00103 typedef struct
00104 {
00105   uint32_t DataFormat;               /*!< Specifies the Data samples format (LSB, MSB, ...).
00106                                           This parameter can be a value of @ref SPDIFRX_Data_Format */
00107
00108   uint32_t StereoMode;               /*!< Specifies whether the peripheral is in stereo or mono mode.
00109                                           This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
00110
00111   uint32_t PreambleTypeMask;          /*!< Specifies whether The preamble type bits are copied or not into the received frame.
00112                                                                                    This parameter can be a value of @ref SPDIFRX_PT_Mask */
00113
00114   uint32_t ChannelStatusMask;        /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
00115                                                                                   This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
00116
00117   uint32_t ValidityBitMask;          /*!< Specifies whether the validity bit is copied or not into the received frame.
00118                                                                                   This parameter can be a value of @ref SPDIFRX_V_Mask */
00119
00120   uint32_t ParityErrorMask;          /*!< Specifies whether the parity error bit is copied or not into the received frame.
00121                                                                                   This parameter can be a value of @ref SPDIFRX_PE_Mask */
00122
00123 } SPDIFRX_SetDataFormatTypeDef;
00124
00125 /**
00126   * @brief  HAL State structures definition
00127   */
00128 typedef enum
00129 {
00130   HAL_SPDIFRX_STATE_RESET      = 0x00U,  /*!< SPDIFRX not yet initialized or disabled                */
00131   HAL_SPDIFRX_STATE_READY      = 0x01U,  /*!< SPDIFRX initialized and ready for use                  */
00132   HAL_SPDIFRX_STATE_BUSY       = 0x02U,  /*!< SPDIFRX internal process is ongoing                    */
00133   HAL_SPDIFRX_STATE_BUSY_RX    = 0x03U,  /*!< SPDIFRX internal Data Flow RX process is ongoing       */
00134   HAL_SPDIFRX_STATE_BUSY_CX    = 0x04U,  /*!< SPDIFRX internal Control Flow RX process is ongoing    */
00135   HAL_SPDIFRX_STATE_ERROR      = 0x07U   /*!< SPDIFRX error state                                    */
00136 } HAL_SPDIFRX_StateTypeDef;
00137
00138 /**
00139   * @brief SPDIFRX handle Structure definition
00140   */
00141 typedef struct
00142 {
00143   SPDIFRX_TypeDef            *Instance;    /* SPDIFRX registers base address */
00144
00145   SPDIFRX_InitTypeDef        Init;         /* SPDIFRX communication parameters */
00146
00147   uint32_t                   *pRxBuffPtr;  /* Pointer to SPDIFRX Rx transfer buffer */
00148
00149   uint32_t                   *pCsBuffPtr;  /* Pointer to SPDIFRX Cx transfer buffer */
00150
00151   __IO uint16_t              RxXferSize;   /* SPDIFRX Rx transfer size */
00152
00153   __IO uint16_t              RxXferCount;  /* SPDIFRX Rx transfer counter
00154                                               (This field is initialized at the
00155                                                same value as transfer size at the
00156                                                beginning of the transfer and
00157                                                decremented when a sample is received.
00158                                                NbSamplesReceived = RxBufferSize-RxBufferCount) */
00159
00160   __IO uint16_t              CsXferSize;   /* SPDIFRX Rx transfer size */
00161
00162   __IO uint16_t              CsXferCount;  /* SPDIFRX Rx transfer counter
00163                                               (This field is initialized at the
00164                                                same value as transfer size at the
00165                                                beginning of the transfer and
00166                                                decremented when a sample is received.
00167                                                NbSamplesReceived = RxBufferSize-RxBufferCount) */
00168
00169   DMA_HandleTypeDef          *hdmaCsRx;    /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */
00170
00171   DMA_HandleTypeDef          *hdmaDrRx;    /* SPDIFRX Rx DMA handle parameters */
00172
00173   __IO HAL_LockTypeDef       Lock;         /* SPDIFRX locking object */
00174
00175   __IO HAL_SPDIFRX_StateTypeDef  State;    /* SPDIFRX communication state */
00176
00177   __IO uint32_t  ErrorCode;                /* SPDIFRX Error code                 */
00178
00179 } SPDIFRX_HandleTypeDef;
00180 /**
00181   * @}
00182   */
00183
00184 /* Exported constants --------------------------------------------------------*/
00185 /** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants
00186   * @{
00187   */
00188 /** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code
00189   * @{
00190   */
00191 #define HAL_SPDIFRX_ERROR_NONE      ((uint32_t)0x00000000U)  /*!< No error           */
00192 #define HAL_SPDIFRX_ERROR_TIMEOUT   ((uint32_t)0x00000001U)  /*!< Timeout error      */
00193 #define HAL_SPDIFRX_ERROR_OVR       ((uint32_t)0x00000002U)  /*!< OVR error          */
00194 #define HAL_SPDIFRX_ERROR_PE        ((uint32_t)0x00000004U)  /*!< Parity error       */
00195 #define HAL_SPDIFRX_ERROR_DMA       ((uint32_t)0x00000008U)  /*!< DMA transfer error */
00196 #define HAL_SPDIFRX_ERROR_UNKNOWN   ((uint32_t)0x00000010U)  /*!< Unknown Error error */
00197 /**
00198   * @}
00199   */
00200
00201 /** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection
00202   * @{
00203   */
00204 #define SPDIFRX_INPUT_IN0               ((uint32_t)0x00000000U)
00205 #define SPDIFRX_INPUT_IN1               ((uint32_t)0x00010000U)
00206 #define SPDIFRX_INPUT_IN2               ((uint32_t)0x00020000U)
00207 #define SPDIFRX_INPUT_IN3               ((uint32_t)0x00030000U)
00208 /**
00209   * @}
00210   */
00211
00212 /** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries
00213   * @{
00214   */
00215 #define SPDIFRX_MAXRETRIES_NONE            ((uint32_t)0x00000000U)
00216 #define SPDIFRX_MAXRETRIES_3               ((uint32_t)0x00001000U)
00217 #define SPDIFRX_MAXRETRIES_15              ((uint32_t)0x00002000U)
00218 #define SPDIFRX_MAXRETRIES_63              ((uint32_t)0x00003000U)
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity
00224   * @{
00225   */
00226 #define SPDIFRX_WAITFORACTIVITY_OFF                   ((uint32_t)0x00000000U)
00227 #define SPDIFRX_WAITFORACTIVITY_ON                    ((uint32_t)SPDIFRX_CR_WFA)
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask
00233   * @{
00234   */
00235 #define SPDIFRX_PREAMBLETYPEMASK_OFF                   ((uint32_t)0x00000000U)
00236 #define SPDIFRX_PREAMBLETYPEMASK_ON                    ((uint32_t)SPDIFRX_CR_PTMSK)
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup SPDIFRX_ChannelStatus_Mask  SPDIFRX Channel Status Mask
00242   * @{
00243   */
00244 #define SPDIFRX_CHANNELSTATUS_OFF                 ((uint32_t)0x00000000U)        /* The channel status and user bits are copied into the SPDIF_DR */
00245 #define SPDIFRX_CHANNELSTATUS_ON                  ((uint32_t)SPDIFRX_CR_CUMSK)  /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
00246 /**
00247   * @}
00248   */
00249
00250 /** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask
00251 * @{
00252 */
00253 #define SPDIFRX_VALIDITYMASK_OFF                   ((uint32_t)0x00000000U)
00254 #define SPDIFRX_VALIDITYMASK_ON                    ((uint32_t)SPDIFRX_CR_VMSK)
00255 /**
00256   * @}
00257   */
00258
00259 /** @defgroup SPDIFRX_PE_Mask  SPDIFRX Parity Error Mask
00260   * @{
00261   */
00262 #define SPDIFRX_PARITYERRORMASK_OFF                   ((uint32_t)0x00000000U)
00263 #define SPDIFRX_PARITYERRORMASK_ON                    ((uint32_t)SPDIFRX_CR_PMSK)
00264 /**
00265   * @}
00266   */
00267
00268 /** @defgroup SPDIFRX_Channel_Selection  SPDIFRX Channel Selection
00269   * @{
00270   */
00271 #define SPDIFRX_CHANNEL_A      ((uint32_t)0x00000000U)
00272 #define SPDIFRX_CHANNEL_B      ((uint32_t)SPDIFRX_CR_CHSEL)
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format
00278   * @{
00279   */
00280 #define SPDIFRX_DATAFORMAT_LSB                   ((uint32_t)0x00000000U)
00281 #define SPDIFRX_DATAFORMAT_MSB                   ((uint32_t)0x00000010U)
00282 #define SPDIFRX_DATAFORMAT_32BITS                ((uint32_t)0x00000020U)
00283 /**
00284   * @}
00285   */
00286
00287 /** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode
00288   * @{
00289   */
00290 #define SPDIFRX_STEREOMODE_DISABLE           ((uint32_t)0x00000000U)
00291 #define SPDIFRX_STEREOMODE_ENABLE           ((uint32_t)SPDIFRX_CR_RXSTEO)
00292 /**
00293   * @}
00294   */
00295
00296 /** @defgroup SPDIFRX_State SPDIFRX State
00297   * @{
00298   */
00299
00300 #define SPDIFRX_STATE_IDLE    ((uint32_t)0xFFFFFFFCU)
00301 #define SPDIFRX_STATE_SYNC    ((uint32_t)0x00000001U)
00302 #define SPDIFRX_STATE_RCV     ((uint32_t)SPDIFRX_CR_SPDIFEN)
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition
00308   * @{
00309   */
00310 #define SPDIFRX_IT_RXNE                       ((uint32_t)SPDIFRX_IMR_RXNEIE)
00311 #define SPDIFRX_IT_CSRNE                      ((uint32_t)SPDIFRX_IMR_CSRNEIE)
00312 #define SPDIFRX_IT_PERRIE                     ((uint32_t)SPDIFRX_IMR_PERRIE)
00313 #define SPDIFRX_IT_OVRIE                      ((uint32_t)SPDIFRX_IMR_OVRIE)
00314 #define SPDIFRX_IT_SBLKIE                     ((uint32_t)SPDIFRX_IMR_SBLKIE)
00315 #define SPDIFRX_IT_SYNCDIE                    ((uint32_t)SPDIFRX_IMR_SYNCDIE)
00316 #define SPDIFRX_IT_IFEIE                      ((uint32_t)SPDIFRX_IMR_IFEIE )
00317 /**
00318   * @}
00319   */
00320
00321 /** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition
00322   * @{
00323   */
00324 #define SPDIFRX_FLAG_RXNE                   ((uint32_t)SPDIFRX_SR_RXNE)
00325 #define SPDIFRX_FLAG_CSRNE                  ((uint32_t)SPDIFRX_SR_CSRNE)
00326 #define SPDIFRX_FLAG_PERR                   ((uint32_t)SPDIFRX_SR_PERR)
00327 #define SPDIFRX_FLAG_OVR                    ((uint32_t)SPDIFRX_SR_OVR)
00328 #define SPDIFRX_FLAG_SBD                    ((uint32_t)SPDIFRX_SR_SBD)
00329 #define SPDIFRX_FLAG_SYNCD                  ((uint32_t)SPDIFRX_SR_SYNCD)
00330 #define SPDIFRX_FLAG_FERR                   ((uint32_t)SPDIFRX_SR_FERR)
00331 #define SPDIFRX_FLAG_SERR                   ((uint32_t)SPDIFRX_SR_SERR)
00332 #define SPDIFRX_FLAG_TERR                   ((uint32_t)SPDIFRX_SR_TERR)
00333 /**
00334   * @}
00335   */
00336
00337 /**
00338   * @}
00339   */
00340
00341 /* Exported macros -----------------------------------------------------------*/
00342 /** @defgroup SPDIFRX_Exported_macros SPDIFRX Exported Macros
00343   * @{
00344   */
00345
00346 /** @brief  Reset SPDIFRX handle state
00347   * @param  __HANDLE__: SPDIFRX handle.
00348   * @retval None
00349   */
00350 #define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN)
00351
00352 /** @brief  Disable the specified SPDIFRX peripheral (IDLE State).
00353   * @param  __HANDLE__: specifies the SPDIFRX Handle.
00354   * @retval None
00355   */
00356 #define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)
00357
00358 /** @brief  Enable the specified SPDIFRX peripheral (SYNC State).
00359   * @param  __HANDLE__: specifies the SPDIFRX Handle.
00360   * @retval None
00361   */
00362 #define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)
00363
00364
00365 /** @brief  Enable the specified SPDIFRX peripheral (RCV State).
00366   * @param  __HANDLE__: specifies the SPDIFRX Handle.
00367   * @retval None
00368   */
00369 #define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)
00370
00371
00372 /** @brief  Enable or disable the specified SPDIFRX interrupts.
00373   * @param  __HANDLE__: specifies the SPDIFRX Handle.
00374   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
00375   *        This parameter can be one of the following values:
00376   *            @arg SPDIFRX_IT_RXNE
00377   *            @arg SPDIFRX_IT_CSRNE
00378   *            @arg SPDIFRX_IT_PERRIE
00379   *            @arg SPDIFRX_IT_OVRIE
00380   *            @arg SPDIFRX_IT_SBLKIE
00381   *            @arg SPDIFRX_IT_SYNCDIE
00382   *            @arg SPDIFRX_IT_IFEIE
00383   * @retval None
00384   */
00385 #define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
00386 #define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
00387
00388 /** @brief  Checks if the specified SPDIFRX interrupt source is enabled or disabled.
00389   * @param  __HANDLE__: specifies the SPDIFRX Handle.
00390   * @param  __INTERRUPT__: specifies the SPDIFRX interrupt source to check.
00391   *          This parameter can be one of the following values:
00392   *            @arg SPDIFRX_IT_RXNE
00393   *            @arg SPDIFRX_IT_CSRNE
00394   *            @arg SPDIFRX_IT_PERRIE
00395   *            @arg SPDIFRX_IT_OVRIE
00396   *            @arg SPDIFRX_IT_SBLKIE
00397   *            @arg SPDIFRX_IT_SYNCDIE
00398   *            @arg SPDIFRX_IT_IFEIE
00399   * @retval The new state of __IT__ (TRUE or FALSE).
00400   */
00401 #define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00402
00403 /** @brief  Checks whether the specified SPDIFRX flag is set or not.
00404   * @param  __HANDLE__: specifies the SPDIFRX Handle.
00405   * @param  __FLAG__: specifies the flag to check.
00406   *        This parameter can be one of the following values:
00407   *            @arg SPDIFRX_FLAG_RXNE
00408   *            @arg SPDIFRX_FLAG_CSRNE
00409   *            @arg SPDIFRX_FLAG_PERR
00410   *            @arg SPDIFRX_FLAG_OVR
00411   *            @arg SPDIFRX_FLAG_SBD
00412   *            @arg SPDIFRX_FLAG_SYNCD
00413   *            @arg SPDIFRX_FLAG_FERR
00414   *            @arg SPDIFRX_FLAG_SERR
00415   *            @arg SPDIFRX_FLAG_TERR
00416   * @retval The new state of __FLAG__ (TRUE or FALSE).
00417   */
00418 #define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00419
00420 /** @brief  Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.
00421   * @param  __HANDLE__: specifies the USART Handle.
00422   * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
00423   *                       to clear the corresponding interrupt
00424   *          This parameter can be one of the following values:
00425   *            @arg SPDIFRX_FLAG_PERR
00426   *            @arg SPDIFRX_FLAG_OVR
00427   *            @arg SPDIFRX_SR_SBD
00428   *            @arg SPDIFRX_SR_SYNCD
00429   * @retval None
00430   */
00431 #define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))
00432
00433 /**
00434   * @}
00435   */
00436
00437 /* Exported functions --------------------------------------------------------*/
00438 /** @addtogroup SPDIFRX_Exported_Functions
00439   * @{
00440   */
00441
00442 /** @addtogroup SPDIFRX_Exported_Functions_Group1
00443   * @{
00444   */
00445 /* Initialization/de-initialization functions  **********************************/
00446 HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif);
00447 HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif);
00448 void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif);
00449 void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif);
00450 HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef  sDataFormat);
00451 /**
00452   * @}
00453   */
00454
00455 /** @addtogroup SPDIFRX_Exported_Functions_Group2
00456   * @{
00457   */
00458 /* I/O operation functions  ***************************************************/
00459  /* Blocking mode: Polling */
00460 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
00461 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
00462
00463  /* Non-Blocking mode: Interrupt */
00464 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
00465 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
00466 void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif);
00467
00468 /* Non-Blocking mode: DMA */
00469 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
00470 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
00471
00472 HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif);
00473
00474 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
00475 void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
00476 void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
00477 void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif);
00478 void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
00479 void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
00480 /**
00481   * @}
00482   */
00483
00484 /** @addtogroup SPDIFRX_Exported_Functions_Group3
00485   * @{
00486   */
00487 /* Peripheral Control and State functions  ************************************/
00488 HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif);
00489 uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif);
00490 /**
00491   * @}
00492   */
00493
00494 /**
00495   * @}
00496   */
00497 /* Private types -------------------------------------------------------------*/
00498 /* Private variables ---------------------------------------------------------*/
00499 /* Private constants ---------------------------------------------------------*/
00500 /* Private macros ------------------------------------------------------------*/
00501 /** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros
00502   * @{
00503   */
00504 #define IS_SPDIFRX_INPUT_SELECT(INPUT)  (((INPUT) == SPDIFRX_INPUT_IN1) || \
00505                                          ((INPUT) == SPDIFRX_INPUT_IN2) || \
00506                                          ((INPUT) == SPDIFRX_INPUT_IN3)  || \
00507                                          ((INPUT) == SPDIFRX_INPUT_IN0))
00508 #define IS_SPDIFRX_MAX_RETRIES(RET)   (((RET) == SPDIFRX_MAXRETRIES_NONE) || \
00509                                       ((RET) == SPDIFRX_MAXRETRIES_3)  || \
00510                                       ((RET) == SPDIFRX_MAXRETRIES_15) || \
00511                                       ((RET) == SPDIFRX_MAXRETRIES_63))
00512 #define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL)    (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
00513                                                ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))
00514 #define IS_PREAMBLE_TYPE_MASK(VAL)           (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
00515                                              ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))
00516 #define IS_VALIDITY_MASK(VAL)               (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \
00517                                              ((VAL) == SPDIFRX_VALIDITYMASK_ON))
00518 #define IS_PARITY_ERROR_MASK(VAL)            (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
00519                                              ((VAL) == SPDIFRX_PARITYERRORMASK_ON))
00520 #define IS_SPDIFRX_CHANNEL(CHANNEL)   (((CHANNEL) == SPDIFRX_CHANNEL_A) || \
00521                                        ((CHANNEL) == SPDIFRX_CHANNEL_B))
00522 #define IS_SPDIFRX_DATA_FORMAT(FORMAT)           (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
00523                                                  ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \
00524                                                  ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))
00525 #define IS_STEREO_MODE(MODE)                 (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
00526                                              ((MODE) == SPDIFRX_STEREOMODE_ENABLE))
00527
00528 #define IS_CHANNEL_STATUS_MASK(VAL)          (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
00529                                               ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))
00530 /**
00531   * @}
00532   */
00533
00534 /* Private functions ---------------------------------------------------------*/
00535 /** @defgroup SPDIFRX_Private_Functions SPDIFRX Private Functions
00536   * @{
00537   */
00538 /**
00539   * @}
00540   */
00541
00542 /**
00543   * @}
00544   */
00545 #endif /* SPDIFRX */
00546 /**
00547   * @}
00548   */
00549
00550 #ifdef __cplusplus
00551 }
00552 #endif
00553
00554
00555 #endif /* __STM32H7xx_HAL_SPDIFRX_H */
00556
00557 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_spi.c Source File

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stm32h7xx_hal_spi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_spi.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   SPI HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020       The SPI HAL driver can be used as follows:
00021
00022       (#) Declare a SPI_HandleTypeDef handle structure, for example:
00023           SPI_HandleTypeDef  hspi;
00024
00025       (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
00026           (##) Enable the SPIx interface clock
00027           (##) SPI pins configuration
00028               (+++) Enable the clock for the SPI GPIOs
00029               (+++) Configure these SPI pins as alternate function push-pull
00030           (##) NVIC configuration if you need to use interrupt process
00031               (+++) Configure the SPIx interrupt priority
00032               (+++) Enable the NVIC SPI IRQ handle
00033           (##) DMA Configuration if you need to use DMA process
00034               (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
00035               (+++) Enable the DMAx clock
00036               (+++) Configure the DMA handle parameters
00037               (+++) Configure the DMA Tx or Rx Stream/Channel
00038               (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
00039               (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
00040
00041       (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
00042           management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
00043
00044       (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
00045           (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00046               by calling the customized HAL_SPI_MspInit() API.
00047
00048     [..]
00049       Circular mode restriction:
00050       (+) The DMA circular mode cannot be used when the SPI is configured in these modes:
00051           (++) Master 2Lines RxOnly
00052           (++) Master 1Line Rx
00053       (+) The CRC feature is not managed when the DMA circular mode is enabled
00054       (+) When the SPI DMA Pause/Stop features are used, we must use the following APIs
00055           the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
00056
00057   @endverbatim
00058   ******************************************************************************
00059   * @attention
00060   *
00061   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00062   *
00063   * Redistribution and use in source and binary forms, with or without modification,
00064   * are permitted provided that the following conditions are met:
00065   *   1. Redistributions of source code must retain the above copyright notice,
00066   *      this list of conditions and the following disclaimer.
00067   *   2. Redistributions in binary form must reproduce the above copyright notice,
00068   *      this list of conditions and the following disclaimer in the documentation
00069   *      and/or other materials provided with the distribution.
00070   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00071   *      may be used to endorse or promote products derived from this software
00072   *      without specific prior written permission.
00073   *
00074   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00075   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00076   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00077   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00078   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00079   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00080   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00081   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00082   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00083   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00084   *
00085   ******************************************************************************
00086   */
00087
00088 /* Includes ------------------------------------------------------------------*/
00089 #include "stm32h7xx_hal.h"
00090
00091 /** @addtogroup STM32H7xx_HAL_Driver
00092   * @{
00093   */
00094
00095 /** @defgroup SPI SPI
00096   * @brief SPI HAL module driver
00097   * @{
00098   */
00099 #ifdef HAL_SPI_MODULE_ENABLED
00100
00101 /* Private typedef -----------------------------------------------------------*/
00102 /* Private defines -----------------------------------------------------------*/
00103 /** @defgroup SPI_Private_Constants SPI Private Constants
00104   * @{
00105   */
00106 #define SPI_DEFAULT_TIMEOUT 100U
00107 /**
00108   * @}
00109   */
00110
00111 /* Private macros ------------------------------------------------------------*/
00112 /* Private variables ---------------------------------------------------------*/
00113 /* Private function prototypes -----------------------------------------------*/
00114 /** @defgroup SPI_Private_Functions SPI Private Functions
00115   * @{
00116   */
00117 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00118 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00119 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
00120 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
00121 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
00122 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
00123 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
00124 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00125 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00126 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00127 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
00128                                                        uint32_t Timeout, uint32_t Tickstart);
00129 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
00130                                                        uint32_t Timeout, uint32_t Tickstart);
00131 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00132 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00133 static void SPI_TxISR_32BIT(struct __SPI_HandleTypeDef *hspi);
00134 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00135 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00136 static void SPI_RxISR_32BIT(struct __SPI_HandleTypeDef *hspi);
00137 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00138 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00139 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00140 static void SPI_2linesTxISR_32BIT(struct __SPI_HandleTypeDef *hspi);
00141 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00142 static void SPI_2linesRxISR_32BIT(struct __SPI_HandleTypeDef *hspi);
00143 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
00144 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
00145 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
00146 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
00147 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
00148 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
00149 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
00150 /**
00151   * @}
00152   */
00153
00154 /* Exported functions --------------------------------------------------------*/
00155 /** @defgroup SPI_Exported_Functions SPI Exported Functions
00156   * @{
00157   */
00158
00159 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
00160  *  @brief    Initialization and Configuration functions
00161  *
00162 @verbatim
00163  ===============================================================================
00164               ##### Initialization and de-initialization functions #####
00165  ===============================================================================
00166     [..]  This subsection provides a set of functions allowing to initialize and
00167           de-initialize the SPIx peripheral:
00168
00169       (+) User must implement HAL_SPI_MspInit() function in which he configures
00170           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00171
00172       (+) Call the function HAL_SPI_Init() to configure the selected device with
00173           the selected configuration:
00174         (++) Mode
00175         (++) Direction
00176         (++) Data Size
00177         (++) Clock Polarity and Phase
00178         (++) NSS Management
00179         (++) BaudRate Prescaler
00180         (++) FirstBit
00181         (++) TIMode
00182         (++) CRC Calculation
00183         (++) CRC Polynomial if CRC enabled
00184         (++) CRC Length, used only with Data8 and Data16
00185         (++) FIFO reception threshold
00186         (++) FIFO transmission threshold
00187
00188       (+) Call the function HAL_SPI_DeInit() to restore the default configuration
00189           of the selected SPIx peripheral.
00190
00191 @endverbatim
00192   * @{
00193   */
00194
00195 /**
00196   * @brief  Initialize the SPI according to the specified parameters
00197   *         in the SPI_InitTypeDef and initialize the associated handle.
00198   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00199   *               the configuration information for SPI module.
00200   * @retval HAL status
00201   */
00202 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
00203 {
00204   /* Check the SPI handle allocation */
00205   if (hspi == NULL)
00206   {
00207     return HAL_ERROR;
00208   }
00209
00210   /* Check the parameters */
00211   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
00212   assert_param(IS_SPI_MODE(hspi->Init.Mode));
00213   assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
00214   assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
00215   assert_param(IS_SPI_FIFOTHRESHOLD(hspi->Init.FifoThreshold));
00216   assert_param(IS_SPI_NSS(hspi->Init.NSS));
00217   assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
00218   assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
00219   assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
00220   assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
00221   if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
00222   {
00223     assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
00224     assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
00225   }
00226 #ifdef USE_SPI_CRC
00227   assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
00228   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00229   {
00230     assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
00231     assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
00232     assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.TxCRCInitializationPattern));
00233     assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.RxCRCInitializationPattern));
00234   }
00235 #else
00236   hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
00237 #endif /* USE_SPI_CRC */
00238
00239   /* Verify that the SPI instance is supporting Data Size higher than 16bits */
00240   if ((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (hspi->Init.DataSize > SPI_DATASIZE_16BIT))
00241   {
00242     return HAL_ERROR;
00243   }
00244
00245 #ifdef USE_SPI_CRC
00246   /* Verify that the SPI instance is supporting CRC Length higher than 16bits */
00247   if ((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (hspi->Init.CRCLength > SPI_CRC_LENGTH_16BIT))
00248   {
00249     return HAL_ERROR;
00250   }
00251
00252   /* CRC calculation is valid only for 16Bit and 32 Bit */
00253   if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_32BIT))
00254   {
00255     /* CRC must be disabled */
00256     hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
00257   }
00258
00259   /* Align the CRC Length on the data size */
00260   if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
00261   {
00262     /* CRC Length aligned on the data size : value set by default */
00263     if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
00264     {
00265       hspi->Init.CRCLength = SPI_CRC_LENGTH_32BIT;
00266     }
00267     else
00268     {
00269       hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
00270     }
00271   }
00272 #endif /* USE_SPI_CRC */
00273
00274   if (hspi->State == HAL_SPI_STATE_RESET)
00275   {
00276     /* Allocate lock resource and initialize it */
00277     hspi->Lock = HAL_UNLOCKED;
00278
00279     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00280     HAL_SPI_MspInit(hspi);
00281   }
00282
00283   hspi->State = HAL_SPI_STATE_BUSY;
00284
00285   /* Disable the selected SPI peripheral */
00286   __HAL_SPI_DISABLE(hspi);
00287
00288   /* Unlock the AF configuration to edit CFG2 register */
00289   HAL_SPIEx_DisableLockConfiguration(hspi);
00290
00291   /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
00292   /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
00293   Communication speed, First bit, CRC calculation state, CRC Length */
00294
00295   if ((hspi->Init.NSS == SPI_NSS_SOFT) && (hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW))
00296   {
00297     SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI);
00298   }
00299
00300   /* SPIx CFG1 Configuration */
00301   WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | hspi->Init.CRCLength |
00302                                    hspi->Init.FifoThreshold     | hspi->Init.DataSize));
00303
00304   /* SPIx CFG2 Configuration */
00305   WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode     | hspi->Init.TIMode           | hspi->Init.NSSPolarity             |
00306                                    hspi->Init.NSS          | hspi->Init.CLKPolarity      | hspi->Init.CLKPhase                |
00307                                    hspi->Init.FirstBit     | hspi->Init.Mode             | hspi->Init.MasterInterDataIdleness |
00308                                    hspi->Init.Direction    | hspi->Init.MasterSSIdleness | hspi->Init.IOSwap));
00309
00310 #ifdef USE_SPI_CRC
00311   /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
00312   /* Configure : CRC Polynomial */
00313   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00314   {
00315     /* Initialize TXCRC Pattern Initial Value */
00316     if (hspi->Init.TxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)
00317       SET_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI);
00318     else
00319       CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI);
00320
00321     /* Initialize RXCRC Pattern Initial Value */
00322     if (hspi->Init.RxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)
00323       SET_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI);
00324     else
00325       CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI);
00326
00327     /* Write CRC polynomial in SPI Register */
00328     if (  ((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) || \
00329           ((IS_SPI_HIGHEND_INSTANCE(hspi->Instance))  && (hspi->Init.CRCLength == SPI_CRC_LENGTH_32BIT)) )
00330     {
00331       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17);
00332       WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial);
00333     }
00334   }
00335 #endif /* USE_SPI_CRC */
00336
00337   /* Insure that Underrun configuration is managed only by Salve */
00338   if (hspi->Init.Mode == SPI_MODE_SLAVE)
00339   {
00340     /* Set Default Underrun configuration */
00341     MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, SPI_CFG1_UDRDET_0);
00342     MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, SPI_CFG1_UDRCFG_1);
00343   }
00344
00345 #if defined(SPI_I2SCFGR_I2SMOD)
00346   /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
00347   CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
00348 #endif /* SPI_I2SCFGR_I2SMOD */
00349
00350   /* Insure that AFCNTR is managed only by Master */
00351   if ((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER)
00352   {
00353     /* Alternate function GPIOs control */
00354     MODIFY_REG(hspi->Instance->CFG2, SPI_CFG2_AFCNTR, (hspi->Init.MasterKeepIOState));
00355   }
00356
00357   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
00358   hspi->State     = HAL_SPI_STATE_READY;
00359
00360   return HAL_OK;
00361 }
00362
00363 /**
00364   * @brief  De-Initialize the SPI peripheral.
00365   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00366   *               the configuration information for SPI module.
00367   * @retval HAL status
00368   */
00369 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
00370 {
00371   /* Check the SPI handle allocation */
00372   if (hspi == NULL)
00373   {
00374     return HAL_ERROR;
00375   }
00376
00377   /* Check SPI Instance parameter */
00378   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
00379
00380   hspi->State = HAL_SPI_STATE_BUSY;
00381
00382   /* Disable the SPI Peripheral Clock */
00383   __HAL_SPI_DISABLE(hspi);
00384
00385   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00386   HAL_SPI_MspDeInit(hspi);
00387
00388   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
00389   hspi->State = HAL_SPI_STATE_RESET;
00390
00391   /* Release Lock */
00392   __HAL_UNLOCK(hspi);
00393
00394   return HAL_OK;
00395 }
00396
00397 /**
00398   * @brief  Initialize the SPI MSP.
00399   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00400   *               the configuration information for SPI module.
00401   * @retval None
00402   */
00403 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
00404 {
00405   /* Prevent unused argument(s) compilation warning */
00406   UNUSED(hspi);
00407
00408   /* NOTE : This function should not be modified, when the callback is needed,
00409             the HAL_SPI_MspInit should be implemented in the user file
00410    */
00411 }
00412
00413 /**
00414   * @brief  De-Initialize the SPI MSP.
00415   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00416   *               the configuration information for SPI module.
00417   * @retval None
00418   */
00419 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
00420 {
00421   /* Prevent unused argument(s) compilation warning */
00422   UNUSED(hspi);
00423
00424   /* NOTE : This function should not be modified, when the callback is needed,
00425             the HAL_SPI_MspDeInit should be implemented in the user file
00426    */
00427 }
00428
00429 /**
00430   * @}
00431   */
00432
00433 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
00434  *  @brief   Data transfers functions
00435  *
00436 @verbatim
00437   ==============================================================================
00438                       ##### IO operation functions #####
00439  ===============================================================================
00440  [..]
00441     This subsection provides a set of functions allowing to manage the SPI
00442     data transfers.
00443
00444     [..] The SPI supports master and slave mode :
00445
00446     (#) There are two modes of transfer:
00447        (##) Blocking mode: The communication is performed in polling mode.
00448             The HAL status of all data processing is returned by the same function
00449             after finishing transfer.
00450        (##) No-Blocking mode: The communication is performed using Interrupts
00451             or DMA, These APIs return the HAL status.
00452             The end of the data processing will be indicated through the
00453             dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
00454             using DMA mode.
00455             The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
00456             will be executed respectively at the end of the transmit or Receive process
00457             The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
00458
00459     (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
00460         exist for 1Line (simplex) and 2Lines (full duplex) modes.
00461
00462 @endverbatim
00463   * @{
00464   */
00465
00466 /**
00467   * @brief  Transmit an amount of data in blocking mode.
00468   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00469   *               the configuration information for SPI module.
00470   * @param  pData: pointer to data buffer
00471   * @param  Size: amount of data to be sent
00472   * @param  Timeout: Timeout duration
00473   * @retval HAL status
00474   */
00475 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00476 {
00477   uint32_t tickstart = 0U;
00478   HAL_StatusTypeDef errorcode = HAL_OK;
00479
00480   /* Check Direction parameter */
00481   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
00482
00483   /* Process Locked */
00484   __HAL_LOCK(hspi);
00485
00486   /* Init tickstart for timeout management*/
00487   tickstart = HAL_GetTick();
00488
00489   if (hspi->State != HAL_SPI_STATE_READY)
00490   {
00491     errorcode = HAL_BUSY;
00492     __HAL_UNLOCK(hspi);
00493     return errorcode;
00494   }
00495
00496   if ((pData == NULL) || (Size == 0U))
00497   {
00498     errorcode = HAL_ERROR;
00499     __HAL_UNLOCK(hspi);
00500     return errorcode;
00501   }
00502
00503   /* Set the transaction information */
00504   hspi->State       = HAL_SPI_STATE_BUSY_TX;
00505   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00506   hspi->pTxBuffPtr  = (uint8_t *)pData;
00507   hspi->TxXferSize  = Size;
00508   hspi->TxXferCount = Size;
00509
00510   /*Init field not used in handle to zero */
00511   hspi->pRxBuffPtr  = NULL;
00512   hspi->RxXferSize  = 0U;
00513   hspi->RxXferCount = 0U;
00514   hspi->TxISR       = NULL;
00515   hspi->RxISR       = NULL;
00516
00517   /* Configure communication direction : 1Line */
00518   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
00519   {
00520     SPI_1LINE_TX(hspi);
00521   }
00522
00523   /* Set the number if data at current transfer */
00524   MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
00525
00526   /* Check if the SPI is already enabled */
00527   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00528   {
00529     /* Enable SPI peripheral */
00530     __HAL_SPI_ENABLE(hspi);
00531   }
00532   else
00533   {
00534     if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_UDR))
00535     {
00536       *((__IO uint8_t *)&hspi->Instance->TXDR) = 0x01U;
00537       __HAL_SPI_CLEAR_UDRFLAG(hspi);
00538       __HAL_SPI_DISABLE(hspi);
00539       __HAL_SPI_ENABLE(hspi);
00540     }
00541   }
00542
00543   if (hspi->Init.Mode == SPI_MODE_MASTER)
00544   {
00545     /* Master transfer start */
00546     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
00547   }
00548
00549   /* Transmit data in 32 Bit mode */
00550   if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
00551   {
00552     /* Transmit data in 32 Bit mode */
00553     while (hspi->TxXferCount > 0U)
00554     {
00555       /* Wait until TXE flag is set to send data */
00556       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
00557       {
00558         *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
00559         hspi->pTxBuffPtr += sizeof(uint32_t);
00560         hspi->TxXferCount--;
00561       }
00562       else
00563       {
00564         /* Timeout management */
00565         if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
00566         {
00567           /* Set the error code and execute error callback*/
00568           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
00569           HAL_SPI_ErrorCallback(hspi);
00570
00571           /* Set the SPI State ready */
00572           hspi->State = HAL_SPI_STATE_READY;
00573
00574           /* Process Unlocked */
00575           __HAL_UNLOCK(hspi);
00576           return HAL_ERROR;
00577         }
00578       }
00579     }
00580   }
00581   /* Transmit data in 16 Bit mode */
00582   else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00583   {
00584     if (IS_SPI_HIGHEND_INSTANCE(hspi->Instance))
00585     {
00586       /* Transmit data in 16 Bit mode */
00587       while (hspi->TxXferCount > 0U)
00588       {
00589         /* Wait until TXE flag is set to send data */
00590         if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
00591         {
00592           if ( (hspi->TxXferCount > 1U) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
00593           {
00594             *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
00595             hspi->pTxBuffPtr += sizeof(uint32_t);
00596             hspi->TxXferCount-=2;
00597           }
00598           else
00599           {
00600             *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
00601             hspi->pTxBuffPtr += sizeof(uint16_t);
00602             hspi->TxXferCount--;
00603           }
00604         }
00605         else
00606         {
00607           /* Timeout management */
00608           if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
00609           {
00610             /* Set the error code and execute error callback*/
00611             SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
00612             HAL_SPI_ErrorCallback(hspi);
00613
00614             /* Set the SPI State ready */
00615             hspi->State = HAL_SPI_STATE_READY;
00616
00617             /* Process Unlocked */
00618             __HAL_UNLOCK(hspi);
00619             return HAL_ERROR;
00620           }
00621         }
00622       }
00623     }
00624   }
00625   /* Transmit data in 8 Bit mode */
00626   else
00627   {
00628     if (IS_SPI_HIGHEND_INSTANCE(hspi->Instance))
00629     {
00630       while (hspi->TxXferCount > 0U)
00631       {
00632         /* Wait until TXE flag is set to send data */
00633         if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
00634         {
00635           if ((hspi->TxXferCount > 3U) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA))
00636           {
00637             *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
00638             hspi->pTxBuffPtr += sizeof(uint32_t);
00639             hspi->TxXferCount-=4;
00640           }
00641           else if ((hspi->TxXferCount > 1U) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
00642           {
00643             *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
00644             hspi->pTxBuffPtr += sizeof(uint16_t);
00645             hspi->TxXferCount-=2;
00646           }
00647           else
00648           {
00649             *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr);
00650             hspi->pTxBuffPtr += sizeof(uint8_t);
00651             hspi->TxXferCount--;
00652           }
00653         }
00654         else
00655         {
00656           /* Timeout management */
00657           if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
00658           {
00659             /* Set the error code and execute error callback*/
00660             SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
00661             HAL_SPI_ErrorCallback(hspi);
00662
00663             /* Set the SPI State ready */
00664             hspi->State = HAL_SPI_STATE_READY;
00665
00666             /* Process Unlocked */
00667             __HAL_UNLOCK(hspi);
00668             return HAL_ERROR;
00669           }
00670         }
00671       }
00672     }
00673   }
00674
00675   /* Check the end of the transaction */
00676   if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
00677   {
00678     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
00679   }
00680
00681   /* Clear overrun flag in 2 Lines communication mode because received data is not read */
00682   if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
00683   {
00684     __HAL_SPI_CLEAR_OVRFLAG(hspi);
00685   }
00686
00687   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
00688   {
00689     errorcode = HAL_ERROR;
00690   }
00691
00692   hspi->State = HAL_SPI_STATE_READY;
00693   /* Process Unlocked */
00694   __HAL_UNLOCK(hspi);
00695   return errorcode;
00696 }
00697
00698 /**
00699   * @brief  Receive an amount of data in blocking mode.
00700   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00701   *               the configuration information for SPI module.
00702   * @param  pData: pointer to data buffer
00703   * @param  Size: amount of data to be received
00704   * @param  Timeout: Timeout duration
00705   * @retval HAL status
00706   */
00707 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00708 {
00709   uint32_t tickstart = 0U;
00710   HAL_StatusTypeDef errorcode = HAL_OK;
00711
00712   /* Check Direction parameter */
00713   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
00714
00715   if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
00716   {
00717     hspi->State = HAL_SPI_STATE_BUSY_RX;
00718     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
00719     return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
00720   }
00721
00722   /* Process Locked */
00723   __HAL_LOCK(hspi);
00724
00725   /* Init tickstart for timeout management*/
00726   tickstart = HAL_GetTick();
00727
00728   if (hspi->State != HAL_SPI_STATE_READY)
00729   {
00730     errorcode = HAL_BUSY;
00731     __HAL_UNLOCK(hspi);
00732     return errorcode;
00733   }
00734
00735   if ((pData == NULL) || (Size == 0U))
00736   {
00737     errorcode = HAL_ERROR;
00738     __HAL_UNLOCK(hspi);
00739     return errorcode;
00740   }
00741
00742   /* Set the transaction information */
00743   hspi->State       = HAL_SPI_STATE_BUSY_RX;
00744   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00745   hspi->pRxBuffPtr  = (uint8_t *)pData;
00746   hspi->RxXferSize  = Size;
00747   hspi->RxXferCount = Size;
00748
00749   /*Init field not used in handle to zero */
00750   hspi->pTxBuffPtr  = NULL;
00751   hspi->TxXferSize  = 0U;
00752   hspi->TxXferCount = 0U;
00753   hspi->RxISR       = NULL;
00754   hspi->TxISR       = NULL;
00755
00756   /* Configure communication direction: 1Line */
00757   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
00758   {
00759     SPI_1LINE_RX(hspi);
00760   }
00761
00762   /* Set the number if data at current transfer */
00763   MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
00764
00765   /* Check if the SPI is already enabled */
00766   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00767   {
00768     /* Enable SPI peripheral */
00769     __HAL_SPI_ENABLE(hspi);
00770   }
00771
00772   if (hspi->Init.Mode == SPI_MODE_MASTER)
00773   {
00774     /* Master transfer start */
00775     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
00776   }
00777
00778   /* Receive data in 32 Bit mode */
00779   if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
00780   {
00781     /* Transfer loop */
00782     while (hspi->RxXferCount > 0U)
00783     {
00784       /* Check the RXNE flag */
00785       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
00786       {
00787         *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
00788         hspi->pRxBuffPtr += sizeof(uint32_t);
00789         hspi->RxXferCount--;
00790       }
00791       else
00792       {
00793         /* Timeout management */
00794         if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
00795         {
00796           /* Set the error code and execute error callback*/
00797           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
00798           HAL_SPI_ErrorCallback(hspi);
00799
00800           /* Set the SPI State ready */
00801           hspi->State = HAL_SPI_STATE_READY;
00802
00803           /* Process Unlocked */
00804           __HAL_UNLOCK(hspi);
00805           return HAL_ERROR;
00806         }
00807       }
00808     }
00809   }
00810   /* Receive data in 16 Bit mode */
00811   else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00812   {
00813     if (IS_SPI_HIGHEND_INSTANCE(hspi->Instance))
00814     {
00815       /* Transfer loop */
00816       while (hspi->RxXferCount > 0U)
00817       {
00818         /* Check the RXNE flag */
00819         if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
00820         {
00821           if (hspi->Instance->SR & SPI_FLAG_RXWNE)
00822           {
00823             *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
00824             hspi->pRxBuffPtr += sizeof(uint32_t);
00825             hspi->RxXferCount-=2;
00826           }
00827           else
00828           {
00829             *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
00830             hspi->pRxBuffPtr += sizeof(uint16_t);
00831             hspi->RxXferCount--;
00832           }
00833         }
00834         else
00835         {
00836           /* Timeout management */
00837           if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
00838           {
00839             /* Set the error code and execute error callback*/
00840             SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
00841             HAL_SPI_ErrorCallback(hspi);
00842
00843             /* Set the SPI State ready */
00844             hspi->State = HAL_SPI_STATE_READY;
00845
00846             /* Process Unlocked */
00847             __HAL_UNLOCK(hspi);
00848             return HAL_ERROR;
00849           }
00850         }
00851       }
00852     }
00853   }
00854   /* Receive data in 8 Bit mode */
00855   else
00856   {
00857
00858     if (IS_SPI_HIGHEND_INSTANCE(hspi->Instance))
00859     {
00860       /* Transfer loop */
00861       while (hspi->RxXferCount > 0U)
00862       {
00863         /* Check the RXNE flag */
00864         if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
00865         {
00866           if (hspi->Instance->SR & SPI_FLAG_RXWNE)
00867           {
00868             *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
00869             hspi->pRxBuffPtr += sizeof(uint32_t);
00870             hspi->RxXferCount-=4;
00871           }
00872           else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_FRLVL_QUARTER_FULL)
00873           {
00874             *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
00875             hspi->pRxBuffPtr += sizeof(uint16_t);
00876             hspi->RxXferCount-=2;
00877           }
00878           else
00879           {
00880             (*hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
00881             hspi->pRxBuffPtr += sizeof(uint8_t);
00882             hspi->RxXferCount--;
00883           }
00884         }
00885         else
00886         {
00887           /* Timeout management */
00888           if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
00889             {
00890             /* Set the error code and execute error callback*/
00891             SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
00892             HAL_SPI_ErrorCallback(hspi);
00893
00894             /* Set the SPI State ready */
00895             hspi->State = HAL_SPI_STATE_READY;
00896
00897             /* Process Unlocked */
00898             __HAL_UNLOCK(hspi);
00899             return HAL_ERROR;
00900           }
00901         }
00902       }
00903     }
00904   }
00905
00906   /* Check the end of the transaction */
00907   if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
00908   {
00909     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
00910   }
00911
00912 #ifdef USE_SPI_CRC
00913   /* Check if CRC error occurred */
00914   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
00915   {
00916     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
00917     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
00918   }
00919 #endif /* USE_SPI_CRC */
00920
00921   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
00922   {
00923     errorcode = HAL_ERROR;
00924   }
00925
00926   hspi->State = HAL_SPI_STATE_READY;
00927   __HAL_UNLOCK(hspi);
00928   return errorcode;
00929 }
00930
00931 /**
00932   * @brief  Transmit and Receive an amount of data in blocking mode.
00933   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00934   *               the configuration information for SPI module.
00935   * @param  pTxData: pointer to transmission data buffer
00936   * @param  pRxData: pointer to reception data buffer
00937   * @param  Size: amount of data to be sent and received
00938   * @param  Timeout: Timeout duration
00939   * @retval HAL status
00940   */
00941 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
00942                                           uint32_t Timeout)
00943 {
00944   uint32_t tickstart = 0U;
00945   HAL_StatusTypeDef errorcode = HAL_OK;
00946
00947   /* Check Direction parameter */
00948   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
00949
00950   /* Process Locked */
00951   __HAL_LOCK(hspi);
00952
00953   /* Init tickstart for timeout management*/
00954   tickstart = HAL_GetTick();
00955
00956   if (!((hspi->State == HAL_SPI_STATE_READY) || \
00957         ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
00958   {
00959     errorcode = HAL_BUSY;
00960     __HAL_UNLOCK(hspi);
00961     return errorcode;
00962   }
00963
00964   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
00965   {
00966     errorcode = HAL_ERROR;
00967     __HAL_UNLOCK(hspi);
00968     return errorcode;
00969   }
00970
00971   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
00972   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
00973   {
00974     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
00975   }
00976
00977   /* Set the transaction information */
00978   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00979   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
00980   hspi->RxXferCount = Size;
00981   hspi->RxXferSize  = Size;
00982   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
00983   hspi->TxXferCount = Size;
00984   hspi->TxXferSize  = Size;
00985
00986   /*Init field not used in handle to zero */
00987   hspi->RxISR       = NULL;
00988   hspi->TxISR       = NULL;
00989
00990   /* Set the number if data at current transfer */
00991   MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
00992
00993   /* Check if the SPI is already enabled */
00994   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00995   {
00996     /* Enable SPI peripheral */
00997     __HAL_SPI_ENABLE(hspi);
00998   }
00999
01000   if (hspi->Init.Mode == SPI_MODE_MASTER)
01001   {
01002     /* Master transfer start */
01003     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
01004   }
01005
01006   /* Transmit and Receive data in 32 Bit mode */
01007   if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
01008   {
01009     while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
01010     {
01011       /* Check TXE flag */
01012       if ((hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
01013       {
01014         *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
01015         hspi->pTxBuffPtr += sizeof(uint32_t);
01016         hspi->TxXferCount --;
01017       }
01018
01019       /* Check RXNE flag */
01020       if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
01021       {
01022         *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
01023         hspi->pRxBuffPtr += sizeof(uint32_t);
01024         hspi->RxXferCount --;
01025       }
01026
01027       if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout))
01028       {
01029         /* Set the error code and execute error callback*/
01030         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
01031         HAL_SPI_ErrorCallback(hspi);
01032
01033         /* Set the SPI State ready */
01034         hspi->State = HAL_SPI_STATE_READY;
01035
01036         /* Process Unlocked */
01037         __HAL_UNLOCK(hspi);
01038         return HAL_ERROR;
01039       }
01040     }
01041   }
01042   /* Transmit and Receive data in 16 Bit mode */
01043   else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01044   {
01045     if (IS_SPI_HIGHEND_INSTANCE(hspi->Instance))
01046     {
01047       while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
01048       {
01049         /* Check TXE flag */
01050         if ((hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
01051         {
01052           if ( (hspi->TxXferCount > 1U) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
01053           {
01054             *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
01055             hspi->pTxBuffPtr += sizeof(uint32_t);
01056             hspi->TxXferCount-=2;
01057           }
01058           else
01059           {
01060             *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
01061             hspi->pTxBuffPtr += sizeof(uint16_t);
01062             hspi->TxXferCount--;
01063           }
01064         }
01065
01066         /* Check RXNE flag */
01067         if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
01068         {
01069           if (hspi->Instance->SR & SPI_FLAG_RXWNE)
01070           {
01071             *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
01072             hspi->pRxBuffPtr += sizeof(uint32_t);
01073             hspi->RxXferCount-=2;
01074           }
01075           else
01076           {
01077             *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
01078             hspi->pRxBuffPtr += sizeof(uint16_t);
01079             hspi->RxXferCount--;
01080           }
01081         }
01082
01083         if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout))
01084         {
01085           /* Set the error code and execute error callback*/
01086           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
01087           HAL_SPI_ErrorCallback(hspi);
01088
01089           /* Set the SPI State ready */
01090           hspi->State = HAL_SPI_STATE_READY;
01091
01092           /* Process Unlocked */
01093           __HAL_UNLOCK(hspi);
01094           return HAL_ERROR;
01095         }
01096       }
01097     }
01098   }
01099   /* Transmit and Receive data in 8 Bit mode */
01100   else
01101   {
01102     if (IS_SPI_HIGHEND_INSTANCE(hspi->Instance))
01103     {
01104       while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
01105       {
01106         /* check TXE flag */
01107         if ((hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
01108         {
01109           if ((hspi->TxXferCount > 3U) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA))
01110           {
01111             *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
01112             hspi->pTxBuffPtr += sizeof(uint32_t);
01113             hspi->TxXferCount-=4;
01114           }
01115           else if ((hspi->TxXferCount > 1U) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
01116           {
01117             *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
01118             hspi->pTxBuffPtr += sizeof(uint16_t);
01119             hspi->TxXferCount-=2;
01120           }
01121           else
01122           {
01123             *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr);
01124             hspi->pTxBuffPtr += sizeof(uint8_t);
01125             hspi->TxXferCount--;
01126           }
01127         }
01128
01129         /* check TXTF flag */
01130         if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXTF))
01131         {
01132           __HAL_SPI_CLEAR_TXTFFLAG(hspi);
01133         }
01134
01135         /* Wait until RXNE flag is reset */
01136         if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
01137         {
01138           if (hspi->Instance->SR & SPI_FLAG_RXWNE)
01139           {
01140             *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
01141             hspi->pRxBuffPtr += sizeof(uint32_t);
01142             hspi->RxXferCount-=4;
01143           }
01144           else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_FRLVL_QUARTER_FULL)
01145           {
01146             *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
01147             hspi->pRxBuffPtr += sizeof(uint16_t);
01148             hspi->RxXferCount-=2;
01149           }
01150           else
01151           {
01152             (*hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
01153             hspi->pRxBuffPtr += sizeof(uint8_t);
01154             hspi->RxXferCount--;
01155           }
01156         }
01157
01158         if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout))
01159         {
01160           /* Set the error code and execute error callback*/
01161           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
01162           HAL_SPI_ErrorCallback(hspi);
01163
01164           /* Set the SPI State ready */
01165           hspi->State = HAL_SPI_STATE_READY;
01166
01167           /* Process Unlocked */
01168           __HAL_UNLOCK(hspi);
01169           return HAL_ERROR;
01170         }
01171       }
01172     }
01173   }
01174
01175   /* Check the end of the transaction */
01176   if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
01177   {
01178     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
01179   }
01180
01181 #ifdef USE_SPI_CRC
01182   /* Check if CRC error occurred */
01183   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01184   {
01185     if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
01186     {
01187       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01188
01189       /* Clear CRC Flag */
01190       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
01191     }
01192   }
01193 #endif /* USE_SPI_CRC */
01194
01195   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
01196   {
01197     errorcode = HAL_ERROR;
01198   }
01199
01200   hspi->State = HAL_SPI_STATE_READY;
01201   __HAL_UNLOCK(hspi);
01202   return errorcode;
01203 }
01204
01205 /**
01206   * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
01207   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01208   *               the configuration information for SPI module.
01209   * @param  pData: pointer to data buffer
01210   * @param  Size: amount of data to be sent
01211   * @retval HAL status
01212   */
01213 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01214 {
01215   HAL_StatusTypeDef errorcode = HAL_OK;
01216
01217   /* Check Direction parameter */
01218   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
01219
01220   /* Process Locked */
01221   __HAL_LOCK(hspi);
01222
01223   if ((pData == NULL) || (Size == 0U))
01224   {
01225     errorcode = HAL_ERROR;
01226     __HAL_UNLOCK(hspi);
01227     return errorcode;
01228   }
01229
01230   if (hspi->State != HAL_SPI_STATE_READY)
01231   {
01232     errorcode = HAL_BUSY;
01233     __HAL_UNLOCK(hspi);
01234     return errorcode;
01235   }
01236
01237   /* Set the transaction information */
01238   hspi->State       = HAL_SPI_STATE_BUSY_TX;
01239   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01240   hspi->pTxBuffPtr  = (uint8_t *)pData;
01241   hspi->TxXferSize  = Size;
01242   hspi->TxXferCount = Size;
01243
01244   /* Init field not used in handle to zero */
01245   hspi->pRxBuffPtr  = NULL;
01246   hspi->RxXferSize  = 0U;
01247   hspi->RxXferCount = 0U;
01248   hspi->RxISR       = NULL;
01249
01250   /* Set the function for IT treatment */
01251   if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
01252   {
01253     hspi->TxISR = SPI_TxISR_32BIT;
01254   }
01255   else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01256   {
01257     hspi->TxISR = SPI_TxISR_16BIT;
01258   }
01259   else
01260   {
01261     hspi->TxISR = SPI_TxISR_8BIT;
01262   }
01263
01264   /* Configure communication direction : 1Line */
01265   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01266   {
01267     SPI_1LINE_TX(hspi);
01268   }
01269
01270   /* Set the number if data at current transfer */
01271   MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
01272
01273   /* Check if the SPI is already enabled */
01274   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01275   {
01276     /* Enable SPI peripheral */
01277     __HAL_SPI_ENABLE(hspi);
01278   }
01279   else
01280   {
01281     if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_UDR))
01282     {
01283       *((__IO uint8_t *)&hspi->Instance->TXDR) = 0x01U;
01284       __HAL_SPI_CLEAR_UDRFLAG(hspi);
01285       __HAL_SPI_DISABLE(hspi);
01286       __HAL_SPI_ENABLE(hspi);
01287     }
01288   }
01289
01290   if (hspi->Init.Mode == SPI_MODE_MASTER)
01291   {
01292     /* Master transfer start */
01293     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
01294   }
01295
01296   /* Enable TXE and ERR interrupt */
01297   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
01298
01299   __HAL_UNLOCK(hspi);
01300   return errorcode;
01301 }
01302
01303 /**
01304   * @brief  Receive an amount of data in non-blocking mode with Interrupt.
01305   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01306   *               the configuration information for SPI module.
01307   * @param  pData: pointer to data buffer
01308   * @param  Size: amount of data to be sent
01309   * @retval HAL status
01310   */
01311 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01312 {
01313   HAL_StatusTypeDef errorcode = HAL_OK;
01314
01315   /* Check Direction parameter */
01316   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
01317
01318   if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
01319   {
01320     hspi->State = HAL_SPI_STATE_BUSY_RX;
01321     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
01322     return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
01323   }
01324
01325   /* Process Locked */
01326   __HAL_LOCK(hspi);
01327
01328   if (hspi->State != HAL_SPI_STATE_READY)
01329   {
01330     errorcode = HAL_BUSY;
01331     __HAL_UNLOCK(hspi);
01332     return errorcode;
01333   }
01334
01335   if ((pData == NULL) || (Size == 0U))
01336   {
01337     errorcode = HAL_ERROR;
01338     __HAL_UNLOCK(hspi);
01339     return errorcode;
01340   }
01341
01342   /* Set the transaction information */
01343   hspi->State       = HAL_SPI_STATE_BUSY_RX;
01344   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01345   hspi->pRxBuffPtr  = (uint8_t *)pData;
01346   hspi->RxXferSize  = Size;
01347   hspi->RxXferCount = Size;
01348
01349   /* Init field not used in handle to zero */
01350   hspi->pTxBuffPtr  = NULL;
01351   hspi->TxXferSize  = 0U;
01352   hspi->TxXferCount = 0U;
01353   hspi->TxISR       = NULL;
01354
01355   /* Set the function for IT treatment */
01356   if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
01357   {
01358     hspi->RxISR = SPI_RxISR_32BIT;
01359   }
01360   else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01361   {
01362     hspi->RxISR = SPI_RxISR_16BIT;
01363   }
01364   else
01365   {
01366     hspi->RxISR = SPI_RxISR_8BIT;
01367   }
01368
01369   /* Configure communication direction : 1Line */
01370   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01371   {
01372     SPI_1LINE_RX(hspi);
01373   }
01374
01375   /* Note : The SPI must be enabled after unlocking current process
01376             to avoid the risk of SPI interrupt handle execution before current
01377             process unlock */
01378
01379   /* Set the number if data at current transfer */
01380   MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
01381
01382   /* Check if the SPI is already enabled */
01383   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01384   {
01385     /* Enable SPI peripheral */
01386     __HAL_SPI_ENABLE(hspi);
01387   }
01388
01389   if (hspi->Init.Mode == SPI_MODE_MASTER)
01390   {
01391     /* Master transfer start */
01392     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
01393   }
01394
01395   /* Enable TXE and ERR interrupt */
01396   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_EOT | SPI_IT_ERR));
01397
01398   /* Process Unlocked */
01399   __HAL_UNLOCK(hspi);
01400   return errorcode;
01401 }
01402
01403 /**
01404   * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
01405   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01406   *               the configuration information for SPI module.
01407   * @param  pTxData: pointer to transmission data buffer
01408   * @param  pRxData: pointer to reception data buffer
01409   * @param  Size: amount of data to be sent and received
01410   * @retval HAL status
01411   */
01412 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
01413 {
01414   HAL_StatusTypeDef errorcode = HAL_OK;
01415
01416   /* Check Direction parameter */
01417   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
01418
01419   /* Process locked */
01420   __HAL_LOCK(hspi);
01421
01422   if (!((hspi->State == HAL_SPI_STATE_READY) || \
01423         ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
01424   {
01425     errorcode = HAL_BUSY;
01426     __HAL_UNLOCK(hspi);
01427     return errorcode;
01428   }
01429
01430   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01431   {
01432     errorcode = HAL_ERROR;
01433     __HAL_UNLOCK(hspi);
01434     return errorcode;
01435   }
01436
01437   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
01438   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
01439   {
01440     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
01441   }
01442
01443   /* Set the transaction information */
01444   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01445   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
01446   hspi->TxXferSize  = Size;
01447   hspi->TxXferCount = Size;
01448   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
01449   hspi->RxXferSize  = Size;
01450   hspi->RxXferCount = Size;
01451
01452   /* Set the function for IT treatment */
01453   if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
01454   {
01455     hspi->RxISR     = SPI_2linesRxISR_32BIT;
01456     hspi->TxISR     = SPI_2linesTxISR_32BIT;
01457   }
01458   else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01459   {
01460     hspi->RxISR     = SPI_2linesRxISR_16BIT;
01461     hspi->TxISR     = SPI_2linesTxISR_16BIT;
01462   }
01463   else
01464   {
01465     hspi->RxISR     = SPI_2linesRxISR_8BIT;
01466     hspi->TxISR     = SPI_2linesTxISR_8BIT;
01467   }
01468
01469   /* Set the number if data at current transfer */
01470   MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
01471
01472   /* Check if the SPI is already enabled */
01473   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01474   {
01475     /* Enable SPI peripheral */
01476     __HAL_SPI_ENABLE(hspi);
01477   }
01478
01479   if (hspi->Init.Mode == SPI_MODE_MASTER)
01480   {
01481     /* Master transfer start */
01482     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
01483   }
01484
01485   /* Enable TXE, RXNE and ERR interrupt */
01486   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_EOT | SPI_IT_ERR));
01487
01488   /* Process Unlocked */
01489   __HAL_UNLOCK(hspi);
01490   return errorcode;
01491 }
01492
01493 /**
01494   * @brief  Transmit an amount of data in non-blocking mode with DMA.
01495   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01496   *               the configuration information for SPI module.
01497   * @param  pData: pointer to data buffer
01498   * @param  Size: amount of data to be sent
01499   * @retval HAL status
01500   */
01501 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01502 {
01503   HAL_StatusTypeDef errorcode = HAL_OK;
01504
01505   /* Check Direction parameter */
01506   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
01507
01508   /* Process Locked */
01509   __HAL_LOCK(hspi);
01510
01511   if (hspi->State != HAL_SPI_STATE_READY)
01512   {
01513     errorcode = HAL_BUSY;
01514     __HAL_UNLOCK(hspi);
01515     return errorcode;
01516   }
01517
01518   if ((pData == NULL) || (Size == 0U))
01519   {
01520     errorcode = HAL_ERROR;
01521     __HAL_UNLOCK(hspi);
01522     return errorcode;
01523   }
01524
01525   /* Set the transaction information */
01526   hspi->State       = HAL_SPI_STATE_BUSY_TX;
01527   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01528   hspi->pTxBuffPtr  = (uint8_t *)pData;
01529   hspi->TxXferSize  = Size;
01530   hspi->TxXferCount = Size;
01531
01532   /* Init field not used in handle to zero */
01533   hspi->pRxBuffPtr  = NULL;
01534   hspi->TxISR       = NULL;
01535   hspi->RxISR       = NULL;
01536   hspi->RxXferSize  = 0U;
01537   hspi->RxXferCount = 0U;
01538
01539   /* Configure communication direction : 1Line */
01540   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01541   {
01542     SPI_1LINE_TX(hspi);
01543   }
01544
01545   /* Packing mode management is enabled by the DMA settings */
01546   if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))    || \
01547       ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \
01548                                                          (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
01549   {
01550     /* Restriction the DMA data received is not allowed in this mode */
01551     errorcode = HAL_ERROR;
01552     __HAL_UNLOCK(hspi);
01553     return errorcode;
01554   }
01555
01556   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01557   {
01558     /* Set FifoThreshold according the reception data length: 8bit */
01559     SET_BIT(hspi->Instance->CFG1, SPI_FIFO_THRESHOLD_08DATA);
01560   }
01561   else
01562   {
01563     /* Set FifoThreshold according the reception data length: 16bit */
01564     SET_BIT(hspi->Instance->CFG1, SPI_FIFO_THRESHOLD_16DATA);
01565
01566     if ((hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) ||\
01567         (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD))
01568     {
01569       if ((hspi->TxXferSize & 0x1U) == 0x0U)
01570       {
01571         hspi->TxXferCount = hspi->TxXferCount >> 1U;
01572       }
01573       else
01574       {
01575         hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
01576       }
01577     }
01578   }
01579
01580   /* Set the SPI TxDMA Half transfer complete callback */
01581   hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
01582
01583   /* Set the SPI TxDMA transfer complete callback */
01584   hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
01585
01586   /* Set the DMA error callback */
01587   hspi->hdmatx->XferErrorCallback = SPI_DMAError;
01588
01589   /* Set the DMA AbortCpltCallback */
01590   hspi->hdmatx->XferAbortCallback = NULL;
01591
01592   /* Check if the SPI is disabled to edit CFG1 register */
01593   if ((hspi->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE)
01594   {
01595     /* Disable SPI peripheral */
01596     __HAL_SPI_DISABLE(hspi);
01597   }
01598
01599   /* Clear TXDMAEN bit*/
01600   CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
01601
01602   /* Enable the Tx DMA Stream/Channel */
01603   HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, hspi->TxXferCount);
01604
01605   /* Set the number if data at current transfer */
01606   MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
01607
01608   /* Enable Tx DMA Request */
01609   SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
01610
01611   /* Enable SPI peripheral */
01612   __HAL_SPI_ENABLE(hspi);
01613
01614   /* Enable the SPI Error Interrupt Bit */
01615   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
01616
01617   if (hspi->Init.Mode == SPI_MODE_MASTER)
01618   {
01619     /* Master transfer start */
01620     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
01621   }
01622
01623   /* Process Unlocked */
01624   __HAL_UNLOCK(hspi);
01625   return errorcode;
01626 }
01627
01628 /**
01629   * @brief  Receive an amount of data in non-blocking mode with DMA.
01630   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01631   *               the configuration information for SPI module.
01632   * @param  pData: pointer to data buffer
01633   * @note   When the CRC feature is enabled the pData Length must be Size + 1.
01634   * @param  Size: amount of data to be sent
01635   * @retval HAL status
01636   */
01637 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01638 {
01639   HAL_StatusTypeDef errorcode = HAL_OK;
01640
01641   /* Check Direction parameter */
01642   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
01643
01644   if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
01645   {
01646     hspi->State = HAL_SPI_STATE_BUSY_RX;
01647     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
01648     return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
01649   }
01650
01651   /* Process Locked */
01652   __HAL_LOCK(hspi);
01653
01654   if (hspi->State != HAL_SPI_STATE_READY)
01655   {
01656     errorcode = HAL_BUSY;
01657     __HAL_UNLOCK(hspi);
01658     return errorcode;
01659   }
01660
01661   if ((pData == NULL) || (Size == 0U))
01662   {
01663     errorcode = HAL_ERROR;
01664     __HAL_UNLOCK(hspi);
01665     return errorcode;
01666   }
01667
01668   /* Set the transaction information */
01669   hspi->State       = HAL_SPI_STATE_BUSY_RX;
01670   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01671   hspi->pRxBuffPtr  = (uint8_t *)pData;
01672   hspi->RxXferSize  = Size;
01673   hspi->RxXferCount = Size;
01674
01675   /*Init field not used in handle to zero */
01676   hspi->RxISR       = NULL;
01677   hspi->TxISR       = NULL;
01678   hspi->TxXferSize  = 0U;
01679   hspi->TxXferCount = 0U;
01680
01681   /* Configure communication direction : 1Line */
01682   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01683   {
01684     SPI_1LINE_RX(hspi);
01685   }
01686
01687   /* Packing mode management is enabled by the DMA settings */
01688   if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))    || \
01689       ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \
01690                                                      (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
01691   {
01692     /* Restriction the DMA data received is not allowed in this mode */
01693     errorcode = HAL_ERROR;
01694     __HAL_UNLOCK(hspi);
01695     return errorcode;
01696   }
01697
01698   /* Check if the SPI is disabled to edit CFG1 register */
01699   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01700   {
01701     /* Disable SPI peripheral */
01702     __HAL_SPI_DISABLE(hspi);
01703   }
01704
01705   /* Clear RXDMAEN bit */
01706   CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
01707
01708   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01709   {
01710     /* set FifoThreshold according the reception data length: 16bit */
01711     SET_BIT(hspi->Instance->CFG1, SPI_FIFO_THRESHOLD_16DATA);
01712   }
01713   else
01714   {
01715     /* set FifoThreshold according the reception data length: 8bit */
01716     SET_BIT(hspi->Instance->CFG1, SPI_FIFO_THRESHOLD_08DATA);
01717
01718     if ((hspi->RxXferCount & 0x1U) == 0x0U)
01719     {
01720       hspi->RxXferCount = hspi->RxXferCount >> 1U;
01721     }
01722     else
01723     {
01724       hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
01725      }
01726   }
01727
01728   /* Set the SPI RxDMA Half transfer complete callback */
01729   hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
01730
01731   /* Set the SPI Rx DMA transfer complete callback */
01732   hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
01733
01734   /* Set the DMA error callback */
01735   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
01736
01737   /* Set the DMA AbortCpltCallback */
01738   hspi->hdmarx->XferAbortCallback = NULL;
01739
01740   /* Enable the Rx DMA Stream/Channel  */
01741   HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
01742
01743   /* Set the number if data at current transfer */
01744   MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
01745
01746   /* Enable Rx DMA Request */
01747   SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
01748
01749   /* Enable SPI peripheral */
01750   __HAL_SPI_ENABLE(hspi);
01751
01752   /* Enable the SPI Error Interrupt Bit */
01753   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
01754
01755   if (hspi->Init.Mode == SPI_MODE_MASTER)
01756   {
01757     /* Master transfer start */
01758     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
01759   }
01760
01761   /* Process Unlocked */
01762   __HAL_UNLOCK(hspi);
01763   return errorcode;
01764 }
01765
01766 /**
01767   * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
01768   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01769   *               the configuration information for SPI module.
01770   * @param  pTxData: pointer to transmission data buffer
01771   * @param  pRxData: pointer to reception data buffer
01772   * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
01773   * @param  Size: amount of data to be sent
01774   * @retval HAL status
01775   */
01776 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
01777                                               uint16_t Size)
01778 {
01779   HAL_StatusTypeDef errorcode = HAL_OK;
01780
01781   /* Check Direction parameter */
01782   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
01783
01784   /* Process locked */
01785   __HAL_LOCK(hspi);
01786
01787   if (!((hspi->State == HAL_SPI_STATE_READY) ||
01788         ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
01789   {
01790     errorcode = HAL_BUSY;
01791     __HAL_UNLOCK(hspi);
01792     return errorcode;
01793   }
01794
01795   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01796   {
01797     errorcode = HAL_ERROR;
01798     __HAL_UNLOCK(hspi);
01799     return errorcode;
01800   }
01801
01802   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
01803   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
01804   {
01805     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
01806   }
01807
01808   /* Set the transaction information */
01809   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01810   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
01811   hspi->TxXferSize  = Size;
01812   hspi->TxXferCount = Size;
01813   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
01814   hspi->RxXferSize  = Size;
01815   hspi->RxXferCount = Size;
01816
01817   /* Init field not used in handle to zero */
01818   hspi->RxISR       = NULL;
01819   hspi->TxISR       = NULL;
01820
01821   /* Check if the SPI is disabled to edit CFG1 register */
01822   if ((hspi->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE)
01823   {
01824     /* Disable SPI peripheral */
01825     __HAL_SPI_DISABLE(hspi);
01826   }
01827
01828   /* Reset the Tx/Rx DMA bits */
01829   CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
01830
01831   /* Packing mode management is enabled by the DMA settings */
01832   if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))    || \
01833       ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \
01834                                                          (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
01835   {
01836     /* Restriction the DMA data received is not allowed in this mode */
01837     errorcode = HAL_ERROR;
01838     /* Process Unlocked */
01839     __HAL_UNLOCK(hspi);
01840     return errorcode;
01841   }
01842
01843   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01844   {
01845     /* Set FifoThreshold according the reception data length: 16bit */
01846     SET_BIT(hspi->Instance->CFG1, SPI_FIFO_THRESHOLD_16DATA);
01847   }
01848   else
01849   {
01850     /* Set FifoThreshold according the reception data length: 8bit */
01851     SET_BIT(hspi->Instance->CFG1, SPI_FIFO_THRESHOLD_08DATA);
01852
01853     if ((hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) ||\
01854         (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD))
01855
01856     {
01857       if ((hspi->TxXferSize & 0x1U) == 0x0U)
01858       {
01859         hspi->TxXferCount = hspi->TxXferCount >> 1U;
01860       }
01861       else
01862       {
01863         hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
01864       }
01865     }
01866
01867     if ((hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)||\
01868         (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD))
01869     {
01870       /* Set FifoThreshold according the reception data length: 16bit */
01871       SET_BIT(hspi->Instance->CFG1, SPI_FIFO_THRESHOLD_16DATA);
01872
01873       if ((hspi->RxXferCount & 0x1U) == 0x0U)
01874       {
01875         hspi->RxXferCount = hspi->RxXferCount >> 1U;
01876       }
01877       else
01878       {
01879         hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
01880       }
01881     }
01882   }
01883
01884   /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
01885   if (hspi->State == HAL_SPI_STATE_BUSY_RX)
01886   {
01887     /* Set the SPI Rx DMA Half transfer complete callback */
01888     hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
01889     hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;
01890   }
01891   else
01892   {
01893     /* Set the SPI Tx/Rx DMA Half transfer complete callback */
01894     hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
01895     hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
01896   }
01897
01898   /* Set the DMA error callback */
01899   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
01900
01901   /* Set the DMA AbortCpltCallback */
01902   hspi->hdmarx->XferAbortCallback = NULL;
01903
01904   /* Enable the Rx DMA Stream/Channel  */
01905   HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
01906
01907   /* Enable Rx DMA Request */
01908   SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
01909
01910   /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
01911   is performed in DMA reception complete callback  */
01912   hspi->hdmatx->XferHalfCpltCallback = NULL;
01913   hspi->hdmatx->XferCpltCallback     = NULL;
01914   hspi->hdmatx->XferErrorCallback    = NULL;
01915   hspi->hdmatx->XferAbortCallback    = NULL;
01916
01917   /* Enable the Tx DMA Stream/Channel  */
01918   HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, hspi->TxXferCount);
01919
01920   MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
01921
01922   /* Enable Tx DMA Request */
01923   SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
01924
01925   /* Enable SPI peripheral */
01926   __HAL_SPI_ENABLE(hspi);
01927
01928   /* Enable the SPI Error Interrupt Bit */
01929   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
01930
01931   if (hspi->Init.Mode == SPI_MODE_MASTER)
01932   {
01933     /* Master transfer start */
01934     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
01935   }
01936
01937   /* Process Unlocked */
01938   __HAL_UNLOCK(hspi);
01939   return errorcode;
01940 }
01941
01942 /**
01943   * @brief  Abort ongoing transfer (blocking mode).
01944   * @param  hspi SPI handle.
01945   * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
01946   *         started in Interrupt or DMA mode.
01947   * @note   This procedure performs following operations :
01948   *          + Disable SPI Interrupts (depending of transfer direction)
01949   *          + Disable the DMA transfer in the peripheral register (if enabled)
01950   *          + Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01951   *          + Set handle State to READY.
01952   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01953   * @retval HAL status
01954 */
01955 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
01956 {
01957   HAL_StatusTypeDef errorcode;
01958   __IO uint32_t count, resetcount;
01959
01960   /* Initialized local variable  */
01961   errorcode = HAL_OK;
01962   resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
01963   count = resetcount;
01964
01965   /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
01966   if (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_TXE))
01967   {
01968     hspi->TxISR = SPI_AbortTx_ISR;
01969     /* Wait HAL_SPI_STATE_ABORT state */
01970     do
01971     {
01972       if (count-- == 0U)
01973       {
01974         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
01975         break;
01976       }
01977     }
01978     while (hspi->State != HAL_SPI_STATE_ABORT);
01979     /* Reset Timeout Counter */
01980     count = resetcount;
01981   }
01982
01983   if (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_RXNE))
01984   {
01985     hspi->RxISR = SPI_AbortRx_ISR;
01986     /* Wait HAL_SPI_STATE_ABORT state */
01987     do
01988     {
01989       if (count-- == 0U)
01990       {
01991         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
01992         break;
01993       }
01994     }
01995     while (hspi->State != HAL_SPI_STATE_ABORT);
01996     /* Reset Timeout Counter */
01997     count = resetcount;
01998   }
01999
02000   /* Clear ERRIE interrupts in case of DMA Mode */
02001   CLEAR_BIT(hspi->Instance->IER, SPI_IT_ERR);
02002
02003   /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
02004   if ((HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN)))
02005   {
02006     /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
02007     if (hspi->hdmatx != NULL)
02008     {
02009       /* Set the SPI DMA Abort callback :
02010       will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
02011       hspi->hdmatx->XferAbortCallback = NULL;
02012
02013       /* Abort DMA Tx Handle linked to SPI Peripheral */
02014       if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
02015       {
02016         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02017       }
02018
02019       /* Disable SPI Peripheral */
02020       __HAL_SPI_DISABLE(hspi);
02021
02022       /* Disable Tx DMA Request */
02023       CLEAR_BIT(hspi->Instance->CFG1, (SPI_CFG1_TXDMAEN));
02024
02025       if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
02026       {
02027         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02028       }
02029
02030
02031       /* Empty the FRLVL fifo */
02032       if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
02033       {
02034         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02035       }
02036     }
02037     /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
02038     if (hspi->hdmarx != NULL)
02039     {
02040       /* Set the SPI DMA Abort callback :
02041       will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
02042       hspi->hdmarx->XferAbortCallback = NULL;
02043
02044       /* Abort DMA Rx Handle linked to SPI Peripheral */
02045       if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
02046       {
02047         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02048       }
02049
02050       /* Disable peripheral */
02051       __HAL_SPI_DISABLE(hspi);
02052
02053       /* Empty the FRLVL fifo */
02054       if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
02055       {
02056         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02057       }
02058
02059       /* Disable Rx DMA Request */
02060       CLEAR_BIT(hspi->Instance->CFG1, (SPI_CFG1_RXDMAEN));
02061     }
02062   }
02063   /* Reset Tx and Rx transfer counters */
02064   hspi->RxXferCount = 0U;
02065   hspi->TxXferCount = 0U;
02066
02067   /* Check error during Abort procedure */
02068   if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
02069   {
02070     /* return HAL_Error in case of error during Abort procedure */
02071     errorcode = HAL_ERROR;
02072   }
02073   else
02074   {
02075     /* Reset errorCode */
02076     hspi->ErrorCode = HAL_SPI_ERROR_NONE;
02077   }
02078
02079   /* Clear the Error flags in the SR register */
02080   __HAL_SPI_CLEAR_OVRFLAG(hspi);
02081   __HAL_SPI_CLEAR_FREFLAG(hspi);
02082   __HAL_SPI_CLEAR_UDRFLAG(hspi);
02083
02084   /* Restore hspi->state to ready */
02085   hspi->State = HAL_SPI_STATE_READY;
02086
02087   return errorcode;
02088 }
02089
02090 /**
02091   * @brief  Abort ongoing transfer (Interrupt mode).
02092   * @param  hspi SPI handle.
02093   * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
02094   *         started in Interrupt or DMA mode.
02095   * @note   This procedure performs following operations :
02096   *          + Disable SPI Interrupts (depending of transfer direction)
02097   *          + Disable the DMA transfer in the peripheral register (if enabled)
02098   *          + Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
02099   *          + Set handle State to READY
02100   *          + At abort completion, call user abort complete callback.
02101   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
02102   *         considered as completed only when user abort complete callback is executed (not when exiting function).
02103   * @retval HAL status
02104 */
02105 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
02106 {
02107   HAL_StatusTypeDef errorcode;
02108   uint32_t abortcplt ;
02109   __IO uint32_t count, resetcount;
02110
02111   /* Initialized local variable  */
02112   errorcode = HAL_OK;
02113   abortcplt = 1U;
02114   resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
02115   count = resetcount;
02116
02117   /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
02118   if (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_TXE))
02119   {
02120     hspi->TxISR = SPI_AbortTx_ISR;
02121     /* Wait HAL_SPI_STATE_ABORT state */
02122     do
02123     {
02124       if (count-- == 0U)
02125       {
02126         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02127         break;
02128       }
02129     }
02130     while (hspi->State != HAL_SPI_STATE_ABORT);
02131     /* Reset Timeout Counter */
02132     count = resetcount;
02133   }
02134
02135   if (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_RXNE))
02136   {
02137     hspi->RxISR = SPI_AbortRx_ISR;
02138     /* Wait HAL_SPI_STATE_ABORT state */
02139     do
02140     {
02141       if (count-- == 0U)
02142       {
02143         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02144         break;
02145       }
02146     }
02147     while (hspi->State != HAL_SPI_STATE_ABORT);
02148     /* Reset Timeout Counter */
02149     count = resetcount;
02150   }
02151
02152   /* Clear ERRIE interrupts in case of DMA Mode */
02153   CLEAR_BIT(hspi->Instance->IER, SPI_IT_ERR);
02154
02155   /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
02156      before any call to DMA Abort functions */
02157   /* DMA Tx Handle is valid */
02158   if (hspi->hdmatx != NULL)
02159   {
02160     /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
02161        Otherwise, set it to NULL */
02162     if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN))
02163     {
02164       hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
02165     }
02166     else
02167     {
02168       hspi->hdmatx->XferAbortCallback = NULL;
02169     }
02170   }
02171   /* DMA Rx Handle is valid */
02172   if (hspi->hdmarx != NULL)
02173   {
02174     /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
02175        Otherwise, set it to NULL */
02176     if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN))
02177     {
02178       hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
02179     }
02180     else
02181     {
02182       hspi->hdmarx->XferAbortCallback = NULL;
02183     }
02184   }
02185
02186   /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
02187   if ((HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN)))
02188   {
02189     /* Abort the SPI DMA Tx Stream/Channel */
02190     if (hspi->hdmatx != NULL)
02191     {
02192       /* Abort DMA Tx Handle linked to SPI Peripheral */
02193       if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
02194       {
02195         hspi->hdmatx->XferAbortCallback = NULL;
02196         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02197       }
02198       else
02199       {
02200         abortcplt = 0U;
02201       }
02202     }
02203     /* Abort the SPI DMA Rx Stream/Channel */
02204     if (hspi->hdmarx != NULL)
02205     {
02206       /* Abort DMA Rx Handle linked to SPI Peripheral */
02207       if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)
02208       {
02209         hspi->hdmarx->XferAbortCallback = NULL;
02210         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02211         abortcplt = 1U;
02212       }
02213       else
02214       {
02215         abortcplt = 0U;
02216       }
02217     }
02218   }
02219
02220   /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
02221   if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN))
02222   {
02223     /* Abort the SPI DMA Tx Stream/Channel */
02224     if (hspi->hdmatx != NULL)
02225     {
02226       /* Abort DMA Tx Handle linked to SPI Peripheral */
02227       if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
02228       {
02229         hspi->hdmatx->XferAbortCallback = NULL;
02230         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02231       }
02232       else
02233       {
02234         abortcplt = 0U;
02235       }
02236     }
02237   }
02238   /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
02239   if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN))
02240   {
02241     /* Abort the SPI DMA Rx Stream/Channel */
02242     if (hspi->hdmarx != NULL)
02243     {
02244       /* Abort DMA Rx Handle linked to SPI Peripheral */
02245       if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)
02246       {
02247         hspi->hdmarx->XferAbortCallback = NULL;
02248         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02249       }
02250       else
02251       {
02252         abortcplt = 0U;
02253       }
02254     }
02255   }
02256
02257   if (abortcplt == 1U)
02258   {
02259     /* Reset Tx and Rx transfer counters */
02260     hspi->RxXferCount = 0U;
02261     hspi->TxXferCount = 0U;
02262
02263     /* Check error during Abort procedure */
02264     if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
02265     {
02266       /* return HAL_Error in case of error during Abort procedure */
02267       errorcode = HAL_ERROR;
02268     }
02269     else
02270     {
02271       /* Reset errorCode */
02272       hspi->ErrorCode = HAL_SPI_ERROR_NONE;
02273     }
02274
02275     /* Clear the Error flags in the SR register */
02276     __HAL_SPI_CLEAR_OVRFLAG(hspi);
02277     __HAL_SPI_CLEAR_FREFLAG(hspi);
02278     __HAL_SPI_CLEAR_UDRFLAG(hspi);
02279
02280     /* Restore hspi->State to Ready */
02281     hspi->State = HAL_SPI_STATE_READY;
02282
02283     /* As no DMA to be aborted, call directly user Abort complete callback */
02284     HAL_SPI_AbortCpltCallback(hspi);
02285   }
02286
02287   return errorcode;
02288 }
02289
02290 /**
02291   * @brief  Pause the DMA Transfer.
02292   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02293   *               the configuration information for the specified SPI module.
02294   * @retval HAL status
02295   */
02296 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
02297 {
02298   /* Process Locked */
02299   __HAL_LOCK(hspi);
02300
02301   /* Check if the SPI is disabled to edit CFG1 register */
02302   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
02303   {
02304     /* Disable the SPI DMA Tx & Rx requests */
02305     CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
02306   }
02307   else
02308   {
02309     /* Disable SPI peripheral */
02310     __HAL_SPI_DISABLE(hspi);
02311
02312     /* Disable the SPI DMA Tx & Rx requests */
02313     CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
02314
02315     /* Enable SPI peripheral */
02316     __HAL_SPI_ENABLE(hspi);
02317   }
02318
02319   /* Process Unlocked */
02320   __HAL_UNLOCK(hspi);
02321
02322   return HAL_OK;
02323 }
02324
02325 /**
02326   * @brief  Resume the DMA Transfer.
02327   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02328   *               the configuration information for the specified SPI module.
02329   * @retval HAL status
02330   */
02331 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
02332 {
02333   /* Process Locked */
02334   __HAL_LOCK(hspi);
02335
02336   /* Check if the SPI is disabled to edit CFG1 register */
02337   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
02338   {
02339     /* Enable the SPI DMA Tx & Rx requests */
02340     SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
02341   }
02342   else
02343   {
02344     /* Disable SPI peripheral */
02345     __HAL_SPI_DISABLE(hspi);
02346
02347     /* Enable the SPI DMA Tx & Rx requests */
02348     SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
02349
02350     /* Enable SPI peripheral */
02351     __HAL_SPI_ENABLE(hspi);
02352   }
02353
02354   /* Process Unlocked */
02355   __HAL_UNLOCK(hspi);
02356
02357   return HAL_OK;
02358 }
02359
02360 /**
02361   * @brief Stop the DMA Transfer.
02362   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02363   *               the configuration information for the specified SPI module.
02364   * @retval HAL status
02365   */
02366 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
02367 {
02368   /* The Lock is not implemented on this API to allow the user application
02369      to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
02370      when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
02371      and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
02372      */
02373
02374   /* Abort the SPI DMA tx Stream/Channel  */
02375   if (hspi->hdmatx != NULL)
02376   {
02377     HAL_DMA_Abort(hspi->hdmatx);
02378   }
02379   /* Abort the SPI DMA rx Stream/Channel  */
02380   if (hspi->hdmarx != NULL)
02381   {
02382     HAL_DMA_Abort(hspi->hdmarx);
02383   }
02384
02385
02386   /* Check if the SPI is disabled to edit CFG1 register */
02387   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
02388   {
02389     /* Disable the SPI DMA Tx & Rx requests */
02390     CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
02391   }
02392   else
02393   {
02394     /* Disable SPI peripheral */
02395     __HAL_SPI_DISABLE(hspi);
02396
02397     /* Disable the SPI DMA Tx & Rx requests */
02398     CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
02399
02400     /* Enable SPI peripheral */
02401     __HAL_SPI_ENABLE(hspi);
02402   }
02403
02404   hspi->State = HAL_SPI_STATE_READY;
02405   return HAL_OK;
02406 }
02407
02408 /**
02409   * @brief  Handle SPI interrupt request.
02410   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02411   *               the configuration information for the specified SPI module.
02412   * @retval None
02413   */
02414 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
02415 {
02416   uint32_t itsource = hspi->Instance->IER;
02417   uint32_t itflag   = hspi->Instance->SR;
02418
02419   /* SPI in mode Receiver ----------------------------------------------------*/
02420   if (((itflag & SPI_FLAG_OVR) == RESET) &&
02421       ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
02422   {
02423     hspi->RxISR(hspi);
02424     return;
02425   }
02426
02427     /* SPI in mode Receiver ----------------------------------------------------*/
02428   if (((itflag & SPI_FLAG_EOT) != RESET) && ((itsource & SPI_IT_EOT) != RESET))
02429   {
02430     hspi->RxISR(hspi);
02431     return;
02432   }
02433
02434   /* SPI in mode Transmitter -------------------------------------------------*/
02435   if(((itflag & SPI_FLAG_UDR) == RESET) &&
02436      ((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
02437   {
02438     hspi->TxISR(hspi);
02439     return;
02440   }
02441
02442   /* SPI in Error Treatment --------------------------------------------------*/
02443   if (((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE | SPI_FLAG_UDR)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
02444   {
02445     /* SPI Overrun error interrupt occurred ----------------------------------*/
02446     if ((itflag & SPI_FLAG_OVR) != RESET)
02447     {
02448       if (hspi->State != HAL_SPI_STATE_BUSY_TX)
02449       {
02450         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
02451         __HAL_SPI_CLEAR_OVRFLAG(hspi);
02452       }
02453       else
02454       {
02455         __HAL_SPI_CLEAR_OVRFLAG(hspi);
02456         return;
02457       }
02458     }
02459
02460     /* SPI Mode Fault error interrupt occurred -------------------------------*/
02461     if ((itflag & SPI_FLAG_MODF) != RESET)
02462     {
02463       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
02464       __HAL_SPI_CLEAR_MODFFLAG(hspi);
02465     }
02466
02467     /* SPI Frame error interrupt occurred ------------------------------------*/
02468     if ((itflag & SPI_FLAG_FRE) != RESET)
02469     {
02470       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
02471       __HAL_SPI_CLEAR_FREFLAG(hspi);
02472     }
02473
02474     /* SPI Underrun error interrupt occurred ------------------------------------*/
02475     if ((itflag & SPI_FLAG_UDR) != RESET)
02476     {
02477       if (hspi->State != HAL_SPI_STATE_BUSY_RX)
02478       {
02479         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR);
02480         *((__IO uint8_t *)&hspi->Instance->TXDR) = 0x01U;
02481       __HAL_SPI_CLEAR_UDRFLAG(hspi);
02482       }
02483       else
02484       {
02485         __HAL_SPI_CLEAR_UDRFLAG(hspi);
02486         return;
02487       }
02488     }
02489
02490     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02491     {
02492       /* Disable all interrupts */
02493       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
02494
02495       hspi->State = HAL_SPI_STATE_READY;
02496       /* Disable the SPI DMA requests if enabled */
02497       if ((HAL_IS_BIT_SET(itsource, SPI_CFG1_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CFG1_RXDMAEN)))
02498       {
02499         /* Check if the SPI is disabled to edit CFG1 register */
02500         if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
02501         {
02502           /* Disable the SPI DMA requests */
02503           CLEAR_BIT(hspi->Instance->CR2, (SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN));
02504         }
02505         else
02506         {
02507           /* Disable SPI peripheral */
02508           __HAL_SPI_DISABLE(hspi);
02509
02510           /* Disable the SPI DMA requests */
02511           CLEAR_BIT(hspi->Instance->CR2, (SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN));
02512
02513           /* Enable SPI peripheral */
02514           __HAL_SPI_ENABLE(hspi);
02515         }
02516
02517         /* Abort the SPI DMA Rx channel */
02518         if (hspi->hdmarx != NULL)
02519         {
02520           /* Set the SPI DMA Abort callback :
02521           will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
02522           hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
02523           HAL_DMA_Abort_IT(hspi->hdmarx);
02524         }
02525         /* Abort the SPI DMA Tx channel */
02526         if (hspi->hdmatx != NULL)
02527         {
02528           /* Set the SPI DMA Abort callback :
02529           will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
02530           hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
02531           HAL_DMA_Abort_IT(hspi->hdmatx);
02532         }
02533       }
02534       else
02535       {
02536         /* Call user error callback */
02537         HAL_SPI_ErrorCallback(hspi);
02538       }
02539     }
02540     return;
02541   }
02542 }
02543
02544 /**
02545   * @brief Tx Transfer completed callback.
02546   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02547   *               the configuration information for SPI module.
02548   * @retval None
02549   */
02550 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
02551 {
02552   /* Prevent unused argument(s) compilation warning */
02553   UNUSED(hspi);
02554
02555   /* NOTE : This function should not be modified, when the callback is needed,
02556             the HAL_SPI_TxCpltCallback should be implemented in the user file
02557    */
02558 }
02559
02560 /**
02561   * @brief Rx Transfer completed callback.
02562   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02563   *               the configuration information for SPI module.
02564   * @retval None
02565   */
02566 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
02567 {
02568   /* Prevent unused argument(s) compilation warning */
02569   UNUSED(hspi);
02570
02571   /* NOTE : This function should not be modified, when the callback is needed,
02572             the HAL_SPI_RxCpltCallback should be implemented in the user file
02573    */
02574 }
02575
02576 /**
02577   * @brief Tx and Rx Transfer completed callback.
02578   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02579   *               the configuration information for SPI module.
02580   * @retval None
02581   */
02582 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
02583 {
02584   /* Prevent unused argument(s) compilation warning */
02585   UNUSED(hspi);
02586
02587   /* NOTE : This function should not be modified, when the callback is needed,
02588             the HAL_SPI_TxRxCpltCallback should be implemented in the user file
02589    */
02590 }
02591
02592 /**
02593   * @brief Tx Half Transfer completed callback.
02594   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02595   *               the configuration information for SPI module.
02596   * @retval None
02597   */
02598 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
02599 {
02600   /* Prevent unused argument(s) compilation warning */
02601   UNUSED(hspi);
02602
02603   /* NOTE : This function should not be modified, when the callback is needed,
02604             the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
02605    */
02606 }
02607
02608 /**
02609   * @brief Rx Half Transfer completed callback.
02610   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02611   *               the configuration information for SPI module.
02612   * @retval None
02613   */
02614 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
02615 {
02616   /* Prevent unused argument(s) compilation warning */
02617   UNUSED(hspi);
02618
02619   /* NOTE : This function should not be modified, when the callback is needed,
02620             the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
02621    */
02622 }
02623
02624 /**
02625   * @brief Tx and Rx Half Transfer callback.
02626   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02627   *               the configuration information for SPI module.
02628   * @retval None
02629   */
02630 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
02631 {
02632   /* Prevent unused argument(s) compilation warning */
02633   UNUSED(hspi);
02634
02635   /* NOTE : This function should not be modified, when the callback is needed,
02636             the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
02637    */
02638 }
02639
02640 /**
02641   * @brief SPI error callback.
02642   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02643   *               the configuration information for SPI module.
02644   * @retval None
02645   */
02646 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
02647 {
02648   /* Prevent unused argument(s) compilation warning */
02649   UNUSED(hspi);
02650
02651   /* NOTE : This function should not be modified, when the callback is needed,
02652             the HAL_SPI_ErrorCallback should be implemented in the user file
02653    */
02654   /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
02655             and user can use HAL_SPI_GetError() API to check the latest error occurred
02656    */
02657 }
02658
02659 /**
02660   * @brief  SPI Abort Complete callback.
02661   * @param  hspi SPI handle.
02662   * @retval None
02663   */
02664 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
02665 {
02666   /* Prevent unused argument(s) compilation warning */
02667   UNUSED(hspi);
02668
02669   /* NOTE : This function should not be modified, when the callback is needed,
02670             the HAL_SPI_AbortCpltCallback can be implemented in the user file.
02671    */
02672 }
02673
02674 /**
02675   * @}
02676   */
02677
02678 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
02679   * @brief   SPI control functions
02680   *
02681 @verbatim
02682  ===============================================================================
02683                       ##### Peripheral State and Errors functions #####
02684  ===============================================================================
02685     [..]
02686     This subsection provides a set of functions allowing to control the SPI.
02687      (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
02688      (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
02689 @endverbatim
02690   * @{
02691   */
02692
02693 /**
02694   * @brief  Return the SPI handle state.
02695   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02696   *               the configuration information for SPI module.
02697   * @retval SPI state
02698   */
02699 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
02700 {
02701   /* Return SPI handle state */
02702   return hspi->State;
02703 }
02704
02705 /**
02706   * @brief  Return the SPI error code.
02707   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02708   *               the configuration information for SPI module.
02709   * @retval SPI error code in bitmap format
02710   */
02711 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
02712 {
02713   /* Return SPI ErrorCode */
02714   return hspi->ErrorCode;
02715 }
02716
02717 /**
02718   * @}
02719   */
02720
02721 /**
02722   * @}
02723   */
02724
02725 /** @addtogroup SPI_Private_Functions
02726   * @brief   Private functions
02727   * @{
02728   */
02729
02730 /**
02731   * @brief DMA SPI transmit process complete callback.
02732   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02733   *               the configuration information for the specified DMA module.
02734   * @retval None
02735   */
02736 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
02737 {
02738   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02739
02740   /* DMA Normal Mode */
02741   if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_CIRC)) != DMA_SxCR_CIRC)
02742   {
02743     /* Disable ERR interrupt */
02744     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
02745
02746     /* Check if the SPI is disabled to edit CFG1 register */
02747     if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
02748     {
02749       /* Disable Tx DMA Request */
02750       CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
02751     }
02752     else
02753     {
02754       /* Disable SPI peripheral */
02755       __HAL_SPI_DISABLE(hspi);
02756
02757       /* Disable Tx DMA Request */
02758       CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
02759
02760       /* Enable SPI peripheral */
02761       __HAL_SPI_ENABLE(hspi);
02762     }
02763
02764     __HAL_SPI_CLEAR_EOTFLAG(hspi);
02765     __HAL_SPI_CLEAR_TXTFFLAG(hspi);
02766
02767     /* Clear overrun flag in 2 Lines communication mode because received data is not read */
02768     if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
02769     {
02770       __HAL_SPI_CLEAR_OVRFLAG(hspi);
02771     }
02772
02773     /* Clear underrun flag in 1 Line communication mode because transmitted is not feeded */
02774     if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
02775     {
02776       __HAL_SPI_CLEAR_UDRFLAG(hspi);
02777     }
02778
02779     hspi->TxXferCount = 0U;
02780     hspi->State = HAL_SPI_STATE_READY;
02781
02782     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02783     {
02784       HAL_SPI_ErrorCallback(hspi);
02785       return;
02786     }
02787   }
02788   HAL_SPI_TxCpltCallback(hspi);
02789 }
02790
02791 /**
02792   * @brief DMA SPI receive process complete callback.
02793   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02794   *               the configuration information for the specified DMA module.
02795   * @retval None
02796   */
02797 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
02798 {
02799   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02800
02801   /* DMA Normal Mode */
02802   if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_CIRC)) != DMA_SxCR_CIRC)
02803   {
02804     /* Disable ERR interrupt */
02805     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
02806
02807     /* Check if the SPI is disabled to edit CFG1 register */
02808     if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
02809     {
02810       /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
02811       CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
02812     }
02813     else
02814     {
02815       /* Disable SPI peripheral */
02816       __HAL_SPI_DISABLE(hspi);
02817
02818       /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
02819       CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
02820
02821       /* Enable SPI peripheral */
02822       __HAL_SPI_ENABLE(hspi);
02823     }
02824
02825     __HAL_SPI_CLEAR_EOTFLAG(hspi);
02826     __HAL_SPI_CLEAR_TXTFFLAG(hspi);
02827
02828     hspi->RxXferCount = 0U;
02829     hspi->State = HAL_SPI_STATE_READY;
02830
02831 #ifdef USE_SPI_CRC
02832     /* Check if CRC error occurred */
02833     if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
02834     {
02835       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
02836       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
02837     }
02838 #endif /* USE_SPI_CRC */
02839
02840     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02841     {
02842       HAL_SPI_ErrorCallback(hspi);
02843       return;
02844     }
02845   }
02846   HAL_SPI_RxCpltCallback(hspi);
02847 }
02848
02849 /**
02850   * @brief  DMA SPI transmit receive process complete callback.
02851   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02852   *               the configuration information for the specified DMA module.
02853   * @retval None
02854   */
02855 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
02856 {
02857   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02858   uint32_t tickstart = 0U;
02859
02860   /* Init tickstart for timeout management*/
02861   tickstart = HAL_GetTick();
02862
02863   /* DMA Normal Mode */
02864   if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_CIRC)) != DMA_SxCR_CIRC)
02865   {
02866     /* Disable ERR interrupt */
02867     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
02868
02869     /* Check the end of the transaction */
02870      if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
02871     {
02872       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
02873     }
02874
02875     /* Check if the SPI is disabled to edit CFG1 register */
02876     if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
02877     {
02878       /* Disable Rx/Tx DMA Request */
02879       CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
02880     }
02881     else
02882     {
02883       /* Disable SPI peripheral */
02884       __HAL_SPI_DISABLE(hspi);
02885
02886       /* Disable Rx/Tx DMA Request */
02887       CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
02888
02889       /* Enable SPI peripheral */
02890       __HAL_SPI_ENABLE(hspi);
02891     }
02892
02893     hspi->TxXferCount = 0U;
02894     hspi->RxXferCount = 0U;
02895     hspi->State = HAL_SPI_STATE_READY;
02896
02897 #ifdef USE_SPI_CRC
02898     /* Check if CRC error occurred */
02899     if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
02900     {
02901       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
02902       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
02903     }
02904 #endif /* USE_SPI_CRC */
02905
02906     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02907     {
02908       HAL_SPI_ErrorCallback(hspi);
02909       return;
02910     }
02911   }
02912   HAL_SPI_TxRxCpltCallback(hspi);
02913 }
02914
02915 /**
02916   * @brief  DMA SPI half transmit process complete callback.
02917   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02918   *               the configuration information for the specified DMA module.
02919   * @retval None
02920   */
02921 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
02922 {
02923   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02924
02925   HAL_SPI_TxHalfCpltCallback(hspi);
02926 }
02927
02928 /**
02929   * @brief  DMA SPI half receive process complete callback
02930   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02931   *               the configuration information for the specified DMA module.
02932   * @retval None
02933   */
02934 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
02935 {
02936   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02937
02938   HAL_SPI_RxHalfCpltCallback(hspi);
02939 }
02940
02941 /**
02942   * @brief  DMA SPI half transmit receive process complete callback.
02943   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02944   *               the configuration information for the specified DMA module.
02945   * @retval None
02946   */
02947 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
02948 {
02949   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02950
02951   HAL_SPI_TxRxHalfCpltCallback(hspi);
02952 }
02953
02954 /**
02955   * @brief  DMA SPI communication error callback.
02956   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02957   *               the configuration information for the specified DMA module.
02958   * @retval None
02959   */
02960 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
02961 {
02962   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02963
02964   /* Check if the SPI is disabled to edit CFG1 register */
02965   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
02966   {
02967     /* Stop the disable DMA transfer on SPI side */
02968     CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
02969   }
02970   else
02971   {
02972     /* Disable SPI peripheral */
02973     __HAL_SPI_DISABLE(hspi);
02974
02975     /* Stop the disable DMA transfer on SPI side */
02976     CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
02977
02978     /* Enable SPI peripheral */
02979     __HAL_SPI_ENABLE(hspi);
02980   }
02981
02982   SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02983   hspi->State = HAL_SPI_STATE_READY;
02984   HAL_SPI_ErrorCallback(hspi);
02985 }
02986
02987 /**
02988   * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error
02989   *         (To be called at end of DMA Abort procedure following error occurrence).
02990   * @param  hdma DMA handle.
02991   * @retval None
02992   */
02993 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02994 {
02995   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02996   hspi->RxXferCount = 0U;
02997   hspi->TxXferCount = 0U;
02998
02999   HAL_SPI_ErrorCallback(hspi);
03000 }
03001
03002 /**
03003   * @brief  DMA SPI Tx communication abort callback, when initiated by user
03004   *         (To be called at end of DMA Tx Abort procedure following user abort request).
03005   * @note   When this callback is executed, User Abort complete call back is called only if no
03006   *         Abort still ongoing for Rx DMA Handle.
03007   * @param  hdma DMA handle.
03008   * @retval None
03009   */
03010 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
03011 {
03012   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03013
03014   hspi->hdmatx->XferAbortCallback = NULL;
03015
03016   /* Check if the SPI is disabled to edit CFG1 register */
03017   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
03018   {
03019     /* Disable Tx DMA Request */
03020     CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
03021   }
03022   else
03023   {
03024     /* Disable SPI peripheral */
03025     __HAL_SPI_DISABLE(hspi);
03026
03027     /* Disable Tx DMA Request */
03028     CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
03029
03030     /* Enable SPI peripheral */
03031     __HAL_SPI_ENABLE(hspi);
03032   }
03033
03034   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03035   {
03036     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03037   }
03038
03039   /* Disable SPI Peripheral */
03040   __HAL_SPI_DISABLE(hspi);
03041
03042   /* Empty the FRLVL fifo */
03043   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03044   {
03045     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03046   }
03047
03048   /* Check if an Abort process is still ongoing */
03049   if (hspi->hdmarx != NULL)
03050   {
03051     if (hspi->hdmarx->XferAbortCallback != NULL)
03052     {
03053       return;
03054     }
03055   }
03056
03057   /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
03058   hspi->RxXferCount = 0U;
03059   hspi->TxXferCount = 0U;
03060
03061   /* Check no error during Abort procedure */
03062   if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
03063   {
03064     /* Reset errorCode */
03065     hspi->ErrorCode = HAL_SPI_ERROR_NONE;
03066   }
03067
03068   /* Clear the Error flags in the SR register */
03069   __HAL_SPI_CLEAR_OVRFLAG(hspi);
03070   __HAL_SPI_CLEAR_FREFLAG(hspi);
03071   __HAL_SPI_CLEAR_UDRFLAG(hspi);
03072
03073   /* Restore hspi->State to Ready */
03074   hspi->State  = HAL_SPI_STATE_READY;
03075
03076   /* Call user Abort complete callback */
03077   HAL_SPI_AbortCpltCallback(hspi);
03078 }
03079
03080 /**
03081   * @brief  DMA SPI Rx communication abort callback, when initiated by user
03082   *         (To be called at end of DMA Rx Abort procedure following user abort request).
03083   * @note   When this callback is executed, User Abort complete call back is called only if no
03084   *         Abort still ongoing for Tx DMA Handle.
03085   * @param  hdma DMA handle.
03086   * @retval None
03087   */
03088 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
03089 {
03090   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03091
03092   /* Disable SPI Peripheral */
03093   __HAL_SPI_DISABLE(hspi);
03094
03095   hspi->hdmarx->XferAbortCallback = NULL;
03096
03097   /* Check if the SPI is disabled to edit CFG1 register */
03098   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
03099   {
03100     /* Disable Rx DMA Request */
03101     CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
03102   }
03103   else
03104   {
03105     /* Disable SPI peripheral */
03106     __HAL_SPI_DISABLE(hspi);
03107
03108     /* Disable Rx DMA Request */
03109     CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
03110
03111     /* Enable SPI peripheral */
03112     __HAL_SPI_ENABLE(hspi);
03113   }
03114
03115   /* Empty the FRLVL fifo */
03116   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03117   {
03118     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03119   }
03120
03121   /* Check if an Abort process is still ongoing */
03122   if (hspi->hdmatx != NULL)
03123   {
03124     if (hspi->hdmatx->XferAbortCallback != NULL)
03125     {
03126       return;
03127     }
03128   }
03129
03130   /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
03131   hspi->RxXferCount = 0U;
03132   hspi->TxXferCount = 0U;
03133
03134   /* Check no error during Abort procedure */
03135   if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
03136   {
03137     /* Reset errorCode */
03138     hspi->ErrorCode = HAL_SPI_ERROR_NONE;
03139   }
03140
03141   /* Clear the Error flags in the SR register */
03142   __HAL_SPI_CLEAR_OVRFLAG(hspi);
03143   __HAL_SPI_CLEAR_FREFLAG(hspi);
03144   __HAL_SPI_CLEAR_UDRFLAG(hspi);
03145
03146   /* Restore hspi->State to Ready */
03147   hspi->State  = HAL_SPI_STATE_READY;
03148
03149   /* Call user Abort complete callback */
03150   HAL_SPI_AbortCpltCallback(hspi);
03151 }
03152
03153 /**
03154   * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
03155   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03156   *               the configuration information for SPI module.
03157   * @retval None
03158   */
03159 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
03160 {
03161   /* Receive data in 8 Bit mode */
03162   if (hspi->RxXferCount > 0U)
03163   {
03164     *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->RXDR);
03165     hspi->pRxBuffPtr += sizeof(uint8_t);
03166     hspi->RxXferCount--;
03167   }
03168
03169   /* check end of the reception */
03170   if (hspi->RxXferCount == 0U)
03171   {
03172     /* Disable RXNE interrupt */
03173     __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
03174
03175     if (hspi->TxXferCount == 0U)
03176     {
03177       SPI_CloseRxTx_ISR(hspi);
03178     }
03179   }
03180 }
03181
03182
03183 /**
03184   * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
03185   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03186   *               the configuration information for SPI module.
03187   * @retval None
03188   */
03189 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
03190 {
03191   /* Receive data in 16 Bit mode */
03192   *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->RXDR;
03193   hspi->pRxBuffPtr += sizeof(uint16_t);
03194   hspi->RxXferCount--;
03195
03196   if (hspi->RxXferCount == 0U)
03197   {
03198     /* Disable RXNE interrupt */
03199     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
03200
03201     if (hspi->TxXferCount == 0U)
03202     {
03203       SPI_CloseRxTx_ISR(hspi);
03204     }
03205   }
03206 }
03207
03208
03209 /**
03210   * @brief  Rx 32-bit handler for Transmit and Receive in Interrupt mode.
03211   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03212   *               the configuration information for SPI module.
03213   * @retval None
03214   */
03215 static void SPI_2linesRxISR_32BIT(struct __SPI_HandleTypeDef *hspi)
03216 {
03217   /* Receive data in 32 Bit mode */
03218   *((uint32_t *)hspi->pRxBuffPtr) = hspi->Instance->RXDR;
03219   hspi->pRxBuffPtr += sizeof(uint32_t);
03220   hspi->RxXferCount--;
03221
03222   if (hspi->RxXferCount == 0U)
03223   {
03224     /* Disable RXNE interrupt */
03225     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
03226
03227     if (hspi->TxXferCount == 0U)
03228     {
03229       SPI_CloseRxTx_ISR(hspi);
03230     }
03231   }
03232 }
03233
03234
03235 /**
03236   * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
03237   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03238   *               the configuration information for SPI module.
03239   * @retval None
03240   */
03241 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
03242 {
03243   /* Transmit data in 8 Bit mode */
03244   if (hspi->TxXferCount > 0U)
03245   {
03246     *(__IO uint8_t *)&hspi->Instance->TXDR = *hspi->pTxBuffPtr;
03247     hspi->pTxBuffPtr += sizeof(uint8_t);
03248     hspi->TxXferCount--;
03249   }
03250
03251   /* check the end of the transmission */
03252   if (hspi->TxXferCount == 0U)
03253   {
03254     /* Disable TXE interrupt */
03255     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
03256
03257     if (hspi->RxXferCount == 0U)
03258     {
03259       SPI_CloseRxTx_ISR(hspi);
03260     }
03261   }
03262 }
03263
03264
03265 /**
03266   * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
03267   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03268   *               the configuration information for SPI module.
03269   * @retval None
03270   */
03271 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
03272 {
03273   /* Transmit data in 16 Bit mode */
03274   *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
03275   hspi->pTxBuffPtr += sizeof(uint16_t);
03276   hspi->TxXferCount--;
03277
03278   /* Enable CRC Transmission */
03279   if (hspi->TxXferCount == 0U)
03280   {
03281     /* Disable TXE interrupt */
03282     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
03283
03284     if (hspi->RxXferCount == 0U)
03285     {
03286       SPI_CloseRxTx_ISR(hspi);
03287     }
03288   }
03289 }
03290
03291
03292 /**
03293   * @brief  Tx 32-bit handler for Transmit and Receive in Interrupt mode.
03294   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03295   *               the configuration information for SPI module.
03296   * @retval None
03297   */
03298 static void SPI_2linesTxISR_32BIT(struct __SPI_HandleTypeDef *hspi)
03299 {
03300   /* Transmit data in 32 Bit mode */
03301   *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
03302   hspi->pTxBuffPtr += sizeof(uint32_t);
03303   hspi->TxXferCount--;
03304
03305   /* Enable CRC Transmission */
03306   if (hspi->TxXferCount == 0U)
03307   {
03308     /* Disable TXE interrupt */
03309     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
03310
03311     if (hspi->RxXferCount == 0U)
03312     {
03313       SPI_CloseRxTx_ISR(hspi);
03314     }
03315   }
03316 }
03317
03318
03319 /**
03320   * @brief  Manage the receive 8-bit in Interrupt context.
03321   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03322   *               the configuration information for SPI module.
03323   * @retval None
03324   */
03325 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
03326 {
03327   *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->RXDR);
03328   hspi->pRxBuffPtr += sizeof(uint8_t);
03329   hspi->RxXferCount--;
03330
03331   if (hspi->RxXferCount == 0U)
03332   {
03333     SPI_CloseRx_ISR(hspi);
03334   }
03335 }
03336
03337
03338 /**
03339   * @brief  Manage the 16-bit receive in Interrupt context.
03340   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03341   *               the configuration information for SPI module.
03342   * @retval None
03343   */
03344 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
03345 {
03346   *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->RXDR;
03347   hspi->pRxBuffPtr += sizeof(uint16_t);
03348   hspi->RxXferCount--;
03349
03350   if (hspi->RxXferCount == 0U)
03351   {
03352     SPI_CloseRx_ISR(hspi);
03353   }
03354 }
03355
03356
03357 /**
03358   * @brief  Manage the 32-bit receive in Interrupt context.
03359   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03360   *               the configuration information for SPI module.
03361   * @retval None
03362   */
03363 static void SPI_RxISR_32BIT(struct __SPI_HandleTypeDef *hspi)
03364 {
03365   *((uint32_t *)hspi->pRxBuffPtr) = hspi->Instance->RXDR;
03366   hspi->pRxBuffPtr += sizeof(uint32_t);
03367   hspi->RxXferCount--;
03368
03369   if (hspi->RxXferCount == 0U)
03370   {
03371     SPI_CloseRx_ISR(hspi);
03372   }
03373 }
03374
03375
03376 /**
03377   * @brief  Handle the data 8-bit transmit in Interrupt mode.
03378   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03379   *               the configuration information for SPI module.
03380   * @retval None
03381   */
03382 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
03383 {
03384   *(__IO uint8_t *)&hspi->Instance->TXDR = *((uint8_t *)hspi->pTxBuffPtr);
03385   hspi->pTxBuffPtr += sizeof(uint8_t);
03386   hspi->TxXferCount--;
03387
03388   if (hspi->TxXferCount == 0U)
03389   {
03390     SPI_CloseTx_ISR(hspi);
03391   }
03392 }
03393
03394 /**
03395   * @brief  Handle the data 16-bit transmit in Interrupt mode.
03396   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03397   *               the configuration information for SPI module.
03398   * @retval None
03399   */
03400 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
03401 {
03402   /* Transmit data in 16 Bit mode */
03403   *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
03404   hspi->pTxBuffPtr += sizeof(uint16_t);
03405   hspi->TxXferCount--;
03406
03407   if (hspi->TxXferCount == 0U)
03408   {
03409     SPI_CloseTx_ISR(hspi);
03410   }
03411 }
03412
03413 /**
03414   * @brief  Handle the data 32-bit transmit in Interrupt mode.
03415   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03416   *               the configuration information for SPI module.
03417   * @retval None
03418   */
03419 static void SPI_TxISR_32BIT(struct __SPI_HandleTypeDef *hspi)
03420 {
03421   /* Transmit data in 16 Bit mode */
03422   *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
03423   hspi->pTxBuffPtr += sizeof(uint32_t);
03424   hspi->TxXferCount--;
03425
03426   if (hspi->TxXferCount == 0U)
03427   {
03428     SPI_CloseTx_ISR(hspi);
03429   }
03430 }
03431
03432
03433 /**
03434   * @brief Handle SPI Communication Timeout.
03435   * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
03436   *              the configuration information for SPI module.
03437   * @param Flag: SPI flag to check
03438   * @param State: flag state to check
03439   * @param Timeout: Timeout duration
03440   * @param Tickstart: Tick start value
03441   * @retval HAL status
03442   */
03443 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
03444                                                        uint32_t Timeout, uint32_t Tickstart)
03445 {
03446   while ((hspi->Instance->SR & Flag) != State)
03447   {
03448     if (Timeout != HAL_MAX_DELAY)
03449     {
03450       if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
03451       {
03452         /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
03453         __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
03454
03455         if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
03456                                                      || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
03457         {
03458           /* Disable SPI peripheral */
03459           __HAL_SPI_DISABLE(hspi);
03460         }
03461
03462         hspi->State = HAL_SPI_STATE_READY;
03463
03464         /* Process Unlocked */
03465         __HAL_UNLOCK(hspi);
03466
03467         return HAL_TIMEOUT;
03468       }
03469     }
03470   }
03471
03472   return HAL_OK;
03473 }
03474
03475 /**
03476   * @brief Handle SPI FIFO Communication Timeout.
03477   * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
03478   *              the configuration information for SPI module.
03479   * @param Fifo: Fifo to check
03480   * @param State: Fifo state to check
03481   * @param Timeout: Timeout duration
03482   * @param Tickstart: tick start value
03483   * @retval HAL status
03484   */
03485 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
03486                                                        uint32_t Timeout, uint32_t Tickstart)
03487 {
03488   while ((hspi->Instance->SR & Fifo) != State)
03489   {
03490     if (Timeout != HAL_MAX_DELAY)
03491     {
03492       if ((Timeout == 0) || ((HAL_GetTick() - Tickstart) >= Timeout))
03493       {
03494         /* Disable the SPI and reset the CRC: the CRC value should be cleared
03495            on both master and slave sides in order to resynchronize the master
03496            and slave for their respective CRC calculation */
03497
03498         /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
03499         __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
03500
03501         if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
03502                                                      || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
03503         {
03504           /* Disable SPI peripheral */
03505           __HAL_SPI_DISABLE(hspi);
03506         }
03507
03508         hspi->State = HAL_SPI_STATE_READY;
03509
03510         /* Process Unlocked */
03511         __HAL_UNLOCK(hspi);
03512
03513         return HAL_TIMEOUT;
03514       }
03515     }
03516   }
03517
03518   return HAL_OK;
03519 }
03520
03521 /**
03522   * @brief  Handle the check of the RX transaction complete.
03523   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03524   *               the configuration information for SPI module.
03525   * @param  Timeout: Timeout duration
03526   * @param  Tickstart: tick start value
03527   * @retval None.
03528   */
03529 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout, uint32_t Tickstart)
03530 {
03531     /* wait for Tx data to be sent */
03532   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_EOT, SPI_FLAG_EOT, SPI_DEFAULT_TIMEOUT, Tickstart) != HAL_OK)
03533   {
03534     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03535     return HAL_TIMEOUT;
03536   }
03537   else
03538   {
03539     __HAL_SPI_CLEAR_EOTFLAG(hspi);
03540     __HAL_SPI_CLEAR_TXTFFLAG(hspi);
03541   }
03542
03543   while ( (hspi->Instance->SR & SPI_FLAG_RXWNE) || ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY))
03544   {
03545     /* Receive data in 32 Bit mode */
03546     if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
03547     {
03548       *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
03549       hspi->pRxBuffPtr += sizeof(uint32_t);
03550       hspi->RxXferCount--;
03551     }
03552     /* Receive data in 16 Bit mode */
03553     else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
03554     {
03555       if ((hspi->Instance->SR & SPI_FLAG_RXWNE) && IS_SPI_HIGHEND_INSTANCE(hspi->Instance))
03556       {
03557         *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
03558         hspi->pRxBuffPtr += sizeof(uint32_t);
03559         hspi->RxXferCount-=2;
03560       }
03561       else
03562       {
03563         *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
03564         hspi->pRxBuffPtr += sizeof(uint16_t);
03565         hspi->RxXferCount--;
03566       }
03567     }
03568     /* Receive data in 8 Bit mode */
03569     else
03570     {
03571       if ((hspi->Instance->SR & SPI_FLAG_RXWNE) && IS_SPI_HIGHEND_INSTANCE(hspi->Instance))
03572       {
03573         *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
03574         hspi->pRxBuffPtr += sizeof(uint32_t);
03575         hspi->RxXferCount-=4;
03576       }
03577       else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_FRLVL_QUARTER_FULL)
03578       {
03579         *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
03580         hspi->pRxBuffPtr += sizeof(uint16_t);
03581         hspi->RxXferCount-=2;
03582       }
03583       else
03584       {
03585         (*hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
03586         hspi->pRxBuffPtr += sizeof(uint8_t);
03587         hspi->RxXferCount--;
03588       }
03589     }
03590   }
03591
03592   return HAL_OK;
03593 }
03594
03595 /**
03596   * @brief Handle the check of the RXTX or TX transaction complete.
03597   * @param hspi: SPI handle
03598   * @param Timeout: Timeout duration
03599   * @param Tickstart: tick start value
03600   */
03601 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
03602 {
03603   /* wait for Tx data to be sent */
03604   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_EOT, SPI_FLAG_EOT, SPI_DEFAULT_TIMEOUT, Tickstart) != HAL_OK)
03605   {
03606     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03607     return HAL_TIMEOUT;
03608   }
03609   else
03610   {
03611     __HAL_SPI_CLEAR_EOTFLAG(hspi);
03612     __HAL_SPI_CLEAR_TXTFFLAG(hspi);
03613   }
03614
03615   if (IS_SPI_HIGHEND_INSTANCE(hspi->Instance))
03616   {
03617     while ( (hspi->Instance->SR & SPI_FLAG_RXWNE) || ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY))
03618     {
03619       if (hspi->RxXferCount != 0)
03620       {
03621         /* Receive data in 32 Bit mode */
03622         if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
03623         {
03624           *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
03625           hspi->pRxBuffPtr += sizeof(uint32_t);
03626           hspi->RxXferCount--;
03627         }
03628         /* Receive data in 16 Bit mode */
03629         else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
03630         {
03631           if (hspi->Instance->SR & SPI_FLAG_RXWNE)
03632           {
03633             *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
03634             hspi->pRxBuffPtr += sizeof(uint32_t);
03635             hspi->RxXferCount-=2;
03636           }
03637           else
03638           {
03639             *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
03640             hspi->pRxBuffPtr += sizeof(uint16_t);
03641             hspi->RxXferCount--;
03642           }
03643         }
03644         /* Receive data in 8 Bit mode */
03645         else
03646         {
03647           if (hspi->Instance->SR & SPI_FLAG_RXWNE)
03648           {
03649             *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
03650             hspi->pRxBuffPtr += sizeof(uint32_t);
03651             hspi->RxXferCount-=4;
03652           }
03653           else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_FRLVL_QUARTER_FULL)
03654           {
03655             *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
03656             hspi->pRxBuffPtr += sizeof(uint16_t);
03657             hspi->RxXferCount-=2;
03658           }
03659           else
03660           {
03661             (*hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
03662             hspi->pRxBuffPtr += sizeof(uint8_t);
03663             hspi->RxXferCount--;
03664           }
03665         }
03666       }
03667       else
03668       {
03669         return  HAL_SPIEx_FlushRxFifo(hspi);
03670       }
03671     }
03672   }
03673
03674   return HAL_OK;
03675 }
03676
03677 /**
03678   * @brief  Handle the end of the RXTX transaction.
03679   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03680   *               the configuration information for SPI module.
03681   * @retval None
03682   */
03683 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
03684 {
03685   /* Disable ERR interrupt */
03686   __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR);
03687
03688   __HAL_SPI_CLEAR_EOTFLAG(hspi);
03689   __HAL_SPI_CLEAR_TXTFFLAG(hspi);
03690
03691 #ifdef USE_SPI_CRC
03692   /* Check if CRC error occurred */
03693   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
03694   {
03695     hspi->State = HAL_SPI_STATE_READY;
03696     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03697     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
03698     HAL_SPI_ErrorCallback(hspi);
03699   }
03700   else
03701   {
03702 #endif /* USE_SPI_CRC */
03703     if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
03704     {
03705       if (hspi->State == HAL_SPI_STATE_BUSY_RX)
03706       {
03707         hspi->State = HAL_SPI_STATE_READY;
03708         HAL_SPI_RxCpltCallback(hspi);
03709       }
03710       else
03711       {
03712         hspi->State = HAL_SPI_STATE_READY;
03713         HAL_SPI_TxRxCpltCallback(hspi);
03714       }
03715     }
03716     else
03717     {
03718       hspi->State = HAL_SPI_STATE_READY;
03719       HAL_SPI_ErrorCallback(hspi);
03720     }
03721 #ifdef USE_SPI_CRC
03722   }
03723 #endif /* USE_SPI_CRC */
03724 }
03725
03726 /**
03727   * @brief  Handle the end of the RX transaction.
03728   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03729   *               the configuration information for SPI module.
03730   * @retval None
03731   */
03732 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
03733 {
03734   /* Disable RXNE and ERR interrupt */
03735   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
03736
03737   __HAL_SPI_CLEAR_EOTFLAG(hspi);
03738   __HAL_SPI_CLEAR_TXTFFLAG(hspi);
03739
03740   /* Clear underrun flag in 1 Line communication mode because transmitted is not feeded */
03741   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
03742   {
03743     *((__IO uint8_t *)&hspi->Instance->TXDR) = 0x01U;
03744     __HAL_SPI_CLEAR_UDRFLAG(hspi);
03745   }
03746
03747   hspi->State = HAL_SPI_STATE_READY;
03748
03749 #ifdef USE_SPI_CRC
03750   /* Check if CRC error occurred */
03751   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
03752   {
03753     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03754     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
03755     HAL_SPI_ErrorCallback(hspi);
03756   }
03757   else
03758   {
03759 #endif /* USE_SPI_CRC */
03760     if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
03761     {
03762       HAL_SPI_RxCpltCallback(hspi);
03763     }
03764     else
03765     {
03766       HAL_SPI_ErrorCallback(hspi);
03767     }
03768 #ifdef USE_SPI_CRC
03769   }
03770 #endif /* USE_SPI_CRC */
03771 }
03772
03773 /**
03774   * @brief  Handle the end of the TX transaction.
03775   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03776   *               the configuration information for SPI module.
03777   * @retval None
03778   */
03779 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
03780 {
03781   /* Disable TXE and ERR interrupt */
03782   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
03783
03784   __HAL_SPI_CLEAR_EOTFLAG(hspi);
03785   __HAL_SPI_CLEAR_TXTFFLAG(hspi);
03786
03787   /* Clear overrun flag in 2 Lines communication mode because received is not read */
03788   if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
03789   {
03790     __HAL_SPI_CLEAR_OVRFLAG(hspi);
03791   }
03792
03793   hspi->State = HAL_SPI_STATE_READY;
03794   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
03795   {
03796     HAL_SPI_ErrorCallback(hspi);
03797   }
03798   else
03799   {
03800     HAL_SPI_TxCpltCallback(hspi);
03801   }
03802 }
03803
03804 /**
03805   * @brief  Handle abort a Rx transaction.
03806   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03807   *               the configuration information for SPI module.
03808   * @retval None
03809   */
03810 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
03811 {
03812   uint32_t tickstart = 0U;
03813
03814   /* Init tickstart for timeout managment*/
03815   tickstart = HAL_GetTick();
03816
03817   /* Disable SPI Peripheral */
03818   __HAL_SPI_DISABLE(hspi);
03819
03820   /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
03821   CLEAR_BIT(hspi->Instance->IER, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
03822
03823   while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_RXNE))
03824   {
03825     if ((HAL_GetTick() - tickstart) >=  HAL_MAX_DELAY)
03826     {
03827       hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03828     }
03829   }
03830
03831   /* Empty the FRLVL fifo */
03832   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03833   {
03834     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03835   }
03836
03837   hspi->State = HAL_SPI_STATE_ABORT;
03838 }
03839
03840 /**
03841   * @brief  Handle abort a Tx or Rx/Tx transaction.
03842   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03843   *               the configuration information for SPI module.
03844   * @retval None
03845   */
03846 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
03847 {
03848   uint32_t tickstart = 0U;
03849
03850   /* Init tickstart for timeout managment*/
03851   tickstart = HAL_GetTick();
03852
03853   /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
03854   CLEAR_BIT(hspi->Instance->CR2, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
03855
03856   while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_TXE))
03857   {
03858     if ((HAL_GetTick() - tickstart) >=  HAL_MAX_DELAY)
03859     {
03860       hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03861     }
03862   }
03863
03864   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03865   {
03866     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03867   }
03868
03869   /* Disable SPI Peripheral */
03870   __HAL_SPI_DISABLE(hspi);
03871
03872   /* Empty the FRLVL fifo */
03873   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03874   {
03875     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03876   }
03877
03878   hspi->State = HAL_SPI_STATE_ABORT;
03879 }
03880
03881 /**
03882   * @}
03883   */
03884
03885 #endif /* HAL_SPI_MODULE_ENABLED */
03886
03887 /**
03888   * @}
03889   */
03890
03891 /**
03892   * @}
03893   */
03894
03895 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_spi.h Source File

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stm32h7xx_hal_spi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_spi.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of SPI HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_SPI_H
00040 #define __STM32H7xx_HAL_SPI_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SPI
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup SPI_Exported_Types SPI Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  SPI Configuration Structure definition
00064   */
00065 typedef struct
00066 {
00067     uint32_t Mode;                              /*!< Specifies the SPI operating mode.
00068                                                      This parameter can be a value of @ref SPI_Mode */
00069
00070     uint32_t Direction;                         /*!< Specifies the SPI bidirectional mode state.
00071                                                      This parameter can be a value of @ref SPI_Direction */
00072
00073     uint32_t DataSize;                          /*!< Specifies the SPI data size.
00074                                                      This parameter can be a value of @ref SPI_Data_Size */
00075
00076     uint32_t CLKPolarity;                       /*!< Specifies the serial clock steady state.
00077                                                      This parameter can be a value of @ref SPI_Clock_Polarity */
00078
00079     uint32_t CLKPhase;                          /*!< Specifies the clock active edge for the bit capture.
00080                                                      This parameter can be a value of @ref SPI_Clock_Phase */
00081
00082     uint32_t NSS;                               /*!< Specifies whether the NSS signal is managed by
00083                                                      hardware (NSS pin) or by software using the SSI bit.
00084                                                      This parameter can be a value of @ref SPI_Slave_Select_Management */
00085
00086     uint32_t BaudRatePrescaler;                 /*!< Specifies the Baud Rate prescaler value which will be
00087                                                      used to configure the transmit and receive SCK clock.
00088                                                      This parameter can be a value of @ref SPI_BaudRate_Prescaler
00089                                                      @note The communication clock is derived from the master
00090                                                      clock. The slave clock does not need to be set. */
00091
00092     uint32_t FirstBit;                          /*!< Specifies whether data transfers start from MSB or LSB bit.
00093                                                      This parameter can be a value of @ref SPI_MSB_LSB_Transmission */
00094
00095     uint32_t TIMode;                            /*!< Specifies if the TI mode is enabled or not.
00096                                                      This parameter can be a value of @ref SPI_TI_Mode */
00097
00098     uint32_t CRCCalculation;                    /*!< Specifies if the CRC calculation is enabled or not.
00099                                                      This parameter can be a value of @ref SPI_CRC_Calculation */
00100
00101     uint32_t CRCPolynomial;                     /*!< Specifies the polynomial used for the CRC calculation.
00102                                                      This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */
00103
00104     uint32_t CRCLength;                         /*!< Specifies the CRC Length used for the CRC calculation.
00105                                                      CRC Length is only used with Data8 and Data16, not other data size
00106                                                      This parameter can be a value of @ref SPI_CRC_length */
00107
00108     uint32_t NSSPMode;                          /*!< Specifies whether the NSSP signal is enabled or not .
00109                                                      This parameter can be a value of @ref SPI_NSSP_Mode
00110                                                      This mode is activated by the NSSP bit in the SPIx_CR2 register and
00111                                                      it takes effect only if the SPI interface is configured as Motorola SPI
00112                                                      master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
00113                                                      CPOL setting is ignored). */
00114
00115     uint32_t NSSPolarity;                       /*!< Specifies which level of SS input/output external signal (present on SS pin) is
00116                                                      considered as active one.
00117                                                      This parameter can be a value of @ref SPI_NSS_Polarity */
00118
00119     uint32_t FifoThreshold;                     /*!< Specifies the FIFO threshold level.
00120                                                      This parameter can be a value of @ref SPI_Fifo_Threshold */
00121
00122     uint32_t TxCRCInitializationPattern;        /*!< Specifies the transmitter CRC initialization Pattern used for the CRC calculation.
00123                                                      This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */
00124
00125     uint32_t RxCRCInitializationPattern;        /*!< Specifies the receiver CRC initialization Pattern used for the CRC calculation.
00126                                                      This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */
00127
00128     uint32_t MasterSSIdleness;                  /*!< Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted
00129                                                      additionally between active edge of SS and first data transaction start in master mode.
00130                                                      This parameter can be a value of @ref SPI_Master_SS_Idleness */
00131
00132     uint32_t MasterInterDataIdleness;           /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between
00133                                                      two consecutive data frames in master mode
00134                                                      This parameter can be a value of @ref SPI_Master_InterData_Idleness */
00135
00136     uint32_t MasterReceiverAutoSusp;            /*!< Control continuous SPI transfer in master receiver mode and automatic management
00137                                                      in order to avoid overrun condition.
00138                                                      This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/
00139
00140     uint32_t MasterKeepIOState;                 /*!< Control of Alternate function GPIOs state
00141                                                      This parameter can be a value of @ref SPI_Master_Keep_IO_State */
00142
00143     uint32_t IOSwap;                            /*!< Invert MISO/MOSI alternate functions
00144                                                      This parameter can be a value of @ref SPI_IO_Swap */
00145
00146 } SPI_InitTypeDef;
00147
00148 /**
00149   * @brief  HAL SPI State structure definition
00150   */
00151 typedef enum
00152 {
00153     HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */
00154     HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */
00155     HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */
00156     HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */
00157     HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */
00158     HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */
00159     HAL_SPI_STATE_ERROR      = 0x06U,    /*!< SPI error state                                    */
00160     HAL_SPI_STATE_ABORT      = 0x07U     /*!< SPI abort is ongoing                               */
00161 } HAL_SPI_StateTypeDef;
00162
00163 /**
00164   * @brief  SPI handle Structure definition
00165   */
00166 typedef struct __SPI_HandleTypeDef
00167 {
00168     SPI_TypeDef                *Instance;                    /*!< SPI registers base address               */
00169
00170     SPI_InitTypeDef            Init;                         /*!< SPI communication parameters             */
00171
00172     uint8_t                    *pTxBuffPtr;                  /*!< Pointer to SPI Tx transfer Buffer        */
00173
00174     uint16_t                   TxXferSize;                   /*!< SPI Tx Transfer size                     */
00175
00176     __IO uint16_t              TxXferCount;                  /*!< SPI Tx Transfer Counter                  */
00177
00178     uint8_t                    *pRxBuffPtr;                  /*!< Pointer to SPI Rx transfer Buffer        */
00179
00180     uint16_t                   RxXferSize;                   /*!< SPI Rx Transfer size                     */
00181
00182     __IO uint16_t              RxXferCount;                  /*!< SPI Rx Transfer Counter                  */
00183
00184     uint32_t                   CRCSize;                      /*!< SPI CRC size used for the transfer       */
00185
00186     void (*RxISR)(struct __SPI_HandleTypeDef *hspi);         /*!< function pointer on Rx ISR               */
00187
00188     void (*TxISR)(struct __SPI_HandleTypeDef *hspi);         /*!< function pointer on Tx ISR               */
00189
00190     DMA_HandleTypeDef          *hdmatx;                      /*!< SPI Tx DMA Handle parameters             */
00191
00192     DMA_HandleTypeDef          *hdmarx;                      /*!< SPI Rx DMA Handle parameters             */
00193
00194     HAL_LockTypeDef            Lock;                         /*!< Locking object                           */
00195
00196     __IO HAL_SPI_StateTypeDef  State;                        /*!< SPI communication state                  */
00197
00198     __IO uint32_t              ErrorCode;                    /*!< SPI Error code                           */
00199
00200 } SPI_HandleTypeDef;
00201
00202 /**
00203   * @}
00204   */
00205
00206 /* Exported constants --------------------------------------------------------*/
00207
00208 /** @defgroup SPI_Exported_Constants SPI Exported Constants
00209   * @{
00210   */
00211
00212 /** @defgroup SPI_FIFO_Type SPI FIFO Type
00213   * @{
00214   */
00215 #define SPI_LOWEND_FIFO_SIZE            8U
00216 #define SPI_HIGHEND_FIFO_SIZE           16U
00217 /**
00218   * @}
00219   */
00220
00221 /** @defgroup SPI_Error_Code SPI Error Codes
00222   * @{
00223   */
00224 #define HAL_SPI_ERROR_NONE              (0x00000000U)   /*!< No error                               */
00225 #define HAL_SPI_ERROR_MODF              (0x00000001U)   /*!< MODF error                             */
00226 #define HAL_SPI_ERROR_CRC               (0x00000002U)   /*!< CRC error                              */
00227 #define HAL_SPI_ERROR_OVR               (0x00000004U)   /*!< OVR error                              */
00228 #define HAL_SPI_ERROR_FRE               (0x00000008U)   /*!< FRE error                              */
00229 #define HAL_SPI_ERROR_DMA               (0x00000010U)   /*!< DMA transfer error                     */
00230 #define HAL_SPI_ERROR_FLAG              (0x00000020U)   /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
00231 #define HAL_SPI_ERROR_ABORT             (0x00000040U)   /*!< Error during SPI Abort procedure       */
00232 #define HAL_SPI_ERROR_UDR               (0x00000080U)   /*!< Underrun error                         */
00233 #define HAL_SPI_ERROR_TIMEOUT           (0x00000100U)   /*!< Timeout error                          */
00234 #define HAL_SPI_ERROR_UNKNOW            (0x00000200U)   /*!< Unknow error                           */
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup SPI_Mode SPI Mode
00240   * @{
00241   */
00242 #define SPI_MODE_SLAVE                  (0x00000000U)
00243 #define SPI_MODE_MASTER                 SPI_CFG2_MASTER
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup SPI_Direction SPI Direction Mode
00249   * @{
00250   */
00251 #define SPI_DIRECTION_2LINES            (0x00000000U)
00252 #define SPI_DIRECTION_2LINES_TXONLY     SPI_CFG2_COMM_0
00253 #define SPI_DIRECTION_2LINES_RXONLY     SPI_CFG2_COMM_1
00254 #define SPI_DIRECTION_1LINE             SPI_CFG2_COMM
00255 /**
00256   * @}
00257   */
00258
00259 /** @defgroup SPI_Data_Size SPI Data Size
00260   * @{
00261   */
00262 #define SPI_DATASIZE_4BIT               (0x00000003U)
00263 #define SPI_DATASIZE_5BIT               (0x00000004U)
00264 #define SPI_DATASIZE_6BIT               (0x00000005U)
00265 #define SPI_DATASIZE_7BIT               (0x00000006U)
00266 #define SPI_DATASIZE_8BIT               (0x00000007U)
00267 #define SPI_DATASIZE_9BIT               (0x00000008U)
00268 #define SPI_DATASIZE_10BIT              (0x00000009U)
00269 #define SPI_DATASIZE_11BIT              (0x0000000AU)
00270 #define SPI_DATASIZE_12BIT              (0x0000000BU)
00271 #define SPI_DATASIZE_13BIT              (0x0000000CU)
00272 #define SPI_DATASIZE_14BIT              (0x0000000DU)
00273 #define SPI_DATASIZE_15BIT              (0x0000000EU)
00274 #define SPI_DATASIZE_16BIT              (0x0000000FU)
00275 #define SPI_DATASIZE_17BIT              (0x00000010U)
00276 #define SPI_DATASIZE_18BIT              (0x00000011U)
00277 #define SPI_DATASIZE_19BIT              (0x00000012U)
00278 #define SPI_DATASIZE_20BIT              (0x00000013U)
00279 #define SPI_DATASIZE_21BIT              (0x00000014U)
00280 #define SPI_DATASIZE_22BIT              (0x00000015U)
00281 #define SPI_DATASIZE_23BIT              (0x00000016U)
00282 #define SPI_DATASIZE_24BIT              (0x00000017U)
00283 #define SPI_DATASIZE_25BIT              (0x00000018U)
00284 #define SPI_DATASIZE_26BIT              (0x00000019U)
00285 #define SPI_DATASIZE_27BIT              (0x0000001AU)
00286 #define SPI_DATASIZE_28BIT              (0x0000001BU)
00287 #define SPI_DATASIZE_29BIT              (0x0000001CU)
00288 #define SPI_DATASIZE_30BIT              (0x0000001DU)
00289 #define SPI_DATASIZE_31BIT              (0x0000001EU)
00290 #define SPI_DATASIZE_32BIT              (0x0000001FU)
00291 /**
00292   * @}
00293   */
00294
00295 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
00296   * @{
00297   */
00298 #define SPI_POLARITY_LOW                (0x00000000U)
00299 #define SPI_POLARITY_HIGH               SPI_CFG2_CPOL
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup SPI_Clock_Phase SPI Clock Phase
00305   * @{
00306   */
00307 #define SPI_PHASE_1EDGE                 (0x00000000U)
00308 #define SPI_PHASE_2EDGE                 SPI_CFG2_CPHA
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup SPI_Slave_Select_Management SPI Slave Select Management
00314   * @{
00315   */
00316 #define SPI_NSS_SOFT                    SPI_CFG2_SSM
00317 #define SPI_NSS_HARD_INPUT              (0x00000000U)
00318 #define SPI_NSS_HARD_OUTPUT             SPI_CFG2_SSOE
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
00324   * @{
00325   */
00326 #define SPI_NSS_PULSE_DISABLE           (0x00000000U)
00327 #define SPI_NSS_PULSE_ENABLE            SPI_CFG2_SSOM
00328 /**
00329   * @}
00330   */
00331
00332 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
00333   * @{
00334   */
00335 #define SPI_BAUDRATEPRESCALER_2         (0x00000000U)
00336 #define SPI_BAUDRATEPRESCALER_4         (0x10000000U)
00337 #define SPI_BAUDRATEPRESCALER_8         (0x20000000U)
00338 #define SPI_BAUDRATEPRESCALER_16        (0x30000000U)
00339 #define SPI_BAUDRATEPRESCALER_32        (0x40000000U)
00340 #define SPI_BAUDRATEPRESCALER_64        (0x50000000U)
00341 #define SPI_BAUDRATEPRESCALER_128       (0x60000000U)
00342 #define SPI_BAUDRATEPRESCALER_256       (0x70000000U)
00343 /**
00344   * @}
00345   */
00346
00347 /** @defgroup SPI_MSB_LSB_Transmission SPI MSB LSB Transmission
00348   * @{
00349   */
00350 #define SPI_FIRSTBIT_MSB                (0x00000000U)
00351 #define SPI_FIRSTBIT_LSB                SPI_CFG2_LSBFRST
00352 /**
00353   * @}
00354   */
00355
00356 /** @defgroup SPI_TI_Mode SPI TI Mode
00357   * @{
00358   */
00359 #define SPI_TIMODE_DISABLE              (0x00000000U)
00360 #define SPI_TIMODE_ENABLE               SPI_CFG2_SP_0
00361 /**
00362   * @}
00363   */
00364
00365 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
00366   * @{
00367   */
00368 #define SPI_CRCCALCULATION_DISABLE      (0x00000000U)
00369 #define SPI_CRCCALCULATION_ENABLE       SPI_CFG1_CRCEN
00370 /**
00371   * @}
00372   */
00373
00374 /** @defgroup SPI_CRC_length SPI CRC Length
00375   * @{
00376   */
00377 #define SPI_CRC_LENGTH_DATASIZE         (0x00000000U)
00378 #define SPI_CRC_LENGTH_4BIT             (0x00030000U)
00379 #define SPI_CRC_LENGTH_5BIT             (0x00040000U)
00380 #define SPI_CRC_LENGTH_6BIT             (0x00050000U)
00381 #define SPI_CRC_LENGTH_7BIT             (0x00060000U)
00382 #define SPI_CRC_LENGTH_8BIT             (0x00070000U)
00383 #define SPI_CRC_LENGTH_9BIT             (0x00080000U)
00384 #define SPI_CRC_LENGTH_10BIT            (0x00090000U)
00385 #define SPI_CRC_LENGTH_11BIT            (0x000A0000U)
00386 #define SPI_CRC_LENGTH_12BIT            (0x000B0000U)
00387 #define SPI_CRC_LENGTH_13BIT            (0x000C0000U)
00388 #define SPI_CRC_LENGTH_14BIT            (0x000D0000U)
00389 #define SPI_CRC_LENGTH_15BIT            (0x000E0000U)
00390 #define SPI_CRC_LENGTH_16BIT            (0x000F0000U)
00391 #define SPI_CRC_LENGTH_17BIT            (0x00100000U)
00392 #define SPI_CRC_LENGTH_18BIT            (0x00110000U)
00393 #define SPI_CRC_LENGTH_19BIT            (0x00120000U)
00394 #define SPI_CRC_LENGTH_20BIT            (0x00130000U)
00395 #define SPI_CRC_LENGTH_21BIT            (0x00140000U)
00396 #define SPI_CRC_LENGTH_22BIT            (0x00150000U)
00397 #define SPI_CRC_LENGTH_23BIT            (0x00160000U)
00398 #define SPI_CRC_LENGTH_24BIT            (0x00170000U)
00399 #define SPI_CRC_LENGTH_25BIT            (0x00180000U)
00400 #define SPI_CRC_LENGTH_26BIT            (0x00190000U)
00401 #define SPI_CRC_LENGTH_27BIT            (0x001A0000U)
00402 #define SPI_CRC_LENGTH_28BIT            (0x001B0000U)
00403 #define SPI_CRC_LENGTH_29BIT            (0x001C0000U)
00404 #define SPI_CRC_LENGTH_30BIT            (0x001D0000U)
00405 #define SPI_CRC_LENGTH_31BIT            (0x001E0000U)
00406 #define SPI_CRC_LENGTH_32BIT            (0x001F0000U)
00407 /**
00408   * @}
00409   */
00410
00411 /** @defgroup SPI_Fifo_Threshold SPI Fifo Threshold
00412   * @{
00413   */
00414 #define SPI_FIFO_THRESHOLD_01DATA       (0x00000000U)
00415 #define SPI_FIFO_THRESHOLD_02DATA       (0x00000020U)
00416 #define SPI_FIFO_THRESHOLD_03DATA       (0x00000040U)
00417 #define SPI_FIFO_THRESHOLD_04DATA       (0x00000060U)
00418 #define SPI_FIFO_THRESHOLD_05DATA       (0x00000080U)
00419 #define SPI_FIFO_THRESHOLD_06DATA       (0x000000A0U)
00420 #define SPI_FIFO_THRESHOLD_07DATA       (0x000000C0U)
00421 #define SPI_FIFO_THRESHOLD_08DATA       (0x000000E0U)
00422 #define SPI_FIFO_THRESHOLD_09DATA       (0x00000100U)
00423 #define SPI_FIFO_THRESHOLD_10DATA       (0x00000120U)
00424 #define SPI_FIFO_THRESHOLD_11DATA       (0x00000140U)
00425 #define SPI_FIFO_THRESHOLD_12DATA       (0x00000160U)
00426 #define SPI_FIFO_THRESHOLD_13DATA       (0x00000180U)
00427 #define SPI_FIFO_THRESHOLD_14DATA       (0x000001A0U)
00428 #define SPI_FIFO_THRESHOLD_15DATA       (0x000001C0U)
00429 #define SPI_FIFO_THRESHOLD_16DATA       (0x000001E0U)
00430 /**
00431   * @}
00432   */
00433
00434 /** @defgroup SPI_CRC_Calculation_Initialization_Pattern SPI CRC Calculation Initialization Pattern
00435   * @{
00436   */
00437 #define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN       (0x00000000U)
00438 #define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN        (0x00000001U)
00439 /**
00440   * @}
00441   */
00442
00443 /** @defgroup SPI_NSS_Polarity SPI NSS Polarity
00444   * @{
00445   */
00446 #define SPI_NSS_POLARITY_LOW                          (0x00000000U)
00447 #define SPI_NSS_POLARITY_HIGH                          SPI_CFG2_SSIOP
00448 /**
00449   * @}
00450   */
00451
00452 /** @defgroup SPI_Master_Keep_IO_State Keep IO State
00453   * @{
00454   */
00455 #define SPI_MASTER_KEEP_IO_STATE_DISABLE              (0x00000000U)
00456 #define SPI_MASTER_KEEP_IO_STATE_ENABLE               SPI_CFG2_AFCNTR
00457 /**
00458   * @}
00459   */
00460
00461 /** @defgroup SPI_IO_Swap Control SPI IO Swap
00462   * @{
00463   */
00464 #define SPI_IO_SWAP_DISABLE                           (0x00000000U)
00465 #define SPI_IO_SWAP_ENABLE                            SPI_CFG2_IOSWP
00466 /**
00467   * @}
00468   */
00469
00470 /** @defgroup SPI_Master_SS_Idleness SPI Master SS Ideleness
00471   * @{
00472   */
00473 #define SPI_MASTER_SS_IDLENESS_00CYCLE                (0x00000000U)
00474 #define SPI_MASTER_SS_IDLENESS_01CYCLE                (0x00000001U)
00475 #define SPI_MASTER_SS_IDLENESS_02CYCLE                (0x00000002U)
00476 #define SPI_MASTER_SS_IDLENESS_03CYCLE                (0x00000003U)
00477 #define SPI_MASTER_SS_IDLENESS_04CYCLE                (0x00000004U)
00478 #define SPI_MASTER_SS_IDLENESS_05CYCLE                (0x00000005U)
00479 #define SPI_MASTER_SS_IDLENESS_06CYCLE                (0x00000006U)
00480 #define SPI_MASTER_SS_IDLENESS_07CYCLE                (0x00000007U)
00481 #define SPI_MASTER_SS_IDLENESS_08CYCLE                (0x00000008U)
00482 #define SPI_MASTER_SS_IDLENESS_09CYCLE                (0x00000009U)
00483 #define SPI_MASTER_SS_IDLENESS_10CYCLE                (0x0000000AU)
00484 #define SPI_MASTER_SS_IDLENESS_11CYCLE                (0x0000000BU)
00485 #define SPI_MASTER_SS_IDLENESS_12CYCLE                (0x0000000CU)
00486 #define SPI_MASTER_SS_IDLENESS_13CYCLE                (0x0000000DU)
00487 #define SPI_MASTER_SS_IDLENESS_14CYCLE                (0x0000000EU)
00488 #define SPI_MASTER_SS_IDLENESS_15CYCLE                (0x0000000FU)
00489 /**
00490   * @}
00491   */
00492
00493 /** @defgroup SPI_Master_InterData_Idleness SPI Master Inter-Data Ideleness
00494   * @{
00495   */
00496 #define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE         (0x00000000U)
00497 #define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE         (0x00000001U)
00498 #define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE         (0x00000002U)
00499 #define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE         (0x00000003U)
00500 #define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE         (0x00000004U)
00501 #define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE         (0x00000005U)
00502 #define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE         (0x00000006U)
00503 #define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE         (0x00000007U)
00504 #define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE         (0x00000008U)
00505 #define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE         (0x00000009U)
00506 #define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE         (0x0000000AU)
00507 #define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE         (0x0000000BU)
00508 #define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE         (0x0000000CU)
00509 #define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE         (0x0000000DU)
00510 #define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE         (0x0000000EU)
00511 #define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE         (0x0000000FU)
00512 /**
00513   * @}
00514   */
00515
00516 /** @defgroup SPI_Master_RX_AutoSuspend SPI Master Receiver AutoSuspend
00517   * @{
00518   */
00519 #define SPI_MASTER_RX_AUTOSUSP_DISABLE                (0x00000000U)
00520 #define SPI_MASTER_RX_AUTOSUSP_ENABLE                 SPI_CR1_MASRX
00521 /**
00522   * @}
00523   */
00524
00525 /** @defgroup SPI_Underrun_Detection SPI Underrun Detection
00526   * @{
00527   */
00528 #define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME          (0x00000000U)
00529 #define SPI_UNDERRUN_DETECT_END_DATA_FRAME            SPI_CFG1_UDRDET_0
00530 #define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS          SPI_CFG1_UDRDET_1
00531 /**
00532   * @}
00533   */
00534
00535 /** @defgroup SPI_Underrun_Behaviour SPI Underrun Behaviour
00536   * @{
00537   */
00538 #define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN           (0x00000000U)
00539 #define SPI_UNDERRUN_BEHAV_LAST_RECEIVED              SPI_CFG1_UDRCFG_0
00540 #define SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED           SPI_CFG1_UDRCFG_1
00541 /**
00542   * @}
00543   */
00544
00545 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
00546   * @{
00547   */
00548 #define SPI_IT_TXE                      SPI_IER_TXPIE
00549 #define SPI_IT_RXNE                     SPI_IER_RXPIE
00550 #define SPI_IT_EOT                      SPI_IER_EOTIE
00551 #define SPI_IT_TXTF                     SPI_IER_TXTFIE
00552 #define SPI_IT_ERR                      (SPI_IER_UDRIE | SPI_IER_OVRIE | SPI_IER_TIFREIE | SPI_IER_MODFIE)
00553 /**
00554   * @}
00555   */
00556
00557 /** @defgroup SPI_Flags_definition SPI Flags Definition
00558   * @{
00559   */
00560 #define SPI_FLAG_TXE                    SPI_SR_TXP     /* SPI status flag: Tx buffer empty flag           */
00561 #define SPI_FLAG_RXNE                   SPI_SR_RXP     /* SPI status flag: Rx buffer not empty flag       */
00562 #define SPI_FLAG_UDR                    SPI_SR_UDR     /* SPI Error flag: Underrun flag                   */
00563 #define SPI_FLAG_OVR                    SPI_SR_OVR     /* SPI Error flag: Overrun flag                    */
00564 #define SPI_FLAG_FRE                    SPI_SR_TIFRE   /* SPI Error flag: TI mode frame format error flag */
00565 #define SPI_FLAG_CRCERR                 SPI_SR_CRCE    /* SPI Error flag: CRC error flag                  */
00566 #define SPI_FLAG_MODF                   SPI_SR_MODF    /* SPI Error flag: Mode fault flag                 */
00567 #define SPI_FLAG_FRLVL                  SPI_SR_RXPLVL  /* SPI fifo reception level                        */
00568 #define SPI_FLAG_RXWNE                  SPI_SR_RXWNE   /* SPI RxFIFO Word Not Empty                       */
00569 #define SPI_FLAG_TXTF                   SPI_SR_TXTF    /* SPI Transmission Transfer Filled flag           */
00570 #define SPI_FLAG_EOT                    SPI_SR_EOT     /* SPI fifo transmision complete                   */
00571 /**
00572   * @}
00573   */
00574
00575 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
00576   * @{
00577   */
00578 #define SPI_FRLVL_EMPTY                 (0x00000000U)
00579 #define SPI_FRLVL_QUARTER_FULL          (0x00002000U)
00580 #define SPI_FRLVL_HALF_FULL             (0x00004000U)
00581 #define SPI_FRLVL_FULL                  (0x00006000U)
00582 /**
00583   * @}
00584   */
00585
00586 /**
00587   * @}
00588   */
00589
00590 /* Exported macros -----------------------------------------------------------*/
00591 /** @defgroup SPI_Exported_Macros SPI Exported Macros
00592   * @{
00593   */
00594
00595 /** @brief  Reset SPI handle state.
00596   * @param  __HANDLE__: specifies the SPI Handle.
00597   *         This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
00598   * @retval None
00599   */
00600 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
00601
00602 /** @brief  Enable the specified SPI interrupts.
00603   * @param  __HANDLE__: specifies the SPI Handle.
00604   *         This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
00605   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
00606   *         This parameter can be one of the following values:
00607   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00608   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00609   *            @arg SPI_IT_ERR: Error interrupt enable
00610   * @retval None
00611   */
00612 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
00613
00614 /** @brief  Disable the specified SPI interrupts.
00615   * @param  __HANDLE__: specifies the SPI Handle.
00616   *         This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
00617   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
00618   *         This parameter can be one of the following values:
00619   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00620   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00621   *            @arg SPI_IT_ERR: Error interrupt enable
00622   * @retval None
00623   */
00624 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
00625
00626 /** @brief  Check whether the specified SPI interrupt source is enabled or not.
00627   * @param  __HANDLE__: specifies the SPI Handle.
00628   *         This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
00629   * @param  __INTERRUPT__: specifies the SPI interrupt source to check.
00630   *          This parameter can be one of the following values:
00631   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00632   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00633   *            @arg SPI_IT_ERR: Error interrupt enable
00634   * @retval The new state of __IT__ (TRUE or FALSE).
00635   */
00636 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00637
00638 /** @brief  Check whether the specified SPI flag is set or not.
00639   * @param  __HANDLE__: specifies the SPI Handle.
00640   *         This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
00641   * @param  __FLAG__: specifies the flag to check.
00642   *         This parameter can be one of the following values:
00643   *            @arg SPI_FLAG_TXE   : Tx buffer empty flag
00644   *            @arg SPI_FLAG_RXNE  : Rx buffer not empty flag
00645   *            @arg SPI_FLAG_UDR   : Underrun flag
00646   *            @arg SPI_FLAG_OVR   : Overrun flag
00647   *            @arg SPI_FLAG_FRE   : TI mode frame format error flag
00648   *            @arg SPI_FLAG_CRCERR: CRC error flag
00649   *            @arg SPI_FLAG_MODF  : Mode fault flag
00650   *            @arg SPI_FLAG_FRLVL : fifo reception level
00651   *            @arg SPI_FLAG_RXWNE : RxFIFO Word Not Empty
00652   *            @arg SPI_FLAG_TXTF  : Transmission Transfer Filled flag
00653   *            @arg SPI_FLAG_EOT   : fifo transmision complete
00654   * @retval The new state of __FLAG__ (TRUE or FALSE).
00655   */
00656 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00657
00658 /** @brief  Clear the SPI CRCERR pending flag.
00659   * @param  __HANDLE__: specifies the SPI Handle.
00660   * @retval None
00661   */
00662 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC)
00663
00664 /** @brief  Clear the SPI MODF pending flag.
00665   * @param  __HANDLE__: specifies the SPI Handle.
00666   * @retval None
00667   */
00668 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC));
00669
00670 /** @brief  Clear the SPI OVR pending flag.
00671   * @param  __HANDLE__: specifies the SPI Handle.
00672   * @retval None
00673   */
00674 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
00675
00676 /** @brief  Clear the SPI FRE pending flag.
00677   * @param  __HANDLE__: specifies the SPI Handle.
00678   * @retval None
00679   */
00680 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
00681
00682 /** @brief  Clear the SPI UDR pending flag.
00683   * @param  __HANDLE__: specifies the SPI Handle.
00684   * @retval None
00685   */
00686 #define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
00687
00688 /** @brief  Clear the SPI EOT pending flag.
00689   * @param  __HANDLE__: specifies the SPI Handle.
00690   * @retval None
00691   */
00692 #define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC)
00693
00694 /** @brief  Clear the SPI UDR pending flag.
00695   * @param  __HANDLE__: specifies the SPI Handle.
00696   * @retval None
00697   */
00698 #define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC)
00699
00700 /** @brief  Enable the SPI peripheral.
00701   * @param  __HANDLE__: specifies the SPI Handle.
00702   * @retval None
00703   */
00704 #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
00705
00706 /** @brief  Disable the SPI peripheral.
00707   * @param  __HANDLE__: specifies the SPI Handle.
00708   * @retval None
00709   */
00710 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
00711 /**
00712   * @}
00713   */
00714
00715
00716 /* Include SPI HAL Extension module */
00717 #include "stm32h7xx_hal_spi_ex.h"
00718
00719
00720 /* Exported functions --------------------------------------------------------*/
00721 /** @addtogroup SPI_Exported_Functions
00722   * @{
00723   */
00724
00725 /** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
00726   * @{
00727   */
00728 /* Initialization/de-initialization functions  ********************************/
00729 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
00730 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
00731 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
00732 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
00733 /**
00734   * @}
00735   */
00736
00737 /** @addtogroup SPI_Exported_Functions_Group2 IO operation functions
00738   * @{
00739   */
00740 /* I/O operation functions  ***************************************************/
00741 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00742 HAL_StatusTypeDef HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00743 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
00744                                           uint32_t Timeout);
00745 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00746 HAL_StatusTypeDef HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00747 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
00748                                              uint16_t Size);
00749 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00750 HAL_StatusTypeDef HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00751 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
00752                                               uint16_t Size);
00753
00754 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
00755 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
00756 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
00757
00758 /* Transfer Abort functions */
00759 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
00760 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
00761
00762 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
00763 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
00764 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
00765 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
00766 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00767 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00768 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00769 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
00770 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
00771 /**
00772   * @}
00773   */
00774
00775 /** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
00776   * @{
00777   */
00778
00779 /* Peripheral State and Error functions ***************************************/
00780 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
00781 uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
00782 /**
00783   * @}
00784   */
00785
00786 /**
00787   * @}
00788   */
00789
00790 /* Private macros ------------------------------------------------------------*/
00791 /** @defgroup SPI_Private_Macros SPI Private Macros
00792   * @{
00793   */
00794
00795 /** @brief  Set the SPI transmit-only mode.
00796   * @param  __HANDLE__: specifies the SPI Handle.
00797   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00798   * @retval None
00799   */
00800 #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR)
00801
00802 /** @brief  Set the SPI receive-only mode.
00803   * @param  __HANDLE__: specifies the SPI Handle.
00804   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00805   * @retval None
00806   */
00807 #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR)
00808
00809 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
00810                            ((MODE) == SPI_MODE_MASTER))
00811
00812 #define IS_SPI_DIRECTION(MODE)   (((MODE) == SPI_DIRECTION_2LINES)        || \
00813                                   ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
00814                                   ((MODE) == SPI_DIRECTION_1LINE)         || \
00815                                   ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
00816
00817 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
00818
00819 #define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) (    \
00820                                   ((MODE) == SPI_DIRECTION_2LINES)|| \
00821                                   ((MODE) == SPI_DIRECTION_1LINE) || \
00822                                   ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
00823
00824 #define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) (    \
00825                                   ((MODE) == SPI_DIRECTION_2LINES)|| \
00826                                   ((MODE) == SPI_DIRECTION_1LINE) || \
00827                                   ((MODE) == SPI_DIRECTION_2LINES_RXONLY))
00828
00829 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) || \
00830                                    ((DATASIZE) == SPI_DATASIZE_31BIT) || \
00831                                    ((DATASIZE) == SPI_DATASIZE_30BIT) || \
00832                                    ((DATASIZE) == SPI_DATASIZE_29BIT) || \
00833                                    ((DATASIZE) == SPI_DATASIZE_28BIT) || \
00834                                    ((DATASIZE) == SPI_DATASIZE_27BIT) || \
00835                                    ((DATASIZE) == SPI_DATASIZE_26BIT) || \
00836                                    ((DATASIZE) == SPI_DATASIZE_25BIT) || \
00837                                    ((DATASIZE) == SPI_DATASIZE_24BIT) || \
00838                                    ((DATASIZE) == SPI_DATASIZE_23BIT) || \
00839                                    ((DATASIZE) == SPI_DATASIZE_22BIT) || \
00840                                    ((DATASIZE) == SPI_DATASIZE_21BIT) || \
00841                                    ((DATASIZE) == SPI_DATASIZE_20BIT) || \
00842                                    ((DATASIZE) == SPI_DATASIZE_22BIT) || \
00843                                    ((DATASIZE) == SPI_DATASIZE_19BIT) || \
00844                                    ((DATASIZE) == SPI_DATASIZE_18BIT) || \
00845                                    ((DATASIZE) == SPI_DATASIZE_17BIT) || \
00846                                    ((DATASIZE) == SPI_DATASIZE_16BIT) || \
00847                                    ((DATASIZE) == SPI_DATASIZE_15BIT) || \
00848                                    ((DATASIZE) == SPI_DATASIZE_14BIT) || \
00849                                    ((DATASIZE) == SPI_DATASIZE_13BIT) || \
00850                                    ((DATASIZE) == SPI_DATASIZE_12BIT) || \
00851                                    ((DATASIZE) == SPI_DATASIZE_11BIT) || \
00852                                    ((DATASIZE) == SPI_DATASIZE_10BIT) || \
00853                                    ((DATASIZE) == SPI_DATASIZE_9BIT)  || \
00854                                    ((DATASIZE) == SPI_DATASIZE_8BIT)  || \
00855                                    ((DATASIZE) == SPI_DATASIZE_7BIT)  || \
00856                                    ((DATASIZE) == SPI_DATASIZE_6BIT)  || \
00857                                    ((DATASIZE) == SPI_DATASIZE_5BIT)  || \
00858                                    ((DATASIZE) == SPI_DATASIZE_4BIT))
00859
00860 #define IS_SPI_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \
00861                                          ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \
00862                                          ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \
00863                                          ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \
00864                                          ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \
00865                                          ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \
00866                                          ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \
00867                                          ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \
00868                                          ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \
00869                                          ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \
00870                                          ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \
00871                                          ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \
00872                                          ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \
00873                                          ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \
00874                                          ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \
00875                                          ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA))
00876
00877 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
00878                            ((CPOL) == SPI_POLARITY_HIGH))
00879
00880 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
00881                            ((CPHA) == SPI_PHASE_2EDGE))
00882
00883 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT)       || \
00884                          ((NSS) == SPI_NSS_HARD_INPUT) || \
00885                          ((NSS) == SPI_NSS_HARD_OUTPUT))
00886
00887 #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
00888                            ((NSSP) == SPI_NSS_PULSE_DISABLE))
00889
00890 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
00891                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
00892                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
00893                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
00894                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
00895                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
00896                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
00897                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
00898
00899 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
00900                                ((BIT) == SPI_FIRSTBIT_LSB))
00901
00902 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
00903                              ((MODE) == SPI_TIMODE_ENABLE))
00904
00905 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
00906                                              ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
00907
00908 #define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \
00909                                                     ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN))
00910
00911 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE)  ||\
00912                                    ((LENGTH) == SPI_CRC_LENGTH_32BIT)     ||\
00913                                    ((LENGTH) == SPI_CRC_LENGTH_31BIT)     ||\
00914                                    ((LENGTH) == SPI_CRC_LENGTH_30BIT)     ||\
00915                                    ((LENGTH) == SPI_CRC_LENGTH_29BIT)     ||\
00916                                    ((LENGTH) == SPI_CRC_LENGTH_28BIT)     ||\
00917                                    ((LENGTH) == SPI_CRC_LENGTH_27BIT)     ||\
00918                                    ((LENGTH) == SPI_CRC_LENGTH_26BIT)     ||\
00919                                    ((LENGTH) == SPI_CRC_LENGTH_25BIT)     ||\
00920                                    ((LENGTH) == SPI_CRC_LENGTH_24BIT)     ||\
00921                                    ((LENGTH) == SPI_CRC_LENGTH_23BIT)     ||\
00922                                    ((LENGTH) == SPI_CRC_LENGTH_22BIT)     ||\
00923                                    ((LENGTH) == SPI_CRC_LENGTH_21BIT)     ||\
00924                                    ((LENGTH) == SPI_CRC_LENGTH_20BIT)     ||\
00925                                    ((LENGTH) == SPI_CRC_LENGTH_19BIT)     ||\
00926                                    ((LENGTH) == SPI_CRC_LENGTH_18BIT)     ||\
00927                                    ((LENGTH) == SPI_CRC_LENGTH_17BIT)     ||\
00928                                    ((LENGTH) == SPI_CRC_LENGTH_16BIT)     ||\
00929                                    ((LENGTH) == SPI_CRC_LENGTH_15BIT)     ||\
00930                                    ((LENGTH) == SPI_CRC_LENGTH_14BIT)     ||\
00931                                    ((LENGTH) == SPI_CRC_LENGTH_13BIT)     ||\
00932                                    ((LENGTH) == SPI_CRC_LENGTH_12BIT)     ||\
00933                                    ((LENGTH) == SPI_CRC_LENGTH_11BIT)     ||\
00934                                    ((LENGTH) == SPI_CRC_LENGTH_10BIT)     ||\
00935                                    ((LENGTH) == SPI_CRC_LENGTH_9BIT)      ||\
00936                                    ((LENGTH) == SPI_CRC_LENGTH_8BIT)      ||\
00937                                    ((LENGTH) == SPI_CRC_LENGTH_7BIT)      ||\
00938                                    ((LENGTH) == SPI_CRC_LENGTH_6BIT)      ||\
00939                                    ((LENGTH) == SPI_CRC_LENGTH_5BIT)      ||\
00940                                    ((LENGTH) == SPI_CRC_LENGTH_4BIT))
00941
00942 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFFFFFF))
00943
00944 #define IS_SPI_UNDERRUN_DETECTION(MODE) (((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \
00945                                          ((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME)   || \
00946                                          ((MODE) == SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS))
00947
00948 #define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \
00949                                          ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED)    || \
00950                                          ((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED))
00951 /**
00952   * @}
00953   */
00954
00955 /**
00956   * @}
00957   */
00958
00959 /**
00960   * @}
00961   */
00962
00963 #ifdef __cplusplus
00964 }
00965 #endif
00966
00967 #endif /* __STM32H7xx_HAL_SPI_H */
00968
00969 /**
00970   * @}
00971   */
00972 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_spi_ex.c Source File

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stm32h7xx_hal_spi_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_spi_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Extended SPI HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          SPI peripheral extended functionalities :
00010   *           + IO operation functions
00011   *           + Peripheral Control functions
00012   *
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00017   *
00018   * Redistribution and use in source and binary forms, with or without modification,
00019   * are permitted provided that the following conditions are met:
00020   *   1. Redistributions of source code must retain the above copyright notice,
00021   *      this list of conditions and the following disclaimer.
00022   *   2. Redistributions in binary form must reproduce the above copyright notice,
00023   *      this list of conditions and the following disclaimer in the documentation
00024   *      and/or other materials provided with the distribution.
00025   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00026   *      may be used to endorse or promote products derived from this software
00027   *      without specific prior written permission.
00028   *
00029   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00030   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00031   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00032   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00033   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00034   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00035   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00036   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00037   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00038   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00039   *
00040   ******************************************************************************
00041   */
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32h7xx_hal.h"
00045
00046 /** @addtogroup STM32H7xx_HAL_Driver
00047   * @{
00048   */
00049
00050 /** @defgroup SPIEx SPIEx
00051   * @brief SPI Extended HAL module driver
00052   * @{
00053   */
00054 #ifdef HAL_SPI_MODULE_ENABLED
00055
00056 /* Private typedef -----------------------------------------------------------*/
00057 /* Private defines -----------------------------------------------------------*/
00058 /* Private macros ------------------------------------------------------------*/
00059 /* Private variables ---------------------------------------------------------*/
00060 /* Private function prototypes -----------------------------------------------*/
00061 /* Exported functions --------------------------------------------------------*/
00062
00063 /** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
00064   * @{
00065   */
00066
00067 /** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
00068   *  @brief   Data transfers functions
00069   *
00070 @verbatim
00071   ==============================================================================
00072                       ##### IO operation functions #####
00073  ===============================================================================
00074  [..]
00075     This subsection provides a set of extended functions to manage the SPI
00076     data transfers.
00077
00078     (#) SPIEx function:
00079         (++) HAL_SPIEx_FlushRxFifo()
00080         (++) HAL_SPIEx_FlushRxFifo()
00081         (++) HAL_SPIEx_EnableLockConfiguration()
00082         (++) HAL_SPIEx_DisableLockConfiguration()
00083         (++) HAL_SPIEx_ConfigureUnderrun()
00084
00085 @endverbatim
00086   * @{
00087   */
00088
00089 /**
00090   * @brief Flush the RX fifo.
00091   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00092   *               the configuration information for the specified SPI module.
00093   * @retval HAL status
00094   */
00095 HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
00096 {
00097   __IO uint32_t tmpreg;
00098   uint8_t  count = 0;
00099   while ( ((hspi->Instance->SR & SPI_FLAG_FRLVL) !=  SPI_FRLVL_EMPTY) || ((hspi->Instance->SR & SPI_FLAG_RXWNE) ==  SPI_FLAG_RXWNE))
00100   {
00101     count+=4;
00102     tmpreg = hspi->Instance->RXDR;
00103     UNUSED(tmpreg); /* To avoid GCC warning */
00104
00105     if (IS_SPI_HIGHEND_INSTANCE(hspi->Instance))
00106     {
00107       if(count > SPI_HIGHEND_FIFO_SIZE)
00108       {
00109         return HAL_TIMEOUT;
00110       }
00111     }
00112     else
00113     {
00114       if(count > SPI_LOWEND_FIFO_SIZE)
00115       {
00116         return HAL_TIMEOUT;
00117       }
00118     }
00119   }
00120   return HAL_OK;
00121 }
00122
00123
00124 /**
00125   * @brief  Enable the Lock for the AF configuration of associated IOs
00126   *         and write protect the Content of Configuartion register 2
00127   *         when SPI is enabled
00128   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00129   *               the configuration information for SPI module.
00130   * @retval None
00131   */
00132 HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi)
00133 {
00134   HAL_StatusTypeDef errorcode = HAL_OK;
00135
00136   /* Process Locked */
00137   __HAL_LOCK(hspi);
00138
00139   if (hspi->State != HAL_SPI_STATE_READY)
00140   {
00141     errorcode = HAL_BUSY;
00142     hspi->State = HAL_SPI_STATE_READY;
00143     /* Process Unlocked */
00144     __HAL_UNLOCK(hspi);
00145     return errorcode;
00146   }
00147
00148   /* Check if the SPI is disabled to edit IOLOCK bit */
00149   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00150   {
00151     SET_BIT(hspi->Instance->CR1 , SPI_CR1_IOLOCK);
00152   }
00153   else
00154   {
00155     /* Disable SPI peripheral */
00156     __HAL_SPI_DISABLE(hspi);
00157
00158     SET_BIT(hspi->Instance->CR1 , SPI_CR1_IOLOCK);
00159
00160     /* Enable SPI peripheral */
00161     __HAL_SPI_ENABLE(hspi);
00162   }
00163
00164   hspi->State = HAL_SPI_STATE_READY;
00165   /* Process Unlocked */
00166   __HAL_UNLOCK(hspi);
00167   return errorcode;
00168 }
00169
00170 /**
00171   * @brief  Disable the Lock for the AF configuration of associated IOs
00172   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00173   *               the configuration information for SPI module.
00174   * @retval None
00175   */
00176 HAL_StatusTypeDef HAL_SPIEx_DisableLockConfiguration(SPI_HandleTypeDef *hspi)
00177 {
00178   HAL_StatusTypeDef errorcode = HAL_OK;
00179
00180   /* Process Locked */
00181   __HAL_LOCK(hspi);
00182
00183   if (hspi->State != HAL_SPI_STATE_READY)
00184   {
00185     errorcode = HAL_BUSY;
00186     hspi->State = HAL_SPI_STATE_READY;
00187     /* Process Unlocked */
00188     __HAL_UNLOCK(hspi);
00189     return errorcode;
00190   }
00191
00192   /* Check if the SPI is disabled to edit IOLOCK bit */
00193   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00194   {
00195     CLEAR_BIT(hspi->Instance->CR1 , SPI_CR1_IOLOCK);
00196   }
00197   else
00198   {
00199     /* Disable SPI peripheral */
00200     __HAL_SPI_DISABLE(hspi);
00201
00202     CLEAR_BIT(hspi->Instance->CR1 , SPI_CR1_IOLOCK);
00203
00204     /* Enable SPI peripheral */
00205     __HAL_SPI_ENABLE(hspi);
00206   }
00207
00208   hspi->Instance->CR1 &= ~(SPI_CR1_IOLOCK);
00209
00210   hspi->State = HAL_SPI_STATE_READY;
00211   /* Process Unlocked */
00212   __HAL_UNLOCK(hspi);
00213   return errorcode;
00214 }
00215
00216 /**
00217   * @brief  Configure the UNDERRUN condition and behavior of slave transmitter.
00218   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00219   *               the configuration information for SPI module.
00220   * @param  UnderrunDetection : Detection of underrun condition at slave transmitter
00221   *                             This parameter can be a value of @ref SPI_Underrun_Detection.
00222   * @param  UnderrunBehaviour : Behavior of slave transmitter at underrun condition
00223   *                             This parameter can be a value of @ref SPI_Underrun_Behaviour.
00224   * @retval None
00225   */
00226 HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour)
00227 {
00228   HAL_StatusTypeDef errorcode = HAL_OK;
00229
00230   /* Process Locked */
00231   __HAL_LOCK(hspi);
00232
00233   /* Check State and Insure that Underrun configuration is managed only by Salve */
00234   if ((hspi->State != HAL_SPI_STATE_READY) || (hspi->Init.Mode != SPI_MODE_SLAVE))
00235   {
00236     errorcode = HAL_BUSY;
00237     hspi->State = HAL_SPI_STATE_READY;
00238     /* Process Unlocked */
00239     __HAL_UNLOCK(hspi);
00240     return errorcode;
00241   }
00242
00243   /* Check the parameters */
00244   assert_param(IS_SPI_UNDERRUN_DETECTION(UnderrunDetection));
00245   assert_param(IS_SPI_UNDERRUN_BEHAVIOUR(UnderrunBehaviour));
00246
00247   /* Check if the SPI is disabled to edit CFG1 register */
00248   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00249   {
00250     /* Configure Underrun fields */
00251     MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, UnderrunDetection);
00252     MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
00253   }
00254   else
00255   {
00256     /* Disable SPI peripheral */
00257     __HAL_SPI_DISABLE(hspi);
00258
00259     /* Configure Underrun fields */
00260     MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, UnderrunDetection);
00261     MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
00262
00263     /* Enable SPI peripheral */
00264     __HAL_SPI_ENABLE(hspi);
00265   }
00266
00267
00268   hspi->State = HAL_SPI_STATE_READY;
00269   /* Process Unlocked */
00270   __HAL_UNLOCK(hspi);
00271   return errorcode;
00272 }
00273
00274 /**
00275   * @}
00276   */
00277
00278 /**
00279   * @}
00280   */
00281
00282 #endif /* HAL_SPI_MODULE_ENABLED */
00283
00284 /**
00285   * @}
00286   */
00287
00288 /**
00289   * @}
00290   */
00291
00292 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_spi_ex.h Source File

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stm32h7xx_hal_spi_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_spi_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of SPI HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_SPI_EX_H
00040 #define __STM32H7xx_HAL_SPI_EX_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SPIEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059 /* Exported macros -----------------------------------------------------------*/
00060 /* Exported functions --------------------------------------------------------*/
00061 /** @addtogroup SPIEx_Exported_Functions
00062   * @{
00063   */
00064
00065 /* Initialization and de-initialization functions  ****************************/
00066 /* IO operation functions *****************************************************/
00067 /** @addtogroup SPIEx_Exported_Functions_Group1
00068   * @{
00069   */
00070 HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
00071 HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi);
00072 HAL_StatusTypeDef HAL_SPIEx_DisableLockConfiguration(SPI_HandleTypeDef *hspi);
00073 HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour);
00074 /**
00075   * @}
00076   */
00077
00078 /**
00079   * @}
00080   */
00081
00082 /**
00083   * @}
00084   */
00085
00086 /**
00087   * @}
00088   */
00089
00090 #ifdef __cplusplus
00091 }
00092 #endif
00093
00094 #endif /* __STM32H7xx_HAL_SPI_EX_H */
00095
00096 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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STM32H753xx HAL User Manual: stm32h7xx_hal_sram.c Source File

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stm32h7xx_hal_sram.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sram.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   SRAM HAL module driver.
00008   *          This file provides a generic firmware to drive SRAM memories
00009   *          mounted as external device.
00010   *
00011   @verbatim
00012   ==============================================================================
00013                           ##### How to use this driver #####
00014   ==============================================================================
00015   [..]
00016     This driver is a generic layered driver which contains a set of APIs used to
00017     control SRAM memories. It uses the FMC layer functions to interface
00018     with SRAM devices.
00019     The following sequence should be followed to configure the FMC to interface
00020     with SRAM/PSRAM memories:
00021
00022    (#) Declare a SRAM_HandleTypeDef handle structure, for example:
00023           SRAM_HandleTypeDef  hsram; and:
00024
00025        (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
00026             values of the structure member.
00027
00028        (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
00029             base register instance for NOR or SRAM device
00030
00031        (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
00032             base register instance for NOR or SRAM extended mode
00033
00034    (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
00035        mode timings; for example:
00036           FMC_NORSRAM_TimingTypeDef  Timing and FMC_NORSRAM_TimingTypeDef  ExTiming;
00037       and fill its fields with the allowed values of the structure member.
00038
00039    (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
00040        performs the following sequence:
00041
00042        (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
00043        (##) Control register configuration using the FMC NORSRAM interface function
00044             FMC_NORSRAM_Init()
00045        (##) Timing register configuration using the FMC NORSRAM interface function
00046             FMC_NORSRAM_Timing_Init()
00047        (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
00048             FMC_NORSRAM_Extended_Timing_Init()
00049        (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
00050
00051    (#) At this stage you can perform read/write accesses from/to the memory connected
00052        to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
00053        following APIs:
00054        (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
00055        (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
00056
00057    (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
00058        HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
00059
00060    (#) You can continuously monitor the SRAM device HAL state by calling the function
00061        HAL_SRAM_GetState()
00062
00063   @endverbatim
00064   ******************************************************************************
00065   * @attention
00066   *
00067   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00068   *
00069   * Redistribution and use in source and binary forms, with or without modification,
00070   * are permitted provided that the following conditions are met:
00071   *   1. Redistributions of source code must retain the above copyright notice,
00072   *      this list of conditions and the following disclaimer.
00073   *   2. Redistributions in binary form must reproduce the above copyright notice,
00074   *      this list of conditions and the following disclaimer in the documentation
00075   *      and/or other materials provided with the distribution.
00076   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00077   *      may be used to endorse or promote products derived from this software
00078   *      without specific prior written permission.
00079   *
00080   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00081   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00082   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00083   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00084   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00085   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00086   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00087   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00088   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00089   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00090   *
00091   ******************************************************************************
00092   */
00093
00094 /* Includes ------------------------------------------------------------------*/
00095 #include "stm32h7xx_hal.h"
00096
00097 /** @addtogroup STM32H7xx_HAL_Driver
00098   * @{
00099   */
00100
00101 /** @defgroup SRAM SRAM
00102   * @brief SRAM driver modules
00103   * @{
00104   */
00105 #ifdef HAL_SRAM_MODULE_ENABLED
00106 /* Private typedef -----------------------------------------------------------*/
00107 /* Private define ------------------------------------------------------------*/
00108 /* Private macro -------------------------------------------------------------*/
00109 /* Private variables ---------------------------------------------------------*/
00110 /* Private function prototypes -----------------------------------------------*/
00111 /* Exported functions --------------------------------------------------------*/
00112
00113 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
00114   * @{
00115   */
00116
00117 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
00118   * @brief    Initialization and Configuration functions.
00119   *
00120   @verbatim
00121   ==============================================================================
00122            ##### SRAM Initialization and de_initialization functions #####
00123   ==============================================================================
00124     [..]  This section provides functions allowing to initialize/de-initialize
00125           the SRAM memory
00126
00127 @endverbatim
00128   * @{
00129   */
00130
00131 /**
00132   * @brief  Performs the SRAM device initialization sequence
00133   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00134   *                the configuration information for SRAM module.
00135   * @param  Timing: Pointer to SRAM control timing structure
00136   * @param  ExtTiming: Pointer to SRAM extended mode timing structure
00137   * @retval HAL status
00138   */
00139 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
00140 {
00141   /* Check the SRAM handle parameter */
00142   if(hsram == NULL)
00143   {
00144      return HAL_ERROR;
00145   }
00146
00147   if(hsram->State == HAL_SRAM_STATE_RESET)
00148   {
00149     /* Allocate lock resource and initialize it */
00150     hsram->Lock = HAL_UNLOCKED;
00151     /* Initialize the low level hardware (MSP) */
00152     HAL_SRAM_MspInit(hsram);
00153   }
00154
00155   /* Initialize SRAM control Interface */
00156   FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
00157
00158   /* Initialize SRAM timing Interface */
00159   FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
00160
00161   /* Initialize SRAM extended mode timing Interface */
00162   FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,  hsram->Init.ExtendedMode);
00163
00164   /* Enable the NORSRAM device */
00165   __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
00166
00167   /* Enable FMC IP */
00168   __FMC_ENABLE();
00169
00170   return HAL_OK;
00171 }
00172
00173 /**
00174   * @brief  Performs the SRAM device De-initialization sequence.
00175   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00176   *                the configuration information for SRAM module.
00177   * @retval HAL status
00178   */
00179 HAL_StatusTypeDef  HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
00180 {
00181   /* De-Initialize the low level hardware (MSP) */
00182   HAL_SRAM_MspDeInit(hsram);
00183
00184   /* Configure the SRAM registers with their reset values */
00185   FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
00186
00187   hsram->State = HAL_SRAM_STATE_RESET;
00188
00189   /* Release Lock */
00190   __HAL_UNLOCK(hsram);
00191
00192   return HAL_OK;
00193 }
00194
00195 /**
00196   * @brief  SRAM MSP Init.
00197   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00198   *                the configuration information for SRAM module.
00199   * @retval None
00200   */
00201 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
00202 {
00203   /* Prevent unused argument(s) compilation warning */
00204   UNUSED(hsram);
00205
00206   /* NOTE : This function Should not be modified, when the callback is needed,
00207             the HAL_SRAM_MspInit could be implemented in the user file
00208    */
00209 }
00210
00211 /**
00212   * @brief  SRAM MSP DeInit.
00213   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00214   *                the configuration information for SRAM module.
00215   * @retval None
00216   */
00217 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
00218 {
00219   /* Prevent unused argument(s) compilation warning */
00220   UNUSED(hsram);
00221
00222   /* NOTE : This function Should not be modified, when the callback is needed,
00223             the HAL_SRAM_MspDeInit could be implemented in the user file
00224    */
00225 }
00226
00227 /**
00228   * @brief  DMA transfer complete callback.
00229   * @param  hmdma: pointer to a SRAM_HandleTypeDef structure that contains
00230   *                the configuration information for SRAM module.
00231   * @retval None
00232   */
00233 __weak void HAL_SRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma)
00234 {
00235   /* Prevent unused argument(s) compilation warning */
00236   UNUSED(hmdma);
00237
00238   /* NOTE : This function Should not be modified, when the callback is needed,
00239             the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
00240    */
00241 }
00242
00243 /**
00244   * @brief  DMA transfer complete error callback.
00245   * @param  hmdma: pointer to a SRAM_HandleTypeDef structure that contains
00246   *                the configuration information for SRAM module.
00247   * @retval None
00248   */
00249 __weak void HAL_SRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma)
00250 {
00251   /* Prevent unused argument(s) compilation warning */
00252   UNUSED(hmdma);
00253
00254   /* NOTE : This function Should not be modified, when the callback is needed,
00255             the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
00256    */
00257 }
00258
00259 /**
00260   * @}
00261   */
00262
00263 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
00264   * @brief    Input Output and memory control functions
00265   *
00266   @verbatim
00267   ==============================================================================
00268                   ##### SRAM Input and Output functions #####
00269   ==============================================================================
00270   [..]
00271     This section provides functions allowing to use and control the SRAM memory
00272
00273 @endverbatim
00274   * @{
00275   */
00276
00277 /**
00278   * @brief  Reads 8-bit buffer from SRAM memory.
00279   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00280   *                the configuration information for SRAM module.
00281   * @param  pAddress: Pointer to read start address
00282   * @param  pDstBuffer: Pointer to destination buffer
00283   * @param  BufferSize: Size of the buffer to read from memory
00284   * @retval HAL status
00285   */
00286 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
00287 {
00288   __IO uint8_t * psramaddress = (uint8_t *)pAddress;
00289
00290   /* Process Locked */
00291   __HAL_LOCK(hsram);
00292
00293   /* Update the SRAM controller state */
00294   hsram->State = HAL_SRAM_STATE_BUSY;
00295
00296   /* Read data from memory */
00297   for(; BufferSize != 0; BufferSize--)
00298   {
00299     *pDstBuffer = *(__IO uint8_t *)psramaddress;
00300     pDstBuffer++;
00301     psramaddress++;
00302   }
00303
00304   /* Update the SRAM controller state */
00305   hsram->State = HAL_SRAM_STATE_READY;
00306
00307   /* Process unlocked */
00308   __HAL_UNLOCK(hsram);
00309
00310   return HAL_OK;
00311 }
00312
00313 /**
00314   * @brief  Writes 8-bit buffer to SRAM memory.
00315   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00316   *                the configuration information for SRAM module.
00317   * @param  pAddress: Pointer to write start address
00318   * @param  pSrcBuffer: Pointer to source buffer to write
00319   * @param  BufferSize: Size of the buffer to write to memory
00320   * @retval HAL status
00321   */
00322 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
00323 {
00324   __IO uint8_t * psramaddress = (uint8_t *)pAddress;
00325
00326   /* Check the SRAM controller state */
00327   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00328   {
00329     return  HAL_ERROR;
00330   }
00331
00332   /* Process Locked */
00333   __HAL_LOCK(hsram);
00334
00335   /* Update the SRAM controller state */
00336   hsram->State = HAL_SRAM_STATE_BUSY;
00337
00338   /* Write data to memory */
00339   for(; BufferSize != 0; BufferSize--)
00340   {
00341     *(__IO uint8_t *)psramaddress = *pSrcBuffer;
00342     pSrcBuffer++;
00343     psramaddress++;
00344   }
00345
00346   /* Update the SRAM controller state */
00347   hsram->State = HAL_SRAM_STATE_READY;
00348
00349   /* Process unlocked */
00350   __HAL_UNLOCK(hsram);
00351
00352   return HAL_OK;
00353 }
00354
00355 /**
00356   * @brief  Reads 16-bit buffer from SRAM memory.
00357   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00358   *                the configuration information for SRAM module.
00359   * @param  pAddress: Pointer to read start address
00360   * @param  pDstBuffer: Pointer to destination buffer
00361   * @param  BufferSize: Size of the buffer to read from memory
00362   * @retval HAL status
00363   */
00364 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
00365 {
00366   __IO uint16_t * psramaddress = (uint16_t *)pAddress;
00367
00368   /* Process Locked */
00369   __HAL_LOCK(hsram);
00370
00371   /* Update the SRAM controller state */
00372   hsram->State = HAL_SRAM_STATE_BUSY;
00373
00374   /* Read data from memory */
00375   for(; BufferSize != 0; BufferSize--)
00376   {
00377     *pDstBuffer = *(__IO uint16_t *)psramaddress;
00378     pDstBuffer++;
00379     psramaddress++;
00380   }
00381
00382   /* Update the SRAM controller state */
00383   hsram->State = HAL_SRAM_STATE_READY;
00384
00385   /* Process unlocked */
00386   __HAL_UNLOCK(hsram);
00387
00388   return HAL_OK;
00389 }
00390
00391 /**
00392   * @brief  Writes 16-bit buffer to SRAM memory.
00393   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00394   *                the configuration information for SRAM module.
00395   * @param  pAddress: Pointer to write start address
00396   * @param  pSrcBuffer: Pointer to source buffer to write
00397   * @param  BufferSize: Size of the buffer to write to memory
00398   * @retval HAL status
00399   */
00400 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
00401 {
00402   __IO uint16_t * psramaddress = (uint16_t *)pAddress;
00403
00404   /* Check the SRAM controller state */
00405   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00406   {
00407     return  HAL_ERROR;
00408   }
00409
00410   /* Process Locked */
00411   __HAL_LOCK(hsram);
00412
00413   /* Update the SRAM controller state */
00414   hsram->State = HAL_SRAM_STATE_BUSY;
00415
00416   /* Write data to memory */
00417   for(; BufferSize != 0; BufferSize--)
00418   {
00419     *(__IO uint16_t *)psramaddress = *pSrcBuffer;
00420     pSrcBuffer++;
00421     psramaddress++;
00422   }
00423
00424   /* Update the SRAM controller state */
00425   hsram->State = HAL_SRAM_STATE_READY;
00426
00427   /* Process unlocked */
00428   __HAL_UNLOCK(hsram);
00429
00430   return HAL_OK;
00431 }
00432
00433 /**
00434   * @brief  Reads 32-bit buffer from SRAM memory.
00435   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00436   *                the configuration information for SRAM module.
00437   * @param  pAddress: Pointer to read start address
00438   * @param  pDstBuffer: Pointer to destination buffer
00439   * @param  BufferSize: Size of the buffer to read from memory
00440   * @retval HAL status
00441   */
00442 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00443 {
00444   /* Process Locked */
00445   __HAL_LOCK(hsram);
00446
00447   /* Update the SRAM controller state */
00448   hsram->State = HAL_SRAM_STATE_BUSY;
00449
00450   /* Read data from memory */
00451   for(; BufferSize != 0; BufferSize--)
00452   {
00453     *pDstBuffer = *(__IO uint32_t *)pAddress;
00454     pDstBuffer++;
00455     pAddress++;
00456   }
00457
00458   /* Update the SRAM controller state */
00459   hsram->State = HAL_SRAM_STATE_READY;
00460
00461   /* Process unlocked */
00462   __HAL_UNLOCK(hsram);
00463
00464   return HAL_OK;
00465 }
00466
00467 /**
00468   * @brief  Writes 32-bit buffer to SRAM memory.
00469   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00470   *                the configuration information for SRAM module.
00471   * @param  pAddress: Pointer to write start address
00472   * @param  pSrcBuffer: Pointer to source buffer to write
00473   * @param  BufferSize: Size of the buffer to write to memory
00474   * @retval HAL status
00475   */
00476 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00477 {
00478   /* Check the SRAM controller state */
00479   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00480   {
00481     return  HAL_ERROR;
00482   }
00483
00484   /* Process Locked */
00485   __HAL_LOCK(hsram);
00486
00487   /* Update the SRAM controller state */
00488   hsram->State = HAL_SRAM_STATE_BUSY;
00489
00490   /* Write data to memory */
00491   for(; BufferSize != 0; BufferSize--)
00492   {
00493     *(__IO uint32_t *)pAddress = *pSrcBuffer;
00494     pSrcBuffer++;
00495     pAddress++;
00496   }
00497
00498   /* Update the SRAM controller state */
00499   hsram->State = HAL_SRAM_STATE_READY;
00500
00501   /* Process unlocked */
00502   __HAL_UNLOCK(hsram);
00503
00504   return HAL_OK;
00505 }
00506
00507 /**
00508   * @brief  Reads a Words data from the SRAM memory using DMA transfer.
00509   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00510   *                the configuration information for SRAM module.
00511   * @param  pAddress: Pointer to read start address
00512   * @param  pDstBuffer: Pointer to destination buffer
00513   * @param  BufferSize: Size of the buffer to read from memory
00514   * @retval HAL status
00515   */
00516 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00517 {
00518   /* Process Locked */
00519   __HAL_LOCK(hsram);
00520
00521   /* Update the SRAM controller state */
00522   hsram->State = HAL_SRAM_STATE_BUSY;
00523
00524   /* Configure DMA user callbacks */
00525   hsram->hmdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
00526   hsram->hmdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
00527
00528   /* Enable the DMA Stream */
00529   HAL_MDMA_Start_IT(hsram->hmdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)(BufferSize * 4), 1);
00530
00531   /* Update the SRAM controller state */
00532   hsram->State = HAL_SRAM_STATE_READY;
00533
00534   /* Process unlocked */
00535   __HAL_UNLOCK(hsram);
00536
00537   return HAL_OK;
00538 }
00539
00540 /**
00541   * @brief  Writes a Words data buffer to SRAM memory using DMA transfer.
00542   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00543   *                the configuration information for SRAM module.
00544   * @param  pAddress: Pointer to write start address
00545   * @param  pSrcBuffer: Pointer to source buffer to write
00546   * @param  BufferSize: Size of the buffer to write to memory
00547   * @retval HAL status
00548   */
00549 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00550 {
00551   /* Check the SRAM controller state */
00552   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00553   {
00554     return  HAL_ERROR;
00555   }
00556
00557   /* Process Locked */
00558   __HAL_LOCK(hsram);
00559
00560   /* Update the SRAM controller state */
00561   hsram->State = HAL_SRAM_STATE_BUSY;
00562
00563   /* Configure DMA user callbacks */
00564   hsram->hmdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
00565   hsram->hmdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
00566
00567   /* Enable the DMA Stream */
00568   HAL_MDMA_Start_IT(hsram->hmdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)(BufferSize * 4), 1);
00569
00570   /* Update the SRAM controller state */
00571   hsram->State = HAL_SRAM_STATE_READY;
00572
00573   /* Process unlocked */
00574   __HAL_UNLOCK(hsram);
00575
00576   return HAL_OK;
00577 }
00578
00579 /**
00580   * @}
00581   */
00582
00583 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
00584  *  @brief   Control functions
00585  *
00586 @verbatim
00587   ==============================================================================
00588                         ##### SRAM Control functions #####
00589   ==============================================================================
00590   [..]
00591     This subsection provides a set of functions allowing to control dynamically
00592     the SRAM interface.
00593
00594 @endverbatim
00595   * @{
00596   */
00597
00598 /**
00599   * @brief  Enables dynamically SRAM write operation.
00600   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00601   *                the configuration information for SRAM module.
00602   * @retval HAL status
00603   */
00604 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
00605 {
00606   /* Process Locked */
00607   __HAL_LOCK(hsram);
00608
00609   /* Enable write operation */
00610   FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
00611
00612   /* Update the SRAM controller state */
00613   hsram->State = HAL_SRAM_STATE_READY;
00614
00615   /* Process unlocked */
00616   __HAL_UNLOCK(hsram);
00617
00618   return HAL_OK;
00619 }
00620
00621 /**
00622   * @brief  Disables dynamically SRAM write operation.
00623   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00624   *                the configuration information for SRAM module.
00625   * @retval HAL status
00626   */
00627 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
00628 {
00629   /* Process Locked */
00630   __HAL_LOCK(hsram);
00631
00632   /* Update the SRAM controller state */
00633   hsram->State = HAL_SRAM_STATE_BUSY;
00634
00635   /* Disable write operation */
00636   FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
00637
00638   /* Update the SRAM controller state */
00639   hsram->State = HAL_SRAM_STATE_PROTECTED;
00640
00641   /* Process unlocked */
00642   __HAL_UNLOCK(hsram);
00643
00644   return HAL_OK;
00645 }
00646
00647 /**
00648   * @}
00649   */
00650
00651 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
00652  *  @brief   Peripheral State functions
00653  *
00654 @verbatim
00655   ==============================================================================
00656                       ##### SRAM State functions #####
00657   ==============================================================================
00658   [..]
00659     This subsection permits to get in run-time the status of the SRAM controller
00660     and the data flow.
00661
00662 @endverbatim
00663   * @{
00664   */
00665
00666 /**
00667   * @brief  Returns the SRAM controller state
00668   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00669   *                the configuration information for SRAM module.
00670   * @retval HAL state
00671   */
00672 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
00673 {
00674   return hsram->State;
00675 }
00676
00677 /**
00678   * @}
00679   */
00680
00681 /**
00682   * @}
00683   */
00684 #endif /* HAL_SRAM_MODULE_ENABLED */
00685 /**
00686   * @}
00687   */
00688
00689 /**
00690   * @}
00691   */
00692
00693 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_sram.h Source File

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stm32h7xx_hal_sram.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_sram.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of SRAM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_SRAM_H
00040 #define __STM32H7xx_HAL_SRAM_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_ll_fmc.h"
00048 #include "stm32h7xx_hal_mdma.h"
00049
00050 /** @addtogroup STM32H7xx_HAL_Driver
00051   * @{
00052   */
00053 /** @addtogroup SRAM
00054   * @{
00055   */
00056
00057 /* Exported typedef ----------------------------------------------------------*/
00058
00059 /** @defgroup SRAM_Exported_Types SRAM Exported Types
00060   * @{
00061   */
00062 /**
00063   * @brief  HAL SRAM State structures definition
00064   */
00065 typedef enum
00066 {
00067   HAL_SRAM_STATE_RESET     = 0x00U,  /*!< SRAM not yet initialized or disabled           */
00068   HAL_SRAM_STATE_READY     = 0x01U,  /*!< SRAM initialized and ready for use             */
00069   HAL_SRAM_STATE_BUSY      = 0x02U,  /*!< SRAM internal process is ongoing               */
00070   HAL_SRAM_STATE_ERROR     = 0x03U,  /*!< SRAM error state                               */
00071   HAL_SRAM_STATE_PROTECTED = 0x04U   /*!< SRAM peripheral NORSRAM device write protected */
00072
00073 }HAL_SRAM_StateTypeDef;
00074
00075 /**
00076   * @brief  SRAM handle Structure definition
00077   */
00078 typedef struct
00079 {
00080   FMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */
00081
00082   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
00083
00084   FMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
00085
00086   HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */
00087
00088   __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
00089
00090   MDMA_HandleTypeDef             *hmdma;      /*!< Pointer DMA handler                          */
00091
00092 }SRAM_HandleTypeDef;
00093
00094 /**
00095   * @}
00096   */
00097
00098 /* Exported constants --------------------------------------------------------*/
00099 /* Exported macro ------------------------------------------------------------*/
00100
00101 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
00102  * @{
00103  */
00104
00105 /** @brief Reset SRAM handle state
00106   * @param  __HANDLE__: SRAM handle
00107   * @retval None
00108   */
00109 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
00110
00111 /**
00112   * @}
00113   */
00114
00115 /* Exported functions --------------------------------------------------------*/
00116 /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
00117   * @{
00118   */
00119
00120 /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
00121  * @{
00122  */
00123
00124 /* Initialization/de-initialization functions  ********************************/
00125 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
00126 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
00127 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
00128 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
00129
00130 /**
00131   * @}
00132   */
00133
00134 /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
00135  * @{
00136  */
00137
00138 /* I/O operation functions  ***************************************************/
00139 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
00140 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
00141 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
00142 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
00143 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00144 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00145 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00146 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00147
00148 void HAL_SRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma);
00149 void HAL_SRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma);
00150
00151 /**
00152   * @}
00153   */
00154
00155 /** @addtogroup SRAM_Exported_Functions_Group3 Control functions
00156  * @{
00157  */
00158
00159 /* SRAM Control functions  ****************************************************/
00160 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
00161 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
00162
00163 /**
00164   * @}
00165   */
00166
00167 /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
00168  * @{
00169  */
00170
00171 /* SRAM  State functions ******************************************************/
00172 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
00173
00174 /**
00175   * @}
00176   */
00177
00178 /**
00179   * @}
00180   */
00181
00182 /**
00183   * @}
00184   */
00185
00186 /**
00187   * @}
00188   */
00189
00190 #ifdef __cplusplus
00191 }
00192 #endif
00193
00194 #endif /* __STM32H7xx_HAL_SRAM_H */
00195
00196 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_swpmi.c Source File

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stm32h7xx_hal_swpmi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_swpmi.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   SWPMI HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Single Wire Protocol Master Interface (SWPMI).
00010   *           + Initialization and Configuration
00011   *           + Data transfers functions
00012   *           + DMA transfers management
00013   *           + Interrupts and flags management
00014   @verbatim
00015  ===============================================================================
00016                         ##### How to use this driver #####
00017  ===============================================================================
00018   [..]
00019      The SWPMI HAL driver can be used as follows:
00020
00021     (#) Declare a SWPMI_HandleTypeDef handle structure (eg. SWPMI_HandleTypeDef hswpmi).
00022
00023     (#) Initialize the SWPMI low level resources by implementing the HAL_SWPMI_MspInit() API:
00024         (##) Enable the SWPMIx interface clock with __HAL_RCC_SWPMIx_CLK_ENABLE().
00025         (##) SWPMI IO configuration:
00026             (+++) Enable the clock for the SWPMI GPIO.
00027             (+++) Configure these SWPMI pins as alternate function pull-up.
00028         (##) NVIC configuration if you need to use interrupt process (HAL_SWPMI_Transmit_IT()
00029              and HAL_SWPMI_Receive_IT() APIs):
00030             (+++) Configure the SWPMIx interrupt priority with HAL_NVIC_SetPriority().
00031             (+++) Enable the NVIC SWPMI IRQ handle with HAL_NVIC_EnableIRQ().
00032
00033         (##) DMA Configuration if you need to use DMA process (HAL_SWPMI_Transmit_DMA()
00034              and HAL_SWPMI_Receive_DMA() APIs):
00035             (+++) Declare a DMA handle structure for the Tx/Rx channels.
00036             (+++) Enable the DMAx interface clock.
00037             (+++) Configure the declared DMA handle structure with the required
00038                   Tx/Rx parameters.
00039             (+++) Configure the DMA Tx/Rx channels and requests.
00040             (+++) Associate the initialized DMA handle to the SWPMI DMA Tx/Rx handle.
00041             (+++) Configure the priority and enable the NVIC for the transfer complete
00042                   interrupt on the DMA Tx/Rx channels.
00043
00044     (#) Program the Bite Rate, Tx Buffering mode, Rx Buffering mode in the Init structure.
00045
00046     (#) Enable the SWPMI peripheral by calling the HAL_SWPMI_Init() function.
00047
00048   @endverbatim
00049   ******************************************************************************
00050   * @attention
00051   *
00052   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00053   *
00054   * Redistribution and use in source and binary forms, with or without modification,
00055   * are permitted provided that the following conditions are met:
00056   *   1. Redistributions of source code must retain the above copyright notice,
00057   *      this list of conditions and the following disclaimer.
00058   *   2. Redistributions in binary form must reproduce the above copyright notice,
00059   *      this list of conditions and the following disclaimer in the documentation
00060   *      and/or other materials provided with the distribution.
00061   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00062   *      may be used to endorse or promote products derived from this software
00063   *      without specific prior written permission.
00064   *
00065   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00066   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00067   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00068   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00069   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00070   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00071   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00072   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00073   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00074   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00075   *
00076   ******************************************************************************
00077   */
00078
00079 /* Includes ------------------------------------------------------------------*/
00080 #include "stm32h7xx_hal.h"
00081
00082 /** @addtogroup STM32H7xx_HAL_Driver
00083   * @{
00084   */
00085
00086 /** @defgroup SWPMI SWPMI
00087   * @brief HAL SWPMI module driver
00088   * @{
00089   */
00090 #ifdef HAL_SWPMI_MODULE_ENABLED
00091
00092 /* Private typedef -----------------------------------------------------------*/
00093 /* Private define ------------------------------------------------------------*/
00094 /* Private constants ---------------------------------------------------------*/
00095 /** @addtogroup SWPMI_Private_Constants SWPMI Private Constants
00096   * @{
00097   */
00098 #define SWPMI_TIMEOUT_VALUE       ((uint32_t) 22000U)
00099
00100 /**
00101   * @}
00102   */
00103
00104 /* Private macros ------------------------------------------------------------*/
00105 /* Private variables ---------------------------------------------------------*/
00106 /* Private function prototypes -----------------------------------------------*/
00107 static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00108 static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00109 static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00110 static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00111 static void SWPMI_DMAError(DMA_HandleTypeDef *hdma);
00112 static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00113 static HAL_StatusTypeDef SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi);
00114 static HAL_StatusTypeDef SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi);
00115 static HAL_StatusTypeDef SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi);
00116 static HAL_StatusTypeDef SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi);
00117 static HAL_StatusTypeDef SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi);
00118 static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout);
00119
00120 /* Exported functions --------------------------------------------------------*/
00121
00122 /** @defgroup SWPMI_Exported_Functions SWPMI Exported Functions
00123   * @{
00124   */
00125
00126 /** @defgroup SWPMI_Exported_Group1 Initialization/de-initialization methods
00127   *  @brief    Initialization and Configuration functions
00128   *
00129 @verbatim
00130  ===============================================================================
00131             ##### Initialization and Configuration functions #####
00132  ===============================================================================
00133     [..]  This section provides functions allowing to:
00134       (+) Initialize and configure the SWPMI peripheral.
00135       (+) De-initialize the SWPMI peripheral.
00136
00137 @endverbatim
00138   * @{
00139   */
00140
00141 /**
00142   * @brief Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.
00143   * @param hswpmi: SWPMI handle
00144   * @retval HAL status
00145   */
00146 HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi)
00147 {
00148   uint32_t tickstart = HAL_GetTick();
00149   HAL_StatusTypeDef status = HAL_OK;
00150
00151   /* Check the SWPMI handle allocation */
00152   if(hswpmi == NULL)
00153   {
00154     status = HAL_ERROR;
00155   }
00156   else
00157   {
00158     /* Check the parameters */
00159     assert_param(IS_SWPMI_VOLTAGE_CLASS(hswpmi->Init.VoltageClass));
00160     assert_param(IS_SWPMI_BITRATE_VALUE(hswpmi->Init.BitRate));
00161     assert_param(IS_SWPMI_TX_BUFFERING_MODE(hswpmi->Init.TxBufferingMode));
00162     assert_param(IS_SWPMI_RX_BUFFERING_MODE(hswpmi->Init.RxBufferingMode));
00163
00164     if(hswpmi->State == HAL_SWPMI_STATE_RESET)
00165     {
00166       /* Allocate lock resource and initialize it */
00167       hswpmi->Lock = HAL_UNLOCKED;
00168       /* Init the low level hardware : GPIO, CLOCK, CORTEX */
00169       HAL_SWPMI_MspInit(hswpmi);
00170     }
00171
00172     hswpmi->State = HAL_SWPMI_STATE_BUSY;
00173
00174     /* Disable SWPMI interface */
00175     CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00176
00177     /* Apply Voltage class selection */
00178     MODIFY_REG(hswpmi->Instance->OR, SWPMI_OR_CLASS, hswpmi->Init.VoltageClass);
00179
00180     /* Configure the BRR register (Bitrate) */
00181     WRITE_REG(hswpmi->Instance->BRR, hswpmi->Init.BitRate);
00182
00183     /* Apply SWPMI CR configuration */
00184     MODIFY_REG(hswpmi->Instance->CR, \
00185                SWPMI_CR_RXDMA | SWPMI_CR_TXDMA  | SWPMI_CR_RXMODE | SWPMI_CR_TXMODE, \
00186                hswpmi->Init.TxBufferingMode | hswpmi->Init.RxBufferingMode);
00187
00188     hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
00189     hswpmi->State = HAL_SWPMI_STATE_READY;
00190     /*Enable the SWPMI transceiver.*/
00191     __HAL_SWPMI_TRANSCEIVER_ENABLE(hswpmi);
00192     /* Wait on TXBEF flag to be able to start a second transfer */
00193     if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_RDYF, tickstart, SWPMI_TIMEOUT_VALUE) != HAL_OK)
00194       {
00195         status = HAL_TIMEOUT;
00196       }
00197     /* Enable SWPMI peripheral if not */
00198     SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00199   }
00200
00201   return status;
00202 }
00203
00204 /**
00205   * @brief De-initialize the SWPMI peripheral.
00206   * @param hswpmi: SWPMI handle
00207   * @retval HAL status
00208   */
00209 HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi)
00210 {
00211   HAL_StatusTypeDef status = HAL_OK;
00212
00213   /* Check the SWPMI handle allocation */
00214   if(hswpmi == NULL)
00215   {
00216     status = HAL_ERROR;
00217   }
00218   else
00219   {
00220     /* Check the parameters */
00221     assert_param(IS_SWPMI_INSTANCE(hswpmi->Instance));
00222
00223     hswpmi->State = HAL_SWPMI_STATE_BUSY;
00224
00225     /* Disable SWPMI interface */
00226     CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00227
00228     /* Disable SWPMI transceiver */
00229     __HAL_SWPMI_TRANSCEIVER_DISABLE(hswpmi);
00230
00231     /* DeInit the low level hardware */
00232     HAL_SWPMI_MspDeInit(hswpmi);
00233
00234     hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
00235
00236     hswpmi->State = HAL_SWPMI_STATE_RESET;
00237
00238     /* Release Lock */
00239     __HAL_UNLOCK(hswpmi);
00240   }
00241
00242   return status;
00243 }
00244
00245 /**
00246   * @brief Initialize the SWPMI MSP.
00247   * @param hswpmi: SWPMI handle
00248   * @retval None
00249   */
00250 __weak void HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi)
00251 {
00252   /* Prevent unused argument(s) compilation warning */
00253   UNUSED(hswpmi);
00254
00255   /* NOTE : This function should not be modified, when the callback is needed,
00256             the HAL_SWPMI_MspInit can be implemented in the user file
00257    */
00258 }
00259
00260 /**
00261   * @brief DeInitialize the SWPMI MSP.
00262   * @param hswpmi: SWPMI handle
00263   * @retval None
00264   */
00265 __weak void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi)
00266 {
00267   /* Prevent unused argument(s) compilation warning */
00268   UNUSED(hswpmi);
00269
00270   /* NOTE : This function should not be modified, when the callback is needed,
00271             the HAL_SWPMI_MspDeInit can be implemented in the user file
00272    */
00273 }
00274
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup SWPMI_Exported_Group2 IO operation methods
00280   *  @brief SWPMI Transmit/Receive functions
00281   *
00282 @verbatim
00283  ===============================================================================
00284                       ##### IO operation methods #####
00285  ===============================================================================
00286  [..]
00287     This subsection provides a set of functions allowing to manage the SWPMI
00288      data transfers.
00289
00290     (#) There are two modes of transfer:
00291        (++) Blocking mode: The communication is performed in polling mode.
00292             The HAL status of all data processing is returned by the same function
00293             after finishing transfer.
00294        (++) Non-Blocking mode: The communication is performed using Interrupts
00295            or DMA. The end of the data processing will be indicated through the
00296            dedicated SWPMI Interrupt handler (HAL_SWPMI_IRQHandler()) when using Interrupt mode or
00297            the selected DMA channel interrupt handler when using DMA mode.
00298            The HAL_SWPMI_TxCpltCallback(), HAL_SWPMI_RxCpltCallback() user callbacks
00299            will be executed respectively at the end of the transmit or receive process.
00300            The HAL_SWPMI_ErrorCallback() user callback will be executed when a communication error is detected.
00301
00302     (#) Blocking mode API's are:
00303         (++) HAL_SWPMI_Transmit()
00304         (++) HAL_SWPMI_Receive()
00305
00306     (#) Non-Blocking mode API's with Interrupt are:
00307         (++) HAL_SWPMI_Transmit_IT()
00308         (++) HAL_SWPMI_Receive_IT()
00309         (++) HAL_SWPMI_IRQHandler()
00310
00311     (#) Non-Blocking mode API's with DMA are:
00312         (++) HAL_SWPMI_Transmit_DMA()
00313         (++) HAL_SWPMI_Receive_DMA()
00314         (++) HAL_SWPMI_DMAPause()
00315         (++) HAL_SWPMI_DMAResume()
00316         (++) HAL_SWPMI_DMAStop()
00317
00318     (#) A set of Transfer Complete Callbacks are provided in Non-Blocking mode:
00319         (++) HAL_SWPMI_TxHalfCpltCallback()
00320         (++) HAL_SWPMI_TxCpltCallback()
00321         (++) HAL_SWPMI_RxHalfCpltCallback()
00322         (++) HAL_SWPMI_RxCpltCallback()
00323         (++) HAL_SWPMI_ErrorCallback()
00324
00325     (#) The capability to launch the above IO operations in loopback mode for
00326         user application verification:
00327         (++) HAL_SWPMI_EnableLoopback()
00328         (++) HAL_SWPMI_DisableLoopback()
00329
00330 @endverbatim
00331   * @{
00332   */
00333
00334 /**
00335   * @brief  Transmit an amount of data in blocking mode.
00336   * @param  hswpmi: pointer to a SWPMI_HandleTypeDef structure that contains
00337   *                the configuration information for SWPMI module.
00338   * @param  pData: Pointer to data buffer
00339   * @param  Size: Amount of data to be sent
00340   * @param  Timeout: Timeout duration
00341   * @retval HAL status
00342   */
00343 HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pData, uint16_t Size, uint32_t Timeout)
00344 {
00345   uint32_t tickstart = HAL_GetTick();
00346   HAL_StatusTypeDef status = HAL_OK;
00347
00348   if((pData == NULL ) || (Size == 0))
00349   {
00350     status = HAL_ERROR;
00351   }
00352   else
00353   {
00354     /* Process Locked */
00355     __HAL_LOCK(hswpmi);
00356
00357     if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_RX))
00358     {
00359       /* Check if a non-blocking receive process is ongoing or not */
00360       if(hswpmi->State == HAL_SWPMI_STATE_READY)
00361       {
00362         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
00363
00364         /* Disable any transmitter interrupts */
00365         __HAL_SWPMI_DISABLE_IT(hswpmi, SWPMI_IT_TCIE | SWPMI_IT_TIE | SWPMI_IT_TXUNRIE | SWPMI_IT_TXBEIE);
00366
00367         /* Disable any transmitter flags */
00368         __HAL_SWPMI_CLEAR_FLAG(hswpmi, SWPMI_FLAG_TXBEF | SWPMI_FLAG_TXUNRF | SWPMI_FLAG_TCF);
00369
00370         /* Enable SWPMI peripheral if not */
00371         SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00372       }
00373       else
00374       {
00375         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
00376       }
00377
00378       do
00379       {
00380         /* Wait the TXE to write data */
00381         if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_TXE))
00382         {
00383           hswpmi->Instance->TDR = (*pData++);
00384           Size--;
00385         }
00386         else
00387         {
00388           /* Check for the Timeout */
00389           if(Timeout != HAL_MAX_DELAY)
00390           {
00391             if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
00392             {
00393               status = HAL_TIMEOUT;
00394               break;
00395             }
00396           }
00397         }
00398       } while(Size != 0);
00399
00400       /* Wait on TXBEF flag to be able to start a second transfer */
00401       if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, Timeout) != HAL_OK)
00402       {
00403         status = HAL_TIMEOUT;
00404       }
00405
00406       if(status == HAL_OK)
00407       {
00408         /* Check if a non-blocking receive Process is ongoing or not */
00409         if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
00410         {
00411           hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
00412         }
00413         else
00414         {
00415           hswpmi->State = HAL_SWPMI_STATE_READY;
00416         }
00417       }
00418     }
00419     else
00420     {
00421       status = HAL_BUSY;
00422     }
00423   }
00424
00425   if((status != HAL_OK) && (status != HAL_BUSY))
00426   {
00427     hswpmi->State = HAL_SWPMI_STATE_READY;
00428   }
00429   /* Process Unlocked */
00430   __HAL_UNLOCK(hswpmi);
00431
00432   return status;
00433 }
00434
00435 /**
00436   * @brief  Receive an amount of data in blocking mode.
00437   * @param  hswpmi: pointer to a SWPMI_HandleTypeDef structure that contains
00438   *                the configuration information for SWPMI module.
00439   * @param  pData: Pointer to data buffer
00440   * @param  Size: Amount of data to be received
00441   * @param  Timeout: Timeout duration
00442   * @retval HAL status
00443   */
00444 HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
00445 {
00446   uint32_t tickstart = HAL_GetTick();
00447   HAL_StatusTypeDef status = HAL_OK;
00448
00449   if((pData == NULL ) || (Size == 0))
00450   {
00451     status = HAL_ERROR;
00452   }
00453   else
00454   {
00455     /* Process Locked */
00456     __HAL_LOCK(hswpmi);
00457
00458     if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX))
00459     {
00460       /* Check if a non-blocking transmit process is ongoing or not */
00461       if(hswpmi->State == HAL_SWPMI_STATE_READY)
00462       {
00463         hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
00464
00465         /* Disable any receiver interrupts */
00466         CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_SRIE | SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE);
00467
00468         /* Enable SWPMI peripheral if not */
00469         SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00470       }
00471       else
00472       {
00473         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
00474       }
00475
00476       do
00477       {
00478         /* Wait the RXNE to read data */
00479         if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXNE))
00480         {
00481           (*pData++) = hswpmi->Instance->RDR;
00482           Size--;
00483         }
00484         else
00485         {
00486           /* Check for the Timeout */
00487           if(Timeout != HAL_MAX_DELAY)
00488           {
00489             if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
00490             {
00491               status = HAL_TIMEOUT;
00492               break;
00493             }
00494           }
00495         }
00496       } while(Size != 0);
00497
00498       if(status == HAL_OK)
00499       {
00500         if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXBFF))
00501         {
00502           /* Clear RXBFF at end of reception */
00503           WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBFF);
00504         }
00505
00506         /* Check if a non-blocking transmit Process is ongoing or not */
00507         if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
00508         {
00509           hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
00510         }
00511         else
00512         {
00513           hswpmi->State = HAL_SWPMI_STATE_READY;
00514         }
00515       }
00516     }
00517     else
00518     {
00519       status = HAL_BUSY;
00520     }
00521   }
00522
00523   if((status != HAL_OK) && (status != HAL_BUSY))
00524   {
00525     hswpmi->State = HAL_SWPMI_STATE_READY;
00526   }
00527   /* Process Unlocked */
00528   __HAL_UNLOCK(hswpmi);
00529
00530   return status;
00531 }
00532
00533 /**
00534   * @brief  Transmit an amount of data in non-blocking mode with interrupt.
00535   * @param  hswpmi: pointer to a SWPMI_HandleTypeDef structure that contains
00536   *                the configuration information for SWPMI module.
00537   * @param  pData: Pointer to data buffer
00538   * @param  Size: Amount of data to be sent
00539   * @retval HAL status
00540   */
00541 HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
00542 {
00543   HAL_StatusTypeDef status = HAL_OK;
00544
00545   if((pData == NULL ) || (Size == 0))
00546   {
00547     status =  HAL_ERROR;
00548   }
00549   else
00550   {
00551     /* Process Locked */
00552     __HAL_LOCK(hswpmi);
00553
00554     if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_RX))
00555     {
00556       /* Update handle */
00557       hswpmi->pTxBuffPtr = pData;
00558       hswpmi->TxXferSize = Size;
00559       hswpmi->TxXferCount = Size;
00560       hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
00561
00562       /* Check if a receive process is ongoing or not */
00563       if(hswpmi->State == HAL_SWPMI_STATE_READY)
00564       {
00565         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
00566
00567         /* Enable SWPMI peripheral if not */
00568         SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00569       }
00570       else
00571       {
00572         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
00573       }
00574
00575       /* Enable the SWPMI transmit underrun error */
00576       __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_TXUNRIE);
00577
00578       /* Process Unlocked */
00579       __HAL_UNLOCK(hswpmi);
00580
00581       /* Enable the SWPMI interrupts:      */
00582       /* - Transmit data register empty    */
00583       /* - Transmit buffer empty           */
00584       /* - Transmit/Reception completion   */
00585       __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_TIE | SWPMI_IT_TXBEIE | SWPMI_IT_TCIE);
00586     }
00587     else
00588     {
00589       status =  HAL_BUSY;
00590
00591       /* Process Unlocked */
00592       __HAL_UNLOCK(hswpmi);
00593     }
00594   }
00595
00596   return status;
00597 }
00598
00599 /**
00600   * @brief Receive an amount of data in non-blocking mode with interrupt.
00601   * @param hswpmi: SWPMI handle
00602   * @param pData: pointer to data buffer
00603   * @param Size: amount of data to be received
00604   * @retval HAL status
00605   */
00606 HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
00607 {
00608   HAL_StatusTypeDef status = HAL_OK;
00609
00610   if((pData == NULL ) || (Size == 0))
00611   {
00612     status =  HAL_ERROR;
00613   }
00614   else
00615   {
00616     /* Process Locked */
00617     __HAL_LOCK(hswpmi);
00618
00619     if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX))
00620     {
00621       /* Update handle */
00622       hswpmi->pRxBuffPtr = pData;
00623       hswpmi->RxXferSize = Size;
00624       hswpmi->RxXferCount = Size;
00625       hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
00626
00627       /* Check if a transmit process is ongoing or not */
00628       if(hswpmi->State == HAL_SWPMI_STATE_READY)
00629       {
00630         hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
00631
00632         /* Enable SWPMI peripheral if not */
00633         SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00634       }
00635       else
00636       {
00637         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
00638       }
00639
00640       /* Process Unlocked */
00641       __HAL_UNLOCK(hswpmi);
00642
00643       /* Enable the SWPMI slave resume */
00644       /* Enable the SWPMI Data Register not empty Interrupt, receive CRC Error, receive overrun and RxBuf Interrupt */
00645       /*  Enable the SWPMI Transmit/Reception completion   */
00646       __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE);
00647     }
00648     else
00649     {
00650       status = HAL_BUSY;
00651
00652       /* Process Unlocked */
00653       __HAL_UNLOCK(hswpmi);
00654     }
00655   }
00656
00657   return status;
00658 }
00659
00660 /**
00661   * @brief Transmit an amount of data in non-blocking mode with DMA interrupt.
00662   * @param hswpmi: SWPMI handle
00663   * @param pData: pointer to data buffer
00664   * @param Size: amount of data to be sent
00665   * @retval HAL status
00666   */
00667 HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
00668 {
00669   HAL_StatusTypeDef status = HAL_OK;
00670
00671   if((pData == NULL ) || (Size == 0))
00672   {
00673     status =  HAL_ERROR;
00674   }
00675   else
00676   {
00677     /* Process Locked */
00678     __HAL_LOCK(hswpmi);
00679
00680     if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_RX))
00681     {
00682       /* Update handle */
00683       hswpmi->pTxBuffPtr = pData;
00684       hswpmi->TxXferSize = Size;
00685       hswpmi->TxXferCount = Size;
00686       hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
00687
00688       /* Check if a receive process is ongoing or not */
00689       if(hswpmi->State == HAL_SWPMI_STATE_READY)
00690       {
00691         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
00692
00693         /* Enable SWPMI peripheral if not */
00694         SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00695       }
00696       else
00697       {
00698         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
00699       }
00700
00701       /* Set the SWPMI DMA transfer complete callback */
00702       hswpmi->hdmatx->XferCpltCallback = SWPMI_DMATransmitCplt;
00703
00704       /* Set the SWPMI DMA Half transfer complete callback */
00705       hswpmi->hdmatx->XferHalfCpltCallback = SWPMI_DMATxHalfCplt;
00706
00707       /* Set the DMA error callback */
00708       hswpmi->hdmatx->XferErrorCallback = SWPMI_DMAError;
00709
00710       /* Enable the SWPMI transmit DMA Stream */
00711       HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size);
00712
00713       /* Process Unlocked */
00714       __HAL_UNLOCK(hswpmi);
00715
00716       /* Enable the SWPMI transmit underrun error */
00717       __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_TXUNRIE);
00718
00719       /* Enable the DMA transfer for transmit request by setting the TXDMA bit
00720          in the SWPMI CR register */
00721       SET_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
00722     }
00723     else
00724     {
00725       status = HAL_BUSY;
00726
00727       /* Process Unlocked */
00728       __HAL_UNLOCK(hswpmi);
00729     }
00730   }
00731
00732   return status;
00733 }
00734
00735 /**
00736   * @brief Receive an amount of data in non-blocking mode with DMA interrupt.
00737   * @param hswpmi: SWPMI handle
00738   * @param pData: pointer to data buffer
00739   * @param Size: amount of data to be received
00740   * @retval HAL status
00741   */
00742 HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
00743 {
00744   HAL_StatusTypeDef status = HAL_OK;
00745
00746   if((pData == NULL ) || (Size == 0))
00747   {
00748     status =  HAL_ERROR;
00749   }
00750   else
00751   {
00752     /* Process Locked */
00753     __HAL_LOCK(hswpmi);
00754
00755     if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX))
00756     {
00757       /* Update handle */
00758       hswpmi->pRxBuffPtr = pData;
00759       hswpmi->RxXferSize = Size;
00760       hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
00761
00762       /* Check if a transmit process is ongoing or not */
00763       if(hswpmi->State == HAL_SWPMI_STATE_READY)
00764       {
00765         hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
00766
00767         /* Enable SWPMI peripheral if not */
00768         SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00769       }
00770       else
00771       {
00772         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
00773       }
00774
00775       /* Set the SWPMI DMA transfer complete callback */
00776       hswpmi->hdmarx->XferCpltCallback = SWPMI_DMAReceiveCplt;
00777
00778       /* Set the SWPMI DMA Half transfer complete callback */
00779       hswpmi->hdmarx->XferHalfCpltCallback = SWPMI_DMARxHalfCplt;
00780
00781       /* Set the DMA error callback */
00782       hswpmi->hdmarx->XferErrorCallback = SWPMI_DMAError;
00783
00784       /* Enable the DMA request */
00785       HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size);
00786
00787       /* Process Unlocked */
00788       __HAL_UNLOCK(hswpmi);
00789
00790       /* Enable the SWPMI receive CRC Error and receive overrun interrupts */
00791       __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE);
00792
00793       /* Enable the DMA transfer for the receiver request by setting the RXDMA bit
00794          in the SWPMI CR register */
00795       SET_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
00796     }
00797     else
00798     {
00799       status = HAL_BUSY;
00800
00801       /* Process Unlocked */
00802       __HAL_UNLOCK(hswpmi);
00803     }
00804   }
00805
00806   return status;
00807 }
00808
00809 /**
00810   * @brief Stop all DMA transfers.
00811   * @param hswpmi: SWPMI handle
00812   * @retval HAL_OK
00813   */
00814 HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi)
00815 {
00816   /* Process Locked */
00817   __HAL_LOCK(hswpmi);
00818
00819   /* Disable the SWPMI Tx/Rx DMA requests */
00820   CLEAR_BIT(hswpmi->Instance->CR, (SWPMI_CR_TXDMA | SWPMI_CR_RXDMA));
00821
00822   /* Abort the SWPMI DMA tx channel */
00823   if(hswpmi->hdmatx != NULL)
00824   {
00825     HAL_DMA_Abort(hswpmi->hdmatx);
00826   }
00827   /* Abort the SWPMI DMA rx channel */
00828   if(hswpmi->hdmarx != NULL)
00829   {
00830     HAL_DMA_Abort(hswpmi->hdmarx);
00831   }
00832
00833   /* Disable SWPMI interface */
00834   CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00835
00836   hswpmi->State = HAL_SWPMI_STATE_READY;
00837
00838   /* Process Unlocked */
00839   __HAL_UNLOCK(hswpmi);
00840
00841   return HAL_OK;
00842 }
00843
00844
00845 /**
00846   * @brief Enable the Loopback mode.
00847   * @param hswpmi: SWPMI handle
00848   * @note  Loopback mode is to be used only for test purposes
00849   * @retval HAL_OK / HAL_BUSY
00850   */
00851 HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi)
00852 {
00853   HAL_StatusTypeDef  status = HAL_OK;
00854
00855   /* Process Locked */
00856   __HAL_LOCK(hswpmi);
00857
00858   /* Check SWPMI not enabled */
00859   if(READ_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT) != RESET)
00860   {
00861     status = HAL_BUSY;
00862   }
00863   else
00864   {
00865     /* Set Loopback */
00866     SET_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK);
00867   }
00868
00869   /* Process Unlocked */
00870   __HAL_UNLOCK(hswpmi);
00871
00872   return status;
00873 }
00874
00875 /**
00876   * @brief Disable the Loopback mode.
00877   * @param hswpmi: SWPMI handle
00878   * @note  Loopback mode is to be used only for test purposes
00879   * @retval HAL_OK / HAL_BUSY
00880   */
00881 HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi)
00882 {
00883   HAL_StatusTypeDef  status = HAL_OK;
00884
00885   /* Process Locked */
00886   __HAL_LOCK(hswpmi);
00887
00888   /* Check SWPMI not enabled */
00889   if(READ_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT) != RESET)
00890   {
00891     status = HAL_BUSY;
00892   }
00893   else
00894   {
00895     /* Reset Loopback */
00896     CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK);
00897   }
00898
00899   /* Process Unlocked */
00900   __HAL_UNLOCK(hswpmi);
00901
00902   return status;
00903 }
00904
00905 /**
00906   * @}
00907   */
00908
00909 /** @defgroup SWPMI_Exported_Group3 SWPMI IRQ handler and callbacks
00910  *  @brief  SWPMI  IRQ handler.
00911  *
00912 @verbatim
00913   ==============================================================================
00914                       ##### SWPMI IRQ handler and callbacks  #####
00915   ==============================================================================
00916 [..]  This section provides SWPMI IRQ handler and callback functions called within
00917       the IRQ handler.
00918
00919 @endverbatim
00920   * @{
00921   */
00922
00923 /**
00924   * @brief Handle SWPMI interrupt request.
00925   * @param hswpmi: SWPMI handle
00926   * @retval None
00927   */
00928 void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi)
00929 {
00930
00931   uint32_t regisr = READ_REG(hswpmi->Instance->ISR);
00932   uint32_t regier = READ_REG(hswpmi->Instance->IER);
00933   uint32_t errcode = HAL_SWPMI_ERROR_NONE;
00934
00935   /* SWPMI CRC error interrupt occurred --------------------------------------*/
00936   if(((regisr & SWPMI_FLAG_RXBERF) != RESET) && ((regier & SWPMI_IT_RXBERIE) != RESET))
00937   {
00938     /* Disable Receive CRC interrupt */
00939     CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXBERIE | SWPMI_IT_RXBFIE);
00940     /* Clear Receive CRC and Receive buffer full flag */
00941     WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBERF | SWPMI_FLAG_RXBFF);
00942
00943     errcode |= HAL_SWPMI_ERROR_CRC;
00944   }
00945
00946   /* SWPMI Over-Run interrupt occurred -----------------------------------------*/
00947   if(((regisr & SWPMI_FLAG_RXOVRF) != RESET) && ((regier & SWPMI_IT_RXOVRIE) != RESET))
00948   {
00949     /* Disable Receive overrun interrupt */
00950     CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXOVRIE);
00951     /* Clear Receive overrun flag */
00952     WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXOVRF);
00953
00954     errcode |= HAL_SWPMI_ERROR_OVR;
00955   }
00956
00957   /* SWPMI Under-Run interrupt occurred -----------------------------------------*/
00958   if(((regisr & SWPMI_FLAG_TXUNRF) != RESET) && ((regier & SWPMI_IT_TXUNRIE) != RESET))
00959   {
00960     /* Disable Transmit under run interrupt */
00961     CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TXUNRIE);
00962     /* Clear Transmit under run flag */
00963     WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TXUNRF);
00964
00965     errcode |= HAL_SWPMI_ERROR_UDR;
00966   }
00967
00968    /* Call SWPMI Error Call back function if needed --------------------------*/
00969   if(errcode != HAL_SWPMI_ERROR_NONE)
00970   {
00971     hswpmi->ErrorCode |= errcode;
00972
00973     if((errcode & HAL_SWPMI_ERROR_UDR) != RESET)
00974     {
00975       /* Check TXDMA transfer to abort */
00976       if(HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_TXDMA))
00977       {
00978         /* Disable DMA TX at SWPMI level */
00979         CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
00980
00981         /* Abort the USART DMA Tx channel */
00982         if(hswpmi->hdmatx != NULL)
00983         {
00984           /* Set the SWPMI Tx DMA Abort callback :
00985              will lead to call HAL_SWPMI_ErrorCallback() at end of DMA abort procedure */
00986           hswpmi->hdmatx->XferAbortCallback = SWPMI_DMAAbortOnError;
00987           /* Abort DMA TX */
00988           if(HAL_DMA_Abort_IT(hswpmi->hdmatx) != HAL_OK)
00989           {
00990             /* Call Directly hswpmi->hdmatx->XferAbortCallback function in case of error */
00991             hswpmi->hdmatx->XferAbortCallback(hswpmi->hdmatx);
00992           }
00993         }
00994         else
00995         {
00996           /* Set the SWPMI state ready to be able to start again the process */
00997           hswpmi->State = HAL_SWPMI_STATE_READY;
00998
00999           HAL_SWPMI_ErrorCallback(hswpmi);
01000         }
01001       }
01002       else
01003       {
01004         /* Set the SWPMI state ready to be able to start again the process */
01005         hswpmi->State = HAL_SWPMI_STATE_READY;
01006
01007         HAL_SWPMI_ErrorCallback(hswpmi);
01008       }
01009     }
01010     else
01011     {
01012       /* Check RXDMA transfer to abort */
01013       if(HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_RXDMA))
01014       {
01015         /* Disable DMA RX at SWPMI level */
01016         CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
01017
01018         /* Abort the USART DMA Rx channel */
01019         if(hswpmi->hdmarx != NULL)
01020         {
01021           /* Set the SWPMI Rx DMA Abort callback :
01022              will lead to call HAL_SWPMI_ErrorCallback() at end of DMA abort procedure */
01023           hswpmi->hdmarx->XferAbortCallback = SWPMI_DMAAbortOnError;
01024           /* Abort DMA RX */
01025           if(HAL_DMA_Abort_IT(hswpmi->hdmarx) != HAL_OK)
01026           {
01027             /* Call Directly hswpmi->hdmarx->XferAbortCallback function in case of error */
01028             hswpmi->hdmarx->XferAbortCallback(hswpmi->hdmarx);
01029           }
01030         }
01031         else
01032         {
01033           /* Set the SWPMI state ready to be able to start again the process */
01034           hswpmi->State = HAL_SWPMI_STATE_READY;
01035
01036           HAL_SWPMI_ErrorCallback(hswpmi);
01037         }
01038       }
01039       else
01040       {
01041         /* Set the SWPMI state ready to be able to start again the process */
01042         hswpmi->State = HAL_SWPMI_STATE_READY;
01043
01044         HAL_SWPMI_ErrorCallback(hswpmi);
01045       }
01046     }
01047   }
01048
01049   /* SWPMI in mode Receiver ---------------------------------------------------*/
01050   if(((regisr & SWPMI_FLAG_RXNE) != RESET) && ((regier & SWPMI_IT_RIE)  != RESET))
01051   {
01052     SWPMI_Receive_IT(hswpmi);
01053   }
01054
01055   /* SWPMI in mode Transmitter ------------------------------------------------*/
01056   if(((regisr & SWPMI_FLAG_TXE) != RESET) && ((regier & SWPMI_IT_TIE) != RESET))
01057   {
01058     SWPMI_Transmit_IT(hswpmi);
01059   }
01060
01061   /* SWPMI in mode Transmitter (Transmit buffer empty) ------------------------*/
01062   if(((regisr & SWPMI_FLAG_TXBEF) != RESET) && ((regier & SWPMI_IT_TXBEIE) != RESET))
01063   {
01064     SWPMI_EndTransmit_IT(hswpmi);
01065   }
01066
01067   /* SWPMI in mode Receiver (Receive buffer full) -----------------------------*/
01068   if(((regisr & SWPMI_FLAG_RXBFF) != RESET) && ((regier & SWPMI_IT_RXBFIE) != RESET))
01069   {
01070     SWPMI_EndReceive_IT(hswpmi);
01071   }
01072
01073   /* Both Transmission and reception complete ---------------------------------*/
01074   if(((regisr & SWPMI_FLAG_TCF) != RESET) && ((regier & SWPMI_IT_TCIE) != RESET))
01075   {
01076     SWPMI_EndTransmitReceive_IT(hswpmi);
01077   }
01078 }
01079
01080 /**
01081   * @brief Tx Transfer completed callback.
01082   * @param hswpmi: SWPMI handle
01083   * @retval None
01084   */
01085 __weak void HAL_SWPMI_TxCpltCallback(SWPMI_HandleTypeDef *hswpmi)
01086 {
01087   /* Prevent unused argument(s) compilation warning */
01088   UNUSED(hswpmi);
01089
01090   /* NOTE : This function should not be modified, when the callback is needed,
01091             the HAL_SWPMI_TxCpltCallback is to be implemented in the user file
01092    */
01093 }
01094
01095 /**
01096   * @brief  Tx Half Transfer completed callback.
01097   * @param  hswpmi: SWPMI handle
01098   * @retval None
01099   */
01100 __weak void HAL_SWPMI_TxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi)
01101 {
01102   /* Prevent unused argument(s) compilation warning */
01103   UNUSED(hswpmi);
01104
01105   /* NOTE: This function should not be modified, when the callback is needed,
01106            the HAL_SWPMI_TxHalfCpltCallback is to be implemented in the user file
01107    */
01108 }
01109
01110 /**
01111   * @brief Rx Transfer completed callback.
01112   * @param hswpmi: SWPMI handle
01113   * @retval None
01114   */
01115 __weak void HAL_SWPMI_RxCpltCallback(SWPMI_HandleTypeDef *hswpmi)
01116 {
01117   /* Prevent unused argument(s) compilation warning */
01118   UNUSED(hswpmi);
01119
01120   /* NOTE : This function should not be modified, when the callback is needed,
01121             the HAL_SWPMI_RxCpltCallback is to be implemented in the user file
01122    */
01123 }
01124
01125 /**
01126   * @brief  Rx Half Transfer completed callback.
01127   * @param  hswpmi: SWPMI handle
01128   * @retval None
01129   */
01130 __weak void HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi)
01131 {
01132   /* Prevent unused argument(s) compilation warning */
01133   UNUSED(hswpmi);
01134
01135   /* NOTE: This function should not be modified, when the callback is needed,
01136            the HAL_SWPMI_RxHalfCpltCallback is to be implemented in the user file
01137    */
01138 }
01139
01140 /**
01141   * @brief SWPMI error callback.
01142   * @param hswpmi: SWPMI handle
01143   * @retval None
01144   */
01145 __weak void HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi)
01146 {
01147   /* Prevent unused argument(s) compilation warning */
01148   UNUSED(hswpmi);
01149
01150   /* NOTE : This function should not be modified, when the callback is needed,
01151             the HAL_SWPMI_ErrorCallback is to be implemented in the user file
01152    */
01153 }
01154
01155 /**
01156   * @}
01157   */
01158
01159 /** @defgroup SWPMI_Exported_Group4 Peripheral Control methods
01160   *  @brief   SWPMI control functions
01161   *
01162 @verbatim
01163  ===============================================================================
01164                       ##### Peripheral Control methods #####
01165  ===============================================================================
01166     [..]
01167     This subsection provides a set of functions allowing to control the SWPMI.
01168      (+) HAL_SWPMI_GetState() API is helpful to check in run-time the state of the SWPMI peripheral
01169      (+) HAL_SWPMI_GetError() API is helpful to check in run-time the error state of the SWPMI peripheral
01170 @endverbatim
01171   * @{
01172   */
01173
01174 /**
01175   * @brief Return the SWPMI handle state.
01176   * @param hswpmi: SWPMI handle
01177   * @retval HAL state
01178   */
01179 HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi)
01180 {
01181   /* Return SWPMI handle state */
01182   return hswpmi->State;
01183 }
01184
01185 /**
01186 * @brief  Return the SWPMI error code.
01187 * @param  hswpmi : pointer to a SWPMI_HandleTypeDef structure that contains
01188   *              the configuration information for the specified SWPMI.
01189 * @retval SWPMI Error Code
01190 */
01191 uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi)
01192 {
01193   return hswpmi->ErrorCode;
01194 }
01195
01196 /**
01197   * @}
01198   */
01199
01200 /**
01201   * @}
01202   */
01203
01204 /* Private functions ---------------------------------------------------------*/
01205
01206 /** @defgroup SWPMI_Private_Functions SWPMI Private Functions
01207   * @{
01208   */
01209
01210 /**
01211   * @brief Transmit an amount of data in interrupt mode.
01212   * @note  Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Transmit_IT()
01213   * @param  hswpmi: SWPMI handle
01214   * @retval HAL status
01215   */
01216 static HAL_StatusTypeDef SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi)
01217 {
01218   HAL_StatusTypeDef status = HAL_OK;
01219
01220   if ((hswpmi->State == HAL_SWPMI_STATE_BUSY_TX) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX))
01221   {
01222     if(hswpmi->TxXferCount == 0)
01223     {
01224       /* Disable the SWPMI TXE and Underrun Interrupts */
01225       CLEAR_BIT(hswpmi->Instance->IER, (SWPMI_IT_TIE | SWPMI_IT_TXUNRIE));
01226     }
01227     else
01228     {
01229       hswpmi->Instance->TDR = (uint32_t)(*hswpmi->pTxBuffPtr++);
01230       hswpmi->TxXferCount--;
01231     }
01232   }
01233   else
01234   {
01235     status = HAL_BUSY;
01236   }
01237
01238   return status;
01239 }
01240
01241 /**
01242   * @brief  Wraps up transmission in non-blocking mode.
01243   * @param  hswpmi: SWPMI handle
01244   * @retval HAL status
01245   * @retval HAL status
01246   */
01247 static HAL_StatusTypeDef SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi)
01248 {
01249   /* Clear the SWPMI Transmit buffer empty Flag */
01250   WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TXBEF);
01251   /* Disable the all SWPMI Transmit Interrupts  */
01252   CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TIE | SWPMI_IT_TXUNRIE | SWPMI_IT_TXBEIE);
01253
01254   /* Check if a receive Process is ongoing or not */
01255   if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
01256   {
01257     hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
01258   }
01259   else
01260   {
01261     hswpmi->State = HAL_SWPMI_STATE_READY;
01262   }
01263
01264   HAL_SWPMI_TxCpltCallback(hswpmi);
01265
01266   return HAL_OK;
01267 }
01268
01269 /**
01270   * @brief Receive an amount of data in interrupt mode.
01271   * @note  Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Receive_IT()
01272   * @param  hswpmi: SWPMI handle
01273   * @retval HAL status
01274   */
01275 static HAL_StatusTypeDef SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi)
01276 {
01277   HAL_StatusTypeDef status = HAL_OK;
01278
01279   if((hswpmi->State == HAL_SWPMI_STATE_BUSY_RX) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX))
01280   {
01281     *hswpmi->pRxBuffPtr++ = (uint32_t)(hswpmi->Instance->RDR);
01282
01283     if(--hswpmi->RxXferCount == 0)
01284     {
01285       /* Wait for RXBFF flag to update state */
01286       HAL_SWPMI_RxCpltCallback(hswpmi);
01287     }
01288   }
01289   else
01290   {
01291     status = HAL_BUSY;
01292   }
01293
01294   return status;
01295 }
01296
01297 /**
01298   * @brief  Wraps up reception in non-blocking mode.
01299   * @param  hswpmi: SWPMI handle
01300   * @retval HAL status
01301   * @retval HAL status
01302   */
01303 static HAL_StatusTypeDef SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi)
01304 {
01305   /* Clear the SWPMI Receive buffer full Flag */
01306   WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBFF);
01307   /* Disable the all SWPMI Receive Interrupts  */
01308   CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE);
01309
01310   /* Check if a transmit Process is ongoing or not */
01311   if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
01312   {
01313     hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
01314   }
01315   else
01316   {
01317     hswpmi->State = HAL_SWPMI_STATE_READY;
01318   }
01319
01320   return HAL_OK;
01321 }
01322
01323 /**
01324   * @brief  Wraps up transmission and reception in non-blocking mode.
01325   * @param  hswpmi: SWPMI handle
01326   * @retval HAL status
01327   * @retval HAL status
01328   */
01329 static HAL_StatusTypeDef SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi)
01330 {
01331   /* Clear the SWPMI Transmission Complete Flag */
01332   WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TCF);
01333   /* Disable the SWPMI Transmission  Complete Interrupt */
01334   CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TCIE);
01335
01336   /* Check if a receive Process is ongoing or not */
01337   if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
01338   {
01339     hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
01340   }
01341   else if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX)
01342   {
01343     hswpmi->State = HAL_SWPMI_STATE_READY;
01344   }
01345
01346   return HAL_OK;
01347 }
01348
01349 /**
01350   * @brief DMA SWPMI transmit process complete callback.
01351   * @param hdma: DMA handle
01352   * @retval None
01353   */
01354 static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01355 {
01356   SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01357   uint32_t tickstart = 0;
01358
01359   /* DMA Normal mode*/
01360   if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) != SET)
01361   {
01362     hswpmi->TxXferCount = 0;
01363
01364     /* Disable the DMA transfer for transmit request by setting the TXDMA bit
01365     in the SWPMI CR register */
01366     CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
01367
01368     /* Init tickstart for timeout managment*/
01369     tickstart = HAL_GetTick();
01370
01371     /* Wait the TXBEF */
01372     if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, SWPMI_TIMEOUT_VALUE) != HAL_OK)
01373     {
01374       /* Timeout occurred */
01375       HAL_SWPMI_ErrorCallback(hswpmi);
01376     }
01377     else
01378     {
01379       /* No Timeout */
01380       /* Check if a receive process is ongoing or not */
01381       if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
01382       {
01383         hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
01384       }
01385       else
01386       {
01387         hswpmi->State = HAL_SWPMI_STATE_READY;
01388       }
01389
01390       HAL_SWPMI_TxCpltCallback(hswpmi);
01391     }
01392   }
01393   /* DMA Circular mode */
01394   else
01395   {
01396     HAL_SWPMI_TxCpltCallback(hswpmi);
01397   }
01398 }
01399
01400 /**
01401   * @brief DMA SWPMI transmit process half complete callback.
01402   * @param hdma : DMA handle
01403   * @retval None
01404   */
01405 static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01406 {
01407   SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01408
01409   HAL_SWPMI_TxHalfCpltCallback(hswpmi);
01410 }
01411
01412
01413 /**
01414   * @brief DMA SWPMI receive process complete callback.
01415   * @param hdma: DMA handle
01416   * @retval None
01417   */
01418 static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01419 {
01420   SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01421
01422   /* DMA Normal mode*/
01423   if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == RESET)
01424   {
01425     hswpmi->RxXferCount = 0;
01426
01427     /* Disable the DMA transfer for the receiver request by setting the RXDMA bit
01428     in the SWPMI CR register */
01429     CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
01430
01431     /* Check if a transmit Process is ongoing or not */
01432     if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
01433     {
01434       hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
01435     }
01436     else
01437     {
01438       hswpmi->State = HAL_SWPMI_STATE_READY;
01439     }
01440   }
01441   HAL_SWPMI_RxCpltCallback(hswpmi);
01442 }
01443
01444 /**
01445   * @brief DMA SWPMI receive process half complete callback.
01446   * @param hdma : DMA handle
01447   * @retval None
01448   */
01449 static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01450 {
01451   SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01452
01453   HAL_SWPMI_RxHalfCpltCallback(hswpmi);
01454 }
01455
01456 /**
01457   * @brief DMA SWPMI communication error callback.
01458   * @param hdma: DMA handle
01459   * @retval None
01460   */
01461 static void SWPMI_DMAError(DMA_HandleTypeDef *hdma)
01462 {
01463   SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01464
01465   /* Update handle */
01466   hswpmi->RxXferCount = 0;
01467   hswpmi->TxXferCount = 0;
01468   hswpmi->State= HAL_SWPMI_STATE_READY;
01469   hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA;
01470
01471   HAL_SWPMI_ErrorCallback(hswpmi);
01472 }
01473 /**
01474   * @brief DMA SWPMI communication abort callback.
01475   * @param hdma: DMA handle
01476   * @retval None
01477   */
01478 static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
01479 {
01480   SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01481
01482   /* Update handle */
01483   hswpmi->RxXferCount = 0;
01484   hswpmi->TxXferCount = 0;
01485   hswpmi->State= HAL_SWPMI_STATE_READY;
01486
01487   HAL_SWPMI_ErrorCallback(hswpmi);
01488 }
01489
01490 /**
01491   * @brief  Handle SWPMI Communication Timeout.
01492   * @param  hswpmi: SWPMI handle
01493   * @param  Flag: specifies the SWPMI flag to check.
01494   * @param  Tickstart Tick start value
01495   * @param  Timeout timeout duration.
01496   * @retval HAL status
01497   */
01498 static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout)
01499 {
01500   HAL_StatusTypeDef status = HAL_OK;
01501
01502   /* Wait until flag is set */
01503   while(!(HAL_IS_BIT_SET(hswpmi->Instance->ISR, Flag)))
01504   {
01505     /* Check for the Timeout */
01506     if(Timeout != HAL_MAX_DELAY)
01507     {
01508       if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
01509       {
01510         hswpmi->State = HAL_SWPMI_STATE_READY;
01511
01512         status = HAL_TIMEOUT;
01513         break;
01514       }
01515     }
01516   }
01517
01518   return status;
01519 }
01520
01521 /**
01522   * @}
01523   */
01524
01525 #endif /* HAL_SWPMI_MODULE_ENABLED */
01526 /**
01527   * @}
01528   */
01529
01530 /**
01531   * @}
01532   */
01533
01534 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_swpmi.h Source File

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stm32h7xx_hal_swpmi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_swpmi.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of SWPMI HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_SWPMI_H
00040 #define __STM32H7xx_HAL_SWPMI_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SWPMI
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup SWPMI_Exported_Types SWPMI Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief SWPMI Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t VoltageClass;             /*!< Specifies the SWP Voltage Class.
00068                                           This parameter can be a value of @ref SWPMI_Voltage_Class */
00069
00070   uint32_t BitRate;                  /*!< Specifies the SWPMI Bitrate.
00071                                           This parameter must be a number between 0 and 63.
00072                                           The Bitrate is computed using the following formula:
00073                                           SWPMI_freq = SWPMI_clk / (((BitRate) + 1)  * 4)
00074                                           */
00075
00076   uint32_t TxBufferingMode;          /*!< Specifies the transmission buffering mode.
00077                                           This parameter can be a value of @ref SWPMI_Tx_Buffering_Mode */
00078
00079   uint32_t RxBufferingMode;          /*!< Specifies the reception buffering mode.
00080                                           This parameter can be a value of @ref SWPMI_Rx_Buffering_Mode */
00081
00082 }SWPMI_InitTypeDef;
00083
00084
00085 /**
00086   * @brief HAL SWPMI State structures definition
00087   */
00088 typedef enum
00089 {
00090   HAL_SWPMI_STATE_RESET             = 0x00,    /*!< Peripheral Reset state                             */
00091   HAL_SWPMI_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */
00092   HAL_SWPMI_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */
00093   HAL_SWPMI_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */
00094   HAL_SWPMI_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */
00095   HAL_SWPMI_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
00096   HAL_SWPMI_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */
00097   HAL_SWPMI_STATE_ERROR             = 0x04     /*!< Error                                              */
00098 }HAL_SWPMI_StateTypeDef;
00099
00100 /**
00101   * @brief  SWPMI handle Structure definition
00102   */
00103 typedef struct
00104 {
00105   SWPMI_TypeDef                  *Instance;     /* SWPMI registers base address         */
00106
00107   SWPMI_InitTypeDef              Init;          /* SWMPI communication parameters       */
00108
00109   uint32_t                       *pTxBuffPtr;   /* Pointer to SWPMI Tx transfer Buffer  */
00110
00111   uint32_t                       TxXferSize;    /* SWPMI Tx Transfer size               */
00112
00113   uint32_t                       TxXferCount;   /* SWPMI Tx Transfer Counter            */
00114
00115   uint32_t                       *pRxBuffPtr;   /* Pointer to SWPMI Rx transfer Buffer  */
00116
00117   uint32_t                       RxXferSize;    /* SWPMI Rx Transfer size               */
00118
00119   uint32_t                       RxXferCount;   /* SWPMI Rx Transfer Counter            */
00120
00121   DMA_HandleTypeDef              *hdmatx;       /* SWPMI Tx DMA Handle parameters       */
00122
00123   DMA_HandleTypeDef              *hdmarx;       /* SWPMI Rx DMA Handle parameters       */
00124
00125   HAL_LockTypeDef                Lock;          /* SWPMI object                         */
00126
00127   __IO HAL_SWPMI_StateTypeDef    State;         /* SWPMI communication state            */
00128
00129   __IO uint32_t                  ErrorCode;     /* SWPMI Error code                     */
00130
00131 }SWPMI_HandleTypeDef;
00132
00133 /**
00134   * @}
00135   */
00136
00137 /* Exported constants --------------------------------------------------------*/
00138 /** @defgroup SWPMI_Exported_Constants SWPMI Exported Constants
00139   * @{
00140   */
00141
00142 /**
00143   * @defgroup SWPMI_Error_Code SWPMI Error Code Bitmap
00144   * @{
00145   */
00146 #define HAL_SWPMI_ERROR_NONE                 ((uint32_t)0x00000000) /*!< No error             */
00147 #define HAL_SWPMI_ERROR_CRC                  ((uint32_t)0x00000004) /*!< frame error          */
00148 #define HAL_SWPMI_ERROR_OVR                  ((uint32_t)0x00000008) /*!< Overrun error        */
00149 #define HAL_SWPMI_ERROR_UDR                  ((uint32_t)0x0000000C) /*!< Underrun error       */
00150 #define HAL_SWPMI_ERROR_DMA                  ((uint32_t)0x00000010) /*!< DMA transfer error   */
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup SWPMI_Voltage_Class SWPMI Voltage Class
00156   * @{
00157   */
00158 #define SWPMI_VOLTAGE_CLASS_C                ((uint32_t)0x00000000)
00159 #define SWPMI_VOLTAGE_CLASS_B                SWPMI_OR_CLASS
00160 /**
00161   * @}
00162   */
00163
00164 /** @defgroup SWPMI_Tx_Buffering_Mode SWPMI Tx Buffering Mode
00165   * @{
00166   */
00167 #define SWPMI_TX_NO_SOFTWAREBUFFER           ((uint32_t)0x00000000)
00168 #define SWPMI_TX_SINGLE_SOFTWAREBUFFER       ((uint32_t)0x00000000)
00169 #define SWPMI_TX_MULTI_SOFTWAREBUFFER        SWPMI_CR_TXMODE
00170 /**
00171   * @}
00172   */
00173
00174 /** @defgroup SWPMI_Rx_Buffering_Mode SWPMI Rx Buffering Mode
00175   * @{
00176   */
00177 #define SWPMI_RX_NO_SOFTWAREBUFFER           ((uint32_t)0x00000000)
00178 #define SWPMI_RX_SINGLE_SOFTWAREBUFFER       ((uint32_t)0x00000000)
00179 #define SWPMI_RX_MULTI_SOFTWAREBUFFER        SWPMI_CR_RXMODE
00180 /**
00181   * @}
00182   */
00183
00184 /** @defgroup SWPMI_Flags SWPMI Status Flags
00185   *        Elements values convention: 0xXXXXXXXX
00186   *           - 0xXXXXXXXX  : Flag mask in the ISR register
00187   * @{
00188   */
00189 #define SWPMI_FLAG_RXBFF                 SWPMI_ISR_RXBFF
00190 #define SWPMI_FLAG_TXBEF                 SWPMI_ISR_TXBEF
00191 #define SWPMI_FLAG_RXBERF                SWPMI_ISR_RXBERF
00192 #define SWPMI_FLAG_RXOVRF                SWPMI_ISR_RXOVRF
00193 #define SWPMI_FLAG_TXUNRF                SWPMI_ISR_TXUNRF
00194 #define SWPMI_FLAG_RXNE                  SWPMI_ISR_RXNE
00195 #define SWPMI_FLAG_TXE                   SWPMI_ISR_TXE
00196 #define SWPMI_FLAG_TCF                   SWPMI_ISR_TCF
00197 #define SWPMI_FLAG_SRF                   SWPMI_ISR_SRF
00198 #define SWPMI_FLAG_SUSP                  SWPMI_ISR_SUSP
00199 #define SWPMI_FLAG_DEACTF                SWPMI_ISR_DEACTF
00200 #define SWPMI_FLAG_RDYF                  SWPMI_ISR_RDYF
00201 /**
00202   * @}
00203   */
00204
00205 /** @defgroup SWPMI_Interrupt_definition SWPMI Interrupts Definition
00206   *        Elements values convention: 0xXXXX
00207   *           - 0xXXXX  : Flag mask in the IER register
00208   * @{
00209   */
00210 #define SWPMI_IT_RDYIE                   SWPMI_IER_RDYIE
00211 #define SWPMI_IT_SRIE                    SWPMI_IER_SRIE
00212 #define SWPMI_IT_TCIE                    SWPMI_IER_TCIE
00213 #define SWPMI_IT_TIE                     SWPMI_IER_TIE
00214 #define SWPMI_IT_RIE                     SWPMI_IER_RIE
00215 #define SWPMI_IT_TXUNRIE                 SWPMI_IER_TXUNRIE
00216 #define SWPMI_IT_RXOVRIE                 SWPMI_IER_RXOVRIE
00217 #define SWPMI_IT_RXBERIE                 SWPMI_IER_RXBERIE
00218 #define SWPMI_IT_TXBEIE                  SWPMI_IER_TXBEIE
00219 #define SWPMI_IT_RXBFIE                  SWPMI_IER_RXBFIE
00220 /**
00221   * @}
00222   */
00223
00224 /**
00225   * @}
00226   */
00227
00228 /* Exported macros -----------------------------------------------------------*/
00229 /** @defgroup SWPMI_Exported_Macros SWPMI Exported Macros
00230   * @{
00231   */
00232
00233 /** @brief Reset SWPMI handle state.
00234   * @param  __HANDLE__: specifies the SWPMI Handle.
00235   * @retval None
00236   */
00237 #define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET)
00238
00239 /**
00240   * @brief  Enable the SWPMI peripheral.
00241   * @param  __HANDLE__: SWPMI handle
00242   * @retval None
00243   */
00244 #define __HAL_SWPMI_ENABLE(__HANDLE__)   SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
00245
00246 /**
00247   * @brief  Disable the SWPMI peripheral.
00248   * @param  __HANDLE__: SWPMI handle
00249   * @retval None
00250   */
00251 #define __HAL_SWPMI_DISABLE(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
00252
00253 /**
00254   * @brief  Enable/Disable the SWPMI transceiver.
00255   * @param  __HANDLE__: SWPMI handle
00256   * @retval None
00257   */
00258 #define __HAL_SWPMI_TRANSCEIVER_ENABLE(__HANDLE__)   SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)
00259 #define __HAL_SWPMI_TRANSCEIVER_DISABLE(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)
00260
00261 /** @brief  Check whether the specified SWPMI flag is set or not.
00262   * @param  __HANDLE__: specifies the SWPMI Handle.
00263   * @param  __FLAG__: specifies the flag to check.
00264   *        This parameter can be one of the following values:
00265   *            @arg SWPMI_FLAG_RXBFF : Receive buffer full flag.
00266   *            @arg SWPMI_FLAG_TXBEF : Transmit buffer empty flag.
00267   *            @arg SWPMI_FLAG_RXBERF : Receive CRC error flag.
00268   *            @arg SWPMI_FLAG_RXOVRF : Receive overrun error flag.
00269   *            @arg SWPMI_FLAG_TXUNRF : Transmit underrun error flag.
00270   *            @arg SWPMI_FLAG_RXNE : Receive data register not empty.
00271   *            @arg SWPMI_FLAG_TXE : Transmit data register empty.
00272   *            @arg SWPMI_FLAG_TCF : Transfer complete flag.
00273   *            @arg SWPMI_FLAG_SRF : Slave resume flag.
00274   *            @arg SWPMI_FLAG_SUSP : SUSPEND flag.
00275   *            @arg SWPMI_FLAG_DEACTF : DEACTIVATED flag.
00276   * @retval The new state of __FLAG__ (TRUE or FALSE).
00277   */
00278 #define __HAL_SWPMI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__))
00279
00280 /** @brief  Clear the specified SWPMI ISR flag.
00281   * @param  __HANDLE__: specifies the SWPMI Handle.
00282   * @param  __FLAG__: specifies the flag to clear.
00283   *        This parameter can be one of the following values:
00284   *            @arg SWPMI_FLAG_RXBFF : Receive buffer full flag.
00285   *            @arg SWPMI_FLAG_TXBEF : Transmit buffer empty flag.
00286   *            @arg SWPMI_FLAG_RXBERF : Receive CRC error flag.
00287   *            @arg SWPMI_FLAG_RXOVRF : Receive overrun error flag.
00288   *            @arg SWPMI_FLAG_TXUNRF : Transmit underrun error flag.
00289   *            @arg SWPMI_FLAG_TCF : Transfer complete flag.
00290   *            @arg SWPMI_FLAG_SRF : Slave resume flag.
00291   *            @arg SWPMI_FLAG_RDYF: Transceiver ready flag
00292   * @retval None
00293   */
00294 #define __HAL_SWPMI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__))
00295
00296 /** @brief  Enable the specified SWPMI interrupt.
00297   * @param  __HANDLE__: specifies the SWPMI Handle.
00298   * @param  __INTERRUPT__: specifies the SWPMI interrupt source to enable.
00299   *          This parameter can be one of the following values:
00300   *            @arg SWPMI_IT_SRIE : Slave resume interrupt.
00301   *            @arg SWPMI_IT_TCIE : Transmit complete interrupt.
00302   *            @arg SWPMI_IT_TIE :  Transmit interrupt.
00303   *            @arg SWPMI_IT_RIE :  Receive interrupt.
00304   *            @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
00305   *            @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
00306   *            @arg SWPMI_IT_RXBEIE : Receive CRC error interrupt.
00307   *            @arg SWPMI_IT_TXBEIE :  Transmit buffer empty interrupt.
00308   *            @arg SWPMI_IT_RXBFIE :  Receive buffer full interrupt.
00309   * @retval None
00310   */
00311 #define __HAL_SWPMI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
00312
00313 /** @brief  Disable the specified SWPMI interrupt.
00314   * @param  __HANDLE__: specifies the SWPMI Handle.
00315   * @param  __INTERRUPT__: specifies the SWPMI interrupt source to disable.
00316   *          This parameter can be one of the following values:
00317   *            @arg SWPMI_IT_SRIE : Slave resume interrupt.
00318   *            @arg SWPMI_IT_TCIE : Transmit complete interrupt.
00319   *            @arg SWPMI_IT_TIE :  Transmit interrupt.
00320   *            @arg SWPMI_IT_RIE :  Receive interrupt.
00321   *            @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
00322   *            @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
00323   *            @arg SWPMI_IT_RXBEIE : Receive CRC error interrupt.
00324   *            @arg SWPMI_IT_TXBEIE :  Transmit buffer empty interrupt.
00325   *            @arg SWPMI_IT_RXBFIE :  Receive buffer full interrupt.
00326   * @retval None
00327   */
00328 #define __HAL_SWPMI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
00329
00330 /** @brief  Check whether the specified SWPMI interrupt has occurred or not.
00331   * @param  __HANDLE__: specifies the SWPMI Handle.
00332   * @param  __IT__: specifies the SWPMI interrupt to check.
00333   *          This parameter can be one of the following values:
00334   *            @arg SWPMI_IT_SRIE : Slave resume interrupt.
00335   *            @arg SWPMI_IT_TCIE : Transmit complete interrupt.
00336   *            @arg SWPMI_IT_TIE :  Transmit interrupt.
00337   *            @arg SWPMI_IT_RIE :  Receive interrupt.
00338   *            @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
00339   *            @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
00340   *            @arg SWPMI_IT_RXBERIE : Receive CRC error interrupt.
00341   *            @arg SWPMI_IT_TXBEIE :  Transmit buffer empty interrupt.
00342   *            @arg SWPMI_IT_RXBFIE :  Receive buffer full interrupt.
00343   * @retval The new state of __IT__ (TRUE or FALSE).
00344   */
00345 #define __HAL_SWPMI_GET_IT(__HANDLE__, __IT__)  (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__))
00346
00347 /** @brief  Check whether the specified SWPMI interrupt source is enabled or not.
00348   * @param  __HANDLE__: specifies the SWPMI Handle.
00349   * @param  __IT__: specifies the SWPMI interrupt source to check.
00350   *          This parameter can be one of the following values:
00351   *            @arg SWPMI_IT_SRIE : Slave resume interrupt.
00352   *            @arg SWPMI_IT_TCIE : Transmit complete interrupt.
00353   *            @arg SWPMI_IT_TIE :  Transmit interrupt.
00354   *            @arg SWPMI_IT_RIE :  Receive interrupt.
00355   *            @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
00356   *            @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
00357   *            @arg SWPMI_IT_RXBERIE : Receive CRC error interrupt.
00358   *            @arg SWPMI_IT_TXBEIE :  Transmit buffer empty interrupt.
00359   *            @arg SWPMI_IT_RXBFIE :  Receive buffer full interrupt.
00360   * @retval The new state of __IT__ (TRUE or FALSE).
00361   */
00362 #define __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET)
00363
00364 /**
00365   * @}
00366   */
00367
00368 /* Exported functions --------------------------------------------------------*/
00369 /** @defgroup SWPMI_Exported_Functions SWPMI Exported Functions
00370   * @{
00371   */
00372 /* Initialization/de-initialization functions  ********************************/
00373 HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi);
00374 HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi);
00375 void              HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi);
00376 void              HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi);
00377
00378 /* IO operation functions *****************************************************/
00379 HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout);
00380 HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout);
00381 HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
00382 HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
00383 HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
00384 HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
00385 HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi);
00386 HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi);
00387 HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi);
00388 void              HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi);
00389 void              HAL_SWPMI_TxCpltCallback(SWPMI_HandleTypeDef *hswpmi);
00390 void              HAL_SWPMI_TxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi);
00391 void              HAL_SWPMI_RxCpltCallback(SWPMI_HandleTypeDef *hswpmi);
00392 void              HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi);
00393 void              HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi);
00394
00395 /* Peripheral Control and State functions  ************************************/
00396 HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi);
00397 uint32_t               HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi);
00398
00399 /**
00400   * @}
00401   */
00402
00403 /* Private types -------------------------------------------------------------*/
00404 /** @defgroup SWPMI_Private_Types SWPMI Private Types
00405   * @{
00406   */
00407
00408 /**
00409   * @}
00410   */
00411
00412 /* Private variables ---------------------------------------------------------*/
00413 /** @defgroup SWPMI_Private_Variables SWPMI Private Variables
00414   * @{
00415   */
00416
00417 /**
00418   * @}
00419   */
00420
00421 /* Private constants ---------------------------------------------------------*/
00422 /** @defgroup SWPMI_Private_Constants SWPMI Private Constants
00423   * @{
00424   */
00425
00426 /**
00427   * @}
00428   */
00429
00430 /* Private macros ------------------------------------------------------------*/
00431 /** @defgroup SWPMI_Private_Macros SWPMI Private Macros
00432   * @{
00433   */
00434
00435
00436 #define IS_SWPMI_VOLTAGE_CLASS(__CLASS__)    (((__CLASS__) == SWPMI_VOLTAGE_CLASS_C) || \
00437                                               ((__CLASS__) == SWPMI_VOLTAGE_CLASS_B))
00438
00439 #define IS_SWPMI_BITRATE_VALUE(__VALUE__)    (((__VALUE__) <= 63))
00440
00441
00442 #define IS_SWPMI_TX_BUFFERING_MODE(__MODE__) (((__MODE__) == SWPMI_TX_NO_SOFTWAREBUFFER) || \
00443                                               ((__MODE__) == SWPMI_TX_MULTI_SOFTWAREBUFFER))
00444
00445
00446 #define IS_SWPMI_RX_BUFFERING_MODE(__MODE__) (((__MODE__) == SWPMI_RX_NO_SOFTWAREBUFFER) || \
00447                                               ((__MODE__) == SWPMI_RX_MULTI_SOFTWAREBUFFER))
00448
00449 /**
00450   * @}
00451   */
00452
00453 /**
00454   * @}
00455   */
00456
00457 /**
00458   * @}
00459   */
00460
00461 #ifdef __cplusplus
00462 }
00463 #endif
00464
00465 #endif /* __STM32H7xx_HAL_SWPMI_H */
00466
00467 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_tim.c Source File

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stm32h7xx_hal_tim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_tim.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   TIM HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Timer (TIM) peripheral:
00010   *           + Time Base Initialization
00011   *           + Time Base Start
00012   *           + Time Base Start Interruption
00013   *           + Time Base Start DMA
00014   *           + Time Output Compare/PWM Initialization
00015   *           + Time Output Compare/PWM Channel Configuration
00016   *           + Time Output Compare/PWM  Start
00017   *           + Time Output Compare/PWM  Start Interruption
00018   *           + Time Output Compare/PWM Start DMA
00019   *           + Time Input Capture Initialization
00020   *           + Time Input Capture Channel Configuration
00021   *           + Time Input Capture Start
00022   *           + Time Input Capture Start Interruption
00023   *           + Time Input Capture Start DMA
00024   *           + Time One Pulse Initialization
00025   *           + Time One Pulse Channel Configuration
00026   *           + Time One Pulse Start
00027   *           + Time Encoder Interface Initialization
00028   *           + Time Encoder Interface Start
00029   *           + Time Encoder Interface Start Interruption
00030   *           + Time Encoder Interface Start DMA
00031   *           + Commutation Event configuration with Interruption and DMA
00032   *           + Time OCRef clear configuration
00033   *           + Time External Clock configuration
00034   @verbatim
00035   ==============================================================================
00036                       ##### TIM Generic features #####
00037   ==============================================================================
00038   [..] The Timer features include:
00039        (#) 16-bit (32-bit for TIM2/TIM5) up, down, up/down auto-reload counter.
00040        (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
00041            counter clock frequency either by any factor between 1 and 65536.
00042        (#) Up to 4 independent channels for:
00043            (++) Input Capture
00044            (++) Output Compare
00045            (++) PWM generation (Edge and Center-aligned Mode)
00046            (++) One-pulse mode output
00047
00048             ##### How to use this driver #####
00049   ==============================================================================
00050     [..]
00051      (#) Initialize the TIM low level resources by implementing the following functions
00052          depending on the selected feature:
00053            (++) Time Base : HAL_TIM_Base_MspInit()
00054            (++) Input Capture : HAL_TIM_IC_MspInit()
00055            (++) Output Compare : HAL_TIM_OC_MspInit()
00056            (++) PWM generation : HAL_TIM_PWM_MspInit()
00057            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
00058            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
00059
00060      (#) Initialize the TIM low level resources :
00061         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
00062         (##) TIM pins configuration
00063             (+++) Enable the clock for the TIM GPIOs using the following function:
00064              __HAL_RCC_GPIOx_CLK_ENABLE();
00065             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00066
00067      (#) The external Clock can be configured, if needed (the default clock is the
00068          internal clock from the APBx), using the following function:
00069          HAL_TIM_ConfigClockSource, the clock configuration should be done before
00070          any start function.
00071      (#) Configure the TIM in the desired functioning mode using one of the
00072        Initialization function of this driver:
00073        (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base.
00074        (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
00075             Output Compare signal.
00076        (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
00077             PWM signal.
00078        (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
00079             external signal.
00080        (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
00081               in One Pulse Mode.
00082        (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
00083      (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
00084            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT().
00085            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT().
00086            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT().
00087            (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT().
00088            (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT().
00089            (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
00090      (#) The DMA Burst is managed with the two following functions:
00091            (++)HAL_TIM_DMABurst_WriteStart().
00092            (++)HAL_TIM_DMABurst_ReadStart().
00093   @endverbatim
00094   ******************************************************************************
00095   * @attention
00096   *
00097   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00098   *
00099   * Redistribution and use in source and binary forms, with or without modification,
00100   * are permitted provided that the following conditions are met:
00101   *   1. Redistributions of source code must retain the above copyright notice,
00102   *      this list of conditions and the following disclaimer.
00103   *   2. Redistributions in binary form must reproduce the above copyright notice,
00104   *      this list of conditions and the following disclaimer in the documentation
00105   *      and/or other materials provided with the distribution.
00106   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00107   *      may be used to endorse or promote products derived from this software
00108   *      without specific prior written permission.
00109   *
00110   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00111   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00112   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00113   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00114   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00115   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00116   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00117   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00118   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00119   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00120   *
00121   ******************************************************************************
00122   */
00123
00124 /* Includes ------------------------------------------------------------------*/
00125 #include "stm32h7xx_hal.h"
00126
00127 /** @addtogroup STM32H7xx_HAL_Driver
00128   * @{
00129   */
00130
00131 /** @defgroup TIM TIM
00132   * @brief TIM HAL module driver
00133   * @{
00134   */
00135
00136 #ifdef HAL_TIM_MODULE_ENABLED
00137
00138 /* Private typedef -----------------------------------------------------------*/
00139 /* Private define ------------------------------------------------------------*/
00140 /* Private macro -------------------------------------------------------------*/
00141 /* Private variables ---------------------------------------------------------*/
00142 /* Private function prototypes -----------------------------------------------*/
00143 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00144 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00145 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00146 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00147                        uint32_t TIM_ICFilter);
00148 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00149 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00150                        uint32_t TIM_ICFilter);
00151 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00152                        uint32_t TIM_ICFilter);
00153 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
00154 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
00155 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
00156 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
00157                                      TIM_SlaveConfigTypeDef * sSlaveConfig);
00158
00159 /* Exported functions --------------------------------------------------------*/
00160
00161 /** @defgroup TIM_Exported_Functions TIM Exported Functions
00162   * @{
00163   */
00164
00165 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
00166  *  @brief    TIM Time Base functions
00167  *
00168 @verbatim
00169   ==============================================================================
00170               ##### TIM Time Base functions #####
00171   ==============================================================================
00172   [..]
00173     This section provides functions allowing to:
00174     (+) Initialize and configure the TIM Time base.
00175     (+) De-initialize the TIM Time base.
00176     (+) Start the TIM Time Base.
00177     (+) Stop the TIM Time Base.
00178     (+) Start the TIM Time Base and enable interrupt.
00179     (+) Stop the TIM Time Base and disable interrupt.
00180     (+) Start the TIM Time Base and enable DMA transfer.
00181     (+) Stop the TIM Time Base and disable DMA transfer.
00182
00183 @endverbatim
00184   * @{
00185   */
00186 /**
00187   * @brief  Initialize the TIM Time base Unit according to the specified
00188   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
00189   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00190   *                the configuration information for TIM module.
00191   * @retval HAL status
00192   */
00193 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
00194 {
00195   /* Check the TIM handle allocation */
00196   if(htim == NULL)
00197   {
00198     return HAL_ERROR;
00199   }
00200
00201   /* Check the parameters */
00202   assert_param(IS_TIM_INSTANCE(htim->Instance));
00203   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00204   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00205
00206   if(htim->State == HAL_TIM_STATE_RESET)
00207   {
00208     /* Allocate lock resource and initialize it */
00209     htim->Lock = HAL_UNLOCKED;
00210     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00211     HAL_TIM_Base_MspInit(htim);
00212   }
00213
00214   /* Set the TIM state */
00215   htim->State= HAL_TIM_STATE_BUSY;
00216
00217   /* Set the Time Base configuration */
00218   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00219
00220   /* Initialize the TIM state*/
00221   htim->State= HAL_TIM_STATE_READY;
00222
00223   return HAL_OK;
00224 }
00225
00226 /**
00227   * @brief  DeInitialize the TIM Base peripheral
00228   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00229   *                the configuration information for TIM module.
00230   * @retval HAL status
00231   */
00232 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
00233 {
00234   /* Check the parameters */
00235   assert_param(IS_TIM_INSTANCE(htim->Instance));
00236
00237   htim->State = HAL_TIM_STATE_BUSY;
00238
00239   /* Disable the TIM Peripheral Clock */
00240   __HAL_TIM_DISABLE(htim);
00241
00242   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00243   HAL_TIM_Base_MspDeInit(htim);
00244
00245   /* Change TIM state */
00246   htim->State = HAL_TIM_STATE_RESET;
00247
00248   /* Release Lock */
00249   __HAL_UNLOCK(htim);
00250
00251   return HAL_OK;
00252 }
00253
00254 /**
00255   * @brief  Initialize the TIM Time Base MSP.
00256   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00257   *                the configuration information for TIM module.
00258   * @retval None
00259   */
00260 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
00261 {
00262   /* Prevent unused argument(s) compilation warning */
00263   UNUSED(htim);
00264   /* NOTE : This function Should not be modified, when the callback is needed,
00265             the HAL_TIM_Base_MspDeInit could be implemented in the user file
00266    */
00267 }
00268
00269 /**
00270   * @brief  DeInitialize TIM Time Base MSP.
00271   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00272   *                the configuration information for TIM module.
00273   * @retval None
00274   */
00275 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
00276 {
00277   /* Prevent unused argument(s) compilation warning */
00278   UNUSED(htim);
00279   /* NOTE : This function Should not be modified, when the callback is needed,
00280             the HAL_TIM_Base_MspDeInit could be implemented in the user file
00281    */
00282 }
00283
00284
00285 /**
00286   * @brief  Starts the TIM Time Base generation.
00287   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00288   *                the configuration information for TIM module.
00289   * @retval HAL status
00290 */
00291 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
00292 {
00293   /* Check the parameters */
00294   assert_param(IS_TIM_INSTANCE(htim->Instance));
00295
00296   /* Set the TIM state */
00297   htim->State= HAL_TIM_STATE_BUSY;
00298
00299   /* Enable the Peripheral */
00300   __HAL_TIM_ENABLE(htim);
00301
00302   /* Change the TIM state*/
00303   htim->State= HAL_TIM_STATE_READY;
00304
00305   /* Return function status */
00306   return HAL_OK;
00307 }
00308
00309 /**
00310   * @brief  Stops the TIM Time Base generation.
00311   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00312   *                the configuration information for TIM module.
00313   * @retval HAL status
00314 */
00315 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
00316 {
00317   /* Check the parameters */
00318   assert_param(IS_TIM_INSTANCE(htim->Instance));
00319
00320   /* Set the TIM state */
00321   htim->State= HAL_TIM_STATE_BUSY;
00322
00323   /* Disable the Peripheral */
00324   __HAL_TIM_DISABLE(htim);
00325
00326   /* Change the TIM state*/
00327   htim->State= HAL_TIM_STATE_READY;
00328
00329   /* Return function status */
00330   return HAL_OK;
00331 }
00332
00333 /**
00334   * @brief  Starts the TIM Time Base generation in interrupt mode.
00335   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00336   *                the configuration information for TIM module.
00337   * @retval HAL status
00338 */
00339 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
00340 {
00341   /* Check the parameters */
00342   assert_param(IS_TIM_INSTANCE(htim->Instance));
00343
00344    /* Enable the TIM Update interrupt */
00345    __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
00346
00347    /* Enable the Peripheral */
00348   __HAL_TIM_ENABLE(htim);
00349
00350   /* Return function status */
00351   return HAL_OK;
00352 }
00353
00354 /**
00355   * @brief  Stops the TIM Time Base generation in interrupt mode.
00356   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00357   *                the configuration information for TIM module.
00358   * @retval HAL status
00359 */
00360 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
00361 {
00362   /* Check the parameters */
00363   assert_param(IS_TIM_INSTANCE(htim->Instance));
00364   /* Disable the TIM Update interrupt */
00365   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
00366
00367   /* Disable the Peripheral */
00368   __HAL_TIM_DISABLE(htim);
00369
00370   /* Return function status */
00371   return HAL_OK;
00372 }
00373
00374 /**
00375   * @brief  Starts the TIM Time Base generation in DMA mode.
00376   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00377   *                the configuration information for TIM module.
00378   * @param  pData: The source Buffer address.
00379   * @param  Length: The length of data to be transferred from memory to peripheral.
00380   * @retval HAL status
00381 */
00382 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
00383 {
00384   /* Check the parameters */
00385   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00386
00387   if(htim->State == HAL_TIM_STATE_BUSY)
00388   {
00389      return HAL_BUSY;
00390   }
00391   else if(htim->State == HAL_TIM_STATE_READY)
00392   {
00393     if((pData == 0 ) && (Length > 0))
00394     {
00395       return HAL_ERROR;
00396     }
00397     else
00398     {
00399       htim->State = HAL_TIM_STATE_BUSY;
00400     }
00401   }
00402   /* Set the DMA Period elapsed callback */
00403   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
00404
00405   /* Set the DMA error callback */
00406   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
00407
00408   /* Enable t  he DMA Stream */
00409   HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
00410
00411   /* Enable the TIM Update DMA request */
00412   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
00413
00414   /* Enable the Peripheral */
00415   __HAL_TIM_ENABLE(htim);
00416
00417   /* Return function status */
00418   return HAL_OK;
00419 }
00420
00421 /**
00422   * @brief  Stops the TIM Time Base generation in DMA mode.
00423   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00424   *                the configuration information for TIM module.
00425   * @retval HAL status
00426 */
00427 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
00428 {
00429   /* Check the parameters */
00430   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00431
00432   /* Disable the TIM Update DMA request */
00433   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
00434
00435   /* Disable the Peripheral */
00436   __HAL_TIM_DISABLE(htim);
00437
00438   /* Change the htim state */
00439   htim->State = HAL_TIM_STATE_READY;
00440
00441   /* Return function status */
00442   return HAL_OK;
00443 }
00444
00445 /**
00446   * @}
00447   */
00448
00449 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
00450  *  @brief    Time Output Compare functions
00451  *
00452 @verbatim
00453   ==============================================================================
00454                   ##### TIM Output Compare functions #####
00455   ==============================================================================
00456   [..]
00457     This section provides functions allowing to:
00458     (+) Initialize and configure the TIM Output Compare.
00459     (+) De-initialize the TIM Output Compare.
00460     (+) Start the TIM Output Compare.
00461     (+) Stop the TIM Output Compare.
00462     (+) Start the TIM Output Compare and enable interrupt.
00463     (+) Stop the TIM Output Compare and disable interrupt.
00464     (+) Start the TIM Output Compare and enable DMA transfer.
00465     (+) Stop the TIM Output Compare and disable DMA transfer.
00466
00467 @endverbatim
00468   * @{
00469   */
00470 /**
00471   * @brief  Initialize the TIM Output Compare according to the specified
00472   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
00473   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00474   *                the configuration information for TIM module.
00475   * @retval HAL status
00476   */
00477 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
00478 {
00479   /* Check the TIM handle allocation */
00480   if(htim == NULL)
00481   {
00482     return HAL_ERROR;
00483   }
00484
00485   /* Check the parameters */
00486   assert_param(IS_TIM_INSTANCE(htim->Instance));
00487   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00488   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00489
00490   if(htim->State == HAL_TIM_STATE_RESET)
00491   {
00492     /* Allocate lock resource and initialize it */
00493     htim->Lock = HAL_UNLOCKED;
00494
00495     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00496     HAL_TIM_OC_MspInit(htim);
00497   }
00498
00499   /* Set the TIM state */
00500   htim->State= HAL_TIM_STATE_BUSY;
00501
00502   /* Init the base time for the Output Compare */
00503   TIM_Base_SetConfig(htim->Instance,  &htim->Init);
00504
00505   /* Initialize the TIM state*/
00506   htim->State= HAL_TIM_STATE_READY;
00507
00508   return HAL_OK;
00509 }
00510
00511 /**
00512   * @brief  DeInitialize the TIM peripheral
00513   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00514   *                the configuration information for TIM module.
00515   * @retval HAL status
00516   */
00517 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
00518 {
00519   /* Check the parameters */
00520   assert_param(IS_TIM_INSTANCE(htim->Instance));
00521
00522    htim->State = HAL_TIM_STATE_BUSY;
00523
00524   /* Disable the TIM Peripheral Clock */
00525   __HAL_TIM_DISABLE(htim);
00526
00527   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
00528   HAL_TIM_OC_MspDeInit(htim);
00529
00530   /* Change TIM state */
00531   htim->State = HAL_TIM_STATE_RESET;
00532
00533   /* Release Lock */
00534   __HAL_UNLOCK(htim);
00535
00536   return HAL_OK;
00537 }
00538
00539 /**
00540   * @brief  Initialize the TIM Output Compare MSP.
00541   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00542   *                the configuration information for TIM module.
00543   * @retval None
00544   */
00545 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
00546 {
00547   /* Prevent unused argument(s) compilation warning */
00548   UNUSED(htim);
00549
00550   /* NOTE : This function Should not be modified, when the callback is needed,
00551             the HAL_TIM_OC_MspInit could be implemented in the user file
00552    */
00553 }
00554
00555 /**
00556   * @brief  DeInitialize TIM Output Compare MSP.
00557   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00558   *                the configuration information for TIM module.
00559   * @retval None
00560   */
00561 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
00562 {
00563   /* Prevent unused argument(s) compilation warning */
00564   UNUSED(htim);
00565
00566   /* NOTE : This function Should not be modified, when the callback is needed,
00567             the HAL_TIM_OC_MspDeInit could be implemented in the user file
00568    */
00569 }
00570
00571 /**
00572   * @brief  Starts the TIM Output Compare signal generation.
00573   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00574   *                the configuration information for TIM module.
00575   * @param  Channel : TIM Channel to be enabled.
00576   *          This parameter can be one of the following values:
00577   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00578   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00579   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00580   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00581   * @retval HAL status
00582 */
00583 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00584 {
00585   /* Check the parameters */
00586   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00587
00588   /* Enable the Output compare channel */
00589   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00590
00591   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00592   {
00593     /* Enable the main output */
00594     __HAL_TIM_MOE_ENABLE(htim);
00595   }
00596
00597   /* Enable the Peripheral */
00598   __HAL_TIM_ENABLE(htim);
00599
00600   /* Return function status */
00601   return HAL_OK;
00602 }
00603
00604 /**
00605   * @brief  Stops the TIM Output Compare signal generation.
00606   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00607   *                the configuration information for TIM module.
00608   * @param  Channel : TIM Channel to be disabled.
00609   *          This parameter can be one of the following values:
00610   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00611   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00612   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00613   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00614   * @retval HAL status
00615 */
00616 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00617 {
00618   /* Check the parameters */
00619   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00620
00621   /* Disable the Output compare channel */
00622   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00623
00624   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00625   {
00626     /* Disable the Main Output */
00627     __HAL_TIM_MOE_DISABLE(htim);
00628   }
00629
00630   /* Disable the Peripheral */
00631   __HAL_TIM_DISABLE(htim);
00632
00633   /* Return function status */
00634   return HAL_OK;
00635 }
00636
00637 /**
00638   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
00639   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00640   *                the configuration information for TIM module.
00641   * @param  Channel : TIM Channel to be enabled.
00642   *          This parameter can be one of the following values:
00643   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00644   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00645   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00646   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00647   * @retval HAL status
00648 */
00649 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00650 {
00651   /* Check the parameters */
00652   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00653
00654   switch (Channel)
00655   {
00656     case TIM_CHANNEL_1:
00657     {
00658       /* Enable the TIM Capture/Compare 1 interrupt */
00659       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00660     }
00661     break;
00662
00663     case TIM_CHANNEL_2:
00664     {
00665       /* Enable the TIM Capture/Compare 2 interrupt */
00666       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00667     }
00668     break;
00669
00670     case TIM_CHANNEL_3:
00671     {
00672       /* Enable the TIM Capture/Compare 3 interrupt */
00673       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00674     }
00675     break;
00676
00677     case TIM_CHANNEL_4:
00678     {
00679       /* Enable the TIM Capture/Compare 4 interrupt */
00680       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
00681     }
00682     break;
00683
00684     default:
00685     break;
00686   }
00687
00688   /* Enable the Output compare channel */
00689   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00690
00691   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00692   {
00693     /* Enable the main output */
00694     __HAL_TIM_MOE_ENABLE(htim);
00695   }
00696
00697   /* Enable the Peripheral */
00698   __HAL_TIM_ENABLE(htim);
00699
00700   /* Return function status */
00701   return HAL_OK;
00702 }
00703
00704 /**
00705   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
00706   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00707   *                the configuration information for TIM module.
00708   * @param  Channel : TIM Channel to be disabled.
00709   *          This parameter can be one of the following values:
00710   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00711   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00712   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00713   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00714   * @retval HAL status
00715 */
00716 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00717 {
00718   /* Check the parameters */
00719   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00720
00721   switch (Channel)
00722   {
00723     case TIM_CHANNEL_1:
00724     {
00725       /* Disable the TIM Capture/Compare 1 interrupt */
00726       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00727     }
00728     break;
00729
00730     case TIM_CHANNEL_2:
00731     {
00732       /* Disable the TIM Capture/Compare 2 interrupt */
00733       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
00734     }
00735     break;
00736
00737     case TIM_CHANNEL_3:
00738     {
00739       /* Disable the TIM Capture/Compare 3 interrupt */
00740       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
00741     }
00742     break;
00743
00744     case TIM_CHANNEL_4:
00745     {
00746       /* Disable the TIM Capture/Compare 4 interrupt */
00747       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
00748     }
00749     break;
00750
00751     default:
00752     break;
00753   }
00754
00755   /* Disable the Output compare channel */
00756   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00757
00758   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00759   {
00760     /* Disable the Main Output */
00761     __HAL_TIM_MOE_DISABLE(htim);
00762   }
00763
00764   /* Disable the Peripheral */
00765   __HAL_TIM_DISABLE(htim);
00766
00767   /* Return function status */
00768   return HAL_OK;
00769 }
00770
00771 /**
00772   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
00773   * @param  htim : TIM Output Compare handle
00774   * @param  Channel : TIM Channel to be enabled.
00775   *          This parameter can be one of the following values:
00776   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00777   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00778   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00779   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00780   * @param  pData: The source Buffer address.
00781   * @param  Length: The length of data to be transferred from memory to TIM peripheral
00782   * @retval HAL status
00783 */
00784 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
00785 {
00786   /* Check the parameters */
00787   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00788
00789   if(htim->State == HAL_TIM_STATE_BUSY)
00790   {
00791      return HAL_BUSY;
00792   }
00793   else if((htim->State) == (HAL_TIM_STATE_READY))
00794   {
00795     if(((uint32_t)pData == 0 ) && (Length > 0))
00796     {
00797       return HAL_ERROR;
00798     }
00799     else
00800     {
00801       htim->State = HAL_TIM_STATE_BUSY;
00802     }
00803   }
00804   switch (Channel)
00805   {
00806     case TIM_CHANNEL_1:
00807     {
00808       /* Set the DMA Period elapsed callback */
00809       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
00810
00811       /* Set the DMA error callback */
00812       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
00813
00814       /* Enable t  he DMA Stream */
00815       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
00816
00817       /* Enable the TIM Capture/Compare 1 DMA request */
00818       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00819     }
00820     break;
00821
00822     case TIM_CHANNEL_2:
00823     {
00824       /* Set the DMA Period elapsed callback */
00825       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
00826
00827       /* Set the DMA error callback */
00828       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
00829
00830       /* Enable t  he DMA Stream */
00831       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
00832
00833       /* Enable the TIM Capture/Compare 2 DMA request */
00834       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
00835     }
00836     break;
00837
00838     case TIM_CHANNEL_3:
00839     {
00840       /* Set the DMA Period elapsed callback */
00841       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
00842
00843       /* Set the DMA error callback */
00844       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
00845
00846       /* Enable t  he DMA Stream */
00847       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
00848
00849       /* Enable the TIM Capture/Compare 3 DMA request */
00850       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
00851     }
00852     break;
00853
00854     case TIM_CHANNEL_4:
00855     {
00856      /* Set the DMA Period elapsed callback */
00857       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
00858
00859       /* Set the DMA error callback */
00860       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
00861
00862       /* Enable t  he DMA Stream */
00863       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
00864
00865       /* Enable the TIM Capture/Compare 4 DMA request */
00866       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
00867     }
00868     break;
00869
00870     default:
00871     break;
00872   }
00873
00874   /* Enable the Output compare channel */
00875   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00876
00877   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00878   {
00879     /* Enable the main output */
00880     __HAL_TIM_MOE_ENABLE(htim);
00881   }
00882
00883   /* Enable the Peripheral */
00884   __HAL_TIM_ENABLE(htim);
00885
00886   /* Return function status */
00887   return HAL_OK;
00888 }
00889
00890 /**
00891   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
00892   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00893   *                the configuration information for TIM module.
00894   * @param  Channel : TIM Channel to be disabled.
00895   *          This parameter can be one of the following values:
00896   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00897   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00898   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00899   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00900   * @retval HAL status
00901 */
00902 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
00903 {
00904   /* Check the parameters */
00905   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00906
00907   switch (Channel)
00908   {
00909     case TIM_CHANNEL_1:
00910     {
00911       /* Disable the TIM Capture/Compare 1 DMA request */
00912       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00913     }
00914     break;
00915
00916     case TIM_CHANNEL_2:
00917     {
00918       /* Disable the TIM Capture/Compare 2 DMA request */
00919       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
00920     }
00921     break;
00922
00923     case TIM_CHANNEL_3:
00924     {
00925       /* Disable the TIM Capture/Compare 3 DMA request */
00926       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
00927     }
00928     break;
00929
00930     case TIM_CHANNEL_4:
00931     {
00932       /* Disable the TIM Capture/Compare 4 interrupt */
00933       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
00934     }
00935     break;
00936
00937     default:
00938     break;
00939   }
00940
00941   /* Disable the Output compare channel */
00942   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00943
00944   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00945   {
00946     /* Disable the Main Output */
00947     __HAL_TIM_MOE_DISABLE(htim);
00948   }
00949
00950   /* Disable the Peripheral */
00951   __HAL_TIM_DISABLE(htim);
00952
00953   /* Change the htim state */
00954   htim->State = HAL_TIM_STATE_READY;
00955
00956   /* Return function status */
00957   return HAL_OK;
00958 }
00959
00960 /**
00961   * @}
00962   */
00963
00964 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
00965  *  @brief    Time PWM functions
00966  *
00967 @verbatim
00968   ==============================================================================
00969                           ##### TIM PWM functions #####
00970   ==============================================================================
00971   [..]
00972     This section provides functions allowing to:
00973     (+) Initialize and configure the TIM PWM mode.
00974     (+) De-initialize the TIM PWM mode.
00975     (+) Start the TIM PWM mode.
00976     (+) Stop the TIM PWM mode.
00977     (+) Start the TIM PWM mode and enable interrupt.
00978     (+) Stop the TIM PWM mode and disable interrupt.
00979     (+) Start the TIM PWM mode and enable DMA transfer.
00980     (+) Stop the TIM PWM mode and disable DMA transfer.
00981
00982 @endverbatim
00983   * @{
00984   */
00985 /**
00986   * @brief  Initialize the TIM PWM mode according to the specified
00987   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
00988   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00989   *                the configuration information for TIM module.
00990   * @retval HAL status
00991   */
00992 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
00993 {
00994   /* Check the TIM handle allocation */
00995   if(htim == NULL)
00996   {
00997     return HAL_ERROR;
00998   }
00999
01000   /* Check the parameters */
01001   assert_param(IS_TIM_INSTANCE(htim->Instance));
01002   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
01003   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
01004
01005   if(htim->State == HAL_TIM_STATE_RESET)
01006   {
01007     /* Allocate lock resource and initialize it */
01008     htim->Lock = HAL_UNLOCKED;
01009
01010     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01011     HAL_TIM_PWM_MspInit(htim);
01012   }
01013
01014   /* Set the TIM state */
01015   htim->State= HAL_TIM_STATE_BUSY;
01016
01017   /* Init the base time for the PWM */
01018   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01019
01020   /* Initialize the TIM state*/
01021   htim->State= HAL_TIM_STATE_READY;
01022
01023   return HAL_OK;
01024 }
01025
01026 /**
01027   * @brief  DeInitialize the TIM peripheral
01028   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01029   *                the configuration information for TIM module.
01030   * @retval HAL status
01031   */
01032 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
01033 {
01034   /* Check the parameters */
01035   assert_param(IS_TIM_INSTANCE(htim->Instance));
01036
01037   htim->State = HAL_TIM_STATE_BUSY;
01038
01039   /* Disable the TIM Peripheral Clock */
01040   __HAL_TIM_DISABLE(htim);
01041
01042   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
01043   HAL_TIM_PWM_MspDeInit(htim);
01044
01045   /* Change TIM state */
01046   htim->State = HAL_TIM_STATE_RESET;
01047
01048   /* Release Lock */
01049   __HAL_UNLOCK(htim);
01050
01051   return HAL_OK;
01052 }
01053
01054 /**
01055   * @brief  Initialize the TIM PWM MSP.
01056   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01057   *                the configuration information for TIM module.
01058   * @retval None
01059   */
01060 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
01061 {
01062   /* Prevent unused argument(s) compilation warning */
01063   UNUSED(htim);
01064
01065   /* NOTE : This function Should not be modified, when the callback is needed,
01066             the HAL_TIM_PWM_MspInit could be implemented in the user file
01067    */
01068 }
01069
01070 /**
01071   * @brief  DeInitialize TIM PWM MSP.
01072   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01073   *                the configuration information for TIM module.
01074   * @retval None
01075   */
01076 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
01077 {
01078   /* Prevent unused argument(s) compilation warning */
01079   UNUSED(htim);
01080
01081   /* NOTE : This function Should not be modified, when the callback is needed,
01082             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
01083    */
01084 }
01085
01086 /**
01087   * @brief  Starts the PWM signal generation.
01088   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01089   *                the configuration information for TIM module.
01090   * @param  Channel : TIM Channels to be enabled.
01091   *          This parameter can be one of the following values:
01092   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01093   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01094   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01095   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01096   * @retval HAL status
01097 */
01098 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
01099 {
01100   /* Check the parameters */
01101   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01102
01103   /* Enable the Capture compare channel */
01104   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01105
01106   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01107   {
01108     /* Enable the main output */
01109     __HAL_TIM_MOE_ENABLE(htim);
01110   }
01111
01112   /* Enable the Peripheral */
01113   __HAL_TIM_ENABLE(htim);
01114
01115   /* Return function status */
01116   return HAL_OK;
01117 }
01118
01119 /**
01120   * @brief  Stops the PWM signal generation.
01121   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01122   *                the configuration information for TIM module.
01123   * @param  Channel : TIM Channels to be disabled.
01124   *          This parameter can be one of the following values:
01125   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01126   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01127   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01128   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01129   * @retval HAL status
01130 */
01131 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01132 {
01133   /* Check the parameters */
01134   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01135
01136   /* Disable the Capture compare channel */
01137   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01138
01139   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01140   {
01141     /* Disable the Main Output */
01142     __HAL_TIM_MOE_DISABLE(htim);
01143   }
01144
01145   /* Disable the Peripheral */
01146   __HAL_TIM_DISABLE(htim);
01147
01148   /* Change the htim state */
01149   htim->State = HAL_TIM_STATE_READY;
01150
01151   /* Return function status */
01152   return HAL_OK;
01153 }
01154
01155 /**
01156   * @brief  Starts the PWM signal generation in interrupt mode.
01157   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01158   *                the configuration information for TIM module.
01159   * @param  Channel : TIM Channel to be disabled.
01160   *          This parameter can be one of the following values:
01161   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01162   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01163   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01164   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01165   * @retval HAL status
01166 */
01167 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01168 {
01169   /* Check the parameters */
01170   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01171
01172   switch (Channel)
01173   {
01174     case TIM_CHANNEL_1:
01175     {
01176       /* Enable the TIM Capture/Compare 1 interrupt */
01177       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01178     }
01179     break;
01180
01181     case TIM_CHANNEL_2:
01182     {
01183       /* Enable the TIM Capture/Compare 2 interrupt */
01184       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01185     }
01186     break;
01187
01188     case TIM_CHANNEL_3:
01189     {
01190       /* Enable the TIM Capture/Compare 3 interrupt */
01191       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01192     }
01193     break;
01194
01195     case TIM_CHANNEL_4:
01196     {
01197       /* Enable the TIM Capture/Compare 4 interrupt */
01198       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01199     }
01200     break;
01201
01202     default:
01203     break;
01204   }
01205
01206   /* Enable the Capture compare channel */
01207   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01208
01209   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01210   {
01211     /* Enable the main output */
01212     __HAL_TIM_MOE_ENABLE(htim);
01213   }
01214
01215   /* Enable the Peripheral */
01216   __HAL_TIM_ENABLE(htim);
01217
01218   /* Return function status */
01219   return HAL_OK;
01220 }
01221
01222 /**
01223   * @brief  Stops the PWM signal generation in interrupt mode.
01224   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01225   *                the configuration information for TIM module.
01226   * @param  Channel : TIM Channels to be disabled.
01227   *          This parameter can be one of the following values:
01228   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01229   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01230   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01231   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01232   * @retval HAL status
01233 */
01234 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
01235 {
01236   /* Check the parameters */
01237   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01238
01239   switch (Channel)
01240   {
01241     case TIM_CHANNEL_1:
01242     {
01243       /* Disable the TIM Capture/Compare 1 interrupt */
01244       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01245     }
01246     break;
01247
01248     case TIM_CHANNEL_2:
01249     {
01250       /* Disable the TIM Capture/Compare 2 interrupt */
01251       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01252     }
01253     break;
01254
01255     case TIM_CHANNEL_3:
01256     {
01257       /* Disable the TIM Capture/Compare 3 interrupt */
01258       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01259     }
01260     break;
01261
01262     case TIM_CHANNEL_4:
01263     {
01264       /* Disable the TIM Capture/Compare 4 interrupt */
01265       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01266     }
01267     break;
01268
01269     default:
01270     break;
01271   }
01272
01273   /* Disable the Capture compare channel */
01274   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01275
01276   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01277   {
01278     /* Disable the Main Output */
01279     __HAL_TIM_MOE_DISABLE(htim);
01280   }
01281
01282   /* Disable the Peripheral */
01283   __HAL_TIM_DISABLE(htim);
01284
01285   /* Return function status */
01286   return HAL_OK;
01287 }
01288
01289 /**
01290   * @brief  Starts the TIM PWM signal generation in DMA mode.
01291   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01292   *                the configuration information for TIM module.
01293   * @param  Channel : TIM Channels to be enabled.
01294   *          This parameter can be one of the following values:
01295   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01296   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01297   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01298   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01299   * @param  pData: The source Buffer address.
01300   * @param  Length: The length of data to be transferred from memory to TIM peripheral
01301   * @retval HAL status
01302 */
01303 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01304 {
01305   /* Check the parameters */
01306   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01307
01308   if((htim->State) == (HAL_TIM_STATE_BUSY))
01309   {
01310      return HAL_BUSY;
01311   }
01312   else if((htim->State) == (HAL_TIM_STATE_READY))
01313   {
01314     if(((uint32_t)pData == 0 ) && (Length > 0))
01315     {
01316       return HAL_ERROR;
01317     }
01318     else
01319     {
01320       htim->State = HAL_TIM_STATE_BUSY;
01321     }
01322   }
01323   switch (Channel)
01324   {
01325     case TIM_CHANNEL_1:
01326     {
01327       /* Set the DMA Period elapsed callback */
01328       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
01329
01330       /* Set the DMA error callback */
01331       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
01332
01333       /* Enable t  he DMA Stream */
01334       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
01335
01336       /* Enable the TIM Capture/Compare 1 DMA request */
01337       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01338     }
01339     break;
01340
01341     case TIM_CHANNEL_2:
01342     {
01343       /* Set the DMA Period elapsed callback */
01344       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
01345
01346       /* Set the DMA error callback */
01347       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
01348
01349       /* Enable t  he DMA Stream */
01350       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
01351
01352       /* Enable the TIM Capture/Compare 2 DMA request */
01353       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01354     }
01355     break;
01356
01357     case TIM_CHANNEL_3:
01358     {
01359       /* Set the DMA Period elapsed callback */
01360       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
01361
01362       /* Set the DMA error callback */
01363       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
01364
01365       /* Enable t  he DMA Stream */
01366       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
01367
01368       /* Enable the TIM Output Capture/Compare 3 request */
01369       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01370     }
01371     break;
01372
01373     case TIM_CHANNEL_4:
01374     {
01375      /* Set the DMA Period elapsed callback */
01376       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
01377
01378       /* Set the DMA error callback */
01379       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
01380
01381       /* Enable t  he DMA Stream */
01382       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
01383
01384       /* Enable the TIM Capture/Compare 4 DMA request */
01385       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01386     }
01387     break;
01388
01389     default:
01390     break;
01391   }
01392
01393   /* Enable the Capture compare channel */
01394   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01395
01396   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01397   {
01398     /* Enable the main output */
01399     __HAL_TIM_MOE_ENABLE(htim);
01400   }
01401
01402   /* Enable the Peripheral */
01403   __HAL_TIM_ENABLE(htim);
01404
01405   /* Return function status */
01406   return HAL_OK;
01407 }
01408
01409 /**
01410   * @brief  Stops the TIM PWM signal generation in DMA mode.
01411   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01412   *                the configuration information for TIM module.
01413   * @param  Channel : TIM Channels to be disabled.
01414   *          This parameter can be one of the following values:
01415   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01416   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01417   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01418   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01419   * @retval HAL status
01420 */
01421 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01422 {
01423   /* Check the parameters */
01424   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01425
01426   switch (Channel)
01427   {
01428     case TIM_CHANNEL_1:
01429     {
01430       /* Disable the TIM Capture/Compare 1 DMA request */
01431       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01432     }
01433     break;
01434
01435     case TIM_CHANNEL_2:
01436     {
01437       /* Disable the TIM Capture/Compare 2 DMA request */
01438       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01439     }
01440     break;
01441
01442     case TIM_CHANNEL_3:
01443     {
01444       /* Disable the TIM Capture/Compare 3 DMA request */
01445       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01446     }
01447     break;
01448
01449     case TIM_CHANNEL_4:
01450     {
01451       /* Disable the TIM Capture/Compare 4 interrupt */
01452       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01453     }
01454     break;
01455
01456     default:
01457     break;
01458   }
01459
01460   /* Disable the Capture compare channel */
01461   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01462
01463   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01464   {
01465     /* Disable the Main Output */
01466     __HAL_TIM_MOE_DISABLE(htim);
01467   }
01468
01469   /* Disable the Peripheral */
01470   __HAL_TIM_DISABLE(htim);
01471
01472   /* Change the htim state */
01473   htim->State = HAL_TIM_STATE_READY;
01474
01475   /* Return function status */
01476   return HAL_OK;
01477 }
01478
01479 /**
01480   * @}
01481   */
01482
01483 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
01484  *  @brief    Time Input Capture functions
01485  *
01486 @verbatim
01487   ==============================================================================
01488               ##### TIM Input Capture functions #####
01489   ==============================================================================
01490  [..]
01491    This section provides functions allowing to:
01492    (+) Initialize and configure the TIM Input Capture.
01493    (+) De-initialize the TIM Input Capture.
01494    (+) Start the TIM Input Capture mode.
01495    (+) Stop the TIM Input Capture mode.
01496    (+) Start the TIM Input Capture mode and enable interrupt.
01497    (+) Stop the TIM Input Capture mode and disable interrupt.
01498    (+) Start the TIM Input Capture mode and enable DMA transfer.
01499    (+) Stop the TIM Input Capture mode and disable DMA transfer.
01500
01501 @endverbatim
01502   * @{
01503   */
01504 /**
01505   * @brief  Initialize the TIM Input Capture Time base according to the specified
01506   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
01507   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01508   *                the configuration information for TIM module.
01509   * @retval HAL status
01510   */
01511 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
01512 {
01513   /* Check the TIM handle allocation */
01514   if(htim == NULL)
01515   {
01516     return HAL_ERROR;
01517   }
01518
01519   /* Check the parameters */
01520   assert_param(IS_TIM_INSTANCE(htim->Instance));
01521   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
01522   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
01523
01524   if(htim->State == HAL_TIM_STATE_RESET)
01525   {
01526     /* Allocate lock resource and initialize it */
01527     htim->Lock = HAL_UNLOCKED;
01528
01529     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01530     HAL_TIM_IC_MspInit(htim);
01531   }
01532
01533   /* Set the TIM state */
01534   htim->State= HAL_TIM_STATE_BUSY;
01535
01536   /* Init the base time for the input capture */
01537   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01538
01539   /* Initialize the TIM state*/
01540   htim->State= HAL_TIM_STATE_READY;
01541
01542   return HAL_OK;
01543 }
01544
01545 /**
01546   * @brief  DeInitialize the TIM peripheral
01547   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01548   *                the configuration information for TIM module.
01549   * @retval HAL status
01550   */
01551 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
01552 {
01553   /* Check the parameters */
01554   assert_param(IS_TIM_INSTANCE(htim->Instance));
01555
01556   htim->State = HAL_TIM_STATE_BUSY;
01557
01558   /* Disable the TIM Peripheral Clock */
01559   __HAL_TIM_DISABLE(htim);
01560
01561   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
01562   HAL_TIM_IC_MspDeInit(htim);
01563
01564   /* Change TIM state */
01565   htim->State = HAL_TIM_STATE_RESET;
01566
01567   /* Release Lock */
01568   __HAL_UNLOCK(htim);
01569
01570   return HAL_OK;
01571 }
01572
01573 /**
01574   * @brief  Initialize the TIM Input Capture MSP.
01575   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01576   *                the configuration information for TIM module.
01577   * @retval None
01578   */
01579 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
01580 {
01581   /* Prevent unused argument(s) compilation warning */
01582   UNUSED(htim);
01583
01584   /* NOTE : This function Should not be modified, when the callback is needed,
01585             the HAL_TIM_IC_MspInit could be implemented in the user file
01586    */
01587 }
01588
01589 /**
01590   * @brief  DeInitialize TIM Input Capture MSP.
01591   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01592   *                the configuration information for TIM module.
01593   * @retval None
01594   */
01595 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
01596 {
01597   /* Prevent unused argument(s) compilation warning */
01598   UNUSED(htim);
01599
01600   /* NOTE : This function Should not be modified, when the callback is needed,
01601             the HAL_TIM_IC_MspDeInit could be implemented in the user file
01602    */
01603 }
01604
01605 /**
01606   * @brief  Starts the TIM Input Capture measurement.
01607   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01608   *                the configuration information for TIM module.
01609   * @param  Channel : TIM Channels to be enabled.
01610   *          This parameter can be one of the following values:
01611   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01612   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01613   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01614   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01615   * @retval HAL status
01616 */
01617 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
01618 {
01619   /* Check the parameters */
01620   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01621
01622   /* Enable the Input Capture channel */
01623   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01624
01625   /* Enable the Peripheral */
01626   __HAL_TIM_ENABLE(htim);
01627
01628   /* Return function status */
01629   return HAL_OK;
01630 }
01631
01632 /**
01633   * @brief  Stops the TIM Input Capture measurement.
01634   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01635   *                the configuration information for TIM module.
01636   * @param  Channel : TIM Channels to be disabled.
01637   *          This parameter can be one of the following values:
01638   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01639   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01640   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01641   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01642   * @retval HAL status
01643 */
01644 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01645 {
01646   /* Check the parameters */
01647   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01648
01649   /* Disable the Input Capture channel */
01650   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01651
01652   /* Disable the Peripheral */
01653   __HAL_TIM_DISABLE(htim);
01654
01655   /* Return function status */
01656   return HAL_OK;
01657 }
01658
01659 /**
01660   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
01661   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01662   *                the configuration information for TIM module.
01663   * @param  Channel : TIM Channels to be enabled.
01664   *          This parameter can be one of the following values:
01665   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01666   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01667   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01668   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01669   * @retval HAL status
01670 */
01671 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
01672 {
01673   /* Check the parameters */
01674   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01675
01676   switch (Channel)
01677   {
01678     case TIM_CHANNEL_1:
01679     {
01680       /* Enable the TIM Capture/Compare 1 interrupt */
01681       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01682     }
01683     break;
01684
01685     case TIM_CHANNEL_2:
01686     {
01687       /* Enable the TIM Capture/Compare 2 interrupt */
01688       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01689     }
01690     break;
01691
01692     case TIM_CHANNEL_3:
01693     {
01694       /* Enable the TIM Capture/Compare 3 interrupt */
01695       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01696     }
01697     break;
01698
01699     case TIM_CHANNEL_4:
01700     {
01701       /* Enable the TIM Capture/Compare 4 interrupt */
01702       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01703     }
01704     break;
01705
01706     default:
01707     break;
01708   }
01709   /* Enable the Input Capture channel */
01710   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01711
01712   /* Enable the Peripheral */
01713   __HAL_TIM_ENABLE(htim);
01714
01715   /* Return function status */
01716   return HAL_OK;
01717 }
01718
01719 /**
01720   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
01721   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01722   *                the configuration information for TIM module.
01723   * @param  Channel : TIM Channels to be disabled.
01724   *          This parameter can be one of the following values:
01725   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01726   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01727   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01728   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01729   * @retval HAL status
01730 */
01731 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01732 {
01733   /* Check the parameters */
01734   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01735
01736   switch (Channel)
01737   {
01738     case TIM_CHANNEL_1:
01739     {
01740       /* Disable the TIM Capture/Compare 1 interrupt */
01741       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01742     }
01743     break;
01744
01745     case TIM_CHANNEL_2:
01746     {
01747       /* Disable the TIM Capture/Compare 2 interrupt */
01748       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01749     }
01750     break;
01751
01752     case TIM_CHANNEL_3:
01753     {
01754       /* Disable the TIM Capture/Compare 3 interrupt */
01755       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01756     }
01757     break;
01758
01759     case TIM_CHANNEL_4:
01760     {
01761       /* Disable the TIM Capture/Compare 4 interrupt */
01762       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01763     }
01764     break;
01765
01766     default:
01767     break;
01768   }
01769
01770   /* Disable the Input Capture channel */
01771   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01772
01773   /* Disable the Peripheral */
01774   __HAL_TIM_DISABLE(htim);
01775
01776   /* Return function status */
01777   return HAL_OK;
01778 }
01779
01780 /**
01781   * @brief  Starts the TIM Input Capture measurement on in DMA mode.
01782   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01783   *                the configuration information for TIM module.
01784   * @param  Channel : TIM Channels to be enabled.
01785   *          This parameter can be one of the following values:
01786   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01787   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01788   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01789   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01790   * @param  pData: The destination Buffer address.
01791   * @param  Length: The length of data to be transferred from TIM peripheral to memory.
01792   * @retval HAL status
01793 */
01794 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01795 {
01796   /* Check the parameters */
01797   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01798   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
01799
01800   if((htim->State) == (HAL_TIM_STATE_BUSY))
01801   {
01802      return HAL_BUSY;
01803   }
01804   else if((htim->State) == (HAL_TIM_STATE_READY))
01805   {
01806     if((pData == 0 ) && (Length > 0))
01807     {
01808       return HAL_ERROR;
01809     }
01810     else
01811     {
01812       htim->State = HAL_TIM_STATE_BUSY;
01813     }
01814   }
01815
01816   switch (Channel)
01817   {
01818     case TIM_CHANNEL_1:
01819     {
01820       /* Set the DMA Period elapsed callback */
01821       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
01822
01823       /* Set the DMA error callback */
01824       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
01825
01826       /* Enable t  he DMA Stream */
01827       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
01828
01829       /* Enable the TIM Capture/Compare 1 DMA request */
01830       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01831     }
01832     break;
01833
01834     case TIM_CHANNEL_2:
01835     {
01836       /* Set the DMA Period elapsed callback */
01837       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
01838
01839       /* Set the DMA error callback */
01840       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
01841
01842       /* Enable t  he DMA Stream */
01843       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
01844
01845       /* Enable the TIM Capture/Compare 2  DMA request */
01846       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01847     }
01848     break;
01849
01850     case TIM_CHANNEL_3:
01851     {
01852       /* Set the DMA Period elapsed callback */
01853       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
01854
01855       /* Set the DMA error callback */
01856       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
01857
01858       /* Enable t  he DMA Stream */
01859       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
01860
01861       /* Enable the TIM Capture/Compare 3  DMA request */
01862       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01863     }
01864     break;
01865
01866     case TIM_CHANNEL_4:
01867     {
01868       /* Set the DMA Period elapsed callback */
01869       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
01870
01871       /* Set the DMA error callback */
01872       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
01873
01874       /* Enable t  he DMA Stream */
01875       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
01876
01877       /* Enable the TIM Capture/Compare 4  DMA request */
01878       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01879     }
01880     break;
01881
01882     default:
01883     break;
01884   }
01885
01886   /* Enable the Input Capture channel */
01887   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01888
01889   /* Enable the Peripheral */
01890   __HAL_TIM_ENABLE(htim);
01891
01892   /* Return function status */
01893   return HAL_OK;
01894 }
01895
01896 /**
01897   * @brief  Stops the TIM Input Capture measurement on in DMA mode.
01898   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01899   *                the configuration information for TIM module.
01900   * @param  Channel : TIM Channels to be disabled.
01901   *          This parameter can be one of the following values:
01902   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01903   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01904   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01905   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01906   * @retval HAL status
01907 */
01908 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01909 {
01910   /* Check the parameters */
01911   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01912   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
01913
01914   switch (Channel)
01915   {
01916     case TIM_CHANNEL_1:
01917     {
01918       /* Disable the TIM Capture/Compare 1 DMA request */
01919       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01920     }
01921     break;
01922
01923     case TIM_CHANNEL_2:
01924     {
01925       /* Disable the TIM Capture/Compare 2 DMA request */
01926       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01927     }
01928     break;
01929
01930     case TIM_CHANNEL_3:
01931     {
01932       /* Disable the TIM Capture/Compare 3  DMA request */
01933       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01934     }
01935     break;
01936
01937     case TIM_CHANNEL_4:
01938     {
01939       /* Disable the TIM Capture/Compare 4  DMA request */
01940       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01941     }
01942     break;
01943
01944     default:
01945     break;
01946   }
01947
01948   /* Disable the Input Capture channel */
01949   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01950
01951   /* Disable the Peripheral */
01952   __HAL_TIM_DISABLE(htim);
01953
01954   /* Change the htim state */
01955   htim->State = HAL_TIM_STATE_READY;
01956
01957   /* Return function status */
01958   return HAL_OK;
01959 }
01960 /**
01961   * @}
01962   */
01963
01964 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
01965  *  @brief    Time One Pulse functions
01966  *
01967 @verbatim
01968   ==============================================================================
01969                         ##### TIM One Pulse functions #####
01970   ==============================================================================
01971   [..]
01972     This section provides functions allowing to:
01973     (+) Initialize and configure the TIM One Pulse mode.
01974     (+) De-initialize the TIM One Pulse mode.
01975     (+) Start the TIM One Pulse mode.
01976     (+) Stop the TIM One Pulse mode.
01977     (+) Start the TIM One Pulse mode and enable interrupt.
01978     (+) Stop the TIM One Pulse mode and disable interrupt.
01979     (+) Start the TIM One Pulse mode and enable DMA transfer.
01980     (+) Stop the TIM One Pulse mode and disable DMA transfer.
01981
01982 @endverbatim
01983   * @{
01984   */
01985 /**
01986   * @brief  Initialize the TIM One Pulse mode according to the specified
01987   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
01988   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01989   *                the configuration information for TIM module.
01990   * @param  OnePulseMode: Select the One pulse mode.
01991   *         This parameter can be one of the following values:
01992   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
01993   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
01994   * @retval HAL status
01995   */
01996 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
01997 {
01998   /* Check the TIM handle allocation */
01999   if(htim == NULL)
02000   {
02001     return HAL_ERROR;
02002   }
02003
02004   /* Check the parameters */
02005   assert_param(IS_TIM_INSTANCE(htim->Instance));
02006   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
02007   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
02008   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
02009
02010   if(htim->State == HAL_TIM_STATE_RESET)
02011   {
02012     /* Allocate lock resource and initialize it */
02013     htim->Lock = HAL_UNLOCKED;
02014
02015     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
02016     HAL_TIM_OnePulse_MspInit(htim);
02017   }
02018
02019   /* Set the TIM state */
02020   htim->State= HAL_TIM_STATE_BUSY;
02021
02022   /* Configure the Time base in the One Pulse Mode */
02023   TIM_Base_SetConfig(htim->Instance, &htim->Init);
02024
02025   /* Reset the OPM Bit */
02026   htim->Instance->CR1 &= ~TIM_CR1_OPM;
02027
02028   /* Configure the OPM Mode */
02029   htim->Instance->CR1 |= OnePulseMode;
02030
02031   /* Initialize the TIM state*/
02032   htim->State= HAL_TIM_STATE_READY;
02033
02034   return HAL_OK;
02035 }
02036
02037 /**
02038   * @brief  DeInitialize the TIM One Pulse mode
02039   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02040   *                the configuration information for TIM module.
02041   * @retval HAL status
02042   */
02043 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
02044 {
02045   /* Check the parameters */
02046   assert_param(IS_TIM_INSTANCE(htim->Instance));
02047
02048   htim->State = HAL_TIM_STATE_BUSY;
02049
02050   /* Disable the TIM Peripheral Clock */
02051   __HAL_TIM_DISABLE(htim);
02052
02053   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
02054   HAL_TIM_OnePulse_MspDeInit(htim);
02055
02056   /* Change TIM state */
02057   htim->State = HAL_TIM_STATE_RESET;
02058
02059   /* Release Lock */
02060   __HAL_UNLOCK(htim);
02061
02062   return HAL_OK;
02063 }
02064
02065 /**
02066   * @brief  Initialize the TIM One Pulse MSP.
02067   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02068   *                the configuration information for TIM module.
02069   * @retval None
02070   */
02071 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
02072 {
02073   /* Prevent unused argument(s) compilation warning */
02074   UNUSED(htim);
02075
02076   /* NOTE : This function Should not be modified, when the callback is needed,
02077             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
02078    */
02079 }
02080
02081 /**
02082   * @brief  DeInitialize TIM One Pulse MSP.
02083   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02084   *                the configuration information for TIM module.
02085   * @retval None
02086   */
02087 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
02088 {
02089   /* Prevent unused argument(s) compilation warning */
02090   UNUSED(htim);
02091
02092   /* NOTE : This function Should not be modified, when the callback is needed,
02093             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
02094    */
02095 }
02096
02097 /**
02098   * @brief  Starts the TIM One Pulse signal generation.
02099   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02100   *                the configuration information for TIM module.
02101   * @param  OutputChannel : TIM Channels to be enabled.
02102   *          This parameter can be one of the following values:
02103   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02104   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02105   * @retval HAL status
02106 */
02107 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02108 {
02109   /* Prevent unused argument(s) compilation warning */
02110   UNUSED(OutputChannel);
02111
02112   /* Enable the Capture compare and the Input Capture channels
02113     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02114     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02115     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02116     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
02117
02118     No need to enable the counter, it's enabled automatically by hardware
02119     (the counter starts in response to a stimulus and generate a pulse */
02120
02121   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02122   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02123
02124   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02125   {
02126     /* Enable the main output */
02127     __HAL_TIM_MOE_ENABLE(htim);
02128   }
02129
02130   /* Return function status */
02131   return HAL_OK;
02132 }
02133
02134 /**
02135   * @brief  Stops the TIM One Pulse signal generation.
02136   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02137   *                the configuration information for TIM module.
02138   * @param  OutputChannel : TIM Channels to be disabled.
02139   *          This parameter can be one of the following values:
02140   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02141   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02142   * @retval HAL status
02143 */
02144 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02145 {
02146   /* Prevent unused argument(s) compilation warning */
02147   UNUSED(OutputChannel);
02148
02149   /* Disable the Capture compare and the Input Capture channels
02150   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02151   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02152   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02153   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02154
02155   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02156   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02157
02158   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02159   {
02160     /* Disable the Main Output */
02161     __HAL_TIM_MOE_DISABLE(htim);
02162   }
02163
02164   /* Disable the Peripheral */
02165   __HAL_TIM_DISABLE(htim);
02166
02167   /* Return function status */
02168   return HAL_OK;
02169 }
02170
02171 /**
02172   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
02173   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02174   *                the configuration information for TIM module.
02175   * @param  OutputChannel : TIM Channels to be enabled.
02176   *          This parameter can be one of the following values:
02177   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02178   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02179   * @retval HAL status
02180 */
02181 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02182 {
02183   /* Prevent unused argument(s) compilation warning */
02184   UNUSED(OutputChannel);
02185
02186   /* Enable the Capture compare and the Input Capture channels
02187     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02188     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02189     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02190     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
02191
02192     No need to enable the counter, it's enabled automatically by hardware
02193     (the counter starts in response to a stimulus and generate a pulse */
02194
02195   /* Enable the TIM Capture/Compare 1 interrupt */
02196   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02197
02198   /* Enable the TIM Capture/Compare 2 interrupt */
02199   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02200
02201   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02202   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02203
02204   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02205   {
02206     /* Enable the main output */
02207     __HAL_TIM_MOE_ENABLE(htim);
02208   }
02209
02210   /* Return function status */
02211   return HAL_OK;
02212 }
02213
02214 /**
02215   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
02216   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02217   *                the configuration information for TIM module.
02218   * @param  OutputChannel : TIM Channels to be enabled.
02219   *          This parameter can be one of the following values:
02220   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02221   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02222   * @retval HAL status
02223 */
02224 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02225 {
02226   /* Prevent unused argument(s) compilation warning */
02227   UNUSED(OutputChannel);
02228
02229   /* Disable the TIM Capture/Compare 1 interrupt */
02230   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02231
02232   /* Disable the TIM Capture/Compare 2 interrupt */
02233   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02234
02235   /* Disable the Capture compare and the Input Capture channels
02236   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02237   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02238   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02239   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02240   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02241   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02242
02243   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02244   {
02245     /* Disable the Main Output */
02246     __HAL_TIM_MOE_DISABLE(htim);
02247   }
02248
02249   /* Disable the Peripheral */
02250    __HAL_TIM_DISABLE(htim);
02251
02252   /* Return function status */
02253   return HAL_OK;
02254 }
02255
02256 /**
02257   * @}
02258   */
02259
02260 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
02261  *  @brief    TIM Encoder functions
02262  *
02263 @verbatim
02264   ==============================================================================
02265                           ##### TIM Encoder functions #####
02266   ==============================================================================
02267   [..]
02268     This section provides functions allowing to:
02269     (+) Initialize and configure the TIM Encoder.
02270     (+) De-initialize the TIM Encoder mode.
02271     (+) Start the Time Encoder mode.
02272     (+) Stop the Time Encoder mode.
02273     (+) Start the Time Encoder mode and enable interrupt.
02274     (+) Stop the Time Encoder mode and disable interrupt.
02275     (+) Start the Time Encoder mode and enable DMA transfer.
02276     (+) Stop the Time Encoder mode and disable DMA transfer.
02277
02278 @endverbatim
02279   * @{
02280   */
02281 /**
02282   * @brief  Initialize the TIM Encoder Interface and initialize the associated handle.
02283   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02284   *                the configuration information for TIM module.
02285   * @param  sConfig: TIM Encoder Interface configuration structure.
02286   * @retval HAL status
02287   */
02288 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig)
02289 {
02290   uint32_t tmpsmcr = 0;
02291   uint32_t tmpccmr1 = 0;
02292   uint32_t tmpccer = 0;
02293
02294   /* Check the TIM handle allocation */
02295   if(htim == NULL)
02296   {
02297     return HAL_ERROR;
02298   }
02299
02300   /* Check the parameters */
02301   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02302   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
02303   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
02304   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
02305   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
02306   assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
02307   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
02308   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
02309   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
02310   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
02311
02312   if(htim->State == HAL_TIM_STATE_RESET)
02313   {
02314     /* Allocate lock resource and initialize it */
02315     htim->Lock = HAL_UNLOCKED;
02316
02317     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
02318     HAL_TIM_Encoder_MspInit(htim);
02319   }
02320
02321   /* Set the TIM state */
02322   htim->State= HAL_TIM_STATE_BUSY;
02323
02324   /* Reset the SMS bits */
02325   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
02326
02327   /* Configure the Time base in the Encoder Mode */
02328   TIM_Base_SetConfig(htim->Instance, &htim->Init);
02329
02330   /* Get the TIMx SMCR register value */
02331   tmpsmcr = htim->Instance->SMCR;
02332
02333   /* Get the TIMx CCMR1 register value */
02334   tmpccmr1 = htim->Instance->CCMR1;
02335
02336   /* Get the TIMx CCER register value */
02337   tmpccer = htim->Instance->CCER;
02338
02339   /* Set the encoder Mode */
02340   tmpsmcr |= sConfig->EncoderMode;
02341
02342   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
02343   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
02344   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
02345
02346   /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
02347   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
02348   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
02349   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
02350   tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
02351
02352   /* Set the TI1 and the TI2 Polarities */
02353   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
02354   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
02355   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
02356
02357   /* Write to TIMx SMCR */
02358   htim->Instance->SMCR = tmpsmcr;
02359
02360   /* Write to TIMx CCMR1 */
02361   htim->Instance->CCMR1 = tmpccmr1;
02362
02363   /* Write to TIMx CCER */
02364   htim->Instance->CCER = tmpccer;
02365
02366   /* Initialize the TIM state*/
02367   htim->State= HAL_TIM_STATE_READY;
02368
02369   return HAL_OK;
02370 }
02371
02372
02373 /**
02374   * @brief  DeInitialize the TIM Encoder interface
02375   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02376   *                the configuration information for TIM module.
02377   * @retval HAL status
02378   */
02379 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
02380 {
02381   /* Check the parameters */
02382   assert_param(IS_TIM_INSTANCE(htim->Instance));
02383
02384   htim->State = HAL_TIM_STATE_BUSY;
02385
02386   /* Disable the TIM Peripheral Clock */
02387   __HAL_TIM_DISABLE(htim);
02388
02389   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
02390   HAL_TIM_Encoder_MspDeInit(htim);
02391
02392   /* Change TIM state */
02393   htim->State = HAL_TIM_STATE_RESET;
02394
02395   /* Release Lock */
02396   __HAL_UNLOCK(htim);
02397
02398   return HAL_OK;
02399 }
02400
02401 /**
02402   * @brief  Initialize the TIM Encoder Interface MSP.
02403   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02404   *                the configuration information for TIM module.
02405   * @retval None
02406   */
02407 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
02408 {
02409   /* Prevent unused argument(s) compilation warning */
02410   UNUSED(htim);
02411
02412   /* NOTE : This function Should not be modified, when the callback is needed,
02413             the HAL_TIM_Encoder_MspInit could be implemented in the user file
02414    */
02415 }
02416
02417 /**
02418   * @brief  DeInitialize TIM Encoder Interface MSP.
02419   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02420   *                the configuration information for TIM module.
02421   * @retval None
02422   */
02423 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
02424 {
02425   /* Prevent unused argument(s) compilation warning */
02426   UNUSED(htim);
02427
02428   /* NOTE : This function Should not be modified, when the callback is needed,
02429             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
02430    */
02431 }
02432
02433 /**
02434   * @brief  Starts the TIM Encoder Interface.
02435   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02436   *                the configuration information for TIM module.
02437   * @param  Channel : TIM Channels to be enabled.
02438   *          This parameter can be one of the following values:
02439   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02440   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02441   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02442   * @retval HAL status
02443 */
02444 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
02445 {
02446   /* Check the parameters */
02447   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02448
02449   /* Enable the encoder interface channels */
02450   switch (Channel)
02451   {
02452     case TIM_CHANNEL_1:
02453     {
02454       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02455     }
02456     break;
02457     case TIM_CHANNEL_2:
02458     {
02459       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02460     }
02461     break;
02462     default :
02463     {
02464        TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02465        TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02466     }
02467     break;
02468   }
02469   /* Enable the Peripheral */
02470   __HAL_TIM_ENABLE(htim);
02471
02472   /* Return function status */
02473   return HAL_OK;
02474 }
02475
02476 /**
02477   * @brief  Stops the TIM Encoder Interface.
02478   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02479   *                the configuration information for TIM module.
02480   * @param  Channel : TIM Channels to be disabled.
02481   *          This parameter can be one of the following values:
02482   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02483   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02484   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02485   * @retval HAL status
02486 */
02487 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
02488 {
02489   /* Check the parameters */
02490     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02491
02492    /* Disable the Input Capture channels 1 and 2
02493     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02494   switch (Channel)
02495   {
02496     case TIM_CHANNEL_1:
02497     {
02498        TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02499     }
02500     break;
02501     case TIM_CHANNEL_2:
02502     {
02503       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02504     }
02505     break;
02506     default :
02507     {
02508       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02509       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02510     }
02511     break;
02512   }
02513
02514   /* Disable the Peripheral */
02515   __HAL_TIM_DISABLE(htim);
02516
02517   /* Return function status */
02518   return HAL_OK;
02519 }
02520
02521 /**
02522   * @brief  Starts the TIM Encoder Interface in interrupt mode.
02523   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02524   *                the configuration information for TIM module.
02525   * @param  Channel : TIM Channels to be enabled.
02526   *          This parameter can be one of the following values:
02527   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02528   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02529   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02530   * @retval HAL status
02531 */
02532 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02533 {
02534   /* Check the parameters */
02535   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02536
02537   /* Enable the encoder interface channels */
02538   /* Enable the capture compare Interrupts 1 and/or 2 */
02539   switch (Channel)
02540   {
02541     case TIM_CHANNEL_1:
02542     {
02543       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02544       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02545     }
02546     break;
02547     case TIM_CHANNEL_2:
02548     {
02549       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02550       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02551     }
02552     break;
02553     default :
02554     {
02555        TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02556        TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02557        __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02558        __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02559     }
02560     break;
02561   }
02562
02563   /* Enable the Peripheral */
02564   __HAL_TIM_ENABLE(htim);
02565
02566   /* Return function status */
02567   return HAL_OK;
02568 }
02569
02570 /**
02571   * @brief  Stops the TIM Encoder Interface in interrupt mode.
02572   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02573   *                the configuration information for TIM module.
02574   * @param  Channel : TIM Channels to be disabled.
02575   *          This parameter can be one of the following values:
02576   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02577   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02578   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02579   * @retval HAL status
02580 */
02581 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02582 {
02583   /* Check the parameters */
02584   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02585
02586   /* Disable the Input Capture channels 1 and 2
02587     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02588   if(Channel == TIM_CHANNEL_1)
02589   {
02590     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02591
02592     /* Disable the capture compare Interrupts 1 */
02593   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02594   }
02595   else if(Channel == TIM_CHANNEL_2)
02596   {
02597     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02598
02599     /* Disable the capture compare Interrupts 2 */
02600   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02601   }
02602   else
02603   {
02604     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02605     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02606
02607     /* Disable the capture compare Interrupts 1 and 2 */
02608     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02609     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02610   }
02611
02612   /* Disable the Peripheral */
02613   __HAL_TIM_DISABLE(htim);
02614
02615   /* Change the htim state */
02616   htim->State = HAL_TIM_STATE_READY;
02617
02618   /* Return function status */
02619   return HAL_OK;
02620 }
02621
02622 /**
02623   * @brief  Starts the TIM Encoder Interface in DMA mode.
02624   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02625   *                the configuration information for TIM module.
02626   * @param  Channel : TIM Channels to be enabled.
02627   *          This parameter can be one of the following values:
02628   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02629   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02630   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02631   * @param  pData1: The destination Buffer address for Input Capture Channel1.
02632   * @param  pData2: The destination Buffer address for Input Capture Channel2.
02633   * @param  Length: The length of data to be transferred from TIM peripheral to memory.
02634   * @retval HAL status
02635 */
02636 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
02637 {
02638   /* Check the parameters */
02639   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02640
02641   if(htim->State == HAL_TIM_STATE_BUSY)
02642   {
02643      return HAL_BUSY;
02644   }
02645   else if(htim->State == HAL_TIM_STATE_READY)
02646   {
02647     if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
02648     {
02649       return HAL_ERROR;
02650     }
02651     else
02652     {
02653       htim->State = HAL_TIM_STATE_BUSY;
02654     }
02655   }
02656
02657   switch (Channel)
02658   {
02659     case TIM_CHANNEL_1:
02660     {
02661       /* Set the DMA Period elapsed callback */
02662       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
02663
02664       /* Set the DMA error callback */
02665       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
02666
02667       /* Enable t  he DMA Stream */
02668       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
02669
02670       /* Enable the TIM Input Capture DMA request */
02671       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
02672
02673       /* Enable the Peripheral */
02674       __HAL_TIM_ENABLE(htim);
02675
02676       /* Enable the Capture compare channel */
02677       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02678     }
02679     break;
02680
02681     case TIM_CHANNEL_2:
02682     {
02683       /* Set the DMA Period elapsed callback */
02684       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
02685
02686       /* Set the DMA error callback */
02687       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
02688       /* Enable t  he DMA Stream */
02689       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
02690
02691       /* Enable the TIM Input Capture  DMA request */
02692       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
02693
02694       /* Enable the Peripheral */
02695       __HAL_TIM_ENABLE(htim);
02696
02697       /* Enable the Capture compare channel */
02698       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02699     }
02700     break;
02701
02702     case TIM_CHANNEL_ALL:
02703     {
02704       /* Set the DMA Period elapsed callback */
02705       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
02706
02707       /* Set the DMA error callback */
02708       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
02709
02710       /* Enable t  he DMA Stream */
02711       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
02712
02713       /* Set the DMA Period elapsed callback */
02714       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
02715
02716       /* Set the DMA error callback */
02717       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
02718
02719       /* Enable t  he DMA Stream */
02720       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
02721
02722      /* Enable the Peripheral */
02723       __HAL_TIM_ENABLE(htim);
02724
02725       /* Enable the Capture compare channel */
02726       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02727       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02728
02729       /* Enable the TIM Input Capture  DMA request */
02730       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
02731       /* Enable the TIM Input Capture  DMA request */
02732       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
02733     }
02734     break;
02735
02736     default:
02737     break;
02738   }
02739   /* Return function status */
02740   return HAL_OK;
02741 }
02742
02743 /**
02744   * @brief  Stops the TIM Encoder Interface in DMA mode.
02745   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02746   *                the configuration information for TIM module.
02747   * @param  Channel : TIM Channels to be enabled.
02748   *          This parameter can be one of the following values:
02749   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02750   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02751   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02752   * @retval HAL status
02753 */
02754 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
02755 {
02756   /* Check the parameters */
02757   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02758
02759   /* Disable the Input Capture channels 1 and 2
02760     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02761   if(Channel == TIM_CHANNEL_1)
02762   {
02763     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02764
02765     /* Disable the capture compare DMA Request 1 */
02766     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
02767   }
02768   else if(Channel == TIM_CHANNEL_2)
02769   {
02770     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02771
02772     /* Disable the capture compare DMA Request 2 */
02773     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
02774   }
02775   else
02776   {
02777     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02778     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02779
02780     /* Disable the capture compare DMA Request 1 and 2 */
02781     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
02782     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
02783   }
02784
02785   /* Disable the Peripheral */
02786   __HAL_TIM_DISABLE(htim);
02787
02788   /* Change the htim state */
02789   htim->State = HAL_TIM_STATE_READY;
02790
02791   /* Return function status */
02792   return HAL_OK;
02793 }
02794
02795 /**
02796   * @}
02797   */
02798 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
02799  *  @brief    IRQ handler management
02800  *
02801 @verbatim
02802   ==============================================================================
02803                         ##### IRQ handler management #####
02804   ==============================================================================
02805   [..]
02806     This section provides TIM IRQ handler function.
02807
02808 @endverbatim
02809   * @{
02810   */
02811 /**
02812   * @brief  This function handles TIM interrupts requests.
02813   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02814   *                the configuration information for TIM module.
02815   * @retval None
02816   */
02817 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
02818 {
02819   /* Capture compare 1 event */
02820   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
02821   {
02822     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
02823     {
02824       {
02825         __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
02826         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
02827
02828         /* Input capture event */
02829         if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
02830         {
02831           HAL_TIM_IC_CaptureCallback(htim);
02832         }
02833         /* Output compare event */
02834         else
02835         {
02836           HAL_TIM_OC_DelayElapsedCallback(htim);
02837           HAL_TIM_PWM_PulseFinishedCallback(htim);
02838         }
02839         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02840       }
02841     }
02842   }
02843   /* Capture compare 2 event */
02844   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
02845   {
02846     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
02847     {
02848       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
02849       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
02850       /* Input capture event */
02851       if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
02852       {
02853         HAL_TIM_IC_CaptureCallback(htim);
02854       }
02855       /* Output compare event */
02856       else
02857       {
02858         HAL_TIM_OC_DelayElapsedCallback(htim);
02859         HAL_TIM_PWM_PulseFinishedCallback(htim);
02860       }
02861       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02862     }
02863   }
02864   /* Capture compare 3 event */
02865   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
02866   {
02867     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
02868     {
02869       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
02870       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
02871       /* Input capture event */
02872       if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
02873       {
02874         HAL_TIM_IC_CaptureCallback(htim);
02875       }
02876       /* Output compare event */
02877       else
02878       {
02879         HAL_TIM_OC_DelayElapsedCallback(htim);
02880         HAL_TIM_PWM_PulseFinishedCallback(htim);
02881       }
02882       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02883     }
02884   }
02885   /* Capture compare 4 event */
02886   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
02887   {
02888     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
02889     {
02890       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
02891       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
02892       /* Input capture event */
02893       if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
02894       {
02895         HAL_TIM_IC_CaptureCallback(htim);
02896       }
02897       /* Output compare event */
02898       else
02899       {
02900         HAL_TIM_OC_DelayElapsedCallback(htim);
02901         HAL_TIM_PWM_PulseFinishedCallback(htim);
02902       }
02903       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02904     }
02905   }
02906   /* TIM Update event */
02907   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
02908   {
02909     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
02910     {
02911       __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
02912       HAL_TIM_PeriodElapsedCallback(htim);
02913     }
02914   }
02915   /* TIM Break input event */
02916   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
02917   {
02918     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
02919     {
02920       __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
02921       HAL_TIMEx_BreakCallback(htim);
02922     }
02923   }
02924   /* TIM Break input2 event */
02925   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
02926   {
02927     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
02928     {
02929       __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
02930       HAL_TIMEx_BreakCallback(htim);
02931     }
02932   }
02933   /* TIM Trigger detection event */
02934   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
02935   {
02936     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
02937     {
02938       __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
02939       HAL_TIM_TriggerCallback(htim);
02940     }
02941   }
02942   /* TIM commutation event */
02943   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
02944   {
02945     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
02946     {
02947       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
02948       HAL_TIMEx_CommutationCallback(htim);
02949     }
02950   }
02951 }
02952
02953 /**
02954   * @}
02955   */
02956
02957 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
02958  *  @brief     Peripheral Control functions
02959  *
02960 @verbatim
02961   ==============================================================================
02962                    ##### Peripheral Control functions #####
02963   ==============================================================================
02964  [..]
02965    This section provides functions allowing to:
02966       (+) Configure The Input/Output channels for Output Compare, PWM, Input Capture
02967           or One Pulse mode.
02968       (+) Configure External Clock source.
02969       (+) Configure Complementary channels, break features and dead time.
02970       (+) Configure Master and the Slave synchronization.
02971       (+) Configure the DMA Burst Mode.
02972
02973 @endverbatim
02974   * @{
02975   */
02976
02977 /**
02978   * @brief  Initialize the TIM Output Compare Channels according to the specified
02979   *         parameters in the TIM_OC_InitTypeDef.
02980   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02981   *                the configuration information for TIM module.
02982   * @param  sConfig: TIM Output Compare configuration structure.
02983   * @param  Channel : TIM Channels to configure.
02984   *          This parameter can be one of the following values:
02985   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02986   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02987   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02988   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02989   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
02990   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
02991   * @retval HAL status
02992   */
02993 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
02994                                            TIM_OC_InitTypeDef* sConfig,
02995                                            uint32_t Channel)
02996 {
02997   /* Check the parameters */
02998   assert_param(IS_TIM_CHANNELS(Channel));
02999   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
03000   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
03001
03002   /* Process Locked */
03003   __HAL_LOCK(htim);
03004
03005   htim->State = HAL_TIM_STATE_BUSY;
03006
03007   switch (Channel)
03008   {
03009     case TIM_CHANNEL_1:
03010     {
03011       /* Check the parameters */
03012       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03013
03014      /* Configure the TIM Channel 1 in Output Compare */
03015       TIM_OC1_SetConfig(htim->Instance, sConfig);
03016     }
03017     break;
03018
03019     case TIM_CHANNEL_2:
03020     {
03021       /* Check the parameters */
03022       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03023
03024       /* Configure the TIM Channel 2 in Output Compare */
03025       TIM_OC2_SetConfig(htim->Instance, sConfig);
03026     }
03027     break;
03028
03029     case TIM_CHANNEL_3:
03030     {
03031       /* Check the parameters */
03032       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03033
03034       /* Configure the TIM Channel 3 in Output Compare */
03035       TIM_OC3_SetConfig(htim->Instance, sConfig);
03036     }
03037     break;
03038
03039     case TIM_CHANNEL_4:
03040     {
03041       /* Check the parameters */
03042       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03043
03044        /* Configure the TIM Channel 4 in Output Compare */
03045        TIM_OC4_SetConfig(htim->Instance, sConfig);
03046     }
03047     break;
03048
03049     case TIM_CHANNEL_5:
03050     {
03051       /* Check the parameters */
03052       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
03053
03054        /* Configure the TIM Channel 5 in Output Compare */
03055        TIM_OC5_SetConfig(htim->Instance, sConfig);
03056     }
03057     break;
03058
03059     case TIM_CHANNEL_6:
03060     {
03061       /* Check the parameters */
03062       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
03063
03064        /* Configure the TIM Channel 6 in Output Compare */
03065        TIM_OC6_SetConfig(htim->Instance, sConfig);
03066     }
03067     break;
03068
03069     default:
03070     break;
03071   }
03072
03073   htim->State = HAL_TIM_STATE_READY;
03074
03075   __HAL_UNLOCK(htim);
03076
03077   return HAL_OK;
03078 }
03079
03080 /**
03081   * @brief  Initialize the TIM Input Capture Channels according to the specified
03082   *         parameters in the TIM_IC_InitTypeDef.
03083   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03084   *                the configuration information for TIM module.
03085   * @param  sConfig: TIM Input Capture configuration structure.
03086   * @param  Channel : TIM Channels to be enabled.
03087   *          This parameter can be one of the following values:
03088   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03089   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03090   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
03091   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
03092   * @retval HAL status
03093   */
03094 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
03095 {
03096   /* Check the parameters */
03097   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03098   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
03099   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
03100   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
03101   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
03102
03103   /* Process Locked */
03104   __HAL_LOCK(htim);
03105
03106   htim->State = HAL_TIM_STATE_BUSY;
03107
03108   if (Channel == TIM_CHANNEL_1)
03109   {
03110     /* TI1 Configuration */
03111     TIM_TI1_SetConfig(htim->Instance,
03112                sConfig->ICPolarity,
03113                sConfig->ICSelection,
03114                sConfig->ICFilter);
03115
03116     /* Reset the IC1PSC Bits */
03117     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
03118
03119     /* Set the IC1PSC value */
03120     htim->Instance->CCMR1 |= sConfig->ICPrescaler;
03121   }
03122   else if (Channel == TIM_CHANNEL_2)
03123   {
03124     /* TI2 Configuration */
03125     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03126
03127     TIM_TI2_SetConfig(htim->Instance,
03128                       sConfig->ICPolarity,
03129                       sConfig->ICSelection,
03130                       sConfig->ICFilter);
03131
03132     /* Reset the IC2PSC Bits */
03133     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
03134
03135     /* Set the IC2PSC value */
03136     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
03137   }
03138   else if (Channel == TIM_CHANNEL_3)
03139   {
03140     /* TI3 Configuration */
03141     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03142
03143     TIM_TI3_SetConfig(htim->Instance,
03144                sConfig->ICPolarity,
03145                sConfig->ICSelection,
03146                sConfig->ICFilter);
03147
03148     /* Reset the IC3PSC Bits */
03149     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
03150
03151     /* Set the IC3PSC value */
03152     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
03153   }
03154   else
03155   {
03156     /* TI4 Configuration */
03157     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03158
03159     TIM_TI4_SetConfig(htim->Instance,
03160                sConfig->ICPolarity,
03161                sConfig->ICSelection,
03162                sConfig->ICFilter);
03163
03164     /* Reset the IC4PSC Bits */
03165     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
03166
03167     /* Set the IC4PSC value */
03168     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
03169   }
03170
03171   htim->State = HAL_TIM_STATE_READY;
03172
03173   __HAL_UNLOCK(htim);
03174
03175   return HAL_OK;
03176 }
03177
03178 /**
03179   * @brief  Initialize the TIM PWM  channels according to the specified
03180   *         parameters in the TIM_OC_InitTypeDef.
03181   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03182   *                the configuration information for TIM module.
03183   * @param  sConfig: TIM PWM configuration structure.
03184   * @param  Channel : TIM Channels to be configured.
03185   *          This parameter can be one of the following values:
03186   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03187   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03188   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
03189   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
03190   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
03191   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
03192   * @retval HAL status
03193   */
03194 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
03195                                             TIM_OC_InitTypeDef* sConfig,
03196                                             uint32_t Channel)
03197 {
03198
03199
03200   /* Check the parameters */
03201   assert_param(IS_TIM_CHANNELS(Channel));
03202   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
03203   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
03204
03205   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
03206
03207
03208
03209   /* Process Locked */
03210   __HAL_LOCK(htim);
03211
03212   htim->State = HAL_TIM_STATE_BUSY;
03213
03214   switch (Channel)
03215   {
03216     case TIM_CHANNEL_1:
03217     {
03218       /* Check the parameters */
03219       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03220
03221       /* Configure the Channel 1 in PWM mode */
03222       TIM_OC1_SetConfig(htim->Instance, sConfig);
03223
03224       /* Set the Preload enable bit for channel1 */
03225       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
03226
03227       /* Configure the Output Fast mode */
03228       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
03229       htim->Instance->CCMR1 |= sConfig->OCFastMode;
03230     }
03231     break;
03232
03233     case TIM_CHANNEL_2:
03234     {
03235       /* Check the parameters */
03236       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03237
03238       /* Configure the Channel 2 in PWM mode */
03239       TIM_OC2_SetConfig(htim->Instance, sConfig);
03240
03241       /* Set the Preload enable bit for channel2 */
03242       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
03243
03244       /* Configure the Output Fast mode */
03245       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
03246       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
03247     }
03248     break;
03249
03250     case TIM_CHANNEL_3:
03251     {
03252       /* Check the parameters */
03253       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03254
03255       /* Configure the Channel 3 in PWM mode */
03256       TIM_OC3_SetConfig(htim->Instance, sConfig);
03257
03258       /* Set the Preload enable bit for channel3 */
03259       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
03260
03261      /* Configure the Output Fast mode */
03262       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
03263       htim->Instance->CCMR2 |= sConfig->OCFastMode;
03264     }
03265     break;
03266
03267     case TIM_CHANNEL_4:
03268     {
03269       /* Check the parameters */
03270       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03271
03272       /* Configure the Channel 4 in PWM mode */
03273       TIM_OC4_SetConfig(htim->Instance, sConfig);
03274
03275       /* Set the Preload enable bit for channel4 */
03276       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
03277
03278      /* Configure the Output Fast mode */
03279       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
03280       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
03281     }
03282     break;
03283
03284     case TIM_CHANNEL_5:
03285     {
03286        /* Check the parameters */
03287       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
03288
03289      /* Configure the Channel 5 in PWM mode */
03290       TIM_OC5_SetConfig(htim->Instance, sConfig);
03291
03292       /* Set the Preload enable bit for channel5*/
03293       htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
03294
03295      /* Configure the Output Fast mode */
03296       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
03297       htim->Instance->CCMR3 |= sConfig->OCFastMode;
03298     }
03299     break;
03300
03301     case TIM_CHANNEL_6:
03302     {
03303        /* Check the parameters */
03304       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
03305
03306      /* Configure the Channel 5 in PWM mode */
03307       TIM_OC6_SetConfig(htim->Instance, sConfig);
03308
03309       /* Set the Preload enable bit for channel6 */
03310       htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
03311
03312      /* Configure the Output Fast mode */
03313       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
03314       htim->Instance->CCMR3 |= sConfig->OCFastMode << 8;
03315     }
03316     break;
03317
03318     default:
03319     break;
03320   }
03321
03322   htim->State = HAL_TIM_STATE_READY;
03323
03324   __HAL_UNLOCK(htim);
03325
03326   return HAL_OK;
03327 }
03328
03329 /**
03330   * @brief  Initialize the TIM One Pulse Channels according to the specified
03331   *         parameters in the TIM_OnePulse_InitTypeDef.
03332   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03333   *                the configuration information for TIM module.
03334   * @param  sConfig: TIM One Pulse configuration structure.
03335   * @param  OutputChannel : TIM Channels to be enabled.
03336   *          This parameter can be one of the following values:
03337   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03338   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03339   * @param  InputChannel : TIM Channels to be enabled.
03340   *          This parameter can be one of the following values:
03341   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03342   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03343   * @retval HAL status
03344   */
03345 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel)
03346 {
03347   TIM_OC_InitTypeDef temp1;
03348
03349   /* Check the parameters */
03350   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
03351   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
03352
03353   if(OutputChannel != InputChannel)
03354   {
03355     /* Process Locked */
03356     __HAL_LOCK(htim);
03357
03358     htim->State = HAL_TIM_STATE_BUSY;
03359
03360     /* Extract the Output compare configuration from sConfig structure */
03361     temp1.OCMode = sConfig->OCMode;
03362     temp1.Pulse = sConfig->Pulse;
03363     temp1.OCPolarity = sConfig->OCPolarity;
03364     temp1.OCNPolarity = sConfig->OCNPolarity;
03365     temp1.OCIdleState = sConfig->OCIdleState;
03366     temp1.OCNIdleState = sConfig->OCNIdleState;
03367
03368     switch (OutputChannel)
03369     {
03370       case TIM_CHANNEL_1:
03371       {
03372         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03373
03374         TIM_OC1_SetConfig(htim->Instance, &temp1);
03375       }
03376       break;
03377       case TIM_CHANNEL_2:
03378       {
03379         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03380
03381         TIM_OC2_SetConfig(htim->Instance, &temp1);
03382       }
03383       break;
03384       default:
03385       break;
03386     }
03387     switch (InputChannel)
03388     {
03389       case TIM_CHANNEL_1:
03390       {
03391         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03392
03393         TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
03394                         sConfig->ICSelection, sConfig->ICFilter);
03395
03396         /* Reset the IC1PSC Bits */
03397         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
03398
03399         /* Select the Trigger source */
03400         htim->Instance->SMCR &= ~TIM_SMCR_TS;
03401         htim->Instance->SMCR |= TIM_TS_TI1FP1;
03402
03403         /* Select the Slave Mode */
03404         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03405         htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
03406       }
03407       break;
03408       case TIM_CHANNEL_2:
03409       {
03410         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03411
03412         TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
03413                  sConfig->ICSelection, sConfig->ICFilter);
03414
03415         /* Reset the IC2PSC Bits */
03416         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
03417
03418         /* Select the Trigger source */
03419         htim->Instance->SMCR &= ~TIM_SMCR_TS;
03420         htim->Instance->SMCR |= TIM_TS_TI2FP2;
03421
03422         /* Select the Slave Mode */
03423         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03424         htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
03425       }
03426       break;
03427
03428       default:
03429       break;
03430     }
03431
03432     htim->State = HAL_TIM_STATE_READY;
03433
03434     __HAL_UNLOCK(htim);
03435
03436     return HAL_OK;
03437   }
03438   else
03439   {
03440     return HAL_ERROR;
03441   }
03442 }
03443
03444 /**
03445   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
03446   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03447   *                the configuration information for TIM module.
03448   * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
03449   *         This parameters can be on of the following values:
03450   *            @arg TIM_DMABASE_CR1
03451   *            @arg TIM_DMABASE_CR2
03452   *            @arg TIM_DMABASE_SMCR
03453   *            @arg TIM_DMABASE_DIER
03454   *            @arg TIM_DMABASE_SR
03455   *            @arg TIM_DMABASE_EGR
03456   *            @arg TIM_DMABASE_CCMR1
03457   *            @arg TIM_DMABASE_CCMR2
03458   *            @arg TIM_DMABASE_CCER
03459   *            @arg TIM_DMABASE_CNT
03460   *            @arg TIM_DMABASE_PSC
03461   *            @arg TIM_DMABASE_ARR
03462   *            @arg TIM_DMABASE_RCR
03463   *            @arg TIM_DMABASE_CCR1
03464   *            @arg TIM_DMABASE_CCR2
03465   *            @arg TIM_DMABASE_CCR3
03466   *            @arg TIM_DMABASE_CCR4
03467   *            @arg TIM_DMABASE_BDTR
03468   *            @arg TIM_DMABASE_DCR
03469   * @param  BurstRequestSrc: TIM DMA Request sources.
03470   *         This parameters can be on of the following values:
03471   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
03472   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
03473   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
03474   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
03475   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
03476   *            @arg TIM_DMA_COM: TIM Commutation DMA source
03477   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
03478   * @param  BurstBuffer: The Buffer address.
03479   * @param  BurstLength: DMA Burst length. This parameter can be one value
03480   *         between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
03481   * @retval HAL status
03482   */
03483 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
03484                                               uint32_t* BurstBuffer, uint32_t  BurstLength)
03485 {
03486   /* Check the parameters */
03487   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
03488   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
03489   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03490   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
03491
03492   if(htim->State == HAL_TIM_STATE_BUSY)
03493   {
03494      return HAL_BUSY;
03495   }
03496   else if(htim->State == HAL_TIM_STATE_READY)
03497   {
03498     if((BurstBuffer == 0 ) && (BurstLength > 0))
03499     {
03500       return HAL_ERROR;
03501     }
03502     else
03503     {
03504       htim->State = HAL_TIM_STATE_BUSY;
03505     }
03506   }
03507   switch(BurstRequestSrc)
03508   {
03509     case TIM_DMA_UPDATE:
03510     {
03511       /* Set the DMA Period elapsed callback */
03512       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
03513
03514       /* Set the DMA error callback */
03515       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
03516
03517       /* Enable t  he DMA Stream */
03518       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03519     }
03520     break;
03521     case TIM_DMA_CC1:
03522     {
03523       /* Set the DMA Period elapsed callback */
03524       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback =  HAL_TIM_DMADelayPulseCplt;
03525
03526       /* Set the DMA error callback */
03527       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
03528
03529       /* Enable t  he DMA Stream */
03530       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03531     }
03532     break;
03533     case TIM_DMA_CC2:
03534     {
03535       /* Set the DMA Period elapsed callback */
03536       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback =  HAL_TIM_DMADelayPulseCplt;
03537
03538       /* Set the DMA error callback */
03539       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
03540
03541       /* Enable t  he DMA Stream */
03542       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03543     }
03544     break;
03545     case TIM_DMA_CC3:
03546     {
03547       /* Set the DMA Period elapsed callback */
03548       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback =  HAL_TIM_DMADelayPulseCplt;
03549
03550       /* Set the DMA error callback */
03551       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
03552
03553       /* Enable t  he DMA Stream */
03554       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03555     }
03556     break;
03557     case TIM_DMA_CC4:
03558     {
03559       /* Set the DMA Period elapsed callback */
03560       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback =  HAL_TIM_DMADelayPulseCplt;
03561
03562       /* Set the DMA error callback */
03563       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
03564
03565       /* Enable t  he DMA Stream */
03566       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03567     }
03568     break;
03569     case TIM_DMA_COM:
03570     {
03571       /* Set the DMA Period elapsed callback */
03572       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  HAL_TIMEx_DMACommutationCplt;
03573
03574       /* Set the DMA error callback */
03575       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
03576
03577       /* Enable t  he DMA Stream */
03578       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03579     }
03580     break;
03581     case TIM_DMA_TRIGGER:
03582     {
03583       /* Set the DMA Period elapsed callback */
03584       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
03585
03586       /* Set the DMA error callback */
03587       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
03588
03589       /* Enable t  he DMA Stream */
03590       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03591     }
03592     break;
03593     default:
03594     break;
03595   }
03596    /* configure the DMA Burst Mode */
03597    htim->Instance->DCR = BurstBaseAddress | BurstLength;
03598
03599    /* Enable the TIM DMA Request */
03600    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
03601
03602    htim->State = HAL_TIM_STATE_READY;
03603
03604   /* Return function status */
03605   return HAL_OK;
03606 }
03607
03608 /**
03609   * @brief  Stops the TIM DMA Burst mode
03610   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03611   *                the configuration information for TIM module.
03612   * @param  BurstRequestSrc: TIM DMA Request sources to disable
03613   * @retval HAL status
03614   */
03615 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
03616 {
03617   /* Check the parameters */
03618   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03619
03620   /* Abort the DMA transfer (at least disable the DMA channel) */
03621   switch(BurstRequestSrc)
03622   {
03623     case TIM_DMA_UPDATE:
03624     {
03625       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
03626     }
03627     break;
03628     case TIM_DMA_CC1:
03629     {
03630       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
03631     }
03632     break;
03633     case TIM_DMA_CC2:
03634     {
03635       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
03636     }
03637     break;
03638     case TIM_DMA_CC3:
03639     {
03640       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
03641     }
03642     break;
03643     case TIM_DMA_CC4:
03644     {
03645       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
03646     }
03647     break;
03648     case TIM_DMA_COM:
03649     {
03650       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
03651     }
03652     break;
03653     case TIM_DMA_TRIGGER:
03654     {
03655       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
03656     }
03657     break;
03658     default:
03659     break;
03660   }
03661
03662   /* Disable the TIM Update DMA request */
03663   __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
03664
03665   /* Return function status */
03666   return HAL_OK;
03667 }
03668
03669 /**
03670   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
03671   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03672   *                the configuration information for TIM module.
03673   * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
03674   *         This parameters can be on of the following values:
03675   *            @arg TIM_DMABASE_CR1
03676   *            @arg TIM_DMABASE_CR2
03677   *            @arg TIM_DMABASE_SMCR
03678   *            @arg TIM_DMABASE_DIER
03679   *            @arg TIM_DMABASE_SR
03680   *            @arg TIM_DMABASE_EGR
03681   *            @arg TIM_DMABASE_CCMR1
03682   *            @arg TIM_DMABASE_CCMR2
03683   *            @arg TIM_DMABASE_CCER
03684   *            @arg TIM_DMABASE_CNT
03685   *            @arg TIM_DMABASE_PSC
03686   *            @arg TIM_DMABASE_ARR
03687   *            @arg TIM_DMABASE_RCR
03688   *            @arg TIM_DMABASE_CCR1
03689   *            @arg TIM_DMABASE_CCR2
03690   *            @arg TIM_DMABASE_CCR3
03691   *            @arg TIM_DMABASE_CCR4
03692   *            @arg TIM_DMABASE_BDTR
03693   *            @arg TIM_DMABASE_DCR
03694   * @param  BurstRequestSrc: TIM DMA Request sources.
03695   *         This parameters can be on of the following values:
03696   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
03697   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
03698   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
03699   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
03700   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
03701   *            @arg TIM_DMA_COM: TIM Commutation DMA source
03702   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
03703   * @param  BurstBuffer: The Buffer address.
03704   * @param  BurstLength: DMA Burst length. This parameter can be one value
03705   *         between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
03706   * @retval HAL status
03707   */
03708 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
03709                                              uint32_t  *BurstBuffer, uint32_t  BurstLength)
03710 {
03711   /* Check the parameters */
03712   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
03713   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
03714   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03715   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
03716
03717   if((htim->State) == (HAL_TIM_STATE_BUSY))
03718   {
03719      return HAL_BUSY;
03720   }
03721   else if((htim->State) == (HAL_TIM_STATE_READY))
03722   {
03723     if((BurstBuffer == 0 ) && (BurstLength > 0))
03724     {
03725       return HAL_ERROR;
03726     }
03727     else
03728     {
03729       htim->State = HAL_TIM_STATE_BUSY;
03730     }
03731   }
03732   switch(BurstRequestSrc)
03733   {
03734     case TIM_DMA_UPDATE:
03735     {
03736       /* Set the DMA Period elapsed callback */
03737       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
03738
03739       /* Set the DMA error callback */
03740       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
03741
03742       /* Enable t  he DMA Stream */
03743        HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03744     }
03745     break;
03746     case TIM_DMA_CC1:
03747     {
03748       /* Set the DMA Period elapsed callback */
03749       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback =  HAL_TIM_DMACaptureCplt;
03750
03751       /* Set the DMA error callback */
03752       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
03753
03754       /* Enable t  he DMA Stream */
03755       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03756     }
03757     break;
03758     case TIM_DMA_CC2:
03759     {
03760       /* Set the DMA Period elapsed callback */
03761       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback =  HAL_TIM_DMACaptureCplt;
03762
03763       /* Set the DMA error callback */
03764       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
03765
03766       /* Enable t  he DMA Stream */
03767       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03768     }
03769     break;
03770     case TIM_DMA_CC3:
03771     {
03772       /* Set the DMA Period elapsed callback */
03773       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback =  HAL_TIM_DMACaptureCplt;
03774
03775       /* Set the DMA error callback */
03776       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
03777
03778       /* Enable t  he DMA Stream */
03779       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03780     }
03781     break;
03782     case TIM_DMA_CC4:
03783     {
03784       /* Set the DMA Period elapsed callback */
03785       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback =  HAL_TIM_DMACaptureCplt;
03786
03787       /* Set the DMA error callback */
03788       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
03789
03790       /* Enable t  he DMA Stream */
03791       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03792     }
03793     break;
03794     case TIM_DMA_COM:
03795     {
03796       /* Set the DMA Period elapsed callback */
03797       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  HAL_TIMEx_DMACommutationCplt;
03798
03799       /* Set the DMA error callback */
03800       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
03801
03802       /* Enable t  he DMA Stream */
03803       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03804     }
03805     break;
03806     case TIM_DMA_TRIGGER:
03807     {
03808       /* Set the DMA Period elapsed callback */
03809       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
03810
03811       /* Set the DMA error callback */
03812       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
03813
03814       /* Enable t  he DMA Stream */
03815       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03816     }
03817     break;
03818     default:
03819     break;
03820   }
03821
03822   /* configure the DMA Burst Mode */
03823   htim->Instance->DCR = BurstBaseAddress | BurstLength;
03824
03825   /* Enable the TIM DMA Request */
03826   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
03827
03828   htim->State = HAL_TIM_STATE_READY;
03829
03830   /* Return function status */
03831   return HAL_OK;
03832 }
03833
03834 /**
03835   * @brief  Stop the DMA burst reading
03836   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03837   *                the configuration information for TIM module.
03838   * @param  BurstRequestSrc: TIM DMA Request sources to disable.
03839   * @retval HAL status
03840   */
03841 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
03842 {
03843   /* Check the parameters */
03844   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03845
03846   /* Abort the DMA transfer (at least disable the DMA channel) */
03847   switch(BurstRequestSrc)
03848   {
03849     case TIM_DMA_UPDATE:
03850     {
03851       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
03852     }
03853     break;
03854     case TIM_DMA_CC1:
03855     {
03856       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
03857     }
03858     break;
03859     case TIM_DMA_CC2:
03860     {
03861       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
03862     }
03863     break;
03864     case TIM_DMA_CC3:
03865     {
03866       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
03867     }
03868     break;
03869     case TIM_DMA_CC4:
03870     {
03871       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
03872     }
03873     break;
03874     case TIM_DMA_COM:
03875     {
03876       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
03877     }
03878     break;
03879     case TIM_DMA_TRIGGER:
03880     {
03881       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
03882     }
03883     break;
03884     default:
03885     break;
03886   }
03887
03888   /* Disable the TIM Update DMA request */
03889   __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
03890
03891   /* Return function status */
03892   return HAL_OK;
03893 }
03894
03895 /**
03896   * @brief  Generate a software event
03897   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03898   *                the configuration information for TIM module.
03899   * @param  EventSource: specifies the event source.
03900   *          This parameter can be one of the following values:
03901   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
03902   *            @arg TIM_EVENTSOURCE_CC1: TIM Capture Compare 1 Event source
03903   *            @arg TIM_EVENTSOURCE_CC2: TIM Capture Compare 2 Event source
03904   *            @arg TIM_EVENTSOURCE_CC3: TIM Capture Compare 3 Event source
03905   *            @arg TIM_EVENTSOURCE_CC4: TIM Capture Compare 4 Event source
03906   *            @arg TIM_EVENTSOURCE_COM: TIM COM event source
03907   *            @arg TIM_EVENTSOURCE_TRIGGER: TIM Trigger Event source
03908   *            @arg TIM_EVENTSOURCE_BREAK: TIM Break event source
03909   *            @arg TIM_EVENTSOURCE_BREAK2: TIM Break2 event source
03910   * @note   TIM6 and TIM7 can only generate an update event.
03911   * @note   TIM_EVENTSOURCE_COM, TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are used only with TIM1 and TIM8.
03912   * @retval HAL status
03913   */
03914
03915 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
03916 {
03917   /* Check the parameters */
03918   assert_param(IS_TIM_INSTANCE(htim->Instance));
03919   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
03920
03921   /* Process Locked */
03922   __HAL_LOCK(htim);
03923
03924   /* Change the TIM state */
03925   htim->State = HAL_TIM_STATE_BUSY;
03926
03927   /* Set the event sources */
03928   htim->Instance->EGR = EventSource;
03929
03930   /* Change the TIM state */
03931   htim->State = HAL_TIM_STATE_READY;
03932
03933   __HAL_UNLOCK(htim);
03934
03935   /* Return function status */
03936   return HAL_OK;
03937 }
03938
03939 /**
03940   * @brief  Configures the OCRef clear feature
03941   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03942   *                the configuration information for TIM module.
03943   * @param  sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
03944   *         contains the OCREF clear feature and parameters for the TIM peripheral.
03945   * @param  Channel: specifies the TIM Channel.
03946   *          This parameter can be one of the following values:
03947   *            @arg TIM_Channel_1: TIM Channel 1
03948   *            @arg TIM_Channel_2: TIM Channel 2
03949   *            @arg TIM_Channel_3: TIM Channel 3
03950   *            @arg TIM_Channel_4: TIM Channel 4
03951   *            @arg TIM_Channel_5: TIM Channel 5
03952   *            @arg TIM_Channel_6: TIM Channel 6
03953   * @retval None
03954   */
03955 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
03956                                            TIM_ClearInputConfigTypeDef *sClearInputConfig,
03957                                            uint32_t Channel)
03958 {
03959   uint32_t tmpsmcr = 0;
03960
03961   /* Check the parameters */
03962   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
03963   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
03964
03965   /* Process Locked */
03966   __HAL_LOCK(htim);
03967
03968   switch (sClearInputConfig->ClearInputSource)
03969   {
03970     case TIM_CLEARINPUTSOURCE_NONE:
03971     {
03972       /* Get the TIMx SMCR register value */
03973       tmpsmcr = htim->Instance->SMCR;
03974
03975       /* Clear the ETR Bits */
03976       tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
03977
03978       /* Set TIMx_SMCR */
03979       htim->Instance->SMCR = tmpsmcr;
03980    }
03981     break;
03982
03983     case TIM_CLEARINPUTSOURCE_ETR:
03984     {
03985       /* Check the parameters */
03986       assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
03987       assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
03988       assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
03989
03990       TIM_ETR_SetConfig(htim->Instance,
03991                         sClearInputConfig->ClearInputPrescaler,
03992                         sClearInputConfig->ClearInputPolarity,
03993                         sClearInputConfig->ClearInputFilter);
03994
03995     }
03996     break;
03997
03998   default:
03999     break;
04000   }
04001
04002   switch (Channel)
04003   {
04004     case TIM_CHANNEL_1:
04005       {
04006         if(sClearInputConfig->ClearInputState != RESET)
04007         {
04008           /* Enable the OCREF clear feature for Channel 1 */
04009           htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
04010         }
04011         else
04012         {
04013           /* Disable the OCREF clear feature for Channel 1 */
04014           htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
04015         }
04016       }
04017       break;
04018     case TIM_CHANNEL_2:
04019       {
04020         if(sClearInputConfig->ClearInputState != RESET)
04021         {
04022           /* Enable the OCREF clear feature for Channel 2 */
04023           htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
04024         }
04025         else
04026         {
04027           /* Disable the OCREF clear feature for Channel 2 */
04028           htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
04029         }
04030       }
04031     break;
04032     case TIM_CHANNEL_3:
04033       {
04034         if(sClearInputConfig->ClearInputState != RESET)
04035         {
04036           /* Enable the OCREF clear feature for Channel 3 */
04037           htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
04038         }
04039         else
04040         {
04041           /* Disable the OCREF clear feature for Channel 3 */
04042           htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
04043         }
04044       }
04045     break;
04046     case TIM_CHANNEL_4:
04047       {
04048         if(sClearInputConfig->ClearInputState != RESET)
04049         {
04050           /* Enable the OCREF clear feature for Channel 4 */
04051           htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
04052         }
04053         else
04054         {
04055           /* Disable the OCREF clear feature for Channel 4 */
04056           htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
04057         }
04058       }
04059     break;
04060     case TIM_CHANNEL_5:
04061       {
04062         if(sClearInputConfig->ClearInputState != RESET)
04063         {
04064           /* Enable the OCREF clear feature for Channel 1 */
04065           htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
04066         }
04067         else
04068         {
04069           /* Disable the OCREF clear feature for Channel 1 */
04070           htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
04071         }
04072       }
04073     break;
04074     case TIM_CHANNEL_6:
04075       {
04076         if(sClearInputConfig->ClearInputState != RESET)
04077         {
04078           /* Enable the OCREF clear feature for Channel 1 */
04079           htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
04080         }
04081         else
04082         {
04083           /* Disable the OCREF clear feature for Channel 1 */
04084           htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
04085         }
04086       }
04087     break;
04088     default:
04089     break;
04090   }
04091
04092     htim->State = HAL_TIM_STATE_READY;
04093
04094   __HAL_UNLOCK(htim);
04095
04096   return HAL_OK;
04097 }
04098
04099 /**
04100   * @brief   Configures the clock source to be used
04101   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04102   *                the configuration information for TIM module.
04103   * @param  sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
04104   *         contains the clock source information for the TIM peripheral.
04105   * @retval HAL status
04106   */
04107 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
04108 {
04109   uint32_t tmpsmcr = 0;
04110
04111   /* Process Locked */
04112   __HAL_LOCK(htim);
04113
04114   htim->State = HAL_TIM_STATE_BUSY;
04115
04116   /* Check the parameters */
04117   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
04118
04119   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
04120   tmpsmcr = htim->Instance->SMCR;
04121   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
04122   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
04123   htim->Instance->SMCR = tmpsmcr;
04124
04125   switch (sClockSourceConfig->ClockSource)
04126   {
04127   case TIM_CLOCKSOURCE_INTERNAL:
04128     {
04129       assert_param(IS_TIM_INSTANCE(htim->Instance));
04130       /* Disable slave mode to clock the prescaler directly with the internal clock */
04131       htim->Instance->SMCR &= ~TIM_SMCR_SMS;
04132     }
04133     break;
04134
04135   case TIM_CLOCKSOURCE_ETRMODE1:
04136     {
04137       /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
04138       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
04139
04140       /* Check ETR input conditioning related parameters */
04141       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
04142       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04143       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04144
04145       /* Configure the ETR Clock source */
04146       TIM_ETR_SetConfig(htim->Instance,
04147                         sClockSourceConfig->ClockPrescaler,
04148                         sClockSourceConfig->ClockPolarity,
04149                         sClockSourceConfig->ClockFilter);
04150       /* Get the TIMx SMCR register value */
04151       tmpsmcr = htim->Instance->SMCR;
04152       /* Reset the SMS and TS Bits */
04153       tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
04154       /* Select the External clock mode1 and the ETRF trigger */
04155       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
04156       /* Write to TIMx SMCR */
04157       htim->Instance->SMCR = tmpsmcr;
04158     }
04159     break;
04160
04161   case TIM_CLOCKSOURCE_ETRMODE2:
04162     {
04163       /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
04164       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
04165       /* Check ETR input conditioning related parameters */
04166       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
04167       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04168       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04169
04170       /* Configure the ETR Clock source */
04171       TIM_ETR_SetConfig(htim->Instance,
04172                         sClockSourceConfig->ClockPrescaler,
04173                         sClockSourceConfig->ClockPolarity,
04174                         sClockSourceConfig->ClockFilter);
04175       /* Enable the External clock mode2 */
04176       htim->Instance->SMCR |= TIM_SMCR_ECE;
04177     }
04178     break;
04179
04180   case TIM_CLOCKSOURCE_TI1:
04181     {
04182       /* Check whether or not the timer instance supports external clock mode 1 */
04183       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
04184
04185       /* Check TI1 input conditioning related parameters */
04186       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04187       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04188
04189       TIM_TI1_ConfigInputStage(htim->Instance,
04190                                sClockSourceConfig->ClockPolarity,
04191                                sClockSourceConfig->ClockFilter);
04192       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
04193     }
04194     break;
04195   case TIM_CLOCKSOURCE_TI2:
04196     {
04197       /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
04198       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
04199
04200       /* Check TI2 input conditioning related parameters */
04201       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04202       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04203
04204       TIM_TI2_ConfigInputStage(htim->Instance,
04205                                sClockSourceConfig->ClockPolarity,
04206                                sClockSourceConfig->ClockFilter);
04207       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
04208     }
04209     break;
04210   case TIM_CLOCKSOURCE_TI1ED:
04211     {
04212       /* Check whether or not the timer instance supports external clock mode 1 */
04213       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
04214
04215       /* Check TI1 input conditioning related parameters */
04216       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04217       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04218
04219       TIM_TI1_ConfigInputStage(htim->Instance,
04220                                sClockSourceConfig->ClockPolarity,
04221                                sClockSourceConfig->ClockFilter);
04222       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
04223     }
04224     break;
04225   case TIM_CLOCKSOURCE_ITR0:
04226     {
04227       /* Check whether or not the timer instance supports internal trigger input */
04228       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04229
04230       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
04231     }
04232     break;
04233   case TIM_CLOCKSOURCE_ITR1:
04234     {
04235       /* Check whether or not the timer instance supports internal trigger input */
04236       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04237
04238       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
04239     }
04240     break;
04241   case TIM_CLOCKSOURCE_ITR2:
04242     {
04243       /* Check whether or not the timer instance supports internal trigger input */
04244       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04245
04246       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
04247     }
04248     break;
04249   case TIM_CLOCKSOURCE_ITR3:
04250     {
04251       /* Check whether or not the timer instance supports internal trigger input */
04252       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04253
04254       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
04255     }
04256     break;
04257
04258   default:
04259     break;
04260   }
04261   htim->State = HAL_TIM_STATE_READY;
04262
04263   __HAL_UNLOCK(htim);
04264
04265   return HAL_OK;
04266 }
04267
04268 /**
04269   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
04270   *         or a XOR combination between CH1_input, CH2_input & CH3_input
04271   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04272   *                the configuration information for TIM module.
04273   * @param  TI1_Selection: Indicate whether or not channel 1 is connected to the
04274   *         output of a XOR gate.
04275   *          This parameter can be one of the following values:
04276   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
04277   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
04278   *            pins are connected to the TI1 input (XOR combination)
04279   * @retval HAL status
04280   */
04281 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
04282 {
04283   uint32_t tmpcr2 = 0;
04284
04285   /* Check the parameters */
04286   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
04287   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
04288
04289   /* Get the TIMx CR2 register value */
04290   tmpcr2 = htim->Instance->CR2;
04291
04292   /* Reset the TI1 selection */
04293   tmpcr2 &= ~TIM_CR2_TI1S;
04294
04295   /* Set the TI1 selection */
04296   tmpcr2 |= TI1_Selection;
04297
04298   /* Write to TIMxCR2 */
04299   htim->Instance->CR2 = tmpcr2;
04300
04301   return HAL_OK;
04302 }
04303
04304 /**
04305   * @brief  Configures the TIM in Slave mode
04306   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04307   *                the configuration information for TIM module.
04308   * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
04309   *         contains the selected trigger (internal trigger input, filtered
04310   *         timer input or external trigger input) and the Slave mode
04311   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
04312   * @retval HAL status
04313   */
04314 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
04315 {
04316   /* Check the parameters */
04317   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
04318   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
04319   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
04320
04321   /* Process Locked */
04322   __HAL_LOCK(htim);
04323
04324   htim->State = HAL_TIM_STATE_BUSY;
04325
04326   TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
04327
04328   /* Disable Trigger Interrupt */
04329   __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
04330
04331   /* Disable Trigger DMA request */
04332   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
04333
04334   htim->State = HAL_TIM_STATE_READY;
04335
04336   __HAL_UNLOCK(htim);
04337
04338   return HAL_OK;
04339 }
04340
04341 /**
04342   * @brief  Configures the TIM in Slave mode in interrupt mode
04343   * @param  htim: TIM handle.
04344   * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
04345   *         contains the selected trigger (internal trigger input, filtered
04346   *         timer input or external trigger input) and the Slave mode
04347   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
04348   * @retval HAL status
04349   */
04350 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
04351                                                         TIM_SlaveConfigTypeDef * sSlaveConfig)
04352 {
04353   /* Check the parameters */
04354   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
04355   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
04356   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
04357
04358   /* Process Locked */
04359   __HAL_LOCK(htim);
04360
04361   htim->State = HAL_TIM_STATE_BUSY;
04362
04363   TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
04364
04365   /* Enable Trigger Interrupt */
04366   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
04367
04368   /* Disable Trigger DMA request */
04369   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
04370
04371   htim->State = HAL_TIM_STATE_READY;
04372
04373   __HAL_UNLOCK(htim);
04374
04375   return HAL_OK;
04376 }
04377 /**
04378   * @brief  Read the captured value from Capture Compare unit
04379   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04380   *                the configuration information for TIM module.
04381   * @param  Channel : TIM Channels to be enabled.
04382   *          This parameter can be one of the following values:
04383   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
04384   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
04385   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
04386   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
04387   * @retval Captured value
04388   */
04389 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
04390 {
04391   uint32_t tmpreg = 0;
04392
04393   __HAL_LOCK(htim);
04394
04395   switch (Channel)
04396   {
04397   case TIM_CHANNEL_1:
04398     {
04399       /* Check the parameters */
04400       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04401
04402       /* Return the capture 1 value */
04403       tmpreg =  htim->Instance->CCR1;
04404
04405       break;
04406     }
04407   case TIM_CHANNEL_2:
04408     {
04409       /* Check the parameters */
04410       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04411
04412       /* Return the capture 2 value */
04413       tmpreg =   htim->Instance->CCR2;
04414
04415       break;
04416     }
04417
04418   case TIM_CHANNEL_3:
04419     {
04420       /* Check the parameters */
04421       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
04422
04423       /* Return the capture 3 value */
04424       tmpreg =   htim->Instance->CCR3;
04425
04426       break;
04427     }
04428
04429   case TIM_CHANNEL_4:
04430     {
04431       /* Check the parameters */
04432       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
04433
04434       /* Return the capture 4 value */
04435       tmpreg =   htim->Instance->CCR4;
04436
04437       break;
04438     }
04439
04440   default:
04441     break;
04442   }
04443
04444   __HAL_UNLOCK(htim);
04445   return tmpreg;
04446 }
04447
04448 /**
04449   * @}
04450   */
04451
04452 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
04453  *  @brief    TIM Callbacks functions
04454  *
04455 @verbatim
04456   ==============================================================================
04457                         ##### TIM Callbacks functions #####
04458   ==============================================================================
04459  [..]
04460    This section provides TIM callback functions:
04461    (+) TIM Period elapsed callback
04462    (+) TIM Output Compare callback
04463    (+) TIM Input capture callback
04464    (+) TIM Trigger callback
04465    (+) TIM Error callback
04466
04467 @endverbatim
04468   * @{
04469   */
04470
04471 /**
04472   * @brief  Period elapsed callback in non blocking mode
04473   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04474   *                the configuration information for TIM module.
04475   * @retval None
04476   */
04477 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
04478 {
04479   /* Prevent unused argument(s) compilation warning */
04480   UNUSED(htim);
04481
04482   /* NOTE : This function Should not be modified, when the callback is needed,
04483             the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
04484    */
04485
04486 }
04487 /**
04488   * @brief  Output Compare callback in non blocking mode
04489   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04490   *                the configuration information for TIM module.
04491   * @retval None
04492   */
04493 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
04494 {
04495   /* Prevent unused argument(s) compilation warning */
04496   UNUSED(htim);
04497
04498   /* NOTE : This function Should not be modified, when the callback is needed,
04499             the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
04500    */
04501 }
04502 /**
04503   * @brief  Input Capture callback in non blocking mode
04504   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04505   *                the configuration information for TIM module.
04506   * @retval None
04507   */
04508 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
04509 {
04510   /* Prevent unused argument(s) compilation warning */
04511   UNUSED(htim);
04512
04513   /* NOTE : This function Should not be modified, when the callback is needed,
04514             the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
04515    */
04516 }
04517
04518 /**
04519   * @brief  PWM Pulse finished callback in non blocking mode
04520   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04521   *                the configuration information for TIM module.
04522   * @retval None
04523   */
04524 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
04525 {
04526   /* Prevent unused argument(s) compilation warning */
04527   UNUSED(htim);
04528
04529   /* NOTE : This function Should not be modified, when the callback is needed,
04530             the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
04531    */
04532 }
04533
04534 /**
04535   * @brief  Hall Trigger detection callback in non blocking mode
04536   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04537   *                the configuration information for TIM module.
04538   * @retval None
04539   */
04540 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
04541 {
04542   /* Prevent unused argument(s) compilation warning */
04543   UNUSED(htim);
04544
04545   /* NOTE : This function Should not be modified, when the callback is needed,
04546             the HAL_TIM_TriggerCallback could be implemented in the user file
04547    */
04548 }
04549
04550 /**
04551   * @brief  TIM error callback in non blocking mode
04552   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04553   *                the configuration information for TIM module.
04554   * @retval None
04555   */
04556 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
04557 {
04558   /* Prevent unused argument(s) compilation warning */
04559   UNUSED(htim);
04560
04561   /* NOTE : This function Should not be modified, when the callback is needed,
04562             the HAL_TIM_ErrorCallback could be implemented in the user file
04563    */
04564 }
04565
04566 /**
04567   * @}
04568   */
04569
04570 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
04571  *  @brief   Peripheral State functions
04572  *
04573 @verbatim
04574   ==============================================================================
04575                         ##### Peripheral State functions #####
04576   ==============================================================================
04577     [..]
04578     This subsection permits to get in run-time the status of the peripheral
04579     and the data flow.
04580
04581 @endverbatim
04582   * @{
04583   */
04584
04585 /**
04586   * @brief  Return the TIM Base handle state
04587   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04588   *                the configuration information for TIM module.
04589   * @retval HAL state
04590   */
04591 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
04592 {
04593   return htim->State;
04594 }
04595
04596 /**
04597   * @brief  Return the TIM Output Compare handle state
04598   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04599   *                the configuration information for TIM module.
04600   * @retval HAL state
04601   */
04602 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
04603 {
04604   return htim->State;
04605 }
04606
04607 /**
04608   * @brief  Return the TIM PWM handle state
04609   * @param  htim: TIM handle
04610   * @retval HAL state
04611   */
04612 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
04613 {
04614   return htim->State;
04615 }
04616
04617 /**
04618   * @brief  Return the TIM Input Capture handle state
04619   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04620   *                the configuration information for TIM module.
04621   * @retval HAL state
04622   */
04623 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
04624 {
04625   return htim->State;
04626 }
04627
04628 /**
04629   * @brief  Return the TIM One Pulse Mode handle state
04630   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04631   *                the configuration information for TIM module.
04632   * @retval HAL state
04633   */
04634 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
04635 {
04636   return htim->State;
04637 }
04638
04639 /**
04640   * @brief  Return the TIM Encoder Mode state
04641   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04642   *                the configuration information for TIM module.
04643   * @retval HAL state
04644   */
04645 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
04646 {
04647   return htim->State;
04648 }
04649
04650 /**
04651   * @}
04652   */
04653
04654 /**
04655   * @brief  TIM DMA error callback
04656   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
04657   *               the configuration information for the specified DMA module.
04658   * @retval None
04659   */
04660 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
04661 {
04662   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04663
04664   htim->State= HAL_TIM_STATE_READY;
04665
04666   HAL_TIM_ErrorCallback(htim);
04667 }
04668
04669 /**
04670   * @brief  TIM DMA Delay Pulse complete callback.
04671   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
04672   *               the configuration information for the specified DMA module.
04673   * @retval None
04674   */
04675 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
04676 {
04677   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04678
04679   htim->State= HAL_TIM_STATE_READY;
04680
04681   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
04682   {
04683     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
04684   }
04685   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
04686   {
04687     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
04688   }
04689   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
04690   {
04691     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
04692   }
04693   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
04694   {
04695     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
04696   }
04697
04698   HAL_TIM_PWM_PulseFinishedCallback(htim);
04699
04700   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
04701 }
04702 /**
04703   * @brief  TIM DMA Capture complete callback.
04704   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
04705   *               the configuration information for the specified DMA module.
04706   * @retval None
04707   */
04708 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
04709 {
04710   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04711
04712   htim->State= HAL_TIM_STATE_READY;
04713
04714   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
04715   {
04716     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
04717   }
04718   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
04719   {
04720     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
04721   }
04722   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
04723   {
04724     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
04725   }
04726   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
04727   {
04728     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
04729   }
04730
04731   HAL_TIM_IC_CaptureCallback(htim);
04732
04733   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
04734 }
04735
04736 /**
04737   * @brief  TIM DMA Period Elapse complete callback.
04738   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
04739   *               the configuration information for the specified DMA module.
04740   * @retval None
04741   */
04742 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
04743 {
04744   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04745
04746   htim->State= HAL_TIM_STATE_READY;
04747
04748   HAL_TIM_PeriodElapsedCallback(htim);
04749 }
04750
04751 /**
04752   * @brief  TIM DMA Trigger callback.
04753   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
04754   *               the configuration information for the specified DMA module.
04755   * @retval None
04756   */
04757 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
04758 {
04759   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04760
04761   htim->State= HAL_TIM_STATE_READY;
04762
04763   HAL_TIM_TriggerCallback(htim);
04764 }
04765
04766 /**
04767   * @brief  Time Base configuration
04768   * @param  TIMx: TIM periheral
04769   * @param  Structure: TIM Base configuration structure
04770   * @retval None
04771   */
04772 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
04773 {
04774   uint32_t tmpcr1 = 0;
04775   tmpcr1 = TIMx->CR1;
04776
04777   /* Set TIM Time Base Unit parameters ---------------------------------------*/
04778   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
04779   {
04780     /* Select the Counter Mode */
04781     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
04782     tmpcr1 |= Structure->CounterMode;
04783   }
04784
04785   if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
04786   {
04787     /* Set the clock division */
04788     tmpcr1 &= ~TIM_CR1_CKD;
04789     tmpcr1 |= (uint32_t)Structure->ClockDivision;
04790   }
04791
04792   /* Set the auto-reload preload */
04793   MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
04794   TIMx->CR1 = tmpcr1;
04795
04796   /* Set the Autoreload value */
04797   TIMx->ARR = (uint32_t)Structure->Period ;
04798
04799   /* Set the Prescaler value */
04800   TIMx->PSC = (uint32_t)Structure->Prescaler;
04801
04802   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
04803   {
04804     /* Set the Repetition Counter value */
04805     TIMx->RCR = Structure->RepetitionCounter;
04806   }
04807
04808   /* Generate an update event to reload the Prescaler
04809      and the repetition counter(only for TIM1 and TIM8) value immediatly */
04810   TIMx->EGR = TIM_EGR_UG;
04811 }
04812
04813 /**
04814   * @brief  TIM Output Compare 1 configuration
04815   * @param  TIMx to select the TIM peripheral
04816   * @param  OC_Config: The Output configuration structure
04817   * @retval None
04818   */
04819 void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04820 {
04821   uint32_t tmpccmrx = 0;
04822   uint32_t tmpccer = 0;
04823   uint32_t tmpcr2 = 0;
04824
04825    /* Disable the Channel 1: Reset the CC1E Bit */
04826   TIMx->CCER &= ~TIM_CCER_CC1E;
04827
04828   /* Get the TIMx CCER register value */
04829   tmpccer = TIMx->CCER;
04830   /* Get the TIMx CR2 register value */
04831   tmpcr2 =  TIMx->CR2;
04832
04833   /* Get the TIMx CCMR1 register value */
04834   tmpccmrx = TIMx->CCMR1;
04835
04836   /* Reset the Output Compare Mode Bits */
04837   tmpccmrx &= ~TIM_CCMR1_OC1M;
04838   tmpccmrx &= ~TIM_CCMR1_CC1S;
04839   /* Select the Output Compare Mode */
04840   tmpccmrx |= OC_Config->OCMode;
04841
04842   /* Reset the Output Polarity level */
04843   tmpccer &= ~TIM_CCER_CC1P;
04844   /* Set the Output Compare Polarity */
04845   tmpccer |= OC_Config->OCPolarity;
04846
04847   if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
04848   {
04849     /* Check parameters */
04850     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
04851
04852     /* Reset the Output N Polarity level */
04853     tmpccer &= ~TIM_CCER_CC1NP;
04854     /* Set the Output N Polarity */
04855     tmpccer |= OC_Config->OCNPolarity;
04856     /* Reset the Output N State */
04857     tmpccer &= ~TIM_CCER_CC1NE;
04858   }
04859
04860   if(IS_TIM_BREAK_INSTANCE(TIMx))
04861   {
04862     /* Check parameters */
04863     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
04864     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
04865
04866     /* Reset the Output Compare and Output Compare N IDLE State */
04867     tmpcr2 &= ~TIM_CR2_OIS1;
04868     tmpcr2 &= ~TIM_CR2_OIS1N;
04869     /* Set the Output Idle state */
04870     tmpcr2 |= OC_Config->OCIdleState;
04871     /* Set the Output N Idle state */
04872     tmpcr2 |= OC_Config->OCNIdleState;
04873   }
04874   /* Write to TIMx CR2 */
04875   TIMx->CR2 = tmpcr2;
04876
04877   /* Write to TIMx CCMR1 */
04878   TIMx->CCMR1 = tmpccmrx;
04879
04880   /* Set the Capture Compare Register value */
04881   TIMx->CCR1 = OC_Config->Pulse;
04882
04883   /* Write to TIMx CCER */
04884   TIMx->CCER = tmpccer;
04885 }
04886
04887 /**
04888   * @brief  TIM Output Compare 2 configuration
04889   * @param  TIMx to select the TIM peripheral
04890   * @param  OC_Config: The Output configuration structure
04891   * @retval None
04892   */
04893 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04894 {
04895   uint32_t tmpccmrx = 0;
04896   uint32_t tmpccer = 0;
04897   uint32_t tmpcr2 = 0;
04898
04899   /* Disable the Channel 2: Reset the CC2E Bit */
04900   TIMx->CCER &= ~TIM_CCER_CC2E;
04901
04902   /* Get the TIMx CCER register value */
04903   tmpccer = TIMx->CCER;
04904   /* Get the TIMx CR2 register value */
04905   tmpcr2 =  TIMx->CR2;
04906
04907   /* Get the TIMx CCMR1 register value */
04908   tmpccmrx = TIMx->CCMR1;
04909
04910   /* Reset the Output Compare mode and Capture/Compare selection Bits */
04911   tmpccmrx &= ~TIM_CCMR1_OC2M;
04912   tmpccmrx &= ~TIM_CCMR1_CC2S;
04913
04914   /* Select the Output Compare Mode */
04915   tmpccmrx |= (OC_Config->OCMode << 8);
04916
04917   /* Reset the Output Polarity level */
04918   tmpccer &= ~TIM_CCER_CC2P;
04919   /* Set the Output Compare Polarity */
04920   tmpccer |= (OC_Config->OCPolarity << 4);
04921
04922   if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
04923   {
04924     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
04925     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
04926
04927     /* Reset the Output N Polarity level */
04928     tmpccer &= ~TIM_CCER_CC2NP;
04929     /* Set the Output N Polarity */
04930     tmpccer |= (OC_Config->OCNPolarity << 4);
04931     /* Reset the Output N State */
04932     tmpccer &= ~TIM_CCER_CC2NE;
04933
04934   }
04935
04936   if(IS_TIM_BREAK_INSTANCE(TIMx))
04937   {
04938     /* Check parameters */
04939     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
04940     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
04941
04942     /* Reset the Output Compare and Output Compare N IDLE State */
04943     tmpcr2 &= ~TIM_CR2_OIS2;
04944     tmpcr2 &= ~TIM_CR2_OIS2N;
04945     /* Set the Output Idle state */
04946     tmpcr2 |= (OC_Config->OCIdleState << 2);
04947     /* Set the Output N Idle state */
04948     tmpcr2 |= (OC_Config->OCNIdleState << 2);
04949   }
04950
04951   /* Write to TIMx CR2 */
04952   TIMx->CR2 = tmpcr2;
04953
04954   /* Write to TIMx CCMR1 */
04955   TIMx->CCMR1 = tmpccmrx;
04956
04957   /* Set the Capture Compare Register value */
04958   TIMx->CCR2 = OC_Config->Pulse;
04959
04960   /* Write to TIMx CCER */
04961   TIMx->CCER = tmpccer;
04962 }
04963
04964 /**
04965   * @brief  TIM Output Compare 3 configuration
04966   * @param  TIMx to select the TIM peripheral
04967   * @param  OC_Config: The output configuration structure
04968   * @retval None
04969   */
04970 void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04971 {
04972   uint32_t tmpccmrx = 0;
04973   uint32_t tmpccer = 0;
04974   uint32_t tmpcr2 = 0;
04975
04976   /* Disable the Channel 3: Reset the CC2E Bit */
04977   TIMx->CCER &= ~TIM_CCER_CC3E;
04978
04979   /* Get the TIMx CCER register value */
04980   tmpccer = TIMx->CCER;
04981   /* Get the TIMx CR2 register value */
04982   tmpcr2 =  TIMx->CR2;
04983
04984   /* Get the TIMx CCMR2 register value */
04985   tmpccmrx = TIMx->CCMR2;
04986
04987   /* Reset the Output Compare mode and Capture/Compare selection Bits */
04988   tmpccmrx &= ~TIM_CCMR2_OC3M;
04989   tmpccmrx &= ~TIM_CCMR2_CC3S;
04990   /* Select the Output Compare Mode */
04991   tmpccmrx |= OC_Config->OCMode;
04992
04993   /* Reset the Output Polarity level */
04994   tmpccer &= ~TIM_CCER_CC3P;
04995   /* Set the Output Compare Polarity */
04996   tmpccer |= (OC_Config->OCPolarity << 8);
04997
04998   if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
04999   {
05000     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
05001     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
05002
05003     /* Reset the Output N Polarity level */
05004     tmpccer &= ~TIM_CCER_CC3NP;
05005     /* Set the Output N Polarity */
05006     tmpccer |= (OC_Config->OCNPolarity << 8);
05007     /* Reset the Output N State */
05008     tmpccer &= ~TIM_CCER_CC3NE;
05009   }
05010
05011   if(IS_TIM_BREAK_INSTANCE(TIMx))
05012   {
05013     /* Check parameters */
05014     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
05015     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
05016
05017     /* Reset the Output Compare and Output Compare N IDLE State */
05018     tmpcr2 &= ~TIM_CR2_OIS3;
05019     tmpcr2 &= ~TIM_CR2_OIS3N;
05020     /* Set the Output Idle state */
05021     tmpcr2 |= (OC_Config->OCIdleState << 4);
05022     /* Set the Output N Idle state */
05023     tmpcr2 |= (OC_Config->OCNIdleState << 4);
05024   }
05025
05026   /* Write to TIMx CR2 */
05027   TIMx->CR2 = tmpcr2;
05028
05029   /* Write to TIMx CCMR2 */
05030   TIMx->CCMR2 = tmpccmrx;
05031
05032   /* Set the Capture Compare Register value */
05033   TIMx->CCR3 = OC_Config->Pulse;
05034
05035   /* Write to TIMx CCER */
05036   TIMx->CCER = tmpccer;
05037 }
05038
05039 /**
05040   * @brief  TIM Output Compare 4 configuration
05041   * @param  TIMx to select the TIM peripheral
05042   * @param  OC_Config: The Output configuration structure
05043   * @retval None
05044   */
05045 void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
05046 {
05047   uint32_t tmpccmrx = 0;
05048   uint32_t tmpccer = 0;
05049   uint32_t tmpcr2 = 0;
05050
05051   /* Disable the Channel 4: Reset the CC4E Bit */
05052   TIMx->CCER &= ~TIM_CCER_CC4E;
05053
05054   /* Get the TIMx CCER register value */
05055   tmpccer = TIMx->CCER;
05056   /* Get the TIMx CR2 register value */
05057   tmpcr2 =  TIMx->CR2;
05058
05059   /* Get the TIMx CCMR2 register value */
05060   tmpccmrx = TIMx->CCMR2;
05061
05062   /* Reset the Output Compare mode and Capture/Compare selection Bits */
05063   tmpccmrx &= ~TIM_CCMR2_OC4M;
05064   tmpccmrx &= ~TIM_CCMR2_CC4S;
05065
05066   /* Select the Output Compare Mode */
05067   tmpccmrx |= (OC_Config->OCMode << 8);
05068
05069   /* Reset the Output Polarity level */
05070   tmpccer &= ~TIM_CCER_CC4P;
05071   /* Set the Output Compare Polarity */
05072   tmpccer |= (OC_Config->OCPolarity << 12);
05073
05074   if(IS_TIM_BREAK_INSTANCE(TIMx))
05075   {
05076     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
05077
05078    /* Reset the Output Compare IDLE State */
05079     tmpcr2 &= ~TIM_CR2_OIS4;
05080     /* Set the Output Idle state */
05081     tmpcr2 |= (OC_Config->OCIdleState << 6);
05082   }
05083
05084   /* Write to TIMx CR2 */
05085   TIMx->CR2 = tmpcr2;
05086
05087   /* Write to TIMx CCMR2 */
05088   TIMx->CCMR2 = tmpccmrx;
05089
05090   /* Set the Capture Compare Register value */
05091   TIMx->CCR4 = OC_Config->Pulse;
05092
05093   /* Write to TIMx CCER */
05094   TIMx->CCER = tmpccer;
05095 }
05096
05097 /**
05098   * @brief  TIM Output Compare 5 configuration
05099   * @param  TIMx to select the TIM peripheral
05100   * @param  OC_Config: The Output configuration structure
05101   * @retval None
05102   */
05103 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
05104 {
05105   uint32_t tmpccmrx = 0;
05106   uint32_t tmpccer = 0;
05107   uint32_t tmpcr2 = 0;
05108
05109   /* Disable the output: Reset the CCxE Bit */
05110   TIMx->CCER &= ~TIM_CCER_CC5E;
05111
05112   /* Get the TIMx CCER register value */
05113   tmpccer = TIMx->CCER;
05114   /* Get the TIMx CR2 register value */
05115   tmpcr2 =  TIMx->CR2;
05116   /* Get the TIMx CCMR1 register value */
05117   tmpccmrx = TIMx->CCMR3;
05118
05119   /* Reset the Output Compare Mode Bits */
05120   tmpccmrx &= ~(TIM_CCMR3_OC5M);
05121   /* Select the Output Compare Mode */
05122   tmpccmrx |= OC_Config->OCMode;
05123
05124   /* Reset the Output Polarity level */
05125   tmpccer &= ~TIM_CCER_CC5P;
05126   /* Set the Output Compare Polarity */
05127   tmpccer |= (OC_Config->OCPolarity << 16);
05128
05129   if(IS_TIM_BREAK_INSTANCE(TIMx))
05130   {
05131     /* Reset the Output Compare IDLE State */
05132     tmpcr2 &= ~TIM_CR2_OIS5;
05133     /* Set the Output Idle state */
05134     tmpcr2 |= (OC_Config->OCIdleState << 8);
05135   }
05136   /* Write to TIMx CR2 */
05137   TIMx->CR2 = tmpcr2;
05138
05139   /* Write to TIMx CCMR3 */
05140   TIMx->CCMR3 = tmpccmrx;
05141
05142   /* Set the Capture Compare Register value */
05143   TIMx->CCR5 = OC_Config->Pulse;
05144
05145   /* Write to TIMx CCER */
05146   TIMx->CCER = tmpccer;
05147 }
05148
05149 /**
05150   * @brief  TIM Output Compare 6 configuration
05151   * @param  TIMx to select the TIM peripheral
05152   * @param  OC_Config: The Output configuration structure
05153   * @retval None
05154   */
05155 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
05156 {
05157   uint32_t tmpccmrx = 0;
05158   uint32_t tmpccer = 0;
05159   uint32_t tmpcr2 = 0;
05160
05161   /* Disable the output: Reset the CCxE Bit */
05162   TIMx->CCER &= ~TIM_CCER_CC6E;
05163
05164   /* Get the TIMx CCER register value */
05165   tmpccer = TIMx->CCER;
05166   /* Get the TIMx CR2 register value */
05167   tmpcr2 =  TIMx->CR2;
05168   /* Get the TIMx CCMR1 register value */
05169   tmpccmrx = TIMx->CCMR3;
05170
05171   /* Reset the Output Compare Mode Bits */
05172   tmpccmrx &= ~(TIM_CCMR3_OC6M);
05173   /* Select the Output Compare Mode */
05174   tmpccmrx |= (OC_Config->OCMode << 8);
05175
05176   /* Reset the Output Polarity level */
05177   tmpccer &= (uint32_t)~TIM_CCER_CC6P;
05178   /* Set the Output Compare Polarity */
05179   tmpccer |= (OC_Config->OCPolarity << 20);
05180
05181   if(IS_TIM_BREAK_INSTANCE(TIMx))
05182   {
05183     /* Reset the Output Compare IDLE State */
05184     tmpcr2 &= ~TIM_CR2_OIS6;
05185     /* Set the Output Idle state */
05186     tmpcr2 |= (OC_Config->OCIdleState << 10);
05187   }
05188
05189   /* Write to TIMx CR2 */
05190   TIMx->CR2 = tmpcr2;
05191
05192   /* Write to TIMx CCMR3 */
05193   TIMx->CCMR3 = tmpccmrx;
05194
05195   /* Set the Capture Compare Register value */
05196   TIMx->CCR6 = OC_Config->Pulse;
05197
05198   /* Write to TIMx CCER */
05199   TIMx->CCER = tmpccer;
05200 }
05201
05202 /**
05203   * @brief  TIM Slave mode configuration
05204   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
05205   *                the configuration information for TIM module.
05206   * @param  sSlaveConfig: The slave configuration structure
05207   * @retval None
05208   */
05209 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
05210                                      TIM_SlaveConfigTypeDef * sSlaveConfig)
05211 {
05212   uint32_t tmpsmcr = 0;
05213   uint32_t tmpccmr1 = 0;
05214   uint32_t tmpccer = 0;
05215
05216   /* Get the TIMx SMCR register value */
05217   tmpsmcr = htim->Instance->SMCR;
05218
05219   /* Reset the Trigger Selection Bits */
05220   tmpsmcr &= ~TIM_SMCR_TS;
05221   /* Set the Input Trigger source */
05222   tmpsmcr |= sSlaveConfig->InputTrigger;
05223
05224   /* Reset the slave mode Bits */
05225   tmpsmcr &= ~TIM_SMCR_SMS;
05226   /* Set the slave mode */
05227   tmpsmcr |= sSlaveConfig->SlaveMode;
05228
05229   /* Write to TIMx SMCR */
05230   htim->Instance->SMCR = tmpsmcr;
05231
05232   /* Configure the trigger prescaler, filter, and polarity */
05233   switch (sSlaveConfig->InputTrigger)
05234   {
05235     case TIM_TS_ETRF:
05236     {
05237       /* Check the parameters */
05238       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
05239       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
05240       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
05241       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
05242       /* Configure the ETR Trigger source */
05243       TIM_ETR_SetConfig(htim->Instance,
05244                         sSlaveConfig->TriggerPrescaler,
05245                         sSlaveConfig->TriggerPolarity,
05246                         sSlaveConfig->TriggerFilter);
05247     }
05248     break;
05249
05250     case TIM_TS_TI1F_ED:
05251     {
05252       /* Check the parameters */
05253       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
05254       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
05255
05256       /* Disable the Channel 1: Reset the CC1E Bit */
05257       tmpccer = htim->Instance->CCER;
05258       htim->Instance->CCER &= ~TIM_CCER_CC1E;
05259       tmpccmr1 = htim->Instance->CCMR1;
05260
05261       /* Set the filter */
05262       tmpccmr1 &= ~TIM_CCMR1_IC1F;
05263       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
05264
05265       /* Write to TIMx CCMR1 and CCER registers */
05266       htim->Instance->CCMR1 = tmpccmr1;
05267       htim->Instance->CCER = tmpccer;
05268
05269     }
05270     break;
05271
05272     case TIM_TS_TI1FP1:
05273     {
05274       /* Check the parameters */
05275       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
05276       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
05277       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
05278
05279       /* Configure TI1 Filter and Polarity */
05280       TIM_TI1_ConfigInputStage(htim->Instance,
05281                                sSlaveConfig->TriggerPolarity,
05282                                sSlaveConfig->TriggerFilter);
05283     }
05284     break;
05285
05286     case TIM_TS_TI2FP2:
05287     {
05288       /* Check the parameters */
05289       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05290       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
05291       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
05292
05293       /* Configure TI2 Filter and Polarity */
05294       TIM_TI2_ConfigInputStage(htim->Instance,
05295                                 sSlaveConfig->TriggerPolarity,
05296                                 sSlaveConfig->TriggerFilter);
05297     }
05298     break;
05299
05300     case TIM_TS_ITR0:
05301     {
05302       /* Check the parameter */
05303       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05304     }
05305     break;
05306
05307     case TIM_TS_ITR1:
05308     {
05309       /* Check the parameter */
05310       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05311     }
05312     break;
05313
05314     case TIM_TS_ITR2:
05315     {
05316       /* Check the parameter */
05317       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05318     }
05319     break;
05320
05321     case TIM_TS_ITR3:
05322     {
05323       /* Check the parameter */
05324       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05325     }
05326     break;
05327
05328     default:
05329     break;
05330   }
05331 }
05332
05333 /**
05334   * @brief  Configure the TI1 as Input.
05335   * @param  TIMx to select the TIM peripheral.
05336   * @param  TIM_ICPolarity : The Input Polarity.
05337   *          This parameter can be one of the following values:
05338   *            @arg TIM_ICPolarity_Rising
05339   *            @arg TIM_ICPolarity_Falling
05340   *            @arg TIM_ICPolarity_BothEdge
05341   * @param  TIM_ICSelection: specifies the input to be used.
05342   *          This parameter can be one of the following values:
05343   *            @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
05344   *            @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
05345   *            @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
05346   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05347   *          This parameter must be a value between 0x00 and 0x0F.
05348   * @retval None
05349   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
05350   *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
05351   *        protected against un-initialized filter and polarity values.
05352   */
05353 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05354                        uint32_t TIM_ICFilter)
05355 {
05356   uint32_t tmpccmr1 = 0;
05357   uint32_t tmpccer = 0;
05358
05359   /* Disable the Channel 1: Reset the CC1E Bit */
05360   TIMx->CCER &= ~TIM_CCER_CC1E;
05361   tmpccmr1 = TIMx->CCMR1;
05362   tmpccer = TIMx->CCER;
05363
05364   /* Select the Input */
05365   if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
05366   {
05367     tmpccmr1 &= ~TIM_CCMR1_CC1S;
05368     tmpccmr1 |= TIM_ICSelection;
05369   }
05370   else
05371   {
05372     tmpccmr1 |= TIM_CCMR1_CC1S_0;
05373   }
05374
05375   /* Set the filter */
05376   tmpccmr1 &= ~TIM_CCMR1_IC1F;
05377   tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
05378
05379   /* Select the Polarity and set the CC1E Bit */
05380   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
05381   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
05382
05383   /* Write to TIMx CCMR1 and CCER registers */
05384   TIMx->CCMR1 = tmpccmr1;
05385   TIMx->CCER = tmpccer;
05386 }
05387
05388 /**
05389   * @brief  Configure the Polarity and Filter for TI1.
05390   * @param  TIMx to select the TIM peripheral.
05391   * @param  TIM_ICPolarity : The Input Polarity.
05392   *          This parameter can be one of the following values:
05393   *            @arg TIM_ICPolarity_Rising
05394   *            @arg TIM_ICPolarity_Falling
05395   *            @arg TIM_ICPolarity_BothEdge
05396   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05397   *          This parameter must be a value between 0x00 and 0x0F.
05398   * @retval None
05399   */
05400 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
05401 {
05402   uint32_t tmpccmr1 = 0;
05403   uint32_t tmpccer = 0;
05404
05405   /* Disable the Channel 1: Reset the CC1E Bit */
05406   tmpccer = TIMx->CCER;
05407   TIMx->CCER &= ~TIM_CCER_CC1E;
05408   tmpccmr1 = TIMx->CCMR1;
05409
05410   /* Set the filter */
05411   tmpccmr1 &= ~TIM_CCMR1_IC1F;
05412   tmpccmr1 |= (TIM_ICFilter << 4);
05413
05414   /* Select the Polarity and set the CC1E Bit */
05415   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
05416   tmpccer |= TIM_ICPolarity;
05417
05418   /* Write to TIMx CCMR1 and CCER registers */
05419   TIMx->CCMR1 = tmpccmr1;
05420   TIMx->CCER = tmpccer;
05421 }
05422
05423 /**
05424   * @brief  Configure the TI2 as Input.
05425   * @param  TIMx to select the TIM peripheral
05426   * @param  TIM_ICPolarity : The Input Polarity.
05427   *          This parameter can be one of the following values:
05428   *            @arg TIM_ICPolarity_Rising
05429   *            @arg TIM_ICPolarity_Falling
05430   *            @arg TIM_ICPolarity_BothEdge
05431   * @param  TIM_ICSelection: specifies the input to be used.
05432   *          This parameter can be one of the following values:
05433   *            @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
05434   *            @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
05435   *            @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
05436   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05437   *          This parameter must be a value between 0x00 and 0x0F.
05438   * @retval None
05439   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
05440   *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
05441   *        protected against un-initialized filter and polarity values.
05442   */
05443 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05444                        uint32_t TIM_ICFilter)
05445 {
05446   uint32_t tmpccmr1 = 0;
05447   uint32_t tmpccer = 0;
05448
05449   /* Disable the Channel 2: Reset the CC2E Bit */
05450   TIMx->CCER &= ~TIM_CCER_CC2E;
05451   tmpccmr1 = TIMx->CCMR1;
05452   tmpccer = TIMx->CCER;
05453
05454   /* Select the Input */
05455   tmpccmr1 &= ~TIM_CCMR1_CC2S;
05456   tmpccmr1 |= (TIM_ICSelection << 8);
05457
05458   /* Set the filter */
05459   tmpccmr1 &= ~TIM_CCMR1_IC2F;
05460   tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
05461
05462   /* Select the Polarity and set the CC2E Bit */
05463   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
05464   tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
05465
05466   /* Write to TIMx CCMR1 and CCER registers */
05467   TIMx->CCMR1 = tmpccmr1 ;
05468   TIMx->CCER = tmpccer;
05469 }
05470
05471 /**
05472   * @brief  Configure the Polarity and Filter for TI2.
05473   * @param  TIMx to select the TIM peripheral.
05474   * @param  TIM_ICPolarity : The Input Polarity.
05475   *          This parameter can be one of the following values:
05476   *            @arg TIM_ICPolarity_Rising
05477   *            @arg TIM_ICPolarity_Falling
05478   *            @arg TIM_ICPolarity_BothEdge
05479   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05480   *          This parameter must be a value between 0x00 and 0x0F.
05481   * @retval None
05482   */
05483 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
05484 {
05485   uint32_t tmpccmr1 = 0;
05486   uint32_t tmpccer = 0;
05487
05488   /* Disable the Channel 2: Reset the CC2E Bit */
05489   TIMx->CCER &= ~TIM_CCER_CC2E;
05490   tmpccmr1 = TIMx->CCMR1;
05491   tmpccer = TIMx->CCER;
05492
05493   /* Set the filter */
05494   tmpccmr1 &= ~TIM_CCMR1_IC2F;
05495   tmpccmr1 |= (TIM_ICFilter << 12);
05496
05497   /* Select the Polarity and set the CC2E Bit */
05498   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
05499   tmpccer |= (TIM_ICPolarity << 4);
05500
05501   /* Write to TIMx CCMR1 and CCER registers */
05502   TIMx->CCMR1 = tmpccmr1 ;
05503   TIMx->CCER = tmpccer;
05504 }
05505
05506 /**
05507   * @brief  Configure the TI3 as Input.
05508   * @param  TIMx to select the TIM peripheral
05509   * @param  TIM_ICPolarity : The Input Polarity.
05510   *          This parameter can be one of the following values:
05511   *            @arg TIM_ICPolarity_Rising
05512   *            @arg TIM_ICPolarity_Falling
05513   *            @arg TIM_ICPolarity_BothEdge
05514   * @param  TIM_ICSelection: specifies the input to be used.
05515   *          This parameter can be one of the following values:
05516   *            @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
05517   *            @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
05518   *            @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
05519   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05520   *          This parameter must be a value between 0x00 and 0x0F.
05521   * @retval None
05522   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
05523   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
05524   *        protected against un-initialized filter and polarity values.
05525   */
05526 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05527                        uint32_t TIM_ICFilter)
05528 {
05529   uint32_t tmpccmr2 = 0;
05530   uint32_t tmpccer = 0;
05531
05532   /* Disable the Channel 3: Reset the CC3E Bit */
05533   TIMx->CCER &= ~TIM_CCER_CC3E;
05534   tmpccmr2 = TIMx->CCMR2;
05535   tmpccer = TIMx->CCER;
05536
05537   /* Select the Input */
05538   tmpccmr2 &= ~TIM_CCMR2_CC3S;
05539   tmpccmr2 |= TIM_ICSelection;
05540
05541   /* Set the filter */
05542   tmpccmr2 &= ~TIM_CCMR2_IC3F;
05543   tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
05544
05545   /* Select the Polarity and set the CC3E Bit */
05546   tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
05547   tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
05548
05549   /* Write to TIMx CCMR2 and CCER registers */
05550   TIMx->CCMR2 = tmpccmr2;
05551   TIMx->CCER = tmpccer;
05552 }
05553
05554 /**
05555   * @brief  Configure the TI4 as Input.
05556   * @param  TIMx to select the TIM peripheral
05557   * @param  TIM_ICPolarity : The Input Polarity.
05558   *          This parameter can be one of the following values:
05559   *            @arg TIM_ICPolarity_Rising
05560   *            @arg TIM_ICPolarity_Falling
05561   *            @arg TIM_ICPolarity_BothEdge
05562   * @param  TIM_ICSelection: specifies the input to be used.
05563   *          This parameter can be one of the following values:
05564   *            @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
05565   *            @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
05566   *            @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
05567   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05568   *          This parameter must be a value between 0x00 and 0x0F.
05569   * @retval None
05570   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
05571   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
05572   *        protected against un-initialized filter and polarity values.
05573   */
05574 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05575                        uint32_t TIM_ICFilter)
05576 {
05577   uint32_t tmpccmr2 = 0;
05578   uint32_t tmpccer = 0;
05579
05580   /* Disable the Channel 4: Reset the CC4E Bit */
05581   TIMx->CCER &= ~TIM_CCER_CC4E;
05582   tmpccmr2 = TIMx->CCMR2;
05583   tmpccer = TIMx->CCER;
05584
05585   /* Select the Input */
05586   tmpccmr2 &= ~TIM_CCMR2_CC4S;
05587   tmpccmr2 |= (TIM_ICSelection << 8);
05588
05589   /* Set the filter */
05590   tmpccmr2 &= ~TIM_CCMR2_IC4F;
05591   tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
05592
05593   /* Select the Polarity and set the CC4E Bit */
05594   tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
05595   tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
05596
05597   /* Write to TIMx CCMR2 and CCER registers */
05598   TIMx->CCMR2 = tmpccmr2;
05599   TIMx->CCER = tmpccer ;
05600 }
05601
05602 /**
05603   * @brief  Selects the Input Trigger source
05604   * @param  TIMx to select the TIM peripheral
05605   * @param  InputTriggerSource: The Input Trigger source.
05606   *          This parameter can be one of the following values:
05607   *            @arg TIM_TS_ITR0: Internal Trigger 0
05608   *            @arg TIM_TS_ITR1: Internal Trigger 1
05609   *            @arg TIM_TS_ITR2: Internal Trigger 2
05610   *            @arg TIM_TS_ITR3: Internal Trigger 3
05611   *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
05612   *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
05613   *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
05614   *            @arg TIM_TS_ETRF: External Trigger input
05615   * @retval None
05616   */
05617 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
05618 {
05619   uint32_t tmpsmcr = 0;
05620
05621    /* Get the TIMx SMCR register value */
05622    tmpsmcr = TIMx->SMCR;
05623    /* Reset the TS Bits */
05624    tmpsmcr &= ~TIM_SMCR_TS;
05625    /* Set the Input Trigger source and the slave mode*/
05626    tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
05627    /* Write to TIMx SMCR */
05628    TIMx->SMCR = tmpsmcr;
05629 }
05630 /**
05631   * @brief  Configures the TIMx External Trigger (ETR).
05632   * @param  TIMx to select the TIM peripheral
05633   * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
05634   *          This parameter can be one of the following values:
05635   *            @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
05636   *            @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
05637   *            @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
05638   *            @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
05639   * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
05640   *          This parameter can be one of the following values:
05641   *            @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
05642   *            @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
05643   * @param  ExtTRGFilter: External Trigger Filter.
05644   *          This parameter must be a value between 0x00 and 0x0F
05645   * @retval None
05646   */
05647 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
05648                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
05649 {
05650   uint32_t tmpsmcr = 0;
05651
05652   tmpsmcr = TIMx->SMCR;
05653
05654   /* Reset the ETR Bits */
05655   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
05656
05657   /* Set the Prescaler, the Filter value and the Polarity */
05658   tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
05659
05660   /* Write to TIMx SMCR */
05661   TIMx->SMCR = tmpsmcr;
05662 }
05663
05664 /**
05665   * @brief  Enables or disables the TIM Capture Compare Channel x.
05666   * @param  TIMx to select the TIM peripheral
05667   * @param  Channel: specifies the TIM Channel
05668   *          This parameter can be one of the following values:
05669   *            @arg TIM_Channel_1: TIM Channel 1
05670   *            @arg TIM_Channel_2: TIM Channel 2
05671   *            @arg TIM_Channel_3: TIM Channel 3
05672   *            @arg TIM_Channel_4: TIM Channel 4
05673   * @param  ChannelState: specifies the TIM Channel CCxE bit new state.
05674   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
05675   * @retval None
05676   */
05677 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
05678 {
05679   uint32_t tmp = 0;
05680
05681   /* Check the parameters */
05682   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
05683   assert_param(IS_TIM_CHANNELS(Channel));
05684
05685   tmp = TIM_CCER_CC1E << Channel;
05686
05687   /* Reset the CCxE Bit */
05688   TIMx->CCER &= ~tmp;
05689
05690   /* Set or reset the CCxE Bit */
05691   TIMx->CCER |=  (uint32_t)(ChannelState << Channel);
05692 }
05693
05694 /**
05695   * @}
05696   */
05697 #endif /* HAL_TIM_MODULE_ENABLED */
05698 /**
05699   * @}
05700   */
05701
05702 /**
05703   * @}
05704   */
05705
05706 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_tim.h Source File

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stm32h7xx_hal_tim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_tim.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of TIM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_TIM_H
00040 #define __STM32H7xx_HAL_TIM_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup TIM
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup TIM_Exported_Types TIM Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  TIM Time base Configuration Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00068                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00069
00070   uint32_t CounterMode;       /*!< Specifies the counter mode.
00071                                    This parameter can be a value of @ref TIM_Counter_Mode */
00072
00073   uint32_t Period;            /*!< Specifies the period value to be loaded into the active
00074                                    Auto-Reload Register at the next update event.
00075                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
00076
00077   uint32_t ClockDivision;     /*!< Specifies the clock division.
00078                                    This parameter can be a value of @ref TIM_ClockDivision */
00079
00080   uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR down-counter
00081                                     reaches zero, an update event is generated and counting restarts
00082                                     from the RCR value (N).
00083                                     This means in PWM mode that (N+1) corresponds to:
00084                                         - the number of PWM periods in edge-aligned mode
00085                                         - the number of half PWM period in center-aligned mode
00086                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
00087                                      @note This parameter is valid only for TIM1 and TIM8. */
00088   uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
00089                                    This parameter can be a value of @ref TIM_AutoReloadPreload */
00090 } TIM_Base_InitTypeDef;
00091
00092 /**
00093   * @brief  TIM Output Compare Configuration Structure definition
00094   */
00095 typedef struct
00096 {
00097   uint32_t OCMode;        /*!< Specifies the TIM mode.
00098                                This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
00099
00100   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00101                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00102
00103   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00104                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00105
00106   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00107                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00108                                @note This parameter is valid only for TIM1 and TIM8. */
00109
00110   uint32_t OCFastMode;   /*!< Specifies the Fast mode state.
00111                                This parameter can be a value of @ref TIM_Output_Fast_State
00112                                @note This parameter is valid only in PWM1 and PWM2 mode. */
00113
00114
00115   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00116                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00117                                @note This parameter is valid only for TIM1 and TIM8. */
00118
00119   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00120                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00121                                @note This parameter is valid only for TIM1 and TIM8. */
00122 } TIM_OC_InitTypeDef;
00123
00124 /**
00125   * @brief  TIM One Pulse Mode Configuration Structure definition
00126   */
00127 typedef struct
00128 {
00129   uint32_t OCMode;        /*!< Specifies the TIM mode.
00130                                This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
00131
00132   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00133                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00134
00135   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00136                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00137
00138   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00139                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00140                                @note This parameter is valid only for TIM1 and TIM8. */
00141
00142   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00143                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00144                                @note This parameter is valid only for TIM1 and TIM8. */
00145
00146   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00147                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00148                                @note This parameter is valid only for TIM1 and TIM8. */
00149
00150   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
00151                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00152
00153   uint32_t ICSelection;   /*!< Specifies the input.
00154                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00155
00156   uint32_t ICFilter;      /*!< Specifies the input capture filter.
00157                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00158 } TIM_OnePulse_InitTypeDef;
00159
00160
00161 /**
00162   * @brief  TIM Input Capture Configuration Structure definition
00163   */
00164 typedef struct
00165 {
00166   uint32_t  ICPolarity;   /*!< Specifies the active edge of the input signal.
00167                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00168
00169   uint32_t ICSelection;  /*!< Specifies the input.
00170                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00171
00172   uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
00173                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00174
00175   uint32_t ICFilter;     /*!< Specifies the input capture filter.
00176                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00177 } TIM_IC_InitTypeDef;
00178
00179 /**
00180   * @brief  TIM Encoder Configuration Structure definition
00181   */
00182 typedef struct
00183 {
00184   uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
00185                                This parameter can be a value of @ref TIM_Encoder_Mode */
00186
00187   uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
00188                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00189
00190   uint32_t IC1Selection;  /*!< Specifies the input.
00191                                This parameter can be a value of @ref TIM_Input_Capture_Selection */
00192
00193   uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
00194                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00195
00196   uint32_t IC1Filter;     /*!< Specifies the input capture filter.
00197                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00198
00199   uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
00200                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00201
00202   uint32_t IC2Selection;  /*!< Specifies the input.
00203                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00204
00205   uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
00206                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00207
00208   uint32_t IC2Filter;     /*!< Specifies the input capture filter.
00209                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00210 } TIM_Encoder_InitTypeDef;
00211
00212
00213 /**
00214   * @brief  Clock Configuration Handle Structure definition
00215   */
00216 typedef struct
00217 {
00218   uint32_t ClockSource;     /*!< TIM clock sources
00219                                  This parameter can be a value of @ref TIM_Clock_Source */
00220   uint32_t ClockPolarity;   /*!< TIM clock polarity
00221                                  This parameter can be a value of @ref TIM_Clock_Polarity */
00222   uint32_t ClockPrescaler;  /*!< TIM clock prescaler
00223                                  This parameter can be a value of @ref TIM_Clock_Prescaler */
00224   uint32_t ClockFilter;    /*!< TIM clock filter
00225                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00226 }TIM_ClockConfigTypeDef;
00227
00228 /**
00229   * @brief  Clear Input Configuration Handle Structure definition
00230   */
00231 typedef struct
00232 {
00233   uint32_t ClearInputState;      /*!< TIM clear Input state
00234                                       This parameter can be ENABLE or DISABLE */
00235   uint32_t ClearInputSource;     /*!< TIM clear Input sources
00236                                       This parameter can be a value of @ref TIMEx_ClearInput_Source */
00237   uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
00238                                       This parameter can be a value of @ref TIM_ClearInput_Polarity */
00239   uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
00240                                       This parameter can be a value of @ref TIM_ClearInput_Prescaler */
00241   uint32_t ClearInputFilter;    /*!< TIM Clear Input filter
00242                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00243 }TIM_ClearInputConfigTypeDef;
00244
00245 /**
00246   * @brief  TIM Master configuration Structure definition
00247   * @note   Advanced timers provide TRGO2 internal line which is redirected
00248   *         to the ADC
00249   */
00250 typedef struct {
00251   uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
00252                                       This parameter can be a value of @ref TIM_Master_Mode_Selection */
00253   uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
00254                                       This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
00255   uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
00256                                       This parameter can be a value of @ref TIM_Master_Slave_Mode */
00257 }TIM_MasterConfigTypeDef;
00258
00259 /**
00260   * @brief  TIM Slave configuration Structure definition
00261   */
00262 typedef struct {
00263   uint32_t  SlaveMode;      /*!< Slave mode selection
00264                                This parameter can be a value of @ref TIM_Slave_Mode */
00265   uint32_t  InputTrigger;      /*!< Input Trigger source
00266                                   This parameter can be a value of @ref TIM_Trigger_Selection */
00267   uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
00268                                   This parameter can be a value of @ref TIM_Trigger_Polarity */
00269   uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
00270                                   This parameter can be a value of @ref TIM_Trigger_Prescaler */
00271   uint32_t  TriggerFilter;     /*!< Input trigger filter
00272                                   This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
00273
00274 }TIM_SlaveConfigTypeDef;
00275
00276 /**
00277   * @brief  TIM Break input(s) and Dead time configuration Structure definition
00278   * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
00279   *        filter and polarity.
00280   */
00281 typedef struct
00282 {
00283   uint32_t OffStateRunMode;          /*!< TIM off state in run mode
00284                                          This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
00285   uint32_t OffStateIDLEMode;        /*!< TIM off state in IDLE mode
00286                                          This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
00287   uint32_t LockLevel;              /*!< TIM Lock level
00288                                          This parameter can be a value of @ref TIM_Lock_level */
00289   uint32_t DeadTime;               /*!< TIM dead Time
00290                                          This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
00291   uint32_t BreakState;             /*!< TIM Break State
00292                                          This parameter can be a value of @ref TIM_Break_Input_enable_disable */
00293   uint32_t BreakPolarity;           /*!< TIM Break input polarity
00294                                          This parameter can be a value of @ref TIM_Break_Polarity */
00295   uint32_t BreakFilter;             /*!< Specifies the break input filter.
00296                                          This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00297   uint32_t Break2State;            /*!< TIM Break2 State
00298                                          This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */
00299   uint32_t Break2Polarity;          /*!< TIM Break2 input polarity
00300                                          This parameter can be a value of @ref TIMEx_Break2_Polarity */
00301   uint32_t Break2Filter;            /*!< TIM break2 input filter.
00302                                          This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00303   uint32_t AutomaticOutput;         /*!< TIM Automatic Output Enable state
00304                                          This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
00305 } TIM_BreakDeadTimeConfigTypeDef;
00306
00307 /**
00308   * @brief  HAL State structures definition
00309   */
00310 typedef enum
00311 {
00312   HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
00313   HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
00314   HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
00315   HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
00316   HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
00317 }HAL_TIM_StateTypeDef;
00318
00319 /**
00320   * @brief  HAL Active channel structures definition
00321   */
00322 typedef enum
00323 {
00324   HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
00325   HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
00326   HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
00327   HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
00328   HAL_TIM_ACTIVE_CHANNEL_5        = 0x10U,    /*!< The active channel is 5     */
00329   HAL_TIM_ACTIVE_CHANNEL_6        = 0x20U,    /*!< The active channel is 6     */
00330   HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U    /*!< All active channels cleared */
00331 }HAL_TIM_ActiveChannel;
00332
00333 /**
00334   * @brief  TIM Time Base Handle Structure definition
00335   */
00336 typedef struct
00337 {
00338   TIM_TypeDef              *Instance;     /*!< Register base address             */
00339   TIM_Base_InitTypeDef     Init;          /*!< TIM Time Base required parameters */
00340   HAL_TIM_ActiveChannel    Channel;       /*!< Active channel                    */
00341   DMA_HandleTypeDef        *hdma[7];      /*!< DMA Handlers array This array is accessed by a @ref DMA_Handle_index */
00342   HAL_LockTypeDef          Lock;          /*!< Locking object                    */
00343   __IO HAL_TIM_StateTypeDef   State;      /*!< TIM operation state               */
00344 }TIM_HandleTypeDef;
00345
00346 /**
00347   * @}
00348   */
00349 /* End of exported types -----------------------------------------------------*/
00350
00351 /* Exported constants --------------------------------------------------------*/
00352 /** @defgroup TIM_Exported_Constants TIM Exported Constants
00353   * @{
00354   */
00355
00356 /** @defgroup TIM_Event_Source TIM  Extended Event Source
00357   * @{
00358   */
00359 #define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
00360 #define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
00361 #define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
00362 #define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
00363 #define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
00364 #define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
00365 #define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
00366 #define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
00367 #define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */
00368 /**
00369   * @}
00370   */
00371
00372 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
00373   * @{
00374   */
00375 #define  TIM_INPUTCHANNELPOLARITY_RISING      ((uint32_t)0x00000000U)            /*!< Polarity for TIx source */
00376 #define  TIM_INPUTCHANNELPOLARITY_FALLING     (TIM_CCER_CC1P)                   /*!< Polarity for TIx source */
00377 #define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
00378 /**
00379   * @}
00380   */
00381
00382 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
00383   * @{
00384   */
00385 #define TIM_ETRPOLARITY_INVERTED              (TIM_SMCR_ETP)                    /*!< Polarity for ETR source */
00386 #define TIM_ETRPOLARITY_NONINVERTED           ((uint32_t)0x0000U)               /*!< Polarity for ETR source */
00387 /**
00388   * @}
00389   */
00390
00391 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
00392   * @{
00393   */
00394 #define TIM_ETRPRESCALER_DIV1                 ((uint32_t)0x0000U)               /*!< No prescaler is used */
00395 #define TIM_ETRPRESCALER_DIV2                 (TIM_SMCR_ETPS_0)                 /*!< ETR input source is divided by 2 */
00396 #define TIM_ETRPRESCALER_DIV4                 (TIM_SMCR_ETPS_1)                 /*!< ETR input source is divided by 4 */
00397 #define TIM_ETRPRESCALER_DIV8                 (TIM_SMCR_ETPS)                   /*!< ETR input source is divided by 8 */
00398 /**
00399   * @}
00400   */
00401
00402 /** @defgroup TIM_Counter_Mode TIM Counter Mode
00403   * @{
00404   */
00405
00406 #define TIM_COUNTERMODE_UP                 ((uint32_t)0x0000U)                  /*!< Up counting mode */
00407 #define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Down counting mode */
00408 #define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned counting mode 1 */
00409 #define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned counting mode 2 */
00410 #define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned counting mode 3 */
00411
00412 /**
00413   * @}
00414   */
00415
00416 /** @defgroup TIM_ClockDivision TIM Clock Division
00417   * @{
00418   */
00419
00420 #define TIM_CLOCKDIVISION_DIV1                       ((uint32_t)0x0000U)        /*!< Clock Division DIV1 */
00421 #define TIM_CLOCKDIVISION_DIV2                       (TIM_CR1_CKD_0)            /*!< Clock Division DIV2 */
00422 #define TIM_CLOCKDIVISION_DIV4                       (TIM_CR1_CKD_1)            /*!< Clock Division DIV4 */
00423
00424 /**
00425   * @}
00426   */
00427
00428 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
00429   * @{
00430   */
00431 #define TIM_OUTPUTSTATE_DISABLE            ((uint32_t)0x0000U)             /*!< Output State disabled */
00432 #define TIM_OUTPUTSTATE_ENABLE             (TIM_CCER_CC1E)                 /*!< Output State enabled */
00433
00434 /**
00435   * @}
00436   */
00437 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
00438   * @{
00439   */
00440 #define TIM_AUTORELOAD_PRELOAD_DISABLE                ((uint32_t)0x0000U)   /*!< TIMx_ARR register is not buffered */
00441 #define TIM_AUTORELOAD_PRELOAD_ENABLE                 (TIM_CR1_ARPE)        /*!< TIMx_ARR register is buffered */
00442
00443 /**
00444   * @}
00445   */
00446
00447 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
00448   * @{
00449   */
00450 #define TIM_OCFAST_DISABLE                ((uint32_t)0x0000U)
00451 #define TIM_OCFAST_ENABLE                 (TIM_CCMR1_OC1FE)
00452
00453 /**
00454   * @}
00455   */
00456
00457 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
00458   * @{
00459   */
00460
00461 #define TIM_OCPOLARITY_HIGH                ((uint32_t)0x0000U)
00462 #define TIM_OCPOLARITY_LOW                 (TIM_CCER_CC1P)
00463
00464 /**
00465   * @}
00466   */
00467
00468 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
00469   * @{
00470   */
00471
00472 #define TIM_OCNPOLARITY_HIGH               ((uint32_t)0x0000U)
00473 #define TIM_OCNPOLARITY_LOW                (TIM_CCER_CC1NP)
00474
00475 /**
00476   * @}
00477   */
00478
00479 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
00480   * @{
00481   */
00482
00483 #define TIM_OCIDLESTATE_SET                (TIM_CR2_OIS1)
00484 #define TIM_OCIDLESTATE_RESET              ((uint32_t)0x0000U)
00485
00486 /**
00487   * @}
00488   */
00489
00490 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
00491   * @{
00492   */
00493
00494 #define TIM_OCNIDLESTATE_SET               (TIM_CR2_OIS1N)
00495 #define TIM_OCNIDLESTATE_RESET             ((uint32_t)0x0000U)
00496
00497 /**
00498   * @}
00499   */
00500
00501
00502
00503 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
00504   * @{
00505   */
00506
00507 #define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING
00508 #define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING
00509 #define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE
00510
00511 /**
00512   * @}
00513   */
00514
00515 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
00516   * @{
00517   */
00518
00519 #define TIM_ICSELECTION_DIRECTTI           (TIM_CCMR1_CC1S_0)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
00520                                                                                connected to IC1, IC2, IC3 or IC4, respectively */
00521 #define TIM_ICSELECTION_INDIRECTTI         (TIM_CCMR1_CC1S_1)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
00522                                                                                connected to IC2, IC1, IC4 or IC3, respectively */
00523 #define TIM_ICSELECTION_TRC                (TIM_CCMR1_CC1S)     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
00524
00525 /**
00526   * @}
00527   */
00528
00529 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
00530   * @{
00531   */
00532
00533 #define TIM_ICPSC_DIV1                     ((uint32_t)0x0000U)                 /*!< Capture performed each time an edge is detected on the capture input */
00534 #define TIM_ICPSC_DIV2                     (TIM_CCMR1_IC1PSC_0)     /*!< Capture performed once every 2 events */
00535 #define TIM_ICPSC_DIV4                     (TIM_CCMR1_IC1PSC_1)     /*!< Capture performed once every 4 events */
00536 #define TIM_ICPSC_DIV8                     (TIM_CCMR1_IC1PSC)       /*!< Capture performed once every 8 events */
00537
00538 /**
00539   * @}
00540   */
00541
00542 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
00543   * @{
00544   */
00545
00546 #define TIM_OPMODE_SINGLE                  (TIM_CR1_OPM)
00547 #define TIM_OPMODE_REPETITIVE              ((uint32_t)0x0000U)
00548
00549 /**
00550   * @}
00551   */
00552 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
00553   * @{
00554   */
00555 #define TIM_ENCODERMODE_TI1                (TIM_SMCR_SMS_0)
00556 #define TIM_ENCODERMODE_TI2                (TIM_SMCR_SMS_1)
00557 #define TIM_ENCODERMODE_TI12               (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
00558
00559 /**
00560   * @}
00561   */
00562 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
00563   * @{
00564   */
00565 #define TIM_IT_UPDATE           (TIM_DIER_UIE)
00566 #define TIM_IT_CC1              (TIM_DIER_CC1IE)
00567 #define TIM_IT_CC2              (TIM_DIER_CC2IE)
00568 #define TIM_IT_CC3              (TIM_DIER_CC3IE)
00569 #define TIM_IT_CC4              (TIM_DIER_CC4IE)
00570 #define TIM_IT_COM              (TIM_DIER_COMIE)
00571 #define TIM_IT_TRIGGER          (TIM_DIER_TIE)
00572 #define TIM_IT_BREAK            (TIM_DIER_BIE)
00573
00574 /**
00575   * @}
00576   */
00577 /** @defgroup TIM_Commutation_Source  TIM Commutation Source
00578   * @{
00579   */
00580 #define TIM_COMMUTATION_TRGI              (TIM_CR2_CCUS)
00581 #define TIM_COMMUTATION_SOFTWARE          ((uint32_t)0x0000U)
00582
00583 /**
00584   * @}
00585   */
00586
00587 /** @defgroup TIM_DMA_sources TIM DMA Sources
00588   * @{
00589   */
00590
00591 #define TIM_DMA_UPDATE                     (TIM_DIER_UDE)
00592 #define TIM_DMA_CC1                        (TIM_DIER_CC1DE)
00593 #define TIM_DMA_CC2                        (TIM_DIER_CC2DE)
00594 #define TIM_DMA_CC3                        (TIM_DIER_CC3DE)
00595 #define TIM_DMA_CC4                        (TIM_DIER_CC4DE)
00596 #define TIM_DMA_COM                        (TIM_DIER_COMDE)
00597 #define TIM_DMA_TRIGGER                    (TIM_DIER_TDE)
00598
00599 /**
00600   * @}
00601   */
00602
00603 /** @defgroup TIM_Flag_definition TIM Flag Definition
00604   * @{
00605   */
00606
00607 #define TIM_FLAG_UPDATE                    (TIM_SR_UIF)
00608 #define TIM_FLAG_CC1                       (TIM_SR_CC1IF)
00609 #define TIM_FLAG_CC2                       (TIM_SR_CC2IF)
00610 #define TIM_FLAG_CC3                       (TIM_SR_CC3IF)
00611 #define TIM_FLAG_CC4                       (TIM_SR_CC4IF)
00612 #define TIM_FLAG_CC5                       (TIM_SR_CC5IF)
00613 #define TIM_FLAG_CC6                       (TIM_SR_CC6IF)
00614 #define TIM_FLAG_COM                       (TIM_SR_COMIF)
00615 #define TIM_FLAG_TRIGGER                   (TIM_SR_TIF)
00616 #define TIM_FLAG_BREAK                     (TIM_SR_BIF)
00617 #define TIM_FLAG_BREAK2                    (TIM_SR_B2IF)
00618 #define TIM_FLAG_SYSTEM_BREAK              (TIM_SR_SBIF)
00619 #define TIM_FLAG_CC1OF                     (TIM_SR_CC1OF)
00620 #define TIM_FLAG_CC2OF                     (TIM_SR_CC2OF)
00621 #define TIM_FLAG_CC3OF                     (TIM_SR_CC3OF)
00622 #define TIM_FLAG_CC4OF                     (TIM_SR_CC4OF)
00623
00624 /**
00625   * @}
00626   */
00627
00628 /** @defgroup TIM_Clock_Source TIM Clock Source
00629   * @{
00630   */
00631 #define TIM_CLOCKSOURCE_ETRMODE2    (TIM_SMCR_ETPS_1)
00632 #define TIM_CLOCKSOURCE_INTERNAL    (TIM_SMCR_ETPS_0)
00633 #define TIM_CLOCKSOURCE_ITR0        ((uint32_t)0x0000U)
00634 #define TIM_CLOCKSOURCE_ITR1        (TIM_SMCR_TS_0)
00635 #define TIM_CLOCKSOURCE_ITR2        (TIM_SMCR_TS_1)
00636 #define TIM_CLOCKSOURCE_ITR3        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
00637 #define TIM_CLOCKSOURCE_TI1ED       (TIM_SMCR_TS_2)
00638 #define TIM_CLOCKSOURCE_TI1         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
00639 #define TIM_CLOCKSOURCE_TI2         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
00640 #define TIM_CLOCKSOURCE_ETRMODE1    (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
00641
00642 /**
00643   * @}
00644   */
00645
00646 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
00647   * @{
00648   */
00649 #define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED          /*!< Polarity for ETRx clock sources */
00650 #define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED       /*!< Polarity for ETRx clock sources */
00651 #define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING   /*!< Polarity for TIx clock sources */
00652 #define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
00653 #define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
00654
00655 /**
00656   * @}
00657   */
00658 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
00659   * @{
00660   */
00661 #define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
00662 #define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
00663 #define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
00664 #define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
00665
00666 /**
00667   * @}
00668   */
00669
00670 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
00671   * @{
00672   */
00673 #define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED                    /*!< Polarity for ETRx pin */
00674 #define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED                 /*!< Polarity for ETRx pin */
00675
00676 /**
00677   * @}
00678   */
00679
00680 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
00681   * @{
00682   */
00683 #define TIM_CLEARINPUTPRESCALER_DIV1                    TIM_ETRPRESCALER_DIV1      /*!< No prescaler is used */
00684 #define TIM_CLEARINPUTPRESCALER_DIV2                    TIM_ETRPRESCALER_DIV2      /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
00685 #define TIM_CLEARINPUTPRESCALER_DIV4                    TIM_ETRPRESCALER_DIV4      /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
00686 #define TIM_CLEARINPUTPRESCALER_DIV8                    TIM_ETRPRESCALER_DIV8        /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
00687
00688 /**
00689   * @}
00690   */
00691
00692 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM Off-state Selection for Run Mode
00693   * @{
00694   */
00695 #define TIM_OSSR_ENABLE               (TIM_BDTR_OSSR)
00696 #define TIM_OSSR_DISABLE              ((uint32_t)0x0000U)
00697
00698 /**
00699   * @}
00700   */
00701
00702 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM Off-state Selection for Idle Mode
00703   * @{
00704   */
00705 #define TIM_OSSI_ENABLE             (TIM_BDTR_OSSI)
00706 #define TIM_OSSI_DISABLE            ((uint32_t)0x0000U)
00707
00708 /**
00709   * @}
00710   */
00711 /** @defgroup TIM_Lock_level TIM Lock Configuration
00712   * @{
00713   */
00714 #define TIM_LOCKLEVEL_OFF          ((uint32_t)0x0000U)
00715 #define TIM_LOCKLEVEL_1            (TIM_BDTR_LOCK_0)
00716 #define TIM_LOCKLEVEL_2            (TIM_BDTR_LOCK_1)
00717 #define TIM_LOCKLEVEL_3            (TIM_BDTR_LOCK)
00718
00719 /**
00720   * @}
00721   */
00722 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
00723   * @{
00724   */
00725 #define TIM_BREAK_ENABLE          (TIM_BDTR_BKE)
00726 #define TIM_BREAK_DISABLE         ((uint32_t)0x0000U)
00727
00728 /**
00729   * @}
00730   */
00731
00732 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
00733   * @{
00734   */
00735 #define TIM_BREAKPOLARITY_LOW              ((uint32_t)0x0000U)
00736 #define TIM_BREAKPOLARITY_HIGH             (TIM_BDTR_BKP)
00737 /**
00738   * @}
00739   */
00740
00741 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
00742   * @{
00743   */
00744 #define TIM_AUTOMATICOUTPUT_ENABLE           (TIM_BDTR_AOE)
00745 #define TIM_AUTOMATICOUTPUT_DISABLE          ((uint32_t)0x0000U)
00746
00747 /**
00748   * @}
00749   */
00750
00751
00752 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
00753   * @{
00754   */
00755 #define TIM_TRGO_RESET            ((uint32_t)0x0000U)
00756 #define TIM_TRGO_ENABLE           (TIM_CR2_MMS_0)
00757 #define TIM_TRGO_UPDATE           (TIM_CR2_MMS_1)
00758 #define TIM_TRGO_OC1              ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
00759 #define TIM_TRGO_OC1REF           (TIM_CR2_MMS_2)
00760 #define TIM_TRGO_OC2REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
00761 #define TIM_TRGO_OC3REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
00762 #define TIM_TRGO_OC4REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
00763
00764 /**
00765   * @}
00766   */
00767 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
00768   * @{
00769   */
00770 #define TIM_TRGO2_RESET                          ((uint32_t)0x00000000U)
00771 #define TIM_TRGO2_ENABLE                         ((uint32_t)(TIM_CR2_MMS2_0))
00772 #define TIM_TRGO2_UPDATE                         ((uint32_t)(TIM_CR2_MMS2_1))
00773 #define TIM_TRGO2_OC1                            ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
00774 #define TIM_TRGO2_OC1REF                         ((uint32_t)(TIM_CR2_MMS2_2))
00775 #define TIM_TRGO2_OC2REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
00776 #define TIM_TRGO2_OC3REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
00777 #define TIM_TRGO2_OC4REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
00778 #define TIM_TRGO2_OC5REF                         ((uint32_t)(TIM_CR2_MMS2_3))
00779 #define TIM_TRGO2_OC6REF                         ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
00780 #define TIM_TRGO2_OC4REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
00781 #define TIM_TRGO2_OC6REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
00782 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
00783 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
00784 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
00785 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
00786 /**
00787   * @}
00788   */
00789
00790 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
00791   * @{
00792   */
00793
00794 #define TIM_MASTERSLAVEMODE_ENABLE          ((uint32_t)0x0080U)
00795 #define TIM_MASTERSLAVEMODE_DISABLE         ((uint32_t)0x0000U)
00796
00797 /**
00798   * @}
00799   */
00800
00801 /** @defgroup TIM_Slave_Mode TIM Slave mode
00802   * @{
00803   */
00804 #define TIM_SLAVEMODE_DISABLE                ((uint32_t)0x0000U)
00805 #define TIM_SLAVEMODE_RESET                  ((uint32_t)(TIM_SMCR_SMS_2))
00806 #define TIM_SLAVEMODE_GATED                  ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
00807 #define TIM_SLAVEMODE_TRIGGER                ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
00808 #define TIM_SLAVEMODE_EXTERNAL1              ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
00809 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  ((uint32_t)(TIM_SMCR_SMS_3))
00810 /**
00811   * @}
00812   */
00813
00814 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
00815   * @{
00816   */
00817
00818 #define TIM_TS_ITR0                        ((uint32_t)0x0000U)
00819 #define TIM_TS_ITR1                        ((uint32_t)0x0010U)
00820 #define TIM_TS_ITR2                        ((uint32_t)0x0020U)
00821 #define TIM_TS_ITR3                        ((uint32_t)0x0030U)
00822 #define TIM_TS_TI1F_ED                     ((uint32_t)0x0040U)
00823 #define TIM_TS_TI1FP1                      ((uint32_t)0x0050U)
00824 #define TIM_TS_TI2FP2                      ((uint32_t)0x0060U)
00825 #define TIM_TS_ETRF                        ((uint32_t)0x0070U)
00826 #define TIM_TS_NONE                        ((uint32_t)0xFFFFU)
00827
00828 /**
00829   * @}
00830   */
00831
00832 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
00833   * @{
00834   */
00835 #define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources */
00836 #define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources */
00837 #define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00838 #define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00839 #define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00840
00841 /**
00842   * @}
00843   */
00844
00845 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
00846   * @{
00847   */
00848 #define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
00849 #define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
00850 #define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
00851 #define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
00852
00853 /**
00854   * @}
00855   */
00856
00857   /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
00858   * @{
00859   */
00860
00861 #define TIM_TI1SELECTION_CH1                ((uint32_t)0x0000U)
00862 #define TIM_TI1SELECTION_XORCOMBINATION     (TIM_CR2_TI1S)
00863
00864 /**
00865   * @}
00866   */
00867
00868 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
00869   * @{
00870   */
00871 #define TIM_DMABURSTLENGTH_1TRANSFER           (0x00000000U)
00872 #define TIM_DMABURSTLENGTH_2TRANSFERS          (0x00000100U)
00873 #define TIM_DMABURSTLENGTH_3TRANSFERS          (0x00000200U)
00874 #define TIM_DMABURSTLENGTH_4TRANSFERS          (0x00000300U)
00875 #define TIM_DMABURSTLENGTH_5TRANSFERS          (0x00000400U)
00876 #define TIM_DMABURSTLENGTH_6TRANSFERS          (0x00000500U)
00877 #define TIM_DMABURSTLENGTH_7TRANSFERS          (0x00000600U)
00878 #define TIM_DMABURSTLENGTH_8TRANSFERS          (0x00000700U)
00879 #define TIM_DMABURSTLENGTH_9TRANSFERS          (0x00000800U)
00880 #define TIM_DMABURSTLENGTH_10TRANSFERS         (0x00000900U)
00881 #define TIM_DMABURSTLENGTH_11TRANSFERS         (0x00000A00U)
00882 #define TIM_DMABURSTLENGTH_12TRANSFERS         (0x00000B00U)
00883 #define TIM_DMABURSTLENGTH_13TRANSFERS         (0x00000C00U)
00884 #define TIM_DMABURSTLENGTH_14TRANSFERS         (0x00000D00U)
00885 #define TIM_DMABURSTLENGTH_15TRANSFERS         (0x00000E00U)
00886 #define TIM_DMABURSTLENGTH_16TRANSFERS         (0x00000F00U)
00887 #define TIM_DMABURSTLENGTH_17TRANSFERS         (0x00001000U)
00888 #define TIM_DMABURSTLENGTH_18TRANSFERS         (0x00001100U)
00889
00890 /**
00891   * @}
00892   */
00893
00894 /** @defgroup DMA_Handle_index TIM DMA Handle Index
00895   * @{
00896   */
00897 #define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0U)       /*!< Index of the DMA handle used for Update DMA requests */
00898 #define TIM_DMA_ID_CC1                   ((uint16_t) 0x1U)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
00899 #define TIM_DMA_ID_CC2                   ((uint16_t) 0x2U)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
00900 #define TIM_DMA_ID_CC3                   ((uint16_t) 0x3U)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
00901 #define TIM_DMA_ID_CC4                   ((uint16_t) 0x4U)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
00902 #define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x5U)       /*!< Index of the DMA handle used for Commutation DMA requests */
00903 #define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x6U)       /*!< Index of the DMA handle used for Trigger DMA requests */
00904 /**
00905   * @}
00906   */
00907
00908 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
00909   * @{
00910   */
00911 #define TIM_CCx_ENABLE                   ((uint32_t)0x0001U)
00912 #define TIM_CCx_DISABLE                  ((uint32_t)0x0000U)
00913 #define TIM_CCxN_ENABLE                  ((uint32_t)0x0004U)
00914 #define TIM_CCxN_DISABLE                 ((uint32_t)0x0000U)
00915 /**
00916   * @}
00917   */
00918
00919 /**
00920   * @}
00921   */
00922 /* End of exported constants -------------------------------------------------*/
00923
00924 /* Exported macros -----------------------------------------------------------*/
00925 /** @defgroup TIM_Exported_Macros TIM Exported Macros
00926   * @{
00927   */
00928
00929 /** @brief  Reset TIM handle state
00930   * @param  __HANDLE__: TIM handle.
00931   * @retval None
00932   */
00933 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
00934
00935 /**
00936   * @brief  Enable the TIM peripheral.
00937   * @param  __HANDLE__: TIM handle
00938   * @retval None
00939  */
00940 #define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
00941
00942 /**
00943   * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
00944   * @param  __HANDLE__: TIM handle.
00945   * @note  When the USR bit of the TIMx_CR1 register is set, only counter
00946   *        overflow/underflow generates an update interrupt or DMA request (if
00947   *        enabled)
00948   * @retval None
00949   */
00950 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
00951     ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
00952 /**
00953   * @brief  Enable the TIM main Output.
00954   * @param  __HANDLE__: TIM handle
00955   * @retval None
00956   */
00957 #define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
00958
00959 /* The counter of a timer instance is disabled only if all the CCx and CCxN
00960    channels have been disabled */
00961 #define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
00962 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
00963
00964 /**
00965   * @brief  Disable the TIM peripheral.
00966   * @param  __HANDLE__: TIM handle
00967   * @retval None
00968   */
00969 #define __HAL_TIM_DISABLE(__HANDLE__) \
00970                         do { \
00971                           if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
00972                             { \
00973                             if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
00974                             { \
00975                               (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
00976                             } \
00977                           } \
00978                         } while(0)
00979 /**
00980   * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
00981   * @param  __HANDLE__: TIM handle.
00982   * @note  When the USR bit of the TIMx_CR1 register is reset, any of the
00983   *        following events generate an update interrupt or DMA request (if
00984   *        enabled):
00985   *           _ Counter overflow underflow
00986   *           _ Setting the UG bit
00987   *           _ Update generation through the slave mode controller
00988   * @retval None
00989   */
00990 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
00991       ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
00992
00993 /**
00994   * @brief  Disable the TIM main Output.
00995   * @param  __HANDLE__: TIM handle
00996   * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
00997   * @retval None
00998   */
00999 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
01000                         do { \
01001                           if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
01002                           { \
01003                             if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
01004                             { \
01005                               (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
01006                             } \
01007                             } \
01008                         } while(0)
01009
01010 /* The Main Output Enable of a timer instance is disabled unconditionally */
01011 /**
01012   * @brief  Disable the TIM main Output.
01013   * @param  __HANDLE__: TIM handle
01014   * @retval None
01015   * @note The Main Output Enable of a timer instance is disabled uncondiotionally
01016   */
01017 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  ((__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE))
01018
01019 /** @brief  Enable the specified TIM interrupt.
01020 * @param  __HANDLE__: specifies the TIM Handle.
01021 * @param  __INTERRUPT__: specifies the TIM interrupt source to enable.
01022 *          This parameter can be one of the following values:
01023 *            @arg TIM_IT_UPDATE: Update interrupt
01024 *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01025 *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01026 *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01027 *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01028 *            @arg TIM_IT_COM:   Commutation interrupt
01029 *            @arg TIM_IT_TRIGGER: Trigger interrupt
01030 *            @arg TIM_IT_BREAK: Break interrupt
01031 * @retval None
01032 */
01033 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
01034
01035   /** @brief  Disable the specified TIM interrupt.
01036   * @param  __HANDLE__: specifies the TIM Handle.
01037   * @param  __INTERRUPT__: specifies the TIM interrupt source to disable.
01038   *          This parameter can be one of the following values:
01039   *            @arg TIM_IT_UPDATE: Update interrupt
01040   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01041   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01042   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01043   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01044   *            @arg TIM_IT_COM:   Commutation interrupt
01045   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01046   *            @arg TIM_IT_BREAK: Break interrupt
01047   * @retval None
01048   */
01049 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
01050
01051 /** @brief  Enable the specified DMA request.
01052   * @param  __HANDLE__: specifies the TIM Handle.
01053   * @param  __DMA__: specifies the TIM DMA request to enable.
01054   *          This parameter can be one of the following values:
01055   *            @arg TIM_DMA_UPDATE: Update DMA request
01056   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
01057   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
01058   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
01059   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
01060   *            @arg TIM_DMA_COM:   Commutation DMA request
01061   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
01062   * @retval None
01063   */
01064 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)  ((__HANDLE__)->Instance->DIER |= (__DMA__))
01065
01066 /** @brief  Disable the specified DMA request.
01067   * @param  __HANDLE__: specifies the TIM Handle.
01068   * @param  __DMA__: specifies the TIM DMA request to disable.
01069   *          This parameter can be one of the following values:
01070   *            @arg TIM_DMA_UPDATE: Update DMA request
01071   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
01072   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
01073   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
01074   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
01075   *            @arg TIM_DMA_COM:   Commutation DMA request
01076   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
01077   *            @arg TIM_DMA_BREAK: Break DMA request
01078   * @retval None
01079   */
01080 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)  ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
01081
01082 /** @brief  Check whether the specified TIM interrupt flag is set or not.
01083   * @param  __HANDLE__: specifies the TIM Handle.
01084   * @param  __FLAG__: specifies the TIM interrupt flag to check.
01085   *        This parameter can be one of the following values:
01086   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
01087   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
01088   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
01089   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
01090   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
01091   *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
01092   *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
01093   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
01094   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
01095   *            @arg TIM_FLAG_BREAK: Break interrupt flag
01096   *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
01097   *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
01098   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
01099   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
01100   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
01101   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
01102   * @retval The new state of __FLAG__ (TRUE or FALSE).
01103   */
01104 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)       (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
01105
01106 /** @brief  Clear the specified TIM interrupt flag.
01107   * @param  __HANDLE__: specifies the TIM Handle.
01108   * @param  __FLAG__: specifies the TIM interrupt flag to clear.
01109   *        This parameter can be one of the following values:
01110   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
01111   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
01112   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
01113   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
01114   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
01115   *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
01116   *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
01117   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
01118   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
01119   *            @arg TIM_FLAG_BREAK: Break interrupt flag
01120   *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
01121   *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
01122   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
01123   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
01124   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
01125   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
01126   * @retval The new state of __FLAG__ (TRUE or FALSE).
01127   */
01128 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)       ((__HANDLE__)->Instance->SR = ~(__FLAG__))
01129
01130 /**
01131   * @brief  Check whether the specified TIM interrupt source is enabled or not.
01132   * @param  __HANDLE__: TIM handle
01133   * @param  __INTERRUPT__: specifies the TIM interrupt source to check.
01134   *          This parameter can be one of the following values:
01135   *            @arg TIM_IT_UPDATE: Update interrupt
01136   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01137   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01138   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01139   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01140   *            @arg TIM_IT_COM:   Commutation interrupt
01141   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01142   *            @arg TIM_IT_BREAK: Break interrupt
01143   * @retval The state of TIM_IT (SET or RESET).
01144   */
01145 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
01146
01147 /** @brief Clear the TIM interrupt pending bits.
01148   * @param  __HANDLE__: TIM handle
01149   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
01150   *          This parameter can be one of the following values:
01151   *            @arg TIM_IT_UPDATE: Update interrupt
01152   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01153   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01154   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01155   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01156   *            @arg TIM_IT_COM:   Commutation interrupt
01157   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01158   *            @arg TIM_IT_BREAK: Break interrupt
01159   * @retval None
01160   */
01161 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->SR = ~(uint32_t)(__INTERRUPT__))
01162
01163 /**
01164   * @brief  Indicates whether or not the TIM Counter is used as downcounter.
01165   * @param  __HANDLE__: TIM handle.
01166   * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
01167   * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
01168 mode.
01169   */
01170 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
01171
01172 /**
01173   * @brief  Set the TIM Prescaler on runtime.
01174   * @param  __HANDLE__: TIM handle.
01175   * @param  __PRESC__: specifies the Prescaler new value.
01176   * @retval None
01177   */
01178 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
01179
01180 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
01181 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
01182  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
01183  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
01184  ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
01185
01186 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
01187 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
01188  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
01189  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
01190  ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
01191
01192 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
01193 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
01194  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
01195  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
01196  ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12))))
01197
01198 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
01199 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
01200  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
01201  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
01202  ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
01203 /**
01204   * @brief  Set the TIM Counter Register value on runtime.
01205   * @param  __HANDLE__: TIM handle.
01206   * @param  __COUNTER__: specifies the Counter register new value.
01207   * @retval None
01208   */
01209 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
01210
01211 /**
01212   * @brief  Get the TIM Counter Register value on runtime.
01213   * @param  __HANDLE__: TIM handle.
01214   * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
01215
01216   */
01217 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
01218
01219 /**
01220   * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
01221   * @param  __HANDLE__: TIM handle.
01222   * @param  __AUTORELOAD__: specifies the Counter register new value.
01223   * @retval None
01224   */
01225 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
01226                          do{                                                    \
01227                               (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
01228                               (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
01229                           } while(0)
01230
01231 /**
01232   * @brief  Get the TIM Autoreload Register value on runtime.
01233   * @param  __HANDLE__: TIM handle.
01234   * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
01235   */
01236 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
01237
01238 /**
01239   * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
01240   * @param  __HANDLE__: TIM handle.
01241   * @param  __CKD__: specifies the clock division value.
01242   *          This parameter can be one of the following value:
01243   *            @arg TIM_CLOCKDIVISION_DIV1
01244   *            @arg TIM_CLOCKDIVISION_DIV2
01245   *            @arg TIM_CLOCKDIVISION_DIV4
01246   * @retval None
01247   */
01248 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
01249                         do{                                                    \
01250                               (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
01251                               (__HANDLE__)->Instance->CR1 |= (__CKD__);                   \
01252                               (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
01253                           } while(0)
01254
01255 /**
01256   * @brief  Get the TIM Clock Division value on runtime.
01257   * @param  __HANDLE__: TIM handle.
01258   * @retval The clock division can be one of the following values:
01259   *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
01260   *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
01261   *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
01262   */
01263 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
01264
01265 /**
01266   * @brief  Set the TIM Input Capture prescaler on runtime without calling
01267   *         another time HAL_TIM_IC_ConfigChannel() function.
01268   * @param  __HANDLE__: TIM handle.
01269   * @param  __CHANNEL__: TIM Channels to be configured.
01270   *          This parameter can be one of the following values:
01271   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01272   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01273   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01274   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01275   * @param  __ICPSC__: specifies the Input Capture4 prescaler new value.
01276   *          This parameter can be one of the following values:
01277   *            @arg TIM_ICPSC_DIV1: no prescaler
01278   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
01279   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
01280   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
01281   * @retval None
01282   */
01283 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
01284                         do{                                                    \
01285                               TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
01286                               TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
01287                           } while(0)
01288
01289 /**
01290   * @brief  Get the TIM Input Capture prescaler on runtime.
01291   * @param  __HANDLE__: TIM handle.
01292   * @param  __CHANNEL__: TIM Channels to be configured.
01293   *          This parameter can be one of the following values:
01294   *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
01295   *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
01296   *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
01297   *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
01298   * @retval The input capture prescaler can be one of the following values:
01299   *            @arg TIM_ICPSC_DIV1: no prescaler
01300   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
01301   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
01302   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
01303   */
01304 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
01305   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
01306    ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
01307    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
01308    (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
01309
01310 /**
01311   * @brief  Set the TIM Capture x input polarity on runtime.
01312   * @param  __HANDLE__: TIM handle.
01313   * @param  __CHANNEL__: TIM Channels to be configured.
01314   *          This parameter can be one of the following values:
01315   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01316   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01317   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01318   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01319   * @param  __POLARITY__: Polarity for TIx source
01320   *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
01321   *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
01322   *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
01323   * @retval None
01324   */
01325 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
01326         do{                                                                     \
01327           TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
01328           TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
01329         }while(0)
01330 /**
01331   * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
01332   * @param  __HANDLE__: TIM handle.
01333   * @param  __CHANNEL__: TIM Channels to be configured.
01334   *          This parameter can be one of the following values:
01335   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01336   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01337   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01338   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01339   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01340   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01341   * @param  __COMPARE__: specifies the Capture Compare register new value.
01342   * @retval None
01343   */
01344 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
01345 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
01346  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
01347  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
01348  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
01349  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
01350  ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
01351
01352 /**
01353   * @brief  Get the TIM Capture Compare Register value on runtime.
01354   * @param  __HANDLE__: TIM handle.
01355   * @param  __CHANNEL__: TIM Channel associated with the capture compare register
01356   *          This parameter can be one of the following values:
01357   *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
01358   *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
01359   *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
01360   *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
01361   *            @arg TIM_CHANNEL_5: get capture/compare 5 register value
01362   *            @arg TIM_CHANNEL_6: get capture/compare 6 register value
01363   * @retval None by @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
01364   */
01365 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
01366 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
01367  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
01368  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
01369  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
01370  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
01371  ((__HANDLE__)->Instance->CCR6))
01372
01373 /**
01374   * @}
01375   */
01376 /* End of exported macros ----------------------------------------------------*/
01377
01378 /* Private constants ---------------------------------------------------------*/
01379 /** @defgroup TIM_Private_Constants TIM Private Constants
01380   * @{
01381   */
01382
01383 /**
01384   * @}
01385   */
01386 /* End of private constants --------------------------------------------------*/
01387
01388 /* Private macros ------------------------------------------------------------*/
01389 /** @defgroup TIM_Private_Macros TIM Private Macros
01390   * @{
01391   */
01392
01393 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)      || \
01394                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
01395                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
01396
01397 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
01398                                    ((__BASE__) == TIM_DMABASE_CR2)   || \
01399                                    ((__BASE__) == TIM_DMABASE_SMCR)  || \
01400                                    ((__BASE__) == TIM_DMABASE_DIER)  || \
01401                                    ((__BASE__) == TIM_DMABASE_SR)    || \
01402                                    ((__BASE__) == TIM_DMABASE_EGR)   || \
01403                                    ((__BASE__) == TIM_DMABASE_CCMR1) || \
01404                                    ((__BASE__) == TIM_DMABASE_CCMR2) || \
01405                                    ((__BASE__) == TIM_DMABASE_CCER)  || \
01406                                    ((__BASE__) == TIM_DMABASE_CNT)   || \
01407                                    ((__BASE__) == TIM_DMABASE_PSC)   || \
01408                                    ((__BASE__) == TIM_DMABASE_ARR)   || \
01409                                    ((__BASE__) == TIM_DMABASE_RCR)   || \
01410                                    ((__BASE__) == TIM_DMABASE_CCR1)  || \
01411                                    ((__BASE__) == TIM_DMABASE_CCR2)  || \
01412                                    ((__BASE__) == TIM_DMABASE_CCR3)  || \
01413                                    ((__BASE__) == TIM_DMABASE_CCR4)  || \
01414                                    ((__BASE__) == TIM_DMABASE_BDTR)  || \
01415                                    ((__BASE__) == TIM_DMABASE_CCMR3) || \
01416                                    ((__BASE__) == TIM_DMABASE_CCR5)  || \
01417                                    ((__BASE__) == TIM_DMABASE_CCR6)  || \
01418                                    ((__BASE__) == TIM_DMABASE_AF1)   || \
01419                                    ((__BASE__) == TIM_DMABASE_AF2)   || \
01420                                    ((__BASE__) == TIM_DMABASE_TISEL))
01421
01422
01423 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
01424
01425
01426 #define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
01427                                             ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
01428                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
01429                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
01430                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
01431
01432 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
01433                                             ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
01434                                             ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
01435
01436 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
01437                                             ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
01438
01439
01440 #define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
01441                                             ((__STATE__) == TIM_OCFAST_ENABLE))
01442
01443 #define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
01444                                             ((__POLARITY__) == TIM_OCPOLARITY_LOW))
01445
01446 #define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
01447                                             ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
01448
01449 #define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \
01450                                             ((__STATE__) == TIM_OCIDLESTATE_RESET))
01451
01452 #define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
01453                                             ((__STATE__) == TIM_OCNIDLESTATE_RESET))
01454
01455 #define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
01456                                             ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
01457                                             ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
01458
01459 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
01460                                             ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
01461                                             ((__SELECTION__) == TIM_ICSELECTION_TRC))
01462
01463 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
01464                                             ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
01465                                             ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
01466                                             ((__PRESCALER__) == TIM_ICPSC_DIV8))
01467
01468 #define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
01469                                             ((__MODE__) == TIM_OPMODE_REPETITIVE))
01470
01471 #define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
01472                                             ((__MODE__) == TIM_ENCODERMODE_TI2) || \
01473                                             ((__MODE__) == TIM_ENCODERMODE_TI12))
01474
01475 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
01476
01477 #define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
01478                                             ((__CHANNEL__) == TIM_CHANNEL_2) || \
01479                                             ((__CHANNEL__) == TIM_CHANNEL_3) || \
01480                                             ((__CHANNEL__) == TIM_CHANNEL_4) || \
01481                                             ((__CHANNEL__) == TIM_CHANNEL_5) || \
01482                                             ((__CHANNEL__) == TIM_CHANNEL_6) || \
01483                                             ((__CHANNEL__) == TIM_CHANNEL_ALL))
01484
01485 #define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
01486                                             ((__CHANNEL__) == TIM_CHANNEL_2))
01487
01488 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
01489                                                     ((__CHANNEL__) == TIM_CHANNEL_2) || \
01490                                                     ((__CHANNEL__) == TIM_CHANNEL_3))
01491
01492 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
01493                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
01494                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
01495                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
01496                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
01497                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
01498                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
01499                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
01500                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
01501                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
01502
01503 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
01504                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
01505                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
01506                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
01507                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
01508
01509 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
01510                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
01511                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
01512                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
01513
01514 #define IS_TIM_CLOCKFILTER(ICFILTER)      ((ICFILTER) <= 0xF)
01515
01516 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
01517                                                   ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
01518
01519 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
01520                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
01521                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
01522                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
01523
01524 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
01525
01526
01527 #define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \
01528                                             ((__STATE__) == TIM_OSSR_DISABLE))
01529
01530 #define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \
01531                                             ((__STATE__) == TIM_OSSI_DISABLE))
01532
01533 #define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
01534                                             ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
01535                                             ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
01536                                             ((__LEVEL__) == TIM_LOCKLEVEL_3))
01537
01538 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xF)
01539
01540
01541 #define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
01542                                             ((__STATE__) == TIM_BREAK_DISABLE))
01543
01544 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
01545                                              ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
01546
01547 #define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \
01548                                             ((__STATE__) == TIM_BREAK2_DISABLE))
01549
01550 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
01551                                               ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
01552
01553 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
01554                                                   ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
01555
01556 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
01557
01558 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
01559                                         ((__SOURCE__) == TIM_TRGO_ENABLE) || \
01560                                         ((__SOURCE__) == TIM_TRGO_UPDATE) || \
01561                                         ((__SOURCE__) == TIM_TRGO_OC1)    || \
01562                                         ((__SOURCE__) == TIM_TRGO_OC1REF) || \
01563                                         ((__SOURCE__) == TIM_TRGO_OC2REF) || \
01564                                         ((__SOURCE__) == TIM_TRGO_OC3REF) || \
01565                                         ((__SOURCE__) == TIM_TRGO_OC4REF))
01566
01567 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET)                        || \
01568                                          ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
01569                                          ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
01570                                          ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
01571                                          ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
01572                                          ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
01573                                          ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
01574                                          ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
01575                                          ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
01576                                          ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
01577                                          ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
01578                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
01579                                          ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
01580                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
01581                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
01582                                          ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
01583                                          ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
01584
01585 #define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
01586                                           ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
01587
01588 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
01589                                      ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
01590                                      ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
01591                                      ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
01592                                      ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
01593                                      ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
01594
01595 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
01596                                    ((__MODE__) == TIM_OCMODE_PWM2)               || \
01597                                    ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
01598                                    ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
01599                                    ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
01600                                    ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
01601
01602 #define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
01603                                    ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
01604                                    ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
01605                                    ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
01606                                    ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
01607                                    ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
01608                                    ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
01609                                    ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
01610
01611 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
01612                                                  ((__SELECTION__) == TIM_TS_ITR1) || \
01613                                                  ((__SELECTION__) == TIM_TS_ITR2) || \
01614                                                  ((__SELECTION__) == TIM_TS_ITR3) || \
01615                                                  ((__SELECTION__) == TIM_TS_TI1F_ED) || \
01616                                                  ((__SELECTION__) == TIM_TS_TI1FP1) || \
01617                                                  ((__SELECTION__) == TIM_TS_TI2FP2) || \
01618                                                  ((__SELECTION__) == TIM_TS_ETRF))
01619
01620 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
01621                                                                ((__SELECTION__) == TIM_TS_ITR1) || \
01622                                                                ((__SELECTION__) == TIM_TS_ITR2) || \
01623                                                                ((__SELECTION__) == TIM_TS_ITR3) || \
01624                                                                ((__SELECTION__) == TIM_TS_NONE))
01625
01626
01627 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
01628                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
01629                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
01630                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
01631                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
01632
01633 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
01634                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
01635                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
01636                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
01637
01638 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
01639
01640 #define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
01641                                                 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
01642
01643 #define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
01644                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
01645                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
01646                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
01647                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
01648                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
01649                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
01650                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
01651                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
01652                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
01653                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
01654                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
01655                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
01656                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
01657                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
01658                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
01659                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
01660                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
01661
01662 #define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
01663
01664 #define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)
01665
01666 #define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                 || \
01667                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                 || \
01668                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR)  || \
01669                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
01670
01671 /**
01672   * @}
01673   */
01674 /* End of private macros -----------------------------------------------------*/
01675
01676 /* Include TIM HAL Extended module */
01677 #include "stm32h7xx_hal_tim_ex.h"
01678
01679 /* Exported functions --------------------------------------------------------*/
01680 /** @addtogroup TIM_Exported_Functions TIM Exported Functions
01681   * @{
01682   */
01683
01684 /** @addtogroup TIM_Exported_Functions_Group1 Time Base functions
01685  *  @brief    Time Base functions
01686  * @{
01687  */
01688 /* Time Base functions ********************************************************/
01689 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
01690 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
01691 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
01692 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
01693 /* Blocking mode: Polling */
01694 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
01695 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
01696 /* Non-Blocking mode: Interrupt */
01697 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
01698 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
01699 /* Non-Blocking mode: DMA */
01700 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
01701 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
01702 /**
01703   * @}
01704   */
01705
01706 /** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions
01707  *  @brief    Time Output Compare functions
01708  * @{
01709  */
01710 /* Timer Output Compare functions **********************************************/
01711 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
01712 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
01713 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
01714 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
01715 /* Blocking mode: Polling */
01716 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01717 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01718 /* Non-Blocking mode: Interrupt */
01719 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01720 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01721 /* Non-Blocking mode: DMA */
01722 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01723 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01724 /**
01725   * @}
01726   */
01727
01728 /** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions
01729  *  @brief    Time PWM functions
01730  * @{
01731  */
01732 /* Timer PWM functions *********************************************************/
01733 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
01734 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
01735 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
01736 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
01737 /* Blocking mode: Polling */
01738 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01739 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01740 /* Non-Blocking mode: Interrupt */
01741 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01742 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01743 /* Non-Blocking mode: DMA */
01744 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01745 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01746 /**
01747   * @}
01748   */
01749
01750 /** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions
01751  *  @brief    Time Input Capture functions
01752  * @{
01753  */
01754 /* Timer Input Capture functions ***********************************************/
01755 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
01756 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
01757 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
01758 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
01759 /* Blocking mode: Polling */
01760 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01761 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01762 /* Non-Blocking mode: Interrupt */
01763 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01764 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01765 /* Non-Blocking mode: DMA */
01766 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01767 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01768 /**
01769   * @}
01770   */
01771
01772 /** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions
01773  *  @brief    Time One Pulse functions
01774  * @{
01775  */
01776 /* Timer One Pulse functions ***************************************************/
01777 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
01778 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
01779 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
01780 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
01781 /* Blocking mode: Polling */
01782 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01783 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01784 /* Non-Blocking mode: Interrupt */
01785 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01786 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01787 /**
01788   * @}
01789   */
01790
01791 /** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions
01792  *  @brief    Time Encoder functions
01793  * @{
01794  */
01795 /* Timer Encoder functions *****************************************************/
01796 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig);
01797 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
01798 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
01799 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
01800  /* Blocking mode: Polling */
01801 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01802 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01803 /* Non-Blocking mode: Interrupt */
01804 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01805 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01806 /* Non-Blocking mode: DMA */
01807 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
01808 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01809 /**
01810   * @}
01811   */
01812
01813 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
01814  *  @brief    IRQ handler management
01815   * @{
01816   */
01817 /* Interrupt Handler functions  **********************************************/
01818 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
01819 /**
01820   * @}
01821   */
01822
01823 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
01824  *  @brief   Peripheral Control functions
01825   * @{
01826   */
01827 /* Control functions  *********************************************************/
01828 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
01829 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
01830 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
01831 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel);
01832 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
01833 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
01834 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
01835 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
01836 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
01837 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
01838                                               uint32_t  *BurstBuffer, uint32_t  BurstLength);
01839 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
01840 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
01841                                               uint32_t  *BurstBuffer, uint32_t  BurstLength);
01842 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
01843 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
01844 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
01845 /**
01846   * @}
01847   */
01848
01849 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
01850  *  @brief    TIM Callbacks functions
01851   * @{
01852   */
01853 /* Callback in non blocking modes (Interrupt and DMA) *************************/
01854 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
01855 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
01856 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
01857 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
01858 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
01859 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
01860 /**
01861   * @}
01862   */
01863
01864 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
01865  *  @brief   Peripheral State functions
01866  * @{
01867  */
01868 /* Peripheral State functions  **************************************************/
01869 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
01870 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
01871 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
01872 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
01873 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
01874 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
01875 /**
01876   * @}
01877   */
01878
01879 /**
01880   * @}
01881   */
01882 /* End of exported functions -------------------------------------------------*/
01883
01884 /* Private functions----------------------------------------------------------*/
01885 /** @defgroup TIM_Private_Functions TIM Private Functions
01886 * @{
01887 */
01888 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
01889 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
01890 void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
01891 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
01892 void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
01893 void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
01894 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
01895                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
01896 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
01897 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
01898 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
01899 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
01900
01901 /**
01902 * @}
01903 */
01904 /* End of private functions --------------------------------------------------*/
01905 /**
01906   * @}
01907   */
01908
01909 /**
01910   * @}
01911   */
01912
01913 #ifdef __cplusplus
01914 }
01915 #endif
01916
01917 #endif /* __STM32H7xx_HAL_TIM_H */
01918
01919 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_tim_ex.c Source File

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stm32h7xx_hal_tim_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_tim_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   TIM HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Timer Extended peripheral:
00010   *           + Time Hall Sensor Interface Initialization
00011   *           + Time Hall Sensor Interface Start
00012   *           + Time Complementary signal bread and dead time configuration
00013   *           + Time Master and Slave synchronization configuration
00014   *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
00015   *           + Time OCRef clear configuration
00016   *           + Timer remapping capabilities configuration
00017   @verbatim
00018   ==============================================================================
00019                       ##### TIM Extended features #####
00020   ==============================================================================
00021   [..]
00022     The Timer Extended features include:
00023     (#) Complementary outputs with programmable dead-time for :
00024         (++) Output Compare
00025         (++) PWM generation (Edge and Center-aligned Mode)
00026         (++) One-pulse mode output
00027     (#) Synchronization circuit to control the timer with external signals and to
00028         interconnect several timers together.
00029     (#) Break input to put the timer output signals in reset state or in a known state.
00030     (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
00031         positioning purposes
00032
00033             ##### How to use this driver #####
00034   ==============================================================================
00035     [..]
00036      (#) Initialize the TIM low level resources by implementing the following functions
00037          depending from feature used :
00038            (++) Complementary Output Compare : HAL_TIM_OC_MspInit().
00039            (++) Complementary PWM generation : HAL_TIM_PWM_MspInit().
00040            (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit().
00041            (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit().
00042
00043      (#) Initialize the TIM low level resources :
00044         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
00045         (##) TIM pins configuration
00046             (+++) Enable the clock for the TIM GPIOs using the following function:
00047               __HAL_RCC_GPIOx_CLK_ENABLE();
00048             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00049
00050      (#) The external Clock can be configured, if needed (the default clock is the
00051          internal clock from the APBx), using the following function:
00052          HAL_TIM_ConfigClockSource, the clock configuration should be done before
00053          any start function.
00054
00055      (#) Configure the TIM in the desired functioning mode using one of the
00056          initialization function of this driver:
00057           (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
00058               Timer Hall Sensor Interface and the commutation event with the corresponding
00059               Interrupt and DMA request if needed (Note that One Timer is used to interface
00060              with the Hall sensor Interface and another Timer should be used to use
00061              the commutation event).
00062
00063      (#) Activate the TIM peripheral using one of the start functions:
00064            (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT().
00065            (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT().
00066            (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT().
00067            (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
00068
00069
00070   @endverbatim
00071   ******************************************************************************
00072   * @attention
00073   *
00074   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00075   *
00076   * Redistribution and use in source and binary forms, with or without modification,
00077   * are permitted provided that the following conditions are met:
00078   *   1. Redistributions of source code must retain the above copyright notice,
00079   *      this list of conditions and the following disclaimer.
00080   *   2. Redistributions in binary form must reproduce the above copyright notice,
00081   *      this list of conditions and the following disclaimer in the documentation
00082   *      and/or other materials provided with the distribution.
00083   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00084   *      may be used to endorse or promote products derived from this software
00085   *      without specific prior written permission.
00086   *
00087   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00088   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00089   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00090   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00091   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00092   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00093   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00094   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00095   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00096   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00097   *
00098   ******************************************************************************
00099 */
00100
00101 /* Includes ------------------------------------------------------------------*/
00102 #include "stm32h7xx_hal.h"
00103
00104 /** @addtogroup STM32H7xx_HAL_Driver
00105   * @{
00106   */
00107
00108 /** @defgroup TIMEx TIMEx
00109   * @brief TIM Extended HAL module driver
00110   * @{
00111   */
00112
00113 #ifdef HAL_TIM_MODULE_ENABLED
00114
00115 /* Private typedef -----------------------------------------------------------*/
00116 /* Private define ------------------------------------------------------------*/
00117 #define BDTR_BKF_SHIFT (16)
00118 #define BDTR_BK2F_SHIFT (20)
00119 #define TIMx_ETRSEL_MASK ((uint32_t)0x003C000)
00120 #define TIMx_TIxSEL_MASK ((uint32_t)0x000000F)
00121 /* Private macro -------------------------------------------------------------*/
00122 /* Private variables ---------------------------------------------------------*/
00123 /* Private function prototypes -----------------------------------------------*/
00124 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
00125
00126 /* Private functions ---------------------------------------------------------*/
00127
00128 /* Exported functions --------------------------------------------------------*/
00129 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
00130   * @{
00131   */
00132
00133 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
00134   * @brief    TIM Hall Sensor functions
00135   *
00136 @verbatim
00137   ==============================================================================
00138                       ##### TIM Hall Sensor functions #####
00139   ==============================================================================
00140   [..]
00141     This section provides functions allowing to:
00142     (+) Initialize and configure TIM HAL Sensor.
00143     (+) De-initialize TIM HAL Sensor.
00144     (+) Start the Hall Sensor Interface.
00145     (+) Stop the Hall Sensor Interface.
00146     (+) Start the Hall Sensor Interface and enable interrupts.
00147     (+) Stop the Hall Sensor Interface and disable interrupts.
00148     (+) Start the Hall Sensor Interface and enable DMA transfers.
00149     (+) Stop the Hall Sensor Interface and disable DMA transfers.
00150
00151 @endverbatim
00152   * @{
00153   */
00154 /**
00155   * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
00156   * @param  htim: TIM Encoder Interface handle
00157   * @param  sConfig: TIM Hall Sensor configuration structure.
00158   * @retval HAL status
00159   */
00160 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
00161 {
00162   TIM_OC_InitTypeDef OC_Config;
00163
00164   /* Check the TIM handle allocation */
00165   if(htim == NULL)
00166   {
00167     return HAL_ERROR;
00168   }
00169
00170   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00171   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00172   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00173   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
00174   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
00175   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
00176
00177   if(htim->State == HAL_TIM_STATE_RESET)
00178   {
00179     /* Allocate lock resource and initialize it */
00180     htim->Lock = HAL_UNLOCKED;
00181
00182     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00183     HAL_TIMEx_HallSensor_MspInit(htim);
00184   }
00185
00186   /* Set the TIM state */
00187   htim->State = HAL_TIM_STATE_BUSY;
00188
00189   /* Configure the Time base in the Encoder Mode */
00190   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00191
00192   /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
00193   TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
00194
00195   /* Reset the IC1PSC Bits */
00196   htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
00197   /* Set the IC1PSC value */
00198   htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
00199
00200   /* Enable the Hall sensor interface (XOR function of the three inputs) */
00201   htim->Instance->CR2 |= TIM_CR2_TI1S;
00202
00203   /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
00204   htim->Instance->SMCR &= ~TIM_SMCR_TS;
00205   htim->Instance->SMCR |= TIM_TS_TI1F_ED;
00206
00207   /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
00208   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
00209   htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
00210
00211   /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
00212   OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
00213   OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
00214   OC_Config.OCMode = TIM_OCMODE_PWM2;
00215   OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
00216   OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
00217   OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
00218   OC_Config.Pulse = sConfig->Commutation_Delay;
00219
00220   TIM_OC2_SetConfig(htim->Instance, &OC_Config);
00221
00222   /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
00223     register to 101 */
00224   htim->Instance->CR2 &= ~TIM_CR2_MMS;
00225   htim->Instance->CR2 |= TIM_TRGO_OC2REF;
00226
00227   /* Initialize the TIM state*/
00228   htim->State= HAL_TIM_STATE_READY;
00229
00230   return HAL_OK;
00231 }
00232
00233 /**
00234   * @brief  DeInitialize the TIM Hall Sensor interface
00235   * @param  htim: TIM Hall Sensor handle.
00236   * @retval HAL status
00237   */
00238 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
00239 {
00240   /* Check the parameters */
00241   assert_param(IS_TIM_INSTANCE(htim->Instance));
00242
00243   htim->State = HAL_TIM_STATE_BUSY;
00244
00245   /* Disable the TIM Peripheral Clock */
00246   __HAL_TIM_DISABLE(htim);
00247
00248   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00249   HAL_TIMEx_HallSensor_MspDeInit(htim);
00250
00251   /* Change TIM state */
00252   htim->State = HAL_TIM_STATE_RESET;
00253
00254   /* Release Lock */
00255   __HAL_UNLOCK(htim);
00256
00257   return HAL_OK;
00258 }
00259
00260 /**
00261   * @brief  Initializes the TIM Hall Sensor MSP.
00262   * @param  htim: TIM handle
00263   * @retval None
00264   */
00265 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
00266 {
00267   /* Prevent unused argument(s) compilation warning */
00268   UNUSED(htim);
00269
00270   /* NOTE : This function Should not be modified, when the callback is needed,
00271             the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
00272    */
00273 }
00274
00275 /**
00276   * @brief  DeInitialize TIM Hall Sensor MSP.
00277   * @param  htim: TIM handle
00278   * @retval None
00279   */
00280 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
00281 {
00282   /* Prevent unused argument(s) compilation warning */
00283   UNUSED(htim);
00284
00285   /* NOTE : This function Should not be modified, when the callback is needed,
00286             the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
00287    */
00288 }
00289
00290 /**
00291   * @brief  Starts the TIM Hall Sensor Interface.
00292   * @param  htim : TIM Hall Sensor handle
00293   * @retval HAL status
00294   */
00295 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
00296 {
00297   /* Check the parameters */
00298   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00299
00300   /* Enable the Input Capture channels 1
00301     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00302   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00303
00304   /* Enable the Peripheral */
00305   __HAL_TIM_ENABLE(htim);
00306
00307   /* Return function status */
00308   return HAL_OK;
00309 }
00310
00311 /**
00312   * @brief  Stops the TIM Hall sensor Interface.
00313   * @param  htim : TIM Hall Sensor handle
00314   * @retval HAL status
00315   */
00316 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
00317 {
00318   /* Check the parameters */
00319   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00320
00321   /* Disable the Input Capture channels 1, 2 and 3
00322     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00323   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00324
00325   /* Disable the Peripheral */
00326   __HAL_TIM_DISABLE(htim);
00327
00328   /* Return function status */
00329   return HAL_OK;
00330 }
00331
00332 /**
00333   * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
00334   * @param  htim : TIM Hall Sensor handle.
00335   * @retval HAL status
00336   */
00337 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
00338 {
00339   /* Check the parameters */
00340   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00341
00342   /* Enable the capture compare Interrupts 1 event */
00343   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00344
00345   /* Enable the Input Capture channels 1
00346     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00347   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00348
00349   /* Enable the Peripheral */
00350   __HAL_TIM_ENABLE(htim);
00351
00352   /* Return function status */
00353   return HAL_OK;
00354 }
00355
00356 /**
00357   * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
00358   * @param  htim : TIM handle.
00359   * @retval HAL status
00360   */
00361 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
00362 {
00363   /* Check the parameters */
00364   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00365
00366   /* Disable the Input Capture channels 1
00367     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00368   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00369
00370   /* Disable the capture compare Interrupts event */
00371   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00372
00373   /* Disable the Peripheral */
00374   __HAL_TIM_DISABLE(htim);
00375
00376   /* Return function status */
00377   return HAL_OK;
00378 }
00379
00380 /**
00381   * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
00382   * @param  htim : TIM Hall Sensor handle.
00383   * @param  pData: The destination Buffer address.
00384   * @param  Length: The length of data to be transferred from TIM peripheral to memory.
00385   * @retval HAL status
00386   */
00387 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
00388 {
00389   /* Check the parameters */
00390   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00391
00392    if((htim->State) == (HAL_TIM_STATE_BUSY))
00393   {
00394      return HAL_BUSY;
00395   }
00396   else if((htim->State) == (HAL_TIM_STATE_READY))
00397   {
00398     if(((uint32_t)pData == 0 ) && (Length > 0))
00399     {
00400       return HAL_ERROR;
00401     }
00402     else
00403     {
00404       htim->State = HAL_TIM_STATE_BUSY;
00405     }
00406   }
00407   /* Enable the Input Capture channels 1
00408     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00409   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00410
00411   /* Set the DMA Input Capture 1 Callback */
00412   htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
00413   /* Set the DMA error callback */
00414   htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
00415
00416   /* Enable the DMA channel for Capture 1*/
00417   HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
00418
00419   /* Enable the capture compare 1 Interrupt */
00420   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00421
00422   /* Enable the Peripheral */
00423   __HAL_TIM_ENABLE(htim);
00424
00425   /* Return function status */
00426   return HAL_OK;
00427 }
00428
00429 /**
00430   * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
00431   * @param  htim : TIM handle.
00432   * @retval HAL status
00433   */
00434 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
00435 {
00436   /* Check the parameters */
00437   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00438
00439   /* Disable the Input Capture channels 1
00440     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00441   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00442
00443
00444   /* Disable the capture compare Interrupts 1 event */
00445   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00446
00447   /* Disable the Peripheral */
00448   __HAL_TIM_DISABLE(htim);
00449
00450   /* Return function status */
00451   return HAL_OK;
00452 }
00453
00454 /**
00455   * @}
00456   */
00457
00458 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
00459   *  @brief   TIM Complementary Output Compare functions
00460   *
00461 @verbatim
00462   ==============================================================================
00463               ##### TIM Complementary Output Compare functions #####
00464   ==============================================================================
00465   [..]
00466     This section provides functions allowing to:
00467     (+) Start the Complementary Output Compare/PWM.
00468     (+) Stop the Complementary Output Compare/PWM.
00469     (+) Start the Complementary Output Compare/PWM and enable interrupts.
00470     (+) Stop the Complementary Output Compare/PWM and disable interrupts.
00471     (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
00472     (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
00473
00474 @endverbatim
00475   * @{
00476   */
00477
00478 /**
00479   * @brief  Starts the TIM Output Compare signal generation on the complementary
00480   *         output.
00481   * @param  htim : TIM Output Compare handle
00482   * @param  Channel : TIM Channel to be enabled.
00483   *          This parameter can be one of the following values:
00484   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00485   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00486   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00487   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00488   * @retval HAL status
00489   */
00490 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00491 {
00492   /* Check the parameters */
00493   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00494
00495      /* Enable the Capture compare channel N */
00496      TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00497
00498   /* Enable the Main Ouput */
00499     __HAL_TIM_MOE_ENABLE(htim);
00500
00501   /* Enable the Peripheral */
00502   __HAL_TIM_ENABLE(htim);
00503
00504   /* Return function status */
00505   return HAL_OK;
00506 }
00507
00508 /**
00509   * @brief  Stops the TIM Output Compare signal generation on the complementary
00510   *         output.
00511   * @param  htim : TIM handle
00512   * @param  Channel : TIM Channel to be disabled.
00513   *          This parameter can be one of the following values:
00514   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00515   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00516   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00517   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00518   * @retval HAL status
00519   */
00520 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00521 {
00522   /* Check the parameters */
00523   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00524
00525     /* Disable the Capture compare channel N */
00526   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00527
00528   /* Disable the Main Ouput */
00529     __HAL_TIM_MOE_DISABLE(htim);
00530
00531   /* Disable the Peripheral */
00532   __HAL_TIM_DISABLE(htim);
00533
00534   /* Return function status */
00535   return HAL_OK;
00536 }
00537
00538 /**
00539   * @brief  Starts the TIM Output Compare signal generation in interrupt mode
00540   *         on the complementary output.
00541   * @param  htim : TIM OC handle
00542   * @param  Channel : TIM Channel to be enabled.
00543   *          This parameter can be one of the following values:
00544   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00545   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00546   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00547   * @retval HAL status
00548   */
00549 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00550 {
00551   /* Check the parameters */
00552   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00553
00554   switch (Channel)
00555   {
00556     case TIM_CHANNEL_1:
00557     {
00558       /* Enable the TIM Output Compare interrupt */
00559       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00560     }
00561     break;
00562
00563     case TIM_CHANNEL_2:
00564     {
00565       /* Enable the TIM Output Compare interrupt */
00566       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00567     }
00568     break;
00569
00570     case TIM_CHANNEL_3:
00571     {
00572       /* Enable the TIM Output Compare interrupt */
00573       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00574     }
00575     break;
00576
00577     default:
00578     break;
00579   }
00580
00581   /* Enable the TIM Break interrupt */
00582   __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
00583
00584   /* Enable the Capture compare channel N */
00585   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00586
00587   /* Enable the Main Ouput */
00588   __HAL_TIM_MOE_ENABLE(htim);
00589
00590   /* Enable the Peripheral */
00591   __HAL_TIM_ENABLE(htim);
00592
00593   /* Return function status */
00594   return HAL_OK;
00595 }
00596
00597 /**
00598   * @brief  Stops the TIM Output Compare signal generation in interrupt mode
00599   *         on the complementary output.
00600   * @param  htim : TIM Output Compare handle.
00601   * @param  Channel : TIM Channel to be disabled.
00602   *          This parameter can be one of the following values:
00603   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00604   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00605   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00606   * @retval HAL status
00607   */
00608 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00609 {
00610   uint32_t tmpccer = 0;
00611
00612   /* Check the parameters */
00613   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00614
00615   switch (Channel)
00616   {
00617     case TIM_CHANNEL_1:
00618     {
00619       /* Disable the TIM Output Compare interrupt */
00620       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00621     }
00622     break;
00623
00624     case TIM_CHANNEL_2:
00625     {
00626       /* Disable the TIM Output Compare interrupt */
00627       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
00628     }
00629     break;
00630
00631     case TIM_CHANNEL_3:
00632     {
00633       /* Disable the TIM Output Compare interrupt */
00634       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
00635     }
00636     break;
00637
00638     default:
00639     break;
00640   }
00641
00642   /* Disable the Capture compare channel N */
00643   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00644
00645   /* Disable the TIM Break interrupt (only if no more channel is active) */
00646   tmpccer = htim->Instance->CCER;
00647   if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
00648   {
00649     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
00650   }
00651
00652   /* Disable the Main Ouput */
00653     __HAL_TIM_MOE_DISABLE(htim);
00654
00655   /* Disable the Peripheral */
00656   __HAL_TIM_DISABLE(htim);
00657
00658   /* Return function status */
00659   return HAL_OK;
00660 }
00661
00662 /**
00663   * @brief  Starts the TIM Output Compare signal generation in DMA mode
00664   *         on the complementary output.
00665   * @param  htim : TIM Output Compare handle
00666   * @param  Channel : TIM Channel to be enabled.
00667   *          This parameter can be one of the following values:
00668   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00669   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00670   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00671   * @param  pData: The source Buffer address.
00672   * @param  Length: The length of data to be transferred from memory to TIM peripheral
00673   * @retval HAL status
00674   */
00675 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
00676 {
00677   /* Check the parameters */
00678   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00679
00680   if((htim->State) == (HAL_TIM_STATE_BUSY))
00681   {
00682      return HAL_BUSY;
00683   }
00684   else if((htim->State) == (HAL_TIM_STATE_READY))
00685   {
00686     if(((uint32_t)pData == 0 ) && (Length > 0))
00687     {
00688       return HAL_ERROR;
00689     }
00690     else
00691     {
00692       htim->State = HAL_TIM_STATE_BUSY;
00693     }
00694   }
00695   switch (Channel)
00696   {
00697     case TIM_CHANNEL_1:
00698     {
00699       /* Set the DMA Period elapsed callback */
00700       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
00701
00702       /* Set the DMA error callback */
00703       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
00704
00705       /* Enable the DMA channel */
00706       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
00707
00708       /* Enable the TIM Output Compare DMA request */
00709       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00710     }
00711     break;
00712
00713     case TIM_CHANNEL_2:
00714     {
00715       /* Set the DMA Period elapsed callback */
00716       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
00717
00718       /* Set the DMA error callback */
00719       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
00720
00721       /* Enable the DMA channel */
00722       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
00723
00724       /* Enable the TIM Output Compare DMA request */
00725       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
00726     }
00727     break;
00728
00729     case TIM_CHANNEL_3:
00730 {
00731       /* Set the DMA Period elapsed callback */
00732       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
00733
00734       /* Set the DMA error callback */
00735       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
00736
00737       /* Enable the DMA channel */
00738       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
00739
00740       /* Enable the TIM Output Compare DMA request */
00741       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
00742     }
00743     break;
00744
00745     default:
00746     break;
00747   }
00748
00749   /* Enable the Capture compare channel N */
00750   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00751
00752   /* Enable the Main Ouput */
00753   __HAL_TIM_MOE_ENABLE(htim);
00754
00755   /* Enable the Peripheral */
00756   __HAL_TIM_ENABLE(htim);
00757
00758   /* Return function status */
00759   return HAL_OK;
00760 }
00761
00762 /**
00763   * @brief  Stops the TIM Output Compare signal generation in DMA mode
00764   *         on the complementary output.
00765   * @param  htim : TIM Output Compare handle
00766   * @param  Channel : TIM Channel to be disabled.
00767   *          This parameter can be one of the following values:
00768   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00769   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00770   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00771   * @retval HAL status
00772   */
00773 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
00774 {
00775   /* Check the parameters */
00776   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00777
00778   switch (Channel)
00779   {
00780     case TIM_CHANNEL_1:
00781     {
00782       /* Disable the TIM Output Compare DMA request */
00783       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00784     }
00785     break;
00786
00787     case TIM_CHANNEL_2:
00788     {
00789       /* Disable the TIM Output Compare DMA request */
00790       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
00791     }
00792     break;
00793
00794     case TIM_CHANNEL_3:
00795     {
00796       /* Disable the TIM Output Compare DMA request */
00797       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
00798     }
00799     break;
00800
00801     default:
00802     break;
00803   }
00804
00805   /* Disable the Capture compare channel N */
00806   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00807
00808   /* Disable the Main Ouput */
00809   __HAL_TIM_MOE_DISABLE(htim);
00810
00811   /* Disable the Peripheral */
00812   __HAL_TIM_DISABLE(htim);
00813
00814   /* Change the htim state */
00815   htim->State = HAL_TIM_STATE_READY;
00816
00817   /* Return function status */
00818   return HAL_OK;
00819 }
00820
00821 /**
00822   * @}
00823   */
00824
00825 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
00826   * @brief    TIM Complementary PWM functions
00827   *
00828 @verbatim
00829   ==============================================================================
00830                  ##### TIM Complementary PWM functions #####
00831   ==============================================================================
00832   [..]
00833     This section provides functions allowing to:
00834     (+) Start the Complementary PWM.
00835     (+) Stop the Complementary PWM.
00836     (+) Start the Complementary PWM and enable interrupts.
00837     (+) Stop the Complementary PWM and disable interrupts.
00838     (+) Start the Complementary PWM and enable DMA transfers.
00839     (+) Stop the Complementary PWM and disable DMA transfers.
00840     (+) Start the Complementary Input Capture measurement.
00841     (+) Stop the Complementary Input Capture.
00842     (+) Start the Complementary Input Capture and enable interrupts.
00843     (+) Stop the Complementary Input Capture and disable interrupts.
00844     (+) Start the Complementary Input Capture and enable DMA transfers.
00845     (+) Stop the Complementary Input Capture and disable DMA transfers.
00846     (+) Start the Complementary One Pulse generation.
00847     (+) Stop the Complementary One Pulse.
00848     (+) Start the Complementary One Pulse and enable interrupts.
00849     (+) Stop the Complementary One Pulse and disable interrupts.
00850
00851 @endverbatim
00852   * @{
00853   */
00854
00855 /**
00856   * @brief  Starts the PWM signal generation on the complementary output.
00857   * @param  htim : TIM handle
00858   * @param  Channel : TIM Channel to be enabled.
00859   *          This parameter can be one of the following values:
00860   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00861   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00862   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00863   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00864   * @retval HAL status
00865   */
00866 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00867 {
00868   /* Check the parameters */
00869   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00870
00871   /* Enable the complementary PWM output  */
00872   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00873
00874   /* Enable the Main Ouput */
00875   __HAL_TIM_MOE_ENABLE(htim);
00876
00877   /* Enable the Peripheral */
00878   __HAL_TIM_ENABLE(htim);
00879
00880   /* Return function status */
00881   return HAL_OK;
00882 }
00883
00884 /**
00885   * @brief  Stops the PWM signal generation on the complementary output.
00886   * @param  htim : TIM handle
00887   * @param  Channel : TIM Channel to be disabled.
00888   *          This parameter can be one of the following values:
00889   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00890   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00891   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00892   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00893   * @retval HAL status
00894   */
00895 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00896 {
00897   /* Check the parameters */
00898   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00899
00900   /* Disable the complementary PWM output  */
00901   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00902
00903   /* Disable the Main Ouput */
00904   __HAL_TIM_MOE_DISABLE(htim);
00905
00906   /* Disable the Peripheral */
00907   __HAL_TIM_DISABLE(htim);
00908
00909   /* Return function status */
00910   return HAL_OK;
00911 }
00912
00913 /**
00914   * @brief  Starts the PWM signal generation in interrupt mode on the
00915   *         complementary output.
00916   * @param  htim : TIM handle
00917   * @param  Channel : TIM Channel to be disabled.
00918   *          This parameter can be one of the following values:
00919   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00920   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00921   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00922   * @retval HAL status
00923   */
00924 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00925 {
00926   /* Check the parameters */
00927   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00928
00929   switch (Channel)
00930   {
00931     case TIM_CHANNEL_1:
00932     {
00933       /* Enable the TIM Capture/Compare 1 interrupt */
00934       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00935     }
00936     break;
00937
00938     case TIM_CHANNEL_2:
00939     {
00940       /* Enable the TIM Capture/Compare 2 interrupt */
00941       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00942     }
00943     break;
00944
00945     case TIM_CHANNEL_3:
00946     {
00947       /* Enable the TIM Capture/Compare 3 interrupt */
00948       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00949     }
00950     break;
00951
00952     default:
00953     break;
00954   }
00955
00956   /* Enable the TIM Break interrupt */
00957   __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
00958
00959   /* Enable the complementary PWM output  */
00960   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00961
00962   /* Enable the Main Ouput */
00963   __HAL_TIM_MOE_ENABLE(htim);
00964
00965   /* Enable the Peripheral */
00966   __HAL_TIM_ENABLE(htim);
00967
00968   /* Return function status */
00969   return HAL_OK;
00970 }
00971
00972 /**
00973   * @brief  Stops the PWM signal generation in interrupt mode on the
00974   *         complementary output.
00975   * @param  htim : TIM handle
00976   * @param  Channel : TIM Channel to be disabled.
00977   *          This parameter can be one of the following values:
00978   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00979   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00980   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00981   * @retval HAL status
00982   */
00983 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
00984 {
00985   uint32_t tmpccer = 0;
00986
00987   /* Check the parameters */
00988   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00989
00990   switch (Channel)
00991   {
00992     case TIM_CHANNEL_1:
00993     {
00994       /* Disable the TIM Capture/Compare 1 interrupt */
00995       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00996     }
00997     break;
00998
00999     case TIM_CHANNEL_2:
01000     {
01001       /* Disable the TIM Capture/Compare 2 interrupt */
01002       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01003     }
01004     break;
01005
01006     case TIM_CHANNEL_3:
01007     {
01008       /* Disable the TIM Capture/Compare 3 interrupt */
01009       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01010     }
01011     break;
01012
01013     default:
01014     break;
01015   }
01016
01017   /* Disable the complementary PWM output  */
01018   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01019
01020   /* Disable the TIM Break interrupt (only if no more channel is active) */
01021   tmpccer = htim->Instance->CCER;
01022   if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
01023   {
01024     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
01025   }
01026
01027   /* Disable the Main Ouput */
01028   __HAL_TIM_MOE_DISABLE(htim);
01029
01030   /* Disable the Peripheral */
01031   __HAL_TIM_DISABLE(htim);
01032
01033   /* Return function status */
01034   return HAL_OK;
01035 }
01036
01037 /**
01038   * @brief  Start the TIM PWM signal generation in DMA mode on the
01039   *         complementary output
01040   * @param  htim : TIM handle
01041   * @param  Channel : TIM Channel to be enabled.
01042   *          This parameter can be one of the following values:
01043   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01044   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01045   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01046   * @param  pData: The source Buffer address.
01047   * @param  Length: The length of data to be transferred from memory to TIM peripheral
01048   * @retval HAL status
01049   */
01050 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01051 {
01052   /* Check the parameters */
01053   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01054
01055   if((htim->State) == (HAL_TIM_STATE_BUSY))
01056   {
01057      return HAL_BUSY;
01058   }
01059   else if((htim->State) == (HAL_TIM_STATE_READY))
01060   {
01061     if(((uint32_t)pData == 0 ) && (Length > 0))
01062     {
01063       return HAL_ERROR;
01064     }
01065     else
01066     {
01067       htim->State = HAL_TIM_STATE_BUSY;
01068     }
01069   }
01070   switch (Channel)
01071   {
01072     case TIM_CHANNEL_1:
01073     {
01074       /* Set the DMA Period elapsed callback */
01075       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
01076
01077       /* Set the DMA error callback */
01078       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
01079
01080       /* Enable the DMA channel */
01081       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
01082
01083       /* Enable the TIM Capture/Compare 1 DMA request */
01084       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01085     }
01086     break;
01087
01088     case TIM_CHANNEL_2:
01089     {
01090       /* Set the DMA Period elapsed callback */
01091       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
01092
01093       /* Set the DMA error callback */
01094       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
01095
01096       /* Enable the DMA channel */
01097       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
01098
01099       /* Enable the TIM Capture/Compare 2 DMA request */
01100       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01101     }
01102     break;
01103
01104     case TIM_CHANNEL_3:
01105     {
01106       /* Set the DMA Period elapsed callback */
01107       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
01108
01109       /* Set the DMA error callback */
01110       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
01111
01112       /* Enable the DMA channel */
01113       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
01114
01115       /* Enable the TIM Capture/Compare 3 DMA request */
01116       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01117     }
01118     break;
01119
01120     default:
01121     break;
01122   }
01123
01124   /* Enable the complementary PWM output  */
01125      TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01126
01127   /* Enable the Main Ouput */
01128     __HAL_TIM_MOE_ENABLE(htim);
01129
01130   /* Enable the Peripheral */
01131   __HAL_TIM_ENABLE(htim);
01132
01133   /* Return function status */
01134   return HAL_OK;
01135 }
01136
01137 /**
01138   * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
01139   *         output
01140   * @param  htim : TIM handle
01141   * @param  Channel : TIM Channel to be disabled.
01142   *          This parameter can be one of the following values:
01143   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01144   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01145   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01146   * @retval HAL status
01147   */
01148 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01149 {
01150   /* Check the parameters */
01151   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01152
01153   switch (Channel)
01154   {
01155     case TIM_CHANNEL_1:
01156     {
01157       /* Disable the TIM Capture/Compare 1 DMA request */
01158       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01159     }
01160     break;
01161
01162     case TIM_CHANNEL_2:
01163     {
01164       /* Disable the TIM Capture/Compare 2 DMA request */
01165       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01166     }
01167     break;
01168
01169     case TIM_CHANNEL_3:
01170     {
01171       /* Disable the TIM Capture/Compare 3 DMA request */
01172       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01173     }
01174     break;
01175
01176     default:
01177     break;
01178   }
01179
01180   /* Disable the complementary PWM output */
01181     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01182
01183   /* Disable the Main Ouput */
01184     __HAL_TIM_MOE_DISABLE(htim);
01185
01186   /* Disable the Peripheral */
01187   __HAL_TIM_DISABLE(htim);
01188
01189   /* Change the htim state */
01190   htim->State = HAL_TIM_STATE_READY;
01191
01192   /* Return function status */
01193   return HAL_OK;
01194 }
01195
01196 /**
01197   * @}
01198   */
01199
01200 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
01201   * @brief    TIM Complementary One Pulse functions
01202   *
01203 @verbatim
01204   ==============================================================================
01205                 ##### TIM Complementary One Pulse functions #####
01206   ==============================================================================
01207   [..]
01208     This section provides functions allowing to:
01209     (+) Start the Complementary One Pulse generation.
01210     (+) Stop the Complementary One Pulse.
01211     (+) Start the Complementary One Pulse and enable interrupts.
01212     (+) Stop the Complementary One Pulse and disable interrupts.
01213
01214 @endverbatim
01215   * @{
01216   */
01217
01218 /**
01219   * @brief  Starts the TIM One Pulse signal generation on the complemetary
01220   *         output.
01221   * @param  htim : TIM One Pulse handle
01222   * @param  OutputChannel : TIM Channel to be enabled.
01223   *          This parameter can be one of the following values:
01224   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01225   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01226   * @retval HAL status
01227   */
01228 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01229   {
01230   /* Check the parameters */
01231   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01232
01233   /* Enable the complementary One Pulse output */
01234   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01235
01236   /* Enable the Main Ouput */
01237   __HAL_TIM_MOE_ENABLE(htim);
01238
01239   /* Return function status */
01240   return HAL_OK;
01241 }
01242
01243 /**
01244   * @brief  Stops the TIM One Pulse signal generation on the complementary
01245   *         output.
01246   * @param  htim : TIM One Pulse handle
01247   * @param  OutputChannel : TIM Channel to be disabled.
01248   *          This parameter can be one of the following values:
01249   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01250   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01251   * @retval HAL status
01252   */
01253 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01254 {
01255
01256   /* Check the parameters */
01257   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01258
01259   /* Disable the complementary One Pulse output */
01260     TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01261
01262   /* Disable the Main Ouput */
01263     __HAL_TIM_MOE_DISABLE(htim);
01264
01265   /* Disable the Peripheral */
01266   __HAL_TIM_DISABLE(htim);
01267
01268   /* Return function status */
01269   return HAL_OK;
01270 }
01271
01272 /**
01273   * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
01274   *         complementary channel.
01275   * @param  htim : TIM One Pulse handle
01276   * @param  OutputChannel : TIM Channel to be enabled.
01277   *          This parameter can be one of the following values:
01278   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01279   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01280   * @retval HAL status
01281   */
01282 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01283 {
01284   /* Check the parameters */
01285   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01286
01287   /* Enable the TIM Capture/Compare 1 interrupt */
01288   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01289
01290   /* Enable the TIM Capture/Compare 2 interrupt */
01291   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01292
01293   /* Enable the complementary One Pulse output */
01294   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01295
01296   /* Enable the Main Ouput */
01297   __HAL_TIM_MOE_ENABLE(htim);
01298
01299   /* Return function status */
01300   return HAL_OK;
01301   }
01302
01303 /**
01304   * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
01305   *         complementary channel.
01306   * @param  htim : TIM One Pulse handle
01307   * @param  OutputChannel : TIM Channel to be disabled.
01308   *          This parameter can be one of the following values:
01309   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01310   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01311   * @retval HAL status
01312   */
01313 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01314 {
01315   /* Check the parameters */
01316   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01317
01318   /* Disable the TIM Capture/Compare 1 interrupt */
01319   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01320
01321   /* Disable the TIM Capture/Compare 2 interrupt */
01322   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01323
01324   /* Disable the complementary One Pulse output */
01325   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01326
01327   /* Disable the Main Ouput */
01328   __HAL_TIM_MOE_DISABLE(htim);
01329
01330   /* Disable the Peripheral */
01331    __HAL_TIM_DISABLE(htim);
01332
01333   /* Return function status */
01334   return HAL_OK;
01335 }
01336
01337 /**
01338   * @}
01339   */
01340 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
01341   * @brief    Peripheral Control functions
01342   *
01343 @verbatim
01344   ==============================================================================
01345                     ##### Peripheral Control functions #####
01346   ==============================================================================
01347   [..]
01348     This section provides functions allowing to:
01349       (+) Configure the commutation event in case of use of the Hall sensor interface.
01350       (+) Configure Output channels for OC and PWM mode.
01351       (+) Configure Complementary channels, break features and dead time.
01352       (+) Configure Master synchronization.
01353       (+) Configure timer remapping capabilities.
01354       (+) Enable or disable channel grouping
01355
01356 @endverbatim
01357   * @{
01358   */
01359 /**
01360   * @brief  Configure the TIM commutation event sequence.
01361   * @note: this function is mandatory to use the commutation event in order to
01362   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01363   *        the typical use of this feature is with the use of another Timer(interface Timer)
01364   *        configured in Hall sensor interface, this interface Timer will generate the
01365   *        commutation at its TRGO output (connected to Timer used in this function) each time
01366   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01367   * @param  htim: TIM handle
01368   * @param  InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
01369   *          This parameter can be one of the following values:
01370   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01371   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01372   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01373   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01374   *            @arg TIM_TS_NONE: No trigger is needed
01375   * @param  CommutationSource : the Commutation Event source.
01376   *          This parameter can be one of the following values:
01377   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01378   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01379   * @retval HAL status
01380   */
01381 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
01382 {
01383   /* Check the parameters */
01384   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01385   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01386
01387   __HAL_LOCK(htim);
01388
01389   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01390       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01391   {
01392     /* Select the Input trigger */
01393     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01394     htim->Instance->SMCR |= InputTrigger;
01395   }
01396
01397   /* Select the Capture Compare preload feature */
01398   htim->Instance->CR2 |= TIM_CR2_CCPC;
01399   /* Select the Commutation event source */
01400   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01401   htim->Instance->CR2 |= CommutationSource;
01402
01403   __HAL_UNLOCK(htim);
01404
01405   return HAL_OK;
01406 }
01407
01408 /**
01409   * @brief  Configure the TIM commutation event sequence with interrupt.
01410   * @note: this function is mandatory to use the commutation event in order to
01411   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01412   *        the typical use of this feature is with the use of another Timer(interface Timer)
01413   *        configured in Hall sensor interface, this interface Timer will generate the
01414   *        commutation at its TRGO output (connected to Timer used in this function) each time
01415   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01416   * @param  htim: TIM handle
01417   * @param  InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
01418   *          This parameter can be one of the following values:
01419   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01420   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01421   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01422   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01423   *            @arg TIM_TS_NONE: No trigger is needed
01424   * @param  CommutationSource : the Commutation Event source.
01425   *          This parameter can be one of the following values:
01426   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01427   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01428   * @retval HAL status
01429   */
01430 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
01431 {
01432   /* Check the parameters */
01433   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01434   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01435
01436   __HAL_LOCK(htim);
01437
01438   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01439       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01440   {
01441     /* Select the Input trigger */
01442     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01443     htim->Instance->SMCR |= InputTrigger;
01444   }
01445
01446   /* Select the Capture Compare preload feature */
01447   htim->Instance->CR2 |= TIM_CR2_CCPC;
01448   /* Select the Commutation event source */
01449   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01450   htim->Instance->CR2 |= CommutationSource;
01451
01452   /* Enable the Commutation Interrupt Request */
01453   __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
01454
01455   __HAL_UNLOCK(htim);
01456
01457   return HAL_OK;
01458 }
01459
01460 /**
01461   * @brief  Configure the TIM commutation event sequence with DMA.
01462   * @note:  this function is mandatory to use the commutation event in order to
01463   *         update the configuration at each commutation detection on the TRGI input of the Timer,
01464   *         the typical use of this feature is with the use of another Timer(interface Timer)
01465   *         configured in Hall sensor interface, this interface Timer will generate the
01466   *         commutation at its TRGO output (connected to Timer used in this function) each time
01467   *         the TI1 of the Interface Timer detect a commutation at its input TI1.
01468   * @note:  The user should configure the DMA in his own software, in This function only the COMDE bit is set.
01469   * @param  htim: TIM handle
01470   * @param  InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
01471   *          This parameter can be one of the following values:
01472   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01473   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01474   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01475   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01476   *            @arg TIM_TS_NONE: No trigger is needed
01477   * @param  CommutationSource : the Commutation Event source.
01478   *          This parameter can be one of the following values:
01479   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01480   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01481   * @retval HAL status
01482   */
01483 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
01484 {
01485   /* Check the parameters */
01486   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01487   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01488
01489   __HAL_LOCK(htim);
01490
01491   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01492       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01493   {
01494     /* Select the Input trigger */
01495     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01496     htim->Instance->SMCR |= InputTrigger;
01497   }
01498
01499   /* Select the Capture Compare preload feature */
01500   htim->Instance->CR2 |= TIM_CR2_CCPC;
01501   /* Select the Commutation event source */
01502   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01503   htim->Instance->CR2 |= CommutationSource;
01504
01505   /* Enable the Commutation DMA Request */
01506   /* Set the DMA Commutation Callback */
01507   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
01508   /* Set the DMA error callback */
01509   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;
01510
01511   /* Enable the Commutation DMA Request */
01512   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
01513
01514   __HAL_UNLOCK(htim);
01515
01516   return HAL_OK;
01517 }
01518
01519 /**
01520   * @brief  Configures the TIM in master mode.
01521   * @param  htim: TIM handle.
01522   * @param  sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
01523   *         contains the selected trigger output (TRGO) and the Master/Slave
01524   *         mode.
01525   * @retval HAL status
01526   */
01527 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
01528                                                       TIM_MasterConfigTypeDef * sMasterConfig)
01529 {
01530   uint32_t tmpcr2;
01531   uint32_t tmpsmcr;
01532
01533   /* Check the parameters */
01534   assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
01535   assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
01536   assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
01537
01538   /* Check input state */
01539   __HAL_LOCK(htim);
01540
01541  /* Get the TIMx CR2 register value */
01542   tmpcr2 = htim->Instance->CR2;
01543
01544   /* Get the TIMx SMCR register value */
01545   tmpsmcr = htim->Instance->SMCR;
01546
01547   /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
01548   if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
01549   {
01550     /* Check the parameters */
01551     assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
01552
01553     /* Clear the MMS2 bits */
01554     tmpcr2 &= ~TIM_CR2_MMS2;
01555     /* Select the TRGO2 source*/
01556     tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
01557   }
01558
01559   /* Reset the MMS Bits */
01560   tmpcr2 &= ~TIM_CR2_MMS;
01561   /* Select the TRGO source */
01562   tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
01563
01564   /* Reset the MSM Bit */
01565   tmpsmcr &= ~TIM_SMCR_MSM;
01566   /* Set master mode */
01567   tmpsmcr |= sMasterConfig->MasterSlaveMode;
01568
01569   /* Update TIMx CR2 */
01570   htim->Instance->CR2 = tmpcr2;
01571
01572   /* Update TIMx SMCR */
01573   htim->Instance->SMCR = tmpsmcr;
01574
01575   __HAL_UNLOCK(htim);
01576
01577   return HAL_OK;
01578 }
01579
01580 /**
01581   * @brief   Configures the Break feature, dead time, Lock level, OSSI/OSSR State
01582   *          and the AOE(automatic output enable).
01583   * @param   htim: TIM handle
01584   * @param   sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
01585   *          contains the BDTR Register configuration  information for the TIM peripheral.
01586   * @retval  HAL status
01587   */
01588 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
01589                                                 TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
01590 {
01591   uint32_t tmpbdtr = 0;
01592
01593   /* Check the parameters */
01594   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
01595   assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
01596   assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
01597   assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
01598   assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
01599   assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
01600   assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
01601   assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
01602   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
01603
01604   /* Check input state */
01605   __HAL_LOCK(htim);
01606
01607   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
01608   the OSSI State, the dead time value and the Automatic Output Enable Bit */
01609
01610   /* Set the BDTR bits */
01611   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
01612   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
01613   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
01614   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
01615   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
01616   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
01617   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
01618   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT));
01619
01620   if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
01621   {
01622     assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
01623     assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
01624     assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
01625
01626     /* Set the BREAK2 input related BDTR bits */
01627     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT));
01628     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
01629     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
01630   }
01631
01632   /* Set TIMx_BDTR */
01633   htim->Instance->BDTR = tmpbdtr;
01634
01635   __HAL_UNLOCK(htim);
01636
01637   return HAL_OK;
01638 }
01639
01640 /**
01641   * @brief  Configures the break input source.
01642   * @param  htim: TIM handle.
01643   * @param  BreakInput: Break input to configure.
01644   *          This parameter can be one of the following values:
01645   *            @arg TIM_BREAKINPUT_BRK: Timer break input
01646   *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
01647   * @param  sBreakInputConfig: Break input source configuration
01648   * @retval HAL status
01649   */
01650 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
01651                                              uint32_t BreakInput,
01652                                              TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
01653
01654 {
01655   uint32_t tmporx = 0;
01656   uint32_t bkin_enable_mask = 0;
01657   uint32_t bkin_polarity_mask = 0;
01658   uint32_t bkin_enable_bitpos = 0;
01659   uint32_t bkin_polarity_bitpos = 0;
01660
01661   /* Check the parameters */
01662   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
01663   assert_param(IS_TIM_BREAKINPUT(BreakInput));
01664   assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
01665   assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
01666   if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
01667   {
01668     assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
01669   }
01670
01671   /* Check input state */
01672   __HAL_LOCK(htim);
01673
01674   switch(sBreakInputConfig->Source)
01675   {
01676   case TIM_BREAKINPUTSOURCE_BKIN:
01677     {
01678       bkin_enable_mask = TIM1_AF1_BKINE;
01679       bkin_enable_bitpos = 0;
01680       bkin_polarity_mask = TIM1_AF1_BKINP;
01681       bkin_polarity_bitpos = 9;
01682     }
01683     break;
01684   case TIM_BREAKINPUTSOURCE_COMP1:
01685     {
01686       bkin_enable_mask = TIM1_AF1_BKCMP1E;
01687       bkin_enable_bitpos = 1;
01688       bkin_polarity_mask = TIM1_AF1_BKCMP1P;
01689       bkin_polarity_bitpos = 10;
01690     }
01691     break;
01692   case TIM_BREAKINPUTSOURCE_COMP2:
01693     {
01694       bkin_enable_mask = TIM1_AF1_BKCMP2E;
01695       bkin_enable_bitpos = 2;
01696       bkin_polarity_mask = TIM1_AF1_BKCMP2P;
01697       bkin_polarity_bitpos = 11;
01698     }
01699     break;
01700   case TIM_BREAKINPUTSOURCE_DFSDM1:
01701     {
01702       bkin_enable_mask = TIM1_AF1_BKDFBK0E;
01703       bkin_enable_bitpos = 8;
01704     }
01705     break;
01706
01707   default:
01708     break;
01709   }
01710
01711   switch(BreakInput)
01712   {
01713     case TIM_BREAKINPUT_BRK:
01714       {
01715         /* Get the TIMx_OR2 register value */
01716         tmporx = htim->Instance->AF1;
01717
01718         /* Enable the break input */
01719         tmporx &= ~bkin_enable_mask;
01720         tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
01721
01722         /* Set the break input polarity */
01723         if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
01724         {
01725           tmporx &= ~bkin_polarity_mask;
01726           tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
01727         }
01728
01729         /* Set TIMx_OR2 */
01730         htim->Instance->AF1 = tmporx;
01731       }
01732         break;
01733     case TIM_BREAKINPUT_BRK2:
01734       {
01735         /* Get the TIMx_OR3 register value */
01736         tmporx = htim->Instance->AF2;
01737
01738         /* Enable the break input */
01739         tmporx &= ~bkin_enable_mask;
01740         tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
01741
01742         /* Set the break input polarity */
01743         if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
01744         {
01745           tmporx &= ~bkin_polarity_mask;
01746           tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
01747         }
01748
01749         /* Set TIMx_OR3 */
01750         htim->Instance->AF2 = tmporx;
01751       }
01752       break;
01753   default:
01754     break;
01755   }
01756
01757   __HAL_UNLOCK(htim);
01758
01759   return HAL_OK;
01760 }
01761
01762 /**
01763   * @brief  Configures the TIMx Remapping input capabilities.
01764   * @param  htim: TIM handle.
01765   * @param  Remap: specifies the TIM remapping source.
01766   *         For TIM1, the parameter is one of the following values:
01767   *            @arg TIM_TIM1_ETR_GPIO:                TIM1_ETR is connected to GPIO
01768   *            @arg TIM_TIM1_ETR_COMP1:               TIM1_ETR is connected to COMP1 output
01769   *            @arg TIM_TIM1_ETR_COMP2:               TIM1_ETR is connected to COMP2 output
01770   *            @arg TIM_TIM1_ETR_ADC1_AWD1:           TIM1_ETR is connected to ADC1 AWD1
01771   *            @arg TIM_TIM1_ETR_ADC1_AWD2:           TIM1_ETR is connected to ADC1 AWD2
01772   *            @arg TIM_TIM1_ETR_ADC1_AWD3:           TIM1_ETR is connected to ADC1 AWD3
01773   *            @arg TIM_TIM1_ETR_ADC3_AWD1:           TIM1_ETR is connected to ADC3 AWD1
01774   *            @arg TIM_TIM1_ETR_ADC3_AWD2:           TIM1_ETR is connected to ADC3 AWD2
01775   *            @arg TIM_TIM1_ETR_ADC3_AWD3:           TIM1_ETR is connected to ADC3 AWD3:
01776   *
01777   *         For TIM2, the parameter is one of the following values:
01778   *            @arg TIM_TIM2_ETR_GPIO:                TIM2_ETR is connected to GPIO
01779   *            @arg TIM_TIM2_ETR_COMP1:               TIM2_ETR is connected to COMP1 output
01780   *            @arg TIM_TIM2_ETR_COMP2:               TIM2_ETR is connected to COMP2 output
01781   *            @arg TIM_TIM2_ETR_LSE:                 TIM2_ETR is connected to LSE
01782   *            @arg TIM_TIM2_ETR_SAI1_FSA:            TIM2_ETR is connected to SAI1 FS_A
01783   *            @arg TIM_TIM2_ETR_SAI1_FSB:            TIM2_ETR is connected to SAI1 FS_B
01784   *
01785   *         For TIM3, the parameter is one of the following values:
01786   *            @arg TIM_TIM3_ETR_GPIO:                TIM3_ETR is connected to GPIO
01787   *            @arg TIM_TIM3_ETR_COMP1:               TIM3_ETR is connected to COMP1 output
01788   *
01789   *         For TIM5, the parameter is one of the following values:
01790   *            @arg TIM_TIM5_ETR_GPIO:                TIM5_ETR is connected to GPIO
01791   *            @arg TIM_TIM5_ETR_SAI2_FSA:            TIM5_ETR is connected to SAI2 FS_A
01792   *            @arg TIM_TIM5_ETR_SAI2_FSB:            TIM5_ETR is connected to SAI2 FS_B
01793   *
01794   *         For TIM8, the parameter is one of the following values:
01795   *            @arg TIM_TIM8_ETR_GPIO:               TIM8_ETR is connected to GPIO
01796   *            @arg TIM_TIM8_ETR_COMP1:              TIM8_ETR is connected to COMP1 output
01797   *            @arg TIM_TIM8_ETR_COMP2:              TIM8_ETR is connected to COMP2 output
01798   *            @arg TIM_TIM8_ETR_ADC2_AWD1:          TIM8_ETR is connected to ADC2 AWD1
01799   *            @arg TIM_TIM8_ETR_ADC2_AWD2:          TIM8_ETR is connected to ADC2 AWD2
01800   *            @arg TIM_TIM8_ETR_ADC2_AWD3:          TIM8_ETR is connected to ADC2 AWD3
01801   *            @arg TIM_TIM8_ETR_ADC3_AWD1:          TIM8_ETR is connected to ADC3 AWD1
01802   *            @arg TIM_TIM8_ETR_ADC3_AWD2:          TIM8_ETR is connected to ADC3 AWD2
01803   *            @arg TIM_TIM8_ETR_ADC3_AWD3:          TIM8_ETR is connected to ADC3 AWD3
01804   *
01805   *
01806   * @retval HAL status
01807   */
01808 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
01809 {
01810   uint32_t tmpor2 = 0;
01811
01812   __HAL_LOCK(htim);
01813
01814   /* Check parameters */
01815   assert_param(IS_TIM_ETRSEL_INSTANCE(htim->Instance));
01816   assert_param(IS_TIM_ETRREMAP(Remap));
01817
01818   tmpor2 = htim->Instance->AF1;
01819   tmpor2 &= ~TIMx_ETRSEL_MASK;
01820   tmpor2 |= (Remap & TIMx_ETRSEL_MASK);
01821
01822   /* Set TIMx_OR2 */
01823   htim->Instance->AF1 = tmpor2;
01824
01825   htim->State = HAL_TIM_STATE_READY;
01826
01827   __HAL_UNLOCK(htim);
01828
01829   return HAL_OK;
01830 }
01831
01832 /**
01833   * @brief  Configures the TIMx input Selection capabilities.
01834   * @param  htim: TIM handle.
01835   * @param  TISelection : parameter of the TIM_TISelectionStruct structure.
01836   * @param  Channel: specifies the channels that will be selected for configuration:
01837   *              @arg TIM_CHANNEL_1: TIM Channel 1
01838   *              @arg TIM_CHANNEL_2: TIM Channel 2
01839   *              @arg TIM_CHANNEL_3: TIM Channel 3
01840   *              @arg TIM_CHANNEL_4: TIM Channel 4
01841   *
01842   *         TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows:
01843   *         For TIM1, the parameter is one of the following values:
01844   *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO
01845   *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output
01846   *
01847   *         For TIM2, the parameter is one of the following values:
01848   *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO
01849   *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output
01850   *            @arg TIM_TIM2_TI4_COMP2:               TIM2 TI4 is connected to COMP2 output
01851   *            @arg TIM_TIM2_TI4_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
01852   *
01853   *         For TIM3, the parameter is one of the following values:
01854   *            @arg TIM_TIM3_TI1_GPIO:                TIM3 TI1 is connected to GPIO
01855   *            @arg TIM_TIM3_TI1_COMP1:               TIM3 TI1 is connected to COMP1 output
01856   *            @arg TIM_TIM3_TI1_COMP2:               TIM3 TI1 is connected to COMP2 output
01857   *            @arg TIM_TIM3_TI1_COMP1_COMP2:         TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
01858   *
01859   *         For TIM5, the parameter is one of the following values:
01860   *            @arg TIM_TIM5_TI1_GPIO:                TIM5 TI1 is connected to GPIO
01861   *            @arg TIM_TIM5_TI1_CAN_TMP:             TIM5 TI1 is connected to CAN TMP
01862   *            @arg TIM_TIM5_TI1_CAN_RTP:             TIM5 TI1 is connected to CAN RTP
01863   *
01864   *         For TIM8, the parameter is one of the following values:
01865   *            @arg TIM_TIM8_TI1_GPIO:               TIM8 TI1 is connected to GPIO
01866   *            @arg TIM_TIM8_TI1_COMP2:              TIM8 TI1 is connected to COMP2 output
01867   *
01868   *         For TIM15, the parameter is one of the following values:
01869   *            @arg TIM_TIM15_TI1_GPIO:              TIM15 TI1 is connected to GPIO
01870   *            @arg TIM_TIM15_TI1_TIM2:              TIM15 TI1 is connected to TIM2 CH1
01871   *            @arg TIM_TIM15_TI1_TIM3:              TIM15 TI1 is connected to TIM3 CH1
01872   *            @arg TIM_TIM15_TI1_TIM4:              TIM15 TI1 is connected to TIM4 CH1
01873   *            @arg TIM_TIM15_TI1_LSE:               TIM15 TI1 is connected to LSE
01874   *            @arg TIM_TIM15_TI1_CSI:               TIM15 TI1 is connected to CSI
01875   *            @arg TIM_TIM15_TI1_MCO2:              TIM15 TI1 is connected to MCO2
01876   *            @arg TIM_TIM15_TI2_GPIO:              TIM15 TI2 is connected to GPIO
01877   *            @arg TIM_TIM15_TI2_TIM2:              TIM15 TI2 is connected to TIM2 CH2
01878   *            @arg TIM_TIM15_TI2_TIM3:              TIM15 TI2 is connected to TIM3 CH2
01879   *            @arg TIM_TIM15_TI2_TIM4:              TIM15 TI2 is connected to TIM4 CH2
01880   *
01881   *         For TIM16, the parameter can have the following values:
01882   *            @arg TIM_TIM16_TI1_GPIO:              TIM16 TI1 is connected to GPIO
01883   *            @arg TIM_TIM16_TI1_LSI:               TIM16 TI1 is connected to LSI
01884   *            @arg TIM_TIM16_TI1_LSE:               TIM16 TI1 is connected to LSE
01885   *            @arg TIM_TIM16_TI1_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt
01886   *
01887   *         For TIM17, the parameter can have the following values:
01888   *            @arg TIM_TIM17_TI1_GPIO:              TIM17 TI1 is connected to GPIO
01889   *            @arg TIM_TIM17_TI1_SPDIFFS:           TIM17 TI1 is connected to SPDIF FS
01890   *            @arg TIM_TIM17_TI1_HSE_1MHZ:          TIM17 TI1 is connected to HSE 1MHz
01891   *            @arg TIM_TIM17_TI1_MCO1:              TIM17 TI1 is connected to MCO1
01892   *
01893   * @retval HAL status
01894   */
01895 HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection , uint32_t Channel)
01896 {
01897   uint32_t tmptisel = 0;
01898
01899   __HAL_LOCK(htim);
01900
01901   /* Check parameters */
01902   assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance));
01903   assert_param(IS_TIM_TISEL(TISelection));
01904
01905   tmptisel = htim->Instance->TISEL;
01906
01907   tmptisel &= ~(TIMx_TIxSEL_MASK << (Channel << 2));
01908   tmptisel |= (TISelection);
01909
01910   /* Set TIMx_TISEL */
01911   htim->Instance->TISEL = tmptisel;
01912
01913   htim->State = HAL_TIM_STATE_READY;
01914
01915   __HAL_UNLOCK(htim);
01916
01917   return HAL_OK;
01918 }
01919 /**
01920   * @brief  Group channel 5 and channel 1, 2 or 3
01921   * @param  htim: TIM handle.
01922   * @param  Channels: specifies the reference signal(s) the OC5REF is combined with.
01923   *         This parameter can be any combination of the following values:
01924   *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
01925   *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
01926   *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
01927   *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
01928   * @retval HAL status
01929   */
01930 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
01931 {
01932   /* Check parameters */
01933   assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
01934   assert_param(IS_TIM_GROUPCH5(Channels));
01935
01936   /* Process Locked */
01937   __HAL_LOCK(htim);
01938
01939   htim->State = HAL_TIM_STATE_BUSY;
01940
01941   /* Clear GC5Cx bit fields */
01942   htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
01943
01944   /* Set GC5Cx bit fields */
01945   htim->Instance->CCR5 |= Channels;
01946
01947   htim->State = HAL_TIM_STATE_READY;
01948
01949   __HAL_UNLOCK(htim);
01950
01951   return HAL_OK;
01952 }
01953
01954
01955 /**
01956   * @}
01957   */
01958
01959 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
01960   * @brief    Extended Callbacks functions
01961   *
01962 @verbatim
01963   ==============================================================================
01964                     ##### Extended Callbacks functions #####
01965   ==============================================================================
01966   [..]
01967     This section provides Extended TIM callback functions:
01968     (+) TIM Commutation callback
01969     (+) TIM Break callback
01970
01971 @endverbatim
01972   * @{
01973   */
01974
01975 /**
01976   * @brief  Hall commutation changed callback in non blocking mode
01977   * @param  htim : TIM handle
01978   * @retval None
01979   */
01980 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
01981 {
01982   /* Prevent unused argument(s) compilation warning */
01983   UNUSED(htim);
01984
01985   /* NOTE : This function Should not be modified, when the callback is needed,
01986             the HAL_TIMEx_CommutationCallback could be implemented in the user file
01987    */
01988 }
01989
01990 /**
01991   * @brief  Hall Break detection callback in non blocking mode
01992   * @param  htim : TIM handle
01993   * @retval None
01994   */
01995 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
01996 {
01997   /* Prevent unused argument(s) compilation warning */
01998   UNUSED(htim);
01999
02000   /* NOTE : This function Should not be modified, when the callback is needed,
02001             the HAL_TIMEx_BreakCallback could be implemented in the user file
02002    */
02003 }
02004
02005 /**
02006   * @}
02007   */
02008
02009 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
02010   * @brief    Extended Peripheral State functions
02011   *
02012 @verbatim
02013   ==============================================================================
02014                 ##### Extended Peripheral State functions #####
02015   ==============================================================================
02016   [..]
02017     This subsection permit to get in run-time the status of the peripheral
02018     and the data flow.
02019
02020 @endverbatim
02021   * @{
02022   */
02023
02024 /**
02025   * @brief  Return the TIM Hall Sensor interface state
02026   * @param  htim: TIM Hall Sensor handle
02027   * @retval HAL state
02028   */
02029 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
02030 {
02031   return htim->State;
02032 }
02033
02034 /**
02035   * @}
02036   */
02037
02038 /**
02039   * @brief  TIM DMA Commutation callback.
02040   * @param  hdma : pointer to DMA handle.
02041   * @retval None
02042   */
02043 void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
02044 {
02045   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02046
02047   htim->State= HAL_TIM_STATE_READY;
02048
02049   HAL_TIMEx_CommutationCallback(htim);
02050 }
02051
02052 /**
02053   * @brief  Enables or disables the TIM Capture Compare Channel xN.
02054   * @param  TIMx to select the TIM peripheral
02055   * @param  Channel: specifies the TIM Channel
02056   *          This parameter can be one of the following values:
02057   *            @arg TIM_Channel_1: TIM Channel 1
02058   *            @arg TIM_Channel_2: TIM Channel 2
02059   *            @arg TIM_Channel_3: TIM Channel 3
02060   * @param  ChannelNState: specifies the TIM Channel CCxNE bit new state.
02061   *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
02062   * @retval None
02063   */
02064 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
02065 {
02066   uint32_t tmp = 0;
02067
02068   tmp = TIM_CCER_CC1NE << Channel;
02069
02070   /* Reset the CCxNE Bit */
02071   TIMx->CCER &=  ~tmp;
02072
02073   /* Set or reset the CCxNE Bit */
02074   TIMx->CCER |=  (uint32_t)(ChannelNState << Channel);
02075 }
02076
02077 /**
02078   * @}
02079   */
02080
02081 #endif /* HAL_TIM_MODULE_ENABLED */
02082 /**
02083   * @}
02084   */
02085
02086 /**
02087   * @}
02088   */
02089
02090 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_tim_ex.h Source File

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stm32h7xx_hal_tim_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_tim_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of TIM HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_TIM_EX_H
00040 #define __STM32H7xx_HAL_TIM_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup TIMEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  TIM Hall sensor Configuration Structure definition
00064   */
00065
00066 typedef struct
00067 {
00068
00069   uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
00070                                         This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00071
00072   uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
00073                                      This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00074
00075   uint32_t IC1Filter;           /*!< Specifies the input capture filter.
00076                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00077   uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00078                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00079 } TIM_HallSensor_InitTypeDef;
00080
00081 /**
00082   * @brief  TIM Break/Break2 input configuration
00083   */
00084 typedef struct {
00085   uint32_t Source;         /*!< Specifies the source of the timer break input.
00086                                 This parameter can be a value of @ref TIMEx_Break_Input_Source */
00087   uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.
00088                                 This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
00089   uint32_t Polarity;       /*!< Specifies the break input source polarity.
00090                                 This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
00091                                 Not relevant when analog watchdog output of the DFSDM1 used as break input source */
00092 } TIMEx_BreakInputConfigTypeDef;
00093
00094 /**
00095   * @}
00096   */
00097
00098 /* Exported constants --------------------------------------------------------*/
00099 /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
00100   * @{
00101   */
00102
00103 /** @defgroup TIMEx_Channel TIM Extended Channel
00104   * @{
00105   */
00106 #define TIM_CHANNEL_1                      ((uint32_t)0x0000U)   /*!< TIM Channel 1*/
00107 #define TIM_CHANNEL_2                      ((uint32_t)0x0004U)   /*!< TIM Channel 2*/
00108 #define TIM_CHANNEL_3                      ((uint32_t)0x0008U)   /*!< TIM Channel 3*/
00109 #define TIM_CHANNEL_4                      ((uint32_t)0x000CU)   /*!< TIM Channel 4*/
00110 #define TIM_CHANNEL_5                      ((uint32_t)0x0010U)   /*!< TIM Channel 5*/
00111 #define TIM_CHANNEL_6                      ((uint32_t)0x0014U)   /*!< TIM Channel 6*/
00112 #define TIM_CHANNEL_ALL                    ((uint32_t)0x003CU)   /*!< TIM all Channels */
00113
00114 /**
00115   * @}
00116   */
00117
00118 /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
00119   * @{
00120   */
00121 #define TIM_OCMODE_TIMING                   ((uint32_t)0x0000U)                                                  /*!< TIM Output timing mode */
00122 #define TIM_OCMODE_ACTIVE                   ((uint32_t)TIM_CCMR1_OC1M_0)                                         /*!< TIM Output Active mode */
00123 #define TIM_OCMODE_INACTIVE                 ((uint32_t)TIM_CCMR1_OC1M_1)                                         /*!< TIM Output Inactive mode */
00124 #define TIM_OCMODE_TOGGLE                   ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                      /*!< TIM Output Toggle mode */
00125 #define TIM_OCMODE_PWM1                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                      /*!< TIM PWM mode 1 */
00126 #define TIM_OCMODE_PWM2                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)   /*!< TIM PWM mode 2 */
00127 #define TIM_OCMODE_FORCED_ACTIVE            ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                      /*!< TIM Forced Active mode */
00128 #define TIM_OCMODE_FORCED_INACTIVE          ((uint32_t)TIM_CCMR1_OC1M_2)                                         /*!< TIM Forced Inactive mode */
00129
00130 #define TIM_OCMODE_RETRIGERRABLE_OPM1      ((uint32_t)TIM_CCMR1_OC1M_3)                                           /*!< TIM Rettrigerrable OPM mode 1 */
00131 #define TIM_OCMODE_RETRIGERRABLE_OPM2      ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                        /*!< TIM Rettrigerrable OPM mode 2 */
00132 #define TIM_OCMODE_COMBINED_PWM1           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                        /*!< TIM Combined PWM mode 1 */
00133 #define TIM_OCMODE_COMBINED_PWM2           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)     /*!< TIM Combined PWM mode 2 */
00134 #define TIM_OCMODE_ASSYMETRIC_PWM1         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)     /*!< TIM Asymetruc PWM mode 1 */
00135 #define TIM_OCMODE_ASSYMETRIC_PWM2         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                          /*!< TIM Asymetruc PWM mode 2 */
00136 /**
00137   * @}
00138   */
00139
00140 /** @defgroup TIMEx_ClearInput_Source TIM  Extended Clear Input Source
00141   * @{
00142   */
00143 #define TIM_CLEARINPUTSOURCE_ETR            ((uint32_t)0x0001U)            /*!< TIM Clear input source connected to ETR */
00144 #define TIM_CLEARINPUTSOURCE_OCREFCLR       ((uint32_t)0x0002U)            /*!< TIM Clear input source connected to OCREFClear */
00145 #define TIM_CLEARINPUTSOURCE_NONE           ((uint32_t)0x0000U)            /*!< TIM Clear input source None */
00146
00147 /**
00148   * @}
00149   */
00150
00151 /** @defgroup TIMEx_Break2_Input_enable_disable  TIMEX Break input 2 Enable
00152   * @{
00153   */
00154 #define TIM_BREAK2_DISABLE         ((uint32_t)0x00000000U)            /*!< TIM Break2 disabled */
00155 #define TIM_BREAK2_ENABLE          ((uint32_t)TIM_BDTR_BK2E)          /*!< TIM Break2 enabled */
00156
00157 /**
00158   * @}
00159   */
00160 /** @defgroup TIMEx_Break2_Polarity TIM  Extended Break Input 2 Polarity
00161   * @{
00162   */
00163 #define TIM_BREAK2POLARITY_LOW        ((uint32_t)0x00000000U)          /*!< TIM Break2 polarity low */
00164 #define TIM_BREAK2POLARITY_HIGH       ((uint32_t)TIM_BDTR_BK2P)        /*!< TIM Break2 polarity high */
00165
00166 /**
00167   * @}
00168   */
00169
00170 /** @defgroup TIMEx_Trigger_Selection TIM Trigger Selection
00171   * @{
00172   */
00173 #define TIM_TS_ITR4                        ((uint32_t)0x0100000)       /*!< TIM Internal trigger 4 */
00174 #define TIM_TS_ITR5                        ((uint32_t)0x0100010)       /*!< TIM Internal trigger 5 */
00175 #define TIM_TS_ITR6                        ((uint32_t)0x0100020)       /*!< TIM Internal trigger 6 */
00176 #define TIM_TS_ITR7                        ((uint32_t)0x0100030)       /*!< TIM Internal trigger 7 */
00177 #define TIM_TS_ITR8                        ((uint32_t)0x0100040)       /*!< TIM Internal trigger 8 */
00178
00179
00180 /**
00181   * @}
00182   */
00183
00184 /** @defgroup TIM_Event_Source TIM  Extended Event Source
00185   * @{
00186   */
00187
00188 #define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
00189 #define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
00190 #define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
00191 #define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
00192 #define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
00193 #define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
00194 #define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
00195 #define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
00196 #define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */
00197
00198 /**
00199   * @}
00200   */
00201
00202 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
00203   * @{
00204   */
00205 #define TIM_DMABASE_CR1                    (0x00000000U)              /*!< TIM DMA Base Address is CR1 */
00206 #define TIM_DMABASE_CR2                    (0x00000001U)              /*!< TIM DMA Base Address is CR2 */
00207 #define TIM_DMABASE_SMCR                   (0x00000002U)              /*!< TIM DMA Base Address is SMCR */
00208 #define TIM_DMABASE_DIER                   (0x00000003U)              /*!< TIM DMA Base Address is DIER */
00209 #define TIM_DMABASE_SR                     (0x00000004U)              /*!< TIM DMA Base Address is SR */
00210 #define TIM_DMABASE_EGR                    (0x00000005U)              /*!< TIM DMA Base Address is EGR */
00211 #define TIM_DMABASE_CCMR1                  (0x00000006U)              /*!< TIM DMA Base Address is CCMR1 */
00212 #define TIM_DMABASE_CCMR2                  (0x00000007U)              /*!< TIM DMA Base Address is CCMR2*/
00213 #define TIM_DMABASE_CCER                   (0x00000008U)              /*!< TIM DMA Base Address is CCER */
00214 #define TIM_DMABASE_CNT                    (0x00000009U)              /*!< TIM DMA Base Address is CNT */
00215 #define TIM_DMABASE_PSC                    (0x0000000AU)              /*!< TIM DMA Base Address is PSC */
00216 #define TIM_DMABASE_ARR                    (0x0000000BU)              /*!< TIM DMA Base Address is ARR */
00217 #define TIM_DMABASE_RCR                    (0x0000000CU)              /*!< TIM DMA Base Address is RCR */
00218 #define TIM_DMABASE_CCR1                   (0x0000000DU)              /*!< TIM DMA Base Address is CCR1 */
00219 #define TIM_DMABASE_CCR2                   (0x0000000EU)              /*!< TIM DMA Base Address is CCR2 */
00220 #define TIM_DMABASE_CCR3                   (0x0000000FU)              /*!< TIM DMA Base Address is CCR3 */
00221 #define TIM_DMABASE_CCR4                   (0x00000010U)              /*!< TIM DMA Base Address is CCR3 */
00222 #define TIM_DMABASE_BDTR                   (0x00000011U)              /*!< TIM DMA Base Address is BDTR */
00223 #define TIM_DMABASE_DCR                    (0x00000012U)              /*!< TIM DMA Base Address is DCR */
00224 #define TIM_DMABASE_DMAR                   (0x00000013U)              /*!< TIM DMA Base Address is DMAR */
00225 #define TIM_DMABASE_AF1                    (0x00000014U)              /*!< TIM DMA Base Address is AF1 */
00226 #define TIM_DMABASE_CCMR3                  (0x00000015U)              /*!< TIM DMA Base Address is CCMR3 */
00227 #define TIM_DMABASE_CCR5                   (0x00000016U)              /*!< TIM DMA Base Address is CCR5 */
00228 #define TIM_DMABASE_CCR6                   (0x00000017U)              /*!< TIM DMA Base Address is CCR6 */
00229 #define TIM_DMABASE_AF2                    (0x00000018U)              /*!< TIM DMA Base Address is AF2 */
00230 #define TIM_DMABASE_AF3                    (0x00000019U)              /*!< TIM DMA Base Address is AF3 */
00231 #define TIM_DMABASE_TISEL                  (0x0000001AU)              /*!< TIM DMA Base Address is TISEL */
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup TIMEx_Remap TIM  Extended Remapping
00237   * @{
00238   */
00239 #define TIM_TIM1_ETR_GPIO                          (0x00000000) /* !< TIM1_ETR is connected to GPIO */
00240 #define TIM_TIM1_ETR_ADC1_AWD1                     (0x0000C000) /* !< TIM1_ETR is connected to ADC1 AWD1 */
00241 #define TIM_TIM1_ETR_ADC1_AWD2                     (0x00010000) /* !< TIM1_ETR is connected to ADC1 AWD2 */
00242 #define TIM_TIM1_ETR_ADC1_AWD3                     (0x00014000) /* !< TIM1_ETR is connected to ADC1 AWD3 */
00243 #define TIM_TIM1_ETR_ADC3_AWD1                     (0x00018000) /* !< TIM1_ETR is connected to ADC3 AWD1 */
00244 #define TIM_TIM1_ETR_ADC3_AWD2                     (0x0001C000) /* !< TIM1_ETR is connected to ADC3 AWD2 */
00245 #define TIM_TIM1_ETR_ADC3_AWD3                     (0x00020000) /* !< TIM1_ETR is connected to ADC3 AWD3 */
00246 #define TIM_TIM1_ETR_COMP1_OUT                     (0x00004000) /* !< TIM1_ETR is connected to COMP1 OUT */
00247 #define TIM_TIM1_ETR_COMP2_OUT                     (0x00008000) /* !< TIM1_ETR is connected to COMP2 OUT */
00248
00249 #define TIM_TIM8_ETR_GPIO                          (0x00000000) /* !< TIM8_ETR is connected to GPIO */
00250 #define TIM_TIM8_ETR_ADC2_AWD1                     (0x0000C000) /* !< TIM8_ETR is connected to ADC2 AWD1 */
00251 #define TIM_TIM8_ETR_ADC2_AWD2                     (0x00010000) /* !< TIM8_ETR is connected to ADC2 AWD2 */
00252 #define TIM_TIM8_ETR_ADC2_AWD3                     (0x00014000) /* !< TIM8_ETR is connected to ADC2 AWD3 */
00253 #define TIM_TIM8_ETR_ADC3_AWD1                     (0x00018000) /* !< TIM8_ETR is connected to ADC3 AWD1 */
00254 #define TIM_TIM8_ETR_ADC3_AWD2                     (0x0001C000) /* !< TIM8_ETR is connected to ADC3 AWD2 */
00255 #define TIM_TIM8_ETR_ADC3_AWD3                     (0x00020000) /* !< TIM8_ETR is connected to ADC3 AWD3 */
00256 #define TIM_TIM8_ETR_COMP1_OUT                     (0x00004000) /* !< TIM8_ETR is connected to COMP1 OUT */
00257 #define TIM_TIM8_ETR_COMP2_OUT                     (0x00008000) /* !< TIM8_ETR is connected to COMP2 OUT */
00258
00259 #define TIM_TIM2_ETR_GPIO                          (0x00000000) /* !< TIM2_ETR is connected to GPIO */
00260 #define TIM_TIM2_ETR_COMP1_OUT                     (0x0000C000) /* !< TIM2_ETR is connected to COMP1 OUT */
00261 #define TIM_TIM2_ETR_COMP2_OUT                     (0x00010000) /* !< TIM2_ETR is connected to COMP2 OUT */
00262 #define TIM_TIM2_ETR_RCC_LSE                       (0x00014000) /* !< TIM2_ETR is connected to RCC LSE */
00263 #define TIM_TIM2_ETR_SAI1_FSA                      (0x00018000) /* !< TIM2_ETR is connected to SAI1 FS_A */
00264 #define TIM_TIM2_ETR_SAI1_FSB                      (0x0001C000) /* !< TIM2_ETR is connected to SAI1 FS_B */
00265
00266 #define TIM_TIM3_ETR_GPIO                          (0x00000000) /* !< TIM3_ETR is connected to GPIO */
00267 #define TIM_TIM3_ETR_COMP1_OUT                     (0x00000000) /* !< TIM3_ETR is connected to COMP1 OUT */
00268
00269 #define TIM_TIM5_ETR_GPIO                          (0x00000000) /* !< TIM5_ETR is connected to GPIO */
00270 #define TIM_TIM5_ETR_SAI2_FSA                      (0x00000000) /* !< TIM5_ETR is connected to SAI2 FS_A */
00271 #define TIM_TIM5_ETR_SAI2_FSB                      (0x00000000) /* !< TIM5_ETR is connected to SAI2 FS_B */
00272
00273 #define TIM_TIM1_BKR_GPIO                          (0x00000000) /* !< TIM1_BKR is connected to GPIO */
00274 #define TIM_TIM1_BKR_COMP1_OUT                     (0x00000002) /* !< TIM1_BKR is connected to COMP1 OUT */
00275 #define TIM_TIM1_BKR_COMP2_OUT                     (0x00000004) /* !< TIM1_BKR is connected to COMP2 OUT */
00276 #define TIM_TIM1_BKR_DFSDM_BRK0                    (0x00000000) /* !< TIM1_BKR is connected to DFSDM BRK0 */
00277
00278 #define TIM_TIM8_BKR_GPIO                          (0x00000000) /* !< TIM8_BKR is connected to GPIO */
00279 #define TIM_TIM8_BKR_COMP1_OUT                     (0x00000002) /* !< TIM8_BKR is connected to COMP1 OUT */
00280 #define TIM_TIM8_BKR_COMP2_OUT                     (0x00000004) /* !< TIM8_BKR is connected to COMP2 OUT */
00281 #define TIM_TIM8_BKR_DFSDM_BRK2                    (0x00000000) /* !< TIM8_BKR is connected to DFSDM BRK2 */
00282
00283 #define TIM_TIM15_BKR_GPIO                         (0x00000000) /* !< TIM15_BKR is connected to GPIO */
00284 #define TIM_TIM15_BKR_COMP1_OUT                    (0x00000002) /* !< TIM15_BKR is connected to COMP1 OUT */
00285 #define TIM_TIM15_BKR_COMP2_OUT                    (0x00000004) /* !< TIM15_BKR is connected to COMP2 OUT */
00286 #define TIM_TIM15_BKR_DFSDM_BRK0                   (0x00000000) /* !< TIM15_BKR is connected to DFSDM BRK0 */
00287
00288 #define TIM_TIM16_BKR_GPIO                         (0x00000000) /* !< TIM16_BKR is connected to GPIO */
00289 #define TIM_TIM16_BKR_COMP1_OUT                    (0x00000002) /* !< TIM16_BKR is connected to COMP1 OUT */
00290 #define TIM_TIM16_BKR_COMP2_OUT                    (0x00000004) /* !< TIM16_BKR is connected to COMP2 OUT */
00291 #define TIM_TIM16_BKR_DFSDM_BRK1                   (0x00000000) /* !< TIM16_BKR is connected to DFSDM BRK1 */
00292
00293 #define TIM_TIM17_BKR_GPIO                         (0x00000000) /* !< TIM17_BKR is connected to GPIO */
00294 #define TIM_TIM17_BKR_COMP1_OUT                    (0x00000002) /* !< TIM17_BKR is connected to COMP1 OUT */
00295 #define TIM_TIM17_BKR_COMP2_OUT                    (0x00000004) /* !< TIM17_BKR is connected to COMP2 OUT */
00296 #define TIM_TIM17_BKR_DFSDM_BRK2                   (0x00000000) /* !< TIM17_BKR is connected to DFSDM BRK2 */
00297
00298 #define TIM_TIM1_BKR2_GPIO                         (0x00000000) /* !< TIM1_BKR2 is connected to GPIO */
00299 #define TIM_TIM1_BKR2_COMP1_OUT                    (0x00000002) /* !< TIM1_BKR2 is connected to COMP1 OUT */
00300 #define TIM_TIM1_BKR2_COMP2_OUT                    (0x00000004) /* !< TIM1_BKR2 is connected to COMP2 OUT */
00301 #define TIM_TIM1_BKR2_DFSDM_BRK1                   (0x00000000) /* !< TIM1_BKR2 is connected to DFSDM BRK0 */
00302
00303 #define TIM_TIM8_BKR2_GPIO                         (0x00000000) /* !< TIM8_BKR2 is connected to GPIO */
00304 #define TIM_TIM8_BKR2_COMP1_OUT                    (0x00000002) /* !< TIM8_BKR2 is connected to COMP1 OUT */
00305 #define TIM_TIM8_BKR2_COMP2_OUT                    (0x00000004) /* !< TIM8_BKR2 is connected to COMP2 OUT */
00306 #define TIM_TIM8_BKR2_DFSDM_BRK3                   (0x00000000) /* !< TIM8_BKR2 is connected to DFSDM BRK3 */
00307
00308 #define TIM_TIM1_TI1_GPIO                          (0x00000000) /* !< TIM1_TI1 is connected to GPIO */
00309 #define TIM_TIM1_TI1_COMP1_OUT                     (0x00000001) /* !< TIM1_TI1 is connected to COMP1 OUT */
00310
00311 #define TIM_TIM8_TI1_GPIO                          (0x00000000) /* !< TIM8_TI1 is connected to GPIO */
00312 #define TIM_TIM8_TI1_COMP2_OUT                     (0x00000001) /* !< TIM8_TI1 is connected to COMP2 OUT */
00313
00314 #define TIM_TIM2_TI4_GPIO                          (0x00000000) /* !< TIM2_TI4 is connected to GPIO */
00315 #define TIM_TIM2_TI4_COMP1_OUT                     (0x01000000) /* !< TIM2_TI4 is connected to COMP1 OUT */
00316 #define TIM_TIM2_TI4_COMP2_OUT                     (0x02000000) /* !< TIM2_TI4 is connected to COMP2 OUT */
00317 #define TIM_TIM2_TI4_COMP1COMP2_OUT                (0x03000000) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */
00318
00319 #define TIM_TIM3_TI1_GPIO                          (0x00000000) /* !< TIM3_TI1 is connected to GPIO */
00320 #define TIM_TIM3_TI1_COMP1_OUT                     (0x00000001) /* !< TIM3_TI1 is connected to COMP1 OUT */
00321 #define TIM_TIM3_TI1_COMP2_OUT                     (0x00000002) /* !< TIM3_TI1 is connected to COMP2 OUT */
00322 #define TIM_TIM3_TI1_COMP1COMP2_OUT                (0x00000003) /* !< TIM3_TI1 is connected to COMP2 OUT OR COMP2 OUT */
00323
00324 #define TIM_TIM5_TI1_GPIO                          (0x00000000) /* !< TIM5_TI1 is connected to GPIO */
00325 #define TIM_TIM5_TI1_CAN_TMP                       (0x00000001) /* !< TIM5_TI1 is connected to CAN TMP */
00326 #define TIM_TIM5_TI1_CAN_RTP                       (0x00000002) /* !< TIM5_TI1 is connected to CAN RTP */
00327
00328 #define TIM_TIM15_TI1_GPIO                         (0x00000000) /* !< TIM15_TI1 is connected to GPIO */
00329 #define TIM_TIM15_TI1_TIM2_CH1                     (0x00000001) /* !< TIM15_TI1 is connected to TIM2 CH1 */
00330 #define TIM_TIM15_TI1_TIM3_CH1                     (0x00000002) /* !< TIM15_TI1 is connected to TIM3 CH1 */
00331 #define TIM_TIM15_TI1_TIM4_CH1                     (0x00000003) /* !< TIM15_TI1 is connected to TIM4 CH1 */
00332 #define TIM_TIM15_TI1_RCC_LSE                      (0x00000004) /* !< TIM15_TI1 is connected to RCC LSE */
00333 #define TIM_TIM15_TI1_RCC_CSI                      (0x00000005) /* !< TIM15_TI1 is connected to RCC CSI */
00334 #define TIM_TIM15_TI1_RCC_MCO2                     (0x00000006) /* !< TIM15_TI1 is connected to RCC MCO2 */
00335
00336 #define TIM_TIM15_TI2_GPIO                         (0x00000000) /* !< TIM15_TI2 is connected to GPIO */
00337 #define TIM_TIM15_TI2_TIM2_CH2                     (0x00000100) /* !< TIM15_TI2 is connected to TIM2 CH2 */
00338 #define TIM_TIM15_TI2_TIM3_CH2                     (0x00000200) /* !< TIM15_TI2 is connected to TIM3 CH2 */
00339 #define TIM_TIM15_TI2_TIM4_CH2                     (0x00000300) /* !< TIM15_TI2 is connected to TIM4 CH2 */
00340
00341 #define TIM_TIM16_TI1_GPIO                         (0x00000000) /* !< TIM16 TI1 is connected to GPIO */
00342 #define TIM_TIM16_TI1_RCC_LSI                      (0x00000001) /* !< TIM16 TI1 is connected to RCC LSI */
00343 #define TIM_TIM16_TI1_RCC_LSE                      (0x00000002) /* !< TIM16 TI1 is connected to RCC LSE */
00344 #define TIM_TIM16_TI1_WKUP_IT                      (0x00000003) /* !< TIM16 TI1 is connected to WKUP_IT */
00345
00346 #define TIM_TIM17_TI1_GPIO                         (0x00000000) /* !< TIM17 TI1 is connected to GPIO */
00347 #define TIM_TIM17_TI1_SPDIF_FS                     (0x00000001) /* !< TIM17 TI1 is connected to RCC LSI */
00348 #define TIM_TIM17_TI1_RCC_HSE1MHZ                  (0x00000002) /* !< TIM17 TI1 is connected to RCC LSE */
00349 #define TIM_TIM17_TI1_RCC_MCO1                     (0x00000003) /* !< TIM17 TI1 is connected to RCC MCO1 */
00350
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
00356   * @{
00357   */
00358 #define TIM_GROUPCH5_NONE       (uint32_t)0x00000000  /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
00359 #define TIM_GROUPCH5_OC1REFC    (TIM_CCR5_GC5C1)      /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
00360 #define TIM_GROUPCH5_OC2REFC    (TIM_CCR5_GC5C2)      /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
00361 #define TIM_GROUPCH5_OC3REFC    (TIM_CCR5_GC5C3)       /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
00362
00363
00364 /** @defgroup TIMEx_Break_Input TIM  Extended Break input
00365   * @{
00366   */
00367 #define TIM_BREAKINPUT_BRK     ((uint32_t)(0x00000001)) /* !< Timer break input  */
00368 #define TIM_BREAKINPUT_BRK2    ((uint32_t)(0x00000002)) /* !< Timer break2 input */
00369 /**
00370   * @}
00371   */
00372
00373 /** @defgroup TIMEx_Break_Input_Source TIM  Extended Break input source
00374   * @{
00375   */
00376 #define TIM_BREAKINPUTSOURCE_BKIN     ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin  */
00377 #define TIM_BREAKINPUTSOURCE_COMP1    ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */
00378 #define TIM_BREAKINPUTSOURCE_COMP2    ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */
00379 #define TIM_BREAKINPUTSOURCE_DFSDM1   ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
00380 /**
00381   * @}
00382   */
00383
00384 /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
00385   * @{
00386   */
00387 #define TIM_BREAKINPUTSOURCE_DISABLE     ((uint32_t)(0x00000000)) /* !< Break input source is disabled */
00388 #define TIM_BREAKINPUTSOURCE_ENABLE      ((uint32_t)(0x00000001)) /* !< Break input source is enabled */
00389 /**
00390   * @}
00391   */
00392
00393 /** @defgroup TIMEx_Break_Input_Source_Polarity TIM  Extended Break input polarity
00394   * @{
00395   */
00396 #define TIM_BREAKINPUTSOURCE_POLARITY_LOW     ((uint32_t)(0x00000001)) /* !< Break input source is active low */
00397 #define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    ((uint32_t)(0x00000000)) /* !< Break input source is active_high */
00398 /**
00399   * @}
00400   */
00401
00402 /**
00403   * @}
00404   */
00405 /**
00406   * @}
00407   */
00408
00409 /* Exported macro ------------------------------------------------------------*/
00410 /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
00411   * @{
00412   */
00413
00414 /* Private macro -------------------------------------------------------------*/
00415 /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
00416   * @{
00417  */
00418 #define IS_TIM_REMAP(__REMAP__)    (((__REMAP__) <= (uint32_t)0x0001C01F))
00419
00420 #define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
00421                                             ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
00422
00423 #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
00424                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
00425                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
00426                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
00427
00428 #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
00429                                                    ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
00430
00431 #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
00432                                                          ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
00433
00434 #define IS_TIM_TISEL(TISEL)    (((TISEL) == TIM_TIM1_TI1_GPIO) ||\
00435                                 ((TISEL) == TIM_TIM1_TI1_COMP1_OUT) ||\
00436                                 ((TISEL) == TIM_TIM8_TI1_GPIO) ||\
00437                                 ((TISEL) == TIM_TIM8_TI1_COMP2_OUT) ||\
00438                                 ((TISEL) == TIM_TIM2_TI4_GPIO)     ||\
00439                                 ((TISEL) == TIM_TIM2_TI4_COMP1_OUT)      ||\
00440                                 ((TISEL) == TIM_TIM2_TI4_COMP2_OUT)      ||\
00441                                 ((TISEL) == TIM_TIM2_TI4_COMP1COMP2_OUT) ||\
00442                                 ((TISEL) == TIM_TIM3_TI1_GPIO) ||\
00443                                 ((TISEL) == TIM_TIM3_TI1_COMP1_OUT) ||\
00444                                 ((TISEL) == TIM_TIM3_TI1_COMP2_OUT) ||\
00445                                 ((TISEL) == TIM_TIM3_TI1_COMP1COMP2_OUT) ||\
00446                                 ((TISEL) == TIM_TIM5_TI1_GPIO) ||\
00447                                 ((TISEL) == TIM_TIM5_TI1_CAN_TMP) ||\
00448                                 ((TISEL) == TIM_TIM5_TI1_CAN_RTP) ||\
00449                                 ((TISEL) == TIM_TIM15_TI1_GPIO) ||\
00450                                 ((TISEL) == TIM_TIM15_TI1_TIM2_CH1) ||\
00451                                 ((TISEL) == TIM_TIM15_TI1_TIM3_CH1) ||\
00452                                 ((TISEL) == TIM_TIM15_TI1_TIM4_CH1) ||\
00453                                 ((TISEL) == TIM_TIM15_TI1_RCC_LSE) ||\
00454                                 ((TISEL) == TIM_TIM15_TI1_RCC_CSI) ||\
00455                                 ((TISEL) == TIM_TIM15_TI1_RCC_MCO2) ||\
00456                                 ((TISEL) == TIM_TIM15_TI2_GPIO) ||\
00457                                 ((TISEL) == TIM_TIM15_TI2_TIM2_CH2) ||\
00458                                 ((TISEL) == TIM_TIM15_TI2_TIM3_CH2) ||\
00459                                 ((TISEL) == TIM_TIM15_TI2_TIM4_CH2) ||\
00460                                 ((TISEL) == TIM_TIM16_TI1_GPIO) ||\
00461                                 ((TISEL) == TIM_TIM16_TI1_RCC_LSI) ||\
00462                                 ((TISEL) == TIM_TIM16_TI1_RCC_LSE) ||\
00463                                 ((TISEL) == TIM_TIM16_TI1_WKUP_IT) ||\
00464                                 ((TISEL) == TIM_TIM17_TI1_GPIO) ||\
00465                                 ((TISEL) == TIM_TIM17_TI1_SPDIF_FS) ||\
00466                                 ((TISEL) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\
00467                                 ((TISEL) == TIM_TIM17_TI1_RCC_MCO1))
00468
00469 #define IS_TIM_BKR2REMAP(BK2RREMAP)    (((BKR2REMAP) == TIM_TIM1_BKR_GPIO)      ||\
00470                                         ((BKR2REMAP) == TIM_TIM1_BKR_GPIO)      ||\
00471                                         ((BKR2REMAP) == TIM_TIM1_BKR_GPIO)      ||\
00472                                         ((BKR2REMAP) == TIM_TIM1_BKR_GPIO)      ||\
00473                                         ((BKR2REMAP) == TIM_TIM1_BKR_GPIO)      ||\
00474                                         ((BKR2REMAP) == TIM_TIM1_BKR_GPIO)      ||\
00475                                         ((BKR2REMAP) == TIM_TIM1_BKR_GPIO)      ||\
00476                                         ((BKR2REMAP) == TIM_TIM1_BKR_GPIO))
00477
00478 #define IS_TIM_BKRREMAP(BKRREMAP)    (((BKRREMAP) == TIM_TIM1_BKR_GPIO)      ||\
00479                                       ((BKRREMAP) == TIM_TIM1_BKR_COMP1_OUT)      ||\
00480                                       ((BKRREMAP) == TIM_TIM1_BKR_COMP2_OUT)      ||\
00481                                       ((BKRREMAP) == TIM_TIM1_BKR_DFSDM_BRK0)      ||\
00482                                       ((BKRREMAP) == TIM_TIM8_BKR_GPIO)      ||\
00483                                       ((BKRREMAP) == TIM_TIM8_BKR_COMP1_OUT)      ||\
00484                                       ((BKRREMAP) == TIM_TIM8_BKR_COMP2_OUT)      ||\
00485                                       ((BKRREMAP) == TIM_TIM8_BKR_DFSDM_BRK2)      ||\
00486                                       ((BKRREMAP) == TIM_TIM15_BKR_GPIO)      ||\
00487                                       ((BKRREMAP) == TIM_TIM15_BKR_COMP1_OUT)      ||\
00488                                       ((BKRREMAP) == TIM_TIM15_BKR_COMP2_OUT)      ||\
00489                                       ((BKRREMAP) == TIM_TIM15_BKR_DFSDM_BRK0)      ||\
00490                                       ((BKRREMAP) == TIM_TIM16_BKR_GPIO)      ||\
00491                                       ((BKRREMAP) == TIM_TIM16_BKR_COMP1_OUT)      ||\
00492                                       ((BKRREMAP) == TIM_TIM16_BKR_COMP2_OUT)      ||\
00493                                       ((BKRREMAP) == TIM_TIM16_BKR_DFSDM_BRK1)      ||\
00494                                       ((BKRREMAP) == TIM_TIM17_BKR_GPIO)      ||\
00495                                       ((BKRREMAP) == TIM_TIM17_BKR_COMP1_OUT)      ||\
00496                                       ((BKRREMAP) == TIM_TIM17_BKR_COMP2_OUT)      ||\
00497                                       ((BKRREMAP) == TIM_TIM17_BKR_DFSDM_BRK2))
00498
00499 #define IS_TIM_ETRREMAP(ETRREMAP)    (((ETRREMAP) == TIM_TIM1_ETR_GPIO)      ||\
00500                                       ((ETRREMAP) == TIM_TIM1_ETR_ADC1_AWD1) ||\
00501                                       ((ETRREMAP) == TIM_TIM1_ETR_ADC1_AWD2) ||\
00502                                       ((ETRREMAP) == TIM_TIM1_ETR_ADC1_AWD3) ||\
00503                                       ((ETRREMAP) == TIM_TIM1_ETR_ADC3_AWD1) ||\
00504                                       ((ETRREMAP) == TIM_TIM1_ETR_ADC3_AWD2) ||\
00505                                       ((ETRREMAP) == TIM_TIM1_ETR_ADC3_AWD3) ||\
00506                                       ((ETRREMAP) == TIM_TIM1_ETR_COMP1_OUT) ||\
00507                                       ((ETRREMAP) == TIM_TIM1_ETR_COMP2_OUT) ||\
00508                                       ((ETRREMAP) == TIM_TIM8_ETR_GPIO)      ||\
00509                                       ((ETRREMAP) == TIM_TIM8_ETR_ADC2_AWD1) ||\
00510                                       ((ETRREMAP) == TIM_TIM8_ETR_ADC2_AWD2) ||\
00511                                       ((ETRREMAP) == TIM_TIM8_ETR_ADC2_AWD3) ||\
00512                                       ((ETRREMAP) == TIM_TIM8_ETR_ADC3_AWD1) ||\
00513                                       ((ETRREMAP) == TIM_TIM8_ETR_ADC3_AWD2) ||\
00514                                       ((ETRREMAP) == TIM_TIM8_ETR_ADC3_AWD3) ||\
00515                                       ((ETRREMAP) == TIM_TIM8_ETR_COMP1_OUT) ||\
00516                                       ((ETRREMAP) == TIM_TIM8_ETR_COMP2_OUT) ||\
00517                                       ((ETRREMAP) == TIM_TIM2_ETR_GPIO)      ||\
00518                                       ((ETRREMAP) == TIM_TIM2_ETR_COMP1_OUT) ||\
00519                                       ((ETRREMAP) == TIM_TIM2_ETR_COMP2_OUT) ||\
00520                                       ((ETRREMAP) == TIM_TIM2_ETR_RCC_LSE)   ||\
00521                                       ((ETRREMAP) == TIM_TIM2_ETR_SAI1_FSA)  ||\
00522                                       ((ETRREMAP) == TIM_TIM2_ETR_SAI1_FSB)  ||\
00523                                       ((ETRREMAP) == TIM_TIM3_ETR_GPIO)      ||\
00524                                       ((ETRREMAP) == TIM_TIM3_ETR_COMP1_OUT) ||\
00525                                       ((ETRREMAP) == TIM_TIM5_ETR_GPIO)      ||\
00526                                       ((ETRREMAP) == TIM_TIM5_ETR_SAI2_FSA)  |\
00527                                       ((ETRREMAP) == TIM_TIM5_ETR_SAI2_FSB))
00528 /**
00529   * @}
00530   */
00531 /* End of private macro ------------------------------------------------------*/
00532
00533 /* Exported functions --------------------------------------------------------*/
00534 /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
00535   * @{
00536   */
00537
00538 /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
00539  *  @brief    Timer Hall Sensor functions
00540  * @{
00541  */
00542 /*  Timer Hall Sensor functions  **********************************************/
00543 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
00544 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
00545
00546 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
00547 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
00548
00549  /* Blocking mode: Polling */
00550 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
00551 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
00552 /* Non-Blocking mode: Interrupt */
00553 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
00554 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
00555 /* Non-Blocking mode: DMA */
00556 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
00557 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
00558 /**
00559   * @}
00560   */
00561
00562 /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
00563  *  @brief   Timer Complementary Output Compare functions
00564  * @{
00565  */
00566 /*  Timer Complementary Output Compare functions  *****************************/
00567 /* Blocking mode: Polling */
00568 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
00569 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
00570
00571 /* Non-Blocking mode: Interrupt */
00572 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00573 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00574
00575 /* Non-Blocking mode: DMA */
00576 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
00577 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
00578 /**
00579   * @}
00580   */
00581
00582 /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
00583  *  @brief    Timer Complementary PWM functions
00584  * @{
00585  */
00586 /*  Timer Complementary PWM functions  ****************************************/
00587 /* Blocking mode: Polling */
00588 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
00589 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
00590
00591 /* Non-Blocking mode: Interrupt */
00592 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00593 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00594 /* Non-Blocking mode: DMA */
00595 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
00596 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
00597 /**
00598   * @}
00599   */
00600
00601 /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
00602  *  @brief    Timer Complementary One Pulse functions
00603  * @{
00604  */
00605 /*  Timer Complementary One Pulse functions  **********************************/
00606 /* Blocking mode: Polling */
00607 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00608 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00609
00610 /* Non-Blocking mode: Interrupt */
00611 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00612 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00613 /**
00614   * @}
00615   */
00616
00617 /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
00618  *  @brief    Peripheral Control functions
00619  * @{
00620  */
00621 /* Extended Control functions  ************************************************/
00622 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
00623 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
00624 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
00625 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
00626 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
00627 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
00628 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
00629 HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection , uint32_t Channel);
00630 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
00631
00632 /**
00633   * @}
00634   */
00635
00636 /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
00637   * @brief    Extended Callbacks functions
00638   * @{
00639   */
00640 /* Extended Callback *********************************************************/
00641 void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
00642 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
00643
00644 /**
00645   * @}
00646   */
00647
00648 /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
00649   * @brief    Extended Peripheral State functions
00650   * @{
00651   */
00652 /* Extended Peripheral State functions  **************************************/
00653 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
00654 /**
00655   * @}
00656   */
00657 /* End of exported functions -------------------------------------------------*/
00658 /**
00659   * @}
00660   */
00661 /* Private functions----------------------------------------------------------*/
00662 /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
00663 * @{
00664 */
00665 void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
00666 /**
00667 * @}
00668 */
00669 /* End of private functions --------------------------------------------------*/
00670 /**
00671   * @}
00672   */
00673
00674 /**
00675   * @}
00676   */
00677
00678 /**
00679   * @}
00680   */
00681 #ifdef __cplusplus
00682 }
00683 #endif
00684
00685 #endif /* __STM32H7xx_HAL_TIM_EX_H */
00686
00687 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_uart.c Source File

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stm32h7xx_hal_uart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_uart.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   UART HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *
00014   *
00015   @verbatim
00016  ===============================================================================
00017                         ##### How to use this driver #####
00018  ===============================================================================
00019   [..]
00020     The UART HAL driver can be used as follows:
00021
00022     (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
00023     (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
00024         (++) Enable the USARTx interface clock.
00025         (++) UART pins configuration:
00026             (+++) Enable the clock for the UART GPIOs.
00027             (+++) Configure these UART pins as alternate function pull-up.
00028         (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
00029              and HAL_UART_Receive_IT() APIs):
00030             (+++) Configure the USARTx interrupt priority.
00031             (+++) Enable the NVIC USART IRQ handle.
00032         (++) UART interrupts handling:
00033               -@@-  The specific UART interrupts (Transmission complete interrupt,
00034                 RXNE interrupt and Error Interrupts) are managed using the macros
00035                 __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive processes.
00036         (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
00037              and HAL_UART_Receive_DMA() APIs):
00038             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00039             (+++) Enable the DMAx interface clock.
00040             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00041             (+++) Configure the DMA Tx/Rx channel.
00042             (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
00043             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00044
00045     (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
00046         flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
00047
00048     (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
00049         in the huart handle AdvancedInit structure.
00050
00051     (#) For the UART asynchronous mode, initialize the UART registers by calling
00052         the HAL_UART_Init() API.
00053
00054     (#) For the UART Half duplex mode, initialize the UART registers by calling
00055         the HAL_HalfDuplex_Init() API.
00056
00057     (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
00058         by calling the HAL_LIN_Init() API.
00059
00060     (#) For the UART Multiprocessor mode, initialize the UART registers
00061         by calling the HAL_MultiProcessor_Init() API.
00062
00063     (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
00064         by calling the HAL_RS485Ex_Init() API.
00065
00066     [..]
00067     (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
00068         also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
00069         calling the customized HAL_UART_MspInit() API.
00070
00071   @endverbatim
00072   ******************************************************************************
00073   * @attention
00074   *
00075   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00076   *
00077   * Redistribution and use in source and binary forms, with or without modification,
00078   * are permitted provided that the following conditions are met:
00079   *   1. Redistributions of source code must retain the above copyright notice,
00080   *      this list of conditions and the following disclaimer.
00081   *   2. Redistributions in binary form must reproduce the above copyright notice,
00082   *      this list of conditions and the following disclaimer in the documentation
00083   *      and/or other materials provided with the distribution.
00084   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00085   *      may be used to endorse or promote products derived from this software
00086   *      without specific prior written permission.
00087   *
00088   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00089   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00090   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00091   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00092   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00093   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00094   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00095   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00096   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00097   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00098   *
00099   ******************************************************************************
00100   */
00101
00102 /* Includes ------------------------------------------------------------------*/
00103 #include "stm32h7xx_hal.h"
00104
00105 /** @addtogroup STM32H7xx_HAL_Driver
00106   * @{
00107   */
00108
00109 /** @defgroup UART UART
00110   * @brief HAL UART module driver
00111   * @{
00112   */
00113
00114 #ifdef HAL_UART_MODULE_ENABLED
00115
00116 /* Private typedef -----------------------------------------------------------*/
00117 /* Private define ------------------------------------------------------------*/
00118 /** @defgroup UART_Private_Constants UART Private Constants
00119   * @{
00120   */
00121 #define UART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
00122                                      USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
00123                                      USART_CR1_FIFOEN ))                      /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
00124
00125 #define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \
00126                                     USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))  /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
00127
00128 #define UART_LPUART_BRR_MIN           ((uint32_t)0x00000300)  /* LPUART BRR minimum authorized value */
00129 #define UART_LPUART_BRR_MAX           ((uint32_t)0x000FFFFF)  /* LPUART BRR maximum authorized value */
00130 /**
00131   * @}
00132   */
00133
00134 /* Private macros ------------------------------------------------------------*/
00135 /* Private variables ---------------------------------------------------------*/
00136 /* Private function prototypes -----------------------------------------------*/
00137 /** @addtogroup UART_Private_Functions
00138   * @{
00139   */
00140 static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
00141 static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
00142 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00143 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00144 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00145 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00146 static void UART_DMAError(DMA_HandleTypeDef *hdma);
00147 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00148 static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00149 static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00150 static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00151 static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00152 static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
00153 static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
00154 static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
00155 /**
00156   * @}
00157   */
00158
00159 /* Exported functions --------------------------------------------------------*/
00160
00161 /** @defgroup UART_Exported_Functions UART Exported Functions
00162   * @{
00163   */
00164
00165 /** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
00166   *  @brief    Initialization and Configuration functions
00167   *
00168 @verbatim
00169 ===============================================================================
00170             ##### Initialization and Configuration functions #####
00171  ===============================================================================
00172     [..]
00173     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
00174     in asynchronous mode.
00175       (+) For the asynchronous mode the parameters below can be configured:
00176         (++) Baud Rate
00177         (++) Word Length
00178         (++) Stop Bit
00179         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00180              in the data register is transmitted but is changed by the parity bit.
00181         (++) Hardware flow control
00182         (++) Receiver/transmitter modes
00183         (++) Over Sampling Method
00184         (++) One-Bit Sampling Method
00185       (+) For the asynchronous mode, the following advanced features can be configured as well:
00186         (++) TX and/or RX pin level inversion
00187         (++) data logical level inversion
00188         (++) RX and TX pins swap
00189         (++) RX overrun detection disabling
00190         (++) DMA disabling on RX error
00191         (++) MSB first on communication line
00192         (++) auto Baud rate detection
00193     [..]
00194     The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
00195     follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
00196     and UART multiprocessor mode configuration procedures (details for the procedures
00197     are available in reference manual).
00198
00199 @endverbatim
00200
00201   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00202   8-bit or 9-bit), the possible UART formats are listed in the
00203   following table.
00204
00205   Table 1. UART frame format.
00206     +-----------------------------------------------------------------------+
00207     |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
00208     |---------|---------|-----------|---------------------------------------|
00209     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00210     |---------|---------|-----------|---------------------------------------|
00211     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00212     |---------|---------|-----------|---------------------------------------|
00213     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00214     |---------|---------|-----------|---------------------------------------|
00215     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00216     |---------|---------|-----------|---------------------------------------|
00217     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00218     |---------|---------|-----------|---------------------------------------|
00219     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00220     +-----------------------------------------------------------------------+
00221
00222   * @{
00223   */
00224
00225 /**
00226   * @brief Initialize the UART mode according to the specified
00227   *        parameters in the UART_InitTypeDef and initialize the associated handle.
00228   * @param huart: UART handle.
00229   * @retval HAL status
00230   */
00231 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
00232 {
00233   /* Check the UART handle allocation */
00234   if(huart == NULL)
00235   {
00236     return HAL_ERROR;
00237   }
00238
00239   if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
00240   {
00241     /* Check the parameters */
00242     assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
00243   }
00244   else
00245   {
00246     /* Check the parameters */
00247     assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
00248   }
00249
00250   if(huart->gState == HAL_UART_STATE_RESET)
00251   {
00252     /* Allocate lock resource and initialize it */
00253     huart->Lock = HAL_UNLOCKED;
00254
00255     /* Init the low level hardware : GPIO, CLOCK */
00256     HAL_UART_MspInit(huart);
00257   }
00258
00259   huart->gState = HAL_UART_STATE_BUSY;
00260
00261   /* Disable the Peripheral */
00262   __HAL_UART_DISABLE(huart);
00263
00264   /* Set the UART Communication parameters */
00265   if (UART_SetConfig(huart) == HAL_ERROR)
00266   {
00267     return HAL_ERROR;
00268   }
00269
00270   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00271   {
00272     UART_AdvFeatureConfig(huart);
00273   }
00274
00275   /* In asynchronous mode, the following bits must be kept cleared:
00276   - LINEN and CLKEN bits in the USART_CR2 register,
00277   - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
00278   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00279   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
00280
00281   /* Enable the Peripheral */
00282   __HAL_UART_ENABLE(huart);
00283
00284   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00285   return (UART_CheckIdleState(huart));
00286 }
00287
00288 /**
00289   * @brief Initialize the half-duplex mode according to the specified
00290   *        parameters in the UART_InitTypeDef and creates the associated handle.
00291   * @param huart: UART handle.
00292   * @retval HAL status
00293   */
00294 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
00295 {
00296   /* Check the UART handle allocation */
00297   if(huart == NULL)
00298   {
00299     return HAL_ERROR;
00300   }
00301
00302   /* Check UART instance */
00303   assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
00304
00305   if(huart->gState == HAL_UART_STATE_RESET)
00306   {
00307     /* Allocate lock resource and initialize it */
00308     huart->Lock = HAL_UNLOCKED;
00309
00310     /* Init the low level hardware : GPIO, CLOCK */
00311     HAL_UART_MspInit(huart);
00312   }
00313
00314   huart->gState = HAL_UART_STATE_BUSY;
00315
00316   /* Disable the Peripheral */
00317   __HAL_UART_DISABLE(huart);
00318
00319   /* Set the UART Communication parameters */
00320   if (UART_SetConfig(huart) == HAL_ERROR)
00321   {
00322     return HAL_ERROR;
00323   }
00324
00325   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00326   {
00327     UART_AdvFeatureConfig(huart);
00328   }
00329
00330   /* In half-duplex mode, the following bits must be kept cleared:
00331   - LINEN and CLKEN bits in the USART_CR2 register,
00332   - SCEN and IREN bits in the USART_CR3 register.*/
00333   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00334   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
00335
00336   /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
00337   SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
00338
00339   /* Enable the Peripheral */
00340   __HAL_UART_ENABLE(huart);
00341
00342   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00343   return (UART_CheckIdleState(huart));
00344 }
00345
00346
00347 /**
00348   * @brief Initialize the LIN mode according to the specified
00349   *        parameters in the UART_InitTypeDef and creates the associated handle .
00350   * @param huart: UART handle.
00351   * @param BreakDetectLength: specifies the LIN break detection length.
00352   *        This parameter can be one of the following values:
00353   *          @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
00354   *          @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
00355   * @retval HAL status
00356   */
00357 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
00358 {
00359   /* Check the UART handle allocation */
00360   if(huart == NULL)
00361   {
00362     return HAL_ERROR;
00363   }
00364
00365   /* Check the LIN UART instance */
00366   assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
00367   /* Check the Break detection length parameter */
00368   assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
00369
00370   /* LIN mode limited to 16-bit oversampling only */
00371   if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
00372   {
00373     return HAL_ERROR;
00374   }
00375   /* LIN mode limited to 8-bit data length */
00376   if(huart->Init.WordLength != UART_WORDLENGTH_8B)
00377   {
00378     return HAL_ERROR;
00379   }
00380
00381   if(huart->gState == HAL_UART_STATE_RESET)
00382   {
00383     /* Allocate lock resource and initialize it */
00384     huart->Lock = HAL_UNLOCKED;
00385
00386     /* Init the low level hardware : GPIO, CLOCK */
00387     HAL_UART_MspInit(huart);
00388   }
00389
00390   huart->gState = HAL_UART_STATE_BUSY;
00391
00392   /* Disable the Peripheral */
00393   __HAL_UART_DISABLE(huart);
00394
00395   /* Set the UART Communication parameters */
00396   if (UART_SetConfig(huart) == HAL_ERROR)
00397   {
00398     return HAL_ERROR;
00399   }
00400
00401   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00402   {
00403     UART_AdvFeatureConfig(huart);
00404   }
00405
00406   /* In LIN mode, the following bits must be kept cleared:
00407   - LINEN and CLKEN bits in the USART_CR2 register,
00408   - SCEN and IREN bits in the USART_CR3 register.*/
00409   CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
00410   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
00411
00412   /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
00413   SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
00414
00415   /* Set the USART LIN Break detection length. */
00416   MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
00417
00418   /* Enable the Peripheral */
00419   __HAL_UART_ENABLE(huart);
00420
00421   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00422   return (UART_CheckIdleState(huart));
00423 }
00424
00425
00426 /**
00427   * @brief Initialize the multiprocessor mode according to the specified
00428   *        parameters in the UART_InitTypeDef and initialize the associated handle.
00429   * @param huart: UART handle.
00430   * @param Address: UART node address (4-, 6-, 7- or 8-bit long).
00431   * @param WakeUpMethod: specifies the UART wakeup method.
00432   *        This parameter can be one of the following values:
00433   *          @arg UART_WAKEUPMETHOD_IDLELINE: WakeUp by an idle line detection
00434   *          @arg UART_WAKEUPMETHOD_ADDRESSMARK: WakeUp by an address mark
00435   * @note  If the user resorts to idle line detection wake up, the Address parameter
00436   *        is useless and ignored by the initialization function.
00437   * @note  If the user resorts to address mark wake up, the address length detection
00438   *        is configured by default to 4 bits only. For the UART to be able to
00439   *        manage 6-, 7- or 8-bit long addresses detection, the API
00440   *        HAL_MultiProcessorEx_AddressLength_Set() must be called after
00441   *        HAL_MultiProcessor_Init().
00442   * @retval HAL status
00443   */
00444 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
00445 {
00446   /* Check the UART handle allocation */
00447   if(huart == NULL)
00448   {
00449     return HAL_ERROR;
00450   }
00451
00452   /* Check the wake up method parameter */
00453   assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
00454
00455   if(huart->gState == HAL_UART_STATE_RESET)
00456   {
00457     /* Allocate lock resource and initialize it */
00458     huart->Lock = HAL_UNLOCKED;
00459
00460     /* Init the low level hardware : GPIO, CLOCK */
00461     HAL_UART_MspInit(huart);
00462   }
00463
00464   huart->gState = HAL_UART_STATE_BUSY;
00465
00466   /* Disable the Peripheral */
00467   __HAL_UART_DISABLE(huart);
00468
00469   /* Set the UART Communication parameters */
00470   if (UART_SetConfig(huart) == HAL_ERROR)
00471   {
00472     return HAL_ERROR;
00473   }
00474
00475   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00476   {
00477     UART_AdvFeatureConfig(huart);
00478   }
00479
00480   /* In multiprocessor mode, the following bits must be kept cleared:
00481   - LINEN and CLKEN bits in the USART_CR2 register,
00482   - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */
00483   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00484   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
00485
00486   if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
00487   {
00488     /* If address mark wake up method is chosen, set the USART address node */
00489     MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
00490   }
00491
00492   /* Set the wake up method by setting the WAKE bit in the CR1 register */
00493   MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
00494
00495   /* Enable the Peripheral */
00496   __HAL_UART_ENABLE(huart);
00497
00498   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00499   return (UART_CheckIdleState(huart));
00500 }
00501
00502
00503 /**
00504   * @brief DeInitialize the UART peripheral.
00505   * @param huart: UART handle.
00506   * @retval HAL status
00507   */
00508 HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
00509 {
00510   /* Check the UART handle allocation */
00511   if(huart == NULL)
00512   {
00513     return HAL_ERROR;
00514   }
00515
00516   /* Check the parameters */
00517   assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
00518
00519   huart->gState = HAL_UART_STATE_BUSY;
00520
00521   /* Disable the Peripheral */
00522   __HAL_UART_DISABLE(huart);
00523
00524   huart->Instance->CR1 = 0x0U;
00525   huart->Instance->CR2 = 0x0U;
00526   huart->Instance->CR3 = 0x0U;
00527
00528   /* DeInit the low level hardware */
00529   HAL_UART_MspDeInit(huart);
00530
00531   huart->ErrorCode = HAL_UART_ERROR_NONE;
00532   huart->gState = HAL_UART_STATE_RESET;
00533   huart->RxState = HAL_UART_STATE_RESET;
00534
00535   /* Process Unlock */
00536   __HAL_UNLOCK(huart);
00537
00538   return HAL_OK;
00539 }
00540
00541 /**
00542   * @brief Initialize the UART MSP.
00543   * @param huart: UART handle.
00544   * @retval None
00545   */
00546 __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
00547 {
00548   /* Prevent unused argument(s) compilation warning */
00549   UNUSED(huart);
00550
00551   /* NOTE : This function should not be modified, when the callback is needed,
00552             the HAL_UART_MspInit can be implemented in the user file
00553    */
00554 }
00555
00556 /**
00557   * @brief DeInitialize the UART MSP.
00558   * @param huart: UART handle.
00559   * @retval None
00560   */
00561 __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
00562 {
00563   /* Prevent unused argument(s) compilation warning */
00564   UNUSED(huart);
00565
00566   /* NOTE : This function should not be modified, when the callback is needed,
00567             the HAL_UART_MspDeInit can be implemented in the user file
00568    */
00569 }
00570
00571 /**
00572   * @}
00573   */
00574
00575 /** @defgroup UART_Exported_Functions_Group2 IO operation functions
00576   * @brief UART Transmit/Receive functions
00577   *
00578 @verbatim
00579  ===============================================================================
00580                       ##### IO operation functions #####
00581  ===============================================================================
00582     This subsection provides a set of functions allowing to manage the UART asynchronous
00583     and Half duplex data transfers.
00584
00585     (#) There are two mode of transfer:
00586        (+) Blocking mode: The communication is performed in polling mode.
00587            The HAL status of all data processing is returned by the same function
00588            after finishing transfer.
00589        (+) Non-Blocking mode: The communication is performed using Interrupts
00590            or DMA, These API's return the HAL status.
00591            The end of the data processing will be indicated through the
00592            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
00593            using DMA mode.
00594            The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
00595            will be executed respectively at the end of the transmit or Receive process
00596            The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
00597
00598     (#) Blocking mode API's are :
00599         (+) HAL_UART_Transmit()
00600         (+) HAL_UART_Receive()
00601
00602     (#) Non-Blocking mode API's with Interrupt are :
00603         (+) HAL_UART_Transmit_IT()
00604         (+) HAL_UART_Receive_IT()
00605         (+) HAL_UART_IRQHandler()
00606
00607     (#) Non-Blocking mode API's with DMA are :
00608         (+) HAL_UART_Transmit_DMA()
00609         (+) HAL_UART_Receive_DMA()
00610         (+) HAL_UART_DMAPause()
00611         (+) HAL_UART_DMAResume()
00612         (+) HAL_UART_DMAStop()
00613
00614     (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
00615         (+) HAL_UART_TxHalfCpltCallback()
00616         (+) HAL_UART_TxCpltCallback()
00617         (+) HAL_UART_RxHalfCpltCallback()
00618         (+) HAL_UART_RxCpltCallback()
00619         (+) HAL_UART_ErrorCallback()
00620
00621     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00622         (+) HAL_UART_Abort()
00623         (+) HAL_UART_AbortTransmit()
00624         (+) HAL_UART_AbortReceive()
00625         (+) HAL_UART_Abort_IT()
00626         (+) HAL_UART_AbortTransmit_IT()
00627         (+) HAL_UART_AbortReceive_IT()
00628
00629     (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
00630         (+) HAL_UART_AbortCpltCallback()
00631         (+) HAL_UART_AbortTransmitCpltCallback()
00632         (+) HAL_UART_AbortReceiveCpltCallback()
00633
00634     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00635         Errors are handled as follows :
00636        (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00637            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
00638            Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
00639            and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
00640            If user wants to abort it, Abort services should be called by user.
00641        (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00642            This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
00643            Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
00644
00645     -@- In the Half duplex communication, it is forbidden to run the transmit
00646         and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
00647
00648 @endverbatim
00649   * @{
00650   */
00651
00652 /**
00653   * @brief Send an amount of data in blocking mode.
00654   * @param huart: UART handle.
00655   * @param pData: Pointer to data buffer.
00656   * @param Size: Amount of data to be sent.
00657   * @param Timeout: Timeout duration.
00658   * @retval HAL status
00659   */
00660 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00661 {
00662   uint16_t* tmp;
00663   uint32_t tickstart = 0U;
00664
00665   /* Check that a Tx process is not already ongoing */
00666   if(huart->gState == HAL_UART_STATE_READY)
00667   {
00668     if((pData == NULL ) || (Size == 0U))
00669     {
00670       return  HAL_ERROR;
00671     }
00672
00673     /* Process Locked */
00674     __HAL_LOCK(huart);
00675
00676     huart->ErrorCode = HAL_UART_ERROR_NONE;
00677     huart->gState = HAL_UART_STATE_BUSY_TX;
00678
00679     /* Init tickstart for timeout managment*/
00680     tickstart = HAL_GetTick();
00681
00682     huart->TxXferSize = Size;
00683     huart->TxXferCount = Size;
00684     while(huart->TxXferCount > 0U)
00685     {
00686       huart->TxXferCount--;
00687       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00688       {
00689         return HAL_TIMEOUT;
00690       }
00691       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
00692       {
00693         tmp = (uint16_t*) pData;
00694         huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
00695         pData += 2U;
00696       }
00697       else
00698       {
00699         huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
00700       }
00701     }
00702     if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00703     {
00704       return HAL_TIMEOUT;
00705     }
00706
00707     /* At end of Tx process, restore huart->gState to Ready */
00708     huart->gState = HAL_UART_STATE_READY;
00709
00710     /* Process Unlocked */
00711     __HAL_UNLOCK(huart);
00712
00713     return HAL_OK;
00714   }
00715   else
00716   {
00717     return HAL_BUSY;
00718   }
00719 }
00720
00721 /**
00722   * @brief Receive an amount of data in blocking mode.
00723   * @param huart: UART handle.
00724   * @param pData: pointer to data buffer.
00725   * @param Size: amount of data to be received.
00726   * @param Timeout: Timeout duration.
00727   * @retval HAL status
00728   */
00729 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00730 {
00731   uint16_t* tmp;
00732   uint16_t uhMask;
00733   uint32_t tickstart = 0;
00734
00735   /* Check that a Rx process is not already ongoing */
00736   if(huart->RxState == HAL_UART_STATE_READY)
00737   {
00738     if((pData == NULL ) || (Size == 0U))
00739     {
00740       return  HAL_ERROR;
00741     }
00742
00743     /* Process Locked */
00744     __HAL_LOCK(huart);
00745
00746     huart->ErrorCode = HAL_UART_ERROR_NONE;
00747     huart->RxState = HAL_UART_STATE_BUSY_RX;
00748
00749     /* Init tickstart for timeout managment*/
00750     tickstart = HAL_GetTick();
00751
00752     huart->RxXferSize = Size;
00753     huart->RxXferCount = Size;
00754
00755     /* Computation of UART mask to apply to RDR register */
00756     UART_MASK_COMPUTATION(huart);
00757     uhMask = huart->Mask;
00758
00759     /* as long as data have to be received */
00760     while(huart->RxXferCount > 0U)
00761     {
00762       huart->RxXferCount--;
00763       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00764       {
00765         return HAL_TIMEOUT;
00766       }
00767       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
00768       {
00769         tmp = (uint16_t*) pData ;
00770         *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
00771         pData +=2U;
00772       }
00773       else
00774       {
00775         *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
00776       }
00777     }
00778
00779     /* At end of Rx process, restore huart->RxState to Ready */
00780     huart->RxState = HAL_UART_STATE_READY;
00781
00782     /* Process Unlocked */
00783     __HAL_UNLOCK(huart);
00784
00785     return HAL_OK;
00786   }
00787   else
00788   {
00789     return HAL_BUSY;
00790   }
00791 }
00792
00793 /**
00794   * @brief Send an amount of data in interrupt mode.
00795   * @param huart: UART handle.
00796   * @param pData: pointer to data buffer.
00797   * @param Size: amount of data to be sent.
00798   * @retval HAL status
00799   */
00800 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00801 {
00802   /* Check that a Tx process is not already ongoing */
00803   if(huart->gState == HAL_UART_STATE_READY)
00804   {
00805     if((pData == NULL ) || (Size == 0U))
00806     {
00807       return HAL_ERROR;
00808     }
00809
00810     /* Process Locked */
00811     __HAL_LOCK(huart);
00812
00813     huart->pTxBuffPtr = pData;
00814     huart->TxXferSize = Size;
00815     huart->TxXferCount = Size;
00816
00817     huart->ErrorCode = HAL_UART_ERROR_NONE;
00818     huart->gState = HAL_UART_STATE_BUSY_TX;
00819
00820     /* Process Unlocked */
00821     __HAL_UNLOCK(huart);
00822
00823     /* Enable the TX FIFO threshold interrupt (if FIFO mode is enabled) or
00824        Transmit Data Register Empty interrupt (if FIFO mode is Disabled).
00825     */
00826     if (READ_BIT(huart->Instance->CR1, USART_CR1_FIFOEN) != RESET)
00827     {
00828       SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
00829     }
00830     else
00831     {
00832       SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
00833     }
00834
00835     return HAL_OK;
00836   }
00837   else
00838   {
00839     return HAL_BUSY;
00840   }
00841 }
00842
00843 /**
00844   * @brief Receive an amount of data in interrupt mode.
00845   * @param huart: UART handle.
00846   * @param pData: pointer to data buffer.
00847   * @param Size: amount of data to be received.
00848   * @retval HAL status
00849   */
00850 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00851 {
00852   /* Check that a Rx process is not already ongoing */
00853   if(huart->RxState == HAL_UART_STATE_READY)
00854   {
00855     if((pData == NULL ) || (Size == 0U))
00856     {
00857       return HAL_ERROR;
00858     }
00859
00860     /* Process Locked */
00861     __HAL_LOCK(huart);
00862
00863     huart->pRxBuffPtr = pData;
00864     huart->RxXferSize = Size;
00865     huart->RxXferCount = Size;
00866
00867     /* Computation of UART mask to apply to RDR register */
00868     UART_MASK_COMPUTATION(huart);
00869
00870     huart->ErrorCode = HAL_UART_ERROR_NONE;
00871     huart->RxState = HAL_UART_STATE_BUSY_RX;
00872
00873     /* Process Unlocked */
00874     __HAL_UNLOCK(huart);
00875
00876     /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
00877     SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
00878
00879     /* Enable the UART Parity Error interupt and RX FIFO Threshold interrupt
00880        (if FIFO mode is enabled) or Data Register Not Empty interrupt
00881        (if FIFO mode is disabled).
00882     */
00883     if (READ_BIT(huart->Instance->CR1, USART_CR1_FIFOEN) != RESET)
00884     {
00885       SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
00886       SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
00887     }
00888     else
00889     {
00890       SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
00891     }
00892
00893     return HAL_OK;
00894   }
00895   else
00896   {
00897     return HAL_BUSY;
00898   }
00899 }
00900
00901 /**
00902   * @brief Send an amount of data in DMA mode.
00903   * @param huart: UART handle.
00904   * @param pData: pointer to data buffer.
00905   * @param Size: amount of data to be sent.
00906   * @retval HAL status
00907   */
00908 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00909 {
00910   /* Check that a Tx process is not already ongoing */
00911   if(huart->gState == HAL_UART_STATE_READY)
00912   {
00913     if((pData == NULL ) || (Size == 0U))
00914     {
00915       return HAL_ERROR;
00916     }
00917
00918     /* Process Locked */
00919     __HAL_LOCK(huart);
00920
00921     huart->pTxBuffPtr = pData;
00922     huart->TxXferSize = Size;
00923     huart->TxXferCount = Size;
00924
00925     huart->ErrorCode = HAL_UART_ERROR_NONE;
00926     huart->gState = HAL_UART_STATE_BUSY_TX;
00927
00928     /* Set the UART DMA transfer complete callback */
00929     huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
00930
00931     /* Set the UART DMA Half transfer complete callback */
00932     huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
00933
00934     /* Set the DMA error callback */
00935     huart->hdmatx->XferErrorCallback = UART_DMAError;
00936
00937     /* Set the DMA abort callback */
00938     huart->hdmatx->XferAbortCallback = NULL;
00939
00940     /* Enable the UART transmit DMA channel */
00941     HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size);
00942
00943     /* Clear the TC flag in the ICR register */
00944     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
00945
00946     /* Process Unlocked */
00947     __HAL_UNLOCK(huart);
00948
00949     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00950        in the UART CR3 register */
00951     SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
00952
00953     return HAL_OK;
00954   }
00955   else
00956   {
00957     return HAL_BUSY;
00958   }
00959 }
00960
00961 /**
00962   * @brief Receive an amount of data in DMA mode.
00963   * @param huart: UART handle.
00964   * @param pData: pointer to data buffer.
00965   * @param Size: amount of data to be received.
00966   * @note   When the UART parity is enabled (PCE = 1), the received data contain
00967   *         the parity bit (MSB position).
00968   * @retval HAL status
00969   */
00970 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00971 {
00972   /* Check that a Rx process is not already ongoing */
00973   if(huart->RxState == HAL_UART_STATE_READY)
00974   {
00975     if((pData == NULL ) || (Size == 0U))
00976     {
00977       return HAL_ERROR;
00978     }
00979
00980     /* Process Locked */
00981     __HAL_LOCK(huart);
00982
00983     huart->pRxBuffPtr = pData;
00984     huart->RxXferSize = Size;
00985
00986     huart->ErrorCode = HAL_UART_ERROR_NONE;
00987     huart->RxState = HAL_UART_STATE_BUSY_RX;
00988
00989     /* Set the UART DMA transfer complete callback */
00990     huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
00991
00992     /* Set the UART DMA Half transfer complete callback */
00993     huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
00994
00995     /* Set the DMA error callback */
00996     huart->hdmarx->XferErrorCallback = UART_DMAError;
00997
00998     /* Set the DMA abort callback */
00999     huart->hdmarx->XferAbortCallback = NULL;
01000
01001     /* Enable the DMA channel */
01002     HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size);
01003
01004     /* Process Unlocked */
01005     __HAL_UNLOCK(huart);
01006
01007     /* Enable the UART Parity Error Interrupt */
01008     SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01009
01010     /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
01011     SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
01012
01013     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01014        in the UART CR3 register */
01015     SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01016
01017     return HAL_OK;
01018   }
01019   else
01020   {
01021     return HAL_BUSY;
01022   }
01023 }
01024
01025 /**
01026   * @brief Pause the DMA Transfer.
01027   * @param huart: UART handle.
01028   * @retval HAL status
01029   */
01030 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
01031 {
01032   /* Process Locked */
01033   __HAL_LOCK(huart);
01034
01035   if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
01036       (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
01037   {
01038     /* Disable the UART DMA Tx request */
01039     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01040   }
01041   if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
01042       (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
01043   {
01044     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01045     CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01046     CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
01047
01048     /* Disable the UART DMA Rx request */
01049     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01050   }
01051
01052   /* Process Unlocked */
01053   __HAL_UNLOCK(huart);
01054
01055   return HAL_OK;
01056 }
01057
01058 /**
01059   * @brief Resume the DMA Transfer.
01060   * @param huart: UART handle.
01061   * @retval HAL status
01062   */
01063 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
01064 {
01065   /* Process Locked */
01066   __HAL_LOCK(huart);
01067
01068   if(huart->gState == HAL_UART_STATE_BUSY_TX)
01069   {
01070     /* Enable the UART DMA Tx request */
01071     SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01072   }
01073   if(huart->RxState == HAL_UART_STATE_BUSY_RX)
01074   {
01075     /* Clear the Overrun flag before resuming the Rx transfer */
01076     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
01077
01078     /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
01079     SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01080     SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
01081
01082     /* Enable the UART DMA Rx request */
01083     SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01084   }
01085
01086   /* Process Unlocked */
01087   __HAL_UNLOCK(huart);
01088
01089   return HAL_OK;
01090 }
01091
01092 /**
01093   * @brief Stop the DMA Transfer.
01094   * @param huart: UART handle.
01095   * @retval HAL status
01096   */
01097 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
01098 {
01099   /* The Lock is not implemented on this API to allow the user application
01100      to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
01101      HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
01102      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
01103      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
01104      the stream and the corresponding call back is executed. */
01105
01106   /* Stop UART DMA Tx request if ongoing */
01107   if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
01108       (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
01109   {
01110     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01111
01112     /* Abort the UART DMA Tx channel */
01113     if(huart->hdmatx != NULL)
01114     {
01115       HAL_DMA_Abort(huart->hdmatx);
01116     }
01117
01118     UART_EndTxTransfer(huart);
01119   }
01120
01121   /* Stop UART DMA Rx request if ongoing */
01122   if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
01123       (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
01124   {
01125     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01126
01127     /* Abort the UART DMA Rx channel */
01128     if(huart->hdmarx != NULL)
01129     {
01130       HAL_DMA_Abort(huart->hdmarx);
01131     }
01132
01133     UART_EndRxTransfer(huart);
01134   }
01135
01136   return HAL_OK;
01137 }
01138
01139 /**
01140   * @brief  Abort ongoing transfers (blocking mode).
01141   * @param  huart UART handle.
01142   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01143   *         This procedure performs following operations :
01144   *           - Disable UART Interrupts (Tx and Rx)
01145   *           - Disable the DMA transfer in the peripheral register (if enabled)
01146   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01147   *           - Set handle State to READY
01148   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01149   * @retval HAL status
01150 */
01151 HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
01152 {
01153   /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
01154   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
01155   CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
01156
01157   /* Disable the UART DMA Tx request if enabled */
01158   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01159   {
01160     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01161
01162     /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
01163     if(huart->hdmatx != NULL)
01164     {
01165       /* Set the UART DMA Abort callback to Null.
01166          No call back execution at end of DMA abort procedure */
01167       huart->hdmatx->XferAbortCallback = NULL;
01168
01169       HAL_DMA_Abort(huart->hdmatx);
01170     }
01171   }
01172
01173   /* Disable the UART DMA Rx request if enabled */
01174   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01175   {
01176     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01177
01178     /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
01179     if(huart->hdmarx != NULL)
01180     {
01181       /* Set the UART DMA Abort callback to Null.
01182          No call back execution at end of DMA abort procedure */
01183       huart->hdmarx->XferAbortCallback = NULL;
01184
01185       HAL_DMA_Abort(huart->hdmarx);
01186     }
01187   }
01188
01189   /* Reset Tx and Rx transfer counters */
01190   huart->TxXferCount = 0U;
01191   huart->RxXferCount = 0U;
01192
01193   /* Clear the Error flags in the ICR register */
01194   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
01195
01196   /* Restore huart->gState and huart->RxState to Ready */
01197   huart->gState  = HAL_UART_STATE_READY;
01198   huart->RxState = HAL_UART_STATE_READY;
01199
01200   /* Reset Handle ErrorCode to No Error */
01201   huart->ErrorCode = HAL_UART_ERROR_NONE;
01202
01203   return HAL_OK;
01204 }
01205
01206 /**
01207   * @brief  Abort ongoing Transmit transfer (blocking mode).
01208   * @param  huart UART handle.
01209   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01210   *         This procedure performs following operations :
01211   *           - Disable UART Interrupts (Tx)
01212   *           - Disable the DMA transfer in the peripheral register (if enabled)
01213   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01214   *           - Set handle State to READY
01215   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01216   * @retval HAL status
01217 */
01218 HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
01219 {
01220   /* Disable TCIE, TXEIE and TXFTIE interrupts */
01221   CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE | USART_CR1_TXEIE);
01222   CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
01223
01224   /* Disable the UART DMA Tx request if enabled */
01225   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01226   {
01227     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01228
01229     /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
01230     if(huart->hdmatx != NULL)
01231     {
01232       /* Set the UART DMA Abort callback to Null.
01233          No call back execution at end of DMA abort procedure */
01234       huart->hdmatx->XferAbortCallback = NULL;
01235
01236       HAL_DMA_Abort(huart->hdmatx);
01237     }
01238   }
01239
01240   /* Reset Tx transfer counter */
01241   huart->TxXferCount = 0U;
01242
01243   /* Restore huart->gState to Ready */
01244   huart->gState = HAL_UART_STATE_READY;
01245
01246   return HAL_OK;
01247 }
01248
01249 /**
01250   * @brief  Abort ongoing Receive transfer (blocking mode).
01251   * @param  huart UART handle.
01252   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01253   *         This procedure performs following operations :
01254   *           - Disable UART Interrupts (Rx)
01255   *           - Disable the DMA transfer in the peripheral register (if enabled)
01256   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01257   *           - Set handle State to READY
01258   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01259   * @retval HAL status
01260 */
01261 HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
01262 {
01263   /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupt */
01264   CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
01265   CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
01266
01267   /* Disable the UART DMA Rx request if enabled */
01268   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01269   {
01270     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01271
01272     /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
01273     if(huart->hdmarx != NULL)
01274     {
01275       /* Set the UART DMA Abort callback to Null.
01276          No call back execution at end of DMA abort procedure */
01277       huart->hdmarx->XferAbortCallback = NULL;
01278
01279       HAL_DMA_Abort(huart->hdmarx);
01280     }
01281   }
01282
01283   /* Reset Rx transfer counter */
01284   huart->RxXferCount = 0U;
01285
01286   /* Clear the Error flags in the ICR register */
01287   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
01288
01289   /* Restore huart->RxState to Ready */
01290   huart->RxState = HAL_UART_STATE_READY;
01291
01292   return HAL_OK;
01293 }
01294
01295 /**
01296   * @brief  Abort ongoing transfers (Interrupt mode).
01297   * @param  huart UART handle.
01298   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01299   *         This procedure performs following operations :
01300   *           - Disable UART Interrupts (Tx and Rx)
01301   *           - Disable the DMA transfer in the peripheral register (if enabled)
01302   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01303   *           - Set handle State to READY
01304   *           - At abort completion, call user abort complete callback
01305   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01306   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01307   * @retval HAL status
01308 */
01309 HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
01310 {
01311   uint32_t abortcplt = 1U;
01312
01313   /* Disable interrupts */
01314   CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE);
01315   CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
01316
01317   /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
01318      before any call to DMA Abort functions */
01319   /* DMA Tx Handle is valid */
01320   if(huart->hdmatx != NULL)
01321   {
01322     /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
01323        Otherwise, set it to NULL */
01324     if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01325     {
01326       huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
01327     }
01328     else
01329     {
01330       huart->hdmatx->XferAbortCallback = NULL;
01331     }
01332   }
01333   /* DMA Rx Handle is valid */
01334   if(huart->hdmarx != NULL)
01335   {
01336     /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
01337        Otherwise, set it to NULL */
01338     if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01339     {
01340       huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
01341     }
01342     else
01343     {
01344       huart->hdmarx->XferAbortCallback = NULL;
01345     }
01346   }
01347
01348   /* Disable the UART DMA Tx request if enabled */
01349   if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01350   {
01351     /* Disable DMA Tx at UART level */
01352     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01353
01354     /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
01355     if(huart->hdmatx != NULL)
01356     {
01357       /* UART Tx DMA Abort callback has already been initialised :
01358          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
01359
01360       /* Abort DMA TX */
01361       if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
01362       {
01363         huart->hdmatx->XferAbortCallback = NULL;
01364       }
01365       else
01366       {
01367         abortcplt = 0U;
01368       }
01369     }
01370   }
01371
01372   /* Disable the UART DMA Rx request if enabled */
01373   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01374   {
01375     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01376
01377     /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
01378     if(huart->hdmarx != NULL)
01379     {
01380       /* UART Rx DMA Abort callback has already been initialised :
01381          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
01382
01383       /* Abort DMA RX */
01384       if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
01385       {
01386         huart->hdmarx->XferAbortCallback = NULL;
01387         abortcplt = 1U;
01388       }
01389       else
01390       {
01391         abortcplt = 0U;
01392       }
01393     }
01394   }
01395
01396   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01397   if (abortcplt == 1U)
01398   {
01399     /* Reset Tx and Rx transfer counters */
01400     huart->TxXferCount = 0U;
01401     huart->RxXferCount = 0U;
01402
01403     /* Reset errorCode */
01404     huart->ErrorCode = HAL_UART_ERROR_NONE;
01405
01406     /* Clear the Error flags in the ICR register */
01407     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
01408
01409     /* Restore huart->gState and huart->RxState to Ready */
01410     huart->gState  = HAL_UART_STATE_READY;
01411     huart->RxState = HAL_UART_STATE_READY;
01412
01413     /* As no DMA to be aborted, call directly user Abort complete callback */
01414     HAL_UART_AbortCpltCallback(huart);
01415   }
01416
01417   return HAL_OK;
01418 }
01419
01420 /**
01421   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
01422   * @param  huart UART handle.
01423   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01424   *         This procedure performs following operations :
01425   *           - Disable UART Interrupts (Tx)
01426   *           - Disable the DMA transfer in the peripheral register (if enabled)
01427   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01428   *           - Set handle State to READY
01429   *           - At abort completion, call user abort complete callback
01430   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01431   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01432   * @retval HAL status
01433 */
01434 HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
01435 {
01436   /* Disable interrupts */
01437   CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE | USART_CR1_TXEIE);
01438   CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
01439
01440   /* Disable the UART DMA Tx request if enabled */
01441   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01442   {
01443     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01444
01445     /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
01446     if(huart->hdmatx != NULL)
01447     {
01448       /* Set the UART DMA Abort callback :
01449          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
01450       huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
01451
01452       /* Abort DMA TX */
01453       if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
01454       {
01455         /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
01456         huart->hdmatx->XferAbortCallback(huart->hdmatx);
01457       }
01458     }
01459     else
01460     {
01461       /* Reset Tx transfer counter */
01462       huart->TxXferCount = 0U;
01463
01464       /* Restore huart->gState to Ready */
01465       huart->gState = HAL_UART_STATE_READY;
01466
01467       /* As no DMA to be aborted, call directly user Abort complete callback */
01468       HAL_UART_AbortTransmitCpltCallback(huart);
01469     }
01470   }
01471   else
01472   {
01473     /* Reset Tx transfer counter */
01474     huart->TxXferCount = 0U;
01475
01476     /* Restore huart->gState to Ready */
01477     huart->gState = HAL_UART_STATE_READY;
01478
01479     /* As no DMA to be aborted, call directly user Abort complete callback */
01480     HAL_UART_AbortTransmitCpltCallback(huart);
01481   }
01482
01483   return HAL_OK;
01484 }
01485
01486 /**
01487   * @brief  Abort ongoing Receive transfer (Interrupt mode).
01488   * @param  huart UART handle.
01489   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01490   *         This procedure performs following operations :
01491   *           - Disable UART Interrupts (Rx)
01492   *           - Disable the DMA transfer in the peripheral register (if enabled)
01493   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01494   *           - Set handle State to READY
01495   *           - At abort completion, call user abort complete callback
01496   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01497   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01498   * @retval HAL status
01499 */
01500 HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
01501 {
01502   /* Disable ERR (Frame error, noise error, overrun error) interrupt */
01503   CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
01504   CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
01505
01506   /* Disable the UART DMA Rx request if enabled */
01507   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01508   {
01509     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01510
01511     /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
01512     if(huart->hdmarx != NULL)
01513     {
01514       /* Set the UART DMA Abort callback :
01515          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
01516       huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
01517
01518       /* Abort DMA RX */
01519       if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
01520       {
01521         /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
01522         huart->hdmarx->XferAbortCallback(huart->hdmarx);
01523       }
01524     }
01525     else
01526     {
01527       /* Reset Rx transfer counter */
01528       huart->RxXferCount = 0U;
01529
01530       /* Clear the Error flags in the ICR register */
01531       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
01532
01533       /* Restore huart->RxState to Ready */
01534       huart->RxState = HAL_UART_STATE_READY;
01535
01536       /* As no DMA to be aborted, call directly user Abort complete callback */
01537       HAL_UART_AbortReceiveCpltCallback(huart);
01538     }
01539   }
01540   else
01541   {
01542     /* Reset Rx transfer counter */
01543     huart->RxXferCount = 0U;
01544
01545     /* Clear the Error flags in the ICR register */
01546     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
01547
01548     /* Restore huart->RxState to Ready */
01549     huart->RxState = HAL_UART_STATE_READY;
01550
01551     /* As no DMA to be aborted, call directly user Abort complete callback */
01552     HAL_UART_AbortReceiveCpltCallback(huart);
01553   }
01554
01555   return HAL_OK;
01556 }
01557
01558 /**
01559   * @brief Handle UART interrupt request.
01560   * @param huart: UART handle.
01561   * @retval None
01562   */
01563 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
01564 {
01565   uint32_t isrflags   = READ_REG(huart->Instance->ISR);
01566   uint32_t cr1its     = READ_REG(huart->Instance->CR1);
01567   uint32_t cr3its     = READ_REG(huart->Instance->CR3);
01568   uint32_t errorflags;
01569
01570   /* If no error occurs */
01571   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
01572   if (errorflags == RESET)
01573   {
01574     /* UART in mode Receiver ---------------------------------------------------*/
01575     if(((isrflags & USART_ISR_RXNE) != RESET)
01576      && (   ((cr1its & USART_CR1_RXNEIE) != RESET)
01577          || ((cr3its & USART_CR3_RXFTIE) != RESET)) )
01578     {
01579       UART_Receive_IT(huart);
01580       return;
01581     }
01582   }
01583
01584   /* If some errors occur */
01585   if(   (errorflags != RESET)
01586      && (   ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET)
01587          || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
01588   {
01589     /* UART parity error interrupt occurred -------------------------------------*/
01590     if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
01591     {
01592       __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
01593
01594       huart->ErrorCode |= HAL_UART_ERROR_PE;
01595     }
01596
01597     /* UART frame error interrupt occurred --------------------------------------*/
01598     if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01599     {
01600       __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
01601
01602       huart->ErrorCode |= HAL_UART_ERROR_FE;
01603     }
01604
01605     /* UART noise error interrupt occurred --------------------------------------*/
01606     if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01607     {
01608       __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
01609
01610       huart->ErrorCode |= HAL_UART_ERROR_NE;
01611     }
01612
01613     /* UART Over-Run interrupt occurred -----------------------------------------*/
01614     if(   ((isrflags & USART_ISR_ORE) != RESET)
01615         &&(  ((cr1its & USART_CR1_RXNEIE) != RESET) ||
01616              ((cr3its & USART_CR3_RXFTIE) != RESET) ||
01617              ((cr3its & USART_CR3_EIE) != RESET)) )
01618     {
01619       __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
01620
01621       huart->ErrorCode |= HAL_UART_ERROR_ORE;
01622     }
01623
01624     /* Call UART Error Call back function if need be --------------------------*/
01625     if(huart->ErrorCode != HAL_UART_ERROR_NONE)
01626     {
01627       /* UART in mode Receiver ---------------------------------------------------*/
01628       if(((isrflags & USART_ISR_RXNE) != RESET)
01629          && (   ((cr1its & USART_CR1_RXNEIE) != RESET)
01630              || ((cr3its & USART_CR3_RXFTIE) != RESET)) )
01631       {
01632         UART_Receive_IT(huart);
01633       }
01634
01635       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
01636          consider error as blocking */
01637       if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) ||
01638           (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
01639       {
01640         /* Blocking error : transfer is aborted
01641            Set the UART state ready to be able to start again the process,
01642            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
01643         UART_EndRxTransfer(huart);
01644
01645         /* Disable the UART DMA Rx request if enabled */
01646         if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01647         {
01648           CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01649
01650           /* Abort the UART DMA Rx channel */
01651           if(huart->hdmarx != NULL)
01652           {
01653             /* Set the UART DMA Abort callback :
01654                will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
01655             huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
01656
01657             /* Abort DMA RX */
01658             if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
01659             {
01660               /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
01661               huart->hdmarx->XferAbortCallback(huart->hdmarx);
01662             }
01663           }
01664           else
01665           {
01666             /* Call user error callback */
01667             HAL_UART_ErrorCallback(huart);
01668           }
01669         }
01670         else
01671         {
01672           /* Call user error callback */
01673           HAL_UART_ErrorCallback(huart);
01674         }
01675       }
01676       else
01677       {
01678         /* Non Blocking error : transfer could go on.
01679            Error is notified to user through user error callback */
01680         HAL_UART_ErrorCallback(huart);
01681         huart->ErrorCode = HAL_UART_ERROR_NONE;
01682       }
01683     }
01684     return;
01685
01686   } /* End if some error occurs */
01687
01688   /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
01689   if(((isrflags & USART_ISR_WUF) != RESET) && ((cr3its & USART_CR3_WUFIE) != RESET))
01690   {
01691     __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF);
01692     /* Set the UART state ready to be able to start again the process */
01693     huart->gState  = HAL_UART_STATE_READY;
01694     huart->RxState = HAL_UART_STATE_READY;
01695     HAL_UARTEx_WakeupCallback(huart);
01696     return;
01697   }
01698
01699   /* UART in mode Transmitter ------------------------------------------------*/
01700   if(((isrflags & USART_ISR_TXE) != RESET)
01701      && (   ((cr1its & USART_CR1_TXEIE) != RESET)
01702          || ((cr3its & USART_CR3_TXFTIE) != RESET)) )
01703   {
01704     UART_Transmit_IT(huart);
01705     return;
01706   }
01707
01708   /* UART in mode Transmitter (transmission end) -----------------------------*/
01709   if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
01710   {
01711     UART_EndTransmit_IT(huart);
01712     return;
01713   }
01714
01715   /* UART TX FIFO Empty  -----------------------------------------------------*/
01716   if(((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET))
01717   {
01718     CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXFEIE);
01719   }
01720 }
01721
01722 /**
01723   * @brief Tx Transfer completed callback.
01724   * @param huart: UART handle.
01725   * @retval None
01726   */
01727 __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
01728 {
01729   /* Prevent unused argument(s) compilation warning */
01730   UNUSED(huart);
01731
01732   /* NOTE : This function should not be modified, when the callback is needed,
01733             the HAL_UART_TxCpltCallback can be implemented in the user file.
01734    */
01735 }
01736
01737 /**
01738   * @brief  Tx Half Transfer completed callback.
01739   * @param  huart: UART handle.
01740   * @retval None
01741   */
01742 __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
01743 {
01744   /* Prevent unused argument(s) compilation warning */
01745   UNUSED(huart);
01746
01747   /* NOTE: This function should not be modified, when the callback is needed,
01748            the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
01749    */
01750 }
01751
01752 /**
01753   * @brief Rx Transfer completed callback.
01754   * @param huart: UART handle.
01755   * @retval None
01756   */
01757 __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
01758 {
01759   /* Prevent unused argument(s) compilation warning */
01760   UNUSED(huart);
01761
01762   /* NOTE : This function should not be modified, when the callback is needed,
01763             the HAL_UART_RxCpltCallback can be implemented in the user file.
01764    */
01765 }
01766
01767 /**
01768   * @brief  Rx Half Transfer completed callback.
01769   * @param  huart: UART handle.
01770   * @retval None
01771   */
01772 __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
01773 {
01774   /* Prevent unused argument(s) compilation warning */
01775   UNUSED(huart);
01776
01777   /* NOTE: This function should not be modified, when the callback is needed,
01778            the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
01779    */
01780 }
01781
01782 /**
01783   * @brief UART error callback.
01784   * @param huart: UART handle.
01785   * @retval None
01786   */
01787 __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
01788 {
01789   /* Prevent unused argument(s) compilation warning */
01790   UNUSED(huart);
01791
01792   /* NOTE : This function should not be modified, when the callback is needed,
01793             the HAL_UART_ErrorCallback can be implemented in the user file.
01794    */
01795 }
01796
01797 /**
01798   * @brief  UART Abort Complete callback.
01799   * @param  huart UART handle.
01800   * @retval None
01801   */
01802 __weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
01803 {
01804   /* Prevent unused argument(s) compilation warning */
01805   UNUSED(huart);
01806
01807   /* NOTE : This function should not be modified, when the callback is needed,
01808             the HAL_UART_AbortCpltCallback can be implemented in the user file.
01809    */
01810 }
01811
01812 /**
01813   * @brief  UART Abort Complete callback.
01814   * @param  huart UART handle.
01815   * @retval None
01816   */
01817 __weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
01818 {
01819   /* Prevent unused argument(s) compilation warning */
01820   UNUSED(huart);
01821
01822   /* NOTE : This function should not be modified, when the callback is needed,
01823             the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
01824    */
01825 }
01826
01827 /**
01828   * @brief  UART Abort Receive Complete callback.
01829   * @param  huart UART handle.
01830   * @retval None
01831   */
01832 __weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
01833 {
01834   /* Prevent unused argument(s) compilation warning */
01835   UNUSED(huart);
01836
01837   /* NOTE : This function should not be modified, when the callback is needed,
01838             the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
01839    */
01840 }
01841
01842 /**
01843   * @}
01844   */
01845
01846 /** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
01847   *  @brief   UART control functions
01848   *
01849 @verbatim
01850  ===============================================================================
01851                       ##### Peripheral Control functions #####
01852  ===============================================================================
01853     [..]
01854     This subsection provides a set of functions allowing to control the UART.
01855      (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
01856      (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
01857      (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
01858      (+) UART_SetConfig() API configures the UART peripheral
01859      (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
01860      (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
01861      (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
01862      (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
01863      (+) HAL_LIN_SendBreak() API transmits the break characters
01864 @endverbatim
01865   * @{
01866   */
01867
01868 /**
01869   * @brief Enable UART in mute mode (does not mean UART enters mute mode;
01870   * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
01871   * @param huart: UART handle.
01872   * @retval HAL status
01873   */
01874 HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
01875 {
01876   /* Process Locked */
01877   __HAL_LOCK(huart);
01878
01879   huart->gState = HAL_UART_STATE_BUSY;
01880
01881   /* Enable USART mute mode by setting the MME bit in the CR1 register */
01882   SET_BIT(huart->Instance->CR1, USART_CR1_MME);
01883
01884   huart->gState = HAL_UART_STATE_READY;
01885
01886   return (UART_CheckIdleState(huart));
01887 }
01888
01889 /**
01890   * @brief  Disable UART mute mode (does not mean the UART actually exits mute mode
01891   *         as it may not have been in mute mode at this very moment).
01892   * @param  huart: UART handle.
01893   * @retval HAL status
01894   */
01895 HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
01896 {
01897   /* Process Locked */
01898   __HAL_LOCK(huart);
01899
01900   huart->gState = HAL_UART_STATE_BUSY;
01901
01902    /* Disable USART mute mode by clearing the MME bit in the CR1 register */
01903   CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
01904
01905   huart->gState = HAL_UART_STATE_READY;
01906
01907   return (UART_CheckIdleState(huart));
01908 }
01909
01910 /**
01911   * @brief Enter UART mute mode (means UART actually enters mute mode).
01912   * @note  To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
01913   * @param huart: UART handle.
01914   * @retval None
01915   */
01916 void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
01917 {
01918   __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
01919 }
01920
01921 /**
01922   * @brief  Enable the UART transmitter and disable the UART receiver.
01923   * @param  huart: UART handle.
01924   * @retval HAL status
01925   */
01926 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
01927 {
01928   /* Process Locked */
01929   __HAL_LOCK(huart);
01930   huart->gState = HAL_UART_STATE_BUSY;
01931
01932   /* Clear TE and RE bits */
01933   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
01934   /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
01935   SET_BIT(huart->Instance->CR1, USART_CR1_TE);
01936
01937   huart->gState = HAL_UART_STATE_READY;
01938
01939   /* Process Unlocked */
01940   __HAL_UNLOCK(huart);
01941
01942   return HAL_OK;
01943 }
01944
01945 /**
01946   * @brief  Enable the UART receiver and disable the UART transmitter.
01947   * @param  huart: UART handle.
01948   * @retval HAL status.
01949   */
01950 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
01951 {
01952   /* Process Locked */
01953   __HAL_LOCK(huart);
01954   huart->gState = HAL_UART_STATE_BUSY;
01955
01956   /* Clear TE and RE bits */
01957   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
01958   /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
01959   SET_BIT(huart->Instance->CR1, USART_CR1_RE);
01960
01961   huart->gState = HAL_UART_STATE_READY;
01962   /* Process Unlocked */
01963   __HAL_UNLOCK(huart);
01964
01965   return HAL_OK;
01966 }
01967
01968
01969 /**
01970   * @brief  Transmit break characters.
01971   * @param  huart: UART handle.
01972   * @retval HAL status
01973   */
01974 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
01975 {
01976   /* Check the parameters */
01977   assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
01978
01979   /* Process Locked */
01980   __HAL_LOCK(huart);
01981
01982   huart->gState = HAL_UART_STATE_BUSY;
01983
01984   /* Send break characters */
01985   SET_BIT(huart->Instance->RQR, UART_SENDBREAK_REQUEST);
01986
01987   huart->gState = HAL_UART_STATE_READY;
01988
01989   /* Process Unlocked */
01990   __HAL_UNLOCK(huart);
01991
01992   return HAL_OK;
01993 }
01994
01995
01996 /**
01997   * @}
01998   */
01999
02000 /** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
02001  *  @brief   UART Peripheral State functions
02002  *
02003 @verbatim
02004   ==============================================================================
02005             ##### Peripheral State and Error functions #####
02006   ==============================================================================
02007     [..]
02008     This subsection provides functions allowing to :
02009       (+) Return the UART handle state.
02010       (+) Return the UART handle error code
02011
02012 @endverbatim
02013   * @{
02014   */
02015
02016 /**
02017   * @brief  Return the UART handle state.
02018   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02019   *               the configuration information for the specified UART.
02020   * @retval HAL state
02021   */
02022 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
02023 {
02024   uint32_t temp1= 0x00U, temp2 = 0x00U;
02025   temp1 = huart->gState;
02026   temp2 = huart->RxState;
02027
02028   return (HAL_UART_StateTypeDef)(temp1 | temp2);
02029 }
02030
02031 /**
02032   * @brief  Return the UART handle error code.
02033   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02034   *               the configuration information for the specified UART.
02035   * @retval UART Error Code
02036 */
02037 uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
02038 {
02039   return huart->ErrorCode;
02040 }
02041 /**
02042   * @}
02043   */
02044
02045 /**
02046   * @}
02047   */
02048
02049 /** @defgroup UART_Private_Functions UART Private Functions
02050   * @{
02051   */
02052
02053 /**
02054   * @brief Configure the UART peripheral.
02055   * @param huart: UART handle.
02056   * @retval HAL status
02057   */
02058 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
02059 {
02060   uint32_t tmpreg                     = 0x00000000U;
02061   UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
02062   uint16_t brrtemp                    = 0x0000U;
02063   uint16_t usartdiv                   = 0x0000U;
02064   HAL_StatusTypeDef ret               = HAL_OK;
02065   PLL2_ClocksTypeDef pll2_clocks;
02066   PLL3_ClocksTypeDef pll3_clocks;
02067   /* Check the parameters */
02068   assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
02069   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
02070   if(UART_INSTANCE_LOWPOWER(huart))
02071   {
02072     assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));
02073   }
02074   else
02075   {
02076     assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
02077     assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
02078   }
02079
02080   assert_param(IS_UART_PARITY(huart->Init.Parity));
02081   assert_param(IS_UART_MODE(huart->Init.Mode));
02082   assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
02083   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
02084   assert_param(IS_UART_PRESCALER(huart->Init.Prescaler));
02085   assert_param(IS_UART_FIFO_MODE_STATE(huart->Init.FIFOMode));
02086   if (huart->Init.FIFOMode == UART_FIFOMODE_ENABLE)
02087   {
02088     assert_param(IS_UART_TXFIFO_THRESHOLD(huart->Init.TXFIFOThreshold));
02089     assert_param(IS_UART_RXFIFO_THRESHOLD(huart->Init.RXFIFOThreshold));
02090   }
02091
02092   /*-------------------------- USART CR1 Configuration -----------------------*/
02093   /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
02094    *  the UART Word Length, Parity, Mode and oversampling:
02095    *  set the M bits according to huart->Init.WordLength value
02096    *  set PCE and PS bits according to huart->Init.Parity value
02097    *  set TE and RE bits according to huart->Init.Mode value
02098    *  set OVER8 bit according to huart->Init.OverSampling value */
02099   tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
02100   tmpreg |=  (uint32_t)huart->Init.FIFOMode;
02101   MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
02102
02103   /*-------------------------- USART CR2 Configuration -----------------------*/
02104   /* Configure the UART Stop Bits: Set STOP[13:12] bits according
02105    * to huart->Init.StopBits value */
02106   MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
02107
02108   /*-------------------------- USART CR3 Configuration -----------------------*/
02109   /* Configure
02110    * - UART HardWare Flow Control: set CTSE and RTSE bits according
02111    *   to huart->Init.HwFlowCtl value
02112    * - one-bit sampling method versus three samples' majority rule according
02113    *   to huart->Init.OneBitSampling (not applicable to LPUART)
02114    * - set TXFTCFG bit according to husart->Init.TXFIFOThreshold value
02115    * - set RXFTCFG bit according to husart->Init.RXFIFOThreshold value */
02116   tmpreg = (uint32_t)huart->Init.HwFlowCtl;
02117
02118   if (!(UART_INSTANCE_LOWPOWER(huart)))
02119   {
02120     tmpreg |= huart->Init.OneBitSampling;
02121   }
02122
02123   if (huart->Init.FIFOMode == UART_FIFOMODE_ENABLE)
02124   {
02125     tmpreg |= ((uint32_t)huart->Init.TXFIFOThreshold | (uint32_t)huart->Init.RXFIFOThreshold);
02126   }
02127
02128   MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
02129
02130 /*-------------------------- USART PRESC Configuration -----------------------*/
02131   /* Configure
02132    * - UART Clock Prescaler : set PRESCALER according to huart->Init.Prescaler value */
02133   MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.Prescaler);
02134
02135   /*-------------------------- USART BRR Configuration -----------------------*/
02136   UART_GETCLOCKSOURCE(huart, clocksource);
02137
02138   /* Check LPUART instance */
02139   if(UART_INSTANCE_LOWPOWER(huart))
02140   {
02141     /* Retrieve frequency clock */
02142     tmpreg = 0U;
02143
02144     switch (clocksource)
02145     {
02146     case UART_CLOCKSOURCE_D3PCLK1:
02147       tmpreg = HAL_RCCEx_GetD3PCLK1Freq();
02148       break;
02149     case UART_CLOCKSOURCE_PLL2:
02150       HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02151       tmpreg = pll2_clocks.PLL2_Q_Frequency;
02152       break;
02153     case UART_CLOCKSOURCE_PLL3:
02154       HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
02155       tmpreg = pll3_clocks.PLL3_Q_Frequency;
02156       break;
02157     case UART_CLOCKSOURCE_HSI:
02158       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
02159       {
02160         tmpreg = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
02161       }
02162       else
02163       {
02164         tmpreg = (uint32_t) HSI_VALUE;
02165       }
02166       break;
02167     case UART_CLOCKSOURCE_CSI:
02168       tmpreg =(uint32_t) CSI_VALUE;
02169       break;
02170     case UART_CLOCKSOURCE_LSE:
02171       tmpreg = (uint32_t) LSE_VALUE;
02172       break;
02173     case UART_CLOCKSOURCE_UNDEFINED:
02174     default:
02175         ret = HAL_ERROR;
02176       break;
02177     }
02178
02179     /* if proper clock source reported */
02180     if (tmpreg != 0U)
02181     {
02182       /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
02183       if ( (tmpreg < (3 * huart->Init.BaudRate) ) ||
02184            (tmpreg > (4096 * huart->Init.BaudRate) ))
02185       {
02186         ret = HAL_ERROR;
02187       }
02188       else
02189       {
02190         switch (clocksource)
02191         {
02192         case UART_CLOCKSOURCE_D3PCLK1:
02193           tmpreg = (uint32_t)(UART_DIV_LPUART(HAL_RCCEx_GetD3PCLK1Freq(), huart->Init.BaudRate, huart->Init.Prescaler));
02194           break;
02195         case UART_CLOCKSOURCE_PLL2:
02196           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02197           tmpreg = (uint32_t)(UART_DIV_LPUART(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.Prescaler));
02198           break;
02199         case UART_CLOCKSOURCE_PLL3:
02200           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
02201           tmpreg = (uint32_t)(UART_DIV_LPUART(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.Prescaler));
02202           break;
02203         case UART_CLOCKSOURCE_HSI:
02204           if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
02205           {
02206             tmpreg = (uint32_t)(UART_DIV_LPUART((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)), huart->Init.BaudRate, huart->Init.Prescaler));
02207           }
02208           else
02209           {
02210             tmpreg = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.Prescaler));
02211           }
02212           break;
02213         case UART_CLOCKSOURCE_CSI:
02214           tmpreg = (uint32_t)(UART_DIV_LPUART(CSI_VALUE, huart->Init.BaudRate, huart->Init.Prescaler));
02215           break;
02216         case UART_CLOCKSOURCE_LSE:
02217           tmpreg = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.Prescaler));
02218           break;
02219         case UART_CLOCKSOURCE_UNDEFINED:
02220         default:
02221           ret = HAL_ERROR;
02222           break;
02223         }
02224
02225         if ((tmpreg >= UART_LPUART_BRR_MIN) && (tmpreg <= UART_LPUART_BRR_MAX))
02226         {
02227            huart->Instance->BRR = tmpreg;
02228         }
02229         else
02230         {
02231           ret = HAL_ERROR;
02232         }
02233       }  /*   if ( (tmpreg < (3 * huart->Init.BaudRate) ) || (tmpreg > (4096 * huart->Init.BaudRate) )) */
02234     } /* if (tmpreg != 0) */
02235   }
02236   /* Check UART Over Sampling to set Baud Rate Register */
02237   else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
02238   {
02239     switch (clocksource)
02240     {
02241     case UART_CLOCKSOURCE_D2PCLK1:
02242         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.Prescaler));
02243       break;
02244     case UART_CLOCKSOURCE_D2PCLK2:
02245         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.Prescaler));
02246       break;
02247     case UART_CLOCKSOURCE_PLL2:
02248         HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02249         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.Prescaler));
02250       break;
02251     case UART_CLOCKSOURCE_PLL3:
02252         HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
02253         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.Prescaler));
02254       break;
02255     case UART_CLOCKSOURCE_HSI:
02256       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
02257       {
02258         usartdiv = (uint16_t)(UART_DIV_SAMPLING8((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)), huart->Init.BaudRate, huart->Init.Prescaler));
02259       }
02260       else
02261       {
02262         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.Prescaler));
02263       }
02264       break;
02265     case UART_CLOCKSOURCE_CSI:
02266         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(CSI_VALUE, huart->Init.BaudRate, huart->Init.Prescaler));
02267       break;
02268     case UART_CLOCKSOURCE_LSE:
02269         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate, huart->Init.Prescaler));
02270       break;
02271     case UART_CLOCKSOURCE_UNDEFINED:
02272     default:
02273         ret = HAL_ERROR;
02274       break;
02275     }
02276
02277     brrtemp = usartdiv & 0xFFF0U;
02278     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
02279     huart->Instance->BRR = brrtemp;
02280   }
02281   else
02282   {
02283     switch (clocksource)
02284     {
02285     case UART_CLOCKSOURCE_D2PCLK1:
02286         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.Prescaler));
02287       break;
02288     case UART_CLOCKSOURCE_D2PCLK2:
02289         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.Prescaler));
02290       break;
02291     case UART_CLOCKSOURCE_PLL2:
02292         HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02293         huart->Instance->BRR =  (uint16_t)(UART_DIV_SAMPLING16(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.Prescaler));
02294       break;
02295     case UART_CLOCKSOURCE_PLL3:
02296         HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
02297         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.Prescaler));
02298       break;
02299     case UART_CLOCKSOURCE_HSI:
02300       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
02301       {
02302         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)), huart->Init.BaudRate, huart->Init.Prescaler));
02303       }
02304       else
02305       {
02306         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.Prescaler));
02307       }
02308       break;
02309     case UART_CLOCKSOURCE_CSI:
02310         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(CSI_VALUE, huart->Init.BaudRate, huart->Init.Prescaler));
02311       break;
02312     case UART_CLOCKSOURCE_LSE:
02313         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate, huart->Init.Prescaler));
02314       break;
02315     case UART_CLOCKSOURCE_UNDEFINED:
02316     default:
02317         ret = HAL_ERROR;
02318       break;
02319     }
02320   }
02321
02322   return ret;
02323 }
02324
02325 /**
02326   * @brief Configure the UART peripheral advanced features.
02327   * @param huart: UART handle.
02328   * @retval None
02329   */
02330 void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
02331 {
02332   /* Check whether the set of advanced features to configure is properly set */
02333   assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
02334
02335   /* if required, configure TX pin active level inversion */
02336   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
02337   {
02338     assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
02339     MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
02340   }
02341
02342   /* if required, configure RX pin active level inversion */
02343   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
02344   {
02345     assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
02346     MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
02347   }
02348
02349   /* if required, configure data inversion */
02350   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
02351   {
02352     assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
02353     MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
02354   }
02355
02356   /* if required, configure RX/TX pins swap */
02357   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
02358   {
02359     assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
02360     MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
02361   }
02362
02363   /* if required, configure RX overrun detection disabling */
02364   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
02365   {
02366     assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
02367     MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
02368   }
02369
02370   /* if required, configure DMA disabling on reception error */
02371   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
02372   {
02373     assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
02374     MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
02375   }
02376
02377   /* if required, configure auto Baud rate detection scheme */
02378   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
02379   {
02380     assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
02381     assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
02382     MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
02383     /* set auto Baudrate detection parameters if detection is enabled */
02384     if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
02385     {
02386       assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
02387       MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
02388     }
02389   }
02390
02391   /* if required, configure MSB first on communication line */
02392   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
02393   {
02394     assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
02395     MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
02396   }
02397 }
02398
02399 /**
02400   * @brief Check the UART Idle State.
02401   * @param huart: UART handle.
02402   * @retval HAL status
02403   */
02404 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
02405 {
02406   uint32_t tickstart = 0U;
02407
02408   /* Initialize the UART ErrorCode */
02409   huart->ErrorCode = HAL_UART_ERROR_NONE;
02410
02411   /* Init tickstart for timeout managment*/
02412   tickstart = HAL_GetTick();
02413
02414   /* Check if the Transmitter is enabled */
02415   if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
02416   {
02417     /* Wait until TEACK flag is set */
02418     if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
02419     {
02420       /* Timeout occurred */
02421       return HAL_TIMEOUT;
02422     }
02423   }
02424   /* Check if the Receiver is enabled */
02425   if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
02426   {
02427     /* Wait until REACK flag is set */
02428     if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
02429     {
02430       /* Timeout occurred */
02431       return HAL_TIMEOUT;
02432     }
02433   }
02434
02435   /* Initialize the UART State */
02436   huart->gState = HAL_UART_STATE_READY;
02437   huart->RxState = HAL_UART_STATE_READY;
02438
02439   /* Process Unlocked */
02440   __HAL_UNLOCK(huart);
02441
02442   return HAL_OK;
02443 }
02444
02445 /**
02446   * @brief  Handle UART Communication Timeout.
02447   * @param  huart: UART handle.
02448   * @param  Flag Specifies the UART flag to check
02449   * @param  Status Flag status (SET or RESET)
02450   * @param  Tickstart Tick start value
02451   * @param  Timeout Timeout duration
02452   * @retval HAL status
02453   */
02454 HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
02455 {
02456   /* Wait until flag is set */
02457   while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
02458   {
02459     /* Check for the Timeout */
02460     if(Timeout != HAL_MAX_DELAY)
02461     {
02462       if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
02463       {
02464         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
02465         CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
02466         CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
02467
02468         huart->gState = HAL_UART_STATE_READY;
02469         huart->RxState = HAL_UART_STATE_READY;
02470
02471         /* Process Unlocked */
02472         __HAL_UNLOCK(huart);
02473
02474         return HAL_TIMEOUT;
02475       }
02476     }
02477   }
02478   return HAL_OK;
02479 }
02480
02481
02482 /**
02483   * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
02484   * @param  huart: UART handle.
02485   * @retval None
02486   */
02487 static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
02488 {
02489   /* Disable TXEIE and TCIE interrupts */
02490   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
02491
02492   /* At end of Tx process, restore huart->gState to Ready */
02493   huart->gState = HAL_UART_STATE_READY;
02494 }
02495
02496
02497 /**
02498   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
02499   * @param  huart: UART handle.
02500   * @retval None
02501   */
02502 static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
02503 {
02504   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
02505   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
02506   CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
02507
02508   /* At end of Rx process, restore huart->RxState to Ready */
02509   huart->RxState = HAL_UART_STATE_READY;
02510 }
02511
02512
02513 /**
02514   * @brief DMA UART transmit process complete callback.
02515   * @param hdma: DMA handle.
02516   * @retval None
02517   */
02518 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
02519 {
02520   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
02521
02522   /* DMA Normal mode */
02523   if (hdma->Init.Mode != DMA_CIRCULAR)
02524   {
02525     huart->TxXferCount = 0U;
02526
02527     /* Disable the DMA transfer for transmit request by resetting the DMAT bit
02528        in the UART CR3 register */
02529     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
02530
02531     /* Enable the UART Transmit Complete Interrupt */
02532     SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
02533   }
02534   /* DMA Circular mode */
02535   else
02536   {
02537     HAL_UART_TxCpltCallback(huart);
02538   }
02539
02540 }
02541
02542 /**
02543   * @brief DMA UART transmit process half complete callback.
02544   * @param hdma : DMA handle.
02545   * @retval None
02546   */
02547 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
02548 {
02549   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
02550
02551   HAL_UART_TxHalfCpltCallback(huart);
02552 }
02553
02554 /**
02555   * @brief DMA UART receive process complete callback.
02556   * @param hdma: DMA handle.
02557   * @retval None
02558   */
02559 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
02560 {
02561   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
02562
02563   /* DMA Normal mode */
02564   if (hdma->Init.Mode != DMA_CIRCULAR)
02565   {
02566     huart->RxXferCount = 0U;
02567
02568     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
02569     CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
02570     CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
02571
02572     /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
02573        in the UART CR3 register */
02574     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
02575
02576     /* At end of Rx process, restore huart->RxState to Ready */
02577     huart->RxState = HAL_UART_STATE_READY;
02578   }
02579
02580   HAL_UART_RxCpltCallback(huart);
02581 }
02582
02583 /**
02584   * @brief DMA UART receive process half complete callback.
02585   * @param hdma : DMA handle.
02586   * @retval None
02587   */
02588 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
02589 {
02590   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
02591
02592   HAL_UART_RxHalfCpltCallback(huart);
02593 }
02594
02595 /**
02596   * @brief DMA UART communication error callback.
02597   * @param hdma: DMA handle.
02598   * @retval None
02599   */
02600 static void UART_DMAError(DMA_HandleTypeDef *hdma)
02601 {
02602   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
02603
02604   /* if DMA error is FIFO error ignore it */
02605   if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
02606   {
02607     /* Stop UART DMA Tx request if ongoing */
02608     if (  (huart->gState == HAL_UART_STATE_BUSY_TX)
02609         &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) )
02610     {
02611       huart->TxXferCount = 0U;
02612       UART_EndTxTransfer(huart);
02613     }
02614
02615     /* Stop UART DMA Rx request if ongoing */
02616     if (  (huart->RxState == HAL_UART_STATE_BUSY_RX)
02617         &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) )
02618     {
02619       huart->RxXferCount = 0U;
02620       UART_EndRxTransfer(huart);
02621     }
02622
02623     huart->ErrorCode |= HAL_UART_ERROR_DMA;
02624     HAL_UART_ErrorCallback(huart);
02625   }
02626 }
02627
02628 /**
02629   * @brief DMA UART communication abort callback
02630   *        (To be called at end of DMA Abort procedure).
02631   * @param hdma: DMA handle.
02632   * @retval None
02633   */
02634 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02635 {
02636   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
02637   huart->RxXferCount = 0U;
02638   huart->TxXferCount = 0U;
02639
02640   HAL_UART_ErrorCallback(huart);
02641 }
02642
02643 /**
02644   * @brief  DMA UART Tx communication abort callback, when initiated by user
02645   *         (To be called at end of DMA Tx Abort procedure following user abort request).
02646   * @note   When this callback is executed, User Abort complete call back is called only if no
02647   *         Abort still ongoing for Rx DMA Handle.
02648   * @param  hdma DMA handle.
02649   * @retval None
02650   */
02651 static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
02652 {
02653   UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent);
02654
02655   huart->hdmatx->XferAbortCallback = NULL;
02656
02657   /* Check if an Abort process is still ongoing */
02658   if(huart->hdmarx != NULL)
02659   {
02660     if(huart->hdmarx->XferAbortCallback != NULL)
02661     {
02662       return;
02663     }
02664   }
02665
02666   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02667   huart->TxXferCount = 0U;
02668   huart->RxXferCount = 0U;
02669
02670   /* Reset errorCode */
02671   huart->ErrorCode = HAL_UART_ERROR_NONE;
02672
02673   /* Clear the Error flags in the ICR register */
02674   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
02675
02676   /* Restore huart->gState and huart->RxState to Ready */
02677   huart->gState  = HAL_UART_STATE_READY;
02678   huart->RxState = HAL_UART_STATE_READY;
02679
02680   /* Call user Abort complete callback */
02681   HAL_UART_AbortCpltCallback(huart);
02682 }
02683
02684
02685 /**
02686   * @brief  DMA UART Rx communication abort callback, when initiated by user
02687   *         (To be called at end of DMA Rx Abort procedure following user abort request).
02688   * @note   When this callback is executed, User Abort complete call back is called only if no
02689   *         Abort still ongoing for Tx DMA Handle.
02690   * @param  hdma DMA handle.
02691   * @retval None
02692   */
02693 static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
02694 {
02695   UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent);
02696
02697   huart->hdmarx->XferAbortCallback = NULL;
02698
02699   /* Check if an Abort process is still ongoing */
02700   if(huart->hdmatx != NULL)
02701   {
02702     if(huart->hdmatx->XferAbortCallback != NULL)
02703     {
02704       return;
02705     }
02706   }
02707
02708   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02709   huart->TxXferCount = 0U;
02710   huart->RxXferCount = 0U;
02711
02712   /* Reset errorCode */
02713   huart->ErrorCode = HAL_UART_ERROR_NONE;
02714
02715   /* Clear the Error flags in the ICR register */
02716   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
02717
02718   /* Restore huart->gState and huart->RxState to Ready */
02719   huart->gState  = HAL_UART_STATE_READY;
02720   huart->RxState = HAL_UART_STATE_READY;
02721
02722   /* Call user Abort complete callback */
02723   HAL_UART_AbortCpltCallback(huart);
02724 }
02725
02726
02727 /**
02728   * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to
02729   *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
02730   *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
02731   *         and leads to user Tx Abort Complete callback execution).
02732   * @param  hdma DMA handle.
02733   * @retval None
02734   */
02735 static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02736 {
02737   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
02738
02739   huart->TxXferCount = 0U;
02740
02741   /* Restore huart->gState to Ready */
02742   huart->gState = HAL_UART_STATE_READY;
02743
02744   /* Call user Abort complete callback */
02745   HAL_UART_AbortTransmitCpltCallback(huart);
02746 }
02747
02748 /**
02749   * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to
02750   *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
02751   *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
02752   *         and leads to user Rx Abort Complete callback execution).
02753   * @param  hdma DMA handle.
02754   * @retval None
02755   */
02756 static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02757 {
02758   UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02759
02760   huart->RxXferCount = 0U;
02761
02762   /* Clear the Error flags in the ICR register */
02763   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
02764
02765   /* Restore huart->RxState to Ready */
02766   huart->RxState = HAL_UART_STATE_READY;
02767
02768   /* Call user Abort complete callback */
02769   HAL_UART_AbortReceiveCpltCallback(huart);
02770 }
02771
02772 /**
02773   * @brief  Send an amount of data in interrupt mode.
02774   * @note   Function is called under interruption only, once
02775   *         interruptions have been enabled by HAL_UART_Transmit_IT().
02776   * @param  huart: UART handle.
02777   * @retval HAL status
02778   */
02779 static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
02780 {
02781   uint16_t* tmp;
02782
02783   /* Check that a Tx process is ongoing */
02784   if (huart->gState == HAL_UART_STATE_BUSY_TX)
02785   {
02786     if(huart->TxXferCount == 0U)
02787     {
02788       /* Disable the TX FIFO threshold interrupt (if FIFO mode is enabled) or
02789          Transmit Data Register Empty interrupt (if FIFO mode is Disabled).
02790       */
02791       if (READ_BIT(huart->Instance->CR1, USART_CR1_FIFOEN) != RESET)
02792       {
02793         CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
02794       }
02795       else
02796       {
02797         CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
02798       }
02799
02800       /* Enable the UART Transmit Complete Interrupt */
02801       SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
02802
02803       return HAL_OK;
02804     }
02805     else
02806     {
02807       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
02808       {
02809         tmp = (uint16_t*) huart->pTxBuffPtr;
02810         huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
02811         huart->pTxBuffPtr += 2U;
02812       }
02813       else
02814       {
02815         huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU);
02816       }
02817       huart->TxXferCount--;
02818
02819       return HAL_OK;
02820     }
02821   }
02822   else
02823   {
02824     return HAL_BUSY;
02825   }
02826 }
02827
02828 /**
02829   * @brief  Wrap up transmission in non-blocking mode.
02830   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
02831   *                the configuration information for the specified UART module.
02832   * @retval HAL status
02833   */
02834 static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
02835 {
02836   /* Disable the UART Transmit Complete Interrupt */
02837   CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
02838
02839   /* Tx process is ended, restore huart->gState to Ready */
02840   huart->gState = HAL_UART_STATE_READY;
02841
02842   HAL_UART_TxCpltCallback(huart);
02843
02844   return HAL_OK;
02845 }
02846
02847
02848 /**
02849   * @brief  Receive an amount of data in interrupt mode.
02850   * @note   Function is called under interruption only, once
02851   *         interruptions have been enabled by HAL_UART_Receive_IT()
02852   * @param  huart: UART handle.
02853   * @retval HAL status
02854   */
02855 static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
02856 {
02857   uint16_t* tmp;
02858   uint16_t  uhMask = huart->Mask;
02859   uint16_t  uhdata;
02860
02861   /* Check that a Rx process is ongoing */
02862   if(huart->RxState == HAL_UART_STATE_BUSY_RX)
02863   {
02864     uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
02865     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
02866     {
02867       tmp = (uint16_t*) huart->pRxBuffPtr ;
02868       *tmp = (uint16_t)(uhdata & uhMask);
02869       huart->pRxBuffPtr +=2;
02870     }
02871     else
02872     {
02873       *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
02874     }
02875
02876     if(--huart->RxXferCount == 0U)
02877     {
02878       /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
02879       CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
02880
02881       /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
02882       CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
02883
02884       /* Rx process is completed, restore huart->RxState to Ready */
02885       huart->RxState = HAL_UART_STATE_READY;
02886
02887       HAL_UART_RxCpltCallback(huart);
02888
02889       return HAL_OK;
02890     }
02891
02892     return HAL_OK;
02893   }
02894   else
02895   {
02896     /* Clear RXNE interrupt flag */
02897     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
02898
02899     return HAL_BUSY;
02900   }
02901 }
02902
02903 /**
02904   * @}
02905   */
02906
02907 #endif /* HAL_UART_MODULE_ENABLED */
02908 /**
02909   * @}
02910   */
02911
02912 /**
02913   * @}
02914   */
02915
02916 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_uart.h Source File

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stm32h7xx_hal_uart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_uart.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of UART HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_UART_H
00040 #define __STM32H7xx_HAL_UART_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup UART
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup UART_Exported_Types UART Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief UART Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
00068                                            The baud rate register is computed using the following formula:
00069                                            - If oversampling is 16 or in LIN mode,
00070                                               Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
00071                                            - If oversampling is 8,
00072                                               Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]
00073                                               Baud Rate Register[3] =  0
00074                                               Baud Rate Register[2:0] =  (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1      */
00075
00076   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00077                                            This parameter can be a value of @ref UARTEx_Word_Length. */
00078
00079   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00080                                            This parameter can be a value of @ref UART_Stop_Bits. */
00081
00082   uint32_t Parity;                    /*!< Specifies the parity mode.
00083                                            This parameter can be a value of @ref UART_Parity
00084                                            @note When parity is enabled, the computed parity is inserted
00085                                                  at the MSB position of the transmitted data (9th bit when
00086                                                  the word length is set to 9 data bits; 8th bit when the
00087                                                  word length is set to 8 data bits). */
00088
00089   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00090                                            This parameter can be a value of @ref UART_Mode. */
00091
00092   uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled
00093                                            or disabled.
00094                                            This parameter can be a value of @ref UART_Hardware_Flow_Control. */
00095
00096   uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).
00097                                            This parameter can be a value of @ref UART_Over_Sampling. */
00098
00099   uint32_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.
00100                                            Selecting the single sample method increases the receiver tolerance to clock
00101                                            deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
00102
00103   uint32_t Prescaler;                 /*!< Specifies the prescaler value used to divide the UART clock source.
00104                                            This parameter can be a value of @ref UART_Prescaler. */
00105
00106   uint32_t FIFOMode;                  /*!< Specifies if the FIFO mode will be used. This parameter can be a value
00107                                            of @ref UART_FIFO_mode. */
00108
00109   uint32_t TXFIFOThreshold;           /*!< Specifies the TXFIFO threshold level.
00110                                            This parameter can be a value of @ref UART_TXFIFO_threshold_level. */
00111
00112   uint32_t RXFIFOThreshold;           /*!< Specifies the RXFIFO threshold level.
00113                                            This parameter can be a value of @ref UART_RXFIFO_threshold_level. */
00114
00115 }UART_InitTypeDef;
00116
00117 /**
00118   * @brief  UART Advanced Features initalization structure definition
00119   */
00120 typedef struct
00121 {
00122   uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several
00123                                        Advanced Features may be initialized at the same time .
00124                                        This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
00125
00126   uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.
00127                                        This parameter can be a value of @ref UART_Tx_Inv.  */
00128
00129   uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.
00130                                        This parameter can be a value of @ref UART_Rx_Inv.  */
00131
00132   uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic
00133                                        vs negative/inverted logic).
00134                                        This parameter can be a value of @ref UART_Data_Inv. */
00135
00136   uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.
00137                                        This parameter can be a value of @ref UART_Rx_Tx_Swap. */
00138
00139   uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.
00140                                        This parameter can be a value of @ref UART_Overrun_Disable. */
00141
00142   uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.
00143                                        This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
00144
00145   uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.
00146                                        This parameter can be a value of @ref UART_AutoBaudRate_Enable */
00147
00148   uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate
00149                                        detection is carried out.
00150                                        This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
00151
00152   uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.
00153                                        This parameter can be a value of @ref UART_MSB_First. */
00154 } UART_AdvFeatureInitTypeDef;
00155
00156
00157
00158 /**
00159   * @brief HAL UART State structures definition
00160   * @note  HAL UART State value is a combination of 2 different substates: gState and RxState.
00161   *        - gState contains UART state information related to global Handle management
00162   *          and also information related to Tx operations.
00163   *          gState value coding follow below described bitmap :
00164   *          b7-b6  Error information
00165   *             00 : No Error
00166   *             01 : (Not Used)
00167   *             10 : Timeout
00168   *             11 : Error
00169   *          b5     IP initilisation status
00170   *             0  : Reset (IP not initialized)
00171   *             1  : Init done (IP not initialized. HAL UART Init function already called)
00172   *          b4-b3  (not used)
00173   *             xx : Should be set to 00
00174   *          b2     Intrinsic process state
00175   *             0  : Ready
00176   *             1  : Busy (IP busy with some configuration or internal operations)
00177   *          b1     (not used)
00178   *             x  : Should be set to 0
00179   *          b0     Tx state
00180   *             0  : Ready (no Tx operation ongoing)
00181   *             1  : Busy (Tx operation ongoing)
00182   *        - RxState contains information related to Rx operations.
00183   *          RxState value coding follow below described bitmap :
00184   *          b7-b6  (not used)
00185   *             xx : Should be set to 00
00186   *          b5     IP initilisation status
00187   *             0  : Reset (IP not initialized)
00188   *             1  : Init done (IP not initialized)
00189   *          b4-b2  (not used)
00190   *            xxx : Should be set to 000
00191   *          b1     Rx state
00192   *             0  : Ready (no Rx operation ongoing)
00193   *             1  : Busy (Rx operation ongoing)
00194   *          b0     (not used)
00195   *             x  : Should be set to 0.
00196   */
00197 typedef enum
00198 {
00199   HAL_UART_STATE_RESET             = 0x00U,   /*!< Peripheral is not initialized
00200                                                    Value is allowed for gState and RxState */
00201   HAL_UART_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use
00202                                                    Value is allowed for gState and RxState */
00203   HAL_UART_STATE_BUSY              = 0x24U,   /*!< an internal process is ongoing
00204                                                    Value is allowed for gState only */
00205   HAL_UART_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing
00206                                                    Value is allowed for gState only */
00207   HAL_UART_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing
00208                                                    Value is allowed for RxState only */
00209   HAL_UART_STATE_BUSY_TX_RX        = 0x23U,   /*!< Data Transmission and Reception process is ongoing
00210                                                    Not to be used for neither gState nor RxState.
00211                                                    Value is result of combination (Or) between gState and RxState values */
00212   HAL_UART_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state
00213                                                    Value is allowed for gState only */
00214   HAL_UART_STATE_ERROR             = 0xE0U    /*!< Error
00215                                                    Value is allowed for gState only */
00216 }HAL_UART_StateTypeDef;
00217
00218 /**
00219   * @brief  HAL UART Error Code structure definition
00220   */
00221 typedef enum
00222 {
00223   HAL_UART_ERROR_NONE      = 0x00U,    /*!< No error            */
00224   HAL_UART_ERROR_PE        = 0x01U,    /*!< Parity error        */
00225   HAL_UART_ERROR_NE        = 0x02U,    /*!< Noise error         */
00226   HAL_UART_ERROR_FE        = 0x04U,    /*!< frame error         */
00227   HAL_UART_ERROR_ORE       = 0x08U,    /*!< Overrun error       */
00228   HAL_UART_ERROR_DMA       = 0x10U     /*!< DMA transfer error  */
00229 }HAL_UART_ErrorTypeDef;
00230
00231 /**
00232   * @brief UART clock sources definition
00233   */
00234 typedef enum
00235 {
00236   UART_CLOCKSOURCE_D2PCLK1    = 0x00U,    /*!< Domain2 PCLK1 clock source */
00237   UART_CLOCKSOURCE_D2PCLK2    = 0x01U,    /*!< Domain2 PCLK2 clock source */
00238   UART_CLOCKSOURCE_D3PCLK1    = 0x02U,    /*!< Domain3 PCLK1 clock source */
00239   UART_CLOCKSOURCE_PLL2       = 0x04U,    /*!< PLL2Q clock source         */
00240   UART_CLOCKSOURCE_HSI        = 0x08U,    /*!< HSI clock source           */
00241   UART_CLOCKSOURCE_CSI        = 0x10U,    /*!< CSI clock source           */
00242   UART_CLOCKSOURCE_LSE        = 0x20U,    /*!< LSE clock source           */
00243   UART_CLOCKSOURCE_PLL3       = 0x40U,    /*!< PLL3Q clock source         */
00244   UART_CLOCKSOURCE_UNDEFINED  = 0x80U     /*!< Undefined clock source     */
00245 }UART_ClockSourceTypeDef;
00246
00247 /**
00248   * @brief  UART handle Structure definition
00249   */
00250 typedef struct
00251 {
00252   USART_TypeDef            *Instance;        /*!< UART registers base address        */
00253
00254   UART_InitTypeDef         Init;             /*!< UART communication parameters      */
00255
00256   UART_AdvFeatureInitTypeDef AdvancedInit;   /*!< UART Advanced Features initialization parameters */
00257
00258   uint8_t                  *pTxBuffPtr;      /*!< Pointer to UART Tx transfer Buffer */
00259
00260   uint16_t                 TxXferSize;       /*!< UART Tx Transfer size              */
00261
00262   __IO uint16_t            TxXferCount;      /*!< UART Tx Transfer Counter           */
00263
00264   uint8_t                  *pRxBuffPtr;      /*!< Pointer to UART Rx transfer Buffer */
00265
00266   uint16_t                 RxXferSize;       /*!< UART Rx Transfer size              */
00267
00268   __IO uint16_t            RxXferCount;      /*!< UART Rx Transfer Counter           */
00269
00270   uint16_t                 Mask;             /*!< UART Rx RDR register mask          */
00271
00272   DMA_HandleTypeDef        *hdmatx;          /*!< UART Tx DMA Handle parameters      */
00273
00274   DMA_HandleTypeDef        *hdmarx;          /*!< UART Rx DMA Handle parameters      */
00275
00276   HAL_LockTypeDef           Lock;            /*!< Locking object                     */
00277
00278   __IO HAL_UART_StateTypeDef    gState;      /*!< UART state information related to global Handle management
00279                                                   and also related to Tx operations.
00280                                                   This parameter can be a value of @ref HAL_UART_StateTypeDef */
00281
00282   __IO HAL_UART_StateTypeDef    RxState;     /*!< UART state information related to Rx operations.
00283                                                   This parameter can be a value of @ref HAL_UART_StateTypeDef */
00284
00285   __IO uint32_t             ErrorCode;       /*!< UART Error code                    */
00286
00287 }UART_HandleTypeDef;
00288
00289 /**
00290   * @}
00291   */
00292
00293 /* Exported constants --------------------------------------------------------*/
00294 /** @defgroup UART_Exported_Constants UART Exported Constants
00295   * @{
00296   */
00297
00298 /** @defgroup UART_Stop_Bits   UART Number of Stop Bits
00299   * @{
00300   */
00301 #define UART_STOPBITS_0_5                    USART_CR2_STOP_0                     /*!< UART frame with 0.5 stop bit  */
00302 #define UART_STOPBITS_1                     ((uint32_t)0x00000000U)               /*!< UART frame with 1 stop bit    */
00303 #define UART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
00304 #define UART_STOPBITS_2                      USART_CR2_STOP_1                     /*!< UART frame with 2 stop bits   */
00305 /**
00306   * @}
00307   */
00308
00309 /** @defgroup UART_Parity  UART Parity
00310   * @{
00311   */
00312 #define UART_PARITY_NONE                    ((uint32_t)0x00000000U)                        /*!< No parity   */
00313 #define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)                      /*!< Even parity */
00314 #define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))     /*!< Odd parity  */
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
00320   * @{
00321   */
00322 #define UART_HWCONTROL_NONE                  ((uint32_t)0x00000000U)                          /*!< No hardware control       */
00323 #define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)                       /*!< Request To Send           */
00324 #define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)                       /*!< Clear To Send             */
00325 #define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))    /*!< Request and Clear To Send */
00326 /**
00327   * @}
00328   */
00329
00330 /** @defgroup UART_Mode UART Transfer Mode
00331   * @{
00332   */
00333 #define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)                    /*!< RX mode        */
00334 #define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)                    /*!< TX mode        */
00335 #define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))    /*!< RX and TX mode */
00336 /**
00337   * @}
00338   */
00339
00340 /** @defgroup UART_State  UART State
00341   * @{
00342   */
00343 #define UART_STATE_DISABLE                  ((uint32_t)0x00000000U)         /*!< UART disabled  */
00344 #define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)        /*!< UART enabled   */
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup UART_Over_Sampling UART Over Sampling
00350   * @{
00351   */
00352 #define UART_OVERSAMPLING_16                ((uint32_t)0x00000000U)         /*!< Oversampling by 16 */
00353 #define UART_OVERSAMPLING_8                 ((uint32_t)USART_CR1_OVER8)     /*!< Oversampling by 8  */
00354 /**
00355   * @}
00356   */
00357
00358 /** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
00359   * @{
00360   */
00361 #define UART_ONE_BIT_SAMPLE_DISABLE         ((uint32_t)0x00000000U)         /*!< One-bit sampling disable */
00362 #define UART_ONE_BIT_SAMPLE_ENABLE          ((uint32_t)USART_CR3_ONEBIT)    /*!< One-bit sampling enable  */
00363 /**
00364   * @}
00365   */
00366
00367 /** @defgroup UART_Prescaler  UART Prescaler
00368   * @{
00369   */
00370 #define UART_PRESCALER_DIV1    ((uint32_t)0x00000000U)  /*!< UART clock /1   */
00371 #define UART_PRESCALER_DIV2    ((uint32_t)0x00000001U)  /*!< UART clock /2   */
00372 #define UART_PRESCALER_DIV4    ((uint32_t)0x00000002U)  /*!< UART clock /4   */
00373 #define UART_PRESCALER_DIV6    ((uint32_t)0x00000003U)  /*!< UART clock /6   */
00374 #define UART_PRESCALER_DIV8    ((uint32_t)0x00000004U)  /*!< UART clock /8   */
00375 #define UART_PRESCALER_DIV10   ((uint32_t)0x00000005U)  /*!< UART clock /10  */
00376 #define UART_PRESCALER_DIV12   ((uint32_t)0x00000006U)  /*!< UART clock /12  */
00377 #define UART_PRESCALER_DIV16   ((uint32_t)0x00000007U)  /*!< UART clock /16  */
00378 #define UART_PRESCALER_DIV32   ((uint32_t)0x00000008U)  /*!< UART clock /32  */
00379 #define UART_PRESCALER_DIV64   ((uint32_t)0x00000009U)  /*!< UART clock /64  */
00380 #define UART_PRESCALER_DIV128  ((uint32_t)0x0000000AU)  /*!< UART clock /128 */
00381 #define UART_PRESCALER_DIV256  ((uint32_t)0x0000000BU)  /*!< UART clock /256 */
00382
00383 /**
00384   * @}
00385   */
00386
00387 /** @defgroup UART_FIFO_mode UART FIFO mode
00388   * @brief    UART FIFO  mode
00389   * @{
00390   */
00391 #define UART_FIFOMODE_DISABLE        ((uint32_t)0x00000000U)       /*!< FIFO mode disable */
00392 #define UART_FIFOMODE_ENABLE         ((uint32_t)USART_CR1_FIFOEN)  /*!< FIFO mode enable  */
00393 /**
00394   * @}
00395   */
00396
00397 /** @defgroup UART_TXFIFO_threshold_level UART TXFIFO threshold level
00398   * @brief    UART TXFIFO level
00399   * @{
00400   */
00401 #define UART_TXFIFO_THRESHOLD_1_8    ((uint32_t)0x00000000U)                               /*!< TXFIFO reaches 1/8 of its depth */
00402 #define UART_TXFIFO_THRESHOLD_1_4    ((uint32_t)USART_CR3_TXFTCFG_0)                       /*!< TXFIFO reaches 1/4 of its depth */
00403 #define UART_TXFIFO_THRESHOLD_1_2    ((uint32_t)USART_CR3_TXFTCFG_1)                       /*!< TXFIFO reaches 1/2 of its depth */
00404 #define UART_TXFIFO_THRESHOLD_3_4    ((uint32_t)(USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)) /*!< TXFIFO reaches 3/4 of its depth */
00405 #define UART_TXFIFO_THRESHOLD_7_8    ((uint32_t)USART_CR3_TXFTCFG_2)                       /*!< TXFIFO reaches 7/8 of its depth */
00406 #define UART_TXFIFO_THRESHOLD_8_8    ((uint32_t)(USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)) /*!< TXFIFO becomes empty            */
00407 /**
00408   * @}
00409   */
00410
00411 /** @defgroup UART_RXFIFO_threshold_level UART RXFIFO threshold level
00412   * @brief    UART RXFIFO level
00413   * @{
00414   */
00415 #define UART_RXFIFO_THRESHOLD_1_8    ((uint32_t)0x00000000U)                               /*!< RXFIFO reaches 1/8 of its depth */
00416 #define UART_RXFIFO_THRESHOLD_1_4    ((uint32_t)USART_CR3_RXFTCFG_0)                       /*!< RXFIFO reaches 1/4 of its depth */
00417 #define UART_RXFIFO_THRESHOLD_1_2    ((uint32_t)USART_CR3_RXFTCFG_1)                       /*!< RXFIFO reaches 1/2 of its depth */
00418 #define UART_RXFIFO_THRESHOLD_3_4    ((uint32_t)(USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)) /*!< RXFIFO reaches 3/4 of its depth */
00419 #define UART_RXFIFO_THRESHOLD_7_8    ((uint32_t)USART_CR3_RXFTCFG_2)                       /*!< RXFIFO reaches 7/8 of its depth */
00420 #define UART_RXFIFO_THRESHOLD_8_8    ((uint32_t)(USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)) /*!< RXFIFO becomes full             */
00421 /**
00422   * @}
00423   */
00424
00425 /** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode
00426   * @{
00427   */
00428 #define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    ((uint32_t)0x00000000U)           /*!< Auto Baud rate detection on start bit            */
00429 #define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)   /*!< Auto Baud rate detection on falling edge         */
00430 #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   ((uint32_t)USART_CR2_ABRMODE_1)   /*!< Auto Baud rate detection on 0x7F frame detection */
00431 #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   ((uint32_t)USART_CR2_ABRMODE)     /*!< Auto Baud rate detection on 0x55 frame detection */
00432 /**
00433   * @}
00434   */
00435
00436 /** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
00437   * @{
00438   */
00439 #define UART_RECEIVER_TIMEOUT_DISABLE       ((uint32_t)0x00000000U)                 /*!< UART receiver timeout disable */
00440 #define UART_RECEIVER_TIMEOUT_ENABLE        ((uint32_t)USART_CR2_RTOEN)             /*!< UART receiver timeout enable  */
00441 /**
00442   * @}
00443   */
00444
00445 /** @defgroup UART_LIN    UART Local Interconnection Network mode
00446   * @{
00447   */
00448 #define UART_LIN_DISABLE                    ((uint32_t)0x00000000U)                /*!< Local Interconnect Network disable */
00449 #define UART_LIN_ENABLE                     ((uint32_t)USART_CR2_LINEN)            /*!< Local Interconnect Network enable  */
00450 /**
00451   * @}
00452   */
00453
00454 /** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection
00455   * @{
00456   */
00457 #define UART_LINBREAKDETECTLENGTH_10B       ((uint32_t)0x00000000U)               /*!< LIN 10-bit break detection length */
00458 #define UART_LINBREAKDETECTLENGTH_11B       ((uint32_t)USART_CR2_LBDL)            /*!< LIN 11-bit break detection length  */
00459 /**
00460   * @}
00461   */
00462
00463 /** @defgroup UART_DMA_Tx    UART DMA Tx
00464   * @{
00465   */
00466 #define UART_DMA_TX_DISABLE                 ((uint32_t)0x00000000U)               /*!< UART DMA TX disabled */
00467 #define UART_DMA_TX_ENABLE                  ((uint32_t)USART_CR3_DMAT)            /*!< UART DMA TX enabled  */
00468 /**
00469   * @}
00470   */
00471
00472 /** @defgroup UART_DMA_Rx   UART DMA Rx
00473   * @{
00474   */
00475 #define UART_DMA_RX_DISABLE                 ((uint32_t)0x00000000U)                 /*!< UART DMA RX disabled */
00476 #define UART_DMA_RX_ENABLE                  ((uint32_t)USART_CR3_DMAR)              /*!< UART DMA RX enabled  */
00477 /**
00478   * @}
00479   */
00480
00481 /** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection
00482   * @{
00483   */
00484 #define UART_HALF_DUPLEX_DISABLE            ((uint32_t)0x00000000U)                 /*!< UART half-duplex disabled */
00485 #define UART_HALF_DUPLEX_ENABLE             ((uint32_t)USART_CR3_HDSEL)             /*!< UART half-duplex enabled  */
00486 /**
00487   * @}
00488   */
00489
00490 /** @defgroup UART_WakeUp_Methods   UART WakeUp Methods
00491   * @{
00492   */
00493 #define UART_WAKEUPMETHOD_IDLELINE          ((uint32_t)0x00000000U)                 /*!< UART wake-up on idle line    */
00494 #define UART_WAKEUPMETHOD_ADDRESSMARK       ((uint32_t)USART_CR1_WAKE)              /*!< UART wake-up on address mark */
00495 /**
00496   * @}
00497   */
00498
00499 /** @defgroup UART_Request_Parameters UART Request Parameters
00500   * @{
00501   */
00502 #define UART_AUTOBAUD_REQUEST               ((uint32_t)USART_RQR_ABRRQ)        /*!< Auto-Baud Rate Request      */
00503 #define UART_SENDBREAK_REQUEST              ((uint32_t)USART_RQR_SBKRQ)        /*!< Send Break Request          */
00504 #define UART_MUTE_MODE_REQUEST              ((uint32_t)USART_RQR_MMRQ)         /*!< Mute Mode Request           */
00505 #define UART_RXDATA_FLUSH_REQUEST           ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request  */
00506 #define UART_TXDATA_FLUSH_REQUEST           ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */
00507 /**
00508   * @}
00509   */
00510
00511 /** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type
00512   * @{
00513   */
00514 #define UART_ADVFEATURE_NO_INIT                 ((uint32_t)0x00000000U)        /*!< No advanced feature initialization       */
00515 #define UART_ADVFEATURE_TXINVERT_INIT           ((uint32_t)0x00000001U)        /*!< TX pin active level inversion            */
00516 #define UART_ADVFEATURE_RXINVERT_INIT           ((uint32_t)0x00000002U)        /*!< RX pin active level inversion            */
00517 #define UART_ADVFEATURE_DATAINVERT_INIT         ((uint32_t)0x00000004U)        /*!< Binary data inversion                    */
00518 #define UART_ADVFEATURE_SWAP_INIT               ((uint32_t)0x00000008U)        /*!< TX/RX pins swap                          */
00519 #define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   ((uint32_t)0x00000010U)        /*!< RX overrun disable                       */
00520 #define UART_ADVFEATURE_DMADISABLEONERROR_INIT  ((uint32_t)0x00000020U)        /*!< DMA disable on Reception Error           */
00521 #define UART_ADVFEATURE_AUTOBAUDRATE_INIT       ((uint32_t)0x00000040U)        /*!< Auto Baud rate detection initialization  */
00522 #define UART_ADVFEATURE_MSBFIRST_INIT           ((uint32_t)0x00000080U)        /*!< Most significant bit sent/received first */
00523 /**
00524   * @}
00525   */
00526
00527 /** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
00528   * @{
00529   */
00530 #define UART_ADVFEATURE_TXINV_DISABLE       ((uint32_t)0x00000000U)            /*!< TX pin active level inversion disable */
00531 #define UART_ADVFEATURE_TXINV_ENABLE        ((uint32_t)USART_CR2_TXINV)        /*!< TX pin active level inversion enable  */
00532 /**
00533   * @}
00534   */
00535
00536 /** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
00537   * @{
00538   */
00539 #define UART_ADVFEATURE_RXINV_DISABLE       ((uint32_t)0x00000000U)             /*!< RX pin active level inversion disable */
00540 #define UART_ADVFEATURE_RXINV_ENABLE        ((uint32_t)USART_CR2_RXINV)         /*!< RX pin active level inversion enable  */
00541 /**
00542   * @}
00543   */
00544
00545 /** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion
00546   * @{
00547   */
00548 #define UART_ADVFEATURE_DATAINV_DISABLE     ((uint32_t)0x00000000U)             /*!< Binary data inversion disable */
00549 #define UART_ADVFEATURE_DATAINV_ENABLE      ((uint32_t)USART_CR2_DATAINV)       /*!< Binary data inversion enable  */
00550 /**
00551   * @}
00552   */
00553
00554 /** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
00555   * @{
00556   */
00557 #define UART_ADVFEATURE_SWAP_DISABLE        ((uint32_t)0x00000000U)             /*!< TX/RX pins swap disable */
00558 #define UART_ADVFEATURE_SWAP_ENABLE         ((uint32_t)USART_CR2_SWAP)          /*!< TX/RX pins swap enable  */
00559 /**
00560   * @}
00561   */
00562
00563 /** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable
00564   * @{
00565   */
00566 #define UART_ADVFEATURE_OVERRUN_ENABLE      ((uint32_t)0x00000000U)             /*!< RX overrun enable  */
00567 #define UART_ADVFEATURE_OVERRUN_DISABLE     ((uint32_t)USART_CR3_OVRDIS)        /*!< RX overrun disable */
00568 /**
00569   * @}
00570   */
00571
00572 /** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable
00573   * @{
00574   */
00575 #define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   ((uint32_t)0x00000000U)          /*!< RX Auto Baud rate detection enable  */
00576 #define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    ((uint32_t)USART_CR2_ABREN)      /*!< RX Auto Baud rate detection disable */
00577 /**
00578   * @}
00579   */
00580
00581 /** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error
00582   * @{
00583   */
00584 #define UART_ADVFEATURE_DMA_ENABLEONRXERROR    ((uint32_t)0x00000000U)          /*!< DMA enable on Reception Error  */
00585 #define UART_ADVFEATURE_DMA_DISABLEONRXERROR   ((uint32_t)USART_CR3_DDRE)       /*!< DMA disable on Reception Error */
00586 /**
00587   * @}
00588   */
00589
00590 /** @defgroup UART_MSB_First   UART Advanced Feature MSB First
00591   * @{
00592   */
00593 #define UART_ADVFEATURE_MSBFIRST_DISABLE    ((uint32_t)0x00000000U)             /*!< Most significant bit sent/received first disable */
00594 #define UART_ADVFEATURE_MSBFIRST_ENABLE     ((uint32_t)USART_CR2_MSBFIRST)      /*!< Most significant bit sent/received first enable  */
00595 /**
00596   * @}
00597   */
00598
00599 /** @defgroup UART_Stop_Mode_Enable   UART Advanced Feature Stop Mode Enable
00600   * @{
00601   */
00602 #define UART_ADVFEATURE_STOPMODE_DISABLE    ((uint32_t)0x00000000U)             /*!< UART stop mode disable */
00603 #define UART_ADVFEATURE_STOPMODE_ENABLE     ((uint32_t)USART_CR1_UESM)          /*!< UART stop mode enable  */
00604 /**
00605   * @}
00606   */
00607
00608 /** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable
00609   * @{
00610   */
00611 #define UART_ADVFEATURE_MUTEMODE_DISABLE    ((uint32_t)0x00000000U)             /*!< UART mute mode disable */
00612 #define UART_ADVFEATURE_MUTEMODE_ENABLE     ((uint32_t)USART_CR1_MME)           /*!< UART mute mode enable  */
00613 /**
00614   * @}
00615   */
00616
00617 /** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register
00618   * @{
00619   */
00620 #define UART_CR2_ADDRESS_LSB_POS            ((uint32_t) 24U)                    /*!< UART address-matching LSB position in CR2 register */
00621 /**
00622   * @}
00623   */
00624
00625 /** @defgroup UART_WakeUp_from_Stop_Selection   UART WakeUp From Stop Selection
00626   * @{
00627   */
00628 #define UART_WAKEUP_ON_ADDRESS              ((uint32_t)0x00000000U)             /*!< UART wake-up on address                         */
00629 #define UART_WAKEUP_ON_STARTBIT             ((uint32_t)USART_CR3_WUS_1)         /*!< UART wake-up on start bit                       */
00630 #define UART_WAKEUP_ON_READDATA_NONEMPTY    ((uint32_t)USART_CR3_WUS)           /*!< UART wake-up on receive data register not empty */
00631 #define UART_WAKEUP_ON_RXFIFO_THRESHOLD     ((uint32_t)USART_CR3_RXFTIE)        /*!< UART wake-up when the RXFIFO reaches threshold  */
00632 #define UART_WAKEUP_ON_RXFIFO_FULL          ((uint32_t)USART_CR1_RXFFIE)        /*!< UART wake-up when the RXFIFO is full            */
00633 #define UART_WAKEUP_ON_TXFIFO_THRESHOLD     ((uint32_t)USART_CR3_TXFTIE)        /*!< UART wake-up when the TXFIFO reaches threshold  */
00634 #define UART_WAKEUP_ON_TXFIFO_EMPTY         ((uint32_t)USART_CR1_TXFEIE)        /*!< UART wake-up when the TXFIFO is  empty          */
00635 /**
00636   * @}
00637   */
00638
00639 /** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity
00640   * @{
00641   */
00642 #define UART_DE_POLARITY_HIGH               ((uint32_t)0x00000000U)             /*!< Driver enable signal is active high */
00643 #define UART_DE_POLARITY_LOW                ((uint32_t)USART_CR3_DEP)           /*!< Driver enable signal is active low  */
00644 /**
00645   * @}
00646   */
00647
00648 /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register
00649   * @{
00650   */
00651 #define UART_CR1_DEAT_ADDRESS_LSB_POS       ((uint32_t) 21U)                    /*!< UART Driver Enable assertion time LSB position in CR1 register */
00652 /**
00653   * @}
00654   */
00655
00656 /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register
00657   * @{
00658   */
00659 #define UART_CR1_DEDT_ADDRESS_LSB_POS       ((uint32_t) 16U)                    /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
00660 /**
00661   * @}
00662   */
00663
00664 /** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask
00665   * @{
00666   */
00667 #define UART_IT_MASK                        ((uint32_t)0x001FU)                 /*!< UART interruptions flags mask */
00668 /**
00669   * @}
00670   */
00671
00672 /** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value
00673   * @{
00674   */
00675 #define HAL_UART_TIMEOUT_VALUE              0x1FFFFFFU                          /*!< UART polling-based communications time-out value */
00676 /**
00677   * @}
00678   */
00679
00680 /** @defgroup UART_Flags     UART Status Flags
00681   *        Elements values convention: 0xXXXX
00682   *           - 0xXXXX  : Flag mask in the ISR register
00683   * @{
00684   */
00685 #define UART_FLAG_TXFT                      USART_ISR_TXFT   /*!< UART TXFIFO threshold flag                */
00686 #define UART_FLAG_RXFT                      USART_ISR_RXFT   /*!< UART RXFIFO threshold flag                */
00687 #define UART_FLAG_RXFF                      USART_ISR_RXFF   /*!< UART RXFIFO Full flag                     */
00688 #define UART_FLAG_TXFE                      USART_ISR_TXFE   /*!< UART TXFIFO Empty flag                    */
00689 #define UART_FLAG_REACK                     USART_ISR_REACK  /*!< UART receive enable acknowledge flag      */
00690 #define UART_FLAG_TEACK                     USART_ISR_TEACK  /*!< UART transmit enable acknowledge flag     */
00691 #define UART_FLAG_WUF                       USART_ISR_WUF    /*!< UART wake-up from stop mode flag          */
00692 #define UART_FLAG_RWU                       USART_ISR_RWU    /*!< UART receiver wake-up from mute mode flag */
00693 #define UART_FLAG_SBKF                      USART_ISR_SBKF   /*!< UART send break flag                      */
00694 #define UART_FLAG_CMF                       USART_ISR_CMF    /*!< UART character match flag                 */
00695 #define UART_FLAG_BUSY                      USART_ISR_BUSY   /*!< UART busy flag                            */
00696 #define UART_FLAG_ABRF                      USART_ISR_ABRF   /*!< UART auto Baud rate flag                  */
00697 #define UART_FLAG_ABRE                      USART_ISR_ABRE   /*!< UART uto Baud rate error                  */
00698 #define UART_FLAG_RTOF                      USART_ISR_RTOF   /*!< UART receiver timeout flag                */
00699 #define UART_FLAG_CTS                       USART_ISR_CTS    /*!< UART clear to send flag                   */
00700 #define UART_FLAG_CTSIF                     USART_ISR_CTSIF  /*!< UART clear to send interrupt flag         */
00701 #define UART_FLAG_LBDF                      USART_ISR_LBDF   /*!< UART LIN break detection flag             */
00702 #define UART_FLAG_TXE                       USART_ISR_TXE    /*!< UART transmit data register empty         */
00703 #define UART_FLAG_TXFNF                     USART_ISR_TXE    /*!< UART TXFIFO not full                      */
00704 #define UART_FLAG_TC                        USART_ISR_TC     /*!< UART transmission complete                */
00705 #define UART_FLAG_RXNE                      USART_ISR_RXNE   /*!< UART read data register not empty         */
00706 #define UART_FLAG_RXFNE                     USART_ISR_RXNE   /*!< UART RXFIFO not empty                     */
00707 #define UART_FLAG_IDLE                      USART_ISR_IDLE   /*!< UART idle flag                            */
00708 #define UART_FLAG_ORE                       USART_ISR_ORE    /*!< UART overrun error                        */
00709 #define UART_FLAG_NE                        USART_ISR_NE     /*!< UART noise error                          */
00710 #define UART_FLAG_FE                        USART_ISR_FE     /*!< UART frame error                          */
00711 #define UART_FLAG_PE                        USART_ISR_PE     /*!< UART parity error                         */
00712 /**
00713   * @}
00714   */
00715
00716 /** @defgroup UART_Interrupt_definition   UART Interrupts Definition
00717   *        Elements values convention: 000ZZZZZ0XXYYYYYb
00718   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00719   *           - XX  : Interrupt source register (2bits)
00720   *                 - 01: CR1 register
00721   *                 - 10: CR2 register
00722   *                 - 11: CR3 register
00723   *           - ZZZZZ  : Flag position in the ISR register(5bits)
00724   * @{
00725   */
00726 #define UART_IT_PE                          ((uint32_t)0x0028U)                  /*!< UART parity error interruption                 */
00727 #define UART_IT_TXE                         ((uint32_t)0x0727U)                  /*!< UART transmit data register empty interruption */
00728 #define UART_IT_TC                          ((uint32_t)0x0626U)                  /*!< UART transmission complete interruption        */
00729 #define UART_IT_RXNE                        ((uint32_t)0x0525U)                  /*!< UART read data register not empty interruption */
00730 #define UART_IT_IDLE                        ((uint32_t)0x0424U)                  /*!< UART idle interruption                         */
00731 #define UART_IT_LBD                         ((uint32_t)0x0846U)                  /*!< UART LIN break detection interruption          */
00732 #define UART_IT_CTS                         ((uint32_t)0x096AU)                  /*!< UART CTS interruption                          */
00733 #define UART_IT_CM                          ((uint32_t)0x112EU)                  /*!< UART character match interruption              */
00734 #define UART_IT_WUF                         ((uint32_t)0x1476U)                  /*!< UART wake-up from stop mode interruption       */
00735 #define UART_IT_RXFF                        ((uint16_t)0x183FU)
00736 #define UART_IT_TXFE                        ((uint16_t)0x173EU)
00737 #define UART_IT_RXFT                        ((uint16_t)0x1A7CU)
00738 #define UART_IT_TXFT                        ((uint16_t)0x1B77U)
00739
00740
00741 /**       Elements values convention: 000000000XXYYYYYb
00742   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00743   *           - XX  : Interrupt source register (2bits)
00744   *                 - 01: CR1 register
00745   *                 - 10: CR2 register
00746   *                 - 11: CR3 register
00747   */
00748 #define UART_IT_ERR                         ((uint32_t)0x0060U)                  /*!< UART error interruption         */
00749
00750 /**       Elements values convention: 0000ZZZZ00000000b
00751   *           - ZZZZ  : Flag position in the ISR register(4bits)
00752   */
00753 #define UART_IT_ORE                         ((uint32_t)0x0300U)                  /*!< UART overrun error interruption */
00754 #define UART_IT_NE                          ((uint32_t)0x0200U)                  /*!< UART noise error interruption   */
00755 #define UART_IT_FE                          ((uint32_t)0x0100U)                  /*!< UART frame error interruption   */
00756 /**
00757   * @}
00758   */
00759
00760 /** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags
00761   * @{
00762   */
00763 #define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag           */
00764 #define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag          */
00765 #define UART_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag         */
00766 #define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag          */
00767 #define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag     */
00768 #define UART_CLEAR_TXFECF                    USART_ICR_TXFECF          /*!< TXFIFO empty clear flag           */
00769 #define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag  */
00770 #define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag    */
00771 #define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag          */
00772 #define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< Receiver Time Out Clear Flag      */
00773 #define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag        */
00774 #define UART_CLEAR_WUF                       USART_ICR_WUCF            /*!< Wake Up from stop mode Clear Flag */
00775 /**
00776   * @}
00777   */
00778
00779
00780 /**
00781   * @}
00782   */
00783
00784 /* Exported macros -----------------------------------------------------------*/
00785 /** @defgroup UART_Exported_Macros UART Exported Macros
00786   * @{
00787   */
00788
00789 /** @brief  Reset UART handle states.
00790   * @param  __HANDLE__: UART handle.
00791   * @retval None
00792   */
00793 #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00794                                                        (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
00795                                                        (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
00796                                                      } while(0)
00797 /** @brief  Flush the UART Data registers.
00798   * @param  __HANDLE__: specifies the UART Handle.
00799   * @retval None
00800   */
00801 #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \
00802   do{                \
00803       SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
00804       SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
00805     }  while(0)
00806
00807 /** @brief  Clear the specified UART pending flag.
00808   * @param  __HANDLE__: specifies the UART Handle.
00809   * @param  __FLAG__: specifies the flag to check.
00810   *          This parameter can be any combination of the following values:
00811   *            @arg UART_FLAG_WUF:   Wake up from stop mode flag
00812   *            @arg UART_FLAG_CMF:   Character match flag
00813   *            @arg UART_FLAG_RTOF:  Receiver timeout flag
00814   *            @arg UART_FLAG_CTS:   CTS Change flag (not available for UART4 and UART5)
00815   *            @arg UART_FLAG_LBD:   LIN Break detection flag
00816   *            @arg UART_FLAG_TC:    Transmission Complete flag
00817   *            @arg UART_FLAG_TXFE:  TXFIFO Empty flag
00818   *            @arg UART_FLAG_IDLE:  Idle Line detection flag
00819   *            @arg UART_FLAG_ORE:   OverRun Error flag
00820   *            @arg UART_FLAG_NE:    Noise Error flag
00821   *            @arg UART_FLAG_FE:    Framing Error flag
00822   *            @arg UART_FLAG_PE:    Parity Error flag
00823   * @retval The new state of __FLAG__ (TRUE or FALSE).
00824   */
00825 #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00826
00827 /** @brief  Clear the UART PE pending flag.
00828   * @param  __HANDLE__: specifies the UART Handle.
00829   * @retval None
00830   */
00831 #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
00832
00833 /** @brief  Clear the UART FE pending flag.
00834   * @param  __HANDLE__: specifies the UART Handle.
00835   * @retval None
00836   */
00837 #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
00838
00839 /** @brief  Clear the UART NE pending flag.
00840   * @param  __HANDLE__: specifies the UART Handle.
00841   * @retval None
00842   */
00843 #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
00844
00845 /** @brief  Clear the UART ORE pending flag.
00846   * @param  __HANDLE__: specifies the UART Handle.
00847   * @retval None
00848   */
00849 #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
00850
00851 /** @brief  Clear the UART IDLE pending flag.
00852   * @param  __HANDLE__: specifies the UART Handle.
00853   * @retval None
00854   */
00855 #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
00856
00857 /** @brief  Clear the UART TX FIFO empty clear flag.
00858   * @param  __HANDLE__: specifies the UART Handle.
00859   * @retval None
00860   */
00861 #define __HAL_UART_CLEAR_TXFECF(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
00862
00863 /** @brief  Check whether the specified UART flag is set or not.
00864   * @param  __HANDLE__: specifies the UART Handle.
00865   * @param  __FLAG__: specifies the flag to check.
00866   *        This parameter can be one of the following values:
00867   *            @arg UART_FLAG_TXFT: TXFIFO threshold flag
00868   *            @arg UART_FLAG_RXFT: RXFIFO threshold flag
00869   *            @arg UART_FLAG_RXFF:  RXFIFO Full flag
00870   *            @arg UART_FLAG_TXFE:  TXFIFO Empty flag
00871   *            @arg UART_FLAG_REACK: Receive enable acknowledge flag
00872   *            @arg UART_FLAG_TEACK: Transmit enable acknowledge flag
00873   *            @arg UART_FLAG_WUF:   Wake up from stop mode flag
00874   *            @arg UART_FLAG_RWU:   Receiver wake up flag (if the UART in mute mode)
00875   *            @arg UART_FLAG_SBKF:  Send Break flag
00876   *            @arg UART_FLAG_CMF:   Character match flag
00877   *            @arg UART_FLAG_BUSY:  Busy flag
00878   *            @arg UART_FLAG_ABRF:  Auto Baud rate detection flag
00879   *            @arg UART_FLAG_ABRE:  Auto Baud rate detection error flag
00880   *            @arg UART_FLAG_RTOF:  Receiver timeout flag
00881   *            @arg UART_FLAG_CTS:   CTS Change flag
00882   *            @arg UART_FLAG_LBD:   LIN Break detection flag
00883   *            @arg UART_FLAG_TXE:   Transmit data register empty flag
00884   *            @arg UART_FLAG_TC:    Transmission Complete flag
00885   *            @arg UART_FLAG_RXNE:  Receive data register not empty flag
00886   *            @arg UART_FLAG_IDLE:  Idle Line detection flag
00887   *            @arg UART_FLAG_ORE:   OverRun Error flag
00888   *            @arg.UART_FLAG_NE:    Noise Error flag
00889   *            @arg UART_FLAG_FE:    Framing Error flag
00890   *            @arg UART_FLAG_PE:    Parity Error flag
00891   * @retval The new state of __FLAG__ (TRUE or FALSE).
00892   */
00893 #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00894
00895 /** @brief  Enable the specified UART interrupt.
00896   * @param  __HANDLE__: specifies the UART Handle.
00897   * @param  __INTERRUPT__: specifies the UART interrupt source to enable.
00898   *          This parameter can be one of the following values:
00899   *            @arg UART_IT_RXFF :  RXFIFO Full interrupt
00900   *            @arg UART_IT_TXFE :  TXFIFO Empty interrupt
00901   *            @arg.UART_IT_RXFT :  RXFIFO threshold interrupt
00902   *            @arg UART_IT_TXFT :  TXFIFO threshold interrupt
00903   *            @arg UART_IT_WUF:  Wakeup from stop mode interrupt
00904   *            @arg UART_IT_CM:   Character match interrupt
00905   *            @arg UART_IT_CTS:  CTS change interrupt
00906   *            @arg UART_IT_LBD:  LIN Break detection interrupt
00907   *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
00908   *            @arg UART_IT_TC:   Transmission complete interrupt
00909   *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
00910   *            @arg UART_IT_IDLE: Idle line detection interrupt
00911   *            @arg.UART_IT_PE:   Parity Error interrupt
00912   *            @arg UART_IT_ERR:  Error interrupt (Frame error, noise error, overrun error)
00913   * @retval None
00914   */
00915 #define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00916                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00917                                                            ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
00918
00919
00920 /** @brief  Disable the specified UART interrupt.
00921   * @param  __HANDLE__: specifies the UART Handle.
00922   * @param  __INTERRUPT__: specifies the UART interrupt source to disable.
00923   *          This parameter can be one of the following values:
00924   *            @arg.UART_IT_RXFF :  RXFIFO Full interrupt
00925   *            @arg UART_IT_TXFE :  TXFIFO Empty interrupt
00926   *            @arg UART_IT_RXFT :  RXFIFO threshold interrupt
00927   *            @arg UART_IT_TXFT :  TXFIFO threshold interrupt
00928   *            @arg UART_IT_WUF:  Wakeup from stop mode interrupt
00929   *            @arg UART_IT_CM:   Character match interrupt
00930   *            @arg UART_IT_CTS:  CTS change interrupt
00931   *            @arg UART_IT_LBD:  LIN Break detection interrupt
00932   *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
00933   *            @arg UART_IT_TC:   Transmission complete interrupt
00934   *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
00935   *            @arg UART_IT_IDLE: Idle line detection interrupt
00936   *            @arg UART_IT_PE:   Parity Error interrupt
00937   *            @arg UART_IT_ERR:  Error interrupt (Frame error, noise error, overrun error)
00938   * @retval None
00939   */
00940 #define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00941                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00942                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
00943
00944 /** @brief  Check whether the specified UART interrupt has occurred or not.
00945   * @param  __HANDLE__: specifies the UART Handle.
00946   * @param  __IT__: specifies the UART interrupt to check.
00947   *          This parameter can be one of the following values:
00948   *            @arg UART_IT_RXFF :  RXFIFO Full interrupt
00949   *            @arg UART_IT_TXFE :  TXFIFO Empty interrupt
00950   *            @arg UART_IT_RXFT :  RXFIFO threshold interrupt
00951   *            @arg UART_IT_TXFT :  TXFIFO threshold interrupt
00952   *            @arg UART_IT_WUF:  Wakeup from stop mode interrupt
00953   *            @arg UART_IT_CM:   Character match interrupt
00954   *            @arg UART_IT_CTS:  CTS change interrupt
00955   *            @arg UART_IT_LBD:  LIN Break detection interrupt
00956   *            @arg  UART_IT_TXE:  Transmit Data Register empty interrupt
00957   *            @arg UART_IT_TC:   Transmission complete interrupt
00958   *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
00959   *            @arg UART_IT_IDLE: Idle line detection interrupt
00960   *            @arg UART_IT_ORE:  OverRun Error interrupt
00961   *            @arg UART_IT_NE:   Noise Error interrupt
00962   *            @arg UART_IT_FE:   Framing Error interrupt
00963   *            @arg UART_IT_PE:   Parity Error interrupt
00964   * @retval The new state of __IT__ (TRUE or FALSE).
00965   */
00966 #define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
00967
00968 /** @brief  Check whether the specified UART interrupt source is enabled or not.
00969   * @param  __HANDLE__: specifies the UART Handle.
00970   * @param  __IT__: specifies the UART interrupt source to check.
00971   *          This parameter can be one of the following values:
00972   *            @arg UART_IT_RXFF :  RXFIFO Full interrupt
00973   *            @arg UART_IT_TXFE :  TXFIFO Empty interrupt
00974   *            @arg UART_IT_RXFT :  RXFIFO threshold interrupt
00975   *            @arg UART_IT_TXFT :  TXFIFO threshold interrupt
00976   *            @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
00977   *            @arg UART_IT_LBD: LIN Break detection interrupt
00978   *            @arg UART_IT_TXE: Transmit Data Register empty interrupt
00979   *            @arg UART_IT_TC:  Transmission complete interrupt
00980   *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
00981   *            @arg UART_IT_IDLE: Idle line detection interrupt
00982   *            @arg UART_IT_ORE: OverRun Error interrupt
00983   *            @arg UART_IT_NE: Noise Error interrupt
00984   *            @arg UART_IT_FE: Framing Error interrupt
00985   *            @arg UART_IT_PE: Parity Error interrupt
00986   * @retval The new state of __IT__ (TRUE or FALSE).
00987   */
00988 #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
00989                                                        (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))
00990
00991 /** @brief  Clear the specified UART ISR flag, in setting the proper ICR register flag.
00992   * @param  __HANDLE__: specifies the UART Handle.
00993   * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
00994   *                       to clear the corresponding interrupt
00995   *          This parameter can be one of the following values:
00996   *            @arg UART_CLEAR_PEF: Parity Error Clear Flag
00997   *            @arg UART_CLEAR_FEF: Framing Error Clear Flag
00998   *            @arg UART_CLEAR_NEF: Noise detected Clear Flag
00999   *            @arg UART_CLEAR_OREF: OverRun Error Clear Flag
01000   *            @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag
01001   *            @arg UART_CLEAR_TCF: Transmission Complete Clear Flag
01002   *            @arg UART_CLEAR_LBDF: LIN Break Detection Clear Flag
01003   *            @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag
01004   *            @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag
01005   *            @arg UART_CLEAR_CMF: Character Match Clear Flag
01006   *            @arg.UART_CLEAR_WUF:  Wake Up from stop mode Clear Flag
01007   *            @arg UART_CLEAR_TXFECF: TXFIFO empty Clear Flag
01008   * @retval None
01009   */
01010 #define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
01011
01012 /** @brief  Set a specific UART request flag.
01013   * @param  __HANDLE__: specifies the UART Handle.
01014   * @param  __REQ__: specifies the request flag to set
01015   *          This parameter can be one of the following values:
01016   *            @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request
01017   *            @arg UART_SENDBREAK_REQUEST: Send Break Request
01018   *            @arg UART_MUTE_MODE_REQUEST: Mute Mode Request
01019   *            @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
01020   *            @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
01021   * @retval None
01022   */
01023 #define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
01024
01025 /** @brief  Enable the UART one bit sample method.
01026   * @param  __HANDLE__: specifies the UART Handle.
01027   * @retval None
01028   */
01029 #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
01030
01031 /** @brief  Disable the UART one bit sample method.
01032   * @param  __HANDLE__: specifies the UART Handle.
01033   * @retval None
01034   */
01035 #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
01036
01037 /** @brief  Enable UART.
01038   * @param  __HANDLE__: specifies the UART Handle.
01039   * @retval None
01040   */
01041 #define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
01042
01043 /** @brief  Disable UART.
01044   * @param  __HANDLE__: specifies the UART Handle.
01045   * @retval None
01046   */
01047 #define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
01048
01049 /** @brief  Enable CTS flow control.
01050   * @note   This macro allows to enable CTS hardware flow control for a given UART instance,
01051   *         without need to call HAL_UART_Init() function.
01052   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
01053   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
01054   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
01055   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
01056   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
01057   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
01058   * @param  __HANDLE__: specifies the UART Handle.
01059   * @retval None
01060   */
01061 #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
01062   do{                                                      \
01063     SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
01064     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
01065   } while(0)
01066
01067 /** @brief  Disable CTS flow control.
01068   * @note   This macro allows to disable CTS hardware flow control for a given UART instance,
01069   *         without need to call HAL_UART_Init() function.
01070   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
01071   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
01072   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
01073   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
01074   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
01075   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
01076   * @param  __HANDLE__: specifies the UART Handle.
01077   * @retval None
01078   */
01079 #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
01080   do{                                                       \
01081     CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
01082     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
01083   } while(0)
01084
01085 /** @brief  Enable RTS flow control.
01086   * @note   This macro allows to enable RTS hardware flow control for a given UART instance,
01087   *         without need to call HAL_UART_Init() function.
01088   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
01089   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
01090   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
01091   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
01092   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
01093   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
01094   * @param  __HANDLE__: specifies the UART Handle.
01095   * @retval None
01096   */
01097 #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
01098   do{                                                     \
01099     SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
01100     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
01101   } while(0)
01102
01103 /** @brief  Disable RTS flow control.
01104   * @note   This macro allows to disable RTS hardware flow control for a given UART instance,
01105   *         without need to call HAL_UART_Init() function.
01106   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
01107   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
01108   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
01109   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
01110   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
01111   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
01112   * @param  __HANDLE__: specifies the UART Handle.
01113   * @retval None
01114   */
01115 #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
01116   do{                                                      \
01117     CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
01118     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
01119   } while(0)
01120
01121 /**
01122   * @}
01123   */
01124
01125 /* Private variables -----------------------------------------------------*/
01126 /** @defgroup UART_Private_Variables   UART Private Variables
01127   * @{
01128   */
01129 static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256};
01130 /**
01131   * @}
01132   */
01133
01134 /* Private macros --------------------------------------------------------*/
01135 /** @defgroup UART_Private_Macros   UART Private Macros
01136   * @{
01137   */
01138 /** @brief  BRR division operation to set BRR register with LPUART.
01139   * @param  __PCLK__: LPUART clock.
01140   * @param  __BAUD__: Baud rate set by the user.
01141   * @param  __PRESCALER__: UART prescaler value.
01142   * @retval Division result
01143   */
01144 #define UART_DIV_LPUART(__PCLK__, __BAUD__, __PRESCALER__)      ((((((uint64_t)(__PCLK__)/UARTPrescTable[(__PRESCALER__)])*256)) + ((__BAUD__)/2)) / (__BAUD__))
01145
01146 /** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
01147   * @param  __PCLK__: UART clock.
01148   * @param  __BAUD__: Baud rate set by the user.
01149   * @param  __PRESCALER__: UART prescaler value.
01150   * @retval Division result
01151   */
01152 #define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __PRESCALER__)   (((((__PCLK__)/UARTPrescTable[(__PRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__))
01153
01154 /** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
01155   * @param  __PCLK__: UART clock.
01156   * @param  __BAUD__: Baud rate set by the user.
01157   * @param  __PRESCALER__: UART prescaler value.
01158   * @retval Division result
01159   */
01160 #define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__)  ((((__PCLK__)/UARTPrescTable[(__PRESCALER__)]) + ((__BAUD__)/2)) / (__BAUD__))
01161
01162 /** @brief  Check whether or not UART instance is Low Power UART.
01163   * @param  __HANDLE__: specifies the UART Handle.
01164   * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
01165   */
01166 #define UART_INSTANCE_LOWPOWER(__HANDLE__) (((__HANDLE__)->Instance == LPUART1) ? SET : RESET )
01167
01168 /** @brief  Check UART Baud rate.
01169   * @param  __BAUDRATE__: Baudrate specified by the user.
01170   *         The maximum Baud Rate is derived from the maximum clock on H7 (i.e. 100 MHz)
01171   *         divided by the smallest oversampling used on the USART (i.e. 8)
01172   * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
01173   */
01174 #define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
01175
01176 /** @brief  Check UART assertion time.
01177   * @param  __TIME__: 5-bit value assertion time.
01178   * @retval Test result (TRUE or FALSE).
01179   */
01180 #define IS_UART_ASSERTIONTIME(__TIME__)    ((__TIME__) <= 0x1FU)
01181
01182 /** @brief  Check UART deassertion time.
01183   * @param  __TIME__: 5-bit value deassertion time.
01184   * @retval Test result (TRUE or FALSE).
01185   */
01186 #define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
01187
01188 /**
01189   * @brief Ensure that UART frame number of stop bits is valid.
01190   * @param __STOPBITS__: UART frame number of stop bits.
01191   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
01192   */
01193 #define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
01194                                         ((__STOPBITS__) == UART_STOPBITS_1)   || \
01195                                         ((__STOPBITS__) == UART_STOPBITS_1_5) || \
01196                                         ((__STOPBITS__) == UART_STOPBITS_2))
01197
01198 /**
01199   * @brief Ensure that LPUART frame number of stop bits is valid.
01200   * @param __STOPBITS__: LPUART frame number of stop bits.
01201   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
01202   */
01203 #define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
01204                                           ((__STOPBITS__) == UART_STOPBITS_2))
01205
01206 /**
01207   * @brief Ensure that UART frame parity is valid.
01208   * @param __PARITY__: UART frame parity.
01209   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
01210   */
01211 #define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
01212                                     ((__PARITY__) == UART_PARITY_EVEN) || \
01213                                     ((__PARITY__) == UART_PARITY_ODD))
01214
01215 /**
01216   * @brief Ensure that UART hardware flow control is valid.
01217   * @param __CONTROL__: UART hardware flow control.
01218   * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
01219   */
01220 #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
01221                                    (((__CONTROL__) == UART_HWCONTROL_NONE) || \
01222                                     ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
01223                                     ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
01224                                     ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
01225
01226 /**
01227   * @brief Ensure that UART communication mode is valid.
01228   * @param __MODE__: UART communication mode.
01229   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01230   */
01231 #define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
01232
01233 /**
01234   * @brief Ensure that UART state is valid.
01235   * @param __STATE__: UART state.
01236   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
01237   */
01238 #define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
01239                                   ((__STATE__) == UART_STATE_ENABLE))
01240
01241 /**
01242   * @brief Ensure that UART oversampling is valid.
01243   * @param __SAMPLING__: UART oversampling.
01244   * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
01245   */
01246 #define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
01247                                             ((__SAMPLING__) == UART_OVERSAMPLING_8))
01248
01249 /**
01250   * @brief Ensure that UART frame sampling is valid.
01251   * @param __ONEBIT__: UART frame sampling.
01252   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
01253   */
01254 #define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
01255                                             ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
01256
01257 /**
01258   * @brief Ensure that UART auto Baud rate detection mode is valid.
01259   * @param __MODE__: UART auto Baud rate detection mode.
01260   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01261   */
01262 #define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)  (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
01263                                                         ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
01264                                                         ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
01265                                                         ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
01266
01267 /**
01268   * @brief Ensure that UART receiver timeout setting is valid.
01269   * @param __TIMEOUT__: UART receiver timeout setting.
01270   * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
01271   */
01272 #define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
01273                                                ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
01274
01275 /**
01276   * @brief Ensure that UART LIN state is valid.
01277   * @param __LIN__: UART LIN state.
01278   * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
01279   */
01280 #define IS_UART_LIN(__LIN__)        (((__LIN__) == UART_LIN_DISABLE) || \
01281                                      ((__LIN__) == UART_LIN_ENABLE))
01282
01283 /**
01284   * @brief Ensure that UART LIN break detection length is valid.
01285   * @param __LENGTH__: UART LIN break detection length.
01286   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
01287   */
01288 #define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
01289                                                      ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
01290
01291 /**
01292   * @brief Ensure that UART DMA TX state is valid.
01293   * @param __DMATX__: UART DMA TX state.
01294   * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
01295   */
01296 #define IS_UART_DMA_TX(__DMATX__)     (((__DMATX__) == UART_DMA_TX_DISABLE) || \
01297                                        ((__DMATX__) == UART_DMA_TX_ENABLE))
01298
01299 /**
01300   * @brief Ensure that UART DMA RX state is valid.
01301   * @param __DMARX__: UART DMA RX state.
01302   * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
01303   */
01304 #define IS_UART_DMA_RX(__DMARX__)     (((__DMARX__) == UART_DMA_RX_DISABLE) || \
01305                                        ((__DMARX__) == UART_DMA_RX_ENABLE))
01306
01307 /**
01308   * @brief Ensure that UART half-duplex state is valid.
01309   * @param __HDSEL__: UART half-duplex state.
01310   * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
01311   */
01312 #define IS_UART_HALF_DUPLEX(__HDSEL__)     (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
01313                                             ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
01314
01315 /**
01316   * @brief Ensure that UART wake-up method is valid.
01317   * @param __WAKEUP__: UART wake-up method .
01318   * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
01319   */
01320 #define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
01321                                           ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
01322
01323 /**
01324   * @brief Ensure that UART request parameter is valid.
01325   * @param __PARAM__: UART request parameter.
01326   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
01327   */
01328 #define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
01329                                               ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
01330                                               ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
01331                                               ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
01332                                               ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
01333
01334 /**
01335   * @brief Ensure that UART advanced features initialization is valid.
01336   * @param __INIT__: UART advanced features initialization.
01337   * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
01338   */
01339 #define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
01340                                                             UART_ADVFEATURE_TXINVERT_INIT          | \
01341                                                             UART_ADVFEATURE_RXINVERT_INIT          | \
01342                                                             UART_ADVFEATURE_DATAINVERT_INIT        | \
01343                                                             UART_ADVFEATURE_SWAP_INIT              | \
01344                                                             UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
01345                                                             UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
01346                                                             UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
01347                                                             UART_ADVFEATURE_MSBFIRST_INIT))
01348
01349 /**
01350   * @brief Ensure that UART frame TX inversion setting is valid.
01351   * @param __TXINV__: UART frame TX inversion setting.
01352   * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
01353   */
01354 #define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
01355                                              ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
01356
01357 /**
01358   * @brief Ensure that UART frame RX inversion setting is valid.
01359   * @param __RXINV__: UART frame RX inversion setting.
01360   * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
01361   */
01362 #define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
01363                                              ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
01364
01365 /**
01366   * @brief Ensure that UART frame data inversion setting is valid.
01367   * @param __DATAINV__: UART frame data inversion setting.
01368   * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
01369   */
01370 #define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
01371                                                  ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
01372
01373 /**
01374   * @brief Ensure that UART frame RX/TX pins swap setting is valid.
01375   * @param __SWAP__: UART frame RX/TX pins swap setting.
01376   * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
01377   */
01378 #define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
01379                                            ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
01380
01381 /**
01382   * @brief Ensure that UART frame overrun setting is valid.
01383   * @param __OVERRUN__: UART frame overrun setting.
01384   * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
01385   */
01386 #define IS_UART_OVERRUN(__OVERRUN__)     (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
01387                                           ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
01388
01389 /**
01390   * @brief Ensure that UART auto Baud rate state is valid.
01391   * @param __AUTOBAUDRATE__: UART auto Baud rate state.
01392   * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
01393   */
01394 #define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)  (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
01395                                                             ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
01396
01397 /**
01398   * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
01399   * @param __DMA__: UART DMA enabling or disabling on error setting.
01400   * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
01401   */
01402 #define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)  (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
01403                                                    ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
01404
01405 /**
01406   * @brief Ensure that UART frame MSB first setting is valid.
01407   * @param __MSBFIRST__: UART frame MSB first setting.
01408   * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
01409   */
01410 #define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
01411                                                    ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
01412
01413 /**
01414   * @brief Ensure that UART stop mode state is valid.
01415   * @param __STOPMODE__: UART stop mode state.
01416   * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
01417   */
01418 #define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
01419                                                    ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
01420
01421 /**
01422   * @brief Ensure that UART mute mode state is valid.
01423   * @param __MUTE__: UART mute mode state.
01424   * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
01425   */
01426 #define IS_UART_MUTE_MODE(__MUTE__)       (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
01427                                            ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
01428
01429 /**
01430   * @brief Ensure that UART wake-up selection is valid.
01431   * @param __WAKE__: UART wake-up selection.
01432   * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
01433   */
01434 #define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS           ) || \
01435                                             ((__WAKE__) == UART_WAKEUP_ON_STARTBIT          ) || \
01436                                             ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY ) || \
01437                                             ((__WAKE__) == UART_WAKEUP_ON_RXFIFO_THRESHOLD  ) || \
01438                                             ((__WAKE__) == UART_WAKEUP_ON_RXFIFO_FULL       ) || \
01439                                             ((__WAKE__) == UART_WAKEUP_ON_TXFIFO_THRESHOLD  ) || \
01440                                             ((__WAKE__) == UART_WAKEUP_ON_TXFIFO_EMPTY      ))
01441
01442 /**
01443   * @brief Ensure that UART driver enable polarity is valid.
01444   * @param __POLARITY__: UART driver enable polarity.
01445   * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
01446   */
01447 #define IS_UART_DE_POLARITY(__POLARITY__)    (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
01448                                               ((__POLARITY__) == UART_DE_POLARITY_LOW))
01449
01450 /**
01451   * @brief Ensure that LPUART frame number of stop bits is valid.
01452   * @param __STOPBITS__: LPUART frame number of stop bits.
01453   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
01454   */
01455 #define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
01456                                           ((__STOPBITS__) == UART_STOPBITS_2))
01457
01458 /**
01459   * @brief Ensure that UART Prescaler is valid.
01460   * @param __PRESCALER__: UART Prescaler value.
01461   * @retval SET (__PRESCALER__ is valid) or RESET (__PRESCALER__ is invalid)
01462   */
01463 #define IS_UART_PRESCALER(__PRESCALER__) (((__PRESCALER__) == UART_PRESCALER_DIV1) || \
01464                                           ((__PRESCALER__) == UART_PRESCALER_DIV2) || \
01465                                           ((__PRESCALER__) == UART_PRESCALER_DIV4) || \
01466                                           ((__PRESCALER__) == UART_PRESCALER_DIV6) || \
01467                                           ((__PRESCALER__) == UART_PRESCALER_DIV8) || \
01468                                           ((__PRESCALER__) == UART_PRESCALER_DIV10) || \
01469                                           ((__PRESCALER__) == UART_PRESCALER_DIV12) || \
01470                                           ((__PRESCALER__) == UART_PRESCALER_DIV16) || \
01471                                           ((__PRESCALER__) == UART_PRESCALER_DIV32) || \
01472                                           ((__PRESCALER__) == UART_PRESCALER_DIV64) || \
01473                                           ((__PRESCALER__) == UART_PRESCALER_DIV128) || \
01474                                           ((__PRESCALER__) == UART_PRESCALER_DIV256))
01475
01476 /**
01477   * @brief Ensure that UART FIFO mode is valid.
01478   * @param __STATE__: UART FIFO mode.
01479   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
01480   */
01481 #define IS_UART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == UART_FIFOMODE_DISABLE ) || \
01482                                                 ((__STATE__) == UART_FIFOMODE_ENABLE))
01483
01484 /**
01485   * @brief Ensure that UART TXFIFO threshold level is valid.
01486   * @param __THRESHOLD__: UART TXFIFO threshold level.
01487   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
01488   */
01489 #define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) ((((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8 ) || \
01490                                                   ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4 ) || \
01491                                                   ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2)  || \
01492                                                   ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4)  || \
01493                                                   ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8)) || \
01494                                                   ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
01495
01496 /**
01497   * @brief Ensure that UART RXFIFO threshold level is valid.
01498   * @param __THRESHOLD__: UART RXFIFO threshold level.
01499   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
01500   */
01501 #define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) ((((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8 ) || \
01502                                                   ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4 ) || \
01503                                                   ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2)  || \
01504                                                   ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4)  || \
01505                                                   ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8)) || \
01506                                                   ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
01507
01508 /**
01509   * @}
01510   */
01511
01512 /* Include UART HAL Extended module */
01513 #include "stm32h7xx_hal_uart_ex.h"
01514
01515 /* Exported functions --------------------------------------------------------*/
01516 /** @addtogroup UART_Exported_Functions UART Exported Functions
01517   * @{
01518   */
01519
01520 /** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
01521   * @{
01522   */
01523
01524 /* Initialization and de-initialization functions  ****************************/
01525 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
01526 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
01527 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
01528 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
01529 HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
01530 void HAL_UART_MspInit(UART_HandleTypeDef *huart);
01531 void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
01532
01533 /**
01534   * @}
01535   */
01536
01537 /** @addtogroup UART_Exported_Functions_Group2 IO operation functions
01538   * @{
01539   */
01540
01541 /* IO operation functions *****************************************************/
01542 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
01543 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
01544 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01545 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01546 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01547 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01548 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
01549 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
01550 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
01551 /* Transfer Abort functions */
01552 HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
01553 HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
01554 HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
01555 HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
01556 HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
01557 HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
01558
01559 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
01560 void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
01561 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
01562 void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
01563 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
01564 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
01565 void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart);
01566 void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart);
01567 void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart);
01568
01569 /**
01570   * @}
01571   */
01572
01573 /** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
01574   * @{
01575   */
01576
01577 /* Peripheral Control functions  ************************************************/
01578 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
01579 HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
01580 HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
01581 void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
01582 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
01583 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
01584
01585 /**
01586   * @}
01587   */
01588
01589 /** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
01590   * @{
01591   */
01592
01593 /* Peripheral State and Errors functions  **************************************************/
01594 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
01595 uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
01596
01597 /**
01598   * @}
01599   */
01600
01601 /**
01602   * @}
01603   */
01604
01605 /* Private functions -----------------------------------------------------------*/
01606 /** @addtogroup UART_Private_Functions UART Private Functions
01607   * @{
01608   */
01609
01610 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
01611 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
01612 HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
01613 void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
01614
01615 /**
01616   * @}
01617   */
01618
01619 /**
01620   * @}
01621   */
01622
01623 /**
01624   * @}
01625   */
01626
01627 #ifdef __cplusplus
01628 }
01629 #endif
01630
01631 #endif /* __STM32H7xx_HAL_UART_H */
01632
01633 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_uart_ex.c Source File

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stm32h7xx_hal_uart_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_uart_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Extended UART HAL module driver.
00008   *          This file provides firmware functions to manage the following extended
00009   *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
00010   *           + Initialization and de-initialization functions
00011   *           + Peripheral Control functions
00012   *
00013   *
00014   @verbatim
00015   ==============================================================================
00016                ##### UART peripheral extended features  #####
00017   ==============================================================================
00018
00019     (#) Declare a UART_HandleTypeDef handle structure.
00020
00021     (#) For the UART RS485 Driver Enable mode, initialize the UART registers
00022         by calling the HAL_RS485Ex_Init() API.
00023
00024
00025   @endverbatim
00026   ******************************************************************************
00027   * @attention
00028   *
00029   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00030   *
00031   * Redistribution and use in source and binary forms, with or without modification,
00032   * are permitted provided that the following conditions are met:
00033   *   1. Redistributions of source code must retain the above copyright notice,
00034   *      this list of conditions and the following disclaimer.
00035   *   2. Redistributions in binary form must reproduce the above copyright notice,
00036   *      this list of conditions and the following disclaimer in the documentation
00037   *      and/or other materials provided with the distribution.
00038   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00039   *      may be used to endorse or promote products derived from this software
00040   *      without specific prior written permission.
00041   *
00042   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00043   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00044   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00045   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00046   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00047   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00048   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00049   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00050   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00051   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00052   *
00053   ******************************************************************************
00054   */
00055
00056 /* Includes ------------------------------------------------------------------*/
00057 #include "stm32h7xx_hal.h"
00058
00059 /** @addtogroup STM32H7xx_HAL_Driver
00060   * @{
00061   */
00062
00063 /** @defgroup UARTEx UARTEx
00064   * @brief UART Extended HAL module driver
00065   * @{
00066   */
00067
00068 #ifdef HAL_UART_MODULE_ENABLED
00069
00070 /* Private typedef -----------------------------------------------------------*/
00071 /* Private define ------------------------------------------------------------*/
00072 /* Private macros ------------------------------------------------------------*/
00073 /* Private variables ---------------------------------------------------------*/
00074 /* Private function prototypes -----------------------------------------------*/
00075 /** @defgroup UARTEx_Private_Functions UARTEx Private Functions
00076   * @{
00077   */
00078 static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
00079 /**
00080   * @}
00081   */
00082
00083 /* Exported functions --------------------------------------------------------*/
00084
00085 /** @defgroup UARTEx_Exported_Functions  UARTEx Exported Functions
00086   * @{
00087   */
00088
00089 /** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
00090   * @brief    Extended Initialization and Configuration Functions
00091   *
00092 @verbatim
00093 ===============================================================================
00094             ##### Initialization and Configuration functions #####
00095  ===============================================================================
00096     [..]
00097     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
00098     in asynchronous mode.
00099       (+) For the asynchronous mode the parameters below can be configured:
00100         (++) Baud Rate
00101         (++) Word Length
00102         (++) Stop Bit
00103         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00104              in the data register is transmitted but is changed by the parity bit.
00105         (++) Hardware flow control
00106         (++) Receiver/transmitter modes
00107         (++) Over Sampling Method
00108         (++) One-Bit Sampling Method
00109       (+) For the asynchronous mode, the following advanced features can be configured as well:
00110         (++) TX and/or RX pin level inversion
00111         (++) data logical level inversion
00112         (++) RX and TX pins swap
00113         (++) RX overrun detection disabling
00114         (++) DMA disabling on RX error
00115         (++) MSB first on communication line
00116         (++) auto Baud rate detection
00117     [..]
00118     The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
00119      procedures (details for the procedures are available in reference manual).
00120
00121 @endverbatim
00122
00123   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00124   8-bit or 9-bit), the possible UART formats are listed in the
00125   following table.
00126
00127     Table 1. UART frame format.
00128     +-----------------------------------------------------------------------+
00129     |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
00130     |---------|---------|-----------|---------------------------------------|
00131     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00132     |---------|---------|-----------|---------------------------------------|
00133     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00134     |---------|---------|-----------|---------------------------------------|
00135     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00136     |---------|---------|-----------|---------------------------------------|
00137     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00138     |---------|---------|-----------|---------------------------------------|
00139     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00140     |---------|---------|-----------|---------------------------------------|
00141     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00142     +-----------------------------------------------------------------------+
00143
00144   * @{
00145   */
00146
00147 /**
00148   * @brief Initialize the RS485 Driver enable feature according to the specified
00149   *         parameters in the UART_InitTypeDef and creates the associated handle.
00150   * @param huart: UART handle.
00151   * @param Polarity: select the driver enable polarity.
00152   *        This parameter can be one of the following values:
00153   *          @arg UART_DE_POLARITY_HIGH: DE signal is active high
00154   *          @arg UART_DE_POLARITY_LOW: DE signal is active low
00155   * @param AssertionTime: Driver Enable assertion time:
00156   *                         5-bit value defining the time between the activation of the DE (Driver Enable)
00157   *                         signal and the beginning of the start bit. It is expressed in sample time
00158   *                         units (1/8 or 1/16 bit time, depending on the oversampling rate)
00159   * @param DeassertionTime: Driver Enable deassertion time:
00160   *                         5-bit value defining the time between the end of the last stop bit, in a
00161   *                         transmitted message, and the de-activation of the DE (Driver Enable) signal.
00162   *                         It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
00163   *                         oversampling rate).
00164   * @retval HAL status
00165   */
00166 HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
00167 {
00168   uint32_t temp = 0x0U;
00169
00170   /* Check the UART handle allocation */
00171   if(huart == NULL)
00172   {
00173     return HAL_ERROR;
00174   }
00175   /* Check the Driver Enable UART instance */
00176   assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
00177
00178   /* Check the Driver Enable polarity */
00179   assert_param(IS_UART_DE_POLARITY(Polarity));
00180
00181   /* Check the Driver Enable assertion time */
00182   assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
00183
00184   /* Check the Driver Enable deassertion time */
00185   assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
00186
00187   if(huart->gState == HAL_UART_STATE_RESET)
00188   {
00189     /* Allocate lock resource and initialize it */
00190     huart->Lock = HAL_UNLOCKED;
00191
00192     /* Init the low level hardware : GPIO, CLOCK, CORTEX */
00193     HAL_UART_MspInit(huart);
00194   }
00195
00196   huart->gState = HAL_UART_STATE_BUSY;
00197
00198   /* Disable the Peripheral */
00199   __HAL_UART_DISABLE(huart);
00200
00201   /* Set the UART Communication parameters */
00202   if (UART_SetConfig(huart) == HAL_ERROR)
00203   {
00204     return HAL_ERROR;
00205   }
00206
00207   if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00208   {
00209     UART_AdvFeatureConfig(huart);
00210   }
00211
00212   /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
00213   SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
00214
00215   /* Set the Driver Enable polarity */
00216   MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
00217
00218   /* Set the Driver Enable assertion and deassertion times */
00219   temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
00220   temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
00221   MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp);
00222
00223   /* Enable the Peripheral */
00224   __HAL_UART_ENABLE(huart);
00225
00226   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00227   return (UART_CheckIdleState(huart));
00228 }
00229
00230
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
00236   * @brief    Extended Peripheral Control functions
00237  *
00238 @verbatim
00239  ===============================================================================
00240                       ##### Peripheral Control functions #####
00241  ===============================================================================
00242     [..] This section provides the following functions:
00243      (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode
00244      (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality
00245      (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
00246          detection length to more than 4 bits for multiprocessor address mark wake up.
00247      (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
00248          trigger: address match, Start Bit detection or RXNE bit status.
00249      (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
00250      (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
00251      (+) HAL_UARTEx_WakeupCallback() called upon UART wakeup interrupt
00252
00253
00254 @endverbatim
00255   * @{
00256   */
00257
00258
00259
00260
00261 /**
00262   * @brief By default in multiprocessor mode, when the wake up method is set
00263   *        to address mark, the UART handles only 4-bit long addresses detection;
00264   *        this API allows to enable longer addresses detection (6-, 7- or 8-bit
00265   *        long).
00266   * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
00267   *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
00268   * @param huart: UART handle.
00269   * @param AddressLength: this parameter can be one of the following values:
00270   *          @arg UART_ADDRESS_DETECT_4B: 4-bit long address
00271   *          @arg UART_ADDRESS_DETECT_7B: 6-, 7- or 8-bit long address
00272   * @retval HAL status
00273   */
00274 HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
00275 {
00276   /* Check the UART handle allocation */
00277   if(huart == NULL)
00278   {
00279     return HAL_ERROR;
00280   }
00281
00282   /* Check the address length parameter */
00283   assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
00284
00285   huart->gState = HAL_UART_STATE_BUSY;
00286
00287   /* Disable the Peripheral */
00288   __HAL_UART_DISABLE(huart);
00289
00290   /* Set the address length */
00291   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
00292
00293   /* Enable the Peripheral */
00294   __HAL_UART_ENABLE(huart);
00295
00296   /* TEACK and/or REACK to check before moving huart->gState to Ready */
00297   return (UART_CheckIdleState(huart));
00298 }
00299
00300
00301 /**
00302   * @brief Set Wakeup from Stop mode interrupt flag selection.
00303   * @param huart: UART handle.
00304   * @param WakeUpSelection: address match, Start Bit detection, RXNE bit status
00305   *                         or RX/TX FIFO related event.
00306   * This parameter can be one of the following values:
00307   *      @arg @ref UART_WAKEUP_ON_ADDRESS
00308   *      @arg @ref UART_WAKEUP_ON_STARTBIT
00309   *      @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
00310   *      @arg @ref UART_WAKEUP_ON_RXFIFO_THRESHOLD
00311   *      @arg @ref UART_WAKEUP_ON_RXFIFO_FULL
00312   *      @arg @ref UART_WAKEUP_ON_TXFIFO_THRESHOLD
00313   *      @arg @ref UART_WAKEUP_ON_TXFIFO_EMPTY
00314   * @retval HAL status
00315   */
00316 HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
00317 {
00318   HAL_StatusTypeDef status = HAL_OK;
00319   uint32_t tickstart = 0U;
00320
00321   /* check the wake-up from stop mode UART instance */
00322   assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
00323   /* check the wake-up selection parameter */
00324   assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
00325
00326   /* Process Locked */
00327   __HAL_LOCK(huart);
00328
00329   huart->gState = HAL_UART_STATE_BUSY;
00330
00331   switch (WakeUpSelection.WakeUpEvent)
00332   {
00333     case UART_WAKEUP_ON_ADDRESS:
00334     case UART_WAKEUP_ON_STARTBIT:
00335     case UART_WAKEUP_ON_READDATA_NONEMPTY:
00336       /* Disable the Peripheral */
00337       __HAL_UART_DISABLE(huart);
00338
00339       /* Set the wake-up selection scheme */
00340       MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
00341
00342
00343       if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
00344       {
00345         UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
00346       }
00347
00348       /* Enable the Peripheral */
00349       __HAL_UART_ENABLE(huart);
00350
00351       /* Init tickstart for timeout managment*/
00352       tickstart = HAL_GetTick();
00353
00354       /* Wait until REACK flag is set */
00355       if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
00356       {
00357         status = HAL_TIMEOUT;
00358       }
00359       else
00360       {
00361         /* Initialize the UART State */
00362         huart->gState = HAL_UART_STATE_READY;
00363       }
00364       break;
00365
00366     case UART_WAKEUP_ON_RXFIFO_THRESHOLD:
00367       /* Enable RXFT interrupt */
00368       SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
00369       huart->gState = HAL_UART_STATE_READY;
00370       break;
00371
00372     case UART_WAKEUP_ON_RXFIFO_FULL:
00373       /* Enable RXFF interrupt */
00374       SET_BIT(huart->Instance->CR1, USART_CR1_RXFFIE);
00375       huart->gState = HAL_UART_STATE_READY;
00376       break;
00377
00378     case UART_WAKEUP_ON_TXFIFO_THRESHOLD:
00379       /* Enable TXFT interrupt */
00380       SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
00381       huart->gState = HAL_UART_STATE_READY;
00382       break;
00383
00384     case UART_WAKEUP_ON_TXFIFO_EMPTY:
00385       /* Enable TXFE interrupt */
00386       SET_BIT(huart->Instance->CR1, USART_CR1_TXFEIE);
00387       huart->gState = HAL_UART_STATE_READY;
00388       break;
00389
00390     default:
00391       break;
00392   }
00393
00394   /* Process Unlocked */
00395   __HAL_UNLOCK(huart);
00396
00397   return status;
00398 }
00399
00400
00401 /**
00402   * @brief Enable UART Stop Mode.
00403   * @note  The UART is able to wake up the MCU from Stop mode as long as UART clock is HSI or LSE.
00404   * @param huart: UART handle.
00405   * @retval HAL status
00406   */
00407 HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
00408 {
00409   /* Process Locked */
00410   __HAL_LOCK(huart);
00411
00412   huart->gState = HAL_UART_STATE_BUSY;
00413
00414   /* Set UESM bit */
00415   SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
00416
00417   huart->gState = HAL_UART_STATE_READY;
00418
00419   /* Process Unlocked */
00420   __HAL_UNLOCK(huart);
00421
00422   return HAL_OK;
00423 }
00424
00425 /**
00426   * @brief Disable UART Stop Mode.
00427   * @param huart: UART handle.
00428   * @retval HAL status
00429   */
00430 HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
00431 {
00432   /* Process Locked */
00433   __HAL_LOCK(huart);
00434
00435   huart->gState = HAL_UART_STATE_BUSY;
00436
00437   /* Clear UESM bit */
00438   CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
00439
00440   huart->gState = HAL_UART_STATE_READY;
00441
00442   /* Process Unlocked */
00443   __HAL_UNLOCK(huart);
00444
00445   return HAL_OK;
00446 }
00447
00448 /**
00449   * @brief UART wakeup from Stop mode callback.
00450   * @param huart: UART handle.
00451   * @retval None
00452   */
00453 __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
00454 {
00455   /* Prevent unused argument(s) compilation warning */
00456   UNUSED(huart);
00457
00458   /* NOTE : This function should not be modified, when the callback is needed,
00459             the HAL_UARTEx_WakeupCallback can be implemented in the user file.
00460    */
00461 }
00462
00463 /**
00464   * @}
00465   */
00466
00467 /**
00468   * @}
00469   */
00470
00471 /** @addtogroup UARTEx_Private_Functions
00472   * @{
00473   */
00474
00475 /**
00476   * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
00477   * @param huart: UART handle.
00478   * @param WakeUpSelection: UART wake up from stop mode parameters.
00479   * @retval None
00480   */
00481 static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
00482 {
00483   assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
00484
00485   /* Set the USART address length */
00486   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
00487
00488   /* Set the USART address node */
00489   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
00490 }
00491
00492 /**
00493   * @}
00494   */
00495
00496 #endif /* HAL_UART_MODULE_ENABLED */
00497
00498 /**
00499   * @}
00500   */
00501
00502 /**
00503   * @}
00504   */
00505
00506 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_uart_ex.h Source File

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stm32h7xx_hal_uart_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_uart_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of UART HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_UART_EX_H
00040 #define __STM32H7xx_HAL_UART_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup UARTEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup UARTEx_Exported_Types UARTEx Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  UART wake up from stop mode parameters
00064   */
00065 typedef struct
00066 {
00067   uint32_t WakeUpEvent;        /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF).
00068                                     This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
00069                                     If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
00070                                     be filled up. */
00071
00072   uint16_t AddressLength;      /*!< Specifies whether the address is 4 or 7-bit long.
00073                                     This parameter can be a value of @ref UARTEx_WakeUp_Address_Length.  */
00074
00075   uint8_t Address;             /*!< UART/USART node address (7-bit long max). */
00076 } UART_WakeUpTypeDef;
00077
00078 /**
00079   * @}
00080   */
00081
00082 /* Exported constants --------------------------------------------------------*/
00083 /** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
00084   * @{
00085   */
00086
00087 /** @defgroup UARTEx_Word_Length UART Word Length
00088   * @{
00089   */
00090 #define UART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M1)   /*!< 7-bit long UART frame */
00091 #define UART_WORDLENGTH_8B                  ((uint32_t)0x00000000U)    /*!< 8-bit long UART frame */
00092 #define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M0)   /*!< 9-bit long UART frame */
00093 /**
00094   * @}
00095   */
00096
00097 /** @defgroup UARTEx_WakeUp_Address_Length UART Extended WakeUp Address Length
00098   * @{
00099   */
00100 #define UART_ADDRESS_DETECT_4B              ((uint32_t)0x00000000U)      /*!< 4-bit long wake-up address */
00101 #define UART_ADDRESS_DETECT_7B              ((uint32_t)USART_CR2_ADDM7)  /*!< 7-bit long wake-up address */
00102 /**
00103   * @}
00104   */
00105
00106 /**
00107   * @}
00108   */
00109
00110 /* Exported macros -----------------------------------------------------------*/
00111 /* Exported functions --------------------------------------------------------*/
00112 /** @addtogroup UARTEx_Exported_Functions
00113   * @{
00114   */
00115
00116 /** @addtogroup UARTEx_Exported_Functions_Group1
00117   * @{
00118   */
00119
00120 /* Initialization and de-initialization functions  ****************************/
00121 HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
00122
00123 /**
00124   * @}
00125   */
00126
00127 /* IO operation functions *****************************************************/
00128
00129 /** @addtogroup UARTEx_Exported_Functions_Group3
00130   * @{
00131   */
00132
00133 /* Peripheral Control functions  **********************************************/
00134 HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
00135 HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
00136 HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
00137 HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
00138 void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
00139
00140 /**
00141   * @}
00142   */
00143
00144 /**
00145   * @}
00146   */
00147
00148 /* Private macros ------------------------------------------------------------*/
00149 /** @defgroup UARTEx_Private_Macros UARTEx Private Macros
00150   * @{
00151   */
00152
00153 /** @brief  Report the UART clock source.
00154   * @param  __HANDLE__: specifies the UART Handle.
00155   * @param  __CLOCKSOURCE__: output variable.
00156   * @retval UART clocking source, written in __CLOCKSOURCE__.
00157   */
00158 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00159   do {                                                        \
00160     if((__HANDLE__)->Instance == USART1)                      \
00161     {                                                         \
00162        switch(__HAL_RCC_GET_USART1_SOURCE())                  \
00163        {                                                      \
00164         case RCC_USART1CLKSOURCE_D2PCLK2:                     \
00165           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
00166           break;                                              \
00167         case RCC_USART1CLKSOURCE_PLL2:                        \
00168           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00169           break;                                              \
00170         case RCC_USART1CLKSOURCE_PLL3:                        \
00171           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00172           break;                                              \
00173         case RCC_USART1CLKSOURCE_HSI:                         \
00174           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00175           break;                                              \
00176         case RCC_USART1CLKSOURCE_CSI:                         \
00177           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00178           break;                                              \
00179         case RCC_USART1CLKSOURCE_LSE:                         \
00180           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00181           break;                                              \
00182        }                                                      \
00183     }                                                         \
00184     else if((__HANDLE__)->Instance == USART2)                 \
00185     {                                                         \
00186        switch(__HAL_RCC_GET_USART2_SOURCE())                  \
00187        {                                                      \
00188         case RCC_USART2CLKSOURCE_D2PCLK1:                     \
00189           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
00190           break;                                              \
00191         case RCC_USART2CLKSOURCE_PLL2:                        \
00192           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00193           break;                                              \
00194         case RCC_USART2CLKSOURCE_PLL3:                        \
00195           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00196           break;                                              \
00197         case RCC_USART2CLKSOURCE_HSI:                         \
00198           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00199           break;                                              \
00200         case RCC_USART2CLKSOURCE_CSI:                         \
00201           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00202           break;                                              \
00203         case RCC_USART2CLKSOURCE_LSE:                         \
00204           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00205           break;                                              \
00206        }                                                      \
00207     }                                                         \
00208     else if((__HANDLE__)->Instance == USART3)                 \
00209     {                                                         \
00210        switch(__HAL_RCC_GET_USART3_SOURCE())                  \
00211        {                                                      \
00212         case RCC_USART3CLKSOURCE_D2PCLK1:                     \
00213           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
00214           break;                                              \
00215         case RCC_USART3CLKSOURCE_PLL2:                        \
00216           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00217           break;                                              \
00218         case RCC_USART3CLKSOURCE_PLL3:                        \
00219           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00220           break;                                              \
00221         case RCC_USART3CLKSOURCE_HSI:                         \
00222           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00223           break;                                              \
00224         case RCC_USART3CLKSOURCE_CSI:                         \
00225           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00226           break;                                              \
00227         case RCC_USART3CLKSOURCE_LSE:                         \
00228           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00229           break;                                              \
00230        }                                                      \
00231     }                                                         \
00232     else if((__HANDLE__)->Instance == UART4)                  \
00233     {                                                         \
00234        switch(__HAL_RCC_GET_UART4_SOURCE())                   \
00235        {                                                      \
00236         case RCC_UART4CLKSOURCE_D2PCLK1:                      \
00237           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
00238           break;                                              \
00239         case RCC_UART4CLKSOURCE_PLL2:                         \
00240           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00241           break;                                              \
00242         case RCC_UART4CLKSOURCE_PLL3:                         \
00243           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00244           break;                                              \
00245         case RCC_UART4CLKSOURCE_HSI:                          \
00246           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00247           break;                                              \
00248         case RCC_UART4CLKSOURCE_CSI:                          \
00249           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00250           break;                                              \
00251         case RCC_UART4CLKSOURCE_LSE:                          \
00252           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00253           break;                                              \
00254        }                                                      \
00255     }                                                         \
00256     else if ((__HANDLE__)->Instance == UART5)                 \
00257     {                                                         \
00258        switch(__HAL_RCC_GET_UART5_SOURCE())                   \
00259        {                                                      \
00260         case RCC_UART5CLKSOURCE_D2PCLK1:                      \
00261           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
00262           break;                                              \
00263         case RCC_UART5CLKSOURCE_PLL2:                         \
00264           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00265           break;                                              \
00266         case RCC_UART5CLKSOURCE_PLL3:                         \
00267           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00268           break;                                              \
00269         case RCC_UART5CLKSOURCE_HSI:                          \
00270           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00271           break;                                              \
00272         case RCC_UART5CLKSOURCE_CSI:                          \
00273           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00274           break;                                              \
00275         case RCC_UART5CLKSOURCE_LSE:                          \
00276           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00277           break;                                              \
00278        }                                                      \
00279     }                                                         \
00280     else if((__HANDLE__)->Instance == USART6)                 \
00281     {                                                         \
00282        switch(__HAL_RCC_GET_USART6_SOURCE())                  \
00283        {                                                      \
00284         case RCC_USART6CLKSOURCE_D2PCLK2:                     \
00285           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
00286           break;                                              \
00287         case RCC_USART6CLKSOURCE_PLL2:                        \
00288           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00289           break;                                              \
00290         case RCC_USART6CLKSOURCE_PLL3:                        \
00291           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00292           break;                                              \
00293         case RCC_USART6CLKSOURCE_HSI:                         \
00294           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00295           break;                                              \
00296         case RCC_USART6CLKSOURCE_CSI:                         \
00297           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00298           break;                                              \
00299         case RCC_USART6CLKSOURCE_LSE:                         \
00300           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00301           break;                                              \
00302        }                                                      \
00303     }                                                         \
00304     else if((__HANDLE__)->Instance == UART7)                  \
00305     {                                                         \
00306        switch(__HAL_RCC_GET_UART7_SOURCE())                   \
00307        {                                                      \
00308         case RCC_UART7CLKSOURCE_D2PCLK1:                      \
00309           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
00310           break;                                              \
00311         case RCC_UART7CLKSOURCE_PLL2:                         \
00312           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00313           break;                                              \
00314         case RCC_UART7CLKSOURCE_PLL3:                         \
00315           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00316           break;                                              \
00317         case RCC_UART7CLKSOURCE_HSI:                          \
00318           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00319           break;                                              \
00320         case RCC_UART7CLKSOURCE_CSI:                          \
00321           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00322           break;                                              \
00323         case RCC_UART7CLKSOURCE_LSE:                          \
00324           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00325           break;                                              \
00326        }                                                      \
00327     }                                                         \
00328     else if((__HANDLE__)->Instance == UART8)                  \
00329     {                                                         \
00330        switch(__HAL_RCC_GET_UART8_SOURCE())                   \
00331        {                                                      \
00332         case RCC_UART8CLKSOURCE_D2PCLK1:                      \
00333           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
00334           break;                                              \
00335         case RCC_UART8CLKSOURCE_PLL2:                         \
00336           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00337           break;                                              \
00338         case RCC_UART8CLKSOURCE_PLL3:                         \
00339           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00340           break;                                              \
00341         case RCC_UART8CLKSOURCE_HSI:                          \
00342           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00343           break;                                              \
00344         case RCC_UART8CLKSOURCE_CSI:                          \
00345           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00346           break;                                              \
00347         case RCC_UART8CLKSOURCE_LSE:                          \
00348           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00349           break;                                              \
00350        }                                                      \
00351     }                                                         \
00352     else if((__HANDLE__)->Instance == LPUART1)                \
00353     {                                                         \
00354        switch(__HAL_RCC_GET_LPUART1_SOURCE())                 \
00355        {                                                      \
00356         case RCC_LPUART1CLKSOURCE_D3PCLK1:                    \
00357           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D3PCLK1;       \
00358           break;                                              \
00359         case RCC_LPUART1CLKSOURCE_PLL2:                       \
00360           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
00361           break;                                              \
00362         case RCC_LPUART1CLKSOURCE_PLL3:                       \
00363           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
00364           break;                                              \
00365         case RCC_LPUART1CLKSOURCE_HSI:                        \
00366           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00367           break;                                              \
00368         case RCC_LPUART1CLKSOURCE_CSI:                        \
00369           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
00370           break;                                              \
00371         case RCC_LPUART1CLKSOURCE_LSE:                        \
00372           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00373           break;                                              \
00374        }                                                      \
00375     }                                                         \
00376   } while(0)
00377
00378 /** @brief  Report the UART mask to apply to retrieve the received data
00379   *         according to the word length and to the parity bits activation.
00380   * @note   If PCE = 1, the parity bit is not included in the data extracted
00381   *         by the reception API().
00382   *         This masking operation is not carried out in the case of
00383   *         DMA transfers.
00384   * @param  __HANDLE__: specifies the UART Handle.
00385   * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
00386   */
00387 #define UART_MASK_COMPUTATION(__HANDLE__)                             \
00388   do {                                                                \
00389   if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)            \
00390   {                                                                   \
00391      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
00392      {                                                                \
00393         (__HANDLE__)->Mask = 0x01FF ;                                 \
00394      }                                                                \
00395      else                                                             \
00396      {                                                                \
00397         (__HANDLE__)->Mask = 0x00FF ;                                 \
00398      }                                                                \
00399   }                                                                   \
00400   else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)       \
00401   {                                                                   \
00402      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
00403      {                                                                \
00404         (__HANDLE__)->Mask = 0x00FF ;                                 \
00405      }                                                                \
00406      else                                                             \
00407      {                                                                \
00408         (__HANDLE__)->Mask = 0x007F ;                                 \
00409      }                                                                \
00410   }                                                                   \
00411   else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)       \
00412   {                                                                   \
00413      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
00414      {                                                                \
00415         (__HANDLE__)->Mask = 0x007F ;                                 \
00416      }                                                                \
00417      else                                                             \
00418      {                                                                \
00419         (__HANDLE__)->Mask = 0x003F ;                                 \
00420      }                                                                \
00421   }                                                                   \
00422 } while(0)
00423
00424
00425 /**
00426   * @brief Ensure that UART frame length is valid.
00427   * @param __LENGTH__: UART frame length.
00428   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00429   */
00430 #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
00431                                          ((__LENGTH__) == UART_WORDLENGTH_8B) || \
00432                                          ((__LENGTH__) == UART_WORDLENGTH_9B))
00433
00434 /**
00435   * @brief Ensure that UART wake-up address length is valid.
00436   * @param __ADDRESS__: UART wake-up address length.
00437   * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
00438   */
00439 #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
00440                                                    ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
00441
00442 /**
00443   * @}
00444   */
00445
00446 /* Private functions ---------------------------------------------------------*/
00447 /* Private constants ---------------------------------------------------------*/
00448 /**
00449   * @}
00450   */
00451
00452 /**
00453   * @}
00454   */
00455
00456 #ifdef __cplusplus
00457 }
00458 #endif
00459
00460 #endif /* __STM32H7xx_HAL_UART_EX_H */
00461
00462 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_usart.c Source File

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stm32h7xx_hal_usart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_usart.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   USART HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
00010   *          Peripheral (USART).
00011   *           + Initialization and de-initialization functions
00012   *           + IO operation functions
00013   *           + Peripheral Control functions
00014   *           + Peripheral State and Error functions
00015   *
00016   @verbatim
00017  ===============================================================================
00018                         ##### How to use this driver #####
00019  ===============================================================================
00020     [..]
00021       The USART HAL driver can be used as follows:
00022
00023       (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
00024       (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
00025           (++) Enable the USARTx interface clock.
00026           (++) USART pins configuration:
00027             (+++) Enable the clock for the USART GPIOs.
00028             (+++) Configure these USART pins as alternate function pull-up.
00029           (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
00030                 HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
00031             (+++) Configure the USARTx interrupt priority.
00032             (+++) Enable the NVIC USART IRQ handle.
00033             (++) USART interrupts handling:
00034               -@@-   The specific USART interrupts (Transmission complete interrupt,
00035                   RXNE interrupt and Error Interrupts) will be managed using the macros
00036                   __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
00037           (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
00038                HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
00039             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00040             (+++) Enable the DMAx interface clock.
00041             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00042             (+++) Configure the DMA Tx/Rx channel.
00043             (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
00044             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00045
00046       (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
00047           flow control and Mode (Receiver/Transmitter) in the husart handle Init structure.
00048
00049       (#) Initialize the USART registers by calling the HAL_USART_Init() API:
00050           (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00051                by calling the customized HAL_USART_MspInit(&husart) API.
00052
00053     [..]
00054      (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
00055         HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
00056         HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
00057
00058   @endverbatim
00059   ******************************************************************************
00060   * @attention
00061   *
00062   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00063   *
00064   * Redistribution and use in source and binary forms, with or without modification,
00065   * are permitted provided that the following conditions are met:
00066   *   1. Redistributions of source code must retain the above copyright notice,
00067   *      this list of conditions and the following disclaimer.
00068   *   2. Redistributions in binary form must reproduce the above copyright notice,
00069   *      this list of conditions and the following disclaimer in the documentation
00070   *      and/or other materials provided with the distribution.
00071   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00072   *      may be used to endorse or promote products derived from this software
00073   *      without specific prior written permission.
00074   *
00075   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00076   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00077   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00078   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00079   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00080   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00081   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00082   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00083   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00084   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00085   *
00086   ******************************************************************************
00087   */
00088
00089 /* Includes ------------------------------------------------------------------*/
00090 #include "stm32h7xx_hal.h"
00091
00092 /** @addtogroup STM32H7xx_HAL_Driver
00093   * @{
00094   */
00095
00096 /** @defgroup USART USART
00097   * @brief HAL USART Synchronous module driver
00098   * @{
00099   */
00100
00101 #ifdef HAL_USART_MODULE_ENABLED
00102
00103 /* Private typedef -----------------------------------------------------------*/
00104 /* Private define ------------------------------------------------------------*/
00105 /** @defgroup USART_Private_Constants USART Private Constants
00106   * @{
00107   */
00108 #define USART_DUMMY_DATA          ((uint16_t) 0xFFFF)           /*!< USART transmitted dummy data                     */
00109 #define USART_TEACK_REACK_TIMEOUT ((uint32_t) 1000)             /*!< USART TX or RX enable acknowledge time-out value */
00110 #define USART_CR1_FIELDS          ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
00111                                               USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8|\
00112                                               USART_CR1_FIFOEN ))                       /*!< USART CR1 fields of parameters set by USART_SetConfig API */
00113 #define USART_CR2_FIELDS          ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL |USART_CR2_DIS_NSS|\
00114                                               USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP|\
00115                                               USART_CR2_SLVEN))                         /*!< USART CR2 fields of parameters set by USART_SetConfig API */
00116 #define USART_CR3_FIELDS          ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))  /*!< USART CR3 fields of parameters set by USART_SetConfig API */
00117
00118 /**
00119   * @}
00120   */
00121
00122 /* Private macros ------------------------------------------------------------*/
00123 /* Private variables ---------------------------------------------------------*/
00124 /* Private function prototypes -----------------------------------------------*/
00125 /** @addtogroup USART_Private_Functions
00126   * @{
00127   */
00128 static void USART_EndTransfer(USART_HandleTypeDef *husart);
00129 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00130 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00131 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00132 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00133 static void USART_DMAError(DMA_HandleTypeDef *hdma);
00134 static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00135 static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00136 static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00137 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
00138 static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
00139 static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
00140 static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
00141 static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
00142 static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
00143 static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
00144 /**
00145   * @}
00146   */
00147
00148 /* Exported functions --------------------------------------------------------*/
00149
00150 /** @defgroup USART_Exported_Functions USART Exported Functions
00151   * @{
00152   */
00153
00154 /** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
00155   *  @brief    Initialization and Configuration functions
00156   *
00157 @verbatim
00158  ===============================================================================
00159             ##### Initialization and Configuration functions #####
00160  ===============================================================================
00161     [..]
00162     This subsection provides a set of functions allowing to initialize the USART
00163     in asynchronous and in synchronous modes.
00164       (+) For the asynchronous mode only these parameters can be configured:
00165         (++) Baud Rate
00166         (++) Word Length
00167         (++) Stop Bit
00168         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00169              in the data register is transmitted but is changed by the parity bit.
00170         (++) USART polarity
00171         (++) USART phase
00172         (++) USART LastBit
00173         (++) Receiver/transmitter modes
00174
00175     [..]
00176     The HAL_USART_Init() function follows the USART  synchronous configuration
00177     procedure (details for the procedure are available in reference manual).
00178
00179 @endverbatim
00180
00181   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00182   8-bit or 9-bit), the possible USART formats are listed in the
00183   following table.
00184
00185     Table 1. USART frame format.
00186     +-----------------------------------------------------------------------+
00187     |  M1 bit |  M0 bit |  PCE bit  |            USART frame                |
00188     |---------|---------|-----------|---------------------------------------|
00189     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00190     |---------|---------|-----------|---------------------------------------|
00191     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00192     |---------|---------|-----------|---------------------------------------|
00193     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00194     |---------|---------|-----------|---------------------------------------|
00195     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00196     |---------|---------|-----------|---------------------------------------|
00197     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00198     |---------|---------|-----------|---------------------------------------|
00199     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00200     +-----------------------------------------------------------------------+
00201
00202   * @{
00203   */
00204
00205 /**
00206   * @brief  Initialize the USART mode according to the specified
00207   *         parameters in the USART_InitTypeDef and initialize the associated handle.
00208   * @param husart: USART handle.
00209   * @retval HAL status
00210   */
00211 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
00212 {
00213   /* Check the USART handle allocation */
00214   if(husart == NULL)
00215   {
00216     return HAL_ERROR;
00217   }
00218
00219   /* Check the parameters */
00220   assert_param(IS_USART_INSTANCE(husart->Instance));
00221
00222   if(husart->State == HAL_USART_STATE_RESET)
00223   {
00224     /* Allocate lock resource and initialize it */
00225     husart->Lock = HAL_UNLOCKED;
00226
00227     /* Init the low level hardware : GPIO, CLOCK */
00228     HAL_USART_MspInit(husart);
00229   }
00230
00231   husart->State = HAL_USART_STATE_BUSY;
00232
00233   /* Disable the Peripheral */
00234   __HAL_USART_DISABLE(husart);
00235
00236   /* Set the Usart Communication parameters */
00237   if (USART_SetConfig(husart) == HAL_ERROR)
00238   {
00239     return HAL_ERROR;
00240   }
00241
00242   /* In Synchronous mode, the following bits must be kept cleared:
00243   - LINEN bit in the USART_CR2 register
00244   - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
00245   CLEAR_BIT(husart->Instance->CR2, USART_CR2_LINEN);
00246   CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
00247
00248   /* In Synchronous Slave mode, the following bits must be kept cleared:
00249   - CLKEN bits in the USART_CR2 register, */
00250   if (husart->Init.SlaveMode)
00251   {
00252     CLEAR_BIT(husart->Instance->CR2, USART_CR2_CLKEN);
00253   }
00254
00255   /* Enable the Peripheral */
00256   __HAL_USART_ENABLE(husart);
00257
00258   /* TEACK and/or REACK to check before moving husart->State to Ready */
00259   return (USART_CheckIdleState(husart));
00260 }
00261
00262 /**
00263   * @brief DeInitialize the USART peripheral.
00264   * @param husart: USART handle.
00265   * @retval HAL status
00266   */
00267 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
00268 {
00269   /* Check the USART handle allocation */
00270   if(husart == NULL)
00271   {
00272     return HAL_ERROR;
00273   }
00274
00275   /* Check the parameters */
00276   assert_param(IS_USART_INSTANCE(husart->Instance));
00277
00278   husart->State = HAL_USART_STATE_BUSY;
00279
00280   husart->Instance->CR1 = 0x0U;
00281   husart->Instance->CR2 = 0x0U;
00282   husart->Instance->CR3 = 0x0U;
00283
00284   /* DeInit the low level hardware */
00285   HAL_USART_MspDeInit(husart);
00286
00287   husart->ErrorCode = HAL_USART_ERROR_NONE;
00288   husart->State = HAL_USART_STATE_RESET;
00289
00290   /* Process Unlock */
00291   __HAL_UNLOCK(husart);
00292
00293   return HAL_OK;
00294 }
00295
00296 /**
00297   * @brief Initialize the USART MSP.
00298   * @param husart: USART handle.
00299   * @retval None
00300   */
00301 __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
00302 {
00303   /* Prevent unused argument(s) compilation warning */
00304   UNUSED(husart);
00305
00306   /* NOTE : This function should not be modified, when the callback is needed,
00307             the HAL_USART_MspInit can be implemented in the user file
00308    */
00309 }
00310
00311 /**
00312   * @brief DeInitialize the USART MSP.
00313   * @param husart: USART handle.
00314   * @retval None
00315   */
00316 __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
00317 {
00318   /* Prevent unused argument(s) compilation warning */
00319   UNUSED(husart);
00320
00321   /* NOTE : This function should not be modified, when the callback is needed,
00322             the HAL_USART_MspDeInit can be implemented in the user file
00323    */
00324 }
00325
00326 /**
00327   * @}
00328   */
00329
00330 /** @defgroup USART_Exported_Functions_Group2 IO operation functions
00331   *  @brief   USART Transmit and Receive functions
00332   *
00333 @verbatim
00334  ===============================================================================
00335                       ##### IO operation functions #####
00336  ===============================================================================
00337     [..] This subsection provides a set of functions allowing to manage the USART synchronous
00338     data transfers.
00339
00340     [..] The USART supports master mode only: it cannot receive or send data related to an input
00341          clock (SCLK is always an output).
00342
00343     (#) There are two modes of transfer:
00344        (++) Blocking mode: The communication is performed in polling mode.
00345             The HAL status of all data processing is returned by the same function
00346             after finishing transfer.
00347        (++) No-Blocking mode: The communication is performed using Interrupts
00348            or DMA, These API's return the HAL status.
00349            The end of the data processing will be indicated through the
00350            dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
00351            using DMA mode.
00352            The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
00353            will be executed respectively at the end of the transmit or Receive process
00354            The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
00355
00356     (#) Blocking mode API's are :
00357         (++) HAL_USART_Transmit()in simplex mode
00358         (++) HAL_USART_Receive() in full duplex receive only
00359         (++) HAL_USART_TransmitReceive() in full duplex mode
00360
00361     (#) Non-Blocking mode API's with Interrupt are :
00362         (++) HAL_USART_Transmit_IT()in simplex mode
00363         (++) HAL_USART_Receive_IT() in full duplex receive only
00364         (++) HAL_USART_TransmitReceive_IT()in full duplex mode
00365         (++) HAL_USART_IRQHandler()
00366
00367     (#) No-Blocking mode API's  with DMA are :
00368         (++) HAL_USART_Transmit_DMA()in simplex mode
00369         (++) HAL_USART_Receive_DMA() in full duplex receive only
00370         (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
00371         (++) HAL_USART_DMAPause()
00372         (++) HAL_USART_DMAResume()
00373         (++) HAL_USART_DMAStop()
00374
00375     (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
00376         (++) HAL_USART_TxCpltCallback()
00377         (++) HAL_USART_RxCpltCallback()
00378         (++) HAL_USART_TxHalfCpltCallback()
00379         (++) HAL_USART_RxHalfCpltCallback()
00380         (++) HAL_USART_ErrorCallback()
00381         (++) HAL_USART_TxRxCpltCallback()
00382
00383     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00384         (+) HAL_USART_Abort()
00385         (+) HAL_USART_Abort_IT()
00386
00387     (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
00388         (+) HAL_USART_AbortCpltCallback()
00389
00390     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00391         Errors are handled as follows :
00392        (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00393            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
00394            Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
00395            and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
00396            If user wants to abort it, Abort services should be called by user.
00397        (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00398            This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
00399            Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
00400
00401 @endverbatim
00402   * @{
00403   */
00404
00405 /**
00406   * @brief  Simplex send an amount of data in blocking mode.
00407   * @param husart: USART handle.
00408   * @param pTxData: Pointer to data buffer.
00409   * @param Size: Amount of data to be sent.
00410   * @param Timeout: Timeout duration.
00411   * @retval HAL status
00412   */
00413 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
00414 {
00415   uint16_t* tmp;
00416   uint32_t tickstart = 0U;
00417
00418   if(husart->State == HAL_USART_STATE_READY)
00419   {
00420     if((pTxData == NULL) || (Size == 0U))
00421     {
00422       return  HAL_ERROR;
00423     }
00424
00425     /* Process Locked */
00426     __HAL_LOCK(husart);
00427
00428     husart->ErrorCode = HAL_USART_ERROR_NONE;
00429     husart->State = HAL_USART_STATE_BUSY_TX;
00430
00431     /* Init tickstart for timeout managment */
00432     tickstart = HAL_GetTick();
00433
00434     husart->TxXferSize = Size;
00435     husart->TxXferCount = Size;
00436
00437     /* Check the remaining data to be sent */
00438     while(husart->TxXferCount > 0U)
00439     {
00440       husart->TxXferCount--;
00441       if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00442       {
00443         return HAL_TIMEOUT;
00444       }
00445       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00446       {
00447         tmp = (uint16_t*) pTxData;
00448         husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
00449         pTxData += 2U;
00450       }
00451       else
00452       {
00453         husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFFU);
00454       }
00455     }
00456
00457     if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00458     {
00459       return HAL_TIMEOUT;
00460     }
00461
00462     /* At end of Tx process, restore husart->State to Ready */
00463     husart->State = HAL_USART_STATE_READY;
00464
00465     /* Process Unlocked */
00466     __HAL_UNLOCK(husart);
00467
00468     return HAL_OK;
00469   }
00470   else
00471   {
00472     return HAL_BUSY;
00473   }
00474 }
00475
00476 /**
00477   * @brief Receive an amount of data in blocking mode.
00478   * @note To receive synchronous data, dummy data are simultaneously transmitted.
00479   * @param husart: USART handle.
00480   * @param pRxData: Pointer to data buffer.
00481   * @param Size: Amount of data to be received.
00482   * @param Timeout: Timeout duration.
00483   * @retval HAL status
00484   */
00485 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
00486 {
00487   uint16_t* tmp;
00488   uint16_t uhMask;
00489   uint32_t tickstart = 0U;
00490
00491   if(husart->State == HAL_USART_STATE_READY)
00492   {
00493     if((pRxData == NULL) || (Size == 0U))
00494     {
00495       return  HAL_ERROR;
00496     }
00497     /* Process Locked */
00498     __HAL_LOCK(husart);
00499
00500     husart->ErrorCode = HAL_USART_ERROR_NONE;
00501     husart->State = HAL_USART_STATE_BUSY_RX;
00502
00503     /* Init tickstart for timeout managment */
00504     tickstart = HAL_GetTick();
00505
00506     husart->RxXferSize = Size;
00507     husart->RxXferCount = Size;
00508
00509     /* Computation of USART mask to apply to RDR register */
00510     USART_MASK_COMPUTATION(husart);
00511     uhMask = husart->Mask;
00512
00513     /* as long as data have to be received */
00514     while(husart->RxXferCount > 0U)
00515     {
00516       husart->RxXferCount--;
00517
00518       if (husart->Init.SlaveMode == USART_SLAVEMODE_DISABLE)
00519       {
00520         /* Wait until TC flag is set to send dummy byte in order to generate the
00521          * clock for the slave to send data.
00522          * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
00523          * can be written for all the cases. */
00524         if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00525         {
00526           return HAL_TIMEOUT;
00527         }
00528         husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FFU);
00529       }
00530
00531       /* Wait for RXNE Flag */
00532       if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00533       {
00534         return HAL_TIMEOUT;
00535       }
00536
00537       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00538       {
00539         tmp = (uint16_t*) pRxData ;
00540         *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
00541         pRxData +=2U;
00542       }
00543       else
00544       {
00545         *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
00546       }
00547     }
00548
00549     /* At end of Rx process, restore husart->State to Ready */
00550     husart->State = HAL_USART_STATE_READY;
00551
00552     /* Process Unlocked */
00553     __HAL_UNLOCK(husart);
00554
00555     return HAL_OK;
00556   }
00557   else
00558   {
00559     return HAL_BUSY;
00560   }
00561 }
00562
00563 /**
00564   * @brief Full-Duplex Send and Receive an amount of data in blocking mode.
00565   * @param husart: USART handle.
00566   * @param pTxData: pointer to TX data buffer.
00567   * @param pRxData: pointer to RX data buffer.
00568   * @param Size: amount of data to be sent (same amount to be received).
00569   * @param Timeout: Timeout duration.
00570   * @retval HAL status
00571   */
00572 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
00573 {
00574   uint16_t* tmp;
00575   uint16_t uhMask;
00576   uint32_t tickstart = 0U;
00577
00578   if(husart->State == HAL_USART_STATE_READY)
00579   {
00580     if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
00581     {
00582       return  HAL_ERROR;
00583     }
00584     /* Process Locked */
00585     __HAL_LOCK(husart);
00586
00587     husart->ErrorCode = HAL_USART_ERROR_NONE;
00588     husart->State = HAL_USART_STATE_BUSY_RX;
00589
00590     /* Init tickstart for timeout managment */
00591     tickstart = HAL_GetTick();
00592
00593     husart->RxXferSize = Size;
00594     husart->TxXferSize = Size;
00595     husart->TxXferCount = Size;
00596     husart->RxXferCount = Size;
00597
00598     /* Computation of USART mask to apply to RDR register */
00599     USART_MASK_COMPUTATION(husart);
00600     uhMask = husart->Mask;
00601
00602     if (husart->Init.SlaveMode == USART_SLAVEMODE_ENABLE)
00603     {
00604       husart->TxXferCount--;
00605
00606       /* Wait until TXE flag is set to send data */
00607       if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00608       {
00609         return HAL_TIMEOUT;
00610       }
00611       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00612       {
00613         tmp = (uint16_t*) pTxData;
00614         husart->Instance->TDR = (*tmp & uhMask);
00615         pTxData += 2U;
00616       }
00617       else
00618       {
00619         husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);
00620       }
00621     }
00622
00623     /* Check the remain data to be sent */
00624     while(husart->TxXferCount > 0U)
00625     {
00626       husart->TxXferCount--;
00627       husart->RxXferCount--;
00628
00629       /* Wait until TXE flag is set to send data */
00630       if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00631       {
00632         return HAL_TIMEOUT;
00633       }
00634
00635       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00636       {
00637         tmp = (uint16_t*) pTxData;
00638         husart->Instance->TDR = (*tmp & uhMask);
00639         pTxData += 2U;
00640       }
00641       else
00642       {
00643         husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);
00644       }
00645
00646       /* Wait for RXNE Flag */
00647       if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00648       {
00649         return HAL_TIMEOUT;
00650       }
00651
00652       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00653       {
00654         tmp = (uint16_t*) pRxData ;
00655         *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
00656         pRxData +=2U;
00657       }
00658       else
00659       {
00660         *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
00661       }
00662     }
00663
00664     if (husart->Init.SlaveMode == USART_SLAVEMODE_ENABLE)
00665     {
00666       husart->RxXferCount--;
00667
00668       /* Wait for RXNE Flag */
00669       if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00670       {
00671         return HAL_TIMEOUT;
00672       }
00673
00674       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00675       {
00676         tmp = (uint16_t*) pRxData ;
00677         *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
00678         pRxData +=2U;
00679       }
00680       else
00681       {
00682         *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
00683       }
00684     }
00685
00686     /* At end of TxRx process, restore husart->State to Ready */
00687     husart->State = HAL_USART_STATE_READY;
00688
00689     /* Process Unlocked */
00690     __HAL_UNLOCK(husart);
00691
00692     return HAL_OK;
00693   }
00694   else
00695   {
00696     return HAL_BUSY;
00697   }
00698 }
00699
00700 /**
00701   * @brief  Send an amount of data in interrupt mode.
00702   * @param husart: USART handle.
00703   * @param pTxData: pointer to data buffer.
00704   * @param Size: amount of data to be sent.
00705   * @retval HAL status
00706   */
00707 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
00708 {
00709   if(husart->State == HAL_USART_STATE_READY)
00710   {
00711     if((pTxData == NULL ) || (Size == 0U))
00712     {
00713       return HAL_ERROR;
00714     }
00715
00716     /* Process Locked */
00717     __HAL_LOCK(husart);
00718
00719     husart->pTxBuffPtr = pTxData;
00720     husart->TxXferSize = Size;
00721     husart->TxXferCount = Size;
00722
00723     husart->ErrorCode = HAL_USART_ERROR_NONE;
00724     husart->State = HAL_USART_STATE_BUSY_TX;
00725
00726     /* The USART Error Interrupts: (Frame error, noise error, overrun error)
00727     are not managed by the USART Transmit Process to avoid the overrun interrupt
00728     when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
00729     to benefit for the frame error and noise interrupts the usart mode should be
00730     configured only for transmit "USART_MODE_TX" */
00731
00732     /* Process Unlocked */
00733     __HAL_UNLOCK(husart);
00734
00735     /* Enable the TX FIFO threshold interrupt (if FIFO mode is enabled) or
00736        Transmit Data Register Empty interrupt (if FIFO mode is Disabled).
00737     */
00738     if (READ_BIT(husart->Instance->CR1, USART_CR1_FIFOEN) != RESET)
00739     {
00740       SET_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
00741     }
00742     else
00743     {
00744       SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
00745     }
00746
00747     return HAL_OK;
00748   }
00749   else
00750   {
00751     return HAL_BUSY;
00752   }
00753 }
00754
00755 /**
00756   * @brief Receive an amount of data in interrupt mode.
00757   * @note  To receive synchronous data, dummy data are simultaneously transmitted.
00758   * @param husart: USART handle.
00759   * @param pRxData: pointer to data buffer.
00760   * @param Size: amount of data to be received.
00761   * @retval HAL status
00762   */
00763 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
00764 {
00765   if(husart->State == HAL_USART_STATE_READY)
00766   {
00767     if((pRxData == NULL ) || (Size == 0U))
00768     {
00769       return HAL_ERROR;
00770     }
00771
00772     /* Process Locked */
00773     __HAL_LOCK(husart);
00774
00775     husart->pRxBuffPtr = pRxData;
00776     husart->RxXferSize = Size;
00777     husart->RxXferCount = Size;
00778
00779     USART_MASK_COMPUTATION(husart);
00780
00781     husart->ErrorCode = HAL_USART_ERROR_NONE;
00782     husart->State = HAL_USART_STATE_BUSY_RX;
00783
00784     /* Process Unlocked */
00785     __HAL_UNLOCK(husart);
00786
00787     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
00788     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
00789
00790     /* Enable the USART Parity Error interupt and RX FIFO Threshold interrupt
00791        (if FIFO mode is enabled) or Data Register Not Empty interrupt
00792        (if FIFO mode is disabled).
00793     */
00794     if (READ_BIT(husart->Instance->CR1, USART_CR1_FIFOEN) != RESET)
00795     {
00796       SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
00797       SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
00798     }
00799     else
00800     {
00801       SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
00802     }
00803
00804     if (husart->Init.SlaveMode == USART_SLAVEMODE_DISABLE)
00805     {
00806       /* Send dummy byte in order to generate the clock for the Slave to send the next data */
00807       if(husart->Init.WordLength == USART_WORDLENGTH_9B)
00808       {
00809         husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x01FFU);
00810       }
00811       else
00812       {
00813         husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
00814       }
00815     }
00816
00817     return HAL_OK;
00818   }
00819   else
00820   {
00821     return HAL_BUSY;
00822   }
00823 }
00824
00825 /**
00826   * @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
00827   * @param husart: USART handle.
00828   * @param pTxData: pointer to TX data buffer.
00829   * @param pRxData: pointer to RX data buffer.
00830   * @param Size: amount of data to be sent (same amount to be received).
00831   * @retval HAL status
00832   */
00833 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size)
00834 {
00835
00836   if(husart->State == HAL_USART_STATE_READY)
00837   {
00838     if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
00839     {
00840       return HAL_ERROR;
00841     }
00842     /* Process Locked */
00843     __HAL_LOCK(husart);
00844
00845     husart->pRxBuffPtr = pRxData;
00846     husart->RxXferSize = Size;
00847     husart->RxXferCount = Size;
00848     husart->pTxBuffPtr = pTxData;
00849     husart->TxXferSize = Size;
00850     husart->TxXferCount = Size;
00851
00852     /* Computation of USART mask to apply to RDR register */
00853     USART_MASK_COMPUTATION(husart);
00854
00855     husart->ErrorCode = HAL_USART_ERROR_NONE;
00856     husart->State = HAL_USART_STATE_BUSY_TX_RX;
00857
00858     /* Process Unlocked */
00859     __HAL_UNLOCK(husart);
00860
00861     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
00862     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
00863
00864     /* Enable the USART Parity Error interupt and RX/TX FIFO Threshold interrupts
00865        (if FIFO mode is enabled) or Receive Data Register Not Empty and Transmit
00866        Data Register Empty Interrupts (if FIFO mode is disabled).
00867     */
00868     if (READ_BIT(husart->Instance->CR1, USART_CR1_FIFOEN) != RESET)
00869     {
00870       SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
00871       SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE | USART_CR3_TXFTIE);
00872     }
00873     else
00874     {
00875       SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE | USART_CR1_TXEIE);
00876     }
00877
00878     return HAL_OK;
00879   }
00880   else
00881   {
00882     return HAL_BUSY;
00883   }
00884
00885 }
00886
00887 /**
00888   * @brief Send an amount of data in DMA mode.
00889   * @param husart: USART handle.
00890   * @param pTxData: pointer to data buffer.
00891   * @param Size: amount of data to be sent.
00892   * @retval HAL status
00893   */
00894 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
00895 {
00896   uint32_t *tmp;
00897
00898   if(husart->State == HAL_USART_STATE_READY)
00899   {
00900     if((pTxData == NULL ) || (Size == 0U))
00901     {
00902       return HAL_ERROR;
00903     }
00904     /* Process Locked */
00905     __HAL_LOCK(husart);
00906
00907     husart->pTxBuffPtr = pTxData;
00908     husart->TxXferSize = Size;
00909     husart->TxXferCount = Size;
00910
00911     husart->ErrorCode = HAL_USART_ERROR_NONE;
00912     husart->State = HAL_USART_STATE_BUSY_TX;
00913
00914     /* Set the USART DMA transfer complete callback */
00915     husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
00916
00917     /* Set the USART DMA Half transfer complete callback */
00918     husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
00919
00920     /* Set the DMA error callback */
00921     husart->hdmatx->XferErrorCallback = USART_DMAError;
00922
00923     /* Enable the USART transmit DMA channel */
00924     tmp = (uint32_t*)&pTxData;
00925     HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
00926
00927     /* Clear the TC flag in the ICR register */
00928     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
00929
00930     /* Process Unlocked */
00931     __HAL_UNLOCK(husart);
00932
00933     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00934        in the USART CR3 register */
00935     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
00936
00937     return HAL_OK;
00938   }
00939   else
00940   {
00941     return HAL_BUSY;
00942   }
00943 }
00944
00945 /**
00946   * @brief Receive an amount of data in DMA mode.
00947   * @param husart: USART handle.
00948   * @param pRxData: pointer to data buffer.
00949   * @param Size: amount of data to be received.
00950   * @note   When the USART parity is enabled (PCE = 1), the received data contain
00951   *         the parity bit (MSB position).
00952   * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
00953   * @retval HAL status
00954   */
00955 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
00956 {
00957   uint32_t *tmp;
00958
00959   /* Check that a Rx process is not already ongoing */
00960   if(husart->State == HAL_USART_STATE_READY)
00961   {
00962     if((pRxData == NULL ) || (Size == 0U))
00963     {
00964       return HAL_ERROR;
00965     }
00966
00967     /* Process Locked */
00968     __HAL_LOCK(husart);
00969
00970     husart->pRxBuffPtr = pRxData;
00971     husart->RxXferSize = Size;
00972     husart->pTxBuffPtr = pRxData;
00973     husart->TxXferSize = Size;
00974
00975     husart->ErrorCode = HAL_USART_ERROR_NONE;
00976     husart->State = HAL_USART_STATE_BUSY_RX;
00977
00978     /* Set the USART DMA Rx transfer complete callback */
00979     husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
00980
00981     /* Set the USART DMA Half transfer complete callback */
00982     husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
00983
00984     /* Set the USART DMA Rx transfer error callback */
00985     husart->hdmarx->XferErrorCallback = USART_DMAError;
00986
00987     /* Enable the USART receive DMA channel */
00988     tmp = (uint32_t*)&pRxData;
00989     HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
00990
00991     if (husart->Init.SlaveMode == USART_SLAVEMODE_DISABLE)
00992     {
00993       /* Enable the USART transmit DMA channel: the transmit channel is used in order
00994          to generate in the non-blocking mode the clock to the slave device,
00995          this mode isn't a simplex receive mode but a full-duplex receive mode */
00996       /* Set the USART DMA Tx Complete and Error callback to Null */
00997       husart->hdmatx->XferErrorCallback = NULL;
00998       husart->hdmatx->XferHalfCpltCallback = NULL;
00999       husart->hdmatx->XferCpltCallback = NULL;
01000       HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
01001     }
01002
01003     /* Process Unlocked */
01004     __HAL_UNLOCK(husart);
01005
01006     /* Enable the USART Parity Error Interrupt */
01007     SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01008
01009     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01010     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01011
01012     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01013        in the USART CR3 register */
01014     SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01015
01016     if (husart->Init.SlaveMode == USART_SLAVEMODE_DISABLE)
01017     {
01018       /* Enable the DMA transfer for transmit request by setting the DMAT bit
01019          in the USART CR3 register */
01020       SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01021     }
01022
01023     return HAL_OK;
01024   }
01025   else
01026   {
01027     return HAL_BUSY;
01028   }
01029 }
01030
01031 /**
01032   * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
01033   * @param husart: USART handle.
01034   * @param pTxData: pointer to TX data buffer.
01035   * @param pRxData: pointer to RX data buffer.
01036   * @param Size: amount of data to be received/sent.
01037   * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
01038   * @retval HAL status
01039   */
01040 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
01041 {
01042   uint32_t *tmp;
01043
01044   if(husart->State == HAL_USART_STATE_READY)
01045   {
01046     if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01047     {
01048       return HAL_ERROR;
01049     }
01050     /* Process Locked */
01051     __HAL_LOCK(husart);
01052
01053     husart->pRxBuffPtr = pRxData;
01054     husart->RxXferSize = Size;
01055     husart->pTxBuffPtr = pTxData;
01056     husart->TxXferSize = Size;
01057
01058     husart->ErrorCode = HAL_USART_ERROR_NONE;
01059     husart->State = HAL_USART_STATE_BUSY_TX_RX;
01060
01061     /* Set the USART DMA Rx transfer complete callback */
01062     husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
01063
01064     /* Set the USART DMA Half transfer complete callback */
01065     husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
01066
01067     /* Set the USART DMA Tx transfer complete callback */
01068     husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
01069
01070     /* Set the USART DMA Half transfer complete callback */
01071     husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
01072
01073     /* Set the USART DMA Tx transfer error callback */
01074     husart->hdmatx->XferErrorCallback = USART_DMAError;
01075
01076     /* Set the USART DMA Rx transfer error callback */
01077     husart->hdmarx->XferErrorCallback = USART_DMAError;
01078
01079     /* Enable the USART receive DMA channel */
01080     tmp = (uint32_t*)&pRxData;
01081     HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
01082
01083     /* Enable the USART transmit DMA channel */
01084     tmp = (uint32_t*)&pTxData;
01085     HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
01086
01087     /* Process Unlocked */
01088     __HAL_UNLOCK(husart);
01089
01090     /* Enable the USART Parity Error Interrupt */
01091     SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01092
01093     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01094     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01095
01096     /* Clear the TC flag in the ICR register */
01097     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
01098
01099     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01100        in the USART CR3 register */
01101     SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01102
01103     /* Enable the DMA transfer for transmit request by setting the DMAT bit
01104        in the USART CR3 register */
01105     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01106
01107     return HAL_OK;
01108   }
01109   else
01110   {
01111     return HAL_BUSY;
01112   }
01113 }
01114
01115 /**
01116   * @brief Pause the DMA Transfer.
01117   * @param husart: USART handle.
01118   * @retval HAL status
01119   */
01120 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
01121 {
01122   /* Process Locked */
01123   __HAL_LOCK(husart);
01124
01125   if( (husart->State == HAL_USART_STATE_BUSY_TX) &&
01126       (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))
01127   {
01128     /* Disable the USART DMA Tx request */
01129     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01130   }
01131   else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
01132            (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
01133   {
01134     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01135     {
01136       /* Disable the USART DMA Tx request */
01137       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01138     }
01139     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01140     {
01141       /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01142       CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01143       CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
01144
01145       /* Disable the USART DMA Rx request */
01146       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01147     }
01148   }
01149
01150   /* Process Unlocked */
01151   __HAL_UNLOCK(husart);
01152
01153   return HAL_OK;
01154 }
01155
01156 /**
01157   * @brief Resume the DMA Transfer.
01158   * @param husart: USART handle.
01159   * @retval HAL status
01160   */
01161 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
01162 {
01163   /* Process Locked */
01164   __HAL_LOCK(husart);
01165
01166   if(husart->State == HAL_USART_STATE_BUSY_TX)
01167   {
01168     /* Enable the USART DMA Tx request */
01169     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01170   }
01171   else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
01172            (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
01173   {
01174     /* Clear the Overrun flag before resuming the Rx transfer*/
01175     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
01176
01177     /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
01178     SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01179     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01180
01181     /* Enable the USART DMA Rx request  before the DMA Tx request */
01182     SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01183
01184     /* Enable the USART DMA Tx request */
01185     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01186   }
01187
01188   /* Process Unlocked */
01189   __HAL_UNLOCK(husart);
01190
01191   return HAL_OK;
01192 }
01193
01194 /**
01195   * @brief Stop the DMA Transfer.
01196   * @param husart: USART handle.
01197   * @retval HAL status
01198   */
01199 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
01200 {
01201   /* The Lock is not implemented on this API to allow the user application
01202      to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
01203      HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback:
01204      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
01205      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
01206      the stream and the corresponding call back is executed. */
01207
01208   /* Disable the USART Tx/Rx DMA requests */
01209   CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01210   CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01211
01212   /* Abort the USART DMA tx channel */
01213   if(husart->hdmatx != NULL)
01214   {
01215     HAL_DMA_Abort(husart->hdmatx);
01216   }
01217   /* Abort the USART DMA rx channel */
01218   if(husart->hdmarx != NULL)
01219   {
01220     HAL_DMA_Abort(husart->hdmarx);
01221   }
01222
01223   USART_EndTransfer(husart);
01224   husart->State = HAL_USART_STATE_READY;
01225
01226   return HAL_OK;
01227 }
01228
01229 /**
01230   * @brief  Abort ongoing transfers (blocking mode).
01231   * @param  husart USART handle.
01232   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01233   *         This procedure performs following operations :
01234   *           - Disable USART Interrupts (Tx and Rx)
01235   *           - Disable the DMA transfer in the peripheral register (if enabled)
01236   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01237   *           - Set handle State to READY
01238   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01239   * @retval HAL status
01240 */
01241 HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
01242 {
01243   /* Disable RXNE, PE, TXE, TC, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
01244   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
01245   CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
01246
01247   /* Disable the USART DMA Tx request if enabled */
01248   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01249   {
01250     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01251
01252     /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
01253     if(husart->hdmatx != NULL)
01254     {
01255       /* Set the USART DMA Abort callback to Null.
01256          No call back execution at end of DMA abort procedure */
01257       husart->hdmatx->XferAbortCallback = NULL;
01258
01259       HAL_DMA_Abort(husart->hdmatx);
01260     }
01261   }
01262
01263   /* Disable the USART DMA Rx request if enabled */
01264   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01265   {
01266     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01267
01268     /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
01269     if(husart->hdmarx != NULL)
01270     {
01271       /* Set the USART DMA Abort callback to Null.
01272          No call back execution at end of DMA abort procedure */
01273       husart->hdmarx->XferAbortCallback = NULL;
01274
01275       HAL_DMA_Abort(husart->hdmarx);
01276     }
01277   }
01278
01279   /* Reset Tx and Rx transfer counters */
01280   husart->TxXferCount = 0U;
01281   husart->RxXferCount = 0U;
01282
01283   /* Clear the Error flags in the ICR register */
01284   __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
01285
01286   /* Restore husart->State to Ready */
01287   husart->State  = HAL_USART_STATE_READY;
01288
01289   /* Reset Handle ErrorCode to No Error */
01290   husart->ErrorCode = HAL_USART_ERROR_NONE;
01291
01292   return HAL_OK;
01293 }
01294
01295 /**
01296   * @brief  Abort ongoing transfers (Interrupt mode).
01297   * @param  husart USART handle.
01298   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01299   *         This procedure performs following operations :
01300   *           - Disable USART Interrupts (Tx and Rx)
01301   *           - Disable the DMA transfer in the peripheral register (if enabled)
01302   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01303   *           - Set handle State to READY
01304   *           - At abort completion, call user abort complete callback
01305   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01306   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01307   * @retval HAL status
01308 */
01309 HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
01310 {
01311   uint32_t abortcplt = 1U;
01312
01313   /* Disable RXNE, PE, TXE, TC, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
01314   CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
01315   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
01316
01317   /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
01318      before any call to DMA Abort functions */
01319   /* DMA Tx Handle is valid */
01320   if(husart->hdmatx != NULL)
01321   {
01322     /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
01323        Otherwise, set it to NULL */
01324     if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01325     {
01326       husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
01327     }
01328     else
01329     {
01330       husart->hdmatx->XferAbortCallback = NULL;
01331     }
01332   }
01333   /* DMA Rx Handle is valid */
01334   if(husart->hdmarx != NULL)
01335   {
01336     /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
01337        Otherwise, set it to NULL */
01338     if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01339     {
01340       husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
01341     }
01342     else
01343     {
01344       husart->hdmarx->XferAbortCallback = NULL;
01345     }
01346   }
01347
01348   /* Disable the USART DMA Tx request if enabled */
01349   if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01350   {
01351     /* Disable DMA Tx at USART level */
01352     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01353
01354     /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
01355     if(husart->hdmatx != NULL)
01356     {
01357       /* USART Tx DMA Abort callback has already been initialised :
01358          will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
01359
01360       /* Abort DMA TX */
01361       if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
01362       {
01363         husart->hdmatx->XferAbortCallback = NULL;
01364       }
01365       else
01366       {
01367         abortcplt = 0U;
01368       }
01369     }
01370   }
01371
01372   /* Disable the USART DMA Rx request if enabled */
01373   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01374   {
01375     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01376
01377     /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
01378     if(husart->hdmarx != NULL)
01379     {
01380       /* USART Rx DMA Abort callback has already been initialised :
01381          will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
01382
01383       /* Abort DMA RX */
01384       if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
01385       {
01386         husart->hdmarx->XferAbortCallback = NULL;
01387         abortcplt = 1U;
01388       }
01389       else
01390       {
01391         abortcplt = 0U;
01392       }
01393     }
01394   }
01395
01396   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01397   if (abortcplt == 1U)
01398   {
01399     /* Reset Tx and Rx transfer counters */
01400     husart->TxXferCount = 0U;
01401     husart->RxXferCount = 0U;
01402
01403     /* Reset errorCode */
01404     husart->ErrorCode = HAL_USART_ERROR_NONE;
01405
01406     /* Clear the Error flags in the ICR register */
01407     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
01408
01409     /* Restore husart->State to Ready */
01410     husart->State  = HAL_USART_STATE_READY;
01411
01412     /* As no DMA to be aborted, call directly user Abort complete callback */
01413     HAL_USART_AbortCpltCallback(husart);
01414   }
01415
01416   return HAL_OK;
01417 }
01418
01419 /**
01420   * @brief  Handle USART interrupt request.
01421   * @param  husart USART handle.
01422   * @retval None
01423   */
01424 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
01425 {
01426   uint32_t isrflags   = READ_REG(husart->Instance->ISR);
01427   uint32_t cr1its     = READ_REG(husart->Instance->CR1);
01428   uint32_t cr3its     = READ_REG(husart->Instance->CR3);
01429   uint32_t errorflags;
01430
01431   /* If no error occurs */
01432   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR));
01433   if (errorflags == RESET)
01434   {
01435     /* USART in mode Receiver ---------------------------------------------------*/
01436     if(((isrflags & USART_ISR_RXNE) != RESET)
01437        && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_RXFTIE) != RESET)))
01438     {
01439       if(husart->State == HAL_USART_STATE_BUSY_RX)
01440       {
01441         USART_Receive_IT(husart);
01442       }
01443       else
01444       {
01445         USART_TransmitReceive_IT(husart);
01446       }
01447       return;
01448     }
01449   }
01450
01451   /* If some errors occur */
01452   if((errorflags != RESET)
01453      && (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET)
01454           || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
01455   {
01456     /* USART parity error interrupt occurred -------------------------------------*/
01457     if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
01458     {
01459       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
01460
01461       husart->ErrorCode |= HAL_USART_ERROR_PE;
01462     }
01463
01464     /* USART frame error interrupt occurred --------------------------------------*/
01465     if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01466     {
01467       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
01468
01469       husart->ErrorCode |= HAL_USART_ERROR_FE;
01470     }
01471
01472     /* USART noise error interrupt occurred --------------------------------------*/
01473     if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01474     {
01475       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
01476
01477       husart->ErrorCode |= HAL_USART_ERROR_NE;
01478     }
01479
01480     /* USART Over-Run interrupt occurred -----------------------------------------*/
01481     if(((isrflags & USART_ISR_ORE) != RESET)
01482        && (((cr1its & USART_CR1_RXNEIE) != RESET)
01483            || ((cr3its & USART_CR3_RXFTIE) != RESET)
01484            || ((cr3its & USART_CR3_EIE) != RESET)))
01485     {
01486       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
01487
01488       husart->ErrorCode |= HAL_USART_ERROR_ORE;
01489     }
01490
01491     /* USART Under-Run interrupt occurred --------------------------------------*/
01492     if(((isrflags & USART_ISR_UDR) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01493     {
01494       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_UDRCF);
01495       husart->ErrorCode |= HAL_USART_ERROR_UDR;
01496     }
01497
01498     /* Call USART Error Call back function if need be --------------------------*/
01499     if(husart->ErrorCode != HAL_USART_ERROR_NONE)
01500     {
01501       /* USART in mode Receiver ---------------------------------------------------*/
01502       if(((isrflags & USART_ISR_RXNE) != RESET)
01503          && (((cr1its & USART_CR1_RXNEIE) != RESET)
01504              || ((cr3its & USART_CR3_RXFTIE) != RESET)))
01505       {
01506         if(husart->State == HAL_USART_STATE_BUSY_RX)
01507         {
01508           USART_Receive_IT(husart);
01509         }
01510         else
01511         {
01512           USART_TransmitReceive_IT(husart);
01513         }
01514       }
01515
01516       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
01517          consider error as blocking */
01518       if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) ||
01519           (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))
01520       {
01521         /* Blocking error : transfer is aborted
01522            Set the USART state ready to be able to start again the process,
01523            Disable Interrupts, and disable DMA requests, if ongoing */
01524         USART_EndTransfer(husart);
01525
01526         /* Disable the USART DMA Rx request if enabled */
01527         if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01528         {
01529           CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
01530
01531           /* Abort the USART DMA Tx channel */
01532           if(husart->hdmatx != NULL)
01533           {
01534             /* Set the USART Tx DMA Abort callback to NULL : no callback
01535                executed at end of DMA abort procedure */
01536             husart->hdmatx->XferAbortCallback = NULL;
01537
01538             /* Abort DMA TX */
01539             HAL_DMA_Abort_IT(husart->hdmatx);
01540           }
01541
01542           /* Abort the USART DMA Rx channel */
01543           if(husart->hdmarx != NULL)
01544           {
01545             /* Set the USART Rx DMA Abort callback :
01546                will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
01547             husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
01548
01549             /* Abort DMA RX */
01550             if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
01551             {
01552               /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
01553               husart->hdmarx->XferAbortCallback(husart->hdmarx);
01554             }
01555           }
01556           else
01557           {
01558             /* Call user error callback */
01559             HAL_USART_ErrorCallback(husart);
01560           }
01561         }
01562         else
01563         {
01564           /* Call user error callback */
01565           HAL_USART_ErrorCallback(husart);
01566         }
01567       }
01568       else
01569       {
01570         /* Non Blocking error : transfer could go on.
01571            Error is notified to user through user error callback */
01572         HAL_USART_ErrorCallback(husart);
01573         husart->ErrorCode = HAL_USART_ERROR_NONE;
01574       }
01575     }
01576     return;
01577
01578   } /* End if some error occurs */
01579
01580
01581   /* USART in mode Transmitter ------------------------------------------------*/
01582   if(((isrflags & USART_ISR_TXE) != RESET)
01583      && (((cr1its & USART_CR1_TXEIE) != RESET)
01584          || ((cr3its & USART_CR3_TXFTIE) != RESET)))
01585   {
01586     if(husart->State == HAL_USART_STATE_BUSY_TX)
01587     {
01588       USART_Transmit_IT(husart);
01589     }
01590     else
01591     {
01592       USART_TransmitReceive_IT(husart);
01593     }
01594     return;
01595   }
01596
01597   /* USART in mode Transmitter (transmission end) -----------------------------*/
01598   if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
01599   {
01600     USART_EndTransmit_IT(husart);
01601     return;
01602   }
01603
01604   /* USART TX FIFO Empty  -----------------------------------------------------*/
01605   if(((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET))
01606   {
01607     CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXFEIE);
01608   }
01609 }
01610
01611 /**
01612   * @brief Tx Transfer completed callback.
01613   * @param husart: USART handle.
01614   * @retval None
01615   */
01616 __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
01617 {
01618   /* Prevent unused argument(s) compilation warning */
01619   UNUSED(husart);
01620
01621   /* NOTE : This function should not be modified, when the callback is needed,
01622             the HAL_USART_TxCpltCallback can be implemented in the user file.
01623    */
01624 }
01625
01626 /**
01627   * @brief  Tx Half Transfer completed callback.
01628   * @param husart: USART handle.
01629   * @retval None
01630   */
01631 __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
01632 {
01633   /* Prevent unused argument(s) compilation warning */
01634   UNUSED(husart);
01635
01636   /* NOTE: This function should not be modified, when the callback is needed,
01637            the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
01638    */
01639 }
01640
01641 /**
01642   * @brief  Rx Transfer completed callback.
01643   * @param husart: USART handle.
01644   * @retval None
01645   */
01646 __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
01647 {
01648   /* Prevent unused argument(s) compilation warning */
01649   UNUSED(husart);
01650
01651   /* NOTE: This function should not be modified, when the callback is needed,
01652            the HAL_USART_RxCpltCallback can be implemented in the user file.
01653    */
01654 }
01655
01656 /**
01657   * @brief Rx Half Transfer completed callback.
01658   * @param husart: USART handle.
01659   * @retval None
01660   */
01661 __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
01662 {
01663   /* Prevent unused argument(s) compilation warning */
01664   UNUSED(husart);
01665
01666   /* NOTE : This function should not be modified, when the callback is needed,
01667             the HAL_USART_RxHalfCpltCallback can be implemented in the user file
01668    */
01669 }
01670
01671 /**
01672   * @brief Tx/Rx Transfers completed callback for the non-blocking process.
01673   * @param husart: USART handle.
01674   * @retval None
01675   */
01676 __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
01677 {
01678   /* Prevent unused argument(s) compilation warning */
01679   UNUSED(husart);
01680
01681   /* NOTE : This function should not be modified, when the callback is needed,
01682             the HAL_USART_TxRxCpltCallback can be implemented in the user file
01683    */
01684 }
01685
01686 /**
01687   * @brief USART error callback.
01688   * @param husart: USART handle.
01689   * @retval None
01690   */
01691 __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
01692 {
01693   /* Prevent unused argument(s) compilation warning */
01694   UNUSED(husart);
01695
01696   /* NOTE : This function should not be modified, when the callback is needed,
01697             the HAL_USART_ErrorCallback can be implemented in the user file.
01698    */
01699 }
01700
01701 /**
01702   * @brief  USART Abort Complete callback.
01703   * @param  husart USART handle.
01704   * @retval None
01705   */
01706 __weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
01707 {
01708   /* Prevent unused argument(s) compilation warning */
01709   UNUSED(husart);
01710
01711   /* NOTE : This function should not be modified, when the callback is needed,
01712             the HAL_USART_AbortCpltCallback can be implemented in the user file.
01713    */
01714 }
01715
01716 /**
01717   * @}
01718   */
01719
01720 /** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions
01721  *  @brief   USART Peripheral State and Error functions
01722  *
01723 @verbatim
01724   ==============================================================================
01725             ##### Peripheral State and Error functions #####
01726   ==============================================================================
01727     [..]
01728     This subsection provides functions allowing to :
01729       (+) Return the USART handle state
01730       (+) Return the USART handle error code
01731
01732 @endverbatim
01733   * @{
01734   */
01735
01736
01737 /**
01738   * @brief Return the USART handle state.
01739   * @param husart : pointer to a USART_HandleTypeDef structure that contains
01740   *              the configuration information for the specified USART.
01741   * @retval USART handle state
01742   */
01743 HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
01744 {
01745   return husart->State;
01746 }
01747
01748 /**
01749   * @brief Return the USART error code.
01750   * @param husart : pointer to a USART_HandleTypeDef structure that contains
01751   *              the configuration information for the specified USART.
01752   * @retval USART handle Error Code
01753   */
01754 uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
01755 {
01756   return husart->ErrorCode;
01757 }
01758
01759 /**
01760   * @}
01761   */
01762
01763 /**
01764   * @}
01765   */
01766
01767 /** @defgroup USART_Private_Functions USART Private Functions
01768  * @{
01769  */
01770
01771 /**
01772   * @brief  End ongoing transfer on USART peripheral (following error detection or Transfer completion).
01773   * @param  husart USART handle.
01774   * @retval None
01775   */
01776 static void USART_EndTransfer(USART_HandleTypeDef *husart)
01777 {
01778   /* Disable RXNE, PE, TXE, TC, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
01779   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
01780   CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
01781
01782   /* At end of process, restore husart->State to Ready */
01783   husart->State = HAL_USART_STATE_READY;
01784 }
01785
01786 /**
01787   * @brief  DMA USART transmit process complete callback.
01788   * @param  hdma DMA handle.
01789   * @retval None
01790   */
01791 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01792 {
01793   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
01794
01795   /* DMA Normal mode */
01796   if (hdma->Init.Mode != DMA_CIRCULAR)
01797   {
01798     husart->TxXferCount = 0U;
01799
01800     if(husart->State == HAL_USART_STATE_BUSY_TX)
01801     {
01802       /* Disable the DMA transfer for transmit request by resetting the DMAT bit
01803          in the USART CR3 register */
01804       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01805
01806       /* Enable the USART Transmit Complete Interrupt */
01807       SET_BIT(husart->Instance->CR1, USART_CR1_TCIE);
01808     }
01809   }
01810   /* DMA Circular mode */
01811   else
01812   {
01813     if(husart->State == HAL_USART_STATE_BUSY_TX)
01814     {
01815     HAL_USART_TxCpltCallback(husart);
01816    }
01817  }
01818 }
01819
01820 /**
01821   * @brief DMA USART transmit process half complete callback.
01822   * @param hdma : DMA handle.
01823   * @retval None
01824   */
01825 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01826 {
01827   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
01828
01829   HAL_USART_TxHalfCpltCallback(husart);
01830 }
01831
01832 /**
01833   * @brief DMA USART receive process complete callback.
01834   * @param  hdma: DMA handle.
01835   * @retval None
01836   */
01837 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01838 {
01839   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
01840
01841   /* DMA Normal mode */
01842   if (hdma->Init.Mode != DMA_CIRCULAR)
01843   {
01844     husart->RxXferCount = 0U;
01845
01846     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01847     CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01848     CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
01849
01850     /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
01851        in USART CR3 register */
01852     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01853     /* similarly, disable the DMA TX transfer that was started to provide the
01854        clock to the slave device */
01855     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01856
01857     if(husart->State == HAL_USART_STATE_BUSY_RX)
01858     {
01859       HAL_USART_RxCpltCallback(husart);
01860     }
01861     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
01862     else
01863     {
01864       HAL_USART_TxRxCpltCallback(husart);
01865     }
01866     husart->State= HAL_USART_STATE_READY;
01867   }
01868   /* DMA circular mode */
01869   else
01870   {
01871     if(husart->State == HAL_USART_STATE_BUSY_RX)
01872     {
01873       HAL_USART_RxCpltCallback(husart);
01874     }
01875     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
01876     else
01877     {
01878       HAL_USART_TxRxCpltCallback(husart);
01879     }
01880   }
01881
01882 }
01883
01884 /**
01885   * @brief DMA USART receive process half complete callback.
01886   * @param hdma : DMA handle.
01887   * @retval None
01888   */
01889 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01890 {
01891   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
01892
01893   HAL_USART_RxHalfCpltCallback(husart);
01894 }
01895
01896 /**
01897   * @brief DMA USART communication error callback.
01898   * @param  hdma: DMA handle.
01899   * @retval None
01900   */
01901 static void USART_DMAError(DMA_HandleTypeDef *hdma)
01902 {
01903   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
01904
01905   husart->RxXferCount = 0U;
01906   husart->TxXferCount = 0U;
01907   USART_EndTransfer(husart);
01908
01909   husart->ErrorCode |= HAL_USART_ERROR_DMA;
01910   husart->State= HAL_USART_STATE_READY;
01911
01912   HAL_USART_ErrorCallback(husart);
01913 }
01914
01915 /**
01916   * @brief  DMA USART communication abort callback, when initiated by HAL services on Error
01917   *         (To be called at end of DMA Abort procedure following error occurrence).
01918   * @param  hdma: DMA handle.
01919   * @retval None
01920   */
01921 static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
01922 {
01923   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
01924   husart->RxXferCount = 0U;
01925   husart->TxXferCount = 0U;
01926
01927   HAL_USART_ErrorCallback(husart);
01928 }
01929
01930 /**
01931   * @brief  DMA USART Tx communication abort callback, when initiated by user
01932   *         (To be called at end of DMA Tx Abort procedure following user abort request).
01933   * @note   When this callback is executed, User Abort complete call back is called only if no
01934   *         Abort still ongoing for Rx DMA Handle.
01935   * @param  hdma DMA handle.
01936   * @retval None
01937   */
01938 static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
01939 {
01940   USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
01941
01942   husart->hdmatx->XferAbortCallback = NULL;
01943
01944   /* Check if an Abort process is still ongoing */
01945   if(husart->hdmarx != NULL)
01946   {
01947     if(husart->hdmarx->XferAbortCallback != NULL)
01948     {
01949       return;
01950     }
01951   }
01952
01953   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
01954   husart->TxXferCount = 0U;
01955   husart->RxXferCount = 0U;
01956
01957   /* Reset errorCode */
01958   husart->ErrorCode = HAL_USART_ERROR_NONE;
01959
01960   /* Clear the Error flags in the ICR register */
01961   __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
01962
01963   /* Restore husart->State to Ready */
01964   husart->State  = HAL_USART_STATE_READY;
01965
01966   /* Call user Abort complete callback */
01967   HAL_USART_AbortCpltCallback(husart);
01968 }
01969
01970
01971 /**
01972   * @brief  DMA USART Rx communication abort callback, when initiated by user
01973   *         (To be called at end of DMA Rx Abort procedure following user abort request).
01974   * @note   When this callback is executed, User Abort complete call back is called only if no
01975   *         Abort still ongoing for Tx DMA Handle.
01976   * @param  hdma DMA handle.
01977   * @retval None
01978   */
01979 static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
01980 {
01981   USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
01982
01983   husart->hdmarx->XferAbortCallback = NULL;
01984
01985   /* Check if an Abort process is still ongoing */
01986   if(husart->hdmatx != NULL)
01987   {
01988     if(husart->hdmatx->XferAbortCallback != NULL)
01989     {
01990       return;
01991     }
01992   }
01993
01994   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
01995   husart->TxXferCount = 0U;
01996   husart->RxXferCount = 0U;
01997
01998   /* Reset errorCode */
01999   husart->ErrorCode = HAL_USART_ERROR_NONE;
02000
02001   /* Clear the Error flags in the ICR register */
02002   __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
02003
02004   /* Restore husart->State to Ready */
02005   husart->State  = HAL_USART_STATE_READY;
02006
02007   /* Call user Abort complete callback */
02008   HAL_USART_AbortCpltCallback(husart);
02009 }
02010
02011
02012 /**
02013   * @brief  Handle USART Communication Timeout.
02014   * @param husart: USART handle.
02015   * @param  Flag: specifies the USART flag to check.
02016   * @param  Status: the Flag status (SET or RESET).
02017   * @param  Tickstart: tick start value.
02018   * @param  Timeout: timeout duration.
02019   * @retval HAL status
02020   */
02021 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
02022 {
02023   /* Wait until flag is set */
02024   while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
02025   {
02026     /* Check for the Timeout */
02027     if(Timeout != HAL_MAX_DELAY)
02028     {
02029       if((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
02030       {
02031         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
02032         CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
02033         CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
02034
02035         husart->State= HAL_USART_STATE_READY;
02036
02037         /* Process Unlocked */
02038         __HAL_UNLOCK(husart);
02039
02040         return HAL_TIMEOUT;
02041       }
02042     }
02043   }
02044
02045   return HAL_OK;
02046 }
02047
02048 /**
02049   * @brief Configure the USART peripheral.
02050   * @param husart: USART handle.
02051   * @retval HAL status
02052   */
02053 static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
02054 {
02055   uint32_t tmpreg                      = 0x0U;
02056   USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;
02057   HAL_StatusTypeDef ret                = HAL_OK;
02058   uint16_t brrtemp                     = 0x0000U;
02059   uint16_t usartdiv                    = 0x0000U;
02060   PLL2_ClocksTypeDef pll2_clocks;
02061   PLL3_ClocksTypeDef pll3_clocks;
02062
02063   /* Check the parameters */
02064   assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
02065   assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
02066   assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
02067   assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
02068   assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
02069   assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
02070   assert_param(IS_USART_PARITY(husart->Init.Parity));
02071   assert_param(IS_USART_MODE(husart->Init.Mode));
02072   assert_param(IS_USART_PRESCALER(husart->Init.Prescaler));
02073   assert_param(IS_USART_NSS(husart->Init.NSS));
02074   assert_param(IS_USART_SLAVEMODE(husart->Init.SlaveMode));
02075   assert_param(IS_USART_FIFO_MODE_STATE(husart->Init.FIFOMode));
02076   if (husart->Init.FIFOMode == USART_FIFOMODE_ENABLE)
02077   {
02078     assert_param(IS_USART_TXFIFO_THRESHOLD(husart->Init.TXFIFOThreshold));
02079     assert_param(IS_USART_RXFIFO_THRESHOLD(husart->Init.RXFIFOThreshold));
02080   }
02081
02082   /*-------------------------- USART CR1 Configuration -----------------------*/
02083    /* Clear M, PCE, PS, TE and RE bits and configure
02084    *  the USART Word Length, Parity and Mode:
02085    *  set the M bits according to husart->Init.WordLength value
02086    *  set PCE and PS bits according to husart->Init.Parity value
02087    *  set TE and RE bits according to husart->Init.Mode value
02088    *  force OVER8 to 1 to allow to reach the maximum speed (Fclock/8)  */
02089   tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
02090   tmpreg |=  (uint32_t)husart->Init.FIFOMode;
02091   MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
02092
02093   /*---------------------------- USART CR2 Configuration ---------------------*/
02094   /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:
02095    * set CPOL bit according to husart->Init.CLKPolarity value
02096    * set CPHA bit according to husart->Init.CLKPhase value
02097    * set DIS_NSS bit according to husart->Init.NSS value
02098    * set LBCL bit according to husart->Init.CLKLastBit value
02099    * set STOP[13:12] bits according to husart->Init.StopBits value
02100    * set SlaveMode bit according to husart->Init.SlaveMode value */
02101   tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
02102   tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase | (uint32_t)husart->Init.NSS);
02103   tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits | (uint32_t)husart->Init.SlaveMode);
02104   MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
02105
02106   /*-------------------------- USART CR3 Configuration -----------------------*/
02107   /* Clear and configure the TXFTCFG & RXFTCFG bits:
02108    * set TXFTCFG bit according to husart->Init.TXFIFOThreshold value
02109    * set RXFTCFG bit according to husart->Init.RXFIFOThreshold value */
02110   if (husart->Init.FIFOMode == USART_FIFOMODE_ENABLE)
02111   {
02112     tmpreg = ((uint32_t)husart->Init.TXFIFOThreshold | (uint32_t)husart->Init.RXFIFOThreshold );
02113     MODIFY_REG(husart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
02114   }
02115
02116   /*-------------------------- USART PRESC Configuration -----------------------*/
02117   /* Configure
02118    * - USART Clock Prescaler : set PRESCALER according to husart->Init.Prescaler value */
02119   MODIFY_REG(husart->Instance->PRESC, USART_PRESC_PRESCALER, husart->Init.Prescaler);
02120
02121   /*-------------------------- USART BRR Configuration -----------------------*/
02122   /* BRR is filled-up according to OVER8 bit setting which is forced to 1     */
02123   USART_GETCLOCKSOURCE(husart, clocksource);
02124   switch (clocksource)
02125   {
02126     case USART_CLOCKSOURCE_D2PCLK1:
02127       usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate, husart->Init.Prescaler));
02128       break;
02129     case USART_CLOCKSOURCE_D2PCLK2:
02130       usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate, husart->Init.Prescaler));
02131       break;
02132     case USART_CLOCKSOURCE_PLL2:
02133       HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
02134       usartdiv = (uint16_t)(USART_DIV_SAMPLING8(pll2_clocks.PLL2_Q_Frequency, husart->Init.BaudRate, husart->Init.Prescaler));
02135       break;
02136     case USART_CLOCKSOURCE_PLL3:
02137       HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
02138       usartdiv = (uint16_t)(USART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, husart->Init.BaudRate, husart->Init.Prescaler));
02139       break;
02140     case USART_CLOCKSOURCE_HSI:
02141       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
02142       {
02143         usartdiv = (uint16_t)(USART_DIV_SAMPLING8((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)), husart->Init.BaudRate, husart->Init.Prescaler));
02144       }
02145       else
02146       {
02147         usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.Prescaler));
02148       }
02149       break;
02150     case USART_CLOCKSOURCE_CSI:
02151       usartdiv = (uint16_t)(USART_DIV_SAMPLING8(CSI_VALUE, husart->Init.BaudRate, husart->Init.Prescaler));
02152       break;
02153     case USART_CLOCKSOURCE_LSE:
02154       usartdiv = (uint16_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.Prescaler));
02155       break;
02156     case USART_CLOCKSOURCE_UNDEFINED:
02157     default:
02158       ret = HAL_ERROR;
02159       break;
02160   }
02161
02162   brrtemp = usartdiv & 0xFFF0U;
02163   brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
02164   husart->Instance->BRR = brrtemp;
02165
02166   return ret;
02167 }
02168
02169 /**
02170   * @brief Check the USART Idle State.
02171   * @param husart: USART handle.
02172   * @retval HAL status
02173   */
02174 static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
02175 {
02176   uint32_t tickstart = 0U;
02177
02178   /* Initialize the USART ErrorCode */
02179   husart->ErrorCode = HAL_USART_ERROR_NONE;
02180
02181   /* Init tickstart for timeout managment */
02182   tickstart = HAL_GetTick();
02183
02184   /* Check if the Transmitter is enabled */
02185   if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
02186   {
02187     /* Wait until TEACK flag is set */
02188     if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
02189     {
02190       /* Timeout occurred */
02191       return HAL_TIMEOUT;
02192     }
02193   }
02194   /* Check if the Receiver is enabled */
02195   if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
02196   {
02197     /* Wait until REACK flag is set */
02198     if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
02199     {
02200       /* Timeout occurred */
02201       return HAL_TIMEOUT;
02202     }
02203   }
02204
02205   /* Initialize the USART state*/
02206   husart->State= HAL_USART_STATE_READY;
02207
02208   /* Process Unlocked */
02209   __HAL_UNLOCK(husart);
02210
02211   return HAL_OK;
02212 }
02213
02214 /**
02215   * @brief  Simplex send an amount of data in non-blocking mode.
02216   * @note   Function called under interruption only, once
02217   *         interruptions have been enabled by HAL_USART_Transmit_IT().
02218   * @note   The USART errors are not managed to avoid the overrun error.
02219   * @param husart: USART handle.
02220   * @retval HAL status
02221   */
02222 static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
02223 {
02224   uint16_t* tmp;
02225
02226   if(husart->TxXferCount == 0U)
02227   {
02228     /* Disable the TX FIFO threshold interrupt (if FIFO mode is enabled) or
02229        Transmit Data Register Empty interrupt (if FIFO mode is Disabled).
02230     */
02231     if (READ_BIT(husart->Instance->CR1, USART_CR1_FIFOEN) != RESET)
02232     {
02233       CLEAR_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
02234     }
02235     else
02236     {
02237       CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
02238     }
02239
02240     /* Enable the USART Transmit Complete Interrupt */
02241     SET_BIT(husart->Instance->CR1, USART_CR1_TCIE);
02242
02243     return HAL_OK;
02244   }
02245   else
02246   {
02247     if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
02248     {
02249       tmp = (uint16_t*) husart->pTxBuffPtr;
02250       husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
02251       husart->pTxBuffPtr += 2U;
02252     }
02253     else
02254     {
02255       husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFFU);
02256     }
02257
02258     husart->TxXferCount--;
02259
02260     return HAL_OK;
02261   }
02262 }
02263
02264
02265 /**
02266   * @brief  Wraps up transmission in non-blocking mode.
02267   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
02268   *                the configuration information for the specified USART module.
02269   * @retval HAL status
02270   */
02271 static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
02272 {
02273   /* Disable the USART Transmit Complete Interrupt */
02274   CLEAR_BIT(husart->Instance->CR1, USART_CR1_TCIE);
02275
02276   /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
02277   CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
02278
02279   /* Tx process is ended, restore husart->State to Ready */
02280   husart->State = HAL_USART_STATE_READY;
02281
02282   HAL_USART_TxCpltCallback(husart);
02283
02284   return HAL_OK;
02285 }
02286
02287
02288 /**
02289   * @brief  Simplex receive an amount of data in non-blocking mode.
02290   * @note   Function called under interruption only, once
02291   *         interruptions have been enabled by HAL_USART_Receive_IT().
02292   * @param husart: USART handle
02293   * @retval HAL status
02294   */
02295 static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
02296 {
02297   uint16_t* tmp;
02298   uint16_t uhMask = husart->Mask;
02299
02300   if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
02301   {
02302     tmp = (uint16_t*) husart->pRxBuffPtr;
02303     *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
02304     husart->pRxBuffPtr += 2U;
02305   }
02306   else
02307   {
02308     *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
02309   }
02310
02311   if (husart->Init.SlaveMode == USART_SLAVEMODE_DISABLE)
02312   {
02313     /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
02314     husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
02315   }
02316
02317   if(--husart->RxXferCount == 0U)
02318   {
02319     /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
02320     CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
02321
02322     /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
02323     CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
02324
02325     /* Rx process is completed, restore husart->State to Ready */
02326     husart->State = HAL_USART_STATE_READY;
02327
02328     HAL_USART_RxCpltCallback(husart);
02329
02330     return HAL_OK;
02331   }
02332
02333   return HAL_OK;
02334 }
02335
02336 /**
02337   * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
02338   * @note   Function called under interruption only, once
02339   *         interruptions have been enabled by HAL_USART_TransmitReceive_IT().
02340   * @param husart: USART handle.
02341   * @retval HAL status
02342   */
02343 static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
02344 {
02345   uint16_t* tmp;
02346   uint16_t uhMask = husart->Mask;
02347
02348   if(husart->TxXferCount != 0x00U)
02349   {
02350     if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
02351     {
02352       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
02353       {
02354         tmp = (uint16_t*) husart->pTxBuffPtr;
02355         husart->Instance->TDR = (uint16_t)(*tmp & uhMask);
02356         husart->pTxBuffPtr += 2U;
02357       }
02358       else
02359       {
02360         husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);
02361       }
02362       husart->TxXferCount--;
02363
02364       /* Check the latest data transmitted */
02365       if(husart->TxXferCount == 0U)
02366       {
02367         /* Disable the TX FIFO threshold interrupt (if FIFO mode is enabled) or
02368            Transmit Data Register Empty interrupt (if FIFO mode is Disabled) */
02369         if (READ_BIT(husart->Instance->CR1, USART_CR1_FIFOEN) != RESET)
02370         {
02371           CLEAR_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
02372         }
02373         else
02374         {
02375           CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
02376         }
02377       }
02378     }
02379   }
02380
02381   if(husart->RxXferCount != 0x00U)
02382   {
02383     if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
02384     {
02385       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
02386       {
02387         tmp = (uint16_t*) husart->pRxBuffPtr;
02388         *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
02389         husart->pRxBuffPtr += 2U;
02390       }
02391       else
02392       {
02393         *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
02394       }
02395       husart->RxXferCount--;
02396     }
02397   }
02398
02399   /* Check the latest data received */
02400   if(husart->RxXferCount == 0U)
02401   {
02402     /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
02403     CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
02404
02405     /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
02406     CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
02407
02408     /* Rx process is completed, restore husart->State to Ready */
02409     husart->State = HAL_USART_STATE_READY;
02410
02411     HAL_USART_TxRxCpltCallback(husart);
02412
02413     return HAL_OK;
02414   }
02415
02416   return HAL_OK;
02417 }
02418
02419 /**
02420   * @}
02421   */
02422
02423 #endif /* HAL_USART_MODULE_ENABLED */
02424 /**
02425   * @}
02426   */
02427
02428 /**
02429   * @}
02430   */
02431
02432 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_usart.h Source File

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stm32h7xx_hal_usart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_usart.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of USART HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_USART_H
00040 #define __STM3H7xx_HAL_USART_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup USART
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup USART_Exported_Types USART Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief USART Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.
00068                                            The baud rate is computed using the following formula:
00069                                               Baud Rate Register = ((PCLKx) / ((husart->Init.BaudRate))) */
00070
00071   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00072                                            This parameter can be a value of @ref USARTEx_Word_Length */
00073
00074   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00075                                            This parameter can be a value of @ref USART_Stop_Bits */
00076
00077   uint32_t Parity;                   /*!< Specifies the parity mode.
00078                                            This parameter can be a value of @ref USART_Parity
00079                                            @note When parity is enabled, the computed parity is inserted
00080                                                  at the MSB position of the transmitted data (9th bit when
00081                                                  the word length is set to 9 data bits; 8th bit when the
00082                                                  word length is set to 8 data bits). */
00083
00084   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00085                                            This parameter can be a value of @ref USART_Mode */
00086
00087   uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
00088                                            This parameter can be a value of @ref USART_Clock_Polarity */
00089
00090   uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
00091                                            This parameter can be a value of @ref USART_Clock_Phase */
00092
00093   uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
00094                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00095                                            This parameter can be a value of @ref USART_Last_Bit */
00096
00097   uint32_t Prescaler;                 /*!< Specifies the prescaler value used to divide the USART clock source.
00098                                            This parameter can be a value of @ref USART_Prescaler */
00099
00100   uint32_t NSS;                       /*!< Specifies whether the NSS signal is managed by hardware (DIS_NSS pin)
00101                                            or by software . This parameter can be a value
00102                                            of @ref USART_Slave_Select_management */
00103
00104   uint32_t SlaveMode;                 /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value
00105                                            of @ref USART_Slave_Mode */
00106
00107   uint32_t FIFOMode;                  /*!< Specifies if the FIFO mode will be used. This parameter can be a value
00108                                            of @ref USART_FIFO_mode */
00109
00110   uint32_t TXFIFOThreshold;           /*!< Specifies the TXFIFO threshold level.
00111                                            This parameter can be a value of @ref USART_TXFIFO_threshold_level */
00112
00113   uint32_t RXFIFOThreshold;           /*!< Specifies the RXFIFO threshold level.
00114                                            This parameter can be a value of @ref USART_RXFIFO_threshold_level */
00115
00116 }USART_InitTypeDef;
00117
00118 /**
00119   * @brief HAL USART State structures definition
00120   */
00121 typedef enum
00122 {
00123   HAL_USART_STATE_RESET             = 0x00U,    /*!< Peripheral is not initialized                  */
00124   HAL_USART_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use       */
00125   HAL_USART_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                 */
00126   HAL_USART_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing           */
00127   HAL_USART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing              */
00128   HAL_USART_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission Reception process is ongoing */
00129   HAL_USART_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                                  */
00130   HAL_USART_STATE_ERROR             = 0x04U     /*!< Error                                          */
00131 }HAL_USART_StateTypeDef;
00132
00133 /**
00134   * @brief  HAL USART Error Code structure definition
00135   */
00136 typedef enum
00137 {
00138   HAL_USART_ERROR_NONE      = 0x00U,    /*!< No error            */
00139   HAL_USART_ERROR_PE        = 0x01U,    /*!< Parity error        */
00140   HAL_USART_ERROR_NE        = 0x02U,    /*!< Noise error         */
00141   HAL_USART_ERROR_FE        = 0x04U,    /*!< frame error         */
00142   HAL_USART_ERROR_ORE       = 0x08U,    /*!< Overrun error       */
00143   HAL_USART_ERROR_DMA       = 0x10U,    /*!< DMA transfer error  */
00144   HAL_USART_ERROR_UDR       = 0x11U     /*!< SPI UnderRun error  */
00145 }HAL_USART_ErrorTypeDef;
00146
00147 /**
00148   * @brief  USART clock sources definitions
00149   */
00150 typedef enum
00151 {
00152   USART_CLOCKSOURCE_D2PCLK1    = 0x00U,    /*!< Domain2 PCLK1 clock source */
00153   USART_CLOCKSOURCE_D2PCLK2    = 0x01U,    /*!< Domain2 PCLK2 clock source */
00154   USART_CLOCKSOURCE_D3PCLK1    = 0x02U,    /*!< Domain3 PCLK1 clock source */
00155   USART_CLOCKSOURCE_PLL2       = 0x04U,    /*!< PLL2Q clock source         */
00156   USART_CLOCKSOURCE_HSI        = 0x08U,    /*!< HSI clock source           */
00157   USART_CLOCKSOURCE_CSI        = 0x10U,    /*!< CSI clock source           */
00158   USART_CLOCKSOURCE_LSE        = 0x20U,    /*!< LSE clock source           */
00159   USART_CLOCKSOURCE_PLL3       = 0x40U,    /*!< PLL3Q clock source         */
00160   USART_CLOCKSOURCE_UNDEFINED  = 0x80U     /*!< Undefined clock source     */
00161 }USART_ClockSourceTypeDef;
00162
00163
00164 /**
00165   * @brief  USART handle Structure definition
00166   */
00167 typedef struct
00168 {
00169   USART_TypeDef                 *Instance;        /*!<  USART registers base address        */
00170
00171   USART_InitTypeDef             Init;             /*!< USART communication parameters      */
00172
00173   uint8_t                       *pTxBuffPtr;      /*!< Pointer to USART Tx transfer Buffer */
00174
00175   uint16_t                      TxXferSize;       /*!< USART Tx Transfer size              */
00176
00177   __IO uint16_t                 TxXferCount;      /*!< USART Tx Transfer Counter           */
00178
00179   uint8_t                       *pRxBuffPtr;      /*!< Pointer to USART Rx transfer Buffer */
00180
00181   uint16_t                      RxXferSize;       /*!< USART Rx Transfer size              */
00182
00183   __IO uint16_t                 RxXferCount;      /*!< USART Rx Transfer Counter           */
00184
00185   uint16_t                      Mask;             /*!< USART Rx RDR register mask          */
00186
00187   DMA_HandleTypeDef             *hdmatx;          /*!< USART Tx DMA Handle parameters      */
00188
00189   DMA_HandleTypeDef             *hdmarx;          /*!< USART Rx DMA Handle parameters      */
00190
00191   HAL_LockTypeDef               Lock;            /*!<  Locking object                      */
00192
00193   __IO HAL_USART_StateTypeDef   State;           /*!< USART communication state           */
00194
00195   __IO uint32_t                 ErrorCode;       /*!< USART Error code                    */
00196
00197 }USART_HandleTypeDef;
00198
00199 /**
00200   * @}
00201   */
00202
00203 /* Exported constants --------------------------------------------------------*/
00204 /** @defgroup USART_Exported_Constants USART Exported Constants
00205   * @{
00206   */
00207
00208 /** @defgroup USART_Stop_Bits  USART Number of Stop Bits
00209   * @{
00210   */
00211 #define USART_STOPBITS_0_5                  ((uint32_t)USART_CR2_STOP_0)                      /*!< USART frame with 0.5 stop bit  */
00212 #define USART_STOPBITS_1                    ((uint32_t)0x00000000U)                           /*!< USART frame with 1 stop bit    */
00213 #define USART_STOPBITS_1_5                  ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< USART frame with 1.5 stop bits */
00214 #define USART_STOPBITS_2                    ((uint32_t)USART_CR2_STOP_1)                      /*!< USART frame with 2 stop bits   */
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup USART_Parity    USART Parity
00220   * @{
00221   */
00222 #define USART_PARITY_NONE                   ((uint32_t)0x00000000U)                     /*!< No parity   */
00223 #define USART_PARITY_EVEN                   ((uint32_t)USART_CR1_PCE)                   /*!< Even parity */
00224 #define USART_PARITY_ODD                    ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))  /*!< Odd parity  */
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup USART_Mode   USART Mode
00230   * @{
00231   */
00232 #define USART_MODE_RX                       ((uint32_t)USART_CR1_RE)                   /*!< RX mode        */
00233 #define USART_MODE_TX                       ((uint32_t)USART_CR1_TE)                   /*!< TX mode        */
00234 #define USART_MODE_TX_RX                    ((uint32_t)(USART_CR1_TE |USART_CR1_RE))   /*!< RX and TX mode */
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup USART_Over_Sampling USART Over Sampling
00240   * @{
00241   */
00242 #define USART_OVERSAMPLING_16               ((uint32_t)0x00000000U)         /*!< Oversampling by 16 */
00243 #define USART_OVERSAMPLING_8                ((uint32_t)USART_CR1_OVER8)     /*!< Oversampling by 8  */
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup USART_Clock  USART Clock
00249   * @{
00250   */
00251 #define USART_CLOCK_DISABLE                 ((uint32_t)0x00000000U)       /*!< USART clock disable */
00252 #define USART_CLOCK_ENABLE                  ((uint32_t)USART_CR2_CLKEN)   /*!< USART clock enable  */
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup USART_Clock_Polarity  USART Clock Polarity
00258   * @{
00259   */
00260 #define USART_POLARITY_LOW                  ((uint32_t)0x00000000U)      /*!< USART Clock signal is steady Low  */
00261 #define USART_POLARITY_HIGH                 ((uint32_t)USART_CR2_CPOL)   /*!< USART Clock signal is steady High */
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup USART_Clock_Phase   USART Clock Phase
00267   * @{
00268   */
00269 #define USART_PHASE_1EDGE                   ((uint32_t)0x00000000U)      /*!< USART frame phase on first clock transition  */
00270 #define USART_PHASE_2EDGE                   ((uint32_t)USART_CR2_CPHA)   /*!< USART frame phase on second clock transition */
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup USART_Last_Bit  USART Last Bit
00276   * @{
00277   */
00278 #define USART_LASTBIT_DISABLE               ((uint32_t)0x00000000U)      /*!< USART frame last data bit clock pulse not output to SCLK pin */
00279 #define USART_LASTBIT_ENABLE                ((uint32_t)USART_CR2_LBCL)   /*!< USART frame last data bit clock pulse output to SCLK pin     */
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup USART_Prescaler  USART Prescaler
00285   * @{
00286   */
00287 #define USART_PRESCALER_DIV1    ((uint32_t)0x00000000U)  /*!< USART clock /1   */
00288 #define USART_PRESCALER_DIV2    ((uint32_t)0x00000001U)  /*!< USART clock /2   */
00289 #define USART_PRESCALER_DIV4    ((uint32_t)0x00000002U)  /*!< USART clock /4   */
00290 #define USART_PRESCALER_DIV6    ((uint32_t)0x00000003U)  /*!< USART clock /6   */
00291 #define USART_PRESCALER_DIV8    ((uint32_t)0x00000004U)  /*!< USART clock /8   */
00292 #define USART_PRESCALER_DIV10   ((uint32_t)0x00000005U)  /*!< USART clock /10  */
00293 #define USART_PRESCALER_DIV12   ((uint32_t)0x00000006U)  /*!< USART clock /12  */
00294 #define USART_PRESCALER_DIV16   ((uint32_t)0x00000007U)  /*!< USART clock /16  */
00295 #define USART_PRESCALER_DIV32   ((uint32_t)0x00000008U)  /*!< USART clock /32  */
00296 #define USART_PRESCALER_DIV64   ((uint32_t)0x00000009U)  /*!< USART clock /64  */
00297 #define USART_PRESCALER_DIV128  ((uint32_t)0x0000000AU)  /*!< USART clock /128 */
00298 #define USART_PRESCALER_DIV256  ((uint32_t)0x0000000BU)  /*!< USART clock /256 */
00299
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup USART_Slave_Select_management USART Slave Select Management
00305   * @{
00306   */
00307 #define USART_NSS_HW    ((uint32_t)0x00000000U)       /*!< USART Hardware NSS management */
00308 #define USART_NSS_SW    ((uint32_t)USART_CR2_DIS_NSS) /*!< USART Software NSS management */
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup USART_Slave_Mode USART Synchronous Slave mode enable
00314   * @{
00315   */
00316 #define USART_SLAVEMODE_DISABLE   ((uint32_t)0x00000000U)     /*!< USART SPI Slave Mode Enable  */
00317 #define USART_SLAVEMODE_ENABLE    ((uint32_t)USART_CR2_SLVEN) /*!< USART SPI Slave Mode Disable */
00318 /**
00319   * @}
00320   */
00321
00322
00323  /** @defgroup USART_FIFO_mode USART FIFO mode
00324    * @brief    USART FIFO  mode
00325    * @{
00326    */
00327 #define USART_FIFOMODE_DISABLE        ((uint32_t)0x00000000U)       /*!< FIFO mode disable */
00328 #define USART_FIFOMODE_ENABLE         ((uint32_t)USART_CR1_FIFOEN)  /*!< FIFO mode enable  */
00329 /**
00330   * @}
00331   */
00332
00333 /** @defgroup USART_TXFIFO_threshold_level USART TXFIFO threshold level
00334   * @brief    USART TXFIFO level
00335   * @{
00336   */
00337 #define USART_TXFIFO_THRESHOLD_1_8    ((uint32_t)0x00000000U)                               /*!< TXFIFO reaches 1/8 of its depth */
00338 #define USART_TXFIFO_THRESHOLD_1_4    ((uint32_t)USART_CR3_TXFTCFG_0)                       /*!< TXFIFO reaches 1/4 of its depth */
00339 #define USART_TXFIFO_THRESHOLD_1_2    ((uint32_t)USART_CR3_TXFTCFG_1)                       /*!< TXFIFO reaches 1/2 of its depth */
00340 #define USART_TXFIFO_THRESHOLD_3_4    ((uint32_t)(USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)) /*!< TXFIFO reaches 3/4 of its depth */
00341 #define USART_TXFIFO_THRESHOLD_7_8    ((uint32_t)USART_CR3_TXFTCFG_2)                       /*!< TXFIFO reaches 7/8 of its depth */
00342 #define USART_TXFIFO_THRESHOLD_8_8    ((uint32_t)(USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)) /*!< TXFIFO becomes empty            */
00343 /**
00344   * @}
00345   */
00346
00347 /** @defgroup USART_RXFIFO_threshold_level USART RXFIFO threshold level
00348   * @brief    USART RXFIFO level
00349   * @{
00350   */
00351 #define USART_RXFIFO_THRESHOLD_1_8    ((uint32_t)0x00000000U)                               /*!< RXFIFO reaches 1/8 of its depth */
00352 #define USART_RXFIFO_THRESHOLD_1_4    ((uint32_t)USART_CR3_RXFTCFG_0)                       /*!< RXFIFO reaches 1/4 of its depth */
00353 #define USART_RXFIFO_THRESHOLD_1_2    ((uint32_t)USART_CR3_RXFTCFG_1)                       /*!< RXFIFO reaches 1/2 of its depth */
00354 #define USART_RXFIFO_THRESHOLD_3_4    ((uint32_t)(USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)) /*!< RXFIFO reaches 3/4 of its depth */
00355 #define USART_RXFIFO_THRESHOLD_7_8    ((uint32_t)USART_CR3_RXFTCFG_2)                       /*!< RXFIFO reaches 7/8 of its depth */
00356 #define USART_RXFIFO_THRESHOLD_8_8    ((uint32_t)(USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)) /*!< RXFIFO becomes full             */
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup USART_Request_Parameters  USART Request Parameters
00362   * @{
00363   */
00364 #define USART_RXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request  */
00365 #define USART_TXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup USART_Flags      USART Flags
00371   *        Elements values convention: 0xXXXX
00372   *           - 0xXXXX  : Flag mask in the ISR register
00373   * @{
00374   */
00375 #define USART_FLAG_TXFT                      USART_ISR_TXFT    /*!< USART TXFIFO threshold flag            */
00376 #define USART_FLAG_RXFT                      USART_ISR_RXFT    /*!< USART RXFIFO threshold flag            */
00377 #define USART_FLAG_RXFF                      USART_ISR_RXFF    /*!< USART RXFIFO Fullflag                  */
00378 #define USART_FLAG_TXFE                      USART_ISR_TXFE    /*!< USART TXFIFO Empty flag                */
00379 #define USART_FLAG_REACK                     USART_ISR_REACK   /*!< USART receive enable acknowledge flag  */
00380 #define USART_FLAG_TEACK                     USART_ISR_TEACK   /*!< USART transmit enable acknowledge flag */
00381 #define USART_FLAG_BUSY                      USART_ISR_BUSY    /*!< USART busy flag                        */
00382 #define USART_FLAG_UDR                       USART_ISR_UDR     /*!< USART SPI slave underrun error         */
00383 #define USART_FLAG_LBDF                      USART_ISR_LBDF    /*!< USART LIN break detection flag         */
00384 #define USART_FLAG_TXE                       USART_ISR_TXE     /*!< USART transmit data register empty     */
00385 #define USART_FLAG_TXFNF                     USART_ISR_TXE     /*!< USART TXFIFO not full                  */
00386 #define USART_FLAG_TC                        USART_ISR_TC      /*!< USART transmission complete            */
00387 #define USART_FLAG_RXNE                      USART_ISR_RXNE    /*!< USART read data register not empty     */
00388 #define USART_FLAG_RXFNE                     USART_ISR_RXNE    /*!< USART RXFIFO not empty                 */
00389 #define USART_FLAG_IDLE                      USART_ISR_IDLE    /*!< USART idle flag                        */
00390 #define USART_FLAG_ORE                       USART_ISR_ORE     /*!< USART overrun error                    */
00391 #define USART_FLAG_NE                        USART_ISR_NE      /*!< USART noise error                      */
00392 #define USART_FLAG_FE                        USART_ISR_FE      /*!< USART frame error                      */
00393 #define USART_FLAG_PE                        USART_ISR_PE      /*!< USART parity error                     */
00394 /**
00395   * @}
00396   */
00397
00398 /** @defgroup USART_Interrupt_definition USART Interrupts Definition
00399   *        Elements values convention: 0000ZZZZ0XXYYYYYb
00400   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00401   *           - XX  : Interrupt source register (2bits)
00402   *                 - 01: CR1 register
00403   *                 - 10: CR2 register
00404   *                 - 11: CR3 register
00405   *           - ZZZZ  : Flag position in the ISR register(5bits instead of 4bits)
00406   * @{
00407   */
00408
00409 #define USART_IT_PE                          ((uint16_t)0x0028U)
00410 #define USART_IT_TXE                         ((uint16_t)0x0727U)
00411 #define USART_IT_TC                          ((uint16_t)0x0626U)
00412 #define USART_IT_RXNE                        ((uint16_t)0x0525U)
00413 #define USART_IT_IDLE                        ((uint16_t)0x0424U)
00414 #define USART_IT_ERR                         ((uint16_t)0x0060U)
00415 #define USART_IT_RXFF                        ((uint16_t)0x183FU)
00416 #define USART_IT_TXFE                        ((uint16_t)0x173EU)
00417 #define USART_IT_RXFT                        ((uint16_t)0x1A7CU)
00418 #define USART_IT_TXFT                        ((uint16_t)0x1B77U)
00419
00420 #define USART_IT_UDR                         ((uint16_t)0x0D00U)
00421 #define USART_IT_ORE                         ((uint16_t)0x0300U)
00422 #define USART_IT_NE                          ((uint16_t)0x0200U)
00423 #define USART_IT_FE                          ((uint16_t)0x0100U)
00424 /**
00425   * @}
00426   */
00427
00428 /** @defgroup USART_IT_CLEAR_Flags    USART Interruption Clear Flags
00429   * @{
00430   */
00431 #define USART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag          */
00432 #define USART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag         */
00433 #define USART_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag        */
00434 #define USART_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag         */
00435 #define USART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag    */
00436 #define USART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
00437 #define USART_CLEAR_UDRCF                     USART_ICR_UDRCF           /*!< UnderRun Error Clear Flag        */
00438 #define USART_CLEAR_TXFECF                    USART_ICR_TXFECF          /*!< TXFIFO empty clear flag          */
00439 /**
00440   * @}
00441   */
00442
00443 /** @defgroup USART_Interruption_Mask    USART Interruption Flags Mask
00444   * @{
00445   */
00446 #define USART_IT_MASK                             ((uint16_t)0x001FU)     /*!< USART interruptions flags mask */
00447 /**
00448   * @}
00449   */
00450
00451 /**
00452   * @}
00453   */
00454
00455 /* Exported macros -----------------------------------------------------------*/
00456 /** @defgroup USART_Exported_Macros USART Exported Macros
00457   * @{
00458   */
00459
00460 /** @brief Reset USART handle state.
00461   * @param  __HANDLE__: USART handle.
00462   * @retval None
00463   */
00464 #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_USART_STATE_RESET)
00465
00466 /** @brief  Check whether the specified USART flag is set or not.
00467   * @param  __HANDLE__: specifies the USART Handle
00468   * @param  __FLAG__: specifies the flag to check.
00469   *        This parameter can be one of the following values:
00470   *            @arg USART_FLAG_TXFT: TXFIFO threshold flag
00471   *            @arg USART_FLAG_RXFT: RXFIFO threshold flag
00472   *            @arg USART_FLAG_RXFF:  RXFIFO Full flag
00473   *            @arg USART_FLAG_TXFE:  TXFIFO Empty flag
00474   *            @arg USART_FLAG_REACK: Receive enable ackowledge flag
00475   *            @arg USART_FLAG_TEACK: Transmit enable ackowledge flag
00476   *            @arg USART_FLAG_BUSY:  Busy flag
00477   *            @arg USART_FLAG_TXE:   Transmit data register empty flag
00478   *            @arg USART_FLAG_TC:    Transmission Complete flag
00479   *            @arg USART_FLAG_RXNE:  Receive data register not empty flag
00480   *            @arg USART_FLAG_IDLE:  Idle Line detection flag
00481   *            @arg USART_FLAG_ORE:   OverRun Error flag
00482   *            @arg USART_FLAG_UDR:   UnderRun Error flag
00483   *            @arg USART_FLAG_NE:    Noise Error flag
00484   *            @arg USART_FLAG_FE:    Framing Error flag
00485   *            @arg USART_FLAG_PE:    Parity Error flag
00486   * @retval The new state of __FLAG__ (TRUE or FALSE).
00487   */
00488 #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00489
00490 /** @brief  Clear the specified USART pending flag.
00491   * @param  __HANDLE__: specifies the USART Handle.
00492   * @param  __FLAG__: specifies the flag to check.
00493   *          This parameter can be any combination of the following values:
00494   *            @arg USART_FLAG_TXFT:  TXFIFO threshold flag
00495   *            @arg USART_FLAG_RXFT:  RXFIFO threshold flag
00496   *            @arg USART_FLAG_RXFF:  RXFIFO Full flag
00497   *            @arg USART_FLAG_TXFE:  TXFIFO Empty flag
00498   *            @arg USART_FLAG_REACK: Receive enable ackowledge flag
00499   *            @arg USART_FLAG_TEACK: Transmit enable ackowledge flag
00500   *            @arg USART_FLAG_WUF:   Wake up from stop mode flag
00501   *            @arg USART_FLAG_RWU:   Receiver wake up flag (is the USART in mute mode)
00502   *            @arg USART_FLAG_SBKF:  Send Break flag
00503   *            @arg USART_FLAG_CMF:   Character match flag
00504   *            @arg USART_FLAG_BUSY:  Busy flag
00505   *            @arg USART_FLAG_ABRF:  Auto Baud rate detection flag
00506   *            @arg USART_FLAG_ABRE:  Auto Baud rate detection error flag
00507   *            @arg USART_FLAG_RTOF:  Receiver timeout flag
00508   *            @arg USART_FLAG_LBD:   LIN Break detection flag
00509   *            @arg USART_FLAG_TXE:   Transmit data register empty flag
00510   *            @arg USART_FLAG_TC:    Transmission Complete flag
00511   *            @arg USART_FLAG_RXNE:  Receive data register not empty flag
00512   *            @arg USART_FLAG_IDLE:  Idle Line detection flag
00513   *            @arg USART_FLAG_ORE:   OverRun Error flag
00514   *            @arg USART_FLAG_NE:    Noise Error flag
00515   *            @arg USART_FLAG_FE:    Framing Error flag
00516   *            @arg USART_FLAG_PE:    Parity Error flag
00517   * @retval The new state of __FLAG__ (TRUE or FALSE).
00518   */
00519 #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00520
00521
00522 /** @brief  Enable the specified USART interrupt.
00523   * @param  __HANDLE__: specifies the USART Handle.
00524   * @param  __INTERRUPT__: specifies the USART interrupt source to enable.
00525   *          This parameter can be one of the following values:
00526   *            @arg USART_IT_RXFF: RXFIFO Full interrupt
00527   *            @arg USART_IT_TXFE: TXFIFO Empty interrupt
00528   *            @arg USART_IT_RXFT: RXFIFO threshold interrupt
00529   *            @arg USART_IT_TXFT: TXFIFO threshold interrupt
00530   *            @arg USART_IT_TXE : Transmit Data Register empty interrupt
00531   *            @arg USART_IT_TC  : Transmission complete interrupt
00532   *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
00533   *            @arg USART_IT_IDLE: Idle line detection interrupt
00534   *            @arg USART_IT_PE  : Parity Error interrupt
00535   *            @arg USART_IT_ERR : Error interrupt(Frame error, noise error, overrun error)
00536   * @retval None
00537   */
00538 #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00539                                                             ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00540                                                             ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
00541
00542 /** @brief  Disable the specified USART interrupt.
00543   * @param  __HANDLE__: specifies the USART Handle.
00544   * @param  __INTERRUPT__: specifies the USART interrupt source to disable.
00545   *          This parameter can be one of the following values:
00546   *            @arg USART_IT_RXFF: RXFIFO Full interrupt
00547   *            @arg USART_IT_TXFE: TXFIFO Empty interrupt
00548   *            @arg USART_IT_RXFT: RXFIFO threshold interrupt
00549   *            @arg USART_IT_TXFT: TXFIFO threshold interrupt
00550   *            @arg USART_IT_TXE : Transmit Data Register empty interrupt
00551   *            @arg USART_IT_TC  : Transmission complete interrupt
00552   *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
00553   *            @arg USART_IT_IDLE: Idle line detection interrupt
00554   *            @arg USART_IT_PE  : Parity Error interrupt
00555   *            @arg USART_IT_ERR : Error interrupt(Frame error, noise error, overrun error)
00556   * @retval None
00557   */
00558 #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00559                                                             ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00560                                                             ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
00561
00562
00563 /** @brief  Check whether the specified USART interrupt has occurred or not.
00564   * @param  __HANDLE__: specifies the USART Handle.
00565   * @param  __IT__: specifies the USART interrupt source to check.
00566   *          This parameter can be one of the following values:
00567   *            @arg USART_IT_RXFF: RXFIFO Full interrupt
00568   *            @arg USART_IT_TXFE: TXFIFO Empty interrupt
00569   *            @arg USART_IT_RXFT: RXFIFO threshold interrupt
00570   *            @arg USART_IT_TXFT: TXFIFO threshold interrupt
00571   *            @arg USART_IT_TXE : Transmit Data Register empty interrupt
00572   *            @arg USART_IT_TC  : Transmission complete interrupt
00573   *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
00574   *            @arg USART_IT_IDLE: Idle line detection interrupt
00575   *            @arg USART_IT_ORE : OverRun Error interrupt
00576   *            @arg USART_IT_UDR : UnderRun Error interrupt
00577   *            @arg USART_IT_NE  : Noise Error interrupt
00578   *            @arg USART_IT_FE  : Framing Error interrupt
00579   *            @arg USART_IT_PE  : Parity Error interrupt
00580   * @retval The new state of __IT__ (TRUE or FALSE).
00581   */
00582 #define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
00583
00584 /** @brief  Check whether the specified USART interrupt source is enabled or not.
00585   * @param  __HANDLE__: specifies the USART Handle.
00586   * @param  __IT__: specifies the USART interrupt source to check.
00587   *          This parameter can be one of the following values:
00588    *           @arg USART_IT_RXFF: RXFIFO Full interrupt
00589   *            @arg USART_IT_TXFE: TXFIFO Empty interrupt
00590   *            @arg USART_IT_RXFT: RXFIFO threshold interrupt
00591   *            @arg USART_IT_TXFT: TXFIFO threshold interrupt
00592   *            @arg USART_IT_TXE : Transmit Data Register empty interrupt
00593   *            @arg USART_IT_TC  : Transmission complete interrupt
00594   *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
00595   *            @arg USART_IT_IDLE: Idle line detection interrupt
00596   *            @arg USART_IT_ORE : OverRun Error interrupt
00597   *            @arg USART_IT_NE  : Noise Error interrupt
00598   *            @arg USART_IT_FE  : Framing Error interrupt
00599   *            @arg USART_IT_PE  : Parity Error interrupt
00600   * @retval The new state of __IT__ (TRUE or FALSE).
00601   */
00602 #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
00603                                                    (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \
00604                                                    (((uint16_t)(__IT__)) & USART_IT_MASK)))
00605
00606
00607 /** @brief  Clear the specified USART ISR flag, in setting the proper ICR register flag.
00608   * @param  __HANDLE__: specifies the USART Handle.
00609   * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
00610   *                       to clear the corresponding interrupt.
00611   *          This parameter can be one of the following values:
00612   *            @arg USART_CLEAR_PEF: Parity Error Clear Flag
00613   *            @arg USART_CLEAR_FEF: Framing Error Clear Flag
00614   *            @arg USART_CLEAR_NEF: Noise detected Clear Flag
00615   *            @arg USART_CLEAR_OREF: OverRun Error Clear Flag
00616   *            @arg USART_CLEAR_IDLEF: IDLE line detected Clear Flag
00617   *            @arg USART_CLEAR_TCF: Transmission Complete Clear Flag
00618   *            @arg USART_CLEAR_UDRCF: UnderRun Error Clear Flag
00619   *            @arg USART_CLEAR_TXFECF: TXFIFO empty Clear Flag
00620   * @retval None
00621   */
00622 #define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
00623
00624 /** @brief  Clear the USART PE pending flag.
00625   * @param  __HANDLE__: specifies the USART Handle.
00626   * @retval None
00627   */
00628 #define __HAL_USART_CLEAR_PEFLAG(__HANDLE__)   __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_PEF)
00629
00630 /** @brief  Clear the USART FE pending flag.
00631   * @param  __HANDLE__: specifies the USART Handle.
00632   * @retval None
00633   */
00634 #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__)   __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_FEF)
00635
00636 /** @brief  Clear the USART NE pending flag.
00637   * @param  __HANDLE__: specifies the USART Handle.
00638   * @retval None
00639   */
00640 #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__)  __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_NEF)
00641
00642 /** @brief  Clear the USART ORE pending flag.
00643   * @param  __HANDLE__: specifies the USART Handle.
00644   * @retval None
00645   */
00646 #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__)   __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_OREF)
00647
00648 /** @brief  Clear the USART IDLE pending flag.
00649   * @param  __HANDLE__: specifies the USART Handle.
00650   * @retval None
00651   */
00652 #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_IDLEF)
00653
00654 /** @brief  Clear the USART UDR pending flag.
00655   * @param  __HANDLE__: specifies the USART Handle.
00656   * @retval None
00657   */
00658 #define __HAL_USART_CLEAR_UDRFLAG(__HANDLE__)   __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_UDRCF)
00659
00660 /** @brief  Clear the USART TX FIFO empty clear flag.
00661   * @param  __HANDLE__: specifies the USART Handle.
00662   * @retval None
00663   */
00664 #define __HAL_USART_CLEAR_TXFECF(__HANDLE__)   __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_TXFECF)
00665
00666
00667
00668 /** @brief  Set a specific USART request flag.
00669   * @param  __HANDLE__: specifies the USART Handle.
00670   * @param  __REQ__: specifies the request flag to set.
00671   *          This parameter can be one of the following values:
00672   *            @arg USART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
00673   *            @arg USART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
00674   *
00675   * @retval None
00676   */
00677 #define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__)      ((__HANDLE__)->Instance->RQR |= (__REQ__))
00678
00679 /** @brief  Enable the USART one bit sample method.
00680   * @param  __HANDLE__: specifies the USART Handle.
00681   * @retval None
00682   */
00683 #define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00684
00685 /** @brief  Disable the USART one bit sample method.
00686   * @param  __HANDLE__: specifies the USART Handle.
00687   * @retval None
00688   */
00689 #define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
00690
00691 /** @brief  Enable USART.
00692   * @param  __HANDLE__: specifies the USART Handle.
00693   * @retval None
00694   */
00695 #define __HAL_USART_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00696
00697 /** @brief  Disable USART.
00698   * @param  __HANDLE__: specifies the USART Handle.
00699   * @retval None
00700   */
00701 #define __HAL_USART_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00702
00703 /**
00704   * @}
00705   */
00706
00707 /* Private variables -----------------------------------------------------*/
00708 /** @defgroup USART_Private_Variables   USART Private Variables
00709   * @{
00710   */
00711 static const uint16_t USARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256};
00712 /**
00713   * @}
00714   */
00715
00716 /* Private macros --------------------------------------------------------*/
00717 /** @defgroup USART_Private_Macros   USART Private Macros
00718   * @{
00719   */
00720
00721 /** @brief  Report the USART clock source.
00722   * @param  __HANDLE__: specifies the USART Handle.
00723   * @param  __CLOCKSOURCE__: output variable.
00724   * @retval the USART clocking source, written in __CLOCKSOURCE__.
00725   */
00726 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00727   do {                                                         \
00728     if((__HANDLE__)->Instance == USART1)                       \
00729     {                                                          \
00730        switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00731        {                                                       \
00732         case RCC_USART1CLKSOURCE_D2PCLK2:                      \
00733           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2;       \
00734           break;                                               \
00735         case RCC_USART1CLKSOURCE_PLL2:                        \
00736           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \
00737           break;                                               \
00738         case RCC_USART1CLKSOURCE_PLL3:                        \
00739           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \
00740           break;                                               \
00741         case RCC_USART1CLKSOURCE_HSI:                          \
00742           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00743           break;                                               \
00744         case RCC_USART1CLKSOURCE_CSI:                          \
00745           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \
00746           break;                                               \
00747         case RCC_USART1CLKSOURCE_LSE:                          \
00748           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00749           break;                                               \
00750        }                                                       \
00751     }                                                          \
00752     else if((__HANDLE__)->Instance == USART2)                  \
00753     {                                                          \
00754        switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00755        {                                                       \
00756         case RCC_USART2CLKSOURCE_D2PCLK1:                      \
00757           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1;       \
00758           break;                                               \
00759         case RCC_USART2CLKSOURCE_PLL2:                        \
00760            (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;         \
00761           break;                                               \
00762         case RCC_USART2CLKSOURCE_PLL3:                        \
00763           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \
00764           break;                                               \
00765         case RCC_USART2CLKSOURCE_HSI:                          \
00766           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00767           break;                                               \
00768         case RCC_USART2CLKSOURCE_CSI:                          \
00769           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \
00770           break;                                               \
00771         case RCC_USART2CLKSOURCE_LSE:                          \
00772           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00773           break;                                               \
00774        }                                                       \
00775     }                                                          \
00776     else if((__HANDLE__)->Instance == USART3)                  \
00777     {                                                          \
00778        switch(__HAL_RCC_GET_USART3_SOURCE())                   \
00779        {                                                       \
00780         case RCC_USART3CLKSOURCE_D2PCLK1:                      \
00781           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1;       \
00782           break;                                               \
00783         case RCC_USART3CLKSOURCE_PLL2:                        \
00784           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \
00785           break;                                               \
00786         case RCC_USART3CLKSOURCE_PLL3:                        \
00787           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \
00788           break;                                               \
00789         case RCC_USART3CLKSOURCE_HSI:                          \
00790           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00791           break;                                               \
00792         case RCC_USART3CLKSOURCE_CSI:                          \
00793           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \
00794           break;                                               \
00795         case RCC_USART3CLKSOURCE_LSE:                          \
00796           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00797           break;                                               \
00798        }                                                       \
00799     }                                                          \
00800     else if((__HANDLE__)->Instance == USART6)                  \
00801     {                                                          \
00802        switch(__HAL_RCC_GET_USART6_SOURCE())                   \
00803        {                                                       \
00804         case RCC_USART6CLKSOURCE_D2PCLK2:                      \
00805           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2;       \
00806           break;                                               \
00807         case RCC_USART6CLKSOURCE_PLL2:                        \
00808           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \
00809           break;                                               \
00810         case RCC_USART6CLKSOURCE_PLL3:                        \
00811           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \
00812           break;                                               \
00813         case RCC_USART6CLKSOURCE_HSI:                          \
00814           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00815           break;                                               \
00816         case RCC_USART6CLKSOURCE_CSI:                          \
00817           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \
00818           break;                                               \
00819         case RCC_USART6CLKSOURCE_LSE:                          \
00820           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00821           break;                                               \
00822        }                                                       \
00823     }                                                          \
00824   } while(0)
00825
00826 /** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
00827   * @param  __PCLK__: USART clock.
00828   * @param  __BAUD__: Baud rate set by the user.
00829   * @param  __PRESCALER__: UART prescaler value.
00830   * @retval Division result
00831   */
00832 #define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __PRESCALER__)   (((((__PCLK__)/USARTPrescTable[(__PRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__))
00833
00834 /** @brief  Check USART Baud rate.
00835   * @param  __BAUDRATE__: Baudrate specified by the user.
00836   *         The maximum Baud Rate is derived from the maximum clock on H7 (i.e. 100 MHz)
00837   *         divided by the smallest oversampling used on the USART (i.e. 8).
00838   * @retval Test result (TRUE or FALSE).
00839   */
00840 #define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
00841
00842 /**
00843   * @brief Ensure that USART frame number of stop bits is valid.
00844   * @param __STOPBITS__: USART frame number of stop bits.
00845   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
00846   */
00847 #define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
00848                                          ((__STOPBITS__) == USART_STOPBITS_1)   || \
00849                                          ((__STOPBITS__) == USART_STOPBITS_1_5) || \
00850                                          ((__STOPBITS__) == USART_STOPBITS_2))
00851
00852 /**
00853   * @brief Ensure that USART frame parity is valid.
00854   * @param __PARITY__: USART frame parity.
00855   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
00856   */
00857 #define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
00858                                      ((__PARITY__) == USART_PARITY_EVEN) || \
00859                                      ((__PARITY__) == USART_PARITY_ODD))
00860
00861 /**
00862   * @brief Ensure that USART communication mode is valid.
00863   * @param __MODE__: USART communication mode.
00864   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00865   */
00866 #define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3U) == 0x00U) && ((__MODE__) != (uint32_t)0x00U))
00867
00868 /**
00869   * @brief Ensure that USART oversampling is valid.
00870   * @param __SAMPLING__: USART oversampling.
00871   * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
00872   */
00873 #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
00874                                              ((__SAMPLING__) == USART_OVERSAMPLING_8))
00875
00876 /**
00877   * @brief Ensure that USART clock state is valid.
00878   * @param __CLOCK__: USART clock state.
00879   * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
00880   */
00881 #define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
00882                                    ((__CLOCK__) == USART_CLOCK_ENABLE))
00883
00884 /**
00885   * @brief Ensure that USART frame polarity is valid.
00886   * @param __CPOL__: USART frame polarity.
00887   * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
00888   */
00889 #define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
00890
00891 /**
00892   * @brief Ensure that USART frame phase is valid.
00893   * @param __CPHA__: USART frame phase.
00894   * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
00895   */
00896 #define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
00897
00898 /**
00899   * @brief Ensure that USART frame last bit clock pulse setting is valid.
00900   * @param __LASTBIT__: USART frame last bit clock pulse setting.
00901   * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
00902   */
00903 #define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
00904                                        ((__LASTBIT__) == USART_LASTBIT_ENABLE))
00905
00906 /**
00907   * @brief Ensure that USART request parameter is valid.
00908   * @param __PARAM__: USART request parameter.
00909   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
00910   */
00911 #define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
00912                                                ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
00913
00914 /**
00915   * @brief Ensure that USART Prescaler is valid.
00916   * @param __PRESCALER__: USART Prescaler value.
00917   * @retval SET (__PRESCALER__ is valid) or RESET (__PRESCALER__ is invalid)
00918   */
00919 #define IS_USART_PRESCALER(__PRESCALER__) (((__PRESCALER__) == USART_PRESCALER_DIV1) || \
00920                                            ((__PRESCALER__) == USART_PRESCALER_DIV2) || \
00921                                            ((__PRESCALER__) == USART_PRESCALER_DIV4) || \
00922                                            ((__PRESCALER__) == USART_PRESCALER_DIV6) || \
00923                                            ((__PRESCALER__) == USART_PRESCALER_DIV8) || \
00924                                            ((__PRESCALER__) == USART_PRESCALER_DIV10) || \
00925                                            ((__PRESCALER__) == USART_PRESCALER_DIV12) || \
00926                                            ((__PRESCALER__) == USART_PRESCALER_DIV16) || \
00927                                            ((__PRESCALER__) == USART_PRESCALER_DIV32) || \
00928                                            ((__PRESCALER__) == USART_PRESCALER_DIV64) || \
00929                                            ((__PRESCALER__) == USART_PRESCALER_DIV128) || \
00930                                            ((__PRESCALER__) == USART_PRESCALER_DIV256))
00931
00932 /**
00933   * @brief Ensure that USART NSS is valid.
00934   * @param __NSS__: USART Negative Slave Select pin management.
00935   * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid)
00936   */
00937 #define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HW) || ((__NSS__) == USART_NSS_SW))
00938
00939 /**
00940   * @brief Ensure that USART FIFO mode is valid.
00941   * @param __STATE__: USART FIFO mode.
00942   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00943   */
00944 #define IS_USART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == USART_FIFOMODE_DISABLE ) || \
00945                                              ((__STATE__) == USART_FIFOMODE_ENABLE))
00946
00947 /**
00948   * @brief Ensure that USART TXFIFO threshold level is valid.
00949   * @param __THRESHOLD__: USART TXFIFO threshold level.
00950   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00951   */
00952 #define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8) || \
00953                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4) || \
00954                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2) || \
00955                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4) || \
00956                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8) || \
00957                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8))
00958
00959 /**
00960   * @brief Ensure that USART RXFIFO threshold level is valid.
00961   * @param __THRESHOLD__: USART RXFIFO threshold level.
00962   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00963   */
00964 #define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8) || \
00965                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4) || \
00966                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2) || \
00967                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4) || \
00968                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8) || \
00969                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8))
00970
00971 /**
00972   * @brief Ensure that USART Slave Mode is valid.
00973   * @param __STATE__: USART Slave Mode.
00974   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00975   */
00976 #define IS_USART_SLAVEMODE(__STATE__)   (((__STATE__) == USART_SLAVEMODE_DISABLE ) || \
00977                                          ((__STATE__) == USART_SLAVEMODE_ENABLE))
00978
00979 /**
00980   * @}
00981   */
00982
00983 /* Include USART HAL Extended module */
00984 #include "stm32h7xx_hal_usart_ex.h"
00985
00986 /* Exported functions --------------------------------------------------------*/
00987 /** @addtogroup USART_Exported_Functions USART Exported Functions
00988   * @{
00989   */
00990
00991 /** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
00992   * @{
00993   */
00994
00995 /* Initialization and de-initialization functions  ****************************/
00996 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
00997 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
00998 void HAL_USART_MspInit(USART_HandleTypeDef *husart);
00999 void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
01000
01001 /**
01002   * @}
01003   */
01004
01005 /** @addtogroup USART_Exported_Functions_Group2 IO operation functions
01006   * @{
01007   */
01008
01009 /* IO operation functions *****************************************************/
01010 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
01011 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
01012 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
01013 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
01014 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
01015 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size);
01016 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
01017 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
01018 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
01019 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
01020 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
01021 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
01022 /* Transfer Abort functions */
01023 HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
01024 HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
01025
01026 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
01027 void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
01028 void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
01029 void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
01030 void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
01031 void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
01032 void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
01033 void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart);
01034
01035 /**
01036   * @}
01037   */
01038
01039 /* Peripheral Control functions ***********************************************/
01040
01041 /** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions
01042   * @{
01043   */
01044
01045 /* Peripheral State and Error functions ***************************************/
01046 HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
01047 uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
01048
01049 /**
01050   * @}
01051   */
01052
01053 /**
01054   * @}
01055   */
01056
01057 /**
01058   * @}
01059   */
01060
01061 /**
01062   * @}
01063   */
01064
01065 #ifdef __cplusplus
01066 }
01067 #endif
01068
01069 #endif /* __STM32H7xx_HAL_USART_H */
01070
01071 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_usart_ex.h Source File

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stm32h7xx_hal_usart_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_usart_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of USART HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_USART_EX_H
00040 #define __STM32H7xx_HAL_USART_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup USARTEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059 /** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
00060   * @{
00061   */
00062
00063 /** @defgroup USARTEx_Word_Length USARTEx Word Length
00064   * @{
00065   */
00066 #define USART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M1)   /*!< 7-bit long USART frame */
00067 #define USART_WORDLENGTH_8B                  ((uint32_t)0x00000000U)    /*!< 8-bit long USART frame */
00068 #define USART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M0)   /*!< 9-bit long USART frame */
00069 /**
00070   * @}
00071   */
00072
00073 /**
00074   * @}
00075   */
00076
00077 /* Exported functions --------------------------------------------------------*/
00078
00079 /* Private macros ------------------------------------------------------------*/
00080 /** @defgroup USARTEx_Private_Macros USARTEx Private Macros
00081   * @{
00082   */
00083
00084 /** @brief  Compute the USART mask to apply to retrieve the received data
00085   *         according to the word length and to the parity bits activation.
00086   * @note   If PCE = 1, the parity bit is not included in the data extracted
00087   *         by the reception API().
00088   *         This masking operation is not carried out in the case of
00089   *         DMA transfers.
00090   * @param  __HANDLE__: specifies the USART Handle.
00091   * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
00092   */
00093 #define USART_MASK_COMPUTATION(__HANDLE__)                            \
00094   do {                                                                \
00095   if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B)           \
00096   {                                                                   \
00097      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
00098      {                                                                \
00099         (__HANDLE__)->Mask = 0x01FF ;                                 \
00100      }                                                                \
00101      else                                                             \
00102      {                                                                \
00103         (__HANDLE__)->Mask = 0x00FF ;                                 \
00104      }                                                                \
00105   }                                                                   \
00106   else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B)      \
00107   {                                                                   \
00108      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
00109      {                                                                \
00110         (__HANDLE__)->Mask = 0x00FF ;                                 \
00111      }                                                                \
00112      else                                                             \
00113      {                                                                \
00114         (__HANDLE__)->Mask = 0x007F ;                                 \
00115      }                                                                \
00116   }                                                                   \
00117   else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B)      \
00118   {                                                                   \
00119      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
00120      {                                                                \
00121         (__HANDLE__)->Mask = 0x007F ;                                 \
00122      }                                                                \
00123      else                                                             \
00124      {                                                                \
00125         (__HANDLE__)->Mask = 0x003F ;                                 \
00126      }                                                                \
00127   }                                                                   \
00128 } while(0)
00129
00130 /**
00131   * @brief Ensure that USART frame length is valid.
00132   * @param __LENGTH__: USART frame length.
00133   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00134   */
00135 #define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
00136                                           ((__LENGTH__) == USART_WORDLENGTH_8B) || \
00137                                           ((__LENGTH__) == USART_WORDLENGTH_9B))
00138
00139 /**
00140   * @}
00141   */
00142
00143 /* Exported functions --------------------------------------------------------*/
00144
00145 /**
00146   * @}
00147   */
00148
00149 /**
00150   * @}
00151   */
00152
00153 #ifdef __cplusplus
00154 }
00155 #endif
00156
00157 #endif /* __STM32H7xx_HAL_USART_EX_H */
00158
00159 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_wwdg.c Source File

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stm32h7xx_hal_wwdg.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_wwdg.c
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   WWDG HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Window Watchdog (WWDG) peripheral:
00010   *           + Initialization and Configuration function
00011   *           + IO operation functions
00012   @verbatim
00013   ==============================================================================
00014                       ##### WWDG specific features #####
00015   ==============================================================================
00016   [..]
00017     Once enabled the WWDG generates a system reset on expiry of a programmed
00018     time period, unless the program refreshes the counter (T[6;0] downcounter)
00019     before reaching 0x3F value (i.e. a reset is generated when the counter
00020     value rolls over from 0x40 to 0x3F).
00021
00022     (+) An MCU reset is also generated if the counter value is refreshed
00023         before the counter has reached the refresh window value. This
00024         implies that the counter must be refreshed in a limited window.
00025
00026     (+) Once enabled the WWDG cannot be disabled except by a system reset.
00027
00028     (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has
00029         occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)).
00030
00031     (+) The WWDG downcounter input clock is derived from the APB clock divided
00032         by a programmable prescaler.
00033
00034     (+) WWDG downcounter clock (Hz) = PCLK1 / (4096 * Prescaler)
00035
00036     (+) WWDG timeout (ms) = (1000 * (T[5;0] + 1)) / (WWDG downcounter clock)
00037         where T[5;0] are the lowest 6 bits of downcounter.
00038
00039     (+) WWDG Counter refresh is allowed between the following limits :
00040         (++) min time (ms) = (1000 * (T[5;0] - Window)) / (WWDG downcounter clock)
00041         (++) max time (ms) = (1000 * (T[5;0] - 0x40)) / (WWDG downcounter clock)
00042
00043     (+) Min-max timeout value @80 MHz(PCLK1): ~51.2 us / ~26.22 ms
00044
00045     (+) The Early Wakeup Interrupt (EWI) can be used if specific safety
00046         operations or data logging must be performed before the actual reset is
00047         generated. When the downcounter reaches the value 0x40, an EWI interrupt
00048         is generated and the corresponding interrupt service routine (ISR) can
00049         be used to trigger specific actions (such as communications or data
00050         logging), before resetting the device.
00051         In some applications, the EWI interrupt can be used to manage a software
00052         system check and/or system recovery/graceful degradation, without
00053         generating a WWDG reset. In this case, the corresponding interrupt
00054         service routine (ISR) should reload the WWDG counter to avoid the WWDG
00055         reset, then trigger the required actions.
00056         Note:When the EWI interrupt cannot be served, e.g. due to a system lock
00057         in a higher priority task, the WWDG reset will eventually be generated.
00058
00059     (+) Debug mode : When the microcontroller enters debug mode (core halted),
00060         the WWDG counter either continues to work normally or stops, depending
00061         on DBG_WWDG_STOP configuration bit in DBG module, accessible through
00062         __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros
00063
00064                      ##### How to use this driver #####
00065   ==============================================================================
00066   [..]
00067     (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
00068
00069     (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup
00070         Interrupt mode using using HAL_WWDG_Init() function.
00071         This enables WWDG peripheral and the downcounter starts downcounting
00072         from given counter value.
00073         Init function can be called again to modify all watchdog parameters,
00074         however if EWI mode has been set once, it can't be clear until next
00075         reset.
00076
00077     (+) The application program must refresh the WWDG counter at regular
00078         intervals during normal operation to prevent an MCU reset using
00079         HAL_WWDG_Refresh() function. This operation must occur only when
00080         the counter is lower than the window value already programmed.
00081
00082     (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when
00083         the counter reaches 0x40. User can add his own code in weak function
00084         HAL_WWDG_EarlyWakeupCallback().
00085
00086      *** WWDG HAL driver macros list ***
00087      ==================================
00088      [..]
00089        Below the list of most used macros in WWDG HAL driver.
00090
00091       (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
00092       (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
00093       (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
00094
00095   @endverbatim
00096   ******************************************************************************
00097   * @attention
00098   *
00099   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00100   *
00101   * Redistribution and use in source and binary forms, with or without modification,
00102   * are permitted provided that the following conditions are met:
00103   *   1. Redistributions of source code must retain the above copyright notice,
00104   *      this list of conditions and the following disclaimer.
00105   *   2. Redistributions in binary form must reproduce the above copyright notice,
00106   *      this list of conditions and the following disclaimer in the documentation
00107   *      and/or other materials provided with the distribution.
00108   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00109   *      may be used to endorse or promote products derived from this software
00110   *      without specific prior written permission.
00111   *
00112   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00113   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00114   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00115   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00116   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00117   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00118   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00119   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00120   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00121   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00122   *
00123   ******************************************************************************
00124   */
00125
00126 /* Includes ------------------------------------------------------------------*/
00127 #include "stm32h7xx_hal.h"
00128
00129 /** @addtogroup STM32H7xx_HAL_Driver
00130   * @{
00131   */
00132
00133 #ifdef HAL_WWDG_MODULE_ENABLED
00134 /** @defgroup WWDG WWDG
00135   * @brief WWDG HAL module driver.
00136   * @{
00137   */
00138
00139 /* Private typedef -----------------------------------------------------------*/
00140 /* Private define ------------------------------------------------------------*/
00141 /* Private macro -------------------------------------------------------------*/
00142 /* Private variables ---------------------------------------------------------*/
00143 /* Private function prototypes -----------------------------------------------*/
00144 /* Exported functions --------------------------------------------------------*/
00145
00146 /** @defgroup WWDG_Exported_Functions WWDG Exported Functions
00147   * @{
00148   */
00149
00150 /** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
00151  *  @brief    Initialization and Configuration functions.
00152  *
00153 @verbatim
00154   ==============================================================================
00155           ##### Initialization and Configuration functions #####
00156   ==============================================================================
00157   [..]
00158     This section provides functions allowing to:
00159       (+) Initialize and start the WWDG according to the specified parameters
00160           in the WWDG_InitTypeDef of associated handle.
00161       (+) Initialize the WWDG MSP.
00162
00163 @endverbatim
00164   * @{
00165   */
00166
00167 /**
00168   * @brief  Initialize the WWDG according to the specified.
00169   *         parameters in the WWDG_InitTypeDef of  associated handle.
00170   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00171   *                the configuration information for the specified WWDG module.
00172   * @retval HAL status
00173   */
00174 HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
00175 {
00176   /* Check the WWDG handle allocation */
00177   if(hwwdg == NULL)
00178   {
00179     return HAL_ERROR;
00180   }
00181
00182   /* Check the parameters */
00183   assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
00184   assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
00185   assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
00186   assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
00187   assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
00188
00189   /* Init the low level hardware */
00190   HAL_WWDG_MspInit(hwwdg);
00191
00192   /* Set WWDG Counter */
00193   WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
00194
00195   /* Set WWDG Prescaler and Window */
00196   WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
00197
00198   /* Return function status */
00199   return HAL_OK;
00200 }
00201
00202
00203 /**
00204   * @brief  Initialize the WWDG MSP.
00205   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00206   *                the configuration information for the specified WWDG module.
00207   * @note   When rewriting this function in user file, mechanism may be added
00208   *         to avoid multiple initialize when HAL_WWDG_Init function is called
00209   *         again to change parameters.
00210   * @retval None
00211   */
00212 __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
00213 {
00214   /* Prevent unused argument(s) compilation warning */
00215   UNUSED(hwwdg);
00216
00217   /* NOTE: This function should not be modified, when the callback is needed,
00218            the HAL_WWDG_MspInit could be implemented in the user file
00219    */
00220 }
00221
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
00227  *  @brief    IO operation functions
00228  *
00229 @verbatim
00230   ==============================================================================
00231                       ##### IO operation functions #####
00232   ==============================================================================
00233   [..]
00234     This section provides functions allowing to:
00235     (+) Refresh the WWDG.
00236     (+) Handle WWDG interrupt request and associated function callback.
00237
00238 @endverbatim
00239   * @{
00240   */
00241
00242 /**
00243   * @brief  Refresh the WWDG.
00244   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00245   *                the configuration information for the specified WWDG module.
00246   * @retval HAL status
00247   */
00248 HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
00249 {
00250   /* Write to WWDG CR the WWDG Counter value to refresh with */
00251   WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
00252
00253   /* Return function status */
00254   return HAL_OK;
00255 }
00256
00257 /**
00258   * @brief  Handle WWDG interrupt request.
00259   * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations
00260   *         or data logging must be performed before the actual reset is generated.
00261   *         The EWI interrupt is enabled by calling HAL_WWDG_Init function with
00262   *         EWIMode set to WWDG_EWI_ENABLE.
00263   *         When the downcounter reaches the value 0x40, and EWI interrupt is
00264   *         generated and the corresponding Interrupt Service Routine (ISR) can
00265   *         be used to trigger specific actions (such as communications or data
00266   *         logging), before resetting the device.
00267   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00268   *                the configuration information for the specified WWDG module.
00269   * @retval None
00270   */
00271 void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
00272 {
00273   /* Check if Early Wakeup Interrupt is enable */
00274   if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
00275   {
00276     /* Check if WWDG Early Wakeup Interrupt occurred */
00277     if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
00278     {
00279       /* Clear the WWDG Early Wakeup flag */
00280       __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
00281
00282       /* Early Wakeup callback */
00283       HAL_WWDG_EarlyWakeupCallback(hwwdg);
00284     }
00285   }
00286 }
00287
00288
00289 /**
00290   * @brief  WWDG Early Wakeup callback.
00291   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00292   *                the configuration information for the specified WWDG module.
00293   * @retval None
00294   */
00295 __weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
00296 {
00297   /* Prevent unused argument(s) compilation warning */
00298   UNUSED(hwwdg);
00299
00300   /* NOTE: This function should not be modified, when the callback is needed,
00301            the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
00302    */
00303 }
00304
00305 /**
00306   * @}
00307   */
00308
00309 /**
00310   * @}
00311   */
00312
00313 #endif /* HAL_WWDG_MODULE_ENABLED */
00314 /**
00315   * @}
00316   */
00317
00318 /**
00319   * @}
00320   */
00321
00322 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Apr 28 2017 15:42:40 for STM32H753xx HAL User Manual by doxygen 1.7.6.1


STM32H753xx HAL User Manual: stm32h7xx_hal_wwdg.h Source File

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stm32h7xx_hal_wwdg.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_hal_wwdg.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    21-April-2017
00007   * @brief   Header file of WWDG HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32H7xx_HAL_WWDG_H
00040 #define __STM32H7xx_HAL_WWDG_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32h7xx_hal_def.h"
00048
00049 /** @addtogroup STM32H7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup WWDG
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup WWDG_Exported_Types WWDG Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  WWDG Init structure definition
00065   */
00066 typedef struct
00067 {
00068   uint32_t Prescaler;     /*!< Specifies the prescaler value of the WWDG.
00069                                This parameter can be a value of @ref WWDG_Prescaler */
00070
00071   uint32_t Window;        /*!< Specifies the WWDG window value to be compared to the downcounter.
00072                                This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
00073
00074   uint32_t Counter;       /*!< Specifies the WWDG free-running downcounter  value.
00075                                This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
00076
00077   uint32_t EWIMode ;      /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
00078                                This parameter can be a value of @ref WWDG_EWI_Mode */
00079
00080 }WWDG_InitTypeDef;
00081
00082 /**
00083   * @brief  WWDG handle Structure definition
00084   */
00085 typedef struct
00086 {
00087   WWDG_TypeDef                 *Instance;  /*!< Register base address    */
00088
00089   WWDG_InitTypeDef             Init;       /*!< WWDG required parameters */
00090
00091 }WWDG_HandleTypeDef;
00092 /**
00093   * @}
00094   */
00095
00096 /* Exported constants --------------------------------------------------------*/
00097
00098 /** @defgroup WWDG_Exported_Constants WWDG Exported Constants
00099   * @{
00100   */
00101
00102 /** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
00103   * @{
00104   */
00105 #define WWDG_IT_EWI                         WWDG_CFR_EWI  /*!< Early wakeup interrupt */
00106 /**
00107   * @}
00108   */
00109
00110 /** @defgroup WWDG_Flag_definition WWDG Flag definition
00111   * @brief WWDG Flag definition
00112   * @{
00113   */
00114 #define WWDG_FLAG_EWIF                      WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
00115 /**
00116   * @}
00117   */
00118
00119 /** @defgroup WWDG_Prescaler WWDG Prescaler
00120   * @{
00121   */
00122 #define WWDG_PRESCALER_1                    ((uint32_t)(0x00000000U))                                     /*!< WWDG counter clock = (PCLK1/4096)/1   */
00123 #define WWDG_PRESCALER_2                    ((uint32_t)(WWDG_CFR_WDGTB0))                                 /*!< WWDG counter clock = (PCLK1/4096)/2   */
00124 #define WWDG_PRESCALER_4                    ((uint32_t)(WWDG_CFR_WDGTB1))                                 /*!< WWDG counter clock = (PCLK1/4096)/4   */
00125 #define WWDG_PRESCALER_8                    ((uint32_t)(WWDG_CFR_WDGTB1|WWDG_CFR_WDGTB0))                 /*!< WWDG counter clock = (PCLK1/4096)/8   */
00126 #define WWDG_PRESCALER_16                   ((uint32_t)(WWDG_CFR_WDGTB2))                                 /*!< WWDG counter clock = (PCLK1/4096)/16  */
00127 #define WWDG_PRESCALER_32                   ((uint32_t)(WWDG_CFR_WDGTB2|WWDG_CFR_WDGTB0))                 /*!< WWDG counter clock = (PCLK1/4096)/32  */
00128 #define WWDG_PRESCALER_64                   ((uint32_t)(WWDG_CFR_WDGTB2|WWDG_CFR_WDGTB1))                 /*!< WWDG counter clock = (PCLK1/4096)/64  */
00129 #define WWDG_PRESCALER_128                  ((uint32_t)(WWDG_CFR_WDGTB2|WWDG_CFR_WDGTB1|WWDG_CFR_WDGTB0)) /*!< WWDG counter clock = (PCLK1/4096)/128 */
00130
00131 /**
00132   * @}
00133   */
00134
00135 /** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
00136   * @{
00137   */
00138 #define WWDG_EWI_DISABLE                    0x00000000u       /*!< EWI Disable */
00139 #define WWDG_EWI_ENABLE                     WWDG_CFR_EWI      /*!< EWI Enable */
00140 /**
00141   * @}
00142   */
00143
00144 /**
00145   * @}
00146   */
00147
00148 /* Private macros ------------------------------------------------------------*/
00149
00150 /** @defgroup WWDG_Private_Macros WWDG Private Macros
00151   * @{
00152   */
00153 #define IS_WWDG_PRESCALER(__PRESCALER__)    (((__PRESCALER__) == WWDG_PRESCALER_1)  || \
00154                                              ((__PRESCALER__) == WWDG_PRESCALER_2)  || \
00155                                              ((__PRESCALER__) == WWDG_PRESCALER_4)  || \
00156                                              ((__PRESCALER__) == WWDG_PRESCALER_8)  || \
00157                                              ((__PRESCALER__) == WWDG_PRESCALER_16) || \
00158                                              ((__PRESCALER__) == WWDG_PRESCALER_32) || \
00159                                              ((__PRESCALER__) == WWDG_PRESCALER_64) || \
00160                                              ((__PRESCALER__) == WWDG_PRESCALER_128))
00161
00162 #define IS_WWDG_WINDOW(__WINDOW__)          (((__WINDOW__) >= WWDG_CFR_W6) && ((__WINDOW__) <= WWDG_CFR_W))
00163
00164 #define IS_WWDG_COUNTER(__COUNTER__)        (((__COUNTER__) >= WWDG_CR_T6) && ((__COUNTER__) <= WWDG_CR_T))
00165
00166 #define IS_WWDG_EWI_MODE(__MODE__)          (((__MODE__) == WWDG_EWI_ENABLE) || \
00167                                              ((__MODE__) == WWDG_EWI_DISABLE))
00168 /**
00169   * @}
00170   */
00171
00172
00173 /* Exported macros ------------------------------------------------------------*/
00174
00175 /** @defgroup WWDG_Exported_Macros WWDG Exported Macros
00176   * @{
00177   */
00178
00179 /**
00180   * @brief  Enable the WWDG peripheral.
00181   * @param  __HANDLE__  WWDG handle
00182   * @retval None
00183   */
00184 #define __HAL_WWDG_ENABLE(__HANDLE__)                         SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
00185
00186 /**
00187   * @brief  Enable the WWDG early wakeup interrupt.
00188   * @param  __HANDLE__: WWDG handle
00189   * @param  __INTERRUPT__  specifies the interrupt to enable.
00190   *         This parameter can be one of the following values:
00191   *            @arg WWDG_IT_EWI: Early wakeup interrupt
00192   * @note   Once enabled this interrupt cannot be disabled except by a system reset.
00193   * @retval None
00194   */
00195 #define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__)       SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
00196
00197 /**
00198   * @brief  Check whether the selected WWDG interrupt has occurred or not.
00199   * @param  __HANDLE__  WWDG handle
00200   * @param  __INTERRUPT__  specifies the it to check.
00201   *        This parameter can be one of the following values:
00202   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
00203   * @retval The new state of WWDG_FLAG (SET or RESET).
00204   */
00205 #define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)        __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
00206
00207 /** @brief  Clear the WWDG interrupt pending bits.
00208   *         bits to clear the selected interrupt pending bits.
00209   * @param  __HANDLE__  WWDG handle
00210   * @param  __INTERRUPT__  specifies the interrupt pending bit to clear.
00211   *         This parameter can be one of the following values:
00212   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00213   */
00214 #define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)      __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
00215
00216 /**
00217   * @brief  Check whether the specified WWDG flag is set or not.
00218   * @param  __HANDLE__  WWDG handle
00219   * @param  __FLAG__  specifies the flag to check.
00220   *         This parameter can be one of the following values:
00221   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00222   * @retval The new state of WWDG_FLAG (SET or RESET).
00223   */
00224 #define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__)           (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00225
00226 /**
00227   * @brief  Clear the WWDG's pending flags.
00228   * @param  __HANDLE__  WWDG handle
00229   * @param  __FLAG__  specifies the flag to clear.
00230   *         This parameter can be one of the following values:
00231   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00232   * @retval None
00233   */
00234 #define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->SR = ~(uint32_t)(__FLAG__))
00235
00236 /** @brief  Check whether the specified WWDG interrupt source is enabled or not.
00237   * @param  __HANDLE__  WWDG Handle.
00238   * @param  __INTERRUPT__  specifies the WWDG interrupt source to check.
00239   *         This parameter can be one of the following values:
00240   *            @arg WWDG_IT_EWI: Early Wakeup Interrupt
00241   * @retval state of __INTERRUPT__ (TRUE or FALSE).
00242   */
00243 #define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
00244
00245 /**
00246   * @}
00247   */
00248
00249 /* Exported functions --------------------------------------------------------*/
00250
00251 /** @addtogroup WWDG_Exported_Functions
00252   * @{
00253   */
00254
00255 /** @addtogroup WWDG_Exported_Functions_Group1
00256   * @{
00257   */
00258 /* Initialization/de-initialization functions  **********************************/
00259 HAL_StatusTypeDef     HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
00260 void                  HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
00261 /**
00262   * @}
00263   */
00264
00265 /** @addtogroup WWDG_Exported_Functions_Group2
00266   * @{
00267   */
00268 /* I/O operation functions ******************************************************/
00269 HAL_StatusTypeDef     HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
00270 void                  HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
00271 void                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);
00272 /**
00273   * @}
00274   */
00275
00276 /**
00277   * @}
00278   */
00279
00280 /**
00281   * @}
00282   */
00283
00284 /**
00285   * @}
00286   */
00287
00288 #ifdef __cplusplus
00289 }
00290 #endif
00291
00292 #endif /* __STM32H7xx_HAL_WWDG_H */
00293
00294 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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Generated on Fri Apr 28 2017 15:42:43 for STM32H753xx HAL User Manual by doxygen 1.7.6.1